2006.181.07:08:54.00;Log Opened: Mark IV Field System Version 9.7.7 2006.181.07:08:54.00;location,TSUKUB32,-140.09,36.10,61.0 2006.181.07:08:54.00;horizon1,0.,5.,360. 2006.181.07:08:54.00;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.181.07:08:54.00;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.181.07:08:54.00;drivev11,330,270,no 2006.181.07:08:54.00;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.181.07:08:54.00;drivev13,15.000,268,10.000,10.000,10.000 2006.181.07:08:54.00;drivev21,330,270,no 2006.181.07:08:54.00;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.181.07:08:54.00;drivev23,15.000,268,10.000,10.000,10.000 2006.181.07:08:54.00;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.181.07:08:54.00;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.181.07:08:54.00;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.181.07:08:54.00;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.181.07:08:54.00;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.181.07:08:54.00;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.181.07:08:54.00;time,-0.364,101.533,rate 2006.181.07:08:54.00;flagr,200 2006.181.07:08:54.00:" K06182 2006 TSUKUB32 T Ts 2006.181.07:08:54.00:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.181.07:08:54.00:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.181.07:08:54.00:" 108 TSUKUB32 14 17400 2006.181.07:08:54.00:" drudg version 050216 compiled under FS 9.7.07 2006.181.07:08:54.00:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.181.07:08:54.00:exper_initi 2006.181.07:08:54.00&exper_initi/proc_library 2006.181.07:08:54.00&exper_initi/sched_initi 2006.181.07:08:54.00:!2006.182.06:29:50 2006.181.07:08:54.00&proc_library/" k06182 tsukub32 ts 2006.181.07:08:54.00&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.181.07:08:54.00&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.181.07:08:54.00&sched_initi/startcheck 2006.181.07:08:54.00&startcheck/sy=check_fsrun.pl & 2006.181.07:08:54.00&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.181.07:09:38.30;cable 2006.181.07:09:38.40/cable/+6.4404E-03 2006.181.07:11:25.40;cablelong 2006.181.07:11:25.49/cablelong/+7.0001E-03 2006.181.07:11:39.11;cablediff 2006.181.07:11:39.11/cablediff/559.7e-6,+ 2006.181.07:11:55.83;cable 2006.181.07:11:55.97/cable/+6.4419E-03 2006.181.07:13:33.81;wx 2006.181.07:13:33.81/wx/29.35,1005.2,75 2006.181.07:13:57.39;"Sky is cloudy. 2006.181.07:14:53.09;xfe 2006.181.07:14:53.17/xfe/off,on,14.7 2006.181.07:15:05.66;clockoff\ 2006.181.07:15:05.66?ERROR sp -4 Unrecognized name (not a function or procedure). 2006.181.07:15:09.29;clockoff 2006.181.07:15:09.29&clockoff/"gps-fmout=1p 2006.181.07:15:09.29&clockoff/fmout-gps=1p 2006.181.07:15:10.07/fmout-gps/S +3.46E-07 2006.182.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.182.06:29:50.02:!2006.182.07:19:50 2006.182.07:19:50.00:unstow 2006.182.07:19:50.00&unstow/antenna=e 2006.182.07:19:50.00&unstow/!+10s 2006.182.07:19:50.00&unstow/antenna=m2 2006.182.07:20:02.02:scan_name=182-0730,k06182,60 2006.182.07:20:02.02:source=3c371,180650.68,694928.1,2000.0,ccw 2006.182.07:20:03.15#antcn#PM 1 00019 2005 228 00 22 31 00 2006.182.07:20:03.15#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.182.07:20:03.15#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.182.07:20:03.15#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.182.07:20:03.15#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.182.07:20:03.15#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.182.07:20:04.15:ready_k5 2006.182.07:20:04.15&ready_k5/obsinfo=st 2006.182.07:20:04.15&ready_k5/autoobs=1 2006.182.07:20:04.15&ready_k5/autoobs=2 2006.182.07:20:04.15&ready_k5/autoobs=3 2006.182.07:20:04.15&ready_k5/autoobs=4 2006.182.07:20:04.15&ready_k5/obsinfo 2006.182.07:20:04.15#flagr#flagr/antenna,new-source 2006.182.07:20:04.15/obsinfo=st/error_log.tmp was not found (or not removed). 2006.182.07:20:07.33/autoobs//k5ts1/ autoobs started! 2006.182.07:20:10.43/autoobs//k5ts2/ autoobs started! 2006.182.07:20:13.55/autoobs//k5ts3/ autoobs started! 2006.182.07:20:16.67/autoobs//k5ts4/ autoobs started! 2006.182.07:20:16.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:20:16.70:4f8m12a=1 2006.182.07:20:16.70&4f8m12a/xlog=on 2006.182.07:20:16.70&4f8m12a/echo=on 2006.182.07:20:16.70&4f8m12a/pcalon 2006.182.07:20:16.70&4f8m12a/"tpicd=stop 2006.182.07:20:16.70&4f8m12a/vc4f8 2006.182.07:20:16.70&4f8m12a/ifd4f 2006.182.07:20:16.70&4f8m12a/"form=m,16.000,1:2 2006.182.07:20:16.70&4f8m12a/"tpicd 2006.182.07:20:16.70&4f8m12a/echo=off 2006.182.07:20:16.70&4f8m12a/xlog=off 2006.182.07:20:16.70$4f8m12a/echo=on 2006.182.07:20:16.70$4f8m12a/pcalon 2006.182.07:20:16.70&pcalon/"no phase cal control is implemented here 2006.182.07:20:16.70$pcalon/"no phase cal control is implemented here 2006.182.07:20:16.70$4f8m12a/"tpicd=stop 2006.182.07:20:16.70$4f8m12a/vc4f8 2006.182.07:20:16.70&vc4f8/valo=1,532.99 2006.182.07:20:16.70&vc4f8/va=1,8 2006.182.07:20:16.70&vc4f8/valo=2,572.99 2006.182.07:20:16.70&vc4f8/va=2,7 2006.182.07:20:16.70&vc4f8/valo=3,672.99 2006.182.07:20:16.70&vc4f8/va=3,6 2006.182.07:20:16.70&vc4f8/valo=4,832.99 2006.182.07:20:16.70&vc4f8/va=4,7 2006.182.07:20:16.70&vc4f8/valo=5,652.99 2006.182.07:20:16.70&vc4f8/va=5,7 2006.182.07:20:16.70&vc4f8/valo=6,772.99 2006.182.07:20:16.70&vc4f8/va=6,6 2006.182.07:20:16.70&vc4f8/valo=7,832.99 2006.182.07:20:16.70&vc4f8/va=7,6 2006.182.07:20:16.70&vc4f8/valo=8,852.99 2006.182.07:20:16.70&vc4f8/va=8,7 2006.182.07:20:16.70&vc4f8/vblo=1,632.99 2006.182.07:20:16.70&vc4f8/vb=1,4 2006.182.07:20:16.70&vc4f8/vblo=2,640.99 2006.182.07:20:16.70&vc4f8/vb=2,4 2006.182.07:20:16.70&vc4f8/vblo=3,656.99 2006.182.07:20:16.70&vc4f8/vb=3,4 2006.182.07:20:16.70&vc4f8/vblo=4,712.99 2006.182.07:20:16.70&vc4f8/vb=4,4 2006.182.07:20:16.70&vc4f8/vblo=5,744.99 2006.182.07:20:16.70&vc4f8/vb=5,4 2006.182.07:20:16.70&vc4f8/vblo=6,752.99 2006.182.07:20:16.70&vc4f8/vb=6,4 2006.182.07:20:16.70&vc4f8/vabw=wide 2006.182.07:20:16.70&vc4f8/vbbw=wide 2006.182.07:20:16.70$vc4f8/valo=1,532.99 2006.182.07:20:16.70#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.07:20:16.70#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.07:20:16.70#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:16.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:16.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:16.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:16.70#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:20:16.70#ibcon#first serial, iclass 38, count 0 2006.182.07:20:16.70#ibcon#enter sib2, iclass 38, count 0 2006.182.07:20:16.70#ibcon#flushed, iclass 38, count 0 2006.182.07:20:16.70#ibcon#about to write, iclass 38, count 0 2006.182.07:20:16.70#ibcon#wrote, iclass 38, count 0 2006.182.07:20:16.70#ibcon#about to read 3, iclass 38, count 0 2006.182.07:20:16.74#ibcon#read 3, iclass 38, count 0 2006.182.07:20:16.74#ibcon#about to read 4, iclass 38, count 0 2006.182.07:20:16.74#ibcon#read 4, iclass 38, count 0 2006.182.07:20:16.74#ibcon#about to read 5, iclass 38, count 0 2006.182.07:20:16.74#ibcon#read 5, iclass 38, count 0 2006.182.07:20:16.74#ibcon#about to read 6, iclass 38, count 0 2006.182.07:20:16.74#ibcon#read 6, iclass 38, count 0 2006.182.07:20:16.74#ibcon#end of sib2, iclass 38, count 0 2006.182.07:20:16.74#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:20:16.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:20:16.74#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:20:16.74#ibcon#*before write, iclass 38, count 0 2006.182.07:20:16.74#ibcon#enter sib2, iclass 38, count 0 2006.182.07:20:16.74#ibcon#flushed, iclass 38, count 0 2006.182.07:20:16.74#ibcon#about to write, iclass 38, count 0 2006.182.07:20:16.74#ibcon#wrote, iclass 38, count 0 2006.182.07:20:16.74#ibcon#about to read 3, iclass 38, count 0 2006.182.07:20:16.80#ibcon#read 3, iclass 38, count 0 2006.182.07:20:16.80#ibcon#about to read 4, iclass 38, count 0 2006.182.07:20:16.80#ibcon#read 4, iclass 38, count 0 2006.182.07:20:16.80#ibcon#about to read 5, iclass 38, count 0 2006.182.07:20:16.80#ibcon#read 5, iclass 38, count 0 2006.182.07:20:16.80#ibcon#about to read 6, iclass 38, count 0 2006.182.07:20:16.80#ibcon#read 6, iclass 38, count 0 2006.182.07:20:16.80#ibcon#end of sib2, iclass 38, count 0 2006.182.07:20:16.80#ibcon#*after write, iclass 38, count 0 2006.182.07:20:16.80#ibcon#*before return 0, iclass 38, count 0 2006.182.07:20:16.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:16.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:16.80#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:20:16.80#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:20:16.80$vc4f8/va=1,8 2006.182.07:20:16.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.07:20:16.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.07:20:16.81#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:16.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:16.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:16.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:16.81#ibcon#enter wrdev, iclass 40, count 2 2006.182.07:20:16.81#ibcon#first serial, iclass 40, count 2 2006.182.07:20:16.81#ibcon#enter sib2, iclass 40, count 2 2006.182.07:20:16.81#ibcon#flushed, iclass 40, count 2 2006.182.07:20:16.81#ibcon#about to write, iclass 40, count 2 2006.182.07:20:16.81#ibcon#wrote, iclass 40, count 2 2006.182.07:20:16.81#ibcon#about to read 3, iclass 40, count 2 2006.182.07:20:16.83#ibcon#read 3, iclass 40, count 2 2006.182.07:20:16.83#ibcon#about to read 4, iclass 40, count 2 2006.182.07:20:16.83#ibcon#read 4, iclass 40, count 2 2006.182.07:20:16.83#ibcon#about to read 5, iclass 40, count 2 2006.182.07:20:16.83#ibcon#read 5, iclass 40, count 2 2006.182.07:20:16.83#ibcon#about to read 6, iclass 40, count 2 2006.182.07:20:16.83#ibcon#read 6, iclass 40, count 2 2006.182.07:20:16.83#ibcon#end of sib2, iclass 40, count 2 2006.182.07:20:16.83#ibcon#*mode == 0, iclass 40, count 2 2006.182.07:20:16.83#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.07:20:16.83#ibcon#[25=AT01-08\r\n] 2006.182.07:20:16.83#ibcon#*before write, iclass 40, count 2 2006.182.07:20:16.83#ibcon#enter sib2, iclass 40, count 2 2006.182.07:20:16.83#ibcon#flushed, iclass 40, count 2 2006.182.07:20:16.83#ibcon#about to write, iclass 40, count 2 2006.182.07:20:16.83#ibcon#wrote, iclass 40, count 2 2006.182.07:20:16.83#ibcon#about to read 3, iclass 40, count 2 2006.182.07:20:16.86#ibcon#read 3, iclass 40, count 2 2006.182.07:20:16.86#ibcon#about to read 4, iclass 40, count 2 2006.182.07:20:16.86#ibcon#read 4, iclass 40, count 2 2006.182.07:20:16.86#ibcon#about to read 5, iclass 40, count 2 2006.182.07:20:16.86#ibcon#read 5, iclass 40, count 2 2006.182.07:20:16.86#ibcon#about to read 6, iclass 40, count 2 2006.182.07:20:16.86#ibcon#read 6, iclass 40, count 2 2006.182.07:20:16.86#ibcon#end of sib2, iclass 40, count 2 2006.182.07:20:16.86#ibcon#*after write, iclass 40, count 2 2006.182.07:20:16.86#ibcon#*before return 0, iclass 40, count 2 2006.182.07:20:16.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:16.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:16.86#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.07:20:16.86#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:16.86#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:16.98#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:16.98#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:16.98#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:20:16.98#ibcon#first serial, iclass 40, count 0 2006.182.07:20:16.98#ibcon#enter sib2, iclass 40, count 0 2006.182.07:20:16.98#ibcon#flushed, iclass 40, count 0 2006.182.07:20:16.98#ibcon#about to write, iclass 40, count 0 2006.182.07:20:16.98#ibcon#wrote, iclass 40, count 0 2006.182.07:20:16.98#ibcon#about to read 3, iclass 40, count 0 2006.182.07:20:17.00#ibcon#read 3, iclass 40, count 0 2006.182.07:20:17.00#ibcon#about to read 4, iclass 40, count 0 2006.182.07:20:17.00#ibcon#read 4, iclass 40, count 0 2006.182.07:20:17.00#ibcon#about to read 5, iclass 40, count 0 2006.182.07:20:17.00#ibcon#read 5, iclass 40, count 0 2006.182.07:20:17.00#ibcon#about to read 6, iclass 40, count 0 2006.182.07:20:17.00#ibcon#read 6, iclass 40, count 0 2006.182.07:20:17.00#ibcon#end of sib2, iclass 40, count 0 2006.182.07:20:17.00#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:20:17.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:20:17.00#ibcon#[25=USB\r\n] 2006.182.07:20:17.00#ibcon#*before write, iclass 40, count 0 2006.182.07:20:17.00#ibcon#enter sib2, iclass 40, count 0 2006.182.07:20:17.00#ibcon#flushed, iclass 40, count 0 2006.182.07:20:17.00#ibcon#about to write, iclass 40, count 0 2006.182.07:20:17.00#ibcon#wrote, iclass 40, count 0 2006.182.07:20:17.00#ibcon#about to read 3, iclass 40, count 0 2006.182.07:20:17.03#ibcon#read 3, iclass 40, count 0 2006.182.07:20:17.03#ibcon#about to read 4, iclass 40, count 0 2006.182.07:20:17.03#ibcon#read 4, iclass 40, count 0 2006.182.07:20:17.03#ibcon#about to read 5, iclass 40, count 0 2006.182.07:20:17.03#ibcon#read 5, iclass 40, count 0 2006.182.07:20:17.03#ibcon#about to read 6, iclass 40, count 0 2006.182.07:20:17.03#ibcon#read 6, iclass 40, count 0 2006.182.07:20:17.03#ibcon#end of sib2, iclass 40, count 0 2006.182.07:20:17.03#ibcon#*after write, iclass 40, count 0 2006.182.07:20:17.03#ibcon#*before return 0, iclass 40, count 0 2006.182.07:20:17.03#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:17.03#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:17.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:20:17.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:20:17.03$vc4f8/valo=2,572.99 2006.182.07:20:17.04#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.07:20:17.04#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.07:20:17.04#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:17.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:17.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:17.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:17.04#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:20:17.04#ibcon#first serial, iclass 4, count 0 2006.182.07:20:17.04#ibcon#enter sib2, iclass 4, count 0 2006.182.07:20:17.04#ibcon#flushed, iclass 4, count 0 2006.182.07:20:17.04#ibcon#about to write, iclass 4, count 0 2006.182.07:20:17.04#ibcon#wrote, iclass 4, count 0 2006.182.07:20:17.04#ibcon#about to read 3, iclass 4, count 0 2006.182.07:20:17.06#ibcon#read 3, iclass 4, count 0 2006.182.07:20:17.06#ibcon#about to read 4, iclass 4, count 0 2006.182.07:20:17.06#ibcon#read 4, iclass 4, count 0 2006.182.07:20:17.06#ibcon#about to read 5, iclass 4, count 0 2006.182.07:20:17.06#ibcon#read 5, iclass 4, count 0 2006.182.07:20:17.06#ibcon#about to read 6, iclass 4, count 0 2006.182.07:20:17.06#ibcon#read 6, iclass 4, count 0 2006.182.07:20:17.06#ibcon#end of sib2, iclass 4, count 0 2006.182.07:20:17.06#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:20:17.06#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:20:17.06#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:20:17.06#ibcon#*before write, iclass 4, count 0 2006.182.07:20:17.06#ibcon#enter sib2, iclass 4, count 0 2006.182.07:20:17.06#ibcon#flushed, iclass 4, count 0 2006.182.07:20:17.06#ibcon#about to write, iclass 4, count 0 2006.182.07:20:17.06#ibcon#wrote, iclass 4, count 0 2006.182.07:20:17.06#ibcon#about to read 3, iclass 4, count 0 2006.182.07:20:17.10#ibcon#read 3, iclass 4, count 0 2006.182.07:20:17.10#ibcon#about to read 4, iclass 4, count 0 2006.182.07:20:17.10#ibcon#read 4, iclass 4, count 0 2006.182.07:20:17.10#ibcon#about to read 5, iclass 4, count 0 2006.182.07:20:17.10#ibcon#read 5, iclass 4, count 0 2006.182.07:20:17.10#ibcon#about to read 6, iclass 4, count 0 2006.182.07:20:17.10#ibcon#read 6, iclass 4, count 0 2006.182.07:20:17.10#ibcon#end of sib2, iclass 4, count 0 2006.182.07:20:17.10#ibcon#*after write, iclass 4, count 0 2006.182.07:20:17.10#ibcon#*before return 0, iclass 4, count 0 2006.182.07:20:17.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:17.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:17.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:20:17.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:20:17.11$vc4f8/va=2,7 2006.182.07:20:17.11#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.07:20:17.11#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.07:20:17.11#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:17.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:17.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:17.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:17.14#ibcon#enter wrdev, iclass 6, count 2 2006.182.07:20:17.14#ibcon#first serial, iclass 6, count 2 2006.182.07:20:17.14#ibcon#enter sib2, iclass 6, count 2 2006.182.07:20:17.14#ibcon#flushed, iclass 6, count 2 2006.182.07:20:17.14#ibcon#about to write, iclass 6, count 2 2006.182.07:20:17.14#ibcon#wrote, iclass 6, count 2 2006.182.07:20:17.14#ibcon#about to read 3, iclass 6, count 2 2006.182.07:20:17.16#ibcon#read 3, iclass 6, count 2 2006.182.07:20:17.16#ibcon#about to read 4, iclass 6, count 2 2006.182.07:20:17.16#ibcon#read 4, iclass 6, count 2 2006.182.07:20:17.16#ibcon#about to read 5, iclass 6, count 2 2006.182.07:20:17.16#ibcon#read 5, iclass 6, count 2 2006.182.07:20:17.16#ibcon#about to read 6, iclass 6, count 2 2006.182.07:20:17.16#ibcon#read 6, iclass 6, count 2 2006.182.07:20:17.16#ibcon#end of sib2, iclass 6, count 2 2006.182.07:20:17.16#ibcon#*mode == 0, iclass 6, count 2 2006.182.07:20:17.16#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.07:20:17.16#ibcon#[25=AT02-07\r\n] 2006.182.07:20:17.16#ibcon#*before write, iclass 6, count 2 2006.182.07:20:17.16#ibcon#enter sib2, iclass 6, count 2 2006.182.07:20:17.16#ibcon#flushed, iclass 6, count 2 2006.182.07:20:17.16#ibcon#about to write, iclass 6, count 2 2006.182.07:20:17.16#ibcon#wrote, iclass 6, count 2 2006.182.07:20:17.16#ibcon#about to read 3, iclass 6, count 2 2006.182.07:20:17.19#ibcon#read 3, iclass 6, count 2 2006.182.07:20:17.19#ibcon#about to read 4, iclass 6, count 2 2006.182.07:20:17.19#ibcon#read 4, iclass 6, count 2 2006.182.07:20:17.19#ibcon#about to read 5, iclass 6, count 2 2006.182.07:20:17.19#ibcon#read 5, iclass 6, count 2 2006.182.07:20:17.19#ibcon#about to read 6, iclass 6, count 2 2006.182.07:20:17.19#ibcon#read 6, iclass 6, count 2 2006.182.07:20:17.19#ibcon#end of sib2, iclass 6, count 2 2006.182.07:20:17.19#ibcon#*after write, iclass 6, count 2 2006.182.07:20:17.19#ibcon#*before return 0, iclass 6, count 2 2006.182.07:20:17.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:17.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:17.19#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.07:20:17.19#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:17.19#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:17.31#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:17.31#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:17.31#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:20:17.31#ibcon#first serial, iclass 6, count 0 2006.182.07:20:17.31#ibcon#enter sib2, iclass 6, count 0 2006.182.07:20:17.31#ibcon#flushed, iclass 6, count 0 2006.182.07:20:17.31#ibcon#about to write, iclass 6, count 0 2006.182.07:20:17.31#ibcon#wrote, iclass 6, count 0 2006.182.07:20:17.31#ibcon#about to read 3, iclass 6, count 0 2006.182.07:20:17.33#ibcon#read 3, iclass 6, count 0 2006.182.07:20:17.33#ibcon#about to read 4, iclass 6, count 0 2006.182.07:20:17.33#ibcon#read 4, iclass 6, count 0 2006.182.07:20:17.33#ibcon#about to read 5, iclass 6, count 0 2006.182.07:20:17.33#ibcon#read 5, iclass 6, count 0 2006.182.07:20:17.33#ibcon#about to read 6, iclass 6, count 0 2006.182.07:20:17.33#ibcon#read 6, iclass 6, count 0 2006.182.07:20:17.33#ibcon#end of sib2, iclass 6, count 0 2006.182.07:20:17.33#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:20:17.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:20:17.33#ibcon#[25=USB\r\n] 2006.182.07:20:17.33#ibcon#*before write, iclass 6, count 0 2006.182.07:20:17.33#ibcon#enter sib2, iclass 6, count 0 2006.182.07:20:17.33#ibcon#flushed, iclass 6, count 0 2006.182.07:20:17.33#ibcon#about to write, iclass 6, count 0 2006.182.07:20:17.33#ibcon#wrote, iclass 6, count 0 2006.182.07:20:17.33#ibcon#about to read 3, iclass 6, count 0 2006.182.07:20:17.36#ibcon#read 3, iclass 6, count 0 2006.182.07:20:17.36#ibcon#about to read 4, iclass 6, count 0 2006.182.07:20:17.36#ibcon#read 4, iclass 6, count 0 2006.182.07:20:17.36#ibcon#about to read 5, iclass 6, count 0 2006.182.07:20:17.36#ibcon#read 5, iclass 6, count 0 2006.182.07:20:17.36#ibcon#about to read 6, iclass 6, count 0 2006.182.07:20:17.36#ibcon#read 6, iclass 6, count 0 2006.182.07:20:17.36#ibcon#end of sib2, iclass 6, count 0 2006.182.07:20:17.36#ibcon#*after write, iclass 6, count 0 2006.182.07:20:17.36#ibcon#*before return 0, iclass 6, count 0 2006.182.07:20:17.36#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:17.36#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:17.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:20:17.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:20:17.36$vc4f8/valo=3,672.99 2006.182.07:20:17.37#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.07:20:17.37#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.07:20:17.37#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:17.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:17.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:17.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:17.37#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:20:17.37#ibcon#first serial, iclass 10, count 0 2006.182.07:20:17.37#ibcon#enter sib2, iclass 10, count 0 2006.182.07:20:17.37#ibcon#flushed, iclass 10, count 0 2006.182.07:20:17.37#ibcon#about to write, iclass 10, count 0 2006.182.07:20:17.37#ibcon#wrote, iclass 10, count 0 2006.182.07:20:17.37#ibcon#about to read 3, iclass 10, count 0 2006.182.07:20:17.39#ibcon#read 3, iclass 10, count 0 2006.182.07:20:17.39#ibcon#about to read 4, iclass 10, count 0 2006.182.07:20:17.39#ibcon#read 4, iclass 10, count 0 2006.182.07:20:17.39#ibcon#about to read 5, iclass 10, count 0 2006.182.07:20:17.39#ibcon#read 5, iclass 10, count 0 2006.182.07:20:17.39#ibcon#about to read 6, iclass 10, count 0 2006.182.07:20:17.39#ibcon#read 6, iclass 10, count 0 2006.182.07:20:17.39#ibcon#end of sib2, iclass 10, count 0 2006.182.07:20:17.39#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:20:17.39#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:20:17.39#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:20:17.39#ibcon#*before write, iclass 10, count 0 2006.182.07:20:17.39#ibcon#enter sib2, iclass 10, count 0 2006.182.07:20:17.39#ibcon#flushed, iclass 10, count 0 2006.182.07:20:17.39#ibcon#about to write, iclass 10, count 0 2006.182.07:20:17.39#ibcon#wrote, iclass 10, count 0 2006.182.07:20:17.39#ibcon#about to read 3, iclass 10, count 0 2006.182.07:20:17.43#ibcon#read 3, iclass 10, count 0 2006.182.07:20:17.43#ibcon#about to read 4, iclass 10, count 0 2006.182.07:20:17.43#ibcon#read 4, iclass 10, count 0 2006.182.07:20:17.43#ibcon#about to read 5, iclass 10, count 0 2006.182.07:20:17.43#ibcon#read 5, iclass 10, count 0 2006.182.07:20:17.43#ibcon#about to read 6, iclass 10, count 0 2006.182.07:20:17.43#ibcon#read 6, iclass 10, count 0 2006.182.07:20:17.43#ibcon#end of sib2, iclass 10, count 0 2006.182.07:20:17.43#ibcon#*after write, iclass 10, count 0 2006.182.07:20:17.43#ibcon#*before return 0, iclass 10, count 0 2006.182.07:20:17.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:17.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:17.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:20:17.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:20:17.44$vc4f8/va=3,6 2006.182.07:20:17.44#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.07:20:17.44#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.07:20:17.44#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:17.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:17.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:17.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:17.47#ibcon#enter wrdev, iclass 12, count 2 2006.182.07:20:17.47#ibcon#first serial, iclass 12, count 2 2006.182.07:20:17.47#ibcon#enter sib2, iclass 12, count 2 2006.182.07:20:17.47#ibcon#flushed, iclass 12, count 2 2006.182.07:20:17.47#ibcon#about to write, iclass 12, count 2 2006.182.07:20:17.47#ibcon#wrote, iclass 12, count 2 2006.182.07:20:17.47#ibcon#about to read 3, iclass 12, count 2 2006.182.07:20:17.50#ibcon#read 3, iclass 12, count 2 2006.182.07:20:17.50#ibcon#about to read 4, iclass 12, count 2 2006.182.07:20:17.50#ibcon#read 4, iclass 12, count 2 2006.182.07:20:17.50#ibcon#about to read 5, iclass 12, count 2 2006.182.07:20:17.50#ibcon#read 5, iclass 12, count 2 2006.182.07:20:17.50#ibcon#about to read 6, iclass 12, count 2 2006.182.07:20:17.50#ibcon#read 6, iclass 12, count 2 2006.182.07:20:17.50#ibcon#end of sib2, iclass 12, count 2 2006.182.07:20:17.50#ibcon#*mode == 0, iclass 12, count 2 2006.182.07:20:17.50#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.07:20:17.50#ibcon#[25=AT03-06\r\n] 2006.182.07:20:17.50#ibcon#*before write, iclass 12, count 2 2006.182.07:20:17.50#ibcon#enter sib2, iclass 12, count 2 2006.182.07:20:17.50#ibcon#flushed, iclass 12, count 2 2006.182.07:20:17.50#ibcon#about to write, iclass 12, count 2 2006.182.07:20:17.50#ibcon#wrote, iclass 12, count 2 2006.182.07:20:17.50#ibcon#about to read 3, iclass 12, count 2 2006.182.07:20:17.53#ibcon#read 3, iclass 12, count 2 2006.182.07:20:17.53#ibcon#about to read 4, iclass 12, count 2 2006.182.07:20:17.53#ibcon#read 4, iclass 12, count 2 2006.182.07:20:17.53#ibcon#about to read 5, iclass 12, count 2 2006.182.07:20:17.53#ibcon#read 5, iclass 12, count 2 2006.182.07:20:17.53#ibcon#about to read 6, iclass 12, count 2 2006.182.07:20:17.53#ibcon#read 6, iclass 12, count 2 2006.182.07:20:17.53#ibcon#end of sib2, iclass 12, count 2 2006.182.07:20:17.53#ibcon#*after write, iclass 12, count 2 2006.182.07:20:17.53#ibcon#*before return 0, iclass 12, count 2 2006.182.07:20:17.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:17.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:17.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.07:20:17.53#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:17.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:17.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:17.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:17.65#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:20:17.65#ibcon#first serial, iclass 12, count 0 2006.182.07:20:17.65#ibcon#enter sib2, iclass 12, count 0 2006.182.07:20:17.65#ibcon#flushed, iclass 12, count 0 2006.182.07:20:17.65#ibcon#about to write, iclass 12, count 0 2006.182.07:20:17.65#ibcon#wrote, iclass 12, count 0 2006.182.07:20:17.65#ibcon#about to read 3, iclass 12, count 0 2006.182.07:20:17.67#ibcon#read 3, iclass 12, count 0 2006.182.07:20:17.67#ibcon#about to read 4, iclass 12, count 0 2006.182.07:20:17.67#ibcon#read 4, iclass 12, count 0 2006.182.07:20:17.67#ibcon#about to read 5, iclass 12, count 0 2006.182.07:20:17.67#ibcon#read 5, iclass 12, count 0 2006.182.07:20:17.67#ibcon#about to read 6, iclass 12, count 0 2006.182.07:20:17.67#ibcon#read 6, iclass 12, count 0 2006.182.07:20:17.67#ibcon#end of sib2, iclass 12, count 0 2006.182.07:20:17.67#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:20:17.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:20:17.67#ibcon#[25=USB\r\n] 2006.182.07:20:17.67#ibcon#*before write, iclass 12, count 0 2006.182.07:20:17.67#ibcon#enter sib2, iclass 12, count 0 2006.182.07:20:17.67#ibcon#flushed, iclass 12, count 0 2006.182.07:20:17.67#ibcon#about to write, iclass 12, count 0 2006.182.07:20:17.67#ibcon#wrote, iclass 12, count 0 2006.182.07:20:17.67#ibcon#about to read 3, iclass 12, count 0 2006.182.07:20:17.70#ibcon#read 3, iclass 12, count 0 2006.182.07:20:17.70#ibcon#about to read 4, iclass 12, count 0 2006.182.07:20:17.70#ibcon#read 4, iclass 12, count 0 2006.182.07:20:17.70#ibcon#about to read 5, iclass 12, count 0 2006.182.07:20:17.70#ibcon#read 5, iclass 12, count 0 2006.182.07:20:17.70#ibcon#about to read 6, iclass 12, count 0 2006.182.07:20:17.70#ibcon#read 6, iclass 12, count 0 2006.182.07:20:17.70#ibcon#end of sib2, iclass 12, count 0 2006.182.07:20:17.70#ibcon#*after write, iclass 12, count 0 2006.182.07:20:17.70#ibcon#*before return 0, iclass 12, count 0 2006.182.07:20:17.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:17.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:17.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:20:17.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:20:17.70$vc4f8/valo=4,832.99 2006.182.07:20:17.71#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.07:20:17.71#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.07:20:17.71#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:17.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:17.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:17.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:17.71#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:20:17.71#ibcon#first serial, iclass 14, count 0 2006.182.07:20:17.71#ibcon#enter sib2, iclass 14, count 0 2006.182.07:20:17.71#ibcon#flushed, iclass 14, count 0 2006.182.07:20:17.71#ibcon#about to write, iclass 14, count 0 2006.182.07:20:17.71#ibcon#wrote, iclass 14, count 0 2006.182.07:20:17.71#ibcon#about to read 3, iclass 14, count 0 2006.182.07:20:17.72#ibcon#read 3, iclass 14, count 0 2006.182.07:20:17.72#ibcon#about to read 4, iclass 14, count 0 2006.182.07:20:17.72#ibcon#read 4, iclass 14, count 0 2006.182.07:20:17.72#ibcon#about to read 5, iclass 14, count 0 2006.182.07:20:17.72#ibcon#read 5, iclass 14, count 0 2006.182.07:20:17.72#ibcon#about to read 6, iclass 14, count 0 2006.182.07:20:17.72#ibcon#read 6, iclass 14, count 0 2006.182.07:20:17.72#ibcon#end of sib2, iclass 14, count 0 2006.182.07:20:17.72#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:20:17.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:20:17.72#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:20:17.72#ibcon#*before write, iclass 14, count 0 2006.182.07:20:17.72#ibcon#enter sib2, iclass 14, count 0 2006.182.07:20:17.72#ibcon#flushed, iclass 14, count 0 2006.182.07:20:17.72#ibcon#about to write, iclass 14, count 0 2006.182.07:20:17.72#ibcon#wrote, iclass 14, count 0 2006.182.07:20:17.72#ibcon#about to read 3, iclass 14, count 0 2006.182.07:20:17.76#ibcon#read 3, iclass 14, count 0 2006.182.07:20:17.76#ibcon#about to read 4, iclass 14, count 0 2006.182.07:20:17.76#ibcon#read 4, iclass 14, count 0 2006.182.07:20:17.76#ibcon#about to read 5, iclass 14, count 0 2006.182.07:20:17.76#ibcon#read 5, iclass 14, count 0 2006.182.07:20:17.76#ibcon#about to read 6, iclass 14, count 0 2006.182.07:20:17.76#ibcon#read 6, iclass 14, count 0 2006.182.07:20:17.76#ibcon#end of sib2, iclass 14, count 0 2006.182.07:20:17.76#ibcon#*after write, iclass 14, count 0 2006.182.07:20:17.76#ibcon#*before return 0, iclass 14, count 0 2006.182.07:20:17.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:17.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:17.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:20:17.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:20:17.76$vc4f8/va=4,7 2006.182.07:20:17.77#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.07:20:17.77#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.07:20:17.77#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:17.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:17.81#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:17.81#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:17.81#ibcon#enter wrdev, iclass 16, count 2 2006.182.07:20:17.81#ibcon#first serial, iclass 16, count 2 2006.182.07:20:17.81#ibcon#enter sib2, iclass 16, count 2 2006.182.07:20:17.81#ibcon#flushed, iclass 16, count 2 2006.182.07:20:17.81#ibcon#about to write, iclass 16, count 2 2006.182.07:20:17.81#ibcon#wrote, iclass 16, count 2 2006.182.07:20:17.81#ibcon#about to read 3, iclass 16, count 2 2006.182.07:20:17.83#ibcon#read 3, iclass 16, count 2 2006.182.07:20:17.83#ibcon#about to read 4, iclass 16, count 2 2006.182.07:20:17.83#ibcon#read 4, iclass 16, count 2 2006.182.07:20:17.83#ibcon#about to read 5, iclass 16, count 2 2006.182.07:20:17.83#ibcon#read 5, iclass 16, count 2 2006.182.07:20:17.83#ibcon#about to read 6, iclass 16, count 2 2006.182.07:20:17.83#ibcon#read 6, iclass 16, count 2 2006.182.07:20:17.83#ibcon#end of sib2, iclass 16, count 2 2006.182.07:20:17.83#ibcon#*mode == 0, iclass 16, count 2 2006.182.07:20:17.83#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.07:20:17.83#ibcon#[25=AT04-07\r\n] 2006.182.07:20:17.83#ibcon#*before write, iclass 16, count 2 2006.182.07:20:17.83#ibcon#enter sib2, iclass 16, count 2 2006.182.07:20:17.83#ibcon#flushed, iclass 16, count 2 2006.182.07:20:17.83#ibcon#about to write, iclass 16, count 2 2006.182.07:20:17.83#ibcon#wrote, iclass 16, count 2 2006.182.07:20:17.83#ibcon#about to read 3, iclass 16, count 2 2006.182.07:20:17.86#ibcon#read 3, iclass 16, count 2 2006.182.07:20:17.86#ibcon#about to read 4, iclass 16, count 2 2006.182.07:20:17.86#ibcon#read 4, iclass 16, count 2 2006.182.07:20:17.86#ibcon#about to read 5, iclass 16, count 2 2006.182.07:20:17.86#ibcon#read 5, iclass 16, count 2 2006.182.07:20:17.86#ibcon#about to read 6, iclass 16, count 2 2006.182.07:20:17.86#ibcon#read 6, iclass 16, count 2 2006.182.07:20:17.86#ibcon#end of sib2, iclass 16, count 2 2006.182.07:20:17.86#ibcon#*after write, iclass 16, count 2 2006.182.07:20:17.86#ibcon#*before return 0, iclass 16, count 2 2006.182.07:20:17.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:17.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:17.86#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.07:20:17.86#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:17.86#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:17.98#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:17.98#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:17.98#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:20:17.98#ibcon#first serial, iclass 16, count 0 2006.182.07:20:17.98#ibcon#enter sib2, iclass 16, count 0 2006.182.07:20:17.98#ibcon#flushed, iclass 16, count 0 2006.182.07:20:17.98#ibcon#about to write, iclass 16, count 0 2006.182.07:20:17.98#ibcon#wrote, iclass 16, count 0 2006.182.07:20:17.98#ibcon#about to read 3, iclass 16, count 0 2006.182.07:20:18.00#ibcon#read 3, iclass 16, count 0 2006.182.07:20:18.00#ibcon#about to read 4, iclass 16, count 0 2006.182.07:20:18.00#ibcon#read 4, iclass 16, count 0 2006.182.07:20:18.00#ibcon#about to read 5, iclass 16, count 0 2006.182.07:20:18.00#ibcon#read 5, iclass 16, count 0 2006.182.07:20:18.00#ibcon#about to read 6, iclass 16, count 0 2006.182.07:20:18.00#ibcon#read 6, iclass 16, count 0 2006.182.07:20:18.00#ibcon#end of sib2, iclass 16, count 0 2006.182.07:20:18.00#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:20:18.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:20:18.00#ibcon#[25=USB\r\n] 2006.182.07:20:18.00#ibcon#*before write, iclass 16, count 0 2006.182.07:20:18.00#ibcon#enter sib2, iclass 16, count 0 2006.182.07:20:18.00#ibcon#flushed, iclass 16, count 0 2006.182.07:20:18.00#ibcon#about to write, iclass 16, count 0 2006.182.07:20:18.00#ibcon#wrote, iclass 16, count 0 2006.182.07:20:18.00#ibcon#about to read 3, iclass 16, count 0 2006.182.07:20:18.03#ibcon#read 3, iclass 16, count 0 2006.182.07:20:18.03#ibcon#about to read 4, iclass 16, count 0 2006.182.07:20:18.03#ibcon#read 4, iclass 16, count 0 2006.182.07:20:18.03#ibcon#about to read 5, iclass 16, count 0 2006.182.07:20:18.03#ibcon#read 5, iclass 16, count 0 2006.182.07:20:18.03#ibcon#about to read 6, iclass 16, count 0 2006.182.07:20:18.03#ibcon#read 6, iclass 16, count 0 2006.182.07:20:18.03#ibcon#end of sib2, iclass 16, count 0 2006.182.07:20:18.03#ibcon#*after write, iclass 16, count 0 2006.182.07:20:18.03#ibcon#*before return 0, iclass 16, count 0 2006.182.07:20:18.03#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:18.03#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:18.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:20:18.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:20:18.03$vc4f8/valo=5,652.99 2006.182.07:20:18.04#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.07:20:18.04#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.07:20:18.04#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:18.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:18.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:18.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:18.04#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:20:18.04#ibcon#first serial, iclass 18, count 0 2006.182.07:20:18.04#ibcon#enter sib2, iclass 18, count 0 2006.182.07:20:18.04#ibcon#flushed, iclass 18, count 0 2006.182.07:20:18.04#ibcon#about to write, iclass 18, count 0 2006.182.07:20:18.04#ibcon#wrote, iclass 18, count 0 2006.182.07:20:18.04#ibcon#about to read 3, iclass 18, count 0 2006.182.07:20:18.05#ibcon#read 3, iclass 18, count 0 2006.182.07:20:18.05#ibcon#about to read 4, iclass 18, count 0 2006.182.07:20:18.05#ibcon#read 4, iclass 18, count 0 2006.182.07:20:18.05#ibcon#about to read 5, iclass 18, count 0 2006.182.07:20:18.05#ibcon#read 5, iclass 18, count 0 2006.182.07:20:18.05#ibcon#about to read 6, iclass 18, count 0 2006.182.07:20:18.05#ibcon#read 6, iclass 18, count 0 2006.182.07:20:18.05#ibcon#end of sib2, iclass 18, count 0 2006.182.07:20:18.05#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:20:18.05#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:20:18.05#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:20:18.05#ibcon#*before write, iclass 18, count 0 2006.182.07:20:18.05#ibcon#enter sib2, iclass 18, count 0 2006.182.07:20:18.05#ibcon#flushed, iclass 18, count 0 2006.182.07:20:18.05#ibcon#about to write, iclass 18, count 0 2006.182.07:20:18.05#ibcon#wrote, iclass 18, count 0 2006.182.07:20:18.05#ibcon#about to read 3, iclass 18, count 0 2006.182.07:20:18.09#ibcon#read 3, iclass 18, count 0 2006.182.07:20:18.09#ibcon#about to read 4, iclass 18, count 0 2006.182.07:20:18.09#ibcon#read 4, iclass 18, count 0 2006.182.07:20:18.09#ibcon#about to read 5, iclass 18, count 0 2006.182.07:20:18.09#ibcon#read 5, iclass 18, count 0 2006.182.07:20:18.09#ibcon#about to read 6, iclass 18, count 0 2006.182.07:20:18.09#ibcon#read 6, iclass 18, count 0 2006.182.07:20:18.09#ibcon#end of sib2, iclass 18, count 0 2006.182.07:20:18.09#ibcon#*after write, iclass 18, count 0 2006.182.07:20:18.09#ibcon#*before return 0, iclass 18, count 0 2006.182.07:20:18.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:18.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:18.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:20:18.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:20:18.09$vc4f8/va=5,7 2006.182.07:20:18.10#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.07:20:18.10#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.07:20:18.10#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:18.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:18.14#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:18.14#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:18.14#ibcon#enter wrdev, iclass 20, count 2 2006.182.07:20:18.14#ibcon#first serial, iclass 20, count 2 2006.182.07:20:18.14#ibcon#enter sib2, iclass 20, count 2 2006.182.07:20:18.14#ibcon#flushed, iclass 20, count 2 2006.182.07:20:18.14#ibcon#about to write, iclass 20, count 2 2006.182.07:20:18.14#ibcon#wrote, iclass 20, count 2 2006.182.07:20:18.14#ibcon#about to read 3, iclass 20, count 2 2006.182.07:20:18.16#ibcon#read 3, iclass 20, count 2 2006.182.07:20:18.16#ibcon#about to read 4, iclass 20, count 2 2006.182.07:20:18.16#ibcon#read 4, iclass 20, count 2 2006.182.07:20:18.16#ibcon#about to read 5, iclass 20, count 2 2006.182.07:20:18.16#ibcon#read 5, iclass 20, count 2 2006.182.07:20:18.16#ibcon#about to read 6, iclass 20, count 2 2006.182.07:20:18.16#ibcon#read 6, iclass 20, count 2 2006.182.07:20:18.16#ibcon#end of sib2, iclass 20, count 2 2006.182.07:20:18.16#ibcon#*mode == 0, iclass 20, count 2 2006.182.07:20:18.16#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.07:20:18.16#ibcon#[25=AT05-07\r\n] 2006.182.07:20:18.16#ibcon#*before write, iclass 20, count 2 2006.182.07:20:18.16#ibcon#enter sib2, iclass 20, count 2 2006.182.07:20:18.16#ibcon#flushed, iclass 20, count 2 2006.182.07:20:18.16#ibcon#about to write, iclass 20, count 2 2006.182.07:20:18.16#ibcon#wrote, iclass 20, count 2 2006.182.07:20:18.16#ibcon#about to read 3, iclass 20, count 2 2006.182.07:20:18.19#ibcon#read 3, iclass 20, count 2 2006.182.07:20:18.19#ibcon#about to read 4, iclass 20, count 2 2006.182.07:20:18.19#ibcon#read 4, iclass 20, count 2 2006.182.07:20:18.19#ibcon#about to read 5, iclass 20, count 2 2006.182.07:20:18.19#ibcon#read 5, iclass 20, count 2 2006.182.07:20:18.19#ibcon#about to read 6, iclass 20, count 2 2006.182.07:20:18.19#ibcon#read 6, iclass 20, count 2 2006.182.07:20:18.19#ibcon#end of sib2, iclass 20, count 2 2006.182.07:20:18.19#ibcon#*after write, iclass 20, count 2 2006.182.07:20:18.19#ibcon#*before return 0, iclass 20, count 2 2006.182.07:20:18.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:18.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:18.19#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.07:20:18.19#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:18.19#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:18.31#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:18.31#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:18.31#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:20:18.31#ibcon#first serial, iclass 20, count 0 2006.182.07:20:18.31#ibcon#enter sib2, iclass 20, count 0 2006.182.07:20:18.31#ibcon#flushed, iclass 20, count 0 2006.182.07:20:18.31#ibcon#about to write, iclass 20, count 0 2006.182.07:20:18.31#ibcon#wrote, iclass 20, count 0 2006.182.07:20:18.31#ibcon#about to read 3, iclass 20, count 0 2006.182.07:20:18.33#ibcon#read 3, iclass 20, count 0 2006.182.07:20:18.33#ibcon#about to read 4, iclass 20, count 0 2006.182.07:20:18.33#ibcon#read 4, iclass 20, count 0 2006.182.07:20:18.33#ibcon#about to read 5, iclass 20, count 0 2006.182.07:20:18.33#ibcon#read 5, iclass 20, count 0 2006.182.07:20:18.33#ibcon#about to read 6, iclass 20, count 0 2006.182.07:20:18.33#ibcon#read 6, iclass 20, count 0 2006.182.07:20:18.33#ibcon#end of sib2, iclass 20, count 0 2006.182.07:20:18.33#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:20:18.33#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:20:18.33#ibcon#[25=USB\r\n] 2006.182.07:20:18.33#ibcon#*before write, iclass 20, count 0 2006.182.07:20:18.33#ibcon#enter sib2, iclass 20, count 0 2006.182.07:20:18.33#ibcon#flushed, iclass 20, count 0 2006.182.07:20:18.33#ibcon#about to write, iclass 20, count 0 2006.182.07:20:18.33#ibcon#wrote, iclass 20, count 0 2006.182.07:20:18.33#ibcon#about to read 3, iclass 20, count 0 2006.182.07:20:18.36#ibcon#read 3, iclass 20, count 0 2006.182.07:20:18.36#ibcon#about to read 4, iclass 20, count 0 2006.182.07:20:18.36#ibcon#read 4, iclass 20, count 0 2006.182.07:20:18.36#ibcon#about to read 5, iclass 20, count 0 2006.182.07:20:18.36#ibcon#read 5, iclass 20, count 0 2006.182.07:20:18.36#ibcon#about to read 6, iclass 20, count 0 2006.182.07:20:18.36#ibcon#read 6, iclass 20, count 0 2006.182.07:20:18.36#ibcon#end of sib2, iclass 20, count 0 2006.182.07:20:18.36#ibcon#*after write, iclass 20, count 0 2006.182.07:20:18.36#ibcon#*before return 0, iclass 20, count 0 2006.182.07:20:18.36#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:18.36#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:18.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:20:18.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:20:18.36$vc4f8/valo=6,772.99 2006.182.07:20:18.37#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.07:20:18.37#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.07:20:18.37#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:18.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:18.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:18.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:18.37#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:20:18.37#ibcon#first serial, iclass 22, count 0 2006.182.07:20:18.37#ibcon#enter sib2, iclass 22, count 0 2006.182.07:20:18.37#ibcon#flushed, iclass 22, count 0 2006.182.07:20:18.37#ibcon#about to write, iclass 22, count 0 2006.182.07:20:18.37#ibcon#wrote, iclass 22, count 0 2006.182.07:20:18.37#ibcon#about to read 3, iclass 22, count 0 2006.182.07:20:18.38#ibcon#read 3, iclass 22, count 0 2006.182.07:20:18.38#ibcon#about to read 4, iclass 22, count 0 2006.182.07:20:18.38#ibcon#read 4, iclass 22, count 0 2006.182.07:20:18.38#ibcon#about to read 5, iclass 22, count 0 2006.182.07:20:18.38#ibcon#read 5, iclass 22, count 0 2006.182.07:20:18.38#ibcon#about to read 6, iclass 22, count 0 2006.182.07:20:18.38#ibcon#read 6, iclass 22, count 0 2006.182.07:20:18.38#ibcon#end of sib2, iclass 22, count 0 2006.182.07:20:18.38#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:20:18.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:20:18.38#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:20:18.38#ibcon#*before write, iclass 22, count 0 2006.182.07:20:18.38#ibcon#enter sib2, iclass 22, count 0 2006.182.07:20:18.38#ibcon#flushed, iclass 22, count 0 2006.182.07:20:18.38#ibcon#about to write, iclass 22, count 0 2006.182.07:20:18.38#ibcon#wrote, iclass 22, count 0 2006.182.07:20:18.38#ibcon#about to read 3, iclass 22, count 0 2006.182.07:20:18.42#ibcon#read 3, iclass 22, count 0 2006.182.07:20:18.42#ibcon#about to read 4, iclass 22, count 0 2006.182.07:20:18.42#ibcon#read 4, iclass 22, count 0 2006.182.07:20:18.42#ibcon#about to read 5, iclass 22, count 0 2006.182.07:20:18.42#ibcon#read 5, iclass 22, count 0 2006.182.07:20:18.42#ibcon#about to read 6, iclass 22, count 0 2006.182.07:20:18.42#ibcon#read 6, iclass 22, count 0 2006.182.07:20:18.42#ibcon#end of sib2, iclass 22, count 0 2006.182.07:20:18.42#ibcon#*after write, iclass 22, count 0 2006.182.07:20:18.42#ibcon#*before return 0, iclass 22, count 0 2006.182.07:20:18.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:18.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:18.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:20:18.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:20:18.42$vc4f8/va=6,6 2006.182.07:20:18.43#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.07:20:18.43#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.07:20:18.43#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:18.43#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:20:18.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:20:18.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:20:18.47#ibcon#enter wrdev, iclass 24, count 2 2006.182.07:20:18.47#ibcon#first serial, iclass 24, count 2 2006.182.07:20:18.47#ibcon#enter sib2, iclass 24, count 2 2006.182.07:20:18.47#ibcon#flushed, iclass 24, count 2 2006.182.07:20:18.47#ibcon#about to write, iclass 24, count 2 2006.182.07:20:18.47#ibcon#wrote, iclass 24, count 2 2006.182.07:20:18.47#ibcon#about to read 3, iclass 24, count 2 2006.182.07:20:18.49#ibcon#read 3, iclass 24, count 2 2006.182.07:20:18.49#ibcon#about to read 4, iclass 24, count 2 2006.182.07:20:18.49#ibcon#read 4, iclass 24, count 2 2006.182.07:20:18.49#ibcon#about to read 5, iclass 24, count 2 2006.182.07:20:18.49#ibcon#read 5, iclass 24, count 2 2006.182.07:20:18.49#ibcon#about to read 6, iclass 24, count 2 2006.182.07:20:18.49#ibcon#read 6, iclass 24, count 2 2006.182.07:20:18.49#ibcon#end of sib2, iclass 24, count 2 2006.182.07:20:18.49#ibcon#*mode == 0, iclass 24, count 2 2006.182.07:20:18.49#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.07:20:18.49#ibcon#[25=AT06-06\r\n] 2006.182.07:20:18.49#ibcon#*before write, iclass 24, count 2 2006.182.07:20:18.49#ibcon#enter sib2, iclass 24, count 2 2006.182.07:20:18.49#ibcon#flushed, iclass 24, count 2 2006.182.07:20:18.49#ibcon#about to write, iclass 24, count 2 2006.182.07:20:18.49#ibcon#wrote, iclass 24, count 2 2006.182.07:20:18.49#ibcon#about to read 3, iclass 24, count 2 2006.182.07:20:18.52#ibcon#read 3, iclass 24, count 2 2006.182.07:20:18.52#ibcon#about to read 4, iclass 24, count 2 2006.182.07:20:18.52#ibcon#read 4, iclass 24, count 2 2006.182.07:20:18.52#ibcon#about to read 5, iclass 24, count 2 2006.182.07:20:18.52#ibcon#read 5, iclass 24, count 2 2006.182.07:20:18.52#ibcon#about to read 6, iclass 24, count 2 2006.182.07:20:18.52#ibcon#read 6, iclass 24, count 2 2006.182.07:20:18.52#ibcon#end of sib2, iclass 24, count 2 2006.182.07:20:18.52#ibcon#*after write, iclass 24, count 2 2006.182.07:20:18.52#ibcon#*before return 0, iclass 24, count 2 2006.182.07:20:18.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:20:18.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:20:18.52#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.07:20:18.52#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:18.52#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:20:18.64#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:20:18.64#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:20:18.64#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:20:18.64#ibcon#first serial, iclass 24, count 0 2006.182.07:20:18.64#ibcon#enter sib2, iclass 24, count 0 2006.182.07:20:18.64#ibcon#flushed, iclass 24, count 0 2006.182.07:20:18.64#ibcon#about to write, iclass 24, count 0 2006.182.07:20:18.64#ibcon#wrote, iclass 24, count 0 2006.182.07:20:18.64#ibcon#about to read 3, iclass 24, count 0 2006.182.07:20:18.66#ibcon#read 3, iclass 24, count 0 2006.182.07:20:18.66#ibcon#about to read 4, iclass 24, count 0 2006.182.07:20:18.66#ibcon#read 4, iclass 24, count 0 2006.182.07:20:18.66#ibcon#about to read 5, iclass 24, count 0 2006.182.07:20:18.66#ibcon#read 5, iclass 24, count 0 2006.182.07:20:18.66#ibcon#about to read 6, iclass 24, count 0 2006.182.07:20:18.66#ibcon#read 6, iclass 24, count 0 2006.182.07:20:18.66#ibcon#end of sib2, iclass 24, count 0 2006.182.07:20:18.66#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:20:18.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:20:18.66#ibcon#[25=USB\r\n] 2006.182.07:20:18.66#ibcon#*before write, iclass 24, count 0 2006.182.07:20:18.66#ibcon#enter sib2, iclass 24, count 0 2006.182.07:20:18.66#ibcon#flushed, iclass 24, count 0 2006.182.07:20:18.66#ibcon#about to write, iclass 24, count 0 2006.182.07:20:18.66#ibcon#wrote, iclass 24, count 0 2006.182.07:20:18.66#ibcon#about to read 3, iclass 24, count 0 2006.182.07:20:18.69#ibcon#read 3, iclass 24, count 0 2006.182.07:20:18.69#ibcon#about to read 4, iclass 24, count 0 2006.182.07:20:18.69#ibcon#read 4, iclass 24, count 0 2006.182.07:20:18.69#ibcon#about to read 5, iclass 24, count 0 2006.182.07:20:18.69#ibcon#read 5, iclass 24, count 0 2006.182.07:20:18.69#ibcon#about to read 6, iclass 24, count 0 2006.182.07:20:18.69#ibcon#read 6, iclass 24, count 0 2006.182.07:20:18.69#ibcon#end of sib2, iclass 24, count 0 2006.182.07:20:18.69#ibcon#*after write, iclass 24, count 0 2006.182.07:20:18.69#ibcon#*before return 0, iclass 24, count 0 2006.182.07:20:18.69#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:20:18.69#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:20:18.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:20:18.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:20:18.69$vc4f8/valo=7,832.99 2006.182.07:20:18.70#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.07:20:18.70#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.07:20:18.70#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:18.70#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:20:18.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:20:18.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:20:18.70#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:20:18.70#ibcon#first serial, iclass 26, count 0 2006.182.07:20:18.70#ibcon#enter sib2, iclass 26, count 0 2006.182.07:20:18.70#ibcon#flushed, iclass 26, count 0 2006.182.07:20:18.70#ibcon#about to write, iclass 26, count 0 2006.182.07:20:18.70#ibcon#wrote, iclass 26, count 0 2006.182.07:20:18.70#ibcon#about to read 3, iclass 26, count 0 2006.182.07:20:18.71#ibcon#read 3, iclass 26, count 0 2006.182.07:20:18.71#ibcon#about to read 4, iclass 26, count 0 2006.182.07:20:18.71#ibcon#read 4, iclass 26, count 0 2006.182.07:20:18.71#ibcon#about to read 5, iclass 26, count 0 2006.182.07:20:18.71#ibcon#read 5, iclass 26, count 0 2006.182.07:20:18.71#ibcon#about to read 6, iclass 26, count 0 2006.182.07:20:18.71#ibcon#read 6, iclass 26, count 0 2006.182.07:20:18.71#ibcon#end of sib2, iclass 26, count 0 2006.182.07:20:18.71#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:20:18.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:20:18.71#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:20:18.71#ibcon#*before write, iclass 26, count 0 2006.182.07:20:18.71#ibcon#enter sib2, iclass 26, count 0 2006.182.07:20:18.71#ibcon#flushed, iclass 26, count 0 2006.182.07:20:18.71#ibcon#about to write, iclass 26, count 0 2006.182.07:20:18.71#ibcon#wrote, iclass 26, count 0 2006.182.07:20:18.71#ibcon#about to read 3, iclass 26, count 0 2006.182.07:20:18.75#ibcon#read 3, iclass 26, count 0 2006.182.07:20:18.75#ibcon#about to read 4, iclass 26, count 0 2006.182.07:20:18.75#ibcon#read 4, iclass 26, count 0 2006.182.07:20:18.75#ibcon#about to read 5, iclass 26, count 0 2006.182.07:20:18.75#ibcon#read 5, iclass 26, count 0 2006.182.07:20:18.75#ibcon#about to read 6, iclass 26, count 0 2006.182.07:20:18.75#ibcon#read 6, iclass 26, count 0 2006.182.07:20:18.75#ibcon#end of sib2, iclass 26, count 0 2006.182.07:20:18.75#ibcon#*after write, iclass 26, count 0 2006.182.07:20:18.75#ibcon#*before return 0, iclass 26, count 0 2006.182.07:20:18.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:20:18.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:20:18.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:20:18.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:20:18.76$vc4f8/va=7,6 2006.182.07:20:18.76#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.07:20:18.76#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.07:20:18.76#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:18.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:20:18.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:20:18.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:20:18.80#ibcon#enter wrdev, iclass 28, count 2 2006.182.07:20:18.80#ibcon#first serial, iclass 28, count 2 2006.182.07:20:18.80#ibcon#enter sib2, iclass 28, count 2 2006.182.07:20:18.80#ibcon#flushed, iclass 28, count 2 2006.182.07:20:18.80#ibcon#about to write, iclass 28, count 2 2006.182.07:20:18.80#ibcon#wrote, iclass 28, count 2 2006.182.07:20:18.80#ibcon#about to read 3, iclass 28, count 2 2006.182.07:20:18.82#ibcon#read 3, iclass 28, count 2 2006.182.07:20:18.82#ibcon#about to read 4, iclass 28, count 2 2006.182.07:20:18.82#ibcon#read 4, iclass 28, count 2 2006.182.07:20:18.82#ibcon#about to read 5, iclass 28, count 2 2006.182.07:20:18.82#ibcon#read 5, iclass 28, count 2 2006.182.07:20:18.82#ibcon#about to read 6, iclass 28, count 2 2006.182.07:20:18.82#ibcon#read 6, iclass 28, count 2 2006.182.07:20:18.82#ibcon#end of sib2, iclass 28, count 2 2006.182.07:20:18.82#ibcon#*mode == 0, iclass 28, count 2 2006.182.07:20:18.82#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.07:20:18.82#ibcon#[25=AT07-06\r\n] 2006.182.07:20:18.82#ibcon#*before write, iclass 28, count 2 2006.182.07:20:18.82#ibcon#enter sib2, iclass 28, count 2 2006.182.07:20:18.82#ibcon#flushed, iclass 28, count 2 2006.182.07:20:18.82#ibcon#about to write, iclass 28, count 2 2006.182.07:20:18.82#ibcon#wrote, iclass 28, count 2 2006.182.07:20:18.82#ibcon#about to read 3, iclass 28, count 2 2006.182.07:20:18.85#ibcon#read 3, iclass 28, count 2 2006.182.07:20:18.85#ibcon#about to read 4, iclass 28, count 2 2006.182.07:20:18.85#ibcon#read 4, iclass 28, count 2 2006.182.07:20:18.85#ibcon#about to read 5, iclass 28, count 2 2006.182.07:20:18.85#ibcon#read 5, iclass 28, count 2 2006.182.07:20:18.85#ibcon#about to read 6, iclass 28, count 2 2006.182.07:20:18.85#ibcon#read 6, iclass 28, count 2 2006.182.07:20:18.85#ibcon#end of sib2, iclass 28, count 2 2006.182.07:20:18.85#ibcon#*after write, iclass 28, count 2 2006.182.07:20:18.85#ibcon#*before return 0, iclass 28, count 2 2006.182.07:20:18.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:20:18.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:20:18.85#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.07:20:18.85#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:18.85#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:20:18.97#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:20:18.97#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:20:18.97#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:20:18.97#ibcon#first serial, iclass 28, count 0 2006.182.07:20:18.97#ibcon#enter sib2, iclass 28, count 0 2006.182.07:20:18.97#ibcon#flushed, iclass 28, count 0 2006.182.07:20:18.97#ibcon#about to write, iclass 28, count 0 2006.182.07:20:18.97#ibcon#wrote, iclass 28, count 0 2006.182.07:20:18.97#ibcon#about to read 3, iclass 28, count 0 2006.182.07:20:18.99#ibcon#read 3, iclass 28, count 0 2006.182.07:20:18.99#ibcon#about to read 4, iclass 28, count 0 2006.182.07:20:18.99#ibcon#read 4, iclass 28, count 0 2006.182.07:20:18.99#ibcon#about to read 5, iclass 28, count 0 2006.182.07:20:18.99#ibcon#read 5, iclass 28, count 0 2006.182.07:20:18.99#ibcon#about to read 6, iclass 28, count 0 2006.182.07:20:18.99#ibcon#read 6, iclass 28, count 0 2006.182.07:20:18.99#ibcon#end of sib2, iclass 28, count 0 2006.182.07:20:18.99#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:20:18.99#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:20:18.99#ibcon#[25=USB\r\n] 2006.182.07:20:18.99#ibcon#*before write, iclass 28, count 0 2006.182.07:20:18.99#ibcon#enter sib2, iclass 28, count 0 2006.182.07:20:18.99#ibcon#flushed, iclass 28, count 0 2006.182.07:20:18.99#ibcon#about to write, iclass 28, count 0 2006.182.07:20:18.99#ibcon#wrote, iclass 28, count 0 2006.182.07:20:18.99#ibcon#about to read 3, iclass 28, count 0 2006.182.07:20:19.02#ibcon#read 3, iclass 28, count 0 2006.182.07:20:19.02#ibcon#about to read 4, iclass 28, count 0 2006.182.07:20:19.02#ibcon#read 4, iclass 28, count 0 2006.182.07:20:19.02#ibcon#about to read 5, iclass 28, count 0 2006.182.07:20:19.02#ibcon#read 5, iclass 28, count 0 2006.182.07:20:19.02#ibcon#about to read 6, iclass 28, count 0 2006.182.07:20:19.02#ibcon#read 6, iclass 28, count 0 2006.182.07:20:19.02#ibcon#end of sib2, iclass 28, count 0 2006.182.07:20:19.02#ibcon#*after write, iclass 28, count 0 2006.182.07:20:19.02#ibcon#*before return 0, iclass 28, count 0 2006.182.07:20:19.02#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:20:19.02#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:20:19.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:20:19.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:20:19.02$vc4f8/valo=8,852.99 2006.182.07:20:19.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.07:20:19.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.07:20:19.03#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:19.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:20:19.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:20:19.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:20:19.03#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:20:19.03#ibcon#first serial, iclass 30, count 0 2006.182.07:20:19.03#ibcon#enter sib2, iclass 30, count 0 2006.182.07:20:19.03#ibcon#flushed, iclass 30, count 0 2006.182.07:20:19.03#ibcon#about to write, iclass 30, count 0 2006.182.07:20:19.03#ibcon#wrote, iclass 30, count 0 2006.182.07:20:19.03#ibcon#about to read 3, iclass 30, count 0 2006.182.07:20:19.04#ibcon#read 3, iclass 30, count 0 2006.182.07:20:19.04#ibcon#about to read 4, iclass 30, count 0 2006.182.07:20:19.04#ibcon#read 4, iclass 30, count 0 2006.182.07:20:19.04#ibcon#about to read 5, iclass 30, count 0 2006.182.07:20:19.04#ibcon#read 5, iclass 30, count 0 2006.182.07:20:19.04#ibcon#about to read 6, iclass 30, count 0 2006.182.07:20:19.04#ibcon#read 6, iclass 30, count 0 2006.182.07:20:19.04#ibcon#end of sib2, iclass 30, count 0 2006.182.07:20:19.04#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:20:19.04#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:20:19.04#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:20:19.04#ibcon#*before write, iclass 30, count 0 2006.182.07:20:19.04#ibcon#enter sib2, iclass 30, count 0 2006.182.07:20:19.04#ibcon#flushed, iclass 30, count 0 2006.182.07:20:19.04#ibcon#about to write, iclass 30, count 0 2006.182.07:20:19.04#ibcon#wrote, iclass 30, count 0 2006.182.07:20:19.04#ibcon#about to read 3, iclass 30, count 0 2006.182.07:20:19.08#ibcon#read 3, iclass 30, count 0 2006.182.07:20:19.08#ibcon#about to read 4, iclass 30, count 0 2006.182.07:20:19.08#ibcon#read 4, iclass 30, count 0 2006.182.07:20:19.08#ibcon#about to read 5, iclass 30, count 0 2006.182.07:20:19.08#ibcon#read 5, iclass 30, count 0 2006.182.07:20:19.08#ibcon#about to read 6, iclass 30, count 0 2006.182.07:20:19.08#ibcon#read 6, iclass 30, count 0 2006.182.07:20:19.08#ibcon#end of sib2, iclass 30, count 0 2006.182.07:20:19.08#ibcon#*after write, iclass 30, count 0 2006.182.07:20:19.08#ibcon#*before return 0, iclass 30, count 0 2006.182.07:20:19.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:20:19.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:20:19.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:20:19.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:20:19.09$vc4f8/va=8,7 2006.182.07:20:19.09#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.07:20:19.09#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.07:20:19.09#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:19.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:20:19.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:20:19.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:20:19.14#ibcon#enter wrdev, iclass 32, count 2 2006.182.07:20:19.14#ibcon#first serial, iclass 32, count 2 2006.182.07:20:19.14#ibcon#enter sib2, iclass 32, count 2 2006.182.07:20:19.14#ibcon#flushed, iclass 32, count 2 2006.182.07:20:19.14#ibcon#about to write, iclass 32, count 2 2006.182.07:20:19.14#ibcon#wrote, iclass 32, count 2 2006.182.07:20:19.14#ibcon#about to read 3, iclass 32, count 2 2006.182.07:20:19.15#ibcon#read 3, iclass 32, count 2 2006.182.07:20:19.15#ibcon#about to read 4, iclass 32, count 2 2006.182.07:20:19.15#ibcon#read 4, iclass 32, count 2 2006.182.07:20:19.15#ibcon#about to read 5, iclass 32, count 2 2006.182.07:20:19.15#ibcon#read 5, iclass 32, count 2 2006.182.07:20:19.15#ibcon#about to read 6, iclass 32, count 2 2006.182.07:20:19.15#ibcon#read 6, iclass 32, count 2 2006.182.07:20:19.15#ibcon#end of sib2, iclass 32, count 2 2006.182.07:20:19.15#ibcon#*mode == 0, iclass 32, count 2 2006.182.07:20:19.15#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.07:20:19.15#ibcon#[25=AT08-07\r\n] 2006.182.07:20:19.15#ibcon#*before write, iclass 32, count 2 2006.182.07:20:19.15#ibcon#enter sib2, iclass 32, count 2 2006.182.07:20:19.15#ibcon#flushed, iclass 32, count 2 2006.182.07:20:19.15#ibcon#about to write, iclass 32, count 2 2006.182.07:20:19.15#ibcon#wrote, iclass 32, count 2 2006.182.07:20:19.15#ibcon#about to read 3, iclass 32, count 2 2006.182.07:20:19.18#ibcon#read 3, iclass 32, count 2 2006.182.07:20:19.18#ibcon#about to read 4, iclass 32, count 2 2006.182.07:20:19.18#ibcon#read 4, iclass 32, count 2 2006.182.07:20:19.18#ibcon#about to read 5, iclass 32, count 2 2006.182.07:20:19.18#ibcon#read 5, iclass 32, count 2 2006.182.07:20:19.18#ibcon#about to read 6, iclass 32, count 2 2006.182.07:20:19.18#ibcon#read 6, iclass 32, count 2 2006.182.07:20:19.18#ibcon#end of sib2, iclass 32, count 2 2006.182.07:20:19.18#ibcon#*after write, iclass 32, count 2 2006.182.07:20:19.18#ibcon#*before return 0, iclass 32, count 2 2006.182.07:20:19.18#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:20:19.18#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:20:19.18#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.07:20:19.18#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:19.18#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:20:19.30#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:20:19.30#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:20:19.30#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:20:19.30#ibcon#first serial, iclass 32, count 0 2006.182.07:20:19.30#ibcon#enter sib2, iclass 32, count 0 2006.182.07:20:19.30#ibcon#flushed, iclass 32, count 0 2006.182.07:20:19.30#ibcon#about to write, iclass 32, count 0 2006.182.07:20:19.30#ibcon#wrote, iclass 32, count 0 2006.182.07:20:19.30#ibcon#about to read 3, iclass 32, count 0 2006.182.07:20:19.32#ibcon#read 3, iclass 32, count 0 2006.182.07:20:19.32#ibcon#about to read 4, iclass 32, count 0 2006.182.07:20:19.32#ibcon#read 4, iclass 32, count 0 2006.182.07:20:19.32#ibcon#about to read 5, iclass 32, count 0 2006.182.07:20:19.32#ibcon#read 5, iclass 32, count 0 2006.182.07:20:19.32#ibcon#about to read 6, iclass 32, count 0 2006.182.07:20:19.32#ibcon#read 6, iclass 32, count 0 2006.182.07:20:19.32#ibcon#end of sib2, iclass 32, count 0 2006.182.07:20:19.32#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:20:19.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:20:19.32#ibcon#[25=USB\r\n] 2006.182.07:20:19.32#ibcon#*before write, iclass 32, count 0 2006.182.07:20:19.32#ibcon#enter sib2, iclass 32, count 0 2006.182.07:20:19.32#ibcon#flushed, iclass 32, count 0 2006.182.07:20:19.32#ibcon#about to write, iclass 32, count 0 2006.182.07:20:19.32#ibcon#wrote, iclass 32, count 0 2006.182.07:20:19.32#ibcon#about to read 3, iclass 32, count 0 2006.182.07:20:19.35#ibcon#read 3, iclass 32, count 0 2006.182.07:20:19.35#ibcon#about to read 4, iclass 32, count 0 2006.182.07:20:19.35#ibcon#read 4, iclass 32, count 0 2006.182.07:20:19.35#ibcon#about to read 5, iclass 32, count 0 2006.182.07:20:19.35#ibcon#read 5, iclass 32, count 0 2006.182.07:20:19.35#ibcon#about to read 6, iclass 32, count 0 2006.182.07:20:19.35#ibcon#read 6, iclass 32, count 0 2006.182.07:20:19.35#ibcon#end of sib2, iclass 32, count 0 2006.182.07:20:19.35#ibcon#*after write, iclass 32, count 0 2006.182.07:20:19.35#ibcon#*before return 0, iclass 32, count 0 2006.182.07:20:19.35#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:20:19.35#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:20:19.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:20:19.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:20:19.35$vc4f8/vblo=1,632.99 2006.182.07:20:19.36#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.07:20:19.36#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.07:20:19.36#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:19.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:20:19.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:20:19.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:20:19.36#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:20:19.36#ibcon#first serial, iclass 34, count 0 2006.182.07:20:19.36#ibcon#enter sib2, iclass 34, count 0 2006.182.07:20:19.36#ibcon#flushed, iclass 34, count 0 2006.182.07:20:19.36#ibcon#about to write, iclass 34, count 0 2006.182.07:20:19.36#ibcon#wrote, iclass 34, count 0 2006.182.07:20:19.36#ibcon#about to read 3, iclass 34, count 0 2006.182.07:20:19.37#ibcon#read 3, iclass 34, count 0 2006.182.07:20:19.37#ibcon#about to read 4, iclass 34, count 0 2006.182.07:20:19.37#ibcon#read 4, iclass 34, count 0 2006.182.07:20:19.37#ibcon#about to read 5, iclass 34, count 0 2006.182.07:20:19.37#ibcon#read 5, iclass 34, count 0 2006.182.07:20:19.37#ibcon#about to read 6, iclass 34, count 0 2006.182.07:20:19.37#ibcon#read 6, iclass 34, count 0 2006.182.07:20:19.37#ibcon#end of sib2, iclass 34, count 0 2006.182.07:20:19.37#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:20:19.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:20:19.37#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:20:19.37#ibcon#*before write, iclass 34, count 0 2006.182.07:20:19.37#ibcon#enter sib2, iclass 34, count 0 2006.182.07:20:19.37#ibcon#flushed, iclass 34, count 0 2006.182.07:20:19.37#ibcon#about to write, iclass 34, count 0 2006.182.07:20:19.37#ibcon#wrote, iclass 34, count 0 2006.182.07:20:19.37#ibcon#about to read 3, iclass 34, count 0 2006.182.07:20:19.43#ibcon#read 3, iclass 34, count 0 2006.182.07:20:19.43#ibcon#about to read 4, iclass 34, count 0 2006.182.07:20:19.43#ibcon#read 4, iclass 34, count 0 2006.182.07:20:19.43#ibcon#about to read 5, iclass 34, count 0 2006.182.07:20:19.43#ibcon#read 5, iclass 34, count 0 2006.182.07:20:19.43#ibcon#about to read 6, iclass 34, count 0 2006.182.07:20:19.43#ibcon#read 6, iclass 34, count 0 2006.182.07:20:19.43#ibcon#end of sib2, iclass 34, count 0 2006.182.07:20:19.43#ibcon#*after write, iclass 34, count 0 2006.182.07:20:19.43#ibcon#*before return 0, iclass 34, count 0 2006.182.07:20:19.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:20:19.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:20:19.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:20:19.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:20:19.43$vc4f8/vb=1,4 2006.182.07:20:19.44#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.182.07:20:19.44#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.182.07:20:19.44#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:19.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:20:19.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:20:19.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:20:19.44#ibcon#enter wrdev, iclass 36, count 2 2006.182.07:20:19.44#ibcon#first serial, iclass 36, count 2 2006.182.07:20:19.44#ibcon#enter sib2, iclass 36, count 2 2006.182.07:20:19.44#ibcon#flushed, iclass 36, count 2 2006.182.07:20:19.44#ibcon#about to write, iclass 36, count 2 2006.182.07:20:19.44#ibcon#wrote, iclass 36, count 2 2006.182.07:20:19.44#ibcon#about to read 3, iclass 36, count 2 2006.182.07:20:19.45#ibcon#read 3, iclass 36, count 2 2006.182.07:20:19.45#ibcon#about to read 4, iclass 36, count 2 2006.182.07:20:19.45#ibcon#read 4, iclass 36, count 2 2006.182.07:20:19.45#ibcon#about to read 5, iclass 36, count 2 2006.182.07:20:19.45#ibcon#read 5, iclass 36, count 2 2006.182.07:20:19.45#ibcon#about to read 6, iclass 36, count 2 2006.182.07:20:19.45#ibcon#read 6, iclass 36, count 2 2006.182.07:20:19.45#ibcon#end of sib2, iclass 36, count 2 2006.182.07:20:19.45#ibcon#*mode == 0, iclass 36, count 2 2006.182.07:20:19.45#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.182.07:20:19.45#ibcon#[27=AT01-04\r\n] 2006.182.07:20:19.45#ibcon#*before write, iclass 36, count 2 2006.182.07:20:19.45#ibcon#enter sib2, iclass 36, count 2 2006.182.07:20:19.45#ibcon#flushed, iclass 36, count 2 2006.182.07:20:19.45#ibcon#about to write, iclass 36, count 2 2006.182.07:20:19.45#ibcon#wrote, iclass 36, count 2 2006.182.07:20:19.45#ibcon#about to read 3, iclass 36, count 2 2006.182.07:20:19.49#ibcon#read 3, iclass 36, count 2 2006.182.07:20:19.49#ibcon#about to read 4, iclass 36, count 2 2006.182.07:20:19.49#ibcon#read 4, iclass 36, count 2 2006.182.07:20:19.49#ibcon#about to read 5, iclass 36, count 2 2006.182.07:20:19.49#ibcon#read 5, iclass 36, count 2 2006.182.07:20:19.49#ibcon#about to read 6, iclass 36, count 2 2006.182.07:20:19.49#ibcon#read 6, iclass 36, count 2 2006.182.07:20:19.49#ibcon#end of sib2, iclass 36, count 2 2006.182.07:20:19.49#ibcon#*after write, iclass 36, count 2 2006.182.07:20:19.49#ibcon#*before return 0, iclass 36, count 2 2006.182.07:20:19.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:20:19.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:20:19.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.182.07:20:19.49#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:19.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:20:19.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:20:19.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:20:19.61#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:20:19.61#ibcon#first serial, iclass 36, count 0 2006.182.07:20:19.61#ibcon#enter sib2, iclass 36, count 0 2006.182.07:20:19.61#ibcon#flushed, iclass 36, count 0 2006.182.07:20:19.61#ibcon#about to write, iclass 36, count 0 2006.182.07:20:19.61#ibcon#wrote, iclass 36, count 0 2006.182.07:20:19.61#ibcon#about to read 3, iclass 36, count 0 2006.182.07:20:19.63#ibcon#read 3, iclass 36, count 0 2006.182.07:20:19.63#ibcon#about to read 4, iclass 36, count 0 2006.182.07:20:19.63#ibcon#read 4, iclass 36, count 0 2006.182.07:20:19.63#ibcon#about to read 5, iclass 36, count 0 2006.182.07:20:19.63#ibcon#read 5, iclass 36, count 0 2006.182.07:20:19.63#ibcon#about to read 6, iclass 36, count 0 2006.182.07:20:19.63#ibcon#read 6, iclass 36, count 0 2006.182.07:20:19.63#ibcon#end of sib2, iclass 36, count 0 2006.182.07:20:19.63#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:20:19.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:20:19.63#ibcon#[27=USB\r\n] 2006.182.07:20:19.63#ibcon#*before write, iclass 36, count 0 2006.182.07:20:19.63#ibcon#enter sib2, iclass 36, count 0 2006.182.07:20:19.63#ibcon#flushed, iclass 36, count 0 2006.182.07:20:19.63#ibcon#about to write, iclass 36, count 0 2006.182.07:20:19.63#ibcon#wrote, iclass 36, count 0 2006.182.07:20:19.63#ibcon#about to read 3, iclass 36, count 0 2006.182.07:20:19.66#ibcon#read 3, iclass 36, count 0 2006.182.07:20:19.66#ibcon#about to read 4, iclass 36, count 0 2006.182.07:20:19.66#ibcon#read 4, iclass 36, count 0 2006.182.07:20:19.66#ibcon#about to read 5, iclass 36, count 0 2006.182.07:20:19.66#ibcon#read 5, iclass 36, count 0 2006.182.07:20:19.66#ibcon#about to read 6, iclass 36, count 0 2006.182.07:20:19.66#ibcon#read 6, iclass 36, count 0 2006.182.07:20:19.66#ibcon#end of sib2, iclass 36, count 0 2006.182.07:20:19.66#ibcon#*after write, iclass 36, count 0 2006.182.07:20:19.66#ibcon#*before return 0, iclass 36, count 0 2006.182.07:20:19.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:20:19.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:20:19.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:20:19.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:20:19.66$vc4f8/vblo=2,640.99 2006.182.07:20:19.67#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.07:20:19.67#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.07:20:19.67#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:19.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:19.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:19.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:19.67#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:20:19.67#ibcon#first serial, iclass 38, count 0 2006.182.07:20:19.67#ibcon#enter sib2, iclass 38, count 0 2006.182.07:20:19.67#ibcon#flushed, iclass 38, count 0 2006.182.07:20:19.67#ibcon#about to write, iclass 38, count 0 2006.182.07:20:19.67#ibcon#wrote, iclass 38, count 0 2006.182.07:20:19.67#ibcon#about to read 3, iclass 38, count 0 2006.182.07:20:19.68#ibcon#read 3, iclass 38, count 0 2006.182.07:20:19.68#ibcon#about to read 4, iclass 38, count 0 2006.182.07:20:19.68#ibcon#read 4, iclass 38, count 0 2006.182.07:20:19.68#ibcon#about to read 5, iclass 38, count 0 2006.182.07:20:19.68#ibcon#read 5, iclass 38, count 0 2006.182.07:20:19.68#ibcon#about to read 6, iclass 38, count 0 2006.182.07:20:19.68#ibcon#read 6, iclass 38, count 0 2006.182.07:20:19.68#ibcon#end of sib2, iclass 38, count 0 2006.182.07:20:19.68#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:20:19.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:20:19.68#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:20:19.68#ibcon#*before write, iclass 38, count 0 2006.182.07:20:19.68#ibcon#enter sib2, iclass 38, count 0 2006.182.07:20:19.68#ibcon#flushed, iclass 38, count 0 2006.182.07:20:19.68#ibcon#about to write, iclass 38, count 0 2006.182.07:20:19.68#ibcon#wrote, iclass 38, count 0 2006.182.07:20:19.68#ibcon#about to read 3, iclass 38, count 0 2006.182.07:20:19.72#ibcon#read 3, iclass 38, count 0 2006.182.07:20:19.72#ibcon#about to read 4, iclass 38, count 0 2006.182.07:20:19.72#ibcon#read 4, iclass 38, count 0 2006.182.07:20:19.72#ibcon#about to read 5, iclass 38, count 0 2006.182.07:20:19.72#ibcon#read 5, iclass 38, count 0 2006.182.07:20:19.72#ibcon#about to read 6, iclass 38, count 0 2006.182.07:20:19.72#ibcon#read 6, iclass 38, count 0 2006.182.07:20:19.72#ibcon#end of sib2, iclass 38, count 0 2006.182.07:20:19.72#ibcon#*after write, iclass 38, count 0 2006.182.07:20:19.72#ibcon#*before return 0, iclass 38, count 0 2006.182.07:20:19.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:19.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:20:19.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:20:19.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:20:19.72$vc4f8/vb=2,4 2006.182.07:20:19.73#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.07:20:19.73#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.07:20:19.73#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:19.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:19.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:19.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:19.77#ibcon#enter wrdev, iclass 40, count 2 2006.182.07:20:19.77#ibcon#first serial, iclass 40, count 2 2006.182.07:20:19.77#ibcon#enter sib2, iclass 40, count 2 2006.182.07:20:19.77#ibcon#flushed, iclass 40, count 2 2006.182.07:20:19.77#ibcon#about to write, iclass 40, count 2 2006.182.07:20:19.77#ibcon#wrote, iclass 40, count 2 2006.182.07:20:19.77#ibcon#about to read 3, iclass 40, count 2 2006.182.07:20:19.79#ibcon#read 3, iclass 40, count 2 2006.182.07:20:19.79#ibcon#about to read 4, iclass 40, count 2 2006.182.07:20:19.79#ibcon#read 4, iclass 40, count 2 2006.182.07:20:19.79#ibcon#about to read 5, iclass 40, count 2 2006.182.07:20:19.79#ibcon#read 5, iclass 40, count 2 2006.182.07:20:19.79#ibcon#about to read 6, iclass 40, count 2 2006.182.07:20:19.79#ibcon#read 6, iclass 40, count 2 2006.182.07:20:19.79#ibcon#end of sib2, iclass 40, count 2 2006.182.07:20:19.79#ibcon#*mode == 0, iclass 40, count 2 2006.182.07:20:19.79#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.07:20:19.79#ibcon#[27=AT02-04\r\n] 2006.182.07:20:19.79#ibcon#*before write, iclass 40, count 2 2006.182.07:20:19.79#ibcon#enter sib2, iclass 40, count 2 2006.182.07:20:19.79#ibcon#flushed, iclass 40, count 2 2006.182.07:20:19.79#ibcon#about to write, iclass 40, count 2 2006.182.07:20:19.79#ibcon#wrote, iclass 40, count 2 2006.182.07:20:19.79#ibcon#about to read 3, iclass 40, count 2 2006.182.07:20:19.82#ibcon#read 3, iclass 40, count 2 2006.182.07:20:19.82#ibcon#about to read 4, iclass 40, count 2 2006.182.07:20:19.82#ibcon#read 4, iclass 40, count 2 2006.182.07:20:19.82#ibcon#about to read 5, iclass 40, count 2 2006.182.07:20:19.82#ibcon#read 5, iclass 40, count 2 2006.182.07:20:19.82#ibcon#about to read 6, iclass 40, count 2 2006.182.07:20:19.82#ibcon#read 6, iclass 40, count 2 2006.182.07:20:19.82#ibcon#end of sib2, iclass 40, count 2 2006.182.07:20:19.82#ibcon#*after write, iclass 40, count 2 2006.182.07:20:19.82#ibcon#*before return 0, iclass 40, count 2 2006.182.07:20:19.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:19.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:20:19.82#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.07:20:19.82#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:19.82#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:19.94#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:19.94#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:19.94#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:20:19.94#ibcon#first serial, iclass 40, count 0 2006.182.07:20:19.94#ibcon#enter sib2, iclass 40, count 0 2006.182.07:20:19.94#ibcon#flushed, iclass 40, count 0 2006.182.07:20:19.94#ibcon#about to write, iclass 40, count 0 2006.182.07:20:19.94#ibcon#wrote, iclass 40, count 0 2006.182.07:20:19.94#ibcon#about to read 3, iclass 40, count 0 2006.182.07:20:19.96#ibcon#read 3, iclass 40, count 0 2006.182.07:20:19.96#ibcon#about to read 4, iclass 40, count 0 2006.182.07:20:19.96#ibcon#read 4, iclass 40, count 0 2006.182.07:20:19.96#ibcon#about to read 5, iclass 40, count 0 2006.182.07:20:19.96#ibcon#read 5, iclass 40, count 0 2006.182.07:20:19.96#ibcon#about to read 6, iclass 40, count 0 2006.182.07:20:19.96#ibcon#read 6, iclass 40, count 0 2006.182.07:20:19.96#ibcon#end of sib2, iclass 40, count 0 2006.182.07:20:19.96#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:20:19.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:20:19.96#ibcon#[27=USB\r\n] 2006.182.07:20:19.96#ibcon#*before write, iclass 40, count 0 2006.182.07:20:19.96#ibcon#enter sib2, iclass 40, count 0 2006.182.07:20:19.96#ibcon#flushed, iclass 40, count 0 2006.182.07:20:19.96#ibcon#about to write, iclass 40, count 0 2006.182.07:20:19.96#ibcon#wrote, iclass 40, count 0 2006.182.07:20:19.96#ibcon#about to read 3, iclass 40, count 0 2006.182.07:20:19.99#ibcon#read 3, iclass 40, count 0 2006.182.07:20:19.99#ibcon#about to read 4, iclass 40, count 0 2006.182.07:20:19.99#ibcon#read 4, iclass 40, count 0 2006.182.07:20:19.99#ibcon#about to read 5, iclass 40, count 0 2006.182.07:20:19.99#ibcon#read 5, iclass 40, count 0 2006.182.07:20:19.99#ibcon#about to read 6, iclass 40, count 0 2006.182.07:20:19.99#ibcon#read 6, iclass 40, count 0 2006.182.07:20:19.99#ibcon#end of sib2, iclass 40, count 0 2006.182.07:20:19.99#ibcon#*after write, iclass 40, count 0 2006.182.07:20:19.99#ibcon#*before return 0, iclass 40, count 0 2006.182.07:20:19.99#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:19.99#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:20:19.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:20:19.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:20:19.99$vc4f8/vblo=3,656.99 2006.182.07:20:20.00#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.07:20:20.00#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.07:20:20.00#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:20.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:20.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:20.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:20.00#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:20:20.00#ibcon#first serial, iclass 4, count 0 2006.182.07:20:20.00#ibcon#enter sib2, iclass 4, count 0 2006.182.07:20:20.00#ibcon#flushed, iclass 4, count 0 2006.182.07:20:20.00#ibcon#about to write, iclass 4, count 0 2006.182.07:20:20.00#ibcon#wrote, iclass 4, count 0 2006.182.07:20:20.00#ibcon#about to read 3, iclass 4, count 0 2006.182.07:20:20.01#ibcon#read 3, iclass 4, count 0 2006.182.07:20:20.01#ibcon#about to read 4, iclass 4, count 0 2006.182.07:20:20.01#ibcon#read 4, iclass 4, count 0 2006.182.07:20:20.01#ibcon#about to read 5, iclass 4, count 0 2006.182.07:20:20.01#ibcon#read 5, iclass 4, count 0 2006.182.07:20:20.01#ibcon#about to read 6, iclass 4, count 0 2006.182.07:20:20.01#ibcon#read 6, iclass 4, count 0 2006.182.07:20:20.01#ibcon#end of sib2, iclass 4, count 0 2006.182.07:20:20.01#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:20:20.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:20:20.01#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:20:20.01#ibcon#*before write, iclass 4, count 0 2006.182.07:20:20.01#ibcon#enter sib2, iclass 4, count 0 2006.182.07:20:20.01#ibcon#flushed, iclass 4, count 0 2006.182.07:20:20.01#ibcon#about to write, iclass 4, count 0 2006.182.07:20:20.01#ibcon#wrote, iclass 4, count 0 2006.182.07:20:20.01#ibcon#about to read 3, iclass 4, count 0 2006.182.07:20:20.05#ibcon#read 3, iclass 4, count 0 2006.182.07:20:20.05#ibcon#about to read 4, iclass 4, count 0 2006.182.07:20:20.05#ibcon#read 4, iclass 4, count 0 2006.182.07:20:20.05#ibcon#about to read 5, iclass 4, count 0 2006.182.07:20:20.05#ibcon#read 5, iclass 4, count 0 2006.182.07:20:20.05#ibcon#about to read 6, iclass 4, count 0 2006.182.07:20:20.05#ibcon#read 6, iclass 4, count 0 2006.182.07:20:20.05#ibcon#end of sib2, iclass 4, count 0 2006.182.07:20:20.05#ibcon#*after write, iclass 4, count 0 2006.182.07:20:20.05#ibcon#*before return 0, iclass 4, count 0 2006.182.07:20:20.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:20.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:20:20.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:20:20.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:20:20.06$vc4f8/vb=3,4 2006.182.07:20:20.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.07:20:20.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.07:20:20.06#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:20.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:20.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:20.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:20.10#ibcon#enter wrdev, iclass 6, count 2 2006.182.07:20:20.10#ibcon#first serial, iclass 6, count 2 2006.182.07:20:20.10#ibcon#enter sib2, iclass 6, count 2 2006.182.07:20:20.10#ibcon#flushed, iclass 6, count 2 2006.182.07:20:20.10#ibcon#about to write, iclass 6, count 2 2006.182.07:20:20.10#ibcon#wrote, iclass 6, count 2 2006.182.07:20:20.10#ibcon#about to read 3, iclass 6, count 2 2006.182.07:20:20.12#ibcon#read 3, iclass 6, count 2 2006.182.07:20:20.12#ibcon#about to read 4, iclass 6, count 2 2006.182.07:20:20.12#ibcon#read 4, iclass 6, count 2 2006.182.07:20:20.12#ibcon#about to read 5, iclass 6, count 2 2006.182.07:20:20.12#ibcon#read 5, iclass 6, count 2 2006.182.07:20:20.12#ibcon#about to read 6, iclass 6, count 2 2006.182.07:20:20.12#ibcon#read 6, iclass 6, count 2 2006.182.07:20:20.12#ibcon#end of sib2, iclass 6, count 2 2006.182.07:20:20.12#ibcon#*mode == 0, iclass 6, count 2 2006.182.07:20:20.12#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.07:20:20.12#ibcon#[27=AT03-04\r\n] 2006.182.07:20:20.12#ibcon#*before write, iclass 6, count 2 2006.182.07:20:20.12#ibcon#enter sib2, iclass 6, count 2 2006.182.07:20:20.12#ibcon#flushed, iclass 6, count 2 2006.182.07:20:20.12#ibcon#about to write, iclass 6, count 2 2006.182.07:20:20.12#ibcon#wrote, iclass 6, count 2 2006.182.07:20:20.12#ibcon#about to read 3, iclass 6, count 2 2006.182.07:20:20.15#ibcon#read 3, iclass 6, count 2 2006.182.07:20:20.15#ibcon#about to read 4, iclass 6, count 2 2006.182.07:20:20.15#ibcon#read 4, iclass 6, count 2 2006.182.07:20:20.15#ibcon#about to read 5, iclass 6, count 2 2006.182.07:20:20.15#ibcon#read 5, iclass 6, count 2 2006.182.07:20:20.15#ibcon#about to read 6, iclass 6, count 2 2006.182.07:20:20.15#ibcon#read 6, iclass 6, count 2 2006.182.07:20:20.15#ibcon#end of sib2, iclass 6, count 2 2006.182.07:20:20.15#ibcon#*after write, iclass 6, count 2 2006.182.07:20:20.15#ibcon#*before return 0, iclass 6, count 2 2006.182.07:20:20.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:20.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:20:20.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.07:20:20.15#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:20.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:20.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:20.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:20.27#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:20:20.27#ibcon#first serial, iclass 6, count 0 2006.182.07:20:20.27#ibcon#enter sib2, iclass 6, count 0 2006.182.07:20:20.27#ibcon#flushed, iclass 6, count 0 2006.182.07:20:20.27#ibcon#about to write, iclass 6, count 0 2006.182.07:20:20.27#ibcon#wrote, iclass 6, count 0 2006.182.07:20:20.27#ibcon#about to read 3, iclass 6, count 0 2006.182.07:20:20.29#ibcon#read 3, iclass 6, count 0 2006.182.07:20:20.29#ibcon#about to read 4, iclass 6, count 0 2006.182.07:20:20.29#ibcon#read 4, iclass 6, count 0 2006.182.07:20:20.29#ibcon#about to read 5, iclass 6, count 0 2006.182.07:20:20.29#ibcon#read 5, iclass 6, count 0 2006.182.07:20:20.29#ibcon#about to read 6, iclass 6, count 0 2006.182.07:20:20.29#ibcon#read 6, iclass 6, count 0 2006.182.07:20:20.29#ibcon#end of sib2, iclass 6, count 0 2006.182.07:20:20.29#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:20:20.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:20:20.29#ibcon#[27=USB\r\n] 2006.182.07:20:20.29#ibcon#*before write, iclass 6, count 0 2006.182.07:20:20.29#ibcon#enter sib2, iclass 6, count 0 2006.182.07:20:20.29#ibcon#flushed, iclass 6, count 0 2006.182.07:20:20.29#ibcon#about to write, iclass 6, count 0 2006.182.07:20:20.29#ibcon#wrote, iclass 6, count 0 2006.182.07:20:20.29#ibcon#about to read 3, iclass 6, count 0 2006.182.07:20:20.32#ibcon#read 3, iclass 6, count 0 2006.182.07:20:20.32#ibcon#about to read 4, iclass 6, count 0 2006.182.07:20:20.32#ibcon#read 4, iclass 6, count 0 2006.182.07:20:20.32#ibcon#about to read 5, iclass 6, count 0 2006.182.07:20:20.32#ibcon#read 5, iclass 6, count 0 2006.182.07:20:20.32#ibcon#about to read 6, iclass 6, count 0 2006.182.07:20:20.32#ibcon#read 6, iclass 6, count 0 2006.182.07:20:20.32#ibcon#end of sib2, iclass 6, count 0 2006.182.07:20:20.32#ibcon#*after write, iclass 6, count 0 2006.182.07:20:20.32#ibcon#*before return 0, iclass 6, count 0 2006.182.07:20:20.32#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:20.32#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:20:20.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:20:20.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:20:20.32$vc4f8/vblo=4,712.99 2006.182.07:20:20.33#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.07:20:20.33#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.07:20:20.33#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:20.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:20.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:20.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:20.33#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:20:20.33#ibcon#first serial, iclass 10, count 0 2006.182.07:20:20.33#ibcon#enter sib2, iclass 10, count 0 2006.182.07:20:20.33#ibcon#flushed, iclass 10, count 0 2006.182.07:20:20.33#ibcon#about to write, iclass 10, count 0 2006.182.07:20:20.33#ibcon#wrote, iclass 10, count 0 2006.182.07:20:20.33#ibcon#about to read 3, iclass 10, count 0 2006.182.07:20:20.34#ibcon#read 3, iclass 10, count 0 2006.182.07:20:20.34#ibcon#about to read 4, iclass 10, count 0 2006.182.07:20:20.34#ibcon#read 4, iclass 10, count 0 2006.182.07:20:20.34#ibcon#about to read 5, iclass 10, count 0 2006.182.07:20:20.34#ibcon#read 5, iclass 10, count 0 2006.182.07:20:20.34#ibcon#about to read 6, iclass 10, count 0 2006.182.07:20:20.34#ibcon#read 6, iclass 10, count 0 2006.182.07:20:20.34#ibcon#end of sib2, iclass 10, count 0 2006.182.07:20:20.34#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:20:20.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:20:20.34#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:20:20.34#ibcon#*before write, iclass 10, count 0 2006.182.07:20:20.34#ibcon#enter sib2, iclass 10, count 0 2006.182.07:20:20.34#ibcon#flushed, iclass 10, count 0 2006.182.07:20:20.34#ibcon#about to write, iclass 10, count 0 2006.182.07:20:20.34#ibcon#wrote, iclass 10, count 0 2006.182.07:20:20.34#ibcon#about to read 3, iclass 10, count 0 2006.182.07:20:20.38#ibcon#read 3, iclass 10, count 0 2006.182.07:20:20.38#ibcon#about to read 4, iclass 10, count 0 2006.182.07:20:20.38#ibcon#read 4, iclass 10, count 0 2006.182.07:20:20.38#ibcon#about to read 5, iclass 10, count 0 2006.182.07:20:20.38#ibcon#read 5, iclass 10, count 0 2006.182.07:20:20.38#ibcon#about to read 6, iclass 10, count 0 2006.182.07:20:20.38#ibcon#read 6, iclass 10, count 0 2006.182.07:20:20.38#ibcon#end of sib2, iclass 10, count 0 2006.182.07:20:20.38#ibcon#*after write, iclass 10, count 0 2006.182.07:20:20.38#ibcon#*before return 0, iclass 10, count 0 2006.182.07:20:20.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:20.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:20:20.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:20:20.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:20:20.38$vc4f8/vb=4,4 2006.182.07:20:20.39#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.07:20:20.39#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.07:20:20.39#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:20.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:20.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:20.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:20.44#ibcon#enter wrdev, iclass 12, count 2 2006.182.07:20:20.44#ibcon#first serial, iclass 12, count 2 2006.182.07:20:20.44#ibcon#enter sib2, iclass 12, count 2 2006.182.07:20:20.44#ibcon#flushed, iclass 12, count 2 2006.182.07:20:20.44#ibcon#about to write, iclass 12, count 2 2006.182.07:20:20.44#ibcon#wrote, iclass 12, count 2 2006.182.07:20:20.44#ibcon#about to read 3, iclass 12, count 2 2006.182.07:20:20.45#ibcon#read 3, iclass 12, count 2 2006.182.07:20:20.45#ibcon#about to read 4, iclass 12, count 2 2006.182.07:20:20.45#ibcon#read 4, iclass 12, count 2 2006.182.07:20:20.45#ibcon#about to read 5, iclass 12, count 2 2006.182.07:20:20.45#ibcon#read 5, iclass 12, count 2 2006.182.07:20:20.45#ibcon#about to read 6, iclass 12, count 2 2006.182.07:20:20.45#ibcon#read 6, iclass 12, count 2 2006.182.07:20:20.45#ibcon#end of sib2, iclass 12, count 2 2006.182.07:20:20.45#ibcon#*mode == 0, iclass 12, count 2 2006.182.07:20:20.45#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.07:20:20.45#ibcon#[27=AT04-04\r\n] 2006.182.07:20:20.45#ibcon#*before write, iclass 12, count 2 2006.182.07:20:20.45#ibcon#enter sib2, iclass 12, count 2 2006.182.07:20:20.45#ibcon#flushed, iclass 12, count 2 2006.182.07:20:20.45#ibcon#about to write, iclass 12, count 2 2006.182.07:20:20.45#ibcon#wrote, iclass 12, count 2 2006.182.07:20:20.45#ibcon#about to read 3, iclass 12, count 2 2006.182.07:20:20.48#ibcon#read 3, iclass 12, count 2 2006.182.07:20:20.48#ibcon#about to read 4, iclass 12, count 2 2006.182.07:20:20.48#ibcon#read 4, iclass 12, count 2 2006.182.07:20:20.48#ibcon#about to read 5, iclass 12, count 2 2006.182.07:20:20.48#ibcon#read 5, iclass 12, count 2 2006.182.07:20:20.48#ibcon#about to read 6, iclass 12, count 2 2006.182.07:20:20.48#ibcon#read 6, iclass 12, count 2 2006.182.07:20:20.48#ibcon#end of sib2, iclass 12, count 2 2006.182.07:20:20.48#ibcon#*after write, iclass 12, count 2 2006.182.07:20:20.48#ibcon#*before return 0, iclass 12, count 2 2006.182.07:20:20.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:20.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:20:20.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.07:20:20.48#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:20.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:20.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:20.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:20.60#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:20:20.60#ibcon#first serial, iclass 12, count 0 2006.182.07:20:20.60#ibcon#enter sib2, iclass 12, count 0 2006.182.07:20:20.60#ibcon#flushed, iclass 12, count 0 2006.182.07:20:20.60#ibcon#about to write, iclass 12, count 0 2006.182.07:20:20.60#ibcon#wrote, iclass 12, count 0 2006.182.07:20:20.60#ibcon#about to read 3, iclass 12, count 0 2006.182.07:20:20.62#ibcon#read 3, iclass 12, count 0 2006.182.07:20:20.62#ibcon#about to read 4, iclass 12, count 0 2006.182.07:20:20.62#ibcon#read 4, iclass 12, count 0 2006.182.07:20:20.62#ibcon#about to read 5, iclass 12, count 0 2006.182.07:20:20.62#ibcon#read 5, iclass 12, count 0 2006.182.07:20:20.62#ibcon#about to read 6, iclass 12, count 0 2006.182.07:20:20.62#ibcon#read 6, iclass 12, count 0 2006.182.07:20:20.62#ibcon#end of sib2, iclass 12, count 0 2006.182.07:20:20.62#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:20:20.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:20:20.62#ibcon#[27=USB\r\n] 2006.182.07:20:20.62#ibcon#*before write, iclass 12, count 0 2006.182.07:20:20.62#ibcon#enter sib2, iclass 12, count 0 2006.182.07:20:20.62#ibcon#flushed, iclass 12, count 0 2006.182.07:20:20.62#ibcon#about to write, iclass 12, count 0 2006.182.07:20:20.62#ibcon#wrote, iclass 12, count 0 2006.182.07:20:20.62#ibcon#about to read 3, iclass 12, count 0 2006.182.07:20:20.65#ibcon#read 3, iclass 12, count 0 2006.182.07:20:20.65#ibcon#about to read 4, iclass 12, count 0 2006.182.07:20:20.65#ibcon#read 4, iclass 12, count 0 2006.182.07:20:20.65#ibcon#about to read 5, iclass 12, count 0 2006.182.07:20:20.65#ibcon#read 5, iclass 12, count 0 2006.182.07:20:20.65#ibcon#about to read 6, iclass 12, count 0 2006.182.07:20:20.65#ibcon#read 6, iclass 12, count 0 2006.182.07:20:20.65#ibcon#end of sib2, iclass 12, count 0 2006.182.07:20:20.65#ibcon#*after write, iclass 12, count 0 2006.182.07:20:20.65#ibcon#*before return 0, iclass 12, count 0 2006.182.07:20:20.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:20.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:20:20.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:20:20.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:20:20.65$vc4f8/vblo=5,744.99 2006.182.07:20:20.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.07:20:20.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.07:20:20.66#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:20.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:20.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:20.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:20.66#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:20:20.66#ibcon#first serial, iclass 14, count 0 2006.182.07:20:20.66#ibcon#enter sib2, iclass 14, count 0 2006.182.07:20:20.66#ibcon#flushed, iclass 14, count 0 2006.182.07:20:20.66#ibcon#about to write, iclass 14, count 0 2006.182.07:20:20.66#ibcon#wrote, iclass 14, count 0 2006.182.07:20:20.66#ibcon#about to read 3, iclass 14, count 0 2006.182.07:20:20.67#ibcon#read 3, iclass 14, count 0 2006.182.07:20:20.67#ibcon#about to read 4, iclass 14, count 0 2006.182.07:20:20.67#ibcon#read 4, iclass 14, count 0 2006.182.07:20:20.67#ibcon#about to read 5, iclass 14, count 0 2006.182.07:20:20.67#ibcon#read 5, iclass 14, count 0 2006.182.07:20:20.67#ibcon#about to read 6, iclass 14, count 0 2006.182.07:20:20.67#ibcon#read 6, iclass 14, count 0 2006.182.07:20:20.67#ibcon#end of sib2, iclass 14, count 0 2006.182.07:20:20.67#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:20:20.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:20:20.67#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:20:20.67#ibcon#*before write, iclass 14, count 0 2006.182.07:20:20.67#ibcon#enter sib2, iclass 14, count 0 2006.182.07:20:20.67#ibcon#flushed, iclass 14, count 0 2006.182.07:20:20.67#ibcon#about to write, iclass 14, count 0 2006.182.07:20:20.67#ibcon#wrote, iclass 14, count 0 2006.182.07:20:20.67#ibcon#about to read 3, iclass 14, count 0 2006.182.07:20:20.71#ibcon#read 3, iclass 14, count 0 2006.182.07:20:20.71#ibcon#about to read 4, iclass 14, count 0 2006.182.07:20:20.71#ibcon#read 4, iclass 14, count 0 2006.182.07:20:20.71#ibcon#about to read 5, iclass 14, count 0 2006.182.07:20:20.71#ibcon#read 5, iclass 14, count 0 2006.182.07:20:20.71#ibcon#about to read 6, iclass 14, count 0 2006.182.07:20:20.71#ibcon#read 6, iclass 14, count 0 2006.182.07:20:20.71#ibcon#end of sib2, iclass 14, count 0 2006.182.07:20:20.71#ibcon#*after write, iclass 14, count 0 2006.182.07:20:20.71#ibcon#*before return 0, iclass 14, count 0 2006.182.07:20:20.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:20.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:20:20.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:20:20.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:20:20.72$vc4f8/vb=5,4 2006.182.07:20:20.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.07:20:20.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.07:20:20.72#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:20.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:20.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:20.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:20.76#ibcon#enter wrdev, iclass 16, count 2 2006.182.07:20:20.76#ibcon#first serial, iclass 16, count 2 2006.182.07:20:20.76#ibcon#enter sib2, iclass 16, count 2 2006.182.07:20:20.76#ibcon#flushed, iclass 16, count 2 2006.182.07:20:20.76#ibcon#about to write, iclass 16, count 2 2006.182.07:20:20.76#ibcon#wrote, iclass 16, count 2 2006.182.07:20:20.76#ibcon#about to read 3, iclass 16, count 2 2006.182.07:20:20.78#ibcon#read 3, iclass 16, count 2 2006.182.07:20:20.78#ibcon#about to read 4, iclass 16, count 2 2006.182.07:20:20.78#ibcon#read 4, iclass 16, count 2 2006.182.07:20:20.78#ibcon#about to read 5, iclass 16, count 2 2006.182.07:20:20.78#ibcon#read 5, iclass 16, count 2 2006.182.07:20:20.78#ibcon#about to read 6, iclass 16, count 2 2006.182.07:20:20.78#ibcon#read 6, iclass 16, count 2 2006.182.07:20:20.78#ibcon#end of sib2, iclass 16, count 2 2006.182.07:20:20.78#ibcon#*mode == 0, iclass 16, count 2 2006.182.07:20:20.78#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.07:20:20.78#ibcon#[27=AT05-04\r\n] 2006.182.07:20:20.78#ibcon#*before write, iclass 16, count 2 2006.182.07:20:20.78#ibcon#enter sib2, iclass 16, count 2 2006.182.07:20:20.78#ibcon#flushed, iclass 16, count 2 2006.182.07:20:20.78#ibcon#about to write, iclass 16, count 2 2006.182.07:20:20.78#ibcon#wrote, iclass 16, count 2 2006.182.07:20:20.78#ibcon#about to read 3, iclass 16, count 2 2006.182.07:20:20.81#ibcon#read 3, iclass 16, count 2 2006.182.07:20:20.81#ibcon#about to read 4, iclass 16, count 2 2006.182.07:20:20.81#ibcon#read 4, iclass 16, count 2 2006.182.07:20:20.81#ibcon#about to read 5, iclass 16, count 2 2006.182.07:20:20.81#ibcon#read 5, iclass 16, count 2 2006.182.07:20:20.81#ibcon#about to read 6, iclass 16, count 2 2006.182.07:20:20.81#ibcon#read 6, iclass 16, count 2 2006.182.07:20:20.81#ibcon#end of sib2, iclass 16, count 2 2006.182.07:20:20.81#ibcon#*after write, iclass 16, count 2 2006.182.07:20:20.81#ibcon#*before return 0, iclass 16, count 2 2006.182.07:20:20.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:20.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:20:20.81#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.07:20:20.81#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:20.81#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:20.93#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:20.93#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:20.93#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:20:20.93#ibcon#first serial, iclass 16, count 0 2006.182.07:20:20.93#ibcon#enter sib2, iclass 16, count 0 2006.182.07:20:20.93#ibcon#flushed, iclass 16, count 0 2006.182.07:20:20.93#ibcon#about to write, iclass 16, count 0 2006.182.07:20:20.93#ibcon#wrote, iclass 16, count 0 2006.182.07:20:20.93#ibcon#about to read 3, iclass 16, count 0 2006.182.07:20:20.95#ibcon#read 3, iclass 16, count 0 2006.182.07:20:20.95#ibcon#about to read 4, iclass 16, count 0 2006.182.07:20:20.95#ibcon#read 4, iclass 16, count 0 2006.182.07:20:20.95#ibcon#about to read 5, iclass 16, count 0 2006.182.07:20:20.95#ibcon#read 5, iclass 16, count 0 2006.182.07:20:20.95#ibcon#about to read 6, iclass 16, count 0 2006.182.07:20:20.95#ibcon#read 6, iclass 16, count 0 2006.182.07:20:20.95#ibcon#end of sib2, iclass 16, count 0 2006.182.07:20:20.95#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:20:20.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:20:20.95#ibcon#[27=USB\r\n] 2006.182.07:20:20.95#ibcon#*before write, iclass 16, count 0 2006.182.07:20:20.95#ibcon#enter sib2, iclass 16, count 0 2006.182.07:20:20.95#ibcon#flushed, iclass 16, count 0 2006.182.07:20:20.95#ibcon#about to write, iclass 16, count 0 2006.182.07:20:20.95#ibcon#wrote, iclass 16, count 0 2006.182.07:20:20.95#ibcon#about to read 3, iclass 16, count 0 2006.182.07:20:20.98#ibcon#read 3, iclass 16, count 0 2006.182.07:20:20.98#ibcon#about to read 4, iclass 16, count 0 2006.182.07:20:20.98#ibcon#read 4, iclass 16, count 0 2006.182.07:20:20.98#ibcon#about to read 5, iclass 16, count 0 2006.182.07:20:20.98#ibcon#read 5, iclass 16, count 0 2006.182.07:20:20.98#ibcon#about to read 6, iclass 16, count 0 2006.182.07:20:20.98#ibcon#read 6, iclass 16, count 0 2006.182.07:20:20.98#ibcon#end of sib2, iclass 16, count 0 2006.182.07:20:20.98#ibcon#*after write, iclass 16, count 0 2006.182.07:20:20.98#ibcon#*before return 0, iclass 16, count 0 2006.182.07:20:20.98#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:20.98#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:20:20.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:20:20.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:20:20.98$vc4f8/vblo=6,752.99 2006.182.07:20:20.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.07:20:20.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.07:20:20.99#ibcon#ireg 17 cls_cnt 0 2006.182.07:20:20.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:20.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:20.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:20.99#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:20:20.99#ibcon#first serial, iclass 18, count 0 2006.182.07:20:20.99#ibcon#enter sib2, iclass 18, count 0 2006.182.07:20:20.99#ibcon#flushed, iclass 18, count 0 2006.182.07:20:20.99#ibcon#about to write, iclass 18, count 0 2006.182.07:20:20.99#ibcon#wrote, iclass 18, count 0 2006.182.07:20:20.99#ibcon#about to read 3, iclass 18, count 0 2006.182.07:20:21.00#ibcon#read 3, iclass 18, count 0 2006.182.07:20:21.00#ibcon#about to read 4, iclass 18, count 0 2006.182.07:20:21.00#ibcon#read 4, iclass 18, count 0 2006.182.07:20:21.00#ibcon#about to read 5, iclass 18, count 0 2006.182.07:20:21.00#ibcon#read 5, iclass 18, count 0 2006.182.07:20:21.00#ibcon#about to read 6, iclass 18, count 0 2006.182.07:20:21.00#ibcon#read 6, iclass 18, count 0 2006.182.07:20:21.00#ibcon#end of sib2, iclass 18, count 0 2006.182.07:20:21.00#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:20:21.00#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:20:21.00#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:20:21.00#ibcon#*before write, iclass 18, count 0 2006.182.07:20:21.00#ibcon#enter sib2, iclass 18, count 0 2006.182.07:20:21.00#ibcon#flushed, iclass 18, count 0 2006.182.07:20:21.00#ibcon#about to write, iclass 18, count 0 2006.182.07:20:21.00#ibcon#wrote, iclass 18, count 0 2006.182.07:20:21.00#ibcon#about to read 3, iclass 18, count 0 2006.182.07:20:21.04#ibcon#read 3, iclass 18, count 0 2006.182.07:20:21.04#ibcon#about to read 4, iclass 18, count 0 2006.182.07:20:21.04#ibcon#read 4, iclass 18, count 0 2006.182.07:20:21.04#ibcon#about to read 5, iclass 18, count 0 2006.182.07:20:21.04#ibcon#read 5, iclass 18, count 0 2006.182.07:20:21.04#ibcon#about to read 6, iclass 18, count 0 2006.182.07:20:21.04#ibcon#read 6, iclass 18, count 0 2006.182.07:20:21.04#ibcon#end of sib2, iclass 18, count 0 2006.182.07:20:21.04#ibcon#*after write, iclass 18, count 0 2006.182.07:20:21.04#ibcon#*before return 0, iclass 18, count 0 2006.182.07:20:21.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:21.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:20:21.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:20:21.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:20:21.04$vc4f8/vb=6,4 2006.182.07:20:21.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.07:20:21.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.07:20:21.05#ibcon#ireg 11 cls_cnt 2 2006.182.07:20:21.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:21.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:21.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:21.09#ibcon#enter wrdev, iclass 20, count 2 2006.182.07:20:21.09#ibcon#first serial, iclass 20, count 2 2006.182.07:20:21.09#ibcon#enter sib2, iclass 20, count 2 2006.182.07:20:21.09#ibcon#flushed, iclass 20, count 2 2006.182.07:20:21.09#ibcon#about to write, iclass 20, count 2 2006.182.07:20:21.09#ibcon#wrote, iclass 20, count 2 2006.182.07:20:21.09#ibcon#about to read 3, iclass 20, count 2 2006.182.07:20:21.11#ibcon#read 3, iclass 20, count 2 2006.182.07:20:21.11#ibcon#about to read 4, iclass 20, count 2 2006.182.07:20:21.11#ibcon#read 4, iclass 20, count 2 2006.182.07:20:21.11#ibcon#about to read 5, iclass 20, count 2 2006.182.07:20:21.11#ibcon#read 5, iclass 20, count 2 2006.182.07:20:21.11#ibcon#about to read 6, iclass 20, count 2 2006.182.07:20:21.11#ibcon#read 6, iclass 20, count 2 2006.182.07:20:21.11#ibcon#end of sib2, iclass 20, count 2 2006.182.07:20:21.11#ibcon#*mode == 0, iclass 20, count 2 2006.182.07:20:21.11#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.07:20:21.11#ibcon#[27=AT06-04\r\n] 2006.182.07:20:21.11#ibcon#*before write, iclass 20, count 2 2006.182.07:20:21.11#ibcon#enter sib2, iclass 20, count 2 2006.182.07:20:21.11#ibcon#flushed, iclass 20, count 2 2006.182.07:20:21.11#ibcon#about to write, iclass 20, count 2 2006.182.07:20:21.11#ibcon#wrote, iclass 20, count 2 2006.182.07:20:21.11#ibcon#about to read 3, iclass 20, count 2 2006.182.07:20:21.14#ibcon#read 3, iclass 20, count 2 2006.182.07:20:21.14#ibcon#about to read 4, iclass 20, count 2 2006.182.07:20:21.14#ibcon#read 4, iclass 20, count 2 2006.182.07:20:21.14#ibcon#about to read 5, iclass 20, count 2 2006.182.07:20:21.14#ibcon#read 5, iclass 20, count 2 2006.182.07:20:21.14#ibcon#about to read 6, iclass 20, count 2 2006.182.07:20:21.14#ibcon#read 6, iclass 20, count 2 2006.182.07:20:21.14#ibcon#end of sib2, iclass 20, count 2 2006.182.07:20:21.14#ibcon#*after write, iclass 20, count 2 2006.182.07:20:21.14#ibcon#*before return 0, iclass 20, count 2 2006.182.07:20:21.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:21.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:20:21.14#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.07:20:21.14#ibcon#ireg 7 cls_cnt 0 2006.182.07:20:21.14#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:21.26#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:21.26#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:21.26#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:20:21.26#ibcon#first serial, iclass 20, count 0 2006.182.07:20:21.26#ibcon#enter sib2, iclass 20, count 0 2006.182.07:20:21.26#ibcon#flushed, iclass 20, count 0 2006.182.07:20:21.26#ibcon#about to write, iclass 20, count 0 2006.182.07:20:21.26#ibcon#wrote, iclass 20, count 0 2006.182.07:20:21.26#ibcon#about to read 3, iclass 20, count 0 2006.182.07:20:21.28#ibcon#read 3, iclass 20, count 0 2006.182.07:20:21.28#ibcon#about to read 4, iclass 20, count 0 2006.182.07:20:21.28#ibcon#read 4, iclass 20, count 0 2006.182.07:20:21.28#ibcon#about to read 5, iclass 20, count 0 2006.182.07:20:21.28#ibcon#read 5, iclass 20, count 0 2006.182.07:20:21.28#ibcon#about to read 6, iclass 20, count 0 2006.182.07:20:21.28#ibcon#read 6, iclass 20, count 0 2006.182.07:20:21.28#ibcon#end of sib2, iclass 20, count 0 2006.182.07:20:21.28#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:20:21.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:20:21.28#ibcon#[27=USB\r\n] 2006.182.07:20:21.28#ibcon#*before write, iclass 20, count 0 2006.182.07:20:21.28#ibcon#enter sib2, iclass 20, count 0 2006.182.07:20:21.28#ibcon#flushed, iclass 20, count 0 2006.182.07:20:21.28#ibcon#about to write, iclass 20, count 0 2006.182.07:20:21.28#ibcon#wrote, iclass 20, count 0 2006.182.07:20:21.28#ibcon#about to read 3, iclass 20, count 0 2006.182.07:20:21.31#ibcon#read 3, iclass 20, count 0 2006.182.07:20:21.31#ibcon#about to read 4, iclass 20, count 0 2006.182.07:20:21.31#ibcon#read 4, iclass 20, count 0 2006.182.07:20:21.31#ibcon#about to read 5, iclass 20, count 0 2006.182.07:20:21.31#ibcon#read 5, iclass 20, count 0 2006.182.07:20:21.31#ibcon#about to read 6, iclass 20, count 0 2006.182.07:20:21.31#ibcon#read 6, iclass 20, count 0 2006.182.07:20:21.31#ibcon#end of sib2, iclass 20, count 0 2006.182.07:20:21.31#ibcon#*after write, iclass 20, count 0 2006.182.07:20:21.31#ibcon#*before return 0, iclass 20, count 0 2006.182.07:20:21.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:21.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:20:21.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:20:21.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:20:21.31$vc4f8/vabw=wide 2006.182.07:20:21.32#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.07:20:21.32#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.07:20:21.32#ibcon#ireg 8 cls_cnt 0 2006.182.07:20:21.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:21.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:21.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:21.32#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:20:21.32#ibcon#first serial, iclass 22, count 0 2006.182.07:20:21.32#ibcon#enter sib2, iclass 22, count 0 2006.182.07:20:21.32#ibcon#flushed, iclass 22, count 0 2006.182.07:20:21.32#ibcon#about to write, iclass 22, count 0 2006.182.07:20:21.32#ibcon#wrote, iclass 22, count 0 2006.182.07:20:21.32#ibcon#about to read 3, iclass 22, count 0 2006.182.07:20:21.33#ibcon#read 3, iclass 22, count 0 2006.182.07:20:21.33#ibcon#about to read 4, iclass 22, count 0 2006.182.07:20:21.33#ibcon#read 4, iclass 22, count 0 2006.182.07:20:21.33#ibcon#about to read 5, iclass 22, count 0 2006.182.07:20:21.33#ibcon#read 5, iclass 22, count 0 2006.182.07:20:21.33#ibcon#about to read 6, iclass 22, count 0 2006.182.07:20:21.33#ibcon#read 6, iclass 22, count 0 2006.182.07:20:21.33#ibcon#end of sib2, iclass 22, count 0 2006.182.07:20:21.33#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:20:21.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:20:21.33#ibcon#[25=BW32\r\n] 2006.182.07:20:21.33#ibcon#*before write, iclass 22, count 0 2006.182.07:20:21.33#ibcon#enter sib2, iclass 22, count 0 2006.182.07:20:21.33#ibcon#flushed, iclass 22, count 0 2006.182.07:20:21.33#ibcon#about to write, iclass 22, count 0 2006.182.07:20:21.33#ibcon#wrote, iclass 22, count 0 2006.182.07:20:21.33#ibcon#about to read 3, iclass 22, count 0 2006.182.07:20:21.36#ibcon#read 3, iclass 22, count 0 2006.182.07:20:21.36#ibcon#about to read 4, iclass 22, count 0 2006.182.07:20:21.36#ibcon#read 4, iclass 22, count 0 2006.182.07:20:21.36#ibcon#about to read 5, iclass 22, count 0 2006.182.07:20:21.36#ibcon#read 5, iclass 22, count 0 2006.182.07:20:21.36#ibcon#about to read 6, iclass 22, count 0 2006.182.07:20:21.36#ibcon#read 6, iclass 22, count 0 2006.182.07:20:21.36#ibcon#end of sib2, iclass 22, count 0 2006.182.07:20:21.36#ibcon#*after write, iclass 22, count 0 2006.182.07:20:21.36#ibcon#*before return 0, iclass 22, count 0 2006.182.07:20:21.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:21.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:20:21.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:20:21.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:20:21.37$vc4f8/vbbw=wide 2006.182.07:20:21.37#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.07:20:21.37#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.07:20:21.37#ibcon#ireg 8 cls_cnt 0 2006.182.07:20:21.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:20:21.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:20:21.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:20:21.43#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:20:21.43#ibcon#first serial, iclass 24, count 0 2006.182.07:20:21.43#ibcon#enter sib2, iclass 24, count 0 2006.182.07:20:21.43#ibcon#flushed, iclass 24, count 0 2006.182.07:20:21.43#ibcon#about to write, iclass 24, count 0 2006.182.07:20:21.43#ibcon#wrote, iclass 24, count 0 2006.182.07:20:21.43#ibcon#about to read 3, iclass 24, count 0 2006.182.07:20:21.44#ibcon#read 3, iclass 24, count 0 2006.182.07:20:21.44#ibcon#about to read 4, iclass 24, count 0 2006.182.07:20:21.44#ibcon#read 4, iclass 24, count 0 2006.182.07:20:21.44#ibcon#about to read 5, iclass 24, count 0 2006.182.07:20:21.44#ibcon#read 5, iclass 24, count 0 2006.182.07:20:21.44#ibcon#about to read 6, iclass 24, count 0 2006.182.07:20:21.44#ibcon#read 6, iclass 24, count 0 2006.182.07:20:21.44#ibcon#end of sib2, iclass 24, count 0 2006.182.07:20:21.44#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:20:21.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:20:21.44#ibcon#[27=BW32\r\n] 2006.182.07:20:21.44#ibcon#*before write, iclass 24, count 0 2006.182.07:20:21.44#ibcon#enter sib2, iclass 24, count 0 2006.182.07:20:21.44#ibcon#flushed, iclass 24, count 0 2006.182.07:20:21.44#ibcon#about to write, iclass 24, count 0 2006.182.07:20:21.44#ibcon#wrote, iclass 24, count 0 2006.182.07:20:21.44#ibcon#about to read 3, iclass 24, count 0 2006.182.07:20:21.47#ibcon#read 3, iclass 24, count 0 2006.182.07:20:21.47#ibcon#about to read 4, iclass 24, count 0 2006.182.07:20:21.47#ibcon#read 4, iclass 24, count 0 2006.182.07:20:21.47#ibcon#about to read 5, iclass 24, count 0 2006.182.07:20:21.47#ibcon#read 5, iclass 24, count 0 2006.182.07:20:21.47#ibcon#about to read 6, iclass 24, count 0 2006.182.07:20:21.47#ibcon#read 6, iclass 24, count 0 2006.182.07:20:21.47#ibcon#end of sib2, iclass 24, count 0 2006.182.07:20:21.47#ibcon#*after write, iclass 24, count 0 2006.182.07:20:21.47#ibcon#*before return 0, iclass 24, count 0 2006.182.07:20:21.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:20:21.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:20:21.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:20:21.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:20:21.48$4f8m12a/ifd4f 2006.182.07:20:21.48&ifd4f/lo= 2006.182.07:20:21.48&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:20:21.48&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:20:21.48&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:20:21.48&ifd4f/patch= 2006.182.07:20:21.48&ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:20:21.48&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:20:21.48&ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:20:21.48$ifd4f/lo= 2006.182.07:20:21.48$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:20:21.48$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:20:21.48$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:20:21.48$ifd4f/patch= 2006.182.07:20:21.48$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:20:21.48$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:20:21.48$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:20:21.48$4f8m12a/"form=m,16.000,1:2 2006.182.07:20:21.48$4f8m12a/"tpicd 2006.182.07:20:21.48$4f8m12a/echo=off 2006.182.07:20:21.48$4f8m12a/xlog=off 2006.182.07:20:21.48:!2006.182.07:29:50 2006.182.07:20:38.13#trakl#Source acquired 2006.182.07:20:38.14#flagr#flagr/antenna,acquired 2006.182.07:29:50.00:preob 2006.182.07:29:50.00&preob/onsource 2006.182.07:29:51.13/onsource/TRACKING 2006.182.07:29:51.13:!2006.182.07:30:00 2006.182.07:30:00.00:data_valid=on 2006.182.07:30:00.00:midob 2006.182.07:30:00.00&midob/onsource 2006.182.07:30:00.00&midob/wx 2006.182.07:30:00.00&midob/cable 2006.182.07:30:00.00&midob/va 2006.182.07:30:00.00&midob/valo 2006.182.07:30:00.00&midob/vb 2006.182.07:30:00.00&midob/vblo 2006.182.07:30:00.00&midob/vabw 2006.182.07:30:00.00&midob/vbbw 2006.182.07:30:00.00&midob/"form 2006.182.07:30:00.00&midob/xfe 2006.182.07:30:00.00&midob/ifatt 2006.182.07:30:00.00&midob/clockoff 2006.182.07:30:00.00&midob/sy=logmail 2006.182.07:30:00.00&midob/"sy=run setcl adapt & 2006.182.07:30:00.13/onsource/TRACKING 2006.182.07:30:00.13/wx/27.51,1002.8,82 2006.182.07:30:00.36/cable/+6.4670E-03 2006.182.07:30:01.45/va/01,08,usb,yes,29,31 2006.182.07:30:01.45/va/02,07,usb,yes,30,31 2006.182.07:30:01.45/va/03,06,usb,yes,31,31 2006.182.07:30:01.45/va/04,07,usb,yes,30,33 2006.182.07:30:01.45/va/05,07,usb,yes,31,33 2006.182.07:30:01.45/va/06,06,usb,yes,31,30 2006.182.07:30:01.45/va/07,06,usb,yes,31,31 2006.182.07:30:01.45/va/08,07,usb,yes,30,29 2006.182.07:30:01.68/valo/01,532.99,yes,locked 2006.182.07:30:01.68/valo/02,572.99,yes,locked 2006.182.07:30:01.68/valo/03,672.99,yes,locked 2006.182.07:30:01.68/valo/04,832.99,yes,locked 2006.182.07:30:01.68/valo/05,652.99,yes,locked 2006.182.07:30:01.68/valo/06,772.99,yes,locked 2006.182.07:30:01.68/valo/07,832.99,yes,locked 2006.182.07:30:01.68/valo/08,852.99,yes,locked 2006.182.07:30:02.77/vb/01,04,usb,yes,29,28 2006.182.07:30:02.77/vb/02,04,usb,yes,31,33 2006.182.07:30:02.77/vb/03,04,usb,yes,28,31 2006.182.07:30:02.77/vb/04,04,usb,yes,28,29 2006.182.07:30:02.77/vb/05,04,usb,yes,27,31 2006.182.07:30:02.77/vb/06,04,usb,yes,28,31 2006.182.07:30:02.77/vb/07,04,usb,yes,30,30 2006.182.07:30:02.77/vb/08,04,usb,yes,28,31 2006.182.07:30:03.00/vblo/01,632.99,yes,locked 2006.182.07:30:03.00/vblo/02,640.99,yes,locked 2006.182.07:30:03.00/vblo/03,656.99,yes,locked 2006.182.07:30:03.00/vblo/04,712.99,yes,locked 2006.182.07:30:03.00/vblo/05,744.99,yes,locked 2006.182.07:30:03.00/vblo/06,752.99,yes,locked 2006.182.07:30:03.00/vblo/07,734.99,yes,locked 2006.182.07:30:03.00/vblo/08,744.99,yes,locked 2006.182.07:30:03.15/vabw/8 2006.182.07:30:03.30/vbbw/8 2006.182.07:30:03.42/xfe/off,on,15.2 2006.182.07:30:03.81/ifatt/23,28,28,28 2006.182.07:30:04.07/fmout-gps/S +3.36E-07 2006.182.07:30:04.15:!2006.182.07:31:00 2006.182.07:31:00.01:data_valid=off 2006.182.07:31:00.02:postob 2006.182.07:31:00.02&postob/cable 2006.182.07:31:00.02&postob/wx 2006.182.07:31:00.03&postob/clockoff 2006.182.07:31:00.20/cable/+6.4654E-03 2006.182.07:31:00.21/wx/27.50,1002.8,81 2006.182.07:31:01.07/fmout-gps/S +3.35E-07 2006.182.07:31:01.08:scan_name=182-0733,k06182,60 2006.182.07:31:01.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.182.07:31:01.14#flagr#flagr/antenna,new-source 2006.182.07:31:02.14:checkk5 2006.182.07:31:02.14&checkk5/chk_autoobs=1 2006.182.07:31:02.14&checkk5/chk_autoobs=2 2006.182.07:31:02.14&checkk5/chk_autoobs=3 2006.182.07:31:02.14&checkk5/chk_autoobs=4 2006.182.07:31:02.14&checkk5/chk_obsdata=1 2006.182.07:31:02.14&checkk5/chk_obsdata=2 2006.182.07:31:02.14&checkk5/chk_obsdata=3 2006.182.07:31:02.14&checkk5/chk_obsdata=4 2006.182.07:31:02.14&checkk5/k5log=1 2006.182.07:31:02.14&checkk5/k5log=2 2006.182.07:31:02.14&checkk5/k5log=3 2006.182.07:31:02.14&checkk5/k5log=4 2006.182.07:31:02.14&checkk5/obsinfo 2006.182.07:31:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:31:02.96/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:31:03.35/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:31:03.73/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:31:04.10/chk_obsdata//k5ts1/T1820730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:31:04.47/chk_obsdata//k5ts2/T1820730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:31:04.84/chk_obsdata//k5ts3/T1820730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:31:05.21/chk_obsdata//k5ts4/T1820730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:31:05.92/k5log//k5ts1_log_newline 2006.182.07:31:06.61/k5log//k5ts2_log_newline 2006.182.07:31:07.29/k5log//k5ts3_log_newline 2006.182.07:31:07.98/k5log//k5ts4_log_newline 2006.182.07:31:08.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:31:08.01:4f8m12a=1 2006.182.07:31:08.01$4f8m12a/echo=on 2006.182.07:31:08.01$4f8m12a/pcalon 2006.182.07:31:08.01$pcalon/"no phase cal control is implemented here 2006.182.07:31:08.01$4f8m12a/"tpicd=stop 2006.182.07:31:08.01$4f8m12a/vc4f8 2006.182.07:31:08.01$vc4f8/valo=1,532.99 2006.182.07:31:08.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.07:31:08.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.07:31:08.01#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:08.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:08.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:08.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:08.01#ibcon#enter wrdev, iclass 31, count 0 2006.182.07:31:08.01#ibcon#first serial, iclass 31, count 0 2006.182.07:31:08.01#ibcon#enter sib2, iclass 31, count 0 2006.182.07:31:08.01#ibcon#flushed, iclass 31, count 0 2006.182.07:31:08.01#ibcon#about to write, iclass 31, count 0 2006.182.07:31:08.01#ibcon#wrote, iclass 31, count 0 2006.182.07:31:08.01#ibcon#about to read 3, iclass 31, count 0 2006.182.07:31:08.05#ibcon#read 3, iclass 31, count 0 2006.182.07:31:08.05#ibcon#about to read 4, iclass 31, count 0 2006.182.07:31:08.05#ibcon#read 4, iclass 31, count 0 2006.182.07:31:08.05#ibcon#about to read 5, iclass 31, count 0 2006.182.07:31:08.05#ibcon#read 5, iclass 31, count 0 2006.182.07:31:08.05#ibcon#about to read 6, iclass 31, count 0 2006.182.07:31:08.05#ibcon#read 6, iclass 31, count 0 2006.182.07:31:08.05#ibcon#end of sib2, iclass 31, count 0 2006.182.07:31:08.05#ibcon#*mode == 0, iclass 31, count 0 2006.182.07:31:08.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.07:31:08.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:31:08.05#ibcon#*before write, iclass 31, count 0 2006.182.07:31:08.05#ibcon#enter sib2, iclass 31, count 0 2006.182.07:31:08.05#ibcon#flushed, iclass 31, count 0 2006.182.07:31:08.05#ibcon#about to write, iclass 31, count 0 2006.182.07:31:08.05#ibcon#wrote, iclass 31, count 0 2006.182.07:31:08.05#ibcon#about to read 3, iclass 31, count 0 2006.182.07:31:08.10#ibcon#read 3, iclass 31, count 0 2006.182.07:31:08.10#ibcon#about to read 4, iclass 31, count 0 2006.182.07:31:08.10#ibcon#read 4, iclass 31, count 0 2006.182.07:31:08.10#ibcon#about to read 5, iclass 31, count 0 2006.182.07:31:08.10#ibcon#read 5, iclass 31, count 0 2006.182.07:31:08.10#ibcon#about to read 6, iclass 31, count 0 2006.182.07:31:08.10#ibcon#read 6, iclass 31, count 0 2006.182.07:31:08.10#ibcon#end of sib2, iclass 31, count 0 2006.182.07:31:08.10#ibcon#*after write, iclass 31, count 0 2006.182.07:31:08.10#ibcon#*before return 0, iclass 31, count 0 2006.182.07:31:08.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:08.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:08.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.07:31:08.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.07:31:08.10$vc4f8/va=1,8 2006.182.07:31:08.10#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.07:31:08.10#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.07:31:08.10#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:08.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:08.10#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:08.10#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:08.10#ibcon#enter wrdev, iclass 33, count 2 2006.182.07:31:08.10#ibcon#first serial, iclass 33, count 2 2006.182.07:31:08.10#ibcon#enter sib2, iclass 33, count 2 2006.182.07:31:08.10#ibcon#flushed, iclass 33, count 2 2006.182.07:31:08.10#ibcon#about to write, iclass 33, count 2 2006.182.07:31:08.10#ibcon#wrote, iclass 33, count 2 2006.182.07:31:08.10#ibcon#about to read 3, iclass 33, count 2 2006.182.07:31:08.13#ibcon#read 3, iclass 33, count 2 2006.182.07:31:08.13#ibcon#about to read 4, iclass 33, count 2 2006.182.07:31:08.13#ibcon#read 4, iclass 33, count 2 2006.182.07:31:08.13#ibcon#about to read 5, iclass 33, count 2 2006.182.07:31:08.13#ibcon#read 5, iclass 33, count 2 2006.182.07:31:08.13#ibcon#about to read 6, iclass 33, count 2 2006.182.07:31:08.13#ibcon#read 6, iclass 33, count 2 2006.182.07:31:08.13#ibcon#end of sib2, iclass 33, count 2 2006.182.07:31:08.13#ibcon#*mode == 0, iclass 33, count 2 2006.182.07:31:08.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.07:31:08.13#ibcon#[25=AT01-08\r\n] 2006.182.07:31:08.13#ibcon#*before write, iclass 33, count 2 2006.182.07:31:08.13#ibcon#enter sib2, iclass 33, count 2 2006.182.07:31:08.13#ibcon#flushed, iclass 33, count 2 2006.182.07:31:08.13#ibcon#about to write, iclass 33, count 2 2006.182.07:31:08.13#ibcon#wrote, iclass 33, count 2 2006.182.07:31:08.13#ibcon#about to read 3, iclass 33, count 2 2006.182.07:31:08.16#ibcon#read 3, iclass 33, count 2 2006.182.07:31:08.16#ibcon#about to read 4, iclass 33, count 2 2006.182.07:31:08.16#ibcon#read 4, iclass 33, count 2 2006.182.07:31:08.16#ibcon#about to read 5, iclass 33, count 2 2006.182.07:31:08.16#ibcon#read 5, iclass 33, count 2 2006.182.07:31:08.16#ibcon#about to read 6, iclass 33, count 2 2006.182.07:31:08.16#ibcon#read 6, iclass 33, count 2 2006.182.07:31:08.16#ibcon#end of sib2, iclass 33, count 2 2006.182.07:31:08.16#ibcon#*after write, iclass 33, count 2 2006.182.07:31:08.16#ibcon#*before return 0, iclass 33, count 2 2006.182.07:31:08.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:08.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:08.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.07:31:08.16#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:08.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:08.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:08.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:08.28#ibcon#enter wrdev, iclass 33, count 0 2006.182.07:31:08.28#ibcon#first serial, iclass 33, count 0 2006.182.07:31:08.28#ibcon#enter sib2, iclass 33, count 0 2006.182.07:31:08.28#ibcon#flushed, iclass 33, count 0 2006.182.07:31:08.28#ibcon#about to write, iclass 33, count 0 2006.182.07:31:08.28#ibcon#wrote, iclass 33, count 0 2006.182.07:31:08.28#ibcon#about to read 3, iclass 33, count 0 2006.182.07:31:08.30#ibcon#read 3, iclass 33, count 0 2006.182.07:31:08.30#ibcon#about to read 4, iclass 33, count 0 2006.182.07:31:08.30#ibcon#read 4, iclass 33, count 0 2006.182.07:31:08.30#ibcon#about to read 5, iclass 33, count 0 2006.182.07:31:08.30#ibcon#read 5, iclass 33, count 0 2006.182.07:31:08.30#ibcon#about to read 6, iclass 33, count 0 2006.182.07:31:08.30#ibcon#read 6, iclass 33, count 0 2006.182.07:31:08.30#ibcon#end of sib2, iclass 33, count 0 2006.182.07:31:08.30#ibcon#*mode == 0, iclass 33, count 0 2006.182.07:31:08.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.07:31:08.30#ibcon#[25=USB\r\n] 2006.182.07:31:08.30#ibcon#*before write, iclass 33, count 0 2006.182.07:31:08.30#ibcon#enter sib2, iclass 33, count 0 2006.182.07:31:08.30#ibcon#flushed, iclass 33, count 0 2006.182.07:31:08.30#ibcon#about to write, iclass 33, count 0 2006.182.07:31:08.30#ibcon#wrote, iclass 33, count 0 2006.182.07:31:08.30#ibcon#about to read 3, iclass 33, count 0 2006.182.07:31:08.33#ibcon#read 3, iclass 33, count 0 2006.182.07:31:08.33#ibcon#about to read 4, iclass 33, count 0 2006.182.07:31:08.33#ibcon#read 4, iclass 33, count 0 2006.182.07:31:08.33#ibcon#about to read 5, iclass 33, count 0 2006.182.07:31:08.33#ibcon#read 5, iclass 33, count 0 2006.182.07:31:08.33#ibcon#about to read 6, iclass 33, count 0 2006.182.07:31:08.33#ibcon#read 6, iclass 33, count 0 2006.182.07:31:08.33#ibcon#end of sib2, iclass 33, count 0 2006.182.07:31:08.33#ibcon#*after write, iclass 33, count 0 2006.182.07:31:08.33#ibcon#*before return 0, iclass 33, count 0 2006.182.07:31:08.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:08.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:08.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.07:31:08.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.07:31:08.33$vc4f8/valo=2,572.99 2006.182.07:31:08.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.07:31:08.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.07:31:08.33#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:08.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:08.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:08.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:08.33#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:31:08.33#ibcon#first serial, iclass 35, count 0 2006.182.07:31:08.33#ibcon#enter sib2, iclass 35, count 0 2006.182.07:31:08.33#ibcon#flushed, iclass 35, count 0 2006.182.07:31:08.33#ibcon#about to write, iclass 35, count 0 2006.182.07:31:08.33#ibcon#wrote, iclass 35, count 0 2006.182.07:31:08.33#ibcon#about to read 3, iclass 35, count 0 2006.182.07:31:08.36#ibcon#read 3, iclass 35, count 0 2006.182.07:31:08.36#ibcon#about to read 4, iclass 35, count 0 2006.182.07:31:08.36#ibcon#read 4, iclass 35, count 0 2006.182.07:31:08.36#ibcon#about to read 5, iclass 35, count 0 2006.182.07:31:08.36#ibcon#read 5, iclass 35, count 0 2006.182.07:31:08.36#ibcon#about to read 6, iclass 35, count 0 2006.182.07:31:08.36#ibcon#read 6, iclass 35, count 0 2006.182.07:31:08.36#ibcon#end of sib2, iclass 35, count 0 2006.182.07:31:08.36#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:31:08.36#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:31:08.36#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:31:08.36#ibcon#*before write, iclass 35, count 0 2006.182.07:31:08.36#ibcon#enter sib2, iclass 35, count 0 2006.182.07:31:08.36#ibcon#flushed, iclass 35, count 0 2006.182.07:31:08.36#ibcon#about to write, iclass 35, count 0 2006.182.07:31:08.36#ibcon#wrote, iclass 35, count 0 2006.182.07:31:08.36#ibcon#about to read 3, iclass 35, count 0 2006.182.07:31:08.40#ibcon#read 3, iclass 35, count 0 2006.182.07:31:08.40#ibcon#about to read 4, iclass 35, count 0 2006.182.07:31:08.40#ibcon#read 4, iclass 35, count 0 2006.182.07:31:08.40#ibcon#about to read 5, iclass 35, count 0 2006.182.07:31:08.40#ibcon#read 5, iclass 35, count 0 2006.182.07:31:08.40#ibcon#about to read 6, iclass 35, count 0 2006.182.07:31:08.40#ibcon#read 6, iclass 35, count 0 2006.182.07:31:08.40#ibcon#end of sib2, iclass 35, count 0 2006.182.07:31:08.40#ibcon#*after write, iclass 35, count 0 2006.182.07:31:08.40#ibcon#*before return 0, iclass 35, count 0 2006.182.07:31:08.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:08.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:08.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:31:08.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:31:08.40$vc4f8/va=2,7 2006.182.07:31:08.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.07:31:08.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.07:31:08.40#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:08.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:08.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:08.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:08.45#ibcon#enter wrdev, iclass 37, count 2 2006.182.07:31:08.45#ibcon#first serial, iclass 37, count 2 2006.182.07:31:08.45#ibcon#enter sib2, iclass 37, count 2 2006.182.07:31:08.45#ibcon#flushed, iclass 37, count 2 2006.182.07:31:08.45#ibcon#about to write, iclass 37, count 2 2006.182.07:31:08.45#ibcon#wrote, iclass 37, count 2 2006.182.07:31:08.45#ibcon#about to read 3, iclass 37, count 2 2006.182.07:31:08.47#ibcon#read 3, iclass 37, count 2 2006.182.07:31:08.47#ibcon#about to read 4, iclass 37, count 2 2006.182.07:31:08.47#ibcon#read 4, iclass 37, count 2 2006.182.07:31:08.47#ibcon#about to read 5, iclass 37, count 2 2006.182.07:31:08.47#ibcon#read 5, iclass 37, count 2 2006.182.07:31:08.47#ibcon#about to read 6, iclass 37, count 2 2006.182.07:31:08.47#ibcon#read 6, iclass 37, count 2 2006.182.07:31:08.47#ibcon#end of sib2, iclass 37, count 2 2006.182.07:31:08.47#ibcon#*mode == 0, iclass 37, count 2 2006.182.07:31:08.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.07:31:08.47#ibcon#[25=AT02-07\r\n] 2006.182.07:31:08.47#ibcon#*before write, iclass 37, count 2 2006.182.07:31:08.47#ibcon#enter sib2, iclass 37, count 2 2006.182.07:31:08.47#ibcon#flushed, iclass 37, count 2 2006.182.07:31:08.47#ibcon#about to write, iclass 37, count 2 2006.182.07:31:08.47#ibcon#wrote, iclass 37, count 2 2006.182.07:31:08.47#ibcon#about to read 3, iclass 37, count 2 2006.182.07:31:08.50#ibcon#read 3, iclass 37, count 2 2006.182.07:31:08.50#ibcon#about to read 4, iclass 37, count 2 2006.182.07:31:08.50#ibcon#read 4, iclass 37, count 2 2006.182.07:31:08.50#ibcon#about to read 5, iclass 37, count 2 2006.182.07:31:08.50#ibcon#read 5, iclass 37, count 2 2006.182.07:31:08.50#ibcon#about to read 6, iclass 37, count 2 2006.182.07:31:08.50#ibcon#read 6, iclass 37, count 2 2006.182.07:31:08.50#ibcon#end of sib2, iclass 37, count 2 2006.182.07:31:08.50#ibcon#*after write, iclass 37, count 2 2006.182.07:31:08.50#ibcon#*before return 0, iclass 37, count 2 2006.182.07:31:08.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:08.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:08.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.07:31:08.50#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:08.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:08.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:08.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:08.62#ibcon#enter wrdev, iclass 37, count 0 2006.182.07:31:08.62#ibcon#first serial, iclass 37, count 0 2006.182.07:31:08.62#ibcon#enter sib2, iclass 37, count 0 2006.182.07:31:08.62#ibcon#flushed, iclass 37, count 0 2006.182.07:31:08.62#ibcon#about to write, iclass 37, count 0 2006.182.07:31:08.62#ibcon#wrote, iclass 37, count 0 2006.182.07:31:08.62#ibcon#about to read 3, iclass 37, count 0 2006.182.07:31:08.64#ibcon#read 3, iclass 37, count 0 2006.182.07:31:08.64#ibcon#about to read 4, iclass 37, count 0 2006.182.07:31:08.64#ibcon#read 4, iclass 37, count 0 2006.182.07:31:08.64#ibcon#about to read 5, iclass 37, count 0 2006.182.07:31:08.64#ibcon#read 5, iclass 37, count 0 2006.182.07:31:08.64#ibcon#about to read 6, iclass 37, count 0 2006.182.07:31:08.64#ibcon#read 6, iclass 37, count 0 2006.182.07:31:08.64#ibcon#end of sib2, iclass 37, count 0 2006.182.07:31:08.64#ibcon#*mode == 0, iclass 37, count 0 2006.182.07:31:08.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.07:31:08.64#ibcon#[25=USB\r\n] 2006.182.07:31:08.64#ibcon#*before write, iclass 37, count 0 2006.182.07:31:08.64#ibcon#enter sib2, iclass 37, count 0 2006.182.07:31:08.64#ibcon#flushed, iclass 37, count 0 2006.182.07:31:08.64#ibcon#about to write, iclass 37, count 0 2006.182.07:31:08.64#ibcon#wrote, iclass 37, count 0 2006.182.07:31:08.64#ibcon#about to read 3, iclass 37, count 0 2006.182.07:31:08.67#ibcon#read 3, iclass 37, count 0 2006.182.07:31:08.67#ibcon#about to read 4, iclass 37, count 0 2006.182.07:31:08.67#ibcon#read 4, iclass 37, count 0 2006.182.07:31:08.67#ibcon#about to read 5, iclass 37, count 0 2006.182.07:31:08.67#ibcon#read 5, iclass 37, count 0 2006.182.07:31:08.67#ibcon#about to read 6, iclass 37, count 0 2006.182.07:31:08.67#ibcon#read 6, iclass 37, count 0 2006.182.07:31:08.67#ibcon#end of sib2, iclass 37, count 0 2006.182.07:31:08.67#ibcon#*after write, iclass 37, count 0 2006.182.07:31:08.67#ibcon#*before return 0, iclass 37, count 0 2006.182.07:31:08.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:08.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:08.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.07:31:08.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.07:31:08.67$vc4f8/valo=3,672.99 2006.182.07:31:08.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.07:31:08.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.07:31:08.67#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:08.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:08.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:08.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:08.67#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:31:08.67#ibcon#first serial, iclass 39, count 0 2006.182.07:31:08.67#ibcon#enter sib2, iclass 39, count 0 2006.182.07:31:08.67#ibcon#flushed, iclass 39, count 0 2006.182.07:31:08.67#ibcon#about to write, iclass 39, count 0 2006.182.07:31:08.67#ibcon#wrote, iclass 39, count 0 2006.182.07:31:08.67#ibcon#about to read 3, iclass 39, count 0 2006.182.07:31:08.70#ibcon#read 3, iclass 39, count 0 2006.182.07:31:08.70#ibcon#about to read 4, iclass 39, count 0 2006.182.07:31:08.70#ibcon#read 4, iclass 39, count 0 2006.182.07:31:08.70#ibcon#about to read 5, iclass 39, count 0 2006.182.07:31:08.70#ibcon#read 5, iclass 39, count 0 2006.182.07:31:08.70#ibcon#about to read 6, iclass 39, count 0 2006.182.07:31:08.70#ibcon#read 6, iclass 39, count 0 2006.182.07:31:08.70#ibcon#end of sib2, iclass 39, count 0 2006.182.07:31:08.70#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:31:08.70#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:31:08.70#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:31:08.70#ibcon#*before write, iclass 39, count 0 2006.182.07:31:08.70#ibcon#enter sib2, iclass 39, count 0 2006.182.07:31:08.70#ibcon#flushed, iclass 39, count 0 2006.182.07:31:08.70#ibcon#about to write, iclass 39, count 0 2006.182.07:31:08.70#ibcon#wrote, iclass 39, count 0 2006.182.07:31:08.70#ibcon#about to read 3, iclass 39, count 0 2006.182.07:31:08.74#ibcon#read 3, iclass 39, count 0 2006.182.07:31:08.74#ibcon#about to read 4, iclass 39, count 0 2006.182.07:31:08.74#ibcon#read 4, iclass 39, count 0 2006.182.07:31:08.74#ibcon#about to read 5, iclass 39, count 0 2006.182.07:31:08.74#ibcon#read 5, iclass 39, count 0 2006.182.07:31:08.74#ibcon#about to read 6, iclass 39, count 0 2006.182.07:31:08.74#ibcon#read 6, iclass 39, count 0 2006.182.07:31:08.74#ibcon#end of sib2, iclass 39, count 0 2006.182.07:31:08.74#ibcon#*after write, iclass 39, count 0 2006.182.07:31:08.74#ibcon#*before return 0, iclass 39, count 0 2006.182.07:31:08.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:08.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:08.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:31:08.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:31:08.74$vc4f8/va=3,6 2006.182.07:31:08.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.07:31:08.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.07:31:08.74#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:08.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:08.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:08.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:08.79#ibcon#enter wrdev, iclass 3, count 2 2006.182.07:31:08.79#ibcon#first serial, iclass 3, count 2 2006.182.07:31:08.79#ibcon#enter sib2, iclass 3, count 2 2006.182.07:31:08.79#ibcon#flushed, iclass 3, count 2 2006.182.07:31:08.79#ibcon#about to write, iclass 3, count 2 2006.182.07:31:08.79#ibcon#wrote, iclass 3, count 2 2006.182.07:31:08.79#ibcon#about to read 3, iclass 3, count 2 2006.182.07:31:08.81#ibcon#read 3, iclass 3, count 2 2006.182.07:31:08.81#ibcon#about to read 4, iclass 3, count 2 2006.182.07:31:08.81#ibcon#read 4, iclass 3, count 2 2006.182.07:31:08.81#ibcon#about to read 5, iclass 3, count 2 2006.182.07:31:08.81#ibcon#read 5, iclass 3, count 2 2006.182.07:31:08.81#ibcon#about to read 6, iclass 3, count 2 2006.182.07:31:08.81#ibcon#read 6, iclass 3, count 2 2006.182.07:31:08.81#ibcon#end of sib2, iclass 3, count 2 2006.182.07:31:08.81#ibcon#*mode == 0, iclass 3, count 2 2006.182.07:31:08.81#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.07:31:08.81#ibcon#[25=AT03-06\r\n] 2006.182.07:31:08.81#ibcon#*before write, iclass 3, count 2 2006.182.07:31:08.81#ibcon#enter sib2, iclass 3, count 2 2006.182.07:31:08.81#ibcon#flushed, iclass 3, count 2 2006.182.07:31:08.81#ibcon#about to write, iclass 3, count 2 2006.182.07:31:08.81#ibcon#wrote, iclass 3, count 2 2006.182.07:31:08.81#ibcon#about to read 3, iclass 3, count 2 2006.182.07:31:08.84#ibcon#read 3, iclass 3, count 2 2006.182.07:31:08.84#ibcon#about to read 4, iclass 3, count 2 2006.182.07:31:08.84#ibcon#read 4, iclass 3, count 2 2006.182.07:31:08.84#ibcon#about to read 5, iclass 3, count 2 2006.182.07:31:08.84#ibcon#read 5, iclass 3, count 2 2006.182.07:31:08.84#ibcon#about to read 6, iclass 3, count 2 2006.182.07:31:08.84#ibcon#read 6, iclass 3, count 2 2006.182.07:31:08.84#ibcon#end of sib2, iclass 3, count 2 2006.182.07:31:08.84#ibcon#*after write, iclass 3, count 2 2006.182.07:31:08.84#ibcon#*before return 0, iclass 3, count 2 2006.182.07:31:08.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:08.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:08.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.07:31:08.84#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:08.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:08.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:08.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:08.96#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:31:08.96#ibcon#first serial, iclass 3, count 0 2006.182.07:31:08.96#ibcon#enter sib2, iclass 3, count 0 2006.182.07:31:08.96#ibcon#flushed, iclass 3, count 0 2006.182.07:31:08.96#ibcon#about to write, iclass 3, count 0 2006.182.07:31:08.96#ibcon#wrote, iclass 3, count 0 2006.182.07:31:08.96#ibcon#about to read 3, iclass 3, count 0 2006.182.07:31:08.98#ibcon#read 3, iclass 3, count 0 2006.182.07:31:08.98#ibcon#about to read 4, iclass 3, count 0 2006.182.07:31:08.98#ibcon#read 4, iclass 3, count 0 2006.182.07:31:08.98#ibcon#about to read 5, iclass 3, count 0 2006.182.07:31:08.98#ibcon#read 5, iclass 3, count 0 2006.182.07:31:08.98#ibcon#about to read 6, iclass 3, count 0 2006.182.07:31:08.98#ibcon#read 6, iclass 3, count 0 2006.182.07:31:08.98#ibcon#end of sib2, iclass 3, count 0 2006.182.07:31:08.98#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:31:08.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:31:08.98#ibcon#[25=USB\r\n] 2006.182.07:31:08.98#ibcon#*before write, iclass 3, count 0 2006.182.07:31:08.98#ibcon#enter sib2, iclass 3, count 0 2006.182.07:31:08.98#ibcon#flushed, iclass 3, count 0 2006.182.07:31:08.98#ibcon#about to write, iclass 3, count 0 2006.182.07:31:08.98#ibcon#wrote, iclass 3, count 0 2006.182.07:31:08.98#ibcon#about to read 3, iclass 3, count 0 2006.182.07:31:09.01#ibcon#read 3, iclass 3, count 0 2006.182.07:31:09.01#ibcon#about to read 4, iclass 3, count 0 2006.182.07:31:09.01#ibcon#read 4, iclass 3, count 0 2006.182.07:31:09.01#ibcon#about to read 5, iclass 3, count 0 2006.182.07:31:09.01#ibcon#read 5, iclass 3, count 0 2006.182.07:31:09.01#ibcon#about to read 6, iclass 3, count 0 2006.182.07:31:09.01#ibcon#read 6, iclass 3, count 0 2006.182.07:31:09.01#ibcon#end of sib2, iclass 3, count 0 2006.182.07:31:09.01#ibcon#*after write, iclass 3, count 0 2006.182.07:31:09.01#ibcon#*before return 0, iclass 3, count 0 2006.182.07:31:09.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:09.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:09.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:31:09.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:31:09.01$vc4f8/valo=4,832.99 2006.182.07:31:09.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.07:31:09.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.07:31:09.01#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:09.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:09.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:09.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:09.01#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:31:09.01#ibcon#first serial, iclass 5, count 0 2006.182.07:31:09.01#ibcon#enter sib2, iclass 5, count 0 2006.182.07:31:09.01#ibcon#flushed, iclass 5, count 0 2006.182.07:31:09.01#ibcon#about to write, iclass 5, count 0 2006.182.07:31:09.01#ibcon#wrote, iclass 5, count 0 2006.182.07:31:09.01#ibcon#about to read 3, iclass 5, count 0 2006.182.07:31:09.03#ibcon#read 3, iclass 5, count 0 2006.182.07:31:09.03#ibcon#about to read 4, iclass 5, count 0 2006.182.07:31:09.03#ibcon#read 4, iclass 5, count 0 2006.182.07:31:09.03#ibcon#about to read 5, iclass 5, count 0 2006.182.07:31:09.03#ibcon#read 5, iclass 5, count 0 2006.182.07:31:09.03#ibcon#about to read 6, iclass 5, count 0 2006.182.07:31:09.03#ibcon#read 6, iclass 5, count 0 2006.182.07:31:09.03#ibcon#end of sib2, iclass 5, count 0 2006.182.07:31:09.03#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:31:09.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:31:09.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:31:09.03#ibcon#*before write, iclass 5, count 0 2006.182.07:31:09.03#ibcon#enter sib2, iclass 5, count 0 2006.182.07:31:09.03#ibcon#flushed, iclass 5, count 0 2006.182.07:31:09.03#ibcon#about to write, iclass 5, count 0 2006.182.07:31:09.03#ibcon#wrote, iclass 5, count 0 2006.182.07:31:09.03#ibcon#about to read 3, iclass 5, count 0 2006.182.07:31:09.07#ibcon#read 3, iclass 5, count 0 2006.182.07:31:09.07#ibcon#about to read 4, iclass 5, count 0 2006.182.07:31:09.07#ibcon#read 4, iclass 5, count 0 2006.182.07:31:09.07#ibcon#about to read 5, iclass 5, count 0 2006.182.07:31:09.07#ibcon#read 5, iclass 5, count 0 2006.182.07:31:09.07#ibcon#about to read 6, iclass 5, count 0 2006.182.07:31:09.07#ibcon#read 6, iclass 5, count 0 2006.182.07:31:09.07#ibcon#end of sib2, iclass 5, count 0 2006.182.07:31:09.07#ibcon#*after write, iclass 5, count 0 2006.182.07:31:09.07#ibcon#*before return 0, iclass 5, count 0 2006.182.07:31:09.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:09.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:09.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:31:09.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:31:09.07$vc4f8/va=4,7 2006.182.07:31:09.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.07:31:09.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.07:31:09.07#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:09.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:09.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:09.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:09.13#ibcon#enter wrdev, iclass 7, count 2 2006.182.07:31:09.13#ibcon#first serial, iclass 7, count 2 2006.182.07:31:09.13#ibcon#enter sib2, iclass 7, count 2 2006.182.07:31:09.13#ibcon#flushed, iclass 7, count 2 2006.182.07:31:09.13#ibcon#about to write, iclass 7, count 2 2006.182.07:31:09.13#ibcon#wrote, iclass 7, count 2 2006.182.07:31:09.13#ibcon#about to read 3, iclass 7, count 2 2006.182.07:31:09.15#ibcon#read 3, iclass 7, count 2 2006.182.07:31:09.15#ibcon#about to read 4, iclass 7, count 2 2006.182.07:31:09.15#ibcon#read 4, iclass 7, count 2 2006.182.07:31:09.15#ibcon#about to read 5, iclass 7, count 2 2006.182.07:31:09.15#ibcon#read 5, iclass 7, count 2 2006.182.07:31:09.15#ibcon#about to read 6, iclass 7, count 2 2006.182.07:31:09.15#ibcon#read 6, iclass 7, count 2 2006.182.07:31:09.15#ibcon#end of sib2, iclass 7, count 2 2006.182.07:31:09.15#ibcon#*mode == 0, iclass 7, count 2 2006.182.07:31:09.15#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.07:31:09.15#ibcon#[25=AT04-07\r\n] 2006.182.07:31:09.15#ibcon#*before write, iclass 7, count 2 2006.182.07:31:09.15#ibcon#enter sib2, iclass 7, count 2 2006.182.07:31:09.15#ibcon#flushed, iclass 7, count 2 2006.182.07:31:09.15#ibcon#about to write, iclass 7, count 2 2006.182.07:31:09.15#ibcon#wrote, iclass 7, count 2 2006.182.07:31:09.15#ibcon#about to read 3, iclass 7, count 2 2006.182.07:31:09.18#ibcon#read 3, iclass 7, count 2 2006.182.07:31:09.18#ibcon#about to read 4, iclass 7, count 2 2006.182.07:31:09.18#ibcon#read 4, iclass 7, count 2 2006.182.07:31:09.18#ibcon#about to read 5, iclass 7, count 2 2006.182.07:31:09.18#ibcon#read 5, iclass 7, count 2 2006.182.07:31:09.18#ibcon#about to read 6, iclass 7, count 2 2006.182.07:31:09.18#ibcon#read 6, iclass 7, count 2 2006.182.07:31:09.18#ibcon#end of sib2, iclass 7, count 2 2006.182.07:31:09.18#ibcon#*after write, iclass 7, count 2 2006.182.07:31:09.18#ibcon#*before return 0, iclass 7, count 2 2006.182.07:31:09.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:09.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:09.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.07:31:09.18#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:09.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:09.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:09.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:09.30#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:31:09.30#ibcon#first serial, iclass 7, count 0 2006.182.07:31:09.30#ibcon#enter sib2, iclass 7, count 0 2006.182.07:31:09.30#ibcon#flushed, iclass 7, count 0 2006.182.07:31:09.30#ibcon#about to write, iclass 7, count 0 2006.182.07:31:09.30#ibcon#wrote, iclass 7, count 0 2006.182.07:31:09.30#ibcon#about to read 3, iclass 7, count 0 2006.182.07:31:09.32#ibcon#read 3, iclass 7, count 0 2006.182.07:31:09.32#ibcon#about to read 4, iclass 7, count 0 2006.182.07:31:09.32#ibcon#read 4, iclass 7, count 0 2006.182.07:31:09.32#ibcon#about to read 5, iclass 7, count 0 2006.182.07:31:09.32#ibcon#read 5, iclass 7, count 0 2006.182.07:31:09.32#ibcon#about to read 6, iclass 7, count 0 2006.182.07:31:09.32#ibcon#read 6, iclass 7, count 0 2006.182.07:31:09.32#ibcon#end of sib2, iclass 7, count 0 2006.182.07:31:09.32#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:31:09.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:31:09.32#ibcon#[25=USB\r\n] 2006.182.07:31:09.32#ibcon#*before write, iclass 7, count 0 2006.182.07:31:09.32#ibcon#enter sib2, iclass 7, count 0 2006.182.07:31:09.32#ibcon#flushed, iclass 7, count 0 2006.182.07:31:09.32#ibcon#about to write, iclass 7, count 0 2006.182.07:31:09.32#ibcon#wrote, iclass 7, count 0 2006.182.07:31:09.32#ibcon#about to read 3, iclass 7, count 0 2006.182.07:31:09.35#ibcon#read 3, iclass 7, count 0 2006.182.07:31:09.35#ibcon#about to read 4, iclass 7, count 0 2006.182.07:31:09.35#ibcon#read 4, iclass 7, count 0 2006.182.07:31:09.35#ibcon#about to read 5, iclass 7, count 0 2006.182.07:31:09.35#ibcon#read 5, iclass 7, count 0 2006.182.07:31:09.35#ibcon#about to read 6, iclass 7, count 0 2006.182.07:31:09.35#ibcon#read 6, iclass 7, count 0 2006.182.07:31:09.35#ibcon#end of sib2, iclass 7, count 0 2006.182.07:31:09.35#ibcon#*after write, iclass 7, count 0 2006.182.07:31:09.35#ibcon#*before return 0, iclass 7, count 0 2006.182.07:31:09.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:09.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:09.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:31:09.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:31:09.35$vc4f8/valo=5,652.99 2006.182.07:31:09.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.07:31:09.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.07:31:09.35#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:09.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:09.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:09.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:09.35#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:31:09.35#ibcon#first serial, iclass 11, count 0 2006.182.07:31:09.35#ibcon#enter sib2, iclass 11, count 0 2006.182.07:31:09.35#ibcon#flushed, iclass 11, count 0 2006.182.07:31:09.35#ibcon#about to write, iclass 11, count 0 2006.182.07:31:09.35#ibcon#wrote, iclass 11, count 0 2006.182.07:31:09.35#ibcon#about to read 3, iclass 11, count 0 2006.182.07:31:09.37#ibcon#read 3, iclass 11, count 0 2006.182.07:31:09.37#ibcon#about to read 4, iclass 11, count 0 2006.182.07:31:09.37#ibcon#read 4, iclass 11, count 0 2006.182.07:31:09.37#ibcon#about to read 5, iclass 11, count 0 2006.182.07:31:09.37#ibcon#read 5, iclass 11, count 0 2006.182.07:31:09.37#ibcon#about to read 6, iclass 11, count 0 2006.182.07:31:09.37#ibcon#read 6, iclass 11, count 0 2006.182.07:31:09.37#ibcon#end of sib2, iclass 11, count 0 2006.182.07:31:09.37#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:31:09.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:31:09.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:31:09.37#ibcon#*before write, iclass 11, count 0 2006.182.07:31:09.37#ibcon#enter sib2, iclass 11, count 0 2006.182.07:31:09.37#ibcon#flushed, iclass 11, count 0 2006.182.07:31:09.37#ibcon#about to write, iclass 11, count 0 2006.182.07:31:09.37#ibcon#wrote, iclass 11, count 0 2006.182.07:31:09.37#ibcon#about to read 3, iclass 11, count 0 2006.182.07:31:09.41#ibcon#read 3, iclass 11, count 0 2006.182.07:31:09.41#ibcon#about to read 4, iclass 11, count 0 2006.182.07:31:09.41#ibcon#read 4, iclass 11, count 0 2006.182.07:31:09.41#ibcon#about to read 5, iclass 11, count 0 2006.182.07:31:09.41#ibcon#read 5, iclass 11, count 0 2006.182.07:31:09.41#ibcon#about to read 6, iclass 11, count 0 2006.182.07:31:09.41#ibcon#read 6, iclass 11, count 0 2006.182.07:31:09.41#ibcon#end of sib2, iclass 11, count 0 2006.182.07:31:09.41#ibcon#*after write, iclass 11, count 0 2006.182.07:31:09.41#ibcon#*before return 0, iclass 11, count 0 2006.182.07:31:09.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:09.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:09.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:31:09.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:31:09.41$vc4f8/va=5,7 2006.182.07:31:09.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.07:31:09.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.07:31:09.41#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:09.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:09.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:09.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:09.47#ibcon#enter wrdev, iclass 13, count 2 2006.182.07:31:09.47#ibcon#first serial, iclass 13, count 2 2006.182.07:31:09.47#ibcon#enter sib2, iclass 13, count 2 2006.182.07:31:09.47#ibcon#flushed, iclass 13, count 2 2006.182.07:31:09.47#ibcon#about to write, iclass 13, count 2 2006.182.07:31:09.47#ibcon#wrote, iclass 13, count 2 2006.182.07:31:09.47#ibcon#about to read 3, iclass 13, count 2 2006.182.07:31:09.49#ibcon#read 3, iclass 13, count 2 2006.182.07:31:09.49#ibcon#about to read 4, iclass 13, count 2 2006.182.07:31:09.49#ibcon#read 4, iclass 13, count 2 2006.182.07:31:09.49#ibcon#about to read 5, iclass 13, count 2 2006.182.07:31:09.49#ibcon#read 5, iclass 13, count 2 2006.182.07:31:09.49#ibcon#about to read 6, iclass 13, count 2 2006.182.07:31:09.49#ibcon#read 6, iclass 13, count 2 2006.182.07:31:09.49#ibcon#end of sib2, iclass 13, count 2 2006.182.07:31:09.49#ibcon#*mode == 0, iclass 13, count 2 2006.182.07:31:09.49#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.07:31:09.49#ibcon#[25=AT05-07\r\n] 2006.182.07:31:09.49#ibcon#*before write, iclass 13, count 2 2006.182.07:31:09.49#ibcon#enter sib2, iclass 13, count 2 2006.182.07:31:09.49#ibcon#flushed, iclass 13, count 2 2006.182.07:31:09.49#ibcon#about to write, iclass 13, count 2 2006.182.07:31:09.49#ibcon#wrote, iclass 13, count 2 2006.182.07:31:09.49#ibcon#about to read 3, iclass 13, count 2 2006.182.07:31:09.52#ibcon#read 3, iclass 13, count 2 2006.182.07:31:09.52#ibcon#about to read 4, iclass 13, count 2 2006.182.07:31:09.52#ibcon#read 4, iclass 13, count 2 2006.182.07:31:09.52#ibcon#about to read 5, iclass 13, count 2 2006.182.07:31:09.52#ibcon#read 5, iclass 13, count 2 2006.182.07:31:09.52#ibcon#about to read 6, iclass 13, count 2 2006.182.07:31:09.52#ibcon#read 6, iclass 13, count 2 2006.182.07:31:09.52#ibcon#end of sib2, iclass 13, count 2 2006.182.07:31:09.52#ibcon#*after write, iclass 13, count 2 2006.182.07:31:09.52#ibcon#*before return 0, iclass 13, count 2 2006.182.07:31:09.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:09.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:09.52#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.07:31:09.52#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:09.52#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:09.64#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:09.64#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:09.64#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:31:09.64#ibcon#first serial, iclass 13, count 0 2006.182.07:31:09.64#ibcon#enter sib2, iclass 13, count 0 2006.182.07:31:09.64#ibcon#flushed, iclass 13, count 0 2006.182.07:31:09.64#ibcon#about to write, iclass 13, count 0 2006.182.07:31:09.64#ibcon#wrote, iclass 13, count 0 2006.182.07:31:09.64#ibcon#about to read 3, iclass 13, count 0 2006.182.07:31:09.66#ibcon#read 3, iclass 13, count 0 2006.182.07:31:09.66#ibcon#about to read 4, iclass 13, count 0 2006.182.07:31:09.66#ibcon#read 4, iclass 13, count 0 2006.182.07:31:09.66#ibcon#about to read 5, iclass 13, count 0 2006.182.07:31:09.66#ibcon#read 5, iclass 13, count 0 2006.182.07:31:09.66#ibcon#about to read 6, iclass 13, count 0 2006.182.07:31:09.66#ibcon#read 6, iclass 13, count 0 2006.182.07:31:09.66#ibcon#end of sib2, iclass 13, count 0 2006.182.07:31:09.66#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:31:09.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:31:09.66#ibcon#[25=USB\r\n] 2006.182.07:31:09.66#ibcon#*before write, iclass 13, count 0 2006.182.07:31:09.66#ibcon#enter sib2, iclass 13, count 0 2006.182.07:31:09.66#ibcon#flushed, iclass 13, count 0 2006.182.07:31:09.66#ibcon#about to write, iclass 13, count 0 2006.182.07:31:09.66#ibcon#wrote, iclass 13, count 0 2006.182.07:31:09.66#ibcon#about to read 3, iclass 13, count 0 2006.182.07:31:09.69#ibcon#read 3, iclass 13, count 0 2006.182.07:31:09.69#ibcon#about to read 4, iclass 13, count 0 2006.182.07:31:09.69#ibcon#read 4, iclass 13, count 0 2006.182.07:31:09.69#ibcon#about to read 5, iclass 13, count 0 2006.182.07:31:09.69#ibcon#read 5, iclass 13, count 0 2006.182.07:31:09.69#ibcon#about to read 6, iclass 13, count 0 2006.182.07:31:09.69#ibcon#read 6, iclass 13, count 0 2006.182.07:31:09.69#ibcon#end of sib2, iclass 13, count 0 2006.182.07:31:09.69#ibcon#*after write, iclass 13, count 0 2006.182.07:31:09.69#ibcon#*before return 0, iclass 13, count 0 2006.182.07:31:09.69#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:09.69#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:09.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:31:09.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:31:09.69$vc4f8/valo=6,772.99 2006.182.07:31:09.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.07:31:09.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.07:31:09.69#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:09.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:09.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:09.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:09.69#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:31:09.69#ibcon#first serial, iclass 15, count 0 2006.182.07:31:09.69#ibcon#enter sib2, iclass 15, count 0 2006.182.07:31:09.69#ibcon#flushed, iclass 15, count 0 2006.182.07:31:09.69#ibcon#about to write, iclass 15, count 0 2006.182.07:31:09.69#ibcon#wrote, iclass 15, count 0 2006.182.07:31:09.69#ibcon#about to read 3, iclass 15, count 0 2006.182.07:31:09.72#ibcon#read 3, iclass 15, count 0 2006.182.07:31:09.72#ibcon#about to read 4, iclass 15, count 0 2006.182.07:31:09.72#ibcon#read 4, iclass 15, count 0 2006.182.07:31:09.72#ibcon#about to read 5, iclass 15, count 0 2006.182.07:31:09.72#ibcon#read 5, iclass 15, count 0 2006.182.07:31:09.72#ibcon#about to read 6, iclass 15, count 0 2006.182.07:31:09.72#ibcon#read 6, iclass 15, count 0 2006.182.07:31:09.72#ibcon#end of sib2, iclass 15, count 0 2006.182.07:31:09.72#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:31:09.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:31:09.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:31:09.72#ibcon#*before write, iclass 15, count 0 2006.182.07:31:09.72#ibcon#enter sib2, iclass 15, count 0 2006.182.07:31:09.72#ibcon#flushed, iclass 15, count 0 2006.182.07:31:09.72#ibcon#about to write, iclass 15, count 0 2006.182.07:31:09.72#ibcon#wrote, iclass 15, count 0 2006.182.07:31:09.72#ibcon#about to read 3, iclass 15, count 0 2006.182.07:31:09.76#ibcon#read 3, iclass 15, count 0 2006.182.07:31:09.76#ibcon#about to read 4, iclass 15, count 0 2006.182.07:31:09.76#ibcon#read 4, iclass 15, count 0 2006.182.07:31:09.76#ibcon#about to read 5, iclass 15, count 0 2006.182.07:31:09.76#ibcon#read 5, iclass 15, count 0 2006.182.07:31:09.76#ibcon#about to read 6, iclass 15, count 0 2006.182.07:31:09.76#ibcon#read 6, iclass 15, count 0 2006.182.07:31:09.76#ibcon#end of sib2, iclass 15, count 0 2006.182.07:31:09.76#ibcon#*after write, iclass 15, count 0 2006.182.07:31:09.76#ibcon#*before return 0, iclass 15, count 0 2006.182.07:31:09.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:09.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:09.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:31:09.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:31:09.76$vc4f8/va=6,6 2006.182.07:31:09.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.07:31:09.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.07:31:09.76#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:09.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:31:09.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:31:09.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:31:09.81#ibcon#enter wrdev, iclass 17, count 2 2006.182.07:31:09.81#ibcon#first serial, iclass 17, count 2 2006.182.07:31:09.81#ibcon#enter sib2, iclass 17, count 2 2006.182.07:31:09.81#ibcon#flushed, iclass 17, count 2 2006.182.07:31:09.81#ibcon#about to write, iclass 17, count 2 2006.182.07:31:09.81#ibcon#wrote, iclass 17, count 2 2006.182.07:31:09.81#ibcon#about to read 3, iclass 17, count 2 2006.182.07:31:09.83#ibcon#read 3, iclass 17, count 2 2006.182.07:31:09.83#ibcon#about to read 4, iclass 17, count 2 2006.182.07:31:09.83#ibcon#read 4, iclass 17, count 2 2006.182.07:31:09.83#ibcon#about to read 5, iclass 17, count 2 2006.182.07:31:09.83#ibcon#read 5, iclass 17, count 2 2006.182.07:31:09.83#ibcon#about to read 6, iclass 17, count 2 2006.182.07:31:09.83#ibcon#read 6, iclass 17, count 2 2006.182.07:31:09.83#ibcon#end of sib2, iclass 17, count 2 2006.182.07:31:09.83#ibcon#*mode == 0, iclass 17, count 2 2006.182.07:31:09.83#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.07:31:09.83#ibcon#[25=AT06-06\r\n] 2006.182.07:31:09.83#ibcon#*before write, iclass 17, count 2 2006.182.07:31:09.83#ibcon#enter sib2, iclass 17, count 2 2006.182.07:31:09.83#ibcon#flushed, iclass 17, count 2 2006.182.07:31:09.83#ibcon#about to write, iclass 17, count 2 2006.182.07:31:09.83#ibcon#wrote, iclass 17, count 2 2006.182.07:31:09.83#ibcon#about to read 3, iclass 17, count 2 2006.182.07:31:09.86#ibcon#read 3, iclass 17, count 2 2006.182.07:31:09.86#ibcon#about to read 4, iclass 17, count 2 2006.182.07:31:09.86#ibcon#read 4, iclass 17, count 2 2006.182.07:31:09.86#ibcon#about to read 5, iclass 17, count 2 2006.182.07:31:09.86#ibcon#read 5, iclass 17, count 2 2006.182.07:31:09.86#ibcon#about to read 6, iclass 17, count 2 2006.182.07:31:09.86#ibcon#read 6, iclass 17, count 2 2006.182.07:31:09.86#ibcon#end of sib2, iclass 17, count 2 2006.182.07:31:09.86#ibcon#*after write, iclass 17, count 2 2006.182.07:31:09.86#ibcon#*before return 0, iclass 17, count 2 2006.182.07:31:09.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:31:09.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:31:09.86#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.07:31:09.86#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:09.86#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:31:09.98#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:31:09.98#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:31:09.98#ibcon#enter wrdev, iclass 17, count 0 2006.182.07:31:09.98#ibcon#first serial, iclass 17, count 0 2006.182.07:31:09.98#ibcon#enter sib2, iclass 17, count 0 2006.182.07:31:09.98#ibcon#flushed, iclass 17, count 0 2006.182.07:31:09.98#ibcon#about to write, iclass 17, count 0 2006.182.07:31:09.98#ibcon#wrote, iclass 17, count 0 2006.182.07:31:09.98#ibcon#about to read 3, iclass 17, count 0 2006.182.07:31:10.00#ibcon#read 3, iclass 17, count 0 2006.182.07:31:10.00#ibcon#about to read 4, iclass 17, count 0 2006.182.07:31:10.00#ibcon#read 4, iclass 17, count 0 2006.182.07:31:10.00#ibcon#about to read 5, iclass 17, count 0 2006.182.07:31:10.00#ibcon#read 5, iclass 17, count 0 2006.182.07:31:10.00#ibcon#about to read 6, iclass 17, count 0 2006.182.07:31:10.00#ibcon#read 6, iclass 17, count 0 2006.182.07:31:10.00#ibcon#end of sib2, iclass 17, count 0 2006.182.07:31:10.00#ibcon#*mode == 0, iclass 17, count 0 2006.182.07:31:10.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.07:31:10.00#ibcon#[25=USB\r\n] 2006.182.07:31:10.00#ibcon#*before write, iclass 17, count 0 2006.182.07:31:10.00#ibcon#enter sib2, iclass 17, count 0 2006.182.07:31:10.00#ibcon#flushed, iclass 17, count 0 2006.182.07:31:10.00#ibcon#about to write, iclass 17, count 0 2006.182.07:31:10.00#ibcon#wrote, iclass 17, count 0 2006.182.07:31:10.00#ibcon#about to read 3, iclass 17, count 0 2006.182.07:31:10.03#ibcon#read 3, iclass 17, count 0 2006.182.07:31:10.03#ibcon#about to read 4, iclass 17, count 0 2006.182.07:31:10.03#ibcon#read 4, iclass 17, count 0 2006.182.07:31:10.03#ibcon#about to read 5, iclass 17, count 0 2006.182.07:31:10.03#ibcon#read 5, iclass 17, count 0 2006.182.07:31:10.03#ibcon#about to read 6, iclass 17, count 0 2006.182.07:31:10.03#ibcon#read 6, iclass 17, count 0 2006.182.07:31:10.03#ibcon#end of sib2, iclass 17, count 0 2006.182.07:31:10.03#ibcon#*after write, iclass 17, count 0 2006.182.07:31:10.03#ibcon#*before return 0, iclass 17, count 0 2006.182.07:31:10.03#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:31:10.03#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:31:10.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.07:31:10.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.07:31:10.03$vc4f8/valo=7,832.99 2006.182.07:31:10.03#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.07:31:10.03#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.07:31:10.03#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:10.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:31:10.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:31:10.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:31:10.03#ibcon#enter wrdev, iclass 19, count 0 2006.182.07:31:10.03#ibcon#first serial, iclass 19, count 0 2006.182.07:31:10.03#ibcon#enter sib2, iclass 19, count 0 2006.182.07:31:10.03#ibcon#flushed, iclass 19, count 0 2006.182.07:31:10.03#ibcon#about to write, iclass 19, count 0 2006.182.07:31:10.03#ibcon#wrote, iclass 19, count 0 2006.182.07:31:10.03#ibcon#about to read 3, iclass 19, count 0 2006.182.07:31:10.05#ibcon#read 3, iclass 19, count 0 2006.182.07:31:10.05#ibcon#about to read 4, iclass 19, count 0 2006.182.07:31:10.05#ibcon#read 4, iclass 19, count 0 2006.182.07:31:10.05#ibcon#about to read 5, iclass 19, count 0 2006.182.07:31:10.05#ibcon#read 5, iclass 19, count 0 2006.182.07:31:10.05#ibcon#about to read 6, iclass 19, count 0 2006.182.07:31:10.05#ibcon#read 6, iclass 19, count 0 2006.182.07:31:10.05#ibcon#end of sib2, iclass 19, count 0 2006.182.07:31:10.05#ibcon#*mode == 0, iclass 19, count 0 2006.182.07:31:10.05#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.07:31:10.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:31:10.05#ibcon#*before write, iclass 19, count 0 2006.182.07:31:10.05#ibcon#enter sib2, iclass 19, count 0 2006.182.07:31:10.05#ibcon#flushed, iclass 19, count 0 2006.182.07:31:10.05#ibcon#about to write, iclass 19, count 0 2006.182.07:31:10.05#ibcon#wrote, iclass 19, count 0 2006.182.07:31:10.05#ibcon#about to read 3, iclass 19, count 0 2006.182.07:31:10.09#ibcon#read 3, iclass 19, count 0 2006.182.07:31:10.09#ibcon#about to read 4, iclass 19, count 0 2006.182.07:31:10.09#ibcon#read 4, iclass 19, count 0 2006.182.07:31:10.09#ibcon#about to read 5, iclass 19, count 0 2006.182.07:31:10.09#ibcon#read 5, iclass 19, count 0 2006.182.07:31:10.09#ibcon#about to read 6, iclass 19, count 0 2006.182.07:31:10.09#ibcon#read 6, iclass 19, count 0 2006.182.07:31:10.09#ibcon#end of sib2, iclass 19, count 0 2006.182.07:31:10.09#ibcon#*after write, iclass 19, count 0 2006.182.07:31:10.09#ibcon#*before return 0, iclass 19, count 0 2006.182.07:31:10.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:31:10.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:31:10.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.07:31:10.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.07:31:10.09$vc4f8/va=7,6 2006.182.07:31:10.09#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.07:31:10.09#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.07:31:10.09#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:10.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:31:10.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:31:10.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:31:10.15#ibcon#enter wrdev, iclass 21, count 2 2006.182.07:31:10.15#ibcon#first serial, iclass 21, count 2 2006.182.07:31:10.15#ibcon#enter sib2, iclass 21, count 2 2006.182.07:31:10.15#ibcon#flushed, iclass 21, count 2 2006.182.07:31:10.15#ibcon#about to write, iclass 21, count 2 2006.182.07:31:10.15#ibcon#wrote, iclass 21, count 2 2006.182.07:31:10.15#ibcon#about to read 3, iclass 21, count 2 2006.182.07:31:10.17#ibcon#read 3, iclass 21, count 2 2006.182.07:31:10.17#ibcon#about to read 4, iclass 21, count 2 2006.182.07:31:10.17#ibcon#read 4, iclass 21, count 2 2006.182.07:31:10.17#ibcon#about to read 5, iclass 21, count 2 2006.182.07:31:10.17#ibcon#read 5, iclass 21, count 2 2006.182.07:31:10.17#ibcon#about to read 6, iclass 21, count 2 2006.182.07:31:10.17#ibcon#read 6, iclass 21, count 2 2006.182.07:31:10.17#ibcon#end of sib2, iclass 21, count 2 2006.182.07:31:10.17#ibcon#*mode == 0, iclass 21, count 2 2006.182.07:31:10.17#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.07:31:10.17#ibcon#[25=AT07-06\r\n] 2006.182.07:31:10.17#ibcon#*before write, iclass 21, count 2 2006.182.07:31:10.17#ibcon#enter sib2, iclass 21, count 2 2006.182.07:31:10.17#ibcon#flushed, iclass 21, count 2 2006.182.07:31:10.17#ibcon#about to write, iclass 21, count 2 2006.182.07:31:10.17#ibcon#wrote, iclass 21, count 2 2006.182.07:31:10.17#ibcon#about to read 3, iclass 21, count 2 2006.182.07:31:10.20#ibcon#read 3, iclass 21, count 2 2006.182.07:31:10.20#ibcon#about to read 4, iclass 21, count 2 2006.182.07:31:10.20#ibcon#read 4, iclass 21, count 2 2006.182.07:31:10.20#ibcon#about to read 5, iclass 21, count 2 2006.182.07:31:10.20#ibcon#read 5, iclass 21, count 2 2006.182.07:31:10.20#ibcon#about to read 6, iclass 21, count 2 2006.182.07:31:10.20#ibcon#read 6, iclass 21, count 2 2006.182.07:31:10.20#ibcon#end of sib2, iclass 21, count 2 2006.182.07:31:10.20#ibcon#*after write, iclass 21, count 2 2006.182.07:31:10.20#ibcon#*before return 0, iclass 21, count 2 2006.182.07:31:10.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:31:10.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:31:10.20#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.07:31:10.20#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:10.20#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:31:10.32#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:31:10.32#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:31:10.32#ibcon#enter wrdev, iclass 21, count 0 2006.182.07:31:10.32#ibcon#first serial, iclass 21, count 0 2006.182.07:31:10.32#ibcon#enter sib2, iclass 21, count 0 2006.182.07:31:10.32#ibcon#flushed, iclass 21, count 0 2006.182.07:31:10.32#ibcon#about to write, iclass 21, count 0 2006.182.07:31:10.32#ibcon#wrote, iclass 21, count 0 2006.182.07:31:10.32#ibcon#about to read 3, iclass 21, count 0 2006.182.07:31:10.34#ibcon#read 3, iclass 21, count 0 2006.182.07:31:10.34#ibcon#about to read 4, iclass 21, count 0 2006.182.07:31:10.34#ibcon#read 4, iclass 21, count 0 2006.182.07:31:10.34#ibcon#about to read 5, iclass 21, count 0 2006.182.07:31:10.34#ibcon#read 5, iclass 21, count 0 2006.182.07:31:10.34#ibcon#about to read 6, iclass 21, count 0 2006.182.07:31:10.34#ibcon#read 6, iclass 21, count 0 2006.182.07:31:10.34#ibcon#end of sib2, iclass 21, count 0 2006.182.07:31:10.34#ibcon#*mode == 0, iclass 21, count 0 2006.182.07:31:10.34#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.07:31:10.34#ibcon#[25=USB\r\n] 2006.182.07:31:10.34#ibcon#*before write, iclass 21, count 0 2006.182.07:31:10.34#ibcon#enter sib2, iclass 21, count 0 2006.182.07:31:10.34#ibcon#flushed, iclass 21, count 0 2006.182.07:31:10.34#ibcon#about to write, iclass 21, count 0 2006.182.07:31:10.34#ibcon#wrote, iclass 21, count 0 2006.182.07:31:10.34#ibcon#about to read 3, iclass 21, count 0 2006.182.07:31:10.37#ibcon#read 3, iclass 21, count 0 2006.182.07:31:10.37#ibcon#about to read 4, iclass 21, count 0 2006.182.07:31:10.37#ibcon#read 4, iclass 21, count 0 2006.182.07:31:10.37#ibcon#about to read 5, iclass 21, count 0 2006.182.07:31:10.37#ibcon#read 5, iclass 21, count 0 2006.182.07:31:10.37#ibcon#about to read 6, iclass 21, count 0 2006.182.07:31:10.37#ibcon#read 6, iclass 21, count 0 2006.182.07:31:10.37#ibcon#end of sib2, iclass 21, count 0 2006.182.07:31:10.37#ibcon#*after write, iclass 21, count 0 2006.182.07:31:10.37#ibcon#*before return 0, iclass 21, count 0 2006.182.07:31:10.37#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:31:10.37#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:31:10.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.07:31:10.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.07:31:10.37$vc4f8/valo=8,852.99 2006.182.07:31:10.37#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.07:31:10.37#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.07:31:10.37#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:10.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:31:10.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:31:10.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:31:10.37#ibcon#enter wrdev, iclass 23, count 0 2006.182.07:31:10.37#ibcon#first serial, iclass 23, count 0 2006.182.07:31:10.37#ibcon#enter sib2, iclass 23, count 0 2006.182.07:31:10.37#ibcon#flushed, iclass 23, count 0 2006.182.07:31:10.37#ibcon#about to write, iclass 23, count 0 2006.182.07:31:10.37#ibcon#wrote, iclass 23, count 0 2006.182.07:31:10.37#ibcon#about to read 3, iclass 23, count 0 2006.182.07:31:10.40#ibcon#read 3, iclass 23, count 0 2006.182.07:31:10.40#ibcon#about to read 4, iclass 23, count 0 2006.182.07:31:10.40#ibcon#read 4, iclass 23, count 0 2006.182.07:31:10.40#ibcon#about to read 5, iclass 23, count 0 2006.182.07:31:10.40#ibcon#read 5, iclass 23, count 0 2006.182.07:31:10.40#ibcon#about to read 6, iclass 23, count 0 2006.182.07:31:10.40#ibcon#read 6, iclass 23, count 0 2006.182.07:31:10.40#ibcon#end of sib2, iclass 23, count 0 2006.182.07:31:10.40#ibcon#*mode == 0, iclass 23, count 0 2006.182.07:31:10.40#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.07:31:10.40#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:31:10.40#ibcon#*before write, iclass 23, count 0 2006.182.07:31:10.40#ibcon#enter sib2, iclass 23, count 0 2006.182.07:31:10.40#ibcon#flushed, iclass 23, count 0 2006.182.07:31:10.40#ibcon#about to write, iclass 23, count 0 2006.182.07:31:10.40#ibcon#wrote, iclass 23, count 0 2006.182.07:31:10.40#ibcon#about to read 3, iclass 23, count 0 2006.182.07:31:10.44#ibcon#read 3, iclass 23, count 0 2006.182.07:31:10.44#ibcon#about to read 4, iclass 23, count 0 2006.182.07:31:10.44#ibcon#read 4, iclass 23, count 0 2006.182.07:31:10.44#ibcon#about to read 5, iclass 23, count 0 2006.182.07:31:10.44#ibcon#read 5, iclass 23, count 0 2006.182.07:31:10.44#ibcon#about to read 6, iclass 23, count 0 2006.182.07:31:10.44#ibcon#read 6, iclass 23, count 0 2006.182.07:31:10.44#ibcon#end of sib2, iclass 23, count 0 2006.182.07:31:10.44#ibcon#*after write, iclass 23, count 0 2006.182.07:31:10.44#ibcon#*before return 0, iclass 23, count 0 2006.182.07:31:10.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:31:10.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:31:10.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.07:31:10.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.07:31:10.44$vc4f8/va=8,7 2006.182.07:31:10.44#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.07:31:10.44#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.07:31:10.44#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:10.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:31:10.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:31:10.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:31:10.49#ibcon#enter wrdev, iclass 25, count 2 2006.182.07:31:10.49#ibcon#first serial, iclass 25, count 2 2006.182.07:31:10.49#ibcon#enter sib2, iclass 25, count 2 2006.182.07:31:10.49#ibcon#flushed, iclass 25, count 2 2006.182.07:31:10.49#ibcon#about to write, iclass 25, count 2 2006.182.07:31:10.49#ibcon#wrote, iclass 25, count 2 2006.182.07:31:10.49#ibcon#about to read 3, iclass 25, count 2 2006.182.07:31:10.51#ibcon#read 3, iclass 25, count 2 2006.182.07:31:10.51#ibcon#about to read 4, iclass 25, count 2 2006.182.07:31:10.51#ibcon#read 4, iclass 25, count 2 2006.182.07:31:10.51#ibcon#about to read 5, iclass 25, count 2 2006.182.07:31:10.51#ibcon#read 5, iclass 25, count 2 2006.182.07:31:10.51#ibcon#about to read 6, iclass 25, count 2 2006.182.07:31:10.51#ibcon#read 6, iclass 25, count 2 2006.182.07:31:10.51#ibcon#end of sib2, iclass 25, count 2 2006.182.07:31:10.51#ibcon#*mode == 0, iclass 25, count 2 2006.182.07:31:10.51#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.07:31:10.51#ibcon#[25=AT08-07\r\n] 2006.182.07:31:10.51#ibcon#*before write, iclass 25, count 2 2006.182.07:31:10.51#ibcon#enter sib2, iclass 25, count 2 2006.182.07:31:10.51#ibcon#flushed, iclass 25, count 2 2006.182.07:31:10.51#ibcon#about to write, iclass 25, count 2 2006.182.07:31:10.51#ibcon#wrote, iclass 25, count 2 2006.182.07:31:10.51#ibcon#about to read 3, iclass 25, count 2 2006.182.07:31:10.54#ibcon#read 3, iclass 25, count 2 2006.182.07:31:10.54#ibcon#about to read 4, iclass 25, count 2 2006.182.07:31:10.54#ibcon#read 4, iclass 25, count 2 2006.182.07:31:10.54#ibcon#about to read 5, iclass 25, count 2 2006.182.07:31:10.54#ibcon#read 5, iclass 25, count 2 2006.182.07:31:10.54#ibcon#about to read 6, iclass 25, count 2 2006.182.07:31:10.54#ibcon#read 6, iclass 25, count 2 2006.182.07:31:10.54#ibcon#end of sib2, iclass 25, count 2 2006.182.07:31:10.54#ibcon#*after write, iclass 25, count 2 2006.182.07:31:10.54#ibcon#*before return 0, iclass 25, count 2 2006.182.07:31:10.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:31:10.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:31:10.54#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.07:31:10.54#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:10.54#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:31:10.66#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:31:10.66#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:31:10.66#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:31:10.66#ibcon#first serial, iclass 25, count 0 2006.182.07:31:10.66#ibcon#enter sib2, iclass 25, count 0 2006.182.07:31:10.66#ibcon#flushed, iclass 25, count 0 2006.182.07:31:10.66#ibcon#about to write, iclass 25, count 0 2006.182.07:31:10.66#ibcon#wrote, iclass 25, count 0 2006.182.07:31:10.66#ibcon#about to read 3, iclass 25, count 0 2006.182.07:31:10.68#ibcon#read 3, iclass 25, count 0 2006.182.07:31:10.68#ibcon#about to read 4, iclass 25, count 0 2006.182.07:31:10.68#ibcon#read 4, iclass 25, count 0 2006.182.07:31:10.68#ibcon#about to read 5, iclass 25, count 0 2006.182.07:31:10.68#ibcon#read 5, iclass 25, count 0 2006.182.07:31:10.68#ibcon#about to read 6, iclass 25, count 0 2006.182.07:31:10.68#ibcon#read 6, iclass 25, count 0 2006.182.07:31:10.68#ibcon#end of sib2, iclass 25, count 0 2006.182.07:31:10.68#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:31:10.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:31:10.68#ibcon#[25=USB\r\n] 2006.182.07:31:10.68#ibcon#*before write, iclass 25, count 0 2006.182.07:31:10.68#ibcon#enter sib2, iclass 25, count 0 2006.182.07:31:10.68#ibcon#flushed, iclass 25, count 0 2006.182.07:31:10.68#ibcon#about to write, iclass 25, count 0 2006.182.07:31:10.68#ibcon#wrote, iclass 25, count 0 2006.182.07:31:10.68#ibcon#about to read 3, iclass 25, count 0 2006.182.07:31:10.71#ibcon#read 3, iclass 25, count 0 2006.182.07:31:10.71#ibcon#about to read 4, iclass 25, count 0 2006.182.07:31:10.71#ibcon#read 4, iclass 25, count 0 2006.182.07:31:10.71#ibcon#about to read 5, iclass 25, count 0 2006.182.07:31:10.71#ibcon#read 5, iclass 25, count 0 2006.182.07:31:10.71#ibcon#about to read 6, iclass 25, count 0 2006.182.07:31:10.71#ibcon#read 6, iclass 25, count 0 2006.182.07:31:10.71#ibcon#end of sib2, iclass 25, count 0 2006.182.07:31:10.71#ibcon#*after write, iclass 25, count 0 2006.182.07:31:10.71#ibcon#*before return 0, iclass 25, count 0 2006.182.07:31:10.71#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:31:10.71#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:31:10.71#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:31:10.71#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:31:10.71$vc4f8/vblo=1,632.99 2006.182.07:31:10.71#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.07:31:10.71#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.07:31:10.71#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:10.71#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:31:10.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:31:10.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:31:10.71#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:31:10.71#ibcon#first serial, iclass 27, count 0 2006.182.07:31:10.71#ibcon#enter sib2, iclass 27, count 0 2006.182.07:31:10.71#ibcon#flushed, iclass 27, count 0 2006.182.07:31:10.71#ibcon#about to write, iclass 27, count 0 2006.182.07:31:10.71#ibcon#wrote, iclass 27, count 0 2006.182.07:31:10.71#ibcon#about to read 3, iclass 27, count 0 2006.182.07:31:10.73#ibcon#read 3, iclass 27, count 0 2006.182.07:31:10.73#ibcon#about to read 4, iclass 27, count 0 2006.182.07:31:10.73#ibcon#read 4, iclass 27, count 0 2006.182.07:31:10.73#ibcon#about to read 5, iclass 27, count 0 2006.182.07:31:10.73#ibcon#read 5, iclass 27, count 0 2006.182.07:31:10.73#ibcon#about to read 6, iclass 27, count 0 2006.182.07:31:10.73#ibcon#read 6, iclass 27, count 0 2006.182.07:31:10.73#ibcon#end of sib2, iclass 27, count 0 2006.182.07:31:10.73#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:31:10.73#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:31:10.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:31:10.73#ibcon#*before write, iclass 27, count 0 2006.182.07:31:10.73#ibcon#enter sib2, iclass 27, count 0 2006.182.07:31:10.73#ibcon#flushed, iclass 27, count 0 2006.182.07:31:10.73#ibcon#about to write, iclass 27, count 0 2006.182.07:31:10.73#ibcon#wrote, iclass 27, count 0 2006.182.07:31:10.73#ibcon#about to read 3, iclass 27, count 0 2006.182.07:31:10.77#ibcon#read 3, iclass 27, count 0 2006.182.07:31:10.77#ibcon#about to read 4, iclass 27, count 0 2006.182.07:31:10.77#ibcon#read 4, iclass 27, count 0 2006.182.07:31:10.77#ibcon#about to read 5, iclass 27, count 0 2006.182.07:31:10.77#ibcon#read 5, iclass 27, count 0 2006.182.07:31:10.77#ibcon#about to read 6, iclass 27, count 0 2006.182.07:31:10.77#ibcon#read 6, iclass 27, count 0 2006.182.07:31:10.77#ibcon#end of sib2, iclass 27, count 0 2006.182.07:31:10.77#ibcon#*after write, iclass 27, count 0 2006.182.07:31:10.77#ibcon#*before return 0, iclass 27, count 0 2006.182.07:31:10.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:31:10.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:31:10.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:31:10.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:31:10.77$vc4f8/vb=1,4 2006.182.07:31:10.77#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.07:31:10.77#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.07:31:10.77#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:10.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:31:10.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:31:10.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:31:10.77#ibcon#enter wrdev, iclass 29, count 2 2006.182.07:31:10.77#ibcon#first serial, iclass 29, count 2 2006.182.07:31:10.77#ibcon#enter sib2, iclass 29, count 2 2006.182.07:31:10.77#ibcon#flushed, iclass 29, count 2 2006.182.07:31:10.77#ibcon#about to write, iclass 29, count 2 2006.182.07:31:10.77#ibcon#wrote, iclass 29, count 2 2006.182.07:31:10.77#ibcon#about to read 3, iclass 29, count 2 2006.182.07:31:10.79#ibcon#read 3, iclass 29, count 2 2006.182.07:31:10.79#ibcon#about to read 4, iclass 29, count 2 2006.182.07:31:10.79#ibcon#read 4, iclass 29, count 2 2006.182.07:31:10.79#ibcon#about to read 5, iclass 29, count 2 2006.182.07:31:10.79#ibcon#read 5, iclass 29, count 2 2006.182.07:31:10.79#ibcon#about to read 6, iclass 29, count 2 2006.182.07:31:10.79#ibcon#read 6, iclass 29, count 2 2006.182.07:31:10.79#ibcon#end of sib2, iclass 29, count 2 2006.182.07:31:10.79#ibcon#*mode == 0, iclass 29, count 2 2006.182.07:31:10.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.07:31:10.79#ibcon#[27=AT01-04\r\n] 2006.182.07:31:10.79#ibcon#*before write, iclass 29, count 2 2006.182.07:31:10.79#ibcon#enter sib2, iclass 29, count 2 2006.182.07:31:10.79#ibcon#flushed, iclass 29, count 2 2006.182.07:31:10.79#ibcon#about to write, iclass 29, count 2 2006.182.07:31:10.79#ibcon#wrote, iclass 29, count 2 2006.182.07:31:10.79#ibcon#about to read 3, iclass 29, count 2 2006.182.07:31:10.82#ibcon#read 3, iclass 29, count 2 2006.182.07:31:10.82#ibcon#about to read 4, iclass 29, count 2 2006.182.07:31:10.82#ibcon#read 4, iclass 29, count 2 2006.182.07:31:10.82#ibcon#about to read 5, iclass 29, count 2 2006.182.07:31:10.82#ibcon#read 5, iclass 29, count 2 2006.182.07:31:10.82#ibcon#about to read 6, iclass 29, count 2 2006.182.07:31:10.82#ibcon#read 6, iclass 29, count 2 2006.182.07:31:10.82#ibcon#end of sib2, iclass 29, count 2 2006.182.07:31:10.82#ibcon#*after write, iclass 29, count 2 2006.182.07:31:10.82#ibcon#*before return 0, iclass 29, count 2 2006.182.07:31:10.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:31:10.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:31:10.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.07:31:10.82#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:10.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:31:10.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:31:10.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:31:10.94#ibcon#enter wrdev, iclass 29, count 0 2006.182.07:31:10.94#ibcon#first serial, iclass 29, count 0 2006.182.07:31:10.94#ibcon#enter sib2, iclass 29, count 0 2006.182.07:31:10.94#ibcon#flushed, iclass 29, count 0 2006.182.07:31:10.94#ibcon#about to write, iclass 29, count 0 2006.182.07:31:10.94#ibcon#wrote, iclass 29, count 0 2006.182.07:31:10.94#ibcon#about to read 3, iclass 29, count 0 2006.182.07:31:10.96#ibcon#read 3, iclass 29, count 0 2006.182.07:31:10.96#ibcon#about to read 4, iclass 29, count 0 2006.182.07:31:10.96#ibcon#read 4, iclass 29, count 0 2006.182.07:31:10.96#ibcon#about to read 5, iclass 29, count 0 2006.182.07:31:10.96#ibcon#read 5, iclass 29, count 0 2006.182.07:31:10.96#ibcon#about to read 6, iclass 29, count 0 2006.182.07:31:10.96#ibcon#read 6, iclass 29, count 0 2006.182.07:31:10.96#ibcon#end of sib2, iclass 29, count 0 2006.182.07:31:10.96#ibcon#*mode == 0, iclass 29, count 0 2006.182.07:31:10.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.07:31:10.96#ibcon#[27=USB\r\n] 2006.182.07:31:10.96#ibcon#*before write, iclass 29, count 0 2006.182.07:31:10.96#ibcon#enter sib2, iclass 29, count 0 2006.182.07:31:10.96#ibcon#flushed, iclass 29, count 0 2006.182.07:31:10.96#ibcon#about to write, iclass 29, count 0 2006.182.07:31:10.96#ibcon#wrote, iclass 29, count 0 2006.182.07:31:10.96#ibcon#about to read 3, iclass 29, count 0 2006.182.07:31:10.99#ibcon#read 3, iclass 29, count 0 2006.182.07:31:10.99#ibcon#about to read 4, iclass 29, count 0 2006.182.07:31:10.99#ibcon#read 4, iclass 29, count 0 2006.182.07:31:10.99#ibcon#about to read 5, iclass 29, count 0 2006.182.07:31:10.99#ibcon#read 5, iclass 29, count 0 2006.182.07:31:10.99#ibcon#about to read 6, iclass 29, count 0 2006.182.07:31:10.99#ibcon#read 6, iclass 29, count 0 2006.182.07:31:10.99#ibcon#end of sib2, iclass 29, count 0 2006.182.07:31:10.99#ibcon#*after write, iclass 29, count 0 2006.182.07:31:10.99#ibcon#*before return 0, iclass 29, count 0 2006.182.07:31:10.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:31:10.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:31:10.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.07:31:10.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.07:31:10.99$vc4f8/vblo=2,640.99 2006.182.07:31:10.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.07:31:10.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.07:31:10.99#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:10.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:10.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:10.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:10.99#ibcon#enter wrdev, iclass 31, count 0 2006.182.07:31:10.99#ibcon#first serial, iclass 31, count 0 2006.182.07:31:10.99#ibcon#enter sib2, iclass 31, count 0 2006.182.07:31:10.99#ibcon#flushed, iclass 31, count 0 2006.182.07:31:10.99#ibcon#about to write, iclass 31, count 0 2006.182.07:31:10.99#ibcon#wrote, iclass 31, count 0 2006.182.07:31:10.99#ibcon#about to read 3, iclass 31, count 0 2006.182.07:31:11.01#ibcon#read 3, iclass 31, count 0 2006.182.07:31:11.01#ibcon#about to read 4, iclass 31, count 0 2006.182.07:31:11.01#ibcon#read 4, iclass 31, count 0 2006.182.07:31:11.01#ibcon#about to read 5, iclass 31, count 0 2006.182.07:31:11.01#ibcon#read 5, iclass 31, count 0 2006.182.07:31:11.01#ibcon#about to read 6, iclass 31, count 0 2006.182.07:31:11.01#ibcon#read 6, iclass 31, count 0 2006.182.07:31:11.01#ibcon#end of sib2, iclass 31, count 0 2006.182.07:31:11.01#ibcon#*mode == 0, iclass 31, count 0 2006.182.07:31:11.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.07:31:11.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:31:11.01#ibcon#*before write, iclass 31, count 0 2006.182.07:31:11.01#ibcon#enter sib2, iclass 31, count 0 2006.182.07:31:11.01#ibcon#flushed, iclass 31, count 0 2006.182.07:31:11.01#ibcon#about to write, iclass 31, count 0 2006.182.07:31:11.01#ibcon#wrote, iclass 31, count 0 2006.182.07:31:11.01#ibcon#about to read 3, iclass 31, count 0 2006.182.07:31:11.05#ibcon#read 3, iclass 31, count 0 2006.182.07:31:11.05#ibcon#about to read 4, iclass 31, count 0 2006.182.07:31:11.05#ibcon#read 4, iclass 31, count 0 2006.182.07:31:11.05#ibcon#about to read 5, iclass 31, count 0 2006.182.07:31:11.05#ibcon#read 5, iclass 31, count 0 2006.182.07:31:11.05#ibcon#about to read 6, iclass 31, count 0 2006.182.07:31:11.05#ibcon#read 6, iclass 31, count 0 2006.182.07:31:11.05#ibcon#end of sib2, iclass 31, count 0 2006.182.07:31:11.05#ibcon#*after write, iclass 31, count 0 2006.182.07:31:11.05#ibcon#*before return 0, iclass 31, count 0 2006.182.07:31:11.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:11.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:31:11.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.07:31:11.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.07:31:11.05$vc4f8/vb=2,4 2006.182.07:31:11.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.07:31:11.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.07:31:11.05#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:11.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:11.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:11.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:11.11#ibcon#enter wrdev, iclass 33, count 2 2006.182.07:31:11.11#ibcon#first serial, iclass 33, count 2 2006.182.07:31:11.11#ibcon#enter sib2, iclass 33, count 2 2006.182.07:31:11.11#ibcon#flushed, iclass 33, count 2 2006.182.07:31:11.11#ibcon#about to write, iclass 33, count 2 2006.182.07:31:11.11#ibcon#wrote, iclass 33, count 2 2006.182.07:31:11.11#ibcon#about to read 3, iclass 33, count 2 2006.182.07:31:11.13#ibcon#read 3, iclass 33, count 2 2006.182.07:31:11.13#ibcon#about to read 4, iclass 33, count 2 2006.182.07:31:11.13#ibcon#read 4, iclass 33, count 2 2006.182.07:31:11.13#ibcon#about to read 5, iclass 33, count 2 2006.182.07:31:11.13#ibcon#read 5, iclass 33, count 2 2006.182.07:31:11.13#ibcon#about to read 6, iclass 33, count 2 2006.182.07:31:11.13#ibcon#read 6, iclass 33, count 2 2006.182.07:31:11.13#ibcon#end of sib2, iclass 33, count 2 2006.182.07:31:11.13#ibcon#*mode == 0, iclass 33, count 2 2006.182.07:31:11.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.07:31:11.13#ibcon#[27=AT02-04\r\n] 2006.182.07:31:11.13#ibcon#*before write, iclass 33, count 2 2006.182.07:31:11.13#ibcon#enter sib2, iclass 33, count 2 2006.182.07:31:11.13#ibcon#flushed, iclass 33, count 2 2006.182.07:31:11.13#ibcon#about to write, iclass 33, count 2 2006.182.07:31:11.13#ibcon#wrote, iclass 33, count 2 2006.182.07:31:11.13#ibcon#about to read 3, iclass 33, count 2 2006.182.07:31:11.16#ibcon#read 3, iclass 33, count 2 2006.182.07:31:11.16#ibcon#about to read 4, iclass 33, count 2 2006.182.07:31:11.16#ibcon#read 4, iclass 33, count 2 2006.182.07:31:11.16#ibcon#about to read 5, iclass 33, count 2 2006.182.07:31:11.16#ibcon#read 5, iclass 33, count 2 2006.182.07:31:11.16#ibcon#about to read 6, iclass 33, count 2 2006.182.07:31:11.16#ibcon#read 6, iclass 33, count 2 2006.182.07:31:11.16#ibcon#end of sib2, iclass 33, count 2 2006.182.07:31:11.16#ibcon#*after write, iclass 33, count 2 2006.182.07:31:11.16#ibcon#*before return 0, iclass 33, count 2 2006.182.07:31:11.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:11.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:31:11.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.07:31:11.16#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:11.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:11.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:11.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:11.28#ibcon#enter wrdev, iclass 33, count 0 2006.182.07:31:11.28#ibcon#first serial, iclass 33, count 0 2006.182.07:31:11.28#ibcon#enter sib2, iclass 33, count 0 2006.182.07:31:11.28#ibcon#flushed, iclass 33, count 0 2006.182.07:31:11.28#ibcon#about to write, iclass 33, count 0 2006.182.07:31:11.28#ibcon#wrote, iclass 33, count 0 2006.182.07:31:11.28#ibcon#about to read 3, iclass 33, count 0 2006.182.07:31:11.30#ibcon#read 3, iclass 33, count 0 2006.182.07:31:11.30#ibcon#about to read 4, iclass 33, count 0 2006.182.07:31:11.30#ibcon#read 4, iclass 33, count 0 2006.182.07:31:11.30#ibcon#about to read 5, iclass 33, count 0 2006.182.07:31:11.30#ibcon#read 5, iclass 33, count 0 2006.182.07:31:11.30#ibcon#about to read 6, iclass 33, count 0 2006.182.07:31:11.30#ibcon#read 6, iclass 33, count 0 2006.182.07:31:11.30#ibcon#end of sib2, iclass 33, count 0 2006.182.07:31:11.30#ibcon#*mode == 0, iclass 33, count 0 2006.182.07:31:11.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.07:31:11.30#ibcon#[27=USB\r\n] 2006.182.07:31:11.30#ibcon#*before write, iclass 33, count 0 2006.182.07:31:11.30#ibcon#enter sib2, iclass 33, count 0 2006.182.07:31:11.30#ibcon#flushed, iclass 33, count 0 2006.182.07:31:11.30#ibcon#about to write, iclass 33, count 0 2006.182.07:31:11.30#ibcon#wrote, iclass 33, count 0 2006.182.07:31:11.30#ibcon#about to read 3, iclass 33, count 0 2006.182.07:31:11.33#ibcon#read 3, iclass 33, count 0 2006.182.07:31:11.33#ibcon#about to read 4, iclass 33, count 0 2006.182.07:31:11.33#ibcon#read 4, iclass 33, count 0 2006.182.07:31:11.33#ibcon#about to read 5, iclass 33, count 0 2006.182.07:31:11.33#ibcon#read 5, iclass 33, count 0 2006.182.07:31:11.33#ibcon#about to read 6, iclass 33, count 0 2006.182.07:31:11.33#ibcon#read 6, iclass 33, count 0 2006.182.07:31:11.33#ibcon#end of sib2, iclass 33, count 0 2006.182.07:31:11.33#ibcon#*after write, iclass 33, count 0 2006.182.07:31:11.33#ibcon#*before return 0, iclass 33, count 0 2006.182.07:31:11.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:11.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:31:11.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.07:31:11.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.07:31:11.33$vc4f8/vblo=3,656.99 2006.182.07:31:11.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.07:31:11.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.07:31:11.33#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:11.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:11.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:11.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:11.33#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:31:11.33#ibcon#first serial, iclass 35, count 0 2006.182.07:31:11.33#ibcon#enter sib2, iclass 35, count 0 2006.182.07:31:11.33#ibcon#flushed, iclass 35, count 0 2006.182.07:31:11.33#ibcon#about to write, iclass 35, count 0 2006.182.07:31:11.33#ibcon#wrote, iclass 35, count 0 2006.182.07:31:11.33#ibcon#about to read 3, iclass 35, count 0 2006.182.07:31:11.36#ibcon#read 3, iclass 35, count 0 2006.182.07:31:11.36#ibcon#about to read 4, iclass 35, count 0 2006.182.07:31:11.36#ibcon#read 4, iclass 35, count 0 2006.182.07:31:11.36#ibcon#about to read 5, iclass 35, count 0 2006.182.07:31:11.36#ibcon#read 5, iclass 35, count 0 2006.182.07:31:11.36#ibcon#about to read 6, iclass 35, count 0 2006.182.07:31:11.36#ibcon#read 6, iclass 35, count 0 2006.182.07:31:11.36#ibcon#end of sib2, iclass 35, count 0 2006.182.07:31:11.36#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:31:11.36#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:31:11.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:31:11.36#ibcon#*before write, iclass 35, count 0 2006.182.07:31:11.36#ibcon#enter sib2, iclass 35, count 0 2006.182.07:31:11.36#ibcon#flushed, iclass 35, count 0 2006.182.07:31:11.36#ibcon#about to write, iclass 35, count 0 2006.182.07:31:11.36#ibcon#wrote, iclass 35, count 0 2006.182.07:31:11.36#ibcon#about to read 3, iclass 35, count 0 2006.182.07:31:11.40#ibcon#read 3, iclass 35, count 0 2006.182.07:31:11.40#ibcon#about to read 4, iclass 35, count 0 2006.182.07:31:11.40#ibcon#read 4, iclass 35, count 0 2006.182.07:31:11.40#ibcon#about to read 5, iclass 35, count 0 2006.182.07:31:11.40#ibcon#read 5, iclass 35, count 0 2006.182.07:31:11.40#ibcon#about to read 6, iclass 35, count 0 2006.182.07:31:11.40#ibcon#read 6, iclass 35, count 0 2006.182.07:31:11.40#ibcon#end of sib2, iclass 35, count 0 2006.182.07:31:11.40#ibcon#*after write, iclass 35, count 0 2006.182.07:31:11.40#ibcon#*before return 0, iclass 35, count 0 2006.182.07:31:11.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:11.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:31:11.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:31:11.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:31:11.40$vc4f8/vb=3,4 2006.182.07:31:11.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.07:31:11.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.07:31:11.40#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:11.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:11.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:11.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:11.45#ibcon#enter wrdev, iclass 37, count 2 2006.182.07:31:11.45#ibcon#first serial, iclass 37, count 2 2006.182.07:31:11.45#ibcon#enter sib2, iclass 37, count 2 2006.182.07:31:11.45#ibcon#flushed, iclass 37, count 2 2006.182.07:31:11.45#ibcon#about to write, iclass 37, count 2 2006.182.07:31:11.45#ibcon#wrote, iclass 37, count 2 2006.182.07:31:11.45#ibcon#about to read 3, iclass 37, count 2 2006.182.07:31:11.47#ibcon#read 3, iclass 37, count 2 2006.182.07:31:11.47#ibcon#about to read 4, iclass 37, count 2 2006.182.07:31:11.47#ibcon#read 4, iclass 37, count 2 2006.182.07:31:11.47#ibcon#about to read 5, iclass 37, count 2 2006.182.07:31:11.47#ibcon#read 5, iclass 37, count 2 2006.182.07:31:11.47#ibcon#about to read 6, iclass 37, count 2 2006.182.07:31:11.47#ibcon#read 6, iclass 37, count 2 2006.182.07:31:11.47#ibcon#end of sib2, iclass 37, count 2 2006.182.07:31:11.47#ibcon#*mode == 0, iclass 37, count 2 2006.182.07:31:11.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.07:31:11.47#ibcon#[27=AT03-04\r\n] 2006.182.07:31:11.47#ibcon#*before write, iclass 37, count 2 2006.182.07:31:11.47#ibcon#enter sib2, iclass 37, count 2 2006.182.07:31:11.47#ibcon#flushed, iclass 37, count 2 2006.182.07:31:11.47#ibcon#about to write, iclass 37, count 2 2006.182.07:31:11.47#ibcon#wrote, iclass 37, count 2 2006.182.07:31:11.47#ibcon#about to read 3, iclass 37, count 2 2006.182.07:31:11.50#ibcon#read 3, iclass 37, count 2 2006.182.07:31:11.50#ibcon#about to read 4, iclass 37, count 2 2006.182.07:31:11.50#ibcon#read 4, iclass 37, count 2 2006.182.07:31:11.50#ibcon#about to read 5, iclass 37, count 2 2006.182.07:31:11.50#ibcon#read 5, iclass 37, count 2 2006.182.07:31:11.50#ibcon#about to read 6, iclass 37, count 2 2006.182.07:31:11.50#ibcon#read 6, iclass 37, count 2 2006.182.07:31:11.50#ibcon#end of sib2, iclass 37, count 2 2006.182.07:31:11.50#ibcon#*after write, iclass 37, count 2 2006.182.07:31:11.50#ibcon#*before return 0, iclass 37, count 2 2006.182.07:31:11.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:11.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:31:11.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.07:31:11.50#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:11.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:11.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:11.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:11.62#ibcon#enter wrdev, iclass 37, count 0 2006.182.07:31:11.62#ibcon#first serial, iclass 37, count 0 2006.182.07:31:11.62#ibcon#enter sib2, iclass 37, count 0 2006.182.07:31:11.62#ibcon#flushed, iclass 37, count 0 2006.182.07:31:11.62#ibcon#about to write, iclass 37, count 0 2006.182.07:31:11.62#ibcon#wrote, iclass 37, count 0 2006.182.07:31:11.62#ibcon#about to read 3, iclass 37, count 0 2006.182.07:31:11.64#ibcon#read 3, iclass 37, count 0 2006.182.07:31:11.64#ibcon#about to read 4, iclass 37, count 0 2006.182.07:31:11.64#ibcon#read 4, iclass 37, count 0 2006.182.07:31:11.64#ibcon#about to read 5, iclass 37, count 0 2006.182.07:31:11.64#ibcon#read 5, iclass 37, count 0 2006.182.07:31:11.64#ibcon#about to read 6, iclass 37, count 0 2006.182.07:31:11.64#ibcon#read 6, iclass 37, count 0 2006.182.07:31:11.64#ibcon#end of sib2, iclass 37, count 0 2006.182.07:31:11.64#ibcon#*mode == 0, iclass 37, count 0 2006.182.07:31:11.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.07:31:11.64#ibcon#[27=USB\r\n] 2006.182.07:31:11.64#ibcon#*before write, iclass 37, count 0 2006.182.07:31:11.64#ibcon#enter sib2, iclass 37, count 0 2006.182.07:31:11.64#ibcon#flushed, iclass 37, count 0 2006.182.07:31:11.64#ibcon#about to write, iclass 37, count 0 2006.182.07:31:11.64#ibcon#wrote, iclass 37, count 0 2006.182.07:31:11.64#ibcon#about to read 3, iclass 37, count 0 2006.182.07:31:11.67#ibcon#read 3, iclass 37, count 0 2006.182.07:31:11.67#ibcon#about to read 4, iclass 37, count 0 2006.182.07:31:11.67#ibcon#read 4, iclass 37, count 0 2006.182.07:31:11.67#ibcon#about to read 5, iclass 37, count 0 2006.182.07:31:11.67#ibcon#read 5, iclass 37, count 0 2006.182.07:31:11.67#ibcon#about to read 6, iclass 37, count 0 2006.182.07:31:11.67#ibcon#read 6, iclass 37, count 0 2006.182.07:31:11.67#ibcon#end of sib2, iclass 37, count 0 2006.182.07:31:11.67#ibcon#*after write, iclass 37, count 0 2006.182.07:31:11.67#ibcon#*before return 0, iclass 37, count 0 2006.182.07:31:11.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:11.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:31:11.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.07:31:11.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.07:31:11.67$vc4f8/vblo=4,712.99 2006.182.07:31:11.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.07:31:11.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.07:31:11.67#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:11.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:11.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:11.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:11.67#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:31:11.67#ibcon#first serial, iclass 39, count 0 2006.182.07:31:11.67#ibcon#enter sib2, iclass 39, count 0 2006.182.07:31:11.67#ibcon#flushed, iclass 39, count 0 2006.182.07:31:11.67#ibcon#about to write, iclass 39, count 0 2006.182.07:31:11.67#ibcon#wrote, iclass 39, count 0 2006.182.07:31:11.67#ibcon#about to read 3, iclass 39, count 0 2006.182.07:31:11.69#ibcon#read 3, iclass 39, count 0 2006.182.07:31:11.69#ibcon#about to read 4, iclass 39, count 0 2006.182.07:31:11.69#ibcon#read 4, iclass 39, count 0 2006.182.07:31:11.69#ibcon#about to read 5, iclass 39, count 0 2006.182.07:31:11.69#ibcon#read 5, iclass 39, count 0 2006.182.07:31:11.69#ibcon#about to read 6, iclass 39, count 0 2006.182.07:31:11.69#ibcon#read 6, iclass 39, count 0 2006.182.07:31:11.69#ibcon#end of sib2, iclass 39, count 0 2006.182.07:31:11.69#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:31:11.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:31:11.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:31:11.69#ibcon#*before write, iclass 39, count 0 2006.182.07:31:11.69#ibcon#enter sib2, iclass 39, count 0 2006.182.07:31:11.69#ibcon#flushed, iclass 39, count 0 2006.182.07:31:11.69#ibcon#about to write, iclass 39, count 0 2006.182.07:31:11.69#ibcon#wrote, iclass 39, count 0 2006.182.07:31:11.69#ibcon#about to read 3, iclass 39, count 0 2006.182.07:31:11.73#ibcon#read 3, iclass 39, count 0 2006.182.07:31:11.73#ibcon#about to read 4, iclass 39, count 0 2006.182.07:31:11.73#ibcon#read 4, iclass 39, count 0 2006.182.07:31:11.73#ibcon#about to read 5, iclass 39, count 0 2006.182.07:31:11.73#ibcon#read 5, iclass 39, count 0 2006.182.07:31:11.73#ibcon#about to read 6, iclass 39, count 0 2006.182.07:31:11.73#ibcon#read 6, iclass 39, count 0 2006.182.07:31:11.73#ibcon#end of sib2, iclass 39, count 0 2006.182.07:31:11.73#ibcon#*after write, iclass 39, count 0 2006.182.07:31:11.73#ibcon#*before return 0, iclass 39, count 0 2006.182.07:31:11.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:11.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:31:11.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:31:11.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:31:11.73$vc4f8/vb=4,4 2006.182.07:31:11.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.07:31:11.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.07:31:11.73#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:11.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:11.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:11.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:11.79#ibcon#enter wrdev, iclass 3, count 2 2006.182.07:31:11.79#ibcon#first serial, iclass 3, count 2 2006.182.07:31:11.79#ibcon#enter sib2, iclass 3, count 2 2006.182.07:31:11.79#ibcon#flushed, iclass 3, count 2 2006.182.07:31:11.79#ibcon#about to write, iclass 3, count 2 2006.182.07:31:11.79#ibcon#wrote, iclass 3, count 2 2006.182.07:31:11.79#ibcon#about to read 3, iclass 3, count 2 2006.182.07:31:11.81#ibcon#read 3, iclass 3, count 2 2006.182.07:31:11.81#ibcon#about to read 4, iclass 3, count 2 2006.182.07:31:11.81#ibcon#read 4, iclass 3, count 2 2006.182.07:31:11.81#ibcon#about to read 5, iclass 3, count 2 2006.182.07:31:11.81#ibcon#read 5, iclass 3, count 2 2006.182.07:31:11.81#ibcon#about to read 6, iclass 3, count 2 2006.182.07:31:11.81#ibcon#read 6, iclass 3, count 2 2006.182.07:31:11.81#ibcon#end of sib2, iclass 3, count 2 2006.182.07:31:11.81#ibcon#*mode == 0, iclass 3, count 2 2006.182.07:31:11.81#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.07:31:11.81#ibcon#[27=AT04-04\r\n] 2006.182.07:31:11.81#ibcon#*before write, iclass 3, count 2 2006.182.07:31:11.81#ibcon#enter sib2, iclass 3, count 2 2006.182.07:31:11.81#ibcon#flushed, iclass 3, count 2 2006.182.07:31:11.81#ibcon#about to write, iclass 3, count 2 2006.182.07:31:11.81#ibcon#wrote, iclass 3, count 2 2006.182.07:31:11.81#ibcon#about to read 3, iclass 3, count 2 2006.182.07:31:11.84#ibcon#read 3, iclass 3, count 2 2006.182.07:31:11.84#ibcon#about to read 4, iclass 3, count 2 2006.182.07:31:11.84#ibcon#read 4, iclass 3, count 2 2006.182.07:31:11.84#ibcon#about to read 5, iclass 3, count 2 2006.182.07:31:11.84#ibcon#read 5, iclass 3, count 2 2006.182.07:31:11.84#ibcon#about to read 6, iclass 3, count 2 2006.182.07:31:11.84#ibcon#read 6, iclass 3, count 2 2006.182.07:31:11.84#ibcon#end of sib2, iclass 3, count 2 2006.182.07:31:11.84#ibcon#*after write, iclass 3, count 2 2006.182.07:31:11.84#ibcon#*before return 0, iclass 3, count 2 2006.182.07:31:11.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:11.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:31:11.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.07:31:11.84#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:11.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:11.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:11.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:11.96#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:31:11.96#ibcon#first serial, iclass 3, count 0 2006.182.07:31:11.96#ibcon#enter sib2, iclass 3, count 0 2006.182.07:31:11.96#ibcon#flushed, iclass 3, count 0 2006.182.07:31:11.96#ibcon#about to write, iclass 3, count 0 2006.182.07:31:11.96#ibcon#wrote, iclass 3, count 0 2006.182.07:31:11.96#ibcon#about to read 3, iclass 3, count 0 2006.182.07:31:11.98#ibcon#read 3, iclass 3, count 0 2006.182.07:31:11.98#ibcon#about to read 4, iclass 3, count 0 2006.182.07:31:11.98#ibcon#read 4, iclass 3, count 0 2006.182.07:31:11.98#ibcon#about to read 5, iclass 3, count 0 2006.182.07:31:11.98#ibcon#read 5, iclass 3, count 0 2006.182.07:31:11.98#ibcon#about to read 6, iclass 3, count 0 2006.182.07:31:11.98#ibcon#read 6, iclass 3, count 0 2006.182.07:31:11.98#ibcon#end of sib2, iclass 3, count 0 2006.182.07:31:11.98#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:31:11.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:31:11.98#ibcon#[27=USB\r\n] 2006.182.07:31:11.98#ibcon#*before write, iclass 3, count 0 2006.182.07:31:11.98#ibcon#enter sib2, iclass 3, count 0 2006.182.07:31:11.98#ibcon#flushed, iclass 3, count 0 2006.182.07:31:11.98#ibcon#about to write, iclass 3, count 0 2006.182.07:31:11.98#ibcon#wrote, iclass 3, count 0 2006.182.07:31:11.98#ibcon#about to read 3, iclass 3, count 0 2006.182.07:31:12.01#ibcon#read 3, iclass 3, count 0 2006.182.07:31:12.01#ibcon#about to read 4, iclass 3, count 0 2006.182.07:31:12.01#ibcon#read 4, iclass 3, count 0 2006.182.07:31:12.01#ibcon#about to read 5, iclass 3, count 0 2006.182.07:31:12.01#ibcon#read 5, iclass 3, count 0 2006.182.07:31:12.01#ibcon#about to read 6, iclass 3, count 0 2006.182.07:31:12.01#ibcon#read 6, iclass 3, count 0 2006.182.07:31:12.01#ibcon#end of sib2, iclass 3, count 0 2006.182.07:31:12.01#ibcon#*after write, iclass 3, count 0 2006.182.07:31:12.01#ibcon#*before return 0, iclass 3, count 0 2006.182.07:31:12.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:12.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:31:12.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:31:12.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:31:12.01$vc4f8/vblo=5,744.99 2006.182.07:31:12.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.07:31:12.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.07:31:12.01#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:12.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:12.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:12.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:12.01#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:31:12.01#ibcon#first serial, iclass 5, count 0 2006.182.07:31:12.01#ibcon#enter sib2, iclass 5, count 0 2006.182.07:31:12.01#ibcon#flushed, iclass 5, count 0 2006.182.07:31:12.01#ibcon#about to write, iclass 5, count 0 2006.182.07:31:12.01#ibcon#wrote, iclass 5, count 0 2006.182.07:31:12.01#ibcon#about to read 3, iclass 5, count 0 2006.182.07:31:12.04#ibcon#read 3, iclass 5, count 0 2006.182.07:31:12.04#ibcon#about to read 4, iclass 5, count 0 2006.182.07:31:12.04#ibcon#read 4, iclass 5, count 0 2006.182.07:31:12.04#ibcon#about to read 5, iclass 5, count 0 2006.182.07:31:12.04#ibcon#read 5, iclass 5, count 0 2006.182.07:31:12.04#ibcon#about to read 6, iclass 5, count 0 2006.182.07:31:12.04#ibcon#read 6, iclass 5, count 0 2006.182.07:31:12.04#ibcon#end of sib2, iclass 5, count 0 2006.182.07:31:12.04#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:31:12.04#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:31:12.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:31:12.04#ibcon#*before write, iclass 5, count 0 2006.182.07:31:12.04#ibcon#enter sib2, iclass 5, count 0 2006.182.07:31:12.04#ibcon#flushed, iclass 5, count 0 2006.182.07:31:12.04#ibcon#about to write, iclass 5, count 0 2006.182.07:31:12.04#ibcon#wrote, iclass 5, count 0 2006.182.07:31:12.04#ibcon#about to read 3, iclass 5, count 0 2006.182.07:31:12.08#ibcon#read 3, iclass 5, count 0 2006.182.07:31:12.08#ibcon#about to read 4, iclass 5, count 0 2006.182.07:31:12.08#ibcon#read 4, iclass 5, count 0 2006.182.07:31:12.08#ibcon#about to read 5, iclass 5, count 0 2006.182.07:31:12.08#ibcon#read 5, iclass 5, count 0 2006.182.07:31:12.08#ibcon#about to read 6, iclass 5, count 0 2006.182.07:31:12.08#ibcon#read 6, iclass 5, count 0 2006.182.07:31:12.08#ibcon#end of sib2, iclass 5, count 0 2006.182.07:31:12.08#ibcon#*after write, iclass 5, count 0 2006.182.07:31:12.08#ibcon#*before return 0, iclass 5, count 0 2006.182.07:31:12.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:12.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:31:12.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:31:12.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:31:12.08$vc4f8/vb=5,4 2006.182.07:31:12.08#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.07:31:12.08#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.07:31:12.08#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:12.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:12.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:12.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:12.13#ibcon#enter wrdev, iclass 7, count 2 2006.182.07:31:12.13#ibcon#first serial, iclass 7, count 2 2006.182.07:31:12.13#ibcon#enter sib2, iclass 7, count 2 2006.182.07:31:12.13#ibcon#flushed, iclass 7, count 2 2006.182.07:31:12.13#ibcon#about to write, iclass 7, count 2 2006.182.07:31:12.13#ibcon#wrote, iclass 7, count 2 2006.182.07:31:12.13#ibcon#about to read 3, iclass 7, count 2 2006.182.07:31:12.15#ibcon#read 3, iclass 7, count 2 2006.182.07:31:12.15#ibcon#about to read 4, iclass 7, count 2 2006.182.07:31:12.15#ibcon#read 4, iclass 7, count 2 2006.182.07:31:12.15#ibcon#about to read 5, iclass 7, count 2 2006.182.07:31:12.15#ibcon#read 5, iclass 7, count 2 2006.182.07:31:12.15#ibcon#about to read 6, iclass 7, count 2 2006.182.07:31:12.15#ibcon#read 6, iclass 7, count 2 2006.182.07:31:12.15#ibcon#end of sib2, iclass 7, count 2 2006.182.07:31:12.15#ibcon#*mode == 0, iclass 7, count 2 2006.182.07:31:12.15#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.07:31:12.15#ibcon#[27=AT05-04\r\n] 2006.182.07:31:12.15#ibcon#*before write, iclass 7, count 2 2006.182.07:31:12.15#ibcon#enter sib2, iclass 7, count 2 2006.182.07:31:12.15#ibcon#flushed, iclass 7, count 2 2006.182.07:31:12.15#ibcon#about to write, iclass 7, count 2 2006.182.07:31:12.15#ibcon#wrote, iclass 7, count 2 2006.182.07:31:12.15#ibcon#about to read 3, iclass 7, count 2 2006.182.07:31:12.18#ibcon#read 3, iclass 7, count 2 2006.182.07:31:12.18#ibcon#about to read 4, iclass 7, count 2 2006.182.07:31:12.18#ibcon#read 4, iclass 7, count 2 2006.182.07:31:12.18#ibcon#about to read 5, iclass 7, count 2 2006.182.07:31:12.18#ibcon#read 5, iclass 7, count 2 2006.182.07:31:12.18#ibcon#about to read 6, iclass 7, count 2 2006.182.07:31:12.18#ibcon#read 6, iclass 7, count 2 2006.182.07:31:12.18#ibcon#end of sib2, iclass 7, count 2 2006.182.07:31:12.18#ibcon#*after write, iclass 7, count 2 2006.182.07:31:12.18#ibcon#*before return 0, iclass 7, count 2 2006.182.07:31:12.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:12.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:31:12.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.07:31:12.18#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:12.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:12.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:12.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:12.30#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:31:12.30#ibcon#first serial, iclass 7, count 0 2006.182.07:31:12.30#ibcon#enter sib2, iclass 7, count 0 2006.182.07:31:12.30#ibcon#flushed, iclass 7, count 0 2006.182.07:31:12.30#ibcon#about to write, iclass 7, count 0 2006.182.07:31:12.30#ibcon#wrote, iclass 7, count 0 2006.182.07:31:12.30#ibcon#about to read 3, iclass 7, count 0 2006.182.07:31:12.32#ibcon#read 3, iclass 7, count 0 2006.182.07:31:12.32#ibcon#about to read 4, iclass 7, count 0 2006.182.07:31:12.32#ibcon#read 4, iclass 7, count 0 2006.182.07:31:12.32#ibcon#about to read 5, iclass 7, count 0 2006.182.07:31:12.32#ibcon#read 5, iclass 7, count 0 2006.182.07:31:12.32#ibcon#about to read 6, iclass 7, count 0 2006.182.07:31:12.32#ibcon#read 6, iclass 7, count 0 2006.182.07:31:12.32#ibcon#end of sib2, iclass 7, count 0 2006.182.07:31:12.32#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:31:12.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:31:12.32#ibcon#[27=USB\r\n] 2006.182.07:31:12.32#ibcon#*before write, iclass 7, count 0 2006.182.07:31:12.32#ibcon#enter sib2, iclass 7, count 0 2006.182.07:31:12.32#ibcon#flushed, iclass 7, count 0 2006.182.07:31:12.32#ibcon#about to write, iclass 7, count 0 2006.182.07:31:12.32#ibcon#wrote, iclass 7, count 0 2006.182.07:31:12.32#ibcon#about to read 3, iclass 7, count 0 2006.182.07:31:12.35#ibcon#read 3, iclass 7, count 0 2006.182.07:31:12.35#ibcon#about to read 4, iclass 7, count 0 2006.182.07:31:12.35#ibcon#read 4, iclass 7, count 0 2006.182.07:31:12.35#ibcon#about to read 5, iclass 7, count 0 2006.182.07:31:12.35#ibcon#read 5, iclass 7, count 0 2006.182.07:31:12.35#ibcon#about to read 6, iclass 7, count 0 2006.182.07:31:12.35#ibcon#read 6, iclass 7, count 0 2006.182.07:31:12.35#ibcon#end of sib2, iclass 7, count 0 2006.182.07:31:12.35#ibcon#*after write, iclass 7, count 0 2006.182.07:31:12.35#ibcon#*before return 0, iclass 7, count 0 2006.182.07:31:12.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:12.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:31:12.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:31:12.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:31:12.35$vc4f8/vblo=6,752.99 2006.182.07:31:12.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.07:31:12.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.07:31:12.35#ibcon#ireg 17 cls_cnt 0 2006.182.07:31:12.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:12.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:12.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:12.35#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:31:12.35#ibcon#first serial, iclass 11, count 0 2006.182.07:31:12.35#ibcon#enter sib2, iclass 11, count 0 2006.182.07:31:12.35#ibcon#flushed, iclass 11, count 0 2006.182.07:31:12.35#ibcon#about to write, iclass 11, count 0 2006.182.07:31:12.35#ibcon#wrote, iclass 11, count 0 2006.182.07:31:12.35#ibcon#about to read 3, iclass 11, count 0 2006.182.07:31:12.37#ibcon#read 3, iclass 11, count 0 2006.182.07:31:12.37#ibcon#about to read 4, iclass 11, count 0 2006.182.07:31:12.37#ibcon#read 4, iclass 11, count 0 2006.182.07:31:12.37#ibcon#about to read 5, iclass 11, count 0 2006.182.07:31:12.37#ibcon#read 5, iclass 11, count 0 2006.182.07:31:12.37#ibcon#about to read 6, iclass 11, count 0 2006.182.07:31:12.37#ibcon#read 6, iclass 11, count 0 2006.182.07:31:12.37#ibcon#end of sib2, iclass 11, count 0 2006.182.07:31:12.37#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:31:12.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:31:12.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:31:12.37#ibcon#*before write, iclass 11, count 0 2006.182.07:31:12.37#ibcon#enter sib2, iclass 11, count 0 2006.182.07:31:12.37#ibcon#flushed, iclass 11, count 0 2006.182.07:31:12.37#ibcon#about to write, iclass 11, count 0 2006.182.07:31:12.37#ibcon#wrote, iclass 11, count 0 2006.182.07:31:12.37#ibcon#about to read 3, iclass 11, count 0 2006.182.07:31:12.41#ibcon#read 3, iclass 11, count 0 2006.182.07:31:12.41#ibcon#about to read 4, iclass 11, count 0 2006.182.07:31:12.41#ibcon#read 4, iclass 11, count 0 2006.182.07:31:12.41#ibcon#about to read 5, iclass 11, count 0 2006.182.07:31:12.41#ibcon#read 5, iclass 11, count 0 2006.182.07:31:12.41#ibcon#about to read 6, iclass 11, count 0 2006.182.07:31:12.41#ibcon#read 6, iclass 11, count 0 2006.182.07:31:12.41#ibcon#end of sib2, iclass 11, count 0 2006.182.07:31:12.41#ibcon#*after write, iclass 11, count 0 2006.182.07:31:12.41#ibcon#*before return 0, iclass 11, count 0 2006.182.07:31:12.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:12.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:31:12.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:31:12.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:31:12.41$vc4f8/vb=6,4 2006.182.07:31:12.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.07:31:12.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.07:31:12.41#ibcon#ireg 11 cls_cnt 2 2006.182.07:31:12.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:12.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:12.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:12.47#ibcon#enter wrdev, iclass 13, count 2 2006.182.07:31:12.47#ibcon#first serial, iclass 13, count 2 2006.182.07:31:12.47#ibcon#enter sib2, iclass 13, count 2 2006.182.07:31:12.47#ibcon#flushed, iclass 13, count 2 2006.182.07:31:12.47#ibcon#about to write, iclass 13, count 2 2006.182.07:31:12.47#ibcon#wrote, iclass 13, count 2 2006.182.07:31:12.47#ibcon#about to read 3, iclass 13, count 2 2006.182.07:31:12.49#ibcon#read 3, iclass 13, count 2 2006.182.07:31:12.49#ibcon#about to read 4, iclass 13, count 2 2006.182.07:31:12.49#ibcon#read 4, iclass 13, count 2 2006.182.07:31:12.49#ibcon#about to read 5, iclass 13, count 2 2006.182.07:31:12.49#ibcon#read 5, iclass 13, count 2 2006.182.07:31:12.49#ibcon#about to read 6, iclass 13, count 2 2006.182.07:31:12.49#ibcon#read 6, iclass 13, count 2 2006.182.07:31:12.49#ibcon#end of sib2, iclass 13, count 2 2006.182.07:31:12.49#ibcon#*mode == 0, iclass 13, count 2 2006.182.07:31:12.49#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.07:31:12.49#ibcon#[27=AT06-04\r\n] 2006.182.07:31:12.49#ibcon#*before write, iclass 13, count 2 2006.182.07:31:12.49#ibcon#enter sib2, iclass 13, count 2 2006.182.07:31:12.49#ibcon#flushed, iclass 13, count 2 2006.182.07:31:12.49#ibcon#about to write, iclass 13, count 2 2006.182.07:31:12.49#ibcon#wrote, iclass 13, count 2 2006.182.07:31:12.49#ibcon#about to read 3, iclass 13, count 2 2006.182.07:31:12.52#ibcon#read 3, iclass 13, count 2 2006.182.07:31:12.52#ibcon#about to read 4, iclass 13, count 2 2006.182.07:31:12.52#ibcon#read 4, iclass 13, count 2 2006.182.07:31:12.52#ibcon#about to read 5, iclass 13, count 2 2006.182.07:31:12.52#ibcon#read 5, iclass 13, count 2 2006.182.07:31:12.52#ibcon#about to read 6, iclass 13, count 2 2006.182.07:31:12.52#ibcon#read 6, iclass 13, count 2 2006.182.07:31:12.52#ibcon#end of sib2, iclass 13, count 2 2006.182.07:31:12.52#ibcon#*after write, iclass 13, count 2 2006.182.07:31:12.52#ibcon#*before return 0, iclass 13, count 2 2006.182.07:31:12.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:12.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:31:12.52#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.07:31:12.52#ibcon#ireg 7 cls_cnt 0 2006.182.07:31:12.52#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:12.64#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:12.64#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:12.64#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:31:12.64#ibcon#first serial, iclass 13, count 0 2006.182.07:31:12.64#ibcon#enter sib2, iclass 13, count 0 2006.182.07:31:12.64#ibcon#flushed, iclass 13, count 0 2006.182.07:31:12.64#ibcon#about to write, iclass 13, count 0 2006.182.07:31:12.64#ibcon#wrote, iclass 13, count 0 2006.182.07:31:12.64#ibcon#about to read 3, iclass 13, count 0 2006.182.07:31:12.66#ibcon#read 3, iclass 13, count 0 2006.182.07:31:12.66#ibcon#about to read 4, iclass 13, count 0 2006.182.07:31:12.66#ibcon#read 4, iclass 13, count 0 2006.182.07:31:12.66#ibcon#about to read 5, iclass 13, count 0 2006.182.07:31:12.66#ibcon#read 5, iclass 13, count 0 2006.182.07:31:12.66#ibcon#about to read 6, iclass 13, count 0 2006.182.07:31:12.66#ibcon#read 6, iclass 13, count 0 2006.182.07:31:12.66#ibcon#end of sib2, iclass 13, count 0 2006.182.07:31:12.66#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:31:12.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:31:12.66#ibcon#[27=USB\r\n] 2006.182.07:31:12.66#ibcon#*before write, iclass 13, count 0 2006.182.07:31:12.66#ibcon#enter sib2, iclass 13, count 0 2006.182.07:31:12.66#ibcon#flushed, iclass 13, count 0 2006.182.07:31:12.66#ibcon#about to write, iclass 13, count 0 2006.182.07:31:12.66#ibcon#wrote, iclass 13, count 0 2006.182.07:31:12.66#ibcon#about to read 3, iclass 13, count 0 2006.182.07:31:12.69#ibcon#read 3, iclass 13, count 0 2006.182.07:31:12.69#ibcon#about to read 4, iclass 13, count 0 2006.182.07:31:12.69#ibcon#read 4, iclass 13, count 0 2006.182.07:31:12.69#ibcon#about to read 5, iclass 13, count 0 2006.182.07:31:12.69#ibcon#read 5, iclass 13, count 0 2006.182.07:31:12.69#ibcon#about to read 6, iclass 13, count 0 2006.182.07:31:12.69#ibcon#read 6, iclass 13, count 0 2006.182.07:31:12.69#ibcon#end of sib2, iclass 13, count 0 2006.182.07:31:12.69#ibcon#*after write, iclass 13, count 0 2006.182.07:31:12.69#ibcon#*before return 0, iclass 13, count 0 2006.182.07:31:12.69#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:12.69#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:31:12.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:31:12.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:31:12.69$vc4f8/vabw=wide 2006.182.07:31:12.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.07:31:12.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.07:31:12.69#ibcon#ireg 8 cls_cnt 0 2006.182.07:31:12.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:12.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:12.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:12.69#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:31:12.69#ibcon#first serial, iclass 15, count 0 2006.182.07:31:12.69#ibcon#enter sib2, iclass 15, count 0 2006.182.07:31:12.69#ibcon#flushed, iclass 15, count 0 2006.182.07:31:12.69#ibcon#about to write, iclass 15, count 0 2006.182.07:31:12.69#ibcon#wrote, iclass 15, count 0 2006.182.07:31:12.69#ibcon#about to read 3, iclass 15, count 0 2006.182.07:31:12.71#ibcon#read 3, iclass 15, count 0 2006.182.07:31:12.71#ibcon#about to read 4, iclass 15, count 0 2006.182.07:31:12.71#ibcon#read 4, iclass 15, count 0 2006.182.07:31:12.71#ibcon#about to read 5, iclass 15, count 0 2006.182.07:31:12.71#ibcon#read 5, iclass 15, count 0 2006.182.07:31:12.71#ibcon#about to read 6, iclass 15, count 0 2006.182.07:31:12.71#ibcon#read 6, iclass 15, count 0 2006.182.07:31:12.71#ibcon#end of sib2, iclass 15, count 0 2006.182.07:31:12.71#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:31:12.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:31:12.71#ibcon#[25=BW32\r\n] 2006.182.07:31:12.71#ibcon#*before write, iclass 15, count 0 2006.182.07:31:12.71#ibcon#enter sib2, iclass 15, count 0 2006.182.07:31:12.71#ibcon#flushed, iclass 15, count 0 2006.182.07:31:12.71#ibcon#about to write, iclass 15, count 0 2006.182.07:31:12.71#ibcon#wrote, iclass 15, count 0 2006.182.07:31:12.71#ibcon#about to read 3, iclass 15, count 0 2006.182.07:31:12.74#ibcon#read 3, iclass 15, count 0 2006.182.07:31:12.74#ibcon#about to read 4, iclass 15, count 0 2006.182.07:31:12.74#ibcon#read 4, iclass 15, count 0 2006.182.07:31:12.74#ibcon#about to read 5, iclass 15, count 0 2006.182.07:31:12.74#ibcon#read 5, iclass 15, count 0 2006.182.07:31:12.74#ibcon#about to read 6, iclass 15, count 0 2006.182.07:31:12.74#ibcon#read 6, iclass 15, count 0 2006.182.07:31:12.74#ibcon#end of sib2, iclass 15, count 0 2006.182.07:31:12.74#ibcon#*after write, iclass 15, count 0 2006.182.07:31:12.74#ibcon#*before return 0, iclass 15, count 0 2006.182.07:31:12.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:12.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:31:12.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:31:12.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:31:12.74$vc4f8/vbbw=wide 2006.182.07:31:12.74#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.07:31:12.74#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.07:31:12.74#ibcon#ireg 8 cls_cnt 0 2006.182.07:31:12.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:31:12.81#abcon#<5=/04 0.5 1.5 27.50 811002.8\r\n> 2006.182.07:31:12.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:31:12.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:31:12.81#ibcon#enter wrdev, iclass 17, count 0 2006.182.07:31:12.81#ibcon#first serial, iclass 17, count 0 2006.182.07:31:12.81#ibcon#enter sib2, iclass 17, count 0 2006.182.07:31:12.81#ibcon#flushed, iclass 17, count 0 2006.182.07:31:12.81#ibcon#about to write, iclass 17, count 0 2006.182.07:31:12.81#ibcon#wrote, iclass 17, count 0 2006.182.07:31:12.81#ibcon#about to read 3, iclass 17, count 0 2006.182.07:31:12.83#ibcon#read 3, iclass 17, count 0 2006.182.07:31:12.83#ibcon#about to read 4, iclass 17, count 0 2006.182.07:31:12.83#ibcon#read 4, iclass 17, count 0 2006.182.07:31:12.83#ibcon#about to read 5, iclass 17, count 0 2006.182.07:31:12.83#ibcon#read 5, iclass 17, count 0 2006.182.07:31:12.83#ibcon#about to read 6, iclass 17, count 0 2006.182.07:31:12.83#ibcon#read 6, iclass 17, count 0 2006.182.07:31:12.83#ibcon#end of sib2, iclass 17, count 0 2006.182.07:31:12.83#ibcon#*mode == 0, iclass 17, count 0 2006.182.07:31:12.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.07:31:12.83#ibcon#[27=BW32\r\n] 2006.182.07:31:12.83#ibcon#*before write, iclass 17, count 0 2006.182.07:31:12.83#ibcon#enter sib2, iclass 17, count 0 2006.182.07:31:12.83#ibcon#flushed, iclass 17, count 0 2006.182.07:31:12.83#ibcon#about to write, iclass 17, count 0 2006.182.07:31:12.83#ibcon#wrote, iclass 17, count 0 2006.182.07:31:12.83#ibcon#about to read 3, iclass 17, count 0 2006.182.07:31:12.83#abcon#{5=INTERFACE CLEAR} 2006.182.07:31:12.86#ibcon#read 3, iclass 17, count 0 2006.182.07:31:12.86#ibcon#about to read 4, iclass 17, count 0 2006.182.07:31:12.86#ibcon#read 4, iclass 17, count 0 2006.182.07:31:12.86#ibcon#about to read 5, iclass 17, count 0 2006.182.07:31:12.86#ibcon#read 5, iclass 17, count 0 2006.182.07:31:12.86#ibcon#about to read 6, iclass 17, count 0 2006.182.07:31:12.86#ibcon#read 6, iclass 17, count 0 2006.182.07:31:12.86#ibcon#end of sib2, iclass 17, count 0 2006.182.07:31:12.86#ibcon#*after write, iclass 17, count 0 2006.182.07:31:12.86#ibcon#*before return 0, iclass 17, count 0 2006.182.07:31:12.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:31:12.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:31:12.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.07:31:12.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.07:31:12.86$4f8m12a/ifd4f 2006.182.07:31:12.86$ifd4f/lo= 2006.182.07:31:12.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:31:12.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:31:12.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:31:12.86$ifd4f/patch= 2006.182.07:31:12.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:31:12.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:31:12.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:31:12.86$4f8m12a/"form=m,16.000,1:2 2006.182.07:31:12.86$4f8m12a/"tpicd 2006.182.07:31:12.86$4f8m12a/echo=off 2006.182.07:31:12.86$4f8m12a/xlog=off 2006.182.07:31:12.86:!2006.182.07:33:20 2006.182.07:31:51.14#trakl#Source acquired 2006.182.07:31:52.14#flagr#flagr/antenna,acquired 2006.182.07:33:20.00:preob 2006.182.07:33:20.14/onsource/TRACKING 2006.182.07:33:20.14:!2006.182.07:33:30 2006.182.07:33:30.00:data_valid=on 2006.182.07:33:30.00:midob 2006.182.07:33:31.14/onsource/TRACKING 2006.182.07:33:31.14/wx/27.46,1002.8,81 2006.182.07:33:31.20/cable/+6.4673E-03 2006.182.07:33:32.29/va/01,08,usb,yes,29,30 2006.182.07:33:32.29/va/02,07,usb,yes,29,31 2006.182.07:33:32.29/va/03,06,usb,yes,31,31 2006.182.07:33:32.29/va/04,07,usb,yes,30,32 2006.182.07:33:32.29/va/05,07,usb,yes,31,33 2006.182.07:33:32.29/va/06,06,usb,yes,30,30 2006.182.07:33:32.29/va/07,06,usb,yes,30,30 2006.182.07:33:32.29/va/08,07,usb,yes,29,28 2006.182.07:33:32.52/valo/01,532.99,yes,locked 2006.182.07:33:32.52/valo/02,572.99,yes,locked 2006.182.07:33:32.52/valo/03,672.99,yes,locked 2006.182.07:33:32.52/valo/04,832.99,yes,locked 2006.182.07:33:32.52/valo/05,652.99,yes,locked 2006.182.07:33:32.52/valo/06,772.99,yes,locked 2006.182.07:33:32.52/valo/07,832.99,yes,locked 2006.182.07:33:32.52/valo/08,852.99,yes,locked 2006.182.07:33:33.61/vb/01,04,usb,yes,29,28 2006.182.07:33:33.61/vb/02,04,usb,yes,31,32 2006.182.07:33:33.61/vb/03,04,usb,yes,27,31 2006.182.07:33:33.61/vb/04,04,usb,yes,28,28 2006.182.07:33:33.61/vb/05,04,usb,yes,27,31 2006.182.07:33:33.61/vb/06,04,usb,yes,28,30 2006.182.07:33:33.61/vb/07,04,usb,yes,30,29 2006.182.07:33:33.61/vb/08,04,usb,yes,27,31 2006.182.07:33:33.85/vblo/01,632.99,yes,locked 2006.182.07:33:33.85/vblo/02,640.99,yes,locked 2006.182.07:33:33.85/vblo/03,656.99,yes,locked 2006.182.07:33:33.85/vblo/04,712.99,yes,locked 2006.182.07:33:33.85/vblo/05,744.99,yes,locked 2006.182.07:33:33.85/vblo/06,752.99,yes,locked 2006.182.07:33:33.85/vblo/07,734.99,yes,locked 2006.182.07:33:33.85/vblo/08,744.99,yes,locked 2006.182.07:33:34.00/vabw/8 2006.182.07:33:34.15/vbbw/8 2006.182.07:33:34.24/xfe/off,on,14.5 2006.182.07:33:34.63/ifatt/23,28,28,28 2006.182.07:33:35.07/fmout-gps/S +3.35E-07 2006.182.07:33:35.15:!2006.182.07:34:30 2006.182.07:34:30.00:data_valid=off 2006.182.07:34:30.00:postob 2006.182.07:34:30.20/cable/+6.4674E-03 2006.182.07:34:30.20/wx/27.45,1002.9,82 2006.182.07:34:31.08/fmout-gps/S +3.35E-07 2006.182.07:34:31.08:scan_name=182-0735,k06182,60 2006.182.07:34:31.09:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.182.07:34:31.14#flagr#flagr/antenna,new-source 2006.182.07:34:32.14:checkk5 2006.182.07:34:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:34:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:34:33.29/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:34:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:34:34.03/chk_obsdata//k5ts1/T1820733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:34:34.40/chk_obsdata//k5ts2/T1820733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:34:34.77/chk_obsdata//k5ts3/T1820733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:34:35.14/chk_obsdata//k5ts4/T1820733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:34:35.82/k5log//k5ts1_log_newline 2006.182.07:34:36.51/k5log//k5ts2_log_newline 2006.182.07:34:37.20/k5log//k5ts3_log_newline 2006.182.07:34:37.88/k5log//k5ts4_log_newline 2006.182.07:34:37.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:34:37.91:4f8m12a=1 2006.182.07:34:37.91$4f8m12a/echo=on 2006.182.07:34:37.91$4f8m12a/pcalon 2006.182.07:34:37.91$pcalon/"no phase cal control is implemented here 2006.182.07:34:37.91$4f8m12a/"tpicd=stop 2006.182.07:34:37.91$4f8m12a/vc4f8 2006.182.07:34:37.91$vc4f8/valo=1,532.99 2006.182.07:34:37.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.07:34:37.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.07:34:37.91#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:37.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:37.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:37.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:37.91#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:34:37.91#ibcon#first serial, iclass 32, count 0 2006.182.07:34:37.91#ibcon#enter sib2, iclass 32, count 0 2006.182.07:34:37.91#ibcon#flushed, iclass 32, count 0 2006.182.07:34:37.91#ibcon#about to write, iclass 32, count 0 2006.182.07:34:37.91#ibcon#wrote, iclass 32, count 0 2006.182.07:34:37.91#ibcon#about to read 3, iclass 32, count 0 2006.182.07:34:37.95#ibcon#read 3, iclass 32, count 0 2006.182.07:34:37.95#ibcon#about to read 4, iclass 32, count 0 2006.182.07:34:37.95#ibcon#read 4, iclass 32, count 0 2006.182.07:34:37.95#ibcon#about to read 5, iclass 32, count 0 2006.182.07:34:37.95#ibcon#read 5, iclass 32, count 0 2006.182.07:34:37.95#ibcon#about to read 6, iclass 32, count 0 2006.182.07:34:37.95#ibcon#read 6, iclass 32, count 0 2006.182.07:34:37.95#ibcon#end of sib2, iclass 32, count 0 2006.182.07:34:37.95#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:34:37.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:34:37.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:34:37.95#ibcon#*before write, iclass 32, count 0 2006.182.07:34:37.95#ibcon#enter sib2, iclass 32, count 0 2006.182.07:34:37.95#ibcon#flushed, iclass 32, count 0 2006.182.07:34:37.95#ibcon#about to write, iclass 32, count 0 2006.182.07:34:37.95#ibcon#wrote, iclass 32, count 0 2006.182.07:34:37.95#ibcon#about to read 3, iclass 32, count 0 2006.182.07:34:38.00#ibcon#read 3, iclass 32, count 0 2006.182.07:34:38.00#ibcon#about to read 4, iclass 32, count 0 2006.182.07:34:38.00#ibcon#read 4, iclass 32, count 0 2006.182.07:34:38.00#ibcon#about to read 5, iclass 32, count 0 2006.182.07:34:38.00#ibcon#read 5, iclass 32, count 0 2006.182.07:34:38.00#ibcon#about to read 6, iclass 32, count 0 2006.182.07:34:38.00#ibcon#read 6, iclass 32, count 0 2006.182.07:34:38.00#ibcon#end of sib2, iclass 32, count 0 2006.182.07:34:38.00#ibcon#*after write, iclass 32, count 0 2006.182.07:34:38.00#ibcon#*before return 0, iclass 32, count 0 2006.182.07:34:38.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:38.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:38.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:34:38.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:34:38.00$vc4f8/va=1,8 2006.182.07:34:38.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.07:34:38.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.07:34:38.00#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:38.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:38.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:38.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:38.00#ibcon#enter wrdev, iclass 34, count 2 2006.182.07:34:38.00#ibcon#first serial, iclass 34, count 2 2006.182.07:34:38.00#ibcon#enter sib2, iclass 34, count 2 2006.182.07:34:38.00#ibcon#flushed, iclass 34, count 2 2006.182.07:34:38.00#ibcon#about to write, iclass 34, count 2 2006.182.07:34:38.00#ibcon#wrote, iclass 34, count 2 2006.182.07:34:38.00#ibcon#about to read 3, iclass 34, count 2 2006.182.07:34:38.03#ibcon#read 3, iclass 34, count 2 2006.182.07:34:38.03#ibcon#about to read 4, iclass 34, count 2 2006.182.07:34:38.03#ibcon#read 4, iclass 34, count 2 2006.182.07:34:38.03#ibcon#about to read 5, iclass 34, count 2 2006.182.07:34:38.03#ibcon#read 5, iclass 34, count 2 2006.182.07:34:38.03#ibcon#about to read 6, iclass 34, count 2 2006.182.07:34:38.03#ibcon#read 6, iclass 34, count 2 2006.182.07:34:38.03#ibcon#end of sib2, iclass 34, count 2 2006.182.07:34:38.03#ibcon#*mode == 0, iclass 34, count 2 2006.182.07:34:38.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.07:34:38.03#ibcon#[25=AT01-08\r\n] 2006.182.07:34:38.03#ibcon#*before write, iclass 34, count 2 2006.182.07:34:38.03#ibcon#enter sib2, iclass 34, count 2 2006.182.07:34:38.03#ibcon#flushed, iclass 34, count 2 2006.182.07:34:38.03#ibcon#about to write, iclass 34, count 2 2006.182.07:34:38.03#ibcon#wrote, iclass 34, count 2 2006.182.07:34:38.03#ibcon#about to read 3, iclass 34, count 2 2006.182.07:34:38.06#ibcon#read 3, iclass 34, count 2 2006.182.07:34:38.06#ibcon#about to read 4, iclass 34, count 2 2006.182.07:34:38.06#ibcon#read 4, iclass 34, count 2 2006.182.07:34:38.06#ibcon#about to read 5, iclass 34, count 2 2006.182.07:34:38.06#ibcon#read 5, iclass 34, count 2 2006.182.07:34:38.06#ibcon#about to read 6, iclass 34, count 2 2006.182.07:34:38.06#ibcon#read 6, iclass 34, count 2 2006.182.07:34:38.06#ibcon#end of sib2, iclass 34, count 2 2006.182.07:34:38.06#ibcon#*after write, iclass 34, count 2 2006.182.07:34:38.06#ibcon#*before return 0, iclass 34, count 2 2006.182.07:34:38.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:38.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:38.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.07:34:38.06#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:38.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:38.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:38.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:38.18#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:34:38.18#ibcon#first serial, iclass 34, count 0 2006.182.07:34:38.18#ibcon#enter sib2, iclass 34, count 0 2006.182.07:34:38.18#ibcon#flushed, iclass 34, count 0 2006.182.07:34:38.18#ibcon#about to write, iclass 34, count 0 2006.182.07:34:38.18#ibcon#wrote, iclass 34, count 0 2006.182.07:34:38.18#ibcon#about to read 3, iclass 34, count 0 2006.182.07:34:38.20#ibcon#read 3, iclass 34, count 0 2006.182.07:34:38.20#ibcon#about to read 4, iclass 34, count 0 2006.182.07:34:38.20#ibcon#read 4, iclass 34, count 0 2006.182.07:34:38.20#ibcon#about to read 5, iclass 34, count 0 2006.182.07:34:38.20#ibcon#read 5, iclass 34, count 0 2006.182.07:34:38.20#ibcon#about to read 6, iclass 34, count 0 2006.182.07:34:38.20#ibcon#read 6, iclass 34, count 0 2006.182.07:34:38.20#ibcon#end of sib2, iclass 34, count 0 2006.182.07:34:38.20#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:34:38.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:34:38.20#ibcon#[25=USB\r\n] 2006.182.07:34:38.20#ibcon#*before write, iclass 34, count 0 2006.182.07:34:38.20#ibcon#enter sib2, iclass 34, count 0 2006.182.07:34:38.20#ibcon#flushed, iclass 34, count 0 2006.182.07:34:38.20#ibcon#about to write, iclass 34, count 0 2006.182.07:34:38.20#ibcon#wrote, iclass 34, count 0 2006.182.07:34:38.20#ibcon#about to read 3, iclass 34, count 0 2006.182.07:34:38.23#ibcon#read 3, iclass 34, count 0 2006.182.07:34:38.23#ibcon#about to read 4, iclass 34, count 0 2006.182.07:34:38.23#ibcon#read 4, iclass 34, count 0 2006.182.07:34:38.23#ibcon#about to read 5, iclass 34, count 0 2006.182.07:34:38.23#ibcon#read 5, iclass 34, count 0 2006.182.07:34:38.23#ibcon#about to read 6, iclass 34, count 0 2006.182.07:34:38.23#ibcon#read 6, iclass 34, count 0 2006.182.07:34:38.23#ibcon#end of sib2, iclass 34, count 0 2006.182.07:34:38.23#ibcon#*after write, iclass 34, count 0 2006.182.07:34:38.23#ibcon#*before return 0, iclass 34, count 0 2006.182.07:34:38.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:38.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:38.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:34:38.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:34:38.23$vc4f8/valo=2,572.99 2006.182.07:34:38.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.07:34:38.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.07:34:38.23#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:38.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:38.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:38.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:38.23#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:34:38.23#ibcon#first serial, iclass 36, count 0 2006.182.07:34:38.23#ibcon#enter sib2, iclass 36, count 0 2006.182.07:34:38.23#ibcon#flushed, iclass 36, count 0 2006.182.07:34:38.23#ibcon#about to write, iclass 36, count 0 2006.182.07:34:38.23#ibcon#wrote, iclass 36, count 0 2006.182.07:34:38.23#ibcon#about to read 3, iclass 36, count 0 2006.182.07:34:38.25#ibcon#read 3, iclass 36, count 0 2006.182.07:34:38.25#ibcon#about to read 4, iclass 36, count 0 2006.182.07:34:38.25#ibcon#read 4, iclass 36, count 0 2006.182.07:34:38.25#ibcon#about to read 5, iclass 36, count 0 2006.182.07:34:38.25#ibcon#read 5, iclass 36, count 0 2006.182.07:34:38.25#ibcon#about to read 6, iclass 36, count 0 2006.182.07:34:38.25#ibcon#read 6, iclass 36, count 0 2006.182.07:34:38.25#ibcon#end of sib2, iclass 36, count 0 2006.182.07:34:38.25#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:34:38.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:34:38.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:34:38.25#ibcon#*before write, iclass 36, count 0 2006.182.07:34:38.25#ibcon#enter sib2, iclass 36, count 0 2006.182.07:34:38.25#ibcon#flushed, iclass 36, count 0 2006.182.07:34:38.25#ibcon#about to write, iclass 36, count 0 2006.182.07:34:38.25#ibcon#wrote, iclass 36, count 0 2006.182.07:34:38.25#ibcon#about to read 3, iclass 36, count 0 2006.182.07:34:38.29#ibcon#read 3, iclass 36, count 0 2006.182.07:34:38.29#ibcon#about to read 4, iclass 36, count 0 2006.182.07:34:38.29#ibcon#read 4, iclass 36, count 0 2006.182.07:34:38.29#ibcon#about to read 5, iclass 36, count 0 2006.182.07:34:38.29#ibcon#read 5, iclass 36, count 0 2006.182.07:34:38.29#ibcon#about to read 6, iclass 36, count 0 2006.182.07:34:38.29#ibcon#read 6, iclass 36, count 0 2006.182.07:34:38.29#ibcon#end of sib2, iclass 36, count 0 2006.182.07:34:38.29#ibcon#*after write, iclass 36, count 0 2006.182.07:34:38.29#ibcon#*before return 0, iclass 36, count 0 2006.182.07:34:38.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:38.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:38.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:34:38.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:34:38.29$vc4f8/va=2,7 2006.182.07:34:38.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.07:34:38.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.07:34:38.29#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:38.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:38.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:38.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:38.35#ibcon#enter wrdev, iclass 38, count 2 2006.182.07:34:38.35#ibcon#first serial, iclass 38, count 2 2006.182.07:34:38.35#ibcon#enter sib2, iclass 38, count 2 2006.182.07:34:38.35#ibcon#flushed, iclass 38, count 2 2006.182.07:34:38.35#ibcon#about to write, iclass 38, count 2 2006.182.07:34:38.35#ibcon#wrote, iclass 38, count 2 2006.182.07:34:38.35#ibcon#about to read 3, iclass 38, count 2 2006.182.07:34:38.37#ibcon#read 3, iclass 38, count 2 2006.182.07:34:38.37#ibcon#about to read 4, iclass 38, count 2 2006.182.07:34:38.37#ibcon#read 4, iclass 38, count 2 2006.182.07:34:38.37#ibcon#about to read 5, iclass 38, count 2 2006.182.07:34:38.37#ibcon#read 5, iclass 38, count 2 2006.182.07:34:38.37#ibcon#about to read 6, iclass 38, count 2 2006.182.07:34:38.37#ibcon#read 6, iclass 38, count 2 2006.182.07:34:38.37#ibcon#end of sib2, iclass 38, count 2 2006.182.07:34:38.37#ibcon#*mode == 0, iclass 38, count 2 2006.182.07:34:38.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.07:34:38.37#ibcon#[25=AT02-07\r\n] 2006.182.07:34:38.37#ibcon#*before write, iclass 38, count 2 2006.182.07:34:38.37#ibcon#enter sib2, iclass 38, count 2 2006.182.07:34:38.37#ibcon#flushed, iclass 38, count 2 2006.182.07:34:38.37#ibcon#about to write, iclass 38, count 2 2006.182.07:34:38.37#ibcon#wrote, iclass 38, count 2 2006.182.07:34:38.37#ibcon#about to read 3, iclass 38, count 2 2006.182.07:34:38.40#ibcon#read 3, iclass 38, count 2 2006.182.07:34:38.40#ibcon#about to read 4, iclass 38, count 2 2006.182.07:34:38.40#ibcon#read 4, iclass 38, count 2 2006.182.07:34:38.40#ibcon#about to read 5, iclass 38, count 2 2006.182.07:34:38.40#ibcon#read 5, iclass 38, count 2 2006.182.07:34:38.40#ibcon#about to read 6, iclass 38, count 2 2006.182.07:34:38.40#ibcon#read 6, iclass 38, count 2 2006.182.07:34:38.40#ibcon#end of sib2, iclass 38, count 2 2006.182.07:34:38.40#ibcon#*after write, iclass 38, count 2 2006.182.07:34:38.40#ibcon#*before return 0, iclass 38, count 2 2006.182.07:34:38.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:38.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:38.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.07:34:38.40#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:38.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:38.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:38.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:38.53#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:34:38.53#ibcon#first serial, iclass 38, count 0 2006.182.07:34:38.53#ibcon#enter sib2, iclass 38, count 0 2006.182.07:34:38.53#ibcon#flushed, iclass 38, count 0 2006.182.07:34:38.53#ibcon#about to write, iclass 38, count 0 2006.182.07:34:38.53#ibcon#wrote, iclass 38, count 0 2006.182.07:34:38.53#ibcon#about to read 3, iclass 38, count 0 2006.182.07:34:38.54#ibcon#read 3, iclass 38, count 0 2006.182.07:34:38.54#ibcon#about to read 4, iclass 38, count 0 2006.182.07:34:38.54#ibcon#read 4, iclass 38, count 0 2006.182.07:34:38.54#ibcon#about to read 5, iclass 38, count 0 2006.182.07:34:38.54#ibcon#read 5, iclass 38, count 0 2006.182.07:34:38.54#ibcon#about to read 6, iclass 38, count 0 2006.182.07:34:38.54#ibcon#read 6, iclass 38, count 0 2006.182.07:34:38.54#ibcon#end of sib2, iclass 38, count 0 2006.182.07:34:38.54#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:34:38.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:34:38.54#ibcon#[25=USB\r\n] 2006.182.07:34:38.54#ibcon#*before write, iclass 38, count 0 2006.182.07:34:38.54#ibcon#enter sib2, iclass 38, count 0 2006.182.07:34:38.54#ibcon#flushed, iclass 38, count 0 2006.182.07:34:38.54#ibcon#about to write, iclass 38, count 0 2006.182.07:34:38.54#ibcon#wrote, iclass 38, count 0 2006.182.07:34:38.54#ibcon#about to read 3, iclass 38, count 0 2006.182.07:34:38.57#ibcon#read 3, iclass 38, count 0 2006.182.07:34:38.57#ibcon#about to read 4, iclass 38, count 0 2006.182.07:34:38.57#ibcon#read 4, iclass 38, count 0 2006.182.07:34:38.57#ibcon#about to read 5, iclass 38, count 0 2006.182.07:34:38.57#ibcon#read 5, iclass 38, count 0 2006.182.07:34:38.57#ibcon#about to read 6, iclass 38, count 0 2006.182.07:34:38.57#ibcon#read 6, iclass 38, count 0 2006.182.07:34:38.57#ibcon#end of sib2, iclass 38, count 0 2006.182.07:34:38.57#ibcon#*after write, iclass 38, count 0 2006.182.07:34:38.57#ibcon#*before return 0, iclass 38, count 0 2006.182.07:34:38.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:38.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:38.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:34:38.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:34:38.57$vc4f8/valo=3,672.99 2006.182.07:34:38.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.07:34:38.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.07:34:38.57#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:38.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:38.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:38.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:38.57#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:34:38.57#ibcon#first serial, iclass 40, count 0 2006.182.07:34:38.57#ibcon#enter sib2, iclass 40, count 0 2006.182.07:34:38.57#ibcon#flushed, iclass 40, count 0 2006.182.07:34:38.57#ibcon#about to write, iclass 40, count 0 2006.182.07:34:38.57#ibcon#wrote, iclass 40, count 0 2006.182.07:34:38.57#ibcon#about to read 3, iclass 40, count 0 2006.182.07:34:38.60#ibcon#read 3, iclass 40, count 0 2006.182.07:34:38.60#ibcon#about to read 4, iclass 40, count 0 2006.182.07:34:38.60#ibcon#read 4, iclass 40, count 0 2006.182.07:34:38.60#ibcon#about to read 5, iclass 40, count 0 2006.182.07:34:38.60#ibcon#read 5, iclass 40, count 0 2006.182.07:34:38.60#ibcon#about to read 6, iclass 40, count 0 2006.182.07:34:38.60#ibcon#read 6, iclass 40, count 0 2006.182.07:34:38.60#ibcon#end of sib2, iclass 40, count 0 2006.182.07:34:38.60#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:34:38.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:34:38.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:34:38.60#ibcon#*before write, iclass 40, count 0 2006.182.07:34:38.60#ibcon#enter sib2, iclass 40, count 0 2006.182.07:34:38.60#ibcon#flushed, iclass 40, count 0 2006.182.07:34:38.60#ibcon#about to write, iclass 40, count 0 2006.182.07:34:38.60#ibcon#wrote, iclass 40, count 0 2006.182.07:34:38.60#ibcon#about to read 3, iclass 40, count 0 2006.182.07:34:38.64#ibcon#read 3, iclass 40, count 0 2006.182.07:34:38.64#ibcon#about to read 4, iclass 40, count 0 2006.182.07:34:38.64#ibcon#read 4, iclass 40, count 0 2006.182.07:34:38.64#ibcon#about to read 5, iclass 40, count 0 2006.182.07:34:38.64#ibcon#read 5, iclass 40, count 0 2006.182.07:34:38.64#ibcon#about to read 6, iclass 40, count 0 2006.182.07:34:38.64#ibcon#read 6, iclass 40, count 0 2006.182.07:34:38.64#ibcon#end of sib2, iclass 40, count 0 2006.182.07:34:38.64#ibcon#*after write, iclass 40, count 0 2006.182.07:34:38.64#ibcon#*before return 0, iclass 40, count 0 2006.182.07:34:38.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:38.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:38.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:34:38.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:34:38.64$vc4f8/va=3,6 2006.182.07:34:38.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.07:34:38.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.07:34:38.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:38.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:38.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:38.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:38.69#ibcon#enter wrdev, iclass 4, count 2 2006.182.07:34:38.69#ibcon#first serial, iclass 4, count 2 2006.182.07:34:38.69#ibcon#enter sib2, iclass 4, count 2 2006.182.07:34:38.69#ibcon#flushed, iclass 4, count 2 2006.182.07:34:38.69#ibcon#about to write, iclass 4, count 2 2006.182.07:34:38.69#ibcon#wrote, iclass 4, count 2 2006.182.07:34:38.69#ibcon#about to read 3, iclass 4, count 2 2006.182.07:34:38.71#ibcon#read 3, iclass 4, count 2 2006.182.07:34:38.71#ibcon#about to read 4, iclass 4, count 2 2006.182.07:34:38.71#ibcon#read 4, iclass 4, count 2 2006.182.07:34:38.71#ibcon#about to read 5, iclass 4, count 2 2006.182.07:34:38.71#ibcon#read 5, iclass 4, count 2 2006.182.07:34:38.71#ibcon#about to read 6, iclass 4, count 2 2006.182.07:34:38.71#ibcon#read 6, iclass 4, count 2 2006.182.07:34:38.71#ibcon#end of sib2, iclass 4, count 2 2006.182.07:34:38.71#ibcon#*mode == 0, iclass 4, count 2 2006.182.07:34:38.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.07:34:38.71#ibcon#[25=AT03-06\r\n] 2006.182.07:34:38.71#ibcon#*before write, iclass 4, count 2 2006.182.07:34:38.71#ibcon#enter sib2, iclass 4, count 2 2006.182.07:34:38.71#ibcon#flushed, iclass 4, count 2 2006.182.07:34:38.71#ibcon#about to write, iclass 4, count 2 2006.182.07:34:38.71#ibcon#wrote, iclass 4, count 2 2006.182.07:34:38.71#ibcon#about to read 3, iclass 4, count 2 2006.182.07:34:38.74#ibcon#read 3, iclass 4, count 2 2006.182.07:34:38.74#ibcon#about to read 4, iclass 4, count 2 2006.182.07:34:38.74#ibcon#read 4, iclass 4, count 2 2006.182.07:34:38.74#ibcon#about to read 5, iclass 4, count 2 2006.182.07:34:38.74#ibcon#read 5, iclass 4, count 2 2006.182.07:34:38.74#ibcon#about to read 6, iclass 4, count 2 2006.182.07:34:38.74#ibcon#read 6, iclass 4, count 2 2006.182.07:34:38.74#ibcon#end of sib2, iclass 4, count 2 2006.182.07:34:38.74#ibcon#*after write, iclass 4, count 2 2006.182.07:34:38.74#ibcon#*before return 0, iclass 4, count 2 2006.182.07:34:38.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:38.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:38.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.07:34:38.74#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:38.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:38.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:38.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:38.86#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:34:38.86#ibcon#first serial, iclass 4, count 0 2006.182.07:34:38.86#ibcon#enter sib2, iclass 4, count 0 2006.182.07:34:38.86#ibcon#flushed, iclass 4, count 0 2006.182.07:34:38.86#ibcon#about to write, iclass 4, count 0 2006.182.07:34:38.86#ibcon#wrote, iclass 4, count 0 2006.182.07:34:38.86#ibcon#about to read 3, iclass 4, count 0 2006.182.07:34:38.88#ibcon#read 3, iclass 4, count 0 2006.182.07:34:38.88#ibcon#about to read 4, iclass 4, count 0 2006.182.07:34:38.88#ibcon#read 4, iclass 4, count 0 2006.182.07:34:38.88#ibcon#about to read 5, iclass 4, count 0 2006.182.07:34:38.88#ibcon#read 5, iclass 4, count 0 2006.182.07:34:38.88#ibcon#about to read 6, iclass 4, count 0 2006.182.07:34:38.88#ibcon#read 6, iclass 4, count 0 2006.182.07:34:38.88#ibcon#end of sib2, iclass 4, count 0 2006.182.07:34:38.88#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:34:38.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:34:38.88#ibcon#[25=USB\r\n] 2006.182.07:34:38.88#ibcon#*before write, iclass 4, count 0 2006.182.07:34:38.88#ibcon#enter sib2, iclass 4, count 0 2006.182.07:34:38.88#ibcon#flushed, iclass 4, count 0 2006.182.07:34:38.88#ibcon#about to write, iclass 4, count 0 2006.182.07:34:38.88#ibcon#wrote, iclass 4, count 0 2006.182.07:34:38.88#ibcon#about to read 3, iclass 4, count 0 2006.182.07:34:38.91#ibcon#read 3, iclass 4, count 0 2006.182.07:34:38.91#ibcon#about to read 4, iclass 4, count 0 2006.182.07:34:38.91#ibcon#read 4, iclass 4, count 0 2006.182.07:34:38.91#ibcon#about to read 5, iclass 4, count 0 2006.182.07:34:38.91#ibcon#read 5, iclass 4, count 0 2006.182.07:34:38.91#ibcon#about to read 6, iclass 4, count 0 2006.182.07:34:38.91#ibcon#read 6, iclass 4, count 0 2006.182.07:34:38.91#ibcon#end of sib2, iclass 4, count 0 2006.182.07:34:38.91#ibcon#*after write, iclass 4, count 0 2006.182.07:34:38.91#ibcon#*before return 0, iclass 4, count 0 2006.182.07:34:38.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:38.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:38.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:34:38.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:34:38.91$vc4f8/valo=4,832.99 2006.182.07:34:38.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.07:34:38.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.07:34:38.91#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:38.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:38.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:38.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:38.91#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:34:38.91#ibcon#first serial, iclass 6, count 0 2006.182.07:34:38.91#ibcon#enter sib2, iclass 6, count 0 2006.182.07:34:38.91#ibcon#flushed, iclass 6, count 0 2006.182.07:34:38.91#ibcon#about to write, iclass 6, count 0 2006.182.07:34:38.91#ibcon#wrote, iclass 6, count 0 2006.182.07:34:38.91#ibcon#about to read 3, iclass 6, count 0 2006.182.07:34:38.93#ibcon#read 3, iclass 6, count 0 2006.182.07:34:38.93#ibcon#about to read 4, iclass 6, count 0 2006.182.07:34:38.93#ibcon#read 4, iclass 6, count 0 2006.182.07:34:38.93#ibcon#about to read 5, iclass 6, count 0 2006.182.07:34:38.93#ibcon#read 5, iclass 6, count 0 2006.182.07:34:38.93#ibcon#about to read 6, iclass 6, count 0 2006.182.07:34:38.93#ibcon#read 6, iclass 6, count 0 2006.182.07:34:38.93#ibcon#end of sib2, iclass 6, count 0 2006.182.07:34:38.93#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:34:38.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:34:38.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:34:38.93#ibcon#*before write, iclass 6, count 0 2006.182.07:34:38.93#ibcon#enter sib2, iclass 6, count 0 2006.182.07:34:38.93#ibcon#flushed, iclass 6, count 0 2006.182.07:34:38.93#ibcon#about to write, iclass 6, count 0 2006.182.07:34:38.93#ibcon#wrote, iclass 6, count 0 2006.182.07:34:38.93#ibcon#about to read 3, iclass 6, count 0 2006.182.07:34:38.97#ibcon#read 3, iclass 6, count 0 2006.182.07:34:38.97#ibcon#about to read 4, iclass 6, count 0 2006.182.07:34:38.97#ibcon#read 4, iclass 6, count 0 2006.182.07:34:38.97#ibcon#about to read 5, iclass 6, count 0 2006.182.07:34:38.97#ibcon#read 5, iclass 6, count 0 2006.182.07:34:38.97#ibcon#about to read 6, iclass 6, count 0 2006.182.07:34:38.97#ibcon#read 6, iclass 6, count 0 2006.182.07:34:38.97#ibcon#end of sib2, iclass 6, count 0 2006.182.07:34:38.97#ibcon#*after write, iclass 6, count 0 2006.182.07:34:38.97#ibcon#*before return 0, iclass 6, count 0 2006.182.07:34:38.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:38.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:38.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:34:38.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:34:38.97$vc4f8/va=4,7 2006.182.07:34:38.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.07:34:38.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.07:34:38.97#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:38.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:39.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:39.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:39.03#ibcon#enter wrdev, iclass 10, count 2 2006.182.07:34:39.03#ibcon#first serial, iclass 10, count 2 2006.182.07:34:39.03#ibcon#enter sib2, iclass 10, count 2 2006.182.07:34:39.03#ibcon#flushed, iclass 10, count 2 2006.182.07:34:39.03#ibcon#about to write, iclass 10, count 2 2006.182.07:34:39.03#ibcon#wrote, iclass 10, count 2 2006.182.07:34:39.03#ibcon#about to read 3, iclass 10, count 2 2006.182.07:34:39.05#ibcon#read 3, iclass 10, count 2 2006.182.07:34:39.05#ibcon#about to read 4, iclass 10, count 2 2006.182.07:34:39.05#ibcon#read 4, iclass 10, count 2 2006.182.07:34:39.05#ibcon#about to read 5, iclass 10, count 2 2006.182.07:34:39.05#ibcon#read 5, iclass 10, count 2 2006.182.07:34:39.05#ibcon#about to read 6, iclass 10, count 2 2006.182.07:34:39.05#ibcon#read 6, iclass 10, count 2 2006.182.07:34:39.05#ibcon#end of sib2, iclass 10, count 2 2006.182.07:34:39.05#ibcon#*mode == 0, iclass 10, count 2 2006.182.07:34:39.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.07:34:39.05#ibcon#[25=AT04-07\r\n] 2006.182.07:34:39.05#ibcon#*before write, iclass 10, count 2 2006.182.07:34:39.05#ibcon#enter sib2, iclass 10, count 2 2006.182.07:34:39.05#ibcon#flushed, iclass 10, count 2 2006.182.07:34:39.05#ibcon#about to write, iclass 10, count 2 2006.182.07:34:39.05#ibcon#wrote, iclass 10, count 2 2006.182.07:34:39.05#ibcon#about to read 3, iclass 10, count 2 2006.182.07:34:39.08#ibcon#read 3, iclass 10, count 2 2006.182.07:34:39.08#ibcon#about to read 4, iclass 10, count 2 2006.182.07:34:39.08#ibcon#read 4, iclass 10, count 2 2006.182.07:34:39.08#ibcon#about to read 5, iclass 10, count 2 2006.182.07:34:39.08#ibcon#read 5, iclass 10, count 2 2006.182.07:34:39.08#ibcon#about to read 6, iclass 10, count 2 2006.182.07:34:39.08#ibcon#read 6, iclass 10, count 2 2006.182.07:34:39.08#ibcon#end of sib2, iclass 10, count 2 2006.182.07:34:39.08#ibcon#*after write, iclass 10, count 2 2006.182.07:34:39.08#ibcon#*before return 0, iclass 10, count 2 2006.182.07:34:39.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:39.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:39.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.07:34:39.08#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:39.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:39.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:39.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:39.20#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:34:39.20#ibcon#first serial, iclass 10, count 0 2006.182.07:34:39.20#ibcon#enter sib2, iclass 10, count 0 2006.182.07:34:39.20#ibcon#flushed, iclass 10, count 0 2006.182.07:34:39.20#ibcon#about to write, iclass 10, count 0 2006.182.07:34:39.20#ibcon#wrote, iclass 10, count 0 2006.182.07:34:39.20#ibcon#about to read 3, iclass 10, count 0 2006.182.07:34:39.22#ibcon#read 3, iclass 10, count 0 2006.182.07:34:39.22#ibcon#about to read 4, iclass 10, count 0 2006.182.07:34:39.22#ibcon#read 4, iclass 10, count 0 2006.182.07:34:39.22#ibcon#about to read 5, iclass 10, count 0 2006.182.07:34:39.22#ibcon#read 5, iclass 10, count 0 2006.182.07:34:39.22#ibcon#about to read 6, iclass 10, count 0 2006.182.07:34:39.22#ibcon#read 6, iclass 10, count 0 2006.182.07:34:39.22#ibcon#end of sib2, iclass 10, count 0 2006.182.07:34:39.22#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:34:39.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:34:39.22#ibcon#[25=USB\r\n] 2006.182.07:34:39.22#ibcon#*before write, iclass 10, count 0 2006.182.07:34:39.22#ibcon#enter sib2, iclass 10, count 0 2006.182.07:34:39.22#ibcon#flushed, iclass 10, count 0 2006.182.07:34:39.22#ibcon#about to write, iclass 10, count 0 2006.182.07:34:39.22#ibcon#wrote, iclass 10, count 0 2006.182.07:34:39.22#ibcon#about to read 3, iclass 10, count 0 2006.182.07:34:39.25#ibcon#read 3, iclass 10, count 0 2006.182.07:34:39.25#ibcon#about to read 4, iclass 10, count 0 2006.182.07:34:39.25#ibcon#read 4, iclass 10, count 0 2006.182.07:34:39.25#ibcon#about to read 5, iclass 10, count 0 2006.182.07:34:39.25#ibcon#read 5, iclass 10, count 0 2006.182.07:34:39.25#ibcon#about to read 6, iclass 10, count 0 2006.182.07:34:39.25#ibcon#read 6, iclass 10, count 0 2006.182.07:34:39.25#ibcon#end of sib2, iclass 10, count 0 2006.182.07:34:39.25#ibcon#*after write, iclass 10, count 0 2006.182.07:34:39.25#ibcon#*before return 0, iclass 10, count 0 2006.182.07:34:39.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:39.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:39.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:34:39.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:34:39.25$vc4f8/valo=5,652.99 2006.182.07:34:39.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.07:34:39.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.07:34:39.25#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:39.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:39.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:39.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:39.25#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:34:39.25#ibcon#first serial, iclass 12, count 0 2006.182.07:34:39.25#ibcon#enter sib2, iclass 12, count 0 2006.182.07:34:39.25#ibcon#flushed, iclass 12, count 0 2006.182.07:34:39.25#ibcon#about to write, iclass 12, count 0 2006.182.07:34:39.25#ibcon#wrote, iclass 12, count 0 2006.182.07:34:39.25#ibcon#about to read 3, iclass 12, count 0 2006.182.07:34:39.27#ibcon#read 3, iclass 12, count 0 2006.182.07:34:39.27#ibcon#about to read 4, iclass 12, count 0 2006.182.07:34:39.27#ibcon#read 4, iclass 12, count 0 2006.182.07:34:39.27#ibcon#about to read 5, iclass 12, count 0 2006.182.07:34:39.27#ibcon#read 5, iclass 12, count 0 2006.182.07:34:39.27#ibcon#about to read 6, iclass 12, count 0 2006.182.07:34:39.27#ibcon#read 6, iclass 12, count 0 2006.182.07:34:39.27#ibcon#end of sib2, iclass 12, count 0 2006.182.07:34:39.27#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:34:39.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:34:39.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:34:39.27#ibcon#*before write, iclass 12, count 0 2006.182.07:34:39.27#ibcon#enter sib2, iclass 12, count 0 2006.182.07:34:39.27#ibcon#flushed, iclass 12, count 0 2006.182.07:34:39.27#ibcon#about to write, iclass 12, count 0 2006.182.07:34:39.27#ibcon#wrote, iclass 12, count 0 2006.182.07:34:39.27#ibcon#about to read 3, iclass 12, count 0 2006.182.07:34:39.31#ibcon#read 3, iclass 12, count 0 2006.182.07:34:39.31#ibcon#about to read 4, iclass 12, count 0 2006.182.07:34:39.31#ibcon#read 4, iclass 12, count 0 2006.182.07:34:39.31#ibcon#about to read 5, iclass 12, count 0 2006.182.07:34:39.31#ibcon#read 5, iclass 12, count 0 2006.182.07:34:39.31#ibcon#about to read 6, iclass 12, count 0 2006.182.07:34:39.31#ibcon#read 6, iclass 12, count 0 2006.182.07:34:39.31#ibcon#end of sib2, iclass 12, count 0 2006.182.07:34:39.31#ibcon#*after write, iclass 12, count 0 2006.182.07:34:39.31#ibcon#*before return 0, iclass 12, count 0 2006.182.07:34:39.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:39.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:39.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:34:39.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:34:39.31$vc4f8/va=5,7 2006.182.07:34:39.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.07:34:39.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.07:34:39.31#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:39.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:39.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:39.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:39.37#ibcon#enter wrdev, iclass 14, count 2 2006.182.07:34:39.37#ibcon#first serial, iclass 14, count 2 2006.182.07:34:39.37#ibcon#enter sib2, iclass 14, count 2 2006.182.07:34:39.37#ibcon#flushed, iclass 14, count 2 2006.182.07:34:39.37#ibcon#about to write, iclass 14, count 2 2006.182.07:34:39.37#ibcon#wrote, iclass 14, count 2 2006.182.07:34:39.37#ibcon#about to read 3, iclass 14, count 2 2006.182.07:34:39.39#ibcon#read 3, iclass 14, count 2 2006.182.07:34:39.39#ibcon#about to read 4, iclass 14, count 2 2006.182.07:34:39.39#ibcon#read 4, iclass 14, count 2 2006.182.07:34:39.39#ibcon#about to read 5, iclass 14, count 2 2006.182.07:34:39.39#ibcon#read 5, iclass 14, count 2 2006.182.07:34:39.39#ibcon#about to read 6, iclass 14, count 2 2006.182.07:34:39.39#ibcon#read 6, iclass 14, count 2 2006.182.07:34:39.39#ibcon#end of sib2, iclass 14, count 2 2006.182.07:34:39.39#ibcon#*mode == 0, iclass 14, count 2 2006.182.07:34:39.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.07:34:39.39#ibcon#[25=AT05-07\r\n] 2006.182.07:34:39.39#ibcon#*before write, iclass 14, count 2 2006.182.07:34:39.39#ibcon#enter sib2, iclass 14, count 2 2006.182.07:34:39.39#ibcon#flushed, iclass 14, count 2 2006.182.07:34:39.39#ibcon#about to write, iclass 14, count 2 2006.182.07:34:39.39#ibcon#wrote, iclass 14, count 2 2006.182.07:34:39.39#ibcon#about to read 3, iclass 14, count 2 2006.182.07:34:39.42#ibcon#read 3, iclass 14, count 2 2006.182.07:34:39.42#ibcon#about to read 4, iclass 14, count 2 2006.182.07:34:39.42#ibcon#read 4, iclass 14, count 2 2006.182.07:34:39.42#ibcon#about to read 5, iclass 14, count 2 2006.182.07:34:39.42#ibcon#read 5, iclass 14, count 2 2006.182.07:34:39.42#ibcon#about to read 6, iclass 14, count 2 2006.182.07:34:39.42#ibcon#read 6, iclass 14, count 2 2006.182.07:34:39.42#ibcon#end of sib2, iclass 14, count 2 2006.182.07:34:39.42#ibcon#*after write, iclass 14, count 2 2006.182.07:34:39.42#ibcon#*before return 0, iclass 14, count 2 2006.182.07:34:39.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:39.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:39.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.07:34:39.42#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:39.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:39.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:39.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:39.54#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:34:39.54#ibcon#first serial, iclass 14, count 0 2006.182.07:34:39.54#ibcon#enter sib2, iclass 14, count 0 2006.182.07:34:39.54#ibcon#flushed, iclass 14, count 0 2006.182.07:34:39.54#ibcon#about to write, iclass 14, count 0 2006.182.07:34:39.54#ibcon#wrote, iclass 14, count 0 2006.182.07:34:39.54#ibcon#about to read 3, iclass 14, count 0 2006.182.07:34:39.56#ibcon#read 3, iclass 14, count 0 2006.182.07:34:39.56#ibcon#about to read 4, iclass 14, count 0 2006.182.07:34:39.56#ibcon#read 4, iclass 14, count 0 2006.182.07:34:39.56#ibcon#about to read 5, iclass 14, count 0 2006.182.07:34:39.56#ibcon#read 5, iclass 14, count 0 2006.182.07:34:39.56#ibcon#about to read 6, iclass 14, count 0 2006.182.07:34:39.56#ibcon#read 6, iclass 14, count 0 2006.182.07:34:39.56#ibcon#end of sib2, iclass 14, count 0 2006.182.07:34:39.56#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:34:39.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:34:39.56#ibcon#[25=USB\r\n] 2006.182.07:34:39.56#ibcon#*before write, iclass 14, count 0 2006.182.07:34:39.56#ibcon#enter sib2, iclass 14, count 0 2006.182.07:34:39.56#ibcon#flushed, iclass 14, count 0 2006.182.07:34:39.56#ibcon#about to write, iclass 14, count 0 2006.182.07:34:39.56#ibcon#wrote, iclass 14, count 0 2006.182.07:34:39.56#ibcon#about to read 3, iclass 14, count 0 2006.182.07:34:39.59#ibcon#read 3, iclass 14, count 0 2006.182.07:34:39.59#ibcon#about to read 4, iclass 14, count 0 2006.182.07:34:39.59#ibcon#read 4, iclass 14, count 0 2006.182.07:34:39.59#ibcon#about to read 5, iclass 14, count 0 2006.182.07:34:39.59#ibcon#read 5, iclass 14, count 0 2006.182.07:34:39.59#ibcon#about to read 6, iclass 14, count 0 2006.182.07:34:39.59#ibcon#read 6, iclass 14, count 0 2006.182.07:34:39.59#ibcon#end of sib2, iclass 14, count 0 2006.182.07:34:39.59#ibcon#*after write, iclass 14, count 0 2006.182.07:34:39.59#ibcon#*before return 0, iclass 14, count 0 2006.182.07:34:39.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:39.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:39.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:34:39.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:34:39.59$vc4f8/valo=6,772.99 2006.182.07:34:39.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.07:34:39.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.07:34:39.59#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:39.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:39.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:39.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:39.59#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:34:39.59#ibcon#first serial, iclass 16, count 0 2006.182.07:34:39.59#ibcon#enter sib2, iclass 16, count 0 2006.182.07:34:39.59#ibcon#flushed, iclass 16, count 0 2006.182.07:34:39.59#ibcon#about to write, iclass 16, count 0 2006.182.07:34:39.59#ibcon#wrote, iclass 16, count 0 2006.182.07:34:39.59#ibcon#about to read 3, iclass 16, count 0 2006.182.07:34:39.61#ibcon#read 3, iclass 16, count 0 2006.182.07:34:39.61#ibcon#about to read 4, iclass 16, count 0 2006.182.07:34:39.61#ibcon#read 4, iclass 16, count 0 2006.182.07:34:39.61#ibcon#about to read 5, iclass 16, count 0 2006.182.07:34:39.61#ibcon#read 5, iclass 16, count 0 2006.182.07:34:39.61#ibcon#about to read 6, iclass 16, count 0 2006.182.07:34:39.61#ibcon#read 6, iclass 16, count 0 2006.182.07:34:39.61#ibcon#end of sib2, iclass 16, count 0 2006.182.07:34:39.61#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:34:39.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:34:39.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:34:39.61#ibcon#*before write, iclass 16, count 0 2006.182.07:34:39.61#ibcon#enter sib2, iclass 16, count 0 2006.182.07:34:39.61#ibcon#flushed, iclass 16, count 0 2006.182.07:34:39.61#ibcon#about to write, iclass 16, count 0 2006.182.07:34:39.61#ibcon#wrote, iclass 16, count 0 2006.182.07:34:39.61#ibcon#about to read 3, iclass 16, count 0 2006.182.07:34:39.65#ibcon#read 3, iclass 16, count 0 2006.182.07:34:39.65#ibcon#about to read 4, iclass 16, count 0 2006.182.07:34:39.65#ibcon#read 4, iclass 16, count 0 2006.182.07:34:39.65#ibcon#about to read 5, iclass 16, count 0 2006.182.07:34:39.65#ibcon#read 5, iclass 16, count 0 2006.182.07:34:39.65#ibcon#about to read 6, iclass 16, count 0 2006.182.07:34:39.65#ibcon#read 6, iclass 16, count 0 2006.182.07:34:39.65#ibcon#end of sib2, iclass 16, count 0 2006.182.07:34:39.65#ibcon#*after write, iclass 16, count 0 2006.182.07:34:39.65#ibcon#*before return 0, iclass 16, count 0 2006.182.07:34:39.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:39.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:39.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:34:39.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:34:39.65$vc4f8/va=6,6 2006.182.07:34:39.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.07:34:39.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.07:34:39.65#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:39.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:34:39.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:34:39.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:34:39.71#ibcon#enter wrdev, iclass 18, count 2 2006.182.07:34:39.71#ibcon#first serial, iclass 18, count 2 2006.182.07:34:39.71#ibcon#enter sib2, iclass 18, count 2 2006.182.07:34:39.71#ibcon#flushed, iclass 18, count 2 2006.182.07:34:39.71#ibcon#about to write, iclass 18, count 2 2006.182.07:34:39.71#ibcon#wrote, iclass 18, count 2 2006.182.07:34:39.71#ibcon#about to read 3, iclass 18, count 2 2006.182.07:34:39.73#ibcon#read 3, iclass 18, count 2 2006.182.07:34:39.73#ibcon#about to read 4, iclass 18, count 2 2006.182.07:34:39.73#ibcon#read 4, iclass 18, count 2 2006.182.07:34:39.73#ibcon#about to read 5, iclass 18, count 2 2006.182.07:34:39.73#ibcon#read 5, iclass 18, count 2 2006.182.07:34:39.73#ibcon#about to read 6, iclass 18, count 2 2006.182.07:34:39.73#ibcon#read 6, iclass 18, count 2 2006.182.07:34:39.73#ibcon#end of sib2, iclass 18, count 2 2006.182.07:34:39.73#ibcon#*mode == 0, iclass 18, count 2 2006.182.07:34:39.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.07:34:39.73#ibcon#[25=AT06-06\r\n] 2006.182.07:34:39.73#ibcon#*before write, iclass 18, count 2 2006.182.07:34:39.73#ibcon#enter sib2, iclass 18, count 2 2006.182.07:34:39.73#ibcon#flushed, iclass 18, count 2 2006.182.07:34:39.73#ibcon#about to write, iclass 18, count 2 2006.182.07:34:39.73#ibcon#wrote, iclass 18, count 2 2006.182.07:34:39.73#ibcon#about to read 3, iclass 18, count 2 2006.182.07:34:39.76#ibcon#read 3, iclass 18, count 2 2006.182.07:34:39.76#ibcon#about to read 4, iclass 18, count 2 2006.182.07:34:39.76#ibcon#read 4, iclass 18, count 2 2006.182.07:34:39.76#ibcon#about to read 5, iclass 18, count 2 2006.182.07:34:39.76#ibcon#read 5, iclass 18, count 2 2006.182.07:34:39.76#ibcon#about to read 6, iclass 18, count 2 2006.182.07:34:39.76#ibcon#read 6, iclass 18, count 2 2006.182.07:34:39.76#ibcon#end of sib2, iclass 18, count 2 2006.182.07:34:39.76#ibcon#*after write, iclass 18, count 2 2006.182.07:34:39.76#ibcon#*before return 0, iclass 18, count 2 2006.182.07:34:39.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:34:39.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:34:39.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.07:34:39.76#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:39.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:34:39.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:34:39.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:34:39.88#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:34:39.88#ibcon#first serial, iclass 18, count 0 2006.182.07:34:39.88#ibcon#enter sib2, iclass 18, count 0 2006.182.07:34:39.88#ibcon#flushed, iclass 18, count 0 2006.182.07:34:39.88#ibcon#about to write, iclass 18, count 0 2006.182.07:34:39.88#ibcon#wrote, iclass 18, count 0 2006.182.07:34:39.88#ibcon#about to read 3, iclass 18, count 0 2006.182.07:34:39.90#ibcon#read 3, iclass 18, count 0 2006.182.07:34:39.90#ibcon#about to read 4, iclass 18, count 0 2006.182.07:34:39.90#ibcon#read 4, iclass 18, count 0 2006.182.07:34:39.90#ibcon#about to read 5, iclass 18, count 0 2006.182.07:34:39.90#ibcon#read 5, iclass 18, count 0 2006.182.07:34:39.90#ibcon#about to read 6, iclass 18, count 0 2006.182.07:34:39.90#ibcon#read 6, iclass 18, count 0 2006.182.07:34:39.90#ibcon#end of sib2, iclass 18, count 0 2006.182.07:34:39.90#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:34:39.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:34:39.90#ibcon#[25=USB\r\n] 2006.182.07:34:39.90#ibcon#*before write, iclass 18, count 0 2006.182.07:34:39.90#ibcon#enter sib2, iclass 18, count 0 2006.182.07:34:39.90#ibcon#flushed, iclass 18, count 0 2006.182.07:34:39.90#ibcon#about to write, iclass 18, count 0 2006.182.07:34:39.90#ibcon#wrote, iclass 18, count 0 2006.182.07:34:39.90#ibcon#about to read 3, iclass 18, count 0 2006.182.07:34:39.93#ibcon#read 3, iclass 18, count 0 2006.182.07:34:39.93#ibcon#about to read 4, iclass 18, count 0 2006.182.07:34:39.93#ibcon#read 4, iclass 18, count 0 2006.182.07:34:39.93#ibcon#about to read 5, iclass 18, count 0 2006.182.07:34:39.93#ibcon#read 5, iclass 18, count 0 2006.182.07:34:39.93#ibcon#about to read 6, iclass 18, count 0 2006.182.07:34:39.93#ibcon#read 6, iclass 18, count 0 2006.182.07:34:39.93#ibcon#end of sib2, iclass 18, count 0 2006.182.07:34:39.93#ibcon#*after write, iclass 18, count 0 2006.182.07:34:39.93#ibcon#*before return 0, iclass 18, count 0 2006.182.07:34:39.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:34:39.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:34:39.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:34:39.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:34:39.93$vc4f8/valo=7,832.99 2006.182.07:34:39.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.07:34:39.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.07:34:39.93#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:39.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:34:39.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:34:39.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:34:39.93#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:34:39.93#ibcon#first serial, iclass 20, count 0 2006.182.07:34:39.93#ibcon#enter sib2, iclass 20, count 0 2006.182.07:34:39.93#ibcon#flushed, iclass 20, count 0 2006.182.07:34:39.93#ibcon#about to write, iclass 20, count 0 2006.182.07:34:39.93#ibcon#wrote, iclass 20, count 0 2006.182.07:34:39.93#ibcon#about to read 3, iclass 20, count 0 2006.182.07:34:39.95#ibcon#read 3, iclass 20, count 0 2006.182.07:34:39.95#ibcon#about to read 4, iclass 20, count 0 2006.182.07:34:39.95#ibcon#read 4, iclass 20, count 0 2006.182.07:34:39.95#ibcon#about to read 5, iclass 20, count 0 2006.182.07:34:39.95#ibcon#read 5, iclass 20, count 0 2006.182.07:34:39.95#ibcon#about to read 6, iclass 20, count 0 2006.182.07:34:39.95#ibcon#read 6, iclass 20, count 0 2006.182.07:34:39.95#ibcon#end of sib2, iclass 20, count 0 2006.182.07:34:39.95#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:34:39.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:34:39.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:34:39.95#ibcon#*before write, iclass 20, count 0 2006.182.07:34:39.95#ibcon#enter sib2, iclass 20, count 0 2006.182.07:34:39.95#ibcon#flushed, iclass 20, count 0 2006.182.07:34:39.95#ibcon#about to write, iclass 20, count 0 2006.182.07:34:39.95#ibcon#wrote, iclass 20, count 0 2006.182.07:34:39.95#ibcon#about to read 3, iclass 20, count 0 2006.182.07:34:39.99#ibcon#read 3, iclass 20, count 0 2006.182.07:34:39.99#ibcon#about to read 4, iclass 20, count 0 2006.182.07:34:39.99#ibcon#read 4, iclass 20, count 0 2006.182.07:34:39.99#ibcon#about to read 5, iclass 20, count 0 2006.182.07:34:39.99#ibcon#read 5, iclass 20, count 0 2006.182.07:34:39.99#ibcon#about to read 6, iclass 20, count 0 2006.182.07:34:39.99#ibcon#read 6, iclass 20, count 0 2006.182.07:34:39.99#ibcon#end of sib2, iclass 20, count 0 2006.182.07:34:39.99#ibcon#*after write, iclass 20, count 0 2006.182.07:34:39.99#ibcon#*before return 0, iclass 20, count 0 2006.182.07:34:39.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:34:39.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:34:39.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:34:39.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:34:39.99$vc4f8/va=7,6 2006.182.07:34:39.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.07:34:39.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.07:34:39.99#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:39.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:34:40.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:34:40.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:34:40.05#ibcon#enter wrdev, iclass 22, count 2 2006.182.07:34:40.05#ibcon#first serial, iclass 22, count 2 2006.182.07:34:40.05#ibcon#enter sib2, iclass 22, count 2 2006.182.07:34:40.05#ibcon#flushed, iclass 22, count 2 2006.182.07:34:40.05#ibcon#about to write, iclass 22, count 2 2006.182.07:34:40.05#ibcon#wrote, iclass 22, count 2 2006.182.07:34:40.05#ibcon#about to read 3, iclass 22, count 2 2006.182.07:34:40.07#ibcon#read 3, iclass 22, count 2 2006.182.07:34:40.07#ibcon#about to read 4, iclass 22, count 2 2006.182.07:34:40.07#ibcon#read 4, iclass 22, count 2 2006.182.07:34:40.07#ibcon#about to read 5, iclass 22, count 2 2006.182.07:34:40.07#ibcon#read 5, iclass 22, count 2 2006.182.07:34:40.07#ibcon#about to read 6, iclass 22, count 2 2006.182.07:34:40.07#ibcon#read 6, iclass 22, count 2 2006.182.07:34:40.07#ibcon#end of sib2, iclass 22, count 2 2006.182.07:34:40.07#ibcon#*mode == 0, iclass 22, count 2 2006.182.07:34:40.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.07:34:40.07#ibcon#[25=AT07-06\r\n] 2006.182.07:34:40.07#ibcon#*before write, iclass 22, count 2 2006.182.07:34:40.07#ibcon#enter sib2, iclass 22, count 2 2006.182.07:34:40.07#ibcon#flushed, iclass 22, count 2 2006.182.07:34:40.07#ibcon#about to write, iclass 22, count 2 2006.182.07:34:40.07#ibcon#wrote, iclass 22, count 2 2006.182.07:34:40.07#ibcon#about to read 3, iclass 22, count 2 2006.182.07:34:40.10#ibcon#read 3, iclass 22, count 2 2006.182.07:34:40.10#ibcon#about to read 4, iclass 22, count 2 2006.182.07:34:40.10#ibcon#read 4, iclass 22, count 2 2006.182.07:34:40.10#ibcon#about to read 5, iclass 22, count 2 2006.182.07:34:40.10#ibcon#read 5, iclass 22, count 2 2006.182.07:34:40.10#ibcon#about to read 6, iclass 22, count 2 2006.182.07:34:40.10#ibcon#read 6, iclass 22, count 2 2006.182.07:34:40.10#ibcon#end of sib2, iclass 22, count 2 2006.182.07:34:40.10#ibcon#*after write, iclass 22, count 2 2006.182.07:34:40.10#ibcon#*before return 0, iclass 22, count 2 2006.182.07:34:40.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:34:40.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:34:40.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.07:34:40.10#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:40.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:34:40.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:34:40.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:34:40.22#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:34:40.22#ibcon#first serial, iclass 22, count 0 2006.182.07:34:40.22#ibcon#enter sib2, iclass 22, count 0 2006.182.07:34:40.22#ibcon#flushed, iclass 22, count 0 2006.182.07:34:40.22#ibcon#about to write, iclass 22, count 0 2006.182.07:34:40.22#ibcon#wrote, iclass 22, count 0 2006.182.07:34:40.22#ibcon#about to read 3, iclass 22, count 0 2006.182.07:34:40.26#ibcon#read 3, iclass 22, count 0 2006.182.07:34:40.26#ibcon#about to read 4, iclass 22, count 0 2006.182.07:34:40.26#ibcon#read 4, iclass 22, count 0 2006.182.07:34:40.26#ibcon#about to read 5, iclass 22, count 0 2006.182.07:34:40.26#ibcon#read 5, iclass 22, count 0 2006.182.07:34:40.26#ibcon#about to read 6, iclass 22, count 0 2006.182.07:34:40.26#ibcon#read 6, iclass 22, count 0 2006.182.07:34:40.26#ibcon#end of sib2, iclass 22, count 0 2006.182.07:34:40.26#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:34:40.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:34:40.26#ibcon#[25=USB\r\n] 2006.182.07:34:40.26#ibcon#*before write, iclass 22, count 0 2006.182.07:34:40.26#ibcon#enter sib2, iclass 22, count 0 2006.182.07:34:40.26#ibcon#flushed, iclass 22, count 0 2006.182.07:34:40.26#ibcon#about to write, iclass 22, count 0 2006.182.07:34:40.26#ibcon#wrote, iclass 22, count 0 2006.182.07:34:40.26#ibcon#about to read 3, iclass 22, count 0 2006.182.07:34:40.28#ibcon#read 3, iclass 22, count 0 2006.182.07:34:40.28#ibcon#about to read 4, iclass 22, count 0 2006.182.07:34:40.28#ibcon#read 4, iclass 22, count 0 2006.182.07:34:40.28#ibcon#about to read 5, iclass 22, count 0 2006.182.07:34:40.28#ibcon#read 5, iclass 22, count 0 2006.182.07:34:40.28#ibcon#about to read 6, iclass 22, count 0 2006.182.07:34:40.28#ibcon#read 6, iclass 22, count 0 2006.182.07:34:40.28#ibcon#end of sib2, iclass 22, count 0 2006.182.07:34:40.28#ibcon#*after write, iclass 22, count 0 2006.182.07:34:40.28#ibcon#*before return 0, iclass 22, count 0 2006.182.07:34:40.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:34:40.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:34:40.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:34:40.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:34:40.28$vc4f8/valo=8,852.99 2006.182.07:34:40.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.07:34:40.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.07:34:40.28#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:40.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:34:40.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:34:40.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:34:40.28#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:34:40.28#ibcon#first serial, iclass 24, count 0 2006.182.07:34:40.28#ibcon#enter sib2, iclass 24, count 0 2006.182.07:34:40.28#ibcon#flushed, iclass 24, count 0 2006.182.07:34:40.28#ibcon#about to write, iclass 24, count 0 2006.182.07:34:40.28#ibcon#wrote, iclass 24, count 0 2006.182.07:34:40.28#ibcon#about to read 3, iclass 24, count 0 2006.182.07:34:40.30#ibcon#read 3, iclass 24, count 0 2006.182.07:34:40.30#ibcon#about to read 4, iclass 24, count 0 2006.182.07:34:40.30#ibcon#read 4, iclass 24, count 0 2006.182.07:34:40.30#ibcon#about to read 5, iclass 24, count 0 2006.182.07:34:40.30#ibcon#read 5, iclass 24, count 0 2006.182.07:34:40.30#ibcon#about to read 6, iclass 24, count 0 2006.182.07:34:40.30#ibcon#read 6, iclass 24, count 0 2006.182.07:34:40.30#ibcon#end of sib2, iclass 24, count 0 2006.182.07:34:40.30#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:34:40.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:34:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:34:40.30#ibcon#*before write, iclass 24, count 0 2006.182.07:34:40.30#ibcon#enter sib2, iclass 24, count 0 2006.182.07:34:40.30#ibcon#flushed, iclass 24, count 0 2006.182.07:34:40.30#ibcon#about to write, iclass 24, count 0 2006.182.07:34:40.30#ibcon#wrote, iclass 24, count 0 2006.182.07:34:40.30#ibcon#about to read 3, iclass 24, count 0 2006.182.07:34:40.34#ibcon#read 3, iclass 24, count 0 2006.182.07:34:40.34#ibcon#about to read 4, iclass 24, count 0 2006.182.07:34:40.34#ibcon#read 4, iclass 24, count 0 2006.182.07:34:40.34#ibcon#about to read 5, iclass 24, count 0 2006.182.07:34:40.34#ibcon#read 5, iclass 24, count 0 2006.182.07:34:40.34#ibcon#about to read 6, iclass 24, count 0 2006.182.07:34:40.34#ibcon#read 6, iclass 24, count 0 2006.182.07:34:40.34#ibcon#end of sib2, iclass 24, count 0 2006.182.07:34:40.34#ibcon#*after write, iclass 24, count 0 2006.182.07:34:40.34#ibcon#*before return 0, iclass 24, count 0 2006.182.07:34:40.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:34:40.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:34:40.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:34:40.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:34:40.34$vc4f8/va=8,7 2006.182.07:34:40.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.07:34:40.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.07:34:40.34#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:40.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:34:40.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:34:40.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:34:40.40#ibcon#enter wrdev, iclass 26, count 2 2006.182.07:34:40.40#ibcon#first serial, iclass 26, count 2 2006.182.07:34:40.40#ibcon#enter sib2, iclass 26, count 2 2006.182.07:34:40.40#ibcon#flushed, iclass 26, count 2 2006.182.07:34:40.40#ibcon#about to write, iclass 26, count 2 2006.182.07:34:40.40#ibcon#wrote, iclass 26, count 2 2006.182.07:34:40.40#ibcon#about to read 3, iclass 26, count 2 2006.182.07:34:40.42#ibcon#read 3, iclass 26, count 2 2006.182.07:34:40.42#ibcon#about to read 4, iclass 26, count 2 2006.182.07:34:40.42#ibcon#read 4, iclass 26, count 2 2006.182.07:34:40.42#ibcon#about to read 5, iclass 26, count 2 2006.182.07:34:40.42#ibcon#read 5, iclass 26, count 2 2006.182.07:34:40.42#ibcon#about to read 6, iclass 26, count 2 2006.182.07:34:40.42#ibcon#read 6, iclass 26, count 2 2006.182.07:34:40.42#ibcon#end of sib2, iclass 26, count 2 2006.182.07:34:40.42#ibcon#*mode == 0, iclass 26, count 2 2006.182.07:34:40.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.07:34:40.42#ibcon#[25=AT08-07\r\n] 2006.182.07:34:40.42#ibcon#*before write, iclass 26, count 2 2006.182.07:34:40.42#ibcon#enter sib2, iclass 26, count 2 2006.182.07:34:40.42#ibcon#flushed, iclass 26, count 2 2006.182.07:34:40.42#ibcon#about to write, iclass 26, count 2 2006.182.07:34:40.42#ibcon#wrote, iclass 26, count 2 2006.182.07:34:40.42#ibcon#about to read 3, iclass 26, count 2 2006.182.07:34:40.45#ibcon#read 3, iclass 26, count 2 2006.182.07:34:40.45#ibcon#about to read 4, iclass 26, count 2 2006.182.07:34:40.45#ibcon#read 4, iclass 26, count 2 2006.182.07:34:40.45#ibcon#about to read 5, iclass 26, count 2 2006.182.07:34:40.45#ibcon#read 5, iclass 26, count 2 2006.182.07:34:40.45#ibcon#about to read 6, iclass 26, count 2 2006.182.07:34:40.45#ibcon#read 6, iclass 26, count 2 2006.182.07:34:40.45#ibcon#end of sib2, iclass 26, count 2 2006.182.07:34:40.45#ibcon#*after write, iclass 26, count 2 2006.182.07:34:40.45#ibcon#*before return 0, iclass 26, count 2 2006.182.07:34:40.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:34:40.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:34:40.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.07:34:40.45#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:40.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:34:40.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:34:40.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:34:40.57#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:34:40.57#ibcon#first serial, iclass 26, count 0 2006.182.07:34:40.57#ibcon#enter sib2, iclass 26, count 0 2006.182.07:34:40.57#ibcon#flushed, iclass 26, count 0 2006.182.07:34:40.57#ibcon#about to write, iclass 26, count 0 2006.182.07:34:40.57#ibcon#wrote, iclass 26, count 0 2006.182.07:34:40.57#ibcon#about to read 3, iclass 26, count 0 2006.182.07:34:40.59#ibcon#read 3, iclass 26, count 0 2006.182.07:34:40.59#ibcon#about to read 4, iclass 26, count 0 2006.182.07:34:40.59#ibcon#read 4, iclass 26, count 0 2006.182.07:34:40.59#ibcon#about to read 5, iclass 26, count 0 2006.182.07:34:40.59#ibcon#read 5, iclass 26, count 0 2006.182.07:34:40.59#ibcon#about to read 6, iclass 26, count 0 2006.182.07:34:40.59#ibcon#read 6, iclass 26, count 0 2006.182.07:34:40.59#ibcon#end of sib2, iclass 26, count 0 2006.182.07:34:40.59#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:34:40.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:34:40.59#ibcon#[25=USB\r\n] 2006.182.07:34:40.59#ibcon#*before write, iclass 26, count 0 2006.182.07:34:40.59#ibcon#enter sib2, iclass 26, count 0 2006.182.07:34:40.59#ibcon#flushed, iclass 26, count 0 2006.182.07:34:40.59#ibcon#about to write, iclass 26, count 0 2006.182.07:34:40.59#ibcon#wrote, iclass 26, count 0 2006.182.07:34:40.59#ibcon#about to read 3, iclass 26, count 0 2006.182.07:34:40.62#ibcon#read 3, iclass 26, count 0 2006.182.07:34:40.62#ibcon#about to read 4, iclass 26, count 0 2006.182.07:34:40.62#ibcon#read 4, iclass 26, count 0 2006.182.07:34:40.62#ibcon#about to read 5, iclass 26, count 0 2006.182.07:34:40.62#ibcon#read 5, iclass 26, count 0 2006.182.07:34:40.62#ibcon#about to read 6, iclass 26, count 0 2006.182.07:34:40.62#ibcon#read 6, iclass 26, count 0 2006.182.07:34:40.62#ibcon#end of sib2, iclass 26, count 0 2006.182.07:34:40.62#ibcon#*after write, iclass 26, count 0 2006.182.07:34:40.62#ibcon#*before return 0, iclass 26, count 0 2006.182.07:34:40.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:34:40.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:34:40.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:34:40.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:34:40.62$vc4f8/vblo=1,632.99 2006.182.07:34:40.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.07:34:40.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.07:34:40.62#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:40.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:34:40.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:34:40.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:34:40.62#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:34:40.62#ibcon#first serial, iclass 28, count 0 2006.182.07:34:40.62#ibcon#enter sib2, iclass 28, count 0 2006.182.07:34:40.62#ibcon#flushed, iclass 28, count 0 2006.182.07:34:40.62#ibcon#about to write, iclass 28, count 0 2006.182.07:34:40.62#ibcon#wrote, iclass 28, count 0 2006.182.07:34:40.62#ibcon#about to read 3, iclass 28, count 0 2006.182.07:34:40.64#ibcon#read 3, iclass 28, count 0 2006.182.07:34:40.64#ibcon#about to read 4, iclass 28, count 0 2006.182.07:34:40.64#ibcon#read 4, iclass 28, count 0 2006.182.07:34:40.64#ibcon#about to read 5, iclass 28, count 0 2006.182.07:34:40.64#ibcon#read 5, iclass 28, count 0 2006.182.07:34:40.64#ibcon#about to read 6, iclass 28, count 0 2006.182.07:34:40.64#ibcon#read 6, iclass 28, count 0 2006.182.07:34:40.64#ibcon#end of sib2, iclass 28, count 0 2006.182.07:34:40.64#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:34:40.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:34:40.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:34:40.64#ibcon#*before write, iclass 28, count 0 2006.182.07:34:40.64#ibcon#enter sib2, iclass 28, count 0 2006.182.07:34:40.64#ibcon#flushed, iclass 28, count 0 2006.182.07:34:40.64#ibcon#about to write, iclass 28, count 0 2006.182.07:34:40.64#ibcon#wrote, iclass 28, count 0 2006.182.07:34:40.64#ibcon#about to read 3, iclass 28, count 0 2006.182.07:34:40.68#ibcon#read 3, iclass 28, count 0 2006.182.07:34:40.68#ibcon#about to read 4, iclass 28, count 0 2006.182.07:34:40.68#ibcon#read 4, iclass 28, count 0 2006.182.07:34:40.68#ibcon#about to read 5, iclass 28, count 0 2006.182.07:34:40.68#ibcon#read 5, iclass 28, count 0 2006.182.07:34:40.68#ibcon#about to read 6, iclass 28, count 0 2006.182.07:34:40.68#ibcon#read 6, iclass 28, count 0 2006.182.07:34:40.68#ibcon#end of sib2, iclass 28, count 0 2006.182.07:34:40.68#ibcon#*after write, iclass 28, count 0 2006.182.07:34:40.68#ibcon#*before return 0, iclass 28, count 0 2006.182.07:34:40.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:34:40.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:34:40.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:34:40.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:34:40.68$vc4f8/vb=1,4 2006.182.07:34:40.68#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.07:34:40.68#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.07:34:40.68#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:40.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:34:40.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:34:40.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:34:40.68#ibcon#enter wrdev, iclass 30, count 2 2006.182.07:34:40.68#ibcon#first serial, iclass 30, count 2 2006.182.07:34:40.68#ibcon#enter sib2, iclass 30, count 2 2006.182.07:34:40.68#ibcon#flushed, iclass 30, count 2 2006.182.07:34:40.68#ibcon#about to write, iclass 30, count 2 2006.182.07:34:40.68#ibcon#wrote, iclass 30, count 2 2006.182.07:34:40.68#ibcon#about to read 3, iclass 30, count 2 2006.182.07:34:40.70#ibcon#read 3, iclass 30, count 2 2006.182.07:34:40.70#ibcon#about to read 4, iclass 30, count 2 2006.182.07:34:40.70#ibcon#read 4, iclass 30, count 2 2006.182.07:34:40.70#ibcon#about to read 5, iclass 30, count 2 2006.182.07:34:40.70#ibcon#read 5, iclass 30, count 2 2006.182.07:34:40.70#ibcon#about to read 6, iclass 30, count 2 2006.182.07:34:40.70#ibcon#read 6, iclass 30, count 2 2006.182.07:34:40.70#ibcon#end of sib2, iclass 30, count 2 2006.182.07:34:40.70#ibcon#*mode == 0, iclass 30, count 2 2006.182.07:34:40.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.07:34:40.70#ibcon#[27=AT01-04\r\n] 2006.182.07:34:40.70#ibcon#*before write, iclass 30, count 2 2006.182.07:34:40.70#ibcon#enter sib2, iclass 30, count 2 2006.182.07:34:40.70#ibcon#flushed, iclass 30, count 2 2006.182.07:34:40.70#ibcon#about to write, iclass 30, count 2 2006.182.07:34:40.70#ibcon#wrote, iclass 30, count 2 2006.182.07:34:40.70#ibcon#about to read 3, iclass 30, count 2 2006.182.07:34:40.73#ibcon#read 3, iclass 30, count 2 2006.182.07:34:40.73#ibcon#about to read 4, iclass 30, count 2 2006.182.07:34:40.73#ibcon#read 4, iclass 30, count 2 2006.182.07:34:40.73#ibcon#about to read 5, iclass 30, count 2 2006.182.07:34:40.73#ibcon#read 5, iclass 30, count 2 2006.182.07:34:40.73#ibcon#about to read 6, iclass 30, count 2 2006.182.07:34:40.73#ibcon#read 6, iclass 30, count 2 2006.182.07:34:40.73#ibcon#end of sib2, iclass 30, count 2 2006.182.07:34:40.73#ibcon#*after write, iclass 30, count 2 2006.182.07:34:40.73#ibcon#*before return 0, iclass 30, count 2 2006.182.07:34:40.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:34:40.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:34:40.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.07:34:40.73#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:40.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:34:40.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:34:40.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:34:40.85#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:34:40.85#ibcon#first serial, iclass 30, count 0 2006.182.07:34:40.85#ibcon#enter sib2, iclass 30, count 0 2006.182.07:34:40.85#ibcon#flushed, iclass 30, count 0 2006.182.07:34:40.85#ibcon#about to write, iclass 30, count 0 2006.182.07:34:40.85#ibcon#wrote, iclass 30, count 0 2006.182.07:34:40.85#ibcon#about to read 3, iclass 30, count 0 2006.182.07:34:40.87#ibcon#read 3, iclass 30, count 0 2006.182.07:34:40.87#ibcon#about to read 4, iclass 30, count 0 2006.182.07:34:40.87#ibcon#read 4, iclass 30, count 0 2006.182.07:34:40.87#ibcon#about to read 5, iclass 30, count 0 2006.182.07:34:40.87#ibcon#read 5, iclass 30, count 0 2006.182.07:34:40.87#ibcon#about to read 6, iclass 30, count 0 2006.182.07:34:40.87#ibcon#read 6, iclass 30, count 0 2006.182.07:34:40.87#ibcon#end of sib2, iclass 30, count 0 2006.182.07:34:40.87#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:34:40.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:34:40.87#ibcon#[27=USB\r\n] 2006.182.07:34:40.87#ibcon#*before write, iclass 30, count 0 2006.182.07:34:40.87#ibcon#enter sib2, iclass 30, count 0 2006.182.07:34:40.87#ibcon#flushed, iclass 30, count 0 2006.182.07:34:40.87#ibcon#about to write, iclass 30, count 0 2006.182.07:34:40.87#ibcon#wrote, iclass 30, count 0 2006.182.07:34:40.87#ibcon#about to read 3, iclass 30, count 0 2006.182.07:34:40.90#ibcon#read 3, iclass 30, count 0 2006.182.07:34:40.90#ibcon#about to read 4, iclass 30, count 0 2006.182.07:34:40.90#ibcon#read 4, iclass 30, count 0 2006.182.07:34:40.90#ibcon#about to read 5, iclass 30, count 0 2006.182.07:34:40.90#ibcon#read 5, iclass 30, count 0 2006.182.07:34:40.90#ibcon#about to read 6, iclass 30, count 0 2006.182.07:34:40.90#ibcon#read 6, iclass 30, count 0 2006.182.07:34:40.90#ibcon#end of sib2, iclass 30, count 0 2006.182.07:34:40.90#ibcon#*after write, iclass 30, count 0 2006.182.07:34:40.90#ibcon#*before return 0, iclass 30, count 0 2006.182.07:34:40.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:34:40.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:34:40.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:34:40.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:34:40.90$vc4f8/vblo=2,640.99 2006.182.07:34:40.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.07:34:40.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.07:34:40.90#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:40.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:40.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:40.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:40.90#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:34:40.90#ibcon#first serial, iclass 32, count 0 2006.182.07:34:40.90#ibcon#enter sib2, iclass 32, count 0 2006.182.07:34:40.90#ibcon#flushed, iclass 32, count 0 2006.182.07:34:40.90#ibcon#about to write, iclass 32, count 0 2006.182.07:34:40.90#ibcon#wrote, iclass 32, count 0 2006.182.07:34:40.90#ibcon#about to read 3, iclass 32, count 0 2006.182.07:34:40.93#ibcon#read 3, iclass 32, count 0 2006.182.07:34:40.93#ibcon#about to read 4, iclass 32, count 0 2006.182.07:34:40.93#ibcon#read 4, iclass 32, count 0 2006.182.07:34:40.93#ibcon#about to read 5, iclass 32, count 0 2006.182.07:34:40.93#ibcon#read 5, iclass 32, count 0 2006.182.07:34:40.93#ibcon#about to read 6, iclass 32, count 0 2006.182.07:34:40.93#ibcon#read 6, iclass 32, count 0 2006.182.07:34:40.93#ibcon#end of sib2, iclass 32, count 0 2006.182.07:34:40.93#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:34:40.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:34:40.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:34:40.93#ibcon#*before write, iclass 32, count 0 2006.182.07:34:40.93#ibcon#enter sib2, iclass 32, count 0 2006.182.07:34:40.93#ibcon#flushed, iclass 32, count 0 2006.182.07:34:40.93#ibcon#about to write, iclass 32, count 0 2006.182.07:34:40.93#ibcon#wrote, iclass 32, count 0 2006.182.07:34:40.93#ibcon#about to read 3, iclass 32, count 0 2006.182.07:34:40.97#ibcon#read 3, iclass 32, count 0 2006.182.07:34:40.97#ibcon#about to read 4, iclass 32, count 0 2006.182.07:34:40.97#ibcon#read 4, iclass 32, count 0 2006.182.07:34:40.97#ibcon#about to read 5, iclass 32, count 0 2006.182.07:34:40.97#ibcon#read 5, iclass 32, count 0 2006.182.07:34:40.97#ibcon#about to read 6, iclass 32, count 0 2006.182.07:34:40.97#ibcon#read 6, iclass 32, count 0 2006.182.07:34:40.97#ibcon#end of sib2, iclass 32, count 0 2006.182.07:34:40.97#ibcon#*after write, iclass 32, count 0 2006.182.07:34:40.97#ibcon#*before return 0, iclass 32, count 0 2006.182.07:34:40.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:40.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:34:40.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:34:40.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:34:40.97$vc4f8/vb=2,4 2006.182.07:34:40.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.07:34:40.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.07:34:40.97#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:40.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:41.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:41.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:41.02#ibcon#enter wrdev, iclass 34, count 2 2006.182.07:34:41.02#ibcon#first serial, iclass 34, count 2 2006.182.07:34:41.02#ibcon#enter sib2, iclass 34, count 2 2006.182.07:34:41.02#ibcon#flushed, iclass 34, count 2 2006.182.07:34:41.02#ibcon#about to write, iclass 34, count 2 2006.182.07:34:41.02#ibcon#wrote, iclass 34, count 2 2006.182.07:34:41.02#ibcon#about to read 3, iclass 34, count 2 2006.182.07:34:41.04#ibcon#read 3, iclass 34, count 2 2006.182.07:34:41.04#ibcon#about to read 4, iclass 34, count 2 2006.182.07:34:41.04#ibcon#read 4, iclass 34, count 2 2006.182.07:34:41.04#ibcon#about to read 5, iclass 34, count 2 2006.182.07:34:41.04#ibcon#read 5, iclass 34, count 2 2006.182.07:34:41.04#ibcon#about to read 6, iclass 34, count 2 2006.182.07:34:41.04#ibcon#read 6, iclass 34, count 2 2006.182.07:34:41.04#ibcon#end of sib2, iclass 34, count 2 2006.182.07:34:41.04#ibcon#*mode == 0, iclass 34, count 2 2006.182.07:34:41.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.07:34:41.04#ibcon#[27=AT02-04\r\n] 2006.182.07:34:41.04#ibcon#*before write, iclass 34, count 2 2006.182.07:34:41.04#ibcon#enter sib2, iclass 34, count 2 2006.182.07:34:41.04#ibcon#flushed, iclass 34, count 2 2006.182.07:34:41.04#ibcon#about to write, iclass 34, count 2 2006.182.07:34:41.04#ibcon#wrote, iclass 34, count 2 2006.182.07:34:41.04#ibcon#about to read 3, iclass 34, count 2 2006.182.07:34:41.07#ibcon#read 3, iclass 34, count 2 2006.182.07:34:41.07#ibcon#about to read 4, iclass 34, count 2 2006.182.07:34:41.07#ibcon#read 4, iclass 34, count 2 2006.182.07:34:41.07#ibcon#about to read 5, iclass 34, count 2 2006.182.07:34:41.07#ibcon#read 5, iclass 34, count 2 2006.182.07:34:41.07#ibcon#about to read 6, iclass 34, count 2 2006.182.07:34:41.07#ibcon#read 6, iclass 34, count 2 2006.182.07:34:41.07#ibcon#end of sib2, iclass 34, count 2 2006.182.07:34:41.07#ibcon#*after write, iclass 34, count 2 2006.182.07:34:41.07#ibcon#*before return 0, iclass 34, count 2 2006.182.07:34:41.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:41.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:34:41.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.07:34:41.07#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:41.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:41.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:41.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:41.19#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:34:41.19#ibcon#first serial, iclass 34, count 0 2006.182.07:34:41.19#ibcon#enter sib2, iclass 34, count 0 2006.182.07:34:41.19#ibcon#flushed, iclass 34, count 0 2006.182.07:34:41.19#ibcon#about to write, iclass 34, count 0 2006.182.07:34:41.19#ibcon#wrote, iclass 34, count 0 2006.182.07:34:41.19#ibcon#about to read 3, iclass 34, count 0 2006.182.07:34:41.21#ibcon#read 3, iclass 34, count 0 2006.182.07:34:41.21#ibcon#about to read 4, iclass 34, count 0 2006.182.07:34:41.21#ibcon#read 4, iclass 34, count 0 2006.182.07:34:41.21#ibcon#about to read 5, iclass 34, count 0 2006.182.07:34:41.21#ibcon#read 5, iclass 34, count 0 2006.182.07:34:41.21#ibcon#about to read 6, iclass 34, count 0 2006.182.07:34:41.21#ibcon#read 6, iclass 34, count 0 2006.182.07:34:41.21#ibcon#end of sib2, iclass 34, count 0 2006.182.07:34:41.21#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:34:41.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:34:41.21#ibcon#[27=USB\r\n] 2006.182.07:34:41.21#ibcon#*before write, iclass 34, count 0 2006.182.07:34:41.21#ibcon#enter sib2, iclass 34, count 0 2006.182.07:34:41.21#ibcon#flushed, iclass 34, count 0 2006.182.07:34:41.21#ibcon#about to write, iclass 34, count 0 2006.182.07:34:41.21#ibcon#wrote, iclass 34, count 0 2006.182.07:34:41.21#ibcon#about to read 3, iclass 34, count 0 2006.182.07:34:41.24#ibcon#read 3, iclass 34, count 0 2006.182.07:34:41.24#ibcon#about to read 4, iclass 34, count 0 2006.182.07:34:41.24#ibcon#read 4, iclass 34, count 0 2006.182.07:34:41.24#ibcon#about to read 5, iclass 34, count 0 2006.182.07:34:41.24#ibcon#read 5, iclass 34, count 0 2006.182.07:34:41.24#ibcon#about to read 6, iclass 34, count 0 2006.182.07:34:41.24#ibcon#read 6, iclass 34, count 0 2006.182.07:34:41.24#ibcon#end of sib2, iclass 34, count 0 2006.182.07:34:41.24#ibcon#*after write, iclass 34, count 0 2006.182.07:34:41.24#ibcon#*before return 0, iclass 34, count 0 2006.182.07:34:41.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:41.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:34:41.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:34:41.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:34:41.24$vc4f8/vblo=3,656.99 2006.182.07:34:41.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.07:34:41.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.07:34:41.24#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:41.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:41.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:41.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:41.24#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:34:41.24#ibcon#first serial, iclass 36, count 0 2006.182.07:34:41.24#ibcon#enter sib2, iclass 36, count 0 2006.182.07:34:41.24#ibcon#flushed, iclass 36, count 0 2006.182.07:34:41.24#ibcon#about to write, iclass 36, count 0 2006.182.07:34:41.24#ibcon#wrote, iclass 36, count 0 2006.182.07:34:41.24#ibcon#about to read 3, iclass 36, count 0 2006.182.07:34:41.26#ibcon#read 3, iclass 36, count 0 2006.182.07:34:41.26#ibcon#about to read 4, iclass 36, count 0 2006.182.07:34:41.26#ibcon#read 4, iclass 36, count 0 2006.182.07:34:41.26#ibcon#about to read 5, iclass 36, count 0 2006.182.07:34:41.26#ibcon#read 5, iclass 36, count 0 2006.182.07:34:41.26#ibcon#about to read 6, iclass 36, count 0 2006.182.07:34:41.26#ibcon#read 6, iclass 36, count 0 2006.182.07:34:41.26#ibcon#end of sib2, iclass 36, count 0 2006.182.07:34:41.26#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:34:41.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:34:41.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:34:41.26#ibcon#*before write, iclass 36, count 0 2006.182.07:34:41.26#ibcon#enter sib2, iclass 36, count 0 2006.182.07:34:41.26#ibcon#flushed, iclass 36, count 0 2006.182.07:34:41.26#ibcon#about to write, iclass 36, count 0 2006.182.07:34:41.26#ibcon#wrote, iclass 36, count 0 2006.182.07:34:41.26#ibcon#about to read 3, iclass 36, count 0 2006.182.07:34:41.30#ibcon#read 3, iclass 36, count 0 2006.182.07:34:41.30#ibcon#about to read 4, iclass 36, count 0 2006.182.07:34:41.30#ibcon#read 4, iclass 36, count 0 2006.182.07:34:41.30#ibcon#about to read 5, iclass 36, count 0 2006.182.07:34:41.30#ibcon#read 5, iclass 36, count 0 2006.182.07:34:41.30#ibcon#about to read 6, iclass 36, count 0 2006.182.07:34:41.30#ibcon#read 6, iclass 36, count 0 2006.182.07:34:41.30#ibcon#end of sib2, iclass 36, count 0 2006.182.07:34:41.30#ibcon#*after write, iclass 36, count 0 2006.182.07:34:41.30#ibcon#*before return 0, iclass 36, count 0 2006.182.07:34:41.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:41.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:34:41.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:34:41.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:34:41.30$vc4f8/vb=3,4 2006.182.07:34:41.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.07:34:41.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.07:34:41.30#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:41.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:41.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:41.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:41.36#ibcon#enter wrdev, iclass 38, count 2 2006.182.07:34:41.36#ibcon#first serial, iclass 38, count 2 2006.182.07:34:41.36#ibcon#enter sib2, iclass 38, count 2 2006.182.07:34:41.36#ibcon#flushed, iclass 38, count 2 2006.182.07:34:41.36#ibcon#about to write, iclass 38, count 2 2006.182.07:34:41.36#ibcon#wrote, iclass 38, count 2 2006.182.07:34:41.36#ibcon#about to read 3, iclass 38, count 2 2006.182.07:34:41.38#ibcon#read 3, iclass 38, count 2 2006.182.07:34:41.38#ibcon#about to read 4, iclass 38, count 2 2006.182.07:34:41.38#ibcon#read 4, iclass 38, count 2 2006.182.07:34:41.38#ibcon#about to read 5, iclass 38, count 2 2006.182.07:34:41.38#ibcon#read 5, iclass 38, count 2 2006.182.07:34:41.38#ibcon#about to read 6, iclass 38, count 2 2006.182.07:34:41.38#ibcon#read 6, iclass 38, count 2 2006.182.07:34:41.38#ibcon#end of sib2, iclass 38, count 2 2006.182.07:34:41.38#ibcon#*mode == 0, iclass 38, count 2 2006.182.07:34:41.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.07:34:41.38#ibcon#[27=AT03-04\r\n] 2006.182.07:34:41.38#ibcon#*before write, iclass 38, count 2 2006.182.07:34:41.38#ibcon#enter sib2, iclass 38, count 2 2006.182.07:34:41.38#ibcon#flushed, iclass 38, count 2 2006.182.07:34:41.38#ibcon#about to write, iclass 38, count 2 2006.182.07:34:41.38#ibcon#wrote, iclass 38, count 2 2006.182.07:34:41.38#ibcon#about to read 3, iclass 38, count 2 2006.182.07:34:41.41#ibcon#read 3, iclass 38, count 2 2006.182.07:34:41.41#ibcon#about to read 4, iclass 38, count 2 2006.182.07:34:41.41#ibcon#read 4, iclass 38, count 2 2006.182.07:34:41.41#ibcon#about to read 5, iclass 38, count 2 2006.182.07:34:41.41#ibcon#read 5, iclass 38, count 2 2006.182.07:34:41.41#ibcon#about to read 6, iclass 38, count 2 2006.182.07:34:41.41#ibcon#read 6, iclass 38, count 2 2006.182.07:34:41.41#ibcon#end of sib2, iclass 38, count 2 2006.182.07:34:41.41#ibcon#*after write, iclass 38, count 2 2006.182.07:34:41.41#ibcon#*before return 0, iclass 38, count 2 2006.182.07:34:41.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:41.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:34:41.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.07:34:41.41#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:41.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:41.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:41.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:41.53#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:34:41.53#ibcon#first serial, iclass 38, count 0 2006.182.07:34:41.53#ibcon#enter sib2, iclass 38, count 0 2006.182.07:34:41.53#ibcon#flushed, iclass 38, count 0 2006.182.07:34:41.53#ibcon#about to write, iclass 38, count 0 2006.182.07:34:41.53#ibcon#wrote, iclass 38, count 0 2006.182.07:34:41.53#ibcon#about to read 3, iclass 38, count 0 2006.182.07:34:41.55#ibcon#read 3, iclass 38, count 0 2006.182.07:34:41.55#ibcon#about to read 4, iclass 38, count 0 2006.182.07:34:41.55#ibcon#read 4, iclass 38, count 0 2006.182.07:34:41.55#ibcon#about to read 5, iclass 38, count 0 2006.182.07:34:41.55#ibcon#read 5, iclass 38, count 0 2006.182.07:34:41.55#ibcon#about to read 6, iclass 38, count 0 2006.182.07:34:41.55#ibcon#read 6, iclass 38, count 0 2006.182.07:34:41.55#ibcon#end of sib2, iclass 38, count 0 2006.182.07:34:41.55#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:34:41.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:34:41.55#ibcon#[27=USB\r\n] 2006.182.07:34:41.55#ibcon#*before write, iclass 38, count 0 2006.182.07:34:41.55#ibcon#enter sib2, iclass 38, count 0 2006.182.07:34:41.55#ibcon#flushed, iclass 38, count 0 2006.182.07:34:41.55#ibcon#about to write, iclass 38, count 0 2006.182.07:34:41.55#ibcon#wrote, iclass 38, count 0 2006.182.07:34:41.55#ibcon#about to read 3, iclass 38, count 0 2006.182.07:34:41.58#ibcon#read 3, iclass 38, count 0 2006.182.07:34:41.58#ibcon#about to read 4, iclass 38, count 0 2006.182.07:34:41.58#ibcon#read 4, iclass 38, count 0 2006.182.07:34:41.58#ibcon#about to read 5, iclass 38, count 0 2006.182.07:34:41.58#ibcon#read 5, iclass 38, count 0 2006.182.07:34:41.58#ibcon#about to read 6, iclass 38, count 0 2006.182.07:34:41.58#ibcon#read 6, iclass 38, count 0 2006.182.07:34:41.58#ibcon#end of sib2, iclass 38, count 0 2006.182.07:34:41.58#ibcon#*after write, iclass 38, count 0 2006.182.07:34:41.58#ibcon#*before return 0, iclass 38, count 0 2006.182.07:34:41.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:41.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:34:41.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:34:41.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:34:41.58$vc4f8/vblo=4,712.99 2006.182.07:34:41.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.07:34:41.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.07:34:41.58#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:41.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:41.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:41.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:41.58#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:34:41.58#ibcon#first serial, iclass 40, count 0 2006.182.07:34:41.58#ibcon#enter sib2, iclass 40, count 0 2006.182.07:34:41.58#ibcon#flushed, iclass 40, count 0 2006.182.07:34:41.58#ibcon#about to write, iclass 40, count 0 2006.182.07:34:41.58#ibcon#wrote, iclass 40, count 0 2006.182.07:34:41.58#ibcon#about to read 3, iclass 40, count 0 2006.182.07:34:41.60#ibcon#read 3, iclass 40, count 0 2006.182.07:34:41.60#ibcon#about to read 4, iclass 40, count 0 2006.182.07:34:41.60#ibcon#read 4, iclass 40, count 0 2006.182.07:34:41.60#ibcon#about to read 5, iclass 40, count 0 2006.182.07:34:41.60#ibcon#read 5, iclass 40, count 0 2006.182.07:34:41.60#ibcon#about to read 6, iclass 40, count 0 2006.182.07:34:41.60#ibcon#read 6, iclass 40, count 0 2006.182.07:34:41.60#ibcon#end of sib2, iclass 40, count 0 2006.182.07:34:41.60#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:34:41.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:34:41.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:34:41.60#ibcon#*before write, iclass 40, count 0 2006.182.07:34:41.60#ibcon#enter sib2, iclass 40, count 0 2006.182.07:34:41.60#ibcon#flushed, iclass 40, count 0 2006.182.07:34:41.60#ibcon#about to write, iclass 40, count 0 2006.182.07:34:41.60#ibcon#wrote, iclass 40, count 0 2006.182.07:34:41.60#ibcon#about to read 3, iclass 40, count 0 2006.182.07:34:41.64#ibcon#read 3, iclass 40, count 0 2006.182.07:34:41.64#ibcon#about to read 4, iclass 40, count 0 2006.182.07:34:41.64#ibcon#read 4, iclass 40, count 0 2006.182.07:34:41.64#ibcon#about to read 5, iclass 40, count 0 2006.182.07:34:41.64#ibcon#read 5, iclass 40, count 0 2006.182.07:34:41.64#ibcon#about to read 6, iclass 40, count 0 2006.182.07:34:41.64#ibcon#read 6, iclass 40, count 0 2006.182.07:34:41.64#ibcon#end of sib2, iclass 40, count 0 2006.182.07:34:41.64#ibcon#*after write, iclass 40, count 0 2006.182.07:34:41.64#ibcon#*before return 0, iclass 40, count 0 2006.182.07:34:41.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:41.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:34:41.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:34:41.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:34:41.64$vc4f8/vb=4,4 2006.182.07:34:41.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.07:34:41.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.07:34:41.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:41.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:41.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:41.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:41.70#ibcon#enter wrdev, iclass 4, count 2 2006.182.07:34:41.70#ibcon#first serial, iclass 4, count 2 2006.182.07:34:41.70#ibcon#enter sib2, iclass 4, count 2 2006.182.07:34:41.70#ibcon#flushed, iclass 4, count 2 2006.182.07:34:41.70#ibcon#about to write, iclass 4, count 2 2006.182.07:34:41.70#ibcon#wrote, iclass 4, count 2 2006.182.07:34:41.70#ibcon#about to read 3, iclass 4, count 2 2006.182.07:34:41.72#ibcon#read 3, iclass 4, count 2 2006.182.07:34:41.72#ibcon#about to read 4, iclass 4, count 2 2006.182.07:34:41.72#ibcon#read 4, iclass 4, count 2 2006.182.07:34:41.72#ibcon#about to read 5, iclass 4, count 2 2006.182.07:34:41.72#ibcon#read 5, iclass 4, count 2 2006.182.07:34:41.72#ibcon#about to read 6, iclass 4, count 2 2006.182.07:34:41.72#ibcon#read 6, iclass 4, count 2 2006.182.07:34:41.72#ibcon#end of sib2, iclass 4, count 2 2006.182.07:34:41.72#ibcon#*mode == 0, iclass 4, count 2 2006.182.07:34:41.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.07:34:41.72#ibcon#[27=AT04-04\r\n] 2006.182.07:34:41.72#ibcon#*before write, iclass 4, count 2 2006.182.07:34:41.72#ibcon#enter sib2, iclass 4, count 2 2006.182.07:34:41.72#ibcon#flushed, iclass 4, count 2 2006.182.07:34:41.72#ibcon#about to write, iclass 4, count 2 2006.182.07:34:41.72#ibcon#wrote, iclass 4, count 2 2006.182.07:34:41.72#ibcon#about to read 3, iclass 4, count 2 2006.182.07:34:41.75#ibcon#read 3, iclass 4, count 2 2006.182.07:34:41.75#ibcon#about to read 4, iclass 4, count 2 2006.182.07:34:41.75#ibcon#read 4, iclass 4, count 2 2006.182.07:34:41.75#ibcon#about to read 5, iclass 4, count 2 2006.182.07:34:41.75#ibcon#read 5, iclass 4, count 2 2006.182.07:34:41.75#ibcon#about to read 6, iclass 4, count 2 2006.182.07:34:41.75#ibcon#read 6, iclass 4, count 2 2006.182.07:34:41.75#ibcon#end of sib2, iclass 4, count 2 2006.182.07:34:41.75#ibcon#*after write, iclass 4, count 2 2006.182.07:34:41.75#ibcon#*before return 0, iclass 4, count 2 2006.182.07:34:41.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:41.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:34:41.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.07:34:41.75#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:41.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:41.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:41.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:41.87#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:34:41.87#ibcon#first serial, iclass 4, count 0 2006.182.07:34:41.87#ibcon#enter sib2, iclass 4, count 0 2006.182.07:34:41.87#ibcon#flushed, iclass 4, count 0 2006.182.07:34:41.87#ibcon#about to write, iclass 4, count 0 2006.182.07:34:41.87#ibcon#wrote, iclass 4, count 0 2006.182.07:34:41.87#ibcon#about to read 3, iclass 4, count 0 2006.182.07:34:41.89#ibcon#read 3, iclass 4, count 0 2006.182.07:34:41.89#ibcon#about to read 4, iclass 4, count 0 2006.182.07:34:41.89#ibcon#read 4, iclass 4, count 0 2006.182.07:34:41.89#ibcon#about to read 5, iclass 4, count 0 2006.182.07:34:41.89#ibcon#read 5, iclass 4, count 0 2006.182.07:34:41.89#ibcon#about to read 6, iclass 4, count 0 2006.182.07:34:41.89#ibcon#read 6, iclass 4, count 0 2006.182.07:34:41.89#ibcon#end of sib2, iclass 4, count 0 2006.182.07:34:41.89#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:34:41.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:34:41.89#ibcon#[27=USB\r\n] 2006.182.07:34:41.89#ibcon#*before write, iclass 4, count 0 2006.182.07:34:41.89#ibcon#enter sib2, iclass 4, count 0 2006.182.07:34:41.89#ibcon#flushed, iclass 4, count 0 2006.182.07:34:41.89#ibcon#about to write, iclass 4, count 0 2006.182.07:34:41.89#ibcon#wrote, iclass 4, count 0 2006.182.07:34:41.89#ibcon#about to read 3, iclass 4, count 0 2006.182.07:34:41.92#ibcon#read 3, iclass 4, count 0 2006.182.07:34:41.92#ibcon#about to read 4, iclass 4, count 0 2006.182.07:34:41.92#ibcon#read 4, iclass 4, count 0 2006.182.07:34:41.92#ibcon#about to read 5, iclass 4, count 0 2006.182.07:34:41.92#ibcon#read 5, iclass 4, count 0 2006.182.07:34:41.92#ibcon#about to read 6, iclass 4, count 0 2006.182.07:34:41.92#ibcon#read 6, iclass 4, count 0 2006.182.07:34:41.92#ibcon#end of sib2, iclass 4, count 0 2006.182.07:34:41.92#ibcon#*after write, iclass 4, count 0 2006.182.07:34:41.92#ibcon#*before return 0, iclass 4, count 0 2006.182.07:34:41.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:41.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:34:41.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:34:41.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:34:41.92$vc4f8/vblo=5,744.99 2006.182.07:34:41.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.07:34:41.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.07:34:41.92#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:41.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:41.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:41.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:41.92#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:34:41.92#ibcon#first serial, iclass 6, count 0 2006.182.07:34:41.92#ibcon#enter sib2, iclass 6, count 0 2006.182.07:34:41.92#ibcon#flushed, iclass 6, count 0 2006.182.07:34:41.92#ibcon#about to write, iclass 6, count 0 2006.182.07:34:41.92#ibcon#wrote, iclass 6, count 0 2006.182.07:34:41.92#ibcon#about to read 3, iclass 6, count 0 2006.182.07:34:41.94#ibcon#read 3, iclass 6, count 0 2006.182.07:34:41.94#ibcon#about to read 4, iclass 6, count 0 2006.182.07:34:41.94#ibcon#read 4, iclass 6, count 0 2006.182.07:34:41.94#ibcon#about to read 5, iclass 6, count 0 2006.182.07:34:41.94#ibcon#read 5, iclass 6, count 0 2006.182.07:34:41.94#ibcon#about to read 6, iclass 6, count 0 2006.182.07:34:41.94#ibcon#read 6, iclass 6, count 0 2006.182.07:34:41.94#ibcon#end of sib2, iclass 6, count 0 2006.182.07:34:41.94#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:34:41.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:34:41.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:34:41.94#ibcon#*before write, iclass 6, count 0 2006.182.07:34:41.94#ibcon#enter sib2, iclass 6, count 0 2006.182.07:34:41.94#ibcon#flushed, iclass 6, count 0 2006.182.07:34:41.94#ibcon#about to write, iclass 6, count 0 2006.182.07:34:41.94#ibcon#wrote, iclass 6, count 0 2006.182.07:34:41.94#ibcon#about to read 3, iclass 6, count 0 2006.182.07:34:41.98#ibcon#read 3, iclass 6, count 0 2006.182.07:34:41.98#ibcon#about to read 4, iclass 6, count 0 2006.182.07:34:41.98#ibcon#read 4, iclass 6, count 0 2006.182.07:34:41.98#ibcon#about to read 5, iclass 6, count 0 2006.182.07:34:41.98#ibcon#read 5, iclass 6, count 0 2006.182.07:34:41.98#ibcon#about to read 6, iclass 6, count 0 2006.182.07:34:41.98#ibcon#read 6, iclass 6, count 0 2006.182.07:34:41.98#ibcon#end of sib2, iclass 6, count 0 2006.182.07:34:41.98#ibcon#*after write, iclass 6, count 0 2006.182.07:34:41.98#ibcon#*before return 0, iclass 6, count 0 2006.182.07:34:41.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:41.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:34:41.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:34:41.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:34:41.98$vc4f8/vb=5,4 2006.182.07:34:41.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.07:34:41.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.07:34:41.98#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:41.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:42.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:42.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:42.04#ibcon#enter wrdev, iclass 10, count 2 2006.182.07:34:42.04#ibcon#first serial, iclass 10, count 2 2006.182.07:34:42.04#ibcon#enter sib2, iclass 10, count 2 2006.182.07:34:42.04#ibcon#flushed, iclass 10, count 2 2006.182.07:34:42.04#ibcon#about to write, iclass 10, count 2 2006.182.07:34:42.04#ibcon#wrote, iclass 10, count 2 2006.182.07:34:42.04#ibcon#about to read 3, iclass 10, count 2 2006.182.07:34:42.06#ibcon#read 3, iclass 10, count 2 2006.182.07:34:42.06#ibcon#about to read 4, iclass 10, count 2 2006.182.07:34:42.06#ibcon#read 4, iclass 10, count 2 2006.182.07:34:42.06#ibcon#about to read 5, iclass 10, count 2 2006.182.07:34:42.06#ibcon#read 5, iclass 10, count 2 2006.182.07:34:42.06#ibcon#about to read 6, iclass 10, count 2 2006.182.07:34:42.06#ibcon#read 6, iclass 10, count 2 2006.182.07:34:42.06#ibcon#end of sib2, iclass 10, count 2 2006.182.07:34:42.06#ibcon#*mode == 0, iclass 10, count 2 2006.182.07:34:42.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.07:34:42.06#ibcon#[27=AT05-04\r\n] 2006.182.07:34:42.06#ibcon#*before write, iclass 10, count 2 2006.182.07:34:42.06#ibcon#enter sib2, iclass 10, count 2 2006.182.07:34:42.06#ibcon#flushed, iclass 10, count 2 2006.182.07:34:42.06#ibcon#about to write, iclass 10, count 2 2006.182.07:34:42.06#ibcon#wrote, iclass 10, count 2 2006.182.07:34:42.06#ibcon#about to read 3, iclass 10, count 2 2006.182.07:34:42.09#ibcon#read 3, iclass 10, count 2 2006.182.07:34:42.09#ibcon#about to read 4, iclass 10, count 2 2006.182.07:34:42.09#ibcon#read 4, iclass 10, count 2 2006.182.07:34:42.09#ibcon#about to read 5, iclass 10, count 2 2006.182.07:34:42.09#ibcon#read 5, iclass 10, count 2 2006.182.07:34:42.09#ibcon#about to read 6, iclass 10, count 2 2006.182.07:34:42.09#ibcon#read 6, iclass 10, count 2 2006.182.07:34:42.09#ibcon#end of sib2, iclass 10, count 2 2006.182.07:34:42.09#ibcon#*after write, iclass 10, count 2 2006.182.07:34:42.09#ibcon#*before return 0, iclass 10, count 2 2006.182.07:34:42.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:42.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:34:42.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.07:34:42.09#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:42.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:42.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:42.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:42.21#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:34:42.21#ibcon#first serial, iclass 10, count 0 2006.182.07:34:42.21#ibcon#enter sib2, iclass 10, count 0 2006.182.07:34:42.21#ibcon#flushed, iclass 10, count 0 2006.182.07:34:42.21#ibcon#about to write, iclass 10, count 0 2006.182.07:34:42.21#ibcon#wrote, iclass 10, count 0 2006.182.07:34:42.21#ibcon#about to read 3, iclass 10, count 0 2006.182.07:34:42.23#ibcon#read 3, iclass 10, count 0 2006.182.07:34:42.23#ibcon#about to read 4, iclass 10, count 0 2006.182.07:34:42.23#ibcon#read 4, iclass 10, count 0 2006.182.07:34:42.23#ibcon#about to read 5, iclass 10, count 0 2006.182.07:34:42.23#ibcon#read 5, iclass 10, count 0 2006.182.07:34:42.23#ibcon#about to read 6, iclass 10, count 0 2006.182.07:34:42.23#ibcon#read 6, iclass 10, count 0 2006.182.07:34:42.23#ibcon#end of sib2, iclass 10, count 0 2006.182.07:34:42.23#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:34:42.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:34:42.23#ibcon#[27=USB\r\n] 2006.182.07:34:42.23#ibcon#*before write, iclass 10, count 0 2006.182.07:34:42.23#ibcon#enter sib2, iclass 10, count 0 2006.182.07:34:42.23#ibcon#flushed, iclass 10, count 0 2006.182.07:34:42.23#ibcon#about to write, iclass 10, count 0 2006.182.07:34:42.23#ibcon#wrote, iclass 10, count 0 2006.182.07:34:42.23#ibcon#about to read 3, iclass 10, count 0 2006.182.07:34:42.26#ibcon#read 3, iclass 10, count 0 2006.182.07:34:42.26#ibcon#about to read 4, iclass 10, count 0 2006.182.07:34:42.26#ibcon#read 4, iclass 10, count 0 2006.182.07:34:42.26#ibcon#about to read 5, iclass 10, count 0 2006.182.07:34:42.26#ibcon#read 5, iclass 10, count 0 2006.182.07:34:42.26#ibcon#about to read 6, iclass 10, count 0 2006.182.07:34:42.26#ibcon#read 6, iclass 10, count 0 2006.182.07:34:42.26#ibcon#end of sib2, iclass 10, count 0 2006.182.07:34:42.26#ibcon#*after write, iclass 10, count 0 2006.182.07:34:42.26#ibcon#*before return 0, iclass 10, count 0 2006.182.07:34:42.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:42.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:34:42.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:34:42.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:34:42.26$vc4f8/vblo=6,752.99 2006.182.07:34:42.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.07:34:42.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.07:34:42.26#ibcon#ireg 17 cls_cnt 0 2006.182.07:34:42.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:42.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:42.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:42.26#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:34:42.26#ibcon#first serial, iclass 12, count 0 2006.182.07:34:42.26#ibcon#enter sib2, iclass 12, count 0 2006.182.07:34:42.26#ibcon#flushed, iclass 12, count 0 2006.182.07:34:42.26#ibcon#about to write, iclass 12, count 0 2006.182.07:34:42.26#ibcon#wrote, iclass 12, count 0 2006.182.07:34:42.26#ibcon#about to read 3, iclass 12, count 0 2006.182.07:34:42.28#ibcon#read 3, iclass 12, count 0 2006.182.07:34:42.28#ibcon#about to read 4, iclass 12, count 0 2006.182.07:34:42.28#ibcon#read 4, iclass 12, count 0 2006.182.07:34:42.28#ibcon#about to read 5, iclass 12, count 0 2006.182.07:34:42.28#ibcon#read 5, iclass 12, count 0 2006.182.07:34:42.28#ibcon#about to read 6, iclass 12, count 0 2006.182.07:34:42.28#ibcon#read 6, iclass 12, count 0 2006.182.07:34:42.28#ibcon#end of sib2, iclass 12, count 0 2006.182.07:34:42.28#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:34:42.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:34:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:34:42.28#ibcon#*before write, iclass 12, count 0 2006.182.07:34:42.28#ibcon#enter sib2, iclass 12, count 0 2006.182.07:34:42.28#ibcon#flushed, iclass 12, count 0 2006.182.07:34:42.28#ibcon#about to write, iclass 12, count 0 2006.182.07:34:42.28#ibcon#wrote, iclass 12, count 0 2006.182.07:34:42.28#ibcon#about to read 3, iclass 12, count 0 2006.182.07:34:42.32#ibcon#read 3, iclass 12, count 0 2006.182.07:34:42.32#ibcon#about to read 4, iclass 12, count 0 2006.182.07:34:42.32#ibcon#read 4, iclass 12, count 0 2006.182.07:34:42.32#ibcon#about to read 5, iclass 12, count 0 2006.182.07:34:42.32#ibcon#read 5, iclass 12, count 0 2006.182.07:34:42.32#ibcon#about to read 6, iclass 12, count 0 2006.182.07:34:42.32#ibcon#read 6, iclass 12, count 0 2006.182.07:34:42.32#ibcon#end of sib2, iclass 12, count 0 2006.182.07:34:42.32#ibcon#*after write, iclass 12, count 0 2006.182.07:34:42.32#ibcon#*before return 0, iclass 12, count 0 2006.182.07:34:42.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:42.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:34:42.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:34:42.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:34:42.32$vc4f8/vb=6,4 2006.182.07:34:42.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.07:34:42.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.07:34:42.32#ibcon#ireg 11 cls_cnt 2 2006.182.07:34:42.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:42.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:42.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:42.38#ibcon#enter wrdev, iclass 14, count 2 2006.182.07:34:42.38#ibcon#first serial, iclass 14, count 2 2006.182.07:34:42.38#ibcon#enter sib2, iclass 14, count 2 2006.182.07:34:42.38#ibcon#flushed, iclass 14, count 2 2006.182.07:34:42.38#ibcon#about to write, iclass 14, count 2 2006.182.07:34:42.38#ibcon#wrote, iclass 14, count 2 2006.182.07:34:42.38#ibcon#about to read 3, iclass 14, count 2 2006.182.07:34:42.40#ibcon#read 3, iclass 14, count 2 2006.182.07:34:42.40#ibcon#about to read 4, iclass 14, count 2 2006.182.07:34:42.40#ibcon#read 4, iclass 14, count 2 2006.182.07:34:42.40#ibcon#about to read 5, iclass 14, count 2 2006.182.07:34:42.40#ibcon#read 5, iclass 14, count 2 2006.182.07:34:42.40#ibcon#about to read 6, iclass 14, count 2 2006.182.07:34:42.40#ibcon#read 6, iclass 14, count 2 2006.182.07:34:42.40#ibcon#end of sib2, iclass 14, count 2 2006.182.07:34:42.40#ibcon#*mode == 0, iclass 14, count 2 2006.182.07:34:42.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.07:34:42.40#ibcon#[27=AT06-04\r\n] 2006.182.07:34:42.40#ibcon#*before write, iclass 14, count 2 2006.182.07:34:42.40#ibcon#enter sib2, iclass 14, count 2 2006.182.07:34:42.40#ibcon#flushed, iclass 14, count 2 2006.182.07:34:42.40#ibcon#about to write, iclass 14, count 2 2006.182.07:34:42.40#ibcon#wrote, iclass 14, count 2 2006.182.07:34:42.40#ibcon#about to read 3, iclass 14, count 2 2006.182.07:34:42.43#ibcon#read 3, iclass 14, count 2 2006.182.07:34:42.43#ibcon#about to read 4, iclass 14, count 2 2006.182.07:34:42.43#ibcon#read 4, iclass 14, count 2 2006.182.07:34:42.43#ibcon#about to read 5, iclass 14, count 2 2006.182.07:34:42.43#ibcon#read 5, iclass 14, count 2 2006.182.07:34:42.43#ibcon#about to read 6, iclass 14, count 2 2006.182.07:34:42.43#ibcon#read 6, iclass 14, count 2 2006.182.07:34:42.43#ibcon#end of sib2, iclass 14, count 2 2006.182.07:34:42.43#ibcon#*after write, iclass 14, count 2 2006.182.07:34:42.43#ibcon#*before return 0, iclass 14, count 2 2006.182.07:34:42.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:42.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:34:42.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.07:34:42.43#ibcon#ireg 7 cls_cnt 0 2006.182.07:34:42.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:42.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:42.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:42.55#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:34:42.55#ibcon#first serial, iclass 14, count 0 2006.182.07:34:42.55#ibcon#enter sib2, iclass 14, count 0 2006.182.07:34:42.55#ibcon#flushed, iclass 14, count 0 2006.182.07:34:42.55#ibcon#about to write, iclass 14, count 0 2006.182.07:34:42.55#ibcon#wrote, iclass 14, count 0 2006.182.07:34:42.55#ibcon#about to read 3, iclass 14, count 0 2006.182.07:34:42.57#ibcon#read 3, iclass 14, count 0 2006.182.07:34:42.57#ibcon#about to read 4, iclass 14, count 0 2006.182.07:34:42.57#ibcon#read 4, iclass 14, count 0 2006.182.07:34:42.57#ibcon#about to read 5, iclass 14, count 0 2006.182.07:34:42.57#ibcon#read 5, iclass 14, count 0 2006.182.07:34:42.57#ibcon#about to read 6, iclass 14, count 0 2006.182.07:34:42.57#ibcon#read 6, iclass 14, count 0 2006.182.07:34:42.57#ibcon#end of sib2, iclass 14, count 0 2006.182.07:34:42.57#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:34:42.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:34:42.57#ibcon#[27=USB\r\n] 2006.182.07:34:42.57#ibcon#*before write, iclass 14, count 0 2006.182.07:34:42.57#ibcon#enter sib2, iclass 14, count 0 2006.182.07:34:42.57#ibcon#flushed, iclass 14, count 0 2006.182.07:34:42.57#ibcon#about to write, iclass 14, count 0 2006.182.07:34:42.57#ibcon#wrote, iclass 14, count 0 2006.182.07:34:42.57#ibcon#about to read 3, iclass 14, count 0 2006.182.07:34:42.60#ibcon#read 3, iclass 14, count 0 2006.182.07:34:42.60#ibcon#about to read 4, iclass 14, count 0 2006.182.07:34:42.60#ibcon#read 4, iclass 14, count 0 2006.182.07:34:42.60#ibcon#about to read 5, iclass 14, count 0 2006.182.07:34:42.60#ibcon#read 5, iclass 14, count 0 2006.182.07:34:42.60#ibcon#about to read 6, iclass 14, count 0 2006.182.07:34:42.60#ibcon#read 6, iclass 14, count 0 2006.182.07:34:42.60#ibcon#end of sib2, iclass 14, count 0 2006.182.07:34:42.60#ibcon#*after write, iclass 14, count 0 2006.182.07:34:42.60#ibcon#*before return 0, iclass 14, count 0 2006.182.07:34:42.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:42.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:34:42.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:34:42.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:34:42.60$vc4f8/vabw=wide 2006.182.07:34:42.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.07:34:42.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.07:34:42.60#ibcon#ireg 8 cls_cnt 0 2006.182.07:34:42.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:42.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:42.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:42.60#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:34:42.60#ibcon#first serial, iclass 16, count 0 2006.182.07:34:42.60#ibcon#enter sib2, iclass 16, count 0 2006.182.07:34:42.60#ibcon#flushed, iclass 16, count 0 2006.182.07:34:42.60#ibcon#about to write, iclass 16, count 0 2006.182.07:34:42.60#ibcon#wrote, iclass 16, count 0 2006.182.07:34:42.60#ibcon#about to read 3, iclass 16, count 0 2006.182.07:34:42.63#ibcon#read 3, iclass 16, count 0 2006.182.07:34:42.63#ibcon#about to read 4, iclass 16, count 0 2006.182.07:34:42.63#ibcon#read 4, iclass 16, count 0 2006.182.07:34:42.63#ibcon#about to read 5, iclass 16, count 0 2006.182.07:34:42.63#ibcon#read 5, iclass 16, count 0 2006.182.07:34:42.63#ibcon#about to read 6, iclass 16, count 0 2006.182.07:34:42.63#ibcon#read 6, iclass 16, count 0 2006.182.07:34:42.63#ibcon#end of sib2, iclass 16, count 0 2006.182.07:34:42.63#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:34:42.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:34:42.63#ibcon#[25=BW32\r\n] 2006.182.07:34:42.63#ibcon#*before write, iclass 16, count 0 2006.182.07:34:42.63#ibcon#enter sib2, iclass 16, count 0 2006.182.07:34:42.63#ibcon#flushed, iclass 16, count 0 2006.182.07:34:42.63#ibcon#about to write, iclass 16, count 0 2006.182.07:34:42.63#ibcon#wrote, iclass 16, count 0 2006.182.07:34:42.63#ibcon#about to read 3, iclass 16, count 0 2006.182.07:34:42.66#ibcon#read 3, iclass 16, count 0 2006.182.07:34:42.66#ibcon#about to read 4, iclass 16, count 0 2006.182.07:34:42.66#ibcon#read 4, iclass 16, count 0 2006.182.07:34:42.66#ibcon#about to read 5, iclass 16, count 0 2006.182.07:34:42.66#ibcon#read 5, iclass 16, count 0 2006.182.07:34:42.66#ibcon#about to read 6, iclass 16, count 0 2006.182.07:34:42.66#ibcon#read 6, iclass 16, count 0 2006.182.07:34:42.66#ibcon#end of sib2, iclass 16, count 0 2006.182.07:34:42.66#ibcon#*after write, iclass 16, count 0 2006.182.07:34:42.66#ibcon#*before return 0, iclass 16, count 0 2006.182.07:34:42.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:42.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:34:42.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:34:42.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:34:42.66$vc4f8/vbbw=wide 2006.182.07:34:42.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.07:34:42.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.07:34:42.66#ibcon#ireg 8 cls_cnt 0 2006.182.07:34:42.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:34:42.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:34:42.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:34:42.72#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:34:42.72#ibcon#first serial, iclass 18, count 0 2006.182.07:34:42.72#ibcon#enter sib2, iclass 18, count 0 2006.182.07:34:42.72#ibcon#flushed, iclass 18, count 0 2006.182.07:34:42.72#ibcon#about to write, iclass 18, count 0 2006.182.07:34:42.72#ibcon#wrote, iclass 18, count 0 2006.182.07:34:42.72#ibcon#about to read 3, iclass 18, count 0 2006.182.07:34:42.74#ibcon#read 3, iclass 18, count 0 2006.182.07:34:42.74#ibcon#about to read 4, iclass 18, count 0 2006.182.07:34:42.74#ibcon#read 4, iclass 18, count 0 2006.182.07:34:42.74#ibcon#about to read 5, iclass 18, count 0 2006.182.07:34:42.74#ibcon#read 5, iclass 18, count 0 2006.182.07:34:42.74#ibcon#about to read 6, iclass 18, count 0 2006.182.07:34:42.74#ibcon#read 6, iclass 18, count 0 2006.182.07:34:42.74#ibcon#end of sib2, iclass 18, count 0 2006.182.07:34:42.74#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:34:42.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:34:42.74#ibcon#[27=BW32\r\n] 2006.182.07:34:42.74#ibcon#*before write, iclass 18, count 0 2006.182.07:34:42.74#ibcon#enter sib2, iclass 18, count 0 2006.182.07:34:42.74#ibcon#flushed, iclass 18, count 0 2006.182.07:34:42.74#ibcon#about to write, iclass 18, count 0 2006.182.07:34:42.74#ibcon#wrote, iclass 18, count 0 2006.182.07:34:42.74#ibcon#about to read 3, iclass 18, count 0 2006.182.07:34:42.77#ibcon#read 3, iclass 18, count 0 2006.182.07:34:42.77#ibcon#about to read 4, iclass 18, count 0 2006.182.07:34:42.77#ibcon#read 4, iclass 18, count 0 2006.182.07:34:42.77#ibcon#about to read 5, iclass 18, count 0 2006.182.07:34:42.77#ibcon#read 5, iclass 18, count 0 2006.182.07:34:42.77#ibcon#about to read 6, iclass 18, count 0 2006.182.07:34:42.77#ibcon#read 6, iclass 18, count 0 2006.182.07:34:42.77#ibcon#end of sib2, iclass 18, count 0 2006.182.07:34:42.77#ibcon#*after write, iclass 18, count 0 2006.182.07:34:42.77#ibcon#*before return 0, iclass 18, count 0 2006.182.07:34:42.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:34:42.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:34:42.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:34:42.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:34:42.77$4f8m12a/ifd4f 2006.182.07:34:42.77$ifd4f/lo= 2006.182.07:34:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:34:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:34:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:34:42.77$ifd4f/patch= 2006.182.07:34:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:34:42.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:34:42.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:34:42.77$4f8m12a/"form=m,16.000,1:2 2006.182.07:34:42.77$4f8m12a/"tpicd 2006.182.07:34:42.77$4f8m12a/echo=off 2006.182.07:34:42.77$4f8m12a/xlog=off 2006.182.07:34:42.77:!2006.182.07:35:10 2006.182.07:34:52.14#trakl#Source acquired 2006.182.07:34:52.14#flagr#flagr/antenna,acquired 2006.182.07:35:10.00:preob 2006.182.07:35:11.14/onsource/TRACKING 2006.182.07:35:11.14:!2006.182.07:35:20 2006.182.07:35:20.00:data_valid=on 2006.182.07:35:20.00:midob 2006.182.07:35:20.14/onsource/TRACKING 2006.182.07:35:20.14/wx/27.44,1002.8,83 2006.182.07:35:20.29/cable/+6.4661E-03 2006.182.07:35:21.38/va/01,08,usb,yes,29,30 2006.182.07:35:21.38/va/02,07,usb,yes,29,30 2006.182.07:35:21.38/va/03,06,usb,yes,30,31 2006.182.07:35:21.38/va/04,07,usb,yes,30,32 2006.182.07:35:21.38/va/05,07,usb,yes,31,32 2006.182.07:35:21.38/va/06,06,usb,yes,30,30 2006.182.07:35:21.38/va/07,06,usb,yes,30,30 2006.182.07:35:21.38/va/08,07,usb,yes,29,28 2006.182.07:35:21.61/valo/01,532.99,yes,locked 2006.182.07:35:21.61/valo/02,572.99,yes,locked 2006.182.07:35:21.61/valo/03,672.99,yes,locked 2006.182.07:35:21.61/valo/04,832.99,yes,locked 2006.182.07:35:21.61/valo/05,652.99,yes,locked 2006.182.07:35:21.61/valo/06,772.99,yes,locked 2006.182.07:35:21.61/valo/07,832.99,yes,locked 2006.182.07:35:21.61/valo/08,852.99,yes,locked 2006.182.07:35:22.70/vb/01,04,usb,yes,29,28 2006.182.07:35:22.70/vb/02,04,usb,yes,31,32 2006.182.07:35:22.70/vb/03,04,usb,yes,27,31 2006.182.07:35:22.70/vb/04,04,usb,yes,28,28 2006.182.07:35:22.70/vb/05,04,usb,yes,26,30 2006.182.07:35:22.70/vb/06,04,usb,yes,27,30 2006.182.07:35:22.70/vb/07,04,usb,yes,29,29 2006.182.07:35:22.70/vb/08,04,usb,yes,27,30 2006.182.07:35:22.93/vblo/01,632.99,yes,locked 2006.182.07:35:22.93/vblo/02,640.99,yes,locked 2006.182.07:35:22.93/vblo/03,656.99,yes,locked 2006.182.07:35:22.93/vblo/04,712.99,yes,locked 2006.182.07:35:22.93/vblo/05,744.99,yes,locked 2006.182.07:35:22.93/vblo/06,752.99,yes,locked 2006.182.07:35:22.93/vblo/07,734.99,yes,locked 2006.182.07:35:22.93/vblo/08,744.99,yes,locked 2006.182.07:35:23.08/vabw/8 2006.182.07:35:23.23/vbbw/8 2006.182.07:35:23.33/xfe/off,on,15.0 2006.182.07:35:23.73/ifatt/23,28,28,28 2006.182.07:35:24.08/fmout-gps/S +3.34E-07 2006.182.07:35:24.12:!2006.182.07:36:20 2006.182.07:36:20.00:data_valid=off 2006.182.07:36:20.00:postob 2006.182.07:36:20.12/cable/+6.4660E-03 2006.182.07:36:20.12/wx/27.45,1002.9,82 2006.182.07:36:21.08/fmout-gps/S +3.35E-07 2006.182.07:36:21.08:scan_name=182-0737,k06182,60 2006.182.07:36:21.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.182.07:36:21.14#flagr#flagr/antenna,new-source 2006.182.07:36:22.14:checkk5 2006.182.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:36:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:36:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:36:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:36:24.02/chk_obsdata//k5ts1/T1820735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:36:24.38/chk_obsdata//k5ts2/T1820735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:36:24.75/chk_obsdata//k5ts3/T1820735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:36:25.12/chk_obsdata//k5ts4/T1820735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:36:25.80/k5log//k5ts1_log_newline 2006.182.07:36:26.49/k5log//k5ts2_log_newline 2006.182.07:36:27.18/k5log//k5ts3_log_newline 2006.182.07:36:27.86/k5log//k5ts4_log_newline 2006.182.07:36:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:36:27.89:4f8m12a=1 2006.182.07:36:27.89$4f8m12a/echo=on 2006.182.07:36:27.89$4f8m12a/pcalon 2006.182.07:36:27.89$pcalon/"no phase cal control is implemented here 2006.182.07:36:27.89$4f8m12a/"tpicd=stop 2006.182.07:36:27.89$4f8m12a/vc4f8 2006.182.07:36:27.89$vc4f8/valo=1,532.99 2006.182.07:36:27.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.07:36:27.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.07:36:27.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:27.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:27.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:27.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:27.89#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:36:27.89#ibcon#first serial, iclass 25, count 0 2006.182.07:36:27.89#ibcon#enter sib2, iclass 25, count 0 2006.182.07:36:27.89#ibcon#flushed, iclass 25, count 0 2006.182.07:36:27.89#ibcon#about to write, iclass 25, count 0 2006.182.07:36:27.89#ibcon#wrote, iclass 25, count 0 2006.182.07:36:27.89#ibcon#about to read 3, iclass 25, count 0 2006.182.07:36:27.93#ibcon#read 3, iclass 25, count 0 2006.182.07:36:27.93#ibcon#about to read 4, iclass 25, count 0 2006.182.07:36:27.93#ibcon#read 4, iclass 25, count 0 2006.182.07:36:27.93#ibcon#about to read 5, iclass 25, count 0 2006.182.07:36:27.93#ibcon#read 5, iclass 25, count 0 2006.182.07:36:27.93#ibcon#about to read 6, iclass 25, count 0 2006.182.07:36:27.93#ibcon#read 6, iclass 25, count 0 2006.182.07:36:27.93#ibcon#end of sib2, iclass 25, count 0 2006.182.07:36:27.93#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:36:27.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:36:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:36:27.93#ibcon#*before write, iclass 25, count 0 2006.182.07:36:27.93#ibcon#enter sib2, iclass 25, count 0 2006.182.07:36:27.93#ibcon#flushed, iclass 25, count 0 2006.182.07:36:27.93#ibcon#about to write, iclass 25, count 0 2006.182.07:36:27.93#ibcon#wrote, iclass 25, count 0 2006.182.07:36:27.93#ibcon#about to read 3, iclass 25, count 0 2006.182.07:36:27.98#ibcon#read 3, iclass 25, count 0 2006.182.07:36:27.98#ibcon#about to read 4, iclass 25, count 0 2006.182.07:36:27.98#ibcon#read 4, iclass 25, count 0 2006.182.07:36:27.98#ibcon#about to read 5, iclass 25, count 0 2006.182.07:36:27.98#ibcon#read 5, iclass 25, count 0 2006.182.07:36:27.98#ibcon#about to read 6, iclass 25, count 0 2006.182.07:36:27.98#ibcon#read 6, iclass 25, count 0 2006.182.07:36:27.98#ibcon#end of sib2, iclass 25, count 0 2006.182.07:36:27.98#ibcon#*after write, iclass 25, count 0 2006.182.07:36:27.98#ibcon#*before return 0, iclass 25, count 0 2006.182.07:36:27.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:27.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:27.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:36:27.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:36:27.98$vc4f8/va=1,8 2006.182.07:36:27.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.182.07:36:27.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.182.07:36:27.98#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:27.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:27.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:27.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:27.98#ibcon#enter wrdev, iclass 27, count 2 2006.182.07:36:27.98#ibcon#first serial, iclass 27, count 2 2006.182.07:36:27.98#ibcon#enter sib2, iclass 27, count 2 2006.182.07:36:27.98#ibcon#flushed, iclass 27, count 2 2006.182.07:36:27.98#ibcon#about to write, iclass 27, count 2 2006.182.07:36:27.98#ibcon#wrote, iclass 27, count 2 2006.182.07:36:27.98#ibcon#about to read 3, iclass 27, count 2 2006.182.07:36:28.00#ibcon#read 3, iclass 27, count 2 2006.182.07:36:28.00#ibcon#about to read 4, iclass 27, count 2 2006.182.07:36:28.00#ibcon#read 4, iclass 27, count 2 2006.182.07:36:28.00#ibcon#about to read 5, iclass 27, count 2 2006.182.07:36:28.00#ibcon#read 5, iclass 27, count 2 2006.182.07:36:28.00#ibcon#about to read 6, iclass 27, count 2 2006.182.07:36:28.00#ibcon#read 6, iclass 27, count 2 2006.182.07:36:28.00#ibcon#end of sib2, iclass 27, count 2 2006.182.07:36:28.00#ibcon#*mode == 0, iclass 27, count 2 2006.182.07:36:28.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.182.07:36:28.00#ibcon#[25=AT01-08\r\n] 2006.182.07:36:28.00#ibcon#*before write, iclass 27, count 2 2006.182.07:36:28.00#ibcon#enter sib2, iclass 27, count 2 2006.182.07:36:28.00#ibcon#flushed, iclass 27, count 2 2006.182.07:36:28.00#ibcon#about to write, iclass 27, count 2 2006.182.07:36:28.00#ibcon#wrote, iclass 27, count 2 2006.182.07:36:28.00#ibcon#about to read 3, iclass 27, count 2 2006.182.07:36:28.03#ibcon#read 3, iclass 27, count 2 2006.182.07:36:28.03#ibcon#about to read 4, iclass 27, count 2 2006.182.07:36:28.03#ibcon#read 4, iclass 27, count 2 2006.182.07:36:28.03#ibcon#about to read 5, iclass 27, count 2 2006.182.07:36:28.03#ibcon#read 5, iclass 27, count 2 2006.182.07:36:28.03#ibcon#about to read 6, iclass 27, count 2 2006.182.07:36:28.03#ibcon#read 6, iclass 27, count 2 2006.182.07:36:28.03#ibcon#end of sib2, iclass 27, count 2 2006.182.07:36:28.03#ibcon#*after write, iclass 27, count 2 2006.182.07:36:28.03#ibcon#*before return 0, iclass 27, count 2 2006.182.07:36:28.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:28.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:28.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.182.07:36:28.03#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:28.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:28.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:28.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:28.15#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:36:28.15#ibcon#first serial, iclass 27, count 0 2006.182.07:36:28.15#ibcon#enter sib2, iclass 27, count 0 2006.182.07:36:28.15#ibcon#flushed, iclass 27, count 0 2006.182.07:36:28.15#ibcon#about to write, iclass 27, count 0 2006.182.07:36:28.15#ibcon#wrote, iclass 27, count 0 2006.182.07:36:28.15#ibcon#about to read 3, iclass 27, count 0 2006.182.07:36:28.17#ibcon#read 3, iclass 27, count 0 2006.182.07:36:28.17#ibcon#about to read 4, iclass 27, count 0 2006.182.07:36:28.17#ibcon#read 4, iclass 27, count 0 2006.182.07:36:28.17#ibcon#about to read 5, iclass 27, count 0 2006.182.07:36:28.17#ibcon#read 5, iclass 27, count 0 2006.182.07:36:28.17#ibcon#about to read 6, iclass 27, count 0 2006.182.07:36:28.17#ibcon#read 6, iclass 27, count 0 2006.182.07:36:28.17#ibcon#end of sib2, iclass 27, count 0 2006.182.07:36:28.17#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:36:28.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:36:28.17#ibcon#[25=USB\r\n] 2006.182.07:36:28.17#ibcon#*before write, iclass 27, count 0 2006.182.07:36:28.17#ibcon#enter sib2, iclass 27, count 0 2006.182.07:36:28.17#ibcon#flushed, iclass 27, count 0 2006.182.07:36:28.17#ibcon#about to write, iclass 27, count 0 2006.182.07:36:28.17#ibcon#wrote, iclass 27, count 0 2006.182.07:36:28.17#ibcon#about to read 3, iclass 27, count 0 2006.182.07:36:28.20#ibcon#read 3, iclass 27, count 0 2006.182.07:36:28.20#ibcon#about to read 4, iclass 27, count 0 2006.182.07:36:28.20#ibcon#read 4, iclass 27, count 0 2006.182.07:36:28.20#ibcon#about to read 5, iclass 27, count 0 2006.182.07:36:28.20#ibcon#read 5, iclass 27, count 0 2006.182.07:36:28.20#ibcon#about to read 6, iclass 27, count 0 2006.182.07:36:28.20#ibcon#read 6, iclass 27, count 0 2006.182.07:36:28.20#ibcon#end of sib2, iclass 27, count 0 2006.182.07:36:28.20#ibcon#*after write, iclass 27, count 0 2006.182.07:36:28.20#ibcon#*before return 0, iclass 27, count 0 2006.182.07:36:28.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:28.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:28.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:36:28.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:36:28.20$vc4f8/valo=2,572.99 2006.182.07:36:28.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.07:36:28.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.07:36:28.20#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:28.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:36:28.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:36:28.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:36:28.20#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:36:28.20#ibcon#first serial, iclass 30, count 0 2006.182.07:36:28.20#ibcon#enter sib2, iclass 30, count 0 2006.182.07:36:28.20#ibcon#flushed, iclass 30, count 0 2006.182.07:36:28.20#ibcon#about to write, iclass 30, count 0 2006.182.07:36:28.20#ibcon#wrote, iclass 30, count 0 2006.182.07:36:28.20#ibcon#about to read 3, iclass 30, count 0 2006.182.07:36:28.22#abcon#<5=/03 0.5 1.5 27.45 821002.9\r\n> 2006.182.07:36:28.22#ibcon#read 3, iclass 30, count 0 2006.182.07:36:28.22#ibcon#about to read 4, iclass 30, count 0 2006.182.07:36:28.22#ibcon#read 4, iclass 30, count 0 2006.182.07:36:28.22#ibcon#about to read 5, iclass 30, count 0 2006.182.07:36:28.22#ibcon#read 5, iclass 30, count 0 2006.182.07:36:28.22#ibcon#about to read 6, iclass 30, count 0 2006.182.07:36:28.22#ibcon#read 6, iclass 30, count 0 2006.182.07:36:28.22#ibcon#end of sib2, iclass 30, count 0 2006.182.07:36:28.22#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:36:28.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:36:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:36:28.22#ibcon#*before write, iclass 30, count 0 2006.182.07:36:28.22#ibcon#enter sib2, iclass 30, count 0 2006.182.07:36:28.22#ibcon#flushed, iclass 30, count 0 2006.182.07:36:28.22#ibcon#about to write, iclass 30, count 0 2006.182.07:36:28.22#ibcon#wrote, iclass 30, count 0 2006.182.07:36:28.22#ibcon#about to read 3, iclass 30, count 0 2006.182.07:36:28.24#abcon#{5=INTERFACE CLEAR} 2006.182.07:36:28.26#ibcon#read 3, iclass 30, count 0 2006.182.07:36:28.26#ibcon#about to read 4, iclass 30, count 0 2006.182.07:36:28.26#ibcon#read 4, iclass 30, count 0 2006.182.07:36:28.26#ibcon#about to read 5, iclass 30, count 0 2006.182.07:36:28.26#ibcon#read 5, iclass 30, count 0 2006.182.07:36:28.26#ibcon#about to read 6, iclass 30, count 0 2006.182.07:36:28.26#ibcon#read 6, iclass 30, count 0 2006.182.07:36:28.26#ibcon#end of sib2, iclass 30, count 0 2006.182.07:36:28.26#ibcon#*after write, iclass 30, count 0 2006.182.07:36:28.26#ibcon#*before return 0, iclass 30, count 0 2006.182.07:36:28.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:36:28.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:36:28.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:36:28.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:36:28.26$vc4f8/va=2,7 2006.182.07:36:28.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.07:36:28.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.07:36:28.26#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:28.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:36:28.30#abcon#[5=S1D000X0/0*\r\n] 2006.182.07:36:28.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:36:28.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:36:28.32#ibcon#enter wrdev, iclass 34, count 2 2006.182.07:36:28.32#ibcon#first serial, iclass 34, count 2 2006.182.07:36:28.32#ibcon#enter sib2, iclass 34, count 2 2006.182.07:36:28.32#ibcon#flushed, iclass 34, count 2 2006.182.07:36:28.32#ibcon#about to write, iclass 34, count 2 2006.182.07:36:28.32#ibcon#wrote, iclass 34, count 2 2006.182.07:36:28.32#ibcon#about to read 3, iclass 34, count 2 2006.182.07:36:28.34#ibcon#read 3, iclass 34, count 2 2006.182.07:36:28.34#ibcon#about to read 4, iclass 34, count 2 2006.182.07:36:28.34#ibcon#read 4, iclass 34, count 2 2006.182.07:36:28.34#ibcon#about to read 5, iclass 34, count 2 2006.182.07:36:28.34#ibcon#read 5, iclass 34, count 2 2006.182.07:36:28.34#ibcon#about to read 6, iclass 34, count 2 2006.182.07:36:28.34#ibcon#read 6, iclass 34, count 2 2006.182.07:36:28.34#ibcon#end of sib2, iclass 34, count 2 2006.182.07:36:28.34#ibcon#*mode == 0, iclass 34, count 2 2006.182.07:36:28.34#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.07:36:28.34#ibcon#[25=AT02-07\r\n] 2006.182.07:36:28.34#ibcon#*before write, iclass 34, count 2 2006.182.07:36:28.34#ibcon#enter sib2, iclass 34, count 2 2006.182.07:36:28.34#ibcon#flushed, iclass 34, count 2 2006.182.07:36:28.34#ibcon#about to write, iclass 34, count 2 2006.182.07:36:28.34#ibcon#wrote, iclass 34, count 2 2006.182.07:36:28.34#ibcon#about to read 3, iclass 34, count 2 2006.182.07:36:28.37#ibcon#read 3, iclass 34, count 2 2006.182.07:36:28.37#ibcon#about to read 4, iclass 34, count 2 2006.182.07:36:28.37#ibcon#read 4, iclass 34, count 2 2006.182.07:36:28.37#ibcon#about to read 5, iclass 34, count 2 2006.182.07:36:28.37#ibcon#read 5, iclass 34, count 2 2006.182.07:36:28.37#ibcon#about to read 6, iclass 34, count 2 2006.182.07:36:28.37#ibcon#read 6, iclass 34, count 2 2006.182.07:36:28.37#ibcon#end of sib2, iclass 34, count 2 2006.182.07:36:28.37#ibcon#*after write, iclass 34, count 2 2006.182.07:36:28.37#ibcon#*before return 0, iclass 34, count 2 2006.182.07:36:28.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:36:28.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:36:28.37#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.07:36:28.37#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:28.37#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:36:28.49#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:36:28.49#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:36:28.49#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:36:28.49#ibcon#first serial, iclass 34, count 0 2006.182.07:36:28.49#ibcon#enter sib2, iclass 34, count 0 2006.182.07:36:28.49#ibcon#flushed, iclass 34, count 0 2006.182.07:36:28.49#ibcon#about to write, iclass 34, count 0 2006.182.07:36:28.49#ibcon#wrote, iclass 34, count 0 2006.182.07:36:28.49#ibcon#about to read 3, iclass 34, count 0 2006.182.07:36:28.51#ibcon#read 3, iclass 34, count 0 2006.182.07:36:28.51#ibcon#about to read 4, iclass 34, count 0 2006.182.07:36:28.51#ibcon#read 4, iclass 34, count 0 2006.182.07:36:28.51#ibcon#about to read 5, iclass 34, count 0 2006.182.07:36:28.51#ibcon#read 5, iclass 34, count 0 2006.182.07:36:28.51#ibcon#about to read 6, iclass 34, count 0 2006.182.07:36:28.51#ibcon#read 6, iclass 34, count 0 2006.182.07:36:28.51#ibcon#end of sib2, iclass 34, count 0 2006.182.07:36:28.51#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:36:28.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:36:28.51#ibcon#[25=USB\r\n] 2006.182.07:36:28.51#ibcon#*before write, iclass 34, count 0 2006.182.07:36:28.51#ibcon#enter sib2, iclass 34, count 0 2006.182.07:36:28.51#ibcon#flushed, iclass 34, count 0 2006.182.07:36:28.51#ibcon#about to write, iclass 34, count 0 2006.182.07:36:28.51#ibcon#wrote, iclass 34, count 0 2006.182.07:36:28.51#ibcon#about to read 3, iclass 34, count 0 2006.182.07:36:28.54#ibcon#read 3, iclass 34, count 0 2006.182.07:36:28.54#ibcon#about to read 4, iclass 34, count 0 2006.182.07:36:28.54#ibcon#read 4, iclass 34, count 0 2006.182.07:36:28.54#ibcon#about to read 5, iclass 34, count 0 2006.182.07:36:28.54#ibcon#read 5, iclass 34, count 0 2006.182.07:36:28.54#ibcon#about to read 6, iclass 34, count 0 2006.182.07:36:28.54#ibcon#read 6, iclass 34, count 0 2006.182.07:36:28.54#ibcon#end of sib2, iclass 34, count 0 2006.182.07:36:28.54#ibcon#*after write, iclass 34, count 0 2006.182.07:36:28.54#ibcon#*before return 0, iclass 34, count 0 2006.182.07:36:28.54#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:36:28.54#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:36:28.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:36:28.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:36:28.54$vc4f8/valo=3,672.99 2006.182.07:36:28.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.182.07:36:28.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.182.07:36:28.54#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:28.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:28.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:28.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:28.54#ibcon#enter wrdev, iclass 37, count 0 2006.182.07:36:28.54#ibcon#first serial, iclass 37, count 0 2006.182.07:36:28.54#ibcon#enter sib2, iclass 37, count 0 2006.182.07:36:28.54#ibcon#flushed, iclass 37, count 0 2006.182.07:36:28.54#ibcon#about to write, iclass 37, count 0 2006.182.07:36:28.54#ibcon#wrote, iclass 37, count 0 2006.182.07:36:28.54#ibcon#about to read 3, iclass 37, count 0 2006.182.07:36:28.56#ibcon#read 3, iclass 37, count 0 2006.182.07:36:28.56#ibcon#about to read 4, iclass 37, count 0 2006.182.07:36:28.56#ibcon#read 4, iclass 37, count 0 2006.182.07:36:28.56#ibcon#about to read 5, iclass 37, count 0 2006.182.07:36:28.56#ibcon#read 5, iclass 37, count 0 2006.182.07:36:28.56#ibcon#about to read 6, iclass 37, count 0 2006.182.07:36:28.56#ibcon#read 6, iclass 37, count 0 2006.182.07:36:28.56#ibcon#end of sib2, iclass 37, count 0 2006.182.07:36:28.56#ibcon#*mode == 0, iclass 37, count 0 2006.182.07:36:28.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.07:36:28.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:36:28.56#ibcon#*before write, iclass 37, count 0 2006.182.07:36:28.56#ibcon#enter sib2, iclass 37, count 0 2006.182.07:36:28.56#ibcon#flushed, iclass 37, count 0 2006.182.07:36:28.56#ibcon#about to write, iclass 37, count 0 2006.182.07:36:28.56#ibcon#wrote, iclass 37, count 0 2006.182.07:36:28.56#ibcon#about to read 3, iclass 37, count 0 2006.182.07:36:28.60#ibcon#read 3, iclass 37, count 0 2006.182.07:36:28.60#ibcon#about to read 4, iclass 37, count 0 2006.182.07:36:28.60#ibcon#read 4, iclass 37, count 0 2006.182.07:36:28.60#ibcon#about to read 5, iclass 37, count 0 2006.182.07:36:28.60#ibcon#read 5, iclass 37, count 0 2006.182.07:36:28.60#ibcon#about to read 6, iclass 37, count 0 2006.182.07:36:28.60#ibcon#read 6, iclass 37, count 0 2006.182.07:36:28.60#ibcon#end of sib2, iclass 37, count 0 2006.182.07:36:28.60#ibcon#*after write, iclass 37, count 0 2006.182.07:36:28.60#ibcon#*before return 0, iclass 37, count 0 2006.182.07:36:28.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:28.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:28.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.07:36:28.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.07:36:28.60$vc4f8/va=3,6 2006.182.07:36:28.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.07:36:28.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.07:36:28.60#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:28.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:28.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:28.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:28.66#ibcon#enter wrdev, iclass 39, count 2 2006.182.07:36:28.66#ibcon#first serial, iclass 39, count 2 2006.182.07:36:28.66#ibcon#enter sib2, iclass 39, count 2 2006.182.07:36:28.66#ibcon#flushed, iclass 39, count 2 2006.182.07:36:28.66#ibcon#about to write, iclass 39, count 2 2006.182.07:36:28.66#ibcon#wrote, iclass 39, count 2 2006.182.07:36:28.66#ibcon#about to read 3, iclass 39, count 2 2006.182.07:36:28.69#ibcon#read 3, iclass 39, count 2 2006.182.07:36:28.69#ibcon#about to read 4, iclass 39, count 2 2006.182.07:36:28.69#ibcon#read 4, iclass 39, count 2 2006.182.07:36:28.69#ibcon#about to read 5, iclass 39, count 2 2006.182.07:36:28.69#ibcon#read 5, iclass 39, count 2 2006.182.07:36:28.69#ibcon#about to read 6, iclass 39, count 2 2006.182.07:36:28.69#ibcon#read 6, iclass 39, count 2 2006.182.07:36:28.69#ibcon#end of sib2, iclass 39, count 2 2006.182.07:36:28.69#ibcon#*mode == 0, iclass 39, count 2 2006.182.07:36:28.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.07:36:28.69#ibcon#[25=AT03-06\r\n] 2006.182.07:36:28.69#ibcon#*before write, iclass 39, count 2 2006.182.07:36:28.69#ibcon#enter sib2, iclass 39, count 2 2006.182.07:36:28.69#ibcon#flushed, iclass 39, count 2 2006.182.07:36:28.69#ibcon#about to write, iclass 39, count 2 2006.182.07:36:28.69#ibcon#wrote, iclass 39, count 2 2006.182.07:36:28.69#ibcon#about to read 3, iclass 39, count 2 2006.182.07:36:28.72#ibcon#read 3, iclass 39, count 2 2006.182.07:36:28.72#ibcon#about to read 4, iclass 39, count 2 2006.182.07:36:28.72#ibcon#read 4, iclass 39, count 2 2006.182.07:36:28.72#ibcon#about to read 5, iclass 39, count 2 2006.182.07:36:28.72#ibcon#read 5, iclass 39, count 2 2006.182.07:36:28.72#ibcon#about to read 6, iclass 39, count 2 2006.182.07:36:28.72#ibcon#read 6, iclass 39, count 2 2006.182.07:36:28.72#ibcon#end of sib2, iclass 39, count 2 2006.182.07:36:28.72#ibcon#*after write, iclass 39, count 2 2006.182.07:36:28.72#ibcon#*before return 0, iclass 39, count 2 2006.182.07:36:28.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:28.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:28.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.07:36:28.72#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:28.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:28.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:28.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:28.84#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:36:28.84#ibcon#first serial, iclass 39, count 0 2006.182.07:36:28.84#ibcon#enter sib2, iclass 39, count 0 2006.182.07:36:28.84#ibcon#flushed, iclass 39, count 0 2006.182.07:36:28.84#ibcon#about to write, iclass 39, count 0 2006.182.07:36:28.84#ibcon#wrote, iclass 39, count 0 2006.182.07:36:28.84#ibcon#about to read 3, iclass 39, count 0 2006.182.07:36:28.86#ibcon#read 3, iclass 39, count 0 2006.182.07:36:28.86#ibcon#about to read 4, iclass 39, count 0 2006.182.07:36:28.86#ibcon#read 4, iclass 39, count 0 2006.182.07:36:28.86#ibcon#about to read 5, iclass 39, count 0 2006.182.07:36:28.86#ibcon#read 5, iclass 39, count 0 2006.182.07:36:28.86#ibcon#about to read 6, iclass 39, count 0 2006.182.07:36:28.86#ibcon#read 6, iclass 39, count 0 2006.182.07:36:28.86#ibcon#end of sib2, iclass 39, count 0 2006.182.07:36:28.86#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:36:28.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:36:28.86#ibcon#[25=USB\r\n] 2006.182.07:36:28.86#ibcon#*before write, iclass 39, count 0 2006.182.07:36:28.86#ibcon#enter sib2, iclass 39, count 0 2006.182.07:36:28.86#ibcon#flushed, iclass 39, count 0 2006.182.07:36:28.86#ibcon#about to write, iclass 39, count 0 2006.182.07:36:28.86#ibcon#wrote, iclass 39, count 0 2006.182.07:36:28.86#ibcon#about to read 3, iclass 39, count 0 2006.182.07:36:28.89#ibcon#read 3, iclass 39, count 0 2006.182.07:36:28.89#ibcon#about to read 4, iclass 39, count 0 2006.182.07:36:28.89#ibcon#read 4, iclass 39, count 0 2006.182.07:36:28.89#ibcon#about to read 5, iclass 39, count 0 2006.182.07:36:28.89#ibcon#read 5, iclass 39, count 0 2006.182.07:36:28.89#ibcon#about to read 6, iclass 39, count 0 2006.182.07:36:28.89#ibcon#read 6, iclass 39, count 0 2006.182.07:36:28.89#ibcon#end of sib2, iclass 39, count 0 2006.182.07:36:28.89#ibcon#*after write, iclass 39, count 0 2006.182.07:36:28.89#ibcon#*before return 0, iclass 39, count 0 2006.182.07:36:28.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:28.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:28.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:36:28.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:36:28.89$vc4f8/valo=4,832.99 2006.182.07:36:28.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.07:36:28.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.07:36:28.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:28.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:28.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:28.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:28.89#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:36:28.89#ibcon#first serial, iclass 3, count 0 2006.182.07:36:28.89#ibcon#enter sib2, iclass 3, count 0 2006.182.07:36:28.89#ibcon#flushed, iclass 3, count 0 2006.182.07:36:28.89#ibcon#about to write, iclass 3, count 0 2006.182.07:36:28.89#ibcon#wrote, iclass 3, count 0 2006.182.07:36:28.89#ibcon#about to read 3, iclass 3, count 0 2006.182.07:36:28.91#ibcon#read 3, iclass 3, count 0 2006.182.07:36:28.91#ibcon#about to read 4, iclass 3, count 0 2006.182.07:36:28.91#ibcon#read 4, iclass 3, count 0 2006.182.07:36:28.91#ibcon#about to read 5, iclass 3, count 0 2006.182.07:36:28.91#ibcon#read 5, iclass 3, count 0 2006.182.07:36:28.91#ibcon#about to read 6, iclass 3, count 0 2006.182.07:36:28.91#ibcon#read 6, iclass 3, count 0 2006.182.07:36:28.91#ibcon#end of sib2, iclass 3, count 0 2006.182.07:36:28.91#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:36:28.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:36:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:36:28.91#ibcon#*before write, iclass 3, count 0 2006.182.07:36:28.91#ibcon#enter sib2, iclass 3, count 0 2006.182.07:36:28.91#ibcon#flushed, iclass 3, count 0 2006.182.07:36:28.91#ibcon#about to write, iclass 3, count 0 2006.182.07:36:28.91#ibcon#wrote, iclass 3, count 0 2006.182.07:36:28.91#ibcon#about to read 3, iclass 3, count 0 2006.182.07:36:28.95#ibcon#read 3, iclass 3, count 0 2006.182.07:36:28.95#ibcon#about to read 4, iclass 3, count 0 2006.182.07:36:28.95#ibcon#read 4, iclass 3, count 0 2006.182.07:36:28.95#ibcon#about to read 5, iclass 3, count 0 2006.182.07:36:28.95#ibcon#read 5, iclass 3, count 0 2006.182.07:36:28.95#ibcon#about to read 6, iclass 3, count 0 2006.182.07:36:28.95#ibcon#read 6, iclass 3, count 0 2006.182.07:36:28.95#ibcon#end of sib2, iclass 3, count 0 2006.182.07:36:28.95#ibcon#*after write, iclass 3, count 0 2006.182.07:36:28.95#ibcon#*before return 0, iclass 3, count 0 2006.182.07:36:28.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:28.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:28.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:36:28.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:36:28.95$vc4f8/va=4,7 2006.182.07:36:28.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.07:36:28.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.07:36:28.95#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:28.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:29.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:29.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:29.01#ibcon#enter wrdev, iclass 5, count 2 2006.182.07:36:29.01#ibcon#first serial, iclass 5, count 2 2006.182.07:36:29.01#ibcon#enter sib2, iclass 5, count 2 2006.182.07:36:29.01#ibcon#flushed, iclass 5, count 2 2006.182.07:36:29.01#ibcon#about to write, iclass 5, count 2 2006.182.07:36:29.01#ibcon#wrote, iclass 5, count 2 2006.182.07:36:29.01#ibcon#about to read 3, iclass 5, count 2 2006.182.07:36:29.03#ibcon#read 3, iclass 5, count 2 2006.182.07:36:29.03#ibcon#about to read 4, iclass 5, count 2 2006.182.07:36:29.03#ibcon#read 4, iclass 5, count 2 2006.182.07:36:29.03#ibcon#about to read 5, iclass 5, count 2 2006.182.07:36:29.03#ibcon#read 5, iclass 5, count 2 2006.182.07:36:29.03#ibcon#about to read 6, iclass 5, count 2 2006.182.07:36:29.03#ibcon#read 6, iclass 5, count 2 2006.182.07:36:29.03#ibcon#end of sib2, iclass 5, count 2 2006.182.07:36:29.03#ibcon#*mode == 0, iclass 5, count 2 2006.182.07:36:29.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.07:36:29.03#ibcon#[25=AT04-07\r\n] 2006.182.07:36:29.03#ibcon#*before write, iclass 5, count 2 2006.182.07:36:29.03#ibcon#enter sib2, iclass 5, count 2 2006.182.07:36:29.03#ibcon#flushed, iclass 5, count 2 2006.182.07:36:29.03#ibcon#about to write, iclass 5, count 2 2006.182.07:36:29.03#ibcon#wrote, iclass 5, count 2 2006.182.07:36:29.03#ibcon#about to read 3, iclass 5, count 2 2006.182.07:36:29.06#ibcon#read 3, iclass 5, count 2 2006.182.07:36:29.06#ibcon#about to read 4, iclass 5, count 2 2006.182.07:36:29.06#ibcon#read 4, iclass 5, count 2 2006.182.07:36:29.06#ibcon#about to read 5, iclass 5, count 2 2006.182.07:36:29.06#ibcon#read 5, iclass 5, count 2 2006.182.07:36:29.06#ibcon#about to read 6, iclass 5, count 2 2006.182.07:36:29.06#ibcon#read 6, iclass 5, count 2 2006.182.07:36:29.06#ibcon#end of sib2, iclass 5, count 2 2006.182.07:36:29.06#ibcon#*after write, iclass 5, count 2 2006.182.07:36:29.06#ibcon#*before return 0, iclass 5, count 2 2006.182.07:36:29.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:29.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:29.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.07:36:29.06#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:29.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:29.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:29.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:29.18#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:36:29.18#ibcon#first serial, iclass 5, count 0 2006.182.07:36:29.18#ibcon#enter sib2, iclass 5, count 0 2006.182.07:36:29.18#ibcon#flushed, iclass 5, count 0 2006.182.07:36:29.18#ibcon#about to write, iclass 5, count 0 2006.182.07:36:29.18#ibcon#wrote, iclass 5, count 0 2006.182.07:36:29.18#ibcon#about to read 3, iclass 5, count 0 2006.182.07:36:29.20#ibcon#read 3, iclass 5, count 0 2006.182.07:36:29.20#ibcon#about to read 4, iclass 5, count 0 2006.182.07:36:29.20#ibcon#read 4, iclass 5, count 0 2006.182.07:36:29.20#ibcon#about to read 5, iclass 5, count 0 2006.182.07:36:29.20#ibcon#read 5, iclass 5, count 0 2006.182.07:36:29.20#ibcon#about to read 6, iclass 5, count 0 2006.182.07:36:29.20#ibcon#read 6, iclass 5, count 0 2006.182.07:36:29.20#ibcon#end of sib2, iclass 5, count 0 2006.182.07:36:29.20#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:36:29.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:36:29.20#ibcon#[25=USB\r\n] 2006.182.07:36:29.20#ibcon#*before write, iclass 5, count 0 2006.182.07:36:29.20#ibcon#enter sib2, iclass 5, count 0 2006.182.07:36:29.20#ibcon#flushed, iclass 5, count 0 2006.182.07:36:29.20#ibcon#about to write, iclass 5, count 0 2006.182.07:36:29.20#ibcon#wrote, iclass 5, count 0 2006.182.07:36:29.20#ibcon#about to read 3, iclass 5, count 0 2006.182.07:36:29.23#ibcon#read 3, iclass 5, count 0 2006.182.07:36:29.23#ibcon#about to read 4, iclass 5, count 0 2006.182.07:36:29.23#ibcon#read 4, iclass 5, count 0 2006.182.07:36:29.23#ibcon#about to read 5, iclass 5, count 0 2006.182.07:36:29.23#ibcon#read 5, iclass 5, count 0 2006.182.07:36:29.23#ibcon#about to read 6, iclass 5, count 0 2006.182.07:36:29.23#ibcon#read 6, iclass 5, count 0 2006.182.07:36:29.23#ibcon#end of sib2, iclass 5, count 0 2006.182.07:36:29.23#ibcon#*after write, iclass 5, count 0 2006.182.07:36:29.23#ibcon#*before return 0, iclass 5, count 0 2006.182.07:36:29.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:29.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:29.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:36:29.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:36:29.23$vc4f8/valo=5,652.99 2006.182.07:36:29.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.07:36:29.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.07:36:29.23#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:29.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:29.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:29.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:29.23#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:36:29.23#ibcon#first serial, iclass 7, count 0 2006.182.07:36:29.23#ibcon#enter sib2, iclass 7, count 0 2006.182.07:36:29.23#ibcon#flushed, iclass 7, count 0 2006.182.07:36:29.23#ibcon#about to write, iclass 7, count 0 2006.182.07:36:29.23#ibcon#wrote, iclass 7, count 0 2006.182.07:36:29.23#ibcon#about to read 3, iclass 7, count 0 2006.182.07:36:29.25#ibcon#read 3, iclass 7, count 0 2006.182.07:36:29.25#ibcon#about to read 4, iclass 7, count 0 2006.182.07:36:29.25#ibcon#read 4, iclass 7, count 0 2006.182.07:36:29.25#ibcon#about to read 5, iclass 7, count 0 2006.182.07:36:29.25#ibcon#read 5, iclass 7, count 0 2006.182.07:36:29.25#ibcon#about to read 6, iclass 7, count 0 2006.182.07:36:29.25#ibcon#read 6, iclass 7, count 0 2006.182.07:36:29.25#ibcon#end of sib2, iclass 7, count 0 2006.182.07:36:29.25#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:36:29.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:36:29.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:36:29.25#ibcon#*before write, iclass 7, count 0 2006.182.07:36:29.25#ibcon#enter sib2, iclass 7, count 0 2006.182.07:36:29.25#ibcon#flushed, iclass 7, count 0 2006.182.07:36:29.25#ibcon#about to write, iclass 7, count 0 2006.182.07:36:29.25#ibcon#wrote, iclass 7, count 0 2006.182.07:36:29.25#ibcon#about to read 3, iclass 7, count 0 2006.182.07:36:29.29#ibcon#read 3, iclass 7, count 0 2006.182.07:36:29.29#ibcon#about to read 4, iclass 7, count 0 2006.182.07:36:29.29#ibcon#read 4, iclass 7, count 0 2006.182.07:36:29.29#ibcon#about to read 5, iclass 7, count 0 2006.182.07:36:29.29#ibcon#read 5, iclass 7, count 0 2006.182.07:36:29.29#ibcon#about to read 6, iclass 7, count 0 2006.182.07:36:29.29#ibcon#read 6, iclass 7, count 0 2006.182.07:36:29.29#ibcon#end of sib2, iclass 7, count 0 2006.182.07:36:29.29#ibcon#*after write, iclass 7, count 0 2006.182.07:36:29.29#ibcon#*before return 0, iclass 7, count 0 2006.182.07:36:29.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:29.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:29.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:36:29.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:36:29.29$vc4f8/va=5,7 2006.182.07:36:29.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.07:36:29.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.07:36:29.29#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:29.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:29.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:29.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:29.35#ibcon#enter wrdev, iclass 11, count 2 2006.182.07:36:29.35#ibcon#first serial, iclass 11, count 2 2006.182.07:36:29.35#ibcon#enter sib2, iclass 11, count 2 2006.182.07:36:29.35#ibcon#flushed, iclass 11, count 2 2006.182.07:36:29.35#ibcon#about to write, iclass 11, count 2 2006.182.07:36:29.35#ibcon#wrote, iclass 11, count 2 2006.182.07:36:29.35#ibcon#about to read 3, iclass 11, count 2 2006.182.07:36:29.37#ibcon#read 3, iclass 11, count 2 2006.182.07:36:29.37#ibcon#about to read 4, iclass 11, count 2 2006.182.07:36:29.37#ibcon#read 4, iclass 11, count 2 2006.182.07:36:29.37#ibcon#about to read 5, iclass 11, count 2 2006.182.07:36:29.37#ibcon#read 5, iclass 11, count 2 2006.182.07:36:29.37#ibcon#about to read 6, iclass 11, count 2 2006.182.07:36:29.37#ibcon#read 6, iclass 11, count 2 2006.182.07:36:29.37#ibcon#end of sib2, iclass 11, count 2 2006.182.07:36:29.37#ibcon#*mode == 0, iclass 11, count 2 2006.182.07:36:29.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.07:36:29.37#ibcon#[25=AT05-07\r\n] 2006.182.07:36:29.37#ibcon#*before write, iclass 11, count 2 2006.182.07:36:29.37#ibcon#enter sib2, iclass 11, count 2 2006.182.07:36:29.37#ibcon#flushed, iclass 11, count 2 2006.182.07:36:29.37#ibcon#about to write, iclass 11, count 2 2006.182.07:36:29.37#ibcon#wrote, iclass 11, count 2 2006.182.07:36:29.37#ibcon#about to read 3, iclass 11, count 2 2006.182.07:36:29.40#ibcon#read 3, iclass 11, count 2 2006.182.07:36:29.40#ibcon#about to read 4, iclass 11, count 2 2006.182.07:36:29.40#ibcon#read 4, iclass 11, count 2 2006.182.07:36:29.40#ibcon#about to read 5, iclass 11, count 2 2006.182.07:36:29.40#ibcon#read 5, iclass 11, count 2 2006.182.07:36:29.40#ibcon#about to read 6, iclass 11, count 2 2006.182.07:36:29.40#ibcon#read 6, iclass 11, count 2 2006.182.07:36:29.40#ibcon#end of sib2, iclass 11, count 2 2006.182.07:36:29.40#ibcon#*after write, iclass 11, count 2 2006.182.07:36:29.40#ibcon#*before return 0, iclass 11, count 2 2006.182.07:36:29.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:29.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:29.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.07:36:29.40#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:29.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:29.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:29.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:29.52#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:36:29.52#ibcon#first serial, iclass 11, count 0 2006.182.07:36:29.52#ibcon#enter sib2, iclass 11, count 0 2006.182.07:36:29.52#ibcon#flushed, iclass 11, count 0 2006.182.07:36:29.52#ibcon#about to write, iclass 11, count 0 2006.182.07:36:29.52#ibcon#wrote, iclass 11, count 0 2006.182.07:36:29.52#ibcon#about to read 3, iclass 11, count 0 2006.182.07:36:29.54#ibcon#read 3, iclass 11, count 0 2006.182.07:36:29.54#ibcon#about to read 4, iclass 11, count 0 2006.182.07:36:29.54#ibcon#read 4, iclass 11, count 0 2006.182.07:36:29.54#ibcon#about to read 5, iclass 11, count 0 2006.182.07:36:29.54#ibcon#read 5, iclass 11, count 0 2006.182.07:36:29.54#ibcon#about to read 6, iclass 11, count 0 2006.182.07:36:29.54#ibcon#read 6, iclass 11, count 0 2006.182.07:36:29.54#ibcon#end of sib2, iclass 11, count 0 2006.182.07:36:29.54#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:36:29.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:36:29.54#ibcon#[25=USB\r\n] 2006.182.07:36:29.54#ibcon#*before write, iclass 11, count 0 2006.182.07:36:29.54#ibcon#enter sib2, iclass 11, count 0 2006.182.07:36:29.54#ibcon#flushed, iclass 11, count 0 2006.182.07:36:29.54#ibcon#about to write, iclass 11, count 0 2006.182.07:36:29.54#ibcon#wrote, iclass 11, count 0 2006.182.07:36:29.54#ibcon#about to read 3, iclass 11, count 0 2006.182.07:36:29.57#ibcon#read 3, iclass 11, count 0 2006.182.07:36:29.57#ibcon#about to read 4, iclass 11, count 0 2006.182.07:36:29.57#ibcon#read 4, iclass 11, count 0 2006.182.07:36:29.57#ibcon#about to read 5, iclass 11, count 0 2006.182.07:36:29.57#ibcon#read 5, iclass 11, count 0 2006.182.07:36:29.57#ibcon#about to read 6, iclass 11, count 0 2006.182.07:36:29.57#ibcon#read 6, iclass 11, count 0 2006.182.07:36:29.57#ibcon#end of sib2, iclass 11, count 0 2006.182.07:36:29.57#ibcon#*after write, iclass 11, count 0 2006.182.07:36:29.57#ibcon#*before return 0, iclass 11, count 0 2006.182.07:36:29.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:29.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:29.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:36:29.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:36:29.57$vc4f8/valo=6,772.99 2006.182.07:36:29.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.07:36:29.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.07:36:29.57#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:29.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:29.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:29.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:29.57#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:36:29.57#ibcon#first serial, iclass 13, count 0 2006.182.07:36:29.57#ibcon#enter sib2, iclass 13, count 0 2006.182.07:36:29.57#ibcon#flushed, iclass 13, count 0 2006.182.07:36:29.57#ibcon#about to write, iclass 13, count 0 2006.182.07:36:29.57#ibcon#wrote, iclass 13, count 0 2006.182.07:36:29.57#ibcon#about to read 3, iclass 13, count 0 2006.182.07:36:29.59#ibcon#read 3, iclass 13, count 0 2006.182.07:36:29.59#ibcon#about to read 4, iclass 13, count 0 2006.182.07:36:29.59#ibcon#read 4, iclass 13, count 0 2006.182.07:36:29.59#ibcon#about to read 5, iclass 13, count 0 2006.182.07:36:29.59#ibcon#read 5, iclass 13, count 0 2006.182.07:36:29.59#ibcon#about to read 6, iclass 13, count 0 2006.182.07:36:29.59#ibcon#read 6, iclass 13, count 0 2006.182.07:36:29.59#ibcon#end of sib2, iclass 13, count 0 2006.182.07:36:29.59#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:36:29.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:36:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:36:29.59#ibcon#*before write, iclass 13, count 0 2006.182.07:36:29.59#ibcon#enter sib2, iclass 13, count 0 2006.182.07:36:29.59#ibcon#flushed, iclass 13, count 0 2006.182.07:36:29.59#ibcon#about to write, iclass 13, count 0 2006.182.07:36:29.59#ibcon#wrote, iclass 13, count 0 2006.182.07:36:29.59#ibcon#about to read 3, iclass 13, count 0 2006.182.07:36:29.63#ibcon#read 3, iclass 13, count 0 2006.182.07:36:29.63#ibcon#about to read 4, iclass 13, count 0 2006.182.07:36:29.63#ibcon#read 4, iclass 13, count 0 2006.182.07:36:29.63#ibcon#about to read 5, iclass 13, count 0 2006.182.07:36:29.63#ibcon#read 5, iclass 13, count 0 2006.182.07:36:29.63#ibcon#about to read 6, iclass 13, count 0 2006.182.07:36:29.63#ibcon#read 6, iclass 13, count 0 2006.182.07:36:29.63#ibcon#end of sib2, iclass 13, count 0 2006.182.07:36:29.63#ibcon#*after write, iclass 13, count 0 2006.182.07:36:29.63#ibcon#*before return 0, iclass 13, count 0 2006.182.07:36:29.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:29.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:29.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:36:29.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:36:29.63$vc4f8/va=6,6 2006.182.07:36:29.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.182.07:36:29.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.182.07:36:29.63#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:29.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:36:29.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:36:29.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:36:29.69#ibcon#enter wrdev, iclass 15, count 2 2006.182.07:36:29.69#ibcon#first serial, iclass 15, count 2 2006.182.07:36:29.69#ibcon#enter sib2, iclass 15, count 2 2006.182.07:36:29.69#ibcon#flushed, iclass 15, count 2 2006.182.07:36:29.69#ibcon#about to write, iclass 15, count 2 2006.182.07:36:29.69#ibcon#wrote, iclass 15, count 2 2006.182.07:36:29.69#ibcon#about to read 3, iclass 15, count 2 2006.182.07:36:29.71#ibcon#read 3, iclass 15, count 2 2006.182.07:36:29.71#ibcon#about to read 4, iclass 15, count 2 2006.182.07:36:29.71#ibcon#read 4, iclass 15, count 2 2006.182.07:36:29.71#ibcon#about to read 5, iclass 15, count 2 2006.182.07:36:29.71#ibcon#read 5, iclass 15, count 2 2006.182.07:36:29.71#ibcon#about to read 6, iclass 15, count 2 2006.182.07:36:29.71#ibcon#read 6, iclass 15, count 2 2006.182.07:36:29.71#ibcon#end of sib2, iclass 15, count 2 2006.182.07:36:29.71#ibcon#*mode == 0, iclass 15, count 2 2006.182.07:36:29.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.182.07:36:29.71#ibcon#[25=AT06-06\r\n] 2006.182.07:36:29.71#ibcon#*before write, iclass 15, count 2 2006.182.07:36:29.71#ibcon#enter sib2, iclass 15, count 2 2006.182.07:36:29.71#ibcon#flushed, iclass 15, count 2 2006.182.07:36:29.71#ibcon#about to write, iclass 15, count 2 2006.182.07:36:29.71#ibcon#wrote, iclass 15, count 2 2006.182.07:36:29.71#ibcon#about to read 3, iclass 15, count 2 2006.182.07:36:29.74#ibcon#read 3, iclass 15, count 2 2006.182.07:36:29.74#ibcon#about to read 4, iclass 15, count 2 2006.182.07:36:29.74#ibcon#read 4, iclass 15, count 2 2006.182.07:36:29.74#ibcon#about to read 5, iclass 15, count 2 2006.182.07:36:29.74#ibcon#read 5, iclass 15, count 2 2006.182.07:36:29.74#ibcon#about to read 6, iclass 15, count 2 2006.182.07:36:29.74#ibcon#read 6, iclass 15, count 2 2006.182.07:36:29.74#ibcon#end of sib2, iclass 15, count 2 2006.182.07:36:29.74#ibcon#*after write, iclass 15, count 2 2006.182.07:36:29.74#ibcon#*before return 0, iclass 15, count 2 2006.182.07:36:29.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:36:29.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:36:29.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.182.07:36:29.74#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:29.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:36:29.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:36:29.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:36:29.86#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:36:29.86#ibcon#first serial, iclass 15, count 0 2006.182.07:36:29.86#ibcon#enter sib2, iclass 15, count 0 2006.182.07:36:29.86#ibcon#flushed, iclass 15, count 0 2006.182.07:36:29.86#ibcon#about to write, iclass 15, count 0 2006.182.07:36:29.86#ibcon#wrote, iclass 15, count 0 2006.182.07:36:29.86#ibcon#about to read 3, iclass 15, count 0 2006.182.07:36:29.88#ibcon#read 3, iclass 15, count 0 2006.182.07:36:29.88#ibcon#about to read 4, iclass 15, count 0 2006.182.07:36:29.88#ibcon#read 4, iclass 15, count 0 2006.182.07:36:29.88#ibcon#about to read 5, iclass 15, count 0 2006.182.07:36:29.88#ibcon#read 5, iclass 15, count 0 2006.182.07:36:29.88#ibcon#about to read 6, iclass 15, count 0 2006.182.07:36:29.88#ibcon#read 6, iclass 15, count 0 2006.182.07:36:29.88#ibcon#end of sib2, iclass 15, count 0 2006.182.07:36:29.88#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:36:29.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:36:29.88#ibcon#[25=USB\r\n] 2006.182.07:36:29.88#ibcon#*before write, iclass 15, count 0 2006.182.07:36:29.88#ibcon#enter sib2, iclass 15, count 0 2006.182.07:36:29.88#ibcon#flushed, iclass 15, count 0 2006.182.07:36:29.88#ibcon#about to write, iclass 15, count 0 2006.182.07:36:29.88#ibcon#wrote, iclass 15, count 0 2006.182.07:36:29.88#ibcon#about to read 3, iclass 15, count 0 2006.182.07:36:29.91#ibcon#read 3, iclass 15, count 0 2006.182.07:36:29.91#ibcon#about to read 4, iclass 15, count 0 2006.182.07:36:29.91#ibcon#read 4, iclass 15, count 0 2006.182.07:36:29.91#ibcon#about to read 5, iclass 15, count 0 2006.182.07:36:29.91#ibcon#read 5, iclass 15, count 0 2006.182.07:36:29.91#ibcon#about to read 6, iclass 15, count 0 2006.182.07:36:29.91#ibcon#read 6, iclass 15, count 0 2006.182.07:36:29.91#ibcon#end of sib2, iclass 15, count 0 2006.182.07:36:29.91#ibcon#*after write, iclass 15, count 0 2006.182.07:36:29.91#ibcon#*before return 0, iclass 15, count 0 2006.182.07:36:29.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:36:29.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:36:29.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:36:29.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:36:29.91$vc4f8/valo=7,832.99 2006.182.07:36:29.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.07:36:29.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.07:36:29.91#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:29.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:36:29.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:36:29.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:36:29.91#ibcon#enter wrdev, iclass 17, count 0 2006.182.07:36:29.91#ibcon#first serial, iclass 17, count 0 2006.182.07:36:29.91#ibcon#enter sib2, iclass 17, count 0 2006.182.07:36:29.91#ibcon#flushed, iclass 17, count 0 2006.182.07:36:29.91#ibcon#about to write, iclass 17, count 0 2006.182.07:36:29.91#ibcon#wrote, iclass 17, count 0 2006.182.07:36:29.91#ibcon#about to read 3, iclass 17, count 0 2006.182.07:36:29.93#ibcon#read 3, iclass 17, count 0 2006.182.07:36:29.93#ibcon#about to read 4, iclass 17, count 0 2006.182.07:36:29.93#ibcon#read 4, iclass 17, count 0 2006.182.07:36:29.93#ibcon#about to read 5, iclass 17, count 0 2006.182.07:36:29.93#ibcon#read 5, iclass 17, count 0 2006.182.07:36:29.93#ibcon#about to read 6, iclass 17, count 0 2006.182.07:36:29.93#ibcon#read 6, iclass 17, count 0 2006.182.07:36:29.93#ibcon#end of sib2, iclass 17, count 0 2006.182.07:36:29.93#ibcon#*mode == 0, iclass 17, count 0 2006.182.07:36:29.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.07:36:29.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:36:29.93#ibcon#*before write, iclass 17, count 0 2006.182.07:36:29.93#ibcon#enter sib2, iclass 17, count 0 2006.182.07:36:29.93#ibcon#flushed, iclass 17, count 0 2006.182.07:36:29.93#ibcon#about to write, iclass 17, count 0 2006.182.07:36:29.93#ibcon#wrote, iclass 17, count 0 2006.182.07:36:29.93#ibcon#about to read 3, iclass 17, count 0 2006.182.07:36:29.97#ibcon#read 3, iclass 17, count 0 2006.182.07:36:29.97#ibcon#about to read 4, iclass 17, count 0 2006.182.07:36:29.97#ibcon#read 4, iclass 17, count 0 2006.182.07:36:29.97#ibcon#about to read 5, iclass 17, count 0 2006.182.07:36:29.97#ibcon#read 5, iclass 17, count 0 2006.182.07:36:29.97#ibcon#about to read 6, iclass 17, count 0 2006.182.07:36:29.97#ibcon#read 6, iclass 17, count 0 2006.182.07:36:29.97#ibcon#end of sib2, iclass 17, count 0 2006.182.07:36:29.97#ibcon#*after write, iclass 17, count 0 2006.182.07:36:29.97#ibcon#*before return 0, iclass 17, count 0 2006.182.07:36:29.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:36:29.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:36:29.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.07:36:29.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.07:36:29.97$vc4f8/va=7,6 2006.182.07:36:29.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.182.07:36:29.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.182.07:36:29.97#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:29.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:36:30.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:36:30.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:36:30.03#ibcon#enter wrdev, iclass 19, count 2 2006.182.07:36:30.03#ibcon#first serial, iclass 19, count 2 2006.182.07:36:30.03#ibcon#enter sib2, iclass 19, count 2 2006.182.07:36:30.03#ibcon#flushed, iclass 19, count 2 2006.182.07:36:30.03#ibcon#about to write, iclass 19, count 2 2006.182.07:36:30.03#ibcon#wrote, iclass 19, count 2 2006.182.07:36:30.03#ibcon#about to read 3, iclass 19, count 2 2006.182.07:36:30.05#ibcon#read 3, iclass 19, count 2 2006.182.07:36:30.05#ibcon#about to read 4, iclass 19, count 2 2006.182.07:36:30.05#ibcon#read 4, iclass 19, count 2 2006.182.07:36:30.05#ibcon#about to read 5, iclass 19, count 2 2006.182.07:36:30.05#ibcon#read 5, iclass 19, count 2 2006.182.07:36:30.05#ibcon#about to read 6, iclass 19, count 2 2006.182.07:36:30.05#ibcon#read 6, iclass 19, count 2 2006.182.07:36:30.05#ibcon#end of sib2, iclass 19, count 2 2006.182.07:36:30.05#ibcon#*mode == 0, iclass 19, count 2 2006.182.07:36:30.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.182.07:36:30.05#ibcon#[25=AT07-06\r\n] 2006.182.07:36:30.05#ibcon#*before write, iclass 19, count 2 2006.182.07:36:30.05#ibcon#enter sib2, iclass 19, count 2 2006.182.07:36:30.05#ibcon#flushed, iclass 19, count 2 2006.182.07:36:30.05#ibcon#about to write, iclass 19, count 2 2006.182.07:36:30.05#ibcon#wrote, iclass 19, count 2 2006.182.07:36:30.05#ibcon#about to read 3, iclass 19, count 2 2006.182.07:36:30.08#ibcon#read 3, iclass 19, count 2 2006.182.07:36:30.08#ibcon#about to read 4, iclass 19, count 2 2006.182.07:36:30.08#ibcon#read 4, iclass 19, count 2 2006.182.07:36:30.08#ibcon#about to read 5, iclass 19, count 2 2006.182.07:36:30.08#ibcon#read 5, iclass 19, count 2 2006.182.07:36:30.08#ibcon#about to read 6, iclass 19, count 2 2006.182.07:36:30.08#ibcon#read 6, iclass 19, count 2 2006.182.07:36:30.08#ibcon#end of sib2, iclass 19, count 2 2006.182.07:36:30.08#ibcon#*after write, iclass 19, count 2 2006.182.07:36:30.08#ibcon#*before return 0, iclass 19, count 2 2006.182.07:36:30.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:36:30.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:36:30.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.182.07:36:30.08#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:30.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:36:30.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:36:30.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:36:30.20#ibcon#enter wrdev, iclass 19, count 0 2006.182.07:36:30.20#ibcon#first serial, iclass 19, count 0 2006.182.07:36:30.20#ibcon#enter sib2, iclass 19, count 0 2006.182.07:36:30.20#ibcon#flushed, iclass 19, count 0 2006.182.07:36:30.20#ibcon#about to write, iclass 19, count 0 2006.182.07:36:30.20#ibcon#wrote, iclass 19, count 0 2006.182.07:36:30.20#ibcon#about to read 3, iclass 19, count 0 2006.182.07:36:30.22#ibcon#read 3, iclass 19, count 0 2006.182.07:36:30.22#ibcon#about to read 4, iclass 19, count 0 2006.182.07:36:30.22#ibcon#read 4, iclass 19, count 0 2006.182.07:36:30.22#ibcon#about to read 5, iclass 19, count 0 2006.182.07:36:30.22#ibcon#read 5, iclass 19, count 0 2006.182.07:36:30.22#ibcon#about to read 6, iclass 19, count 0 2006.182.07:36:30.22#ibcon#read 6, iclass 19, count 0 2006.182.07:36:30.22#ibcon#end of sib2, iclass 19, count 0 2006.182.07:36:30.22#ibcon#*mode == 0, iclass 19, count 0 2006.182.07:36:30.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.07:36:30.22#ibcon#[25=USB\r\n] 2006.182.07:36:30.22#ibcon#*before write, iclass 19, count 0 2006.182.07:36:30.22#ibcon#enter sib2, iclass 19, count 0 2006.182.07:36:30.22#ibcon#flushed, iclass 19, count 0 2006.182.07:36:30.22#ibcon#about to write, iclass 19, count 0 2006.182.07:36:30.22#ibcon#wrote, iclass 19, count 0 2006.182.07:36:30.22#ibcon#about to read 3, iclass 19, count 0 2006.182.07:36:30.25#ibcon#read 3, iclass 19, count 0 2006.182.07:36:30.25#ibcon#about to read 4, iclass 19, count 0 2006.182.07:36:30.25#ibcon#read 4, iclass 19, count 0 2006.182.07:36:30.25#ibcon#about to read 5, iclass 19, count 0 2006.182.07:36:30.25#ibcon#read 5, iclass 19, count 0 2006.182.07:36:30.25#ibcon#about to read 6, iclass 19, count 0 2006.182.07:36:30.25#ibcon#read 6, iclass 19, count 0 2006.182.07:36:30.25#ibcon#end of sib2, iclass 19, count 0 2006.182.07:36:30.25#ibcon#*after write, iclass 19, count 0 2006.182.07:36:30.25#ibcon#*before return 0, iclass 19, count 0 2006.182.07:36:30.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:36:30.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:36:30.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.07:36:30.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.07:36:30.25$vc4f8/valo=8,852.99 2006.182.07:36:30.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.07:36:30.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.07:36:30.25#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:30.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:36:30.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:36:30.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:36:30.25#ibcon#enter wrdev, iclass 21, count 0 2006.182.07:36:30.25#ibcon#first serial, iclass 21, count 0 2006.182.07:36:30.25#ibcon#enter sib2, iclass 21, count 0 2006.182.07:36:30.25#ibcon#flushed, iclass 21, count 0 2006.182.07:36:30.25#ibcon#about to write, iclass 21, count 0 2006.182.07:36:30.25#ibcon#wrote, iclass 21, count 0 2006.182.07:36:30.25#ibcon#about to read 3, iclass 21, count 0 2006.182.07:36:30.27#ibcon#read 3, iclass 21, count 0 2006.182.07:36:30.27#ibcon#about to read 4, iclass 21, count 0 2006.182.07:36:30.27#ibcon#read 4, iclass 21, count 0 2006.182.07:36:30.27#ibcon#about to read 5, iclass 21, count 0 2006.182.07:36:30.27#ibcon#read 5, iclass 21, count 0 2006.182.07:36:30.27#ibcon#about to read 6, iclass 21, count 0 2006.182.07:36:30.27#ibcon#read 6, iclass 21, count 0 2006.182.07:36:30.27#ibcon#end of sib2, iclass 21, count 0 2006.182.07:36:30.27#ibcon#*mode == 0, iclass 21, count 0 2006.182.07:36:30.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.07:36:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:36:30.27#ibcon#*before write, iclass 21, count 0 2006.182.07:36:30.27#ibcon#enter sib2, iclass 21, count 0 2006.182.07:36:30.27#ibcon#flushed, iclass 21, count 0 2006.182.07:36:30.27#ibcon#about to write, iclass 21, count 0 2006.182.07:36:30.27#ibcon#wrote, iclass 21, count 0 2006.182.07:36:30.27#ibcon#about to read 3, iclass 21, count 0 2006.182.07:36:30.31#ibcon#read 3, iclass 21, count 0 2006.182.07:36:30.31#ibcon#about to read 4, iclass 21, count 0 2006.182.07:36:30.31#ibcon#read 4, iclass 21, count 0 2006.182.07:36:30.31#ibcon#about to read 5, iclass 21, count 0 2006.182.07:36:30.31#ibcon#read 5, iclass 21, count 0 2006.182.07:36:30.31#ibcon#about to read 6, iclass 21, count 0 2006.182.07:36:30.31#ibcon#read 6, iclass 21, count 0 2006.182.07:36:30.31#ibcon#end of sib2, iclass 21, count 0 2006.182.07:36:30.31#ibcon#*after write, iclass 21, count 0 2006.182.07:36:30.31#ibcon#*before return 0, iclass 21, count 0 2006.182.07:36:30.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:36:30.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:36:30.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.07:36:30.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.07:36:30.31$vc4f8/va=8,7 2006.182.07:36:30.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.182.07:36:30.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.182.07:36:30.31#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:30.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:36:30.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:36:30.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:36:30.37#ibcon#enter wrdev, iclass 23, count 2 2006.182.07:36:30.37#ibcon#first serial, iclass 23, count 2 2006.182.07:36:30.37#ibcon#enter sib2, iclass 23, count 2 2006.182.07:36:30.37#ibcon#flushed, iclass 23, count 2 2006.182.07:36:30.37#ibcon#about to write, iclass 23, count 2 2006.182.07:36:30.37#ibcon#wrote, iclass 23, count 2 2006.182.07:36:30.37#ibcon#about to read 3, iclass 23, count 2 2006.182.07:36:30.39#ibcon#read 3, iclass 23, count 2 2006.182.07:36:30.39#ibcon#about to read 4, iclass 23, count 2 2006.182.07:36:30.39#ibcon#read 4, iclass 23, count 2 2006.182.07:36:30.39#ibcon#about to read 5, iclass 23, count 2 2006.182.07:36:30.39#ibcon#read 5, iclass 23, count 2 2006.182.07:36:30.39#ibcon#about to read 6, iclass 23, count 2 2006.182.07:36:30.39#ibcon#read 6, iclass 23, count 2 2006.182.07:36:30.39#ibcon#end of sib2, iclass 23, count 2 2006.182.07:36:30.39#ibcon#*mode == 0, iclass 23, count 2 2006.182.07:36:30.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.182.07:36:30.39#ibcon#[25=AT08-07\r\n] 2006.182.07:36:30.39#ibcon#*before write, iclass 23, count 2 2006.182.07:36:30.39#ibcon#enter sib2, iclass 23, count 2 2006.182.07:36:30.39#ibcon#flushed, iclass 23, count 2 2006.182.07:36:30.39#ibcon#about to write, iclass 23, count 2 2006.182.07:36:30.39#ibcon#wrote, iclass 23, count 2 2006.182.07:36:30.39#ibcon#about to read 3, iclass 23, count 2 2006.182.07:36:30.42#ibcon#read 3, iclass 23, count 2 2006.182.07:36:30.42#ibcon#about to read 4, iclass 23, count 2 2006.182.07:36:30.42#ibcon#read 4, iclass 23, count 2 2006.182.07:36:30.42#ibcon#about to read 5, iclass 23, count 2 2006.182.07:36:30.42#ibcon#read 5, iclass 23, count 2 2006.182.07:36:30.42#ibcon#about to read 6, iclass 23, count 2 2006.182.07:36:30.42#ibcon#read 6, iclass 23, count 2 2006.182.07:36:30.42#ibcon#end of sib2, iclass 23, count 2 2006.182.07:36:30.42#ibcon#*after write, iclass 23, count 2 2006.182.07:36:30.42#ibcon#*before return 0, iclass 23, count 2 2006.182.07:36:30.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:36:30.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:36:30.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.182.07:36:30.42#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:30.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:36:30.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:36:30.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:36:30.54#ibcon#enter wrdev, iclass 23, count 0 2006.182.07:36:30.54#ibcon#first serial, iclass 23, count 0 2006.182.07:36:30.54#ibcon#enter sib2, iclass 23, count 0 2006.182.07:36:30.54#ibcon#flushed, iclass 23, count 0 2006.182.07:36:30.54#ibcon#about to write, iclass 23, count 0 2006.182.07:36:30.54#ibcon#wrote, iclass 23, count 0 2006.182.07:36:30.54#ibcon#about to read 3, iclass 23, count 0 2006.182.07:36:30.56#ibcon#read 3, iclass 23, count 0 2006.182.07:36:30.56#ibcon#about to read 4, iclass 23, count 0 2006.182.07:36:30.56#ibcon#read 4, iclass 23, count 0 2006.182.07:36:30.56#ibcon#about to read 5, iclass 23, count 0 2006.182.07:36:30.56#ibcon#read 5, iclass 23, count 0 2006.182.07:36:30.56#ibcon#about to read 6, iclass 23, count 0 2006.182.07:36:30.56#ibcon#read 6, iclass 23, count 0 2006.182.07:36:30.56#ibcon#end of sib2, iclass 23, count 0 2006.182.07:36:30.56#ibcon#*mode == 0, iclass 23, count 0 2006.182.07:36:30.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.07:36:30.56#ibcon#[25=USB\r\n] 2006.182.07:36:30.56#ibcon#*before write, iclass 23, count 0 2006.182.07:36:30.56#ibcon#enter sib2, iclass 23, count 0 2006.182.07:36:30.56#ibcon#flushed, iclass 23, count 0 2006.182.07:36:30.56#ibcon#about to write, iclass 23, count 0 2006.182.07:36:30.56#ibcon#wrote, iclass 23, count 0 2006.182.07:36:30.56#ibcon#about to read 3, iclass 23, count 0 2006.182.07:36:30.59#ibcon#read 3, iclass 23, count 0 2006.182.07:36:30.59#ibcon#about to read 4, iclass 23, count 0 2006.182.07:36:30.59#ibcon#read 4, iclass 23, count 0 2006.182.07:36:30.59#ibcon#about to read 5, iclass 23, count 0 2006.182.07:36:30.59#ibcon#read 5, iclass 23, count 0 2006.182.07:36:30.59#ibcon#about to read 6, iclass 23, count 0 2006.182.07:36:30.59#ibcon#read 6, iclass 23, count 0 2006.182.07:36:30.59#ibcon#end of sib2, iclass 23, count 0 2006.182.07:36:30.59#ibcon#*after write, iclass 23, count 0 2006.182.07:36:30.59#ibcon#*before return 0, iclass 23, count 0 2006.182.07:36:30.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:36:30.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:36:30.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.07:36:30.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.07:36:30.59$vc4f8/vblo=1,632.99 2006.182.07:36:30.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.07:36:30.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.07:36:30.59#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:30.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:30.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:30.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:30.59#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:36:30.59#ibcon#first serial, iclass 25, count 0 2006.182.07:36:30.59#ibcon#enter sib2, iclass 25, count 0 2006.182.07:36:30.59#ibcon#flushed, iclass 25, count 0 2006.182.07:36:30.59#ibcon#about to write, iclass 25, count 0 2006.182.07:36:30.59#ibcon#wrote, iclass 25, count 0 2006.182.07:36:30.59#ibcon#about to read 3, iclass 25, count 0 2006.182.07:36:30.61#ibcon#read 3, iclass 25, count 0 2006.182.07:36:30.61#ibcon#about to read 4, iclass 25, count 0 2006.182.07:36:30.61#ibcon#read 4, iclass 25, count 0 2006.182.07:36:30.61#ibcon#about to read 5, iclass 25, count 0 2006.182.07:36:30.61#ibcon#read 5, iclass 25, count 0 2006.182.07:36:30.61#ibcon#about to read 6, iclass 25, count 0 2006.182.07:36:30.61#ibcon#read 6, iclass 25, count 0 2006.182.07:36:30.61#ibcon#end of sib2, iclass 25, count 0 2006.182.07:36:30.61#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:36:30.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:36:30.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:36:30.61#ibcon#*before write, iclass 25, count 0 2006.182.07:36:30.61#ibcon#enter sib2, iclass 25, count 0 2006.182.07:36:30.61#ibcon#flushed, iclass 25, count 0 2006.182.07:36:30.61#ibcon#about to write, iclass 25, count 0 2006.182.07:36:30.61#ibcon#wrote, iclass 25, count 0 2006.182.07:36:30.61#ibcon#about to read 3, iclass 25, count 0 2006.182.07:36:30.65#ibcon#read 3, iclass 25, count 0 2006.182.07:36:30.65#ibcon#about to read 4, iclass 25, count 0 2006.182.07:36:30.65#ibcon#read 4, iclass 25, count 0 2006.182.07:36:30.65#ibcon#about to read 5, iclass 25, count 0 2006.182.07:36:30.65#ibcon#read 5, iclass 25, count 0 2006.182.07:36:30.65#ibcon#about to read 6, iclass 25, count 0 2006.182.07:36:30.65#ibcon#read 6, iclass 25, count 0 2006.182.07:36:30.65#ibcon#end of sib2, iclass 25, count 0 2006.182.07:36:30.65#ibcon#*after write, iclass 25, count 0 2006.182.07:36:30.65#ibcon#*before return 0, iclass 25, count 0 2006.182.07:36:30.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:30.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:36:30.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:36:30.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:36:30.65$vc4f8/vb=1,4 2006.182.07:36:30.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.182.07:36:30.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.182.07:36:30.65#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:30.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:30.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:30.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:30.65#ibcon#enter wrdev, iclass 27, count 2 2006.182.07:36:30.65#ibcon#first serial, iclass 27, count 2 2006.182.07:36:30.65#ibcon#enter sib2, iclass 27, count 2 2006.182.07:36:30.65#ibcon#flushed, iclass 27, count 2 2006.182.07:36:30.65#ibcon#about to write, iclass 27, count 2 2006.182.07:36:30.65#ibcon#wrote, iclass 27, count 2 2006.182.07:36:30.65#ibcon#about to read 3, iclass 27, count 2 2006.182.07:36:30.67#ibcon#read 3, iclass 27, count 2 2006.182.07:36:30.67#ibcon#about to read 4, iclass 27, count 2 2006.182.07:36:30.67#ibcon#read 4, iclass 27, count 2 2006.182.07:36:30.67#ibcon#about to read 5, iclass 27, count 2 2006.182.07:36:30.67#ibcon#read 5, iclass 27, count 2 2006.182.07:36:30.67#ibcon#about to read 6, iclass 27, count 2 2006.182.07:36:30.67#ibcon#read 6, iclass 27, count 2 2006.182.07:36:30.67#ibcon#end of sib2, iclass 27, count 2 2006.182.07:36:30.67#ibcon#*mode == 0, iclass 27, count 2 2006.182.07:36:30.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.182.07:36:30.67#ibcon#[27=AT01-04\r\n] 2006.182.07:36:30.67#ibcon#*before write, iclass 27, count 2 2006.182.07:36:30.67#ibcon#enter sib2, iclass 27, count 2 2006.182.07:36:30.67#ibcon#flushed, iclass 27, count 2 2006.182.07:36:30.67#ibcon#about to write, iclass 27, count 2 2006.182.07:36:30.67#ibcon#wrote, iclass 27, count 2 2006.182.07:36:30.67#ibcon#about to read 3, iclass 27, count 2 2006.182.07:36:30.70#ibcon#read 3, iclass 27, count 2 2006.182.07:36:30.70#ibcon#about to read 4, iclass 27, count 2 2006.182.07:36:30.70#ibcon#read 4, iclass 27, count 2 2006.182.07:36:30.70#ibcon#about to read 5, iclass 27, count 2 2006.182.07:36:30.70#ibcon#read 5, iclass 27, count 2 2006.182.07:36:30.70#ibcon#about to read 6, iclass 27, count 2 2006.182.07:36:30.70#ibcon#read 6, iclass 27, count 2 2006.182.07:36:30.70#ibcon#end of sib2, iclass 27, count 2 2006.182.07:36:30.70#ibcon#*after write, iclass 27, count 2 2006.182.07:36:30.70#ibcon#*before return 0, iclass 27, count 2 2006.182.07:36:30.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:30.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:36:30.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.182.07:36:30.70#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:30.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:30.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:30.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:30.82#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:36:30.82#ibcon#first serial, iclass 27, count 0 2006.182.07:36:30.82#ibcon#enter sib2, iclass 27, count 0 2006.182.07:36:30.82#ibcon#flushed, iclass 27, count 0 2006.182.07:36:30.82#ibcon#about to write, iclass 27, count 0 2006.182.07:36:30.82#ibcon#wrote, iclass 27, count 0 2006.182.07:36:30.82#ibcon#about to read 3, iclass 27, count 0 2006.182.07:36:30.84#ibcon#read 3, iclass 27, count 0 2006.182.07:36:30.84#ibcon#about to read 4, iclass 27, count 0 2006.182.07:36:30.84#ibcon#read 4, iclass 27, count 0 2006.182.07:36:30.84#ibcon#about to read 5, iclass 27, count 0 2006.182.07:36:30.84#ibcon#read 5, iclass 27, count 0 2006.182.07:36:30.84#ibcon#about to read 6, iclass 27, count 0 2006.182.07:36:30.84#ibcon#read 6, iclass 27, count 0 2006.182.07:36:30.84#ibcon#end of sib2, iclass 27, count 0 2006.182.07:36:30.84#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:36:30.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:36:30.84#ibcon#[27=USB\r\n] 2006.182.07:36:30.84#ibcon#*before write, iclass 27, count 0 2006.182.07:36:30.84#ibcon#enter sib2, iclass 27, count 0 2006.182.07:36:30.84#ibcon#flushed, iclass 27, count 0 2006.182.07:36:30.84#ibcon#about to write, iclass 27, count 0 2006.182.07:36:30.84#ibcon#wrote, iclass 27, count 0 2006.182.07:36:30.84#ibcon#about to read 3, iclass 27, count 0 2006.182.07:36:30.87#ibcon#read 3, iclass 27, count 0 2006.182.07:36:30.87#ibcon#about to read 4, iclass 27, count 0 2006.182.07:36:30.87#ibcon#read 4, iclass 27, count 0 2006.182.07:36:30.87#ibcon#about to read 5, iclass 27, count 0 2006.182.07:36:30.87#ibcon#read 5, iclass 27, count 0 2006.182.07:36:30.87#ibcon#about to read 6, iclass 27, count 0 2006.182.07:36:30.87#ibcon#read 6, iclass 27, count 0 2006.182.07:36:30.87#ibcon#end of sib2, iclass 27, count 0 2006.182.07:36:30.87#ibcon#*after write, iclass 27, count 0 2006.182.07:36:30.87#ibcon#*before return 0, iclass 27, count 0 2006.182.07:36:30.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:30.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:36:30.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:36:30.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:36:30.87$vc4f8/vblo=2,640.99 2006.182.07:36:30.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.07:36:30.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.07:36:30.87#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:30.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:36:30.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:36:30.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:36:30.87#ibcon#enter wrdev, iclass 29, count 0 2006.182.07:36:30.87#ibcon#first serial, iclass 29, count 0 2006.182.07:36:30.87#ibcon#enter sib2, iclass 29, count 0 2006.182.07:36:30.87#ibcon#flushed, iclass 29, count 0 2006.182.07:36:30.87#ibcon#about to write, iclass 29, count 0 2006.182.07:36:30.87#ibcon#wrote, iclass 29, count 0 2006.182.07:36:30.87#ibcon#about to read 3, iclass 29, count 0 2006.182.07:36:30.89#ibcon#read 3, iclass 29, count 0 2006.182.07:36:30.89#ibcon#about to read 4, iclass 29, count 0 2006.182.07:36:30.89#ibcon#read 4, iclass 29, count 0 2006.182.07:36:30.89#ibcon#about to read 5, iclass 29, count 0 2006.182.07:36:30.89#ibcon#read 5, iclass 29, count 0 2006.182.07:36:30.89#ibcon#about to read 6, iclass 29, count 0 2006.182.07:36:30.89#ibcon#read 6, iclass 29, count 0 2006.182.07:36:30.89#ibcon#end of sib2, iclass 29, count 0 2006.182.07:36:30.89#ibcon#*mode == 0, iclass 29, count 0 2006.182.07:36:30.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.07:36:30.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:36:30.89#ibcon#*before write, iclass 29, count 0 2006.182.07:36:30.89#ibcon#enter sib2, iclass 29, count 0 2006.182.07:36:30.89#ibcon#flushed, iclass 29, count 0 2006.182.07:36:30.89#ibcon#about to write, iclass 29, count 0 2006.182.07:36:30.89#ibcon#wrote, iclass 29, count 0 2006.182.07:36:30.89#ibcon#about to read 3, iclass 29, count 0 2006.182.07:36:30.93#ibcon#read 3, iclass 29, count 0 2006.182.07:36:30.93#ibcon#about to read 4, iclass 29, count 0 2006.182.07:36:30.93#ibcon#read 4, iclass 29, count 0 2006.182.07:36:30.93#ibcon#about to read 5, iclass 29, count 0 2006.182.07:36:30.93#ibcon#read 5, iclass 29, count 0 2006.182.07:36:30.93#ibcon#about to read 6, iclass 29, count 0 2006.182.07:36:30.93#ibcon#read 6, iclass 29, count 0 2006.182.07:36:30.93#ibcon#end of sib2, iclass 29, count 0 2006.182.07:36:30.93#ibcon#*after write, iclass 29, count 0 2006.182.07:36:30.93#ibcon#*before return 0, iclass 29, count 0 2006.182.07:36:30.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:36:30.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:36:30.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.07:36:30.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.07:36:30.93$vc4f8/vb=2,4 2006.182.07:36:30.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.182.07:36:30.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.182.07:36:30.93#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:30.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:36:30.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:36:30.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:36:30.99#ibcon#enter wrdev, iclass 31, count 2 2006.182.07:36:30.99#ibcon#first serial, iclass 31, count 2 2006.182.07:36:30.99#ibcon#enter sib2, iclass 31, count 2 2006.182.07:36:30.99#ibcon#flushed, iclass 31, count 2 2006.182.07:36:30.99#ibcon#about to write, iclass 31, count 2 2006.182.07:36:30.99#ibcon#wrote, iclass 31, count 2 2006.182.07:36:30.99#ibcon#about to read 3, iclass 31, count 2 2006.182.07:36:31.01#ibcon#read 3, iclass 31, count 2 2006.182.07:36:31.01#ibcon#about to read 4, iclass 31, count 2 2006.182.07:36:31.01#ibcon#read 4, iclass 31, count 2 2006.182.07:36:31.01#ibcon#about to read 5, iclass 31, count 2 2006.182.07:36:31.01#ibcon#read 5, iclass 31, count 2 2006.182.07:36:31.01#ibcon#about to read 6, iclass 31, count 2 2006.182.07:36:31.01#ibcon#read 6, iclass 31, count 2 2006.182.07:36:31.01#ibcon#end of sib2, iclass 31, count 2 2006.182.07:36:31.01#ibcon#*mode == 0, iclass 31, count 2 2006.182.07:36:31.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.182.07:36:31.01#ibcon#[27=AT02-04\r\n] 2006.182.07:36:31.01#ibcon#*before write, iclass 31, count 2 2006.182.07:36:31.01#ibcon#enter sib2, iclass 31, count 2 2006.182.07:36:31.01#ibcon#flushed, iclass 31, count 2 2006.182.07:36:31.01#ibcon#about to write, iclass 31, count 2 2006.182.07:36:31.01#ibcon#wrote, iclass 31, count 2 2006.182.07:36:31.01#ibcon#about to read 3, iclass 31, count 2 2006.182.07:36:31.04#ibcon#read 3, iclass 31, count 2 2006.182.07:36:31.04#ibcon#about to read 4, iclass 31, count 2 2006.182.07:36:31.04#ibcon#read 4, iclass 31, count 2 2006.182.07:36:31.04#ibcon#about to read 5, iclass 31, count 2 2006.182.07:36:31.04#ibcon#read 5, iclass 31, count 2 2006.182.07:36:31.04#ibcon#about to read 6, iclass 31, count 2 2006.182.07:36:31.04#ibcon#read 6, iclass 31, count 2 2006.182.07:36:31.04#ibcon#end of sib2, iclass 31, count 2 2006.182.07:36:31.04#ibcon#*after write, iclass 31, count 2 2006.182.07:36:31.04#ibcon#*before return 0, iclass 31, count 2 2006.182.07:36:31.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:36:31.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:36:31.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.182.07:36:31.04#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:31.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:36:31.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:36:31.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:36:31.16#ibcon#enter wrdev, iclass 31, count 0 2006.182.07:36:31.16#ibcon#first serial, iclass 31, count 0 2006.182.07:36:31.16#ibcon#enter sib2, iclass 31, count 0 2006.182.07:36:31.16#ibcon#flushed, iclass 31, count 0 2006.182.07:36:31.16#ibcon#about to write, iclass 31, count 0 2006.182.07:36:31.16#ibcon#wrote, iclass 31, count 0 2006.182.07:36:31.16#ibcon#about to read 3, iclass 31, count 0 2006.182.07:36:31.18#ibcon#read 3, iclass 31, count 0 2006.182.07:36:31.18#ibcon#about to read 4, iclass 31, count 0 2006.182.07:36:31.18#ibcon#read 4, iclass 31, count 0 2006.182.07:36:31.18#ibcon#about to read 5, iclass 31, count 0 2006.182.07:36:31.18#ibcon#read 5, iclass 31, count 0 2006.182.07:36:31.18#ibcon#about to read 6, iclass 31, count 0 2006.182.07:36:31.18#ibcon#read 6, iclass 31, count 0 2006.182.07:36:31.18#ibcon#end of sib2, iclass 31, count 0 2006.182.07:36:31.18#ibcon#*mode == 0, iclass 31, count 0 2006.182.07:36:31.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.07:36:31.18#ibcon#[27=USB\r\n] 2006.182.07:36:31.18#ibcon#*before write, iclass 31, count 0 2006.182.07:36:31.18#ibcon#enter sib2, iclass 31, count 0 2006.182.07:36:31.18#ibcon#flushed, iclass 31, count 0 2006.182.07:36:31.18#ibcon#about to write, iclass 31, count 0 2006.182.07:36:31.18#ibcon#wrote, iclass 31, count 0 2006.182.07:36:31.18#ibcon#about to read 3, iclass 31, count 0 2006.182.07:36:31.21#ibcon#read 3, iclass 31, count 0 2006.182.07:36:31.21#ibcon#about to read 4, iclass 31, count 0 2006.182.07:36:31.21#ibcon#read 4, iclass 31, count 0 2006.182.07:36:31.21#ibcon#about to read 5, iclass 31, count 0 2006.182.07:36:31.21#ibcon#read 5, iclass 31, count 0 2006.182.07:36:31.21#ibcon#about to read 6, iclass 31, count 0 2006.182.07:36:31.21#ibcon#read 6, iclass 31, count 0 2006.182.07:36:31.21#ibcon#end of sib2, iclass 31, count 0 2006.182.07:36:31.21#ibcon#*after write, iclass 31, count 0 2006.182.07:36:31.21#ibcon#*before return 0, iclass 31, count 0 2006.182.07:36:31.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:36:31.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:36:31.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.07:36:31.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.07:36:31.21$vc4f8/vblo=3,656.99 2006.182.07:36:31.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.182.07:36:31.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.182.07:36:31.21#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:31.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:36:31.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:36:31.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:36:31.21#ibcon#enter wrdev, iclass 33, count 0 2006.182.07:36:31.21#ibcon#first serial, iclass 33, count 0 2006.182.07:36:31.21#ibcon#enter sib2, iclass 33, count 0 2006.182.07:36:31.21#ibcon#flushed, iclass 33, count 0 2006.182.07:36:31.21#ibcon#about to write, iclass 33, count 0 2006.182.07:36:31.21#ibcon#wrote, iclass 33, count 0 2006.182.07:36:31.21#ibcon#about to read 3, iclass 33, count 0 2006.182.07:36:31.23#ibcon#read 3, iclass 33, count 0 2006.182.07:36:31.23#ibcon#about to read 4, iclass 33, count 0 2006.182.07:36:31.23#ibcon#read 4, iclass 33, count 0 2006.182.07:36:31.23#ibcon#about to read 5, iclass 33, count 0 2006.182.07:36:31.23#ibcon#read 5, iclass 33, count 0 2006.182.07:36:31.23#ibcon#about to read 6, iclass 33, count 0 2006.182.07:36:31.23#ibcon#read 6, iclass 33, count 0 2006.182.07:36:31.23#ibcon#end of sib2, iclass 33, count 0 2006.182.07:36:31.23#ibcon#*mode == 0, iclass 33, count 0 2006.182.07:36:31.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.07:36:31.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:36:31.23#ibcon#*before write, iclass 33, count 0 2006.182.07:36:31.23#ibcon#enter sib2, iclass 33, count 0 2006.182.07:36:31.23#ibcon#flushed, iclass 33, count 0 2006.182.07:36:31.23#ibcon#about to write, iclass 33, count 0 2006.182.07:36:31.23#ibcon#wrote, iclass 33, count 0 2006.182.07:36:31.23#ibcon#about to read 3, iclass 33, count 0 2006.182.07:36:31.27#ibcon#read 3, iclass 33, count 0 2006.182.07:36:31.27#ibcon#about to read 4, iclass 33, count 0 2006.182.07:36:31.27#ibcon#read 4, iclass 33, count 0 2006.182.07:36:31.27#ibcon#about to read 5, iclass 33, count 0 2006.182.07:36:31.27#ibcon#read 5, iclass 33, count 0 2006.182.07:36:31.27#ibcon#about to read 6, iclass 33, count 0 2006.182.07:36:31.27#ibcon#read 6, iclass 33, count 0 2006.182.07:36:31.27#ibcon#end of sib2, iclass 33, count 0 2006.182.07:36:31.27#ibcon#*after write, iclass 33, count 0 2006.182.07:36:31.27#ibcon#*before return 0, iclass 33, count 0 2006.182.07:36:31.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:36:31.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:36:31.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.07:36:31.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.07:36:31.27$vc4f8/vb=3,4 2006.182.07:36:31.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.182.07:36:31.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.182.07:36:31.27#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:31.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:36:31.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:36:31.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:36:31.33#ibcon#enter wrdev, iclass 35, count 2 2006.182.07:36:31.33#ibcon#first serial, iclass 35, count 2 2006.182.07:36:31.33#ibcon#enter sib2, iclass 35, count 2 2006.182.07:36:31.33#ibcon#flushed, iclass 35, count 2 2006.182.07:36:31.33#ibcon#about to write, iclass 35, count 2 2006.182.07:36:31.33#ibcon#wrote, iclass 35, count 2 2006.182.07:36:31.33#ibcon#about to read 3, iclass 35, count 2 2006.182.07:36:31.35#ibcon#read 3, iclass 35, count 2 2006.182.07:36:31.35#ibcon#about to read 4, iclass 35, count 2 2006.182.07:36:31.35#ibcon#read 4, iclass 35, count 2 2006.182.07:36:31.35#ibcon#about to read 5, iclass 35, count 2 2006.182.07:36:31.35#ibcon#read 5, iclass 35, count 2 2006.182.07:36:31.35#ibcon#about to read 6, iclass 35, count 2 2006.182.07:36:31.35#ibcon#read 6, iclass 35, count 2 2006.182.07:36:31.35#ibcon#end of sib2, iclass 35, count 2 2006.182.07:36:31.35#ibcon#*mode == 0, iclass 35, count 2 2006.182.07:36:31.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.182.07:36:31.35#ibcon#[27=AT03-04\r\n] 2006.182.07:36:31.35#ibcon#*before write, iclass 35, count 2 2006.182.07:36:31.35#ibcon#enter sib2, iclass 35, count 2 2006.182.07:36:31.35#ibcon#flushed, iclass 35, count 2 2006.182.07:36:31.35#ibcon#about to write, iclass 35, count 2 2006.182.07:36:31.35#ibcon#wrote, iclass 35, count 2 2006.182.07:36:31.35#ibcon#about to read 3, iclass 35, count 2 2006.182.07:36:31.38#ibcon#read 3, iclass 35, count 2 2006.182.07:36:31.38#ibcon#about to read 4, iclass 35, count 2 2006.182.07:36:31.38#ibcon#read 4, iclass 35, count 2 2006.182.07:36:31.38#ibcon#about to read 5, iclass 35, count 2 2006.182.07:36:31.38#ibcon#read 5, iclass 35, count 2 2006.182.07:36:31.38#ibcon#about to read 6, iclass 35, count 2 2006.182.07:36:31.38#ibcon#read 6, iclass 35, count 2 2006.182.07:36:31.38#ibcon#end of sib2, iclass 35, count 2 2006.182.07:36:31.38#ibcon#*after write, iclass 35, count 2 2006.182.07:36:31.38#ibcon#*before return 0, iclass 35, count 2 2006.182.07:36:31.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:36:31.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:36:31.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.182.07:36:31.38#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:31.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:36:31.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:36:31.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:36:31.50#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:36:31.50#ibcon#first serial, iclass 35, count 0 2006.182.07:36:31.50#ibcon#enter sib2, iclass 35, count 0 2006.182.07:36:31.50#ibcon#flushed, iclass 35, count 0 2006.182.07:36:31.50#ibcon#about to write, iclass 35, count 0 2006.182.07:36:31.50#ibcon#wrote, iclass 35, count 0 2006.182.07:36:31.50#ibcon#about to read 3, iclass 35, count 0 2006.182.07:36:31.52#ibcon#read 3, iclass 35, count 0 2006.182.07:36:31.52#ibcon#about to read 4, iclass 35, count 0 2006.182.07:36:31.52#ibcon#read 4, iclass 35, count 0 2006.182.07:36:31.52#ibcon#about to read 5, iclass 35, count 0 2006.182.07:36:31.52#ibcon#read 5, iclass 35, count 0 2006.182.07:36:31.52#ibcon#about to read 6, iclass 35, count 0 2006.182.07:36:31.52#ibcon#read 6, iclass 35, count 0 2006.182.07:36:31.52#ibcon#end of sib2, iclass 35, count 0 2006.182.07:36:31.52#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:36:31.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:36:31.52#ibcon#[27=USB\r\n] 2006.182.07:36:31.52#ibcon#*before write, iclass 35, count 0 2006.182.07:36:31.52#ibcon#enter sib2, iclass 35, count 0 2006.182.07:36:31.52#ibcon#flushed, iclass 35, count 0 2006.182.07:36:31.52#ibcon#about to write, iclass 35, count 0 2006.182.07:36:31.52#ibcon#wrote, iclass 35, count 0 2006.182.07:36:31.52#ibcon#about to read 3, iclass 35, count 0 2006.182.07:36:31.55#ibcon#read 3, iclass 35, count 0 2006.182.07:36:31.55#ibcon#about to read 4, iclass 35, count 0 2006.182.07:36:31.55#ibcon#read 4, iclass 35, count 0 2006.182.07:36:31.55#ibcon#about to read 5, iclass 35, count 0 2006.182.07:36:31.55#ibcon#read 5, iclass 35, count 0 2006.182.07:36:31.55#ibcon#about to read 6, iclass 35, count 0 2006.182.07:36:31.55#ibcon#read 6, iclass 35, count 0 2006.182.07:36:31.55#ibcon#end of sib2, iclass 35, count 0 2006.182.07:36:31.55#ibcon#*after write, iclass 35, count 0 2006.182.07:36:31.55#ibcon#*before return 0, iclass 35, count 0 2006.182.07:36:31.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:36:31.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:36:31.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:36:31.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:36:31.55$vc4f8/vblo=4,712.99 2006.182.07:36:31.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.182.07:36:31.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.182.07:36:31.55#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:31.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:31.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:31.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:31.55#ibcon#enter wrdev, iclass 37, count 0 2006.182.07:36:31.55#ibcon#first serial, iclass 37, count 0 2006.182.07:36:31.55#ibcon#enter sib2, iclass 37, count 0 2006.182.07:36:31.55#ibcon#flushed, iclass 37, count 0 2006.182.07:36:31.55#ibcon#about to write, iclass 37, count 0 2006.182.07:36:31.55#ibcon#wrote, iclass 37, count 0 2006.182.07:36:31.55#ibcon#about to read 3, iclass 37, count 0 2006.182.07:36:31.57#ibcon#read 3, iclass 37, count 0 2006.182.07:36:31.57#ibcon#about to read 4, iclass 37, count 0 2006.182.07:36:31.57#ibcon#read 4, iclass 37, count 0 2006.182.07:36:31.57#ibcon#about to read 5, iclass 37, count 0 2006.182.07:36:31.57#ibcon#read 5, iclass 37, count 0 2006.182.07:36:31.57#ibcon#about to read 6, iclass 37, count 0 2006.182.07:36:31.57#ibcon#read 6, iclass 37, count 0 2006.182.07:36:31.57#ibcon#end of sib2, iclass 37, count 0 2006.182.07:36:31.57#ibcon#*mode == 0, iclass 37, count 0 2006.182.07:36:31.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.07:36:31.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:36:31.57#ibcon#*before write, iclass 37, count 0 2006.182.07:36:31.57#ibcon#enter sib2, iclass 37, count 0 2006.182.07:36:31.57#ibcon#flushed, iclass 37, count 0 2006.182.07:36:31.57#ibcon#about to write, iclass 37, count 0 2006.182.07:36:31.57#ibcon#wrote, iclass 37, count 0 2006.182.07:36:31.57#ibcon#about to read 3, iclass 37, count 0 2006.182.07:36:31.61#ibcon#read 3, iclass 37, count 0 2006.182.07:36:31.61#ibcon#about to read 4, iclass 37, count 0 2006.182.07:36:31.61#ibcon#read 4, iclass 37, count 0 2006.182.07:36:31.61#ibcon#about to read 5, iclass 37, count 0 2006.182.07:36:31.61#ibcon#read 5, iclass 37, count 0 2006.182.07:36:31.61#ibcon#about to read 6, iclass 37, count 0 2006.182.07:36:31.61#ibcon#read 6, iclass 37, count 0 2006.182.07:36:31.61#ibcon#end of sib2, iclass 37, count 0 2006.182.07:36:31.61#ibcon#*after write, iclass 37, count 0 2006.182.07:36:31.61#ibcon#*before return 0, iclass 37, count 0 2006.182.07:36:31.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:31.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:36:31.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.07:36:31.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.07:36:31.61$vc4f8/vb=4,4 2006.182.07:36:31.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.07:36:31.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.07:36:31.61#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:31.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:31.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:31.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:31.67#ibcon#enter wrdev, iclass 39, count 2 2006.182.07:36:31.67#ibcon#first serial, iclass 39, count 2 2006.182.07:36:31.67#ibcon#enter sib2, iclass 39, count 2 2006.182.07:36:31.67#ibcon#flushed, iclass 39, count 2 2006.182.07:36:31.67#ibcon#about to write, iclass 39, count 2 2006.182.07:36:31.67#ibcon#wrote, iclass 39, count 2 2006.182.07:36:31.67#ibcon#about to read 3, iclass 39, count 2 2006.182.07:36:31.69#ibcon#read 3, iclass 39, count 2 2006.182.07:36:31.69#ibcon#about to read 4, iclass 39, count 2 2006.182.07:36:31.69#ibcon#read 4, iclass 39, count 2 2006.182.07:36:31.69#ibcon#about to read 5, iclass 39, count 2 2006.182.07:36:31.69#ibcon#read 5, iclass 39, count 2 2006.182.07:36:31.69#ibcon#about to read 6, iclass 39, count 2 2006.182.07:36:31.69#ibcon#read 6, iclass 39, count 2 2006.182.07:36:31.69#ibcon#end of sib2, iclass 39, count 2 2006.182.07:36:31.69#ibcon#*mode == 0, iclass 39, count 2 2006.182.07:36:31.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.07:36:31.69#ibcon#[27=AT04-04\r\n] 2006.182.07:36:31.69#ibcon#*before write, iclass 39, count 2 2006.182.07:36:31.69#ibcon#enter sib2, iclass 39, count 2 2006.182.07:36:31.69#ibcon#flushed, iclass 39, count 2 2006.182.07:36:31.69#ibcon#about to write, iclass 39, count 2 2006.182.07:36:31.69#ibcon#wrote, iclass 39, count 2 2006.182.07:36:31.69#ibcon#about to read 3, iclass 39, count 2 2006.182.07:36:31.72#ibcon#read 3, iclass 39, count 2 2006.182.07:36:31.72#ibcon#about to read 4, iclass 39, count 2 2006.182.07:36:31.72#ibcon#read 4, iclass 39, count 2 2006.182.07:36:31.72#ibcon#about to read 5, iclass 39, count 2 2006.182.07:36:31.72#ibcon#read 5, iclass 39, count 2 2006.182.07:36:31.72#ibcon#about to read 6, iclass 39, count 2 2006.182.07:36:31.72#ibcon#read 6, iclass 39, count 2 2006.182.07:36:31.72#ibcon#end of sib2, iclass 39, count 2 2006.182.07:36:31.72#ibcon#*after write, iclass 39, count 2 2006.182.07:36:31.72#ibcon#*before return 0, iclass 39, count 2 2006.182.07:36:31.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:31.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:36:31.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.07:36:31.72#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:31.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:31.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:31.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:31.84#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:36:31.84#ibcon#first serial, iclass 39, count 0 2006.182.07:36:31.84#ibcon#enter sib2, iclass 39, count 0 2006.182.07:36:31.84#ibcon#flushed, iclass 39, count 0 2006.182.07:36:31.84#ibcon#about to write, iclass 39, count 0 2006.182.07:36:31.84#ibcon#wrote, iclass 39, count 0 2006.182.07:36:31.84#ibcon#about to read 3, iclass 39, count 0 2006.182.07:36:31.86#ibcon#read 3, iclass 39, count 0 2006.182.07:36:31.86#ibcon#about to read 4, iclass 39, count 0 2006.182.07:36:31.86#ibcon#read 4, iclass 39, count 0 2006.182.07:36:31.86#ibcon#about to read 5, iclass 39, count 0 2006.182.07:36:31.86#ibcon#read 5, iclass 39, count 0 2006.182.07:36:31.86#ibcon#about to read 6, iclass 39, count 0 2006.182.07:36:31.86#ibcon#read 6, iclass 39, count 0 2006.182.07:36:31.86#ibcon#end of sib2, iclass 39, count 0 2006.182.07:36:31.86#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:36:31.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:36:31.86#ibcon#[27=USB\r\n] 2006.182.07:36:31.86#ibcon#*before write, iclass 39, count 0 2006.182.07:36:31.86#ibcon#enter sib2, iclass 39, count 0 2006.182.07:36:31.86#ibcon#flushed, iclass 39, count 0 2006.182.07:36:31.86#ibcon#about to write, iclass 39, count 0 2006.182.07:36:31.86#ibcon#wrote, iclass 39, count 0 2006.182.07:36:31.86#ibcon#about to read 3, iclass 39, count 0 2006.182.07:36:31.89#ibcon#read 3, iclass 39, count 0 2006.182.07:36:31.89#ibcon#about to read 4, iclass 39, count 0 2006.182.07:36:31.89#ibcon#read 4, iclass 39, count 0 2006.182.07:36:31.89#ibcon#about to read 5, iclass 39, count 0 2006.182.07:36:31.89#ibcon#read 5, iclass 39, count 0 2006.182.07:36:31.89#ibcon#about to read 6, iclass 39, count 0 2006.182.07:36:31.89#ibcon#read 6, iclass 39, count 0 2006.182.07:36:31.89#ibcon#end of sib2, iclass 39, count 0 2006.182.07:36:31.89#ibcon#*after write, iclass 39, count 0 2006.182.07:36:31.89#ibcon#*before return 0, iclass 39, count 0 2006.182.07:36:31.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:31.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:36:31.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:36:31.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:36:31.89$vc4f8/vblo=5,744.99 2006.182.07:36:31.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.07:36:31.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.07:36:31.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:31.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:31.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:31.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:31.89#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:36:31.89#ibcon#first serial, iclass 3, count 0 2006.182.07:36:31.89#ibcon#enter sib2, iclass 3, count 0 2006.182.07:36:31.89#ibcon#flushed, iclass 3, count 0 2006.182.07:36:31.89#ibcon#about to write, iclass 3, count 0 2006.182.07:36:31.89#ibcon#wrote, iclass 3, count 0 2006.182.07:36:31.89#ibcon#about to read 3, iclass 3, count 0 2006.182.07:36:31.92#ibcon#read 3, iclass 3, count 0 2006.182.07:36:31.92#ibcon#about to read 4, iclass 3, count 0 2006.182.07:36:31.92#ibcon#read 4, iclass 3, count 0 2006.182.07:36:31.92#ibcon#about to read 5, iclass 3, count 0 2006.182.07:36:31.92#ibcon#read 5, iclass 3, count 0 2006.182.07:36:31.92#ibcon#about to read 6, iclass 3, count 0 2006.182.07:36:31.92#ibcon#read 6, iclass 3, count 0 2006.182.07:36:31.92#ibcon#end of sib2, iclass 3, count 0 2006.182.07:36:31.92#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:36:31.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:36:31.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:36:31.92#ibcon#*before write, iclass 3, count 0 2006.182.07:36:31.92#ibcon#enter sib2, iclass 3, count 0 2006.182.07:36:31.92#ibcon#flushed, iclass 3, count 0 2006.182.07:36:31.92#ibcon#about to write, iclass 3, count 0 2006.182.07:36:31.92#ibcon#wrote, iclass 3, count 0 2006.182.07:36:31.92#ibcon#about to read 3, iclass 3, count 0 2006.182.07:36:31.96#ibcon#read 3, iclass 3, count 0 2006.182.07:36:31.96#ibcon#about to read 4, iclass 3, count 0 2006.182.07:36:31.96#ibcon#read 4, iclass 3, count 0 2006.182.07:36:31.96#ibcon#about to read 5, iclass 3, count 0 2006.182.07:36:31.96#ibcon#read 5, iclass 3, count 0 2006.182.07:36:31.96#ibcon#about to read 6, iclass 3, count 0 2006.182.07:36:31.96#ibcon#read 6, iclass 3, count 0 2006.182.07:36:31.96#ibcon#end of sib2, iclass 3, count 0 2006.182.07:36:31.96#ibcon#*after write, iclass 3, count 0 2006.182.07:36:31.96#ibcon#*before return 0, iclass 3, count 0 2006.182.07:36:31.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:31.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:36:31.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:36:31.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:36:31.96$vc4f8/vb=5,4 2006.182.07:36:31.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.07:36:31.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.07:36:31.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:31.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:32.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:32.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:32.01#ibcon#enter wrdev, iclass 5, count 2 2006.182.07:36:32.01#ibcon#first serial, iclass 5, count 2 2006.182.07:36:32.01#ibcon#enter sib2, iclass 5, count 2 2006.182.07:36:32.01#ibcon#flushed, iclass 5, count 2 2006.182.07:36:32.01#ibcon#about to write, iclass 5, count 2 2006.182.07:36:32.01#ibcon#wrote, iclass 5, count 2 2006.182.07:36:32.01#ibcon#about to read 3, iclass 5, count 2 2006.182.07:36:32.03#ibcon#read 3, iclass 5, count 2 2006.182.07:36:32.03#ibcon#about to read 4, iclass 5, count 2 2006.182.07:36:32.03#ibcon#read 4, iclass 5, count 2 2006.182.07:36:32.03#ibcon#about to read 5, iclass 5, count 2 2006.182.07:36:32.03#ibcon#read 5, iclass 5, count 2 2006.182.07:36:32.03#ibcon#about to read 6, iclass 5, count 2 2006.182.07:36:32.03#ibcon#read 6, iclass 5, count 2 2006.182.07:36:32.03#ibcon#end of sib2, iclass 5, count 2 2006.182.07:36:32.03#ibcon#*mode == 0, iclass 5, count 2 2006.182.07:36:32.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.07:36:32.03#ibcon#[27=AT05-04\r\n] 2006.182.07:36:32.03#ibcon#*before write, iclass 5, count 2 2006.182.07:36:32.03#ibcon#enter sib2, iclass 5, count 2 2006.182.07:36:32.03#ibcon#flushed, iclass 5, count 2 2006.182.07:36:32.03#ibcon#about to write, iclass 5, count 2 2006.182.07:36:32.03#ibcon#wrote, iclass 5, count 2 2006.182.07:36:32.03#ibcon#about to read 3, iclass 5, count 2 2006.182.07:36:32.06#ibcon#read 3, iclass 5, count 2 2006.182.07:36:32.06#ibcon#about to read 4, iclass 5, count 2 2006.182.07:36:32.06#ibcon#read 4, iclass 5, count 2 2006.182.07:36:32.06#ibcon#about to read 5, iclass 5, count 2 2006.182.07:36:32.06#ibcon#read 5, iclass 5, count 2 2006.182.07:36:32.06#ibcon#about to read 6, iclass 5, count 2 2006.182.07:36:32.06#ibcon#read 6, iclass 5, count 2 2006.182.07:36:32.06#ibcon#end of sib2, iclass 5, count 2 2006.182.07:36:32.06#ibcon#*after write, iclass 5, count 2 2006.182.07:36:32.06#ibcon#*before return 0, iclass 5, count 2 2006.182.07:36:32.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:32.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:36:32.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.07:36:32.06#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:32.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:32.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:32.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:32.18#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:36:32.18#ibcon#first serial, iclass 5, count 0 2006.182.07:36:32.18#ibcon#enter sib2, iclass 5, count 0 2006.182.07:36:32.18#ibcon#flushed, iclass 5, count 0 2006.182.07:36:32.18#ibcon#about to write, iclass 5, count 0 2006.182.07:36:32.18#ibcon#wrote, iclass 5, count 0 2006.182.07:36:32.18#ibcon#about to read 3, iclass 5, count 0 2006.182.07:36:32.20#ibcon#read 3, iclass 5, count 0 2006.182.07:36:32.20#ibcon#about to read 4, iclass 5, count 0 2006.182.07:36:32.20#ibcon#read 4, iclass 5, count 0 2006.182.07:36:32.20#ibcon#about to read 5, iclass 5, count 0 2006.182.07:36:32.20#ibcon#read 5, iclass 5, count 0 2006.182.07:36:32.20#ibcon#about to read 6, iclass 5, count 0 2006.182.07:36:32.20#ibcon#read 6, iclass 5, count 0 2006.182.07:36:32.20#ibcon#end of sib2, iclass 5, count 0 2006.182.07:36:32.20#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:36:32.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:36:32.20#ibcon#[27=USB\r\n] 2006.182.07:36:32.20#ibcon#*before write, iclass 5, count 0 2006.182.07:36:32.20#ibcon#enter sib2, iclass 5, count 0 2006.182.07:36:32.20#ibcon#flushed, iclass 5, count 0 2006.182.07:36:32.20#ibcon#about to write, iclass 5, count 0 2006.182.07:36:32.20#ibcon#wrote, iclass 5, count 0 2006.182.07:36:32.20#ibcon#about to read 3, iclass 5, count 0 2006.182.07:36:32.23#ibcon#read 3, iclass 5, count 0 2006.182.07:36:32.23#ibcon#about to read 4, iclass 5, count 0 2006.182.07:36:32.23#ibcon#read 4, iclass 5, count 0 2006.182.07:36:32.23#ibcon#about to read 5, iclass 5, count 0 2006.182.07:36:32.23#ibcon#read 5, iclass 5, count 0 2006.182.07:36:32.23#ibcon#about to read 6, iclass 5, count 0 2006.182.07:36:32.23#ibcon#read 6, iclass 5, count 0 2006.182.07:36:32.23#ibcon#end of sib2, iclass 5, count 0 2006.182.07:36:32.23#ibcon#*after write, iclass 5, count 0 2006.182.07:36:32.23#ibcon#*before return 0, iclass 5, count 0 2006.182.07:36:32.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:32.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:36:32.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:36:32.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:36:32.23$vc4f8/vblo=6,752.99 2006.182.07:36:32.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.07:36:32.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.07:36:32.23#ibcon#ireg 17 cls_cnt 0 2006.182.07:36:32.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:32.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:32.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:32.23#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:36:32.23#ibcon#first serial, iclass 7, count 0 2006.182.07:36:32.23#ibcon#enter sib2, iclass 7, count 0 2006.182.07:36:32.23#ibcon#flushed, iclass 7, count 0 2006.182.07:36:32.23#ibcon#about to write, iclass 7, count 0 2006.182.07:36:32.23#ibcon#wrote, iclass 7, count 0 2006.182.07:36:32.23#ibcon#about to read 3, iclass 7, count 0 2006.182.07:36:32.25#ibcon#read 3, iclass 7, count 0 2006.182.07:36:32.25#ibcon#about to read 4, iclass 7, count 0 2006.182.07:36:32.25#ibcon#read 4, iclass 7, count 0 2006.182.07:36:32.25#ibcon#about to read 5, iclass 7, count 0 2006.182.07:36:32.25#ibcon#read 5, iclass 7, count 0 2006.182.07:36:32.25#ibcon#about to read 6, iclass 7, count 0 2006.182.07:36:32.25#ibcon#read 6, iclass 7, count 0 2006.182.07:36:32.25#ibcon#end of sib2, iclass 7, count 0 2006.182.07:36:32.25#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:36:32.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:36:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:36:32.25#ibcon#*before write, iclass 7, count 0 2006.182.07:36:32.25#ibcon#enter sib2, iclass 7, count 0 2006.182.07:36:32.25#ibcon#flushed, iclass 7, count 0 2006.182.07:36:32.25#ibcon#about to write, iclass 7, count 0 2006.182.07:36:32.25#ibcon#wrote, iclass 7, count 0 2006.182.07:36:32.25#ibcon#about to read 3, iclass 7, count 0 2006.182.07:36:32.29#ibcon#read 3, iclass 7, count 0 2006.182.07:36:32.29#ibcon#about to read 4, iclass 7, count 0 2006.182.07:36:32.29#ibcon#read 4, iclass 7, count 0 2006.182.07:36:32.29#ibcon#about to read 5, iclass 7, count 0 2006.182.07:36:32.29#ibcon#read 5, iclass 7, count 0 2006.182.07:36:32.29#ibcon#about to read 6, iclass 7, count 0 2006.182.07:36:32.29#ibcon#read 6, iclass 7, count 0 2006.182.07:36:32.29#ibcon#end of sib2, iclass 7, count 0 2006.182.07:36:32.29#ibcon#*after write, iclass 7, count 0 2006.182.07:36:32.29#ibcon#*before return 0, iclass 7, count 0 2006.182.07:36:32.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:32.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:36:32.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:36:32.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:36:32.29$vc4f8/vb=6,4 2006.182.07:36:32.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.07:36:32.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.07:36:32.29#ibcon#ireg 11 cls_cnt 2 2006.182.07:36:32.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:32.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:32.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:32.35#ibcon#enter wrdev, iclass 11, count 2 2006.182.07:36:32.35#ibcon#first serial, iclass 11, count 2 2006.182.07:36:32.35#ibcon#enter sib2, iclass 11, count 2 2006.182.07:36:32.35#ibcon#flushed, iclass 11, count 2 2006.182.07:36:32.35#ibcon#about to write, iclass 11, count 2 2006.182.07:36:32.35#ibcon#wrote, iclass 11, count 2 2006.182.07:36:32.35#ibcon#about to read 3, iclass 11, count 2 2006.182.07:36:32.37#ibcon#read 3, iclass 11, count 2 2006.182.07:36:32.37#ibcon#about to read 4, iclass 11, count 2 2006.182.07:36:32.37#ibcon#read 4, iclass 11, count 2 2006.182.07:36:32.37#ibcon#about to read 5, iclass 11, count 2 2006.182.07:36:32.37#ibcon#read 5, iclass 11, count 2 2006.182.07:36:32.37#ibcon#about to read 6, iclass 11, count 2 2006.182.07:36:32.37#ibcon#read 6, iclass 11, count 2 2006.182.07:36:32.37#ibcon#end of sib2, iclass 11, count 2 2006.182.07:36:32.37#ibcon#*mode == 0, iclass 11, count 2 2006.182.07:36:32.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.07:36:32.37#ibcon#[27=AT06-04\r\n] 2006.182.07:36:32.37#ibcon#*before write, iclass 11, count 2 2006.182.07:36:32.37#ibcon#enter sib2, iclass 11, count 2 2006.182.07:36:32.37#ibcon#flushed, iclass 11, count 2 2006.182.07:36:32.37#ibcon#about to write, iclass 11, count 2 2006.182.07:36:32.37#ibcon#wrote, iclass 11, count 2 2006.182.07:36:32.37#ibcon#about to read 3, iclass 11, count 2 2006.182.07:36:32.40#ibcon#read 3, iclass 11, count 2 2006.182.07:36:32.40#ibcon#about to read 4, iclass 11, count 2 2006.182.07:36:32.40#ibcon#read 4, iclass 11, count 2 2006.182.07:36:32.40#ibcon#about to read 5, iclass 11, count 2 2006.182.07:36:32.40#ibcon#read 5, iclass 11, count 2 2006.182.07:36:32.40#ibcon#about to read 6, iclass 11, count 2 2006.182.07:36:32.40#ibcon#read 6, iclass 11, count 2 2006.182.07:36:32.40#ibcon#end of sib2, iclass 11, count 2 2006.182.07:36:32.40#ibcon#*after write, iclass 11, count 2 2006.182.07:36:32.40#ibcon#*before return 0, iclass 11, count 2 2006.182.07:36:32.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:32.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:36:32.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.07:36:32.40#ibcon#ireg 7 cls_cnt 0 2006.182.07:36:32.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:32.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:32.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:32.52#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:36:32.52#ibcon#first serial, iclass 11, count 0 2006.182.07:36:32.52#ibcon#enter sib2, iclass 11, count 0 2006.182.07:36:32.52#ibcon#flushed, iclass 11, count 0 2006.182.07:36:32.52#ibcon#about to write, iclass 11, count 0 2006.182.07:36:32.52#ibcon#wrote, iclass 11, count 0 2006.182.07:36:32.52#ibcon#about to read 3, iclass 11, count 0 2006.182.07:36:32.54#ibcon#read 3, iclass 11, count 0 2006.182.07:36:32.54#ibcon#about to read 4, iclass 11, count 0 2006.182.07:36:32.54#ibcon#read 4, iclass 11, count 0 2006.182.07:36:32.54#ibcon#about to read 5, iclass 11, count 0 2006.182.07:36:32.54#ibcon#read 5, iclass 11, count 0 2006.182.07:36:32.54#ibcon#about to read 6, iclass 11, count 0 2006.182.07:36:32.54#ibcon#read 6, iclass 11, count 0 2006.182.07:36:32.54#ibcon#end of sib2, iclass 11, count 0 2006.182.07:36:32.54#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:36:32.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:36:32.54#ibcon#[27=USB\r\n] 2006.182.07:36:32.54#ibcon#*before write, iclass 11, count 0 2006.182.07:36:32.54#ibcon#enter sib2, iclass 11, count 0 2006.182.07:36:32.54#ibcon#flushed, iclass 11, count 0 2006.182.07:36:32.54#ibcon#about to write, iclass 11, count 0 2006.182.07:36:32.54#ibcon#wrote, iclass 11, count 0 2006.182.07:36:32.54#ibcon#about to read 3, iclass 11, count 0 2006.182.07:36:32.57#ibcon#read 3, iclass 11, count 0 2006.182.07:36:32.57#ibcon#about to read 4, iclass 11, count 0 2006.182.07:36:32.57#ibcon#read 4, iclass 11, count 0 2006.182.07:36:32.57#ibcon#about to read 5, iclass 11, count 0 2006.182.07:36:32.57#ibcon#read 5, iclass 11, count 0 2006.182.07:36:32.57#ibcon#about to read 6, iclass 11, count 0 2006.182.07:36:32.57#ibcon#read 6, iclass 11, count 0 2006.182.07:36:32.57#ibcon#end of sib2, iclass 11, count 0 2006.182.07:36:32.57#ibcon#*after write, iclass 11, count 0 2006.182.07:36:32.57#ibcon#*before return 0, iclass 11, count 0 2006.182.07:36:32.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:32.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:36:32.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:36:32.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:36:32.57$vc4f8/vabw=wide 2006.182.07:36:32.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.07:36:32.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.07:36:32.57#ibcon#ireg 8 cls_cnt 0 2006.182.07:36:32.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:32.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:32.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:32.57#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:36:32.57#ibcon#first serial, iclass 13, count 0 2006.182.07:36:32.57#ibcon#enter sib2, iclass 13, count 0 2006.182.07:36:32.57#ibcon#flushed, iclass 13, count 0 2006.182.07:36:32.57#ibcon#about to write, iclass 13, count 0 2006.182.07:36:32.57#ibcon#wrote, iclass 13, count 0 2006.182.07:36:32.57#ibcon#about to read 3, iclass 13, count 0 2006.182.07:36:32.59#ibcon#read 3, iclass 13, count 0 2006.182.07:36:32.59#ibcon#about to read 4, iclass 13, count 0 2006.182.07:36:32.59#ibcon#read 4, iclass 13, count 0 2006.182.07:36:32.59#ibcon#about to read 5, iclass 13, count 0 2006.182.07:36:32.59#ibcon#read 5, iclass 13, count 0 2006.182.07:36:32.59#ibcon#about to read 6, iclass 13, count 0 2006.182.07:36:32.59#ibcon#read 6, iclass 13, count 0 2006.182.07:36:32.59#ibcon#end of sib2, iclass 13, count 0 2006.182.07:36:32.59#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:36:32.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:36:32.59#ibcon#[25=BW32\r\n] 2006.182.07:36:32.59#ibcon#*before write, iclass 13, count 0 2006.182.07:36:32.59#ibcon#enter sib2, iclass 13, count 0 2006.182.07:36:32.59#ibcon#flushed, iclass 13, count 0 2006.182.07:36:32.59#ibcon#about to write, iclass 13, count 0 2006.182.07:36:32.59#ibcon#wrote, iclass 13, count 0 2006.182.07:36:32.59#ibcon#about to read 3, iclass 13, count 0 2006.182.07:36:32.62#ibcon#read 3, iclass 13, count 0 2006.182.07:36:32.62#ibcon#about to read 4, iclass 13, count 0 2006.182.07:36:32.62#ibcon#read 4, iclass 13, count 0 2006.182.07:36:32.62#ibcon#about to read 5, iclass 13, count 0 2006.182.07:36:32.62#ibcon#read 5, iclass 13, count 0 2006.182.07:36:32.62#ibcon#about to read 6, iclass 13, count 0 2006.182.07:36:32.62#ibcon#read 6, iclass 13, count 0 2006.182.07:36:32.62#ibcon#end of sib2, iclass 13, count 0 2006.182.07:36:32.62#ibcon#*after write, iclass 13, count 0 2006.182.07:36:32.62#ibcon#*before return 0, iclass 13, count 0 2006.182.07:36:32.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:32.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:36:32.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:36:32.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:36:32.62$vc4f8/vbbw=wide 2006.182.07:36:32.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.07:36:32.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.07:36:32.62#ibcon#ireg 8 cls_cnt 0 2006.182.07:36:32.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:36:32.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:36:32.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:36:32.69#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:36:32.69#ibcon#first serial, iclass 15, count 0 2006.182.07:36:32.69#ibcon#enter sib2, iclass 15, count 0 2006.182.07:36:32.69#ibcon#flushed, iclass 15, count 0 2006.182.07:36:32.69#ibcon#about to write, iclass 15, count 0 2006.182.07:36:32.69#ibcon#wrote, iclass 15, count 0 2006.182.07:36:32.69#ibcon#about to read 3, iclass 15, count 0 2006.182.07:36:32.71#ibcon#read 3, iclass 15, count 0 2006.182.07:36:32.71#ibcon#about to read 4, iclass 15, count 0 2006.182.07:36:32.71#ibcon#read 4, iclass 15, count 0 2006.182.07:36:32.71#ibcon#about to read 5, iclass 15, count 0 2006.182.07:36:32.71#ibcon#read 5, iclass 15, count 0 2006.182.07:36:32.71#ibcon#about to read 6, iclass 15, count 0 2006.182.07:36:32.71#ibcon#read 6, iclass 15, count 0 2006.182.07:36:32.71#ibcon#end of sib2, iclass 15, count 0 2006.182.07:36:32.71#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:36:32.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:36:32.71#ibcon#[27=BW32\r\n] 2006.182.07:36:32.71#ibcon#*before write, iclass 15, count 0 2006.182.07:36:32.71#ibcon#enter sib2, iclass 15, count 0 2006.182.07:36:32.71#ibcon#flushed, iclass 15, count 0 2006.182.07:36:32.71#ibcon#about to write, iclass 15, count 0 2006.182.07:36:32.71#ibcon#wrote, iclass 15, count 0 2006.182.07:36:32.71#ibcon#about to read 3, iclass 15, count 0 2006.182.07:36:32.74#ibcon#read 3, iclass 15, count 0 2006.182.07:36:32.74#ibcon#about to read 4, iclass 15, count 0 2006.182.07:36:32.74#ibcon#read 4, iclass 15, count 0 2006.182.07:36:32.74#ibcon#about to read 5, iclass 15, count 0 2006.182.07:36:32.74#ibcon#read 5, iclass 15, count 0 2006.182.07:36:32.74#ibcon#about to read 6, iclass 15, count 0 2006.182.07:36:32.74#ibcon#read 6, iclass 15, count 0 2006.182.07:36:32.74#ibcon#end of sib2, iclass 15, count 0 2006.182.07:36:32.74#ibcon#*after write, iclass 15, count 0 2006.182.07:36:32.74#ibcon#*before return 0, iclass 15, count 0 2006.182.07:36:32.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:36:32.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:36:32.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:36:32.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:36:32.74$4f8m12a/ifd4f 2006.182.07:36:32.74$ifd4f/lo= 2006.182.07:36:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:36:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:36:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:36:32.74$ifd4f/patch= 2006.182.07:36:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:36:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:36:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:36:32.74$4f8m12a/"form=m,16.000,1:2 2006.182.07:36:32.74$4f8m12a/"tpicd 2006.182.07:36:32.74$4f8m12a/echo=off 2006.182.07:36:32.74$4f8m12a/xlog=off 2006.182.07:36:32.74:!2006.182.07:37:00 2006.182.07:36:47.14#trakl#Source acquired 2006.182.07:36:48.14#flagr#flagr/antenna,acquired 2006.182.07:37:00.00:preob 2006.182.07:37:01.13/onsource/TRACKING 2006.182.07:37:01.13:!2006.182.07:37:10 2006.182.07:37:10.00:data_valid=on 2006.182.07:37:10.00:midob 2006.182.07:37:10.13/onsource/TRACKING 2006.182.07:37:10.13/wx/27.45,1002.9,82 2006.182.07:37:10.21/cable/+6.4678E-03 2006.182.07:37:11.30/va/01,08,usb,yes,30,32 2006.182.07:37:11.30/va/02,07,usb,yes,30,32 2006.182.07:37:11.30/va/03,06,usb,yes,32,32 2006.182.07:37:11.30/va/04,07,usb,yes,31,33 2006.182.07:37:11.30/va/05,07,usb,yes,32,34 2006.182.07:37:11.30/va/06,06,usb,yes,31,31 2006.182.07:37:11.30/va/07,06,usb,yes,32,32 2006.182.07:37:11.30/va/08,07,usb,yes,30,30 2006.182.07:37:11.53/valo/01,532.99,yes,locked 2006.182.07:37:11.53/valo/02,572.99,yes,locked 2006.182.07:37:11.53/valo/03,672.99,yes,locked 2006.182.07:37:11.53/valo/04,832.99,yes,locked 2006.182.07:37:11.53/valo/05,652.99,yes,locked 2006.182.07:37:11.53/valo/06,772.99,yes,locked 2006.182.07:37:11.53/valo/07,832.99,yes,locked 2006.182.07:37:11.53/valo/08,852.99,yes,locked 2006.182.07:37:12.62/vb/01,04,usb,yes,30,29 2006.182.07:37:12.62/vb/02,04,usb,yes,32,33 2006.182.07:37:12.62/vb/03,04,usb,yes,28,32 2006.182.07:37:12.62/vb/04,04,usb,yes,29,29 2006.182.07:37:12.62/vb/05,04,usb,yes,28,31 2006.182.07:37:12.62/vb/06,04,usb,yes,28,31 2006.182.07:37:12.62/vb/07,04,usb,yes,31,30 2006.182.07:37:12.62/vb/08,04,usb,yes,28,31 2006.182.07:37:12.85/vblo/01,632.99,yes,locked 2006.182.07:37:12.85/vblo/02,640.99,yes,locked 2006.182.07:37:12.85/vblo/03,656.99,yes,locked 2006.182.07:37:12.85/vblo/04,712.99,yes,locked 2006.182.07:37:12.85/vblo/05,744.99,yes,locked 2006.182.07:37:12.85/vblo/06,752.99,yes,locked 2006.182.07:37:12.85/vblo/07,734.99,yes,locked 2006.182.07:37:12.85/vblo/08,744.99,yes,locked 2006.182.07:37:13.00/vabw/8 2006.182.07:37:13.15/vbbw/8 2006.182.07:37:13.26/xfe/off,on,14.5 2006.182.07:37:13.63/ifatt/23,28,28,28 2006.182.07:37:14.07/fmout-gps/S +3.36E-07 2006.182.07:37:14.15:!2006.182.07:38:10 2006.182.07:38:10.00:data_valid=off 2006.182.07:38:10.00:postob 2006.182.07:38:10.16/cable/+6.4643E-03 2006.182.07:38:10.16/wx/27.46,1002.9,81 2006.182.07:38:11.08/fmout-gps/S +3.37E-07 2006.182.07:38:11.08:scan_name=182-0739,k06182,60 2006.182.07:38:11.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.182.07:38:11.13#flagr#flagr/antenna,new-source 2006.182.07:38:12.13:checkk5 2006.182.07:38:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:38:12.87/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:38:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:38:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:38:13.99/chk_obsdata//k5ts1/T1820737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:38:14.36/chk_obsdata//k5ts2/T1820737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:38:14.73/chk_obsdata//k5ts3/T1820737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:38:15.10/chk_obsdata//k5ts4/T1820737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:38:15.78/k5log//k5ts1_log_newline 2006.182.07:38:16.48/k5log//k5ts2_log_newline 2006.182.07:38:17.17/k5log//k5ts3_log_newline 2006.182.07:38:17.86/k5log//k5ts4_log_newline 2006.182.07:38:17.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:38:17.89:4f8m12a=1 2006.182.07:38:17.89$4f8m12a/echo=on 2006.182.07:38:17.89$4f8m12a/pcalon 2006.182.07:38:17.89$pcalon/"no phase cal control is implemented here 2006.182.07:38:17.89$4f8m12a/"tpicd=stop 2006.182.07:38:17.89$4f8m12a/vc4f8 2006.182.07:38:17.89$vc4f8/valo=1,532.99 2006.182.07:38:17.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.07:38:17.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.07:38:17.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:17.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:17.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:17.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:17.89#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:38:17.89#ibcon#first serial, iclass 22, count 0 2006.182.07:38:17.89#ibcon#enter sib2, iclass 22, count 0 2006.182.07:38:17.89#ibcon#flushed, iclass 22, count 0 2006.182.07:38:17.89#ibcon#about to write, iclass 22, count 0 2006.182.07:38:17.89#ibcon#wrote, iclass 22, count 0 2006.182.07:38:17.89#ibcon#about to read 3, iclass 22, count 0 2006.182.07:38:17.93#ibcon#read 3, iclass 22, count 0 2006.182.07:38:17.93#ibcon#about to read 4, iclass 22, count 0 2006.182.07:38:17.93#ibcon#read 4, iclass 22, count 0 2006.182.07:38:17.93#ibcon#about to read 5, iclass 22, count 0 2006.182.07:38:17.93#ibcon#read 5, iclass 22, count 0 2006.182.07:38:17.93#ibcon#about to read 6, iclass 22, count 0 2006.182.07:38:17.93#ibcon#read 6, iclass 22, count 0 2006.182.07:38:17.93#ibcon#end of sib2, iclass 22, count 0 2006.182.07:38:17.93#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:38:17.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:38:17.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:38:17.93#ibcon#*before write, iclass 22, count 0 2006.182.07:38:17.93#ibcon#enter sib2, iclass 22, count 0 2006.182.07:38:17.93#ibcon#flushed, iclass 22, count 0 2006.182.07:38:17.93#ibcon#about to write, iclass 22, count 0 2006.182.07:38:17.93#ibcon#wrote, iclass 22, count 0 2006.182.07:38:17.93#ibcon#about to read 3, iclass 22, count 0 2006.182.07:38:17.98#ibcon#read 3, iclass 22, count 0 2006.182.07:38:17.98#ibcon#about to read 4, iclass 22, count 0 2006.182.07:38:17.98#ibcon#read 4, iclass 22, count 0 2006.182.07:38:17.98#ibcon#about to read 5, iclass 22, count 0 2006.182.07:38:17.98#ibcon#read 5, iclass 22, count 0 2006.182.07:38:17.98#ibcon#about to read 6, iclass 22, count 0 2006.182.07:38:17.98#ibcon#read 6, iclass 22, count 0 2006.182.07:38:17.98#ibcon#end of sib2, iclass 22, count 0 2006.182.07:38:17.98#ibcon#*after write, iclass 22, count 0 2006.182.07:38:17.98#ibcon#*before return 0, iclass 22, count 0 2006.182.07:38:17.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:17.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:17.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:38:17.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:38:17.98$vc4f8/va=1,8 2006.182.07:38:17.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.07:38:17.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.07:38:17.98#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:17.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:17.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:17.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:17.98#ibcon#enter wrdev, iclass 24, count 2 2006.182.07:38:17.98#ibcon#first serial, iclass 24, count 2 2006.182.07:38:17.98#ibcon#enter sib2, iclass 24, count 2 2006.182.07:38:17.98#ibcon#flushed, iclass 24, count 2 2006.182.07:38:17.98#ibcon#about to write, iclass 24, count 2 2006.182.07:38:17.98#ibcon#wrote, iclass 24, count 2 2006.182.07:38:17.98#ibcon#about to read 3, iclass 24, count 2 2006.182.07:38:18.00#ibcon#read 3, iclass 24, count 2 2006.182.07:38:18.00#ibcon#about to read 4, iclass 24, count 2 2006.182.07:38:18.00#ibcon#read 4, iclass 24, count 2 2006.182.07:38:18.00#ibcon#about to read 5, iclass 24, count 2 2006.182.07:38:18.00#ibcon#read 5, iclass 24, count 2 2006.182.07:38:18.00#ibcon#about to read 6, iclass 24, count 2 2006.182.07:38:18.00#ibcon#read 6, iclass 24, count 2 2006.182.07:38:18.00#ibcon#end of sib2, iclass 24, count 2 2006.182.07:38:18.00#ibcon#*mode == 0, iclass 24, count 2 2006.182.07:38:18.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.07:38:18.00#ibcon#[25=AT01-08\r\n] 2006.182.07:38:18.00#ibcon#*before write, iclass 24, count 2 2006.182.07:38:18.00#ibcon#enter sib2, iclass 24, count 2 2006.182.07:38:18.00#ibcon#flushed, iclass 24, count 2 2006.182.07:38:18.00#ibcon#about to write, iclass 24, count 2 2006.182.07:38:18.00#ibcon#wrote, iclass 24, count 2 2006.182.07:38:18.00#ibcon#about to read 3, iclass 24, count 2 2006.182.07:38:18.03#ibcon#read 3, iclass 24, count 2 2006.182.07:38:18.03#ibcon#about to read 4, iclass 24, count 2 2006.182.07:38:18.03#ibcon#read 4, iclass 24, count 2 2006.182.07:38:18.03#ibcon#about to read 5, iclass 24, count 2 2006.182.07:38:18.03#ibcon#read 5, iclass 24, count 2 2006.182.07:38:18.03#ibcon#about to read 6, iclass 24, count 2 2006.182.07:38:18.03#ibcon#read 6, iclass 24, count 2 2006.182.07:38:18.03#ibcon#end of sib2, iclass 24, count 2 2006.182.07:38:18.03#ibcon#*after write, iclass 24, count 2 2006.182.07:38:18.03#ibcon#*before return 0, iclass 24, count 2 2006.182.07:38:18.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:18.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:18.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.07:38:18.03#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:18.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:18.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:18.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:18.15#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:38:18.15#ibcon#first serial, iclass 24, count 0 2006.182.07:38:18.15#ibcon#enter sib2, iclass 24, count 0 2006.182.07:38:18.15#ibcon#flushed, iclass 24, count 0 2006.182.07:38:18.15#ibcon#about to write, iclass 24, count 0 2006.182.07:38:18.15#ibcon#wrote, iclass 24, count 0 2006.182.07:38:18.15#ibcon#about to read 3, iclass 24, count 0 2006.182.07:38:18.17#ibcon#read 3, iclass 24, count 0 2006.182.07:38:18.17#ibcon#about to read 4, iclass 24, count 0 2006.182.07:38:18.17#ibcon#read 4, iclass 24, count 0 2006.182.07:38:18.17#ibcon#about to read 5, iclass 24, count 0 2006.182.07:38:18.17#ibcon#read 5, iclass 24, count 0 2006.182.07:38:18.17#ibcon#about to read 6, iclass 24, count 0 2006.182.07:38:18.17#ibcon#read 6, iclass 24, count 0 2006.182.07:38:18.17#ibcon#end of sib2, iclass 24, count 0 2006.182.07:38:18.17#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:38:18.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:38:18.17#ibcon#[25=USB\r\n] 2006.182.07:38:18.17#ibcon#*before write, iclass 24, count 0 2006.182.07:38:18.17#ibcon#enter sib2, iclass 24, count 0 2006.182.07:38:18.17#ibcon#flushed, iclass 24, count 0 2006.182.07:38:18.17#ibcon#about to write, iclass 24, count 0 2006.182.07:38:18.17#ibcon#wrote, iclass 24, count 0 2006.182.07:38:18.17#ibcon#about to read 3, iclass 24, count 0 2006.182.07:38:18.20#ibcon#read 3, iclass 24, count 0 2006.182.07:38:18.20#ibcon#about to read 4, iclass 24, count 0 2006.182.07:38:18.20#ibcon#read 4, iclass 24, count 0 2006.182.07:38:18.20#ibcon#about to read 5, iclass 24, count 0 2006.182.07:38:18.20#ibcon#read 5, iclass 24, count 0 2006.182.07:38:18.20#ibcon#about to read 6, iclass 24, count 0 2006.182.07:38:18.20#ibcon#read 6, iclass 24, count 0 2006.182.07:38:18.20#ibcon#end of sib2, iclass 24, count 0 2006.182.07:38:18.20#ibcon#*after write, iclass 24, count 0 2006.182.07:38:18.20#ibcon#*before return 0, iclass 24, count 0 2006.182.07:38:18.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:18.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:18.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:38:18.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:38:18.20$vc4f8/valo=2,572.99 2006.182.07:38:18.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.07:38:18.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.07:38:18.20#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:18.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:18.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:18.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:18.20#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:38:18.20#ibcon#first serial, iclass 26, count 0 2006.182.07:38:18.20#ibcon#enter sib2, iclass 26, count 0 2006.182.07:38:18.20#ibcon#flushed, iclass 26, count 0 2006.182.07:38:18.20#ibcon#about to write, iclass 26, count 0 2006.182.07:38:18.20#ibcon#wrote, iclass 26, count 0 2006.182.07:38:18.20#ibcon#about to read 3, iclass 26, count 0 2006.182.07:38:18.22#ibcon#read 3, iclass 26, count 0 2006.182.07:38:18.22#ibcon#about to read 4, iclass 26, count 0 2006.182.07:38:18.22#ibcon#read 4, iclass 26, count 0 2006.182.07:38:18.22#ibcon#about to read 5, iclass 26, count 0 2006.182.07:38:18.22#ibcon#read 5, iclass 26, count 0 2006.182.07:38:18.22#ibcon#about to read 6, iclass 26, count 0 2006.182.07:38:18.22#ibcon#read 6, iclass 26, count 0 2006.182.07:38:18.22#ibcon#end of sib2, iclass 26, count 0 2006.182.07:38:18.22#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:38:18.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:38:18.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:38:18.22#ibcon#*before write, iclass 26, count 0 2006.182.07:38:18.22#ibcon#enter sib2, iclass 26, count 0 2006.182.07:38:18.22#ibcon#flushed, iclass 26, count 0 2006.182.07:38:18.22#ibcon#about to write, iclass 26, count 0 2006.182.07:38:18.22#ibcon#wrote, iclass 26, count 0 2006.182.07:38:18.22#ibcon#about to read 3, iclass 26, count 0 2006.182.07:38:18.26#ibcon#read 3, iclass 26, count 0 2006.182.07:38:18.26#ibcon#about to read 4, iclass 26, count 0 2006.182.07:38:18.26#ibcon#read 4, iclass 26, count 0 2006.182.07:38:18.26#ibcon#about to read 5, iclass 26, count 0 2006.182.07:38:18.26#ibcon#read 5, iclass 26, count 0 2006.182.07:38:18.26#ibcon#about to read 6, iclass 26, count 0 2006.182.07:38:18.26#ibcon#read 6, iclass 26, count 0 2006.182.07:38:18.26#ibcon#end of sib2, iclass 26, count 0 2006.182.07:38:18.26#ibcon#*after write, iclass 26, count 0 2006.182.07:38:18.26#ibcon#*before return 0, iclass 26, count 0 2006.182.07:38:18.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:18.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:18.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:38:18.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:38:18.26$vc4f8/va=2,7 2006.182.07:38:18.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.07:38:18.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.07:38:18.26#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:18.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:18.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:18.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:18.33#ibcon#enter wrdev, iclass 28, count 2 2006.182.07:38:18.33#ibcon#first serial, iclass 28, count 2 2006.182.07:38:18.33#ibcon#enter sib2, iclass 28, count 2 2006.182.07:38:18.33#ibcon#flushed, iclass 28, count 2 2006.182.07:38:18.33#ibcon#about to write, iclass 28, count 2 2006.182.07:38:18.33#ibcon#wrote, iclass 28, count 2 2006.182.07:38:18.33#ibcon#about to read 3, iclass 28, count 2 2006.182.07:38:18.34#ibcon#read 3, iclass 28, count 2 2006.182.07:38:18.34#ibcon#about to read 4, iclass 28, count 2 2006.182.07:38:18.34#ibcon#read 4, iclass 28, count 2 2006.182.07:38:18.34#ibcon#about to read 5, iclass 28, count 2 2006.182.07:38:18.34#ibcon#read 5, iclass 28, count 2 2006.182.07:38:18.34#ibcon#about to read 6, iclass 28, count 2 2006.182.07:38:18.34#ibcon#read 6, iclass 28, count 2 2006.182.07:38:18.34#ibcon#end of sib2, iclass 28, count 2 2006.182.07:38:18.34#ibcon#*mode == 0, iclass 28, count 2 2006.182.07:38:18.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.07:38:18.34#ibcon#[25=AT02-07\r\n] 2006.182.07:38:18.34#ibcon#*before write, iclass 28, count 2 2006.182.07:38:18.34#ibcon#enter sib2, iclass 28, count 2 2006.182.07:38:18.34#ibcon#flushed, iclass 28, count 2 2006.182.07:38:18.34#ibcon#about to write, iclass 28, count 2 2006.182.07:38:18.34#ibcon#wrote, iclass 28, count 2 2006.182.07:38:18.34#ibcon#about to read 3, iclass 28, count 2 2006.182.07:38:18.37#ibcon#read 3, iclass 28, count 2 2006.182.07:38:18.37#ibcon#about to read 4, iclass 28, count 2 2006.182.07:38:18.37#ibcon#read 4, iclass 28, count 2 2006.182.07:38:18.37#ibcon#about to read 5, iclass 28, count 2 2006.182.07:38:18.37#ibcon#read 5, iclass 28, count 2 2006.182.07:38:18.37#ibcon#about to read 6, iclass 28, count 2 2006.182.07:38:18.37#ibcon#read 6, iclass 28, count 2 2006.182.07:38:18.37#ibcon#end of sib2, iclass 28, count 2 2006.182.07:38:18.37#ibcon#*after write, iclass 28, count 2 2006.182.07:38:18.37#ibcon#*before return 0, iclass 28, count 2 2006.182.07:38:18.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:18.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:18.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.07:38:18.37#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:18.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:18.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:18.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:18.49#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:38:18.49#ibcon#first serial, iclass 28, count 0 2006.182.07:38:18.49#ibcon#enter sib2, iclass 28, count 0 2006.182.07:38:18.49#ibcon#flushed, iclass 28, count 0 2006.182.07:38:18.49#ibcon#about to write, iclass 28, count 0 2006.182.07:38:18.49#ibcon#wrote, iclass 28, count 0 2006.182.07:38:18.49#ibcon#about to read 3, iclass 28, count 0 2006.182.07:38:18.51#ibcon#read 3, iclass 28, count 0 2006.182.07:38:18.51#ibcon#about to read 4, iclass 28, count 0 2006.182.07:38:18.51#ibcon#read 4, iclass 28, count 0 2006.182.07:38:18.51#ibcon#about to read 5, iclass 28, count 0 2006.182.07:38:18.51#ibcon#read 5, iclass 28, count 0 2006.182.07:38:18.51#ibcon#about to read 6, iclass 28, count 0 2006.182.07:38:18.51#ibcon#read 6, iclass 28, count 0 2006.182.07:38:18.51#ibcon#end of sib2, iclass 28, count 0 2006.182.07:38:18.51#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:38:18.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:38:18.51#ibcon#[25=USB\r\n] 2006.182.07:38:18.51#ibcon#*before write, iclass 28, count 0 2006.182.07:38:18.51#ibcon#enter sib2, iclass 28, count 0 2006.182.07:38:18.51#ibcon#flushed, iclass 28, count 0 2006.182.07:38:18.51#ibcon#about to write, iclass 28, count 0 2006.182.07:38:18.51#ibcon#wrote, iclass 28, count 0 2006.182.07:38:18.51#ibcon#about to read 3, iclass 28, count 0 2006.182.07:38:18.54#ibcon#read 3, iclass 28, count 0 2006.182.07:38:18.54#ibcon#about to read 4, iclass 28, count 0 2006.182.07:38:18.54#ibcon#read 4, iclass 28, count 0 2006.182.07:38:18.54#ibcon#about to read 5, iclass 28, count 0 2006.182.07:38:18.54#ibcon#read 5, iclass 28, count 0 2006.182.07:38:18.54#ibcon#about to read 6, iclass 28, count 0 2006.182.07:38:18.54#ibcon#read 6, iclass 28, count 0 2006.182.07:38:18.54#ibcon#end of sib2, iclass 28, count 0 2006.182.07:38:18.54#ibcon#*after write, iclass 28, count 0 2006.182.07:38:18.54#ibcon#*before return 0, iclass 28, count 0 2006.182.07:38:18.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:18.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:18.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:38:18.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:38:18.54$vc4f8/valo=3,672.99 2006.182.07:38:18.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.07:38:18.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.07:38:18.54#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:18.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:18.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:18.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:18.54#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:38:18.54#ibcon#first serial, iclass 30, count 0 2006.182.07:38:18.54#ibcon#enter sib2, iclass 30, count 0 2006.182.07:38:18.54#ibcon#flushed, iclass 30, count 0 2006.182.07:38:18.54#ibcon#about to write, iclass 30, count 0 2006.182.07:38:18.54#ibcon#wrote, iclass 30, count 0 2006.182.07:38:18.54#ibcon#about to read 3, iclass 30, count 0 2006.182.07:38:18.57#ibcon#read 3, iclass 30, count 0 2006.182.07:38:18.57#ibcon#about to read 4, iclass 30, count 0 2006.182.07:38:18.57#ibcon#read 4, iclass 30, count 0 2006.182.07:38:18.57#ibcon#about to read 5, iclass 30, count 0 2006.182.07:38:18.57#ibcon#read 5, iclass 30, count 0 2006.182.07:38:18.57#ibcon#about to read 6, iclass 30, count 0 2006.182.07:38:18.57#ibcon#read 6, iclass 30, count 0 2006.182.07:38:18.57#ibcon#end of sib2, iclass 30, count 0 2006.182.07:38:18.57#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:38:18.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:38:18.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:38:18.57#ibcon#*before write, iclass 30, count 0 2006.182.07:38:18.57#ibcon#enter sib2, iclass 30, count 0 2006.182.07:38:18.57#ibcon#flushed, iclass 30, count 0 2006.182.07:38:18.57#ibcon#about to write, iclass 30, count 0 2006.182.07:38:18.57#ibcon#wrote, iclass 30, count 0 2006.182.07:38:18.57#ibcon#about to read 3, iclass 30, count 0 2006.182.07:38:18.61#ibcon#read 3, iclass 30, count 0 2006.182.07:38:18.61#ibcon#about to read 4, iclass 30, count 0 2006.182.07:38:18.61#ibcon#read 4, iclass 30, count 0 2006.182.07:38:18.61#ibcon#about to read 5, iclass 30, count 0 2006.182.07:38:18.61#ibcon#read 5, iclass 30, count 0 2006.182.07:38:18.61#ibcon#about to read 6, iclass 30, count 0 2006.182.07:38:18.61#ibcon#read 6, iclass 30, count 0 2006.182.07:38:18.61#ibcon#end of sib2, iclass 30, count 0 2006.182.07:38:18.61#ibcon#*after write, iclass 30, count 0 2006.182.07:38:18.61#ibcon#*before return 0, iclass 30, count 0 2006.182.07:38:18.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:18.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:18.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:38:18.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:38:18.61$vc4f8/va=3,6 2006.182.07:38:18.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.07:38:18.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.07:38:18.61#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:18.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:18.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:18.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:18.66#ibcon#enter wrdev, iclass 32, count 2 2006.182.07:38:18.66#ibcon#first serial, iclass 32, count 2 2006.182.07:38:18.66#ibcon#enter sib2, iclass 32, count 2 2006.182.07:38:18.66#ibcon#flushed, iclass 32, count 2 2006.182.07:38:18.66#ibcon#about to write, iclass 32, count 2 2006.182.07:38:18.66#ibcon#wrote, iclass 32, count 2 2006.182.07:38:18.66#ibcon#about to read 3, iclass 32, count 2 2006.182.07:38:18.68#ibcon#read 3, iclass 32, count 2 2006.182.07:38:18.68#ibcon#about to read 4, iclass 32, count 2 2006.182.07:38:18.68#ibcon#read 4, iclass 32, count 2 2006.182.07:38:18.68#ibcon#about to read 5, iclass 32, count 2 2006.182.07:38:18.68#ibcon#read 5, iclass 32, count 2 2006.182.07:38:18.68#ibcon#about to read 6, iclass 32, count 2 2006.182.07:38:18.68#ibcon#read 6, iclass 32, count 2 2006.182.07:38:18.68#ibcon#end of sib2, iclass 32, count 2 2006.182.07:38:18.68#ibcon#*mode == 0, iclass 32, count 2 2006.182.07:38:18.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.07:38:18.68#ibcon#[25=AT03-06\r\n] 2006.182.07:38:18.68#ibcon#*before write, iclass 32, count 2 2006.182.07:38:18.68#ibcon#enter sib2, iclass 32, count 2 2006.182.07:38:18.68#ibcon#flushed, iclass 32, count 2 2006.182.07:38:18.68#ibcon#about to write, iclass 32, count 2 2006.182.07:38:18.68#ibcon#wrote, iclass 32, count 2 2006.182.07:38:18.68#ibcon#about to read 3, iclass 32, count 2 2006.182.07:38:18.71#ibcon#read 3, iclass 32, count 2 2006.182.07:38:18.71#ibcon#about to read 4, iclass 32, count 2 2006.182.07:38:18.71#ibcon#read 4, iclass 32, count 2 2006.182.07:38:18.71#ibcon#about to read 5, iclass 32, count 2 2006.182.07:38:18.71#ibcon#read 5, iclass 32, count 2 2006.182.07:38:18.71#ibcon#about to read 6, iclass 32, count 2 2006.182.07:38:18.71#ibcon#read 6, iclass 32, count 2 2006.182.07:38:18.71#ibcon#end of sib2, iclass 32, count 2 2006.182.07:38:18.71#ibcon#*after write, iclass 32, count 2 2006.182.07:38:18.71#ibcon#*before return 0, iclass 32, count 2 2006.182.07:38:18.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:18.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:18.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.07:38:18.71#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:18.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:18.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:18.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:18.83#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:38:18.83#ibcon#first serial, iclass 32, count 0 2006.182.07:38:18.83#ibcon#enter sib2, iclass 32, count 0 2006.182.07:38:18.83#ibcon#flushed, iclass 32, count 0 2006.182.07:38:18.83#ibcon#about to write, iclass 32, count 0 2006.182.07:38:18.83#ibcon#wrote, iclass 32, count 0 2006.182.07:38:18.83#ibcon#about to read 3, iclass 32, count 0 2006.182.07:38:18.85#ibcon#read 3, iclass 32, count 0 2006.182.07:38:18.85#ibcon#about to read 4, iclass 32, count 0 2006.182.07:38:18.85#ibcon#read 4, iclass 32, count 0 2006.182.07:38:18.85#ibcon#about to read 5, iclass 32, count 0 2006.182.07:38:18.85#ibcon#read 5, iclass 32, count 0 2006.182.07:38:18.85#ibcon#about to read 6, iclass 32, count 0 2006.182.07:38:18.85#ibcon#read 6, iclass 32, count 0 2006.182.07:38:18.85#ibcon#end of sib2, iclass 32, count 0 2006.182.07:38:18.85#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:38:18.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:38:18.85#ibcon#[25=USB\r\n] 2006.182.07:38:18.85#ibcon#*before write, iclass 32, count 0 2006.182.07:38:18.85#ibcon#enter sib2, iclass 32, count 0 2006.182.07:38:18.85#ibcon#flushed, iclass 32, count 0 2006.182.07:38:18.85#ibcon#about to write, iclass 32, count 0 2006.182.07:38:18.85#ibcon#wrote, iclass 32, count 0 2006.182.07:38:18.85#ibcon#about to read 3, iclass 32, count 0 2006.182.07:38:18.88#ibcon#read 3, iclass 32, count 0 2006.182.07:38:18.88#ibcon#about to read 4, iclass 32, count 0 2006.182.07:38:18.88#ibcon#read 4, iclass 32, count 0 2006.182.07:38:18.88#ibcon#about to read 5, iclass 32, count 0 2006.182.07:38:18.88#ibcon#read 5, iclass 32, count 0 2006.182.07:38:18.88#ibcon#about to read 6, iclass 32, count 0 2006.182.07:38:18.88#ibcon#read 6, iclass 32, count 0 2006.182.07:38:18.88#ibcon#end of sib2, iclass 32, count 0 2006.182.07:38:18.88#ibcon#*after write, iclass 32, count 0 2006.182.07:38:18.88#ibcon#*before return 0, iclass 32, count 0 2006.182.07:38:18.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:18.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:18.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:38:18.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:38:18.88$vc4f8/valo=4,832.99 2006.182.07:38:18.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.07:38:18.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.07:38:18.88#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:18.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:18.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:18.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:18.88#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:38:18.88#ibcon#first serial, iclass 34, count 0 2006.182.07:38:18.88#ibcon#enter sib2, iclass 34, count 0 2006.182.07:38:18.88#ibcon#flushed, iclass 34, count 0 2006.182.07:38:18.88#ibcon#about to write, iclass 34, count 0 2006.182.07:38:18.88#ibcon#wrote, iclass 34, count 0 2006.182.07:38:18.88#ibcon#about to read 3, iclass 34, count 0 2006.182.07:38:18.91#ibcon#read 3, iclass 34, count 0 2006.182.07:38:18.91#ibcon#about to read 4, iclass 34, count 0 2006.182.07:38:18.91#ibcon#read 4, iclass 34, count 0 2006.182.07:38:18.91#ibcon#about to read 5, iclass 34, count 0 2006.182.07:38:18.91#ibcon#read 5, iclass 34, count 0 2006.182.07:38:18.91#ibcon#about to read 6, iclass 34, count 0 2006.182.07:38:18.91#ibcon#read 6, iclass 34, count 0 2006.182.07:38:18.91#ibcon#end of sib2, iclass 34, count 0 2006.182.07:38:18.91#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:38:18.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:38:18.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:38:18.91#ibcon#*before write, iclass 34, count 0 2006.182.07:38:18.91#ibcon#enter sib2, iclass 34, count 0 2006.182.07:38:18.91#ibcon#flushed, iclass 34, count 0 2006.182.07:38:18.91#ibcon#about to write, iclass 34, count 0 2006.182.07:38:18.91#ibcon#wrote, iclass 34, count 0 2006.182.07:38:18.91#ibcon#about to read 3, iclass 34, count 0 2006.182.07:38:18.95#ibcon#read 3, iclass 34, count 0 2006.182.07:38:18.95#ibcon#about to read 4, iclass 34, count 0 2006.182.07:38:18.95#ibcon#read 4, iclass 34, count 0 2006.182.07:38:18.95#ibcon#about to read 5, iclass 34, count 0 2006.182.07:38:18.95#ibcon#read 5, iclass 34, count 0 2006.182.07:38:18.95#ibcon#about to read 6, iclass 34, count 0 2006.182.07:38:18.95#ibcon#read 6, iclass 34, count 0 2006.182.07:38:18.95#ibcon#end of sib2, iclass 34, count 0 2006.182.07:38:18.95#ibcon#*after write, iclass 34, count 0 2006.182.07:38:18.95#ibcon#*before return 0, iclass 34, count 0 2006.182.07:38:18.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:18.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:18.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:38:18.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:38:18.95$vc4f8/va=4,7 2006.182.07:38:18.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.182.07:38:18.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.182.07:38:18.95#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:18.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:19.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:19.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:19.00#ibcon#enter wrdev, iclass 36, count 2 2006.182.07:38:19.00#ibcon#first serial, iclass 36, count 2 2006.182.07:38:19.00#ibcon#enter sib2, iclass 36, count 2 2006.182.07:38:19.00#ibcon#flushed, iclass 36, count 2 2006.182.07:38:19.00#ibcon#about to write, iclass 36, count 2 2006.182.07:38:19.00#ibcon#wrote, iclass 36, count 2 2006.182.07:38:19.00#ibcon#about to read 3, iclass 36, count 2 2006.182.07:38:19.02#ibcon#read 3, iclass 36, count 2 2006.182.07:38:19.02#ibcon#about to read 4, iclass 36, count 2 2006.182.07:38:19.02#ibcon#read 4, iclass 36, count 2 2006.182.07:38:19.02#ibcon#about to read 5, iclass 36, count 2 2006.182.07:38:19.02#ibcon#read 5, iclass 36, count 2 2006.182.07:38:19.02#ibcon#about to read 6, iclass 36, count 2 2006.182.07:38:19.02#ibcon#read 6, iclass 36, count 2 2006.182.07:38:19.02#ibcon#end of sib2, iclass 36, count 2 2006.182.07:38:19.02#ibcon#*mode == 0, iclass 36, count 2 2006.182.07:38:19.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.182.07:38:19.02#ibcon#[25=AT04-07\r\n] 2006.182.07:38:19.02#ibcon#*before write, iclass 36, count 2 2006.182.07:38:19.02#ibcon#enter sib2, iclass 36, count 2 2006.182.07:38:19.02#ibcon#flushed, iclass 36, count 2 2006.182.07:38:19.02#ibcon#about to write, iclass 36, count 2 2006.182.07:38:19.02#ibcon#wrote, iclass 36, count 2 2006.182.07:38:19.02#ibcon#about to read 3, iclass 36, count 2 2006.182.07:38:19.05#ibcon#read 3, iclass 36, count 2 2006.182.07:38:19.05#ibcon#about to read 4, iclass 36, count 2 2006.182.07:38:19.05#ibcon#read 4, iclass 36, count 2 2006.182.07:38:19.05#ibcon#about to read 5, iclass 36, count 2 2006.182.07:38:19.05#ibcon#read 5, iclass 36, count 2 2006.182.07:38:19.05#ibcon#about to read 6, iclass 36, count 2 2006.182.07:38:19.05#ibcon#read 6, iclass 36, count 2 2006.182.07:38:19.05#ibcon#end of sib2, iclass 36, count 2 2006.182.07:38:19.05#ibcon#*after write, iclass 36, count 2 2006.182.07:38:19.05#ibcon#*before return 0, iclass 36, count 2 2006.182.07:38:19.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:19.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:19.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.182.07:38:19.05#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:19.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:19.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:19.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:19.17#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:38:19.17#ibcon#first serial, iclass 36, count 0 2006.182.07:38:19.17#ibcon#enter sib2, iclass 36, count 0 2006.182.07:38:19.17#ibcon#flushed, iclass 36, count 0 2006.182.07:38:19.17#ibcon#about to write, iclass 36, count 0 2006.182.07:38:19.17#ibcon#wrote, iclass 36, count 0 2006.182.07:38:19.17#ibcon#about to read 3, iclass 36, count 0 2006.182.07:38:19.19#ibcon#read 3, iclass 36, count 0 2006.182.07:38:19.19#ibcon#about to read 4, iclass 36, count 0 2006.182.07:38:19.19#ibcon#read 4, iclass 36, count 0 2006.182.07:38:19.19#ibcon#about to read 5, iclass 36, count 0 2006.182.07:38:19.19#ibcon#read 5, iclass 36, count 0 2006.182.07:38:19.19#ibcon#about to read 6, iclass 36, count 0 2006.182.07:38:19.19#ibcon#read 6, iclass 36, count 0 2006.182.07:38:19.19#ibcon#end of sib2, iclass 36, count 0 2006.182.07:38:19.19#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:38:19.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:38:19.19#ibcon#[25=USB\r\n] 2006.182.07:38:19.19#ibcon#*before write, iclass 36, count 0 2006.182.07:38:19.19#ibcon#enter sib2, iclass 36, count 0 2006.182.07:38:19.19#ibcon#flushed, iclass 36, count 0 2006.182.07:38:19.19#ibcon#about to write, iclass 36, count 0 2006.182.07:38:19.19#ibcon#wrote, iclass 36, count 0 2006.182.07:38:19.19#ibcon#about to read 3, iclass 36, count 0 2006.182.07:38:19.22#ibcon#read 3, iclass 36, count 0 2006.182.07:38:19.22#ibcon#about to read 4, iclass 36, count 0 2006.182.07:38:19.22#ibcon#read 4, iclass 36, count 0 2006.182.07:38:19.22#ibcon#about to read 5, iclass 36, count 0 2006.182.07:38:19.22#ibcon#read 5, iclass 36, count 0 2006.182.07:38:19.22#ibcon#about to read 6, iclass 36, count 0 2006.182.07:38:19.22#ibcon#read 6, iclass 36, count 0 2006.182.07:38:19.22#ibcon#end of sib2, iclass 36, count 0 2006.182.07:38:19.22#ibcon#*after write, iclass 36, count 0 2006.182.07:38:19.22#ibcon#*before return 0, iclass 36, count 0 2006.182.07:38:19.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:19.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:19.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:38:19.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:38:19.22$vc4f8/valo=5,652.99 2006.182.07:38:19.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.07:38:19.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.07:38:19.22#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:19.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:19.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:19.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:19.22#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:38:19.22#ibcon#first serial, iclass 38, count 0 2006.182.07:38:19.22#ibcon#enter sib2, iclass 38, count 0 2006.182.07:38:19.22#ibcon#flushed, iclass 38, count 0 2006.182.07:38:19.22#ibcon#about to write, iclass 38, count 0 2006.182.07:38:19.22#ibcon#wrote, iclass 38, count 0 2006.182.07:38:19.22#ibcon#about to read 3, iclass 38, count 0 2006.182.07:38:19.24#ibcon#read 3, iclass 38, count 0 2006.182.07:38:19.24#ibcon#about to read 4, iclass 38, count 0 2006.182.07:38:19.24#ibcon#read 4, iclass 38, count 0 2006.182.07:38:19.24#ibcon#about to read 5, iclass 38, count 0 2006.182.07:38:19.24#ibcon#read 5, iclass 38, count 0 2006.182.07:38:19.24#ibcon#about to read 6, iclass 38, count 0 2006.182.07:38:19.24#ibcon#read 6, iclass 38, count 0 2006.182.07:38:19.24#ibcon#end of sib2, iclass 38, count 0 2006.182.07:38:19.24#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:38:19.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:38:19.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:38:19.24#ibcon#*before write, iclass 38, count 0 2006.182.07:38:19.24#ibcon#enter sib2, iclass 38, count 0 2006.182.07:38:19.24#ibcon#flushed, iclass 38, count 0 2006.182.07:38:19.24#ibcon#about to write, iclass 38, count 0 2006.182.07:38:19.24#ibcon#wrote, iclass 38, count 0 2006.182.07:38:19.24#ibcon#about to read 3, iclass 38, count 0 2006.182.07:38:19.28#ibcon#read 3, iclass 38, count 0 2006.182.07:38:19.28#ibcon#about to read 4, iclass 38, count 0 2006.182.07:38:19.28#ibcon#read 4, iclass 38, count 0 2006.182.07:38:19.28#ibcon#about to read 5, iclass 38, count 0 2006.182.07:38:19.28#ibcon#read 5, iclass 38, count 0 2006.182.07:38:19.28#ibcon#about to read 6, iclass 38, count 0 2006.182.07:38:19.28#ibcon#read 6, iclass 38, count 0 2006.182.07:38:19.28#ibcon#end of sib2, iclass 38, count 0 2006.182.07:38:19.28#ibcon#*after write, iclass 38, count 0 2006.182.07:38:19.28#ibcon#*before return 0, iclass 38, count 0 2006.182.07:38:19.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:19.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:19.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:38:19.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:38:19.28$vc4f8/va=5,7 2006.182.07:38:19.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.07:38:19.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.07:38:19.28#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:19.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:19.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:19.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:19.34#ibcon#enter wrdev, iclass 40, count 2 2006.182.07:38:19.34#ibcon#first serial, iclass 40, count 2 2006.182.07:38:19.34#ibcon#enter sib2, iclass 40, count 2 2006.182.07:38:19.34#ibcon#flushed, iclass 40, count 2 2006.182.07:38:19.34#ibcon#about to write, iclass 40, count 2 2006.182.07:38:19.34#ibcon#wrote, iclass 40, count 2 2006.182.07:38:19.34#ibcon#about to read 3, iclass 40, count 2 2006.182.07:38:19.36#ibcon#read 3, iclass 40, count 2 2006.182.07:38:19.36#ibcon#about to read 4, iclass 40, count 2 2006.182.07:38:19.36#ibcon#read 4, iclass 40, count 2 2006.182.07:38:19.36#ibcon#about to read 5, iclass 40, count 2 2006.182.07:38:19.36#ibcon#read 5, iclass 40, count 2 2006.182.07:38:19.36#ibcon#about to read 6, iclass 40, count 2 2006.182.07:38:19.36#ibcon#read 6, iclass 40, count 2 2006.182.07:38:19.36#ibcon#end of sib2, iclass 40, count 2 2006.182.07:38:19.36#ibcon#*mode == 0, iclass 40, count 2 2006.182.07:38:19.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.07:38:19.36#ibcon#[25=AT05-07\r\n] 2006.182.07:38:19.36#ibcon#*before write, iclass 40, count 2 2006.182.07:38:19.36#ibcon#enter sib2, iclass 40, count 2 2006.182.07:38:19.36#ibcon#flushed, iclass 40, count 2 2006.182.07:38:19.36#ibcon#about to write, iclass 40, count 2 2006.182.07:38:19.36#ibcon#wrote, iclass 40, count 2 2006.182.07:38:19.36#ibcon#about to read 3, iclass 40, count 2 2006.182.07:38:19.39#ibcon#read 3, iclass 40, count 2 2006.182.07:38:19.39#ibcon#about to read 4, iclass 40, count 2 2006.182.07:38:19.39#ibcon#read 4, iclass 40, count 2 2006.182.07:38:19.39#ibcon#about to read 5, iclass 40, count 2 2006.182.07:38:19.39#ibcon#read 5, iclass 40, count 2 2006.182.07:38:19.39#ibcon#about to read 6, iclass 40, count 2 2006.182.07:38:19.39#ibcon#read 6, iclass 40, count 2 2006.182.07:38:19.39#ibcon#end of sib2, iclass 40, count 2 2006.182.07:38:19.39#ibcon#*after write, iclass 40, count 2 2006.182.07:38:19.39#ibcon#*before return 0, iclass 40, count 2 2006.182.07:38:19.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:19.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:19.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.07:38:19.39#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:19.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:19.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:19.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:19.51#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:38:19.51#ibcon#first serial, iclass 40, count 0 2006.182.07:38:19.51#ibcon#enter sib2, iclass 40, count 0 2006.182.07:38:19.51#ibcon#flushed, iclass 40, count 0 2006.182.07:38:19.51#ibcon#about to write, iclass 40, count 0 2006.182.07:38:19.51#ibcon#wrote, iclass 40, count 0 2006.182.07:38:19.51#ibcon#about to read 3, iclass 40, count 0 2006.182.07:38:19.53#ibcon#read 3, iclass 40, count 0 2006.182.07:38:19.53#ibcon#about to read 4, iclass 40, count 0 2006.182.07:38:19.53#ibcon#read 4, iclass 40, count 0 2006.182.07:38:19.53#ibcon#about to read 5, iclass 40, count 0 2006.182.07:38:19.53#ibcon#read 5, iclass 40, count 0 2006.182.07:38:19.53#ibcon#about to read 6, iclass 40, count 0 2006.182.07:38:19.53#ibcon#read 6, iclass 40, count 0 2006.182.07:38:19.53#ibcon#end of sib2, iclass 40, count 0 2006.182.07:38:19.53#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:38:19.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:38:19.53#ibcon#[25=USB\r\n] 2006.182.07:38:19.53#ibcon#*before write, iclass 40, count 0 2006.182.07:38:19.53#ibcon#enter sib2, iclass 40, count 0 2006.182.07:38:19.53#ibcon#flushed, iclass 40, count 0 2006.182.07:38:19.53#ibcon#about to write, iclass 40, count 0 2006.182.07:38:19.53#ibcon#wrote, iclass 40, count 0 2006.182.07:38:19.53#ibcon#about to read 3, iclass 40, count 0 2006.182.07:38:19.56#ibcon#read 3, iclass 40, count 0 2006.182.07:38:19.56#ibcon#about to read 4, iclass 40, count 0 2006.182.07:38:19.56#ibcon#read 4, iclass 40, count 0 2006.182.07:38:19.56#ibcon#about to read 5, iclass 40, count 0 2006.182.07:38:19.56#ibcon#read 5, iclass 40, count 0 2006.182.07:38:19.56#ibcon#about to read 6, iclass 40, count 0 2006.182.07:38:19.56#ibcon#read 6, iclass 40, count 0 2006.182.07:38:19.56#ibcon#end of sib2, iclass 40, count 0 2006.182.07:38:19.56#ibcon#*after write, iclass 40, count 0 2006.182.07:38:19.56#ibcon#*before return 0, iclass 40, count 0 2006.182.07:38:19.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:19.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:19.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:38:19.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:38:19.56$vc4f8/valo=6,772.99 2006.182.07:38:19.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.07:38:19.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.07:38:19.56#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:19.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:19.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:19.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:19.56#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:38:19.56#ibcon#first serial, iclass 4, count 0 2006.182.07:38:19.56#ibcon#enter sib2, iclass 4, count 0 2006.182.07:38:19.56#ibcon#flushed, iclass 4, count 0 2006.182.07:38:19.56#ibcon#about to write, iclass 4, count 0 2006.182.07:38:19.56#ibcon#wrote, iclass 4, count 0 2006.182.07:38:19.56#ibcon#about to read 3, iclass 4, count 0 2006.182.07:38:19.59#ibcon#read 3, iclass 4, count 0 2006.182.07:38:19.59#ibcon#about to read 4, iclass 4, count 0 2006.182.07:38:19.59#ibcon#read 4, iclass 4, count 0 2006.182.07:38:19.59#ibcon#about to read 5, iclass 4, count 0 2006.182.07:38:19.59#ibcon#read 5, iclass 4, count 0 2006.182.07:38:19.59#ibcon#about to read 6, iclass 4, count 0 2006.182.07:38:19.59#ibcon#read 6, iclass 4, count 0 2006.182.07:38:19.59#ibcon#end of sib2, iclass 4, count 0 2006.182.07:38:19.59#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:38:19.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:38:19.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:38:19.59#ibcon#*before write, iclass 4, count 0 2006.182.07:38:19.59#ibcon#enter sib2, iclass 4, count 0 2006.182.07:38:19.59#ibcon#flushed, iclass 4, count 0 2006.182.07:38:19.59#ibcon#about to write, iclass 4, count 0 2006.182.07:38:19.59#ibcon#wrote, iclass 4, count 0 2006.182.07:38:19.59#ibcon#about to read 3, iclass 4, count 0 2006.182.07:38:19.63#ibcon#read 3, iclass 4, count 0 2006.182.07:38:19.63#ibcon#about to read 4, iclass 4, count 0 2006.182.07:38:19.63#ibcon#read 4, iclass 4, count 0 2006.182.07:38:19.63#ibcon#about to read 5, iclass 4, count 0 2006.182.07:38:19.63#ibcon#read 5, iclass 4, count 0 2006.182.07:38:19.63#ibcon#about to read 6, iclass 4, count 0 2006.182.07:38:19.63#ibcon#read 6, iclass 4, count 0 2006.182.07:38:19.63#ibcon#end of sib2, iclass 4, count 0 2006.182.07:38:19.63#ibcon#*after write, iclass 4, count 0 2006.182.07:38:19.63#ibcon#*before return 0, iclass 4, count 0 2006.182.07:38:19.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:19.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:19.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:38:19.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:38:19.63$vc4f8/va=6,6 2006.182.07:38:19.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.07:38:19.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.07:38:19.63#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:19.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:19.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:19.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:19.68#ibcon#enter wrdev, iclass 6, count 2 2006.182.07:38:19.68#ibcon#first serial, iclass 6, count 2 2006.182.07:38:19.68#ibcon#enter sib2, iclass 6, count 2 2006.182.07:38:19.68#ibcon#flushed, iclass 6, count 2 2006.182.07:38:19.68#ibcon#about to write, iclass 6, count 2 2006.182.07:38:19.68#ibcon#wrote, iclass 6, count 2 2006.182.07:38:19.68#ibcon#about to read 3, iclass 6, count 2 2006.182.07:38:19.70#ibcon#read 3, iclass 6, count 2 2006.182.07:38:19.70#ibcon#about to read 4, iclass 6, count 2 2006.182.07:38:19.70#ibcon#read 4, iclass 6, count 2 2006.182.07:38:19.70#ibcon#about to read 5, iclass 6, count 2 2006.182.07:38:19.70#ibcon#read 5, iclass 6, count 2 2006.182.07:38:19.70#ibcon#about to read 6, iclass 6, count 2 2006.182.07:38:19.70#ibcon#read 6, iclass 6, count 2 2006.182.07:38:19.70#ibcon#end of sib2, iclass 6, count 2 2006.182.07:38:19.70#ibcon#*mode == 0, iclass 6, count 2 2006.182.07:38:19.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.07:38:19.70#ibcon#[25=AT06-06\r\n] 2006.182.07:38:19.70#ibcon#*before write, iclass 6, count 2 2006.182.07:38:19.70#ibcon#enter sib2, iclass 6, count 2 2006.182.07:38:19.70#ibcon#flushed, iclass 6, count 2 2006.182.07:38:19.70#ibcon#about to write, iclass 6, count 2 2006.182.07:38:19.70#ibcon#wrote, iclass 6, count 2 2006.182.07:38:19.70#ibcon#about to read 3, iclass 6, count 2 2006.182.07:38:19.73#ibcon#read 3, iclass 6, count 2 2006.182.07:38:19.73#ibcon#about to read 4, iclass 6, count 2 2006.182.07:38:19.73#ibcon#read 4, iclass 6, count 2 2006.182.07:38:19.73#ibcon#about to read 5, iclass 6, count 2 2006.182.07:38:19.73#ibcon#read 5, iclass 6, count 2 2006.182.07:38:19.73#ibcon#about to read 6, iclass 6, count 2 2006.182.07:38:19.73#ibcon#read 6, iclass 6, count 2 2006.182.07:38:19.73#ibcon#end of sib2, iclass 6, count 2 2006.182.07:38:19.73#ibcon#*after write, iclass 6, count 2 2006.182.07:38:19.73#ibcon#*before return 0, iclass 6, count 2 2006.182.07:38:19.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:19.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:19.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.07:38:19.73#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:19.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:19.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:19.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:19.85#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:38:19.85#ibcon#first serial, iclass 6, count 0 2006.182.07:38:19.85#ibcon#enter sib2, iclass 6, count 0 2006.182.07:38:19.85#ibcon#flushed, iclass 6, count 0 2006.182.07:38:19.85#ibcon#about to write, iclass 6, count 0 2006.182.07:38:19.85#ibcon#wrote, iclass 6, count 0 2006.182.07:38:19.85#ibcon#about to read 3, iclass 6, count 0 2006.182.07:38:19.87#ibcon#read 3, iclass 6, count 0 2006.182.07:38:19.87#ibcon#about to read 4, iclass 6, count 0 2006.182.07:38:19.87#ibcon#read 4, iclass 6, count 0 2006.182.07:38:19.87#ibcon#about to read 5, iclass 6, count 0 2006.182.07:38:19.87#ibcon#read 5, iclass 6, count 0 2006.182.07:38:19.87#ibcon#about to read 6, iclass 6, count 0 2006.182.07:38:19.87#ibcon#read 6, iclass 6, count 0 2006.182.07:38:19.87#ibcon#end of sib2, iclass 6, count 0 2006.182.07:38:19.87#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:38:19.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:38:19.87#ibcon#[25=USB\r\n] 2006.182.07:38:19.87#ibcon#*before write, iclass 6, count 0 2006.182.07:38:19.87#ibcon#enter sib2, iclass 6, count 0 2006.182.07:38:19.87#ibcon#flushed, iclass 6, count 0 2006.182.07:38:19.87#ibcon#about to write, iclass 6, count 0 2006.182.07:38:19.87#ibcon#wrote, iclass 6, count 0 2006.182.07:38:19.87#ibcon#about to read 3, iclass 6, count 0 2006.182.07:38:19.90#ibcon#read 3, iclass 6, count 0 2006.182.07:38:19.90#ibcon#about to read 4, iclass 6, count 0 2006.182.07:38:19.90#ibcon#read 4, iclass 6, count 0 2006.182.07:38:19.90#ibcon#about to read 5, iclass 6, count 0 2006.182.07:38:19.90#ibcon#read 5, iclass 6, count 0 2006.182.07:38:19.90#ibcon#about to read 6, iclass 6, count 0 2006.182.07:38:19.90#ibcon#read 6, iclass 6, count 0 2006.182.07:38:19.90#ibcon#end of sib2, iclass 6, count 0 2006.182.07:38:19.90#ibcon#*after write, iclass 6, count 0 2006.182.07:38:19.90#ibcon#*before return 0, iclass 6, count 0 2006.182.07:38:19.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:19.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:19.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:38:19.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:38:19.90$vc4f8/valo=7,832.99 2006.182.07:38:19.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.07:38:19.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.07:38:19.90#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:19.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:19.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:19.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:19.90#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:38:19.90#ibcon#first serial, iclass 10, count 0 2006.182.07:38:19.90#ibcon#enter sib2, iclass 10, count 0 2006.182.07:38:19.90#ibcon#flushed, iclass 10, count 0 2006.182.07:38:19.90#ibcon#about to write, iclass 10, count 0 2006.182.07:38:19.90#ibcon#wrote, iclass 10, count 0 2006.182.07:38:19.90#ibcon#about to read 3, iclass 10, count 0 2006.182.07:38:19.92#ibcon#read 3, iclass 10, count 0 2006.182.07:38:19.92#ibcon#about to read 4, iclass 10, count 0 2006.182.07:38:19.92#ibcon#read 4, iclass 10, count 0 2006.182.07:38:19.92#ibcon#about to read 5, iclass 10, count 0 2006.182.07:38:19.92#ibcon#read 5, iclass 10, count 0 2006.182.07:38:19.92#ibcon#about to read 6, iclass 10, count 0 2006.182.07:38:19.92#ibcon#read 6, iclass 10, count 0 2006.182.07:38:19.92#ibcon#end of sib2, iclass 10, count 0 2006.182.07:38:19.92#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:38:19.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:38:19.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:38:19.92#ibcon#*before write, iclass 10, count 0 2006.182.07:38:19.92#ibcon#enter sib2, iclass 10, count 0 2006.182.07:38:19.92#ibcon#flushed, iclass 10, count 0 2006.182.07:38:19.92#ibcon#about to write, iclass 10, count 0 2006.182.07:38:19.92#ibcon#wrote, iclass 10, count 0 2006.182.07:38:19.92#ibcon#about to read 3, iclass 10, count 0 2006.182.07:38:19.96#ibcon#read 3, iclass 10, count 0 2006.182.07:38:19.96#ibcon#about to read 4, iclass 10, count 0 2006.182.07:38:19.96#ibcon#read 4, iclass 10, count 0 2006.182.07:38:19.96#ibcon#about to read 5, iclass 10, count 0 2006.182.07:38:19.96#ibcon#read 5, iclass 10, count 0 2006.182.07:38:19.96#ibcon#about to read 6, iclass 10, count 0 2006.182.07:38:19.96#ibcon#read 6, iclass 10, count 0 2006.182.07:38:19.96#ibcon#end of sib2, iclass 10, count 0 2006.182.07:38:19.96#ibcon#*after write, iclass 10, count 0 2006.182.07:38:19.96#ibcon#*before return 0, iclass 10, count 0 2006.182.07:38:19.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:19.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:19.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:38:19.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:38:19.96$vc4f8/va=7,6 2006.182.07:38:19.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.07:38:19.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.07:38:19.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:19.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:38:20.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:38:20.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:38:20.02#ibcon#enter wrdev, iclass 12, count 2 2006.182.07:38:20.02#ibcon#first serial, iclass 12, count 2 2006.182.07:38:20.02#ibcon#enter sib2, iclass 12, count 2 2006.182.07:38:20.02#ibcon#flushed, iclass 12, count 2 2006.182.07:38:20.02#ibcon#about to write, iclass 12, count 2 2006.182.07:38:20.02#ibcon#wrote, iclass 12, count 2 2006.182.07:38:20.02#ibcon#about to read 3, iclass 12, count 2 2006.182.07:38:20.04#ibcon#read 3, iclass 12, count 2 2006.182.07:38:20.04#ibcon#about to read 4, iclass 12, count 2 2006.182.07:38:20.04#ibcon#read 4, iclass 12, count 2 2006.182.07:38:20.04#ibcon#about to read 5, iclass 12, count 2 2006.182.07:38:20.04#ibcon#read 5, iclass 12, count 2 2006.182.07:38:20.04#ibcon#about to read 6, iclass 12, count 2 2006.182.07:38:20.04#ibcon#read 6, iclass 12, count 2 2006.182.07:38:20.04#ibcon#end of sib2, iclass 12, count 2 2006.182.07:38:20.04#ibcon#*mode == 0, iclass 12, count 2 2006.182.07:38:20.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.07:38:20.04#ibcon#[25=AT07-06\r\n] 2006.182.07:38:20.04#ibcon#*before write, iclass 12, count 2 2006.182.07:38:20.04#ibcon#enter sib2, iclass 12, count 2 2006.182.07:38:20.04#ibcon#flushed, iclass 12, count 2 2006.182.07:38:20.04#ibcon#about to write, iclass 12, count 2 2006.182.07:38:20.04#ibcon#wrote, iclass 12, count 2 2006.182.07:38:20.04#ibcon#about to read 3, iclass 12, count 2 2006.182.07:38:20.07#ibcon#read 3, iclass 12, count 2 2006.182.07:38:20.07#ibcon#about to read 4, iclass 12, count 2 2006.182.07:38:20.07#ibcon#read 4, iclass 12, count 2 2006.182.07:38:20.07#ibcon#about to read 5, iclass 12, count 2 2006.182.07:38:20.07#ibcon#read 5, iclass 12, count 2 2006.182.07:38:20.07#ibcon#about to read 6, iclass 12, count 2 2006.182.07:38:20.07#ibcon#read 6, iclass 12, count 2 2006.182.07:38:20.07#ibcon#end of sib2, iclass 12, count 2 2006.182.07:38:20.07#ibcon#*after write, iclass 12, count 2 2006.182.07:38:20.07#ibcon#*before return 0, iclass 12, count 2 2006.182.07:38:20.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:38:20.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:38:20.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.07:38:20.07#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:20.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:38:20.09#abcon#<5=/04 0.5 1.5 27.46 811002.9\r\n> 2006.182.07:38:20.11#abcon#{5=INTERFACE CLEAR} 2006.182.07:38:20.17#abcon#[5=S1D000X0/0*\r\n] 2006.182.07:38:20.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:38:20.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:38:20.19#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:38:20.19#ibcon#first serial, iclass 12, count 0 2006.182.07:38:20.19#ibcon#enter sib2, iclass 12, count 0 2006.182.07:38:20.19#ibcon#flushed, iclass 12, count 0 2006.182.07:38:20.19#ibcon#about to write, iclass 12, count 0 2006.182.07:38:20.19#ibcon#wrote, iclass 12, count 0 2006.182.07:38:20.19#ibcon#about to read 3, iclass 12, count 0 2006.182.07:38:20.21#ibcon#read 3, iclass 12, count 0 2006.182.07:38:20.21#ibcon#about to read 4, iclass 12, count 0 2006.182.07:38:20.21#ibcon#read 4, iclass 12, count 0 2006.182.07:38:20.21#ibcon#about to read 5, iclass 12, count 0 2006.182.07:38:20.21#ibcon#read 5, iclass 12, count 0 2006.182.07:38:20.21#ibcon#about to read 6, iclass 12, count 0 2006.182.07:38:20.21#ibcon#read 6, iclass 12, count 0 2006.182.07:38:20.21#ibcon#end of sib2, iclass 12, count 0 2006.182.07:38:20.21#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:38:20.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:38:20.21#ibcon#[25=USB\r\n] 2006.182.07:38:20.21#ibcon#*before write, iclass 12, count 0 2006.182.07:38:20.21#ibcon#enter sib2, iclass 12, count 0 2006.182.07:38:20.21#ibcon#flushed, iclass 12, count 0 2006.182.07:38:20.21#ibcon#about to write, iclass 12, count 0 2006.182.07:38:20.21#ibcon#wrote, iclass 12, count 0 2006.182.07:38:20.21#ibcon#about to read 3, iclass 12, count 0 2006.182.07:38:20.24#ibcon#read 3, iclass 12, count 0 2006.182.07:38:20.24#ibcon#about to read 4, iclass 12, count 0 2006.182.07:38:20.24#ibcon#read 4, iclass 12, count 0 2006.182.07:38:20.24#ibcon#about to read 5, iclass 12, count 0 2006.182.07:38:20.24#ibcon#read 5, iclass 12, count 0 2006.182.07:38:20.24#ibcon#about to read 6, iclass 12, count 0 2006.182.07:38:20.24#ibcon#read 6, iclass 12, count 0 2006.182.07:38:20.24#ibcon#end of sib2, iclass 12, count 0 2006.182.07:38:20.24#ibcon#*after write, iclass 12, count 0 2006.182.07:38:20.24#ibcon#*before return 0, iclass 12, count 0 2006.182.07:38:20.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:38:20.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:38:20.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:38:20.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:38:20.24$vc4f8/valo=8,852.99 2006.182.07:38:20.24#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.07:38:20.24#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.07:38:20.24#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:20.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:38:20.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:38:20.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:38:20.24#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:38:20.24#ibcon#first serial, iclass 18, count 0 2006.182.07:38:20.24#ibcon#enter sib2, iclass 18, count 0 2006.182.07:38:20.24#ibcon#flushed, iclass 18, count 0 2006.182.07:38:20.24#ibcon#about to write, iclass 18, count 0 2006.182.07:38:20.24#ibcon#wrote, iclass 18, count 0 2006.182.07:38:20.24#ibcon#about to read 3, iclass 18, count 0 2006.182.07:38:20.26#ibcon#read 3, iclass 18, count 0 2006.182.07:38:20.26#ibcon#about to read 4, iclass 18, count 0 2006.182.07:38:20.26#ibcon#read 4, iclass 18, count 0 2006.182.07:38:20.26#ibcon#about to read 5, iclass 18, count 0 2006.182.07:38:20.26#ibcon#read 5, iclass 18, count 0 2006.182.07:38:20.26#ibcon#about to read 6, iclass 18, count 0 2006.182.07:38:20.26#ibcon#read 6, iclass 18, count 0 2006.182.07:38:20.26#ibcon#end of sib2, iclass 18, count 0 2006.182.07:38:20.26#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:38:20.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:38:20.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:38:20.26#ibcon#*before write, iclass 18, count 0 2006.182.07:38:20.26#ibcon#enter sib2, iclass 18, count 0 2006.182.07:38:20.26#ibcon#flushed, iclass 18, count 0 2006.182.07:38:20.26#ibcon#about to write, iclass 18, count 0 2006.182.07:38:20.26#ibcon#wrote, iclass 18, count 0 2006.182.07:38:20.26#ibcon#about to read 3, iclass 18, count 0 2006.182.07:38:20.30#ibcon#read 3, iclass 18, count 0 2006.182.07:38:20.30#ibcon#about to read 4, iclass 18, count 0 2006.182.07:38:20.30#ibcon#read 4, iclass 18, count 0 2006.182.07:38:20.30#ibcon#about to read 5, iclass 18, count 0 2006.182.07:38:20.30#ibcon#read 5, iclass 18, count 0 2006.182.07:38:20.30#ibcon#about to read 6, iclass 18, count 0 2006.182.07:38:20.30#ibcon#read 6, iclass 18, count 0 2006.182.07:38:20.30#ibcon#end of sib2, iclass 18, count 0 2006.182.07:38:20.30#ibcon#*after write, iclass 18, count 0 2006.182.07:38:20.30#ibcon#*before return 0, iclass 18, count 0 2006.182.07:38:20.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:38:20.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:38:20.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:38:20.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:38:20.30$vc4f8/va=8,7 2006.182.07:38:20.30#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.07:38:20.30#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.07:38:20.30#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:20.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:38:20.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:38:20.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:38:20.36#ibcon#enter wrdev, iclass 20, count 2 2006.182.07:38:20.36#ibcon#first serial, iclass 20, count 2 2006.182.07:38:20.36#ibcon#enter sib2, iclass 20, count 2 2006.182.07:38:20.36#ibcon#flushed, iclass 20, count 2 2006.182.07:38:20.36#ibcon#about to write, iclass 20, count 2 2006.182.07:38:20.36#ibcon#wrote, iclass 20, count 2 2006.182.07:38:20.36#ibcon#about to read 3, iclass 20, count 2 2006.182.07:38:20.38#ibcon#read 3, iclass 20, count 2 2006.182.07:38:20.38#ibcon#about to read 4, iclass 20, count 2 2006.182.07:38:20.38#ibcon#read 4, iclass 20, count 2 2006.182.07:38:20.38#ibcon#about to read 5, iclass 20, count 2 2006.182.07:38:20.38#ibcon#read 5, iclass 20, count 2 2006.182.07:38:20.38#ibcon#about to read 6, iclass 20, count 2 2006.182.07:38:20.38#ibcon#read 6, iclass 20, count 2 2006.182.07:38:20.38#ibcon#end of sib2, iclass 20, count 2 2006.182.07:38:20.38#ibcon#*mode == 0, iclass 20, count 2 2006.182.07:38:20.38#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.07:38:20.38#ibcon#[25=AT08-07\r\n] 2006.182.07:38:20.38#ibcon#*before write, iclass 20, count 2 2006.182.07:38:20.38#ibcon#enter sib2, iclass 20, count 2 2006.182.07:38:20.38#ibcon#flushed, iclass 20, count 2 2006.182.07:38:20.38#ibcon#about to write, iclass 20, count 2 2006.182.07:38:20.38#ibcon#wrote, iclass 20, count 2 2006.182.07:38:20.38#ibcon#about to read 3, iclass 20, count 2 2006.182.07:38:20.41#ibcon#read 3, iclass 20, count 2 2006.182.07:38:20.41#ibcon#about to read 4, iclass 20, count 2 2006.182.07:38:20.41#ibcon#read 4, iclass 20, count 2 2006.182.07:38:20.41#ibcon#about to read 5, iclass 20, count 2 2006.182.07:38:20.41#ibcon#read 5, iclass 20, count 2 2006.182.07:38:20.41#ibcon#about to read 6, iclass 20, count 2 2006.182.07:38:20.41#ibcon#read 6, iclass 20, count 2 2006.182.07:38:20.41#ibcon#end of sib2, iclass 20, count 2 2006.182.07:38:20.41#ibcon#*after write, iclass 20, count 2 2006.182.07:38:20.41#ibcon#*before return 0, iclass 20, count 2 2006.182.07:38:20.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:38:20.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:38:20.41#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.07:38:20.41#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:20.41#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:38:20.53#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:38:20.53#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:38:20.53#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:38:20.53#ibcon#first serial, iclass 20, count 0 2006.182.07:38:20.53#ibcon#enter sib2, iclass 20, count 0 2006.182.07:38:20.53#ibcon#flushed, iclass 20, count 0 2006.182.07:38:20.53#ibcon#about to write, iclass 20, count 0 2006.182.07:38:20.53#ibcon#wrote, iclass 20, count 0 2006.182.07:38:20.53#ibcon#about to read 3, iclass 20, count 0 2006.182.07:38:20.55#ibcon#read 3, iclass 20, count 0 2006.182.07:38:20.55#ibcon#about to read 4, iclass 20, count 0 2006.182.07:38:20.55#ibcon#read 4, iclass 20, count 0 2006.182.07:38:20.55#ibcon#about to read 5, iclass 20, count 0 2006.182.07:38:20.55#ibcon#read 5, iclass 20, count 0 2006.182.07:38:20.55#ibcon#about to read 6, iclass 20, count 0 2006.182.07:38:20.55#ibcon#read 6, iclass 20, count 0 2006.182.07:38:20.55#ibcon#end of sib2, iclass 20, count 0 2006.182.07:38:20.55#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:38:20.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:38:20.55#ibcon#[25=USB\r\n] 2006.182.07:38:20.55#ibcon#*before write, iclass 20, count 0 2006.182.07:38:20.55#ibcon#enter sib2, iclass 20, count 0 2006.182.07:38:20.55#ibcon#flushed, iclass 20, count 0 2006.182.07:38:20.55#ibcon#about to write, iclass 20, count 0 2006.182.07:38:20.55#ibcon#wrote, iclass 20, count 0 2006.182.07:38:20.55#ibcon#about to read 3, iclass 20, count 0 2006.182.07:38:20.58#ibcon#read 3, iclass 20, count 0 2006.182.07:38:20.58#ibcon#about to read 4, iclass 20, count 0 2006.182.07:38:20.58#ibcon#read 4, iclass 20, count 0 2006.182.07:38:20.58#ibcon#about to read 5, iclass 20, count 0 2006.182.07:38:20.58#ibcon#read 5, iclass 20, count 0 2006.182.07:38:20.58#ibcon#about to read 6, iclass 20, count 0 2006.182.07:38:20.58#ibcon#read 6, iclass 20, count 0 2006.182.07:38:20.58#ibcon#end of sib2, iclass 20, count 0 2006.182.07:38:20.58#ibcon#*after write, iclass 20, count 0 2006.182.07:38:20.58#ibcon#*before return 0, iclass 20, count 0 2006.182.07:38:20.58#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:38:20.58#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:38:20.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:38:20.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:38:20.58$vc4f8/vblo=1,632.99 2006.182.07:38:20.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.07:38:20.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.07:38:20.58#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:20.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:20.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:20.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:20.58#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:38:20.58#ibcon#first serial, iclass 22, count 0 2006.182.07:38:20.58#ibcon#enter sib2, iclass 22, count 0 2006.182.07:38:20.58#ibcon#flushed, iclass 22, count 0 2006.182.07:38:20.58#ibcon#about to write, iclass 22, count 0 2006.182.07:38:20.58#ibcon#wrote, iclass 22, count 0 2006.182.07:38:20.58#ibcon#about to read 3, iclass 22, count 0 2006.182.07:38:20.60#ibcon#read 3, iclass 22, count 0 2006.182.07:38:20.60#ibcon#about to read 4, iclass 22, count 0 2006.182.07:38:20.60#ibcon#read 4, iclass 22, count 0 2006.182.07:38:20.60#ibcon#about to read 5, iclass 22, count 0 2006.182.07:38:20.60#ibcon#read 5, iclass 22, count 0 2006.182.07:38:20.60#ibcon#about to read 6, iclass 22, count 0 2006.182.07:38:20.60#ibcon#read 6, iclass 22, count 0 2006.182.07:38:20.60#ibcon#end of sib2, iclass 22, count 0 2006.182.07:38:20.60#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:38:20.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:38:20.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:38:20.60#ibcon#*before write, iclass 22, count 0 2006.182.07:38:20.60#ibcon#enter sib2, iclass 22, count 0 2006.182.07:38:20.60#ibcon#flushed, iclass 22, count 0 2006.182.07:38:20.60#ibcon#about to write, iclass 22, count 0 2006.182.07:38:20.60#ibcon#wrote, iclass 22, count 0 2006.182.07:38:20.60#ibcon#about to read 3, iclass 22, count 0 2006.182.07:38:20.64#ibcon#read 3, iclass 22, count 0 2006.182.07:38:20.64#ibcon#about to read 4, iclass 22, count 0 2006.182.07:38:20.64#ibcon#read 4, iclass 22, count 0 2006.182.07:38:20.64#ibcon#about to read 5, iclass 22, count 0 2006.182.07:38:20.64#ibcon#read 5, iclass 22, count 0 2006.182.07:38:20.64#ibcon#about to read 6, iclass 22, count 0 2006.182.07:38:20.64#ibcon#read 6, iclass 22, count 0 2006.182.07:38:20.64#ibcon#end of sib2, iclass 22, count 0 2006.182.07:38:20.64#ibcon#*after write, iclass 22, count 0 2006.182.07:38:20.64#ibcon#*before return 0, iclass 22, count 0 2006.182.07:38:20.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:20.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:38:20.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:38:20.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:38:20.64$vc4f8/vb=1,4 2006.182.07:38:20.64#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.07:38:20.64#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.07:38:20.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:20.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:20.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:20.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:20.64#ibcon#enter wrdev, iclass 24, count 2 2006.182.07:38:20.64#ibcon#first serial, iclass 24, count 2 2006.182.07:38:20.64#ibcon#enter sib2, iclass 24, count 2 2006.182.07:38:20.64#ibcon#flushed, iclass 24, count 2 2006.182.07:38:20.64#ibcon#about to write, iclass 24, count 2 2006.182.07:38:20.64#ibcon#wrote, iclass 24, count 2 2006.182.07:38:20.64#ibcon#about to read 3, iclass 24, count 2 2006.182.07:38:20.66#ibcon#read 3, iclass 24, count 2 2006.182.07:38:20.66#ibcon#about to read 4, iclass 24, count 2 2006.182.07:38:20.66#ibcon#read 4, iclass 24, count 2 2006.182.07:38:20.66#ibcon#about to read 5, iclass 24, count 2 2006.182.07:38:20.66#ibcon#read 5, iclass 24, count 2 2006.182.07:38:20.66#ibcon#about to read 6, iclass 24, count 2 2006.182.07:38:20.66#ibcon#read 6, iclass 24, count 2 2006.182.07:38:20.66#ibcon#end of sib2, iclass 24, count 2 2006.182.07:38:20.66#ibcon#*mode == 0, iclass 24, count 2 2006.182.07:38:20.66#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.07:38:20.66#ibcon#[27=AT01-04\r\n] 2006.182.07:38:20.66#ibcon#*before write, iclass 24, count 2 2006.182.07:38:20.66#ibcon#enter sib2, iclass 24, count 2 2006.182.07:38:20.66#ibcon#flushed, iclass 24, count 2 2006.182.07:38:20.66#ibcon#about to write, iclass 24, count 2 2006.182.07:38:20.66#ibcon#wrote, iclass 24, count 2 2006.182.07:38:20.66#ibcon#about to read 3, iclass 24, count 2 2006.182.07:38:20.69#ibcon#read 3, iclass 24, count 2 2006.182.07:38:20.69#ibcon#about to read 4, iclass 24, count 2 2006.182.07:38:20.69#ibcon#read 4, iclass 24, count 2 2006.182.07:38:20.69#ibcon#about to read 5, iclass 24, count 2 2006.182.07:38:20.69#ibcon#read 5, iclass 24, count 2 2006.182.07:38:20.69#ibcon#about to read 6, iclass 24, count 2 2006.182.07:38:20.69#ibcon#read 6, iclass 24, count 2 2006.182.07:38:20.69#ibcon#end of sib2, iclass 24, count 2 2006.182.07:38:20.69#ibcon#*after write, iclass 24, count 2 2006.182.07:38:20.69#ibcon#*before return 0, iclass 24, count 2 2006.182.07:38:20.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:20.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:38:20.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.07:38:20.69#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:20.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:20.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:20.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:20.81#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:38:20.81#ibcon#first serial, iclass 24, count 0 2006.182.07:38:20.81#ibcon#enter sib2, iclass 24, count 0 2006.182.07:38:20.81#ibcon#flushed, iclass 24, count 0 2006.182.07:38:20.81#ibcon#about to write, iclass 24, count 0 2006.182.07:38:20.81#ibcon#wrote, iclass 24, count 0 2006.182.07:38:20.81#ibcon#about to read 3, iclass 24, count 0 2006.182.07:38:20.83#ibcon#read 3, iclass 24, count 0 2006.182.07:38:20.83#ibcon#about to read 4, iclass 24, count 0 2006.182.07:38:20.83#ibcon#read 4, iclass 24, count 0 2006.182.07:38:20.83#ibcon#about to read 5, iclass 24, count 0 2006.182.07:38:20.83#ibcon#read 5, iclass 24, count 0 2006.182.07:38:20.83#ibcon#about to read 6, iclass 24, count 0 2006.182.07:38:20.83#ibcon#read 6, iclass 24, count 0 2006.182.07:38:20.83#ibcon#end of sib2, iclass 24, count 0 2006.182.07:38:20.83#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:38:20.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:38:20.83#ibcon#[27=USB\r\n] 2006.182.07:38:20.83#ibcon#*before write, iclass 24, count 0 2006.182.07:38:20.83#ibcon#enter sib2, iclass 24, count 0 2006.182.07:38:20.83#ibcon#flushed, iclass 24, count 0 2006.182.07:38:20.83#ibcon#about to write, iclass 24, count 0 2006.182.07:38:20.83#ibcon#wrote, iclass 24, count 0 2006.182.07:38:20.83#ibcon#about to read 3, iclass 24, count 0 2006.182.07:38:20.86#ibcon#read 3, iclass 24, count 0 2006.182.07:38:20.86#ibcon#about to read 4, iclass 24, count 0 2006.182.07:38:20.86#ibcon#read 4, iclass 24, count 0 2006.182.07:38:20.86#ibcon#about to read 5, iclass 24, count 0 2006.182.07:38:20.86#ibcon#read 5, iclass 24, count 0 2006.182.07:38:20.86#ibcon#about to read 6, iclass 24, count 0 2006.182.07:38:20.86#ibcon#read 6, iclass 24, count 0 2006.182.07:38:20.86#ibcon#end of sib2, iclass 24, count 0 2006.182.07:38:20.86#ibcon#*after write, iclass 24, count 0 2006.182.07:38:20.86#ibcon#*before return 0, iclass 24, count 0 2006.182.07:38:20.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:20.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:38:20.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:38:20.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:38:20.86$vc4f8/vblo=2,640.99 2006.182.07:38:20.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.07:38:20.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.07:38:20.86#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:20.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:20.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:20.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:20.86#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:38:20.86#ibcon#first serial, iclass 26, count 0 2006.182.07:38:20.86#ibcon#enter sib2, iclass 26, count 0 2006.182.07:38:20.86#ibcon#flushed, iclass 26, count 0 2006.182.07:38:20.86#ibcon#about to write, iclass 26, count 0 2006.182.07:38:20.86#ibcon#wrote, iclass 26, count 0 2006.182.07:38:20.86#ibcon#about to read 3, iclass 26, count 0 2006.182.07:38:20.88#ibcon#read 3, iclass 26, count 0 2006.182.07:38:20.88#ibcon#about to read 4, iclass 26, count 0 2006.182.07:38:20.88#ibcon#read 4, iclass 26, count 0 2006.182.07:38:20.88#ibcon#about to read 5, iclass 26, count 0 2006.182.07:38:20.88#ibcon#read 5, iclass 26, count 0 2006.182.07:38:20.88#ibcon#about to read 6, iclass 26, count 0 2006.182.07:38:20.88#ibcon#read 6, iclass 26, count 0 2006.182.07:38:20.88#ibcon#end of sib2, iclass 26, count 0 2006.182.07:38:20.88#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:38:20.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:38:20.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:38:20.88#ibcon#*before write, iclass 26, count 0 2006.182.07:38:20.88#ibcon#enter sib2, iclass 26, count 0 2006.182.07:38:20.88#ibcon#flushed, iclass 26, count 0 2006.182.07:38:20.88#ibcon#about to write, iclass 26, count 0 2006.182.07:38:20.88#ibcon#wrote, iclass 26, count 0 2006.182.07:38:20.88#ibcon#about to read 3, iclass 26, count 0 2006.182.07:38:20.92#ibcon#read 3, iclass 26, count 0 2006.182.07:38:20.92#ibcon#about to read 4, iclass 26, count 0 2006.182.07:38:20.92#ibcon#read 4, iclass 26, count 0 2006.182.07:38:20.92#ibcon#about to read 5, iclass 26, count 0 2006.182.07:38:20.92#ibcon#read 5, iclass 26, count 0 2006.182.07:38:20.92#ibcon#about to read 6, iclass 26, count 0 2006.182.07:38:20.92#ibcon#read 6, iclass 26, count 0 2006.182.07:38:20.92#ibcon#end of sib2, iclass 26, count 0 2006.182.07:38:20.92#ibcon#*after write, iclass 26, count 0 2006.182.07:38:20.92#ibcon#*before return 0, iclass 26, count 0 2006.182.07:38:20.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:20.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:38:20.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:38:20.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:38:20.92$vc4f8/vb=2,4 2006.182.07:38:20.92#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.07:38:20.92#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.07:38:20.92#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:20.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:20.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:20.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:20.98#ibcon#enter wrdev, iclass 28, count 2 2006.182.07:38:20.98#ibcon#first serial, iclass 28, count 2 2006.182.07:38:20.98#ibcon#enter sib2, iclass 28, count 2 2006.182.07:38:20.98#ibcon#flushed, iclass 28, count 2 2006.182.07:38:20.98#ibcon#about to write, iclass 28, count 2 2006.182.07:38:20.98#ibcon#wrote, iclass 28, count 2 2006.182.07:38:20.98#ibcon#about to read 3, iclass 28, count 2 2006.182.07:38:21.00#ibcon#read 3, iclass 28, count 2 2006.182.07:38:21.00#ibcon#about to read 4, iclass 28, count 2 2006.182.07:38:21.00#ibcon#read 4, iclass 28, count 2 2006.182.07:38:21.00#ibcon#about to read 5, iclass 28, count 2 2006.182.07:38:21.00#ibcon#read 5, iclass 28, count 2 2006.182.07:38:21.00#ibcon#about to read 6, iclass 28, count 2 2006.182.07:38:21.00#ibcon#read 6, iclass 28, count 2 2006.182.07:38:21.00#ibcon#end of sib2, iclass 28, count 2 2006.182.07:38:21.00#ibcon#*mode == 0, iclass 28, count 2 2006.182.07:38:21.00#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.07:38:21.00#ibcon#[27=AT02-04\r\n] 2006.182.07:38:21.00#ibcon#*before write, iclass 28, count 2 2006.182.07:38:21.00#ibcon#enter sib2, iclass 28, count 2 2006.182.07:38:21.00#ibcon#flushed, iclass 28, count 2 2006.182.07:38:21.00#ibcon#about to write, iclass 28, count 2 2006.182.07:38:21.00#ibcon#wrote, iclass 28, count 2 2006.182.07:38:21.00#ibcon#about to read 3, iclass 28, count 2 2006.182.07:38:21.03#ibcon#read 3, iclass 28, count 2 2006.182.07:38:21.03#ibcon#about to read 4, iclass 28, count 2 2006.182.07:38:21.03#ibcon#read 4, iclass 28, count 2 2006.182.07:38:21.03#ibcon#about to read 5, iclass 28, count 2 2006.182.07:38:21.03#ibcon#read 5, iclass 28, count 2 2006.182.07:38:21.03#ibcon#about to read 6, iclass 28, count 2 2006.182.07:38:21.03#ibcon#read 6, iclass 28, count 2 2006.182.07:38:21.03#ibcon#end of sib2, iclass 28, count 2 2006.182.07:38:21.03#ibcon#*after write, iclass 28, count 2 2006.182.07:38:21.03#ibcon#*before return 0, iclass 28, count 2 2006.182.07:38:21.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:21.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:38:21.03#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.07:38:21.03#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:21.03#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:21.15#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:21.15#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:21.15#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:38:21.15#ibcon#first serial, iclass 28, count 0 2006.182.07:38:21.15#ibcon#enter sib2, iclass 28, count 0 2006.182.07:38:21.15#ibcon#flushed, iclass 28, count 0 2006.182.07:38:21.15#ibcon#about to write, iclass 28, count 0 2006.182.07:38:21.15#ibcon#wrote, iclass 28, count 0 2006.182.07:38:21.15#ibcon#about to read 3, iclass 28, count 0 2006.182.07:38:21.17#ibcon#read 3, iclass 28, count 0 2006.182.07:38:21.17#ibcon#about to read 4, iclass 28, count 0 2006.182.07:38:21.17#ibcon#read 4, iclass 28, count 0 2006.182.07:38:21.17#ibcon#about to read 5, iclass 28, count 0 2006.182.07:38:21.17#ibcon#read 5, iclass 28, count 0 2006.182.07:38:21.17#ibcon#about to read 6, iclass 28, count 0 2006.182.07:38:21.17#ibcon#read 6, iclass 28, count 0 2006.182.07:38:21.17#ibcon#end of sib2, iclass 28, count 0 2006.182.07:38:21.17#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:38:21.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:38:21.17#ibcon#[27=USB\r\n] 2006.182.07:38:21.17#ibcon#*before write, iclass 28, count 0 2006.182.07:38:21.17#ibcon#enter sib2, iclass 28, count 0 2006.182.07:38:21.17#ibcon#flushed, iclass 28, count 0 2006.182.07:38:21.17#ibcon#about to write, iclass 28, count 0 2006.182.07:38:21.17#ibcon#wrote, iclass 28, count 0 2006.182.07:38:21.17#ibcon#about to read 3, iclass 28, count 0 2006.182.07:38:21.20#ibcon#read 3, iclass 28, count 0 2006.182.07:38:21.20#ibcon#about to read 4, iclass 28, count 0 2006.182.07:38:21.20#ibcon#read 4, iclass 28, count 0 2006.182.07:38:21.20#ibcon#about to read 5, iclass 28, count 0 2006.182.07:38:21.20#ibcon#read 5, iclass 28, count 0 2006.182.07:38:21.20#ibcon#about to read 6, iclass 28, count 0 2006.182.07:38:21.20#ibcon#read 6, iclass 28, count 0 2006.182.07:38:21.20#ibcon#end of sib2, iclass 28, count 0 2006.182.07:38:21.20#ibcon#*after write, iclass 28, count 0 2006.182.07:38:21.20#ibcon#*before return 0, iclass 28, count 0 2006.182.07:38:21.20#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:21.20#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:38:21.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:38:21.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:38:21.20$vc4f8/vblo=3,656.99 2006.182.07:38:21.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.07:38:21.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.07:38:21.20#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:21.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:21.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:21.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:21.20#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:38:21.20#ibcon#first serial, iclass 30, count 0 2006.182.07:38:21.20#ibcon#enter sib2, iclass 30, count 0 2006.182.07:38:21.20#ibcon#flushed, iclass 30, count 0 2006.182.07:38:21.20#ibcon#about to write, iclass 30, count 0 2006.182.07:38:21.20#ibcon#wrote, iclass 30, count 0 2006.182.07:38:21.20#ibcon#about to read 3, iclass 30, count 0 2006.182.07:38:21.22#ibcon#read 3, iclass 30, count 0 2006.182.07:38:21.22#ibcon#about to read 4, iclass 30, count 0 2006.182.07:38:21.22#ibcon#read 4, iclass 30, count 0 2006.182.07:38:21.22#ibcon#about to read 5, iclass 30, count 0 2006.182.07:38:21.22#ibcon#read 5, iclass 30, count 0 2006.182.07:38:21.22#ibcon#about to read 6, iclass 30, count 0 2006.182.07:38:21.22#ibcon#read 6, iclass 30, count 0 2006.182.07:38:21.22#ibcon#end of sib2, iclass 30, count 0 2006.182.07:38:21.22#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:38:21.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:38:21.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:38:21.22#ibcon#*before write, iclass 30, count 0 2006.182.07:38:21.22#ibcon#enter sib2, iclass 30, count 0 2006.182.07:38:21.22#ibcon#flushed, iclass 30, count 0 2006.182.07:38:21.22#ibcon#about to write, iclass 30, count 0 2006.182.07:38:21.22#ibcon#wrote, iclass 30, count 0 2006.182.07:38:21.22#ibcon#about to read 3, iclass 30, count 0 2006.182.07:38:21.26#ibcon#read 3, iclass 30, count 0 2006.182.07:38:21.26#ibcon#about to read 4, iclass 30, count 0 2006.182.07:38:21.26#ibcon#read 4, iclass 30, count 0 2006.182.07:38:21.26#ibcon#about to read 5, iclass 30, count 0 2006.182.07:38:21.26#ibcon#read 5, iclass 30, count 0 2006.182.07:38:21.26#ibcon#about to read 6, iclass 30, count 0 2006.182.07:38:21.26#ibcon#read 6, iclass 30, count 0 2006.182.07:38:21.26#ibcon#end of sib2, iclass 30, count 0 2006.182.07:38:21.26#ibcon#*after write, iclass 30, count 0 2006.182.07:38:21.26#ibcon#*before return 0, iclass 30, count 0 2006.182.07:38:21.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:21.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:38:21.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:38:21.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:38:21.26$vc4f8/vb=3,4 2006.182.07:38:21.26#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.07:38:21.26#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.07:38:21.26#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:21.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:21.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:21.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:21.32#ibcon#enter wrdev, iclass 32, count 2 2006.182.07:38:21.32#ibcon#first serial, iclass 32, count 2 2006.182.07:38:21.32#ibcon#enter sib2, iclass 32, count 2 2006.182.07:38:21.32#ibcon#flushed, iclass 32, count 2 2006.182.07:38:21.32#ibcon#about to write, iclass 32, count 2 2006.182.07:38:21.32#ibcon#wrote, iclass 32, count 2 2006.182.07:38:21.32#ibcon#about to read 3, iclass 32, count 2 2006.182.07:38:21.34#ibcon#read 3, iclass 32, count 2 2006.182.07:38:21.34#ibcon#about to read 4, iclass 32, count 2 2006.182.07:38:21.34#ibcon#read 4, iclass 32, count 2 2006.182.07:38:21.34#ibcon#about to read 5, iclass 32, count 2 2006.182.07:38:21.34#ibcon#read 5, iclass 32, count 2 2006.182.07:38:21.34#ibcon#about to read 6, iclass 32, count 2 2006.182.07:38:21.34#ibcon#read 6, iclass 32, count 2 2006.182.07:38:21.34#ibcon#end of sib2, iclass 32, count 2 2006.182.07:38:21.34#ibcon#*mode == 0, iclass 32, count 2 2006.182.07:38:21.34#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.07:38:21.34#ibcon#[27=AT03-04\r\n] 2006.182.07:38:21.34#ibcon#*before write, iclass 32, count 2 2006.182.07:38:21.34#ibcon#enter sib2, iclass 32, count 2 2006.182.07:38:21.34#ibcon#flushed, iclass 32, count 2 2006.182.07:38:21.34#ibcon#about to write, iclass 32, count 2 2006.182.07:38:21.34#ibcon#wrote, iclass 32, count 2 2006.182.07:38:21.34#ibcon#about to read 3, iclass 32, count 2 2006.182.07:38:21.37#ibcon#read 3, iclass 32, count 2 2006.182.07:38:21.37#ibcon#about to read 4, iclass 32, count 2 2006.182.07:38:21.37#ibcon#read 4, iclass 32, count 2 2006.182.07:38:21.37#ibcon#about to read 5, iclass 32, count 2 2006.182.07:38:21.37#ibcon#read 5, iclass 32, count 2 2006.182.07:38:21.37#ibcon#about to read 6, iclass 32, count 2 2006.182.07:38:21.37#ibcon#read 6, iclass 32, count 2 2006.182.07:38:21.37#ibcon#end of sib2, iclass 32, count 2 2006.182.07:38:21.37#ibcon#*after write, iclass 32, count 2 2006.182.07:38:21.37#ibcon#*before return 0, iclass 32, count 2 2006.182.07:38:21.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:21.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:38:21.37#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.07:38:21.37#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:21.37#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:21.49#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:21.49#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:21.49#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:38:21.49#ibcon#first serial, iclass 32, count 0 2006.182.07:38:21.49#ibcon#enter sib2, iclass 32, count 0 2006.182.07:38:21.49#ibcon#flushed, iclass 32, count 0 2006.182.07:38:21.49#ibcon#about to write, iclass 32, count 0 2006.182.07:38:21.49#ibcon#wrote, iclass 32, count 0 2006.182.07:38:21.49#ibcon#about to read 3, iclass 32, count 0 2006.182.07:38:21.51#ibcon#read 3, iclass 32, count 0 2006.182.07:38:21.51#ibcon#about to read 4, iclass 32, count 0 2006.182.07:38:21.51#ibcon#read 4, iclass 32, count 0 2006.182.07:38:21.51#ibcon#about to read 5, iclass 32, count 0 2006.182.07:38:21.51#ibcon#read 5, iclass 32, count 0 2006.182.07:38:21.51#ibcon#about to read 6, iclass 32, count 0 2006.182.07:38:21.51#ibcon#read 6, iclass 32, count 0 2006.182.07:38:21.51#ibcon#end of sib2, iclass 32, count 0 2006.182.07:38:21.51#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:38:21.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:38:21.51#ibcon#[27=USB\r\n] 2006.182.07:38:21.51#ibcon#*before write, iclass 32, count 0 2006.182.07:38:21.51#ibcon#enter sib2, iclass 32, count 0 2006.182.07:38:21.51#ibcon#flushed, iclass 32, count 0 2006.182.07:38:21.51#ibcon#about to write, iclass 32, count 0 2006.182.07:38:21.51#ibcon#wrote, iclass 32, count 0 2006.182.07:38:21.51#ibcon#about to read 3, iclass 32, count 0 2006.182.07:38:21.54#ibcon#read 3, iclass 32, count 0 2006.182.07:38:21.54#ibcon#about to read 4, iclass 32, count 0 2006.182.07:38:21.54#ibcon#read 4, iclass 32, count 0 2006.182.07:38:21.54#ibcon#about to read 5, iclass 32, count 0 2006.182.07:38:21.54#ibcon#read 5, iclass 32, count 0 2006.182.07:38:21.54#ibcon#about to read 6, iclass 32, count 0 2006.182.07:38:21.54#ibcon#read 6, iclass 32, count 0 2006.182.07:38:21.54#ibcon#end of sib2, iclass 32, count 0 2006.182.07:38:21.54#ibcon#*after write, iclass 32, count 0 2006.182.07:38:21.54#ibcon#*before return 0, iclass 32, count 0 2006.182.07:38:21.54#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:21.54#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:38:21.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:38:21.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:38:21.54$vc4f8/vblo=4,712.99 2006.182.07:38:21.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.07:38:21.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.07:38:21.54#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:21.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:21.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:21.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:21.54#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:38:21.54#ibcon#first serial, iclass 34, count 0 2006.182.07:38:21.54#ibcon#enter sib2, iclass 34, count 0 2006.182.07:38:21.54#ibcon#flushed, iclass 34, count 0 2006.182.07:38:21.54#ibcon#about to write, iclass 34, count 0 2006.182.07:38:21.54#ibcon#wrote, iclass 34, count 0 2006.182.07:38:21.54#ibcon#about to read 3, iclass 34, count 0 2006.182.07:38:21.56#ibcon#read 3, iclass 34, count 0 2006.182.07:38:21.56#ibcon#about to read 4, iclass 34, count 0 2006.182.07:38:21.56#ibcon#read 4, iclass 34, count 0 2006.182.07:38:21.56#ibcon#about to read 5, iclass 34, count 0 2006.182.07:38:21.56#ibcon#read 5, iclass 34, count 0 2006.182.07:38:21.56#ibcon#about to read 6, iclass 34, count 0 2006.182.07:38:21.56#ibcon#read 6, iclass 34, count 0 2006.182.07:38:21.56#ibcon#end of sib2, iclass 34, count 0 2006.182.07:38:21.56#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:38:21.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:38:21.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:38:21.56#ibcon#*before write, iclass 34, count 0 2006.182.07:38:21.56#ibcon#enter sib2, iclass 34, count 0 2006.182.07:38:21.56#ibcon#flushed, iclass 34, count 0 2006.182.07:38:21.56#ibcon#about to write, iclass 34, count 0 2006.182.07:38:21.56#ibcon#wrote, iclass 34, count 0 2006.182.07:38:21.56#ibcon#about to read 3, iclass 34, count 0 2006.182.07:38:21.60#ibcon#read 3, iclass 34, count 0 2006.182.07:38:21.60#ibcon#about to read 4, iclass 34, count 0 2006.182.07:38:21.60#ibcon#read 4, iclass 34, count 0 2006.182.07:38:21.60#ibcon#about to read 5, iclass 34, count 0 2006.182.07:38:21.60#ibcon#read 5, iclass 34, count 0 2006.182.07:38:21.60#ibcon#about to read 6, iclass 34, count 0 2006.182.07:38:21.60#ibcon#read 6, iclass 34, count 0 2006.182.07:38:21.60#ibcon#end of sib2, iclass 34, count 0 2006.182.07:38:21.60#ibcon#*after write, iclass 34, count 0 2006.182.07:38:21.60#ibcon#*before return 0, iclass 34, count 0 2006.182.07:38:21.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:21.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:38:21.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:38:21.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:38:21.60$vc4f8/vb=4,4 2006.182.07:38:21.60#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.182.07:38:21.60#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.182.07:38:21.60#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:21.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:21.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:21.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:21.66#ibcon#enter wrdev, iclass 36, count 2 2006.182.07:38:21.66#ibcon#first serial, iclass 36, count 2 2006.182.07:38:21.66#ibcon#enter sib2, iclass 36, count 2 2006.182.07:38:21.66#ibcon#flushed, iclass 36, count 2 2006.182.07:38:21.66#ibcon#about to write, iclass 36, count 2 2006.182.07:38:21.66#ibcon#wrote, iclass 36, count 2 2006.182.07:38:21.66#ibcon#about to read 3, iclass 36, count 2 2006.182.07:38:21.68#ibcon#read 3, iclass 36, count 2 2006.182.07:38:21.68#ibcon#about to read 4, iclass 36, count 2 2006.182.07:38:21.68#ibcon#read 4, iclass 36, count 2 2006.182.07:38:21.68#ibcon#about to read 5, iclass 36, count 2 2006.182.07:38:21.68#ibcon#read 5, iclass 36, count 2 2006.182.07:38:21.68#ibcon#about to read 6, iclass 36, count 2 2006.182.07:38:21.68#ibcon#read 6, iclass 36, count 2 2006.182.07:38:21.68#ibcon#end of sib2, iclass 36, count 2 2006.182.07:38:21.68#ibcon#*mode == 0, iclass 36, count 2 2006.182.07:38:21.68#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.182.07:38:21.68#ibcon#[27=AT04-04\r\n] 2006.182.07:38:21.68#ibcon#*before write, iclass 36, count 2 2006.182.07:38:21.68#ibcon#enter sib2, iclass 36, count 2 2006.182.07:38:21.68#ibcon#flushed, iclass 36, count 2 2006.182.07:38:21.68#ibcon#about to write, iclass 36, count 2 2006.182.07:38:21.68#ibcon#wrote, iclass 36, count 2 2006.182.07:38:21.68#ibcon#about to read 3, iclass 36, count 2 2006.182.07:38:21.71#ibcon#read 3, iclass 36, count 2 2006.182.07:38:21.71#ibcon#about to read 4, iclass 36, count 2 2006.182.07:38:21.71#ibcon#read 4, iclass 36, count 2 2006.182.07:38:21.71#ibcon#about to read 5, iclass 36, count 2 2006.182.07:38:21.71#ibcon#read 5, iclass 36, count 2 2006.182.07:38:21.71#ibcon#about to read 6, iclass 36, count 2 2006.182.07:38:21.71#ibcon#read 6, iclass 36, count 2 2006.182.07:38:21.71#ibcon#end of sib2, iclass 36, count 2 2006.182.07:38:21.71#ibcon#*after write, iclass 36, count 2 2006.182.07:38:21.71#ibcon#*before return 0, iclass 36, count 2 2006.182.07:38:21.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:21.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:38:21.71#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.182.07:38:21.71#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:21.71#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:21.83#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:21.83#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:21.83#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:38:21.83#ibcon#first serial, iclass 36, count 0 2006.182.07:38:21.83#ibcon#enter sib2, iclass 36, count 0 2006.182.07:38:21.83#ibcon#flushed, iclass 36, count 0 2006.182.07:38:21.83#ibcon#about to write, iclass 36, count 0 2006.182.07:38:21.83#ibcon#wrote, iclass 36, count 0 2006.182.07:38:21.83#ibcon#about to read 3, iclass 36, count 0 2006.182.07:38:21.85#ibcon#read 3, iclass 36, count 0 2006.182.07:38:21.85#ibcon#about to read 4, iclass 36, count 0 2006.182.07:38:21.85#ibcon#read 4, iclass 36, count 0 2006.182.07:38:21.85#ibcon#about to read 5, iclass 36, count 0 2006.182.07:38:21.85#ibcon#read 5, iclass 36, count 0 2006.182.07:38:21.85#ibcon#about to read 6, iclass 36, count 0 2006.182.07:38:21.85#ibcon#read 6, iclass 36, count 0 2006.182.07:38:21.85#ibcon#end of sib2, iclass 36, count 0 2006.182.07:38:21.85#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:38:21.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:38:21.85#ibcon#[27=USB\r\n] 2006.182.07:38:21.85#ibcon#*before write, iclass 36, count 0 2006.182.07:38:21.85#ibcon#enter sib2, iclass 36, count 0 2006.182.07:38:21.85#ibcon#flushed, iclass 36, count 0 2006.182.07:38:21.85#ibcon#about to write, iclass 36, count 0 2006.182.07:38:21.85#ibcon#wrote, iclass 36, count 0 2006.182.07:38:21.85#ibcon#about to read 3, iclass 36, count 0 2006.182.07:38:21.88#ibcon#read 3, iclass 36, count 0 2006.182.07:38:21.88#ibcon#about to read 4, iclass 36, count 0 2006.182.07:38:21.88#ibcon#read 4, iclass 36, count 0 2006.182.07:38:21.88#ibcon#about to read 5, iclass 36, count 0 2006.182.07:38:21.88#ibcon#read 5, iclass 36, count 0 2006.182.07:38:21.88#ibcon#about to read 6, iclass 36, count 0 2006.182.07:38:21.88#ibcon#read 6, iclass 36, count 0 2006.182.07:38:21.88#ibcon#end of sib2, iclass 36, count 0 2006.182.07:38:21.88#ibcon#*after write, iclass 36, count 0 2006.182.07:38:21.88#ibcon#*before return 0, iclass 36, count 0 2006.182.07:38:21.88#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:21.88#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:38:21.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:38:21.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:38:21.88$vc4f8/vblo=5,744.99 2006.182.07:38:21.88#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.07:38:21.88#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.07:38:21.88#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:21.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:21.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:21.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:21.88#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:38:21.88#ibcon#first serial, iclass 38, count 0 2006.182.07:38:21.88#ibcon#enter sib2, iclass 38, count 0 2006.182.07:38:21.88#ibcon#flushed, iclass 38, count 0 2006.182.07:38:21.88#ibcon#about to write, iclass 38, count 0 2006.182.07:38:21.88#ibcon#wrote, iclass 38, count 0 2006.182.07:38:21.88#ibcon#about to read 3, iclass 38, count 0 2006.182.07:38:21.91#ibcon#read 3, iclass 38, count 0 2006.182.07:38:21.91#ibcon#about to read 4, iclass 38, count 0 2006.182.07:38:21.91#ibcon#read 4, iclass 38, count 0 2006.182.07:38:21.91#ibcon#about to read 5, iclass 38, count 0 2006.182.07:38:21.91#ibcon#read 5, iclass 38, count 0 2006.182.07:38:21.91#ibcon#about to read 6, iclass 38, count 0 2006.182.07:38:21.91#ibcon#read 6, iclass 38, count 0 2006.182.07:38:21.91#ibcon#end of sib2, iclass 38, count 0 2006.182.07:38:21.91#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:38:21.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:38:21.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:38:21.91#ibcon#*before write, iclass 38, count 0 2006.182.07:38:21.91#ibcon#enter sib2, iclass 38, count 0 2006.182.07:38:21.91#ibcon#flushed, iclass 38, count 0 2006.182.07:38:21.91#ibcon#about to write, iclass 38, count 0 2006.182.07:38:21.91#ibcon#wrote, iclass 38, count 0 2006.182.07:38:21.91#ibcon#about to read 3, iclass 38, count 0 2006.182.07:38:21.95#ibcon#read 3, iclass 38, count 0 2006.182.07:38:21.95#ibcon#about to read 4, iclass 38, count 0 2006.182.07:38:21.95#ibcon#read 4, iclass 38, count 0 2006.182.07:38:21.95#ibcon#about to read 5, iclass 38, count 0 2006.182.07:38:21.95#ibcon#read 5, iclass 38, count 0 2006.182.07:38:21.95#ibcon#about to read 6, iclass 38, count 0 2006.182.07:38:21.95#ibcon#read 6, iclass 38, count 0 2006.182.07:38:21.95#ibcon#end of sib2, iclass 38, count 0 2006.182.07:38:21.95#ibcon#*after write, iclass 38, count 0 2006.182.07:38:21.95#ibcon#*before return 0, iclass 38, count 0 2006.182.07:38:21.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:21.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:38:21.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:38:21.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:38:21.95$vc4f8/vb=5,4 2006.182.07:38:21.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.07:38:21.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.07:38:21.95#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:21.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:22.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:22.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:22.00#ibcon#enter wrdev, iclass 40, count 2 2006.182.07:38:22.00#ibcon#first serial, iclass 40, count 2 2006.182.07:38:22.00#ibcon#enter sib2, iclass 40, count 2 2006.182.07:38:22.00#ibcon#flushed, iclass 40, count 2 2006.182.07:38:22.00#ibcon#about to write, iclass 40, count 2 2006.182.07:38:22.00#ibcon#wrote, iclass 40, count 2 2006.182.07:38:22.00#ibcon#about to read 3, iclass 40, count 2 2006.182.07:38:22.02#ibcon#read 3, iclass 40, count 2 2006.182.07:38:22.02#ibcon#about to read 4, iclass 40, count 2 2006.182.07:38:22.02#ibcon#read 4, iclass 40, count 2 2006.182.07:38:22.02#ibcon#about to read 5, iclass 40, count 2 2006.182.07:38:22.02#ibcon#read 5, iclass 40, count 2 2006.182.07:38:22.02#ibcon#about to read 6, iclass 40, count 2 2006.182.07:38:22.02#ibcon#read 6, iclass 40, count 2 2006.182.07:38:22.02#ibcon#end of sib2, iclass 40, count 2 2006.182.07:38:22.02#ibcon#*mode == 0, iclass 40, count 2 2006.182.07:38:22.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.07:38:22.02#ibcon#[27=AT05-04\r\n] 2006.182.07:38:22.02#ibcon#*before write, iclass 40, count 2 2006.182.07:38:22.02#ibcon#enter sib2, iclass 40, count 2 2006.182.07:38:22.02#ibcon#flushed, iclass 40, count 2 2006.182.07:38:22.02#ibcon#about to write, iclass 40, count 2 2006.182.07:38:22.02#ibcon#wrote, iclass 40, count 2 2006.182.07:38:22.02#ibcon#about to read 3, iclass 40, count 2 2006.182.07:38:22.05#ibcon#read 3, iclass 40, count 2 2006.182.07:38:22.05#ibcon#about to read 4, iclass 40, count 2 2006.182.07:38:22.05#ibcon#read 4, iclass 40, count 2 2006.182.07:38:22.05#ibcon#about to read 5, iclass 40, count 2 2006.182.07:38:22.05#ibcon#read 5, iclass 40, count 2 2006.182.07:38:22.05#ibcon#about to read 6, iclass 40, count 2 2006.182.07:38:22.05#ibcon#read 6, iclass 40, count 2 2006.182.07:38:22.05#ibcon#end of sib2, iclass 40, count 2 2006.182.07:38:22.05#ibcon#*after write, iclass 40, count 2 2006.182.07:38:22.05#ibcon#*before return 0, iclass 40, count 2 2006.182.07:38:22.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:22.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:38:22.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.07:38:22.05#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:22.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:22.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:22.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:22.17#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:38:22.17#ibcon#first serial, iclass 40, count 0 2006.182.07:38:22.17#ibcon#enter sib2, iclass 40, count 0 2006.182.07:38:22.17#ibcon#flushed, iclass 40, count 0 2006.182.07:38:22.17#ibcon#about to write, iclass 40, count 0 2006.182.07:38:22.17#ibcon#wrote, iclass 40, count 0 2006.182.07:38:22.17#ibcon#about to read 3, iclass 40, count 0 2006.182.07:38:22.19#ibcon#read 3, iclass 40, count 0 2006.182.07:38:22.19#ibcon#about to read 4, iclass 40, count 0 2006.182.07:38:22.19#ibcon#read 4, iclass 40, count 0 2006.182.07:38:22.19#ibcon#about to read 5, iclass 40, count 0 2006.182.07:38:22.19#ibcon#read 5, iclass 40, count 0 2006.182.07:38:22.19#ibcon#about to read 6, iclass 40, count 0 2006.182.07:38:22.19#ibcon#read 6, iclass 40, count 0 2006.182.07:38:22.19#ibcon#end of sib2, iclass 40, count 0 2006.182.07:38:22.19#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:38:22.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:38:22.19#ibcon#[27=USB\r\n] 2006.182.07:38:22.19#ibcon#*before write, iclass 40, count 0 2006.182.07:38:22.19#ibcon#enter sib2, iclass 40, count 0 2006.182.07:38:22.19#ibcon#flushed, iclass 40, count 0 2006.182.07:38:22.19#ibcon#about to write, iclass 40, count 0 2006.182.07:38:22.19#ibcon#wrote, iclass 40, count 0 2006.182.07:38:22.19#ibcon#about to read 3, iclass 40, count 0 2006.182.07:38:22.22#ibcon#read 3, iclass 40, count 0 2006.182.07:38:22.22#ibcon#about to read 4, iclass 40, count 0 2006.182.07:38:22.22#ibcon#read 4, iclass 40, count 0 2006.182.07:38:22.22#ibcon#about to read 5, iclass 40, count 0 2006.182.07:38:22.22#ibcon#read 5, iclass 40, count 0 2006.182.07:38:22.22#ibcon#about to read 6, iclass 40, count 0 2006.182.07:38:22.22#ibcon#read 6, iclass 40, count 0 2006.182.07:38:22.22#ibcon#end of sib2, iclass 40, count 0 2006.182.07:38:22.22#ibcon#*after write, iclass 40, count 0 2006.182.07:38:22.22#ibcon#*before return 0, iclass 40, count 0 2006.182.07:38:22.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:22.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:38:22.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:38:22.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:38:22.22$vc4f8/vblo=6,752.99 2006.182.07:38:22.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.07:38:22.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.07:38:22.22#ibcon#ireg 17 cls_cnt 0 2006.182.07:38:22.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:22.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:22.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:22.22#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:38:22.22#ibcon#first serial, iclass 4, count 0 2006.182.07:38:22.22#ibcon#enter sib2, iclass 4, count 0 2006.182.07:38:22.22#ibcon#flushed, iclass 4, count 0 2006.182.07:38:22.22#ibcon#about to write, iclass 4, count 0 2006.182.07:38:22.22#ibcon#wrote, iclass 4, count 0 2006.182.07:38:22.22#ibcon#about to read 3, iclass 4, count 0 2006.182.07:38:22.24#ibcon#read 3, iclass 4, count 0 2006.182.07:38:22.24#ibcon#about to read 4, iclass 4, count 0 2006.182.07:38:22.24#ibcon#read 4, iclass 4, count 0 2006.182.07:38:22.24#ibcon#about to read 5, iclass 4, count 0 2006.182.07:38:22.24#ibcon#read 5, iclass 4, count 0 2006.182.07:38:22.24#ibcon#about to read 6, iclass 4, count 0 2006.182.07:38:22.24#ibcon#read 6, iclass 4, count 0 2006.182.07:38:22.24#ibcon#end of sib2, iclass 4, count 0 2006.182.07:38:22.24#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:38:22.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:38:22.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:38:22.24#ibcon#*before write, iclass 4, count 0 2006.182.07:38:22.24#ibcon#enter sib2, iclass 4, count 0 2006.182.07:38:22.24#ibcon#flushed, iclass 4, count 0 2006.182.07:38:22.24#ibcon#about to write, iclass 4, count 0 2006.182.07:38:22.24#ibcon#wrote, iclass 4, count 0 2006.182.07:38:22.24#ibcon#about to read 3, iclass 4, count 0 2006.182.07:38:22.28#ibcon#read 3, iclass 4, count 0 2006.182.07:38:22.28#ibcon#about to read 4, iclass 4, count 0 2006.182.07:38:22.28#ibcon#read 4, iclass 4, count 0 2006.182.07:38:22.28#ibcon#about to read 5, iclass 4, count 0 2006.182.07:38:22.28#ibcon#read 5, iclass 4, count 0 2006.182.07:38:22.28#ibcon#about to read 6, iclass 4, count 0 2006.182.07:38:22.28#ibcon#read 6, iclass 4, count 0 2006.182.07:38:22.28#ibcon#end of sib2, iclass 4, count 0 2006.182.07:38:22.28#ibcon#*after write, iclass 4, count 0 2006.182.07:38:22.28#ibcon#*before return 0, iclass 4, count 0 2006.182.07:38:22.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:22.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:38:22.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:38:22.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:38:22.28$vc4f8/vb=6,4 2006.182.07:38:22.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.07:38:22.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.07:38:22.28#ibcon#ireg 11 cls_cnt 2 2006.182.07:38:22.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:22.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:22.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:22.34#ibcon#enter wrdev, iclass 6, count 2 2006.182.07:38:22.34#ibcon#first serial, iclass 6, count 2 2006.182.07:38:22.34#ibcon#enter sib2, iclass 6, count 2 2006.182.07:38:22.34#ibcon#flushed, iclass 6, count 2 2006.182.07:38:22.34#ibcon#about to write, iclass 6, count 2 2006.182.07:38:22.34#ibcon#wrote, iclass 6, count 2 2006.182.07:38:22.34#ibcon#about to read 3, iclass 6, count 2 2006.182.07:38:22.36#ibcon#read 3, iclass 6, count 2 2006.182.07:38:22.36#ibcon#about to read 4, iclass 6, count 2 2006.182.07:38:22.36#ibcon#read 4, iclass 6, count 2 2006.182.07:38:22.36#ibcon#about to read 5, iclass 6, count 2 2006.182.07:38:22.36#ibcon#read 5, iclass 6, count 2 2006.182.07:38:22.36#ibcon#about to read 6, iclass 6, count 2 2006.182.07:38:22.36#ibcon#read 6, iclass 6, count 2 2006.182.07:38:22.36#ibcon#end of sib2, iclass 6, count 2 2006.182.07:38:22.36#ibcon#*mode == 0, iclass 6, count 2 2006.182.07:38:22.36#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.07:38:22.36#ibcon#[27=AT06-04\r\n] 2006.182.07:38:22.36#ibcon#*before write, iclass 6, count 2 2006.182.07:38:22.36#ibcon#enter sib2, iclass 6, count 2 2006.182.07:38:22.36#ibcon#flushed, iclass 6, count 2 2006.182.07:38:22.36#ibcon#about to write, iclass 6, count 2 2006.182.07:38:22.36#ibcon#wrote, iclass 6, count 2 2006.182.07:38:22.36#ibcon#about to read 3, iclass 6, count 2 2006.182.07:38:22.39#ibcon#read 3, iclass 6, count 2 2006.182.07:38:22.39#ibcon#about to read 4, iclass 6, count 2 2006.182.07:38:22.39#ibcon#read 4, iclass 6, count 2 2006.182.07:38:22.39#ibcon#about to read 5, iclass 6, count 2 2006.182.07:38:22.39#ibcon#read 5, iclass 6, count 2 2006.182.07:38:22.39#ibcon#about to read 6, iclass 6, count 2 2006.182.07:38:22.39#ibcon#read 6, iclass 6, count 2 2006.182.07:38:22.39#ibcon#end of sib2, iclass 6, count 2 2006.182.07:38:22.39#ibcon#*after write, iclass 6, count 2 2006.182.07:38:22.39#ibcon#*before return 0, iclass 6, count 2 2006.182.07:38:22.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:22.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:38:22.39#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.07:38:22.39#ibcon#ireg 7 cls_cnt 0 2006.182.07:38:22.39#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:22.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:22.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:22.51#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:38:22.51#ibcon#first serial, iclass 6, count 0 2006.182.07:38:22.51#ibcon#enter sib2, iclass 6, count 0 2006.182.07:38:22.51#ibcon#flushed, iclass 6, count 0 2006.182.07:38:22.51#ibcon#about to write, iclass 6, count 0 2006.182.07:38:22.51#ibcon#wrote, iclass 6, count 0 2006.182.07:38:22.51#ibcon#about to read 3, iclass 6, count 0 2006.182.07:38:22.53#ibcon#read 3, iclass 6, count 0 2006.182.07:38:22.53#ibcon#about to read 4, iclass 6, count 0 2006.182.07:38:22.53#ibcon#read 4, iclass 6, count 0 2006.182.07:38:22.53#ibcon#about to read 5, iclass 6, count 0 2006.182.07:38:22.53#ibcon#read 5, iclass 6, count 0 2006.182.07:38:22.53#ibcon#about to read 6, iclass 6, count 0 2006.182.07:38:22.53#ibcon#read 6, iclass 6, count 0 2006.182.07:38:22.53#ibcon#end of sib2, iclass 6, count 0 2006.182.07:38:22.53#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:38:22.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:38:22.53#ibcon#[27=USB\r\n] 2006.182.07:38:22.53#ibcon#*before write, iclass 6, count 0 2006.182.07:38:22.53#ibcon#enter sib2, iclass 6, count 0 2006.182.07:38:22.53#ibcon#flushed, iclass 6, count 0 2006.182.07:38:22.53#ibcon#about to write, iclass 6, count 0 2006.182.07:38:22.53#ibcon#wrote, iclass 6, count 0 2006.182.07:38:22.53#ibcon#about to read 3, iclass 6, count 0 2006.182.07:38:22.56#ibcon#read 3, iclass 6, count 0 2006.182.07:38:22.56#ibcon#about to read 4, iclass 6, count 0 2006.182.07:38:22.56#ibcon#read 4, iclass 6, count 0 2006.182.07:38:22.56#ibcon#about to read 5, iclass 6, count 0 2006.182.07:38:22.56#ibcon#read 5, iclass 6, count 0 2006.182.07:38:22.56#ibcon#about to read 6, iclass 6, count 0 2006.182.07:38:22.56#ibcon#read 6, iclass 6, count 0 2006.182.07:38:22.56#ibcon#end of sib2, iclass 6, count 0 2006.182.07:38:22.56#ibcon#*after write, iclass 6, count 0 2006.182.07:38:22.56#ibcon#*before return 0, iclass 6, count 0 2006.182.07:38:22.56#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:22.56#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:38:22.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:38:22.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:38:22.56$vc4f8/vabw=wide 2006.182.07:38:22.56#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.07:38:22.56#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.07:38:22.56#ibcon#ireg 8 cls_cnt 0 2006.182.07:38:22.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:22.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:22.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:22.56#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:38:22.56#ibcon#first serial, iclass 10, count 0 2006.182.07:38:22.56#ibcon#enter sib2, iclass 10, count 0 2006.182.07:38:22.56#ibcon#flushed, iclass 10, count 0 2006.182.07:38:22.56#ibcon#about to write, iclass 10, count 0 2006.182.07:38:22.56#ibcon#wrote, iclass 10, count 0 2006.182.07:38:22.56#ibcon#about to read 3, iclass 10, count 0 2006.182.07:38:22.58#ibcon#read 3, iclass 10, count 0 2006.182.07:38:22.58#ibcon#about to read 4, iclass 10, count 0 2006.182.07:38:22.58#ibcon#read 4, iclass 10, count 0 2006.182.07:38:22.58#ibcon#about to read 5, iclass 10, count 0 2006.182.07:38:22.58#ibcon#read 5, iclass 10, count 0 2006.182.07:38:22.58#ibcon#about to read 6, iclass 10, count 0 2006.182.07:38:22.58#ibcon#read 6, iclass 10, count 0 2006.182.07:38:22.58#ibcon#end of sib2, iclass 10, count 0 2006.182.07:38:22.58#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:38:22.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:38:22.58#ibcon#[25=BW32\r\n] 2006.182.07:38:22.58#ibcon#*before write, iclass 10, count 0 2006.182.07:38:22.58#ibcon#enter sib2, iclass 10, count 0 2006.182.07:38:22.58#ibcon#flushed, iclass 10, count 0 2006.182.07:38:22.58#ibcon#about to write, iclass 10, count 0 2006.182.07:38:22.58#ibcon#wrote, iclass 10, count 0 2006.182.07:38:22.58#ibcon#about to read 3, iclass 10, count 0 2006.182.07:38:22.61#ibcon#read 3, iclass 10, count 0 2006.182.07:38:22.61#ibcon#about to read 4, iclass 10, count 0 2006.182.07:38:22.61#ibcon#read 4, iclass 10, count 0 2006.182.07:38:22.61#ibcon#about to read 5, iclass 10, count 0 2006.182.07:38:22.61#ibcon#read 5, iclass 10, count 0 2006.182.07:38:22.61#ibcon#about to read 6, iclass 10, count 0 2006.182.07:38:22.61#ibcon#read 6, iclass 10, count 0 2006.182.07:38:22.61#ibcon#end of sib2, iclass 10, count 0 2006.182.07:38:22.61#ibcon#*after write, iclass 10, count 0 2006.182.07:38:22.61#ibcon#*before return 0, iclass 10, count 0 2006.182.07:38:22.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:22.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:38:22.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:38:22.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:38:22.61$vc4f8/vbbw=wide 2006.182.07:38:22.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.07:38:22.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.07:38:22.61#ibcon#ireg 8 cls_cnt 0 2006.182.07:38:22.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:38:22.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:38:22.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:38:22.68#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:38:22.68#ibcon#first serial, iclass 12, count 0 2006.182.07:38:22.68#ibcon#enter sib2, iclass 12, count 0 2006.182.07:38:22.68#ibcon#flushed, iclass 12, count 0 2006.182.07:38:22.68#ibcon#about to write, iclass 12, count 0 2006.182.07:38:22.68#ibcon#wrote, iclass 12, count 0 2006.182.07:38:22.68#ibcon#about to read 3, iclass 12, count 0 2006.182.07:38:22.70#ibcon#read 3, iclass 12, count 0 2006.182.07:38:22.70#ibcon#about to read 4, iclass 12, count 0 2006.182.07:38:22.70#ibcon#read 4, iclass 12, count 0 2006.182.07:38:22.70#ibcon#about to read 5, iclass 12, count 0 2006.182.07:38:22.70#ibcon#read 5, iclass 12, count 0 2006.182.07:38:22.70#ibcon#about to read 6, iclass 12, count 0 2006.182.07:38:22.70#ibcon#read 6, iclass 12, count 0 2006.182.07:38:22.70#ibcon#end of sib2, iclass 12, count 0 2006.182.07:38:22.70#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:38:22.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:38:22.70#ibcon#[27=BW32\r\n] 2006.182.07:38:22.70#ibcon#*before write, iclass 12, count 0 2006.182.07:38:22.70#ibcon#enter sib2, iclass 12, count 0 2006.182.07:38:22.70#ibcon#flushed, iclass 12, count 0 2006.182.07:38:22.70#ibcon#about to write, iclass 12, count 0 2006.182.07:38:22.70#ibcon#wrote, iclass 12, count 0 2006.182.07:38:22.70#ibcon#about to read 3, iclass 12, count 0 2006.182.07:38:22.73#ibcon#read 3, iclass 12, count 0 2006.182.07:38:22.73#ibcon#about to read 4, iclass 12, count 0 2006.182.07:38:22.73#ibcon#read 4, iclass 12, count 0 2006.182.07:38:22.73#ibcon#about to read 5, iclass 12, count 0 2006.182.07:38:22.73#ibcon#read 5, iclass 12, count 0 2006.182.07:38:22.73#ibcon#about to read 6, iclass 12, count 0 2006.182.07:38:22.73#ibcon#read 6, iclass 12, count 0 2006.182.07:38:22.73#ibcon#end of sib2, iclass 12, count 0 2006.182.07:38:22.73#ibcon#*after write, iclass 12, count 0 2006.182.07:38:22.73#ibcon#*before return 0, iclass 12, count 0 2006.182.07:38:22.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:38:22.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:38:22.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:38:22.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:38:22.73$4f8m12a/ifd4f 2006.182.07:38:22.73$ifd4f/lo= 2006.182.07:38:22.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:38:22.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:38:22.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:38:22.73$ifd4f/patch= 2006.182.07:38:22.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:38:22.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:38:22.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:38:22.73$4f8m12a/"form=m,16.000,1:2 2006.182.07:38:22.73$4f8m12a/"tpicd 2006.182.07:38:22.73$4f8m12a/echo=off 2006.182.07:38:22.73$4f8m12a/xlog=off 2006.182.07:38:22.73:!2006.182.07:38:50 2006.182.07:38:32.13#trakl#Source acquired 2006.182.07:38:32.13#flagr#flagr/antenna,acquired 2006.182.07:38:50.00:preob 2006.182.07:38:51.13/onsource/TRACKING 2006.182.07:38:51.13:!2006.182.07:39:00 2006.182.07:39:00.00:data_valid=on 2006.182.07:39:00.00:midob 2006.182.07:39:00.13/onsource/TRACKING 2006.182.07:39:00.13/wx/27.46,1002.9,81 2006.182.07:39:00.22/cable/+6.4670E-03 2006.182.07:39:01.31/va/01,08,usb,yes,29,31 2006.182.07:39:01.31/va/02,07,usb,yes,29,31 2006.182.07:39:01.31/va/03,06,usb,yes,31,31 2006.182.07:39:01.31/va/04,07,usb,yes,30,32 2006.182.07:39:01.31/va/05,07,usb,yes,31,33 2006.182.07:39:01.31/va/06,06,usb,yes,30,30 2006.182.07:39:01.31/va/07,06,usb,yes,31,30 2006.182.07:39:01.31/va/08,07,usb,yes,29,29 2006.182.07:39:01.54/valo/01,532.99,yes,locked 2006.182.07:39:01.54/valo/02,572.99,yes,locked 2006.182.07:39:01.54/valo/03,672.99,yes,locked 2006.182.07:39:01.54/valo/04,832.99,yes,locked 2006.182.07:39:01.54/valo/05,652.99,yes,locked 2006.182.07:39:01.54/valo/06,772.99,yes,locked 2006.182.07:39:01.54/valo/07,832.99,yes,locked 2006.182.07:39:01.54/valo/08,852.99,yes,locked 2006.182.07:39:02.63/vb/01,04,usb,yes,29,28 2006.182.07:39:02.63/vb/02,04,usb,yes,31,32 2006.182.07:39:02.63/vb/03,04,usb,yes,27,31 2006.182.07:39:02.63/vb/04,04,usb,yes,28,29 2006.182.07:39:02.63/vb/05,04,usb,yes,27,31 2006.182.07:39:02.63/vb/06,04,usb,yes,28,31 2006.182.07:39:02.63/vb/07,04,usb,yes,30,30 2006.182.07:39:02.63/vb/08,04,usb,yes,28,31 2006.182.07:39:02.86/vblo/01,632.99,yes,locked 2006.182.07:39:02.86/vblo/02,640.99,yes,locked 2006.182.07:39:02.86/vblo/03,656.99,yes,locked 2006.182.07:39:02.86/vblo/04,712.99,yes,locked 2006.182.07:39:02.86/vblo/05,744.99,yes,locked 2006.182.07:39:02.86/vblo/06,752.99,yes,locked 2006.182.07:39:02.86/vblo/07,734.99,yes,locked 2006.182.07:39:02.86/vblo/08,744.99,yes,locked 2006.182.07:39:03.01/vabw/8 2006.182.07:39:03.16/vbbw/8 2006.182.07:39:03.27/xfe/off,on,15.2 2006.182.07:39:03.65/ifatt/23,28,28,28 2006.182.07:39:04.07/fmout-gps/S +3.37E-07 2006.182.07:39:04.11:!2006.182.07:40:00 2006.182.07:40:00.00:data_valid=off 2006.182.07:40:00.00:postob 2006.182.07:40:00.22/cable/+6.4666E-03 2006.182.07:40:00.22/wx/27.47,1002.9,82 2006.182.07:40:01.08/fmout-gps/S +3.36E-07 2006.182.07:40:01.08:scan_name=182-0740,k06182,60 2006.182.07:40:01.09:source=1357+769,135755.37,764321.1,2000.0,cw 2006.182.07:40:01.14#flagr#flagr/antenna,new-source 2006.182.07:40:02.14:checkk5 2006.182.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:40:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:40:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:40:04.01/chk_obsdata//k5ts1/T1820739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:40:04.38/chk_obsdata//k5ts2/T1820739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:40:04.75/chk_obsdata//k5ts3/T1820739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:40:05.12/chk_obsdata//k5ts4/T1820739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:40:05.81/k5log//k5ts1_log_newline 2006.182.07:40:06.50/k5log//k5ts2_log_newline 2006.182.07:40:07.19/k5log//k5ts3_log_newline 2006.182.07:40:07.87/k5log//k5ts4_log_newline 2006.182.07:40:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:40:07.90:4f8m12a=1 2006.182.07:40:07.90$4f8m12a/echo=on 2006.182.07:40:07.90$4f8m12a/pcalon 2006.182.07:40:07.90$pcalon/"no phase cal control is implemented here 2006.182.07:40:07.90$4f8m12a/"tpicd=stop 2006.182.07:40:07.90$4f8m12a/vc4f8 2006.182.07:40:07.90$vc4f8/valo=1,532.99 2006.182.07:40:07.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.07:40:07.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.07:40:07.91#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:07.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:07.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:07.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:07.91#ibcon#enter wrdev, iclass 19, count 0 2006.182.07:40:07.91#ibcon#first serial, iclass 19, count 0 2006.182.07:40:07.91#ibcon#enter sib2, iclass 19, count 0 2006.182.07:40:07.91#ibcon#flushed, iclass 19, count 0 2006.182.07:40:07.91#ibcon#about to write, iclass 19, count 0 2006.182.07:40:07.91#ibcon#wrote, iclass 19, count 0 2006.182.07:40:07.91#ibcon#about to read 3, iclass 19, count 0 2006.182.07:40:07.94#ibcon#read 3, iclass 19, count 0 2006.182.07:40:07.94#ibcon#about to read 4, iclass 19, count 0 2006.182.07:40:07.94#ibcon#read 4, iclass 19, count 0 2006.182.07:40:07.94#ibcon#about to read 5, iclass 19, count 0 2006.182.07:40:07.94#ibcon#read 5, iclass 19, count 0 2006.182.07:40:07.94#ibcon#about to read 6, iclass 19, count 0 2006.182.07:40:07.94#ibcon#read 6, iclass 19, count 0 2006.182.07:40:07.94#ibcon#end of sib2, iclass 19, count 0 2006.182.07:40:07.94#ibcon#*mode == 0, iclass 19, count 0 2006.182.07:40:07.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.07:40:07.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:40:07.94#ibcon#*before write, iclass 19, count 0 2006.182.07:40:07.94#ibcon#enter sib2, iclass 19, count 0 2006.182.07:40:07.94#ibcon#flushed, iclass 19, count 0 2006.182.07:40:07.94#ibcon#about to write, iclass 19, count 0 2006.182.07:40:07.94#ibcon#wrote, iclass 19, count 0 2006.182.07:40:07.94#ibcon#about to read 3, iclass 19, count 0 2006.182.07:40:07.99#ibcon#read 3, iclass 19, count 0 2006.182.07:40:07.99#ibcon#about to read 4, iclass 19, count 0 2006.182.07:40:07.99#ibcon#read 4, iclass 19, count 0 2006.182.07:40:07.99#ibcon#about to read 5, iclass 19, count 0 2006.182.07:40:07.99#ibcon#read 5, iclass 19, count 0 2006.182.07:40:07.99#ibcon#about to read 6, iclass 19, count 0 2006.182.07:40:07.99#ibcon#read 6, iclass 19, count 0 2006.182.07:40:07.99#ibcon#end of sib2, iclass 19, count 0 2006.182.07:40:07.99#ibcon#*after write, iclass 19, count 0 2006.182.07:40:07.99#ibcon#*before return 0, iclass 19, count 0 2006.182.07:40:07.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:07.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:07.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.07:40:07.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.07:40:07.99$vc4f8/va=1,8 2006.182.07:40:07.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.07:40:07.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.07:40:07.99#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:07.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:07.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:07.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:07.99#ibcon#enter wrdev, iclass 21, count 2 2006.182.07:40:07.99#ibcon#first serial, iclass 21, count 2 2006.182.07:40:07.99#ibcon#enter sib2, iclass 21, count 2 2006.182.07:40:07.99#ibcon#flushed, iclass 21, count 2 2006.182.07:40:07.99#ibcon#about to write, iclass 21, count 2 2006.182.07:40:07.99#ibcon#wrote, iclass 21, count 2 2006.182.07:40:07.99#ibcon#about to read 3, iclass 21, count 2 2006.182.07:40:08.01#ibcon#read 3, iclass 21, count 2 2006.182.07:40:08.01#ibcon#about to read 4, iclass 21, count 2 2006.182.07:40:08.01#ibcon#read 4, iclass 21, count 2 2006.182.07:40:08.01#ibcon#about to read 5, iclass 21, count 2 2006.182.07:40:08.01#ibcon#read 5, iclass 21, count 2 2006.182.07:40:08.01#ibcon#about to read 6, iclass 21, count 2 2006.182.07:40:08.01#ibcon#read 6, iclass 21, count 2 2006.182.07:40:08.01#ibcon#end of sib2, iclass 21, count 2 2006.182.07:40:08.01#ibcon#*mode == 0, iclass 21, count 2 2006.182.07:40:08.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.07:40:08.01#ibcon#[25=AT01-08\r\n] 2006.182.07:40:08.01#ibcon#*before write, iclass 21, count 2 2006.182.07:40:08.01#ibcon#enter sib2, iclass 21, count 2 2006.182.07:40:08.01#ibcon#flushed, iclass 21, count 2 2006.182.07:40:08.01#ibcon#about to write, iclass 21, count 2 2006.182.07:40:08.01#ibcon#wrote, iclass 21, count 2 2006.182.07:40:08.01#ibcon#about to read 3, iclass 21, count 2 2006.182.07:40:08.05#ibcon#read 3, iclass 21, count 2 2006.182.07:40:08.05#ibcon#about to read 4, iclass 21, count 2 2006.182.07:40:08.05#ibcon#read 4, iclass 21, count 2 2006.182.07:40:08.05#ibcon#about to read 5, iclass 21, count 2 2006.182.07:40:08.05#ibcon#read 5, iclass 21, count 2 2006.182.07:40:08.05#ibcon#about to read 6, iclass 21, count 2 2006.182.07:40:08.05#ibcon#read 6, iclass 21, count 2 2006.182.07:40:08.05#ibcon#end of sib2, iclass 21, count 2 2006.182.07:40:08.05#ibcon#*after write, iclass 21, count 2 2006.182.07:40:08.05#ibcon#*before return 0, iclass 21, count 2 2006.182.07:40:08.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:08.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:08.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.07:40:08.05#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:08.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:08.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:08.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:08.16#ibcon#enter wrdev, iclass 21, count 0 2006.182.07:40:08.16#ibcon#first serial, iclass 21, count 0 2006.182.07:40:08.16#ibcon#enter sib2, iclass 21, count 0 2006.182.07:40:08.16#ibcon#flushed, iclass 21, count 0 2006.182.07:40:08.16#ibcon#about to write, iclass 21, count 0 2006.182.07:40:08.16#ibcon#wrote, iclass 21, count 0 2006.182.07:40:08.16#ibcon#about to read 3, iclass 21, count 0 2006.182.07:40:08.18#ibcon#read 3, iclass 21, count 0 2006.182.07:40:08.18#ibcon#about to read 4, iclass 21, count 0 2006.182.07:40:08.18#ibcon#read 4, iclass 21, count 0 2006.182.07:40:08.18#ibcon#about to read 5, iclass 21, count 0 2006.182.07:40:08.18#ibcon#read 5, iclass 21, count 0 2006.182.07:40:08.18#ibcon#about to read 6, iclass 21, count 0 2006.182.07:40:08.18#ibcon#read 6, iclass 21, count 0 2006.182.07:40:08.18#ibcon#end of sib2, iclass 21, count 0 2006.182.07:40:08.18#ibcon#*mode == 0, iclass 21, count 0 2006.182.07:40:08.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.07:40:08.18#ibcon#[25=USB\r\n] 2006.182.07:40:08.18#ibcon#*before write, iclass 21, count 0 2006.182.07:40:08.18#ibcon#enter sib2, iclass 21, count 0 2006.182.07:40:08.18#ibcon#flushed, iclass 21, count 0 2006.182.07:40:08.18#ibcon#about to write, iclass 21, count 0 2006.182.07:40:08.18#ibcon#wrote, iclass 21, count 0 2006.182.07:40:08.18#ibcon#about to read 3, iclass 21, count 0 2006.182.07:40:08.21#ibcon#read 3, iclass 21, count 0 2006.182.07:40:08.21#ibcon#about to read 4, iclass 21, count 0 2006.182.07:40:08.21#ibcon#read 4, iclass 21, count 0 2006.182.07:40:08.21#ibcon#about to read 5, iclass 21, count 0 2006.182.07:40:08.21#ibcon#read 5, iclass 21, count 0 2006.182.07:40:08.21#ibcon#about to read 6, iclass 21, count 0 2006.182.07:40:08.21#ibcon#read 6, iclass 21, count 0 2006.182.07:40:08.21#ibcon#end of sib2, iclass 21, count 0 2006.182.07:40:08.21#ibcon#*after write, iclass 21, count 0 2006.182.07:40:08.21#ibcon#*before return 0, iclass 21, count 0 2006.182.07:40:08.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:08.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:08.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.07:40:08.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.07:40:08.21$vc4f8/valo=2,572.99 2006.182.07:40:08.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.07:40:08.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.07:40:08.21#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:08.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:08.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:08.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:08.21#ibcon#enter wrdev, iclass 23, count 0 2006.182.07:40:08.21#ibcon#first serial, iclass 23, count 0 2006.182.07:40:08.21#ibcon#enter sib2, iclass 23, count 0 2006.182.07:40:08.21#ibcon#flushed, iclass 23, count 0 2006.182.07:40:08.21#ibcon#about to write, iclass 23, count 0 2006.182.07:40:08.21#ibcon#wrote, iclass 23, count 0 2006.182.07:40:08.21#ibcon#about to read 3, iclass 23, count 0 2006.182.07:40:08.24#ibcon#read 3, iclass 23, count 0 2006.182.07:40:08.24#ibcon#about to read 4, iclass 23, count 0 2006.182.07:40:08.24#ibcon#read 4, iclass 23, count 0 2006.182.07:40:08.24#ibcon#about to read 5, iclass 23, count 0 2006.182.07:40:08.24#ibcon#read 5, iclass 23, count 0 2006.182.07:40:08.24#ibcon#about to read 6, iclass 23, count 0 2006.182.07:40:08.24#ibcon#read 6, iclass 23, count 0 2006.182.07:40:08.24#ibcon#end of sib2, iclass 23, count 0 2006.182.07:40:08.24#ibcon#*mode == 0, iclass 23, count 0 2006.182.07:40:08.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.07:40:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:40:08.24#ibcon#*before write, iclass 23, count 0 2006.182.07:40:08.24#ibcon#enter sib2, iclass 23, count 0 2006.182.07:40:08.24#ibcon#flushed, iclass 23, count 0 2006.182.07:40:08.24#ibcon#about to write, iclass 23, count 0 2006.182.07:40:08.24#ibcon#wrote, iclass 23, count 0 2006.182.07:40:08.24#ibcon#about to read 3, iclass 23, count 0 2006.182.07:40:08.28#ibcon#read 3, iclass 23, count 0 2006.182.07:40:08.28#ibcon#about to read 4, iclass 23, count 0 2006.182.07:40:08.28#ibcon#read 4, iclass 23, count 0 2006.182.07:40:08.28#ibcon#about to read 5, iclass 23, count 0 2006.182.07:40:08.28#ibcon#read 5, iclass 23, count 0 2006.182.07:40:08.28#ibcon#about to read 6, iclass 23, count 0 2006.182.07:40:08.28#ibcon#read 6, iclass 23, count 0 2006.182.07:40:08.28#ibcon#end of sib2, iclass 23, count 0 2006.182.07:40:08.28#ibcon#*after write, iclass 23, count 0 2006.182.07:40:08.28#ibcon#*before return 0, iclass 23, count 0 2006.182.07:40:08.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:08.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:08.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.07:40:08.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.07:40:08.28$vc4f8/va=2,7 2006.182.07:40:08.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.07:40:08.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.07:40:08.28#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:08.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:08.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:08.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:08.33#ibcon#enter wrdev, iclass 25, count 2 2006.182.07:40:08.33#ibcon#first serial, iclass 25, count 2 2006.182.07:40:08.33#ibcon#enter sib2, iclass 25, count 2 2006.182.07:40:08.33#ibcon#flushed, iclass 25, count 2 2006.182.07:40:08.33#ibcon#about to write, iclass 25, count 2 2006.182.07:40:08.33#ibcon#wrote, iclass 25, count 2 2006.182.07:40:08.33#ibcon#about to read 3, iclass 25, count 2 2006.182.07:40:08.35#ibcon#read 3, iclass 25, count 2 2006.182.07:40:08.35#ibcon#about to read 4, iclass 25, count 2 2006.182.07:40:08.35#ibcon#read 4, iclass 25, count 2 2006.182.07:40:08.35#ibcon#about to read 5, iclass 25, count 2 2006.182.07:40:08.35#ibcon#read 5, iclass 25, count 2 2006.182.07:40:08.35#ibcon#about to read 6, iclass 25, count 2 2006.182.07:40:08.35#ibcon#read 6, iclass 25, count 2 2006.182.07:40:08.35#ibcon#end of sib2, iclass 25, count 2 2006.182.07:40:08.35#ibcon#*mode == 0, iclass 25, count 2 2006.182.07:40:08.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.07:40:08.35#ibcon#[25=AT02-07\r\n] 2006.182.07:40:08.35#ibcon#*before write, iclass 25, count 2 2006.182.07:40:08.35#ibcon#enter sib2, iclass 25, count 2 2006.182.07:40:08.35#ibcon#flushed, iclass 25, count 2 2006.182.07:40:08.35#ibcon#about to write, iclass 25, count 2 2006.182.07:40:08.35#ibcon#wrote, iclass 25, count 2 2006.182.07:40:08.35#ibcon#about to read 3, iclass 25, count 2 2006.182.07:40:08.38#ibcon#read 3, iclass 25, count 2 2006.182.07:40:08.38#ibcon#about to read 4, iclass 25, count 2 2006.182.07:40:08.38#ibcon#read 4, iclass 25, count 2 2006.182.07:40:08.38#ibcon#about to read 5, iclass 25, count 2 2006.182.07:40:08.38#ibcon#read 5, iclass 25, count 2 2006.182.07:40:08.38#ibcon#about to read 6, iclass 25, count 2 2006.182.07:40:08.38#ibcon#read 6, iclass 25, count 2 2006.182.07:40:08.38#ibcon#end of sib2, iclass 25, count 2 2006.182.07:40:08.38#ibcon#*after write, iclass 25, count 2 2006.182.07:40:08.38#ibcon#*before return 0, iclass 25, count 2 2006.182.07:40:08.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:08.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:08.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.07:40:08.38#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:08.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:08.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:08.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:08.50#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:40:08.50#ibcon#first serial, iclass 25, count 0 2006.182.07:40:08.50#ibcon#enter sib2, iclass 25, count 0 2006.182.07:40:08.50#ibcon#flushed, iclass 25, count 0 2006.182.07:40:08.50#ibcon#about to write, iclass 25, count 0 2006.182.07:40:08.50#ibcon#wrote, iclass 25, count 0 2006.182.07:40:08.50#ibcon#about to read 3, iclass 25, count 0 2006.182.07:40:08.52#ibcon#read 3, iclass 25, count 0 2006.182.07:40:08.52#ibcon#about to read 4, iclass 25, count 0 2006.182.07:40:08.52#ibcon#read 4, iclass 25, count 0 2006.182.07:40:08.52#ibcon#about to read 5, iclass 25, count 0 2006.182.07:40:08.52#ibcon#read 5, iclass 25, count 0 2006.182.07:40:08.52#ibcon#about to read 6, iclass 25, count 0 2006.182.07:40:08.52#ibcon#read 6, iclass 25, count 0 2006.182.07:40:08.52#ibcon#end of sib2, iclass 25, count 0 2006.182.07:40:08.52#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:40:08.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:40:08.52#ibcon#[25=USB\r\n] 2006.182.07:40:08.52#ibcon#*before write, iclass 25, count 0 2006.182.07:40:08.52#ibcon#enter sib2, iclass 25, count 0 2006.182.07:40:08.52#ibcon#flushed, iclass 25, count 0 2006.182.07:40:08.52#ibcon#about to write, iclass 25, count 0 2006.182.07:40:08.52#ibcon#wrote, iclass 25, count 0 2006.182.07:40:08.52#ibcon#about to read 3, iclass 25, count 0 2006.182.07:40:08.55#ibcon#read 3, iclass 25, count 0 2006.182.07:40:08.55#ibcon#about to read 4, iclass 25, count 0 2006.182.07:40:08.55#ibcon#read 4, iclass 25, count 0 2006.182.07:40:08.55#ibcon#about to read 5, iclass 25, count 0 2006.182.07:40:08.55#ibcon#read 5, iclass 25, count 0 2006.182.07:40:08.55#ibcon#about to read 6, iclass 25, count 0 2006.182.07:40:08.55#ibcon#read 6, iclass 25, count 0 2006.182.07:40:08.55#ibcon#end of sib2, iclass 25, count 0 2006.182.07:40:08.55#ibcon#*after write, iclass 25, count 0 2006.182.07:40:08.55#ibcon#*before return 0, iclass 25, count 0 2006.182.07:40:08.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:08.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:08.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:40:08.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:40:08.55$vc4f8/valo=3,672.99 2006.182.07:40:08.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.07:40:08.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.07:40:08.55#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:08.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:08.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:08.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:08.55#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:40:08.55#ibcon#first serial, iclass 27, count 0 2006.182.07:40:08.55#ibcon#enter sib2, iclass 27, count 0 2006.182.07:40:08.55#ibcon#flushed, iclass 27, count 0 2006.182.07:40:08.55#ibcon#about to write, iclass 27, count 0 2006.182.07:40:08.55#ibcon#wrote, iclass 27, count 0 2006.182.07:40:08.55#ibcon#about to read 3, iclass 27, count 0 2006.182.07:40:08.57#ibcon#read 3, iclass 27, count 0 2006.182.07:40:08.57#ibcon#about to read 4, iclass 27, count 0 2006.182.07:40:08.57#ibcon#read 4, iclass 27, count 0 2006.182.07:40:08.57#ibcon#about to read 5, iclass 27, count 0 2006.182.07:40:08.57#ibcon#read 5, iclass 27, count 0 2006.182.07:40:08.57#ibcon#about to read 6, iclass 27, count 0 2006.182.07:40:08.57#ibcon#read 6, iclass 27, count 0 2006.182.07:40:08.57#ibcon#end of sib2, iclass 27, count 0 2006.182.07:40:08.57#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:40:08.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:40:08.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:40:08.57#ibcon#*before write, iclass 27, count 0 2006.182.07:40:08.57#ibcon#enter sib2, iclass 27, count 0 2006.182.07:40:08.57#ibcon#flushed, iclass 27, count 0 2006.182.07:40:08.57#ibcon#about to write, iclass 27, count 0 2006.182.07:40:08.57#ibcon#wrote, iclass 27, count 0 2006.182.07:40:08.57#ibcon#about to read 3, iclass 27, count 0 2006.182.07:40:08.61#ibcon#read 3, iclass 27, count 0 2006.182.07:40:08.61#ibcon#about to read 4, iclass 27, count 0 2006.182.07:40:08.61#ibcon#read 4, iclass 27, count 0 2006.182.07:40:08.61#ibcon#about to read 5, iclass 27, count 0 2006.182.07:40:08.61#ibcon#read 5, iclass 27, count 0 2006.182.07:40:08.61#ibcon#about to read 6, iclass 27, count 0 2006.182.07:40:08.61#ibcon#read 6, iclass 27, count 0 2006.182.07:40:08.61#ibcon#end of sib2, iclass 27, count 0 2006.182.07:40:08.61#ibcon#*after write, iclass 27, count 0 2006.182.07:40:08.61#ibcon#*before return 0, iclass 27, count 0 2006.182.07:40:08.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:08.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:08.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:40:08.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:40:08.61$vc4f8/va=3,6 2006.182.07:40:08.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.07:40:08.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.07:40:08.61#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:08.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:08.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:08.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:08.68#ibcon#enter wrdev, iclass 29, count 2 2006.182.07:40:08.68#ibcon#first serial, iclass 29, count 2 2006.182.07:40:08.68#ibcon#enter sib2, iclass 29, count 2 2006.182.07:40:08.68#ibcon#flushed, iclass 29, count 2 2006.182.07:40:08.68#ibcon#about to write, iclass 29, count 2 2006.182.07:40:08.68#ibcon#wrote, iclass 29, count 2 2006.182.07:40:08.68#ibcon#about to read 3, iclass 29, count 2 2006.182.07:40:08.69#ibcon#read 3, iclass 29, count 2 2006.182.07:40:08.69#ibcon#about to read 4, iclass 29, count 2 2006.182.07:40:08.69#ibcon#read 4, iclass 29, count 2 2006.182.07:40:08.69#ibcon#about to read 5, iclass 29, count 2 2006.182.07:40:08.69#ibcon#read 5, iclass 29, count 2 2006.182.07:40:08.69#ibcon#about to read 6, iclass 29, count 2 2006.182.07:40:08.69#ibcon#read 6, iclass 29, count 2 2006.182.07:40:08.69#ibcon#end of sib2, iclass 29, count 2 2006.182.07:40:08.69#ibcon#*mode == 0, iclass 29, count 2 2006.182.07:40:08.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.07:40:08.69#ibcon#[25=AT03-06\r\n] 2006.182.07:40:08.69#ibcon#*before write, iclass 29, count 2 2006.182.07:40:08.69#ibcon#enter sib2, iclass 29, count 2 2006.182.07:40:08.69#ibcon#flushed, iclass 29, count 2 2006.182.07:40:08.69#ibcon#about to write, iclass 29, count 2 2006.182.07:40:08.69#ibcon#wrote, iclass 29, count 2 2006.182.07:40:08.69#ibcon#about to read 3, iclass 29, count 2 2006.182.07:40:08.72#ibcon#read 3, iclass 29, count 2 2006.182.07:40:08.72#ibcon#about to read 4, iclass 29, count 2 2006.182.07:40:08.72#ibcon#read 4, iclass 29, count 2 2006.182.07:40:08.72#ibcon#about to read 5, iclass 29, count 2 2006.182.07:40:08.72#ibcon#read 5, iclass 29, count 2 2006.182.07:40:08.72#ibcon#about to read 6, iclass 29, count 2 2006.182.07:40:08.72#ibcon#read 6, iclass 29, count 2 2006.182.07:40:08.72#ibcon#end of sib2, iclass 29, count 2 2006.182.07:40:08.72#ibcon#*after write, iclass 29, count 2 2006.182.07:40:08.72#ibcon#*before return 0, iclass 29, count 2 2006.182.07:40:08.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:08.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:08.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.07:40:08.72#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:08.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:08.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:08.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:08.84#ibcon#enter wrdev, iclass 29, count 0 2006.182.07:40:08.84#ibcon#first serial, iclass 29, count 0 2006.182.07:40:08.84#ibcon#enter sib2, iclass 29, count 0 2006.182.07:40:08.84#ibcon#flushed, iclass 29, count 0 2006.182.07:40:08.84#ibcon#about to write, iclass 29, count 0 2006.182.07:40:08.84#ibcon#wrote, iclass 29, count 0 2006.182.07:40:08.84#ibcon#about to read 3, iclass 29, count 0 2006.182.07:40:08.86#ibcon#read 3, iclass 29, count 0 2006.182.07:40:08.86#ibcon#about to read 4, iclass 29, count 0 2006.182.07:40:08.86#ibcon#read 4, iclass 29, count 0 2006.182.07:40:08.86#ibcon#about to read 5, iclass 29, count 0 2006.182.07:40:08.86#ibcon#read 5, iclass 29, count 0 2006.182.07:40:08.86#ibcon#about to read 6, iclass 29, count 0 2006.182.07:40:08.86#ibcon#read 6, iclass 29, count 0 2006.182.07:40:08.86#ibcon#end of sib2, iclass 29, count 0 2006.182.07:40:08.86#ibcon#*mode == 0, iclass 29, count 0 2006.182.07:40:08.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.07:40:08.86#ibcon#[25=USB\r\n] 2006.182.07:40:08.86#ibcon#*before write, iclass 29, count 0 2006.182.07:40:08.86#ibcon#enter sib2, iclass 29, count 0 2006.182.07:40:08.86#ibcon#flushed, iclass 29, count 0 2006.182.07:40:08.86#ibcon#about to write, iclass 29, count 0 2006.182.07:40:08.86#ibcon#wrote, iclass 29, count 0 2006.182.07:40:08.86#ibcon#about to read 3, iclass 29, count 0 2006.182.07:40:08.89#ibcon#read 3, iclass 29, count 0 2006.182.07:40:08.89#ibcon#about to read 4, iclass 29, count 0 2006.182.07:40:08.89#ibcon#read 4, iclass 29, count 0 2006.182.07:40:08.89#ibcon#about to read 5, iclass 29, count 0 2006.182.07:40:08.89#ibcon#read 5, iclass 29, count 0 2006.182.07:40:08.89#ibcon#about to read 6, iclass 29, count 0 2006.182.07:40:08.89#ibcon#read 6, iclass 29, count 0 2006.182.07:40:08.89#ibcon#end of sib2, iclass 29, count 0 2006.182.07:40:08.89#ibcon#*after write, iclass 29, count 0 2006.182.07:40:08.89#ibcon#*before return 0, iclass 29, count 0 2006.182.07:40:08.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:08.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:08.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.07:40:08.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.07:40:08.89$vc4f8/valo=4,832.99 2006.182.07:40:08.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.07:40:08.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.07:40:08.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:08.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:08.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:08.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:08.89#ibcon#enter wrdev, iclass 31, count 0 2006.182.07:40:08.89#ibcon#first serial, iclass 31, count 0 2006.182.07:40:08.89#ibcon#enter sib2, iclass 31, count 0 2006.182.07:40:08.89#ibcon#flushed, iclass 31, count 0 2006.182.07:40:08.89#ibcon#about to write, iclass 31, count 0 2006.182.07:40:08.89#ibcon#wrote, iclass 31, count 0 2006.182.07:40:08.89#ibcon#about to read 3, iclass 31, count 0 2006.182.07:40:08.91#ibcon#read 3, iclass 31, count 0 2006.182.07:40:08.91#ibcon#about to read 4, iclass 31, count 0 2006.182.07:40:08.91#ibcon#read 4, iclass 31, count 0 2006.182.07:40:08.91#ibcon#about to read 5, iclass 31, count 0 2006.182.07:40:08.91#ibcon#read 5, iclass 31, count 0 2006.182.07:40:08.91#ibcon#about to read 6, iclass 31, count 0 2006.182.07:40:08.91#ibcon#read 6, iclass 31, count 0 2006.182.07:40:08.91#ibcon#end of sib2, iclass 31, count 0 2006.182.07:40:08.91#ibcon#*mode == 0, iclass 31, count 0 2006.182.07:40:08.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.07:40:08.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:40:08.91#ibcon#*before write, iclass 31, count 0 2006.182.07:40:08.91#ibcon#enter sib2, iclass 31, count 0 2006.182.07:40:08.91#ibcon#flushed, iclass 31, count 0 2006.182.07:40:08.91#ibcon#about to write, iclass 31, count 0 2006.182.07:40:08.91#ibcon#wrote, iclass 31, count 0 2006.182.07:40:08.91#ibcon#about to read 3, iclass 31, count 0 2006.182.07:40:08.95#ibcon#read 3, iclass 31, count 0 2006.182.07:40:08.95#ibcon#about to read 4, iclass 31, count 0 2006.182.07:40:08.95#ibcon#read 4, iclass 31, count 0 2006.182.07:40:08.95#ibcon#about to read 5, iclass 31, count 0 2006.182.07:40:08.95#ibcon#read 5, iclass 31, count 0 2006.182.07:40:08.95#ibcon#about to read 6, iclass 31, count 0 2006.182.07:40:08.95#ibcon#read 6, iclass 31, count 0 2006.182.07:40:08.95#ibcon#end of sib2, iclass 31, count 0 2006.182.07:40:08.95#ibcon#*after write, iclass 31, count 0 2006.182.07:40:08.95#ibcon#*before return 0, iclass 31, count 0 2006.182.07:40:08.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:08.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:08.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.07:40:08.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.07:40:08.95$vc4f8/va=4,7 2006.182.07:40:08.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.07:40:08.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.07:40:08.95#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:08.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:40:09.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:40:09.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:40:09.01#ibcon#enter wrdev, iclass 33, count 2 2006.182.07:40:09.01#ibcon#first serial, iclass 33, count 2 2006.182.07:40:09.01#ibcon#enter sib2, iclass 33, count 2 2006.182.07:40:09.01#ibcon#flushed, iclass 33, count 2 2006.182.07:40:09.01#ibcon#about to write, iclass 33, count 2 2006.182.07:40:09.01#ibcon#wrote, iclass 33, count 2 2006.182.07:40:09.01#ibcon#about to read 3, iclass 33, count 2 2006.182.07:40:09.03#ibcon#read 3, iclass 33, count 2 2006.182.07:40:09.03#ibcon#about to read 4, iclass 33, count 2 2006.182.07:40:09.03#ibcon#read 4, iclass 33, count 2 2006.182.07:40:09.03#ibcon#about to read 5, iclass 33, count 2 2006.182.07:40:09.03#ibcon#read 5, iclass 33, count 2 2006.182.07:40:09.03#ibcon#about to read 6, iclass 33, count 2 2006.182.07:40:09.03#ibcon#read 6, iclass 33, count 2 2006.182.07:40:09.03#ibcon#end of sib2, iclass 33, count 2 2006.182.07:40:09.03#ibcon#*mode == 0, iclass 33, count 2 2006.182.07:40:09.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.07:40:09.03#ibcon#[25=AT04-07\r\n] 2006.182.07:40:09.03#ibcon#*before write, iclass 33, count 2 2006.182.07:40:09.03#ibcon#enter sib2, iclass 33, count 2 2006.182.07:40:09.03#ibcon#flushed, iclass 33, count 2 2006.182.07:40:09.03#ibcon#about to write, iclass 33, count 2 2006.182.07:40:09.03#ibcon#wrote, iclass 33, count 2 2006.182.07:40:09.03#ibcon#about to read 3, iclass 33, count 2 2006.182.07:40:09.06#ibcon#read 3, iclass 33, count 2 2006.182.07:40:09.06#ibcon#about to read 4, iclass 33, count 2 2006.182.07:40:09.06#ibcon#read 4, iclass 33, count 2 2006.182.07:40:09.06#ibcon#about to read 5, iclass 33, count 2 2006.182.07:40:09.06#ibcon#read 5, iclass 33, count 2 2006.182.07:40:09.06#ibcon#about to read 6, iclass 33, count 2 2006.182.07:40:09.06#ibcon#read 6, iclass 33, count 2 2006.182.07:40:09.06#ibcon#end of sib2, iclass 33, count 2 2006.182.07:40:09.06#ibcon#*after write, iclass 33, count 2 2006.182.07:40:09.06#ibcon#*before return 0, iclass 33, count 2 2006.182.07:40:09.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:40:09.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:40:09.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.07:40:09.06#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:09.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:40:09.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:40:09.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:40:09.18#ibcon#enter wrdev, iclass 33, count 0 2006.182.07:40:09.18#ibcon#first serial, iclass 33, count 0 2006.182.07:40:09.18#ibcon#enter sib2, iclass 33, count 0 2006.182.07:40:09.18#ibcon#flushed, iclass 33, count 0 2006.182.07:40:09.18#ibcon#about to write, iclass 33, count 0 2006.182.07:40:09.18#ibcon#wrote, iclass 33, count 0 2006.182.07:40:09.18#ibcon#about to read 3, iclass 33, count 0 2006.182.07:40:09.20#ibcon#read 3, iclass 33, count 0 2006.182.07:40:09.20#ibcon#about to read 4, iclass 33, count 0 2006.182.07:40:09.20#ibcon#read 4, iclass 33, count 0 2006.182.07:40:09.20#ibcon#about to read 5, iclass 33, count 0 2006.182.07:40:09.20#ibcon#read 5, iclass 33, count 0 2006.182.07:40:09.20#ibcon#about to read 6, iclass 33, count 0 2006.182.07:40:09.20#ibcon#read 6, iclass 33, count 0 2006.182.07:40:09.20#ibcon#end of sib2, iclass 33, count 0 2006.182.07:40:09.20#ibcon#*mode == 0, iclass 33, count 0 2006.182.07:40:09.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.07:40:09.20#ibcon#[25=USB\r\n] 2006.182.07:40:09.20#ibcon#*before write, iclass 33, count 0 2006.182.07:40:09.20#ibcon#enter sib2, iclass 33, count 0 2006.182.07:40:09.20#ibcon#flushed, iclass 33, count 0 2006.182.07:40:09.20#ibcon#about to write, iclass 33, count 0 2006.182.07:40:09.20#ibcon#wrote, iclass 33, count 0 2006.182.07:40:09.20#ibcon#about to read 3, iclass 33, count 0 2006.182.07:40:09.23#ibcon#read 3, iclass 33, count 0 2006.182.07:40:09.23#ibcon#about to read 4, iclass 33, count 0 2006.182.07:40:09.23#ibcon#read 4, iclass 33, count 0 2006.182.07:40:09.23#ibcon#about to read 5, iclass 33, count 0 2006.182.07:40:09.23#ibcon#read 5, iclass 33, count 0 2006.182.07:40:09.23#ibcon#about to read 6, iclass 33, count 0 2006.182.07:40:09.23#ibcon#read 6, iclass 33, count 0 2006.182.07:40:09.23#ibcon#end of sib2, iclass 33, count 0 2006.182.07:40:09.23#ibcon#*after write, iclass 33, count 0 2006.182.07:40:09.23#ibcon#*before return 0, iclass 33, count 0 2006.182.07:40:09.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:40:09.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:40:09.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.07:40:09.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.07:40:09.23$vc4f8/valo=5,652.99 2006.182.07:40:09.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.07:40:09.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.07:40:09.23#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:09.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:40:09.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:40:09.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:40:09.23#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:40:09.23#ibcon#first serial, iclass 35, count 0 2006.182.07:40:09.23#ibcon#enter sib2, iclass 35, count 0 2006.182.07:40:09.23#ibcon#flushed, iclass 35, count 0 2006.182.07:40:09.23#ibcon#about to write, iclass 35, count 0 2006.182.07:40:09.23#ibcon#wrote, iclass 35, count 0 2006.182.07:40:09.23#ibcon#about to read 3, iclass 35, count 0 2006.182.07:40:09.25#ibcon#read 3, iclass 35, count 0 2006.182.07:40:09.25#ibcon#about to read 4, iclass 35, count 0 2006.182.07:40:09.25#ibcon#read 4, iclass 35, count 0 2006.182.07:40:09.25#ibcon#about to read 5, iclass 35, count 0 2006.182.07:40:09.25#ibcon#read 5, iclass 35, count 0 2006.182.07:40:09.25#ibcon#about to read 6, iclass 35, count 0 2006.182.07:40:09.25#ibcon#read 6, iclass 35, count 0 2006.182.07:40:09.25#ibcon#end of sib2, iclass 35, count 0 2006.182.07:40:09.25#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:40:09.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:40:09.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:40:09.25#ibcon#*before write, iclass 35, count 0 2006.182.07:40:09.25#ibcon#enter sib2, iclass 35, count 0 2006.182.07:40:09.25#ibcon#flushed, iclass 35, count 0 2006.182.07:40:09.25#ibcon#about to write, iclass 35, count 0 2006.182.07:40:09.25#ibcon#wrote, iclass 35, count 0 2006.182.07:40:09.25#ibcon#about to read 3, iclass 35, count 0 2006.182.07:40:09.29#ibcon#read 3, iclass 35, count 0 2006.182.07:40:09.29#ibcon#about to read 4, iclass 35, count 0 2006.182.07:40:09.29#ibcon#read 4, iclass 35, count 0 2006.182.07:40:09.29#ibcon#about to read 5, iclass 35, count 0 2006.182.07:40:09.29#ibcon#read 5, iclass 35, count 0 2006.182.07:40:09.29#ibcon#about to read 6, iclass 35, count 0 2006.182.07:40:09.29#ibcon#read 6, iclass 35, count 0 2006.182.07:40:09.29#ibcon#end of sib2, iclass 35, count 0 2006.182.07:40:09.29#ibcon#*after write, iclass 35, count 0 2006.182.07:40:09.29#ibcon#*before return 0, iclass 35, count 0 2006.182.07:40:09.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:40:09.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:40:09.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:40:09.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:40:09.29$vc4f8/va=5,7 2006.182.07:40:09.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.07:40:09.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.07:40:09.29#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:09.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:40:09.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:40:09.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:40:09.35#ibcon#enter wrdev, iclass 37, count 2 2006.182.07:40:09.35#ibcon#first serial, iclass 37, count 2 2006.182.07:40:09.35#ibcon#enter sib2, iclass 37, count 2 2006.182.07:40:09.35#ibcon#flushed, iclass 37, count 2 2006.182.07:40:09.35#ibcon#about to write, iclass 37, count 2 2006.182.07:40:09.35#ibcon#wrote, iclass 37, count 2 2006.182.07:40:09.35#ibcon#about to read 3, iclass 37, count 2 2006.182.07:40:09.37#ibcon#read 3, iclass 37, count 2 2006.182.07:40:09.37#ibcon#about to read 4, iclass 37, count 2 2006.182.07:40:09.37#ibcon#read 4, iclass 37, count 2 2006.182.07:40:09.37#ibcon#about to read 5, iclass 37, count 2 2006.182.07:40:09.37#ibcon#read 5, iclass 37, count 2 2006.182.07:40:09.37#ibcon#about to read 6, iclass 37, count 2 2006.182.07:40:09.37#ibcon#read 6, iclass 37, count 2 2006.182.07:40:09.37#ibcon#end of sib2, iclass 37, count 2 2006.182.07:40:09.37#ibcon#*mode == 0, iclass 37, count 2 2006.182.07:40:09.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.07:40:09.37#ibcon#[25=AT05-07\r\n] 2006.182.07:40:09.37#ibcon#*before write, iclass 37, count 2 2006.182.07:40:09.37#ibcon#enter sib2, iclass 37, count 2 2006.182.07:40:09.37#ibcon#flushed, iclass 37, count 2 2006.182.07:40:09.37#ibcon#about to write, iclass 37, count 2 2006.182.07:40:09.37#ibcon#wrote, iclass 37, count 2 2006.182.07:40:09.37#ibcon#about to read 3, iclass 37, count 2 2006.182.07:40:09.40#ibcon#read 3, iclass 37, count 2 2006.182.07:40:09.40#ibcon#about to read 4, iclass 37, count 2 2006.182.07:40:09.40#ibcon#read 4, iclass 37, count 2 2006.182.07:40:09.40#ibcon#about to read 5, iclass 37, count 2 2006.182.07:40:09.40#ibcon#read 5, iclass 37, count 2 2006.182.07:40:09.40#ibcon#about to read 6, iclass 37, count 2 2006.182.07:40:09.40#ibcon#read 6, iclass 37, count 2 2006.182.07:40:09.40#ibcon#end of sib2, iclass 37, count 2 2006.182.07:40:09.40#ibcon#*after write, iclass 37, count 2 2006.182.07:40:09.40#ibcon#*before return 0, iclass 37, count 2 2006.182.07:40:09.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:40:09.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:40:09.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.07:40:09.40#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:09.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:40:09.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:40:09.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:40:09.52#ibcon#enter wrdev, iclass 37, count 0 2006.182.07:40:09.52#ibcon#first serial, iclass 37, count 0 2006.182.07:40:09.52#ibcon#enter sib2, iclass 37, count 0 2006.182.07:40:09.52#ibcon#flushed, iclass 37, count 0 2006.182.07:40:09.52#ibcon#about to write, iclass 37, count 0 2006.182.07:40:09.52#ibcon#wrote, iclass 37, count 0 2006.182.07:40:09.52#ibcon#about to read 3, iclass 37, count 0 2006.182.07:40:09.54#ibcon#read 3, iclass 37, count 0 2006.182.07:40:09.54#ibcon#about to read 4, iclass 37, count 0 2006.182.07:40:09.54#ibcon#read 4, iclass 37, count 0 2006.182.07:40:09.54#ibcon#about to read 5, iclass 37, count 0 2006.182.07:40:09.54#ibcon#read 5, iclass 37, count 0 2006.182.07:40:09.54#ibcon#about to read 6, iclass 37, count 0 2006.182.07:40:09.54#ibcon#read 6, iclass 37, count 0 2006.182.07:40:09.54#ibcon#end of sib2, iclass 37, count 0 2006.182.07:40:09.54#ibcon#*mode == 0, iclass 37, count 0 2006.182.07:40:09.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.07:40:09.54#ibcon#[25=USB\r\n] 2006.182.07:40:09.54#ibcon#*before write, iclass 37, count 0 2006.182.07:40:09.54#ibcon#enter sib2, iclass 37, count 0 2006.182.07:40:09.54#ibcon#flushed, iclass 37, count 0 2006.182.07:40:09.54#ibcon#about to write, iclass 37, count 0 2006.182.07:40:09.54#ibcon#wrote, iclass 37, count 0 2006.182.07:40:09.54#ibcon#about to read 3, iclass 37, count 0 2006.182.07:40:09.57#ibcon#read 3, iclass 37, count 0 2006.182.07:40:09.57#ibcon#about to read 4, iclass 37, count 0 2006.182.07:40:09.57#ibcon#read 4, iclass 37, count 0 2006.182.07:40:09.57#ibcon#about to read 5, iclass 37, count 0 2006.182.07:40:09.57#ibcon#read 5, iclass 37, count 0 2006.182.07:40:09.57#ibcon#about to read 6, iclass 37, count 0 2006.182.07:40:09.57#ibcon#read 6, iclass 37, count 0 2006.182.07:40:09.57#ibcon#end of sib2, iclass 37, count 0 2006.182.07:40:09.57#ibcon#*after write, iclass 37, count 0 2006.182.07:40:09.57#ibcon#*before return 0, iclass 37, count 0 2006.182.07:40:09.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:40:09.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:40:09.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.07:40:09.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.07:40:09.57$vc4f8/valo=6,772.99 2006.182.07:40:09.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.07:40:09.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.07:40:09.57#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:09.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:09.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:09.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:09.57#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:40:09.57#ibcon#first serial, iclass 39, count 0 2006.182.07:40:09.57#ibcon#enter sib2, iclass 39, count 0 2006.182.07:40:09.57#ibcon#flushed, iclass 39, count 0 2006.182.07:40:09.57#ibcon#about to write, iclass 39, count 0 2006.182.07:40:09.57#ibcon#wrote, iclass 39, count 0 2006.182.07:40:09.57#ibcon#about to read 3, iclass 39, count 0 2006.182.07:40:09.60#ibcon#read 3, iclass 39, count 0 2006.182.07:40:09.60#ibcon#about to read 4, iclass 39, count 0 2006.182.07:40:09.60#ibcon#read 4, iclass 39, count 0 2006.182.07:40:09.60#ibcon#about to read 5, iclass 39, count 0 2006.182.07:40:09.60#ibcon#read 5, iclass 39, count 0 2006.182.07:40:09.60#ibcon#about to read 6, iclass 39, count 0 2006.182.07:40:09.60#ibcon#read 6, iclass 39, count 0 2006.182.07:40:09.60#ibcon#end of sib2, iclass 39, count 0 2006.182.07:40:09.60#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:40:09.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:40:09.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:40:09.60#ibcon#*before write, iclass 39, count 0 2006.182.07:40:09.60#ibcon#enter sib2, iclass 39, count 0 2006.182.07:40:09.60#ibcon#flushed, iclass 39, count 0 2006.182.07:40:09.60#ibcon#about to write, iclass 39, count 0 2006.182.07:40:09.60#ibcon#wrote, iclass 39, count 0 2006.182.07:40:09.60#ibcon#about to read 3, iclass 39, count 0 2006.182.07:40:09.64#ibcon#read 3, iclass 39, count 0 2006.182.07:40:09.64#ibcon#about to read 4, iclass 39, count 0 2006.182.07:40:09.64#ibcon#read 4, iclass 39, count 0 2006.182.07:40:09.64#ibcon#about to read 5, iclass 39, count 0 2006.182.07:40:09.64#ibcon#read 5, iclass 39, count 0 2006.182.07:40:09.64#ibcon#about to read 6, iclass 39, count 0 2006.182.07:40:09.64#ibcon#read 6, iclass 39, count 0 2006.182.07:40:09.64#ibcon#end of sib2, iclass 39, count 0 2006.182.07:40:09.64#ibcon#*after write, iclass 39, count 0 2006.182.07:40:09.64#ibcon#*before return 0, iclass 39, count 0 2006.182.07:40:09.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:09.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:09.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:40:09.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:40:09.64$vc4f8/va=6,6 2006.182.07:40:09.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.07:40:09.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.07:40:09.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:09.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:09.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:09.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:09.69#ibcon#enter wrdev, iclass 3, count 2 2006.182.07:40:09.69#ibcon#first serial, iclass 3, count 2 2006.182.07:40:09.69#ibcon#enter sib2, iclass 3, count 2 2006.182.07:40:09.69#ibcon#flushed, iclass 3, count 2 2006.182.07:40:09.69#ibcon#about to write, iclass 3, count 2 2006.182.07:40:09.69#ibcon#wrote, iclass 3, count 2 2006.182.07:40:09.69#ibcon#about to read 3, iclass 3, count 2 2006.182.07:40:09.71#ibcon#read 3, iclass 3, count 2 2006.182.07:40:09.71#ibcon#about to read 4, iclass 3, count 2 2006.182.07:40:09.71#ibcon#read 4, iclass 3, count 2 2006.182.07:40:09.71#ibcon#about to read 5, iclass 3, count 2 2006.182.07:40:09.71#ibcon#read 5, iclass 3, count 2 2006.182.07:40:09.71#ibcon#about to read 6, iclass 3, count 2 2006.182.07:40:09.71#ibcon#read 6, iclass 3, count 2 2006.182.07:40:09.71#ibcon#end of sib2, iclass 3, count 2 2006.182.07:40:09.71#ibcon#*mode == 0, iclass 3, count 2 2006.182.07:40:09.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.07:40:09.71#ibcon#[25=AT06-06\r\n] 2006.182.07:40:09.71#ibcon#*before write, iclass 3, count 2 2006.182.07:40:09.71#ibcon#enter sib2, iclass 3, count 2 2006.182.07:40:09.71#ibcon#flushed, iclass 3, count 2 2006.182.07:40:09.71#ibcon#about to write, iclass 3, count 2 2006.182.07:40:09.71#ibcon#wrote, iclass 3, count 2 2006.182.07:40:09.71#ibcon#about to read 3, iclass 3, count 2 2006.182.07:40:09.74#ibcon#read 3, iclass 3, count 2 2006.182.07:40:09.74#ibcon#about to read 4, iclass 3, count 2 2006.182.07:40:09.74#ibcon#read 4, iclass 3, count 2 2006.182.07:40:09.74#ibcon#about to read 5, iclass 3, count 2 2006.182.07:40:09.74#ibcon#read 5, iclass 3, count 2 2006.182.07:40:09.74#ibcon#about to read 6, iclass 3, count 2 2006.182.07:40:09.74#ibcon#read 6, iclass 3, count 2 2006.182.07:40:09.74#ibcon#end of sib2, iclass 3, count 2 2006.182.07:40:09.74#ibcon#*after write, iclass 3, count 2 2006.182.07:40:09.74#ibcon#*before return 0, iclass 3, count 2 2006.182.07:40:09.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:09.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:09.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.07:40:09.74#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:09.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:09.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:09.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:09.86#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:40:09.86#ibcon#first serial, iclass 3, count 0 2006.182.07:40:09.86#ibcon#enter sib2, iclass 3, count 0 2006.182.07:40:09.86#ibcon#flushed, iclass 3, count 0 2006.182.07:40:09.86#ibcon#about to write, iclass 3, count 0 2006.182.07:40:09.86#ibcon#wrote, iclass 3, count 0 2006.182.07:40:09.86#ibcon#about to read 3, iclass 3, count 0 2006.182.07:40:09.88#ibcon#read 3, iclass 3, count 0 2006.182.07:40:09.88#ibcon#about to read 4, iclass 3, count 0 2006.182.07:40:09.88#ibcon#read 4, iclass 3, count 0 2006.182.07:40:09.88#ibcon#about to read 5, iclass 3, count 0 2006.182.07:40:09.88#ibcon#read 5, iclass 3, count 0 2006.182.07:40:09.88#ibcon#about to read 6, iclass 3, count 0 2006.182.07:40:09.88#ibcon#read 6, iclass 3, count 0 2006.182.07:40:09.88#ibcon#end of sib2, iclass 3, count 0 2006.182.07:40:09.88#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:40:09.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:40:09.88#ibcon#[25=USB\r\n] 2006.182.07:40:09.88#ibcon#*before write, iclass 3, count 0 2006.182.07:40:09.88#ibcon#enter sib2, iclass 3, count 0 2006.182.07:40:09.88#ibcon#flushed, iclass 3, count 0 2006.182.07:40:09.88#ibcon#about to write, iclass 3, count 0 2006.182.07:40:09.88#ibcon#wrote, iclass 3, count 0 2006.182.07:40:09.88#ibcon#about to read 3, iclass 3, count 0 2006.182.07:40:09.91#ibcon#read 3, iclass 3, count 0 2006.182.07:40:09.91#ibcon#about to read 4, iclass 3, count 0 2006.182.07:40:09.91#ibcon#read 4, iclass 3, count 0 2006.182.07:40:09.91#ibcon#about to read 5, iclass 3, count 0 2006.182.07:40:09.91#ibcon#read 5, iclass 3, count 0 2006.182.07:40:09.91#ibcon#about to read 6, iclass 3, count 0 2006.182.07:40:09.91#ibcon#read 6, iclass 3, count 0 2006.182.07:40:09.91#ibcon#end of sib2, iclass 3, count 0 2006.182.07:40:09.91#ibcon#*after write, iclass 3, count 0 2006.182.07:40:09.91#ibcon#*before return 0, iclass 3, count 0 2006.182.07:40:09.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:09.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:09.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:40:09.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:40:09.91$vc4f8/valo=7,832.99 2006.182.07:40:09.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.07:40:09.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.07:40:09.91#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:09.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:09.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:09.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:09.91#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:40:09.91#ibcon#first serial, iclass 5, count 0 2006.182.07:40:09.91#ibcon#enter sib2, iclass 5, count 0 2006.182.07:40:09.91#ibcon#flushed, iclass 5, count 0 2006.182.07:40:09.91#ibcon#about to write, iclass 5, count 0 2006.182.07:40:09.91#ibcon#wrote, iclass 5, count 0 2006.182.07:40:09.91#ibcon#about to read 3, iclass 5, count 0 2006.182.07:40:09.93#ibcon#read 3, iclass 5, count 0 2006.182.07:40:09.93#ibcon#about to read 4, iclass 5, count 0 2006.182.07:40:09.93#ibcon#read 4, iclass 5, count 0 2006.182.07:40:09.93#ibcon#about to read 5, iclass 5, count 0 2006.182.07:40:09.93#ibcon#read 5, iclass 5, count 0 2006.182.07:40:09.93#ibcon#about to read 6, iclass 5, count 0 2006.182.07:40:09.93#ibcon#read 6, iclass 5, count 0 2006.182.07:40:09.93#ibcon#end of sib2, iclass 5, count 0 2006.182.07:40:09.93#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:40:09.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:40:09.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:40:09.93#ibcon#*before write, iclass 5, count 0 2006.182.07:40:09.93#ibcon#enter sib2, iclass 5, count 0 2006.182.07:40:09.93#ibcon#flushed, iclass 5, count 0 2006.182.07:40:09.93#ibcon#about to write, iclass 5, count 0 2006.182.07:40:09.93#ibcon#wrote, iclass 5, count 0 2006.182.07:40:09.93#ibcon#about to read 3, iclass 5, count 0 2006.182.07:40:09.97#ibcon#read 3, iclass 5, count 0 2006.182.07:40:09.97#ibcon#about to read 4, iclass 5, count 0 2006.182.07:40:09.97#ibcon#read 4, iclass 5, count 0 2006.182.07:40:09.97#ibcon#about to read 5, iclass 5, count 0 2006.182.07:40:09.97#ibcon#read 5, iclass 5, count 0 2006.182.07:40:09.97#ibcon#about to read 6, iclass 5, count 0 2006.182.07:40:09.97#ibcon#read 6, iclass 5, count 0 2006.182.07:40:09.97#ibcon#end of sib2, iclass 5, count 0 2006.182.07:40:09.97#ibcon#*after write, iclass 5, count 0 2006.182.07:40:09.97#ibcon#*before return 0, iclass 5, count 0 2006.182.07:40:09.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:09.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:09.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:40:09.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:40:09.97$vc4f8/va=7,6 2006.182.07:40:09.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.07:40:09.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.07:40:09.97#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:09.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:40:10.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:40:10.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:40:10.03#ibcon#enter wrdev, iclass 7, count 2 2006.182.07:40:10.03#ibcon#first serial, iclass 7, count 2 2006.182.07:40:10.03#ibcon#enter sib2, iclass 7, count 2 2006.182.07:40:10.03#ibcon#flushed, iclass 7, count 2 2006.182.07:40:10.03#ibcon#about to write, iclass 7, count 2 2006.182.07:40:10.03#ibcon#wrote, iclass 7, count 2 2006.182.07:40:10.03#ibcon#about to read 3, iclass 7, count 2 2006.182.07:40:10.05#ibcon#read 3, iclass 7, count 2 2006.182.07:40:10.05#ibcon#about to read 4, iclass 7, count 2 2006.182.07:40:10.05#ibcon#read 4, iclass 7, count 2 2006.182.07:40:10.05#ibcon#about to read 5, iclass 7, count 2 2006.182.07:40:10.05#ibcon#read 5, iclass 7, count 2 2006.182.07:40:10.05#ibcon#about to read 6, iclass 7, count 2 2006.182.07:40:10.05#ibcon#read 6, iclass 7, count 2 2006.182.07:40:10.05#ibcon#end of sib2, iclass 7, count 2 2006.182.07:40:10.05#ibcon#*mode == 0, iclass 7, count 2 2006.182.07:40:10.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.07:40:10.05#ibcon#[25=AT07-06\r\n] 2006.182.07:40:10.05#ibcon#*before write, iclass 7, count 2 2006.182.07:40:10.05#ibcon#enter sib2, iclass 7, count 2 2006.182.07:40:10.05#ibcon#flushed, iclass 7, count 2 2006.182.07:40:10.05#ibcon#about to write, iclass 7, count 2 2006.182.07:40:10.05#ibcon#wrote, iclass 7, count 2 2006.182.07:40:10.05#ibcon#about to read 3, iclass 7, count 2 2006.182.07:40:10.08#ibcon#read 3, iclass 7, count 2 2006.182.07:40:10.08#ibcon#about to read 4, iclass 7, count 2 2006.182.07:40:10.08#ibcon#read 4, iclass 7, count 2 2006.182.07:40:10.08#ibcon#about to read 5, iclass 7, count 2 2006.182.07:40:10.08#ibcon#read 5, iclass 7, count 2 2006.182.07:40:10.08#ibcon#about to read 6, iclass 7, count 2 2006.182.07:40:10.08#ibcon#read 6, iclass 7, count 2 2006.182.07:40:10.08#ibcon#end of sib2, iclass 7, count 2 2006.182.07:40:10.08#ibcon#*after write, iclass 7, count 2 2006.182.07:40:10.08#ibcon#*before return 0, iclass 7, count 2 2006.182.07:40:10.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:40:10.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:40:10.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.07:40:10.08#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:10.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:40:10.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:40:10.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:40:10.20#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:40:10.20#ibcon#first serial, iclass 7, count 0 2006.182.07:40:10.20#ibcon#enter sib2, iclass 7, count 0 2006.182.07:40:10.20#ibcon#flushed, iclass 7, count 0 2006.182.07:40:10.20#ibcon#about to write, iclass 7, count 0 2006.182.07:40:10.20#ibcon#wrote, iclass 7, count 0 2006.182.07:40:10.20#ibcon#about to read 3, iclass 7, count 0 2006.182.07:40:10.22#ibcon#read 3, iclass 7, count 0 2006.182.07:40:10.22#ibcon#about to read 4, iclass 7, count 0 2006.182.07:40:10.22#ibcon#read 4, iclass 7, count 0 2006.182.07:40:10.22#ibcon#about to read 5, iclass 7, count 0 2006.182.07:40:10.22#ibcon#read 5, iclass 7, count 0 2006.182.07:40:10.22#ibcon#about to read 6, iclass 7, count 0 2006.182.07:40:10.22#ibcon#read 6, iclass 7, count 0 2006.182.07:40:10.22#ibcon#end of sib2, iclass 7, count 0 2006.182.07:40:10.22#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:40:10.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:40:10.22#ibcon#[25=USB\r\n] 2006.182.07:40:10.22#ibcon#*before write, iclass 7, count 0 2006.182.07:40:10.22#ibcon#enter sib2, iclass 7, count 0 2006.182.07:40:10.22#ibcon#flushed, iclass 7, count 0 2006.182.07:40:10.22#ibcon#about to write, iclass 7, count 0 2006.182.07:40:10.22#ibcon#wrote, iclass 7, count 0 2006.182.07:40:10.22#ibcon#about to read 3, iclass 7, count 0 2006.182.07:40:10.25#ibcon#read 3, iclass 7, count 0 2006.182.07:40:10.25#ibcon#about to read 4, iclass 7, count 0 2006.182.07:40:10.25#ibcon#read 4, iclass 7, count 0 2006.182.07:40:10.25#ibcon#about to read 5, iclass 7, count 0 2006.182.07:40:10.25#ibcon#read 5, iclass 7, count 0 2006.182.07:40:10.25#ibcon#about to read 6, iclass 7, count 0 2006.182.07:40:10.25#ibcon#read 6, iclass 7, count 0 2006.182.07:40:10.25#ibcon#end of sib2, iclass 7, count 0 2006.182.07:40:10.25#ibcon#*after write, iclass 7, count 0 2006.182.07:40:10.25#ibcon#*before return 0, iclass 7, count 0 2006.182.07:40:10.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:40:10.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:40:10.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:40:10.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:40:10.25$vc4f8/valo=8,852.99 2006.182.07:40:10.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.07:40:10.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.07:40:10.25#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:10.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:40:10.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:40:10.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:40:10.25#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:40:10.25#ibcon#first serial, iclass 11, count 0 2006.182.07:40:10.25#ibcon#enter sib2, iclass 11, count 0 2006.182.07:40:10.25#ibcon#flushed, iclass 11, count 0 2006.182.07:40:10.25#ibcon#about to write, iclass 11, count 0 2006.182.07:40:10.25#ibcon#wrote, iclass 11, count 0 2006.182.07:40:10.25#ibcon#about to read 3, iclass 11, count 0 2006.182.07:40:10.27#ibcon#read 3, iclass 11, count 0 2006.182.07:40:10.27#ibcon#about to read 4, iclass 11, count 0 2006.182.07:40:10.27#ibcon#read 4, iclass 11, count 0 2006.182.07:40:10.27#ibcon#about to read 5, iclass 11, count 0 2006.182.07:40:10.27#ibcon#read 5, iclass 11, count 0 2006.182.07:40:10.27#ibcon#about to read 6, iclass 11, count 0 2006.182.07:40:10.27#ibcon#read 6, iclass 11, count 0 2006.182.07:40:10.27#ibcon#end of sib2, iclass 11, count 0 2006.182.07:40:10.27#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:40:10.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:40:10.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:40:10.27#ibcon#*before write, iclass 11, count 0 2006.182.07:40:10.27#ibcon#enter sib2, iclass 11, count 0 2006.182.07:40:10.27#ibcon#flushed, iclass 11, count 0 2006.182.07:40:10.27#ibcon#about to write, iclass 11, count 0 2006.182.07:40:10.27#ibcon#wrote, iclass 11, count 0 2006.182.07:40:10.27#ibcon#about to read 3, iclass 11, count 0 2006.182.07:40:10.31#ibcon#read 3, iclass 11, count 0 2006.182.07:40:10.31#ibcon#about to read 4, iclass 11, count 0 2006.182.07:40:10.31#ibcon#read 4, iclass 11, count 0 2006.182.07:40:10.31#ibcon#about to read 5, iclass 11, count 0 2006.182.07:40:10.31#ibcon#read 5, iclass 11, count 0 2006.182.07:40:10.31#ibcon#about to read 6, iclass 11, count 0 2006.182.07:40:10.31#ibcon#read 6, iclass 11, count 0 2006.182.07:40:10.31#ibcon#end of sib2, iclass 11, count 0 2006.182.07:40:10.31#ibcon#*after write, iclass 11, count 0 2006.182.07:40:10.31#ibcon#*before return 0, iclass 11, count 0 2006.182.07:40:10.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:40:10.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:40:10.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:40:10.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:40:10.31$vc4f8/va=8,7 2006.182.07:40:10.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.07:40:10.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.07:40:10.31#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:10.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:40:10.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:40:10.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:40:10.37#ibcon#enter wrdev, iclass 13, count 2 2006.182.07:40:10.37#ibcon#first serial, iclass 13, count 2 2006.182.07:40:10.37#ibcon#enter sib2, iclass 13, count 2 2006.182.07:40:10.37#ibcon#flushed, iclass 13, count 2 2006.182.07:40:10.37#ibcon#about to write, iclass 13, count 2 2006.182.07:40:10.37#ibcon#wrote, iclass 13, count 2 2006.182.07:40:10.37#ibcon#about to read 3, iclass 13, count 2 2006.182.07:40:10.39#ibcon#read 3, iclass 13, count 2 2006.182.07:40:10.39#ibcon#about to read 4, iclass 13, count 2 2006.182.07:40:10.39#ibcon#read 4, iclass 13, count 2 2006.182.07:40:10.39#ibcon#about to read 5, iclass 13, count 2 2006.182.07:40:10.39#ibcon#read 5, iclass 13, count 2 2006.182.07:40:10.39#ibcon#about to read 6, iclass 13, count 2 2006.182.07:40:10.39#ibcon#read 6, iclass 13, count 2 2006.182.07:40:10.39#ibcon#end of sib2, iclass 13, count 2 2006.182.07:40:10.39#ibcon#*mode == 0, iclass 13, count 2 2006.182.07:40:10.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.07:40:10.39#ibcon#[25=AT08-07\r\n] 2006.182.07:40:10.39#ibcon#*before write, iclass 13, count 2 2006.182.07:40:10.39#ibcon#enter sib2, iclass 13, count 2 2006.182.07:40:10.39#ibcon#flushed, iclass 13, count 2 2006.182.07:40:10.39#ibcon#about to write, iclass 13, count 2 2006.182.07:40:10.39#ibcon#wrote, iclass 13, count 2 2006.182.07:40:10.39#ibcon#about to read 3, iclass 13, count 2 2006.182.07:40:10.42#ibcon#read 3, iclass 13, count 2 2006.182.07:40:10.42#ibcon#about to read 4, iclass 13, count 2 2006.182.07:40:10.42#ibcon#read 4, iclass 13, count 2 2006.182.07:40:10.42#ibcon#about to read 5, iclass 13, count 2 2006.182.07:40:10.42#ibcon#read 5, iclass 13, count 2 2006.182.07:40:10.42#ibcon#about to read 6, iclass 13, count 2 2006.182.07:40:10.42#ibcon#read 6, iclass 13, count 2 2006.182.07:40:10.42#ibcon#end of sib2, iclass 13, count 2 2006.182.07:40:10.42#ibcon#*after write, iclass 13, count 2 2006.182.07:40:10.42#ibcon#*before return 0, iclass 13, count 2 2006.182.07:40:10.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:40:10.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:40:10.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.07:40:10.42#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:10.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:40:10.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:40:10.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:40:10.54#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:40:10.54#ibcon#first serial, iclass 13, count 0 2006.182.07:40:10.54#ibcon#enter sib2, iclass 13, count 0 2006.182.07:40:10.54#ibcon#flushed, iclass 13, count 0 2006.182.07:40:10.54#ibcon#about to write, iclass 13, count 0 2006.182.07:40:10.54#ibcon#wrote, iclass 13, count 0 2006.182.07:40:10.54#ibcon#about to read 3, iclass 13, count 0 2006.182.07:40:10.56#ibcon#read 3, iclass 13, count 0 2006.182.07:40:10.56#ibcon#about to read 4, iclass 13, count 0 2006.182.07:40:10.56#ibcon#read 4, iclass 13, count 0 2006.182.07:40:10.56#ibcon#about to read 5, iclass 13, count 0 2006.182.07:40:10.56#ibcon#read 5, iclass 13, count 0 2006.182.07:40:10.56#ibcon#about to read 6, iclass 13, count 0 2006.182.07:40:10.56#ibcon#read 6, iclass 13, count 0 2006.182.07:40:10.56#ibcon#end of sib2, iclass 13, count 0 2006.182.07:40:10.56#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:40:10.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:40:10.56#ibcon#[25=USB\r\n] 2006.182.07:40:10.56#ibcon#*before write, iclass 13, count 0 2006.182.07:40:10.56#ibcon#enter sib2, iclass 13, count 0 2006.182.07:40:10.56#ibcon#flushed, iclass 13, count 0 2006.182.07:40:10.56#ibcon#about to write, iclass 13, count 0 2006.182.07:40:10.56#ibcon#wrote, iclass 13, count 0 2006.182.07:40:10.56#ibcon#about to read 3, iclass 13, count 0 2006.182.07:40:10.59#ibcon#read 3, iclass 13, count 0 2006.182.07:40:10.59#ibcon#about to read 4, iclass 13, count 0 2006.182.07:40:10.59#ibcon#read 4, iclass 13, count 0 2006.182.07:40:10.59#ibcon#about to read 5, iclass 13, count 0 2006.182.07:40:10.59#ibcon#read 5, iclass 13, count 0 2006.182.07:40:10.59#ibcon#about to read 6, iclass 13, count 0 2006.182.07:40:10.59#ibcon#read 6, iclass 13, count 0 2006.182.07:40:10.59#ibcon#end of sib2, iclass 13, count 0 2006.182.07:40:10.59#ibcon#*after write, iclass 13, count 0 2006.182.07:40:10.59#ibcon#*before return 0, iclass 13, count 0 2006.182.07:40:10.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:40:10.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:40:10.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:40:10.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:40:10.59$vc4f8/vblo=1,632.99 2006.182.07:40:10.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.07:40:10.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.07:40:10.59#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:10.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:40:10.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:40:10.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:40:10.59#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:40:10.59#ibcon#first serial, iclass 15, count 0 2006.182.07:40:10.59#ibcon#enter sib2, iclass 15, count 0 2006.182.07:40:10.59#ibcon#flushed, iclass 15, count 0 2006.182.07:40:10.59#ibcon#about to write, iclass 15, count 0 2006.182.07:40:10.59#ibcon#wrote, iclass 15, count 0 2006.182.07:40:10.59#ibcon#about to read 3, iclass 15, count 0 2006.182.07:40:10.62#ibcon#read 3, iclass 15, count 0 2006.182.07:40:10.62#ibcon#about to read 4, iclass 15, count 0 2006.182.07:40:10.62#ibcon#read 4, iclass 15, count 0 2006.182.07:40:10.62#ibcon#about to read 5, iclass 15, count 0 2006.182.07:40:10.62#ibcon#read 5, iclass 15, count 0 2006.182.07:40:10.62#ibcon#about to read 6, iclass 15, count 0 2006.182.07:40:10.62#ibcon#read 6, iclass 15, count 0 2006.182.07:40:10.62#ibcon#end of sib2, iclass 15, count 0 2006.182.07:40:10.62#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:40:10.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:40:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:40:10.62#ibcon#*before write, iclass 15, count 0 2006.182.07:40:10.62#ibcon#enter sib2, iclass 15, count 0 2006.182.07:40:10.62#ibcon#flushed, iclass 15, count 0 2006.182.07:40:10.62#ibcon#about to write, iclass 15, count 0 2006.182.07:40:10.62#ibcon#wrote, iclass 15, count 0 2006.182.07:40:10.62#ibcon#about to read 3, iclass 15, count 0 2006.182.07:40:10.66#ibcon#read 3, iclass 15, count 0 2006.182.07:40:10.66#ibcon#about to read 4, iclass 15, count 0 2006.182.07:40:10.66#ibcon#read 4, iclass 15, count 0 2006.182.07:40:10.66#ibcon#about to read 5, iclass 15, count 0 2006.182.07:40:10.66#ibcon#read 5, iclass 15, count 0 2006.182.07:40:10.66#ibcon#about to read 6, iclass 15, count 0 2006.182.07:40:10.66#ibcon#read 6, iclass 15, count 0 2006.182.07:40:10.66#ibcon#end of sib2, iclass 15, count 0 2006.182.07:40:10.66#ibcon#*after write, iclass 15, count 0 2006.182.07:40:10.66#ibcon#*before return 0, iclass 15, count 0 2006.182.07:40:10.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:40:10.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:40:10.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:40:10.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:40:10.66$vc4f8/vb=1,4 2006.182.07:40:10.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.07:40:10.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.07:40:10.66#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:10.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:40:10.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:40:10.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:40:10.66#ibcon#enter wrdev, iclass 17, count 2 2006.182.07:40:10.66#ibcon#first serial, iclass 17, count 2 2006.182.07:40:10.66#ibcon#enter sib2, iclass 17, count 2 2006.182.07:40:10.66#ibcon#flushed, iclass 17, count 2 2006.182.07:40:10.66#ibcon#about to write, iclass 17, count 2 2006.182.07:40:10.66#ibcon#wrote, iclass 17, count 2 2006.182.07:40:10.66#ibcon#about to read 3, iclass 17, count 2 2006.182.07:40:10.68#ibcon#read 3, iclass 17, count 2 2006.182.07:40:10.68#ibcon#about to read 4, iclass 17, count 2 2006.182.07:40:10.68#ibcon#read 4, iclass 17, count 2 2006.182.07:40:10.68#ibcon#about to read 5, iclass 17, count 2 2006.182.07:40:10.68#ibcon#read 5, iclass 17, count 2 2006.182.07:40:10.68#ibcon#about to read 6, iclass 17, count 2 2006.182.07:40:10.68#ibcon#read 6, iclass 17, count 2 2006.182.07:40:10.68#ibcon#end of sib2, iclass 17, count 2 2006.182.07:40:10.68#ibcon#*mode == 0, iclass 17, count 2 2006.182.07:40:10.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.07:40:10.68#ibcon#[27=AT01-04\r\n] 2006.182.07:40:10.68#ibcon#*before write, iclass 17, count 2 2006.182.07:40:10.68#ibcon#enter sib2, iclass 17, count 2 2006.182.07:40:10.68#ibcon#flushed, iclass 17, count 2 2006.182.07:40:10.68#ibcon#about to write, iclass 17, count 2 2006.182.07:40:10.68#ibcon#wrote, iclass 17, count 2 2006.182.07:40:10.68#ibcon#about to read 3, iclass 17, count 2 2006.182.07:40:10.71#ibcon#read 3, iclass 17, count 2 2006.182.07:40:10.71#ibcon#about to read 4, iclass 17, count 2 2006.182.07:40:10.71#ibcon#read 4, iclass 17, count 2 2006.182.07:40:10.71#ibcon#about to read 5, iclass 17, count 2 2006.182.07:40:10.71#ibcon#read 5, iclass 17, count 2 2006.182.07:40:10.71#ibcon#about to read 6, iclass 17, count 2 2006.182.07:40:10.71#ibcon#read 6, iclass 17, count 2 2006.182.07:40:10.71#ibcon#end of sib2, iclass 17, count 2 2006.182.07:40:10.71#ibcon#*after write, iclass 17, count 2 2006.182.07:40:10.71#ibcon#*before return 0, iclass 17, count 2 2006.182.07:40:10.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:40:10.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:40:10.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.07:40:10.71#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:10.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:40:10.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:40:10.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:40:10.83#ibcon#enter wrdev, iclass 17, count 0 2006.182.07:40:10.83#ibcon#first serial, iclass 17, count 0 2006.182.07:40:10.83#ibcon#enter sib2, iclass 17, count 0 2006.182.07:40:10.83#ibcon#flushed, iclass 17, count 0 2006.182.07:40:10.83#ibcon#about to write, iclass 17, count 0 2006.182.07:40:10.83#ibcon#wrote, iclass 17, count 0 2006.182.07:40:10.83#ibcon#about to read 3, iclass 17, count 0 2006.182.07:40:10.85#ibcon#read 3, iclass 17, count 0 2006.182.07:40:10.85#ibcon#about to read 4, iclass 17, count 0 2006.182.07:40:10.85#ibcon#read 4, iclass 17, count 0 2006.182.07:40:10.85#ibcon#about to read 5, iclass 17, count 0 2006.182.07:40:10.85#ibcon#read 5, iclass 17, count 0 2006.182.07:40:10.85#ibcon#about to read 6, iclass 17, count 0 2006.182.07:40:10.85#ibcon#read 6, iclass 17, count 0 2006.182.07:40:10.85#ibcon#end of sib2, iclass 17, count 0 2006.182.07:40:10.85#ibcon#*mode == 0, iclass 17, count 0 2006.182.07:40:10.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.07:40:10.85#ibcon#[27=USB\r\n] 2006.182.07:40:10.85#ibcon#*before write, iclass 17, count 0 2006.182.07:40:10.85#ibcon#enter sib2, iclass 17, count 0 2006.182.07:40:10.85#ibcon#flushed, iclass 17, count 0 2006.182.07:40:10.85#ibcon#about to write, iclass 17, count 0 2006.182.07:40:10.85#ibcon#wrote, iclass 17, count 0 2006.182.07:40:10.85#ibcon#about to read 3, iclass 17, count 0 2006.182.07:40:10.88#ibcon#read 3, iclass 17, count 0 2006.182.07:40:10.88#ibcon#about to read 4, iclass 17, count 0 2006.182.07:40:10.88#ibcon#read 4, iclass 17, count 0 2006.182.07:40:10.88#ibcon#about to read 5, iclass 17, count 0 2006.182.07:40:10.88#ibcon#read 5, iclass 17, count 0 2006.182.07:40:10.88#ibcon#about to read 6, iclass 17, count 0 2006.182.07:40:10.88#ibcon#read 6, iclass 17, count 0 2006.182.07:40:10.88#ibcon#end of sib2, iclass 17, count 0 2006.182.07:40:10.88#ibcon#*after write, iclass 17, count 0 2006.182.07:40:10.88#ibcon#*before return 0, iclass 17, count 0 2006.182.07:40:10.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:40:10.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:40:10.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.07:40:10.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.07:40:10.88$vc4f8/vblo=2,640.99 2006.182.07:40:10.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.07:40:10.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.07:40:10.88#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:10.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:10.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:10.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:10.88#ibcon#enter wrdev, iclass 19, count 0 2006.182.07:40:10.88#ibcon#first serial, iclass 19, count 0 2006.182.07:40:10.88#ibcon#enter sib2, iclass 19, count 0 2006.182.07:40:10.88#ibcon#flushed, iclass 19, count 0 2006.182.07:40:10.88#ibcon#about to write, iclass 19, count 0 2006.182.07:40:10.88#ibcon#wrote, iclass 19, count 0 2006.182.07:40:10.88#ibcon#about to read 3, iclass 19, count 0 2006.182.07:40:10.90#ibcon#read 3, iclass 19, count 0 2006.182.07:40:10.90#ibcon#about to read 4, iclass 19, count 0 2006.182.07:40:10.90#ibcon#read 4, iclass 19, count 0 2006.182.07:40:10.90#ibcon#about to read 5, iclass 19, count 0 2006.182.07:40:10.90#ibcon#read 5, iclass 19, count 0 2006.182.07:40:10.90#ibcon#about to read 6, iclass 19, count 0 2006.182.07:40:10.90#ibcon#read 6, iclass 19, count 0 2006.182.07:40:10.90#ibcon#end of sib2, iclass 19, count 0 2006.182.07:40:10.90#ibcon#*mode == 0, iclass 19, count 0 2006.182.07:40:10.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.07:40:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:40:10.90#ibcon#*before write, iclass 19, count 0 2006.182.07:40:10.90#ibcon#enter sib2, iclass 19, count 0 2006.182.07:40:10.90#ibcon#flushed, iclass 19, count 0 2006.182.07:40:10.90#ibcon#about to write, iclass 19, count 0 2006.182.07:40:10.90#ibcon#wrote, iclass 19, count 0 2006.182.07:40:10.90#ibcon#about to read 3, iclass 19, count 0 2006.182.07:40:10.94#ibcon#read 3, iclass 19, count 0 2006.182.07:40:10.94#ibcon#about to read 4, iclass 19, count 0 2006.182.07:40:10.94#ibcon#read 4, iclass 19, count 0 2006.182.07:40:10.94#ibcon#about to read 5, iclass 19, count 0 2006.182.07:40:10.94#ibcon#read 5, iclass 19, count 0 2006.182.07:40:10.94#ibcon#about to read 6, iclass 19, count 0 2006.182.07:40:10.94#ibcon#read 6, iclass 19, count 0 2006.182.07:40:10.94#ibcon#end of sib2, iclass 19, count 0 2006.182.07:40:10.94#ibcon#*after write, iclass 19, count 0 2006.182.07:40:10.94#ibcon#*before return 0, iclass 19, count 0 2006.182.07:40:10.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:10.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:40:10.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.07:40:10.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.07:40:10.94$vc4f8/vb=2,4 2006.182.07:40:10.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.07:40:10.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.07:40:10.94#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:10.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:11.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:11.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:11.00#ibcon#enter wrdev, iclass 21, count 2 2006.182.07:40:11.00#ibcon#first serial, iclass 21, count 2 2006.182.07:40:11.00#ibcon#enter sib2, iclass 21, count 2 2006.182.07:40:11.00#ibcon#flushed, iclass 21, count 2 2006.182.07:40:11.00#ibcon#about to write, iclass 21, count 2 2006.182.07:40:11.00#ibcon#wrote, iclass 21, count 2 2006.182.07:40:11.00#ibcon#about to read 3, iclass 21, count 2 2006.182.07:40:11.02#ibcon#read 3, iclass 21, count 2 2006.182.07:40:11.02#ibcon#about to read 4, iclass 21, count 2 2006.182.07:40:11.02#ibcon#read 4, iclass 21, count 2 2006.182.07:40:11.02#ibcon#about to read 5, iclass 21, count 2 2006.182.07:40:11.02#ibcon#read 5, iclass 21, count 2 2006.182.07:40:11.02#ibcon#about to read 6, iclass 21, count 2 2006.182.07:40:11.02#ibcon#read 6, iclass 21, count 2 2006.182.07:40:11.02#ibcon#end of sib2, iclass 21, count 2 2006.182.07:40:11.02#ibcon#*mode == 0, iclass 21, count 2 2006.182.07:40:11.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.07:40:11.02#ibcon#[27=AT02-04\r\n] 2006.182.07:40:11.02#ibcon#*before write, iclass 21, count 2 2006.182.07:40:11.02#ibcon#enter sib2, iclass 21, count 2 2006.182.07:40:11.02#ibcon#flushed, iclass 21, count 2 2006.182.07:40:11.02#ibcon#about to write, iclass 21, count 2 2006.182.07:40:11.02#ibcon#wrote, iclass 21, count 2 2006.182.07:40:11.02#ibcon#about to read 3, iclass 21, count 2 2006.182.07:40:11.05#ibcon#read 3, iclass 21, count 2 2006.182.07:40:11.05#ibcon#about to read 4, iclass 21, count 2 2006.182.07:40:11.05#ibcon#read 4, iclass 21, count 2 2006.182.07:40:11.05#ibcon#about to read 5, iclass 21, count 2 2006.182.07:40:11.05#ibcon#read 5, iclass 21, count 2 2006.182.07:40:11.05#ibcon#about to read 6, iclass 21, count 2 2006.182.07:40:11.05#ibcon#read 6, iclass 21, count 2 2006.182.07:40:11.05#ibcon#end of sib2, iclass 21, count 2 2006.182.07:40:11.05#ibcon#*after write, iclass 21, count 2 2006.182.07:40:11.05#ibcon#*before return 0, iclass 21, count 2 2006.182.07:40:11.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:11.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:40:11.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.07:40:11.05#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:11.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:11.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:11.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:11.17#ibcon#enter wrdev, iclass 21, count 0 2006.182.07:40:11.17#ibcon#first serial, iclass 21, count 0 2006.182.07:40:11.17#ibcon#enter sib2, iclass 21, count 0 2006.182.07:40:11.17#ibcon#flushed, iclass 21, count 0 2006.182.07:40:11.17#ibcon#about to write, iclass 21, count 0 2006.182.07:40:11.17#ibcon#wrote, iclass 21, count 0 2006.182.07:40:11.17#ibcon#about to read 3, iclass 21, count 0 2006.182.07:40:11.19#ibcon#read 3, iclass 21, count 0 2006.182.07:40:11.19#ibcon#about to read 4, iclass 21, count 0 2006.182.07:40:11.19#ibcon#read 4, iclass 21, count 0 2006.182.07:40:11.19#ibcon#about to read 5, iclass 21, count 0 2006.182.07:40:11.19#ibcon#read 5, iclass 21, count 0 2006.182.07:40:11.19#ibcon#about to read 6, iclass 21, count 0 2006.182.07:40:11.19#ibcon#read 6, iclass 21, count 0 2006.182.07:40:11.19#ibcon#end of sib2, iclass 21, count 0 2006.182.07:40:11.19#ibcon#*mode == 0, iclass 21, count 0 2006.182.07:40:11.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.07:40:11.19#ibcon#[27=USB\r\n] 2006.182.07:40:11.19#ibcon#*before write, iclass 21, count 0 2006.182.07:40:11.19#ibcon#enter sib2, iclass 21, count 0 2006.182.07:40:11.19#ibcon#flushed, iclass 21, count 0 2006.182.07:40:11.19#ibcon#about to write, iclass 21, count 0 2006.182.07:40:11.19#ibcon#wrote, iclass 21, count 0 2006.182.07:40:11.19#ibcon#about to read 3, iclass 21, count 0 2006.182.07:40:11.22#ibcon#read 3, iclass 21, count 0 2006.182.07:40:11.22#ibcon#about to read 4, iclass 21, count 0 2006.182.07:40:11.22#ibcon#read 4, iclass 21, count 0 2006.182.07:40:11.22#ibcon#about to read 5, iclass 21, count 0 2006.182.07:40:11.22#ibcon#read 5, iclass 21, count 0 2006.182.07:40:11.22#ibcon#about to read 6, iclass 21, count 0 2006.182.07:40:11.22#ibcon#read 6, iclass 21, count 0 2006.182.07:40:11.22#ibcon#end of sib2, iclass 21, count 0 2006.182.07:40:11.22#ibcon#*after write, iclass 21, count 0 2006.182.07:40:11.22#ibcon#*before return 0, iclass 21, count 0 2006.182.07:40:11.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:11.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:40:11.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.07:40:11.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.07:40:11.22$vc4f8/vblo=3,656.99 2006.182.07:40:11.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.07:40:11.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.07:40:11.22#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:11.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:11.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:11.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:11.22#ibcon#enter wrdev, iclass 23, count 0 2006.182.07:40:11.22#ibcon#first serial, iclass 23, count 0 2006.182.07:40:11.22#ibcon#enter sib2, iclass 23, count 0 2006.182.07:40:11.22#ibcon#flushed, iclass 23, count 0 2006.182.07:40:11.22#ibcon#about to write, iclass 23, count 0 2006.182.07:40:11.22#ibcon#wrote, iclass 23, count 0 2006.182.07:40:11.22#ibcon#about to read 3, iclass 23, count 0 2006.182.07:40:11.24#ibcon#read 3, iclass 23, count 0 2006.182.07:40:11.24#ibcon#about to read 4, iclass 23, count 0 2006.182.07:40:11.24#ibcon#read 4, iclass 23, count 0 2006.182.07:40:11.24#ibcon#about to read 5, iclass 23, count 0 2006.182.07:40:11.24#ibcon#read 5, iclass 23, count 0 2006.182.07:40:11.24#ibcon#about to read 6, iclass 23, count 0 2006.182.07:40:11.24#ibcon#read 6, iclass 23, count 0 2006.182.07:40:11.24#ibcon#end of sib2, iclass 23, count 0 2006.182.07:40:11.24#ibcon#*mode == 0, iclass 23, count 0 2006.182.07:40:11.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.07:40:11.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:40:11.24#ibcon#*before write, iclass 23, count 0 2006.182.07:40:11.24#ibcon#enter sib2, iclass 23, count 0 2006.182.07:40:11.24#ibcon#flushed, iclass 23, count 0 2006.182.07:40:11.24#ibcon#about to write, iclass 23, count 0 2006.182.07:40:11.24#ibcon#wrote, iclass 23, count 0 2006.182.07:40:11.24#ibcon#about to read 3, iclass 23, count 0 2006.182.07:40:11.28#ibcon#read 3, iclass 23, count 0 2006.182.07:40:11.28#ibcon#about to read 4, iclass 23, count 0 2006.182.07:40:11.28#ibcon#read 4, iclass 23, count 0 2006.182.07:40:11.28#ibcon#about to read 5, iclass 23, count 0 2006.182.07:40:11.28#ibcon#read 5, iclass 23, count 0 2006.182.07:40:11.28#ibcon#about to read 6, iclass 23, count 0 2006.182.07:40:11.28#ibcon#read 6, iclass 23, count 0 2006.182.07:40:11.28#ibcon#end of sib2, iclass 23, count 0 2006.182.07:40:11.28#ibcon#*after write, iclass 23, count 0 2006.182.07:40:11.28#ibcon#*before return 0, iclass 23, count 0 2006.182.07:40:11.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:11.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:40:11.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.07:40:11.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.07:40:11.28$vc4f8/vb=3,4 2006.182.07:40:11.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.07:40:11.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.07:40:11.28#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:11.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:11.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:11.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:11.34#ibcon#enter wrdev, iclass 25, count 2 2006.182.07:40:11.34#ibcon#first serial, iclass 25, count 2 2006.182.07:40:11.34#ibcon#enter sib2, iclass 25, count 2 2006.182.07:40:11.34#ibcon#flushed, iclass 25, count 2 2006.182.07:40:11.34#ibcon#about to write, iclass 25, count 2 2006.182.07:40:11.34#ibcon#wrote, iclass 25, count 2 2006.182.07:40:11.34#ibcon#about to read 3, iclass 25, count 2 2006.182.07:40:11.36#ibcon#read 3, iclass 25, count 2 2006.182.07:40:11.36#ibcon#about to read 4, iclass 25, count 2 2006.182.07:40:11.36#ibcon#read 4, iclass 25, count 2 2006.182.07:40:11.36#ibcon#about to read 5, iclass 25, count 2 2006.182.07:40:11.36#ibcon#read 5, iclass 25, count 2 2006.182.07:40:11.36#ibcon#about to read 6, iclass 25, count 2 2006.182.07:40:11.36#ibcon#read 6, iclass 25, count 2 2006.182.07:40:11.36#ibcon#end of sib2, iclass 25, count 2 2006.182.07:40:11.36#ibcon#*mode == 0, iclass 25, count 2 2006.182.07:40:11.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.07:40:11.36#ibcon#[27=AT03-04\r\n] 2006.182.07:40:11.36#ibcon#*before write, iclass 25, count 2 2006.182.07:40:11.36#ibcon#enter sib2, iclass 25, count 2 2006.182.07:40:11.36#ibcon#flushed, iclass 25, count 2 2006.182.07:40:11.36#ibcon#about to write, iclass 25, count 2 2006.182.07:40:11.36#ibcon#wrote, iclass 25, count 2 2006.182.07:40:11.36#ibcon#about to read 3, iclass 25, count 2 2006.182.07:40:11.39#ibcon#read 3, iclass 25, count 2 2006.182.07:40:11.39#ibcon#about to read 4, iclass 25, count 2 2006.182.07:40:11.39#ibcon#read 4, iclass 25, count 2 2006.182.07:40:11.39#ibcon#about to read 5, iclass 25, count 2 2006.182.07:40:11.39#ibcon#read 5, iclass 25, count 2 2006.182.07:40:11.39#ibcon#about to read 6, iclass 25, count 2 2006.182.07:40:11.39#ibcon#read 6, iclass 25, count 2 2006.182.07:40:11.39#ibcon#end of sib2, iclass 25, count 2 2006.182.07:40:11.39#ibcon#*after write, iclass 25, count 2 2006.182.07:40:11.39#ibcon#*before return 0, iclass 25, count 2 2006.182.07:40:11.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:11.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:40:11.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.07:40:11.39#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:11.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:11.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:11.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:11.51#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:40:11.51#ibcon#first serial, iclass 25, count 0 2006.182.07:40:11.51#ibcon#enter sib2, iclass 25, count 0 2006.182.07:40:11.51#ibcon#flushed, iclass 25, count 0 2006.182.07:40:11.51#ibcon#about to write, iclass 25, count 0 2006.182.07:40:11.51#ibcon#wrote, iclass 25, count 0 2006.182.07:40:11.51#ibcon#about to read 3, iclass 25, count 0 2006.182.07:40:11.53#ibcon#read 3, iclass 25, count 0 2006.182.07:40:11.53#ibcon#about to read 4, iclass 25, count 0 2006.182.07:40:11.53#ibcon#read 4, iclass 25, count 0 2006.182.07:40:11.53#ibcon#about to read 5, iclass 25, count 0 2006.182.07:40:11.53#ibcon#read 5, iclass 25, count 0 2006.182.07:40:11.53#ibcon#about to read 6, iclass 25, count 0 2006.182.07:40:11.53#ibcon#read 6, iclass 25, count 0 2006.182.07:40:11.53#ibcon#end of sib2, iclass 25, count 0 2006.182.07:40:11.53#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:40:11.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:40:11.53#ibcon#[27=USB\r\n] 2006.182.07:40:11.53#ibcon#*before write, iclass 25, count 0 2006.182.07:40:11.53#ibcon#enter sib2, iclass 25, count 0 2006.182.07:40:11.53#ibcon#flushed, iclass 25, count 0 2006.182.07:40:11.53#ibcon#about to write, iclass 25, count 0 2006.182.07:40:11.53#ibcon#wrote, iclass 25, count 0 2006.182.07:40:11.53#ibcon#about to read 3, iclass 25, count 0 2006.182.07:40:11.56#ibcon#read 3, iclass 25, count 0 2006.182.07:40:11.56#ibcon#about to read 4, iclass 25, count 0 2006.182.07:40:11.56#ibcon#read 4, iclass 25, count 0 2006.182.07:40:11.56#ibcon#about to read 5, iclass 25, count 0 2006.182.07:40:11.56#ibcon#read 5, iclass 25, count 0 2006.182.07:40:11.56#ibcon#about to read 6, iclass 25, count 0 2006.182.07:40:11.56#ibcon#read 6, iclass 25, count 0 2006.182.07:40:11.56#ibcon#end of sib2, iclass 25, count 0 2006.182.07:40:11.56#ibcon#*after write, iclass 25, count 0 2006.182.07:40:11.56#ibcon#*before return 0, iclass 25, count 0 2006.182.07:40:11.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:11.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:40:11.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:40:11.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:40:11.56$vc4f8/vblo=4,712.99 2006.182.07:40:11.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.07:40:11.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.07:40:11.56#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:11.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:11.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:11.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:11.56#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:40:11.56#ibcon#first serial, iclass 27, count 0 2006.182.07:40:11.56#ibcon#enter sib2, iclass 27, count 0 2006.182.07:40:11.56#ibcon#flushed, iclass 27, count 0 2006.182.07:40:11.56#ibcon#about to write, iclass 27, count 0 2006.182.07:40:11.56#ibcon#wrote, iclass 27, count 0 2006.182.07:40:11.56#ibcon#about to read 3, iclass 27, count 0 2006.182.07:40:11.58#ibcon#read 3, iclass 27, count 0 2006.182.07:40:11.58#ibcon#about to read 4, iclass 27, count 0 2006.182.07:40:11.58#ibcon#read 4, iclass 27, count 0 2006.182.07:40:11.58#ibcon#about to read 5, iclass 27, count 0 2006.182.07:40:11.58#ibcon#read 5, iclass 27, count 0 2006.182.07:40:11.58#ibcon#about to read 6, iclass 27, count 0 2006.182.07:40:11.58#ibcon#read 6, iclass 27, count 0 2006.182.07:40:11.58#ibcon#end of sib2, iclass 27, count 0 2006.182.07:40:11.58#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:40:11.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:40:11.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:40:11.58#ibcon#*before write, iclass 27, count 0 2006.182.07:40:11.58#ibcon#enter sib2, iclass 27, count 0 2006.182.07:40:11.58#ibcon#flushed, iclass 27, count 0 2006.182.07:40:11.58#ibcon#about to write, iclass 27, count 0 2006.182.07:40:11.58#ibcon#wrote, iclass 27, count 0 2006.182.07:40:11.58#ibcon#about to read 3, iclass 27, count 0 2006.182.07:40:11.62#ibcon#read 3, iclass 27, count 0 2006.182.07:40:11.62#ibcon#about to read 4, iclass 27, count 0 2006.182.07:40:11.62#ibcon#read 4, iclass 27, count 0 2006.182.07:40:11.62#ibcon#about to read 5, iclass 27, count 0 2006.182.07:40:11.62#ibcon#read 5, iclass 27, count 0 2006.182.07:40:11.62#ibcon#about to read 6, iclass 27, count 0 2006.182.07:40:11.62#ibcon#read 6, iclass 27, count 0 2006.182.07:40:11.62#ibcon#end of sib2, iclass 27, count 0 2006.182.07:40:11.62#ibcon#*after write, iclass 27, count 0 2006.182.07:40:11.62#ibcon#*before return 0, iclass 27, count 0 2006.182.07:40:11.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:11.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:40:11.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:40:11.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:40:11.62$vc4f8/vb=4,4 2006.182.07:40:11.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.07:40:11.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.07:40:11.62#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:11.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:11.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:11.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:11.68#ibcon#enter wrdev, iclass 29, count 2 2006.182.07:40:11.68#ibcon#first serial, iclass 29, count 2 2006.182.07:40:11.68#ibcon#enter sib2, iclass 29, count 2 2006.182.07:40:11.68#ibcon#flushed, iclass 29, count 2 2006.182.07:40:11.68#ibcon#about to write, iclass 29, count 2 2006.182.07:40:11.68#ibcon#wrote, iclass 29, count 2 2006.182.07:40:11.68#ibcon#about to read 3, iclass 29, count 2 2006.182.07:40:11.70#ibcon#read 3, iclass 29, count 2 2006.182.07:40:11.70#ibcon#about to read 4, iclass 29, count 2 2006.182.07:40:11.70#ibcon#read 4, iclass 29, count 2 2006.182.07:40:11.70#ibcon#about to read 5, iclass 29, count 2 2006.182.07:40:11.70#ibcon#read 5, iclass 29, count 2 2006.182.07:40:11.70#ibcon#about to read 6, iclass 29, count 2 2006.182.07:40:11.70#ibcon#read 6, iclass 29, count 2 2006.182.07:40:11.70#ibcon#end of sib2, iclass 29, count 2 2006.182.07:40:11.70#ibcon#*mode == 0, iclass 29, count 2 2006.182.07:40:11.70#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.07:40:11.70#ibcon#[27=AT04-04\r\n] 2006.182.07:40:11.70#ibcon#*before write, iclass 29, count 2 2006.182.07:40:11.70#ibcon#enter sib2, iclass 29, count 2 2006.182.07:40:11.70#ibcon#flushed, iclass 29, count 2 2006.182.07:40:11.70#ibcon#about to write, iclass 29, count 2 2006.182.07:40:11.70#ibcon#wrote, iclass 29, count 2 2006.182.07:40:11.70#ibcon#about to read 3, iclass 29, count 2 2006.182.07:40:11.73#ibcon#read 3, iclass 29, count 2 2006.182.07:40:11.73#ibcon#about to read 4, iclass 29, count 2 2006.182.07:40:11.73#ibcon#read 4, iclass 29, count 2 2006.182.07:40:11.73#ibcon#about to read 5, iclass 29, count 2 2006.182.07:40:11.73#ibcon#read 5, iclass 29, count 2 2006.182.07:40:11.73#ibcon#about to read 6, iclass 29, count 2 2006.182.07:40:11.73#ibcon#read 6, iclass 29, count 2 2006.182.07:40:11.73#ibcon#end of sib2, iclass 29, count 2 2006.182.07:40:11.73#ibcon#*after write, iclass 29, count 2 2006.182.07:40:11.73#ibcon#*before return 0, iclass 29, count 2 2006.182.07:40:11.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:11.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:40:11.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.07:40:11.73#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:11.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:11.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:11.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:11.85#ibcon#enter wrdev, iclass 29, count 0 2006.182.07:40:11.85#ibcon#first serial, iclass 29, count 0 2006.182.07:40:11.85#ibcon#enter sib2, iclass 29, count 0 2006.182.07:40:11.85#ibcon#flushed, iclass 29, count 0 2006.182.07:40:11.85#ibcon#about to write, iclass 29, count 0 2006.182.07:40:11.85#ibcon#wrote, iclass 29, count 0 2006.182.07:40:11.85#ibcon#about to read 3, iclass 29, count 0 2006.182.07:40:11.87#ibcon#read 3, iclass 29, count 0 2006.182.07:40:11.87#ibcon#about to read 4, iclass 29, count 0 2006.182.07:40:11.87#ibcon#read 4, iclass 29, count 0 2006.182.07:40:11.87#ibcon#about to read 5, iclass 29, count 0 2006.182.07:40:11.87#ibcon#read 5, iclass 29, count 0 2006.182.07:40:11.87#ibcon#about to read 6, iclass 29, count 0 2006.182.07:40:11.87#ibcon#read 6, iclass 29, count 0 2006.182.07:40:11.87#ibcon#end of sib2, iclass 29, count 0 2006.182.07:40:11.87#ibcon#*mode == 0, iclass 29, count 0 2006.182.07:40:11.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.07:40:11.87#ibcon#[27=USB\r\n] 2006.182.07:40:11.87#ibcon#*before write, iclass 29, count 0 2006.182.07:40:11.87#ibcon#enter sib2, iclass 29, count 0 2006.182.07:40:11.87#ibcon#flushed, iclass 29, count 0 2006.182.07:40:11.87#ibcon#about to write, iclass 29, count 0 2006.182.07:40:11.87#ibcon#wrote, iclass 29, count 0 2006.182.07:40:11.87#ibcon#about to read 3, iclass 29, count 0 2006.182.07:40:11.90#ibcon#read 3, iclass 29, count 0 2006.182.07:40:11.90#ibcon#about to read 4, iclass 29, count 0 2006.182.07:40:11.90#ibcon#read 4, iclass 29, count 0 2006.182.07:40:11.90#ibcon#about to read 5, iclass 29, count 0 2006.182.07:40:11.90#ibcon#read 5, iclass 29, count 0 2006.182.07:40:11.90#ibcon#about to read 6, iclass 29, count 0 2006.182.07:40:11.90#ibcon#read 6, iclass 29, count 0 2006.182.07:40:11.90#ibcon#end of sib2, iclass 29, count 0 2006.182.07:40:11.90#ibcon#*after write, iclass 29, count 0 2006.182.07:40:11.90#ibcon#*before return 0, iclass 29, count 0 2006.182.07:40:11.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:11.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:40:11.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.07:40:11.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.07:40:11.90$vc4f8/vblo=5,744.99 2006.182.07:40:11.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.07:40:11.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.07:40:11.90#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:11.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:11.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:11.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:11.90#ibcon#enter wrdev, iclass 31, count 0 2006.182.07:40:11.90#ibcon#first serial, iclass 31, count 0 2006.182.07:40:11.90#ibcon#enter sib2, iclass 31, count 0 2006.182.07:40:11.90#ibcon#flushed, iclass 31, count 0 2006.182.07:40:11.90#ibcon#about to write, iclass 31, count 0 2006.182.07:40:11.90#ibcon#wrote, iclass 31, count 0 2006.182.07:40:11.90#ibcon#about to read 3, iclass 31, count 0 2006.182.07:40:11.92#ibcon#read 3, iclass 31, count 0 2006.182.07:40:11.92#ibcon#about to read 4, iclass 31, count 0 2006.182.07:40:11.92#ibcon#read 4, iclass 31, count 0 2006.182.07:40:11.92#ibcon#about to read 5, iclass 31, count 0 2006.182.07:40:11.92#ibcon#read 5, iclass 31, count 0 2006.182.07:40:11.92#ibcon#about to read 6, iclass 31, count 0 2006.182.07:40:11.92#ibcon#read 6, iclass 31, count 0 2006.182.07:40:11.92#ibcon#end of sib2, iclass 31, count 0 2006.182.07:40:11.92#ibcon#*mode == 0, iclass 31, count 0 2006.182.07:40:11.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.07:40:11.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:40:11.92#ibcon#*before write, iclass 31, count 0 2006.182.07:40:11.92#ibcon#enter sib2, iclass 31, count 0 2006.182.07:40:11.92#ibcon#flushed, iclass 31, count 0 2006.182.07:40:11.92#ibcon#about to write, iclass 31, count 0 2006.182.07:40:11.92#ibcon#wrote, iclass 31, count 0 2006.182.07:40:11.92#ibcon#about to read 3, iclass 31, count 0 2006.182.07:40:11.96#abcon#<5=/05 0.5 1.5 27.47 821002.9\r\n> 2006.182.07:40:11.96#ibcon#read 3, iclass 31, count 0 2006.182.07:40:11.96#ibcon#about to read 4, iclass 31, count 0 2006.182.07:40:11.96#ibcon#read 4, iclass 31, count 0 2006.182.07:40:11.96#ibcon#about to read 5, iclass 31, count 0 2006.182.07:40:11.96#ibcon#read 5, iclass 31, count 0 2006.182.07:40:11.96#ibcon#about to read 6, iclass 31, count 0 2006.182.07:40:11.96#ibcon#read 6, iclass 31, count 0 2006.182.07:40:11.96#ibcon#end of sib2, iclass 31, count 0 2006.182.07:40:11.96#ibcon#*after write, iclass 31, count 0 2006.182.07:40:11.96#ibcon#*before return 0, iclass 31, count 0 2006.182.07:40:11.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:11.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:40:11.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.07:40:11.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.07:40:11.96$vc4f8/vb=5,4 2006.182.07:40:11.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.182.07:40:11.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.182.07:40:11.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:11.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:40:11.98#abcon#{5=INTERFACE CLEAR} 2006.182.07:40:12.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:40:12.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:40:12.02#ibcon#enter wrdev, iclass 36, count 2 2006.182.07:40:12.02#ibcon#first serial, iclass 36, count 2 2006.182.07:40:12.02#ibcon#enter sib2, iclass 36, count 2 2006.182.07:40:12.02#ibcon#flushed, iclass 36, count 2 2006.182.07:40:12.02#ibcon#about to write, iclass 36, count 2 2006.182.07:40:12.02#ibcon#wrote, iclass 36, count 2 2006.182.07:40:12.02#ibcon#about to read 3, iclass 36, count 2 2006.182.07:40:12.04#ibcon#read 3, iclass 36, count 2 2006.182.07:40:12.04#ibcon#about to read 4, iclass 36, count 2 2006.182.07:40:12.04#ibcon#read 4, iclass 36, count 2 2006.182.07:40:12.04#ibcon#about to read 5, iclass 36, count 2 2006.182.07:40:12.04#ibcon#read 5, iclass 36, count 2 2006.182.07:40:12.04#ibcon#about to read 6, iclass 36, count 2 2006.182.07:40:12.04#ibcon#read 6, iclass 36, count 2 2006.182.07:40:12.04#ibcon#end of sib2, iclass 36, count 2 2006.182.07:40:12.04#ibcon#*mode == 0, iclass 36, count 2 2006.182.07:40:12.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.182.07:40:12.04#ibcon#[27=AT05-04\r\n] 2006.182.07:40:12.04#ibcon#*before write, iclass 36, count 2 2006.182.07:40:12.04#ibcon#enter sib2, iclass 36, count 2 2006.182.07:40:12.04#ibcon#flushed, iclass 36, count 2 2006.182.07:40:12.04#ibcon#about to write, iclass 36, count 2 2006.182.07:40:12.04#ibcon#wrote, iclass 36, count 2 2006.182.07:40:12.04#ibcon#about to read 3, iclass 36, count 2 2006.182.07:40:12.04#abcon#[5=S1D000X0/0*\r\n] 2006.182.07:40:12.07#ibcon#read 3, iclass 36, count 2 2006.182.07:40:12.07#ibcon#about to read 4, iclass 36, count 2 2006.182.07:40:12.07#ibcon#read 4, iclass 36, count 2 2006.182.07:40:12.07#ibcon#about to read 5, iclass 36, count 2 2006.182.07:40:12.07#ibcon#read 5, iclass 36, count 2 2006.182.07:40:12.07#ibcon#about to read 6, iclass 36, count 2 2006.182.07:40:12.07#ibcon#read 6, iclass 36, count 2 2006.182.07:40:12.07#ibcon#end of sib2, iclass 36, count 2 2006.182.07:40:12.07#ibcon#*after write, iclass 36, count 2 2006.182.07:40:12.07#ibcon#*before return 0, iclass 36, count 2 2006.182.07:40:12.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:40:12.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:40:12.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.182.07:40:12.07#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:12.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:40:12.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:40:12.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:40:12.19#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:40:12.19#ibcon#first serial, iclass 36, count 0 2006.182.07:40:12.19#ibcon#enter sib2, iclass 36, count 0 2006.182.07:40:12.19#ibcon#flushed, iclass 36, count 0 2006.182.07:40:12.19#ibcon#about to write, iclass 36, count 0 2006.182.07:40:12.19#ibcon#wrote, iclass 36, count 0 2006.182.07:40:12.19#ibcon#about to read 3, iclass 36, count 0 2006.182.07:40:12.22#ibcon#read 3, iclass 36, count 0 2006.182.07:40:12.22#ibcon#about to read 4, iclass 36, count 0 2006.182.07:40:12.22#ibcon#read 4, iclass 36, count 0 2006.182.07:40:12.22#ibcon#about to read 5, iclass 36, count 0 2006.182.07:40:12.22#ibcon#read 5, iclass 36, count 0 2006.182.07:40:12.22#ibcon#about to read 6, iclass 36, count 0 2006.182.07:40:12.22#ibcon#read 6, iclass 36, count 0 2006.182.07:40:12.22#ibcon#end of sib2, iclass 36, count 0 2006.182.07:40:12.22#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:40:12.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:40:12.22#ibcon#[27=USB\r\n] 2006.182.07:40:12.22#ibcon#*before write, iclass 36, count 0 2006.182.07:40:12.22#ibcon#enter sib2, iclass 36, count 0 2006.182.07:40:12.22#ibcon#flushed, iclass 36, count 0 2006.182.07:40:12.22#ibcon#about to write, iclass 36, count 0 2006.182.07:40:12.22#ibcon#wrote, iclass 36, count 0 2006.182.07:40:12.22#ibcon#about to read 3, iclass 36, count 0 2006.182.07:40:12.25#ibcon#read 3, iclass 36, count 0 2006.182.07:40:12.25#ibcon#about to read 4, iclass 36, count 0 2006.182.07:40:12.25#ibcon#read 4, iclass 36, count 0 2006.182.07:40:12.25#ibcon#about to read 5, iclass 36, count 0 2006.182.07:40:12.25#ibcon#read 5, iclass 36, count 0 2006.182.07:40:12.25#ibcon#about to read 6, iclass 36, count 0 2006.182.07:40:12.25#ibcon#read 6, iclass 36, count 0 2006.182.07:40:12.25#ibcon#end of sib2, iclass 36, count 0 2006.182.07:40:12.25#ibcon#*after write, iclass 36, count 0 2006.182.07:40:12.25#ibcon#*before return 0, iclass 36, count 0 2006.182.07:40:12.25#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:40:12.25#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:40:12.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:40:12.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:40:12.25$vc4f8/vblo=6,752.99 2006.182.07:40:12.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.07:40:12.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.07:40:12.25#ibcon#ireg 17 cls_cnt 0 2006.182.07:40:12.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:12.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:12.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:12.25#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:40:12.25#ibcon#first serial, iclass 39, count 0 2006.182.07:40:12.25#ibcon#enter sib2, iclass 39, count 0 2006.182.07:40:12.25#ibcon#flushed, iclass 39, count 0 2006.182.07:40:12.25#ibcon#about to write, iclass 39, count 0 2006.182.07:40:12.25#ibcon#wrote, iclass 39, count 0 2006.182.07:40:12.25#ibcon#about to read 3, iclass 39, count 0 2006.182.07:40:12.27#ibcon#read 3, iclass 39, count 0 2006.182.07:40:12.27#ibcon#about to read 4, iclass 39, count 0 2006.182.07:40:12.27#ibcon#read 4, iclass 39, count 0 2006.182.07:40:12.27#ibcon#about to read 5, iclass 39, count 0 2006.182.07:40:12.27#ibcon#read 5, iclass 39, count 0 2006.182.07:40:12.27#ibcon#about to read 6, iclass 39, count 0 2006.182.07:40:12.27#ibcon#read 6, iclass 39, count 0 2006.182.07:40:12.27#ibcon#end of sib2, iclass 39, count 0 2006.182.07:40:12.27#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:40:12.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:40:12.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:40:12.27#ibcon#*before write, iclass 39, count 0 2006.182.07:40:12.27#ibcon#enter sib2, iclass 39, count 0 2006.182.07:40:12.27#ibcon#flushed, iclass 39, count 0 2006.182.07:40:12.27#ibcon#about to write, iclass 39, count 0 2006.182.07:40:12.27#ibcon#wrote, iclass 39, count 0 2006.182.07:40:12.27#ibcon#about to read 3, iclass 39, count 0 2006.182.07:40:12.31#ibcon#read 3, iclass 39, count 0 2006.182.07:40:12.31#ibcon#about to read 4, iclass 39, count 0 2006.182.07:40:12.31#ibcon#read 4, iclass 39, count 0 2006.182.07:40:12.31#ibcon#about to read 5, iclass 39, count 0 2006.182.07:40:12.31#ibcon#read 5, iclass 39, count 0 2006.182.07:40:12.31#ibcon#about to read 6, iclass 39, count 0 2006.182.07:40:12.31#ibcon#read 6, iclass 39, count 0 2006.182.07:40:12.31#ibcon#end of sib2, iclass 39, count 0 2006.182.07:40:12.31#ibcon#*after write, iclass 39, count 0 2006.182.07:40:12.31#ibcon#*before return 0, iclass 39, count 0 2006.182.07:40:12.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:12.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:40:12.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:40:12.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:40:12.31$vc4f8/vb=6,4 2006.182.07:40:12.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.07:40:12.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.07:40:12.31#ibcon#ireg 11 cls_cnt 2 2006.182.07:40:12.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:12.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:12.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:12.37#ibcon#enter wrdev, iclass 3, count 2 2006.182.07:40:12.37#ibcon#first serial, iclass 3, count 2 2006.182.07:40:12.37#ibcon#enter sib2, iclass 3, count 2 2006.182.07:40:12.37#ibcon#flushed, iclass 3, count 2 2006.182.07:40:12.37#ibcon#about to write, iclass 3, count 2 2006.182.07:40:12.37#ibcon#wrote, iclass 3, count 2 2006.182.07:40:12.37#ibcon#about to read 3, iclass 3, count 2 2006.182.07:40:12.39#ibcon#read 3, iclass 3, count 2 2006.182.07:40:12.39#ibcon#about to read 4, iclass 3, count 2 2006.182.07:40:12.39#ibcon#read 4, iclass 3, count 2 2006.182.07:40:12.39#ibcon#about to read 5, iclass 3, count 2 2006.182.07:40:12.39#ibcon#read 5, iclass 3, count 2 2006.182.07:40:12.39#ibcon#about to read 6, iclass 3, count 2 2006.182.07:40:12.39#ibcon#read 6, iclass 3, count 2 2006.182.07:40:12.39#ibcon#end of sib2, iclass 3, count 2 2006.182.07:40:12.39#ibcon#*mode == 0, iclass 3, count 2 2006.182.07:40:12.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.07:40:12.39#ibcon#[27=AT06-04\r\n] 2006.182.07:40:12.39#ibcon#*before write, iclass 3, count 2 2006.182.07:40:12.39#ibcon#enter sib2, iclass 3, count 2 2006.182.07:40:12.39#ibcon#flushed, iclass 3, count 2 2006.182.07:40:12.39#ibcon#about to write, iclass 3, count 2 2006.182.07:40:12.39#ibcon#wrote, iclass 3, count 2 2006.182.07:40:12.39#ibcon#about to read 3, iclass 3, count 2 2006.182.07:40:12.42#ibcon#read 3, iclass 3, count 2 2006.182.07:40:12.42#ibcon#about to read 4, iclass 3, count 2 2006.182.07:40:12.42#ibcon#read 4, iclass 3, count 2 2006.182.07:40:12.42#ibcon#about to read 5, iclass 3, count 2 2006.182.07:40:12.42#ibcon#read 5, iclass 3, count 2 2006.182.07:40:12.42#ibcon#about to read 6, iclass 3, count 2 2006.182.07:40:12.42#ibcon#read 6, iclass 3, count 2 2006.182.07:40:12.42#ibcon#end of sib2, iclass 3, count 2 2006.182.07:40:12.42#ibcon#*after write, iclass 3, count 2 2006.182.07:40:12.42#ibcon#*before return 0, iclass 3, count 2 2006.182.07:40:12.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:12.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:40:12.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.07:40:12.42#ibcon#ireg 7 cls_cnt 0 2006.182.07:40:12.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:12.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:12.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:12.54#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:40:12.54#ibcon#first serial, iclass 3, count 0 2006.182.07:40:12.54#ibcon#enter sib2, iclass 3, count 0 2006.182.07:40:12.54#ibcon#flushed, iclass 3, count 0 2006.182.07:40:12.54#ibcon#about to write, iclass 3, count 0 2006.182.07:40:12.54#ibcon#wrote, iclass 3, count 0 2006.182.07:40:12.54#ibcon#about to read 3, iclass 3, count 0 2006.182.07:40:12.56#ibcon#read 3, iclass 3, count 0 2006.182.07:40:12.56#ibcon#about to read 4, iclass 3, count 0 2006.182.07:40:12.56#ibcon#read 4, iclass 3, count 0 2006.182.07:40:12.56#ibcon#about to read 5, iclass 3, count 0 2006.182.07:40:12.56#ibcon#read 5, iclass 3, count 0 2006.182.07:40:12.56#ibcon#about to read 6, iclass 3, count 0 2006.182.07:40:12.56#ibcon#read 6, iclass 3, count 0 2006.182.07:40:12.56#ibcon#end of sib2, iclass 3, count 0 2006.182.07:40:12.56#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:40:12.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:40:12.56#ibcon#[27=USB\r\n] 2006.182.07:40:12.56#ibcon#*before write, iclass 3, count 0 2006.182.07:40:12.56#ibcon#enter sib2, iclass 3, count 0 2006.182.07:40:12.56#ibcon#flushed, iclass 3, count 0 2006.182.07:40:12.56#ibcon#about to write, iclass 3, count 0 2006.182.07:40:12.56#ibcon#wrote, iclass 3, count 0 2006.182.07:40:12.56#ibcon#about to read 3, iclass 3, count 0 2006.182.07:40:12.59#ibcon#read 3, iclass 3, count 0 2006.182.07:40:12.59#ibcon#about to read 4, iclass 3, count 0 2006.182.07:40:12.59#ibcon#read 4, iclass 3, count 0 2006.182.07:40:12.59#ibcon#about to read 5, iclass 3, count 0 2006.182.07:40:12.59#ibcon#read 5, iclass 3, count 0 2006.182.07:40:12.59#ibcon#about to read 6, iclass 3, count 0 2006.182.07:40:12.59#ibcon#read 6, iclass 3, count 0 2006.182.07:40:12.59#ibcon#end of sib2, iclass 3, count 0 2006.182.07:40:12.59#ibcon#*after write, iclass 3, count 0 2006.182.07:40:12.59#ibcon#*before return 0, iclass 3, count 0 2006.182.07:40:12.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:12.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:40:12.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:40:12.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:40:12.59$vc4f8/vabw=wide 2006.182.07:40:12.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.07:40:12.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.07:40:12.59#ibcon#ireg 8 cls_cnt 0 2006.182.07:40:12.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:12.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:12.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:12.59#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:40:12.59#ibcon#first serial, iclass 5, count 0 2006.182.07:40:12.59#ibcon#enter sib2, iclass 5, count 0 2006.182.07:40:12.59#ibcon#flushed, iclass 5, count 0 2006.182.07:40:12.59#ibcon#about to write, iclass 5, count 0 2006.182.07:40:12.59#ibcon#wrote, iclass 5, count 0 2006.182.07:40:12.59#ibcon#about to read 3, iclass 5, count 0 2006.182.07:40:12.61#ibcon#read 3, iclass 5, count 0 2006.182.07:40:12.61#ibcon#about to read 4, iclass 5, count 0 2006.182.07:40:12.61#ibcon#read 4, iclass 5, count 0 2006.182.07:40:12.61#ibcon#about to read 5, iclass 5, count 0 2006.182.07:40:12.61#ibcon#read 5, iclass 5, count 0 2006.182.07:40:12.61#ibcon#about to read 6, iclass 5, count 0 2006.182.07:40:12.61#ibcon#read 6, iclass 5, count 0 2006.182.07:40:12.61#ibcon#end of sib2, iclass 5, count 0 2006.182.07:40:12.61#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:40:12.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:40:12.61#ibcon#[25=BW32\r\n] 2006.182.07:40:12.61#ibcon#*before write, iclass 5, count 0 2006.182.07:40:12.61#ibcon#enter sib2, iclass 5, count 0 2006.182.07:40:12.61#ibcon#flushed, iclass 5, count 0 2006.182.07:40:12.61#ibcon#about to write, iclass 5, count 0 2006.182.07:40:12.61#ibcon#wrote, iclass 5, count 0 2006.182.07:40:12.61#ibcon#about to read 3, iclass 5, count 0 2006.182.07:40:12.64#ibcon#read 3, iclass 5, count 0 2006.182.07:40:12.64#ibcon#about to read 4, iclass 5, count 0 2006.182.07:40:12.64#ibcon#read 4, iclass 5, count 0 2006.182.07:40:12.64#ibcon#about to read 5, iclass 5, count 0 2006.182.07:40:12.64#ibcon#read 5, iclass 5, count 0 2006.182.07:40:12.64#ibcon#about to read 6, iclass 5, count 0 2006.182.07:40:12.64#ibcon#read 6, iclass 5, count 0 2006.182.07:40:12.64#ibcon#end of sib2, iclass 5, count 0 2006.182.07:40:12.64#ibcon#*after write, iclass 5, count 0 2006.182.07:40:12.64#ibcon#*before return 0, iclass 5, count 0 2006.182.07:40:12.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:12.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:40:12.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:40:12.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:40:12.64$vc4f8/vbbw=wide 2006.182.07:40:12.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.07:40:12.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.07:40:12.64#ibcon#ireg 8 cls_cnt 0 2006.182.07:40:12.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:40:12.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:40:12.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:40:12.71#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:40:12.71#ibcon#first serial, iclass 7, count 0 2006.182.07:40:12.71#ibcon#enter sib2, iclass 7, count 0 2006.182.07:40:12.71#ibcon#flushed, iclass 7, count 0 2006.182.07:40:12.71#ibcon#about to write, iclass 7, count 0 2006.182.07:40:12.71#ibcon#wrote, iclass 7, count 0 2006.182.07:40:12.71#ibcon#about to read 3, iclass 7, count 0 2006.182.07:40:12.73#ibcon#read 3, iclass 7, count 0 2006.182.07:40:12.73#ibcon#about to read 4, iclass 7, count 0 2006.182.07:40:12.73#ibcon#read 4, iclass 7, count 0 2006.182.07:40:12.73#ibcon#about to read 5, iclass 7, count 0 2006.182.07:40:12.73#ibcon#read 5, iclass 7, count 0 2006.182.07:40:12.73#ibcon#about to read 6, iclass 7, count 0 2006.182.07:40:12.73#ibcon#read 6, iclass 7, count 0 2006.182.07:40:12.73#ibcon#end of sib2, iclass 7, count 0 2006.182.07:40:12.73#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:40:12.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:40:12.73#ibcon#[27=BW32\r\n] 2006.182.07:40:12.73#ibcon#*before write, iclass 7, count 0 2006.182.07:40:12.73#ibcon#enter sib2, iclass 7, count 0 2006.182.07:40:12.73#ibcon#flushed, iclass 7, count 0 2006.182.07:40:12.73#ibcon#about to write, iclass 7, count 0 2006.182.07:40:12.73#ibcon#wrote, iclass 7, count 0 2006.182.07:40:12.73#ibcon#about to read 3, iclass 7, count 0 2006.182.07:40:12.76#ibcon#read 3, iclass 7, count 0 2006.182.07:40:12.76#ibcon#about to read 4, iclass 7, count 0 2006.182.07:40:12.76#ibcon#read 4, iclass 7, count 0 2006.182.07:40:12.76#ibcon#about to read 5, iclass 7, count 0 2006.182.07:40:12.76#ibcon#read 5, iclass 7, count 0 2006.182.07:40:12.76#ibcon#about to read 6, iclass 7, count 0 2006.182.07:40:12.76#ibcon#read 6, iclass 7, count 0 2006.182.07:40:12.76#ibcon#end of sib2, iclass 7, count 0 2006.182.07:40:12.76#ibcon#*after write, iclass 7, count 0 2006.182.07:40:12.76#ibcon#*before return 0, iclass 7, count 0 2006.182.07:40:12.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:40:12.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:40:12.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:40:12.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:40:12.76$4f8m12a/ifd4f 2006.182.07:40:12.76$ifd4f/lo= 2006.182.07:40:12.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:40:12.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:40:12.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:40:12.76$ifd4f/patch= 2006.182.07:40:12.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:40:12.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:40:12.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:40:12.76$4f8m12a/"form=m,16.000,1:2 2006.182.07:40:12.76$4f8m12a/"tpicd 2006.182.07:40:12.76$4f8m12a/echo=off 2006.182.07:40:12.76$4f8m12a/xlog=off 2006.182.07:40:12.76:!2006.182.07:40:40 2006.182.07:40:24.14#trakl#Source acquired 2006.182.07:40:25.14#flagr#flagr/antenna,acquired 2006.182.07:40:40.00:preob 2006.182.07:40:41.14/onsource/TRACKING 2006.182.07:40:41.14:!2006.182.07:40:50 2006.182.07:40:50.00:data_valid=on 2006.182.07:40:50.00:midob 2006.182.07:40:50.14/onsource/TRACKING 2006.182.07:40:50.14/wx/27.48,1002.8,82 2006.182.07:40:50.29/cable/+6.4665E-03 2006.182.07:40:51.38/va/01,08,usb,yes,28,30 2006.182.07:40:51.38/va/02,07,usb,yes,29,30 2006.182.07:40:51.38/va/03,06,usb,yes,30,30 2006.182.07:40:51.38/va/04,07,usb,yes,29,32 2006.182.07:40:51.38/va/05,07,usb,yes,30,32 2006.182.07:40:51.38/va/06,06,usb,yes,29,29 2006.182.07:40:51.38/va/07,06,usb,yes,30,30 2006.182.07:40:51.38/va/08,07,usb,yes,28,28 2006.182.07:40:51.61/valo/01,532.99,yes,locked 2006.182.07:40:51.61/valo/02,572.99,yes,locked 2006.182.07:40:51.61/valo/03,672.99,yes,locked 2006.182.07:40:51.61/valo/04,832.99,yes,locked 2006.182.07:40:51.61/valo/05,652.99,yes,locked 2006.182.07:40:51.61/valo/06,772.99,yes,locked 2006.182.07:40:51.61/valo/07,832.99,yes,locked 2006.182.07:40:51.61/valo/08,852.99,yes,locked 2006.182.07:40:52.70/vb/01,04,usb,yes,29,27 2006.182.07:40:52.70/vb/02,04,usb,yes,30,32 2006.182.07:40:52.70/vb/03,04,usb,yes,27,31 2006.182.07:40:52.70/vb/04,04,usb,yes,28,28 2006.182.07:40:52.70/vb/05,04,usb,yes,27,30 2006.182.07:40:52.70/vb/06,04,usb,yes,27,30 2006.182.07:40:52.70/vb/07,04,usb,yes,29,29 2006.182.07:40:52.70/vb/08,04,usb,yes,27,30 2006.182.07:40:52.94/vblo/01,632.99,yes,locked 2006.182.07:40:52.94/vblo/02,640.99,yes,locked 2006.182.07:40:52.94/vblo/03,656.99,yes,locked 2006.182.07:40:52.94/vblo/04,712.99,yes,locked 2006.182.07:40:52.94/vblo/05,744.99,yes,locked 2006.182.07:40:52.94/vblo/06,752.99,yes,locked 2006.182.07:40:52.94/vblo/07,734.99,yes,locked 2006.182.07:40:52.94/vblo/08,744.99,yes,locked 2006.182.07:40:53.09/vabw/8 2006.182.07:40:53.24/vbbw/8 2006.182.07:40:53.33/xfe/off,on,15.2 2006.182.07:40:53.72/ifatt/23,28,28,28 2006.182.07:40:54.08/fmout-gps/S +3.36E-07 2006.182.07:40:54.16:!2006.182.07:41:50 2006.182.07:41:50.00:data_valid=off 2006.182.07:41:50.00:postob 2006.182.07:41:50.09/cable/+6.4655E-03 2006.182.07:41:50.09/wx/27.50,1002.9,81 2006.182.07:41:51.08/fmout-gps/S +3.36E-07 2006.182.07:41:51.08:scan_name=182-0743,k06182,180 2006.182.07:41:51.09:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.182.07:41:51.14#flagr#flagr/antenna,new-source 2006.182.07:41:52.14:checkk5 2006.182.07:41:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:41:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:41:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:41:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:41:54.01/chk_obsdata//k5ts1/T1820740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:41:54.38/chk_obsdata//k5ts2/T1820740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:41:54.75/chk_obsdata//k5ts3/T1820740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:41:55.12/chk_obsdata//k5ts4/T1820740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:41:55.81/k5log//k5ts1_log_newline 2006.182.07:41:56.49/k5log//k5ts2_log_newline 2006.182.07:41:57.18/k5log//k5ts3_log_newline 2006.182.07:41:57.87/k5log//k5ts4_log_newline 2006.182.07:41:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:41:57.90:4f8m12a=1 2006.182.07:41:57.90$4f8m12a/echo=on 2006.182.07:41:57.90$4f8m12a/pcalon 2006.182.07:41:57.90$pcalon/"no phase cal control is implemented here 2006.182.07:41:57.90$4f8m12a/"tpicd=stop 2006.182.07:41:57.90$4f8m12a/vc4f8 2006.182.07:41:57.90$vc4f8/valo=1,532.99 2006.182.07:41:57.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.07:41:57.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.07:41:57.91#ibcon#ireg 17 cls_cnt 0 2006.182.07:41:57.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:41:57.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:41:57.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:41:57.91#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:41:57.91#ibcon#first serial, iclass 16, count 0 2006.182.07:41:57.91#ibcon#enter sib2, iclass 16, count 0 2006.182.07:41:57.91#ibcon#flushed, iclass 16, count 0 2006.182.07:41:57.91#ibcon#about to write, iclass 16, count 0 2006.182.07:41:57.91#ibcon#wrote, iclass 16, count 0 2006.182.07:41:57.91#ibcon#about to read 3, iclass 16, count 0 2006.182.07:41:57.94#ibcon#read 3, iclass 16, count 0 2006.182.07:41:57.94#ibcon#about to read 4, iclass 16, count 0 2006.182.07:41:57.94#ibcon#read 4, iclass 16, count 0 2006.182.07:41:57.94#ibcon#about to read 5, iclass 16, count 0 2006.182.07:41:57.94#ibcon#read 5, iclass 16, count 0 2006.182.07:41:57.94#ibcon#about to read 6, iclass 16, count 0 2006.182.07:41:57.94#ibcon#read 6, iclass 16, count 0 2006.182.07:41:57.94#ibcon#end of sib2, iclass 16, count 0 2006.182.07:41:57.94#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:41:57.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:41:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:41:57.94#ibcon#*before write, iclass 16, count 0 2006.182.07:41:57.94#ibcon#enter sib2, iclass 16, count 0 2006.182.07:41:57.94#ibcon#flushed, iclass 16, count 0 2006.182.07:41:57.94#ibcon#about to write, iclass 16, count 0 2006.182.07:41:57.94#ibcon#wrote, iclass 16, count 0 2006.182.07:41:57.94#ibcon#about to read 3, iclass 16, count 0 2006.182.07:41:57.99#ibcon#read 3, iclass 16, count 0 2006.182.07:41:57.99#ibcon#about to read 4, iclass 16, count 0 2006.182.07:41:57.99#ibcon#read 4, iclass 16, count 0 2006.182.07:41:57.99#ibcon#about to read 5, iclass 16, count 0 2006.182.07:41:57.99#ibcon#read 5, iclass 16, count 0 2006.182.07:41:57.99#ibcon#about to read 6, iclass 16, count 0 2006.182.07:41:57.99#ibcon#read 6, iclass 16, count 0 2006.182.07:41:57.99#ibcon#end of sib2, iclass 16, count 0 2006.182.07:41:57.99#ibcon#*after write, iclass 16, count 0 2006.182.07:41:57.99#ibcon#*before return 0, iclass 16, count 0 2006.182.07:41:57.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:41:57.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:41:57.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:41:57.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:41:57.99$vc4f8/va=1,8 2006.182.07:41:57.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.07:41:57.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.07:41:57.99#ibcon#ireg 11 cls_cnt 2 2006.182.07:41:57.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:41:57.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:41:57.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:41:57.99#ibcon#enter wrdev, iclass 18, count 2 2006.182.07:41:57.99#ibcon#first serial, iclass 18, count 2 2006.182.07:41:57.99#ibcon#enter sib2, iclass 18, count 2 2006.182.07:41:57.99#ibcon#flushed, iclass 18, count 2 2006.182.07:41:57.99#ibcon#about to write, iclass 18, count 2 2006.182.07:41:57.99#ibcon#wrote, iclass 18, count 2 2006.182.07:41:57.99#ibcon#about to read 3, iclass 18, count 2 2006.182.07:41:58.01#ibcon#read 3, iclass 18, count 2 2006.182.07:41:58.01#ibcon#about to read 4, iclass 18, count 2 2006.182.07:41:58.01#ibcon#read 4, iclass 18, count 2 2006.182.07:41:58.01#ibcon#about to read 5, iclass 18, count 2 2006.182.07:41:58.01#ibcon#read 5, iclass 18, count 2 2006.182.07:41:58.01#ibcon#about to read 6, iclass 18, count 2 2006.182.07:41:58.01#ibcon#read 6, iclass 18, count 2 2006.182.07:41:58.01#ibcon#end of sib2, iclass 18, count 2 2006.182.07:41:58.01#ibcon#*mode == 0, iclass 18, count 2 2006.182.07:41:58.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.07:41:58.01#ibcon#[25=AT01-08\r\n] 2006.182.07:41:58.01#ibcon#*before write, iclass 18, count 2 2006.182.07:41:58.01#ibcon#enter sib2, iclass 18, count 2 2006.182.07:41:58.01#ibcon#flushed, iclass 18, count 2 2006.182.07:41:58.01#ibcon#about to write, iclass 18, count 2 2006.182.07:41:58.01#ibcon#wrote, iclass 18, count 2 2006.182.07:41:58.01#ibcon#about to read 3, iclass 18, count 2 2006.182.07:41:58.04#ibcon#read 3, iclass 18, count 2 2006.182.07:41:58.04#ibcon#about to read 4, iclass 18, count 2 2006.182.07:41:58.04#ibcon#read 4, iclass 18, count 2 2006.182.07:41:58.04#ibcon#about to read 5, iclass 18, count 2 2006.182.07:41:58.04#ibcon#read 5, iclass 18, count 2 2006.182.07:41:58.04#ibcon#about to read 6, iclass 18, count 2 2006.182.07:41:58.04#ibcon#read 6, iclass 18, count 2 2006.182.07:41:58.04#ibcon#end of sib2, iclass 18, count 2 2006.182.07:41:58.04#ibcon#*after write, iclass 18, count 2 2006.182.07:41:58.04#ibcon#*before return 0, iclass 18, count 2 2006.182.07:41:58.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:41:58.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:41:58.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.07:41:58.04#ibcon#ireg 7 cls_cnt 0 2006.182.07:41:58.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:41:58.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:41:58.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:41:58.16#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:41:58.16#ibcon#first serial, iclass 18, count 0 2006.182.07:41:58.16#ibcon#enter sib2, iclass 18, count 0 2006.182.07:41:58.16#ibcon#flushed, iclass 18, count 0 2006.182.07:41:58.16#ibcon#about to write, iclass 18, count 0 2006.182.07:41:58.16#ibcon#wrote, iclass 18, count 0 2006.182.07:41:58.16#ibcon#about to read 3, iclass 18, count 0 2006.182.07:41:58.18#ibcon#read 3, iclass 18, count 0 2006.182.07:41:58.18#ibcon#about to read 4, iclass 18, count 0 2006.182.07:41:58.18#ibcon#read 4, iclass 18, count 0 2006.182.07:41:58.18#ibcon#about to read 5, iclass 18, count 0 2006.182.07:41:58.18#ibcon#read 5, iclass 18, count 0 2006.182.07:41:58.18#ibcon#about to read 6, iclass 18, count 0 2006.182.07:41:58.18#ibcon#read 6, iclass 18, count 0 2006.182.07:41:58.18#ibcon#end of sib2, iclass 18, count 0 2006.182.07:41:58.18#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:41:58.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:41:58.18#ibcon#[25=USB\r\n] 2006.182.07:41:58.18#ibcon#*before write, iclass 18, count 0 2006.182.07:41:58.18#ibcon#enter sib2, iclass 18, count 0 2006.182.07:41:58.18#ibcon#flushed, iclass 18, count 0 2006.182.07:41:58.18#ibcon#about to write, iclass 18, count 0 2006.182.07:41:58.18#ibcon#wrote, iclass 18, count 0 2006.182.07:41:58.18#ibcon#about to read 3, iclass 18, count 0 2006.182.07:41:58.21#ibcon#read 3, iclass 18, count 0 2006.182.07:41:58.21#ibcon#about to read 4, iclass 18, count 0 2006.182.07:41:58.21#ibcon#read 4, iclass 18, count 0 2006.182.07:41:58.21#ibcon#about to read 5, iclass 18, count 0 2006.182.07:41:58.21#ibcon#read 5, iclass 18, count 0 2006.182.07:41:58.21#ibcon#about to read 6, iclass 18, count 0 2006.182.07:41:58.21#ibcon#read 6, iclass 18, count 0 2006.182.07:41:58.21#ibcon#end of sib2, iclass 18, count 0 2006.182.07:41:58.21#ibcon#*after write, iclass 18, count 0 2006.182.07:41:58.21#ibcon#*before return 0, iclass 18, count 0 2006.182.07:41:58.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:41:58.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:41:58.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:41:58.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:41:58.22$vc4f8/valo=2,572.99 2006.182.07:41:58.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.07:41:58.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.07:41:58.22#ibcon#ireg 17 cls_cnt 0 2006.182.07:41:58.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:41:58.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:41:58.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:41:58.22#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:41:58.22#ibcon#first serial, iclass 20, count 0 2006.182.07:41:58.22#ibcon#enter sib2, iclass 20, count 0 2006.182.07:41:58.22#ibcon#flushed, iclass 20, count 0 2006.182.07:41:58.22#ibcon#about to write, iclass 20, count 0 2006.182.07:41:58.22#ibcon#wrote, iclass 20, count 0 2006.182.07:41:58.22#ibcon#about to read 3, iclass 20, count 0 2006.182.07:41:58.23#ibcon#read 3, iclass 20, count 0 2006.182.07:41:58.23#ibcon#about to read 4, iclass 20, count 0 2006.182.07:41:58.23#ibcon#read 4, iclass 20, count 0 2006.182.07:41:58.23#ibcon#about to read 5, iclass 20, count 0 2006.182.07:41:58.23#ibcon#read 5, iclass 20, count 0 2006.182.07:41:58.23#ibcon#about to read 6, iclass 20, count 0 2006.182.07:41:58.23#ibcon#read 6, iclass 20, count 0 2006.182.07:41:58.23#ibcon#end of sib2, iclass 20, count 0 2006.182.07:41:58.23#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:41:58.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:41:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:41:58.23#ibcon#*before write, iclass 20, count 0 2006.182.07:41:58.23#ibcon#enter sib2, iclass 20, count 0 2006.182.07:41:58.23#ibcon#flushed, iclass 20, count 0 2006.182.07:41:58.23#ibcon#about to write, iclass 20, count 0 2006.182.07:41:58.23#ibcon#wrote, iclass 20, count 0 2006.182.07:41:58.23#ibcon#about to read 3, iclass 20, count 0 2006.182.07:41:58.27#ibcon#read 3, iclass 20, count 0 2006.182.07:41:58.27#ibcon#about to read 4, iclass 20, count 0 2006.182.07:41:58.27#ibcon#read 4, iclass 20, count 0 2006.182.07:41:58.27#ibcon#about to read 5, iclass 20, count 0 2006.182.07:41:58.27#ibcon#read 5, iclass 20, count 0 2006.182.07:41:58.27#ibcon#about to read 6, iclass 20, count 0 2006.182.07:41:58.27#ibcon#read 6, iclass 20, count 0 2006.182.07:41:58.27#ibcon#end of sib2, iclass 20, count 0 2006.182.07:41:58.27#ibcon#*after write, iclass 20, count 0 2006.182.07:41:58.27#ibcon#*before return 0, iclass 20, count 0 2006.182.07:41:58.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:41:58.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:41:58.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:41:58.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:41:58.27$vc4f8/va=2,7 2006.182.07:41:58.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.07:41:58.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.07:41:58.27#ibcon#ireg 11 cls_cnt 2 2006.182.07:41:58.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:41:58.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:41:58.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:41:58.34#ibcon#enter wrdev, iclass 22, count 2 2006.182.07:41:58.34#ibcon#first serial, iclass 22, count 2 2006.182.07:41:58.34#ibcon#enter sib2, iclass 22, count 2 2006.182.07:41:58.34#ibcon#flushed, iclass 22, count 2 2006.182.07:41:58.34#ibcon#about to write, iclass 22, count 2 2006.182.07:41:58.34#ibcon#wrote, iclass 22, count 2 2006.182.07:41:58.34#ibcon#about to read 3, iclass 22, count 2 2006.182.07:41:58.36#ibcon#read 3, iclass 22, count 2 2006.182.07:41:58.36#ibcon#about to read 4, iclass 22, count 2 2006.182.07:41:58.36#ibcon#read 4, iclass 22, count 2 2006.182.07:41:58.36#ibcon#about to read 5, iclass 22, count 2 2006.182.07:41:58.36#ibcon#read 5, iclass 22, count 2 2006.182.07:41:58.36#ibcon#about to read 6, iclass 22, count 2 2006.182.07:41:58.36#ibcon#read 6, iclass 22, count 2 2006.182.07:41:58.36#ibcon#end of sib2, iclass 22, count 2 2006.182.07:41:58.36#ibcon#*mode == 0, iclass 22, count 2 2006.182.07:41:58.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.07:41:58.36#ibcon#[25=AT02-07\r\n] 2006.182.07:41:58.36#ibcon#*before write, iclass 22, count 2 2006.182.07:41:58.36#ibcon#enter sib2, iclass 22, count 2 2006.182.07:41:58.36#ibcon#flushed, iclass 22, count 2 2006.182.07:41:58.36#ibcon#about to write, iclass 22, count 2 2006.182.07:41:58.36#ibcon#wrote, iclass 22, count 2 2006.182.07:41:58.36#ibcon#about to read 3, iclass 22, count 2 2006.182.07:41:58.39#ibcon#read 3, iclass 22, count 2 2006.182.07:41:58.39#ibcon#about to read 4, iclass 22, count 2 2006.182.07:41:58.39#ibcon#read 4, iclass 22, count 2 2006.182.07:41:58.39#ibcon#about to read 5, iclass 22, count 2 2006.182.07:41:58.39#ibcon#read 5, iclass 22, count 2 2006.182.07:41:58.39#ibcon#about to read 6, iclass 22, count 2 2006.182.07:41:58.39#ibcon#read 6, iclass 22, count 2 2006.182.07:41:58.39#ibcon#end of sib2, iclass 22, count 2 2006.182.07:41:58.39#ibcon#*after write, iclass 22, count 2 2006.182.07:41:58.39#ibcon#*before return 0, iclass 22, count 2 2006.182.07:41:58.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:41:58.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:41:58.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.07:41:58.39#ibcon#ireg 7 cls_cnt 0 2006.182.07:41:58.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:41:58.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:41:58.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:41:58.51#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:41:58.51#ibcon#first serial, iclass 22, count 0 2006.182.07:41:58.51#ibcon#enter sib2, iclass 22, count 0 2006.182.07:41:58.51#ibcon#flushed, iclass 22, count 0 2006.182.07:41:58.51#ibcon#about to write, iclass 22, count 0 2006.182.07:41:58.51#ibcon#wrote, iclass 22, count 0 2006.182.07:41:58.51#ibcon#about to read 3, iclass 22, count 0 2006.182.07:41:58.53#ibcon#read 3, iclass 22, count 0 2006.182.07:41:58.53#ibcon#about to read 4, iclass 22, count 0 2006.182.07:41:58.53#ibcon#read 4, iclass 22, count 0 2006.182.07:41:58.53#ibcon#about to read 5, iclass 22, count 0 2006.182.07:41:58.53#ibcon#read 5, iclass 22, count 0 2006.182.07:41:58.53#ibcon#about to read 6, iclass 22, count 0 2006.182.07:41:58.53#ibcon#read 6, iclass 22, count 0 2006.182.07:41:58.53#ibcon#end of sib2, iclass 22, count 0 2006.182.07:41:58.53#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:41:58.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:41:58.53#ibcon#[25=USB\r\n] 2006.182.07:41:58.53#ibcon#*before write, iclass 22, count 0 2006.182.07:41:58.53#ibcon#enter sib2, iclass 22, count 0 2006.182.07:41:58.53#ibcon#flushed, iclass 22, count 0 2006.182.07:41:58.53#ibcon#about to write, iclass 22, count 0 2006.182.07:41:58.53#ibcon#wrote, iclass 22, count 0 2006.182.07:41:58.53#ibcon#about to read 3, iclass 22, count 0 2006.182.07:41:58.56#ibcon#read 3, iclass 22, count 0 2006.182.07:41:58.56#ibcon#about to read 4, iclass 22, count 0 2006.182.07:41:58.56#ibcon#read 4, iclass 22, count 0 2006.182.07:41:58.56#ibcon#about to read 5, iclass 22, count 0 2006.182.07:41:58.56#ibcon#read 5, iclass 22, count 0 2006.182.07:41:58.56#ibcon#about to read 6, iclass 22, count 0 2006.182.07:41:58.56#ibcon#read 6, iclass 22, count 0 2006.182.07:41:58.56#ibcon#end of sib2, iclass 22, count 0 2006.182.07:41:58.56#ibcon#*after write, iclass 22, count 0 2006.182.07:41:58.56#ibcon#*before return 0, iclass 22, count 0 2006.182.07:41:58.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:41:58.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:41:58.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:41:58.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:41:58.56$vc4f8/valo=3,672.99 2006.182.07:41:58.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.07:41:58.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.07:41:58.56#ibcon#ireg 17 cls_cnt 0 2006.182.07:41:58.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:41:58.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:41:58.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:41:58.56#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:41:58.56#ibcon#first serial, iclass 24, count 0 2006.182.07:41:58.56#ibcon#enter sib2, iclass 24, count 0 2006.182.07:41:58.56#ibcon#flushed, iclass 24, count 0 2006.182.07:41:58.56#ibcon#about to write, iclass 24, count 0 2006.182.07:41:58.56#ibcon#wrote, iclass 24, count 0 2006.182.07:41:58.56#ibcon#about to read 3, iclass 24, count 0 2006.182.07:41:58.58#ibcon#read 3, iclass 24, count 0 2006.182.07:41:58.58#ibcon#about to read 4, iclass 24, count 0 2006.182.07:41:58.58#ibcon#read 4, iclass 24, count 0 2006.182.07:41:58.58#ibcon#about to read 5, iclass 24, count 0 2006.182.07:41:58.58#ibcon#read 5, iclass 24, count 0 2006.182.07:41:58.58#ibcon#about to read 6, iclass 24, count 0 2006.182.07:41:58.58#ibcon#read 6, iclass 24, count 0 2006.182.07:41:58.58#ibcon#end of sib2, iclass 24, count 0 2006.182.07:41:58.58#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:41:58.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:41:58.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:41:58.58#ibcon#*before write, iclass 24, count 0 2006.182.07:41:58.58#ibcon#enter sib2, iclass 24, count 0 2006.182.07:41:58.58#ibcon#flushed, iclass 24, count 0 2006.182.07:41:58.58#ibcon#about to write, iclass 24, count 0 2006.182.07:41:58.58#ibcon#wrote, iclass 24, count 0 2006.182.07:41:58.58#ibcon#about to read 3, iclass 24, count 0 2006.182.07:41:58.62#ibcon#read 3, iclass 24, count 0 2006.182.07:41:58.62#ibcon#about to read 4, iclass 24, count 0 2006.182.07:41:58.62#ibcon#read 4, iclass 24, count 0 2006.182.07:41:58.62#ibcon#about to read 5, iclass 24, count 0 2006.182.07:41:58.62#ibcon#read 5, iclass 24, count 0 2006.182.07:41:58.62#ibcon#about to read 6, iclass 24, count 0 2006.182.07:41:58.62#ibcon#read 6, iclass 24, count 0 2006.182.07:41:58.62#ibcon#end of sib2, iclass 24, count 0 2006.182.07:41:58.62#ibcon#*after write, iclass 24, count 0 2006.182.07:41:58.62#ibcon#*before return 0, iclass 24, count 0 2006.182.07:41:58.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:41:58.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:41:58.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:41:58.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:41:58.62$vc4f8/va=3,6 2006.182.07:41:58.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.07:41:58.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.07:41:58.62#ibcon#ireg 11 cls_cnt 2 2006.182.07:41:58.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:41:58.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:41:58.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:41:58.68#ibcon#enter wrdev, iclass 26, count 2 2006.182.07:41:58.68#ibcon#first serial, iclass 26, count 2 2006.182.07:41:58.68#ibcon#enter sib2, iclass 26, count 2 2006.182.07:41:58.68#ibcon#flushed, iclass 26, count 2 2006.182.07:41:58.68#ibcon#about to write, iclass 26, count 2 2006.182.07:41:58.68#ibcon#wrote, iclass 26, count 2 2006.182.07:41:58.68#ibcon#about to read 3, iclass 26, count 2 2006.182.07:41:58.70#ibcon#read 3, iclass 26, count 2 2006.182.07:41:58.70#ibcon#about to read 4, iclass 26, count 2 2006.182.07:41:58.70#ibcon#read 4, iclass 26, count 2 2006.182.07:41:58.70#ibcon#about to read 5, iclass 26, count 2 2006.182.07:41:58.70#ibcon#read 5, iclass 26, count 2 2006.182.07:41:58.70#ibcon#about to read 6, iclass 26, count 2 2006.182.07:41:58.70#ibcon#read 6, iclass 26, count 2 2006.182.07:41:58.70#ibcon#end of sib2, iclass 26, count 2 2006.182.07:41:58.70#ibcon#*mode == 0, iclass 26, count 2 2006.182.07:41:58.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.07:41:58.70#ibcon#[25=AT03-06\r\n] 2006.182.07:41:58.70#ibcon#*before write, iclass 26, count 2 2006.182.07:41:58.70#ibcon#enter sib2, iclass 26, count 2 2006.182.07:41:58.70#ibcon#flushed, iclass 26, count 2 2006.182.07:41:58.70#ibcon#about to write, iclass 26, count 2 2006.182.07:41:58.70#ibcon#wrote, iclass 26, count 2 2006.182.07:41:58.70#ibcon#about to read 3, iclass 26, count 2 2006.182.07:41:58.73#ibcon#read 3, iclass 26, count 2 2006.182.07:41:58.73#ibcon#about to read 4, iclass 26, count 2 2006.182.07:41:58.73#ibcon#read 4, iclass 26, count 2 2006.182.07:41:58.73#ibcon#about to read 5, iclass 26, count 2 2006.182.07:41:58.73#ibcon#read 5, iclass 26, count 2 2006.182.07:41:58.73#ibcon#about to read 6, iclass 26, count 2 2006.182.07:41:58.73#ibcon#read 6, iclass 26, count 2 2006.182.07:41:58.73#ibcon#end of sib2, iclass 26, count 2 2006.182.07:41:58.73#ibcon#*after write, iclass 26, count 2 2006.182.07:41:58.73#ibcon#*before return 0, iclass 26, count 2 2006.182.07:41:58.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:41:58.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:41:58.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.07:41:58.73#ibcon#ireg 7 cls_cnt 0 2006.182.07:41:58.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:41:58.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:41:58.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:41:58.85#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:41:58.85#ibcon#first serial, iclass 26, count 0 2006.182.07:41:58.85#ibcon#enter sib2, iclass 26, count 0 2006.182.07:41:58.85#ibcon#flushed, iclass 26, count 0 2006.182.07:41:58.85#ibcon#about to write, iclass 26, count 0 2006.182.07:41:58.85#ibcon#wrote, iclass 26, count 0 2006.182.07:41:58.85#ibcon#about to read 3, iclass 26, count 0 2006.182.07:41:58.87#ibcon#read 3, iclass 26, count 0 2006.182.07:41:58.87#ibcon#about to read 4, iclass 26, count 0 2006.182.07:41:58.87#ibcon#read 4, iclass 26, count 0 2006.182.07:41:58.87#ibcon#about to read 5, iclass 26, count 0 2006.182.07:41:58.87#ibcon#read 5, iclass 26, count 0 2006.182.07:41:58.87#ibcon#about to read 6, iclass 26, count 0 2006.182.07:41:58.87#ibcon#read 6, iclass 26, count 0 2006.182.07:41:58.87#ibcon#end of sib2, iclass 26, count 0 2006.182.07:41:58.87#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:41:58.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:41:58.87#ibcon#[25=USB\r\n] 2006.182.07:41:58.87#ibcon#*before write, iclass 26, count 0 2006.182.07:41:58.87#ibcon#enter sib2, iclass 26, count 0 2006.182.07:41:58.87#ibcon#flushed, iclass 26, count 0 2006.182.07:41:58.87#ibcon#about to write, iclass 26, count 0 2006.182.07:41:58.87#ibcon#wrote, iclass 26, count 0 2006.182.07:41:58.87#ibcon#about to read 3, iclass 26, count 0 2006.182.07:41:58.90#ibcon#read 3, iclass 26, count 0 2006.182.07:41:58.90#ibcon#about to read 4, iclass 26, count 0 2006.182.07:41:58.90#ibcon#read 4, iclass 26, count 0 2006.182.07:41:58.90#ibcon#about to read 5, iclass 26, count 0 2006.182.07:41:58.90#ibcon#read 5, iclass 26, count 0 2006.182.07:41:58.90#ibcon#about to read 6, iclass 26, count 0 2006.182.07:41:58.90#ibcon#read 6, iclass 26, count 0 2006.182.07:41:58.90#ibcon#end of sib2, iclass 26, count 0 2006.182.07:41:58.90#ibcon#*after write, iclass 26, count 0 2006.182.07:41:58.90#ibcon#*before return 0, iclass 26, count 0 2006.182.07:41:58.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:41:58.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:41:58.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:41:58.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:41:58.90$vc4f8/valo=4,832.99 2006.182.07:41:58.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.07:41:58.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.07:41:58.90#ibcon#ireg 17 cls_cnt 0 2006.182.07:41:58.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:41:58.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:41:58.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:41:58.90#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:41:58.90#ibcon#first serial, iclass 28, count 0 2006.182.07:41:58.90#ibcon#enter sib2, iclass 28, count 0 2006.182.07:41:58.90#ibcon#flushed, iclass 28, count 0 2006.182.07:41:58.90#ibcon#about to write, iclass 28, count 0 2006.182.07:41:58.90#ibcon#wrote, iclass 28, count 0 2006.182.07:41:58.90#ibcon#about to read 3, iclass 28, count 0 2006.182.07:41:58.92#ibcon#read 3, iclass 28, count 0 2006.182.07:41:58.92#ibcon#about to read 4, iclass 28, count 0 2006.182.07:41:58.92#ibcon#read 4, iclass 28, count 0 2006.182.07:41:58.92#ibcon#about to read 5, iclass 28, count 0 2006.182.07:41:58.92#ibcon#read 5, iclass 28, count 0 2006.182.07:41:58.92#ibcon#about to read 6, iclass 28, count 0 2006.182.07:41:58.92#ibcon#read 6, iclass 28, count 0 2006.182.07:41:58.92#ibcon#end of sib2, iclass 28, count 0 2006.182.07:41:58.92#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:41:58.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:41:58.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:41:58.92#ibcon#*before write, iclass 28, count 0 2006.182.07:41:58.92#ibcon#enter sib2, iclass 28, count 0 2006.182.07:41:58.92#ibcon#flushed, iclass 28, count 0 2006.182.07:41:58.92#ibcon#about to write, iclass 28, count 0 2006.182.07:41:58.92#ibcon#wrote, iclass 28, count 0 2006.182.07:41:58.92#ibcon#about to read 3, iclass 28, count 0 2006.182.07:41:58.96#ibcon#read 3, iclass 28, count 0 2006.182.07:41:58.96#ibcon#about to read 4, iclass 28, count 0 2006.182.07:41:58.96#ibcon#read 4, iclass 28, count 0 2006.182.07:41:58.96#ibcon#about to read 5, iclass 28, count 0 2006.182.07:41:58.96#ibcon#read 5, iclass 28, count 0 2006.182.07:41:58.96#ibcon#about to read 6, iclass 28, count 0 2006.182.07:41:58.96#ibcon#read 6, iclass 28, count 0 2006.182.07:41:58.96#ibcon#end of sib2, iclass 28, count 0 2006.182.07:41:58.96#ibcon#*after write, iclass 28, count 0 2006.182.07:41:58.96#ibcon#*before return 0, iclass 28, count 0 2006.182.07:41:58.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:41:58.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:41:58.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:41:58.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:41:58.96$vc4f8/va=4,7 2006.182.07:41:58.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.07:41:58.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.07:41:58.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:41:58.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:41:59.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:41:59.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:41:59.02#ibcon#enter wrdev, iclass 30, count 2 2006.182.07:41:59.02#ibcon#first serial, iclass 30, count 2 2006.182.07:41:59.02#ibcon#enter sib2, iclass 30, count 2 2006.182.07:41:59.02#ibcon#flushed, iclass 30, count 2 2006.182.07:41:59.02#ibcon#about to write, iclass 30, count 2 2006.182.07:41:59.02#ibcon#wrote, iclass 30, count 2 2006.182.07:41:59.02#ibcon#about to read 3, iclass 30, count 2 2006.182.07:41:59.04#ibcon#read 3, iclass 30, count 2 2006.182.07:41:59.04#ibcon#about to read 4, iclass 30, count 2 2006.182.07:41:59.04#ibcon#read 4, iclass 30, count 2 2006.182.07:41:59.04#ibcon#about to read 5, iclass 30, count 2 2006.182.07:41:59.04#ibcon#read 5, iclass 30, count 2 2006.182.07:41:59.04#ibcon#about to read 6, iclass 30, count 2 2006.182.07:41:59.04#ibcon#read 6, iclass 30, count 2 2006.182.07:41:59.04#ibcon#end of sib2, iclass 30, count 2 2006.182.07:41:59.04#ibcon#*mode == 0, iclass 30, count 2 2006.182.07:41:59.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.07:41:59.04#ibcon#[25=AT04-07\r\n] 2006.182.07:41:59.04#ibcon#*before write, iclass 30, count 2 2006.182.07:41:59.04#ibcon#enter sib2, iclass 30, count 2 2006.182.07:41:59.04#ibcon#flushed, iclass 30, count 2 2006.182.07:41:59.04#ibcon#about to write, iclass 30, count 2 2006.182.07:41:59.04#ibcon#wrote, iclass 30, count 2 2006.182.07:41:59.04#ibcon#about to read 3, iclass 30, count 2 2006.182.07:41:59.07#ibcon#read 3, iclass 30, count 2 2006.182.07:41:59.07#ibcon#about to read 4, iclass 30, count 2 2006.182.07:41:59.07#ibcon#read 4, iclass 30, count 2 2006.182.07:41:59.07#ibcon#about to read 5, iclass 30, count 2 2006.182.07:41:59.07#ibcon#read 5, iclass 30, count 2 2006.182.07:41:59.07#ibcon#about to read 6, iclass 30, count 2 2006.182.07:41:59.07#ibcon#read 6, iclass 30, count 2 2006.182.07:41:59.07#ibcon#end of sib2, iclass 30, count 2 2006.182.07:41:59.07#ibcon#*after write, iclass 30, count 2 2006.182.07:41:59.07#ibcon#*before return 0, iclass 30, count 2 2006.182.07:41:59.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:41:59.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:41:59.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.07:41:59.07#ibcon#ireg 7 cls_cnt 0 2006.182.07:41:59.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:41:59.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:41:59.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:41:59.19#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:41:59.19#ibcon#first serial, iclass 30, count 0 2006.182.07:41:59.19#ibcon#enter sib2, iclass 30, count 0 2006.182.07:41:59.19#ibcon#flushed, iclass 30, count 0 2006.182.07:41:59.19#ibcon#about to write, iclass 30, count 0 2006.182.07:41:59.19#ibcon#wrote, iclass 30, count 0 2006.182.07:41:59.19#ibcon#about to read 3, iclass 30, count 0 2006.182.07:41:59.21#ibcon#read 3, iclass 30, count 0 2006.182.07:41:59.21#ibcon#about to read 4, iclass 30, count 0 2006.182.07:41:59.21#ibcon#read 4, iclass 30, count 0 2006.182.07:41:59.21#ibcon#about to read 5, iclass 30, count 0 2006.182.07:41:59.21#ibcon#read 5, iclass 30, count 0 2006.182.07:41:59.21#ibcon#about to read 6, iclass 30, count 0 2006.182.07:41:59.21#ibcon#read 6, iclass 30, count 0 2006.182.07:41:59.21#ibcon#end of sib2, iclass 30, count 0 2006.182.07:41:59.21#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:41:59.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:41:59.21#ibcon#[25=USB\r\n] 2006.182.07:41:59.21#ibcon#*before write, iclass 30, count 0 2006.182.07:41:59.21#ibcon#enter sib2, iclass 30, count 0 2006.182.07:41:59.21#ibcon#flushed, iclass 30, count 0 2006.182.07:41:59.21#ibcon#about to write, iclass 30, count 0 2006.182.07:41:59.21#ibcon#wrote, iclass 30, count 0 2006.182.07:41:59.21#ibcon#about to read 3, iclass 30, count 0 2006.182.07:41:59.24#ibcon#read 3, iclass 30, count 0 2006.182.07:41:59.24#ibcon#about to read 4, iclass 30, count 0 2006.182.07:41:59.24#ibcon#read 4, iclass 30, count 0 2006.182.07:41:59.24#ibcon#about to read 5, iclass 30, count 0 2006.182.07:41:59.24#ibcon#read 5, iclass 30, count 0 2006.182.07:41:59.24#ibcon#about to read 6, iclass 30, count 0 2006.182.07:41:59.24#ibcon#read 6, iclass 30, count 0 2006.182.07:41:59.24#ibcon#end of sib2, iclass 30, count 0 2006.182.07:41:59.24#ibcon#*after write, iclass 30, count 0 2006.182.07:41:59.24#ibcon#*before return 0, iclass 30, count 0 2006.182.07:41:59.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:41:59.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:41:59.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:41:59.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:41:59.24$vc4f8/valo=5,652.99 2006.182.07:41:59.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.07:41:59.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.07:41:59.24#ibcon#ireg 17 cls_cnt 0 2006.182.07:41:59.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:41:59.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:41:59.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:41:59.24#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:41:59.24#ibcon#first serial, iclass 32, count 0 2006.182.07:41:59.24#ibcon#enter sib2, iclass 32, count 0 2006.182.07:41:59.24#ibcon#flushed, iclass 32, count 0 2006.182.07:41:59.24#ibcon#about to write, iclass 32, count 0 2006.182.07:41:59.24#ibcon#wrote, iclass 32, count 0 2006.182.07:41:59.24#ibcon#about to read 3, iclass 32, count 0 2006.182.07:41:59.26#ibcon#read 3, iclass 32, count 0 2006.182.07:41:59.26#ibcon#about to read 4, iclass 32, count 0 2006.182.07:41:59.26#ibcon#read 4, iclass 32, count 0 2006.182.07:41:59.26#ibcon#about to read 5, iclass 32, count 0 2006.182.07:41:59.26#ibcon#read 5, iclass 32, count 0 2006.182.07:41:59.26#ibcon#about to read 6, iclass 32, count 0 2006.182.07:41:59.26#ibcon#read 6, iclass 32, count 0 2006.182.07:41:59.26#ibcon#end of sib2, iclass 32, count 0 2006.182.07:41:59.26#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:41:59.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:41:59.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:41:59.26#ibcon#*before write, iclass 32, count 0 2006.182.07:41:59.26#ibcon#enter sib2, iclass 32, count 0 2006.182.07:41:59.26#ibcon#flushed, iclass 32, count 0 2006.182.07:41:59.26#ibcon#about to write, iclass 32, count 0 2006.182.07:41:59.26#ibcon#wrote, iclass 32, count 0 2006.182.07:41:59.26#ibcon#about to read 3, iclass 32, count 0 2006.182.07:41:59.30#ibcon#read 3, iclass 32, count 0 2006.182.07:41:59.30#ibcon#about to read 4, iclass 32, count 0 2006.182.07:41:59.30#ibcon#read 4, iclass 32, count 0 2006.182.07:41:59.30#ibcon#about to read 5, iclass 32, count 0 2006.182.07:41:59.30#ibcon#read 5, iclass 32, count 0 2006.182.07:41:59.30#ibcon#about to read 6, iclass 32, count 0 2006.182.07:41:59.30#ibcon#read 6, iclass 32, count 0 2006.182.07:41:59.30#ibcon#end of sib2, iclass 32, count 0 2006.182.07:41:59.30#ibcon#*after write, iclass 32, count 0 2006.182.07:41:59.30#ibcon#*before return 0, iclass 32, count 0 2006.182.07:41:59.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:41:59.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:41:59.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:41:59.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:41:59.30$vc4f8/va=5,7 2006.182.07:41:59.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.07:41:59.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.07:41:59.30#ibcon#ireg 11 cls_cnt 2 2006.182.07:41:59.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:41:59.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:41:59.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:41:59.36#ibcon#enter wrdev, iclass 34, count 2 2006.182.07:41:59.36#ibcon#first serial, iclass 34, count 2 2006.182.07:41:59.36#ibcon#enter sib2, iclass 34, count 2 2006.182.07:41:59.36#ibcon#flushed, iclass 34, count 2 2006.182.07:41:59.36#ibcon#about to write, iclass 34, count 2 2006.182.07:41:59.36#ibcon#wrote, iclass 34, count 2 2006.182.07:41:59.36#ibcon#about to read 3, iclass 34, count 2 2006.182.07:41:59.38#ibcon#read 3, iclass 34, count 2 2006.182.07:41:59.38#ibcon#about to read 4, iclass 34, count 2 2006.182.07:41:59.38#ibcon#read 4, iclass 34, count 2 2006.182.07:41:59.38#ibcon#about to read 5, iclass 34, count 2 2006.182.07:41:59.38#ibcon#read 5, iclass 34, count 2 2006.182.07:41:59.38#ibcon#about to read 6, iclass 34, count 2 2006.182.07:41:59.38#ibcon#read 6, iclass 34, count 2 2006.182.07:41:59.38#ibcon#end of sib2, iclass 34, count 2 2006.182.07:41:59.38#ibcon#*mode == 0, iclass 34, count 2 2006.182.07:41:59.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.07:41:59.38#ibcon#[25=AT05-07\r\n] 2006.182.07:41:59.38#ibcon#*before write, iclass 34, count 2 2006.182.07:41:59.38#ibcon#enter sib2, iclass 34, count 2 2006.182.07:41:59.38#ibcon#flushed, iclass 34, count 2 2006.182.07:41:59.38#ibcon#about to write, iclass 34, count 2 2006.182.07:41:59.38#ibcon#wrote, iclass 34, count 2 2006.182.07:41:59.38#ibcon#about to read 3, iclass 34, count 2 2006.182.07:41:59.41#ibcon#read 3, iclass 34, count 2 2006.182.07:41:59.41#ibcon#about to read 4, iclass 34, count 2 2006.182.07:41:59.41#ibcon#read 4, iclass 34, count 2 2006.182.07:41:59.41#ibcon#about to read 5, iclass 34, count 2 2006.182.07:41:59.41#ibcon#read 5, iclass 34, count 2 2006.182.07:41:59.41#ibcon#about to read 6, iclass 34, count 2 2006.182.07:41:59.41#ibcon#read 6, iclass 34, count 2 2006.182.07:41:59.41#ibcon#end of sib2, iclass 34, count 2 2006.182.07:41:59.41#ibcon#*after write, iclass 34, count 2 2006.182.07:41:59.41#ibcon#*before return 0, iclass 34, count 2 2006.182.07:41:59.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:41:59.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:41:59.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.07:41:59.41#ibcon#ireg 7 cls_cnt 0 2006.182.07:41:59.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:41:59.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:41:59.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:41:59.53#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:41:59.53#ibcon#first serial, iclass 34, count 0 2006.182.07:41:59.53#ibcon#enter sib2, iclass 34, count 0 2006.182.07:41:59.53#ibcon#flushed, iclass 34, count 0 2006.182.07:41:59.53#ibcon#about to write, iclass 34, count 0 2006.182.07:41:59.53#ibcon#wrote, iclass 34, count 0 2006.182.07:41:59.53#ibcon#about to read 3, iclass 34, count 0 2006.182.07:41:59.55#ibcon#read 3, iclass 34, count 0 2006.182.07:41:59.55#ibcon#about to read 4, iclass 34, count 0 2006.182.07:41:59.55#ibcon#read 4, iclass 34, count 0 2006.182.07:41:59.55#ibcon#about to read 5, iclass 34, count 0 2006.182.07:41:59.55#ibcon#read 5, iclass 34, count 0 2006.182.07:41:59.55#ibcon#about to read 6, iclass 34, count 0 2006.182.07:41:59.55#ibcon#read 6, iclass 34, count 0 2006.182.07:41:59.55#ibcon#end of sib2, iclass 34, count 0 2006.182.07:41:59.55#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:41:59.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:41:59.55#ibcon#[25=USB\r\n] 2006.182.07:41:59.55#ibcon#*before write, iclass 34, count 0 2006.182.07:41:59.55#ibcon#enter sib2, iclass 34, count 0 2006.182.07:41:59.55#ibcon#flushed, iclass 34, count 0 2006.182.07:41:59.55#ibcon#about to write, iclass 34, count 0 2006.182.07:41:59.55#ibcon#wrote, iclass 34, count 0 2006.182.07:41:59.55#ibcon#about to read 3, iclass 34, count 0 2006.182.07:41:59.58#ibcon#read 3, iclass 34, count 0 2006.182.07:41:59.58#ibcon#about to read 4, iclass 34, count 0 2006.182.07:41:59.58#ibcon#read 4, iclass 34, count 0 2006.182.07:41:59.58#ibcon#about to read 5, iclass 34, count 0 2006.182.07:41:59.58#ibcon#read 5, iclass 34, count 0 2006.182.07:41:59.58#ibcon#about to read 6, iclass 34, count 0 2006.182.07:41:59.58#ibcon#read 6, iclass 34, count 0 2006.182.07:41:59.58#ibcon#end of sib2, iclass 34, count 0 2006.182.07:41:59.58#ibcon#*after write, iclass 34, count 0 2006.182.07:41:59.58#ibcon#*before return 0, iclass 34, count 0 2006.182.07:41:59.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:41:59.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:41:59.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:41:59.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:41:59.58$vc4f8/valo=6,772.99 2006.182.07:41:59.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.07:41:59.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.07:41:59.58#ibcon#ireg 17 cls_cnt 0 2006.182.07:41:59.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:41:59.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:41:59.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:41:59.58#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:41:59.58#ibcon#first serial, iclass 36, count 0 2006.182.07:41:59.58#ibcon#enter sib2, iclass 36, count 0 2006.182.07:41:59.58#ibcon#flushed, iclass 36, count 0 2006.182.07:41:59.58#ibcon#about to write, iclass 36, count 0 2006.182.07:41:59.58#ibcon#wrote, iclass 36, count 0 2006.182.07:41:59.58#ibcon#about to read 3, iclass 36, count 0 2006.182.07:41:59.60#ibcon#read 3, iclass 36, count 0 2006.182.07:41:59.60#ibcon#about to read 4, iclass 36, count 0 2006.182.07:41:59.60#ibcon#read 4, iclass 36, count 0 2006.182.07:41:59.60#ibcon#about to read 5, iclass 36, count 0 2006.182.07:41:59.60#ibcon#read 5, iclass 36, count 0 2006.182.07:41:59.60#ibcon#about to read 6, iclass 36, count 0 2006.182.07:41:59.60#ibcon#read 6, iclass 36, count 0 2006.182.07:41:59.60#ibcon#end of sib2, iclass 36, count 0 2006.182.07:41:59.60#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:41:59.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:41:59.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:41:59.60#ibcon#*before write, iclass 36, count 0 2006.182.07:41:59.60#ibcon#enter sib2, iclass 36, count 0 2006.182.07:41:59.60#ibcon#flushed, iclass 36, count 0 2006.182.07:41:59.60#ibcon#about to write, iclass 36, count 0 2006.182.07:41:59.60#ibcon#wrote, iclass 36, count 0 2006.182.07:41:59.60#ibcon#about to read 3, iclass 36, count 0 2006.182.07:41:59.64#ibcon#read 3, iclass 36, count 0 2006.182.07:41:59.64#ibcon#about to read 4, iclass 36, count 0 2006.182.07:41:59.64#ibcon#read 4, iclass 36, count 0 2006.182.07:41:59.64#ibcon#about to read 5, iclass 36, count 0 2006.182.07:41:59.64#ibcon#read 5, iclass 36, count 0 2006.182.07:41:59.64#ibcon#about to read 6, iclass 36, count 0 2006.182.07:41:59.64#ibcon#read 6, iclass 36, count 0 2006.182.07:41:59.64#ibcon#end of sib2, iclass 36, count 0 2006.182.07:41:59.64#ibcon#*after write, iclass 36, count 0 2006.182.07:41:59.64#ibcon#*before return 0, iclass 36, count 0 2006.182.07:41:59.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:41:59.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:41:59.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:41:59.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:41:59.64$vc4f8/va=6,6 2006.182.07:41:59.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.07:41:59.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.07:41:59.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:41:59.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:41:59.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:41:59.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:41:59.70#ibcon#enter wrdev, iclass 38, count 2 2006.182.07:41:59.70#ibcon#first serial, iclass 38, count 2 2006.182.07:41:59.70#ibcon#enter sib2, iclass 38, count 2 2006.182.07:41:59.70#ibcon#flushed, iclass 38, count 2 2006.182.07:41:59.70#ibcon#about to write, iclass 38, count 2 2006.182.07:41:59.70#ibcon#wrote, iclass 38, count 2 2006.182.07:41:59.70#ibcon#about to read 3, iclass 38, count 2 2006.182.07:41:59.72#ibcon#read 3, iclass 38, count 2 2006.182.07:41:59.72#ibcon#about to read 4, iclass 38, count 2 2006.182.07:41:59.72#ibcon#read 4, iclass 38, count 2 2006.182.07:41:59.72#ibcon#about to read 5, iclass 38, count 2 2006.182.07:41:59.72#ibcon#read 5, iclass 38, count 2 2006.182.07:41:59.72#ibcon#about to read 6, iclass 38, count 2 2006.182.07:41:59.72#ibcon#read 6, iclass 38, count 2 2006.182.07:41:59.72#ibcon#end of sib2, iclass 38, count 2 2006.182.07:41:59.72#ibcon#*mode == 0, iclass 38, count 2 2006.182.07:41:59.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.07:41:59.72#ibcon#[25=AT06-06\r\n] 2006.182.07:41:59.72#ibcon#*before write, iclass 38, count 2 2006.182.07:41:59.72#ibcon#enter sib2, iclass 38, count 2 2006.182.07:41:59.72#ibcon#flushed, iclass 38, count 2 2006.182.07:41:59.72#ibcon#about to write, iclass 38, count 2 2006.182.07:41:59.72#ibcon#wrote, iclass 38, count 2 2006.182.07:41:59.72#ibcon#about to read 3, iclass 38, count 2 2006.182.07:41:59.75#ibcon#read 3, iclass 38, count 2 2006.182.07:41:59.75#ibcon#about to read 4, iclass 38, count 2 2006.182.07:41:59.75#ibcon#read 4, iclass 38, count 2 2006.182.07:41:59.75#ibcon#about to read 5, iclass 38, count 2 2006.182.07:41:59.75#ibcon#read 5, iclass 38, count 2 2006.182.07:41:59.75#ibcon#about to read 6, iclass 38, count 2 2006.182.07:41:59.75#ibcon#read 6, iclass 38, count 2 2006.182.07:41:59.75#ibcon#end of sib2, iclass 38, count 2 2006.182.07:41:59.75#ibcon#*after write, iclass 38, count 2 2006.182.07:41:59.75#ibcon#*before return 0, iclass 38, count 2 2006.182.07:41:59.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:41:59.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:41:59.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.07:41:59.75#ibcon#ireg 7 cls_cnt 0 2006.182.07:41:59.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:41:59.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:41:59.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:41:59.87#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:41:59.87#ibcon#first serial, iclass 38, count 0 2006.182.07:41:59.87#ibcon#enter sib2, iclass 38, count 0 2006.182.07:41:59.87#ibcon#flushed, iclass 38, count 0 2006.182.07:41:59.87#ibcon#about to write, iclass 38, count 0 2006.182.07:41:59.87#ibcon#wrote, iclass 38, count 0 2006.182.07:41:59.87#ibcon#about to read 3, iclass 38, count 0 2006.182.07:41:59.89#ibcon#read 3, iclass 38, count 0 2006.182.07:41:59.89#ibcon#about to read 4, iclass 38, count 0 2006.182.07:41:59.89#ibcon#read 4, iclass 38, count 0 2006.182.07:41:59.89#ibcon#about to read 5, iclass 38, count 0 2006.182.07:41:59.89#ibcon#read 5, iclass 38, count 0 2006.182.07:41:59.89#ibcon#about to read 6, iclass 38, count 0 2006.182.07:41:59.89#ibcon#read 6, iclass 38, count 0 2006.182.07:41:59.89#ibcon#end of sib2, iclass 38, count 0 2006.182.07:41:59.89#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:41:59.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:41:59.89#ibcon#[25=USB\r\n] 2006.182.07:41:59.89#ibcon#*before write, iclass 38, count 0 2006.182.07:41:59.89#ibcon#enter sib2, iclass 38, count 0 2006.182.07:41:59.89#ibcon#flushed, iclass 38, count 0 2006.182.07:41:59.89#ibcon#about to write, iclass 38, count 0 2006.182.07:41:59.89#ibcon#wrote, iclass 38, count 0 2006.182.07:41:59.89#ibcon#about to read 3, iclass 38, count 0 2006.182.07:41:59.92#ibcon#read 3, iclass 38, count 0 2006.182.07:41:59.92#ibcon#about to read 4, iclass 38, count 0 2006.182.07:41:59.92#ibcon#read 4, iclass 38, count 0 2006.182.07:41:59.92#ibcon#about to read 5, iclass 38, count 0 2006.182.07:41:59.92#ibcon#read 5, iclass 38, count 0 2006.182.07:41:59.92#ibcon#about to read 6, iclass 38, count 0 2006.182.07:41:59.92#ibcon#read 6, iclass 38, count 0 2006.182.07:41:59.92#ibcon#end of sib2, iclass 38, count 0 2006.182.07:41:59.92#ibcon#*after write, iclass 38, count 0 2006.182.07:41:59.92#ibcon#*before return 0, iclass 38, count 0 2006.182.07:41:59.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:41:59.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:41:59.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:41:59.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:41:59.92$vc4f8/valo=7,832.99 2006.182.07:41:59.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.07:41:59.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.07:41:59.92#ibcon#ireg 17 cls_cnt 0 2006.182.07:41:59.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:41:59.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:41:59.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:41:59.92#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:41:59.92#ibcon#first serial, iclass 40, count 0 2006.182.07:41:59.92#ibcon#enter sib2, iclass 40, count 0 2006.182.07:41:59.92#ibcon#flushed, iclass 40, count 0 2006.182.07:41:59.92#ibcon#about to write, iclass 40, count 0 2006.182.07:41:59.92#ibcon#wrote, iclass 40, count 0 2006.182.07:41:59.92#ibcon#about to read 3, iclass 40, count 0 2006.182.07:41:59.94#ibcon#read 3, iclass 40, count 0 2006.182.07:41:59.94#ibcon#about to read 4, iclass 40, count 0 2006.182.07:41:59.94#ibcon#read 4, iclass 40, count 0 2006.182.07:41:59.94#ibcon#about to read 5, iclass 40, count 0 2006.182.07:41:59.94#ibcon#read 5, iclass 40, count 0 2006.182.07:41:59.94#ibcon#about to read 6, iclass 40, count 0 2006.182.07:41:59.94#ibcon#read 6, iclass 40, count 0 2006.182.07:41:59.94#ibcon#end of sib2, iclass 40, count 0 2006.182.07:41:59.94#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:41:59.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:41:59.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:41:59.94#ibcon#*before write, iclass 40, count 0 2006.182.07:41:59.94#ibcon#enter sib2, iclass 40, count 0 2006.182.07:41:59.94#ibcon#flushed, iclass 40, count 0 2006.182.07:41:59.94#ibcon#about to write, iclass 40, count 0 2006.182.07:41:59.94#ibcon#wrote, iclass 40, count 0 2006.182.07:41:59.94#ibcon#about to read 3, iclass 40, count 0 2006.182.07:41:59.98#ibcon#read 3, iclass 40, count 0 2006.182.07:41:59.98#ibcon#about to read 4, iclass 40, count 0 2006.182.07:41:59.98#ibcon#read 4, iclass 40, count 0 2006.182.07:41:59.98#ibcon#about to read 5, iclass 40, count 0 2006.182.07:41:59.98#ibcon#read 5, iclass 40, count 0 2006.182.07:41:59.98#ibcon#about to read 6, iclass 40, count 0 2006.182.07:41:59.98#ibcon#read 6, iclass 40, count 0 2006.182.07:41:59.98#ibcon#end of sib2, iclass 40, count 0 2006.182.07:41:59.98#ibcon#*after write, iclass 40, count 0 2006.182.07:41:59.98#ibcon#*before return 0, iclass 40, count 0 2006.182.07:41:59.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:41:59.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:41:59.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:41:59.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:41:59.98$vc4f8/va=7,6 2006.182.07:41:59.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.07:41:59.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.07:41:59.98#ibcon#ireg 11 cls_cnt 2 2006.182.07:41:59.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:42:00.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:42:00.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:42:00.04#ibcon#enter wrdev, iclass 4, count 2 2006.182.07:42:00.04#ibcon#first serial, iclass 4, count 2 2006.182.07:42:00.04#ibcon#enter sib2, iclass 4, count 2 2006.182.07:42:00.04#ibcon#flushed, iclass 4, count 2 2006.182.07:42:00.04#ibcon#about to write, iclass 4, count 2 2006.182.07:42:00.04#ibcon#wrote, iclass 4, count 2 2006.182.07:42:00.04#ibcon#about to read 3, iclass 4, count 2 2006.182.07:42:00.06#ibcon#read 3, iclass 4, count 2 2006.182.07:42:00.06#ibcon#about to read 4, iclass 4, count 2 2006.182.07:42:00.06#ibcon#read 4, iclass 4, count 2 2006.182.07:42:00.06#ibcon#about to read 5, iclass 4, count 2 2006.182.07:42:00.06#ibcon#read 5, iclass 4, count 2 2006.182.07:42:00.06#ibcon#about to read 6, iclass 4, count 2 2006.182.07:42:00.06#ibcon#read 6, iclass 4, count 2 2006.182.07:42:00.06#ibcon#end of sib2, iclass 4, count 2 2006.182.07:42:00.06#ibcon#*mode == 0, iclass 4, count 2 2006.182.07:42:00.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.07:42:00.06#ibcon#[25=AT07-06\r\n] 2006.182.07:42:00.06#ibcon#*before write, iclass 4, count 2 2006.182.07:42:00.06#ibcon#enter sib2, iclass 4, count 2 2006.182.07:42:00.06#ibcon#flushed, iclass 4, count 2 2006.182.07:42:00.06#ibcon#about to write, iclass 4, count 2 2006.182.07:42:00.06#ibcon#wrote, iclass 4, count 2 2006.182.07:42:00.06#ibcon#about to read 3, iclass 4, count 2 2006.182.07:42:00.09#ibcon#read 3, iclass 4, count 2 2006.182.07:42:00.09#ibcon#about to read 4, iclass 4, count 2 2006.182.07:42:00.09#ibcon#read 4, iclass 4, count 2 2006.182.07:42:00.09#ibcon#about to read 5, iclass 4, count 2 2006.182.07:42:00.09#ibcon#read 5, iclass 4, count 2 2006.182.07:42:00.09#ibcon#about to read 6, iclass 4, count 2 2006.182.07:42:00.09#ibcon#read 6, iclass 4, count 2 2006.182.07:42:00.09#ibcon#end of sib2, iclass 4, count 2 2006.182.07:42:00.09#ibcon#*after write, iclass 4, count 2 2006.182.07:42:00.09#ibcon#*before return 0, iclass 4, count 2 2006.182.07:42:00.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:42:00.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:42:00.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.07:42:00.09#ibcon#ireg 7 cls_cnt 0 2006.182.07:42:00.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:42:00.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:42:00.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:42:00.21#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:42:00.21#ibcon#first serial, iclass 4, count 0 2006.182.07:42:00.21#ibcon#enter sib2, iclass 4, count 0 2006.182.07:42:00.21#ibcon#flushed, iclass 4, count 0 2006.182.07:42:00.21#ibcon#about to write, iclass 4, count 0 2006.182.07:42:00.21#ibcon#wrote, iclass 4, count 0 2006.182.07:42:00.21#ibcon#about to read 3, iclass 4, count 0 2006.182.07:42:00.23#ibcon#read 3, iclass 4, count 0 2006.182.07:42:00.23#ibcon#about to read 4, iclass 4, count 0 2006.182.07:42:00.23#ibcon#read 4, iclass 4, count 0 2006.182.07:42:00.23#ibcon#about to read 5, iclass 4, count 0 2006.182.07:42:00.23#ibcon#read 5, iclass 4, count 0 2006.182.07:42:00.23#ibcon#about to read 6, iclass 4, count 0 2006.182.07:42:00.23#ibcon#read 6, iclass 4, count 0 2006.182.07:42:00.23#ibcon#end of sib2, iclass 4, count 0 2006.182.07:42:00.23#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:42:00.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:42:00.23#ibcon#[25=USB\r\n] 2006.182.07:42:00.23#ibcon#*before write, iclass 4, count 0 2006.182.07:42:00.23#ibcon#enter sib2, iclass 4, count 0 2006.182.07:42:00.23#ibcon#flushed, iclass 4, count 0 2006.182.07:42:00.23#ibcon#about to write, iclass 4, count 0 2006.182.07:42:00.23#ibcon#wrote, iclass 4, count 0 2006.182.07:42:00.23#ibcon#about to read 3, iclass 4, count 0 2006.182.07:42:00.26#ibcon#read 3, iclass 4, count 0 2006.182.07:42:00.26#ibcon#about to read 4, iclass 4, count 0 2006.182.07:42:00.26#ibcon#read 4, iclass 4, count 0 2006.182.07:42:00.26#ibcon#about to read 5, iclass 4, count 0 2006.182.07:42:00.26#ibcon#read 5, iclass 4, count 0 2006.182.07:42:00.26#ibcon#about to read 6, iclass 4, count 0 2006.182.07:42:00.26#ibcon#read 6, iclass 4, count 0 2006.182.07:42:00.26#ibcon#end of sib2, iclass 4, count 0 2006.182.07:42:00.26#ibcon#*after write, iclass 4, count 0 2006.182.07:42:00.26#ibcon#*before return 0, iclass 4, count 0 2006.182.07:42:00.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:42:00.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:42:00.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:42:00.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:42:00.26$vc4f8/valo=8,852.99 2006.182.07:42:00.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.07:42:00.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.07:42:00.26#ibcon#ireg 17 cls_cnt 0 2006.182.07:42:00.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:42:00.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:42:00.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:42:00.26#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:42:00.26#ibcon#first serial, iclass 6, count 0 2006.182.07:42:00.26#ibcon#enter sib2, iclass 6, count 0 2006.182.07:42:00.26#ibcon#flushed, iclass 6, count 0 2006.182.07:42:00.26#ibcon#about to write, iclass 6, count 0 2006.182.07:42:00.26#ibcon#wrote, iclass 6, count 0 2006.182.07:42:00.26#ibcon#about to read 3, iclass 6, count 0 2006.182.07:42:00.28#ibcon#read 3, iclass 6, count 0 2006.182.07:42:00.28#ibcon#about to read 4, iclass 6, count 0 2006.182.07:42:00.28#ibcon#read 4, iclass 6, count 0 2006.182.07:42:00.28#ibcon#about to read 5, iclass 6, count 0 2006.182.07:42:00.28#ibcon#read 5, iclass 6, count 0 2006.182.07:42:00.28#ibcon#about to read 6, iclass 6, count 0 2006.182.07:42:00.28#ibcon#read 6, iclass 6, count 0 2006.182.07:42:00.28#ibcon#end of sib2, iclass 6, count 0 2006.182.07:42:00.28#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:42:00.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:42:00.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:42:00.28#ibcon#*before write, iclass 6, count 0 2006.182.07:42:00.28#ibcon#enter sib2, iclass 6, count 0 2006.182.07:42:00.28#ibcon#flushed, iclass 6, count 0 2006.182.07:42:00.28#ibcon#about to write, iclass 6, count 0 2006.182.07:42:00.28#ibcon#wrote, iclass 6, count 0 2006.182.07:42:00.28#ibcon#about to read 3, iclass 6, count 0 2006.182.07:42:00.32#ibcon#read 3, iclass 6, count 0 2006.182.07:42:00.32#ibcon#about to read 4, iclass 6, count 0 2006.182.07:42:00.32#ibcon#read 4, iclass 6, count 0 2006.182.07:42:00.32#ibcon#about to read 5, iclass 6, count 0 2006.182.07:42:00.32#ibcon#read 5, iclass 6, count 0 2006.182.07:42:00.32#ibcon#about to read 6, iclass 6, count 0 2006.182.07:42:00.32#ibcon#read 6, iclass 6, count 0 2006.182.07:42:00.32#ibcon#end of sib2, iclass 6, count 0 2006.182.07:42:00.32#ibcon#*after write, iclass 6, count 0 2006.182.07:42:00.32#ibcon#*before return 0, iclass 6, count 0 2006.182.07:42:00.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:42:00.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:42:00.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:42:00.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:42:00.32$vc4f8/va=8,7 2006.182.07:42:00.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.07:42:00.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.07:42:00.32#ibcon#ireg 11 cls_cnt 2 2006.182.07:42:00.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:42:00.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:42:00.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:42:00.38#ibcon#enter wrdev, iclass 10, count 2 2006.182.07:42:00.38#ibcon#first serial, iclass 10, count 2 2006.182.07:42:00.38#ibcon#enter sib2, iclass 10, count 2 2006.182.07:42:00.38#ibcon#flushed, iclass 10, count 2 2006.182.07:42:00.38#ibcon#about to write, iclass 10, count 2 2006.182.07:42:00.38#ibcon#wrote, iclass 10, count 2 2006.182.07:42:00.38#ibcon#about to read 3, iclass 10, count 2 2006.182.07:42:00.40#ibcon#read 3, iclass 10, count 2 2006.182.07:42:00.40#ibcon#about to read 4, iclass 10, count 2 2006.182.07:42:00.40#ibcon#read 4, iclass 10, count 2 2006.182.07:42:00.40#ibcon#about to read 5, iclass 10, count 2 2006.182.07:42:00.40#ibcon#read 5, iclass 10, count 2 2006.182.07:42:00.40#ibcon#about to read 6, iclass 10, count 2 2006.182.07:42:00.40#ibcon#read 6, iclass 10, count 2 2006.182.07:42:00.40#ibcon#end of sib2, iclass 10, count 2 2006.182.07:42:00.40#ibcon#*mode == 0, iclass 10, count 2 2006.182.07:42:00.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.07:42:00.40#ibcon#[25=AT08-07\r\n] 2006.182.07:42:00.40#ibcon#*before write, iclass 10, count 2 2006.182.07:42:00.40#ibcon#enter sib2, iclass 10, count 2 2006.182.07:42:00.40#ibcon#flushed, iclass 10, count 2 2006.182.07:42:00.40#ibcon#about to write, iclass 10, count 2 2006.182.07:42:00.40#ibcon#wrote, iclass 10, count 2 2006.182.07:42:00.40#ibcon#about to read 3, iclass 10, count 2 2006.182.07:42:00.43#ibcon#read 3, iclass 10, count 2 2006.182.07:42:00.43#ibcon#about to read 4, iclass 10, count 2 2006.182.07:42:00.43#ibcon#read 4, iclass 10, count 2 2006.182.07:42:00.43#ibcon#about to read 5, iclass 10, count 2 2006.182.07:42:00.43#ibcon#read 5, iclass 10, count 2 2006.182.07:42:00.43#ibcon#about to read 6, iclass 10, count 2 2006.182.07:42:00.43#ibcon#read 6, iclass 10, count 2 2006.182.07:42:00.43#ibcon#end of sib2, iclass 10, count 2 2006.182.07:42:00.43#ibcon#*after write, iclass 10, count 2 2006.182.07:42:00.43#ibcon#*before return 0, iclass 10, count 2 2006.182.07:42:00.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:42:00.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:42:00.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.07:42:00.43#ibcon#ireg 7 cls_cnt 0 2006.182.07:42:00.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:42:00.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:42:00.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:42:00.55#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:42:00.55#ibcon#first serial, iclass 10, count 0 2006.182.07:42:00.55#ibcon#enter sib2, iclass 10, count 0 2006.182.07:42:00.55#ibcon#flushed, iclass 10, count 0 2006.182.07:42:00.55#ibcon#about to write, iclass 10, count 0 2006.182.07:42:00.55#ibcon#wrote, iclass 10, count 0 2006.182.07:42:00.55#ibcon#about to read 3, iclass 10, count 0 2006.182.07:42:00.57#ibcon#read 3, iclass 10, count 0 2006.182.07:42:00.57#ibcon#about to read 4, iclass 10, count 0 2006.182.07:42:00.57#ibcon#read 4, iclass 10, count 0 2006.182.07:42:00.57#ibcon#about to read 5, iclass 10, count 0 2006.182.07:42:00.57#ibcon#read 5, iclass 10, count 0 2006.182.07:42:00.57#ibcon#about to read 6, iclass 10, count 0 2006.182.07:42:00.57#ibcon#read 6, iclass 10, count 0 2006.182.07:42:00.57#ibcon#end of sib2, iclass 10, count 0 2006.182.07:42:00.57#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:42:00.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:42:00.57#ibcon#[25=USB\r\n] 2006.182.07:42:00.57#ibcon#*before write, iclass 10, count 0 2006.182.07:42:00.57#ibcon#enter sib2, iclass 10, count 0 2006.182.07:42:00.57#ibcon#flushed, iclass 10, count 0 2006.182.07:42:00.57#ibcon#about to write, iclass 10, count 0 2006.182.07:42:00.57#ibcon#wrote, iclass 10, count 0 2006.182.07:42:00.57#ibcon#about to read 3, iclass 10, count 0 2006.182.07:42:00.60#ibcon#read 3, iclass 10, count 0 2006.182.07:42:00.60#ibcon#about to read 4, iclass 10, count 0 2006.182.07:42:00.60#ibcon#read 4, iclass 10, count 0 2006.182.07:42:00.60#ibcon#about to read 5, iclass 10, count 0 2006.182.07:42:00.60#ibcon#read 5, iclass 10, count 0 2006.182.07:42:00.60#ibcon#about to read 6, iclass 10, count 0 2006.182.07:42:00.60#ibcon#read 6, iclass 10, count 0 2006.182.07:42:00.60#ibcon#end of sib2, iclass 10, count 0 2006.182.07:42:00.60#ibcon#*after write, iclass 10, count 0 2006.182.07:42:00.60#ibcon#*before return 0, iclass 10, count 0 2006.182.07:42:00.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:42:00.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:42:00.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:42:00.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:42:00.60$vc4f8/vblo=1,632.99 2006.182.07:42:00.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.07:42:00.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.07:42:00.60#ibcon#ireg 17 cls_cnt 0 2006.182.07:42:00.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:42:00.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:42:00.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:42:00.60#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:42:00.60#ibcon#first serial, iclass 12, count 0 2006.182.07:42:00.60#ibcon#enter sib2, iclass 12, count 0 2006.182.07:42:00.60#ibcon#flushed, iclass 12, count 0 2006.182.07:42:00.60#ibcon#about to write, iclass 12, count 0 2006.182.07:42:00.60#ibcon#wrote, iclass 12, count 0 2006.182.07:42:00.60#ibcon#about to read 3, iclass 12, count 0 2006.182.07:42:00.62#ibcon#read 3, iclass 12, count 0 2006.182.07:42:00.62#ibcon#about to read 4, iclass 12, count 0 2006.182.07:42:00.62#ibcon#read 4, iclass 12, count 0 2006.182.07:42:00.62#ibcon#about to read 5, iclass 12, count 0 2006.182.07:42:00.62#ibcon#read 5, iclass 12, count 0 2006.182.07:42:00.62#ibcon#about to read 6, iclass 12, count 0 2006.182.07:42:00.62#ibcon#read 6, iclass 12, count 0 2006.182.07:42:00.62#ibcon#end of sib2, iclass 12, count 0 2006.182.07:42:00.62#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:42:00.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:42:00.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:42:00.62#ibcon#*before write, iclass 12, count 0 2006.182.07:42:00.62#ibcon#enter sib2, iclass 12, count 0 2006.182.07:42:00.62#ibcon#flushed, iclass 12, count 0 2006.182.07:42:00.62#ibcon#about to write, iclass 12, count 0 2006.182.07:42:00.62#ibcon#wrote, iclass 12, count 0 2006.182.07:42:00.62#ibcon#about to read 3, iclass 12, count 0 2006.182.07:42:00.66#ibcon#read 3, iclass 12, count 0 2006.182.07:42:00.66#ibcon#about to read 4, iclass 12, count 0 2006.182.07:42:00.66#ibcon#read 4, iclass 12, count 0 2006.182.07:42:00.66#ibcon#about to read 5, iclass 12, count 0 2006.182.07:42:00.66#ibcon#read 5, iclass 12, count 0 2006.182.07:42:00.66#ibcon#about to read 6, iclass 12, count 0 2006.182.07:42:00.66#ibcon#read 6, iclass 12, count 0 2006.182.07:42:00.66#ibcon#end of sib2, iclass 12, count 0 2006.182.07:42:00.66#ibcon#*after write, iclass 12, count 0 2006.182.07:42:00.66#ibcon#*before return 0, iclass 12, count 0 2006.182.07:42:00.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:42:00.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:42:00.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:42:00.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:42:00.66$vc4f8/vb=1,4 2006.182.07:42:00.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.07:42:00.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.07:42:00.66#ibcon#ireg 11 cls_cnt 2 2006.182.07:42:00.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:42:00.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:42:00.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:42:00.66#ibcon#enter wrdev, iclass 14, count 2 2006.182.07:42:00.66#ibcon#first serial, iclass 14, count 2 2006.182.07:42:00.66#ibcon#enter sib2, iclass 14, count 2 2006.182.07:42:00.66#ibcon#flushed, iclass 14, count 2 2006.182.07:42:00.66#ibcon#about to write, iclass 14, count 2 2006.182.07:42:00.66#ibcon#wrote, iclass 14, count 2 2006.182.07:42:00.66#ibcon#about to read 3, iclass 14, count 2 2006.182.07:42:00.68#ibcon#read 3, iclass 14, count 2 2006.182.07:42:00.68#ibcon#about to read 4, iclass 14, count 2 2006.182.07:42:00.68#ibcon#read 4, iclass 14, count 2 2006.182.07:42:00.68#ibcon#about to read 5, iclass 14, count 2 2006.182.07:42:00.68#ibcon#read 5, iclass 14, count 2 2006.182.07:42:00.68#ibcon#about to read 6, iclass 14, count 2 2006.182.07:42:00.68#ibcon#read 6, iclass 14, count 2 2006.182.07:42:00.68#ibcon#end of sib2, iclass 14, count 2 2006.182.07:42:00.68#ibcon#*mode == 0, iclass 14, count 2 2006.182.07:42:00.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.07:42:00.68#ibcon#[27=AT01-04\r\n] 2006.182.07:42:00.68#ibcon#*before write, iclass 14, count 2 2006.182.07:42:00.68#ibcon#enter sib2, iclass 14, count 2 2006.182.07:42:00.68#ibcon#flushed, iclass 14, count 2 2006.182.07:42:00.68#ibcon#about to write, iclass 14, count 2 2006.182.07:42:00.68#ibcon#wrote, iclass 14, count 2 2006.182.07:42:00.68#ibcon#about to read 3, iclass 14, count 2 2006.182.07:42:00.71#ibcon#read 3, iclass 14, count 2 2006.182.07:42:00.71#ibcon#about to read 4, iclass 14, count 2 2006.182.07:42:00.71#ibcon#read 4, iclass 14, count 2 2006.182.07:42:00.71#ibcon#about to read 5, iclass 14, count 2 2006.182.07:42:00.71#ibcon#read 5, iclass 14, count 2 2006.182.07:42:00.71#ibcon#about to read 6, iclass 14, count 2 2006.182.07:42:00.71#ibcon#read 6, iclass 14, count 2 2006.182.07:42:00.71#ibcon#end of sib2, iclass 14, count 2 2006.182.07:42:00.71#ibcon#*after write, iclass 14, count 2 2006.182.07:42:00.71#ibcon#*before return 0, iclass 14, count 2 2006.182.07:42:00.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:42:00.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:42:00.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.07:42:00.71#ibcon#ireg 7 cls_cnt 0 2006.182.07:42:00.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:42:00.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:42:00.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:42:00.83#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:42:00.83#ibcon#first serial, iclass 14, count 0 2006.182.07:42:00.83#ibcon#enter sib2, iclass 14, count 0 2006.182.07:42:00.83#ibcon#flushed, iclass 14, count 0 2006.182.07:42:00.83#ibcon#about to write, iclass 14, count 0 2006.182.07:42:00.83#ibcon#wrote, iclass 14, count 0 2006.182.07:42:00.83#ibcon#about to read 3, iclass 14, count 0 2006.182.07:42:00.85#ibcon#read 3, iclass 14, count 0 2006.182.07:42:00.85#ibcon#about to read 4, iclass 14, count 0 2006.182.07:42:00.85#ibcon#read 4, iclass 14, count 0 2006.182.07:42:00.85#ibcon#about to read 5, iclass 14, count 0 2006.182.07:42:00.85#ibcon#read 5, iclass 14, count 0 2006.182.07:42:00.85#ibcon#about to read 6, iclass 14, count 0 2006.182.07:42:00.85#ibcon#read 6, iclass 14, count 0 2006.182.07:42:00.85#ibcon#end of sib2, iclass 14, count 0 2006.182.07:42:00.85#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:42:00.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:42:00.85#ibcon#[27=USB\r\n] 2006.182.07:42:00.85#ibcon#*before write, iclass 14, count 0 2006.182.07:42:00.85#ibcon#enter sib2, iclass 14, count 0 2006.182.07:42:00.85#ibcon#flushed, iclass 14, count 0 2006.182.07:42:00.85#ibcon#about to write, iclass 14, count 0 2006.182.07:42:00.85#ibcon#wrote, iclass 14, count 0 2006.182.07:42:00.85#ibcon#about to read 3, iclass 14, count 0 2006.182.07:42:00.88#ibcon#read 3, iclass 14, count 0 2006.182.07:42:00.88#ibcon#about to read 4, iclass 14, count 0 2006.182.07:42:00.88#ibcon#read 4, iclass 14, count 0 2006.182.07:42:00.88#ibcon#about to read 5, iclass 14, count 0 2006.182.07:42:00.88#ibcon#read 5, iclass 14, count 0 2006.182.07:42:00.88#ibcon#about to read 6, iclass 14, count 0 2006.182.07:42:00.88#ibcon#read 6, iclass 14, count 0 2006.182.07:42:00.88#ibcon#end of sib2, iclass 14, count 0 2006.182.07:42:00.88#ibcon#*after write, iclass 14, count 0 2006.182.07:42:00.88#ibcon#*before return 0, iclass 14, count 0 2006.182.07:42:00.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:42:00.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:42:00.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:42:00.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:42:00.88$vc4f8/vblo=2,640.99 2006.182.07:42:00.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.07:42:00.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.07:42:00.88#ibcon#ireg 17 cls_cnt 0 2006.182.07:42:00.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:42:00.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:42:00.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:42:00.88#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:42:00.88#ibcon#first serial, iclass 16, count 0 2006.182.07:42:00.88#ibcon#enter sib2, iclass 16, count 0 2006.182.07:42:00.88#ibcon#flushed, iclass 16, count 0 2006.182.07:42:00.88#ibcon#about to write, iclass 16, count 0 2006.182.07:42:00.88#ibcon#wrote, iclass 16, count 0 2006.182.07:42:00.88#ibcon#about to read 3, iclass 16, count 0 2006.182.07:42:00.90#ibcon#read 3, iclass 16, count 0 2006.182.07:42:00.90#ibcon#about to read 4, iclass 16, count 0 2006.182.07:42:00.90#ibcon#read 4, iclass 16, count 0 2006.182.07:42:00.90#ibcon#about to read 5, iclass 16, count 0 2006.182.07:42:00.90#ibcon#read 5, iclass 16, count 0 2006.182.07:42:00.90#ibcon#about to read 6, iclass 16, count 0 2006.182.07:42:00.90#ibcon#read 6, iclass 16, count 0 2006.182.07:42:00.90#ibcon#end of sib2, iclass 16, count 0 2006.182.07:42:00.90#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:42:00.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:42:00.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:42:00.90#ibcon#*before write, iclass 16, count 0 2006.182.07:42:00.90#ibcon#enter sib2, iclass 16, count 0 2006.182.07:42:00.90#ibcon#flushed, iclass 16, count 0 2006.182.07:42:00.90#ibcon#about to write, iclass 16, count 0 2006.182.07:42:00.90#ibcon#wrote, iclass 16, count 0 2006.182.07:42:00.90#ibcon#about to read 3, iclass 16, count 0 2006.182.07:42:00.94#ibcon#read 3, iclass 16, count 0 2006.182.07:42:00.94#ibcon#about to read 4, iclass 16, count 0 2006.182.07:42:00.94#ibcon#read 4, iclass 16, count 0 2006.182.07:42:00.94#ibcon#about to read 5, iclass 16, count 0 2006.182.07:42:00.94#ibcon#read 5, iclass 16, count 0 2006.182.07:42:00.94#ibcon#about to read 6, iclass 16, count 0 2006.182.07:42:00.94#ibcon#read 6, iclass 16, count 0 2006.182.07:42:00.94#ibcon#end of sib2, iclass 16, count 0 2006.182.07:42:00.94#ibcon#*after write, iclass 16, count 0 2006.182.07:42:00.94#ibcon#*before return 0, iclass 16, count 0 2006.182.07:42:00.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:42:00.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:42:00.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:42:00.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:42:00.94$vc4f8/vb=2,4 2006.182.07:42:00.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.07:42:00.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.07:42:00.94#ibcon#ireg 11 cls_cnt 2 2006.182.07:42:00.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:42:01.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:42:01.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:42:01.00#ibcon#enter wrdev, iclass 18, count 2 2006.182.07:42:01.00#ibcon#first serial, iclass 18, count 2 2006.182.07:42:01.00#ibcon#enter sib2, iclass 18, count 2 2006.182.07:42:01.00#ibcon#flushed, iclass 18, count 2 2006.182.07:42:01.00#ibcon#about to write, iclass 18, count 2 2006.182.07:42:01.00#ibcon#wrote, iclass 18, count 2 2006.182.07:42:01.00#ibcon#about to read 3, iclass 18, count 2 2006.182.07:42:01.02#ibcon#read 3, iclass 18, count 2 2006.182.07:42:01.02#ibcon#about to read 4, iclass 18, count 2 2006.182.07:42:01.02#ibcon#read 4, iclass 18, count 2 2006.182.07:42:01.02#ibcon#about to read 5, iclass 18, count 2 2006.182.07:42:01.02#ibcon#read 5, iclass 18, count 2 2006.182.07:42:01.02#ibcon#about to read 6, iclass 18, count 2 2006.182.07:42:01.02#ibcon#read 6, iclass 18, count 2 2006.182.07:42:01.02#ibcon#end of sib2, iclass 18, count 2 2006.182.07:42:01.02#ibcon#*mode == 0, iclass 18, count 2 2006.182.07:42:01.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.07:42:01.02#ibcon#[27=AT02-04\r\n] 2006.182.07:42:01.02#ibcon#*before write, iclass 18, count 2 2006.182.07:42:01.02#ibcon#enter sib2, iclass 18, count 2 2006.182.07:42:01.02#ibcon#flushed, iclass 18, count 2 2006.182.07:42:01.02#ibcon#about to write, iclass 18, count 2 2006.182.07:42:01.02#ibcon#wrote, iclass 18, count 2 2006.182.07:42:01.02#ibcon#about to read 3, iclass 18, count 2 2006.182.07:42:01.05#ibcon#read 3, iclass 18, count 2 2006.182.07:42:01.05#ibcon#about to read 4, iclass 18, count 2 2006.182.07:42:01.05#ibcon#read 4, iclass 18, count 2 2006.182.07:42:01.05#ibcon#about to read 5, iclass 18, count 2 2006.182.07:42:01.05#ibcon#read 5, iclass 18, count 2 2006.182.07:42:01.05#ibcon#about to read 6, iclass 18, count 2 2006.182.07:42:01.05#ibcon#read 6, iclass 18, count 2 2006.182.07:42:01.05#ibcon#end of sib2, iclass 18, count 2 2006.182.07:42:01.05#ibcon#*after write, iclass 18, count 2 2006.182.07:42:01.05#ibcon#*before return 0, iclass 18, count 2 2006.182.07:42:01.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:42:01.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:42:01.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.07:42:01.05#ibcon#ireg 7 cls_cnt 0 2006.182.07:42:01.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:42:01.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:42:01.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:42:01.17#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:42:01.17#ibcon#first serial, iclass 18, count 0 2006.182.07:42:01.17#ibcon#enter sib2, iclass 18, count 0 2006.182.07:42:01.17#ibcon#flushed, iclass 18, count 0 2006.182.07:42:01.17#ibcon#about to write, iclass 18, count 0 2006.182.07:42:01.17#ibcon#wrote, iclass 18, count 0 2006.182.07:42:01.17#ibcon#about to read 3, iclass 18, count 0 2006.182.07:42:01.19#ibcon#read 3, iclass 18, count 0 2006.182.07:42:01.19#ibcon#about to read 4, iclass 18, count 0 2006.182.07:42:01.19#ibcon#read 4, iclass 18, count 0 2006.182.07:42:01.19#ibcon#about to read 5, iclass 18, count 0 2006.182.07:42:01.19#ibcon#read 5, iclass 18, count 0 2006.182.07:42:01.19#ibcon#about to read 6, iclass 18, count 0 2006.182.07:42:01.19#ibcon#read 6, iclass 18, count 0 2006.182.07:42:01.19#ibcon#end of sib2, iclass 18, count 0 2006.182.07:42:01.19#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:42:01.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:42:01.19#ibcon#[27=USB\r\n] 2006.182.07:42:01.19#ibcon#*before write, iclass 18, count 0 2006.182.07:42:01.19#ibcon#enter sib2, iclass 18, count 0 2006.182.07:42:01.19#ibcon#flushed, iclass 18, count 0 2006.182.07:42:01.19#ibcon#about to write, iclass 18, count 0 2006.182.07:42:01.19#ibcon#wrote, iclass 18, count 0 2006.182.07:42:01.19#ibcon#about to read 3, iclass 18, count 0 2006.182.07:42:01.22#ibcon#read 3, iclass 18, count 0 2006.182.07:42:01.22#ibcon#about to read 4, iclass 18, count 0 2006.182.07:42:01.22#ibcon#read 4, iclass 18, count 0 2006.182.07:42:01.22#ibcon#about to read 5, iclass 18, count 0 2006.182.07:42:01.22#ibcon#read 5, iclass 18, count 0 2006.182.07:42:01.22#ibcon#about to read 6, iclass 18, count 0 2006.182.07:42:01.22#ibcon#read 6, iclass 18, count 0 2006.182.07:42:01.22#ibcon#end of sib2, iclass 18, count 0 2006.182.07:42:01.22#ibcon#*after write, iclass 18, count 0 2006.182.07:42:01.22#ibcon#*before return 0, iclass 18, count 0 2006.182.07:42:01.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:42:01.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:42:01.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:42:01.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:42:01.22$vc4f8/vblo=3,656.99 2006.182.07:42:01.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.07:42:01.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.07:42:01.22#ibcon#ireg 17 cls_cnt 0 2006.182.07:42:01.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:42:01.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:42:01.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:42:01.22#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:42:01.22#ibcon#first serial, iclass 20, count 0 2006.182.07:42:01.22#ibcon#enter sib2, iclass 20, count 0 2006.182.07:42:01.22#ibcon#flushed, iclass 20, count 0 2006.182.07:42:01.22#ibcon#about to write, iclass 20, count 0 2006.182.07:42:01.22#ibcon#wrote, iclass 20, count 0 2006.182.07:42:01.22#ibcon#about to read 3, iclass 20, count 0 2006.182.07:42:01.24#ibcon#read 3, iclass 20, count 0 2006.182.07:42:01.24#ibcon#about to read 4, iclass 20, count 0 2006.182.07:42:01.24#ibcon#read 4, iclass 20, count 0 2006.182.07:42:01.24#ibcon#about to read 5, iclass 20, count 0 2006.182.07:42:01.24#ibcon#read 5, iclass 20, count 0 2006.182.07:42:01.24#ibcon#about to read 6, iclass 20, count 0 2006.182.07:42:01.24#ibcon#read 6, iclass 20, count 0 2006.182.07:42:01.24#ibcon#end of sib2, iclass 20, count 0 2006.182.07:42:01.24#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:42:01.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:42:01.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:42:01.24#ibcon#*before write, iclass 20, count 0 2006.182.07:42:01.24#ibcon#enter sib2, iclass 20, count 0 2006.182.07:42:01.24#ibcon#flushed, iclass 20, count 0 2006.182.07:42:01.24#ibcon#about to write, iclass 20, count 0 2006.182.07:42:01.24#ibcon#wrote, iclass 20, count 0 2006.182.07:42:01.24#ibcon#about to read 3, iclass 20, count 0 2006.182.07:42:01.28#ibcon#read 3, iclass 20, count 0 2006.182.07:42:01.28#ibcon#about to read 4, iclass 20, count 0 2006.182.07:42:01.28#ibcon#read 4, iclass 20, count 0 2006.182.07:42:01.28#ibcon#about to read 5, iclass 20, count 0 2006.182.07:42:01.28#ibcon#read 5, iclass 20, count 0 2006.182.07:42:01.28#ibcon#about to read 6, iclass 20, count 0 2006.182.07:42:01.28#ibcon#read 6, iclass 20, count 0 2006.182.07:42:01.28#ibcon#end of sib2, iclass 20, count 0 2006.182.07:42:01.28#ibcon#*after write, iclass 20, count 0 2006.182.07:42:01.28#ibcon#*before return 0, iclass 20, count 0 2006.182.07:42:01.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:42:01.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:42:01.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:42:01.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:42:01.28$vc4f8/vb=3,4 2006.182.07:42:01.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.07:42:01.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.07:42:01.28#ibcon#ireg 11 cls_cnt 2 2006.182.07:42:01.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:42:01.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:42:01.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:42:01.34#ibcon#enter wrdev, iclass 22, count 2 2006.182.07:42:01.34#ibcon#first serial, iclass 22, count 2 2006.182.07:42:01.34#ibcon#enter sib2, iclass 22, count 2 2006.182.07:42:01.34#ibcon#flushed, iclass 22, count 2 2006.182.07:42:01.34#ibcon#about to write, iclass 22, count 2 2006.182.07:42:01.34#ibcon#wrote, iclass 22, count 2 2006.182.07:42:01.34#ibcon#about to read 3, iclass 22, count 2 2006.182.07:42:01.36#ibcon#read 3, iclass 22, count 2 2006.182.07:42:01.36#ibcon#about to read 4, iclass 22, count 2 2006.182.07:42:01.36#ibcon#read 4, iclass 22, count 2 2006.182.07:42:01.36#ibcon#about to read 5, iclass 22, count 2 2006.182.07:42:01.36#ibcon#read 5, iclass 22, count 2 2006.182.07:42:01.36#ibcon#about to read 6, iclass 22, count 2 2006.182.07:42:01.36#ibcon#read 6, iclass 22, count 2 2006.182.07:42:01.36#ibcon#end of sib2, iclass 22, count 2 2006.182.07:42:01.36#ibcon#*mode == 0, iclass 22, count 2 2006.182.07:42:01.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.07:42:01.36#ibcon#[27=AT03-04\r\n] 2006.182.07:42:01.36#ibcon#*before write, iclass 22, count 2 2006.182.07:42:01.36#ibcon#enter sib2, iclass 22, count 2 2006.182.07:42:01.36#ibcon#flushed, iclass 22, count 2 2006.182.07:42:01.36#ibcon#about to write, iclass 22, count 2 2006.182.07:42:01.36#ibcon#wrote, iclass 22, count 2 2006.182.07:42:01.36#ibcon#about to read 3, iclass 22, count 2 2006.182.07:42:01.39#ibcon#read 3, iclass 22, count 2 2006.182.07:42:01.39#ibcon#about to read 4, iclass 22, count 2 2006.182.07:42:01.39#ibcon#read 4, iclass 22, count 2 2006.182.07:42:01.39#ibcon#about to read 5, iclass 22, count 2 2006.182.07:42:01.39#ibcon#read 5, iclass 22, count 2 2006.182.07:42:01.39#ibcon#about to read 6, iclass 22, count 2 2006.182.07:42:01.39#ibcon#read 6, iclass 22, count 2 2006.182.07:42:01.39#ibcon#end of sib2, iclass 22, count 2 2006.182.07:42:01.39#ibcon#*after write, iclass 22, count 2 2006.182.07:42:01.39#ibcon#*before return 0, iclass 22, count 2 2006.182.07:42:01.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:42:01.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:42:01.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.07:42:01.39#ibcon#ireg 7 cls_cnt 0 2006.182.07:42:01.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:42:01.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:42:01.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:42:01.51#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:42:01.51#ibcon#first serial, iclass 22, count 0 2006.182.07:42:01.51#ibcon#enter sib2, iclass 22, count 0 2006.182.07:42:01.51#ibcon#flushed, iclass 22, count 0 2006.182.07:42:01.51#ibcon#about to write, iclass 22, count 0 2006.182.07:42:01.51#ibcon#wrote, iclass 22, count 0 2006.182.07:42:01.51#ibcon#about to read 3, iclass 22, count 0 2006.182.07:42:01.53#ibcon#read 3, iclass 22, count 0 2006.182.07:42:01.53#ibcon#about to read 4, iclass 22, count 0 2006.182.07:42:01.53#ibcon#read 4, iclass 22, count 0 2006.182.07:42:01.53#ibcon#about to read 5, iclass 22, count 0 2006.182.07:42:01.53#ibcon#read 5, iclass 22, count 0 2006.182.07:42:01.53#ibcon#about to read 6, iclass 22, count 0 2006.182.07:42:01.53#ibcon#read 6, iclass 22, count 0 2006.182.07:42:01.53#ibcon#end of sib2, iclass 22, count 0 2006.182.07:42:01.53#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:42:01.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:42:01.53#ibcon#[27=USB\r\n] 2006.182.07:42:01.53#ibcon#*before write, iclass 22, count 0 2006.182.07:42:01.53#ibcon#enter sib2, iclass 22, count 0 2006.182.07:42:01.53#ibcon#flushed, iclass 22, count 0 2006.182.07:42:01.53#ibcon#about to write, iclass 22, count 0 2006.182.07:42:01.53#ibcon#wrote, iclass 22, count 0 2006.182.07:42:01.53#ibcon#about to read 3, iclass 22, count 0 2006.182.07:42:01.56#ibcon#read 3, iclass 22, count 0 2006.182.07:42:01.56#ibcon#about to read 4, iclass 22, count 0 2006.182.07:42:01.56#ibcon#read 4, iclass 22, count 0 2006.182.07:42:01.56#ibcon#about to read 5, iclass 22, count 0 2006.182.07:42:01.56#ibcon#read 5, iclass 22, count 0 2006.182.07:42:01.56#ibcon#about to read 6, iclass 22, count 0 2006.182.07:42:01.56#ibcon#read 6, iclass 22, count 0 2006.182.07:42:01.56#ibcon#end of sib2, iclass 22, count 0 2006.182.07:42:01.56#ibcon#*after write, iclass 22, count 0 2006.182.07:42:01.56#ibcon#*before return 0, iclass 22, count 0 2006.182.07:42:01.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:42:01.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:42:01.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:42:01.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:42:01.56$vc4f8/vblo=4,712.99 2006.182.07:42:01.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.07:42:01.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.07:42:01.56#ibcon#ireg 17 cls_cnt 0 2006.182.07:42:01.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:42:01.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:42:01.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:42:01.56#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:42:01.56#ibcon#first serial, iclass 24, count 0 2006.182.07:42:01.56#ibcon#enter sib2, iclass 24, count 0 2006.182.07:42:01.56#ibcon#flushed, iclass 24, count 0 2006.182.07:42:01.56#ibcon#about to write, iclass 24, count 0 2006.182.07:42:01.56#ibcon#wrote, iclass 24, count 0 2006.182.07:42:01.56#ibcon#about to read 3, iclass 24, count 0 2006.182.07:42:01.58#ibcon#read 3, iclass 24, count 0 2006.182.07:42:01.58#ibcon#about to read 4, iclass 24, count 0 2006.182.07:42:01.58#ibcon#read 4, iclass 24, count 0 2006.182.07:42:01.58#ibcon#about to read 5, iclass 24, count 0 2006.182.07:42:01.58#ibcon#read 5, iclass 24, count 0 2006.182.07:42:01.58#ibcon#about to read 6, iclass 24, count 0 2006.182.07:42:01.58#ibcon#read 6, iclass 24, count 0 2006.182.07:42:01.58#ibcon#end of sib2, iclass 24, count 0 2006.182.07:42:01.58#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:42:01.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:42:01.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:42:01.58#ibcon#*before write, iclass 24, count 0 2006.182.07:42:01.58#ibcon#enter sib2, iclass 24, count 0 2006.182.07:42:01.58#ibcon#flushed, iclass 24, count 0 2006.182.07:42:01.58#ibcon#about to write, iclass 24, count 0 2006.182.07:42:01.58#ibcon#wrote, iclass 24, count 0 2006.182.07:42:01.58#ibcon#about to read 3, iclass 24, count 0 2006.182.07:42:01.62#ibcon#read 3, iclass 24, count 0 2006.182.07:42:01.62#ibcon#about to read 4, iclass 24, count 0 2006.182.07:42:01.62#ibcon#read 4, iclass 24, count 0 2006.182.07:42:01.62#ibcon#about to read 5, iclass 24, count 0 2006.182.07:42:01.62#ibcon#read 5, iclass 24, count 0 2006.182.07:42:01.62#ibcon#about to read 6, iclass 24, count 0 2006.182.07:42:01.62#ibcon#read 6, iclass 24, count 0 2006.182.07:42:01.62#ibcon#end of sib2, iclass 24, count 0 2006.182.07:42:01.62#ibcon#*after write, iclass 24, count 0 2006.182.07:42:01.62#ibcon#*before return 0, iclass 24, count 0 2006.182.07:42:01.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:42:01.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:42:01.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:42:01.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:42:01.62$vc4f8/vb=4,4 2006.182.07:42:01.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.07:42:01.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.07:42:01.62#ibcon#ireg 11 cls_cnt 2 2006.182.07:42:01.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:42:01.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:42:01.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:42:01.68#ibcon#enter wrdev, iclass 26, count 2 2006.182.07:42:01.68#ibcon#first serial, iclass 26, count 2 2006.182.07:42:01.68#ibcon#enter sib2, iclass 26, count 2 2006.182.07:42:01.68#ibcon#flushed, iclass 26, count 2 2006.182.07:42:01.68#ibcon#about to write, iclass 26, count 2 2006.182.07:42:01.68#ibcon#wrote, iclass 26, count 2 2006.182.07:42:01.68#ibcon#about to read 3, iclass 26, count 2 2006.182.07:42:01.70#ibcon#read 3, iclass 26, count 2 2006.182.07:42:01.70#ibcon#about to read 4, iclass 26, count 2 2006.182.07:42:01.70#ibcon#read 4, iclass 26, count 2 2006.182.07:42:01.70#ibcon#about to read 5, iclass 26, count 2 2006.182.07:42:01.70#ibcon#read 5, iclass 26, count 2 2006.182.07:42:01.70#ibcon#about to read 6, iclass 26, count 2 2006.182.07:42:01.70#ibcon#read 6, iclass 26, count 2 2006.182.07:42:01.70#ibcon#end of sib2, iclass 26, count 2 2006.182.07:42:01.70#ibcon#*mode == 0, iclass 26, count 2 2006.182.07:42:01.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.07:42:01.70#ibcon#[27=AT04-04\r\n] 2006.182.07:42:01.70#ibcon#*before write, iclass 26, count 2 2006.182.07:42:01.70#ibcon#enter sib2, iclass 26, count 2 2006.182.07:42:01.70#ibcon#flushed, iclass 26, count 2 2006.182.07:42:01.70#ibcon#about to write, iclass 26, count 2 2006.182.07:42:01.70#ibcon#wrote, iclass 26, count 2 2006.182.07:42:01.70#ibcon#about to read 3, iclass 26, count 2 2006.182.07:42:01.73#ibcon#read 3, iclass 26, count 2 2006.182.07:42:01.73#ibcon#about to read 4, iclass 26, count 2 2006.182.07:42:01.73#ibcon#read 4, iclass 26, count 2 2006.182.07:42:01.73#ibcon#about to read 5, iclass 26, count 2 2006.182.07:42:01.73#ibcon#read 5, iclass 26, count 2 2006.182.07:42:01.73#ibcon#about to read 6, iclass 26, count 2 2006.182.07:42:01.73#ibcon#read 6, iclass 26, count 2 2006.182.07:42:01.73#ibcon#end of sib2, iclass 26, count 2 2006.182.07:42:01.73#ibcon#*after write, iclass 26, count 2 2006.182.07:42:01.73#ibcon#*before return 0, iclass 26, count 2 2006.182.07:42:01.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:42:01.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:42:01.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.07:42:01.73#ibcon#ireg 7 cls_cnt 0 2006.182.07:42:01.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:42:01.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:42:01.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:42:01.85#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:42:01.85#ibcon#first serial, iclass 26, count 0 2006.182.07:42:01.85#ibcon#enter sib2, iclass 26, count 0 2006.182.07:42:01.85#ibcon#flushed, iclass 26, count 0 2006.182.07:42:01.85#ibcon#about to write, iclass 26, count 0 2006.182.07:42:01.85#ibcon#wrote, iclass 26, count 0 2006.182.07:42:01.85#ibcon#about to read 3, iclass 26, count 0 2006.182.07:42:01.87#ibcon#read 3, iclass 26, count 0 2006.182.07:42:01.87#ibcon#about to read 4, iclass 26, count 0 2006.182.07:42:01.87#ibcon#read 4, iclass 26, count 0 2006.182.07:42:01.87#ibcon#about to read 5, iclass 26, count 0 2006.182.07:42:01.87#ibcon#read 5, iclass 26, count 0 2006.182.07:42:01.87#ibcon#about to read 6, iclass 26, count 0 2006.182.07:42:01.87#ibcon#read 6, iclass 26, count 0 2006.182.07:42:01.87#ibcon#end of sib2, iclass 26, count 0 2006.182.07:42:01.87#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:42:01.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:42:01.87#ibcon#[27=USB\r\n] 2006.182.07:42:01.87#ibcon#*before write, iclass 26, count 0 2006.182.07:42:01.87#ibcon#enter sib2, iclass 26, count 0 2006.182.07:42:01.87#ibcon#flushed, iclass 26, count 0 2006.182.07:42:01.87#ibcon#about to write, iclass 26, count 0 2006.182.07:42:01.87#ibcon#wrote, iclass 26, count 0 2006.182.07:42:01.87#ibcon#about to read 3, iclass 26, count 0 2006.182.07:42:01.90#ibcon#read 3, iclass 26, count 0 2006.182.07:42:01.90#ibcon#about to read 4, iclass 26, count 0 2006.182.07:42:01.90#ibcon#read 4, iclass 26, count 0 2006.182.07:42:01.90#ibcon#about to read 5, iclass 26, count 0 2006.182.07:42:01.90#ibcon#read 5, iclass 26, count 0 2006.182.07:42:01.90#ibcon#about to read 6, iclass 26, count 0 2006.182.07:42:01.90#ibcon#read 6, iclass 26, count 0 2006.182.07:42:01.90#ibcon#end of sib2, iclass 26, count 0 2006.182.07:42:01.90#ibcon#*after write, iclass 26, count 0 2006.182.07:42:01.90#ibcon#*before return 0, iclass 26, count 0 2006.182.07:42:01.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:42:01.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:42:01.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:42:01.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:42:01.90$vc4f8/vblo=5,744.99 2006.182.07:42:01.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.07:42:01.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.07:42:01.90#ibcon#ireg 17 cls_cnt 0 2006.182.07:42:01.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:42:01.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:42:01.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:42:01.90#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:42:01.90#ibcon#first serial, iclass 28, count 0 2006.182.07:42:01.90#ibcon#enter sib2, iclass 28, count 0 2006.182.07:42:01.90#ibcon#flushed, iclass 28, count 0 2006.182.07:42:01.90#ibcon#about to write, iclass 28, count 0 2006.182.07:42:01.90#ibcon#wrote, iclass 28, count 0 2006.182.07:42:01.90#ibcon#about to read 3, iclass 28, count 0 2006.182.07:42:01.93#ibcon#read 3, iclass 28, count 0 2006.182.07:42:01.93#ibcon#about to read 4, iclass 28, count 0 2006.182.07:42:01.93#ibcon#read 4, iclass 28, count 0 2006.182.07:42:01.93#ibcon#about to read 5, iclass 28, count 0 2006.182.07:42:01.93#ibcon#read 5, iclass 28, count 0 2006.182.07:42:01.93#ibcon#about to read 6, iclass 28, count 0 2006.182.07:42:01.93#ibcon#read 6, iclass 28, count 0 2006.182.07:42:01.93#ibcon#end of sib2, iclass 28, count 0 2006.182.07:42:01.93#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:42:01.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:42:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:42:01.93#ibcon#*before write, iclass 28, count 0 2006.182.07:42:01.93#ibcon#enter sib2, iclass 28, count 0 2006.182.07:42:01.93#ibcon#flushed, iclass 28, count 0 2006.182.07:42:01.93#ibcon#about to write, iclass 28, count 0 2006.182.07:42:01.93#ibcon#wrote, iclass 28, count 0 2006.182.07:42:01.93#ibcon#about to read 3, iclass 28, count 0 2006.182.07:42:01.97#ibcon#read 3, iclass 28, count 0 2006.182.07:42:01.97#ibcon#about to read 4, iclass 28, count 0 2006.182.07:42:01.97#ibcon#read 4, iclass 28, count 0 2006.182.07:42:01.97#ibcon#about to read 5, iclass 28, count 0 2006.182.07:42:01.97#ibcon#read 5, iclass 28, count 0 2006.182.07:42:01.97#ibcon#about to read 6, iclass 28, count 0 2006.182.07:42:01.97#ibcon#read 6, iclass 28, count 0 2006.182.07:42:01.97#ibcon#end of sib2, iclass 28, count 0 2006.182.07:42:01.97#ibcon#*after write, iclass 28, count 0 2006.182.07:42:01.97#ibcon#*before return 0, iclass 28, count 0 2006.182.07:42:01.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:42:01.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:42:01.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:42:01.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:42:01.97$vc4f8/vb=5,4 2006.182.07:42:01.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.07:42:01.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.07:42:01.97#ibcon#ireg 11 cls_cnt 2 2006.182.07:42:01.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:42:02.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:42:02.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:42:02.02#ibcon#enter wrdev, iclass 30, count 2 2006.182.07:42:02.02#ibcon#first serial, iclass 30, count 2 2006.182.07:42:02.02#ibcon#enter sib2, iclass 30, count 2 2006.182.07:42:02.02#ibcon#flushed, iclass 30, count 2 2006.182.07:42:02.02#ibcon#about to write, iclass 30, count 2 2006.182.07:42:02.02#ibcon#wrote, iclass 30, count 2 2006.182.07:42:02.02#ibcon#about to read 3, iclass 30, count 2 2006.182.07:42:02.04#ibcon#read 3, iclass 30, count 2 2006.182.07:42:02.04#ibcon#about to read 4, iclass 30, count 2 2006.182.07:42:02.04#ibcon#read 4, iclass 30, count 2 2006.182.07:42:02.04#ibcon#about to read 5, iclass 30, count 2 2006.182.07:42:02.04#ibcon#read 5, iclass 30, count 2 2006.182.07:42:02.04#ibcon#about to read 6, iclass 30, count 2 2006.182.07:42:02.04#ibcon#read 6, iclass 30, count 2 2006.182.07:42:02.04#ibcon#end of sib2, iclass 30, count 2 2006.182.07:42:02.04#ibcon#*mode == 0, iclass 30, count 2 2006.182.07:42:02.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.07:42:02.04#ibcon#[27=AT05-04\r\n] 2006.182.07:42:02.04#ibcon#*before write, iclass 30, count 2 2006.182.07:42:02.04#ibcon#enter sib2, iclass 30, count 2 2006.182.07:42:02.04#ibcon#flushed, iclass 30, count 2 2006.182.07:42:02.04#ibcon#about to write, iclass 30, count 2 2006.182.07:42:02.04#ibcon#wrote, iclass 30, count 2 2006.182.07:42:02.04#ibcon#about to read 3, iclass 30, count 2 2006.182.07:42:02.07#ibcon#read 3, iclass 30, count 2 2006.182.07:42:02.07#ibcon#about to read 4, iclass 30, count 2 2006.182.07:42:02.07#ibcon#read 4, iclass 30, count 2 2006.182.07:42:02.07#ibcon#about to read 5, iclass 30, count 2 2006.182.07:42:02.07#ibcon#read 5, iclass 30, count 2 2006.182.07:42:02.07#ibcon#about to read 6, iclass 30, count 2 2006.182.07:42:02.07#ibcon#read 6, iclass 30, count 2 2006.182.07:42:02.07#ibcon#end of sib2, iclass 30, count 2 2006.182.07:42:02.07#ibcon#*after write, iclass 30, count 2 2006.182.07:42:02.07#ibcon#*before return 0, iclass 30, count 2 2006.182.07:42:02.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:42:02.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:42:02.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.07:42:02.07#ibcon#ireg 7 cls_cnt 0 2006.182.07:42:02.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:42:02.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:42:02.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:42:02.19#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:42:02.19#ibcon#first serial, iclass 30, count 0 2006.182.07:42:02.19#ibcon#enter sib2, iclass 30, count 0 2006.182.07:42:02.19#ibcon#flushed, iclass 30, count 0 2006.182.07:42:02.19#ibcon#about to write, iclass 30, count 0 2006.182.07:42:02.19#ibcon#wrote, iclass 30, count 0 2006.182.07:42:02.19#ibcon#about to read 3, iclass 30, count 0 2006.182.07:42:02.21#ibcon#read 3, iclass 30, count 0 2006.182.07:42:02.21#ibcon#about to read 4, iclass 30, count 0 2006.182.07:42:02.21#ibcon#read 4, iclass 30, count 0 2006.182.07:42:02.21#ibcon#about to read 5, iclass 30, count 0 2006.182.07:42:02.21#ibcon#read 5, iclass 30, count 0 2006.182.07:42:02.21#ibcon#about to read 6, iclass 30, count 0 2006.182.07:42:02.21#ibcon#read 6, iclass 30, count 0 2006.182.07:42:02.21#ibcon#end of sib2, iclass 30, count 0 2006.182.07:42:02.21#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:42:02.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:42:02.21#ibcon#[27=USB\r\n] 2006.182.07:42:02.21#ibcon#*before write, iclass 30, count 0 2006.182.07:42:02.21#ibcon#enter sib2, iclass 30, count 0 2006.182.07:42:02.21#ibcon#flushed, iclass 30, count 0 2006.182.07:42:02.21#ibcon#about to write, iclass 30, count 0 2006.182.07:42:02.21#ibcon#wrote, iclass 30, count 0 2006.182.07:42:02.21#ibcon#about to read 3, iclass 30, count 0 2006.182.07:42:02.24#ibcon#read 3, iclass 30, count 0 2006.182.07:42:02.24#ibcon#about to read 4, iclass 30, count 0 2006.182.07:42:02.24#ibcon#read 4, iclass 30, count 0 2006.182.07:42:02.24#ibcon#about to read 5, iclass 30, count 0 2006.182.07:42:02.24#ibcon#read 5, iclass 30, count 0 2006.182.07:42:02.24#ibcon#about to read 6, iclass 30, count 0 2006.182.07:42:02.24#ibcon#read 6, iclass 30, count 0 2006.182.07:42:02.24#ibcon#end of sib2, iclass 30, count 0 2006.182.07:42:02.24#ibcon#*after write, iclass 30, count 0 2006.182.07:42:02.24#ibcon#*before return 0, iclass 30, count 0 2006.182.07:42:02.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:42:02.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:42:02.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:42:02.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:42:02.24$vc4f8/vblo=6,752.99 2006.182.07:42:02.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.07:42:02.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.07:42:02.24#ibcon#ireg 17 cls_cnt 0 2006.182.07:42:02.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:42:02.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:42:02.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:42:02.24#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:42:02.24#ibcon#first serial, iclass 32, count 0 2006.182.07:42:02.24#ibcon#enter sib2, iclass 32, count 0 2006.182.07:42:02.24#ibcon#flushed, iclass 32, count 0 2006.182.07:42:02.24#ibcon#about to write, iclass 32, count 0 2006.182.07:42:02.24#ibcon#wrote, iclass 32, count 0 2006.182.07:42:02.24#ibcon#about to read 3, iclass 32, count 0 2006.182.07:42:02.26#ibcon#read 3, iclass 32, count 0 2006.182.07:42:02.26#ibcon#about to read 4, iclass 32, count 0 2006.182.07:42:02.26#ibcon#read 4, iclass 32, count 0 2006.182.07:42:02.26#ibcon#about to read 5, iclass 32, count 0 2006.182.07:42:02.26#ibcon#read 5, iclass 32, count 0 2006.182.07:42:02.26#ibcon#about to read 6, iclass 32, count 0 2006.182.07:42:02.26#ibcon#read 6, iclass 32, count 0 2006.182.07:42:02.26#ibcon#end of sib2, iclass 32, count 0 2006.182.07:42:02.26#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:42:02.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:42:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:42:02.26#ibcon#*before write, iclass 32, count 0 2006.182.07:42:02.26#ibcon#enter sib2, iclass 32, count 0 2006.182.07:42:02.26#ibcon#flushed, iclass 32, count 0 2006.182.07:42:02.26#ibcon#about to write, iclass 32, count 0 2006.182.07:42:02.26#ibcon#wrote, iclass 32, count 0 2006.182.07:42:02.26#ibcon#about to read 3, iclass 32, count 0 2006.182.07:42:02.30#ibcon#read 3, iclass 32, count 0 2006.182.07:42:02.30#ibcon#about to read 4, iclass 32, count 0 2006.182.07:42:02.30#ibcon#read 4, iclass 32, count 0 2006.182.07:42:02.30#ibcon#about to read 5, iclass 32, count 0 2006.182.07:42:02.30#ibcon#read 5, iclass 32, count 0 2006.182.07:42:02.30#ibcon#about to read 6, iclass 32, count 0 2006.182.07:42:02.30#ibcon#read 6, iclass 32, count 0 2006.182.07:42:02.30#ibcon#end of sib2, iclass 32, count 0 2006.182.07:42:02.30#ibcon#*after write, iclass 32, count 0 2006.182.07:42:02.30#ibcon#*before return 0, iclass 32, count 0 2006.182.07:42:02.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:42:02.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:42:02.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:42:02.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:42:02.30$vc4f8/vb=6,4 2006.182.07:42:02.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.07:42:02.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.07:42:02.30#ibcon#ireg 11 cls_cnt 2 2006.182.07:42:02.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:42:02.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:42:02.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:42:02.36#ibcon#enter wrdev, iclass 34, count 2 2006.182.07:42:02.36#ibcon#first serial, iclass 34, count 2 2006.182.07:42:02.36#ibcon#enter sib2, iclass 34, count 2 2006.182.07:42:02.36#ibcon#flushed, iclass 34, count 2 2006.182.07:42:02.36#ibcon#about to write, iclass 34, count 2 2006.182.07:42:02.36#ibcon#wrote, iclass 34, count 2 2006.182.07:42:02.36#ibcon#about to read 3, iclass 34, count 2 2006.182.07:42:02.38#ibcon#read 3, iclass 34, count 2 2006.182.07:42:02.38#ibcon#about to read 4, iclass 34, count 2 2006.182.07:42:02.38#ibcon#read 4, iclass 34, count 2 2006.182.07:42:02.38#ibcon#about to read 5, iclass 34, count 2 2006.182.07:42:02.38#ibcon#read 5, iclass 34, count 2 2006.182.07:42:02.38#ibcon#about to read 6, iclass 34, count 2 2006.182.07:42:02.38#ibcon#read 6, iclass 34, count 2 2006.182.07:42:02.38#ibcon#end of sib2, iclass 34, count 2 2006.182.07:42:02.38#ibcon#*mode == 0, iclass 34, count 2 2006.182.07:42:02.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.07:42:02.38#ibcon#[27=AT06-04\r\n] 2006.182.07:42:02.38#ibcon#*before write, iclass 34, count 2 2006.182.07:42:02.38#ibcon#enter sib2, iclass 34, count 2 2006.182.07:42:02.38#ibcon#flushed, iclass 34, count 2 2006.182.07:42:02.38#ibcon#about to write, iclass 34, count 2 2006.182.07:42:02.38#ibcon#wrote, iclass 34, count 2 2006.182.07:42:02.38#ibcon#about to read 3, iclass 34, count 2 2006.182.07:42:02.41#ibcon#read 3, iclass 34, count 2 2006.182.07:42:02.41#ibcon#about to read 4, iclass 34, count 2 2006.182.07:42:02.41#ibcon#read 4, iclass 34, count 2 2006.182.07:42:02.41#ibcon#about to read 5, iclass 34, count 2 2006.182.07:42:02.41#ibcon#read 5, iclass 34, count 2 2006.182.07:42:02.41#ibcon#about to read 6, iclass 34, count 2 2006.182.07:42:02.41#ibcon#read 6, iclass 34, count 2 2006.182.07:42:02.41#ibcon#end of sib2, iclass 34, count 2 2006.182.07:42:02.41#ibcon#*after write, iclass 34, count 2 2006.182.07:42:02.41#ibcon#*before return 0, iclass 34, count 2 2006.182.07:42:02.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:42:02.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:42:02.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.07:42:02.41#ibcon#ireg 7 cls_cnt 0 2006.182.07:42:02.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:42:02.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:42:02.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:42:02.53#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:42:02.53#ibcon#first serial, iclass 34, count 0 2006.182.07:42:02.53#ibcon#enter sib2, iclass 34, count 0 2006.182.07:42:02.53#ibcon#flushed, iclass 34, count 0 2006.182.07:42:02.53#ibcon#about to write, iclass 34, count 0 2006.182.07:42:02.53#ibcon#wrote, iclass 34, count 0 2006.182.07:42:02.53#ibcon#about to read 3, iclass 34, count 0 2006.182.07:42:02.55#ibcon#read 3, iclass 34, count 0 2006.182.07:42:02.55#ibcon#about to read 4, iclass 34, count 0 2006.182.07:42:02.55#ibcon#read 4, iclass 34, count 0 2006.182.07:42:02.55#ibcon#about to read 5, iclass 34, count 0 2006.182.07:42:02.55#ibcon#read 5, iclass 34, count 0 2006.182.07:42:02.55#ibcon#about to read 6, iclass 34, count 0 2006.182.07:42:02.55#ibcon#read 6, iclass 34, count 0 2006.182.07:42:02.55#ibcon#end of sib2, iclass 34, count 0 2006.182.07:42:02.55#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:42:02.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:42:02.55#ibcon#[27=USB\r\n] 2006.182.07:42:02.55#ibcon#*before write, iclass 34, count 0 2006.182.07:42:02.55#ibcon#enter sib2, iclass 34, count 0 2006.182.07:42:02.55#ibcon#flushed, iclass 34, count 0 2006.182.07:42:02.55#ibcon#about to write, iclass 34, count 0 2006.182.07:42:02.55#ibcon#wrote, iclass 34, count 0 2006.182.07:42:02.55#ibcon#about to read 3, iclass 34, count 0 2006.182.07:42:02.58#ibcon#read 3, iclass 34, count 0 2006.182.07:42:02.58#ibcon#about to read 4, iclass 34, count 0 2006.182.07:42:02.58#ibcon#read 4, iclass 34, count 0 2006.182.07:42:02.58#ibcon#about to read 5, iclass 34, count 0 2006.182.07:42:02.58#ibcon#read 5, iclass 34, count 0 2006.182.07:42:02.58#ibcon#about to read 6, iclass 34, count 0 2006.182.07:42:02.58#ibcon#read 6, iclass 34, count 0 2006.182.07:42:02.58#ibcon#end of sib2, iclass 34, count 0 2006.182.07:42:02.58#ibcon#*after write, iclass 34, count 0 2006.182.07:42:02.58#ibcon#*before return 0, iclass 34, count 0 2006.182.07:42:02.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:42:02.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:42:02.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:42:02.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:42:02.58$vc4f8/vabw=wide 2006.182.07:42:02.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.07:42:02.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.07:42:02.58#ibcon#ireg 8 cls_cnt 0 2006.182.07:42:02.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:42:02.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:42:02.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:42:02.58#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:42:02.58#ibcon#first serial, iclass 36, count 0 2006.182.07:42:02.58#ibcon#enter sib2, iclass 36, count 0 2006.182.07:42:02.58#ibcon#flushed, iclass 36, count 0 2006.182.07:42:02.58#ibcon#about to write, iclass 36, count 0 2006.182.07:42:02.58#ibcon#wrote, iclass 36, count 0 2006.182.07:42:02.58#ibcon#about to read 3, iclass 36, count 0 2006.182.07:42:02.60#ibcon#read 3, iclass 36, count 0 2006.182.07:42:02.60#ibcon#about to read 4, iclass 36, count 0 2006.182.07:42:02.60#ibcon#read 4, iclass 36, count 0 2006.182.07:42:02.60#ibcon#about to read 5, iclass 36, count 0 2006.182.07:42:02.60#ibcon#read 5, iclass 36, count 0 2006.182.07:42:02.60#ibcon#about to read 6, iclass 36, count 0 2006.182.07:42:02.60#ibcon#read 6, iclass 36, count 0 2006.182.07:42:02.60#ibcon#end of sib2, iclass 36, count 0 2006.182.07:42:02.60#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:42:02.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:42:02.60#ibcon#[25=BW32\r\n] 2006.182.07:42:02.60#ibcon#*before write, iclass 36, count 0 2006.182.07:42:02.60#ibcon#enter sib2, iclass 36, count 0 2006.182.07:42:02.60#ibcon#flushed, iclass 36, count 0 2006.182.07:42:02.60#ibcon#about to write, iclass 36, count 0 2006.182.07:42:02.60#ibcon#wrote, iclass 36, count 0 2006.182.07:42:02.60#ibcon#about to read 3, iclass 36, count 0 2006.182.07:42:02.63#ibcon#read 3, iclass 36, count 0 2006.182.07:42:02.63#ibcon#about to read 4, iclass 36, count 0 2006.182.07:42:02.63#ibcon#read 4, iclass 36, count 0 2006.182.07:42:02.63#ibcon#about to read 5, iclass 36, count 0 2006.182.07:42:02.63#ibcon#read 5, iclass 36, count 0 2006.182.07:42:02.63#ibcon#about to read 6, iclass 36, count 0 2006.182.07:42:02.63#ibcon#read 6, iclass 36, count 0 2006.182.07:42:02.63#ibcon#end of sib2, iclass 36, count 0 2006.182.07:42:02.63#ibcon#*after write, iclass 36, count 0 2006.182.07:42:02.63#ibcon#*before return 0, iclass 36, count 0 2006.182.07:42:02.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:42:02.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:42:02.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:42:02.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:42:02.63$vc4f8/vbbw=wide 2006.182.07:42:02.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.07:42:02.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.07:42:02.63#ibcon#ireg 8 cls_cnt 0 2006.182.07:42:02.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:42:02.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:42:02.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:42:02.70#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:42:02.70#ibcon#first serial, iclass 38, count 0 2006.182.07:42:02.70#ibcon#enter sib2, iclass 38, count 0 2006.182.07:42:02.70#ibcon#flushed, iclass 38, count 0 2006.182.07:42:02.70#ibcon#about to write, iclass 38, count 0 2006.182.07:42:02.70#ibcon#wrote, iclass 38, count 0 2006.182.07:42:02.70#ibcon#about to read 3, iclass 38, count 0 2006.182.07:42:02.72#ibcon#read 3, iclass 38, count 0 2006.182.07:42:02.72#ibcon#about to read 4, iclass 38, count 0 2006.182.07:42:02.72#ibcon#read 4, iclass 38, count 0 2006.182.07:42:02.72#ibcon#about to read 5, iclass 38, count 0 2006.182.07:42:02.72#ibcon#read 5, iclass 38, count 0 2006.182.07:42:02.72#ibcon#about to read 6, iclass 38, count 0 2006.182.07:42:02.72#ibcon#read 6, iclass 38, count 0 2006.182.07:42:02.72#ibcon#end of sib2, iclass 38, count 0 2006.182.07:42:02.72#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:42:02.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:42:02.72#ibcon#[27=BW32\r\n] 2006.182.07:42:02.72#ibcon#*before write, iclass 38, count 0 2006.182.07:42:02.72#ibcon#enter sib2, iclass 38, count 0 2006.182.07:42:02.72#ibcon#flushed, iclass 38, count 0 2006.182.07:42:02.72#ibcon#about to write, iclass 38, count 0 2006.182.07:42:02.72#ibcon#wrote, iclass 38, count 0 2006.182.07:42:02.72#ibcon#about to read 3, iclass 38, count 0 2006.182.07:42:02.75#ibcon#read 3, iclass 38, count 0 2006.182.07:42:02.75#ibcon#about to read 4, iclass 38, count 0 2006.182.07:42:02.75#ibcon#read 4, iclass 38, count 0 2006.182.07:42:02.75#ibcon#about to read 5, iclass 38, count 0 2006.182.07:42:02.75#ibcon#read 5, iclass 38, count 0 2006.182.07:42:02.75#ibcon#about to read 6, iclass 38, count 0 2006.182.07:42:02.75#ibcon#read 6, iclass 38, count 0 2006.182.07:42:02.75#ibcon#end of sib2, iclass 38, count 0 2006.182.07:42:02.75#ibcon#*after write, iclass 38, count 0 2006.182.07:42:02.75#ibcon#*before return 0, iclass 38, count 0 2006.182.07:42:02.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:42:02.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:42:02.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:42:02.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:42:02.75$4f8m12a/ifd4f 2006.182.07:42:02.75$ifd4f/lo= 2006.182.07:42:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:42:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:42:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:42:02.75$ifd4f/patch= 2006.182.07:42:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:42:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:42:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:42:02.75$4f8m12a/"form=m,16.000,1:2 2006.182.07:42:02.75$4f8m12a/"tpicd 2006.182.07:42:02.75$4f8m12a/echo=off 2006.182.07:42:02.75$4f8m12a/xlog=off 2006.182.07:42:02.75:!2006.182.07:43:00 2006.182.07:42:40.14#trakl#Source acquired 2006.182.07:42:42.14#flagr#flagr/antenna,acquired 2006.182.07:43:00.00:preob 2006.182.07:43:01.14/onsource/TRACKING 2006.182.07:43:01.14:!2006.182.07:43:10 2006.182.07:43:10.00:data_valid=on 2006.182.07:43:10.00:midob 2006.182.07:43:10.14/onsource/TRACKING 2006.182.07:43:10.14/wx/27.52,1002.9,82 2006.182.07:43:10.34/cable/+6.4665E-03 2006.182.07:43:11.43/va/01,08,usb,yes,29,31 2006.182.07:43:11.43/va/02,07,usb,yes,30,31 2006.182.07:43:11.43/va/03,06,usb,yes,31,31 2006.182.07:43:11.43/va/04,07,usb,yes,30,33 2006.182.07:43:11.43/va/05,07,usb,yes,31,33 2006.182.07:43:11.43/va/06,06,usb,yes,30,30 2006.182.07:43:11.43/va/07,06,usb,yes,31,31 2006.182.07:43:11.43/va/08,07,usb,yes,29,29 2006.182.07:43:11.66/valo/01,532.99,yes,locked 2006.182.07:43:11.66/valo/02,572.99,yes,locked 2006.182.07:43:11.66/valo/03,672.99,yes,locked 2006.182.07:43:11.66/valo/04,832.99,yes,locked 2006.182.07:43:11.66/valo/05,652.99,yes,locked 2006.182.07:43:11.66/valo/06,772.99,yes,locked 2006.182.07:43:11.66/valo/07,832.99,yes,locked 2006.182.07:43:11.66/valo/08,852.99,yes,locked 2006.182.07:43:12.75/vb/01,04,usb,yes,29,28 2006.182.07:43:12.75/vb/02,04,usb,yes,31,33 2006.182.07:43:12.75/vb/03,04,usb,yes,27,31 2006.182.07:43:12.75/vb/04,04,usb,yes,28,28 2006.182.07:43:12.75/vb/05,04,usb,yes,27,31 2006.182.07:43:12.75/vb/06,04,usb,yes,28,30 2006.182.07:43:12.75/vb/07,04,usb,yes,30,30 2006.182.07:43:12.75/vb/08,04,usb,yes,27,31 2006.182.07:43:12.98/vblo/01,632.99,yes,locked 2006.182.07:43:12.98/vblo/02,640.99,yes,locked 2006.182.07:43:12.98/vblo/03,656.99,yes,locked 2006.182.07:43:12.98/vblo/04,712.99,yes,locked 2006.182.07:43:12.98/vblo/05,744.99,yes,locked 2006.182.07:43:12.98/vblo/06,752.99,yes,locked 2006.182.07:43:12.98/vblo/07,734.99,yes,locked 2006.182.07:43:12.98/vblo/08,744.99,yes,locked 2006.182.07:43:13.13/vabw/8 2006.182.07:43:13.28/vbbw/8 2006.182.07:43:13.37/xfe/off,on,14.5 2006.182.07:43:13.74/ifatt/23,28,28,28 2006.182.07:43:14.08/fmout-gps/S +3.36E-07 2006.182.07:43:14.12:!2006.182.07:46:10 2006.182.07:46:10.00:data_valid=off 2006.182.07:46:10.00:postob 2006.182.07:46:10.08/cable/+6.4656E-03 2006.182.07:46:10.08/wx/27.58,1002.9,81 2006.182.07:46:11.08/fmout-gps/S +3.38E-07 2006.182.07:46:11.08:scan_name=182-0747,k06182,60 2006.182.07:46:11.09:source=1739+522,174036.98,521143.4,2000.0,cw 2006.182.07:46:11.13#flagr#flagr/antenna,new-source 2006.182.07:46:12.13:checkk5 2006.182.07:46:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:46:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:46:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:46:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:46:13.99/chk_obsdata//k5ts1/T1820743??a.dat file size is correct (nominal:1440MB, actual:1432MB). 2006.182.07:46:14.36/chk_obsdata//k5ts2/T1820743??b.dat file size is correct (nominal:1440MB, actual:1432MB). 2006.182.07:46:14.72/chk_obsdata//k5ts3/T1820743??c.dat file size is correct (nominal:1440MB, actual:1432MB). 2006.182.07:46:15.09/chk_obsdata//k5ts4/T1820743??d.dat file size is correct (nominal:1440MB, actual:1432MB). 2006.182.07:46:15.79/k5log//k5ts1_log_newline 2006.182.07:46:16.49/k5log//k5ts2_log_newline 2006.182.07:46:17.18/k5log//k5ts3_log_newline 2006.182.07:46:17.88/k5log//k5ts4_log_newline 2006.182.07:46:17.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:46:17.90:4f8m12a=1 2006.182.07:46:17.90$4f8m12a/echo=on 2006.182.07:46:17.90$4f8m12a/pcalon 2006.182.07:46:17.90$pcalon/"no phase cal control is implemented here 2006.182.07:46:17.90$4f8m12a/"tpicd=stop 2006.182.07:46:17.91$4f8m12a/vc4f8 2006.182.07:46:17.91$vc4f8/valo=1,532.99 2006.182.07:46:17.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.182.07:46:17.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.182.07:46:17.91#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:17.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:17.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:17.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:17.91#ibcon#enter wrdev, iclass 33, count 0 2006.182.07:46:17.91#ibcon#first serial, iclass 33, count 0 2006.182.07:46:17.91#ibcon#enter sib2, iclass 33, count 0 2006.182.07:46:17.91#ibcon#flushed, iclass 33, count 0 2006.182.07:46:17.91#ibcon#about to write, iclass 33, count 0 2006.182.07:46:17.91#ibcon#wrote, iclass 33, count 0 2006.182.07:46:17.91#ibcon#about to read 3, iclass 33, count 0 2006.182.07:46:17.95#ibcon#read 3, iclass 33, count 0 2006.182.07:46:17.95#ibcon#about to read 4, iclass 33, count 0 2006.182.07:46:17.95#ibcon#read 4, iclass 33, count 0 2006.182.07:46:17.95#ibcon#about to read 5, iclass 33, count 0 2006.182.07:46:17.95#ibcon#read 5, iclass 33, count 0 2006.182.07:46:17.95#ibcon#about to read 6, iclass 33, count 0 2006.182.07:46:17.95#ibcon#read 6, iclass 33, count 0 2006.182.07:46:17.95#ibcon#end of sib2, iclass 33, count 0 2006.182.07:46:17.95#ibcon#*mode == 0, iclass 33, count 0 2006.182.07:46:17.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.07:46:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:46:17.95#ibcon#*before write, iclass 33, count 0 2006.182.07:46:17.95#ibcon#enter sib2, iclass 33, count 0 2006.182.07:46:17.95#ibcon#flushed, iclass 33, count 0 2006.182.07:46:17.95#ibcon#about to write, iclass 33, count 0 2006.182.07:46:17.95#ibcon#wrote, iclass 33, count 0 2006.182.07:46:17.95#ibcon#about to read 3, iclass 33, count 0 2006.182.07:46:18.00#ibcon#read 3, iclass 33, count 0 2006.182.07:46:18.00#ibcon#about to read 4, iclass 33, count 0 2006.182.07:46:18.00#ibcon#read 4, iclass 33, count 0 2006.182.07:46:18.00#ibcon#about to read 5, iclass 33, count 0 2006.182.07:46:18.00#ibcon#read 5, iclass 33, count 0 2006.182.07:46:18.00#ibcon#about to read 6, iclass 33, count 0 2006.182.07:46:18.00#ibcon#read 6, iclass 33, count 0 2006.182.07:46:18.00#ibcon#end of sib2, iclass 33, count 0 2006.182.07:46:18.00#ibcon#*after write, iclass 33, count 0 2006.182.07:46:18.00#ibcon#*before return 0, iclass 33, count 0 2006.182.07:46:18.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:18.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:18.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.07:46:18.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.07:46:18.00$vc4f8/va=1,8 2006.182.07:46:18.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.182.07:46:18.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.182.07:46:18.00#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:18.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:18.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:18.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:18.00#ibcon#enter wrdev, iclass 35, count 2 2006.182.07:46:18.00#ibcon#first serial, iclass 35, count 2 2006.182.07:46:18.00#ibcon#enter sib2, iclass 35, count 2 2006.182.07:46:18.00#ibcon#flushed, iclass 35, count 2 2006.182.07:46:18.00#ibcon#about to write, iclass 35, count 2 2006.182.07:46:18.00#ibcon#wrote, iclass 35, count 2 2006.182.07:46:18.00#ibcon#about to read 3, iclass 35, count 2 2006.182.07:46:18.02#ibcon#read 3, iclass 35, count 2 2006.182.07:46:18.02#ibcon#about to read 4, iclass 35, count 2 2006.182.07:46:18.02#ibcon#read 4, iclass 35, count 2 2006.182.07:46:18.02#ibcon#about to read 5, iclass 35, count 2 2006.182.07:46:18.02#ibcon#read 5, iclass 35, count 2 2006.182.07:46:18.02#ibcon#about to read 6, iclass 35, count 2 2006.182.07:46:18.02#ibcon#read 6, iclass 35, count 2 2006.182.07:46:18.02#ibcon#end of sib2, iclass 35, count 2 2006.182.07:46:18.02#ibcon#*mode == 0, iclass 35, count 2 2006.182.07:46:18.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.182.07:46:18.02#ibcon#[25=AT01-08\r\n] 2006.182.07:46:18.02#ibcon#*before write, iclass 35, count 2 2006.182.07:46:18.02#ibcon#enter sib2, iclass 35, count 2 2006.182.07:46:18.02#ibcon#flushed, iclass 35, count 2 2006.182.07:46:18.02#ibcon#about to write, iclass 35, count 2 2006.182.07:46:18.02#ibcon#wrote, iclass 35, count 2 2006.182.07:46:18.02#ibcon#about to read 3, iclass 35, count 2 2006.182.07:46:18.06#ibcon#read 3, iclass 35, count 2 2006.182.07:46:18.06#ibcon#about to read 4, iclass 35, count 2 2006.182.07:46:18.06#ibcon#read 4, iclass 35, count 2 2006.182.07:46:18.06#ibcon#about to read 5, iclass 35, count 2 2006.182.07:46:18.06#ibcon#read 5, iclass 35, count 2 2006.182.07:46:18.06#ibcon#about to read 6, iclass 35, count 2 2006.182.07:46:18.06#ibcon#read 6, iclass 35, count 2 2006.182.07:46:18.06#ibcon#end of sib2, iclass 35, count 2 2006.182.07:46:18.06#ibcon#*after write, iclass 35, count 2 2006.182.07:46:18.06#ibcon#*before return 0, iclass 35, count 2 2006.182.07:46:18.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:18.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:18.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.182.07:46:18.06#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:18.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:18.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:18.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:18.18#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:46:18.18#ibcon#first serial, iclass 35, count 0 2006.182.07:46:18.18#ibcon#enter sib2, iclass 35, count 0 2006.182.07:46:18.18#ibcon#flushed, iclass 35, count 0 2006.182.07:46:18.18#ibcon#about to write, iclass 35, count 0 2006.182.07:46:18.18#ibcon#wrote, iclass 35, count 0 2006.182.07:46:18.18#ibcon#about to read 3, iclass 35, count 0 2006.182.07:46:18.20#ibcon#read 3, iclass 35, count 0 2006.182.07:46:18.20#ibcon#about to read 4, iclass 35, count 0 2006.182.07:46:18.20#ibcon#read 4, iclass 35, count 0 2006.182.07:46:18.20#ibcon#about to read 5, iclass 35, count 0 2006.182.07:46:18.20#ibcon#read 5, iclass 35, count 0 2006.182.07:46:18.20#ibcon#about to read 6, iclass 35, count 0 2006.182.07:46:18.20#ibcon#read 6, iclass 35, count 0 2006.182.07:46:18.20#ibcon#end of sib2, iclass 35, count 0 2006.182.07:46:18.20#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:46:18.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:46:18.20#ibcon#[25=USB\r\n] 2006.182.07:46:18.20#ibcon#*before write, iclass 35, count 0 2006.182.07:46:18.20#ibcon#enter sib2, iclass 35, count 0 2006.182.07:46:18.20#ibcon#flushed, iclass 35, count 0 2006.182.07:46:18.20#ibcon#about to write, iclass 35, count 0 2006.182.07:46:18.20#ibcon#wrote, iclass 35, count 0 2006.182.07:46:18.20#ibcon#about to read 3, iclass 35, count 0 2006.182.07:46:18.23#abcon#<5=/08 0.6 1.9 27.58 811002.9\r\n> 2006.182.07:46:18.23#ibcon#read 3, iclass 35, count 0 2006.182.07:46:18.23#ibcon#about to read 4, iclass 35, count 0 2006.182.07:46:18.23#ibcon#read 4, iclass 35, count 0 2006.182.07:46:18.23#ibcon#about to read 5, iclass 35, count 0 2006.182.07:46:18.23#ibcon#read 5, iclass 35, count 0 2006.182.07:46:18.23#ibcon#about to read 6, iclass 35, count 0 2006.182.07:46:18.23#ibcon#read 6, iclass 35, count 0 2006.182.07:46:18.23#ibcon#end of sib2, iclass 35, count 0 2006.182.07:46:18.23#ibcon#*after write, iclass 35, count 0 2006.182.07:46:18.23#ibcon#*before return 0, iclass 35, count 0 2006.182.07:46:18.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:18.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:18.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:46:18.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:46:18.23$vc4f8/valo=2,572.99 2006.182.07:46:18.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.07:46:18.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.07:46:18.23#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:18.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:46:18.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:46:18.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:46:18.23#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:46:18.23#ibcon#first serial, iclass 40, count 0 2006.182.07:46:18.23#ibcon#enter sib2, iclass 40, count 0 2006.182.07:46:18.23#ibcon#flushed, iclass 40, count 0 2006.182.07:46:18.23#ibcon#about to write, iclass 40, count 0 2006.182.07:46:18.23#ibcon#wrote, iclass 40, count 0 2006.182.07:46:18.23#ibcon#about to read 3, iclass 40, count 0 2006.182.07:46:18.25#abcon#{5=INTERFACE CLEAR} 2006.182.07:46:18.25#ibcon#read 3, iclass 40, count 0 2006.182.07:46:18.25#ibcon#about to read 4, iclass 40, count 0 2006.182.07:46:18.25#ibcon#read 4, iclass 40, count 0 2006.182.07:46:18.25#ibcon#about to read 5, iclass 40, count 0 2006.182.07:46:18.25#ibcon#read 5, iclass 40, count 0 2006.182.07:46:18.25#ibcon#about to read 6, iclass 40, count 0 2006.182.07:46:18.25#ibcon#read 6, iclass 40, count 0 2006.182.07:46:18.25#ibcon#end of sib2, iclass 40, count 0 2006.182.07:46:18.25#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:46:18.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:46:18.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:46:18.25#ibcon#*before write, iclass 40, count 0 2006.182.07:46:18.25#ibcon#enter sib2, iclass 40, count 0 2006.182.07:46:18.25#ibcon#flushed, iclass 40, count 0 2006.182.07:46:18.25#ibcon#about to write, iclass 40, count 0 2006.182.07:46:18.25#ibcon#wrote, iclass 40, count 0 2006.182.07:46:18.25#ibcon#about to read 3, iclass 40, count 0 2006.182.07:46:18.29#ibcon#read 3, iclass 40, count 0 2006.182.07:46:18.29#ibcon#about to read 4, iclass 40, count 0 2006.182.07:46:18.29#ibcon#read 4, iclass 40, count 0 2006.182.07:46:18.29#ibcon#about to read 5, iclass 40, count 0 2006.182.07:46:18.29#ibcon#read 5, iclass 40, count 0 2006.182.07:46:18.29#ibcon#about to read 6, iclass 40, count 0 2006.182.07:46:18.29#ibcon#read 6, iclass 40, count 0 2006.182.07:46:18.29#ibcon#end of sib2, iclass 40, count 0 2006.182.07:46:18.29#ibcon#*after write, iclass 40, count 0 2006.182.07:46:18.29#ibcon#*before return 0, iclass 40, count 0 2006.182.07:46:18.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:46:18.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:46:18.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:46:18.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:46:18.29$vc4f8/va=2,7 2006.182.07:46:18.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.07:46:18.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.07:46:18.29#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:18.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:46:18.31#abcon#[5=S1D000X0/0*\r\n] 2006.182.07:46:18.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:46:18.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:46:18.35#ibcon#enter wrdev, iclass 4, count 2 2006.182.07:46:18.35#ibcon#first serial, iclass 4, count 2 2006.182.07:46:18.35#ibcon#enter sib2, iclass 4, count 2 2006.182.07:46:18.35#ibcon#flushed, iclass 4, count 2 2006.182.07:46:18.35#ibcon#about to write, iclass 4, count 2 2006.182.07:46:18.35#ibcon#wrote, iclass 4, count 2 2006.182.07:46:18.35#ibcon#about to read 3, iclass 4, count 2 2006.182.07:46:18.37#ibcon#read 3, iclass 4, count 2 2006.182.07:46:18.37#ibcon#about to read 4, iclass 4, count 2 2006.182.07:46:18.37#ibcon#read 4, iclass 4, count 2 2006.182.07:46:18.37#ibcon#about to read 5, iclass 4, count 2 2006.182.07:46:18.37#ibcon#read 5, iclass 4, count 2 2006.182.07:46:18.37#ibcon#about to read 6, iclass 4, count 2 2006.182.07:46:18.37#ibcon#read 6, iclass 4, count 2 2006.182.07:46:18.37#ibcon#end of sib2, iclass 4, count 2 2006.182.07:46:18.37#ibcon#*mode == 0, iclass 4, count 2 2006.182.07:46:18.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.07:46:18.37#ibcon#[25=AT02-07\r\n] 2006.182.07:46:18.37#ibcon#*before write, iclass 4, count 2 2006.182.07:46:18.37#ibcon#enter sib2, iclass 4, count 2 2006.182.07:46:18.37#ibcon#flushed, iclass 4, count 2 2006.182.07:46:18.37#ibcon#about to write, iclass 4, count 2 2006.182.07:46:18.37#ibcon#wrote, iclass 4, count 2 2006.182.07:46:18.37#ibcon#about to read 3, iclass 4, count 2 2006.182.07:46:18.40#ibcon#read 3, iclass 4, count 2 2006.182.07:46:18.40#ibcon#about to read 4, iclass 4, count 2 2006.182.07:46:18.40#ibcon#read 4, iclass 4, count 2 2006.182.07:46:18.40#ibcon#about to read 5, iclass 4, count 2 2006.182.07:46:18.40#ibcon#read 5, iclass 4, count 2 2006.182.07:46:18.40#ibcon#about to read 6, iclass 4, count 2 2006.182.07:46:18.40#ibcon#read 6, iclass 4, count 2 2006.182.07:46:18.40#ibcon#end of sib2, iclass 4, count 2 2006.182.07:46:18.40#ibcon#*after write, iclass 4, count 2 2006.182.07:46:18.40#ibcon#*before return 0, iclass 4, count 2 2006.182.07:46:18.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:46:18.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:46:18.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.07:46:18.40#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:18.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:46:18.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:46:18.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:46:18.52#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:46:18.52#ibcon#first serial, iclass 4, count 0 2006.182.07:46:18.52#ibcon#enter sib2, iclass 4, count 0 2006.182.07:46:18.52#ibcon#flushed, iclass 4, count 0 2006.182.07:46:18.52#ibcon#about to write, iclass 4, count 0 2006.182.07:46:18.52#ibcon#wrote, iclass 4, count 0 2006.182.07:46:18.52#ibcon#about to read 3, iclass 4, count 0 2006.182.07:46:18.54#ibcon#read 3, iclass 4, count 0 2006.182.07:46:18.54#ibcon#about to read 4, iclass 4, count 0 2006.182.07:46:18.54#ibcon#read 4, iclass 4, count 0 2006.182.07:46:18.54#ibcon#about to read 5, iclass 4, count 0 2006.182.07:46:18.54#ibcon#read 5, iclass 4, count 0 2006.182.07:46:18.54#ibcon#about to read 6, iclass 4, count 0 2006.182.07:46:18.54#ibcon#read 6, iclass 4, count 0 2006.182.07:46:18.54#ibcon#end of sib2, iclass 4, count 0 2006.182.07:46:18.54#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:46:18.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:46:18.54#ibcon#[25=USB\r\n] 2006.182.07:46:18.54#ibcon#*before write, iclass 4, count 0 2006.182.07:46:18.54#ibcon#enter sib2, iclass 4, count 0 2006.182.07:46:18.54#ibcon#flushed, iclass 4, count 0 2006.182.07:46:18.54#ibcon#about to write, iclass 4, count 0 2006.182.07:46:18.54#ibcon#wrote, iclass 4, count 0 2006.182.07:46:18.54#ibcon#about to read 3, iclass 4, count 0 2006.182.07:46:18.57#ibcon#read 3, iclass 4, count 0 2006.182.07:46:18.57#ibcon#about to read 4, iclass 4, count 0 2006.182.07:46:18.57#ibcon#read 4, iclass 4, count 0 2006.182.07:46:18.57#ibcon#about to read 5, iclass 4, count 0 2006.182.07:46:18.57#ibcon#read 5, iclass 4, count 0 2006.182.07:46:18.57#ibcon#about to read 6, iclass 4, count 0 2006.182.07:46:18.57#ibcon#read 6, iclass 4, count 0 2006.182.07:46:18.57#ibcon#end of sib2, iclass 4, count 0 2006.182.07:46:18.57#ibcon#*after write, iclass 4, count 0 2006.182.07:46:18.57#ibcon#*before return 0, iclass 4, count 0 2006.182.07:46:18.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:46:18.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:46:18.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:46:18.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:46:18.57$vc4f8/valo=3,672.99 2006.182.07:46:18.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.07:46:18.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.07:46:18.57#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:18.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:18.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:18.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:18.57#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:46:18.57#ibcon#first serial, iclass 7, count 0 2006.182.07:46:18.57#ibcon#enter sib2, iclass 7, count 0 2006.182.07:46:18.57#ibcon#flushed, iclass 7, count 0 2006.182.07:46:18.57#ibcon#about to write, iclass 7, count 0 2006.182.07:46:18.57#ibcon#wrote, iclass 7, count 0 2006.182.07:46:18.57#ibcon#about to read 3, iclass 7, count 0 2006.182.07:46:18.59#ibcon#read 3, iclass 7, count 0 2006.182.07:46:18.59#ibcon#about to read 4, iclass 7, count 0 2006.182.07:46:18.59#ibcon#read 4, iclass 7, count 0 2006.182.07:46:18.59#ibcon#about to read 5, iclass 7, count 0 2006.182.07:46:18.59#ibcon#read 5, iclass 7, count 0 2006.182.07:46:18.59#ibcon#about to read 6, iclass 7, count 0 2006.182.07:46:18.59#ibcon#read 6, iclass 7, count 0 2006.182.07:46:18.59#ibcon#end of sib2, iclass 7, count 0 2006.182.07:46:18.59#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:46:18.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:46:18.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:46:18.59#ibcon#*before write, iclass 7, count 0 2006.182.07:46:18.59#ibcon#enter sib2, iclass 7, count 0 2006.182.07:46:18.59#ibcon#flushed, iclass 7, count 0 2006.182.07:46:18.59#ibcon#about to write, iclass 7, count 0 2006.182.07:46:18.59#ibcon#wrote, iclass 7, count 0 2006.182.07:46:18.59#ibcon#about to read 3, iclass 7, count 0 2006.182.07:46:18.64#ibcon#read 3, iclass 7, count 0 2006.182.07:46:18.64#ibcon#about to read 4, iclass 7, count 0 2006.182.07:46:18.64#ibcon#read 4, iclass 7, count 0 2006.182.07:46:18.64#ibcon#about to read 5, iclass 7, count 0 2006.182.07:46:18.64#ibcon#read 5, iclass 7, count 0 2006.182.07:46:18.64#ibcon#about to read 6, iclass 7, count 0 2006.182.07:46:18.64#ibcon#read 6, iclass 7, count 0 2006.182.07:46:18.64#ibcon#end of sib2, iclass 7, count 0 2006.182.07:46:18.64#ibcon#*after write, iclass 7, count 0 2006.182.07:46:18.64#ibcon#*before return 0, iclass 7, count 0 2006.182.07:46:18.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:18.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:18.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:46:18.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:46:18.64$vc4f8/va=3,6 2006.182.07:46:18.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.07:46:18.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.07:46:18.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:18.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:18.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:18.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:18.69#ibcon#enter wrdev, iclass 11, count 2 2006.182.07:46:18.69#ibcon#first serial, iclass 11, count 2 2006.182.07:46:18.69#ibcon#enter sib2, iclass 11, count 2 2006.182.07:46:18.69#ibcon#flushed, iclass 11, count 2 2006.182.07:46:18.69#ibcon#about to write, iclass 11, count 2 2006.182.07:46:18.69#ibcon#wrote, iclass 11, count 2 2006.182.07:46:18.69#ibcon#about to read 3, iclass 11, count 2 2006.182.07:46:18.71#ibcon#read 3, iclass 11, count 2 2006.182.07:46:18.71#ibcon#about to read 4, iclass 11, count 2 2006.182.07:46:18.71#ibcon#read 4, iclass 11, count 2 2006.182.07:46:18.71#ibcon#about to read 5, iclass 11, count 2 2006.182.07:46:18.71#ibcon#read 5, iclass 11, count 2 2006.182.07:46:18.71#ibcon#about to read 6, iclass 11, count 2 2006.182.07:46:18.71#ibcon#read 6, iclass 11, count 2 2006.182.07:46:18.71#ibcon#end of sib2, iclass 11, count 2 2006.182.07:46:18.71#ibcon#*mode == 0, iclass 11, count 2 2006.182.07:46:18.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.07:46:18.71#ibcon#[25=AT03-06\r\n] 2006.182.07:46:18.71#ibcon#*before write, iclass 11, count 2 2006.182.07:46:18.71#ibcon#enter sib2, iclass 11, count 2 2006.182.07:46:18.71#ibcon#flushed, iclass 11, count 2 2006.182.07:46:18.71#ibcon#about to write, iclass 11, count 2 2006.182.07:46:18.71#ibcon#wrote, iclass 11, count 2 2006.182.07:46:18.71#ibcon#about to read 3, iclass 11, count 2 2006.182.07:46:18.74#ibcon#read 3, iclass 11, count 2 2006.182.07:46:18.74#ibcon#about to read 4, iclass 11, count 2 2006.182.07:46:18.74#ibcon#read 4, iclass 11, count 2 2006.182.07:46:18.74#ibcon#about to read 5, iclass 11, count 2 2006.182.07:46:18.74#ibcon#read 5, iclass 11, count 2 2006.182.07:46:18.74#ibcon#about to read 6, iclass 11, count 2 2006.182.07:46:18.74#ibcon#read 6, iclass 11, count 2 2006.182.07:46:18.74#ibcon#end of sib2, iclass 11, count 2 2006.182.07:46:18.74#ibcon#*after write, iclass 11, count 2 2006.182.07:46:18.74#ibcon#*before return 0, iclass 11, count 2 2006.182.07:46:18.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:18.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:18.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.07:46:18.74#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:18.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:18.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:18.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:18.86#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:46:18.86#ibcon#first serial, iclass 11, count 0 2006.182.07:46:18.86#ibcon#enter sib2, iclass 11, count 0 2006.182.07:46:18.86#ibcon#flushed, iclass 11, count 0 2006.182.07:46:18.86#ibcon#about to write, iclass 11, count 0 2006.182.07:46:18.86#ibcon#wrote, iclass 11, count 0 2006.182.07:46:18.86#ibcon#about to read 3, iclass 11, count 0 2006.182.07:46:18.88#ibcon#read 3, iclass 11, count 0 2006.182.07:46:18.88#ibcon#about to read 4, iclass 11, count 0 2006.182.07:46:18.88#ibcon#read 4, iclass 11, count 0 2006.182.07:46:18.88#ibcon#about to read 5, iclass 11, count 0 2006.182.07:46:18.88#ibcon#read 5, iclass 11, count 0 2006.182.07:46:18.88#ibcon#about to read 6, iclass 11, count 0 2006.182.07:46:18.88#ibcon#read 6, iclass 11, count 0 2006.182.07:46:18.88#ibcon#end of sib2, iclass 11, count 0 2006.182.07:46:18.88#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:46:18.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:46:18.88#ibcon#[25=USB\r\n] 2006.182.07:46:18.88#ibcon#*before write, iclass 11, count 0 2006.182.07:46:18.88#ibcon#enter sib2, iclass 11, count 0 2006.182.07:46:18.88#ibcon#flushed, iclass 11, count 0 2006.182.07:46:18.88#ibcon#about to write, iclass 11, count 0 2006.182.07:46:18.88#ibcon#wrote, iclass 11, count 0 2006.182.07:46:18.88#ibcon#about to read 3, iclass 11, count 0 2006.182.07:46:18.91#ibcon#read 3, iclass 11, count 0 2006.182.07:46:18.91#ibcon#about to read 4, iclass 11, count 0 2006.182.07:46:18.91#ibcon#read 4, iclass 11, count 0 2006.182.07:46:18.91#ibcon#about to read 5, iclass 11, count 0 2006.182.07:46:18.91#ibcon#read 5, iclass 11, count 0 2006.182.07:46:18.91#ibcon#about to read 6, iclass 11, count 0 2006.182.07:46:18.91#ibcon#read 6, iclass 11, count 0 2006.182.07:46:18.91#ibcon#end of sib2, iclass 11, count 0 2006.182.07:46:18.91#ibcon#*after write, iclass 11, count 0 2006.182.07:46:18.91#ibcon#*before return 0, iclass 11, count 0 2006.182.07:46:18.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:18.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:18.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:46:18.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:46:18.91$vc4f8/valo=4,832.99 2006.182.07:46:18.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.07:46:18.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.07:46:18.91#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:18.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:18.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:18.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:18.91#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:46:18.91#ibcon#first serial, iclass 13, count 0 2006.182.07:46:18.91#ibcon#enter sib2, iclass 13, count 0 2006.182.07:46:18.91#ibcon#flushed, iclass 13, count 0 2006.182.07:46:18.91#ibcon#about to write, iclass 13, count 0 2006.182.07:46:18.91#ibcon#wrote, iclass 13, count 0 2006.182.07:46:18.91#ibcon#about to read 3, iclass 13, count 0 2006.182.07:46:18.93#ibcon#read 3, iclass 13, count 0 2006.182.07:46:18.93#ibcon#about to read 4, iclass 13, count 0 2006.182.07:46:18.93#ibcon#read 4, iclass 13, count 0 2006.182.07:46:18.93#ibcon#about to read 5, iclass 13, count 0 2006.182.07:46:18.93#ibcon#read 5, iclass 13, count 0 2006.182.07:46:18.93#ibcon#about to read 6, iclass 13, count 0 2006.182.07:46:18.93#ibcon#read 6, iclass 13, count 0 2006.182.07:46:18.93#ibcon#end of sib2, iclass 13, count 0 2006.182.07:46:18.93#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:46:18.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:46:18.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:46:18.93#ibcon#*before write, iclass 13, count 0 2006.182.07:46:18.93#ibcon#enter sib2, iclass 13, count 0 2006.182.07:46:18.93#ibcon#flushed, iclass 13, count 0 2006.182.07:46:18.93#ibcon#about to write, iclass 13, count 0 2006.182.07:46:18.93#ibcon#wrote, iclass 13, count 0 2006.182.07:46:18.93#ibcon#about to read 3, iclass 13, count 0 2006.182.07:46:18.97#ibcon#read 3, iclass 13, count 0 2006.182.07:46:18.97#ibcon#about to read 4, iclass 13, count 0 2006.182.07:46:18.97#ibcon#read 4, iclass 13, count 0 2006.182.07:46:18.97#ibcon#about to read 5, iclass 13, count 0 2006.182.07:46:18.97#ibcon#read 5, iclass 13, count 0 2006.182.07:46:18.97#ibcon#about to read 6, iclass 13, count 0 2006.182.07:46:18.97#ibcon#read 6, iclass 13, count 0 2006.182.07:46:18.97#ibcon#end of sib2, iclass 13, count 0 2006.182.07:46:18.97#ibcon#*after write, iclass 13, count 0 2006.182.07:46:18.97#ibcon#*before return 0, iclass 13, count 0 2006.182.07:46:18.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:18.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:18.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:46:18.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:46:18.97$vc4f8/va=4,7 2006.182.07:46:18.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.182.07:46:18.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.182.07:46:18.97#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:18.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:19.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:19.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:19.03#ibcon#enter wrdev, iclass 15, count 2 2006.182.07:46:19.03#ibcon#first serial, iclass 15, count 2 2006.182.07:46:19.03#ibcon#enter sib2, iclass 15, count 2 2006.182.07:46:19.03#ibcon#flushed, iclass 15, count 2 2006.182.07:46:19.03#ibcon#about to write, iclass 15, count 2 2006.182.07:46:19.03#ibcon#wrote, iclass 15, count 2 2006.182.07:46:19.03#ibcon#about to read 3, iclass 15, count 2 2006.182.07:46:19.05#ibcon#read 3, iclass 15, count 2 2006.182.07:46:19.05#ibcon#about to read 4, iclass 15, count 2 2006.182.07:46:19.05#ibcon#read 4, iclass 15, count 2 2006.182.07:46:19.05#ibcon#about to read 5, iclass 15, count 2 2006.182.07:46:19.05#ibcon#read 5, iclass 15, count 2 2006.182.07:46:19.05#ibcon#about to read 6, iclass 15, count 2 2006.182.07:46:19.05#ibcon#read 6, iclass 15, count 2 2006.182.07:46:19.05#ibcon#end of sib2, iclass 15, count 2 2006.182.07:46:19.05#ibcon#*mode == 0, iclass 15, count 2 2006.182.07:46:19.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.182.07:46:19.05#ibcon#[25=AT04-07\r\n] 2006.182.07:46:19.05#ibcon#*before write, iclass 15, count 2 2006.182.07:46:19.05#ibcon#enter sib2, iclass 15, count 2 2006.182.07:46:19.05#ibcon#flushed, iclass 15, count 2 2006.182.07:46:19.05#ibcon#about to write, iclass 15, count 2 2006.182.07:46:19.05#ibcon#wrote, iclass 15, count 2 2006.182.07:46:19.05#ibcon#about to read 3, iclass 15, count 2 2006.182.07:46:19.08#ibcon#read 3, iclass 15, count 2 2006.182.07:46:19.08#ibcon#about to read 4, iclass 15, count 2 2006.182.07:46:19.08#ibcon#read 4, iclass 15, count 2 2006.182.07:46:19.08#ibcon#about to read 5, iclass 15, count 2 2006.182.07:46:19.08#ibcon#read 5, iclass 15, count 2 2006.182.07:46:19.08#ibcon#about to read 6, iclass 15, count 2 2006.182.07:46:19.08#ibcon#read 6, iclass 15, count 2 2006.182.07:46:19.08#ibcon#end of sib2, iclass 15, count 2 2006.182.07:46:19.08#ibcon#*after write, iclass 15, count 2 2006.182.07:46:19.08#ibcon#*before return 0, iclass 15, count 2 2006.182.07:46:19.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:19.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:19.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.182.07:46:19.08#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:19.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:19.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:19.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:19.20#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:46:19.20#ibcon#first serial, iclass 15, count 0 2006.182.07:46:19.20#ibcon#enter sib2, iclass 15, count 0 2006.182.07:46:19.20#ibcon#flushed, iclass 15, count 0 2006.182.07:46:19.20#ibcon#about to write, iclass 15, count 0 2006.182.07:46:19.20#ibcon#wrote, iclass 15, count 0 2006.182.07:46:19.20#ibcon#about to read 3, iclass 15, count 0 2006.182.07:46:19.22#ibcon#read 3, iclass 15, count 0 2006.182.07:46:19.22#ibcon#about to read 4, iclass 15, count 0 2006.182.07:46:19.22#ibcon#read 4, iclass 15, count 0 2006.182.07:46:19.22#ibcon#about to read 5, iclass 15, count 0 2006.182.07:46:19.22#ibcon#read 5, iclass 15, count 0 2006.182.07:46:19.22#ibcon#about to read 6, iclass 15, count 0 2006.182.07:46:19.22#ibcon#read 6, iclass 15, count 0 2006.182.07:46:19.22#ibcon#end of sib2, iclass 15, count 0 2006.182.07:46:19.22#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:46:19.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:46:19.22#ibcon#[25=USB\r\n] 2006.182.07:46:19.22#ibcon#*before write, iclass 15, count 0 2006.182.07:46:19.22#ibcon#enter sib2, iclass 15, count 0 2006.182.07:46:19.22#ibcon#flushed, iclass 15, count 0 2006.182.07:46:19.22#ibcon#about to write, iclass 15, count 0 2006.182.07:46:19.22#ibcon#wrote, iclass 15, count 0 2006.182.07:46:19.22#ibcon#about to read 3, iclass 15, count 0 2006.182.07:46:19.25#ibcon#read 3, iclass 15, count 0 2006.182.07:46:19.25#ibcon#about to read 4, iclass 15, count 0 2006.182.07:46:19.25#ibcon#read 4, iclass 15, count 0 2006.182.07:46:19.25#ibcon#about to read 5, iclass 15, count 0 2006.182.07:46:19.25#ibcon#read 5, iclass 15, count 0 2006.182.07:46:19.25#ibcon#about to read 6, iclass 15, count 0 2006.182.07:46:19.25#ibcon#read 6, iclass 15, count 0 2006.182.07:46:19.25#ibcon#end of sib2, iclass 15, count 0 2006.182.07:46:19.25#ibcon#*after write, iclass 15, count 0 2006.182.07:46:19.25#ibcon#*before return 0, iclass 15, count 0 2006.182.07:46:19.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:19.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:19.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:46:19.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:46:19.25$vc4f8/valo=5,652.99 2006.182.07:46:19.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.07:46:19.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.07:46:19.25#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:19.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:19.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:19.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:19.25#ibcon#enter wrdev, iclass 17, count 0 2006.182.07:46:19.25#ibcon#first serial, iclass 17, count 0 2006.182.07:46:19.25#ibcon#enter sib2, iclass 17, count 0 2006.182.07:46:19.25#ibcon#flushed, iclass 17, count 0 2006.182.07:46:19.25#ibcon#about to write, iclass 17, count 0 2006.182.07:46:19.25#ibcon#wrote, iclass 17, count 0 2006.182.07:46:19.25#ibcon#about to read 3, iclass 17, count 0 2006.182.07:46:19.27#ibcon#read 3, iclass 17, count 0 2006.182.07:46:19.27#ibcon#about to read 4, iclass 17, count 0 2006.182.07:46:19.27#ibcon#read 4, iclass 17, count 0 2006.182.07:46:19.27#ibcon#about to read 5, iclass 17, count 0 2006.182.07:46:19.27#ibcon#read 5, iclass 17, count 0 2006.182.07:46:19.27#ibcon#about to read 6, iclass 17, count 0 2006.182.07:46:19.27#ibcon#read 6, iclass 17, count 0 2006.182.07:46:19.27#ibcon#end of sib2, iclass 17, count 0 2006.182.07:46:19.27#ibcon#*mode == 0, iclass 17, count 0 2006.182.07:46:19.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.07:46:19.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:46:19.27#ibcon#*before write, iclass 17, count 0 2006.182.07:46:19.27#ibcon#enter sib2, iclass 17, count 0 2006.182.07:46:19.27#ibcon#flushed, iclass 17, count 0 2006.182.07:46:19.27#ibcon#about to write, iclass 17, count 0 2006.182.07:46:19.27#ibcon#wrote, iclass 17, count 0 2006.182.07:46:19.27#ibcon#about to read 3, iclass 17, count 0 2006.182.07:46:19.31#ibcon#read 3, iclass 17, count 0 2006.182.07:46:19.31#ibcon#about to read 4, iclass 17, count 0 2006.182.07:46:19.31#ibcon#read 4, iclass 17, count 0 2006.182.07:46:19.31#ibcon#about to read 5, iclass 17, count 0 2006.182.07:46:19.31#ibcon#read 5, iclass 17, count 0 2006.182.07:46:19.31#ibcon#about to read 6, iclass 17, count 0 2006.182.07:46:19.31#ibcon#read 6, iclass 17, count 0 2006.182.07:46:19.31#ibcon#end of sib2, iclass 17, count 0 2006.182.07:46:19.31#ibcon#*after write, iclass 17, count 0 2006.182.07:46:19.31#ibcon#*before return 0, iclass 17, count 0 2006.182.07:46:19.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:19.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:19.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.07:46:19.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.07:46:19.31$vc4f8/va=5,7 2006.182.07:46:19.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.182.07:46:19.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.182.07:46:19.31#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:19.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:19.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:19.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:19.37#ibcon#enter wrdev, iclass 19, count 2 2006.182.07:46:19.37#ibcon#first serial, iclass 19, count 2 2006.182.07:46:19.37#ibcon#enter sib2, iclass 19, count 2 2006.182.07:46:19.37#ibcon#flushed, iclass 19, count 2 2006.182.07:46:19.37#ibcon#about to write, iclass 19, count 2 2006.182.07:46:19.37#ibcon#wrote, iclass 19, count 2 2006.182.07:46:19.37#ibcon#about to read 3, iclass 19, count 2 2006.182.07:46:19.39#ibcon#read 3, iclass 19, count 2 2006.182.07:46:19.39#ibcon#about to read 4, iclass 19, count 2 2006.182.07:46:19.39#ibcon#read 4, iclass 19, count 2 2006.182.07:46:19.39#ibcon#about to read 5, iclass 19, count 2 2006.182.07:46:19.39#ibcon#read 5, iclass 19, count 2 2006.182.07:46:19.39#ibcon#about to read 6, iclass 19, count 2 2006.182.07:46:19.39#ibcon#read 6, iclass 19, count 2 2006.182.07:46:19.39#ibcon#end of sib2, iclass 19, count 2 2006.182.07:46:19.39#ibcon#*mode == 0, iclass 19, count 2 2006.182.07:46:19.39#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.182.07:46:19.39#ibcon#[25=AT05-07\r\n] 2006.182.07:46:19.39#ibcon#*before write, iclass 19, count 2 2006.182.07:46:19.39#ibcon#enter sib2, iclass 19, count 2 2006.182.07:46:19.39#ibcon#flushed, iclass 19, count 2 2006.182.07:46:19.39#ibcon#about to write, iclass 19, count 2 2006.182.07:46:19.39#ibcon#wrote, iclass 19, count 2 2006.182.07:46:19.39#ibcon#about to read 3, iclass 19, count 2 2006.182.07:46:19.42#ibcon#read 3, iclass 19, count 2 2006.182.07:46:19.42#ibcon#about to read 4, iclass 19, count 2 2006.182.07:46:19.42#ibcon#read 4, iclass 19, count 2 2006.182.07:46:19.42#ibcon#about to read 5, iclass 19, count 2 2006.182.07:46:19.42#ibcon#read 5, iclass 19, count 2 2006.182.07:46:19.42#ibcon#about to read 6, iclass 19, count 2 2006.182.07:46:19.42#ibcon#read 6, iclass 19, count 2 2006.182.07:46:19.42#ibcon#end of sib2, iclass 19, count 2 2006.182.07:46:19.42#ibcon#*after write, iclass 19, count 2 2006.182.07:46:19.42#ibcon#*before return 0, iclass 19, count 2 2006.182.07:46:19.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:19.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:19.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.182.07:46:19.42#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:19.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:19.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:19.54#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:19.54#ibcon#enter wrdev, iclass 19, count 0 2006.182.07:46:19.54#ibcon#first serial, iclass 19, count 0 2006.182.07:46:19.54#ibcon#enter sib2, iclass 19, count 0 2006.182.07:46:19.54#ibcon#flushed, iclass 19, count 0 2006.182.07:46:19.54#ibcon#about to write, iclass 19, count 0 2006.182.07:46:19.54#ibcon#wrote, iclass 19, count 0 2006.182.07:46:19.54#ibcon#about to read 3, iclass 19, count 0 2006.182.07:46:19.56#ibcon#read 3, iclass 19, count 0 2006.182.07:46:19.56#ibcon#about to read 4, iclass 19, count 0 2006.182.07:46:19.56#ibcon#read 4, iclass 19, count 0 2006.182.07:46:19.56#ibcon#about to read 5, iclass 19, count 0 2006.182.07:46:19.56#ibcon#read 5, iclass 19, count 0 2006.182.07:46:19.56#ibcon#about to read 6, iclass 19, count 0 2006.182.07:46:19.56#ibcon#read 6, iclass 19, count 0 2006.182.07:46:19.56#ibcon#end of sib2, iclass 19, count 0 2006.182.07:46:19.56#ibcon#*mode == 0, iclass 19, count 0 2006.182.07:46:19.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.07:46:19.56#ibcon#[25=USB\r\n] 2006.182.07:46:19.56#ibcon#*before write, iclass 19, count 0 2006.182.07:46:19.56#ibcon#enter sib2, iclass 19, count 0 2006.182.07:46:19.56#ibcon#flushed, iclass 19, count 0 2006.182.07:46:19.56#ibcon#about to write, iclass 19, count 0 2006.182.07:46:19.56#ibcon#wrote, iclass 19, count 0 2006.182.07:46:19.56#ibcon#about to read 3, iclass 19, count 0 2006.182.07:46:19.59#ibcon#read 3, iclass 19, count 0 2006.182.07:46:19.59#ibcon#about to read 4, iclass 19, count 0 2006.182.07:46:19.59#ibcon#read 4, iclass 19, count 0 2006.182.07:46:19.59#ibcon#about to read 5, iclass 19, count 0 2006.182.07:46:19.59#ibcon#read 5, iclass 19, count 0 2006.182.07:46:19.59#ibcon#about to read 6, iclass 19, count 0 2006.182.07:46:19.59#ibcon#read 6, iclass 19, count 0 2006.182.07:46:19.59#ibcon#end of sib2, iclass 19, count 0 2006.182.07:46:19.59#ibcon#*after write, iclass 19, count 0 2006.182.07:46:19.59#ibcon#*before return 0, iclass 19, count 0 2006.182.07:46:19.59#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:19.59#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:19.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.07:46:19.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.07:46:19.59$vc4f8/valo=6,772.99 2006.182.07:46:19.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.07:46:19.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.07:46:19.59#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:19.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:19.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:19.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:19.59#ibcon#enter wrdev, iclass 21, count 0 2006.182.07:46:19.59#ibcon#first serial, iclass 21, count 0 2006.182.07:46:19.59#ibcon#enter sib2, iclass 21, count 0 2006.182.07:46:19.59#ibcon#flushed, iclass 21, count 0 2006.182.07:46:19.59#ibcon#about to write, iclass 21, count 0 2006.182.07:46:19.59#ibcon#wrote, iclass 21, count 0 2006.182.07:46:19.59#ibcon#about to read 3, iclass 21, count 0 2006.182.07:46:19.61#ibcon#read 3, iclass 21, count 0 2006.182.07:46:19.61#ibcon#about to read 4, iclass 21, count 0 2006.182.07:46:19.61#ibcon#read 4, iclass 21, count 0 2006.182.07:46:19.61#ibcon#about to read 5, iclass 21, count 0 2006.182.07:46:19.61#ibcon#read 5, iclass 21, count 0 2006.182.07:46:19.61#ibcon#about to read 6, iclass 21, count 0 2006.182.07:46:19.61#ibcon#read 6, iclass 21, count 0 2006.182.07:46:19.61#ibcon#end of sib2, iclass 21, count 0 2006.182.07:46:19.61#ibcon#*mode == 0, iclass 21, count 0 2006.182.07:46:19.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.07:46:19.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:46:19.61#ibcon#*before write, iclass 21, count 0 2006.182.07:46:19.61#ibcon#enter sib2, iclass 21, count 0 2006.182.07:46:19.61#ibcon#flushed, iclass 21, count 0 2006.182.07:46:19.61#ibcon#about to write, iclass 21, count 0 2006.182.07:46:19.61#ibcon#wrote, iclass 21, count 0 2006.182.07:46:19.61#ibcon#about to read 3, iclass 21, count 0 2006.182.07:46:19.66#ibcon#read 3, iclass 21, count 0 2006.182.07:46:19.66#ibcon#about to read 4, iclass 21, count 0 2006.182.07:46:19.66#ibcon#read 4, iclass 21, count 0 2006.182.07:46:19.66#ibcon#about to read 5, iclass 21, count 0 2006.182.07:46:19.66#ibcon#read 5, iclass 21, count 0 2006.182.07:46:19.66#ibcon#about to read 6, iclass 21, count 0 2006.182.07:46:19.66#ibcon#read 6, iclass 21, count 0 2006.182.07:46:19.66#ibcon#end of sib2, iclass 21, count 0 2006.182.07:46:19.66#ibcon#*after write, iclass 21, count 0 2006.182.07:46:19.66#ibcon#*before return 0, iclass 21, count 0 2006.182.07:46:19.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:19.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:19.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.07:46:19.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.07:46:19.66$vc4f8/va=6,6 2006.182.07:46:19.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.182.07:46:19.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.182.07:46:19.66#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:19.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:46:19.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:46:19.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:46:19.71#ibcon#enter wrdev, iclass 23, count 2 2006.182.07:46:19.71#ibcon#first serial, iclass 23, count 2 2006.182.07:46:19.71#ibcon#enter sib2, iclass 23, count 2 2006.182.07:46:19.71#ibcon#flushed, iclass 23, count 2 2006.182.07:46:19.71#ibcon#about to write, iclass 23, count 2 2006.182.07:46:19.71#ibcon#wrote, iclass 23, count 2 2006.182.07:46:19.71#ibcon#about to read 3, iclass 23, count 2 2006.182.07:46:19.73#ibcon#read 3, iclass 23, count 2 2006.182.07:46:19.73#ibcon#about to read 4, iclass 23, count 2 2006.182.07:46:19.73#ibcon#read 4, iclass 23, count 2 2006.182.07:46:19.73#ibcon#about to read 5, iclass 23, count 2 2006.182.07:46:19.73#ibcon#read 5, iclass 23, count 2 2006.182.07:46:19.73#ibcon#about to read 6, iclass 23, count 2 2006.182.07:46:19.73#ibcon#read 6, iclass 23, count 2 2006.182.07:46:19.73#ibcon#end of sib2, iclass 23, count 2 2006.182.07:46:19.73#ibcon#*mode == 0, iclass 23, count 2 2006.182.07:46:19.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.182.07:46:19.73#ibcon#[25=AT06-06\r\n] 2006.182.07:46:19.73#ibcon#*before write, iclass 23, count 2 2006.182.07:46:19.73#ibcon#enter sib2, iclass 23, count 2 2006.182.07:46:19.73#ibcon#flushed, iclass 23, count 2 2006.182.07:46:19.73#ibcon#about to write, iclass 23, count 2 2006.182.07:46:19.73#ibcon#wrote, iclass 23, count 2 2006.182.07:46:19.73#ibcon#about to read 3, iclass 23, count 2 2006.182.07:46:19.76#ibcon#read 3, iclass 23, count 2 2006.182.07:46:19.76#ibcon#about to read 4, iclass 23, count 2 2006.182.07:46:19.76#ibcon#read 4, iclass 23, count 2 2006.182.07:46:19.76#ibcon#about to read 5, iclass 23, count 2 2006.182.07:46:19.76#ibcon#read 5, iclass 23, count 2 2006.182.07:46:19.76#ibcon#about to read 6, iclass 23, count 2 2006.182.07:46:19.76#ibcon#read 6, iclass 23, count 2 2006.182.07:46:19.76#ibcon#end of sib2, iclass 23, count 2 2006.182.07:46:19.76#ibcon#*after write, iclass 23, count 2 2006.182.07:46:19.76#ibcon#*before return 0, iclass 23, count 2 2006.182.07:46:19.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:46:19.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:46:19.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.182.07:46:19.76#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:19.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:46:19.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:46:19.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:46:19.88#ibcon#enter wrdev, iclass 23, count 0 2006.182.07:46:19.88#ibcon#first serial, iclass 23, count 0 2006.182.07:46:19.88#ibcon#enter sib2, iclass 23, count 0 2006.182.07:46:19.88#ibcon#flushed, iclass 23, count 0 2006.182.07:46:19.88#ibcon#about to write, iclass 23, count 0 2006.182.07:46:19.88#ibcon#wrote, iclass 23, count 0 2006.182.07:46:19.88#ibcon#about to read 3, iclass 23, count 0 2006.182.07:46:19.90#ibcon#read 3, iclass 23, count 0 2006.182.07:46:19.90#ibcon#about to read 4, iclass 23, count 0 2006.182.07:46:19.90#ibcon#read 4, iclass 23, count 0 2006.182.07:46:19.90#ibcon#about to read 5, iclass 23, count 0 2006.182.07:46:19.90#ibcon#read 5, iclass 23, count 0 2006.182.07:46:19.90#ibcon#about to read 6, iclass 23, count 0 2006.182.07:46:19.90#ibcon#read 6, iclass 23, count 0 2006.182.07:46:19.90#ibcon#end of sib2, iclass 23, count 0 2006.182.07:46:19.90#ibcon#*mode == 0, iclass 23, count 0 2006.182.07:46:19.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.07:46:19.90#ibcon#[25=USB\r\n] 2006.182.07:46:19.90#ibcon#*before write, iclass 23, count 0 2006.182.07:46:19.90#ibcon#enter sib2, iclass 23, count 0 2006.182.07:46:19.90#ibcon#flushed, iclass 23, count 0 2006.182.07:46:19.90#ibcon#about to write, iclass 23, count 0 2006.182.07:46:19.90#ibcon#wrote, iclass 23, count 0 2006.182.07:46:19.90#ibcon#about to read 3, iclass 23, count 0 2006.182.07:46:19.93#ibcon#read 3, iclass 23, count 0 2006.182.07:46:19.93#ibcon#about to read 4, iclass 23, count 0 2006.182.07:46:19.93#ibcon#read 4, iclass 23, count 0 2006.182.07:46:19.93#ibcon#about to read 5, iclass 23, count 0 2006.182.07:46:19.93#ibcon#read 5, iclass 23, count 0 2006.182.07:46:19.93#ibcon#about to read 6, iclass 23, count 0 2006.182.07:46:19.93#ibcon#read 6, iclass 23, count 0 2006.182.07:46:19.93#ibcon#end of sib2, iclass 23, count 0 2006.182.07:46:19.93#ibcon#*after write, iclass 23, count 0 2006.182.07:46:19.93#ibcon#*before return 0, iclass 23, count 0 2006.182.07:46:19.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:46:19.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:46:19.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.07:46:19.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.07:46:19.93$vc4f8/valo=7,832.99 2006.182.07:46:19.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.07:46:19.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.07:46:19.93#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:19.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:46:19.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:46:19.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:46:19.93#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:46:19.93#ibcon#first serial, iclass 25, count 0 2006.182.07:46:19.93#ibcon#enter sib2, iclass 25, count 0 2006.182.07:46:19.93#ibcon#flushed, iclass 25, count 0 2006.182.07:46:19.93#ibcon#about to write, iclass 25, count 0 2006.182.07:46:19.93#ibcon#wrote, iclass 25, count 0 2006.182.07:46:19.93#ibcon#about to read 3, iclass 25, count 0 2006.182.07:46:19.95#ibcon#read 3, iclass 25, count 0 2006.182.07:46:19.95#ibcon#about to read 4, iclass 25, count 0 2006.182.07:46:19.95#ibcon#read 4, iclass 25, count 0 2006.182.07:46:19.95#ibcon#about to read 5, iclass 25, count 0 2006.182.07:46:19.95#ibcon#read 5, iclass 25, count 0 2006.182.07:46:19.95#ibcon#about to read 6, iclass 25, count 0 2006.182.07:46:19.95#ibcon#read 6, iclass 25, count 0 2006.182.07:46:19.95#ibcon#end of sib2, iclass 25, count 0 2006.182.07:46:19.95#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:46:19.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:46:19.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:46:19.95#ibcon#*before write, iclass 25, count 0 2006.182.07:46:19.95#ibcon#enter sib2, iclass 25, count 0 2006.182.07:46:19.95#ibcon#flushed, iclass 25, count 0 2006.182.07:46:19.95#ibcon#about to write, iclass 25, count 0 2006.182.07:46:19.95#ibcon#wrote, iclass 25, count 0 2006.182.07:46:19.95#ibcon#about to read 3, iclass 25, count 0 2006.182.07:46:19.99#ibcon#read 3, iclass 25, count 0 2006.182.07:46:19.99#ibcon#about to read 4, iclass 25, count 0 2006.182.07:46:19.99#ibcon#read 4, iclass 25, count 0 2006.182.07:46:19.99#ibcon#about to read 5, iclass 25, count 0 2006.182.07:46:19.99#ibcon#read 5, iclass 25, count 0 2006.182.07:46:19.99#ibcon#about to read 6, iclass 25, count 0 2006.182.07:46:19.99#ibcon#read 6, iclass 25, count 0 2006.182.07:46:19.99#ibcon#end of sib2, iclass 25, count 0 2006.182.07:46:19.99#ibcon#*after write, iclass 25, count 0 2006.182.07:46:19.99#ibcon#*before return 0, iclass 25, count 0 2006.182.07:46:19.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:46:19.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:46:19.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:46:19.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:46:19.99$vc4f8/va=7,6 2006.182.07:46:19.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.182.07:46:19.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.182.07:46:19.99#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:19.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:46:20.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:46:20.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:46:20.05#ibcon#enter wrdev, iclass 27, count 2 2006.182.07:46:20.05#ibcon#first serial, iclass 27, count 2 2006.182.07:46:20.05#ibcon#enter sib2, iclass 27, count 2 2006.182.07:46:20.05#ibcon#flushed, iclass 27, count 2 2006.182.07:46:20.05#ibcon#about to write, iclass 27, count 2 2006.182.07:46:20.05#ibcon#wrote, iclass 27, count 2 2006.182.07:46:20.05#ibcon#about to read 3, iclass 27, count 2 2006.182.07:46:20.07#ibcon#read 3, iclass 27, count 2 2006.182.07:46:20.07#ibcon#about to read 4, iclass 27, count 2 2006.182.07:46:20.07#ibcon#read 4, iclass 27, count 2 2006.182.07:46:20.07#ibcon#about to read 5, iclass 27, count 2 2006.182.07:46:20.07#ibcon#read 5, iclass 27, count 2 2006.182.07:46:20.07#ibcon#about to read 6, iclass 27, count 2 2006.182.07:46:20.07#ibcon#read 6, iclass 27, count 2 2006.182.07:46:20.07#ibcon#end of sib2, iclass 27, count 2 2006.182.07:46:20.07#ibcon#*mode == 0, iclass 27, count 2 2006.182.07:46:20.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.182.07:46:20.07#ibcon#[25=AT07-06\r\n] 2006.182.07:46:20.07#ibcon#*before write, iclass 27, count 2 2006.182.07:46:20.07#ibcon#enter sib2, iclass 27, count 2 2006.182.07:46:20.07#ibcon#flushed, iclass 27, count 2 2006.182.07:46:20.07#ibcon#about to write, iclass 27, count 2 2006.182.07:46:20.07#ibcon#wrote, iclass 27, count 2 2006.182.07:46:20.07#ibcon#about to read 3, iclass 27, count 2 2006.182.07:46:20.10#ibcon#read 3, iclass 27, count 2 2006.182.07:46:20.10#ibcon#about to read 4, iclass 27, count 2 2006.182.07:46:20.10#ibcon#read 4, iclass 27, count 2 2006.182.07:46:20.10#ibcon#about to read 5, iclass 27, count 2 2006.182.07:46:20.10#ibcon#read 5, iclass 27, count 2 2006.182.07:46:20.10#ibcon#about to read 6, iclass 27, count 2 2006.182.07:46:20.10#ibcon#read 6, iclass 27, count 2 2006.182.07:46:20.10#ibcon#end of sib2, iclass 27, count 2 2006.182.07:46:20.10#ibcon#*after write, iclass 27, count 2 2006.182.07:46:20.10#ibcon#*before return 0, iclass 27, count 2 2006.182.07:46:20.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:46:20.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:46:20.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.182.07:46:20.10#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:20.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:46:20.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:46:20.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:46:20.22#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:46:20.22#ibcon#first serial, iclass 27, count 0 2006.182.07:46:20.22#ibcon#enter sib2, iclass 27, count 0 2006.182.07:46:20.22#ibcon#flushed, iclass 27, count 0 2006.182.07:46:20.22#ibcon#about to write, iclass 27, count 0 2006.182.07:46:20.22#ibcon#wrote, iclass 27, count 0 2006.182.07:46:20.22#ibcon#about to read 3, iclass 27, count 0 2006.182.07:46:20.24#ibcon#read 3, iclass 27, count 0 2006.182.07:46:20.24#ibcon#about to read 4, iclass 27, count 0 2006.182.07:46:20.24#ibcon#read 4, iclass 27, count 0 2006.182.07:46:20.24#ibcon#about to read 5, iclass 27, count 0 2006.182.07:46:20.24#ibcon#read 5, iclass 27, count 0 2006.182.07:46:20.24#ibcon#about to read 6, iclass 27, count 0 2006.182.07:46:20.24#ibcon#read 6, iclass 27, count 0 2006.182.07:46:20.24#ibcon#end of sib2, iclass 27, count 0 2006.182.07:46:20.24#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:46:20.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:46:20.24#ibcon#[25=USB\r\n] 2006.182.07:46:20.24#ibcon#*before write, iclass 27, count 0 2006.182.07:46:20.24#ibcon#enter sib2, iclass 27, count 0 2006.182.07:46:20.24#ibcon#flushed, iclass 27, count 0 2006.182.07:46:20.24#ibcon#about to write, iclass 27, count 0 2006.182.07:46:20.24#ibcon#wrote, iclass 27, count 0 2006.182.07:46:20.24#ibcon#about to read 3, iclass 27, count 0 2006.182.07:46:20.27#ibcon#read 3, iclass 27, count 0 2006.182.07:46:20.27#ibcon#about to read 4, iclass 27, count 0 2006.182.07:46:20.27#ibcon#read 4, iclass 27, count 0 2006.182.07:46:20.27#ibcon#about to read 5, iclass 27, count 0 2006.182.07:46:20.27#ibcon#read 5, iclass 27, count 0 2006.182.07:46:20.27#ibcon#about to read 6, iclass 27, count 0 2006.182.07:46:20.27#ibcon#read 6, iclass 27, count 0 2006.182.07:46:20.27#ibcon#end of sib2, iclass 27, count 0 2006.182.07:46:20.27#ibcon#*after write, iclass 27, count 0 2006.182.07:46:20.27#ibcon#*before return 0, iclass 27, count 0 2006.182.07:46:20.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:46:20.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:46:20.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:46:20.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:46:20.27$vc4f8/valo=8,852.99 2006.182.07:46:20.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.07:46:20.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.07:46:20.27#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:20.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:46:20.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:46:20.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:46:20.27#ibcon#enter wrdev, iclass 29, count 0 2006.182.07:46:20.27#ibcon#first serial, iclass 29, count 0 2006.182.07:46:20.27#ibcon#enter sib2, iclass 29, count 0 2006.182.07:46:20.27#ibcon#flushed, iclass 29, count 0 2006.182.07:46:20.27#ibcon#about to write, iclass 29, count 0 2006.182.07:46:20.27#ibcon#wrote, iclass 29, count 0 2006.182.07:46:20.27#ibcon#about to read 3, iclass 29, count 0 2006.182.07:46:20.29#ibcon#read 3, iclass 29, count 0 2006.182.07:46:20.29#ibcon#about to read 4, iclass 29, count 0 2006.182.07:46:20.29#ibcon#read 4, iclass 29, count 0 2006.182.07:46:20.29#ibcon#about to read 5, iclass 29, count 0 2006.182.07:46:20.29#ibcon#read 5, iclass 29, count 0 2006.182.07:46:20.29#ibcon#about to read 6, iclass 29, count 0 2006.182.07:46:20.29#ibcon#read 6, iclass 29, count 0 2006.182.07:46:20.29#ibcon#end of sib2, iclass 29, count 0 2006.182.07:46:20.29#ibcon#*mode == 0, iclass 29, count 0 2006.182.07:46:20.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.07:46:20.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:46:20.29#ibcon#*before write, iclass 29, count 0 2006.182.07:46:20.29#ibcon#enter sib2, iclass 29, count 0 2006.182.07:46:20.29#ibcon#flushed, iclass 29, count 0 2006.182.07:46:20.29#ibcon#about to write, iclass 29, count 0 2006.182.07:46:20.29#ibcon#wrote, iclass 29, count 0 2006.182.07:46:20.29#ibcon#about to read 3, iclass 29, count 0 2006.182.07:46:20.33#ibcon#read 3, iclass 29, count 0 2006.182.07:46:20.33#ibcon#about to read 4, iclass 29, count 0 2006.182.07:46:20.33#ibcon#read 4, iclass 29, count 0 2006.182.07:46:20.33#ibcon#about to read 5, iclass 29, count 0 2006.182.07:46:20.33#ibcon#read 5, iclass 29, count 0 2006.182.07:46:20.33#ibcon#about to read 6, iclass 29, count 0 2006.182.07:46:20.33#ibcon#read 6, iclass 29, count 0 2006.182.07:46:20.33#ibcon#end of sib2, iclass 29, count 0 2006.182.07:46:20.33#ibcon#*after write, iclass 29, count 0 2006.182.07:46:20.33#ibcon#*before return 0, iclass 29, count 0 2006.182.07:46:20.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:46:20.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:46:20.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.07:46:20.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.07:46:20.33$vc4f8/va=8,7 2006.182.07:46:20.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.182.07:46:20.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.182.07:46:20.33#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:20.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:46:20.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:46:20.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:46:20.39#ibcon#enter wrdev, iclass 31, count 2 2006.182.07:46:20.39#ibcon#first serial, iclass 31, count 2 2006.182.07:46:20.39#ibcon#enter sib2, iclass 31, count 2 2006.182.07:46:20.39#ibcon#flushed, iclass 31, count 2 2006.182.07:46:20.39#ibcon#about to write, iclass 31, count 2 2006.182.07:46:20.39#ibcon#wrote, iclass 31, count 2 2006.182.07:46:20.39#ibcon#about to read 3, iclass 31, count 2 2006.182.07:46:20.41#ibcon#read 3, iclass 31, count 2 2006.182.07:46:20.41#ibcon#about to read 4, iclass 31, count 2 2006.182.07:46:20.41#ibcon#read 4, iclass 31, count 2 2006.182.07:46:20.41#ibcon#about to read 5, iclass 31, count 2 2006.182.07:46:20.41#ibcon#read 5, iclass 31, count 2 2006.182.07:46:20.41#ibcon#about to read 6, iclass 31, count 2 2006.182.07:46:20.41#ibcon#read 6, iclass 31, count 2 2006.182.07:46:20.41#ibcon#end of sib2, iclass 31, count 2 2006.182.07:46:20.41#ibcon#*mode == 0, iclass 31, count 2 2006.182.07:46:20.41#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.182.07:46:20.41#ibcon#[25=AT08-07\r\n] 2006.182.07:46:20.41#ibcon#*before write, iclass 31, count 2 2006.182.07:46:20.41#ibcon#enter sib2, iclass 31, count 2 2006.182.07:46:20.41#ibcon#flushed, iclass 31, count 2 2006.182.07:46:20.41#ibcon#about to write, iclass 31, count 2 2006.182.07:46:20.41#ibcon#wrote, iclass 31, count 2 2006.182.07:46:20.41#ibcon#about to read 3, iclass 31, count 2 2006.182.07:46:20.44#ibcon#read 3, iclass 31, count 2 2006.182.07:46:20.44#ibcon#about to read 4, iclass 31, count 2 2006.182.07:46:20.44#ibcon#read 4, iclass 31, count 2 2006.182.07:46:20.44#ibcon#about to read 5, iclass 31, count 2 2006.182.07:46:20.44#ibcon#read 5, iclass 31, count 2 2006.182.07:46:20.44#ibcon#about to read 6, iclass 31, count 2 2006.182.07:46:20.44#ibcon#read 6, iclass 31, count 2 2006.182.07:46:20.44#ibcon#end of sib2, iclass 31, count 2 2006.182.07:46:20.44#ibcon#*after write, iclass 31, count 2 2006.182.07:46:20.44#ibcon#*before return 0, iclass 31, count 2 2006.182.07:46:20.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:46:20.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:46:20.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.182.07:46:20.44#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:20.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:46:20.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:46:20.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:46:20.56#ibcon#enter wrdev, iclass 31, count 0 2006.182.07:46:20.56#ibcon#first serial, iclass 31, count 0 2006.182.07:46:20.56#ibcon#enter sib2, iclass 31, count 0 2006.182.07:46:20.56#ibcon#flushed, iclass 31, count 0 2006.182.07:46:20.56#ibcon#about to write, iclass 31, count 0 2006.182.07:46:20.56#ibcon#wrote, iclass 31, count 0 2006.182.07:46:20.56#ibcon#about to read 3, iclass 31, count 0 2006.182.07:46:20.58#ibcon#read 3, iclass 31, count 0 2006.182.07:46:20.58#ibcon#about to read 4, iclass 31, count 0 2006.182.07:46:20.58#ibcon#read 4, iclass 31, count 0 2006.182.07:46:20.58#ibcon#about to read 5, iclass 31, count 0 2006.182.07:46:20.58#ibcon#read 5, iclass 31, count 0 2006.182.07:46:20.58#ibcon#about to read 6, iclass 31, count 0 2006.182.07:46:20.58#ibcon#read 6, iclass 31, count 0 2006.182.07:46:20.58#ibcon#end of sib2, iclass 31, count 0 2006.182.07:46:20.58#ibcon#*mode == 0, iclass 31, count 0 2006.182.07:46:20.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.07:46:20.58#ibcon#[25=USB\r\n] 2006.182.07:46:20.58#ibcon#*before write, iclass 31, count 0 2006.182.07:46:20.58#ibcon#enter sib2, iclass 31, count 0 2006.182.07:46:20.58#ibcon#flushed, iclass 31, count 0 2006.182.07:46:20.58#ibcon#about to write, iclass 31, count 0 2006.182.07:46:20.58#ibcon#wrote, iclass 31, count 0 2006.182.07:46:20.58#ibcon#about to read 3, iclass 31, count 0 2006.182.07:46:20.61#ibcon#read 3, iclass 31, count 0 2006.182.07:46:20.61#ibcon#about to read 4, iclass 31, count 0 2006.182.07:46:20.61#ibcon#read 4, iclass 31, count 0 2006.182.07:46:20.61#ibcon#about to read 5, iclass 31, count 0 2006.182.07:46:20.61#ibcon#read 5, iclass 31, count 0 2006.182.07:46:20.61#ibcon#about to read 6, iclass 31, count 0 2006.182.07:46:20.61#ibcon#read 6, iclass 31, count 0 2006.182.07:46:20.61#ibcon#end of sib2, iclass 31, count 0 2006.182.07:46:20.61#ibcon#*after write, iclass 31, count 0 2006.182.07:46:20.61#ibcon#*before return 0, iclass 31, count 0 2006.182.07:46:20.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:46:20.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:46:20.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.07:46:20.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.07:46:20.61$vc4f8/vblo=1,632.99 2006.182.07:46:20.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.182.07:46:20.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.182.07:46:20.61#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:20.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:20.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:20.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:20.61#ibcon#enter wrdev, iclass 33, count 0 2006.182.07:46:20.61#ibcon#first serial, iclass 33, count 0 2006.182.07:46:20.61#ibcon#enter sib2, iclass 33, count 0 2006.182.07:46:20.61#ibcon#flushed, iclass 33, count 0 2006.182.07:46:20.61#ibcon#about to write, iclass 33, count 0 2006.182.07:46:20.61#ibcon#wrote, iclass 33, count 0 2006.182.07:46:20.61#ibcon#about to read 3, iclass 33, count 0 2006.182.07:46:20.63#ibcon#read 3, iclass 33, count 0 2006.182.07:46:20.63#ibcon#about to read 4, iclass 33, count 0 2006.182.07:46:20.63#ibcon#read 4, iclass 33, count 0 2006.182.07:46:20.63#ibcon#about to read 5, iclass 33, count 0 2006.182.07:46:20.63#ibcon#read 5, iclass 33, count 0 2006.182.07:46:20.63#ibcon#about to read 6, iclass 33, count 0 2006.182.07:46:20.63#ibcon#read 6, iclass 33, count 0 2006.182.07:46:20.63#ibcon#end of sib2, iclass 33, count 0 2006.182.07:46:20.63#ibcon#*mode == 0, iclass 33, count 0 2006.182.07:46:20.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.07:46:20.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:46:20.63#ibcon#*before write, iclass 33, count 0 2006.182.07:46:20.63#ibcon#enter sib2, iclass 33, count 0 2006.182.07:46:20.63#ibcon#flushed, iclass 33, count 0 2006.182.07:46:20.63#ibcon#about to write, iclass 33, count 0 2006.182.07:46:20.63#ibcon#wrote, iclass 33, count 0 2006.182.07:46:20.63#ibcon#about to read 3, iclass 33, count 0 2006.182.07:46:20.68#ibcon#read 3, iclass 33, count 0 2006.182.07:46:20.68#ibcon#about to read 4, iclass 33, count 0 2006.182.07:46:20.68#ibcon#read 4, iclass 33, count 0 2006.182.07:46:20.68#ibcon#about to read 5, iclass 33, count 0 2006.182.07:46:20.68#ibcon#read 5, iclass 33, count 0 2006.182.07:46:20.68#ibcon#about to read 6, iclass 33, count 0 2006.182.07:46:20.68#ibcon#read 6, iclass 33, count 0 2006.182.07:46:20.68#ibcon#end of sib2, iclass 33, count 0 2006.182.07:46:20.68#ibcon#*after write, iclass 33, count 0 2006.182.07:46:20.68#ibcon#*before return 0, iclass 33, count 0 2006.182.07:46:20.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:20.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:46:20.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.07:46:20.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.07:46:20.68$vc4f8/vb=1,4 2006.182.07:46:20.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.182.07:46:20.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.182.07:46:20.68#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:20.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:20.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:20.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:20.68#ibcon#enter wrdev, iclass 35, count 2 2006.182.07:46:20.68#ibcon#first serial, iclass 35, count 2 2006.182.07:46:20.68#ibcon#enter sib2, iclass 35, count 2 2006.182.07:46:20.68#ibcon#flushed, iclass 35, count 2 2006.182.07:46:20.68#ibcon#about to write, iclass 35, count 2 2006.182.07:46:20.68#ibcon#wrote, iclass 35, count 2 2006.182.07:46:20.68#ibcon#about to read 3, iclass 35, count 2 2006.182.07:46:20.70#ibcon#read 3, iclass 35, count 2 2006.182.07:46:20.70#ibcon#about to read 4, iclass 35, count 2 2006.182.07:46:20.70#ibcon#read 4, iclass 35, count 2 2006.182.07:46:20.70#ibcon#about to read 5, iclass 35, count 2 2006.182.07:46:20.70#ibcon#read 5, iclass 35, count 2 2006.182.07:46:20.70#ibcon#about to read 6, iclass 35, count 2 2006.182.07:46:20.70#ibcon#read 6, iclass 35, count 2 2006.182.07:46:20.70#ibcon#end of sib2, iclass 35, count 2 2006.182.07:46:20.70#ibcon#*mode == 0, iclass 35, count 2 2006.182.07:46:20.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.182.07:46:20.70#ibcon#[27=AT01-04\r\n] 2006.182.07:46:20.70#ibcon#*before write, iclass 35, count 2 2006.182.07:46:20.70#ibcon#enter sib2, iclass 35, count 2 2006.182.07:46:20.70#ibcon#flushed, iclass 35, count 2 2006.182.07:46:20.70#ibcon#about to write, iclass 35, count 2 2006.182.07:46:20.70#ibcon#wrote, iclass 35, count 2 2006.182.07:46:20.70#ibcon#about to read 3, iclass 35, count 2 2006.182.07:46:20.73#ibcon#read 3, iclass 35, count 2 2006.182.07:46:20.73#ibcon#about to read 4, iclass 35, count 2 2006.182.07:46:20.73#ibcon#read 4, iclass 35, count 2 2006.182.07:46:20.73#ibcon#about to read 5, iclass 35, count 2 2006.182.07:46:20.73#ibcon#read 5, iclass 35, count 2 2006.182.07:46:20.73#ibcon#about to read 6, iclass 35, count 2 2006.182.07:46:20.73#ibcon#read 6, iclass 35, count 2 2006.182.07:46:20.73#ibcon#end of sib2, iclass 35, count 2 2006.182.07:46:20.73#ibcon#*after write, iclass 35, count 2 2006.182.07:46:20.73#ibcon#*before return 0, iclass 35, count 2 2006.182.07:46:20.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:20.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:46:20.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.182.07:46:20.73#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:20.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:20.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:20.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:20.85#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:46:20.85#ibcon#first serial, iclass 35, count 0 2006.182.07:46:20.85#ibcon#enter sib2, iclass 35, count 0 2006.182.07:46:20.85#ibcon#flushed, iclass 35, count 0 2006.182.07:46:20.85#ibcon#about to write, iclass 35, count 0 2006.182.07:46:20.85#ibcon#wrote, iclass 35, count 0 2006.182.07:46:20.85#ibcon#about to read 3, iclass 35, count 0 2006.182.07:46:20.87#ibcon#read 3, iclass 35, count 0 2006.182.07:46:20.87#ibcon#about to read 4, iclass 35, count 0 2006.182.07:46:20.87#ibcon#read 4, iclass 35, count 0 2006.182.07:46:20.87#ibcon#about to read 5, iclass 35, count 0 2006.182.07:46:20.87#ibcon#read 5, iclass 35, count 0 2006.182.07:46:20.87#ibcon#about to read 6, iclass 35, count 0 2006.182.07:46:20.87#ibcon#read 6, iclass 35, count 0 2006.182.07:46:20.87#ibcon#end of sib2, iclass 35, count 0 2006.182.07:46:20.87#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:46:20.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:46:20.87#ibcon#[27=USB\r\n] 2006.182.07:46:20.87#ibcon#*before write, iclass 35, count 0 2006.182.07:46:20.87#ibcon#enter sib2, iclass 35, count 0 2006.182.07:46:20.87#ibcon#flushed, iclass 35, count 0 2006.182.07:46:20.87#ibcon#about to write, iclass 35, count 0 2006.182.07:46:20.87#ibcon#wrote, iclass 35, count 0 2006.182.07:46:20.87#ibcon#about to read 3, iclass 35, count 0 2006.182.07:46:20.90#ibcon#read 3, iclass 35, count 0 2006.182.07:46:20.90#ibcon#about to read 4, iclass 35, count 0 2006.182.07:46:20.90#ibcon#read 4, iclass 35, count 0 2006.182.07:46:20.90#ibcon#about to read 5, iclass 35, count 0 2006.182.07:46:20.90#ibcon#read 5, iclass 35, count 0 2006.182.07:46:20.90#ibcon#about to read 6, iclass 35, count 0 2006.182.07:46:20.90#ibcon#read 6, iclass 35, count 0 2006.182.07:46:20.90#ibcon#end of sib2, iclass 35, count 0 2006.182.07:46:20.90#ibcon#*after write, iclass 35, count 0 2006.182.07:46:20.90#ibcon#*before return 0, iclass 35, count 0 2006.182.07:46:20.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:20.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:46:20.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:46:20.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:46:20.90$vc4f8/vblo=2,640.99 2006.182.07:46:20.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.182.07:46:20.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.182.07:46:20.90#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:20.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:46:20.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:46:20.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:46:20.90#ibcon#enter wrdev, iclass 37, count 0 2006.182.07:46:20.90#ibcon#first serial, iclass 37, count 0 2006.182.07:46:20.90#ibcon#enter sib2, iclass 37, count 0 2006.182.07:46:20.90#ibcon#flushed, iclass 37, count 0 2006.182.07:46:20.90#ibcon#about to write, iclass 37, count 0 2006.182.07:46:20.90#ibcon#wrote, iclass 37, count 0 2006.182.07:46:20.90#ibcon#about to read 3, iclass 37, count 0 2006.182.07:46:20.92#ibcon#read 3, iclass 37, count 0 2006.182.07:46:20.92#ibcon#about to read 4, iclass 37, count 0 2006.182.07:46:20.92#ibcon#read 4, iclass 37, count 0 2006.182.07:46:20.92#ibcon#about to read 5, iclass 37, count 0 2006.182.07:46:20.92#ibcon#read 5, iclass 37, count 0 2006.182.07:46:20.92#ibcon#about to read 6, iclass 37, count 0 2006.182.07:46:20.92#ibcon#read 6, iclass 37, count 0 2006.182.07:46:20.92#ibcon#end of sib2, iclass 37, count 0 2006.182.07:46:20.92#ibcon#*mode == 0, iclass 37, count 0 2006.182.07:46:20.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.07:46:20.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:46:20.92#ibcon#*before write, iclass 37, count 0 2006.182.07:46:20.92#ibcon#enter sib2, iclass 37, count 0 2006.182.07:46:20.92#ibcon#flushed, iclass 37, count 0 2006.182.07:46:20.92#ibcon#about to write, iclass 37, count 0 2006.182.07:46:20.92#ibcon#wrote, iclass 37, count 0 2006.182.07:46:20.92#ibcon#about to read 3, iclass 37, count 0 2006.182.07:46:20.96#ibcon#read 3, iclass 37, count 0 2006.182.07:46:20.96#ibcon#about to read 4, iclass 37, count 0 2006.182.07:46:20.96#ibcon#read 4, iclass 37, count 0 2006.182.07:46:20.96#ibcon#about to read 5, iclass 37, count 0 2006.182.07:46:20.96#ibcon#read 5, iclass 37, count 0 2006.182.07:46:20.96#ibcon#about to read 6, iclass 37, count 0 2006.182.07:46:20.96#ibcon#read 6, iclass 37, count 0 2006.182.07:46:20.96#ibcon#end of sib2, iclass 37, count 0 2006.182.07:46:20.96#ibcon#*after write, iclass 37, count 0 2006.182.07:46:20.96#ibcon#*before return 0, iclass 37, count 0 2006.182.07:46:20.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:46:20.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:46:20.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.07:46:20.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.07:46:20.96$vc4f8/vb=2,4 2006.182.07:46:20.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.07:46:20.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.07:46:20.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:20.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:46:21.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:46:21.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:46:21.02#ibcon#enter wrdev, iclass 39, count 2 2006.182.07:46:21.02#ibcon#first serial, iclass 39, count 2 2006.182.07:46:21.02#ibcon#enter sib2, iclass 39, count 2 2006.182.07:46:21.02#ibcon#flushed, iclass 39, count 2 2006.182.07:46:21.02#ibcon#about to write, iclass 39, count 2 2006.182.07:46:21.02#ibcon#wrote, iclass 39, count 2 2006.182.07:46:21.02#ibcon#about to read 3, iclass 39, count 2 2006.182.07:46:21.04#ibcon#read 3, iclass 39, count 2 2006.182.07:46:21.04#ibcon#about to read 4, iclass 39, count 2 2006.182.07:46:21.04#ibcon#read 4, iclass 39, count 2 2006.182.07:46:21.04#ibcon#about to read 5, iclass 39, count 2 2006.182.07:46:21.04#ibcon#read 5, iclass 39, count 2 2006.182.07:46:21.04#ibcon#about to read 6, iclass 39, count 2 2006.182.07:46:21.04#ibcon#read 6, iclass 39, count 2 2006.182.07:46:21.04#ibcon#end of sib2, iclass 39, count 2 2006.182.07:46:21.04#ibcon#*mode == 0, iclass 39, count 2 2006.182.07:46:21.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.07:46:21.04#ibcon#[27=AT02-04\r\n] 2006.182.07:46:21.04#ibcon#*before write, iclass 39, count 2 2006.182.07:46:21.04#ibcon#enter sib2, iclass 39, count 2 2006.182.07:46:21.04#ibcon#flushed, iclass 39, count 2 2006.182.07:46:21.04#ibcon#about to write, iclass 39, count 2 2006.182.07:46:21.04#ibcon#wrote, iclass 39, count 2 2006.182.07:46:21.04#ibcon#about to read 3, iclass 39, count 2 2006.182.07:46:21.07#ibcon#read 3, iclass 39, count 2 2006.182.07:46:21.07#ibcon#about to read 4, iclass 39, count 2 2006.182.07:46:21.07#ibcon#read 4, iclass 39, count 2 2006.182.07:46:21.07#ibcon#about to read 5, iclass 39, count 2 2006.182.07:46:21.07#ibcon#read 5, iclass 39, count 2 2006.182.07:46:21.07#ibcon#about to read 6, iclass 39, count 2 2006.182.07:46:21.07#ibcon#read 6, iclass 39, count 2 2006.182.07:46:21.07#ibcon#end of sib2, iclass 39, count 2 2006.182.07:46:21.07#ibcon#*after write, iclass 39, count 2 2006.182.07:46:21.07#ibcon#*before return 0, iclass 39, count 2 2006.182.07:46:21.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:46:21.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:46:21.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.07:46:21.07#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:21.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:46:21.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:46:21.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:46:21.19#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:46:21.19#ibcon#first serial, iclass 39, count 0 2006.182.07:46:21.19#ibcon#enter sib2, iclass 39, count 0 2006.182.07:46:21.19#ibcon#flushed, iclass 39, count 0 2006.182.07:46:21.19#ibcon#about to write, iclass 39, count 0 2006.182.07:46:21.19#ibcon#wrote, iclass 39, count 0 2006.182.07:46:21.19#ibcon#about to read 3, iclass 39, count 0 2006.182.07:46:21.21#ibcon#read 3, iclass 39, count 0 2006.182.07:46:21.21#ibcon#about to read 4, iclass 39, count 0 2006.182.07:46:21.21#ibcon#read 4, iclass 39, count 0 2006.182.07:46:21.21#ibcon#about to read 5, iclass 39, count 0 2006.182.07:46:21.21#ibcon#read 5, iclass 39, count 0 2006.182.07:46:21.21#ibcon#about to read 6, iclass 39, count 0 2006.182.07:46:21.21#ibcon#read 6, iclass 39, count 0 2006.182.07:46:21.21#ibcon#end of sib2, iclass 39, count 0 2006.182.07:46:21.21#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:46:21.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:46:21.21#ibcon#[27=USB\r\n] 2006.182.07:46:21.21#ibcon#*before write, iclass 39, count 0 2006.182.07:46:21.21#ibcon#enter sib2, iclass 39, count 0 2006.182.07:46:21.21#ibcon#flushed, iclass 39, count 0 2006.182.07:46:21.21#ibcon#about to write, iclass 39, count 0 2006.182.07:46:21.21#ibcon#wrote, iclass 39, count 0 2006.182.07:46:21.21#ibcon#about to read 3, iclass 39, count 0 2006.182.07:46:21.24#ibcon#read 3, iclass 39, count 0 2006.182.07:46:21.24#ibcon#about to read 4, iclass 39, count 0 2006.182.07:46:21.24#ibcon#read 4, iclass 39, count 0 2006.182.07:46:21.24#ibcon#about to read 5, iclass 39, count 0 2006.182.07:46:21.24#ibcon#read 5, iclass 39, count 0 2006.182.07:46:21.24#ibcon#about to read 6, iclass 39, count 0 2006.182.07:46:21.24#ibcon#read 6, iclass 39, count 0 2006.182.07:46:21.24#ibcon#end of sib2, iclass 39, count 0 2006.182.07:46:21.24#ibcon#*after write, iclass 39, count 0 2006.182.07:46:21.24#ibcon#*before return 0, iclass 39, count 0 2006.182.07:46:21.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:46:21.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:46:21.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:46:21.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:46:21.24$vc4f8/vblo=3,656.99 2006.182.07:46:21.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.07:46:21.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.07:46:21.24#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:21.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:46:21.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:46:21.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:46:21.24#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:46:21.24#ibcon#first serial, iclass 3, count 0 2006.182.07:46:21.24#ibcon#enter sib2, iclass 3, count 0 2006.182.07:46:21.24#ibcon#flushed, iclass 3, count 0 2006.182.07:46:21.24#ibcon#about to write, iclass 3, count 0 2006.182.07:46:21.24#ibcon#wrote, iclass 3, count 0 2006.182.07:46:21.24#ibcon#about to read 3, iclass 3, count 0 2006.182.07:46:21.26#ibcon#read 3, iclass 3, count 0 2006.182.07:46:21.26#ibcon#about to read 4, iclass 3, count 0 2006.182.07:46:21.26#ibcon#read 4, iclass 3, count 0 2006.182.07:46:21.26#ibcon#about to read 5, iclass 3, count 0 2006.182.07:46:21.26#ibcon#read 5, iclass 3, count 0 2006.182.07:46:21.26#ibcon#about to read 6, iclass 3, count 0 2006.182.07:46:21.26#ibcon#read 6, iclass 3, count 0 2006.182.07:46:21.26#ibcon#end of sib2, iclass 3, count 0 2006.182.07:46:21.26#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:46:21.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:46:21.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:46:21.26#ibcon#*before write, iclass 3, count 0 2006.182.07:46:21.26#ibcon#enter sib2, iclass 3, count 0 2006.182.07:46:21.26#ibcon#flushed, iclass 3, count 0 2006.182.07:46:21.26#ibcon#about to write, iclass 3, count 0 2006.182.07:46:21.26#ibcon#wrote, iclass 3, count 0 2006.182.07:46:21.26#ibcon#about to read 3, iclass 3, count 0 2006.182.07:46:21.30#ibcon#read 3, iclass 3, count 0 2006.182.07:46:21.30#ibcon#about to read 4, iclass 3, count 0 2006.182.07:46:21.30#ibcon#read 4, iclass 3, count 0 2006.182.07:46:21.30#ibcon#about to read 5, iclass 3, count 0 2006.182.07:46:21.30#ibcon#read 5, iclass 3, count 0 2006.182.07:46:21.30#ibcon#about to read 6, iclass 3, count 0 2006.182.07:46:21.30#ibcon#read 6, iclass 3, count 0 2006.182.07:46:21.30#ibcon#end of sib2, iclass 3, count 0 2006.182.07:46:21.30#ibcon#*after write, iclass 3, count 0 2006.182.07:46:21.30#ibcon#*before return 0, iclass 3, count 0 2006.182.07:46:21.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:46:21.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:46:21.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:46:21.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:46:21.30$vc4f8/vb=3,4 2006.182.07:46:21.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.07:46:21.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.07:46:21.30#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:21.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:46:21.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:46:21.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:46:21.36#ibcon#enter wrdev, iclass 5, count 2 2006.182.07:46:21.36#ibcon#first serial, iclass 5, count 2 2006.182.07:46:21.36#ibcon#enter sib2, iclass 5, count 2 2006.182.07:46:21.36#ibcon#flushed, iclass 5, count 2 2006.182.07:46:21.36#ibcon#about to write, iclass 5, count 2 2006.182.07:46:21.36#ibcon#wrote, iclass 5, count 2 2006.182.07:46:21.36#ibcon#about to read 3, iclass 5, count 2 2006.182.07:46:21.38#ibcon#read 3, iclass 5, count 2 2006.182.07:46:21.38#ibcon#about to read 4, iclass 5, count 2 2006.182.07:46:21.38#ibcon#read 4, iclass 5, count 2 2006.182.07:46:21.38#ibcon#about to read 5, iclass 5, count 2 2006.182.07:46:21.38#ibcon#read 5, iclass 5, count 2 2006.182.07:46:21.38#ibcon#about to read 6, iclass 5, count 2 2006.182.07:46:21.38#ibcon#read 6, iclass 5, count 2 2006.182.07:46:21.38#ibcon#end of sib2, iclass 5, count 2 2006.182.07:46:21.38#ibcon#*mode == 0, iclass 5, count 2 2006.182.07:46:21.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.07:46:21.38#ibcon#[27=AT03-04\r\n] 2006.182.07:46:21.38#ibcon#*before write, iclass 5, count 2 2006.182.07:46:21.38#ibcon#enter sib2, iclass 5, count 2 2006.182.07:46:21.38#ibcon#flushed, iclass 5, count 2 2006.182.07:46:21.38#ibcon#about to write, iclass 5, count 2 2006.182.07:46:21.38#ibcon#wrote, iclass 5, count 2 2006.182.07:46:21.38#ibcon#about to read 3, iclass 5, count 2 2006.182.07:46:21.41#ibcon#read 3, iclass 5, count 2 2006.182.07:46:21.41#ibcon#about to read 4, iclass 5, count 2 2006.182.07:46:21.41#ibcon#read 4, iclass 5, count 2 2006.182.07:46:21.41#ibcon#about to read 5, iclass 5, count 2 2006.182.07:46:21.41#ibcon#read 5, iclass 5, count 2 2006.182.07:46:21.41#ibcon#about to read 6, iclass 5, count 2 2006.182.07:46:21.41#ibcon#read 6, iclass 5, count 2 2006.182.07:46:21.41#ibcon#end of sib2, iclass 5, count 2 2006.182.07:46:21.41#ibcon#*after write, iclass 5, count 2 2006.182.07:46:21.41#ibcon#*before return 0, iclass 5, count 2 2006.182.07:46:21.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:46:21.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:46:21.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.07:46:21.41#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:21.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:46:21.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:46:21.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:46:21.53#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:46:21.53#ibcon#first serial, iclass 5, count 0 2006.182.07:46:21.53#ibcon#enter sib2, iclass 5, count 0 2006.182.07:46:21.53#ibcon#flushed, iclass 5, count 0 2006.182.07:46:21.53#ibcon#about to write, iclass 5, count 0 2006.182.07:46:21.53#ibcon#wrote, iclass 5, count 0 2006.182.07:46:21.53#ibcon#about to read 3, iclass 5, count 0 2006.182.07:46:21.55#ibcon#read 3, iclass 5, count 0 2006.182.07:46:21.55#ibcon#about to read 4, iclass 5, count 0 2006.182.07:46:21.55#ibcon#read 4, iclass 5, count 0 2006.182.07:46:21.55#ibcon#about to read 5, iclass 5, count 0 2006.182.07:46:21.55#ibcon#read 5, iclass 5, count 0 2006.182.07:46:21.55#ibcon#about to read 6, iclass 5, count 0 2006.182.07:46:21.55#ibcon#read 6, iclass 5, count 0 2006.182.07:46:21.55#ibcon#end of sib2, iclass 5, count 0 2006.182.07:46:21.55#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:46:21.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:46:21.55#ibcon#[27=USB\r\n] 2006.182.07:46:21.55#ibcon#*before write, iclass 5, count 0 2006.182.07:46:21.55#ibcon#enter sib2, iclass 5, count 0 2006.182.07:46:21.55#ibcon#flushed, iclass 5, count 0 2006.182.07:46:21.55#ibcon#about to write, iclass 5, count 0 2006.182.07:46:21.55#ibcon#wrote, iclass 5, count 0 2006.182.07:46:21.55#ibcon#about to read 3, iclass 5, count 0 2006.182.07:46:21.58#ibcon#read 3, iclass 5, count 0 2006.182.07:46:21.58#ibcon#about to read 4, iclass 5, count 0 2006.182.07:46:21.58#ibcon#read 4, iclass 5, count 0 2006.182.07:46:21.58#ibcon#about to read 5, iclass 5, count 0 2006.182.07:46:21.58#ibcon#read 5, iclass 5, count 0 2006.182.07:46:21.58#ibcon#about to read 6, iclass 5, count 0 2006.182.07:46:21.58#ibcon#read 6, iclass 5, count 0 2006.182.07:46:21.58#ibcon#end of sib2, iclass 5, count 0 2006.182.07:46:21.58#ibcon#*after write, iclass 5, count 0 2006.182.07:46:21.58#ibcon#*before return 0, iclass 5, count 0 2006.182.07:46:21.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:46:21.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:46:21.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:46:21.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:46:21.58$vc4f8/vblo=4,712.99 2006.182.07:46:21.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.07:46:21.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.07:46:21.58#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:21.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:21.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:21.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:21.58#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:46:21.58#ibcon#first serial, iclass 7, count 0 2006.182.07:46:21.58#ibcon#enter sib2, iclass 7, count 0 2006.182.07:46:21.58#ibcon#flushed, iclass 7, count 0 2006.182.07:46:21.58#ibcon#about to write, iclass 7, count 0 2006.182.07:46:21.58#ibcon#wrote, iclass 7, count 0 2006.182.07:46:21.58#ibcon#about to read 3, iclass 7, count 0 2006.182.07:46:21.60#ibcon#read 3, iclass 7, count 0 2006.182.07:46:21.60#ibcon#about to read 4, iclass 7, count 0 2006.182.07:46:21.60#ibcon#read 4, iclass 7, count 0 2006.182.07:46:21.60#ibcon#about to read 5, iclass 7, count 0 2006.182.07:46:21.60#ibcon#read 5, iclass 7, count 0 2006.182.07:46:21.60#ibcon#about to read 6, iclass 7, count 0 2006.182.07:46:21.60#ibcon#read 6, iclass 7, count 0 2006.182.07:46:21.60#ibcon#end of sib2, iclass 7, count 0 2006.182.07:46:21.60#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:46:21.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:46:21.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:46:21.60#ibcon#*before write, iclass 7, count 0 2006.182.07:46:21.60#ibcon#enter sib2, iclass 7, count 0 2006.182.07:46:21.60#ibcon#flushed, iclass 7, count 0 2006.182.07:46:21.60#ibcon#about to write, iclass 7, count 0 2006.182.07:46:21.60#ibcon#wrote, iclass 7, count 0 2006.182.07:46:21.60#ibcon#about to read 3, iclass 7, count 0 2006.182.07:46:21.64#ibcon#read 3, iclass 7, count 0 2006.182.07:46:21.64#ibcon#about to read 4, iclass 7, count 0 2006.182.07:46:21.64#ibcon#read 4, iclass 7, count 0 2006.182.07:46:21.64#ibcon#about to read 5, iclass 7, count 0 2006.182.07:46:21.64#ibcon#read 5, iclass 7, count 0 2006.182.07:46:21.64#ibcon#about to read 6, iclass 7, count 0 2006.182.07:46:21.64#ibcon#read 6, iclass 7, count 0 2006.182.07:46:21.64#ibcon#end of sib2, iclass 7, count 0 2006.182.07:46:21.64#ibcon#*after write, iclass 7, count 0 2006.182.07:46:21.64#ibcon#*before return 0, iclass 7, count 0 2006.182.07:46:21.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:21.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:46:21.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:46:21.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:46:21.64$vc4f8/vb=4,4 2006.182.07:46:21.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.07:46:21.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.07:46:21.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:21.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:21.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:21.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:21.70#ibcon#enter wrdev, iclass 11, count 2 2006.182.07:46:21.70#ibcon#first serial, iclass 11, count 2 2006.182.07:46:21.70#ibcon#enter sib2, iclass 11, count 2 2006.182.07:46:21.70#ibcon#flushed, iclass 11, count 2 2006.182.07:46:21.70#ibcon#about to write, iclass 11, count 2 2006.182.07:46:21.70#ibcon#wrote, iclass 11, count 2 2006.182.07:46:21.70#ibcon#about to read 3, iclass 11, count 2 2006.182.07:46:21.72#ibcon#read 3, iclass 11, count 2 2006.182.07:46:21.72#ibcon#about to read 4, iclass 11, count 2 2006.182.07:46:21.72#ibcon#read 4, iclass 11, count 2 2006.182.07:46:21.72#ibcon#about to read 5, iclass 11, count 2 2006.182.07:46:21.72#ibcon#read 5, iclass 11, count 2 2006.182.07:46:21.72#ibcon#about to read 6, iclass 11, count 2 2006.182.07:46:21.72#ibcon#read 6, iclass 11, count 2 2006.182.07:46:21.72#ibcon#end of sib2, iclass 11, count 2 2006.182.07:46:21.72#ibcon#*mode == 0, iclass 11, count 2 2006.182.07:46:21.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.07:46:21.72#ibcon#[27=AT04-04\r\n] 2006.182.07:46:21.72#ibcon#*before write, iclass 11, count 2 2006.182.07:46:21.72#ibcon#enter sib2, iclass 11, count 2 2006.182.07:46:21.72#ibcon#flushed, iclass 11, count 2 2006.182.07:46:21.72#ibcon#about to write, iclass 11, count 2 2006.182.07:46:21.72#ibcon#wrote, iclass 11, count 2 2006.182.07:46:21.72#ibcon#about to read 3, iclass 11, count 2 2006.182.07:46:21.75#ibcon#read 3, iclass 11, count 2 2006.182.07:46:21.75#ibcon#about to read 4, iclass 11, count 2 2006.182.07:46:21.75#ibcon#read 4, iclass 11, count 2 2006.182.07:46:21.75#ibcon#about to read 5, iclass 11, count 2 2006.182.07:46:21.75#ibcon#read 5, iclass 11, count 2 2006.182.07:46:21.75#ibcon#about to read 6, iclass 11, count 2 2006.182.07:46:21.75#ibcon#read 6, iclass 11, count 2 2006.182.07:46:21.75#ibcon#end of sib2, iclass 11, count 2 2006.182.07:46:21.75#ibcon#*after write, iclass 11, count 2 2006.182.07:46:21.75#ibcon#*before return 0, iclass 11, count 2 2006.182.07:46:21.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:21.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:46:21.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.07:46:21.75#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:21.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:21.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:21.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:21.87#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:46:21.87#ibcon#first serial, iclass 11, count 0 2006.182.07:46:21.87#ibcon#enter sib2, iclass 11, count 0 2006.182.07:46:21.87#ibcon#flushed, iclass 11, count 0 2006.182.07:46:21.87#ibcon#about to write, iclass 11, count 0 2006.182.07:46:21.87#ibcon#wrote, iclass 11, count 0 2006.182.07:46:21.87#ibcon#about to read 3, iclass 11, count 0 2006.182.07:46:21.89#ibcon#read 3, iclass 11, count 0 2006.182.07:46:21.89#ibcon#about to read 4, iclass 11, count 0 2006.182.07:46:21.89#ibcon#read 4, iclass 11, count 0 2006.182.07:46:21.89#ibcon#about to read 5, iclass 11, count 0 2006.182.07:46:21.89#ibcon#read 5, iclass 11, count 0 2006.182.07:46:21.89#ibcon#about to read 6, iclass 11, count 0 2006.182.07:46:21.89#ibcon#read 6, iclass 11, count 0 2006.182.07:46:21.89#ibcon#end of sib2, iclass 11, count 0 2006.182.07:46:21.89#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:46:21.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:46:21.89#ibcon#[27=USB\r\n] 2006.182.07:46:21.89#ibcon#*before write, iclass 11, count 0 2006.182.07:46:21.89#ibcon#enter sib2, iclass 11, count 0 2006.182.07:46:21.89#ibcon#flushed, iclass 11, count 0 2006.182.07:46:21.89#ibcon#about to write, iclass 11, count 0 2006.182.07:46:21.89#ibcon#wrote, iclass 11, count 0 2006.182.07:46:21.89#ibcon#about to read 3, iclass 11, count 0 2006.182.07:46:21.92#ibcon#read 3, iclass 11, count 0 2006.182.07:46:21.92#ibcon#about to read 4, iclass 11, count 0 2006.182.07:46:21.92#ibcon#read 4, iclass 11, count 0 2006.182.07:46:21.92#ibcon#about to read 5, iclass 11, count 0 2006.182.07:46:21.92#ibcon#read 5, iclass 11, count 0 2006.182.07:46:21.92#ibcon#about to read 6, iclass 11, count 0 2006.182.07:46:21.92#ibcon#read 6, iclass 11, count 0 2006.182.07:46:21.92#ibcon#end of sib2, iclass 11, count 0 2006.182.07:46:21.92#ibcon#*after write, iclass 11, count 0 2006.182.07:46:21.92#ibcon#*before return 0, iclass 11, count 0 2006.182.07:46:21.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:21.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:46:21.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:46:21.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:46:21.92$vc4f8/vblo=5,744.99 2006.182.07:46:21.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.07:46:21.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.07:46:21.92#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:21.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:21.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:21.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:21.92#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:46:21.92#ibcon#first serial, iclass 13, count 0 2006.182.07:46:21.92#ibcon#enter sib2, iclass 13, count 0 2006.182.07:46:21.92#ibcon#flushed, iclass 13, count 0 2006.182.07:46:21.92#ibcon#about to write, iclass 13, count 0 2006.182.07:46:21.92#ibcon#wrote, iclass 13, count 0 2006.182.07:46:21.92#ibcon#about to read 3, iclass 13, count 0 2006.182.07:46:21.94#ibcon#read 3, iclass 13, count 0 2006.182.07:46:21.94#ibcon#about to read 4, iclass 13, count 0 2006.182.07:46:21.94#ibcon#read 4, iclass 13, count 0 2006.182.07:46:21.94#ibcon#about to read 5, iclass 13, count 0 2006.182.07:46:21.94#ibcon#read 5, iclass 13, count 0 2006.182.07:46:21.94#ibcon#about to read 6, iclass 13, count 0 2006.182.07:46:21.94#ibcon#read 6, iclass 13, count 0 2006.182.07:46:21.94#ibcon#end of sib2, iclass 13, count 0 2006.182.07:46:21.94#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:46:21.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:46:21.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:46:21.94#ibcon#*before write, iclass 13, count 0 2006.182.07:46:21.94#ibcon#enter sib2, iclass 13, count 0 2006.182.07:46:21.94#ibcon#flushed, iclass 13, count 0 2006.182.07:46:21.94#ibcon#about to write, iclass 13, count 0 2006.182.07:46:21.94#ibcon#wrote, iclass 13, count 0 2006.182.07:46:21.94#ibcon#about to read 3, iclass 13, count 0 2006.182.07:46:21.98#ibcon#read 3, iclass 13, count 0 2006.182.07:46:21.98#ibcon#about to read 4, iclass 13, count 0 2006.182.07:46:21.98#ibcon#read 4, iclass 13, count 0 2006.182.07:46:21.98#ibcon#about to read 5, iclass 13, count 0 2006.182.07:46:21.98#ibcon#read 5, iclass 13, count 0 2006.182.07:46:21.98#ibcon#about to read 6, iclass 13, count 0 2006.182.07:46:21.98#ibcon#read 6, iclass 13, count 0 2006.182.07:46:21.98#ibcon#end of sib2, iclass 13, count 0 2006.182.07:46:21.98#ibcon#*after write, iclass 13, count 0 2006.182.07:46:21.98#ibcon#*before return 0, iclass 13, count 0 2006.182.07:46:21.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:21.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:46:21.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:46:21.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:46:21.98$vc4f8/vb=5,4 2006.182.07:46:21.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.182.07:46:21.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.182.07:46:21.98#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:21.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:22.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:22.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:22.04#ibcon#enter wrdev, iclass 15, count 2 2006.182.07:46:22.04#ibcon#first serial, iclass 15, count 2 2006.182.07:46:22.04#ibcon#enter sib2, iclass 15, count 2 2006.182.07:46:22.04#ibcon#flushed, iclass 15, count 2 2006.182.07:46:22.04#ibcon#about to write, iclass 15, count 2 2006.182.07:46:22.04#ibcon#wrote, iclass 15, count 2 2006.182.07:46:22.04#ibcon#about to read 3, iclass 15, count 2 2006.182.07:46:22.06#ibcon#read 3, iclass 15, count 2 2006.182.07:46:22.06#ibcon#about to read 4, iclass 15, count 2 2006.182.07:46:22.06#ibcon#read 4, iclass 15, count 2 2006.182.07:46:22.06#ibcon#about to read 5, iclass 15, count 2 2006.182.07:46:22.06#ibcon#read 5, iclass 15, count 2 2006.182.07:46:22.06#ibcon#about to read 6, iclass 15, count 2 2006.182.07:46:22.06#ibcon#read 6, iclass 15, count 2 2006.182.07:46:22.06#ibcon#end of sib2, iclass 15, count 2 2006.182.07:46:22.06#ibcon#*mode == 0, iclass 15, count 2 2006.182.07:46:22.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.182.07:46:22.06#ibcon#[27=AT05-04\r\n] 2006.182.07:46:22.06#ibcon#*before write, iclass 15, count 2 2006.182.07:46:22.06#ibcon#enter sib2, iclass 15, count 2 2006.182.07:46:22.06#ibcon#flushed, iclass 15, count 2 2006.182.07:46:22.06#ibcon#about to write, iclass 15, count 2 2006.182.07:46:22.06#ibcon#wrote, iclass 15, count 2 2006.182.07:46:22.06#ibcon#about to read 3, iclass 15, count 2 2006.182.07:46:22.09#ibcon#read 3, iclass 15, count 2 2006.182.07:46:22.09#ibcon#about to read 4, iclass 15, count 2 2006.182.07:46:22.09#ibcon#read 4, iclass 15, count 2 2006.182.07:46:22.09#ibcon#about to read 5, iclass 15, count 2 2006.182.07:46:22.09#ibcon#read 5, iclass 15, count 2 2006.182.07:46:22.09#ibcon#about to read 6, iclass 15, count 2 2006.182.07:46:22.09#ibcon#read 6, iclass 15, count 2 2006.182.07:46:22.09#ibcon#end of sib2, iclass 15, count 2 2006.182.07:46:22.09#ibcon#*after write, iclass 15, count 2 2006.182.07:46:22.09#ibcon#*before return 0, iclass 15, count 2 2006.182.07:46:22.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:22.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:46:22.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.182.07:46:22.09#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:22.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:22.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:22.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:22.21#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:46:22.21#ibcon#first serial, iclass 15, count 0 2006.182.07:46:22.21#ibcon#enter sib2, iclass 15, count 0 2006.182.07:46:22.21#ibcon#flushed, iclass 15, count 0 2006.182.07:46:22.21#ibcon#about to write, iclass 15, count 0 2006.182.07:46:22.21#ibcon#wrote, iclass 15, count 0 2006.182.07:46:22.21#ibcon#about to read 3, iclass 15, count 0 2006.182.07:46:22.24#ibcon#read 3, iclass 15, count 0 2006.182.07:46:22.24#ibcon#about to read 4, iclass 15, count 0 2006.182.07:46:22.24#ibcon#read 4, iclass 15, count 0 2006.182.07:46:22.24#ibcon#about to read 5, iclass 15, count 0 2006.182.07:46:22.24#ibcon#read 5, iclass 15, count 0 2006.182.07:46:22.24#ibcon#about to read 6, iclass 15, count 0 2006.182.07:46:22.24#ibcon#read 6, iclass 15, count 0 2006.182.07:46:22.24#ibcon#end of sib2, iclass 15, count 0 2006.182.07:46:22.24#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:46:22.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:46:22.24#ibcon#[27=USB\r\n] 2006.182.07:46:22.24#ibcon#*before write, iclass 15, count 0 2006.182.07:46:22.24#ibcon#enter sib2, iclass 15, count 0 2006.182.07:46:22.24#ibcon#flushed, iclass 15, count 0 2006.182.07:46:22.24#ibcon#about to write, iclass 15, count 0 2006.182.07:46:22.24#ibcon#wrote, iclass 15, count 0 2006.182.07:46:22.24#ibcon#about to read 3, iclass 15, count 0 2006.182.07:46:22.27#ibcon#read 3, iclass 15, count 0 2006.182.07:46:22.27#ibcon#about to read 4, iclass 15, count 0 2006.182.07:46:22.27#ibcon#read 4, iclass 15, count 0 2006.182.07:46:22.27#ibcon#about to read 5, iclass 15, count 0 2006.182.07:46:22.27#ibcon#read 5, iclass 15, count 0 2006.182.07:46:22.27#ibcon#about to read 6, iclass 15, count 0 2006.182.07:46:22.27#ibcon#read 6, iclass 15, count 0 2006.182.07:46:22.27#ibcon#end of sib2, iclass 15, count 0 2006.182.07:46:22.27#ibcon#*after write, iclass 15, count 0 2006.182.07:46:22.27#ibcon#*before return 0, iclass 15, count 0 2006.182.07:46:22.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:22.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:46:22.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:46:22.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:46:22.27$vc4f8/vblo=6,752.99 2006.182.07:46:22.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.07:46:22.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.07:46:22.27#ibcon#ireg 17 cls_cnt 0 2006.182.07:46:22.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:22.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:22.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:22.27#ibcon#enter wrdev, iclass 17, count 0 2006.182.07:46:22.27#ibcon#first serial, iclass 17, count 0 2006.182.07:46:22.27#ibcon#enter sib2, iclass 17, count 0 2006.182.07:46:22.27#ibcon#flushed, iclass 17, count 0 2006.182.07:46:22.27#ibcon#about to write, iclass 17, count 0 2006.182.07:46:22.27#ibcon#wrote, iclass 17, count 0 2006.182.07:46:22.27#ibcon#about to read 3, iclass 17, count 0 2006.182.07:46:22.29#ibcon#read 3, iclass 17, count 0 2006.182.07:46:22.29#ibcon#about to read 4, iclass 17, count 0 2006.182.07:46:22.29#ibcon#read 4, iclass 17, count 0 2006.182.07:46:22.29#ibcon#about to read 5, iclass 17, count 0 2006.182.07:46:22.29#ibcon#read 5, iclass 17, count 0 2006.182.07:46:22.29#ibcon#about to read 6, iclass 17, count 0 2006.182.07:46:22.29#ibcon#read 6, iclass 17, count 0 2006.182.07:46:22.29#ibcon#end of sib2, iclass 17, count 0 2006.182.07:46:22.29#ibcon#*mode == 0, iclass 17, count 0 2006.182.07:46:22.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.07:46:22.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:46:22.29#ibcon#*before write, iclass 17, count 0 2006.182.07:46:22.29#ibcon#enter sib2, iclass 17, count 0 2006.182.07:46:22.29#ibcon#flushed, iclass 17, count 0 2006.182.07:46:22.29#ibcon#about to write, iclass 17, count 0 2006.182.07:46:22.29#ibcon#wrote, iclass 17, count 0 2006.182.07:46:22.29#ibcon#about to read 3, iclass 17, count 0 2006.182.07:46:22.33#ibcon#read 3, iclass 17, count 0 2006.182.07:46:22.33#ibcon#about to read 4, iclass 17, count 0 2006.182.07:46:22.33#ibcon#read 4, iclass 17, count 0 2006.182.07:46:22.33#ibcon#about to read 5, iclass 17, count 0 2006.182.07:46:22.33#ibcon#read 5, iclass 17, count 0 2006.182.07:46:22.33#ibcon#about to read 6, iclass 17, count 0 2006.182.07:46:22.33#ibcon#read 6, iclass 17, count 0 2006.182.07:46:22.33#ibcon#end of sib2, iclass 17, count 0 2006.182.07:46:22.33#ibcon#*after write, iclass 17, count 0 2006.182.07:46:22.33#ibcon#*before return 0, iclass 17, count 0 2006.182.07:46:22.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:22.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:46:22.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.07:46:22.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.07:46:22.33$vc4f8/vb=6,4 2006.182.07:46:22.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.182.07:46:22.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.182.07:46:22.33#ibcon#ireg 11 cls_cnt 2 2006.182.07:46:22.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:22.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:22.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:22.39#ibcon#enter wrdev, iclass 19, count 2 2006.182.07:46:22.39#ibcon#first serial, iclass 19, count 2 2006.182.07:46:22.39#ibcon#enter sib2, iclass 19, count 2 2006.182.07:46:22.39#ibcon#flushed, iclass 19, count 2 2006.182.07:46:22.39#ibcon#about to write, iclass 19, count 2 2006.182.07:46:22.39#ibcon#wrote, iclass 19, count 2 2006.182.07:46:22.39#ibcon#about to read 3, iclass 19, count 2 2006.182.07:46:22.41#ibcon#read 3, iclass 19, count 2 2006.182.07:46:22.41#ibcon#about to read 4, iclass 19, count 2 2006.182.07:46:22.41#ibcon#read 4, iclass 19, count 2 2006.182.07:46:22.41#ibcon#about to read 5, iclass 19, count 2 2006.182.07:46:22.41#ibcon#read 5, iclass 19, count 2 2006.182.07:46:22.41#ibcon#about to read 6, iclass 19, count 2 2006.182.07:46:22.41#ibcon#read 6, iclass 19, count 2 2006.182.07:46:22.41#ibcon#end of sib2, iclass 19, count 2 2006.182.07:46:22.41#ibcon#*mode == 0, iclass 19, count 2 2006.182.07:46:22.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.182.07:46:22.41#ibcon#[27=AT06-04\r\n] 2006.182.07:46:22.41#ibcon#*before write, iclass 19, count 2 2006.182.07:46:22.41#ibcon#enter sib2, iclass 19, count 2 2006.182.07:46:22.41#ibcon#flushed, iclass 19, count 2 2006.182.07:46:22.41#ibcon#about to write, iclass 19, count 2 2006.182.07:46:22.41#ibcon#wrote, iclass 19, count 2 2006.182.07:46:22.41#ibcon#about to read 3, iclass 19, count 2 2006.182.07:46:22.44#ibcon#read 3, iclass 19, count 2 2006.182.07:46:22.44#ibcon#about to read 4, iclass 19, count 2 2006.182.07:46:22.44#ibcon#read 4, iclass 19, count 2 2006.182.07:46:22.44#ibcon#about to read 5, iclass 19, count 2 2006.182.07:46:22.44#ibcon#read 5, iclass 19, count 2 2006.182.07:46:22.44#ibcon#about to read 6, iclass 19, count 2 2006.182.07:46:22.44#ibcon#read 6, iclass 19, count 2 2006.182.07:46:22.44#ibcon#end of sib2, iclass 19, count 2 2006.182.07:46:22.44#ibcon#*after write, iclass 19, count 2 2006.182.07:46:22.44#ibcon#*before return 0, iclass 19, count 2 2006.182.07:46:22.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:22.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:46:22.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.182.07:46:22.44#ibcon#ireg 7 cls_cnt 0 2006.182.07:46:22.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:22.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:22.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:22.56#ibcon#enter wrdev, iclass 19, count 0 2006.182.07:46:22.56#ibcon#first serial, iclass 19, count 0 2006.182.07:46:22.56#ibcon#enter sib2, iclass 19, count 0 2006.182.07:46:22.56#ibcon#flushed, iclass 19, count 0 2006.182.07:46:22.56#ibcon#about to write, iclass 19, count 0 2006.182.07:46:22.56#ibcon#wrote, iclass 19, count 0 2006.182.07:46:22.56#ibcon#about to read 3, iclass 19, count 0 2006.182.07:46:22.58#ibcon#read 3, iclass 19, count 0 2006.182.07:46:22.58#ibcon#about to read 4, iclass 19, count 0 2006.182.07:46:22.58#ibcon#read 4, iclass 19, count 0 2006.182.07:46:22.58#ibcon#about to read 5, iclass 19, count 0 2006.182.07:46:22.58#ibcon#read 5, iclass 19, count 0 2006.182.07:46:22.58#ibcon#about to read 6, iclass 19, count 0 2006.182.07:46:22.58#ibcon#read 6, iclass 19, count 0 2006.182.07:46:22.58#ibcon#end of sib2, iclass 19, count 0 2006.182.07:46:22.58#ibcon#*mode == 0, iclass 19, count 0 2006.182.07:46:22.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.07:46:22.58#ibcon#[27=USB\r\n] 2006.182.07:46:22.58#ibcon#*before write, iclass 19, count 0 2006.182.07:46:22.58#ibcon#enter sib2, iclass 19, count 0 2006.182.07:46:22.58#ibcon#flushed, iclass 19, count 0 2006.182.07:46:22.58#ibcon#about to write, iclass 19, count 0 2006.182.07:46:22.58#ibcon#wrote, iclass 19, count 0 2006.182.07:46:22.58#ibcon#about to read 3, iclass 19, count 0 2006.182.07:46:22.61#ibcon#read 3, iclass 19, count 0 2006.182.07:46:22.61#ibcon#about to read 4, iclass 19, count 0 2006.182.07:46:22.61#ibcon#read 4, iclass 19, count 0 2006.182.07:46:22.61#ibcon#about to read 5, iclass 19, count 0 2006.182.07:46:22.61#ibcon#read 5, iclass 19, count 0 2006.182.07:46:22.61#ibcon#about to read 6, iclass 19, count 0 2006.182.07:46:22.61#ibcon#read 6, iclass 19, count 0 2006.182.07:46:22.61#ibcon#end of sib2, iclass 19, count 0 2006.182.07:46:22.61#ibcon#*after write, iclass 19, count 0 2006.182.07:46:22.61#ibcon#*before return 0, iclass 19, count 0 2006.182.07:46:22.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:22.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:46:22.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.07:46:22.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.07:46:22.61$vc4f8/vabw=wide 2006.182.07:46:22.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.07:46:22.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.07:46:22.61#ibcon#ireg 8 cls_cnt 0 2006.182.07:46:22.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:22.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:22.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:22.61#ibcon#enter wrdev, iclass 21, count 0 2006.182.07:46:22.61#ibcon#first serial, iclass 21, count 0 2006.182.07:46:22.61#ibcon#enter sib2, iclass 21, count 0 2006.182.07:46:22.61#ibcon#flushed, iclass 21, count 0 2006.182.07:46:22.61#ibcon#about to write, iclass 21, count 0 2006.182.07:46:22.61#ibcon#wrote, iclass 21, count 0 2006.182.07:46:22.61#ibcon#about to read 3, iclass 21, count 0 2006.182.07:46:22.63#ibcon#read 3, iclass 21, count 0 2006.182.07:46:22.63#ibcon#about to read 4, iclass 21, count 0 2006.182.07:46:22.63#ibcon#read 4, iclass 21, count 0 2006.182.07:46:22.63#ibcon#about to read 5, iclass 21, count 0 2006.182.07:46:22.63#ibcon#read 5, iclass 21, count 0 2006.182.07:46:22.63#ibcon#about to read 6, iclass 21, count 0 2006.182.07:46:22.63#ibcon#read 6, iclass 21, count 0 2006.182.07:46:22.63#ibcon#end of sib2, iclass 21, count 0 2006.182.07:46:22.63#ibcon#*mode == 0, iclass 21, count 0 2006.182.07:46:22.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.07:46:22.63#ibcon#[25=BW32\r\n] 2006.182.07:46:22.63#ibcon#*before write, iclass 21, count 0 2006.182.07:46:22.63#ibcon#enter sib2, iclass 21, count 0 2006.182.07:46:22.63#ibcon#flushed, iclass 21, count 0 2006.182.07:46:22.63#ibcon#about to write, iclass 21, count 0 2006.182.07:46:22.63#ibcon#wrote, iclass 21, count 0 2006.182.07:46:22.63#ibcon#about to read 3, iclass 21, count 0 2006.182.07:46:22.66#ibcon#read 3, iclass 21, count 0 2006.182.07:46:22.66#ibcon#about to read 4, iclass 21, count 0 2006.182.07:46:22.66#ibcon#read 4, iclass 21, count 0 2006.182.07:46:22.66#ibcon#about to read 5, iclass 21, count 0 2006.182.07:46:22.66#ibcon#read 5, iclass 21, count 0 2006.182.07:46:22.66#ibcon#about to read 6, iclass 21, count 0 2006.182.07:46:22.66#ibcon#read 6, iclass 21, count 0 2006.182.07:46:22.66#ibcon#end of sib2, iclass 21, count 0 2006.182.07:46:22.66#ibcon#*after write, iclass 21, count 0 2006.182.07:46:22.66#ibcon#*before return 0, iclass 21, count 0 2006.182.07:46:22.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:22.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:46:22.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.07:46:22.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.07:46:22.66$vc4f8/vbbw=wide 2006.182.07:46:22.66#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.07:46:22.66#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.07:46:22.66#ibcon#ireg 8 cls_cnt 0 2006.182.07:46:22.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:46:22.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:46:22.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:46:22.73#ibcon#enter wrdev, iclass 23, count 0 2006.182.07:46:22.73#ibcon#first serial, iclass 23, count 0 2006.182.07:46:22.73#ibcon#enter sib2, iclass 23, count 0 2006.182.07:46:22.73#ibcon#flushed, iclass 23, count 0 2006.182.07:46:22.73#ibcon#about to write, iclass 23, count 0 2006.182.07:46:22.73#ibcon#wrote, iclass 23, count 0 2006.182.07:46:22.73#ibcon#about to read 3, iclass 23, count 0 2006.182.07:46:22.75#ibcon#read 3, iclass 23, count 0 2006.182.07:46:22.75#ibcon#about to read 4, iclass 23, count 0 2006.182.07:46:22.75#ibcon#read 4, iclass 23, count 0 2006.182.07:46:22.75#ibcon#about to read 5, iclass 23, count 0 2006.182.07:46:22.75#ibcon#read 5, iclass 23, count 0 2006.182.07:46:22.75#ibcon#about to read 6, iclass 23, count 0 2006.182.07:46:22.75#ibcon#read 6, iclass 23, count 0 2006.182.07:46:22.75#ibcon#end of sib2, iclass 23, count 0 2006.182.07:46:22.75#ibcon#*mode == 0, iclass 23, count 0 2006.182.07:46:22.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.07:46:22.75#ibcon#[27=BW32\r\n] 2006.182.07:46:22.75#ibcon#*before write, iclass 23, count 0 2006.182.07:46:22.75#ibcon#enter sib2, iclass 23, count 0 2006.182.07:46:22.75#ibcon#flushed, iclass 23, count 0 2006.182.07:46:22.75#ibcon#about to write, iclass 23, count 0 2006.182.07:46:22.75#ibcon#wrote, iclass 23, count 0 2006.182.07:46:22.75#ibcon#about to read 3, iclass 23, count 0 2006.182.07:46:22.78#ibcon#read 3, iclass 23, count 0 2006.182.07:46:22.78#ibcon#about to read 4, iclass 23, count 0 2006.182.07:46:22.78#ibcon#read 4, iclass 23, count 0 2006.182.07:46:22.78#ibcon#about to read 5, iclass 23, count 0 2006.182.07:46:22.78#ibcon#read 5, iclass 23, count 0 2006.182.07:46:22.78#ibcon#about to read 6, iclass 23, count 0 2006.182.07:46:22.78#ibcon#read 6, iclass 23, count 0 2006.182.07:46:22.78#ibcon#end of sib2, iclass 23, count 0 2006.182.07:46:22.78#ibcon#*after write, iclass 23, count 0 2006.182.07:46:22.78#ibcon#*before return 0, iclass 23, count 0 2006.182.07:46:22.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:46:22.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:46:22.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.07:46:22.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.07:46:22.78$4f8m12a/ifd4f 2006.182.07:46:22.78$ifd4f/lo= 2006.182.07:46:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:46:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:46:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:46:22.78$ifd4f/patch= 2006.182.07:46:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:46:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:46:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:46:22.78$4f8m12a/"form=m,16.000,1:2 2006.182.07:46:22.78$4f8m12a/"tpicd 2006.182.07:46:22.78$4f8m12a/echo=off 2006.182.07:46:22.78$4f8m12a/xlog=off 2006.182.07:46:22.78:!2006.182.07:47:30 2006.182.07:47:11.13#trakl#Source acquired 2006.182.07:47:11.13#flagr#flagr/antenna,acquired 2006.182.07:47:30.00:preob 2006.182.07:47:30.14/onsource/TRACKING 2006.182.07:47:30.14:!2006.182.07:47:40 2006.182.07:47:40.00:data_valid=on 2006.182.07:47:40.00:midob 2006.182.07:47:41.14/onsource/TRACKING 2006.182.07:47:41.14/wx/27.60,1002.8,79 2006.182.07:47:41.33/cable/+6.4651E-03 2006.182.07:47:42.42/va/01,08,usb,yes,29,31 2006.182.07:47:42.42/va/02,07,usb,yes,30,31 2006.182.07:47:42.42/va/03,06,usb,yes,31,32 2006.182.07:47:42.42/va/04,07,usb,yes,31,33 2006.182.07:47:42.42/va/05,07,usb,yes,32,34 2006.182.07:47:42.42/va/06,06,usb,yes,31,31 2006.182.07:47:42.42/va/07,06,usb,yes,32,31 2006.182.07:47:42.42/va/08,07,usb,yes,30,29 2006.182.07:47:42.65/valo/01,532.99,yes,locked 2006.182.07:47:42.65/valo/02,572.99,yes,locked 2006.182.07:47:42.65/valo/03,672.99,yes,locked 2006.182.07:47:42.65/valo/04,832.99,yes,locked 2006.182.07:47:42.65/valo/05,652.99,yes,locked 2006.182.07:47:42.65/valo/06,772.99,yes,locked 2006.182.07:47:42.65/valo/07,832.99,yes,locked 2006.182.07:47:42.65/valo/08,852.99,yes,locked 2006.182.07:47:43.74/vb/01,04,usb,yes,30,28 2006.182.07:47:43.74/vb/02,04,usb,yes,31,33 2006.182.07:47:43.74/vb/03,04,usb,yes,28,31 2006.182.07:47:43.74/vb/04,04,usb,yes,29,29 2006.182.07:47:43.74/vb/05,04,usb,yes,27,31 2006.182.07:47:43.74/vb/06,04,usb,yes,28,31 2006.182.07:47:43.74/vb/07,04,usb,yes,30,30 2006.182.07:47:43.74/vb/08,04,usb,yes,28,31 2006.182.07:47:43.97/vblo/01,632.99,yes,locked 2006.182.07:47:43.97/vblo/02,640.99,yes,locked 2006.182.07:47:43.97/vblo/03,656.99,yes,locked 2006.182.07:47:43.97/vblo/04,712.99,yes,locked 2006.182.07:47:43.97/vblo/05,744.99,yes,locked 2006.182.07:47:43.97/vblo/06,752.99,yes,locked 2006.182.07:47:43.97/vblo/07,734.99,yes,locked 2006.182.07:47:43.97/vblo/08,744.99,yes,locked 2006.182.07:47:44.12/vabw/8 2006.182.07:47:44.27/vbbw/8 2006.182.07:47:44.36/xfe/off,on,15.2 2006.182.07:47:44.75/ifatt/23,28,28,28 2006.182.07:47:45.08/fmout-gps/S +3.38E-07 2006.182.07:47:45.15:!2006.182.07:48:40 2006.182.07:48:40.00:data_valid=off 2006.182.07:48:40.00:postob 2006.182.07:48:40.16/cable/+6.4645E-03 2006.182.07:48:40.16/wx/27.61,1002.8,80 2006.182.07:48:41.08/fmout-gps/S +3.37E-07 2006.182.07:48:41.08:scan_name=182-0749,k06182,60 2006.182.07:48:41.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.182.07:48:41.14#flagr#flagr/antenna,new-source 2006.182.07:48:42.14:checkk5 2006.182.07:48:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:48:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:48:43.23/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:48:43.60/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:48:43.97/chk_obsdata//k5ts1/T1820747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:48:44.35/chk_obsdata//k5ts2/T1820747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:48:44.72/chk_obsdata//k5ts3/T1820747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:48:45.09/chk_obsdata//k5ts4/T1820747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:48:45.78/k5log//k5ts1_log_newline 2006.182.07:48:46.46/k5log//k5ts2_log_newline 2006.182.07:48:47.16/k5log//k5ts3_log_newline 2006.182.07:48:47.85/k5log//k5ts4_log_newline 2006.182.07:48:47.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:48:47.87:4f8m12a=1 2006.182.07:48:47.87$4f8m12a/echo=on 2006.182.07:48:47.87$4f8m12a/pcalon 2006.182.07:48:47.87$pcalon/"no phase cal control is implemented here 2006.182.07:48:47.87$4f8m12a/"tpicd=stop 2006.182.07:48:47.87$4f8m12a/vc4f8 2006.182.07:48:47.87$vc4f8/valo=1,532.99 2006.182.07:48:47.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.07:48:47.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.07:48:47.87#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:47.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:48:47.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:48:47.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:48:47.87#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:48:47.87#ibcon#first serial, iclass 10, count 0 2006.182.07:48:47.87#ibcon#enter sib2, iclass 10, count 0 2006.182.07:48:47.87#ibcon#flushed, iclass 10, count 0 2006.182.07:48:47.87#ibcon#about to write, iclass 10, count 0 2006.182.07:48:47.87#ibcon#wrote, iclass 10, count 0 2006.182.07:48:47.87#ibcon#about to read 3, iclass 10, count 0 2006.182.07:48:47.91#ibcon#read 3, iclass 10, count 0 2006.182.07:48:47.91#ibcon#about to read 4, iclass 10, count 0 2006.182.07:48:47.91#ibcon#read 4, iclass 10, count 0 2006.182.07:48:47.91#ibcon#about to read 5, iclass 10, count 0 2006.182.07:48:47.91#ibcon#read 5, iclass 10, count 0 2006.182.07:48:47.91#ibcon#about to read 6, iclass 10, count 0 2006.182.07:48:47.91#ibcon#read 6, iclass 10, count 0 2006.182.07:48:47.91#ibcon#end of sib2, iclass 10, count 0 2006.182.07:48:47.91#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:48:47.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:48:47.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:48:47.91#ibcon#*before write, iclass 10, count 0 2006.182.07:48:47.91#ibcon#enter sib2, iclass 10, count 0 2006.182.07:48:47.91#ibcon#flushed, iclass 10, count 0 2006.182.07:48:47.91#ibcon#about to write, iclass 10, count 0 2006.182.07:48:47.91#ibcon#wrote, iclass 10, count 0 2006.182.07:48:47.91#ibcon#about to read 3, iclass 10, count 0 2006.182.07:48:47.96#ibcon#read 3, iclass 10, count 0 2006.182.07:48:47.96#ibcon#about to read 4, iclass 10, count 0 2006.182.07:48:47.96#ibcon#read 4, iclass 10, count 0 2006.182.07:48:47.96#ibcon#about to read 5, iclass 10, count 0 2006.182.07:48:47.96#ibcon#read 5, iclass 10, count 0 2006.182.07:48:47.96#ibcon#about to read 6, iclass 10, count 0 2006.182.07:48:47.96#ibcon#read 6, iclass 10, count 0 2006.182.07:48:47.96#ibcon#end of sib2, iclass 10, count 0 2006.182.07:48:47.96#ibcon#*after write, iclass 10, count 0 2006.182.07:48:47.96#ibcon#*before return 0, iclass 10, count 0 2006.182.07:48:47.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:48:47.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:48:47.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:48:47.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:48:47.96$vc4f8/va=1,8 2006.182.07:48:47.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.07:48:47.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.07:48:47.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:47.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:48:47.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:48:47.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:48:47.96#ibcon#enter wrdev, iclass 12, count 2 2006.182.07:48:47.96#ibcon#first serial, iclass 12, count 2 2006.182.07:48:47.96#ibcon#enter sib2, iclass 12, count 2 2006.182.07:48:47.96#ibcon#flushed, iclass 12, count 2 2006.182.07:48:47.96#ibcon#about to write, iclass 12, count 2 2006.182.07:48:47.96#ibcon#wrote, iclass 12, count 2 2006.182.07:48:47.96#ibcon#about to read 3, iclass 12, count 2 2006.182.07:48:47.98#ibcon#read 3, iclass 12, count 2 2006.182.07:48:47.98#ibcon#about to read 4, iclass 12, count 2 2006.182.07:48:47.98#ibcon#read 4, iclass 12, count 2 2006.182.07:48:47.98#ibcon#about to read 5, iclass 12, count 2 2006.182.07:48:47.98#ibcon#read 5, iclass 12, count 2 2006.182.07:48:47.98#ibcon#about to read 6, iclass 12, count 2 2006.182.07:48:47.98#ibcon#read 6, iclass 12, count 2 2006.182.07:48:47.98#ibcon#end of sib2, iclass 12, count 2 2006.182.07:48:47.98#ibcon#*mode == 0, iclass 12, count 2 2006.182.07:48:47.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.07:48:47.98#ibcon#[25=AT01-08\r\n] 2006.182.07:48:47.98#ibcon#*before write, iclass 12, count 2 2006.182.07:48:47.98#ibcon#enter sib2, iclass 12, count 2 2006.182.07:48:47.98#ibcon#flushed, iclass 12, count 2 2006.182.07:48:47.98#ibcon#about to write, iclass 12, count 2 2006.182.07:48:47.98#ibcon#wrote, iclass 12, count 2 2006.182.07:48:47.98#ibcon#about to read 3, iclass 12, count 2 2006.182.07:48:48.01#ibcon#read 3, iclass 12, count 2 2006.182.07:48:48.01#ibcon#about to read 4, iclass 12, count 2 2006.182.07:48:48.01#ibcon#read 4, iclass 12, count 2 2006.182.07:48:48.01#ibcon#about to read 5, iclass 12, count 2 2006.182.07:48:48.01#ibcon#read 5, iclass 12, count 2 2006.182.07:48:48.01#ibcon#about to read 6, iclass 12, count 2 2006.182.07:48:48.01#ibcon#read 6, iclass 12, count 2 2006.182.07:48:48.01#ibcon#end of sib2, iclass 12, count 2 2006.182.07:48:48.01#ibcon#*after write, iclass 12, count 2 2006.182.07:48:48.01#ibcon#*before return 0, iclass 12, count 2 2006.182.07:48:48.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:48:48.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:48:48.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.07:48:48.01#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:48.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:48:48.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:48:48.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:48:48.13#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:48:48.13#ibcon#first serial, iclass 12, count 0 2006.182.07:48:48.13#ibcon#enter sib2, iclass 12, count 0 2006.182.07:48:48.13#ibcon#flushed, iclass 12, count 0 2006.182.07:48:48.13#ibcon#about to write, iclass 12, count 0 2006.182.07:48:48.13#ibcon#wrote, iclass 12, count 0 2006.182.07:48:48.13#ibcon#about to read 3, iclass 12, count 0 2006.182.07:48:48.15#ibcon#read 3, iclass 12, count 0 2006.182.07:48:48.15#ibcon#about to read 4, iclass 12, count 0 2006.182.07:48:48.15#ibcon#read 4, iclass 12, count 0 2006.182.07:48:48.15#ibcon#about to read 5, iclass 12, count 0 2006.182.07:48:48.15#ibcon#read 5, iclass 12, count 0 2006.182.07:48:48.15#ibcon#about to read 6, iclass 12, count 0 2006.182.07:48:48.15#ibcon#read 6, iclass 12, count 0 2006.182.07:48:48.15#ibcon#end of sib2, iclass 12, count 0 2006.182.07:48:48.15#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:48:48.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:48:48.15#ibcon#[25=USB\r\n] 2006.182.07:48:48.15#ibcon#*before write, iclass 12, count 0 2006.182.07:48:48.15#ibcon#enter sib2, iclass 12, count 0 2006.182.07:48:48.15#ibcon#flushed, iclass 12, count 0 2006.182.07:48:48.15#ibcon#about to write, iclass 12, count 0 2006.182.07:48:48.15#ibcon#wrote, iclass 12, count 0 2006.182.07:48:48.15#ibcon#about to read 3, iclass 12, count 0 2006.182.07:48:48.18#ibcon#read 3, iclass 12, count 0 2006.182.07:48:48.18#ibcon#about to read 4, iclass 12, count 0 2006.182.07:48:48.18#ibcon#read 4, iclass 12, count 0 2006.182.07:48:48.18#ibcon#about to read 5, iclass 12, count 0 2006.182.07:48:48.18#ibcon#read 5, iclass 12, count 0 2006.182.07:48:48.18#ibcon#about to read 6, iclass 12, count 0 2006.182.07:48:48.18#ibcon#read 6, iclass 12, count 0 2006.182.07:48:48.18#ibcon#end of sib2, iclass 12, count 0 2006.182.07:48:48.18#ibcon#*after write, iclass 12, count 0 2006.182.07:48:48.18#ibcon#*before return 0, iclass 12, count 0 2006.182.07:48:48.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:48:48.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:48:48.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:48:48.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:48:48.18$vc4f8/valo=2,572.99 2006.182.07:48:48.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.07:48:48.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.07:48:48.18#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:48.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:48.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:48.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:48.18#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:48:48.18#ibcon#first serial, iclass 14, count 0 2006.182.07:48:48.18#ibcon#enter sib2, iclass 14, count 0 2006.182.07:48:48.18#ibcon#flushed, iclass 14, count 0 2006.182.07:48:48.18#ibcon#about to write, iclass 14, count 0 2006.182.07:48:48.18#ibcon#wrote, iclass 14, count 0 2006.182.07:48:48.18#ibcon#about to read 3, iclass 14, count 0 2006.182.07:48:48.20#ibcon#read 3, iclass 14, count 0 2006.182.07:48:48.20#ibcon#about to read 4, iclass 14, count 0 2006.182.07:48:48.20#ibcon#read 4, iclass 14, count 0 2006.182.07:48:48.20#ibcon#about to read 5, iclass 14, count 0 2006.182.07:48:48.20#ibcon#read 5, iclass 14, count 0 2006.182.07:48:48.20#ibcon#about to read 6, iclass 14, count 0 2006.182.07:48:48.20#ibcon#read 6, iclass 14, count 0 2006.182.07:48:48.20#ibcon#end of sib2, iclass 14, count 0 2006.182.07:48:48.20#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:48:48.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:48:48.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:48:48.20#ibcon#*before write, iclass 14, count 0 2006.182.07:48:48.20#ibcon#enter sib2, iclass 14, count 0 2006.182.07:48:48.20#ibcon#flushed, iclass 14, count 0 2006.182.07:48:48.20#ibcon#about to write, iclass 14, count 0 2006.182.07:48:48.20#ibcon#wrote, iclass 14, count 0 2006.182.07:48:48.20#ibcon#about to read 3, iclass 14, count 0 2006.182.07:48:48.25#ibcon#read 3, iclass 14, count 0 2006.182.07:48:48.25#ibcon#about to read 4, iclass 14, count 0 2006.182.07:48:48.25#ibcon#read 4, iclass 14, count 0 2006.182.07:48:48.25#ibcon#about to read 5, iclass 14, count 0 2006.182.07:48:48.25#ibcon#read 5, iclass 14, count 0 2006.182.07:48:48.25#ibcon#about to read 6, iclass 14, count 0 2006.182.07:48:48.25#ibcon#read 6, iclass 14, count 0 2006.182.07:48:48.25#ibcon#end of sib2, iclass 14, count 0 2006.182.07:48:48.25#ibcon#*after write, iclass 14, count 0 2006.182.07:48:48.25#ibcon#*before return 0, iclass 14, count 0 2006.182.07:48:48.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:48.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:48.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:48:48.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:48:48.25$vc4f8/va=2,7 2006.182.07:48:48.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.07:48:48.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.07:48:48.25#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:48.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:48.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:48.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:48.30#ibcon#enter wrdev, iclass 16, count 2 2006.182.07:48:48.30#ibcon#first serial, iclass 16, count 2 2006.182.07:48:48.30#ibcon#enter sib2, iclass 16, count 2 2006.182.07:48:48.30#ibcon#flushed, iclass 16, count 2 2006.182.07:48:48.30#ibcon#about to write, iclass 16, count 2 2006.182.07:48:48.30#ibcon#wrote, iclass 16, count 2 2006.182.07:48:48.30#ibcon#about to read 3, iclass 16, count 2 2006.182.07:48:48.32#ibcon#read 3, iclass 16, count 2 2006.182.07:48:48.32#ibcon#about to read 4, iclass 16, count 2 2006.182.07:48:48.32#ibcon#read 4, iclass 16, count 2 2006.182.07:48:48.32#ibcon#about to read 5, iclass 16, count 2 2006.182.07:48:48.32#ibcon#read 5, iclass 16, count 2 2006.182.07:48:48.32#ibcon#about to read 6, iclass 16, count 2 2006.182.07:48:48.32#ibcon#read 6, iclass 16, count 2 2006.182.07:48:48.32#ibcon#end of sib2, iclass 16, count 2 2006.182.07:48:48.32#ibcon#*mode == 0, iclass 16, count 2 2006.182.07:48:48.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.07:48:48.32#ibcon#[25=AT02-07\r\n] 2006.182.07:48:48.32#ibcon#*before write, iclass 16, count 2 2006.182.07:48:48.32#ibcon#enter sib2, iclass 16, count 2 2006.182.07:48:48.32#ibcon#flushed, iclass 16, count 2 2006.182.07:48:48.32#ibcon#about to write, iclass 16, count 2 2006.182.07:48:48.32#ibcon#wrote, iclass 16, count 2 2006.182.07:48:48.32#ibcon#about to read 3, iclass 16, count 2 2006.182.07:48:48.35#ibcon#read 3, iclass 16, count 2 2006.182.07:48:48.35#ibcon#about to read 4, iclass 16, count 2 2006.182.07:48:48.35#ibcon#read 4, iclass 16, count 2 2006.182.07:48:48.35#ibcon#about to read 5, iclass 16, count 2 2006.182.07:48:48.35#ibcon#read 5, iclass 16, count 2 2006.182.07:48:48.35#ibcon#about to read 6, iclass 16, count 2 2006.182.07:48:48.35#ibcon#read 6, iclass 16, count 2 2006.182.07:48:48.35#ibcon#end of sib2, iclass 16, count 2 2006.182.07:48:48.35#ibcon#*after write, iclass 16, count 2 2006.182.07:48:48.35#ibcon#*before return 0, iclass 16, count 2 2006.182.07:48:48.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:48.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:48.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.07:48:48.35#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:48.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:48.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:48.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:48.47#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:48:48.47#ibcon#first serial, iclass 16, count 0 2006.182.07:48:48.47#ibcon#enter sib2, iclass 16, count 0 2006.182.07:48:48.47#ibcon#flushed, iclass 16, count 0 2006.182.07:48:48.47#ibcon#about to write, iclass 16, count 0 2006.182.07:48:48.47#ibcon#wrote, iclass 16, count 0 2006.182.07:48:48.47#ibcon#about to read 3, iclass 16, count 0 2006.182.07:48:48.49#ibcon#read 3, iclass 16, count 0 2006.182.07:48:48.49#ibcon#about to read 4, iclass 16, count 0 2006.182.07:48:48.49#ibcon#read 4, iclass 16, count 0 2006.182.07:48:48.49#ibcon#about to read 5, iclass 16, count 0 2006.182.07:48:48.49#ibcon#read 5, iclass 16, count 0 2006.182.07:48:48.49#ibcon#about to read 6, iclass 16, count 0 2006.182.07:48:48.49#ibcon#read 6, iclass 16, count 0 2006.182.07:48:48.49#ibcon#end of sib2, iclass 16, count 0 2006.182.07:48:48.49#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:48:48.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:48:48.49#ibcon#[25=USB\r\n] 2006.182.07:48:48.49#ibcon#*before write, iclass 16, count 0 2006.182.07:48:48.49#ibcon#enter sib2, iclass 16, count 0 2006.182.07:48:48.49#ibcon#flushed, iclass 16, count 0 2006.182.07:48:48.49#ibcon#about to write, iclass 16, count 0 2006.182.07:48:48.49#ibcon#wrote, iclass 16, count 0 2006.182.07:48:48.49#ibcon#about to read 3, iclass 16, count 0 2006.182.07:48:48.52#ibcon#read 3, iclass 16, count 0 2006.182.07:48:48.52#ibcon#about to read 4, iclass 16, count 0 2006.182.07:48:48.52#ibcon#read 4, iclass 16, count 0 2006.182.07:48:48.52#ibcon#about to read 5, iclass 16, count 0 2006.182.07:48:48.52#ibcon#read 5, iclass 16, count 0 2006.182.07:48:48.52#ibcon#about to read 6, iclass 16, count 0 2006.182.07:48:48.52#ibcon#read 6, iclass 16, count 0 2006.182.07:48:48.52#ibcon#end of sib2, iclass 16, count 0 2006.182.07:48:48.52#ibcon#*after write, iclass 16, count 0 2006.182.07:48:48.52#ibcon#*before return 0, iclass 16, count 0 2006.182.07:48:48.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:48.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:48.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:48:48.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:48:48.52$vc4f8/valo=3,672.99 2006.182.07:48:48.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.07:48:48.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.07:48:48.52#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:48.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:48.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:48.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:48.52#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:48:48.52#ibcon#first serial, iclass 18, count 0 2006.182.07:48:48.52#ibcon#enter sib2, iclass 18, count 0 2006.182.07:48:48.52#ibcon#flushed, iclass 18, count 0 2006.182.07:48:48.52#ibcon#about to write, iclass 18, count 0 2006.182.07:48:48.52#ibcon#wrote, iclass 18, count 0 2006.182.07:48:48.52#ibcon#about to read 3, iclass 18, count 0 2006.182.07:48:48.54#ibcon#read 3, iclass 18, count 0 2006.182.07:48:48.54#ibcon#about to read 4, iclass 18, count 0 2006.182.07:48:48.54#ibcon#read 4, iclass 18, count 0 2006.182.07:48:48.54#ibcon#about to read 5, iclass 18, count 0 2006.182.07:48:48.54#ibcon#read 5, iclass 18, count 0 2006.182.07:48:48.54#ibcon#about to read 6, iclass 18, count 0 2006.182.07:48:48.54#ibcon#read 6, iclass 18, count 0 2006.182.07:48:48.54#ibcon#end of sib2, iclass 18, count 0 2006.182.07:48:48.54#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:48:48.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:48:48.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:48:48.54#ibcon#*before write, iclass 18, count 0 2006.182.07:48:48.54#ibcon#enter sib2, iclass 18, count 0 2006.182.07:48:48.54#ibcon#flushed, iclass 18, count 0 2006.182.07:48:48.54#ibcon#about to write, iclass 18, count 0 2006.182.07:48:48.54#ibcon#wrote, iclass 18, count 0 2006.182.07:48:48.54#ibcon#about to read 3, iclass 18, count 0 2006.182.07:48:48.59#ibcon#read 3, iclass 18, count 0 2006.182.07:48:48.59#ibcon#about to read 4, iclass 18, count 0 2006.182.07:48:48.59#ibcon#read 4, iclass 18, count 0 2006.182.07:48:48.59#ibcon#about to read 5, iclass 18, count 0 2006.182.07:48:48.59#ibcon#read 5, iclass 18, count 0 2006.182.07:48:48.59#ibcon#about to read 6, iclass 18, count 0 2006.182.07:48:48.59#ibcon#read 6, iclass 18, count 0 2006.182.07:48:48.59#ibcon#end of sib2, iclass 18, count 0 2006.182.07:48:48.59#ibcon#*after write, iclass 18, count 0 2006.182.07:48:48.59#ibcon#*before return 0, iclass 18, count 0 2006.182.07:48:48.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:48.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:48.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:48:48.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:48:48.59$vc4f8/va=3,6 2006.182.07:48:48.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.07:48:48.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.07:48:48.59#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:48.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:48.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:48.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:48.64#ibcon#enter wrdev, iclass 20, count 2 2006.182.07:48:48.64#ibcon#first serial, iclass 20, count 2 2006.182.07:48:48.64#ibcon#enter sib2, iclass 20, count 2 2006.182.07:48:48.64#ibcon#flushed, iclass 20, count 2 2006.182.07:48:48.64#ibcon#about to write, iclass 20, count 2 2006.182.07:48:48.64#ibcon#wrote, iclass 20, count 2 2006.182.07:48:48.64#ibcon#about to read 3, iclass 20, count 2 2006.182.07:48:48.66#ibcon#read 3, iclass 20, count 2 2006.182.07:48:48.66#ibcon#about to read 4, iclass 20, count 2 2006.182.07:48:48.66#ibcon#read 4, iclass 20, count 2 2006.182.07:48:48.66#ibcon#about to read 5, iclass 20, count 2 2006.182.07:48:48.66#ibcon#read 5, iclass 20, count 2 2006.182.07:48:48.66#ibcon#about to read 6, iclass 20, count 2 2006.182.07:48:48.66#ibcon#read 6, iclass 20, count 2 2006.182.07:48:48.66#ibcon#end of sib2, iclass 20, count 2 2006.182.07:48:48.66#ibcon#*mode == 0, iclass 20, count 2 2006.182.07:48:48.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.07:48:48.66#ibcon#[25=AT03-06\r\n] 2006.182.07:48:48.66#ibcon#*before write, iclass 20, count 2 2006.182.07:48:48.66#ibcon#enter sib2, iclass 20, count 2 2006.182.07:48:48.66#ibcon#flushed, iclass 20, count 2 2006.182.07:48:48.66#ibcon#about to write, iclass 20, count 2 2006.182.07:48:48.66#ibcon#wrote, iclass 20, count 2 2006.182.07:48:48.66#ibcon#about to read 3, iclass 20, count 2 2006.182.07:48:48.69#ibcon#read 3, iclass 20, count 2 2006.182.07:48:48.69#ibcon#about to read 4, iclass 20, count 2 2006.182.07:48:48.69#ibcon#read 4, iclass 20, count 2 2006.182.07:48:48.69#ibcon#about to read 5, iclass 20, count 2 2006.182.07:48:48.69#ibcon#read 5, iclass 20, count 2 2006.182.07:48:48.69#ibcon#about to read 6, iclass 20, count 2 2006.182.07:48:48.69#ibcon#read 6, iclass 20, count 2 2006.182.07:48:48.69#ibcon#end of sib2, iclass 20, count 2 2006.182.07:48:48.69#ibcon#*after write, iclass 20, count 2 2006.182.07:48:48.69#ibcon#*before return 0, iclass 20, count 2 2006.182.07:48:48.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:48.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:48.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.07:48:48.69#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:48.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:48.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:48.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:48.81#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:48:48.81#ibcon#first serial, iclass 20, count 0 2006.182.07:48:48.81#ibcon#enter sib2, iclass 20, count 0 2006.182.07:48:48.81#ibcon#flushed, iclass 20, count 0 2006.182.07:48:48.81#ibcon#about to write, iclass 20, count 0 2006.182.07:48:48.81#ibcon#wrote, iclass 20, count 0 2006.182.07:48:48.81#ibcon#about to read 3, iclass 20, count 0 2006.182.07:48:48.83#ibcon#read 3, iclass 20, count 0 2006.182.07:48:48.83#ibcon#about to read 4, iclass 20, count 0 2006.182.07:48:48.83#ibcon#read 4, iclass 20, count 0 2006.182.07:48:48.83#ibcon#about to read 5, iclass 20, count 0 2006.182.07:48:48.83#ibcon#read 5, iclass 20, count 0 2006.182.07:48:48.83#ibcon#about to read 6, iclass 20, count 0 2006.182.07:48:48.83#ibcon#read 6, iclass 20, count 0 2006.182.07:48:48.83#ibcon#end of sib2, iclass 20, count 0 2006.182.07:48:48.83#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:48:48.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:48:48.83#ibcon#[25=USB\r\n] 2006.182.07:48:48.83#ibcon#*before write, iclass 20, count 0 2006.182.07:48:48.83#ibcon#enter sib2, iclass 20, count 0 2006.182.07:48:48.83#ibcon#flushed, iclass 20, count 0 2006.182.07:48:48.83#ibcon#about to write, iclass 20, count 0 2006.182.07:48:48.83#ibcon#wrote, iclass 20, count 0 2006.182.07:48:48.83#ibcon#about to read 3, iclass 20, count 0 2006.182.07:48:48.86#ibcon#read 3, iclass 20, count 0 2006.182.07:48:48.86#ibcon#about to read 4, iclass 20, count 0 2006.182.07:48:48.86#ibcon#read 4, iclass 20, count 0 2006.182.07:48:48.86#ibcon#about to read 5, iclass 20, count 0 2006.182.07:48:48.86#ibcon#read 5, iclass 20, count 0 2006.182.07:48:48.86#ibcon#about to read 6, iclass 20, count 0 2006.182.07:48:48.86#ibcon#read 6, iclass 20, count 0 2006.182.07:48:48.86#ibcon#end of sib2, iclass 20, count 0 2006.182.07:48:48.86#ibcon#*after write, iclass 20, count 0 2006.182.07:48:48.86#ibcon#*before return 0, iclass 20, count 0 2006.182.07:48:48.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:48.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:48.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:48:48.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:48:48.86$vc4f8/valo=4,832.99 2006.182.07:48:48.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.07:48:48.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.07:48:48.86#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:48.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:48.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:48.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:48.86#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:48:48.86#ibcon#first serial, iclass 22, count 0 2006.182.07:48:48.86#ibcon#enter sib2, iclass 22, count 0 2006.182.07:48:48.86#ibcon#flushed, iclass 22, count 0 2006.182.07:48:48.86#ibcon#about to write, iclass 22, count 0 2006.182.07:48:48.86#ibcon#wrote, iclass 22, count 0 2006.182.07:48:48.86#ibcon#about to read 3, iclass 22, count 0 2006.182.07:48:48.88#ibcon#read 3, iclass 22, count 0 2006.182.07:48:48.88#ibcon#about to read 4, iclass 22, count 0 2006.182.07:48:48.88#ibcon#read 4, iclass 22, count 0 2006.182.07:48:48.88#ibcon#about to read 5, iclass 22, count 0 2006.182.07:48:48.88#ibcon#read 5, iclass 22, count 0 2006.182.07:48:48.88#ibcon#about to read 6, iclass 22, count 0 2006.182.07:48:48.88#ibcon#read 6, iclass 22, count 0 2006.182.07:48:48.88#ibcon#end of sib2, iclass 22, count 0 2006.182.07:48:48.88#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:48:48.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:48:48.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:48:48.88#ibcon#*before write, iclass 22, count 0 2006.182.07:48:48.88#ibcon#enter sib2, iclass 22, count 0 2006.182.07:48:48.88#ibcon#flushed, iclass 22, count 0 2006.182.07:48:48.88#ibcon#about to write, iclass 22, count 0 2006.182.07:48:48.88#ibcon#wrote, iclass 22, count 0 2006.182.07:48:48.88#ibcon#about to read 3, iclass 22, count 0 2006.182.07:48:48.93#ibcon#read 3, iclass 22, count 0 2006.182.07:48:48.93#ibcon#about to read 4, iclass 22, count 0 2006.182.07:48:48.93#ibcon#read 4, iclass 22, count 0 2006.182.07:48:48.93#ibcon#about to read 5, iclass 22, count 0 2006.182.07:48:48.93#ibcon#read 5, iclass 22, count 0 2006.182.07:48:48.93#ibcon#about to read 6, iclass 22, count 0 2006.182.07:48:48.93#ibcon#read 6, iclass 22, count 0 2006.182.07:48:48.93#ibcon#end of sib2, iclass 22, count 0 2006.182.07:48:48.93#ibcon#*after write, iclass 22, count 0 2006.182.07:48:48.93#ibcon#*before return 0, iclass 22, count 0 2006.182.07:48:48.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:48.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:48.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:48:48.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:48:48.93$vc4f8/va=4,7 2006.182.07:48:48.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.07:48:48.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.07:48:48.93#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:48.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:48.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:48.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:48.98#ibcon#enter wrdev, iclass 24, count 2 2006.182.07:48:48.98#ibcon#first serial, iclass 24, count 2 2006.182.07:48:48.98#ibcon#enter sib2, iclass 24, count 2 2006.182.07:48:48.98#ibcon#flushed, iclass 24, count 2 2006.182.07:48:48.98#ibcon#about to write, iclass 24, count 2 2006.182.07:48:48.98#ibcon#wrote, iclass 24, count 2 2006.182.07:48:48.98#ibcon#about to read 3, iclass 24, count 2 2006.182.07:48:49.00#ibcon#read 3, iclass 24, count 2 2006.182.07:48:49.00#ibcon#about to read 4, iclass 24, count 2 2006.182.07:48:49.00#ibcon#read 4, iclass 24, count 2 2006.182.07:48:49.00#ibcon#about to read 5, iclass 24, count 2 2006.182.07:48:49.00#ibcon#read 5, iclass 24, count 2 2006.182.07:48:49.00#ibcon#about to read 6, iclass 24, count 2 2006.182.07:48:49.00#ibcon#read 6, iclass 24, count 2 2006.182.07:48:49.00#ibcon#end of sib2, iclass 24, count 2 2006.182.07:48:49.00#ibcon#*mode == 0, iclass 24, count 2 2006.182.07:48:49.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.07:48:49.00#ibcon#[25=AT04-07\r\n] 2006.182.07:48:49.00#ibcon#*before write, iclass 24, count 2 2006.182.07:48:49.00#ibcon#enter sib2, iclass 24, count 2 2006.182.07:48:49.00#ibcon#flushed, iclass 24, count 2 2006.182.07:48:49.00#ibcon#about to write, iclass 24, count 2 2006.182.07:48:49.00#ibcon#wrote, iclass 24, count 2 2006.182.07:48:49.00#ibcon#about to read 3, iclass 24, count 2 2006.182.07:48:49.03#ibcon#read 3, iclass 24, count 2 2006.182.07:48:49.03#ibcon#about to read 4, iclass 24, count 2 2006.182.07:48:49.03#ibcon#read 4, iclass 24, count 2 2006.182.07:48:49.03#ibcon#about to read 5, iclass 24, count 2 2006.182.07:48:49.03#ibcon#read 5, iclass 24, count 2 2006.182.07:48:49.03#ibcon#about to read 6, iclass 24, count 2 2006.182.07:48:49.03#ibcon#read 6, iclass 24, count 2 2006.182.07:48:49.03#ibcon#end of sib2, iclass 24, count 2 2006.182.07:48:49.03#ibcon#*after write, iclass 24, count 2 2006.182.07:48:49.03#ibcon#*before return 0, iclass 24, count 2 2006.182.07:48:49.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:49.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:49.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.07:48:49.03#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:49.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:49.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:49.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:49.15#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:48:49.15#ibcon#first serial, iclass 24, count 0 2006.182.07:48:49.15#ibcon#enter sib2, iclass 24, count 0 2006.182.07:48:49.15#ibcon#flushed, iclass 24, count 0 2006.182.07:48:49.15#ibcon#about to write, iclass 24, count 0 2006.182.07:48:49.15#ibcon#wrote, iclass 24, count 0 2006.182.07:48:49.15#ibcon#about to read 3, iclass 24, count 0 2006.182.07:48:49.17#ibcon#read 3, iclass 24, count 0 2006.182.07:48:49.17#ibcon#about to read 4, iclass 24, count 0 2006.182.07:48:49.17#ibcon#read 4, iclass 24, count 0 2006.182.07:48:49.17#ibcon#about to read 5, iclass 24, count 0 2006.182.07:48:49.17#ibcon#read 5, iclass 24, count 0 2006.182.07:48:49.17#ibcon#about to read 6, iclass 24, count 0 2006.182.07:48:49.17#ibcon#read 6, iclass 24, count 0 2006.182.07:48:49.17#ibcon#end of sib2, iclass 24, count 0 2006.182.07:48:49.17#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:48:49.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:48:49.17#ibcon#[25=USB\r\n] 2006.182.07:48:49.17#ibcon#*before write, iclass 24, count 0 2006.182.07:48:49.17#ibcon#enter sib2, iclass 24, count 0 2006.182.07:48:49.17#ibcon#flushed, iclass 24, count 0 2006.182.07:48:49.17#ibcon#about to write, iclass 24, count 0 2006.182.07:48:49.17#ibcon#wrote, iclass 24, count 0 2006.182.07:48:49.17#ibcon#about to read 3, iclass 24, count 0 2006.182.07:48:49.20#ibcon#read 3, iclass 24, count 0 2006.182.07:48:49.20#ibcon#about to read 4, iclass 24, count 0 2006.182.07:48:49.20#ibcon#read 4, iclass 24, count 0 2006.182.07:48:49.20#ibcon#about to read 5, iclass 24, count 0 2006.182.07:48:49.20#ibcon#read 5, iclass 24, count 0 2006.182.07:48:49.20#ibcon#about to read 6, iclass 24, count 0 2006.182.07:48:49.20#ibcon#read 6, iclass 24, count 0 2006.182.07:48:49.20#ibcon#end of sib2, iclass 24, count 0 2006.182.07:48:49.20#ibcon#*after write, iclass 24, count 0 2006.182.07:48:49.20#ibcon#*before return 0, iclass 24, count 0 2006.182.07:48:49.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:49.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:49.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:48:49.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:48:49.20$vc4f8/valo=5,652.99 2006.182.07:48:49.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.07:48:49.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.07:48:49.20#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:49.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:49.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:49.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:49.20#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:48:49.20#ibcon#first serial, iclass 26, count 0 2006.182.07:48:49.20#ibcon#enter sib2, iclass 26, count 0 2006.182.07:48:49.20#ibcon#flushed, iclass 26, count 0 2006.182.07:48:49.20#ibcon#about to write, iclass 26, count 0 2006.182.07:48:49.20#ibcon#wrote, iclass 26, count 0 2006.182.07:48:49.20#ibcon#about to read 3, iclass 26, count 0 2006.182.07:48:49.22#ibcon#read 3, iclass 26, count 0 2006.182.07:48:49.22#ibcon#about to read 4, iclass 26, count 0 2006.182.07:48:49.22#ibcon#read 4, iclass 26, count 0 2006.182.07:48:49.22#ibcon#about to read 5, iclass 26, count 0 2006.182.07:48:49.22#ibcon#read 5, iclass 26, count 0 2006.182.07:48:49.22#ibcon#about to read 6, iclass 26, count 0 2006.182.07:48:49.22#ibcon#read 6, iclass 26, count 0 2006.182.07:48:49.22#ibcon#end of sib2, iclass 26, count 0 2006.182.07:48:49.22#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:48:49.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:48:49.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:48:49.22#ibcon#*before write, iclass 26, count 0 2006.182.07:48:49.22#ibcon#enter sib2, iclass 26, count 0 2006.182.07:48:49.22#ibcon#flushed, iclass 26, count 0 2006.182.07:48:49.22#ibcon#about to write, iclass 26, count 0 2006.182.07:48:49.22#ibcon#wrote, iclass 26, count 0 2006.182.07:48:49.22#ibcon#about to read 3, iclass 26, count 0 2006.182.07:48:49.26#ibcon#read 3, iclass 26, count 0 2006.182.07:48:49.26#ibcon#about to read 4, iclass 26, count 0 2006.182.07:48:49.26#ibcon#read 4, iclass 26, count 0 2006.182.07:48:49.26#ibcon#about to read 5, iclass 26, count 0 2006.182.07:48:49.26#ibcon#read 5, iclass 26, count 0 2006.182.07:48:49.26#ibcon#about to read 6, iclass 26, count 0 2006.182.07:48:49.26#ibcon#read 6, iclass 26, count 0 2006.182.07:48:49.26#ibcon#end of sib2, iclass 26, count 0 2006.182.07:48:49.26#ibcon#*after write, iclass 26, count 0 2006.182.07:48:49.26#ibcon#*before return 0, iclass 26, count 0 2006.182.07:48:49.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:49.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:49.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:48:49.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:48:49.26$vc4f8/va=5,7 2006.182.07:48:49.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.07:48:49.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.07:48:49.26#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:49.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:49.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:49.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:49.32#ibcon#enter wrdev, iclass 28, count 2 2006.182.07:48:49.32#ibcon#first serial, iclass 28, count 2 2006.182.07:48:49.32#ibcon#enter sib2, iclass 28, count 2 2006.182.07:48:49.32#ibcon#flushed, iclass 28, count 2 2006.182.07:48:49.32#ibcon#about to write, iclass 28, count 2 2006.182.07:48:49.32#ibcon#wrote, iclass 28, count 2 2006.182.07:48:49.32#ibcon#about to read 3, iclass 28, count 2 2006.182.07:48:49.34#ibcon#read 3, iclass 28, count 2 2006.182.07:48:49.34#ibcon#about to read 4, iclass 28, count 2 2006.182.07:48:49.34#ibcon#read 4, iclass 28, count 2 2006.182.07:48:49.34#ibcon#about to read 5, iclass 28, count 2 2006.182.07:48:49.34#ibcon#read 5, iclass 28, count 2 2006.182.07:48:49.34#ibcon#about to read 6, iclass 28, count 2 2006.182.07:48:49.34#ibcon#read 6, iclass 28, count 2 2006.182.07:48:49.34#ibcon#end of sib2, iclass 28, count 2 2006.182.07:48:49.34#ibcon#*mode == 0, iclass 28, count 2 2006.182.07:48:49.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.07:48:49.34#ibcon#[25=AT05-07\r\n] 2006.182.07:48:49.34#ibcon#*before write, iclass 28, count 2 2006.182.07:48:49.34#ibcon#enter sib2, iclass 28, count 2 2006.182.07:48:49.34#ibcon#flushed, iclass 28, count 2 2006.182.07:48:49.34#ibcon#about to write, iclass 28, count 2 2006.182.07:48:49.34#ibcon#wrote, iclass 28, count 2 2006.182.07:48:49.34#ibcon#about to read 3, iclass 28, count 2 2006.182.07:48:49.37#ibcon#read 3, iclass 28, count 2 2006.182.07:48:49.37#ibcon#about to read 4, iclass 28, count 2 2006.182.07:48:49.37#ibcon#read 4, iclass 28, count 2 2006.182.07:48:49.37#ibcon#about to read 5, iclass 28, count 2 2006.182.07:48:49.37#ibcon#read 5, iclass 28, count 2 2006.182.07:48:49.37#ibcon#about to read 6, iclass 28, count 2 2006.182.07:48:49.37#ibcon#read 6, iclass 28, count 2 2006.182.07:48:49.37#ibcon#end of sib2, iclass 28, count 2 2006.182.07:48:49.37#ibcon#*after write, iclass 28, count 2 2006.182.07:48:49.37#ibcon#*before return 0, iclass 28, count 2 2006.182.07:48:49.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:49.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:49.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.07:48:49.37#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:49.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:49.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:49.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:49.49#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:48:49.49#ibcon#first serial, iclass 28, count 0 2006.182.07:48:49.49#ibcon#enter sib2, iclass 28, count 0 2006.182.07:48:49.49#ibcon#flushed, iclass 28, count 0 2006.182.07:48:49.49#ibcon#about to write, iclass 28, count 0 2006.182.07:48:49.49#ibcon#wrote, iclass 28, count 0 2006.182.07:48:49.49#ibcon#about to read 3, iclass 28, count 0 2006.182.07:48:49.51#ibcon#read 3, iclass 28, count 0 2006.182.07:48:49.51#ibcon#about to read 4, iclass 28, count 0 2006.182.07:48:49.51#ibcon#read 4, iclass 28, count 0 2006.182.07:48:49.51#ibcon#about to read 5, iclass 28, count 0 2006.182.07:48:49.51#ibcon#read 5, iclass 28, count 0 2006.182.07:48:49.51#ibcon#about to read 6, iclass 28, count 0 2006.182.07:48:49.51#ibcon#read 6, iclass 28, count 0 2006.182.07:48:49.51#ibcon#end of sib2, iclass 28, count 0 2006.182.07:48:49.51#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:48:49.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:48:49.51#ibcon#[25=USB\r\n] 2006.182.07:48:49.51#ibcon#*before write, iclass 28, count 0 2006.182.07:48:49.51#ibcon#enter sib2, iclass 28, count 0 2006.182.07:48:49.51#ibcon#flushed, iclass 28, count 0 2006.182.07:48:49.51#ibcon#about to write, iclass 28, count 0 2006.182.07:48:49.51#ibcon#wrote, iclass 28, count 0 2006.182.07:48:49.51#ibcon#about to read 3, iclass 28, count 0 2006.182.07:48:49.54#ibcon#read 3, iclass 28, count 0 2006.182.07:48:49.54#ibcon#about to read 4, iclass 28, count 0 2006.182.07:48:49.54#ibcon#read 4, iclass 28, count 0 2006.182.07:48:49.54#ibcon#about to read 5, iclass 28, count 0 2006.182.07:48:49.54#ibcon#read 5, iclass 28, count 0 2006.182.07:48:49.54#ibcon#about to read 6, iclass 28, count 0 2006.182.07:48:49.54#ibcon#read 6, iclass 28, count 0 2006.182.07:48:49.54#ibcon#end of sib2, iclass 28, count 0 2006.182.07:48:49.54#ibcon#*after write, iclass 28, count 0 2006.182.07:48:49.54#ibcon#*before return 0, iclass 28, count 0 2006.182.07:48:49.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:49.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:49.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:48:49.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:48:49.54$vc4f8/valo=6,772.99 2006.182.07:48:49.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.07:48:49.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.07:48:49.54#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:49.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:49.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:49.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:49.54#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:48:49.54#ibcon#first serial, iclass 30, count 0 2006.182.07:48:49.54#ibcon#enter sib2, iclass 30, count 0 2006.182.07:48:49.54#ibcon#flushed, iclass 30, count 0 2006.182.07:48:49.54#ibcon#about to write, iclass 30, count 0 2006.182.07:48:49.54#ibcon#wrote, iclass 30, count 0 2006.182.07:48:49.54#ibcon#about to read 3, iclass 30, count 0 2006.182.07:48:49.56#ibcon#read 3, iclass 30, count 0 2006.182.07:48:49.56#ibcon#about to read 4, iclass 30, count 0 2006.182.07:48:49.56#ibcon#read 4, iclass 30, count 0 2006.182.07:48:49.56#ibcon#about to read 5, iclass 30, count 0 2006.182.07:48:49.56#ibcon#read 5, iclass 30, count 0 2006.182.07:48:49.56#ibcon#about to read 6, iclass 30, count 0 2006.182.07:48:49.56#ibcon#read 6, iclass 30, count 0 2006.182.07:48:49.56#ibcon#end of sib2, iclass 30, count 0 2006.182.07:48:49.56#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:48:49.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:48:49.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:48:49.56#ibcon#*before write, iclass 30, count 0 2006.182.07:48:49.56#ibcon#enter sib2, iclass 30, count 0 2006.182.07:48:49.56#ibcon#flushed, iclass 30, count 0 2006.182.07:48:49.56#ibcon#about to write, iclass 30, count 0 2006.182.07:48:49.56#ibcon#wrote, iclass 30, count 0 2006.182.07:48:49.56#ibcon#about to read 3, iclass 30, count 0 2006.182.07:48:49.60#ibcon#read 3, iclass 30, count 0 2006.182.07:48:49.60#ibcon#about to read 4, iclass 30, count 0 2006.182.07:48:49.60#ibcon#read 4, iclass 30, count 0 2006.182.07:48:49.60#ibcon#about to read 5, iclass 30, count 0 2006.182.07:48:49.60#ibcon#read 5, iclass 30, count 0 2006.182.07:48:49.60#ibcon#about to read 6, iclass 30, count 0 2006.182.07:48:49.60#ibcon#read 6, iclass 30, count 0 2006.182.07:48:49.60#ibcon#end of sib2, iclass 30, count 0 2006.182.07:48:49.60#ibcon#*after write, iclass 30, count 0 2006.182.07:48:49.60#ibcon#*before return 0, iclass 30, count 0 2006.182.07:48:49.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:49.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:49.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:48:49.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:48:49.60$vc4f8/va=6,6 2006.182.07:48:49.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.07:48:49.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.07:48:49.60#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:49.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:49.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:49.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:49.66#ibcon#enter wrdev, iclass 32, count 2 2006.182.07:48:49.66#ibcon#first serial, iclass 32, count 2 2006.182.07:48:49.66#ibcon#enter sib2, iclass 32, count 2 2006.182.07:48:49.66#ibcon#flushed, iclass 32, count 2 2006.182.07:48:49.66#ibcon#about to write, iclass 32, count 2 2006.182.07:48:49.66#ibcon#wrote, iclass 32, count 2 2006.182.07:48:49.66#ibcon#about to read 3, iclass 32, count 2 2006.182.07:48:49.68#ibcon#read 3, iclass 32, count 2 2006.182.07:48:49.68#ibcon#about to read 4, iclass 32, count 2 2006.182.07:48:49.68#ibcon#read 4, iclass 32, count 2 2006.182.07:48:49.68#ibcon#about to read 5, iclass 32, count 2 2006.182.07:48:49.68#ibcon#read 5, iclass 32, count 2 2006.182.07:48:49.68#ibcon#about to read 6, iclass 32, count 2 2006.182.07:48:49.68#ibcon#read 6, iclass 32, count 2 2006.182.07:48:49.68#ibcon#end of sib2, iclass 32, count 2 2006.182.07:48:49.68#ibcon#*mode == 0, iclass 32, count 2 2006.182.07:48:49.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.07:48:49.68#ibcon#[25=AT06-06\r\n] 2006.182.07:48:49.68#ibcon#*before write, iclass 32, count 2 2006.182.07:48:49.68#ibcon#enter sib2, iclass 32, count 2 2006.182.07:48:49.68#ibcon#flushed, iclass 32, count 2 2006.182.07:48:49.68#ibcon#about to write, iclass 32, count 2 2006.182.07:48:49.68#ibcon#wrote, iclass 32, count 2 2006.182.07:48:49.68#ibcon#about to read 3, iclass 32, count 2 2006.182.07:48:49.72#ibcon#read 3, iclass 32, count 2 2006.182.07:48:49.72#ibcon#about to read 4, iclass 32, count 2 2006.182.07:48:49.72#ibcon#read 4, iclass 32, count 2 2006.182.07:48:49.72#ibcon#about to read 5, iclass 32, count 2 2006.182.07:48:49.72#ibcon#read 5, iclass 32, count 2 2006.182.07:48:49.72#ibcon#about to read 6, iclass 32, count 2 2006.182.07:48:49.72#ibcon#read 6, iclass 32, count 2 2006.182.07:48:49.72#ibcon#end of sib2, iclass 32, count 2 2006.182.07:48:49.72#ibcon#*after write, iclass 32, count 2 2006.182.07:48:49.72#ibcon#*before return 0, iclass 32, count 2 2006.182.07:48:49.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:49.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:49.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.07:48:49.72#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:49.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:49.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:49.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:49.84#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:48:49.84#ibcon#first serial, iclass 32, count 0 2006.182.07:48:49.84#ibcon#enter sib2, iclass 32, count 0 2006.182.07:48:49.84#ibcon#flushed, iclass 32, count 0 2006.182.07:48:49.84#ibcon#about to write, iclass 32, count 0 2006.182.07:48:49.84#ibcon#wrote, iclass 32, count 0 2006.182.07:48:49.84#ibcon#about to read 3, iclass 32, count 0 2006.182.07:48:49.86#ibcon#read 3, iclass 32, count 0 2006.182.07:48:49.86#ibcon#about to read 4, iclass 32, count 0 2006.182.07:48:49.86#ibcon#read 4, iclass 32, count 0 2006.182.07:48:49.86#ibcon#about to read 5, iclass 32, count 0 2006.182.07:48:49.86#ibcon#read 5, iclass 32, count 0 2006.182.07:48:49.86#ibcon#about to read 6, iclass 32, count 0 2006.182.07:48:49.86#ibcon#read 6, iclass 32, count 0 2006.182.07:48:49.86#ibcon#end of sib2, iclass 32, count 0 2006.182.07:48:49.86#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:48:49.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:48:49.86#ibcon#[25=USB\r\n] 2006.182.07:48:49.86#ibcon#*before write, iclass 32, count 0 2006.182.07:48:49.86#ibcon#enter sib2, iclass 32, count 0 2006.182.07:48:49.86#ibcon#flushed, iclass 32, count 0 2006.182.07:48:49.86#ibcon#about to write, iclass 32, count 0 2006.182.07:48:49.86#ibcon#wrote, iclass 32, count 0 2006.182.07:48:49.86#ibcon#about to read 3, iclass 32, count 0 2006.182.07:48:49.89#ibcon#read 3, iclass 32, count 0 2006.182.07:48:49.89#ibcon#about to read 4, iclass 32, count 0 2006.182.07:48:49.89#ibcon#read 4, iclass 32, count 0 2006.182.07:48:49.89#ibcon#about to read 5, iclass 32, count 0 2006.182.07:48:49.89#ibcon#read 5, iclass 32, count 0 2006.182.07:48:49.89#ibcon#about to read 6, iclass 32, count 0 2006.182.07:48:49.89#ibcon#read 6, iclass 32, count 0 2006.182.07:48:49.89#ibcon#end of sib2, iclass 32, count 0 2006.182.07:48:49.89#ibcon#*after write, iclass 32, count 0 2006.182.07:48:49.89#ibcon#*before return 0, iclass 32, count 0 2006.182.07:48:49.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:49.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:49.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:48:49.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:48:49.89$vc4f8/valo=7,832.99 2006.182.07:48:49.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.07:48:49.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.07:48:49.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:49.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:49.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:49.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:49.89#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:48:49.89#ibcon#first serial, iclass 34, count 0 2006.182.07:48:49.89#ibcon#enter sib2, iclass 34, count 0 2006.182.07:48:49.89#ibcon#flushed, iclass 34, count 0 2006.182.07:48:49.89#ibcon#about to write, iclass 34, count 0 2006.182.07:48:49.89#ibcon#wrote, iclass 34, count 0 2006.182.07:48:49.89#ibcon#about to read 3, iclass 34, count 0 2006.182.07:48:49.91#ibcon#read 3, iclass 34, count 0 2006.182.07:48:49.91#ibcon#about to read 4, iclass 34, count 0 2006.182.07:48:49.91#ibcon#read 4, iclass 34, count 0 2006.182.07:48:49.91#ibcon#about to read 5, iclass 34, count 0 2006.182.07:48:49.91#ibcon#read 5, iclass 34, count 0 2006.182.07:48:49.91#ibcon#about to read 6, iclass 34, count 0 2006.182.07:48:49.91#ibcon#read 6, iclass 34, count 0 2006.182.07:48:49.91#ibcon#end of sib2, iclass 34, count 0 2006.182.07:48:49.91#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:48:49.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:48:49.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:48:49.91#ibcon#*before write, iclass 34, count 0 2006.182.07:48:49.91#ibcon#enter sib2, iclass 34, count 0 2006.182.07:48:49.91#ibcon#flushed, iclass 34, count 0 2006.182.07:48:49.91#ibcon#about to write, iclass 34, count 0 2006.182.07:48:49.91#ibcon#wrote, iclass 34, count 0 2006.182.07:48:49.91#ibcon#about to read 3, iclass 34, count 0 2006.182.07:48:49.95#ibcon#read 3, iclass 34, count 0 2006.182.07:48:49.95#ibcon#about to read 4, iclass 34, count 0 2006.182.07:48:49.95#ibcon#read 4, iclass 34, count 0 2006.182.07:48:49.95#ibcon#about to read 5, iclass 34, count 0 2006.182.07:48:49.95#ibcon#read 5, iclass 34, count 0 2006.182.07:48:49.95#ibcon#about to read 6, iclass 34, count 0 2006.182.07:48:49.95#ibcon#read 6, iclass 34, count 0 2006.182.07:48:49.95#ibcon#end of sib2, iclass 34, count 0 2006.182.07:48:49.95#ibcon#*after write, iclass 34, count 0 2006.182.07:48:49.95#ibcon#*before return 0, iclass 34, count 0 2006.182.07:48:49.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:49.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:49.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:48:49.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:48:49.95$vc4f8/va=7,6 2006.182.07:48:49.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.182.07:48:49.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.182.07:48:49.95#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:49.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:48:50.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:48:50.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:48:50.01#ibcon#enter wrdev, iclass 36, count 2 2006.182.07:48:50.01#ibcon#first serial, iclass 36, count 2 2006.182.07:48:50.01#ibcon#enter sib2, iclass 36, count 2 2006.182.07:48:50.01#ibcon#flushed, iclass 36, count 2 2006.182.07:48:50.01#ibcon#about to write, iclass 36, count 2 2006.182.07:48:50.01#ibcon#wrote, iclass 36, count 2 2006.182.07:48:50.01#ibcon#about to read 3, iclass 36, count 2 2006.182.07:48:50.03#ibcon#read 3, iclass 36, count 2 2006.182.07:48:50.03#ibcon#about to read 4, iclass 36, count 2 2006.182.07:48:50.03#ibcon#read 4, iclass 36, count 2 2006.182.07:48:50.03#ibcon#about to read 5, iclass 36, count 2 2006.182.07:48:50.03#ibcon#read 5, iclass 36, count 2 2006.182.07:48:50.03#ibcon#about to read 6, iclass 36, count 2 2006.182.07:48:50.03#ibcon#read 6, iclass 36, count 2 2006.182.07:48:50.03#ibcon#end of sib2, iclass 36, count 2 2006.182.07:48:50.03#ibcon#*mode == 0, iclass 36, count 2 2006.182.07:48:50.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.182.07:48:50.03#ibcon#[25=AT07-06\r\n] 2006.182.07:48:50.03#ibcon#*before write, iclass 36, count 2 2006.182.07:48:50.03#ibcon#enter sib2, iclass 36, count 2 2006.182.07:48:50.03#ibcon#flushed, iclass 36, count 2 2006.182.07:48:50.03#ibcon#about to write, iclass 36, count 2 2006.182.07:48:50.03#ibcon#wrote, iclass 36, count 2 2006.182.07:48:50.03#ibcon#about to read 3, iclass 36, count 2 2006.182.07:48:50.06#ibcon#read 3, iclass 36, count 2 2006.182.07:48:50.06#ibcon#about to read 4, iclass 36, count 2 2006.182.07:48:50.06#ibcon#read 4, iclass 36, count 2 2006.182.07:48:50.06#ibcon#about to read 5, iclass 36, count 2 2006.182.07:48:50.06#ibcon#read 5, iclass 36, count 2 2006.182.07:48:50.06#ibcon#about to read 6, iclass 36, count 2 2006.182.07:48:50.06#ibcon#read 6, iclass 36, count 2 2006.182.07:48:50.06#ibcon#end of sib2, iclass 36, count 2 2006.182.07:48:50.06#ibcon#*after write, iclass 36, count 2 2006.182.07:48:50.06#ibcon#*before return 0, iclass 36, count 2 2006.182.07:48:50.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:48:50.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:48:50.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.182.07:48:50.06#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:50.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:48:50.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:48:50.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:48:50.18#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:48:50.18#ibcon#first serial, iclass 36, count 0 2006.182.07:48:50.18#ibcon#enter sib2, iclass 36, count 0 2006.182.07:48:50.18#ibcon#flushed, iclass 36, count 0 2006.182.07:48:50.18#ibcon#about to write, iclass 36, count 0 2006.182.07:48:50.18#ibcon#wrote, iclass 36, count 0 2006.182.07:48:50.18#ibcon#about to read 3, iclass 36, count 0 2006.182.07:48:50.20#ibcon#read 3, iclass 36, count 0 2006.182.07:48:50.20#ibcon#about to read 4, iclass 36, count 0 2006.182.07:48:50.20#ibcon#read 4, iclass 36, count 0 2006.182.07:48:50.20#ibcon#about to read 5, iclass 36, count 0 2006.182.07:48:50.20#ibcon#read 5, iclass 36, count 0 2006.182.07:48:50.20#ibcon#about to read 6, iclass 36, count 0 2006.182.07:48:50.20#ibcon#read 6, iclass 36, count 0 2006.182.07:48:50.20#ibcon#end of sib2, iclass 36, count 0 2006.182.07:48:50.20#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:48:50.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:48:50.20#ibcon#[25=USB\r\n] 2006.182.07:48:50.20#ibcon#*before write, iclass 36, count 0 2006.182.07:48:50.20#ibcon#enter sib2, iclass 36, count 0 2006.182.07:48:50.20#ibcon#flushed, iclass 36, count 0 2006.182.07:48:50.20#ibcon#about to write, iclass 36, count 0 2006.182.07:48:50.20#ibcon#wrote, iclass 36, count 0 2006.182.07:48:50.20#ibcon#about to read 3, iclass 36, count 0 2006.182.07:48:50.23#ibcon#read 3, iclass 36, count 0 2006.182.07:48:50.23#ibcon#about to read 4, iclass 36, count 0 2006.182.07:48:50.23#ibcon#read 4, iclass 36, count 0 2006.182.07:48:50.23#ibcon#about to read 5, iclass 36, count 0 2006.182.07:48:50.23#ibcon#read 5, iclass 36, count 0 2006.182.07:48:50.23#ibcon#about to read 6, iclass 36, count 0 2006.182.07:48:50.23#ibcon#read 6, iclass 36, count 0 2006.182.07:48:50.23#ibcon#end of sib2, iclass 36, count 0 2006.182.07:48:50.23#ibcon#*after write, iclass 36, count 0 2006.182.07:48:50.23#ibcon#*before return 0, iclass 36, count 0 2006.182.07:48:50.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:48:50.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:48:50.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:48:50.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:48:50.23$vc4f8/valo=8,852.99 2006.182.07:48:50.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.07:48:50.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.07:48:50.23#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:50.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:48:50.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:48:50.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:48:50.23#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:48:50.23#ibcon#first serial, iclass 38, count 0 2006.182.07:48:50.23#ibcon#enter sib2, iclass 38, count 0 2006.182.07:48:50.23#ibcon#flushed, iclass 38, count 0 2006.182.07:48:50.23#ibcon#about to write, iclass 38, count 0 2006.182.07:48:50.23#ibcon#wrote, iclass 38, count 0 2006.182.07:48:50.23#ibcon#about to read 3, iclass 38, count 0 2006.182.07:48:50.25#ibcon#read 3, iclass 38, count 0 2006.182.07:48:50.25#ibcon#about to read 4, iclass 38, count 0 2006.182.07:48:50.25#ibcon#read 4, iclass 38, count 0 2006.182.07:48:50.25#ibcon#about to read 5, iclass 38, count 0 2006.182.07:48:50.25#ibcon#read 5, iclass 38, count 0 2006.182.07:48:50.25#ibcon#about to read 6, iclass 38, count 0 2006.182.07:48:50.25#ibcon#read 6, iclass 38, count 0 2006.182.07:48:50.25#ibcon#end of sib2, iclass 38, count 0 2006.182.07:48:50.25#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:48:50.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:48:50.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:48:50.25#ibcon#*before write, iclass 38, count 0 2006.182.07:48:50.25#ibcon#enter sib2, iclass 38, count 0 2006.182.07:48:50.25#ibcon#flushed, iclass 38, count 0 2006.182.07:48:50.25#ibcon#about to write, iclass 38, count 0 2006.182.07:48:50.25#ibcon#wrote, iclass 38, count 0 2006.182.07:48:50.25#ibcon#about to read 3, iclass 38, count 0 2006.182.07:48:50.29#ibcon#read 3, iclass 38, count 0 2006.182.07:48:50.29#ibcon#about to read 4, iclass 38, count 0 2006.182.07:48:50.29#ibcon#read 4, iclass 38, count 0 2006.182.07:48:50.29#ibcon#about to read 5, iclass 38, count 0 2006.182.07:48:50.29#ibcon#read 5, iclass 38, count 0 2006.182.07:48:50.29#ibcon#about to read 6, iclass 38, count 0 2006.182.07:48:50.29#ibcon#read 6, iclass 38, count 0 2006.182.07:48:50.29#ibcon#end of sib2, iclass 38, count 0 2006.182.07:48:50.29#ibcon#*after write, iclass 38, count 0 2006.182.07:48:50.29#ibcon#*before return 0, iclass 38, count 0 2006.182.07:48:50.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:48:50.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:48:50.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:48:50.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:48:50.29$vc4f8/va=8,7 2006.182.07:48:50.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.07:48:50.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.07:48:50.29#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:50.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:48:50.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:48:50.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:48:50.35#ibcon#enter wrdev, iclass 40, count 2 2006.182.07:48:50.35#ibcon#first serial, iclass 40, count 2 2006.182.07:48:50.35#ibcon#enter sib2, iclass 40, count 2 2006.182.07:48:50.35#ibcon#flushed, iclass 40, count 2 2006.182.07:48:50.35#ibcon#about to write, iclass 40, count 2 2006.182.07:48:50.35#ibcon#wrote, iclass 40, count 2 2006.182.07:48:50.35#ibcon#about to read 3, iclass 40, count 2 2006.182.07:48:50.37#ibcon#read 3, iclass 40, count 2 2006.182.07:48:50.37#ibcon#about to read 4, iclass 40, count 2 2006.182.07:48:50.37#ibcon#read 4, iclass 40, count 2 2006.182.07:48:50.37#ibcon#about to read 5, iclass 40, count 2 2006.182.07:48:50.37#ibcon#read 5, iclass 40, count 2 2006.182.07:48:50.37#ibcon#about to read 6, iclass 40, count 2 2006.182.07:48:50.37#ibcon#read 6, iclass 40, count 2 2006.182.07:48:50.37#ibcon#end of sib2, iclass 40, count 2 2006.182.07:48:50.37#ibcon#*mode == 0, iclass 40, count 2 2006.182.07:48:50.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.07:48:50.37#ibcon#[25=AT08-07\r\n] 2006.182.07:48:50.37#ibcon#*before write, iclass 40, count 2 2006.182.07:48:50.37#ibcon#enter sib2, iclass 40, count 2 2006.182.07:48:50.37#ibcon#flushed, iclass 40, count 2 2006.182.07:48:50.37#ibcon#about to write, iclass 40, count 2 2006.182.07:48:50.37#ibcon#wrote, iclass 40, count 2 2006.182.07:48:50.37#ibcon#about to read 3, iclass 40, count 2 2006.182.07:48:50.40#ibcon#read 3, iclass 40, count 2 2006.182.07:48:50.40#ibcon#about to read 4, iclass 40, count 2 2006.182.07:48:50.40#ibcon#read 4, iclass 40, count 2 2006.182.07:48:50.40#ibcon#about to read 5, iclass 40, count 2 2006.182.07:48:50.40#ibcon#read 5, iclass 40, count 2 2006.182.07:48:50.40#ibcon#about to read 6, iclass 40, count 2 2006.182.07:48:50.40#ibcon#read 6, iclass 40, count 2 2006.182.07:48:50.40#ibcon#end of sib2, iclass 40, count 2 2006.182.07:48:50.40#ibcon#*after write, iclass 40, count 2 2006.182.07:48:50.40#ibcon#*before return 0, iclass 40, count 2 2006.182.07:48:50.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:48:50.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:48:50.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.07:48:50.40#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:50.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:48:50.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:48:50.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:48:50.52#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:48:50.52#ibcon#first serial, iclass 40, count 0 2006.182.07:48:50.52#ibcon#enter sib2, iclass 40, count 0 2006.182.07:48:50.52#ibcon#flushed, iclass 40, count 0 2006.182.07:48:50.52#ibcon#about to write, iclass 40, count 0 2006.182.07:48:50.52#ibcon#wrote, iclass 40, count 0 2006.182.07:48:50.52#ibcon#about to read 3, iclass 40, count 0 2006.182.07:48:50.54#ibcon#read 3, iclass 40, count 0 2006.182.07:48:50.54#ibcon#about to read 4, iclass 40, count 0 2006.182.07:48:50.54#ibcon#read 4, iclass 40, count 0 2006.182.07:48:50.54#ibcon#about to read 5, iclass 40, count 0 2006.182.07:48:50.54#ibcon#read 5, iclass 40, count 0 2006.182.07:48:50.54#ibcon#about to read 6, iclass 40, count 0 2006.182.07:48:50.54#ibcon#read 6, iclass 40, count 0 2006.182.07:48:50.54#ibcon#end of sib2, iclass 40, count 0 2006.182.07:48:50.54#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:48:50.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:48:50.54#ibcon#[25=USB\r\n] 2006.182.07:48:50.54#ibcon#*before write, iclass 40, count 0 2006.182.07:48:50.54#ibcon#enter sib2, iclass 40, count 0 2006.182.07:48:50.54#ibcon#flushed, iclass 40, count 0 2006.182.07:48:50.54#ibcon#about to write, iclass 40, count 0 2006.182.07:48:50.54#ibcon#wrote, iclass 40, count 0 2006.182.07:48:50.54#ibcon#about to read 3, iclass 40, count 0 2006.182.07:48:50.57#ibcon#read 3, iclass 40, count 0 2006.182.07:48:50.57#ibcon#about to read 4, iclass 40, count 0 2006.182.07:48:50.57#ibcon#read 4, iclass 40, count 0 2006.182.07:48:50.57#ibcon#about to read 5, iclass 40, count 0 2006.182.07:48:50.57#ibcon#read 5, iclass 40, count 0 2006.182.07:48:50.57#ibcon#about to read 6, iclass 40, count 0 2006.182.07:48:50.57#ibcon#read 6, iclass 40, count 0 2006.182.07:48:50.57#ibcon#end of sib2, iclass 40, count 0 2006.182.07:48:50.57#ibcon#*after write, iclass 40, count 0 2006.182.07:48:50.57#ibcon#*before return 0, iclass 40, count 0 2006.182.07:48:50.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:48:50.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:48:50.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:48:50.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:48:50.57$vc4f8/vblo=1,632.99 2006.182.07:48:50.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.07:48:50.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.07:48:50.57#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:50.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:48:50.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:48:50.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:48:50.57#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:48:50.57#ibcon#first serial, iclass 4, count 0 2006.182.07:48:50.57#ibcon#enter sib2, iclass 4, count 0 2006.182.07:48:50.57#ibcon#flushed, iclass 4, count 0 2006.182.07:48:50.57#ibcon#about to write, iclass 4, count 0 2006.182.07:48:50.57#ibcon#wrote, iclass 4, count 0 2006.182.07:48:50.57#ibcon#about to read 3, iclass 4, count 0 2006.182.07:48:50.59#ibcon#read 3, iclass 4, count 0 2006.182.07:48:50.59#ibcon#about to read 4, iclass 4, count 0 2006.182.07:48:50.59#ibcon#read 4, iclass 4, count 0 2006.182.07:48:50.59#ibcon#about to read 5, iclass 4, count 0 2006.182.07:48:50.59#ibcon#read 5, iclass 4, count 0 2006.182.07:48:50.59#ibcon#about to read 6, iclass 4, count 0 2006.182.07:48:50.59#ibcon#read 6, iclass 4, count 0 2006.182.07:48:50.59#ibcon#end of sib2, iclass 4, count 0 2006.182.07:48:50.59#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:48:50.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:48:50.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:48:50.59#ibcon#*before write, iclass 4, count 0 2006.182.07:48:50.59#ibcon#enter sib2, iclass 4, count 0 2006.182.07:48:50.59#ibcon#flushed, iclass 4, count 0 2006.182.07:48:50.59#ibcon#about to write, iclass 4, count 0 2006.182.07:48:50.59#ibcon#wrote, iclass 4, count 0 2006.182.07:48:50.59#ibcon#about to read 3, iclass 4, count 0 2006.182.07:48:50.64#ibcon#read 3, iclass 4, count 0 2006.182.07:48:50.64#ibcon#about to read 4, iclass 4, count 0 2006.182.07:48:50.64#ibcon#read 4, iclass 4, count 0 2006.182.07:48:50.64#ibcon#about to read 5, iclass 4, count 0 2006.182.07:48:50.64#ibcon#read 5, iclass 4, count 0 2006.182.07:48:50.64#ibcon#about to read 6, iclass 4, count 0 2006.182.07:48:50.64#ibcon#read 6, iclass 4, count 0 2006.182.07:48:50.64#ibcon#end of sib2, iclass 4, count 0 2006.182.07:48:50.64#ibcon#*after write, iclass 4, count 0 2006.182.07:48:50.64#ibcon#*before return 0, iclass 4, count 0 2006.182.07:48:50.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:48:50.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:48:50.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:48:50.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:48:50.64$vc4f8/vb=1,4 2006.182.07:48:50.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.07:48:50.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.07:48:50.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:50.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:48:50.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:48:50.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:48:50.64#ibcon#enter wrdev, iclass 6, count 2 2006.182.07:48:50.64#ibcon#first serial, iclass 6, count 2 2006.182.07:48:50.64#ibcon#enter sib2, iclass 6, count 2 2006.182.07:48:50.64#ibcon#flushed, iclass 6, count 2 2006.182.07:48:50.64#ibcon#about to write, iclass 6, count 2 2006.182.07:48:50.64#ibcon#wrote, iclass 6, count 2 2006.182.07:48:50.64#ibcon#about to read 3, iclass 6, count 2 2006.182.07:48:50.66#ibcon#read 3, iclass 6, count 2 2006.182.07:48:50.66#ibcon#about to read 4, iclass 6, count 2 2006.182.07:48:50.66#ibcon#read 4, iclass 6, count 2 2006.182.07:48:50.66#ibcon#about to read 5, iclass 6, count 2 2006.182.07:48:50.66#ibcon#read 5, iclass 6, count 2 2006.182.07:48:50.66#ibcon#about to read 6, iclass 6, count 2 2006.182.07:48:50.66#ibcon#read 6, iclass 6, count 2 2006.182.07:48:50.66#ibcon#end of sib2, iclass 6, count 2 2006.182.07:48:50.66#ibcon#*mode == 0, iclass 6, count 2 2006.182.07:48:50.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.07:48:50.66#ibcon#[27=AT01-04\r\n] 2006.182.07:48:50.66#ibcon#*before write, iclass 6, count 2 2006.182.07:48:50.66#ibcon#enter sib2, iclass 6, count 2 2006.182.07:48:50.66#ibcon#flushed, iclass 6, count 2 2006.182.07:48:50.66#ibcon#about to write, iclass 6, count 2 2006.182.07:48:50.66#ibcon#wrote, iclass 6, count 2 2006.182.07:48:50.66#ibcon#about to read 3, iclass 6, count 2 2006.182.07:48:50.69#ibcon#read 3, iclass 6, count 2 2006.182.07:48:50.69#ibcon#about to read 4, iclass 6, count 2 2006.182.07:48:50.69#ibcon#read 4, iclass 6, count 2 2006.182.07:48:50.69#ibcon#about to read 5, iclass 6, count 2 2006.182.07:48:50.69#ibcon#read 5, iclass 6, count 2 2006.182.07:48:50.69#ibcon#about to read 6, iclass 6, count 2 2006.182.07:48:50.69#ibcon#read 6, iclass 6, count 2 2006.182.07:48:50.69#ibcon#end of sib2, iclass 6, count 2 2006.182.07:48:50.69#ibcon#*after write, iclass 6, count 2 2006.182.07:48:50.69#ibcon#*before return 0, iclass 6, count 2 2006.182.07:48:50.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:48:50.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:48:50.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.07:48:50.69#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:50.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:48:50.79#abcon#<5=/07 0.7 1.9 27.61 801002.8\r\n> 2006.182.07:48:50.81#abcon#{5=INTERFACE CLEAR} 2006.182.07:48:50.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:48:50.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:48:50.81#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:48:50.81#ibcon#first serial, iclass 6, count 0 2006.182.07:48:50.81#ibcon#enter sib2, iclass 6, count 0 2006.182.07:48:50.81#ibcon#flushed, iclass 6, count 0 2006.182.07:48:50.81#ibcon#about to write, iclass 6, count 0 2006.182.07:48:50.81#ibcon#wrote, iclass 6, count 0 2006.182.07:48:50.81#ibcon#about to read 3, iclass 6, count 0 2006.182.07:48:50.83#ibcon#read 3, iclass 6, count 0 2006.182.07:48:50.83#ibcon#about to read 4, iclass 6, count 0 2006.182.07:48:50.83#ibcon#read 4, iclass 6, count 0 2006.182.07:48:50.83#ibcon#about to read 5, iclass 6, count 0 2006.182.07:48:50.83#ibcon#read 5, iclass 6, count 0 2006.182.07:48:50.83#ibcon#about to read 6, iclass 6, count 0 2006.182.07:48:50.83#ibcon#read 6, iclass 6, count 0 2006.182.07:48:50.83#ibcon#end of sib2, iclass 6, count 0 2006.182.07:48:50.83#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:48:50.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:48:50.83#ibcon#[27=USB\r\n] 2006.182.07:48:50.83#ibcon#*before write, iclass 6, count 0 2006.182.07:48:50.83#ibcon#enter sib2, iclass 6, count 0 2006.182.07:48:50.83#ibcon#flushed, iclass 6, count 0 2006.182.07:48:50.83#ibcon#about to write, iclass 6, count 0 2006.182.07:48:50.83#ibcon#wrote, iclass 6, count 0 2006.182.07:48:50.83#ibcon#about to read 3, iclass 6, count 0 2006.182.07:48:50.86#ibcon#read 3, iclass 6, count 0 2006.182.07:48:50.86#ibcon#about to read 4, iclass 6, count 0 2006.182.07:48:50.86#ibcon#read 4, iclass 6, count 0 2006.182.07:48:50.86#ibcon#about to read 5, iclass 6, count 0 2006.182.07:48:50.86#ibcon#read 5, iclass 6, count 0 2006.182.07:48:50.86#ibcon#about to read 6, iclass 6, count 0 2006.182.07:48:50.86#ibcon#read 6, iclass 6, count 0 2006.182.07:48:50.86#ibcon#end of sib2, iclass 6, count 0 2006.182.07:48:50.86#ibcon#*after write, iclass 6, count 0 2006.182.07:48:50.86#ibcon#*before return 0, iclass 6, count 0 2006.182.07:48:50.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:48:50.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:48:50.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:48:50.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:48:50.86$vc4f8/vblo=2,640.99 2006.182.07:48:50.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.07:48:50.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.07:48:50.86#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:50.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:50.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:50.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:50.86#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:48:50.86#ibcon#first serial, iclass 14, count 0 2006.182.07:48:50.86#ibcon#enter sib2, iclass 14, count 0 2006.182.07:48:50.86#ibcon#flushed, iclass 14, count 0 2006.182.07:48:50.86#ibcon#about to write, iclass 14, count 0 2006.182.07:48:50.86#ibcon#wrote, iclass 14, count 0 2006.182.07:48:50.86#ibcon#about to read 3, iclass 14, count 0 2006.182.07:48:50.87#abcon#[5=S1D000X0/0*\r\n] 2006.182.07:48:50.88#ibcon#read 3, iclass 14, count 0 2006.182.07:48:50.88#ibcon#about to read 4, iclass 14, count 0 2006.182.07:48:50.88#ibcon#read 4, iclass 14, count 0 2006.182.07:48:50.88#ibcon#about to read 5, iclass 14, count 0 2006.182.07:48:50.88#ibcon#read 5, iclass 14, count 0 2006.182.07:48:50.88#ibcon#about to read 6, iclass 14, count 0 2006.182.07:48:50.88#ibcon#read 6, iclass 14, count 0 2006.182.07:48:50.88#ibcon#end of sib2, iclass 14, count 0 2006.182.07:48:50.88#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:48:50.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:48:50.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:48:50.88#ibcon#*before write, iclass 14, count 0 2006.182.07:48:50.88#ibcon#enter sib2, iclass 14, count 0 2006.182.07:48:50.88#ibcon#flushed, iclass 14, count 0 2006.182.07:48:50.88#ibcon#about to write, iclass 14, count 0 2006.182.07:48:50.88#ibcon#wrote, iclass 14, count 0 2006.182.07:48:50.88#ibcon#about to read 3, iclass 14, count 0 2006.182.07:48:50.92#ibcon#read 3, iclass 14, count 0 2006.182.07:48:50.92#ibcon#about to read 4, iclass 14, count 0 2006.182.07:48:50.92#ibcon#read 4, iclass 14, count 0 2006.182.07:48:50.92#ibcon#about to read 5, iclass 14, count 0 2006.182.07:48:50.92#ibcon#read 5, iclass 14, count 0 2006.182.07:48:50.92#ibcon#about to read 6, iclass 14, count 0 2006.182.07:48:50.92#ibcon#read 6, iclass 14, count 0 2006.182.07:48:50.92#ibcon#end of sib2, iclass 14, count 0 2006.182.07:48:50.92#ibcon#*after write, iclass 14, count 0 2006.182.07:48:50.92#ibcon#*before return 0, iclass 14, count 0 2006.182.07:48:50.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:50.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:48:50.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:48:50.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:48:50.92$vc4f8/vb=2,4 2006.182.07:48:50.92#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.07:48:50.92#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.07:48:50.92#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:50.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:50.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:50.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:50.98#ibcon#enter wrdev, iclass 16, count 2 2006.182.07:48:50.98#ibcon#first serial, iclass 16, count 2 2006.182.07:48:50.98#ibcon#enter sib2, iclass 16, count 2 2006.182.07:48:50.98#ibcon#flushed, iclass 16, count 2 2006.182.07:48:50.98#ibcon#about to write, iclass 16, count 2 2006.182.07:48:50.98#ibcon#wrote, iclass 16, count 2 2006.182.07:48:50.98#ibcon#about to read 3, iclass 16, count 2 2006.182.07:48:51.00#ibcon#read 3, iclass 16, count 2 2006.182.07:48:51.00#ibcon#about to read 4, iclass 16, count 2 2006.182.07:48:51.00#ibcon#read 4, iclass 16, count 2 2006.182.07:48:51.00#ibcon#about to read 5, iclass 16, count 2 2006.182.07:48:51.00#ibcon#read 5, iclass 16, count 2 2006.182.07:48:51.00#ibcon#about to read 6, iclass 16, count 2 2006.182.07:48:51.00#ibcon#read 6, iclass 16, count 2 2006.182.07:48:51.00#ibcon#end of sib2, iclass 16, count 2 2006.182.07:48:51.00#ibcon#*mode == 0, iclass 16, count 2 2006.182.07:48:51.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.07:48:51.00#ibcon#[27=AT02-04\r\n] 2006.182.07:48:51.00#ibcon#*before write, iclass 16, count 2 2006.182.07:48:51.00#ibcon#enter sib2, iclass 16, count 2 2006.182.07:48:51.00#ibcon#flushed, iclass 16, count 2 2006.182.07:48:51.00#ibcon#about to write, iclass 16, count 2 2006.182.07:48:51.00#ibcon#wrote, iclass 16, count 2 2006.182.07:48:51.00#ibcon#about to read 3, iclass 16, count 2 2006.182.07:48:51.03#ibcon#read 3, iclass 16, count 2 2006.182.07:48:51.03#ibcon#about to read 4, iclass 16, count 2 2006.182.07:48:51.03#ibcon#read 4, iclass 16, count 2 2006.182.07:48:51.03#ibcon#about to read 5, iclass 16, count 2 2006.182.07:48:51.03#ibcon#read 5, iclass 16, count 2 2006.182.07:48:51.03#ibcon#about to read 6, iclass 16, count 2 2006.182.07:48:51.03#ibcon#read 6, iclass 16, count 2 2006.182.07:48:51.03#ibcon#end of sib2, iclass 16, count 2 2006.182.07:48:51.03#ibcon#*after write, iclass 16, count 2 2006.182.07:48:51.03#ibcon#*before return 0, iclass 16, count 2 2006.182.07:48:51.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:51.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:48:51.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.07:48:51.03#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:51.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:51.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:51.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:51.15#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:48:51.15#ibcon#first serial, iclass 16, count 0 2006.182.07:48:51.15#ibcon#enter sib2, iclass 16, count 0 2006.182.07:48:51.15#ibcon#flushed, iclass 16, count 0 2006.182.07:48:51.15#ibcon#about to write, iclass 16, count 0 2006.182.07:48:51.15#ibcon#wrote, iclass 16, count 0 2006.182.07:48:51.15#ibcon#about to read 3, iclass 16, count 0 2006.182.07:48:51.17#ibcon#read 3, iclass 16, count 0 2006.182.07:48:51.17#ibcon#about to read 4, iclass 16, count 0 2006.182.07:48:51.17#ibcon#read 4, iclass 16, count 0 2006.182.07:48:51.17#ibcon#about to read 5, iclass 16, count 0 2006.182.07:48:51.17#ibcon#read 5, iclass 16, count 0 2006.182.07:48:51.17#ibcon#about to read 6, iclass 16, count 0 2006.182.07:48:51.17#ibcon#read 6, iclass 16, count 0 2006.182.07:48:51.17#ibcon#end of sib2, iclass 16, count 0 2006.182.07:48:51.17#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:48:51.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:48:51.17#ibcon#[27=USB\r\n] 2006.182.07:48:51.17#ibcon#*before write, iclass 16, count 0 2006.182.07:48:51.17#ibcon#enter sib2, iclass 16, count 0 2006.182.07:48:51.17#ibcon#flushed, iclass 16, count 0 2006.182.07:48:51.17#ibcon#about to write, iclass 16, count 0 2006.182.07:48:51.17#ibcon#wrote, iclass 16, count 0 2006.182.07:48:51.17#ibcon#about to read 3, iclass 16, count 0 2006.182.07:48:51.20#ibcon#read 3, iclass 16, count 0 2006.182.07:48:51.20#ibcon#about to read 4, iclass 16, count 0 2006.182.07:48:51.20#ibcon#read 4, iclass 16, count 0 2006.182.07:48:51.20#ibcon#about to read 5, iclass 16, count 0 2006.182.07:48:51.20#ibcon#read 5, iclass 16, count 0 2006.182.07:48:51.20#ibcon#about to read 6, iclass 16, count 0 2006.182.07:48:51.20#ibcon#read 6, iclass 16, count 0 2006.182.07:48:51.20#ibcon#end of sib2, iclass 16, count 0 2006.182.07:48:51.20#ibcon#*after write, iclass 16, count 0 2006.182.07:48:51.20#ibcon#*before return 0, iclass 16, count 0 2006.182.07:48:51.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:51.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:48:51.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:48:51.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:48:51.20$vc4f8/vblo=3,656.99 2006.182.07:48:51.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.07:48:51.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.07:48:51.20#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:51.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:51.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:51.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:51.20#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:48:51.20#ibcon#first serial, iclass 18, count 0 2006.182.07:48:51.20#ibcon#enter sib2, iclass 18, count 0 2006.182.07:48:51.20#ibcon#flushed, iclass 18, count 0 2006.182.07:48:51.20#ibcon#about to write, iclass 18, count 0 2006.182.07:48:51.20#ibcon#wrote, iclass 18, count 0 2006.182.07:48:51.20#ibcon#about to read 3, iclass 18, count 0 2006.182.07:48:51.22#ibcon#read 3, iclass 18, count 0 2006.182.07:48:51.22#ibcon#about to read 4, iclass 18, count 0 2006.182.07:48:51.22#ibcon#read 4, iclass 18, count 0 2006.182.07:48:51.22#ibcon#about to read 5, iclass 18, count 0 2006.182.07:48:51.22#ibcon#read 5, iclass 18, count 0 2006.182.07:48:51.22#ibcon#about to read 6, iclass 18, count 0 2006.182.07:48:51.22#ibcon#read 6, iclass 18, count 0 2006.182.07:48:51.22#ibcon#end of sib2, iclass 18, count 0 2006.182.07:48:51.22#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:48:51.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:48:51.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:48:51.22#ibcon#*before write, iclass 18, count 0 2006.182.07:48:51.22#ibcon#enter sib2, iclass 18, count 0 2006.182.07:48:51.22#ibcon#flushed, iclass 18, count 0 2006.182.07:48:51.22#ibcon#about to write, iclass 18, count 0 2006.182.07:48:51.22#ibcon#wrote, iclass 18, count 0 2006.182.07:48:51.22#ibcon#about to read 3, iclass 18, count 0 2006.182.07:48:51.26#ibcon#read 3, iclass 18, count 0 2006.182.07:48:51.26#ibcon#about to read 4, iclass 18, count 0 2006.182.07:48:51.26#ibcon#read 4, iclass 18, count 0 2006.182.07:48:51.26#ibcon#about to read 5, iclass 18, count 0 2006.182.07:48:51.26#ibcon#read 5, iclass 18, count 0 2006.182.07:48:51.26#ibcon#about to read 6, iclass 18, count 0 2006.182.07:48:51.26#ibcon#read 6, iclass 18, count 0 2006.182.07:48:51.26#ibcon#end of sib2, iclass 18, count 0 2006.182.07:48:51.26#ibcon#*after write, iclass 18, count 0 2006.182.07:48:51.26#ibcon#*before return 0, iclass 18, count 0 2006.182.07:48:51.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:51.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:48:51.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:48:51.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:48:51.26$vc4f8/vb=3,4 2006.182.07:48:51.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.07:48:51.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.07:48:51.26#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:51.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:51.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:51.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:51.32#ibcon#enter wrdev, iclass 20, count 2 2006.182.07:48:51.32#ibcon#first serial, iclass 20, count 2 2006.182.07:48:51.32#ibcon#enter sib2, iclass 20, count 2 2006.182.07:48:51.32#ibcon#flushed, iclass 20, count 2 2006.182.07:48:51.32#ibcon#about to write, iclass 20, count 2 2006.182.07:48:51.32#ibcon#wrote, iclass 20, count 2 2006.182.07:48:51.32#ibcon#about to read 3, iclass 20, count 2 2006.182.07:48:51.34#ibcon#read 3, iclass 20, count 2 2006.182.07:48:51.34#ibcon#about to read 4, iclass 20, count 2 2006.182.07:48:51.34#ibcon#read 4, iclass 20, count 2 2006.182.07:48:51.34#ibcon#about to read 5, iclass 20, count 2 2006.182.07:48:51.34#ibcon#read 5, iclass 20, count 2 2006.182.07:48:51.34#ibcon#about to read 6, iclass 20, count 2 2006.182.07:48:51.34#ibcon#read 6, iclass 20, count 2 2006.182.07:48:51.34#ibcon#end of sib2, iclass 20, count 2 2006.182.07:48:51.34#ibcon#*mode == 0, iclass 20, count 2 2006.182.07:48:51.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.07:48:51.34#ibcon#[27=AT03-04\r\n] 2006.182.07:48:51.34#ibcon#*before write, iclass 20, count 2 2006.182.07:48:51.34#ibcon#enter sib2, iclass 20, count 2 2006.182.07:48:51.34#ibcon#flushed, iclass 20, count 2 2006.182.07:48:51.34#ibcon#about to write, iclass 20, count 2 2006.182.07:48:51.34#ibcon#wrote, iclass 20, count 2 2006.182.07:48:51.34#ibcon#about to read 3, iclass 20, count 2 2006.182.07:48:51.37#ibcon#read 3, iclass 20, count 2 2006.182.07:48:51.37#ibcon#about to read 4, iclass 20, count 2 2006.182.07:48:51.37#ibcon#read 4, iclass 20, count 2 2006.182.07:48:51.37#ibcon#about to read 5, iclass 20, count 2 2006.182.07:48:51.37#ibcon#read 5, iclass 20, count 2 2006.182.07:48:51.37#ibcon#about to read 6, iclass 20, count 2 2006.182.07:48:51.37#ibcon#read 6, iclass 20, count 2 2006.182.07:48:51.37#ibcon#end of sib2, iclass 20, count 2 2006.182.07:48:51.37#ibcon#*after write, iclass 20, count 2 2006.182.07:48:51.37#ibcon#*before return 0, iclass 20, count 2 2006.182.07:48:51.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:51.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:48:51.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.07:48:51.37#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:51.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:51.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:51.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:51.49#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:48:51.49#ibcon#first serial, iclass 20, count 0 2006.182.07:48:51.49#ibcon#enter sib2, iclass 20, count 0 2006.182.07:48:51.49#ibcon#flushed, iclass 20, count 0 2006.182.07:48:51.49#ibcon#about to write, iclass 20, count 0 2006.182.07:48:51.49#ibcon#wrote, iclass 20, count 0 2006.182.07:48:51.49#ibcon#about to read 3, iclass 20, count 0 2006.182.07:48:51.51#ibcon#read 3, iclass 20, count 0 2006.182.07:48:51.51#ibcon#about to read 4, iclass 20, count 0 2006.182.07:48:51.51#ibcon#read 4, iclass 20, count 0 2006.182.07:48:51.51#ibcon#about to read 5, iclass 20, count 0 2006.182.07:48:51.51#ibcon#read 5, iclass 20, count 0 2006.182.07:48:51.51#ibcon#about to read 6, iclass 20, count 0 2006.182.07:48:51.51#ibcon#read 6, iclass 20, count 0 2006.182.07:48:51.51#ibcon#end of sib2, iclass 20, count 0 2006.182.07:48:51.51#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:48:51.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:48:51.51#ibcon#[27=USB\r\n] 2006.182.07:48:51.51#ibcon#*before write, iclass 20, count 0 2006.182.07:48:51.51#ibcon#enter sib2, iclass 20, count 0 2006.182.07:48:51.51#ibcon#flushed, iclass 20, count 0 2006.182.07:48:51.51#ibcon#about to write, iclass 20, count 0 2006.182.07:48:51.51#ibcon#wrote, iclass 20, count 0 2006.182.07:48:51.51#ibcon#about to read 3, iclass 20, count 0 2006.182.07:48:51.54#ibcon#read 3, iclass 20, count 0 2006.182.07:48:51.54#ibcon#about to read 4, iclass 20, count 0 2006.182.07:48:51.54#ibcon#read 4, iclass 20, count 0 2006.182.07:48:51.54#ibcon#about to read 5, iclass 20, count 0 2006.182.07:48:51.54#ibcon#read 5, iclass 20, count 0 2006.182.07:48:51.54#ibcon#about to read 6, iclass 20, count 0 2006.182.07:48:51.54#ibcon#read 6, iclass 20, count 0 2006.182.07:48:51.54#ibcon#end of sib2, iclass 20, count 0 2006.182.07:48:51.54#ibcon#*after write, iclass 20, count 0 2006.182.07:48:51.54#ibcon#*before return 0, iclass 20, count 0 2006.182.07:48:51.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:51.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:48:51.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:48:51.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:48:51.54$vc4f8/vblo=4,712.99 2006.182.07:48:51.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.07:48:51.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.07:48:51.54#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:51.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:51.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:51.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:51.54#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:48:51.54#ibcon#first serial, iclass 22, count 0 2006.182.07:48:51.54#ibcon#enter sib2, iclass 22, count 0 2006.182.07:48:51.54#ibcon#flushed, iclass 22, count 0 2006.182.07:48:51.54#ibcon#about to write, iclass 22, count 0 2006.182.07:48:51.54#ibcon#wrote, iclass 22, count 0 2006.182.07:48:51.54#ibcon#about to read 3, iclass 22, count 0 2006.182.07:48:51.56#ibcon#read 3, iclass 22, count 0 2006.182.07:48:51.56#ibcon#about to read 4, iclass 22, count 0 2006.182.07:48:51.56#ibcon#read 4, iclass 22, count 0 2006.182.07:48:51.56#ibcon#about to read 5, iclass 22, count 0 2006.182.07:48:51.56#ibcon#read 5, iclass 22, count 0 2006.182.07:48:51.56#ibcon#about to read 6, iclass 22, count 0 2006.182.07:48:51.56#ibcon#read 6, iclass 22, count 0 2006.182.07:48:51.56#ibcon#end of sib2, iclass 22, count 0 2006.182.07:48:51.56#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:48:51.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:48:51.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:48:51.56#ibcon#*before write, iclass 22, count 0 2006.182.07:48:51.56#ibcon#enter sib2, iclass 22, count 0 2006.182.07:48:51.56#ibcon#flushed, iclass 22, count 0 2006.182.07:48:51.56#ibcon#about to write, iclass 22, count 0 2006.182.07:48:51.56#ibcon#wrote, iclass 22, count 0 2006.182.07:48:51.56#ibcon#about to read 3, iclass 22, count 0 2006.182.07:48:51.60#ibcon#read 3, iclass 22, count 0 2006.182.07:48:51.60#ibcon#about to read 4, iclass 22, count 0 2006.182.07:48:51.60#ibcon#read 4, iclass 22, count 0 2006.182.07:48:51.60#ibcon#about to read 5, iclass 22, count 0 2006.182.07:48:51.60#ibcon#read 5, iclass 22, count 0 2006.182.07:48:51.60#ibcon#about to read 6, iclass 22, count 0 2006.182.07:48:51.60#ibcon#read 6, iclass 22, count 0 2006.182.07:48:51.60#ibcon#end of sib2, iclass 22, count 0 2006.182.07:48:51.60#ibcon#*after write, iclass 22, count 0 2006.182.07:48:51.60#ibcon#*before return 0, iclass 22, count 0 2006.182.07:48:51.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:51.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:48:51.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:48:51.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:48:51.60$vc4f8/vb=4,4 2006.182.07:48:51.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.07:48:51.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.07:48:51.60#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:51.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:51.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:51.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:51.66#ibcon#enter wrdev, iclass 24, count 2 2006.182.07:48:51.66#ibcon#first serial, iclass 24, count 2 2006.182.07:48:51.66#ibcon#enter sib2, iclass 24, count 2 2006.182.07:48:51.66#ibcon#flushed, iclass 24, count 2 2006.182.07:48:51.66#ibcon#about to write, iclass 24, count 2 2006.182.07:48:51.66#ibcon#wrote, iclass 24, count 2 2006.182.07:48:51.66#ibcon#about to read 3, iclass 24, count 2 2006.182.07:48:51.68#ibcon#read 3, iclass 24, count 2 2006.182.07:48:51.68#ibcon#about to read 4, iclass 24, count 2 2006.182.07:48:51.68#ibcon#read 4, iclass 24, count 2 2006.182.07:48:51.68#ibcon#about to read 5, iclass 24, count 2 2006.182.07:48:51.68#ibcon#read 5, iclass 24, count 2 2006.182.07:48:51.68#ibcon#about to read 6, iclass 24, count 2 2006.182.07:48:51.68#ibcon#read 6, iclass 24, count 2 2006.182.07:48:51.68#ibcon#end of sib2, iclass 24, count 2 2006.182.07:48:51.68#ibcon#*mode == 0, iclass 24, count 2 2006.182.07:48:51.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.07:48:51.68#ibcon#[27=AT04-04\r\n] 2006.182.07:48:51.68#ibcon#*before write, iclass 24, count 2 2006.182.07:48:51.68#ibcon#enter sib2, iclass 24, count 2 2006.182.07:48:51.68#ibcon#flushed, iclass 24, count 2 2006.182.07:48:51.68#ibcon#about to write, iclass 24, count 2 2006.182.07:48:51.68#ibcon#wrote, iclass 24, count 2 2006.182.07:48:51.68#ibcon#about to read 3, iclass 24, count 2 2006.182.07:48:51.71#ibcon#read 3, iclass 24, count 2 2006.182.07:48:51.71#ibcon#about to read 4, iclass 24, count 2 2006.182.07:48:51.71#ibcon#read 4, iclass 24, count 2 2006.182.07:48:51.71#ibcon#about to read 5, iclass 24, count 2 2006.182.07:48:51.71#ibcon#read 5, iclass 24, count 2 2006.182.07:48:51.71#ibcon#about to read 6, iclass 24, count 2 2006.182.07:48:51.71#ibcon#read 6, iclass 24, count 2 2006.182.07:48:51.71#ibcon#end of sib2, iclass 24, count 2 2006.182.07:48:51.71#ibcon#*after write, iclass 24, count 2 2006.182.07:48:51.71#ibcon#*before return 0, iclass 24, count 2 2006.182.07:48:51.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:51.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:48:51.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.07:48:51.71#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:51.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:51.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:51.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:51.83#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:48:51.83#ibcon#first serial, iclass 24, count 0 2006.182.07:48:51.83#ibcon#enter sib2, iclass 24, count 0 2006.182.07:48:51.83#ibcon#flushed, iclass 24, count 0 2006.182.07:48:51.83#ibcon#about to write, iclass 24, count 0 2006.182.07:48:51.83#ibcon#wrote, iclass 24, count 0 2006.182.07:48:51.83#ibcon#about to read 3, iclass 24, count 0 2006.182.07:48:51.85#ibcon#read 3, iclass 24, count 0 2006.182.07:48:51.85#ibcon#about to read 4, iclass 24, count 0 2006.182.07:48:51.85#ibcon#read 4, iclass 24, count 0 2006.182.07:48:51.85#ibcon#about to read 5, iclass 24, count 0 2006.182.07:48:51.85#ibcon#read 5, iclass 24, count 0 2006.182.07:48:51.85#ibcon#about to read 6, iclass 24, count 0 2006.182.07:48:51.85#ibcon#read 6, iclass 24, count 0 2006.182.07:48:51.85#ibcon#end of sib2, iclass 24, count 0 2006.182.07:48:51.85#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:48:51.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:48:51.85#ibcon#[27=USB\r\n] 2006.182.07:48:51.85#ibcon#*before write, iclass 24, count 0 2006.182.07:48:51.85#ibcon#enter sib2, iclass 24, count 0 2006.182.07:48:51.85#ibcon#flushed, iclass 24, count 0 2006.182.07:48:51.85#ibcon#about to write, iclass 24, count 0 2006.182.07:48:51.85#ibcon#wrote, iclass 24, count 0 2006.182.07:48:51.85#ibcon#about to read 3, iclass 24, count 0 2006.182.07:48:51.88#ibcon#read 3, iclass 24, count 0 2006.182.07:48:51.88#ibcon#about to read 4, iclass 24, count 0 2006.182.07:48:51.88#ibcon#read 4, iclass 24, count 0 2006.182.07:48:51.88#ibcon#about to read 5, iclass 24, count 0 2006.182.07:48:51.88#ibcon#read 5, iclass 24, count 0 2006.182.07:48:51.88#ibcon#about to read 6, iclass 24, count 0 2006.182.07:48:51.88#ibcon#read 6, iclass 24, count 0 2006.182.07:48:51.88#ibcon#end of sib2, iclass 24, count 0 2006.182.07:48:51.88#ibcon#*after write, iclass 24, count 0 2006.182.07:48:51.88#ibcon#*before return 0, iclass 24, count 0 2006.182.07:48:51.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:51.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:48:51.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:48:51.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:48:51.88$vc4f8/vblo=5,744.99 2006.182.07:48:51.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.07:48:51.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.07:48:51.88#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:51.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:51.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:51.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:51.88#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:48:51.88#ibcon#first serial, iclass 26, count 0 2006.182.07:48:51.88#ibcon#enter sib2, iclass 26, count 0 2006.182.07:48:51.88#ibcon#flushed, iclass 26, count 0 2006.182.07:48:51.88#ibcon#about to write, iclass 26, count 0 2006.182.07:48:51.88#ibcon#wrote, iclass 26, count 0 2006.182.07:48:51.88#ibcon#about to read 3, iclass 26, count 0 2006.182.07:48:51.90#ibcon#read 3, iclass 26, count 0 2006.182.07:48:51.90#ibcon#about to read 4, iclass 26, count 0 2006.182.07:48:51.90#ibcon#read 4, iclass 26, count 0 2006.182.07:48:51.90#ibcon#about to read 5, iclass 26, count 0 2006.182.07:48:51.90#ibcon#read 5, iclass 26, count 0 2006.182.07:48:51.90#ibcon#about to read 6, iclass 26, count 0 2006.182.07:48:51.90#ibcon#read 6, iclass 26, count 0 2006.182.07:48:51.90#ibcon#end of sib2, iclass 26, count 0 2006.182.07:48:51.90#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:48:51.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:48:51.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:48:51.90#ibcon#*before write, iclass 26, count 0 2006.182.07:48:51.90#ibcon#enter sib2, iclass 26, count 0 2006.182.07:48:51.90#ibcon#flushed, iclass 26, count 0 2006.182.07:48:51.90#ibcon#about to write, iclass 26, count 0 2006.182.07:48:51.90#ibcon#wrote, iclass 26, count 0 2006.182.07:48:51.90#ibcon#about to read 3, iclass 26, count 0 2006.182.07:48:51.94#ibcon#read 3, iclass 26, count 0 2006.182.07:48:51.94#ibcon#about to read 4, iclass 26, count 0 2006.182.07:48:51.94#ibcon#read 4, iclass 26, count 0 2006.182.07:48:51.94#ibcon#about to read 5, iclass 26, count 0 2006.182.07:48:51.94#ibcon#read 5, iclass 26, count 0 2006.182.07:48:51.94#ibcon#about to read 6, iclass 26, count 0 2006.182.07:48:51.94#ibcon#read 6, iclass 26, count 0 2006.182.07:48:51.94#ibcon#end of sib2, iclass 26, count 0 2006.182.07:48:51.94#ibcon#*after write, iclass 26, count 0 2006.182.07:48:51.94#ibcon#*before return 0, iclass 26, count 0 2006.182.07:48:51.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:51.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:48:51.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:48:51.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:48:51.94$vc4f8/vb=5,4 2006.182.07:48:51.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.07:48:51.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.07:48:51.94#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:51.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:52.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:52.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:52.00#ibcon#enter wrdev, iclass 28, count 2 2006.182.07:48:52.00#ibcon#first serial, iclass 28, count 2 2006.182.07:48:52.00#ibcon#enter sib2, iclass 28, count 2 2006.182.07:48:52.00#ibcon#flushed, iclass 28, count 2 2006.182.07:48:52.00#ibcon#about to write, iclass 28, count 2 2006.182.07:48:52.00#ibcon#wrote, iclass 28, count 2 2006.182.07:48:52.00#ibcon#about to read 3, iclass 28, count 2 2006.182.07:48:52.02#ibcon#read 3, iclass 28, count 2 2006.182.07:48:52.02#ibcon#about to read 4, iclass 28, count 2 2006.182.07:48:52.02#ibcon#read 4, iclass 28, count 2 2006.182.07:48:52.02#ibcon#about to read 5, iclass 28, count 2 2006.182.07:48:52.02#ibcon#read 5, iclass 28, count 2 2006.182.07:48:52.02#ibcon#about to read 6, iclass 28, count 2 2006.182.07:48:52.02#ibcon#read 6, iclass 28, count 2 2006.182.07:48:52.02#ibcon#end of sib2, iclass 28, count 2 2006.182.07:48:52.02#ibcon#*mode == 0, iclass 28, count 2 2006.182.07:48:52.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.07:48:52.02#ibcon#[27=AT05-04\r\n] 2006.182.07:48:52.02#ibcon#*before write, iclass 28, count 2 2006.182.07:48:52.02#ibcon#enter sib2, iclass 28, count 2 2006.182.07:48:52.02#ibcon#flushed, iclass 28, count 2 2006.182.07:48:52.02#ibcon#about to write, iclass 28, count 2 2006.182.07:48:52.02#ibcon#wrote, iclass 28, count 2 2006.182.07:48:52.02#ibcon#about to read 3, iclass 28, count 2 2006.182.07:48:52.05#ibcon#read 3, iclass 28, count 2 2006.182.07:48:52.05#ibcon#about to read 4, iclass 28, count 2 2006.182.07:48:52.05#ibcon#read 4, iclass 28, count 2 2006.182.07:48:52.05#ibcon#about to read 5, iclass 28, count 2 2006.182.07:48:52.05#ibcon#read 5, iclass 28, count 2 2006.182.07:48:52.05#ibcon#about to read 6, iclass 28, count 2 2006.182.07:48:52.05#ibcon#read 6, iclass 28, count 2 2006.182.07:48:52.05#ibcon#end of sib2, iclass 28, count 2 2006.182.07:48:52.05#ibcon#*after write, iclass 28, count 2 2006.182.07:48:52.05#ibcon#*before return 0, iclass 28, count 2 2006.182.07:48:52.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:52.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:48:52.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.07:48:52.05#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:52.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:52.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:52.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:52.17#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:48:52.17#ibcon#first serial, iclass 28, count 0 2006.182.07:48:52.17#ibcon#enter sib2, iclass 28, count 0 2006.182.07:48:52.17#ibcon#flushed, iclass 28, count 0 2006.182.07:48:52.17#ibcon#about to write, iclass 28, count 0 2006.182.07:48:52.17#ibcon#wrote, iclass 28, count 0 2006.182.07:48:52.17#ibcon#about to read 3, iclass 28, count 0 2006.182.07:48:52.19#ibcon#read 3, iclass 28, count 0 2006.182.07:48:52.19#ibcon#about to read 4, iclass 28, count 0 2006.182.07:48:52.19#ibcon#read 4, iclass 28, count 0 2006.182.07:48:52.19#ibcon#about to read 5, iclass 28, count 0 2006.182.07:48:52.19#ibcon#read 5, iclass 28, count 0 2006.182.07:48:52.19#ibcon#about to read 6, iclass 28, count 0 2006.182.07:48:52.19#ibcon#read 6, iclass 28, count 0 2006.182.07:48:52.19#ibcon#end of sib2, iclass 28, count 0 2006.182.07:48:52.19#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:48:52.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:48:52.19#ibcon#[27=USB\r\n] 2006.182.07:48:52.19#ibcon#*before write, iclass 28, count 0 2006.182.07:48:52.19#ibcon#enter sib2, iclass 28, count 0 2006.182.07:48:52.19#ibcon#flushed, iclass 28, count 0 2006.182.07:48:52.19#ibcon#about to write, iclass 28, count 0 2006.182.07:48:52.19#ibcon#wrote, iclass 28, count 0 2006.182.07:48:52.19#ibcon#about to read 3, iclass 28, count 0 2006.182.07:48:52.22#ibcon#read 3, iclass 28, count 0 2006.182.07:48:52.22#ibcon#about to read 4, iclass 28, count 0 2006.182.07:48:52.22#ibcon#read 4, iclass 28, count 0 2006.182.07:48:52.22#ibcon#about to read 5, iclass 28, count 0 2006.182.07:48:52.22#ibcon#read 5, iclass 28, count 0 2006.182.07:48:52.22#ibcon#about to read 6, iclass 28, count 0 2006.182.07:48:52.22#ibcon#read 6, iclass 28, count 0 2006.182.07:48:52.22#ibcon#end of sib2, iclass 28, count 0 2006.182.07:48:52.22#ibcon#*after write, iclass 28, count 0 2006.182.07:48:52.22#ibcon#*before return 0, iclass 28, count 0 2006.182.07:48:52.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:52.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:48:52.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:48:52.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:48:52.22$vc4f8/vblo=6,752.99 2006.182.07:48:52.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.07:48:52.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.07:48:52.22#ibcon#ireg 17 cls_cnt 0 2006.182.07:48:52.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:52.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:52.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:52.22#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:48:52.22#ibcon#first serial, iclass 30, count 0 2006.182.07:48:52.22#ibcon#enter sib2, iclass 30, count 0 2006.182.07:48:52.22#ibcon#flushed, iclass 30, count 0 2006.182.07:48:52.22#ibcon#about to write, iclass 30, count 0 2006.182.07:48:52.22#ibcon#wrote, iclass 30, count 0 2006.182.07:48:52.22#ibcon#about to read 3, iclass 30, count 0 2006.182.07:48:52.24#ibcon#read 3, iclass 30, count 0 2006.182.07:48:52.24#ibcon#about to read 4, iclass 30, count 0 2006.182.07:48:52.24#ibcon#read 4, iclass 30, count 0 2006.182.07:48:52.24#ibcon#about to read 5, iclass 30, count 0 2006.182.07:48:52.24#ibcon#read 5, iclass 30, count 0 2006.182.07:48:52.24#ibcon#about to read 6, iclass 30, count 0 2006.182.07:48:52.24#ibcon#read 6, iclass 30, count 0 2006.182.07:48:52.24#ibcon#end of sib2, iclass 30, count 0 2006.182.07:48:52.24#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:48:52.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:48:52.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:48:52.24#ibcon#*before write, iclass 30, count 0 2006.182.07:48:52.24#ibcon#enter sib2, iclass 30, count 0 2006.182.07:48:52.24#ibcon#flushed, iclass 30, count 0 2006.182.07:48:52.24#ibcon#about to write, iclass 30, count 0 2006.182.07:48:52.24#ibcon#wrote, iclass 30, count 0 2006.182.07:48:52.24#ibcon#about to read 3, iclass 30, count 0 2006.182.07:48:52.28#ibcon#read 3, iclass 30, count 0 2006.182.07:48:52.28#ibcon#about to read 4, iclass 30, count 0 2006.182.07:48:52.28#ibcon#read 4, iclass 30, count 0 2006.182.07:48:52.28#ibcon#about to read 5, iclass 30, count 0 2006.182.07:48:52.28#ibcon#read 5, iclass 30, count 0 2006.182.07:48:52.28#ibcon#about to read 6, iclass 30, count 0 2006.182.07:48:52.28#ibcon#read 6, iclass 30, count 0 2006.182.07:48:52.28#ibcon#end of sib2, iclass 30, count 0 2006.182.07:48:52.28#ibcon#*after write, iclass 30, count 0 2006.182.07:48:52.28#ibcon#*before return 0, iclass 30, count 0 2006.182.07:48:52.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:52.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:48:52.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:48:52.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:48:52.28$vc4f8/vb=6,4 2006.182.07:48:52.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.07:48:52.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.07:48:52.28#ibcon#ireg 11 cls_cnt 2 2006.182.07:48:52.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:52.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:52.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:52.34#ibcon#enter wrdev, iclass 32, count 2 2006.182.07:48:52.34#ibcon#first serial, iclass 32, count 2 2006.182.07:48:52.34#ibcon#enter sib2, iclass 32, count 2 2006.182.07:48:52.34#ibcon#flushed, iclass 32, count 2 2006.182.07:48:52.34#ibcon#about to write, iclass 32, count 2 2006.182.07:48:52.34#ibcon#wrote, iclass 32, count 2 2006.182.07:48:52.34#ibcon#about to read 3, iclass 32, count 2 2006.182.07:48:52.36#ibcon#read 3, iclass 32, count 2 2006.182.07:48:52.36#ibcon#about to read 4, iclass 32, count 2 2006.182.07:48:52.36#ibcon#read 4, iclass 32, count 2 2006.182.07:48:52.36#ibcon#about to read 5, iclass 32, count 2 2006.182.07:48:52.36#ibcon#read 5, iclass 32, count 2 2006.182.07:48:52.36#ibcon#about to read 6, iclass 32, count 2 2006.182.07:48:52.36#ibcon#read 6, iclass 32, count 2 2006.182.07:48:52.36#ibcon#end of sib2, iclass 32, count 2 2006.182.07:48:52.36#ibcon#*mode == 0, iclass 32, count 2 2006.182.07:48:52.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.07:48:52.36#ibcon#[27=AT06-04\r\n] 2006.182.07:48:52.36#ibcon#*before write, iclass 32, count 2 2006.182.07:48:52.36#ibcon#enter sib2, iclass 32, count 2 2006.182.07:48:52.36#ibcon#flushed, iclass 32, count 2 2006.182.07:48:52.36#ibcon#about to write, iclass 32, count 2 2006.182.07:48:52.36#ibcon#wrote, iclass 32, count 2 2006.182.07:48:52.36#ibcon#about to read 3, iclass 32, count 2 2006.182.07:48:52.39#ibcon#read 3, iclass 32, count 2 2006.182.07:48:52.39#ibcon#about to read 4, iclass 32, count 2 2006.182.07:48:52.39#ibcon#read 4, iclass 32, count 2 2006.182.07:48:52.39#ibcon#about to read 5, iclass 32, count 2 2006.182.07:48:52.39#ibcon#read 5, iclass 32, count 2 2006.182.07:48:52.39#ibcon#about to read 6, iclass 32, count 2 2006.182.07:48:52.39#ibcon#read 6, iclass 32, count 2 2006.182.07:48:52.39#ibcon#end of sib2, iclass 32, count 2 2006.182.07:48:52.39#ibcon#*after write, iclass 32, count 2 2006.182.07:48:52.39#ibcon#*before return 0, iclass 32, count 2 2006.182.07:48:52.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:52.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:48:52.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.07:48:52.39#ibcon#ireg 7 cls_cnt 0 2006.182.07:48:52.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:52.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:52.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:52.51#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:48:52.51#ibcon#first serial, iclass 32, count 0 2006.182.07:48:52.51#ibcon#enter sib2, iclass 32, count 0 2006.182.07:48:52.51#ibcon#flushed, iclass 32, count 0 2006.182.07:48:52.51#ibcon#about to write, iclass 32, count 0 2006.182.07:48:52.51#ibcon#wrote, iclass 32, count 0 2006.182.07:48:52.51#ibcon#about to read 3, iclass 32, count 0 2006.182.07:48:52.53#ibcon#read 3, iclass 32, count 0 2006.182.07:48:52.53#ibcon#about to read 4, iclass 32, count 0 2006.182.07:48:52.53#ibcon#read 4, iclass 32, count 0 2006.182.07:48:52.53#ibcon#about to read 5, iclass 32, count 0 2006.182.07:48:52.53#ibcon#read 5, iclass 32, count 0 2006.182.07:48:52.53#ibcon#about to read 6, iclass 32, count 0 2006.182.07:48:52.53#ibcon#read 6, iclass 32, count 0 2006.182.07:48:52.53#ibcon#end of sib2, iclass 32, count 0 2006.182.07:48:52.53#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:48:52.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:48:52.53#ibcon#[27=USB\r\n] 2006.182.07:48:52.53#ibcon#*before write, iclass 32, count 0 2006.182.07:48:52.53#ibcon#enter sib2, iclass 32, count 0 2006.182.07:48:52.53#ibcon#flushed, iclass 32, count 0 2006.182.07:48:52.53#ibcon#about to write, iclass 32, count 0 2006.182.07:48:52.53#ibcon#wrote, iclass 32, count 0 2006.182.07:48:52.53#ibcon#about to read 3, iclass 32, count 0 2006.182.07:48:52.56#ibcon#read 3, iclass 32, count 0 2006.182.07:48:52.56#ibcon#about to read 4, iclass 32, count 0 2006.182.07:48:52.56#ibcon#read 4, iclass 32, count 0 2006.182.07:48:52.56#ibcon#about to read 5, iclass 32, count 0 2006.182.07:48:52.56#ibcon#read 5, iclass 32, count 0 2006.182.07:48:52.56#ibcon#about to read 6, iclass 32, count 0 2006.182.07:48:52.56#ibcon#read 6, iclass 32, count 0 2006.182.07:48:52.56#ibcon#end of sib2, iclass 32, count 0 2006.182.07:48:52.56#ibcon#*after write, iclass 32, count 0 2006.182.07:48:52.56#ibcon#*before return 0, iclass 32, count 0 2006.182.07:48:52.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:52.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:48:52.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:48:52.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:48:52.56$vc4f8/vabw=wide 2006.182.07:48:52.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.07:48:52.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.07:48:52.56#ibcon#ireg 8 cls_cnt 0 2006.182.07:48:52.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:52.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:52.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:52.56#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:48:52.56#ibcon#first serial, iclass 34, count 0 2006.182.07:48:52.56#ibcon#enter sib2, iclass 34, count 0 2006.182.07:48:52.56#ibcon#flushed, iclass 34, count 0 2006.182.07:48:52.56#ibcon#about to write, iclass 34, count 0 2006.182.07:48:52.56#ibcon#wrote, iclass 34, count 0 2006.182.07:48:52.56#ibcon#about to read 3, iclass 34, count 0 2006.182.07:48:52.58#ibcon#read 3, iclass 34, count 0 2006.182.07:48:52.58#ibcon#about to read 4, iclass 34, count 0 2006.182.07:48:52.58#ibcon#read 4, iclass 34, count 0 2006.182.07:48:52.58#ibcon#about to read 5, iclass 34, count 0 2006.182.07:48:52.58#ibcon#read 5, iclass 34, count 0 2006.182.07:48:52.58#ibcon#about to read 6, iclass 34, count 0 2006.182.07:48:52.58#ibcon#read 6, iclass 34, count 0 2006.182.07:48:52.58#ibcon#end of sib2, iclass 34, count 0 2006.182.07:48:52.58#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:48:52.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:48:52.58#ibcon#[25=BW32\r\n] 2006.182.07:48:52.58#ibcon#*before write, iclass 34, count 0 2006.182.07:48:52.58#ibcon#enter sib2, iclass 34, count 0 2006.182.07:48:52.58#ibcon#flushed, iclass 34, count 0 2006.182.07:48:52.58#ibcon#about to write, iclass 34, count 0 2006.182.07:48:52.58#ibcon#wrote, iclass 34, count 0 2006.182.07:48:52.58#ibcon#about to read 3, iclass 34, count 0 2006.182.07:48:52.61#ibcon#read 3, iclass 34, count 0 2006.182.07:48:52.61#ibcon#about to read 4, iclass 34, count 0 2006.182.07:48:52.61#ibcon#read 4, iclass 34, count 0 2006.182.07:48:52.61#ibcon#about to read 5, iclass 34, count 0 2006.182.07:48:52.61#ibcon#read 5, iclass 34, count 0 2006.182.07:48:52.61#ibcon#about to read 6, iclass 34, count 0 2006.182.07:48:52.61#ibcon#read 6, iclass 34, count 0 2006.182.07:48:52.61#ibcon#end of sib2, iclass 34, count 0 2006.182.07:48:52.61#ibcon#*after write, iclass 34, count 0 2006.182.07:48:52.61#ibcon#*before return 0, iclass 34, count 0 2006.182.07:48:52.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:52.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:48:52.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:48:52.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:48:52.61$vc4f8/vbbw=wide 2006.182.07:48:52.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.07:48:52.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.07:48:52.61#ibcon#ireg 8 cls_cnt 0 2006.182.07:48:52.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:48:52.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:48:52.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:48:52.68#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:48:52.68#ibcon#first serial, iclass 36, count 0 2006.182.07:48:52.68#ibcon#enter sib2, iclass 36, count 0 2006.182.07:48:52.68#ibcon#flushed, iclass 36, count 0 2006.182.07:48:52.68#ibcon#about to write, iclass 36, count 0 2006.182.07:48:52.68#ibcon#wrote, iclass 36, count 0 2006.182.07:48:52.68#ibcon#about to read 3, iclass 36, count 0 2006.182.07:48:52.70#ibcon#read 3, iclass 36, count 0 2006.182.07:48:52.70#ibcon#about to read 4, iclass 36, count 0 2006.182.07:48:52.70#ibcon#read 4, iclass 36, count 0 2006.182.07:48:52.70#ibcon#about to read 5, iclass 36, count 0 2006.182.07:48:52.70#ibcon#read 5, iclass 36, count 0 2006.182.07:48:52.70#ibcon#about to read 6, iclass 36, count 0 2006.182.07:48:52.70#ibcon#read 6, iclass 36, count 0 2006.182.07:48:52.70#ibcon#end of sib2, iclass 36, count 0 2006.182.07:48:52.70#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:48:52.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:48:52.70#ibcon#[27=BW32\r\n] 2006.182.07:48:52.70#ibcon#*before write, iclass 36, count 0 2006.182.07:48:52.70#ibcon#enter sib2, iclass 36, count 0 2006.182.07:48:52.70#ibcon#flushed, iclass 36, count 0 2006.182.07:48:52.70#ibcon#about to write, iclass 36, count 0 2006.182.07:48:52.70#ibcon#wrote, iclass 36, count 0 2006.182.07:48:52.70#ibcon#about to read 3, iclass 36, count 0 2006.182.07:48:52.73#ibcon#read 3, iclass 36, count 0 2006.182.07:48:52.73#ibcon#about to read 4, iclass 36, count 0 2006.182.07:48:52.73#ibcon#read 4, iclass 36, count 0 2006.182.07:48:52.73#ibcon#about to read 5, iclass 36, count 0 2006.182.07:48:52.73#ibcon#read 5, iclass 36, count 0 2006.182.07:48:52.73#ibcon#about to read 6, iclass 36, count 0 2006.182.07:48:52.73#ibcon#read 6, iclass 36, count 0 2006.182.07:48:52.73#ibcon#end of sib2, iclass 36, count 0 2006.182.07:48:52.73#ibcon#*after write, iclass 36, count 0 2006.182.07:48:52.73#ibcon#*before return 0, iclass 36, count 0 2006.182.07:48:52.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:48:52.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:48:52.73#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:48:52.73#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:48:52.73$4f8m12a/ifd4f 2006.182.07:48:52.73$ifd4f/lo= 2006.182.07:48:52.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:48:52.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:48:52.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:48:52.73$ifd4f/patch= 2006.182.07:48:52.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:48:52.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:48:52.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:48:52.73$4f8m12a/"form=m,16.000,1:2 2006.182.07:48:52.73$4f8m12a/"tpicd 2006.182.07:48:52.73$4f8m12a/echo=off 2006.182.07:48:52.73$4f8m12a/xlog=off 2006.182.07:48:52.73:!2006.182.07:49:20 2006.182.07:49:07.14#trakl#Source acquired 2006.182.07:49:08.14#flagr#flagr/antenna,acquired 2006.182.07:49:20.00:preob 2006.182.07:49:21.14/onsource/TRACKING 2006.182.07:49:21.14:!2006.182.07:49:30 2006.182.07:49:30.00:data_valid=on 2006.182.07:49:30.00:midob 2006.182.07:49:30.14/onsource/TRACKING 2006.182.07:49:30.14/wx/27.62,1002.8,80 2006.182.07:49:30.22/cable/+6.4642E-03 2006.182.07:49:31.31/va/01,08,usb,yes,28,30 2006.182.07:49:31.31/va/02,07,usb,yes,28,30 2006.182.07:49:31.31/va/03,06,usb,yes,30,30 2006.182.07:49:31.31/va/04,07,usb,yes,29,31 2006.182.07:49:31.31/va/05,07,usb,yes,30,32 2006.182.07:49:31.31/va/06,06,usb,yes,29,29 2006.182.07:49:31.31/va/07,06,usb,yes,30,29 2006.182.07:49:31.31/va/08,07,usb,yes,28,28 2006.182.07:49:31.54/valo/01,532.99,yes,locked 2006.182.07:49:31.54/valo/02,572.99,yes,locked 2006.182.07:49:31.54/valo/03,672.99,yes,locked 2006.182.07:49:31.54/valo/04,832.99,yes,locked 2006.182.07:49:31.54/valo/05,652.99,yes,locked 2006.182.07:49:31.54/valo/06,772.99,yes,locked 2006.182.07:49:31.54/valo/07,832.99,yes,locked 2006.182.07:49:31.54/valo/08,852.99,yes,locked 2006.182.07:49:32.63/vb/01,04,usb,yes,28,27 2006.182.07:49:32.63/vb/02,04,usb,yes,30,32 2006.182.07:49:32.63/vb/03,04,usb,yes,27,30 2006.182.07:49:32.63/vb/04,04,usb,yes,27,28 2006.182.07:49:32.63/vb/05,04,usb,yes,26,30 2006.182.07:49:32.63/vb/06,04,usb,yes,27,30 2006.182.07:49:32.63/vb/07,04,usb,yes,29,29 2006.182.07:49:32.63/vb/08,04,usb,yes,27,30 2006.182.07:49:32.87/vblo/01,632.99,yes,locked 2006.182.07:49:32.87/vblo/02,640.99,yes,locked 2006.182.07:49:32.87/vblo/03,656.99,yes,locked 2006.182.07:49:32.87/vblo/04,712.99,yes,locked 2006.182.07:49:32.87/vblo/05,744.99,yes,locked 2006.182.07:49:32.87/vblo/06,752.99,yes,locked 2006.182.07:49:32.87/vblo/07,734.99,yes,locked 2006.182.07:49:32.87/vblo/08,744.99,yes,locked 2006.182.07:49:33.02/vabw/8 2006.182.07:49:33.17/vbbw/8 2006.182.07:49:33.33/xfe/off,on,14.7 2006.182.07:49:33.72/ifatt/23,28,28,28 2006.182.07:49:34.08/fmout-gps/S +3.37E-07 2006.182.07:49:34.12:!2006.182.07:50:30 2006.182.07:50:30.00:data_valid=off 2006.182.07:50:30.00:postob 2006.182.07:50:30.13/cable/+6.4659E-03 2006.182.07:50:30.13/wx/27.63,1002.8,82 2006.182.07:50:31.08/fmout-gps/S +3.37E-07 2006.182.07:50:31.08:scan_name=182-0751,k06182,60 2006.182.07:50:31.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.182.07:50:31.14#flagr#flagr/antenna,new-source 2006.182.07:50:32.14:checkk5 2006.182.07:50:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:50:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:50:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:50:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:50:34.00/chk_obsdata//k5ts1/T1820749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:50:34.37/chk_obsdata//k5ts2/T1820749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:50:34.74/chk_obsdata//k5ts3/T1820749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:50:35.11/chk_obsdata//k5ts4/T1820749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:50:35.80/k5log//k5ts1_log_newline 2006.182.07:50:36.49/k5log//k5ts2_log_newline 2006.182.07:50:37.18/k5log//k5ts3_log_newline 2006.182.07:50:37.87/k5log//k5ts4_log_newline 2006.182.07:50:37.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:50:37.89:4f8m12a=1 2006.182.07:50:37.89$4f8m12a/echo=on 2006.182.07:50:37.89$4f8m12a/pcalon 2006.182.07:50:37.89$pcalon/"no phase cal control is implemented here 2006.182.07:50:37.89$4f8m12a/"tpicd=stop 2006.182.07:50:37.89$4f8m12a/vc4f8 2006.182.07:50:37.89$vc4f8/valo=1,532.99 2006.182.07:50:37.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.07:50:37.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.07:50:37.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:37.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:37.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:37.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:37.89#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:50:37.89#ibcon#first serial, iclass 5, count 0 2006.182.07:50:37.89#ibcon#enter sib2, iclass 5, count 0 2006.182.07:50:37.89#ibcon#flushed, iclass 5, count 0 2006.182.07:50:37.89#ibcon#about to write, iclass 5, count 0 2006.182.07:50:37.89#ibcon#wrote, iclass 5, count 0 2006.182.07:50:37.89#ibcon#about to read 3, iclass 5, count 0 2006.182.07:50:37.91#ibcon#read 3, iclass 5, count 0 2006.182.07:50:37.91#ibcon#about to read 4, iclass 5, count 0 2006.182.07:50:37.91#ibcon#read 4, iclass 5, count 0 2006.182.07:50:37.91#ibcon#about to read 5, iclass 5, count 0 2006.182.07:50:37.91#ibcon#read 5, iclass 5, count 0 2006.182.07:50:37.91#ibcon#about to read 6, iclass 5, count 0 2006.182.07:50:37.91#ibcon#read 6, iclass 5, count 0 2006.182.07:50:37.91#ibcon#end of sib2, iclass 5, count 0 2006.182.07:50:37.91#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:50:37.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:50:37.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:50:37.91#ibcon#*before write, iclass 5, count 0 2006.182.07:50:37.91#ibcon#enter sib2, iclass 5, count 0 2006.182.07:50:37.91#ibcon#flushed, iclass 5, count 0 2006.182.07:50:37.91#ibcon#about to write, iclass 5, count 0 2006.182.07:50:37.91#ibcon#wrote, iclass 5, count 0 2006.182.07:50:37.91#ibcon#about to read 3, iclass 5, count 0 2006.182.07:50:37.96#ibcon#read 3, iclass 5, count 0 2006.182.07:50:37.96#ibcon#about to read 4, iclass 5, count 0 2006.182.07:50:37.96#ibcon#read 4, iclass 5, count 0 2006.182.07:50:37.96#ibcon#about to read 5, iclass 5, count 0 2006.182.07:50:37.96#ibcon#read 5, iclass 5, count 0 2006.182.07:50:37.96#ibcon#about to read 6, iclass 5, count 0 2006.182.07:50:37.96#ibcon#read 6, iclass 5, count 0 2006.182.07:50:37.96#ibcon#end of sib2, iclass 5, count 0 2006.182.07:50:37.96#ibcon#*after write, iclass 5, count 0 2006.182.07:50:37.96#ibcon#*before return 0, iclass 5, count 0 2006.182.07:50:37.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:37.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:37.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:50:37.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:50:37.96$vc4f8/va=1,8 2006.182.07:50:37.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.07:50:37.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.07:50:37.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:37.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:37.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:37.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:37.96#ibcon#enter wrdev, iclass 7, count 2 2006.182.07:50:37.96#ibcon#first serial, iclass 7, count 2 2006.182.07:50:37.96#ibcon#enter sib2, iclass 7, count 2 2006.182.07:50:37.96#ibcon#flushed, iclass 7, count 2 2006.182.07:50:37.96#ibcon#about to write, iclass 7, count 2 2006.182.07:50:37.96#ibcon#wrote, iclass 7, count 2 2006.182.07:50:37.96#ibcon#about to read 3, iclass 7, count 2 2006.182.07:50:37.98#ibcon#read 3, iclass 7, count 2 2006.182.07:50:37.98#ibcon#about to read 4, iclass 7, count 2 2006.182.07:50:37.98#ibcon#read 4, iclass 7, count 2 2006.182.07:50:37.98#ibcon#about to read 5, iclass 7, count 2 2006.182.07:50:37.98#ibcon#read 5, iclass 7, count 2 2006.182.07:50:37.98#ibcon#about to read 6, iclass 7, count 2 2006.182.07:50:37.98#ibcon#read 6, iclass 7, count 2 2006.182.07:50:37.98#ibcon#end of sib2, iclass 7, count 2 2006.182.07:50:37.98#ibcon#*mode == 0, iclass 7, count 2 2006.182.07:50:37.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.07:50:37.98#ibcon#[25=AT01-08\r\n] 2006.182.07:50:37.98#ibcon#*before write, iclass 7, count 2 2006.182.07:50:37.98#ibcon#enter sib2, iclass 7, count 2 2006.182.07:50:37.98#ibcon#flushed, iclass 7, count 2 2006.182.07:50:37.98#ibcon#about to write, iclass 7, count 2 2006.182.07:50:37.98#ibcon#wrote, iclass 7, count 2 2006.182.07:50:37.98#ibcon#about to read 3, iclass 7, count 2 2006.182.07:50:38.01#ibcon#read 3, iclass 7, count 2 2006.182.07:50:38.01#ibcon#about to read 4, iclass 7, count 2 2006.182.07:50:38.01#ibcon#read 4, iclass 7, count 2 2006.182.07:50:38.01#ibcon#about to read 5, iclass 7, count 2 2006.182.07:50:38.01#ibcon#read 5, iclass 7, count 2 2006.182.07:50:38.01#ibcon#about to read 6, iclass 7, count 2 2006.182.07:50:38.01#ibcon#read 6, iclass 7, count 2 2006.182.07:50:38.01#ibcon#end of sib2, iclass 7, count 2 2006.182.07:50:38.01#ibcon#*after write, iclass 7, count 2 2006.182.07:50:38.01#ibcon#*before return 0, iclass 7, count 2 2006.182.07:50:38.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:38.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:38.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.07:50:38.01#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:38.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:38.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:38.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:38.13#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:50:38.13#ibcon#first serial, iclass 7, count 0 2006.182.07:50:38.13#ibcon#enter sib2, iclass 7, count 0 2006.182.07:50:38.13#ibcon#flushed, iclass 7, count 0 2006.182.07:50:38.13#ibcon#about to write, iclass 7, count 0 2006.182.07:50:38.13#ibcon#wrote, iclass 7, count 0 2006.182.07:50:38.13#ibcon#about to read 3, iclass 7, count 0 2006.182.07:50:38.15#ibcon#read 3, iclass 7, count 0 2006.182.07:50:38.15#ibcon#about to read 4, iclass 7, count 0 2006.182.07:50:38.15#ibcon#read 4, iclass 7, count 0 2006.182.07:50:38.15#ibcon#about to read 5, iclass 7, count 0 2006.182.07:50:38.15#ibcon#read 5, iclass 7, count 0 2006.182.07:50:38.15#ibcon#about to read 6, iclass 7, count 0 2006.182.07:50:38.15#ibcon#read 6, iclass 7, count 0 2006.182.07:50:38.15#ibcon#end of sib2, iclass 7, count 0 2006.182.07:50:38.15#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:50:38.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:50:38.15#ibcon#[25=USB\r\n] 2006.182.07:50:38.15#ibcon#*before write, iclass 7, count 0 2006.182.07:50:38.15#ibcon#enter sib2, iclass 7, count 0 2006.182.07:50:38.15#ibcon#flushed, iclass 7, count 0 2006.182.07:50:38.15#ibcon#about to write, iclass 7, count 0 2006.182.07:50:38.15#ibcon#wrote, iclass 7, count 0 2006.182.07:50:38.15#ibcon#about to read 3, iclass 7, count 0 2006.182.07:50:38.18#ibcon#read 3, iclass 7, count 0 2006.182.07:50:38.18#ibcon#about to read 4, iclass 7, count 0 2006.182.07:50:38.18#ibcon#read 4, iclass 7, count 0 2006.182.07:50:38.18#ibcon#about to read 5, iclass 7, count 0 2006.182.07:50:38.18#ibcon#read 5, iclass 7, count 0 2006.182.07:50:38.18#ibcon#about to read 6, iclass 7, count 0 2006.182.07:50:38.18#ibcon#read 6, iclass 7, count 0 2006.182.07:50:38.18#ibcon#end of sib2, iclass 7, count 0 2006.182.07:50:38.18#ibcon#*after write, iclass 7, count 0 2006.182.07:50:38.18#ibcon#*before return 0, iclass 7, count 0 2006.182.07:50:38.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:38.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:38.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:50:38.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:50:38.18$vc4f8/valo=2,572.99 2006.182.07:50:38.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.07:50:38.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.07:50:38.18#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:38.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:38.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:38.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:38.18#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:50:38.18#ibcon#first serial, iclass 11, count 0 2006.182.07:50:38.18#ibcon#enter sib2, iclass 11, count 0 2006.182.07:50:38.18#ibcon#flushed, iclass 11, count 0 2006.182.07:50:38.18#ibcon#about to write, iclass 11, count 0 2006.182.07:50:38.18#ibcon#wrote, iclass 11, count 0 2006.182.07:50:38.18#ibcon#about to read 3, iclass 11, count 0 2006.182.07:50:38.20#ibcon#read 3, iclass 11, count 0 2006.182.07:50:38.20#ibcon#about to read 4, iclass 11, count 0 2006.182.07:50:38.20#ibcon#read 4, iclass 11, count 0 2006.182.07:50:38.20#ibcon#about to read 5, iclass 11, count 0 2006.182.07:50:38.20#ibcon#read 5, iclass 11, count 0 2006.182.07:50:38.20#ibcon#about to read 6, iclass 11, count 0 2006.182.07:50:38.20#ibcon#read 6, iclass 11, count 0 2006.182.07:50:38.20#ibcon#end of sib2, iclass 11, count 0 2006.182.07:50:38.20#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:50:38.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:50:38.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:50:38.20#ibcon#*before write, iclass 11, count 0 2006.182.07:50:38.20#ibcon#enter sib2, iclass 11, count 0 2006.182.07:50:38.20#ibcon#flushed, iclass 11, count 0 2006.182.07:50:38.20#ibcon#about to write, iclass 11, count 0 2006.182.07:50:38.20#ibcon#wrote, iclass 11, count 0 2006.182.07:50:38.20#ibcon#about to read 3, iclass 11, count 0 2006.182.07:50:38.25#ibcon#read 3, iclass 11, count 0 2006.182.07:50:38.25#ibcon#about to read 4, iclass 11, count 0 2006.182.07:50:38.25#ibcon#read 4, iclass 11, count 0 2006.182.07:50:38.25#ibcon#about to read 5, iclass 11, count 0 2006.182.07:50:38.25#ibcon#read 5, iclass 11, count 0 2006.182.07:50:38.25#ibcon#about to read 6, iclass 11, count 0 2006.182.07:50:38.25#ibcon#read 6, iclass 11, count 0 2006.182.07:50:38.25#ibcon#end of sib2, iclass 11, count 0 2006.182.07:50:38.25#ibcon#*after write, iclass 11, count 0 2006.182.07:50:38.25#ibcon#*before return 0, iclass 11, count 0 2006.182.07:50:38.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:38.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:38.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:50:38.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:50:38.25$vc4f8/va=2,7 2006.182.07:50:38.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.07:50:38.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.07:50:38.25#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:38.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:38.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:38.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:38.30#ibcon#enter wrdev, iclass 13, count 2 2006.182.07:50:38.30#ibcon#first serial, iclass 13, count 2 2006.182.07:50:38.30#ibcon#enter sib2, iclass 13, count 2 2006.182.07:50:38.30#ibcon#flushed, iclass 13, count 2 2006.182.07:50:38.30#ibcon#about to write, iclass 13, count 2 2006.182.07:50:38.30#ibcon#wrote, iclass 13, count 2 2006.182.07:50:38.30#ibcon#about to read 3, iclass 13, count 2 2006.182.07:50:38.32#ibcon#read 3, iclass 13, count 2 2006.182.07:50:38.32#ibcon#about to read 4, iclass 13, count 2 2006.182.07:50:38.32#ibcon#read 4, iclass 13, count 2 2006.182.07:50:38.32#ibcon#about to read 5, iclass 13, count 2 2006.182.07:50:38.32#ibcon#read 5, iclass 13, count 2 2006.182.07:50:38.32#ibcon#about to read 6, iclass 13, count 2 2006.182.07:50:38.32#ibcon#read 6, iclass 13, count 2 2006.182.07:50:38.32#ibcon#end of sib2, iclass 13, count 2 2006.182.07:50:38.32#ibcon#*mode == 0, iclass 13, count 2 2006.182.07:50:38.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.07:50:38.32#ibcon#[25=AT02-07\r\n] 2006.182.07:50:38.32#ibcon#*before write, iclass 13, count 2 2006.182.07:50:38.32#ibcon#enter sib2, iclass 13, count 2 2006.182.07:50:38.32#ibcon#flushed, iclass 13, count 2 2006.182.07:50:38.32#ibcon#about to write, iclass 13, count 2 2006.182.07:50:38.32#ibcon#wrote, iclass 13, count 2 2006.182.07:50:38.32#ibcon#about to read 3, iclass 13, count 2 2006.182.07:50:38.35#ibcon#read 3, iclass 13, count 2 2006.182.07:50:38.35#ibcon#about to read 4, iclass 13, count 2 2006.182.07:50:38.35#ibcon#read 4, iclass 13, count 2 2006.182.07:50:38.35#ibcon#about to read 5, iclass 13, count 2 2006.182.07:50:38.35#ibcon#read 5, iclass 13, count 2 2006.182.07:50:38.35#ibcon#about to read 6, iclass 13, count 2 2006.182.07:50:38.35#ibcon#read 6, iclass 13, count 2 2006.182.07:50:38.35#ibcon#end of sib2, iclass 13, count 2 2006.182.07:50:38.35#ibcon#*after write, iclass 13, count 2 2006.182.07:50:38.35#ibcon#*before return 0, iclass 13, count 2 2006.182.07:50:38.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:38.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:38.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.07:50:38.35#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:38.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:38.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:38.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:38.47#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:50:38.47#ibcon#first serial, iclass 13, count 0 2006.182.07:50:38.47#ibcon#enter sib2, iclass 13, count 0 2006.182.07:50:38.47#ibcon#flushed, iclass 13, count 0 2006.182.07:50:38.47#ibcon#about to write, iclass 13, count 0 2006.182.07:50:38.47#ibcon#wrote, iclass 13, count 0 2006.182.07:50:38.47#ibcon#about to read 3, iclass 13, count 0 2006.182.07:50:38.49#ibcon#read 3, iclass 13, count 0 2006.182.07:50:38.49#ibcon#about to read 4, iclass 13, count 0 2006.182.07:50:38.49#ibcon#read 4, iclass 13, count 0 2006.182.07:50:38.49#ibcon#about to read 5, iclass 13, count 0 2006.182.07:50:38.49#ibcon#read 5, iclass 13, count 0 2006.182.07:50:38.49#ibcon#about to read 6, iclass 13, count 0 2006.182.07:50:38.49#ibcon#read 6, iclass 13, count 0 2006.182.07:50:38.49#ibcon#end of sib2, iclass 13, count 0 2006.182.07:50:38.49#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:50:38.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:50:38.49#ibcon#[25=USB\r\n] 2006.182.07:50:38.49#ibcon#*before write, iclass 13, count 0 2006.182.07:50:38.49#ibcon#enter sib2, iclass 13, count 0 2006.182.07:50:38.49#ibcon#flushed, iclass 13, count 0 2006.182.07:50:38.49#ibcon#about to write, iclass 13, count 0 2006.182.07:50:38.49#ibcon#wrote, iclass 13, count 0 2006.182.07:50:38.49#ibcon#about to read 3, iclass 13, count 0 2006.182.07:50:38.52#ibcon#read 3, iclass 13, count 0 2006.182.07:50:38.52#ibcon#about to read 4, iclass 13, count 0 2006.182.07:50:38.52#ibcon#read 4, iclass 13, count 0 2006.182.07:50:38.52#ibcon#about to read 5, iclass 13, count 0 2006.182.07:50:38.52#ibcon#read 5, iclass 13, count 0 2006.182.07:50:38.52#ibcon#about to read 6, iclass 13, count 0 2006.182.07:50:38.52#ibcon#read 6, iclass 13, count 0 2006.182.07:50:38.52#ibcon#end of sib2, iclass 13, count 0 2006.182.07:50:38.52#ibcon#*after write, iclass 13, count 0 2006.182.07:50:38.52#ibcon#*before return 0, iclass 13, count 0 2006.182.07:50:38.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:38.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:38.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:50:38.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:50:38.52$vc4f8/valo=3,672.99 2006.182.07:50:38.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.07:50:38.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.07:50:38.52#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:38.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:38.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:38.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:38.52#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:50:38.52#ibcon#first serial, iclass 15, count 0 2006.182.07:50:38.52#ibcon#enter sib2, iclass 15, count 0 2006.182.07:50:38.52#ibcon#flushed, iclass 15, count 0 2006.182.07:50:38.52#ibcon#about to write, iclass 15, count 0 2006.182.07:50:38.52#ibcon#wrote, iclass 15, count 0 2006.182.07:50:38.52#ibcon#about to read 3, iclass 15, count 0 2006.182.07:50:38.54#ibcon#read 3, iclass 15, count 0 2006.182.07:50:38.54#ibcon#about to read 4, iclass 15, count 0 2006.182.07:50:38.54#ibcon#read 4, iclass 15, count 0 2006.182.07:50:38.54#ibcon#about to read 5, iclass 15, count 0 2006.182.07:50:38.54#ibcon#read 5, iclass 15, count 0 2006.182.07:50:38.54#ibcon#about to read 6, iclass 15, count 0 2006.182.07:50:38.54#ibcon#read 6, iclass 15, count 0 2006.182.07:50:38.54#ibcon#end of sib2, iclass 15, count 0 2006.182.07:50:38.54#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:50:38.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:50:38.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:50:38.54#ibcon#*before write, iclass 15, count 0 2006.182.07:50:38.54#ibcon#enter sib2, iclass 15, count 0 2006.182.07:50:38.54#ibcon#flushed, iclass 15, count 0 2006.182.07:50:38.54#ibcon#about to write, iclass 15, count 0 2006.182.07:50:38.54#ibcon#wrote, iclass 15, count 0 2006.182.07:50:38.54#ibcon#about to read 3, iclass 15, count 0 2006.182.07:50:38.58#ibcon#read 3, iclass 15, count 0 2006.182.07:50:38.58#ibcon#about to read 4, iclass 15, count 0 2006.182.07:50:38.58#ibcon#read 4, iclass 15, count 0 2006.182.07:50:38.58#ibcon#about to read 5, iclass 15, count 0 2006.182.07:50:38.58#ibcon#read 5, iclass 15, count 0 2006.182.07:50:38.58#ibcon#about to read 6, iclass 15, count 0 2006.182.07:50:38.58#ibcon#read 6, iclass 15, count 0 2006.182.07:50:38.58#ibcon#end of sib2, iclass 15, count 0 2006.182.07:50:38.58#ibcon#*after write, iclass 15, count 0 2006.182.07:50:38.58#ibcon#*before return 0, iclass 15, count 0 2006.182.07:50:38.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:38.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:38.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:50:38.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:50:38.58$vc4f8/va=3,6 2006.182.07:50:38.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.07:50:38.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.07:50:38.58#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:38.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:38.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:38.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:38.64#ibcon#enter wrdev, iclass 17, count 2 2006.182.07:50:38.64#ibcon#first serial, iclass 17, count 2 2006.182.07:50:38.64#ibcon#enter sib2, iclass 17, count 2 2006.182.07:50:38.64#ibcon#flushed, iclass 17, count 2 2006.182.07:50:38.64#ibcon#about to write, iclass 17, count 2 2006.182.07:50:38.64#ibcon#wrote, iclass 17, count 2 2006.182.07:50:38.64#ibcon#about to read 3, iclass 17, count 2 2006.182.07:50:38.66#ibcon#read 3, iclass 17, count 2 2006.182.07:50:38.66#ibcon#about to read 4, iclass 17, count 2 2006.182.07:50:38.66#ibcon#read 4, iclass 17, count 2 2006.182.07:50:38.66#ibcon#about to read 5, iclass 17, count 2 2006.182.07:50:38.66#ibcon#read 5, iclass 17, count 2 2006.182.07:50:38.66#ibcon#about to read 6, iclass 17, count 2 2006.182.07:50:38.66#ibcon#read 6, iclass 17, count 2 2006.182.07:50:38.66#ibcon#end of sib2, iclass 17, count 2 2006.182.07:50:38.66#ibcon#*mode == 0, iclass 17, count 2 2006.182.07:50:38.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.07:50:38.66#ibcon#[25=AT03-06\r\n] 2006.182.07:50:38.66#ibcon#*before write, iclass 17, count 2 2006.182.07:50:38.66#ibcon#enter sib2, iclass 17, count 2 2006.182.07:50:38.66#ibcon#flushed, iclass 17, count 2 2006.182.07:50:38.66#ibcon#about to write, iclass 17, count 2 2006.182.07:50:38.66#ibcon#wrote, iclass 17, count 2 2006.182.07:50:38.66#ibcon#about to read 3, iclass 17, count 2 2006.182.07:50:38.69#ibcon#read 3, iclass 17, count 2 2006.182.07:50:38.69#ibcon#about to read 4, iclass 17, count 2 2006.182.07:50:38.69#ibcon#read 4, iclass 17, count 2 2006.182.07:50:38.69#ibcon#about to read 5, iclass 17, count 2 2006.182.07:50:38.69#ibcon#read 5, iclass 17, count 2 2006.182.07:50:38.69#ibcon#about to read 6, iclass 17, count 2 2006.182.07:50:38.69#ibcon#read 6, iclass 17, count 2 2006.182.07:50:38.69#ibcon#end of sib2, iclass 17, count 2 2006.182.07:50:38.69#ibcon#*after write, iclass 17, count 2 2006.182.07:50:38.69#ibcon#*before return 0, iclass 17, count 2 2006.182.07:50:38.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:38.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:38.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.07:50:38.69#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:38.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:38.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:38.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:38.81#ibcon#enter wrdev, iclass 17, count 0 2006.182.07:50:38.81#ibcon#first serial, iclass 17, count 0 2006.182.07:50:38.81#ibcon#enter sib2, iclass 17, count 0 2006.182.07:50:38.81#ibcon#flushed, iclass 17, count 0 2006.182.07:50:38.81#ibcon#about to write, iclass 17, count 0 2006.182.07:50:38.81#ibcon#wrote, iclass 17, count 0 2006.182.07:50:38.81#ibcon#about to read 3, iclass 17, count 0 2006.182.07:50:38.83#ibcon#read 3, iclass 17, count 0 2006.182.07:50:38.83#ibcon#about to read 4, iclass 17, count 0 2006.182.07:50:38.83#ibcon#read 4, iclass 17, count 0 2006.182.07:50:38.83#ibcon#about to read 5, iclass 17, count 0 2006.182.07:50:38.83#ibcon#read 5, iclass 17, count 0 2006.182.07:50:38.83#ibcon#about to read 6, iclass 17, count 0 2006.182.07:50:38.83#ibcon#read 6, iclass 17, count 0 2006.182.07:50:38.83#ibcon#end of sib2, iclass 17, count 0 2006.182.07:50:38.83#ibcon#*mode == 0, iclass 17, count 0 2006.182.07:50:38.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.07:50:38.83#ibcon#[25=USB\r\n] 2006.182.07:50:38.83#ibcon#*before write, iclass 17, count 0 2006.182.07:50:38.83#ibcon#enter sib2, iclass 17, count 0 2006.182.07:50:38.83#ibcon#flushed, iclass 17, count 0 2006.182.07:50:38.83#ibcon#about to write, iclass 17, count 0 2006.182.07:50:38.83#ibcon#wrote, iclass 17, count 0 2006.182.07:50:38.83#ibcon#about to read 3, iclass 17, count 0 2006.182.07:50:38.86#ibcon#read 3, iclass 17, count 0 2006.182.07:50:38.86#ibcon#about to read 4, iclass 17, count 0 2006.182.07:50:38.86#ibcon#read 4, iclass 17, count 0 2006.182.07:50:38.86#ibcon#about to read 5, iclass 17, count 0 2006.182.07:50:38.86#ibcon#read 5, iclass 17, count 0 2006.182.07:50:38.86#ibcon#about to read 6, iclass 17, count 0 2006.182.07:50:38.86#ibcon#read 6, iclass 17, count 0 2006.182.07:50:38.86#ibcon#end of sib2, iclass 17, count 0 2006.182.07:50:38.86#ibcon#*after write, iclass 17, count 0 2006.182.07:50:38.86#ibcon#*before return 0, iclass 17, count 0 2006.182.07:50:38.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:38.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:38.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.07:50:38.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.07:50:38.86$vc4f8/valo=4,832.99 2006.182.07:50:38.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.07:50:38.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.07:50:38.86#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:38.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:38.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:38.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:38.86#ibcon#enter wrdev, iclass 19, count 0 2006.182.07:50:38.86#ibcon#first serial, iclass 19, count 0 2006.182.07:50:38.86#ibcon#enter sib2, iclass 19, count 0 2006.182.07:50:38.86#ibcon#flushed, iclass 19, count 0 2006.182.07:50:38.86#ibcon#about to write, iclass 19, count 0 2006.182.07:50:38.86#ibcon#wrote, iclass 19, count 0 2006.182.07:50:38.86#ibcon#about to read 3, iclass 19, count 0 2006.182.07:50:38.88#ibcon#read 3, iclass 19, count 0 2006.182.07:50:38.88#ibcon#about to read 4, iclass 19, count 0 2006.182.07:50:38.88#ibcon#read 4, iclass 19, count 0 2006.182.07:50:38.88#ibcon#about to read 5, iclass 19, count 0 2006.182.07:50:38.88#ibcon#read 5, iclass 19, count 0 2006.182.07:50:38.88#ibcon#about to read 6, iclass 19, count 0 2006.182.07:50:38.88#ibcon#read 6, iclass 19, count 0 2006.182.07:50:38.88#ibcon#end of sib2, iclass 19, count 0 2006.182.07:50:38.88#ibcon#*mode == 0, iclass 19, count 0 2006.182.07:50:38.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.07:50:38.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:50:38.88#ibcon#*before write, iclass 19, count 0 2006.182.07:50:38.88#ibcon#enter sib2, iclass 19, count 0 2006.182.07:50:38.88#ibcon#flushed, iclass 19, count 0 2006.182.07:50:38.88#ibcon#about to write, iclass 19, count 0 2006.182.07:50:38.88#ibcon#wrote, iclass 19, count 0 2006.182.07:50:38.88#ibcon#about to read 3, iclass 19, count 0 2006.182.07:50:38.92#ibcon#read 3, iclass 19, count 0 2006.182.07:50:38.92#ibcon#about to read 4, iclass 19, count 0 2006.182.07:50:38.92#ibcon#read 4, iclass 19, count 0 2006.182.07:50:38.92#ibcon#about to read 5, iclass 19, count 0 2006.182.07:50:38.92#ibcon#read 5, iclass 19, count 0 2006.182.07:50:38.92#ibcon#about to read 6, iclass 19, count 0 2006.182.07:50:38.92#ibcon#read 6, iclass 19, count 0 2006.182.07:50:38.92#ibcon#end of sib2, iclass 19, count 0 2006.182.07:50:38.92#ibcon#*after write, iclass 19, count 0 2006.182.07:50:38.92#ibcon#*before return 0, iclass 19, count 0 2006.182.07:50:38.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:38.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:38.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.07:50:38.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.07:50:38.92$vc4f8/va=4,7 2006.182.07:50:38.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.07:50:38.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.07:50:38.92#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:38.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:38.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:38.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:38.98#ibcon#enter wrdev, iclass 21, count 2 2006.182.07:50:38.98#ibcon#first serial, iclass 21, count 2 2006.182.07:50:38.98#ibcon#enter sib2, iclass 21, count 2 2006.182.07:50:38.98#ibcon#flushed, iclass 21, count 2 2006.182.07:50:38.98#ibcon#about to write, iclass 21, count 2 2006.182.07:50:38.98#ibcon#wrote, iclass 21, count 2 2006.182.07:50:38.98#ibcon#about to read 3, iclass 21, count 2 2006.182.07:50:39.00#ibcon#read 3, iclass 21, count 2 2006.182.07:50:39.00#ibcon#about to read 4, iclass 21, count 2 2006.182.07:50:39.00#ibcon#read 4, iclass 21, count 2 2006.182.07:50:39.00#ibcon#about to read 5, iclass 21, count 2 2006.182.07:50:39.00#ibcon#read 5, iclass 21, count 2 2006.182.07:50:39.00#ibcon#about to read 6, iclass 21, count 2 2006.182.07:50:39.00#ibcon#read 6, iclass 21, count 2 2006.182.07:50:39.00#ibcon#end of sib2, iclass 21, count 2 2006.182.07:50:39.00#ibcon#*mode == 0, iclass 21, count 2 2006.182.07:50:39.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.07:50:39.00#ibcon#[25=AT04-07\r\n] 2006.182.07:50:39.00#ibcon#*before write, iclass 21, count 2 2006.182.07:50:39.00#ibcon#enter sib2, iclass 21, count 2 2006.182.07:50:39.00#ibcon#flushed, iclass 21, count 2 2006.182.07:50:39.00#ibcon#about to write, iclass 21, count 2 2006.182.07:50:39.00#ibcon#wrote, iclass 21, count 2 2006.182.07:50:39.00#ibcon#about to read 3, iclass 21, count 2 2006.182.07:50:39.03#ibcon#read 3, iclass 21, count 2 2006.182.07:50:39.03#ibcon#about to read 4, iclass 21, count 2 2006.182.07:50:39.03#ibcon#read 4, iclass 21, count 2 2006.182.07:50:39.03#ibcon#about to read 5, iclass 21, count 2 2006.182.07:50:39.03#ibcon#read 5, iclass 21, count 2 2006.182.07:50:39.03#ibcon#about to read 6, iclass 21, count 2 2006.182.07:50:39.03#ibcon#read 6, iclass 21, count 2 2006.182.07:50:39.03#ibcon#end of sib2, iclass 21, count 2 2006.182.07:50:39.03#ibcon#*after write, iclass 21, count 2 2006.182.07:50:39.03#ibcon#*before return 0, iclass 21, count 2 2006.182.07:50:39.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:39.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:39.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.07:50:39.03#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:39.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:39.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:39.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:39.15#ibcon#enter wrdev, iclass 21, count 0 2006.182.07:50:39.15#ibcon#first serial, iclass 21, count 0 2006.182.07:50:39.15#ibcon#enter sib2, iclass 21, count 0 2006.182.07:50:39.15#ibcon#flushed, iclass 21, count 0 2006.182.07:50:39.15#ibcon#about to write, iclass 21, count 0 2006.182.07:50:39.15#ibcon#wrote, iclass 21, count 0 2006.182.07:50:39.15#ibcon#about to read 3, iclass 21, count 0 2006.182.07:50:39.17#ibcon#read 3, iclass 21, count 0 2006.182.07:50:39.17#ibcon#about to read 4, iclass 21, count 0 2006.182.07:50:39.17#ibcon#read 4, iclass 21, count 0 2006.182.07:50:39.17#ibcon#about to read 5, iclass 21, count 0 2006.182.07:50:39.17#ibcon#read 5, iclass 21, count 0 2006.182.07:50:39.17#ibcon#about to read 6, iclass 21, count 0 2006.182.07:50:39.17#ibcon#read 6, iclass 21, count 0 2006.182.07:50:39.17#ibcon#end of sib2, iclass 21, count 0 2006.182.07:50:39.17#ibcon#*mode == 0, iclass 21, count 0 2006.182.07:50:39.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.07:50:39.17#ibcon#[25=USB\r\n] 2006.182.07:50:39.17#ibcon#*before write, iclass 21, count 0 2006.182.07:50:39.17#ibcon#enter sib2, iclass 21, count 0 2006.182.07:50:39.17#ibcon#flushed, iclass 21, count 0 2006.182.07:50:39.17#ibcon#about to write, iclass 21, count 0 2006.182.07:50:39.17#ibcon#wrote, iclass 21, count 0 2006.182.07:50:39.17#ibcon#about to read 3, iclass 21, count 0 2006.182.07:50:39.20#ibcon#read 3, iclass 21, count 0 2006.182.07:50:39.20#ibcon#about to read 4, iclass 21, count 0 2006.182.07:50:39.20#ibcon#read 4, iclass 21, count 0 2006.182.07:50:39.20#ibcon#about to read 5, iclass 21, count 0 2006.182.07:50:39.20#ibcon#read 5, iclass 21, count 0 2006.182.07:50:39.20#ibcon#about to read 6, iclass 21, count 0 2006.182.07:50:39.20#ibcon#read 6, iclass 21, count 0 2006.182.07:50:39.20#ibcon#end of sib2, iclass 21, count 0 2006.182.07:50:39.20#ibcon#*after write, iclass 21, count 0 2006.182.07:50:39.20#ibcon#*before return 0, iclass 21, count 0 2006.182.07:50:39.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:39.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:39.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.07:50:39.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.07:50:39.20$vc4f8/valo=5,652.99 2006.182.07:50:39.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.07:50:39.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.07:50:39.20#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:39.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:39.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:39.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:39.20#ibcon#enter wrdev, iclass 23, count 0 2006.182.07:50:39.20#ibcon#first serial, iclass 23, count 0 2006.182.07:50:39.20#ibcon#enter sib2, iclass 23, count 0 2006.182.07:50:39.20#ibcon#flushed, iclass 23, count 0 2006.182.07:50:39.20#ibcon#about to write, iclass 23, count 0 2006.182.07:50:39.20#ibcon#wrote, iclass 23, count 0 2006.182.07:50:39.20#ibcon#about to read 3, iclass 23, count 0 2006.182.07:50:39.22#ibcon#read 3, iclass 23, count 0 2006.182.07:50:39.22#ibcon#about to read 4, iclass 23, count 0 2006.182.07:50:39.22#ibcon#read 4, iclass 23, count 0 2006.182.07:50:39.22#ibcon#about to read 5, iclass 23, count 0 2006.182.07:50:39.22#ibcon#read 5, iclass 23, count 0 2006.182.07:50:39.22#ibcon#about to read 6, iclass 23, count 0 2006.182.07:50:39.22#ibcon#read 6, iclass 23, count 0 2006.182.07:50:39.22#ibcon#end of sib2, iclass 23, count 0 2006.182.07:50:39.22#ibcon#*mode == 0, iclass 23, count 0 2006.182.07:50:39.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.07:50:39.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:50:39.22#ibcon#*before write, iclass 23, count 0 2006.182.07:50:39.22#ibcon#enter sib2, iclass 23, count 0 2006.182.07:50:39.22#ibcon#flushed, iclass 23, count 0 2006.182.07:50:39.22#ibcon#about to write, iclass 23, count 0 2006.182.07:50:39.22#ibcon#wrote, iclass 23, count 0 2006.182.07:50:39.22#ibcon#about to read 3, iclass 23, count 0 2006.182.07:50:39.26#ibcon#read 3, iclass 23, count 0 2006.182.07:50:39.26#ibcon#about to read 4, iclass 23, count 0 2006.182.07:50:39.26#ibcon#read 4, iclass 23, count 0 2006.182.07:50:39.26#ibcon#about to read 5, iclass 23, count 0 2006.182.07:50:39.26#ibcon#read 5, iclass 23, count 0 2006.182.07:50:39.26#ibcon#about to read 6, iclass 23, count 0 2006.182.07:50:39.26#ibcon#read 6, iclass 23, count 0 2006.182.07:50:39.26#ibcon#end of sib2, iclass 23, count 0 2006.182.07:50:39.26#ibcon#*after write, iclass 23, count 0 2006.182.07:50:39.26#ibcon#*before return 0, iclass 23, count 0 2006.182.07:50:39.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:39.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:39.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.07:50:39.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.07:50:39.26$vc4f8/va=5,7 2006.182.07:50:39.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.07:50:39.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.07:50:39.26#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:39.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:39.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:39.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:39.32#ibcon#enter wrdev, iclass 25, count 2 2006.182.07:50:39.32#ibcon#first serial, iclass 25, count 2 2006.182.07:50:39.32#ibcon#enter sib2, iclass 25, count 2 2006.182.07:50:39.32#ibcon#flushed, iclass 25, count 2 2006.182.07:50:39.32#ibcon#about to write, iclass 25, count 2 2006.182.07:50:39.32#ibcon#wrote, iclass 25, count 2 2006.182.07:50:39.32#ibcon#about to read 3, iclass 25, count 2 2006.182.07:50:39.34#ibcon#read 3, iclass 25, count 2 2006.182.07:50:39.34#ibcon#about to read 4, iclass 25, count 2 2006.182.07:50:39.34#ibcon#read 4, iclass 25, count 2 2006.182.07:50:39.34#ibcon#about to read 5, iclass 25, count 2 2006.182.07:50:39.34#ibcon#read 5, iclass 25, count 2 2006.182.07:50:39.34#ibcon#about to read 6, iclass 25, count 2 2006.182.07:50:39.34#ibcon#read 6, iclass 25, count 2 2006.182.07:50:39.34#ibcon#end of sib2, iclass 25, count 2 2006.182.07:50:39.34#ibcon#*mode == 0, iclass 25, count 2 2006.182.07:50:39.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.07:50:39.34#ibcon#[25=AT05-07\r\n] 2006.182.07:50:39.34#ibcon#*before write, iclass 25, count 2 2006.182.07:50:39.34#ibcon#enter sib2, iclass 25, count 2 2006.182.07:50:39.34#ibcon#flushed, iclass 25, count 2 2006.182.07:50:39.34#ibcon#about to write, iclass 25, count 2 2006.182.07:50:39.34#ibcon#wrote, iclass 25, count 2 2006.182.07:50:39.34#ibcon#about to read 3, iclass 25, count 2 2006.182.07:50:39.37#ibcon#read 3, iclass 25, count 2 2006.182.07:50:39.37#ibcon#about to read 4, iclass 25, count 2 2006.182.07:50:39.37#ibcon#read 4, iclass 25, count 2 2006.182.07:50:39.37#ibcon#about to read 5, iclass 25, count 2 2006.182.07:50:39.37#ibcon#read 5, iclass 25, count 2 2006.182.07:50:39.37#ibcon#about to read 6, iclass 25, count 2 2006.182.07:50:39.37#ibcon#read 6, iclass 25, count 2 2006.182.07:50:39.37#ibcon#end of sib2, iclass 25, count 2 2006.182.07:50:39.37#ibcon#*after write, iclass 25, count 2 2006.182.07:50:39.37#ibcon#*before return 0, iclass 25, count 2 2006.182.07:50:39.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:39.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:39.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.07:50:39.37#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:39.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:39.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:39.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:39.49#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:50:39.49#ibcon#first serial, iclass 25, count 0 2006.182.07:50:39.49#ibcon#enter sib2, iclass 25, count 0 2006.182.07:50:39.49#ibcon#flushed, iclass 25, count 0 2006.182.07:50:39.49#ibcon#about to write, iclass 25, count 0 2006.182.07:50:39.49#ibcon#wrote, iclass 25, count 0 2006.182.07:50:39.49#ibcon#about to read 3, iclass 25, count 0 2006.182.07:50:39.51#ibcon#read 3, iclass 25, count 0 2006.182.07:50:39.51#ibcon#about to read 4, iclass 25, count 0 2006.182.07:50:39.51#ibcon#read 4, iclass 25, count 0 2006.182.07:50:39.51#ibcon#about to read 5, iclass 25, count 0 2006.182.07:50:39.51#ibcon#read 5, iclass 25, count 0 2006.182.07:50:39.51#ibcon#about to read 6, iclass 25, count 0 2006.182.07:50:39.51#ibcon#read 6, iclass 25, count 0 2006.182.07:50:39.51#ibcon#end of sib2, iclass 25, count 0 2006.182.07:50:39.51#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:50:39.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:50:39.51#ibcon#[25=USB\r\n] 2006.182.07:50:39.51#ibcon#*before write, iclass 25, count 0 2006.182.07:50:39.51#ibcon#enter sib2, iclass 25, count 0 2006.182.07:50:39.51#ibcon#flushed, iclass 25, count 0 2006.182.07:50:39.51#ibcon#about to write, iclass 25, count 0 2006.182.07:50:39.51#ibcon#wrote, iclass 25, count 0 2006.182.07:50:39.51#ibcon#about to read 3, iclass 25, count 0 2006.182.07:50:39.54#ibcon#read 3, iclass 25, count 0 2006.182.07:50:39.54#ibcon#about to read 4, iclass 25, count 0 2006.182.07:50:39.54#ibcon#read 4, iclass 25, count 0 2006.182.07:50:39.54#ibcon#about to read 5, iclass 25, count 0 2006.182.07:50:39.54#ibcon#read 5, iclass 25, count 0 2006.182.07:50:39.54#ibcon#about to read 6, iclass 25, count 0 2006.182.07:50:39.54#ibcon#read 6, iclass 25, count 0 2006.182.07:50:39.54#ibcon#end of sib2, iclass 25, count 0 2006.182.07:50:39.54#ibcon#*after write, iclass 25, count 0 2006.182.07:50:39.54#ibcon#*before return 0, iclass 25, count 0 2006.182.07:50:39.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:39.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:39.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:50:39.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:50:39.54$vc4f8/valo=6,772.99 2006.182.07:50:39.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.07:50:39.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.07:50:39.54#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:39.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:39.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:39.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:39.54#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:50:39.54#ibcon#first serial, iclass 27, count 0 2006.182.07:50:39.54#ibcon#enter sib2, iclass 27, count 0 2006.182.07:50:39.54#ibcon#flushed, iclass 27, count 0 2006.182.07:50:39.54#ibcon#about to write, iclass 27, count 0 2006.182.07:50:39.54#ibcon#wrote, iclass 27, count 0 2006.182.07:50:39.54#ibcon#about to read 3, iclass 27, count 0 2006.182.07:50:39.56#ibcon#read 3, iclass 27, count 0 2006.182.07:50:39.56#ibcon#about to read 4, iclass 27, count 0 2006.182.07:50:39.56#ibcon#read 4, iclass 27, count 0 2006.182.07:50:39.56#ibcon#about to read 5, iclass 27, count 0 2006.182.07:50:39.56#ibcon#read 5, iclass 27, count 0 2006.182.07:50:39.56#ibcon#about to read 6, iclass 27, count 0 2006.182.07:50:39.56#ibcon#read 6, iclass 27, count 0 2006.182.07:50:39.56#ibcon#end of sib2, iclass 27, count 0 2006.182.07:50:39.56#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:50:39.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:50:39.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:50:39.56#ibcon#*before write, iclass 27, count 0 2006.182.07:50:39.56#ibcon#enter sib2, iclass 27, count 0 2006.182.07:50:39.56#ibcon#flushed, iclass 27, count 0 2006.182.07:50:39.56#ibcon#about to write, iclass 27, count 0 2006.182.07:50:39.56#ibcon#wrote, iclass 27, count 0 2006.182.07:50:39.56#ibcon#about to read 3, iclass 27, count 0 2006.182.07:50:39.60#ibcon#read 3, iclass 27, count 0 2006.182.07:50:39.60#ibcon#about to read 4, iclass 27, count 0 2006.182.07:50:39.60#ibcon#read 4, iclass 27, count 0 2006.182.07:50:39.60#ibcon#about to read 5, iclass 27, count 0 2006.182.07:50:39.60#ibcon#read 5, iclass 27, count 0 2006.182.07:50:39.60#ibcon#about to read 6, iclass 27, count 0 2006.182.07:50:39.60#ibcon#read 6, iclass 27, count 0 2006.182.07:50:39.60#ibcon#end of sib2, iclass 27, count 0 2006.182.07:50:39.60#ibcon#*after write, iclass 27, count 0 2006.182.07:50:39.60#ibcon#*before return 0, iclass 27, count 0 2006.182.07:50:39.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:39.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:39.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:50:39.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:50:39.60$vc4f8/va=6,6 2006.182.07:50:39.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.07:50:39.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.07:50:39.60#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:39.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:50:39.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:50:39.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:50:39.66#ibcon#enter wrdev, iclass 29, count 2 2006.182.07:50:39.66#ibcon#first serial, iclass 29, count 2 2006.182.07:50:39.66#ibcon#enter sib2, iclass 29, count 2 2006.182.07:50:39.66#ibcon#flushed, iclass 29, count 2 2006.182.07:50:39.66#ibcon#about to write, iclass 29, count 2 2006.182.07:50:39.66#ibcon#wrote, iclass 29, count 2 2006.182.07:50:39.66#ibcon#about to read 3, iclass 29, count 2 2006.182.07:50:39.68#ibcon#read 3, iclass 29, count 2 2006.182.07:50:39.68#ibcon#about to read 4, iclass 29, count 2 2006.182.07:50:39.68#ibcon#read 4, iclass 29, count 2 2006.182.07:50:39.68#ibcon#about to read 5, iclass 29, count 2 2006.182.07:50:39.68#ibcon#read 5, iclass 29, count 2 2006.182.07:50:39.68#ibcon#about to read 6, iclass 29, count 2 2006.182.07:50:39.68#ibcon#read 6, iclass 29, count 2 2006.182.07:50:39.68#ibcon#end of sib2, iclass 29, count 2 2006.182.07:50:39.68#ibcon#*mode == 0, iclass 29, count 2 2006.182.07:50:39.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.07:50:39.68#ibcon#[25=AT06-06\r\n] 2006.182.07:50:39.68#ibcon#*before write, iclass 29, count 2 2006.182.07:50:39.68#ibcon#enter sib2, iclass 29, count 2 2006.182.07:50:39.68#ibcon#flushed, iclass 29, count 2 2006.182.07:50:39.68#ibcon#about to write, iclass 29, count 2 2006.182.07:50:39.68#ibcon#wrote, iclass 29, count 2 2006.182.07:50:39.68#ibcon#about to read 3, iclass 29, count 2 2006.182.07:50:39.71#ibcon#read 3, iclass 29, count 2 2006.182.07:50:39.71#ibcon#about to read 4, iclass 29, count 2 2006.182.07:50:39.71#ibcon#read 4, iclass 29, count 2 2006.182.07:50:39.71#ibcon#about to read 5, iclass 29, count 2 2006.182.07:50:39.71#ibcon#read 5, iclass 29, count 2 2006.182.07:50:39.71#ibcon#about to read 6, iclass 29, count 2 2006.182.07:50:39.71#ibcon#read 6, iclass 29, count 2 2006.182.07:50:39.71#ibcon#end of sib2, iclass 29, count 2 2006.182.07:50:39.71#ibcon#*after write, iclass 29, count 2 2006.182.07:50:39.71#ibcon#*before return 0, iclass 29, count 2 2006.182.07:50:39.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:50:39.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.07:50:39.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.07:50:39.71#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:39.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:50:39.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:50:39.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:50:39.83#ibcon#enter wrdev, iclass 29, count 0 2006.182.07:50:39.83#ibcon#first serial, iclass 29, count 0 2006.182.07:50:39.83#ibcon#enter sib2, iclass 29, count 0 2006.182.07:50:39.83#ibcon#flushed, iclass 29, count 0 2006.182.07:50:39.83#ibcon#about to write, iclass 29, count 0 2006.182.07:50:39.83#ibcon#wrote, iclass 29, count 0 2006.182.07:50:39.83#ibcon#about to read 3, iclass 29, count 0 2006.182.07:50:39.85#ibcon#read 3, iclass 29, count 0 2006.182.07:50:39.85#ibcon#about to read 4, iclass 29, count 0 2006.182.07:50:39.85#ibcon#read 4, iclass 29, count 0 2006.182.07:50:39.85#ibcon#about to read 5, iclass 29, count 0 2006.182.07:50:39.85#ibcon#read 5, iclass 29, count 0 2006.182.07:50:39.85#ibcon#about to read 6, iclass 29, count 0 2006.182.07:50:39.85#ibcon#read 6, iclass 29, count 0 2006.182.07:50:39.85#ibcon#end of sib2, iclass 29, count 0 2006.182.07:50:39.85#ibcon#*mode == 0, iclass 29, count 0 2006.182.07:50:39.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.07:50:39.85#ibcon#[25=USB\r\n] 2006.182.07:50:39.85#ibcon#*before write, iclass 29, count 0 2006.182.07:50:39.85#ibcon#enter sib2, iclass 29, count 0 2006.182.07:50:39.85#ibcon#flushed, iclass 29, count 0 2006.182.07:50:39.85#ibcon#about to write, iclass 29, count 0 2006.182.07:50:39.85#ibcon#wrote, iclass 29, count 0 2006.182.07:50:39.85#ibcon#about to read 3, iclass 29, count 0 2006.182.07:50:39.88#ibcon#read 3, iclass 29, count 0 2006.182.07:50:39.88#ibcon#about to read 4, iclass 29, count 0 2006.182.07:50:39.88#ibcon#read 4, iclass 29, count 0 2006.182.07:50:39.88#ibcon#about to read 5, iclass 29, count 0 2006.182.07:50:39.88#ibcon#read 5, iclass 29, count 0 2006.182.07:50:39.88#ibcon#about to read 6, iclass 29, count 0 2006.182.07:50:39.88#ibcon#read 6, iclass 29, count 0 2006.182.07:50:39.88#ibcon#end of sib2, iclass 29, count 0 2006.182.07:50:39.88#ibcon#*after write, iclass 29, count 0 2006.182.07:50:39.88#ibcon#*before return 0, iclass 29, count 0 2006.182.07:50:39.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:50:39.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.07:50:39.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.07:50:39.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.07:50:39.88$vc4f8/valo=7,832.99 2006.182.07:50:39.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.07:50:39.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.07:50:39.88#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:39.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:50:39.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:50:39.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:50:39.88#ibcon#enter wrdev, iclass 31, count 0 2006.182.07:50:39.88#ibcon#first serial, iclass 31, count 0 2006.182.07:50:39.88#ibcon#enter sib2, iclass 31, count 0 2006.182.07:50:39.88#ibcon#flushed, iclass 31, count 0 2006.182.07:50:39.88#ibcon#about to write, iclass 31, count 0 2006.182.07:50:39.88#ibcon#wrote, iclass 31, count 0 2006.182.07:50:39.88#ibcon#about to read 3, iclass 31, count 0 2006.182.07:50:39.90#ibcon#read 3, iclass 31, count 0 2006.182.07:50:39.90#ibcon#about to read 4, iclass 31, count 0 2006.182.07:50:39.90#ibcon#read 4, iclass 31, count 0 2006.182.07:50:39.90#ibcon#about to read 5, iclass 31, count 0 2006.182.07:50:39.90#ibcon#read 5, iclass 31, count 0 2006.182.07:50:39.90#ibcon#about to read 6, iclass 31, count 0 2006.182.07:50:39.90#ibcon#read 6, iclass 31, count 0 2006.182.07:50:39.90#ibcon#end of sib2, iclass 31, count 0 2006.182.07:50:39.90#ibcon#*mode == 0, iclass 31, count 0 2006.182.07:50:39.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.07:50:39.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:50:39.90#ibcon#*before write, iclass 31, count 0 2006.182.07:50:39.90#ibcon#enter sib2, iclass 31, count 0 2006.182.07:50:39.90#ibcon#flushed, iclass 31, count 0 2006.182.07:50:39.90#ibcon#about to write, iclass 31, count 0 2006.182.07:50:39.90#ibcon#wrote, iclass 31, count 0 2006.182.07:50:39.90#ibcon#about to read 3, iclass 31, count 0 2006.182.07:50:39.94#ibcon#read 3, iclass 31, count 0 2006.182.07:50:39.94#ibcon#about to read 4, iclass 31, count 0 2006.182.07:50:39.94#ibcon#read 4, iclass 31, count 0 2006.182.07:50:39.94#ibcon#about to read 5, iclass 31, count 0 2006.182.07:50:39.94#ibcon#read 5, iclass 31, count 0 2006.182.07:50:39.94#ibcon#about to read 6, iclass 31, count 0 2006.182.07:50:39.94#ibcon#read 6, iclass 31, count 0 2006.182.07:50:39.94#ibcon#end of sib2, iclass 31, count 0 2006.182.07:50:39.94#ibcon#*after write, iclass 31, count 0 2006.182.07:50:39.94#ibcon#*before return 0, iclass 31, count 0 2006.182.07:50:39.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:50:39.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.07:50:39.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.07:50:39.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.07:50:39.94$vc4f8/va=7,6 2006.182.07:50:39.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.07:50:39.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.07:50:39.94#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:39.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:50:40.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:50:40.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:50:40.00#ibcon#enter wrdev, iclass 33, count 2 2006.182.07:50:40.00#ibcon#first serial, iclass 33, count 2 2006.182.07:50:40.00#ibcon#enter sib2, iclass 33, count 2 2006.182.07:50:40.00#ibcon#flushed, iclass 33, count 2 2006.182.07:50:40.00#ibcon#about to write, iclass 33, count 2 2006.182.07:50:40.00#ibcon#wrote, iclass 33, count 2 2006.182.07:50:40.00#ibcon#about to read 3, iclass 33, count 2 2006.182.07:50:40.02#ibcon#read 3, iclass 33, count 2 2006.182.07:50:40.02#ibcon#about to read 4, iclass 33, count 2 2006.182.07:50:40.02#ibcon#read 4, iclass 33, count 2 2006.182.07:50:40.02#ibcon#about to read 5, iclass 33, count 2 2006.182.07:50:40.02#ibcon#read 5, iclass 33, count 2 2006.182.07:50:40.02#ibcon#about to read 6, iclass 33, count 2 2006.182.07:50:40.02#ibcon#read 6, iclass 33, count 2 2006.182.07:50:40.02#ibcon#end of sib2, iclass 33, count 2 2006.182.07:50:40.02#ibcon#*mode == 0, iclass 33, count 2 2006.182.07:50:40.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.07:50:40.02#ibcon#[25=AT07-06\r\n] 2006.182.07:50:40.02#ibcon#*before write, iclass 33, count 2 2006.182.07:50:40.02#ibcon#enter sib2, iclass 33, count 2 2006.182.07:50:40.02#ibcon#flushed, iclass 33, count 2 2006.182.07:50:40.02#ibcon#about to write, iclass 33, count 2 2006.182.07:50:40.02#ibcon#wrote, iclass 33, count 2 2006.182.07:50:40.02#ibcon#about to read 3, iclass 33, count 2 2006.182.07:50:40.05#ibcon#read 3, iclass 33, count 2 2006.182.07:50:40.05#ibcon#about to read 4, iclass 33, count 2 2006.182.07:50:40.05#ibcon#read 4, iclass 33, count 2 2006.182.07:50:40.05#ibcon#about to read 5, iclass 33, count 2 2006.182.07:50:40.05#ibcon#read 5, iclass 33, count 2 2006.182.07:50:40.05#ibcon#about to read 6, iclass 33, count 2 2006.182.07:50:40.05#ibcon#read 6, iclass 33, count 2 2006.182.07:50:40.05#ibcon#end of sib2, iclass 33, count 2 2006.182.07:50:40.05#ibcon#*after write, iclass 33, count 2 2006.182.07:50:40.05#ibcon#*before return 0, iclass 33, count 2 2006.182.07:50:40.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:50:40.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.07:50:40.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.07:50:40.05#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:40.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:50:40.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:50:40.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:50:40.17#ibcon#enter wrdev, iclass 33, count 0 2006.182.07:50:40.17#ibcon#first serial, iclass 33, count 0 2006.182.07:50:40.17#ibcon#enter sib2, iclass 33, count 0 2006.182.07:50:40.17#ibcon#flushed, iclass 33, count 0 2006.182.07:50:40.17#ibcon#about to write, iclass 33, count 0 2006.182.07:50:40.17#ibcon#wrote, iclass 33, count 0 2006.182.07:50:40.17#ibcon#about to read 3, iclass 33, count 0 2006.182.07:50:40.19#ibcon#read 3, iclass 33, count 0 2006.182.07:50:40.19#ibcon#about to read 4, iclass 33, count 0 2006.182.07:50:40.19#ibcon#read 4, iclass 33, count 0 2006.182.07:50:40.19#ibcon#about to read 5, iclass 33, count 0 2006.182.07:50:40.19#ibcon#read 5, iclass 33, count 0 2006.182.07:50:40.19#ibcon#about to read 6, iclass 33, count 0 2006.182.07:50:40.19#ibcon#read 6, iclass 33, count 0 2006.182.07:50:40.19#ibcon#end of sib2, iclass 33, count 0 2006.182.07:50:40.19#ibcon#*mode == 0, iclass 33, count 0 2006.182.07:50:40.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.07:50:40.19#ibcon#[25=USB\r\n] 2006.182.07:50:40.19#ibcon#*before write, iclass 33, count 0 2006.182.07:50:40.19#ibcon#enter sib2, iclass 33, count 0 2006.182.07:50:40.19#ibcon#flushed, iclass 33, count 0 2006.182.07:50:40.19#ibcon#about to write, iclass 33, count 0 2006.182.07:50:40.19#ibcon#wrote, iclass 33, count 0 2006.182.07:50:40.19#ibcon#about to read 3, iclass 33, count 0 2006.182.07:50:40.22#ibcon#read 3, iclass 33, count 0 2006.182.07:50:40.22#ibcon#about to read 4, iclass 33, count 0 2006.182.07:50:40.22#ibcon#read 4, iclass 33, count 0 2006.182.07:50:40.22#ibcon#about to read 5, iclass 33, count 0 2006.182.07:50:40.22#ibcon#read 5, iclass 33, count 0 2006.182.07:50:40.22#ibcon#about to read 6, iclass 33, count 0 2006.182.07:50:40.22#ibcon#read 6, iclass 33, count 0 2006.182.07:50:40.22#ibcon#end of sib2, iclass 33, count 0 2006.182.07:50:40.22#ibcon#*after write, iclass 33, count 0 2006.182.07:50:40.22#ibcon#*before return 0, iclass 33, count 0 2006.182.07:50:40.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:50:40.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.07:50:40.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.07:50:40.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.07:50:40.22$vc4f8/valo=8,852.99 2006.182.07:50:40.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.07:50:40.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.07:50:40.22#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:40.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:50:40.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:50:40.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:50:40.22#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:50:40.22#ibcon#first serial, iclass 35, count 0 2006.182.07:50:40.22#ibcon#enter sib2, iclass 35, count 0 2006.182.07:50:40.22#ibcon#flushed, iclass 35, count 0 2006.182.07:50:40.22#ibcon#about to write, iclass 35, count 0 2006.182.07:50:40.22#ibcon#wrote, iclass 35, count 0 2006.182.07:50:40.22#ibcon#about to read 3, iclass 35, count 0 2006.182.07:50:40.24#ibcon#read 3, iclass 35, count 0 2006.182.07:50:40.24#ibcon#about to read 4, iclass 35, count 0 2006.182.07:50:40.24#ibcon#read 4, iclass 35, count 0 2006.182.07:50:40.24#ibcon#about to read 5, iclass 35, count 0 2006.182.07:50:40.24#ibcon#read 5, iclass 35, count 0 2006.182.07:50:40.24#ibcon#about to read 6, iclass 35, count 0 2006.182.07:50:40.24#ibcon#read 6, iclass 35, count 0 2006.182.07:50:40.24#ibcon#end of sib2, iclass 35, count 0 2006.182.07:50:40.24#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:50:40.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:50:40.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:50:40.24#ibcon#*before write, iclass 35, count 0 2006.182.07:50:40.24#ibcon#enter sib2, iclass 35, count 0 2006.182.07:50:40.24#ibcon#flushed, iclass 35, count 0 2006.182.07:50:40.24#ibcon#about to write, iclass 35, count 0 2006.182.07:50:40.24#ibcon#wrote, iclass 35, count 0 2006.182.07:50:40.24#ibcon#about to read 3, iclass 35, count 0 2006.182.07:50:40.28#ibcon#read 3, iclass 35, count 0 2006.182.07:50:40.28#ibcon#about to read 4, iclass 35, count 0 2006.182.07:50:40.28#ibcon#read 4, iclass 35, count 0 2006.182.07:50:40.28#ibcon#about to read 5, iclass 35, count 0 2006.182.07:50:40.28#ibcon#read 5, iclass 35, count 0 2006.182.07:50:40.28#ibcon#about to read 6, iclass 35, count 0 2006.182.07:50:40.28#ibcon#read 6, iclass 35, count 0 2006.182.07:50:40.28#ibcon#end of sib2, iclass 35, count 0 2006.182.07:50:40.28#ibcon#*after write, iclass 35, count 0 2006.182.07:50:40.28#ibcon#*before return 0, iclass 35, count 0 2006.182.07:50:40.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:50:40.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:50:40.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:50:40.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:50:40.28$vc4f8/va=8,7 2006.182.07:50:40.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.07:50:40.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.07:50:40.28#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:40.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:50:40.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:50:40.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:50:40.34#ibcon#enter wrdev, iclass 37, count 2 2006.182.07:50:40.34#ibcon#first serial, iclass 37, count 2 2006.182.07:50:40.34#ibcon#enter sib2, iclass 37, count 2 2006.182.07:50:40.34#ibcon#flushed, iclass 37, count 2 2006.182.07:50:40.34#ibcon#about to write, iclass 37, count 2 2006.182.07:50:40.34#ibcon#wrote, iclass 37, count 2 2006.182.07:50:40.34#ibcon#about to read 3, iclass 37, count 2 2006.182.07:50:40.36#ibcon#read 3, iclass 37, count 2 2006.182.07:50:40.36#ibcon#about to read 4, iclass 37, count 2 2006.182.07:50:40.36#ibcon#read 4, iclass 37, count 2 2006.182.07:50:40.36#ibcon#about to read 5, iclass 37, count 2 2006.182.07:50:40.36#ibcon#read 5, iclass 37, count 2 2006.182.07:50:40.36#ibcon#about to read 6, iclass 37, count 2 2006.182.07:50:40.36#ibcon#read 6, iclass 37, count 2 2006.182.07:50:40.36#ibcon#end of sib2, iclass 37, count 2 2006.182.07:50:40.36#ibcon#*mode == 0, iclass 37, count 2 2006.182.07:50:40.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.07:50:40.36#ibcon#[25=AT08-07\r\n] 2006.182.07:50:40.36#ibcon#*before write, iclass 37, count 2 2006.182.07:50:40.36#ibcon#enter sib2, iclass 37, count 2 2006.182.07:50:40.36#ibcon#flushed, iclass 37, count 2 2006.182.07:50:40.36#ibcon#about to write, iclass 37, count 2 2006.182.07:50:40.36#ibcon#wrote, iclass 37, count 2 2006.182.07:50:40.36#ibcon#about to read 3, iclass 37, count 2 2006.182.07:50:40.39#ibcon#read 3, iclass 37, count 2 2006.182.07:50:40.39#ibcon#about to read 4, iclass 37, count 2 2006.182.07:50:40.39#ibcon#read 4, iclass 37, count 2 2006.182.07:50:40.39#ibcon#about to read 5, iclass 37, count 2 2006.182.07:50:40.39#ibcon#read 5, iclass 37, count 2 2006.182.07:50:40.39#ibcon#about to read 6, iclass 37, count 2 2006.182.07:50:40.39#ibcon#read 6, iclass 37, count 2 2006.182.07:50:40.39#ibcon#end of sib2, iclass 37, count 2 2006.182.07:50:40.39#ibcon#*after write, iclass 37, count 2 2006.182.07:50:40.39#ibcon#*before return 0, iclass 37, count 2 2006.182.07:50:40.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:50:40.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.07:50:40.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.07:50:40.39#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:40.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:50:40.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:50:40.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:50:40.51#ibcon#enter wrdev, iclass 37, count 0 2006.182.07:50:40.51#ibcon#first serial, iclass 37, count 0 2006.182.07:50:40.51#ibcon#enter sib2, iclass 37, count 0 2006.182.07:50:40.51#ibcon#flushed, iclass 37, count 0 2006.182.07:50:40.51#ibcon#about to write, iclass 37, count 0 2006.182.07:50:40.51#ibcon#wrote, iclass 37, count 0 2006.182.07:50:40.51#ibcon#about to read 3, iclass 37, count 0 2006.182.07:50:40.53#ibcon#read 3, iclass 37, count 0 2006.182.07:50:40.53#ibcon#about to read 4, iclass 37, count 0 2006.182.07:50:40.53#ibcon#read 4, iclass 37, count 0 2006.182.07:50:40.53#ibcon#about to read 5, iclass 37, count 0 2006.182.07:50:40.53#ibcon#read 5, iclass 37, count 0 2006.182.07:50:40.53#ibcon#about to read 6, iclass 37, count 0 2006.182.07:50:40.53#ibcon#read 6, iclass 37, count 0 2006.182.07:50:40.53#ibcon#end of sib2, iclass 37, count 0 2006.182.07:50:40.53#ibcon#*mode == 0, iclass 37, count 0 2006.182.07:50:40.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.07:50:40.53#ibcon#[25=USB\r\n] 2006.182.07:50:40.53#ibcon#*before write, iclass 37, count 0 2006.182.07:50:40.53#ibcon#enter sib2, iclass 37, count 0 2006.182.07:50:40.53#ibcon#flushed, iclass 37, count 0 2006.182.07:50:40.53#ibcon#about to write, iclass 37, count 0 2006.182.07:50:40.53#ibcon#wrote, iclass 37, count 0 2006.182.07:50:40.53#ibcon#about to read 3, iclass 37, count 0 2006.182.07:50:40.56#ibcon#read 3, iclass 37, count 0 2006.182.07:50:40.56#ibcon#about to read 4, iclass 37, count 0 2006.182.07:50:40.56#ibcon#read 4, iclass 37, count 0 2006.182.07:50:40.56#ibcon#about to read 5, iclass 37, count 0 2006.182.07:50:40.56#ibcon#read 5, iclass 37, count 0 2006.182.07:50:40.56#ibcon#about to read 6, iclass 37, count 0 2006.182.07:50:40.56#ibcon#read 6, iclass 37, count 0 2006.182.07:50:40.56#ibcon#end of sib2, iclass 37, count 0 2006.182.07:50:40.56#ibcon#*after write, iclass 37, count 0 2006.182.07:50:40.56#ibcon#*before return 0, iclass 37, count 0 2006.182.07:50:40.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:50:40.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.07:50:40.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.07:50:40.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.07:50:40.56$vc4f8/vblo=1,632.99 2006.182.07:50:40.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.07:50:40.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.07:50:40.56#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:40.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:50:40.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:50:40.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:50:40.56#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:50:40.56#ibcon#first serial, iclass 39, count 0 2006.182.07:50:40.56#ibcon#enter sib2, iclass 39, count 0 2006.182.07:50:40.56#ibcon#flushed, iclass 39, count 0 2006.182.07:50:40.56#ibcon#about to write, iclass 39, count 0 2006.182.07:50:40.56#ibcon#wrote, iclass 39, count 0 2006.182.07:50:40.56#ibcon#about to read 3, iclass 39, count 0 2006.182.07:50:40.58#ibcon#read 3, iclass 39, count 0 2006.182.07:50:40.58#ibcon#about to read 4, iclass 39, count 0 2006.182.07:50:40.58#ibcon#read 4, iclass 39, count 0 2006.182.07:50:40.58#ibcon#about to read 5, iclass 39, count 0 2006.182.07:50:40.58#ibcon#read 5, iclass 39, count 0 2006.182.07:50:40.58#ibcon#about to read 6, iclass 39, count 0 2006.182.07:50:40.58#ibcon#read 6, iclass 39, count 0 2006.182.07:50:40.58#ibcon#end of sib2, iclass 39, count 0 2006.182.07:50:40.58#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:50:40.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:50:40.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:50:40.58#ibcon#*before write, iclass 39, count 0 2006.182.07:50:40.58#ibcon#enter sib2, iclass 39, count 0 2006.182.07:50:40.58#ibcon#flushed, iclass 39, count 0 2006.182.07:50:40.58#ibcon#about to write, iclass 39, count 0 2006.182.07:50:40.58#ibcon#wrote, iclass 39, count 0 2006.182.07:50:40.58#ibcon#about to read 3, iclass 39, count 0 2006.182.07:50:40.62#ibcon#read 3, iclass 39, count 0 2006.182.07:50:40.62#ibcon#about to read 4, iclass 39, count 0 2006.182.07:50:40.62#ibcon#read 4, iclass 39, count 0 2006.182.07:50:40.62#ibcon#about to read 5, iclass 39, count 0 2006.182.07:50:40.62#ibcon#read 5, iclass 39, count 0 2006.182.07:50:40.62#ibcon#about to read 6, iclass 39, count 0 2006.182.07:50:40.62#ibcon#read 6, iclass 39, count 0 2006.182.07:50:40.62#ibcon#end of sib2, iclass 39, count 0 2006.182.07:50:40.62#ibcon#*after write, iclass 39, count 0 2006.182.07:50:40.62#ibcon#*before return 0, iclass 39, count 0 2006.182.07:50:40.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:50:40.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.07:50:40.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:50:40.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:50:40.62$vc4f8/vb=1,4 2006.182.07:50:40.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.07:50:40.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.07:50:40.62#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:40.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:50:40.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:50:40.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:50:40.62#ibcon#enter wrdev, iclass 3, count 2 2006.182.07:50:40.62#ibcon#first serial, iclass 3, count 2 2006.182.07:50:40.62#ibcon#enter sib2, iclass 3, count 2 2006.182.07:50:40.62#ibcon#flushed, iclass 3, count 2 2006.182.07:50:40.62#ibcon#about to write, iclass 3, count 2 2006.182.07:50:40.62#ibcon#wrote, iclass 3, count 2 2006.182.07:50:40.62#ibcon#about to read 3, iclass 3, count 2 2006.182.07:50:40.64#ibcon#read 3, iclass 3, count 2 2006.182.07:50:40.64#ibcon#about to read 4, iclass 3, count 2 2006.182.07:50:40.64#ibcon#read 4, iclass 3, count 2 2006.182.07:50:40.64#ibcon#about to read 5, iclass 3, count 2 2006.182.07:50:40.64#ibcon#read 5, iclass 3, count 2 2006.182.07:50:40.64#ibcon#about to read 6, iclass 3, count 2 2006.182.07:50:40.64#ibcon#read 6, iclass 3, count 2 2006.182.07:50:40.64#ibcon#end of sib2, iclass 3, count 2 2006.182.07:50:40.64#ibcon#*mode == 0, iclass 3, count 2 2006.182.07:50:40.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.07:50:40.64#ibcon#[27=AT01-04\r\n] 2006.182.07:50:40.64#ibcon#*before write, iclass 3, count 2 2006.182.07:50:40.64#ibcon#enter sib2, iclass 3, count 2 2006.182.07:50:40.64#ibcon#flushed, iclass 3, count 2 2006.182.07:50:40.64#ibcon#about to write, iclass 3, count 2 2006.182.07:50:40.64#ibcon#wrote, iclass 3, count 2 2006.182.07:50:40.64#ibcon#about to read 3, iclass 3, count 2 2006.182.07:50:40.67#ibcon#read 3, iclass 3, count 2 2006.182.07:50:40.67#ibcon#about to read 4, iclass 3, count 2 2006.182.07:50:40.67#ibcon#read 4, iclass 3, count 2 2006.182.07:50:40.67#ibcon#about to read 5, iclass 3, count 2 2006.182.07:50:40.67#ibcon#read 5, iclass 3, count 2 2006.182.07:50:40.67#ibcon#about to read 6, iclass 3, count 2 2006.182.07:50:40.67#ibcon#read 6, iclass 3, count 2 2006.182.07:50:40.67#ibcon#end of sib2, iclass 3, count 2 2006.182.07:50:40.67#ibcon#*after write, iclass 3, count 2 2006.182.07:50:40.67#ibcon#*before return 0, iclass 3, count 2 2006.182.07:50:40.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:50:40.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.07:50:40.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.07:50:40.67#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:40.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:50:40.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:50:40.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:50:40.79#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:50:40.79#ibcon#first serial, iclass 3, count 0 2006.182.07:50:40.79#ibcon#enter sib2, iclass 3, count 0 2006.182.07:50:40.79#ibcon#flushed, iclass 3, count 0 2006.182.07:50:40.79#ibcon#about to write, iclass 3, count 0 2006.182.07:50:40.79#ibcon#wrote, iclass 3, count 0 2006.182.07:50:40.79#ibcon#about to read 3, iclass 3, count 0 2006.182.07:50:40.81#ibcon#read 3, iclass 3, count 0 2006.182.07:50:40.81#ibcon#about to read 4, iclass 3, count 0 2006.182.07:50:40.81#ibcon#read 4, iclass 3, count 0 2006.182.07:50:40.81#ibcon#about to read 5, iclass 3, count 0 2006.182.07:50:40.81#ibcon#read 5, iclass 3, count 0 2006.182.07:50:40.81#ibcon#about to read 6, iclass 3, count 0 2006.182.07:50:40.81#ibcon#read 6, iclass 3, count 0 2006.182.07:50:40.81#ibcon#end of sib2, iclass 3, count 0 2006.182.07:50:40.81#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:50:40.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:50:40.81#ibcon#[27=USB\r\n] 2006.182.07:50:40.81#ibcon#*before write, iclass 3, count 0 2006.182.07:50:40.81#ibcon#enter sib2, iclass 3, count 0 2006.182.07:50:40.81#ibcon#flushed, iclass 3, count 0 2006.182.07:50:40.81#ibcon#about to write, iclass 3, count 0 2006.182.07:50:40.81#ibcon#wrote, iclass 3, count 0 2006.182.07:50:40.81#ibcon#about to read 3, iclass 3, count 0 2006.182.07:50:40.84#ibcon#read 3, iclass 3, count 0 2006.182.07:50:40.84#ibcon#about to read 4, iclass 3, count 0 2006.182.07:50:40.84#ibcon#read 4, iclass 3, count 0 2006.182.07:50:40.84#ibcon#about to read 5, iclass 3, count 0 2006.182.07:50:40.84#ibcon#read 5, iclass 3, count 0 2006.182.07:50:40.84#ibcon#about to read 6, iclass 3, count 0 2006.182.07:50:40.84#ibcon#read 6, iclass 3, count 0 2006.182.07:50:40.84#ibcon#end of sib2, iclass 3, count 0 2006.182.07:50:40.84#ibcon#*after write, iclass 3, count 0 2006.182.07:50:40.84#ibcon#*before return 0, iclass 3, count 0 2006.182.07:50:40.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:50:40.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.07:50:40.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:50:40.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:50:40.84$vc4f8/vblo=2,640.99 2006.182.07:50:40.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.07:50:40.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.07:50:40.84#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:40.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:40.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:40.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:40.84#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:50:40.84#ibcon#first serial, iclass 5, count 0 2006.182.07:50:40.84#ibcon#enter sib2, iclass 5, count 0 2006.182.07:50:40.84#ibcon#flushed, iclass 5, count 0 2006.182.07:50:40.84#ibcon#about to write, iclass 5, count 0 2006.182.07:50:40.84#ibcon#wrote, iclass 5, count 0 2006.182.07:50:40.84#ibcon#about to read 3, iclass 5, count 0 2006.182.07:50:40.86#ibcon#read 3, iclass 5, count 0 2006.182.07:50:40.86#ibcon#about to read 4, iclass 5, count 0 2006.182.07:50:40.86#ibcon#read 4, iclass 5, count 0 2006.182.07:50:40.86#ibcon#about to read 5, iclass 5, count 0 2006.182.07:50:40.86#ibcon#read 5, iclass 5, count 0 2006.182.07:50:40.86#ibcon#about to read 6, iclass 5, count 0 2006.182.07:50:40.86#ibcon#read 6, iclass 5, count 0 2006.182.07:50:40.86#ibcon#end of sib2, iclass 5, count 0 2006.182.07:50:40.86#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:50:40.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:50:40.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:50:40.86#ibcon#*before write, iclass 5, count 0 2006.182.07:50:40.86#ibcon#enter sib2, iclass 5, count 0 2006.182.07:50:40.86#ibcon#flushed, iclass 5, count 0 2006.182.07:50:40.86#ibcon#about to write, iclass 5, count 0 2006.182.07:50:40.86#ibcon#wrote, iclass 5, count 0 2006.182.07:50:40.86#ibcon#about to read 3, iclass 5, count 0 2006.182.07:50:40.90#ibcon#read 3, iclass 5, count 0 2006.182.07:50:40.90#ibcon#about to read 4, iclass 5, count 0 2006.182.07:50:40.90#ibcon#read 4, iclass 5, count 0 2006.182.07:50:40.90#ibcon#about to read 5, iclass 5, count 0 2006.182.07:50:40.90#ibcon#read 5, iclass 5, count 0 2006.182.07:50:40.90#ibcon#about to read 6, iclass 5, count 0 2006.182.07:50:40.90#ibcon#read 6, iclass 5, count 0 2006.182.07:50:40.90#ibcon#end of sib2, iclass 5, count 0 2006.182.07:50:40.90#ibcon#*after write, iclass 5, count 0 2006.182.07:50:40.90#ibcon#*before return 0, iclass 5, count 0 2006.182.07:50:40.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:40.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.07:50:40.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:50:40.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:50:40.90$vc4f8/vb=2,4 2006.182.07:50:40.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.07:50:40.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.07:50:40.90#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:40.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:40.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:40.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:40.96#ibcon#enter wrdev, iclass 7, count 2 2006.182.07:50:40.96#ibcon#first serial, iclass 7, count 2 2006.182.07:50:40.96#ibcon#enter sib2, iclass 7, count 2 2006.182.07:50:40.96#ibcon#flushed, iclass 7, count 2 2006.182.07:50:40.96#ibcon#about to write, iclass 7, count 2 2006.182.07:50:40.96#ibcon#wrote, iclass 7, count 2 2006.182.07:50:40.96#ibcon#about to read 3, iclass 7, count 2 2006.182.07:50:40.98#ibcon#read 3, iclass 7, count 2 2006.182.07:50:40.98#ibcon#about to read 4, iclass 7, count 2 2006.182.07:50:40.98#ibcon#read 4, iclass 7, count 2 2006.182.07:50:40.98#ibcon#about to read 5, iclass 7, count 2 2006.182.07:50:40.98#ibcon#read 5, iclass 7, count 2 2006.182.07:50:40.98#ibcon#about to read 6, iclass 7, count 2 2006.182.07:50:40.98#ibcon#read 6, iclass 7, count 2 2006.182.07:50:40.98#ibcon#end of sib2, iclass 7, count 2 2006.182.07:50:40.98#ibcon#*mode == 0, iclass 7, count 2 2006.182.07:50:40.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.07:50:40.98#ibcon#[27=AT02-04\r\n] 2006.182.07:50:40.98#ibcon#*before write, iclass 7, count 2 2006.182.07:50:40.98#ibcon#enter sib2, iclass 7, count 2 2006.182.07:50:40.98#ibcon#flushed, iclass 7, count 2 2006.182.07:50:40.98#ibcon#about to write, iclass 7, count 2 2006.182.07:50:40.98#ibcon#wrote, iclass 7, count 2 2006.182.07:50:40.98#ibcon#about to read 3, iclass 7, count 2 2006.182.07:50:41.01#ibcon#read 3, iclass 7, count 2 2006.182.07:50:41.01#ibcon#about to read 4, iclass 7, count 2 2006.182.07:50:41.01#ibcon#read 4, iclass 7, count 2 2006.182.07:50:41.01#ibcon#about to read 5, iclass 7, count 2 2006.182.07:50:41.01#ibcon#read 5, iclass 7, count 2 2006.182.07:50:41.01#ibcon#about to read 6, iclass 7, count 2 2006.182.07:50:41.01#ibcon#read 6, iclass 7, count 2 2006.182.07:50:41.01#ibcon#end of sib2, iclass 7, count 2 2006.182.07:50:41.01#ibcon#*after write, iclass 7, count 2 2006.182.07:50:41.01#ibcon#*before return 0, iclass 7, count 2 2006.182.07:50:41.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:41.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.07:50:41.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.07:50:41.01#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:41.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:41.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:41.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:41.13#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:50:41.13#ibcon#first serial, iclass 7, count 0 2006.182.07:50:41.13#ibcon#enter sib2, iclass 7, count 0 2006.182.07:50:41.13#ibcon#flushed, iclass 7, count 0 2006.182.07:50:41.13#ibcon#about to write, iclass 7, count 0 2006.182.07:50:41.13#ibcon#wrote, iclass 7, count 0 2006.182.07:50:41.13#ibcon#about to read 3, iclass 7, count 0 2006.182.07:50:41.15#ibcon#read 3, iclass 7, count 0 2006.182.07:50:41.15#ibcon#about to read 4, iclass 7, count 0 2006.182.07:50:41.15#ibcon#read 4, iclass 7, count 0 2006.182.07:50:41.15#ibcon#about to read 5, iclass 7, count 0 2006.182.07:50:41.15#ibcon#read 5, iclass 7, count 0 2006.182.07:50:41.15#ibcon#about to read 6, iclass 7, count 0 2006.182.07:50:41.15#ibcon#read 6, iclass 7, count 0 2006.182.07:50:41.15#ibcon#end of sib2, iclass 7, count 0 2006.182.07:50:41.15#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:50:41.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:50:41.15#ibcon#[27=USB\r\n] 2006.182.07:50:41.15#ibcon#*before write, iclass 7, count 0 2006.182.07:50:41.15#ibcon#enter sib2, iclass 7, count 0 2006.182.07:50:41.15#ibcon#flushed, iclass 7, count 0 2006.182.07:50:41.15#ibcon#about to write, iclass 7, count 0 2006.182.07:50:41.15#ibcon#wrote, iclass 7, count 0 2006.182.07:50:41.15#ibcon#about to read 3, iclass 7, count 0 2006.182.07:50:41.18#ibcon#read 3, iclass 7, count 0 2006.182.07:50:41.18#ibcon#about to read 4, iclass 7, count 0 2006.182.07:50:41.18#ibcon#read 4, iclass 7, count 0 2006.182.07:50:41.18#ibcon#about to read 5, iclass 7, count 0 2006.182.07:50:41.18#ibcon#read 5, iclass 7, count 0 2006.182.07:50:41.18#ibcon#about to read 6, iclass 7, count 0 2006.182.07:50:41.18#ibcon#read 6, iclass 7, count 0 2006.182.07:50:41.18#ibcon#end of sib2, iclass 7, count 0 2006.182.07:50:41.18#ibcon#*after write, iclass 7, count 0 2006.182.07:50:41.18#ibcon#*before return 0, iclass 7, count 0 2006.182.07:50:41.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:41.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.07:50:41.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:50:41.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:50:41.18$vc4f8/vblo=3,656.99 2006.182.07:50:41.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.07:50:41.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.07:50:41.18#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:41.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:41.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:41.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:41.18#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:50:41.18#ibcon#first serial, iclass 11, count 0 2006.182.07:50:41.18#ibcon#enter sib2, iclass 11, count 0 2006.182.07:50:41.18#ibcon#flushed, iclass 11, count 0 2006.182.07:50:41.18#ibcon#about to write, iclass 11, count 0 2006.182.07:50:41.18#ibcon#wrote, iclass 11, count 0 2006.182.07:50:41.18#ibcon#about to read 3, iclass 11, count 0 2006.182.07:50:41.20#ibcon#read 3, iclass 11, count 0 2006.182.07:50:41.20#ibcon#about to read 4, iclass 11, count 0 2006.182.07:50:41.20#ibcon#read 4, iclass 11, count 0 2006.182.07:50:41.20#ibcon#about to read 5, iclass 11, count 0 2006.182.07:50:41.20#ibcon#read 5, iclass 11, count 0 2006.182.07:50:41.20#ibcon#about to read 6, iclass 11, count 0 2006.182.07:50:41.20#ibcon#read 6, iclass 11, count 0 2006.182.07:50:41.20#ibcon#end of sib2, iclass 11, count 0 2006.182.07:50:41.20#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:50:41.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:50:41.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:50:41.20#ibcon#*before write, iclass 11, count 0 2006.182.07:50:41.20#ibcon#enter sib2, iclass 11, count 0 2006.182.07:50:41.20#ibcon#flushed, iclass 11, count 0 2006.182.07:50:41.20#ibcon#about to write, iclass 11, count 0 2006.182.07:50:41.20#ibcon#wrote, iclass 11, count 0 2006.182.07:50:41.20#ibcon#about to read 3, iclass 11, count 0 2006.182.07:50:41.24#ibcon#read 3, iclass 11, count 0 2006.182.07:50:41.24#ibcon#about to read 4, iclass 11, count 0 2006.182.07:50:41.24#ibcon#read 4, iclass 11, count 0 2006.182.07:50:41.24#ibcon#about to read 5, iclass 11, count 0 2006.182.07:50:41.24#ibcon#read 5, iclass 11, count 0 2006.182.07:50:41.24#ibcon#about to read 6, iclass 11, count 0 2006.182.07:50:41.24#ibcon#read 6, iclass 11, count 0 2006.182.07:50:41.24#ibcon#end of sib2, iclass 11, count 0 2006.182.07:50:41.24#ibcon#*after write, iclass 11, count 0 2006.182.07:50:41.24#ibcon#*before return 0, iclass 11, count 0 2006.182.07:50:41.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:41.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.07:50:41.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:50:41.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:50:41.24$vc4f8/vb=3,4 2006.182.07:50:41.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.07:50:41.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.07:50:41.24#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:41.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:41.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:41.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:41.30#ibcon#enter wrdev, iclass 13, count 2 2006.182.07:50:41.30#ibcon#first serial, iclass 13, count 2 2006.182.07:50:41.30#ibcon#enter sib2, iclass 13, count 2 2006.182.07:50:41.30#ibcon#flushed, iclass 13, count 2 2006.182.07:50:41.30#ibcon#about to write, iclass 13, count 2 2006.182.07:50:41.30#ibcon#wrote, iclass 13, count 2 2006.182.07:50:41.30#ibcon#about to read 3, iclass 13, count 2 2006.182.07:50:41.32#ibcon#read 3, iclass 13, count 2 2006.182.07:50:41.32#ibcon#about to read 4, iclass 13, count 2 2006.182.07:50:41.32#ibcon#read 4, iclass 13, count 2 2006.182.07:50:41.32#ibcon#about to read 5, iclass 13, count 2 2006.182.07:50:41.32#ibcon#read 5, iclass 13, count 2 2006.182.07:50:41.32#ibcon#about to read 6, iclass 13, count 2 2006.182.07:50:41.32#ibcon#read 6, iclass 13, count 2 2006.182.07:50:41.32#ibcon#end of sib2, iclass 13, count 2 2006.182.07:50:41.32#ibcon#*mode == 0, iclass 13, count 2 2006.182.07:50:41.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.07:50:41.32#ibcon#[27=AT03-04\r\n] 2006.182.07:50:41.32#ibcon#*before write, iclass 13, count 2 2006.182.07:50:41.32#ibcon#enter sib2, iclass 13, count 2 2006.182.07:50:41.32#ibcon#flushed, iclass 13, count 2 2006.182.07:50:41.32#ibcon#about to write, iclass 13, count 2 2006.182.07:50:41.32#ibcon#wrote, iclass 13, count 2 2006.182.07:50:41.32#ibcon#about to read 3, iclass 13, count 2 2006.182.07:50:41.35#ibcon#read 3, iclass 13, count 2 2006.182.07:50:41.35#ibcon#about to read 4, iclass 13, count 2 2006.182.07:50:41.35#ibcon#read 4, iclass 13, count 2 2006.182.07:50:41.35#ibcon#about to read 5, iclass 13, count 2 2006.182.07:50:41.35#ibcon#read 5, iclass 13, count 2 2006.182.07:50:41.35#ibcon#about to read 6, iclass 13, count 2 2006.182.07:50:41.35#ibcon#read 6, iclass 13, count 2 2006.182.07:50:41.35#ibcon#end of sib2, iclass 13, count 2 2006.182.07:50:41.35#ibcon#*after write, iclass 13, count 2 2006.182.07:50:41.35#ibcon#*before return 0, iclass 13, count 2 2006.182.07:50:41.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:41.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.07:50:41.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.07:50:41.35#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:41.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:41.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:41.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:41.47#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:50:41.47#ibcon#first serial, iclass 13, count 0 2006.182.07:50:41.47#ibcon#enter sib2, iclass 13, count 0 2006.182.07:50:41.47#ibcon#flushed, iclass 13, count 0 2006.182.07:50:41.47#ibcon#about to write, iclass 13, count 0 2006.182.07:50:41.47#ibcon#wrote, iclass 13, count 0 2006.182.07:50:41.47#ibcon#about to read 3, iclass 13, count 0 2006.182.07:50:41.49#ibcon#read 3, iclass 13, count 0 2006.182.07:50:41.49#ibcon#about to read 4, iclass 13, count 0 2006.182.07:50:41.49#ibcon#read 4, iclass 13, count 0 2006.182.07:50:41.49#ibcon#about to read 5, iclass 13, count 0 2006.182.07:50:41.49#ibcon#read 5, iclass 13, count 0 2006.182.07:50:41.49#ibcon#about to read 6, iclass 13, count 0 2006.182.07:50:41.49#ibcon#read 6, iclass 13, count 0 2006.182.07:50:41.49#ibcon#end of sib2, iclass 13, count 0 2006.182.07:50:41.49#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:50:41.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:50:41.49#ibcon#[27=USB\r\n] 2006.182.07:50:41.49#ibcon#*before write, iclass 13, count 0 2006.182.07:50:41.49#ibcon#enter sib2, iclass 13, count 0 2006.182.07:50:41.49#ibcon#flushed, iclass 13, count 0 2006.182.07:50:41.49#ibcon#about to write, iclass 13, count 0 2006.182.07:50:41.49#ibcon#wrote, iclass 13, count 0 2006.182.07:50:41.49#ibcon#about to read 3, iclass 13, count 0 2006.182.07:50:41.52#ibcon#read 3, iclass 13, count 0 2006.182.07:50:41.52#ibcon#about to read 4, iclass 13, count 0 2006.182.07:50:41.52#ibcon#read 4, iclass 13, count 0 2006.182.07:50:41.52#ibcon#about to read 5, iclass 13, count 0 2006.182.07:50:41.52#ibcon#read 5, iclass 13, count 0 2006.182.07:50:41.52#ibcon#about to read 6, iclass 13, count 0 2006.182.07:50:41.52#ibcon#read 6, iclass 13, count 0 2006.182.07:50:41.52#ibcon#end of sib2, iclass 13, count 0 2006.182.07:50:41.52#ibcon#*after write, iclass 13, count 0 2006.182.07:50:41.52#ibcon#*before return 0, iclass 13, count 0 2006.182.07:50:41.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:41.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.07:50:41.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:50:41.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:50:41.52$vc4f8/vblo=4,712.99 2006.182.07:50:41.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.07:50:41.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.07:50:41.52#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:41.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:41.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:41.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:41.52#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:50:41.52#ibcon#first serial, iclass 15, count 0 2006.182.07:50:41.52#ibcon#enter sib2, iclass 15, count 0 2006.182.07:50:41.52#ibcon#flushed, iclass 15, count 0 2006.182.07:50:41.52#ibcon#about to write, iclass 15, count 0 2006.182.07:50:41.52#ibcon#wrote, iclass 15, count 0 2006.182.07:50:41.52#ibcon#about to read 3, iclass 15, count 0 2006.182.07:50:41.54#ibcon#read 3, iclass 15, count 0 2006.182.07:50:41.54#ibcon#about to read 4, iclass 15, count 0 2006.182.07:50:41.54#ibcon#read 4, iclass 15, count 0 2006.182.07:50:41.54#ibcon#about to read 5, iclass 15, count 0 2006.182.07:50:41.54#ibcon#read 5, iclass 15, count 0 2006.182.07:50:41.54#ibcon#about to read 6, iclass 15, count 0 2006.182.07:50:41.54#ibcon#read 6, iclass 15, count 0 2006.182.07:50:41.54#ibcon#end of sib2, iclass 15, count 0 2006.182.07:50:41.54#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:50:41.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:50:41.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:50:41.54#ibcon#*before write, iclass 15, count 0 2006.182.07:50:41.54#ibcon#enter sib2, iclass 15, count 0 2006.182.07:50:41.54#ibcon#flushed, iclass 15, count 0 2006.182.07:50:41.54#ibcon#about to write, iclass 15, count 0 2006.182.07:50:41.54#ibcon#wrote, iclass 15, count 0 2006.182.07:50:41.54#ibcon#about to read 3, iclass 15, count 0 2006.182.07:50:41.58#ibcon#read 3, iclass 15, count 0 2006.182.07:50:41.58#ibcon#about to read 4, iclass 15, count 0 2006.182.07:50:41.58#ibcon#read 4, iclass 15, count 0 2006.182.07:50:41.58#ibcon#about to read 5, iclass 15, count 0 2006.182.07:50:41.58#ibcon#read 5, iclass 15, count 0 2006.182.07:50:41.58#ibcon#about to read 6, iclass 15, count 0 2006.182.07:50:41.58#ibcon#read 6, iclass 15, count 0 2006.182.07:50:41.58#ibcon#end of sib2, iclass 15, count 0 2006.182.07:50:41.58#ibcon#*after write, iclass 15, count 0 2006.182.07:50:41.58#ibcon#*before return 0, iclass 15, count 0 2006.182.07:50:41.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:41.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:50:41.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:50:41.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:50:41.58$vc4f8/vb=4,4 2006.182.07:50:41.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.07:50:41.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.07:50:41.58#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:41.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:41.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:41.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:41.64#ibcon#enter wrdev, iclass 17, count 2 2006.182.07:50:41.64#ibcon#first serial, iclass 17, count 2 2006.182.07:50:41.64#ibcon#enter sib2, iclass 17, count 2 2006.182.07:50:41.64#ibcon#flushed, iclass 17, count 2 2006.182.07:50:41.64#ibcon#about to write, iclass 17, count 2 2006.182.07:50:41.64#ibcon#wrote, iclass 17, count 2 2006.182.07:50:41.64#ibcon#about to read 3, iclass 17, count 2 2006.182.07:50:41.66#ibcon#read 3, iclass 17, count 2 2006.182.07:50:41.66#ibcon#about to read 4, iclass 17, count 2 2006.182.07:50:41.66#ibcon#read 4, iclass 17, count 2 2006.182.07:50:41.66#ibcon#about to read 5, iclass 17, count 2 2006.182.07:50:41.66#ibcon#read 5, iclass 17, count 2 2006.182.07:50:41.66#ibcon#about to read 6, iclass 17, count 2 2006.182.07:50:41.66#ibcon#read 6, iclass 17, count 2 2006.182.07:50:41.66#ibcon#end of sib2, iclass 17, count 2 2006.182.07:50:41.66#ibcon#*mode == 0, iclass 17, count 2 2006.182.07:50:41.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.07:50:41.66#ibcon#[27=AT04-04\r\n] 2006.182.07:50:41.66#ibcon#*before write, iclass 17, count 2 2006.182.07:50:41.66#ibcon#enter sib2, iclass 17, count 2 2006.182.07:50:41.66#ibcon#flushed, iclass 17, count 2 2006.182.07:50:41.66#ibcon#about to write, iclass 17, count 2 2006.182.07:50:41.66#ibcon#wrote, iclass 17, count 2 2006.182.07:50:41.66#ibcon#about to read 3, iclass 17, count 2 2006.182.07:50:41.69#ibcon#read 3, iclass 17, count 2 2006.182.07:50:41.69#ibcon#about to read 4, iclass 17, count 2 2006.182.07:50:41.69#ibcon#read 4, iclass 17, count 2 2006.182.07:50:41.69#ibcon#about to read 5, iclass 17, count 2 2006.182.07:50:41.69#ibcon#read 5, iclass 17, count 2 2006.182.07:50:41.69#ibcon#about to read 6, iclass 17, count 2 2006.182.07:50:41.69#ibcon#read 6, iclass 17, count 2 2006.182.07:50:41.69#ibcon#end of sib2, iclass 17, count 2 2006.182.07:50:41.69#ibcon#*after write, iclass 17, count 2 2006.182.07:50:41.69#ibcon#*before return 0, iclass 17, count 2 2006.182.07:50:41.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:41.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.07:50:41.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.07:50:41.69#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:41.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:41.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:41.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:41.81#ibcon#enter wrdev, iclass 17, count 0 2006.182.07:50:41.81#ibcon#first serial, iclass 17, count 0 2006.182.07:50:41.81#ibcon#enter sib2, iclass 17, count 0 2006.182.07:50:41.81#ibcon#flushed, iclass 17, count 0 2006.182.07:50:41.81#ibcon#about to write, iclass 17, count 0 2006.182.07:50:41.81#ibcon#wrote, iclass 17, count 0 2006.182.07:50:41.81#ibcon#about to read 3, iclass 17, count 0 2006.182.07:50:41.83#ibcon#read 3, iclass 17, count 0 2006.182.07:50:41.83#ibcon#about to read 4, iclass 17, count 0 2006.182.07:50:41.83#ibcon#read 4, iclass 17, count 0 2006.182.07:50:41.83#ibcon#about to read 5, iclass 17, count 0 2006.182.07:50:41.83#ibcon#read 5, iclass 17, count 0 2006.182.07:50:41.83#ibcon#about to read 6, iclass 17, count 0 2006.182.07:50:41.83#ibcon#read 6, iclass 17, count 0 2006.182.07:50:41.83#ibcon#end of sib2, iclass 17, count 0 2006.182.07:50:41.83#ibcon#*mode == 0, iclass 17, count 0 2006.182.07:50:41.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.07:50:41.83#ibcon#[27=USB\r\n] 2006.182.07:50:41.83#ibcon#*before write, iclass 17, count 0 2006.182.07:50:41.83#ibcon#enter sib2, iclass 17, count 0 2006.182.07:50:41.83#ibcon#flushed, iclass 17, count 0 2006.182.07:50:41.83#ibcon#about to write, iclass 17, count 0 2006.182.07:50:41.83#ibcon#wrote, iclass 17, count 0 2006.182.07:50:41.83#ibcon#about to read 3, iclass 17, count 0 2006.182.07:50:41.86#ibcon#read 3, iclass 17, count 0 2006.182.07:50:41.86#ibcon#about to read 4, iclass 17, count 0 2006.182.07:50:41.86#ibcon#read 4, iclass 17, count 0 2006.182.07:50:41.86#ibcon#about to read 5, iclass 17, count 0 2006.182.07:50:41.86#ibcon#read 5, iclass 17, count 0 2006.182.07:50:41.86#ibcon#about to read 6, iclass 17, count 0 2006.182.07:50:41.86#ibcon#read 6, iclass 17, count 0 2006.182.07:50:41.86#ibcon#end of sib2, iclass 17, count 0 2006.182.07:50:41.86#ibcon#*after write, iclass 17, count 0 2006.182.07:50:41.86#ibcon#*before return 0, iclass 17, count 0 2006.182.07:50:41.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:41.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.07:50:41.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.07:50:41.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.07:50:41.86$vc4f8/vblo=5,744.99 2006.182.07:50:41.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.07:50:41.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.07:50:41.86#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:41.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:41.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:41.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:41.86#ibcon#enter wrdev, iclass 19, count 0 2006.182.07:50:41.86#ibcon#first serial, iclass 19, count 0 2006.182.07:50:41.86#ibcon#enter sib2, iclass 19, count 0 2006.182.07:50:41.86#ibcon#flushed, iclass 19, count 0 2006.182.07:50:41.86#ibcon#about to write, iclass 19, count 0 2006.182.07:50:41.86#ibcon#wrote, iclass 19, count 0 2006.182.07:50:41.86#ibcon#about to read 3, iclass 19, count 0 2006.182.07:50:41.88#ibcon#read 3, iclass 19, count 0 2006.182.07:50:41.88#ibcon#about to read 4, iclass 19, count 0 2006.182.07:50:41.88#ibcon#read 4, iclass 19, count 0 2006.182.07:50:41.88#ibcon#about to read 5, iclass 19, count 0 2006.182.07:50:41.88#ibcon#read 5, iclass 19, count 0 2006.182.07:50:41.88#ibcon#about to read 6, iclass 19, count 0 2006.182.07:50:41.88#ibcon#read 6, iclass 19, count 0 2006.182.07:50:41.88#ibcon#end of sib2, iclass 19, count 0 2006.182.07:50:41.88#ibcon#*mode == 0, iclass 19, count 0 2006.182.07:50:41.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.07:50:41.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:50:41.88#ibcon#*before write, iclass 19, count 0 2006.182.07:50:41.88#ibcon#enter sib2, iclass 19, count 0 2006.182.07:50:41.88#ibcon#flushed, iclass 19, count 0 2006.182.07:50:41.88#ibcon#about to write, iclass 19, count 0 2006.182.07:50:41.88#ibcon#wrote, iclass 19, count 0 2006.182.07:50:41.88#ibcon#about to read 3, iclass 19, count 0 2006.182.07:50:41.92#ibcon#read 3, iclass 19, count 0 2006.182.07:50:41.92#ibcon#about to read 4, iclass 19, count 0 2006.182.07:50:41.92#ibcon#read 4, iclass 19, count 0 2006.182.07:50:41.92#ibcon#about to read 5, iclass 19, count 0 2006.182.07:50:41.92#ibcon#read 5, iclass 19, count 0 2006.182.07:50:41.92#ibcon#about to read 6, iclass 19, count 0 2006.182.07:50:41.92#ibcon#read 6, iclass 19, count 0 2006.182.07:50:41.92#ibcon#end of sib2, iclass 19, count 0 2006.182.07:50:41.92#ibcon#*after write, iclass 19, count 0 2006.182.07:50:41.92#ibcon#*before return 0, iclass 19, count 0 2006.182.07:50:41.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:41.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.07:50:41.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.07:50:41.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.07:50:41.92$vc4f8/vb=5,4 2006.182.07:50:41.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.07:50:41.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.07:50:41.92#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:41.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:41.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:41.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:41.98#ibcon#enter wrdev, iclass 21, count 2 2006.182.07:50:41.98#ibcon#first serial, iclass 21, count 2 2006.182.07:50:41.98#ibcon#enter sib2, iclass 21, count 2 2006.182.07:50:41.98#ibcon#flushed, iclass 21, count 2 2006.182.07:50:41.98#ibcon#about to write, iclass 21, count 2 2006.182.07:50:41.98#ibcon#wrote, iclass 21, count 2 2006.182.07:50:41.98#ibcon#about to read 3, iclass 21, count 2 2006.182.07:50:42.00#ibcon#read 3, iclass 21, count 2 2006.182.07:50:42.00#ibcon#about to read 4, iclass 21, count 2 2006.182.07:50:42.00#ibcon#read 4, iclass 21, count 2 2006.182.07:50:42.00#ibcon#about to read 5, iclass 21, count 2 2006.182.07:50:42.00#ibcon#read 5, iclass 21, count 2 2006.182.07:50:42.00#ibcon#about to read 6, iclass 21, count 2 2006.182.07:50:42.00#ibcon#read 6, iclass 21, count 2 2006.182.07:50:42.00#ibcon#end of sib2, iclass 21, count 2 2006.182.07:50:42.00#ibcon#*mode == 0, iclass 21, count 2 2006.182.07:50:42.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.07:50:42.00#ibcon#[27=AT05-04\r\n] 2006.182.07:50:42.00#ibcon#*before write, iclass 21, count 2 2006.182.07:50:42.00#ibcon#enter sib2, iclass 21, count 2 2006.182.07:50:42.00#ibcon#flushed, iclass 21, count 2 2006.182.07:50:42.00#ibcon#about to write, iclass 21, count 2 2006.182.07:50:42.00#ibcon#wrote, iclass 21, count 2 2006.182.07:50:42.00#ibcon#about to read 3, iclass 21, count 2 2006.182.07:50:42.03#ibcon#read 3, iclass 21, count 2 2006.182.07:50:42.03#ibcon#about to read 4, iclass 21, count 2 2006.182.07:50:42.03#ibcon#read 4, iclass 21, count 2 2006.182.07:50:42.03#ibcon#about to read 5, iclass 21, count 2 2006.182.07:50:42.03#ibcon#read 5, iclass 21, count 2 2006.182.07:50:42.03#ibcon#about to read 6, iclass 21, count 2 2006.182.07:50:42.03#ibcon#read 6, iclass 21, count 2 2006.182.07:50:42.03#ibcon#end of sib2, iclass 21, count 2 2006.182.07:50:42.03#ibcon#*after write, iclass 21, count 2 2006.182.07:50:42.03#ibcon#*before return 0, iclass 21, count 2 2006.182.07:50:42.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:42.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.07:50:42.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.07:50:42.03#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:42.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:42.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:42.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:42.15#ibcon#enter wrdev, iclass 21, count 0 2006.182.07:50:42.15#ibcon#first serial, iclass 21, count 0 2006.182.07:50:42.15#ibcon#enter sib2, iclass 21, count 0 2006.182.07:50:42.15#ibcon#flushed, iclass 21, count 0 2006.182.07:50:42.15#ibcon#about to write, iclass 21, count 0 2006.182.07:50:42.15#ibcon#wrote, iclass 21, count 0 2006.182.07:50:42.15#ibcon#about to read 3, iclass 21, count 0 2006.182.07:50:42.17#ibcon#read 3, iclass 21, count 0 2006.182.07:50:42.17#ibcon#about to read 4, iclass 21, count 0 2006.182.07:50:42.17#ibcon#read 4, iclass 21, count 0 2006.182.07:50:42.17#ibcon#about to read 5, iclass 21, count 0 2006.182.07:50:42.17#ibcon#read 5, iclass 21, count 0 2006.182.07:50:42.17#ibcon#about to read 6, iclass 21, count 0 2006.182.07:50:42.17#ibcon#read 6, iclass 21, count 0 2006.182.07:50:42.17#ibcon#end of sib2, iclass 21, count 0 2006.182.07:50:42.17#ibcon#*mode == 0, iclass 21, count 0 2006.182.07:50:42.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.07:50:42.17#ibcon#[27=USB\r\n] 2006.182.07:50:42.17#ibcon#*before write, iclass 21, count 0 2006.182.07:50:42.17#ibcon#enter sib2, iclass 21, count 0 2006.182.07:50:42.17#ibcon#flushed, iclass 21, count 0 2006.182.07:50:42.17#ibcon#about to write, iclass 21, count 0 2006.182.07:50:42.17#ibcon#wrote, iclass 21, count 0 2006.182.07:50:42.17#ibcon#about to read 3, iclass 21, count 0 2006.182.07:50:42.20#ibcon#read 3, iclass 21, count 0 2006.182.07:50:42.20#ibcon#about to read 4, iclass 21, count 0 2006.182.07:50:42.20#ibcon#read 4, iclass 21, count 0 2006.182.07:50:42.20#ibcon#about to read 5, iclass 21, count 0 2006.182.07:50:42.20#ibcon#read 5, iclass 21, count 0 2006.182.07:50:42.20#ibcon#about to read 6, iclass 21, count 0 2006.182.07:50:42.20#ibcon#read 6, iclass 21, count 0 2006.182.07:50:42.20#ibcon#end of sib2, iclass 21, count 0 2006.182.07:50:42.20#ibcon#*after write, iclass 21, count 0 2006.182.07:50:42.20#ibcon#*before return 0, iclass 21, count 0 2006.182.07:50:42.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:42.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.07:50:42.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.07:50:42.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.07:50:42.20$vc4f8/vblo=6,752.99 2006.182.07:50:42.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.07:50:42.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.07:50:42.20#ibcon#ireg 17 cls_cnt 0 2006.182.07:50:42.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:42.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:42.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:42.20#ibcon#enter wrdev, iclass 23, count 0 2006.182.07:50:42.20#ibcon#first serial, iclass 23, count 0 2006.182.07:50:42.20#ibcon#enter sib2, iclass 23, count 0 2006.182.07:50:42.20#ibcon#flushed, iclass 23, count 0 2006.182.07:50:42.20#ibcon#about to write, iclass 23, count 0 2006.182.07:50:42.20#ibcon#wrote, iclass 23, count 0 2006.182.07:50:42.20#ibcon#about to read 3, iclass 23, count 0 2006.182.07:50:42.22#ibcon#read 3, iclass 23, count 0 2006.182.07:50:42.22#ibcon#about to read 4, iclass 23, count 0 2006.182.07:50:42.22#ibcon#read 4, iclass 23, count 0 2006.182.07:50:42.22#ibcon#about to read 5, iclass 23, count 0 2006.182.07:50:42.22#ibcon#read 5, iclass 23, count 0 2006.182.07:50:42.22#ibcon#about to read 6, iclass 23, count 0 2006.182.07:50:42.22#ibcon#read 6, iclass 23, count 0 2006.182.07:50:42.22#ibcon#end of sib2, iclass 23, count 0 2006.182.07:50:42.22#ibcon#*mode == 0, iclass 23, count 0 2006.182.07:50:42.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.07:50:42.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:50:42.22#ibcon#*before write, iclass 23, count 0 2006.182.07:50:42.22#ibcon#enter sib2, iclass 23, count 0 2006.182.07:50:42.22#ibcon#flushed, iclass 23, count 0 2006.182.07:50:42.22#ibcon#about to write, iclass 23, count 0 2006.182.07:50:42.22#ibcon#wrote, iclass 23, count 0 2006.182.07:50:42.22#ibcon#about to read 3, iclass 23, count 0 2006.182.07:50:42.26#ibcon#read 3, iclass 23, count 0 2006.182.07:50:42.26#ibcon#about to read 4, iclass 23, count 0 2006.182.07:50:42.26#ibcon#read 4, iclass 23, count 0 2006.182.07:50:42.26#ibcon#about to read 5, iclass 23, count 0 2006.182.07:50:42.26#ibcon#read 5, iclass 23, count 0 2006.182.07:50:42.26#ibcon#about to read 6, iclass 23, count 0 2006.182.07:50:42.26#ibcon#read 6, iclass 23, count 0 2006.182.07:50:42.26#ibcon#end of sib2, iclass 23, count 0 2006.182.07:50:42.26#ibcon#*after write, iclass 23, count 0 2006.182.07:50:42.26#ibcon#*before return 0, iclass 23, count 0 2006.182.07:50:42.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:42.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.07:50:42.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.07:50:42.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.07:50:42.26$vc4f8/vb=6,4 2006.182.07:50:42.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.07:50:42.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.07:50:42.26#ibcon#ireg 11 cls_cnt 2 2006.182.07:50:42.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:42.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:42.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:42.32#ibcon#enter wrdev, iclass 25, count 2 2006.182.07:50:42.32#ibcon#first serial, iclass 25, count 2 2006.182.07:50:42.32#ibcon#enter sib2, iclass 25, count 2 2006.182.07:50:42.32#ibcon#flushed, iclass 25, count 2 2006.182.07:50:42.32#ibcon#about to write, iclass 25, count 2 2006.182.07:50:42.32#ibcon#wrote, iclass 25, count 2 2006.182.07:50:42.32#ibcon#about to read 3, iclass 25, count 2 2006.182.07:50:42.34#ibcon#read 3, iclass 25, count 2 2006.182.07:50:42.34#ibcon#about to read 4, iclass 25, count 2 2006.182.07:50:42.34#ibcon#read 4, iclass 25, count 2 2006.182.07:50:42.34#ibcon#about to read 5, iclass 25, count 2 2006.182.07:50:42.34#ibcon#read 5, iclass 25, count 2 2006.182.07:50:42.34#ibcon#about to read 6, iclass 25, count 2 2006.182.07:50:42.34#ibcon#read 6, iclass 25, count 2 2006.182.07:50:42.34#ibcon#end of sib2, iclass 25, count 2 2006.182.07:50:42.34#ibcon#*mode == 0, iclass 25, count 2 2006.182.07:50:42.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.07:50:42.34#ibcon#[27=AT06-04\r\n] 2006.182.07:50:42.34#ibcon#*before write, iclass 25, count 2 2006.182.07:50:42.34#ibcon#enter sib2, iclass 25, count 2 2006.182.07:50:42.34#ibcon#flushed, iclass 25, count 2 2006.182.07:50:42.34#ibcon#about to write, iclass 25, count 2 2006.182.07:50:42.34#ibcon#wrote, iclass 25, count 2 2006.182.07:50:42.34#ibcon#about to read 3, iclass 25, count 2 2006.182.07:50:42.37#ibcon#read 3, iclass 25, count 2 2006.182.07:50:42.37#ibcon#about to read 4, iclass 25, count 2 2006.182.07:50:42.37#ibcon#read 4, iclass 25, count 2 2006.182.07:50:42.37#ibcon#about to read 5, iclass 25, count 2 2006.182.07:50:42.37#ibcon#read 5, iclass 25, count 2 2006.182.07:50:42.37#ibcon#about to read 6, iclass 25, count 2 2006.182.07:50:42.37#ibcon#read 6, iclass 25, count 2 2006.182.07:50:42.37#ibcon#end of sib2, iclass 25, count 2 2006.182.07:50:42.37#ibcon#*after write, iclass 25, count 2 2006.182.07:50:42.37#ibcon#*before return 0, iclass 25, count 2 2006.182.07:50:42.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:42.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.07:50:42.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.07:50:42.37#ibcon#ireg 7 cls_cnt 0 2006.182.07:50:42.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:42.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:42.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:42.49#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:50:42.49#ibcon#first serial, iclass 25, count 0 2006.182.07:50:42.49#ibcon#enter sib2, iclass 25, count 0 2006.182.07:50:42.49#ibcon#flushed, iclass 25, count 0 2006.182.07:50:42.49#ibcon#about to write, iclass 25, count 0 2006.182.07:50:42.49#ibcon#wrote, iclass 25, count 0 2006.182.07:50:42.49#ibcon#about to read 3, iclass 25, count 0 2006.182.07:50:42.51#ibcon#read 3, iclass 25, count 0 2006.182.07:50:42.51#ibcon#about to read 4, iclass 25, count 0 2006.182.07:50:42.51#ibcon#read 4, iclass 25, count 0 2006.182.07:50:42.51#ibcon#about to read 5, iclass 25, count 0 2006.182.07:50:42.51#ibcon#read 5, iclass 25, count 0 2006.182.07:50:42.51#ibcon#about to read 6, iclass 25, count 0 2006.182.07:50:42.51#ibcon#read 6, iclass 25, count 0 2006.182.07:50:42.51#ibcon#end of sib2, iclass 25, count 0 2006.182.07:50:42.51#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:50:42.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:50:42.51#ibcon#[27=USB\r\n] 2006.182.07:50:42.51#ibcon#*before write, iclass 25, count 0 2006.182.07:50:42.51#ibcon#enter sib2, iclass 25, count 0 2006.182.07:50:42.51#ibcon#flushed, iclass 25, count 0 2006.182.07:50:42.51#ibcon#about to write, iclass 25, count 0 2006.182.07:50:42.51#ibcon#wrote, iclass 25, count 0 2006.182.07:50:42.51#ibcon#about to read 3, iclass 25, count 0 2006.182.07:50:42.54#ibcon#read 3, iclass 25, count 0 2006.182.07:50:42.54#ibcon#about to read 4, iclass 25, count 0 2006.182.07:50:42.54#ibcon#read 4, iclass 25, count 0 2006.182.07:50:42.54#ibcon#about to read 5, iclass 25, count 0 2006.182.07:50:42.54#ibcon#read 5, iclass 25, count 0 2006.182.07:50:42.54#ibcon#about to read 6, iclass 25, count 0 2006.182.07:50:42.54#ibcon#read 6, iclass 25, count 0 2006.182.07:50:42.54#ibcon#end of sib2, iclass 25, count 0 2006.182.07:50:42.54#ibcon#*after write, iclass 25, count 0 2006.182.07:50:42.54#ibcon#*before return 0, iclass 25, count 0 2006.182.07:50:42.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:42.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.07:50:42.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:50:42.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:50:42.54$vc4f8/vabw=wide 2006.182.07:50:42.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.07:50:42.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.07:50:42.54#ibcon#ireg 8 cls_cnt 0 2006.182.07:50:42.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:42.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:42.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:42.54#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:50:42.54#ibcon#first serial, iclass 27, count 0 2006.182.07:50:42.54#ibcon#enter sib2, iclass 27, count 0 2006.182.07:50:42.54#ibcon#flushed, iclass 27, count 0 2006.182.07:50:42.54#ibcon#about to write, iclass 27, count 0 2006.182.07:50:42.54#ibcon#wrote, iclass 27, count 0 2006.182.07:50:42.54#ibcon#about to read 3, iclass 27, count 0 2006.182.07:50:42.56#ibcon#read 3, iclass 27, count 0 2006.182.07:50:42.56#ibcon#about to read 4, iclass 27, count 0 2006.182.07:50:42.56#ibcon#read 4, iclass 27, count 0 2006.182.07:50:42.56#ibcon#about to read 5, iclass 27, count 0 2006.182.07:50:42.56#ibcon#read 5, iclass 27, count 0 2006.182.07:50:42.56#ibcon#about to read 6, iclass 27, count 0 2006.182.07:50:42.56#ibcon#read 6, iclass 27, count 0 2006.182.07:50:42.56#ibcon#end of sib2, iclass 27, count 0 2006.182.07:50:42.56#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:50:42.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:50:42.56#ibcon#[25=BW32\r\n] 2006.182.07:50:42.56#ibcon#*before write, iclass 27, count 0 2006.182.07:50:42.56#ibcon#enter sib2, iclass 27, count 0 2006.182.07:50:42.56#ibcon#flushed, iclass 27, count 0 2006.182.07:50:42.56#ibcon#about to write, iclass 27, count 0 2006.182.07:50:42.56#ibcon#wrote, iclass 27, count 0 2006.182.07:50:42.56#ibcon#about to read 3, iclass 27, count 0 2006.182.07:50:42.59#ibcon#read 3, iclass 27, count 0 2006.182.07:50:42.59#ibcon#about to read 4, iclass 27, count 0 2006.182.07:50:42.59#ibcon#read 4, iclass 27, count 0 2006.182.07:50:42.59#ibcon#about to read 5, iclass 27, count 0 2006.182.07:50:42.59#ibcon#read 5, iclass 27, count 0 2006.182.07:50:42.59#ibcon#about to read 6, iclass 27, count 0 2006.182.07:50:42.59#ibcon#read 6, iclass 27, count 0 2006.182.07:50:42.59#ibcon#end of sib2, iclass 27, count 0 2006.182.07:50:42.59#ibcon#*after write, iclass 27, count 0 2006.182.07:50:42.59#ibcon#*before return 0, iclass 27, count 0 2006.182.07:50:42.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:42.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.07:50:42.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:50:42.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:50:42.59$vc4f8/vbbw=wide 2006.182.07:50:42.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.07:50:42.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.07:50:42.59#ibcon#ireg 8 cls_cnt 0 2006.182.07:50:42.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:50:42.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:50:42.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:50:42.66#ibcon#enter wrdev, iclass 29, count 0 2006.182.07:50:42.66#ibcon#first serial, iclass 29, count 0 2006.182.07:50:42.66#ibcon#enter sib2, iclass 29, count 0 2006.182.07:50:42.66#ibcon#flushed, iclass 29, count 0 2006.182.07:50:42.66#ibcon#about to write, iclass 29, count 0 2006.182.07:50:42.66#ibcon#wrote, iclass 29, count 0 2006.182.07:50:42.66#ibcon#about to read 3, iclass 29, count 0 2006.182.07:50:42.68#ibcon#read 3, iclass 29, count 0 2006.182.07:50:42.68#ibcon#about to read 4, iclass 29, count 0 2006.182.07:50:42.68#ibcon#read 4, iclass 29, count 0 2006.182.07:50:42.68#ibcon#about to read 5, iclass 29, count 0 2006.182.07:50:42.68#ibcon#read 5, iclass 29, count 0 2006.182.07:50:42.68#ibcon#about to read 6, iclass 29, count 0 2006.182.07:50:42.68#ibcon#read 6, iclass 29, count 0 2006.182.07:50:42.68#ibcon#end of sib2, iclass 29, count 0 2006.182.07:50:42.68#ibcon#*mode == 0, iclass 29, count 0 2006.182.07:50:42.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.07:50:42.68#ibcon#[27=BW32\r\n] 2006.182.07:50:42.68#ibcon#*before write, iclass 29, count 0 2006.182.07:50:42.68#ibcon#enter sib2, iclass 29, count 0 2006.182.07:50:42.68#ibcon#flushed, iclass 29, count 0 2006.182.07:50:42.68#ibcon#about to write, iclass 29, count 0 2006.182.07:50:42.68#ibcon#wrote, iclass 29, count 0 2006.182.07:50:42.68#ibcon#about to read 3, iclass 29, count 0 2006.182.07:50:42.68#abcon#<5=/07 0.8 1.9 27.63 811002.8\r\n> 2006.182.07:50:42.70#abcon#{5=INTERFACE CLEAR} 2006.182.07:50:42.71#ibcon#read 3, iclass 29, count 0 2006.182.07:50:42.71#ibcon#about to read 4, iclass 29, count 0 2006.182.07:50:42.71#ibcon#read 4, iclass 29, count 0 2006.182.07:50:42.71#ibcon#about to read 5, iclass 29, count 0 2006.182.07:50:42.71#ibcon#read 5, iclass 29, count 0 2006.182.07:50:42.71#ibcon#about to read 6, iclass 29, count 0 2006.182.07:50:42.71#ibcon#read 6, iclass 29, count 0 2006.182.07:50:42.71#ibcon#end of sib2, iclass 29, count 0 2006.182.07:50:42.71#ibcon#*after write, iclass 29, count 0 2006.182.07:50:42.71#ibcon#*before return 0, iclass 29, count 0 2006.182.07:50:42.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:50:42.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:50:42.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.07:50:42.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.07:50:42.71$4f8m12a/ifd4f 2006.182.07:50:42.71$ifd4f/lo= 2006.182.07:50:42.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:50:42.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:50:42.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:50:42.71$ifd4f/patch= 2006.182.07:50:42.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:50:42.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:50:42.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:50:42.71$4f8m12a/"form=m,16.000,1:2 2006.182.07:50:42.71$4f8m12a/"tpicd 2006.182.07:50:42.71$4f8m12a/echo=off 2006.182.07:50:42.71$4f8m12a/xlog=off 2006.182.07:50:42.71:!2006.182.07:51:10 2006.182.07:50:54.14#trakl#Source acquired 2006.182.07:50:55.14#flagr#flagr/antenna,acquired 2006.182.07:51:10.00:preob 2006.182.07:51:11.14/onsource/TRACKING 2006.182.07:51:11.14:!2006.182.07:51:20 2006.182.07:51:20.00:data_valid=on 2006.182.07:51:20.00:midob 2006.182.07:51:20.14/onsource/TRACKING 2006.182.07:51:20.14/wx/27.64,1002.8,82 2006.182.07:51:20.30/cable/+6.4648E-03 2006.182.07:51:21.39/va/01,08,usb,yes,29,31 2006.182.07:51:21.39/va/02,07,usb,yes,29,31 2006.182.07:51:21.39/va/03,06,usb,yes,31,31 2006.182.07:51:21.39/va/04,07,usb,yes,30,32 2006.182.07:51:21.39/va/05,07,usb,yes,31,33 2006.182.07:51:21.39/va/06,06,usb,yes,30,30 2006.182.07:51:21.39/va/07,06,usb,yes,31,30 2006.182.07:51:21.39/va/08,07,usb,yes,29,29 2006.182.07:51:21.62/valo/01,532.99,yes,locked 2006.182.07:51:21.62/valo/02,572.99,yes,locked 2006.182.07:51:21.62/valo/03,672.99,yes,locked 2006.182.07:51:21.62/valo/04,832.99,yes,locked 2006.182.07:51:21.62/valo/05,652.99,yes,locked 2006.182.07:51:21.62/valo/06,772.99,yes,locked 2006.182.07:51:21.62/valo/07,832.99,yes,locked 2006.182.07:51:21.62/valo/08,852.99,yes,locked 2006.182.07:51:22.71/vb/01,04,usb,yes,29,28 2006.182.07:51:22.71/vb/02,04,usb,yes,31,32 2006.182.07:51:22.71/vb/03,04,usb,yes,27,31 2006.182.07:51:22.71/vb/04,04,usb,yes,28,28 2006.182.07:51:22.71/vb/05,04,usb,yes,27,31 2006.182.07:51:22.71/vb/06,04,usb,yes,28,31 2006.182.07:51:22.71/vb/07,04,usb,yes,30,30 2006.182.07:51:22.71/vb/08,04,usb,yes,27,31 2006.182.07:51:22.94/vblo/01,632.99,yes,locked 2006.182.07:51:22.94/vblo/02,640.99,yes,locked 2006.182.07:51:22.94/vblo/03,656.99,yes,locked 2006.182.07:51:22.94/vblo/04,712.99,yes,locked 2006.182.07:51:22.94/vblo/05,744.99,yes,locked 2006.182.07:51:22.94/vblo/06,752.99,yes,locked 2006.182.07:51:22.94/vblo/07,734.99,yes,locked 2006.182.07:51:22.94/vblo/08,744.99,yes,locked 2006.182.07:51:23.09/vabw/8 2006.182.07:51:23.24/vbbw/8 2006.182.07:51:23.33/xfe/off,on,15.2 2006.182.07:51:23.76/ifatt/23,28,28,28 2006.182.07:51:24.08/fmout-gps/S +3.38E-07 2006.182.07:51:24.12:!2006.182.07:52:20 2006.182.07:52:20.00:data_valid=off 2006.182.07:52:20.00:postob 2006.182.07:52:20.18/cable/+6.4653E-03 2006.182.07:52:20.18/wx/27.66,1002.8,82 2006.182.07:52:21.08/fmout-gps/S +3.38E-07 2006.182.07:52:21.08:scan_name=182-0754,k06182,60 2006.182.07:52:21.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.182.07:52:21.16#flagr#flagr/antenna,new-source 2006.182.07:52:22.13:checkk5 2006.182.07:52:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:52:22.87/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:52:23.25/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:52:23.62/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:52:23.99/chk_obsdata//k5ts1/T1820751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:52:24.36/chk_obsdata//k5ts2/T1820751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:52:24.73/chk_obsdata//k5ts3/T1820751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:52:25.10/chk_obsdata//k5ts4/T1820751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:52:25.79/k5log//k5ts1_log_newline 2006.182.07:52:26.48/k5log//k5ts2_log_newline 2006.182.07:52:27.17/k5log//k5ts3_log_newline 2006.182.07:52:27.86/k5log//k5ts4_log_newline 2006.182.07:52:27.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:52:27.88:4f8m12a=2 2006.182.07:52:27.88$4f8m12a/echo=on 2006.182.07:52:27.88$4f8m12a/pcalon 2006.182.07:52:27.88$pcalon/"no phase cal control is implemented here 2006.182.07:52:27.88$4f8m12a/"tpicd=stop 2006.182.07:52:27.88$4f8m12a/vc4f8 2006.182.07:52:27.88$vc4f8/valo=1,532.99 2006.182.07:52:27.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.07:52:27.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.07:52:27.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:27.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:27.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:27.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:27.89#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:52:27.89#ibcon#first serial, iclass 40, count 0 2006.182.07:52:27.89#ibcon#enter sib2, iclass 40, count 0 2006.182.07:52:27.89#ibcon#flushed, iclass 40, count 0 2006.182.07:52:27.89#ibcon#about to write, iclass 40, count 0 2006.182.07:52:27.89#ibcon#wrote, iclass 40, count 0 2006.182.07:52:27.89#ibcon#about to read 3, iclass 40, count 0 2006.182.07:52:27.93#ibcon#read 3, iclass 40, count 0 2006.182.07:52:27.93#ibcon#about to read 4, iclass 40, count 0 2006.182.07:52:27.93#ibcon#read 4, iclass 40, count 0 2006.182.07:52:27.93#ibcon#about to read 5, iclass 40, count 0 2006.182.07:52:27.93#ibcon#read 5, iclass 40, count 0 2006.182.07:52:27.93#ibcon#about to read 6, iclass 40, count 0 2006.182.07:52:27.93#ibcon#read 6, iclass 40, count 0 2006.182.07:52:27.93#ibcon#end of sib2, iclass 40, count 0 2006.182.07:52:27.93#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:52:27.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:52:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:52:27.93#ibcon#*before write, iclass 40, count 0 2006.182.07:52:27.93#ibcon#enter sib2, iclass 40, count 0 2006.182.07:52:27.93#ibcon#flushed, iclass 40, count 0 2006.182.07:52:27.93#ibcon#about to write, iclass 40, count 0 2006.182.07:52:27.93#ibcon#wrote, iclass 40, count 0 2006.182.07:52:27.93#ibcon#about to read 3, iclass 40, count 0 2006.182.07:52:27.98#ibcon#read 3, iclass 40, count 0 2006.182.07:52:27.98#ibcon#about to read 4, iclass 40, count 0 2006.182.07:52:27.98#ibcon#read 4, iclass 40, count 0 2006.182.07:52:27.98#ibcon#about to read 5, iclass 40, count 0 2006.182.07:52:27.98#ibcon#read 5, iclass 40, count 0 2006.182.07:52:27.98#ibcon#about to read 6, iclass 40, count 0 2006.182.07:52:27.98#ibcon#read 6, iclass 40, count 0 2006.182.07:52:27.98#ibcon#end of sib2, iclass 40, count 0 2006.182.07:52:27.98#ibcon#*after write, iclass 40, count 0 2006.182.07:52:27.98#ibcon#*before return 0, iclass 40, count 0 2006.182.07:52:27.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:27.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:27.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:52:27.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:52:27.98$vc4f8/va=1,8 2006.182.07:52:27.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.07:52:27.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.07:52:27.98#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:27.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:27.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:27.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:27.98#ibcon#enter wrdev, iclass 4, count 2 2006.182.07:52:27.98#ibcon#first serial, iclass 4, count 2 2006.182.07:52:27.98#ibcon#enter sib2, iclass 4, count 2 2006.182.07:52:27.98#ibcon#flushed, iclass 4, count 2 2006.182.07:52:27.98#ibcon#about to write, iclass 4, count 2 2006.182.07:52:27.98#ibcon#wrote, iclass 4, count 2 2006.182.07:52:27.98#ibcon#about to read 3, iclass 4, count 2 2006.182.07:52:28.00#ibcon#read 3, iclass 4, count 2 2006.182.07:52:28.00#ibcon#about to read 4, iclass 4, count 2 2006.182.07:52:28.00#ibcon#read 4, iclass 4, count 2 2006.182.07:52:28.00#ibcon#about to read 5, iclass 4, count 2 2006.182.07:52:28.00#ibcon#read 5, iclass 4, count 2 2006.182.07:52:28.00#ibcon#about to read 6, iclass 4, count 2 2006.182.07:52:28.00#ibcon#read 6, iclass 4, count 2 2006.182.07:52:28.00#ibcon#end of sib2, iclass 4, count 2 2006.182.07:52:28.00#ibcon#*mode == 0, iclass 4, count 2 2006.182.07:52:28.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.07:52:28.00#ibcon#[25=AT01-08\r\n] 2006.182.07:52:28.00#ibcon#*before write, iclass 4, count 2 2006.182.07:52:28.00#ibcon#enter sib2, iclass 4, count 2 2006.182.07:52:28.00#ibcon#flushed, iclass 4, count 2 2006.182.07:52:28.00#ibcon#about to write, iclass 4, count 2 2006.182.07:52:28.00#ibcon#wrote, iclass 4, count 2 2006.182.07:52:28.00#ibcon#about to read 3, iclass 4, count 2 2006.182.07:52:28.04#ibcon#read 3, iclass 4, count 2 2006.182.07:52:28.04#ibcon#about to read 4, iclass 4, count 2 2006.182.07:52:28.04#ibcon#read 4, iclass 4, count 2 2006.182.07:52:28.04#ibcon#about to read 5, iclass 4, count 2 2006.182.07:52:28.04#ibcon#read 5, iclass 4, count 2 2006.182.07:52:28.04#ibcon#about to read 6, iclass 4, count 2 2006.182.07:52:28.04#ibcon#read 6, iclass 4, count 2 2006.182.07:52:28.04#ibcon#end of sib2, iclass 4, count 2 2006.182.07:52:28.04#ibcon#*after write, iclass 4, count 2 2006.182.07:52:28.04#ibcon#*before return 0, iclass 4, count 2 2006.182.07:52:28.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:28.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:28.04#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.07:52:28.04#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:28.04#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:28.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:28.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:28.16#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:52:28.16#ibcon#first serial, iclass 4, count 0 2006.182.07:52:28.16#ibcon#enter sib2, iclass 4, count 0 2006.182.07:52:28.16#ibcon#flushed, iclass 4, count 0 2006.182.07:52:28.16#ibcon#about to write, iclass 4, count 0 2006.182.07:52:28.16#ibcon#wrote, iclass 4, count 0 2006.182.07:52:28.16#ibcon#about to read 3, iclass 4, count 0 2006.182.07:52:28.18#ibcon#read 3, iclass 4, count 0 2006.182.07:52:28.18#ibcon#about to read 4, iclass 4, count 0 2006.182.07:52:28.18#ibcon#read 4, iclass 4, count 0 2006.182.07:52:28.18#ibcon#about to read 5, iclass 4, count 0 2006.182.07:52:28.18#ibcon#read 5, iclass 4, count 0 2006.182.07:52:28.18#ibcon#about to read 6, iclass 4, count 0 2006.182.07:52:28.18#ibcon#read 6, iclass 4, count 0 2006.182.07:52:28.18#ibcon#end of sib2, iclass 4, count 0 2006.182.07:52:28.18#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:52:28.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:52:28.18#ibcon#[25=USB\r\n] 2006.182.07:52:28.18#ibcon#*before write, iclass 4, count 0 2006.182.07:52:28.18#ibcon#enter sib2, iclass 4, count 0 2006.182.07:52:28.18#ibcon#flushed, iclass 4, count 0 2006.182.07:52:28.18#ibcon#about to write, iclass 4, count 0 2006.182.07:52:28.18#ibcon#wrote, iclass 4, count 0 2006.182.07:52:28.18#ibcon#about to read 3, iclass 4, count 0 2006.182.07:52:28.21#ibcon#read 3, iclass 4, count 0 2006.182.07:52:28.21#ibcon#about to read 4, iclass 4, count 0 2006.182.07:52:28.21#ibcon#read 4, iclass 4, count 0 2006.182.07:52:28.21#ibcon#about to read 5, iclass 4, count 0 2006.182.07:52:28.21#ibcon#read 5, iclass 4, count 0 2006.182.07:52:28.21#ibcon#about to read 6, iclass 4, count 0 2006.182.07:52:28.21#ibcon#read 6, iclass 4, count 0 2006.182.07:52:28.21#ibcon#end of sib2, iclass 4, count 0 2006.182.07:52:28.21#ibcon#*after write, iclass 4, count 0 2006.182.07:52:28.21#ibcon#*before return 0, iclass 4, count 0 2006.182.07:52:28.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:28.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:28.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:52:28.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:52:28.21$vc4f8/valo=2,572.99 2006.182.07:52:28.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.07:52:28.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.07:52:28.21#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:28.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:28.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:28.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:28.21#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:52:28.21#ibcon#first serial, iclass 6, count 0 2006.182.07:52:28.21#ibcon#enter sib2, iclass 6, count 0 2006.182.07:52:28.21#ibcon#flushed, iclass 6, count 0 2006.182.07:52:28.21#ibcon#about to write, iclass 6, count 0 2006.182.07:52:28.21#ibcon#wrote, iclass 6, count 0 2006.182.07:52:28.21#ibcon#about to read 3, iclass 6, count 0 2006.182.07:52:28.23#ibcon#read 3, iclass 6, count 0 2006.182.07:52:28.23#ibcon#about to read 4, iclass 6, count 0 2006.182.07:52:28.23#ibcon#read 4, iclass 6, count 0 2006.182.07:52:28.23#ibcon#about to read 5, iclass 6, count 0 2006.182.07:52:28.23#ibcon#read 5, iclass 6, count 0 2006.182.07:52:28.23#ibcon#about to read 6, iclass 6, count 0 2006.182.07:52:28.23#ibcon#read 6, iclass 6, count 0 2006.182.07:52:28.23#ibcon#end of sib2, iclass 6, count 0 2006.182.07:52:28.23#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:52:28.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:52:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:52:28.23#ibcon#*before write, iclass 6, count 0 2006.182.07:52:28.23#ibcon#enter sib2, iclass 6, count 0 2006.182.07:52:28.23#ibcon#flushed, iclass 6, count 0 2006.182.07:52:28.23#ibcon#about to write, iclass 6, count 0 2006.182.07:52:28.23#ibcon#wrote, iclass 6, count 0 2006.182.07:52:28.23#ibcon#about to read 3, iclass 6, count 0 2006.182.07:52:28.27#ibcon#read 3, iclass 6, count 0 2006.182.07:52:28.27#ibcon#about to read 4, iclass 6, count 0 2006.182.07:52:28.27#ibcon#read 4, iclass 6, count 0 2006.182.07:52:28.27#ibcon#about to read 5, iclass 6, count 0 2006.182.07:52:28.27#ibcon#read 5, iclass 6, count 0 2006.182.07:52:28.27#ibcon#about to read 6, iclass 6, count 0 2006.182.07:52:28.27#ibcon#read 6, iclass 6, count 0 2006.182.07:52:28.27#ibcon#end of sib2, iclass 6, count 0 2006.182.07:52:28.27#ibcon#*after write, iclass 6, count 0 2006.182.07:52:28.27#ibcon#*before return 0, iclass 6, count 0 2006.182.07:52:28.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:28.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:28.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:52:28.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:52:28.27$vc4f8/va=2,7 2006.182.07:52:28.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.07:52:28.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.07:52:28.27#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:28.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:28.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:28.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:28.33#ibcon#enter wrdev, iclass 10, count 2 2006.182.07:52:28.33#ibcon#first serial, iclass 10, count 2 2006.182.07:52:28.33#ibcon#enter sib2, iclass 10, count 2 2006.182.07:52:28.33#ibcon#flushed, iclass 10, count 2 2006.182.07:52:28.33#ibcon#about to write, iclass 10, count 2 2006.182.07:52:28.33#ibcon#wrote, iclass 10, count 2 2006.182.07:52:28.33#ibcon#about to read 3, iclass 10, count 2 2006.182.07:52:28.35#ibcon#read 3, iclass 10, count 2 2006.182.07:52:28.35#ibcon#about to read 4, iclass 10, count 2 2006.182.07:52:28.35#ibcon#read 4, iclass 10, count 2 2006.182.07:52:28.35#ibcon#about to read 5, iclass 10, count 2 2006.182.07:52:28.35#ibcon#read 5, iclass 10, count 2 2006.182.07:52:28.35#ibcon#about to read 6, iclass 10, count 2 2006.182.07:52:28.35#ibcon#read 6, iclass 10, count 2 2006.182.07:52:28.35#ibcon#end of sib2, iclass 10, count 2 2006.182.07:52:28.35#ibcon#*mode == 0, iclass 10, count 2 2006.182.07:52:28.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.07:52:28.35#ibcon#[25=AT02-07\r\n] 2006.182.07:52:28.35#ibcon#*before write, iclass 10, count 2 2006.182.07:52:28.35#ibcon#enter sib2, iclass 10, count 2 2006.182.07:52:28.35#ibcon#flushed, iclass 10, count 2 2006.182.07:52:28.35#ibcon#about to write, iclass 10, count 2 2006.182.07:52:28.35#ibcon#wrote, iclass 10, count 2 2006.182.07:52:28.35#ibcon#about to read 3, iclass 10, count 2 2006.182.07:52:28.38#ibcon#read 3, iclass 10, count 2 2006.182.07:52:28.38#ibcon#about to read 4, iclass 10, count 2 2006.182.07:52:28.38#ibcon#read 4, iclass 10, count 2 2006.182.07:52:28.38#ibcon#about to read 5, iclass 10, count 2 2006.182.07:52:28.38#ibcon#read 5, iclass 10, count 2 2006.182.07:52:28.38#ibcon#about to read 6, iclass 10, count 2 2006.182.07:52:28.38#ibcon#read 6, iclass 10, count 2 2006.182.07:52:28.38#ibcon#end of sib2, iclass 10, count 2 2006.182.07:52:28.38#ibcon#*after write, iclass 10, count 2 2006.182.07:52:28.38#ibcon#*before return 0, iclass 10, count 2 2006.182.07:52:28.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:28.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:28.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.07:52:28.38#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:28.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:28.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:28.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:28.50#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:52:28.50#ibcon#first serial, iclass 10, count 0 2006.182.07:52:28.50#ibcon#enter sib2, iclass 10, count 0 2006.182.07:52:28.50#ibcon#flushed, iclass 10, count 0 2006.182.07:52:28.50#ibcon#about to write, iclass 10, count 0 2006.182.07:52:28.50#ibcon#wrote, iclass 10, count 0 2006.182.07:52:28.50#ibcon#about to read 3, iclass 10, count 0 2006.182.07:52:28.52#ibcon#read 3, iclass 10, count 0 2006.182.07:52:28.52#ibcon#about to read 4, iclass 10, count 0 2006.182.07:52:28.52#ibcon#read 4, iclass 10, count 0 2006.182.07:52:28.52#ibcon#about to read 5, iclass 10, count 0 2006.182.07:52:28.52#ibcon#read 5, iclass 10, count 0 2006.182.07:52:28.52#ibcon#about to read 6, iclass 10, count 0 2006.182.07:52:28.52#ibcon#read 6, iclass 10, count 0 2006.182.07:52:28.52#ibcon#end of sib2, iclass 10, count 0 2006.182.07:52:28.52#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:52:28.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:52:28.52#ibcon#[25=USB\r\n] 2006.182.07:52:28.52#ibcon#*before write, iclass 10, count 0 2006.182.07:52:28.52#ibcon#enter sib2, iclass 10, count 0 2006.182.07:52:28.52#ibcon#flushed, iclass 10, count 0 2006.182.07:52:28.52#ibcon#about to write, iclass 10, count 0 2006.182.07:52:28.52#ibcon#wrote, iclass 10, count 0 2006.182.07:52:28.52#ibcon#about to read 3, iclass 10, count 0 2006.182.07:52:28.55#ibcon#read 3, iclass 10, count 0 2006.182.07:52:28.55#ibcon#about to read 4, iclass 10, count 0 2006.182.07:52:28.55#ibcon#read 4, iclass 10, count 0 2006.182.07:52:28.55#ibcon#about to read 5, iclass 10, count 0 2006.182.07:52:28.55#ibcon#read 5, iclass 10, count 0 2006.182.07:52:28.55#ibcon#about to read 6, iclass 10, count 0 2006.182.07:52:28.55#ibcon#read 6, iclass 10, count 0 2006.182.07:52:28.55#ibcon#end of sib2, iclass 10, count 0 2006.182.07:52:28.55#ibcon#*after write, iclass 10, count 0 2006.182.07:52:28.55#ibcon#*before return 0, iclass 10, count 0 2006.182.07:52:28.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:28.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:28.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:52:28.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:52:28.55$vc4f8/valo=3,672.99 2006.182.07:52:28.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.07:52:28.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.07:52:28.55#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:28.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:28.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:28.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:28.55#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:52:28.55#ibcon#first serial, iclass 12, count 0 2006.182.07:52:28.55#ibcon#enter sib2, iclass 12, count 0 2006.182.07:52:28.55#ibcon#flushed, iclass 12, count 0 2006.182.07:52:28.55#ibcon#about to write, iclass 12, count 0 2006.182.07:52:28.55#ibcon#wrote, iclass 12, count 0 2006.182.07:52:28.55#ibcon#about to read 3, iclass 12, count 0 2006.182.07:52:28.57#ibcon#read 3, iclass 12, count 0 2006.182.07:52:28.57#ibcon#about to read 4, iclass 12, count 0 2006.182.07:52:28.57#ibcon#read 4, iclass 12, count 0 2006.182.07:52:28.57#ibcon#about to read 5, iclass 12, count 0 2006.182.07:52:28.57#ibcon#read 5, iclass 12, count 0 2006.182.07:52:28.57#ibcon#about to read 6, iclass 12, count 0 2006.182.07:52:28.57#ibcon#read 6, iclass 12, count 0 2006.182.07:52:28.57#ibcon#end of sib2, iclass 12, count 0 2006.182.07:52:28.57#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:52:28.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:52:28.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:52:28.57#ibcon#*before write, iclass 12, count 0 2006.182.07:52:28.57#ibcon#enter sib2, iclass 12, count 0 2006.182.07:52:28.57#ibcon#flushed, iclass 12, count 0 2006.182.07:52:28.57#ibcon#about to write, iclass 12, count 0 2006.182.07:52:28.57#ibcon#wrote, iclass 12, count 0 2006.182.07:52:28.57#ibcon#about to read 3, iclass 12, count 0 2006.182.07:52:28.62#ibcon#read 3, iclass 12, count 0 2006.182.07:52:28.62#ibcon#about to read 4, iclass 12, count 0 2006.182.07:52:28.62#ibcon#read 4, iclass 12, count 0 2006.182.07:52:28.62#ibcon#about to read 5, iclass 12, count 0 2006.182.07:52:28.62#ibcon#read 5, iclass 12, count 0 2006.182.07:52:28.62#ibcon#about to read 6, iclass 12, count 0 2006.182.07:52:28.62#ibcon#read 6, iclass 12, count 0 2006.182.07:52:28.62#ibcon#end of sib2, iclass 12, count 0 2006.182.07:52:28.62#ibcon#*after write, iclass 12, count 0 2006.182.07:52:28.62#ibcon#*before return 0, iclass 12, count 0 2006.182.07:52:28.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:28.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:28.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:52:28.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:52:28.62$vc4f8/va=3,6 2006.182.07:52:28.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.07:52:28.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.07:52:28.62#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:28.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:28.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:28.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:28.67#ibcon#enter wrdev, iclass 14, count 2 2006.182.07:52:28.67#ibcon#first serial, iclass 14, count 2 2006.182.07:52:28.67#ibcon#enter sib2, iclass 14, count 2 2006.182.07:52:28.67#ibcon#flushed, iclass 14, count 2 2006.182.07:52:28.67#ibcon#about to write, iclass 14, count 2 2006.182.07:52:28.67#ibcon#wrote, iclass 14, count 2 2006.182.07:52:28.67#ibcon#about to read 3, iclass 14, count 2 2006.182.07:52:28.69#ibcon#read 3, iclass 14, count 2 2006.182.07:52:28.69#ibcon#about to read 4, iclass 14, count 2 2006.182.07:52:28.69#ibcon#read 4, iclass 14, count 2 2006.182.07:52:28.69#ibcon#about to read 5, iclass 14, count 2 2006.182.07:52:28.69#ibcon#read 5, iclass 14, count 2 2006.182.07:52:28.69#ibcon#about to read 6, iclass 14, count 2 2006.182.07:52:28.69#ibcon#read 6, iclass 14, count 2 2006.182.07:52:28.69#ibcon#end of sib2, iclass 14, count 2 2006.182.07:52:28.69#ibcon#*mode == 0, iclass 14, count 2 2006.182.07:52:28.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.07:52:28.69#ibcon#[25=AT03-06\r\n] 2006.182.07:52:28.69#ibcon#*before write, iclass 14, count 2 2006.182.07:52:28.69#ibcon#enter sib2, iclass 14, count 2 2006.182.07:52:28.69#ibcon#flushed, iclass 14, count 2 2006.182.07:52:28.69#ibcon#about to write, iclass 14, count 2 2006.182.07:52:28.69#ibcon#wrote, iclass 14, count 2 2006.182.07:52:28.69#ibcon#about to read 3, iclass 14, count 2 2006.182.07:52:28.72#ibcon#read 3, iclass 14, count 2 2006.182.07:52:28.72#ibcon#about to read 4, iclass 14, count 2 2006.182.07:52:28.72#ibcon#read 4, iclass 14, count 2 2006.182.07:52:28.72#ibcon#about to read 5, iclass 14, count 2 2006.182.07:52:28.72#ibcon#read 5, iclass 14, count 2 2006.182.07:52:28.72#ibcon#about to read 6, iclass 14, count 2 2006.182.07:52:28.72#ibcon#read 6, iclass 14, count 2 2006.182.07:52:28.72#ibcon#end of sib2, iclass 14, count 2 2006.182.07:52:28.72#ibcon#*after write, iclass 14, count 2 2006.182.07:52:28.72#ibcon#*before return 0, iclass 14, count 2 2006.182.07:52:28.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:28.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:28.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.07:52:28.72#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:28.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:28.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:28.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:28.84#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:52:28.84#ibcon#first serial, iclass 14, count 0 2006.182.07:52:28.84#ibcon#enter sib2, iclass 14, count 0 2006.182.07:52:28.84#ibcon#flushed, iclass 14, count 0 2006.182.07:52:28.84#ibcon#about to write, iclass 14, count 0 2006.182.07:52:28.84#ibcon#wrote, iclass 14, count 0 2006.182.07:52:28.84#ibcon#about to read 3, iclass 14, count 0 2006.182.07:52:28.86#ibcon#read 3, iclass 14, count 0 2006.182.07:52:28.86#ibcon#about to read 4, iclass 14, count 0 2006.182.07:52:28.86#ibcon#read 4, iclass 14, count 0 2006.182.07:52:28.86#ibcon#about to read 5, iclass 14, count 0 2006.182.07:52:28.86#ibcon#read 5, iclass 14, count 0 2006.182.07:52:28.86#ibcon#about to read 6, iclass 14, count 0 2006.182.07:52:28.86#ibcon#read 6, iclass 14, count 0 2006.182.07:52:28.86#ibcon#end of sib2, iclass 14, count 0 2006.182.07:52:28.86#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:52:28.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:52:28.86#ibcon#[25=USB\r\n] 2006.182.07:52:28.86#ibcon#*before write, iclass 14, count 0 2006.182.07:52:28.86#ibcon#enter sib2, iclass 14, count 0 2006.182.07:52:28.86#ibcon#flushed, iclass 14, count 0 2006.182.07:52:28.86#ibcon#about to write, iclass 14, count 0 2006.182.07:52:28.86#ibcon#wrote, iclass 14, count 0 2006.182.07:52:28.86#ibcon#about to read 3, iclass 14, count 0 2006.182.07:52:28.89#ibcon#read 3, iclass 14, count 0 2006.182.07:52:28.89#ibcon#about to read 4, iclass 14, count 0 2006.182.07:52:28.89#ibcon#read 4, iclass 14, count 0 2006.182.07:52:28.89#ibcon#about to read 5, iclass 14, count 0 2006.182.07:52:28.89#ibcon#read 5, iclass 14, count 0 2006.182.07:52:28.89#ibcon#about to read 6, iclass 14, count 0 2006.182.07:52:28.89#ibcon#read 6, iclass 14, count 0 2006.182.07:52:28.89#ibcon#end of sib2, iclass 14, count 0 2006.182.07:52:28.89#ibcon#*after write, iclass 14, count 0 2006.182.07:52:28.89#ibcon#*before return 0, iclass 14, count 0 2006.182.07:52:28.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:28.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:28.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:52:28.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:52:28.89$vc4f8/valo=4,832.99 2006.182.07:52:28.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.07:52:28.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.07:52:28.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:28.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:28.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:28.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:28.89#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:52:28.89#ibcon#first serial, iclass 16, count 0 2006.182.07:52:28.89#ibcon#enter sib2, iclass 16, count 0 2006.182.07:52:28.89#ibcon#flushed, iclass 16, count 0 2006.182.07:52:28.89#ibcon#about to write, iclass 16, count 0 2006.182.07:52:28.89#ibcon#wrote, iclass 16, count 0 2006.182.07:52:28.89#ibcon#about to read 3, iclass 16, count 0 2006.182.07:52:28.91#ibcon#read 3, iclass 16, count 0 2006.182.07:52:28.91#ibcon#about to read 4, iclass 16, count 0 2006.182.07:52:28.91#ibcon#read 4, iclass 16, count 0 2006.182.07:52:28.91#ibcon#about to read 5, iclass 16, count 0 2006.182.07:52:28.91#ibcon#read 5, iclass 16, count 0 2006.182.07:52:28.91#ibcon#about to read 6, iclass 16, count 0 2006.182.07:52:28.91#ibcon#read 6, iclass 16, count 0 2006.182.07:52:28.91#ibcon#end of sib2, iclass 16, count 0 2006.182.07:52:28.91#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:52:28.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:52:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:52:28.91#ibcon#*before write, iclass 16, count 0 2006.182.07:52:28.91#ibcon#enter sib2, iclass 16, count 0 2006.182.07:52:28.91#ibcon#flushed, iclass 16, count 0 2006.182.07:52:28.91#ibcon#about to write, iclass 16, count 0 2006.182.07:52:28.91#ibcon#wrote, iclass 16, count 0 2006.182.07:52:28.91#ibcon#about to read 3, iclass 16, count 0 2006.182.07:52:28.95#ibcon#read 3, iclass 16, count 0 2006.182.07:52:28.95#ibcon#about to read 4, iclass 16, count 0 2006.182.07:52:28.95#ibcon#read 4, iclass 16, count 0 2006.182.07:52:28.95#ibcon#about to read 5, iclass 16, count 0 2006.182.07:52:28.95#ibcon#read 5, iclass 16, count 0 2006.182.07:52:28.95#ibcon#about to read 6, iclass 16, count 0 2006.182.07:52:28.95#ibcon#read 6, iclass 16, count 0 2006.182.07:52:28.95#ibcon#end of sib2, iclass 16, count 0 2006.182.07:52:28.95#ibcon#*after write, iclass 16, count 0 2006.182.07:52:28.95#ibcon#*before return 0, iclass 16, count 0 2006.182.07:52:28.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:28.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:28.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:52:28.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:52:28.95$vc4f8/va=4,7 2006.182.07:52:28.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.07:52:28.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.07:52:28.95#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:28.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:29.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:29.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:29.01#ibcon#enter wrdev, iclass 18, count 2 2006.182.07:52:29.01#ibcon#first serial, iclass 18, count 2 2006.182.07:52:29.01#ibcon#enter sib2, iclass 18, count 2 2006.182.07:52:29.01#ibcon#flushed, iclass 18, count 2 2006.182.07:52:29.01#ibcon#about to write, iclass 18, count 2 2006.182.07:52:29.01#ibcon#wrote, iclass 18, count 2 2006.182.07:52:29.01#ibcon#about to read 3, iclass 18, count 2 2006.182.07:52:29.03#ibcon#read 3, iclass 18, count 2 2006.182.07:52:29.03#ibcon#about to read 4, iclass 18, count 2 2006.182.07:52:29.03#ibcon#read 4, iclass 18, count 2 2006.182.07:52:29.03#ibcon#about to read 5, iclass 18, count 2 2006.182.07:52:29.03#ibcon#read 5, iclass 18, count 2 2006.182.07:52:29.03#ibcon#about to read 6, iclass 18, count 2 2006.182.07:52:29.03#ibcon#read 6, iclass 18, count 2 2006.182.07:52:29.03#ibcon#end of sib2, iclass 18, count 2 2006.182.07:52:29.03#ibcon#*mode == 0, iclass 18, count 2 2006.182.07:52:29.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.07:52:29.03#ibcon#[25=AT04-07\r\n] 2006.182.07:52:29.03#ibcon#*before write, iclass 18, count 2 2006.182.07:52:29.03#ibcon#enter sib2, iclass 18, count 2 2006.182.07:52:29.03#ibcon#flushed, iclass 18, count 2 2006.182.07:52:29.03#ibcon#about to write, iclass 18, count 2 2006.182.07:52:29.03#ibcon#wrote, iclass 18, count 2 2006.182.07:52:29.03#ibcon#about to read 3, iclass 18, count 2 2006.182.07:52:29.06#ibcon#read 3, iclass 18, count 2 2006.182.07:52:29.06#ibcon#about to read 4, iclass 18, count 2 2006.182.07:52:29.06#ibcon#read 4, iclass 18, count 2 2006.182.07:52:29.06#ibcon#about to read 5, iclass 18, count 2 2006.182.07:52:29.06#ibcon#read 5, iclass 18, count 2 2006.182.07:52:29.06#ibcon#about to read 6, iclass 18, count 2 2006.182.07:52:29.06#ibcon#read 6, iclass 18, count 2 2006.182.07:52:29.06#ibcon#end of sib2, iclass 18, count 2 2006.182.07:52:29.06#ibcon#*after write, iclass 18, count 2 2006.182.07:52:29.06#ibcon#*before return 0, iclass 18, count 2 2006.182.07:52:29.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:29.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:29.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.07:52:29.06#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:29.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:29.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:29.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:29.18#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:52:29.18#ibcon#first serial, iclass 18, count 0 2006.182.07:52:29.18#ibcon#enter sib2, iclass 18, count 0 2006.182.07:52:29.18#ibcon#flushed, iclass 18, count 0 2006.182.07:52:29.18#ibcon#about to write, iclass 18, count 0 2006.182.07:52:29.18#ibcon#wrote, iclass 18, count 0 2006.182.07:52:29.18#ibcon#about to read 3, iclass 18, count 0 2006.182.07:52:29.20#ibcon#read 3, iclass 18, count 0 2006.182.07:52:29.20#ibcon#about to read 4, iclass 18, count 0 2006.182.07:52:29.20#ibcon#read 4, iclass 18, count 0 2006.182.07:52:29.20#ibcon#about to read 5, iclass 18, count 0 2006.182.07:52:29.20#ibcon#read 5, iclass 18, count 0 2006.182.07:52:29.20#ibcon#about to read 6, iclass 18, count 0 2006.182.07:52:29.20#ibcon#read 6, iclass 18, count 0 2006.182.07:52:29.20#ibcon#end of sib2, iclass 18, count 0 2006.182.07:52:29.20#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:52:29.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:52:29.20#ibcon#[25=USB\r\n] 2006.182.07:52:29.20#ibcon#*before write, iclass 18, count 0 2006.182.07:52:29.20#ibcon#enter sib2, iclass 18, count 0 2006.182.07:52:29.20#ibcon#flushed, iclass 18, count 0 2006.182.07:52:29.20#ibcon#about to write, iclass 18, count 0 2006.182.07:52:29.20#ibcon#wrote, iclass 18, count 0 2006.182.07:52:29.20#ibcon#about to read 3, iclass 18, count 0 2006.182.07:52:29.23#ibcon#read 3, iclass 18, count 0 2006.182.07:52:29.23#ibcon#about to read 4, iclass 18, count 0 2006.182.07:52:29.23#ibcon#read 4, iclass 18, count 0 2006.182.07:52:29.23#ibcon#about to read 5, iclass 18, count 0 2006.182.07:52:29.23#ibcon#read 5, iclass 18, count 0 2006.182.07:52:29.23#ibcon#about to read 6, iclass 18, count 0 2006.182.07:52:29.23#ibcon#read 6, iclass 18, count 0 2006.182.07:52:29.23#ibcon#end of sib2, iclass 18, count 0 2006.182.07:52:29.23#ibcon#*after write, iclass 18, count 0 2006.182.07:52:29.23#ibcon#*before return 0, iclass 18, count 0 2006.182.07:52:29.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:29.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:29.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:52:29.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:52:29.23$vc4f8/valo=5,652.99 2006.182.07:52:29.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.07:52:29.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.07:52:29.23#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:29.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:29.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:29.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:29.23#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:52:29.23#ibcon#first serial, iclass 20, count 0 2006.182.07:52:29.23#ibcon#enter sib2, iclass 20, count 0 2006.182.07:52:29.23#ibcon#flushed, iclass 20, count 0 2006.182.07:52:29.23#ibcon#about to write, iclass 20, count 0 2006.182.07:52:29.23#ibcon#wrote, iclass 20, count 0 2006.182.07:52:29.23#ibcon#about to read 3, iclass 20, count 0 2006.182.07:52:29.25#ibcon#read 3, iclass 20, count 0 2006.182.07:52:29.25#ibcon#about to read 4, iclass 20, count 0 2006.182.07:52:29.25#ibcon#read 4, iclass 20, count 0 2006.182.07:52:29.25#ibcon#about to read 5, iclass 20, count 0 2006.182.07:52:29.25#ibcon#read 5, iclass 20, count 0 2006.182.07:52:29.25#ibcon#about to read 6, iclass 20, count 0 2006.182.07:52:29.25#ibcon#read 6, iclass 20, count 0 2006.182.07:52:29.25#ibcon#end of sib2, iclass 20, count 0 2006.182.07:52:29.25#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:52:29.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:52:29.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:52:29.25#ibcon#*before write, iclass 20, count 0 2006.182.07:52:29.25#ibcon#enter sib2, iclass 20, count 0 2006.182.07:52:29.25#ibcon#flushed, iclass 20, count 0 2006.182.07:52:29.25#ibcon#about to write, iclass 20, count 0 2006.182.07:52:29.25#ibcon#wrote, iclass 20, count 0 2006.182.07:52:29.25#ibcon#about to read 3, iclass 20, count 0 2006.182.07:52:29.29#ibcon#read 3, iclass 20, count 0 2006.182.07:52:29.29#ibcon#about to read 4, iclass 20, count 0 2006.182.07:52:29.29#ibcon#read 4, iclass 20, count 0 2006.182.07:52:29.29#ibcon#about to read 5, iclass 20, count 0 2006.182.07:52:29.29#ibcon#read 5, iclass 20, count 0 2006.182.07:52:29.29#ibcon#about to read 6, iclass 20, count 0 2006.182.07:52:29.29#ibcon#read 6, iclass 20, count 0 2006.182.07:52:29.29#ibcon#end of sib2, iclass 20, count 0 2006.182.07:52:29.29#ibcon#*after write, iclass 20, count 0 2006.182.07:52:29.29#ibcon#*before return 0, iclass 20, count 0 2006.182.07:52:29.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:29.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:29.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:52:29.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:52:29.29$vc4f8/va=5,7 2006.182.07:52:29.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.07:52:29.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.07:52:29.29#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:29.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:29.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:29.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:29.35#ibcon#enter wrdev, iclass 22, count 2 2006.182.07:52:29.35#ibcon#first serial, iclass 22, count 2 2006.182.07:52:29.35#ibcon#enter sib2, iclass 22, count 2 2006.182.07:52:29.35#ibcon#flushed, iclass 22, count 2 2006.182.07:52:29.35#ibcon#about to write, iclass 22, count 2 2006.182.07:52:29.35#ibcon#wrote, iclass 22, count 2 2006.182.07:52:29.35#ibcon#about to read 3, iclass 22, count 2 2006.182.07:52:29.37#ibcon#read 3, iclass 22, count 2 2006.182.07:52:29.37#ibcon#about to read 4, iclass 22, count 2 2006.182.07:52:29.37#ibcon#read 4, iclass 22, count 2 2006.182.07:52:29.37#ibcon#about to read 5, iclass 22, count 2 2006.182.07:52:29.37#ibcon#read 5, iclass 22, count 2 2006.182.07:52:29.37#ibcon#about to read 6, iclass 22, count 2 2006.182.07:52:29.37#ibcon#read 6, iclass 22, count 2 2006.182.07:52:29.37#ibcon#end of sib2, iclass 22, count 2 2006.182.07:52:29.37#ibcon#*mode == 0, iclass 22, count 2 2006.182.07:52:29.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.07:52:29.37#ibcon#[25=AT05-07\r\n] 2006.182.07:52:29.37#ibcon#*before write, iclass 22, count 2 2006.182.07:52:29.37#ibcon#enter sib2, iclass 22, count 2 2006.182.07:52:29.37#ibcon#flushed, iclass 22, count 2 2006.182.07:52:29.37#ibcon#about to write, iclass 22, count 2 2006.182.07:52:29.37#ibcon#wrote, iclass 22, count 2 2006.182.07:52:29.37#ibcon#about to read 3, iclass 22, count 2 2006.182.07:52:29.40#ibcon#read 3, iclass 22, count 2 2006.182.07:52:29.40#ibcon#about to read 4, iclass 22, count 2 2006.182.07:52:29.40#ibcon#read 4, iclass 22, count 2 2006.182.07:52:29.40#ibcon#about to read 5, iclass 22, count 2 2006.182.07:52:29.40#ibcon#read 5, iclass 22, count 2 2006.182.07:52:29.40#ibcon#about to read 6, iclass 22, count 2 2006.182.07:52:29.40#ibcon#read 6, iclass 22, count 2 2006.182.07:52:29.40#ibcon#end of sib2, iclass 22, count 2 2006.182.07:52:29.40#ibcon#*after write, iclass 22, count 2 2006.182.07:52:29.40#ibcon#*before return 0, iclass 22, count 2 2006.182.07:52:29.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:29.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:29.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.07:52:29.40#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:29.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:29.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:29.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:29.52#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:52:29.52#ibcon#first serial, iclass 22, count 0 2006.182.07:52:29.52#ibcon#enter sib2, iclass 22, count 0 2006.182.07:52:29.52#ibcon#flushed, iclass 22, count 0 2006.182.07:52:29.52#ibcon#about to write, iclass 22, count 0 2006.182.07:52:29.52#ibcon#wrote, iclass 22, count 0 2006.182.07:52:29.52#ibcon#about to read 3, iclass 22, count 0 2006.182.07:52:29.54#ibcon#read 3, iclass 22, count 0 2006.182.07:52:29.54#ibcon#about to read 4, iclass 22, count 0 2006.182.07:52:29.54#ibcon#read 4, iclass 22, count 0 2006.182.07:52:29.54#ibcon#about to read 5, iclass 22, count 0 2006.182.07:52:29.54#ibcon#read 5, iclass 22, count 0 2006.182.07:52:29.54#ibcon#about to read 6, iclass 22, count 0 2006.182.07:52:29.54#ibcon#read 6, iclass 22, count 0 2006.182.07:52:29.54#ibcon#end of sib2, iclass 22, count 0 2006.182.07:52:29.54#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:52:29.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:52:29.54#ibcon#[25=USB\r\n] 2006.182.07:52:29.54#ibcon#*before write, iclass 22, count 0 2006.182.07:52:29.54#ibcon#enter sib2, iclass 22, count 0 2006.182.07:52:29.54#ibcon#flushed, iclass 22, count 0 2006.182.07:52:29.54#ibcon#about to write, iclass 22, count 0 2006.182.07:52:29.54#ibcon#wrote, iclass 22, count 0 2006.182.07:52:29.54#ibcon#about to read 3, iclass 22, count 0 2006.182.07:52:29.57#ibcon#read 3, iclass 22, count 0 2006.182.07:52:29.57#ibcon#about to read 4, iclass 22, count 0 2006.182.07:52:29.57#ibcon#read 4, iclass 22, count 0 2006.182.07:52:29.57#ibcon#about to read 5, iclass 22, count 0 2006.182.07:52:29.57#ibcon#read 5, iclass 22, count 0 2006.182.07:52:29.57#ibcon#about to read 6, iclass 22, count 0 2006.182.07:52:29.57#ibcon#read 6, iclass 22, count 0 2006.182.07:52:29.57#ibcon#end of sib2, iclass 22, count 0 2006.182.07:52:29.57#ibcon#*after write, iclass 22, count 0 2006.182.07:52:29.57#ibcon#*before return 0, iclass 22, count 0 2006.182.07:52:29.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:29.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:29.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:52:29.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:52:29.57$vc4f8/valo=6,772.99 2006.182.07:52:29.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.07:52:29.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.07:52:29.57#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:29.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:29.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:29.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:29.57#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:52:29.57#ibcon#first serial, iclass 24, count 0 2006.182.07:52:29.57#ibcon#enter sib2, iclass 24, count 0 2006.182.07:52:29.57#ibcon#flushed, iclass 24, count 0 2006.182.07:52:29.57#ibcon#about to write, iclass 24, count 0 2006.182.07:52:29.57#ibcon#wrote, iclass 24, count 0 2006.182.07:52:29.57#ibcon#about to read 3, iclass 24, count 0 2006.182.07:52:29.59#ibcon#read 3, iclass 24, count 0 2006.182.07:52:29.59#ibcon#about to read 4, iclass 24, count 0 2006.182.07:52:29.59#ibcon#read 4, iclass 24, count 0 2006.182.07:52:29.59#ibcon#about to read 5, iclass 24, count 0 2006.182.07:52:29.59#ibcon#read 5, iclass 24, count 0 2006.182.07:52:29.59#ibcon#about to read 6, iclass 24, count 0 2006.182.07:52:29.59#ibcon#read 6, iclass 24, count 0 2006.182.07:52:29.59#ibcon#end of sib2, iclass 24, count 0 2006.182.07:52:29.59#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:52:29.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:52:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:52:29.59#ibcon#*before write, iclass 24, count 0 2006.182.07:52:29.59#ibcon#enter sib2, iclass 24, count 0 2006.182.07:52:29.59#ibcon#flushed, iclass 24, count 0 2006.182.07:52:29.59#ibcon#about to write, iclass 24, count 0 2006.182.07:52:29.59#ibcon#wrote, iclass 24, count 0 2006.182.07:52:29.59#ibcon#about to read 3, iclass 24, count 0 2006.182.07:52:29.64#ibcon#read 3, iclass 24, count 0 2006.182.07:52:29.64#ibcon#about to read 4, iclass 24, count 0 2006.182.07:52:29.64#ibcon#read 4, iclass 24, count 0 2006.182.07:52:29.64#ibcon#about to read 5, iclass 24, count 0 2006.182.07:52:29.64#ibcon#read 5, iclass 24, count 0 2006.182.07:52:29.64#ibcon#about to read 6, iclass 24, count 0 2006.182.07:52:29.64#ibcon#read 6, iclass 24, count 0 2006.182.07:52:29.64#ibcon#end of sib2, iclass 24, count 0 2006.182.07:52:29.64#ibcon#*after write, iclass 24, count 0 2006.182.07:52:29.64#ibcon#*before return 0, iclass 24, count 0 2006.182.07:52:29.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:29.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:29.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:52:29.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:52:29.64$vc4f8/va=6,6 2006.182.07:52:29.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.07:52:29.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.07:52:29.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:29.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:52:29.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:52:29.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:52:29.69#ibcon#enter wrdev, iclass 26, count 2 2006.182.07:52:29.69#ibcon#first serial, iclass 26, count 2 2006.182.07:52:29.69#ibcon#enter sib2, iclass 26, count 2 2006.182.07:52:29.69#ibcon#flushed, iclass 26, count 2 2006.182.07:52:29.69#ibcon#about to write, iclass 26, count 2 2006.182.07:52:29.69#ibcon#wrote, iclass 26, count 2 2006.182.07:52:29.69#ibcon#about to read 3, iclass 26, count 2 2006.182.07:52:29.71#ibcon#read 3, iclass 26, count 2 2006.182.07:52:29.71#ibcon#about to read 4, iclass 26, count 2 2006.182.07:52:29.71#ibcon#read 4, iclass 26, count 2 2006.182.07:52:29.71#ibcon#about to read 5, iclass 26, count 2 2006.182.07:52:29.71#ibcon#read 5, iclass 26, count 2 2006.182.07:52:29.71#ibcon#about to read 6, iclass 26, count 2 2006.182.07:52:29.71#ibcon#read 6, iclass 26, count 2 2006.182.07:52:29.71#ibcon#end of sib2, iclass 26, count 2 2006.182.07:52:29.71#ibcon#*mode == 0, iclass 26, count 2 2006.182.07:52:29.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.07:52:29.71#ibcon#[25=AT06-06\r\n] 2006.182.07:52:29.71#ibcon#*before write, iclass 26, count 2 2006.182.07:52:29.71#ibcon#enter sib2, iclass 26, count 2 2006.182.07:52:29.71#ibcon#flushed, iclass 26, count 2 2006.182.07:52:29.71#ibcon#about to write, iclass 26, count 2 2006.182.07:52:29.71#ibcon#wrote, iclass 26, count 2 2006.182.07:52:29.71#ibcon#about to read 3, iclass 26, count 2 2006.182.07:52:29.74#ibcon#read 3, iclass 26, count 2 2006.182.07:52:29.74#ibcon#about to read 4, iclass 26, count 2 2006.182.07:52:29.74#ibcon#read 4, iclass 26, count 2 2006.182.07:52:29.74#ibcon#about to read 5, iclass 26, count 2 2006.182.07:52:29.74#ibcon#read 5, iclass 26, count 2 2006.182.07:52:29.74#ibcon#about to read 6, iclass 26, count 2 2006.182.07:52:29.74#ibcon#read 6, iclass 26, count 2 2006.182.07:52:29.74#ibcon#end of sib2, iclass 26, count 2 2006.182.07:52:29.74#ibcon#*after write, iclass 26, count 2 2006.182.07:52:29.74#ibcon#*before return 0, iclass 26, count 2 2006.182.07:52:29.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:52:29.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.07:52:29.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.07:52:29.74#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:29.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:52:29.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:52:29.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:52:29.86#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:52:29.86#ibcon#first serial, iclass 26, count 0 2006.182.07:52:29.86#ibcon#enter sib2, iclass 26, count 0 2006.182.07:52:29.86#ibcon#flushed, iclass 26, count 0 2006.182.07:52:29.86#ibcon#about to write, iclass 26, count 0 2006.182.07:52:29.86#ibcon#wrote, iclass 26, count 0 2006.182.07:52:29.86#ibcon#about to read 3, iclass 26, count 0 2006.182.07:52:29.88#ibcon#read 3, iclass 26, count 0 2006.182.07:52:29.88#ibcon#about to read 4, iclass 26, count 0 2006.182.07:52:29.88#ibcon#read 4, iclass 26, count 0 2006.182.07:52:29.88#ibcon#about to read 5, iclass 26, count 0 2006.182.07:52:29.88#ibcon#read 5, iclass 26, count 0 2006.182.07:52:29.88#ibcon#about to read 6, iclass 26, count 0 2006.182.07:52:29.88#ibcon#read 6, iclass 26, count 0 2006.182.07:52:29.88#ibcon#end of sib2, iclass 26, count 0 2006.182.07:52:29.88#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:52:29.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:52:29.88#ibcon#[25=USB\r\n] 2006.182.07:52:29.88#ibcon#*before write, iclass 26, count 0 2006.182.07:52:29.88#ibcon#enter sib2, iclass 26, count 0 2006.182.07:52:29.88#ibcon#flushed, iclass 26, count 0 2006.182.07:52:29.88#ibcon#about to write, iclass 26, count 0 2006.182.07:52:29.88#ibcon#wrote, iclass 26, count 0 2006.182.07:52:29.88#ibcon#about to read 3, iclass 26, count 0 2006.182.07:52:29.91#ibcon#read 3, iclass 26, count 0 2006.182.07:52:29.91#ibcon#about to read 4, iclass 26, count 0 2006.182.07:52:29.91#ibcon#read 4, iclass 26, count 0 2006.182.07:52:29.91#ibcon#about to read 5, iclass 26, count 0 2006.182.07:52:29.91#ibcon#read 5, iclass 26, count 0 2006.182.07:52:29.91#ibcon#about to read 6, iclass 26, count 0 2006.182.07:52:29.91#ibcon#read 6, iclass 26, count 0 2006.182.07:52:29.91#ibcon#end of sib2, iclass 26, count 0 2006.182.07:52:29.91#ibcon#*after write, iclass 26, count 0 2006.182.07:52:29.91#ibcon#*before return 0, iclass 26, count 0 2006.182.07:52:29.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:52:29.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.07:52:29.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:52:29.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:52:29.91$vc4f8/valo=7,832.99 2006.182.07:52:29.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.07:52:29.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.07:52:29.91#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:29.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:52:29.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:52:29.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:52:29.91#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:52:29.91#ibcon#first serial, iclass 28, count 0 2006.182.07:52:29.91#ibcon#enter sib2, iclass 28, count 0 2006.182.07:52:29.91#ibcon#flushed, iclass 28, count 0 2006.182.07:52:29.91#ibcon#about to write, iclass 28, count 0 2006.182.07:52:29.91#ibcon#wrote, iclass 28, count 0 2006.182.07:52:29.91#ibcon#about to read 3, iclass 28, count 0 2006.182.07:52:29.93#ibcon#read 3, iclass 28, count 0 2006.182.07:52:29.93#ibcon#about to read 4, iclass 28, count 0 2006.182.07:52:29.93#ibcon#read 4, iclass 28, count 0 2006.182.07:52:29.93#ibcon#about to read 5, iclass 28, count 0 2006.182.07:52:29.93#ibcon#read 5, iclass 28, count 0 2006.182.07:52:29.93#ibcon#about to read 6, iclass 28, count 0 2006.182.07:52:29.93#ibcon#read 6, iclass 28, count 0 2006.182.07:52:29.93#ibcon#end of sib2, iclass 28, count 0 2006.182.07:52:29.93#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:52:29.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:52:29.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:52:29.93#ibcon#*before write, iclass 28, count 0 2006.182.07:52:29.93#ibcon#enter sib2, iclass 28, count 0 2006.182.07:52:29.93#ibcon#flushed, iclass 28, count 0 2006.182.07:52:29.93#ibcon#about to write, iclass 28, count 0 2006.182.07:52:29.93#ibcon#wrote, iclass 28, count 0 2006.182.07:52:29.93#ibcon#about to read 3, iclass 28, count 0 2006.182.07:52:29.97#ibcon#read 3, iclass 28, count 0 2006.182.07:52:29.97#ibcon#about to read 4, iclass 28, count 0 2006.182.07:52:29.97#ibcon#read 4, iclass 28, count 0 2006.182.07:52:29.97#ibcon#about to read 5, iclass 28, count 0 2006.182.07:52:29.97#ibcon#read 5, iclass 28, count 0 2006.182.07:52:29.97#ibcon#about to read 6, iclass 28, count 0 2006.182.07:52:29.97#ibcon#read 6, iclass 28, count 0 2006.182.07:52:29.97#ibcon#end of sib2, iclass 28, count 0 2006.182.07:52:29.97#ibcon#*after write, iclass 28, count 0 2006.182.07:52:29.97#ibcon#*before return 0, iclass 28, count 0 2006.182.07:52:29.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:52:29.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.07:52:29.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:52:29.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:52:29.97$vc4f8/va=7,6 2006.182.07:52:29.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.07:52:29.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.07:52:29.97#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:29.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:52:30.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:52:30.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:52:30.03#ibcon#enter wrdev, iclass 30, count 2 2006.182.07:52:30.03#ibcon#first serial, iclass 30, count 2 2006.182.07:52:30.03#ibcon#enter sib2, iclass 30, count 2 2006.182.07:52:30.03#ibcon#flushed, iclass 30, count 2 2006.182.07:52:30.03#ibcon#about to write, iclass 30, count 2 2006.182.07:52:30.03#ibcon#wrote, iclass 30, count 2 2006.182.07:52:30.03#ibcon#about to read 3, iclass 30, count 2 2006.182.07:52:30.05#ibcon#read 3, iclass 30, count 2 2006.182.07:52:30.05#ibcon#about to read 4, iclass 30, count 2 2006.182.07:52:30.05#ibcon#read 4, iclass 30, count 2 2006.182.07:52:30.05#ibcon#about to read 5, iclass 30, count 2 2006.182.07:52:30.05#ibcon#read 5, iclass 30, count 2 2006.182.07:52:30.05#ibcon#about to read 6, iclass 30, count 2 2006.182.07:52:30.05#ibcon#read 6, iclass 30, count 2 2006.182.07:52:30.05#ibcon#end of sib2, iclass 30, count 2 2006.182.07:52:30.05#ibcon#*mode == 0, iclass 30, count 2 2006.182.07:52:30.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.07:52:30.05#ibcon#[25=AT07-06\r\n] 2006.182.07:52:30.05#ibcon#*before write, iclass 30, count 2 2006.182.07:52:30.05#ibcon#enter sib2, iclass 30, count 2 2006.182.07:52:30.05#ibcon#flushed, iclass 30, count 2 2006.182.07:52:30.05#ibcon#about to write, iclass 30, count 2 2006.182.07:52:30.05#ibcon#wrote, iclass 30, count 2 2006.182.07:52:30.05#ibcon#about to read 3, iclass 30, count 2 2006.182.07:52:30.08#ibcon#read 3, iclass 30, count 2 2006.182.07:52:30.08#ibcon#about to read 4, iclass 30, count 2 2006.182.07:52:30.08#ibcon#read 4, iclass 30, count 2 2006.182.07:52:30.08#ibcon#about to read 5, iclass 30, count 2 2006.182.07:52:30.08#ibcon#read 5, iclass 30, count 2 2006.182.07:52:30.08#ibcon#about to read 6, iclass 30, count 2 2006.182.07:52:30.08#ibcon#read 6, iclass 30, count 2 2006.182.07:52:30.08#ibcon#end of sib2, iclass 30, count 2 2006.182.07:52:30.08#ibcon#*after write, iclass 30, count 2 2006.182.07:52:30.08#ibcon#*before return 0, iclass 30, count 2 2006.182.07:52:30.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:52:30.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.07:52:30.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.07:52:30.08#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:30.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:52:30.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:52:30.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:52:30.20#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:52:30.20#ibcon#first serial, iclass 30, count 0 2006.182.07:52:30.20#ibcon#enter sib2, iclass 30, count 0 2006.182.07:52:30.20#ibcon#flushed, iclass 30, count 0 2006.182.07:52:30.20#ibcon#about to write, iclass 30, count 0 2006.182.07:52:30.20#ibcon#wrote, iclass 30, count 0 2006.182.07:52:30.20#ibcon#about to read 3, iclass 30, count 0 2006.182.07:52:30.22#ibcon#read 3, iclass 30, count 0 2006.182.07:52:30.22#ibcon#about to read 4, iclass 30, count 0 2006.182.07:52:30.22#ibcon#read 4, iclass 30, count 0 2006.182.07:52:30.22#ibcon#about to read 5, iclass 30, count 0 2006.182.07:52:30.22#ibcon#read 5, iclass 30, count 0 2006.182.07:52:30.22#ibcon#about to read 6, iclass 30, count 0 2006.182.07:52:30.22#ibcon#read 6, iclass 30, count 0 2006.182.07:52:30.22#ibcon#end of sib2, iclass 30, count 0 2006.182.07:52:30.22#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:52:30.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:52:30.22#ibcon#[25=USB\r\n] 2006.182.07:52:30.22#ibcon#*before write, iclass 30, count 0 2006.182.07:52:30.22#ibcon#enter sib2, iclass 30, count 0 2006.182.07:52:30.22#ibcon#flushed, iclass 30, count 0 2006.182.07:52:30.22#ibcon#about to write, iclass 30, count 0 2006.182.07:52:30.22#ibcon#wrote, iclass 30, count 0 2006.182.07:52:30.22#ibcon#about to read 3, iclass 30, count 0 2006.182.07:52:30.25#ibcon#read 3, iclass 30, count 0 2006.182.07:52:30.25#ibcon#about to read 4, iclass 30, count 0 2006.182.07:52:30.25#ibcon#read 4, iclass 30, count 0 2006.182.07:52:30.25#ibcon#about to read 5, iclass 30, count 0 2006.182.07:52:30.25#ibcon#read 5, iclass 30, count 0 2006.182.07:52:30.25#ibcon#about to read 6, iclass 30, count 0 2006.182.07:52:30.25#ibcon#read 6, iclass 30, count 0 2006.182.07:52:30.25#ibcon#end of sib2, iclass 30, count 0 2006.182.07:52:30.25#ibcon#*after write, iclass 30, count 0 2006.182.07:52:30.25#ibcon#*before return 0, iclass 30, count 0 2006.182.07:52:30.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:52:30.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.07:52:30.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:52:30.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:52:30.25$vc4f8/valo=8,852.99 2006.182.07:52:30.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.07:52:30.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.07:52:30.25#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:30.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:52:30.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:52:30.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:52:30.25#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:52:30.25#ibcon#first serial, iclass 32, count 0 2006.182.07:52:30.25#ibcon#enter sib2, iclass 32, count 0 2006.182.07:52:30.25#ibcon#flushed, iclass 32, count 0 2006.182.07:52:30.25#ibcon#about to write, iclass 32, count 0 2006.182.07:52:30.25#ibcon#wrote, iclass 32, count 0 2006.182.07:52:30.25#ibcon#about to read 3, iclass 32, count 0 2006.182.07:52:30.27#ibcon#read 3, iclass 32, count 0 2006.182.07:52:30.27#ibcon#about to read 4, iclass 32, count 0 2006.182.07:52:30.27#ibcon#read 4, iclass 32, count 0 2006.182.07:52:30.27#ibcon#about to read 5, iclass 32, count 0 2006.182.07:52:30.27#ibcon#read 5, iclass 32, count 0 2006.182.07:52:30.27#ibcon#about to read 6, iclass 32, count 0 2006.182.07:52:30.27#ibcon#read 6, iclass 32, count 0 2006.182.07:52:30.27#ibcon#end of sib2, iclass 32, count 0 2006.182.07:52:30.27#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:52:30.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:52:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:52:30.27#ibcon#*before write, iclass 32, count 0 2006.182.07:52:30.27#ibcon#enter sib2, iclass 32, count 0 2006.182.07:52:30.27#ibcon#flushed, iclass 32, count 0 2006.182.07:52:30.27#ibcon#about to write, iclass 32, count 0 2006.182.07:52:30.27#ibcon#wrote, iclass 32, count 0 2006.182.07:52:30.27#ibcon#about to read 3, iclass 32, count 0 2006.182.07:52:30.31#ibcon#read 3, iclass 32, count 0 2006.182.07:52:30.31#ibcon#about to read 4, iclass 32, count 0 2006.182.07:52:30.31#ibcon#read 4, iclass 32, count 0 2006.182.07:52:30.31#ibcon#about to read 5, iclass 32, count 0 2006.182.07:52:30.31#ibcon#read 5, iclass 32, count 0 2006.182.07:52:30.31#ibcon#about to read 6, iclass 32, count 0 2006.182.07:52:30.31#ibcon#read 6, iclass 32, count 0 2006.182.07:52:30.31#ibcon#end of sib2, iclass 32, count 0 2006.182.07:52:30.31#ibcon#*after write, iclass 32, count 0 2006.182.07:52:30.31#ibcon#*before return 0, iclass 32, count 0 2006.182.07:52:30.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:52:30.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.07:52:30.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:52:30.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:52:30.31$vc4f8/va=8,7 2006.182.07:52:30.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.07:52:30.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.07:52:30.31#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:30.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:52:30.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:52:30.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:52:30.37#ibcon#enter wrdev, iclass 34, count 2 2006.182.07:52:30.37#ibcon#first serial, iclass 34, count 2 2006.182.07:52:30.37#ibcon#enter sib2, iclass 34, count 2 2006.182.07:52:30.37#ibcon#flushed, iclass 34, count 2 2006.182.07:52:30.37#ibcon#about to write, iclass 34, count 2 2006.182.07:52:30.37#ibcon#wrote, iclass 34, count 2 2006.182.07:52:30.37#ibcon#about to read 3, iclass 34, count 2 2006.182.07:52:30.39#ibcon#read 3, iclass 34, count 2 2006.182.07:52:30.39#ibcon#about to read 4, iclass 34, count 2 2006.182.07:52:30.39#ibcon#read 4, iclass 34, count 2 2006.182.07:52:30.39#ibcon#about to read 5, iclass 34, count 2 2006.182.07:52:30.39#ibcon#read 5, iclass 34, count 2 2006.182.07:52:30.39#ibcon#about to read 6, iclass 34, count 2 2006.182.07:52:30.39#ibcon#read 6, iclass 34, count 2 2006.182.07:52:30.39#ibcon#end of sib2, iclass 34, count 2 2006.182.07:52:30.39#ibcon#*mode == 0, iclass 34, count 2 2006.182.07:52:30.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.07:52:30.39#ibcon#[25=AT08-07\r\n] 2006.182.07:52:30.39#ibcon#*before write, iclass 34, count 2 2006.182.07:52:30.39#ibcon#enter sib2, iclass 34, count 2 2006.182.07:52:30.39#ibcon#flushed, iclass 34, count 2 2006.182.07:52:30.39#ibcon#about to write, iclass 34, count 2 2006.182.07:52:30.39#ibcon#wrote, iclass 34, count 2 2006.182.07:52:30.39#ibcon#about to read 3, iclass 34, count 2 2006.182.07:52:30.42#ibcon#read 3, iclass 34, count 2 2006.182.07:52:30.42#ibcon#about to read 4, iclass 34, count 2 2006.182.07:52:30.42#ibcon#read 4, iclass 34, count 2 2006.182.07:52:30.42#ibcon#about to read 5, iclass 34, count 2 2006.182.07:52:30.42#ibcon#read 5, iclass 34, count 2 2006.182.07:52:30.42#ibcon#about to read 6, iclass 34, count 2 2006.182.07:52:30.42#ibcon#read 6, iclass 34, count 2 2006.182.07:52:30.42#ibcon#end of sib2, iclass 34, count 2 2006.182.07:52:30.42#ibcon#*after write, iclass 34, count 2 2006.182.07:52:30.42#ibcon#*before return 0, iclass 34, count 2 2006.182.07:52:30.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:52:30.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.07:52:30.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.07:52:30.42#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:30.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:52:30.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:52:30.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:52:30.54#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:52:30.54#ibcon#first serial, iclass 34, count 0 2006.182.07:52:30.54#ibcon#enter sib2, iclass 34, count 0 2006.182.07:52:30.54#ibcon#flushed, iclass 34, count 0 2006.182.07:52:30.54#ibcon#about to write, iclass 34, count 0 2006.182.07:52:30.54#ibcon#wrote, iclass 34, count 0 2006.182.07:52:30.54#ibcon#about to read 3, iclass 34, count 0 2006.182.07:52:30.56#ibcon#read 3, iclass 34, count 0 2006.182.07:52:30.56#ibcon#about to read 4, iclass 34, count 0 2006.182.07:52:30.56#ibcon#read 4, iclass 34, count 0 2006.182.07:52:30.56#ibcon#about to read 5, iclass 34, count 0 2006.182.07:52:30.56#ibcon#read 5, iclass 34, count 0 2006.182.07:52:30.56#ibcon#about to read 6, iclass 34, count 0 2006.182.07:52:30.56#ibcon#read 6, iclass 34, count 0 2006.182.07:52:30.56#ibcon#end of sib2, iclass 34, count 0 2006.182.07:52:30.56#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:52:30.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:52:30.56#ibcon#[25=USB\r\n] 2006.182.07:52:30.56#ibcon#*before write, iclass 34, count 0 2006.182.07:52:30.56#ibcon#enter sib2, iclass 34, count 0 2006.182.07:52:30.56#ibcon#flushed, iclass 34, count 0 2006.182.07:52:30.56#ibcon#about to write, iclass 34, count 0 2006.182.07:52:30.56#ibcon#wrote, iclass 34, count 0 2006.182.07:52:30.56#ibcon#about to read 3, iclass 34, count 0 2006.182.07:52:30.59#ibcon#read 3, iclass 34, count 0 2006.182.07:52:30.59#ibcon#about to read 4, iclass 34, count 0 2006.182.07:52:30.59#ibcon#read 4, iclass 34, count 0 2006.182.07:52:30.59#ibcon#about to read 5, iclass 34, count 0 2006.182.07:52:30.59#ibcon#read 5, iclass 34, count 0 2006.182.07:52:30.59#ibcon#about to read 6, iclass 34, count 0 2006.182.07:52:30.59#ibcon#read 6, iclass 34, count 0 2006.182.07:52:30.59#ibcon#end of sib2, iclass 34, count 0 2006.182.07:52:30.59#ibcon#*after write, iclass 34, count 0 2006.182.07:52:30.59#ibcon#*before return 0, iclass 34, count 0 2006.182.07:52:30.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:52:30.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.07:52:30.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:52:30.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:52:30.59$vc4f8/vblo=1,632.99 2006.182.07:52:30.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.07:52:30.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.07:52:30.59#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:30.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:52:30.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:52:30.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:52:30.59#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:52:30.59#ibcon#first serial, iclass 36, count 0 2006.182.07:52:30.59#ibcon#enter sib2, iclass 36, count 0 2006.182.07:52:30.59#ibcon#flushed, iclass 36, count 0 2006.182.07:52:30.59#ibcon#about to write, iclass 36, count 0 2006.182.07:52:30.59#ibcon#wrote, iclass 36, count 0 2006.182.07:52:30.59#ibcon#about to read 3, iclass 36, count 0 2006.182.07:52:30.61#ibcon#read 3, iclass 36, count 0 2006.182.07:52:30.61#ibcon#about to read 4, iclass 36, count 0 2006.182.07:52:30.61#ibcon#read 4, iclass 36, count 0 2006.182.07:52:30.61#ibcon#about to read 5, iclass 36, count 0 2006.182.07:52:30.61#ibcon#read 5, iclass 36, count 0 2006.182.07:52:30.61#ibcon#about to read 6, iclass 36, count 0 2006.182.07:52:30.61#ibcon#read 6, iclass 36, count 0 2006.182.07:52:30.61#ibcon#end of sib2, iclass 36, count 0 2006.182.07:52:30.61#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:52:30.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:52:30.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:52:30.61#ibcon#*before write, iclass 36, count 0 2006.182.07:52:30.61#ibcon#enter sib2, iclass 36, count 0 2006.182.07:52:30.61#ibcon#flushed, iclass 36, count 0 2006.182.07:52:30.61#ibcon#about to write, iclass 36, count 0 2006.182.07:52:30.61#ibcon#wrote, iclass 36, count 0 2006.182.07:52:30.61#ibcon#about to read 3, iclass 36, count 0 2006.182.07:52:30.65#ibcon#read 3, iclass 36, count 0 2006.182.07:52:30.65#ibcon#about to read 4, iclass 36, count 0 2006.182.07:52:30.65#ibcon#read 4, iclass 36, count 0 2006.182.07:52:30.65#ibcon#about to read 5, iclass 36, count 0 2006.182.07:52:30.65#ibcon#read 5, iclass 36, count 0 2006.182.07:52:30.65#ibcon#about to read 6, iclass 36, count 0 2006.182.07:52:30.65#ibcon#read 6, iclass 36, count 0 2006.182.07:52:30.65#ibcon#end of sib2, iclass 36, count 0 2006.182.07:52:30.65#ibcon#*after write, iclass 36, count 0 2006.182.07:52:30.65#ibcon#*before return 0, iclass 36, count 0 2006.182.07:52:30.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:52:30.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.07:52:30.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:52:30.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:52:30.65$vc4f8/vb=1,4 2006.182.07:52:30.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.07:52:30.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.07:52:30.65#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:30.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:52:30.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:52:30.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:52:30.65#ibcon#enter wrdev, iclass 38, count 2 2006.182.07:52:30.65#ibcon#first serial, iclass 38, count 2 2006.182.07:52:30.65#ibcon#enter sib2, iclass 38, count 2 2006.182.07:52:30.65#ibcon#flushed, iclass 38, count 2 2006.182.07:52:30.65#ibcon#about to write, iclass 38, count 2 2006.182.07:52:30.65#ibcon#wrote, iclass 38, count 2 2006.182.07:52:30.65#ibcon#about to read 3, iclass 38, count 2 2006.182.07:52:30.67#ibcon#read 3, iclass 38, count 2 2006.182.07:52:30.67#ibcon#about to read 4, iclass 38, count 2 2006.182.07:52:30.67#ibcon#read 4, iclass 38, count 2 2006.182.07:52:30.67#ibcon#about to read 5, iclass 38, count 2 2006.182.07:52:30.67#ibcon#read 5, iclass 38, count 2 2006.182.07:52:30.67#ibcon#about to read 6, iclass 38, count 2 2006.182.07:52:30.67#ibcon#read 6, iclass 38, count 2 2006.182.07:52:30.67#ibcon#end of sib2, iclass 38, count 2 2006.182.07:52:30.67#ibcon#*mode == 0, iclass 38, count 2 2006.182.07:52:30.67#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.07:52:30.67#ibcon#[27=AT01-04\r\n] 2006.182.07:52:30.67#ibcon#*before write, iclass 38, count 2 2006.182.07:52:30.67#ibcon#enter sib2, iclass 38, count 2 2006.182.07:52:30.67#ibcon#flushed, iclass 38, count 2 2006.182.07:52:30.67#ibcon#about to write, iclass 38, count 2 2006.182.07:52:30.67#ibcon#wrote, iclass 38, count 2 2006.182.07:52:30.67#ibcon#about to read 3, iclass 38, count 2 2006.182.07:52:30.70#ibcon#read 3, iclass 38, count 2 2006.182.07:52:30.70#ibcon#about to read 4, iclass 38, count 2 2006.182.07:52:30.70#ibcon#read 4, iclass 38, count 2 2006.182.07:52:30.70#ibcon#about to read 5, iclass 38, count 2 2006.182.07:52:30.70#ibcon#read 5, iclass 38, count 2 2006.182.07:52:30.70#ibcon#about to read 6, iclass 38, count 2 2006.182.07:52:30.70#ibcon#read 6, iclass 38, count 2 2006.182.07:52:30.70#ibcon#end of sib2, iclass 38, count 2 2006.182.07:52:30.70#ibcon#*after write, iclass 38, count 2 2006.182.07:52:30.70#ibcon#*before return 0, iclass 38, count 2 2006.182.07:52:30.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:52:30.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.07:52:30.70#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.07:52:30.70#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:30.70#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:52:30.82#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:52:30.82#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:52:30.82#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:52:30.82#ibcon#first serial, iclass 38, count 0 2006.182.07:52:30.82#ibcon#enter sib2, iclass 38, count 0 2006.182.07:52:30.82#ibcon#flushed, iclass 38, count 0 2006.182.07:52:30.82#ibcon#about to write, iclass 38, count 0 2006.182.07:52:30.82#ibcon#wrote, iclass 38, count 0 2006.182.07:52:30.82#ibcon#about to read 3, iclass 38, count 0 2006.182.07:52:30.84#ibcon#read 3, iclass 38, count 0 2006.182.07:52:30.84#ibcon#about to read 4, iclass 38, count 0 2006.182.07:52:30.84#ibcon#read 4, iclass 38, count 0 2006.182.07:52:30.84#ibcon#about to read 5, iclass 38, count 0 2006.182.07:52:30.84#ibcon#read 5, iclass 38, count 0 2006.182.07:52:30.84#ibcon#about to read 6, iclass 38, count 0 2006.182.07:52:30.84#ibcon#read 6, iclass 38, count 0 2006.182.07:52:30.84#ibcon#end of sib2, iclass 38, count 0 2006.182.07:52:30.84#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:52:30.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:52:30.84#ibcon#[27=USB\r\n] 2006.182.07:52:30.84#ibcon#*before write, iclass 38, count 0 2006.182.07:52:30.84#ibcon#enter sib2, iclass 38, count 0 2006.182.07:52:30.84#ibcon#flushed, iclass 38, count 0 2006.182.07:52:30.84#ibcon#about to write, iclass 38, count 0 2006.182.07:52:30.84#ibcon#wrote, iclass 38, count 0 2006.182.07:52:30.84#ibcon#about to read 3, iclass 38, count 0 2006.182.07:52:30.87#ibcon#read 3, iclass 38, count 0 2006.182.07:52:30.87#ibcon#about to read 4, iclass 38, count 0 2006.182.07:52:30.87#ibcon#read 4, iclass 38, count 0 2006.182.07:52:30.87#ibcon#about to read 5, iclass 38, count 0 2006.182.07:52:30.87#ibcon#read 5, iclass 38, count 0 2006.182.07:52:30.87#ibcon#about to read 6, iclass 38, count 0 2006.182.07:52:30.87#ibcon#read 6, iclass 38, count 0 2006.182.07:52:30.87#ibcon#end of sib2, iclass 38, count 0 2006.182.07:52:30.87#ibcon#*after write, iclass 38, count 0 2006.182.07:52:30.87#ibcon#*before return 0, iclass 38, count 0 2006.182.07:52:30.87#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:52:30.87#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.07:52:30.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:52:30.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:52:30.87$vc4f8/vblo=2,640.99 2006.182.07:52:30.87#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.07:52:30.87#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.07:52:30.87#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:30.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:30.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:30.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:30.87#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:52:30.87#ibcon#first serial, iclass 40, count 0 2006.182.07:52:30.87#ibcon#enter sib2, iclass 40, count 0 2006.182.07:52:30.87#ibcon#flushed, iclass 40, count 0 2006.182.07:52:30.87#ibcon#about to write, iclass 40, count 0 2006.182.07:52:30.87#ibcon#wrote, iclass 40, count 0 2006.182.07:52:30.87#ibcon#about to read 3, iclass 40, count 0 2006.182.07:52:30.89#ibcon#read 3, iclass 40, count 0 2006.182.07:52:30.89#ibcon#about to read 4, iclass 40, count 0 2006.182.07:52:30.89#ibcon#read 4, iclass 40, count 0 2006.182.07:52:30.89#ibcon#about to read 5, iclass 40, count 0 2006.182.07:52:30.89#ibcon#read 5, iclass 40, count 0 2006.182.07:52:30.89#ibcon#about to read 6, iclass 40, count 0 2006.182.07:52:30.89#ibcon#read 6, iclass 40, count 0 2006.182.07:52:30.89#ibcon#end of sib2, iclass 40, count 0 2006.182.07:52:30.89#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:52:30.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:52:30.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:52:30.89#ibcon#*before write, iclass 40, count 0 2006.182.07:52:30.89#ibcon#enter sib2, iclass 40, count 0 2006.182.07:52:30.89#ibcon#flushed, iclass 40, count 0 2006.182.07:52:30.89#ibcon#about to write, iclass 40, count 0 2006.182.07:52:30.89#ibcon#wrote, iclass 40, count 0 2006.182.07:52:30.89#ibcon#about to read 3, iclass 40, count 0 2006.182.07:52:30.93#ibcon#read 3, iclass 40, count 0 2006.182.07:52:30.93#ibcon#about to read 4, iclass 40, count 0 2006.182.07:52:30.93#ibcon#read 4, iclass 40, count 0 2006.182.07:52:30.93#ibcon#about to read 5, iclass 40, count 0 2006.182.07:52:30.93#ibcon#read 5, iclass 40, count 0 2006.182.07:52:30.93#ibcon#about to read 6, iclass 40, count 0 2006.182.07:52:30.93#ibcon#read 6, iclass 40, count 0 2006.182.07:52:30.93#ibcon#end of sib2, iclass 40, count 0 2006.182.07:52:30.93#ibcon#*after write, iclass 40, count 0 2006.182.07:52:30.93#ibcon#*before return 0, iclass 40, count 0 2006.182.07:52:30.93#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:30.93#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.07:52:30.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:52:30.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:52:30.93$vc4f8/vb=2,4 2006.182.07:52:30.93#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.07:52:30.93#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.07:52:30.93#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:30.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:30.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:30.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:30.99#ibcon#enter wrdev, iclass 4, count 2 2006.182.07:52:30.99#ibcon#first serial, iclass 4, count 2 2006.182.07:52:30.99#ibcon#enter sib2, iclass 4, count 2 2006.182.07:52:30.99#ibcon#flushed, iclass 4, count 2 2006.182.07:52:30.99#ibcon#about to write, iclass 4, count 2 2006.182.07:52:30.99#ibcon#wrote, iclass 4, count 2 2006.182.07:52:30.99#ibcon#about to read 3, iclass 4, count 2 2006.182.07:52:31.01#ibcon#read 3, iclass 4, count 2 2006.182.07:52:31.01#ibcon#about to read 4, iclass 4, count 2 2006.182.07:52:31.01#ibcon#read 4, iclass 4, count 2 2006.182.07:52:31.01#ibcon#about to read 5, iclass 4, count 2 2006.182.07:52:31.01#ibcon#read 5, iclass 4, count 2 2006.182.07:52:31.01#ibcon#about to read 6, iclass 4, count 2 2006.182.07:52:31.01#ibcon#read 6, iclass 4, count 2 2006.182.07:52:31.01#ibcon#end of sib2, iclass 4, count 2 2006.182.07:52:31.01#ibcon#*mode == 0, iclass 4, count 2 2006.182.07:52:31.01#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.07:52:31.01#ibcon#[27=AT02-04\r\n] 2006.182.07:52:31.01#ibcon#*before write, iclass 4, count 2 2006.182.07:52:31.01#ibcon#enter sib2, iclass 4, count 2 2006.182.07:52:31.01#ibcon#flushed, iclass 4, count 2 2006.182.07:52:31.01#ibcon#about to write, iclass 4, count 2 2006.182.07:52:31.01#ibcon#wrote, iclass 4, count 2 2006.182.07:52:31.01#ibcon#about to read 3, iclass 4, count 2 2006.182.07:52:31.04#ibcon#read 3, iclass 4, count 2 2006.182.07:52:31.04#ibcon#about to read 4, iclass 4, count 2 2006.182.07:52:31.04#ibcon#read 4, iclass 4, count 2 2006.182.07:52:31.04#ibcon#about to read 5, iclass 4, count 2 2006.182.07:52:31.04#ibcon#read 5, iclass 4, count 2 2006.182.07:52:31.04#ibcon#about to read 6, iclass 4, count 2 2006.182.07:52:31.04#ibcon#read 6, iclass 4, count 2 2006.182.07:52:31.04#ibcon#end of sib2, iclass 4, count 2 2006.182.07:52:31.04#ibcon#*after write, iclass 4, count 2 2006.182.07:52:31.04#ibcon#*before return 0, iclass 4, count 2 2006.182.07:52:31.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:31.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.07:52:31.04#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.07:52:31.04#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:31.04#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:31.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:31.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:31.16#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:52:31.16#ibcon#first serial, iclass 4, count 0 2006.182.07:52:31.16#ibcon#enter sib2, iclass 4, count 0 2006.182.07:52:31.16#ibcon#flushed, iclass 4, count 0 2006.182.07:52:31.16#ibcon#about to write, iclass 4, count 0 2006.182.07:52:31.16#ibcon#wrote, iclass 4, count 0 2006.182.07:52:31.16#ibcon#about to read 3, iclass 4, count 0 2006.182.07:52:31.18#ibcon#read 3, iclass 4, count 0 2006.182.07:52:31.18#ibcon#about to read 4, iclass 4, count 0 2006.182.07:52:31.18#ibcon#read 4, iclass 4, count 0 2006.182.07:52:31.18#ibcon#about to read 5, iclass 4, count 0 2006.182.07:52:31.18#ibcon#read 5, iclass 4, count 0 2006.182.07:52:31.18#ibcon#about to read 6, iclass 4, count 0 2006.182.07:52:31.18#ibcon#read 6, iclass 4, count 0 2006.182.07:52:31.18#ibcon#end of sib2, iclass 4, count 0 2006.182.07:52:31.18#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:52:31.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:52:31.18#ibcon#[27=USB\r\n] 2006.182.07:52:31.18#ibcon#*before write, iclass 4, count 0 2006.182.07:52:31.18#ibcon#enter sib2, iclass 4, count 0 2006.182.07:52:31.18#ibcon#flushed, iclass 4, count 0 2006.182.07:52:31.18#ibcon#about to write, iclass 4, count 0 2006.182.07:52:31.18#ibcon#wrote, iclass 4, count 0 2006.182.07:52:31.18#ibcon#about to read 3, iclass 4, count 0 2006.182.07:52:31.21#ibcon#read 3, iclass 4, count 0 2006.182.07:52:31.21#ibcon#about to read 4, iclass 4, count 0 2006.182.07:52:31.21#ibcon#read 4, iclass 4, count 0 2006.182.07:52:31.21#ibcon#about to read 5, iclass 4, count 0 2006.182.07:52:31.21#ibcon#read 5, iclass 4, count 0 2006.182.07:52:31.21#ibcon#about to read 6, iclass 4, count 0 2006.182.07:52:31.21#ibcon#read 6, iclass 4, count 0 2006.182.07:52:31.21#ibcon#end of sib2, iclass 4, count 0 2006.182.07:52:31.21#ibcon#*after write, iclass 4, count 0 2006.182.07:52:31.21#ibcon#*before return 0, iclass 4, count 0 2006.182.07:52:31.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:31.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.07:52:31.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:52:31.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:52:31.21$vc4f8/vblo=3,656.99 2006.182.07:52:31.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.07:52:31.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.07:52:31.21#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:31.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:31.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:31.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:31.21#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:52:31.21#ibcon#first serial, iclass 6, count 0 2006.182.07:52:31.21#ibcon#enter sib2, iclass 6, count 0 2006.182.07:52:31.21#ibcon#flushed, iclass 6, count 0 2006.182.07:52:31.21#ibcon#about to write, iclass 6, count 0 2006.182.07:52:31.21#ibcon#wrote, iclass 6, count 0 2006.182.07:52:31.21#ibcon#about to read 3, iclass 6, count 0 2006.182.07:52:31.23#ibcon#read 3, iclass 6, count 0 2006.182.07:52:31.23#ibcon#about to read 4, iclass 6, count 0 2006.182.07:52:31.23#ibcon#read 4, iclass 6, count 0 2006.182.07:52:31.23#ibcon#about to read 5, iclass 6, count 0 2006.182.07:52:31.23#ibcon#read 5, iclass 6, count 0 2006.182.07:52:31.23#ibcon#about to read 6, iclass 6, count 0 2006.182.07:52:31.23#ibcon#read 6, iclass 6, count 0 2006.182.07:52:31.23#ibcon#end of sib2, iclass 6, count 0 2006.182.07:52:31.23#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:52:31.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:52:31.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:52:31.23#ibcon#*before write, iclass 6, count 0 2006.182.07:52:31.23#ibcon#enter sib2, iclass 6, count 0 2006.182.07:52:31.23#ibcon#flushed, iclass 6, count 0 2006.182.07:52:31.23#ibcon#about to write, iclass 6, count 0 2006.182.07:52:31.23#ibcon#wrote, iclass 6, count 0 2006.182.07:52:31.23#ibcon#about to read 3, iclass 6, count 0 2006.182.07:52:31.27#ibcon#read 3, iclass 6, count 0 2006.182.07:52:31.27#ibcon#about to read 4, iclass 6, count 0 2006.182.07:52:31.27#ibcon#read 4, iclass 6, count 0 2006.182.07:52:31.27#ibcon#about to read 5, iclass 6, count 0 2006.182.07:52:31.27#ibcon#read 5, iclass 6, count 0 2006.182.07:52:31.27#ibcon#about to read 6, iclass 6, count 0 2006.182.07:52:31.27#ibcon#read 6, iclass 6, count 0 2006.182.07:52:31.27#ibcon#end of sib2, iclass 6, count 0 2006.182.07:52:31.27#ibcon#*after write, iclass 6, count 0 2006.182.07:52:31.27#ibcon#*before return 0, iclass 6, count 0 2006.182.07:52:31.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:31.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.07:52:31.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:52:31.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:52:31.27$vc4f8/vb=3,4 2006.182.07:52:31.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.07:52:31.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.07:52:31.27#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:31.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:31.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:31.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:31.33#ibcon#enter wrdev, iclass 10, count 2 2006.182.07:52:31.33#ibcon#first serial, iclass 10, count 2 2006.182.07:52:31.33#ibcon#enter sib2, iclass 10, count 2 2006.182.07:52:31.33#ibcon#flushed, iclass 10, count 2 2006.182.07:52:31.33#ibcon#about to write, iclass 10, count 2 2006.182.07:52:31.33#ibcon#wrote, iclass 10, count 2 2006.182.07:52:31.33#ibcon#about to read 3, iclass 10, count 2 2006.182.07:52:31.35#ibcon#read 3, iclass 10, count 2 2006.182.07:52:31.35#ibcon#about to read 4, iclass 10, count 2 2006.182.07:52:31.35#ibcon#read 4, iclass 10, count 2 2006.182.07:52:31.35#ibcon#about to read 5, iclass 10, count 2 2006.182.07:52:31.35#ibcon#read 5, iclass 10, count 2 2006.182.07:52:31.35#ibcon#about to read 6, iclass 10, count 2 2006.182.07:52:31.35#ibcon#read 6, iclass 10, count 2 2006.182.07:52:31.35#ibcon#end of sib2, iclass 10, count 2 2006.182.07:52:31.35#ibcon#*mode == 0, iclass 10, count 2 2006.182.07:52:31.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.07:52:31.35#ibcon#[27=AT03-04\r\n] 2006.182.07:52:31.35#ibcon#*before write, iclass 10, count 2 2006.182.07:52:31.35#ibcon#enter sib2, iclass 10, count 2 2006.182.07:52:31.35#ibcon#flushed, iclass 10, count 2 2006.182.07:52:31.35#ibcon#about to write, iclass 10, count 2 2006.182.07:52:31.35#ibcon#wrote, iclass 10, count 2 2006.182.07:52:31.35#ibcon#about to read 3, iclass 10, count 2 2006.182.07:52:31.38#ibcon#read 3, iclass 10, count 2 2006.182.07:52:31.38#ibcon#about to read 4, iclass 10, count 2 2006.182.07:52:31.38#ibcon#read 4, iclass 10, count 2 2006.182.07:52:31.38#ibcon#about to read 5, iclass 10, count 2 2006.182.07:52:31.38#ibcon#read 5, iclass 10, count 2 2006.182.07:52:31.38#ibcon#about to read 6, iclass 10, count 2 2006.182.07:52:31.38#ibcon#read 6, iclass 10, count 2 2006.182.07:52:31.38#ibcon#end of sib2, iclass 10, count 2 2006.182.07:52:31.38#ibcon#*after write, iclass 10, count 2 2006.182.07:52:31.38#ibcon#*before return 0, iclass 10, count 2 2006.182.07:52:31.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:31.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.07:52:31.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.07:52:31.38#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:31.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:31.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:31.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:31.50#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:52:31.50#ibcon#first serial, iclass 10, count 0 2006.182.07:52:31.50#ibcon#enter sib2, iclass 10, count 0 2006.182.07:52:31.50#ibcon#flushed, iclass 10, count 0 2006.182.07:52:31.50#ibcon#about to write, iclass 10, count 0 2006.182.07:52:31.50#ibcon#wrote, iclass 10, count 0 2006.182.07:52:31.50#ibcon#about to read 3, iclass 10, count 0 2006.182.07:52:31.52#ibcon#read 3, iclass 10, count 0 2006.182.07:52:31.52#ibcon#about to read 4, iclass 10, count 0 2006.182.07:52:31.52#ibcon#read 4, iclass 10, count 0 2006.182.07:52:31.52#ibcon#about to read 5, iclass 10, count 0 2006.182.07:52:31.52#ibcon#read 5, iclass 10, count 0 2006.182.07:52:31.52#ibcon#about to read 6, iclass 10, count 0 2006.182.07:52:31.52#ibcon#read 6, iclass 10, count 0 2006.182.07:52:31.52#ibcon#end of sib2, iclass 10, count 0 2006.182.07:52:31.52#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:52:31.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:52:31.52#ibcon#[27=USB\r\n] 2006.182.07:52:31.52#ibcon#*before write, iclass 10, count 0 2006.182.07:52:31.52#ibcon#enter sib2, iclass 10, count 0 2006.182.07:52:31.52#ibcon#flushed, iclass 10, count 0 2006.182.07:52:31.52#ibcon#about to write, iclass 10, count 0 2006.182.07:52:31.52#ibcon#wrote, iclass 10, count 0 2006.182.07:52:31.52#ibcon#about to read 3, iclass 10, count 0 2006.182.07:52:31.55#ibcon#read 3, iclass 10, count 0 2006.182.07:52:31.55#ibcon#about to read 4, iclass 10, count 0 2006.182.07:52:31.55#ibcon#read 4, iclass 10, count 0 2006.182.07:52:31.55#ibcon#about to read 5, iclass 10, count 0 2006.182.07:52:31.55#ibcon#read 5, iclass 10, count 0 2006.182.07:52:31.55#ibcon#about to read 6, iclass 10, count 0 2006.182.07:52:31.55#ibcon#read 6, iclass 10, count 0 2006.182.07:52:31.55#ibcon#end of sib2, iclass 10, count 0 2006.182.07:52:31.55#ibcon#*after write, iclass 10, count 0 2006.182.07:52:31.55#ibcon#*before return 0, iclass 10, count 0 2006.182.07:52:31.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:31.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.07:52:31.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:52:31.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:52:31.55$vc4f8/vblo=4,712.99 2006.182.07:52:31.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.07:52:31.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.07:52:31.55#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:31.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:31.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:31.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:31.55#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:52:31.55#ibcon#first serial, iclass 12, count 0 2006.182.07:52:31.55#ibcon#enter sib2, iclass 12, count 0 2006.182.07:52:31.55#ibcon#flushed, iclass 12, count 0 2006.182.07:52:31.55#ibcon#about to write, iclass 12, count 0 2006.182.07:52:31.55#ibcon#wrote, iclass 12, count 0 2006.182.07:52:31.55#ibcon#about to read 3, iclass 12, count 0 2006.182.07:52:31.57#ibcon#read 3, iclass 12, count 0 2006.182.07:52:31.57#ibcon#about to read 4, iclass 12, count 0 2006.182.07:52:31.57#ibcon#read 4, iclass 12, count 0 2006.182.07:52:31.57#ibcon#about to read 5, iclass 12, count 0 2006.182.07:52:31.57#ibcon#read 5, iclass 12, count 0 2006.182.07:52:31.57#ibcon#about to read 6, iclass 12, count 0 2006.182.07:52:31.57#ibcon#read 6, iclass 12, count 0 2006.182.07:52:31.57#ibcon#end of sib2, iclass 12, count 0 2006.182.07:52:31.57#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:52:31.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:52:31.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:52:31.57#ibcon#*before write, iclass 12, count 0 2006.182.07:52:31.57#ibcon#enter sib2, iclass 12, count 0 2006.182.07:52:31.57#ibcon#flushed, iclass 12, count 0 2006.182.07:52:31.57#ibcon#about to write, iclass 12, count 0 2006.182.07:52:31.57#ibcon#wrote, iclass 12, count 0 2006.182.07:52:31.57#ibcon#about to read 3, iclass 12, count 0 2006.182.07:52:31.61#ibcon#read 3, iclass 12, count 0 2006.182.07:52:31.61#ibcon#about to read 4, iclass 12, count 0 2006.182.07:52:31.61#ibcon#read 4, iclass 12, count 0 2006.182.07:52:31.61#ibcon#about to read 5, iclass 12, count 0 2006.182.07:52:31.61#ibcon#read 5, iclass 12, count 0 2006.182.07:52:31.61#ibcon#about to read 6, iclass 12, count 0 2006.182.07:52:31.61#ibcon#read 6, iclass 12, count 0 2006.182.07:52:31.61#ibcon#end of sib2, iclass 12, count 0 2006.182.07:52:31.61#ibcon#*after write, iclass 12, count 0 2006.182.07:52:31.61#ibcon#*before return 0, iclass 12, count 0 2006.182.07:52:31.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:31.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.07:52:31.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:52:31.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:52:31.61$vc4f8/vb=4,4 2006.182.07:52:31.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.07:52:31.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.07:52:31.61#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:31.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:31.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:31.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:31.67#ibcon#enter wrdev, iclass 14, count 2 2006.182.07:52:31.67#ibcon#first serial, iclass 14, count 2 2006.182.07:52:31.67#ibcon#enter sib2, iclass 14, count 2 2006.182.07:52:31.67#ibcon#flushed, iclass 14, count 2 2006.182.07:52:31.67#ibcon#about to write, iclass 14, count 2 2006.182.07:52:31.67#ibcon#wrote, iclass 14, count 2 2006.182.07:52:31.67#ibcon#about to read 3, iclass 14, count 2 2006.182.07:52:31.69#ibcon#read 3, iclass 14, count 2 2006.182.07:52:31.69#ibcon#about to read 4, iclass 14, count 2 2006.182.07:52:31.69#ibcon#read 4, iclass 14, count 2 2006.182.07:52:31.69#ibcon#about to read 5, iclass 14, count 2 2006.182.07:52:31.69#ibcon#read 5, iclass 14, count 2 2006.182.07:52:31.69#ibcon#about to read 6, iclass 14, count 2 2006.182.07:52:31.69#ibcon#read 6, iclass 14, count 2 2006.182.07:52:31.69#ibcon#end of sib2, iclass 14, count 2 2006.182.07:52:31.69#ibcon#*mode == 0, iclass 14, count 2 2006.182.07:52:31.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.07:52:31.69#ibcon#[27=AT04-04\r\n] 2006.182.07:52:31.69#ibcon#*before write, iclass 14, count 2 2006.182.07:52:31.69#ibcon#enter sib2, iclass 14, count 2 2006.182.07:52:31.69#ibcon#flushed, iclass 14, count 2 2006.182.07:52:31.69#ibcon#about to write, iclass 14, count 2 2006.182.07:52:31.69#ibcon#wrote, iclass 14, count 2 2006.182.07:52:31.69#ibcon#about to read 3, iclass 14, count 2 2006.182.07:52:31.72#ibcon#read 3, iclass 14, count 2 2006.182.07:52:31.72#ibcon#about to read 4, iclass 14, count 2 2006.182.07:52:31.72#ibcon#read 4, iclass 14, count 2 2006.182.07:52:31.72#ibcon#about to read 5, iclass 14, count 2 2006.182.07:52:31.72#ibcon#read 5, iclass 14, count 2 2006.182.07:52:31.72#ibcon#about to read 6, iclass 14, count 2 2006.182.07:52:31.72#ibcon#read 6, iclass 14, count 2 2006.182.07:52:31.72#ibcon#end of sib2, iclass 14, count 2 2006.182.07:52:31.72#ibcon#*after write, iclass 14, count 2 2006.182.07:52:31.72#ibcon#*before return 0, iclass 14, count 2 2006.182.07:52:31.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:31.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.07:52:31.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.07:52:31.72#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:31.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:31.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:31.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:31.84#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:52:31.84#ibcon#first serial, iclass 14, count 0 2006.182.07:52:31.84#ibcon#enter sib2, iclass 14, count 0 2006.182.07:52:31.84#ibcon#flushed, iclass 14, count 0 2006.182.07:52:31.84#ibcon#about to write, iclass 14, count 0 2006.182.07:52:31.84#ibcon#wrote, iclass 14, count 0 2006.182.07:52:31.84#ibcon#about to read 3, iclass 14, count 0 2006.182.07:52:31.86#ibcon#read 3, iclass 14, count 0 2006.182.07:52:31.86#ibcon#about to read 4, iclass 14, count 0 2006.182.07:52:31.86#ibcon#read 4, iclass 14, count 0 2006.182.07:52:31.86#ibcon#about to read 5, iclass 14, count 0 2006.182.07:52:31.86#ibcon#read 5, iclass 14, count 0 2006.182.07:52:31.86#ibcon#about to read 6, iclass 14, count 0 2006.182.07:52:31.86#ibcon#read 6, iclass 14, count 0 2006.182.07:52:31.86#ibcon#end of sib2, iclass 14, count 0 2006.182.07:52:31.86#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:52:31.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:52:31.86#ibcon#[27=USB\r\n] 2006.182.07:52:31.86#ibcon#*before write, iclass 14, count 0 2006.182.07:52:31.86#ibcon#enter sib2, iclass 14, count 0 2006.182.07:52:31.86#ibcon#flushed, iclass 14, count 0 2006.182.07:52:31.86#ibcon#about to write, iclass 14, count 0 2006.182.07:52:31.86#ibcon#wrote, iclass 14, count 0 2006.182.07:52:31.86#ibcon#about to read 3, iclass 14, count 0 2006.182.07:52:31.89#ibcon#read 3, iclass 14, count 0 2006.182.07:52:31.89#ibcon#about to read 4, iclass 14, count 0 2006.182.07:52:31.89#ibcon#read 4, iclass 14, count 0 2006.182.07:52:31.89#ibcon#about to read 5, iclass 14, count 0 2006.182.07:52:31.89#ibcon#read 5, iclass 14, count 0 2006.182.07:52:31.89#ibcon#about to read 6, iclass 14, count 0 2006.182.07:52:31.89#ibcon#read 6, iclass 14, count 0 2006.182.07:52:31.89#ibcon#end of sib2, iclass 14, count 0 2006.182.07:52:31.89#ibcon#*after write, iclass 14, count 0 2006.182.07:52:31.89#ibcon#*before return 0, iclass 14, count 0 2006.182.07:52:31.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:31.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.07:52:31.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:52:31.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:52:31.89$vc4f8/vblo=5,744.99 2006.182.07:52:31.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.07:52:31.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.07:52:31.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:31.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:31.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:31.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:31.89#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:52:31.89#ibcon#first serial, iclass 16, count 0 2006.182.07:52:31.89#ibcon#enter sib2, iclass 16, count 0 2006.182.07:52:31.89#ibcon#flushed, iclass 16, count 0 2006.182.07:52:31.89#ibcon#about to write, iclass 16, count 0 2006.182.07:52:31.89#ibcon#wrote, iclass 16, count 0 2006.182.07:52:31.89#ibcon#about to read 3, iclass 16, count 0 2006.182.07:52:31.91#ibcon#read 3, iclass 16, count 0 2006.182.07:52:31.91#ibcon#about to read 4, iclass 16, count 0 2006.182.07:52:31.91#ibcon#read 4, iclass 16, count 0 2006.182.07:52:31.91#ibcon#about to read 5, iclass 16, count 0 2006.182.07:52:31.91#ibcon#read 5, iclass 16, count 0 2006.182.07:52:31.91#ibcon#about to read 6, iclass 16, count 0 2006.182.07:52:31.91#ibcon#read 6, iclass 16, count 0 2006.182.07:52:31.91#ibcon#end of sib2, iclass 16, count 0 2006.182.07:52:31.91#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:52:31.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:52:31.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:52:31.91#ibcon#*before write, iclass 16, count 0 2006.182.07:52:31.91#ibcon#enter sib2, iclass 16, count 0 2006.182.07:52:31.91#ibcon#flushed, iclass 16, count 0 2006.182.07:52:31.91#ibcon#about to write, iclass 16, count 0 2006.182.07:52:31.91#ibcon#wrote, iclass 16, count 0 2006.182.07:52:31.91#ibcon#about to read 3, iclass 16, count 0 2006.182.07:52:31.96#ibcon#read 3, iclass 16, count 0 2006.182.07:52:31.96#ibcon#about to read 4, iclass 16, count 0 2006.182.07:52:31.96#ibcon#read 4, iclass 16, count 0 2006.182.07:52:31.96#ibcon#about to read 5, iclass 16, count 0 2006.182.07:52:31.96#ibcon#read 5, iclass 16, count 0 2006.182.07:52:31.96#ibcon#about to read 6, iclass 16, count 0 2006.182.07:52:31.96#ibcon#read 6, iclass 16, count 0 2006.182.07:52:31.96#ibcon#end of sib2, iclass 16, count 0 2006.182.07:52:31.96#ibcon#*after write, iclass 16, count 0 2006.182.07:52:31.96#ibcon#*before return 0, iclass 16, count 0 2006.182.07:52:31.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:31.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:52:31.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:52:31.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:52:31.96$vc4f8/vb=5,4 2006.182.07:52:31.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.07:52:31.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.07:52:31.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:31.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:32.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:32.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:32.01#ibcon#enter wrdev, iclass 18, count 2 2006.182.07:52:32.01#ibcon#first serial, iclass 18, count 2 2006.182.07:52:32.01#ibcon#enter sib2, iclass 18, count 2 2006.182.07:52:32.01#ibcon#flushed, iclass 18, count 2 2006.182.07:52:32.01#ibcon#about to write, iclass 18, count 2 2006.182.07:52:32.01#ibcon#wrote, iclass 18, count 2 2006.182.07:52:32.01#ibcon#about to read 3, iclass 18, count 2 2006.182.07:52:32.03#ibcon#read 3, iclass 18, count 2 2006.182.07:52:32.03#ibcon#about to read 4, iclass 18, count 2 2006.182.07:52:32.03#ibcon#read 4, iclass 18, count 2 2006.182.07:52:32.03#ibcon#about to read 5, iclass 18, count 2 2006.182.07:52:32.03#ibcon#read 5, iclass 18, count 2 2006.182.07:52:32.03#ibcon#about to read 6, iclass 18, count 2 2006.182.07:52:32.03#ibcon#read 6, iclass 18, count 2 2006.182.07:52:32.03#ibcon#end of sib2, iclass 18, count 2 2006.182.07:52:32.03#ibcon#*mode == 0, iclass 18, count 2 2006.182.07:52:32.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.07:52:32.03#ibcon#[27=AT05-04\r\n] 2006.182.07:52:32.03#ibcon#*before write, iclass 18, count 2 2006.182.07:52:32.03#ibcon#enter sib2, iclass 18, count 2 2006.182.07:52:32.03#ibcon#flushed, iclass 18, count 2 2006.182.07:52:32.03#ibcon#about to write, iclass 18, count 2 2006.182.07:52:32.03#ibcon#wrote, iclass 18, count 2 2006.182.07:52:32.03#ibcon#about to read 3, iclass 18, count 2 2006.182.07:52:32.06#ibcon#read 3, iclass 18, count 2 2006.182.07:52:32.06#ibcon#about to read 4, iclass 18, count 2 2006.182.07:52:32.06#ibcon#read 4, iclass 18, count 2 2006.182.07:52:32.06#ibcon#about to read 5, iclass 18, count 2 2006.182.07:52:32.06#ibcon#read 5, iclass 18, count 2 2006.182.07:52:32.06#ibcon#about to read 6, iclass 18, count 2 2006.182.07:52:32.06#ibcon#read 6, iclass 18, count 2 2006.182.07:52:32.06#ibcon#end of sib2, iclass 18, count 2 2006.182.07:52:32.06#ibcon#*after write, iclass 18, count 2 2006.182.07:52:32.06#ibcon#*before return 0, iclass 18, count 2 2006.182.07:52:32.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:32.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.07:52:32.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.07:52:32.06#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:32.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:32.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:32.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:32.18#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:52:32.18#ibcon#first serial, iclass 18, count 0 2006.182.07:52:32.18#ibcon#enter sib2, iclass 18, count 0 2006.182.07:52:32.18#ibcon#flushed, iclass 18, count 0 2006.182.07:52:32.18#ibcon#about to write, iclass 18, count 0 2006.182.07:52:32.18#ibcon#wrote, iclass 18, count 0 2006.182.07:52:32.18#ibcon#about to read 3, iclass 18, count 0 2006.182.07:52:32.20#ibcon#read 3, iclass 18, count 0 2006.182.07:52:32.20#ibcon#about to read 4, iclass 18, count 0 2006.182.07:52:32.20#ibcon#read 4, iclass 18, count 0 2006.182.07:52:32.20#ibcon#about to read 5, iclass 18, count 0 2006.182.07:52:32.20#ibcon#read 5, iclass 18, count 0 2006.182.07:52:32.20#ibcon#about to read 6, iclass 18, count 0 2006.182.07:52:32.20#ibcon#read 6, iclass 18, count 0 2006.182.07:52:32.20#ibcon#end of sib2, iclass 18, count 0 2006.182.07:52:32.20#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:52:32.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:52:32.20#ibcon#[27=USB\r\n] 2006.182.07:52:32.20#ibcon#*before write, iclass 18, count 0 2006.182.07:52:32.20#ibcon#enter sib2, iclass 18, count 0 2006.182.07:52:32.20#ibcon#flushed, iclass 18, count 0 2006.182.07:52:32.20#ibcon#about to write, iclass 18, count 0 2006.182.07:52:32.20#ibcon#wrote, iclass 18, count 0 2006.182.07:52:32.20#ibcon#about to read 3, iclass 18, count 0 2006.182.07:52:32.23#ibcon#read 3, iclass 18, count 0 2006.182.07:52:32.23#ibcon#about to read 4, iclass 18, count 0 2006.182.07:52:32.23#ibcon#read 4, iclass 18, count 0 2006.182.07:52:32.23#ibcon#about to read 5, iclass 18, count 0 2006.182.07:52:32.23#ibcon#read 5, iclass 18, count 0 2006.182.07:52:32.23#ibcon#about to read 6, iclass 18, count 0 2006.182.07:52:32.23#ibcon#read 6, iclass 18, count 0 2006.182.07:52:32.23#ibcon#end of sib2, iclass 18, count 0 2006.182.07:52:32.23#ibcon#*after write, iclass 18, count 0 2006.182.07:52:32.23#ibcon#*before return 0, iclass 18, count 0 2006.182.07:52:32.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:32.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.07:52:32.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:52:32.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:52:32.23$vc4f8/vblo=6,752.99 2006.182.07:52:32.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.07:52:32.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.07:52:32.23#ibcon#ireg 17 cls_cnt 0 2006.182.07:52:32.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:32.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:32.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:32.23#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:52:32.23#ibcon#first serial, iclass 20, count 0 2006.182.07:52:32.23#ibcon#enter sib2, iclass 20, count 0 2006.182.07:52:32.23#ibcon#flushed, iclass 20, count 0 2006.182.07:52:32.23#ibcon#about to write, iclass 20, count 0 2006.182.07:52:32.23#ibcon#wrote, iclass 20, count 0 2006.182.07:52:32.23#ibcon#about to read 3, iclass 20, count 0 2006.182.07:52:32.25#ibcon#read 3, iclass 20, count 0 2006.182.07:52:32.25#ibcon#about to read 4, iclass 20, count 0 2006.182.07:52:32.25#ibcon#read 4, iclass 20, count 0 2006.182.07:52:32.25#ibcon#about to read 5, iclass 20, count 0 2006.182.07:52:32.25#ibcon#read 5, iclass 20, count 0 2006.182.07:52:32.25#ibcon#about to read 6, iclass 20, count 0 2006.182.07:52:32.25#ibcon#read 6, iclass 20, count 0 2006.182.07:52:32.25#ibcon#end of sib2, iclass 20, count 0 2006.182.07:52:32.25#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:52:32.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:52:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:52:32.25#ibcon#*before write, iclass 20, count 0 2006.182.07:52:32.25#ibcon#enter sib2, iclass 20, count 0 2006.182.07:52:32.25#ibcon#flushed, iclass 20, count 0 2006.182.07:52:32.25#ibcon#about to write, iclass 20, count 0 2006.182.07:52:32.25#ibcon#wrote, iclass 20, count 0 2006.182.07:52:32.25#ibcon#about to read 3, iclass 20, count 0 2006.182.07:52:32.29#ibcon#read 3, iclass 20, count 0 2006.182.07:52:32.29#ibcon#about to read 4, iclass 20, count 0 2006.182.07:52:32.29#ibcon#read 4, iclass 20, count 0 2006.182.07:52:32.29#ibcon#about to read 5, iclass 20, count 0 2006.182.07:52:32.29#ibcon#read 5, iclass 20, count 0 2006.182.07:52:32.29#ibcon#about to read 6, iclass 20, count 0 2006.182.07:52:32.29#ibcon#read 6, iclass 20, count 0 2006.182.07:52:32.29#ibcon#end of sib2, iclass 20, count 0 2006.182.07:52:32.29#ibcon#*after write, iclass 20, count 0 2006.182.07:52:32.29#ibcon#*before return 0, iclass 20, count 0 2006.182.07:52:32.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:32.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.07:52:32.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:52:32.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:52:32.29$vc4f8/vb=6,4 2006.182.07:52:32.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.07:52:32.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.07:52:32.29#ibcon#ireg 11 cls_cnt 2 2006.182.07:52:32.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:32.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:32.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:32.35#ibcon#enter wrdev, iclass 22, count 2 2006.182.07:52:32.35#ibcon#first serial, iclass 22, count 2 2006.182.07:52:32.35#ibcon#enter sib2, iclass 22, count 2 2006.182.07:52:32.35#ibcon#flushed, iclass 22, count 2 2006.182.07:52:32.35#ibcon#about to write, iclass 22, count 2 2006.182.07:52:32.35#ibcon#wrote, iclass 22, count 2 2006.182.07:52:32.35#ibcon#about to read 3, iclass 22, count 2 2006.182.07:52:32.37#ibcon#read 3, iclass 22, count 2 2006.182.07:52:32.37#ibcon#about to read 4, iclass 22, count 2 2006.182.07:52:32.37#ibcon#read 4, iclass 22, count 2 2006.182.07:52:32.37#ibcon#about to read 5, iclass 22, count 2 2006.182.07:52:32.37#ibcon#read 5, iclass 22, count 2 2006.182.07:52:32.37#ibcon#about to read 6, iclass 22, count 2 2006.182.07:52:32.37#ibcon#read 6, iclass 22, count 2 2006.182.07:52:32.37#ibcon#end of sib2, iclass 22, count 2 2006.182.07:52:32.37#ibcon#*mode == 0, iclass 22, count 2 2006.182.07:52:32.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.07:52:32.37#ibcon#[27=AT06-04\r\n] 2006.182.07:52:32.37#ibcon#*before write, iclass 22, count 2 2006.182.07:52:32.37#ibcon#enter sib2, iclass 22, count 2 2006.182.07:52:32.37#ibcon#flushed, iclass 22, count 2 2006.182.07:52:32.37#ibcon#about to write, iclass 22, count 2 2006.182.07:52:32.37#ibcon#wrote, iclass 22, count 2 2006.182.07:52:32.37#ibcon#about to read 3, iclass 22, count 2 2006.182.07:52:32.40#ibcon#read 3, iclass 22, count 2 2006.182.07:52:32.40#ibcon#about to read 4, iclass 22, count 2 2006.182.07:52:32.40#ibcon#read 4, iclass 22, count 2 2006.182.07:52:32.40#ibcon#about to read 5, iclass 22, count 2 2006.182.07:52:32.40#ibcon#read 5, iclass 22, count 2 2006.182.07:52:32.40#ibcon#about to read 6, iclass 22, count 2 2006.182.07:52:32.40#ibcon#read 6, iclass 22, count 2 2006.182.07:52:32.40#ibcon#end of sib2, iclass 22, count 2 2006.182.07:52:32.40#ibcon#*after write, iclass 22, count 2 2006.182.07:52:32.40#ibcon#*before return 0, iclass 22, count 2 2006.182.07:52:32.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:32.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.07:52:32.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.07:52:32.40#ibcon#ireg 7 cls_cnt 0 2006.182.07:52:32.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:32.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:32.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:32.52#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:52:32.52#ibcon#first serial, iclass 22, count 0 2006.182.07:52:32.52#ibcon#enter sib2, iclass 22, count 0 2006.182.07:52:32.52#ibcon#flushed, iclass 22, count 0 2006.182.07:52:32.52#ibcon#about to write, iclass 22, count 0 2006.182.07:52:32.52#ibcon#wrote, iclass 22, count 0 2006.182.07:52:32.52#ibcon#about to read 3, iclass 22, count 0 2006.182.07:52:32.54#ibcon#read 3, iclass 22, count 0 2006.182.07:52:32.54#ibcon#about to read 4, iclass 22, count 0 2006.182.07:52:32.54#ibcon#read 4, iclass 22, count 0 2006.182.07:52:32.54#ibcon#about to read 5, iclass 22, count 0 2006.182.07:52:32.54#ibcon#read 5, iclass 22, count 0 2006.182.07:52:32.54#ibcon#about to read 6, iclass 22, count 0 2006.182.07:52:32.54#ibcon#read 6, iclass 22, count 0 2006.182.07:52:32.54#ibcon#end of sib2, iclass 22, count 0 2006.182.07:52:32.54#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:52:32.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:52:32.54#ibcon#[27=USB\r\n] 2006.182.07:52:32.54#ibcon#*before write, iclass 22, count 0 2006.182.07:52:32.54#ibcon#enter sib2, iclass 22, count 0 2006.182.07:52:32.54#ibcon#flushed, iclass 22, count 0 2006.182.07:52:32.54#ibcon#about to write, iclass 22, count 0 2006.182.07:52:32.54#ibcon#wrote, iclass 22, count 0 2006.182.07:52:32.54#ibcon#about to read 3, iclass 22, count 0 2006.182.07:52:32.57#ibcon#read 3, iclass 22, count 0 2006.182.07:52:32.57#ibcon#about to read 4, iclass 22, count 0 2006.182.07:52:32.57#ibcon#read 4, iclass 22, count 0 2006.182.07:52:32.57#ibcon#about to read 5, iclass 22, count 0 2006.182.07:52:32.57#ibcon#read 5, iclass 22, count 0 2006.182.07:52:32.57#ibcon#about to read 6, iclass 22, count 0 2006.182.07:52:32.57#ibcon#read 6, iclass 22, count 0 2006.182.07:52:32.57#ibcon#end of sib2, iclass 22, count 0 2006.182.07:52:32.57#ibcon#*after write, iclass 22, count 0 2006.182.07:52:32.57#ibcon#*before return 0, iclass 22, count 0 2006.182.07:52:32.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:32.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.07:52:32.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:52:32.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:52:32.57$vc4f8/vabw=wide 2006.182.07:52:32.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.07:52:32.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.07:52:32.57#ibcon#ireg 8 cls_cnt 0 2006.182.07:52:32.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:32.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:32.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:32.57#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:52:32.57#ibcon#first serial, iclass 24, count 0 2006.182.07:52:32.57#ibcon#enter sib2, iclass 24, count 0 2006.182.07:52:32.57#ibcon#flushed, iclass 24, count 0 2006.182.07:52:32.57#ibcon#about to write, iclass 24, count 0 2006.182.07:52:32.57#ibcon#wrote, iclass 24, count 0 2006.182.07:52:32.57#ibcon#about to read 3, iclass 24, count 0 2006.182.07:52:32.59#ibcon#read 3, iclass 24, count 0 2006.182.07:52:32.59#ibcon#about to read 4, iclass 24, count 0 2006.182.07:52:32.59#ibcon#read 4, iclass 24, count 0 2006.182.07:52:32.59#ibcon#about to read 5, iclass 24, count 0 2006.182.07:52:32.59#ibcon#read 5, iclass 24, count 0 2006.182.07:52:32.59#ibcon#about to read 6, iclass 24, count 0 2006.182.07:52:32.59#ibcon#read 6, iclass 24, count 0 2006.182.07:52:32.59#ibcon#end of sib2, iclass 24, count 0 2006.182.07:52:32.59#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:52:32.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:52:32.59#ibcon#[25=BW32\r\n] 2006.182.07:52:32.59#ibcon#*before write, iclass 24, count 0 2006.182.07:52:32.59#ibcon#enter sib2, iclass 24, count 0 2006.182.07:52:32.59#ibcon#flushed, iclass 24, count 0 2006.182.07:52:32.59#ibcon#about to write, iclass 24, count 0 2006.182.07:52:32.59#ibcon#wrote, iclass 24, count 0 2006.182.07:52:32.59#ibcon#about to read 3, iclass 24, count 0 2006.182.07:52:32.62#ibcon#read 3, iclass 24, count 0 2006.182.07:52:32.62#ibcon#about to read 4, iclass 24, count 0 2006.182.07:52:32.62#ibcon#read 4, iclass 24, count 0 2006.182.07:52:32.62#ibcon#about to read 5, iclass 24, count 0 2006.182.07:52:32.62#ibcon#read 5, iclass 24, count 0 2006.182.07:52:32.62#ibcon#about to read 6, iclass 24, count 0 2006.182.07:52:32.62#ibcon#read 6, iclass 24, count 0 2006.182.07:52:32.62#ibcon#end of sib2, iclass 24, count 0 2006.182.07:52:32.62#ibcon#*after write, iclass 24, count 0 2006.182.07:52:32.62#ibcon#*before return 0, iclass 24, count 0 2006.182.07:52:32.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:32.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.07:52:32.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:52:32.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:52:32.62$vc4f8/vbbw=wide 2006.182.07:52:32.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.07:52:32.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.07:52:32.62#ibcon#ireg 8 cls_cnt 0 2006.182.07:52:32.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:52:32.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:52:32.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:52:32.69#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:52:32.69#ibcon#first serial, iclass 26, count 0 2006.182.07:52:32.69#ibcon#enter sib2, iclass 26, count 0 2006.182.07:52:32.69#ibcon#flushed, iclass 26, count 0 2006.182.07:52:32.69#ibcon#about to write, iclass 26, count 0 2006.182.07:52:32.69#ibcon#wrote, iclass 26, count 0 2006.182.07:52:32.69#ibcon#about to read 3, iclass 26, count 0 2006.182.07:52:32.71#ibcon#read 3, iclass 26, count 0 2006.182.07:52:32.71#ibcon#about to read 4, iclass 26, count 0 2006.182.07:52:32.71#ibcon#read 4, iclass 26, count 0 2006.182.07:52:32.71#ibcon#about to read 5, iclass 26, count 0 2006.182.07:52:32.71#ibcon#read 5, iclass 26, count 0 2006.182.07:52:32.71#ibcon#about to read 6, iclass 26, count 0 2006.182.07:52:32.71#ibcon#read 6, iclass 26, count 0 2006.182.07:52:32.71#ibcon#end of sib2, iclass 26, count 0 2006.182.07:52:32.71#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:52:32.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:52:32.71#ibcon#[27=BW32\r\n] 2006.182.07:52:32.71#ibcon#*before write, iclass 26, count 0 2006.182.07:52:32.71#ibcon#enter sib2, iclass 26, count 0 2006.182.07:52:32.71#ibcon#flushed, iclass 26, count 0 2006.182.07:52:32.71#ibcon#about to write, iclass 26, count 0 2006.182.07:52:32.71#ibcon#wrote, iclass 26, count 0 2006.182.07:52:32.71#ibcon#about to read 3, iclass 26, count 0 2006.182.07:52:32.74#ibcon#read 3, iclass 26, count 0 2006.182.07:52:32.74#ibcon#about to read 4, iclass 26, count 0 2006.182.07:52:32.74#ibcon#read 4, iclass 26, count 0 2006.182.07:52:32.74#ibcon#about to read 5, iclass 26, count 0 2006.182.07:52:32.74#ibcon#read 5, iclass 26, count 0 2006.182.07:52:32.74#ibcon#about to read 6, iclass 26, count 0 2006.182.07:52:32.74#ibcon#read 6, iclass 26, count 0 2006.182.07:52:32.74#ibcon#end of sib2, iclass 26, count 0 2006.182.07:52:32.74#ibcon#*after write, iclass 26, count 0 2006.182.07:52:32.74#ibcon#*before return 0, iclass 26, count 0 2006.182.07:52:32.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:52:32.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:52:32.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:52:32.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:52:32.74$4f8m12a/ifd4f 2006.182.07:52:32.74$ifd4f/lo= 2006.182.07:52:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:52:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:52:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:52:32.74$ifd4f/patch= 2006.182.07:52:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:52:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:52:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:52:32.74$4f8m12a/"form=m,16.000,1:2 2006.182.07:52:32.74$4f8m12a/"tpicd 2006.182.07:52:32.74$4f8m12a/echo=off 2006.182.07:52:32.74$4f8m12a/xlog=off 2006.182.07:52:32.74:!2006.182.07:54:10 2006.182.07:52:53.14#trakl#Source acquired 2006.182.07:52:54.14#flagr#flagr/antenna,acquired 2006.182.07:54:10.00:preob 2006.182.07:54:10.13/onsource/TRACKING 2006.182.07:54:10.13:!2006.182.07:54:20 2006.182.07:54:20.00:data_valid=on 2006.182.07:54:20.00:midob 2006.182.07:54:21.13/onsource/TRACKING 2006.182.07:54:21.13/wx/27.68,1002.8,82 2006.182.07:54:21.18/cable/+6.4679E-03 2006.182.07:54:22.28/va/01,08,usb,yes,30,32 2006.182.07:54:22.28/va/02,07,usb,yes,31,32 2006.182.07:54:22.28/va/03,06,usb,yes,32,33 2006.182.07:54:22.28/va/04,07,usb,yes,31,34 2006.182.07:54:22.28/va/05,07,usb,yes,33,35 2006.182.07:54:22.28/va/06,06,usb,yes,32,32 2006.182.07:54:22.28/va/07,06,usb,yes,32,32 2006.182.07:54:22.28/va/08,07,usb,yes,31,30 2006.182.07:54:22.51/valo/01,532.99,yes,locked 2006.182.07:54:22.51/valo/02,572.99,yes,locked 2006.182.07:54:22.51/valo/03,672.99,yes,locked 2006.182.07:54:22.51/valo/04,832.99,yes,locked 2006.182.07:54:22.51/valo/05,652.99,yes,locked 2006.182.07:54:22.51/valo/06,772.99,yes,locked 2006.182.07:54:22.51/valo/07,832.99,yes,locked 2006.182.07:54:22.51/valo/08,852.99,yes,locked 2006.182.07:54:23.60/vb/01,04,usb,yes,30,29 2006.182.07:54:23.60/vb/02,04,usb,yes,32,33 2006.182.07:54:23.60/vb/03,04,usb,yes,28,32 2006.182.07:54:23.60/vb/04,04,usb,yes,29,29 2006.182.07:54:23.60/vb/05,04,usb,yes,28,32 2006.182.07:54:23.60/vb/06,04,usb,yes,29,31 2006.182.07:54:23.60/vb/07,04,usb,yes,31,31 2006.182.07:54:23.60/vb/08,04,usb,yes,28,32 2006.182.07:54:23.84/vblo/01,632.99,yes,locked 2006.182.07:54:23.84/vblo/02,640.99,yes,locked 2006.182.07:54:23.84/vblo/03,656.99,yes,locked 2006.182.07:54:23.84/vblo/04,712.99,yes,locked 2006.182.07:54:23.84/vblo/05,744.99,yes,locked 2006.182.07:54:23.84/vblo/06,752.99,yes,locked 2006.182.07:54:23.84/vblo/07,734.99,yes,locked 2006.182.07:54:23.84/vblo/08,744.99,yes,locked 2006.182.07:54:23.99/vabw/8 2006.182.07:54:24.14/vbbw/8 2006.182.07:54:24.23/xfe/off,on,15.0 2006.182.07:54:24.62/ifatt/23,28,28,28 2006.182.07:54:25.08/fmout-gps/S +3.39E-07 2006.182.07:54:25.12:!2006.182.07:55:20 2006.182.07:55:20.02:data_valid=off 2006.182.07:55:20.02:postob 2006.182.07:55:20.22/cable/+6.4664E-03 2006.182.07:55:20.22/wx/27.69,1002.8,81 2006.182.07:55:21.08/fmout-gps/S +3.39E-07 2006.182.07:55:21.08:scan_name=182-0757,k06182,60 2006.182.07:55:21.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.182.07:55:21.13#flagr#flagr/antenna,new-source 2006.182.07:55:22.13:checkk5 2006.182.07:55:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:55:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:55:23.25/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:55:23.62/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:55:23.99/chk_obsdata//k5ts1/T1820754??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:55:24.36/chk_obsdata//k5ts2/T1820754??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:55:24.73/chk_obsdata//k5ts3/T1820754??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:55:25.10/chk_obsdata//k5ts4/T1820754??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:55:25.79/k5log//k5ts1_log_newline 2006.182.07:55:26.48/k5log//k5ts2_log_newline 2006.182.07:55:27.17/k5log//k5ts3_log_newline 2006.182.07:55:27.86/k5log//k5ts4_log_newline 2006.182.07:55:27.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:55:27.88:4f8m12a=2 2006.182.07:55:27.88$4f8m12a/echo=on 2006.182.07:55:27.88$4f8m12a/pcalon 2006.182.07:55:27.88$pcalon/"no phase cal control is implemented here 2006.182.07:55:27.88$4f8m12a/"tpicd=stop 2006.182.07:55:27.88$4f8m12a/vc4f8 2006.182.07:55:27.88$vc4f8/valo=1,532.99 2006.182.07:55:27.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.07:55:27.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.07:55:27.89#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:27.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:27.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:27.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:27.89#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:55:27.89#ibcon#first serial, iclass 25, count 0 2006.182.07:55:27.89#ibcon#enter sib2, iclass 25, count 0 2006.182.07:55:27.89#ibcon#flushed, iclass 25, count 0 2006.182.07:55:27.89#ibcon#about to write, iclass 25, count 0 2006.182.07:55:27.89#ibcon#wrote, iclass 25, count 0 2006.182.07:55:27.89#ibcon#about to read 3, iclass 25, count 0 2006.182.07:55:27.93#ibcon#read 3, iclass 25, count 0 2006.182.07:55:27.93#ibcon#about to read 4, iclass 25, count 0 2006.182.07:55:27.93#ibcon#read 4, iclass 25, count 0 2006.182.07:55:27.93#ibcon#about to read 5, iclass 25, count 0 2006.182.07:55:27.93#ibcon#read 5, iclass 25, count 0 2006.182.07:55:27.93#ibcon#about to read 6, iclass 25, count 0 2006.182.07:55:27.93#ibcon#read 6, iclass 25, count 0 2006.182.07:55:27.93#ibcon#end of sib2, iclass 25, count 0 2006.182.07:55:27.93#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:55:27.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:55:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:55:27.93#ibcon#*before write, iclass 25, count 0 2006.182.07:55:27.93#ibcon#enter sib2, iclass 25, count 0 2006.182.07:55:27.93#ibcon#flushed, iclass 25, count 0 2006.182.07:55:27.93#ibcon#about to write, iclass 25, count 0 2006.182.07:55:27.93#ibcon#wrote, iclass 25, count 0 2006.182.07:55:27.93#ibcon#about to read 3, iclass 25, count 0 2006.182.07:55:27.97#ibcon#read 3, iclass 25, count 0 2006.182.07:55:27.97#ibcon#about to read 4, iclass 25, count 0 2006.182.07:55:27.98#ibcon#read 4, iclass 25, count 0 2006.182.07:55:27.98#ibcon#about to read 5, iclass 25, count 0 2006.182.07:55:27.98#ibcon#read 5, iclass 25, count 0 2006.182.07:55:27.98#ibcon#about to read 6, iclass 25, count 0 2006.182.07:55:27.98#ibcon#read 6, iclass 25, count 0 2006.182.07:55:27.98#ibcon#end of sib2, iclass 25, count 0 2006.182.07:55:27.98#ibcon#*after write, iclass 25, count 0 2006.182.07:55:27.98#ibcon#*before return 0, iclass 25, count 0 2006.182.07:55:27.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:27.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:27.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:55:27.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:55:27.98$vc4f8/va=1,8 2006.182.07:55:27.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.182.07:55:27.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.182.07:55:27.98#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:27.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:27.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:27.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:27.98#ibcon#enter wrdev, iclass 27, count 2 2006.182.07:55:27.98#ibcon#first serial, iclass 27, count 2 2006.182.07:55:27.98#ibcon#enter sib2, iclass 27, count 2 2006.182.07:55:27.98#ibcon#flushed, iclass 27, count 2 2006.182.07:55:27.98#ibcon#about to write, iclass 27, count 2 2006.182.07:55:27.98#ibcon#wrote, iclass 27, count 2 2006.182.07:55:27.98#ibcon#about to read 3, iclass 27, count 2 2006.182.07:55:27.99#ibcon#read 3, iclass 27, count 2 2006.182.07:55:28.00#ibcon#about to read 4, iclass 27, count 2 2006.182.07:55:28.00#ibcon#read 4, iclass 27, count 2 2006.182.07:55:28.00#ibcon#about to read 5, iclass 27, count 2 2006.182.07:55:28.00#ibcon#read 5, iclass 27, count 2 2006.182.07:55:28.00#ibcon#about to read 6, iclass 27, count 2 2006.182.07:55:28.00#ibcon#read 6, iclass 27, count 2 2006.182.07:55:28.00#ibcon#end of sib2, iclass 27, count 2 2006.182.07:55:28.00#ibcon#*mode == 0, iclass 27, count 2 2006.182.07:55:28.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.182.07:55:28.00#ibcon#[25=AT01-08\r\n] 2006.182.07:55:28.00#ibcon#*before write, iclass 27, count 2 2006.182.07:55:28.00#ibcon#enter sib2, iclass 27, count 2 2006.182.07:55:28.00#ibcon#flushed, iclass 27, count 2 2006.182.07:55:28.00#ibcon#about to write, iclass 27, count 2 2006.182.07:55:28.00#ibcon#wrote, iclass 27, count 2 2006.182.07:55:28.00#ibcon#about to read 3, iclass 27, count 2 2006.182.07:55:28.03#ibcon#read 3, iclass 27, count 2 2006.182.07:55:28.03#ibcon#about to read 4, iclass 27, count 2 2006.182.07:55:28.03#ibcon#read 4, iclass 27, count 2 2006.182.07:55:28.03#ibcon#about to read 5, iclass 27, count 2 2006.182.07:55:28.03#ibcon#read 5, iclass 27, count 2 2006.182.07:55:28.03#ibcon#about to read 6, iclass 27, count 2 2006.182.07:55:28.03#ibcon#read 6, iclass 27, count 2 2006.182.07:55:28.03#ibcon#end of sib2, iclass 27, count 2 2006.182.07:55:28.03#ibcon#*after write, iclass 27, count 2 2006.182.07:55:28.03#ibcon#*before return 0, iclass 27, count 2 2006.182.07:55:28.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:28.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:28.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.182.07:55:28.03#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:28.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:28.06#abcon#<5=/06 0.8 1.7 27.69 811002.8\r\n> 2006.182.07:55:28.07#abcon#{5=INTERFACE CLEAR} 2006.182.07:55:28.13#abcon#[5=S1D000X0/0*\r\n] 2006.182.07:55:28.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:28.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:28.15#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:55:28.15#ibcon#first serial, iclass 27, count 0 2006.182.07:55:28.15#ibcon#enter sib2, iclass 27, count 0 2006.182.07:55:28.15#ibcon#flushed, iclass 27, count 0 2006.182.07:55:28.15#ibcon#about to write, iclass 27, count 0 2006.182.07:55:28.15#ibcon#wrote, iclass 27, count 0 2006.182.07:55:28.15#ibcon#about to read 3, iclass 27, count 0 2006.182.07:55:28.16#ibcon#read 3, iclass 27, count 0 2006.182.07:55:28.16#ibcon#about to read 4, iclass 27, count 0 2006.182.07:55:28.16#ibcon#read 4, iclass 27, count 0 2006.182.07:55:28.17#ibcon#about to read 5, iclass 27, count 0 2006.182.07:55:28.17#ibcon#read 5, iclass 27, count 0 2006.182.07:55:28.17#ibcon#about to read 6, iclass 27, count 0 2006.182.07:55:28.17#ibcon#read 6, iclass 27, count 0 2006.182.07:55:28.17#ibcon#end of sib2, iclass 27, count 0 2006.182.07:55:28.17#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:55:28.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:55:28.17#ibcon#[25=USB\r\n] 2006.182.07:55:28.17#ibcon#*before write, iclass 27, count 0 2006.182.07:55:28.17#ibcon#enter sib2, iclass 27, count 0 2006.182.07:55:28.17#ibcon#flushed, iclass 27, count 0 2006.182.07:55:28.17#ibcon#about to write, iclass 27, count 0 2006.182.07:55:28.17#ibcon#wrote, iclass 27, count 0 2006.182.07:55:28.17#ibcon#about to read 3, iclass 27, count 0 2006.182.07:55:28.20#ibcon#read 3, iclass 27, count 0 2006.182.07:55:28.20#ibcon#about to read 4, iclass 27, count 0 2006.182.07:55:28.20#ibcon#read 4, iclass 27, count 0 2006.182.07:55:28.20#ibcon#about to read 5, iclass 27, count 0 2006.182.07:55:28.20#ibcon#read 5, iclass 27, count 0 2006.182.07:55:28.20#ibcon#about to read 6, iclass 27, count 0 2006.182.07:55:28.20#ibcon#read 6, iclass 27, count 0 2006.182.07:55:28.20#ibcon#end of sib2, iclass 27, count 0 2006.182.07:55:28.20#ibcon#*after write, iclass 27, count 0 2006.182.07:55:28.20#ibcon#*before return 0, iclass 27, count 0 2006.182.07:55:28.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:28.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:28.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:55:28.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:55:28.20$vc4f8/valo=2,572.99 2006.182.07:55:28.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.182.07:55:28.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.182.07:55:28.20#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:28.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:28.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:28.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:28.20#ibcon#enter wrdev, iclass 33, count 0 2006.182.07:55:28.20#ibcon#first serial, iclass 33, count 0 2006.182.07:55:28.20#ibcon#enter sib2, iclass 33, count 0 2006.182.07:55:28.20#ibcon#flushed, iclass 33, count 0 2006.182.07:55:28.20#ibcon#about to write, iclass 33, count 0 2006.182.07:55:28.20#ibcon#wrote, iclass 33, count 0 2006.182.07:55:28.20#ibcon#about to read 3, iclass 33, count 0 2006.182.07:55:28.22#ibcon#read 3, iclass 33, count 0 2006.182.07:55:28.22#ibcon#about to read 4, iclass 33, count 0 2006.182.07:55:28.22#ibcon#read 4, iclass 33, count 0 2006.182.07:55:28.22#ibcon#about to read 5, iclass 33, count 0 2006.182.07:55:28.22#ibcon#read 5, iclass 33, count 0 2006.182.07:55:28.22#ibcon#about to read 6, iclass 33, count 0 2006.182.07:55:28.22#ibcon#read 6, iclass 33, count 0 2006.182.07:55:28.22#ibcon#end of sib2, iclass 33, count 0 2006.182.07:55:28.22#ibcon#*mode == 0, iclass 33, count 0 2006.182.07:55:28.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.07:55:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:55:28.22#ibcon#*before write, iclass 33, count 0 2006.182.07:55:28.22#ibcon#enter sib2, iclass 33, count 0 2006.182.07:55:28.22#ibcon#flushed, iclass 33, count 0 2006.182.07:55:28.22#ibcon#about to write, iclass 33, count 0 2006.182.07:55:28.22#ibcon#wrote, iclass 33, count 0 2006.182.07:55:28.22#ibcon#about to read 3, iclass 33, count 0 2006.182.07:55:28.25#ibcon#read 3, iclass 33, count 0 2006.182.07:55:28.25#ibcon#about to read 4, iclass 33, count 0 2006.182.07:55:28.26#ibcon#read 4, iclass 33, count 0 2006.182.07:55:28.26#ibcon#about to read 5, iclass 33, count 0 2006.182.07:55:28.26#ibcon#read 5, iclass 33, count 0 2006.182.07:55:28.26#ibcon#about to read 6, iclass 33, count 0 2006.182.07:55:28.26#ibcon#read 6, iclass 33, count 0 2006.182.07:55:28.26#ibcon#end of sib2, iclass 33, count 0 2006.182.07:55:28.26#ibcon#*after write, iclass 33, count 0 2006.182.07:55:28.26#ibcon#*before return 0, iclass 33, count 0 2006.182.07:55:28.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:28.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:28.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.07:55:28.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.07:55:28.26$vc4f8/va=2,7 2006.182.07:55:28.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.182.07:55:28.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.182.07:55:28.26#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:28.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:28.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:28.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:28.32#ibcon#enter wrdev, iclass 35, count 2 2006.182.07:55:28.32#ibcon#first serial, iclass 35, count 2 2006.182.07:55:28.32#ibcon#enter sib2, iclass 35, count 2 2006.182.07:55:28.32#ibcon#flushed, iclass 35, count 2 2006.182.07:55:28.32#ibcon#about to write, iclass 35, count 2 2006.182.07:55:28.32#ibcon#wrote, iclass 35, count 2 2006.182.07:55:28.32#ibcon#about to read 3, iclass 35, count 2 2006.182.07:55:28.33#ibcon#read 3, iclass 35, count 2 2006.182.07:55:28.34#ibcon#about to read 4, iclass 35, count 2 2006.182.07:55:28.34#ibcon#read 4, iclass 35, count 2 2006.182.07:55:28.34#ibcon#about to read 5, iclass 35, count 2 2006.182.07:55:28.34#ibcon#read 5, iclass 35, count 2 2006.182.07:55:28.34#ibcon#about to read 6, iclass 35, count 2 2006.182.07:55:28.34#ibcon#read 6, iclass 35, count 2 2006.182.07:55:28.34#ibcon#end of sib2, iclass 35, count 2 2006.182.07:55:28.34#ibcon#*mode == 0, iclass 35, count 2 2006.182.07:55:28.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.182.07:55:28.34#ibcon#[25=AT02-07\r\n] 2006.182.07:55:28.34#ibcon#*before write, iclass 35, count 2 2006.182.07:55:28.34#ibcon#enter sib2, iclass 35, count 2 2006.182.07:55:28.34#ibcon#flushed, iclass 35, count 2 2006.182.07:55:28.34#ibcon#about to write, iclass 35, count 2 2006.182.07:55:28.34#ibcon#wrote, iclass 35, count 2 2006.182.07:55:28.34#ibcon#about to read 3, iclass 35, count 2 2006.182.07:55:28.36#ibcon#read 3, iclass 35, count 2 2006.182.07:55:28.36#ibcon#about to read 4, iclass 35, count 2 2006.182.07:55:28.37#ibcon#read 4, iclass 35, count 2 2006.182.07:55:28.37#ibcon#about to read 5, iclass 35, count 2 2006.182.07:55:28.37#ibcon#read 5, iclass 35, count 2 2006.182.07:55:28.37#ibcon#about to read 6, iclass 35, count 2 2006.182.07:55:28.37#ibcon#read 6, iclass 35, count 2 2006.182.07:55:28.37#ibcon#end of sib2, iclass 35, count 2 2006.182.07:55:28.37#ibcon#*after write, iclass 35, count 2 2006.182.07:55:28.37#ibcon#*before return 0, iclass 35, count 2 2006.182.07:55:28.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:28.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:28.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.182.07:55:28.37#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:28.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:28.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:28.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:28.49#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:55:28.49#ibcon#first serial, iclass 35, count 0 2006.182.07:55:28.49#ibcon#enter sib2, iclass 35, count 0 2006.182.07:55:28.49#ibcon#flushed, iclass 35, count 0 2006.182.07:55:28.49#ibcon#about to write, iclass 35, count 0 2006.182.07:55:28.49#ibcon#wrote, iclass 35, count 0 2006.182.07:55:28.49#ibcon#about to read 3, iclass 35, count 0 2006.182.07:55:28.51#ibcon#read 3, iclass 35, count 0 2006.182.07:55:28.51#ibcon#about to read 4, iclass 35, count 0 2006.182.07:55:28.51#ibcon#read 4, iclass 35, count 0 2006.182.07:55:28.51#ibcon#about to read 5, iclass 35, count 0 2006.182.07:55:28.51#ibcon#read 5, iclass 35, count 0 2006.182.07:55:28.51#ibcon#about to read 6, iclass 35, count 0 2006.182.07:55:28.51#ibcon#read 6, iclass 35, count 0 2006.182.07:55:28.51#ibcon#end of sib2, iclass 35, count 0 2006.182.07:55:28.51#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:55:28.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:55:28.51#ibcon#[25=USB\r\n] 2006.182.07:55:28.51#ibcon#*before write, iclass 35, count 0 2006.182.07:55:28.51#ibcon#enter sib2, iclass 35, count 0 2006.182.07:55:28.51#ibcon#flushed, iclass 35, count 0 2006.182.07:55:28.51#ibcon#about to write, iclass 35, count 0 2006.182.07:55:28.51#ibcon#wrote, iclass 35, count 0 2006.182.07:55:28.51#ibcon#about to read 3, iclass 35, count 0 2006.182.07:55:28.53#ibcon#read 3, iclass 35, count 0 2006.182.07:55:28.53#ibcon#about to read 4, iclass 35, count 0 2006.182.07:55:28.54#ibcon#read 4, iclass 35, count 0 2006.182.07:55:28.54#ibcon#about to read 5, iclass 35, count 0 2006.182.07:55:28.54#ibcon#read 5, iclass 35, count 0 2006.182.07:55:28.54#ibcon#about to read 6, iclass 35, count 0 2006.182.07:55:28.54#ibcon#read 6, iclass 35, count 0 2006.182.07:55:28.54#ibcon#end of sib2, iclass 35, count 0 2006.182.07:55:28.54#ibcon#*after write, iclass 35, count 0 2006.182.07:55:28.54#ibcon#*before return 0, iclass 35, count 0 2006.182.07:55:28.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:28.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:28.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:55:28.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:55:28.54$vc4f8/valo=3,672.99 2006.182.07:55:28.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.182.07:55:28.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.182.07:55:28.54#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:28.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:28.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:28.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:28.54#ibcon#enter wrdev, iclass 37, count 0 2006.182.07:55:28.54#ibcon#first serial, iclass 37, count 0 2006.182.07:55:28.54#ibcon#enter sib2, iclass 37, count 0 2006.182.07:55:28.54#ibcon#flushed, iclass 37, count 0 2006.182.07:55:28.54#ibcon#about to write, iclass 37, count 0 2006.182.07:55:28.54#ibcon#wrote, iclass 37, count 0 2006.182.07:55:28.54#ibcon#about to read 3, iclass 37, count 0 2006.182.07:55:28.56#ibcon#read 3, iclass 37, count 0 2006.182.07:55:28.56#ibcon#about to read 4, iclass 37, count 0 2006.182.07:55:28.56#ibcon#read 4, iclass 37, count 0 2006.182.07:55:28.56#ibcon#about to read 5, iclass 37, count 0 2006.182.07:55:28.56#ibcon#read 5, iclass 37, count 0 2006.182.07:55:28.56#ibcon#about to read 6, iclass 37, count 0 2006.182.07:55:28.56#ibcon#read 6, iclass 37, count 0 2006.182.07:55:28.56#ibcon#end of sib2, iclass 37, count 0 2006.182.07:55:28.56#ibcon#*mode == 0, iclass 37, count 0 2006.182.07:55:28.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.07:55:28.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:55:28.56#ibcon#*before write, iclass 37, count 0 2006.182.07:55:28.56#ibcon#enter sib2, iclass 37, count 0 2006.182.07:55:28.56#ibcon#flushed, iclass 37, count 0 2006.182.07:55:28.56#ibcon#about to write, iclass 37, count 0 2006.182.07:55:28.56#ibcon#wrote, iclass 37, count 0 2006.182.07:55:28.56#ibcon#about to read 3, iclass 37, count 0 2006.182.07:55:28.59#ibcon#read 3, iclass 37, count 0 2006.182.07:55:28.59#ibcon#about to read 4, iclass 37, count 0 2006.182.07:55:28.59#ibcon#read 4, iclass 37, count 0 2006.182.07:55:28.60#ibcon#about to read 5, iclass 37, count 0 2006.182.07:55:28.60#ibcon#read 5, iclass 37, count 0 2006.182.07:55:28.60#ibcon#about to read 6, iclass 37, count 0 2006.182.07:55:28.60#ibcon#read 6, iclass 37, count 0 2006.182.07:55:28.60#ibcon#end of sib2, iclass 37, count 0 2006.182.07:55:28.60#ibcon#*after write, iclass 37, count 0 2006.182.07:55:28.60#ibcon#*before return 0, iclass 37, count 0 2006.182.07:55:28.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:28.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:28.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.07:55:28.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.07:55:28.60$vc4f8/va=3,6 2006.182.07:55:28.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.07:55:28.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.07:55:28.60#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:28.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:28.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:28.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:28.65#ibcon#enter wrdev, iclass 39, count 2 2006.182.07:55:28.65#ibcon#first serial, iclass 39, count 2 2006.182.07:55:28.66#ibcon#enter sib2, iclass 39, count 2 2006.182.07:55:28.66#ibcon#flushed, iclass 39, count 2 2006.182.07:55:28.66#ibcon#about to write, iclass 39, count 2 2006.182.07:55:28.66#ibcon#wrote, iclass 39, count 2 2006.182.07:55:28.66#ibcon#about to read 3, iclass 39, count 2 2006.182.07:55:28.67#ibcon#read 3, iclass 39, count 2 2006.182.07:55:28.68#ibcon#about to read 4, iclass 39, count 2 2006.182.07:55:28.68#ibcon#read 4, iclass 39, count 2 2006.182.07:55:28.68#ibcon#about to read 5, iclass 39, count 2 2006.182.07:55:28.68#ibcon#read 5, iclass 39, count 2 2006.182.07:55:28.68#ibcon#about to read 6, iclass 39, count 2 2006.182.07:55:28.68#ibcon#read 6, iclass 39, count 2 2006.182.07:55:28.68#ibcon#end of sib2, iclass 39, count 2 2006.182.07:55:28.68#ibcon#*mode == 0, iclass 39, count 2 2006.182.07:55:28.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.07:55:28.68#ibcon#[25=AT03-06\r\n] 2006.182.07:55:28.68#ibcon#*before write, iclass 39, count 2 2006.182.07:55:28.68#ibcon#enter sib2, iclass 39, count 2 2006.182.07:55:28.68#ibcon#flushed, iclass 39, count 2 2006.182.07:55:28.68#ibcon#about to write, iclass 39, count 2 2006.182.07:55:28.68#ibcon#wrote, iclass 39, count 2 2006.182.07:55:28.68#ibcon#about to read 3, iclass 39, count 2 2006.182.07:55:28.70#ibcon#read 3, iclass 39, count 2 2006.182.07:55:28.70#ibcon#about to read 4, iclass 39, count 2 2006.182.07:55:28.71#ibcon#read 4, iclass 39, count 2 2006.182.07:55:28.71#ibcon#about to read 5, iclass 39, count 2 2006.182.07:55:28.71#ibcon#read 5, iclass 39, count 2 2006.182.07:55:28.71#ibcon#about to read 6, iclass 39, count 2 2006.182.07:55:28.71#ibcon#read 6, iclass 39, count 2 2006.182.07:55:28.71#ibcon#end of sib2, iclass 39, count 2 2006.182.07:55:28.71#ibcon#*after write, iclass 39, count 2 2006.182.07:55:28.71#ibcon#*before return 0, iclass 39, count 2 2006.182.07:55:28.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:28.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:28.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.07:55:28.71#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:28.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:28.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:28.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:28.82#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:55:28.82#ibcon#first serial, iclass 39, count 0 2006.182.07:55:28.83#ibcon#enter sib2, iclass 39, count 0 2006.182.07:55:28.83#ibcon#flushed, iclass 39, count 0 2006.182.07:55:28.83#ibcon#about to write, iclass 39, count 0 2006.182.07:55:28.83#ibcon#wrote, iclass 39, count 0 2006.182.07:55:28.83#ibcon#about to read 3, iclass 39, count 0 2006.182.07:55:28.84#ibcon#read 3, iclass 39, count 0 2006.182.07:55:28.84#ibcon#about to read 4, iclass 39, count 0 2006.182.07:55:28.85#ibcon#read 4, iclass 39, count 0 2006.182.07:55:28.85#ibcon#about to read 5, iclass 39, count 0 2006.182.07:55:28.85#ibcon#read 5, iclass 39, count 0 2006.182.07:55:28.85#ibcon#about to read 6, iclass 39, count 0 2006.182.07:55:28.85#ibcon#read 6, iclass 39, count 0 2006.182.07:55:28.85#ibcon#end of sib2, iclass 39, count 0 2006.182.07:55:28.85#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:55:28.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:55:28.85#ibcon#[25=USB\r\n] 2006.182.07:55:28.85#ibcon#*before write, iclass 39, count 0 2006.182.07:55:28.85#ibcon#enter sib2, iclass 39, count 0 2006.182.07:55:28.85#ibcon#flushed, iclass 39, count 0 2006.182.07:55:28.85#ibcon#about to write, iclass 39, count 0 2006.182.07:55:28.85#ibcon#wrote, iclass 39, count 0 2006.182.07:55:28.85#ibcon#about to read 3, iclass 39, count 0 2006.182.07:55:28.87#ibcon#read 3, iclass 39, count 0 2006.182.07:55:28.87#ibcon#about to read 4, iclass 39, count 0 2006.182.07:55:28.88#ibcon#read 4, iclass 39, count 0 2006.182.07:55:28.88#ibcon#about to read 5, iclass 39, count 0 2006.182.07:55:28.88#ibcon#read 5, iclass 39, count 0 2006.182.07:55:28.88#ibcon#about to read 6, iclass 39, count 0 2006.182.07:55:28.88#ibcon#read 6, iclass 39, count 0 2006.182.07:55:28.88#ibcon#end of sib2, iclass 39, count 0 2006.182.07:55:28.88#ibcon#*after write, iclass 39, count 0 2006.182.07:55:28.88#ibcon#*before return 0, iclass 39, count 0 2006.182.07:55:28.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:28.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:28.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:55:28.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:55:28.88$vc4f8/valo=4,832.99 2006.182.07:55:28.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.07:55:28.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.07:55:28.88#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:28.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:28.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:28.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:28.88#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:55:28.88#ibcon#first serial, iclass 3, count 0 2006.182.07:55:28.88#ibcon#enter sib2, iclass 3, count 0 2006.182.07:55:28.88#ibcon#flushed, iclass 3, count 0 2006.182.07:55:28.88#ibcon#about to write, iclass 3, count 0 2006.182.07:55:28.88#ibcon#wrote, iclass 3, count 0 2006.182.07:55:28.88#ibcon#about to read 3, iclass 3, count 0 2006.182.07:55:28.89#ibcon#read 3, iclass 3, count 0 2006.182.07:55:28.89#ibcon#about to read 4, iclass 3, count 0 2006.182.07:55:28.90#ibcon#read 4, iclass 3, count 0 2006.182.07:55:28.90#ibcon#about to read 5, iclass 3, count 0 2006.182.07:55:28.90#ibcon#read 5, iclass 3, count 0 2006.182.07:55:28.90#ibcon#about to read 6, iclass 3, count 0 2006.182.07:55:28.90#ibcon#read 6, iclass 3, count 0 2006.182.07:55:28.90#ibcon#end of sib2, iclass 3, count 0 2006.182.07:55:28.90#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:55:28.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:55:28.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:55:28.90#ibcon#*before write, iclass 3, count 0 2006.182.07:55:28.90#ibcon#enter sib2, iclass 3, count 0 2006.182.07:55:28.90#ibcon#flushed, iclass 3, count 0 2006.182.07:55:28.90#ibcon#about to write, iclass 3, count 0 2006.182.07:55:28.90#ibcon#wrote, iclass 3, count 0 2006.182.07:55:28.90#ibcon#about to read 3, iclass 3, count 0 2006.182.07:55:28.93#ibcon#read 3, iclass 3, count 0 2006.182.07:55:28.93#ibcon#about to read 4, iclass 3, count 0 2006.182.07:55:28.93#ibcon#read 4, iclass 3, count 0 2006.182.07:55:28.94#ibcon#about to read 5, iclass 3, count 0 2006.182.07:55:28.94#ibcon#read 5, iclass 3, count 0 2006.182.07:55:28.94#ibcon#about to read 6, iclass 3, count 0 2006.182.07:55:28.94#ibcon#read 6, iclass 3, count 0 2006.182.07:55:28.94#ibcon#end of sib2, iclass 3, count 0 2006.182.07:55:28.94#ibcon#*after write, iclass 3, count 0 2006.182.07:55:28.94#ibcon#*before return 0, iclass 3, count 0 2006.182.07:55:28.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:28.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:28.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:55:28.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:55:28.94$vc4f8/va=4,7 2006.182.07:55:28.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.07:55:28.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.07:55:28.94#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:28.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:28.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:28.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:28.99#ibcon#enter wrdev, iclass 5, count 2 2006.182.07:55:28.99#ibcon#first serial, iclass 5, count 2 2006.182.07:55:29.00#ibcon#enter sib2, iclass 5, count 2 2006.182.07:55:29.00#ibcon#flushed, iclass 5, count 2 2006.182.07:55:29.00#ibcon#about to write, iclass 5, count 2 2006.182.07:55:29.00#ibcon#wrote, iclass 5, count 2 2006.182.07:55:29.00#ibcon#about to read 3, iclass 5, count 2 2006.182.07:55:29.01#ibcon#read 3, iclass 5, count 2 2006.182.07:55:29.01#ibcon#about to read 4, iclass 5, count 2 2006.182.07:55:29.01#ibcon#read 4, iclass 5, count 2 2006.182.07:55:29.02#ibcon#about to read 5, iclass 5, count 2 2006.182.07:55:29.02#ibcon#read 5, iclass 5, count 2 2006.182.07:55:29.02#ibcon#about to read 6, iclass 5, count 2 2006.182.07:55:29.02#ibcon#read 6, iclass 5, count 2 2006.182.07:55:29.02#ibcon#end of sib2, iclass 5, count 2 2006.182.07:55:29.02#ibcon#*mode == 0, iclass 5, count 2 2006.182.07:55:29.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.07:55:29.02#ibcon#[25=AT04-07\r\n] 2006.182.07:55:29.02#ibcon#*before write, iclass 5, count 2 2006.182.07:55:29.02#ibcon#enter sib2, iclass 5, count 2 2006.182.07:55:29.02#ibcon#flushed, iclass 5, count 2 2006.182.07:55:29.02#ibcon#about to write, iclass 5, count 2 2006.182.07:55:29.02#ibcon#wrote, iclass 5, count 2 2006.182.07:55:29.02#ibcon#about to read 3, iclass 5, count 2 2006.182.07:55:29.04#ibcon#read 3, iclass 5, count 2 2006.182.07:55:29.05#ibcon#about to read 4, iclass 5, count 2 2006.182.07:55:29.05#ibcon#read 4, iclass 5, count 2 2006.182.07:55:29.05#ibcon#about to read 5, iclass 5, count 2 2006.182.07:55:29.05#ibcon#read 5, iclass 5, count 2 2006.182.07:55:29.05#ibcon#about to read 6, iclass 5, count 2 2006.182.07:55:29.05#ibcon#read 6, iclass 5, count 2 2006.182.07:55:29.05#ibcon#end of sib2, iclass 5, count 2 2006.182.07:55:29.05#ibcon#*after write, iclass 5, count 2 2006.182.07:55:29.05#ibcon#*before return 0, iclass 5, count 2 2006.182.07:55:29.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:29.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:29.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.07:55:29.05#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:29.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:29.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:29.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:29.16#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:55:29.16#ibcon#first serial, iclass 5, count 0 2006.182.07:55:29.16#ibcon#enter sib2, iclass 5, count 0 2006.182.07:55:29.17#ibcon#flushed, iclass 5, count 0 2006.182.07:55:29.17#ibcon#about to write, iclass 5, count 0 2006.182.07:55:29.17#ibcon#wrote, iclass 5, count 0 2006.182.07:55:29.17#ibcon#about to read 3, iclass 5, count 0 2006.182.07:55:29.18#ibcon#read 3, iclass 5, count 0 2006.182.07:55:29.18#ibcon#about to read 4, iclass 5, count 0 2006.182.07:55:29.18#ibcon#read 4, iclass 5, count 0 2006.182.07:55:29.19#ibcon#about to read 5, iclass 5, count 0 2006.182.07:55:29.19#ibcon#read 5, iclass 5, count 0 2006.182.07:55:29.19#ibcon#about to read 6, iclass 5, count 0 2006.182.07:55:29.19#ibcon#read 6, iclass 5, count 0 2006.182.07:55:29.19#ibcon#end of sib2, iclass 5, count 0 2006.182.07:55:29.19#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:55:29.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:55:29.19#ibcon#[25=USB\r\n] 2006.182.07:55:29.19#ibcon#*before write, iclass 5, count 0 2006.182.07:55:29.19#ibcon#enter sib2, iclass 5, count 0 2006.182.07:55:29.19#ibcon#flushed, iclass 5, count 0 2006.182.07:55:29.19#ibcon#about to write, iclass 5, count 0 2006.182.07:55:29.19#ibcon#wrote, iclass 5, count 0 2006.182.07:55:29.19#ibcon#about to read 3, iclass 5, count 0 2006.182.07:55:29.21#ibcon#read 3, iclass 5, count 0 2006.182.07:55:29.22#ibcon#about to read 4, iclass 5, count 0 2006.182.07:55:29.22#ibcon#read 4, iclass 5, count 0 2006.182.07:55:29.22#ibcon#about to read 5, iclass 5, count 0 2006.182.07:55:29.22#ibcon#read 5, iclass 5, count 0 2006.182.07:55:29.22#ibcon#about to read 6, iclass 5, count 0 2006.182.07:55:29.22#ibcon#read 6, iclass 5, count 0 2006.182.07:55:29.22#ibcon#end of sib2, iclass 5, count 0 2006.182.07:55:29.22#ibcon#*after write, iclass 5, count 0 2006.182.07:55:29.22#ibcon#*before return 0, iclass 5, count 0 2006.182.07:55:29.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:29.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:29.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:55:29.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:55:29.22$vc4f8/valo=5,652.99 2006.182.07:55:29.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.07:55:29.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.07:55:29.22#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:29.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:29.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:29.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:29.22#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:55:29.22#ibcon#first serial, iclass 7, count 0 2006.182.07:55:29.22#ibcon#enter sib2, iclass 7, count 0 2006.182.07:55:29.22#ibcon#flushed, iclass 7, count 0 2006.182.07:55:29.22#ibcon#about to write, iclass 7, count 0 2006.182.07:55:29.22#ibcon#wrote, iclass 7, count 0 2006.182.07:55:29.22#ibcon#about to read 3, iclass 7, count 0 2006.182.07:55:29.23#ibcon#read 3, iclass 7, count 0 2006.182.07:55:29.23#ibcon#about to read 4, iclass 7, count 0 2006.182.07:55:29.24#ibcon#read 4, iclass 7, count 0 2006.182.07:55:29.24#ibcon#about to read 5, iclass 7, count 0 2006.182.07:55:29.24#ibcon#read 5, iclass 7, count 0 2006.182.07:55:29.24#ibcon#about to read 6, iclass 7, count 0 2006.182.07:55:29.24#ibcon#read 6, iclass 7, count 0 2006.182.07:55:29.24#ibcon#end of sib2, iclass 7, count 0 2006.182.07:55:29.24#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:55:29.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:55:29.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:55:29.24#ibcon#*before write, iclass 7, count 0 2006.182.07:55:29.24#ibcon#enter sib2, iclass 7, count 0 2006.182.07:55:29.24#ibcon#flushed, iclass 7, count 0 2006.182.07:55:29.24#ibcon#about to write, iclass 7, count 0 2006.182.07:55:29.24#ibcon#wrote, iclass 7, count 0 2006.182.07:55:29.24#ibcon#about to read 3, iclass 7, count 0 2006.182.07:55:29.27#ibcon#read 3, iclass 7, count 0 2006.182.07:55:29.27#ibcon#about to read 4, iclass 7, count 0 2006.182.07:55:29.27#ibcon#read 4, iclass 7, count 0 2006.182.07:55:29.28#ibcon#about to read 5, iclass 7, count 0 2006.182.07:55:29.28#ibcon#read 5, iclass 7, count 0 2006.182.07:55:29.28#ibcon#about to read 6, iclass 7, count 0 2006.182.07:55:29.28#ibcon#read 6, iclass 7, count 0 2006.182.07:55:29.28#ibcon#end of sib2, iclass 7, count 0 2006.182.07:55:29.28#ibcon#*after write, iclass 7, count 0 2006.182.07:55:29.28#ibcon#*before return 0, iclass 7, count 0 2006.182.07:55:29.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:29.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:29.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:55:29.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:55:29.28$vc4f8/va=5,7 2006.182.07:55:29.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.07:55:29.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.07:55:29.28#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:29.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:29.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:29.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:29.33#ibcon#enter wrdev, iclass 11, count 2 2006.182.07:55:29.33#ibcon#first serial, iclass 11, count 2 2006.182.07:55:29.34#ibcon#enter sib2, iclass 11, count 2 2006.182.07:55:29.34#ibcon#flushed, iclass 11, count 2 2006.182.07:55:29.34#ibcon#about to write, iclass 11, count 2 2006.182.07:55:29.34#ibcon#wrote, iclass 11, count 2 2006.182.07:55:29.34#ibcon#about to read 3, iclass 11, count 2 2006.182.07:55:29.35#ibcon#read 3, iclass 11, count 2 2006.182.07:55:29.35#ibcon#about to read 4, iclass 11, count 2 2006.182.07:55:29.35#ibcon#read 4, iclass 11, count 2 2006.182.07:55:29.36#ibcon#about to read 5, iclass 11, count 2 2006.182.07:55:29.36#ibcon#read 5, iclass 11, count 2 2006.182.07:55:29.36#ibcon#about to read 6, iclass 11, count 2 2006.182.07:55:29.36#ibcon#read 6, iclass 11, count 2 2006.182.07:55:29.36#ibcon#end of sib2, iclass 11, count 2 2006.182.07:55:29.36#ibcon#*mode == 0, iclass 11, count 2 2006.182.07:55:29.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.07:55:29.36#ibcon#[25=AT05-07\r\n] 2006.182.07:55:29.36#ibcon#*before write, iclass 11, count 2 2006.182.07:55:29.36#ibcon#enter sib2, iclass 11, count 2 2006.182.07:55:29.36#ibcon#flushed, iclass 11, count 2 2006.182.07:55:29.36#ibcon#about to write, iclass 11, count 2 2006.182.07:55:29.36#ibcon#wrote, iclass 11, count 2 2006.182.07:55:29.36#ibcon#about to read 3, iclass 11, count 2 2006.182.07:55:29.39#ibcon#read 3, iclass 11, count 2 2006.182.07:55:29.39#ibcon#about to read 4, iclass 11, count 2 2006.182.07:55:29.39#ibcon#read 4, iclass 11, count 2 2006.182.07:55:29.39#ibcon#about to read 5, iclass 11, count 2 2006.182.07:55:29.39#ibcon#read 5, iclass 11, count 2 2006.182.07:55:29.39#ibcon#about to read 6, iclass 11, count 2 2006.182.07:55:29.39#ibcon#read 6, iclass 11, count 2 2006.182.07:55:29.39#ibcon#end of sib2, iclass 11, count 2 2006.182.07:55:29.39#ibcon#*after write, iclass 11, count 2 2006.182.07:55:29.39#ibcon#*before return 0, iclass 11, count 2 2006.182.07:55:29.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:29.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:29.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.07:55:29.39#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:29.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:29.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:29.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:29.50#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:55:29.50#ibcon#first serial, iclass 11, count 0 2006.182.07:55:29.51#ibcon#enter sib2, iclass 11, count 0 2006.182.07:55:29.51#ibcon#flushed, iclass 11, count 0 2006.182.07:55:29.51#ibcon#about to write, iclass 11, count 0 2006.182.07:55:29.51#ibcon#wrote, iclass 11, count 0 2006.182.07:55:29.51#ibcon#about to read 3, iclass 11, count 0 2006.182.07:55:29.52#ibcon#read 3, iclass 11, count 0 2006.182.07:55:29.52#ibcon#about to read 4, iclass 11, count 0 2006.182.07:55:29.53#ibcon#read 4, iclass 11, count 0 2006.182.07:55:29.53#ibcon#about to read 5, iclass 11, count 0 2006.182.07:55:29.53#ibcon#read 5, iclass 11, count 0 2006.182.07:55:29.53#ibcon#about to read 6, iclass 11, count 0 2006.182.07:55:29.53#ibcon#read 6, iclass 11, count 0 2006.182.07:55:29.53#ibcon#end of sib2, iclass 11, count 0 2006.182.07:55:29.53#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:55:29.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:55:29.53#ibcon#[25=USB\r\n] 2006.182.07:55:29.53#ibcon#*before write, iclass 11, count 0 2006.182.07:55:29.53#ibcon#enter sib2, iclass 11, count 0 2006.182.07:55:29.53#ibcon#flushed, iclass 11, count 0 2006.182.07:55:29.53#ibcon#about to write, iclass 11, count 0 2006.182.07:55:29.53#ibcon#wrote, iclass 11, count 0 2006.182.07:55:29.53#ibcon#about to read 3, iclass 11, count 0 2006.182.07:55:29.55#ibcon#read 3, iclass 11, count 0 2006.182.07:55:29.55#ibcon#about to read 4, iclass 11, count 0 2006.182.07:55:29.56#ibcon#read 4, iclass 11, count 0 2006.182.07:55:29.56#ibcon#about to read 5, iclass 11, count 0 2006.182.07:55:29.56#ibcon#read 5, iclass 11, count 0 2006.182.07:55:29.56#ibcon#about to read 6, iclass 11, count 0 2006.182.07:55:29.56#ibcon#read 6, iclass 11, count 0 2006.182.07:55:29.56#ibcon#end of sib2, iclass 11, count 0 2006.182.07:55:29.56#ibcon#*after write, iclass 11, count 0 2006.182.07:55:29.56#ibcon#*before return 0, iclass 11, count 0 2006.182.07:55:29.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:29.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:29.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:55:29.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:55:29.56$vc4f8/valo=6,772.99 2006.182.07:55:29.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.07:55:29.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.07:55:29.56#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:29.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:29.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:29.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:29.56#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:55:29.56#ibcon#first serial, iclass 13, count 0 2006.182.07:55:29.56#ibcon#enter sib2, iclass 13, count 0 2006.182.07:55:29.56#ibcon#flushed, iclass 13, count 0 2006.182.07:55:29.56#ibcon#about to write, iclass 13, count 0 2006.182.07:55:29.56#ibcon#wrote, iclass 13, count 0 2006.182.07:55:29.56#ibcon#about to read 3, iclass 13, count 0 2006.182.07:55:29.57#ibcon#read 3, iclass 13, count 0 2006.182.07:55:29.57#ibcon#about to read 4, iclass 13, count 0 2006.182.07:55:29.58#ibcon#read 4, iclass 13, count 0 2006.182.07:55:29.58#ibcon#about to read 5, iclass 13, count 0 2006.182.07:55:29.58#ibcon#read 5, iclass 13, count 0 2006.182.07:55:29.58#ibcon#about to read 6, iclass 13, count 0 2006.182.07:55:29.58#ibcon#read 6, iclass 13, count 0 2006.182.07:55:29.58#ibcon#end of sib2, iclass 13, count 0 2006.182.07:55:29.58#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:55:29.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:55:29.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:55:29.58#ibcon#*before write, iclass 13, count 0 2006.182.07:55:29.58#ibcon#enter sib2, iclass 13, count 0 2006.182.07:55:29.58#ibcon#flushed, iclass 13, count 0 2006.182.07:55:29.58#ibcon#about to write, iclass 13, count 0 2006.182.07:55:29.58#ibcon#wrote, iclass 13, count 0 2006.182.07:55:29.58#ibcon#about to read 3, iclass 13, count 0 2006.182.07:55:29.61#ibcon#read 3, iclass 13, count 0 2006.182.07:55:29.61#ibcon#about to read 4, iclass 13, count 0 2006.182.07:55:29.62#ibcon#read 4, iclass 13, count 0 2006.182.07:55:29.62#ibcon#about to read 5, iclass 13, count 0 2006.182.07:55:29.62#ibcon#read 5, iclass 13, count 0 2006.182.07:55:29.62#ibcon#about to read 6, iclass 13, count 0 2006.182.07:55:29.62#ibcon#read 6, iclass 13, count 0 2006.182.07:55:29.62#ibcon#end of sib2, iclass 13, count 0 2006.182.07:55:29.62#ibcon#*after write, iclass 13, count 0 2006.182.07:55:29.62#ibcon#*before return 0, iclass 13, count 0 2006.182.07:55:29.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:29.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:29.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:55:29.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:55:29.62$vc4f8/va=6,6 2006.182.07:55:29.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.182.07:55:29.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.182.07:55:29.62#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:29.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:55:29.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:55:29.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:55:29.67#ibcon#enter wrdev, iclass 15, count 2 2006.182.07:55:29.67#ibcon#first serial, iclass 15, count 2 2006.182.07:55:29.68#ibcon#enter sib2, iclass 15, count 2 2006.182.07:55:29.68#ibcon#flushed, iclass 15, count 2 2006.182.07:55:29.68#ibcon#about to write, iclass 15, count 2 2006.182.07:55:29.68#ibcon#wrote, iclass 15, count 2 2006.182.07:55:29.68#ibcon#about to read 3, iclass 15, count 2 2006.182.07:55:29.69#ibcon#read 3, iclass 15, count 2 2006.182.07:55:29.69#ibcon#about to read 4, iclass 15, count 2 2006.182.07:55:29.70#ibcon#read 4, iclass 15, count 2 2006.182.07:55:29.70#ibcon#about to read 5, iclass 15, count 2 2006.182.07:55:29.70#ibcon#read 5, iclass 15, count 2 2006.182.07:55:29.70#ibcon#about to read 6, iclass 15, count 2 2006.182.07:55:29.70#ibcon#read 6, iclass 15, count 2 2006.182.07:55:29.70#ibcon#end of sib2, iclass 15, count 2 2006.182.07:55:29.70#ibcon#*mode == 0, iclass 15, count 2 2006.182.07:55:29.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.182.07:55:29.70#ibcon#[25=AT06-06\r\n] 2006.182.07:55:29.70#ibcon#*before write, iclass 15, count 2 2006.182.07:55:29.70#ibcon#enter sib2, iclass 15, count 2 2006.182.07:55:29.70#ibcon#flushed, iclass 15, count 2 2006.182.07:55:29.70#ibcon#about to write, iclass 15, count 2 2006.182.07:55:29.70#ibcon#wrote, iclass 15, count 2 2006.182.07:55:29.70#ibcon#about to read 3, iclass 15, count 2 2006.182.07:55:29.72#ibcon#read 3, iclass 15, count 2 2006.182.07:55:29.73#ibcon#about to read 4, iclass 15, count 2 2006.182.07:55:29.73#ibcon#read 4, iclass 15, count 2 2006.182.07:55:29.73#ibcon#about to read 5, iclass 15, count 2 2006.182.07:55:29.73#ibcon#read 5, iclass 15, count 2 2006.182.07:55:29.73#ibcon#about to read 6, iclass 15, count 2 2006.182.07:55:29.73#ibcon#read 6, iclass 15, count 2 2006.182.07:55:29.73#ibcon#end of sib2, iclass 15, count 2 2006.182.07:55:29.73#ibcon#*after write, iclass 15, count 2 2006.182.07:55:29.73#ibcon#*before return 0, iclass 15, count 2 2006.182.07:55:29.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:55:29.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.182.07:55:29.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.182.07:55:29.73#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:29.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:55:29.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:55:29.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:55:29.84#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:55:29.84#ibcon#first serial, iclass 15, count 0 2006.182.07:55:29.85#ibcon#enter sib2, iclass 15, count 0 2006.182.07:55:29.85#ibcon#flushed, iclass 15, count 0 2006.182.07:55:29.85#ibcon#about to write, iclass 15, count 0 2006.182.07:55:29.85#ibcon#wrote, iclass 15, count 0 2006.182.07:55:29.85#ibcon#about to read 3, iclass 15, count 0 2006.182.07:55:29.86#ibcon#read 3, iclass 15, count 0 2006.182.07:55:29.86#ibcon#about to read 4, iclass 15, count 0 2006.182.07:55:29.87#ibcon#read 4, iclass 15, count 0 2006.182.07:55:29.87#ibcon#about to read 5, iclass 15, count 0 2006.182.07:55:29.87#ibcon#read 5, iclass 15, count 0 2006.182.07:55:29.87#ibcon#about to read 6, iclass 15, count 0 2006.182.07:55:29.87#ibcon#read 6, iclass 15, count 0 2006.182.07:55:29.87#ibcon#end of sib2, iclass 15, count 0 2006.182.07:55:29.87#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:55:29.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:55:29.87#ibcon#[25=USB\r\n] 2006.182.07:55:29.87#ibcon#*before write, iclass 15, count 0 2006.182.07:55:29.87#ibcon#enter sib2, iclass 15, count 0 2006.182.07:55:29.87#ibcon#flushed, iclass 15, count 0 2006.182.07:55:29.87#ibcon#about to write, iclass 15, count 0 2006.182.07:55:29.87#ibcon#wrote, iclass 15, count 0 2006.182.07:55:29.87#ibcon#about to read 3, iclass 15, count 0 2006.182.07:55:29.89#ibcon#read 3, iclass 15, count 0 2006.182.07:55:29.89#ibcon#about to read 4, iclass 15, count 0 2006.182.07:55:29.90#ibcon#read 4, iclass 15, count 0 2006.182.07:55:29.90#ibcon#about to read 5, iclass 15, count 0 2006.182.07:55:29.90#ibcon#read 5, iclass 15, count 0 2006.182.07:55:29.90#ibcon#about to read 6, iclass 15, count 0 2006.182.07:55:29.90#ibcon#read 6, iclass 15, count 0 2006.182.07:55:29.90#ibcon#end of sib2, iclass 15, count 0 2006.182.07:55:29.90#ibcon#*after write, iclass 15, count 0 2006.182.07:55:29.90#ibcon#*before return 0, iclass 15, count 0 2006.182.07:55:29.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:55:29.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.182.07:55:29.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:55:29.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:55:29.90$vc4f8/valo=7,832.99 2006.182.07:55:29.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.07:55:29.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.07:55:29.90#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:29.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:55:29.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:55:29.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:55:29.90#ibcon#enter wrdev, iclass 17, count 0 2006.182.07:55:29.90#ibcon#first serial, iclass 17, count 0 2006.182.07:55:29.90#ibcon#enter sib2, iclass 17, count 0 2006.182.07:55:29.90#ibcon#flushed, iclass 17, count 0 2006.182.07:55:29.90#ibcon#about to write, iclass 17, count 0 2006.182.07:55:29.90#ibcon#wrote, iclass 17, count 0 2006.182.07:55:29.90#ibcon#about to read 3, iclass 17, count 0 2006.182.07:55:29.91#ibcon#read 3, iclass 17, count 0 2006.182.07:55:29.91#ibcon#about to read 4, iclass 17, count 0 2006.182.07:55:29.92#ibcon#read 4, iclass 17, count 0 2006.182.07:55:29.92#ibcon#about to read 5, iclass 17, count 0 2006.182.07:55:29.92#ibcon#read 5, iclass 17, count 0 2006.182.07:55:29.92#ibcon#about to read 6, iclass 17, count 0 2006.182.07:55:29.92#ibcon#read 6, iclass 17, count 0 2006.182.07:55:29.92#ibcon#end of sib2, iclass 17, count 0 2006.182.07:55:29.92#ibcon#*mode == 0, iclass 17, count 0 2006.182.07:55:29.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.07:55:29.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:55:29.92#ibcon#*before write, iclass 17, count 0 2006.182.07:55:29.92#ibcon#enter sib2, iclass 17, count 0 2006.182.07:55:29.92#ibcon#flushed, iclass 17, count 0 2006.182.07:55:29.92#ibcon#about to write, iclass 17, count 0 2006.182.07:55:29.92#ibcon#wrote, iclass 17, count 0 2006.182.07:55:29.92#ibcon#about to read 3, iclass 17, count 0 2006.182.07:55:29.95#ibcon#read 3, iclass 17, count 0 2006.182.07:55:29.95#ibcon#about to read 4, iclass 17, count 0 2006.182.07:55:29.96#ibcon#read 4, iclass 17, count 0 2006.182.07:55:29.96#ibcon#about to read 5, iclass 17, count 0 2006.182.07:55:29.96#ibcon#read 5, iclass 17, count 0 2006.182.07:55:29.96#ibcon#about to read 6, iclass 17, count 0 2006.182.07:55:29.96#ibcon#read 6, iclass 17, count 0 2006.182.07:55:29.96#ibcon#end of sib2, iclass 17, count 0 2006.182.07:55:29.96#ibcon#*after write, iclass 17, count 0 2006.182.07:55:29.96#ibcon#*before return 0, iclass 17, count 0 2006.182.07:55:29.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:55:29.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.07:55:29.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.07:55:29.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.07:55:29.96$vc4f8/va=7,6 2006.182.07:55:29.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.182.07:55:29.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.182.07:55:29.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:29.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:55:30.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:55:30.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:55:30.01#ibcon#enter wrdev, iclass 19, count 2 2006.182.07:55:30.01#ibcon#first serial, iclass 19, count 2 2006.182.07:55:30.02#ibcon#enter sib2, iclass 19, count 2 2006.182.07:55:30.02#ibcon#flushed, iclass 19, count 2 2006.182.07:55:30.02#ibcon#about to write, iclass 19, count 2 2006.182.07:55:30.02#ibcon#wrote, iclass 19, count 2 2006.182.07:55:30.02#ibcon#about to read 3, iclass 19, count 2 2006.182.07:55:30.03#ibcon#read 3, iclass 19, count 2 2006.182.07:55:30.03#ibcon#about to read 4, iclass 19, count 2 2006.182.07:55:30.03#ibcon#read 4, iclass 19, count 2 2006.182.07:55:30.04#ibcon#about to read 5, iclass 19, count 2 2006.182.07:55:30.04#ibcon#read 5, iclass 19, count 2 2006.182.07:55:30.04#ibcon#about to read 6, iclass 19, count 2 2006.182.07:55:30.04#ibcon#read 6, iclass 19, count 2 2006.182.07:55:30.04#ibcon#end of sib2, iclass 19, count 2 2006.182.07:55:30.04#ibcon#*mode == 0, iclass 19, count 2 2006.182.07:55:30.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.182.07:55:30.04#ibcon#[25=AT07-06\r\n] 2006.182.07:55:30.04#ibcon#*before write, iclass 19, count 2 2006.182.07:55:30.04#ibcon#enter sib2, iclass 19, count 2 2006.182.07:55:30.04#ibcon#flushed, iclass 19, count 2 2006.182.07:55:30.04#ibcon#about to write, iclass 19, count 2 2006.182.07:55:30.04#ibcon#wrote, iclass 19, count 2 2006.182.07:55:30.04#ibcon#about to read 3, iclass 19, count 2 2006.182.07:55:30.06#ibcon#read 3, iclass 19, count 2 2006.182.07:55:30.07#ibcon#about to read 4, iclass 19, count 2 2006.182.07:55:30.07#ibcon#read 4, iclass 19, count 2 2006.182.07:55:30.07#ibcon#about to read 5, iclass 19, count 2 2006.182.07:55:30.07#ibcon#read 5, iclass 19, count 2 2006.182.07:55:30.07#ibcon#about to read 6, iclass 19, count 2 2006.182.07:55:30.07#ibcon#read 6, iclass 19, count 2 2006.182.07:55:30.07#ibcon#end of sib2, iclass 19, count 2 2006.182.07:55:30.07#ibcon#*after write, iclass 19, count 2 2006.182.07:55:30.07#ibcon#*before return 0, iclass 19, count 2 2006.182.07:55:30.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:55:30.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.182.07:55:30.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.182.07:55:30.07#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:30.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:55:30.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:55:30.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:55:30.18#ibcon#enter wrdev, iclass 19, count 0 2006.182.07:55:30.18#ibcon#first serial, iclass 19, count 0 2006.182.07:55:30.18#ibcon#enter sib2, iclass 19, count 0 2006.182.07:55:30.19#ibcon#flushed, iclass 19, count 0 2006.182.07:55:30.19#ibcon#about to write, iclass 19, count 0 2006.182.07:55:30.19#ibcon#wrote, iclass 19, count 0 2006.182.07:55:30.19#ibcon#about to read 3, iclass 19, count 0 2006.182.07:55:30.20#ibcon#read 3, iclass 19, count 0 2006.182.07:55:30.20#ibcon#about to read 4, iclass 19, count 0 2006.182.07:55:30.20#ibcon#read 4, iclass 19, count 0 2006.182.07:55:30.21#ibcon#about to read 5, iclass 19, count 0 2006.182.07:55:30.21#ibcon#read 5, iclass 19, count 0 2006.182.07:55:30.21#ibcon#about to read 6, iclass 19, count 0 2006.182.07:55:30.21#ibcon#read 6, iclass 19, count 0 2006.182.07:55:30.21#ibcon#end of sib2, iclass 19, count 0 2006.182.07:55:30.21#ibcon#*mode == 0, iclass 19, count 0 2006.182.07:55:30.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.07:55:30.21#ibcon#[25=USB\r\n] 2006.182.07:55:30.21#ibcon#*before write, iclass 19, count 0 2006.182.07:55:30.21#ibcon#enter sib2, iclass 19, count 0 2006.182.07:55:30.21#ibcon#flushed, iclass 19, count 0 2006.182.07:55:30.21#ibcon#about to write, iclass 19, count 0 2006.182.07:55:30.21#ibcon#wrote, iclass 19, count 0 2006.182.07:55:30.21#ibcon#about to read 3, iclass 19, count 0 2006.182.07:55:30.23#ibcon#read 3, iclass 19, count 0 2006.182.07:55:30.24#ibcon#about to read 4, iclass 19, count 0 2006.182.07:55:30.24#ibcon#read 4, iclass 19, count 0 2006.182.07:55:30.24#ibcon#about to read 5, iclass 19, count 0 2006.182.07:55:30.24#ibcon#read 5, iclass 19, count 0 2006.182.07:55:30.24#ibcon#about to read 6, iclass 19, count 0 2006.182.07:55:30.24#ibcon#read 6, iclass 19, count 0 2006.182.07:55:30.24#ibcon#end of sib2, iclass 19, count 0 2006.182.07:55:30.24#ibcon#*after write, iclass 19, count 0 2006.182.07:55:30.24#ibcon#*before return 0, iclass 19, count 0 2006.182.07:55:30.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:55:30.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.182.07:55:30.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.07:55:30.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.07:55:30.24$vc4f8/valo=8,852.99 2006.182.07:55:30.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.07:55:30.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.07:55:30.24#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:30.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:55:30.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:55:30.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:55:30.24#ibcon#enter wrdev, iclass 21, count 0 2006.182.07:55:30.24#ibcon#first serial, iclass 21, count 0 2006.182.07:55:30.24#ibcon#enter sib2, iclass 21, count 0 2006.182.07:55:30.24#ibcon#flushed, iclass 21, count 0 2006.182.07:55:30.24#ibcon#about to write, iclass 21, count 0 2006.182.07:55:30.24#ibcon#wrote, iclass 21, count 0 2006.182.07:55:30.24#ibcon#about to read 3, iclass 21, count 0 2006.182.07:55:30.25#ibcon#read 3, iclass 21, count 0 2006.182.07:55:30.25#ibcon#about to read 4, iclass 21, count 0 2006.182.07:55:30.26#ibcon#read 4, iclass 21, count 0 2006.182.07:55:30.26#ibcon#about to read 5, iclass 21, count 0 2006.182.07:55:30.26#ibcon#read 5, iclass 21, count 0 2006.182.07:55:30.26#ibcon#about to read 6, iclass 21, count 0 2006.182.07:55:30.26#ibcon#read 6, iclass 21, count 0 2006.182.07:55:30.26#ibcon#end of sib2, iclass 21, count 0 2006.182.07:55:30.26#ibcon#*mode == 0, iclass 21, count 0 2006.182.07:55:30.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.07:55:30.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:55:30.26#ibcon#*before write, iclass 21, count 0 2006.182.07:55:30.26#ibcon#enter sib2, iclass 21, count 0 2006.182.07:55:30.26#ibcon#flushed, iclass 21, count 0 2006.182.07:55:30.26#ibcon#about to write, iclass 21, count 0 2006.182.07:55:30.26#ibcon#wrote, iclass 21, count 0 2006.182.07:55:30.26#ibcon#about to read 3, iclass 21, count 0 2006.182.07:55:30.29#ibcon#read 3, iclass 21, count 0 2006.182.07:55:30.29#ibcon#about to read 4, iclass 21, count 0 2006.182.07:55:30.29#ibcon#read 4, iclass 21, count 0 2006.182.07:55:30.30#ibcon#about to read 5, iclass 21, count 0 2006.182.07:55:30.30#ibcon#read 5, iclass 21, count 0 2006.182.07:55:30.30#ibcon#about to read 6, iclass 21, count 0 2006.182.07:55:30.30#ibcon#read 6, iclass 21, count 0 2006.182.07:55:30.30#ibcon#end of sib2, iclass 21, count 0 2006.182.07:55:30.30#ibcon#*after write, iclass 21, count 0 2006.182.07:55:30.30#ibcon#*before return 0, iclass 21, count 0 2006.182.07:55:30.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:55:30.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.07:55:30.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.07:55:30.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.07:55:30.30$vc4f8/va=8,7 2006.182.07:55:30.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.182.07:55:30.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.182.07:55:30.30#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:30.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:55:30.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:55:30.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:55:30.35#ibcon#enter wrdev, iclass 23, count 2 2006.182.07:55:30.35#ibcon#first serial, iclass 23, count 2 2006.182.07:55:30.36#ibcon#enter sib2, iclass 23, count 2 2006.182.07:55:30.36#ibcon#flushed, iclass 23, count 2 2006.182.07:55:30.36#ibcon#about to write, iclass 23, count 2 2006.182.07:55:30.36#ibcon#wrote, iclass 23, count 2 2006.182.07:55:30.36#ibcon#about to read 3, iclass 23, count 2 2006.182.07:55:30.37#ibcon#read 3, iclass 23, count 2 2006.182.07:55:30.37#ibcon#about to read 4, iclass 23, count 2 2006.182.07:55:30.38#ibcon#read 4, iclass 23, count 2 2006.182.07:55:30.38#ibcon#about to read 5, iclass 23, count 2 2006.182.07:55:30.38#ibcon#read 5, iclass 23, count 2 2006.182.07:55:30.38#ibcon#about to read 6, iclass 23, count 2 2006.182.07:55:30.38#ibcon#read 6, iclass 23, count 2 2006.182.07:55:30.38#ibcon#end of sib2, iclass 23, count 2 2006.182.07:55:30.38#ibcon#*mode == 0, iclass 23, count 2 2006.182.07:55:30.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.182.07:55:30.38#ibcon#[25=AT08-07\r\n] 2006.182.07:55:30.38#ibcon#*before write, iclass 23, count 2 2006.182.07:55:30.38#ibcon#enter sib2, iclass 23, count 2 2006.182.07:55:30.38#ibcon#flushed, iclass 23, count 2 2006.182.07:55:30.38#ibcon#about to write, iclass 23, count 2 2006.182.07:55:30.38#ibcon#wrote, iclass 23, count 2 2006.182.07:55:30.38#ibcon#about to read 3, iclass 23, count 2 2006.182.07:55:30.40#ibcon#read 3, iclass 23, count 2 2006.182.07:55:30.40#ibcon#about to read 4, iclass 23, count 2 2006.182.07:55:30.40#ibcon#read 4, iclass 23, count 2 2006.182.07:55:30.41#ibcon#about to read 5, iclass 23, count 2 2006.182.07:55:30.41#ibcon#read 5, iclass 23, count 2 2006.182.07:55:30.41#ibcon#about to read 6, iclass 23, count 2 2006.182.07:55:30.41#ibcon#read 6, iclass 23, count 2 2006.182.07:55:30.41#ibcon#end of sib2, iclass 23, count 2 2006.182.07:55:30.41#ibcon#*after write, iclass 23, count 2 2006.182.07:55:30.41#ibcon#*before return 0, iclass 23, count 2 2006.182.07:55:30.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:55:30.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.182.07:55:30.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.182.07:55:30.41#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:30.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:55:30.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:55:30.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:55:30.52#ibcon#enter wrdev, iclass 23, count 0 2006.182.07:55:30.52#ibcon#first serial, iclass 23, count 0 2006.182.07:55:30.53#ibcon#enter sib2, iclass 23, count 0 2006.182.07:55:30.53#ibcon#flushed, iclass 23, count 0 2006.182.07:55:30.53#ibcon#about to write, iclass 23, count 0 2006.182.07:55:30.53#ibcon#wrote, iclass 23, count 0 2006.182.07:55:30.53#ibcon#about to read 3, iclass 23, count 0 2006.182.07:55:30.54#ibcon#read 3, iclass 23, count 0 2006.182.07:55:30.54#ibcon#about to read 4, iclass 23, count 0 2006.182.07:55:30.54#ibcon#read 4, iclass 23, count 0 2006.182.07:55:30.55#ibcon#about to read 5, iclass 23, count 0 2006.182.07:55:30.55#ibcon#read 5, iclass 23, count 0 2006.182.07:55:30.55#ibcon#about to read 6, iclass 23, count 0 2006.182.07:55:30.55#ibcon#read 6, iclass 23, count 0 2006.182.07:55:30.55#ibcon#end of sib2, iclass 23, count 0 2006.182.07:55:30.55#ibcon#*mode == 0, iclass 23, count 0 2006.182.07:55:30.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.07:55:30.55#ibcon#[25=USB\r\n] 2006.182.07:55:30.55#ibcon#*before write, iclass 23, count 0 2006.182.07:55:30.55#ibcon#enter sib2, iclass 23, count 0 2006.182.07:55:30.55#ibcon#flushed, iclass 23, count 0 2006.182.07:55:30.55#ibcon#about to write, iclass 23, count 0 2006.182.07:55:30.55#ibcon#wrote, iclass 23, count 0 2006.182.07:55:30.55#ibcon#about to read 3, iclass 23, count 0 2006.182.07:55:30.57#ibcon#read 3, iclass 23, count 0 2006.182.07:55:30.57#ibcon#about to read 4, iclass 23, count 0 2006.182.07:55:30.57#ibcon#read 4, iclass 23, count 0 2006.182.07:55:30.58#ibcon#about to read 5, iclass 23, count 0 2006.182.07:55:30.58#ibcon#read 5, iclass 23, count 0 2006.182.07:55:30.58#ibcon#about to read 6, iclass 23, count 0 2006.182.07:55:30.58#ibcon#read 6, iclass 23, count 0 2006.182.07:55:30.58#ibcon#end of sib2, iclass 23, count 0 2006.182.07:55:30.58#ibcon#*after write, iclass 23, count 0 2006.182.07:55:30.58#ibcon#*before return 0, iclass 23, count 0 2006.182.07:55:30.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:55:30.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.182.07:55:30.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.07:55:30.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.07:55:30.58$vc4f8/vblo=1,632.99 2006.182.07:55:30.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.07:55:30.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.07:55:30.58#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:30.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:30.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:30.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:30.58#ibcon#enter wrdev, iclass 25, count 0 2006.182.07:55:30.58#ibcon#first serial, iclass 25, count 0 2006.182.07:55:30.58#ibcon#enter sib2, iclass 25, count 0 2006.182.07:55:30.58#ibcon#flushed, iclass 25, count 0 2006.182.07:55:30.58#ibcon#about to write, iclass 25, count 0 2006.182.07:55:30.58#ibcon#wrote, iclass 25, count 0 2006.182.07:55:30.58#ibcon#about to read 3, iclass 25, count 0 2006.182.07:55:30.59#ibcon#read 3, iclass 25, count 0 2006.182.07:55:30.59#ibcon#about to read 4, iclass 25, count 0 2006.182.07:55:30.59#ibcon#read 4, iclass 25, count 0 2006.182.07:55:30.60#ibcon#about to read 5, iclass 25, count 0 2006.182.07:55:30.60#ibcon#read 5, iclass 25, count 0 2006.182.07:55:30.60#ibcon#about to read 6, iclass 25, count 0 2006.182.07:55:30.60#ibcon#read 6, iclass 25, count 0 2006.182.07:55:30.60#ibcon#end of sib2, iclass 25, count 0 2006.182.07:55:30.60#ibcon#*mode == 0, iclass 25, count 0 2006.182.07:55:30.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.07:55:30.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:55:30.60#ibcon#*before write, iclass 25, count 0 2006.182.07:55:30.60#ibcon#enter sib2, iclass 25, count 0 2006.182.07:55:30.60#ibcon#flushed, iclass 25, count 0 2006.182.07:55:30.60#ibcon#about to write, iclass 25, count 0 2006.182.07:55:30.60#ibcon#wrote, iclass 25, count 0 2006.182.07:55:30.60#ibcon#about to read 3, iclass 25, count 0 2006.182.07:55:30.63#ibcon#read 3, iclass 25, count 0 2006.182.07:55:30.63#ibcon#about to read 4, iclass 25, count 0 2006.182.07:55:30.63#ibcon#read 4, iclass 25, count 0 2006.182.07:55:30.64#ibcon#about to read 5, iclass 25, count 0 2006.182.07:55:30.64#ibcon#read 5, iclass 25, count 0 2006.182.07:55:30.64#ibcon#about to read 6, iclass 25, count 0 2006.182.07:55:30.64#ibcon#read 6, iclass 25, count 0 2006.182.07:55:30.64#ibcon#end of sib2, iclass 25, count 0 2006.182.07:55:30.64#ibcon#*after write, iclass 25, count 0 2006.182.07:55:30.64#ibcon#*before return 0, iclass 25, count 0 2006.182.07:55:30.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:30.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.07:55:30.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.07:55:30.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.07:55:30.64$vc4f8/vb=1,4 2006.182.07:55:30.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.182.07:55:30.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.182.07:55:30.64#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:30.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:30.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:30.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:30.64#ibcon#enter wrdev, iclass 27, count 2 2006.182.07:55:30.64#ibcon#first serial, iclass 27, count 2 2006.182.07:55:30.64#ibcon#enter sib2, iclass 27, count 2 2006.182.07:55:30.64#ibcon#flushed, iclass 27, count 2 2006.182.07:55:30.64#ibcon#about to write, iclass 27, count 2 2006.182.07:55:30.64#ibcon#wrote, iclass 27, count 2 2006.182.07:55:30.64#ibcon#about to read 3, iclass 27, count 2 2006.182.07:55:30.65#ibcon#read 3, iclass 27, count 2 2006.182.07:55:30.65#ibcon#about to read 4, iclass 27, count 2 2006.182.07:55:30.65#ibcon#read 4, iclass 27, count 2 2006.182.07:55:30.66#ibcon#about to read 5, iclass 27, count 2 2006.182.07:55:30.66#ibcon#read 5, iclass 27, count 2 2006.182.07:55:30.66#ibcon#about to read 6, iclass 27, count 2 2006.182.07:55:30.66#ibcon#read 6, iclass 27, count 2 2006.182.07:55:30.66#ibcon#end of sib2, iclass 27, count 2 2006.182.07:55:30.66#ibcon#*mode == 0, iclass 27, count 2 2006.182.07:55:30.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.182.07:55:30.66#ibcon#[27=AT01-04\r\n] 2006.182.07:55:30.66#ibcon#*before write, iclass 27, count 2 2006.182.07:55:30.66#ibcon#enter sib2, iclass 27, count 2 2006.182.07:55:30.66#ibcon#flushed, iclass 27, count 2 2006.182.07:55:30.66#ibcon#about to write, iclass 27, count 2 2006.182.07:55:30.66#ibcon#wrote, iclass 27, count 2 2006.182.07:55:30.66#ibcon#about to read 3, iclass 27, count 2 2006.182.07:55:30.68#ibcon#read 3, iclass 27, count 2 2006.182.07:55:30.68#ibcon#about to read 4, iclass 27, count 2 2006.182.07:55:30.69#ibcon#read 4, iclass 27, count 2 2006.182.07:55:30.69#ibcon#about to read 5, iclass 27, count 2 2006.182.07:55:30.69#ibcon#read 5, iclass 27, count 2 2006.182.07:55:30.69#ibcon#about to read 6, iclass 27, count 2 2006.182.07:55:30.69#ibcon#read 6, iclass 27, count 2 2006.182.07:55:30.69#ibcon#end of sib2, iclass 27, count 2 2006.182.07:55:30.69#ibcon#*after write, iclass 27, count 2 2006.182.07:55:30.69#ibcon#*before return 0, iclass 27, count 2 2006.182.07:55:30.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:30.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.182.07:55:30.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.182.07:55:30.69#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:30.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:30.80#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:30.80#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:30.80#ibcon#enter wrdev, iclass 27, count 0 2006.182.07:55:30.80#ibcon#first serial, iclass 27, count 0 2006.182.07:55:30.81#ibcon#enter sib2, iclass 27, count 0 2006.182.07:55:30.81#ibcon#flushed, iclass 27, count 0 2006.182.07:55:30.81#ibcon#about to write, iclass 27, count 0 2006.182.07:55:30.81#ibcon#wrote, iclass 27, count 0 2006.182.07:55:30.81#ibcon#about to read 3, iclass 27, count 0 2006.182.07:55:30.82#ibcon#read 3, iclass 27, count 0 2006.182.07:55:30.82#ibcon#about to read 4, iclass 27, count 0 2006.182.07:55:30.82#ibcon#read 4, iclass 27, count 0 2006.182.07:55:30.83#ibcon#about to read 5, iclass 27, count 0 2006.182.07:55:30.83#ibcon#read 5, iclass 27, count 0 2006.182.07:55:30.83#ibcon#about to read 6, iclass 27, count 0 2006.182.07:55:30.83#ibcon#read 6, iclass 27, count 0 2006.182.07:55:30.83#ibcon#end of sib2, iclass 27, count 0 2006.182.07:55:30.83#ibcon#*mode == 0, iclass 27, count 0 2006.182.07:55:30.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.07:55:30.83#ibcon#[27=USB\r\n] 2006.182.07:55:30.83#ibcon#*before write, iclass 27, count 0 2006.182.07:55:30.83#ibcon#enter sib2, iclass 27, count 0 2006.182.07:55:30.83#ibcon#flushed, iclass 27, count 0 2006.182.07:55:30.83#ibcon#about to write, iclass 27, count 0 2006.182.07:55:30.83#ibcon#wrote, iclass 27, count 0 2006.182.07:55:30.83#ibcon#about to read 3, iclass 27, count 0 2006.182.07:55:30.85#ibcon#read 3, iclass 27, count 0 2006.182.07:55:30.85#ibcon#about to read 4, iclass 27, count 0 2006.182.07:55:30.85#ibcon#read 4, iclass 27, count 0 2006.182.07:55:30.86#ibcon#about to read 5, iclass 27, count 0 2006.182.07:55:30.86#ibcon#read 5, iclass 27, count 0 2006.182.07:55:30.86#ibcon#about to read 6, iclass 27, count 0 2006.182.07:55:30.86#ibcon#read 6, iclass 27, count 0 2006.182.07:55:30.86#ibcon#end of sib2, iclass 27, count 0 2006.182.07:55:30.86#ibcon#*after write, iclass 27, count 0 2006.182.07:55:30.86#ibcon#*before return 0, iclass 27, count 0 2006.182.07:55:30.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:30.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.182.07:55:30.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.07:55:30.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.07:55:30.86$vc4f8/vblo=2,640.99 2006.182.07:55:30.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.07:55:30.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.07:55:30.86#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:30.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:55:30.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:55:30.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:55:30.86#ibcon#enter wrdev, iclass 29, count 0 2006.182.07:55:30.86#ibcon#first serial, iclass 29, count 0 2006.182.07:55:30.86#ibcon#enter sib2, iclass 29, count 0 2006.182.07:55:30.86#ibcon#flushed, iclass 29, count 0 2006.182.07:55:30.86#ibcon#about to write, iclass 29, count 0 2006.182.07:55:30.86#ibcon#wrote, iclass 29, count 0 2006.182.07:55:30.86#ibcon#about to read 3, iclass 29, count 0 2006.182.07:55:30.87#ibcon#read 3, iclass 29, count 0 2006.182.07:55:30.87#ibcon#about to read 4, iclass 29, count 0 2006.182.07:55:30.87#ibcon#read 4, iclass 29, count 0 2006.182.07:55:30.88#ibcon#about to read 5, iclass 29, count 0 2006.182.07:55:30.88#ibcon#read 5, iclass 29, count 0 2006.182.07:55:30.88#ibcon#about to read 6, iclass 29, count 0 2006.182.07:55:30.88#ibcon#read 6, iclass 29, count 0 2006.182.07:55:30.88#ibcon#end of sib2, iclass 29, count 0 2006.182.07:55:30.88#ibcon#*mode == 0, iclass 29, count 0 2006.182.07:55:30.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.07:55:30.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:55:30.88#ibcon#*before write, iclass 29, count 0 2006.182.07:55:30.88#ibcon#enter sib2, iclass 29, count 0 2006.182.07:55:30.88#ibcon#flushed, iclass 29, count 0 2006.182.07:55:30.88#ibcon#about to write, iclass 29, count 0 2006.182.07:55:30.88#ibcon#wrote, iclass 29, count 0 2006.182.07:55:30.88#ibcon#about to read 3, iclass 29, count 0 2006.182.07:55:30.91#ibcon#read 3, iclass 29, count 0 2006.182.07:55:30.91#ibcon#about to read 4, iclass 29, count 0 2006.182.07:55:30.91#ibcon#read 4, iclass 29, count 0 2006.182.07:55:30.92#ibcon#about to read 5, iclass 29, count 0 2006.182.07:55:30.92#ibcon#read 5, iclass 29, count 0 2006.182.07:55:30.92#ibcon#about to read 6, iclass 29, count 0 2006.182.07:55:30.92#ibcon#read 6, iclass 29, count 0 2006.182.07:55:30.92#ibcon#end of sib2, iclass 29, count 0 2006.182.07:55:30.92#ibcon#*after write, iclass 29, count 0 2006.182.07:55:30.92#ibcon#*before return 0, iclass 29, count 0 2006.182.07:55:30.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:55:30.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.07:55:30.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.07:55:30.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.07:55:30.92$vc4f8/vb=2,4 2006.182.07:55:30.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.182.07:55:30.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.182.07:55:30.92#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:30.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:55:30.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:55:30.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:55:30.97#ibcon#enter wrdev, iclass 31, count 2 2006.182.07:55:30.97#ibcon#first serial, iclass 31, count 2 2006.182.07:55:30.97#ibcon#enter sib2, iclass 31, count 2 2006.182.07:55:30.98#ibcon#flushed, iclass 31, count 2 2006.182.07:55:30.98#ibcon#about to write, iclass 31, count 2 2006.182.07:55:30.98#ibcon#wrote, iclass 31, count 2 2006.182.07:55:30.98#ibcon#about to read 3, iclass 31, count 2 2006.182.07:55:30.99#ibcon#read 3, iclass 31, count 2 2006.182.07:55:30.99#ibcon#about to read 4, iclass 31, count 2 2006.182.07:55:31.00#ibcon#read 4, iclass 31, count 2 2006.182.07:55:31.00#ibcon#about to read 5, iclass 31, count 2 2006.182.07:55:31.00#ibcon#read 5, iclass 31, count 2 2006.182.07:55:31.00#ibcon#about to read 6, iclass 31, count 2 2006.182.07:55:31.00#ibcon#read 6, iclass 31, count 2 2006.182.07:55:31.00#ibcon#end of sib2, iclass 31, count 2 2006.182.07:55:31.00#ibcon#*mode == 0, iclass 31, count 2 2006.182.07:55:31.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.182.07:55:31.00#ibcon#[27=AT02-04\r\n] 2006.182.07:55:31.00#ibcon#*before write, iclass 31, count 2 2006.182.07:55:31.00#ibcon#enter sib2, iclass 31, count 2 2006.182.07:55:31.00#ibcon#flushed, iclass 31, count 2 2006.182.07:55:31.00#ibcon#about to write, iclass 31, count 2 2006.182.07:55:31.00#ibcon#wrote, iclass 31, count 2 2006.182.07:55:31.00#ibcon#about to read 3, iclass 31, count 2 2006.182.07:55:31.02#ibcon#read 3, iclass 31, count 2 2006.182.07:55:31.03#ibcon#about to read 4, iclass 31, count 2 2006.182.07:55:31.03#ibcon#read 4, iclass 31, count 2 2006.182.07:55:31.03#ibcon#about to read 5, iclass 31, count 2 2006.182.07:55:31.03#ibcon#read 5, iclass 31, count 2 2006.182.07:55:31.03#ibcon#about to read 6, iclass 31, count 2 2006.182.07:55:31.03#ibcon#read 6, iclass 31, count 2 2006.182.07:55:31.03#ibcon#end of sib2, iclass 31, count 2 2006.182.07:55:31.03#ibcon#*after write, iclass 31, count 2 2006.182.07:55:31.03#ibcon#*before return 0, iclass 31, count 2 2006.182.07:55:31.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:55:31.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.182.07:55:31.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.182.07:55:31.03#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:31.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:55:31.14#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:55:31.14#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:55:31.14#ibcon#enter wrdev, iclass 31, count 0 2006.182.07:55:31.14#ibcon#first serial, iclass 31, count 0 2006.182.07:55:31.14#ibcon#enter sib2, iclass 31, count 0 2006.182.07:55:31.14#ibcon#flushed, iclass 31, count 0 2006.182.07:55:31.15#ibcon#about to write, iclass 31, count 0 2006.182.07:55:31.15#ibcon#wrote, iclass 31, count 0 2006.182.07:55:31.15#ibcon#about to read 3, iclass 31, count 0 2006.182.07:55:31.16#ibcon#read 3, iclass 31, count 0 2006.182.07:55:31.16#ibcon#about to read 4, iclass 31, count 0 2006.182.07:55:31.16#ibcon#read 4, iclass 31, count 0 2006.182.07:55:31.17#ibcon#about to read 5, iclass 31, count 0 2006.182.07:55:31.17#ibcon#read 5, iclass 31, count 0 2006.182.07:55:31.17#ibcon#about to read 6, iclass 31, count 0 2006.182.07:55:31.17#ibcon#read 6, iclass 31, count 0 2006.182.07:55:31.17#ibcon#end of sib2, iclass 31, count 0 2006.182.07:55:31.17#ibcon#*mode == 0, iclass 31, count 0 2006.182.07:55:31.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.07:55:31.17#ibcon#[27=USB\r\n] 2006.182.07:55:31.17#ibcon#*before write, iclass 31, count 0 2006.182.07:55:31.17#ibcon#enter sib2, iclass 31, count 0 2006.182.07:55:31.17#ibcon#flushed, iclass 31, count 0 2006.182.07:55:31.17#ibcon#about to write, iclass 31, count 0 2006.182.07:55:31.17#ibcon#wrote, iclass 31, count 0 2006.182.07:55:31.17#ibcon#about to read 3, iclass 31, count 0 2006.182.07:55:31.19#ibcon#read 3, iclass 31, count 0 2006.182.07:55:31.19#ibcon#about to read 4, iclass 31, count 0 2006.182.07:55:31.19#ibcon#read 4, iclass 31, count 0 2006.182.07:55:31.20#ibcon#about to read 5, iclass 31, count 0 2006.182.07:55:31.20#ibcon#read 5, iclass 31, count 0 2006.182.07:55:31.20#ibcon#about to read 6, iclass 31, count 0 2006.182.07:55:31.20#ibcon#read 6, iclass 31, count 0 2006.182.07:55:31.20#ibcon#end of sib2, iclass 31, count 0 2006.182.07:55:31.20#ibcon#*after write, iclass 31, count 0 2006.182.07:55:31.20#ibcon#*before return 0, iclass 31, count 0 2006.182.07:55:31.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:55:31.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.182.07:55:31.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.07:55:31.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.07:55:31.20$vc4f8/vblo=3,656.99 2006.182.07:55:31.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.182.07:55:31.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.182.07:55:31.20#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:31.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:31.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:31.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:31.20#ibcon#enter wrdev, iclass 33, count 0 2006.182.07:55:31.20#ibcon#first serial, iclass 33, count 0 2006.182.07:55:31.20#ibcon#enter sib2, iclass 33, count 0 2006.182.07:55:31.20#ibcon#flushed, iclass 33, count 0 2006.182.07:55:31.20#ibcon#about to write, iclass 33, count 0 2006.182.07:55:31.20#ibcon#wrote, iclass 33, count 0 2006.182.07:55:31.20#ibcon#about to read 3, iclass 33, count 0 2006.182.07:55:31.21#ibcon#read 3, iclass 33, count 0 2006.182.07:55:31.21#ibcon#about to read 4, iclass 33, count 0 2006.182.07:55:31.22#ibcon#read 4, iclass 33, count 0 2006.182.07:55:31.22#ibcon#about to read 5, iclass 33, count 0 2006.182.07:55:31.22#ibcon#read 5, iclass 33, count 0 2006.182.07:55:31.22#ibcon#about to read 6, iclass 33, count 0 2006.182.07:55:31.22#ibcon#read 6, iclass 33, count 0 2006.182.07:55:31.22#ibcon#end of sib2, iclass 33, count 0 2006.182.07:55:31.22#ibcon#*mode == 0, iclass 33, count 0 2006.182.07:55:31.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.07:55:31.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:55:31.22#ibcon#*before write, iclass 33, count 0 2006.182.07:55:31.22#ibcon#enter sib2, iclass 33, count 0 2006.182.07:55:31.22#ibcon#flushed, iclass 33, count 0 2006.182.07:55:31.22#ibcon#about to write, iclass 33, count 0 2006.182.07:55:31.22#ibcon#wrote, iclass 33, count 0 2006.182.07:55:31.22#ibcon#about to read 3, iclass 33, count 0 2006.182.07:55:31.25#ibcon#read 3, iclass 33, count 0 2006.182.07:55:31.25#ibcon#about to read 4, iclass 33, count 0 2006.182.07:55:31.25#ibcon#read 4, iclass 33, count 0 2006.182.07:55:31.26#ibcon#about to read 5, iclass 33, count 0 2006.182.07:55:31.26#ibcon#read 5, iclass 33, count 0 2006.182.07:55:31.26#ibcon#about to read 6, iclass 33, count 0 2006.182.07:55:31.26#ibcon#read 6, iclass 33, count 0 2006.182.07:55:31.26#ibcon#end of sib2, iclass 33, count 0 2006.182.07:55:31.26#ibcon#*after write, iclass 33, count 0 2006.182.07:55:31.26#ibcon#*before return 0, iclass 33, count 0 2006.182.07:55:31.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:31.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.182.07:55:31.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.07:55:31.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.07:55:31.26$vc4f8/vb=3,4 2006.182.07:55:31.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.182.07:55:31.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.182.07:55:31.26#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:31.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:31.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:31.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:31.31#ibcon#enter wrdev, iclass 35, count 2 2006.182.07:55:31.32#ibcon#first serial, iclass 35, count 2 2006.182.07:55:31.32#ibcon#enter sib2, iclass 35, count 2 2006.182.07:55:31.32#ibcon#flushed, iclass 35, count 2 2006.182.07:55:31.32#ibcon#about to write, iclass 35, count 2 2006.182.07:55:31.32#ibcon#wrote, iclass 35, count 2 2006.182.07:55:31.32#ibcon#about to read 3, iclass 35, count 2 2006.182.07:55:31.33#ibcon#read 3, iclass 35, count 2 2006.182.07:55:31.33#ibcon#about to read 4, iclass 35, count 2 2006.182.07:55:31.33#ibcon#read 4, iclass 35, count 2 2006.182.07:55:31.34#ibcon#about to read 5, iclass 35, count 2 2006.182.07:55:31.34#ibcon#read 5, iclass 35, count 2 2006.182.07:55:31.34#ibcon#about to read 6, iclass 35, count 2 2006.182.07:55:31.34#ibcon#read 6, iclass 35, count 2 2006.182.07:55:31.34#ibcon#end of sib2, iclass 35, count 2 2006.182.07:55:31.34#ibcon#*mode == 0, iclass 35, count 2 2006.182.07:55:31.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.182.07:55:31.34#ibcon#[27=AT03-04\r\n] 2006.182.07:55:31.34#ibcon#*before write, iclass 35, count 2 2006.182.07:55:31.34#ibcon#enter sib2, iclass 35, count 2 2006.182.07:55:31.34#ibcon#flushed, iclass 35, count 2 2006.182.07:55:31.34#ibcon#about to write, iclass 35, count 2 2006.182.07:55:31.34#ibcon#wrote, iclass 35, count 2 2006.182.07:55:31.34#ibcon#about to read 3, iclass 35, count 2 2006.182.07:55:31.36#ibcon#read 3, iclass 35, count 2 2006.182.07:55:31.36#ibcon#about to read 4, iclass 35, count 2 2006.182.07:55:31.36#ibcon#read 4, iclass 35, count 2 2006.182.07:55:31.37#ibcon#about to read 5, iclass 35, count 2 2006.182.07:55:31.37#ibcon#read 5, iclass 35, count 2 2006.182.07:55:31.37#ibcon#about to read 6, iclass 35, count 2 2006.182.07:55:31.37#ibcon#read 6, iclass 35, count 2 2006.182.07:55:31.37#ibcon#end of sib2, iclass 35, count 2 2006.182.07:55:31.37#ibcon#*after write, iclass 35, count 2 2006.182.07:55:31.37#ibcon#*before return 0, iclass 35, count 2 2006.182.07:55:31.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:31.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.182.07:55:31.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.182.07:55:31.37#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:31.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:31.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:31.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:31.48#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:55:31.48#ibcon#first serial, iclass 35, count 0 2006.182.07:55:31.49#ibcon#enter sib2, iclass 35, count 0 2006.182.07:55:31.49#ibcon#flushed, iclass 35, count 0 2006.182.07:55:31.49#ibcon#about to write, iclass 35, count 0 2006.182.07:55:31.49#ibcon#wrote, iclass 35, count 0 2006.182.07:55:31.49#ibcon#about to read 3, iclass 35, count 0 2006.182.07:55:31.50#ibcon#read 3, iclass 35, count 0 2006.182.07:55:31.50#ibcon#about to read 4, iclass 35, count 0 2006.182.07:55:31.50#ibcon#read 4, iclass 35, count 0 2006.182.07:55:31.51#ibcon#about to read 5, iclass 35, count 0 2006.182.07:55:31.51#ibcon#read 5, iclass 35, count 0 2006.182.07:55:31.51#ibcon#about to read 6, iclass 35, count 0 2006.182.07:55:31.51#ibcon#read 6, iclass 35, count 0 2006.182.07:55:31.51#ibcon#end of sib2, iclass 35, count 0 2006.182.07:55:31.51#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:55:31.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:55:31.51#ibcon#[27=USB\r\n] 2006.182.07:55:31.51#ibcon#*before write, iclass 35, count 0 2006.182.07:55:31.51#ibcon#enter sib2, iclass 35, count 0 2006.182.07:55:31.51#ibcon#flushed, iclass 35, count 0 2006.182.07:55:31.51#ibcon#about to write, iclass 35, count 0 2006.182.07:55:31.51#ibcon#wrote, iclass 35, count 0 2006.182.07:55:31.51#ibcon#about to read 3, iclass 35, count 0 2006.182.07:55:31.53#ibcon#read 3, iclass 35, count 0 2006.182.07:55:31.53#ibcon#about to read 4, iclass 35, count 0 2006.182.07:55:31.53#ibcon#read 4, iclass 35, count 0 2006.182.07:55:31.54#ibcon#about to read 5, iclass 35, count 0 2006.182.07:55:31.54#ibcon#read 5, iclass 35, count 0 2006.182.07:55:31.54#ibcon#about to read 6, iclass 35, count 0 2006.182.07:55:31.54#ibcon#read 6, iclass 35, count 0 2006.182.07:55:31.54#ibcon#end of sib2, iclass 35, count 0 2006.182.07:55:31.54#ibcon#*after write, iclass 35, count 0 2006.182.07:55:31.54#ibcon#*before return 0, iclass 35, count 0 2006.182.07:55:31.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:31.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.182.07:55:31.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:55:31.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:55:31.54$vc4f8/vblo=4,712.99 2006.182.07:55:31.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.182.07:55:31.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.182.07:55:31.54#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:31.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:31.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:31.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:31.54#ibcon#enter wrdev, iclass 37, count 0 2006.182.07:55:31.54#ibcon#first serial, iclass 37, count 0 2006.182.07:55:31.54#ibcon#enter sib2, iclass 37, count 0 2006.182.07:55:31.54#ibcon#flushed, iclass 37, count 0 2006.182.07:55:31.54#ibcon#about to write, iclass 37, count 0 2006.182.07:55:31.54#ibcon#wrote, iclass 37, count 0 2006.182.07:55:31.54#ibcon#about to read 3, iclass 37, count 0 2006.182.07:55:31.55#ibcon#read 3, iclass 37, count 0 2006.182.07:55:31.55#ibcon#about to read 4, iclass 37, count 0 2006.182.07:55:31.55#ibcon#read 4, iclass 37, count 0 2006.182.07:55:31.56#ibcon#about to read 5, iclass 37, count 0 2006.182.07:55:31.56#ibcon#read 5, iclass 37, count 0 2006.182.07:55:31.56#ibcon#about to read 6, iclass 37, count 0 2006.182.07:55:31.56#ibcon#read 6, iclass 37, count 0 2006.182.07:55:31.56#ibcon#end of sib2, iclass 37, count 0 2006.182.07:55:31.56#ibcon#*mode == 0, iclass 37, count 0 2006.182.07:55:31.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.07:55:31.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:55:31.56#ibcon#*before write, iclass 37, count 0 2006.182.07:55:31.56#ibcon#enter sib2, iclass 37, count 0 2006.182.07:55:31.56#ibcon#flushed, iclass 37, count 0 2006.182.07:55:31.56#ibcon#about to write, iclass 37, count 0 2006.182.07:55:31.56#ibcon#wrote, iclass 37, count 0 2006.182.07:55:31.56#ibcon#about to read 3, iclass 37, count 0 2006.182.07:55:31.59#ibcon#read 3, iclass 37, count 0 2006.182.07:55:31.59#ibcon#about to read 4, iclass 37, count 0 2006.182.07:55:31.59#ibcon#read 4, iclass 37, count 0 2006.182.07:55:31.60#ibcon#about to read 5, iclass 37, count 0 2006.182.07:55:31.60#ibcon#read 5, iclass 37, count 0 2006.182.07:55:31.60#ibcon#about to read 6, iclass 37, count 0 2006.182.07:55:31.60#ibcon#read 6, iclass 37, count 0 2006.182.07:55:31.60#ibcon#end of sib2, iclass 37, count 0 2006.182.07:55:31.60#ibcon#*after write, iclass 37, count 0 2006.182.07:55:31.60#ibcon#*before return 0, iclass 37, count 0 2006.182.07:55:31.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:31.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.182.07:55:31.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.07:55:31.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.07:55:31.60$vc4f8/vb=4,4 2006.182.07:55:31.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.07:55:31.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.07:55:31.60#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:31.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:31.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:31.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:31.65#ibcon#enter wrdev, iclass 39, count 2 2006.182.07:55:31.65#ibcon#first serial, iclass 39, count 2 2006.182.07:55:31.65#ibcon#enter sib2, iclass 39, count 2 2006.182.07:55:31.66#ibcon#flushed, iclass 39, count 2 2006.182.07:55:31.66#ibcon#about to write, iclass 39, count 2 2006.182.07:55:31.66#ibcon#wrote, iclass 39, count 2 2006.182.07:55:31.66#ibcon#about to read 3, iclass 39, count 2 2006.182.07:55:31.67#ibcon#read 3, iclass 39, count 2 2006.182.07:55:31.67#ibcon#about to read 4, iclass 39, count 2 2006.182.07:55:31.67#ibcon#read 4, iclass 39, count 2 2006.182.07:55:31.68#ibcon#about to read 5, iclass 39, count 2 2006.182.07:55:31.68#ibcon#read 5, iclass 39, count 2 2006.182.07:55:31.68#ibcon#about to read 6, iclass 39, count 2 2006.182.07:55:31.68#ibcon#read 6, iclass 39, count 2 2006.182.07:55:31.68#ibcon#end of sib2, iclass 39, count 2 2006.182.07:55:31.68#ibcon#*mode == 0, iclass 39, count 2 2006.182.07:55:31.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.07:55:31.68#ibcon#[27=AT04-04\r\n] 2006.182.07:55:31.68#ibcon#*before write, iclass 39, count 2 2006.182.07:55:31.68#ibcon#enter sib2, iclass 39, count 2 2006.182.07:55:31.68#ibcon#flushed, iclass 39, count 2 2006.182.07:55:31.68#ibcon#about to write, iclass 39, count 2 2006.182.07:55:31.68#ibcon#wrote, iclass 39, count 2 2006.182.07:55:31.68#ibcon#about to read 3, iclass 39, count 2 2006.182.07:55:31.70#ibcon#read 3, iclass 39, count 2 2006.182.07:55:31.71#ibcon#about to read 4, iclass 39, count 2 2006.182.07:55:31.71#ibcon#read 4, iclass 39, count 2 2006.182.07:55:31.71#ibcon#about to read 5, iclass 39, count 2 2006.182.07:55:31.71#ibcon#read 5, iclass 39, count 2 2006.182.07:55:31.71#ibcon#about to read 6, iclass 39, count 2 2006.182.07:55:31.71#ibcon#read 6, iclass 39, count 2 2006.182.07:55:31.71#ibcon#end of sib2, iclass 39, count 2 2006.182.07:55:31.71#ibcon#*after write, iclass 39, count 2 2006.182.07:55:31.71#ibcon#*before return 0, iclass 39, count 2 2006.182.07:55:31.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:31.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:55:31.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.07:55:31.71#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:31.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:31.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:31.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:31.82#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:55:31.82#ibcon#first serial, iclass 39, count 0 2006.182.07:55:31.82#ibcon#enter sib2, iclass 39, count 0 2006.182.07:55:31.83#ibcon#flushed, iclass 39, count 0 2006.182.07:55:31.83#ibcon#about to write, iclass 39, count 0 2006.182.07:55:31.83#ibcon#wrote, iclass 39, count 0 2006.182.07:55:31.83#ibcon#about to read 3, iclass 39, count 0 2006.182.07:55:31.84#ibcon#read 3, iclass 39, count 0 2006.182.07:55:31.84#ibcon#about to read 4, iclass 39, count 0 2006.182.07:55:31.84#ibcon#read 4, iclass 39, count 0 2006.182.07:55:31.85#ibcon#about to read 5, iclass 39, count 0 2006.182.07:55:31.85#ibcon#read 5, iclass 39, count 0 2006.182.07:55:31.85#ibcon#about to read 6, iclass 39, count 0 2006.182.07:55:31.85#ibcon#read 6, iclass 39, count 0 2006.182.07:55:31.85#ibcon#end of sib2, iclass 39, count 0 2006.182.07:55:31.85#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:55:31.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:55:31.85#ibcon#[27=USB\r\n] 2006.182.07:55:31.85#ibcon#*before write, iclass 39, count 0 2006.182.07:55:31.85#ibcon#enter sib2, iclass 39, count 0 2006.182.07:55:31.85#ibcon#flushed, iclass 39, count 0 2006.182.07:55:31.85#ibcon#about to write, iclass 39, count 0 2006.182.07:55:31.85#ibcon#wrote, iclass 39, count 0 2006.182.07:55:31.85#ibcon#about to read 3, iclass 39, count 0 2006.182.07:55:31.87#ibcon#read 3, iclass 39, count 0 2006.182.07:55:31.87#ibcon#about to read 4, iclass 39, count 0 2006.182.07:55:31.87#ibcon#read 4, iclass 39, count 0 2006.182.07:55:31.88#ibcon#about to read 5, iclass 39, count 0 2006.182.07:55:31.88#ibcon#read 5, iclass 39, count 0 2006.182.07:55:31.88#ibcon#about to read 6, iclass 39, count 0 2006.182.07:55:31.88#ibcon#read 6, iclass 39, count 0 2006.182.07:55:31.88#ibcon#end of sib2, iclass 39, count 0 2006.182.07:55:31.88#ibcon#*after write, iclass 39, count 0 2006.182.07:55:31.88#ibcon#*before return 0, iclass 39, count 0 2006.182.07:55:31.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:31.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:55:31.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:55:31.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:55:31.88$vc4f8/vblo=5,744.99 2006.182.07:55:31.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.07:55:31.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.07:55:31.88#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:31.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:31.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:31.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:31.88#ibcon#enter wrdev, iclass 3, count 0 2006.182.07:55:31.88#ibcon#first serial, iclass 3, count 0 2006.182.07:55:31.88#ibcon#enter sib2, iclass 3, count 0 2006.182.07:55:31.88#ibcon#flushed, iclass 3, count 0 2006.182.07:55:31.88#ibcon#about to write, iclass 3, count 0 2006.182.07:55:31.88#ibcon#wrote, iclass 3, count 0 2006.182.07:55:31.88#ibcon#about to read 3, iclass 3, count 0 2006.182.07:55:31.89#ibcon#read 3, iclass 3, count 0 2006.182.07:55:31.89#ibcon#about to read 4, iclass 3, count 0 2006.182.07:55:31.89#ibcon#read 4, iclass 3, count 0 2006.182.07:55:31.90#ibcon#about to read 5, iclass 3, count 0 2006.182.07:55:31.90#ibcon#read 5, iclass 3, count 0 2006.182.07:55:31.90#ibcon#about to read 6, iclass 3, count 0 2006.182.07:55:31.90#ibcon#read 6, iclass 3, count 0 2006.182.07:55:31.90#ibcon#end of sib2, iclass 3, count 0 2006.182.07:55:31.90#ibcon#*mode == 0, iclass 3, count 0 2006.182.07:55:31.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.07:55:31.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:55:31.90#ibcon#*before write, iclass 3, count 0 2006.182.07:55:31.90#ibcon#enter sib2, iclass 3, count 0 2006.182.07:55:31.90#ibcon#flushed, iclass 3, count 0 2006.182.07:55:31.90#ibcon#about to write, iclass 3, count 0 2006.182.07:55:31.90#ibcon#wrote, iclass 3, count 0 2006.182.07:55:31.90#ibcon#about to read 3, iclass 3, count 0 2006.182.07:55:31.93#ibcon#read 3, iclass 3, count 0 2006.182.07:55:31.93#ibcon#about to read 4, iclass 3, count 0 2006.182.07:55:31.93#ibcon#read 4, iclass 3, count 0 2006.182.07:55:31.94#ibcon#about to read 5, iclass 3, count 0 2006.182.07:55:31.94#ibcon#read 5, iclass 3, count 0 2006.182.07:55:31.94#ibcon#about to read 6, iclass 3, count 0 2006.182.07:55:31.94#ibcon#read 6, iclass 3, count 0 2006.182.07:55:31.94#ibcon#end of sib2, iclass 3, count 0 2006.182.07:55:31.94#ibcon#*after write, iclass 3, count 0 2006.182.07:55:31.94#ibcon#*before return 0, iclass 3, count 0 2006.182.07:55:31.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:31.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.07:55:31.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.07:55:31.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.07:55:31.94$vc4f8/vb=5,4 2006.182.07:55:31.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.07:55:31.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.07:55:31.94#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:31.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:31.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:31.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:31.99#ibcon#enter wrdev, iclass 5, count 2 2006.182.07:55:31.99#ibcon#first serial, iclass 5, count 2 2006.182.07:55:31.99#ibcon#enter sib2, iclass 5, count 2 2006.182.07:55:32.00#ibcon#flushed, iclass 5, count 2 2006.182.07:55:32.00#ibcon#about to write, iclass 5, count 2 2006.182.07:55:32.00#ibcon#wrote, iclass 5, count 2 2006.182.07:55:32.00#ibcon#about to read 3, iclass 5, count 2 2006.182.07:55:32.01#ibcon#read 3, iclass 5, count 2 2006.182.07:55:32.01#ibcon#about to read 4, iclass 5, count 2 2006.182.07:55:32.01#ibcon#read 4, iclass 5, count 2 2006.182.07:55:32.01#ibcon#about to read 5, iclass 5, count 2 2006.182.07:55:32.02#ibcon#read 5, iclass 5, count 2 2006.182.07:55:32.02#ibcon#about to read 6, iclass 5, count 2 2006.182.07:55:32.02#ibcon#read 6, iclass 5, count 2 2006.182.07:55:32.02#ibcon#end of sib2, iclass 5, count 2 2006.182.07:55:32.02#ibcon#*mode == 0, iclass 5, count 2 2006.182.07:55:32.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.07:55:32.02#ibcon#[27=AT05-04\r\n] 2006.182.07:55:32.02#ibcon#*before write, iclass 5, count 2 2006.182.07:55:32.02#ibcon#enter sib2, iclass 5, count 2 2006.182.07:55:32.02#ibcon#flushed, iclass 5, count 2 2006.182.07:55:32.02#ibcon#about to write, iclass 5, count 2 2006.182.07:55:32.02#ibcon#wrote, iclass 5, count 2 2006.182.07:55:32.02#ibcon#about to read 3, iclass 5, count 2 2006.182.07:55:32.04#ibcon#read 3, iclass 5, count 2 2006.182.07:55:32.05#ibcon#about to read 4, iclass 5, count 2 2006.182.07:55:32.05#ibcon#read 4, iclass 5, count 2 2006.182.07:55:32.05#ibcon#about to read 5, iclass 5, count 2 2006.182.07:55:32.05#ibcon#read 5, iclass 5, count 2 2006.182.07:55:32.05#ibcon#about to read 6, iclass 5, count 2 2006.182.07:55:32.05#ibcon#read 6, iclass 5, count 2 2006.182.07:55:32.05#ibcon#end of sib2, iclass 5, count 2 2006.182.07:55:32.05#ibcon#*after write, iclass 5, count 2 2006.182.07:55:32.05#ibcon#*before return 0, iclass 5, count 2 2006.182.07:55:32.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:32.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.07:55:32.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.07:55:32.05#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:32.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:32.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:32.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:32.16#ibcon#enter wrdev, iclass 5, count 0 2006.182.07:55:32.16#ibcon#first serial, iclass 5, count 0 2006.182.07:55:32.16#ibcon#enter sib2, iclass 5, count 0 2006.182.07:55:32.16#ibcon#flushed, iclass 5, count 0 2006.182.07:55:32.17#ibcon#about to write, iclass 5, count 0 2006.182.07:55:32.17#ibcon#wrote, iclass 5, count 0 2006.182.07:55:32.17#ibcon#about to read 3, iclass 5, count 0 2006.182.07:55:32.20#ibcon#read 3, iclass 5, count 0 2006.182.07:55:32.20#ibcon#about to read 4, iclass 5, count 0 2006.182.07:55:32.20#ibcon#read 4, iclass 5, count 0 2006.182.07:55:32.20#ibcon#about to read 5, iclass 5, count 0 2006.182.07:55:32.20#ibcon#read 5, iclass 5, count 0 2006.182.07:55:32.20#ibcon#about to read 6, iclass 5, count 0 2006.182.07:55:32.20#ibcon#read 6, iclass 5, count 0 2006.182.07:55:32.20#ibcon#end of sib2, iclass 5, count 0 2006.182.07:55:32.20#ibcon#*mode == 0, iclass 5, count 0 2006.182.07:55:32.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.07:55:32.20#ibcon#[27=USB\r\n] 2006.182.07:55:32.20#ibcon#*before write, iclass 5, count 0 2006.182.07:55:32.20#ibcon#enter sib2, iclass 5, count 0 2006.182.07:55:32.20#ibcon#flushed, iclass 5, count 0 2006.182.07:55:32.20#ibcon#about to write, iclass 5, count 0 2006.182.07:55:32.20#ibcon#wrote, iclass 5, count 0 2006.182.07:55:32.20#ibcon#about to read 3, iclass 5, count 0 2006.182.07:55:32.22#ibcon#read 3, iclass 5, count 0 2006.182.07:55:32.22#ibcon#about to read 4, iclass 5, count 0 2006.182.07:55:32.22#ibcon#read 4, iclass 5, count 0 2006.182.07:55:32.23#ibcon#about to read 5, iclass 5, count 0 2006.182.07:55:32.23#ibcon#read 5, iclass 5, count 0 2006.182.07:55:32.23#ibcon#about to read 6, iclass 5, count 0 2006.182.07:55:32.23#ibcon#read 6, iclass 5, count 0 2006.182.07:55:32.23#ibcon#end of sib2, iclass 5, count 0 2006.182.07:55:32.23#ibcon#*after write, iclass 5, count 0 2006.182.07:55:32.23#ibcon#*before return 0, iclass 5, count 0 2006.182.07:55:32.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:32.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.07:55:32.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.07:55:32.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.07:55:32.23$vc4f8/vblo=6,752.99 2006.182.07:55:32.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.07:55:32.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.07:55:32.23#ibcon#ireg 17 cls_cnt 0 2006.182.07:55:32.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:32.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:32.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:32.23#ibcon#enter wrdev, iclass 7, count 0 2006.182.07:55:32.23#ibcon#first serial, iclass 7, count 0 2006.182.07:55:32.23#ibcon#enter sib2, iclass 7, count 0 2006.182.07:55:32.23#ibcon#flushed, iclass 7, count 0 2006.182.07:55:32.23#ibcon#about to write, iclass 7, count 0 2006.182.07:55:32.23#ibcon#wrote, iclass 7, count 0 2006.182.07:55:32.23#ibcon#about to read 3, iclass 7, count 0 2006.182.07:55:32.24#ibcon#read 3, iclass 7, count 0 2006.182.07:55:32.24#ibcon#about to read 4, iclass 7, count 0 2006.182.07:55:32.25#ibcon#read 4, iclass 7, count 0 2006.182.07:55:32.25#ibcon#about to read 5, iclass 7, count 0 2006.182.07:55:32.25#ibcon#read 5, iclass 7, count 0 2006.182.07:55:32.25#ibcon#about to read 6, iclass 7, count 0 2006.182.07:55:32.25#ibcon#read 6, iclass 7, count 0 2006.182.07:55:32.25#ibcon#end of sib2, iclass 7, count 0 2006.182.07:55:32.25#ibcon#*mode == 0, iclass 7, count 0 2006.182.07:55:32.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.07:55:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:55:32.25#ibcon#*before write, iclass 7, count 0 2006.182.07:55:32.25#ibcon#enter sib2, iclass 7, count 0 2006.182.07:55:32.25#ibcon#flushed, iclass 7, count 0 2006.182.07:55:32.25#ibcon#about to write, iclass 7, count 0 2006.182.07:55:32.25#ibcon#wrote, iclass 7, count 0 2006.182.07:55:32.25#ibcon#about to read 3, iclass 7, count 0 2006.182.07:55:32.28#ibcon#read 3, iclass 7, count 0 2006.182.07:55:32.28#ibcon#about to read 4, iclass 7, count 0 2006.182.07:55:32.28#ibcon#read 4, iclass 7, count 0 2006.182.07:55:32.29#ibcon#about to read 5, iclass 7, count 0 2006.182.07:55:32.29#ibcon#read 5, iclass 7, count 0 2006.182.07:55:32.29#ibcon#about to read 6, iclass 7, count 0 2006.182.07:55:32.29#ibcon#read 6, iclass 7, count 0 2006.182.07:55:32.29#ibcon#end of sib2, iclass 7, count 0 2006.182.07:55:32.29#ibcon#*after write, iclass 7, count 0 2006.182.07:55:32.29#ibcon#*before return 0, iclass 7, count 0 2006.182.07:55:32.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:32.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.07:55:32.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.07:55:32.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.07:55:32.29$vc4f8/vb=6,4 2006.182.07:55:32.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.07:55:32.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.07:55:32.29#ibcon#ireg 11 cls_cnt 2 2006.182.07:55:32.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:32.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:32.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:32.34#ibcon#enter wrdev, iclass 11, count 2 2006.182.07:55:32.34#ibcon#first serial, iclass 11, count 2 2006.182.07:55:32.34#ibcon#enter sib2, iclass 11, count 2 2006.182.07:55:32.35#ibcon#flushed, iclass 11, count 2 2006.182.07:55:32.35#ibcon#about to write, iclass 11, count 2 2006.182.07:55:32.35#ibcon#wrote, iclass 11, count 2 2006.182.07:55:32.35#ibcon#about to read 3, iclass 11, count 2 2006.182.07:55:32.36#ibcon#read 3, iclass 11, count 2 2006.182.07:55:32.36#ibcon#about to read 4, iclass 11, count 2 2006.182.07:55:32.36#ibcon#read 4, iclass 11, count 2 2006.182.07:55:32.37#ibcon#about to read 5, iclass 11, count 2 2006.182.07:55:32.37#ibcon#read 5, iclass 11, count 2 2006.182.07:55:32.37#ibcon#about to read 6, iclass 11, count 2 2006.182.07:55:32.37#ibcon#read 6, iclass 11, count 2 2006.182.07:55:32.37#ibcon#end of sib2, iclass 11, count 2 2006.182.07:55:32.37#ibcon#*mode == 0, iclass 11, count 2 2006.182.07:55:32.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.07:55:32.37#ibcon#[27=AT06-04\r\n] 2006.182.07:55:32.37#ibcon#*before write, iclass 11, count 2 2006.182.07:55:32.37#ibcon#enter sib2, iclass 11, count 2 2006.182.07:55:32.37#ibcon#flushed, iclass 11, count 2 2006.182.07:55:32.37#ibcon#about to write, iclass 11, count 2 2006.182.07:55:32.37#ibcon#wrote, iclass 11, count 2 2006.182.07:55:32.37#ibcon#about to read 3, iclass 11, count 2 2006.182.07:55:32.39#ibcon#read 3, iclass 11, count 2 2006.182.07:55:32.39#ibcon#about to read 4, iclass 11, count 2 2006.182.07:55:32.39#ibcon#read 4, iclass 11, count 2 2006.182.07:55:32.39#ibcon#about to read 5, iclass 11, count 2 2006.182.07:55:32.40#ibcon#read 5, iclass 11, count 2 2006.182.07:55:32.40#ibcon#about to read 6, iclass 11, count 2 2006.182.07:55:32.40#ibcon#read 6, iclass 11, count 2 2006.182.07:55:32.40#ibcon#end of sib2, iclass 11, count 2 2006.182.07:55:32.40#ibcon#*after write, iclass 11, count 2 2006.182.07:55:32.40#ibcon#*before return 0, iclass 11, count 2 2006.182.07:55:32.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:32.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.07:55:32.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.07:55:32.40#ibcon#ireg 7 cls_cnt 0 2006.182.07:55:32.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:32.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:32.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:32.51#ibcon#enter wrdev, iclass 11, count 0 2006.182.07:55:32.51#ibcon#first serial, iclass 11, count 0 2006.182.07:55:32.51#ibcon#enter sib2, iclass 11, count 0 2006.182.07:55:32.52#ibcon#flushed, iclass 11, count 0 2006.182.07:55:32.52#ibcon#about to write, iclass 11, count 0 2006.182.07:55:32.52#ibcon#wrote, iclass 11, count 0 2006.182.07:55:32.52#ibcon#about to read 3, iclass 11, count 0 2006.182.07:55:32.53#ibcon#read 3, iclass 11, count 0 2006.182.07:55:32.53#ibcon#about to read 4, iclass 11, count 0 2006.182.07:55:32.53#ibcon#read 4, iclass 11, count 0 2006.182.07:55:32.54#ibcon#about to read 5, iclass 11, count 0 2006.182.07:55:32.54#ibcon#read 5, iclass 11, count 0 2006.182.07:55:32.54#ibcon#about to read 6, iclass 11, count 0 2006.182.07:55:32.54#ibcon#read 6, iclass 11, count 0 2006.182.07:55:32.54#ibcon#end of sib2, iclass 11, count 0 2006.182.07:55:32.54#ibcon#*mode == 0, iclass 11, count 0 2006.182.07:55:32.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.07:55:32.54#ibcon#[27=USB\r\n] 2006.182.07:55:32.54#ibcon#*before write, iclass 11, count 0 2006.182.07:55:32.54#ibcon#enter sib2, iclass 11, count 0 2006.182.07:55:32.54#ibcon#flushed, iclass 11, count 0 2006.182.07:55:32.54#ibcon#about to write, iclass 11, count 0 2006.182.07:55:32.54#ibcon#wrote, iclass 11, count 0 2006.182.07:55:32.54#ibcon#about to read 3, iclass 11, count 0 2006.182.07:55:32.56#ibcon#read 3, iclass 11, count 0 2006.182.07:55:32.56#ibcon#about to read 4, iclass 11, count 0 2006.182.07:55:32.56#ibcon#read 4, iclass 11, count 0 2006.182.07:55:32.57#ibcon#about to read 5, iclass 11, count 0 2006.182.07:55:32.57#ibcon#read 5, iclass 11, count 0 2006.182.07:55:32.57#ibcon#about to read 6, iclass 11, count 0 2006.182.07:55:32.57#ibcon#read 6, iclass 11, count 0 2006.182.07:55:32.57#ibcon#end of sib2, iclass 11, count 0 2006.182.07:55:32.57#ibcon#*after write, iclass 11, count 0 2006.182.07:55:32.57#ibcon#*before return 0, iclass 11, count 0 2006.182.07:55:32.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:32.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.07:55:32.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.07:55:32.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.07:55:32.57$vc4f8/vabw=wide 2006.182.07:55:32.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.07:55:32.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.07:55:32.57#ibcon#ireg 8 cls_cnt 0 2006.182.07:55:32.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:32.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:32.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:32.57#ibcon#enter wrdev, iclass 13, count 0 2006.182.07:55:32.57#ibcon#first serial, iclass 13, count 0 2006.182.07:55:32.57#ibcon#enter sib2, iclass 13, count 0 2006.182.07:55:32.57#ibcon#flushed, iclass 13, count 0 2006.182.07:55:32.57#ibcon#about to write, iclass 13, count 0 2006.182.07:55:32.57#ibcon#wrote, iclass 13, count 0 2006.182.07:55:32.57#ibcon#about to read 3, iclass 13, count 0 2006.182.07:55:32.58#ibcon#read 3, iclass 13, count 0 2006.182.07:55:32.58#ibcon#about to read 4, iclass 13, count 0 2006.182.07:55:32.58#ibcon#read 4, iclass 13, count 0 2006.182.07:55:32.59#ibcon#about to read 5, iclass 13, count 0 2006.182.07:55:32.59#ibcon#read 5, iclass 13, count 0 2006.182.07:55:32.59#ibcon#about to read 6, iclass 13, count 0 2006.182.07:55:32.59#ibcon#read 6, iclass 13, count 0 2006.182.07:55:32.59#ibcon#end of sib2, iclass 13, count 0 2006.182.07:55:32.59#ibcon#*mode == 0, iclass 13, count 0 2006.182.07:55:32.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.07:55:32.59#ibcon#[25=BW32\r\n] 2006.182.07:55:32.59#ibcon#*before write, iclass 13, count 0 2006.182.07:55:32.59#ibcon#enter sib2, iclass 13, count 0 2006.182.07:55:32.59#ibcon#flushed, iclass 13, count 0 2006.182.07:55:32.59#ibcon#about to write, iclass 13, count 0 2006.182.07:55:32.59#ibcon#wrote, iclass 13, count 0 2006.182.07:55:32.59#ibcon#about to read 3, iclass 13, count 0 2006.182.07:55:32.61#ibcon#read 3, iclass 13, count 0 2006.182.07:55:32.61#ibcon#about to read 4, iclass 13, count 0 2006.182.07:55:32.61#ibcon#read 4, iclass 13, count 0 2006.182.07:55:32.61#ibcon#about to read 5, iclass 13, count 0 2006.182.07:55:32.62#ibcon#read 5, iclass 13, count 0 2006.182.07:55:32.62#ibcon#about to read 6, iclass 13, count 0 2006.182.07:55:32.62#ibcon#read 6, iclass 13, count 0 2006.182.07:55:32.62#ibcon#end of sib2, iclass 13, count 0 2006.182.07:55:32.62#ibcon#*after write, iclass 13, count 0 2006.182.07:55:32.62#ibcon#*before return 0, iclass 13, count 0 2006.182.07:55:32.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:32.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.07:55:32.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.07:55:32.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.07:55:32.62$vc4f8/vbbw=wide 2006.182.07:55:32.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.07:55:32.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.07:55:32.62#ibcon#ireg 8 cls_cnt 0 2006.182.07:55:32.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:55:32.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:55:32.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:55:32.68#ibcon#enter wrdev, iclass 15, count 0 2006.182.07:55:32.68#ibcon#first serial, iclass 15, count 0 2006.182.07:55:32.68#ibcon#enter sib2, iclass 15, count 0 2006.182.07:55:32.69#ibcon#flushed, iclass 15, count 0 2006.182.07:55:32.69#ibcon#about to write, iclass 15, count 0 2006.182.07:55:32.69#ibcon#wrote, iclass 15, count 0 2006.182.07:55:32.69#ibcon#about to read 3, iclass 15, count 0 2006.182.07:55:32.70#ibcon#read 3, iclass 15, count 0 2006.182.07:55:32.70#ibcon#about to read 4, iclass 15, count 0 2006.182.07:55:32.71#ibcon#read 4, iclass 15, count 0 2006.182.07:55:32.71#ibcon#about to read 5, iclass 15, count 0 2006.182.07:55:32.71#ibcon#read 5, iclass 15, count 0 2006.182.07:55:32.71#ibcon#about to read 6, iclass 15, count 0 2006.182.07:55:32.71#ibcon#read 6, iclass 15, count 0 2006.182.07:55:32.71#ibcon#end of sib2, iclass 15, count 0 2006.182.07:55:32.71#ibcon#*mode == 0, iclass 15, count 0 2006.182.07:55:32.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.07:55:32.71#ibcon#[27=BW32\r\n] 2006.182.07:55:32.71#ibcon#*before write, iclass 15, count 0 2006.182.07:55:32.71#ibcon#enter sib2, iclass 15, count 0 2006.182.07:55:32.71#ibcon#flushed, iclass 15, count 0 2006.182.07:55:32.71#ibcon#about to write, iclass 15, count 0 2006.182.07:55:32.71#ibcon#wrote, iclass 15, count 0 2006.182.07:55:32.71#ibcon#about to read 3, iclass 15, count 0 2006.182.07:55:32.73#ibcon#read 3, iclass 15, count 0 2006.182.07:55:32.74#ibcon#about to read 4, iclass 15, count 0 2006.182.07:55:32.74#ibcon#read 4, iclass 15, count 0 2006.182.07:55:32.74#ibcon#about to read 5, iclass 15, count 0 2006.182.07:55:32.74#ibcon#read 5, iclass 15, count 0 2006.182.07:55:32.74#ibcon#about to read 6, iclass 15, count 0 2006.182.07:55:32.74#ibcon#read 6, iclass 15, count 0 2006.182.07:55:32.74#ibcon#end of sib2, iclass 15, count 0 2006.182.07:55:32.74#ibcon#*after write, iclass 15, count 0 2006.182.07:55:32.74#ibcon#*before return 0, iclass 15, count 0 2006.182.07:55:32.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:55:32.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.07:55:32.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.07:55:32.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.07:55:32.74$4f8m12a/ifd4f 2006.182.07:55:32.74$ifd4f/lo= 2006.182.07:55:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:55:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:55:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:55:32.74$ifd4f/patch= 2006.182.07:55:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:55:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:55:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:55:32.74$4f8m12a/"form=m,16.000,1:2 2006.182.07:55:32.74$4f8m12a/"tpicd 2006.182.07:55:32.74$4f8m12a/echo=off 2006.182.07:55:32.74$4f8m12a/xlog=off 2006.182.07:55:32.74:!2006.182.07:57:40 2006.182.07:55:44.13#trakl#Source acquired 2006.182.07:55:45.14#flagr#flagr/antenna,acquired 2006.182.07:57:40.02:preob 2006.182.07:57:41.15/onsource/TRACKING 2006.182.07:57:41.15:!2006.182.07:57:50 2006.182.07:57:50.02:data_valid=on 2006.182.07:57:50.02:midob 2006.182.07:57:51.15/onsource/TRACKING 2006.182.07:57:51.15/wx/27.72,1002.8,81 2006.182.07:57:51.20/cable/+6.4669E-03 2006.182.07:57:52.29/va/01,08,usb,yes,29,31 2006.182.07:57:52.29/va/02,07,usb,yes,29,31 2006.182.07:57:52.29/va/03,06,usb,yes,31,31 2006.182.07:57:52.29/va/04,07,usb,yes,30,33 2006.182.07:57:52.29/va/05,07,usb,yes,31,33 2006.182.07:57:52.29/va/06,06,usb,yes,30,30 2006.182.07:57:52.29/va/07,06,usb,yes,31,30 2006.182.07:57:52.29/va/08,07,usb,yes,29,29 2006.182.07:57:52.52/valo/01,532.99,yes,locked 2006.182.07:57:52.52/valo/02,572.99,yes,locked 2006.182.07:57:52.52/valo/03,672.99,yes,locked 2006.182.07:57:52.52/valo/04,832.99,yes,locked 2006.182.07:57:52.52/valo/05,652.99,yes,locked 2006.182.07:57:52.52/valo/06,772.99,yes,locked 2006.182.07:57:52.52/valo/07,832.99,yes,locked 2006.182.07:57:52.52/valo/08,852.99,yes,locked 2006.182.07:57:53.61/vb/01,04,usb,yes,29,28 2006.182.07:57:53.61/vb/02,04,usb,yes,31,32 2006.182.07:57:53.61/vb/03,04,usb,yes,27,31 2006.182.07:57:53.61/vb/04,04,usb,yes,28,28 2006.182.07:57:53.61/vb/05,04,usb,yes,27,31 2006.182.07:57:53.61/vb/06,04,usb,yes,28,31 2006.182.07:57:53.61/vb/07,04,usb,yes,30,30 2006.182.07:57:53.61/vb/08,04,usb,yes,27,31 2006.182.07:57:53.84/vblo/01,632.99,yes,locked 2006.182.07:57:53.84/vblo/02,640.99,yes,locked 2006.182.07:57:53.84/vblo/03,656.99,yes,locked 2006.182.07:57:53.84/vblo/04,712.99,yes,locked 2006.182.07:57:53.84/vblo/05,744.99,yes,locked 2006.182.07:57:53.84/vblo/06,752.99,yes,locked 2006.182.07:57:53.84/vblo/07,734.99,yes,locked 2006.182.07:57:53.84/vblo/08,744.99,yes,locked 2006.182.07:57:53.99/vabw/8 2006.182.07:57:54.14/vbbw/8 2006.182.07:57:54.25/xfe/off,on,14.5 2006.182.07:57:54.65/ifatt/23,28,28,28 2006.182.07:57:55.07/fmout-gps/S +3.39E-07 2006.182.07:57:55.12:!2006.182.07:58:50 2006.182.07:58:50.01:data_valid=off 2006.182.07:58:50.02:postob 2006.182.07:58:50.10/cable/+6.4652E-03 2006.182.07:58:50.10/wx/27.74,1002.8,81 2006.182.07:58:51.07/fmout-gps/S +3.40E-07 2006.182.07:58:51.08:scan_name=182-0800,k06182,60 2006.182.07:58:51.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.182.07:58:52.14#flagr#flagr/antenna,new-source 2006.182.07:58:52.15:checkk5 2006.182.07:58:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.182.07:58:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.182.07:58:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.182.07:58:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.182.07:58:54.03/chk_obsdata//k5ts1/T1820757??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:58:54.39/chk_obsdata//k5ts2/T1820757??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:58:54.76/chk_obsdata//k5ts3/T1820757??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:58:55.13/chk_obsdata//k5ts4/T1820757??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.07:58:55.82/k5log//k5ts1_log_newline 2006.182.07:58:56.52/k5log//k5ts2_log_newline 2006.182.07:58:57.21/k5log//k5ts3_log_newline 2006.182.07:58:57.90/k5log//k5ts4_log_newline 2006.182.07:58:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.07:58:57.92:4f8m12a=2 2006.182.07:58:57.92$4f8m12a/echo=on 2006.182.07:58:57.92$4f8m12a/pcalon 2006.182.07:58:57.92$pcalon/"no phase cal control is implemented here 2006.182.07:58:57.92$4f8m12a/"tpicd=stop 2006.182.07:58:57.92$4f8m12a/vc4f8 2006.182.07:58:57.92$vc4f8/valo=1,532.99 2006.182.07:58:57.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.07:58:57.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.07:58:57.93#ibcon#ireg 17 cls_cnt 0 2006.182.07:58:57.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:58:57.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:58:57.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:58:57.93#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:58:57.93#ibcon#first serial, iclass 26, count 0 2006.182.07:58:57.93#ibcon#enter sib2, iclass 26, count 0 2006.182.07:58:57.93#ibcon#flushed, iclass 26, count 0 2006.182.07:58:57.93#ibcon#about to write, iclass 26, count 0 2006.182.07:58:57.93#ibcon#wrote, iclass 26, count 0 2006.182.07:58:57.93#ibcon#about to read 3, iclass 26, count 0 2006.182.07:58:57.97#ibcon#read 3, iclass 26, count 0 2006.182.07:58:57.97#ibcon#about to read 4, iclass 26, count 0 2006.182.07:58:57.97#ibcon#read 4, iclass 26, count 0 2006.182.07:58:57.97#ibcon#about to read 5, iclass 26, count 0 2006.182.07:58:57.97#ibcon#read 5, iclass 26, count 0 2006.182.07:58:57.97#ibcon#about to read 6, iclass 26, count 0 2006.182.07:58:57.97#ibcon#read 6, iclass 26, count 0 2006.182.07:58:57.97#ibcon#end of sib2, iclass 26, count 0 2006.182.07:58:57.97#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:58:57.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:58:57.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.07:58:57.97#ibcon#*before write, iclass 26, count 0 2006.182.07:58:57.97#ibcon#enter sib2, iclass 26, count 0 2006.182.07:58:57.97#ibcon#flushed, iclass 26, count 0 2006.182.07:58:57.97#ibcon#about to write, iclass 26, count 0 2006.182.07:58:57.97#ibcon#wrote, iclass 26, count 0 2006.182.07:58:57.97#ibcon#about to read 3, iclass 26, count 0 2006.182.07:58:58.01#ibcon#read 3, iclass 26, count 0 2006.182.07:58:58.01#ibcon#about to read 4, iclass 26, count 0 2006.182.07:58:58.01#ibcon#read 4, iclass 26, count 0 2006.182.07:58:58.01#ibcon#about to read 5, iclass 26, count 0 2006.182.07:58:58.01#ibcon#read 5, iclass 26, count 0 2006.182.07:58:58.01#ibcon#about to read 6, iclass 26, count 0 2006.182.07:58:58.01#ibcon#read 6, iclass 26, count 0 2006.182.07:58:58.01#ibcon#end of sib2, iclass 26, count 0 2006.182.07:58:58.01#ibcon#*after write, iclass 26, count 0 2006.182.07:58:58.01#ibcon#*before return 0, iclass 26, count 0 2006.182.07:58:58.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:58:58.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:58:58.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:58:58.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:58:58.01$vc4f8/va=1,8 2006.182.07:58:58.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.07:58:58.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.07:58:58.01#ibcon#ireg 11 cls_cnt 2 2006.182.07:58:58.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:58:58.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:58:58.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:58:58.01#ibcon#enter wrdev, iclass 28, count 2 2006.182.07:58:58.01#ibcon#first serial, iclass 28, count 2 2006.182.07:58:58.01#ibcon#enter sib2, iclass 28, count 2 2006.182.07:58:58.01#ibcon#flushed, iclass 28, count 2 2006.182.07:58:58.01#ibcon#about to write, iclass 28, count 2 2006.182.07:58:58.01#ibcon#wrote, iclass 28, count 2 2006.182.07:58:58.01#ibcon#about to read 3, iclass 28, count 2 2006.182.07:58:58.04#ibcon#read 3, iclass 28, count 2 2006.182.07:58:58.04#ibcon#about to read 4, iclass 28, count 2 2006.182.07:58:58.04#ibcon#read 4, iclass 28, count 2 2006.182.07:58:58.04#ibcon#about to read 5, iclass 28, count 2 2006.182.07:58:58.04#ibcon#read 5, iclass 28, count 2 2006.182.07:58:58.04#ibcon#about to read 6, iclass 28, count 2 2006.182.07:58:58.04#ibcon#read 6, iclass 28, count 2 2006.182.07:58:58.04#ibcon#end of sib2, iclass 28, count 2 2006.182.07:58:58.04#ibcon#*mode == 0, iclass 28, count 2 2006.182.07:58:58.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.07:58:58.04#ibcon#[25=AT01-08\r\n] 2006.182.07:58:58.04#ibcon#*before write, iclass 28, count 2 2006.182.07:58:58.04#ibcon#enter sib2, iclass 28, count 2 2006.182.07:58:58.04#ibcon#flushed, iclass 28, count 2 2006.182.07:58:58.04#ibcon#about to write, iclass 28, count 2 2006.182.07:58:58.04#ibcon#wrote, iclass 28, count 2 2006.182.07:58:58.04#ibcon#about to read 3, iclass 28, count 2 2006.182.07:58:58.07#ibcon#read 3, iclass 28, count 2 2006.182.07:58:58.07#ibcon#about to read 4, iclass 28, count 2 2006.182.07:58:58.07#ibcon#read 4, iclass 28, count 2 2006.182.07:58:58.07#ibcon#about to read 5, iclass 28, count 2 2006.182.07:58:58.07#ibcon#read 5, iclass 28, count 2 2006.182.07:58:58.07#ibcon#about to read 6, iclass 28, count 2 2006.182.07:58:58.07#ibcon#read 6, iclass 28, count 2 2006.182.07:58:58.07#ibcon#end of sib2, iclass 28, count 2 2006.182.07:58:58.07#ibcon#*after write, iclass 28, count 2 2006.182.07:58:58.07#ibcon#*before return 0, iclass 28, count 2 2006.182.07:58:58.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:58:58.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:58:58.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.07:58:58.07#ibcon#ireg 7 cls_cnt 0 2006.182.07:58:58.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:58:58.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:58:58.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:58:58.19#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:58:58.19#ibcon#first serial, iclass 28, count 0 2006.182.07:58:58.19#ibcon#enter sib2, iclass 28, count 0 2006.182.07:58:58.19#ibcon#flushed, iclass 28, count 0 2006.182.07:58:58.19#ibcon#about to write, iclass 28, count 0 2006.182.07:58:58.19#ibcon#wrote, iclass 28, count 0 2006.182.07:58:58.19#ibcon#about to read 3, iclass 28, count 0 2006.182.07:58:58.21#ibcon#read 3, iclass 28, count 0 2006.182.07:58:58.21#ibcon#about to read 4, iclass 28, count 0 2006.182.07:58:58.21#ibcon#read 4, iclass 28, count 0 2006.182.07:58:58.21#ibcon#about to read 5, iclass 28, count 0 2006.182.07:58:58.21#ibcon#read 5, iclass 28, count 0 2006.182.07:58:58.21#ibcon#about to read 6, iclass 28, count 0 2006.182.07:58:58.21#ibcon#read 6, iclass 28, count 0 2006.182.07:58:58.21#ibcon#end of sib2, iclass 28, count 0 2006.182.07:58:58.21#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:58:58.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:58:58.21#ibcon#[25=USB\r\n] 2006.182.07:58:58.21#ibcon#*before write, iclass 28, count 0 2006.182.07:58:58.21#ibcon#enter sib2, iclass 28, count 0 2006.182.07:58:58.21#ibcon#flushed, iclass 28, count 0 2006.182.07:58:58.21#ibcon#about to write, iclass 28, count 0 2006.182.07:58:58.21#ibcon#wrote, iclass 28, count 0 2006.182.07:58:58.21#ibcon#about to read 3, iclass 28, count 0 2006.182.07:58:58.24#ibcon#read 3, iclass 28, count 0 2006.182.07:58:58.24#ibcon#about to read 4, iclass 28, count 0 2006.182.07:58:58.24#ibcon#read 4, iclass 28, count 0 2006.182.07:58:58.24#ibcon#about to read 5, iclass 28, count 0 2006.182.07:58:58.24#ibcon#read 5, iclass 28, count 0 2006.182.07:58:58.24#ibcon#about to read 6, iclass 28, count 0 2006.182.07:58:58.24#ibcon#read 6, iclass 28, count 0 2006.182.07:58:58.24#ibcon#end of sib2, iclass 28, count 0 2006.182.07:58:58.24#ibcon#*after write, iclass 28, count 0 2006.182.07:58:58.24#ibcon#*before return 0, iclass 28, count 0 2006.182.07:58:58.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:58:58.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:58:58.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:58:58.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:58:58.24$vc4f8/valo=2,572.99 2006.182.07:58:58.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.07:58:58.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.07:58:58.24#ibcon#ireg 17 cls_cnt 0 2006.182.07:58:58.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:58:58.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:58:58.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:58:58.24#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:58:58.24#ibcon#first serial, iclass 30, count 0 2006.182.07:58:58.24#ibcon#enter sib2, iclass 30, count 0 2006.182.07:58:58.24#ibcon#flushed, iclass 30, count 0 2006.182.07:58:58.25#ibcon#about to write, iclass 30, count 0 2006.182.07:58:58.25#ibcon#wrote, iclass 30, count 0 2006.182.07:58:58.25#ibcon#about to read 3, iclass 30, count 0 2006.182.07:58:58.26#ibcon#read 3, iclass 30, count 0 2006.182.07:58:58.26#ibcon#about to read 4, iclass 30, count 0 2006.182.07:58:58.26#ibcon#read 4, iclass 30, count 0 2006.182.07:58:58.26#ibcon#about to read 5, iclass 30, count 0 2006.182.07:58:58.26#ibcon#read 5, iclass 30, count 0 2006.182.07:58:58.26#ibcon#about to read 6, iclass 30, count 0 2006.182.07:58:58.26#ibcon#read 6, iclass 30, count 0 2006.182.07:58:58.26#ibcon#end of sib2, iclass 30, count 0 2006.182.07:58:58.26#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:58:58.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:58:58.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.07:58:58.26#ibcon#*before write, iclass 30, count 0 2006.182.07:58:58.26#ibcon#enter sib2, iclass 30, count 0 2006.182.07:58:58.26#ibcon#flushed, iclass 30, count 0 2006.182.07:58:58.26#ibcon#about to write, iclass 30, count 0 2006.182.07:58:58.26#ibcon#wrote, iclass 30, count 0 2006.182.07:58:58.26#ibcon#about to read 3, iclass 30, count 0 2006.182.07:58:58.30#ibcon#read 3, iclass 30, count 0 2006.182.07:58:58.30#ibcon#about to read 4, iclass 30, count 0 2006.182.07:58:58.30#ibcon#read 4, iclass 30, count 0 2006.182.07:58:58.30#ibcon#about to read 5, iclass 30, count 0 2006.182.07:58:58.30#ibcon#read 5, iclass 30, count 0 2006.182.07:58:58.30#ibcon#about to read 6, iclass 30, count 0 2006.182.07:58:58.30#ibcon#read 6, iclass 30, count 0 2006.182.07:58:58.30#ibcon#end of sib2, iclass 30, count 0 2006.182.07:58:58.30#ibcon#*after write, iclass 30, count 0 2006.182.07:58:58.30#ibcon#*before return 0, iclass 30, count 0 2006.182.07:58:58.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:58:58.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:58:58.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:58:58.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:58:58.30$vc4f8/va=2,7 2006.182.07:58:58.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.07:58:58.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.07:58:58.30#ibcon#ireg 11 cls_cnt 2 2006.182.07:58:58.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:58:58.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:58:58.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:58:58.36#ibcon#enter wrdev, iclass 32, count 2 2006.182.07:58:58.36#ibcon#first serial, iclass 32, count 2 2006.182.07:58:58.36#ibcon#enter sib2, iclass 32, count 2 2006.182.07:58:58.36#ibcon#flushed, iclass 32, count 2 2006.182.07:58:58.36#ibcon#about to write, iclass 32, count 2 2006.182.07:58:58.36#ibcon#wrote, iclass 32, count 2 2006.182.07:58:58.36#ibcon#about to read 3, iclass 32, count 2 2006.182.07:58:58.38#ibcon#read 3, iclass 32, count 2 2006.182.07:58:58.38#ibcon#about to read 4, iclass 32, count 2 2006.182.07:58:58.38#ibcon#read 4, iclass 32, count 2 2006.182.07:58:58.38#ibcon#about to read 5, iclass 32, count 2 2006.182.07:58:58.38#ibcon#read 5, iclass 32, count 2 2006.182.07:58:58.38#ibcon#about to read 6, iclass 32, count 2 2006.182.07:58:58.38#ibcon#read 6, iclass 32, count 2 2006.182.07:58:58.38#ibcon#end of sib2, iclass 32, count 2 2006.182.07:58:58.38#ibcon#*mode == 0, iclass 32, count 2 2006.182.07:58:58.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.07:58:58.38#ibcon#[25=AT02-07\r\n] 2006.182.07:58:58.38#ibcon#*before write, iclass 32, count 2 2006.182.07:58:58.38#ibcon#enter sib2, iclass 32, count 2 2006.182.07:58:58.38#ibcon#flushed, iclass 32, count 2 2006.182.07:58:58.38#ibcon#about to write, iclass 32, count 2 2006.182.07:58:58.38#ibcon#wrote, iclass 32, count 2 2006.182.07:58:58.38#ibcon#about to read 3, iclass 32, count 2 2006.182.07:58:58.41#ibcon#read 3, iclass 32, count 2 2006.182.07:58:58.41#ibcon#about to read 4, iclass 32, count 2 2006.182.07:58:58.41#ibcon#read 4, iclass 32, count 2 2006.182.07:58:58.41#ibcon#about to read 5, iclass 32, count 2 2006.182.07:58:58.41#ibcon#read 5, iclass 32, count 2 2006.182.07:58:58.41#ibcon#about to read 6, iclass 32, count 2 2006.182.07:58:58.41#ibcon#read 6, iclass 32, count 2 2006.182.07:58:58.41#ibcon#end of sib2, iclass 32, count 2 2006.182.07:58:58.41#ibcon#*after write, iclass 32, count 2 2006.182.07:58:58.41#ibcon#*before return 0, iclass 32, count 2 2006.182.07:58:58.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:58:58.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:58:58.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.07:58:58.41#ibcon#ireg 7 cls_cnt 0 2006.182.07:58:58.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:58:58.54#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:58:58.54#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:58:58.54#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:58:58.54#ibcon#first serial, iclass 32, count 0 2006.182.07:58:58.54#ibcon#enter sib2, iclass 32, count 0 2006.182.07:58:58.54#ibcon#flushed, iclass 32, count 0 2006.182.07:58:58.54#ibcon#about to write, iclass 32, count 0 2006.182.07:58:58.54#ibcon#wrote, iclass 32, count 0 2006.182.07:58:58.54#ibcon#about to read 3, iclass 32, count 0 2006.182.07:58:58.55#ibcon#read 3, iclass 32, count 0 2006.182.07:58:58.55#ibcon#about to read 4, iclass 32, count 0 2006.182.07:58:58.55#ibcon#read 4, iclass 32, count 0 2006.182.07:58:58.55#ibcon#about to read 5, iclass 32, count 0 2006.182.07:58:58.55#ibcon#read 5, iclass 32, count 0 2006.182.07:58:58.55#ibcon#about to read 6, iclass 32, count 0 2006.182.07:58:58.55#ibcon#read 6, iclass 32, count 0 2006.182.07:58:58.55#ibcon#end of sib2, iclass 32, count 0 2006.182.07:58:58.55#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:58:58.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:58:58.55#ibcon#[25=USB\r\n] 2006.182.07:58:58.55#ibcon#*before write, iclass 32, count 0 2006.182.07:58:58.55#ibcon#enter sib2, iclass 32, count 0 2006.182.07:58:58.55#ibcon#flushed, iclass 32, count 0 2006.182.07:58:58.55#ibcon#about to write, iclass 32, count 0 2006.182.07:58:58.55#ibcon#wrote, iclass 32, count 0 2006.182.07:58:58.55#ibcon#about to read 3, iclass 32, count 0 2006.182.07:58:58.58#ibcon#read 3, iclass 32, count 0 2006.182.07:58:58.58#ibcon#about to read 4, iclass 32, count 0 2006.182.07:58:58.58#ibcon#read 4, iclass 32, count 0 2006.182.07:58:58.58#ibcon#about to read 5, iclass 32, count 0 2006.182.07:58:58.58#ibcon#read 5, iclass 32, count 0 2006.182.07:58:58.58#ibcon#about to read 6, iclass 32, count 0 2006.182.07:58:58.58#ibcon#read 6, iclass 32, count 0 2006.182.07:58:58.58#ibcon#end of sib2, iclass 32, count 0 2006.182.07:58:58.58#ibcon#*after write, iclass 32, count 0 2006.182.07:58:58.58#ibcon#*before return 0, iclass 32, count 0 2006.182.07:58:58.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:58:58.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:58:58.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:58:58.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:58:58.58$vc4f8/valo=3,672.99 2006.182.07:58:58.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.07:58:58.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.07:58:58.58#ibcon#ireg 17 cls_cnt 0 2006.182.07:58:58.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:58:58.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:58:58.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:58:58.58#ibcon#enter wrdev, iclass 34, count 0 2006.182.07:58:58.58#ibcon#first serial, iclass 34, count 0 2006.182.07:58:58.58#ibcon#enter sib2, iclass 34, count 0 2006.182.07:58:58.58#ibcon#flushed, iclass 34, count 0 2006.182.07:58:58.58#ibcon#about to write, iclass 34, count 0 2006.182.07:58:58.58#ibcon#wrote, iclass 34, count 0 2006.182.07:58:58.58#ibcon#about to read 3, iclass 34, count 0 2006.182.07:58:58.61#ibcon#read 3, iclass 34, count 0 2006.182.07:58:58.61#ibcon#about to read 4, iclass 34, count 0 2006.182.07:58:58.61#ibcon#read 4, iclass 34, count 0 2006.182.07:58:58.61#ibcon#about to read 5, iclass 34, count 0 2006.182.07:58:58.61#ibcon#read 5, iclass 34, count 0 2006.182.07:58:58.61#ibcon#about to read 6, iclass 34, count 0 2006.182.07:58:58.61#ibcon#read 6, iclass 34, count 0 2006.182.07:58:58.61#ibcon#end of sib2, iclass 34, count 0 2006.182.07:58:58.61#ibcon#*mode == 0, iclass 34, count 0 2006.182.07:58:58.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.07:58:58.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.07:58:58.61#ibcon#*before write, iclass 34, count 0 2006.182.07:58:58.61#ibcon#enter sib2, iclass 34, count 0 2006.182.07:58:58.61#ibcon#flushed, iclass 34, count 0 2006.182.07:58:58.61#ibcon#about to write, iclass 34, count 0 2006.182.07:58:58.61#ibcon#wrote, iclass 34, count 0 2006.182.07:58:58.61#ibcon#about to read 3, iclass 34, count 0 2006.182.07:58:58.65#ibcon#read 3, iclass 34, count 0 2006.182.07:58:58.65#ibcon#about to read 4, iclass 34, count 0 2006.182.07:58:58.65#ibcon#read 4, iclass 34, count 0 2006.182.07:58:58.65#ibcon#about to read 5, iclass 34, count 0 2006.182.07:58:58.65#ibcon#read 5, iclass 34, count 0 2006.182.07:58:58.65#ibcon#about to read 6, iclass 34, count 0 2006.182.07:58:58.65#ibcon#read 6, iclass 34, count 0 2006.182.07:58:58.65#ibcon#end of sib2, iclass 34, count 0 2006.182.07:58:58.65#ibcon#*after write, iclass 34, count 0 2006.182.07:58:58.65#ibcon#*before return 0, iclass 34, count 0 2006.182.07:58:58.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:58:58.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.07:58:58.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.07:58:58.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.07:58:58.65$vc4f8/va=3,6 2006.182.07:58:58.65#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.182.07:58:58.65#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.182.07:58:58.65#ibcon#ireg 11 cls_cnt 2 2006.182.07:58:58.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:58:58.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:58:58.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:58:58.71#ibcon#enter wrdev, iclass 36, count 2 2006.182.07:58:58.71#ibcon#first serial, iclass 36, count 2 2006.182.07:58:58.71#ibcon#enter sib2, iclass 36, count 2 2006.182.07:58:58.71#ibcon#flushed, iclass 36, count 2 2006.182.07:58:58.71#ibcon#about to write, iclass 36, count 2 2006.182.07:58:58.71#ibcon#wrote, iclass 36, count 2 2006.182.07:58:58.71#ibcon#about to read 3, iclass 36, count 2 2006.182.07:58:58.72#ibcon#read 3, iclass 36, count 2 2006.182.07:58:58.72#ibcon#about to read 4, iclass 36, count 2 2006.182.07:58:58.72#ibcon#read 4, iclass 36, count 2 2006.182.07:58:58.72#ibcon#about to read 5, iclass 36, count 2 2006.182.07:58:58.72#ibcon#read 5, iclass 36, count 2 2006.182.07:58:58.72#ibcon#about to read 6, iclass 36, count 2 2006.182.07:58:58.72#ibcon#read 6, iclass 36, count 2 2006.182.07:58:58.72#ibcon#end of sib2, iclass 36, count 2 2006.182.07:58:58.72#ibcon#*mode == 0, iclass 36, count 2 2006.182.07:58:58.72#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.182.07:58:58.72#ibcon#[25=AT03-06\r\n] 2006.182.07:58:58.72#ibcon#*before write, iclass 36, count 2 2006.182.07:58:58.72#ibcon#enter sib2, iclass 36, count 2 2006.182.07:58:58.72#ibcon#flushed, iclass 36, count 2 2006.182.07:58:58.72#ibcon#about to write, iclass 36, count 2 2006.182.07:58:58.72#ibcon#wrote, iclass 36, count 2 2006.182.07:58:58.72#ibcon#about to read 3, iclass 36, count 2 2006.182.07:58:58.75#ibcon#read 3, iclass 36, count 2 2006.182.07:58:58.75#ibcon#about to read 4, iclass 36, count 2 2006.182.07:58:58.75#ibcon#read 4, iclass 36, count 2 2006.182.07:58:58.75#ibcon#about to read 5, iclass 36, count 2 2006.182.07:58:58.75#ibcon#read 5, iclass 36, count 2 2006.182.07:58:58.75#ibcon#about to read 6, iclass 36, count 2 2006.182.07:58:58.75#ibcon#read 6, iclass 36, count 2 2006.182.07:58:58.75#ibcon#end of sib2, iclass 36, count 2 2006.182.07:58:58.75#ibcon#*after write, iclass 36, count 2 2006.182.07:58:58.75#ibcon#*before return 0, iclass 36, count 2 2006.182.07:58:58.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:58:58.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.182.07:58:58.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.182.07:58:58.75#ibcon#ireg 7 cls_cnt 0 2006.182.07:58:58.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:58:58.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:58:58.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:58:58.87#ibcon#enter wrdev, iclass 36, count 0 2006.182.07:58:58.87#ibcon#first serial, iclass 36, count 0 2006.182.07:58:58.87#ibcon#enter sib2, iclass 36, count 0 2006.182.07:58:58.87#ibcon#flushed, iclass 36, count 0 2006.182.07:58:58.87#ibcon#about to write, iclass 36, count 0 2006.182.07:58:58.87#ibcon#wrote, iclass 36, count 0 2006.182.07:58:58.87#ibcon#about to read 3, iclass 36, count 0 2006.182.07:58:58.89#ibcon#read 3, iclass 36, count 0 2006.182.07:58:58.89#ibcon#about to read 4, iclass 36, count 0 2006.182.07:58:58.89#ibcon#read 4, iclass 36, count 0 2006.182.07:58:58.89#ibcon#about to read 5, iclass 36, count 0 2006.182.07:58:58.89#ibcon#read 5, iclass 36, count 0 2006.182.07:58:58.89#ibcon#about to read 6, iclass 36, count 0 2006.182.07:58:58.89#ibcon#read 6, iclass 36, count 0 2006.182.07:58:58.89#ibcon#end of sib2, iclass 36, count 0 2006.182.07:58:58.89#ibcon#*mode == 0, iclass 36, count 0 2006.182.07:58:58.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.07:58:58.89#ibcon#[25=USB\r\n] 2006.182.07:58:58.89#ibcon#*before write, iclass 36, count 0 2006.182.07:58:58.89#ibcon#enter sib2, iclass 36, count 0 2006.182.07:58:58.89#ibcon#flushed, iclass 36, count 0 2006.182.07:58:58.89#ibcon#about to write, iclass 36, count 0 2006.182.07:58:58.89#ibcon#wrote, iclass 36, count 0 2006.182.07:58:58.89#ibcon#about to read 3, iclass 36, count 0 2006.182.07:58:58.92#ibcon#read 3, iclass 36, count 0 2006.182.07:58:58.92#ibcon#about to read 4, iclass 36, count 0 2006.182.07:58:58.92#ibcon#read 4, iclass 36, count 0 2006.182.07:58:58.92#ibcon#about to read 5, iclass 36, count 0 2006.182.07:58:58.92#ibcon#read 5, iclass 36, count 0 2006.182.07:58:58.92#ibcon#about to read 6, iclass 36, count 0 2006.182.07:58:58.92#ibcon#read 6, iclass 36, count 0 2006.182.07:58:58.92#ibcon#end of sib2, iclass 36, count 0 2006.182.07:58:58.92#ibcon#*after write, iclass 36, count 0 2006.182.07:58:58.92#ibcon#*before return 0, iclass 36, count 0 2006.182.07:58:58.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:58:58.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.182.07:58:58.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.07:58:58.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.07:58:58.92$vc4f8/valo=4,832.99 2006.182.07:58:58.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.07:58:58.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.07:58:58.92#ibcon#ireg 17 cls_cnt 0 2006.182.07:58:58.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:58:58.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:58:58.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:58:58.92#ibcon#enter wrdev, iclass 38, count 0 2006.182.07:58:58.92#ibcon#first serial, iclass 38, count 0 2006.182.07:58:58.92#ibcon#enter sib2, iclass 38, count 0 2006.182.07:58:58.92#ibcon#flushed, iclass 38, count 0 2006.182.07:58:58.92#ibcon#about to write, iclass 38, count 0 2006.182.07:58:58.92#ibcon#wrote, iclass 38, count 0 2006.182.07:58:58.92#ibcon#about to read 3, iclass 38, count 0 2006.182.07:58:58.94#ibcon#read 3, iclass 38, count 0 2006.182.07:58:58.94#ibcon#about to read 4, iclass 38, count 0 2006.182.07:58:58.94#ibcon#read 4, iclass 38, count 0 2006.182.07:58:58.94#ibcon#about to read 5, iclass 38, count 0 2006.182.07:58:58.94#ibcon#read 5, iclass 38, count 0 2006.182.07:58:58.94#ibcon#about to read 6, iclass 38, count 0 2006.182.07:58:58.94#ibcon#read 6, iclass 38, count 0 2006.182.07:58:58.94#ibcon#end of sib2, iclass 38, count 0 2006.182.07:58:58.94#ibcon#*mode == 0, iclass 38, count 0 2006.182.07:58:58.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.07:58:58.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.07:58:58.94#ibcon#*before write, iclass 38, count 0 2006.182.07:58:58.94#ibcon#enter sib2, iclass 38, count 0 2006.182.07:58:58.94#ibcon#flushed, iclass 38, count 0 2006.182.07:58:58.94#ibcon#about to write, iclass 38, count 0 2006.182.07:58:58.94#ibcon#wrote, iclass 38, count 0 2006.182.07:58:58.94#ibcon#about to read 3, iclass 38, count 0 2006.182.07:58:58.98#ibcon#read 3, iclass 38, count 0 2006.182.07:58:58.98#ibcon#about to read 4, iclass 38, count 0 2006.182.07:58:58.98#ibcon#read 4, iclass 38, count 0 2006.182.07:58:58.98#ibcon#about to read 5, iclass 38, count 0 2006.182.07:58:58.98#ibcon#read 5, iclass 38, count 0 2006.182.07:58:58.98#ibcon#about to read 6, iclass 38, count 0 2006.182.07:58:58.98#ibcon#read 6, iclass 38, count 0 2006.182.07:58:58.98#ibcon#end of sib2, iclass 38, count 0 2006.182.07:58:58.98#ibcon#*after write, iclass 38, count 0 2006.182.07:58:58.98#ibcon#*before return 0, iclass 38, count 0 2006.182.07:58:58.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:58:58.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.07:58:58.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.07:58:58.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.07:58:58.98$vc4f8/va=4,7 2006.182.07:58:58.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.07:58:58.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.07:58:58.98#ibcon#ireg 11 cls_cnt 2 2006.182.07:58:58.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:58:59.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:58:59.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:58:59.04#ibcon#enter wrdev, iclass 40, count 2 2006.182.07:58:59.04#ibcon#first serial, iclass 40, count 2 2006.182.07:58:59.04#ibcon#enter sib2, iclass 40, count 2 2006.182.07:58:59.04#ibcon#flushed, iclass 40, count 2 2006.182.07:58:59.04#ibcon#about to write, iclass 40, count 2 2006.182.07:58:59.04#ibcon#wrote, iclass 40, count 2 2006.182.07:58:59.04#ibcon#about to read 3, iclass 40, count 2 2006.182.07:58:59.06#ibcon#read 3, iclass 40, count 2 2006.182.07:58:59.06#ibcon#about to read 4, iclass 40, count 2 2006.182.07:58:59.06#ibcon#read 4, iclass 40, count 2 2006.182.07:58:59.06#ibcon#about to read 5, iclass 40, count 2 2006.182.07:58:59.06#ibcon#read 5, iclass 40, count 2 2006.182.07:58:59.06#ibcon#about to read 6, iclass 40, count 2 2006.182.07:58:59.06#ibcon#read 6, iclass 40, count 2 2006.182.07:58:59.06#ibcon#end of sib2, iclass 40, count 2 2006.182.07:58:59.06#ibcon#*mode == 0, iclass 40, count 2 2006.182.07:58:59.06#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.07:58:59.06#ibcon#[25=AT04-07\r\n] 2006.182.07:58:59.06#ibcon#*before write, iclass 40, count 2 2006.182.07:58:59.06#ibcon#enter sib2, iclass 40, count 2 2006.182.07:58:59.06#ibcon#flushed, iclass 40, count 2 2006.182.07:58:59.06#ibcon#about to write, iclass 40, count 2 2006.182.07:58:59.06#ibcon#wrote, iclass 40, count 2 2006.182.07:58:59.06#ibcon#about to read 3, iclass 40, count 2 2006.182.07:58:59.09#ibcon#read 3, iclass 40, count 2 2006.182.07:58:59.09#ibcon#about to read 4, iclass 40, count 2 2006.182.07:58:59.09#ibcon#read 4, iclass 40, count 2 2006.182.07:58:59.09#ibcon#about to read 5, iclass 40, count 2 2006.182.07:58:59.09#ibcon#read 5, iclass 40, count 2 2006.182.07:58:59.09#ibcon#about to read 6, iclass 40, count 2 2006.182.07:58:59.09#ibcon#read 6, iclass 40, count 2 2006.182.07:58:59.09#ibcon#end of sib2, iclass 40, count 2 2006.182.07:58:59.09#ibcon#*after write, iclass 40, count 2 2006.182.07:58:59.09#ibcon#*before return 0, iclass 40, count 2 2006.182.07:58:59.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:58:59.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.07:58:59.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.07:58:59.09#ibcon#ireg 7 cls_cnt 0 2006.182.07:58:59.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:58:59.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:58:59.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:58:59.21#ibcon#enter wrdev, iclass 40, count 0 2006.182.07:58:59.21#ibcon#first serial, iclass 40, count 0 2006.182.07:58:59.21#ibcon#enter sib2, iclass 40, count 0 2006.182.07:58:59.21#ibcon#flushed, iclass 40, count 0 2006.182.07:58:59.21#ibcon#about to write, iclass 40, count 0 2006.182.07:58:59.21#ibcon#wrote, iclass 40, count 0 2006.182.07:58:59.21#ibcon#about to read 3, iclass 40, count 0 2006.182.07:58:59.23#ibcon#read 3, iclass 40, count 0 2006.182.07:58:59.23#ibcon#about to read 4, iclass 40, count 0 2006.182.07:58:59.23#ibcon#read 4, iclass 40, count 0 2006.182.07:58:59.23#ibcon#about to read 5, iclass 40, count 0 2006.182.07:58:59.23#ibcon#read 5, iclass 40, count 0 2006.182.07:58:59.23#ibcon#about to read 6, iclass 40, count 0 2006.182.07:58:59.23#ibcon#read 6, iclass 40, count 0 2006.182.07:58:59.23#ibcon#end of sib2, iclass 40, count 0 2006.182.07:58:59.23#ibcon#*mode == 0, iclass 40, count 0 2006.182.07:58:59.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.07:58:59.23#ibcon#[25=USB\r\n] 2006.182.07:58:59.23#ibcon#*before write, iclass 40, count 0 2006.182.07:58:59.23#ibcon#enter sib2, iclass 40, count 0 2006.182.07:58:59.23#ibcon#flushed, iclass 40, count 0 2006.182.07:58:59.23#ibcon#about to write, iclass 40, count 0 2006.182.07:58:59.23#ibcon#wrote, iclass 40, count 0 2006.182.07:58:59.23#ibcon#about to read 3, iclass 40, count 0 2006.182.07:58:59.26#ibcon#read 3, iclass 40, count 0 2006.182.07:58:59.26#ibcon#about to read 4, iclass 40, count 0 2006.182.07:58:59.26#ibcon#read 4, iclass 40, count 0 2006.182.07:58:59.26#ibcon#about to read 5, iclass 40, count 0 2006.182.07:58:59.26#ibcon#read 5, iclass 40, count 0 2006.182.07:58:59.26#ibcon#about to read 6, iclass 40, count 0 2006.182.07:58:59.26#ibcon#read 6, iclass 40, count 0 2006.182.07:58:59.26#ibcon#end of sib2, iclass 40, count 0 2006.182.07:58:59.26#ibcon#*after write, iclass 40, count 0 2006.182.07:58:59.26#ibcon#*before return 0, iclass 40, count 0 2006.182.07:58:59.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:58:59.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.07:58:59.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.07:58:59.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.07:58:59.26$vc4f8/valo=5,652.99 2006.182.07:58:59.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.07:58:59.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.07:58:59.26#ibcon#ireg 17 cls_cnt 0 2006.182.07:58:59.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:58:59.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:58:59.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:58:59.26#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:58:59.26#ibcon#first serial, iclass 4, count 0 2006.182.07:58:59.26#ibcon#enter sib2, iclass 4, count 0 2006.182.07:58:59.26#ibcon#flushed, iclass 4, count 0 2006.182.07:58:59.26#ibcon#about to write, iclass 4, count 0 2006.182.07:58:59.26#ibcon#wrote, iclass 4, count 0 2006.182.07:58:59.26#ibcon#about to read 3, iclass 4, count 0 2006.182.07:58:59.28#ibcon#read 3, iclass 4, count 0 2006.182.07:58:59.28#ibcon#about to read 4, iclass 4, count 0 2006.182.07:58:59.28#ibcon#read 4, iclass 4, count 0 2006.182.07:58:59.28#ibcon#about to read 5, iclass 4, count 0 2006.182.07:58:59.28#ibcon#read 5, iclass 4, count 0 2006.182.07:58:59.28#ibcon#about to read 6, iclass 4, count 0 2006.182.07:58:59.28#ibcon#read 6, iclass 4, count 0 2006.182.07:58:59.28#ibcon#end of sib2, iclass 4, count 0 2006.182.07:58:59.28#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:58:59.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:58:59.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.07:58:59.28#ibcon#*before write, iclass 4, count 0 2006.182.07:58:59.28#ibcon#enter sib2, iclass 4, count 0 2006.182.07:58:59.28#ibcon#flushed, iclass 4, count 0 2006.182.07:58:59.28#ibcon#about to write, iclass 4, count 0 2006.182.07:58:59.28#ibcon#wrote, iclass 4, count 0 2006.182.07:58:59.28#ibcon#about to read 3, iclass 4, count 0 2006.182.07:58:59.32#ibcon#read 3, iclass 4, count 0 2006.182.07:58:59.32#ibcon#about to read 4, iclass 4, count 0 2006.182.07:58:59.32#ibcon#read 4, iclass 4, count 0 2006.182.07:58:59.32#ibcon#about to read 5, iclass 4, count 0 2006.182.07:58:59.32#ibcon#read 5, iclass 4, count 0 2006.182.07:58:59.32#ibcon#about to read 6, iclass 4, count 0 2006.182.07:58:59.32#ibcon#read 6, iclass 4, count 0 2006.182.07:58:59.32#ibcon#end of sib2, iclass 4, count 0 2006.182.07:58:59.32#ibcon#*after write, iclass 4, count 0 2006.182.07:58:59.32#ibcon#*before return 0, iclass 4, count 0 2006.182.07:58:59.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:58:59.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:58:59.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:58:59.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:58:59.32$vc4f8/va=5,7 2006.182.07:58:59.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.07:58:59.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.07:58:59.32#ibcon#ireg 11 cls_cnt 2 2006.182.07:58:59.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:58:59.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:58:59.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:58:59.38#ibcon#enter wrdev, iclass 6, count 2 2006.182.07:58:59.38#ibcon#first serial, iclass 6, count 2 2006.182.07:58:59.38#ibcon#enter sib2, iclass 6, count 2 2006.182.07:58:59.38#ibcon#flushed, iclass 6, count 2 2006.182.07:58:59.38#ibcon#about to write, iclass 6, count 2 2006.182.07:58:59.38#ibcon#wrote, iclass 6, count 2 2006.182.07:58:59.38#ibcon#about to read 3, iclass 6, count 2 2006.182.07:58:59.40#ibcon#read 3, iclass 6, count 2 2006.182.07:58:59.40#ibcon#about to read 4, iclass 6, count 2 2006.182.07:58:59.40#ibcon#read 4, iclass 6, count 2 2006.182.07:58:59.40#ibcon#about to read 5, iclass 6, count 2 2006.182.07:58:59.40#ibcon#read 5, iclass 6, count 2 2006.182.07:58:59.40#ibcon#about to read 6, iclass 6, count 2 2006.182.07:58:59.40#ibcon#read 6, iclass 6, count 2 2006.182.07:58:59.40#ibcon#end of sib2, iclass 6, count 2 2006.182.07:58:59.40#ibcon#*mode == 0, iclass 6, count 2 2006.182.07:58:59.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.07:58:59.40#ibcon#[25=AT05-07\r\n] 2006.182.07:58:59.40#ibcon#*before write, iclass 6, count 2 2006.182.07:58:59.40#ibcon#enter sib2, iclass 6, count 2 2006.182.07:58:59.40#ibcon#flushed, iclass 6, count 2 2006.182.07:58:59.40#ibcon#about to write, iclass 6, count 2 2006.182.07:58:59.40#ibcon#wrote, iclass 6, count 2 2006.182.07:58:59.40#ibcon#about to read 3, iclass 6, count 2 2006.182.07:58:59.43#ibcon#read 3, iclass 6, count 2 2006.182.07:58:59.43#ibcon#about to read 4, iclass 6, count 2 2006.182.07:58:59.43#ibcon#read 4, iclass 6, count 2 2006.182.07:58:59.43#ibcon#about to read 5, iclass 6, count 2 2006.182.07:58:59.43#ibcon#read 5, iclass 6, count 2 2006.182.07:58:59.43#ibcon#about to read 6, iclass 6, count 2 2006.182.07:58:59.43#ibcon#read 6, iclass 6, count 2 2006.182.07:58:59.43#ibcon#end of sib2, iclass 6, count 2 2006.182.07:58:59.43#ibcon#*after write, iclass 6, count 2 2006.182.07:58:59.43#ibcon#*before return 0, iclass 6, count 2 2006.182.07:58:59.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:58:59.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:58:59.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.07:58:59.43#ibcon#ireg 7 cls_cnt 0 2006.182.07:58:59.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:58:59.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:58:59.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:58:59.55#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:58:59.55#ibcon#first serial, iclass 6, count 0 2006.182.07:58:59.55#ibcon#enter sib2, iclass 6, count 0 2006.182.07:58:59.55#ibcon#flushed, iclass 6, count 0 2006.182.07:58:59.55#ibcon#about to write, iclass 6, count 0 2006.182.07:58:59.55#ibcon#wrote, iclass 6, count 0 2006.182.07:58:59.55#ibcon#about to read 3, iclass 6, count 0 2006.182.07:58:59.57#ibcon#read 3, iclass 6, count 0 2006.182.07:58:59.57#ibcon#about to read 4, iclass 6, count 0 2006.182.07:58:59.57#ibcon#read 4, iclass 6, count 0 2006.182.07:58:59.57#ibcon#about to read 5, iclass 6, count 0 2006.182.07:58:59.57#ibcon#read 5, iclass 6, count 0 2006.182.07:58:59.57#ibcon#about to read 6, iclass 6, count 0 2006.182.07:58:59.57#ibcon#read 6, iclass 6, count 0 2006.182.07:58:59.57#ibcon#end of sib2, iclass 6, count 0 2006.182.07:58:59.57#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:58:59.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:58:59.57#ibcon#[25=USB\r\n] 2006.182.07:58:59.57#ibcon#*before write, iclass 6, count 0 2006.182.07:58:59.57#ibcon#enter sib2, iclass 6, count 0 2006.182.07:58:59.57#ibcon#flushed, iclass 6, count 0 2006.182.07:58:59.57#ibcon#about to write, iclass 6, count 0 2006.182.07:58:59.57#ibcon#wrote, iclass 6, count 0 2006.182.07:58:59.57#ibcon#about to read 3, iclass 6, count 0 2006.182.07:58:59.60#ibcon#read 3, iclass 6, count 0 2006.182.07:58:59.60#ibcon#about to read 4, iclass 6, count 0 2006.182.07:58:59.60#ibcon#read 4, iclass 6, count 0 2006.182.07:58:59.60#ibcon#about to read 5, iclass 6, count 0 2006.182.07:58:59.60#ibcon#read 5, iclass 6, count 0 2006.182.07:58:59.60#ibcon#about to read 6, iclass 6, count 0 2006.182.07:58:59.60#ibcon#read 6, iclass 6, count 0 2006.182.07:58:59.60#ibcon#end of sib2, iclass 6, count 0 2006.182.07:58:59.60#ibcon#*after write, iclass 6, count 0 2006.182.07:58:59.60#ibcon#*before return 0, iclass 6, count 0 2006.182.07:58:59.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:58:59.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:58:59.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:58:59.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:58:59.60$vc4f8/valo=6,772.99 2006.182.07:58:59.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.07:58:59.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.07:58:59.60#ibcon#ireg 17 cls_cnt 0 2006.182.07:58:59.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:58:59.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:58:59.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:58:59.60#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:58:59.60#ibcon#first serial, iclass 10, count 0 2006.182.07:58:59.60#ibcon#enter sib2, iclass 10, count 0 2006.182.07:58:59.60#ibcon#flushed, iclass 10, count 0 2006.182.07:58:59.60#ibcon#about to write, iclass 10, count 0 2006.182.07:58:59.60#ibcon#wrote, iclass 10, count 0 2006.182.07:58:59.60#ibcon#about to read 3, iclass 10, count 0 2006.182.07:58:59.63#ibcon#read 3, iclass 10, count 0 2006.182.07:58:59.63#ibcon#about to read 4, iclass 10, count 0 2006.182.07:58:59.63#ibcon#read 4, iclass 10, count 0 2006.182.07:58:59.63#ibcon#about to read 5, iclass 10, count 0 2006.182.07:58:59.63#ibcon#read 5, iclass 10, count 0 2006.182.07:58:59.63#ibcon#about to read 6, iclass 10, count 0 2006.182.07:58:59.63#ibcon#read 6, iclass 10, count 0 2006.182.07:58:59.63#ibcon#end of sib2, iclass 10, count 0 2006.182.07:58:59.63#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:58:59.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:58:59.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.07:58:59.63#ibcon#*before write, iclass 10, count 0 2006.182.07:58:59.63#ibcon#enter sib2, iclass 10, count 0 2006.182.07:58:59.63#ibcon#flushed, iclass 10, count 0 2006.182.07:58:59.63#ibcon#about to write, iclass 10, count 0 2006.182.07:58:59.63#ibcon#wrote, iclass 10, count 0 2006.182.07:58:59.63#ibcon#about to read 3, iclass 10, count 0 2006.182.07:58:59.67#ibcon#read 3, iclass 10, count 0 2006.182.07:58:59.67#ibcon#about to read 4, iclass 10, count 0 2006.182.07:58:59.67#ibcon#read 4, iclass 10, count 0 2006.182.07:58:59.67#ibcon#about to read 5, iclass 10, count 0 2006.182.07:58:59.67#ibcon#read 5, iclass 10, count 0 2006.182.07:58:59.67#ibcon#about to read 6, iclass 10, count 0 2006.182.07:58:59.67#ibcon#read 6, iclass 10, count 0 2006.182.07:58:59.67#ibcon#end of sib2, iclass 10, count 0 2006.182.07:58:59.67#ibcon#*after write, iclass 10, count 0 2006.182.07:58:59.67#ibcon#*before return 0, iclass 10, count 0 2006.182.07:58:59.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:58:59.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:58:59.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:58:59.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:58:59.67$vc4f8/va=6,6 2006.182.07:58:59.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.07:58:59.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.07:58:59.67#ibcon#ireg 11 cls_cnt 2 2006.182.07:58:59.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:58:59.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:58:59.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:58:59.72#ibcon#enter wrdev, iclass 12, count 2 2006.182.07:58:59.72#ibcon#first serial, iclass 12, count 2 2006.182.07:58:59.72#ibcon#enter sib2, iclass 12, count 2 2006.182.07:58:59.72#ibcon#flushed, iclass 12, count 2 2006.182.07:58:59.72#ibcon#about to write, iclass 12, count 2 2006.182.07:58:59.72#ibcon#wrote, iclass 12, count 2 2006.182.07:58:59.72#ibcon#about to read 3, iclass 12, count 2 2006.182.07:58:59.74#ibcon#read 3, iclass 12, count 2 2006.182.07:58:59.74#ibcon#about to read 4, iclass 12, count 2 2006.182.07:58:59.74#ibcon#read 4, iclass 12, count 2 2006.182.07:58:59.74#ibcon#about to read 5, iclass 12, count 2 2006.182.07:58:59.74#ibcon#read 5, iclass 12, count 2 2006.182.07:58:59.74#ibcon#about to read 6, iclass 12, count 2 2006.182.07:58:59.74#ibcon#read 6, iclass 12, count 2 2006.182.07:58:59.74#ibcon#end of sib2, iclass 12, count 2 2006.182.07:58:59.74#ibcon#*mode == 0, iclass 12, count 2 2006.182.07:58:59.74#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.07:58:59.74#ibcon#[25=AT06-06\r\n] 2006.182.07:58:59.74#ibcon#*before write, iclass 12, count 2 2006.182.07:58:59.74#ibcon#enter sib2, iclass 12, count 2 2006.182.07:58:59.74#ibcon#flushed, iclass 12, count 2 2006.182.07:58:59.74#ibcon#about to write, iclass 12, count 2 2006.182.07:58:59.74#ibcon#wrote, iclass 12, count 2 2006.182.07:58:59.74#ibcon#about to read 3, iclass 12, count 2 2006.182.07:58:59.77#ibcon#read 3, iclass 12, count 2 2006.182.07:58:59.77#ibcon#about to read 4, iclass 12, count 2 2006.182.07:58:59.77#ibcon#read 4, iclass 12, count 2 2006.182.07:58:59.77#ibcon#about to read 5, iclass 12, count 2 2006.182.07:58:59.77#ibcon#read 5, iclass 12, count 2 2006.182.07:58:59.77#ibcon#about to read 6, iclass 12, count 2 2006.182.07:58:59.77#ibcon#read 6, iclass 12, count 2 2006.182.07:58:59.77#ibcon#end of sib2, iclass 12, count 2 2006.182.07:58:59.77#ibcon#*after write, iclass 12, count 2 2006.182.07:58:59.77#ibcon#*before return 0, iclass 12, count 2 2006.182.07:58:59.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:58:59.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:58:59.77#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.07:58:59.77#ibcon#ireg 7 cls_cnt 0 2006.182.07:58:59.77#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:58:59.89#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:58:59.89#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:58:59.89#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:58:59.89#ibcon#first serial, iclass 12, count 0 2006.182.07:58:59.89#ibcon#enter sib2, iclass 12, count 0 2006.182.07:58:59.89#ibcon#flushed, iclass 12, count 0 2006.182.07:58:59.89#ibcon#about to write, iclass 12, count 0 2006.182.07:58:59.89#ibcon#wrote, iclass 12, count 0 2006.182.07:58:59.89#ibcon#about to read 3, iclass 12, count 0 2006.182.07:58:59.91#ibcon#read 3, iclass 12, count 0 2006.182.07:58:59.91#ibcon#about to read 4, iclass 12, count 0 2006.182.07:58:59.91#ibcon#read 4, iclass 12, count 0 2006.182.07:58:59.91#ibcon#about to read 5, iclass 12, count 0 2006.182.07:58:59.91#ibcon#read 5, iclass 12, count 0 2006.182.07:58:59.91#ibcon#about to read 6, iclass 12, count 0 2006.182.07:58:59.91#ibcon#read 6, iclass 12, count 0 2006.182.07:58:59.91#ibcon#end of sib2, iclass 12, count 0 2006.182.07:58:59.91#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:58:59.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:58:59.91#ibcon#[25=USB\r\n] 2006.182.07:58:59.91#ibcon#*before write, iclass 12, count 0 2006.182.07:58:59.91#ibcon#enter sib2, iclass 12, count 0 2006.182.07:58:59.91#ibcon#flushed, iclass 12, count 0 2006.182.07:58:59.91#ibcon#about to write, iclass 12, count 0 2006.182.07:58:59.91#ibcon#wrote, iclass 12, count 0 2006.182.07:58:59.91#ibcon#about to read 3, iclass 12, count 0 2006.182.07:58:59.94#ibcon#read 3, iclass 12, count 0 2006.182.07:58:59.94#ibcon#about to read 4, iclass 12, count 0 2006.182.07:58:59.94#ibcon#read 4, iclass 12, count 0 2006.182.07:58:59.94#ibcon#about to read 5, iclass 12, count 0 2006.182.07:58:59.94#ibcon#read 5, iclass 12, count 0 2006.182.07:58:59.94#ibcon#about to read 6, iclass 12, count 0 2006.182.07:58:59.94#ibcon#read 6, iclass 12, count 0 2006.182.07:58:59.94#ibcon#end of sib2, iclass 12, count 0 2006.182.07:58:59.94#ibcon#*after write, iclass 12, count 0 2006.182.07:58:59.94#ibcon#*before return 0, iclass 12, count 0 2006.182.07:58:59.94#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:58:59.94#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:58:59.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:58:59.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:58:59.94$vc4f8/valo=7,832.99 2006.182.07:58:59.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.07:58:59.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.07:58:59.94#ibcon#ireg 17 cls_cnt 0 2006.182.07:58:59.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:58:59.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:58:59.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:58:59.94#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:58:59.94#ibcon#first serial, iclass 14, count 0 2006.182.07:58:59.94#ibcon#enter sib2, iclass 14, count 0 2006.182.07:58:59.94#ibcon#flushed, iclass 14, count 0 2006.182.07:58:59.94#ibcon#about to write, iclass 14, count 0 2006.182.07:58:59.94#ibcon#wrote, iclass 14, count 0 2006.182.07:58:59.94#ibcon#about to read 3, iclass 14, count 0 2006.182.07:58:59.96#ibcon#read 3, iclass 14, count 0 2006.182.07:58:59.96#ibcon#about to read 4, iclass 14, count 0 2006.182.07:58:59.96#ibcon#read 4, iclass 14, count 0 2006.182.07:58:59.96#ibcon#about to read 5, iclass 14, count 0 2006.182.07:58:59.96#ibcon#read 5, iclass 14, count 0 2006.182.07:58:59.96#ibcon#about to read 6, iclass 14, count 0 2006.182.07:58:59.96#ibcon#read 6, iclass 14, count 0 2006.182.07:58:59.96#ibcon#end of sib2, iclass 14, count 0 2006.182.07:58:59.96#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:58:59.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:58:59.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.07:58:59.96#ibcon#*before write, iclass 14, count 0 2006.182.07:58:59.96#ibcon#enter sib2, iclass 14, count 0 2006.182.07:58:59.96#ibcon#flushed, iclass 14, count 0 2006.182.07:58:59.96#ibcon#about to write, iclass 14, count 0 2006.182.07:58:59.96#ibcon#wrote, iclass 14, count 0 2006.182.07:58:59.96#ibcon#about to read 3, iclass 14, count 0 2006.182.07:59:00.00#ibcon#read 3, iclass 14, count 0 2006.182.07:59:00.00#ibcon#about to read 4, iclass 14, count 0 2006.182.07:59:00.00#ibcon#read 4, iclass 14, count 0 2006.182.07:59:00.00#ibcon#about to read 5, iclass 14, count 0 2006.182.07:59:00.00#ibcon#read 5, iclass 14, count 0 2006.182.07:59:00.00#ibcon#about to read 6, iclass 14, count 0 2006.182.07:59:00.00#ibcon#read 6, iclass 14, count 0 2006.182.07:59:00.00#ibcon#end of sib2, iclass 14, count 0 2006.182.07:59:00.00#ibcon#*after write, iclass 14, count 0 2006.182.07:59:00.00#ibcon#*before return 0, iclass 14, count 0 2006.182.07:59:00.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:59:00.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:59:00.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:59:00.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:59:00.00$vc4f8/va=7,6 2006.182.07:59:00.00#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.07:59:00.00#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.07:59:00.00#ibcon#ireg 11 cls_cnt 2 2006.182.07:59:00.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:59:00.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:59:00.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:59:00.06#ibcon#enter wrdev, iclass 16, count 2 2006.182.07:59:00.06#ibcon#first serial, iclass 16, count 2 2006.182.07:59:00.06#ibcon#enter sib2, iclass 16, count 2 2006.182.07:59:00.06#ibcon#flushed, iclass 16, count 2 2006.182.07:59:00.06#ibcon#about to write, iclass 16, count 2 2006.182.07:59:00.06#ibcon#wrote, iclass 16, count 2 2006.182.07:59:00.06#ibcon#about to read 3, iclass 16, count 2 2006.182.07:59:00.08#ibcon#read 3, iclass 16, count 2 2006.182.07:59:00.08#ibcon#about to read 4, iclass 16, count 2 2006.182.07:59:00.08#ibcon#read 4, iclass 16, count 2 2006.182.07:59:00.08#ibcon#about to read 5, iclass 16, count 2 2006.182.07:59:00.08#ibcon#read 5, iclass 16, count 2 2006.182.07:59:00.08#ibcon#about to read 6, iclass 16, count 2 2006.182.07:59:00.08#ibcon#read 6, iclass 16, count 2 2006.182.07:59:00.08#ibcon#end of sib2, iclass 16, count 2 2006.182.07:59:00.08#ibcon#*mode == 0, iclass 16, count 2 2006.182.07:59:00.08#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.07:59:00.08#ibcon#[25=AT07-06\r\n] 2006.182.07:59:00.08#ibcon#*before write, iclass 16, count 2 2006.182.07:59:00.08#ibcon#enter sib2, iclass 16, count 2 2006.182.07:59:00.08#ibcon#flushed, iclass 16, count 2 2006.182.07:59:00.08#ibcon#about to write, iclass 16, count 2 2006.182.07:59:00.08#ibcon#wrote, iclass 16, count 2 2006.182.07:59:00.08#ibcon#about to read 3, iclass 16, count 2 2006.182.07:59:00.11#ibcon#read 3, iclass 16, count 2 2006.182.07:59:00.11#ibcon#about to read 4, iclass 16, count 2 2006.182.07:59:00.11#ibcon#read 4, iclass 16, count 2 2006.182.07:59:00.11#ibcon#about to read 5, iclass 16, count 2 2006.182.07:59:00.11#ibcon#read 5, iclass 16, count 2 2006.182.07:59:00.11#ibcon#about to read 6, iclass 16, count 2 2006.182.07:59:00.11#ibcon#read 6, iclass 16, count 2 2006.182.07:59:00.11#ibcon#end of sib2, iclass 16, count 2 2006.182.07:59:00.11#ibcon#*after write, iclass 16, count 2 2006.182.07:59:00.11#ibcon#*before return 0, iclass 16, count 2 2006.182.07:59:00.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:59:00.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.07:59:00.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.07:59:00.11#ibcon#ireg 7 cls_cnt 0 2006.182.07:59:00.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:59:00.23#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:59:00.23#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:59:00.23#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:59:00.23#ibcon#first serial, iclass 16, count 0 2006.182.07:59:00.23#ibcon#enter sib2, iclass 16, count 0 2006.182.07:59:00.23#ibcon#flushed, iclass 16, count 0 2006.182.07:59:00.23#ibcon#about to write, iclass 16, count 0 2006.182.07:59:00.23#ibcon#wrote, iclass 16, count 0 2006.182.07:59:00.23#ibcon#about to read 3, iclass 16, count 0 2006.182.07:59:00.25#ibcon#read 3, iclass 16, count 0 2006.182.07:59:00.25#ibcon#about to read 4, iclass 16, count 0 2006.182.07:59:00.25#ibcon#read 4, iclass 16, count 0 2006.182.07:59:00.25#ibcon#about to read 5, iclass 16, count 0 2006.182.07:59:00.25#ibcon#read 5, iclass 16, count 0 2006.182.07:59:00.25#ibcon#about to read 6, iclass 16, count 0 2006.182.07:59:00.25#ibcon#read 6, iclass 16, count 0 2006.182.07:59:00.25#ibcon#end of sib2, iclass 16, count 0 2006.182.07:59:00.25#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:59:00.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:59:00.25#ibcon#[25=USB\r\n] 2006.182.07:59:00.25#ibcon#*before write, iclass 16, count 0 2006.182.07:59:00.25#ibcon#enter sib2, iclass 16, count 0 2006.182.07:59:00.25#ibcon#flushed, iclass 16, count 0 2006.182.07:59:00.25#ibcon#about to write, iclass 16, count 0 2006.182.07:59:00.25#ibcon#wrote, iclass 16, count 0 2006.182.07:59:00.25#ibcon#about to read 3, iclass 16, count 0 2006.182.07:59:00.28#ibcon#read 3, iclass 16, count 0 2006.182.07:59:00.28#ibcon#about to read 4, iclass 16, count 0 2006.182.07:59:00.28#ibcon#read 4, iclass 16, count 0 2006.182.07:59:00.28#ibcon#about to read 5, iclass 16, count 0 2006.182.07:59:00.28#ibcon#read 5, iclass 16, count 0 2006.182.07:59:00.28#ibcon#about to read 6, iclass 16, count 0 2006.182.07:59:00.28#ibcon#read 6, iclass 16, count 0 2006.182.07:59:00.28#ibcon#end of sib2, iclass 16, count 0 2006.182.07:59:00.28#ibcon#*after write, iclass 16, count 0 2006.182.07:59:00.28#ibcon#*before return 0, iclass 16, count 0 2006.182.07:59:00.28#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:59:00.28#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.07:59:00.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:59:00.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:59:00.28$vc4f8/valo=8,852.99 2006.182.07:59:00.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.07:59:00.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.07:59:00.28#ibcon#ireg 17 cls_cnt 0 2006.182.07:59:00.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:59:00.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:59:00.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:59:00.28#ibcon#enter wrdev, iclass 18, count 0 2006.182.07:59:00.28#ibcon#first serial, iclass 18, count 0 2006.182.07:59:00.28#ibcon#enter sib2, iclass 18, count 0 2006.182.07:59:00.28#ibcon#flushed, iclass 18, count 0 2006.182.07:59:00.28#ibcon#about to write, iclass 18, count 0 2006.182.07:59:00.29#ibcon#wrote, iclass 18, count 0 2006.182.07:59:00.29#ibcon#about to read 3, iclass 18, count 0 2006.182.07:59:00.30#ibcon#read 3, iclass 18, count 0 2006.182.07:59:00.30#ibcon#about to read 4, iclass 18, count 0 2006.182.07:59:00.30#ibcon#read 4, iclass 18, count 0 2006.182.07:59:00.30#ibcon#about to read 5, iclass 18, count 0 2006.182.07:59:00.30#ibcon#read 5, iclass 18, count 0 2006.182.07:59:00.30#ibcon#about to read 6, iclass 18, count 0 2006.182.07:59:00.30#ibcon#read 6, iclass 18, count 0 2006.182.07:59:00.30#ibcon#end of sib2, iclass 18, count 0 2006.182.07:59:00.30#ibcon#*mode == 0, iclass 18, count 0 2006.182.07:59:00.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.07:59:00.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.07:59:00.30#ibcon#*before write, iclass 18, count 0 2006.182.07:59:00.30#ibcon#enter sib2, iclass 18, count 0 2006.182.07:59:00.30#ibcon#flushed, iclass 18, count 0 2006.182.07:59:00.30#ibcon#about to write, iclass 18, count 0 2006.182.07:59:00.30#ibcon#wrote, iclass 18, count 0 2006.182.07:59:00.30#ibcon#about to read 3, iclass 18, count 0 2006.182.07:59:00.34#ibcon#read 3, iclass 18, count 0 2006.182.07:59:00.34#ibcon#about to read 4, iclass 18, count 0 2006.182.07:59:00.34#ibcon#read 4, iclass 18, count 0 2006.182.07:59:00.34#ibcon#about to read 5, iclass 18, count 0 2006.182.07:59:00.34#ibcon#read 5, iclass 18, count 0 2006.182.07:59:00.34#ibcon#about to read 6, iclass 18, count 0 2006.182.07:59:00.34#ibcon#read 6, iclass 18, count 0 2006.182.07:59:00.34#ibcon#end of sib2, iclass 18, count 0 2006.182.07:59:00.34#ibcon#*after write, iclass 18, count 0 2006.182.07:59:00.34#ibcon#*before return 0, iclass 18, count 0 2006.182.07:59:00.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:59:00.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.07:59:00.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.07:59:00.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.07:59:00.34$vc4f8/va=8,7 2006.182.07:59:00.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.07:59:00.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.07:59:00.34#ibcon#ireg 11 cls_cnt 2 2006.182.07:59:00.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:59:00.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:59:00.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:59:00.40#ibcon#enter wrdev, iclass 20, count 2 2006.182.07:59:00.40#ibcon#first serial, iclass 20, count 2 2006.182.07:59:00.40#ibcon#enter sib2, iclass 20, count 2 2006.182.07:59:00.40#ibcon#flushed, iclass 20, count 2 2006.182.07:59:00.40#ibcon#about to write, iclass 20, count 2 2006.182.07:59:00.40#ibcon#wrote, iclass 20, count 2 2006.182.07:59:00.40#ibcon#about to read 3, iclass 20, count 2 2006.182.07:59:00.42#ibcon#read 3, iclass 20, count 2 2006.182.07:59:00.42#ibcon#about to read 4, iclass 20, count 2 2006.182.07:59:00.42#ibcon#read 4, iclass 20, count 2 2006.182.07:59:00.42#ibcon#about to read 5, iclass 20, count 2 2006.182.07:59:00.42#ibcon#read 5, iclass 20, count 2 2006.182.07:59:00.42#ibcon#about to read 6, iclass 20, count 2 2006.182.07:59:00.42#ibcon#read 6, iclass 20, count 2 2006.182.07:59:00.42#ibcon#end of sib2, iclass 20, count 2 2006.182.07:59:00.42#ibcon#*mode == 0, iclass 20, count 2 2006.182.07:59:00.42#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.07:59:00.42#ibcon#[25=AT08-07\r\n] 2006.182.07:59:00.42#ibcon#*before write, iclass 20, count 2 2006.182.07:59:00.42#ibcon#enter sib2, iclass 20, count 2 2006.182.07:59:00.42#ibcon#flushed, iclass 20, count 2 2006.182.07:59:00.42#ibcon#about to write, iclass 20, count 2 2006.182.07:59:00.42#ibcon#wrote, iclass 20, count 2 2006.182.07:59:00.42#ibcon#about to read 3, iclass 20, count 2 2006.182.07:59:00.45#ibcon#read 3, iclass 20, count 2 2006.182.07:59:00.45#ibcon#about to read 4, iclass 20, count 2 2006.182.07:59:00.45#ibcon#read 4, iclass 20, count 2 2006.182.07:59:00.45#ibcon#about to read 5, iclass 20, count 2 2006.182.07:59:00.45#ibcon#read 5, iclass 20, count 2 2006.182.07:59:00.45#ibcon#about to read 6, iclass 20, count 2 2006.182.07:59:00.45#ibcon#read 6, iclass 20, count 2 2006.182.07:59:00.45#ibcon#end of sib2, iclass 20, count 2 2006.182.07:59:00.45#ibcon#*after write, iclass 20, count 2 2006.182.07:59:00.45#ibcon#*before return 0, iclass 20, count 2 2006.182.07:59:00.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:59:00.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.07:59:00.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.07:59:00.45#ibcon#ireg 7 cls_cnt 0 2006.182.07:59:00.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:59:00.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:59:00.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:59:00.57#ibcon#enter wrdev, iclass 20, count 0 2006.182.07:59:00.57#ibcon#first serial, iclass 20, count 0 2006.182.07:59:00.57#ibcon#enter sib2, iclass 20, count 0 2006.182.07:59:00.57#ibcon#flushed, iclass 20, count 0 2006.182.07:59:00.57#ibcon#about to write, iclass 20, count 0 2006.182.07:59:00.57#ibcon#wrote, iclass 20, count 0 2006.182.07:59:00.57#ibcon#about to read 3, iclass 20, count 0 2006.182.07:59:00.59#ibcon#read 3, iclass 20, count 0 2006.182.07:59:00.59#ibcon#about to read 4, iclass 20, count 0 2006.182.07:59:00.59#ibcon#read 4, iclass 20, count 0 2006.182.07:59:00.59#ibcon#about to read 5, iclass 20, count 0 2006.182.07:59:00.59#ibcon#read 5, iclass 20, count 0 2006.182.07:59:00.59#ibcon#about to read 6, iclass 20, count 0 2006.182.07:59:00.59#ibcon#read 6, iclass 20, count 0 2006.182.07:59:00.59#ibcon#end of sib2, iclass 20, count 0 2006.182.07:59:00.59#ibcon#*mode == 0, iclass 20, count 0 2006.182.07:59:00.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.07:59:00.59#ibcon#[25=USB\r\n] 2006.182.07:59:00.59#ibcon#*before write, iclass 20, count 0 2006.182.07:59:00.59#ibcon#enter sib2, iclass 20, count 0 2006.182.07:59:00.59#ibcon#flushed, iclass 20, count 0 2006.182.07:59:00.59#ibcon#about to write, iclass 20, count 0 2006.182.07:59:00.59#ibcon#wrote, iclass 20, count 0 2006.182.07:59:00.59#ibcon#about to read 3, iclass 20, count 0 2006.182.07:59:00.62#ibcon#read 3, iclass 20, count 0 2006.182.07:59:00.62#ibcon#about to read 4, iclass 20, count 0 2006.182.07:59:00.62#ibcon#read 4, iclass 20, count 0 2006.182.07:59:00.62#ibcon#about to read 5, iclass 20, count 0 2006.182.07:59:00.62#ibcon#read 5, iclass 20, count 0 2006.182.07:59:00.62#ibcon#about to read 6, iclass 20, count 0 2006.182.07:59:00.62#ibcon#read 6, iclass 20, count 0 2006.182.07:59:00.62#ibcon#end of sib2, iclass 20, count 0 2006.182.07:59:00.62#ibcon#*after write, iclass 20, count 0 2006.182.07:59:00.62#ibcon#*before return 0, iclass 20, count 0 2006.182.07:59:00.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:59:00.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.07:59:00.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.07:59:00.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.07:59:00.62$vc4f8/vblo=1,632.99 2006.182.07:59:00.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.07:59:00.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.07:59:00.62#ibcon#ireg 17 cls_cnt 0 2006.182.07:59:00.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:59:00.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:59:00.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:59:00.62#ibcon#enter wrdev, iclass 22, count 0 2006.182.07:59:00.62#ibcon#first serial, iclass 22, count 0 2006.182.07:59:00.62#ibcon#enter sib2, iclass 22, count 0 2006.182.07:59:00.62#ibcon#flushed, iclass 22, count 0 2006.182.07:59:00.62#ibcon#about to write, iclass 22, count 0 2006.182.07:59:00.62#ibcon#wrote, iclass 22, count 0 2006.182.07:59:00.62#ibcon#about to read 3, iclass 22, count 0 2006.182.07:59:00.64#ibcon#read 3, iclass 22, count 0 2006.182.07:59:00.64#ibcon#about to read 4, iclass 22, count 0 2006.182.07:59:00.64#ibcon#read 4, iclass 22, count 0 2006.182.07:59:00.64#ibcon#about to read 5, iclass 22, count 0 2006.182.07:59:00.64#ibcon#read 5, iclass 22, count 0 2006.182.07:59:00.64#ibcon#about to read 6, iclass 22, count 0 2006.182.07:59:00.64#ibcon#read 6, iclass 22, count 0 2006.182.07:59:00.64#ibcon#end of sib2, iclass 22, count 0 2006.182.07:59:00.64#ibcon#*mode == 0, iclass 22, count 0 2006.182.07:59:00.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.07:59:00.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.07:59:00.64#ibcon#*before write, iclass 22, count 0 2006.182.07:59:00.64#ibcon#enter sib2, iclass 22, count 0 2006.182.07:59:00.64#ibcon#flushed, iclass 22, count 0 2006.182.07:59:00.64#ibcon#about to write, iclass 22, count 0 2006.182.07:59:00.64#ibcon#wrote, iclass 22, count 0 2006.182.07:59:00.64#ibcon#about to read 3, iclass 22, count 0 2006.182.07:59:00.68#ibcon#read 3, iclass 22, count 0 2006.182.07:59:00.68#ibcon#about to read 4, iclass 22, count 0 2006.182.07:59:00.68#ibcon#read 4, iclass 22, count 0 2006.182.07:59:00.68#ibcon#about to read 5, iclass 22, count 0 2006.182.07:59:00.68#ibcon#read 5, iclass 22, count 0 2006.182.07:59:00.68#ibcon#about to read 6, iclass 22, count 0 2006.182.07:59:00.68#ibcon#read 6, iclass 22, count 0 2006.182.07:59:00.68#ibcon#end of sib2, iclass 22, count 0 2006.182.07:59:00.68#ibcon#*after write, iclass 22, count 0 2006.182.07:59:00.68#ibcon#*before return 0, iclass 22, count 0 2006.182.07:59:00.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:59:00.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.07:59:00.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.07:59:00.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.07:59:00.68$vc4f8/vb=1,4 2006.182.07:59:00.68#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.07:59:00.68#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.07:59:00.68#ibcon#ireg 11 cls_cnt 2 2006.182.07:59:00.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:59:00.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:59:00.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:59:00.68#ibcon#enter wrdev, iclass 24, count 2 2006.182.07:59:00.68#ibcon#first serial, iclass 24, count 2 2006.182.07:59:00.68#ibcon#enter sib2, iclass 24, count 2 2006.182.07:59:00.68#ibcon#flushed, iclass 24, count 2 2006.182.07:59:00.68#ibcon#about to write, iclass 24, count 2 2006.182.07:59:00.68#ibcon#wrote, iclass 24, count 2 2006.182.07:59:00.68#ibcon#about to read 3, iclass 24, count 2 2006.182.07:59:00.70#ibcon#read 3, iclass 24, count 2 2006.182.07:59:00.70#ibcon#about to read 4, iclass 24, count 2 2006.182.07:59:00.70#ibcon#read 4, iclass 24, count 2 2006.182.07:59:00.70#ibcon#about to read 5, iclass 24, count 2 2006.182.07:59:00.70#ibcon#read 5, iclass 24, count 2 2006.182.07:59:00.70#ibcon#about to read 6, iclass 24, count 2 2006.182.07:59:00.70#ibcon#read 6, iclass 24, count 2 2006.182.07:59:00.70#ibcon#end of sib2, iclass 24, count 2 2006.182.07:59:00.70#ibcon#*mode == 0, iclass 24, count 2 2006.182.07:59:00.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.07:59:00.70#ibcon#[27=AT01-04\r\n] 2006.182.07:59:00.70#ibcon#*before write, iclass 24, count 2 2006.182.07:59:00.70#ibcon#enter sib2, iclass 24, count 2 2006.182.07:59:00.70#ibcon#flushed, iclass 24, count 2 2006.182.07:59:00.70#ibcon#about to write, iclass 24, count 2 2006.182.07:59:00.70#ibcon#wrote, iclass 24, count 2 2006.182.07:59:00.70#ibcon#about to read 3, iclass 24, count 2 2006.182.07:59:00.73#ibcon#read 3, iclass 24, count 2 2006.182.07:59:00.73#ibcon#about to read 4, iclass 24, count 2 2006.182.07:59:00.73#ibcon#read 4, iclass 24, count 2 2006.182.07:59:00.73#ibcon#about to read 5, iclass 24, count 2 2006.182.07:59:00.73#ibcon#read 5, iclass 24, count 2 2006.182.07:59:00.73#ibcon#about to read 6, iclass 24, count 2 2006.182.07:59:00.73#ibcon#read 6, iclass 24, count 2 2006.182.07:59:00.73#ibcon#end of sib2, iclass 24, count 2 2006.182.07:59:00.73#ibcon#*after write, iclass 24, count 2 2006.182.07:59:00.73#ibcon#*before return 0, iclass 24, count 2 2006.182.07:59:00.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:59:00.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.07:59:00.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.07:59:00.73#ibcon#ireg 7 cls_cnt 0 2006.182.07:59:00.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:59:00.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:59:00.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:59:00.85#ibcon#enter wrdev, iclass 24, count 0 2006.182.07:59:00.85#ibcon#first serial, iclass 24, count 0 2006.182.07:59:00.85#ibcon#enter sib2, iclass 24, count 0 2006.182.07:59:00.85#ibcon#flushed, iclass 24, count 0 2006.182.07:59:00.85#ibcon#about to write, iclass 24, count 0 2006.182.07:59:00.85#ibcon#wrote, iclass 24, count 0 2006.182.07:59:00.85#ibcon#about to read 3, iclass 24, count 0 2006.182.07:59:00.87#ibcon#read 3, iclass 24, count 0 2006.182.07:59:00.87#ibcon#about to read 4, iclass 24, count 0 2006.182.07:59:00.87#ibcon#read 4, iclass 24, count 0 2006.182.07:59:00.87#ibcon#about to read 5, iclass 24, count 0 2006.182.07:59:00.87#ibcon#read 5, iclass 24, count 0 2006.182.07:59:00.87#ibcon#about to read 6, iclass 24, count 0 2006.182.07:59:00.87#ibcon#read 6, iclass 24, count 0 2006.182.07:59:00.87#ibcon#end of sib2, iclass 24, count 0 2006.182.07:59:00.87#ibcon#*mode == 0, iclass 24, count 0 2006.182.07:59:00.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.07:59:00.87#ibcon#[27=USB\r\n] 2006.182.07:59:00.87#ibcon#*before write, iclass 24, count 0 2006.182.07:59:00.87#ibcon#enter sib2, iclass 24, count 0 2006.182.07:59:00.87#ibcon#flushed, iclass 24, count 0 2006.182.07:59:00.87#ibcon#about to write, iclass 24, count 0 2006.182.07:59:00.87#ibcon#wrote, iclass 24, count 0 2006.182.07:59:00.87#ibcon#about to read 3, iclass 24, count 0 2006.182.07:59:00.90#ibcon#read 3, iclass 24, count 0 2006.182.07:59:00.90#ibcon#about to read 4, iclass 24, count 0 2006.182.07:59:00.90#ibcon#read 4, iclass 24, count 0 2006.182.07:59:00.90#ibcon#about to read 5, iclass 24, count 0 2006.182.07:59:00.90#ibcon#read 5, iclass 24, count 0 2006.182.07:59:00.90#ibcon#about to read 6, iclass 24, count 0 2006.182.07:59:00.90#ibcon#read 6, iclass 24, count 0 2006.182.07:59:00.90#ibcon#end of sib2, iclass 24, count 0 2006.182.07:59:00.90#ibcon#*after write, iclass 24, count 0 2006.182.07:59:00.90#ibcon#*before return 0, iclass 24, count 0 2006.182.07:59:00.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:59:00.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.07:59:00.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.07:59:00.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.07:59:00.90$vc4f8/vblo=2,640.99 2006.182.07:59:00.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.07:59:00.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.07:59:00.90#ibcon#ireg 17 cls_cnt 0 2006.182.07:59:00.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:59:00.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:59:00.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:59:00.90#ibcon#enter wrdev, iclass 26, count 0 2006.182.07:59:00.90#ibcon#first serial, iclass 26, count 0 2006.182.07:59:00.90#ibcon#enter sib2, iclass 26, count 0 2006.182.07:59:00.90#ibcon#flushed, iclass 26, count 0 2006.182.07:59:00.90#ibcon#about to write, iclass 26, count 0 2006.182.07:59:00.90#ibcon#wrote, iclass 26, count 0 2006.182.07:59:00.90#ibcon#about to read 3, iclass 26, count 0 2006.182.07:59:00.92#ibcon#read 3, iclass 26, count 0 2006.182.07:59:00.92#ibcon#about to read 4, iclass 26, count 0 2006.182.07:59:00.92#ibcon#read 4, iclass 26, count 0 2006.182.07:59:00.92#ibcon#about to read 5, iclass 26, count 0 2006.182.07:59:00.92#ibcon#read 5, iclass 26, count 0 2006.182.07:59:00.92#ibcon#about to read 6, iclass 26, count 0 2006.182.07:59:00.92#ibcon#read 6, iclass 26, count 0 2006.182.07:59:00.92#ibcon#end of sib2, iclass 26, count 0 2006.182.07:59:00.92#ibcon#*mode == 0, iclass 26, count 0 2006.182.07:59:00.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.07:59:00.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.07:59:00.92#ibcon#*before write, iclass 26, count 0 2006.182.07:59:00.92#ibcon#enter sib2, iclass 26, count 0 2006.182.07:59:00.92#ibcon#flushed, iclass 26, count 0 2006.182.07:59:00.92#ibcon#about to write, iclass 26, count 0 2006.182.07:59:00.92#ibcon#wrote, iclass 26, count 0 2006.182.07:59:00.92#ibcon#about to read 3, iclass 26, count 0 2006.182.07:59:00.96#ibcon#read 3, iclass 26, count 0 2006.182.07:59:00.96#ibcon#about to read 4, iclass 26, count 0 2006.182.07:59:00.96#ibcon#read 4, iclass 26, count 0 2006.182.07:59:00.96#ibcon#about to read 5, iclass 26, count 0 2006.182.07:59:00.96#ibcon#read 5, iclass 26, count 0 2006.182.07:59:00.96#ibcon#about to read 6, iclass 26, count 0 2006.182.07:59:00.96#ibcon#read 6, iclass 26, count 0 2006.182.07:59:00.96#ibcon#end of sib2, iclass 26, count 0 2006.182.07:59:00.96#ibcon#*after write, iclass 26, count 0 2006.182.07:59:00.96#ibcon#*before return 0, iclass 26, count 0 2006.182.07:59:00.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:59:00.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.07:59:00.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.07:59:00.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.07:59:00.96$vc4f8/vb=2,4 2006.182.07:59:00.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.07:59:00.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.07:59:00.96#ibcon#ireg 11 cls_cnt 2 2006.182.07:59:00.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:59:01.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:59:01.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:59:01.03#ibcon#enter wrdev, iclass 28, count 2 2006.182.07:59:01.03#ibcon#first serial, iclass 28, count 2 2006.182.07:59:01.03#ibcon#enter sib2, iclass 28, count 2 2006.182.07:59:01.03#ibcon#flushed, iclass 28, count 2 2006.182.07:59:01.03#ibcon#about to write, iclass 28, count 2 2006.182.07:59:01.03#ibcon#wrote, iclass 28, count 2 2006.182.07:59:01.03#ibcon#about to read 3, iclass 28, count 2 2006.182.07:59:01.04#ibcon#read 3, iclass 28, count 2 2006.182.07:59:01.04#ibcon#about to read 4, iclass 28, count 2 2006.182.07:59:01.04#ibcon#read 4, iclass 28, count 2 2006.182.07:59:01.04#ibcon#about to read 5, iclass 28, count 2 2006.182.07:59:01.04#ibcon#read 5, iclass 28, count 2 2006.182.07:59:01.04#ibcon#about to read 6, iclass 28, count 2 2006.182.07:59:01.04#ibcon#read 6, iclass 28, count 2 2006.182.07:59:01.04#ibcon#end of sib2, iclass 28, count 2 2006.182.07:59:01.04#ibcon#*mode == 0, iclass 28, count 2 2006.182.07:59:01.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.07:59:01.04#ibcon#[27=AT02-04\r\n] 2006.182.07:59:01.04#ibcon#*before write, iclass 28, count 2 2006.182.07:59:01.04#ibcon#enter sib2, iclass 28, count 2 2006.182.07:59:01.04#ibcon#flushed, iclass 28, count 2 2006.182.07:59:01.04#ibcon#about to write, iclass 28, count 2 2006.182.07:59:01.04#ibcon#wrote, iclass 28, count 2 2006.182.07:59:01.04#ibcon#about to read 3, iclass 28, count 2 2006.182.07:59:01.07#ibcon#read 3, iclass 28, count 2 2006.182.07:59:01.07#ibcon#about to read 4, iclass 28, count 2 2006.182.07:59:01.07#ibcon#read 4, iclass 28, count 2 2006.182.07:59:01.07#ibcon#about to read 5, iclass 28, count 2 2006.182.07:59:01.07#ibcon#read 5, iclass 28, count 2 2006.182.07:59:01.07#ibcon#about to read 6, iclass 28, count 2 2006.182.07:59:01.07#ibcon#read 6, iclass 28, count 2 2006.182.07:59:01.07#ibcon#end of sib2, iclass 28, count 2 2006.182.07:59:01.07#ibcon#*after write, iclass 28, count 2 2006.182.07:59:01.07#ibcon#*before return 0, iclass 28, count 2 2006.182.07:59:01.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:59:01.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.07:59:01.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.07:59:01.07#ibcon#ireg 7 cls_cnt 0 2006.182.07:59:01.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:59:01.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:59:01.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:59:01.19#ibcon#enter wrdev, iclass 28, count 0 2006.182.07:59:01.19#ibcon#first serial, iclass 28, count 0 2006.182.07:59:01.19#ibcon#enter sib2, iclass 28, count 0 2006.182.07:59:01.19#ibcon#flushed, iclass 28, count 0 2006.182.07:59:01.19#ibcon#about to write, iclass 28, count 0 2006.182.07:59:01.19#ibcon#wrote, iclass 28, count 0 2006.182.07:59:01.19#ibcon#about to read 3, iclass 28, count 0 2006.182.07:59:01.23#ibcon#read 3, iclass 28, count 0 2006.182.07:59:01.23#ibcon#about to read 4, iclass 28, count 0 2006.182.07:59:01.23#ibcon#read 4, iclass 28, count 0 2006.182.07:59:01.23#ibcon#about to read 5, iclass 28, count 0 2006.182.07:59:01.23#ibcon#read 5, iclass 28, count 0 2006.182.07:59:01.23#ibcon#about to read 6, iclass 28, count 0 2006.182.07:59:01.23#ibcon#read 6, iclass 28, count 0 2006.182.07:59:01.23#ibcon#end of sib2, iclass 28, count 0 2006.182.07:59:01.23#ibcon#*mode == 0, iclass 28, count 0 2006.182.07:59:01.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.07:59:01.23#ibcon#[27=USB\r\n] 2006.182.07:59:01.23#ibcon#*before write, iclass 28, count 0 2006.182.07:59:01.23#ibcon#enter sib2, iclass 28, count 0 2006.182.07:59:01.23#ibcon#flushed, iclass 28, count 0 2006.182.07:59:01.23#ibcon#about to write, iclass 28, count 0 2006.182.07:59:01.23#ibcon#wrote, iclass 28, count 0 2006.182.07:59:01.23#ibcon#about to read 3, iclass 28, count 0 2006.182.07:59:01.25#ibcon#read 3, iclass 28, count 0 2006.182.07:59:01.25#ibcon#about to read 4, iclass 28, count 0 2006.182.07:59:01.25#ibcon#read 4, iclass 28, count 0 2006.182.07:59:01.25#ibcon#about to read 5, iclass 28, count 0 2006.182.07:59:01.25#ibcon#read 5, iclass 28, count 0 2006.182.07:59:01.25#ibcon#about to read 6, iclass 28, count 0 2006.182.07:59:01.25#ibcon#read 6, iclass 28, count 0 2006.182.07:59:01.25#ibcon#end of sib2, iclass 28, count 0 2006.182.07:59:01.25#ibcon#*after write, iclass 28, count 0 2006.182.07:59:01.25#ibcon#*before return 0, iclass 28, count 0 2006.182.07:59:01.25#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:59:01.25#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.07:59:01.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.07:59:01.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.07:59:01.25$vc4f8/vblo=3,656.99 2006.182.07:59:01.25#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.07:59:01.25#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.07:59:01.25#ibcon#ireg 17 cls_cnt 0 2006.182.07:59:01.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:59:01.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:59:01.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:59:01.25#ibcon#enter wrdev, iclass 30, count 0 2006.182.07:59:01.25#ibcon#first serial, iclass 30, count 0 2006.182.07:59:01.25#ibcon#enter sib2, iclass 30, count 0 2006.182.07:59:01.25#ibcon#flushed, iclass 30, count 0 2006.182.07:59:01.25#ibcon#about to write, iclass 30, count 0 2006.182.07:59:01.25#ibcon#wrote, iclass 30, count 0 2006.182.07:59:01.25#ibcon#about to read 3, iclass 30, count 0 2006.182.07:59:01.27#ibcon#read 3, iclass 30, count 0 2006.182.07:59:01.27#ibcon#about to read 4, iclass 30, count 0 2006.182.07:59:01.27#ibcon#read 4, iclass 30, count 0 2006.182.07:59:01.27#ibcon#about to read 5, iclass 30, count 0 2006.182.07:59:01.27#ibcon#read 5, iclass 30, count 0 2006.182.07:59:01.27#ibcon#about to read 6, iclass 30, count 0 2006.182.07:59:01.27#ibcon#read 6, iclass 30, count 0 2006.182.07:59:01.27#ibcon#end of sib2, iclass 30, count 0 2006.182.07:59:01.27#ibcon#*mode == 0, iclass 30, count 0 2006.182.07:59:01.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.07:59:01.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.07:59:01.27#ibcon#*before write, iclass 30, count 0 2006.182.07:59:01.27#ibcon#enter sib2, iclass 30, count 0 2006.182.07:59:01.27#ibcon#flushed, iclass 30, count 0 2006.182.07:59:01.27#ibcon#about to write, iclass 30, count 0 2006.182.07:59:01.27#ibcon#wrote, iclass 30, count 0 2006.182.07:59:01.27#ibcon#about to read 3, iclass 30, count 0 2006.182.07:59:01.31#ibcon#read 3, iclass 30, count 0 2006.182.07:59:01.31#ibcon#about to read 4, iclass 30, count 0 2006.182.07:59:01.31#ibcon#read 4, iclass 30, count 0 2006.182.07:59:01.31#ibcon#about to read 5, iclass 30, count 0 2006.182.07:59:01.31#ibcon#read 5, iclass 30, count 0 2006.182.07:59:01.31#ibcon#about to read 6, iclass 30, count 0 2006.182.07:59:01.31#ibcon#read 6, iclass 30, count 0 2006.182.07:59:01.31#ibcon#end of sib2, iclass 30, count 0 2006.182.07:59:01.31#ibcon#*after write, iclass 30, count 0 2006.182.07:59:01.31#ibcon#*before return 0, iclass 30, count 0 2006.182.07:59:01.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:59:01.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.07:59:01.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.07:59:01.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.07:59:01.31$vc4f8/vb=3,4 2006.182.07:59:01.31#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.07:59:01.31#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.07:59:01.31#ibcon#ireg 11 cls_cnt 2 2006.182.07:59:01.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:59:01.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:59:01.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:59:01.37#ibcon#enter wrdev, iclass 32, count 2 2006.182.07:59:01.37#ibcon#first serial, iclass 32, count 2 2006.182.07:59:01.37#ibcon#enter sib2, iclass 32, count 2 2006.182.07:59:01.37#ibcon#flushed, iclass 32, count 2 2006.182.07:59:01.37#ibcon#about to write, iclass 32, count 2 2006.182.07:59:01.37#ibcon#wrote, iclass 32, count 2 2006.182.07:59:01.37#ibcon#about to read 3, iclass 32, count 2 2006.182.07:59:01.39#ibcon#read 3, iclass 32, count 2 2006.182.07:59:01.39#ibcon#about to read 4, iclass 32, count 2 2006.182.07:59:01.39#ibcon#read 4, iclass 32, count 2 2006.182.07:59:01.39#ibcon#about to read 5, iclass 32, count 2 2006.182.07:59:01.39#ibcon#read 5, iclass 32, count 2 2006.182.07:59:01.39#ibcon#about to read 6, iclass 32, count 2 2006.182.07:59:01.39#ibcon#read 6, iclass 32, count 2 2006.182.07:59:01.39#ibcon#end of sib2, iclass 32, count 2 2006.182.07:59:01.39#ibcon#*mode == 0, iclass 32, count 2 2006.182.07:59:01.39#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.07:59:01.39#ibcon#[27=AT03-04\r\n] 2006.182.07:59:01.39#ibcon#*before write, iclass 32, count 2 2006.182.07:59:01.39#ibcon#enter sib2, iclass 32, count 2 2006.182.07:59:01.39#ibcon#flushed, iclass 32, count 2 2006.182.07:59:01.39#ibcon#about to write, iclass 32, count 2 2006.182.07:59:01.39#ibcon#wrote, iclass 32, count 2 2006.182.07:59:01.39#ibcon#about to read 3, iclass 32, count 2 2006.182.07:59:01.42#ibcon#read 3, iclass 32, count 2 2006.182.07:59:01.42#ibcon#about to read 4, iclass 32, count 2 2006.182.07:59:01.42#ibcon#read 4, iclass 32, count 2 2006.182.07:59:01.42#ibcon#about to read 5, iclass 32, count 2 2006.182.07:59:01.42#ibcon#read 5, iclass 32, count 2 2006.182.07:59:01.42#ibcon#about to read 6, iclass 32, count 2 2006.182.07:59:01.42#ibcon#read 6, iclass 32, count 2 2006.182.07:59:01.42#ibcon#end of sib2, iclass 32, count 2 2006.182.07:59:01.42#ibcon#*after write, iclass 32, count 2 2006.182.07:59:01.42#ibcon#*before return 0, iclass 32, count 2 2006.182.07:59:01.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:59:01.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.07:59:01.42#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.07:59:01.42#ibcon#ireg 7 cls_cnt 0 2006.182.07:59:01.42#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:59:01.54#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:59:01.54#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:59:01.54#ibcon#enter wrdev, iclass 32, count 0 2006.182.07:59:01.54#ibcon#first serial, iclass 32, count 0 2006.182.07:59:01.54#ibcon#enter sib2, iclass 32, count 0 2006.182.07:59:01.54#ibcon#flushed, iclass 32, count 0 2006.182.07:59:01.54#ibcon#about to write, iclass 32, count 0 2006.182.07:59:01.54#ibcon#wrote, iclass 32, count 0 2006.182.07:59:01.54#ibcon#about to read 3, iclass 32, count 0 2006.182.07:59:01.56#ibcon#read 3, iclass 32, count 0 2006.182.07:59:01.56#ibcon#about to read 4, iclass 32, count 0 2006.182.07:59:01.56#ibcon#read 4, iclass 32, count 0 2006.182.07:59:01.56#ibcon#about to read 5, iclass 32, count 0 2006.182.07:59:01.56#ibcon#read 5, iclass 32, count 0 2006.182.07:59:01.56#ibcon#about to read 6, iclass 32, count 0 2006.182.07:59:01.56#ibcon#read 6, iclass 32, count 0 2006.182.07:59:01.56#ibcon#end of sib2, iclass 32, count 0 2006.182.07:59:01.56#ibcon#*mode == 0, iclass 32, count 0 2006.182.07:59:01.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.07:59:01.56#ibcon#[27=USB\r\n] 2006.182.07:59:01.56#ibcon#*before write, iclass 32, count 0 2006.182.07:59:01.56#ibcon#enter sib2, iclass 32, count 0 2006.182.07:59:01.56#ibcon#flushed, iclass 32, count 0 2006.182.07:59:01.56#ibcon#about to write, iclass 32, count 0 2006.182.07:59:01.56#ibcon#wrote, iclass 32, count 0 2006.182.07:59:01.56#ibcon#about to read 3, iclass 32, count 0 2006.182.07:59:01.59#ibcon#read 3, iclass 32, count 0 2006.182.07:59:01.59#ibcon#about to read 4, iclass 32, count 0 2006.182.07:59:01.59#ibcon#read 4, iclass 32, count 0 2006.182.07:59:01.59#ibcon#about to read 5, iclass 32, count 0 2006.182.07:59:01.59#ibcon#read 5, iclass 32, count 0 2006.182.07:59:01.59#ibcon#about to read 6, iclass 32, count 0 2006.182.07:59:01.59#ibcon#read 6, iclass 32, count 0 2006.182.07:59:01.59#ibcon#end of sib2, iclass 32, count 0 2006.182.07:59:01.59#ibcon#*after write, iclass 32, count 0 2006.182.07:59:01.59#ibcon#*before return 0, iclass 32, count 0 2006.182.07:59:01.59#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:59:01.59#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.07:59:01.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.07:59:01.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.07:59:01.59$vc4f8/vblo=4,712.99 2006.182.07:59:01.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.07:59:01.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.07:59:01.59#ibcon#ireg 17 cls_cnt 0 2006.182.07:59:01.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:59:01.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:59:01.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:59:01.59#ibcon#enter wrdev, iclass 35, count 0 2006.182.07:59:01.59#ibcon#first serial, iclass 35, count 0 2006.182.07:59:01.59#ibcon#enter sib2, iclass 35, count 0 2006.182.07:59:01.59#ibcon#flushed, iclass 35, count 0 2006.182.07:59:01.59#ibcon#about to write, iclass 35, count 0 2006.182.07:59:01.59#ibcon#wrote, iclass 35, count 0 2006.182.07:59:01.59#ibcon#about to read 3, iclass 35, count 0 2006.182.07:59:01.61#ibcon#read 3, iclass 35, count 0 2006.182.07:59:01.61#ibcon#about to read 4, iclass 35, count 0 2006.182.07:59:01.61#ibcon#read 4, iclass 35, count 0 2006.182.07:59:01.61#ibcon#about to read 5, iclass 35, count 0 2006.182.07:59:01.61#ibcon#read 5, iclass 35, count 0 2006.182.07:59:01.61#ibcon#about to read 6, iclass 35, count 0 2006.182.07:59:01.61#ibcon#read 6, iclass 35, count 0 2006.182.07:59:01.61#ibcon#end of sib2, iclass 35, count 0 2006.182.07:59:01.61#ibcon#*mode == 0, iclass 35, count 0 2006.182.07:59:01.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.07:59:01.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.07:59:01.61#ibcon#*before write, iclass 35, count 0 2006.182.07:59:01.61#ibcon#enter sib2, iclass 35, count 0 2006.182.07:59:01.61#ibcon#flushed, iclass 35, count 0 2006.182.07:59:01.61#ibcon#about to write, iclass 35, count 0 2006.182.07:59:01.61#ibcon#wrote, iclass 35, count 0 2006.182.07:59:01.61#ibcon#about to read 3, iclass 35, count 0 2006.182.07:59:01.62#abcon#<5=/07 0.7 1.7 27.74 811002.8\r\n> 2006.182.07:59:01.64#abcon#{5=INTERFACE CLEAR} 2006.182.07:59:01.65#ibcon#read 3, iclass 35, count 0 2006.182.07:59:01.65#ibcon#about to read 4, iclass 35, count 0 2006.182.07:59:01.65#ibcon#read 4, iclass 35, count 0 2006.182.07:59:01.65#ibcon#about to read 5, iclass 35, count 0 2006.182.07:59:01.65#ibcon#read 5, iclass 35, count 0 2006.182.07:59:01.65#ibcon#about to read 6, iclass 35, count 0 2006.182.07:59:01.65#ibcon#read 6, iclass 35, count 0 2006.182.07:59:01.65#ibcon#end of sib2, iclass 35, count 0 2006.182.07:59:01.65#ibcon#*after write, iclass 35, count 0 2006.182.07:59:01.65#ibcon#*before return 0, iclass 35, count 0 2006.182.07:59:01.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:59:01.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.07:59:01.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.07:59:01.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.07:59:01.65$vc4f8/vb=4,4 2006.182.07:59:01.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.07:59:01.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.07:59:01.65#ibcon#ireg 11 cls_cnt 2 2006.182.07:59:01.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:59:01.70#abcon#[5=S1D000X0/0*\r\n] 2006.182.07:59:01.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:59:01.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:59:01.71#ibcon#enter wrdev, iclass 39, count 2 2006.182.07:59:01.71#ibcon#first serial, iclass 39, count 2 2006.182.07:59:01.71#ibcon#enter sib2, iclass 39, count 2 2006.182.07:59:01.71#ibcon#flushed, iclass 39, count 2 2006.182.07:59:01.71#ibcon#about to write, iclass 39, count 2 2006.182.07:59:01.71#ibcon#wrote, iclass 39, count 2 2006.182.07:59:01.71#ibcon#about to read 3, iclass 39, count 2 2006.182.07:59:01.73#ibcon#read 3, iclass 39, count 2 2006.182.07:59:01.73#ibcon#about to read 4, iclass 39, count 2 2006.182.07:59:01.73#ibcon#read 4, iclass 39, count 2 2006.182.07:59:01.73#ibcon#about to read 5, iclass 39, count 2 2006.182.07:59:01.73#ibcon#read 5, iclass 39, count 2 2006.182.07:59:01.73#ibcon#about to read 6, iclass 39, count 2 2006.182.07:59:01.73#ibcon#read 6, iclass 39, count 2 2006.182.07:59:01.73#ibcon#end of sib2, iclass 39, count 2 2006.182.07:59:01.73#ibcon#*mode == 0, iclass 39, count 2 2006.182.07:59:01.73#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.07:59:01.73#ibcon#[27=AT04-04\r\n] 2006.182.07:59:01.73#ibcon#*before write, iclass 39, count 2 2006.182.07:59:01.73#ibcon#enter sib2, iclass 39, count 2 2006.182.07:59:01.73#ibcon#flushed, iclass 39, count 2 2006.182.07:59:01.73#ibcon#about to write, iclass 39, count 2 2006.182.07:59:01.73#ibcon#wrote, iclass 39, count 2 2006.182.07:59:01.73#ibcon#about to read 3, iclass 39, count 2 2006.182.07:59:01.76#ibcon#read 3, iclass 39, count 2 2006.182.07:59:01.76#ibcon#about to read 4, iclass 39, count 2 2006.182.07:59:01.76#ibcon#read 4, iclass 39, count 2 2006.182.07:59:01.76#ibcon#about to read 5, iclass 39, count 2 2006.182.07:59:01.76#ibcon#read 5, iclass 39, count 2 2006.182.07:59:01.76#ibcon#about to read 6, iclass 39, count 2 2006.182.07:59:01.76#ibcon#read 6, iclass 39, count 2 2006.182.07:59:01.76#ibcon#end of sib2, iclass 39, count 2 2006.182.07:59:01.76#ibcon#*after write, iclass 39, count 2 2006.182.07:59:01.76#ibcon#*before return 0, iclass 39, count 2 2006.182.07:59:01.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:59:01.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.07:59:01.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.07:59:01.76#ibcon#ireg 7 cls_cnt 0 2006.182.07:59:01.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:59:01.88#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:59:01.88#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:59:01.88#ibcon#enter wrdev, iclass 39, count 0 2006.182.07:59:01.88#ibcon#first serial, iclass 39, count 0 2006.182.07:59:01.88#ibcon#enter sib2, iclass 39, count 0 2006.182.07:59:01.88#ibcon#flushed, iclass 39, count 0 2006.182.07:59:01.88#ibcon#about to write, iclass 39, count 0 2006.182.07:59:01.88#ibcon#wrote, iclass 39, count 0 2006.182.07:59:01.88#ibcon#about to read 3, iclass 39, count 0 2006.182.07:59:01.90#ibcon#read 3, iclass 39, count 0 2006.182.07:59:01.90#ibcon#about to read 4, iclass 39, count 0 2006.182.07:59:01.90#ibcon#read 4, iclass 39, count 0 2006.182.07:59:01.90#ibcon#about to read 5, iclass 39, count 0 2006.182.07:59:01.90#ibcon#read 5, iclass 39, count 0 2006.182.07:59:01.90#ibcon#about to read 6, iclass 39, count 0 2006.182.07:59:01.90#ibcon#read 6, iclass 39, count 0 2006.182.07:59:01.90#ibcon#end of sib2, iclass 39, count 0 2006.182.07:59:01.90#ibcon#*mode == 0, iclass 39, count 0 2006.182.07:59:01.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.07:59:01.90#ibcon#[27=USB\r\n] 2006.182.07:59:01.90#ibcon#*before write, iclass 39, count 0 2006.182.07:59:01.90#ibcon#enter sib2, iclass 39, count 0 2006.182.07:59:01.90#ibcon#flushed, iclass 39, count 0 2006.182.07:59:01.90#ibcon#about to write, iclass 39, count 0 2006.182.07:59:01.90#ibcon#wrote, iclass 39, count 0 2006.182.07:59:01.90#ibcon#about to read 3, iclass 39, count 0 2006.182.07:59:01.93#ibcon#read 3, iclass 39, count 0 2006.182.07:59:01.93#ibcon#about to read 4, iclass 39, count 0 2006.182.07:59:01.93#ibcon#read 4, iclass 39, count 0 2006.182.07:59:01.93#ibcon#about to read 5, iclass 39, count 0 2006.182.07:59:01.93#ibcon#read 5, iclass 39, count 0 2006.182.07:59:01.93#ibcon#about to read 6, iclass 39, count 0 2006.182.07:59:01.93#ibcon#read 6, iclass 39, count 0 2006.182.07:59:01.93#ibcon#end of sib2, iclass 39, count 0 2006.182.07:59:01.93#ibcon#*after write, iclass 39, count 0 2006.182.07:59:01.93#ibcon#*before return 0, iclass 39, count 0 2006.182.07:59:01.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:59:01.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.07:59:01.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.07:59:01.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.07:59:01.93$vc4f8/vblo=5,744.99 2006.182.07:59:01.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.07:59:01.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.07:59:01.93#ibcon#ireg 17 cls_cnt 0 2006.182.07:59:01.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:59:01.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:59:01.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:59:01.93#ibcon#enter wrdev, iclass 4, count 0 2006.182.07:59:01.93#ibcon#first serial, iclass 4, count 0 2006.182.07:59:01.93#ibcon#enter sib2, iclass 4, count 0 2006.182.07:59:01.93#ibcon#flushed, iclass 4, count 0 2006.182.07:59:01.93#ibcon#about to write, iclass 4, count 0 2006.182.07:59:01.93#ibcon#wrote, iclass 4, count 0 2006.182.07:59:01.93#ibcon#about to read 3, iclass 4, count 0 2006.182.07:59:01.96#ibcon#read 3, iclass 4, count 0 2006.182.07:59:01.96#ibcon#about to read 4, iclass 4, count 0 2006.182.07:59:01.96#ibcon#read 4, iclass 4, count 0 2006.182.07:59:01.96#ibcon#about to read 5, iclass 4, count 0 2006.182.07:59:01.96#ibcon#read 5, iclass 4, count 0 2006.182.07:59:01.96#ibcon#about to read 6, iclass 4, count 0 2006.182.07:59:01.96#ibcon#read 6, iclass 4, count 0 2006.182.07:59:01.96#ibcon#end of sib2, iclass 4, count 0 2006.182.07:59:01.96#ibcon#*mode == 0, iclass 4, count 0 2006.182.07:59:01.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.07:59:01.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.07:59:01.96#ibcon#*before write, iclass 4, count 0 2006.182.07:59:01.96#ibcon#enter sib2, iclass 4, count 0 2006.182.07:59:01.96#ibcon#flushed, iclass 4, count 0 2006.182.07:59:01.96#ibcon#about to write, iclass 4, count 0 2006.182.07:59:01.96#ibcon#wrote, iclass 4, count 0 2006.182.07:59:01.96#ibcon#about to read 3, iclass 4, count 0 2006.182.07:59:02.00#ibcon#read 3, iclass 4, count 0 2006.182.07:59:02.00#ibcon#about to read 4, iclass 4, count 0 2006.182.07:59:02.00#ibcon#read 4, iclass 4, count 0 2006.182.07:59:02.00#ibcon#about to read 5, iclass 4, count 0 2006.182.07:59:02.00#ibcon#read 5, iclass 4, count 0 2006.182.07:59:02.00#ibcon#about to read 6, iclass 4, count 0 2006.182.07:59:02.00#ibcon#read 6, iclass 4, count 0 2006.182.07:59:02.00#ibcon#end of sib2, iclass 4, count 0 2006.182.07:59:02.00#ibcon#*after write, iclass 4, count 0 2006.182.07:59:02.00#ibcon#*before return 0, iclass 4, count 0 2006.182.07:59:02.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:59:02.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.07:59:02.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.07:59:02.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.07:59:02.00$vc4f8/vb=5,4 2006.182.07:59:02.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.07:59:02.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.07:59:02.00#ibcon#ireg 11 cls_cnt 2 2006.182.07:59:02.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:59:02.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:59:02.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:59:02.05#ibcon#enter wrdev, iclass 6, count 2 2006.182.07:59:02.05#ibcon#first serial, iclass 6, count 2 2006.182.07:59:02.05#ibcon#enter sib2, iclass 6, count 2 2006.182.07:59:02.05#ibcon#flushed, iclass 6, count 2 2006.182.07:59:02.05#ibcon#about to write, iclass 6, count 2 2006.182.07:59:02.05#ibcon#wrote, iclass 6, count 2 2006.182.07:59:02.05#ibcon#about to read 3, iclass 6, count 2 2006.182.07:59:02.07#ibcon#read 3, iclass 6, count 2 2006.182.07:59:02.07#ibcon#about to read 4, iclass 6, count 2 2006.182.07:59:02.07#ibcon#read 4, iclass 6, count 2 2006.182.07:59:02.07#ibcon#about to read 5, iclass 6, count 2 2006.182.07:59:02.07#ibcon#read 5, iclass 6, count 2 2006.182.07:59:02.07#ibcon#about to read 6, iclass 6, count 2 2006.182.07:59:02.07#ibcon#read 6, iclass 6, count 2 2006.182.07:59:02.07#ibcon#end of sib2, iclass 6, count 2 2006.182.07:59:02.07#ibcon#*mode == 0, iclass 6, count 2 2006.182.07:59:02.07#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.07:59:02.07#ibcon#[27=AT05-04\r\n] 2006.182.07:59:02.07#ibcon#*before write, iclass 6, count 2 2006.182.07:59:02.07#ibcon#enter sib2, iclass 6, count 2 2006.182.07:59:02.07#ibcon#flushed, iclass 6, count 2 2006.182.07:59:02.07#ibcon#about to write, iclass 6, count 2 2006.182.07:59:02.07#ibcon#wrote, iclass 6, count 2 2006.182.07:59:02.07#ibcon#about to read 3, iclass 6, count 2 2006.182.07:59:02.10#ibcon#read 3, iclass 6, count 2 2006.182.07:59:02.10#ibcon#about to read 4, iclass 6, count 2 2006.182.07:59:02.10#ibcon#read 4, iclass 6, count 2 2006.182.07:59:02.10#ibcon#about to read 5, iclass 6, count 2 2006.182.07:59:02.10#ibcon#read 5, iclass 6, count 2 2006.182.07:59:02.10#ibcon#about to read 6, iclass 6, count 2 2006.182.07:59:02.10#ibcon#read 6, iclass 6, count 2 2006.182.07:59:02.10#ibcon#end of sib2, iclass 6, count 2 2006.182.07:59:02.10#ibcon#*after write, iclass 6, count 2 2006.182.07:59:02.10#ibcon#*before return 0, iclass 6, count 2 2006.182.07:59:02.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:59:02.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.07:59:02.10#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.07:59:02.10#ibcon#ireg 7 cls_cnt 0 2006.182.07:59:02.10#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:59:02.22#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:59:02.22#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:59:02.22#ibcon#enter wrdev, iclass 6, count 0 2006.182.07:59:02.22#ibcon#first serial, iclass 6, count 0 2006.182.07:59:02.22#ibcon#enter sib2, iclass 6, count 0 2006.182.07:59:02.22#ibcon#flushed, iclass 6, count 0 2006.182.07:59:02.22#ibcon#about to write, iclass 6, count 0 2006.182.07:59:02.22#ibcon#wrote, iclass 6, count 0 2006.182.07:59:02.22#ibcon#about to read 3, iclass 6, count 0 2006.182.07:59:02.24#ibcon#read 3, iclass 6, count 0 2006.182.07:59:02.24#ibcon#about to read 4, iclass 6, count 0 2006.182.07:59:02.24#ibcon#read 4, iclass 6, count 0 2006.182.07:59:02.24#ibcon#about to read 5, iclass 6, count 0 2006.182.07:59:02.24#ibcon#read 5, iclass 6, count 0 2006.182.07:59:02.24#ibcon#about to read 6, iclass 6, count 0 2006.182.07:59:02.24#ibcon#read 6, iclass 6, count 0 2006.182.07:59:02.24#ibcon#end of sib2, iclass 6, count 0 2006.182.07:59:02.24#ibcon#*mode == 0, iclass 6, count 0 2006.182.07:59:02.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.07:59:02.24#ibcon#[27=USB\r\n] 2006.182.07:59:02.24#ibcon#*before write, iclass 6, count 0 2006.182.07:59:02.24#ibcon#enter sib2, iclass 6, count 0 2006.182.07:59:02.24#ibcon#flushed, iclass 6, count 0 2006.182.07:59:02.24#ibcon#about to write, iclass 6, count 0 2006.182.07:59:02.24#ibcon#wrote, iclass 6, count 0 2006.182.07:59:02.24#ibcon#about to read 3, iclass 6, count 0 2006.182.07:59:02.27#ibcon#read 3, iclass 6, count 0 2006.182.07:59:02.27#ibcon#about to read 4, iclass 6, count 0 2006.182.07:59:02.27#ibcon#read 4, iclass 6, count 0 2006.182.07:59:02.27#ibcon#about to read 5, iclass 6, count 0 2006.182.07:59:02.27#ibcon#read 5, iclass 6, count 0 2006.182.07:59:02.27#ibcon#about to read 6, iclass 6, count 0 2006.182.07:59:02.27#ibcon#read 6, iclass 6, count 0 2006.182.07:59:02.27#ibcon#end of sib2, iclass 6, count 0 2006.182.07:59:02.27#ibcon#*after write, iclass 6, count 0 2006.182.07:59:02.27#ibcon#*before return 0, iclass 6, count 0 2006.182.07:59:02.27#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:59:02.27#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.07:59:02.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.07:59:02.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.07:59:02.27$vc4f8/vblo=6,752.99 2006.182.07:59:02.27#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.07:59:02.27#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.07:59:02.27#ibcon#ireg 17 cls_cnt 0 2006.182.07:59:02.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:59:02.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:59:02.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:59:02.27#ibcon#enter wrdev, iclass 10, count 0 2006.182.07:59:02.27#ibcon#first serial, iclass 10, count 0 2006.182.07:59:02.27#ibcon#enter sib2, iclass 10, count 0 2006.182.07:59:02.27#ibcon#flushed, iclass 10, count 0 2006.182.07:59:02.27#ibcon#about to write, iclass 10, count 0 2006.182.07:59:02.27#ibcon#wrote, iclass 10, count 0 2006.182.07:59:02.27#ibcon#about to read 3, iclass 10, count 0 2006.182.07:59:02.29#ibcon#read 3, iclass 10, count 0 2006.182.07:59:02.29#ibcon#about to read 4, iclass 10, count 0 2006.182.07:59:02.29#ibcon#read 4, iclass 10, count 0 2006.182.07:59:02.29#ibcon#about to read 5, iclass 10, count 0 2006.182.07:59:02.29#ibcon#read 5, iclass 10, count 0 2006.182.07:59:02.29#ibcon#about to read 6, iclass 10, count 0 2006.182.07:59:02.29#ibcon#read 6, iclass 10, count 0 2006.182.07:59:02.29#ibcon#end of sib2, iclass 10, count 0 2006.182.07:59:02.29#ibcon#*mode == 0, iclass 10, count 0 2006.182.07:59:02.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.07:59:02.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.07:59:02.29#ibcon#*before write, iclass 10, count 0 2006.182.07:59:02.29#ibcon#enter sib2, iclass 10, count 0 2006.182.07:59:02.29#ibcon#flushed, iclass 10, count 0 2006.182.07:59:02.29#ibcon#about to write, iclass 10, count 0 2006.182.07:59:02.29#ibcon#wrote, iclass 10, count 0 2006.182.07:59:02.29#ibcon#about to read 3, iclass 10, count 0 2006.182.07:59:02.33#ibcon#read 3, iclass 10, count 0 2006.182.07:59:02.33#ibcon#about to read 4, iclass 10, count 0 2006.182.07:59:02.33#ibcon#read 4, iclass 10, count 0 2006.182.07:59:02.33#ibcon#about to read 5, iclass 10, count 0 2006.182.07:59:02.33#ibcon#read 5, iclass 10, count 0 2006.182.07:59:02.33#ibcon#about to read 6, iclass 10, count 0 2006.182.07:59:02.33#ibcon#read 6, iclass 10, count 0 2006.182.07:59:02.33#ibcon#end of sib2, iclass 10, count 0 2006.182.07:59:02.33#ibcon#*after write, iclass 10, count 0 2006.182.07:59:02.33#ibcon#*before return 0, iclass 10, count 0 2006.182.07:59:02.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:59:02.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.07:59:02.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.07:59:02.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.07:59:02.33$vc4f8/vb=6,4 2006.182.07:59:02.33#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.07:59:02.33#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.07:59:02.33#ibcon#ireg 11 cls_cnt 2 2006.182.07:59:02.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:59:02.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:59:02.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:59:02.39#ibcon#enter wrdev, iclass 12, count 2 2006.182.07:59:02.39#ibcon#first serial, iclass 12, count 2 2006.182.07:59:02.39#ibcon#enter sib2, iclass 12, count 2 2006.182.07:59:02.39#ibcon#flushed, iclass 12, count 2 2006.182.07:59:02.39#ibcon#about to write, iclass 12, count 2 2006.182.07:59:02.39#ibcon#wrote, iclass 12, count 2 2006.182.07:59:02.39#ibcon#about to read 3, iclass 12, count 2 2006.182.07:59:02.41#ibcon#read 3, iclass 12, count 2 2006.182.07:59:02.41#ibcon#about to read 4, iclass 12, count 2 2006.182.07:59:02.41#ibcon#read 4, iclass 12, count 2 2006.182.07:59:02.41#ibcon#about to read 5, iclass 12, count 2 2006.182.07:59:02.41#ibcon#read 5, iclass 12, count 2 2006.182.07:59:02.41#ibcon#about to read 6, iclass 12, count 2 2006.182.07:59:02.41#ibcon#read 6, iclass 12, count 2 2006.182.07:59:02.41#ibcon#end of sib2, iclass 12, count 2 2006.182.07:59:02.41#ibcon#*mode == 0, iclass 12, count 2 2006.182.07:59:02.41#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.07:59:02.41#ibcon#[27=AT06-04\r\n] 2006.182.07:59:02.41#ibcon#*before write, iclass 12, count 2 2006.182.07:59:02.41#ibcon#enter sib2, iclass 12, count 2 2006.182.07:59:02.41#ibcon#flushed, iclass 12, count 2 2006.182.07:59:02.41#ibcon#about to write, iclass 12, count 2 2006.182.07:59:02.41#ibcon#wrote, iclass 12, count 2 2006.182.07:59:02.41#ibcon#about to read 3, iclass 12, count 2 2006.182.07:59:02.44#ibcon#read 3, iclass 12, count 2 2006.182.07:59:02.44#ibcon#about to read 4, iclass 12, count 2 2006.182.07:59:02.44#ibcon#read 4, iclass 12, count 2 2006.182.07:59:02.44#ibcon#about to read 5, iclass 12, count 2 2006.182.07:59:02.44#ibcon#read 5, iclass 12, count 2 2006.182.07:59:02.44#ibcon#about to read 6, iclass 12, count 2 2006.182.07:59:02.44#ibcon#read 6, iclass 12, count 2 2006.182.07:59:02.44#ibcon#end of sib2, iclass 12, count 2 2006.182.07:59:02.44#ibcon#*after write, iclass 12, count 2 2006.182.07:59:02.44#ibcon#*before return 0, iclass 12, count 2 2006.182.07:59:02.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:59:02.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.07:59:02.44#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.07:59:02.44#ibcon#ireg 7 cls_cnt 0 2006.182.07:59:02.44#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:59:02.56#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:59:02.56#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:59:02.56#ibcon#enter wrdev, iclass 12, count 0 2006.182.07:59:02.56#ibcon#first serial, iclass 12, count 0 2006.182.07:59:02.56#ibcon#enter sib2, iclass 12, count 0 2006.182.07:59:02.56#ibcon#flushed, iclass 12, count 0 2006.182.07:59:02.56#ibcon#about to write, iclass 12, count 0 2006.182.07:59:02.56#ibcon#wrote, iclass 12, count 0 2006.182.07:59:02.56#ibcon#about to read 3, iclass 12, count 0 2006.182.07:59:02.58#ibcon#read 3, iclass 12, count 0 2006.182.07:59:02.58#ibcon#about to read 4, iclass 12, count 0 2006.182.07:59:02.58#ibcon#read 4, iclass 12, count 0 2006.182.07:59:02.58#ibcon#about to read 5, iclass 12, count 0 2006.182.07:59:02.58#ibcon#read 5, iclass 12, count 0 2006.182.07:59:02.58#ibcon#about to read 6, iclass 12, count 0 2006.182.07:59:02.58#ibcon#read 6, iclass 12, count 0 2006.182.07:59:02.58#ibcon#end of sib2, iclass 12, count 0 2006.182.07:59:02.58#ibcon#*mode == 0, iclass 12, count 0 2006.182.07:59:02.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.07:59:02.58#ibcon#[27=USB\r\n] 2006.182.07:59:02.58#ibcon#*before write, iclass 12, count 0 2006.182.07:59:02.58#ibcon#enter sib2, iclass 12, count 0 2006.182.07:59:02.58#ibcon#flushed, iclass 12, count 0 2006.182.07:59:02.58#ibcon#about to write, iclass 12, count 0 2006.182.07:59:02.58#ibcon#wrote, iclass 12, count 0 2006.182.07:59:02.58#ibcon#about to read 3, iclass 12, count 0 2006.182.07:59:02.61#ibcon#read 3, iclass 12, count 0 2006.182.07:59:02.61#ibcon#about to read 4, iclass 12, count 0 2006.182.07:59:02.61#ibcon#read 4, iclass 12, count 0 2006.182.07:59:02.61#ibcon#about to read 5, iclass 12, count 0 2006.182.07:59:02.61#ibcon#read 5, iclass 12, count 0 2006.182.07:59:02.61#ibcon#about to read 6, iclass 12, count 0 2006.182.07:59:02.61#ibcon#read 6, iclass 12, count 0 2006.182.07:59:02.61#ibcon#end of sib2, iclass 12, count 0 2006.182.07:59:02.61#ibcon#*after write, iclass 12, count 0 2006.182.07:59:02.61#ibcon#*before return 0, iclass 12, count 0 2006.182.07:59:02.61#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:59:02.61#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.07:59:02.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.07:59:02.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.07:59:02.61$vc4f8/vabw=wide 2006.182.07:59:02.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.07:59:02.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.07:59:02.61#ibcon#ireg 8 cls_cnt 0 2006.182.07:59:02.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:59:02.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:59:02.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:59:02.61#ibcon#enter wrdev, iclass 14, count 0 2006.182.07:59:02.61#ibcon#first serial, iclass 14, count 0 2006.182.07:59:02.61#ibcon#enter sib2, iclass 14, count 0 2006.182.07:59:02.61#ibcon#flushed, iclass 14, count 0 2006.182.07:59:02.61#ibcon#about to write, iclass 14, count 0 2006.182.07:59:02.61#ibcon#wrote, iclass 14, count 0 2006.182.07:59:02.61#ibcon#about to read 3, iclass 14, count 0 2006.182.07:59:02.64#ibcon#read 3, iclass 14, count 0 2006.182.07:59:02.64#ibcon#about to read 4, iclass 14, count 0 2006.182.07:59:02.64#ibcon#read 4, iclass 14, count 0 2006.182.07:59:02.64#ibcon#about to read 5, iclass 14, count 0 2006.182.07:59:02.64#ibcon#read 5, iclass 14, count 0 2006.182.07:59:02.64#ibcon#about to read 6, iclass 14, count 0 2006.182.07:59:02.64#ibcon#read 6, iclass 14, count 0 2006.182.07:59:02.64#ibcon#end of sib2, iclass 14, count 0 2006.182.07:59:02.64#ibcon#*mode == 0, iclass 14, count 0 2006.182.07:59:02.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.07:59:02.64#ibcon#[25=BW32\r\n] 2006.182.07:59:02.64#ibcon#*before write, iclass 14, count 0 2006.182.07:59:02.64#ibcon#enter sib2, iclass 14, count 0 2006.182.07:59:02.64#ibcon#flushed, iclass 14, count 0 2006.182.07:59:02.64#ibcon#about to write, iclass 14, count 0 2006.182.07:59:02.64#ibcon#wrote, iclass 14, count 0 2006.182.07:59:02.64#ibcon#about to read 3, iclass 14, count 0 2006.182.07:59:02.67#ibcon#read 3, iclass 14, count 0 2006.182.07:59:02.67#ibcon#about to read 4, iclass 14, count 0 2006.182.07:59:02.67#ibcon#read 4, iclass 14, count 0 2006.182.07:59:02.67#ibcon#about to read 5, iclass 14, count 0 2006.182.07:59:02.67#ibcon#read 5, iclass 14, count 0 2006.182.07:59:02.67#ibcon#about to read 6, iclass 14, count 0 2006.182.07:59:02.67#ibcon#read 6, iclass 14, count 0 2006.182.07:59:02.67#ibcon#end of sib2, iclass 14, count 0 2006.182.07:59:02.67#ibcon#*after write, iclass 14, count 0 2006.182.07:59:02.67#ibcon#*before return 0, iclass 14, count 0 2006.182.07:59:02.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:59:02.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.07:59:02.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.07:59:02.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.07:59:02.67$vc4f8/vbbw=wide 2006.182.07:59:02.67#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.07:59:02.67#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.07:59:02.67#ibcon#ireg 8 cls_cnt 0 2006.182.07:59:02.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:59:02.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:59:02.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:59:02.74#ibcon#enter wrdev, iclass 16, count 0 2006.182.07:59:02.74#ibcon#first serial, iclass 16, count 0 2006.182.07:59:02.74#ibcon#enter sib2, iclass 16, count 0 2006.182.07:59:02.74#ibcon#flushed, iclass 16, count 0 2006.182.07:59:02.74#ibcon#about to write, iclass 16, count 0 2006.182.07:59:02.74#ibcon#wrote, iclass 16, count 0 2006.182.07:59:02.74#ibcon#about to read 3, iclass 16, count 0 2006.182.07:59:02.75#ibcon#read 3, iclass 16, count 0 2006.182.07:59:02.75#ibcon#about to read 4, iclass 16, count 0 2006.182.07:59:02.75#ibcon#read 4, iclass 16, count 0 2006.182.07:59:02.75#ibcon#about to read 5, iclass 16, count 0 2006.182.07:59:02.75#ibcon#read 5, iclass 16, count 0 2006.182.07:59:02.75#ibcon#about to read 6, iclass 16, count 0 2006.182.07:59:02.75#ibcon#read 6, iclass 16, count 0 2006.182.07:59:02.75#ibcon#end of sib2, iclass 16, count 0 2006.182.07:59:02.75#ibcon#*mode == 0, iclass 16, count 0 2006.182.07:59:02.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.07:59:02.75#ibcon#[27=BW32\r\n] 2006.182.07:59:02.75#ibcon#*before write, iclass 16, count 0 2006.182.07:59:02.75#ibcon#enter sib2, iclass 16, count 0 2006.182.07:59:02.75#ibcon#flushed, iclass 16, count 0 2006.182.07:59:02.75#ibcon#about to write, iclass 16, count 0 2006.182.07:59:02.75#ibcon#wrote, iclass 16, count 0 2006.182.07:59:02.75#ibcon#about to read 3, iclass 16, count 0 2006.182.07:59:02.78#ibcon#read 3, iclass 16, count 0 2006.182.07:59:02.78#ibcon#about to read 4, iclass 16, count 0 2006.182.07:59:02.78#ibcon#read 4, iclass 16, count 0 2006.182.07:59:02.78#ibcon#about to read 5, iclass 16, count 0 2006.182.07:59:02.78#ibcon#read 5, iclass 16, count 0 2006.182.07:59:02.78#ibcon#about to read 6, iclass 16, count 0 2006.182.07:59:02.78#ibcon#read 6, iclass 16, count 0 2006.182.07:59:02.78#ibcon#end of sib2, iclass 16, count 0 2006.182.07:59:02.78#ibcon#*after write, iclass 16, count 0 2006.182.07:59:02.78#ibcon#*before return 0, iclass 16, count 0 2006.182.07:59:02.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:59:02.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.07:59:02.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.07:59:02.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.07:59:02.78$4f8m12a/ifd4f 2006.182.07:59:02.78$ifd4f/lo= 2006.182.07:59:02.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.07:59:02.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.07:59:02.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.07:59:02.79$ifd4f/patch= 2006.182.07:59:02.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.07:59:02.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.07:59:02.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.07:59:02.79$4f8m12a/"form=m,16.000,1:2 2006.182.07:59:02.79$4f8m12a/"tpicd 2006.182.07:59:02.79$4f8m12a/echo=off 2006.182.07:59:02.79$4f8m12a/xlog=off 2006.182.07:59:02.79:!2006.182.08:00:00 2006.182.07:59:39.14#trakl#Source acquired 2006.182.07:59:39.14#flagr#flagr/antenna,acquired 2006.182.08:00:00.01:preob 2006.182.08:00:01.14/onsource/TRACKING 2006.182.08:00:01.14:!2006.182.08:00:10 2006.182.08:00:10.00:data_valid=on 2006.182.08:00:10.00:midob 2006.182.08:00:10.14/onsource/TRACKING 2006.182.08:00:10.14/wx/27.77,1002.8,81 2006.182.08:00:10.20/cable/+6.4642E-03 2006.182.08:00:11.29/va/01,08,usb,yes,29,31 2006.182.08:00:11.29/va/02,07,usb,yes,29,31 2006.182.08:00:11.29/va/03,06,usb,yes,31,31 2006.182.08:00:11.29/va/04,07,usb,yes,30,32 2006.182.08:00:11.29/va/05,07,usb,yes,31,33 2006.182.08:00:11.29/va/06,06,usb,yes,30,30 2006.182.08:00:11.29/va/07,06,usb,yes,31,31 2006.182.08:00:11.29/va/08,07,usb,yes,29,29 2006.182.08:00:11.52/valo/01,532.99,yes,locked 2006.182.08:00:11.52/valo/02,572.99,yes,locked 2006.182.08:00:11.52/valo/03,672.99,yes,locked 2006.182.08:00:11.52/valo/04,832.99,yes,locked 2006.182.08:00:11.52/valo/05,652.99,yes,locked 2006.182.08:00:11.52/valo/06,772.99,yes,locked 2006.182.08:00:11.52/valo/07,832.99,yes,locked 2006.182.08:00:11.52/valo/08,852.99,yes,locked 2006.182.08:00:12.61/vb/01,04,usb,yes,30,28 2006.182.08:00:12.61/vb/02,04,usb,yes,34,33 2006.182.08:00:12.61/vb/03,04,usb,yes,28,33 2006.182.08:00:12.61/vb/04,04,usb,yes,28,29 2006.182.08:00:12.61/vb/05,04,usb,yes,27,31 2006.182.08:00:12.61/vb/06,04,usb,yes,28,31 2006.182.08:00:12.61/vb/07,04,usb,yes,30,30 2006.182.08:00:12.61/vb/08,04,usb,yes,28,31 2006.182.08:00:12.85/vblo/01,632.99,yes,locked 2006.182.08:00:12.85/vblo/02,640.99,yes,locked 2006.182.08:00:12.85/vblo/03,656.99,yes,locked 2006.182.08:00:12.85/vblo/04,712.99,yes,locked 2006.182.08:00:12.85/vblo/05,744.99,yes,locked 2006.182.08:00:12.85/vblo/06,752.99,yes,locked 2006.182.08:00:12.85/vblo/07,734.99,yes,locked 2006.182.08:00:12.85/vblo/08,744.99,yes,locked 2006.182.08:00:13.00/vabw/8 2006.182.08:00:13.15/vbbw/8 2006.182.08:00:13.24/xfe/off,on,14.7 2006.182.08:00:13.63/ifatt/23,28,28,28 2006.182.08:00:14.07/fmout-gps/S +3.39E-07 2006.182.08:00:14.15:!2006.182.08:01:10 2006.182.08:01:10.00:data_valid=off 2006.182.08:01:10.01:postob 2006.182.08:01:10.12/cable/+6.4644E-03 2006.182.08:01:10.13/wx/27.79,1002.9,82 2006.182.08:01:11.07/fmout-gps/S +3.40E-07 2006.182.08:01:11.08:scan_name=182-0802,k06182,60 2006.182.08:01:11.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.182.08:01:11.14#flagr#flagr/antenna,new-source 2006.182.08:01:12.14:checkk5 2006.182.08:01:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:01:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:01:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:01:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:01:14.02/chk_obsdata//k5ts1/T1820800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:01:14.39/chk_obsdata//k5ts2/T1820800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:01:14.76/chk_obsdata//k5ts3/T1820800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:01:15.13/chk_obsdata//k5ts4/T1820800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:01:15.82/k5log//k5ts1_log_newline 2006.182.08:01:16.52/k5log//k5ts2_log_newline 2006.182.08:01:17.21/k5log//k5ts3_log_newline 2006.182.08:01:17.90/k5log//k5ts4_log_newline 2006.182.08:01:17.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:01:17.92:4f8m12a=2 2006.182.08:01:17.92$4f8m12a/echo=on 2006.182.08:01:17.92$4f8m12a/pcalon 2006.182.08:01:17.92$pcalon/"no phase cal control is implemented here 2006.182.08:01:17.92$4f8m12a/"tpicd=stop 2006.182.08:01:17.92$4f8m12a/vc4f8 2006.182.08:01:17.92$vc4f8/valo=1,532.99 2006.182.08:01:17.93#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.08:01:17.93#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.08:01:17.93#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:17.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:17.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:17.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:17.93#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:01:17.93#ibcon#first serial, iclass 35, count 0 2006.182.08:01:17.93#ibcon#enter sib2, iclass 35, count 0 2006.182.08:01:17.93#ibcon#flushed, iclass 35, count 0 2006.182.08:01:17.93#ibcon#about to write, iclass 35, count 0 2006.182.08:01:17.93#ibcon#wrote, iclass 35, count 0 2006.182.08:01:17.93#ibcon#about to read 3, iclass 35, count 0 2006.182.08:01:17.97#ibcon#read 3, iclass 35, count 0 2006.182.08:01:17.97#ibcon#about to read 4, iclass 35, count 0 2006.182.08:01:17.97#ibcon#read 4, iclass 35, count 0 2006.182.08:01:17.97#ibcon#about to read 5, iclass 35, count 0 2006.182.08:01:17.97#ibcon#read 5, iclass 35, count 0 2006.182.08:01:17.97#ibcon#about to read 6, iclass 35, count 0 2006.182.08:01:17.97#ibcon#read 6, iclass 35, count 0 2006.182.08:01:17.97#ibcon#end of sib2, iclass 35, count 0 2006.182.08:01:17.97#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:01:17.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:01:17.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:01:17.97#ibcon#*before write, iclass 35, count 0 2006.182.08:01:17.97#ibcon#enter sib2, iclass 35, count 0 2006.182.08:01:17.97#ibcon#flushed, iclass 35, count 0 2006.182.08:01:17.97#ibcon#about to write, iclass 35, count 0 2006.182.08:01:17.97#ibcon#wrote, iclass 35, count 0 2006.182.08:01:17.97#ibcon#about to read 3, iclass 35, count 0 2006.182.08:01:18.01#ibcon#read 3, iclass 35, count 0 2006.182.08:01:18.01#ibcon#about to read 4, iclass 35, count 0 2006.182.08:01:18.01#ibcon#read 4, iclass 35, count 0 2006.182.08:01:18.01#ibcon#about to read 5, iclass 35, count 0 2006.182.08:01:18.01#ibcon#read 5, iclass 35, count 0 2006.182.08:01:18.01#ibcon#about to read 6, iclass 35, count 0 2006.182.08:01:18.01#ibcon#read 6, iclass 35, count 0 2006.182.08:01:18.01#ibcon#end of sib2, iclass 35, count 0 2006.182.08:01:18.01#ibcon#*after write, iclass 35, count 0 2006.182.08:01:18.01#ibcon#*before return 0, iclass 35, count 0 2006.182.08:01:18.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:18.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:18.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:01:18.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:01:18.01$vc4f8/va=1,8 2006.182.08:01:18.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.08:01:18.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.08:01:18.01#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:18.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:18.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:18.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:18.01#ibcon#enter wrdev, iclass 37, count 2 2006.182.08:01:18.01#ibcon#first serial, iclass 37, count 2 2006.182.08:01:18.01#ibcon#enter sib2, iclass 37, count 2 2006.182.08:01:18.01#ibcon#flushed, iclass 37, count 2 2006.182.08:01:18.01#ibcon#about to write, iclass 37, count 2 2006.182.08:01:18.01#ibcon#wrote, iclass 37, count 2 2006.182.08:01:18.01#ibcon#about to read 3, iclass 37, count 2 2006.182.08:01:18.03#ibcon#read 3, iclass 37, count 2 2006.182.08:01:18.03#ibcon#about to read 4, iclass 37, count 2 2006.182.08:01:18.03#ibcon#read 4, iclass 37, count 2 2006.182.08:01:18.03#ibcon#about to read 5, iclass 37, count 2 2006.182.08:01:18.03#ibcon#read 5, iclass 37, count 2 2006.182.08:01:18.03#ibcon#about to read 6, iclass 37, count 2 2006.182.08:01:18.03#ibcon#read 6, iclass 37, count 2 2006.182.08:01:18.03#ibcon#end of sib2, iclass 37, count 2 2006.182.08:01:18.03#ibcon#*mode == 0, iclass 37, count 2 2006.182.08:01:18.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.08:01:18.03#ibcon#[25=AT01-08\r\n] 2006.182.08:01:18.03#ibcon#*before write, iclass 37, count 2 2006.182.08:01:18.03#ibcon#enter sib2, iclass 37, count 2 2006.182.08:01:18.03#ibcon#flushed, iclass 37, count 2 2006.182.08:01:18.03#ibcon#about to write, iclass 37, count 2 2006.182.08:01:18.03#ibcon#wrote, iclass 37, count 2 2006.182.08:01:18.03#ibcon#about to read 3, iclass 37, count 2 2006.182.08:01:18.07#ibcon#read 3, iclass 37, count 2 2006.182.08:01:18.07#ibcon#about to read 4, iclass 37, count 2 2006.182.08:01:18.07#ibcon#read 4, iclass 37, count 2 2006.182.08:01:18.07#ibcon#about to read 5, iclass 37, count 2 2006.182.08:01:18.07#ibcon#read 5, iclass 37, count 2 2006.182.08:01:18.07#ibcon#about to read 6, iclass 37, count 2 2006.182.08:01:18.07#ibcon#read 6, iclass 37, count 2 2006.182.08:01:18.07#ibcon#end of sib2, iclass 37, count 2 2006.182.08:01:18.07#ibcon#*after write, iclass 37, count 2 2006.182.08:01:18.07#ibcon#*before return 0, iclass 37, count 2 2006.182.08:01:18.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:18.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:18.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.08:01:18.07#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:18.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:18.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:18.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:18.18#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:01:18.18#ibcon#first serial, iclass 37, count 0 2006.182.08:01:18.18#ibcon#enter sib2, iclass 37, count 0 2006.182.08:01:18.18#ibcon#flushed, iclass 37, count 0 2006.182.08:01:18.18#ibcon#about to write, iclass 37, count 0 2006.182.08:01:18.18#ibcon#wrote, iclass 37, count 0 2006.182.08:01:18.18#ibcon#about to read 3, iclass 37, count 0 2006.182.08:01:18.20#ibcon#read 3, iclass 37, count 0 2006.182.08:01:18.20#ibcon#about to read 4, iclass 37, count 0 2006.182.08:01:18.20#ibcon#read 4, iclass 37, count 0 2006.182.08:01:18.20#ibcon#about to read 5, iclass 37, count 0 2006.182.08:01:18.20#ibcon#read 5, iclass 37, count 0 2006.182.08:01:18.20#ibcon#about to read 6, iclass 37, count 0 2006.182.08:01:18.20#ibcon#read 6, iclass 37, count 0 2006.182.08:01:18.20#ibcon#end of sib2, iclass 37, count 0 2006.182.08:01:18.20#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:01:18.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:01:18.20#ibcon#[25=USB\r\n] 2006.182.08:01:18.20#ibcon#*before write, iclass 37, count 0 2006.182.08:01:18.20#ibcon#enter sib2, iclass 37, count 0 2006.182.08:01:18.20#ibcon#flushed, iclass 37, count 0 2006.182.08:01:18.20#ibcon#about to write, iclass 37, count 0 2006.182.08:01:18.20#ibcon#wrote, iclass 37, count 0 2006.182.08:01:18.20#ibcon#about to read 3, iclass 37, count 0 2006.182.08:01:18.24#ibcon#read 3, iclass 37, count 0 2006.182.08:01:18.24#ibcon#about to read 4, iclass 37, count 0 2006.182.08:01:18.24#ibcon#read 4, iclass 37, count 0 2006.182.08:01:18.24#ibcon#about to read 5, iclass 37, count 0 2006.182.08:01:18.24#ibcon#read 5, iclass 37, count 0 2006.182.08:01:18.24#ibcon#about to read 6, iclass 37, count 0 2006.182.08:01:18.24#ibcon#read 6, iclass 37, count 0 2006.182.08:01:18.24#ibcon#end of sib2, iclass 37, count 0 2006.182.08:01:18.24#ibcon#*after write, iclass 37, count 0 2006.182.08:01:18.24#ibcon#*before return 0, iclass 37, count 0 2006.182.08:01:18.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:18.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:18.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:01:18.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:01:18.24$vc4f8/valo=2,572.99 2006.182.08:01:18.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.08:01:18.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.08:01:18.24#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:18.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:18.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:18.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:18.24#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:01:18.24#ibcon#first serial, iclass 39, count 0 2006.182.08:01:18.24#ibcon#enter sib2, iclass 39, count 0 2006.182.08:01:18.24#ibcon#flushed, iclass 39, count 0 2006.182.08:01:18.24#ibcon#about to write, iclass 39, count 0 2006.182.08:01:18.24#ibcon#wrote, iclass 39, count 0 2006.182.08:01:18.24#ibcon#about to read 3, iclass 39, count 0 2006.182.08:01:18.25#ibcon#read 3, iclass 39, count 0 2006.182.08:01:18.25#ibcon#about to read 4, iclass 39, count 0 2006.182.08:01:18.25#ibcon#read 4, iclass 39, count 0 2006.182.08:01:18.25#ibcon#about to read 5, iclass 39, count 0 2006.182.08:01:18.25#ibcon#read 5, iclass 39, count 0 2006.182.08:01:18.25#ibcon#about to read 6, iclass 39, count 0 2006.182.08:01:18.25#ibcon#read 6, iclass 39, count 0 2006.182.08:01:18.25#ibcon#end of sib2, iclass 39, count 0 2006.182.08:01:18.25#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:01:18.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:01:18.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:01:18.25#ibcon#*before write, iclass 39, count 0 2006.182.08:01:18.25#ibcon#enter sib2, iclass 39, count 0 2006.182.08:01:18.25#ibcon#flushed, iclass 39, count 0 2006.182.08:01:18.25#ibcon#about to write, iclass 39, count 0 2006.182.08:01:18.25#ibcon#wrote, iclass 39, count 0 2006.182.08:01:18.25#ibcon#about to read 3, iclass 39, count 0 2006.182.08:01:18.29#ibcon#read 3, iclass 39, count 0 2006.182.08:01:18.29#ibcon#about to read 4, iclass 39, count 0 2006.182.08:01:18.29#ibcon#read 4, iclass 39, count 0 2006.182.08:01:18.29#ibcon#about to read 5, iclass 39, count 0 2006.182.08:01:18.29#ibcon#read 5, iclass 39, count 0 2006.182.08:01:18.29#ibcon#about to read 6, iclass 39, count 0 2006.182.08:01:18.29#ibcon#read 6, iclass 39, count 0 2006.182.08:01:18.29#ibcon#end of sib2, iclass 39, count 0 2006.182.08:01:18.29#ibcon#*after write, iclass 39, count 0 2006.182.08:01:18.29#ibcon#*before return 0, iclass 39, count 0 2006.182.08:01:18.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:18.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:18.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:01:18.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:01:18.29$vc4f8/va=2,7 2006.182.08:01:18.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.08:01:18.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.08:01:18.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:18.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:18.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:18.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:18.36#ibcon#enter wrdev, iclass 3, count 2 2006.182.08:01:18.36#ibcon#first serial, iclass 3, count 2 2006.182.08:01:18.36#ibcon#enter sib2, iclass 3, count 2 2006.182.08:01:18.36#ibcon#flushed, iclass 3, count 2 2006.182.08:01:18.36#ibcon#about to write, iclass 3, count 2 2006.182.08:01:18.36#ibcon#wrote, iclass 3, count 2 2006.182.08:01:18.36#ibcon#about to read 3, iclass 3, count 2 2006.182.08:01:18.38#ibcon#read 3, iclass 3, count 2 2006.182.08:01:18.38#ibcon#about to read 4, iclass 3, count 2 2006.182.08:01:18.38#ibcon#read 4, iclass 3, count 2 2006.182.08:01:18.38#ibcon#about to read 5, iclass 3, count 2 2006.182.08:01:18.38#ibcon#read 5, iclass 3, count 2 2006.182.08:01:18.38#ibcon#about to read 6, iclass 3, count 2 2006.182.08:01:18.38#ibcon#read 6, iclass 3, count 2 2006.182.08:01:18.38#ibcon#end of sib2, iclass 3, count 2 2006.182.08:01:18.38#ibcon#*mode == 0, iclass 3, count 2 2006.182.08:01:18.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.08:01:18.38#ibcon#[25=AT02-07\r\n] 2006.182.08:01:18.38#ibcon#*before write, iclass 3, count 2 2006.182.08:01:18.38#ibcon#enter sib2, iclass 3, count 2 2006.182.08:01:18.38#ibcon#flushed, iclass 3, count 2 2006.182.08:01:18.38#ibcon#about to write, iclass 3, count 2 2006.182.08:01:18.38#ibcon#wrote, iclass 3, count 2 2006.182.08:01:18.38#ibcon#about to read 3, iclass 3, count 2 2006.182.08:01:18.41#ibcon#read 3, iclass 3, count 2 2006.182.08:01:18.41#ibcon#about to read 4, iclass 3, count 2 2006.182.08:01:18.41#ibcon#read 4, iclass 3, count 2 2006.182.08:01:18.41#ibcon#about to read 5, iclass 3, count 2 2006.182.08:01:18.41#ibcon#read 5, iclass 3, count 2 2006.182.08:01:18.41#ibcon#about to read 6, iclass 3, count 2 2006.182.08:01:18.41#ibcon#read 6, iclass 3, count 2 2006.182.08:01:18.41#ibcon#end of sib2, iclass 3, count 2 2006.182.08:01:18.41#ibcon#*after write, iclass 3, count 2 2006.182.08:01:18.41#ibcon#*before return 0, iclass 3, count 2 2006.182.08:01:18.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:18.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:18.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.08:01:18.41#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:18.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:18.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:18.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:18.53#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:01:18.53#ibcon#first serial, iclass 3, count 0 2006.182.08:01:18.53#ibcon#enter sib2, iclass 3, count 0 2006.182.08:01:18.53#ibcon#flushed, iclass 3, count 0 2006.182.08:01:18.53#ibcon#about to write, iclass 3, count 0 2006.182.08:01:18.53#ibcon#wrote, iclass 3, count 0 2006.182.08:01:18.53#ibcon#about to read 3, iclass 3, count 0 2006.182.08:01:18.56#ibcon#read 3, iclass 3, count 0 2006.182.08:01:18.56#ibcon#about to read 4, iclass 3, count 0 2006.182.08:01:18.56#ibcon#read 4, iclass 3, count 0 2006.182.08:01:18.56#ibcon#about to read 5, iclass 3, count 0 2006.182.08:01:18.56#ibcon#read 5, iclass 3, count 0 2006.182.08:01:18.56#ibcon#about to read 6, iclass 3, count 0 2006.182.08:01:18.56#ibcon#read 6, iclass 3, count 0 2006.182.08:01:18.56#ibcon#end of sib2, iclass 3, count 0 2006.182.08:01:18.56#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:01:18.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:01:18.56#ibcon#[25=USB\r\n] 2006.182.08:01:18.56#ibcon#*before write, iclass 3, count 0 2006.182.08:01:18.56#ibcon#enter sib2, iclass 3, count 0 2006.182.08:01:18.56#ibcon#flushed, iclass 3, count 0 2006.182.08:01:18.56#ibcon#about to write, iclass 3, count 0 2006.182.08:01:18.56#ibcon#wrote, iclass 3, count 0 2006.182.08:01:18.56#ibcon#about to read 3, iclass 3, count 0 2006.182.08:01:18.58#ibcon#read 3, iclass 3, count 0 2006.182.08:01:18.58#ibcon#about to read 4, iclass 3, count 0 2006.182.08:01:18.58#ibcon#read 4, iclass 3, count 0 2006.182.08:01:18.58#ibcon#about to read 5, iclass 3, count 0 2006.182.08:01:18.58#ibcon#read 5, iclass 3, count 0 2006.182.08:01:18.58#ibcon#about to read 6, iclass 3, count 0 2006.182.08:01:18.58#ibcon#read 6, iclass 3, count 0 2006.182.08:01:18.58#ibcon#end of sib2, iclass 3, count 0 2006.182.08:01:18.58#ibcon#*after write, iclass 3, count 0 2006.182.08:01:18.58#ibcon#*before return 0, iclass 3, count 0 2006.182.08:01:18.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:18.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:18.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:01:18.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:01:18.58$vc4f8/valo=3,672.99 2006.182.08:01:18.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.08:01:18.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.08:01:18.58#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:18.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:18.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:18.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:18.58#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:01:18.58#ibcon#first serial, iclass 5, count 0 2006.182.08:01:18.58#ibcon#enter sib2, iclass 5, count 0 2006.182.08:01:18.58#ibcon#flushed, iclass 5, count 0 2006.182.08:01:18.58#ibcon#about to write, iclass 5, count 0 2006.182.08:01:18.58#ibcon#wrote, iclass 5, count 0 2006.182.08:01:18.58#ibcon#about to read 3, iclass 5, count 0 2006.182.08:01:18.60#ibcon#read 3, iclass 5, count 0 2006.182.08:01:18.60#ibcon#about to read 4, iclass 5, count 0 2006.182.08:01:18.60#ibcon#read 4, iclass 5, count 0 2006.182.08:01:18.60#ibcon#about to read 5, iclass 5, count 0 2006.182.08:01:18.60#ibcon#read 5, iclass 5, count 0 2006.182.08:01:18.60#ibcon#about to read 6, iclass 5, count 0 2006.182.08:01:18.60#ibcon#read 6, iclass 5, count 0 2006.182.08:01:18.60#ibcon#end of sib2, iclass 5, count 0 2006.182.08:01:18.60#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:01:18.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:01:18.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:01:18.60#ibcon#*before write, iclass 5, count 0 2006.182.08:01:18.60#ibcon#enter sib2, iclass 5, count 0 2006.182.08:01:18.60#ibcon#flushed, iclass 5, count 0 2006.182.08:01:18.60#ibcon#about to write, iclass 5, count 0 2006.182.08:01:18.60#ibcon#wrote, iclass 5, count 0 2006.182.08:01:18.60#ibcon#about to read 3, iclass 5, count 0 2006.182.08:01:18.64#ibcon#read 3, iclass 5, count 0 2006.182.08:01:18.64#ibcon#about to read 4, iclass 5, count 0 2006.182.08:01:18.64#ibcon#read 4, iclass 5, count 0 2006.182.08:01:18.64#ibcon#about to read 5, iclass 5, count 0 2006.182.08:01:18.64#ibcon#read 5, iclass 5, count 0 2006.182.08:01:18.64#ibcon#about to read 6, iclass 5, count 0 2006.182.08:01:18.64#ibcon#read 6, iclass 5, count 0 2006.182.08:01:18.64#ibcon#end of sib2, iclass 5, count 0 2006.182.08:01:18.64#ibcon#*after write, iclass 5, count 0 2006.182.08:01:18.64#ibcon#*before return 0, iclass 5, count 0 2006.182.08:01:18.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:18.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:18.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:01:18.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:01:18.64$vc4f8/va=3,6 2006.182.08:01:18.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.08:01:18.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.08:01:18.64#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:18.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:18.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:18.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:18.70#ibcon#enter wrdev, iclass 7, count 2 2006.182.08:01:18.70#ibcon#first serial, iclass 7, count 2 2006.182.08:01:18.70#ibcon#enter sib2, iclass 7, count 2 2006.182.08:01:18.70#ibcon#flushed, iclass 7, count 2 2006.182.08:01:18.70#ibcon#about to write, iclass 7, count 2 2006.182.08:01:18.70#ibcon#wrote, iclass 7, count 2 2006.182.08:01:18.70#ibcon#about to read 3, iclass 7, count 2 2006.182.08:01:18.73#ibcon#read 3, iclass 7, count 2 2006.182.08:01:18.73#ibcon#about to read 4, iclass 7, count 2 2006.182.08:01:18.73#ibcon#read 4, iclass 7, count 2 2006.182.08:01:18.73#ibcon#about to read 5, iclass 7, count 2 2006.182.08:01:18.73#ibcon#read 5, iclass 7, count 2 2006.182.08:01:18.73#ibcon#about to read 6, iclass 7, count 2 2006.182.08:01:18.73#ibcon#read 6, iclass 7, count 2 2006.182.08:01:18.73#ibcon#end of sib2, iclass 7, count 2 2006.182.08:01:18.73#ibcon#*mode == 0, iclass 7, count 2 2006.182.08:01:18.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.08:01:18.73#ibcon#[25=AT03-06\r\n] 2006.182.08:01:18.73#ibcon#*before write, iclass 7, count 2 2006.182.08:01:18.73#ibcon#enter sib2, iclass 7, count 2 2006.182.08:01:18.73#ibcon#flushed, iclass 7, count 2 2006.182.08:01:18.73#ibcon#about to write, iclass 7, count 2 2006.182.08:01:18.73#ibcon#wrote, iclass 7, count 2 2006.182.08:01:18.73#ibcon#about to read 3, iclass 7, count 2 2006.182.08:01:18.76#ibcon#read 3, iclass 7, count 2 2006.182.08:01:18.76#ibcon#about to read 4, iclass 7, count 2 2006.182.08:01:18.76#ibcon#read 4, iclass 7, count 2 2006.182.08:01:18.76#ibcon#about to read 5, iclass 7, count 2 2006.182.08:01:18.76#ibcon#read 5, iclass 7, count 2 2006.182.08:01:18.76#ibcon#about to read 6, iclass 7, count 2 2006.182.08:01:18.76#ibcon#read 6, iclass 7, count 2 2006.182.08:01:18.76#ibcon#end of sib2, iclass 7, count 2 2006.182.08:01:18.76#ibcon#*after write, iclass 7, count 2 2006.182.08:01:18.76#ibcon#*before return 0, iclass 7, count 2 2006.182.08:01:18.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:18.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:18.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.08:01:18.76#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:18.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:18.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:18.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:18.88#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:01:18.88#ibcon#first serial, iclass 7, count 0 2006.182.08:01:18.88#ibcon#enter sib2, iclass 7, count 0 2006.182.08:01:18.88#ibcon#flushed, iclass 7, count 0 2006.182.08:01:18.88#ibcon#about to write, iclass 7, count 0 2006.182.08:01:18.88#ibcon#wrote, iclass 7, count 0 2006.182.08:01:18.88#ibcon#about to read 3, iclass 7, count 0 2006.182.08:01:18.90#ibcon#read 3, iclass 7, count 0 2006.182.08:01:18.90#ibcon#about to read 4, iclass 7, count 0 2006.182.08:01:18.90#ibcon#read 4, iclass 7, count 0 2006.182.08:01:18.90#ibcon#about to read 5, iclass 7, count 0 2006.182.08:01:18.90#ibcon#read 5, iclass 7, count 0 2006.182.08:01:18.90#ibcon#about to read 6, iclass 7, count 0 2006.182.08:01:18.90#ibcon#read 6, iclass 7, count 0 2006.182.08:01:18.90#ibcon#end of sib2, iclass 7, count 0 2006.182.08:01:18.90#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:01:18.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:01:18.90#ibcon#[25=USB\r\n] 2006.182.08:01:18.90#ibcon#*before write, iclass 7, count 0 2006.182.08:01:18.90#ibcon#enter sib2, iclass 7, count 0 2006.182.08:01:18.90#ibcon#flushed, iclass 7, count 0 2006.182.08:01:18.90#ibcon#about to write, iclass 7, count 0 2006.182.08:01:18.90#ibcon#wrote, iclass 7, count 0 2006.182.08:01:18.90#ibcon#about to read 3, iclass 7, count 0 2006.182.08:01:18.93#ibcon#read 3, iclass 7, count 0 2006.182.08:01:18.93#ibcon#about to read 4, iclass 7, count 0 2006.182.08:01:18.93#ibcon#read 4, iclass 7, count 0 2006.182.08:01:18.93#ibcon#about to read 5, iclass 7, count 0 2006.182.08:01:18.93#ibcon#read 5, iclass 7, count 0 2006.182.08:01:18.93#ibcon#about to read 6, iclass 7, count 0 2006.182.08:01:18.93#ibcon#read 6, iclass 7, count 0 2006.182.08:01:18.93#ibcon#end of sib2, iclass 7, count 0 2006.182.08:01:18.93#ibcon#*after write, iclass 7, count 0 2006.182.08:01:18.93#ibcon#*before return 0, iclass 7, count 0 2006.182.08:01:18.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:18.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:18.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:01:18.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:01:18.93$vc4f8/valo=4,832.99 2006.182.08:01:18.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.08:01:18.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.08:01:18.93#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:18.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:18.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:18.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:18.93#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:01:18.93#ibcon#first serial, iclass 11, count 0 2006.182.08:01:18.93#ibcon#enter sib2, iclass 11, count 0 2006.182.08:01:18.93#ibcon#flushed, iclass 11, count 0 2006.182.08:01:18.93#ibcon#about to write, iclass 11, count 0 2006.182.08:01:18.93#ibcon#wrote, iclass 11, count 0 2006.182.08:01:18.93#ibcon#about to read 3, iclass 11, count 0 2006.182.08:01:18.95#ibcon#read 3, iclass 11, count 0 2006.182.08:01:18.95#ibcon#about to read 4, iclass 11, count 0 2006.182.08:01:18.95#ibcon#read 4, iclass 11, count 0 2006.182.08:01:18.95#ibcon#about to read 5, iclass 11, count 0 2006.182.08:01:18.95#ibcon#read 5, iclass 11, count 0 2006.182.08:01:18.95#ibcon#about to read 6, iclass 11, count 0 2006.182.08:01:18.95#ibcon#read 6, iclass 11, count 0 2006.182.08:01:18.95#ibcon#end of sib2, iclass 11, count 0 2006.182.08:01:18.95#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:01:18.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:01:18.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:01:18.95#ibcon#*before write, iclass 11, count 0 2006.182.08:01:18.95#ibcon#enter sib2, iclass 11, count 0 2006.182.08:01:18.95#ibcon#flushed, iclass 11, count 0 2006.182.08:01:18.95#ibcon#about to write, iclass 11, count 0 2006.182.08:01:18.95#ibcon#wrote, iclass 11, count 0 2006.182.08:01:18.95#ibcon#about to read 3, iclass 11, count 0 2006.182.08:01:18.99#ibcon#read 3, iclass 11, count 0 2006.182.08:01:18.99#ibcon#about to read 4, iclass 11, count 0 2006.182.08:01:18.99#ibcon#read 4, iclass 11, count 0 2006.182.08:01:18.99#ibcon#about to read 5, iclass 11, count 0 2006.182.08:01:18.99#ibcon#read 5, iclass 11, count 0 2006.182.08:01:18.99#ibcon#about to read 6, iclass 11, count 0 2006.182.08:01:18.99#ibcon#read 6, iclass 11, count 0 2006.182.08:01:18.99#ibcon#end of sib2, iclass 11, count 0 2006.182.08:01:18.99#ibcon#*after write, iclass 11, count 0 2006.182.08:01:18.99#ibcon#*before return 0, iclass 11, count 0 2006.182.08:01:18.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:18.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:18.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:01:18.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:01:18.99$vc4f8/va=4,7 2006.182.08:01:18.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.08:01:18.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.08:01:18.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:18.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:19.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:19.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:19.05#ibcon#enter wrdev, iclass 13, count 2 2006.182.08:01:19.05#ibcon#first serial, iclass 13, count 2 2006.182.08:01:19.05#ibcon#enter sib2, iclass 13, count 2 2006.182.08:01:19.05#ibcon#flushed, iclass 13, count 2 2006.182.08:01:19.05#ibcon#about to write, iclass 13, count 2 2006.182.08:01:19.05#ibcon#wrote, iclass 13, count 2 2006.182.08:01:19.05#ibcon#about to read 3, iclass 13, count 2 2006.182.08:01:19.07#ibcon#read 3, iclass 13, count 2 2006.182.08:01:19.07#ibcon#about to read 4, iclass 13, count 2 2006.182.08:01:19.07#ibcon#read 4, iclass 13, count 2 2006.182.08:01:19.07#ibcon#about to read 5, iclass 13, count 2 2006.182.08:01:19.07#ibcon#read 5, iclass 13, count 2 2006.182.08:01:19.07#ibcon#about to read 6, iclass 13, count 2 2006.182.08:01:19.07#ibcon#read 6, iclass 13, count 2 2006.182.08:01:19.07#ibcon#end of sib2, iclass 13, count 2 2006.182.08:01:19.07#ibcon#*mode == 0, iclass 13, count 2 2006.182.08:01:19.07#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.08:01:19.07#ibcon#[25=AT04-07\r\n] 2006.182.08:01:19.07#ibcon#*before write, iclass 13, count 2 2006.182.08:01:19.07#ibcon#enter sib2, iclass 13, count 2 2006.182.08:01:19.07#ibcon#flushed, iclass 13, count 2 2006.182.08:01:19.07#ibcon#about to write, iclass 13, count 2 2006.182.08:01:19.07#ibcon#wrote, iclass 13, count 2 2006.182.08:01:19.07#ibcon#about to read 3, iclass 13, count 2 2006.182.08:01:19.10#ibcon#read 3, iclass 13, count 2 2006.182.08:01:19.10#ibcon#about to read 4, iclass 13, count 2 2006.182.08:01:19.10#ibcon#read 4, iclass 13, count 2 2006.182.08:01:19.10#ibcon#about to read 5, iclass 13, count 2 2006.182.08:01:19.10#ibcon#read 5, iclass 13, count 2 2006.182.08:01:19.10#ibcon#about to read 6, iclass 13, count 2 2006.182.08:01:19.10#ibcon#read 6, iclass 13, count 2 2006.182.08:01:19.10#ibcon#end of sib2, iclass 13, count 2 2006.182.08:01:19.10#ibcon#*after write, iclass 13, count 2 2006.182.08:01:19.10#ibcon#*before return 0, iclass 13, count 2 2006.182.08:01:19.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:19.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:19.10#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.08:01:19.10#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:19.10#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:19.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:19.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:19.22#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:01:19.22#ibcon#first serial, iclass 13, count 0 2006.182.08:01:19.22#ibcon#enter sib2, iclass 13, count 0 2006.182.08:01:19.22#ibcon#flushed, iclass 13, count 0 2006.182.08:01:19.22#ibcon#about to write, iclass 13, count 0 2006.182.08:01:19.22#ibcon#wrote, iclass 13, count 0 2006.182.08:01:19.22#ibcon#about to read 3, iclass 13, count 0 2006.182.08:01:19.24#ibcon#read 3, iclass 13, count 0 2006.182.08:01:19.24#ibcon#about to read 4, iclass 13, count 0 2006.182.08:01:19.24#ibcon#read 4, iclass 13, count 0 2006.182.08:01:19.24#ibcon#about to read 5, iclass 13, count 0 2006.182.08:01:19.24#ibcon#read 5, iclass 13, count 0 2006.182.08:01:19.24#ibcon#about to read 6, iclass 13, count 0 2006.182.08:01:19.24#ibcon#read 6, iclass 13, count 0 2006.182.08:01:19.24#ibcon#end of sib2, iclass 13, count 0 2006.182.08:01:19.24#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:01:19.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:01:19.24#ibcon#[25=USB\r\n] 2006.182.08:01:19.24#ibcon#*before write, iclass 13, count 0 2006.182.08:01:19.24#ibcon#enter sib2, iclass 13, count 0 2006.182.08:01:19.24#ibcon#flushed, iclass 13, count 0 2006.182.08:01:19.24#ibcon#about to write, iclass 13, count 0 2006.182.08:01:19.24#ibcon#wrote, iclass 13, count 0 2006.182.08:01:19.24#ibcon#about to read 3, iclass 13, count 0 2006.182.08:01:19.27#ibcon#read 3, iclass 13, count 0 2006.182.08:01:19.27#ibcon#about to read 4, iclass 13, count 0 2006.182.08:01:19.27#ibcon#read 4, iclass 13, count 0 2006.182.08:01:19.27#ibcon#about to read 5, iclass 13, count 0 2006.182.08:01:19.27#ibcon#read 5, iclass 13, count 0 2006.182.08:01:19.27#ibcon#about to read 6, iclass 13, count 0 2006.182.08:01:19.27#ibcon#read 6, iclass 13, count 0 2006.182.08:01:19.27#ibcon#end of sib2, iclass 13, count 0 2006.182.08:01:19.27#ibcon#*after write, iclass 13, count 0 2006.182.08:01:19.27#ibcon#*before return 0, iclass 13, count 0 2006.182.08:01:19.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:19.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:19.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:01:19.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:01:19.27$vc4f8/valo=5,652.99 2006.182.08:01:19.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.08:01:19.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.08:01:19.27#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:19.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:19.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:19.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:19.27#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:01:19.27#ibcon#first serial, iclass 15, count 0 2006.182.08:01:19.27#ibcon#enter sib2, iclass 15, count 0 2006.182.08:01:19.27#ibcon#flushed, iclass 15, count 0 2006.182.08:01:19.27#ibcon#about to write, iclass 15, count 0 2006.182.08:01:19.27#ibcon#wrote, iclass 15, count 0 2006.182.08:01:19.27#ibcon#about to read 3, iclass 15, count 0 2006.182.08:01:19.29#ibcon#read 3, iclass 15, count 0 2006.182.08:01:19.29#ibcon#about to read 4, iclass 15, count 0 2006.182.08:01:19.29#ibcon#read 4, iclass 15, count 0 2006.182.08:01:19.29#ibcon#about to read 5, iclass 15, count 0 2006.182.08:01:19.29#ibcon#read 5, iclass 15, count 0 2006.182.08:01:19.29#ibcon#about to read 6, iclass 15, count 0 2006.182.08:01:19.29#ibcon#read 6, iclass 15, count 0 2006.182.08:01:19.29#ibcon#end of sib2, iclass 15, count 0 2006.182.08:01:19.29#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:01:19.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:01:19.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:01:19.29#ibcon#*before write, iclass 15, count 0 2006.182.08:01:19.29#ibcon#enter sib2, iclass 15, count 0 2006.182.08:01:19.29#ibcon#flushed, iclass 15, count 0 2006.182.08:01:19.29#ibcon#about to write, iclass 15, count 0 2006.182.08:01:19.29#ibcon#wrote, iclass 15, count 0 2006.182.08:01:19.29#ibcon#about to read 3, iclass 15, count 0 2006.182.08:01:19.33#ibcon#read 3, iclass 15, count 0 2006.182.08:01:19.33#ibcon#about to read 4, iclass 15, count 0 2006.182.08:01:19.33#ibcon#read 4, iclass 15, count 0 2006.182.08:01:19.33#ibcon#about to read 5, iclass 15, count 0 2006.182.08:01:19.33#ibcon#read 5, iclass 15, count 0 2006.182.08:01:19.33#ibcon#about to read 6, iclass 15, count 0 2006.182.08:01:19.33#ibcon#read 6, iclass 15, count 0 2006.182.08:01:19.33#ibcon#end of sib2, iclass 15, count 0 2006.182.08:01:19.33#ibcon#*after write, iclass 15, count 0 2006.182.08:01:19.33#ibcon#*before return 0, iclass 15, count 0 2006.182.08:01:19.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:19.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:19.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:01:19.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:01:19.33$vc4f8/va=5,7 2006.182.08:01:19.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.08:01:19.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.08:01:19.33#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:19.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:19.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:19.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:19.39#ibcon#enter wrdev, iclass 17, count 2 2006.182.08:01:19.39#ibcon#first serial, iclass 17, count 2 2006.182.08:01:19.39#ibcon#enter sib2, iclass 17, count 2 2006.182.08:01:19.39#ibcon#flushed, iclass 17, count 2 2006.182.08:01:19.39#ibcon#about to write, iclass 17, count 2 2006.182.08:01:19.39#ibcon#wrote, iclass 17, count 2 2006.182.08:01:19.39#ibcon#about to read 3, iclass 17, count 2 2006.182.08:01:19.41#ibcon#read 3, iclass 17, count 2 2006.182.08:01:19.41#ibcon#about to read 4, iclass 17, count 2 2006.182.08:01:19.41#ibcon#read 4, iclass 17, count 2 2006.182.08:01:19.41#ibcon#about to read 5, iclass 17, count 2 2006.182.08:01:19.41#ibcon#read 5, iclass 17, count 2 2006.182.08:01:19.41#ibcon#about to read 6, iclass 17, count 2 2006.182.08:01:19.41#ibcon#read 6, iclass 17, count 2 2006.182.08:01:19.41#ibcon#end of sib2, iclass 17, count 2 2006.182.08:01:19.41#ibcon#*mode == 0, iclass 17, count 2 2006.182.08:01:19.41#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.08:01:19.41#ibcon#[25=AT05-07\r\n] 2006.182.08:01:19.41#ibcon#*before write, iclass 17, count 2 2006.182.08:01:19.41#ibcon#enter sib2, iclass 17, count 2 2006.182.08:01:19.41#ibcon#flushed, iclass 17, count 2 2006.182.08:01:19.41#ibcon#about to write, iclass 17, count 2 2006.182.08:01:19.41#ibcon#wrote, iclass 17, count 2 2006.182.08:01:19.41#ibcon#about to read 3, iclass 17, count 2 2006.182.08:01:19.44#ibcon#read 3, iclass 17, count 2 2006.182.08:01:19.44#ibcon#about to read 4, iclass 17, count 2 2006.182.08:01:19.44#ibcon#read 4, iclass 17, count 2 2006.182.08:01:19.44#ibcon#about to read 5, iclass 17, count 2 2006.182.08:01:19.44#ibcon#read 5, iclass 17, count 2 2006.182.08:01:19.44#ibcon#about to read 6, iclass 17, count 2 2006.182.08:01:19.44#ibcon#read 6, iclass 17, count 2 2006.182.08:01:19.44#ibcon#end of sib2, iclass 17, count 2 2006.182.08:01:19.44#ibcon#*after write, iclass 17, count 2 2006.182.08:01:19.44#ibcon#*before return 0, iclass 17, count 2 2006.182.08:01:19.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:19.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:19.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.08:01:19.44#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:19.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:19.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:19.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:19.56#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:01:19.56#ibcon#first serial, iclass 17, count 0 2006.182.08:01:19.56#ibcon#enter sib2, iclass 17, count 0 2006.182.08:01:19.56#ibcon#flushed, iclass 17, count 0 2006.182.08:01:19.56#ibcon#about to write, iclass 17, count 0 2006.182.08:01:19.56#ibcon#wrote, iclass 17, count 0 2006.182.08:01:19.56#ibcon#about to read 3, iclass 17, count 0 2006.182.08:01:19.58#ibcon#read 3, iclass 17, count 0 2006.182.08:01:19.58#ibcon#about to read 4, iclass 17, count 0 2006.182.08:01:19.58#ibcon#read 4, iclass 17, count 0 2006.182.08:01:19.58#ibcon#about to read 5, iclass 17, count 0 2006.182.08:01:19.58#ibcon#read 5, iclass 17, count 0 2006.182.08:01:19.58#ibcon#about to read 6, iclass 17, count 0 2006.182.08:01:19.58#ibcon#read 6, iclass 17, count 0 2006.182.08:01:19.58#ibcon#end of sib2, iclass 17, count 0 2006.182.08:01:19.58#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:01:19.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:01:19.58#ibcon#[25=USB\r\n] 2006.182.08:01:19.58#ibcon#*before write, iclass 17, count 0 2006.182.08:01:19.58#ibcon#enter sib2, iclass 17, count 0 2006.182.08:01:19.58#ibcon#flushed, iclass 17, count 0 2006.182.08:01:19.58#ibcon#about to write, iclass 17, count 0 2006.182.08:01:19.58#ibcon#wrote, iclass 17, count 0 2006.182.08:01:19.58#ibcon#about to read 3, iclass 17, count 0 2006.182.08:01:19.61#ibcon#read 3, iclass 17, count 0 2006.182.08:01:19.61#ibcon#about to read 4, iclass 17, count 0 2006.182.08:01:19.61#ibcon#read 4, iclass 17, count 0 2006.182.08:01:19.61#ibcon#about to read 5, iclass 17, count 0 2006.182.08:01:19.61#ibcon#read 5, iclass 17, count 0 2006.182.08:01:19.61#ibcon#about to read 6, iclass 17, count 0 2006.182.08:01:19.61#ibcon#read 6, iclass 17, count 0 2006.182.08:01:19.61#ibcon#end of sib2, iclass 17, count 0 2006.182.08:01:19.61#ibcon#*after write, iclass 17, count 0 2006.182.08:01:19.61#ibcon#*before return 0, iclass 17, count 0 2006.182.08:01:19.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:19.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:19.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:01:19.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:01:19.61$vc4f8/valo=6,772.99 2006.182.08:01:19.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.08:01:19.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.08:01:19.61#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:19.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:19.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:19.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:19.61#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:01:19.61#ibcon#first serial, iclass 19, count 0 2006.182.08:01:19.61#ibcon#enter sib2, iclass 19, count 0 2006.182.08:01:19.61#ibcon#flushed, iclass 19, count 0 2006.182.08:01:19.61#ibcon#about to write, iclass 19, count 0 2006.182.08:01:19.61#ibcon#wrote, iclass 19, count 0 2006.182.08:01:19.61#ibcon#about to read 3, iclass 19, count 0 2006.182.08:01:19.64#ibcon#read 3, iclass 19, count 0 2006.182.08:01:19.64#ibcon#about to read 4, iclass 19, count 0 2006.182.08:01:19.64#ibcon#read 4, iclass 19, count 0 2006.182.08:01:19.64#ibcon#about to read 5, iclass 19, count 0 2006.182.08:01:19.64#ibcon#read 5, iclass 19, count 0 2006.182.08:01:19.64#ibcon#about to read 6, iclass 19, count 0 2006.182.08:01:19.64#ibcon#read 6, iclass 19, count 0 2006.182.08:01:19.64#ibcon#end of sib2, iclass 19, count 0 2006.182.08:01:19.64#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:01:19.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:01:19.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:01:19.64#ibcon#*before write, iclass 19, count 0 2006.182.08:01:19.64#ibcon#enter sib2, iclass 19, count 0 2006.182.08:01:19.64#ibcon#flushed, iclass 19, count 0 2006.182.08:01:19.64#ibcon#about to write, iclass 19, count 0 2006.182.08:01:19.64#ibcon#wrote, iclass 19, count 0 2006.182.08:01:19.64#ibcon#about to read 3, iclass 19, count 0 2006.182.08:01:19.68#ibcon#read 3, iclass 19, count 0 2006.182.08:01:19.68#ibcon#about to read 4, iclass 19, count 0 2006.182.08:01:19.68#ibcon#read 4, iclass 19, count 0 2006.182.08:01:19.68#ibcon#about to read 5, iclass 19, count 0 2006.182.08:01:19.68#ibcon#read 5, iclass 19, count 0 2006.182.08:01:19.68#ibcon#about to read 6, iclass 19, count 0 2006.182.08:01:19.68#ibcon#read 6, iclass 19, count 0 2006.182.08:01:19.68#ibcon#end of sib2, iclass 19, count 0 2006.182.08:01:19.68#ibcon#*after write, iclass 19, count 0 2006.182.08:01:19.68#ibcon#*before return 0, iclass 19, count 0 2006.182.08:01:19.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:19.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:19.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:01:19.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:01:19.68$vc4f8/va=6,6 2006.182.08:01:19.68#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.08:01:19.68#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.08:01:19.68#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:19.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:01:19.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:01:19.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:01:19.73#ibcon#enter wrdev, iclass 21, count 2 2006.182.08:01:19.73#ibcon#first serial, iclass 21, count 2 2006.182.08:01:19.73#ibcon#enter sib2, iclass 21, count 2 2006.182.08:01:19.73#ibcon#flushed, iclass 21, count 2 2006.182.08:01:19.73#ibcon#about to write, iclass 21, count 2 2006.182.08:01:19.73#ibcon#wrote, iclass 21, count 2 2006.182.08:01:19.73#ibcon#about to read 3, iclass 21, count 2 2006.182.08:01:19.75#ibcon#read 3, iclass 21, count 2 2006.182.08:01:19.75#ibcon#about to read 4, iclass 21, count 2 2006.182.08:01:19.75#ibcon#read 4, iclass 21, count 2 2006.182.08:01:19.75#ibcon#about to read 5, iclass 21, count 2 2006.182.08:01:19.75#ibcon#read 5, iclass 21, count 2 2006.182.08:01:19.75#ibcon#about to read 6, iclass 21, count 2 2006.182.08:01:19.75#ibcon#read 6, iclass 21, count 2 2006.182.08:01:19.75#ibcon#end of sib2, iclass 21, count 2 2006.182.08:01:19.75#ibcon#*mode == 0, iclass 21, count 2 2006.182.08:01:19.75#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.08:01:19.75#ibcon#[25=AT06-06\r\n] 2006.182.08:01:19.75#ibcon#*before write, iclass 21, count 2 2006.182.08:01:19.75#ibcon#enter sib2, iclass 21, count 2 2006.182.08:01:19.75#ibcon#flushed, iclass 21, count 2 2006.182.08:01:19.75#ibcon#about to write, iclass 21, count 2 2006.182.08:01:19.75#ibcon#wrote, iclass 21, count 2 2006.182.08:01:19.75#ibcon#about to read 3, iclass 21, count 2 2006.182.08:01:19.78#ibcon#read 3, iclass 21, count 2 2006.182.08:01:19.78#ibcon#about to read 4, iclass 21, count 2 2006.182.08:01:19.78#ibcon#read 4, iclass 21, count 2 2006.182.08:01:19.78#ibcon#about to read 5, iclass 21, count 2 2006.182.08:01:19.78#ibcon#read 5, iclass 21, count 2 2006.182.08:01:19.78#ibcon#about to read 6, iclass 21, count 2 2006.182.08:01:19.78#ibcon#read 6, iclass 21, count 2 2006.182.08:01:19.78#ibcon#end of sib2, iclass 21, count 2 2006.182.08:01:19.78#ibcon#*after write, iclass 21, count 2 2006.182.08:01:19.78#ibcon#*before return 0, iclass 21, count 2 2006.182.08:01:19.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:01:19.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:01:19.78#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.08:01:19.78#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:19.78#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:01:19.90#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:01:19.90#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:01:19.90#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:01:19.90#ibcon#first serial, iclass 21, count 0 2006.182.08:01:19.90#ibcon#enter sib2, iclass 21, count 0 2006.182.08:01:19.90#ibcon#flushed, iclass 21, count 0 2006.182.08:01:19.90#ibcon#about to write, iclass 21, count 0 2006.182.08:01:19.90#ibcon#wrote, iclass 21, count 0 2006.182.08:01:19.90#ibcon#about to read 3, iclass 21, count 0 2006.182.08:01:19.92#ibcon#read 3, iclass 21, count 0 2006.182.08:01:19.92#ibcon#about to read 4, iclass 21, count 0 2006.182.08:01:19.92#ibcon#read 4, iclass 21, count 0 2006.182.08:01:19.92#ibcon#about to read 5, iclass 21, count 0 2006.182.08:01:19.92#ibcon#read 5, iclass 21, count 0 2006.182.08:01:19.92#ibcon#about to read 6, iclass 21, count 0 2006.182.08:01:19.92#ibcon#read 6, iclass 21, count 0 2006.182.08:01:19.92#ibcon#end of sib2, iclass 21, count 0 2006.182.08:01:19.92#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:01:19.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:01:19.92#ibcon#[25=USB\r\n] 2006.182.08:01:19.92#ibcon#*before write, iclass 21, count 0 2006.182.08:01:19.92#ibcon#enter sib2, iclass 21, count 0 2006.182.08:01:19.92#ibcon#flushed, iclass 21, count 0 2006.182.08:01:19.92#ibcon#about to write, iclass 21, count 0 2006.182.08:01:19.92#ibcon#wrote, iclass 21, count 0 2006.182.08:01:19.92#ibcon#about to read 3, iclass 21, count 0 2006.182.08:01:19.95#ibcon#read 3, iclass 21, count 0 2006.182.08:01:19.95#ibcon#about to read 4, iclass 21, count 0 2006.182.08:01:19.95#ibcon#read 4, iclass 21, count 0 2006.182.08:01:19.95#ibcon#about to read 5, iclass 21, count 0 2006.182.08:01:19.95#ibcon#read 5, iclass 21, count 0 2006.182.08:01:19.95#ibcon#about to read 6, iclass 21, count 0 2006.182.08:01:19.95#ibcon#read 6, iclass 21, count 0 2006.182.08:01:19.95#ibcon#end of sib2, iclass 21, count 0 2006.182.08:01:19.95#ibcon#*after write, iclass 21, count 0 2006.182.08:01:19.95#ibcon#*before return 0, iclass 21, count 0 2006.182.08:01:19.95#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:01:19.95#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:01:19.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:01:19.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:01:19.95$vc4f8/valo=7,832.99 2006.182.08:01:19.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.08:01:19.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.08:01:19.95#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:19.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:01:19.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:01:19.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:01:19.95#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:01:19.95#ibcon#first serial, iclass 23, count 0 2006.182.08:01:19.95#ibcon#enter sib2, iclass 23, count 0 2006.182.08:01:19.95#ibcon#flushed, iclass 23, count 0 2006.182.08:01:19.95#ibcon#about to write, iclass 23, count 0 2006.182.08:01:19.95#ibcon#wrote, iclass 23, count 0 2006.182.08:01:19.95#ibcon#about to read 3, iclass 23, count 0 2006.182.08:01:19.97#ibcon#read 3, iclass 23, count 0 2006.182.08:01:19.97#ibcon#about to read 4, iclass 23, count 0 2006.182.08:01:19.97#ibcon#read 4, iclass 23, count 0 2006.182.08:01:19.97#ibcon#about to read 5, iclass 23, count 0 2006.182.08:01:19.97#ibcon#read 5, iclass 23, count 0 2006.182.08:01:19.97#ibcon#about to read 6, iclass 23, count 0 2006.182.08:01:19.97#ibcon#read 6, iclass 23, count 0 2006.182.08:01:19.97#ibcon#end of sib2, iclass 23, count 0 2006.182.08:01:19.97#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:01:19.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:01:19.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:01:19.97#ibcon#*before write, iclass 23, count 0 2006.182.08:01:19.97#ibcon#enter sib2, iclass 23, count 0 2006.182.08:01:19.97#ibcon#flushed, iclass 23, count 0 2006.182.08:01:19.97#ibcon#about to write, iclass 23, count 0 2006.182.08:01:19.97#ibcon#wrote, iclass 23, count 0 2006.182.08:01:19.97#ibcon#about to read 3, iclass 23, count 0 2006.182.08:01:20.01#ibcon#read 3, iclass 23, count 0 2006.182.08:01:20.01#ibcon#about to read 4, iclass 23, count 0 2006.182.08:01:20.01#ibcon#read 4, iclass 23, count 0 2006.182.08:01:20.01#ibcon#about to read 5, iclass 23, count 0 2006.182.08:01:20.01#ibcon#read 5, iclass 23, count 0 2006.182.08:01:20.01#ibcon#about to read 6, iclass 23, count 0 2006.182.08:01:20.01#ibcon#read 6, iclass 23, count 0 2006.182.08:01:20.01#ibcon#end of sib2, iclass 23, count 0 2006.182.08:01:20.01#ibcon#*after write, iclass 23, count 0 2006.182.08:01:20.01#ibcon#*before return 0, iclass 23, count 0 2006.182.08:01:20.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:01:20.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:01:20.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:01:20.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:01:20.01$vc4f8/va=7,6 2006.182.08:01:20.01#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.08:01:20.01#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.08:01:20.01#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:20.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:01:20.07#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:01:20.07#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:01:20.07#ibcon#enter wrdev, iclass 25, count 2 2006.182.08:01:20.07#ibcon#first serial, iclass 25, count 2 2006.182.08:01:20.07#ibcon#enter sib2, iclass 25, count 2 2006.182.08:01:20.07#ibcon#flushed, iclass 25, count 2 2006.182.08:01:20.07#ibcon#about to write, iclass 25, count 2 2006.182.08:01:20.07#ibcon#wrote, iclass 25, count 2 2006.182.08:01:20.07#ibcon#about to read 3, iclass 25, count 2 2006.182.08:01:20.09#ibcon#read 3, iclass 25, count 2 2006.182.08:01:20.09#ibcon#about to read 4, iclass 25, count 2 2006.182.08:01:20.09#ibcon#read 4, iclass 25, count 2 2006.182.08:01:20.09#ibcon#about to read 5, iclass 25, count 2 2006.182.08:01:20.09#ibcon#read 5, iclass 25, count 2 2006.182.08:01:20.09#ibcon#about to read 6, iclass 25, count 2 2006.182.08:01:20.09#ibcon#read 6, iclass 25, count 2 2006.182.08:01:20.09#ibcon#end of sib2, iclass 25, count 2 2006.182.08:01:20.09#ibcon#*mode == 0, iclass 25, count 2 2006.182.08:01:20.09#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.08:01:20.09#ibcon#[25=AT07-06\r\n] 2006.182.08:01:20.09#ibcon#*before write, iclass 25, count 2 2006.182.08:01:20.09#ibcon#enter sib2, iclass 25, count 2 2006.182.08:01:20.09#ibcon#flushed, iclass 25, count 2 2006.182.08:01:20.09#ibcon#about to write, iclass 25, count 2 2006.182.08:01:20.09#ibcon#wrote, iclass 25, count 2 2006.182.08:01:20.09#ibcon#about to read 3, iclass 25, count 2 2006.182.08:01:20.12#ibcon#read 3, iclass 25, count 2 2006.182.08:01:20.12#ibcon#about to read 4, iclass 25, count 2 2006.182.08:01:20.12#ibcon#read 4, iclass 25, count 2 2006.182.08:01:20.12#ibcon#about to read 5, iclass 25, count 2 2006.182.08:01:20.12#ibcon#read 5, iclass 25, count 2 2006.182.08:01:20.12#ibcon#about to read 6, iclass 25, count 2 2006.182.08:01:20.12#ibcon#read 6, iclass 25, count 2 2006.182.08:01:20.12#ibcon#end of sib2, iclass 25, count 2 2006.182.08:01:20.12#ibcon#*after write, iclass 25, count 2 2006.182.08:01:20.12#ibcon#*before return 0, iclass 25, count 2 2006.182.08:01:20.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:01:20.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:01:20.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.08:01:20.12#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:20.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:01:20.24#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:01:20.24#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:01:20.24#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:01:20.24#ibcon#first serial, iclass 25, count 0 2006.182.08:01:20.24#ibcon#enter sib2, iclass 25, count 0 2006.182.08:01:20.24#ibcon#flushed, iclass 25, count 0 2006.182.08:01:20.24#ibcon#about to write, iclass 25, count 0 2006.182.08:01:20.24#ibcon#wrote, iclass 25, count 0 2006.182.08:01:20.24#ibcon#about to read 3, iclass 25, count 0 2006.182.08:01:20.26#ibcon#read 3, iclass 25, count 0 2006.182.08:01:20.26#ibcon#about to read 4, iclass 25, count 0 2006.182.08:01:20.26#ibcon#read 4, iclass 25, count 0 2006.182.08:01:20.26#ibcon#about to read 5, iclass 25, count 0 2006.182.08:01:20.26#ibcon#read 5, iclass 25, count 0 2006.182.08:01:20.26#ibcon#about to read 6, iclass 25, count 0 2006.182.08:01:20.26#ibcon#read 6, iclass 25, count 0 2006.182.08:01:20.26#ibcon#end of sib2, iclass 25, count 0 2006.182.08:01:20.26#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:01:20.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:01:20.26#ibcon#[25=USB\r\n] 2006.182.08:01:20.26#ibcon#*before write, iclass 25, count 0 2006.182.08:01:20.26#ibcon#enter sib2, iclass 25, count 0 2006.182.08:01:20.26#ibcon#flushed, iclass 25, count 0 2006.182.08:01:20.26#ibcon#about to write, iclass 25, count 0 2006.182.08:01:20.26#ibcon#wrote, iclass 25, count 0 2006.182.08:01:20.26#ibcon#about to read 3, iclass 25, count 0 2006.182.08:01:20.29#ibcon#read 3, iclass 25, count 0 2006.182.08:01:20.29#ibcon#about to read 4, iclass 25, count 0 2006.182.08:01:20.29#ibcon#read 4, iclass 25, count 0 2006.182.08:01:20.29#ibcon#about to read 5, iclass 25, count 0 2006.182.08:01:20.29#ibcon#read 5, iclass 25, count 0 2006.182.08:01:20.29#ibcon#about to read 6, iclass 25, count 0 2006.182.08:01:20.29#ibcon#read 6, iclass 25, count 0 2006.182.08:01:20.29#ibcon#end of sib2, iclass 25, count 0 2006.182.08:01:20.29#ibcon#*after write, iclass 25, count 0 2006.182.08:01:20.29#ibcon#*before return 0, iclass 25, count 0 2006.182.08:01:20.29#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:01:20.29#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:01:20.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:01:20.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:01:20.29$vc4f8/valo=8,852.99 2006.182.08:01:20.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.08:01:20.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.08:01:20.29#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:20.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:01:20.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:01:20.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:01:20.29#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:01:20.29#ibcon#first serial, iclass 27, count 0 2006.182.08:01:20.29#ibcon#enter sib2, iclass 27, count 0 2006.182.08:01:20.29#ibcon#flushed, iclass 27, count 0 2006.182.08:01:20.29#ibcon#about to write, iclass 27, count 0 2006.182.08:01:20.29#ibcon#wrote, iclass 27, count 0 2006.182.08:01:20.29#ibcon#about to read 3, iclass 27, count 0 2006.182.08:01:20.31#ibcon#read 3, iclass 27, count 0 2006.182.08:01:20.31#ibcon#about to read 4, iclass 27, count 0 2006.182.08:01:20.31#ibcon#read 4, iclass 27, count 0 2006.182.08:01:20.31#ibcon#about to read 5, iclass 27, count 0 2006.182.08:01:20.31#ibcon#read 5, iclass 27, count 0 2006.182.08:01:20.31#ibcon#about to read 6, iclass 27, count 0 2006.182.08:01:20.31#ibcon#read 6, iclass 27, count 0 2006.182.08:01:20.31#ibcon#end of sib2, iclass 27, count 0 2006.182.08:01:20.31#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:01:20.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:01:20.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:01:20.31#ibcon#*before write, iclass 27, count 0 2006.182.08:01:20.31#ibcon#enter sib2, iclass 27, count 0 2006.182.08:01:20.31#ibcon#flushed, iclass 27, count 0 2006.182.08:01:20.31#ibcon#about to write, iclass 27, count 0 2006.182.08:01:20.31#ibcon#wrote, iclass 27, count 0 2006.182.08:01:20.31#ibcon#about to read 3, iclass 27, count 0 2006.182.08:01:20.35#ibcon#read 3, iclass 27, count 0 2006.182.08:01:20.35#ibcon#about to read 4, iclass 27, count 0 2006.182.08:01:20.35#ibcon#read 4, iclass 27, count 0 2006.182.08:01:20.35#ibcon#about to read 5, iclass 27, count 0 2006.182.08:01:20.35#ibcon#read 5, iclass 27, count 0 2006.182.08:01:20.35#ibcon#about to read 6, iclass 27, count 0 2006.182.08:01:20.35#ibcon#read 6, iclass 27, count 0 2006.182.08:01:20.35#ibcon#end of sib2, iclass 27, count 0 2006.182.08:01:20.35#ibcon#*after write, iclass 27, count 0 2006.182.08:01:20.35#ibcon#*before return 0, iclass 27, count 0 2006.182.08:01:20.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:01:20.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:01:20.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:01:20.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:01:20.35$vc4f8/va=8,7 2006.182.08:01:20.35#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.08:01:20.35#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.08:01:20.35#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:20.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:01:20.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:01:20.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:01:20.42#ibcon#enter wrdev, iclass 29, count 2 2006.182.08:01:20.42#ibcon#first serial, iclass 29, count 2 2006.182.08:01:20.42#ibcon#enter sib2, iclass 29, count 2 2006.182.08:01:20.42#ibcon#flushed, iclass 29, count 2 2006.182.08:01:20.42#ibcon#about to write, iclass 29, count 2 2006.182.08:01:20.42#ibcon#wrote, iclass 29, count 2 2006.182.08:01:20.42#ibcon#about to read 3, iclass 29, count 2 2006.182.08:01:20.43#ibcon#read 3, iclass 29, count 2 2006.182.08:01:20.43#ibcon#about to read 4, iclass 29, count 2 2006.182.08:01:20.43#ibcon#read 4, iclass 29, count 2 2006.182.08:01:20.43#ibcon#about to read 5, iclass 29, count 2 2006.182.08:01:20.43#ibcon#read 5, iclass 29, count 2 2006.182.08:01:20.43#ibcon#about to read 6, iclass 29, count 2 2006.182.08:01:20.43#ibcon#read 6, iclass 29, count 2 2006.182.08:01:20.43#ibcon#end of sib2, iclass 29, count 2 2006.182.08:01:20.43#ibcon#*mode == 0, iclass 29, count 2 2006.182.08:01:20.43#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.08:01:20.43#ibcon#[25=AT08-07\r\n] 2006.182.08:01:20.43#ibcon#*before write, iclass 29, count 2 2006.182.08:01:20.43#ibcon#enter sib2, iclass 29, count 2 2006.182.08:01:20.43#ibcon#flushed, iclass 29, count 2 2006.182.08:01:20.43#ibcon#about to write, iclass 29, count 2 2006.182.08:01:20.43#ibcon#wrote, iclass 29, count 2 2006.182.08:01:20.43#ibcon#about to read 3, iclass 29, count 2 2006.182.08:01:20.46#ibcon#read 3, iclass 29, count 2 2006.182.08:01:20.46#ibcon#about to read 4, iclass 29, count 2 2006.182.08:01:20.46#ibcon#read 4, iclass 29, count 2 2006.182.08:01:20.46#ibcon#about to read 5, iclass 29, count 2 2006.182.08:01:20.46#ibcon#read 5, iclass 29, count 2 2006.182.08:01:20.46#ibcon#about to read 6, iclass 29, count 2 2006.182.08:01:20.46#ibcon#read 6, iclass 29, count 2 2006.182.08:01:20.46#ibcon#end of sib2, iclass 29, count 2 2006.182.08:01:20.46#ibcon#*after write, iclass 29, count 2 2006.182.08:01:20.46#ibcon#*before return 0, iclass 29, count 2 2006.182.08:01:20.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:01:20.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:01:20.46#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.08:01:20.46#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:20.46#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:01:20.58#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:01:20.58#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:01:20.58#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:01:20.58#ibcon#first serial, iclass 29, count 0 2006.182.08:01:20.58#ibcon#enter sib2, iclass 29, count 0 2006.182.08:01:20.58#ibcon#flushed, iclass 29, count 0 2006.182.08:01:20.58#ibcon#about to write, iclass 29, count 0 2006.182.08:01:20.58#ibcon#wrote, iclass 29, count 0 2006.182.08:01:20.58#ibcon#about to read 3, iclass 29, count 0 2006.182.08:01:20.60#ibcon#read 3, iclass 29, count 0 2006.182.08:01:20.60#ibcon#about to read 4, iclass 29, count 0 2006.182.08:01:20.60#ibcon#read 4, iclass 29, count 0 2006.182.08:01:20.60#ibcon#about to read 5, iclass 29, count 0 2006.182.08:01:20.60#ibcon#read 5, iclass 29, count 0 2006.182.08:01:20.60#ibcon#about to read 6, iclass 29, count 0 2006.182.08:01:20.60#ibcon#read 6, iclass 29, count 0 2006.182.08:01:20.60#ibcon#end of sib2, iclass 29, count 0 2006.182.08:01:20.60#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:01:20.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:01:20.60#ibcon#[25=USB\r\n] 2006.182.08:01:20.60#ibcon#*before write, iclass 29, count 0 2006.182.08:01:20.60#ibcon#enter sib2, iclass 29, count 0 2006.182.08:01:20.60#ibcon#flushed, iclass 29, count 0 2006.182.08:01:20.60#ibcon#about to write, iclass 29, count 0 2006.182.08:01:20.60#ibcon#wrote, iclass 29, count 0 2006.182.08:01:20.60#ibcon#about to read 3, iclass 29, count 0 2006.182.08:01:20.63#ibcon#read 3, iclass 29, count 0 2006.182.08:01:20.63#ibcon#about to read 4, iclass 29, count 0 2006.182.08:01:20.63#ibcon#read 4, iclass 29, count 0 2006.182.08:01:20.63#ibcon#about to read 5, iclass 29, count 0 2006.182.08:01:20.63#ibcon#read 5, iclass 29, count 0 2006.182.08:01:20.63#ibcon#about to read 6, iclass 29, count 0 2006.182.08:01:20.63#ibcon#read 6, iclass 29, count 0 2006.182.08:01:20.63#ibcon#end of sib2, iclass 29, count 0 2006.182.08:01:20.63#ibcon#*after write, iclass 29, count 0 2006.182.08:01:20.63#ibcon#*before return 0, iclass 29, count 0 2006.182.08:01:20.63#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:01:20.63#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:01:20.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:01:20.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:01:20.63$vc4f8/vblo=1,632.99 2006.182.08:01:20.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.08:01:20.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.08:01:20.63#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:20.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:01:20.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:01:20.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:01:20.63#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:01:20.63#ibcon#first serial, iclass 31, count 0 2006.182.08:01:20.63#ibcon#enter sib2, iclass 31, count 0 2006.182.08:01:20.63#ibcon#flushed, iclass 31, count 0 2006.182.08:01:20.63#ibcon#about to write, iclass 31, count 0 2006.182.08:01:20.63#ibcon#wrote, iclass 31, count 0 2006.182.08:01:20.63#ibcon#about to read 3, iclass 31, count 0 2006.182.08:01:20.65#ibcon#read 3, iclass 31, count 0 2006.182.08:01:20.65#ibcon#about to read 4, iclass 31, count 0 2006.182.08:01:20.65#ibcon#read 4, iclass 31, count 0 2006.182.08:01:20.65#ibcon#about to read 5, iclass 31, count 0 2006.182.08:01:20.65#ibcon#read 5, iclass 31, count 0 2006.182.08:01:20.65#ibcon#about to read 6, iclass 31, count 0 2006.182.08:01:20.65#ibcon#read 6, iclass 31, count 0 2006.182.08:01:20.65#ibcon#end of sib2, iclass 31, count 0 2006.182.08:01:20.65#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:01:20.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:01:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:01:20.65#ibcon#*before write, iclass 31, count 0 2006.182.08:01:20.65#ibcon#enter sib2, iclass 31, count 0 2006.182.08:01:20.65#ibcon#flushed, iclass 31, count 0 2006.182.08:01:20.65#ibcon#about to write, iclass 31, count 0 2006.182.08:01:20.65#ibcon#wrote, iclass 31, count 0 2006.182.08:01:20.65#ibcon#about to read 3, iclass 31, count 0 2006.182.08:01:20.69#ibcon#read 3, iclass 31, count 0 2006.182.08:01:20.69#ibcon#about to read 4, iclass 31, count 0 2006.182.08:01:20.69#ibcon#read 4, iclass 31, count 0 2006.182.08:01:20.69#ibcon#about to read 5, iclass 31, count 0 2006.182.08:01:20.69#ibcon#read 5, iclass 31, count 0 2006.182.08:01:20.69#ibcon#about to read 6, iclass 31, count 0 2006.182.08:01:20.69#ibcon#read 6, iclass 31, count 0 2006.182.08:01:20.69#ibcon#end of sib2, iclass 31, count 0 2006.182.08:01:20.69#ibcon#*after write, iclass 31, count 0 2006.182.08:01:20.69#ibcon#*before return 0, iclass 31, count 0 2006.182.08:01:20.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:01:20.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:01:20.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:01:20.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:01:20.69$vc4f8/vb=1,4 2006.182.08:01:20.69#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.08:01:20.69#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.08:01:20.69#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:20.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:01:20.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:01:20.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:01:20.69#ibcon#enter wrdev, iclass 33, count 2 2006.182.08:01:20.69#ibcon#first serial, iclass 33, count 2 2006.182.08:01:20.69#ibcon#enter sib2, iclass 33, count 2 2006.182.08:01:20.69#ibcon#flushed, iclass 33, count 2 2006.182.08:01:20.69#ibcon#about to write, iclass 33, count 2 2006.182.08:01:20.69#ibcon#wrote, iclass 33, count 2 2006.182.08:01:20.69#ibcon#about to read 3, iclass 33, count 2 2006.182.08:01:20.71#ibcon#read 3, iclass 33, count 2 2006.182.08:01:20.71#ibcon#about to read 4, iclass 33, count 2 2006.182.08:01:20.71#ibcon#read 4, iclass 33, count 2 2006.182.08:01:20.71#ibcon#about to read 5, iclass 33, count 2 2006.182.08:01:20.71#ibcon#read 5, iclass 33, count 2 2006.182.08:01:20.71#ibcon#about to read 6, iclass 33, count 2 2006.182.08:01:20.71#ibcon#read 6, iclass 33, count 2 2006.182.08:01:20.71#ibcon#end of sib2, iclass 33, count 2 2006.182.08:01:20.71#ibcon#*mode == 0, iclass 33, count 2 2006.182.08:01:20.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.08:01:20.71#ibcon#[27=AT01-04\r\n] 2006.182.08:01:20.71#ibcon#*before write, iclass 33, count 2 2006.182.08:01:20.71#ibcon#enter sib2, iclass 33, count 2 2006.182.08:01:20.71#ibcon#flushed, iclass 33, count 2 2006.182.08:01:20.71#ibcon#about to write, iclass 33, count 2 2006.182.08:01:20.71#ibcon#wrote, iclass 33, count 2 2006.182.08:01:20.71#ibcon#about to read 3, iclass 33, count 2 2006.182.08:01:20.74#ibcon#read 3, iclass 33, count 2 2006.182.08:01:20.74#ibcon#about to read 4, iclass 33, count 2 2006.182.08:01:20.74#ibcon#read 4, iclass 33, count 2 2006.182.08:01:20.74#ibcon#about to read 5, iclass 33, count 2 2006.182.08:01:20.74#ibcon#read 5, iclass 33, count 2 2006.182.08:01:20.74#ibcon#about to read 6, iclass 33, count 2 2006.182.08:01:20.74#ibcon#read 6, iclass 33, count 2 2006.182.08:01:20.74#ibcon#end of sib2, iclass 33, count 2 2006.182.08:01:20.74#ibcon#*after write, iclass 33, count 2 2006.182.08:01:20.74#ibcon#*before return 0, iclass 33, count 2 2006.182.08:01:20.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:01:20.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:01:20.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.08:01:20.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:20.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:01:20.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:01:20.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:01:20.86#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:01:20.86#ibcon#first serial, iclass 33, count 0 2006.182.08:01:20.86#ibcon#enter sib2, iclass 33, count 0 2006.182.08:01:20.86#ibcon#flushed, iclass 33, count 0 2006.182.08:01:20.86#ibcon#about to write, iclass 33, count 0 2006.182.08:01:20.86#ibcon#wrote, iclass 33, count 0 2006.182.08:01:20.86#ibcon#about to read 3, iclass 33, count 0 2006.182.08:01:20.88#ibcon#read 3, iclass 33, count 0 2006.182.08:01:20.88#ibcon#about to read 4, iclass 33, count 0 2006.182.08:01:20.88#ibcon#read 4, iclass 33, count 0 2006.182.08:01:20.88#ibcon#about to read 5, iclass 33, count 0 2006.182.08:01:20.88#ibcon#read 5, iclass 33, count 0 2006.182.08:01:20.88#ibcon#about to read 6, iclass 33, count 0 2006.182.08:01:20.88#ibcon#read 6, iclass 33, count 0 2006.182.08:01:20.88#ibcon#end of sib2, iclass 33, count 0 2006.182.08:01:20.88#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:01:20.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:01:20.88#ibcon#[27=USB\r\n] 2006.182.08:01:20.88#ibcon#*before write, iclass 33, count 0 2006.182.08:01:20.88#ibcon#enter sib2, iclass 33, count 0 2006.182.08:01:20.88#ibcon#flushed, iclass 33, count 0 2006.182.08:01:20.88#ibcon#about to write, iclass 33, count 0 2006.182.08:01:20.88#ibcon#wrote, iclass 33, count 0 2006.182.08:01:20.88#ibcon#about to read 3, iclass 33, count 0 2006.182.08:01:20.91#ibcon#read 3, iclass 33, count 0 2006.182.08:01:20.91#ibcon#about to read 4, iclass 33, count 0 2006.182.08:01:20.91#ibcon#read 4, iclass 33, count 0 2006.182.08:01:20.91#ibcon#about to read 5, iclass 33, count 0 2006.182.08:01:20.91#ibcon#read 5, iclass 33, count 0 2006.182.08:01:20.91#ibcon#about to read 6, iclass 33, count 0 2006.182.08:01:20.91#ibcon#read 6, iclass 33, count 0 2006.182.08:01:20.91#ibcon#end of sib2, iclass 33, count 0 2006.182.08:01:20.91#ibcon#*after write, iclass 33, count 0 2006.182.08:01:20.91#ibcon#*before return 0, iclass 33, count 0 2006.182.08:01:20.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:01:20.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:01:20.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:01:20.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:01:20.91$vc4f8/vblo=2,640.99 2006.182.08:01:20.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.08:01:20.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.08:01:20.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:20.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:20.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:20.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:20.91#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:01:20.91#ibcon#first serial, iclass 35, count 0 2006.182.08:01:20.91#ibcon#enter sib2, iclass 35, count 0 2006.182.08:01:20.91#ibcon#flushed, iclass 35, count 0 2006.182.08:01:20.91#ibcon#about to write, iclass 35, count 0 2006.182.08:01:20.91#ibcon#wrote, iclass 35, count 0 2006.182.08:01:20.91#ibcon#about to read 3, iclass 35, count 0 2006.182.08:01:20.93#ibcon#read 3, iclass 35, count 0 2006.182.08:01:20.93#ibcon#about to read 4, iclass 35, count 0 2006.182.08:01:20.93#ibcon#read 4, iclass 35, count 0 2006.182.08:01:20.93#ibcon#about to read 5, iclass 35, count 0 2006.182.08:01:20.93#ibcon#read 5, iclass 35, count 0 2006.182.08:01:20.93#ibcon#about to read 6, iclass 35, count 0 2006.182.08:01:20.93#ibcon#read 6, iclass 35, count 0 2006.182.08:01:20.93#ibcon#end of sib2, iclass 35, count 0 2006.182.08:01:20.93#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:01:20.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:01:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:01:20.93#ibcon#*before write, iclass 35, count 0 2006.182.08:01:20.93#ibcon#enter sib2, iclass 35, count 0 2006.182.08:01:20.93#ibcon#flushed, iclass 35, count 0 2006.182.08:01:20.93#ibcon#about to write, iclass 35, count 0 2006.182.08:01:20.93#ibcon#wrote, iclass 35, count 0 2006.182.08:01:20.93#ibcon#about to read 3, iclass 35, count 0 2006.182.08:01:20.97#ibcon#read 3, iclass 35, count 0 2006.182.08:01:20.97#ibcon#about to read 4, iclass 35, count 0 2006.182.08:01:20.97#ibcon#read 4, iclass 35, count 0 2006.182.08:01:20.97#ibcon#about to read 5, iclass 35, count 0 2006.182.08:01:20.97#ibcon#read 5, iclass 35, count 0 2006.182.08:01:20.97#ibcon#about to read 6, iclass 35, count 0 2006.182.08:01:20.97#ibcon#read 6, iclass 35, count 0 2006.182.08:01:20.97#ibcon#end of sib2, iclass 35, count 0 2006.182.08:01:20.97#ibcon#*after write, iclass 35, count 0 2006.182.08:01:20.97#ibcon#*before return 0, iclass 35, count 0 2006.182.08:01:20.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:20.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:01:20.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:01:20.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:01:20.97$vc4f8/vb=2,4 2006.182.08:01:20.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.08:01:20.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.08:01:20.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:20.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:21.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:21.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:21.03#ibcon#enter wrdev, iclass 37, count 2 2006.182.08:01:21.03#ibcon#first serial, iclass 37, count 2 2006.182.08:01:21.03#ibcon#enter sib2, iclass 37, count 2 2006.182.08:01:21.03#ibcon#flushed, iclass 37, count 2 2006.182.08:01:21.03#ibcon#about to write, iclass 37, count 2 2006.182.08:01:21.03#ibcon#wrote, iclass 37, count 2 2006.182.08:01:21.03#ibcon#about to read 3, iclass 37, count 2 2006.182.08:01:21.05#ibcon#read 3, iclass 37, count 2 2006.182.08:01:21.05#ibcon#about to read 4, iclass 37, count 2 2006.182.08:01:21.05#ibcon#read 4, iclass 37, count 2 2006.182.08:01:21.05#ibcon#about to read 5, iclass 37, count 2 2006.182.08:01:21.05#ibcon#read 5, iclass 37, count 2 2006.182.08:01:21.05#ibcon#about to read 6, iclass 37, count 2 2006.182.08:01:21.05#ibcon#read 6, iclass 37, count 2 2006.182.08:01:21.05#ibcon#end of sib2, iclass 37, count 2 2006.182.08:01:21.05#ibcon#*mode == 0, iclass 37, count 2 2006.182.08:01:21.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.08:01:21.05#ibcon#[27=AT02-04\r\n] 2006.182.08:01:21.05#ibcon#*before write, iclass 37, count 2 2006.182.08:01:21.05#ibcon#enter sib2, iclass 37, count 2 2006.182.08:01:21.05#ibcon#flushed, iclass 37, count 2 2006.182.08:01:21.05#ibcon#about to write, iclass 37, count 2 2006.182.08:01:21.05#ibcon#wrote, iclass 37, count 2 2006.182.08:01:21.05#ibcon#about to read 3, iclass 37, count 2 2006.182.08:01:21.08#ibcon#read 3, iclass 37, count 2 2006.182.08:01:21.08#ibcon#about to read 4, iclass 37, count 2 2006.182.08:01:21.08#ibcon#read 4, iclass 37, count 2 2006.182.08:01:21.08#ibcon#about to read 5, iclass 37, count 2 2006.182.08:01:21.08#ibcon#read 5, iclass 37, count 2 2006.182.08:01:21.08#ibcon#about to read 6, iclass 37, count 2 2006.182.08:01:21.08#ibcon#read 6, iclass 37, count 2 2006.182.08:01:21.08#ibcon#end of sib2, iclass 37, count 2 2006.182.08:01:21.08#ibcon#*after write, iclass 37, count 2 2006.182.08:01:21.08#ibcon#*before return 0, iclass 37, count 2 2006.182.08:01:21.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:21.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:01:21.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.08:01:21.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:21.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:21.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:21.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:21.20#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:01:21.20#ibcon#first serial, iclass 37, count 0 2006.182.08:01:21.20#ibcon#enter sib2, iclass 37, count 0 2006.182.08:01:21.20#ibcon#flushed, iclass 37, count 0 2006.182.08:01:21.20#ibcon#about to write, iclass 37, count 0 2006.182.08:01:21.20#ibcon#wrote, iclass 37, count 0 2006.182.08:01:21.20#ibcon#about to read 3, iclass 37, count 0 2006.182.08:01:21.24#ibcon#read 3, iclass 37, count 0 2006.182.08:01:21.24#ibcon#about to read 4, iclass 37, count 0 2006.182.08:01:21.24#ibcon#read 4, iclass 37, count 0 2006.182.08:01:21.24#ibcon#about to read 5, iclass 37, count 0 2006.182.08:01:21.24#ibcon#read 5, iclass 37, count 0 2006.182.08:01:21.24#ibcon#about to read 6, iclass 37, count 0 2006.182.08:01:21.24#ibcon#read 6, iclass 37, count 0 2006.182.08:01:21.24#ibcon#end of sib2, iclass 37, count 0 2006.182.08:01:21.24#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:01:21.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:01:21.24#ibcon#[27=USB\r\n] 2006.182.08:01:21.24#ibcon#*before write, iclass 37, count 0 2006.182.08:01:21.24#ibcon#enter sib2, iclass 37, count 0 2006.182.08:01:21.24#ibcon#flushed, iclass 37, count 0 2006.182.08:01:21.24#ibcon#about to write, iclass 37, count 0 2006.182.08:01:21.24#ibcon#wrote, iclass 37, count 0 2006.182.08:01:21.24#ibcon#about to read 3, iclass 37, count 0 2006.182.08:01:21.26#ibcon#read 3, iclass 37, count 0 2006.182.08:01:21.26#ibcon#about to read 4, iclass 37, count 0 2006.182.08:01:21.26#ibcon#read 4, iclass 37, count 0 2006.182.08:01:21.26#ibcon#about to read 5, iclass 37, count 0 2006.182.08:01:21.26#ibcon#read 5, iclass 37, count 0 2006.182.08:01:21.26#ibcon#about to read 6, iclass 37, count 0 2006.182.08:01:21.26#ibcon#read 6, iclass 37, count 0 2006.182.08:01:21.26#ibcon#end of sib2, iclass 37, count 0 2006.182.08:01:21.26#ibcon#*after write, iclass 37, count 0 2006.182.08:01:21.26#ibcon#*before return 0, iclass 37, count 0 2006.182.08:01:21.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:21.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:01:21.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:01:21.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:01:21.26$vc4f8/vblo=3,656.99 2006.182.08:01:21.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.08:01:21.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.08:01:21.26#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:21.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:21.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:21.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:21.26#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:01:21.26#ibcon#first serial, iclass 39, count 0 2006.182.08:01:21.26#ibcon#enter sib2, iclass 39, count 0 2006.182.08:01:21.26#ibcon#flushed, iclass 39, count 0 2006.182.08:01:21.26#ibcon#about to write, iclass 39, count 0 2006.182.08:01:21.26#ibcon#wrote, iclass 39, count 0 2006.182.08:01:21.26#ibcon#about to read 3, iclass 39, count 0 2006.182.08:01:21.28#ibcon#read 3, iclass 39, count 0 2006.182.08:01:21.28#ibcon#about to read 4, iclass 39, count 0 2006.182.08:01:21.28#ibcon#read 4, iclass 39, count 0 2006.182.08:01:21.28#ibcon#about to read 5, iclass 39, count 0 2006.182.08:01:21.28#ibcon#read 5, iclass 39, count 0 2006.182.08:01:21.28#ibcon#about to read 6, iclass 39, count 0 2006.182.08:01:21.28#ibcon#read 6, iclass 39, count 0 2006.182.08:01:21.28#ibcon#end of sib2, iclass 39, count 0 2006.182.08:01:21.28#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:01:21.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:01:21.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:01:21.28#ibcon#*before write, iclass 39, count 0 2006.182.08:01:21.28#ibcon#enter sib2, iclass 39, count 0 2006.182.08:01:21.28#ibcon#flushed, iclass 39, count 0 2006.182.08:01:21.28#ibcon#about to write, iclass 39, count 0 2006.182.08:01:21.28#ibcon#wrote, iclass 39, count 0 2006.182.08:01:21.28#ibcon#about to read 3, iclass 39, count 0 2006.182.08:01:21.32#ibcon#read 3, iclass 39, count 0 2006.182.08:01:21.32#ibcon#about to read 4, iclass 39, count 0 2006.182.08:01:21.32#ibcon#read 4, iclass 39, count 0 2006.182.08:01:21.32#ibcon#about to read 5, iclass 39, count 0 2006.182.08:01:21.32#ibcon#read 5, iclass 39, count 0 2006.182.08:01:21.32#ibcon#about to read 6, iclass 39, count 0 2006.182.08:01:21.32#ibcon#read 6, iclass 39, count 0 2006.182.08:01:21.32#ibcon#end of sib2, iclass 39, count 0 2006.182.08:01:21.32#ibcon#*after write, iclass 39, count 0 2006.182.08:01:21.32#ibcon#*before return 0, iclass 39, count 0 2006.182.08:01:21.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:21.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:01:21.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:01:21.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:01:21.32$vc4f8/vb=3,4 2006.182.08:01:21.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.08:01:21.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.08:01:21.32#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:21.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:21.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:21.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:21.38#ibcon#enter wrdev, iclass 3, count 2 2006.182.08:01:21.38#ibcon#first serial, iclass 3, count 2 2006.182.08:01:21.38#ibcon#enter sib2, iclass 3, count 2 2006.182.08:01:21.38#ibcon#flushed, iclass 3, count 2 2006.182.08:01:21.38#ibcon#about to write, iclass 3, count 2 2006.182.08:01:21.38#ibcon#wrote, iclass 3, count 2 2006.182.08:01:21.38#ibcon#about to read 3, iclass 3, count 2 2006.182.08:01:21.40#ibcon#read 3, iclass 3, count 2 2006.182.08:01:21.40#ibcon#about to read 4, iclass 3, count 2 2006.182.08:01:21.40#ibcon#read 4, iclass 3, count 2 2006.182.08:01:21.40#ibcon#about to read 5, iclass 3, count 2 2006.182.08:01:21.40#ibcon#read 5, iclass 3, count 2 2006.182.08:01:21.40#ibcon#about to read 6, iclass 3, count 2 2006.182.08:01:21.40#ibcon#read 6, iclass 3, count 2 2006.182.08:01:21.40#ibcon#end of sib2, iclass 3, count 2 2006.182.08:01:21.40#ibcon#*mode == 0, iclass 3, count 2 2006.182.08:01:21.40#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.08:01:21.40#ibcon#[27=AT03-04\r\n] 2006.182.08:01:21.40#ibcon#*before write, iclass 3, count 2 2006.182.08:01:21.40#ibcon#enter sib2, iclass 3, count 2 2006.182.08:01:21.40#ibcon#flushed, iclass 3, count 2 2006.182.08:01:21.40#ibcon#about to write, iclass 3, count 2 2006.182.08:01:21.40#ibcon#wrote, iclass 3, count 2 2006.182.08:01:21.40#ibcon#about to read 3, iclass 3, count 2 2006.182.08:01:21.43#ibcon#read 3, iclass 3, count 2 2006.182.08:01:21.43#ibcon#about to read 4, iclass 3, count 2 2006.182.08:01:21.43#ibcon#read 4, iclass 3, count 2 2006.182.08:01:21.43#ibcon#about to read 5, iclass 3, count 2 2006.182.08:01:21.43#ibcon#read 5, iclass 3, count 2 2006.182.08:01:21.43#ibcon#about to read 6, iclass 3, count 2 2006.182.08:01:21.43#ibcon#read 6, iclass 3, count 2 2006.182.08:01:21.43#ibcon#end of sib2, iclass 3, count 2 2006.182.08:01:21.43#ibcon#*after write, iclass 3, count 2 2006.182.08:01:21.43#ibcon#*before return 0, iclass 3, count 2 2006.182.08:01:21.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:21.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:01:21.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.08:01:21.43#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:21.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:21.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:21.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:21.55#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:01:21.55#ibcon#first serial, iclass 3, count 0 2006.182.08:01:21.55#ibcon#enter sib2, iclass 3, count 0 2006.182.08:01:21.55#ibcon#flushed, iclass 3, count 0 2006.182.08:01:21.55#ibcon#about to write, iclass 3, count 0 2006.182.08:01:21.55#ibcon#wrote, iclass 3, count 0 2006.182.08:01:21.55#ibcon#about to read 3, iclass 3, count 0 2006.182.08:01:21.57#ibcon#read 3, iclass 3, count 0 2006.182.08:01:21.57#ibcon#about to read 4, iclass 3, count 0 2006.182.08:01:21.57#ibcon#read 4, iclass 3, count 0 2006.182.08:01:21.57#ibcon#about to read 5, iclass 3, count 0 2006.182.08:01:21.57#ibcon#read 5, iclass 3, count 0 2006.182.08:01:21.57#ibcon#about to read 6, iclass 3, count 0 2006.182.08:01:21.57#ibcon#read 6, iclass 3, count 0 2006.182.08:01:21.57#ibcon#end of sib2, iclass 3, count 0 2006.182.08:01:21.57#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:01:21.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:01:21.57#ibcon#[27=USB\r\n] 2006.182.08:01:21.57#ibcon#*before write, iclass 3, count 0 2006.182.08:01:21.57#ibcon#enter sib2, iclass 3, count 0 2006.182.08:01:21.57#ibcon#flushed, iclass 3, count 0 2006.182.08:01:21.57#ibcon#about to write, iclass 3, count 0 2006.182.08:01:21.57#ibcon#wrote, iclass 3, count 0 2006.182.08:01:21.57#ibcon#about to read 3, iclass 3, count 0 2006.182.08:01:21.60#ibcon#read 3, iclass 3, count 0 2006.182.08:01:21.60#ibcon#about to read 4, iclass 3, count 0 2006.182.08:01:21.60#ibcon#read 4, iclass 3, count 0 2006.182.08:01:21.60#ibcon#about to read 5, iclass 3, count 0 2006.182.08:01:21.60#ibcon#read 5, iclass 3, count 0 2006.182.08:01:21.60#ibcon#about to read 6, iclass 3, count 0 2006.182.08:01:21.60#ibcon#read 6, iclass 3, count 0 2006.182.08:01:21.60#ibcon#end of sib2, iclass 3, count 0 2006.182.08:01:21.60#ibcon#*after write, iclass 3, count 0 2006.182.08:01:21.60#ibcon#*before return 0, iclass 3, count 0 2006.182.08:01:21.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:21.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:01:21.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:01:21.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:01:21.60$vc4f8/vblo=4,712.99 2006.182.08:01:21.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.08:01:21.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.08:01:21.60#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:21.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:21.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:21.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:21.60#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:01:21.60#ibcon#first serial, iclass 5, count 0 2006.182.08:01:21.60#ibcon#enter sib2, iclass 5, count 0 2006.182.08:01:21.60#ibcon#flushed, iclass 5, count 0 2006.182.08:01:21.60#ibcon#about to write, iclass 5, count 0 2006.182.08:01:21.60#ibcon#wrote, iclass 5, count 0 2006.182.08:01:21.60#ibcon#about to read 3, iclass 5, count 0 2006.182.08:01:21.62#ibcon#read 3, iclass 5, count 0 2006.182.08:01:21.62#ibcon#about to read 4, iclass 5, count 0 2006.182.08:01:21.62#ibcon#read 4, iclass 5, count 0 2006.182.08:01:21.62#ibcon#about to read 5, iclass 5, count 0 2006.182.08:01:21.62#ibcon#read 5, iclass 5, count 0 2006.182.08:01:21.62#ibcon#about to read 6, iclass 5, count 0 2006.182.08:01:21.62#ibcon#read 6, iclass 5, count 0 2006.182.08:01:21.62#ibcon#end of sib2, iclass 5, count 0 2006.182.08:01:21.62#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:01:21.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:01:21.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:01:21.62#ibcon#*before write, iclass 5, count 0 2006.182.08:01:21.62#ibcon#enter sib2, iclass 5, count 0 2006.182.08:01:21.62#ibcon#flushed, iclass 5, count 0 2006.182.08:01:21.62#ibcon#about to write, iclass 5, count 0 2006.182.08:01:21.62#ibcon#wrote, iclass 5, count 0 2006.182.08:01:21.62#ibcon#about to read 3, iclass 5, count 0 2006.182.08:01:21.66#ibcon#read 3, iclass 5, count 0 2006.182.08:01:21.66#ibcon#about to read 4, iclass 5, count 0 2006.182.08:01:21.66#ibcon#read 4, iclass 5, count 0 2006.182.08:01:21.66#ibcon#about to read 5, iclass 5, count 0 2006.182.08:01:21.66#ibcon#read 5, iclass 5, count 0 2006.182.08:01:21.66#ibcon#about to read 6, iclass 5, count 0 2006.182.08:01:21.66#ibcon#read 6, iclass 5, count 0 2006.182.08:01:21.66#ibcon#end of sib2, iclass 5, count 0 2006.182.08:01:21.66#ibcon#*after write, iclass 5, count 0 2006.182.08:01:21.66#ibcon#*before return 0, iclass 5, count 0 2006.182.08:01:21.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:21.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:01:21.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:01:21.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:01:21.66$vc4f8/vb=4,4 2006.182.08:01:21.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.08:01:21.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.08:01:21.66#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:21.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:21.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:21.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:21.72#ibcon#enter wrdev, iclass 7, count 2 2006.182.08:01:21.72#ibcon#first serial, iclass 7, count 2 2006.182.08:01:21.72#ibcon#enter sib2, iclass 7, count 2 2006.182.08:01:21.72#ibcon#flushed, iclass 7, count 2 2006.182.08:01:21.72#ibcon#about to write, iclass 7, count 2 2006.182.08:01:21.72#ibcon#wrote, iclass 7, count 2 2006.182.08:01:21.72#ibcon#about to read 3, iclass 7, count 2 2006.182.08:01:21.74#ibcon#read 3, iclass 7, count 2 2006.182.08:01:21.74#ibcon#about to read 4, iclass 7, count 2 2006.182.08:01:21.74#ibcon#read 4, iclass 7, count 2 2006.182.08:01:21.74#ibcon#about to read 5, iclass 7, count 2 2006.182.08:01:21.74#ibcon#read 5, iclass 7, count 2 2006.182.08:01:21.74#ibcon#about to read 6, iclass 7, count 2 2006.182.08:01:21.74#ibcon#read 6, iclass 7, count 2 2006.182.08:01:21.74#ibcon#end of sib2, iclass 7, count 2 2006.182.08:01:21.74#ibcon#*mode == 0, iclass 7, count 2 2006.182.08:01:21.74#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.08:01:21.74#ibcon#[27=AT04-04\r\n] 2006.182.08:01:21.74#ibcon#*before write, iclass 7, count 2 2006.182.08:01:21.74#ibcon#enter sib2, iclass 7, count 2 2006.182.08:01:21.74#ibcon#flushed, iclass 7, count 2 2006.182.08:01:21.74#ibcon#about to write, iclass 7, count 2 2006.182.08:01:21.74#ibcon#wrote, iclass 7, count 2 2006.182.08:01:21.74#ibcon#about to read 3, iclass 7, count 2 2006.182.08:01:21.77#ibcon#read 3, iclass 7, count 2 2006.182.08:01:21.77#ibcon#about to read 4, iclass 7, count 2 2006.182.08:01:21.77#ibcon#read 4, iclass 7, count 2 2006.182.08:01:21.77#ibcon#about to read 5, iclass 7, count 2 2006.182.08:01:21.77#ibcon#read 5, iclass 7, count 2 2006.182.08:01:21.77#ibcon#about to read 6, iclass 7, count 2 2006.182.08:01:21.77#ibcon#read 6, iclass 7, count 2 2006.182.08:01:21.77#ibcon#end of sib2, iclass 7, count 2 2006.182.08:01:21.77#ibcon#*after write, iclass 7, count 2 2006.182.08:01:21.77#ibcon#*before return 0, iclass 7, count 2 2006.182.08:01:21.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:21.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:01:21.77#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.08:01:21.77#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:21.77#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:21.89#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:21.89#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:21.89#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:01:21.89#ibcon#first serial, iclass 7, count 0 2006.182.08:01:21.89#ibcon#enter sib2, iclass 7, count 0 2006.182.08:01:21.89#ibcon#flushed, iclass 7, count 0 2006.182.08:01:21.89#ibcon#about to write, iclass 7, count 0 2006.182.08:01:21.89#ibcon#wrote, iclass 7, count 0 2006.182.08:01:21.89#ibcon#about to read 3, iclass 7, count 0 2006.182.08:01:21.91#ibcon#read 3, iclass 7, count 0 2006.182.08:01:21.91#ibcon#about to read 4, iclass 7, count 0 2006.182.08:01:21.91#ibcon#read 4, iclass 7, count 0 2006.182.08:01:21.91#ibcon#about to read 5, iclass 7, count 0 2006.182.08:01:21.91#ibcon#read 5, iclass 7, count 0 2006.182.08:01:21.91#ibcon#about to read 6, iclass 7, count 0 2006.182.08:01:21.91#ibcon#read 6, iclass 7, count 0 2006.182.08:01:21.91#ibcon#end of sib2, iclass 7, count 0 2006.182.08:01:21.91#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:01:21.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:01:21.91#ibcon#[27=USB\r\n] 2006.182.08:01:21.91#ibcon#*before write, iclass 7, count 0 2006.182.08:01:21.91#ibcon#enter sib2, iclass 7, count 0 2006.182.08:01:21.91#ibcon#flushed, iclass 7, count 0 2006.182.08:01:21.91#ibcon#about to write, iclass 7, count 0 2006.182.08:01:21.91#ibcon#wrote, iclass 7, count 0 2006.182.08:01:21.91#ibcon#about to read 3, iclass 7, count 0 2006.182.08:01:21.94#ibcon#read 3, iclass 7, count 0 2006.182.08:01:21.94#ibcon#about to read 4, iclass 7, count 0 2006.182.08:01:21.94#ibcon#read 4, iclass 7, count 0 2006.182.08:01:21.94#ibcon#about to read 5, iclass 7, count 0 2006.182.08:01:21.94#ibcon#read 5, iclass 7, count 0 2006.182.08:01:21.94#ibcon#about to read 6, iclass 7, count 0 2006.182.08:01:21.94#ibcon#read 6, iclass 7, count 0 2006.182.08:01:21.94#ibcon#end of sib2, iclass 7, count 0 2006.182.08:01:21.94#ibcon#*after write, iclass 7, count 0 2006.182.08:01:21.94#ibcon#*before return 0, iclass 7, count 0 2006.182.08:01:21.94#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:21.94#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:01:21.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:01:21.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:01:21.94$vc4f8/vblo=5,744.99 2006.182.08:01:21.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.08:01:21.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.08:01:21.94#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:21.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:21.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:21.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:21.94#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:01:21.94#ibcon#first serial, iclass 11, count 0 2006.182.08:01:21.94#ibcon#enter sib2, iclass 11, count 0 2006.182.08:01:21.94#ibcon#flushed, iclass 11, count 0 2006.182.08:01:21.94#ibcon#about to write, iclass 11, count 0 2006.182.08:01:21.94#ibcon#wrote, iclass 11, count 0 2006.182.08:01:21.94#ibcon#about to read 3, iclass 11, count 0 2006.182.08:01:21.96#ibcon#read 3, iclass 11, count 0 2006.182.08:01:21.96#ibcon#about to read 4, iclass 11, count 0 2006.182.08:01:21.96#ibcon#read 4, iclass 11, count 0 2006.182.08:01:21.96#ibcon#about to read 5, iclass 11, count 0 2006.182.08:01:21.96#ibcon#read 5, iclass 11, count 0 2006.182.08:01:21.96#ibcon#about to read 6, iclass 11, count 0 2006.182.08:01:21.96#ibcon#read 6, iclass 11, count 0 2006.182.08:01:21.96#ibcon#end of sib2, iclass 11, count 0 2006.182.08:01:21.96#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:01:21.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:01:21.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:01:21.96#ibcon#*before write, iclass 11, count 0 2006.182.08:01:21.96#ibcon#enter sib2, iclass 11, count 0 2006.182.08:01:21.96#ibcon#flushed, iclass 11, count 0 2006.182.08:01:21.96#ibcon#about to write, iclass 11, count 0 2006.182.08:01:21.96#ibcon#wrote, iclass 11, count 0 2006.182.08:01:21.96#ibcon#about to read 3, iclass 11, count 0 2006.182.08:01:22.00#ibcon#read 3, iclass 11, count 0 2006.182.08:01:22.00#ibcon#about to read 4, iclass 11, count 0 2006.182.08:01:22.00#ibcon#read 4, iclass 11, count 0 2006.182.08:01:22.00#ibcon#about to read 5, iclass 11, count 0 2006.182.08:01:22.00#ibcon#read 5, iclass 11, count 0 2006.182.08:01:22.00#ibcon#about to read 6, iclass 11, count 0 2006.182.08:01:22.00#ibcon#read 6, iclass 11, count 0 2006.182.08:01:22.00#ibcon#end of sib2, iclass 11, count 0 2006.182.08:01:22.00#ibcon#*after write, iclass 11, count 0 2006.182.08:01:22.00#ibcon#*before return 0, iclass 11, count 0 2006.182.08:01:22.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:22.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:01:22.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:01:22.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:01:22.00$vc4f8/vb=5,4 2006.182.08:01:22.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.08:01:22.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.08:01:22.00#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:22.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:22.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:22.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:22.07#ibcon#enter wrdev, iclass 13, count 2 2006.182.08:01:22.07#ibcon#first serial, iclass 13, count 2 2006.182.08:01:22.07#ibcon#enter sib2, iclass 13, count 2 2006.182.08:01:22.07#ibcon#flushed, iclass 13, count 2 2006.182.08:01:22.07#ibcon#about to write, iclass 13, count 2 2006.182.08:01:22.07#ibcon#wrote, iclass 13, count 2 2006.182.08:01:22.07#ibcon#about to read 3, iclass 13, count 2 2006.182.08:01:22.08#ibcon#read 3, iclass 13, count 2 2006.182.08:01:22.08#ibcon#about to read 4, iclass 13, count 2 2006.182.08:01:22.08#ibcon#read 4, iclass 13, count 2 2006.182.08:01:22.08#ibcon#about to read 5, iclass 13, count 2 2006.182.08:01:22.08#ibcon#read 5, iclass 13, count 2 2006.182.08:01:22.08#ibcon#about to read 6, iclass 13, count 2 2006.182.08:01:22.08#ibcon#read 6, iclass 13, count 2 2006.182.08:01:22.08#ibcon#end of sib2, iclass 13, count 2 2006.182.08:01:22.08#ibcon#*mode == 0, iclass 13, count 2 2006.182.08:01:22.08#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.08:01:22.08#ibcon#[27=AT05-04\r\n] 2006.182.08:01:22.08#ibcon#*before write, iclass 13, count 2 2006.182.08:01:22.08#ibcon#enter sib2, iclass 13, count 2 2006.182.08:01:22.08#ibcon#flushed, iclass 13, count 2 2006.182.08:01:22.08#ibcon#about to write, iclass 13, count 2 2006.182.08:01:22.08#ibcon#wrote, iclass 13, count 2 2006.182.08:01:22.08#ibcon#about to read 3, iclass 13, count 2 2006.182.08:01:22.11#ibcon#read 3, iclass 13, count 2 2006.182.08:01:22.11#ibcon#about to read 4, iclass 13, count 2 2006.182.08:01:22.11#ibcon#read 4, iclass 13, count 2 2006.182.08:01:22.11#ibcon#about to read 5, iclass 13, count 2 2006.182.08:01:22.11#ibcon#read 5, iclass 13, count 2 2006.182.08:01:22.11#ibcon#about to read 6, iclass 13, count 2 2006.182.08:01:22.11#ibcon#read 6, iclass 13, count 2 2006.182.08:01:22.11#ibcon#end of sib2, iclass 13, count 2 2006.182.08:01:22.11#ibcon#*after write, iclass 13, count 2 2006.182.08:01:22.11#ibcon#*before return 0, iclass 13, count 2 2006.182.08:01:22.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:22.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:01:22.11#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.08:01:22.11#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:22.11#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:22.23#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:22.23#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:22.23#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:01:22.23#ibcon#first serial, iclass 13, count 0 2006.182.08:01:22.23#ibcon#enter sib2, iclass 13, count 0 2006.182.08:01:22.23#ibcon#flushed, iclass 13, count 0 2006.182.08:01:22.23#ibcon#about to write, iclass 13, count 0 2006.182.08:01:22.23#ibcon#wrote, iclass 13, count 0 2006.182.08:01:22.23#ibcon#about to read 3, iclass 13, count 0 2006.182.08:01:22.25#ibcon#read 3, iclass 13, count 0 2006.182.08:01:22.25#ibcon#about to read 4, iclass 13, count 0 2006.182.08:01:22.25#ibcon#read 4, iclass 13, count 0 2006.182.08:01:22.25#ibcon#about to read 5, iclass 13, count 0 2006.182.08:01:22.25#ibcon#read 5, iclass 13, count 0 2006.182.08:01:22.25#ibcon#about to read 6, iclass 13, count 0 2006.182.08:01:22.25#ibcon#read 6, iclass 13, count 0 2006.182.08:01:22.25#ibcon#end of sib2, iclass 13, count 0 2006.182.08:01:22.25#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:01:22.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:01:22.25#ibcon#[27=USB\r\n] 2006.182.08:01:22.25#ibcon#*before write, iclass 13, count 0 2006.182.08:01:22.25#ibcon#enter sib2, iclass 13, count 0 2006.182.08:01:22.25#ibcon#flushed, iclass 13, count 0 2006.182.08:01:22.25#ibcon#about to write, iclass 13, count 0 2006.182.08:01:22.25#ibcon#wrote, iclass 13, count 0 2006.182.08:01:22.25#ibcon#about to read 3, iclass 13, count 0 2006.182.08:01:22.28#ibcon#read 3, iclass 13, count 0 2006.182.08:01:22.28#ibcon#about to read 4, iclass 13, count 0 2006.182.08:01:22.28#ibcon#read 4, iclass 13, count 0 2006.182.08:01:22.28#ibcon#about to read 5, iclass 13, count 0 2006.182.08:01:22.28#ibcon#read 5, iclass 13, count 0 2006.182.08:01:22.28#ibcon#about to read 6, iclass 13, count 0 2006.182.08:01:22.28#ibcon#read 6, iclass 13, count 0 2006.182.08:01:22.28#ibcon#end of sib2, iclass 13, count 0 2006.182.08:01:22.28#ibcon#*after write, iclass 13, count 0 2006.182.08:01:22.28#ibcon#*before return 0, iclass 13, count 0 2006.182.08:01:22.28#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:22.28#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:01:22.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:01:22.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:01:22.28$vc4f8/vblo=6,752.99 2006.182.08:01:22.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.08:01:22.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.08:01:22.28#ibcon#ireg 17 cls_cnt 0 2006.182.08:01:22.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:22.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:22.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:22.28#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:01:22.28#ibcon#first serial, iclass 15, count 0 2006.182.08:01:22.28#ibcon#enter sib2, iclass 15, count 0 2006.182.08:01:22.28#ibcon#flushed, iclass 15, count 0 2006.182.08:01:22.28#ibcon#about to write, iclass 15, count 0 2006.182.08:01:22.28#ibcon#wrote, iclass 15, count 0 2006.182.08:01:22.28#ibcon#about to read 3, iclass 15, count 0 2006.182.08:01:22.30#ibcon#read 3, iclass 15, count 0 2006.182.08:01:22.30#ibcon#about to read 4, iclass 15, count 0 2006.182.08:01:22.30#ibcon#read 4, iclass 15, count 0 2006.182.08:01:22.30#ibcon#about to read 5, iclass 15, count 0 2006.182.08:01:22.30#ibcon#read 5, iclass 15, count 0 2006.182.08:01:22.30#ibcon#about to read 6, iclass 15, count 0 2006.182.08:01:22.30#ibcon#read 6, iclass 15, count 0 2006.182.08:01:22.30#ibcon#end of sib2, iclass 15, count 0 2006.182.08:01:22.30#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:01:22.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:01:22.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:01:22.30#ibcon#*before write, iclass 15, count 0 2006.182.08:01:22.30#ibcon#enter sib2, iclass 15, count 0 2006.182.08:01:22.30#ibcon#flushed, iclass 15, count 0 2006.182.08:01:22.30#ibcon#about to write, iclass 15, count 0 2006.182.08:01:22.30#ibcon#wrote, iclass 15, count 0 2006.182.08:01:22.30#ibcon#about to read 3, iclass 15, count 0 2006.182.08:01:22.34#ibcon#read 3, iclass 15, count 0 2006.182.08:01:22.34#ibcon#about to read 4, iclass 15, count 0 2006.182.08:01:22.34#ibcon#read 4, iclass 15, count 0 2006.182.08:01:22.34#ibcon#about to read 5, iclass 15, count 0 2006.182.08:01:22.34#ibcon#read 5, iclass 15, count 0 2006.182.08:01:22.34#ibcon#about to read 6, iclass 15, count 0 2006.182.08:01:22.34#ibcon#read 6, iclass 15, count 0 2006.182.08:01:22.34#ibcon#end of sib2, iclass 15, count 0 2006.182.08:01:22.34#ibcon#*after write, iclass 15, count 0 2006.182.08:01:22.34#ibcon#*before return 0, iclass 15, count 0 2006.182.08:01:22.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:22.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:01:22.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:01:22.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:01:22.34$vc4f8/vb=6,4 2006.182.08:01:22.34#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.08:01:22.34#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.08:01:22.34#ibcon#ireg 11 cls_cnt 2 2006.182.08:01:22.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:22.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:22.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:22.40#ibcon#enter wrdev, iclass 17, count 2 2006.182.08:01:22.40#ibcon#first serial, iclass 17, count 2 2006.182.08:01:22.40#ibcon#enter sib2, iclass 17, count 2 2006.182.08:01:22.40#ibcon#flushed, iclass 17, count 2 2006.182.08:01:22.40#ibcon#about to write, iclass 17, count 2 2006.182.08:01:22.40#ibcon#wrote, iclass 17, count 2 2006.182.08:01:22.40#ibcon#about to read 3, iclass 17, count 2 2006.182.08:01:22.42#ibcon#read 3, iclass 17, count 2 2006.182.08:01:22.42#ibcon#about to read 4, iclass 17, count 2 2006.182.08:01:22.42#ibcon#read 4, iclass 17, count 2 2006.182.08:01:22.42#ibcon#about to read 5, iclass 17, count 2 2006.182.08:01:22.42#ibcon#read 5, iclass 17, count 2 2006.182.08:01:22.42#ibcon#about to read 6, iclass 17, count 2 2006.182.08:01:22.42#ibcon#read 6, iclass 17, count 2 2006.182.08:01:22.42#ibcon#end of sib2, iclass 17, count 2 2006.182.08:01:22.42#ibcon#*mode == 0, iclass 17, count 2 2006.182.08:01:22.42#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.08:01:22.42#ibcon#[27=AT06-04\r\n] 2006.182.08:01:22.42#ibcon#*before write, iclass 17, count 2 2006.182.08:01:22.42#ibcon#enter sib2, iclass 17, count 2 2006.182.08:01:22.42#ibcon#flushed, iclass 17, count 2 2006.182.08:01:22.42#ibcon#about to write, iclass 17, count 2 2006.182.08:01:22.42#ibcon#wrote, iclass 17, count 2 2006.182.08:01:22.42#ibcon#about to read 3, iclass 17, count 2 2006.182.08:01:22.45#ibcon#read 3, iclass 17, count 2 2006.182.08:01:22.45#ibcon#about to read 4, iclass 17, count 2 2006.182.08:01:22.45#ibcon#read 4, iclass 17, count 2 2006.182.08:01:22.45#ibcon#about to read 5, iclass 17, count 2 2006.182.08:01:22.45#ibcon#read 5, iclass 17, count 2 2006.182.08:01:22.45#ibcon#about to read 6, iclass 17, count 2 2006.182.08:01:22.45#ibcon#read 6, iclass 17, count 2 2006.182.08:01:22.45#ibcon#end of sib2, iclass 17, count 2 2006.182.08:01:22.45#ibcon#*after write, iclass 17, count 2 2006.182.08:01:22.45#ibcon#*before return 0, iclass 17, count 2 2006.182.08:01:22.45#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:22.45#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:01:22.45#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.08:01:22.45#ibcon#ireg 7 cls_cnt 0 2006.182.08:01:22.45#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:22.57#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:22.57#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:22.57#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:01:22.57#ibcon#first serial, iclass 17, count 0 2006.182.08:01:22.57#ibcon#enter sib2, iclass 17, count 0 2006.182.08:01:22.57#ibcon#flushed, iclass 17, count 0 2006.182.08:01:22.57#ibcon#about to write, iclass 17, count 0 2006.182.08:01:22.57#ibcon#wrote, iclass 17, count 0 2006.182.08:01:22.57#ibcon#about to read 3, iclass 17, count 0 2006.182.08:01:22.59#ibcon#read 3, iclass 17, count 0 2006.182.08:01:22.59#ibcon#about to read 4, iclass 17, count 0 2006.182.08:01:22.59#ibcon#read 4, iclass 17, count 0 2006.182.08:01:22.59#ibcon#about to read 5, iclass 17, count 0 2006.182.08:01:22.59#ibcon#read 5, iclass 17, count 0 2006.182.08:01:22.59#ibcon#about to read 6, iclass 17, count 0 2006.182.08:01:22.59#ibcon#read 6, iclass 17, count 0 2006.182.08:01:22.59#ibcon#end of sib2, iclass 17, count 0 2006.182.08:01:22.59#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:01:22.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:01:22.59#ibcon#[27=USB\r\n] 2006.182.08:01:22.59#ibcon#*before write, iclass 17, count 0 2006.182.08:01:22.59#ibcon#enter sib2, iclass 17, count 0 2006.182.08:01:22.59#ibcon#flushed, iclass 17, count 0 2006.182.08:01:22.59#ibcon#about to write, iclass 17, count 0 2006.182.08:01:22.59#ibcon#wrote, iclass 17, count 0 2006.182.08:01:22.59#ibcon#about to read 3, iclass 17, count 0 2006.182.08:01:22.62#ibcon#read 3, iclass 17, count 0 2006.182.08:01:22.62#ibcon#about to read 4, iclass 17, count 0 2006.182.08:01:22.62#ibcon#read 4, iclass 17, count 0 2006.182.08:01:22.62#ibcon#about to read 5, iclass 17, count 0 2006.182.08:01:22.62#ibcon#read 5, iclass 17, count 0 2006.182.08:01:22.62#ibcon#about to read 6, iclass 17, count 0 2006.182.08:01:22.62#ibcon#read 6, iclass 17, count 0 2006.182.08:01:22.62#ibcon#end of sib2, iclass 17, count 0 2006.182.08:01:22.62#ibcon#*after write, iclass 17, count 0 2006.182.08:01:22.62#ibcon#*before return 0, iclass 17, count 0 2006.182.08:01:22.62#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:22.62#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:01:22.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:01:22.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:01:22.62$vc4f8/vabw=wide 2006.182.08:01:22.62#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.08:01:22.62#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.08:01:22.62#ibcon#ireg 8 cls_cnt 0 2006.182.08:01:22.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:22.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:22.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:22.62#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:01:22.62#ibcon#first serial, iclass 19, count 0 2006.182.08:01:22.62#ibcon#enter sib2, iclass 19, count 0 2006.182.08:01:22.62#ibcon#flushed, iclass 19, count 0 2006.182.08:01:22.62#ibcon#about to write, iclass 19, count 0 2006.182.08:01:22.62#ibcon#wrote, iclass 19, count 0 2006.182.08:01:22.62#ibcon#about to read 3, iclass 19, count 0 2006.182.08:01:22.64#ibcon#read 3, iclass 19, count 0 2006.182.08:01:22.64#ibcon#about to read 4, iclass 19, count 0 2006.182.08:01:22.64#ibcon#read 4, iclass 19, count 0 2006.182.08:01:22.64#ibcon#about to read 5, iclass 19, count 0 2006.182.08:01:22.64#ibcon#read 5, iclass 19, count 0 2006.182.08:01:22.64#ibcon#about to read 6, iclass 19, count 0 2006.182.08:01:22.64#ibcon#read 6, iclass 19, count 0 2006.182.08:01:22.64#ibcon#end of sib2, iclass 19, count 0 2006.182.08:01:22.64#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:01:22.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:01:22.64#ibcon#[25=BW32\r\n] 2006.182.08:01:22.64#ibcon#*before write, iclass 19, count 0 2006.182.08:01:22.64#ibcon#enter sib2, iclass 19, count 0 2006.182.08:01:22.64#ibcon#flushed, iclass 19, count 0 2006.182.08:01:22.64#ibcon#about to write, iclass 19, count 0 2006.182.08:01:22.64#ibcon#wrote, iclass 19, count 0 2006.182.08:01:22.64#ibcon#about to read 3, iclass 19, count 0 2006.182.08:01:22.67#ibcon#read 3, iclass 19, count 0 2006.182.08:01:22.67#ibcon#about to read 4, iclass 19, count 0 2006.182.08:01:22.67#ibcon#read 4, iclass 19, count 0 2006.182.08:01:22.67#ibcon#about to read 5, iclass 19, count 0 2006.182.08:01:22.67#ibcon#read 5, iclass 19, count 0 2006.182.08:01:22.67#ibcon#about to read 6, iclass 19, count 0 2006.182.08:01:22.67#ibcon#read 6, iclass 19, count 0 2006.182.08:01:22.67#ibcon#end of sib2, iclass 19, count 0 2006.182.08:01:22.67#ibcon#*after write, iclass 19, count 0 2006.182.08:01:22.67#ibcon#*before return 0, iclass 19, count 0 2006.182.08:01:22.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:22.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:01:22.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:01:22.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:01:22.67$vc4f8/vbbw=wide 2006.182.08:01:22.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.08:01:22.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.08:01:22.67#ibcon#ireg 8 cls_cnt 0 2006.182.08:01:22.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:01:22.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:01:22.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:01:22.75#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:01:22.75#ibcon#first serial, iclass 21, count 0 2006.182.08:01:22.75#ibcon#enter sib2, iclass 21, count 0 2006.182.08:01:22.75#ibcon#flushed, iclass 21, count 0 2006.182.08:01:22.75#ibcon#about to write, iclass 21, count 0 2006.182.08:01:22.75#ibcon#wrote, iclass 21, count 0 2006.182.08:01:22.75#ibcon#about to read 3, iclass 21, count 0 2006.182.08:01:22.77#ibcon#read 3, iclass 21, count 0 2006.182.08:01:22.77#ibcon#about to read 4, iclass 21, count 0 2006.182.08:01:22.77#ibcon#read 4, iclass 21, count 0 2006.182.08:01:22.77#ibcon#about to read 5, iclass 21, count 0 2006.182.08:01:22.77#ibcon#read 5, iclass 21, count 0 2006.182.08:01:22.77#ibcon#about to read 6, iclass 21, count 0 2006.182.08:01:22.77#ibcon#read 6, iclass 21, count 0 2006.182.08:01:22.77#ibcon#end of sib2, iclass 21, count 0 2006.182.08:01:22.77#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:01:22.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:01:22.77#ibcon#[27=BW32\r\n] 2006.182.08:01:22.77#ibcon#*before write, iclass 21, count 0 2006.182.08:01:22.77#ibcon#enter sib2, iclass 21, count 0 2006.182.08:01:22.77#ibcon#flushed, iclass 21, count 0 2006.182.08:01:22.77#ibcon#about to write, iclass 21, count 0 2006.182.08:01:22.77#ibcon#wrote, iclass 21, count 0 2006.182.08:01:22.77#ibcon#about to read 3, iclass 21, count 0 2006.182.08:01:22.79#ibcon#read 3, iclass 21, count 0 2006.182.08:01:22.79#ibcon#about to read 4, iclass 21, count 0 2006.182.08:01:22.79#ibcon#read 4, iclass 21, count 0 2006.182.08:01:22.79#ibcon#about to read 5, iclass 21, count 0 2006.182.08:01:22.79#ibcon#read 5, iclass 21, count 0 2006.182.08:01:22.79#ibcon#about to read 6, iclass 21, count 0 2006.182.08:01:22.79#ibcon#read 6, iclass 21, count 0 2006.182.08:01:22.79#ibcon#end of sib2, iclass 21, count 0 2006.182.08:01:22.79#ibcon#*after write, iclass 21, count 0 2006.182.08:01:22.79#ibcon#*before return 0, iclass 21, count 0 2006.182.08:01:22.79#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:01:22.79#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:01:22.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:01:22.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:01:22.79$4f8m12a/ifd4f 2006.182.08:01:22.79$ifd4f/lo= 2006.182.08:01:22.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:01:22.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:01:22.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:01:22.79$ifd4f/patch= 2006.182.08:01:22.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:01:22.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:01:22.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:01:22.80$4f8m12a/"form=m,16.000,1:2 2006.182.08:01:22.80$4f8m12a/"tpicd 2006.182.08:01:22.80$4f8m12a/echo=off 2006.182.08:01:22.80$4f8m12a/xlog=off 2006.182.08:01:22.80:!2006.182.08:02:30 2006.182.08:02:03.14#trakl#Source acquired 2006.182.08:02:05.14#flagr#flagr/antenna,acquired 2006.182.08:02:30.01:preob 2006.182.08:02:31.13/onsource/TRACKING 2006.182.08:02:31.13:!2006.182.08:02:40 2006.182.08:02:40.00:data_valid=on 2006.182.08:02:40.00:midob 2006.182.08:02:40.13/onsource/TRACKING 2006.182.08:02:40.13/wx/27.84,1002.9,81 2006.182.08:02:40.33/cable/+6.4653E-03 2006.182.08:02:41.42/va/01,08,usb,yes,29,31 2006.182.08:02:41.42/va/02,07,usb,yes,29,31 2006.182.08:02:41.42/va/03,06,usb,yes,31,31 2006.182.08:02:41.42/va/04,07,usb,yes,30,32 2006.182.08:02:41.42/va/05,07,usb,yes,31,33 2006.182.08:02:41.42/va/06,06,usb,yes,30,30 2006.182.08:02:41.42/va/07,06,usb,yes,31,30 2006.182.08:02:41.42/va/08,07,usb,yes,29,29 2006.182.08:02:41.65/valo/01,532.99,yes,locked 2006.182.08:02:41.65/valo/02,572.99,yes,locked 2006.182.08:02:41.65/valo/03,672.99,yes,locked 2006.182.08:02:41.65/valo/04,832.99,yes,locked 2006.182.08:02:41.65/valo/05,652.99,yes,locked 2006.182.08:02:41.65/valo/06,772.99,yes,locked 2006.182.08:02:41.65/valo/07,832.99,yes,locked 2006.182.08:02:41.65/valo/08,852.99,yes,locked 2006.182.08:02:42.74/vb/01,04,usb,yes,29,28 2006.182.08:02:42.74/vb/02,04,usb,yes,31,33 2006.182.08:02:42.74/vb/03,04,usb,yes,28,31 2006.182.08:02:42.74/vb/04,04,usb,yes,28,28 2006.182.08:02:42.74/vb/05,04,usb,yes,27,31 2006.182.08:02:42.74/vb/06,04,usb,yes,28,31 2006.182.08:02:42.74/vb/07,04,usb,yes,30,30 2006.182.08:02:42.74/vb/08,04,usb,yes,28,31 2006.182.08:02:42.97/vblo/01,632.99,yes,locked 2006.182.08:02:42.97/vblo/02,640.99,yes,locked 2006.182.08:02:42.97/vblo/03,656.99,yes,locked 2006.182.08:02:42.97/vblo/04,712.99,yes,locked 2006.182.08:02:42.97/vblo/05,744.99,yes,locked 2006.182.08:02:42.97/vblo/06,752.99,yes,locked 2006.182.08:02:42.97/vblo/07,734.99,yes,locked 2006.182.08:02:42.97/vblo/08,744.99,yes,locked 2006.182.08:02:43.12/vabw/8 2006.182.08:02:43.27/vbbw/8 2006.182.08:02:43.36/xfe/off,on,14.7 2006.182.08:02:43.73/ifatt/23,28,28,28 2006.182.08:02:44.07/fmout-gps/S +3.40E-07 2006.182.08:02:44.15:!2006.182.08:03:40 2006.182.08:03:40.00:data_valid=off 2006.182.08:03:40.01:postob 2006.182.08:03:40.17/cable/+6.4656E-03 2006.182.08:03:40.18/wx/27.86,1002.9,81 2006.182.08:03:41.07/fmout-gps/S +3.40E-07 2006.182.08:03:41.08:scan_name=182-0804,k06182,60 2006.182.08:03:41.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.182.08:03:42.13#flagr#flagr/antenna,new-source 2006.182.08:03:42.14:checkk5 2006.182.08:03:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:03:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:03:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:03:43.62/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:03:43.99/chk_obsdata//k5ts1/T1820802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:03:44.36/chk_obsdata//k5ts2/T1820802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:03:44.73/chk_obsdata//k5ts3/T1820802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:03:45.11/chk_obsdata//k5ts4/T1820802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:03:45.80/k5log//k5ts1_log_newline 2006.182.08:03:46.49/k5log//k5ts2_log_newline 2006.182.08:03:47.19/k5log//k5ts3_log_newline 2006.182.08:03:47.87/k5log//k5ts4_log_newline 2006.182.08:03:47.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:03:47.89:4f8m12a=2 2006.182.08:03:47.89$4f8m12a/echo=on 2006.182.08:03:47.89$4f8m12a/pcalon 2006.182.08:03:47.89$pcalon/"no phase cal control is implemented here 2006.182.08:03:47.89$4f8m12a/"tpicd=stop 2006.182.08:03:47.89$4f8m12a/vc4f8 2006.182.08:03:47.89$vc4f8/valo=1,532.99 2006.182.08:03:47.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.08:03:47.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.08:03:47.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:47.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:47.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:47.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:47.90#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:03:47.90#ibcon#first serial, iclass 12, count 0 2006.182.08:03:47.90#ibcon#enter sib2, iclass 12, count 0 2006.182.08:03:47.90#ibcon#flushed, iclass 12, count 0 2006.182.08:03:47.90#ibcon#about to write, iclass 12, count 0 2006.182.08:03:47.90#ibcon#wrote, iclass 12, count 0 2006.182.08:03:47.90#ibcon#about to read 3, iclass 12, count 0 2006.182.08:03:47.94#ibcon#read 3, iclass 12, count 0 2006.182.08:03:47.94#ibcon#about to read 4, iclass 12, count 0 2006.182.08:03:47.94#ibcon#read 4, iclass 12, count 0 2006.182.08:03:47.94#ibcon#about to read 5, iclass 12, count 0 2006.182.08:03:47.94#ibcon#read 5, iclass 12, count 0 2006.182.08:03:47.94#ibcon#about to read 6, iclass 12, count 0 2006.182.08:03:47.94#ibcon#read 6, iclass 12, count 0 2006.182.08:03:47.94#ibcon#end of sib2, iclass 12, count 0 2006.182.08:03:47.94#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:03:47.94#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:03:47.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:03:47.94#ibcon#*before write, iclass 12, count 0 2006.182.08:03:47.94#ibcon#enter sib2, iclass 12, count 0 2006.182.08:03:47.94#ibcon#flushed, iclass 12, count 0 2006.182.08:03:47.94#ibcon#about to write, iclass 12, count 0 2006.182.08:03:47.94#ibcon#wrote, iclass 12, count 0 2006.182.08:03:47.94#ibcon#about to read 3, iclass 12, count 0 2006.182.08:03:47.98#ibcon#read 3, iclass 12, count 0 2006.182.08:03:47.98#ibcon#about to read 4, iclass 12, count 0 2006.182.08:03:47.98#ibcon#read 4, iclass 12, count 0 2006.182.08:03:47.98#ibcon#about to read 5, iclass 12, count 0 2006.182.08:03:47.98#ibcon#read 5, iclass 12, count 0 2006.182.08:03:47.98#ibcon#about to read 6, iclass 12, count 0 2006.182.08:03:47.98#ibcon#read 6, iclass 12, count 0 2006.182.08:03:47.98#ibcon#end of sib2, iclass 12, count 0 2006.182.08:03:47.98#ibcon#*after write, iclass 12, count 0 2006.182.08:03:47.98#ibcon#*before return 0, iclass 12, count 0 2006.182.08:03:47.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:47.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:47.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:03:47.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:03:47.98$vc4f8/va=1,8 2006.182.08:03:47.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.08:03:47.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.08:03:47.98#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:47.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:47.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:47.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:47.98#ibcon#enter wrdev, iclass 14, count 2 2006.182.08:03:47.98#ibcon#first serial, iclass 14, count 2 2006.182.08:03:47.98#ibcon#enter sib2, iclass 14, count 2 2006.182.08:03:47.98#ibcon#flushed, iclass 14, count 2 2006.182.08:03:47.98#ibcon#about to write, iclass 14, count 2 2006.182.08:03:47.98#ibcon#wrote, iclass 14, count 2 2006.182.08:03:47.98#ibcon#about to read 3, iclass 14, count 2 2006.182.08:03:48.00#ibcon#read 3, iclass 14, count 2 2006.182.08:03:48.00#ibcon#about to read 4, iclass 14, count 2 2006.182.08:03:48.00#ibcon#read 4, iclass 14, count 2 2006.182.08:03:48.00#ibcon#about to read 5, iclass 14, count 2 2006.182.08:03:48.00#ibcon#read 5, iclass 14, count 2 2006.182.08:03:48.00#ibcon#about to read 6, iclass 14, count 2 2006.182.08:03:48.00#ibcon#read 6, iclass 14, count 2 2006.182.08:03:48.00#ibcon#end of sib2, iclass 14, count 2 2006.182.08:03:48.00#ibcon#*mode == 0, iclass 14, count 2 2006.182.08:03:48.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.08:03:48.00#ibcon#[25=AT01-08\r\n] 2006.182.08:03:48.00#ibcon#*before write, iclass 14, count 2 2006.182.08:03:48.00#ibcon#enter sib2, iclass 14, count 2 2006.182.08:03:48.00#ibcon#flushed, iclass 14, count 2 2006.182.08:03:48.00#ibcon#about to write, iclass 14, count 2 2006.182.08:03:48.00#ibcon#wrote, iclass 14, count 2 2006.182.08:03:48.00#ibcon#about to read 3, iclass 14, count 2 2006.182.08:03:48.03#ibcon#read 3, iclass 14, count 2 2006.182.08:03:48.03#ibcon#about to read 4, iclass 14, count 2 2006.182.08:03:48.03#ibcon#read 4, iclass 14, count 2 2006.182.08:03:48.03#ibcon#about to read 5, iclass 14, count 2 2006.182.08:03:48.03#ibcon#read 5, iclass 14, count 2 2006.182.08:03:48.03#ibcon#about to read 6, iclass 14, count 2 2006.182.08:03:48.03#ibcon#read 6, iclass 14, count 2 2006.182.08:03:48.03#ibcon#end of sib2, iclass 14, count 2 2006.182.08:03:48.03#ibcon#*after write, iclass 14, count 2 2006.182.08:03:48.03#ibcon#*before return 0, iclass 14, count 2 2006.182.08:03:48.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:48.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:48.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.08:03:48.03#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:48.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:48.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:48.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:48.15#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:03:48.15#ibcon#first serial, iclass 14, count 0 2006.182.08:03:48.15#ibcon#enter sib2, iclass 14, count 0 2006.182.08:03:48.15#ibcon#flushed, iclass 14, count 0 2006.182.08:03:48.15#ibcon#about to write, iclass 14, count 0 2006.182.08:03:48.15#ibcon#wrote, iclass 14, count 0 2006.182.08:03:48.15#ibcon#about to read 3, iclass 14, count 0 2006.182.08:03:48.17#ibcon#read 3, iclass 14, count 0 2006.182.08:03:48.17#ibcon#about to read 4, iclass 14, count 0 2006.182.08:03:48.17#ibcon#read 4, iclass 14, count 0 2006.182.08:03:48.17#ibcon#about to read 5, iclass 14, count 0 2006.182.08:03:48.17#ibcon#read 5, iclass 14, count 0 2006.182.08:03:48.17#ibcon#about to read 6, iclass 14, count 0 2006.182.08:03:48.17#ibcon#read 6, iclass 14, count 0 2006.182.08:03:48.17#ibcon#end of sib2, iclass 14, count 0 2006.182.08:03:48.17#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:03:48.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:03:48.17#ibcon#[25=USB\r\n] 2006.182.08:03:48.17#ibcon#*before write, iclass 14, count 0 2006.182.08:03:48.17#ibcon#enter sib2, iclass 14, count 0 2006.182.08:03:48.17#ibcon#flushed, iclass 14, count 0 2006.182.08:03:48.17#ibcon#about to write, iclass 14, count 0 2006.182.08:03:48.17#ibcon#wrote, iclass 14, count 0 2006.182.08:03:48.17#ibcon#about to read 3, iclass 14, count 0 2006.182.08:03:48.21#ibcon#read 3, iclass 14, count 0 2006.182.08:03:48.21#ibcon#about to read 4, iclass 14, count 0 2006.182.08:03:48.21#ibcon#read 4, iclass 14, count 0 2006.182.08:03:48.21#ibcon#about to read 5, iclass 14, count 0 2006.182.08:03:48.21#ibcon#read 5, iclass 14, count 0 2006.182.08:03:48.21#ibcon#about to read 6, iclass 14, count 0 2006.182.08:03:48.21#ibcon#read 6, iclass 14, count 0 2006.182.08:03:48.21#ibcon#end of sib2, iclass 14, count 0 2006.182.08:03:48.21#ibcon#*after write, iclass 14, count 0 2006.182.08:03:48.21#ibcon#*before return 0, iclass 14, count 0 2006.182.08:03:48.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:48.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:48.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:03:48.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:03:48.21$vc4f8/valo=2,572.99 2006.182.08:03:48.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.08:03:48.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.08:03:48.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:48.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:48.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:48.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:48.21#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:03:48.21#ibcon#first serial, iclass 16, count 0 2006.182.08:03:48.21#ibcon#enter sib2, iclass 16, count 0 2006.182.08:03:48.21#ibcon#flushed, iclass 16, count 0 2006.182.08:03:48.21#ibcon#about to write, iclass 16, count 0 2006.182.08:03:48.21#ibcon#wrote, iclass 16, count 0 2006.182.08:03:48.21#ibcon#about to read 3, iclass 16, count 0 2006.182.08:03:48.22#ibcon#read 3, iclass 16, count 0 2006.182.08:03:48.22#ibcon#about to read 4, iclass 16, count 0 2006.182.08:03:48.22#ibcon#read 4, iclass 16, count 0 2006.182.08:03:48.22#ibcon#about to read 5, iclass 16, count 0 2006.182.08:03:48.22#ibcon#read 5, iclass 16, count 0 2006.182.08:03:48.22#ibcon#about to read 6, iclass 16, count 0 2006.182.08:03:48.22#ibcon#read 6, iclass 16, count 0 2006.182.08:03:48.22#ibcon#end of sib2, iclass 16, count 0 2006.182.08:03:48.22#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:03:48.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:03:48.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:03:48.22#ibcon#*before write, iclass 16, count 0 2006.182.08:03:48.22#ibcon#enter sib2, iclass 16, count 0 2006.182.08:03:48.22#ibcon#flushed, iclass 16, count 0 2006.182.08:03:48.22#ibcon#about to write, iclass 16, count 0 2006.182.08:03:48.22#ibcon#wrote, iclass 16, count 0 2006.182.08:03:48.22#ibcon#about to read 3, iclass 16, count 0 2006.182.08:03:48.26#ibcon#read 3, iclass 16, count 0 2006.182.08:03:48.26#ibcon#about to read 4, iclass 16, count 0 2006.182.08:03:48.26#ibcon#read 4, iclass 16, count 0 2006.182.08:03:48.26#ibcon#about to read 5, iclass 16, count 0 2006.182.08:03:48.26#ibcon#read 5, iclass 16, count 0 2006.182.08:03:48.26#ibcon#about to read 6, iclass 16, count 0 2006.182.08:03:48.26#ibcon#read 6, iclass 16, count 0 2006.182.08:03:48.26#ibcon#end of sib2, iclass 16, count 0 2006.182.08:03:48.26#ibcon#*after write, iclass 16, count 0 2006.182.08:03:48.26#ibcon#*before return 0, iclass 16, count 0 2006.182.08:03:48.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:48.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:48.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:03:48.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:03:48.26$vc4f8/va=2,7 2006.182.08:03:48.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.08:03:48.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.08:03:48.26#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:48.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:48.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:48.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:48.33#ibcon#enter wrdev, iclass 18, count 2 2006.182.08:03:48.33#ibcon#first serial, iclass 18, count 2 2006.182.08:03:48.33#ibcon#enter sib2, iclass 18, count 2 2006.182.08:03:48.33#ibcon#flushed, iclass 18, count 2 2006.182.08:03:48.33#ibcon#about to write, iclass 18, count 2 2006.182.08:03:48.33#ibcon#wrote, iclass 18, count 2 2006.182.08:03:48.33#ibcon#about to read 3, iclass 18, count 2 2006.182.08:03:48.35#ibcon#read 3, iclass 18, count 2 2006.182.08:03:48.35#ibcon#about to read 4, iclass 18, count 2 2006.182.08:03:48.35#ibcon#read 4, iclass 18, count 2 2006.182.08:03:48.35#ibcon#about to read 5, iclass 18, count 2 2006.182.08:03:48.35#ibcon#read 5, iclass 18, count 2 2006.182.08:03:48.35#ibcon#about to read 6, iclass 18, count 2 2006.182.08:03:48.35#ibcon#read 6, iclass 18, count 2 2006.182.08:03:48.35#ibcon#end of sib2, iclass 18, count 2 2006.182.08:03:48.35#ibcon#*mode == 0, iclass 18, count 2 2006.182.08:03:48.35#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.08:03:48.35#ibcon#[25=AT02-07\r\n] 2006.182.08:03:48.35#ibcon#*before write, iclass 18, count 2 2006.182.08:03:48.35#ibcon#enter sib2, iclass 18, count 2 2006.182.08:03:48.35#ibcon#flushed, iclass 18, count 2 2006.182.08:03:48.35#ibcon#about to write, iclass 18, count 2 2006.182.08:03:48.35#ibcon#wrote, iclass 18, count 2 2006.182.08:03:48.35#ibcon#about to read 3, iclass 18, count 2 2006.182.08:03:48.38#ibcon#read 3, iclass 18, count 2 2006.182.08:03:48.38#ibcon#about to read 4, iclass 18, count 2 2006.182.08:03:48.38#ibcon#read 4, iclass 18, count 2 2006.182.08:03:48.38#ibcon#about to read 5, iclass 18, count 2 2006.182.08:03:48.38#ibcon#read 5, iclass 18, count 2 2006.182.08:03:48.38#ibcon#about to read 6, iclass 18, count 2 2006.182.08:03:48.38#ibcon#read 6, iclass 18, count 2 2006.182.08:03:48.38#ibcon#end of sib2, iclass 18, count 2 2006.182.08:03:48.38#ibcon#*after write, iclass 18, count 2 2006.182.08:03:48.38#ibcon#*before return 0, iclass 18, count 2 2006.182.08:03:48.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:48.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:48.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.08:03:48.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:48.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:48.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:48.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:48.50#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:03:48.50#ibcon#first serial, iclass 18, count 0 2006.182.08:03:48.50#ibcon#enter sib2, iclass 18, count 0 2006.182.08:03:48.50#ibcon#flushed, iclass 18, count 0 2006.182.08:03:48.50#ibcon#about to write, iclass 18, count 0 2006.182.08:03:48.50#ibcon#wrote, iclass 18, count 0 2006.182.08:03:48.50#ibcon#about to read 3, iclass 18, count 0 2006.182.08:03:48.53#ibcon#read 3, iclass 18, count 0 2006.182.08:03:48.53#ibcon#about to read 4, iclass 18, count 0 2006.182.08:03:48.53#ibcon#read 4, iclass 18, count 0 2006.182.08:03:48.53#ibcon#about to read 5, iclass 18, count 0 2006.182.08:03:48.53#ibcon#read 5, iclass 18, count 0 2006.182.08:03:48.53#ibcon#about to read 6, iclass 18, count 0 2006.182.08:03:48.53#ibcon#read 6, iclass 18, count 0 2006.182.08:03:48.53#ibcon#end of sib2, iclass 18, count 0 2006.182.08:03:48.53#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:03:48.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:03:48.53#ibcon#[25=USB\r\n] 2006.182.08:03:48.53#ibcon#*before write, iclass 18, count 0 2006.182.08:03:48.53#ibcon#enter sib2, iclass 18, count 0 2006.182.08:03:48.53#ibcon#flushed, iclass 18, count 0 2006.182.08:03:48.53#ibcon#about to write, iclass 18, count 0 2006.182.08:03:48.53#ibcon#wrote, iclass 18, count 0 2006.182.08:03:48.53#ibcon#about to read 3, iclass 18, count 0 2006.182.08:03:48.55#ibcon#read 3, iclass 18, count 0 2006.182.08:03:48.55#ibcon#about to read 4, iclass 18, count 0 2006.182.08:03:48.55#ibcon#read 4, iclass 18, count 0 2006.182.08:03:48.55#ibcon#about to read 5, iclass 18, count 0 2006.182.08:03:48.55#ibcon#read 5, iclass 18, count 0 2006.182.08:03:48.55#ibcon#about to read 6, iclass 18, count 0 2006.182.08:03:48.55#ibcon#read 6, iclass 18, count 0 2006.182.08:03:48.55#ibcon#end of sib2, iclass 18, count 0 2006.182.08:03:48.55#ibcon#*after write, iclass 18, count 0 2006.182.08:03:48.55#ibcon#*before return 0, iclass 18, count 0 2006.182.08:03:48.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:48.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:48.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:03:48.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:03:48.55$vc4f8/valo=3,672.99 2006.182.08:03:48.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.08:03:48.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.08:03:48.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:48.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:48.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:48.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:48.55#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:03:48.55#ibcon#first serial, iclass 20, count 0 2006.182.08:03:48.55#ibcon#enter sib2, iclass 20, count 0 2006.182.08:03:48.55#ibcon#flushed, iclass 20, count 0 2006.182.08:03:48.55#ibcon#about to write, iclass 20, count 0 2006.182.08:03:48.55#ibcon#wrote, iclass 20, count 0 2006.182.08:03:48.55#ibcon#about to read 3, iclass 20, count 0 2006.182.08:03:48.58#ibcon#read 3, iclass 20, count 0 2006.182.08:03:48.58#ibcon#about to read 4, iclass 20, count 0 2006.182.08:03:48.58#ibcon#read 4, iclass 20, count 0 2006.182.08:03:48.58#ibcon#about to read 5, iclass 20, count 0 2006.182.08:03:48.58#ibcon#read 5, iclass 20, count 0 2006.182.08:03:48.58#ibcon#about to read 6, iclass 20, count 0 2006.182.08:03:48.58#ibcon#read 6, iclass 20, count 0 2006.182.08:03:48.58#ibcon#end of sib2, iclass 20, count 0 2006.182.08:03:48.58#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:03:48.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:03:48.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:03:48.58#ibcon#*before write, iclass 20, count 0 2006.182.08:03:48.58#ibcon#enter sib2, iclass 20, count 0 2006.182.08:03:48.58#ibcon#flushed, iclass 20, count 0 2006.182.08:03:48.58#ibcon#about to write, iclass 20, count 0 2006.182.08:03:48.58#ibcon#wrote, iclass 20, count 0 2006.182.08:03:48.58#ibcon#about to read 3, iclass 20, count 0 2006.182.08:03:48.61#ibcon#read 3, iclass 20, count 0 2006.182.08:03:48.61#ibcon#about to read 4, iclass 20, count 0 2006.182.08:03:48.61#ibcon#read 4, iclass 20, count 0 2006.182.08:03:48.61#ibcon#about to read 5, iclass 20, count 0 2006.182.08:03:48.61#ibcon#read 5, iclass 20, count 0 2006.182.08:03:48.61#ibcon#about to read 6, iclass 20, count 0 2006.182.08:03:48.61#ibcon#read 6, iclass 20, count 0 2006.182.08:03:48.61#ibcon#end of sib2, iclass 20, count 0 2006.182.08:03:48.61#ibcon#*after write, iclass 20, count 0 2006.182.08:03:48.61#ibcon#*before return 0, iclass 20, count 0 2006.182.08:03:48.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:48.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:48.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:03:48.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:03:48.62$vc4f8/va=3,6 2006.182.08:03:48.62#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.08:03:48.62#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.08:03:48.62#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:48.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:48.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:48.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:48.66#ibcon#enter wrdev, iclass 22, count 2 2006.182.08:03:48.66#ibcon#first serial, iclass 22, count 2 2006.182.08:03:48.66#ibcon#enter sib2, iclass 22, count 2 2006.182.08:03:48.66#ibcon#flushed, iclass 22, count 2 2006.182.08:03:48.66#ibcon#about to write, iclass 22, count 2 2006.182.08:03:48.66#ibcon#wrote, iclass 22, count 2 2006.182.08:03:48.66#ibcon#about to read 3, iclass 22, count 2 2006.182.08:03:48.69#ibcon#read 3, iclass 22, count 2 2006.182.08:03:48.69#ibcon#about to read 4, iclass 22, count 2 2006.182.08:03:48.69#ibcon#read 4, iclass 22, count 2 2006.182.08:03:48.69#ibcon#about to read 5, iclass 22, count 2 2006.182.08:03:48.69#ibcon#read 5, iclass 22, count 2 2006.182.08:03:48.69#ibcon#about to read 6, iclass 22, count 2 2006.182.08:03:48.69#ibcon#read 6, iclass 22, count 2 2006.182.08:03:48.69#ibcon#end of sib2, iclass 22, count 2 2006.182.08:03:48.69#ibcon#*mode == 0, iclass 22, count 2 2006.182.08:03:48.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.08:03:48.69#ibcon#[25=AT03-06\r\n] 2006.182.08:03:48.69#ibcon#*before write, iclass 22, count 2 2006.182.08:03:48.69#ibcon#enter sib2, iclass 22, count 2 2006.182.08:03:48.69#ibcon#flushed, iclass 22, count 2 2006.182.08:03:48.69#ibcon#about to write, iclass 22, count 2 2006.182.08:03:48.69#ibcon#wrote, iclass 22, count 2 2006.182.08:03:48.69#ibcon#about to read 3, iclass 22, count 2 2006.182.08:03:48.72#ibcon#read 3, iclass 22, count 2 2006.182.08:03:48.72#ibcon#about to read 4, iclass 22, count 2 2006.182.08:03:48.72#ibcon#read 4, iclass 22, count 2 2006.182.08:03:48.72#ibcon#about to read 5, iclass 22, count 2 2006.182.08:03:48.72#ibcon#read 5, iclass 22, count 2 2006.182.08:03:48.72#ibcon#about to read 6, iclass 22, count 2 2006.182.08:03:48.72#ibcon#read 6, iclass 22, count 2 2006.182.08:03:48.72#ibcon#end of sib2, iclass 22, count 2 2006.182.08:03:48.72#ibcon#*after write, iclass 22, count 2 2006.182.08:03:48.72#ibcon#*before return 0, iclass 22, count 2 2006.182.08:03:48.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:48.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:48.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.08:03:48.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:48.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:48.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:48.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:48.84#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:03:48.84#ibcon#first serial, iclass 22, count 0 2006.182.08:03:48.84#ibcon#enter sib2, iclass 22, count 0 2006.182.08:03:48.84#ibcon#flushed, iclass 22, count 0 2006.182.08:03:48.84#ibcon#about to write, iclass 22, count 0 2006.182.08:03:48.84#ibcon#wrote, iclass 22, count 0 2006.182.08:03:48.84#ibcon#about to read 3, iclass 22, count 0 2006.182.08:03:48.86#ibcon#read 3, iclass 22, count 0 2006.182.08:03:48.86#ibcon#about to read 4, iclass 22, count 0 2006.182.08:03:48.86#ibcon#read 4, iclass 22, count 0 2006.182.08:03:48.86#ibcon#about to read 5, iclass 22, count 0 2006.182.08:03:48.86#ibcon#read 5, iclass 22, count 0 2006.182.08:03:48.86#ibcon#about to read 6, iclass 22, count 0 2006.182.08:03:48.86#ibcon#read 6, iclass 22, count 0 2006.182.08:03:48.86#ibcon#end of sib2, iclass 22, count 0 2006.182.08:03:48.86#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:03:48.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:03:48.86#ibcon#[25=USB\r\n] 2006.182.08:03:48.86#ibcon#*before write, iclass 22, count 0 2006.182.08:03:48.86#ibcon#enter sib2, iclass 22, count 0 2006.182.08:03:48.86#ibcon#flushed, iclass 22, count 0 2006.182.08:03:48.86#ibcon#about to write, iclass 22, count 0 2006.182.08:03:48.86#ibcon#wrote, iclass 22, count 0 2006.182.08:03:48.86#ibcon#about to read 3, iclass 22, count 0 2006.182.08:03:48.89#ibcon#read 3, iclass 22, count 0 2006.182.08:03:48.89#ibcon#about to read 4, iclass 22, count 0 2006.182.08:03:48.89#ibcon#read 4, iclass 22, count 0 2006.182.08:03:48.89#ibcon#about to read 5, iclass 22, count 0 2006.182.08:03:48.89#ibcon#read 5, iclass 22, count 0 2006.182.08:03:48.89#ibcon#about to read 6, iclass 22, count 0 2006.182.08:03:48.89#ibcon#read 6, iclass 22, count 0 2006.182.08:03:48.89#ibcon#end of sib2, iclass 22, count 0 2006.182.08:03:48.89#ibcon#*after write, iclass 22, count 0 2006.182.08:03:48.89#ibcon#*before return 0, iclass 22, count 0 2006.182.08:03:48.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:48.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:48.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:03:48.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:03:48.89$vc4f8/valo=4,832.99 2006.182.08:03:48.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.08:03:48.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.08:03:48.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:48.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:48.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:48.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:48.89#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:03:48.89#ibcon#first serial, iclass 24, count 0 2006.182.08:03:48.89#ibcon#enter sib2, iclass 24, count 0 2006.182.08:03:48.89#ibcon#flushed, iclass 24, count 0 2006.182.08:03:48.89#ibcon#about to write, iclass 24, count 0 2006.182.08:03:48.89#ibcon#wrote, iclass 24, count 0 2006.182.08:03:48.89#ibcon#about to read 3, iclass 24, count 0 2006.182.08:03:48.91#ibcon#read 3, iclass 24, count 0 2006.182.08:03:48.91#ibcon#about to read 4, iclass 24, count 0 2006.182.08:03:48.91#ibcon#read 4, iclass 24, count 0 2006.182.08:03:48.91#ibcon#about to read 5, iclass 24, count 0 2006.182.08:03:48.91#ibcon#read 5, iclass 24, count 0 2006.182.08:03:48.91#ibcon#about to read 6, iclass 24, count 0 2006.182.08:03:48.91#ibcon#read 6, iclass 24, count 0 2006.182.08:03:48.91#ibcon#end of sib2, iclass 24, count 0 2006.182.08:03:48.91#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:03:48.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:03:48.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:03:48.91#ibcon#*before write, iclass 24, count 0 2006.182.08:03:48.91#ibcon#enter sib2, iclass 24, count 0 2006.182.08:03:48.91#ibcon#flushed, iclass 24, count 0 2006.182.08:03:48.91#ibcon#about to write, iclass 24, count 0 2006.182.08:03:48.91#ibcon#wrote, iclass 24, count 0 2006.182.08:03:48.91#ibcon#about to read 3, iclass 24, count 0 2006.182.08:03:48.95#ibcon#read 3, iclass 24, count 0 2006.182.08:03:48.95#ibcon#about to read 4, iclass 24, count 0 2006.182.08:03:48.95#ibcon#read 4, iclass 24, count 0 2006.182.08:03:48.95#ibcon#about to read 5, iclass 24, count 0 2006.182.08:03:48.95#ibcon#read 5, iclass 24, count 0 2006.182.08:03:48.95#ibcon#about to read 6, iclass 24, count 0 2006.182.08:03:48.95#ibcon#read 6, iclass 24, count 0 2006.182.08:03:48.95#ibcon#end of sib2, iclass 24, count 0 2006.182.08:03:48.95#ibcon#*after write, iclass 24, count 0 2006.182.08:03:48.95#ibcon#*before return 0, iclass 24, count 0 2006.182.08:03:48.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:48.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:48.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:03:48.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:03:48.95$vc4f8/va=4,7 2006.182.08:03:48.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.08:03:48.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.08:03:48.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:48.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:49.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:49.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:49.01#ibcon#enter wrdev, iclass 26, count 2 2006.182.08:03:49.01#ibcon#first serial, iclass 26, count 2 2006.182.08:03:49.01#ibcon#enter sib2, iclass 26, count 2 2006.182.08:03:49.01#ibcon#flushed, iclass 26, count 2 2006.182.08:03:49.01#ibcon#about to write, iclass 26, count 2 2006.182.08:03:49.01#ibcon#wrote, iclass 26, count 2 2006.182.08:03:49.01#ibcon#about to read 3, iclass 26, count 2 2006.182.08:03:49.03#ibcon#read 3, iclass 26, count 2 2006.182.08:03:49.03#ibcon#about to read 4, iclass 26, count 2 2006.182.08:03:49.03#ibcon#read 4, iclass 26, count 2 2006.182.08:03:49.03#ibcon#about to read 5, iclass 26, count 2 2006.182.08:03:49.03#ibcon#read 5, iclass 26, count 2 2006.182.08:03:49.03#ibcon#about to read 6, iclass 26, count 2 2006.182.08:03:49.03#ibcon#read 6, iclass 26, count 2 2006.182.08:03:49.03#ibcon#end of sib2, iclass 26, count 2 2006.182.08:03:49.03#ibcon#*mode == 0, iclass 26, count 2 2006.182.08:03:49.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.08:03:49.03#ibcon#[25=AT04-07\r\n] 2006.182.08:03:49.03#ibcon#*before write, iclass 26, count 2 2006.182.08:03:49.03#ibcon#enter sib2, iclass 26, count 2 2006.182.08:03:49.03#ibcon#flushed, iclass 26, count 2 2006.182.08:03:49.03#ibcon#about to write, iclass 26, count 2 2006.182.08:03:49.03#ibcon#wrote, iclass 26, count 2 2006.182.08:03:49.03#ibcon#about to read 3, iclass 26, count 2 2006.182.08:03:49.06#ibcon#read 3, iclass 26, count 2 2006.182.08:03:49.06#ibcon#about to read 4, iclass 26, count 2 2006.182.08:03:49.06#ibcon#read 4, iclass 26, count 2 2006.182.08:03:49.06#ibcon#about to read 5, iclass 26, count 2 2006.182.08:03:49.06#ibcon#read 5, iclass 26, count 2 2006.182.08:03:49.06#ibcon#about to read 6, iclass 26, count 2 2006.182.08:03:49.06#ibcon#read 6, iclass 26, count 2 2006.182.08:03:49.06#ibcon#end of sib2, iclass 26, count 2 2006.182.08:03:49.06#ibcon#*after write, iclass 26, count 2 2006.182.08:03:49.06#ibcon#*before return 0, iclass 26, count 2 2006.182.08:03:49.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:49.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:49.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.08:03:49.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:49.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:49.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:49.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:49.18#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:03:49.18#ibcon#first serial, iclass 26, count 0 2006.182.08:03:49.18#ibcon#enter sib2, iclass 26, count 0 2006.182.08:03:49.18#ibcon#flushed, iclass 26, count 0 2006.182.08:03:49.18#ibcon#about to write, iclass 26, count 0 2006.182.08:03:49.18#ibcon#wrote, iclass 26, count 0 2006.182.08:03:49.18#ibcon#about to read 3, iclass 26, count 0 2006.182.08:03:49.20#ibcon#read 3, iclass 26, count 0 2006.182.08:03:49.20#ibcon#about to read 4, iclass 26, count 0 2006.182.08:03:49.20#ibcon#read 4, iclass 26, count 0 2006.182.08:03:49.20#ibcon#about to read 5, iclass 26, count 0 2006.182.08:03:49.20#ibcon#read 5, iclass 26, count 0 2006.182.08:03:49.20#ibcon#about to read 6, iclass 26, count 0 2006.182.08:03:49.20#ibcon#read 6, iclass 26, count 0 2006.182.08:03:49.20#ibcon#end of sib2, iclass 26, count 0 2006.182.08:03:49.20#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:03:49.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:03:49.20#ibcon#[25=USB\r\n] 2006.182.08:03:49.20#ibcon#*before write, iclass 26, count 0 2006.182.08:03:49.20#ibcon#enter sib2, iclass 26, count 0 2006.182.08:03:49.20#ibcon#flushed, iclass 26, count 0 2006.182.08:03:49.20#ibcon#about to write, iclass 26, count 0 2006.182.08:03:49.20#ibcon#wrote, iclass 26, count 0 2006.182.08:03:49.20#ibcon#about to read 3, iclass 26, count 0 2006.182.08:03:49.23#ibcon#read 3, iclass 26, count 0 2006.182.08:03:49.23#ibcon#about to read 4, iclass 26, count 0 2006.182.08:03:49.23#ibcon#read 4, iclass 26, count 0 2006.182.08:03:49.23#ibcon#about to read 5, iclass 26, count 0 2006.182.08:03:49.23#ibcon#read 5, iclass 26, count 0 2006.182.08:03:49.23#ibcon#about to read 6, iclass 26, count 0 2006.182.08:03:49.23#ibcon#read 6, iclass 26, count 0 2006.182.08:03:49.23#ibcon#end of sib2, iclass 26, count 0 2006.182.08:03:49.23#ibcon#*after write, iclass 26, count 0 2006.182.08:03:49.23#ibcon#*before return 0, iclass 26, count 0 2006.182.08:03:49.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:49.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:49.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:03:49.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:03:49.23$vc4f8/valo=5,652.99 2006.182.08:03:49.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.08:03:49.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.08:03:49.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:49.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:49.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:49.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:49.23#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:03:49.23#ibcon#first serial, iclass 28, count 0 2006.182.08:03:49.23#ibcon#enter sib2, iclass 28, count 0 2006.182.08:03:49.23#ibcon#flushed, iclass 28, count 0 2006.182.08:03:49.23#ibcon#about to write, iclass 28, count 0 2006.182.08:03:49.23#ibcon#wrote, iclass 28, count 0 2006.182.08:03:49.23#ibcon#about to read 3, iclass 28, count 0 2006.182.08:03:49.25#ibcon#read 3, iclass 28, count 0 2006.182.08:03:49.25#ibcon#about to read 4, iclass 28, count 0 2006.182.08:03:49.25#ibcon#read 4, iclass 28, count 0 2006.182.08:03:49.25#ibcon#about to read 5, iclass 28, count 0 2006.182.08:03:49.25#ibcon#read 5, iclass 28, count 0 2006.182.08:03:49.25#ibcon#about to read 6, iclass 28, count 0 2006.182.08:03:49.25#ibcon#read 6, iclass 28, count 0 2006.182.08:03:49.25#ibcon#end of sib2, iclass 28, count 0 2006.182.08:03:49.25#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:03:49.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:03:49.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:03:49.25#ibcon#*before write, iclass 28, count 0 2006.182.08:03:49.25#ibcon#enter sib2, iclass 28, count 0 2006.182.08:03:49.25#ibcon#flushed, iclass 28, count 0 2006.182.08:03:49.25#ibcon#about to write, iclass 28, count 0 2006.182.08:03:49.25#ibcon#wrote, iclass 28, count 0 2006.182.08:03:49.25#ibcon#about to read 3, iclass 28, count 0 2006.182.08:03:49.29#ibcon#read 3, iclass 28, count 0 2006.182.08:03:49.29#ibcon#about to read 4, iclass 28, count 0 2006.182.08:03:49.29#ibcon#read 4, iclass 28, count 0 2006.182.08:03:49.29#ibcon#about to read 5, iclass 28, count 0 2006.182.08:03:49.29#ibcon#read 5, iclass 28, count 0 2006.182.08:03:49.29#ibcon#about to read 6, iclass 28, count 0 2006.182.08:03:49.29#ibcon#read 6, iclass 28, count 0 2006.182.08:03:49.29#ibcon#end of sib2, iclass 28, count 0 2006.182.08:03:49.29#ibcon#*after write, iclass 28, count 0 2006.182.08:03:49.29#ibcon#*before return 0, iclass 28, count 0 2006.182.08:03:49.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:49.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:49.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:03:49.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:03:49.29$vc4f8/va=5,7 2006.182.08:03:49.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.08:03:49.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.08:03:49.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:49.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:49.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:49.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:49.35#ibcon#enter wrdev, iclass 30, count 2 2006.182.08:03:49.35#ibcon#first serial, iclass 30, count 2 2006.182.08:03:49.35#ibcon#enter sib2, iclass 30, count 2 2006.182.08:03:49.35#ibcon#flushed, iclass 30, count 2 2006.182.08:03:49.35#ibcon#about to write, iclass 30, count 2 2006.182.08:03:49.35#ibcon#wrote, iclass 30, count 2 2006.182.08:03:49.35#ibcon#about to read 3, iclass 30, count 2 2006.182.08:03:49.37#ibcon#read 3, iclass 30, count 2 2006.182.08:03:49.37#ibcon#about to read 4, iclass 30, count 2 2006.182.08:03:49.37#ibcon#read 4, iclass 30, count 2 2006.182.08:03:49.37#ibcon#about to read 5, iclass 30, count 2 2006.182.08:03:49.37#ibcon#read 5, iclass 30, count 2 2006.182.08:03:49.37#ibcon#about to read 6, iclass 30, count 2 2006.182.08:03:49.37#ibcon#read 6, iclass 30, count 2 2006.182.08:03:49.37#ibcon#end of sib2, iclass 30, count 2 2006.182.08:03:49.37#ibcon#*mode == 0, iclass 30, count 2 2006.182.08:03:49.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.08:03:49.37#ibcon#[25=AT05-07\r\n] 2006.182.08:03:49.37#ibcon#*before write, iclass 30, count 2 2006.182.08:03:49.37#ibcon#enter sib2, iclass 30, count 2 2006.182.08:03:49.37#ibcon#flushed, iclass 30, count 2 2006.182.08:03:49.37#ibcon#about to write, iclass 30, count 2 2006.182.08:03:49.37#ibcon#wrote, iclass 30, count 2 2006.182.08:03:49.37#ibcon#about to read 3, iclass 30, count 2 2006.182.08:03:49.40#ibcon#read 3, iclass 30, count 2 2006.182.08:03:49.40#ibcon#about to read 4, iclass 30, count 2 2006.182.08:03:49.40#ibcon#read 4, iclass 30, count 2 2006.182.08:03:49.40#ibcon#about to read 5, iclass 30, count 2 2006.182.08:03:49.40#ibcon#read 5, iclass 30, count 2 2006.182.08:03:49.40#ibcon#about to read 6, iclass 30, count 2 2006.182.08:03:49.40#ibcon#read 6, iclass 30, count 2 2006.182.08:03:49.40#ibcon#end of sib2, iclass 30, count 2 2006.182.08:03:49.40#ibcon#*after write, iclass 30, count 2 2006.182.08:03:49.40#ibcon#*before return 0, iclass 30, count 2 2006.182.08:03:49.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:49.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:49.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.08:03:49.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:49.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:49.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:49.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:49.52#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:03:49.52#ibcon#first serial, iclass 30, count 0 2006.182.08:03:49.52#ibcon#enter sib2, iclass 30, count 0 2006.182.08:03:49.52#ibcon#flushed, iclass 30, count 0 2006.182.08:03:49.52#ibcon#about to write, iclass 30, count 0 2006.182.08:03:49.52#ibcon#wrote, iclass 30, count 0 2006.182.08:03:49.52#ibcon#about to read 3, iclass 30, count 0 2006.182.08:03:49.54#ibcon#read 3, iclass 30, count 0 2006.182.08:03:49.54#ibcon#about to read 4, iclass 30, count 0 2006.182.08:03:49.54#ibcon#read 4, iclass 30, count 0 2006.182.08:03:49.54#ibcon#about to read 5, iclass 30, count 0 2006.182.08:03:49.54#ibcon#read 5, iclass 30, count 0 2006.182.08:03:49.54#ibcon#about to read 6, iclass 30, count 0 2006.182.08:03:49.54#ibcon#read 6, iclass 30, count 0 2006.182.08:03:49.54#ibcon#end of sib2, iclass 30, count 0 2006.182.08:03:49.54#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:03:49.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:03:49.54#ibcon#[25=USB\r\n] 2006.182.08:03:49.54#ibcon#*before write, iclass 30, count 0 2006.182.08:03:49.54#ibcon#enter sib2, iclass 30, count 0 2006.182.08:03:49.54#ibcon#flushed, iclass 30, count 0 2006.182.08:03:49.54#ibcon#about to write, iclass 30, count 0 2006.182.08:03:49.54#ibcon#wrote, iclass 30, count 0 2006.182.08:03:49.54#ibcon#about to read 3, iclass 30, count 0 2006.182.08:03:49.57#ibcon#read 3, iclass 30, count 0 2006.182.08:03:49.57#ibcon#about to read 4, iclass 30, count 0 2006.182.08:03:49.57#ibcon#read 4, iclass 30, count 0 2006.182.08:03:49.57#ibcon#about to read 5, iclass 30, count 0 2006.182.08:03:49.57#ibcon#read 5, iclass 30, count 0 2006.182.08:03:49.57#ibcon#about to read 6, iclass 30, count 0 2006.182.08:03:49.57#ibcon#read 6, iclass 30, count 0 2006.182.08:03:49.57#ibcon#end of sib2, iclass 30, count 0 2006.182.08:03:49.57#ibcon#*after write, iclass 30, count 0 2006.182.08:03:49.57#ibcon#*before return 0, iclass 30, count 0 2006.182.08:03:49.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:49.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:49.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:03:49.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:03:49.57$vc4f8/valo=6,772.99 2006.182.08:03:49.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.08:03:49.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.08:03:49.57#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:49.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:49.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:49.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:49.57#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:03:49.57#ibcon#first serial, iclass 32, count 0 2006.182.08:03:49.57#ibcon#enter sib2, iclass 32, count 0 2006.182.08:03:49.57#ibcon#flushed, iclass 32, count 0 2006.182.08:03:49.57#ibcon#about to write, iclass 32, count 0 2006.182.08:03:49.57#ibcon#wrote, iclass 32, count 0 2006.182.08:03:49.57#ibcon#about to read 3, iclass 32, count 0 2006.182.08:03:49.59#ibcon#read 3, iclass 32, count 0 2006.182.08:03:49.59#ibcon#about to read 4, iclass 32, count 0 2006.182.08:03:49.59#ibcon#read 4, iclass 32, count 0 2006.182.08:03:49.59#ibcon#about to read 5, iclass 32, count 0 2006.182.08:03:49.59#ibcon#read 5, iclass 32, count 0 2006.182.08:03:49.59#ibcon#about to read 6, iclass 32, count 0 2006.182.08:03:49.59#ibcon#read 6, iclass 32, count 0 2006.182.08:03:49.59#ibcon#end of sib2, iclass 32, count 0 2006.182.08:03:49.59#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:03:49.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:03:49.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:03:49.59#ibcon#*before write, iclass 32, count 0 2006.182.08:03:49.59#ibcon#enter sib2, iclass 32, count 0 2006.182.08:03:49.59#ibcon#flushed, iclass 32, count 0 2006.182.08:03:49.59#ibcon#about to write, iclass 32, count 0 2006.182.08:03:49.59#ibcon#wrote, iclass 32, count 0 2006.182.08:03:49.59#ibcon#about to read 3, iclass 32, count 0 2006.182.08:03:49.63#ibcon#read 3, iclass 32, count 0 2006.182.08:03:49.63#ibcon#about to read 4, iclass 32, count 0 2006.182.08:03:49.63#ibcon#read 4, iclass 32, count 0 2006.182.08:03:49.63#ibcon#about to read 5, iclass 32, count 0 2006.182.08:03:49.63#ibcon#read 5, iclass 32, count 0 2006.182.08:03:49.63#ibcon#about to read 6, iclass 32, count 0 2006.182.08:03:49.63#ibcon#read 6, iclass 32, count 0 2006.182.08:03:49.63#ibcon#end of sib2, iclass 32, count 0 2006.182.08:03:49.63#ibcon#*after write, iclass 32, count 0 2006.182.08:03:49.63#ibcon#*before return 0, iclass 32, count 0 2006.182.08:03:49.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:49.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:49.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:03:49.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:03:49.63$vc4f8/va=6,6 2006.182.08:03:49.63#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.08:03:49.63#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.08:03:49.63#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:49.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:03:49.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:03:49.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:03:49.69#ibcon#enter wrdev, iclass 34, count 2 2006.182.08:03:49.69#ibcon#first serial, iclass 34, count 2 2006.182.08:03:49.69#ibcon#enter sib2, iclass 34, count 2 2006.182.08:03:49.69#ibcon#flushed, iclass 34, count 2 2006.182.08:03:49.69#ibcon#about to write, iclass 34, count 2 2006.182.08:03:49.69#ibcon#wrote, iclass 34, count 2 2006.182.08:03:49.69#ibcon#about to read 3, iclass 34, count 2 2006.182.08:03:49.71#ibcon#read 3, iclass 34, count 2 2006.182.08:03:49.71#ibcon#about to read 4, iclass 34, count 2 2006.182.08:03:49.71#ibcon#read 4, iclass 34, count 2 2006.182.08:03:49.71#ibcon#about to read 5, iclass 34, count 2 2006.182.08:03:49.71#ibcon#read 5, iclass 34, count 2 2006.182.08:03:49.71#ibcon#about to read 6, iclass 34, count 2 2006.182.08:03:49.71#ibcon#read 6, iclass 34, count 2 2006.182.08:03:49.71#ibcon#end of sib2, iclass 34, count 2 2006.182.08:03:49.71#ibcon#*mode == 0, iclass 34, count 2 2006.182.08:03:49.71#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.08:03:49.71#ibcon#[25=AT06-06\r\n] 2006.182.08:03:49.71#ibcon#*before write, iclass 34, count 2 2006.182.08:03:49.71#ibcon#enter sib2, iclass 34, count 2 2006.182.08:03:49.71#ibcon#flushed, iclass 34, count 2 2006.182.08:03:49.71#ibcon#about to write, iclass 34, count 2 2006.182.08:03:49.71#ibcon#wrote, iclass 34, count 2 2006.182.08:03:49.71#ibcon#about to read 3, iclass 34, count 2 2006.182.08:03:49.74#ibcon#read 3, iclass 34, count 2 2006.182.08:03:49.74#ibcon#about to read 4, iclass 34, count 2 2006.182.08:03:49.74#ibcon#read 4, iclass 34, count 2 2006.182.08:03:49.74#ibcon#about to read 5, iclass 34, count 2 2006.182.08:03:49.74#ibcon#read 5, iclass 34, count 2 2006.182.08:03:49.74#ibcon#about to read 6, iclass 34, count 2 2006.182.08:03:49.74#ibcon#read 6, iclass 34, count 2 2006.182.08:03:49.74#ibcon#end of sib2, iclass 34, count 2 2006.182.08:03:49.74#ibcon#*after write, iclass 34, count 2 2006.182.08:03:49.74#ibcon#*before return 0, iclass 34, count 2 2006.182.08:03:49.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:03:49.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:03:49.74#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.08:03:49.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:49.74#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:03:49.86#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:03:49.86#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:03:49.86#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:03:49.86#ibcon#first serial, iclass 34, count 0 2006.182.08:03:49.86#ibcon#enter sib2, iclass 34, count 0 2006.182.08:03:49.86#ibcon#flushed, iclass 34, count 0 2006.182.08:03:49.86#ibcon#about to write, iclass 34, count 0 2006.182.08:03:49.86#ibcon#wrote, iclass 34, count 0 2006.182.08:03:49.86#ibcon#about to read 3, iclass 34, count 0 2006.182.08:03:49.88#ibcon#read 3, iclass 34, count 0 2006.182.08:03:49.88#ibcon#about to read 4, iclass 34, count 0 2006.182.08:03:49.88#ibcon#read 4, iclass 34, count 0 2006.182.08:03:49.88#ibcon#about to read 5, iclass 34, count 0 2006.182.08:03:49.88#ibcon#read 5, iclass 34, count 0 2006.182.08:03:49.88#ibcon#about to read 6, iclass 34, count 0 2006.182.08:03:49.88#ibcon#read 6, iclass 34, count 0 2006.182.08:03:49.88#ibcon#end of sib2, iclass 34, count 0 2006.182.08:03:49.88#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:03:49.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:03:49.88#ibcon#[25=USB\r\n] 2006.182.08:03:49.88#ibcon#*before write, iclass 34, count 0 2006.182.08:03:49.88#ibcon#enter sib2, iclass 34, count 0 2006.182.08:03:49.88#ibcon#flushed, iclass 34, count 0 2006.182.08:03:49.88#ibcon#about to write, iclass 34, count 0 2006.182.08:03:49.88#ibcon#wrote, iclass 34, count 0 2006.182.08:03:49.88#ibcon#about to read 3, iclass 34, count 0 2006.182.08:03:49.91#ibcon#read 3, iclass 34, count 0 2006.182.08:03:49.91#ibcon#about to read 4, iclass 34, count 0 2006.182.08:03:49.91#ibcon#read 4, iclass 34, count 0 2006.182.08:03:49.91#ibcon#about to read 5, iclass 34, count 0 2006.182.08:03:49.91#ibcon#read 5, iclass 34, count 0 2006.182.08:03:49.91#ibcon#about to read 6, iclass 34, count 0 2006.182.08:03:49.91#ibcon#read 6, iclass 34, count 0 2006.182.08:03:49.91#ibcon#end of sib2, iclass 34, count 0 2006.182.08:03:49.91#ibcon#*after write, iclass 34, count 0 2006.182.08:03:49.91#ibcon#*before return 0, iclass 34, count 0 2006.182.08:03:49.91#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:03:49.91#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:03:49.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:03:49.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:03:49.91$vc4f8/valo=7,832.99 2006.182.08:03:49.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.08:03:49.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.08:03:49.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:49.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:03:49.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:03:49.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:03:49.91#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:03:49.91#ibcon#first serial, iclass 36, count 0 2006.182.08:03:49.91#ibcon#enter sib2, iclass 36, count 0 2006.182.08:03:49.91#ibcon#flushed, iclass 36, count 0 2006.182.08:03:49.91#ibcon#about to write, iclass 36, count 0 2006.182.08:03:49.91#ibcon#wrote, iclass 36, count 0 2006.182.08:03:49.91#ibcon#about to read 3, iclass 36, count 0 2006.182.08:03:49.93#ibcon#read 3, iclass 36, count 0 2006.182.08:03:49.93#ibcon#about to read 4, iclass 36, count 0 2006.182.08:03:49.93#ibcon#read 4, iclass 36, count 0 2006.182.08:03:49.93#ibcon#about to read 5, iclass 36, count 0 2006.182.08:03:49.93#ibcon#read 5, iclass 36, count 0 2006.182.08:03:49.93#ibcon#about to read 6, iclass 36, count 0 2006.182.08:03:49.93#ibcon#read 6, iclass 36, count 0 2006.182.08:03:49.93#ibcon#end of sib2, iclass 36, count 0 2006.182.08:03:49.93#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:03:49.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:03:49.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:03:49.93#ibcon#*before write, iclass 36, count 0 2006.182.08:03:49.93#ibcon#enter sib2, iclass 36, count 0 2006.182.08:03:49.93#ibcon#flushed, iclass 36, count 0 2006.182.08:03:49.93#ibcon#about to write, iclass 36, count 0 2006.182.08:03:49.93#ibcon#wrote, iclass 36, count 0 2006.182.08:03:49.93#ibcon#about to read 3, iclass 36, count 0 2006.182.08:03:49.97#ibcon#read 3, iclass 36, count 0 2006.182.08:03:49.97#ibcon#about to read 4, iclass 36, count 0 2006.182.08:03:49.97#ibcon#read 4, iclass 36, count 0 2006.182.08:03:49.97#ibcon#about to read 5, iclass 36, count 0 2006.182.08:03:49.97#ibcon#read 5, iclass 36, count 0 2006.182.08:03:49.97#ibcon#about to read 6, iclass 36, count 0 2006.182.08:03:49.97#ibcon#read 6, iclass 36, count 0 2006.182.08:03:49.97#ibcon#end of sib2, iclass 36, count 0 2006.182.08:03:49.97#ibcon#*after write, iclass 36, count 0 2006.182.08:03:49.97#ibcon#*before return 0, iclass 36, count 0 2006.182.08:03:49.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:03:49.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:03:49.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:03:49.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:03:49.97$vc4f8/va=7,6 2006.182.08:03:49.97#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.08:03:49.97#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.08:03:49.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:49.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:03:50.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:03:50.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:03:50.03#ibcon#enter wrdev, iclass 38, count 2 2006.182.08:03:50.03#ibcon#first serial, iclass 38, count 2 2006.182.08:03:50.03#ibcon#enter sib2, iclass 38, count 2 2006.182.08:03:50.03#ibcon#flushed, iclass 38, count 2 2006.182.08:03:50.03#ibcon#about to write, iclass 38, count 2 2006.182.08:03:50.03#ibcon#wrote, iclass 38, count 2 2006.182.08:03:50.03#ibcon#about to read 3, iclass 38, count 2 2006.182.08:03:50.05#ibcon#read 3, iclass 38, count 2 2006.182.08:03:50.05#ibcon#about to read 4, iclass 38, count 2 2006.182.08:03:50.05#ibcon#read 4, iclass 38, count 2 2006.182.08:03:50.05#ibcon#about to read 5, iclass 38, count 2 2006.182.08:03:50.05#ibcon#read 5, iclass 38, count 2 2006.182.08:03:50.05#ibcon#about to read 6, iclass 38, count 2 2006.182.08:03:50.05#ibcon#read 6, iclass 38, count 2 2006.182.08:03:50.05#ibcon#end of sib2, iclass 38, count 2 2006.182.08:03:50.05#ibcon#*mode == 0, iclass 38, count 2 2006.182.08:03:50.05#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.08:03:50.05#ibcon#[25=AT07-06\r\n] 2006.182.08:03:50.05#ibcon#*before write, iclass 38, count 2 2006.182.08:03:50.05#ibcon#enter sib2, iclass 38, count 2 2006.182.08:03:50.05#ibcon#flushed, iclass 38, count 2 2006.182.08:03:50.05#ibcon#about to write, iclass 38, count 2 2006.182.08:03:50.05#ibcon#wrote, iclass 38, count 2 2006.182.08:03:50.05#ibcon#about to read 3, iclass 38, count 2 2006.182.08:03:50.08#ibcon#read 3, iclass 38, count 2 2006.182.08:03:50.08#ibcon#about to read 4, iclass 38, count 2 2006.182.08:03:50.08#ibcon#read 4, iclass 38, count 2 2006.182.08:03:50.08#ibcon#about to read 5, iclass 38, count 2 2006.182.08:03:50.08#ibcon#read 5, iclass 38, count 2 2006.182.08:03:50.08#ibcon#about to read 6, iclass 38, count 2 2006.182.08:03:50.08#ibcon#read 6, iclass 38, count 2 2006.182.08:03:50.08#ibcon#end of sib2, iclass 38, count 2 2006.182.08:03:50.08#ibcon#*after write, iclass 38, count 2 2006.182.08:03:50.08#ibcon#*before return 0, iclass 38, count 2 2006.182.08:03:50.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:03:50.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:03:50.08#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.08:03:50.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:50.08#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:03:50.20#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:03:50.20#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:03:50.20#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:03:50.20#ibcon#first serial, iclass 38, count 0 2006.182.08:03:50.20#ibcon#enter sib2, iclass 38, count 0 2006.182.08:03:50.20#ibcon#flushed, iclass 38, count 0 2006.182.08:03:50.20#ibcon#about to write, iclass 38, count 0 2006.182.08:03:50.20#ibcon#wrote, iclass 38, count 0 2006.182.08:03:50.20#ibcon#about to read 3, iclass 38, count 0 2006.182.08:03:50.22#ibcon#read 3, iclass 38, count 0 2006.182.08:03:50.22#ibcon#about to read 4, iclass 38, count 0 2006.182.08:03:50.22#ibcon#read 4, iclass 38, count 0 2006.182.08:03:50.22#ibcon#about to read 5, iclass 38, count 0 2006.182.08:03:50.22#ibcon#read 5, iclass 38, count 0 2006.182.08:03:50.22#ibcon#about to read 6, iclass 38, count 0 2006.182.08:03:50.22#ibcon#read 6, iclass 38, count 0 2006.182.08:03:50.22#ibcon#end of sib2, iclass 38, count 0 2006.182.08:03:50.22#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:03:50.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:03:50.22#ibcon#[25=USB\r\n] 2006.182.08:03:50.22#ibcon#*before write, iclass 38, count 0 2006.182.08:03:50.22#ibcon#enter sib2, iclass 38, count 0 2006.182.08:03:50.22#ibcon#flushed, iclass 38, count 0 2006.182.08:03:50.22#ibcon#about to write, iclass 38, count 0 2006.182.08:03:50.22#ibcon#wrote, iclass 38, count 0 2006.182.08:03:50.22#ibcon#about to read 3, iclass 38, count 0 2006.182.08:03:50.25#ibcon#read 3, iclass 38, count 0 2006.182.08:03:50.25#ibcon#about to read 4, iclass 38, count 0 2006.182.08:03:50.25#ibcon#read 4, iclass 38, count 0 2006.182.08:03:50.25#ibcon#about to read 5, iclass 38, count 0 2006.182.08:03:50.25#ibcon#read 5, iclass 38, count 0 2006.182.08:03:50.25#ibcon#about to read 6, iclass 38, count 0 2006.182.08:03:50.25#ibcon#read 6, iclass 38, count 0 2006.182.08:03:50.25#ibcon#end of sib2, iclass 38, count 0 2006.182.08:03:50.25#ibcon#*after write, iclass 38, count 0 2006.182.08:03:50.25#ibcon#*before return 0, iclass 38, count 0 2006.182.08:03:50.25#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:03:50.25#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:03:50.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:03:50.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:03:50.25$vc4f8/valo=8,852.99 2006.182.08:03:50.25#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.08:03:50.25#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.08:03:50.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:50.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:03:50.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:03:50.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:03:50.25#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:03:50.25#ibcon#first serial, iclass 40, count 0 2006.182.08:03:50.25#ibcon#enter sib2, iclass 40, count 0 2006.182.08:03:50.25#ibcon#flushed, iclass 40, count 0 2006.182.08:03:50.25#ibcon#about to write, iclass 40, count 0 2006.182.08:03:50.25#ibcon#wrote, iclass 40, count 0 2006.182.08:03:50.25#ibcon#about to read 3, iclass 40, count 0 2006.182.08:03:50.27#ibcon#read 3, iclass 40, count 0 2006.182.08:03:50.27#ibcon#about to read 4, iclass 40, count 0 2006.182.08:03:50.27#ibcon#read 4, iclass 40, count 0 2006.182.08:03:50.27#ibcon#about to read 5, iclass 40, count 0 2006.182.08:03:50.27#ibcon#read 5, iclass 40, count 0 2006.182.08:03:50.27#ibcon#about to read 6, iclass 40, count 0 2006.182.08:03:50.27#ibcon#read 6, iclass 40, count 0 2006.182.08:03:50.27#ibcon#end of sib2, iclass 40, count 0 2006.182.08:03:50.27#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:03:50.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:03:50.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:03:50.27#ibcon#*before write, iclass 40, count 0 2006.182.08:03:50.27#ibcon#enter sib2, iclass 40, count 0 2006.182.08:03:50.27#ibcon#flushed, iclass 40, count 0 2006.182.08:03:50.27#ibcon#about to write, iclass 40, count 0 2006.182.08:03:50.27#ibcon#wrote, iclass 40, count 0 2006.182.08:03:50.27#ibcon#about to read 3, iclass 40, count 0 2006.182.08:03:50.31#ibcon#read 3, iclass 40, count 0 2006.182.08:03:50.31#ibcon#about to read 4, iclass 40, count 0 2006.182.08:03:50.31#ibcon#read 4, iclass 40, count 0 2006.182.08:03:50.31#ibcon#about to read 5, iclass 40, count 0 2006.182.08:03:50.31#ibcon#read 5, iclass 40, count 0 2006.182.08:03:50.31#ibcon#about to read 6, iclass 40, count 0 2006.182.08:03:50.31#ibcon#read 6, iclass 40, count 0 2006.182.08:03:50.31#ibcon#end of sib2, iclass 40, count 0 2006.182.08:03:50.31#ibcon#*after write, iclass 40, count 0 2006.182.08:03:50.31#ibcon#*before return 0, iclass 40, count 0 2006.182.08:03:50.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:03:50.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:03:50.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:03:50.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:03:50.31$vc4f8/va=8,7 2006.182.08:03:50.31#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.08:03:50.31#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.08:03:50.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:50.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:03:50.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:03:50.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:03:50.37#ibcon#enter wrdev, iclass 4, count 2 2006.182.08:03:50.37#ibcon#first serial, iclass 4, count 2 2006.182.08:03:50.37#ibcon#enter sib2, iclass 4, count 2 2006.182.08:03:50.37#ibcon#flushed, iclass 4, count 2 2006.182.08:03:50.37#ibcon#about to write, iclass 4, count 2 2006.182.08:03:50.37#ibcon#wrote, iclass 4, count 2 2006.182.08:03:50.37#ibcon#about to read 3, iclass 4, count 2 2006.182.08:03:50.39#ibcon#read 3, iclass 4, count 2 2006.182.08:03:50.39#ibcon#about to read 4, iclass 4, count 2 2006.182.08:03:50.39#ibcon#read 4, iclass 4, count 2 2006.182.08:03:50.39#ibcon#about to read 5, iclass 4, count 2 2006.182.08:03:50.39#ibcon#read 5, iclass 4, count 2 2006.182.08:03:50.39#ibcon#about to read 6, iclass 4, count 2 2006.182.08:03:50.39#ibcon#read 6, iclass 4, count 2 2006.182.08:03:50.39#ibcon#end of sib2, iclass 4, count 2 2006.182.08:03:50.39#ibcon#*mode == 0, iclass 4, count 2 2006.182.08:03:50.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.08:03:50.39#ibcon#[25=AT08-07\r\n] 2006.182.08:03:50.39#ibcon#*before write, iclass 4, count 2 2006.182.08:03:50.39#ibcon#enter sib2, iclass 4, count 2 2006.182.08:03:50.39#ibcon#flushed, iclass 4, count 2 2006.182.08:03:50.39#ibcon#about to write, iclass 4, count 2 2006.182.08:03:50.39#ibcon#wrote, iclass 4, count 2 2006.182.08:03:50.39#ibcon#about to read 3, iclass 4, count 2 2006.182.08:03:50.42#ibcon#read 3, iclass 4, count 2 2006.182.08:03:50.42#ibcon#about to read 4, iclass 4, count 2 2006.182.08:03:50.42#ibcon#read 4, iclass 4, count 2 2006.182.08:03:50.42#ibcon#about to read 5, iclass 4, count 2 2006.182.08:03:50.42#ibcon#read 5, iclass 4, count 2 2006.182.08:03:50.42#ibcon#about to read 6, iclass 4, count 2 2006.182.08:03:50.42#ibcon#read 6, iclass 4, count 2 2006.182.08:03:50.42#ibcon#end of sib2, iclass 4, count 2 2006.182.08:03:50.42#ibcon#*after write, iclass 4, count 2 2006.182.08:03:50.42#ibcon#*before return 0, iclass 4, count 2 2006.182.08:03:50.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:03:50.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:03:50.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.08:03:50.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:50.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:03:50.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:03:50.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:03:50.54#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:03:50.54#ibcon#first serial, iclass 4, count 0 2006.182.08:03:50.54#ibcon#enter sib2, iclass 4, count 0 2006.182.08:03:50.54#ibcon#flushed, iclass 4, count 0 2006.182.08:03:50.54#ibcon#about to write, iclass 4, count 0 2006.182.08:03:50.54#ibcon#wrote, iclass 4, count 0 2006.182.08:03:50.54#ibcon#about to read 3, iclass 4, count 0 2006.182.08:03:50.56#ibcon#read 3, iclass 4, count 0 2006.182.08:03:50.56#ibcon#about to read 4, iclass 4, count 0 2006.182.08:03:50.56#ibcon#read 4, iclass 4, count 0 2006.182.08:03:50.56#ibcon#about to read 5, iclass 4, count 0 2006.182.08:03:50.56#ibcon#read 5, iclass 4, count 0 2006.182.08:03:50.56#ibcon#about to read 6, iclass 4, count 0 2006.182.08:03:50.56#ibcon#read 6, iclass 4, count 0 2006.182.08:03:50.56#ibcon#end of sib2, iclass 4, count 0 2006.182.08:03:50.56#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:03:50.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:03:50.56#ibcon#[25=USB\r\n] 2006.182.08:03:50.56#ibcon#*before write, iclass 4, count 0 2006.182.08:03:50.56#ibcon#enter sib2, iclass 4, count 0 2006.182.08:03:50.56#ibcon#flushed, iclass 4, count 0 2006.182.08:03:50.56#ibcon#about to write, iclass 4, count 0 2006.182.08:03:50.56#ibcon#wrote, iclass 4, count 0 2006.182.08:03:50.56#ibcon#about to read 3, iclass 4, count 0 2006.182.08:03:50.59#ibcon#read 3, iclass 4, count 0 2006.182.08:03:50.59#ibcon#about to read 4, iclass 4, count 0 2006.182.08:03:50.59#ibcon#read 4, iclass 4, count 0 2006.182.08:03:50.59#ibcon#about to read 5, iclass 4, count 0 2006.182.08:03:50.59#ibcon#read 5, iclass 4, count 0 2006.182.08:03:50.59#ibcon#about to read 6, iclass 4, count 0 2006.182.08:03:50.59#ibcon#read 6, iclass 4, count 0 2006.182.08:03:50.59#ibcon#end of sib2, iclass 4, count 0 2006.182.08:03:50.59#ibcon#*after write, iclass 4, count 0 2006.182.08:03:50.59#ibcon#*before return 0, iclass 4, count 0 2006.182.08:03:50.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:03:50.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:03:50.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:03:50.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:03:50.59$vc4f8/vblo=1,632.99 2006.182.08:03:50.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.08:03:50.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.08:03:50.59#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:50.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:03:50.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:03:50.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:03:50.59#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:03:50.59#ibcon#first serial, iclass 6, count 0 2006.182.08:03:50.59#ibcon#enter sib2, iclass 6, count 0 2006.182.08:03:50.59#ibcon#flushed, iclass 6, count 0 2006.182.08:03:50.59#ibcon#about to write, iclass 6, count 0 2006.182.08:03:50.59#ibcon#wrote, iclass 6, count 0 2006.182.08:03:50.59#ibcon#about to read 3, iclass 6, count 0 2006.182.08:03:50.61#ibcon#read 3, iclass 6, count 0 2006.182.08:03:50.61#ibcon#about to read 4, iclass 6, count 0 2006.182.08:03:50.61#ibcon#read 4, iclass 6, count 0 2006.182.08:03:50.61#ibcon#about to read 5, iclass 6, count 0 2006.182.08:03:50.61#ibcon#read 5, iclass 6, count 0 2006.182.08:03:50.61#ibcon#about to read 6, iclass 6, count 0 2006.182.08:03:50.61#ibcon#read 6, iclass 6, count 0 2006.182.08:03:50.61#ibcon#end of sib2, iclass 6, count 0 2006.182.08:03:50.61#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:03:50.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:03:50.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:03:50.61#ibcon#*before write, iclass 6, count 0 2006.182.08:03:50.61#ibcon#enter sib2, iclass 6, count 0 2006.182.08:03:50.61#ibcon#flushed, iclass 6, count 0 2006.182.08:03:50.61#ibcon#about to write, iclass 6, count 0 2006.182.08:03:50.61#ibcon#wrote, iclass 6, count 0 2006.182.08:03:50.61#ibcon#about to read 3, iclass 6, count 0 2006.182.08:03:50.65#ibcon#read 3, iclass 6, count 0 2006.182.08:03:50.65#ibcon#about to read 4, iclass 6, count 0 2006.182.08:03:50.65#ibcon#read 4, iclass 6, count 0 2006.182.08:03:50.65#ibcon#about to read 5, iclass 6, count 0 2006.182.08:03:50.65#ibcon#read 5, iclass 6, count 0 2006.182.08:03:50.65#ibcon#about to read 6, iclass 6, count 0 2006.182.08:03:50.65#ibcon#read 6, iclass 6, count 0 2006.182.08:03:50.65#ibcon#end of sib2, iclass 6, count 0 2006.182.08:03:50.65#ibcon#*after write, iclass 6, count 0 2006.182.08:03:50.65#ibcon#*before return 0, iclass 6, count 0 2006.182.08:03:50.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:03:50.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:03:50.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:03:50.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:03:50.65$vc4f8/vb=1,4 2006.182.08:03:50.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.08:03:50.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.08:03:50.65#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:50.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:03:50.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:03:50.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:03:50.65#ibcon#enter wrdev, iclass 10, count 2 2006.182.08:03:50.65#ibcon#first serial, iclass 10, count 2 2006.182.08:03:50.65#ibcon#enter sib2, iclass 10, count 2 2006.182.08:03:50.65#ibcon#flushed, iclass 10, count 2 2006.182.08:03:50.65#ibcon#about to write, iclass 10, count 2 2006.182.08:03:50.65#ibcon#wrote, iclass 10, count 2 2006.182.08:03:50.65#ibcon#about to read 3, iclass 10, count 2 2006.182.08:03:50.67#ibcon#read 3, iclass 10, count 2 2006.182.08:03:50.67#ibcon#about to read 4, iclass 10, count 2 2006.182.08:03:50.67#ibcon#read 4, iclass 10, count 2 2006.182.08:03:50.67#ibcon#about to read 5, iclass 10, count 2 2006.182.08:03:50.67#ibcon#read 5, iclass 10, count 2 2006.182.08:03:50.67#ibcon#about to read 6, iclass 10, count 2 2006.182.08:03:50.67#ibcon#read 6, iclass 10, count 2 2006.182.08:03:50.67#ibcon#end of sib2, iclass 10, count 2 2006.182.08:03:50.67#ibcon#*mode == 0, iclass 10, count 2 2006.182.08:03:50.67#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.08:03:50.67#ibcon#[27=AT01-04\r\n] 2006.182.08:03:50.67#ibcon#*before write, iclass 10, count 2 2006.182.08:03:50.67#ibcon#enter sib2, iclass 10, count 2 2006.182.08:03:50.67#ibcon#flushed, iclass 10, count 2 2006.182.08:03:50.67#ibcon#about to write, iclass 10, count 2 2006.182.08:03:50.67#ibcon#wrote, iclass 10, count 2 2006.182.08:03:50.67#ibcon#about to read 3, iclass 10, count 2 2006.182.08:03:50.70#ibcon#read 3, iclass 10, count 2 2006.182.08:03:50.70#ibcon#about to read 4, iclass 10, count 2 2006.182.08:03:50.70#ibcon#read 4, iclass 10, count 2 2006.182.08:03:50.70#ibcon#about to read 5, iclass 10, count 2 2006.182.08:03:50.70#ibcon#read 5, iclass 10, count 2 2006.182.08:03:50.70#ibcon#about to read 6, iclass 10, count 2 2006.182.08:03:50.70#ibcon#read 6, iclass 10, count 2 2006.182.08:03:50.70#ibcon#end of sib2, iclass 10, count 2 2006.182.08:03:50.70#ibcon#*after write, iclass 10, count 2 2006.182.08:03:50.70#ibcon#*before return 0, iclass 10, count 2 2006.182.08:03:50.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:03:50.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:03:50.70#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.08:03:50.70#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:50.70#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:03:50.82#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:03:50.82#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:03:50.82#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:03:50.82#ibcon#first serial, iclass 10, count 0 2006.182.08:03:50.82#ibcon#enter sib2, iclass 10, count 0 2006.182.08:03:50.82#ibcon#flushed, iclass 10, count 0 2006.182.08:03:50.82#ibcon#about to write, iclass 10, count 0 2006.182.08:03:50.82#ibcon#wrote, iclass 10, count 0 2006.182.08:03:50.82#ibcon#about to read 3, iclass 10, count 0 2006.182.08:03:50.84#ibcon#read 3, iclass 10, count 0 2006.182.08:03:50.84#ibcon#about to read 4, iclass 10, count 0 2006.182.08:03:50.84#ibcon#read 4, iclass 10, count 0 2006.182.08:03:50.84#ibcon#about to read 5, iclass 10, count 0 2006.182.08:03:50.84#ibcon#read 5, iclass 10, count 0 2006.182.08:03:50.84#ibcon#about to read 6, iclass 10, count 0 2006.182.08:03:50.84#ibcon#read 6, iclass 10, count 0 2006.182.08:03:50.84#ibcon#end of sib2, iclass 10, count 0 2006.182.08:03:50.84#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:03:50.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:03:50.84#ibcon#[27=USB\r\n] 2006.182.08:03:50.84#ibcon#*before write, iclass 10, count 0 2006.182.08:03:50.84#ibcon#enter sib2, iclass 10, count 0 2006.182.08:03:50.84#ibcon#flushed, iclass 10, count 0 2006.182.08:03:50.84#ibcon#about to write, iclass 10, count 0 2006.182.08:03:50.84#ibcon#wrote, iclass 10, count 0 2006.182.08:03:50.84#ibcon#about to read 3, iclass 10, count 0 2006.182.08:03:50.87#ibcon#read 3, iclass 10, count 0 2006.182.08:03:50.87#ibcon#about to read 4, iclass 10, count 0 2006.182.08:03:50.87#ibcon#read 4, iclass 10, count 0 2006.182.08:03:50.87#ibcon#about to read 5, iclass 10, count 0 2006.182.08:03:50.87#ibcon#read 5, iclass 10, count 0 2006.182.08:03:50.87#ibcon#about to read 6, iclass 10, count 0 2006.182.08:03:50.87#ibcon#read 6, iclass 10, count 0 2006.182.08:03:50.87#ibcon#end of sib2, iclass 10, count 0 2006.182.08:03:50.87#ibcon#*after write, iclass 10, count 0 2006.182.08:03:50.87#ibcon#*before return 0, iclass 10, count 0 2006.182.08:03:50.87#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:03:50.87#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:03:50.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:03:50.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:03:50.87$vc4f8/vblo=2,640.99 2006.182.08:03:50.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.08:03:50.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.08:03:50.87#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:50.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:50.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:50.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:50.87#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:03:50.87#ibcon#first serial, iclass 12, count 0 2006.182.08:03:50.87#ibcon#enter sib2, iclass 12, count 0 2006.182.08:03:50.87#ibcon#flushed, iclass 12, count 0 2006.182.08:03:50.87#ibcon#about to write, iclass 12, count 0 2006.182.08:03:50.87#ibcon#wrote, iclass 12, count 0 2006.182.08:03:50.87#ibcon#about to read 3, iclass 12, count 0 2006.182.08:03:50.89#ibcon#read 3, iclass 12, count 0 2006.182.08:03:50.89#ibcon#about to read 4, iclass 12, count 0 2006.182.08:03:50.89#ibcon#read 4, iclass 12, count 0 2006.182.08:03:50.89#ibcon#about to read 5, iclass 12, count 0 2006.182.08:03:50.89#ibcon#read 5, iclass 12, count 0 2006.182.08:03:50.89#ibcon#about to read 6, iclass 12, count 0 2006.182.08:03:50.89#ibcon#read 6, iclass 12, count 0 2006.182.08:03:50.89#ibcon#end of sib2, iclass 12, count 0 2006.182.08:03:50.89#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:03:50.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:03:50.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:03:50.89#ibcon#*before write, iclass 12, count 0 2006.182.08:03:50.89#ibcon#enter sib2, iclass 12, count 0 2006.182.08:03:50.89#ibcon#flushed, iclass 12, count 0 2006.182.08:03:50.89#ibcon#about to write, iclass 12, count 0 2006.182.08:03:50.89#ibcon#wrote, iclass 12, count 0 2006.182.08:03:50.89#ibcon#about to read 3, iclass 12, count 0 2006.182.08:03:50.93#ibcon#read 3, iclass 12, count 0 2006.182.08:03:50.93#ibcon#about to read 4, iclass 12, count 0 2006.182.08:03:50.93#ibcon#read 4, iclass 12, count 0 2006.182.08:03:50.93#ibcon#about to read 5, iclass 12, count 0 2006.182.08:03:50.93#ibcon#read 5, iclass 12, count 0 2006.182.08:03:50.93#ibcon#about to read 6, iclass 12, count 0 2006.182.08:03:50.93#ibcon#read 6, iclass 12, count 0 2006.182.08:03:50.93#ibcon#end of sib2, iclass 12, count 0 2006.182.08:03:50.93#ibcon#*after write, iclass 12, count 0 2006.182.08:03:50.93#ibcon#*before return 0, iclass 12, count 0 2006.182.08:03:50.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:50.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:03:50.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:03:50.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:03:50.93$vc4f8/vb=2,4 2006.182.08:03:50.93#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.08:03:50.93#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.08:03:50.93#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:50.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:50.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:50.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:50.99#ibcon#enter wrdev, iclass 14, count 2 2006.182.08:03:50.99#ibcon#first serial, iclass 14, count 2 2006.182.08:03:50.99#ibcon#enter sib2, iclass 14, count 2 2006.182.08:03:50.99#ibcon#flushed, iclass 14, count 2 2006.182.08:03:50.99#ibcon#about to write, iclass 14, count 2 2006.182.08:03:50.99#ibcon#wrote, iclass 14, count 2 2006.182.08:03:50.99#ibcon#about to read 3, iclass 14, count 2 2006.182.08:03:51.01#ibcon#read 3, iclass 14, count 2 2006.182.08:03:51.01#ibcon#about to read 4, iclass 14, count 2 2006.182.08:03:51.01#ibcon#read 4, iclass 14, count 2 2006.182.08:03:51.01#ibcon#about to read 5, iclass 14, count 2 2006.182.08:03:51.01#ibcon#read 5, iclass 14, count 2 2006.182.08:03:51.01#ibcon#about to read 6, iclass 14, count 2 2006.182.08:03:51.01#ibcon#read 6, iclass 14, count 2 2006.182.08:03:51.01#ibcon#end of sib2, iclass 14, count 2 2006.182.08:03:51.01#ibcon#*mode == 0, iclass 14, count 2 2006.182.08:03:51.01#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.08:03:51.01#ibcon#[27=AT02-04\r\n] 2006.182.08:03:51.01#ibcon#*before write, iclass 14, count 2 2006.182.08:03:51.01#ibcon#enter sib2, iclass 14, count 2 2006.182.08:03:51.01#ibcon#flushed, iclass 14, count 2 2006.182.08:03:51.01#ibcon#about to write, iclass 14, count 2 2006.182.08:03:51.01#ibcon#wrote, iclass 14, count 2 2006.182.08:03:51.01#ibcon#about to read 3, iclass 14, count 2 2006.182.08:03:51.04#ibcon#read 3, iclass 14, count 2 2006.182.08:03:51.04#ibcon#about to read 4, iclass 14, count 2 2006.182.08:03:51.04#ibcon#read 4, iclass 14, count 2 2006.182.08:03:51.04#ibcon#about to read 5, iclass 14, count 2 2006.182.08:03:51.04#ibcon#read 5, iclass 14, count 2 2006.182.08:03:51.04#ibcon#about to read 6, iclass 14, count 2 2006.182.08:03:51.04#ibcon#read 6, iclass 14, count 2 2006.182.08:03:51.04#ibcon#end of sib2, iclass 14, count 2 2006.182.08:03:51.04#ibcon#*after write, iclass 14, count 2 2006.182.08:03:51.04#ibcon#*before return 0, iclass 14, count 2 2006.182.08:03:51.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:51.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:03:51.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.08:03:51.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:51.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:51.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:51.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:51.16#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:03:51.16#ibcon#first serial, iclass 14, count 0 2006.182.08:03:51.16#ibcon#enter sib2, iclass 14, count 0 2006.182.08:03:51.16#ibcon#flushed, iclass 14, count 0 2006.182.08:03:51.16#ibcon#about to write, iclass 14, count 0 2006.182.08:03:51.16#ibcon#wrote, iclass 14, count 0 2006.182.08:03:51.16#ibcon#about to read 3, iclass 14, count 0 2006.182.08:03:51.18#ibcon#read 3, iclass 14, count 0 2006.182.08:03:51.18#ibcon#about to read 4, iclass 14, count 0 2006.182.08:03:51.18#ibcon#read 4, iclass 14, count 0 2006.182.08:03:51.18#ibcon#about to read 5, iclass 14, count 0 2006.182.08:03:51.18#ibcon#read 5, iclass 14, count 0 2006.182.08:03:51.18#ibcon#about to read 6, iclass 14, count 0 2006.182.08:03:51.18#ibcon#read 6, iclass 14, count 0 2006.182.08:03:51.18#ibcon#end of sib2, iclass 14, count 0 2006.182.08:03:51.18#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:03:51.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:03:51.18#ibcon#[27=USB\r\n] 2006.182.08:03:51.18#ibcon#*before write, iclass 14, count 0 2006.182.08:03:51.18#ibcon#enter sib2, iclass 14, count 0 2006.182.08:03:51.18#ibcon#flushed, iclass 14, count 0 2006.182.08:03:51.18#ibcon#about to write, iclass 14, count 0 2006.182.08:03:51.18#ibcon#wrote, iclass 14, count 0 2006.182.08:03:51.18#ibcon#about to read 3, iclass 14, count 0 2006.182.08:03:51.21#ibcon#read 3, iclass 14, count 0 2006.182.08:03:51.21#ibcon#about to read 4, iclass 14, count 0 2006.182.08:03:51.21#ibcon#read 4, iclass 14, count 0 2006.182.08:03:51.21#ibcon#about to read 5, iclass 14, count 0 2006.182.08:03:51.21#ibcon#read 5, iclass 14, count 0 2006.182.08:03:51.21#ibcon#about to read 6, iclass 14, count 0 2006.182.08:03:51.21#ibcon#read 6, iclass 14, count 0 2006.182.08:03:51.21#ibcon#end of sib2, iclass 14, count 0 2006.182.08:03:51.21#ibcon#*after write, iclass 14, count 0 2006.182.08:03:51.21#ibcon#*before return 0, iclass 14, count 0 2006.182.08:03:51.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:51.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:03:51.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:03:51.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:03:51.21$vc4f8/vblo=3,656.99 2006.182.08:03:51.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.08:03:51.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.08:03:51.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:51.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:51.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:51.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:51.21#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:03:51.21#ibcon#first serial, iclass 16, count 0 2006.182.08:03:51.21#ibcon#enter sib2, iclass 16, count 0 2006.182.08:03:51.21#ibcon#flushed, iclass 16, count 0 2006.182.08:03:51.21#ibcon#about to write, iclass 16, count 0 2006.182.08:03:51.21#ibcon#wrote, iclass 16, count 0 2006.182.08:03:51.21#ibcon#about to read 3, iclass 16, count 0 2006.182.08:03:51.23#ibcon#read 3, iclass 16, count 0 2006.182.08:03:51.23#ibcon#about to read 4, iclass 16, count 0 2006.182.08:03:51.23#ibcon#read 4, iclass 16, count 0 2006.182.08:03:51.23#ibcon#about to read 5, iclass 16, count 0 2006.182.08:03:51.23#ibcon#read 5, iclass 16, count 0 2006.182.08:03:51.23#ibcon#about to read 6, iclass 16, count 0 2006.182.08:03:51.23#ibcon#read 6, iclass 16, count 0 2006.182.08:03:51.23#ibcon#end of sib2, iclass 16, count 0 2006.182.08:03:51.23#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:03:51.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:03:51.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:03:51.23#ibcon#*before write, iclass 16, count 0 2006.182.08:03:51.23#ibcon#enter sib2, iclass 16, count 0 2006.182.08:03:51.23#ibcon#flushed, iclass 16, count 0 2006.182.08:03:51.23#ibcon#about to write, iclass 16, count 0 2006.182.08:03:51.23#ibcon#wrote, iclass 16, count 0 2006.182.08:03:51.23#ibcon#about to read 3, iclass 16, count 0 2006.182.08:03:51.27#ibcon#read 3, iclass 16, count 0 2006.182.08:03:51.27#ibcon#about to read 4, iclass 16, count 0 2006.182.08:03:51.27#ibcon#read 4, iclass 16, count 0 2006.182.08:03:51.27#ibcon#about to read 5, iclass 16, count 0 2006.182.08:03:51.27#ibcon#read 5, iclass 16, count 0 2006.182.08:03:51.27#ibcon#about to read 6, iclass 16, count 0 2006.182.08:03:51.27#ibcon#read 6, iclass 16, count 0 2006.182.08:03:51.27#ibcon#end of sib2, iclass 16, count 0 2006.182.08:03:51.27#ibcon#*after write, iclass 16, count 0 2006.182.08:03:51.27#ibcon#*before return 0, iclass 16, count 0 2006.182.08:03:51.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:51.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:03:51.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:03:51.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:03:51.27$vc4f8/vb=3,4 2006.182.08:03:51.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.08:03:51.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.08:03:51.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:51.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:51.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:51.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:51.33#ibcon#enter wrdev, iclass 18, count 2 2006.182.08:03:51.33#ibcon#first serial, iclass 18, count 2 2006.182.08:03:51.33#ibcon#enter sib2, iclass 18, count 2 2006.182.08:03:51.33#ibcon#flushed, iclass 18, count 2 2006.182.08:03:51.33#ibcon#about to write, iclass 18, count 2 2006.182.08:03:51.33#ibcon#wrote, iclass 18, count 2 2006.182.08:03:51.33#ibcon#about to read 3, iclass 18, count 2 2006.182.08:03:51.35#ibcon#read 3, iclass 18, count 2 2006.182.08:03:51.35#ibcon#about to read 4, iclass 18, count 2 2006.182.08:03:51.35#ibcon#read 4, iclass 18, count 2 2006.182.08:03:51.35#ibcon#about to read 5, iclass 18, count 2 2006.182.08:03:51.35#ibcon#read 5, iclass 18, count 2 2006.182.08:03:51.35#ibcon#about to read 6, iclass 18, count 2 2006.182.08:03:51.35#ibcon#read 6, iclass 18, count 2 2006.182.08:03:51.35#ibcon#end of sib2, iclass 18, count 2 2006.182.08:03:51.35#ibcon#*mode == 0, iclass 18, count 2 2006.182.08:03:51.35#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.08:03:51.35#ibcon#[27=AT03-04\r\n] 2006.182.08:03:51.35#ibcon#*before write, iclass 18, count 2 2006.182.08:03:51.35#ibcon#enter sib2, iclass 18, count 2 2006.182.08:03:51.35#ibcon#flushed, iclass 18, count 2 2006.182.08:03:51.35#ibcon#about to write, iclass 18, count 2 2006.182.08:03:51.35#ibcon#wrote, iclass 18, count 2 2006.182.08:03:51.35#ibcon#about to read 3, iclass 18, count 2 2006.182.08:03:51.38#ibcon#read 3, iclass 18, count 2 2006.182.08:03:51.38#ibcon#about to read 4, iclass 18, count 2 2006.182.08:03:51.38#ibcon#read 4, iclass 18, count 2 2006.182.08:03:51.38#ibcon#about to read 5, iclass 18, count 2 2006.182.08:03:51.38#ibcon#read 5, iclass 18, count 2 2006.182.08:03:51.38#ibcon#about to read 6, iclass 18, count 2 2006.182.08:03:51.38#ibcon#read 6, iclass 18, count 2 2006.182.08:03:51.38#ibcon#end of sib2, iclass 18, count 2 2006.182.08:03:51.38#ibcon#*after write, iclass 18, count 2 2006.182.08:03:51.38#ibcon#*before return 0, iclass 18, count 2 2006.182.08:03:51.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:51.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:03:51.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.08:03:51.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:51.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:51.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:51.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:51.50#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:03:51.50#ibcon#first serial, iclass 18, count 0 2006.182.08:03:51.50#ibcon#enter sib2, iclass 18, count 0 2006.182.08:03:51.50#ibcon#flushed, iclass 18, count 0 2006.182.08:03:51.50#ibcon#about to write, iclass 18, count 0 2006.182.08:03:51.50#ibcon#wrote, iclass 18, count 0 2006.182.08:03:51.50#ibcon#about to read 3, iclass 18, count 0 2006.182.08:03:51.52#ibcon#read 3, iclass 18, count 0 2006.182.08:03:51.52#ibcon#about to read 4, iclass 18, count 0 2006.182.08:03:51.52#ibcon#read 4, iclass 18, count 0 2006.182.08:03:51.52#ibcon#about to read 5, iclass 18, count 0 2006.182.08:03:51.52#ibcon#read 5, iclass 18, count 0 2006.182.08:03:51.52#ibcon#about to read 6, iclass 18, count 0 2006.182.08:03:51.52#ibcon#read 6, iclass 18, count 0 2006.182.08:03:51.52#ibcon#end of sib2, iclass 18, count 0 2006.182.08:03:51.52#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:03:51.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:03:51.52#ibcon#[27=USB\r\n] 2006.182.08:03:51.52#ibcon#*before write, iclass 18, count 0 2006.182.08:03:51.52#ibcon#enter sib2, iclass 18, count 0 2006.182.08:03:51.52#ibcon#flushed, iclass 18, count 0 2006.182.08:03:51.52#ibcon#about to write, iclass 18, count 0 2006.182.08:03:51.52#ibcon#wrote, iclass 18, count 0 2006.182.08:03:51.52#ibcon#about to read 3, iclass 18, count 0 2006.182.08:03:51.55#ibcon#read 3, iclass 18, count 0 2006.182.08:03:51.55#ibcon#about to read 4, iclass 18, count 0 2006.182.08:03:51.55#ibcon#read 4, iclass 18, count 0 2006.182.08:03:51.55#ibcon#about to read 5, iclass 18, count 0 2006.182.08:03:51.55#ibcon#read 5, iclass 18, count 0 2006.182.08:03:51.55#ibcon#about to read 6, iclass 18, count 0 2006.182.08:03:51.55#ibcon#read 6, iclass 18, count 0 2006.182.08:03:51.55#ibcon#end of sib2, iclass 18, count 0 2006.182.08:03:51.55#ibcon#*after write, iclass 18, count 0 2006.182.08:03:51.55#ibcon#*before return 0, iclass 18, count 0 2006.182.08:03:51.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:51.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:03:51.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:03:51.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:03:51.55$vc4f8/vblo=4,712.99 2006.182.08:03:51.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.08:03:51.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.08:03:51.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:51.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:51.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:51.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:51.55#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:03:51.55#ibcon#first serial, iclass 20, count 0 2006.182.08:03:51.55#ibcon#enter sib2, iclass 20, count 0 2006.182.08:03:51.55#ibcon#flushed, iclass 20, count 0 2006.182.08:03:51.55#ibcon#about to write, iclass 20, count 0 2006.182.08:03:51.55#ibcon#wrote, iclass 20, count 0 2006.182.08:03:51.55#ibcon#about to read 3, iclass 20, count 0 2006.182.08:03:51.57#ibcon#read 3, iclass 20, count 0 2006.182.08:03:51.57#ibcon#about to read 4, iclass 20, count 0 2006.182.08:03:51.57#ibcon#read 4, iclass 20, count 0 2006.182.08:03:51.57#ibcon#about to read 5, iclass 20, count 0 2006.182.08:03:51.57#ibcon#read 5, iclass 20, count 0 2006.182.08:03:51.57#ibcon#about to read 6, iclass 20, count 0 2006.182.08:03:51.57#ibcon#read 6, iclass 20, count 0 2006.182.08:03:51.57#ibcon#end of sib2, iclass 20, count 0 2006.182.08:03:51.57#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:03:51.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:03:51.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:03:51.57#ibcon#*before write, iclass 20, count 0 2006.182.08:03:51.57#ibcon#enter sib2, iclass 20, count 0 2006.182.08:03:51.57#ibcon#flushed, iclass 20, count 0 2006.182.08:03:51.57#ibcon#about to write, iclass 20, count 0 2006.182.08:03:51.57#ibcon#wrote, iclass 20, count 0 2006.182.08:03:51.57#ibcon#about to read 3, iclass 20, count 0 2006.182.08:03:51.61#ibcon#read 3, iclass 20, count 0 2006.182.08:03:51.61#ibcon#about to read 4, iclass 20, count 0 2006.182.08:03:51.61#ibcon#read 4, iclass 20, count 0 2006.182.08:03:51.61#ibcon#about to read 5, iclass 20, count 0 2006.182.08:03:51.61#ibcon#read 5, iclass 20, count 0 2006.182.08:03:51.61#ibcon#about to read 6, iclass 20, count 0 2006.182.08:03:51.61#ibcon#read 6, iclass 20, count 0 2006.182.08:03:51.61#ibcon#end of sib2, iclass 20, count 0 2006.182.08:03:51.61#ibcon#*after write, iclass 20, count 0 2006.182.08:03:51.61#ibcon#*before return 0, iclass 20, count 0 2006.182.08:03:51.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:51.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:03:51.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:03:51.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:03:51.61$vc4f8/vb=4,4 2006.182.08:03:51.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.08:03:51.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.08:03:51.61#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:51.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:51.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:51.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:51.67#ibcon#enter wrdev, iclass 22, count 2 2006.182.08:03:51.67#ibcon#first serial, iclass 22, count 2 2006.182.08:03:51.67#ibcon#enter sib2, iclass 22, count 2 2006.182.08:03:51.67#ibcon#flushed, iclass 22, count 2 2006.182.08:03:51.67#ibcon#about to write, iclass 22, count 2 2006.182.08:03:51.67#ibcon#wrote, iclass 22, count 2 2006.182.08:03:51.67#ibcon#about to read 3, iclass 22, count 2 2006.182.08:03:51.69#ibcon#read 3, iclass 22, count 2 2006.182.08:03:51.69#ibcon#about to read 4, iclass 22, count 2 2006.182.08:03:51.69#ibcon#read 4, iclass 22, count 2 2006.182.08:03:51.69#ibcon#about to read 5, iclass 22, count 2 2006.182.08:03:51.69#ibcon#read 5, iclass 22, count 2 2006.182.08:03:51.69#ibcon#about to read 6, iclass 22, count 2 2006.182.08:03:51.69#ibcon#read 6, iclass 22, count 2 2006.182.08:03:51.69#ibcon#end of sib2, iclass 22, count 2 2006.182.08:03:51.69#ibcon#*mode == 0, iclass 22, count 2 2006.182.08:03:51.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.08:03:51.69#ibcon#[27=AT04-04\r\n] 2006.182.08:03:51.69#ibcon#*before write, iclass 22, count 2 2006.182.08:03:51.69#ibcon#enter sib2, iclass 22, count 2 2006.182.08:03:51.69#ibcon#flushed, iclass 22, count 2 2006.182.08:03:51.69#ibcon#about to write, iclass 22, count 2 2006.182.08:03:51.69#ibcon#wrote, iclass 22, count 2 2006.182.08:03:51.69#ibcon#about to read 3, iclass 22, count 2 2006.182.08:03:51.72#ibcon#read 3, iclass 22, count 2 2006.182.08:03:51.72#ibcon#about to read 4, iclass 22, count 2 2006.182.08:03:51.72#ibcon#read 4, iclass 22, count 2 2006.182.08:03:51.72#ibcon#about to read 5, iclass 22, count 2 2006.182.08:03:51.72#ibcon#read 5, iclass 22, count 2 2006.182.08:03:51.72#ibcon#about to read 6, iclass 22, count 2 2006.182.08:03:51.72#ibcon#read 6, iclass 22, count 2 2006.182.08:03:51.72#ibcon#end of sib2, iclass 22, count 2 2006.182.08:03:51.72#ibcon#*after write, iclass 22, count 2 2006.182.08:03:51.72#ibcon#*before return 0, iclass 22, count 2 2006.182.08:03:51.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:51.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:03:51.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.08:03:51.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:51.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:51.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:51.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:51.84#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:03:51.84#ibcon#first serial, iclass 22, count 0 2006.182.08:03:51.84#ibcon#enter sib2, iclass 22, count 0 2006.182.08:03:51.84#ibcon#flushed, iclass 22, count 0 2006.182.08:03:51.84#ibcon#about to write, iclass 22, count 0 2006.182.08:03:51.84#ibcon#wrote, iclass 22, count 0 2006.182.08:03:51.84#ibcon#about to read 3, iclass 22, count 0 2006.182.08:03:51.86#ibcon#read 3, iclass 22, count 0 2006.182.08:03:51.86#ibcon#about to read 4, iclass 22, count 0 2006.182.08:03:51.86#ibcon#read 4, iclass 22, count 0 2006.182.08:03:51.86#ibcon#about to read 5, iclass 22, count 0 2006.182.08:03:51.86#ibcon#read 5, iclass 22, count 0 2006.182.08:03:51.86#ibcon#about to read 6, iclass 22, count 0 2006.182.08:03:51.86#ibcon#read 6, iclass 22, count 0 2006.182.08:03:51.86#ibcon#end of sib2, iclass 22, count 0 2006.182.08:03:51.86#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:03:51.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:03:51.86#ibcon#[27=USB\r\n] 2006.182.08:03:51.86#ibcon#*before write, iclass 22, count 0 2006.182.08:03:51.86#ibcon#enter sib2, iclass 22, count 0 2006.182.08:03:51.86#ibcon#flushed, iclass 22, count 0 2006.182.08:03:51.86#ibcon#about to write, iclass 22, count 0 2006.182.08:03:51.86#ibcon#wrote, iclass 22, count 0 2006.182.08:03:51.86#ibcon#about to read 3, iclass 22, count 0 2006.182.08:03:51.89#ibcon#read 3, iclass 22, count 0 2006.182.08:03:51.89#ibcon#about to read 4, iclass 22, count 0 2006.182.08:03:51.89#ibcon#read 4, iclass 22, count 0 2006.182.08:03:51.89#ibcon#about to read 5, iclass 22, count 0 2006.182.08:03:51.89#ibcon#read 5, iclass 22, count 0 2006.182.08:03:51.89#ibcon#about to read 6, iclass 22, count 0 2006.182.08:03:51.89#ibcon#read 6, iclass 22, count 0 2006.182.08:03:51.89#ibcon#end of sib2, iclass 22, count 0 2006.182.08:03:51.89#ibcon#*after write, iclass 22, count 0 2006.182.08:03:51.89#ibcon#*before return 0, iclass 22, count 0 2006.182.08:03:51.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:51.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:03:51.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:03:51.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:03:51.89$vc4f8/vblo=5,744.99 2006.182.08:03:51.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.08:03:51.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.08:03:51.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:51.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:51.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:51.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:51.89#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:03:51.89#ibcon#first serial, iclass 24, count 0 2006.182.08:03:51.89#ibcon#enter sib2, iclass 24, count 0 2006.182.08:03:51.89#ibcon#flushed, iclass 24, count 0 2006.182.08:03:51.89#ibcon#about to write, iclass 24, count 0 2006.182.08:03:51.89#ibcon#wrote, iclass 24, count 0 2006.182.08:03:51.89#ibcon#about to read 3, iclass 24, count 0 2006.182.08:03:51.92#ibcon#read 3, iclass 24, count 0 2006.182.08:03:51.92#ibcon#about to read 4, iclass 24, count 0 2006.182.08:03:51.92#ibcon#read 4, iclass 24, count 0 2006.182.08:03:51.92#ibcon#about to read 5, iclass 24, count 0 2006.182.08:03:51.92#ibcon#read 5, iclass 24, count 0 2006.182.08:03:51.92#ibcon#about to read 6, iclass 24, count 0 2006.182.08:03:51.92#ibcon#read 6, iclass 24, count 0 2006.182.08:03:51.92#ibcon#end of sib2, iclass 24, count 0 2006.182.08:03:51.92#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:03:51.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:03:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:03:51.92#ibcon#*before write, iclass 24, count 0 2006.182.08:03:51.92#ibcon#enter sib2, iclass 24, count 0 2006.182.08:03:51.92#ibcon#flushed, iclass 24, count 0 2006.182.08:03:51.92#ibcon#about to write, iclass 24, count 0 2006.182.08:03:51.92#ibcon#wrote, iclass 24, count 0 2006.182.08:03:51.92#ibcon#about to read 3, iclass 24, count 0 2006.182.08:03:51.96#ibcon#read 3, iclass 24, count 0 2006.182.08:03:51.96#ibcon#about to read 4, iclass 24, count 0 2006.182.08:03:51.96#ibcon#read 4, iclass 24, count 0 2006.182.08:03:51.96#ibcon#about to read 5, iclass 24, count 0 2006.182.08:03:51.96#ibcon#read 5, iclass 24, count 0 2006.182.08:03:51.96#ibcon#about to read 6, iclass 24, count 0 2006.182.08:03:51.96#ibcon#read 6, iclass 24, count 0 2006.182.08:03:51.96#ibcon#end of sib2, iclass 24, count 0 2006.182.08:03:51.96#ibcon#*after write, iclass 24, count 0 2006.182.08:03:51.96#ibcon#*before return 0, iclass 24, count 0 2006.182.08:03:51.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:51.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:03:51.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:03:51.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:03:51.96$vc4f8/vb=5,4 2006.182.08:03:51.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.08:03:51.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.08:03:51.96#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:51.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:52.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:52.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:52.01#ibcon#enter wrdev, iclass 26, count 2 2006.182.08:03:52.01#ibcon#first serial, iclass 26, count 2 2006.182.08:03:52.01#ibcon#enter sib2, iclass 26, count 2 2006.182.08:03:52.01#ibcon#flushed, iclass 26, count 2 2006.182.08:03:52.01#ibcon#about to write, iclass 26, count 2 2006.182.08:03:52.01#ibcon#wrote, iclass 26, count 2 2006.182.08:03:52.01#ibcon#about to read 3, iclass 26, count 2 2006.182.08:03:52.03#ibcon#read 3, iclass 26, count 2 2006.182.08:03:52.03#ibcon#about to read 4, iclass 26, count 2 2006.182.08:03:52.03#ibcon#read 4, iclass 26, count 2 2006.182.08:03:52.03#ibcon#about to read 5, iclass 26, count 2 2006.182.08:03:52.03#ibcon#read 5, iclass 26, count 2 2006.182.08:03:52.03#ibcon#about to read 6, iclass 26, count 2 2006.182.08:03:52.03#ibcon#read 6, iclass 26, count 2 2006.182.08:03:52.03#ibcon#end of sib2, iclass 26, count 2 2006.182.08:03:52.03#ibcon#*mode == 0, iclass 26, count 2 2006.182.08:03:52.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.08:03:52.03#ibcon#[27=AT05-04\r\n] 2006.182.08:03:52.03#ibcon#*before write, iclass 26, count 2 2006.182.08:03:52.03#ibcon#enter sib2, iclass 26, count 2 2006.182.08:03:52.03#ibcon#flushed, iclass 26, count 2 2006.182.08:03:52.03#ibcon#about to write, iclass 26, count 2 2006.182.08:03:52.03#ibcon#wrote, iclass 26, count 2 2006.182.08:03:52.03#ibcon#about to read 3, iclass 26, count 2 2006.182.08:03:52.06#ibcon#read 3, iclass 26, count 2 2006.182.08:03:52.06#ibcon#about to read 4, iclass 26, count 2 2006.182.08:03:52.06#ibcon#read 4, iclass 26, count 2 2006.182.08:03:52.06#ibcon#about to read 5, iclass 26, count 2 2006.182.08:03:52.06#ibcon#read 5, iclass 26, count 2 2006.182.08:03:52.06#ibcon#about to read 6, iclass 26, count 2 2006.182.08:03:52.06#ibcon#read 6, iclass 26, count 2 2006.182.08:03:52.06#ibcon#end of sib2, iclass 26, count 2 2006.182.08:03:52.06#ibcon#*after write, iclass 26, count 2 2006.182.08:03:52.06#ibcon#*before return 0, iclass 26, count 2 2006.182.08:03:52.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:52.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:03:52.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.08:03:52.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:52.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:52.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:52.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:52.18#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:03:52.18#ibcon#first serial, iclass 26, count 0 2006.182.08:03:52.18#ibcon#enter sib2, iclass 26, count 0 2006.182.08:03:52.18#ibcon#flushed, iclass 26, count 0 2006.182.08:03:52.18#ibcon#about to write, iclass 26, count 0 2006.182.08:03:52.18#ibcon#wrote, iclass 26, count 0 2006.182.08:03:52.18#ibcon#about to read 3, iclass 26, count 0 2006.182.08:03:52.20#ibcon#read 3, iclass 26, count 0 2006.182.08:03:52.20#ibcon#about to read 4, iclass 26, count 0 2006.182.08:03:52.20#ibcon#read 4, iclass 26, count 0 2006.182.08:03:52.20#ibcon#about to read 5, iclass 26, count 0 2006.182.08:03:52.20#ibcon#read 5, iclass 26, count 0 2006.182.08:03:52.20#ibcon#about to read 6, iclass 26, count 0 2006.182.08:03:52.20#ibcon#read 6, iclass 26, count 0 2006.182.08:03:52.20#ibcon#end of sib2, iclass 26, count 0 2006.182.08:03:52.20#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:03:52.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:03:52.20#ibcon#[27=USB\r\n] 2006.182.08:03:52.20#ibcon#*before write, iclass 26, count 0 2006.182.08:03:52.20#ibcon#enter sib2, iclass 26, count 0 2006.182.08:03:52.20#ibcon#flushed, iclass 26, count 0 2006.182.08:03:52.20#ibcon#about to write, iclass 26, count 0 2006.182.08:03:52.20#ibcon#wrote, iclass 26, count 0 2006.182.08:03:52.20#ibcon#about to read 3, iclass 26, count 0 2006.182.08:03:52.23#ibcon#read 3, iclass 26, count 0 2006.182.08:03:52.23#ibcon#about to read 4, iclass 26, count 0 2006.182.08:03:52.23#ibcon#read 4, iclass 26, count 0 2006.182.08:03:52.23#ibcon#about to read 5, iclass 26, count 0 2006.182.08:03:52.23#ibcon#read 5, iclass 26, count 0 2006.182.08:03:52.23#ibcon#about to read 6, iclass 26, count 0 2006.182.08:03:52.23#ibcon#read 6, iclass 26, count 0 2006.182.08:03:52.23#ibcon#end of sib2, iclass 26, count 0 2006.182.08:03:52.23#ibcon#*after write, iclass 26, count 0 2006.182.08:03:52.23#ibcon#*before return 0, iclass 26, count 0 2006.182.08:03:52.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:52.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:03:52.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:03:52.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:03:52.23$vc4f8/vblo=6,752.99 2006.182.08:03:52.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.08:03:52.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.08:03:52.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:03:52.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:52.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:52.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:52.23#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:03:52.23#ibcon#first serial, iclass 28, count 0 2006.182.08:03:52.23#ibcon#enter sib2, iclass 28, count 0 2006.182.08:03:52.23#ibcon#flushed, iclass 28, count 0 2006.182.08:03:52.23#ibcon#about to write, iclass 28, count 0 2006.182.08:03:52.23#ibcon#wrote, iclass 28, count 0 2006.182.08:03:52.23#ibcon#about to read 3, iclass 28, count 0 2006.182.08:03:52.25#ibcon#read 3, iclass 28, count 0 2006.182.08:03:52.25#ibcon#about to read 4, iclass 28, count 0 2006.182.08:03:52.25#ibcon#read 4, iclass 28, count 0 2006.182.08:03:52.25#ibcon#about to read 5, iclass 28, count 0 2006.182.08:03:52.25#ibcon#read 5, iclass 28, count 0 2006.182.08:03:52.25#ibcon#about to read 6, iclass 28, count 0 2006.182.08:03:52.25#ibcon#read 6, iclass 28, count 0 2006.182.08:03:52.25#ibcon#end of sib2, iclass 28, count 0 2006.182.08:03:52.25#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:03:52.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:03:52.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:03:52.25#ibcon#*before write, iclass 28, count 0 2006.182.08:03:52.25#ibcon#enter sib2, iclass 28, count 0 2006.182.08:03:52.25#ibcon#flushed, iclass 28, count 0 2006.182.08:03:52.25#ibcon#about to write, iclass 28, count 0 2006.182.08:03:52.25#ibcon#wrote, iclass 28, count 0 2006.182.08:03:52.25#ibcon#about to read 3, iclass 28, count 0 2006.182.08:03:52.29#ibcon#read 3, iclass 28, count 0 2006.182.08:03:52.29#ibcon#about to read 4, iclass 28, count 0 2006.182.08:03:52.29#ibcon#read 4, iclass 28, count 0 2006.182.08:03:52.29#ibcon#about to read 5, iclass 28, count 0 2006.182.08:03:52.29#ibcon#read 5, iclass 28, count 0 2006.182.08:03:52.29#ibcon#about to read 6, iclass 28, count 0 2006.182.08:03:52.29#ibcon#read 6, iclass 28, count 0 2006.182.08:03:52.29#ibcon#end of sib2, iclass 28, count 0 2006.182.08:03:52.29#ibcon#*after write, iclass 28, count 0 2006.182.08:03:52.29#ibcon#*before return 0, iclass 28, count 0 2006.182.08:03:52.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:52.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:03:52.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:03:52.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:03:52.29$vc4f8/vb=6,4 2006.182.08:03:52.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.08:03:52.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.08:03:52.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:03:52.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:52.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:52.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:52.35#ibcon#enter wrdev, iclass 30, count 2 2006.182.08:03:52.35#ibcon#first serial, iclass 30, count 2 2006.182.08:03:52.35#ibcon#enter sib2, iclass 30, count 2 2006.182.08:03:52.35#ibcon#flushed, iclass 30, count 2 2006.182.08:03:52.35#ibcon#about to write, iclass 30, count 2 2006.182.08:03:52.35#ibcon#wrote, iclass 30, count 2 2006.182.08:03:52.35#ibcon#about to read 3, iclass 30, count 2 2006.182.08:03:52.37#ibcon#read 3, iclass 30, count 2 2006.182.08:03:52.37#ibcon#about to read 4, iclass 30, count 2 2006.182.08:03:52.37#ibcon#read 4, iclass 30, count 2 2006.182.08:03:52.37#ibcon#about to read 5, iclass 30, count 2 2006.182.08:03:52.37#ibcon#read 5, iclass 30, count 2 2006.182.08:03:52.37#ibcon#about to read 6, iclass 30, count 2 2006.182.08:03:52.37#ibcon#read 6, iclass 30, count 2 2006.182.08:03:52.37#ibcon#end of sib2, iclass 30, count 2 2006.182.08:03:52.37#ibcon#*mode == 0, iclass 30, count 2 2006.182.08:03:52.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.08:03:52.37#ibcon#[27=AT06-04\r\n] 2006.182.08:03:52.37#ibcon#*before write, iclass 30, count 2 2006.182.08:03:52.37#ibcon#enter sib2, iclass 30, count 2 2006.182.08:03:52.37#ibcon#flushed, iclass 30, count 2 2006.182.08:03:52.37#ibcon#about to write, iclass 30, count 2 2006.182.08:03:52.37#ibcon#wrote, iclass 30, count 2 2006.182.08:03:52.37#ibcon#about to read 3, iclass 30, count 2 2006.182.08:03:52.40#ibcon#read 3, iclass 30, count 2 2006.182.08:03:52.40#ibcon#about to read 4, iclass 30, count 2 2006.182.08:03:52.40#ibcon#read 4, iclass 30, count 2 2006.182.08:03:52.40#ibcon#about to read 5, iclass 30, count 2 2006.182.08:03:52.40#ibcon#read 5, iclass 30, count 2 2006.182.08:03:52.40#ibcon#about to read 6, iclass 30, count 2 2006.182.08:03:52.40#ibcon#read 6, iclass 30, count 2 2006.182.08:03:52.40#ibcon#end of sib2, iclass 30, count 2 2006.182.08:03:52.40#ibcon#*after write, iclass 30, count 2 2006.182.08:03:52.40#ibcon#*before return 0, iclass 30, count 2 2006.182.08:03:52.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:52.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:03:52.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.08:03:52.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:03:52.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:52.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:52.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:52.52#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:03:52.52#ibcon#first serial, iclass 30, count 0 2006.182.08:03:52.52#ibcon#enter sib2, iclass 30, count 0 2006.182.08:03:52.52#ibcon#flushed, iclass 30, count 0 2006.182.08:03:52.52#ibcon#about to write, iclass 30, count 0 2006.182.08:03:52.52#ibcon#wrote, iclass 30, count 0 2006.182.08:03:52.52#ibcon#about to read 3, iclass 30, count 0 2006.182.08:03:52.54#ibcon#read 3, iclass 30, count 0 2006.182.08:03:52.54#ibcon#about to read 4, iclass 30, count 0 2006.182.08:03:52.54#ibcon#read 4, iclass 30, count 0 2006.182.08:03:52.54#ibcon#about to read 5, iclass 30, count 0 2006.182.08:03:52.54#ibcon#read 5, iclass 30, count 0 2006.182.08:03:52.54#ibcon#about to read 6, iclass 30, count 0 2006.182.08:03:52.54#ibcon#read 6, iclass 30, count 0 2006.182.08:03:52.54#ibcon#end of sib2, iclass 30, count 0 2006.182.08:03:52.54#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:03:52.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:03:52.54#ibcon#[27=USB\r\n] 2006.182.08:03:52.54#ibcon#*before write, iclass 30, count 0 2006.182.08:03:52.54#ibcon#enter sib2, iclass 30, count 0 2006.182.08:03:52.54#ibcon#flushed, iclass 30, count 0 2006.182.08:03:52.54#ibcon#about to write, iclass 30, count 0 2006.182.08:03:52.54#ibcon#wrote, iclass 30, count 0 2006.182.08:03:52.54#ibcon#about to read 3, iclass 30, count 0 2006.182.08:03:52.57#ibcon#read 3, iclass 30, count 0 2006.182.08:03:52.57#ibcon#about to read 4, iclass 30, count 0 2006.182.08:03:52.57#ibcon#read 4, iclass 30, count 0 2006.182.08:03:52.57#ibcon#about to read 5, iclass 30, count 0 2006.182.08:03:52.57#ibcon#read 5, iclass 30, count 0 2006.182.08:03:52.57#ibcon#about to read 6, iclass 30, count 0 2006.182.08:03:52.57#ibcon#read 6, iclass 30, count 0 2006.182.08:03:52.57#ibcon#end of sib2, iclass 30, count 0 2006.182.08:03:52.57#ibcon#*after write, iclass 30, count 0 2006.182.08:03:52.57#ibcon#*before return 0, iclass 30, count 0 2006.182.08:03:52.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:52.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:03:52.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:03:52.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:03:52.57$vc4f8/vabw=wide 2006.182.08:03:52.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.08:03:52.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.08:03:52.57#ibcon#ireg 8 cls_cnt 0 2006.182.08:03:52.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:52.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:52.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:52.57#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:03:52.57#ibcon#first serial, iclass 32, count 0 2006.182.08:03:52.57#ibcon#enter sib2, iclass 32, count 0 2006.182.08:03:52.57#ibcon#flushed, iclass 32, count 0 2006.182.08:03:52.57#ibcon#about to write, iclass 32, count 0 2006.182.08:03:52.57#ibcon#wrote, iclass 32, count 0 2006.182.08:03:52.57#ibcon#about to read 3, iclass 32, count 0 2006.182.08:03:52.59#ibcon#read 3, iclass 32, count 0 2006.182.08:03:52.59#ibcon#about to read 4, iclass 32, count 0 2006.182.08:03:52.59#ibcon#read 4, iclass 32, count 0 2006.182.08:03:52.59#ibcon#about to read 5, iclass 32, count 0 2006.182.08:03:52.59#ibcon#read 5, iclass 32, count 0 2006.182.08:03:52.59#ibcon#about to read 6, iclass 32, count 0 2006.182.08:03:52.59#ibcon#read 6, iclass 32, count 0 2006.182.08:03:52.59#ibcon#end of sib2, iclass 32, count 0 2006.182.08:03:52.59#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:03:52.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:03:52.59#ibcon#[25=BW32\r\n] 2006.182.08:03:52.59#ibcon#*before write, iclass 32, count 0 2006.182.08:03:52.59#ibcon#enter sib2, iclass 32, count 0 2006.182.08:03:52.59#ibcon#flushed, iclass 32, count 0 2006.182.08:03:52.59#ibcon#about to write, iclass 32, count 0 2006.182.08:03:52.59#ibcon#wrote, iclass 32, count 0 2006.182.08:03:52.59#ibcon#about to read 3, iclass 32, count 0 2006.182.08:03:52.62#ibcon#read 3, iclass 32, count 0 2006.182.08:03:52.62#ibcon#about to read 4, iclass 32, count 0 2006.182.08:03:52.62#ibcon#read 4, iclass 32, count 0 2006.182.08:03:52.62#ibcon#about to read 5, iclass 32, count 0 2006.182.08:03:52.62#ibcon#read 5, iclass 32, count 0 2006.182.08:03:52.62#ibcon#about to read 6, iclass 32, count 0 2006.182.08:03:52.62#ibcon#read 6, iclass 32, count 0 2006.182.08:03:52.62#ibcon#end of sib2, iclass 32, count 0 2006.182.08:03:52.62#ibcon#*after write, iclass 32, count 0 2006.182.08:03:52.62#ibcon#*before return 0, iclass 32, count 0 2006.182.08:03:52.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:52.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:03:52.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:03:52.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:03:52.62$vc4f8/vbbw=wide 2006.182.08:03:52.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.08:03:52.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.08:03:52.62#ibcon#ireg 8 cls_cnt 0 2006.182.08:03:52.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:03:52.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:03:52.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:03:52.69#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:03:52.69#ibcon#first serial, iclass 34, count 0 2006.182.08:03:52.69#ibcon#enter sib2, iclass 34, count 0 2006.182.08:03:52.69#ibcon#flushed, iclass 34, count 0 2006.182.08:03:52.69#ibcon#about to write, iclass 34, count 0 2006.182.08:03:52.69#ibcon#wrote, iclass 34, count 0 2006.182.08:03:52.69#ibcon#about to read 3, iclass 34, count 0 2006.182.08:03:52.71#ibcon#read 3, iclass 34, count 0 2006.182.08:03:52.71#ibcon#about to read 4, iclass 34, count 0 2006.182.08:03:52.71#ibcon#read 4, iclass 34, count 0 2006.182.08:03:52.71#ibcon#about to read 5, iclass 34, count 0 2006.182.08:03:52.71#ibcon#read 5, iclass 34, count 0 2006.182.08:03:52.71#ibcon#about to read 6, iclass 34, count 0 2006.182.08:03:52.71#ibcon#read 6, iclass 34, count 0 2006.182.08:03:52.71#ibcon#end of sib2, iclass 34, count 0 2006.182.08:03:52.71#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:03:52.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:03:52.71#ibcon#[27=BW32\r\n] 2006.182.08:03:52.71#ibcon#*before write, iclass 34, count 0 2006.182.08:03:52.71#ibcon#enter sib2, iclass 34, count 0 2006.182.08:03:52.71#ibcon#flushed, iclass 34, count 0 2006.182.08:03:52.71#ibcon#about to write, iclass 34, count 0 2006.182.08:03:52.71#ibcon#wrote, iclass 34, count 0 2006.182.08:03:52.71#ibcon#about to read 3, iclass 34, count 0 2006.182.08:03:52.74#ibcon#read 3, iclass 34, count 0 2006.182.08:03:52.74#ibcon#about to read 4, iclass 34, count 0 2006.182.08:03:52.74#ibcon#read 4, iclass 34, count 0 2006.182.08:03:52.74#ibcon#about to read 5, iclass 34, count 0 2006.182.08:03:52.74#ibcon#read 5, iclass 34, count 0 2006.182.08:03:52.74#ibcon#about to read 6, iclass 34, count 0 2006.182.08:03:52.74#ibcon#read 6, iclass 34, count 0 2006.182.08:03:52.74#ibcon#end of sib2, iclass 34, count 0 2006.182.08:03:52.74#ibcon#*after write, iclass 34, count 0 2006.182.08:03:52.74#ibcon#*before return 0, iclass 34, count 0 2006.182.08:03:52.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:03:52.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:03:52.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:03:52.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:03:52.74$4f8m12a/ifd4f 2006.182.08:03:52.74$ifd4f/lo= 2006.182.08:03:52.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:03:52.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:03:52.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:03:52.74$ifd4f/patch= 2006.182.08:03:52.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:03:52.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:03:52.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:03:52.74$4f8m12a/"form=m,16.000,1:2 2006.182.08:03:52.74$4f8m12a/"tpicd 2006.182.08:03:52.75$4f8m12a/echo=off 2006.182.08:03:52.75$4f8m12a/xlog=off 2006.182.08:03:52.75:!2006.182.08:04:20 2006.182.08:04:05.13#trakl#Source acquired 2006.182.08:04:07.13#flagr#flagr/antenna,acquired 2006.182.08:04:20.01:preob 2006.182.08:04:21.14/onsource/TRACKING 2006.182.08:04:21.14:!2006.182.08:04:30 2006.182.08:04:30.00:data_valid=on 2006.182.08:04:30.00:midob 2006.182.08:04:30.14/onsource/TRACKING 2006.182.08:04:30.14/wx/27.87,1002.9,80 2006.182.08:04:30.21/cable/+6.4641E-03 2006.182.08:04:31.30/va/01,08,usb,yes,29,30 2006.182.08:04:31.30/va/02,07,usb,yes,29,30 2006.182.08:04:31.30/va/03,06,usb,yes,30,31 2006.182.08:04:31.30/va/04,07,usb,yes,30,32 2006.182.08:04:31.30/va/05,07,usb,yes,31,33 2006.182.08:04:31.30/va/06,06,usb,yes,30,30 2006.182.08:04:31.30/va/07,06,usb,yes,30,30 2006.182.08:04:31.30/va/08,07,usb,yes,29,28 2006.182.08:04:31.53/valo/01,532.99,yes,locked 2006.182.08:04:31.53/valo/02,572.99,yes,locked 2006.182.08:04:31.53/valo/03,672.99,yes,locked 2006.182.08:04:31.53/valo/04,832.99,yes,locked 2006.182.08:04:31.53/valo/05,652.99,yes,locked 2006.182.08:04:31.53/valo/06,772.99,yes,locked 2006.182.08:04:31.53/valo/07,832.99,yes,locked 2006.182.08:04:31.53/valo/08,852.99,yes,locked 2006.182.08:04:32.62/vb/01,04,usb,yes,29,28 2006.182.08:04:32.62/vb/02,04,usb,yes,31,32 2006.182.08:04:32.62/vb/03,04,usb,yes,27,31 2006.182.08:04:32.62/vb/04,04,usb,yes,28,28 2006.182.08:04:32.62/vb/05,04,usb,yes,27,30 2006.182.08:04:32.62/vb/06,04,usb,yes,27,30 2006.182.08:04:32.62/vb/07,04,usb,yes,29,29 2006.182.08:04:32.62/vb/08,04,usb,yes,27,30 2006.182.08:04:32.85/vblo/01,632.99,yes,locked 2006.182.08:04:32.85/vblo/02,640.99,yes,locked 2006.182.08:04:32.85/vblo/03,656.99,yes,locked 2006.182.08:04:32.85/vblo/04,712.99,yes,locked 2006.182.08:04:32.85/vblo/05,744.99,yes,locked 2006.182.08:04:32.85/vblo/06,752.99,yes,locked 2006.182.08:04:32.85/vblo/07,734.99,yes,locked 2006.182.08:04:32.85/vblo/08,744.99,yes,locked 2006.182.08:04:33.00/vabw/8 2006.182.08:04:33.15/vbbw/8 2006.182.08:04:33.24/xfe/off,on,15.2 2006.182.08:04:33.63/ifatt/23,28,28,28 2006.182.08:04:34.07/fmout-gps/S +3.41E-07 2006.182.08:04:34.15:!2006.182.08:05:30 2006.182.08:05:30.00:data_valid=off 2006.182.08:05:30.01:postob 2006.182.08:05:30.21/cable/+6.4651E-03 2006.182.08:05:30.22/wx/27.87,1002.9,80 2006.182.08:05:31.07/fmout-gps/S +3.42E-07 2006.182.08:05:31.08:scan_name=182-0806,k06182,60 2006.182.08:05:31.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.182.08:05:32.14#flagr#flagr/antenna,new-source 2006.182.08:05:32.15:checkk5 2006.182.08:05:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:05:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:05:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:05:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:05:34.00/chk_obsdata//k5ts1/T1820804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:05:34.37/chk_obsdata//k5ts2/T1820804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:05:34.75/chk_obsdata//k5ts3/T1820804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:05:35.12/chk_obsdata//k5ts4/T1820804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:05:35.81/k5log//k5ts1_log_newline 2006.182.08:05:36.50/k5log//k5ts2_log_newline 2006.182.08:05:37.19/k5log//k5ts3_log_newline 2006.182.08:05:37.88/k5log//k5ts4_log_newline 2006.182.08:05:37.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:05:37.90:4f8m12a=2 2006.182.08:05:37.90$4f8m12a/echo=on 2006.182.08:05:37.90$4f8m12a/pcalon 2006.182.08:05:37.90$pcalon/"no phase cal control is implemented here 2006.182.08:05:37.90$4f8m12a/"tpicd=stop 2006.182.08:05:37.90$4f8m12a/vc4f8 2006.182.08:05:37.90$vc4f8/valo=1,532.99 2006.182.08:05:37.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.08:05:37.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.08:05:37.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:37.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:37.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:37.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:37.91#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:05:37.91#ibcon#first serial, iclass 3, count 0 2006.182.08:05:37.91#ibcon#enter sib2, iclass 3, count 0 2006.182.08:05:37.91#ibcon#flushed, iclass 3, count 0 2006.182.08:05:37.91#ibcon#about to write, iclass 3, count 0 2006.182.08:05:37.91#ibcon#wrote, iclass 3, count 0 2006.182.08:05:37.91#ibcon#about to read 3, iclass 3, count 0 2006.182.08:05:37.95#ibcon#read 3, iclass 3, count 0 2006.182.08:05:37.95#ibcon#about to read 4, iclass 3, count 0 2006.182.08:05:37.95#ibcon#read 4, iclass 3, count 0 2006.182.08:05:37.95#ibcon#about to read 5, iclass 3, count 0 2006.182.08:05:37.95#ibcon#read 5, iclass 3, count 0 2006.182.08:05:37.95#ibcon#about to read 6, iclass 3, count 0 2006.182.08:05:37.95#ibcon#read 6, iclass 3, count 0 2006.182.08:05:37.95#ibcon#end of sib2, iclass 3, count 0 2006.182.08:05:37.95#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:05:37.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:05:37.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:05:37.95#ibcon#*before write, iclass 3, count 0 2006.182.08:05:37.95#ibcon#enter sib2, iclass 3, count 0 2006.182.08:05:37.95#ibcon#flushed, iclass 3, count 0 2006.182.08:05:37.95#ibcon#about to write, iclass 3, count 0 2006.182.08:05:37.95#ibcon#wrote, iclass 3, count 0 2006.182.08:05:37.95#ibcon#about to read 3, iclass 3, count 0 2006.182.08:05:37.99#ibcon#read 3, iclass 3, count 0 2006.182.08:05:37.99#ibcon#about to read 4, iclass 3, count 0 2006.182.08:05:37.99#ibcon#read 4, iclass 3, count 0 2006.182.08:05:37.99#ibcon#about to read 5, iclass 3, count 0 2006.182.08:05:37.99#ibcon#read 5, iclass 3, count 0 2006.182.08:05:37.99#ibcon#about to read 6, iclass 3, count 0 2006.182.08:05:37.99#ibcon#read 6, iclass 3, count 0 2006.182.08:05:37.99#ibcon#end of sib2, iclass 3, count 0 2006.182.08:05:37.99#ibcon#*after write, iclass 3, count 0 2006.182.08:05:37.99#ibcon#*before return 0, iclass 3, count 0 2006.182.08:05:37.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:37.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:37.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:05:37.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:05:37.99$vc4f8/va=1,8 2006.182.08:05:37.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.08:05:37.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.08:05:37.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:37.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:37.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:37.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:37.99#ibcon#enter wrdev, iclass 5, count 2 2006.182.08:05:37.99#ibcon#first serial, iclass 5, count 2 2006.182.08:05:37.99#ibcon#enter sib2, iclass 5, count 2 2006.182.08:05:37.99#ibcon#flushed, iclass 5, count 2 2006.182.08:05:37.99#ibcon#about to write, iclass 5, count 2 2006.182.08:05:37.99#ibcon#wrote, iclass 5, count 2 2006.182.08:05:37.99#ibcon#about to read 3, iclass 5, count 2 2006.182.08:05:38.01#ibcon#read 3, iclass 5, count 2 2006.182.08:05:38.01#ibcon#about to read 4, iclass 5, count 2 2006.182.08:05:38.01#ibcon#read 4, iclass 5, count 2 2006.182.08:05:38.01#ibcon#about to read 5, iclass 5, count 2 2006.182.08:05:38.01#ibcon#read 5, iclass 5, count 2 2006.182.08:05:38.01#ibcon#about to read 6, iclass 5, count 2 2006.182.08:05:38.01#ibcon#read 6, iclass 5, count 2 2006.182.08:05:38.01#ibcon#end of sib2, iclass 5, count 2 2006.182.08:05:38.01#ibcon#*mode == 0, iclass 5, count 2 2006.182.08:05:38.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.08:05:38.01#ibcon#[25=AT01-08\r\n] 2006.182.08:05:38.01#ibcon#*before write, iclass 5, count 2 2006.182.08:05:38.01#ibcon#enter sib2, iclass 5, count 2 2006.182.08:05:38.01#ibcon#flushed, iclass 5, count 2 2006.182.08:05:38.01#ibcon#about to write, iclass 5, count 2 2006.182.08:05:38.01#ibcon#wrote, iclass 5, count 2 2006.182.08:05:38.01#ibcon#about to read 3, iclass 5, count 2 2006.182.08:05:38.04#ibcon#read 3, iclass 5, count 2 2006.182.08:05:38.04#ibcon#about to read 4, iclass 5, count 2 2006.182.08:05:38.04#ibcon#read 4, iclass 5, count 2 2006.182.08:05:38.04#ibcon#about to read 5, iclass 5, count 2 2006.182.08:05:38.04#ibcon#read 5, iclass 5, count 2 2006.182.08:05:38.04#ibcon#about to read 6, iclass 5, count 2 2006.182.08:05:38.04#ibcon#read 6, iclass 5, count 2 2006.182.08:05:38.04#ibcon#end of sib2, iclass 5, count 2 2006.182.08:05:38.04#ibcon#*after write, iclass 5, count 2 2006.182.08:05:38.04#ibcon#*before return 0, iclass 5, count 2 2006.182.08:05:38.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:38.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:38.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.08:05:38.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:38.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:38.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:38.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:38.16#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:05:38.16#ibcon#first serial, iclass 5, count 0 2006.182.08:05:38.16#ibcon#enter sib2, iclass 5, count 0 2006.182.08:05:38.16#ibcon#flushed, iclass 5, count 0 2006.182.08:05:38.16#ibcon#about to write, iclass 5, count 0 2006.182.08:05:38.16#ibcon#wrote, iclass 5, count 0 2006.182.08:05:38.16#ibcon#about to read 3, iclass 5, count 0 2006.182.08:05:38.18#ibcon#read 3, iclass 5, count 0 2006.182.08:05:38.18#ibcon#about to read 4, iclass 5, count 0 2006.182.08:05:38.18#ibcon#read 4, iclass 5, count 0 2006.182.08:05:38.18#ibcon#about to read 5, iclass 5, count 0 2006.182.08:05:38.18#ibcon#read 5, iclass 5, count 0 2006.182.08:05:38.18#ibcon#about to read 6, iclass 5, count 0 2006.182.08:05:38.18#ibcon#read 6, iclass 5, count 0 2006.182.08:05:38.18#ibcon#end of sib2, iclass 5, count 0 2006.182.08:05:38.18#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:05:38.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:05:38.18#ibcon#[25=USB\r\n] 2006.182.08:05:38.18#ibcon#*before write, iclass 5, count 0 2006.182.08:05:38.18#ibcon#enter sib2, iclass 5, count 0 2006.182.08:05:38.18#ibcon#flushed, iclass 5, count 0 2006.182.08:05:38.18#ibcon#about to write, iclass 5, count 0 2006.182.08:05:38.18#ibcon#wrote, iclass 5, count 0 2006.182.08:05:38.18#ibcon#about to read 3, iclass 5, count 0 2006.182.08:05:38.21#ibcon#read 3, iclass 5, count 0 2006.182.08:05:38.21#ibcon#about to read 4, iclass 5, count 0 2006.182.08:05:38.21#ibcon#read 4, iclass 5, count 0 2006.182.08:05:38.21#ibcon#about to read 5, iclass 5, count 0 2006.182.08:05:38.21#ibcon#read 5, iclass 5, count 0 2006.182.08:05:38.21#ibcon#about to read 6, iclass 5, count 0 2006.182.08:05:38.21#ibcon#read 6, iclass 5, count 0 2006.182.08:05:38.21#ibcon#end of sib2, iclass 5, count 0 2006.182.08:05:38.21#ibcon#*after write, iclass 5, count 0 2006.182.08:05:38.21#ibcon#*before return 0, iclass 5, count 0 2006.182.08:05:38.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:38.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:38.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:05:38.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:05:38.21$vc4f8/valo=2,572.99 2006.182.08:05:38.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.08:05:38.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.08:05:38.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:38.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:38.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:38.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:38.21#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:05:38.21#ibcon#first serial, iclass 7, count 0 2006.182.08:05:38.21#ibcon#enter sib2, iclass 7, count 0 2006.182.08:05:38.21#ibcon#flushed, iclass 7, count 0 2006.182.08:05:38.21#ibcon#about to write, iclass 7, count 0 2006.182.08:05:38.21#ibcon#wrote, iclass 7, count 0 2006.182.08:05:38.21#ibcon#about to read 3, iclass 7, count 0 2006.182.08:05:38.23#ibcon#read 3, iclass 7, count 0 2006.182.08:05:38.23#ibcon#about to read 4, iclass 7, count 0 2006.182.08:05:38.23#ibcon#read 4, iclass 7, count 0 2006.182.08:05:38.23#ibcon#about to read 5, iclass 7, count 0 2006.182.08:05:38.23#ibcon#read 5, iclass 7, count 0 2006.182.08:05:38.23#ibcon#about to read 6, iclass 7, count 0 2006.182.08:05:38.23#ibcon#read 6, iclass 7, count 0 2006.182.08:05:38.23#ibcon#end of sib2, iclass 7, count 0 2006.182.08:05:38.23#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:05:38.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:05:38.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:05:38.23#ibcon#*before write, iclass 7, count 0 2006.182.08:05:38.23#ibcon#enter sib2, iclass 7, count 0 2006.182.08:05:38.23#ibcon#flushed, iclass 7, count 0 2006.182.08:05:38.23#ibcon#about to write, iclass 7, count 0 2006.182.08:05:38.23#ibcon#wrote, iclass 7, count 0 2006.182.08:05:38.23#ibcon#about to read 3, iclass 7, count 0 2006.182.08:05:38.27#ibcon#read 3, iclass 7, count 0 2006.182.08:05:38.27#ibcon#about to read 4, iclass 7, count 0 2006.182.08:05:38.27#ibcon#read 4, iclass 7, count 0 2006.182.08:05:38.27#ibcon#about to read 5, iclass 7, count 0 2006.182.08:05:38.27#ibcon#read 5, iclass 7, count 0 2006.182.08:05:38.27#ibcon#about to read 6, iclass 7, count 0 2006.182.08:05:38.27#ibcon#read 6, iclass 7, count 0 2006.182.08:05:38.27#ibcon#end of sib2, iclass 7, count 0 2006.182.08:05:38.27#ibcon#*after write, iclass 7, count 0 2006.182.08:05:38.27#ibcon#*before return 0, iclass 7, count 0 2006.182.08:05:38.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:38.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:38.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:05:38.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:05:38.27$vc4f8/va=2,7 2006.182.08:05:38.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.08:05:38.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.08:05:38.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:38.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:38.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:38.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:38.34#ibcon#enter wrdev, iclass 11, count 2 2006.182.08:05:38.34#ibcon#first serial, iclass 11, count 2 2006.182.08:05:38.34#ibcon#enter sib2, iclass 11, count 2 2006.182.08:05:38.34#ibcon#flushed, iclass 11, count 2 2006.182.08:05:38.34#ibcon#about to write, iclass 11, count 2 2006.182.08:05:38.34#ibcon#wrote, iclass 11, count 2 2006.182.08:05:38.34#ibcon#about to read 3, iclass 11, count 2 2006.182.08:05:38.36#ibcon#read 3, iclass 11, count 2 2006.182.08:05:38.36#ibcon#about to read 4, iclass 11, count 2 2006.182.08:05:38.36#ibcon#read 4, iclass 11, count 2 2006.182.08:05:38.36#ibcon#about to read 5, iclass 11, count 2 2006.182.08:05:38.36#ibcon#read 5, iclass 11, count 2 2006.182.08:05:38.36#ibcon#about to read 6, iclass 11, count 2 2006.182.08:05:38.36#ibcon#read 6, iclass 11, count 2 2006.182.08:05:38.36#ibcon#end of sib2, iclass 11, count 2 2006.182.08:05:38.36#ibcon#*mode == 0, iclass 11, count 2 2006.182.08:05:38.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.08:05:38.36#ibcon#[25=AT02-07\r\n] 2006.182.08:05:38.36#ibcon#*before write, iclass 11, count 2 2006.182.08:05:38.36#ibcon#enter sib2, iclass 11, count 2 2006.182.08:05:38.36#ibcon#flushed, iclass 11, count 2 2006.182.08:05:38.36#ibcon#about to write, iclass 11, count 2 2006.182.08:05:38.36#ibcon#wrote, iclass 11, count 2 2006.182.08:05:38.36#ibcon#about to read 3, iclass 11, count 2 2006.182.08:05:38.38#ibcon#read 3, iclass 11, count 2 2006.182.08:05:38.38#ibcon#about to read 4, iclass 11, count 2 2006.182.08:05:38.38#ibcon#read 4, iclass 11, count 2 2006.182.08:05:38.38#ibcon#about to read 5, iclass 11, count 2 2006.182.08:05:38.38#ibcon#read 5, iclass 11, count 2 2006.182.08:05:38.38#ibcon#about to read 6, iclass 11, count 2 2006.182.08:05:38.38#ibcon#read 6, iclass 11, count 2 2006.182.08:05:38.38#ibcon#end of sib2, iclass 11, count 2 2006.182.08:05:38.38#ibcon#*after write, iclass 11, count 2 2006.182.08:05:38.38#ibcon#*before return 0, iclass 11, count 2 2006.182.08:05:38.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:38.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:38.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.08:05:38.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:38.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:38.48#abcon#<5=/06 0.8 2.6 27.87 801002.9\r\n> 2006.182.08:05:38.50#abcon#{5=INTERFACE CLEAR} 2006.182.08:05:38.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:38.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:38.50#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:05:38.50#ibcon#first serial, iclass 11, count 0 2006.182.08:05:38.50#ibcon#enter sib2, iclass 11, count 0 2006.182.08:05:38.50#ibcon#flushed, iclass 11, count 0 2006.182.08:05:38.50#ibcon#about to write, iclass 11, count 0 2006.182.08:05:38.50#ibcon#wrote, iclass 11, count 0 2006.182.08:05:38.50#ibcon#about to read 3, iclass 11, count 0 2006.182.08:05:38.52#ibcon#read 3, iclass 11, count 0 2006.182.08:05:38.52#ibcon#about to read 4, iclass 11, count 0 2006.182.08:05:38.52#ibcon#read 4, iclass 11, count 0 2006.182.08:05:38.52#ibcon#about to read 5, iclass 11, count 0 2006.182.08:05:38.52#ibcon#read 5, iclass 11, count 0 2006.182.08:05:38.52#ibcon#about to read 6, iclass 11, count 0 2006.182.08:05:38.52#ibcon#read 6, iclass 11, count 0 2006.182.08:05:38.52#ibcon#end of sib2, iclass 11, count 0 2006.182.08:05:38.52#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:05:38.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:05:38.52#ibcon#[25=USB\r\n] 2006.182.08:05:38.52#ibcon#*before write, iclass 11, count 0 2006.182.08:05:38.52#ibcon#enter sib2, iclass 11, count 0 2006.182.08:05:38.52#ibcon#flushed, iclass 11, count 0 2006.182.08:05:38.52#ibcon#about to write, iclass 11, count 0 2006.182.08:05:38.52#ibcon#wrote, iclass 11, count 0 2006.182.08:05:38.52#ibcon#about to read 3, iclass 11, count 0 2006.182.08:05:38.55#ibcon#read 3, iclass 11, count 0 2006.182.08:05:38.55#ibcon#about to read 4, iclass 11, count 0 2006.182.08:05:38.55#ibcon#read 4, iclass 11, count 0 2006.182.08:05:38.55#ibcon#about to read 5, iclass 11, count 0 2006.182.08:05:38.55#ibcon#read 5, iclass 11, count 0 2006.182.08:05:38.55#ibcon#about to read 6, iclass 11, count 0 2006.182.08:05:38.55#ibcon#read 6, iclass 11, count 0 2006.182.08:05:38.55#ibcon#end of sib2, iclass 11, count 0 2006.182.08:05:38.55#ibcon#*after write, iclass 11, count 0 2006.182.08:05:38.55#ibcon#*before return 0, iclass 11, count 0 2006.182.08:05:38.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:38.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:38.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:05:38.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:05:38.55$vc4f8/valo=3,672.99 2006.182.08:05:38.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.08:05:38.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.08:05:38.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:38.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:38.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:38.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:38.55#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:05:38.55#ibcon#first serial, iclass 17, count 0 2006.182.08:05:38.55#ibcon#enter sib2, iclass 17, count 0 2006.182.08:05:38.55#ibcon#flushed, iclass 17, count 0 2006.182.08:05:38.55#ibcon#about to write, iclass 17, count 0 2006.182.08:05:38.55#ibcon#wrote, iclass 17, count 0 2006.182.08:05:38.55#ibcon#about to read 3, iclass 17, count 0 2006.182.08:05:38.57#abcon#[5=S1D000X0/0*\r\n] 2006.182.08:05:38.57#ibcon#read 3, iclass 17, count 0 2006.182.08:05:38.57#ibcon#about to read 4, iclass 17, count 0 2006.182.08:05:38.57#ibcon#read 4, iclass 17, count 0 2006.182.08:05:38.57#ibcon#about to read 5, iclass 17, count 0 2006.182.08:05:38.57#ibcon#read 5, iclass 17, count 0 2006.182.08:05:38.57#ibcon#about to read 6, iclass 17, count 0 2006.182.08:05:38.57#ibcon#read 6, iclass 17, count 0 2006.182.08:05:38.57#ibcon#end of sib2, iclass 17, count 0 2006.182.08:05:38.57#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:05:38.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:05:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:05:38.57#ibcon#*before write, iclass 17, count 0 2006.182.08:05:38.57#ibcon#enter sib2, iclass 17, count 0 2006.182.08:05:38.57#ibcon#flushed, iclass 17, count 0 2006.182.08:05:38.57#ibcon#about to write, iclass 17, count 0 2006.182.08:05:38.57#ibcon#wrote, iclass 17, count 0 2006.182.08:05:38.57#ibcon#about to read 3, iclass 17, count 0 2006.182.08:05:38.61#ibcon#read 3, iclass 17, count 0 2006.182.08:05:38.61#ibcon#about to read 4, iclass 17, count 0 2006.182.08:05:38.61#ibcon#read 4, iclass 17, count 0 2006.182.08:05:38.61#ibcon#about to read 5, iclass 17, count 0 2006.182.08:05:38.61#ibcon#read 5, iclass 17, count 0 2006.182.08:05:38.61#ibcon#about to read 6, iclass 17, count 0 2006.182.08:05:38.61#ibcon#read 6, iclass 17, count 0 2006.182.08:05:38.61#ibcon#end of sib2, iclass 17, count 0 2006.182.08:05:38.61#ibcon#*after write, iclass 17, count 0 2006.182.08:05:38.61#ibcon#*before return 0, iclass 17, count 0 2006.182.08:05:38.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:38.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:38.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:05:38.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:05:38.61$vc4f8/va=3,6 2006.182.08:05:38.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.182.08:05:38.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.182.08:05:38.61#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:38.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:38.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:38.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:38.67#ibcon#enter wrdev, iclass 19, count 2 2006.182.08:05:38.67#ibcon#first serial, iclass 19, count 2 2006.182.08:05:38.67#ibcon#enter sib2, iclass 19, count 2 2006.182.08:05:38.67#ibcon#flushed, iclass 19, count 2 2006.182.08:05:38.67#ibcon#about to write, iclass 19, count 2 2006.182.08:05:38.67#ibcon#wrote, iclass 19, count 2 2006.182.08:05:38.67#ibcon#about to read 3, iclass 19, count 2 2006.182.08:05:38.69#ibcon#read 3, iclass 19, count 2 2006.182.08:05:38.69#ibcon#about to read 4, iclass 19, count 2 2006.182.08:05:38.69#ibcon#read 4, iclass 19, count 2 2006.182.08:05:38.69#ibcon#about to read 5, iclass 19, count 2 2006.182.08:05:38.69#ibcon#read 5, iclass 19, count 2 2006.182.08:05:38.69#ibcon#about to read 6, iclass 19, count 2 2006.182.08:05:38.69#ibcon#read 6, iclass 19, count 2 2006.182.08:05:38.69#ibcon#end of sib2, iclass 19, count 2 2006.182.08:05:38.69#ibcon#*mode == 0, iclass 19, count 2 2006.182.08:05:38.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.182.08:05:38.69#ibcon#[25=AT03-06\r\n] 2006.182.08:05:38.69#ibcon#*before write, iclass 19, count 2 2006.182.08:05:38.69#ibcon#enter sib2, iclass 19, count 2 2006.182.08:05:38.69#ibcon#flushed, iclass 19, count 2 2006.182.08:05:38.69#ibcon#about to write, iclass 19, count 2 2006.182.08:05:38.69#ibcon#wrote, iclass 19, count 2 2006.182.08:05:38.69#ibcon#about to read 3, iclass 19, count 2 2006.182.08:05:38.72#ibcon#read 3, iclass 19, count 2 2006.182.08:05:38.72#ibcon#about to read 4, iclass 19, count 2 2006.182.08:05:38.72#ibcon#read 4, iclass 19, count 2 2006.182.08:05:38.72#ibcon#about to read 5, iclass 19, count 2 2006.182.08:05:38.72#ibcon#read 5, iclass 19, count 2 2006.182.08:05:38.72#ibcon#about to read 6, iclass 19, count 2 2006.182.08:05:38.72#ibcon#read 6, iclass 19, count 2 2006.182.08:05:38.72#ibcon#end of sib2, iclass 19, count 2 2006.182.08:05:38.72#ibcon#*after write, iclass 19, count 2 2006.182.08:05:38.72#ibcon#*before return 0, iclass 19, count 2 2006.182.08:05:38.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:38.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:38.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.182.08:05:38.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:38.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:38.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:38.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:38.84#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:05:38.84#ibcon#first serial, iclass 19, count 0 2006.182.08:05:38.84#ibcon#enter sib2, iclass 19, count 0 2006.182.08:05:38.84#ibcon#flushed, iclass 19, count 0 2006.182.08:05:38.84#ibcon#about to write, iclass 19, count 0 2006.182.08:05:38.84#ibcon#wrote, iclass 19, count 0 2006.182.08:05:38.84#ibcon#about to read 3, iclass 19, count 0 2006.182.08:05:38.86#ibcon#read 3, iclass 19, count 0 2006.182.08:05:38.86#ibcon#about to read 4, iclass 19, count 0 2006.182.08:05:38.86#ibcon#read 4, iclass 19, count 0 2006.182.08:05:38.86#ibcon#about to read 5, iclass 19, count 0 2006.182.08:05:38.86#ibcon#read 5, iclass 19, count 0 2006.182.08:05:38.86#ibcon#about to read 6, iclass 19, count 0 2006.182.08:05:38.86#ibcon#read 6, iclass 19, count 0 2006.182.08:05:38.86#ibcon#end of sib2, iclass 19, count 0 2006.182.08:05:38.86#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:05:38.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:05:38.86#ibcon#[25=USB\r\n] 2006.182.08:05:38.86#ibcon#*before write, iclass 19, count 0 2006.182.08:05:38.86#ibcon#enter sib2, iclass 19, count 0 2006.182.08:05:38.86#ibcon#flushed, iclass 19, count 0 2006.182.08:05:38.86#ibcon#about to write, iclass 19, count 0 2006.182.08:05:38.86#ibcon#wrote, iclass 19, count 0 2006.182.08:05:38.86#ibcon#about to read 3, iclass 19, count 0 2006.182.08:05:38.89#ibcon#read 3, iclass 19, count 0 2006.182.08:05:38.89#ibcon#about to read 4, iclass 19, count 0 2006.182.08:05:38.89#ibcon#read 4, iclass 19, count 0 2006.182.08:05:38.89#ibcon#about to read 5, iclass 19, count 0 2006.182.08:05:38.89#ibcon#read 5, iclass 19, count 0 2006.182.08:05:38.89#ibcon#about to read 6, iclass 19, count 0 2006.182.08:05:38.89#ibcon#read 6, iclass 19, count 0 2006.182.08:05:38.89#ibcon#end of sib2, iclass 19, count 0 2006.182.08:05:38.89#ibcon#*after write, iclass 19, count 0 2006.182.08:05:38.89#ibcon#*before return 0, iclass 19, count 0 2006.182.08:05:38.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:38.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:38.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:05:38.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:05:38.89$vc4f8/valo=4,832.99 2006.182.08:05:38.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.08:05:38.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.08:05:38.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:38.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:38.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:38.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:38.89#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:05:38.89#ibcon#first serial, iclass 21, count 0 2006.182.08:05:38.89#ibcon#enter sib2, iclass 21, count 0 2006.182.08:05:38.89#ibcon#flushed, iclass 21, count 0 2006.182.08:05:38.89#ibcon#about to write, iclass 21, count 0 2006.182.08:05:38.89#ibcon#wrote, iclass 21, count 0 2006.182.08:05:38.89#ibcon#about to read 3, iclass 21, count 0 2006.182.08:05:38.91#ibcon#read 3, iclass 21, count 0 2006.182.08:05:38.91#ibcon#about to read 4, iclass 21, count 0 2006.182.08:05:38.91#ibcon#read 4, iclass 21, count 0 2006.182.08:05:38.91#ibcon#about to read 5, iclass 21, count 0 2006.182.08:05:38.91#ibcon#read 5, iclass 21, count 0 2006.182.08:05:38.91#ibcon#about to read 6, iclass 21, count 0 2006.182.08:05:38.91#ibcon#read 6, iclass 21, count 0 2006.182.08:05:38.91#ibcon#end of sib2, iclass 21, count 0 2006.182.08:05:38.91#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:05:38.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:05:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:05:38.91#ibcon#*before write, iclass 21, count 0 2006.182.08:05:38.91#ibcon#enter sib2, iclass 21, count 0 2006.182.08:05:38.91#ibcon#flushed, iclass 21, count 0 2006.182.08:05:38.91#ibcon#about to write, iclass 21, count 0 2006.182.08:05:38.91#ibcon#wrote, iclass 21, count 0 2006.182.08:05:38.91#ibcon#about to read 3, iclass 21, count 0 2006.182.08:05:38.95#ibcon#read 3, iclass 21, count 0 2006.182.08:05:38.95#ibcon#about to read 4, iclass 21, count 0 2006.182.08:05:38.95#ibcon#read 4, iclass 21, count 0 2006.182.08:05:38.95#ibcon#about to read 5, iclass 21, count 0 2006.182.08:05:38.95#ibcon#read 5, iclass 21, count 0 2006.182.08:05:38.95#ibcon#about to read 6, iclass 21, count 0 2006.182.08:05:38.95#ibcon#read 6, iclass 21, count 0 2006.182.08:05:38.95#ibcon#end of sib2, iclass 21, count 0 2006.182.08:05:38.95#ibcon#*after write, iclass 21, count 0 2006.182.08:05:38.95#ibcon#*before return 0, iclass 21, count 0 2006.182.08:05:38.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:38.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:38.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:05:38.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:05:38.95$vc4f8/va=4,7 2006.182.08:05:38.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.182.08:05:38.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.182.08:05:38.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:38.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:39.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:39.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:39.01#ibcon#enter wrdev, iclass 23, count 2 2006.182.08:05:39.01#ibcon#first serial, iclass 23, count 2 2006.182.08:05:39.01#ibcon#enter sib2, iclass 23, count 2 2006.182.08:05:39.01#ibcon#flushed, iclass 23, count 2 2006.182.08:05:39.01#ibcon#about to write, iclass 23, count 2 2006.182.08:05:39.01#ibcon#wrote, iclass 23, count 2 2006.182.08:05:39.01#ibcon#about to read 3, iclass 23, count 2 2006.182.08:05:39.03#ibcon#read 3, iclass 23, count 2 2006.182.08:05:39.03#ibcon#about to read 4, iclass 23, count 2 2006.182.08:05:39.03#ibcon#read 4, iclass 23, count 2 2006.182.08:05:39.03#ibcon#about to read 5, iclass 23, count 2 2006.182.08:05:39.03#ibcon#read 5, iclass 23, count 2 2006.182.08:05:39.03#ibcon#about to read 6, iclass 23, count 2 2006.182.08:05:39.03#ibcon#read 6, iclass 23, count 2 2006.182.08:05:39.03#ibcon#end of sib2, iclass 23, count 2 2006.182.08:05:39.03#ibcon#*mode == 0, iclass 23, count 2 2006.182.08:05:39.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.182.08:05:39.03#ibcon#[25=AT04-07\r\n] 2006.182.08:05:39.03#ibcon#*before write, iclass 23, count 2 2006.182.08:05:39.03#ibcon#enter sib2, iclass 23, count 2 2006.182.08:05:39.03#ibcon#flushed, iclass 23, count 2 2006.182.08:05:39.03#ibcon#about to write, iclass 23, count 2 2006.182.08:05:39.03#ibcon#wrote, iclass 23, count 2 2006.182.08:05:39.03#ibcon#about to read 3, iclass 23, count 2 2006.182.08:05:39.06#ibcon#read 3, iclass 23, count 2 2006.182.08:05:39.06#ibcon#about to read 4, iclass 23, count 2 2006.182.08:05:39.06#ibcon#read 4, iclass 23, count 2 2006.182.08:05:39.06#ibcon#about to read 5, iclass 23, count 2 2006.182.08:05:39.06#ibcon#read 5, iclass 23, count 2 2006.182.08:05:39.06#ibcon#about to read 6, iclass 23, count 2 2006.182.08:05:39.06#ibcon#read 6, iclass 23, count 2 2006.182.08:05:39.06#ibcon#end of sib2, iclass 23, count 2 2006.182.08:05:39.06#ibcon#*after write, iclass 23, count 2 2006.182.08:05:39.06#ibcon#*before return 0, iclass 23, count 2 2006.182.08:05:39.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:39.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:39.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.182.08:05:39.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:39.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:39.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:39.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:39.18#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:05:39.18#ibcon#first serial, iclass 23, count 0 2006.182.08:05:39.18#ibcon#enter sib2, iclass 23, count 0 2006.182.08:05:39.18#ibcon#flushed, iclass 23, count 0 2006.182.08:05:39.18#ibcon#about to write, iclass 23, count 0 2006.182.08:05:39.18#ibcon#wrote, iclass 23, count 0 2006.182.08:05:39.18#ibcon#about to read 3, iclass 23, count 0 2006.182.08:05:39.20#ibcon#read 3, iclass 23, count 0 2006.182.08:05:39.20#ibcon#about to read 4, iclass 23, count 0 2006.182.08:05:39.20#ibcon#read 4, iclass 23, count 0 2006.182.08:05:39.20#ibcon#about to read 5, iclass 23, count 0 2006.182.08:05:39.20#ibcon#read 5, iclass 23, count 0 2006.182.08:05:39.20#ibcon#about to read 6, iclass 23, count 0 2006.182.08:05:39.20#ibcon#read 6, iclass 23, count 0 2006.182.08:05:39.20#ibcon#end of sib2, iclass 23, count 0 2006.182.08:05:39.20#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:05:39.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:05:39.20#ibcon#[25=USB\r\n] 2006.182.08:05:39.20#ibcon#*before write, iclass 23, count 0 2006.182.08:05:39.20#ibcon#enter sib2, iclass 23, count 0 2006.182.08:05:39.20#ibcon#flushed, iclass 23, count 0 2006.182.08:05:39.20#ibcon#about to write, iclass 23, count 0 2006.182.08:05:39.20#ibcon#wrote, iclass 23, count 0 2006.182.08:05:39.20#ibcon#about to read 3, iclass 23, count 0 2006.182.08:05:39.23#ibcon#read 3, iclass 23, count 0 2006.182.08:05:39.23#ibcon#about to read 4, iclass 23, count 0 2006.182.08:05:39.23#ibcon#read 4, iclass 23, count 0 2006.182.08:05:39.23#ibcon#about to read 5, iclass 23, count 0 2006.182.08:05:39.23#ibcon#read 5, iclass 23, count 0 2006.182.08:05:39.23#ibcon#about to read 6, iclass 23, count 0 2006.182.08:05:39.23#ibcon#read 6, iclass 23, count 0 2006.182.08:05:39.23#ibcon#end of sib2, iclass 23, count 0 2006.182.08:05:39.23#ibcon#*after write, iclass 23, count 0 2006.182.08:05:39.23#ibcon#*before return 0, iclass 23, count 0 2006.182.08:05:39.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:39.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:39.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:05:39.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:05:39.23$vc4f8/valo=5,652.99 2006.182.08:05:39.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.08:05:39.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.08:05:39.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:39.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:39.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:39.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:39.23#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:05:39.23#ibcon#first serial, iclass 25, count 0 2006.182.08:05:39.23#ibcon#enter sib2, iclass 25, count 0 2006.182.08:05:39.23#ibcon#flushed, iclass 25, count 0 2006.182.08:05:39.23#ibcon#about to write, iclass 25, count 0 2006.182.08:05:39.23#ibcon#wrote, iclass 25, count 0 2006.182.08:05:39.23#ibcon#about to read 3, iclass 25, count 0 2006.182.08:05:39.25#ibcon#read 3, iclass 25, count 0 2006.182.08:05:39.25#ibcon#about to read 4, iclass 25, count 0 2006.182.08:05:39.25#ibcon#read 4, iclass 25, count 0 2006.182.08:05:39.25#ibcon#about to read 5, iclass 25, count 0 2006.182.08:05:39.25#ibcon#read 5, iclass 25, count 0 2006.182.08:05:39.25#ibcon#about to read 6, iclass 25, count 0 2006.182.08:05:39.25#ibcon#read 6, iclass 25, count 0 2006.182.08:05:39.25#ibcon#end of sib2, iclass 25, count 0 2006.182.08:05:39.25#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:05:39.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:05:39.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:05:39.25#ibcon#*before write, iclass 25, count 0 2006.182.08:05:39.25#ibcon#enter sib2, iclass 25, count 0 2006.182.08:05:39.25#ibcon#flushed, iclass 25, count 0 2006.182.08:05:39.25#ibcon#about to write, iclass 25, count 0 2006.182.08:05:39.25#ibcon#wrote, iclass 25, count 0 2006.182.08:05:39.25#ibcon#about to read 3, iclass 25, count 0 2006.182.08:05:39.29#ibcon#read 3, iclass 25, count 0 2006.182.08:05:39.29#ibcon#about to read 4, iclass 25, count 0 2006.182.08:05:39.29#ibcon#read 4, iclass 25, count 0 2006.182.08:05:39.29#ibcon#about to read 5, iclass 25, count 0 2006.182.08:05:39.29#ibcon#read 5, iclass 25, count 0 2006.182.08:05:39.29#ibcon#about to read 6, iclass 25, count 0 2006.182.08:05:39.29#ibcon#read 6, iclass 25, count 0 2006.182.08:05:39.29#ibcon#end of sib2, iclass 25, count 0 2006.182.08:05:39.29#ibcon#*after write, iclass 25, count 0 2006.182.08:05:39.29#ibcon#*before return 0, iclass 25, count 0 2006.182.08:05:39.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:39.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:39.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:05:39.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:05:39.29$vc4f8/va=5,7 2006.182.08:05:39.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.182.08:05:39.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.182.08:05:39.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:39.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:39.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:39.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:39.35#ibcon#enter wrdev, iclass 27, count 2 2006.182.08:05:39.35#ibcon#first serial, iclass 27, count 2 2006.182.08:05:39.35#ibcon#enter sib2, iclass 27, count 2 2006.182.08:05:39.35#ibcon#flushed, iclass 27, count 2 2006.182.08:05:39.35#ibcon#about to write, iclass 27, count 2 2006.182.08:05:39.35#ibcon#wrote, iclass 27, count 2 2006.182.08:05:39.35#ibcon#about to read 3, iclass 27, count 2 2006.182.08:05:39.37#ibcon#read 3, iclass 27, count 2 2006.182.08:05:39.37#ibcon#about to read 4, iclass 27, count 2 2006.182.08:05:39.37#ibcon#read 4, iclass 27, count 2 2006.182.08:05:39.37#ibcon#about to read 5, iclass 27, count 2 2006.182.08:05:39.37#ibcon#read 5, iclass 27, count 2 2006.182.08:05:39.37#ibcon#about to read 6, iclass 27, count 2 2006.182.08:05:39.37#ibcon#read 6, iclass 27, count 2 2006.182.08:05:39.37#ibcon#end of sib2, iclass 27, count 2 2006.182.08:05:39.37#ibcon#*mode == 0, iclass 27, count 2 2006.182.08:05:39.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.182.08:05:39.37#ibcon#[25=AT05-07\r\n] 2006.182.08:05:39.37#ibcon#*before write, iclass 27, count 2 2006.182.08:05:39.37#ibcon#enter sib2, iclass 27, count 2 2006.182.08:05:39.37#ibcon#flushed, iclass 27, count 2 2006.182.08:05:39.37#ibcon#about to write, iclass 27, count 2 2006.182.08:05:39.37#ibcon#wrote, iclass 27, count 2 2006.182.08:05:39.37#ibcon#about to read 3, iclass 27, count 2 2006.182.08:05:39.40#ibcon#read 3, iclass 27, count 2 2006.182.08:05:39.40#ibcon#about to read 4, iclass 27, count 2 2006.182.08:05:39.40#ibcon#read 4, iclass 27, count 2 2006.182.08:05:39.40#ibcon#about to read 5, iclass 27, count 2 2006.182.08:05:39.40#ibcon#read 5, iclass 27, count 2 2006.182.08:05:39.40#ibcon#about to read 6, iclass 27, count 2 2006.182.08:05:39.40#ibcon#read 6, iclass 27, count 2 2006.182.08:05:39.40#ibcon#end of sib2, iclass 27, count 2 2006.182.08:05:39.40#ibcon#*after write, iclass 27, count 2 2006.182.08:05:39.40#ibcon#*before return 0, iclass 27, count 2 2006.182.08:05:39.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:39.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:39.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.182.08:05:39.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:39.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:39.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:39.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:39.52#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:05:39.52#ibcon#first serial, iclass 27, count 0 2006.182.08:05:39.52#ibcon#enter sib2, iclass 27, count 0 2006.182.08:05:39.52#ibcon#flushed, iclass 27, count 0 2006.182.08:05:39.52#ibcon#about to write, iclass 27, count 0 2006.182.08:05:39.52#ibcon#wrote, iclass 27, count 0 2006.182.08:05:39.52#ibcon#about to read 3, iclass 27, count 0 2006.182.08:05:39.54#ibcon#read 3, iclass 27, count 0 2006.182.08:05:39.54#ibcon#about to read 4, iclass 27, count 0 2006.182.08:05:39.54#ibcon#read 4, iclass 27, count 0 2006.182.08:05:39.54#ibcon#about to read 5, iclass 27, count 0 2006.182.08:05:39.54#ibcon#read 5, iclass 27, count 0 2006.182.08:05:39.54#ibcon#about to read 6, iclass 27, count 0 2006.182.08:05:39.54#ibcon#read 6, iclass 27, count 0 2006.182.08:05:39.54#ibcon#end of sib2, iclass 27, count 0 2006.182.08:05:39.54#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:05:39.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:05:39.54#ibcon#[25=USB\r\n] 2006.182.08:05:39.54#ibcon#*before write, iclass 27, count 0 2006.182.08:05:39.54#ibcon#enter sib2, iclass 27, count 0 2006.182.08:05:39.54#ibcon#flushed, iclass 27, count 0 2006.182.08:05:39.54#ibcon#about to write, iclass 27, count 0 2006.182.08:05:39.54#ibcon#wrote, iclass 27, count 0 2006.182.08:05:39.54#ibcon#about to read 3, iclass 27, count 0 2006.182.08:05:39.57#ibcon#read 3, iclass 27, count 0 2006.182.08:05:39.57#ibcon#about to read 4, iclass 27, count 0 2006.182.08:05:39.57#ibcon#read 4, iclass 27, count 0 2006.182.08:05:39.57#ibcon#about to read 5, iclass 27, count 0 2006.182.08:05:39.57#ibcon#read 5, iclass 27, count 0 2006.182.08:05:39.57#ibcon#about to read 6, iclass 27, count 0 2006.182.08:05:39.57#ibcon#read 6, iclass 27, count 0 2006.182.08:05:39.57#ibcon#end of sib2, iclass 27, count 0 2006.182.08:05:39.57#ibcon#*after write, iclass 27, count 0 2006.182.08:05:39.57#ibcon#*before return 0, iclass 27, count 0 2006.182.08:05:39.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:39.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:39.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:05:39.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:05:39.57$vc4f8/valo=6,772.99 2006.182.08:05:39.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.08:05:39.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.08:05:39.57#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:39.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:39.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:39.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:39.57#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:05:39.57#ibcon#first serial, iclass 29, count 0 2006.182.08:05:39.57#ibcon#enter sib2, iclass 29, count 0 2006.182.08:05:39.57#ibcon#flushed, iclass 29, count 0 2006.182.08:05:39.57#ibcon#about to write, iclass 29, count 0 2006.182.08:05:39.57#ibcon#wrote, iclass 29, count 0 2006.182.08:05:39.57#ibcon#about to read 3, iclass 29, count 0 2006.182.08:05:39.59#ibcon#read 3, iclass 29, count 0 2006.182.08:05:39.59#ibcon#about to read 4, iclass 29, count 0 2006.182.08:05:39.59#ibcon#read 4, iclass 29, count 0 2006.182.08:05:39.59#ibcon#about to read 5, iclass 29, count 0 2006.182.08:05:39.59#ibcon#read 5, iclass 29, count 0 2006.182.08:05:39.59#ibcon#about to read 6, iclass 29, count 0 2006.182.08:05:39.59#ibcon#read 6, iclass 29, count 0 2006.182.08:05:39.59#ibcon#end of sib2, iclass 29, count 0 2006.182.08:05:39.59#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:05:39.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:05:39.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:05:39.59#ibcon#*before write, iclass 29, count 0 2006.182.08:05:39.59#ibcon#enter sib2, iclass 29, count 0 2006.182.08:05:39.59#ibcon#flushed, iclass 29, count 0 2006.182.08:05:39.59#ibcon#about to write, iclass 29, count 0 2006.182.08:05:39.59#ibcon#wrote, iclass 29, count 0 2006.182.08:05:39.59#ibcon#about to read 3, iclass 29, count 0 2006.182.08:05:39.63#ibcon#read 3, iclass 29, count 0 2006.182.08:05:39.63#ibcon#about to read 4, iclass 29, count 0 2006.182.08:05:39.63#ibcon#read 4, iclass 29, count 0 2006.182.08:05:39.63#ibcon#about to read 5, iclass 29, count 0 2006.182.08:05:39.63#ibcon#read 5, iclass 29, count 0 2006.182.08:05:39.63#ibcon#about to read 6, iclass 29, count 0 2006.182.08:05:39.63#ibcon#read 6, iclass 29, count 0 2006.182.08:05:39.63#ibcon#end of sib2, iclass 29, count 0 2006.182.08:05:39.63#ibcon#*after write, iclass 29, count 0 2006.182.08:05:39.63#ibcon#*before return 0, iclass 29, count 0 2006.182.08:05:39.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:39.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:39.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:05:39.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:05:39.63$vc4f8/va=6,6 2006.182.08:05:39.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.182.08:05:39.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.182.08:05:39.63#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:39.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:05:39.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:05:39.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:05:39.69#ibcon#enter wrdev, iclass 31, count 2 2006.182.08:05:39.69#ibcon#first serial, iclass 31, count 2 2006.182.08:05:39.69#ibcon#enter sib2, iclass 31, count 2 2006.182.08:05:39.69#ibcon#flushed, iclass 31, count 2 2006.182.08:05:39.69#ibcon#about to write, iclass 31, count 2 2006.182.08:05:39.69#ibcon#wrote, iclass 31, count 2 2006.182.08:05:39.69#ibcon#about to read 3, iclass 31, count 2 2006.182.08:05:39.71#ibcon#read 3, iclass 31, count 2 2006.182.08:05:39.71#ibcon#about to read 4, iclass 31, count 2 2006.182.08:05:39.71#ibcon#read 4, iclass 31, count 2 2006.182.08:05:39.71#ibcon#about to read 5, iclass 31, count 2 2006.182.08:05:39.71#ibcon#read 5, iclass 31, count 2 2006.182.08:05:39.71#ibcon#about to read 6, iclass 31, count 2 2006.182.08:05:39.71#ibcon#read 6, iclass 31, count 2 2006.182.08:05:39.71#ibcon#end of sib2, iclass 31, count 2 2006.182.08:05:39.71#ibcon#*mode == 0, iclass 31, count 2 2006.182.08:05:39.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.182.08:05:39.71#ibcon#[25=AT06-06\r\n] 2006.182.08:05:39.71#ibcon#*before write, iclass 31, count 2 2006.182.08:05:39.71#ibcon#enter sib2, iclass 31, count 2 2006.182.08:05:39.71#ibcon#flushed, iclass 31, count 2 2006.182.08:05:39.71#ibcon#about to write, iclass 31, count 2 2006.182.08:05:39.71#ibcon#wrote, iclass 31, count 2 2006.182.08:05:39.71#ibcon#about to read 3, iclass 31, count 2 2006.182.08:05:39.74#ibcon#read 3, iclass 31, count 2 2006.182.08:05:39.74#ibcon#about to read 4, iclass 31, count 2 2006.182.08:05:39.74#ibcon#read 4, iclass 31, count 2 2006.182.08:05:39.74#ibcon#about to read 5, iclass 31, count 2 2006.182.08:05:39.74#ibcon#read 5, iclass 31, count 2 2006.182.08:05:39.74#ibcon#about to read 6, iclass 31, count 2 2006.182.08:05:39.74#ibcon#read 6, iclass 31, count 2 2006.182.08:05:39.74#ibcon#end of sib2, iclass 31, count 2 2006.182.08:05:39.74#ibcon#*after write, iclass 31, count 2 2006.182.08:05:39.74#ibcon#*before return 0, iclass 31, count 2 2006.182.08:05:39.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:05:39.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:05:39.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.182.08:05:39.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:39.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:05:39.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:05:39.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:05:39.86#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:05:39.86#ibcon#first serial, iclass 31, count 0 2006.182.08:05:39.86#ibcon#enter sib2, iclass 31, count 0 2006.182.08:05:39.86#ibcon#flushed, iclass 31, count 0 2006.182.08:05:39.86#ibcon#about to write, iclass 31, count 0 2006.182.08:05:39.86#ibcon#wrote, iclass 31, count 0 2006.182.08:05:39.86#ibcon#about to read 3, iclass 31, count 0 2006.182.08:05:39.88#ibcon#read 3, iclass 31, count 0 2006.182.08:05:39.88#ibcon#about to read 4, iclass 31, count 0 2006.182.08:05:39.88#ibcon#read 4, iclass 31, count 0 2006.182.08:05:39.88#ibcon#about to read 5, iclass 31, count 0 2006.182.08:05:39.88#ibcon#read 5, iclass 31, count 0 2006.182.08:05:39.88#ibcon#about to read 6, iclass 31, count 0 2006.182.08:05:39.88#ibcon#read 6, iclass 31, count 0 2006.182.08:05:39.88#ibcon#end of sib2, iclass 31, count 0 2006.182.08:05:39.88#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:05:39.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:05:39.88#ibcon#[25=USB\r\n] 2006.182.08:05:39.88#ibcon#*before write, iclass 31, count 0 2006.182.08:05:39.88#ibcon#enter sib2, iclass 31, count 0 2006.182.08:05:39.88#ibcon#flushed, iclass 31, count 0 2006.182.08:05:39.88#ibcon#about to write, iclass 31, count 0 2006.182.08:05:39.88#ibcon#wrote, iclass 31, count 0 2006.182.08:05:39.88#ibcon#about to read 3, iclass 31, count 0 2006.182.08:05:39.91#ibcon#read 3, iclass 31, count 0 2006.182.08:05:39.91#ibcon#about to read 4, iclass 31, count 0 2006.182.08:05:39.91#ibcon#read 4, iclass 31, count 0 2006.182.08:05:39.91#ibcon#about to read 5, iclass 31, count 0 2006.182.08:05:39.91#ibcon#read 5, iclass 31, count 0 2006.182.08:05:39.91#ibcon#about to read 6, iclass 31, count 0 2006.182.08:05:39.91#ibcon#read 6, iclass 31, count 0 2006.182.08:05:39.91#ibcon#end of sib2, iclass 31, count 0 2006.182.08:05:39.91#ibcon#*after write, iclass 31, count 0 2006.182.08:05:39.91#ibcon#*before return 0, iclass 31, count 0 2006.182.08:05:39.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:05:39.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:05:39.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:05:39.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:05:39.91$vc4f8/valo=7,832.99 2006.182.08:05:39.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.182.08:05:39.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.182.08:05:39.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:39.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:05:39.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:05:39.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:05:39.91#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:05:39.91#ibcon#first serial, iclass 33, count 0 2006.182.08:05:39.91#ibcon#enter sib2, iclass 33, count 0 2006.182.08:05:39.91#ibcon#flushed, iclass 33, count 0 2006.182.08:05:39.91#ibcon#about to write, iclass 33, count 0 2006.182.08:05:39.91#ibcon#wrote, iclass 33, count 0 2006.182.08:05:39.91#ibcon#about to read 3, iclass 33, count 0 2006.182.08:05:39.93#ibcon#read 3, iclass 33, count 0 2006.182.08:05:39.93#ibcon#about to read 4, iclass 33, count 0 2006.182.08:05:39.93#ibcon#read 4, iclass 33, count 0 2006.182.08:05:39.93#ibcon#about to read 5, iclass 33, count 0 2006.182.08:05:39.93#ibcon#read 5, iclass 33, count 0 2006.182.08:05:39.93#ibcon#about to read 6, iclass 33, count 0 2006.182.08:05:39.93#ibcon#read 6, iclass 33, count 0 2006.182.08:05:39.93#ibcon#end of sib2, iclass 33, count 0 2006.182.08:05:39.93#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:05:39.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:05:39.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:05:39.93#ibcon#*before write, iclass 33, count 0 2006.182.08:05:39.93#ibcon#enter sib2, iclass 33, count 0 2006.182.08:05:39.93#ibcon#flushed, iclass 33, count 0 2006.182.08:05:39.93#ibcon#about to write, iclass 33, count 0 2006.182.08:05:39.93#ibcon#wrote, iclass 33, count 0 2006.182.08:05:39.93#ibcon#about to read 3, iclass 33, count 0 2006.182.08:05:39.97#ibcon#read 3, iclass 33, count 0 2006.182.08:05:39.97#ibcon#about to read 4, iclass 33, count 0 2006.182.08:05:39.97#ibcon#read 4, iclass 33, count 0 2006.182.08:05:39.97#ibcon#about to read 5, iclass 33, count 0 2006.182.08:05:39.97#ibcon#read 5, iclass 33, count 0 2006.182.08:05:39.97#ibcon#about to read 6, iclass 33, count 0 2006.182.08:05:39.97#ibcon#read 6, iclass 33, count 0 2006.182.08:05:39.97#ibcon#end of sib2, iclass 33, count 0 2006.182.08:05:39.97#ibcon#*after write, iclass 33, count 0 2006.182.08:05:39.97#ibcon#*before return 0, iclass 33, count 0 2006.182.08:05:39.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:05:39.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:05:39.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:05:39.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:05:39.97$vc4f8/va=7,6 2006.182.08:05:39.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.182.08:05:39.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.182.08:05:39.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:39.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:05:40.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:05:40.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:05:40.03#ibcon#enter wrdev, iclass 35, count 2 2006.182.08:05:40.03#ibcon#first serial, iclass 35, count 2 2006.182.08:05:40.03#ibcon#enter sib2, iclass 35, count 2 2006.182.08:05:40.03#ibcon#flushed, iclass 35, count 2 2006.182.08:05:40.03#ibcon#about to write, iclass 35, count 2 2006.182.08:05:40.03#ibcon#wrote, iclass 35, count 2 2006.182.08:05:40.03#ibcon#about to read 3, iclass 35, count 2 2006.182.08:05:40.05#ibcon#read 3, iclass 35, count 2 2006.182.08:05:40.05#ibcon#about to read 4, iclass 35, count 2 2006.182.08:05:40.05#ibcon#read 4, iclass 35, count 2 2006.182.08:05:40.05#ibcon#about to read 5, iclass 35, count 2 2006.182.08:05:40.05#ibcon#read 5, iclass 35, count 2 2006.182.08:05:40.05#ibcon#about to read 6, iclass 35, count 2 2006.182.08:05:40.05#ibcon#read 6, iclass 35, count 2 2006.182.08:05:40.05#ibcon#end of sib2, iclass 35, count 2 2006.182.08:05:40.05#ibcon#*mode == 0, iclass 35, count 2 2006.182.08:05:40.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.182.08:05:40.05#ibcon#[25=AT07-06\r\n] 2006.182.08:05:40.05#ibcon#*before write, iclass 35, count 2 2006.182.08:05:40.05#ibcon#enter sib2, iclass 35, count 2 2006.182.08:05:40.05#ibcon#flushed, iclass 35, count 2 2006.182.08:05:40.05#ibcon#about to write, iclass 35, count 2 2006.182.08:05:40.05#ibcon#wrote, iclass 35, count 2 2006.182.08:05:40.05#ibcon#about to read 3, iclass 35, count 2 2006.182.08:05:40.08#ibcon#read 3, iclass 35, count 2 2006.182.08:05:40.08#ibcon#about to read 4, iclass 35, count 2 2006.182.08:05:40.08#ibcon#read 4, iclass 35, count 2 2006.182.08:05:40.08#ibcon#about to read 5, iclass 35, count 2 2006.182.08:05:40.08#ibcon#read 5, iclass 35, count 2 2006.182.08:05:40.08#ibcon#about to read 6, iclass 35, count 2 2006.182.08:05:40.08#ibcon#read 6, iclass 35, count 2 2006.182.08:05:40.08#ibcon#end of sib2, iclass 35, count 2 2006.182.08:05:40.08#ibcon#*after write, iclass 35, count 2 2006.182.08:05:40.08#ibcon#*before return 0, iclass 35, count 2 2006.182.08:05:40.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:05:40.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:05:40.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.182.08:05:40.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:40.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:05:40.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:05:40.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:05:40.20#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:05:40.20#ibcon#first serial, iclass 35, count 0 2006.182.08:05:40.20#ibcon#enter sib2, iclass 35, count 0 2006.182.08:05:40.20#ibcon#flushed, iclass 35, count 0 2006.182.08:05:40.20#ibcon#about to write, iclass 35, count 0 2006.182.08:05:40.20#ibcon#wrote, iclass 35, count 0 2006.182.08:05:40.20#ibcon#about to read 3, iclass 35, count 0 2006.182.08:05:40.24#ibcon#read 3, iclass 35, count 0 2006.182.08:05:40.24#ibcon#about to read 4, iclass 35, count 0 2006.182.08:05:40.24#ibcon#read 4, iclass 35, count 0 2006.182.08:05:40.24#ibcon#about to read 5, iclass 35, count 0 2006.182.08:05:40.24#ibcon#read 5, iclass 35, count 0 2006.182.08:05:40.24#ibcon#about to read 6, iclass 35, count 0 2006.182.08:05:40.24#ibcon#read 6, iclass 35, count 0 2006.182.08:05:40.24#ibcon#end of sib2, iclass 35, count 0 2006.182.08:05:40.24#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:05:40.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:05:40.24#ibcon#[25=USB\r\n] 2006.182.08:05:40.24#ibcon#*before write, iclass 35, count 0 2006.182.08:05:40.24#ibcon#enter sib2, iclass 35, count 0 2006.182.08:05:40.24#ibcon#flushed, iclass 35, count 0 2006.182.08:05:40.24#ibcon#about to write, iclass 35, count 0 2006.182.08:05:40.24#ibcon#wrote, iclass 35, count 0 2006.182.08:05:40.24#ibcon#about to read 3, iclass 35, count 0 2006.182.08:05:40.26#ibcon#read 3, iclass 35, count 0 2006.182.08:05:40.26#ibcon#about to read 4, iclass 35, count 0 2006.182.08:05:40.26#ibcon#read 4, iclass 35, count 0 2006.182.08:05:40.26#ibcon#about to read 5, iclass 35, count 0 2006.182.08:05:40.26#ibcon#read 5, iclass 35, count 0 2006.182.08:05:40.26#ibcon#about to read 6, iclass 35, count 0 2006.182.08:05:40.26#ibcon#read 6, iclass 35, count 0 2006.182.08:05:40.26#ibcon#end of sib2, iclass 35, count 0 2006.182.08:05:40.26#ibcon#*after write, iclass 35, count 0 2006.182.08:05:40.26#ibcon#*before return 0, iclass 35, count 0 2006.182.08:05:40.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:05:40.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:05:40.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:05:40.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:05:40.26$vc4f8/valo=8,852.99 2006.182.08:05:40.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.182.08:05:40.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.182.08:05:40.26#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:40.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:05:40.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:05:40.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:05:40.26#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:05:40.26#ibcon#first serial, iclass 37, count 0 2006.182.08:05:40.26#ibcon#enter sib2, iclass 37, count 0 2006.182.08:05:40.26#ibcon#flushed, iclass 37, count 0 2006.182.08:05:40.26#ibcon#about to write, iclass 37, count 0 2006.182.08:05:40.26#ibcon#wrote, iclass 37, count 0 2006.182.08:05:40.26#ibcon#about to read 3, iclass 37, count 0 2006.182.08:05:40.28#ibcon#read 3, iclass 37, count 0 2006.182.08:05:40.28#ibcon#about to read 4, iclass 37, count 0 2006.182.08:05:40.28#ibcon#read 4, iclass 37, count 0 2006.182.08:05:40.28#ibcon#about to read 5, iclass 37, count 0 2006.182.08:05:40.28#ibcon#read 5, iclass 37, count 0 2006.182.08:05:40.28#ibcon#about to read 6, iclass 37, count 0 2006.182.08:05:40.28#ibcon#read 6, iclass 37, count 0 2006.182.08:05:40.28#ibcon#end of sib2, iclass 37, count 0 2006.182.08:05:40.28#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:05:40.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:05:40.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:05:40.28#ibcon#*before write, iclass 37, count 0 2006.182.08:05:40.28#ibcon#enter sib2, iclass 37, count 0 2006.182.08:05:40.28#ibcon#flushed, iclass 37, count 0 2006.182.08:05:40.28#ibcon#about to write, iclass 37, count 0 2006.182.08:05:40.28#ibcon#wrote, iclass 37, count 0 2006.182.08:05:40.28#ibcon#about to read 3, iclass 37, count 0 2006.182.08:05:40.32#ibcon#read 3, iclass 37, count 0 2006.182.08:05:40.32#ibcon#about to read 4, iclass 37, count 0 2006.182.08:05:40.32#ibcon#read 4, iclass 37, count 0 2006.182.08:05:40.32#ibcon#about to read 5, iclass 37, count 0 2006.182.08:05:40.32#ibcon#read 5, iclass 37, count 0 2006.182.08:05:40.32#ibcon#about to read 6, iclass 37, count 0 2006.182.08:05:40.32#ibcon#read 6, iclass 37, count 0 2006.182.08:05:40.32#ibcon#end of sib2, iclass 37, count 0 2006.182.08:05:40.32#ibcon#*after write, iclass 37, count 0 2006.182.08:05:40.32#ibcon#*before return 0, iclass 37, count 0 2006.182.08:05:40.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:05:40.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:05:40.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:05:40.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:05:40.32$vc4f8/va=8,7 2006.182.08:05:40.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.08:05:40.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.08:05:40.32#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:40.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:05:40.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:05:40.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:05:40.38#ibcon#enter wrdev, iclass 39, count 2 2006.182.08:05:40.38#ibcon#first serial, iclass 39, count 2 2006.182.08:05:40.38#ibcon#enter sib2, iclass 39, count 2 2006.182.08:05:40.38#ibcon#flushed, iclass 39, count 2 2006.182.08:05:40.38#ibcon#about to write, iclass 39, count 2 2006.182.08:05:40.38#ibcon#wrote, iclass 39, count 2 2006.182.08:05:40.38#ibcon#about to read 3, iclass 39, count 2 2006.182.08:05:40.40#ibcon#read 3, iclass 39, count 2 2006.182.08:05:40.40#ibcon#about to read 4, iclass 39, count 2 2006.182.08:05:40.40#ibcon#read 4, iclass 39, count 2 2006.182.08:05:40.40#ibcon#about to read 5, iclass 39, count 2 2006.182.08:05:40.40#ibcon#read 5, iclass 39, count 2 2006.182.08:05:40.40#ibcon#about to read 6, iclass 39, count 2 2006.182.08:05:40.40#ibcon#read 6, iclass 39, count 2 2006.182.08:05:40.40#ibcon#end of sib2, iclass 39, count 2 2006.182.08:05:40.40#ibcon#*mode == 0, iclass 39, count 2 2006.182.08:05:40.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.08:05:40.40#ibcon#[25=AT08-07\r\n] 2006.182.08:05:40.40#ibcon#*before write, iclass 39, count 2 2006.182.08:05:40.40#ibcon#enter sib2, iclass 39, count 2 2006.182.08:05:40.40#ibcon#flushed, iclass 39, count 2 2006.182.08:05:40.40#ibcon#about to write, iclass 39, count 2 2006.182.08:05:40.40#ibcon#wrote, iclass 39, count 2 2006.182.08:05:40.40#ibcon#about to read 3, iclass 39, count 2 2006.182.08:05:40.43#ibcon#read 3, iclass 39, count 2 2006.182.08:05:40.43#ibcon#about to read 4, iclass 39, count 2 2006.182.08:05:40.43#ibcon#read 4, iclass 39, count 2 2006.182.08:05:40.43#ibcon#about to read 5, iclass 39, count 2 2006.182.08:05:40.43#ibcon#read 5, iclass 39, count 2 2006.182.08:05:40.43#ibcon#about to read 6, iclass 39, count 2 2006.182.08:05:40.43#ibcon#read 6, iclass 39, count 2 2006.182.08:05:40.43#ibcon#end of sib2, iclass 39, count 2 2006.182.08:05:40.43#ibcon#*after write, iclass 39, count 2 2006.182.08:05:40.43#ibcon#*before return 0, iclass 39, count 2 2006.182.08:05:40.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:05:40.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:05:40.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.08:05:40.43#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:40.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:05:40.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:05:40.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:05:40.55#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:05:40.55#ibcon#first serial, iclass 39, count 0 2006.182.08:05:40.55#ibcon#enter sib2, iclass 39, count 0 2006.182.08:05:40.55#ibcon#flushed, iclass 39, count 0 2006.182.08:05:40.55#ibcon#about to write, iclass 39, count 0 2006.182.08:05:40.55#ibcon#wrote, iclass 39, count 0 2006.182.08:05:40.55#ibcon#about to read 3, iclass 39, count 0 2006.182.08:05:40.57#ibcon#read 3, iclass 39, count 0 2006.182.08:05:40.57#ibcon#about to read 4, iclass 39, count 0 2006.182.08:05:40.57#ibcon#read 4, iclass 39, count 0 2006.182.08:05:40.57#ibcon#about to read 5, iclass 39, count 0 2006.182.08:05:40.57#ibcon#read 5, iclass 39, count 0 2006.182.08:05:40.57#ibcon#about to read 6, iclass 39, count 0 2006.182.08:05:40.57#ibcon#read 6, iclass 39, count 0 2006.182.08:05:40.57#ibcon#end of sib2, iclass 39, count 0 2006.182.08:05:40.57#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:05:40.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:05:40.57#ibcon#[25=USB\r\n] 2006.182.08:05:40.57#ibcon#*before write, iclass 39, count 0 2006.182.08:05:40.57#ibcon#enter sib2, iclass 39, count 0 2006.182.08:05:40.57#ibcon#flushed, iclass 39, count 0 2006.182.08:05:40.57#ibcon#about to write, iclass 39, count 0 2006.182.08:05:40.57#ibcon#wrote, iclass 39, count 0 2006.182.08:05:40.57#ibcon#about to read 3, iclass 39, count 0 2006.182.08:05:40.60#ibcon#read 3, iclass 39, count 0 2006.182.08:05:40.60#ibcon#about to read 4, iclass 39, count 0 2006.182.08:05:40.60#ibcon#read 4, iclass 39, count 0 2006.182.08:05:40.60#ibcon#about to read 5, iclass 39, count 0 2006.182.08:05:40.60#ibcon#read 5, iclass 39, count 0 2006.182.08:05:40.60#ibcon#about to read 6, iclass 39, count 0 2006.182.08:05:40.60#ibcon#read 6, iclass 39, count 0 2006.182.08:05:40.60#ibcon#end of sib2, iclass 39, count 0 2006.182.08:05:40.60#ibcon#*after write, iclass 39, count 0 2006.182.08:05:40.60#ibcon#*before return 0, iclass 39, count 0 2006.182.08:05:40.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:05:40.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:05:40.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:05:40.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:05:40.60$vc4f8/vblo=1,632.99 2006.182.08:05:40.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.08:05:40.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.08:05:40.60#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:40.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:40.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:40.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:40.60#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:05:40.60#ibcon#first serial, iclass 3, count 0 2006.182.08:05:40.60#ibcon#enter sib2, iclass 3, count 0 2006.182.08:05:40.60#ibcon#flushed, iclass 3, count 0 2006.182.08:05:40.60#ibcon#about to write, iclass 3, count 0 2006.182.08:05:40.60#ibcon#wrote, iclass 3, count 0 2006.182.08:05:40.60#ibcon#about to read 3, iclass 3, count 0 2006.182.08:05:40.62#ibcon#read 3, iclass 3, count 0 2006.182.08:05:40.62#ibcon#about to read 4, iclass 3, count 0 2006.182.08:05:40.62#ibcon#read 4, iclass 3, count 0 2006.182.08:05:40.62#ibcon#about to read 5, iclass 3, count 0 2006.182.08:05:40.62#ibcon#read 5, iclass 3, count 0 2006.182.08:05:40.62#ibcon#about to read 6, iclass 3, count 0 2006.182.08:05:40.62#ibcon#read 6, iclass 3, count 0 2006.182.08:05:40.62#ibcon#end of sib2, iclass 3, count 0 2006.182.08:05:40.62#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:05:40.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:05:40.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:05:40.62#ibcon#*before write, iclass 3, count 0 2006.182.08:05:40.62#ibcon#enter sib2, iclass 3, count 0 2006.182.08:05:40.62#ibcon#flushed, iclass 3, count 0 2006.182.08:05:40.62#ibcon#about to write, iclass 3, count 0 2006.182.08:05:40.62#ibcon#wrote, iclass 3, count 0 2006.182.08:05:40.62#ibcon#about to read 3, iclass 3, count 0 2006.182.08:05:40.66#ibcon#read 3, iclass 3, count 0 2006.182.08:05:40.66#ibcon#about to read 4, iclass 3, count 0 2006.182.08:05:40.66#ibcon#read 4, iclass 3, count 0 2006.182.08:05:40.66#ibcon#about to read 5, iclass 3, count 0 2006.182.08:05:40.66#ibcon#read 5, iclass 3, count 0 2006.182.08:05:40.66#ibcon#about to read 6, iclass 3, count 0 2006.182.08:05:40.66#ibcon#read 6, iclass 3, count 0 2006.182.08:05:40.66#ibcon#end of sib2, iclass 3, count 0 2006.182.08:05:40.66#ibcon#*after write, iclass 3, count 0 2006.182.08:05:40.66#ibcon#*before return 0, iclass 3, count 0 2006.182.08:05:40.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:40.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:05:40.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:05:40.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:05:40.66$vc4f8/vb=1,4 2006.182.08:05:40.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.08:05:40.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.08:05:40.66#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:40.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:40.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:40.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:40.66#ibcon#enter wrdev, iclass 5, count 2 2006.182.08:05:40.66#ibcon#first serial, iclass 5, count 2 2006.182.08:05:40.66#ibcon#enter sib2, iclass 5, count 2 2006.182.08:05:40.66#ibcon#flushed, iclass 5, count 2 2006.182.08:05:40.66#ibcon#about to write, iclass 5, count 2 2006.182.08:05:40.66#ibcon#wrote, iclass 5, count 2 2006.182.08:05:40.66#ibcon#about to read 3, iclass 5, count 2 2006.182.08:05:40.68#ibcon#read 3, iclass 5, count 2 2006.182.08:05:40.68#ibcon#about to read 4, iclass 5, count 2 2006.182.08:05:40.68#ibcon#read 4, iclass 5, count 2 2006.182.08:05:40.68#ibcon#about to read 5, iclass 5, count 2 2006.182.08:05:40.68#ibcon#read 5, iclass 5, count 2 2006.182.08:05:40.68#ibcon#about to read 6, iclass 5, count 2 2006.182.08:05:40.68#ibcon#read 6, iclass 5, count 2 2006.182.08:05:40.68#ibcon#end of sib2, iclass 5, count 2 2006.182.08:05:40.68#ibcon#*mode == 0, iclass 5, count 2 2006.182.08:05:40.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.08:05:40.68#ibcon#[27=AT01-04\r\n] 2006.182.08:05:40.68#ibcon#*before write, iclass 5, count 2 2006.182.08:05:40.68#ibcon#enter sib2, iclass 5, count 2 2006.182.08:05:40.68#ibcon#flushed, iclass 5, count 2 2006.182.08:05:40.68#ibcon#about to write, iclass 5, count 2 2006.182.08:05:40.68#ibcon#wrote, iclass 5, count 2 2006.182.08:05:40.68#ibcon#about to read 3, iclass 5, count 2 2006.182.08:05:40.71#ibcon#read 3, iclass 5, count 2 2006.182.08:05:40.71#ibcon#about to read 4, iclass 5, count 2 2006.182.08:05:40.71#ibcon#read 4, iclass 5, count 2 2006.182.08:05:40.71#ibcon#about to read 5, iclass 5, count 2 2006.182.08:05:40.71#ibcon#read 5, iclass 5, count 2 2006.182.08:05:40.71#ibcon#about to read 6, iclass 5, count 2 2006.182.08:05:40.71#ibcon#read 6, iclass 5, count 2 2006.182.08:05:40.71#ibcon#end of sib2, iclass 5, count 2 2006.182.08:05:40.71#ibcon#*after write, iclass 5, count 2 2006.182.08:05:40.71#ibcon#*before return 0, iclass 5, count 2 2006.182.08:05:40.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:40.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:05:40.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.08:05:40.71#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:40.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:40.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:40.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:40.83#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:05:40.83#ibcon#first serial, iclass 5, count 0 2006.182.08:05:40.83#ibcon#enter sib2, iclass 5, count 0 2006.182.08:05:40.83#ibcon#flushed, iclass 5, count 0 2006.182.08:05:40.83#ibcon#about to write, iclass 5, count 0 2006.182.08:05:40.83#ibcon#wrote, iclass 5, count 0 2006.182.08:05:40.83#ibcon#about to read 3, iclass 5, count 0 2006.182.08:05:40.85#ibcon#read 3, iclass 5, count 0 2006.182.08:05:40.85#ibcon#about to read 4, iclass 5, count 0 2006.182.08:05:40.85#ibcon#read 4, iclass 5, count 0 2006.182.08:05:40.85#ibcon#about to read 5, iclass 5, count 0 2006.182.08:05:40.85#ibcon#read 5, iclass 5, count 0 2006.182.08:05:40.85#ibcon#about to read 6, iclass 5, count 0 2006.182.08:05:40.85#ibcon#read 6, iclass 5, count 0 2006.182.08:05:40.85#ibcon#end of sib2, iclass 5, count 0 2006.182.08:05:40.85#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:05:40.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:05:40.85#ibcon#[27=USB\r\n] 2006.182.08:05:40.85#ibcon#*before write, iclass 5, count 0 2006.182.08:05:40.85#ibcon#enter sib2, iclass 5, count 0 2006.182.08:05:40.85#ibcon#flushed, iclass 5, count 0 2006.182.08:05:40.85#ibcon#about to write, iclass 5, count 0 2006.182.08:05:40.85#ibcon#wrote, iclass 5, count 0 2006.182.08:05:40.85#ibcon#about to read 3, iclass 5, count 0 2006.182.08:05:40.88#ibcon#read 3, iclass 5, count 0 2006.182.08:05:40.88#ibcon#about to read 4, iclass 5, count 0 2006.182.08:05:40.88#ibcon#read 4, iclass 5, count 0 2006.182.08:05:40.88#ibcon#about to read 5, iclass 5, count 0 2006.182.08:05:40.88#ibcon#read 5, iclass 5, count 0 2006.182.08:05:40.88#ibcon#about to read 6, iclass 5, count 0 2006.182.08:05:40.88#ibcon#read 6, iclass 5, count 0 2006.182.08:05:40.88#ibcon#end of sib2, iclass 5, count 0 2006.182.08:05:40.88#ibcon#*after write, iclass 5, count 0 2006.182.08:05:40.88#ibcon#*before return 0, iclass 5, count 0 2006.182.08:05:40.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:40.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:05:40.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:05:40.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:05:40.88$vc4f8/vblo=2,640.99 2006.182.08:05:40.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.08:05:40.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.08:05:40.88#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:40.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:40.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:40.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:40.88#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:05:40.88#ibcon#first serial, iclass 7, count 0 2006.182.08:05:40.88#ibcon#enter sib2, iclass 7, count 0 2006.182.08:05:40.88#ibcon#flushed, iclass 7, count 0 2006.182.08:05:40.88#ibcon#about to write, iclass 7, count 0 2006.182.08:05:40.88#ibcon#wrote, iclass 7, count 0 2006.182.08:05:40.88#ibcon#about to read 3, iclass 7, count 0 2006.182.08:05:40.90#ibcon#read 3, iclass 7, count 0 2006.182.08:05:40.90#ibcon#about to read 4, iclass 7, count 0 2006.182.08:05:40.90#ibcon#read 4, iclass 7, count 0 2006.182.08:05:40.90#ibcon#about to read 5, iclass 7, count 0 2006.182.08:05:40.90#ibcon#read 5, iclass 7, count 0 2006.182.08:05:40.90#ibcon#about to read 6, iclass 7, count 0 2006.182.08:05:40.90#ibcon#read 6, iclass 7, count 0 2006.182.08:05:40.90#ibcon#end of sib2, iclass 7, count 0 2006.182.08:05:40.90#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:05:40.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:05:40.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:05:40.90#ibcon#*before write, iclass 7, count 0 2006.182.08:05:40.90#ibcon#enter sib2, iclass 7, count 0 2006.182.08:05:40.90#ibcon#flushed, iclass 7, count 0 2006.182.08:05:40.90#ibcon#about to write, iclass 7, count 0 2006.182.08:05:40.90#ibcon#wrote, iclass 7, count 0 2006.182.08:05:40.90#ibcon#about to read 3, iclass 7, count 0 2006.182.08:05:40.94#ibcon#read 3, iclass 7, count 0 2006.182.08:05:40.94#ibcon#about to read 4, iclass 7, count 0 2006.182.08:05:40.94#ibcon#read 4, iclass 7, count 0 2006.182.08:05:40.94#ibcon#about to read 5, iclass 7, count 0 2006.182.08:05:40.94#ibcon#read 5, iclass 7, count 0 2006.182.08:05:40.94#ibcon#about to read 6, iclass 7, count 0 2006.182.08:05:40.94#ibcon#read 6, iclass 7, count 0 2006.182.08:05:40.94#ibcon#end of sib2, iclass 7, count 0 2006.182.08:05:40.94#ibcon#*after write, iclass 7, count 0 2006.182.08:05:40.94#ibcon#*before return 0, iclass 7, count 0 2006.182.08:05:40.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:40.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:05:40.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:05:40.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:05:40.94$vc4f8/vb=2,4 2006.182.08:05:40.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.08:05:40.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.08:05:40.94#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:40.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:41.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:41.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:41.00#ibcon#enter wrdev, iclass 11, count 2 2006.182.08:05:41.00#ibcon#first serial, iclass 11, count 2 2006.182.08:05:41.00#ibcon#enter sib2, iclass 11, count 2 2006.182.08:05:41.00#ibcon#flushed, iclass 11, count 2 2006.182.08:05:41.00#ibcon#about to write, iclass 11, count 2 2006.182.08:05:41.00#ibcon#wrote, iclass 11, count 2 2006.182.08:05:41.00#ibcon#about to read 3, iclass 11, count 2 2006.182.08:05:41.02#ibcon#read 3, iclass 11, count 2 2006.182.08:05:41.02#ibcon#about to read 4, iclass 11, count 2 2006.182.08:05:41.02#ibcon#read 4, iclass 11, count 2 2006.182.08:05:41.02#ibcon#about to read 5, iclass 11, count 2 2006.182.08:05:41.02#ibcon#read 5, iclass 11, count 2 2006.182.08:05:41.02#ibcon#about to read 6, iclass 11, count 2 2006.182.08:05:41.02#ibcon#read 6, iclass 11, count 2 2006.182.08:05:41.02#ibcon#end of sib2, iclass 11, count 2 2006.182.08:05:41.02#ibcon#*mode == 0, iclass 11, count 2 2006.182.08:05:41.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.08:05:41.02#ibcon#[27=AT02-04\r\n] 2006.182.08:05:41.02#ibcon#*before write, iclass 11, count 2 2006.182.08:05:41.02#ibcon#enter sib2, iclass 11, count 2 2006.182.08:05:41.02#ibcon#flushed, iclass 11, count 2 2006.182.08:05:41.02#ibcon#about to write, iclass 11, count 2 2006.182.08:05:41.02#ibcon#wrote, iclass 11, count 2 2006.182.08:05:41.02#ibcon#about to read 3, iclass 11, count 2 2006.182.08:05:41.05#ibcon#read 3, iclass 11, count 2 2006.182.08:05:41.05#ibcon#about to read 4, iclass 11, count 2 2006.182.08:05:41.05#ibcon#read 4, iclass 11, count 2 2006.182.08:05:41.05#ibcon#about to read 5, iclass 11, count 2 2006.182.08:05:41.05#ibcon#read 5, iclass 11, count 2 2006.182.08:05:41.05#ibcon#about to read 6, iclass 11, count 2 2006.182.08:05:41.05#ibcon#read 6, iclass 11, count 2 2006.182.08:05:41.05#ibcon#end of sib2, iclass 11, count 2 2006.182.08:05:41.05#ibcon#*after write, iclass 11, count 2 2006.182.08:05:41.05#ibcon#*before return 0, iclass 11, count 2 2006.182.08:05:41.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:41.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:05:41.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.08:05:41.05#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:41.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:41.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:41.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:41.17#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:05:41.17#ibcon#first serial, iclass 11, count 0 2006.182.08:05:41.17#ibcon#enter sib2, iclass 11, count 0 2006.182.08:05:41.17#ibcon#flushed, iclass 11, count 0 2006.182.08:05:41.17#ibcon#about to write, iclass 11, count 0 2006.182.08:05:41.17#ibcon#wrote, iclass 11, count 0 2006.182.08:05:41.17#ibcon#about to read 3, iclass 11, count 0 2006.182.08:05:41.19#ibcon#read 3, iclass 11, count 0 2006.182.08:05:41.19#ibcon#about to read 4, iclass 11, count 0 2006.182.08:05:41.19#ibcon#read 4, iclass 11, count 0 2006.182.08:05:41.19#ibcon#about to read 5, iclass 11, count 0 2006.182.08:05:41.19#ibcon#read 5, iclass 11, count 0 2006.182.08:05:41.19#ibcon#about to read 6, iclass 11, count 0 2006.182.08:05:41.19#ibcon#read 6, iclass 11, count 0 2006.182.08:05:41.19#ibcon#end of sib2, iclass 11, count 0 2006.182.08:05:41.19#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:05:41.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:05:41.19#ibcon#[27=USB\r\n] 2006.182.08:05:41.19#ibcon#*before write, iclass 11, count 0 2006.182.08:05:41.19#ibcon#enter sib2, iclass 11, count 0 2006.182.08:05:41.19#ibcon#flushed, iclass 11, count 0 2006.182.08:05:41.19#ibcon#about to write, iclass 11, count 0 2006.182.08:05:41.19#ibcon#wrote, iclass 11, count 0 2006.182.08:05:41.19#ibcon#about to read 3, iclass 11, count 0 2006.182.08:05:41.22#ibcon#read 3, iclass 11, count 0 2006.182.08:05:41.22#ibcon#about to read 4, iclass 11, count 0 2006.182.08:05:41.22#ibcon#read 4, iclass 11, count 0 2006.182.08:05:41.22#ibcon#about to read 5, iclass 11, count 0 2006.182.08:05:41.22#ibcon#read 5, iclass 11, count 0 2006.182.08:05:41.22#ibcon#about to read 6, iclass 11, count 0 2006.182.08:05:41.22#ibcon#read 6, iclass 11, count 0 2006.182.08:05:41.22#ibcon#end of sib2, iclass 11, count 0 2006.182.08:05:41.22#ibcon#*after write, iclass 11, count 0 2006.182.08:05:41.22#ibcon#*before return 0, iclass 11, count 0 2006.182.08:05:41.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:41.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:05:41.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:05:41.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:05:41.22$vc4f8/vblo=3,656.99 2006.182.08:05:41.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.08:05:41.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.08:05:41.22#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:41.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:05:41.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:05:41.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:05:41.22#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:05:41.22#ibcon#first serial, iclass 13, count 0 2006.182.08:05:41.22#ibcon#enter sib2, iclass 13, count 0 2006.182.08:05:41.22#ibcon#flushed, iclass 13, count 0 2006.182.08:05:41.22#ibcon#about to write, iclass 13, count 0 2006.182.08:05:41.22#ibcon#wrote, iclass 13, count 0 2006.182.08:05:41.22#ibcon#about to read 3, iclass 13, count 0 2006.182.08:05:41.24#ibcon#read 3, iclass 13, count 0 2006.182.08:05:41.24#ibcon#about to read 4, iclass 13, count 0 2006.182.08:05:41.24#ibcon#read 4, iclass 13, count 0 2006.182.08:05:41.24#ibcon#about to read 5, iclass 13, count 0 2006.182.08:05:41.24#ibcon#read 5, iclass 13, count 0 2006.182.08:05:41.24#ibcon#about to read 6, iclass 13, count 0 2006.182.08:05:41.24#ibcon#read 6, iclass 13, count 0 2006.182.08:05:41.24#ibcon#end of sib2, iclass 13, count 0 2006.182.08:05:41.24#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:05:41.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:05:41.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:05:41.24#ibcon#*before write, iclass 13, count 0 2006.182.08:05:41.24#ibcon#enter sib2, iclass 13, count 0 2006.182.08:05:41.24#ibcon#flushed, iclass 13, count 0 2006.182.08:05:41.24#ibcon#about to write, iclass 13, count 0 2006.182.08:05:41.24#ibcon#wrote, iclass 13, count 0 2006.182.08:05:41.24#ibcon#about to read 3, iclass 13, count 0 2006.182.08:05:41.28#ibcon#read 3, iclass 13, count 0 2006.182.08:05:41.28#ibcon#about to read 4, iclass 13, count 0 2006.182.08:05:41.28#ibcon#read 4, iclass 13, count 0 2006.182.08:05:41.28#ibcon#about to read 5, iclass 13, count 0 2006.182.08:05:41.28#ibcon#read 5, iclass 13, count 0 2006.182.08:05:41.28#ibcon#about to read 6, iclass 13, count 0 2006.182.08:05:41.28#ibcon#read 6, iclass 13, count 0 2006.182.08:05:41.28#ibcon#end of sib2, iclass 13, count 0 2006.182.08:05:41.28#ibcon#*after write, iclass 13, count 0 2006.182.08:05:41.28#ibcon#*before return 0, iclass 13, count 0 2006.182.08:05:41.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:05:41.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:05:41.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:05:41.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:05:41.28$vc4f8/vb=3,4 2006.182.08:05:41.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.182.08:05:41.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.182.08:05:41.28#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:41.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:05:41.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:05:41.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:05:41.34#ibcon#enter wrdev, iclass 15, count 2 2006.182.08:05:41.34#ibcon#first serial, iclass 15, count 2 2006.182.08:05:41.34#ibcon#enter sib2, iclass 15, count 2 2006.182.08:05:41.34#ibcon#flushed, iclass 15, count 2 2006.182.08:05:41.34#ibcon#about to write, iclass 15, count 2 2006.182.08:05:41.34#ibcon#wrote, iclass 15, count 2 2006.182.08:05:41.34#ibcon#about to read 3, iclass 15, count 2 2006.182.08:05:41.36#ibcon#read 3, iclass 15, count 2 2006.182.08:05:41.36#ibcon#about to read 4, iclass 15, count 2 2006.182.08:05:41.36#ibcon#read 4, iclass 15, count 2 2006.182.08:05:41.36#ibcon#about to read 5, iclass 15, count 2 2006.182.08:05:41.36#ibcon#read 5, iclass 15, count 2 2006.182.08:05:41.36#ibcon#about to read 6, iclass 15, count 2 2006.182.08:05:41.36#ibcon#read 6, iclass 15, count 2 2006.182.08:05:41.36#ibcon#end of sib2, iclass 15, count 2 2006.182.08:05:41.36#ibcon#*mode == 0, iclass 15, count 2 2006.182.08:05:41.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.182.08:05:41.36#ibcon#[27=AT03-04\r\n] 2006.182.08:05:41.36#ibcon#*before write, iclass 15, count 2 2006.182.08:05:41.36#ibcon#enter sib2, iclass 15, count 2 2006.182.08:05:41.36#ibcon#flushed, iclass 15, count 2 2006.182.08:05:41.36#ibcon#about to write, iclass 15, count 2 2006.182.08:05:41.36#ibcon#wrote, iclass 15, count 2 2006.182.08:05:41.36#ibcon#about to read 3, iclass 15, count 2 2006.182.08:05:41.39#ibcon#read 3, iclass 15, count 2 2006.182.08:05:41.39#ibcon#about to read 4, iclass 15, count 2 2006.182.08:05:41.39#ibcon#read 4, iclass 15, count 2 2006.182.08:05:41.39#ibcon#about to read 5, iclass 15, count 2 2006.182.08:05:41.39#ibcon#read 5, iclass 15, count 2 2006.182.08:05:41.39#ibcon#about to read 6, iclass 15, count 2 2006.182.08:05:41.39#ibcon#read 6, iclass 15, count 2 2006.182.08:05:41.39#ibcon#end of sib2, iclass 15, count 2 2006.182.08:05:41.39#ibcon#*after write, iclass 15, count 2 2006.182.08:05:41.39#ibcon#*before return 0, iclass 15, count 2 2006.182.08:05:41.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:05:41.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:05:41.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.182.08:05:41.39#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:41.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:05:41.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:05:41.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:05:41.51#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:05:41.51#ibcon#first serial, iclass 15, count 0 2006.182.08:05:41.51#ibcon#enter sib2, iclass 15, count 0 2006.182.08:05:41.51#ibcon#flushed, iclass 15, count 0 2006.182.08:05:41.51#ibcon#about to write, iclass 15, count 0 2006.182.08:05:41.51#ibcon#wrote, iclass 15, count 0 2006.182.08:05:41.51#ibcon#about to read 3, iclass 15, count 0 2006.182.08:05:41.53#ibcon#read 3, iclass 15, count 0 2006.182.08:05:41.53#ibcon#about to read 4, iclass 15, count 0 2006.182.08:05:41.53#ibcon#read 4, iclass 15, count 0 2006.182.08:05:41.53#ibcon#about to read 5, iclass 15, count 0 2006.182.08:05:41.53#ibcon#read 5, iclass 15, count 0 2006.182.08:05:41.53#ibcon#about to read 6, iclass 15, count 0 2006.182.08:05:41.53#ibcon#read 6, iclass 15, count 0 2006.182.08:05:41.53#ibcon#end of sib2, iclass 15, count 0 2006.182.08:05:41.53#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:05:41.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:05:41.53#ibcon#[27=USB\r\n] 2006.182.08:05:41.53#ibcon#*before write, iclass 15, count 0 2006.182.08:05:41.53#ibcon#enter sib2, iclass 15, count 0 2006.182.08:05:41.53#ibcon#flushed, iclass 15, count 0 2006.182.08:05:41.53#ibcon#about to write, iclass 15, count 0 2006.182.08:05:41.53#ibcon#wrote, iclass 15, count 0 2006.182.08:05:41.53#ibcon#about to read 3, iclass 15, count 0 2006.182.08:05:41.56#ibcon#read 3, iclass 15, count 0 2006.182.08:05:41.56#ibcon#about to read 4, iclass 15, count 0 2006.182.08:05:41.56#ibcon#read 4, iclass 15, count 0 2006.182.08:05:41.56#ibcon#about to read 5, iclass 15, count 0 2006.182.08:05:41.56#ibcon#read 5, iclass 15, count 0 2006.182.08:05:41.56#ibcon#about to read 6, iclass 15, count 0 2006.182.08:05:41.56#ibcon#read 6, iclass 15, count 0 2006.182.08:05:41.56#ibcon#end of sib2, iclass 15, count 0 2006.182.08:05:41.56#ibcon#*after write, iclass 15, count 0 2006.182.08:05:41.56#ibcon#*before return 0, iclass 15, count 0 2006.182.08:05:41.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:05:41.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:05:41.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:05:41.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:05:41.56$vc4f8/vblo=4,712.99 2006.182.08:05:41.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.08:05:41.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.08:05:41.56#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:41.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:41.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:41.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:41.56#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:05:41.56#ibcon#first serial, iclass 17, count 0 2006.182.08:05:41.56#ibcon#enter sib2, iclass 17, count 0 2006.182.08:05:41.56#ibcon#flushed, iclass 17, count 0 2006.182.08:05:41.56#ibcon#about to write, iclass 17, count 0 2006.182.08:05:41.56#ibcon#wrote, iclass 17, count 0 2006.182.08:05:41.56#ibcon#about to read 3, iclass 17, count 0 2006.182.08:05:41.58#ibcon#read 3, iclass 17, count 0 2006.182.08:05:41.58#ibcon#about to read 4, iclass 17, count 0 2006.182.08:05:41.58#ibcon#read 4, iclass 17, count 0 2006.182.08:05:41.58#ibcon#about to read 5, iclass 17, count 0 2006.182.08:05:41.58#ibcon#read 5, iclass 17, count 0 2006.182.08:05:41.58#ibcon#about to read 6, iclass 17, count 0 2006.182.08:05:41.58#ibcon#read 6, iclass 17, count 0 2006.182.08:05:41.58#ibcon#end of sib2, iclass 17, count 0 2006.182.08:05:41.58#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:05:41.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:05:41.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:05:41.58#ibcon#*before write, iclass 17, count 0 2006.182.08:05:41.58#ibcon#enter sib2, iclass 17, count 0 2006.182.08:05:41.58#ibcon#flushed, iclass 17, count 0 2006.182.08:05:41.58#ibcon#about to write, iclass 17, count 0 2006.182.08:05:41.58#ibcon#wrote, iclass 17, count 0 2006.182.08:05:41.58#ibcon#about to read 3, iclass 17, count 0 2006.182.08:05:41.62#ibcon#read 3, iclass 17, count 0 2006.182.08:05:41.62#ibcon#about to read 4, iclass 17, count 0 2006.182.08:05:41.62#ibcon#read 4, iclass 17, count 0 2006.182.08:05:41.62#ibcon#about to read 5, iclass 17, count 0 2006.182.08:05:41.62#ibcon#read 5, iclass 17, count 0 2006.182.08:05:41.62#ibcon#about to read 6, iclass 17, count 0 2006.182.08:05:41.62#ibcon#read 6, iclass 17, count 0 2006.182.08:05:41.62#ibcon#end of sib2, iclass 17, count 0 2006.182.08:05:41.62#ibcon#*after write, iclass 17, count 0 2006.182.08:05:41.62#ibcon#*before return 0, iclass 17, count 0 2006.182.08:05:41.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:41.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:05:41.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:05:41.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:05:41.62$vc4f8/vb=4,4 2006.182.08:05:41.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.182.08:05:41.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.182.08:05:41.62#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:41.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:41.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:41.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:41.68#ibcon#enter wrdev, iclass 19, count 2 2006.182.08:05:41.68#ibcon#first serial, iclass 19, count 2 2006.182.08:05:41.68#ibcon#enter sib2, iclass 19, count 2 2006.182.08:05:41.68#ibcon#flushed, iclass 19, count 2 2006.182.08:05:41.68#ibcon#about to write, iclass 19, count 2 2006.182.08:05:41.68#ibcon#wrote, iclass 19, count 2 2006.182.08:05:41.68#ibcon#about to read 3, iclass 19, count 2 2006.182.08:05:41.70#ibcon#read 3, iclass 19, count 2 2006.182.08:05:41.70#ibcon#about to read 4, iclass 19, count 2 2006.182.08:05:41.70#ibcon#read 4, iclass 19, count 2 2006.182.08:05:41.70#ibcon#about to read 5, iclass 19, count 2 2006.182.08:05:41.70#ibcon#read 5, iclass 19, count 2 2006.182.08:05:41.70#ibcon#about to read 6, iclass 19, count 2 2006.182.08:05:41.70#ibcon#read 6, iclass 19, count 2 2006.182.08:05:41.70#ibcon#end of sib2, iclass 19, count 2 2006.182.08:05:41.70#ibcon#*mode == 0, iclass 19, count 2 2006.182.08:05:41.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.182.08:05:41.70#ibcon#[27=AT04-04\r\n] 2006.182.08:05:41.70#ibcon#*before write, iclass 19, count 2 2006.182.08:05:41.70#ibcon#enter sib2, iclass 19, count 2 2006.182.08:05:41.70#ibcon#flushed, iclass 19, count 2 2006.182.08:05:41.70#ibcon#about to write, iclass 19, count 2 2006.182.08:05:41.70#ibcon#wrote, iclass 19, count 2 2006.182.08:05:41.70#ibcon#about to read 3, iclass 19, count 2 2006.182.08:05:41.73#ibcon#read 3, iclass 19, count 2 2006.182.08:05:41.73#ibcon#about to read 4, iclass 19, count 2 2006.182.08:05:41.73#ibcon#read 4, iclass 19, count 2 2006.182.08:05:41.73#ibcon#about to read 5, iclass 19, count 2 2006.182.08:05:41.73#ibcon#read 5, iclass 19, count 2 2006.182.08:05:41.73#ibcon#about to read 6, iclass 19, count 2 2006.182.08:05:41.73#ibcon#read 6, iclass 19, count 2 2006.182.08:05:41.73#ibcon#end of sib2, iclass 19, count 2 2006.182.08:05:41.73#ibcon#*after write, iclass 19, count 2 2006.182.08:05:41.73#ibcon#*before return 0, iclass 19, count 2 2006.182.08:05:41.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:41.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:05:41.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.182.08:05:41.73#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:41.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:41.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:41.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:41.85#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:05:41.85#ibcon#first serial, iclass 19, count 0 2006.182.08:05:41.85#ibcon#enter sib2, iclass 19, count 0 2006.182.08:05:41.85#ibcon#flushed, iclass 19, count 0 2006.182.08:05:41.85#ibcon#about to write, iclass 19, count 0 2006.182.08:05:41.85#ibcon#wrote, iclass 19, count 0 2006.182.08:05:41.85#ibcon#about to read 3, iclass 19, count 0 2006.182.08:05:41.87#ibcon#read 3, iclass 19, count 0 2006.182.08:05:41.87#ibcon#about to read 4, iclass 19, count 0 2006.182.08:05:41.87#ibcon#read 4, iclass 19, count 0 2006.182.08:05:41.87#ibcon#about to read 5, iclass 19, count 0 2006.182.08:05:41.87#ibcon#read 5, iclass 19, count 0 2006.182.08:05:41.87#ibcon#about to read 6, iclass 19, count 0 2006.182.08:05:41.87#ibcon#read 6, iclass 19, count 0 2006.182.08:05:41.87#ibcon#end of sib2, iclass 19, count 0 2006.182.08:05:41.87#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:05:41.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:05:41.87#ibcon#[27=USB\r\n] 2006.182.08:05:41.87#ibcon#*before write, iclass 19, count 0 2006.182.08:05:41.87#ibcon#enter sib2, iclass 19, count 0 2006.182.08:05:41.87#ibcon#flushed, iclass 19, count 0 2006.182.08:05:41.87#ibcon#about to write, iclass 19, count 0 2006.182.08:05:41.87#ibcon#wrote, iclass 19, count 0 2006.182.08:05:41.87#ibcon#about to read 3, iclass 19, count 0 2006.182.08:05:41.90#ibcon#read 3, iclass 19, count 0 2006.182.08:05:41.90#ibcon#about to read 4, iclass 19, count 0 2006.182.08:05:41.90#ibcon#read 4, iclass 19, count 0 2006.182.08:05:41.90#ibcon#about to read 5, iclass 19, count 0 2006.182.08:05:41.90#ibcon#read 5, iclass 19, count 0 2006.182.08:05:41.90#ibcon#about to read 6, iclass 19, count 0 2006.182.08:05:41.90#ibcon#read 6, iclass 19, count 0 2006.182.08:05:41.90#ibcon#end of sib2, iclass 19, count 0 2006.182.08:05:41.90#ibcon#*after write, iclass 19, count 0 2006.182.08:05:41.90#ibcon#*before return 0, iclass 19, count 0 2006.182.08:05:41.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:41.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:05:41.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:05:41.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:05:41.90$vc4f8/vblo=5,744.99 2006.182.08:05:41.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.08:05:41.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.08:05:41.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:41.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:41.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:41.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:41.90#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:05:41.90#ibcon#first serial, iclass 21, count 0 2006.182.08:05:41.90#ibcon#enter sib2, iclass 21, count 0 2006.182.08:05:41.90#ibcon#flushed, iclass 21, count 0 2006.182.08:05:41.90#ibcon#about to write, iclass 21, count 0 2006.182.08:05:41.90#ibcon#wrote, iclass 21, count 0 2006.182.08:05:41.90#ibcon#about to read 3, iclass 21, count 0 2006.182.08:05:41.92#ibcon#read 3, iclass 21, count 0 2006.182.08:05:41.92#ibcon#about to read 4, iclass 21, count 0 2006.182.08:05:41.92#ibcon#read 4, iclass 21, count 0 2006.182.08:05:41.92#ibcon#about to read 5, iclass 21, count 0 2006.182.08:05:41.92#ibcon#read 5, iclass 21, count 0 2006.182.08:05:41.92#ibcon#about to read 6, iclass 21, count 0 2006.182.08:05:41.92#ibcon#read 6, iclass 21, count 0 2006.182.08:05:41.92#ibcon#end of sib2, iclass 21, count 0 2006.182.08:05:41.92#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:05:41.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:05:41.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:05:41.92#ibcon#*before write, iclass 21, count 0 2006.182.08:05:41.92#ibcon#enter sib2, iclass 21, count 0 2006.182.08:05:41.92#ibcon#flushed, iclass 21, count 0 2006.182.08:05:41.92#ibcon#about to write, iclass 21, count 0 2006.182.08:05:41.92#ibcon#wrote, iclass 21, count 0 2006.182.08:05:41.92#ibcon#about to read 3, iclass 21, count 0 2006.182.08:05:41.96#ibcon#read 3, iclass 21, count 0 2006.182.08:05:41.96#ibcon#about to read 4, iclass 21, count 0 2006.182.08:05:41.96#ibcon#read 4, iclass 21, count 0 2006.182.08:05:41.96#ibcon#about to read 5, iclass 21, count 0 2006.182.08:05:41.96#ibcon#read 5, iclass 21, count 0 2006.182.08:05:41.96#ibcon#about to read 6, iclass 21, count 0 2006.182.08:05:41.96#ibcon#read 6, iclass 21, count 0 2006.182.08:05:41.96#ibcon#end of sib2, iclass 21, count 0 2006.182.08:05:41.96#ibcon#*after write, iclass 21, count 0 2006.182.08:05:41.96#ibcon#*before return 0, iclass 21, count 0 2006.182.08:05:41.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:41.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:05:41.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:05:41.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:05:41.96$vc4f8/vb=5,4 2006.182.08:05:41.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.182.08:05:41.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.182.08:05:41.96#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:41.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:42.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:42.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:42.02#ibcon#enter wrdev, iclass 23, count 2 2006.182.08:05:42.02#ibcon#first serial, iclass 23, count 2 2006.182.08:05:42.02#ibcon#enter sib2, iclass 23, count 2 2006.182.08:05:42.02#ibcon#flushed, iclass 23, count 2 2006.182.08:05:42.02#ibcon#about to write, iclass 23, count 2 2006.182.08:05:42.02#ibcon#wrote, iclass 23, count 2 2006.182.08:05:42.02#ibcon#about to read 3, iclass 23, count 2 2006.182.08:05:42.04#ibcon#read 3, iclass 23, count 2 2006.182.08:05:42.04#ibcon#about to read 4, iclass 23, count 2 2006.182.08:05:42.04#ibcon#read 4, iclass 23, count 2 2006.182.08:05:42.04#ibcon#about to read 5, iclass 23, count 2 2006.182.08:05:42.04#ibcon#read 5, iclass 23, count 2 2006.182.08:05:42.04#ibcon#about to read 6, iclass 23, count 2 2006.182.08:05:42.04#ibcon#read 6, iclass 23, count 2 2006.182.08:05:42.04#ibcon#end of sib2, iclass 23, count 2 2006.182.08:05:42.04#ibcon#*mode == 0, iclass 23, count 2 2006.182.08:05:42.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.182.08:05:42.04#ibcon#[27=AT05-04\r\n] 2006.182.08:05:42.04#ibcon#*before write, iclass 23, count 2 2006.182.08:05:42.04#ibcon#enter sib2, iclass 23, count 2 2006.182.08:05:42.04#ibcon#flushed, iclass 23, count 2 2006.182.08:05:42.04#ibcon#about to write, iclass 23, count 2 2006.182.08:05:42.04#ibcon#wrote, iclass 23, count 2 2006.182.08:05:42.04#ibcon#about to read 3, iclass 23, count 2 2006.182.08:05:42.07#ibcon#read 3, iclass 23, count 2 2006.182.08:05:42.07#ibcon#about to read 4, iclass 23, count 2 2006.182.08:05:42.07#ibcon#read 4, iclass 23, count 2 2006.182.08:05:42.07#ibcon#about to read 5, iclass 23, count 2 2006.182.08:05:42.07#ibcon#read 5, iclass 23, count 2 2006.182.08:05:42.07#ibcon#about to read 6, iclass 23, count 2 2006.182.08:05:42.07#ibcon#read 6, iclass 23, count 2 2006.182.08:05:42.07#ibcon#end of sib2, iclass 23, count 2 2006.182.08:05:42.07#ibcon#*after write, iclass 23, count 2 2006.182.08:05:42.07#ibcon#*before return 0, iclass 23, count 2 2006.182.08:05:42.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:42.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:05:42.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.182.08:05:42.07#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:42.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:42.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:42.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:42.19#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:05:42.19#ibcon#first serial, iclass 23, count 0 2006.182.08:05:42.19#ibcon#enter sib2, iclass 23, count 0 2006.182.08:05:42.19#ibcon#flushed, iclass 23, count 0 2006.182.08:05:42.19#ibcon#about to write, iclass 23, count 0 2006.182.08:05:42.19#ibcon#wrote, iclass 23, count 0 2006.182.08:05:42.19#ibcon#about to read 3, iclass 23, count 0 2006.182.08:05:42.21#ibcon#read 3, iclass 23, count 0 2006.182.08:05:42.21#ibcon#about to read 4, iclass 23, count 0 2006.182.08:05:42.21#ibcon#read 4, iclass 23, count 0 2006.182.08:05:42.21#ibcon#about to read 5, iclass 23, count 0 2006.182.08:05:42.21#ibcon#read 5, iclass 23, count 0 2006.182.08:05:42.21#ibcon#about to read 6, iclass 23, count 0 2006.182.08:05:42.21#ibcon#read 6, iclass 23, count 0 2006.182.08:05:42.21#ibcon#end of sib2, iclass 23, count 0 2006.182.08:05:42.21#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:05:42.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:05:42.21#ibcon#[27=USB\r\n] 2006.182.08:05:42.21#ibcon#*before write, iclass 23, count 0 2006.182.08:05:42.21#ibcon#enter sib2, iclass 23, count 0 2006.182.08:05:42.21#ibcon#flushed, iclass 23, count 0 2006.182.08:05:42.21#ibcon#about to write, iclass 23, count 0 2006.182.08:05:42.21#ibcon#wrote, iclass 23, count 0 2006.182.08:05:42.21#ibcon#about to read 3, iclass 23, count 0 2006.182.08:05:42.24#ibcon#read 3, iclass 23, count 0 2006.182.08:05:42.24#ibcon#about to read 4, iclass 23, count 0 2006.182.08:05:42.24#ibcon#read 4, iclass 23, count 0 2006.182.08:05:42.24#ibcon#about to read 5, iclass 23, count 0 2006.182.08:05:42.24#ibcon#read 5, iclass 23, count 0 2006.182.08:05:42.24#ibcon#about to read 6, iclass 23, count 0 2006.182.08:05:42.24#ibcon#read 6, iclass 23, count 0 2006.182.08:05:42.24#ibcon#end of sib2, iclass 23, count 0 2006.182.08:05:42.24#ibcon#*after write, iclass 23, count 0 2006.182.08:05:42.24#ibcon#*before return 0, iclass 23, count 0 2006.182.08:05:42.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:42.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:05:42.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:05:42.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:05:42.24$vc4f8/vblo=6,752.99 2006.182.08:05:42.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.08:05:42.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.08:05:42.24#ibcon#ireg 17 cls_cnt 0 2006.182.08:05:42.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:42.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:42.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:42.24#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:05:42.24#ibcon#first serial, iclass 25, count 0 2006.182.08:05:42.24#ibcon#enter sib2, iclass 25, count 0 2006.182.08:05:42.24#ibcon#flushed, iclass 25, count 0 2006.182.08:05:42.24#ibcon#about to write, iclass 25, count 0 2006.182.08:05:42.24#ibcon#wrote, iclass 25, count 0 2006.182.08:05:42.24#ibcon#about to read 3, iclass 25, count 0 2006.182.08:05:42.26#ibcon#read 3, iclass 25, count 0 2006.182.08:05:42.26#ibcon#about to read 4, iclass 25, count 0 2006.182.08:05:42.26#ibcon#read 4, iclass 25, count 0 2006.182.08:05:42.26#ibcon#about to read 5, iclass 25, count 0 2006.182.08:05:42.26#ibcon#read 5, iclass 25, count 0 2006.182.08:05:42.26#ibcon#about to read 6, iclass 25, count 0 2006.182.08:05:42.26#ibcon#read 6, iclass 25, count 0 2006.182.08:05:42.26#ibcon#end of sib2, iclass 25, count 0 2006.182.08:05:42.26#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:05:42.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:05:42.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:05:42.26#ibcon#*before write, iclass 25, count 0 2006.182.08:05:42.26#ibcon#enter sib2, iclass 25, count 0 2006.182.08:05:42.26#ibcon#flushed, iclass 25, count 0 2006.182.08:05:42.26#ibcon#about to write, iclass 25, count 0 2006.182.08:05:42.26#ibcon#wrote, iclass 25, count 0 2006.182.08:05:42.26#ibcon#about to read 3, iclass 25, count 0 2006.182.08:05:42.30#ibcon#read 3, iclass 25, count 0 2006.182.08:05:42.30#ibcon#about to read 4, iclass 25, count 0 2006.182.08:05:42.30#ibcon#read 4, iclass 25, count 0 2006.182.08:05:42.30#ibcon#about to read 5, iclass 25, count 0 2006.182.08:05:42.30#ibcon#read 5, iclass 25, count 0 2006.182.08:05:42.30#ibcon#about to read 6, iclass 25, count 0 2006.182.08:05:42.30#ibcon#read 6, iclass 25, count 0 2006.182.08:05:42.30#ibcon#end of sib2, iclass 25, count 0 2006.182.08:05:42.30#ibcon#*after write, iclass 25, count 0 2006.182.08:05:42.30#ibcon#*before return 0, iclass 25, count 0 2006.182.08:05:42.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:42.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:05:42.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:05:42.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:05:42.30$vc4f8/vb=6,4 2006.182.08:05:42.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.182.08:05:42.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.182.08:05:42.30#ibcon#ireg 11 cls_cnt 2 2006.182.08:05:42.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:42.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:42.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:42.36#ibcon#enter wrdev, iclass 27, count 2 2006.182.08:05:42.36#ibcon#first serial, iclass 27, count 2 2006.182.08:05:42.36#ibcon#enter sib2, iclass 27, count 2 2006.182.08:05:42.36#ibcon#flushed, iclass 27, count 2 2006.182.08:05:42.36#ibcon#about to write, iclass 27, count 2 2006.182.08:05:42.36#ibcon#wrote, iclass 27, count 2 2006.182.08:05:42.36#ibcon#about to read 3, iclass 27, count 2 2006.182.08:05:42.38#ibcon#read 3, iclass 27, count 2 2006.182.08:05:42.38#ibcon#about to read 4, iclass 27, count 2 2006.182.08:05:42.38#ibcon#read 4, iclass 27, count 2 2006.182.08:05:42.38#ibcon#about to read 5, iclass 27, count 2 2006.182.08:05:42.38#ibcon#read 5, iclass 27, count 2 2006.182.08:05:42.38#ibcon#about to read 6, iclass 27, count 2 2006.182.08:05:42.38#ibcon#read 6, iclass 27, count 2 2006.182.08:05:42.38#ibcon#end of sib2, iclass 27, count 2 2006.182.08:05:42.38#ibcon#*mode == 0, iclass 27, count 2 2006.182.08:05:42.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.182.08:05:42.38#ibcon#[27=AT06-04\r\n] 2006.182.08:05:42.38#ibcon#*before write, iclass 27, count 2 2006.182.08:05:42.38#ibcon#enter sib2, iclass 27, count 2 2006.182.08:05:42.38#ibcon#flushed, iclass 27, count 2 2006.182.08:05:42.38#ibcon#about to write, iclass 27, count 2 2006.182.08:05:42.38#ibcon#wrote, iclass 27, count 2 2006.182.08:05:42.38#ibcon#about to read 3, iclass 27, count 2 2006.182.08:05:42.41#ibcon#read 3, iclass 27, count 2 2006.182.08:05:42.41#ibcon#about to read 4, iclass 27, count 2 2006.182.08:05:42.41#ibcon#read 4, iclass 27, count 2 2006.182.08:05:42.41#ibcon#about to read 5, iclass 27, count 2 2006.182.08:05:42.41#ibcon#read 5, iclass 27, count 2 2006.182.08:05:42.41#ibcon#about to read 6, iclass 27, count 2 2006.182.08:05:42.41#ibcon#read 6, iclass 27, count 2 2006.182.08:05:42.41#ibcon#end of sib2, iclass 27, count 2 2006.182.08:05:42.41#ibcon#*after write, iclass 27, count 2 2006.182.08:05:42.41#ibcon#*before return 0, iclass 27, count 2 2006.182.08:05:42.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:42.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:05:42.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.182.08:05:42.41#ibcon#ireg 7 cls_cnt 0 2006.182.08:05:42.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:42.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:42.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:42.53#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:05:42.53#ibcon#first serial, iclass 27, count 0 2006.182.08:05:42.53#ibcon#enter sib2, iclass 27, count 0 2006.182.08:05:42.53#ibcon#flushed, iclass 27, count 0 2006.182.08:05:42.53#ibcon#about to write, iclass 27, count 0 2006.182.08:05:42.53#ibcon#wrote, iclass 27, count 0 2006.182.08:05:42.53#ibcon#about to read 3, iclass 27, count 0 2006.182.08:05:42.55#ibcon#read 3, iclass 27, count 0 2006.182.08:05:42.55#ibcon#about to read 4, iclass 27, count 0 2006.182.08:05:42.55#ibcon#read 4, iclass 27, count 0 2006.182.08:05:42.55#ibcon#about to read 5, iclass 27, count 0 2006.182.08:05:42.55#ibcon#read 5, iclass 27, count 0 2006.182.08:05:42.55#ibcon#about to read 6, iclass 27, count 0 2006.182.08:05:42.55#ibcon#read 6, iclass 27, count 0 2006.182.08:05:42.55#ibcon#end of sib2, iclass 27, count 0 2006.182.08:05:42.55#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:05:42.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:05:42.55#ibcon#[27=USB\r\n] 2006.182.08:05:42.55#ibcon#*before write, iclass 27, count 0 2006.182.08:05:42.55#ibcon#enter sib2, iclass 27, count 0 2006.182.08:05:42.55#ibcon#flushed, iclass 27, count 0 2006.182.08:05:42.55#ibcon#about to write, iclass 27, count 0 2006.182.08:05:42.55#ibcon#wrote, iclass 27, count 0 2006.182.08:05:42.55#ibcon#about to read 3, iclass 27, count 0 2006.182.08:05:42.58#ibcon#read 3, iclass 27, count 0 2006.182.08:05:42.58#ibcon#about to read 4, iclass 27, count 0 2006.182.08:05:42.58#ibcon#read 4, iclass 27, count 0 2006.182.08:05:42.58#ibcon#about to read 5, iclass 27, count 0 2006.182.08:05:42.58#ibcon#read 5, iclass 27, count 0 2006.182.08:05:42.58#ibcon#about to read 6, iclass 27, count 0 2006.182.08:05:42.58#ibcon#read 6, iclass 27, count 0 2006.182.08:05:42.58#ibcon#end of sib2, iclass 27, count 0 2006.182.08:05:42.58#ibcon#*after write, iclass 27, count 0 2006.182.08:05:42.58#ibcon#*before return 0, iclass 27, count 0 2006.182.08:05:42.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:42.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:05:42.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:05:42.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:05:42.58$vc4f8/vabw=wide 2006.182.08:05:42.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.08:05:42.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.08:05:42.58#ibcon#ireg 8 cls_cnt 0 2006.182.08:05:42.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:42.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:42.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:42.58#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:05:42.58#ibcon#first serial, iclass 29, count 0 2006.182.08:05:42.58#ibcon#enter sib2, iclass 29, count 0 2006.182.08:05:42.58#ibcon#flushed, iclass 29, count 0 2006.182.08:05:42.58#ibcon#about to write, iclass 29, count 0 2006.182.08:05:42.58#ibcon#wrote, iclass 29, count 0 2006.182.08:05:42.58#ibcon#about to read 3, iclass 29, count 0 2006.182.08:05:42.60#ibcon#read 3, iclass 29, count 0 2006.182.08:05:42.60#ibcon#about to read 4, iclass 29, count 0 2006.182.08:05:42.60#ibcon#read 4, iclass 29, count 0 2006.182.08:05:42.60#ibcon#about to read 5, iclass 29, count 0 2006.182.08:05:42.60#ibcon#read 5, iclass 29, count 0 2006.182.08:05:42.60#ibcon#about to read 6, iclass 29, count 0 2006.182.08:05:42.60#ibcon#read 6, iclass 29, count 0 2006.182.08:05:42.60#ibcon#end of sib2, iclass 29, count 0 2006.182.08:05:42.60#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:05:42.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:05:42.60#ibcon#[25=BW32\r\n] 2006.182.08:05:42.60#ibcon#*before write, iclass 29, count 0 2006.182.08:05:42.60#ibcon#enter sib2, iclass 29, count 0 2006.182.08:05:42.60#ibcon#flushed, iclass 29, count 0 2006.182.08:05:42.60#ibcon#about to write, iclass 29, count 0 2006.182.08:05:42.60#ibcon#wrote, iclass 29, count 0 2006.182.08:05:42.60#ibcon#about to read 3, iclass 29, count 0 2006.182.08:05:42.63#ibcon#read 3, iclass 29, count 0 2006.182.08:05:42.63#ibcon#about to read 4, iclass 29, count 0 2006.182.08:05:42.63#ibcon#read 4, iclass 29, count 0 2006.182.08:05:42.63#ibcon#about to read 5, iclass 29, count 0 2006.182.08:05:42.63#ibcon#read 5, iclass 29, count 0 2006.182.08:05:42.63#ibcon#about to read 6, iclass 29, count 0 2006.182.08:05:42.63#ibcon#read 6, iclass 29, count 0 2006.182.08:05:42.63#ibcon#end of sib2, iclass 29, count 0 2006.182.08:05:42.63#ibcon#*after write, iclass 29, count 0 2006.182.08:05:42.63#ibcon#*before return 0, iclass 29, count 0 2006.182.08:05:42.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:42.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:05:42.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:05:42.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:05:42.63$vc4f8/vbbw=wide 2006.182.08:05:42.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.08:05:42.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.08:05:42.63#ibcon#ireg 8 cls_cnt 0 2006.182.08:05:42.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:05:42.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:05:42.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:05:42.71#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:05:42.71#ibcon#first serial, iclass 31, count 0 2006.182.08:05:42.71#ibcon#enter sib2, iclass 31, count 0 2006.182.08:05:42.71#ibcon#flushed, iclass 31, count 0 2006.182.08:05:42.71#ibcon#about to write, iclass 31, count 0 2006.182.08:05:42.71#ibcon#wrote, iclass 31, count 0 2006.182.08:05:42.71#ibcon#about to read 3, iclass 31, count 0 2006.182.08:05:42.73#ibcon#read 3, iclass 31, count 0 2006.182.08:05:42.73#ibcon#about to read 4, iclass 31, count 0 2006.182.08:05:42.73#ibcon#read 4, iclass 31, count 0 2006.182.08:05:42.73#ibcon#about to read 5, iclass 31, count 0 2006.182.08:05:42.73#ibcon#read 5, iclass 31, count 0 2006.182.08:05:42.73#ibcon#about to read 6, iclass 31, count 0 2006.182.08:05:42.73#ibcon#read 6, iclass 31, count 0 2006.182.08:05:42.73#ibcon#end of sib2, iclass 31, count 0 2006.182.08:05:42.73#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:05:42.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:05:42.73#ibcon#[27=BW32\r\n] 2006.182.08:05:42.73#ibcon#*before write, iclass 31, count 0 2006.182.08:05:42.73#ibcon#enter sib2, iclass 31, count 0 2006.182.08:05:42.73#ibcon#flushed, iclass 31, count 0 2006.182.08:05:42.73#ibcon#about to write, iclass 31, count 0 2006.182.08:05:42.73#ibcon#wrote, iclass 31, count 0 2006.182.08:05:42.73#ibcon#about to read 3, iclass 31, count 0 2006.182.08:05:42.75#ibcon#read 3, iclass 31, count 0 2006.182.08:05:42.75#ibcon#about to read 4, iclass 31, count 0 2006.182.08:05:42.75#ibcon#read 4, iclass 31, count 0 2006.182.08:05:42.75#ibcon#about to read 5, iclass 31, count 0 2006.182.08:05:42.75#ibcon#read 5, iclass 31, count 0 2006.182.08:05:42.75#ibcon#about to read 6, iclass 31, count 0 2006.182.08:05:42.75#ibcon#read 6, iclass 31, count 0 2006.182.08:05:42.75#ibcon#end of sib2, iclass 31, count 0 2006.182.08:05:42.75#ibcon#*after write, iclass 31, count 0 2006.182.08:05:42.75#ibcon#*before return 0, iclass 31, count 0 2006.182.08:05:42.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:05:42.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:05:42.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:05:42.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:05:42.75$4f8m12a/ifd4f 2006.182.08:05:42.75$ifd4f/lo= 2006.182.08:05:42.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:05:42.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:05:42.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:05:42.75$ifd4f/patch= 2006.182.08:05:42.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:05:42.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:05:42.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:05:42.75$4f8m12a/"form=m,16.000,1:2 2006.182.08:05:42.75$4f8m12a/"tpicd 2006.182.08:05:42.75$4f8m12a/echo=off 2006.182.08:05:42.75$4f8m12a/xlog=off 2006.182.08:05:42.75:!2006.182.08:06:10 2006.182.08:05:50.14#trakl#Source acquired 2006.182.08:05:51.14#flagr#flagr/antenna,acquired 2006.182.08:06:10.00:preob 2006.182.08:06:10.14/onsource/TRACKING 2006.182.08:06:10.14:!2006.182.08:06:20 2006.182.08:06:20.00:data_valid=on 2006.182.08:06:20.00:midob 2006.182.08:06:21.14/onsource/TRACKING 2006.182.08:06:21.14/wx/27.87,1002.9,81 2006.182.08:06:21.21/cable/+6.4647E-03 2006.182.08:06:22.30/va/01,08,usb,yes,28,29 2006.182.08:06:22.30/va/02,07,usb,yes,28,30 2006.182.08:06:22.30/va/03,06,usb,yes,30,30 2006.182.08:06:22.30/va/04,07,usb,yes,29,31 2006.182.08:06:22.30/va/05,07,usb,yes,30,32 2006.182.08:06:22.30/va/06,06,usb,yes,29,29 2006.182.08:06:22.30/va/07,06,usb,yes,30,29 2006.182.08:06:22.30/va/08,07,usb,yes,28,27 2006.182.08:06:22.53/valo/01,532.99,yes,locked 2006.182.08:06:22.53/valo/02,572.99,yes,locked 2006.182.08:06:22.53/valo/03,672.99,yes,locked 2006.182.08:06:22.53/valo/04,832.99,yes,locked 2006.182.08:06:22.53/valo/05,652.99,yes,locked 2006.182.08:06:22.53/valo/06,772.99,yes,locked 2006.182.08:06:22.53/valo/07,832.99,yes,locked 2006.182.08:06:22.53/valo/08,852.99,yes,locked 2006.182.08:06:23.62/vb/01,04,usb,yes,29,27 2006.182.08:06:23.62/vb/02,04,usb,yes,30,32 2006.182.08:06:23.62/vb/03,04,usb,yes,27,31 2006.182.08:06:23.62/vb/04,04,usb,yes,28,28 2006.182.08:06:23.62/vb/05,04,usb,yes,26,30 2006.182.08:06:23.62/vb/06,04,usb,yes,27,30 2006.182.08:06:23.62/vb/07,04,usb,yes,29,29 2006.182.08:06:23.62/vb/08,04,usb,yes,27,30 2006.182.08:06:23.85/vblo/01,632.99,yes,locked 2006.182.08:06:23.85/vblo/02,640.99,yes,locked 2006.182.08:06:23.85/vblo/03,656.99,yes,locked 2006.182.08:06:23.85/vblo/04,712.99,yes,locked 2006.182.08:06:23.85/vblo/05,744.99,yes,locked 2006.182.08:06:23.85/vblo/06,752.99,yes,locked 2006.182.08:06:23.85/vblo/07,734.99,yes,locked 2006.182.08:06:23.85/vblo/08,744.99,yes,locked 2006.182.08:06:24.00/vabw/8 2006.182.08:06:24.15/vbbw/8 2006.182.08:06:24.24/xfe/off,on,15.5 2006.182.08:06:24.63/ifatt/23,28,28,28 2006.182.08:06:25.07/fmout-gps/S +3.44E-07 2006.182.08:06:25.15:!2006.182.08:07:20 2006.182.08:07:20.00:data_valid=off 2006.182.08:07:20.01:postob 2006.182.08:07:20.16/cable/+6.4656E-03 2006.182.08:07:20.17/wx/27.87,1002.9,82 2006.182.08:07:21.07/fmout-gps/S +3.44E-07 2006.182.08:07:21.08:scan_name=182-0808,k06182,60 2006.182.08:07:21.08:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.182.08:07:21.14#flagr#flagr/antenna,new-source 2006.182.08:07:22.14:checkk5 2006.182.08:07:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:07:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:07:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:07:23.66/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:07:24.03/chk_obsdata//k5ts1/T1820806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:07:24.39/chk_obsdata//k5ts2/T1820806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:07:24.77/chk_obsdata//k5ts3/T1820806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:07:25.14/chk_obsdata//k5ts4/T1820806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:07:25.84/k5log//k5ts1_log_newline 2006.182.08:07:26.52/k5log//k5ts2_log_newline 2006.182.08:07:27.21/k5log//k5ts3_log_newline 2006.182.08:07:27.90/k5log//k5ts4_log_newline 2006.182.08:07:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:07:27.92:4f8m12a=2 2006.182.08:07:27.92$4f8m12a/echo=on 2006.182.08:07:27.92$4f8m12a/pcalon 2006.182.08:07:27.92$pcalon/"no phase cal control is implemented here 2006.182.08:07:27.92$4f8m12a/"tpicd=stop 2006.182.08:07:27.92$4f8m12a/vc4f8 2006.182.08:07:27.92$vc4f8/valo=1,532.99 2006.182.08:07:27.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.08:07:27.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.08:07:27.92#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:27.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:27.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:27.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:27.92#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:07:27.92#ibcon#first serial, iclass 38, count 0 2006.182.08:07:27.92#ibcon#enter sib2, iclass 38, count 0 2006.182.08:07:27.92#ibcon#flushed, iclass 38, count 0 2006.182.08:07:27.92#ibcon#about to write, iclass 38, count 0 2006.182.08:07:27.92#ibcon#wrote, iclass 38, count 0 2006.182.08:07:27.92#ibcon#about to read 3, iclass 38, count 0 2006.182.08:07:27.97#ibcon#read 3, iclass 38, count 0 2006.182.08:07:27.97#ibcon#about to read 4, iclass 38, count 0 2006.182.08:07:27.97#ibcon#read 4, iclass 38, count 0 2006.182.08:07:27.97#ibcon#about to read 5, iclass 38, count 0 2006.182.08:07:27.97#ibcon#read 5, iclass 38, count 0 2006.182.08:07:27.97#ibcon#about to read 6, iclass 38, count 0 2006.182.08:07:27.97#ibcon#read 6, iclass 38, count 0 2006.182.08:07:27.97#ibcon#end of sib2, iclass 38, count 0 2006.182.08:07:27.97#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:07:27.97#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:07:27.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:07:27.97#ibcon#*before write, iclass 38, count 0 2006.182.08:07:27.97#ibcon#enter sib2, iclass 38, count 0 2006.182.08:07:27.97#ibcon#flushed, iclass 38, count 0 2006.182.08:07:27.97#ibcon#about to write, iclass 38, count 0 2006.182.08:07:27.97#ibcon#wrote, iclass 38, count 0 2006.182.08:07:27.97#ibcon#about to read 3, iclass 38, count 0 2006.182.08:07:28.01#ibcon#read 3, iclass 38, count 0 2006.182.08:07:28.01#ibcon#about to read 4, iclass 38, count 0 2006.182.08:07:28.01#ibcon#read 4, iclass 38, count 0 2006.182.08:07:28.01#ibcon#about to read 5, iclass 38, count 0 2006.182.08:07:28.01#ibcon#read 5, iclass 38, count 0 2006.182.08:07:28.01#ibcon#about to read 6, iclass 38, count 0 2006.182.08:07:28.01#ibcon#read 6, iclass 38, count 0 2006.182.08:07:28.01#ibcon#end of sib2, iclass 38, count 0 2006.182.08:07:28.01#ibcon#*after write, iclass 38, count 0 2006.182.08:07:28.01#ibcon#*before return 0, iclass 38, count 0 2006.182.08:07:28.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:28.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:28.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:07:28.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:07:28.01$vc4f8/va=1,8 2006.182.08:07:28.01#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.08:07:28.01#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.08:07:28.01#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:28.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:28.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:28.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:28.01#ibcon#enter wrdev, iclass 40, count 2 2006.182.08:07:28.01#ibcon#first serial, iclass 40, count 2 2006.182.08:07:28.01#ibcon#enter sib2, iclass 40, count 2 2006.182.08:07:28.01#ibcon#flushed, iclass 40, count 2 2006.182.08:07:28.01#ibcon#about to write, iclass 40, count 2 2006.182.08:07:28.01#ibcon#wrote, iclass 40, count 2 2006.182.08:07:28.01#ibcon#about to read 3, iclass 40, count 2 2006.182.08:07:28.03#ibcon#read 3, iclass 40, count 2 2006.182.08:07:28.03#ibcon#about to read 4, iclass 40, count 2 2006.182.08:07:28.03#ibcon#read 4, iclass 40, count 2 2006.182.08:07:28.03#ibcon#about to read 5, iclass 40, count 2 2006.182.08:07:28.03#ibcon#read 5, iclass 40, count 2 2006.182.08:07:28.03#ibcon#about to read 6, iclass 40, count 2 2006.182.08:07:28.03#ibcon#read 6, iclass 40, count 2 2006.182.08:07:28.03#ibcon#end of sib2, iclass 40, count 2 2006.182.08:07:28.03#ibcon#*mode == 0, iclass 40, count 2 2006.182.08:07:28.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.08:07:28.03#ibcon#[25=AT01-08\r\n] 2006.182.08:07:28.03#ibcon#*before write, iclass 40, count 2 2006.182.08:07:28.03#ibcon#enter sib2, iclass 40, count 2 2006.182.08:07:28.03#ibcon#flushed, iclass 40, count 2 2006.182.08:07:28.03#ibcon#about to write, iclass 40, count 2 2006.182.08:07:28.03#ibcon#wrote, iclass 40, count 2 2006.182.08:07:28.03#ibcon#about to read 3, iclass 40, count 2 2006.182.08:07:28.06#ibcon#read 3, iclass 40, count 2 2006.182.08:07:28.06#ibcon#about to read 4, iclass 40, count 2 2006.182.08:07:28.06#ibcon#read 4, iclass 40, count 2 2006.182.08:07:28.06#ibcon#about to read 5, iclass 40, count 2 2006.182.08:07:28.06#ibcon#read 5, iclass 40, count 2 2006.182.08:07:28.06#ibcon#about to read 6, iclass 40, count 2 2006.182.08:07:28.06#ibcon#read 6, iclass 40, count 2 2006.182.08:07:28.06#ibcon#end of sib2, iclass 40, count 2 2006.182.08:07:28.06#ibcon#*after write, iclass 40, count 2 2006.182.08:07:28.06#ibcon#*before return 0, iclass 40, count 2 2006.182.08:07:28.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:28.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:28.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.08:07:28.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:28.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:28.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:28.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:28.18#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:07:28.18#ibcon#first serial, iclass 40, count 0 2006.182.08:07:28.18#ibcon#enter sib2, iclass 40, count 0 2006.182.08:07:28.18#ibcon#flushed, iclass 40, count 0 2006.182.08:07:28.18#ibcon#about to write, iclass 40, count 0 2006.182.08:07:28.18#ibcon#wrote, iclass 40, count 0 2006.182.08:07:28.18#ibcon#about to read 3, iclass 40, count 0 2006.182.08:07:28.20#ibcon#read 3, iclass 40, count 0 2006.182.08:07:28.20#ibcon#about to read 4, iclass 40, count 0 2006.182.08:07:28.20#ibcon#read 4, iclass 40, count 0 2006.182.08:07:28.20#ibcon#about to read 5, iclass 40, count 0 2006.182.08:07:28.20#ibcon#read 5, iclass 40, count 0 2006.182.08:07:28.20#ibcon#about to read 6, iclass 40, count 0 2006.182.08:07:28.20#ibcon#read 6, iclass 40, count 0 2006.182.08:07:28.20#ibcon#end of sib2, iclass 40, count 0 2006.182.08:07:28.20#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:07:28.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:07:28.20#ibcon#[25=USB\r\n] 2006.182.08:07:28.20#ibcon#*before write, iclass 40, count 0 2006.182.08:07:28.20#ibcon#enter sib2, iclass 40, count 0 2006.182.08:07:28.20#ibcon#flushed, iclass 40, count 0 2006.182.08:07:28.20#ibcon#about to write, iclass 40, count 0 2006.182.08:07:28.20#ibcon#wrote, iclass 40, count 0 2006.182.08:07:28.20#ibcon#about to read 3, iclass 40, count 0 2006.182.08:07:28.23#ibcon#read 3, iclass 40, count 0 2006.182.08:07:28.23#ibcon#about to read 4, iclass 40, count 0 2006.182.08:07:28.23#ibcon#read 4, iclass 40, count 0 2006.182.08:07:28.23#ibcon#about to read 5, iclass 40, count 0 2006.182.08:07:28.23#ibcon#read 5, iclass 40, count 0 2006.182.08:07:28.23#ibcon#about to read 6, iclass 40, count 0 2006.182.08:07:28.23#ibcon#read 6, iclass 40, count 0 2006.182.08:07:28.23#ibcon#end of sib2, iclass 40, count 0 2006.182.08:07:28.23#ibcon#*after write, iclass 40, count 0 2006.182.08:07:28.23#ibcon#*before return 0, iclass 40, count 0 2006.182.08:07:28.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:28.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:28.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:07:28.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:07:28.23$vc4f8/valo=2,572.99 2006.182.08:07:28.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.08:07:28.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.08:07:28.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:28.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:28.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:28.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:28.23#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:07:28.23#ibcon#first serial, iclass 4, count 0 2006.182.08:07:28.23#ibcon#enter sib2, iclass 4, count 0 2006.182.08:07:28.23#ibcon#flushed, iclass 4, count 0 2006.182.08:07:28.23#ibcon#about to write, iclass 4, count 0 2006.182.08:07:28.23#ibcon#wrote, iclass 4, count 0 2006.182.08:07:28.23#ibcon#about to read 3, iclass 4, count 0 2006.182.08:07:28.25#ibcon#read 3, iclass 4, count 0 2006.182.08:07:28.25#ibcon#about to read 4, iclass 4, count 0 2006.182.08:07:28.25#ibcon#read 4, iclass 4, count 0 2006.182.08:07:28.25#ibcon#about to read 5, iclass 4, count 0 2006.182.08:07:28.25#ibcon#read 5, iclass 4, count 0 2006.182.08:07:28.25#ibcon#about to read 6, iclass 4, count 0 2006.182.08:07:28.25#ibcon#read 6, iclass 4, count 0 2006.182.08:07:28.25#ibcon#end of sib2, iclass 4, count 0 2006.182.08:07:28.25#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:07:28.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:07:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:07:28.25#ibcon#*before write, iclass 4, count 0 2006.182.08:07:28.25#ibcon#enter sib2, iclass 4, count 0 2006.182.08:07:28.25#ibcon#flushed, iclass 4, count 0 2006.182.08:07:28.25#ibcon#about to write, iclass 4, count 0 2006.182.08:07:28.25#ibcon#wrote, iclass 4, count 0 2006.182.08:07:28.25#ibcon#about to read 3, iclass 4, count 0 2006.182.08:07:28.29#ibcon#read 3, iclass 4, count 0 2006.182.08:07:28.29#ibcon#about to read 4, iclass 4, count 0 2006.182.08:07:28.29#ibcon#read 4, iclass 4, count 0 2006.182.08:07:28.29#ibcon#about to read 5, iclass 4, count 0 2006.182.08:07:28.29#ibcon#read 5, iclass 4, count 0 2006.182.08:07:28.29#ibcon#about to read 6, iclass 4, count 0 2006.182.08:07:28.29#ibcon#read 6, iclass 4, count 0 2006.182.08:07:28.29#ibcon#end of sib2, iclass 4, count 0 2006.182.08:07:28.29#ibcon#*after write, iclass 4, count 0 2006.182.08:07:28.29#ibcon#*before return 0, iclass 4, count 0 2006.182.08:07:28.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:28.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:28.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:07:28.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:07:28.29$vc4f8/va=2,7 2006.182.08:07:28.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.08:07:28.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.08:07:28.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:28.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:28.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:28.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:28.36#ibcon#enter wrdev, iclass 6, count 2 2006.182.08:07:28.36#ibcon#first serial, iclass 6, count 2 2006.182.08:07:28.36#ibcon#enter sib2, iclass 6, count 2 2006.182.08:07:28.36#ibcon#flushed, iclass 6, count 2 2006.182.08:07:28.36#ibcon#about to write, iclass 6, count 2 2006.182.08:07:28.36#ibcon#wrote, iclass 6, count 2 2006.182.08:07:28.36#ibcon#about to read 3, iclass 6, count 2 2006.182.08:07:28.37#ibcon#read 3, iclass 6, count 2 2006.182.08:07:28.37#ibcon#about to read 4, iclass 6, count 2 2006.182.08:07:28.37#ibcon#read 4, iclass 6, count 2 2006.182.08:07:28.37#ibcon#about to read 5, iclass 6, count 2 2006.182.08:07:28.37#ibcon#read 5, iclass 6, count 2 2006.182.08:07:28.38#ibcon#about to read 6, iclass 6, count 2 2006.182.08:07:28.38#ibcon#read 6, iclass 6, count 2 2006.182.08:07:28.38#ibcon#end of sib2, iclass 6, count 2 2006.182.08:07:28.38#ibcon#*mode == 0, iclass 6, count 2 2006.182.08:07:28.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.08:07:28.38#ibcon#[25=AT02-07\r\n] 2006.182.08:07:28.38#ibcon#*before write, iclass 6, count 2 2006.182.08:07:28.38#ibcon#enter sib2, iclass 6, count 2 2006.182.08:07:28.38#ibcon#flushed, iclass 6, count 2 2006.182.08:07:28.38#ibcon#about to write, iclass 6, count 2 2006.182.08:07:28.38#ibcon#wrote, iclass 6, count 2 2006.182.08:07:28.38#ibcon#about to read 3, iclass 6, count 2 2006.182.08:07:28.40#ibcon#read 3, iclass 6, count 2 2006.182.08:07:28.40#ibcon#about to read 4, iclass 6, count 2 2006.182.08:07:28.40#ibcon#read 4, iclass 6, count 2 2006.182.08:07:28.40#ibcon#about to read 5, iclass 6, count 2 2006.182.08:07:28.40#ibcon#read 5, iclass 6, count 2 2006.182.08:07:28.40#ibcon#about to read 6, iclass 6, count 2 2006.182.08:07:28.40#ibcon#read 6, iclass 6, count 2 2006.182.08:07:28.40#ibcon#end of sib2, iclass 6, count 2 2006.182.08:07:28.40#ibcon#*after write, iclass 6, count 2 2006.182.08:07:28.40#ibcon#*before return 0, iclass 6, count 2 2006.182.08:07:28.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:28.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:28.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.08:07:28.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:28.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:28.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:28.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:28.52#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:07:28.52#ibcon#first serial, iclass 6, count 0 2006.182.08:07:28.52#ibcon#enter sib2, iclass 6, count 0 2006.182.08:07:28.52#ibcon#flushed, iclass 6, count 0 2006.182.08:07:28.52#ibcon#about to write, iclass 6, count 0 2006.182.08:07:28.52#ibcon#wrote, iclass 6, count 0 2006.182.08:07:28.52#ibcon#about to read 3, iclass 6, count 0 2006.182.08:07:28.54#ibcon#read 3, iclass 6, count 0 2006.182.08:07:28.54#ibcon#about to read 4, iclass 6, count 0 2006.182.08:07:28.54#ibcon#read 4, iclass 6, count 0 2006.182.08:07:28.54#ibcon#about to read 5, iclass 6, count 0 2006.182.08:07:28.54#ibcon#read 5, iclass 6, count 0 2006.182.08:07:28.54#ibcon#about to read 6, iclass 6, count 0 2006.182.08:07:28.54#ibcon#read 6, iclass 6, count 0 2006.182.08:07:28.54#ibcon#end of sib2, iclass 6, count 0 2006.182.08:07:28.54#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:07:28.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:07:28.54#ibcon#[25=USB\r\n] 2006.182.08:07:28.54#ibcon#*before write, iclass 6, count 0 2006.182.08:07:28.54#ibcon#enter sib2, iclass 6, count 0 2006.182.08:07:28.54#ibcon#flushed, iclass 6, count 0 2006.182.08:07:28.54#ibcon#about to write, iclass 6, count 0 2006.182.08:07:28.54#ibcon#wrote, iclass 6, count 0 2006.182.08:07:28.54#ibcon#about to read 3, iclass 6, count 0 2006.182.08:07:28.57#ibcon#read 3, iclass 6, count 0 2006.182.08:07:28.57#ibcon#about to read 4, iclass 6, count 0 2006.182.08:07:28.57#ibcon#read 4, iclass 6, count 0 2006.182.08:07:28.57#ibcon#about to read 5, iclass 6, count 0 2006.182.08:07:28.57#ibcon#read 5, iclass 6, count 0 2006.182.08:07:28.57#ibcon#about to read 6, iclass 6, count 0 2006.182.08:07:28.57#ibcon#read 6, iclass 6, count 0 2006.182.08:07:28.57#ibcon#end of sib2, iclass 6, count 0 2006.182.08:07:28.57#ibcon#*after write, iclass 6, count 0 2006.182.08:07:28.57#ibcon#*before return 0, iclass 6, count 0 2006.182.08:07:28.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:28.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:28.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:07:28.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:07:28.57$vc4f8/valo=3,672.99 2006.182.08:07:28.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.08:07:28.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.08:07:28.57#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:28.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:28.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:28.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:28.57#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:07:28.57#ibcon#first serial, iclass 10, count 0 2006.182.08:07:28.57#ibcon#enter sib2, iclass 10, count 0 2006.182.08:07:28.57#ibcon#flushed, iclass 10, count 0 2006.182.08:07:28.57#ibcon#about to write, iclass 10, count 0 2006.182.08:07:28.57#ibcon#wrote, iclass 10, count 0 2006.182.08:07:28.57#ibcon#about to read 3, iclass 10, count 0 2006.182.08:07:28.60#ibcon#read 3, iclass 10, count 0 2006.182.08:07:28.60#ibcon#about to read 4, iclass 10, count 0 2006.182.08:07:28.60#ibcon#read 4, iclass 10, count 0 2006.182.08:07:28.60#ibcon#about to read 5, iclass 10, count 0 2006.182.08:07:28.60#ibcon#read 5, iclass 10, count 0 2006.182.08:07:28.60#ibcon#about to read 6, iclass 10, count 0 2006.182.08:07:28.60#ibcon#read 6, iclass 10, count 0 2006.182.08:07:28.60#ibcon#end of sib2, iclass 10, count 0 2006.182.08:07:28.60#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:07:28.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:07:28.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:07:28.60#ibcon#*before write, iclass 10, count 0 2006.182.08:07:28.60#ibcon#enter sib2, iclass 10, count 0 2006.182.08:07:28.60#ibcon#flushed, iclass 10, count 0 2006.182.08:07:28.60#ibcon#about to write, iclass 10, count 0 2006.182.08:07:28.60#ibcon#wrote, iclass 10, count 0 2006.182.08:07:28.60#ibcon#about to read 3, iclass 10, count 0 2006.182.08:07:28.64#ibcon#read 3, iclass 10, count 0 2006.182.08:07:28.64#ibcon#about to read 4, iclass 10, count 0 2006.182.08:07:28.64#ibcon#read 4, iclass 10, count 0 2006.182.08:07:28.64#ibcon#about to read 5, iclass 10, count 0 2006.182.08:07:28.64#ibcon#read 5, iclass 10, count 0 2006.182.08:07:28.64#ibcon#about to read 6, iclass 10, count 0 2006.182.08:07:28.64#ibcon#read 6, iclass 10, count 0 2006.182.08:07:28.64#ibcon#end of sib2, iclass 10, count 0 2006.182.08:07:28.64#ibcon#*after write, iclass 10, count 0 2006.182.08:07:28.64#ibcon#*before return 0, iclass 10, count 0 2006.182.08:07:28.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:28.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:28.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:07:28.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:07:28.64$vc4f8/va=3,6 2006.182.08:07:28.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.08:07:28.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.08:07:28.64#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:28.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:28.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:28.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:28.69#ibcon#enter wrdev, iclass 12, count 2 2006.182.08:07:28.69#ibcon#first serial, iclass 12, count 2 2006.182.08:07:28.69#ibcon#enter sib2, iclass 12, count 2 2006.182.08:07:28.69#ibcon#flushed, iclass 12, count 2 2006.182.08:07:28.69#ibcon#about to write, iclass 12, count 2 2006.182.08:07:28.69#ibcon#wrote, iclass 12, count 2 2006.182.08:07:28.69#ibcon#about to read 3, iclass 12, count 2 2006.182.08:07:28.71#ibcon#read 3, iclass 12, count 2 2006.182.08:07:28.71#ibcon#about to read 4, iclass 12, count 2 2006.182.08:07:28.71#ibcon#read 4, iclass 12, count 2 2006.182.08:07:28.71#ibcon#about to read 5, iclass 12, count 2 2006.182.08:07:28.71#ibcon#read 5, iclass 12, count 2 2006.182.08:07:28.71#ibcon#about to read 6, iclass 12, count 2 2006.182.08:07:28.71#ibcon#read 6, iclass 12, count 2 2006.182.08:07:28.71#ibcon#end of sib2, iclass 12, count 2 2006.182.08:07:28.71#ibcon#*mode == 0, iclass 12, count 2 2006.182.08:07:28.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.08:07:28.71#ibcon#[25=AT03-06\r\n] 2006.182.08:07:28.71#ibcon#*before write, iclass 12, count 2 2006.182.08:07:28.71#ibcon#enter sib2, iclass 12, count 2 2006.182.08:07:28.71#ibcon#flushed, iclass 12, count 2 2006.182.08:07:28.71#ibcon#about to write, iclass 12, count 2 2006.182.08:07:28.71#ibcon#wrote, iclass 12, count 2 2006.182.08:07:28.71#ibcon#about to read 3, iclass 12, count 2 2006.182.08:07:28.74#ibcon#read 3, iclass 12, count 2 2006.182.08:07:28.74#ibcon#about to read 4, iclass 12, count 2 2006.182.08:07:28.74#ibcon#read 4, iclass 12, count 2 2006.182.08:07:28.74#ibcon#about to read 5, iclass 12, count 2 2006.182.08:07:28.74#ibcon#read 5, iclass 12, count 2 2006.182.08:07:28.74#ibcon#about to read 6, iclass 12, count 2 2006.182.08:07:28.74#ibcon#read 6, iclass 12, count 2 2006.182.08:07:28.74#ibcon#end of sib2, iclass 12, count 2 2006.182.08:07:28.74#ibcon#*after write, iclass 12, count 2 2006.182.08:07:28.74#ibcon#*before return 0, iclass 12, count 2 2006.182.08:07:28.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:28.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:28.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.08:07:28.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:28.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:28.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:28.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:28.86#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:07:28.86#ibcon#first serial, iclass 12, count 0 2006.182.08:07:28.86#ibcon#enter sib2, iclass 12, count 0 2006.182.08:07:28.86#ibcon#flushed, iclass 12, count 0 2006.182.08:07:28.86#ibcon#about to write, iclass 12, count 0 2006.182.08:07:28.86#ibcon#wrote, iclass 12, count 0 2006.182.08:07:28.86#ibcon#about to read 3, iclass 12, count 0 2006.182.08:07:28.88#ibcon#read 3, iclass 12, count 0 2006.182.08:07:28.88#ibcon#about to read 4, iclass 12, count 0 2006.182.08:07:28.88#ibcon#read 4, iclass 12, count 0 2006.182.08:07:28.88#ibcon#about to read 5, iclass 12, count 0 2006.182.08:07:28.88#ibcon#read 5, iclass 12, count 0 2006.182.08:07:28.88#ibcon#about to read 6, iclass 12, count 0 2006.182.08:07:28.88#ibcon#read 6, iclass 12, count 0 2006.182.08:07:28.88#ibcon#end of sib2, iclass 12, count 0 2006.182.08:07:28.88#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:07:28.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:07:28.88#ibcon#[25=USB\r\n] 2006.182.08:07:28.88#ibcon#*before write, iclass 12, count 0 2006.182.08:07:28.88#ibcon#enter sib2, iclass 12, count 0 2006.182.08:07:28.88#ibcon#flushed, iclass 12, count 0 2006.182.08:07:28.88#ibcon#about to write, iclass 12, count 0 2006.182.08:07:28.88#ibcon#wrote, iclass 12, count 0 2006.182.08:07:28.88#ibcon#about to read 3, iclass 12, count 0 2006.182.08:07:28.91#ibcon#read 3, iclass 12, count 0 2006.182.08:07:28.91#ibcon#about to read 4, iclass 12, count 0 2006.182.08:07:28.91#ibcon#read 4, iclass 12, count 0 2006.182.08:07:28.91#ibcon#about to read 5, iclass 12, count 0 2006.182.08:07:28.91#ibcon#read 5, iclass 12, count 0 2006.182.08:07:28.91#ibcon#about to read 6, iclass 12, count 0 2006.182.08:07:28.91#ibcon#read 6, iclass 12, count 0 2006.182.08:07:28.91#ibcon#end of sib2, iclass 12, count 0 2006.182.08:07:28.91#ibcon#*after write, iclass 12, count 0 2006.182.08:07:28.91#ibcon#*before return 0, iclass 12, count 0 2006.182.08:07:28.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:28.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:28.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:07:28.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:07:28.91$vc4f8/valo=4,832.99 2006.182.08:07:28.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.08:07:28.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.08:07:28.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:28.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:28.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:28.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:28.91#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:07:28.91#ibcon#first serial, iclass 14, count 0 2006.182.08:07:28.91#ibcon#enter sib2, iclass 14, count 0 2006.182.08:07:28.91#ibcon#flushed, iclass 14, count 0 2006.182.08:07:28.91#ibcon#about to write, iclass 14, count 0 2006.182.08:07:28.91#ibcon#wrote, iclass 14, count 0 2006.182.08:07:28.91#ibcon#about to read 3, iclass 14, count 0 2006.182.08:07:28.94#ibcon#read 3, iclass 14, count 0 2006.182.08:07:28.94#ibcon#about to read 4, iclass 14, count 0 2006.182.08:07:28.94#ibcon#read 4, iclass 14, count 0 2006.182.08:07:28.94#ibcon#about to read 5, iclass 14, count 0 2006.182.08:07:28.94#ibcon#read 5, iclass 14, count 0 2006.182.08:07:28.94#ibcon#about to read 6, iclass 14, count 0 2006.182.08:07:28.94#ibcon#read 6, iclass 14, count 0 2006.182.08:07:28.94#ibcon#end of sib2, iclass 14, count 0 2006.182.08:07:28.94#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:07:28.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:07:28.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:07:28.94#ibcon#*before write, iclass 14, count 0 2006.182.08:07:28.94#ibcon#enter sib2, iclass 14, count 0 2006.182.08:07:28.94#ibcon#flushed, iclass 14, count 0 2006.182.08:07:28.94#ibcon#about to write, iclass 14, count 0 2006.182.08:07:28.94#ibcon#wrote, iclass 14, count 0 2006.182.08:07:28.94#ibcon#about to read 3, iclass 14, count 0 2006.182.08:07:28.98#ibcon#read 3, iclass 14, count 0 2006.182.08:07:28.98#ibcon#about to read 4, iclass 14, count 0 2006.182.08:07:28.98#ibcon#read 4, iclass 14, count 0 2006.182.08:07:28.98#ibcon#about to read 5, iclass 14, count 0 2006.182.08:07:28.98#ibcon#read 5, iclass 14, count 0 2006.182.08:07:28.98#ibcon#about to read 6, iclass 14, count 0 2006.182.08:07:28.98#ibcon#read 6, iclass 14, count 0 2006.182.08:07:28.98#ibcon#end of sib2, iclass 14, count 0 2006.182.08:07:28.98#ibcon#*after write, iclass 14, count 0 2006.182.08:07:28.98#ibcon#*before return 0, iclass 14, count 0 2006.182.08:07:28.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:28.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:28.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:07:28.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:07:28.98$vc4f8/va=4,7 2006.182.08:07:28.98#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.08:07:28.98#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.08:07:28.98#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:28.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:29.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:29.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:29.03#ibcon#enter wrdev, iclass 16, count 2 2006.182.08:07:29.03#ibcon#first serial, iclass 16, count 2 2006.182.08:07:29.03#ibcon#enter sib2, iclass 16, count 2 2006.182.08:07:29.03#ibcon#flushed, iclass 16, count 2 2006.182.08:07:29.03#ibcon#about to write, iclass 16, count 2 2006.182.08:07:29.03#ibcon#wrote, iclass 16, count 2 2006.182.08:07:29.03#ibcon#about to read 3, iclass 16, count 2 2006.182.08:07:29.05#ibcon#read 3, iclass 16, count 2 2006.182.08:07:29.05#ibcon#about to read 4, iclass 16, count 2 2006.182.08:07:29.05#ibcon#read 4, iclass 16, count 2 2006.182.08:07:29.05#ibcon#about to read 5, iclass 16, count 2 2006.182.08:07:29.05#ibcon#read 5, iclass 16, count 2 2006.182.08:07:29.05#ibcon#about to read 6, iclass 16, count 2 2006.182.08:07:29.05#ibcon#read 6, iclass 16, count 2 2006.182.08:07:29.05#ibcon#end of sib2, iclass 16, count 2 2006.182.08:07:29.05#ibcon#*mode == 0, iclass 16, count 2 2006.182.08:07:29.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.08:07:29.05#ibcon#[25=AT04-07\r\n] 2006.182.08:07:29.05#ibcon#*before write, iclass 16, count 2 2006.182.08:07:29.05#ibcon#enter sib2, iclass 16, count 2 2006.182.08:07:29.05#ibcon#flushed, iclass 16, count 2 2006.182.08:07:29.05#ibcon#about to write, iclass 16, count 2 2006.182.08:07:29.05#ibcon#wrote, iclass 16, count 2 2006.182.08:07:29.05#ibcon#about to read 3, iclass 16, count 2 2006.182.08:07:29.08#ibcon#read 3, iclass 16, count 2 2006.182.08:07:29.08#ibcon#about to read 4, iclass 16, count 2 2006.182.08:07:29.08#ibcon#read 4, iclass 16, count 2 2006.182.08:07:29.08#ibcon#about to read 5, iclass 16, count 2 2006.182.08:07:29.08#ibcon#read 5, iclass 16, count 2 2006.182.08:07:29.08#ibcon#about to read 6, iclass 16, count 2 2006.182.08:07:29.08#ibcon#read 6, iclass 16, count 2 2006.182.08:07:29.08#ibcon#end of sib2, iclass 16, count 2 2006.182.08:07:29.08#ibcon#*after write, iclass 16, count 2 2006.182.08:07:29.08#ibcon#*before return 0, iclass 16, count 2 2006.182.08:07:29.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:29.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:29.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.08:07:29.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:29.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:29.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:29.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:29.20#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:07:29.20#ibcon#first serial, iclass 16, count 0 2006.182.08:07:29.20#ibcon#enter sib2, iclass 16, count 0 2006.182.08:07:29.20#ibcon#flushed, iclass 16, count 0 2006.182.08:07:29.20#ibcon#about to write, iclass 16, count 0 2006.182.08:07:29.20#ibcon#wrote, iclass 16, count 0 2006.182.08:07:29.20#ibcon#about to read 3, iclass 16, count 0 2006.182.08:07:29.22#ibcon#read 3, iclass 16, count 0 2006.182.08:07:29.22#ibcon#about to read 4, iclass 16, count 0 2006.182.08:07:29.22#ibcon#read 4, iclass 16, count 0 2006.182.08:07:29.22#ibcon#about to read 5, iclass 16, count 0 2006.182.08:07:29.22#ibcon#read 5, iclass 16, count 0 2006.182.08:07:29.22#ibcon#about to read 6, iclass 16, count 0 2006.182.08:07:29.22#ibcon#read 6, iclass 16, count 0 2006.182.08:07:29.22#ibcon#end of sib2, iclass 16, count 0 2006.182.08:07:29.22#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:07:29.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:07:29.22#ibcon#[25=USB\r\n] 2006.182.08:07:29.22#ibcon#*before write, iclass 16, count 0 2006.182.08:07:29.22#ibcon#enter sib2, iclass 16, count 0 2006.182.08:07:29.22#ibcon#flushed, iclass 16, count 0 2006.182.08:07:29.22#ibcon#about to write, iclass 16, count 0 2006.182.08:07:29.22#ibcon#wrote, iclass 16, count 0 2006.182.08:07:29.22#ibcon#about to read 3, iclass 16, count 0 2006.182.08:07:29.25#ibcon#read 3, iclass 16, count 0 2006.182.08:07:29.25#ibcon#about to read 4, iclass 16, count 0 2006.182.08:07:29.25#ibcon#read 4, iclass 16, count 0 2006.182.08:07:29.25#ibcon#about to read 5, iclass 16, count 0 2006.182.08:07:29.25#ibcon#read 5, iclass 16, count 0 2006.182.08:07:29.25#ibcon#about to read 6, iclass 16, count 0 2006.182.08:07:29.25#ibcon#read 6, iclass 16, count 0 2006.182.08:07:29.25#ibcon#end of sib2, iclass 16, count 0 2006.182.08:07:29.25#ibcon#*after write, iclass 16, count 0 2006.182.08:07:29.25#ibcon#*before return 0, iclass 16, count 0 2006.182.08:07:29.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:29.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:29.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:07:29.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:07:29.25$vc4f8/valo=5,652.99 2006.182.08:07:29.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.08:07:29.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.08:07:29.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:29.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:29.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:29.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:29.25#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:07:29.25#ibcon#first serial, iclass 18, count 0 2006.182.08:07:29.25#ibcon#enter sib2, iclass 18, count 0 2006.182.08:07:29.25#ibcon#flushed, iclass 18, count 0 2006.182.08:07:29.25#ibcon#about to write, iclass 18, count 0 2006.182.08:07:29.25#ibcon#wrote, iclass 18, count 0 2006.182.08:07:29.25#ibcon#about to read 3, iclass 18, count 0 2006.182.08:07:29.27#ibcon#read 3, iclass 18, count 0 2006.182.08:07:29.27#ibcon#about to read 4, iclass 18, count 0 2006.182.08:07:29.27#ibcon#read 4, iclass 18, count 0 2006.182.08:07:29.27#ibcon#about to read 5, iclass 18, count 0 2006.182.08:07:29.27#ibcon#read 5, iclass 18, count 0 2006.182.08:07:29.27#ibcon#about to read 6, iclass 18, count 0 2006.182.08:07:29.27#ibcon#read 6, iclass 18, count 0 2006.182.08:07:29.27#ibcon#end of sib2, iclass 18, count 0 2006.182.08:07:29.27#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:07:29.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:07:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:07:29.27#ibcon#*before write, iclass 18, count 0 2006.182.08:07:29.27#ibcon#enter sib2, iclass 18, count 0 2006.182.08:07:29.27#ibcon#flushed, iclass 18, count 0 2006.182.08:07:29.27#ibcon#about to write, iclass 18, count 0 2006.182.08:07:29.27#ibcon#wrote, iclass 18, count 0 2006.182.08:07:29.27#ibcon#about to read 3, iclass 18, count 0 2006.182.08:07:29.31#ibcon#read 3, iclass 18, count 0 2006.182.08:07:29.31#ibcon#about to read 4, iclass 18, count 0 2006.182.08:07:29.31#ibcon#read 4, iclass 18, count 0 2006.182.08:07:29.31#ibcon#about to read 5, iclass 18, count 0 2006.182.08:07:29.31#ibcon#read 5, iclass 18, count 0 2006.182.08:07:29.31#ibcon#about to read 6, iclass 18, count 0 2006.182.08:07:29.31#ibcon#read 6, iclass 18, count 0 2006.182.08:07:29.31#ibcon#end of sib2, iclass 18, count 0 2006.182.08:07:29.31#ibcon#*after write, iclass 18, count 0 2006.182.08:07:29.31#ibcon#*before return 0, iclass 18, count 0 2006.182.08:07:29.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:29.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:29.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:07:29.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:07:29.31$vc4f8/va=5,7 2006.182.08:07:29.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.08:07:29.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.08:07:29.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:29.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:29.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:29.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:29.37#ibcon#enter wrdev, iclass 20, count 2 2006.182.08:07:29.37#ibcon#first serial, iclass 20, count 2 2006.182.08:07:29.37#ibcon#enter sib2, iclass 20, count 2 2006.182.08:07:29.37#ibcon#flushed, iclass 20, count 2 2006.182.08:07:29.37#ibcon#about to write, iclass 20, count 2 2006.182.08:07:29.37#ibcon#wrote, iclass 20, count 2 2006.182.08:07:29.37#ibcon#about to read 3, iclass 20, count 2 2006.182.08:07:29.39#ibcon#read 3, iclass 20, count 2 2006.182.08:07:29.39#ibcon#about to read 4, iclass 20, count 2 2006.182.08:07:29.39#ibcon#read 4, iclass 20, count 2 2006.182.08:07:29.39#ibcon#about to read 5, iclass 20, count 2 2006.182.08:07:29.39#ibcon#read 5, iclass 20, count 2 2006.182.08:07:29.39#ibcon#about to read 6, iclass 20, count 2 2006.182.08:07:29.39#ibcon#read 6, iclass 20, count 2 2006.182.08:07:29.39#ibcon#end of sib2, iclass 20, count 2 2006.182.08:07:29.39#ibcon#*mode == 0, iclass 20, count 2 2006.182.08:07:29.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.08:07:29.39#ibcon#[25=AT05-07\r\n] 2006.182.08:07:29.39#ibcon#*before write, iclass 20, count 2 2006.182.08:07:29.39#ibcon#enter sib2, iclass 20, count 2 2006.182.08:07:29.39#ibcon#flushed, iclass 20, count 2 2006.182.08:07:29.39#ibcon#about to write, iclass 20, count 2 2006.182.08:07:29.39#ibcon#wrote, iclass 20, count 2 2006.182.08:07:29.39#ibcon#about to read 3, iclass 20, count 2 2006.182.08:07:29.42#ibcon#read 3, iclass 20, count 2 2006.182.08:07:29.42#ibcon#about to read 4, iclass 20, count 2 2006.182.08:07:29.42#ibcon#read 4, iclass 20, count 2 2006.182.08:07:29.42#ibcon#about to read 5, iclass 20, count 2 2006.182.08:07:29.42#ibcon#read 5, iclass 20, count 2 2006.182.08:07:29.42#ibcon#about to read 6, iclass 20, count 2 2006.182.08:07:29.42#ibcon#read 6, iclass 20, count 2 2006.182.08:07:29.42#ibcon#end of sib2, iclass 20, count 2 2006.182.08:07:29.42#ibcon#*after write, iclass 20, count 2 2006.182.08:07:29.42#ibcon#*before return 0, iclass 20, count 2 2006.182.08:07:29.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:29.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:29.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.08:07:29.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:29.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:29.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:29.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:29.54#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:07:29.54#ibcon#first serial, iclass 20, count 0 2006.182.08:07:29.54#ibcon#enter sib2, iclass 20, count 0 2006.182.08:07:29.54#ibcon#flushed, iclass 20, count 0 2006.182.08:07:29.54#ibcon#about to write, iclass 20, count 0 2006.182.08:07:29.54#ibcon#wrote, iclass 20, count 0 2006.182.08:07:29.54#ibcon#about to read 3, iclass 20, count 0 2006.182.08:07:29.56#ibcon#read 3, iclass 20, count 0 2006.182.08:07:29.56#ibcon#about to read 4, iclass 20, count 0 2006.182.08:07:29.56#ibcon#read 4, iclass 20, count 0 2006.182.08:07:29.56#ibcon#about to read 5, iclass 20, count 0 2006.182.08:07:29.56#ibcon#read 5, iclass 20, count 0 2006.182.08:07:29.56#ibcon#about to read 6, iclass 20, count 0 2006.182.08:07:29.56#ibcon#read 6, iclass 20, count 0 2006.182.08:07:29.56#ibcon#end of sib2, iclass 20, count 0 2006.182.08:07:29.56#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:07:29.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:07:29.56#ibcon#[25=USB\r\n] 2006.182.08:07:29.56#ibcon#*before write, iclass 20, count 0 2006.182.08:07:29.56#ibcon#enter sib2, iclass 20, count 0 2006.182.08:07:29.56#ibcon#flushed, iclass 20, count 0 2006.182.08:07:29.56#ibcon#about to write, iclass 20, count 0 2006.182.08:07:29.56#ibcon#wrote, iclass 20, count 0 2006.182.08:07:29.56#ibcon#about to read 3, iclass 20, count 0 2006.182.08:07:29.59#ibcon#read 3, iclass 20, count 0 2006.182.08:07:29.59#ibcon#about to read 4, iclass 20, count 0 2006.182.08:07:29.59#ibcon#read 4, iclass 20, count 0 2006.182.08:07:29.59#ibcon#about to read 5, iclass 20, count 0 2006.182.08:07:29.59#ibcon#read 5, iclass 20, count 0 2006.182.08:07:29.59#ibcon#about to read 6, iclass 20, count 0 2006.182.08:07:29.59#ibcon#read 6, iclass 20, count 0 2006.182.08:07:29.59#ibcon#end of sib2, iclass 20, count 0 2006.182.08:07:29.59#ibcon#*after write, iclass 20, count 0 2006.182.08:07:29.59#ibcon#*before return 0, iclass 20, count 0 2006.182.08:07:29.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:29.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:29.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:07:29.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:07:29.59$vc4f8/valo=6,772.99 2006.182.08:07:29.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.08:07:29.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.08:07:29.59#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:29.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:29.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:29.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:29.59#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:07:29.59#ibcon#first serial, iclass 22, count 0 2006.182.08:07:29.59#ibcon#enter sib2, iclass 22, count 0 2006.182.08:07:29.59#ibcon#flushed, iclass 22, count 0 2006.182.08:07:29.59#ibcon#about to write, iclass 22, count 0 2006.182.08:07:29.59#ibcon#wrote, iclass 22, count 0 2006.182.08:07:29.59#ibcon#about to read 3, iclass 22, count 0 2006.182.08:07:29.61#ibcon#read 3, iclass 22, count 0 2006.182.08:07:29.61#ibcon#about to read 4, iclass 22, count 0 2006.182.08:07:29.61#ibcon#read 4, iclass 22, count 0 2006.182.08:07:29.61#ibcon#about to read 5, iclass 22, count 0 2006.182.08:07:29.61#ibcon#read 5, iclass 22, count 0 2006.182.08:07:29.61#ibcon#about to read 6, iclass 22, count 0 2006.182.08:07:29.61#ibcon#read 6, iclass 22, count 0 2006.182.08:07:29.61#ibcon#end of sib2, iclass 22, count 0 2006.182.08:07:29.61#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:07:29.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:07:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:07:29.61#ibcon#*before write, iclass 22, count 0 2006.182.08:07:29.61#ibcon#enter sib2, iclass 22, count 0 2006.182.08:07:29.61#ibcon#flushed, iclass 22, count 0 2006.182.08:07:29.61#ibcon#about to write, iclass 22, count 0 2006.182.08:07:29.61#ibcon#wrote, iclass 22, count 0 2006.182.08:07:29.61#ibcon#about to read 3, iclass 22, count 0 2006.182.08:07:29.65#ibcon#read 3, iclass 22, count 0 2006.182.08:07:29.65#ibcon#about to read 4, iclass 22, count 0 2006.182.08:07:29.65#ibcon#read 4, iclass 22, count 0 2006.182.08:07:29.65#ibcon#about to read 5, iclass 22, count 0 2006.182.08:07:29.65#ibcon#read 5, iclass 22, count 0 2006.182.08:07:29.65#ibcon#about to read 6, iclass 22, count 0 2006.182.08:07:29.65#ibcon#read 6, iclass 22, count 0 2006.182.08:07:29.65#ibcon#end of sib2, iclass 22, count 0 2006.182.08:07:29.65#ibcon#*after write, iclass 22, count 0 2006.182.08:07:29.65#ibcon#*before return 0, iclass 22, count 0 2006.182.08:07:29.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:29.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:29.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:07:29.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:07:29.65$vc4f8/va=6,6 2006.182.08:07:29.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.08:07:29.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.08:07:29.65#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:29.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:29.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:29.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:29.71#ibcon#enter wrdev, iclass 24, count 2 2006.182.08:07:29.71#ibcon#first serial, iclass 24, count 2 2006.182.08:07:29.71#ibcon#enter sib2, iclass 24, count 2 2006.182.08:07:29.71#ibcon#flushed, iclass 24, count 2 2006.182.08:07:29.71#ibcon#about to write, iclass 24, count 2 2006.182.08:07:29.71#ibcon#wrote, iclass 24, count 2 2006.182.08:07:29.71#ibcon#about to read 3, iclass 24, count 2 2006.182.08:07:29.73#ibcon#read 3, iclass 24, count 2 2006.182.08:07:29.73#ibcon#about to read 4, iclass 24, count 2 2006.182.08:07:29.73#ibcon#read 4, iclass 24, count 2 2006.182.08:07:29.73#ibcon#about to read 5, iclass 24, count 2 2006.182.08:07:29.73#ibcon#read 5, iclass 24, count 2 2006.182.08:07:29.73#ibcon#about to read 6, iclass 24, count 2 2006.182.08:07:29.73#ibcon#read 6, iclass 24, count 2 2006.182.08:07:29.73#ibcon#end of sib2, iclass 24, count 2 2006.182.08:07:29.73#ibcon#*mode == 0, iclass 24, count 2 2006.182.08:07:29.73#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.08:07:29.73#ibcon#[25=AT06-06\r\n] 2006.182.08:07:29.73#ibcon#*before write, iclass 24, count 2 2006.182.08:07:29.73#ibcon#enter sib2, iclass 24, count 2 2006.182.08:07:29.73#ibcon#flushed, iclass 24, count 2 2006.182.08:07:29.73#ibcon#about to write, iclass 24, count 2 2006.182.08:07:29.73#ibcon#wrote, iclass 24, count 2 2006.182.08:07:29.73#ibcon#about to read 3, iclass 24, count 2 2006.182.08:07:29.76#ibcon#read 3, iclass 24, count 2 2006.182.08:07:29.76#ibcon#about to read 4, iclass 24, count 2 2006.182.08:07:29.76#ibcon#read 4, iclass 24, count 2 2006.182.08:07:29.76#ibcon#about to read 5, iclass 24, count 2 2006.182.08:07:29.76#ibcon#read 5, iclass 24, count 2 2006.182.08:07:29.76#ibcon#about to read 6, iclass 24, count 2 2006.182.08:07:29.76#ibcon#read 6, iclass 24, count 2 2006.182.08:07:29.76#ibcon#end of sib2, iclass 24, count 2 2006.182.08:07:29.76#ibcon#*after write, iclass 24, count 2 2006.182.08:07:29.76#ibcon#*before return 0, iclass 24, count 2 2006.182.08:07:29.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:29.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:29.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.08:07:29.76#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:29.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:29.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:29.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:29.88#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:07:29.88#ibcon#first serial, iclass 24, count 0 2006.182.08:07:29.88#ibcon#enter sib2, iclass 24, count 0 2006.182.08:07:29.88#ibcon#flushed, iclass 24, count 0 2006.182.08:07:29.88#ibcon#about to write, iclass 24, count 0 2006.182.08:07:29.88#ibcon#wrote, iclass 24, count 0 2006.182.08:07:29.88#ibcon#about to read 3, iclass 24, count 0 2006.182.08:07:29.90#ibcon#read 3, iclass 24, count 0 2006.182.08:07:29.90#ibcon#about to read 4, iclass 24, count 0 2006.182.08:07:29.90#ibcon#read 4, iclass 24, count 0 2006.182.08:07:29.90#ibcon#about to read 5, iclass 24, count 0 2006.182.08:07:29.90#ibcon#read 5, iclass 24, count 0 2006.182.08:07:29.90#ibcon#about to read 6, iclass 24, count 0 2006.182.08:07:29.90#ibcon#read 6, iclass 24, count 0 2006.182.08:07:29.90#ibcon#end of sib2, iclass 24, count 0 2006.182.08:07:29.90#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:07:29.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:07:29.90#ibcon#[25=USB\r\n] 2006.182.08:07:29.90#ibcon#*before write, iclass 24, count 0 2006.182.08:07:29.90#ibcon#enter sib2, iclass 24, count 0 2006.182.08:07:29.90#ibcon#flushed, iclass 24, count 0 2006.182.08:07:29.90#ibcon#about to write, iclass 24, count 0 2006.182.08:07:29.90#ibcon#wrote, iclass 24, count 0 2006.182.08:07:29.90#ibcon#about to read 3, iclass 24, count 0 2006.182.08:07:29.93#ibcon#read 3, iclass 24, count 0 2006.182.08:07:29.93#ibcon#about to read 4, iclass 24, count 0 2006.182.08:07:29.93#ibcon#read 4, iclass 24, count 0 2006.182.08:07:29.93#ibcon#about to read 5, iclass 24, count 0 2006.182.08:07:29.93#ibcon#read 5, iclass 24, count 0 2006.182.08:07:29.93#ibcon#about to read 6, iclass 24, count 0 2006.182.08:07:29.93#ibcon#read 6, iclass 24, count 0 2006.182.08:07:29.93#ibcon#end of sib2, iclass 24, count 0 2006.182.08:07:29.93#ibcon#*after write, iclass 24, count 0 2006.182.08:07:29.93#ibcon#*before return 0, iclass 24, count 0 2006.182.08:07:29.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:29.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:29.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:07:29.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:07:29.93$vc4f8/valo=7,832.99 2006.182.08:07:29.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.08:07:29.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.08:07:29.93#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:29.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:29.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:29.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:29.93#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:07:29.93#ibcon#first serial, iclass 26, count 0 2006.182.08:07:29.93#ibcon#enter sib2, iclass 26, count 0 2006.182.08:07:29.93#ibcon#flushed, iclass 26, count 0 2006.182.08:07:29.93#ibcon#about to write, iclass 26, count 0 2006.182.08:07:29.93#ibcon#wrote, iclass 26, count 0 2006.182.08:07:29.93#ibcon#about to read 3, iclass 26, count 0 2006.182.08:07:29.95#ibcon#read 3, iclass 26, count 0 2006.182.08:07:29.95#ibcon#about to read 4, iclass 26, count 0 2006.182.08:07:29.95#ibcon#read 4, iclass 26, count 0 2006.182.08:07:29.95#ibcon#about to read 5, iclass 26, count 0 2006.182.08:07:29.95#ibcon#read 5, iclass 26, count 0 2006.182.08:07:29.95#ibcon#about to read 6, iclass 26, count 0 2006.182.08:07:29.95#ibcon#read 6, iclass 26, count 0 2006.182.08:07:29.95#ibcon#end of sib2, iclass 26, count 0 2006.182.08:07:29.95#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:07:29.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:07:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:07:29.95#ibcon#*before write, iclass 26, count 0 2006.182.08:07:29.95#ibcon#enter sib2, iclass 26, count 0 2006.182.08:07:29.95#ibcon#flushed, iclass 26, count 0 2006.182.08:07:29.95#ibcon#about to write, iclass 26, count 0 2006.182.08:07:29.95#ibcon#wrote, iclass 26, count 0 2006.182.08:07:29.95#ibcon#about to read 3, iclass 26, count 0 2006.182.08:07:29.99#ibcon#read 3, iclass 26, count 0 2006.182.08:07:29.99#ibcon#about to read 4, iclass 26, count 0 2006.182.08:07:29.99#ibcon#read 4, iclass 26, count 0 2006.182.08:07:29.99#ibcon#about to read 5, iclass 26, count 0 2006.182.08:07:29.99#ibcon#read 5, iclass 26, count 0 2006.182.08:07:29.99#ibcon#about to read 6, iclass 26, count 0 2006.182.08:07:29.99#ibcon#read 6, iclass 26, count 0 2006.182.08:07:29.99#ibcon#end of sib2, iclass 26, count 0 2006.182.08:07:29.99#ibcon#*after write, iclass 26, count 0 2006.182.08:07:29.99#ibcon#*before return 0, iclass 26, count 0 2006.182.08:07:29.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:29.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:29.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:07:29.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:07:29.99$vc4f8/va=7,6 2006.182.08:07:29.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.08:07:29.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.08:07:29.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:29.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:07:30.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:07:30.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:07:30.05#ibcon#enter wrdev, iclass 28, count 2 2006.182.08:07:30.05#ibcon#first serial, iclass 28, count 2 2006.182.08:07:30.05#ibcon#enter sib2, iclass 28, count 2 2006.182.08:07:30.05#ibcon#flushed, iclass 28, count 2 2006.182.08:07:30.05#ibcon#about to write, iclass 28, count 2 2006.182.08:07:30.05#ibcon#wrote, iclass 28, count 2 2006.182.08:07:30.05#ibcon#about to read 3, iclass 28, count 2 2006.182.08:07:30.07#ibcon#read 3, iclass 28, count 2 2006.182.08:07:30.07#ibcon#about to read 4, iclass 28, count 2 2006.182.08:07:30.07#ibcon#read 4, iclass 28, count 2 2006.182.08:07:30.07#ibcon#about to read 5, iclass 28, count 2 2006.182.08:07:30.07#ibcon#read 5, iclass 28, count 2 2006.182.08:07:30.07#ibcon#about to read 6, iclass 28, count 2 2006.182.08:07:30.07#ibcon#read 6, iclass 28, count 2 2006.182.08:07:30.07#ibcon#end of sib2, iclass 28, count 2 2006.182.08:07:30.07#ibcon#*mode == 0, iclass 28, count 2 2006.182.08:07:30.07#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.08:07:30.07#ibcon#[25=AT07-06\r\n] 2006.182.08:07:30.07#ibcon#*before write, iclass 28, count 2 2006.182.08:07:30.07#ibcon#enter sib2, iclass 28, count 2 2006.182.08:07:30.07#ibcon#flushed, iclass 28, count 2 2006.182.08:07:30.07#ibcon#about to write, iclass 28, count 2 2006.182.08:07:30.07#ibcon#wrote, iclass 28, count 2 2006.182.08:07:30.07#ibcon#about to read 3, iclass 28, count 2 2006.182.08:07:30.10#ibcon#read 3, iclass 28, count 2 2006.182.08:07:30.10#ibcon#about to read 4, iclass 28, count 2 2006.182.08:07:30.10#ibcon#read 4, iclass 28, count 2 2006.182.08:07:30.10#ibcon#about to read 5, iclass 28, count 2 2006.182.08:07:30.10#ibcon#read 5, iclass 28, count 2 2006.182.08:07:30.10#ibcon#about to read 6, iclass 28, count 2 2006.182.08:07:30.10#ibcon#read 6, iclass 28, count 2 2006.182.08:07:30.10#ibcon#end of sib2, iclass 28, count 2 2006.182.08:07:30.10#ibcon#*after write, iclass 28, count 2 2006.182.08:07:30.10#ibcon#*before return 0, iclass 28, count 2 2006.182.08:07:30.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:07:30.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:07:30.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.08:07:30.10#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:30.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:07:30.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:07:30.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:07:30.22#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:07:30.22#ibcon#first serial, iclass 28, count 0 2006.182.08:07:30.22#ibcon#enter sib2, iclass 28, count 0 2006.182.08:07:30.22#ibcon#flushed, iclass 28, count 0 2006.182.08:07:30.22#ibcon#about to write, iclass 28, count 0 2006.182.08:07:30.22#ibcon#wrote, iclass 28, count 0 2006.182.08:07:30.22#ibcon#about to read 3, iclass 28, count 0 2006.182.08:07:30.24#ibcon#read 3, iclass 28, count 0 2006.182.08:07:30.24#ibcon#about to read 4, iclass 28, count 0 2006.182.08:07:30.24#ibcon#read 4, iclass 28, count 0 2006.182.08:07:30.24#ibcon#about to read 5, iclass 28, count 0 2006.182.08:07:30.24#ibcon#read 5, iclass 28, count 0 2006.182.08:07:30.24#ibcon#about to read 6, iclass 28, count 0 2006.182.08:07:30.24#ibcon#read 6, iclass 28, count 0 2006.182.08:07:30.24#ibcon#end of sib2, iclass 28, count 0 2006.182.08:07:30.24#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:07:30.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:07:30.24#ibcon#[25=USB\r\n] 2006.182.08:07:30.24#ibcon#*before write, iclass 28, count 0 2006.182.08:07:30.24#ibcon#enter sib2, iclass 28, count 0 2006.182.08:07:30.24#ibcon#flushed, iclass 28, count 0 2006.182.08:07:30.24#ibcon#about to write, iclass 28, count 0 2006.182.08:07:30.24#ibcon#wrote, iclass 28, count 0 2006.182.08:07:30.24#ibcon#about to read 3, iclass 28, count 0 2006.182.08:07:30.27#ibcon#read 3, iclass 28, count 0 2006.182.08:07:30.27#ibcon#about to read 4, iclass 28, count 0 2006.182.08:07:30.27#ibcon#read 4, iclass 28, count 0 2006.182.08:07:30.27#ibcon#about to read 5, iclass 28, count 0 2006.182.08:07:30.27#ibcon#read 5, iclass 28, count 0 2006.182.08:07:30.27#ibcon#about to read 6, iclass 28, count 0 2006.182.08:07:30.27#ibcon#read 6, iclass 28, count 0 2006.182.08:07:30.27#ibcon#end of sib2, iclass 28, count 0 2006.182.08:07:30.27#ibcon#*after write, iclass 28, count 0 2006.182.08:07:30.27#ibcon#*before return 0, iclass 28, count 0 2006.182.08:07:30.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:07:30.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:07:30.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:07:30.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:07:30.27$vc4f8/valo=8,852.99 2006.182.08:07:30.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.08:07:30.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.08:07:30.27#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:30.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:07:30.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:07:30.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:07:30.27#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:07:30.27#ibcon#first serial, iclass 30, count 0 2006.182.08:07:30.27#ibcon#enter sib2, iclass 30, count 0 2006.182.08:07:30.27#ibcon#flushed, iclass 30, count 0 2006.182.08:07:30.27#ibcon#about to write, iclass 30, count 0 2006.182.08:07:30.27#ibcon#wrote, iclass 30, count 0 2006.182.08:07:30.27#ibcon#about to read 3, iclass 30, count 0 2006.182.08:07:30.29#ibcon#read 3, iclass 30, count 0 2006.182.08:07:30.29#ibcon#about to read 4, iclass 30, count 0 2006.182.08:07:30.29#ibcon#read 4, iclass 30, count 0 2006.182.08:07:30.29#ibcon#about to read 5, iclass 30, count 0 2006.182.08:07:30.29#ibcon#read 5, iclass 30, count 0 2006.182.08:07:30.29#ibcon#about to read 6, iclass 30, count 0 2006.182.08:07:30.29#ibcon#read 6, iclass 30, count 0 2006.182.08:07:30.29#ibcon#end of sib2, iclass 30, count 0 2006.182.08:07:30.29#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:07:30.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:07:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:07:30.29#ibcon#*before write, iclass 30, count 0 2006.182.08:07:30.29#ibcon#enter sib2, iclass 30, count 0 2006.182.08:07:30.29#ibcon#flushed, iclass 30, count 0 2006.182.08:07:30.29#ibcon#about to write, iclass 30, count 0 2006.182.08:07:30.29#ibcon#wrote, iclass 30, count 0 2006.182.08:07:30.29#ibcon#about to read 3, iclass 30, count 0 2006.182.08:07:30.33#ibcon#read 3, iclass 30, count 0 2006.182.08:07:30.33#ibcon#about to read 4, iclass 30, count 0 2006.182.08:07:30.33#ibcon#read 4, iclass 30, count 0 2006.182.08:07:30.33#ibcon#about to read 5, iclass 30, count 0 2006.182.08:07:30.33#ibcon#read 5, iclass 30, count 0 2006.182.08:07:30.33#ibcon#about to read 6, iclass 30, count 0 2006.182.08:07:30.33#ibcon#read 6, iclass 30, count 0 2006.182.08:07:30.33#ibcon#end of sib2, iclass 30, count 0 2006.182.08:07:30.33#ibcon#*after write, iclass 30, count 0 2006.182.08:07:30.33#ibcon#*before return 0, iclass 30, count 0 2006.182.08:07:30.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:07:30.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:07:30.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:07:30.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:07:30.33$vc4f8/va=8,7 2006.182.08:07:30.33#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.08:07:30.33#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.08:07:30.33#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:30.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:07:30.36#abcon#<5=/06 0.9 2.6 27.88 831002.9\r\n> 2006.182.08:07:30.38#abcon#{5=INTERFACE CLEAR} 2006.182.08:07:30.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:07:30.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:07:30.39#ibcon#enter wrdev, iclass 33, count 2 2006.182.08:07:30.39#ibcon#first serial, iclass 33, count 2 2006.182.08:07:30.39#ibcon#enter sib2, iclass 33, count 2 2006.182.08:07:30.39#ibcon#flushed, iclass 33, count 2 2006.182.08:07:30.39#ibcon#about to write, iclass 33, count 2 2006.182.08:07:30.39#ibcon#wrote, iclass 33, count 2 2006.182.08:07:30.39#ibcon#about to read 3, iclass 33, count 2 2006.182.08:07:30.41#ibcon#read 3, iclass 33, count 2 2006.182.08:07:30.41#ibcon#about to read 4, iclass 33, count 2 2006.182.08:07:30.41#ibcon#read 4, iclass 33, count 2 2006.182.08:07:30.41#ibcon#about to read 5, iclass 33, count 2 2006.182.08:07:30.41#ibcon#read 5, iclass 33, count 2 2006.182.08:07:30.41#ibcon#about to read 6, iclass 33, count 2 2006.182.08:07:30.41#ibcon#read 6, iclass 33, count 2 2006.182.08:07:30.41#ibcon#end of sib2, iclass 33, count 2 2006.182.08:07:30.41#ibcon#*mode == 0, iclass 33, count 2 2006.182.08:07:30.41#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.08:07:30.41#ibcon#[25=AT08-07\r\n] 2006.182.08:07:30.41#ibcon#*before write, iclass 33, count 2 2006.182.08:07:30.41#ibcon#enter sib2, iclass 33, count 2 2006.182.08:07:30.41#ibcon#flushed, iclass 33, count 2 2006.182.08:07:30.41#ibcon#about to write, iclass 33, count 2 2006.182.08:07:30.41#ibcon#wrote, iclass 33, count 2 2006.182.08:07:30.41#ibcon#about to read 3, iclass 33, count 2 2006.182.08:07:30.44#abcon#[5=S1D000X0/0*\r\n] 2006.182.08:07:30.44#ibcon#read 3, iclass 33, count 2 2006.182.08:07:30.44#ibcon#about to read 4, iclass 33, count 2 2006.182.08:07:30.44#ibcon#read 4, iclass 33, count 2 2006.182.08:07:30.44#ibcon#about to read 5, iclass 33, count 2 2006.182.08:07:30.44#ibcon#read 5, iclass 33, count 2 2006.182.08:07:30.44#ibcon#about to read 6, iclass 33, count 2 2006.182.08:07:30.44#ibcon#read 6, iclass 33, count 2 2006.182.08:07:30.44#ibcon#end of sib2, iclass 33, count 2 2006.182.08:07:30.44#ibcon#*after write, iclass 33, count 2 2006.182.08:07:30.44#ibcon#*before return 0, iclass 33, count 2 2006.182.08:07:30.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:07:30.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:07:30.44#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.08:07:30.44#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:30.44#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:07:30.56#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:07:30.56#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:07:30.56#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:07:30.56#ibcon#first serial, iclass 33, count 0 2006.182.08:07:30.56#ibcon#enter sib2, iclass 33, count 0 2006.182.08:07:30.56#ibcon#flushed, iclass 33, count 0 2006.182.08:07:30.56#ibcon#about to write, iclass 33, count 0 2006.182.08:07:30.56#ibcon#wrote, iclass 33, count 0 2006.182.08:07:30.56#ibcon#about to read 3, iclass 33, count 0 2006.182.08:07:30.58#ibcon#read 3, iclass 33, count 0 2006.182.08:07:30.58#ibcon#about to read 4, iclass 33, count 0 2006.182.08:07:30.58#ibcon#read 4, iclass 33, count 0 2006.182.08:07:30.58#ibcon#about to read 5, iclass 33, count 0 2006.182.08:07:30.58#ibcon#read 5, iclass 33, count 0 2006.182.08:07:30.58#ibcon#about to read 6, iclass 33, count 0 2006.182.08:07:30.58#ibcon#read 6, iclass 33, count 0 2006.182.08:07:30.58#ibcon#end of sib2, iclass 33, count 0 2006.182.08:07:30.58#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:07:30.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:07:30.58#ibcon#[25=USB\r\n] 2006.182.08:07:30.58#ibcon#*before write, iclass 33, count 0 2006.182.08:07:30.58#ibcon#enter sib2, iclass 33, count 0 2006.182.08:07:30.58#ibcon#flushed, iclass 33, count 0 2006.182.08:07:30.58#ibcon#about to write, iclass 33, count 0 2006.182.08:07:30.58#ibcon#wrote, iclass 33, count 0 2006.182.08:07:30.58#ibcon#about to read 3, iclass 33, count 0 2006.182.08:07:30.61#ibcon#read 3, iclass 33, count 0 2006.182.08:07:30.61#ibcon#about to read 4, iclass 33, count 0 2006.182.08:07:30.61#ibcon#read 4, iclass 33, count 0 2006.182.08:07:30.61#ibcon#about to read 5, iclass 33, count 0 2006.182.08:07:30.61#ibcon#read 5, iclass 33, count 0 2006.182.08:07:30.61#ibcon#about to read 6, iclass 33, count 0 2006.182.08:07:30.61#ibcon#read 6, iclass 33, count 0 2006.182.08:07:30.61#ibcon#end of sib2, iclass 33, count 0 2006.182.08:07:30.61#ibcon#*after write, iclass 33, count 0 2006.182.08:07:30.61#ibcon#*before return 0, iclass 33, count 0 2006.182.08:07:30.61#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:07:30.61#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:07:30.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:07:30.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:07:30.61$vc4f8/vblo=1,632.99 2006.182.08:07:30.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.08:07:30.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.08:07:30.61#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:30.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:30.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:30.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:30.61#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:07:30.61#ibcon#first serial, iclass 38, count 0 2006.182.08:07:30.61#ibcon#enter sib2, iclass 38, count 0 2006.182.08:07:30.61#ibcon#flushed, iclass 38, count 0 2006.182.08:07:30.61#ibcon#about to write, iclass 38, count 0 2006.182.08:07:30.61#ibcon#wrote, iclass 38, count 0 2006.182.08:07:30.61#ibcon#about to read 3, iclass 38, count 0 2006.182.08:07:30.63#ibcon#read 3, iclass 38, count 0 2006.182.08:07:30.63#ibcon#about to read 4, iclass 38, count 0 2006.182.08:07:30.63#ibcon#read 4, iclass 38, count 0 2006.182.08:07:30.63#ibcon#about to read 5, iclass 38, count 0 2006.182.08:07:30.63#ibcon#read 5, iclass 38, count 0 2006.182.08:07:30.63#ibcon#about to read 6, iclass 38, count 0 2006.182.08:07:30.63#ibcon#read 6, iclass 38, count 0 2006.182.08:07:30.63#ibcon#end of sib2, iclass 38, count 0 2006.182.08:07:30.63#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:07:30.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:07:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:07:30.63#ibcon#*before write, iclass 38, count 0 2006.182.08:07:30.63#ibcon#enter sib2, iclass 38, count 0 2006.182.08:07:30.63#ibcon#flushed, iclass 38, count 0 2006.182.08:07:30.63#ibcon#about to write, iclass 38, count 0 2006.182.08:07:30.63#ibcon#wrote, iclass 38, count 0 2006.182.08:07:30.63#ibcon#about to read 3, iclass 38, count 0 2006.182.08:07:30.67#ibcon#read 3, iclass 38, count 0 2006.182.08:07:30.67#ibcon#about to read 4, iclass 38, count 0 2006.182.08:07:30.67#ibcon#read 4, iclass 38, count 0 2006.182.08:07:30.67#ibcon#about to read 5, iclass 38, count 0 2006.182.08:07:30.67#ibcon#read 5, iclass 38, count 0 2006.182.08:07:30.67#ibcon#about to read 6, iclass 38, count 0 2006.182.08:07:30.67#ibcon#read 6, iclass 38, count 0 2006.182.08:07:30.67#ibcon#end of sib2, iclass 38, count 0 2006.182.08:07:30.67#ibcon#*after write, iclass 38, count 0 2006.182.08:07:30.67#ibcon#*before return 0, iclass 38, count 0 2006.182.08:07:30.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:30.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:07:30.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:07:30.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:07:30.67$vc4f8/vb=1,4 2006.182.08:07:30.67#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.08:07:30.67#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.08:07:30.67#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:30.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:30.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:30.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:30.67#ibcon#enter wrdev, iclass 40, count 2 2006.182.08:07:30.67#ibcon#first serial, iclass 40, count 2 2006.182.08:07:30.67#ibcon#enter sib2, iclass 40, count 2 2006.182.08:07:30.67#ibcon#flushed, iclass 40, count 2 2006.182.08:07:30.67#ibcon#about to write, iclass 40, count 2 2006.182.08:07:30.67#ibcon#wrote, iclass 40, count 2 2006.182.08:07:30.67#ibcon#about to read 3, iclass 40, count 2 2006.182.08:07:30.69#ibcon#read 3, iclass 40, count 2 2006.182.08:07:30.69#ibcon#about to read 4, iclass 40, count 2 2006.182.08:07:30.69#ibcon#read 4, iclass 40, count 2 2006.182.08:07:30.69#ibcon#about to read 5, iclass 40, count 2 2006.182.08:07:30.69#ibcon#read 5, iclass 40, count 2 2006.182.08:07:30.69#ibcon#about to read 6, iclass 40, count 2 2006.182.08:07:30.69#ibcon#read 6, iclass 40, count 2 2006.182.08:07:30.69#ibcon#end of sib2, iclass 40, count 2 2006.182.08:07:30.69#ibcon#*mode == 0, iclass 40, count 2 2006.182.08:07:30.69#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.08:07:30.69#ibcon#[27=AT01-04\r\n] 2006.182.08:07:30.69#ibcon#*before write, iclass 40, count 2 2006.182.08:07:30.69#ibcon#enter sib2, iclass 40, count 2 2006.182.08:07:30.69#ibcon#flushed, iclass 40, count 2 2006.182.08:07:30.69#ibcon#about to write, iclass 40, count 2 2006.182.08:07:30.69#ibcon#wrote, iclass 40, count 2 2006.182.08:07:30.69#ibcon#about to read 3, iclass 40, count 2 2006.182.08:07:30.72#ibcon#read 3, iclass 40, count 2 2006.182.08:07:30.72#ibcon#about to read 4, iclass 40, count 2 2006.182.08:07:30.72#ibcon#read 4, iclass 40, count 2 2006.182.08:07:30.72#ibcon#about to read 5, iclass 40, count 2 2006.182.08:07:30.72#ibcon#read 5, iclass 40, count 2 2006.182.08:07:30.72#ibcon#about to read 6, iclass 40, count 2 2006.182.08:07:30.72#ibcon#read 6, iclass 40, count 2 2006.182.08:07:30.72#ibcon#end of sib2, iclass 40, count 2 2006.182.08:07:30.72#ibcon#*after write, iclass 40, count 2 2006.182.08:07:30.72#ibcon#*before return 0, iclass 40, count 2 2006.182.08:07:30.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:30.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:07:30.72#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.08:07:30.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:30.72#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:30.84#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:30.84#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:30.84#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:07:30.84#ibcon#first serial, iclass 40, count 0 2006.182.08:07:30.84#ibcon#enter sib2, iclass 40, count 0 2006.182.08:07:30.84#ibcon#flushed, iclass 40, count 0 2006.182.08:07:30.84#ibcon#about to write, iclass 40, count 0 2006.182.08:07:30.84#ibcon#wrote, iclass 40, count 0 2006.182.08:07:30.84#ibcon#about to read 3, iclass 40, count 0 2006.182.08:07:30.86#ibcon#read 3, iclass 40, count 0 2006.182.08:07:30.86#ibcon#about to read 4, iclass 40, count 0 2006.182.08:07:30.86#ibcon#read 4, iclass 40, count 0 2006.182.08:07:30.86#ibcon#about to read 5, iclass 40, count 0 2006.182.08:07:30.86#ibcon#read 5, iclass 40, count 0 2006.182.08:07:30.86#ibcon#about to read 6, iclass 40, count 0 2006.182.08:07:30.86#ibcon#read 6, iclass 40, count 0 2006.182.08:07:30.86#ibcon#end of sib2, iclass 40, count 0 2006.182.08:07:30.86#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:07:30.86#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:07:30.86#ibcon#[27=USB\r\n] 2006.182.08:07:30.86#ibcon#*before write, iclass 40, count 0 2006.182.08:07:30.86#ibcon#enter sib2, iclass 40, count 0 2006.182.08:07:30.86#ibcon#flushed, iclass 40, count 0 2006.182.08:07:30.86#ibcon#about to write, iclass 40, count 0 2006.182.08:07:30.86#ibcon#wrote, iclass 40, count 0 2006.182.08:07:30.86#ibcon#about to read 3, iclass 40, count 0 2006.182.08:07:30.89#ibcon#read 3, iclass 40, count 0 2006.182.08:07:30.89#ibcon#about to read 4, iclass 40, count 0 2006.182.08:07:30.89#ibcon#read 4, iclass 40, count 0 2006.182.08:07:30.89#ibcon#about to read 5, iclass 40, count 0 2006.182.08:07:30.89#ibcon#read 5, iclass 40, count 0 2006.182.08:07:30.89#ibcon#about to read 6, iclass 40, count 0 2006.182.08:07:30.89#ibcon#read 6, iclass 40, count 0 2006.182.08:07:30.89#ibcon#end of sib2, iclass 40, count 0 2006.182.08:07:30.89#ibcon#*after write, iclass 40, count 0 2006.182.08:07:30.89#ibcon#*before return 0, iclass 40, count 0 2006.182.08:07:30.89#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:30.89#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:07:30.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:07:30.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:07:30.89$vc4f8/vblo=2,640.99 2006.182.08:07:30.89#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.08:07:30.89#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.08:07:30.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:30.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:30.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:30.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:30.89#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:07:30.89#ibcon#first serial, iclass 4, count 0 2006.182.08:07:30.89#ibcon#enter sib2, iclass 4, count 0 2006.182.08:07:30.89#ibcon#flushed, iclass 4, count 0 2006.182.08:07:30.89#ibcon#about to write, iclass 4, count 0 2006.182.08:07:30.89#ibcon#wrote, iclass 4, count 0 2006.182.08:07:30.89#ibcon#about to read 3, iclass 4, count 0 2006.182.08:07:30.91#ibcon#read 3, iclass 4, count 0 2006.182.08:07:30.91#ibcon#about to read 4, iclass 4, count 0 2006.182.08:07:30.91#ibcon#read 4, iclass 4, count 0 2006.182.08:07:30.91#ibcon#about to read 5, iclass 4, count 0 2006.182.08:07:30.91#ibcon#read 5, iclass 4, count 0 2006.182.08:07:30.91#ibcon#about to read 6, iclass 4, count 0 2006.182.08:07:30.91#ibcon#read 6, iclass 4, count 0 2006.182.08:07:30.91#ibcon#end of sib2, iclass 4, count 0 2006.182.08:07:30.91#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:07:30.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:07:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:07:30.91#ibcon#*before write, iclass 4, count 0 2006.182.08:07:30.91#ibcon#enter sib2, iclass 4, count 0 2006.182.08:07:30.91#ibcon#flushed, iclass 4, count 0 2006.182.08:07:30.91#ibcon#about to write, iclass 4, count 0 2006.182.08:07:30.91#ibcon#wrote, iclass 4, count 0 2006.182.08:07:30.91#ibcon#about to read 3, iclass 4, count 0 2006.182.08:07:30.95#ibcon#read 3, iclass 4, count 0 2006.182.08:07:30.95#ibcon#about to read 4, iclass 4, count 0 2006.182.08:07:30.95#ibcon#read 4, iclass 4, count 0 2006.182.08:07:30.95#ibcon#about to read 5, iclass 4, count 0 2006.182.08:07:30.95#ibcon#read 5, iclass 4, count 0 2006.182.08:07:30.95#ibcon#about to read 6, iclass 4, count 0 2006.182.08:07:30.95#ibcon#read 6, iclass 4, count 0 2006.182.08:07:30.95#ibcon#end of sib2, iclass 4, count 0 2006.182.08:07:30.95#ibcon#*after write, iclass 4, count 0 2006.182.08:07:30.95#ibcon#*before return 0, iclass 4, count 0 2006.182.08:07:30.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:30.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:07:30.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:07:30.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:07:30.95$vc4f8/vb=2,4 2006.182.08:07:30.95#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.08:07:30.95#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.08:07:30.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:30.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:31.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:31.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:31.01#ibcon#enter wrdev, iclass 6, count 2 2006.182.08:07:31.01#ibcon#first serial, iclass 6, count 2 2006.182.08:07:31.01#ibcon#enter sib2, iclass 6, count 2 2006.182.08:07:31.01#ibcon#flushed, iclass 6, count 2 2006.182.08:07:31.01#ibcon#about to write, iclass 6, count 2 2006.182.08:07:31.01#ibcon#wrote, iclass 6, count 2 2006.182.08:07:31.01#ibcon#about to read 3, iclass 6, count 2 2006.182.08:07:31.03#ibcon#read 3, iclass 6, count 2 2006.182.08:07:31.03#ibcon#about to read 4, iclass 6, count 2 2006.182.08:07:31.03#ibcon#read 4, iclass 6, count 2 2006.182.08:07:31.03#ibcon#about to read 5, iclass 6, count 2 2006.182.08:07:31.03#ibcon#read 5, iclass 6, count 2 2006.182.08:07:31.03#ibcon#about to read 6, iclass 6, count 2 2006.182.08:07:31.03#ibcon#read 6, iclass 6, count 2 2006.182.08:07:31.03#ibcon#end of sib2, iclass 6, count 2 2006.182.08:07:31.03#ibcon#*mode == 0, iclass 6, count 2 2006.182.08:07:31.03#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.08:07:31.03#ibcon#[27=AT02-04\r\n] 2006.182.08:07:31.03#ibcon#*before write, iclass 6, count 2 2006.182.08:07:31.03#ibcon#enter sib2, iclass 6, count 2 2006.182.08:07:31.03#ibcon#flushed, iclass 6, count 2 2006.182.08:07:31.03#ibcon#about to write, iclass 6, count 2 2006.182.08:07:31.03#ibcon#wrote, iclass 6, count 2 2006.182.08:07:31.03#ibcon#about to read 3, iclass 6, count 2 2006.182.08:07:31.06#ibcon#read 3, iclass 6, count 2 2006.182.08:07:31.06#ibcon#about to read 4, iclass 6, count 2 2006.182.08:07:31.06#ibcon#read 4, iclass 6, count 2 2006.182.08:07:31.06#ibcon#about to read 5, iclass 6, count 2 2006.182.08:07:31.06#ibcon#read 5, iclass 6, count 2 2006.182.08:07:31.06#ibcon#about to read 6, iclass 6, count 2 2006.182.08:07:31.06#ibcon#read 6, iclass 6, count 2 2006.182.08:07:31.06#ibcon#end of sib2, iclass 6, count 2 2006.182.08:07:31.06#ibcon#*after write, iclass 6, count 2 2006.182.08:07:31.06#ibcon#*before return 0, iclass 6, count 2 2006.182.08:07:31.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:31.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:07:31.06#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.08:07:31.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:31.06#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:31.18#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:31.18#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:31.18#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:07:31.18#ibcon#first serial, iclass 6, count 0 2006.182.08:07:31.18#ibcon#enter sib2, iclass 6, count 0 2006.182.08:07:31.18#ibcon#flushed, iclass 6, count 0 2006.182.08:07:31.18#ibcon#about to write, iclass 6, count 0 2006.182.08:07:31.18#ibcon#wrote, iclass 6, count 0 2006.182.08:07:31.18#ibcon#about to read 3, iclass 6, count 0 2006.182.08:07:31.20#ibcon#read 3, iclass 6, count 0 2006.182.08:07:31.20#ibcon#about to read 4, iclass 6, count 0 2006.182.08:07:31.20#ibcon#read 4, iclass 6, count 0 2006.182.08:07:31.20#ibcon#about to read 5, iclass 6, count 0 2006.182.08:07:31.20#ibcon#read 5, iclass 6, count 0 2006.182.08:07:31.20#ibcon#about to read 6, iclass 6, count 0 2006.182.08:07:31.20#ibcon#read 6, iclass 6, count 0 2006.182.08:07:31.20#ibcon#end of sib2, iclass 6, count 0 2006.182.08:07:31.20#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:07:31.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:07:31.20#ibcon#[27=USB\r\n] 2006.182.08:07:31.20#ibcon#*before write, iclass 6, count 0 2006.182.08:07:31.20#ibcon#enter sib2, iclass 6, count 0 2006.182.08:07:31.20#ibcon#flushed, iclass 6, count 0 2006.182.08:07:31.20#ibcon#about to write, iclass 6, count 0 2006.182.08:07:31.20#ibcon#wrote, iclass 6, count 0 2006.182.08:07:31.20#ibcon#about to read 3, iclass 6, count 0 2006.182.08:07:31.23#ibcon#read 3, iclass 6, count 0 2006.182.08:07:31.23#ibcon#about to read 4, iclass 6, count 0 2006.182.08:07:31.23#ibcon#read 4, iclass 6, count 0 2006.182.08:07:31.23#ibcon#about to read 5, iclass 6, count 0 2006.182.08:07:31.23#ibcon#read 5, iclass 6, count 0 2006.182.08:07:31.23#ibcon#about to read 6, iclass 6, count 0 2006.182.08:07:31.23#ibcon#read 6, iclass 6, count 0 2006.182.08:07:31.23#ibcon#end of sib2, iclass 6, count 0 2006.182.08:07:31.23#ibcon#*after write, iclass 6, count 0 2006.182.08:07:31.23#ibcon#*before return 0, iclass 6, count 0 2006.182.08:07:31.23#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:31.23#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:07:31.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:07:31.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:07:31.23$vc4f8/vblo=3,656.99 2006.182.08:07:31.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.08:07:31.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.08:07:31.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:31.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:31.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:31.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:31.23#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:07:31.23#ibcon#first serial, iclass 10, count 0 2006.182.08:07:31.23#ibcon#enter sib2, iclass 10, count 0 2006.182.08:07:31.23#ibcon#flushed, iclass 10, count 0 2006.182.08:07:31.23#ibcon#about to write, iclass 10, count 0 2006.182.08:07:31.23#ibcon#wrote, iclass 10, count 0 2006.182.08:07:31.23#ibcon#about to read 3, iclass 10, count 0 2006.182.08:07:31.25#ibcon#read 3, iclass 10, count 0 2006.182.08:07:31.25#ibcon#about to read 4, iclass 10, count 0 2006.182.08:07:31.25#ibcon#read 4, iclass 10, count 0 2006.182.08:07:31.25#ibcon#about to read 5, iclass 10, count 0 2006.182.08:07:31.25#ibcon#read 5, iclass 10, count 0 2006.182.08:07:31.25#ibcon#about to read 6, iclass 10, count 0 2006.182.08:07:31.25#ibcon#read 6, iclass 10, count 0 2006.182.08:07:31.25#ibcon#end of sib2, iclass 10, count 0 2006.182.08:07:31.25#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:07:31.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:07:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:07:31.25#ibcon#*before write, iclass 10, count 0 2006.182.08:07:31.25#ibcon#enter sib2, iclass 10, count 0 2006.182.08:07:31.25#ibcon#flushed, iclass 10, count 0 2006.182.08:07:31.25#ibcon#about to write, iclass 10, count 0 2006.182.08:07:31.25#ibcon#wrote, iclass 10, count 0 2006.182.08:07:31.25#ibcon#about to read 3, iclass 10, count 0 2006.182.08:07:31.29#ibcon#read 3, iclass 10, count 0 2006.182.08:07:31.29#ibcon#about to read 4, iclass 10, count 0 2006.182.08:07:31.29#ibcon#read 4, iclass 10, count 0 2006.182.08:07:31.29#ibcon#about to read 5, iclass 10, count 0 2006.182.08:07:31.29#ibcon#read 5, iclass 10, count 0 2006.182.08:07:31.29#ibcon#about to read 6, iclass 10, count 0 2006.182.08:07:31.29#ibcon#read 6, iclass 10, count 0 2006.182.08:07:31.29#ibcon#end of sib2, iclass 10, count 0 2006.182.08:07:31.29#ibcon#*after write, iclass 10, count 0 2006.182.08:07:31.29#ibcon#*before return 0, iclass 10, count 0 2006.182.08:07:31.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:31.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:07:31.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:07:31.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:07:31.29$vc4f8/vb=3,4 2006.182.08:07:31.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.08:07:31.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.08:07:31.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:31.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:31.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:31.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:31.35#ibcon#enter wrdev, iclass 12, count 2 2006.182.08:07:31.35#ibcon#first serial, iclass 12, count 2 2006.182.08:07:31.35#ibcon#enter sib2, iclass 12, count 2 2006.182.08:07:31.35#ibcon#flushed, iclass 12, count 2 2006.182.08:07:31.35#ibcon#about to write, iclass 12, count 2 2006.182.08:07:31.35#ibcon#wrote, iclass 12, count 2 2006.182.08:07:31.35#ibcon#about to read 3, iclass 12, count 2 2006.182.08:07:31.37#ibcon#read 3, iclass 12, count 2 2006.182.08:07:31.37#ibcon#about to read 4, iclass 12, count 2 2006.182.08:07:31.37#ibcon#read 4, iclass 12, count 2 2006.182.08:07:31.37#ibcon#about to read 5, iclass 12, count 2 2006.182.08:07:31.37#ibcon#read 5, iclass 12, count 2 2006.182.08:07:31.37#ibcon#about to read 6, iclass 12, count 2 2006.182.08:07:31.37#ibcon#read 6, iclass 12, count 2 2006.182.08:07:31.37#ibcon#end of sib2, iclass 12, count 2 2006.182.08:07:31.37#ibcon#*mode == 0, iclass 12, count 2 2006.182.08:07:31.37#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.08:07:31.37#ibcon#[27=AT03-04\r\n] 2006.182.08:07:31.37#ibcon#*before write, iclass 12, count 2 2006.182.08:07:31.37#ibcon#enter sib2, iclass 12, count 2 2006.182.08:07:31.37#ibcon#flushed, iclass 12, count 2 2006.182.08:07:31.37#ibcon#about to write, iclass 12, count 2 2006.182.08:07:31.37#ibcon#wrote, iclass 12, count 2 2006.182.08:07:31.37#ibcon#about to read 3, iclass 12, count 2 2006.182.08:07:31.40#ibcon#read 3, iclass 12, count 2 2006.182.08:07:31.40#ibcon#about to read 4, iclass 12, count 2 2006.182.08:07:31.40#ibcon#read 4, iclass 12, count 2 2006.182.08:07:31.40#ibcon#about to read 5, iclass 12, count 2 2006.182.08:07:31.40#ibcon#read 5, iclass 12, count 2 2006.182.08:07:31.40#ibcon#about to read 6, iclass 12, count 2 2006.182.08:07:31.40#ibcon#read 6, iclass 12, count 2 2006.182.08:07:31.40#ibcon#end of sib2, iclass 12, count 2 2006.182.08:07:31.40#ibcon#*after write, iclass 12, count 2 2006.182.08:07:31.40#ibcon#*before return 0, iclass 12, count 2 2006.182.08:07:31.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:31.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:07:31.40#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.08:07:31.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:31.40#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:31.52#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:31.52#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:31.52#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:07:31.52#ibcon#first serial, iclass 12, count 0 2006.182.08:07:31.52#ibcon#enter sib2, iclass 12, count 0 2006.182.08:07:31.52#ibcon#flushed, iclass 12, count 0 2006.182.08:07:31.52#ibcon#about to write, iclass 12, count 0 2006.182.08:07:31.52#ibcon#wrote, iclass 12, count 0 2006.182.08:07:31.52#ibcon#about to read 3, iclass 12, count 0 2006.182.08:07:31.54#ibcon#read 3, iclass 12, count 0 2006.182.08:07:31.54#ibcon#about to read 4, iclass 12, count 0 2006.182.08:07:31.54#ibcon#read 4, iclass 12, count 0 2006.182.08:07:31.54#ibcon#about to read 5, iclass 12, count 0 2006.182.08:07:31.54#ibcon#read 5, iclass 12, count 0 2006.182.08:07:31.54#ibcon#about to read 6, iclass 12, count 0 2006.182.08:07:31.54#ibcon#read 6, iclass 12, count 0 2006.182.08:07:31.54#ibcon#end of sib2, iclass 12, count 0 2006.182.08:07:31.54#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:07:31.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:07:31.54#ibcon#[27=USB\r\n] 2006.182.08:07:31.54#ibcon#*before write, iclass 12, count 0 2006.182.08:07:31.54#ibcon#enter sib2, iclass 12, count 0 2006.182.08:07:31.54#ibcon#flushed, iclass 12, count 0 2006.182.08:07:31.54#ibcon#about to write, iclass 12, count 0 2006.182.08:07:31.54#ibcon#wrote, iclass 12, count 0 2006.182.08:07:31.54#ibcon#about to read 3, iclass 12, count 0 2006.182.08:07:31.57#ibcon#read 3, iclass 12, count 0 2006.182.08:07:31.57#ibcon#about to read 4, iclass 12, count 0 2006.182.08:07:31.57#ibcon#read 4, iclass 12, count 0 2006.182.08:07:31.57#ibcon#about to read 5, iclass 12, count 0 2006.182.08:07:31.57#ibcon#read 5, iclass 12, count 0 2006.182.08:07:31.57#ibcon#about to read 6, iclass 12, count 0 2006.182.08:07:31.57#ibcon#read 6, iclass 12, count 0 2006.182.08:07:31.57#ibcon#end of sib2, iclass 12, count 0 2006.182.08:07:31.57#ibcon#*after write, iclass 12, count 0 2006.182.08:07:31.57#ibcon#*before return 0, iclass 12, count 0 2006.182.08:07:31.57#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:31.57#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:07:31.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:07:31.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:07:31.57$vc4f8/vblo=4,712.99 2006.182.08:07:31.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.08:07:31.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.08:07:31.57#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:31.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:31.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:31.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:31.57#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:07:31.57#ibcon#first serial, iclass 14, count 0 2006.182.08:07:31.57#ibcon#enter sib2, iclass 14, count 0 2006.182.08:07:31.57#ibcon#flushed, iclass 14, count 0 2006.182.08:07:31.57#ibcon#about to write, iclass 14, count 0 2006.182.08:07:31.57#ibcon#wrote, iclass 14, count 0 2006.182.08:07:31.57#ibcon#about to read 3, iclass 14, count 0 2006.182.08:07:31.59#ibcon#read 3, iclass 14, count 0 2006.182.08:07:31.59#ibcon#about to read 4, iclass 14, count 0 2006.182.08:07:31.59#ibcon#read 4, iclass 14, count 0 2006.182.08:07:31.59#ibcon#about to read 5, iclass 14, count 0 2006.182.08:07:31.59#ibcon#read 5, iclass 14, count 0 2006.182.08:07:31.59#ibcon#about to read 6, iclass 14, count 0 2006.182.08:07:31.59#ibcon#read 6, iclass 14, count 0 2006.182.08:07:31.59#ibcon#end of sib2, iclass 14, count 0 2006.182.08:07:31.59#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:07:31.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:07:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:07:31.59#ibcon#*before write, iclass 14, count 0 2006.182.08:07:31.59#ibcon#enter sib2, iclass 14, count 0 2006.182.08:07:31.59#ibcon#flushed, iclass 14, count 0 2006.182.08:07:31.59#ibcon#about to write, iclass 14, count 0 2006.182.08:07:31.59#ibcon#wrote, iclass 14, count 0 2006.182.08:07:31.59#ibcon#about to read 3, iclass 14, count 0 2006.182.08:07:31.63#ibcon#read 3, iclass 14, count 0 2006.182.08:07:31.63#ibcon#about to read 4, iclass 14, count 0 2006.182.08:07:31.63#ibcon#read 4, iclass 14, count 0 2006.182.08:07:31.63#ibcon#about to read 5, iclass 14, count 0 2006.182.08:07:31.63#ibcon#read 5, iclass 14, count 0 2006.182.08:07:31.63#ibcon#about to read 6, iclass 14, count 0 2006.182.08:07:31.63#ibcon#read 6, iclass 14, count 0 2006.182.08:07:31.63#ibcon#end of sib2, iclass 14, count 0 2006.182.08:07:31.63#ibcon#*after write, iclass 14, count 0 2006.182.08:07:31.63#ibcon#*before return 0, iclass 14, count 0 2006.182.08:07:31.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:31.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:07:31.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:07:31.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:07:31.63$vc4f8/vb=4,4 2006.182.08:07:31.63#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.08:07:31.63#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.08:07:31.63#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:31.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:31.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:31.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:31.69#ibcon#enter wrdev, iclass 16, count 2 2006.182.08:07:31.69#ibcon#first serial, iclass 16, count 2 2006.182.08:07:31.69#ibcon#enter sib2, iclass 16, count 2 2006.182.08:07:31.69#ibcon#flushed, iclass 16, count 2 2006.182.08:07:31.69#ibcon#about to write, iclass 16, count 2 2006.182.08:07:31.69#ibcon#wrote, iclass 16, count 2 2006.182.08:07:31.69#ibcon#about to read 3, iclass 16, count 2 2006.182.08:07:31.71#ibcon#read 3, iclass 16, count 2 2006.182.08:07:31.71#ibcon#about to read 4, iclass 16, count 2 2006.182.08:07:31.71#ibcon#read 4, iclass 16, count 2 2006.182.08:07:31.71#ibcon#about to read 5, iclass 16, count 2 2006.182.08:07:31.71#ibcon#read 5, iclass 16, count 2 2006.182.08:07:31.71#ibcon#about to read 6, iclass 16, count 2 2006.182.08:07:31.71#ibcon#read 6, iclass 16, count 2 2006.182.08:07:31.71#ibcon#end of sib2, iclass 16, count 2 2006.182.08:07:31.71#ibcon#*mode == 0, iclass 16, count 2 2006.182.08:07:31.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.08:07:31.71#ibcon#[27=AT04-04\r\n] 2006.182.08:07:31.71#ibcon#*before write, iclass 16, count 2 2006.182.08:07:31.71#ibcon#enter sib2, iclass 16, count 2 2006.182.08:07:31.71#ibcon#flushed, iclass 16, count 2 2006.182.08:07:31.71#ibcon#about to write, iclass 16, count 2 2006.182.08:07:31.71#ibcon#wrote, iclass 16, count 2 2006.182.08:07:31.71#ibcon#about to read 3, iclass 16, count 2 2006.182.08:07:31.74#ibcon#read 3, iclass 16, count 2 2006.182.08:07:31.74#ibcon#about to read 4, iclass 16, count 2 2006.182.08:07:31.74#ibcon#read 4, iclass 16, count 2 2006.182.08:07:31.74#ibcon#about to read 5, iclass 16, count 2 2006.182.08:07:31.74#ibcon#read 5, iclass 16, count 2 2006.182.08:07:31.74#ibcon#about to read 6, iclass 16, count 2 2006.182.08:07:31.74#ibcon#read 6, iclass 16, count 2 2006.182.08:07:31.74#ibcon#end of sib2, iclass 16, count 2 2006.182.08:07:31.74#ibcon#*after write, iclass 16, count 2 2006.182.08:07:31.74#ibcon#*before return 0, iclass 16, count 2 2006.182.08:07:31.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:31.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:07:31.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.08:07:31.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:31.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:31.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:31.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:31.86#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:07:31.86#ibcon#first serial, iclass 16, count 0 2006.182.08:07:31.86#ibcon#enter sib2, iclass 16, count 0 2006.182.08:07:31.86#ibcon#flushed, iclass 16, count 0 2006.182.08:07:31.86#ibcon#about to write, iclass 16, count 0 2006.182.08:07:31.86#ibcon#wrote, iclass 16, count 0 2006.182.08:07:31.86#ibcon#about to read 3, iclass 16, count 0 2006.182.08:07:31.88#ibcon#read 3, iclass 16, count 0 2006.182.08:07:31.88#ibcon#about to read 4, iclass 16, count 0 2006.182.08:07:31.88#ibcon#read 4, iclass 16, count 0 2006.182.08:07:31.88#ibcon#about to read 5, iclass 16, count 0 2006.182.08:07:31.88#ibcon#read 5, iclass 16, count 0 2006.182.08:07:31.88#ibcon#about to read 6, iclass 16, count 0 2006.182.08:07:31.88#ibcon#read 6, iclass 16, count 0 2006.182.08:07:31.88#ibcon#end of sib2, iclass 16, count 0 2006.182.08:07:31.88#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:07:31.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:07:31.88#ibcon#[27=USB\r\n] 2006.182.08:07:31.88#ibcon#*before write, iclass 16, count 0 2006.182.08:07:31.88#ibcon#enter sib2, iclass 16, count 0 2006.182.08:07:31.88#ibcon#flushed, iclass 16, count 0 2006.182.08:07:31.88#ibcon#about to write, iclass 16, count 0 2006.182.08:07:31.88#ibcon#wrote, iclass 16, count 0 2006.182.08:07:31.88#ibcon#about to read 3, iclass 16, count 0 2006.182.08:07:31.91#ibcon#read 3, iclass 16, count 0 2006.182.08:07:31.91#ibcon#about to read 4, iclass 16, count 0 2006.182.08:07:31.91#ibcon#read 4, iclass 16, count 0 2006.182.08:07:31.91#ibcon#about to read 5, iclass 16, count 0 2006.182.08:07:31.91#ibcon#read 5, iclass 16, count 0 2006.182.08:07:31.91#ibcon#about to read 6, iclass 16, count 0 2006.182.08:07:31.91#ibcon#read 6, iclass 16, count 0 2006.182.08:07:31.91#ibcon#end of sib2, iclass 16, count 0 2006.182.08:07:31.91#ibcon#*after write, iclass 16, count 0 2006.182.08:07:31.91#ibcon#*before return 0, iclass 16, count 0 2006.182.08:07:31.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:31.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:07:31.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:07:31.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:07:31.91$vc4f8/vblo=5,744.99 2006.182.08:07:31.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.08:07:31.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.08:07:31.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:31.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:31.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:31.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:31.91#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:07:31.91#ibcon#first serial, iclass 18, count 0 2006.182.08:07:31.91#ibcon#enter sib2, iclass 18, count 0 2006.182.08:07:31.91#ibcon#flushed, iclass 18, count 0 2006.182.08:07:31.91#ibcon#about to write, iclass 18, count 0 2006.182.08:07:31.91#ibcon#wrote, iclass 18, count 0 2006.182.08:07:31.91#ibcon#about to read 3, iclass 18, count 0 2006.182.08:07:31.93#ibcon#read 3, iclass 18, count 0 2006.182.08:07:31.93#ibcon#about to read 4, iclass 18, count 0 2006.182.08:07:31.93#ibcon#read 4, iclass 18, count 0 2006.182.08:07:31.93#ibcon#about to read 5, iclass 18, count 0 2006.182.08:07:31.93#ibcon#read 5, iclass 18, count 0 2006.182.08:07:31.93#ibcon#about to read 6, iclass 18, count 0 2006.182.08:07:31.93#ibcon#read 6, iclass 18, count 0 2006.182.08:07:31.93#ibcon#end of sib2, iclass 18, count 0 2006.182.08:07:31.93#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:07:31.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:07:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:07:31.93#ibcon#*before write, iclass 18, count 0 2006.182.08:07:31.93#ibcon#enter sib2, iclass 18, count 0 2006.182.08:07:31.93#ibcon#flushed, iclass 18, count 0 2006.182.08:07:31.93#ibcon#about to write, iclass 18, count 0 2006.182.08:07:31.93#ibcon#wrote, iclass 18, count 0 2006.182.08:07:31.93#ibcon#about to read 3, iclass 18, count 0 2006.182.08:07:31.97#ibcon#read 3, iclass 18, count 0 2006.182.08:07:31.97#ibcon#about to read 4, iclass 18, count 0 2006.182.08:07:31.97#ibcon#read 4, iclass 18, count 0 2006.182.08:07:31.97#ibcon#about to read 5, iclass 18, count 0 2006.182.08:07:31.97#ibcon#read 5, iclass 18, count 0 2006.182.08:07:31.97#ibcon#about to read 6, iclass 18, count 0 2006.182.08:07:31.97#ibcon#read 6, iclass 18, count 0 2006.182.08:07:31.97#ibcon#end of sib2, iclass 18, count 0 2006.182.08:07:31.97#ibcon#*after write, iclass 18, count 0 2006.182.08:07:31.97#ibcon#*before return 0, iclass 18, count 0 2006.182.08:07:31.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:31.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:07:31.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:07:31.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:07:31.97$vc4f8/vb=5,4 2006.182.08:07:31.97#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.08:07:31.97#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.08:07:31.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:31.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:32.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:32.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:32.03#ibcon#enter wrdev, iclass 20, count 2 2006.182.08:07:32.03#ibcon#first serial, iclass 20, count 2 2006.182.08:07:32.03#ibcon#enter sib2, iclass 20, count 2 2006.182.08:07:32.03#ibcon#flushed, iclass 20, count 2 2006.182.08:07:32.03#ibcon#about to write, iclass 20, count 2 2006.182.08:07:32.03#ibcon#wrote, iclass 20, count 2 2006.182.08:07:32.03#ibcon#about to read 3, iclass 20, count 2 2006.182.08:07:32.05#ibcon#read 3, iclass 20, count 2 2006.182.08:07:32.05#ibcon#about to read 4, iclass 20, count 2 2006.182.08:07:32.05#ibcon#read 4, iclass 20, count 2 2006.182.08:07:32.05#ibcon#about to read 5, iclass 20, count 2 2006.182.08:07:32.05#ibcon#read 5, iclass 20, count 2 2006.182.08:07:32.05#ibcon#about to read 6, iclass 20, count 2 2006.182.08:07:32.05#ibcon#read 6, iclass 20, count 2 2006.182.08:07:32.05#ibcon#end of sib2, iclass 20, count 2 2006.182.08:07:32.05#ibcon#*mode == 0, iclass 20, count 2 2006.182.08:07:32.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.08:07:32.05#ibcon#[27=AT05-04\r\n] 2006.182.08:07:32.05#ibcon#*before write, iclass 20, count 2 2006.182.08:07:32.05#ibcon#enter sib2, iclass 20, count 2 2006.182.08:07:32.05#ibcon#flushed, iclass 20, count 2 2006.182.08:07:32.05#ibcon#about to write, iclass 20, count 2 2006.182.08:07:32.05#ibcon#wrote, iclass 20, count 2 2006.182.08:07:32.05#ibcon#about to read 3, iclass 20, count 2 2006.182.08:07:32.08#ibcon#read 3, iclass 20, count 2 2006.182.08:07:32.08#ibcon#about to read 4, iclass 20, count 2 2006.182.08:07:32.08#ibcon#read 4, iclass 20, count 2 2006.182.08:07:32.08#ibcon#about to read 5, iclass 20, count 2 2006.182.08:07:32.08#ibcon#read 5, iclass 20, count 2 2006.182.08:07:32.08#ibcon#about to read 6, iclass 20, count 2 2006.182.08:07:32.08#ibcon#read 6, iclass 20, count 2 2006.182.08:07:32.08#ibcon#end of sib2, iclass 20, count 2 2006.182.08:07:32.08#ibcon#*after write, iclass 20, count 2 2006.182.08:07:32.08#ibcon#*before return 0, iclass 20, count 2 2006.182.08:07:32.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:32.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:07:32.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.08:07:32.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:32.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:32.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:32.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:32.20#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:07:32.20#ibcon#first serial, iclass 20, count 0 2006.182.08:07:32.20#ibcon#enter sib2, iclass 20, count 0 2006.182.08:07:32.20#ibcon#flushed, iclass 20, count 0 2006.182.08:07:32.20#ibcon#about to write, iclass 20, count 0 2006.182.08:07:32.20#ibcon#wrote, iclass 20, count 0 2006.182.08:07:32.20#ibcon#about to read 3, iclass 20, count 0 2006.182.08:07:32.24#ibcon#read 3, iclass 20, count 0 2006.182.08:07:32.24#ibcon#about to read 4, iclass 20, count 0 2006.182.08:07:32.24#ibcon#read 4, iclass 20, count 0 2006.182.08:07:32.24#ibcon#about to read 5, iclass 20, count 0 2006.182.08:07:32.24#ibcon#read 5, iclass 20, count 0 2006.182.08:07:32.24#ibcon#about to read 6, iclass 20, count 0 2006.182.08:07:32.24#ibcon#read 6, iclass 20, count 0 2006.182.08:07:32.24#ibcon#end of sib2, iclass 20, count 0 2006.182.08:07:32.24#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:07:32.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:07:32.24#ibcon#[27=USB\r\n] 2006.182.08:07:32.24#ibcon#*before write, iclass 20, count 0 2006.182.08:07:32.24#ibcon#enter sib2, iclass 20, count 0 2006.182.08:07:32.24#ibcon#flushed, iclass 20, count 0 2006.182.08:07:32.24#ibcon#about to write, iclass 20, count 0 2006.182.08:07:32.24#ibcon#wrote, iclass 20, count 0 2006.182.08:07:32.24#ibcon#about to read 3, iclass 20, count 0 2006.182.08:07:32.26#ibcon#read 3, iclass 20, count 0 2006.182.08:07:32.26#ibcon#about to read 4, iclass 20, count 0 2006.182.08:07:32.26#ibcon#read 4, iclass 20, count 0 2006.182.08:07:32.26#ibcon#about to read 5, iclass 20, count 0 2006.182.08:07:32.26#ibcon#read 5, iclass 20, count 0 2006.182.08:07:32.26#ibcon#about to read 6, iclass 20, count 0 2006.182.08:07:32.26#ibcon#read 6, iclass 20, count 0 2006.182.08:07:32.26#ibcon#end of sib2, iclass 20, count 0 2006.182.08:07:32.26#ibcon#*after write, iclass 20, count 0 2006.182.08:07:32.26#ibcon#*before return 0, iclass 20, count 0 2006.182.08:07:32.26#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:32.26#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:07:32.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:07:32.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:07:32.26$vc4f8/vblo=6,752.99 2006.182.08:07:32.26#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.08:07:32.26#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.08:07:32.26#ibcon#ireg 17 cls_cnt 0 2006.182.08:07:32.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:32.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:32.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:32.26#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:07:32.26#ibcon#first serial, iclass 22, count 0 2006.182.08:07:32.26#ibcon#enter sib2, iclass 22, count 0 2006.182.08:07:32.26#ibcon#flushed, iclass 22, count 0 2006.182.08:07:32.26#ibcon#about to write, iclass 22, count 0 2006.182.08:07:32.26#ibcon#wrote, iclass 22, count 0 2006.182.08:07:32.26#ibcon#about to read 3, iclass 22, count 0 2006.182.08:07:32.28#ibcon#read 3, iclass 22, count 0 2006.182.08:07:32.28#ibcon#about to read 4, iclass 22, count 0 2006.182.08:07:32.28#ibcon#read 4, iclass 22, count 0 2006.182.08:07:32.28#ibcon#about to read 5, iclass 22, count 0 2006.182.08:07:32.28#ibcon#read 5, iclass 22, count 0 2006.182.08:07:32.28#ibcon#about to read 6, iclass 22, count 0 2006.182.08:07:32.28#ibcon#read 6, iclass 22, count 0 2006.182.08:07:32.28#ibcon#end of sib2, iclass 22, count 0 2006.182.08:07:32.28#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:07:32.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:07:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:07:32.28#ibcon#*before write, iclass 22, count 0 2006.182.08:07:32.28#ibcon#enter sib2, iclass 22, count 0 2006.182.08:07:32.28#ibcon#flushed, iclass 22, count 0 2006.182.08:07:32.28#ibcon#about to write, iclass 22, count 0 2006.182.08:07:32.28#ibcon#wrote, iclass 22, count 0 2006.182.08:07:32.28#ibcon#about to read 3, iclass 22, count 0 2006.182.08:07:32.32#ibcon#read 3, iclass 22, count 0 2006.182.08:07:32.32#ibcon#about to read 4, iclass 22, count 0 2006.182.08:07:32.32#ibcon#read 4, iclass 22, count 0 2006.182.08:07:32.32#ibcon#about to read 5, iclass 22, count 0 2006.182.08:07:32.32#ibcon#read 5, iclass 22, count 0 2006.182.08:07:32.32#ibcon#about to read 6, iclass 22, count 0 2006.182.08:07:32.32#ibcon#read 6, iclass 22, count 0 2006.182.08:07:32.32#ibcon#end of sib2, iclass 22, count 0 2006.182.08:07:32.32#ibcon#*after write, iclass 22, count 0 2006.182.08:07:32.32#ibcon#*before return 0, iclass 22, count 0 2006.182.08:07:32.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:32.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:07:32.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:07:32.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:07:32.32$vc4f8/vb=6,4 2006.182.08:07:32.32#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.08:07:32.32#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.08:07:32.32#ibcon#ireg 11 cls_cnt 2 2006.182.08:07:32.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:32.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:32.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:32.38#ibcon#enter wrdev, iclass 24, count 2 2006.182.08:07:32.38#ibcon#first serial, iclass 24, count 2 2006.182.08:07:32.38#ibcon#enter sib2, iclass 24, count 2 2006.182.08:07:32.38#ibcon#flushed, iclass 24, count 2 2006.182.08:07:32.38#ibcon#about to write, iclass 24, count 2 2006.182.08:07:32.38#ibcon#wrote, iclass 24, count 2 2006.182.08:07:32.38#ibcon#about to read 3, iclass 24, count 2 2006.182.08:07:32.40#ibcon#read 3, iclass 24, count 2 2006.182.08:07:32.40#ibcon#about to read 4, iclass 24, count 2 2006.182.08:07:32.40#ibcon#read 4, iclass 24, count 2 2006.182.08:07:32.40#ibcon#about to read 5, iclass 24, count 2 2006.182.08:07:32.40#ibcon#read 5, iclass 24, count 2 2006.182.08:07:32.40#ibcon#about to read 6, iclass 24, count 2 2006.182.08:07:32.40#ibcon#read 6, iclass 24, count 2 2006.182.08:07:32.40#ibcon#end of sib2, iclass 24, count 2 2006.182.08:07:32.40#ibcon#*mode == 0, iclass 24, count 2 2006.182.08:07:32.40#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.08:07:32.40#ibcon#[27=AT06-04\r\n] 2006.182.08:07:32.40#ibcon#*before write, iclass 24, count 2 2006.182.08:07:32.40#ibcon#enter sib2, iclass 24, count 2 2006.182.08:07:32.40#ibcon#flushed, iclass 24, count 2 2006.182.08:07:32.40#ibcon#about to write, iclass 24, count 2 2006.182.08:07:32.40#ibcon#wrote, iclass 24, count 2 2006.182.08:07:32.40#ibcon#about to read 3, iclass 24, count 2 2006.182.08:07:32.43#ibcon#read 3, iclass 24, count 2 2006.182.08:07:32.43#ibcon#about to read 4, iclass 24, count 2 2006.182.08:07:32.43#ibcon#read 4, iclass 24, count 2 2006.182.08:07:32.43#ibcon#about to read 5, iclass 24, count 2 2006.182.08:07:32.43#ibcon#read 5, iclass 24, count 2 2006.182.08:07:32.43#ibcon#about to read 6, iclass 24, count 2 2006.182.08:07:32.43#ibcon#read 6, iclass 24, count 2 2006.182.08:07:32.43#ibcon#end of sib2, iclass 24, count 2 2006.182.08:07:32.43#ibcon#*after write, iclass 24, count 2 2006.182.08:07:32.43#ibcon#*before return 0, iclass 24, count 2 2006.182.08:07:32.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:32.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:07:32.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.08:07:32.43#ibcon#ireg 7 cls_cnt 0 2006.182.08:07:32.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:32.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:32.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:32.55#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:07:32.55#ibcon#first serial, iclass 24, count 0 2006.182.08:07:32.55#ibcon#enter sib2, iclass 24, count 0 2006.182.08:07:32.55#ibcon#flushed, iclass 24, count 0 2006.182.08:07:32.55#ibcon#about to write, iclass 24, count 0 2006.182.08:07:32.55#ibcon#wrote, iclass 24, count 0 2006.182.08:07:32.55#ibcon#about to read 3, iclass 24, count 0 2006.182.08:07:32.57#ibcon#read 3, iclass 24, count 0 2006.182.08:07:32.57#ibcon#about to read 4, iclass 24, count 0 2006.182.08:07:32.57#ibcon#read 4, iclass 24, count 0 2006.182.08:07:32.57#ibcon#about to read 5, iclass 24, count 0 2006.182.08:07:32.57#ibcon#read 5, iclass 24, count 0 2006.182.08:07:32.57#ibcon#about to read 6, iclass 24, count 0 2006.182.08:07:32.57#ibcon#read 6, iclass 24, count 0 2006.182.08:07:32.57#ibcon#end of sib2, iclass 24, count 0 2006.182.08:07:32.57#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:07:32.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:07:32.57#ibcon#[27=USB\r\n] 2006.182.08:07:32.57#ibcon#*before write, iclass 24, count 0 2006.182.08:07:32.57#ibcon#enter sib2, iclass 24, count 0 2006.182.08:07:32.57#ibcon#flushed, iclass 24, count 0 2006.182.08:07:32.57#ibcon#about to write, iclass 24, count 0 2006.182.08:07:32.57#ibcon#wrote, iclass 24, count 0 2006.182.08:07:32.57#ibcon#about to read 3, iclass 24, count 0 2006.182.08:07:32.60#ibcon#read 3, iclass 24, count 0 2006.182.08:07:32.60#ibcon#about to read 4, iclass 24, count 0 2006.182.08:07:32.60#ibcon#read 4, iclass 24, count 0 2006.182.08:07:32.60#ibcon#about to read 5, iclass 24, count 0 2006.182.08:07:32.60#ibcon#read 5, iclass 24, count 0 2006.182.08:07:32.60#ibcon#about to read 6, iclass 24, count 0 2006.182.08:07:32.60#ibcon#read 6, iclass 24, count 0 2006.182.08:07:32.60#ibcon#end of sib2, iclass 24, count 0 2006.182.08:07:32.60#ibcon#*after write, iclass 24, count 0 2006.182.08:07:32.60#ibcon#*before return 0, iclass 24, count 0 2006.182.08:07:32.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:32.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:07:32.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:07:32.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:07:32.60$vc4f8/vabw=wide 2006.182.08:07:32.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.08:07:32.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.08:07:32.60#ibcon#ireg 8 cls_cnt 0 2006.182.08:07:32.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:32.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:32.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:32.60#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:07:32.60#ibcon#first serial, iclass 26, count 0 2006.182.08:07:32.60#ibcon#enter sib2, iclass 26, count 0 2006.182.08:07:32.60#ibcon#flushed, iclass 26, count 0 2006.182.08:07:32.60#ibcon#about to write, iclass 26, count 0 2006.182.08:07:32.60#ibcon#wrote, iclass 26, count 0 2006.182.08:07:32.60#ibcon#about to read 3, iclass 26, count 0 2006.182.08:07:32.62#ibcon#read 3, iclass 26, count 0 2006.182.08:07:32.62#ibcon#about to read 4, iclass 26, count 0 2006.182.08:07:32.62#ibcon#read 4, iclass 26, count 0 2006.182.08:07:32.62#ibcon#about to read 5, iclass 26, count 0 2006.182.08:07:32.62#ibcon#read 5, iclass 26, count 0 2006.182.08:07:32.62#ibcon#about to read 6, iclass 26, count 0 2006.182.08:07:32.62#ibcon#read 6, iclass 26, count 0 2006.182.08:07:32.62#ibcon#end of sib2, iclass 26, count 0 2006.182.08:07:32.62#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:07:32.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:07:32.62#ibcon#[25=BW32\r\n] 2006.182.08:07:32.62#ibcon#*before write, iclass 26, count 0 2006.182.08:07:32.62#ibcon#enter sib2, iclass 26, count 0 2006.182.08:07:32.62#ibcon#flushed, iclass 26, count 0 2006.182.08:07:32.62#ibcon#about to write, iclass 26, count 0 2006.182.08:07:32.62#ibcon#wrote, iclass 26, count 0 2006.182.08:07:32.62#ibcon#about to read 3, iclass 26, count 0 2006.182.08:07:32.65#ibcon#read 3, iclass 26, count 0 2006.182.08:07:32.65#ibcon#about to read 4, iclass 26, count 0 2006.182.08:07:32.65#ibcon#read 4, iclass 26, count 0 2006.182.08:07:32.65#ibcon#about to read 5, iclass 26, count 0 2006.182.08:07:32.65#ibcon#read 5, iclass 26, count 0 2006.182.08:07:32.65#ibcon#about to read 6, iclass 26, count 0 2006.182.08:07:32.65#ibcon#read 6, iclass 26, count 0 2006.182.08:07:32.65#ibcon#end of sib2, iclass 26, count 0 2006.182.08:07:32.65#ibcon#*after write, iclass 26, count 0 2006.182.08:07:32.65#ibcon#*before return 0, iclass 26, count 0 2006.182.08:07:32.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:32.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:07:32.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:07:32.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:07:32.65$vc4f8/vbbw=wide 2006.182.08:07:32.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.08:07:32.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.08:07:32.65#ibcon#ireg 8 cls_cnt 0 2006.182.08:07:32.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:07:32.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:07:32.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:07:32.72#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:07:32.72#ibcon#first serial, iclass 28, count 0 2006.182.08:07:32.72#ibcon#enter sib2, iclass 28, count 0 2006.182.08:07:32.72#ibcon#flushed, iclass 28, count 0 2006.182.08:07:32.72#ibcon#about to write, iclass 28, count 0 2006.182.08:07:32.72#ibcon#wrote, iclass 28, count 0 2006.182.08:07:32.72#ibcon#about to read 3, iclass 28, count 0 2006.182.08:07:32.74#ibcon#read 3, iclass 28, count 0 2006.182.08:07:32.74#ibcon#about to read 4, iclass 28, count 0 2006.182.08:07:32.74#ibcon#read 4, iclass 28, count 0 2006.182.08:07:32.74#ibcon#about to read 5, iclass 28, count 0 2006.182.08:07:32.74#ibcon#read 5, iclass 28, count 0 2006.182.08:07:32.74#ibcon#about to read 6, iclass 28, count 0 2006.182.08:07:32.74#ibcon#read 6, iclass 28, count 0 2006.182.08:07:32.74#ibcon#end of sib2, iclass 28, count 0 2006.182.08:07:32.74#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:07:32.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:07:32.74#ibcon#[27=BW32\r\n] 2006.182.08:07:32.74#ibcon#*before write, iclass 28, count 0 2006.182.08:07:32.74#ibcon#enter sib2, iclass 28, count 0 2006.182.08:07:32.74#ibcon#flushed, iclass 28, count 0 2006.182.08:07:32.74#ibcon#about to write, iclass 28, count 0 2006.182.08:07:32.74#ibcon#wrote, iclass 28, count 0 2006.182.08:07:32.74#ibcon#about to read 3, iclass 28, count 0 2006.182.08:07:32.77#ibcon#read 3, iclass 28, count 0 2006.182.08:07:32.77#ibcon#about to read 4, iclass 28, count 0 2006.182.08:07:32.77#ibcon#read 4, iclass 28, count 0 2006.182.08:07:32.77#ibcon#about to read 5, iclass 28, count 0 2006.182.08:07:32.77#ibcon#read 5, iclass 28, count 0 2006.182.08:07:32.77#ibcon#about to read 6, iclass 28, count 0 2006.182.08:07:32.77#ibcon#read 6, iclass 28, count 0 2006.182.08:07:32.77#ibcon#end of sib2, iclass 28, count 0 2006.182.08:07:32.77#ibcon#*after write, iclass 28, count 0 2006.182.08:07:32.77#ibcon#*before return 0, iclass 28, count 0 2006.182.08:07:32.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:07:32.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:07:32.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:07:32.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:07:32.77$4f8m12a/ifd4f 2006.182.08:07:32.77$ifd4f/lo= 2006.182.08:07:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:07:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:07:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:07:32.77$ifd4f/patch= 2006.182.08:07:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:07:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:07:32.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:07:32.77$4f8m12a/"form=m,16.000,1:2 2006.182.08:07:32.77$4f8m12a/"tpicd 2006.182.08:07:32.77$4f8m12a/echo=off 2006.182.08:07:32.77$4f8m12a/xlog=off 2006.182.08:07:32.77:!2006.182.08:08:00 2006.182.08:07:47.14#trakl#Source acquired 2006.182.08:07:48.14#flagr#flagr/antenna,acquired 2006.182.08:08:00.00:preob 2006.182.08:08:01.14/onsource/TRACKING 2006.182.08:08:01.14:!2006.182.08:08:10 2006.182.08:08:10.00:data_valid=on 2006.182.08:08:10.00:midob 2006.182.08:08:10.14/onsource/TRACKING 2006.182.08:08:10.14/wx/27.88,1002.9,83 2006.182.08:08:10.29/cable/+6.4647E-03 2006.182.08:08:11.38/va/01,08,usb,yes,28,30 2006.182.08:08:11.38/va/02,07,usb,yes,29,30 2006.182.08:08:11.38/va/03,06,usb,yes,30,30 2006.182.08:08:11.38/va/04,07,usb,yes,30,32 2006.182.08:08:11.38/va/05,07,usb,yes,31,32 2006.182.08:08:11.38/va/06,06,usb,yes,30,30 2006.182.08:08:11.38/va/07,06,usb,yes,30,30 2006.182.08:08:11.38/va/08,07,usb,yes,29,28 2006.182.08:08:11.61/valo/01,532.99,yes,locked 2006.182.08:08:11.61/valo/02,572.99,yes,locked 2006.182.08:08:11.61/valo/03,672.99,yes,locked 2006.182.08:08:11.61/valo/04,832.99,yes,locked 2006.182.08:08:11.61/valo/05,652.99,yes,locked 2006.182.08:08:11.61/valo/06,772.99,yes,locked 2006.182.08:08:11.61/valo/07,832.99,yes,locked 2006.182.08:08:11.61/valo/08,852.99,yes,locked 2006.182.08:08:12.70/vb/01,04,usb,yes,29,28 2006.182.08:08:12.70/vb/02,04,usb,yes,31,32 2006.182.08:08:12.70/vb/03,04,usb,yes,27,31 2006.182.08:08:12.70/vb/04,04,usb,yes,28,28 2006.182.08:08:12.70/vb/05,04,usb,yes,27,30 2006.182.08:08:12.70/vb/06,04,usb,yes,28,30 2006.182.08:08:12.70/vb/07,04,usb,yes,29,29 2006.182.08:08:12.70/vb/08,04,usb,yes,27,30 2006.182.08:08:12.93/vblo/01,632.99,yes,locked 2006.182.08:08:12.93/vblo/02,640.99,yes,locked 2006.182.08:08:12.93/vblo/03,656.99,yes,locked 2006.182.08:08:12.93/vblo/04,712.99,yes,locked 2006.182.08:08:12.93/vblo/05,744.99,yes,locked 2006.182.08:08:12.93/vblo/06,752.99,yes,locked 2006.182.08:08:12.93/vblo/07,734.99,yes,locked 2006.182.08:08:12.93/vblo/08,744.99,yes,locked 2006.182.08:08:13.08/vabw/8 2006.182.08:08:13.23/vbbw/8 2006.182.08:08:13.32/xfe/off,on,14.7 2006.182.08:08:13.71/ifatt/23,28,28,28 2006.182.08:08:14.07/fmout-gps/S +3.43E-07 2006.182.08:08:14.15:!2006.182.08:09:10 2006.182.08:09:10.00:data_valid=off 2006.182.08:09:10.01:postob 2006.182.08:09:10.09/cable/+6.4636E-03 2006.182.08:09:10.10/wx/27.90,1002.8,83 2006.182.08:09:11.07/fmout-gps/S +3.45E-07 2006.182.08:09:11.08:scan_name=182-0810,k06182,60 2006.182.08:09:11.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.182.08:09:11.14#flagr#flagr/antenna,new-source 2006.182.08:09:12.14:checkk5 2006.182.08:09:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:09:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:09:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:09:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:09:14.01/chk_obsdata//k5ts1/T1820808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:09:14.38/chk_obsdata//k5ts2/T1820808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:09:14.76/chk_obsdata//k5ts3/T1820808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:09:15.13/chk_obsdata//k5ts4/T1820808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:09:15.83/k5log//k5ts1_log_newline 2006.182.08:09:16.51/k5log//k5ts2_log_newline 2006.182.08:09:17.26/k5log//k5ts3_log_newline 2006.182.08:09:18.02/k5log//k5ts4_log_newline 2006.182.08:09:18.05/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:09:18.05:4f8m12a=2 2006.182.08:09:18.05$4f8m12a/echo=on 2006.182.08:09:18.05$4f8m12a/pcalon 2006.182.08:09:18.05$pcalon/"no phase cal control is implemented here 2006.182.08:09:18.05$4f8m12a/"tpicd=stop 2006.182.08:09:18.05$4f8m12a/vc4f8 2006.182.08:09:18.05$vc4f8/valo=1,532.99 2006.182.08:09:18.05#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.08:09:18.05#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.08:09:18.05#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:18.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:18.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:18.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:18.05#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:09:18.05#ibcon#first serial, iclass 35, count 0 2006.182.08:09:18.05#ibcon#enter sib2, iclass 35, count 0 2006.182.08:09:18.05#ibcon#flushed, iclass 35, count 0 2006.182.08:09:18.05#ibcon#about to write, iclass 35, count 0 2006.182.08:09:18.05#ibcon#wrote, iclass 35, count 0 2006.182.08:09:18.05#ibcon#about to read 3, iclass 35, count 0 2006.182.08:09:18.08#ibcon#read 3, iclass 35, count 0 2006.182.08:09:18.08#ibcon#about to read 4, iclass 35, count 0 2006.182.08:09:18.08#ibcon#read 4, iclass 35, count 0 2006.182.08:09:18.08#ibcon#about to read 5, iclass 35, count 0 2006.182.08:09:18.08#ibcon#read 5, iclass 35, count 0 2006.182.08:09:18.08#ibcon#about to read 6, iclass 35, count 0 2006.182.08:09:18.08#ibcon#read 6, iclass 35, count 0 2006.182.08:09:18.08#ibcon#end of sib2, iclass 35, count 0 2006.182.08:09:18.08#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:09:18.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:09:18.08#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:09:18.08#ibcon#*before write, iclass 35, count 0 2006.182.08:09:18.08#ibcon#enter sib2, iclass 35, count 0 2006.182.08:09:18.08#ibcon#flushed, iclass 35, count 0 2006.182.08:09:18.08#ibcon#about to write, iclass 35, count 0 2006.182.08:09:18.08#ibcon#wrote, iclass 35, count 0 2006.182.08:09:18.08#ibcon#about to read 3, iclass 35, count 0 2006.182.08:09:18.13#ibcon#read 3, iclass 35, count 0 2006.182.08:09:18.13#ibcon#about to read 4, iclass 35, count 0 2006.182.08:09:18.13#ibcon#read 4, iclass 35, count 0 2006.182.08:09:18.13#ibcon#about to read 5, iclass 35, count 0 2006.182.08:09:18.13#ibcon#read 5, iclass 35, count 0 2006.182.08:09:18.13#ibcon#about to read 6, iclass 35, count 0 2006.182.08:09:18.13#ibcon#read 6, iclass 35, count 0 2006.182.08:09:18.13#ibcon#end of sib2, iclass 35, count 0 2006.182.08:09:18.13#ibcon#*after write, iclass 35, count 0 2006.182.08:09:18.13#ibcon#*before return 0, iclass 35, count 0 2006.182.08:09:18.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:18.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:18.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:09:18.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:09:18.13$vc4f8/va=1,8 2006.182.08:09:18.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.08:09:18.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.08:09:18.13#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:18.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:18.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:18.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:18.13#ibcon#enter wrdev, iclass 37, count 2 2006.182.08:09:18.13#ibcon#first serial, iclass 37, count 2 2006.182.08:09:18.13#ibcon#enter sib2, iclass 37, count 2 2006.182.08:09:18.13#ibcon#flushed, iclass 37, count 2 2006.182.08:09:18.13#ibcon#about to write, iclass 37, count 2 2006.182.08:09:18.13#ibcon#wrote, iclass 37, count 2 2006.182.08:09:18.13#ibcon#about to read 3, iclass 37, count 2 2006.182.08:09:18.15#ibcon#read 3, iclass 37, count 2 2006.182.08:09:18.15#ibcon#about to read 4, iclass 37, count 2 2006.182.08:09:18.15#ibcon#read 4, iclass 37, count 2 2006.182.08:09:18.15#ibcon#about to read 5, iclass 37, count 2 2006.182.08:09:18.15#ibcon#read 5, iclass 37, count 2 2006.182.08:09:18.15#ibcon#about to read 6, iclass 37, count 2 2006.182.08:09:18.15#ibcon#read 6, iclass 37, count 2 2006.182.08:09:18.15#ibcon#end of sib2, iclass 37, count 2 2006.182.08:09:18.15#ibcon#*mode == 0, iclass 37, count 2 2006.182.08:09:18.15#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.08:09:18.15#ibcon#[25=AT01-08\r\n] 2006.182.08:09:18.15#ibcon#*before write, iclass 37, count 2 2006.182.08:09:18.15#ibcon#enter sib2, iclass 37, count 2 2006.182.08:09:18.15#ibcon#flushed, iclass 37, count 2 2006.182.08:09:18.15#ibcon#about to write, iclass 37, count 2 2006.182.08:09:18.15#ibcon#wrote, iclass 37, count 2 2006.182.08:09:18.15#ibcon#about to read 3, iclass 37, count 2 2006.182.08:09:18.18#ibcon#read 3, iclass 37, count 2 2006.182.08:09:18.18#ibcon#about to read 4, iclass 37, count 2 2006.182.08:09:18.18#ibcon#read 4, iclass 37, count 2 2006.182.08:09:18.18#ibcon#about to read 5, iclass 37, count 2 2006.182.08:09:18.18#ibcon#read 5, iclass 37, count 2 2006.182.08:09:18.18#ibcon#about to read 6, iclass 37, count 2 2006.182.08:09:18.18#ibcon#read 6, iclass 37, count 2 2006.182.08:09:18.18#ibcon#end of sib2, iclass 37, count 2 2006.182.08:09:18.18#ibcon#*after write, iclass 37, count 2 2006.182.08:09:18.18#ibcon#*before return 0, iclass 37, count 2 2006.182.08:09:18.18#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:18.18#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:18.18#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.08:09:18.18#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:18.18#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:18.30#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:18.30#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:18.30#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:09:18.30#ibcon#first serial, iclass 37, count 0 2006.182.08:09:18.30#ibcon#enter sib2, iclass 37, count 0 2006.182.08:09:18.30#ibcon#flushed, iclass 37, count 0 2006.182.08:09:18.30#ibcon#about to write, iclass 37, count 0 2006.182.08:09:18.30#ibcon#wrote, iclass 37, count 0 2006.182.08:09:18.30#ibcon#about to read 3, iclass 37, count 0 2006.182.08:09:18.32#ibcon#read 3, iclass 37, count 0 2006.182.08:09:18.32#ibcon#about to read 4, iclass 37, count 0 2006.182.08:09:18.32#ibcon#read 4, iclass 37, count 0 2006.182.08:09:18.32#ibcon#about to read 5, iclass 37, count 0 2006.182.08:09:18.32#ibcon#read 5, iclass 37, count 0 2006.182.08:09:18.32#ibcon#about to read 6, iclass 37, count 0 2006.182.08:09:18.32#ibcon#read 6, iclass 37, count 0 2006.182.08:09:18.32#ibcon#end of sib2, iclass 37, count 0 2006.182.08:09:18.32#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:09:18.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:09:18.32#ibcon#[25=USB\r\n] 2006.182.08:09:18.32#ibcon#*before write, iclass 37, count 0 2006.182.08:09:18.32#ibcon#enter sib2, iclass 37, count 0 2006.182.08:09:18.32#ibcon#flushed, iclass 37, count 0 2006.182.08:09:18.32#ibcon#about to write, iclass 37, count 0 2006.182.08:09:18.32#ibcon#wrote, iclass 37, count 0 2006.182.08:09:18.32#ibcon#about to read 3, iclass 37, count 0 2006.182.08:09:18.35#ibcon#read 3, iclass 37, count 0 2006.182.08:09:18.35#ibcon#about to read 4, iclass 37, count 0 2006.182.08:09:18.35#ibcon#read 4, iclass 37, count 0 2006.182.08:09:18.35#ibcon#about to read 5, iclass 37, count 0 2006.182.08:09:18.35#ibcon#read 5, iclass 37, count 0 2006.182.08:09:18.35#ibcon#about to read 6, iclass 37, count 0 2006.182.08:09:18.35#ibcon#read 6, iclass 37, count 0 2006.182.08:09:18.35#ibcon#end of sib2, iclass 37, count 0 2006.182.08:09:18.35#ibcon#*after write, iclass 37, count 0 2006.182.08:09:18.35#ibcon#*before return 0, iclass 37, count 0 2006.182.08:09:18.35#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:18.35#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:18.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:09:18.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:09:18.35$vc4f8/valo=2,572.99 2006.182.08:09:18.35#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.08:09:18.35#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.08:09:18.35#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:18.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:18.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:18.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:18.35#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:09:18.35#ibcon#first serial, iclass 39, count 0 2006.182.08:09:18.35#ibcon#enter sib2, iclass 39, count 0 2006.182.08:09:18.35#ibcon#flushed, iclass 39, count 0 2006.182.08:09:18.35#ibcon#about to write, iclass 39, count 0 2006.182.08:09:18.35#ibcon#wrote, iclass 39, count 0 2006.182.08:09:18.35#ibcon#about to read 3, iclass 39, count 0 2006.182.08:09:18.37#ibcon#read 3, iclass 39, count 0 2006.182.08:09:18.37#ibcon#about to read 4, iclass 39, count 0 2006.182.08:09:18.37#ibcon#read 4, iclass 39, count 0 2006.182.08:09:18.37#ibcon#about to read 5, iclass 39, count 0 2006.182.08:09:18.37#ibcon#read 5, iclass 39, count 0 2006.182.08:09:18.37#ibcon#about to read 6, iclass 39, count 0 2006.182.08:09:18.37#ibcon#read 6, iclass 39, count 0 2006.182.08:09:18.37#ibcon#end of sib2, iclass 39, count 0 2006.182.08:09:18.37#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:09:18.37#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:09:18.37#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:09:18.37#ibcon#*before write, iclass 39, count 0 2006.182.08:09:18.37#ibcon#enter sib2, iclass 39, count 0 2006.182.08:09:18.37#ibcon#flushed, iclass 39, count 0 2006.182.08:09:18.37#ibcon#about to write, iclass 39, count 0 2006.182.08:09:18.37#ibcon#wrote, iclass 39, count 0 2006.182.08:09:18.37#ibcon#about to read 3, iclass 39, count 0 2006.182.08:09:18.41#ibcon#read 3, iclass 39, count 0 2006.182.08:09:18.41#ibcon#about to read 4, iclass 39, count 0 2006.182.08:09:18.41#ibcon#read 4, iclass 39, count 0 2006.182.08:09:18.41#ibcon#about to read 5, iclass 39, count 0 2006.182.08:09:18.41#ibcon#read 5, iclass 39, count 0 2006.182.08:09:18.41#ibcon#about to read 6, iclass 39, count 0 2006.182.08:09:18.41#ibcon#read 6, iclass 39, count 0 2006.182.08:09:18.41#ibcon#end of sib2, iclass 39, count 0 2006.182.08:09:18.41#ibcon#*after write, iclass 39, count 0 2006.182.08:09:18.41#ibcon#*before return 0, iclass 39, count 0 2006.182.08:09:18.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:18.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:18.41#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:09:18.41#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:09:18.41$vc4f8/va=2,7 2006.182.08:09:18.41#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.08:09:18.41#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.08:09:18.41#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:18.41#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:18.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:18.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:18.48#ibcon#enter wrdev, iclass 3, count 2 2006.182.08:09:18.48#ibcon#first serial, iclass 3, count 2 2006.182.08:09:18.48#ibcon#enter sib2, iclass 3, count 2 2006.182.08:09:18.48#ibcon#flushed, iclass 3, count 2 2006.182.08:09:18.48#ibcon#about to write, iclass 3, count 2 2006.182.08:09:18.48#ibcon#wrote, iclass 3, count 2 2006.182.08:09:18.48#ibcon#about to read 3, iclass 3, count 2 2006.182.08:09:18.49#ibcon#read 3, iclass 3, count 2 2006.182.08:09:18.49#ibcon#about to read 4, iclass 3, count 2 2006.182.08:09:18.49#ibcon#read 4, iclass 3, count 2 2006.182.08:09:18.49#ibcon#about to read 5, iclass 3, count 2 2006.182.08:09:18.49#ibcon#read 5, iclass 3, count 2 2006.182.08:09:18.49#ibcon#about to read 6, iclass 3, count 2 2006.182.08:09:18.49#ibcon#read 6, iclass 3, count 2 2006.182.08:09:18.49#ibcon#end of sib2, iclass 3, count 2 2006.182.08:09:18.49#ibcon#*mode == 0, iclass 3, count 2 2006.182.08:09:18.49#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.08:09:18.49#ibcon#[25=AT02-07\r\n] 2006.182.08:09:18.49#ibcon#*before write, iclass 3, count 2 2006.182.08:09:18.49#ibcon#enter sib2, iclass 3, count 2 2006.182.08:09:18.49#ibcon#flushed, iclass 3, count 2 2006.182.08:09:18.49#ibcon#about to write, iclass 3, count 2 2006.182.08:09:18.49#ibcon#wrote, iclass 3, count 2 2006.182.08:09:18.49#ibcon#about to read 3, iclass 3, count 2 2006.182.08:09:18.52#ibcon#read 3, iclass 3, count 2 2006.182.08:09:18.52#ibcon#about to read 4, iclass 3, count 2 2006.182.08:09:18.52#ibcon#read 4, iclass 3, count 2 2006.182.08:09:18.52#ibcon#about to read 5, iclass 3, count 2 2006.182.08:09:18.52#ibcon#read 5, iclass 3, count 2 2006.182.08:09:18.52#ibcon#about to read 6, iclass 3, count 2 2006.182.08:09:18.52#ibcon#read 6, iclass 3, count 2 2006.182.08:09:18.52#ibcon#end of sib2, iclass 3, count 2 2006.182.08:09:18.52#ibcon#*after write, iclass 3, count 2 2006.182.08:09:18.52#ibcon#*before return 0, iclass 3, count 2 2006.182.08:09:18.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:18.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:18.52#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.08:09:18.52#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:18.52#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:18.64#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:18.64#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:18.64#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:09:18.64#ibcon#first serial, iclass 3, count 0 2006.182.08:09:18.64#ibcon#enter sib2, iclass 3, count 0 2006.182.08:09:18.64#ibcon#flushed, iclass 3, count 0 2006.182.08:09:18.64#ibcon#about to write, iclass 3, count 0 2006.182.08:09:18.64#ibcon#wrote, iclass 3, count 0 2006.182.08:09:18.64#ibcon#about to read 3, iclass 3, count 0 2006.182.08:09:18.66#ibcon#read 3, iclass 3, count 0 2006.182.08:09:18.66#ibcon#about to read 4, iclass 3, count 0 2006.182.08:09:18.66#ibcon#read 4, iclass 3, count 0 2006.182.08:09:18.66#ibcon#about to read 5, iclass 3, count 0 2006.182.08:09:18.66#ibcon#read 5, iclass 3, count 0 2006.182.08:09:18.66#ibcon#about to read 6, iclass 3, count 0 2006.182.08:09:18.66#ibcon#read 6, iclass 3, count 0 2006.182.08:09:18.66#ibcon#end of sib2, iclass 3, count 0 2006.182.08:09:18.66#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:09:18.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:09:18.66#ibcon#[25=USB\r\n] 2006.182.08:09:18.66#ibcon#*before write, iclass 3, count 0 2006.182.08:09:18.66#ibcon#enter sib2, iclass 3, count 0 2006.182.08:09:18.66#ibcon#flushed, iclass 3, count 0 2006.182.08:09:18.66#ibcon#about to write, iclass 3, count 0 2006.182.08:09:18.66#ibcon#wrote, iclass 3, count 0 2006.182.08:09:18.66#ibcon#about to read 3, iclass 3, count 0 2006.182.08:09:18.69#ibcon#read 3, iclass 3, count 0 2006.182.08:09:18.69#ibcon#about to read 4, iclass 3, count 0 2006.182.08:09:18.69#ibcon#read 4, iclass 3, count 0 2006.182.08:09:18.69#ibcon#about to read 5, iclass 3, count 0 2006.182.08:09:18.69#ibcon#read 5, iclass 3, count 0 2006.182.08:09:18.69#ibcon#about to read 6, iclass 3, count 0 2006.182.08:09:18.69#ibcon#read 6, iclass 3, count 0 2006.182.08:09:18.69#ibcon#end of sib2, iclass 3, count 0 2006.182.08:09:18.69#ibcon#*after write, iclass 3, count 0 2006.182.08:09:18.69#ibcon#*before return 0, iclass 3, count 0 2006.182.08:09:18.69#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:18.69#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:18.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:09:18.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:09:18.69$vc4f8/valo=3,672.99 2006.182.08:09:18.69#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.08:09:18.69#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.08:09:18.69#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:18.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:18.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:18.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:18.69#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:09:18.69#ibcon#first serial, iclass 5, count 0 2006.182.08:09:18.69#ibcon#enter sib2, iclass 5, count 0 2006.182.08:09:18.69#ibcon#flushed, iclass 5, count 0 2006.182.08:09:18.69#ibcon#about to write, iclass 5, count 0 2006.182.08:09:18.69#ibcon#wrote, iclass 5, count 0 2006.182.08:09:18.69#ibcon#about to read 3, iclass 5, count 0 2006.182.08:09:18.71#ibcon#read 3, iclass 5, count 0 2006.182.08:09:18.71#ibcon#about to read 4, iclass 5, count 0 2006.182.08:09:18.71#ibcon#read 4, iclass 5, count 0 2006.182.08:09:18.71#ibcon#about to read 5, iclass 5, count 0 2006.182.08:09:18.71#ibcon#read 5, iclass 5, count 0 2006.182.08:09:18.71#ibcon#about to read 6, iclass 5, count 0 2006.182.08:09:18.71#ibcon#read 6, iclass 5, count 0 2006.182.08:09:18.71#ibcon#end of sib2, iclass 5, count 0 2006.182.08:09:18.71#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:09:18.71#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:09:18.71#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:09:18.71#ibcon#*before write, iclass 5, count 0 2006.182.08:09:18.71#ibcon#enter sib2, iclass 5, count 0 2006.182.08:09:18.71#ibcon#flushed, iclass 5, count 0 2006.182.08:09:18.71#ibcon#about to write, iclass 5, count 0 2006.182.08:09:18.71#ibcon#wrote, iclass 5, count 0 2006.182.08:09:18.71#ibcon#about to read 3, iclass 5, count 0 2006.182.08:09:18.75#ibcon#read 3, iclass 5, count 0 2006.182.08:09:18.75#ibcon#about to read 4, iclass 5, count 0 2006.182.08:09:18.75#ibcon#read 4, iclass 5, count 0 2006.182.08:09:18.75#ibcon#about to read 5, iclass 5, count 0 2006.182.08:09:18.75#ibcon#read 5, iclass 5, count 0 2006.182.08:09:18.75#ibcon#about to read 6, iclass 5, count 0 2006.182.08:09:18.75#ibcon#read 6, iclass 5, count 0 2006.182.08:09:18.75#ibcon#end of sib2, iclass 5, count 0 2006.182.08:09:18.75#ibcon#*after write, iclass 5, count 0 2006.182.08:09:18.75#ibcon#*before return 0, iclass 5, count 0 2006.182.08:09:18.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:18.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:18.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:09:18.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:09:18.75$vc4f8/va=3,6 2006.182.08:09:18.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.08:09:18.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.08:09:18.75#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:18.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:18.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:18.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:18.82#ibcon#enter wrdev, iclass 7, count 2 2006.182.08:09:18.82#ibcon#first serial, iclass 7, count 2 2006.182.08:09:18.82#ibcon#enter sib2, iclass 7, count 2 2006.182.08:09:18.82#ibcon#flushed, iclass 7, count 2 2006.182.08:09:18.82#ibcon#about to write, iclass 7, count 2 2006.182.08:09:18.82#ibcon#wrote, iclass 7, count 2 2006.182.08:09:18.82#ibcon#about to read 3, iclass 7, count 2 2006.182.08:09:18.83#ibcon#read 3, iclass 7, count 2 2006.182.08:09:18.83#ibcon#about to read 4, iclass 7, count 2 2006.182.08:09:18.83#ibcon#read 4, iclass 7, count 2 2006.182.08:09:18.83#ibcon#about to read 5, iclass 7, count 2 2006.182.08:09:18.83#ibcon#read 5, iclass 7, count 2 2006.182.08:09:18.83#ibcon#about to read 6, iclass 7, count 2 2006.182.08:09:18.83#ibcon#read 6, iclass 7, count 2 2006.182.08:09:18.83#ibcon#end of sib2, iclass 7, count 2 2006.182.08:09:18.83#ibcon#*mode == 0, iclass 7, count 2 2006.182.08:09:18.83#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.08:09:18.83#ibcon#[25=AT03-06\r\n] 2006.182.08:09:18.83#ibcon#*before write, iclass 7, count 2 2006.182.08:09:18.83#ibcon#enter sib2, iclass 7, count 2 2006.182.08:09:18.83#ibcon#flushed, iclass 7, count 2 2006.182.08:09:18.83#ibcon#about to write, iclass 7, count 2 2006.182.08:09:18.83#ibcon#wrote, iclass 7, count 2 2006.182.08:09:18.83#ibcon#about to read 3, iclass 7, count 2 2006.182.08:09:18.86#ibcon#read 3, iclass 7, count 2 2006.182.08:09:18.86#ibcon#about to read 4, iclass 7, count 2 2006.182.08:09:18.86#ibcon#read 4, iclass 7, count 2 2006.182.08:09:18.86#ibcon#about to read 5, iclass 7, count 2 2006.182.08:09:18.86#ibcon#read 5, iclass 7, count 2 2006.182.08:09:18.86#ibcon#about to read 6, iclass 7, count 2 2006.182.08:09:18.86#ibcon#read 6, iclass 7, count 2 2006.182.08:09:18.86#ibcon#end of sib2, iclass 7, count 2 2006.182.08:09:18.86#ibcon#*after write, iclass 7, count 2 2006.182.08:09:18.86#ibcon#*before return 0, iclass 7, count 2 2006.182.08:09:18.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:18.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:18.86#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.08:09:18.86#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:18.86#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:18.98#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:18.98#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:18.98#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:09:18.98#ibcon#first serial, iclass 7, count 0 2006.182.08:09:18.98#ibcon#enter sib2, iclass 7, count 0 2006.182.08:09:18.98#ibcon#flushed, iclass 7, count 0 2006.182.08:09:18.98#ibcon#about to write, iclass 7, count 0 2006.182.08:09:18.98#ibcon#wrote, iclass 7, count 0 2006.182.08:09:18.98#ibcon#about to read 3, iclass 7, count 0 2006.182.08:09:19.00#ibcon#read 3, iclass 7, count 0 2006.182.08:09:19.00#ibcon#about to read 4, iclass 7, count 0 2006.182.08:09:19.00#ibcon#read 4, iclass 7, count 0 2006.182.08:09:19.00#ibcon#about to read 5, iclass 7, count 0 2006.182.08:09:19.00#ibcon#read 5, iclass 7, count 0 2006.182.08:09:19.00#ibcon#about to read 6, iclass 7, count 0 2006.182.08:09:19.00#ibcon#read 6, iclass 7, count 0 2006.182.08:09:19.00#ibcon#end of sib2, iclass 7, count 0 2006.182.08:09:19.00#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:09:19.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:09:19.00#ibcon#[25=USB\r\n] 2006.182.08:09:19.00#ibcon#*before write, iclass 7, count 0 2006.182.08:09:19.00#ibcon#enter sib2, iclass 7, count 0 2006.182.08:09:19.00#ibcon#flushed, iclass 7, count 0 2006.182.08:09:19.00#ibcon#about to write, iclass 7, count 0 2006.182.08:09:19.00#ibcon#wrote, iclass 7, count 0 2006.182.08:09:19.00#ibcon#about to read 3, iclass 7, count 0 2006.182.08:09:19.03#ibcon#read 3, iclass 7, count 0 2006.182.08:09:19.03#ibcon#about to read 4, iclass 7, count 0 2006.182.08:09:19.03#ibcon#read 4, iclass 7, count 0 2006.182.08:09:19.03#ibcon#about to read 5, iclass 7, count 0 2006.182.08:09:19.03#ibcon#read 5, iclass 7, count 0 2006.182.08:09:19.03#ibcon#about to read 6, iclass 7, count 0 2006.182.08:09:19.03#ibcon#read 6, iclass 7, count 0 2006.182.08:09:19.03#ibcon#end of sib2, iclass 7, count 0 2006.182.08:09:19.03#ibcon#*after write, iclass 7, count 0 2006.182.08:09:19.03#ibcon#*before return 0, iclass 7, count 0 2006.182.08:09:19.03#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:19.03#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:19.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:09:19.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:09:19.03$vc4f8/valo=4,832.99 2006.182.08:09:19.03#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.08:09:19.03#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.08:09:19.03#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:19.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:19.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:19.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:19.03#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:09:19.03#ibcon#first serial, iclass 11, count 0 2006.182.08:09:19.03#ibcon#enter sib2, iclass 11, count 0 2006.182.08:09:19.03#ibcon#flushed, iclass 11, count 0 2006.182.08:09:19.03#ibcon#about to write, iclass 11, count 0 2006.182.08:09:19.03#ibcon#wrote, iclass 11, count 0 2006.182.08:09:19.03#ibcon#about to read 3, iclass 11, count 0 2006.182.08:09:19.05#ibcon#read 3, iclass 11, count 0 2006.182.08:09:19.05#ibcon#about to read 4, iclass 11, count 0 2006.182.08:09:19.05#ibcon#read 4, iclass 11, count 0 2006.182.08:09:19.05#ibcon#about to read 5, iclass 11, count 0 2006.182.08:09:19.05#ibcon#read 5, iclass 11, count 0 2006.182.08:09:19.05#ibcon#about to read 6, iclass 11, count 0 2006.182.08:09:19.05#ibcon#read 6, iclass 11, count 0 2006.182.08:09:19.05#ibcon#end of sib2, iclass 11, count 0 2006.182.08:09:19.05#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:09:19.05#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:09:19.05#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:09:19.05#ibcon#*before write, iclass 11, count 0 2006.182.08:09:19.05#ibcon#enter sib2, iclass 11, count 0 2006.182.08:09:19.05#ibcon#flushed, iclass 11, count 0 2006.182.08:09:19.05#ibcon#about to write, iclass 11, count 0 2006.182.08:09:19.05#ibcon#wrote, iclass 11, count 0 2006.182.08:09:19.05#ibcon#about to read 3, iclass 11, count 0 2006.182.08:09:19.09#ibcon#read 3, iclass 11, count 0 2006.182.08:09:19.09#ibcon#about to read 4, iclass 11, count 0 2006.182.08:09:19.09#ibcon#read 4, iclass 11, count 0 2006.182.08:09:19.09#ibcon#about to read 5, iclass 11, count 0 2006.182.08:09:19.09#ibcon#read 5, iclass 11, count 0 2006.182.08:09:19.09#ibcon#about to read 6, iclass 11, count 0 2006.182.08:09:19.09#ibcon#read 6, iclass 11, count 0 2006.182.08:09:19.09#ibcon#end of sib2, iclass 11, count 0 2006.182.08:09:19.09#ibcon#*after write, iclass 11, count 0 2006.182.08:09:19.09#ibcon#*before return 0, iclass 11, count 0 2006.182.08:09:19.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:19.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:19.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:09:19.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:09:19.09$vc4f8/va=4,7 2006.182.08:09:19.09#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.08:09:19.09#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.08:09:19.09#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:19.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:19.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:19.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:19.15#ibcon#enter wrdev, iclass 13, count 2 2006.182.08:09:19.15#ibcon#first serial, iclass 13, count 2 2006.182.08:09:19.15#ibcon#enter sib2, iclass 13, count 2 2006.182.08:09:19.15#ibcon#flushed, iclass 13, count 2 2006.182.08:09:19.15#ibcon#about to write, iclass 13, count 2 2006.182.08:09:19.15#ibcon#wrote, iclass 13, count 2 2006.182.08:09:19.15#ibcon#about to read 3, iclass 13, count 2 2006.182.08:09:19.17#ibcon#read 3, iclass 13, count 2 2006.182.08:09:19.17#ibcon#about to read 4, iclass 13, count 2 2006.182.08:09:19.17#ibcon#read 4, iclass 13, count 2 2006.182.08:09:19.17#ibcon#about to read 5, iclass 13, count 2 2006.182.08:09:19.17#ibcon#read 5, iclass 13, count 2 2006.182.08:09:19.17#ibcon#about to read 6, iclass 13, count 2 2006.182.08:09:19.17#ibcon#read 6, iclass 13, count 2 2006.182.08:09:19.17#ibcon#end of sib2, iclass 13, count 2 2006.182.08:09:19.17#ibcon#*mode == 0, iclass 13, count 2 2006.182.08:09:19.17#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.08:09:19.17#ibcon#[25=AT04-07\r\n] 2006.182.08:09:19.17#ibcon#*before write, iclass 13, count 2 2006.182.08:09:19.17#ibcon#enter sib2, iclass 13, count 2 2006.182.08:09:19.17#ibcon#flushed, iclass 13, count 2 2006.182.08:09:19.17#ibcon#about to write, iclass 13, count 2 2006.182.08:09:19.17#ibcon#wrote, iclass 13, count 2 2006.182.08:09:19.17#ibcon#about to read 3, iclass 13, count 2 2006.182.08:09:19.20#ibcon#read 3, iclass 13, count 2 2006.182.08:09:19.20#ibcon#about to read 4, iclass 13, count 2 2006.182.08:09:19.20#ibcon#read 4, iclass 13, count 2 2006.182.08:09:19.20#ibcon#about to read 5, iclass 13, count 2 2006.182.08:09:19.20#ibcon#read 5, iclass 13, count 2 2006.182.08:09:19.20#ibcon#about to read 6, iclass 13, count 2 2006.182.08:09:19.20#ibcon#read 6, iclass 13, count 2 2006.182.08:09:19.20#ibcon#end of sib2, iclass 13, count 2 2006.182.08:09:19.20#ibcon#*after write, iclass 13, count 2 2006.182.08:09:19.20#ibcon#*before return 0, iclass 13, count 2 2006.182.08:09:19.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:19.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:19.20#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.08:09:19.20#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:19.20#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:19.32#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:19.32#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:19.32#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:09:19.32#ibcon#first serial, iclass 13, count 0 2006.182.08:09:19.32#ibcon#enter sib2, iclass 13, count 0 2006.182.08:09:19.32#ibcon#flushed, iclass 13, count 0 2006.182.08:09:19.32#ibcon#about to write, iclass 13, count 0 2006.182.08:09:19.32#ibcon#wrote, iclass 13, count 0 2006.182.08:09:19.32#ibcon#about to read 3, iclass 13, count 0 2006.182.08:09:19.34#ibcon#read 3, iclass 13, count 0 2006.182.08:09:19.34#ibcon#about to read 4, iclass 13, count 0 2006.182.08:09:19.34#ibcon#read 4, iclass 13, count 0 2006.182.08:09:19.34#ibcon#about to read 5, iclass 13, count 0 2006.182.08:09:19.34#ibcon#read 5, iclass 13, count 0 2006.182.08:09:19.34#ibcon#about to read 6, iclass 13, count 0 2006.182.08:09:19.34#ibcon#read 6, iclass 13, count 0 2006.182.08:09:19.34#ibcon#end of sib2, iclass 13, count 0 2006.182.08:09:19.34#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:09:19.34#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:09:19.34#ibcon#[25=USB\r\n] 2006.182.08:09:19.34#ibcon#*before write, iclass 13, count 0 2006.182.08:09:19.34#ibcon#enter sib2, iclass 13, count 0 2006.182.08:09:19.34#ibcon#flushed, iclass 13, count 0 2006.182.08:09:19.34#ibcon#about to write, iclass 13, count 0 2006.182.08:09:19.34#ibcon#wrote, iclass 13, count 0 2006.182.08:09:19.34#ibcon#about to read 3, iclass 13, count 0 2006.182.08:09:19.37#ibcon#read 3, iclass 13, count 0 2006.182.08:09:19.37#ibcon#about to read 4, iclass 13, count 0 2006.182.08:09:19.37#ibcon#read 4, iclass 13, count 0 2006.182.08:09:19.37#ibcon#about to read 5, iclass 13, count 0 2006.182.08:09:19.37#ibcon#read 5, iclass 13, count 0 2006.182.08:09:19.37#ibcon#about to read 6, iclass 13, count 0 2006.182.08:09:19.37#ibcon#read 6, iclass 13, count 0 2006.182.08:09:19.37#ibcon#end of sib2, iclass 13, count 0 2006.182.08:09:19.37#ibcon#*after write, iclass 13, count 0 2006.182.08:09:19.37#ibcon#*before return 0, iclass 13, count 0 2006.182.08:09:19.37#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:19.37#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:19.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:09:19.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:09:19.37$vc4f8/valo=5,652.99 2006.182.08:09:19.37#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.08:09:19.37#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.08:09:19.37#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:19.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:09:19.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:09:19.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:09:19.37#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:09:19.37#ibcon#first serial, iclass 15, count 0 2006.182.08:09:19.37#ibcon#enter sib2, iclass 15, count 0 2006.182.08:09:19.37#ibcon#flushed, iclass 15, count 0 2006.182.08:09:19.37#ibcon#about to write, iclass 15, count 0 2006.182.08:09:19.37#ibcon#wrote, iclass 15, count 0 2006.182.08:09:19.37#ibcon#about to read 3, iclass 15, count 0 2006.182.08:09:19.39#ibcon#read 3, iclass 15, count 0 2006.182.08:09:19.39#ibcon#about to read 4, iclass 15, count 0 2006.182.08:09:19.39#ibcon#read 4, iclass 15, count 0 2006.182.08:09:19.39#ibcon#about to read 5, iclass 15, count 0 2006.182.08:09:19.39#ibcon#read 5, iclass 15, count 0 2006.182.08:09:19.39#ibcon#about to read 6, iclass 15, count 0 2006.182.08:09:19.39#ibcon#read 6, iclass 15, count 0 2006.182.08:09:19.39#ibcon#end of sib2, iclass 15, count 0 2006.182.08:09:19.39#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:09:19.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:09:19.39#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:09:19.39#ibcon#*before write, iclass 15, count 0 2006.182.08:09:19.39#ibcon#enter sib2, iclass 15, count 0 2006.182.08:09:19.39#ibcon#flushed, iclass 15, count 0 2006.182.08:09:19.39#ibcon#about to write, iclass 15, count 0 2006.182.08:09:19.39#ibcon#wrote, iclass 15, count 0 2006.182.08:09:19.39#ibcon#about to read 3, iclass 15, count 0 2006.182.08:09:19.43#ibcon#read 3, iclass 15, count 0 2006.182.08:09:19.43#ibcon#about to read 4, iclass 15, count 0 2006.182.08:09:19.43#ibcon#read 4, iclass 15, count 0 2006.182.08:09:19.43#ibcon#about to read 5, iclass 15, count 0 2006.182.08:09:19.43#ibcon#read 5, iclass 15, count 0 2006.182.08:09:19.43#ibcon#about to read 6, iclass 15, count 0 2006.182.08:09:19.43#ibcon#read 6, iclass 15, count 0 2006.182.08:09:19.43#ibcon#end of sib2, iclass 15, count 0 2006.182.08:09:19.43#ibcon#*after write, iclass 15, count 0 2006.182.08:09:19.43#ibcon#*before return 0, iclass 15, count 0 2006.182.08:09:19.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:09:19.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:09:19.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:09:19.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:09:19.43$vc4f8/va=5,7 2006.182.08:09:19.43#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.08:09:19.43#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.08:09:19.43#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:19.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:09:19.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:09:19.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:09:19.49#ibcon#enter wrdev, iclass 17, count 2 2006.182.08:09:19.49#ibcon#first serial, iclass 17, count 2 2006.182.08:09:19.49#ibcon#enter sib2, iclass 17, count 2 2006.182.08:09:19.49#ibcon#flushed, iclass 17, count 2 2006.182.08:09:19.49#ibcon#about to write, iclass 17, count 2 2006.182.08:09:19.49#ibcon#wrote, iclass 17, count 2 2006.182.08:09:19.49#ibcon#about to read 3, iclass 17, count 2 2006.182.08:09:19.51#ibcon#read 3, iclass 17, count 2 2006.182.08:09:19.51#ibcon#about to read 4, iclass 17, count 2 2006.182.08:09:19.51#ibcon#read 4, iclass 17, count 2 2006.182.08:09:19.51#ibcon#about to read 5, iclass 17, count 2 2006.182.08:09:19.51#ibcon#read 5, iclass 17, count 2 2006.182.08:09:19.51#ibcon#about to read 6, iclass 17, count 2 2006.182.08:09:19.51#ibcon#read 6, iclass 17, count 2 2006.182.08:09:19.51#ibcon#end of sib2, iclass 17, count 2 2006.182.08:09:19.51#ibcon#*mode == 0, iclass 17, count 2 2006.182.08:09:19.51#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.08:09:19.51#ibcon#[25=AT05-07\r\n] 2006.182.08:09:19.51#ibcon#*before write, iclass 17, count 2 2006.182.08:09:19.51#ibcon#enter sib2, iclass 17, count 2 2006.182.08:09:19.51#ibcon#flushed, iclass 17, count 2 2006.182.08:09:19.51#ibcon#about to write, iclass 17, count 2 2006.182.08:09:19.51#ibcon#wrote, iclass 17, count 2 2006.182.08:09:19.51#ibcon#about to read 3, iclass 17, count 2 2006.182.08:09:19.54#ibcon#read 3, iclass 17, count 2 2006.182.08:09:19.54#ibcon#about to read 4, iclass 17, count 2 2006.182.08:09:19.54#ibcon#read 4, iclass 17, count 2 2006.182.08:09:19.54#ibcon#about to read 5, iclass 17, count 2 2006.182.08:09:19.54#ibcon#read 5, iclass 17, count 2 2006.182.08:09:19.54#ibcon#about to read 6, iclass 17, count 2 2006.182.08:09:19.54#ibcon#read 6, iclass 17, count 2 2006.182.08:09:19.54#ibcon#end of sib2, iclass 17, count 2 2006.182.08:09:19.54#ibcon#*after write, iclass 17, count 2 2006.182.08:09:19.54#ibcon#*before return 0, iclass 17, count 2 2006.182.08:09:19.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:09:19.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:09:19.54#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.08:09:19.54#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:19.54#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:09:19.66#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:09:19.66#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:09:19.66#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:09:19.66#ibcon#first serial, iclass 17, count 0 2006.182.08:09:19.66#ibcon#enter sib2, iclass 17, count 0 2006.182.08:09:19.66#ibcon#flushed, iclass 17, count 0 2006.182.08:09:19.66#ibcon#about to write, iclass 17, count 0 2006.182.08:09:19.66#ibcon#wrote, iclass 17, count 0 2006.182.08:09:19.66#ibcon#about to read 3, iclass 17, count 0 2006.182.08:09:19.68#ibcon#read 3, iclass 17, count 0 2006.182.08:09:19.68#ibcon#about to read 4, iclass 17, count 0 2006.182.08:09:19.68#ibcon#read 4, iclass 17, count 0 2006.182.08:09:19.68#ibcon#about to read 5, iclass 17, count 0 2006.182.08:09:19.68#ibcon#read 5, iclass 17, count 0 2006.182.08:09:19.68#ibcon#about to read 6, iclass 17, count 0 2006.182.08:09:19.68#ibcon#read 6, iclass 17, count 0 2006.182.08:09:19.68#ibcon#end of sib2, iclass 17, count 0 2006.182.08:09:19.68#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:09:19.68#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:09:19.68#ibcon#[25=USB\r\n] 2006.182.08:09:19.68#ibcon#*before write, iclass 17, count 0 2006.182.08:09:19.68#ibcon#enter sib2, iclass 17, count 0 2006.182.08:09:19.68#ibcon#flushed, iclass 17, count 0 2006.182.08:09:19.68#ibcon#about to write, iclass 17, count 0 2006.182.08:09:19.68#ibcon#wrote, iclass 17, count 0 2006.182.08:09:19.68#ibcon#about to read 3, iclass 17, count 0 2006.182.08:09:19.71#ibcon#read 3, iclass 17, count 0 2006.182.08:09:19.71#ibcon#about to read 4, iclass 17, count 0 2006.182.08:09:19.71#ibcon#read 4, iclass 17, count 0 2006.182.08:09:19.71#ibcon#about to read 5, iclass 17, count 0 2006.182.08:09:19.71#ibcon#read 5, iclass 17, count 0 2006.182.08:09:19.71#ibcon#about to read 6, iclass 17, count 0 2006.182.08:09:19.71#ibcon#read 6, iclass 17, count 0 2006.182.08:09:19.71#ibcon#end of sib2, iclass 17, count 0 2006.182.08:09:19.71#ibcon#*after write, iclass 17, count 0 2006.182.08:09:19.71#ibcon#*before return 0, iclass 17, count 0 2006.182.08:09:19.71#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:09:19.71#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:09:19.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:09:19.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:09:19.71$vc4f8/valo=6,772.99 2006.182.08:09:19.71#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.08:09:19.71#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.08:09:19.71#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:19.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:19.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:19.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:19.71#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:09:19.71#ibcon#first serial, iclass 19, count 0 2006.182.08:09:19.71#ibcon#enter sib2, iclass 19, count 0 2006.182.08:09:19.71#ibcon#flushed, iclass 19, count 0 2006.182.08:09:19.71#ibcon#about to write, iclass 19, count 0 2006.182.08:09:19.71#ibcon#wrote, iclass 19, count 0 2006.182.08:09:19.71#ibcon#about to read 3, iclass 19, count 0 2006.182.08:09:19.73#ibcon#read 3, iclass 19, count 0 2006.182.08:09:19.73#ibcon#about to read 4, iclass 19, count 0 2006.182.08:09:19.73#ibcon#read 4, iclass 19, count 0 2006.182.08:09:19.73#ibcon#about to read 5, iclass 19, count 0 2006.182.08:09:19.73#ibcon#read 5, iclass 19, count 0 2006.182.08:09:19.73#ibcon#about to read 6, iclass 19, count 0 2006.182.08:09:19.73#ibcon#read 6, iclass 19, count 0 2006.182.08:09:19.73#ibcon#end of sib2, iclass 19, count 0 2006.182.08:09:19.73#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:09:19.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:09:19.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:09:19.73#ibcon#*before write, iclass 19, count 0 2006.182.08:09:19.73#ibcon#enter sib2, iclass 19, count 0 2006.182.08:09:19.73#ibcon#flushed, iclass 19, count 0 2006.182.08:09:19.73#ibcon#about to write, iclass 19, count 0 2006.182.08:09:19.73#ibcon#wrote, iclass 19, count 0 2006.182.08:09:19.73#ibcon#about to read 3, iclass 19, count 0 2006.182.08:09:19.77#ibcon#read 3, iclass 19, count 0 2006.182.08:09:19.77#ibcon#about to read 4, iclass 19, count 0 2006.182.08:09:19.77#ibcon#read 4, iclass 19, count 0 2006.182.08:09:19.77#ibcon#about to read 5, iclass 19, count 0 2006.182.08:09:19.77#ibcon#read 5, iclass 19, count 0 2006.182.08:09:19.77#ibcon#about to read 6, iclass 19, count 0 2006.182.08:09:19.77#ibcon#read 6, iclass 19, count 0 2006.182.08:09:19.77#ibcon#end of sib2, iclass 19, count 0 2006.182.08:09:19.77#ibcon#*after write, iclass 19, count 0 2006.182.08:09:19.77#ibcon#*before return 0, iclass 19, count 0 2006.182.08:09:19.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:19.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:19.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:09:19.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:09:19.77$vc4f8/va=6,6 2006.182.08:09:19.77#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.08:09:19.77#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.08:09:19.77#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:19.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:19.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:19.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:19.83#ibcon#enter wrdev, iclass 21, count 2 2006.182.08:09:19.83#ibcon#first serial, iclass 21, count 2 2006.182.08:09:19.83#ibcon#enter sib2, iclass 21, count 2 2006.182.08:09:19.83#ibcon#flushed, iclass 21, count 2 2006.182.08:09:19.83#ibcon#about to write, iclass 21, count 2 2006.182.08:09:19.83#ibcon#wrote, iclass 21, count 2 2006.182.08:09:19.83#ibcon#about to read 3, iclass 21, count 2 2006.182.08:09:19.85#ibcon#read 3, iclass 21, count 2 2006.182.08:09:19.85#ibcon#about to read 4, iclass 21, count 2 2006.182.08:09:19.85#ibcon#read 4, iclass 21, count 2 2006.182.08:09:19.85#ibcon#about to read 5, iclass 21, count 2 2006.182.08:09:19.85#ibcon#read 5, iclass 21, count 2 2006.182.08:09:19.85#ibcon#about to read 6, iclass 21, count 2 2006.182.08:09:19.85#ibcon#read 6, iclass 21, count 2 2006.182.08:09:19.85#ibcon#end of sib2, iclass 21, count 2 2006.182.08:09:19.85#ibcon#*mode == 0, iclass 21, count 2 2006.182.08:09:19.85#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.08:09:19.85#ibcon#[25=AT06-06\r\n] 2006.182.08:09:19.85#ibcon#*before write, iclass 21, count 2 2006.182.08:09:19.85#ibcon#enter sib2, iclass 21, count 2 2006.182.08:09:19.85#ibcon#flushed, iclass 21, count 2 2006.182.08:09:19.85#ibcon#about to write, iclass 21, count 2 2006.182.08:09:19.85#ibcon#wrote, iclass 21, count 2 2006.182.08:09:19.85#ibcon#about to read 3, iclass 21, count 2 2006.182.08:09:19.88#ibcon#read 3, iclass 21, count 2 2006.182.08:09:19.88#ibcon#about to read 4, iclass 21, count 2 2006.182.08:09:19.88#ibcon#read 4, iclass 21, count 2 2006.182.08:09:19.88#ibcon#about to read 5, iclass 21, count 2 2006.182.08:09:19.88#ibcon#read 5, iclass 21, count 2 2006.182.08:09:19.88#ibcon#about to read 6, iclass 21, count 2 2006.182.08:09:19.88#ibcon#read 6, iclass 21, count 2 2006.182.08:09:19.88#ibcon#end of sib2, iclass 21, count 2 2006.182.08:09:19.88#ibcon#*after write, iclass 21, count 2 2006.182.08:09:19.88#ibcon#*before return 0, iclass 21, count 2 2006.182.08:09:19.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:19.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:19.88#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.08:09:19.88#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:19.88#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:20.00#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:20.00#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:20.00#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:09:20.00#ibcon#first serial, iclass 21, count 0 2006.182.08:09:20.00#ibcon#enter sib2, iclass 21, count 0 2006.182.08:09:20.00#ibcon#flushed, iclass 21, count 0 2006.182.08:09:20.00#ibcon#about to write, iclass 21, count 0 2006.182.08:09:20.00#ibcon#wrote, iclass 21, count 0 2006.182.08:09:20.00#ibcon#about to read 3, iclass 21, count 0 2006.182.08:09:20.02#ibcon#read 3, iclass 21, count 0 2006.182.08:09:20.02#ibcon#about to read 4, iclass 21, count 0 2006.182.08:09:20.02#ibcon#read 4, iclass 21, count 0 2006.182.08:09:20.02#ibcon#about to read 5, iclass 21, count 0 2006.182.08:09:20.02#ibcon#read 5, iclass 21, count 0 2006.182.08:09:20.02#ibcon#about to read 6, iclass 21, count 0 2006.182.08:09:20.02#ibcon#read 6, iclass 21, count 0 2006.182.08:09:20.02#ibcon#end of sib2, iclass 21, count 0 2006.182.08:09:20.02#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:09:20.02#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:09:20.02#ibcon#[25=USB\r\n] 2006.182.08:09:20.02#ibcon#*before write, iclass 21, count 0 2006.182.08:09:20.02#ibcon#enter sib2, iclass 21, count 0 2006.182.08:09:20.02#ibcon#flushed, iclass 21, count 0 2006.182.08:09:20.02#ibcon#about to write, iclass 21, count 0 2006.182.08:09:20.02#ibcon#wrote, iclass 21, count 0 2006.182.08:09:20.02#ibcon#about to read 3, iclass 21, count 0 2006.182.08:09:20.05#ibcon#read 3, iclass 21, count 0 2006.182.08:09:20.05#ibcon#about to read 4, iclass 21, count 0 2006.182.08:09:20.05#ibcon#read 4, iclass 21, count 0 2006.182.08:09:20.05#ibcon#about to read 5, iclass 21, count 0 2006.182.08:09:20.05#ibcon#read 5, iclass 21, count 0 2006.182.08:09:20.05#ibcon#about to read 6, iclass 21, count 0 2006.182.08:09:20.05#ibcon#read 6, iclass 21, count 0 2006.182.08:09:20.05#ibcon#end of sib2, iclass 21, count 0 2006.182.08:09:20.05#ibcon#*after write, iclass 21, count 0 2006.182.08:09:20.05#ibcon#*before return 0, iclass 21, count 0 2006.182.08:09:20.05#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:20.05#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:20.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:09:20.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:09:20.05$vc4f8/valo=7,832.99 2006.182.08:09:20.05#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.08:09:20.05#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.08:09:20.05#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:20.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:20.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:20.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:20.05#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:09:20.05#ibcon#first serial, iclass 23, count 0 2006.182.08:09:20.05#ibcon#enter sib2, iclass 23, count 0 2006.182.08:09:20.05#ibcon#flushed, iclass 23, count 0 2006.182.08:09:20.05#ibcon#about to write, iclass 23, count 0 2006.182.08:09:20.05#ibcon#wrote, iclass 23, count 0 2006.182.08:09:20.05#ibcon#about to read 3, iclass 23, count 0 2006.182.08:09:20.07#ibcon#read 3, iclass 23, count 0 2006.182.08:09:20.07#ibcon#about to read 4, iclass 23, count 0 2006.182.08:09:20.07#ibcon#read 4, iclass 23, count 0 2006.182.08:09:20.07#ibcon#about to read 5, iclass 23, count 0 2006.182.08:09:20.07#ibcon#read 5, iclass 23, count 0 2006.182.08:09:20.07#ibcon#about to read 6, iclass 23, count 0 2006.182.08:09:20.07#ibcon#read 6, iclass 23, count 0 2006.182.08:09:20.07#ibcon#end of sib2, iclass 23, count 0 2006.182.08:09:20.07#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:09:20.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:09:20.07#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:09:20.07#ibcon#*before write, iclass 23, count 0 2006.182.08:09:20.07#ibcon#enter sib2, iclass 23, count 0 2006.182.08:09:20.07#ibcon#flushed, iclass 23, count 0 2006.182.08:09:20.07#ibcon#about to write, iclass 23, count 0 2006.182.08:09:20.07#ibcon#wrote, iclass 23, count 0 2006.182.08:09:20.07#ibcon#about to read 3, iclass 23, count 0 2006.182.08:09:20.11#ibcon#read 3, iclass 23, count 0 2006.182.08:09:20.11#ibcon#about to read 4, iclass 23, count 0 2006.182.08:09:20.11#ibcon#read 4, iclass 23, count 0 2006.182.08:09:20.11#ibcon#about to read 5, iclass 23, count 0 2006.182.08:09:20.11#ibcon#read 5, iclass 23, count 0 2006.182.08:09:20.11#ibcon#about to read 6, iclass 23, count 0 2006.182.08:09:20.11#ibcon#read 6, iclass 23, count 0 2006.182.08:09:20.11#ibcon#end of sib2, iclass 23, count 0 2006.182.08:09:20.11#ibcon#*after write, iclass 23, count 0 2006.182.08:09:20.11#ibcon#*before return 0, iclass 23, count 0 2006.182.08:09:20.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:20.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:20.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:09:20.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:09:20.11$vc4f8/va=7,6 2006.182.08:09:20.11#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.08:09:20.11#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.08:09:20.11#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:20.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:09:20.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:09:20.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:09:20.17#ibcon#enter wrdev, iclass 25, count 2 2006.182.08:09:20.17#ibcon#first serial, iclass 25, count 2 2006.182.08:09:20.17#ibcon#enter sib2, iclass 25, count 2 2006.182.08:09:20.17#ibcon#flushed, iclass 25, count 2 2006.182.08:09:20.17#ibcon#about to write, iclass 25, count 2 2006.182.08:09:20.17#ibcon#wrote, iclass 25, count 2 2006.182.08:09:20.17#ibcon#about to read 3, iclass 25, count 2 2006.182.08:09:20.19#ibcon#read 3, iclass 25, count 2 2006.182.08:09:20.19#ibcon#about to read 4, iclass 25, count 2 2006.182.08:09:20.19#ibcon#read 4, iclass 25, count 2 2006.182.08:09:20.19#ibcon#about to read 5, iclass 25, count 2 2006.182.08:09:20.19#ibcon#read 5, iclass 25, count 2 2006.182.08:09:20.19#ibcon#about to read 6, iclass 25, count 2 2006.182.08:09:20.19#ibcon#read 6, iclass 25, count 2 2006.182.08:09:20.19#ibcon#end of sib2, iclass 25, count 2 2006.182.08:09:20.19#ibcon#*mode == 0, iclass 25, count 2 2006.182.08:09:20.19#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.08:09:20.19#ibcon#[25=AT07-06\r\n] 2006.182.08:09:20.19#ibcon#*before write, iclass 25, count 2 2006.182.08:09:20.19#ibcon#enter sib2, iclass 25, count 2 2006.182.08:09:20.19#ibcon#flushed, iclass 25, count 2 2006.182.08:09:20.19#ibcon#about to write, iclass 25, count 2 2006.182.08:09:20.19#ibcon#wrote, iclass 25, count 2 2006.182.08:09:20.19#ibcon#about to read 3, iclass 25, count 2 2006.182.08:09:20.22#ibcon#read 3, iclass 25, count 2 2006.182.08:09:20.22#ibcon#about to read 4, iclass 25, count 2 2006.182.08:09:20.22#ibcon#read 4, iclass 25, count 2 2006.182.08:09:20.22#ibcon#about to read 5, iclass 25, count 2 2006.182.08:09:20.22#ibcon#read 5, iclass 25, count 2 2006.182.08:09:20.22#ibcon#about to read 6, iclass 25, count 2 2006.182.08:09:20.22#ibcon#read 6, iclass 25, count 2 2006.182.08:09:20.22#ibcon#end of sib2, iclass 25, count 2 2006.182.08:09:20.22#ibcon#*after write, iclass 25, count 2 2006.182.08:09:20.22#ibcon#*before return 0, iclass 25, count 2 2006.182.08:09:20.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:09:20.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:09:20.22#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.08:09:20.22#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:20.22#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:09:20.34#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:09:20.34#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:09:20.34#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:09:20.34#ibcon#first serial, iclass 25, count 0 2006.182.08:09:20.34#ibcon#enter sib2, iclass 25, count 0 2006.182.08:09:20.34#ibcon#flushed, iclass 25, count 0 2006.182.08:09:20.34#ibcon#about to write, iclass 25, count 0 2006.182.08:09:20.34#ibcon#wrote, iclass 25, count 0 2006.182.08:09:20.34#ibcon#about to read 3, iclass 25, count 0 2006.182.08:09:20.36#ibcon#read 3, iclass 25, count 0 2006.182.08:09:20.36#ibcon#about to read 4, iclass 25, count 0 2006.182.08:09:20.36#ibcon#read 4, iclass 25, count 0 2006.182.08:09:20.36#ibcon#about to read 5, iclass 25, count 0 2006.182.08:09:20.36#ibcon#read 5, iclass 25, count 0 2006.182.08:09:20.36#ibcon#about to read 6, iclass 25, count 0 2006.182.08:09:20.36#ibcon#read 6, iclass 25, count 0 2006.182.08:09:20.36#ibcon#end of sib2, iclass 25, count 0 2006.182.08:09:20.36#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:09:20.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:09:20.36#ibcon#[25=USB\r\n] 2006.182.08:09:20.36#ibcon#*before write, iclass 25, count 0 2006.182.08:09:20.36#ibcon#enter sib2, iclass 25, count 0 2006.182.08:09:20.36#ibcon#flushed, iclass 25, count 0 2006.182.08:09:20.36#ibcon#about to write, iclass 25, count 0 2006.182.08:09:20.36#ibcon#wrote, iclass 25, count 0 2006.182.08:09:20.36#ibcon#about to read 3, iclass 25, count 0 2006.182.08:09:20.39#ibcon#read 3, iclass 25, count 0 2006.182.08:09:20.39#ibcon#about to read 4, iclass 25, count 0 2006.182.08:09:20.39#ibcon#read 4, iclass 25, count 0 2006.182.08:09:20.39#ibcon#about to read 5, iclass 25, count 0 2006.182.08:09:20.39#ibcon#read 5, iclass 25, count 0 2006.182.08:09:20.39#ibcon#about to read 6, iclass 25, count 0 2006.182.08:09:20.39#ibcon#read 6, iclass 25, count 0 2006.182.08:09:20.39#ibcon#end of sib2, iclass 25, count 0 2006.182.08:09:20.39#ibcon#*after write, iclass 25, count 0 2006.182.08:09:20.39#ibcon#*before return 0, iclass 25, count 0 2006.182.08:09:20.39#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:09:20.39#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:09:20.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:09:20.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:09:20.39$vc4f8/valo=8,852.99 2006.182.08:09:20.39#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.08:09:20.39#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.08:09:20.39#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:20.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:09:20.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:09:20.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:09:20.39#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:09:20.39#ibcon#first serial, iclass 27, count 0 2006.182.08:09:20.39#ibcon#enter sib2, iclass 27, count 0 2006.182.08:09:20.39#ibcon#flushed, iclass 27, count 0 2006.182.08:09:20.39#ibcon#about to write, iclass 27, count 0 2006.182.08:09:20.39#ibcon#wrote, iclass 27, count 0 2006.182.08:09:20.39#ibcon#about to read 3, iclass 27, count 0 2006.182.08:09:20.41#ibcon#read 3, iclass 27, count 0 2006.182.08:09:20.41#ibcon#about to read 4, iclass 27, count 0 2006.182.08:09:20.41#ibcon#read 4, iclass 27, count 0 2006.182.08:09:20.41#ibcon#about to read 5, iclass 27, count 0 2006.182.08:09:20.41#ibcon#read 5, iclass 27, count 0 2006.182.08:09:20.41#ibcon#about to read 6, iclass 27, count 0 2006.182.08:09:20.41#ibcon#read 6, iclass 27, count 0 2006.182.08:09:20.41#ibcon#end of sib2, iclass 27, count 0 2006.182.08:09:20.41#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:09:20.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:09:20.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:09:20.41#ibcon#*before write, iclass 27, count 0 2006.182.08:09:20.41#ibcon#enter sib2, iclass 27, count 0 2006.182.08:09:20.41#ibcon#flushed, iclass 27, count 0 2006.182.08:09:20.41#ibcon#about to write, iclass 27, count 0 2006.182.08:09:20.41#ibcon#wrote, iclass 27, count 0 2006.182.08:09:20.41#ibcon#about to read 3, iclass 27, count 0 2006.182.08:09:20.45#ibcon#read 3, iclass 27, count 0 2006.182.08:09:20.45#ibcon#about to read 4, iclass 27, count 0 2006.182.08:09:20.45#ibcon#read 4, iclass 27, count 0 2006.182.08:09:20.45#ibcon#about to read 5, iclass 27, count 0 2006.182.08:09:20.45#ibcon#read 5, iclass 27, count 0 2006.182.08:09:20.45#ibcon#about to read 6, iclass 27, count 0 2006.182.08:09:20.45#ibcon#read 6, iclass 27, count 0 2006.182.08:09:20.45#ibcon#end of sib2, iclass 27, count 0 2006.182.08:09:20.45#ibcon#*after write, iclass 27, count 0 2006.182.08:09:20.45#ibcon#*before return 0, iclass 27, count 0 2006.182.08:09:20.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:09:20.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:09:20.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:09:20.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:09:20.45$vc4f8/va=8,7 2006.182.08:09:20.45#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.08:09:20.45#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.08:09:20.45#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:20.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:09:20.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:09:20.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:09:20.51#ibcon#enter wrdev, iclass 29, count 2 2006.182.08:09:20.51#ibcon#first serial, iclass 29, count 2 2006.182.08:09:20.51#ibcon#enter sib2, iclass 29, count 2 2006.182.08:09:20.51#ibcon#flushed, iclass 29, count 2 2006.182.08:09:20.51#ibcon#about to write, iclass 29, count 2 2006.182.08:09:20.51#ibcon#wrote, iclass 29, count 2 2006.182.08:09:20.51#ibcon#about to read 3, iclass 29, count 2 2006.182.08:09:20.53#ibcon#read 3, iclass 29, count 2 2006.182.08:09:20.53#ibcon#about to read 4, iclass 29, count 2 2006.182.08:09:20.53#ibcon#read 4, iclass 29, count 2 2006.182.08:09:20.53#ibcon#about to read 5, iclass 29, count 2 2006.182.08:09:20.53#ibcon#read 5, iclass 29, count 2 2006.182.08:09:20.53#ibcon#about to read 6, iclass 29, count 2 2006.182.08:09:20.53#ibcon#read 6, iclass 29, count 2 2006.182.08:09:20.53#ibcon#end of sib2, iclass 29, count 2 2006.182.08:09:20.53#ibcon#*mode == 0, iclass 29, count 2 2006.182.08:09:20.53#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.08:09:20.53#ibcon#[25=AT08-07\r\n] 2006.182.08:09:20.53#ibcon#*before write, iclass 29, count 2 2006.182.08:09:20.53#ibcon#enter sib2, iclass 29, count 2 2006.182.08:09:20.53#ibcon#flushed, iclass 29, count 2 2006.182.08:09:20.53#ibcon#about to write, iclass 29, count 2 2006.182.08:09:20.53#ibcon#wrote, iclass 29, count 2 2006.182.08:09:20.53#ibcon#about to read 3, iclass 29, count 2 2006.182.08:09:20.56#ibcon#read 3, iclass 29, count 2 2006.182.08:09:20.56#ibcon#about to read 4, iclass 29, count 2 2006.182.08:09:20.56#ibcon#read 4, iclass 29, count 2 2006.182.08:09:20.56#ibcon#about to read 5, iclass 29, count 2 2006.182.08:09:20.56#ibcon#read 5, iclass 29, count 2 2006.182.08:09:20.56#ibcon#about to read 6, iclass 29, count 2 2006.182.08:09:20.56#ibcon#read 6, iclass 29, count 2 2006.182.08:09:20.56#ibcon#end of sib2, iclass 29, count 2 2006.182.08:09:20.56#ibcon#*after write, iclass 29, count 2 2006.182.08:09:20.56#ibcon#*before return 0, iclass 29, count 2 2006.182.08:09:20.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:09:20.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:09:20.56#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.08:09:20.56#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:20.56#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:09:20.68#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:09:20.68#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:09:20.68#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:09:20.68#ibcon#first serial, iclass 29, count 0 2006.182.08:09:20.68#ibcon#enter sib2, iclass 29, count 0 2006.182.08:09:20.68#ibcon#flushed, iclass 29, count 0 2006.182.08:09:20.68#ibcon#about to write, iclass 29, count 0 2006.182.08:09:20.68#ibcon#wrote, iclass 29, count 0 2006.182.08:09:20.68#ibcon#about to read 3, iclass 29, count 0 2006.182.08:09:20.70#ibcon#read 3, iclass 29, count 0 2006.182.08:09:20.70#ibcon#about to read 4, iclass 29, count 0 2006.182.08:09:20.70#ibcon#read 4, iclass 29, count 0 2006.182.08:09:20.70#ibcon#about to read 5, iclass 29, count 0 2006.182.08:09:20.70#ibcon#read 5, iclass 29, count 0 2006.182.08:09:20.70#ibcon#about to read 6, iclass 29, count 0 2006.182.08:09:20.70#ibcon#read 6, iclass 29, count 0 2006.182.08:09:20.70#ibcon#end of sib2, iclass 29, count 0 2006.182.08:09:20.70#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:09:20.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:09:20.70#ibcon#[25=USB\r\n] 2006.182.08:09:20.70#ibcon#*before write, iclass 29, count 0 2006.182.08:09:20.70#ibcon#enter sib2, iclass 29, count 0 2006.182.08:09:20.70#ibcon#flushed, iclass 29, count 0 2006.182.08:09:20.70#ibcon#about to write, iclass 29, count 0 2006.182.08:09:20.70#ibcon#wrote, iclass 29, count 0 2006.182.08:09:20.70#ibcon#about to read 3, iclass 29, count 0 2006.182.08:09:20.73#ibcon#read 3, iclass 29, count 0 2006.182.08:09:20.73#ibcon#about to read 4, iclass 29, count 0 2006.182.08:09:20.73#ibcon#read 4, iclass 29, count 0 2006.182.08:09:20.73#ibcon#about to read 5, iclass 29, count 0 2006.182.08:09:20.73#ibcon#read 5, iclass 29, count 0 2006.182.08:09:20.73#ibcon#about to read 6, iclass 29, count 0 2006.182.08:09:20.73#ibcon#read 6, iclass 29, count 0 2006.182.08:09:20.73#ibcon#end of sib2, iclass 29, count 0 2006.182.08:09:20.73#ibcon#*after write, iclass 29, count 0 2006.182.08:09:20.73#ibcon#*before return 0, iclass 29, count 0 2006.182.08:09:20.73#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:09:20.73#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:09:20.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:09:20.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:09:20.73$vc4f8/vblo=1,632.99 2006.182.08:09:20.73#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.08:09:20.73#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.08:09:20.73#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:20.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:09:20.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:09:20.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:09:20.73#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:09:20.73#ibcon#first serial, iclass 31, count 0 2006.182.08:09:20.73#ibcon#enter sib2, iclass 31, count 0 2006.182.08:09:20.73#ibcon#flushed, iclass 31, count 0 2006.182.08:09:20.73#ibcon#about to write, iclass 31, count 0 2006.182.08:09:20.73#ibcon#wrote, iclass 31, count 0 2006.182.08:09:20.73#ibcon#about to read 3, iclass 31, count 0 2006.182.08:09:20.75#ibcon#read 3, iclass 31, count 0 2006.182.08:09:20.75#ibcon#about to read 4, iclass 31, count 0 2006.182.08:09:20.75#ibcon#read 4, iclass 31, count 0 2006.182.08:09:20.75#ibcon#about to read 5, iclass 31, count 0 2006.182.08:09:20.75#ibcon#read 5, iclass 31, count 0 2006.182.08:09:20.75#ibcon#about to read 6, iclass 31, count 0 2006.182.08:09:20.75#ibcon#read 6, iclass 31, count 0 2006.182.08:09:20.75#ibcon#end of sib2, iclass 31, count 0 2006.182.08:09:20.75#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:09:20.75#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:09:20.75#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:09:20.75#ibcon#*before write, iclass 31, count 0 2006.182.08:09:20.75#ibcon#enter sib2, iclass 31, count 0 2006.182.08:09:20.75#ibcon#flushed, iclass 31, count 0 2006.182.08:09:20.75#ibcon#about to write, iclass 31, count 0 2006.182.08:09:20.75#ibcon#wrote, iclass 31, count 0 2006.182.08:09:20.75#ibcon#about to read 3, iclass 31, count 0 2006.182.08:09:20.79#ibcon#read 3, iclass 31, count 0 2006.182.08:09:20.79#ibcon#about to read 4, iclass 31, count 0 2006.182.08:09:20.79#ibcon#read 4, iclass 31, count 0 2006.182.08:09:20.79#ibcon#about to read 5, iclass 31, count 0 2006.182.08:09:20.79#ibcon#read 5, iclass 31, count 0 2006.182.08:09:20.79#ibcon#about to read 6, iclass 31, count 0 2006.182.08:09:20.79#ibcon#read 6, iclass 31, count 0 2006.182.08:09:20.79#ibcon#end of sib2, iclass 31, count 0 2006.182.08:09:20.79#ibcon#*after write, iclass 31, count 0 2006.182.08:09:20.79#ibcon#*before return 0, iclass 31, count 0 2006.182.08:09:20.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:09:20.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:09:20.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:09:20.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:09:20.79$vc4f8/vb=1,4 2006.182.08:09:20.79#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.08:09:20.79#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.08:09:20.79#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:20.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:09:20.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:09:20.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:09:20.79#ibcon#enter wrdev, iclass 33, count 2 2006.182.08:09:20.79#ibcon#first serial, iclass 33, count 2 2006.182.08:09:20.79#ibcon#enter sib2, iclass 33, count 2 2006.182.08:09:20.79#ibcon#flushed, iclass 33, count 2 2006.182.08:09:20.79#ibcon#about to write, iclass 33, count 2 2006.182.08:09:20.79#ibcon#wrote, iclass 33, count 2 2006.182.08:09:20.79#ibcon#about to read 3, iclass 33, count 2 2006.182.08:09:20.81#ibcon#read 3, iclass 33, count 2 2006.182.08:09:20.81#ibcon#about to read 4, iclass 33, count 2 2006.182.08:09:20.81#ibcon#read 4, iclass 33, count 2 2006.182.08:09:20.81#ibcon#about to read 5, iclass 33, count 2 2006.182.08:09:20.81#ibcon#read 5, iclass 33, count 2 2006.182.08:09:20.81#ibcon#about to read 6, iclass 33, count 2 2006.182.08:09:20.81#ibcon#read 6, iclass 33, count 2 2006.182.08:09:20.81#ibcon#end of sib2, iclass 33, count 2 2006.182.08:09:20.81#ibcon#*mode == 0, iclass 33, count 2 2006.182.08:09:20.81#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.08:09:20.81#ibcon#[27=AT01-04\r\n] 2006.182.08:09:20.81#ibcon#*before write, iclass 33, count 2 2006.182.08:09:20.81#ibcon#enter sib2, iclass 33, count 2 2006.182.08:09:20.81#ibcon#flushed, iclass 33, count 2 2006.182.08:09:20.81#ibcon#about to write, iclass 33, count 2 2006.182.08:09:20.81#ibcon#wrote, iclass 33, count 2 2006.182.08:09:20.81#ibcon#about to read 3, iclass 33, count 2 2006.182.08:09:20.84#ibcon#read 3, iclass 33, count 2 2006.182.08:09:20.84#ibcon#about to read 4, iclass 33, count 2 2006.182.08:09:20.84#ibcon#read 4, iclass 33, count 2 2006.182.08:09:20.84#ibcon#about to read 5, iclass 33, count 2 2006.182.08:09:20.84#ibcon#read 5, iclass 33, count 2 2006.182.08:09:20.84#ibcon#about to read 6, iclass 33, count 2 2006.182.08:09:20.84#ibcon#read 6, iclass 33, count 2 2006.182.08:09:20.84#ibcon#end of sib2, iclass 33, count 2 2006.182.08:09:20.84#ibcon#*after write, iclass 33, count 2 2006.182.08:09:20.84#ibcon#*before return 0, iclass 33, count 2 2006.182.08:09:20.84#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:09:20.84#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:09:20.84#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.08:09:20.84#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:20.84#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:09:20.96#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:09:20.96#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:09:20.96#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:09:20.96#ibcon#first serial, iclass 33, count 0 2006.182.08:09:20.96#ibcon#enter sib2, iclass 33, count 0 2006.182.08:09:20.96#ibcon#flushed, iclass 33, count 0 2006.182.08:09:20.96#ibcon#about to write, iclass 33, count 0 2006.182.08:09:20.96#ibcon#wrote, iclass 33, count 0 2006.182.08:09:20.96#ibcon#about to read 3, iclass 33, count 0 2006.182.08:09:20.98#ibcon#read 3, iclass 33, count 0 2006.182.08:09:20.98#ibcon#about to read 4, iclass 33, count 0 2006.182.08:09:20.98#ibcon#read 4, iclass 33, count 0 2006.182.08:09:20.98#ibcon#about to read 5, iclass 33, count 0 2006.182.08:09:20.98#ibcon#read 5, iclass 33, count 0 2006.182.08:09:20.98#ibcon#about to read 6, iclass 33, count 0 2006.182.08:09:20.98#ibcon#read 6, iclass 33, count 0 2006.182.08:09:20.98#ibcon#end of sib2, iclass 33, count 0 2006.182.08:09:20.98#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:09:20.98#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:09:20.98#ibcon#[27=USB\r\n] 2006.182.08:09:20.98#ibcon#*before write, iclass 33, count 0 2006.182.08:09:20.98#ibcon#enter sib2, iclass 33, count 0 2006.182.08:09:20.98#ibcon#flushed, iclass 33, count 0 2006.182.08:09:20.98#ibcon#about to write, iclass 33, count 0 2006.182.08:09:20.98#ibcon#wrote, iclass 33, count 0 2006.182.08:09:20.98#ibcon#about to read 3, iclass 33, count 0 2006.182.08:09:21.01#ibcon#read 3, iclass 33, count 0 2006.182.08:09:21.01#ibcon#about to read 4, iclass 33, count 0 2006.182.08:09:21.01#ibcon#read 4, iclass 33, count 0 2006.182.08:09:21.01#ibcon#about to read 5, iclass 33, count 0 2006.182.08:09:21.01#ibcon#read 5, iclass 33, count 0 2006.182.08:09:21.01#ibcon#about to read 6, iclass 33, count 0 2006.182.08:09:21.01#ibcon#read 6, iclass 33, count 0 2006.182.08:09:21.01#ibcon#end of sib2, iclass 33, count 0 2006.182.08:09:21.01#ibcon#*after write, iclass 33, count 0 2006.182.08:09:21.01#ibcon#*before return 0, iclass 33, count 0 2006.182.08:09:21.01#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:09:21.01#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:09:21.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:09:21.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:09:21.01$vc4f8/vblo=2,640.99 2006.182.08:09:21.01#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.08:09:21.01#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.08:09:21.01#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:21.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:21.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:21.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:21.01#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:09:21.01#ibcon#first serial, iclass 35, count 0 2006.182.08:09:21.01#ibcon#enter sib2, iclass 35, count 0 2006.182.08:09:21.01#ibcon#flushed, iclass 35, count 0 2006.182.08:09:21.01#ibcon#about to write, iclass 35, count 0 2006.182.08:09:21.01#ibcon#wrote, iclass 35, count 0 2006.182.08:09:21.01#ibcon#about to read 3, iclass 35, count 0 2006.182.08:09:21.03#ibcon#read 3, iclass 35, count 0 2006.182.08:09:21.03#ibcon#about to read 4, iclass 35, count 0 2006.182.08:09:21.03#ibcon#read 4, iclass 35, count 0 2006.182.08:09:21.03#ibcon#about to read 5, iclass 35, count 0 2006.182.08:09:21.03#ibcon#read 5, iclass 35, count 0 2006.182.08:09:21.03#ibcon#about to read 6, iclass 35, count 0 2006.182.08:09:21.03#ibcon#read 6, iclass 35, count 0 2006.182.08:09:21.03#ibcon#end of sib2, iclass 35, count 0 2006.182.08:09:21.03#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:09:21.03#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:09:21.03#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:09:21.03#ibcon#*before write, iclass 35, count 0 2006.182.08:09:21.03#ibcon#enter sib2, iclass 35, count 0 2006.182.08:09:21.03#ibcon#flushed, iclass 35, count 0 2006.182.08:09:21.03#ibcon#about to write, iclass 35, count 0 2006.182.08:09:21.03#ibcon#wrote, iclass 35, count 0 2006.182.08:09:21.03#ibcon#about to read 3, iclass 35, count 0 2006.182.08:09:21.07#ibcon#read 3, iclass 35, count 0 2006.182.08:09:21.07#ibcon#about to read 4, iclass 35, count 0 2006.182.08:09:21.07#ibcon#read 4, iclass 35, count 0 2006.182.08:09:21.07#ibcon#about to read 5, iclass 35, count 0 2006.182.08:09:21.07#ibcon#read 5, iclass 35, count 0 2006.182.08:09:21.07#ibcon#about to read 6, iclass 35, count 0 2006.182.08:09:21.07#ibcon#read 6, iclass 35, count 0 2006.182.08:09:21.07#ibcon#end of sib2, iclass 35, count 0 2006.182.08:09:21.07#ibcon#*after write, iclass 35, count 0 2006.182.08:09:21.07#ibcon#*before return 0, iclass 35, count 0 2006.182.08:09:21.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:21.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:09:21.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:09:21.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:09:21.07$vc4f8/vb=2,4 2006.182.08:09:21.07#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.08:09:21.07#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.08:09:21.07#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:21.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:21.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:21.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:21.13#ibcon#enter wrdev, iclass 37, count 2 2006.182.08:09:21.13#ibcon#first serial, iclass 37, count 2 2006.182.08:09:21.13#ibcon#enter sib2, iclass 37, count 2 2006.182.08:09:21.13#ibcon#flushed, iclass 37, count 2 2006.182.08:09:21.13#ibcon#about to write, iclass 37, count 2 2006.182.08:09:21.13#ibcon#wrote, iclass 37, count 2 2006.182.08:09:21.13#ibcon#about to read 3, iclass 37, count 2 2006.182.08:09:21.15#ibcon#read 3, iclass 37, count 2 2006.182.08:09:21.15#ibcon#about to read 4, iclass 37, count 2 2006.182.08:09:21.15#ibcon#read 4, iclass 37, count 2 2006.182.08:09:21.15#ibcon#about to read 5, iclass 37, count 2 2006.182.08:09:21.15#ibcon#read 5, iclass 37, count 2 2006.182.08:09:21.15#ibcon#about to read 6, iclass 37, count 2 2006.182.08:09:21.15#ibcon#read 6, iclass 37, count 2 2006.182.08:09:21.15#ibcon#end of sib2, iclass 37, count 2 2006.182.08:09:21.15#ibcon#*mode == 0, iclass 37, count 2 2006.182.08:09:21.15#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.08:09:21.15#ibcon#[27=AT02-04\r\n] 2006.182.08:09:21.15#ibcon#*before write, iclass 37, count 2 2006.182.08:09:21.15#ibcon#enter sib2, iclass 37, count 2 2006.182.08:09:21.15#ibcon#flushed, iclass 37, count 2 2006.182.08:09:21.15#ibcon#about to write, iclass 37, count 2 2006.182.08:09:21.15#ibcon#wrote, iclass 37, count 2 2006.182.08:09:21.15#ibcon#about to read 3, iclass 37, count 2 2006.182.08:09:21.18#ibcon#read 3, iclass 37, count 2 2006.182.08:09:21.18#ibcon#about to read 4, iclass 37, count 2 2006.182.08:09:21.18#ibcon#read 4, iclass 37, count 2 2006.182.08:09:21.18#ibcon#about to read 5, iclass 37, count 2 2006.182.08:09:21.18#ibcon#read 5, iclass 37, count 2 2006.182.08:09:21.18#ibcon#about to read 6, iclass 37, count 2 2006.182.08:09:21.18#ibcon#read 6, iclass 37, count 2 2006.182.08:09:21.18#ibcon#end of sib2, iclass 37, count 2 2006.182.08:09:21.18#ibcon#*after write, iclass 37, count 2 2006.182.08:09:21.18#ibcon#*before return 0, iclass 37, count 2 2006.182.08:09:21.18#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:21.18#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:09:21.18#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.08:09:21.18#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:21.18#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:21.30#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:21.30#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:21.30#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:09:21.30#ibcon#first serial, iclass 37, count 0 2006.182.08:09:21.30#ibcon#enter sib2, iclass 37, count 0 2006.182.08:09:21.30#ibcon#flushed, iclass 37, count 0 2006.182.08:09:21.30#ibcon#about to write, iclass 37, count 0 2006.182.08:09:21.30#ibcon#wrote, iclass 37, count 0 2006.182.08:09:21.30#ibcon#about to read 3, iclass 37, count 0 2006.182.08:09:21.32#ibcon#read 3, iclass 37, count 0 2006.182.08:09:21.32#ibcon#about to read 4, iclass 37, count 0 2006.182.08:09:21.32#ibcon#read 4, iclass 37, count 0 2006.182.08:09:21.32#ibcon#about to read 5, iclass 37, count 0 2006.182.08:09:21.32#ibcon#read 5, iclass 37, count 0 2006.182.08:09:21.32#ibcon#about to read 6, iclass 37, count 0 2006.182.08:09:21.32#ibcon#read 6, iclass 37, count 0 2006.182.08:09:21.32#ibcon#end of sib2, iclass 37, count 0 2006.182.08:09:21.32#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:09:21.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:09:21.32#ibcon#[27=USB\r\n] 2006.182.08:09:21.32#ibcon#*before write, iclass 37, count 0 2006.182.08:09:21.32#ibcon#enter sib2, iclass 37, count 0 2006.182.08:09:21.32#ibcon#flushed, iclass 37, count 0 2006.182.08:09:21.32#ibcon#about to write, iclass 37, count 0 2006.182.08:09:21.32#ibcon#wrote, iclass 37, count 0 2006.182.08:09:21.32#ibcon#about to read 3, iclass 37, count 0 2006.182.08:09:21.35#ibcon#read 3, iclass 37, count 0 2006.182.08:09:21.35#ibcon#about to read 4, iclass 37, count 0 2006.182.08:09:21.35#ibcon#read 4, iclass 37, count 0 2006.182.08:09:21.35#ibcon#about to read 5, iclass 37, count 0 2006.182.08:09:21.35#ibcon#read 5, iclass 37, count 0 2006.182.08:09:21.35#ibcon#about to read 6, iclass 37, count 0 2006.182.08:09:21.35#ibcon#read 6, iclass 37, count 0 2006.182.08:09:21.35#ibcon#end of sib2, iclass 37, count 0 2006.182.08:09:21.35#ibcon#*after write, iclass 37, count 0 2006.182.08:09:21.35#ibcon#*before return 0, iclass 37, count 0 2006.182.08:09:21.35#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:21.35#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:09:21.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:09:21.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:09:21.35$vc4f8/vblo=3,656.99 2006.182.08:09:21.35#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.08:09:21.35#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.08:09:21.35#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:21.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:21.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:21.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:21.35#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:09:21.35#ibcon#first serial, iclass 39, count 0 2006.182.08:09:21.35#ibcon#enter sib2, iclass 39, count 0 2006.182.08:09:21.35#ibcon#flushed, iclass 39, count 0 2006.182.08:09:21.35#ibcon#about to write, iclass 39, count 0 2006.182.08:09:21.35#ibcon#wrote, iclass 39, count 0 2006.182.08:09:21.35#ibcon#about to read 3, iclass 39, count 0 2006.182.08:09:21.37#ibcon#read 3, iclass 39, count 0 2006.182.08:09:21.37#ibcon#about to read 4, iclass 39, count 0 2006.182.08:09:21.37#ibcon#read 4, iclass 39, count 0 2006.182.08:09:21.37#ibcon#about to read 5, iclass 39, count 0 2006.182.08:09:21.37#ibcon#read 5, iclass 39, count 0 2006.182.08:09:21.37#ibcon#about to read 6, iclass 39, count 0 2006.182.08:09:21.37#ibcon#read 6, iclass 39, count 0 2006.182.08:09:21.37#ibcon#end of sib2, iclass 39, count 0 2006.182.08:09:21.37#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:09:21.37#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:09:21.37#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:09:21.37#ibcon#*before write, iclass 39, count 0 2006.182.08:09:21.37#ibcon#enter sib2, iclass 39, count 0 2006.182.08:09:21.37#ibcon#flushed, iclass 39, count 0 2006.182.08:09:21.37#ibcon#about to write, iclass 39, count 0 2006.182.08:09:21.37#ibcon#wrote, iclass 39, count 0 2006.182.08:09:21.37#ibcon#about to read 3, iclass 39, count 0 2006.182.08:09:21.41#ibcon#read 3, iclass 39, count 0 2006.182.08:09:21.41#ibcon#about to read 4, iclass 39, count 0 2006.182.08:09:21.41#ibcon#read 4, iclass 39, count 0 2006.182.08:09:21.41#ibcon#about to read 5, iclass 39, count 0 2006.182.08:09:21.41#ibcon#read 5, iclass 39, count 0 2006.182.08:09:21.41#ibcon#about to read 6, iclass 39, count 0 2006.182.08:09:21.41#ibcon#read 6, iclass 39, count 0 2006.182.08:09:21.41#ibcon#end of sib2, iclass 39, count 0 2006.182.08:09:21.41#ibcon#*after write, iclass 39, count 0 2006.182.08:09:21.41#ibcon#*before return 0, iclass 39, count 0 2006.182.08:09:21.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:21.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:09:21.41#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:09:21.41#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:09:21.41$vc4f8/vb=3,4 2006.182.08:09:21.41#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.08:09:21.41#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.08:09:21.41#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:21.41#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:21.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:21.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:21.47#ibcon#enter wrdev, iclass 3, count 2 2006.182.08:09:21.47#ibcon#first serial, iclass 3, count 2 2006.182.08:09:21.47#ibcon#enter sib2, iclass 3, count 2 2006.182.08:09:21.47#ibcon#flushed, iclass 3, count 2 2006.182.08:09:21.47#ibcon#about to write, iclass 3, count 2 2006.182.08:09:21.47#ibcon#wrote, iclass 3, count 2 2006.182.08:09:21.47#ibcon#about to read 3, iclass 3, count 2 2006.182.08:09:21.49#ibcon#read 3, iclass 3, count 2 2006.182.08:09:21.49#ibcon#about to read 4, iclass 3, count 2 2006.182.08:09:21.49#ibcon#read 4, iclass 3, count 2 2006.182.08:09:21.49#ibcon#about to read 5, iclass 3, count 2 2006.182.08:09:21.49#ibcon#read 5, iclass 3, count 2 2006.182.08:09:21.49#ibcon#about to read 6, iclass 3, count 2 2006.182.08:09:21.49#ibcon#read 6, iclass 3, count 2 2006.182.08:09:21.49#ibcon#end of sib2, iclass 3, count 2 2006.182.08:09:21.49#ibcon#*mode == 0, iclass 3, count 2 2006.182.08:09:21.49#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.08:09:21.49#ibcon#[27=AT03-04\r\n] 2006.182.08:09:21.49#ibcon#*before write, iclass 3, count 2 2006.182.08:09:21.49#ibcon#enter sib2, iclass 3, count 2 2006.182.08:09:21.49#ibcon#flushed, iclass 3, count 2 2006.182.08:09:21.49#ibcon#about to write, iclass 3, count 2 2006.182.08:09:21.49#ibcon#wrote, iclass 3, count 2 2006.182.08:09:21.49#ibcon#about to read 3, iclass 3, count 2 2006.182.08:09:21.52#ibcon#read 3, iclass 3, count 2 2006.182.08:09:21.52#ibcon#about to read 4, iclass 3, count 2 2006.182.08:09:21.52#ibcon#read 4, iclass 3, count 2 2006.182.08:09:21.52#ibcon#about to read 5, iclass 3, count 2 2006.182.08:09:21.52#ibcon#read 5, iclass 3, count 2 2006.182.08:09:21.52#ibcon#about to read 6, iclass 3, count 2 2006.182.08:09:21.52#ibcon#read 6, iclass 3, count 2 2006.182.08:09:21.52#ibcon#end of sib2, iclass 3, count 2 2006.182.08:09:21.52#ibcon#*after write, iclass 3, count 2 2006.182.08:09:21.52#ibcon#*before return 0, iclass 3, count 2 2006.182.08:09:21.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:21.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:09:21.52#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.08:09:21.52#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:21.52#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:21.64#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:21.64#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:21.64#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:09:21.64#ibcon#first serial, iclass 3, count 0 2006.182.08:09:21.64#ibcon#enter sib2, iclass 3, count 0 2006.182.08:09:21.64#ibcon#flushed, iclass 3, count 0 2006.182.08:09:21.64#ibcon#about to write, iclass 3, count 0 2006.182.08:09:21.64#ibcon#wrote, iclass 3, count 0 2006.182.08:09:21.64#ibcon#about to read 3, iclass 3, count 0 2006.182.08:09:21.66#ibcon#read 3, iclass 3, count 0 2006.182.08:09:21.66#ibcon#about to read 4, iclass 3, count 0 2006.182.08:09:21.66#ibcon#read 4, iclass 3, count 0 2006.182.08:09:21.66#ibcon#about to read 5, iclass 3, count 0 2006.182.08:09:21.66#ibcon#read 5, iclass 3, count 0 2006.182.08:09:21.66#ibcon#about to read 6, iclass 3, count 0 2006.182.08:09:21.66#ibcon#read 6, iclass 3, count 0 2006.182.08:09:21.66#ibcon#end of sib2, iclass 3, count 0 2006.182.08:09:21.66#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:09:21.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:09:21.66#ibcon#[27=USB\r\n] 2006.182.08:09:21.66#ibcon#*before write, iclass 3, count 0 2006.182.08:09:21.66#ibcon#enter sib2, iclass 3, count 0 2006.182.08:09:21.66#ibcon#flushed, iclass 3, count 0 2006.182.08:09:21.66#ibcon#about to write, iclass 3, count 0 2006.182.08:09:21.66#ibcon#wrote, iclass 3, count 0 2006.182.08:09:21.66#ibcon#about to read 3, iclass 3, count 0 2006.182.08:09:21.69#ibcon#read 3, iclass 3, count 0 2006.182.08:09:21.69#ibcon#about to read 4, iclass 3, count 0 2006.182.08:09:21.69#ibcon#read 4, iclass 3, count 0 2006.182.08:09:21.69#ibcon#about to read 5, iclass 3, count 0 2006.182.08:09:21.69#ibcon#read 5, iclass 3, count 0 2006.182.08:09:21.69#ibcon#about to read 6, iclass 3, count 0 2006.182.08:09:21.69#ibcon#read 6, iclass 3, count 0 2006.182.08:09:21.69#ibcon#end of sib2, iclass 3, count 0 2006.182.08:09:21.69#ibcon#*after write, iclass 3, count 0 2006.182.08:09:21.69#ibcon#*before return 0, iclass 3, count 0 2006.182.08:09:21.69#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:21.69#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:09:21.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:09:21.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:09:21.69$vc4f8/vblo=4,712.99 2006.182.08:09:21.69#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.08:09:21.69#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.08:09:21.69#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:21.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:21.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:21.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:21.69#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:09:21.69#ibcon#first serial, iclass 5, count 0 2006.182.08:09:21.69#ibcon#enter sib2, iclass 5, count 0 2006.182.08:09:21.69#ibcon#flushed, iclass 5, count 0 2006.182.08:09:21.69#ibcon#about to write, iclass 5, count 0 2006.182.08:09:21.69#ibcon#wrote, iclass 5, count 0 2006.182.08:09:21.69#ibcon#about to read 3, iclass 5, count 0 2006.182.08:09:21.71#ibcon#read 3, iclass 5, count 0 2006.182.08:09:21.71#ibcon#about to read 4, iclass 5, count 0 2006.182.08:09:21.71#ibcon#read 4, iclass 5, count 0 2006.182.08:09:21.71#ibcon#about to read 5, iclass 5, count 0 2006.182.08:09:21.71#ibcon#read 5, iclass 5, count 0 2006.182.08:09:21.71#ibcon#about to read 6, iclass 5, count 0 2006.182.08:09:21.71#ibcon#read 6, iclass 5, count 0 2006.182.08:09:21.71#ibcon#end of sib2, iclass 5, count 0 2006.182.08:09:21.71#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:09:21.71#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:09:21.71#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:09:21.71#ibcon#*before write, iclass 5, count 0 2006.182.08:09:21.71#ibcon#enter sib2, iclass 5, count 0 2006.182.08:09:21.71#ibcon#flushed, iclass 5, count 0 2006.182.08:09:21.71#ibcon#about to write, iclass 5, count 0 2006.182.08:09:21.71#ibcon#wrote, iclass 5, count 0 2006.182.08:09:21.71#ibcon#about to read 3, iclass 5, count 0 2006.182.08:09:21.75#ibcon#read 3, iclass 5, count 0 2006.182.08:09:21.75#ibcon#about to read 4, iclass 5, count 0 2006.182.08:09:21.75#ibcon#read 4, iclass 5, count 0 2006.182.08:09:21.75#ibcon#about to read 5, iclass 5, count 0 2006.182.08:09:21.75#ibcon#read 5, iclass 5, count 0 2006.182.08:09:21.75#ibcon#about to read 6, iclass 5, count 0 2006.182.08:09:21.75#ibcon#read 6, iclass 5, count 0 2006.182.08:09:21.75#ibcon#end of sib2, iclass 5, count 0 2006.182.08:09:21.75#ibcon#*after write, iclass 5, count 0 2006.182.08:09:21.75#ibcon#*before return 0, iclass 5, count 0 2006.182.08:09:21.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:21.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:09:21.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:09:21.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:09:21.75$vc4f8/vb=4,4 2006.182.08:09:21.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.08:09:21.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.08:09:21.75#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:21.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:21.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:21.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:21.82#ibcon#enter wrdev, iclass 7, count 2 2006.182.08:09:21.82#ibcon#first serial, iclass 7, count 2 2006.182.08:09:21.82#ibcon#enter sib2, iclass 7, count 2 2006.182.08:09:21.82#ibcon#flushed, iclass 7, count 2 2006.182.08:09:21.82#ibcon#about to write, iclass 7, count 2 2006.182.08:09:21.82#ibcon#wrote, iclass 7, count 2 2006.182.08:09:21.82#ibcon#about to read 3, iclass 7, count 2 2006.182.08:09:21.83#ibcon#read 3, iclass 7, count 2 2006.182.08:09:21.83#ibcon#about to read 4, iclass 7, count 2 2006.182.08:09:21.83#ibcon#read 4, iclass 7, count 2 2006.182.08:09:21.83#ibcon#about to read 5, iclass 7, count 2 2006.182.08:09:21.83#ibcon#read 5, iclass 7, count 2 2006.182.08:09:21.83#ibcon#about to read 6, iclass 7, count 2 2006.182.08:09:21.83#ibcon#read 6, iclass 7, count 2 2006.182.08:09:21.83#ibcon#end of sib2, iclass 7, count 2 2006.182.08:09:21.83#ibcon#*mode == 0, iclass 7, count 2 2006.182.08:09:21.83#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.08:09:21.83#ibcon#[27=AT04-04\r\n] 2006.182.08:09:21.83#ibcon#*before write, iclass 7, count 2 2006.182.08:09:21.83#ibcon#enter sib2, iclass 7, count 2 2006.182.08:09:21.83#ibcon#flushed, iclass 7, count 2 2006.182.08:09:21.83#ibcon#about to write, iclass 7, count 2 2006.182.08:09:21.83#ibcon#wrote, iclass 7, count 2 2006.182.08:09:21.83#ibcon#about to read 3, iclass 7, count 2 2006.182.08:09:21.86#ibcon#read 3, iclass 7, count 2 2006.182.08:09:21.86#ibcon#about to read 4, iclass 7, count 2 2006.182.08:09:21.86#ibcon#read 4, iclass 7, count 2 2006.182.08:09:21.86#ibcon#about to read 5, iclass 7, count 2 2006.182.08:09:21.86#ibcon#read 5, iclass 7, count 2 2006.182.08:09:21.86#ibcon#about to read 6, iclass 7, count 2 2006.182.08:09:21.86#ibcon#read 6, iclass 7, count 2 2006.182.08:09:21.86#ibcon#end of sib2, iclass 7, count 2 2006.182.08:09:21.86#ibcon#*after write, iclass 7, count 2 2006.182.08:09:21.86#ibcon#*before return 0, iclass 7, count 2 2006.182.08:09:21.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:21.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:09:21.86#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.08:09:21.86#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:21.86#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:21.98#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:21.98#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:21.98#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:09:21.98#ibcon#first serial, iclass 7, count 0 2006.182.08:09:21.98#ibcon#enter sib2, iclass 7, count 0 2006.182.08:09:21.98#ibcon#flushed, iclass 7, count 0 2006.182.08:09:21.98#ibcon#about to write, iclass 7, count 0 2006.182.08:09:21.98#ibcon#wrote, iclass 7, count 0 2006.182.08:09:21.98#ibcon#about to read 3, iclass 7, count 0 2006.182.08:09:22.00#ibcon#read 3, iclass 7, count 0 2006.182.08:09:22.00#ibcon#about to read 4, iclass 7, count 0 2006.182.08:09:22.00#ibcon#read 4, iclass 7, count 0 2006.182.08:09:22.00#ibcon#about to read 5, iclass 7, count 0 2006.182.08:09:22.00#ibcon#read 5, iclass 7, count 0 2006.182.08:09:22.00#ibcon#about to read 6, iclass 7, count 0 2006.182.08:09:22.00#ibcon#read 6, iclass 7, count 0 2006.182.08:09:22.00#ibcon#end of sib2, iclass 7, count 0 2006.182.08:09:22.00#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:09:22.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:09:22.00#ibcon#[27=USB\r\n] 2006.182.08:09:22.00#ibcon#*before write, iclass 7, count 0 2006.182.08:09:22.00#ibcon#enter sib2, iclass 7, count 0 2006.182.08:09:22.00#ibcon#flushed, iclass 7, count 0 2006.182.08:09:22.00#ibcon#about to write, iclass 7, count 0 2006.182.08:09:22.00#ibcon#wrote, iclass 7, count 0 2006.182.08:09:22.00#ibcon#about to read 3, iclass 7, count 0 2006.182.08:09:22.03#ibcon#read 3, iclass 7, count 0 2006.182.08:09:22.03#ibcon#about to read 4, iclass 7, count 0 2006.182.08:09:22.03#ibcon#read 4, iclass 7, count 0 2006.182.08:09:22.03#ibcon#about to read 5, iclass 7, count 0 2006.182.08:09:22.03#ibcon#read 5, iclass 7, count 0 2006.182.08:09:22.03#ibcon#about to read 6, iclass 7, count 0 2006.182.08:09:22.03#ibcon#read 6, iclass 7, count 0 2006.182.08:09:22.03#ibcon#end of sib2, iclass 7, count 0 2006.182.08:09:22.03#ibcon#*after write, iclass 7, count 0 2006.182.08:09:22.03#ibcon#*before return 0, iclass 7, count 0 2006.182.08:09:22.03#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:22.03#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:09:22.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:09:22.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:09:22.03$vc4f8/vblo=5,744.99 2006.182.08:09:22.03#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.08:09:22.03#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.08:09:22.03#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:22.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:22.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:22.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:22.03#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:09:22.03#ibcon#first serial, iclass 11, count 0 2006.182.08:09:22.03#ibcon#enter sib2, iclass 11, count 0 2006.182.08:09:22.03#ibcon#flushed, iclass 11, count 0 2006.182.08:09:22.03#ibcon#about to write, iclass 11, count 0 2006.182.08:09:22.03#ibcon#wrote, iclass 11, count 0 2006.182.08:09:22.03#ibcon#about to read 3, iclass 11, count 0 2006.182.08:09:22.05#ibcon#read 3, iclass 11, count 0 2006.182.08:09:22.05#ibcon#about to read 4, iclass 11, count 0 2006.182.08:09:22.05#ibcon#read 4, iclass 11, count 0 2006.182.08:09:22.05#ibcon#about to read 5, iclass 11, count 0 2006.182.08:09:22.05#ibcon#read 5, iclass 11, count 0 2006.182.08:09:22.05#ibcon#about to read 6, iclass 11, count 0 2006.182.08:09:22.05#ibcon#read 6, iclass 11, count 0 2006.182.08:09:22.05#ibcon#end of sib2, iclass 11, count 0 2006.182.08:09:22.05#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:09:22.05#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:09:22.05#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:09:22.05#ibcon#*before write, iclass 11, count 0 2006.182.08:09:22.05#ibcon#enter sib2, iclass 11, count 0 2006.182.08:09:22.05#ibcon#flushed, iclass 11, count 0 2006.182.08:09:22.05#ibcon#about to write, iclass 11, count 0 2006.182.08:09:22.05#ibcon#wrote, iclass 11, count 0 2006.182.08:09:22.05#ibcon#about to read 3, iclass 11, count 0 2006.182.08:09:22.09#ibcon#read 3, iclass 11, count 0 2006.182.08:09:22.09#ibcon#about to read 4, iclass 11, count 0 2006.182.08:09:22.09#ibcon#read 4, iclass 11, count 0 2006.182.08:09:22.09#ibcon#about to read 5, iclass 11, count 0 2006.182.08:09:22.09#ibcon#read 5, iclass 11, count 0 2006.182.08:09:22.09#ibcon#about to read 6, iclass 11, count 0 2006.182.08:09:22.09#ibcon#read 6, iclass 11, count 0 2006.182.08:09:22.09#ibcon#end of sib2, iclass 11, count 0 2006.182.08:09:22.09#ibcon#*after write, iclass 11, count 0 2006.182.08:09:22.09#ibcon#*before return 0, iclass 11, count 0 2006.182.08:09:22.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:22.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:09:22.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:09:22.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:09:22.09$vc4f8/vb=5,4 2006.182.08:09:22.09#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.08:09:22.09#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.08:09:22.09#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:22.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:22.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:22.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:22.15#ibcon#enter wrdev, iclass 13, count 2 2006.182.08:09:22.15#ibcon#first serial, iclass 13, count 2 2006.182.08:09:22.15#ibcon#enter sib2, iclass 13, count 2 2006.182.08:09:22.15#ibcon#flushed, iclass 13, count 2 2006.182.08:09:22.15#ibcon#about to write, iclass 13, count 2 2006.182.08:09:22.15#ibcon#wrote, iclass 13, count 2 2006.182.08:09:22.15#ibcon#about to read 3, iclass 13, count 2 2006.182.08:09:22.17#ibcon#read 3, iclass 13, count 2 2006.182.08:09:22.17#ibcon#about to read 4, iclass 13, count 2 2006.182.08:09:22.17#ibcon#read 4, iclass 13, count 2 2006.182.08:09:22.17#ibcon#about to read 5, iclass 13, count 2 2006.182.08:09:22.17#ibcon#read 5, iclass 13, count 2 2006.182.08:09:22.17#ibcon#about to read 6, iclass 13, count 2 2006.182.08:09:22.17#ibcon#read 6, iclass 13, count 2 2006.182.08:09:22.17#ibcon#end of sib2, iclass 13, count 2 2006.182.08:09:22.17#ibcon#*mode == 0, iclass 13, count 2 2006.182.08:09:22.17#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.08:09:22.17#ibcon#[27=AT05-04\r\n] 2006.182.08:09:22.17#ibcon#*before write, iclass 13, count 2 2006.182.08:09:22.17#ibcon#enter sib2, iclass 13, count 2 2006.182.08:09:22.17#ibcon#flushed, iclass 13, count 2 2006.182.08:09:22.17#ibcon#about to write, iclass 13, count 2 2006.182.08:09:22.17#ibcon#wrote, iclass 13, count 2 2006.182.08:09:22.17#ibcon#about to read 3, iclass 13, count 2 2006.182.08:09:22.20#ibcon#read 3, iclass 13, count 2 2006.182.08:09:22.20#ibcon#about to read 4, iclass 13, count 2 2006.182.08:09:22.20#ibcon#read 4, iclass 13, count 2 2006.182.08:09:22.20#ibcon#about to read 5, iclass 13, count 2 2006.182.08:09:22.20#ibcon#read 5, iclass 13, count 2 2006.182.08:09:22.20#ibcon#about to read 6, iclass 13, count 2 2006.182.08:09:22.20#ibcon#read 6, iclass 13, count 2 2006.182.08:09:22.20#ibcon#end of sib2, iclass 13, count 2 2006.182.08:09:22.20#ibcon#*after write, iclass 13, count 2 2006.182.08:09:22.20#ibcon#*before return 0, iclass 13, count 2 2006.182.08:09:22.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:22.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:09:22.20#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.08:09:22.20#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:22.20#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:22.23#abcon#<5=/06 1.0 2.6 27.90 831002.8\r\n> 2006.182.08:09:22.25#abcon#{5=INTERFACE CLEAR} 2006.182.08:09:22.31#abcon#[5=S1D000X0/0*\r\n] 2006.182.08:09:22.32#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:22.32#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:22.32#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:09:22.32#ibcon#first serial, iclass 13, count 0 2006.182.08:09:22.32#ibcon#enter sib2, iclass 13, count 0 2006.182.08:09:22.32#ibcon#flushed, iclass 13, count 0 2006.182.08:09:22.32#ibcon#about to write, iclass 13, count 0 2006.182.08:09:22.32#ibcon#wrote, iclass 13, count 0 2006.182.08:09:22.32#ibcon#about to read 3, iclass 13, count 0 2006.182.08:09:22.34#ibcon#read 3, iclass 13, count 0 2006.182.08:09:22.34#ibcon#about to read 4, iclass 13, count 0 2006.182.08:09:22.34#ibcon#read 4, iclass 13, count 0 2006.182.08:09:22.34#ibcon#about to read 5, iclass 13, count 0 2006.182.08:09:22.34#ibcon#read 5, iclass 13, count 0 2006.182.08:09:22.34#ibcon#about to read 6, iclass 13, count 0 2006.182.08:09:22.34#ibcon#read 6, iclass 13, count 0 2006.182.08:09:22.34#ibcon#end of sib2, iclass 13, count 0 2006.182.08:09:22.34#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:09:22.34#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:09:22.34#ibcon#[27=USB\r\n] 2006.182.08:09:22.34#ibcon#*before write, iclass 13, count 0 2006.182.08:09:22.34#ibcon#enter sib2, iclass 13, count 0 2006.182.08:09:22.34#ibcon#flushed, iclass 13, count 0 2006.182.08:09:22.34#ibcon#about to write, iclass 13, count 0 2006.182.08:09:22.34#ibcon#wrote, iclass 13, count 0 2006.182.08:09:22.34#ibcon#about to read 3, iclass 13, count 0 2006.182.08:09:22.37#ibcon#read 3, iclass 13, count 0 2006.182.08:09:22.37#ibcon#about to read 4, iclass 13, count 0 2006.182.08:09:22.37#ibcon#read 4, iclass 13, count 0 2006.182.08:09:22.37#ibcon#about to read 5, iclass 13, count 0 2006.182.08:09:22.37#ibcon#read 5, iclass 13, count 0 2006.182.08:09:22.37#ibcon#about to read 6, iclass 13, count 0 2006.182.08:09:22.37#ibcon#read 6, iclass 13, count 0 2006.182.08:09:22.37#ibcon#end of sib2, iclass 13, count 0 2006.182.08:09:22.37#ibcon#*after write, iclass 13, count 0 2006.182.08:09:22.37#ibcon#*before return 0, iclass 13, count 0 2006.182.08:09:22.37#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:22.37#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:09:22.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:09:22.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:09:22.37$vc4f8/vblo=6,752.99 2006.182.08:09:22.37#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.08:09:22.37#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.08:09:22.37#ibcon#ireg 17 cls_cnt 0 2006.182.08:09:22.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:22.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:22.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:22.37#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:09:22.37#ibcon#first serial, iclass 19, count 0 2006.182.08:09:22.37#ibcon#enter sib2, iclass 19, count 0 2006.182.08:09:22.37#ibcon#flushed, iclass 19, count 0 2006.182.08:09:22.37#ibcon#about to write, iclass 19, count 0 2006.182.08:09:22.37#ibcon#wrote, iclass 19, count 0 2006.182.08:09:22.37#ibcon#about to read 3, iclass 19, count 0 2006.182.08:09:22.39#ibcon#read 3, iclass 19, count 0 2006.182.08:09:22.39#ibcon#about to read 4, iclass 19, count 0 2006.182.08:09:22.39#ibcon#read 4, iclass 19, count 0 2006.182.08:09:22.39#ibcon#about to read 5, iclass 19, count 0 2006.182.08:09:22.39#ibcon#read 5, iclass 19, count 0 2006.182.08:09:22.39#ibcon#about to read 6, iclass 19, count 0 2006.182.08:09:22.39#ibcon#read 6, iclass 19, count 0 2006.182.08:09:22.39#ibcon#end of sib2, iclass 19, count 0 2006.182.08:09:22.39#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:09:22.39#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:09:22.39#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:09:22.39#ibcon#*before write, iclass 19, count 0 2006.182.08:09:22.39#ibcon#enter sib2, iclass 19, count 0 2006.182.08:09:22.39#ibcon#flushed, iclass 19, count 0 2006.182.08:09:22.39#ibcon#about to write, iclass 19, count 0 2006.182.08:09:22.39#ibcon#wrote, iclass 19, count 0 2006.182.08:09:22.39#ibcon#about to read 3, iclass 19, count 0 2006.182.08:09:22.43#ibcon#read 3, iclass 19, count 0 2006.182.08:09:22.43#ibcon#about to read 4, iclass 19, count 0 2006.182.08:09:22.43#ibcon#read 4, iclass 19, count 0 2006.182.08:09:22.43#ibcon#about to read 5, iclass 19, count 0 2006.182.08:09:22.43#ibcon#read 5, iclass 19, count 0 2006.182.08:09:22.43#ibcon#about to read 6, iclass 19, count 0 2006.182.08:09:22.43#ibcon#read 6, iclass 19, count 0 2006.182.08:09:22.43#ibcon#end of sib2, iclass 19, count 0 2006.182.08:09:22.43#ibcon#*after write, iclass 19, count 0 2006.182.08:09:22.43#ibcon#*before return 0, iclass 19, count 0 2006.182.08:09:22.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:22.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:09:22.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:09:22.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:09:22.43$vc4f8/vb=6,4 2006.182.08:09:22.43#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.08:09:22.43#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.08:09:22.43#ibcon#ireg 11 cls_cnt 2 2006.182.08:09:22.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:22.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:22.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:22.49#ibcon#enter wrdev, iclass 21, count 2 2006.182.08:09:22.49#ibcon#first serial, iclass 21, count 2 2006.182.08:09:22.49#ibcon#enter sib2, iclass 21, count 2 2006.182.08:09:22.49#ibcon#flushed, iclass 21, count 2 2006.182.08:09:22.49#ibcon#about to write, iclass 21, count 2 2006.182.08:09:22.49#ibcon#wrote, iclass 21, count 2 2006.182.08:09:22.49#ibcon#about to read 3, iclass 21, count 2 2006.182.08:09:22.51#ibcon#read 3, iclass 21, count 2 2006.182.08:09:22.51#ibcon#about to read 4, iclass 21, count 2 2006.182.08:09:22.51#ibcon#read 4, iclass 21, count 2 2006.182.08:09:22.51#ibcon#about to read 5, iclass 21, count 2 2006.182.08:09:22.51#ibcon#read 5, iclass 21, count 2 2006.182.08:09:22.51#ibcon#about to read 6, iclass 21, count 2 2006.182.08:09:22.51#ibcon#read 6, iclass 21, count 2 2006.182.08:09:22.51#ibcon#end of sib2, iclass 21, count 2 2006.182.08:09:22.51#ibcon#*mode == 0, iclass 21, count 2 2006.182.08:09:22.51#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.08:09:22.51#ibcon#[27=AT06-04\r\n] 2006.182.08:09:22.51#ibcon#*before write, iclass 21, count 2 2006.182.08:09:22.51#ibcon#enter sib2, iclass 21, count 2 2006.182.08:09:22.51#ibcon#flushed, iclass 21, count 2 2006.182.08:09:22.51#ibcon#about to write, iclass 21, count 2 2006.182.08:09:22.51#ibcon#wrote, iclass 21, count 2 2006.182.08:09:22.51#ibcon#about to read 3, iclass 21, count 2 2006.182.08:09:22.54#ibcon#read 3, iclass 21, count 2 2006.182.08:09:22.54#ibcon#about to read 4, iclass 21, count 2 2006.182.08:09:22.54#ibcon#read 4, iclass 21, count 2 2006.182.08:09:22.54#ibcon#about to read 5, iclass 21, count 2 2006.182.08:09:22.54#ibcon#read 5, iclass 21, count 2 2006.182.08:09:22.54#ibcon#about to read 6, iclass 21, count 2 2006.182.08:09:22.54#ibcon#read 6, iclass 21, count 2 2006.182.08:09:22.54#ibcon#end of sib2, iclass 21, count 2 2006.182.08:09:22.54#ibcon#*after write, iclass 21, count 2 2006.182.08:09:22.54#ibcon#*before return 0, iclass 21, count 2 2006.182.08:09:22.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:22.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:09:22.54#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.08:09:22.54#ibcon#ireg 7 cls_cnt 0 2006.182.08:09:22.54#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:22.66#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:22.66#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:22.66#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:09:22.66#ibcon#first serial, iclass 21, count 0 2006.182.08:09:22.66#ibcon#enter sib2, iclass 21, count 0 2006.182.08:09:22.66#ibcon#flushed, iclass 21, count 0 2006.182.08:09:22.66#ibcon#about to write, iclass 21, count 0 2006.182.08:09:22.66#ibcon#wrote, iclass 21, count 0 2006.182.08:09:22.66#ibcon#about to read 3, iclass 21, count 0 2006.182.08:09:22.68#ibcon#read 3, iclass 21, count 0 2006.182.08:09:22.68#ibcon#about to read 4, iclass 21, count 0 2006.182.08:09:22.68#ibcon#read 4, iclass 21, count 0 2006.182.08:09:22.68#ibcon#about to read 5, iclass 21, count 0 2006.182.08:09:22.68#ibcon#read 5, iclass 21, count 0 2006.182.08:09:22.68#ibcon#about to read 6, iclass 21, count 0 2006.182.08:09:22.68#ibcon#read 6, iclass 21, count 0 2006.182.08:09:22.68#ibcon#end of sib2, iclass 21, count 0 2006.182.08:09:22.68#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:09:22.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:09:22.68#ibcon#[27=USB\r\n] 2006.182.08:09:22.68#ibcon#*before write, iclass 21, count 0 2006.182.08:09:22.68#ibcon#enter sib2, iclass 21, count 0 2006.182.08:09:22.68#ibcon#flushed, iclass 21, count 0 2006.182.08:09:22.68#ibcon#about to write, iclass 21, count 0 2006.182.08:09:22.68#ibcon#wrote, iclass 21, count 0 2006.182.08:09:22.68#ibcon#about to read 3, iclass 21, count 0 2006.182.08:09:22.71#ibcon#read 3, iclass 21, count 0 2006.182.08:09:22.71#ibcon#about to read 4, iclass 21, count 0 2006.182.08:09:22.71#ibcon#read 4, iclass 21, count 0 2006.182.08:09:22.71#ibcon#about to read 5, iclass 21, count 0 2006.182.08:09:22.71#ibcon#read 5, iclass 21, count 0 2006.182.08:09:22.71#ibcon#about to read 6, iclass 21, count 0 2006.182.08:09:22.71#ibcon#read 6, iclass 21, count 0 2006.182.08:09:22.71#ibcon#end of sib2, iclass 21, count 0 2006.182.08:09:22.71#ibcon#*after write, iclass 21, count 0 2006.182.08:09:22.71#ibcon#*before return 0, iclass 21, count 0 2006.182.08:09:22.71#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:22.71#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:09:22.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:09:22.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:09:22.71$vc4f8/vabw=wide 2006.182.08:09:22.71#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.08:09:22.71#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.08:09:22.71#ibcon#ireg 8 cls_cnt 0 2006.182.08:09:22.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:22.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:22.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:22.71#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:09:22.71#ibcon#first serial, iclass 23, count 0 2006.182.08:09:22.71#ibcon#enter sib2, iclass 23, count 0 2006.182.08:09:22.71#ibcon#flushed, iclass 23, count 0 2006.182.08:09:22.71#ibcon#about to write, iclass 23, count 0 2006.182.08:09:22.71#ibcon#wrote, iclass 23, count 0 2006.182.08:09:22.71#ibcon#about to read 3, iclass 23, count 0 2006.182.08:09:22.73#ibcon#read 3, iclass 23, count 0 2006.182.08:09:22.73#ibcon#about to read 4, iclass 23, count 0 2006.182.08:09:22.73#ibcon#read 4, iclass 23, count 0 2006.182.08:09:22.73#ibcon#about to read 5, iclass 23, count 0 2006.182.08:09:22.73#ibcon#read 5, iclass 23, count 0 2006.182.08:09:22.73#ibcon#about to read 6, iclass 23, count 0 2006.182.08:09:22.73#ibcon#read 6, iclass 23, count 0 2006.182.08:09:22.73#ibcon#end of sib2, iclass 23, count 0 2006.182.08:09:22.73#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:09:22.73#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:09:22.73#ibcon#[25=BW32\r\n] 2006.182.08:09:22.73#ibcon#*before write, iclass 23, count 0 2006.182.08:09:22.73#ibcon#enter sib2, iclass 23, count 0 2006.182.08:09:22.73#ibcon#flushed, iclass 23, count 0 2006.182.08:09:22.73#ibcon#about to write, iclass 23, count 0 2006.182.08:09:22.73#ibcon#wrote, iclass 23, count 0 2006.182.08:09:22.73#ibcon#about to read 3, iclass 23, count 0 2006.182.08:09:22.76#ibcon#read 3, iclass 23, count 0 2006.182.08:09:22.76#ibcon#about to read 4, iclass 23, count 0 2006.182.08:09:22.76#ibcon#read 4, iclass 23, count 0 2006.182.08:09:22.76#ibcon#about to read 5, iclass 23, count 0 2006.182.08:09:22.76#ibcon#read 5, iclass 23, count 0 2006.182.08:09:22.76#ibcon#about to read 6, iclass 23, count 0 2006.182.08:09:22.76#ibcon#read 6, iclass 23, count 0 2006.182.08:09:22.76#ibcon#end of sib2, iclass 23, count 0 2006.182.08:09:22.76#ibcon#*after write, iclass 23, count 0 2006.182.08:09:22.76#ibcon#*before return 0, iclass 23, count 0 2006.182.08:09:22.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:22.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:09:22.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:09:22.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:09:22.76$vc4f8/vbbw=wide 2006.182.08:09:22.76#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.08:09:22.76#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.08:09:22.76#ibcon#ireg 8 cls_cnt 0 2006.182.08:09:22.76#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:09:22.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:09:22.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:09:22.84#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:09:22.84#ibcon#first serial, iclass 25, count 0 2006.182.08:09:22.84#ibcon#enter sib2, iclass 25, count 0 2006.182.08:09:22.84#ibcon#flushed, iclass 25, count 0 2006.182.08:09:22.84#ibcon#about to write, iclass 25, count 0 2006.182.08:09:22.84#ibcon#wrote, iclass 25, count 0 2006.182.08:09:22.84#ibcon#about to read 3, iclass 25, count 0 2006.182.08:09:22.85#ibcon#read 3, iclass 25, count 0 2006.182.08:09:22.85#ibcon#about to read 4, iclass 25, count 0 2006.182.08:09:22.85#ibcon#read 4, iclass 25, count 0 2006.182.08:09:22.85#ibcon#about to read 5, iclass 25, count 0 2006.182.08:09:22.85#ibcon#read 5, iclass 25, count 0 2006.182.08:09:22.85#ibcon#about to read 6, iclass 25, count 0 2006.182.08:09:22.85#ibcon#read 6, iclass 25, count 0 2006.182.08:09:22.85#ibcon#end of sib2, iclass 25, count 0 2006.182.08:09:22.85#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:09:22.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:09:22.85#ibcon#[27=BW32\r\n] 2006.182.08:09:22.85#ibcon#*before write, iclass 25, count 0 2006.182.08:09:22.85#ibcon#enter sib2, iclass 25, count 0 2006.182.08:09:22.85#ibcon#flushed, iclass 25, count 0 2006.182.08:09:22.85#ibcon#about to write, iclass 25, count 0 2006.182.08:09:22.85#ibcon#wrote, iclass 25, count 0 2006.182.08:09:22.85#ibcon#about to read 3, iclass 25, count 0 2006.182.08:09:22.88#ibcon#read 3, iclass 25, count 0 2006.182.08:09:22.88#ibcon#about to read 4, iclass 25, count 0 2006.182.08:09:22.88#ibcon#read 4, iclass 25, count 0 2006.182.08:09:22.88#ibcon#about to read 5, iclass 25, count 0 2006.182.08:09:22.88#ibcon#read 5, iclass 25, count 0 2006.182.08:09:22.88#ibcon#about to read 6, iclass 25, count 0 2006.182.08:09:22.88#ibcon#read 6, iclass 25, count 0 2006.182.08:09:22.88#ibcon#end of sib2, iclass 25, count 0 2006.182.08:09:22.88#ibcon#*after write, iclass 25, count 0 2006.182.08:09:22.88#ibcon#*before return 0, iclass 25, count 0 2006.182.08:09:22.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:09:22.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:09:22.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:09:22.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:09:22.88$4f8m12a/ifd4f 2006.182.08:09:22.88$ifd4f/lo= 2006.182.08:09:22.88$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:09:22.88$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:09:22.88$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:09:22.88$ifd4f/patch= 2006.182.08:09:22.88$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:09:22.88$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:09:22.88$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:09:22.88$4f8m12a/"form=m,16.000,1:2 2006.182.08:09:22.88$4f8m12a/"tpicd 2006.182.08:09:22.88$4f8m12a/echo=off 2006.182.08:09:22.88$4f8m12a/xlog=off 2006.182.08:09:22.88:!2006.182.08:09:50 2006.182.08:09:28.14#trakl#Source acquired 2006.182.08:09:29.14#flagr#flagr/antenna,acquired 2006.182.08:09:50.00:preob 2006.182.08:09:51.14/onsource/TRACKING 2006.182.08:09:51.14:!2006.182.08:10:00 2006.182.08:10:00.00:data_valid=on 2006.182.08:10:00.00:midob 2006.182.08:10:00.14/onsource/TRACKING 2006.182.08:10:00.14/wx/27.90,1002.8,82 2006.182.08:10:00.20/cable/+6.4633E-03 2006.182.08:10:01.29/va/01,08,usb,yes,29,31 2006.182.08:10:01.29/va/02,07,usb,yes,29,31 2006.182.08:10:01.29/va/03,06,usb,yes,31,31 2006.182.08:10:01.29/va/04,07,usb,yes,30,32 2006.182.08:10:01.29/va/05,07,usb,yes,31,33 2006.182.08:10:01.29/va/06,06,usb,yes,30,30 2006.182.08:10:01.29/va/07,06,usb,yes,31,30 2006.182.08:10:01.29/va/08,07,usb,yes,29,29 2006.182.08:10:01.52/valo/01,532.99,yes,locked 2006.182.08:10:01.52/valo/02,572.99,yes,locked 2006.182.08:10:01.52/valo/03,672.99,yes,locked 2006.182.08:10:01.52/valo/04,832.99,yes,locked 2006.182.08:10:01.52/valo/05,652.99,yes,locked 2006.182.08:10:01.52/valo/06,772.99,yes,locked 2006.182.08:10:01.52/valo/07,832.99,yes,locked 2006.182.08:10:01.52/valo/08,852.99,yes,locked 2006.182.08:10:02.61/vb/01,04,usb,yes,29,28 2006.182.08:10:02.61/vb/02,04,usb,yes,31,33 2006.182.08:10:02.61/vb/03,04,usb,yes,28,31 2006.182.08:10:02.61/vb/04,04,usb,yes,28,29 2006.182.08:10:02.61/vb/05,04,usb,yes,27,31 2006.182.08:10:02.61/vb/06,04,usb,yes,28,31 2006.182.08:10:02.61/vb/07,04,usb,yes,30,30 2006.182.08:10:02.61/vb/08,04,usb,yes,28,31 2006.182.08:10:02.84/vblo/01,632.99,yes,locked 2006.182.08:10:02.84/vblo/02,640.99,yes,locked 2006.182.08:10:02.84/vblo/03,656.99,yes,locked 2006.182.08:10:02.84/vblo/04,712.99,yes,locked 2006.182.08:10:02.84/vblo/05,744.99,yes,locked 2006.182.08:10:02.84/vblo/06,752.99,yes,locked 2006.182.08:10:02.84/vblo/07,734.99,yes,locked 2006.182.08:10:02.84/vblo/08,744.99,yes,locked 2006.182.08:10:02.99/vabw/8 2006.182.08:10:03.14/vbbw/8 2006.182.08:10:03.23/xfe/off,on,14.5 2006.182.08:10:03.62/ifatt/23,28,28,28 2006.182.08:10:04.07/fmout-gps/S +3.45E-07 2006.182.08:10:04.15:!2006.182.08:11:00 2006.182.08:11:00.00:data_valid=off 2006.182.08:11:00.00:postob 2006.182.08:11:00.24/cable/+6.4639E-03 2006.182.08:11:00.24/wx/27.89,1002.8,81 2006.182.08:11:01.07/fmout-gps/S +3.45E-07 2006.182.08:11:01.07:scan_name=182-0811,k06182,60 2006.182.08:11:01.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.182.08:11:01.13#flagr#flagr/antenna,new-source 2006.182.08:11:02.13:checkk5 2006.182.08:11:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:11:02.87/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:11:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:11:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:11:03.99/chk_obsdata//k5ts1/T1820810??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:11:04.37/chk_obsdata//k5ts2/T1820810??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:11:04.74/chk_obsdata//k5ts3/T1820810??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:11:05.11/chk_obsdata//k5ts4/T1820810??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:11:05.80/k5log//k5ts1_log_newline 2006.182.08:11:06.49/k5log//k5ts2_log_newline 2006.182.08:11:07.19/k5log//k5ts3_log_newline 2006.182.08:11:07.88/k5log//k5ts4_log_newline 2006.182.08:11:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:11:07.90:4f8m12a=2 2006.182.08:11:07.90$4f8m12a/echo=on 2006.182.08:11:07.90$4f8m12a/pcalon 2006.182.08:11:07.90$pcalon/"no phase cal control is implemented here 2006.182.08:11:07.90$4f8m12a/"tpicd=stop 2006.182.08:11:07.90$4f8m12a/vc4f8 2006.182.08:11:07.90$vc4f8/valo=1,532.99 2006.182.08:11:07.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.08:11:07.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.08:11:07.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:07.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:07.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:07.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:07.90#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:11:07.90#ibcon#first serial, iclass 32, count 0 2006.182.08:11:07.90#ibcon#enter sib2, iclass 32, count 0 2006.182.08:11:07.91#ibcon#flushed, iclass 32, count 0 2006.182.08:11:07.91#ibcon#about to write, iclass 32, count 0 2006.182.08:11:07.91#ibcon#wrote, iclass 32, count 0 2006.182.08:11:07.91#ibcon#about to read 3, iclass 32, count 0 2006.182.08:11:07.95#ibcon#read 3, iclass 32, count 0 2006.182.08:11:07.95#ibcon#about to read 4, iclass 32, count 0 2006.182.08:11:07.95#ibcon#read 4, iclass 32, count 0 2006.182.08:11:07.95#ibcon#about to read 5, iclass 32, count 0 2006.182.08:11:07.95#ibcon#read 5, iclass 32, count 0 2006.182.08:11:07.95#ibcon#about to read 6, iclass 32, count 0 2006.182.08:11:07.95#ibcon#read 6, iclass 32, count 0 2006.182.08:11:07.95#ibcon#end of sib2, iclass 32, count 0 2006.182.08:11:07.95#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:11:07.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:11:07.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:11:07.95#ibcon#*before write, iclass 32, count 0 2006.182.08:11:07.95#ibcon#enter sib2, iclass 32, count 0 2006.182.08:11:07.95#ibcon#flushed, iclass 32, count 0 2006.182.08:11:07.95#ibcon#about to write, iclass 32, count 0 2006.182.08:11:07.95#ibcon#wrote, iclass 32, count 0 2006.182.08:11:07.95#ibcon#about to read 3, iclass 32, count 0 2006.182.08:11:07.99#ibcon#read 3, iclass 32, count 0 2006.182.08:11:07.99#ibcon#about to read 4, iclass 32, count 0 2006.182.08:11:07.99#ibcon#read 4, iclass 32, count 0 2006.182.08:11:07.99#ibcon#about to read 5, iclass 32, count 0 2006.182.08:11:07.99#ibcon#read 5, iclass 32, count 0 2006.182.08:11:07.99#ibcon#about to read 6, iclass 32, count 0 2006.182.08:11:07.99#ibcon#read 6, iclass 32, count 0 2006.182.08:11:07.99#ibcon#end of sib2, iclass 32, count 0 2006.182.08:11:07.99#ibcon#*after write, iclass 32, count 0 2006.182.08:11:07.99#ibcon#*before return 0, iclass 32, count 0 2006.182.08:11:07.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:07.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:07.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:11:07.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:11:07.99$vc4f8/va=1,8 2006.182.08:11:07.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.08:11:07.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.08:11:07.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:07.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:07.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:07.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:07.99#ibcon#enter wrdev, iclass 34, count 2 2006.182.08:11:07.99#ibcon#first serial, iclass 34, count 2 2006.182.08:11:07.99#ibcon#enter sib2, iclass 34, count 2 2006.182.08:11:07.99#ibcon#flushed, iclass 34, count 2 2006.182.08:11:07.99#ibcon#about to write, iclass 34, count 2 2006.182.08:11:07.99#ibcon#wrote, iclass 34, count 2 2006.182.08:11:07.99#ibcon#about to read 3, iclass 34, count 2 2006.182.08:11:08.01#ibcon#read 3, iclass 34, count 2 2006.182.08:11:08.01#ibcon#about to read 4, iclass 34, count 2 2006.182.08:11:08.01#ibcon#read 4, iclass 34, count 2 2006.182.08:11:08.01#ibcon#about to read 5, iclass 34, count 2 2006.182.08:11:08.01#ibcon#read 5, iclass 34, count 2 2006.182.08:11:08.01#ibcon#about to read 6, iclass 34, count 2 2006.182.08:11:08.01#ibcon#read 6, iclass 34, count 2 2006.182.08:11:08.01#ibcon#end of sib2, iclass 34, count 2 2006.182.08:11:08.01#ibcon#*mode == 0, iclass 34, count 2 2006.182.08:11:08.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.08:11:08.01#ibcon#[25=AT01-08\r\n] 2006.182.08:11:08.01#ibcon#*before write, iclass 34, count 2 2006.182.08:11:08.01#ibcon#enter sib2, iclass 34, count 2 2006.182.08:11:08.01#ibcon#flushed, iclass 34, count 2 2006.182.08:11:08.01#ibcon#about to write, iclass 34, count 2 2006.182.08:11:08.01#ibcon#wrote, iclass 34, count 2 2006.182.08:11:08.01#ibcon#about to read 3, iclass 34, count 2 2006.182.08:11:08.04#ibcon#read 3, iclass 34, count 2 2006.182.08:11:08.04#ibcon#about to read 4, iclass 34, count 2 2006.182.08:11:08.04#ibcon#read 4, iclass 34, count 2 2006.182.08:11:08.04#ibcon#about to read 5, iclass 34, count 2 2006.182.08:11:08.04#ibcon#read 5, iclass 34, count 2 2006.182.08:11:08.04#ibcon#about to read 6, iclass 34, count 2 2006.182.08:11:08.04#ibcon#read 6, iclass 34, count 2 2006.182.08:11:08.04#ibcon#end of sib2, iclass 34, count 2 2006.182.08:11:08.04#ibcon#*after write, iclass 34, count 2 2006.182.08:11:08.04#ibcon#*before return 0, iclass 34, count 2 2006.182.08:11:08.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:08.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:08.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.08:11:08.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:08.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:08.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:08.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:08.16#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:11:08.16#ibcon#first serial, iclass 34, count 0 2006.182.08:11:08.16#ibcon#enter sib2, iclass 34, count 0 2006.182.08:11:08.16#ibcon#flushed, iclass 34, count 0 2006.182.08:11:08.16#ibcon#about to write, iclass 34, count 0 2006.182.08:11:08.16#ibcon#wrote, iclass 34, count 0 2006.182.08:11:08.16#ibcon#about to read 3, iclass 34, count 0 2006.182.08:11:08.18#ibcon#read 3, iclass 34, count 0 2006.182.08:11:08.18#ibcon#about to read 4, iclass 34, count 0 2006.182.08:11:08.18#ibcon#read 4, iclass 34, count 0 2006.182.08:11:08.18#ibcon#about to read 5, iclass 34, count 0 2006.182.08:11:08.18#ibcon#read 5, iclass 34, count 0 2006.182.08:11:08.18#ibcon#about to read 6, iclass 34, count 0 2006.182.08:11:08.18#ibcon#read 6, iclass 34, count 0 2006.182.08:11:08.18#ibcon#end of sib2, iclass 34, count 0 2006.182.08:11:08.18#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:11:08.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:11:08.18#ibcon#[25=USB\r\n] 2006.182.08:11:08.18#ibcon#*before write, iclass 34, count 0 2006.182.08:11:08.18#ibcon#enter sib2, iclass 34, count 0 2006.182.08:11:08.18#ibcon#flushed, iclass 34, count 0 2006.182.08:11:08.18#ibcon#about to write, iclass 34, count 0 2006.182.08:11:08.18#ibcon#wrote, iclass 34, count 0 2006.182.08:11:08.18#ibcon#about to read 3, iclass 34, count 0 2006.182.08:11:08.22#ibcon#read 3, iclass 34, count 0 2006.182.08:11:08.22#ibcon#about to read 4, iclass 34, count 0 2006.182.08:11:08.22#ibcon#read 4, iclass 34, count 0 2006.182.08:11:08.22#ibcon#about to read 5, iclass 34, count 0 2006.182.08:11:08.22#ibcon#read 5, iclass 34, count 0 2006.182.08:11:08.22#ibcon#about to read 6, iclass 34, count 0 2006.182.08:11:08.22#ibcon#read 6, iclass 34, count 0 2006.182.08:11:08.22#ibcon#end of sib2, iclass 34, count 0 2006.182.08:11:08.22#ibcon#*after write, iclass 34, count 0 2006.182.08:11:08.22#ibcon#*before return 0, iclass 34, count 0 2006.182.08:11:08.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:08.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:08.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:11:08.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:11:08.22$vc4f8/valo=2,572.99 2006.182.08:11:08.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.08:11:08.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.08:11:08.22#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:08.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:08.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:08.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:08.22#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:11:08.22#ibcon#first serial, iclass 36, count 0 2006.182.08:11:08.22#ibcon#enter sib2, iclass 36, count 0 2006.182.08:11:08.22#ibcon#flushed, iclass 36, count 0 2006.182.08:11:08.22#ibcon#about to write, iclass 36, count 0 2006.182.08:11:08.22#ibcon#wrote, iclass 36, count 0 2006.182.08:11:08.22#ibcon#about to read 3, iclass 36, count 0 2006.182.08:11:08.23#ibcon#read 3, iclass 36, count 0 2006.182.08:11:08.23#ibcon#about to read 4, iclass 36, count 0 2006.182.08:11:08.23#ibcon#read 4, iclass 36, count 0 2006.182.08:11:08.23#ibcon#about to read 5, iclass 36, count 0 2006.182.08:11:08.23#ibcon#read 5, iclass 36, count 0 2006.182.08:11:08.23#ibcon#about to read 6, iclass 36, count 0 2006.182.08:11:08.23#ibcon#read 6, iclass 36, count 0 2006.182.08:11:08.23#ibcon#end of sib2, iclass 36, count 0 2006.182.08:11:08.23#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:11:08.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:11:08.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:11:08.23#ibcon#*before write, iclass 36, count 0 2006.182.08:11:08.23#ibcon#enter sib2, iclass 36, count 0 2006.182.08:11:08.23#ibcon#flushed, iclass 36, count 0 2006.182.08:11:08.23#ibcon#about to write, iclass 36, count 0 2006.182.08:11:08.23#ibcon#wrote, iclass 36, count 0 2006.182.08:11:08.23#ibcon#about to read 3, iclass 36, count 0 2006.182.08:11:08.27#ibcon#read 3, iclass 36, count 0 2006.182.08:11:08.27#ibcon#about to read 4, iclass 36, count 0 2006.182.08:11:08.27#ibcon#read 4, iclass 36, count 0 2006.182.08:11:08.27#ibcon#about to read 5, iclass 36, count 0 2006.182.08:11:08.27#ibcon#read 5, iclass 36, count 0 2006.182.08:11:08.27#ibcon#about to read 6, iclass 36, count 0 2006.182.08:11:08.27#ibcon#read 6, iclass 36, count 0 2006.182.08:11:08.27#ibcon#end of sib2, iclass 36, count 0 2006.182.08:11:08.27#ibcon#*after write, iclass 36, count 0 2006.182.08:11:08.27#ibcon#*before return 0, iclass 36, count 0 2006.182.08:11:08.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:08.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:08.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:11:08.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:11:08.27$vc4f8/va=2,7 2006.182.08:11:08.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.08:11:08.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.08:11:08.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:08.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:08.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:08.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:08.34#ibcon#enter wrdev, iclass 38, count 2 2006.182.08:11:08.34#ibcon#first serial, iclass 38, count 2 2006.182.08:11:08.34#ibcon#enter sib2, iclass 38, count 2 2006.182.08:11:08.34#ibcon#flushed, iclass 38, count 2 2006.182.08:11:08.34#ibcon#about to write, iclass 38, count 2 2006.182.08:11:08.34#ibcon#wrote, iclass 38, count 2 2006.182.08:11:08.34#ibcon#about to read 3, iclass 38, count 2 2006.182.08:11:08.36#ibcon#read 3, iclass 38, count 2 2006.182.08:11:08.36#ibcon#about to read 4, iclass 38, count 2 2006.182.08:11:08.36#ibcon#read 4, iclass 38, count 2 2006.182.08:11:08.36#ibcon#about to read 5, iclass 38, count 2 2006.182.08:11:08.36#ibcon#read 5, iclass 38, count 2 2006.182.08:11:08.36#ibcon#about to read 6, iclass 38, count 2 2006.182.08:11:08.36#ibcon#read 6, iclass 38, count 2 2006.182.08:11:08.36#ibcon#end of sib2, iclass 38, count 2 2006.182.08:11:08.36#ibcon#*mode == 0, iclass 38, count 2 2006.182.08:11:08.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.08:11:08.36#ibcon#[25=AT02-07\r\n] 2006.182.08:11:08.36#ibcon#*before write, iclass 38, count 2 2006.182.08:11:08.36#ibcon#enter sib2, iclass 38, count 2 2006.182.08:11:08.36#ibcon#flushed, iclass 38, count 2 2006.182.08:11:08.36#ibcon#about to write, iclass 38, count 2 2006.182.08:11:08.36#ibcon#wrote, iclass 38, count 2 2006.182.08:11:08.36#ibcon#about to read 3, iclass 38, count 2 2006.182.08:11:08.39#ibcon#read 3, iclass 38, count 2 2006.182.08:11:08.39#ibcon#about to read 4, iclass 38, count 2 2006.182.08:11:08.39#ibcon#read 4, iclass 38, count 2 2006.182.08:11:08.39#ibcon#about to read 5, iclass 38, count 2 2006.182.08:11:08.39#ibcon#read 5, iclass 38, count 2 2006.182.08:11:08.39#ibcon#about to read 6, iclass 38, count 2 2006.182.08:11:08.39#ibcon#read 6, iclass 38, count 2 2006.182.08:11:08.39#ibcon#end of sib2, iclass 38, count 2 2006.182.08:11:08.39#ibcon#*after write, iclass 38, count 2 2006.182.08:11:08.39#ibcon#*before return 0, iclass 38, count 2 2006.182.08:11:08.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:08.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:08.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.08:11:08.39#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:08.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:08.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:08.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:08.51#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:11:08.51#ibcon#first serial, iclass 38, count 0 2006.182.08:11:08.51#ibcon#enter sib2, iclass 38, count 0 2006.182.08:11:08.51#ibcon#flushed, iclass 38, count 0 2006.182.08:11:08.51#ibcon#about to write, iclass 38, count 0 2006.182.08:11:08.51#ibcon#wrote, iclass 38, count 0 2006.182.08:11:08.51#ibcon#about to read 3, iclass 38, count 0 2006.182.08:11:08.53#ibcon#read 3, iclass 38, count 0 2006.182.08:11:08.53#ibcon#about to read 4, iclass 38, count 0 2006.182.08:11:08.53#ibcon#read 4, iclass 38, count 0 2006.182.08:11:08.53#ibcon#about to read 5, iclass 38, count 0 2006.182.08:11:08.53#ibcon#read 5, iclass 38, count 0 2006.182.08:11:08.53#ibcon#about to read 6, iclass 38, count 0 2006.182.08:11:08.53#ibcon#read 6, iclass 38, count 0 2006.182.08:11:08.53#ibcon#end of sib2, iclass 38, count 0 2006.182.08:11:08.53#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:11:08.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:11:08.53#ibcon#[25=USB\r\n] 2006.182.08:11:08.53#ibcon#*before write, iclass 38, count 0 2006.182.08:11:08.53#ibcon#enter sib2, iclass 38, count 0 2006.182.08:11:08.53#ibcon#flushed, iclass 38, count 0 2006.182.08:11:08.53#ibcon#about to write, iclass 38, count 0 2006.182.08:11:08.53#ibcon#wrote, iclass 38, count 0 2006.182.08:11:08.53#ibcon#about to read 3, iclass 38, count 0 2006.182.08:11:08.56#ibcon#read 3, iclass 38, count 0 2006.182.08:11:08.56#ibcon#about to read 4, iclass 38, count 0 2006.182.08:11:08.56#ibcon#read 4, iclass 38, count 0 2006.182.08:11:08.56#ibcon#about to read 5, iclass 38, count 0 2006.182.08:11:08.56#ibcon#read 5, iclass 38, count 0 2006.182.08:11:08.56#ibcon#about to read 6, iclass 38, count 0 2006.182.08:11:08.56#ibcon#read 6, iclass 38, count 0 2006.182.08:11:08.56#ibcon#end of sib2, iclass 38, count 0 2006.182.08:11:08.56#ibcon#*after write, iclass 38, count 0 2006.182.08:11:08.56#ibcon#*before return 0, iclass 38, count 0 2006.182.08:11:08.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:08.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:08.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:11:08.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:11:08.56$vc4f8/valo=3,672.99 2006.182.08:11:08.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.08:11:08.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.08:11:08.56#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:08.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:08.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:08.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:08.56#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:11:08.56#ibcon#first serial, iclass 40, count 0 2006.182.08:11:08.56#ibcon#enter sib2, iclass 40, count 0 2006.182.08:11:08.56#ibcon#flushed, iclass 40, count 0 2006.182.08:11:08.56#ibcon#about to write, iclass 40, count 0 2006.182.08:11:08.56#ibcon#wrote, iclass 40, count 0 2006.182.08:11:08.56#ibcon#about to read 3, iclass 40, count 0 2006.182.08:11:08.58#ibcon#read 3, iclass 40, count 0 2006.182.08:11:08.58#ibcon#about to read 4, iclass 40, count 0 2006.182.08:11:08.58#ibcon#read 4, iclass 40, count 0 2006.182.08:11:08.58#ibcon#about to read 5, iclass 40, count 0 2006.182.08:11:08.58#ibcon#read 5, iclass 40, count 0 2006.182.08:11:08.58#ibcon#about to read 6, iclass 40, count 0 2006.182.08:11:08.58#ibcon#read 6, iclass 40, count 0 2006.182.08:11:08.58#ibcon#end of sib2, iclass 40, count 0 2006.182.08:11:08.58#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:11:08.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:11:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:11:08.58#ibcon#*before write, iclass 40, count 0 2006.182.08:11:08.58#ibcon#enter sib2, iclass 40, count 0 2006.182.08:11:08.58#ibcon#flushed, iclass 40, count 0 2006.182.08:11:08.58#ibcon#about to write, iclass 40, count 0 2006.182.08:11:08.58#ibcon#wrote, iclass 40, count 0 2006.182.08:11:08.58#ibcon#about to read 3, iclass 40, count 0 2006.182.08:11:08.62#ibcon#read 3, iclass 40, count 0 2006.182.08:11:08.62#ibcon#about to read 4, iclass 40, count 0 2006.182.08:11:08.62#ibcon#read 4, iclass 40, count 0 2006.182.08:11:08.62#ibcon#about to read 5, iclass 40, count 0 2006.182.08:11:08.62#ibcon#read 5, iclass 40, count 0 2006.182.08:11:08.62#ibcon#about to read 6, iclass 40, count 0 2006.182.08:11:08.62#ibcon#read 6, iclass 40, count 0 2006.182.08:11:08.62#ibcon#end of sib2, iclass 40, count 0 2006.182.08:11:08.62#ibcon#*after write, iclass 40, count 0 2006.182.08:11:08.62#ibcon#*before return 0, iclass 40, count 0 2006.182.08:11:08.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:08.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:08.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:11:08.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:11:08.62$vc4f8/va=3,6 2006.182.08:11:08.62#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.08:11:08.62#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.08:11:08.62#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:08.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:08.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:08.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:08.68#ibcon#enter wrdev, iclass 4, count 2 2006.182.08:11:08.68#ibcon#first serial, iclass 4, count 2 2006.182.08:11:08.68#ibcon#enter sib2, iclass 4, count 2 2006.182.08:11:08.68#ibcon#flushed, iclass 4, count 2 2006.182.08:11:08.68#ibcon#about to write, iclass 4, count 2 2006.182.08:11:08.68#ibcon#wrote, iclass 4, count 2 2006.182.08:11:08.68#ibcon#about to read 3, iclass 4, count 2 2006.182.08:11:08.71#ibcon#read 3, iclass 4, count 2 2006.182.08:11:08.71#ibcon#about to read 4, iclass 4, count 2 2006.182.08:11:08.71#ibcon#read 4, iclass 4, count 2 2006.182.08:11:08.71#ibcon#about to read 5, iclass 4, count 2 2006.182.08:11:08.71#ibcon#read 5, iclass 4, count 2 2006.182.08:11:08.71#ibcon#about to read 6, iclass 4, count 2 2006.182.08:11:08.71#ibcon#read 6, iclass 4, count 2 2006.182.08:11:08.71#ibcon#end of sib2, iclass 4, count 2 2006.182.08:11:08.71#ibcon#*mode == 0, iclass 4, count 2 2006.182.08:11:08.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.08:11:08.71#ibcon#[25=AT03-06\r\n] 2006.182.08:11:08.71#ibcon#*before write, iclass 4, count 2 2006.182.08:11:08.71#ibcon#enter sib2, iclass 4, count 2 2006.182.08:11:08.71#ibcon#flushed, iclass 4, count 2 2006.182.08:11:08.71#ibcon#about to write, iclass 4, count 2 2006.182.08:11:08.71#ibcon#wrote, iclass 4, count 2 2006.182.08:11:08.71#ibcon#about to read 3, iclass 4, count 2 2006.182.08:11:08.74#ibcon#read 3, iclass 4, count 2 2006.182.08:11:08.74#ibcon#about to read 4, iclass 4, count 2 2006.182.08:11:08.74#ibcon#read 4, iclass 4, count 2 2006.182.08:11:08.74#ibcon#about to read 5, iclass 4, count 2 2006.182.08:11:08.74#ibcon#read 5, iclass 4, count 2 2006.182.08:11:08.74#ibcon#about to read 6, iclass 4, count 2 2006.182.08:11:08.74#ibcon#read 6, iclass 4, count 2 2006.182.08:11:08.74#ibcon#end of sib2, iclass 4, count 2 2006.182.08:11:08.74#ibcon#*after write, iclass 4, count 2 2006.182.08:11:08.74#ibcon#*before return 0, iclass 4, count 2 2006.182.08:11:08.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:08.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:08.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.08:11:08.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:08.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:08.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:08.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:08.86#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:11:08.86#ibcon#first serial, iclass 4, count 0 2006.182.08:11:08.86#ibcon#enter sib2, iclass 4, count 0 2006.182.08:11:08.86#ibcon#flushed, iclass 4, count 0 2006.182.08:11:08.86#ibcon#about to write, iclass 4, count 0 2006.182.08:11:08.86#ibcon#wrote, iclass 4, count 0 2006.182.08:11:08.86#ibcon#about to read 3, iclass 4, count 0 2006.182.08:11:08.88#ibcon#read 3, iclass 4, count 0 2006.182.08:11:08.88#ibcon#about to read 4, iclass 4, count 0 2006.182.08:11:08.88#ibcon#read 4, iclass 4, count 0 2006.182.08:11:08.88#ibcon#about to read 5, iclass 4, count 0 2006.182.08:11:08.88#ibcon#read 5, iclass 4, count 0 2006.182.08:11:08.88#ibcon#about to read 6, iclass 4, count 0 2006.182.08:11:08.88#ibcon#read 6, iclass 4, count 0 2006.182.08:11:08.88#ibcon#end of sib2, iclass 4, count 0 2006.182.08:11:08.88#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:11:08.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:11:08.88#ibcon#[25=USB\r\n] 2006.182.08:11:08.88#ibcon#*before write, iclass 4, count 0 2006.182.08:11:08.88#ibcon#enter sib2, iclass 4, count 0 2006.182.08:11:08.88#ibcon#flushed, iclass 4, count 0 2006.182.08:11:08.88#ibcon#about to write, iclass 4, count 0 2006.182.08:11:08.88#ibcon#wrote, iclass 4, count 0 2006.182.08:11:08.88#ibcon#about to read 3, iclass 4, count 0 2006.182.08:11:08.91#ibcon#read 3, iclass 4, count 0 2006.182.08:11:08.91#ibcon#about to read 4, iclass 4, count 0 2006.182.08:11:08.91#ibcon#read 4, iclass 4, count 0 2006.182.08:11:08.91#ibcon#about to read 5, iclass 4, count 0 2006.182.08:11:08.91#ibcon#read 5, iclass 4, count 0 2006.182.08:11:08.91#ibcon#about to read 6, iclass 4, count 0 2006.182.08:11:08.91#ibcon#read 6, iclass 4, count 0 2006.182.08:11:08.91#ibcon#end of sib2, iclass 4, count 0 2006.182.08:11:08.91#ibcon#*after write, iclass 4, count 0 2006.182.08:11:08.91#ibcon#*before return 0, iclass 4, count 0 2006.182.08:11:08.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:08.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:08.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:11:08.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:11:08.91$vc4f8/valo=4,832.99 2006.182.08:11:08.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.08:11:08.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.08:11:08.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:08.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:08.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:08.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:08.91#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:11:08.91#ibcon#first serial, iclass 6, count 0 2006.182.08:11:08.91#ibcon#enter sib2, iclass 6, count 0 2006.182.08:11:08.91#ibcon#flushed, iclass 6, count 0 2006.182.08:11:08.91#ibcon#about to write, iclass 6, count 0 2006.182.08:11:08.91#ibcon#wrote, iclass 6, count 0 2006.182.08:11:08.91#ibcon#about to read 3, iclass 6, count 0 2006.182.08:11:08.93#ibcon#read 3, iclass 6, count 0 2006.182.08:11:08.93#ibcon#about to read 4, iclass 6, count 0 2006.182.08:11:08.93#ibcon#read 4, iclass 6, count 0 2006.182.08:11:08.93#ibcon#about to read 5, iclass 6, count 0 2006.182.08:11:08.93#ibcon#read 5, iclass 6, count 0 2006.182.08:11:08.93#ibcon#about to read 6, iclass 6, count 0 2006.182.08:11:08.93#ibcon#read 6, iclass 6, count 0 2006.182.08:11:08.93#ibcon#end of sib2, iclass 6, count 0 2006.182.08:11:08.93#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:11:08.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:11:08.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:11:08.93#ibcon#*before write, iclass 6, count 0 2006.182.08:11:08.93#ibcon#enter sib2, iclass 6, count 0 2006.182.08:11:08.93#ibcon#flushed, iclass 6, count 0 2006.182.08:11:08.93#ibcon#about to write, iclass 6, count 0 2006.182.08:11:08.93#ibcon#wrote, iclass 6, count 0 2006.182.08:11:08.93#ibcon#about to read 3, iclass 6, count 0 2006.182.08:11:08.97#ibcon#read 3, iclass 6, count 0 2006.182.08:11:08.97#ibcon#about to read 4, iclass 6, count 0 2006.182.08:11:08.97#ibcon#read 4, iclass 6, count 0 2006.182.08:11:08.97#ibcon#about to read 5, iclass 6, count 0 2006.182.08:11:08.97#ibcon#read 5, iclass 6, count 0 2006.182.08:11:08.97#ibcon#about to read 6, iclass 6, count 0 2006.182.08:11:08.97#ibcon#read 6, iclass 6, count 0 2006.182.08:11:08.97#ibcon#end of sib2, iclass 6, count 0 2006.182.08:11:08.97#ibcon#*after write, iclass 6, count 0 2006.182.08:11:08.97#ibcon#*before return 0, iclass 6, count 0 2006.182.08:11:08.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:08.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:08.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:11:08.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:11:08.97$vc4f8/va=4,7 2006.182.08:11:08.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.08:11:08.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.08:11:08.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:08.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:09.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:09.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:09.03#ibcon#enter wrdev, iclass 10, count 2 2006.182.08:11:09.03#ibcon#first serial, iclass 10, count 2 2006.182.08:11:09.03#ibcon#enter sib2, iclass 10, count 2 2006.182.08:11:09.03#ibcon#flushed, iclass 10, count 2 2006.182.08:11:09.03#ibcon#about to write, iclass 10, count 2 2006.182.08:11:09.03#ibcon#wrote, iclass 10, count 2 2006.182.08:11:09.03#ibcon#about to read 3, iclass 10, count 2 2006.182.08:11:09.05#ibcon#read 3, iclass 10, count 2 2006.182.08:11:09.05#ibcon#about to read 4, iclass 10, count 2 2006.182.08:11:09.05#ibcon#read 4, iclass 10, count 2 2006.182.08:11:09.05#ibcon#about to read 5, iclass 10, count 2 2006.182.08:11:09.05#ibcon#read 5, iclass 10, count 2 2006.182.08:11:09.05#ibcon#about to read 6, iclass 10, count 2 2006.182.08:11:09.05#ibcon#read 6, iclass 10, count 2 2006.182.08:11:09.05#ibcon#end of sib2, iclass 10, count 2 2006.182.08:11:09.05#ibcon#*mode == 0, iclass 10, count 2 2006.182.08:11:09.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.08:11:09.05#ibcon#[25=AT04-07\r\n] 2006.182.08:11:09.05#ibcon#*before write, iclass 10, count 2 2006.182.08:11:09.05#ibcon#enter sib2, iclass 10, count 2 2006.182.08:11:09.05#ibcon#flushed, iclass 10, count 2 2006.182.08:11:09.05#ibcon#about to write, iclass 10, count 2 2006.182.08:11:09.05#ibcon#wrote, iclass 10, count 2 2006.182.08:11:09.05#ibcon#about to read 3, iclass 10, count 2 2006.182.08:11:09.08#ibcon#read 3, iclass 10, count 2 2006.182.08:11:09.08#ibcon#about to read 4, iclass 10, count 2 2006.182.08:11:09.08#ibcon#read 4, iclass 10, count 2 2006.182.08:11:09.08#ibcon#about to read 5, iclass 10, count 2 2006.182.08:11:09.08#ibcon#read 5, iclass 10, count 2 2006.182.08:11:09.08#ibcon#about to read 6, iclass 10, count 2 2006.182.08:11:09.08#ibcon#read 6, iclass 10, count 2 2006.182.08:11:09.08#ibcon#end of sib2, iclass 10, count 2 2006.182.08:11:09.08#ibcon#*after write, iclass 10, count 2 2006.182.08:11:09.08#ibcon#*before return 0, iclass 10, count 2 2006.182.08:11:09.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:09.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:09.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.08:11:09.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:09.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:09.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:09.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:09.20#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:11:09.20#ibcon#first serial, iclass 10, count 0 2006.182.08:11:09.20#ibcon#enter sib2, iclass 10, count 0 2006.182.08:11:09.20#ibcon#flushed, iclass 10, count 0 2006.182.08:11:09.20#ibcon#about to write, iclass 10, count 0 2006.182.08:11:09.20#ibcon#wrote, iclass 10, count 0 2006.182.08:11:09.20#ibcon#about to read 3, iclass 10, count 0 2006.182.08:11:09.22#ibcon#read 3, iclass 10, count 0 2006.182.08:11:09.22#ibcon#about to read 4, iclass 10, count 0 2006.182.08:11:09.22#ibcon#read 4, iclass 10, count 0 2006.182.08:11:09.22#ibcon#about to read 5, iclass 10, count 0 2006.182.08:11:09.22#ibcon#read 5, iclass 10, count 0 2006.182.08:11:09.22#ibcon#about to read 6, iclass 10, count 0 2006.182.08:11:09.22#ibcon#read 6, iclass 10, count 0 2006.182.08:11:09.22#ibcon#end of sib2, iclass 10, count 0 2006.182.08:11:09.22#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:11:09.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:11:09.22#ibcon#[25=USB\r\n] 2006.182.08:11:09.22#ibcon#*before write, iclass 10, count 0 2006.182.08:11:09.22#ibcon#enter sib2, iclass 10, count 0 2006.182.08:11:09.22#ibcon#flushed, iclass 10, count 0 2006.182.08:11:09.22#ibcon#about to write, iclass 10, count 0 2006.182.08:11:09.22#ibcon#wrote, iclass 10, count 0 2006.182.08:11:09.22#ibcon#about to read 3, iclass 10, count 0 2006.182.08:11:09.25#ibcon#read 3, iclass 10, count 0 2006.182.08:11:09.25#ibcon#about to read 4, iclass 10, count 0 2006.182.08:11:09.25#ibcon#read 4, iclass 10, count 0 2006.182.08:11:09.25#ibcon#about to read 5, iclass 10, count 0 2006.182.08:11:09.25#ibcon#read 5, iclass 10, count 0 2006.182.08:11:09.25#ibcon#about to read 6, iclass 10, count 0 2006.182.08:11:09.25#ibcon#read 6, iclass 10, count 0 2006.182.08:11:09.25#ibcon#end of sib2, iclass 10, count 0 2006.182.08:11:09.25#ibcon#*after write, iclass 10, count 0 2006.182.08:11:09.25#ibcon#*before return 0, iclass 10, count 0 2006.182.08:11:09.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:09.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:09.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:11:09.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:11:09.25$vc4f8/valo=5,652.99 2006.182.08:11:09.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.08:11:09.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.08:11:09.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:09.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:09.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:09.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:09.25#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:11:09.25#ibcon#first serial, iclass 12, count 0 2006.182.08:11:09.25#ibcon#enter sib2, iclass 12, count 0 2006.182.08:11:09.25#ibcon#flushed, iclass 12, count 0 2006.182.08:11:09.25#ibcon#about to write, iclass 12, count 0 2006.182.08:11:09.25#ibcon#wrote, iclass 12, count 0 2006.182.08:11:09.25#ibcon#about to read 3, iclass 12, count 0 2006.182.08:11:09.27#ibcon#read 3, iclass 12, count 0 2006.182.08:11:09.27#ibcon#about to read 4, iclass 12, count 0 2006.182.08:11:09.27#ibcon#read 4, iclass 12, count 0 2006.182.08:11:09.27#ibcon#about to read 5, iclass 12, count 0 2006.182.08:11:09.27#ibcon#read 5, iclass 12, count 0 2006.182.08:11:09.27#ibcon#about to read 6, iclass 12, count 0 2006.182.08:11:09.27#ibcon#read 6, iclass 12, count 0 2006.182.08:11:09.27#ibcon#end of sib2, iclass 12, count 0 2006.182.08:11:09.27#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:11:09.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:11:09.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:11:09.27#ibcon#*before write, iclass 12, count 0 2006.182.08:11:09.27#ibcon#enter sib2, iclass 12, count 0 2006.182.08:11:09.27#ibcon#flushed, iclass 12, count 0 2006.182.08:11:09.27#ibcon#about to write, iclass 12, count 0 2006.182.08:11:09.27#ibcon#wrote, iclass 12, count 0 2006.182.08:11:09.27#ibcon#about to read 3, iclass 12, count 0 2006.182.08:11:09.31#ibcon#read 3, iclass 12, count 0 2006.182.08:11:09.31#ibcon#about to read 4, iclass 12, count 0 2006.182.08:11:09.31#ibcon#read 4, iclass 12, count 0 2006.182.08:11:09.31#ibcon#about to read 5, iclass 12, count 0 2006.182.08:11:09.31#ibcon#read 5, iclass 12, count 0 2006.182.08:11:09.31#ibcon#about to read 6, iclass 12, count 0 2006.182.08:11:09.31#ibcon#read 6, iclass 12, count 0 2006.182.08:11:09.31#ibcon#end of sib2, iclass 12, count 0 2006.182.08:11:09.31#ibcon#*after write, iclass 12, count 0 2006.182.08:11:09.31#ibcon#*before return 0, iclass 12, count 0 2006.182.08:11:09.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:09.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:09.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:11:09.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:11:09.31$vc4f8/va=5,7 2006.182.08:11:09.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.08:11:09.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.08:11:09.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:09.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:09.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:09.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:09.37#ibcon#enter wrdev, iclass 14, count 2 2006.182.08:11:09.37#ibcon#first serial, iclass 14, count 2 2006.182.08:11:09.37#ibcon#enter sib2, iclass 14, count 2 2006.182.08:11:09.37#ibcon#flushed, iclass 14, count 2 2006.182.08:11:09.37#ibcon#about to write, iclass 14, count 2 2006.182.08:11:09.37#ibcon#wrote, iclass 14, count 2 2006.182.08:11:09.37#ibcon#about to read 3, iclass 14, count 2 2006.182.08:11:09.39#ibcon#read 3, iclass 14, count 2 2006.182.08:11:09.39#ibcon#about to read 4, iclass 14, count 2 2006.182.08:11:09.39#ibcon#read 4, iclass 14, count 2 2006.182.08:11:09.39#ibcon#about to read 5, iclass 14, count 2 2006.182.08:11:09.39#ibcon#read 5, iclass 14, count 2 2006.182.08:11:09.39#ibcon#about to read 6, iclass 14, count 2 2006.182.08:11:09.39#ibcon#read 6, iclass 14, count 2 2006.182.08:11:09.39#ibcon#end of sib2, iclass 14, count 2 2006.182.08:11:09.39#ibcon#*mode == 0, iclass 14, count 2 2006.182.08:11:09.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.08:11:09.39#ibcon#[25=AT05-07\r\n] 2006.182.08:11:09.39#ibcon#*before write, iclass 14, count 2 2006.182.08:11:09.39#ibcon#enter sib2, iclass 14, count 2 2006.182.08:11:09.39#ibcon#flushed, iclass 14, count 2 2006.182.08:11:09.39#ibcon#about to write, iclass 14, count 2 2006.182.08:11:09.39#ibcon#wrote, iclass 14, count 2 2006.182.08:11:09.39#ibcon#about to read 3, iclass 14, count 2 2006.182.08:11:09.42#ibcon#read 3, iclass 14, count 2 2006.182.08:11:09.42#ibcon#about to read 4, iclass 14, count 2 2006.182.08:11:09.42#ibcon#read 4, iclass 14, count 2 2006.182.08:11:09.42#ibcon#about to read 5, iclass 14, count 2 2006.182.08:11:09.42#ibcon#read 5, iclass 14, count 2 2006.182.08:11:09.42#ibcon#about to read 6, iclass 14, count 2 2006.182.08:11:09.42#ibcon#read 6, iclass 14, count 2 2006.182.08:11:09.42#ibcon#end of sib2, iclass 14, count 2 2006.182.08:11:09.42#ibcon#*after write, iclass 14, count 2 2006.182.08:11:09.42#ibcon#*before return 0, iclass 14, count 2 2006.182.08:11:09.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:09.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:09.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.08:11:09.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:09.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:09.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:09.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:09.54#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:11:09.54#ibcon#first serial, iclass 14, count 0 2006.182.08:11:09.54#ibcon#enter sib2, iclass 14, count 0 2006.182.08:11:09.54#ibcon#flushed, iclass 14, count 0 2006.182.08:11:09.54#ibcon#about to write, iclass 14, count 0 2006.182.08:11:09.54#ibcon#wrote, iclass 14, count 0 2006.182.08:11:09.54#ibcon#about to read 3, iclass 14, count 0 2006.182.08:11:09.56#ibcon#read 3, iclass 14, count 0 2006.182.08:11:09.56#ibcon#about to read 4, iclass 14, count 0 2006.182.08:11:09.56#ibcon#read 4, iclass 14, count 0 2006.182.08:11:09.56#ibcon#about to read 5, iclass 14, count 0 2006.182.08:11:09.56#ibcon#read 5, iclass 14, count 0 2006.182.08:11:09.56#ibcon#about to read 6, iclass 14, count 0 2006.182.08:11:09.56#ibcon#read 6, iclass 14, count 0 2006.182.08:11:09.56#ibcon#end of sib2, iclass 14, count 0 2006.182.08:11:09.56#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:11:09.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:11:09.56#ibcon#[25=USB\r\n] 2006.182.08:11:09.56#ibcon#*before write, iclass 14, count 0 2006.182.08:11:09.56#ibcon#enter sib2, iclass 14, count 0 2006.182.08:11:09.56#ibcon#flushed, iclass 14, count 0 2006.182.08:11:09.56#ibcon#about to write, iclass 14, count 0 2006.182.08:11:09.56#ibcon#wrote, iclass 14, count 0 2006.182.08:11:09.56#ibcon#about to read 3, iclass 14, count 0 2006.182.08:11:09.59#ibcon#read 3, iclass 14, count 0 2006.182.08:11:09.59#ibcon#about to read 4, iclass 14, count 0 2006.182.08:11:09.59#ibcon#read 4, iclass 14, count 0 2006.182.08:11:09.59#ibcon#about to read 5, iclass 14, count 0 2006.182.08:11:09.59#ibcon#read 5, iclass 14, count 0 2006.182.08:11:09.59#ibcon#about to read 6, iclass 14, count 0 2006.182.08:11:09.59#ibcon#read 6, iclass 14, count 0 2006.182.08:11:09.59#ibcon#end of sib2, iclass 14, count 0 2006.182.08:11:09.59#ibcon#*after write, iclass 14, count 0 2006.182.08:11:09.59#ibcon#*before return 0, iclass 14, count 0 2006.182.08:11:09.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:09.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:09.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:11:09.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:11:09.59$vc4f8/valo=6,772.99 2006.182.08:11:09.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.08:11:09.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.08:11:09.59#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:09.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:09.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:09.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:09.59#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:11:09.59#ibcon#first serial, iclass 16, count 0 2006.182.08:11:09.59#ibcon#enter sib2, iclass 16, count 0 2006.182.08:11:09.59#ibcon#flushed, iclass 16, count 0 2006.182.08:11:09.59#ibcon#about to write, iclass 16, count 0 2006.182.08:11:09.59#ibcon#wrote, iclass 16, count 0 2006.182.08:11:09.59#ibcon#about to read 3, iclass 16, count 0 2006.182.08:11:09.61#ibcon#read 3, iclass 16, count 0 2006.182.08:11:09.61#ibcon#about to read 4, iclass 16, count 0 2006.182.08:11:09.61#ibcon#read 4, iclass 16, count 0 2006.182.08:11:09.61#ibcon#about to read 5, iclass 16, count 0 2006.182.08:11:09.61#ibcon#read 5, iclass 16, count 0 2006.182.08:11:09.61#ibcon#about to read 6, iclass 16, count 0 2006.182.08:11:09.61#ibcon#read 6, iclass 16, count 0 2006.182.08:11:09.61#ibcon#end of sib2, iclass 16, count 0 2006.182.08:11:09.61#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:11:09.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:11:09.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:11:09.61#ibcon#*before write, iclass 16, count 0 2006.182.08:11:09.61#ibcon#enter sib2, iclass 16, count 0 2006.182.08:11:09.61#ibcon#flushed, iclass 16, count 0 2006.182.08:11:09.61#ibcon#about to write, iclass 16, count 0 2006.182.08:11:09.61#ibcon#wrote, iclass 16, count 0 2006.182.08:11:09.61#ibcon#about to read 3, iclass 16, count 0 2006.182.08:11:09.65#ibcon#read 3, iclass 16, count 0 2006.182.08:11:09.65#ibcon#about to read 4, iclass 16, count 0 2006.182.08:11:09.65#ibcon#read 4, iclass 16, count 0 2006.182.08:11:09.65#ibcon#about to read 5, iclass 16, count 0 2006.182.08:11:09.65#ibcon#read 5, iclass 16, count 0 2006.182.08:11:09.65#ibcon#about to read 6, iclass 16, count 0 2006.182.08:11:09.65#ibcon#read 6, iclass 16, count 0 2006.182.08:11:09.65#ibcon#end of sib2, iclass 16, count 0 2006.182.08:11:09.65#ibcon#*after write, iclass 16, count 0 2006.182.08:11:09.65#ibcon#*before return 0, iclass 16, count 0 2006.182.08:11:09.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:09.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:09.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:11:09.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:11:09.65$vc4f8/va=6,6 2006.182.08:11:09.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.08:11:09.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.08:11:09.65#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:09.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:11:09.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:11:09.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:11:09.71#ibcon#enter wrdev, iclass 18, count 2 2006.182.08:11:09.71#ibcon#first serial, iclass 18, count 2 2006.182.08:11:09.71#ibcon#enter sib2, iclass 18, count 2 2006.182.08:11:09.71#ibcon#flushed, iclass 18, count 2 2006.182.08:11:09.71#ibcon#about to write, iclass 18, count 2 2006.182.08:11:09.71#ibcon#wrote, iclass 18, count 2 2006.182.08:11:09.71#ibcon#about to read 3, iclass 18, count 2 2006.182.08:11:09.73#ibcon#read 3, iclass 18, count 2 2006.182.08:11:09.73#ibcon#about to read 4, iclass 18, count 2 2006.182.08:11:09.73#ibcon#read 4, iclass 18, count 2 2006.182.08:11:09.73#ibcon#about to read 5, iclass 18, count 2 2006.182.08:11:09.73#ibcon#read 5, iclass 18, count 2 2006.182.08:11:09.73#ibcon#about to read 6, iclass 18, count 2 2006.182.08:11:09.73#ibcon#read 6, iclass 18, count 2 2006.182.08:11:09.73#ibcon#end of sib2, iclass 18, count 2 2006.182.08:11:09.73#ibcon#*mode == 0, iclass 18, count 2 2006.182.08:11:09.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.08:11:09.73#ibcon#[25=AT06-06\r\n] 2006.182.08:11:09.73#ibcon#*before write, iclass 18, count 2 2006.182.08:11:09.73#ibcon#enter sib2, iclass 18, count 2 2006.182.08:11:09.73#ibcon#flushed, iclass 18, count 2 2006.182.08:11:09.73#ibcon#about to write, iclass 18, count 2 2006.182.08:11:09.73#ibcon#wrote, iclass 18, count 2 2006.182.08:11:09.73#ibcon#about to read 3, iclass 18, count 2 2006.182.08:11:09.76#ibcon#read 3, iclass 18, count 2 2006.182.08:11:09.76#ibcon#about to read 4, iclass 18, count 2 2006.182.08:11:09.76#ibcon#read 4, iclass 18, count 2 2006.182.08:11:09.76#ibcon#about to read 5, iclass 18, count 2 2006.182.08:11:09.76#ibcon#read 5, iclass 18, count 2 2006.182.08:11:09.76#ibcon#about to read 6, iclass 18, count 2 2006.182.08:11:09.76#ibcon#read 6, iclass 18, count 2 2006.182.08:11:09.76#ibcon#end of sib2, iclass 18, count 2 2006.182.08:11:09.76#ibcon#*after write, iclass 18, count 2 2006.182.08:11:09.76#ibcon#*before return 0, iclass 18, count 2 2006.182.08:11:09.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:11:09.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:11:09.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.08:11:09.76#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:09.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:11:09.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:11:09.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:11:09.88#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:11:09.88#ibcon#first serial, iclass 18, count 0 2006.182.08:11:09.88#ibcon#enter sib2, iclass 18, count 0 2006.182.08:11:09.88#ibcon#flushed, iclass 18, count 0 2006.182.08:11:09.88#ibcon#about to write, iclass 18, count 0 2006.182.08:11:09.88#ibcon#wrote, iclass 18, count 0 2006.182.08:11:09.88#ibcon#about to read 3, iclass 18, count 0 2006.182.08:11:09.90#ibcon#read 3, iclass 18, count 0 2006.182.08:11:09.90#ibcon#about to read 4, iclass 18, count 0 2006.182.08:11:09.90#ibcon#read 4, iclass 18, count 0 2006.182.08:11:09.90#ibcon#about to read 5, iclass 18, count 0 2006.182.08:11:09.90#ibcon#read 5, iclass 18, count 0 2006.182.08:11:09.90#ibcon#about to read 6, iclass 18, count 0 2006.182.08:11:09.90#ibcon#read 6, iclass 18, count 0 2006.182.08:11:09.90#ibcon#end of sib2, iclass 18, count 0 2006.182.08:11:09.90#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:11:09.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:11:09.90#ibcon#[25=USB\r\n] 2006.182.08:11:09.90#ibcon#*before write, iclass 18, count 0 2006.182.08:11:09.90#ibcon#enter sib2, iclass 18, count 0 2006.182.08:11:09.90#ibcon#flushed, iclass 18, count 0 2006.182.08:11:09.90#ibcon#about to write, iclass 18, count 0 2006.182.08:11:09.90#ibcon#wrote, iclass 18, count 0 2006.182.08:11:09.90#ibcon#about to read 3, iclass 18, count 0 2006.182.08:11:09.93#ibcon#read 3, iclass 18, count 0 2006.182.08:11:09.93#ibcon#about to read 4, iclass 18, count 0 2006.182.08:11:09.93#ibcon#read 4, iclass 18, count 0 2006.182.08:11:09.93#ibcon#about to read 5, iclass 18, count 0 2006.182.08:11:09.93#ibcon#read 5, iclass 18, count 0 2006.182.08:11:09.93#ibcon#about to read 6, iclass 18, count 0 2006.182.08:11:09.93#ibcon#read 6, iclass 18, count 0 2006.182.08:11:09.93#ibcon#end of sib2, iclass 18, count 0 2006.182.08:11:09.93#ibcon#*after write, iclass 18, count 0 2006.182.08:11:09.93#ibcon#*before return 0, iclass 18, count 0 2006.182.08:11:09.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:11:09.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:11:09.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:11:09.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:11:09.93$vc4f8/valo=7,832.99 2006.182.08:11:09.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.08:11:09.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.08:11:09.93#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:09.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:11:09.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:11:09.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:11:09.93#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:11:09.93#ibcon#first serial, iclass 20, count 0 2006.182.08:11:09.93#ibcon#enter sib2, iclass 20, count 0 2006.182.08:11:09.93#ibcon#flushed, iclass 20, count 0 2006.182.08:11:09.93#ibcon#about to write, iclass 20, count 0 2006.182.08:11:09.93#ibcon#wrote, iclass 20, count 0 2006.182.08:11:09.93#ibcon#about to read 3, iclass 20, count 0 2006.182.08:11:09.95#ibcon#read 3, iclass 20, count 0 2006.182.08:11:09.95#ibcon#about to read 4, iclass 20, count 0 2006.182.08:11:09.95#ibcon#read 4, iclass 20, count 0 2006.182.08:11:09.95#ibcon#about to read 5, iclass 20, count 0 2006.182.08:11:09.95#ibcon#read 5, iclass 20, count 0 2006.182.08:11:09.95#ibcon#about to read 6, iclass 20, count 0 2006.182.08:11:09.95#ibcon#read 6, iclass 20, count 0 2006.182.08:11:09.95#ibcon#end of sib2, iclass 20, count 0 2006.182.08:11:09.95#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:11:09.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:11:09.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:11:09.95#ibcon#*before write, iclass 20, count 0 2006.182.08:11:09.95#ibcon#enter sib2, iclass 20, count 0 2006.182.08:11:09.95#ibcon#flushed, iclass 20, count 0 2006.182.08:11:09.95#ibcon#about to write, iclass 20, count 0 2006.182.08:11:09.95#ibcon#wrote, iclass 20, count 0 2006.182.08:11:09.95#ibcon#about to read 3, iclass 20, count 0 2006.182.08:11:09.99#ibcon#read 3, iclass 20, count 0 2006.182.08:11:09.99#ibcon#about to read 4, iclass 20, count 0 2006.182.08:11:09.99#ibcon#read 4, iclass 20, count 0 2006.182.08:11:09.99#ibcon#about to read 5, iclass 20, count 0 2006.182.08:11:09.99#ibcon#read 5, iclass 20, count 0 2006.182.08:11:09.99#ibcon#about to read 6, iclass 20, count 0 2006.182.08:11:09.99#ibcon#read 6, iclass 20, count 0 2006.182.08:11:09.99#ibcon#end of sib2, iclass 20, count 0 2006.182.08:11:09.99#ibcon#*after write, iclass 20, count 0 2006.182.08:11:09.99#ibcon#*before return 0, iclass 20, count 0 2006.182.08:11:09.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:11:09.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:11:09.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:11:09.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:11:09.99$vc4f8/va=7,6 2006.182.08:11:09.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.08:11:09.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.08:11:09.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:09.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:11:10.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:11:10.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:11:10.05#ibcon#enter wrdev, iclass 22, count 2 2006.182.08:11:10.05#ibcon#first serial, iclass 22, count 2 2006.182.08:11:10.05#ibcon#enter sib2, iclass 22, count 2 2006.182.08:11:10.05#ibcon#flushed, iclass 22, count 2 2006.182.08:11:10.05#ibcon#about to write, iclass 22, count 2 2006.182.08:11:10.05#ibcon#wrote, iclass 22, count 2 2006.182.08:11:10.05#ibcon#about to read 3, iclass 22, count 2 2006.182.08:11:10.07#ibcon#read 3, iclass 22, count 2 2006.182.08:11:10.07#ibcon#about to read 4, iclass 22, count 2 2006.182.08:11:10.07#ibcon#read 4, iclass 22, count 2 2006.182.08:11:10.07#ibcon#about to read 5, iclass 22, count 2 2006.182.08:11:10.07#ibcon#read 5, iclass 22, count 2 2006.182.08:11:10.07#ibcon#about to read 6, iclass 22, count 2 2006.182.08:11:10.07#ibcon#read 6, iclass 22, count 2 2006.182.08:11:10.07#ibcon#end of sib2, iclass 22, count 2 2006.182.08:11:10.07#ibcon#*mode == 0, iclass 22, count 2 2006.182.08:11:10.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.08:11:10.07#ibcon#[25=AT07-06\r\n] 2006.182.08:11:10.07#ibcon#*before write, iclass 22, count 2 2006.182.08:11:10.07#ibcon#enter sib2, iclass 22, count 2 2006.182.08:11:10.07#ibcon#flushed, iclass 22, count 2 2006.182.08:11:10.07#ibcon#about to write, iclass 22, count 2 2006.182.08:11:10.07#ibcon#wrote, iclass 22, count 2 2006.182.08:11:10.07#ibcon#about to read 3, iclass 22, count 2 2006.182.08:11:10.10#ibcon#read 3, iclass 22, count 2 2006.182.08:11:10.10#ibcon#about to read 4, iclass 22, count 2 2006.182.08:11:10.10#ibcon#read 4, iclass 22, count 2 2006.182.08:11:10.10#ibcon#about to read 5, iclass 22, count 2 2006.182.08:11:10.10#ibcon#read 5, iclass 22, count 2 2006.182.08:11:10.10#ibcon#about to read 6, iclass 22, count 2 2006.182.08:11:10.10#ibcon#read 6, iclass 22, count 2 2006.182.08:11:10.10#ibcon#end of sib2, iclass 22, count 2 2006.182.08:11:10.10#ibcon#*after write, iclass 22, count 2 2006.182.08:11:10.10#ibcon#*before return 0, iclass 22, count 2 2006.182.08:11:10.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:11:10.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:11:10.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.08:11:10.10#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:10.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:11:10.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:11:10.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:11:10.22#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:11:10.22#ibcon#first serial, iclass 22, count 0 2006.182.08:11:10.22#ibcon#enter sib2, iclass 22, count 0 2006.182.08:11:10.22#ibcon#flushed, iclass 22, count 0 2006.182.08:11:10.22#ibcon#about to write, iclass 22, count 0 2006.182.08:11:10.22#ibcon#wrote, iclass 22, count 0 2006.182.08:11:10.22#ibcon#about to read 3, iclass 22, count 0 2006.182.08:11:10.24#ibcon#read 3, iclass 22, count 0 2006.182.08:11:10.24#ibcon#about to read 4, iclass 22, count 0 2006.182.08:11:10.24#ibcon#read 4, iclass 22, count 0 2006.182.08:11:10.24#ibcon#about to read 5, iclass 22, count 0 2006.182.08:11:10.24#ibcon#read 5, iclass 22, count 0 2006.182.08:11:10.24#ibcon#about to read 6, iclass 22, count 0 2006.182.08:11:10.24#ibcon#read 6, iclass 22, count 0 2006.182.08:11:10.24#ibcon#end of sib2, iclass 22, count 0 2006.182.08:11:10.24#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:11:10.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:11:10.24#ibcon#[25=USB\r\n] 2006.182.08:11:10.24#ibcon#*before write, iclass 22, count 0 2006.182.08:11:10.24#ibcon#enter sib2, iclass 22, count 0 2006.182.08:11:10.24#ibcon#flushed, iclass 22, count 0 2006.182.08:11:10.24#ibcon#about to write, iclass 22, count 0 2006.182.08:11:10.24#ibcon#wrote, iclass 22, count 0 2006.182.08:11:10.24#ibcon#about to read 3, iclass 22, count 0 2006.182.08:11:10.27#ibcon#read 3, iclass 22, count 0 2006.182.08:11:10.27#ibcon#about to read 4, iclass 22, count 0 2006.182.08:11:10.27#ibcon#read 4, iclass 22, count 0 2006.182.08:11:10.27#ibcon#about to read 5, iclass 22, count 0 2006.182.08:11:10.27#ibcon#read 5, iclass 22, count 0 2006.182.08:11:10.27#ibcon#about to read 6, iclass 22, count 0 2006.182.08:11:10.27#ibcon#read 6, iclass 22, count 0 2006.182.08:11:10.27#ibcon#end of sib2, iclass 22, count 0 2006.182.08:11:10.27#ibcon#*after write, iclass 22, count 0 2006.182.08:11:10.27#ibcon#*before return 0, iclass 22, count 0 2006.182.08:11:10.27#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:11:10.27#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:11:10.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:11:10.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:11:10.27$vc4f8/valo=8,852.99 2006.182.08:11:10.27#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.08:11:10.27#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.08:11:10.27#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:10.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:11:10.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:11:10.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:11:10.27#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:11:10.27#ibcon#first serial, iclass 24, count 0 2006.182.08:11:10.27#ibcon#enter sib2, iclass 24, count 0 2006.182.08:11:10.27#ibcon#flushed, iclass 24, count 0 2006.182.08:11:10.27#ibcon#about to write, iclass 24, count 0 2006.182.08:11:10.27#ibcon#wrote, iclass 24, count 0 2006.182.08:11:10.27#ibcon#about to read 3, iclass 24, count 0 2006.182.08:11:10.29#ibcon#read 3, iclass 24, count 0 2006.182.08:11:10.29#ibcon#about to read 4, iclass 24, count 0 2006.182.08:11:10.29#ibcon#read 4, iclass 24, count 0 2006.182.08:11:10.29#ibcon#about to read 5, iclass 24, count 0 2006.182.08:11:10.29#ibcon#read 5, iclass 24, count 0 2006.182.08:11:10.29#ibcon#about to read 6, iclass 24, count 0 2006.182.08:11:10.29#ibcon#read 6, iclass 24, count 0 2006.182.08:11:10.29#ibcon#end of sib2, iclass 24, count 0 2006.182.08:11:10.29#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:11:10.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:11:10.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:11:10.29#ibcon#*before write, iclass 24, count 0 2006.182.08:11:10.29#ibcon#enter sib2, iclass 24, count 0 2006.182.08:11:10.29#ibcon#flushed, iclass 24, count 0 2006.182.08:11:10.29#ibcon#about to write, iclass 24, count 0 2006.182.08:11:10.29#ibcon#wrote, iclass 24, count 0 2006.182.08:11:10.29#ibcon#about to read 3, iclass 24, count 0 2006.182.08:11:10.33#ibcon#read 3, iclass 24, count 0 2006.182.08:11:10.33#ibcon#about to read 4, iclass 24, count 0 2006.182.08:11:10.33#ibcon#read 4, iclass 24, count 0 2006.182.08:11:10.33#ibcon#about to read 5, iclass 24, count 0 2006.182.08:11:10.33#ibcon#read 5, iclass 24, count 0 2006.182.08:11:10.33#ibcon#about to read 6, iclass 24, count 0 2006.182.08:11:10.33#ibcon#read 6, iclass 24, count 0 2006.182.08:11:10.33#ibcon#end of sib2, iclass 24, count 0 2006.182.08:11:10.33#ibcon#*after write, iclass 24, count 0 2006.182.08:11:10.33#ibcon#*before return 0, iclass 24, count 0 2006.182.08:11:10.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:11:10.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:11:10.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:11:10.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:11:10.33$vc4f8/va=8,7 2006.182.08:11:10.33#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.08:11:10.33#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.08:11:10.33#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:10.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:11:10.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:11:10.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:11:10.39#ibcon#enter wrdev, iclass 26, count 2 2006.182.08:11:10.39#ibcon#first serial, iclass 26, count 2 2006.182.08:11:10.39#ibcon#enter sib2, iclass 26, count 2 2006.182.08:11:10.39#ibcon#flushed, iclass 26, count 2 2006.182.08:11:10.39#ibcon#about to write, iclass 26, count 2 2006.182.08:11:10.39#ibcon#wrote, iclass 26, count 2 2006.182.08:11:10.39#ibcon#about to read 3, iclass 26, count 2 2006.182.08:11:10.41#ibcon#read 3, iclass 26, count 2 2006.182.08:11:10.41#ibcon#about to read 4, iclass 26, count 2 2006.182.08:11:10.41#ibcon#read 4, iclass 26, count 2 2006.182.08:11:10.41#ibcon#about to read 5, iclass 26, count 2 2006.182.08:11:10.41#ibcon#read 5, iclass 26, count 2 2006.182.08:11:10.41#ibcon#about to read 6, iclass 26, count 2 2006.182.08:11:10.41#ibcon#read 6, iclass 26, count 2 2006.182.08:11:10.41#ibcon#end of sib2, iclass 26, count 2 2006.182.08:11:10.41#ibcon#*mode == 0, iclass 26, count 2 2006.182.08:11:10.41#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.08:11:10.41#ibcon#[25=AT08-07\r\n] 2006.182.08:11:10.41#ibcon#*before write, iclass 26, count 2 2006.182.08:11:10.41#ibcon#enter sib2, iclass 26, count 2 2006.182.08:11:10.41#ibcon#flushed, iclass 26, count 2 2006.182.08:11:10.41#ibcon#about to write, iclass 26, count 2 2006.182.08:11:10.41#ibcon#wrote, iclass 26, count 2 2006.182.08:11:10.41#ibcon#about to read 3, iclass 26, count 2 2006.182.08:11:10.44#ibcon#read 3, iclass 26, count 2 2006.182.08:11:10.44#ibcon#about to read 4, iclass 26, count 2 2006.182.08:11:10.44#ibcon#read 4, iclass 26, count 2 2006.182.08:11:10.44#ibcon#about to read 5, iclass 26, count 2 2006.182.08:11:10.44#ibcon#read 5, iclass 26, count 2 2006.182.08:11:10.44#ibcon#about to read 6, iclass 26, count 2 2006.182.08:11:10.44#ibcon#read 6, iclass 26, count 2 2006.182.08:11:10.44#ibcon#end of sib2, iclass 26, count 2 2006.182.08:11:10.44#ibcon#*after write, iclass 26, count 2 2006.182.08:11:10.44#ibcon#*before return 0, iclass 26, count 2 2006.182.08:11:10.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:11:10.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:11:10.44#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.08:11:10.44#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:10.44#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:11:10.56#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:11:10.56#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:11:10.56#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:11:10.56#ibcon#first serial, iclass 26, count 0 2006.182.08:11:10.56#ibcon#enter sib2, iclass 26, count 0 2006.182.08:11:10.56#ibcon#flushed, iclass 26, count 0 2006.182.08:11:10.56#ibcon#about to write, iclass 26, count 0 2006.182.08:11:10.56#ibcon#wrote, iclass 26, count 0 2006.182.08:11:10.56#ibcon#about to read 3, iclass 26, count 0 2006.182.08:11:10.58#ibcon#read 3, iclass 26, count 0 2006.182.08:11:10.58#ibcon#about to read 4, iclass 26, count 0 2006.182.08:11:10.58#ibcon#read 4, iclass 26, count 0 2006.182.08:11:10.58#ibcon#about to read 5, iclass 26, count 0 2006.182.08:11:10.58#ibcon#read 5, iclass 26, count 0 2006.182.08:11:10.58#ibcon#about to read 6, iclass 26, count 0 2006.182.08:11:10.58#ibcon#read 6, iclass 26, count 0 2006.182.08:11:10.58#ibcon#end of sib2, iclass 26, count 0 2006.182.08:11:10.58#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:11:10.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:11:10.58#ibcon#[25=USB\r\n] 2006.182.08:11:10.58#ibcon#*before write, iclass 26, count 0 2006.182.08:11:10.58#ibcon#enter sib2, iclass 26, count 0 2006.182.08:11:10.58#ibcon#flushed, iclass 26, count 0 2006.182.08:11:10.58#ibcon#about to write, iclass 26, count 0 2006.182.08:11:10.58#ibcon#wrote, iclass 26, count 0 2006.182.08:11:10.58#ibcon#about to read 3, iclass 26, count 0 2006.182.08:11:10.61#ibcon#read 3, iclass 26, count 0 2006.182.08:11:10.61#ibcon#about to read 4, iclass 26, count 0 2006.182.08:11:10.61#ibcon#read 4, iclass 26, count 0 2006.182.08:11:10.61#ibcon#about to read 5, iclass 26, count 0 2006.182.08:11:10.61#ibcon#read 5, iclass 26, count 0 2006.182.08:11:10.61#ibcon#about to read 6, iclass 26, count 0 2006.182.08:11:10.61#ibcon#read 6, iclass 26, count 0 2006.182.08:11:10.61#ibcon#end of sib2, iclass 26, count 0 2006.182.08:11:10.61#ibcon#*after write, iclass 26, count 0 2006.182.08:11:10.61#ibcon#*before return 0, iclass 26, count 0 2006.182.08:11:10.61#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:11:10.61#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:11:10.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:11:10.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:11:10.61$vc4f8/vblo=1,632.99 2006.182.08:11:10.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.08:11:10.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.08:11:10.61#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:10.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:11:10.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:11:10.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:11:10.61#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:11:10.61#ibcon#first serial, iclass 28, count 0 2006.182.08:11:10.61#ibcon#enter sib2, iclass 28, count 0 2006.182.08:11:10.61#ibcon#flushed, iclass 28, count 0 2006.182.08:11:10.61#ibcon#about to write, iclass 28, count 0 2006.182.08:11:10.61#ibcon#wrote, iclass 28, count 0 2006.182.08:11:10.61#ibcon#about to read 3, iclass 28, count 0 2006.182.08:11:10.64#ibcon#read 3, iclass 28, count 0 2006.182.08:11:10.64#ibcon#about to read 4, iclass 28, count 0 2006.182.08:11:10.64#ibcon#read 4, iclass 28, count 0 2006.182.08:11:10.64#ibcon#about to read 5, iclass 28, count 0 2006.182.08:11:10.64#ibcon#read 5, iclass 28, count 0 2006.182.08:11:10.64#ibcon#about to read 6, iclass 28, count 0 2006.182.08:11:10.64#ibcon#read 6, iclass 28, count 0 2006.182.08:11:10.64#ibcon#end of sib2, iclass 28, count 0 2006.182.08:11:10.64#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:11:10.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:11:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:11:10.64#ibcon#*before write, iclass 28, count 0 2006.182.08:11:10.64#ibcon#enter sib2, iclass 28, count 0 2006.182.08:11:10.64#ibcon#flushed, iclass 28, count 0 2006.182.08:11:10.64#ibcon#about to write, iclass 28, count 0 2006.182.08:11:10.64#ibcon#wrote, iclass 28, count 0 2006.182.08:11:10.64#ibcon#about to read 3, iclass 28, count 0 2006.182.08:11:10.68#ibcon#read 3, iclass 28, count 0 2006.182.08:11:10.68#ibcon#about to read 4, iclass 28, count 0 2006.182.08:11:10.68#ibcon#read 4, iclass 28, count 0 2006.182.08:11:10.68#ibcon#about to read 5, iclass 28, count 0 2006.182.08:11:10.68#ibcon#read 5, iclass 28, count 0 2006.182.08:11:10.68#ibcon#about to read 6, iclass 28, count 0 2006.182.08:11:10.68#ibcon#read 6, iclass 28, count 0 2006.182.08:11:10.68#ibcon#end of sib2, iclass 28, count 0 2006.182.08:11:10.68#ibcon#*after write, iclass 28, count 0 2006.182.08:11:10.68#ibcon#*before return 0, iclass 28, count 0 2006.182.08:11:10.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:11:10.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:11:10.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:11:10.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:11:10.68$vc4f8/vb=1,4 2006.182.08:11:10.68#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.08:11:10.68#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.08:11:10.68#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:10.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:11:10.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:11:10.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:11:10.68#ibcon#enter wrdev, iclass 30, count 2 2006.182.08:11:10.68#ibcon#first serial, iclass 30, count 2 2006.182.08:11:10.68#ibcon#enter sib2, iclass 30, count 2 2006.182.08:11:10.68#ibcon#flushed, iclass 30, count 2 2006.182.08:11:10.68#ibcon#about to write, iclass 30, count 2 2006.182.08:11:10.68#ibcon#wrote, iclass 30, count 2 2006.182.08:11:10.68#ibcon#about to read 3, iclass 30, count 2 2006.182.08:11:10.70#ibcon#read 3, iclass 30, count 2 2006.182.08:11:10.70#ibcon#about to read 4, iclass 30, count 2 2006.182.08:11:10.70#ibcon#read 4, iclass 30, count 2 2006.182.08:11:10.70#ibcon#about to read 5, iclass 30, count 2 2006.182.08:11:10.70#ibcon#read 5, iclass 30, count 2 2006.182.08:11:10.70#ibcon#about to read 6, iclass 30, count 2 2006.182.08:11:10.70#ibcon#read 6, iclass 30, count 2 2006.182.08:11:10.70#ibcon#end of sib2, iclass 30, count 2 2006.182.08:11:10.70#ibcon#*mode == 0, iclass 30, count 2 2006.182.08:11:10.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.08:11:10.70#ibcon#[27=AT01-04\r\n] 2006.182.08:11:10.70#ibcon#*before write, iclass 30, count 2 2006.182.08:11:10.70#ibcon#enter sib2, iclass 30, count 2 2006.182.08:11:10.70#ibcon#flushed, iclass 30, count 2 2006.182.08:11:10.70#ibcon#about to write, iclass 30, count 2 2006.182.08:11:10.70#ibcon#wrote, iclass 30, count 2 2006.182.08:11:10.70#ibcon#about to read 3, iclass 30, count 2 2006.182.08:11:10.73#ibcon#read 3, iclass 30, count 2 2006.182.08:11:10.73#ibcon#about to read 4, iclass 30, count 2 2006.182.08:11:10.73#ibcon#read 4, iclass 30, count 2 2006.182.08:11:10.73#ibcon#about to read 5, iclass 30, count 2 2006.182.08:11:10.73#ibcon#read 5, iclass 30, count 2 2006.182.08:11:10.73#ibcon#about to read 6, iclass 30, count 2 2006.182.08:11:10.73#ibcon#read 6, iclass 30, count 2 2006.182.08:11:10.73#ibcon#end of sib2, iclass 30, count 2 2006.182.08:11:10.73#ibcon#*after write, iclass 30, count 2 2006.182.08:11:10.73#ibcon#*before return 0, iclass 30, count 2 2006.182.08:11:10.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:11:10.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:11:10.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.08:11:10.73#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:10.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:11:10.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:11:10.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:11:10.85#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:11:10.85#ibcon#first serial, iclass 30, count 0 2006.182.08:11:10.85#ibcon#enter sib2, iclass 30, count 0 2006.182.08:11:10.85#ibcon#flushed, iclass 30, count 0 2006.182.08:11:10.85#ibcon#about to write, iclass 30, count 0 2006.182.08:11:10.85#ibcon#wrote, iclass 30, count 0 2006.182.08:11:10.85#ibcon#about to read 3, iclass 30, count 0 2006.182.08:11:10.87#ibcon#read 3, iclass 30, count 0 2006.182.08:11:10.87#ibcon#about to read 4, iclass 30, count 0 2006.182.08:11:10.87#ibcon#read 4, iclass 30, count 0 2006.182.08:11:10.87#ibcon#about to read 5, iclass 30, count 0 2006.182.08:11:10.87#ibcon#read 5, iclass 30, count 0 2006.182.08:11:10.87#ibcon#about to read 6, iclass 30, count 0 2006.182.08:11:10.87#ibcon#read 6, iclass 30, count 0 2006.182.08:11:10.87#ibcon#end of sib2, iclass 30, count 0 2006.182.08:11:10.87#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:11:10.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:11:10.87#ibcon#[27=USB\r\n] 2006.182.08:11:10.87#ibcon#*before write, iclass 30, count 0 2006.182.08:11:10.87#ibcon#enter sib2, iclass 30, count 0 2006.182.08:11:10.87#ibcon#flushed, iclass 30, count 0 2006.182.08:11:10.87#ibcon#about to write, iclass 30, count 0 2006.182.08:11:10.87#ibcon#wrote, iclass 30, count 0 2006.182.08:11:10.87#ibcon#about to read 3, iclass 30, count 0 2006.182.08:11:10.90#ibcon#read 3, iclass 30, count 0 2006.182.08:11:10.90#ibcon#about to read 4, iclass 30, count 0 2006.182.08:11:10.90#ibcon#read 4, iclass 30, count 0 2006.182.08:11:10.90#ibcon#about to read 5, iclass 30, count 0 2006.182.08:11:10.90#ibcon#read 5, iclass 30, count 0 2006.182.08:11:10.90#ibcon#about to read 6, iclass 30, count 0 2006.182.08:11:10.90#ibcon#read 6, iclass 30, count 0 2006.182.08:11:10.90#ibcon#end of sib2, iclass 30, count 0 2006.182.08:11:10.90#ibcon#*after write, iclass 30, count 0 2006.182.08:11:10.90#ibcon#*before return 0, iclass 30, count 0 2006.182.08:11:10.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:11:10.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:11:10.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:11:10.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:11:10.90$vc4f8/vblo=2,640.99 2006.182.08:11:10.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.08:11:10.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.08:11:10.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:10.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:10.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:10.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:10.90#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:11:10.90#ibcon#first serial, iclass 32, count 0 2006.182.08:11:10.90#ibcon#enter sib2, iclass 32, count 0 2006.182.08:11:10.90#ibcon#flushed, iclass 32, count 0 2006.182.08:11:10.90#ibcon#about to write, iclass 32, count 0 2006.182.08:11:10.90#ibcon#wrote, iclass 32, count 0 2006.182.08:11:10.90#ibcon#about to read 3, iclass 32, count 0 2006.182.08:11:10.92#ibcon#read 3, iclass 32, count 0 2006.182.08:11:10.92#ibcon#about to read 4, iclass 32, count 0 2006.182.08:11:10.92#ibcon#read 4, iclass 32, count 0 2006.182.08:11:10.92#ibcon#about to read 5, iclass 32, count 0 2006.182.08:11:10.92#ibcon#read 5, iclass 32, count 0 2006.182.08:11:10.92#ibcon#about to read 6, iclass 32, count 0 2006.182.08:11:10.92#ibcon#read 6, iclass 32, count 0 2006.182.08:11:10.92#ibcon#end of sib2, iclass 32, count 0 2006.182.08:11:10.92#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:11:10.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:11:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:11:10.92#ibcon#*before write, iclass 32, count 0 2006.182.08:11:10.92#ibcon#enter sib2, iclass 32, count 0 2006.182.08:11:10.92#ibcon#flushed, iclass 32, count 0 2006.182.08:11:10.92#ibcon#about to write, iclass 32, count 0 2006.182.08:11:10.92#ibcon#wrote, iclass 32, count 0 2006.182.08:11:10.92#ibcon#about to read 3, iclass 32, count 0 2006.182.08:11:10.96#ibcon#read 3, iclass 32, count 0 2006.182.08:11:10.96#ibcon#about to read 4, iclass 32, count 0 2006.182.08:11:10.96#ibcon#read 4, iclass 32, count 0 2006.182.08:11:10.96#ibcon#about to read 5, iclass 32, count 0 2006.182.08:11:10.96#ibcon#read 5, iclass 32, count 0 2006.182.08:11:10.96#ibcon#about to read 6, iclass 32, count 0 2006.182.08:11:10.96#ibcon#read 6, iclass 32, count 0 2006.182.08:11:10.96#ibcon#end of sib2, iclass 32, count 0 2006.182.08:11:10.96#ibcon#*after write, iclass 32, count 0 2006.182.08:11:10.96#ibcon#*before return 0, iclass 32, count 0 2006.182.08:11:10.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:10.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:11:10.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:11:10.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:11:10.96$vc4f8/vb=2,4 2006.182.08:11:10.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.08:11:10.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.08:11:10.96#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:10.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:11.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:11.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:11.02#ibcon#enter wrdev, iclass 34, count 2 2006.182.08:11:11.02#ibcon#first serial, iclass 34, count 2 2006.182.08:11:11.02#ibcon#enter sib2, iclass 34, count 2 2006.182.08:11:11.02#ibcon#flushed, iclass 34, count 2 2006.182.08:11:11.02#ibcon#about to write, iclass 34, count 2 2006.182.08:11:11.02#ibcon#wrote, iclass 34, count 2 2006.182.08:11:11.02#ibcon#about to read 3, iclass 34, count 2 2006.182.08:11:11.04#ibcon#read 3, iclass 34, count 2 2006.182.08:11:11.04#ibcon#about to read 4, iclass 34, count 2 2006.182.08:11:11.04#ibcon#read 4, iclass 34, count 2 2006.182.08:11:11.04#ibcon#about to read 5, iclass 34, count 2 2006.182.08:11:11.04#ibcon#read 5, iclass 34, count 2 2006.182.08:11:11.04#ibcon#about to read 6, iclass 34, count 2 2006.182.08:11:11.04#ibcon#read 6, iclass 34, count 2 2006.182.08:11:11.04#ibcon#end of sib2, iclass 34, count 2 2006.182.08:11:11.04#ibcon#*mode == 0, iclass 34, count 2 2006.182.08:11:11.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.08:11:11.04#ibcon#[27=AT02-04\r\n] 2006.182.08:11:11.04#ibcon#*before write, iclass 34, count 2 2006.182.08:11:11.04#ibcon#enter sib2, iclass 34, count 2 2006.182.08:11:11.04#ibcon#flushed, iclass 34, count 2 2006.182.08:11:11.04#ibcon#about to write, iclass 34, count 2 2006.182.08:11:11.04#ibcon#wrote, iclass 34, count 2 2006.182.08:11:11.04#ibcon#about to read 3, iclass 34, count 2 2006.182.08:11:11.07#ibcon#read 3, iclass 34, count 2 2006.182.08:11:11.07#ibcon#about to read 4, iclass 34, count 2 2006.182.08:11:11.07#ibcon#read 4, iclass 34, count 2 2006.182.08:11:11.07#ibcon#about to read 5, iclass 34, count 2 2006.182.08:11:11.07#ibcon#read 5, iclass 34, count 2 2006.182.08:11:11.07#ibcon#about to read 6, iclass 34, count 2 2006.182.08:11:11.07#ibcon#read 6, iclass 34, count 2 2006.182.08:11:11.07#ibcon#end of sib2, iclass 34, count 2 2006.182.08:11:11.07#ibcon#*after write, iclass 34, count 2 2006.182.08:11:11.07#ibcon#*before return 0, iclass 34, count 2 2006.182.08:11:11.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:11.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:11:11.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.08:11:11.07#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:11.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:11.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:11.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:11.19#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:11:11.19#ibcon#first serial, iclass 34, count 0 2006.182.08:11:11.19#ibcon#enter sib2, iclass 34, count 0 2006.182.08:11:11.19#ibcon#flushed, iclass 34, count 0 2006.182.08:11:11.19#ibcon#about to write, iclass 34, count 0 2006.182.08:11:11.19#ibcon#wrote, iclass 34, count 0 2006.182.08:11:11.19#ibcon#about to read 3, iclass 34, count 0 2006.182.08:11:11.21#ibcon#read 3, iclass 34, count 0 2006.182.08:11:11.21#ibcon#about to read 4, iclass 34, count 0 2006.182.08:11:11.21#ibcon#read 4, iclass 34, count 0 2006.182.08:11:11.21#ibcon#about to read 5, iclass 34, count 0 2006.182.08:11:11.21#ibcon#read 5, iclass 34, count 0 2006.182.08:11:11.21#ibcon#about to read 6, iclass 34, count 0 2006.182.08:11:11.21#ibcon#read 6, iclass 34, count 0 2006.182.08:11:11.21#ibcon#end of sib2, iclass 34, count 0 2006.182.08:11:11.21#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:11:11.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:11:11.21#ibcon#[27=USB\r\n] 2006.182.08:11:11.21#ibcon#*before write, iclass 34, count 0 2006.182.08:11:11.21#ibcon#enter sib2, iclass 34, count 0 2006.182.08:11:11.21#ibcon#flushed, iclass 34, count 0 2006.182.08:11:11.21#ibcon#about to write, iclass 34, count 0 2006.182.08:11:11.21#ibcon#wrote, iclass 34, count 0 2006.182.08:11:11.21#ibcon#about to read 3, iclass 34, count 0 2006.182.08:11:11.24#ibcon#read 3, iclass 34, count 0 2006.182.08:11:11.24#ibcon#about to read 4, iclass 34, count 0 2006.182.08:11:11.24#ibcon#read 4, iclass 34, count 0 2006.182.08:11:11.24#ibcon#about to read 5, iclass 34, count 0 2006.182.08:11:11.24#ibcon#read 5, iclass 34, count 0 2006.182.08:11:11.24#ibcon#about to read 6, iclass 34, count 0 2006.182.08:11:11.24#ibcon#read 6, iclass 34, count 0 2006.182.08:11:11.24#ibcon#end of sib2, iclass 34, count 0 2006.182.08:11:11.24#ibcon#*after write, iclass 34, count 0 2006.182.08:11:11.24#ibcon#*before return 0, iclass 34, count 0 2006.182.08:11:11.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:11.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:11:11.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:11:11.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:11:11.24$vc4f8/vblo=3,656.99 2006.182.08:11:11.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.08:11:11.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.08:11:11.24#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:11.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:11.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:11.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:11.24#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:11:11.24#ibcon#first serial, iclass 36, count 0 2006.182.08:11:11.24#ibcon#enter sib2, iclass 36, count 0 2006.182.08:11:11.24#ibcon#flushed, iclass 36, count 0 2006.182.08:11:11.24#ibcon#about to write, iclass 36, count 0 2006.182.08:11:11.24#ibcon#wrote, iclass 36, count 0 2006.182.08:11:11.24#ibcon#about to read 3, iclass 36, count 0 2006.182.08:11:11.26#ibcon#read 3, iclass 36, count 0 2006.182.08:11:11.26#ibcon#about to read 4, iclass 36, count 0 2006.182.08:11:11.26#ibcon#read 4, iclass 36, count 0 2006.182.08:11:11.26#ibcon#about to read 5, iclass 36, count 0 2006.182.08:11:11.26#ibcon#read 5, iclass 36, count 0 2006.182.08:11:11.26#ibcon#about to read 6, iclass 36, count 0 2006.182.08:11:11.26#ibcon#read 6, iclass 36, count 0 2006.182.08:11:11.26#ibcon#end of sib2, iclass 36, count 0 2006.182.08:11:11.26#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:11:11.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:11:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:11:11.26#ibcon#*before write, iclass 36, count 0 2006.182.08:11:11.26#ibcon#enter sib2, iclass 36, count 0 2006.182.08:11:11.26#ibcon#flushed, iclass 36, count 0 2006.182.08:11:11.26#ibcon#about to write, iclass 36, count 0 2006.182.08:11:11.26#ibcon#wrote, iclass 36, count 0 2006.182.08:11:11.26#ibcon#about to read 3, iclass 36, count 0 2006.182.08:11:11.30#ibcon#read 3, iclass 36, count 0 2006.182.08:11:11.30#ibcon#about to read 4, iclass 36, count 0 2006.182.08:11:11.30#ibcon#read 4, iclass 36, count 0 2006.182.08:11:11.30#ibcon#about to read 5, iclass 36, count 0 2006.182.08:11:11.30#ibcon#read 5, iclass 36, count 0 2006.182.08:11:11.30#ibcon#about to read 6, iclass 36, count 0 2006.182.08:11:11.30#ibcon#read 6, iclass 36, count 0 2006.182.08:11:11.30#ibcon#end of sib2, iclass 36, count 0 2006.182.08:11:11.30#ibcon#*after write, iclass 36, count 0 2006.182.08:11:11.30#ibcon#*before return 0, iclass 36, count 0 2006.182.08:11:11.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:11.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:11:11.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:11:11.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:11:11.30$vc4f8/vb=3,4 2006.182.08:11:11.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.08:11:11.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.08:11:11.30#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:11.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:11.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:11.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:11.36#ibcon#enter wrdev, iclass 38, count 2 2006.182.08:11:11.36#ibcon#first serial, iclass 38, count 2 2006.182.08:11:11.36#ibcon#enter sib2, iclass 38, count 2 2006.182.08:11:11.36#ibcon#flushed, iclass 38, count 2 2006.182.08:11:11.36#ibcon#about to write, iclass 38, count 2 2006.182.08:11:11.36#ibcon#wrote, iclass 38, count 2 2006.182.08:11:11.36#ibcon#about to read 3, iclass 38, count 2 2006.182.08:11:11.38#ibcon#read 3, iclass 38, count 2 2006.182.08:11:11.38#ibcon#about to read 4, iclass 38, count 2 2006.182.08:11:11.38#ibcon#read 4, iclass 38, count 2 2006.182.08:11:11.38#ibcon#about to read 5, iclass 38, count 2 2006.182.08:11:11.38#ibcon#read 5, iclass 38, count 2 2006.182.08:11:11.38#ibcon#about to read 6, iclass 38, count 2 2006.182.08:11:11.38#ibcon#read 6, iclass 38, count 2 2006.182.08:11:11.38#ibcon#end of sib2, iclass 38, count 2 2006.182.08:11:11.38#ibcon#*mode == 0, iclass 38, count 2 2006.182.08:11:11.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.08:11:11.38#ibcon#[27=AT03-04\r\n] 2006.182.08:11:11.38#ibcon#*before write, iclass 38, count 2 2006.182.08:11:11.38#ibcon#enter sib2, iclass 38, count 2 2006.182.08:11:11.38#ibcon#flushed, iclass 38, count 2 2006.182.08:11:11.38#ibcon#about to write, iclass 38, count 2 2006.182.08:11:11.38#ibcon#wrote, iclass 38, count 2 2006.182.08:11:11.38#ibcon#about to read 3, iclass 38, count 2 2006.182.08:11:11.41#ibcon#read 3, iclass 38, count 2 2006.182.08:11:11.41#ibcon#about to read 4, iclass 38, count 2 2006.182.08:11:11.41#ibcon#read 4, iclass 38, count 2 2006.182.08:11:11.41#ibcon#about to read 5, iclass 38, count 2 2006.182.08:11:11.41#ibcon#read 5, iclass 38, count 2 2006.182.08:11:11.41#ibcon#about to read 6, iclass 38, count 2 2006.182.08:11:11.41#ibcon#read 6, iclass 38, count 2 2006.182.08:11:11.41#ibcon#end of sib2, iclass 38, count 2 2006.182.08:11:11.41#ibcon#*after write, iclass 38, count 2 2006.182.08:11:11.41#ibcon#*before return 0, iclass 38, count 2 2006.182.08:11:11.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:11.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:11:11.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.08:11:11.41#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:11.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:11.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:11.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:11.53#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:11:11.53#ibcon#first serial, iclass 38, count 0 2006.182.08:11:11.53#ibcon#enter sib2, iclass 38, count 0 2006.182.08:11:11.53#ibcon#flushed, iclass 38, count 0 2006.182.08:11:11.53#ibcon#about to write, iclass 38, count 0 2006.182.08:11:11.53#ibcon#wrote, iclass 38, count 0 2006.182.08:11:11.53#ibcon#about to read 3, iclass 38, count 0 2006.182.08:11:11.55#ibcon#read 3, iclass 38, count 0 2006.182.08:11:11.55#ibcon#about to read 4, iclass 38, count 0 2006.182.08:11:11.55#ibcon#read 4, iclass 38, count 0 2006.182.08:11:11.55#ibcon#about to read 5, iclass 38, count 0 2006.182.08:11:11.55#ibcon#read 5, iclass 38, count 0 2006.182.08:11:11.55#ibcon#about to read 6, iclass 38, count 0 2006.182.08:11:11.55#ibcon#read 6, iclass 38, count 0 2006.182.08:11:11.55#ibcon#end of sib2, iclass 38, count 0 2006.182.08:11:11.55#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:11:11.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:11:11.55#ibcon#[27=USB\r\n] 2006.182.08:11:11.55#ibcon#*before write, iclass 38, count 0 2006.182.08:11:11.55#ibcon#enter sib2, iclass 38, count 0 2006.182.08:11:11.55#ibcon#flushed, iclass 38, count 0 2006.182.08:11:11.55#ibcon#about to write, iclass 38, count 0 2006.182.08:11:11.55#ibcon#wrote, iclass 38, count 0 2006.182.08:11:11.55#ibcon#about to read 3, iclass 38, count 0 2006.182.08:11:11.58#ibcon#read 3, iclass 38, count 0 2006.182.08:11:11.58#ibcon#about to read 4, iclass 38, count 0 2006.182.08:11:11.58#ibcon#read 4, iclass 38, count 0 2006.182.08:11:11.58#ibcon#about to read 5, iclass 38, count 0 2006.182.08:11:11.58#ibcon#read 5, iclass 38, count 0 2006.182.08:11:11.58#ibcon#about to read 6, iclass 38, count 0 2006.182.08:11:11.58#ibcon#read 6, iclass 38, count 0 2006.182.08:11:11.58#ibcon#end of sib2, iclass 38, count 0 2006.182.08:11:11.58#ibcon#*after write, iclass 38, count 0 2006.182.08:11:11.58#ibcon#*before return 0, iclass 38, count 0 2006.182.08:11:11.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:11.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:11:11.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:11:11.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:11:11.58$vc4f8/vblo=4,712.99 2006.182.08:11:11.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.08:11:11.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.08:11:11.58#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:11.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:11.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:11.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:11.58#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:11:11.58#ibcon#first serial, iclass 40, count 0 2006.182.08:11:11.58#ibcon#enter sib2, iclass 40, count 0 2006.182.08:11:11.58#ibcon#flushed, iclass 40, count 0 2006.182.08:11:11.58#ibcon#about to write, iclass 40, count 0 2006.182.08:11:11.58#ibcon#wrote, iclass 40, count 0 2006.182.08:11:11.58#ibcon#about to read 3, iclass 40, count 0 2006.182.08:11:11.60#ibcon#read 3, iclass 40, count 0 2006.182.08:11:11.60#ibcon#about to read 4, iclass 40, count 0 2006.182.08:11:11.60#ibcon#read 4, iclass 40, count 0 2006.182.08:11:11.60#ibcon#about to read 5, iclass 40, count 0 2006.182.08:11:11.60#ibcon#read 5, iclass 40, count 0 2006.182.08:11:11.60#ibcon#about to read 6, iclass 40, count 0 2006.182.08:11:11.60#ibcon#read 6, iclass 40, count 0 2006.182.08:11:11.60#ibcon#end of sib2, iclass 40, count 0 2006.182.08:11:11.60#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:11:11.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:11:11.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:11:11.60#ibcon#*before write, iclass 40, count 0 2006.182.08:11:11.60#ibcon#enter sib2, iclass 40, count 0 2006.182.08:11:11.60#ibcon#flushed, iclass 40, count 0 2006.182.08:11:11.60#ibcon#about to write, iclass 40, count 0 2006.182.08:11:11.60#ibcon#wrote, iclass 40, count 0 2006.182.08:11:11.60#ibcon#about to read 3, iclass 40, count 0 2006.182.08:11:11.64#ibcon#read 3, iclass 40, count 0 2006.182.08:11:11.64#ibcon#about to read 4, iclass 40, count 0 2006.182.08:11:11.64#ibcon#read 4, iclass 40, count 0 2006.182.08:11:11.64#ibcon#about to read 5, iclass 40, count 0 2006.182.08:11:11.64#ibcon#read 5, iclass 40, count 0 2006.182.08:11:11.64#ibcon#about to read 6, iclass 40, count 0 2006.182.08:11:11.64#ibcon#read 6, iclass 40, count 0 2006.182.08:11:11.64#ibcon#end of sib2, iclass 40, count 0 2006.182.08:11:11.64#ibcon#*after write, iclass 40, count 0 2006.182.08:11:11.64#ibcon#*before return 0, iclass 40, count 0 2006.182.08:11:11.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:11.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:11:11.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:11:11.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:11:11.64$vc4f8/vb=4,4 2006.182.08:11:11.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.08:11:11.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.08:11:11.64#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:11.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:11.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:11.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:11.70#ibcon#enter wrdev, iclass 4, count 2 2006.182.08:11:11.70#ibcon#first serial, iclass 4, count 2 2006.182.08:11:11.70#ibcon#enter sib2, iclass 4, count 2 2006.182.08:11:11.70#ibcon#flushed, iclass 4, count 2 2006.182.08:11:11.70#ibcon#about to write, iclass 4, count 2 2006.182.08:11:11.70#ibcon#wrote, iclass 4, count 2 2006.182.08:11:11.70#ibcon#about to read 3, iclass 4, count 2 2006.182.08:11:11.72#ibcon#read 3, iclass 4, count 2 2006.182.08:11:11.72#ibcon#about to read 4, iclass 4, count 2 2006.182.08:11:11.72#ibcon#read 4, iclass 4, count 2 2006.182.08:11:11.72#ibcon#about to read 5, iclass 4, count 2 2006.182.08:11:11.72#ibcon#read 5, iclass 4, count 2 2006.182.08:11:11.72#ibcon#about to read 6, iclass 4, count 2 2006.182.08:11:11.72#ibcon#read 6, iclass 4, count 2 2006.182.08:11:11.72#ibcon#end of sib2, iclass 4, count 2 2006.182.08:11:11.72#ibcon#*mode == 0, iclass 4, count 2 2006.182.08:11:11.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.08:11:11.72#ibcon#[27=AT04-04\r\n] 2006.182.08:11:11.72#ibcon#*before write, iclass 4, count 2 2006.182.08:11:11.72#ibcon#enter sib2, iclass 4, count 2 2006.182.08:11:11.72#ibcon#flushed, iclass 4, count 2 2006.182.08:11:11.72#ibcon#about to write, iclass 4, count 2 2006.182.08:11:11.72#ibcon#wrote, iclass 4, count 2 2006.182.08:11:11.72#ibcon#about to read 3, iclass 4, count 2 2006.182.08:11:11.75#ibcon#read 3, iclass 4, count 2 2006.182.08:11:11.75#ibcon#about to read 4, iclass 4, count 2 2006.182.08:11:11.75#ibcon#read 4, iclass 4, count 2 2006.182.08:11:11.75#ibcon#about to read 5, iclass 4, count 2 2006.182.08:11:11.75#ibcon#read 5, iclass 4, count 2 2006.182.08:11:11.75#ibcon#about to read 6, iclass 4, count 2 2006.182.08:11:11.75#ibcon#read 6, iclass 4, count 2 2006.182.08:11:11.75#ibcon#end of sib2, iclass 4, count 2 2006.182.08:11:11.75#ibcon#*after write, iclass 4, count 2 2006.182.08:11:11.75#ibcon#*before return 0, iclass 4, count 2 2006.182.08:11:11.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:11.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:11:11.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.08:11:11.75#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:11.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:11.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:11.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:11.87#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:11:11.87#ibcon#first serial, iclass 4, count 0 2006.182.08:11:11.87#ibcon#enter sib2, iclass 4, count 0 2006.182.08:11:11.87#ibcon#flushed, iclass 4, count 0 2006.182.08:11:11.87#ibcon#about to write, iclass 4, count 0 2006.182.08:11:11.87#ibcon#wrote, iclass 4, count 0 2006.182.08:11:11.87#ibcon#about to read 3, iclass 4, count 0 2006.182.08:11:11.89#ibcon#read 3, iclass 4, count 0 2006.182.08:11:11.89#ibcon#about to read 4, iclass 4, count 0 2006.182.08:11:11.89#ibcon#read 4, iclass 4, count 0 2006.182.08:11:11.89#ibcon#about to read 5, iclass 4, count 0 2006.182.08:11:11.89#ibcon#read 5, iclass 4, count 0 2006.182.08:11:11.89#ibcon#about to read 6, iclass 4, count 0 2006.182.08:11:11.89#ibcon#read 6, iclass 4, count 0 2006.182.08:11:11.89#ibcon#end of sib2, iclass 4, count 0 2006.182.08:11:11.89#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:11:11.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:11:11.89#ibcon#[27=USB\r\n] 2006.182.08:11:11.89#ibcon#*before write, iclass 4, count 0 2006.182.08:11:11.89#ibcon#enter sib2, iclass 4, count 0 2006.182.08:11:11.89#ibcon#flushed, iclass 4, count 0 2006.182.08:11:11.89#ibcon#about to write, iclass 4, count 0 2006.182.08:11:11.89#ibcon#wrote, iclass 4, count 0 2006.182.08:11:11.89#ibcon#about to read 3, iclass 4, count 0 2006.182.08:11:11.92#ibcon#read 3, iclass 4, count 0 2006.182.08:11:11.92#ibcon#about to read 4, iclass 4, count 0 2006.182.08:11:11.92#ibcon#read 4, iclass 4, count 0 2006.182.08:11:11.92#ibcon#about to read 5, iclass 4, count 0 2006.182.08:11:11.92#ibcon#read 5, iclass 4, count 0 2006.182.08:11:11.92#ibcon#about to read 6, iclass 4, count 0 2006.182.08:11:11.92#ibcon#read 6, iclass 4, count 0 2006.182.08:11:11.92#ibcon#end of sib2, iclass 4, count 0 2006.182.08:11:11.92#ibcon#*after write, iclass 4, count 0 2006.182.08:11:11.92#ibcon#*before return 0, iclass 4, count 0 2006.182.08:11:11.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:11.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:11:11.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:11:11.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:11:11.92$vc4f8/vblo=5,744.99 2006.182.08:11:11.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.08:11:11.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.08:11:11.92#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:11.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:11.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:11.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:11.92#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:11:11.92#ibcon#first serial, iclass 6, count 0 2006.182.08:11:11.92#ibcon#enter sib2, iclass 6, count 0 2006.182.08:11:11.92#ibcon#flushed, iclass 6, count 0 2006.182.08:11:11.92#ibcon#about to write, iclass 6, count 0 2006.182.08:11:11.92#ibcon#wrote, iclass 6, count 0 2006.182.08:11:11.92#ibcon#about to read 3, iclass 6, count 0 2006.182.08:11:11.94#ibcon#read 3, iclass 6, count 0 2006.182.08:11:11.94#ibcon#about to read 4, iclass 6, count 0 2006.182.08:11:11.94#ibcon#read 4, iclass 6, count 0 2006.182.08:11:11.94#ibcon#about to read 5, iclass 6, count 0 2006.182.08:11:11.94#ibcon#read 5, iclass 6, count 0 2006.182.08:11:11.94#ibcon#about to read 6, iclass 6, count 0 2006.182.08:11:11.94#ibcon#read 6, iclass 6, count 0 2006.182.08:11:11.94#ibcon#end of sib2, iclass 6, count 0 2006.182.08:11:11.94#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:11:11.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:11:11.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:11:11.94#ibcon#*before write, iclass 6, count 0 2006.182.08:11:11.94#ibcon#enter sib2, iclass 6, count 0 2006.182.08:11:11.94#ibcon#flushed, iclass 6, count 0 2006.182.08:11:11.94#ibcon#about to write, iclass 6, count 0 2006.182.08:11:11.94#ibcon#wrote, iclass 6, count 0 2006.182.08:11:11.94#ibcon#about to read 3, iclass 6, count 0 2006.182.08:11:11.98#ibcon#read 3, iclass 6, count 0 2006.182.08:11:11.98#ibcon#about to read 4, iclass 6, count 0 2006.182.08:11:11.98#ibcon#read 4, iclass 6, count 0 2006.182.08:11:11.98#ibcon#about to read 5, iclass 6, count 0 2006.182.08:11:11.98#ibcon#read 5, iclass 6, count 0 2006.182.08:11:11.98#ibcon#about to read 6, iclass 6, count 0 2006.182.08:11:11.98#ibcon#read 6, iclass 6, count 0 2006.182.08:11:11.98#ibcon#end of sib2, iclass 6, count 0 2006.182.08:11:11.98#ibcon#*after write, iclass 6, count 0 2006.182.08:11:11.98#ibcon#*before return 0, iclass 6, count 0 2006.182.08:11:11.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:11.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:11:11.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:11:11.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:11:11.98$vc4f8/vb=5,4 2006.182.08:11:11.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.08:11:11.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.08:11:11.98#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:11.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:12.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:12.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:12.04#ibcon#enter wrdev, iclass 10, count 2 2006.182.08:11:12.04#ibcon#first serial, iclass 10, count 2 2006.182.08:11:12.04#ibcon#enter sib2, iclass 10, count 2 2006.182.08:11:12.04#ibcon#flushed, iclass 10, count 2 2006.182.08:11:12.04#ibcon#about to write, iclass 10, count 2 2006.182.08:11:12.04#ibcon#wrote, iclass 10, count 2 2006.182.08:11:12.04#ibcon#about to read 3, iclass 10, count 2 2006.182.08:11:12.06#ibcon#read 3, iclass 10, count 2 2006.182.08:11:12.06#ibcon#about to read 4, iclass 10, count 2 2006.182.08:11:12.06#ibcon#read 4, iclass 10, count 2 2006.182.08:11:12.06#ibcon#about to read 5, iclass 10, count 2 2006.182.08:11:12.06#ibcon#read 5, iclass 10, count 2 2006.182.08:11:12.06#ibcon#about to read 6, iclass 10, count 2 2006.182.08:11:12.06#ibcon#read 6, iclass 10, count 2 2006.182.08:11:12.06#ibcon#end of sib2, iclass 10, count 2 2006.182.08:11:12.06#ibcon#*mode == 0, iclass 10, count 2 2006.182.08:11:12.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.08:11:12.06#ibcon#[27=AT05-04\r\n] 2006.182.08:11:12.06#ibcon#*before write, iclass 10, count 2 2006.182.08:11:12.06#ibcon#enter sib2, iclass 10, count 2 2006.182.08:11:12.06#ibcon#flushed, iclass 10, count 2 2006.182.08:11:12.06#ibcon#about to write, iclass 10, count 2 2006.182.08:11:12.06#ibcon#wrote, iclass 10, count 2 2006.182.08:11:12.06#ibcon#about to read 3, iclass 10, count 2 2006.182.08:11:12.09#ibcon#read 3, iclass 10, count 2 2006.182.08:11:12.09#ibcon#about to read 4, iclass 10, count 2 2006.182.08:11:12.09#ibcon#read 4, iclass 10, count 2 2006.182.08:11:12.09#ibcon#about to read 5, iclass 10, count 2 2006.182.08:11:12.09#ibcon#read 5, iclass 10, count 2 2006.182.08:11:12.09#ibcon#about to read 6, iclass 10, count 2 2006.182.08:11:12.09#ibcon#read 6, iclass 10, count 2 2006.182.08:11:12.09#ibcon#end of sib2, iclass 10, count 2 2006.182.08:11:12.09#ibcon#*after write, iclass 10, count 2 2006.182.08:11:12.09#ibcon#*before return 0, iclass 10, count 2 2006.182.08:11:12.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:12.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:11:12.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.08:11:12.09#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:12.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:12.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:12.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:12.21#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:11:12.21#ibcon#first serial, iclass 10, count 0 2006.182.08:11:12.21#ibcon#enter sib2, iclass 10, count 0 2006.182.08:11:12.21#ibcon#flushed, iclass 10, count 0 2006.182.08:11:12.21#ibcon#about to write, iclass 10, count 0 2006.182.08:11:12.21#ibcon#wrote, iclass 10, count 0 2006.182.08:11:12.21#ibcon#about to read 3, iclass 10, count 0 2006.182.08:11:12.25#ibcon#read 3, iclass 10, count 0 2006.182.08:11:12.25#ibcon#about to read 4, iclass 10, count 0 2006.182.08:11:12.25#ibcon#read 4, iclass 10, count 0 2006.182.08:11:12.25#ibcon#about to read 5, iclass 10, count 0 2006.182.08:11:12.25#ibcon#read 5, iclass 10, count 0 2006.182.08:11:12.25#ibcon#about to read 6, iclass 10, count 0 2006.182.08:11:12.25#ibcon#read 6, iclass 10, count 0 2006.182.08:11:12.25#ibcon#end of sib2, iclass 10, count 0 2006.182.08:11:12.25#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:11:12.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:11:12.25#ibcon#[27=USB\r\n] 2006.182.08:11:12.25#ibcon#*before write, iclass 10, count 0 2006.182.08:11:12.25#ibcon#enter sib2, iclass 10, count 0 2006.182.08:11:12.25#ibcon#flushed, iclass 10, count 0 2006.182.08:11:12.25#ibcon#about to write, iclass 10, count 0 2006.182.08:11:12.25#ibcon#wrote, iclass 10, count 0 2006.182.08:11:12.25#ibcon#about to read 3, iclass 10, count 0 2006.182.08:11:12.27#ibcon#read 3, iclass 10, count 0 2006.182.08:11:12.27#ibcon#about to read 4, iclass 10, count 0 2006.182.08:11:12.27#ibcon#read 4, iclass 10, count 0 2006.182.08:11:12.27#ibcon#about to read 5, iclass 10, count 0 2006.182.08:11:12.27#ibcon#read 5, iclass 10, count 0 2006.182.08:11:12.27#ibcon#about to read 6, iclass 10, count 0 2006.182.08:11:12.27#ibcon#read 6, iclass 10, count 0 2006.182.08:11:12.27#ibcon#end of sib2, iclass 10, count 0 2006.182.08:11:12.27#ibcon#*after write, iclass 10, count 0 2006.182.08:11:12.27#ibcon#*before return 0, iclass 10, count 0 2006.182.08:11:12.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:12.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:11:12.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:11:12.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:11:12.27$vc4f8/vblo=6,752.99 2006.182.08:11:12.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.08:11:12.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.08:11:12.27#ibcon#ireg 17 cls_cnt 0 2006.182.08:11:12.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:12.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:12.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:12.27#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:11:12.27#ibcon#first serial, iclass 12, count 0 2006.182.08:11:12.27#ibcon#enter sib2, iclass 12, count 0 2006.182.08:11:12.27#ibcon#flushed, iclass 12, count 0 2006.182.08:11:12.27#ibcon#about to write, iclass 12, count 0 2006.182.08:11:12.27#ibcon#wrote, iclass 12, count 0 2006.182.08:11:12.27#ibcon#about to read 3, iclass 12, count 0 2006.182.08:11:12.29#ibcon#read 3, iclass 12, count 0 2006.182.08:11:12.29#ibcon#about to read 4, iclass 12, count 0 2006.182.08:11:12.29#ibcon#read 4, iclass 12, count 0 2006.182.08:11:12.29#ibcon#about to read 5, iclass 12, count 0 2006.182.08:11:12.29#ibcon#read 5, iclass 12, count 0 2006.182.08:11:12.29#ibcon#about to read 6, iclass 12, count 0 2006.182.08:11:12.29#ibcon#read 6, iclass 12, count 0 2006.182.08:11:12.29#ibcon#end of sib2, iclass 12, count 0 2006.182.08:11:12.29#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:11:12.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:11:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:11:12.29#ibcon#*before write, iclass 12, count 0 2006.182.08:11:12.29#ibcon#enter sib2, iclass 12, count 0 2006.182.08:11:12.29#ibcon#flushed, iclass 12, count 0 2006.182.08:11:12.29#ibcon#about to write, iclass 12, count 0 2006.182.08:11:12.29#ibcon#wrote, iclass 12, count 0 2006.182.08:11:12.29#ibcon#about to read 3, iclass 12, count 0 2006.182.08:11:12.33#ibcon#read 3, iclass 12, count 0 2006.182.08:11:12.33#ibcon#about to read 4, iclass 12, count 0 2006.182.08:11:12.33#ibcon#read 4, iclass 12, count 0 2006.182.08:11:12.33#ibcon#about to read 5, iclass 12, count 0 2006.182.08:11:12.33#ibcon#read 5, iclass 12, count 0 2006.182.08:11:12.33#ibcon#about to read 6, iclass 12, count 0 2006.182.08:11:12.33#ibcon#read 6, iclass 12, count 0 2006.182.08:11:12.33#ibcon#end of sib2, iclass 12, count 0 2006.182.08:11:12.33#ibcon#*after write, iclass 12, count 0 2006.182.08:11:12.33#ibcon#*before return 0, iclass 12, count 0 2006.182.08:11:12.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:12.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:11:12.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:11:12.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:11:12.33$vc4f8/vb=6,4 2006.182.08:11:12.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.08:11:12.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.08:11:12.33#ibcon#ireg 11 cls_cnt 2 2006.182.08:11:12.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:12.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:12.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:12.39#ibcon#enter wrdev, iclass 14, count 2 2006.182.08:11:12.39#ibcon#first serial, iclass 14, count 2 2006.182.08:11:12.39#ibcon#enter sib2, iclass 14, count 2 2006.182.08:11:12.39#ibcon#flushed, iclass 14, count 2 2006.182.08:11:12.39#ibcon#about to write, iclass 14, count 2 2006.182.08:11:12.39#ibcon#wrote, iclass 14, count 2 2006.182.08:11:12.39#ibcon#about to read 3, iclass 14, count 2 2006.182.08:11:12.41#ibcon#read 3, iclass 14, count 2 2006.182.08:11:12.41#ibcon#about to read 4, iclass 14, count 2 2006.182.08:11:12.41#ibcon#read 4, iclass 14, count 2 2006.182.08:11:12.41#ibcon#about to read 5, iclass 14, count 2 2006.182.08:11:12.41#ibcon#read 5, iclass 14, count 2 2006.182.08:11:12.41#ibcon#about to read 6, iclass 14, count 2 2006.182.08:11:12.41#ibcon#read 6, iclass 14, count 2 2006.182.08:11:12.41#ibcon#end of sib2, iclass 14, count 2 2006.182.08:11:12.41#ibcon#*mode == 0, iclass 14, count 2 2006.182.08:11:12.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.08:11:12.41#ibcon#[27=AT06-04\r\n] 2006.182.08:11:12.41#ibcon#*before write, iclass 14, count 2 2006.182.08:11:12.41#ibcon#enter sib2, iclass 14, count 2 2006.182.08:11:12.41#ibcon#flushed, iclass 14, count 2 2006.182.08:11:12.41#ibcon#about to write, iclass 14, count 2 2006.182.08:11:12.41#ibcon#wrote, iclass 14, count 2 2006.182.08:11:12.41#ibcon#about to read 3, iclass 14, count 2 2006.182.08:11:12.44#ibcon#read 3, iclass 14, count 2 2006.182.08:11:12.44#ibcon#about to read 4, iclass 14, count 2 2006.182.08:11:12.44#ibcon#read 4, iclass 14, count 2 2006.182.08:11:12.44#ibcon#about to read 5, iclass 14, count 2 2006.182.08:11:12.44#ibcon#read 5, iclass 14, count 2 2006.182.08:11:12.44#ibcon#about to read 6, iclass 14, count 2 2006.182.08:11:12.44#ibcon#read 6, iclass 14, count 2 2006.182.08:11:12.44#ibcon#end of sib2, iclass 14, count 2 2006.182.08:11:12.44#ibcon#*after write, iclass 14, count 2 2006.182.08:11:12.44#ibcon#*before return 0, iclass 14, count 2 2006.182.08:11:12.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:12.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:11:12.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.08:11:12.44#ibcon#ireg 7 cls_cnt 0 2006.182.08:11:12.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:12.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:12.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:12.56#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:11:12.56#ibcon#first serial, iclass 14, count 0 2006.182.08:11:12.56#ibcon#enter sib2, iclass 14, count 0 2006.182.08:11:12.56#ibcon#flushed, iclass 14, count 0 2006.182.08:11:12.56#ibcon#about to write, iclass 14, count 0 2006.182.08:11:12.56#ibcon#wrote, iclass 14, count 0 2006.182.08:11:12.56#ibcon#about to read 3, iclass 14, count 0 2006.182.08:11:12.58#ibcon#read 3, iclass 14, count 0 2006.182.08:11:12.58#ibcon#about to read 4, iclass 14, count 0 2006.182.08:11:12.58#ibcon#read 4, iclass 14, count 0 2006.182.08:11:12.58#ibcon#about to read 5, iclass 14, count 0 2006.182.08:11:12.58#ibcon#read 5, iclass 14, count 0 2006.182.08:11:12.58#ibcon#about to read 6, iclass 14, count 0 2006.182.08:11:12.58#ibcon#read 6, iclass 14, count 0 2006.182.08:11:12.58#ibcon#end of sib2, iclass 14, count 0 2006.182.08:11:12.58#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:11:12.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:11:12.58#ibcon#[27=USB\r\n] 2006.182.08:11:12.58#ibcon#*before write, iclass 14, count 0 2006.182.08:11:12.58#ibcon#enter sib2, iclass 14, count 0 2006.182.08:11:12.58#ibcon#flushed, iclass 14, count 0 2006.182.08:11:12.58#ibcon#about to write, iclass 14, count 0 2006.182.08:11:12.58#ibcon#wrote, iclass 14, count 0 2006.182.08:11:12.58#ibcon#about to read 3, iclass 14, count 0 2006.182.08:11:12.61#ibcon#read 3, iclass 14, count 0 2006.182.08:11:12.61#ibcon#about to read 4, iclass 14, count 0 2006.182.08:11:12.61#ibcon#read 4, iclass 14, count 0 2006.182.08:11:12.61#ibcon#about to read 5, iclass 14, count 0 2006.182.08:11:12.61#ibcon#read 5, iclass 14, count 0 2006.182.08:11:12.61#ibcon#about to read 6, iclass 14, count 0 2006.182.08:11:12.61#ibcon#read 6, iclass 14, count 0 2006.182.08:11:12.61#ibcon#end of sib2, iclass 14, count 0 2006.182.08:11:12.61#ibcon#*after write, iclass 14, count 0 2006.182.08:11:12.61#ibcon#*before return 0, iclass 14, count 0 2006.182.08:11:12.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:12.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:11:12.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:11:12.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:11:12.61$vc4f8/vabw=wide 2006.182.08:11:12.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.08:11:12.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.08:11:12.61#ibcon#ireg 8 cls_cnt 0 2006.182.08:11:12.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:12.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:12.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:12.61#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:11:12.61#ibcon#first serial, iclass 16, count 0 2006.182.08:11:12.61#ibcon#enter sib2, iclass 16, count 0 2006.182.08:11:12.61#ibcon#flushed, iclass 16, count 0 2006.182.08:11:12.61#ibcon#about to write, iclass 16, count 0 2006.182.08:11:12.61#ibcon#wrote, iclass 16, count 0 2006.182.08:11:12.61#ibcon#about to read 3, iclass 16, count 0 2006.182.08:11:12.63#ibcon#read 3, iclass 16, count 0 2006.182.08:11:12.63#ibcon#about to read 4, iclass 16, count 0 2006.182.08:11:12.63#ibcon#read 4, iclass 16, count 0 2006.182.08:11:12.63#ibcon#about to read 5, iclass 16, count 0 2006.182.08:11:12.63#ibcon#read 5, iclass 16, count 0 2006.182.08:11:12.63#ibcon#about to read 6, iclass 16, count 0 2006.182.08:11:12.63#ibcon#read 6, iclass 16, count 0 2006.182.08:11:12.63#ibcon#end of sib2, iclass 16, count 0 2006.182.08:11:12.63#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:11:12.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:11:12.63#ibcon#[25=BW32\r\n] 2006.182.08:11:12.63#ibcon#*before write, iclass 16, count 0 2006.182.08:11:12.63#ibcon#enter sib2, iclass 16, count 0 2006.182.08:11:12.63#ibcon#flushed, iclass 16, count 0 2006.182.08:11:12.63#ibcon#about to write, iclass 16, count 0 2006.182.08:11:12.63#ibcon#wrote, iclass 16, count 0 2006.182.08:11:12.63#ibcon#about to read 3, iclass 16, count 0 2006.182.08:11:12.66#ibcon#read 3, iclass 16, count 0 2006.182.08:11:12.66#ibcon#about to read 4, iclass 16, count 0 2006.182.08:11:12.66#ibcon#read 4, iclass 16, count 0 2006.182.08:11:12.66#ibcon#about to read 5, iclass 16, count 0 2006.182.08:11:12.66#ibcon#read 5, iclass 16, count 0 2006.182.08:11:12.66#ibcon#about to read 6, iclass 16, count 0 2006.182.08:11:12.66#ibcon#read 6, iclass 16, count 0 2006.182.08:11:12.66#ibcon#end of sib2, iclass 16, count 0 2006.182.08:11:12.66#ibcon#*after write, iclass 16, count 0 2006.182.08:11:12.66#ibcon#*before return 0, iclass 16, count 0 2006.182.08:11:12.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:12.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:11:12.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:11:12.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:11:12.66$vc4f8/vbbw=wide 2006.182.08:11:12.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.08:11:12.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.08:11:12.66#ibcon#ireg 8 cls_cnt 0 2006.182.08:11:12.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:11:12.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:11:12.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:11:12.73#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:11:12.73#ibcon#first serial, iclass 18, count 0 2006.182.08:11:12.73#ibcon#enter sib2, iclass 18, count 0 2006.182.08:11:12.73#ibcon#flushed, iclass 18, count 0 2006.182.08:11:12.73#ibcon#about to write, iclass 18, count 0 2006.182.08:11:12.73#ibcon#wrote, iclass 18, count 0 2006.182.08:11:12.73#ibcon#about to read 3, iclass 18, count 0 2006.182.08:11:12.75#ibcon#read 3, iclass 18, count 0 2006.182.08:11:12.75#ibcon#about to read 4, iclass 18, count 0 2006.182.08:11:12.75#ibcon#read 4, iclass 18, count 0 2006.182.08:11:12.75#ibcon#about to read 5, iclass 18, count 0 2006.182.08:11:12.75#ibcon#read 5, iclass 18, count 0 2006.182.08:11:12.75#ibcon#about to read 6, iclass 18, count 0 2006.182.08:11:12.75#ibcon#read 6, iclass 18, count 0 2006.182.08:11:12.75#ibcon#end of sib2, iclass 18, count 0 2006.182.08:11:12.75#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:11:12.75#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:11:12.75#ibcon#[27=BW32\r\n] 2006.182.08:11:12.75#ibcon#*before write, iclass 18, count 0 2006.182.08:11:12.75#ibcon#enter sib2, iclass 18, count 0 2006.182.08:11:12.75#ibcon#flushed, iclass 18, count 0 2006.182.08:11:12.75#ibcon#about to write, iclass 18, count 0 2006.182.08:11:12.75#ibcon#wrote, iclass 18, count 0 2006.182.08:11:12.75#ibcon#about to read 3, iclass 18, count 0 2006.182.08:11:12.78#ibcon#read 3, iclass 18, count 0 2006.182.08:11:12.78#ibcon#about to read 4, iclass 18, count 0 2006.182.08:11:12.78#ibcon#read 4, iclass 18, count 0 2006.182.08:11:12.78#ibcon#about to read 5, iclass 18, count 0 2006.182.08:11:12.78#ibcon#read 5, iclass 18, count 0 2006.182.08:11:12.78#ibcon#about to read 6, iclass 18, count 0 2006.182.08:11:12.78#ibcon#read 6, iclass 18, count 0 2006.182.08:11:12.78#ibcon#end of sib2, iclass 18, count 0 2006.182.08:11:12.78#ibcon#*after write, iclass 18, count 0 2006.182.08:11:12.78#ibcon#*before return 0, iclass 18, count 0 2006.182.08:11:12.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:11:12.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:11:12.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:11:12.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:11:12.78$4f8m12a/ifd4f 2006.182.08:11:12.78$ifd4f/lo= 2006.182.08:11:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:11:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:11:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:11:12.78$ifd4f/patch= 2006.182.08:11:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:11:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:11:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:11:12.78$4f8m12a/"form=m,16.000,1:2 2006.182.08:11:12.78$4f8m12a/"tpicd 2006.182.08:11:12.78$4f8m12a/echo=off 2006.182.08:11:12.78$4f8m12a/xlog=off 2006.182.08:11:12.78:!2006.182.08:11:40 2006.182.08:11:25.13#trakl#Source acquired 2006.182.08:11:25.13#flagr#flagr/antenna,acquired 2006.182.08:11:40.00:preob 2006.182.08:11:41.13/onsource/TRACKING 2006.182.08:11:41.13:!2006.182.08:11:50 2006.182.08:11:50.00:data_valid=on 2006.182.08:11:50.00:midob 2006.182.08:11:50.13/onsource/TRACKING 2006.182.08:11:50.13/wx/27.87,1002.8,78 2006.182.08:11:50.25/cable/+6.4638E-03 2006.182.08:11:51.34/va/01,08,usb,yes,29,30 2006.182.08:11:51.34/va/02,07,usb,yes,29,31 2006.182.08:11:51.34/va/03,06,usb,yes,31,31 2006.182.08:11:51.34/va/04,07,usb,yes,30,32 2006.182.08:11:51.34/va/05,07,usb,yes,31,33 2006.182.08:11:51.34/va/06,06,usb,yes,30,30 2006.182.08:11:51.34/va/07,06,usb,yes,31,30 2006.182.08:11:51.34/va/08,07,usb,yes,29,28 2006.182.08:11:51.57/valo/01,532.99,yes,locked 2006.182.08:11:51.57/valo/02,572.99,yes,locked 2006.182.08:11:51.57/valo/03,672.99,yes,locked 2006.182.08:11:51.57/valo/04,832.99,yes,locked 2006.182.08:11:51.57/valo/05,652.99,yes,locked 2006.182.08:11:51.57/valo/06,772.99,yes,locked 2006.182.08:11:51.57/valo/07,832.99,yes,locked 2006.182.08:11:51.57/valo/08,852.99,yes,locked 2006.182.08:11:52.66/vb/01,04,usb,yes,29,28 2006.182.08:11:52.66/vb/02,04,usb,yes,31,32 2006.182.08:11:52.66/vb/03,04,usb,yes,27,31 2006.182.08:11:52.66/vb/04,04,usb,yes,28,28 2006.182.08:11:52.66/vb/05,04,usb,yes,27,31 2006.182.08:11:52.66/vb/06,04,usb,yes,28,30 2006.182.08:11:52.66/vb/07,04,usb,yes,30,30 2006.182.08:11:52.66/vb/08,04,usb,yes,27,31 2006.182.08:11:52.90/vblo/01,632.99,yes,locked 2006.182.08:11:52.90/vblo/02,640.99,yes,locked 2006.182.08:11:52.90/vblo/03,656.99,yes,locked 2006.182.08:11:52.90/vblo/04,712.99,yes,locked 2006.182.08:11:52.90/vblo/05,744.99,yes,locked 2006.182.08:11:52.90/vblo/06,752.99,yes,locked 2006.182.08:11:52.90/vblo/07,734.99,yes,locked 2006.182.08:11:52.90/vblo/08,744.99,yes,locked 2006.182.08:11:53.05/vabw/8 2006.182.08:11:53.20/vbbw/8 2006.182.08:11:53.29/xfe/off,on,14.5 2006.182.08:11:53.68/ifatt/23,28,28,28 2006.182.08:11:54.07/fmout-gps/S +3.46E-07 2006.182.08:11:54.11:!2006.182.08:12:50 2006.182.08:12:50.00:data_valid=off 2006.182.08:12:50.00:postob 2006.182.08:12:50.08/cable/+6.4634E-03 2006.182.08:12:50.08/wx/27.84,1002.8,80 2006.182.08:12:51.08/fmout-gps/S +3.47E-07 2006.182.08:12:51.08:scan_name=182-0813,k06182,60 2006.182.08:12:51.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.182.08:12:51.14#flagr#flagr/antenna,new-source 2006.182.08:12:52.14:checkk5 2006.182.08:12:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:12:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:12:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:12:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:12:54.01/chk_obsdata//k5ts1/T1820811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:12:54.39/chk_obsdata//k5ts2/T1820811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:12:54.75/chk_obsdata//k5ts3/T1820811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:12:55.12/chk_obsdata//k5ts4/T1820811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:12:55.81/k5log//k5ts1_log_newline 2006.182.08:12:56.50/k5log//k5ts2_log_newline 2006.182.08:12:57.19/k5log//k5ts3_log_newline 2006.182.08:12:57.88/k5log//k5ts4_log_newline 2006.182.08:12:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:12:57.90:4f8m12a=2 2006.182.08:12:57.90$4f8m12a/echo=on 2006.182.08:12:57.90$4f8m12a/pcalon 2006.182.08:12:57.90$pcalon/"no phase cal control is implemented here 2006.182.08:12:57.90$4f8m12a/"tpicd=stop 2006.182.08:12:57.90$4f8m12a/vc4f8 2006.182.08:12:57.90$vc4f8/valo=1,532.99 2006.182.08:12:57.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.08:12:57.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.08:12:57.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:12:57.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:12:57.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:12:57.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:12:57.91#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:12:57.91#ibcon#first serial, iclass 29, count 0 2006.182.08:12:57.91#ibcon#enter sib2, iclass 29, count 0 2006.182.08:12:57.91#ibcon#flushed, iclass 29, count 0 2006.182.08:12:57.91#ibcon#about to write, iclass 29, count 0 2006.182.08:12:57.91#ibcon#wrote, iclass 29, count 0 2006.182.08:12:57.91#ibcon#about to read 3, iclass 29, count 0 2006.182.08:12:57.95#ibcon#read 3, iclass 29, count 0 2006.182.08:12:57.95#ibcon#about to read 4, iclass 29, count 0 2006.182.08:12:57.95#ibcon#read 4, iclass 29, count 0 2006.182.08:12:57.95#ibcon#about to read 5, iclass 29, count 0 2006.182.08:12:57.95#ibcon#read 5, iclass 29, count 0 2006.182.08:12:57.95#ibcon#about to read 6, iclass 29, count 0 2006.182.08:12:57.95#ibcon#read 6, iclass 29, count 0 2006.182.08:12:57.95#ibcon#end of sib2, iclass 29, count 0 2006.182.08:12:57.95#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:12:57.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:12:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:12:57.95#ibcon#*before write, iclass 29, count 0 2006.182.08:12:57.95#ibcon#enter sib2, iclass 29, count 0 2006.182.08:12:57.95#ibcon#flushed, iclass 29, count 0 2006.182.08:12:57.95#ibcon#about to write, iclass 29, count 0 2006.182.08:12:57.95#ibcon#wrote, iclass 29, count 0 2006.182.08:12:57.95#ibcon#about to read 3, iclass 29, count 0 2006.182.08:12:57.99#ibcon#read 3, iclass 29, count 0 2006.182.08:12:57.99#ibcon#about to read 4, iclass 29, count 0 2006.182.08:12:57.99#ibcon#read 4, iclass 29, count 0 2006.182.08:12:57.99#ibcon#about to read 5, iclass 29, count 0 2006.182.08:12:57.99#ibcon#read 5, iclass 29, count 0 2006.182.08:12:57.99#ibcon#about to read 6, iclass 29, count 0 2006.182.08:12:57.99#ibcon#read 6, iclass 29, count 0 2006.182.08:12:57.99#ibcon#end of sib2, iclass 29, count 0 2006.182.08:12:57.99#ibcon#*after write, iclass 29, count 0 2006.182.08:12:57.99#ibcon#*before return 0, iclass 29, count 0 2006.182.08:12:57.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:12:57.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:12:57.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:12:57.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:12:57.99$vc4f8/va=1,8 2006.182.08:12:57.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.182.08:12:57.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.182.08:12:57.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:12:57.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:12:57.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:12:57.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:12:57.99#ibcon#enter wrdev, iclass 31, count 2 2006.182.08:12:57.99#ibcon#first serial, iclass 31, count 2 2006.182.08:12:57.99#ibcon#enter sib2, iclass 31, count 2 2006.182.08:12:57.99#ibcon#flushed, iclass 31, count 2 2006.182.08:12:57.99#ibcon#about to write, iclass 31, count 2 2006.182.08:12:57.99#ibcon#wrote, iclass 31, count 2 2006.182.08:12:57.99#ibcon#about to read 3, iclass 31, count 2 2006.182.08:12:58.01#ibcon#read 3, iclass 31, count 2 2006.182.08:12:58.01#ibcon#about to read 4, iclass 31, count 2 2006.182.08:12:58.01#ibcon#read 4, iclass 31, count 2 2006.182.08:12:58.01#ibcon#about to read 5, iclass 31, count 2 2006.182.08:12:58.01#ibcon#read 5, iclass 31, count 2 2006.182.08:12:58.01#ibcon#about to read 6, iclass 31, count 2 2006.182.08:12:58.01#ibcon#read 6, iclass 31, count 2 2006.182.08:12:58.01#ibcon#end of sib2, iclass 31, count 2 2006.182.08:12:58.01#ibcon#*mode == 0, iclass 31, count 2 2006.182.08:12:58.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.182.08:12:58.01#ibcon#[25=AT01-08\r\n] 2006.182.08:12:58.01#ibcon#*before write, iclass 31, count 2 2006.182.08:12:58.01#ibcon#enter sib2, iclass 31, count 2 2006.182.08:12:58.01#ibcon#flushed, iclass 31, count 2 2006.182.08:12:58.01#ibcon#about to write, iclass 31, count 2 2006.182.08:12:58.01#ibcon#wrote, iclass 31, count 2 2006.182.08:12:58.01#ibcon#about to read 3, iclass 31, count 2 2006.182.08:12:58.04#ibcon#read 3, iclass 31, count 2 2006.182.08:12:58.04#ibcon#about to read 4, iclass 31, count 2 2006.182.08:12:58.04#ibcon#read 4, iclass 31, count 2 2006.182.08:12:58.04#ibcon#about to read 5, iclass 31, count 2 2006.182.08:12:58.04#ibcon#read 5, iclass 31, count 2 2006.182.08:12:58.04#ibcon#about to read 6, iclass 31, count 2 2006.182.08:12:58.04#ibcon#read 6, iclass 31, count 2 2006.182.08:12:58.04#ibcon#end of sib2, iclass 31, count 2 2006.182.08:12:58.04#ibcon#*after write, iclass 31, count 2 2006.182.08:12:58.04#ibcon#*before return 0, iclass 31, count 2 2006.182.08:12:58.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:12:58.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:12:58.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.182.08:12:58.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:12:58.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:12:58.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:12:58.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:12:58.16#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:12:58.16#ibcon#first serial, iclass 31, count 0 2006.182.08:12:58.16#ibcon#enter sib2, iclass 31, count 0 2006.182.08:12:58.16#ibcon#flushed, iclass 31, count 0 2006.182.08:12:58.16#ibcon#about to write, iclass 31, count 0 2006.182.08:12:58.16#ibcon#wrote, iclass 31, count 0 2006.182.08:12:58.16#ibcon#about to read 3, iclass 31, count 0 2006.182.08:12:58.18#ibcon#read 3, iclass 31, count 0 2006.182.08:12:58.18#ibcon#about to read 4, iclass 31, count 0 2006.182.08:12:58.18#ibcon#read 4, iclass 31, count 0 2006.182.08:12:58.18#ibcon#about to read 5, iclass 31, count 0 2006.182.08:12:58.18#ibcon#read 5, iclass 31, count 0 2006.182.08:12:58.18#ibcon#about to read 6, iclass 31, count 0 2006.182.08:12:58.18#ibcon#read 6, iclass 31, count 0 2006.182.08:12:58.18#ibcon#end of sib2, iclass 31, count 0 2006.182.08:12:58.18#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:12:58.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:12:58.18#ibcon#[25=USB\r\n] 2006.182.08:12:58.18#ibcon#*before write, iclass 31, count 0 2006.182.08:12:58.18#ibcon#enter sib2, iclass 31, count 0 2006.182.08:12:58.18#ibcon#flushed, iclass 31, count 0 2006.182.08:12:58.18#ibcon#about to write, iclass 31, count 0 2006.182.08:12:58.18#ibcon#wrote, iclass 31, count 0 2006.182.08:12:58.18#ibcon#about to read 3, iclass 31, count 0 2006.182.08:12:58.21#ibcon#read 3, iclass 31, count 0 2006.182.08:12:58.21#ibcon#about to read 4, iclass 31, count 0 2006.182.08:12:58.21#ibcon#read 4, iclass 31, count 0 2006.182.08:12:58.21#ibcon#about to read 5, iclass 31, count 0 2006.182.08:12:58.21#ibcon#read 5, iclass 31, count 0 2006.182.08:12:58.21#ibcon#about to read 6, iclass 31, count 0 2006.182.08:12:58.21#ibcon#read 6, iclass 31, count 0 2006.182.08:12:58.21#ibcon#end of sib2, iclass 31, count 0 2006.182.08:12:58.21#ibcon#*after write, iclass 31, count 0 2006.182.08:12:58.21#ibcon#*before return 0, iclass 31, count 0 2006.182.08:12:58.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:12:58.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:12:58.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:12:58.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:12:58.21$vc4f8/valo=2,572.99 2006.182.08:12:58.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.182.08:12:58.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.182.08:12:58.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:12:58.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:12:58.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:12:58.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:12:58.21#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:12:58.21#ibcon#first serial, iclass 33, count 0 2006.182.08:12:58.21#ibcon#enter sib2, iclass 33, count 0 2006.182.08:12:58.21#ibcon#flushed, iclass 33, count 0 2006.182.08:12:58.21#ibcon#about to write, iclass 33, count 0 2006.182.08:12:58.21#ibcon#wrote, iclass 33, count 0 2006.182.08:12:58.21#ibcon#about to read 3, iclass 33, count 0 2006.182.08:12:58.23#ibcon#read 3, iclass 33, count 0 2006.182.08:12:58.23#ibcon#about to read 4, iclass 33, count 0 2006.182.08:12:58.23#ibcon#read 4, iclass 33, count 0 2006.182.08:12:58.23#ibcon#about to read 5, iclass 33, count 0 2006.182.08:12:58.23#ibcon#read 5, iclass 33, count 0 2006.182.08:12:58.23#ibcon#about to read 6, iclass 33, count 0 2006.182.08:12:58.23#ibcon#read 6, iclass 33, count 0 2006.182.08:12:58.23#ibcon#end of sib2, iclass 33, count 0 2006.182.08:12:58.23#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:12:58.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:12:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:12:58.23#ibcon#*before write, iclass 33, count 0 2006.182.08:12:58.23#ibcon#enter sib2, iclass 33, count 0 2006.182.08:12:58.23#ibcon#flushed, iclass 33, count 0 2006.182.08:12:58.23#ibcon#about to write, iclass 33, count 0 2006.182.08:12:58.23#ibcon#wrote, iclass 33, count 0 2006.182.08:12:58.23#ibcon#about to read 3, iclass 33, count 0 2006.182.08:12:58.27#ibcon#read 3, iclass 33, count 0 2006.182.08:12:58.27#ibcon#about to read 4, iclass 33, count 0 2006.182.08:12:58.27#ibcon#read 4, iclass 33, count 0 2006.182.08:12:58.27#ibcon#about to read 5, iclass 33, count 0 2006.182.08:12:58.27#ibcon#read 5, iclass 33, count 0 2006.182.08:12:58.27#ibcon#about to read 6, iclass 33, count 0 2006.182.08:12:58.27#ibcon#read 6, iclass 33, count 0 2006.182.08:12:58.27#ibcon#end of sib2, iclass 33, count 0 2006.182.08:12:58.27#ibcon#*after write, iclass 33, count 0 2006.182.08:12:58.27#ibcon#*before return 0, iclass 33, count 0 2006.182.08:12:58.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:12:58.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:12:58.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:12:58.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:12:58.27$vc4f8/va=2,7 2006.182.08:12:58.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.182.08:12:58.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.182.08:12:58.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:12:58.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:12:58.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:12:58.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:12:58.34#ibcon#enter wrdev, iclass 35, count 2 2006.182.08:12:58.34#ibcon#first serial, iclass 35, count 2 2006.182.08:12:58.34#ibcon#enter sib2, iclass 35, count 2 2006.182.08:12:58.34#ibcon#flushed, iclass 35, count 2 2006.182.08:12:58.34#ibcon#about to write, iclass 35, count 2 2006.182.08:12:58.34#ibcon#wrote, iclass 35, count 2 2006.182.08:12:58.34#ibcon#about to read 3, iclass 35, count 2 2006.182.08:12:58.35#ibcon#read 3, iclass 35, count 2 2006.182.08:12:58.35#ibcon#about to read 4, iclass 35, count 2 2006.182.08:12:58.35#ibcon#read 4, iclass 35, count 2 2006.182.08:12:58.35#ibcon#about to read 5, iclass 35, count 2 2006.182.08:12:58.35#ibcon#read 5, iclass 35, count 2 2006.182.08:12:58.35#ibcon#about to read 6, iclass 35, count 2 2006.182.08:12:58.35#ibcon#read 6, iclass 35, count 2 2006.182.08:12:58.35#ibcon#end of sib2, iclass 35, count 2 2006.182.08:12:58.35#ibcon#*mode == 0, iclass 35, count 2 2006.182.08:12:58.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.182.08:12:58.35#ibcon#[25=AT02-07\r\n] 2006.182.08:12:58.35#ibcon#*before write, iclass 35, count 2 2006.182.08:12:58.35#ibcon#enter sib2, iclass 35, count 2 2006.182.08:12:58.35#ibcon#flushed, iclass 35, count 2 2006.182.08:12:58.35#ibcon#about to write, iclass 35, count 2 2006.182.08:12:58.35#ibcon#wrote, iclass 35, count 2 2006.182.08:12:58.35#ibcon#about to read 3, iclass 35, count 2 2006.182.08:12:58.38#ibcon#read 3, iclass 35, count 2 2006.182.08:12:58.38#ibcon#about to read 4, iclass 35, count 2 2006.182.08:12:58.38#ibcon#read 4, iclass 35, count 2 2006.182.08:12:58.38#ibcon#about to read 5, iclass 35, count 2 2006.182.08:12:58.38#ibcon#read 5, iclass 35, count 2 2006.182.08:12:58.38#ibcon#about to read 6, iclass 35, count 2 2006.182.08:12:58.38#ibcon#read 6, iclass 35, count 2 2006.182.08:12:58.38#ibcon#end of sib2, iclass 35, count 2 2006.182.08:12:58.38#ibcon#*after write, iclass 35, count 2 2006.182.08:12:58.38#ibcon#*before return 0, iclass 35, count 2 2006.182.08:12:58.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:12:58.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:12:58.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.182.08:12:58.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:12:58.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:12:58.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:12:58.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:12:58.50#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:12:58.50#ibcon#first serial, iclass 35, count 0 2006.182.08:12:58.50#ibcon#enter sib2, iclass 35, count 0 2006.182.08:12:58.50#ibcon#flushed, iclass 35, count 0 2006.182.08:12:58.50#ibcon#about to write, iclass 35, count 0 2006.182.08:12:58.50#ibcon#wrote, iclass 35, count 0 2006.182.08:12:58.50#ibcon#about to read 3, iclass 35, count 0 2006.182.08:12:58.52#ibcon#read 3, iclass 35, count 0 2006.182.08:12:58.52#ibcon#about to read 4, iclass 35, count 0 2006.182.08:12:58.52#ibcon#read 4, iclass 35, count 0 2006.182.08:12:58.52#ibcon#about to read 5, iclass 35, count 0 2006.182.08:12:58.52#ibcon#read 5, iclass 35, count 0 2006.182.08:12:58.52#ibcon#about to read 6, iclass 35, count 0 2006.182.08:12:58.52#ibcon#read 6, iclass 35, count 0 2006.182.08:12:58.52#ibcon#end of sib2, iclass 35, count 0 2006.182.08:12:58.52#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:12:58.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:12:58.52#ibcon#[25=USB\r\n] 2006.182.08:12:58.52#ibcon#*before write, iclass 35, count 0 2006.182.08:12:58.52#ibcon#enter sib2, iclass 35, count 0 2006.182.08:12:58.52#ibcon#flushed, iclass 35, count 0 2006.182.08:12:58.52#ibcon#about to write, iclass 35, count 0 2006.182.08:12:58.52#ibcon#wrote, iclass 35, count 0 2006.182.08:12:58.52#ibcon#about to read 3, iclass 35, count 0 2006.182.08:12:58.55#ibcon#read 3, iclass 35, count 0 2006.182.08:12:58.55#ibcon#about to read 4, iclass 35, count 0 2006.182.08:12:58.55#ibcon#read 4, iclass 35, count 0 2006.182.08:12:58.55#ibcon#about to read 5, iclass 35, count 0 2006.182.08:12:58.55#ibcon#read 5, iclass 35, count 0 2006.182.08:12:58.55#ibcon#about to read 6, iclass 35, count 0 2006.182.08:12:58.55#ibcon#read 6, iclass 35, count 0 2006.182.08:12:58.55#ibcon#end of sib2, iclass 35, count 0 2006.182.08:12:58.55#ibcon#*after write, iclass 35, count 0 2006.182.08:12:58.55#ibcon#*before return 0, iclass 35, count 0 2006.182.08:12:58.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:12:58.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:12:58.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:12:58.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:12:58.55$vc4f8/valo=3,672.99 2006.182.08:12:58.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.182.08:12:58.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.182.08:12:58.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:12:58.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:12:58.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:12:58.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:12:58.55#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:12:58.55#ibcon#first serial, iclass 37, count 0 2006.182.08:12:58.55#ibcon#enter sib2, iclass 37, count 0 2006.182.08:12:58.55#ibcon#flushed, iclass 37, count 0 2006.182.08:12:58.55#ibcon#about to write, iclass 37, count 0 2006.182.08:12:58.55#ibcon#wrote, iclass 37, count 0 2006.182.08:12:58.55#ibcon#about to read 3, iclass 37, count 0 2006.182.08:12:58.57#ibcon#read 3, iclass 37, count 0 2006.182.08:12:58.57#ibcon#about to read 4, iclass 37, count 0 2006.182.08:12:58.57#ibcon#read 4, iclass 37, count 0 2006.182.08:12:58.57#ibcon#about to read 5, iclass 37, count 0 2006.182.08:12:58.57#ibcon#read 5, iclass 37, count 0 2006.182.08:12:58.57#ibcon#about to read 6, iclass 37, count 0 2006.182.08:12:58.57#ibcon#read 6, iclass 37, count 0 2006.182.08:12:58.57#ibcon#end of sib2, iclass 37, count 0 2006.182.08:12:58.57#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:12:58.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:12:58.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:12:58.57#ibcon#*before write, iclass 37, count 0 2006.182.08:12:58.57#ibcon#enter sib2, iclass 37, count 0 2006.182.08:12:58.57#ibcon#flushed, iclass 37, count 0 2006.182.08:12:58.57#ibcon#about to write, iclass 37, count 0 2006.182.08:12:58.57#ibcon#wrote, iclass 37, count 0 2006.182.08:12:58.57#ibcon#about to read 3, iclass 37, count 0 2006.182.08:12:58.61#ibcon#read 3, iclass 37, count 0 2006.182.08:12:58.61#ibcon#about to read 4, iclass 37, count 0 2006.182.08:12:58.61#ibcon#read 4, iclass 37, count 0 2006.182.08:12:58.61#ibcon#about to read 5, iclass 37, count 0 2006.182.08:12:58.61#ibcon#read 5, iclass 37, count 0 2006.182.08:12:58.61#ibcon#about to read 6, iclass 37, count 0 2006.182.08:12:58.61#ibcon#read 6, iclass 37, count 0 2006.182.08:12:58.61#ibcon#end of sib2, iclass 37, count 0 2006.182.08:12:58.61#ibcon#*after write, iclass 37, count 0 2006.182.08:12:58.61#ibcon#*before return 0, iclass 37, count 0 2006.182.08:12:58.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:12:58.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:12:58.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:12:58.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:12:58.61$vc4f8/va=3,6 2006.182.08:12:58.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.08:12:58.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.08:12:58.61#ibcon#ireg 11 cls_cnt 2 2006.182.08:12:58.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:12:58.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:12:58.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:12:58.68#ibcon#enter wrdev, iclass 39, count 2 2006.182.08:12:58.68#ibcon#first serial, iclass 39, count 2 2006.182.08:12:58.68#ibcon#enter sib2, iclass 39, count 2 2006.182.08:12:58.68#ibcon#flushed, iclass 39, count 2 2006.182.08:12:58.68#ibcon#about to write, iclass 39, count 2 2006.182.08:12:58.68#ibcon#wrote, iclass 39, count 2 2006.182.08:12:58.68#ibcon#about to read 3, iclass 39, count 2 2006.182.08:12:58.69#ibcon#read 3, iclass 39, count 2 2006.182.08:12:58.69#ibcon#about to read 4, iclass 39, count 2 2006.182.08:12:58.69#ibcon#read 4, iclass 39, count 2 2006.182.08:12:58.69#ibcon#about to read 5, iclass 39, count 2 2006.182.08:12:58.69#ibcon#read 5, iclass 39, count 2 2006.182.08:12:58.69#ibcon#about to read 6, iclass 39, count 2 2006.182.08:12:58.69#ibcon#read 6, iclass 39, count 2 2006.182.08:12:58.69#ibcon#end of sib2, iclass 39, count 2 2006.182.08:12:58.69#ibcon#*mode == 0, iclass 39, count 2 2006.182.08:12:58.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.08:12:58.69#ibcon#[25=AT03-06\r\n] 2006.182.08:12:58.69#ibcon#*before write, iclass 39, count 2 2006.182.08:12:58.69#ibcon#enter sib2, iclass 39, count 2 2006.182.08:12:58.69#ibcon#flushed, iclass 39, count 2 2006.182.08:12:58.69#ibcon#about to write, iclass 39, count 2 2006.182.08:12:58.69#ibcon#wrote, iclass 39, count 2 2006.182.08:12:58.69#ibcon#about to read 3, iclass 39, count 2 2006.182.08:12:58.72#ibcon#read 3, iclass 39, count 2 2006.182.08:12:58.72#ibcon#about to read 4, iclass 39, count 2 2006.182.08:12:58.72#ibcon#read 4, iclass 39, count 2 2006.182.08:12:58.72#ibcon#about to read 5, iclass 39, count 2 2006.182.08:12:58.72#ibcon#read 5, iclass 39, count 2 2006.182.08:12:58.72#ibcon#about to read 6, iclass 39, count 2 2006.182.08:12:58.72#ibcon#read 6, iclass 39, count 2 2006.182.08:12:58.72#ibcon#end of sib2, iclass 39, count 2 2006.182.08:12:58.72#ibcon#*after write, iclass 39, count 2 2006.182.08:12:58.72#ibcon#*before return 0, iclass 39, count 2 2006.182.08:12:58.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:12:58.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:12:58.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.08:12:58.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:12:58.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:12:58.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:12:58.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:12:58.84#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:12:58.84#ibcon#first serial, iclass 39, count 0 2006.182.08:12:58.84#ibcon#enter sib2, iclass 39, count 0 2006.182.08:12:58.84#ibcon#flushed, iclass 39, count 0 2006.182.08:12:58.84#ibcon#about to write, iclass 39, count 0 2006.182.08:12:58.84#ibcon#wrote, iclass 39, count 0 2006.182.08:12:58.84#ibcon#about to read 3, iclass 39, count 0 2006.182.08:12:58.86#ibcon#read 3, iclass 39, count 0 2006.182.08:12:58.86#ibcon#about to read 4, iclass 39, count 0 2006.182.08:12:58.86#ibcon#read 4, iclass 39, count 0 2006.182.08:12:58.86#ibcon#about to read 5, iclass 39, count 0 2006.182.08:12:58.86#ibcon#read 5, iclass 39, count 0 2006.182.08:12:58.86#ibcon#about to read 6, iclass 39, count 0 2006.182.08:12:58.86#ibcon#read 6, iclass 39, count 0 2006.182.08:12:58.86#ibcon#end of sib2, iclass 39, count 0 2006.182.08:12:58.86#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:12:58.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:12:58.86#ibcon#[25=USB\r\n] 2006.182.08:12:58.86#ibcon#*before write, iclass 39, count 0 2006.182.08:12:58.86#ibcon#enter sib2, iclass 39, count 0 2006.182.08:12:58.86#ibcon#flushed, iclass 39, count 0 2006.182.08:12:58.86#ibcon#about to write, iclass 39, count 0 2006.182.08:12:58.86#ibcon#wrote, iclass 39, count 0 2006.182.08:12:58.86#ibcon#about to read 3, iclass 39, count 0 2006.182.08:12:58.89#ibcon#read 3, iclass 39, count 0 2006.182.08:12:58.89#ibcon#about to read 4, iclass 39, count 0 2006.182.08:12:58.89#ibcon#read 4, iclass 39, count 0 2006.182.08:12:58.89#ibcon#about to read 5, iclass 39, count 0 2006.182.08:12:58.89#ibcon#read 5, iclass 39, count 0 2006.182.08:12:58.89#ibcon#about to read 6, iclass 39, count 0 2006.182.08:12:58.89#ibcon#read 6, iclass 39, count 0 2006.182.08:12:58.89#ibcon#end of sib2, iclass 39, count 0 2006.182.08:12:58.89#ibcon#*after write, iclass 39, count 0 2006.182.08:12:58.89#ibcon#*before return 0, iclass 39, count 0 2006.182.08:12:58.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:12:58.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:12:58.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:12:58.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:12:58.89$vc4f8/valo=4,832.99 2006.182.08:12:58.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.08:12:58.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.08:12:58.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:12:58.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:12:58.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:12:58.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:12:58.89#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:12:58.89#ibcon#first serial, iclass 3, count 0 2006.182.08:12:58.89#ibcon#enter sib2, iclass 3, count 0 2006.182.08:12:58.89#ibcon#flushed, iclass 3, count 0 2006.182.08:12:58.89#ibcon#about to write, iclass 3, count 0 2006.182.08:12:58.89#ibcon#wrote, iclass 3, count 0 2006.182.08:12:58.89#ibcon#about to read 3, iclass 3, count 0 2006.182.08:12:58.91#ibcon#read 3, iclass 3, count 0 2006.182.08:12:58.91#ibcon#about to read 4, iclass 3, count 0 2006.182.08:12:58.91#ibcon#read 4, iclass 3, count 0 2006.182.08:12:58.91#ibcon#about to read 5, iclass 3, count 0 2006.182.08:12:58.91#ibcon#read 5, iclass 3, count 0 2006.182.08:12:58.91#ibcon#about to read 6, iclass 3, count 0 2006.182.08:12:58.91#ibcon#read 6, iclass 3, count 0 2006.182.08:12:58.91#ibcon#end of sib2, iclass 3, count 0 2006.182.08:12:58.91#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:12:58.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:12:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:12:58.91#ibcon#*before write, iclass 3, count 0 2006.182.08:12:58.91#ibcon#enter sib2, iclass 3, count 0 2006.182.08:12:58.91#ibcon#flushed, iclass 3, count 0 2006.182.08:12:58.91#ibcon#about to write, iclass 3, count 0 2006.182.08:12:58.91#ibcon#wrote, iclass 3, count 0 2006.182.08:12:58.91#ibcon#about to read 3, iclass 3, count 0 2006.182.08:12:58.95#ibcon#read 3, iclass 3, count 0 2006.182.08:12:58.95#ibcon#about to read 4, iclass 3, count 0 2006.182.08:12:58.95#ibcon#read 4, iclass 3, count 0 2006.182.08:12:58.95#ibcon#about to read 5, iclass 3, count 0 2006.182.08:12:58.95#ibcon#read 5, iclass 3, count 0 2006.182.08:12:58.95#ibcon#about to read 6, iclass 3, count 0 2006.182.08:12:58.95#ibcon#read 6, iclass 3, count 0 2006.182.08:12:58.95#ibcon#end of sib2, iclass 3, count 0 2006.182.08:12:58.95#ibcon#*after write, iclass 3, count 0 2006.182.08:12:58.95#ibcon#*before return 0, iclass 3, count 0 2006.182.08:12:58.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:12:58.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:12:58.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:12:58.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:12:58.95$vc4f8/va=4,7 2006.182.08:12:58.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.08:12:58.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.08:12:58.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:12:58.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:12:59.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:12:59.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:12:59.02#ibcon#enter wrdev, iclass 5, count 2 2006.182.08:12:59.02#ibcon#first serial, iclass 5, count 2 2006.182.08:12:59.02#ibcon#enter sib2, iclass 5, count 2 2006.182.08:12:59.02#ibcon#flushed, iclass 5, count 2 2006.182.08:12:59.02#ibcon#about to write, iclass 5, count 2 2006.182.08:12:59.02#ibcon#wrote, iclass 5, count 2 2006.182.08:12:59.02#ibcon#about to read 3, iclass 5, count 2 2006.182.08:12:59.03#ibcon#read 3, iclass 5, count 2 2006.182.08:12:59.03#ibcon#about to read 4, iclass 5, count 2 2006.182.08:12:59.03#ibcon#read 4, iclass 5, count 2 2006.182.08:12:59.03#ibcon#about to read 5, iclass 5, count 2 2006.182.08:12:59.03#ibcon#read 5, iclass 5, count 2 2006.182.08:12:59.03#ibcon#about to read 6, iclass 5, count 2 2006.182.08:12:59.03#ibcon#read 6, iclass 5, count 2 2006.182.08:12:59.03#ibcon#end of sib2, iclass 5, count 2 2006.182.08:12:59.03#ibcon#*mode == 0, iclass 5, count 2 2006.182.08:12:59.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.08:12:59.03#ibcon#[25=AT04-07\r\n] 2006.182.08:12:59.03#ibcon#*before write, iclass 5, count 2 2006.182.08:12:59.03#ibcon#enter sib2, iclass 5, count 2 2006.182.08:12:59.03#ibcon#flushed, iclass 5, count 2 2006.182.08:12:59.03#ibcon#about to write, iclass 5, count 2 2006.182.08:12:59.03#ibcon#wrote, iclass 5, count 2 2006.182.08:12:59.03#ibcon#about to read 3, iclass 5, count 2 2006.182.08:12:59.06#ibcon#read 3, iclass 5, count 2 2006.182.08:12:59.06#ibcon#about to read 4, iclass 5, count 2 2006.182.08:12:59.06#ibcon#read 4, iclass 5, count 2 2006.182.08:12:59.06#ibcon#about to read 5, iclass 5, count 2 2006.182.08:12:59.06#ibcon#read 5, iclass 5, count 2 2006.182.08:12:59.06#ibcon#about to read 6, iclass 5, count 2 2006.182.08:12:59.06#ibcon#read 6, iclass 5, count 2 2006.182.08:12:59.06#ibcon#end of sib2, iclass 5, count 2 2006.182.08:12:59.06#ibcon#*after write, iclass 5, count 2 2006.182.08:12:59.06#ibcon#*before return 0, iclass 5, count 2 2006.182.08:12:59.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:12:59.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:12:59.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.08:12:59.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:12:59.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:12:59.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:12:59.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:12:59.18#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:12:59.18#ibcon#first serial, iclass 5, count 0 2006.182.08:12:59.18#ibcon#enter sib2, iclass 5, count 0 2006.182.08:12:59.18#ibcon#flushed, iclass 5, count 0 2006.182.08:12:59.18#ibcon#about to write, iclass 5, count 0 2006.182.08:12:59.18#ibcon#wrote, iclass 5, count 0 2006.182.08:12:59.18#ibcon#about to read 3, iclass 5, count 0 2006.182.08:12:59.20#ibcon#read 3, iclass 5, count 0 2006.182.08:12:59.20#ibcon#about to read 4, iclass 5, count 0 2006.182.08:12:59.20#ibcon#read 4, iclass 5, count 0 2006.182.08:12:59.20#ibcon#about to read 5, iclass 5, count 0 2006.182.08:12:59.20#ibcon#read 5, iclass 5, count 0 2006.182.08:12:59.20#ibcon#about to read 6, iclass 5, count 0 2006.182.08:12:59.20#ibcon#read 6, iclass 5, count 0 2006.182.08:12:59.20#ibcon#end of sib2, iclass 5, count 0 2006.182.08:12:59.20#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:12:59.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:12:59.20#ibcon#[25=USB\r\n] 2006.182.08:12:59.20#ibcon#*before write, iclass 5, count 0 2006.182.08:12:59.20#ibcon#enter sib2, iclass 5, count 0 2006.182.08:12:59.20#ibcon#flushed, iclass 5, count 0 2006.182.08:12:59.20#ibcon#about to write, iclass 5, count 0 2006.182.08:12:59.20#ibcon#wrote, iclass 5, count 0 2006.182.08:12:59.20#ibcon#about to read 3, iclass 5, count 0 2006.182.08:12:59.23#ibcon#read 3, iclass 5, count 0 2006.182.08:12:59.23#ibcon#about to read 4, iclass 5, count 0 2006.182.08:12:59.23#ibcon#read 4, iclass 5, count 0 2006.182.08:12:59.23#ibcon#about to read 5, iclass 5, count 0 2006.182.08:12:59.23#ibcon#read 5, iclass 5, count 0 2006.182.08:12:59.23#ibcon#about to read 6, iclass 5, count 0 2006.182.08:12:59.23#ibcon#read 6, iclass 5, count 0 2006.182.08:12:59.23#ibcon#end of sib2, iclass 5, count 0 2006.182.08:12:59.23#ibcon#*after write, iclass 5, count 0 2006.182.08:12:59.23#ibcon#*before return 0, iclass 5, count 0 2006.182.08:12:59.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:12:59.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:12:59.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:12:59.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:12:59.23$vc4f8/valo=5,652.99 2006.182.08:12:59.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.08:12:59.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.08:12:59.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:12:59.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:12:59.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:12:59.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:12:59.23#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:12:59.23#ibcon#first serial, iclass 7, count 0 2006.182.08:12:59.23#ibcon#enter sib2, iclass 7, count 0 2006.182.08:12:59.23#ibcon#flushed, iclass 7, count 0 2006.182.08:12:59.23#ibcon#about to write, iclass 7, count 0 2006.182.08:12:59.23#ibcon#wrote, iclass 7, count 0 2006.182.08:12:59.23#ibcon#about to read 3, iclass 7, count 0 2006.182.08:12:59.25#ibcon#read 3, iclass 7, count 0 2006.182.08:12:59.25#ibcon#about to read 4, iclass 7, count 0 2006.182.08:12:59.25#ibcon#read 4, iclass 7, count 0 2006.182.08:12:59.25#ibcon#about to read 5, iclass 7, count 0 2006.182.08:12:59.25#ibcon#read 5, iclass 7, count 0 2006.182.08:12:59.25#ibcon#about to read 6, iclass 7, count 0 2006.182.08:12:59.25#ibcon#read 6, iclass 7, count 0 2006.182.08:12:59.25#ibcon#end of sib2, iclass 7, count 0 2006.182.08:12:59.25#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:12:59.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:12:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:12:59.25#ibcon#*before write, iclass 7, count 0 2006.182.08:12:59.25#ibcon#enter sib2, iclass 7, count 0 2006.182.08:12:59.25#ibcon#flushed, iclass 7, count 0 2006.182.08:12:59.25#ibcon#about to write, iclass 7, count 0 2006.182.08:12:59.25#ibcon#wrote, iclass 7, count 0 2006.182.08:12:59.25#ibcon#about to read 3, iclass 7, count 0 2006.182.08:12:59.29#ibcon#read 3, iclass 7, count 0 2006.182.08:12:59.29#ibcon#about to read 4, iclass 7, count 0 2006.182.08:12:59.29#ibcon#read 4, iclass 7, count 0 2006.182.08:12:59.29#ibcon#about to read 5, iclass 7, count 0 2006.182.08:12:59.29#ibcon#read 5, iclass 7, count 0 2006.182.08:12:59.29#ibcon#about to read 6, iclass 7, count 0 2006.182.08:12:59.29#ibcon#read 6, iclass 7, count 0 2006.182.08:12:59.29#ibcon#end of sib2, iclass 7, count 0 2006.182.08:12:59.29#ibcon#*after write, iclass 7, count 0 2006.182.08:12:59.29#ibcon#*before return 0, iclass 7, count 0 2006.182.08:12:59.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:12:59.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:12:59.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:12:59.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:12:59.29$vc4f8/va=5,7 2006.182.08:12:59.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.08:12:59.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.08:12:59.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:12:59.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:12:59.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:12:59.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:12:59.35#ibcon#enter wrdev, iclass 11, count 2 2006.182.08:12:59.35#ibcon#first serial, iclass 11, count 2 2006.182.08:12:59.35#ibcon#enter sib2, iclass 11, count 2 2006.182.08:12:59.35#ibcon#flushed, iclass 11, count 2 2006.182.08:12:59.35#ibcon#about to write, iclass 11, count 2 2006.182.08:12:59.35#ibcon#wrote, iclass 11, count 2 2006.182.08:12:59.35#ibcon#about to read 3, iclass 11, count 2 2006.182.08:12:59.37#ibcon#read 3, iclass 11, count 2 2006.182.08:12:59.37#ibcon#about to read 4, iclass 11, count 2 2006.182.08:12:59.37#ibcon#read 4, iclass 11, count 2 2006.182.08:12:59.37#ibcon#about to read 5, iclass 11, count 2 2006.182.08:12:59.37#ibcon#read 5, iclass 11, count 2 2006.182.08:12:59.37#ibcon#about to read 6, iclass 11, count 2 2006.182.08:12:59.37#ibcon#read 6, iclass 11, count 2 2006.182.08:12:59.37#ibcon#end of sib2, iclass 11, count 2 2006.182.08:12:59.37#ibcon#*mode == 0, iclass 11, count 2 2006.182.08:12:59.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.08:12:59.37#ibcon#[25=AT05-07\r\n] 2006.182.08:12:59.37#ibcon#*before write, iclass 11, count 2 2006.182.08:12:59.37#ibcon#enter sib2, iclass 11, count 2 2006.182.08:12:59.37#ibcon#flushed, iclass 11, count 2 2006.182.08:12:59.37#ibcon#about to write, iclass 11, count 2 2006.182.08:12:59.37#ibcon#wrote, iclass 11, count 2 2006.182.08:12:59.37#ibcon#about to read 3, iclass 11, count 2 2006.182.08:12:59.40#ibcon#read 3, iclass 11, count 2 2006.182.08:12:59.40#ibcon#about to read 4, iclass 11, count 2 2006.182.08:12:59.40#ibcon#read 4, iclass 11, count 2 2006.182.08:12:59.40#ibcon#about to read 5, iclass 11, count 2 2006.182.08:12:59.40#ibcon#read 5, iclass 11, count 2 2006.182.08:12:59.40#ibcon#about to read 6, iclass 11, count 2 2006.182.08:12:59.40#ibcon#read 6, iclass 11, count 2 2006.182.08:12:59.40#ibcon#end of sib2, iclass 11, count 2 2006.182.08:12:59.40#ibcon#*after write, iclass 11, count 2 2006.182.08:12:59.40#ibcon#*before return 0, iclass 11, count 2 2006.182.08:12:59.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:12:59.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:12:59.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.08:12:59.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:12:59.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:12:59.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:12:59.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:12:59.52#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:12:59.52#ibcon#first serial, iclass 11, count 0 2006.182.08:12:59.52#ibcon#enter sib2, iclass 11, count 0 2006.182.08:12:59.52#ibcon#flushed, iclass 11, count 0 2006.182.08:12:59.52#ibcon#about to write, iclass 11, count 0 2006.182.08:12:59.52#ibcon#wrote, iclass 11, count 0 2006.182.08:12:59.52#ibcon#about to read 3, iclass 11, count 0 2006.182.08:12:59.54#ibcon#read 3, iclass 11, count 0 2006.182.08:12:59.54#ibcon#about to read 4, iclass 11, count 0 2006.182.08:12:59.54#ibcon#read 4, iclass 11, count 0 2006.182.08:12:59.54#ibcon#about to read 5, iclass 11, count 0 2006.182.08:12:59.54#ibcon#read 5, iclass 11, count 0 2006.182.08:12:59.54#ibcon#about to read 6, iclass 11, count 0 2006.182.08:12:59.54#ibcon#read 6, iclass 11, count 0 2006.182.08:12:59.54#ibcon#end of sib2, iclass 11, count 0 2006.182.08:12:59.54#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:12:59.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:12:59.54#ibcon#[25=USB\r\n] 2006.182.08:12:59.54#ibcon#*before write, iclass 11, count 0 2006.182.08:12:59.54#ibcon#enter sib2, iclass 11, count 0 2006.182.08:12:59.54#ibcon#flushed, iclass 11, count 0 2006.182.08:12:59.54#ibcon#about to write, iclass 11, count 0 2006.182.08:12:59.54#ibcon#wrote, iclass 11, count 0 2006.182.08:12:59.54#ibcon#about to read 3, iclass 11, count 0 2006.182.08:12:59.57#ibcon#read 3, iclass 11, count 0 2006.182.08:12:59.57#ibcon#about to read 4, iclass 11, count 0 2006.182.08:12:59.57#ibcon#read 4, iclass 11, count 0 2006.182.08:12:59.57#ibcon#about to read 5, iclass 11, count 0 2006.182.08:12:59.57#ibcon#read 5, iclass 11, count 0 2006.182.08:12:59.57#ibcon#about to read 6, iclass 11, count 0 2006.182.08:12:59.57#ibcon#read 6, iclass 11, count 0 2006.182.08:12:59.57#ibcon#end of sib2, iclass 11, count 0 2006.182.08:12:59.57#ibcon#*after write, iclass 11, count 0 2006.182.08:12:59.57#ibcon#*before return 0, iclass 11, count 0 2006.182.08:12:59.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:12:59.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:12:59.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:12:59.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:12:59.57$vc4f8/valo=6,772.99 2006.182.08:12:59.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.08:12:59.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.08:12:59.57#ibcon#ireg 17 cls_cnt 0 2006.182.08:12:59.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:12:59.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:12:59.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:12:59.57#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:12:59.57#ibcon#first serial, iclass 13, count 0 2006.182.08:12:59.57#ibcon#enter sib2, iclass 13, count 0 2006.182.08:12:59.57#ibcon#flushed, iclass 13, count 0 2006.182.08:12:59.57#ibcon#about to write, iclass 13, count 0 2006.182.08:12:59.57#ibcon#wrote, iclass 13, count 0 2006.182.08:12:59.57#ibcon#about to read 3, iclass 13, count 0 2006.182.08:12:59.59#ibcon#read 3, iclass 13, count 0 2006.182.08:12:59.59#ibcon#about to read 4, iclass 13, count 0 2006.182.08:12:59.59#ibcon#read 4, iclass 13, count 0 2006.182.08:12:59.59#ibcon#about to read 5, iclass 13, count 0 2006.182.08:12:59.59#ibcon#read 5, iclass 13, count 0 2006.182.08:12:59.59#ibcon#about to read 6, iclass 13, count 0 2006.182.08:12:59.59#ibcon#read 6, iclass 13, count 0 2006.182.08:12:59.59#ibcon#end of sib2, iclass 13, count 0 2006.182.08:12:59.59#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:12:59.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:12:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:12:59.59#ibcon#*before write, iclass 13, count 0 2006.182.08:12:59.59#ibcon#enter sib2, iclass 13, count 0 2006.182.08:12:59.59#ibcon#flushed, iclass 13, count 0 2006.182.08:12:59.59#ibcon#about to write, iclass 13, count 0 2006.182.08:12:59.59#ibcon#wrote, iclass 13, count 0 2006.182.08:12:59.59#ibcon#about to read 3, iclass 13, count 0 2006.182.08:12:59.63#ibcon#read 3, iclass 13, count 0 2006.182.08:12:59.63#ibcon#about to read 4, iclass 13, count 0 2006.182.08:12:59.63#ibcon#read 4, iclass 13, count 0 2006.182.08:12:59.63#ibcon#about to read 5, iclass 13, count 0 2006.182.08:12:59.63#ibcon#read 5, iclass 13, count 0 2006.182.08:12:59.63#ibcon#about to read 6, iclass 13, count 0 2006.182.08:12:59.63#ibcon#read 6, iclass 13, count 0 2006.182.08:12:59.63#ibcon#end of sib2, iclass 13, count 0 2006.182.08:12:59.63#ibcon#*after write, iclass 13, count 0 2006.182.08:12:59.63#ibcon#*before return 0, iclass 13, count 0 2006.182.08:12:59.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:12:59.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:12:59.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:12:59.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:12:59.63$vc4f8/va=6,6 2006.182.08:12:59.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.182.08:12:59.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.182.08:12:59.63#ibcon#ireg 11 cls_cnt 2 2006.182.08:12:59.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:12:59.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:12:59.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:12:59.70#ibcon#enter wrdev, iclass 15, count 2 2006.182.08:12:59.70#ibcon#first serial, iclass 15, count 2 2006.182.08:12:59.70#ibcon#enter sib2, iclass 15, count 2 2006.182.08:12:59.70#ibcon#flushed, iclass 15, count 2 2006.182.08:12:59.70#ibcon#about to write, iclass 15, count 2 2006.182.08:12:59.70#ibcon#wrote, iclass 15, count 2 2006.182.08:12:59.70#ibcon#about to read 3, iclass 15, count 2 2006.182.08:12:59.71#ibcon#read 3, iclass 15, count 2 2006.182.08:12:59.71#ibcon#about to read 4, iclass 15, count 2 2006.182.08:12:59.71#ibcon#read 4, iclass 15, count 2 2006.182.08:12:59.71#ibcon#about to read 5, iclass 15, count 2 2006.182.08:12:59.71#ibcon#read 5, iclass 15, count 2 2006.182.08:12:59.71#ibcon#about to read 6, iclass 15, count 2 2006.182.08:12:59.71#ibcon#read 6, iclass 15, count 2 2006.182.08:12:59.71#ibcon#end of sib2, iclass 15, count 2 2006.182.08:12:59.71#ibcon#*mode == 0, iclass 15, count 2 2006.182.08:12:59.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.182.08:12:59.71#ibcon#[25=AT06-06\r\n] 2006.182.08:12:59.71#ibcon#*before write, iclass 15, count 2 2006.182.08:12:59.71#ibcon#enter sib2, iclass 15, count 2 2006.182.08:12:59.71#ibcon#flushed, iclass 15, count 2 2006.182.08:12:59.71#ibcon#about to write, iclass 15, count 2 2006.182.08:12:59.71#ibcon#wrote, iclass 15, count 2 2006.182.08:12:59.71#ibcon#about to read 3, iclass 15, count 2 2006.182.08:12:59.74#ibcon#read 3, iclass 15, count 2 2006.182.08:12:59.74#ibcon#about to read 4, iclass 15, count 2 2006.182.08:12:59.74#ibcon#read 4, iclass 15, count 2 2006.182.08:12:59.74#ibcon#about to read 5, iclass 15, count 2 2006.182.08:12:59.74#ibcon#read 5, iclass 15, count 2 2006.182.08:12:59.74#ibcon#about to read 6, iclass 15, count 2 2006.182.08:12:59.74#ibcon#read 6, iclass 15, count 2 2006.182.08:12:59.74#ibcon#end of sib2, iclass 15, count 2 2006.182.08:12:59.74#ibcon#*after write, iclass 15, count 2 2006.182.08:12:59.74#ibcon#*before return 0, iclass 15, count 2 2006.182.08:12:59.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:12:59.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:12:59.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.182.08:12:59.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:12:59.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:12:59.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:12:59.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:12:59.86#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:12:59.86#ibcon#first serial, iclass 15, count 0 2006.182.08:12:59.86#ibcon#enter sib2, iclass 15, count 0 2006.182.08:12:59.86#ibcon#flushed, iclass 15, count 0 2006.182.08:12:59.86#ibcon#about to write, iclass 15, count 0 2006.182.08:12:59.86#ibcon#wrote, iclass 15, count 0 2006.182.08:12:59.86#ibcon#about to read 3, iclass 15, count 0 2006.182.08:12:59.88#ibcon#read 3, iclass 15, count 0 2006.182.08:12:59.88#ibcon#about to read 4, iclass 15, count 0 2006.182.08:12:59.88#ibcon#read 4, iclass 15, count 0 2006.182.08:12:59.88#ibcon#about to read 5, iclass 15, count 0 2006.182.08:12:59.88#ibcon#read 5, iclass 15, count 0 2006.182.08:12:59.88#ibcon#about to read 6, iclass 15, count 0 2006.182.08:12:59.88#ibcon#read 6, iclass 15, count 0 2006.182.08:12:59.88#ibcon#end of sib2, iclass 15, count 0 2006.182.08:12:59.88#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:12:59.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:12:59.88#ibcon#[25=USB\r\n] 2006.182.08:12:59.88#ibcon#*before write, iclass 15, count 0 2006.182.08:12:59.88#ibcon#enter sib2, iclass 15, count 0 2006.182.08:12:59.88#ibcon#flushed, iclass 15, count 0 2006.182.08:12:59.88#ibcon#about to write, iclass 15, count 0 2006.182.08:12:59.88#ibcon#wrote, iclass 15, count 0 2006.182.08:12:59.88#ibcon#about to read 3, iclass 15, count 0 2006.182.08:12:59.91#ibcon#read 3, iclass 15, count 0 2006.182.08:12:59.91#ibcon#about to read 4, iclass 15, count 0 2006.182.08:12:59.91#ibcon#read 4, iclass 15, count 0 2006.182.08:12:59.91#ibcon#about to read 5, iclass 15, count 0 2006.182.08:12:59.91#ibcon#read 5, iclass 15, count 0 2006.182.08:12:59.91#ibcon#about to read 6, iclass 15, count 0 2006.182.08:12:59.91#ibcon#read 6, iclass 15, count 0 2006.182.08:12:59.91#ibcon#end of sib2, iclass 15, count 0 2006.182.08:12:59.91#ibcon#*after write, iclass 15, count 0 2006.182.08:12:59.91#ibcon#*before return 0, iclass 15, count 0 2006.182.08:12:59.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:12:59.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:12:59.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:12:59.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:12:59.91$vc4f8/valo=7,832.99 2006.182.08:12:59.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.08:12:59.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.08:12:59.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:12:59.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:12:59.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:12:59.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:12:59.91#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:12:59.91#ibcon#first serial, iclass 17, count 0 2006.182.08:12:59.91#ibcon#enter sib2, iclass 17, count 0 2006.182.08:12:59.91#ibcon#flushed, iclass 17, count 0 2006.182.08:12:59.91#ibcon#about to write, iclass 17, count 0 2006.182.08:12:59.91#ibcon#wrote, iclass 17, count 0 2006.182.08:12:59.91#ibcon#about to read 3, iclass 17, count 0 2006.182.08:12:59.93#ibcon#read 3, iclass 17, count 0 2006.182.08:12:59.93#ibcon#about to read 4, iclass 17, count 0 2006.182.08:12:59.93#ibcon#read 4, iclass 17, count 0 2006.182.08:12:59.93#ibcon#about to read 5, iclass 17, count 0 2006.182.08:12:59.93#ibcon#read 5, iclass 17, count 0 2006.182.08:12:59.93#ibcon#about to read 6, iclass 17, count 0 2006.182.08:12:59.93#ibcon#read 6, iclass 17, count 0 2006.182.08:12:59.93#ibcon#end of sib2, iclass 17, count 0 2006.182.08:12:59.93#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:12:59.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:12:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:12:59.93#ibcon#*before write, iclass 17, count 0 2006.182.08:12:59.93#ibcon#enter sib2, iclass 17, count 0 2006.182.08:12:59.93#ibcon#flushed, iclass 17, count 0 2006.182.08:12:59.93#ibcon#about to write, iclass 17, count 0 2006.182.08:12:59.93#ibcon#wrote, iclass 17, count 0 2006.182.08:12:59.93#ibcon#about to read 3, iclass 17, count 0 2006.182.08:12:59.97#ibcon#read 3, iclass 17, count 0 2006.182.08:12:59.97#ibcon#about to read 4, iclass 17, count 0 2006.182.08:12:59.97#ibcon#read 4, iclass 17, count 0 2006.182.08:12:59.97#ibcon#about to read 5, iclass 17, count 0 2006.182.08:12:59.97#ibcon#read 5, iclass 17, count 0 2006.182.08:12:59.97#ibcon#about to read 6, iclass 17, count 0 2006.182.08:12:59.97#ibcon#read 6, iclass 17, count 0 2006.182.08:12:59.97#ibcon#end of sib2, iclass 17, count 0 2006.182.08:12:59.97#ibcon#*after write, iclass 17, count 0 2006.182.08:12:59.97#ibcon#*before return 0, iclass 17, count 0 2006.182.08:12:59.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:12:59.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:12:59.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:12:59.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:12:59.97$vc4f8/va=7,6 2006.182.08:12:59.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.182.08:12:59.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.182.08:12:59.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:12:59.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:13:00.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:13:00.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:13:00.03#ibcon#enter wrdev, iclass 19, count 2 2006.182.08:13:00.03#ibcon#first serial, iclass 19, count 2 2006.182.08:13:00.03#ibcon#enter sib2, iclass 19, count 2 2006.182.08:13:00.03#ibcon#flushed, iclass 19, count 2 2006.182.08:13:00.03#ibcon#about to write, iclass 19, count 2 2006.182.08:13:00.03#ibcon#wrote, iclass 19, count 2 2006.182.08:13:00.03#ibcon#about to read 3, iclass 19, count 2 2006.182.08:13:00.05#ibcon#read 3, iclass 19, count 2 2006.182.08:13:00.05#ibcon#about to read 4, iclass 19, count 2 2006.182.08:13:00.05#ibcon#read 4, iclass 19, count 2 2006.182.08:13:00.05#ibcon#about to read 5, iclass 19, count 2 2006.182.08:13:00.05#ibcon#read 5, iclass 19, count 2 2006.182.08:13:00.05#ibcon#about to read 6, iclass 19, count 2 2006.182.08:13:00.05#ibcon#read 6, iclass 19, count 2 2006.182.08:13:00.05#ibcon#end of sib2, iclass 19, count 2 2006.182.08:13:00.05#ibcon#*mode == 0, iclass 19, count 2 2006.182.08:13:00.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.182.08:13:00.05#ibcon#[25=AT07-06\r\n] 2006.182.08:13:00.05#ibcon#*before write, iclass 19, count 2 2006.182.08:13:00.05#ibcon#enter sib2, iclass 19, count 2 2006.182.08:13:00.05#ibcon#flushed, iclass 19, count 2 2006.182.08:13:00.05#ibcon#about to write, iclass 19, count 2 2006.182.08:13:00.05#ibcon#wrote, iclass 19, count 2 2006.182.08:13:00.05#ibcon#about to read 3, iclass 19, count 2 2006.182.08:13:00.08#ibcon#read 3, iclass 19, count 2 2006.182.08:13:00.08#ibcon#about to read 4, iclass 19, count 2 2006.182.08:13:00.08#ibcon#read 4, iclass 19, count 2 2006.182.08:13:00.08#ibcon#about to read 5, iclass 19, count 2 2006.182.08:13:00.08#ibcon#read 5, iclass 19, count 2 2006.182.08:13:00.08#ibcon#about to read 6, iclass 19, count 2 2006.182.08:13:00.08#ibcon#read 6, iclass 19, count 2 2006.182.08:13:00.08#ibcon#end of sib2, iclass 19, count 2 2006.182.08:13:00.08#ibcon#*after write, iclass 19, count 2 2006.182.08:13:00.08#ibcon#*before return 0, iclass 19, count 2 2006.182.08:13:00.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:13:00.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:13:00.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.182.08:13:00.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:13:00.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:13:00.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:13:00.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:13:00.20#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:13:00.20#ibcon#first serial, iclass 19, count 0 2006.182.08:13:00.20#ibcon#enter sib2, iclass 19, count 0 2006.182.08:13:00.20#ibcon#flushed, iclass 19, count 0 2006.182.08:13:00.20#ibcon#about to write, iclass 19, count 0 2006.182.08:13:00.20#ibcon#wrote, iclass 19, count 0 2006.182.08:13:00.20#ibcon#about to read 3, iclass 19, count 0 2006.182.08:13:00.22#ibcon#read 3, iclass 19, count 0 2006.182.08:13:00.22#ibcon#about to read 4, iclass 19, count 0 2006.182.08:13:00.22#ibcon#read 4, iclass 19, count 0 2006.182.08:13:00.22#ibcon#about to read 5, iclass 19, count 0 2006.182.08:13:00.22#ibcon#read 5, iclass 19, count 0 2006.182.08:13:00.22#ibcon#about to read 6, iclass 19, count 0 2006.182.08:13:00.22#ibcon#read 6, iclass 19, count 0 2006.182.08:13:00.22#ibcon#end of sib2, iclass 19, count 0 2006.182.08:13:00.22#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:13:00.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:13:00.22#ibcon#[25=USB\r\n] 2006.182.08:13:00.22#ibcon#*before write, iclass 19, count 0 2006.182.08:13:00.22#ibcon#enter sib2, iclass 19, count 0 2006.182.08:13:00.22#ibcon#flushed, iclass 19, count 0 2006.182.08:13:00.22#ibcon#about to write, iclass 19, count 0 2006.182.08:13:00.22#ibcon#wrote, iclass 19, count 0 2006.182.08:13:00.22#ibcon#about to read 3, iclass 19, count 0 2006.182.08:13:00.25#ibcon#read 3, iclass 19, count 0 2006.182.08:13:00.25#ibcon#about to read 4, iclass 19, count 0 2006.182.08:13:00.25#ibcon#read 4, iclass 19, count 0 2006.182.08:13:00.25#ibcon#about to read 5, iclass 19, count 0 2006.182.08:13:00.25#ibcon#read 5, iclass 19, count 0 2006.182.08:13:00.25#ibcon#about to read 6, iclass 19, count 0 2006.182.08:13:00.25#ibcon#read 6, iclass 19, count 0 2006.182.08:13:00.25#ibcon#end of sib2, iclass 19, count 0 2006.182.08:13:00.25#ibcon#*after write, iclass 19, count 0 2006.182.08:13:00.25#ibcon#*before return 0, iclass 19, count 0 2006.182.08:13:00.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:13:00.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:13:00.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:13:00.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:13:00.25$vc4f8/valo=8,852.99 2006.182.08:13:00.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.08:13:00.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.08:13:00.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:13:00.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:13:00.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:13:00.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:13:00.25#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:13:00.25#ibcon#first serial, iclass 21, count 0 2006.182.08:13:00.25#ibcon#enter sib2, iclass 21, count 0 2006.182.08:13:00.25#ibcon#flushed, iclass 21, count 0 2006.182.08:13:00.25#ibcon#about to write, iclass 21, count 0 2006.182.08:13:00.25#ibcon#wrote, iclass 21, count 0 2006.182.08:13:00.25#ibcon#about to read 3, iclass 21, count 0 2006.182.08:13:00.27#ibcon#read 3, iclass 21, count 0 2006.182.08:13:00.27#ibcon#about to read 4, iclass 21, count 0 2006.182.08:13:00.27#ibcon#read 4, iclass 21, count 0 2006.182.08:13:00.27#ibcon#about to read 5, iclass 21, count 0 2006.182.08:13:00.27#ibcon#read 5, iclass 21, count 0 2006.182.08:13:00.27#ibcon#about to read 6, iclass 21, count 0 2006.182.08:13:00.27#ibcon#read 6, iclass 21, count 0 2006.182.08:13:00.27#ibcon#end of sib2, iclass 21, count 0 2006.182.08:13:00.27#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:13:00.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:13:00.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:13:00.27#ibcon#*before write, iclass 21, count 0 2006.182.08:13:00.27#ibcon#enter sib2, iclass 21, count 0 2006.182.08:13:00.27#ibcon#flushed, iclass 21, count 0 2006.182.08:13:00.27#ibcon#about to write, iclass 21, count 0 2006.182.08:13:00.27#ibcon#wrote, iclass 21, count 0 2006.182.08:13:00.27#ibcon#about to read 3, iclass 21, count 0 2006.182.08:13:00.31#ibcon#read 3, iclass 21, count 0 2006.182.08:13:00.31#ibcon#about to read 4, iclass 21, count 0 2006.182.08:13:00.31#ibcon#read 4, iclass 21, count 0 2006.182.08:13:00.31#ibcon#about to read 5, iclass 21, count 0 2006.182.08:13:00.31#ibcon#read 5, iclass 21, count 0 2006.182.08:13:00.31#ibcon#about to read 6, iclass 21, count 0 2006.182.08:13:00.31#ibcon#read 6, iclass 21, count 0 2006.182.08:13:00.31#ibcon#end of sib2, iclass 21, count 0 2006.182.08:13:00.31#ibcon#*after write, iclass 21, count 0 2006.182.08:13:00.31#ibcon#*before return 0, iclass 21, count 0 2006.182.08:13:00.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:13:00.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:13:00.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:13:00.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:13:00.31$vc4f8/va=8,7 2006.182.08:13:00.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.182.08:13:00.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.182.08:13:00.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:13:00.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:13:00.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:13:00.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:13:00.37#ibcon#enter wrdev, iclass 23, count 2 2006.182.08:13:00.37#ibcon#first serial, iclass 23, count 2 2006.182.08:13:00.37#ibcon#enter sib2, iclass 23, count 2 2006.182.08:13:00.37#ibcon#flushed, iclass 23, count 2 2006.182.08:13:00.37#ibcon#about to write, iclass 23, count 2 2006.182.08:13:00.37#ibcon#wrote, iclass 23, count 2 2006.182.08:13:00.37#ibcon#about to read 3, iclass 23, count 2 2006.182.08:13:00.39#ibcon#read 3, iclass 23, count 2 2006.182.08:13:00.39#ibcon#about to read 4, iclass 23, count 2 2006.182.08:13:00.39#ibcon#read 4, iclass 23, count 2 2006.182.08:13:00.39#ibcon#about to read 5, iclass 23, count 2 2006.182.08:13:00.39#ibcon#read 5, iclass 23, count 2 2006.182.08:13:00.39#ibcon#about to read 6, iclass 23, count 2 2006.182.08:13:00.39#ibcon#read 6, iclass 23, count 2 2006.182.08:13:00.39#ibcon#end of sib2, iclass 23, count 2 2006.182.08:13:00.39#ibcon#*mode == 0, iclass 23, count 2 2006.182.08:13:00.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.182.08:13:00.39#ibcon#[25=AT08-07\r\n] 2006.182.08:13:00.39#ibcon#*before write, iclass 23, count 2 2006.182.08:13:00.39#ibcon#enter sib2, iclass 23, count 2 2006.182.08:13:00.39#ibcon#flushed, iclass 23, count 2 2006.182.08:13:00.39#ibcon#about to write, iclass 23, count 2 2006.182.08:13:00.39#ibcon#wrote, iclass 23, count 2 2006.182.08:13:00.39#ibcon#about to read 3, iclass 23, count 2 2006.182.08:13:00.42#ibcon#read 3, iclass 23, count 2 2006.182.08:13:00.42#ibcon#about to read 4, iclass 23, count 2 2006.182.08:13:00.42#ibcon#read 4, iclass 23, count 2 2006.182.08:13:00.42#ibcon#about to read 5, iclass 23, count 2 2006.182.08:13:00.42#ibcon#read 5, iclass 23, count 2 2006.182.08:13:00.42#ibcon#about to read 6, iclass 23, count 2 2006.182.08:13:00.42#ibcon#read 6, iclass 23, count 2 2006.182.08:13:00.42#ibcon#end of sib2, iclass 23, count 2 2006.182.08:13:00.42#ibcon#*after write, iclass 23, count 2 2006.182.08:13:00.42#ibcon#*before return 0, iclass 23, count 2 2006.182.08:13:00.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:13:00.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:13:00.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.182.08:13:00.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:13:00.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:13:00.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:13:00.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:13:00.54#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:13:00.54#ibcon#first serial, iclass 23, count 0 2006.182.08:13:00.54#ibcon#enter sib2, iclass 23, count 0 2006.182.08:13:00.54#ibcon#flushed, iclass 23, count 0 2006.182.08:13:00.54#ibcon#about to write, iclass 23, count 0 2006.182.08:13:00.54#ibcon#wrote, iclass 23, count 0 2006.182.08:13:00.54#ibcon#about to read 3, iclass 23, count 0 2006.182.08:13:00.56#ibcon#read 3, iclass 23, count 0 2006.182.08:13:00.56#ibcon#about to read 4, iclass 23, count 0 2006.182.08:13:00.56#ibcon#read 4, iclass 23, count 0 2006.182.08:13:00.56#ibcon#about to read 5, iclass 23, count 0 2006.182.08:13:00.56#ibcon#read 5, iclass 23, count 0 2006.182.08:13:00.56#ibcon#about to read 6, iclass 23, count 0 2006.182.08:13:00.56#ibcon#read 6, iclass 23, count 0 2006.182.08:13:00.56#ibcon#end of sib2, iclass 23, count 0 2006.182.08:13:00.56#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:13:00.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:13:00.56#ibcon#[25=USB\r\n] 2006.182.08:13:00.56#ibcon#*before write, iclass 23, count 0 2006.182.08:13:00.56#ibcon#enter sib2, iclass 23, count 0 2006.182.08:13:00.56#ibcon#flushed, iclass 23, count 0 2006.182.08:13:00.56#ibcon#about to write, iclass 23, count 0 2006.182.08:13:00.56#ibcon#wrote, iclass 23, count 0 2006.182.08:13:00.56#ibcon#about to read 3, iclass 23, count 0 2006.182.08:13:00.59#ibcon#read 3, iclass 23, count 0 2006.182.08:13:00.59#ibcon#about to read 4, iclass 23, count 0 2006.182.08:13:00.59#ibcon#read 4, iclass 23, count 0 2006.182.08:13:00.59#ibcon#about to read 5, iclass 23, count 0 2006.182.08:13:00.59#ibcon#read 5, iclass 23, count 0 2006.182.08:13:00.59#ibcon#about to read 6, iclass 23, count 0 2006.182.08:13:00.59#ibcon#read 6, iclass 23, count 0 2006.182.08:13:00.59#ibcon#end of sib2, iclass 23, count 0 2006.182.08:13:00.59#ibcon#*after write, iclass 23, count 0 2006.182.08:13:00.59#ibcon#*before return 0, iclass 23, count 0 2006.182.08:13:00.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:13:00.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:13:00.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:13:00.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:13:00.59$vc4f8/vblo=1,632.99 2006.182.08:13:00.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.08:13:00.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.08:13:00.59#ibcon#ireg 17 cls_cnt 0 2006.182.08:13:00.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:13:00.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:13:00.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:13:00.59#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:13:00.59#ibcon#first serial, iclass 25, count 0 2006.182.08:13:00.59#ibcon#enter sib2, iclass 25, count 0 2006.182.08:13:00.59#ibcon#flushed, iclass 25, count 0 2006.182.08:13:00.59#ibcon#about to write, iclass 25, count 0 2006.182.08:13:00.59#ibcon#wrote, iclass 25, count 0 2006.182.08:13:00.59#ibcon#about to read 3, iclass 25, count 0 2006.182.08:13:00.61#ibcon#read 3, iclass 25, count 0 2006.182.08:13:00.61#ibcon#about to read 4, iclass 25, count 0 2006.182.08:13:00.61#ibcon#read 4, iclass 25, count 0 2006.182.08:13:00.61#ibcon#about to read 5, iclass 25, count 0 2006.182.08:13:00.61#ibcon#read 5, iclass 25, count 0 2006.182.08:13:00.61#ibcon#about to read 6, iclass 25, count 0 2006.182.08:13:00.61#ibcon#read 6, iclass 25, count 0 2006.182.08:13:00.61#ibcon#end of sib2, iclass 25, count 0 2006.182.08:13:00.61#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:13:00.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:13:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:13:00.61#ibcon#*before write, iclass 25, count 0 2006.182.08:13:00.61#ibcon#enter sib2, iclass 25, count 0 2006.182.08:13:00.61#ibcon#flushed, iclass 25, count 0 2006.182.08:13:00.61#ibcon#about to write, iclass 25, count 0 2006.182.08:13:00.61#ibcon#wrote, iclass 25, count 0 2006.182.08:13:00.61#ibcon#about to read 3, iclass 25, count 0 2006.182.08:13:00.65#ibcon#read 3, iclass 25, count 0 2006.182.08:13:00.65#ibcon#about to read 4, iclass 25, count 0 2006.182.08:13:00.65#ibcon#read 4, iclass 25, count 0 2006.182.08:13:00.65#ibcon#about to read 5, iclass 25, count 0 2006.182.08:13:00.65#ibcon#read 5, iclass 25, count 0 2006.182.08:13:00.65#ibcon#about to read 6, iclass 25, count 0 2006.182.08:13:00.65#ibcon#read 6, iclass 25, count 0 2006.182.08:13:00.65#ibcon#end of sib2, iclass 25, count 0 2006.182.08:13:00.65#ibcon#*after write, iclass 25, count 0 2006.182.08:13:00.65#ibcon#*before return 0, iclass 25, count 0 2006.182.08:13:00.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:13:00.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:13:00.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:13:00.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:13:00.65$vc4f8/vb=1,4 2006.182.08:13:00.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.182.08:13:00.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.182.08:13:00.65#ibcon#ireg 11 cls_cnt 2 2006.182.08:13:00.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:13:00.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:13:00.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:13:00.65#ibcon#enter wrdev, iclass 27, count 2 2006.182.08:13:00.65#ibcon#first serial, iclass 27, count 2 2006.182.08:13:00.65#ibcon#enter sib2, iclass 27, count 2 2006.182.08:13:00.65#ibcon#flushed, iclass 27, count 2 2006.182.08:13:00.65#ibcon#about to write, iclass 27, count 2 2006.182.08:13:00.65#ibcon#wrote, iclass 27, count 2 2006.182.08:13:00.65#ibcon#about to read 3, iclass 27, count 2 2006.182.08:13:00.67#ibcon#read 3, iclass 27, count 2 2006.182.08:13:00.67#ibcon#about to read 4, iclass 27, count 2 2006.182.08:13:00.67#ibcon#read 4, iclass 27, count 2 2006.182.08:13:00.67#ibcon#about to read 5, iclass 27, count 2 2006.182.08:13:00.67#ibcon#read 5, iclass 27, count 2 2006.182.08:13:00.67#ibcon#about to read 6, iclass 27, count 2 2006.182.08:13:00.67#ibcon#read 6, iclass 27, count 2 2006.182.08:13:00.67#ibcon#end of sib2, iclass 27, count 2 2006.182.08:13:00.67#ibcon#*mode == 0, iclass 27, count 2 2006.182.08:13:00.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.182.08:13:00.67#ibcon#[27=AT01-04\r\n] 2006.182.08:13:00.67#ibcon#*before write, iclass 27, count 2 2006.182.08:13:00.67#ibcon#enter sib2, iclass 27, count 2 2006.182.08:13:00.67#ibcon#flushed, iclass 27, count 2 2006.182.08:13:00.67#ibcon#about to write, iclass 27, count 2 2006.182.08:13:00.67#ibcon#wrote, iclass 27, count 2 2006.182.08:13:00.67#ibcon#about to read 3, iclass 27, count 2 2006.182.08:13:00.70#ibcon#read 3, iclass 27, count 2 2006.182.08:13:00.70#ibcon#about to read 4, iclass 27, count 2 2006.182.08:13:00.70#ibcon#read 4, iclass 27, count 2 2006.182.08:13:00.70#ibcon#about to read 5, iclass 27, count 2 2006.182.08:13:00.70#ibcon#read 5, iclass 27, count 2 2006.182.08:13:00.70#ibcon#about to read 6, iclass 27, count 2 2006.182.08:13:00.70#ibcon#read 6, iclass 27, count 2 2006.182.08:13:00.70#ibcon#end of sib2, iclass 27, count 2 2006.182.08:13:00.70#ibcon#*after write, iclass 27, count 2 2006.182.08:13:00.70#ibcon#*before return 0, iclass 27, count 2 2006.182.08:13:00.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:13:00.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:13:00.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.182.08:13:00.70#ibcon#ireg 7 cls_cnt 0 2006.182.08:13:00.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:13:00.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:13:00.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:13:00.82#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:13:00.82#ibcon#first serial, iclass 27, count 0 2006.182.08:13:00.82#ibcon#enter sib2, iclass 27, count 0 2006.182.08:13:00.82#ibcon#flushed, iclass 27, count 0 2006.182.08:13:00.82#ibcon#about to write, iclass 27, count 0 2006.182.08:13:00.82#ibcon#wrote, iclass 27, count 0 2006.182.08:13:00.82#ibcon#about to read 3, iclass 27, count 0 2006.182.08:13:00.84#ibcon#read 3, iclass 27, count 0 2006.182.08:13:00.84#ibcon#about to read 4, iclass 27, count 0 2006.182.08:13:00.84#ibcon#read 4, iclass 27, count 0 2006.182.08:13:00.84#ibcon#about to read 5, iclass 27, count 0 2006.182.08:13:00.84#ibcon#read 5, iclass 27, count 0 2006.182.08:13:00.84#ibcon#about to read 6, iclass 27, count 0 2006.182.08:13:00.84#ibcon#read 6, iclass 27, count 0 2006.182.08:13:00.84#ibcon#end of sib2, iclass 27, count 0 2006.182.08:13:00.84#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:13:00.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:13:00.84#ibcon#[27=USB\r\n] 2006.182.08:13:00.84#ibcon#*before write, iclass 27, count 0 2006.182.08:13:00.84#ibcon#enter sib2, iclass 27, count 0 2006.182.08:13:00.84#ibcon#flushed, iclass 27, count 0 2006.182.08:13:00.84#ibcon#about to write, iclass 27, count 0 2006.182.08:13:00.84#ibcon#wrote, iclass 27, count 0 2006.182.08:13:00.84#ibcon#about to read 3, iclass 27, count 0 2006.182.08:13:00.87#ibcon#read 3, iclass 27, count 0 2006.182.08:13:00.87#ibcon#about to read 4, iclass 27, count 0 2006.182.08:13:00.87#ibcon#read 4, iclass 27, count 0 2006.182.08:13:00.87#ibcon#about to read 5, iclass 27, count 0 2006.182.08:13:00.87#ibcon#read 5, iclass 27, count 0 2006.182.08:13:00.87#ibcon#about to read 6, iclass 27, count 0 2006.182.08:13:00.87#ibcon#read 6, iclass 27, count 0 2006.182.08:13:00.87#ibcon#end of sib2, iclass 27, count 0 2006.182.08:13:00.87#ibcon#*after write, iclass 27, count 0 2006.182.08:13:00.87#ibcon#*before return 0, iclass 27, count 0 2006.182.08:13:00.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:13:00.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:13:00.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:13:00.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:13:00.87$vc4f8/vblo=2,640.99 2006.182.08:13:00.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.08:13:00.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.08:13:00.87#ibcon#ireg 17 cls_cnt 0 2006.182.08:13:00.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:13:00.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:13:00.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:13:00.87#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:13:00.87#ibcon#first serial, iclass 29, count 0 2006.182.08:13:00.87#ibcon#enter sib2, iclass 29, count 0 2006.182.08:13:00.87#ibcon#flushed, iclass 29, count 0 2006.182.08:13:00.87#ibcon#about to write, iclass 29, count 0 2006.182.08:13:00.87#ibcon#wrote, iclass 29, count 0 2006.182.08:13:00.87#ibcon#about to read 3, iclass 29, count 0 2006.182.08:13:00.89#ibcon#read 3, iclass 29, count 0 2006.182.08:13:00.89#ibcon#about to read 4, iclass 29, count 0 2006.182.08:13:00.89#ibcon#read 4, iclass 29, count 0 2006.182.08:13:00.89#ibcon#about to read 5, iclass 29, count 0 2006.182.08:13:00.89#ibcon#read 5, iclass 29, count 0 2006.182.08:13:00.89#ibcon#about to read 6, iclass 29, count 0 2006.182.08:13:00.89#ibcon#read 6, iclass 29, count 0 2006.182.08:13:00.89#ibcon#end of sib2, iclass 29, count 0 2006.182.08:13:00.89#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:13:00.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:13:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:13:00.89#ibcon#*before write, iclass 29, count 0 2006.182.08:13:00.89#ibcon#enter sib2, iclass 29, count 0 2006.182.08:13:00.89#ibcon#flushed, iclass 29, count 0 2006.182.08:13:00.89#ibcon#about to write, iclass 29, count 0 2006.182.08:13:00.89#ibcon#wrote, iclass 29, count 0 2006.182.08:13:00.89#ibcon#about to read 3, iclass 29, count 0 2006.182.08:13:00.93#ibcon#read 3, iclass 29, count 0 2006.182.08:13:00.93#ibcon#about to read 4, iclass 29, count 0 2006.182.08:13:00.93#ibcon#read 4, iclass 29, count 0 2006.182.08:13:00.93#ibcon#about to read 5, iclass 29, count 0 2006.182.08:13:00.93#ibcon#read 5, iclass 29, count 0 2006.182.08:13:00.93#ibcon#about to read 6, iclass 29, count 0 2006.182.08:13:00.93#ibcon#read 6, iclass 29, count 0 2006.182.08:13:00.93#ibcon#end of sib2, iclass 29, count 0 2006.182.08:13:00.93#ibcon#*after write, iclass 29, count 0 2006.182.08:13:00.93#ibcon#*before return 0, iclass 29, count 0 2006.182.08:13:00.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:13:00.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:13:00.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:13:00.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:13:00.93$vc4f8/vb=2,4 2006.182.08:13:00.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.182.08:13:00.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.182.08:13:00.93#ibcon#ireg 11 cls_cnt 2 2006.182.08:13:00.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:13:00.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:13:00.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:13:00.99#ibcon#enter wrdev, iclass 31, count 2 2006.182.08:13:00.99#ibcon#first serial, iclass 31, count 2 2006.182.08:13:00.99#ibcon#enter sib2, iclass 31, count 2 2006.182.08:13:00.99#ibcon#flushed, iclass 31, count 2 2006.182.08:13:00.99#ibcon#about to write, iclass 31, count 2 2006.182.08:13:00.99#ibcon#wrote, iclass 31, count 2 2006.182.08:13:00.99#ibcon#about to read 3, iclass 31, count 2 2006.182.08:13:01.01#ibcon#read 3, iclass 31, count 2 2006.182.08:13:01.01#ibcon#about to read 4, iclass 31, count 2 2006.182.08:13:01.01#ibcon#read 4, iclass 31, count 2 2006.182.08:13:01.01#ibcon#about to read 5, iclass 31, count 2 2006.182.08:13:01.01#ibcon#read 5, iclass 31, count 2 2006.182.08:13:01.01#ibcon#about to read 6, iclass 31, count 2 2006.182.08:13:01.01#ibcon#read 6, iclass 31, count 2 2006.182.08:13:01.01#ibcon#end of sib2, iclass 31, count 2 2006.182.08:13:01.01#ibcon#*mode == 0, iclass 31, count 2 2006.182.08:13:01.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.182.08:13:01.01#ibcon#[27=AT02-04\r\n] 2006.182.08:13:01.01#ibcon#*before write, iclass 31, count 2 2006.182.08:13:01.01#ibcon#enter sib2, iclass 31, count 2 2006.182.08:13:01.01#ibcon#flushed, iclass 31, count 2 2006.182.08:13:01.01#ibcon#about to write, iclass 31, count 2 2006.182.08:13:01.01#ibcon#wrote, iclass 31, count 2 2006.182.08:13:01.01#ibcon#about to read 3, iclass 31, count 2 2006.182.08:13:01.04#ibcon#read 3, iclass 31, count 2 2006.182.08:13:01.04#ibcon#about to read 4, iclass 31, count 2 2006.182.08:13:01.04#ibcon#read 4, iclass 31, count 2 2006.182.08:13:01.04#ibcon#about to read 5, iclass 31, count 2 2006.182.08:13:01.04#ibcon#read 5, iclass 31, count 2 2006.182.08:13:01.04#ibcon#about to read 6, iclass 31, count 2 2006.182.08:13:01.04#ibcon#read 6, iclass 31, count 2 2006.182.08:13:01.04#ibcon#end of sib2, iclass 31, count 2 2006.182.08:13:01.04#ibcon#*after write, iclass 31, count 2 2006.182.08:13:01.04#ibcon#*before return 0, iclass 31, count 2 2006.182.08:13:01.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:13:01.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:13:01.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.182.08:13:01.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:13:01.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:13:01.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:13:01.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:13:01.16#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:13:01.16#ibcon#first serial, iclass 31, count 0 2006.182.08:13:01.16#ibcon#enter sib2, iclass 31, count 0 2006.182.08:13:01.16#ibcon#flushed, iclass 31, count 0 2006.182.08:13:01.16#ibcon#about to write, iclass 31, count 0 2006.182.08:13:01.16#ibcon#wrote, iclass 31, count 0 2006.182.08:13:01.16#ibcon#about to read 3, iclass 31, count 0 2006.182.08:13:01.18#ibcon#read 3, iclass 31, count 0 2006.182.08:13:01.18#ibcon#about to read 4, iclass 31, count 0 2006.182.08:13:01.18#ibcon#read 4, iclass 31, count 0 2006.182.08:13:01.18#ibcon#about to read 5, iclass 31, count 0 2006.182.08:13:01.18#ibcon#read 5, iclass 31, count 0 2006.182.08:13:01.18#ibcon#about to read 6, iclass 31, count 0 2006.182.08:13:01.18#ibcon#read 6, iclass 31, count 0 2006.182.08:13:01.18#ibcon#end of sib2, iclass 31, count 0 2006.182.08:13:01.18#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:13:01.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:13:01.18#ibcon#[27=USB\r\n] 2006.182.08:13:01.18#ibcon#*before write, iclass 31, count 0 2006.182.08:13:01.18#ibcon#enter sib2, iclass 31, count 0 2006.182.08:13:01.18#ibcon#flushed, iclass 31, count 0 2006.182.08:13:01.18#ibcon#about to write, iclass 31, count 0 2006.182.08:13:01.18#ibcon#wrote, iclass 31, count 0 2006.182.08:13:01.18#ibcon#about to read 3, iclass 31, count 0 2006.182.08:13:01.21#ibcon#read 3, iclass 31, count 0 2006.182.08:13:01.21#ibcon#about to read 4, iclass 31, count 0 2006.182.08:13:01.21#ibcon#read 4, iclass 31, count 0 2006.182.08:13:01.21#ibcon#about to read 5, iclass 31, count 0 2006.182.08:13:01.21#ibcon#read 5, iclass 31, count 0 2006.182.08:13:01.21#ibcon#about to read 6, iclass 31, count 0 2006.182.08:13:01.21#ibcon#read 6, iclass 31, count 0 2006.182.08:13:01.21#ibcon#end of sib2, iclass 31, count 0 2006.182.08:13:01.21#ibcon#*after write, iclass 31, count 0 2006.182.08:13:01.21#ibcon#*before return 0, iclass 31, count 0 2006.182.08:13:01.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:13:01.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:13:01.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:13:01.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:13:01.21$vc4f8/vblo=3,656.99 2006.182.08:13:01.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.182.08:13:01.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.182.08:13:01.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:13:01.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:13:01.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:13:01.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:13:01.21#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:13:01.21#ibcon#first serial, iclass 33, count 0 2006.182.08:13:01.21#ibcon#enter sib2, iclass 33, count 0 2006.182.08:13:01.21#ibcon#flushed, iclass 33, count 0 2006.182.08:13:01.21#ibcon#about to write, iclass 33, count 0 2006.182.08:13:01.21#ibcon#wrote, iclass 33, count 0 2006.182.08:13:01.21#ibcon#about to read 3, iclass 33, count 0 2006.182.08:13:01.23#ibcon#read 3, iclass 33, count 0 2006.182.08:13:01.23#ibcon#about to read 4, iclass 33, count 0 2006.182.08:13:01.23#ibcon#read 4, iclass 33, count 0 2006.182.08:13:01.23#ibcon#about to read 5, iclass 33, count 0 2006.182.08:13:01.23#ibcon#read 5, iclass 33, count 0 2006.182.08:13:01.23#ibcon#about to read 6, iclass 33, count 0 2006.182.08:13:01.23#ibcon#read 6, iclass 33, count 0 2006.182.08:13:01.23#ibcon#end of sib2, iclass 33, count 0 2006.182.08:13:01.23#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:13:01.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:13:01.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:13:01.23#ibcon#*before write, iclass 33, count 0 2006.182.08:13:01.23#ibcon#enter sib2, iclass 33, count 0 2006.182.08:13:01.23#ibcon#flushed, iclass 33, count 0 2006.182.08:13:01.23#ibcon#about to write, iclass 33, count 0 2006.182.08:13:01.23#ibcon#wrote, iclass 33, count 0 2006.182.08:13:01.23#ibcon#about to read 3, iclass 33, count 0 2006.182.08:13:01.27#ibcon#read 3, iclass 33, count 0 2006.182.08:13:01.27#ibcon#about to read 4, iclass 33, count 0 2006.182.08:13:01.27#ibcon#read 4, iclass 33, count 0 2006.182.08:13:01.27#ibcon#about to read 5, iclass 33, count 0 2006.182.08:13:01.27#ibcon#read 5, iclass 33, count 0 2006.182.08:13:01.27#ibcon#about to read 6, iclass 33, count 0 2006.182.08:13:01.27#ibcon#read 6, iclass 33, count 0 2006.182.08:13:01.27#ibcon#end of sib2, iclass 33, count 0 2006.182.08:13:01.27#ibcon#*after write, iclass 33, count 0 2006.182.08:13:01.27#ibcon#*before return 0, iclass 33, count 0 2006.182.08:13:01.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:13:01.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:13:01.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:13:01.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:13:01.27$vc4f8/vb=3,4 2006.182.08:13:01.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.182.08:13:01.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.182.08:13:01.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:13:01.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:13:01.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:13:01.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:13:01.33#ibcon#enter wrdev, iclass 35, count 2 2006.182.08:13:01.33#ibcon#first serial, iclass 35, count 2 2006.182.08:13:01.33#ibcon#enter sib2, iclass 35, count 2 2006.182.08:13:01.33#ibcon#flushed, iclass 35, count 2 2006.182.08:13:01.33#ibcon#about to write, iclass 35, count 2 2006.182.08:13:01.33#ibcon#wrote, iclass 35, count 2 2006.182.08:13:01.33#ibcon#about to read 3, iclass 35, count 2 2006.182.08:13:01.35#ibcon#read 3, iclass 35, count 2 2006.182.08:13:01.35#ibcon#about to read 4, iclass 35, count 2 2006.182.08:13:01.35#ibcon#read 4, iclass 35, count 2 2006.182.08:13:01.35#ibcon#about to read 5, iclass 35, count 2 2006.182.08:13:01.35#ibcon#read 5, iclass 35, count 2 2006.182.08:13:01.35#ibcon#about to read 6, iclass 35, count 2 2006.182.08:13:01.35#ibcon#read 6, iclass 35, count 2 2006.182.08:13:01.35#ibcon#end of sib2, iclass 35, count 2 2006.182.08:13:01.35#ibcon#*mode == 0, iclass 35, count 2 2006.182.08:13:01.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.182.08:13:01.35#ibcon#[27=AT03-04\r\n] 2006.182.08:13:01.35#ibcon#*before write, iclass 35, count 2 2006.182.08:13:01.35#ibcon#enter sib2, iclass 35, count 2 2006.182.08:13:01.35#ibcon#flushed, iclass 35, count 2 2006.182.08:13:01.35#ibcon#about to write, iclass 35, count 2 2006.182.08:13:01.35#ibcon#wrote, iclass 35, count 2 2006.182.08:13:01.35#ibcon#about to read 3, iclass 35, count 2 2006.182.08:13:01.38#ibcon#read 3, iclass 35, count 2 2006.182.08:13:01.38#ibcon#about to read 4, iclass 35, count 2 2006.182.08:13:01.38#ibcon#read 4, iclass 35, count 2 2006.182.08:13:01.38#ibcon#about to read 5, iclass 35, count 2 2006.182.08:13:01.38#ibcon#read 5, iclass 35, count 2 2006.182.08:13:01.38#ibcon#about to read 6, iclass 35, count 2 2006.182.08:13:01.38#ibcon#read 6, iclass 35, count 2 2006.182.08:13:01.38#ibcon#end of sib2, iclass 35, count 2 2006.182.08:13:01.38#ibcon#*after write, iclass 35, count 2 2006.182.08:13:01.38#ibcon#*before return 0, iclass 35, count 2 2006.182.08:13:01.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:13:01.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:13:01.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.182.08:13:01.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:13:01.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:13:01.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:13:01.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:13:01.50#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:13:01.50#ibcon#first serial, iclass 35, count 0 2006.182.08:13:01.50#ibcon#enter sib2, iclass 35, count 0 2006.182.08:13:01.50#ibcon#flushed, iclass 35, count 0 2006.182.08:13:01.50#ibcon#about to write, iclass 35, count 0 2006.182.08:13:01.50#ibcon#wrote, iclass 35, count 0 2006.182.08:13:01.50#ibcon#about to read 3, iclass 35, count 0 2006.182.08:13:01.52#ibcon#read 3, iclass 35, count 0 2006.182.08:13:01.52#ibcon#about to read 4, iclass 35, count 0 2006.182.08:13:01.52#ibcon#read 4, iclass 35, count 0 2006.182.08:13:01.52#ibcon#about to read 5, iclass 35, count 0 2006.182.08:13:01.52#ibcon#read 5, iclass 35, count 0 2006.182.08:13:01.52#ibcon#about to read 6, iclass 35, count 0 2006.182.08:13:01.52#ibcon#read 6, iclass 35, count 0 2006.182.08:13:01.52#ibcon#end of sib2, iclass 35, count 0 2006.182.08:13:01.52#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:13:01.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:13:01.52#ibcon#[27=USB\r\n] 2006.182.08:13:01.52#ibcon#*before write, iclass 35, count 0 2006.182.08:13:01.52#ibcon#enter sib2, iclass 35, count 0 2006.182.08:13:01.52#ibcon#flushed, iclass 35, count 0 2006.182.08:13:01.52#ibcon#about to write, iclass 35, count 0 2006.182.08:13:01.52#ibcon#wrote, iclass 35, count 0 2006.182.08:13:01.52#ibcon#about to read 3, iclass 35, count 0 2006.182.08:13:01.55#ibcon#read 3, iclass 35, count 0 2006.182.08:13:01.55#ibcon#about to read 4, iclass 35, count 0 2006.182.08:13:01.55#ibcon#read 4, iclass 35, count 0 2006.182.08:13:01.55#ibcon#about to read 5, iclass 35, count 0 2006.182.08:13:01.55#ibcon#read 5, iclass 35, count 0 2006.182.08:13:01.55#ibcon#about to read 6, iclass 35, count 0 2006.182.08:13:01.55#ibcon#read 6, iclass 35, count 0 2006.182.08:13:01.55#ibcon#end of sib2, iclass 35, count 0 2006.182.08:13:01.55#ibcon#*after write, iclass 35, count 0 2006.182.08:13:01.55#ibcon#*before return 0, iclass 35, count 0 2006.182.08:13:01.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:13:01.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:13:01.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:13:01.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:13:01.55$vc4f8/vblo=4,712.99 2006.182.08:13:01.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.182.08:13:01.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.182.08:13:01.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:13:01.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:13:01.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:13:01.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:13:01.55#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:13:01.55#ibcon#first serial, iclass 37, count 0 2006.182.08:13:01.55#ibcon#enter sib2, iclass 37, count 0 2006.182.08:13:01.55#ibcon#flushed, iclass 37, count 0 2006.182.08:13:01.55#ibcon#about to write, iclass 37, count 0 2006.182.08:13:01.55#ibcon#wrote, iclass 37, count 0 2006.182.08:13:01.55#ibcon#about to read 3, iclass 37, count 0 2006.182.08:13:01.57#ibcon#read 3, iclass 37, count 0 2006.182.08:13:01.57#ibcon#about to read 4, iclass 37, count 0 2006.182.08:13:01.57#ibcon#read 4, iclass 37, count 0 2006.182.08:13:01.57#ibcon#about to read 5, iclass 37, count 0 2006.182.08:13:01.57#ibcon#read 5, iclass 37, count 0 2006.182.08:13:01.57#ibcon#about to read 6, iclass 37, count 0 2006.182.08:13:01.57#ibcon#read 6, iclass 37, count 0 2006.182.08:13:01.57#ibcon#end of sib2, iclass 37, count 0 2006.182.08:13:01.57#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:13:01.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:13:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:13:01.57#ibcon#*before write, iclass 37, count 0 2006.182.08:13:01.57#ibcon#enter sib2, iclass 37, count 0 2006.182.08:13:01.57#ibcon#flushed, iclass 37, count 0 2006.182.08:13:01.57#ibcon#about to write, iclass 37, count 0 2006.182.08:13:01.57#ibcon#wrote, iclass 37, count 0 2006.182.08:13:01.57#ibcon#about to read 3, iclass 37, count 0 2006.182.08:13:01.61#ibcon#read 3, iclass 37, count 0 2006.182.08:13:01.61#ibcon#about to read 4, iclass 37, count 0 2006.182.08:13:01.61#ibcon#read 4, iclass 37, count 0 2006.182.08:13:01.61#ibcon#about to read 5, iclass 37, count 0 2006.182.08:13:01.61#ibcon#read 5, iclass 37, count 0 2006.182.08:13:01.61#ibcon#about to read 6, iclass 37, count 0 2006.182.08:13:01.61#ibcon#read 6, iclass 37, count 0 2006.182.08:13:01.61#ibcon#end of sib2, iclass 37, count 0 2006.182.08:13:01.61#ibcon#*after write, iclass 37, count 0 2006.182.08:13:01.61#ibcon#*before return 0, iclass 37, count 0 2006.182.08:13:01.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:13:01.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:13:01.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:13:01.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:13:01.61$vc4f8/vb=4,4 2006.182.08:13:01.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.08:13:01.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.08:13:01.61#ibcon#ireg 11 cls_cnt 2 2006.182.08:13:01.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:13:01.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:13:01.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:13:01.67#ibcon#enter wrdev, iclass 39, count 2 2006.182.08:13:01.67#ibcon#first serial, iclass 39, count 2 2006.182.08:13:01.67#ibcon#enter sib2, iclass 39, count 2 2006.182.08:13:01.67#ibcon#flushed, iclass 39, count 2 2006.182.08:13:01.67#ibcon#about to write, iclass 39, count 2 2006.182.08:13:01.67#ibcon#wrote, iclass 39, count 2 2006.182.08:13:01.67#ibcon#about to read 3, iclass 39, count 2 2006.182.08:13:01.69#ibcon#read 3, iclass 39, count 2 2006.182.08:13:01.69#ibcon#about to read 4, iclass 39, count 2 2006.182.08:13:01.69#ibcon#read 4, iclass 39, count 2 2006.182.08:13:01.69#ibcon#about to read 5, iclass 39, count 2 2006.182.08:13:01.69#ibcon#read 5, iclass 39, count 2 2006.182.08:13:01.69#ibcon#about to read 6, iclass 39, count 2 2006.182.08:13:01.69#ibcon#read 6, iclass 39, count 2 2006.182.08:13:01.69#ibcon#end of sib2, iclass 39, count 2 2006.182.08:13:01.69#ibcon#*mode == 0, iclass 39, count 2 2006.182.08:13:01.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.08:13:01.69#ibcon#[27=AT04-04\r\n] 2006.182.08:13:01.69#ibcon#*before write, iclass 39, count 2 2006.182.08:13:01.69#ibcon#enter sib2, iclass 39, count 2 2006.182.08:13:01.69#ibcon#flushed, iclass 39, count 2 2006.182.08:13:01.69#ibcon#about to write, iclass 39, count 2 2006.182.08:13:01.69#ibcon#wrote, iclass 39, count 2 2006.182.08:13:01.69#ibcon#about to read 3, iclass 39, count 2 2006.182.08:13:01.72#ibcon#read 3, iclass 39, count 2 2006.182.08:13:01.72#ibcon#about to read 4, iclass 39, count 2 2006.182.08:13:01.72#ibcon#read 4, iclass 39, count 2 2006.182.08:13:01.72#ibcon#about to read 5, iclass 39, count 2 2006.182.08:13:01.72#ibcon#read 5, iclass 39, count 2 2006.182.08:13:01.72#ibcon#about to read 6, iclass 39, count 2 2006.182.08:13:01.72#ibcon#read 6, iclass 39, count 2 2006.182.08:13:01.72#ibcon#end of sib2, iclass 39, count 2 2006.182.08:13:01.72#ibcon#*after write, iclass 39, count 2 2006.182.08:13:01.72#ibcon#*before return 0, iclass 39, count 2 2006.182.08:13:01.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:13:01.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:13:01.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.08:13:01.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:13:01.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:13:01.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:13:01.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:13:01.84#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:13:01.84#ibcon#first serial, iclass 39, count 0 2006.182.08:13:01.84#ibcon#enter sib2, iclass 39, count 0 2006.182.08:13:01.84#ibcon#flushed, iclass 39, count 0 2006.182.08:13:01.84#ibcon#about to write, iclass 39, count 0 2006.182.08:13:01.84#ibcon#wrote, iclass 39, count 0 2006.182.08:13:01.84#ibcon#about to read 3, iclass 39, count 0 2006.182.08:13:01.86#ibcon#read 3, iclass 39, count 0 2006.182.08:13:01.86#ibcon#about to read 4, iclass 39, count 0 2006.182.08:13:01.86#ibcon#read 4, iclass 39, count 0 2006.182.08:13:01.86#ibcon#about to read 5, iclass 39, count 0 2006.182.08:13:01.86#ibcon#read 5, iclass 39, count 0 2006.182.08:13:01.86#ibcon#about to read 6, iclass 39, count 0 2006.182.08:13:01.86#ibcon#read 6, iclass 39, count 0 2006.182.08:13:01.86#ibcon#end of sib2, iclass 39, count 0 2006.182.08:13:01.86#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:13:01.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:13:01.86#ibcon#[27=USB\r\n] 2006.182.08:13:01.86#ibcon#*before write, iclass 39, count 0 2006.182.08:13:01.86#ibcon#enter sib2, iclass 39, count 0 2006.182.08:13:01.86#ibcon#flushed, iclass 39, count 0 2006.182.08:13:01.86#ibcon#about to write, iclass 39, count 0 2006.182.08:13:01.86#ibcon#wrote, iclass 39, count 0 2006.182.08:13:01.86#ibcon#about to read 3, iclass 39, count 0 2006.182.08:13:01.89#ibcon#read 3, iclass 39, count 0 2006.182.08:13:01.89#ibcon#about to read 4, iclass 39, count 0 2006.182.08:13:01.89#ibcon#read 4, iclass 39, count 0 2006.182.08:13:01.89#ibcon#about to read 5, iclass 39, count 0 2006.182.08:13:01.89#ibcon#read 5, iclass 39, count 0 2006.182.08:13:01.89#ibcon#about to read 6, iclass 39, count 0 2006.182.08:13:01.89#ibcon#read 6, iclass 39, count 0 2006.182.08:13:01.89#ibcon#end of sib2, iclass 39, count 0 2006.182.08:13:01.89#ibcon#*after write, iclass 39, count 0 2006.182.08:13:01.89#ibcon#*before return 0, iclass 39, count 0 2006.182.08:13:01.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:13:01.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:13:01.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:13:01.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:13:01.89$vc4f8/vblo=5,744.99 2006.182.08:13:01.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.08:13:01.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.08:13:01.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:13:01.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:13:01.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:13:01.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:13:01.89#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:13:01.89#ibcon#first serial, iclass 3, count 0 2006.182.08:13:01.89#ibcon#enter sib2, iclass 3, count 0 2006.182.08:13:01.89#ibcon#flushed, iclass 3, count 0 2006.182.08:13:01.89#ibcon#about to write, iclass 3, count 0 2006.182.08:13:01.89#ibcon#wrote, iclass 3, count 0 2006.182.08:13:01.89#ibcon#about to read 3, iclass 3, count 0 2006.182.08:13:01.91#ibcon#read 3, iclass 3, count 0 2006.182.08:13:01.91#ibcon#about to read 4, iclass 3, count 0 2006.182.08:13:01.91#ibcon#read 4, iclass 3, count 0 2006.182.08:13:01.91#ibcon#about to read 5, iclass 3, count 0 2006.182.08:13:01.91#ibcon#read 5, iclass 3, count 0 2006.182.08:13:01.91#ibcon#about to read 6, iclass 3, count 0 2006.182.08:13:01.91#ibcon#read 6, iclass 3, count 0 2006.182.08:13:01.91#ibcon#end of sib2, iclass 3, count 0 2006.182.08:13:01.91#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:13:01.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:13:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:13:01.91#ibcon#*before write, iclass 3, count 0 2006.182.08:13:01.91#ibcon#enter sib2, iclass 3, count 0 2006.182.08:13:01.91#ibcon#flushed, iclass 3, count 0 2006.182.08:13:01.91#ibcon#about to write, iclass 3, count 0 2006.182.08:13:01.91#ibcon#wrote, iclass 3, count 0 2006.182.08:13:01.91#ibcon#about to read 3, iclass 3, count 0 2006.182.08:13:01.95#ibcon#read 3, iclass 3, count 0 2006.182.08:13:01.95#ibcon#about to read 4, iclass 3, count 0 2006.182.08:13:01.95#ibcon#read 4, iclass 3, count 0 2006.182.08:13:01.95#ibcon#about to read 5, iclass 3, count 0 2006.182.08:13:01.95#ibcon#read 5, iclass 3, count 0 2006.182.08:13:01.95#ibcon#about to read 6, iclass 3, count 0 2006.182.08:13:01.95#ibcon#read 6, iclass 3, count 0 2006.182.08:13:01.95#ibcon#end of sib2, iclass 3, count 0 2006.182.08:13:01.95#ibcon#*after write, iclass 3, count 0 2006.182.08:13:01.95#ibcon#*before return 0, iclass 3, count 0 2006.182.08:13:01.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:13:01.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:13:01.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:13:01.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:13:01.95$vc4f8/vb=5,4 2006.182.08:13:01.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.08:13:01.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.08:13:01.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:13:01.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:13:02.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:13:02.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:13:02.01#ibcon#enter wrdev, iclass 5, count 2 2006.182.08:13:02.01#ibcon#first serial, iclass 5, count 2 2006.182.08:13:02.01#ibcon#enter sib2, iclass 5, count 2 2006.182.08:13:02.01#ibcon#flushed, iclass 5, count 2 2006.182.08:13:02.01#ibcon#about to write, iclass 5, count 2 2006.182.08:13:02.01#ibcon#wrote, iclass 5, count 2 2006.182.08:13:02.01#ibcon#about to read 3, iclass 5, count 2 2006.182.08:13:02.03#ibcon#read 3, iclass 5, count 2 2006.182.08:13:02.03#ibcon#about to read 4, iclass 5, count 2 2006.182.08:13:02.03#ibcon#read 4, iclass 5, count 2 2006.182.08:13:02.03#ibcon#about to read 5, iclass 5, count 2 2006.182.08:13:02.03#ibcon#read 5, iclass 5, count 2 2006.182.08:13:02.03#ibcon#about to read 6, iclass 5, count 2 2006.182.08:13:02.03#ibcon#read 6, iclass 5, count 2 2006.182.08:13:02.03#ibcon#end of sib2, iclass 5, count 2 2006.182.08:13:02.03#ibcon#*mode == 0, iclass 5, count 2 2006.182.08:13:02.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.08:13:02.03#ibcon#[27=AT05-04\r\n] 2006.182.08:13:02.03#ibcon#*before write, iclass 5, count 2 2006.182.08:13:02.03#ibcon#enter sib2, iclass 5, count 2 2006.182.08:13:02.03#ibcon#flushed, iclass 5, count 2 2006.182.08:13:02.03#ibcon#about to write, iclass 5, count 2 2006.182.08:13:02.03#ibcon#wrote, iclass 5, count 2 2006.182.08:13:02.03#ibcon#about to read 3, iclass 5, count 2 2006.182.08:13:02.06#ibcon#read 3, iclass 5, count 2 2006.182.08:13:02.06#ibcon#about to read 4, iclass 5, count 2 2006.182.08:13:02.06#ibcon#read 4, iclass 5, count 2 2006.182.08:13:02.06#ibcon#about to read 5, iclass 5, count 2 2006.182.08:13:02.06#ibcon#read 5, iclass 5, count 2 2006.182.08:13:02.06#ibcon#about to read 6, iclass 5, count 2 2006.182.08:13:02.06#ibcon#read 6, iclass 5, count 2 2006.182.08:13:02.06#ibcon#end of sib2, iclass 5, count 2 2006.182.08:13:02.06#ibcon#*after write, iclass 5, count 2 2006.182.08:13:02.06#ibcon#*before return 0, iclass 5, count 2 2006.182.08:13:02.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:13:02.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:13:02.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.08:13:02.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:13:02.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:13:02.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:13:02.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:13:02.18#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:13:02.18#ibcon#first serial, iclass 5, count 0 2006.182.08:13:02.18#ibcon#enter sib2, iclass 5, count 0 2006.182.08:13:02.18#ibcon#flushed, iclass 5, count 0 2006.182.08:13:02.18#ibcon#about to write, iclass 5, count 0 2006.182.08:13:02.18#ibcon#wrote, iclass 5, count 0 2006.182.08:13:02.18#ibcon#about to read 3, iclass 5, count 0 2006.182.08:13:02.22#ibcon#read 3, iclass 5, count 0 2006.182.08:13:02.22#ibcon#about to read 4, iclass 5, count 0 2006.182.08:13:02.22#ibcon#read 4, iclass 5, count 0 2006.182.08:13:02.22#ibcon#about to read 5, iclass 5, count 0 2006.182.08:13:02.22#ibcon#read 5, iclass 5, count 0 2006.182.08:13:02.22#ibcon#about to read 6, iclass 5, count 0 2006.182.08:13:02.22#ibcon#read 6, iclass 5, count 0 2006.182.08:13:02.22#ibcon#end of sib2, iclass 5, count 0 2006.182.08:13:02.22#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:13:02.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:13:02.22#ibcon#[27=USB\r\n] 2006.182.08:13:02.22#ibcon#*before write, iclass 5, count 0 2006.182.08:13:02.22#ibcon#enter sib2, iclass 5, count 0 2006.182.08:13:02.22#ibcon#flushed, iclass 5, count 0 2006.182.08:13:02.22#ibcon#about to write, iclass 5, count 0 2006.182.08:13:02.22#ibcon#wrote, iclass 5, count 0 2006.182.08:13:02.22#ibcon#about to read 3, iclass 5, count 0 2006.182.08:13:02.24#ibcon#read 3, iclass 5, count 0 2006.182.08:13:02.24#ibcon#about to read 4, iclass 5, count 0 2006.182.08:13:02.24#ibcon#read 4, iclass 5, count 0 2006.182.08:13:02.24#ibcon#about to read 5, iclass 5, count 0 2006.182.08:13:02.24#ibcon#read 5, iclass 5, count 0 2006.182.08:13:02.24#ibcon#about to read 6, iclass 5, count 0 2006.182.08:13:02.24#ibcon#read 6, iclass 5, count 0 2006.182.08:13:02.24#ibcon#end of sib2, iclass 5, count 0 2006.182.08:13:02.24#ibcon#*after write, iclass 5, count 0 2006.182.08:13:02.24#ibcon#*before return 0, iclass 5, count 0 2006.182.08:13:02.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:13:02.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:13:02.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:13:02.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:13:02.24$vc4f8/vblo=6,752.99 2006.182.08:13:02.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.08:13:02.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.08:13:02.24#ibcon#ireg 17 cls_cnt 0 2006.182.08:13:02.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:13:02.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:13:02.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:13:02.24#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:13:02.24#ibcon#first serial, iclass 7, count 0 2006.182.08:13:02.24#ibcon#enter sib2, iclass 7, count 0 2006.182.08:13:02.24#ibcon#flushed, iclass 7, count 0 2006.182.08:13:02.24#ibcon#about to write, iclass 7, count 0 2006.182.08:13:02.24#ibcon#wrote, iclass 7, count 0 2006.182.08:13:02.24#ibcon#about to read 3, iclass 7, count 0 2006.182.08:13:02.26#ibcon#read 3, iclass 7, count 0 2006.182.08:13:02.26#ibcon#about to read 4, iclass 7, count 0 2006.182.08:13:02.26#ibcon#read 4, iclass 7, count 0 2006.182.08:13:02.26#ibcon#about to read 5, iclass 7, count 0 2006.182.08:13:02.26#ibcon#read 5, iclass 7, count 0 2006.182.08:13:02.26#ibcon#about to read 6, iclass 7, count 0 2006.182.08:13:02.26#ibcon#read 6, iclass 7, count 0 2006.182.08:13:02.26#ibcon#end of sib2, iclass 7, count 0 2006.182.08:13:02.26#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:13:02.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:13:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:13:02.26#ibcon#*before write, iclass 7, count 0 2006.182.08:13:02.26#ibcon#enter sib2, iclass 7, count 0 2006.182.08:13:02.26#ibcon#flushed, iclass 7, count 0 2006.182.08:13:02.26#ibcon#about to write, iclass 7, count 0 2006.182.08:13:02.26#ibcon#wrote, iclass 7, count 0 2006.182.08:13:02.26#ibcon#about to read 3, iclass 7, count 0 2006.182.08:13:02.30#ibcon#read 3, iclass 7, count 0 2006.182.08:13:02.30#ibcon#about to read 4, iclass 7, count 0 2006.182.08:13:02.30#ibcon#read 4, iclass 7, count 0 2006.182.08:13:02.30#ibcon#about to read 5, iclass 7, count 0 2006.182.08:13:02.30#ibcon#read 5, iclass 7, count 0 2006.182.08:13:02.30#ibcon#about to read 6, iclass 7, count 0 2006.182.08:13:02.30#ibcon#read 6, iclass 7, count 0 2006.182.08:13:02.30#ibcon#end of sib2, iclass 7, count 0 2006.182.08:13:02.30#ibcon#*after write, iclass 7, count 0 2006.182.08:13:02.30#ibcon#*before return 0, iclass 7, count 0 2006.182.08:13:02.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:13:02.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:13:02.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:13:02.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:13:02.30$vc4f8/vb=6,4 2006.182.08:13:02.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.08:13:02.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.08:13:02.30#ibcon#ireg 11 cls_cnt 2 2006.182.08:13:02.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:13:02.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:13:02.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:13:02.36#ibcon#enter wrdev, iclass 11, count 2 2006.182.08:13:02.36#ibcon#first serial, iclass 11, count 2 2006.182.08:13:02.36#ibcon#enter sib2, iclass 11, count 2 2006.182.08:13:02.36#ibcon#flushed, iclass 11, count 2 2006.182.08:13:02.36#ibcon#about to write, iclass 11, count 2 2006.182.08:13:02.36#ibcon#wrote, iclass 11, count 2 2006.182.08:13:02.36#ibcon#about to read 3, iclass 11, count 2 2006.182.08:13:02.38#ibcon#read 3, iclass 11, count 2 2006.182.08:13:02.38#ibcon#about to read 4, iclass 11, count 2 2006.182.08:13:02.38#ibcon#read 4, iclass 11, count 2 2006.182.08:13:02.38#ibcon#about to read 5, iclass 11, count 2 2006.182.08:13:02.38#ibcon#read 5, iclass 11, count 2 2006.182.08:13:02.38#ibcon#about to read 6, iclass 11, count 2 2006.182.08:13:02.38#ibcon#read 6, iclass 11, count 2 2006.182.08:13:02.38#ibcon#end of sib2, iclass 11, count 2 2006.182.08:13:02.38#ibcon#*mode == 0, iclass 11, count 2 2006.182.08:13:02.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.08:13:02.38#ibcon#[27=AT06-04\r\n] 2006.182.08:13:02.38#ibcon#*before write, iclass 11, count 2 2006.182.08:13:02.38#ibcon#enter sib2, iclass 11, count 2 2006.182.08:13:02.38#ibcon#flushed, iclass 11, count 2 2006.182.08:13:02.38#ibcon#about to write, iclass 11, count 2 2006.182.08:13:02.38#ibcon#wrote, iclass 11, count 2 2006.182.08:13:02.38#ibcon#about to read 3, iclass 11, count 2 2006.182.08:13:02.41#ibcon#read 3, iclass 11, count 2 2006.182.08:13:02.41#ibcon#about to read 4, iclass 11, count 2 2006.182.08:13:02.41#ibcon#read 4, iclass 11, count 2 2006.182.08:13:02.41#ibcon#about to read 5, iclass 11, count 2 2006.182.08:13:02.41#ibcon#read 5, iclass 11, count 2 2006.182.08:13:02.41#ibcon#about to read 6, iclass 11, count 2 2006.182.08:13:02.41#ibcon#read 6, iclass 11, count 2 2006.182.08:13:02.41#ibcon#end of sib2, iclass 11, count 2 2006.182.08:13:02.41#ibcon#*after write, iclass 11, count 2 2006.182.08:13:02.41#ibcon#*before return 0, iclass 11, count 2 2006.182.08:13:02.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:13:02.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:13:02.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.08:13:02.41#ibcon#ireg 7 cls_cnt 0 2006.182.08:13:02.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:13:02.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:13:02.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:13:02.53#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:13:02.53#ibcon#first serial, iclass 11, count 0 2006.182.08:13:02.53#ibcon#enter sib2, iclass 11, count 0 2006.182.08:13:02.53#ibcon#flushed, iclass 11, count 0 2006.182.08:13:02.53#ibcon#about to write, iclass 11, count 0 2006.182.08:13:02.53#ibcon#wrote, iclass 11, count 0 2006.182.08:13:02.53#ibcon#about to read 3, iclass 11, count 0 2006.182.08:13:02.55#ibcon#read 3, iclass 11, count 0 2006.182.08:13:02.55#ibcon#about to read 4, iclass 11, count 0 2006.182.08:13:02.55#ibcon#read 4, iclass 11, count 0 2006.182.08:13:02.55#ibcon#about to read 5, iclass 11, count 0 2006.182.08:13:02.55#ibcon#read 5, iclass 11, count 0 2006.182.08:13:02.55#ibcon#about to read 6, iclass 11, count 0 2006.182.08:13:02.55#ibcon#read 6, iclass 11, count 0 2006.182.08:13:02.55#ibcon#end of sib2, iclass 11, count 0 2006.182.08:13:02.55#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:13:02.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:13:02.55#ibcon#[27=USB\r\n] 2006.182.08:13:02.55#ibcon#*before write, iclass 11, count 0 2006.182.08:13:02.55#ibcon#enter sib2, iclass 11, count 0 2006.182.08:13:02.55#ibcon#flushed, iclass 11, count 0 2006.182.08:13:02.55#ibcon#about to write, iclass 11, count 0 2006.182.08:13:02.55#ibcon#wrote, iclass 11, count 0 2006.182.08:13:02.55#ibcon#about to read 3, iclass 11, count 0 2006.182.08:13:02.58#ibcon#read 3, iclass 11, count 0 2006.182.08:13:02.58#ibcon#about to read 4, iclass 11, count 0 2006.182.08:13:02.58#ibcon#read 4, iclass 11, count 0 2006.182.08:13:02.58#ibcon#about to read 5, iclass 11, count 0 2006.182.08:13:02.58#ibcon#read 5, iclass 11, count 0 2006.182.08:13:02.58#ibcon#about to read 6, iclass 11, count 0 2006.182.08:13:02.58#ibcon#read 6, iclass 11, count 0 2006.182.08:13:02.58#ibcon#end of sib2, iclass 11, count 0 2006.182.08:13:02.58#ibcon#*after write, iclass 11, count 0 2006.182.08:13:02.58#ibcon#*before return 0, iclass 11, count 0 2006.182.08:13:02.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:13:02.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:13:02.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:13:02.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:13:02.58$vc4f8/vabw=wide 2006.182.08:13:02.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.08:13:02.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.08:13:02.58#ibcon#ireg 8 cls_cnt 0 2006.182.08:13:02.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:13:02.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:13:02.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:13:02.58#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:13:02.58#ibcon#first serial, iclass 13, count 0 2006.182.08:13:02.58#ibcon#enter sib2, iclass 13, count 0 2006.182.08:13:02.58#ibcon#flushed, iclass 13, count 0 2006.182.08:13:02.58#ibcon#about to write, iclass 13, count 0 2006.182.08:13:02.58#ibcon#wrote, iclass 13, count 0 2006.182.08:13:02.58#ibcon#about to read 3, iclass 13, count 0 2006.182.08:13:02.60#ibcon#read 3, iclass 13, count 0 2006.182.08:13:02.60#ibcon#about to read 4, iclass 13, count 0 2006.182.08:13:02.60#ibcon#read 4, iclass 13, count 0 2006.182.08:13:02.60#ibcon#about to read 5, iclass 13, count 0 2006.182.08:13:02.60#ibcon#read 5, iclass 13, count 0 2006.182.08:13:02.60#ibcon#about to read 6, iclass 13, count 0 2006.182.08:13:02.60#ibcon#read 6, iclass 13, count 0 2006.182.08:13:02.60#ibcon#end of sib2, iclass 13, count 0 2006.182.08:13:02.60#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:13:02.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:13:02.60#ibcon#[25=BW32\r\n] 2006.182.08:13:02.60#ibcon#*before write, iclass 13, count 0 2006.182.08:13:02.60#ibcon#enter sib2, iclass 13, count 0 2006.182.08:13:02.60#ibcon#flushed, iclass 13, count 0 2006.182.08:13:02.60#ibcon#about to write, iclass 13, count 0 2006.182.08:13:02.60#ibcon#wrote, iclass 13, count 0 2006.182.08:13:02.60#ibcon#about to read 3, iclass 13, count 0 2006.182.08:13:02.63#ibcon#read 3, iclass 13, count 0 2006.182.08:13:02.63#ibcon#about to read 4, iclass 13, count 0 2006.182.08:13:02.63#ibcon#read 4, iclass 13, count 0 2006.182.08:13:02.63#ibcon#about to read 5, iclass 13, count 0 2006.182.08:13:02.63#ibcon#read 5, iclass 13, count 0 2006.182.08:13:02.63#ibcon#about to read 6, iclass 13, count 0 2006.182.08:13:02.63#ibcon#read 6, iclass 13, count 0 2006.182.08:13:02.63#ibcon#end of sib2, iclass 13, count 0 2006.182.08:13:02.63#ibcon#*after write, iclass 13, count 0 2006.182.08:13:02.63#ibcon#*before return 0, iclass 13, count 0 2006.182.08:13:02.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:13:02.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:13:02.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:13:02.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:13:02.63$vc4f8/vbbw=wide 2006.182.08:13:02.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.08:13:02.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.08:13:02.63#ibcon#ireg 8 cls_cnt 0 2006.182.08:13:02.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:13:02.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:13:02.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:13:02.70#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:13:02.70#ibcon#first serial, iclass 15, count 0 2006.182.08:13:02.70#ibcon#enter sib2, iclass 15, count 0 2006.182.08:13:02.70#ibcon#flushed, iclass 15, count 0 2006.182.08:13:02.70#ibcon#about to write, iclass 15, count 0 2006.182.08:13:02.70#ibcon#wrote, iclass 15, count 0 2006.182.08:13:02.70#ibcon#about to read 3, iclass 15, count 0 2006.182.08:13:02.72#ibcon#read 3, iclass 15, count 0 2006.182.08:13:02.72#ibcon#about to read 4, iclass 15, count 0 2006.182.08:13:02.72#ibcon#read 4, iclass 15, count 0 2006.182.08:13:02.72#ibcon#about to read 5, iclass 15, count 0 2006.182.08:13:02.72#ibcon#read 5, iclass 15, count 0 2006.182.08:13:02.72#ibcon#about to read 6, iclass 15, count 0 2006.182.08:13:02.72#ibcon#read 6, iclass 15, count 0 2006.182.08:13:02.72#ibcon#end of sib2, iclass 15, count 0 2006.182.08:13:02.72#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:13:02.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:13:02.72#ibcon#[27=BW32\r\n] 2006.182.08:13:02.72#ibcon#*before write, iclass 15, count 0 2006.182.08:13:02.72#ibcon#enter sib2, iclass 15, count 0 2006.182.08:13:02.72#ibcon#flushed, iclass 15, count 0 2006.182.08:13:02.72#ibcon#about to write, iclass 15, count 0 2006.182.08:13:02.72#ibcon#wrote, iclass 15, count 0 2006.182.08:13:02.72#ibcon#about to read 3, iclass 15, count 0 2006.182.08:13:02.75#ibcon#read 3, iclass 15, count 0 2006.182.08:13:02.75#ibcon#about to read 4, iclass 15, count 0 2006.182.08:13:02.75#ibcon#read 4, iclass 15, count 0 2006.182.08:13:02.75#ibcon#about to read 5, iclass 15, count 0 2006.182.08:13:02.75#ibcon#read 5, iclass 15, count 0 2006.182.08:13:02.75#ibcon#about to read 6, iclass 15, count 0 2006.182.08:13:02.75#ibcon#read 6, iclass 15, count 0 2006.182.08:13:02.75#ibcon#end of sib2, iclass 15, count 0 2006.182.08:13:02.75#ibcon#*after write, iclass 15, count 0 2006.182.08:13:02.75#ibcon#*before return 0, iclass 15, count 0 2006.182.08:13:02.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:13:02.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:13:02.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:13:02.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:13:02.75$4f8m12a/ifd4f 2006.182.08:13:02.75$ifd4f/lo= 2006.182.08:13:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:13:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:13:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:13:02.75$ifd4f/patch= 2006.182.08:13:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:13:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:13:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:13:02.75$4f8m12a/"form=m,16.000,1:2 2006.182.08:13:02.75$4f8m12a/"tpicd 2006.182.08:13:02.75$4f8m12a/echo=off 2006.182.08:13:02.75$4f8m12a/xlog=off 2006.182.08:13:02.75:!2006.182.08:13:30 2006.182.08:13:11.14#trakl#Source acquired 2006.182.08:13:12.14#flagr#flagr/antenna,acquired 2006.182.08:13:30.00:preob 2006.182.08:13:31.14/onsource/TRACKING 2006.182.08:13:31.14:!2006.182.08:13:40 2006.182.08:13:40.00:data_valid=on 2006.182.08:13:40.00:midob 2006.182.08:13:40.14/onsource/TRACKING 2006.182.08:13:40.14/wx/27.82,1002.8,80 2006.182.08:13:40.21/cable/+6.4635E-03 2006.182.08:13:41.30/va/01,08,usb,yes,29,31 2006.182.08:13:41.30/va/02,07,usb,yes,29,31 2006.182.08:13:41.30/va/03,06,usb,yes,31,31 2006.182.08:13:41.30/va/04,07,usb,yes,30,32 2006.182.08:13:41.30/va/05,07,usb,yes,32,33 2006.182.08:13:41.30/va/06,06,usb,yes,31,30 2006.182.08:13:41.30/va/07,06,usb,yes,31,31 2006.182.08:13:41.30/va/08,07,usb,yes,30,29 2006.182.08:13:41.53/valo/01,532.99,yes,locked 2006.182.08:13:41.53/valo/02,572.99,yes,locked 2006.182.08:13:41.53/valo/03,672.99,yes,locked 2006.182.08:13:41.53/valo/04,832.99,yes,locked 2006.182.08:13:41.53/valo/05,652.99,yes,locked 2006.182.08:13:41.53/valo/06,772.99,yes,locked 2006.182.08:13:41.53/valo/07,832.99,yes,locked 2006.182.08:13:41.53/valo/08,852.99,yes,locked 2006.182.08:13:42.62/vb/01,04,usb,yes,29,28 2006.182.08:13:42.62/vb/02,04,usb,yes,31,32 2006.182.08:13:42.62/vb/03,04,usb,yes,27,31 2006.182.08:13:42.62/vb/04,04,usb,yes,28,28 2006.182.08:13:42.62/vb/05,04,usb,yes,27,31 2006.182.08:13:42.62/vb/06,04,usb,yes,28,31 2006.182.08:13:42.62/vb/07,04,usb,yes,30,30 2006.182.08:13:42.62/vb/08,04,usb,yes,28,31 2006.182.08:13:42.85/vblo/01,632.99,yes,locked 2006.182.08:13:42.85/vblo/02,640.99,yes,locked 2006.182.08:13:42.85/vblo/03,656.99,yes,locked 2006.182.08:13:42.85/vblo/04,712.99,yes,locked 2006.182.08:13:42.85/vblo/05,744.99,yes,locked 2006.182.08:13:42.85/vblo/06,752.99,yes,locked 2006.182.08:13:42.85/vblo/07,734.99,yes,locked 2006.182.08:13:42.85/vblo/08,744.99,yes,locked 2006.182.08:13:43.00/vabw/8 2006.182.08:13:43.15/vbbw/8 2006.182.08:13:43.25/xfe/off,on,14.7 2006.182.08:13:43.64/ifatt/23,28,28,28 2006.182.08:13:44.08/fmout-gps/S +3.46E-07 2006.182.08:13:44.12:!2006.182.08:14:40 2006.182.08:14:40.00:data_valid=off 2006.182.08:14:40.00:postob 2006.182.08:14:40.20/cable/+6.4633E-03 2006.182.08:14:40.20/wx/27.82,1002.9,82 2006.182.08:14:41.07/fmout-gps/S +3.46E-07 2006.182.08:14:41.07:scan_name=182-0815,k06182,60 2006.182.08:14:41.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.182.08:14:41.14#flagr#flagr/antenna,new-source 2006.182.08:14:42.14:checkk5 2006.182.08:14:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:14:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:14:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:14:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:14:44.01/chk_obsdata//k5ts1/T1820813??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:14:44.38/chk_obsdata//k5ts2/T1820813??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:14:44.74/chk_obsdata//k5ts3/T1820813??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:14:45.11/chk_obsdata//k5ts4/T1820813??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:14:45.80/k5log//k5ts1_log_newline 2006.182.08:14:46.48/k5log//k5ts2_log_newline 2006.182.08:14:47.17/k5log//k5ts3_log_newline 2006.182.08:14:47.86/k5log//k5ts4_log_newline 2006.182.08:14:47.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:14:47.89:4f8m12a=2 2006.182.08:14:47.89$4f8m12a/echo=on 2006.182.08:14:47.89$4f8m12a/pcalon 2006.182.08:14:47.89$pcalon/"no phase cal control is implemented here 2006.182.08:14:47.89$4f8m12a/"tpicd=stop 2006.182.08:14:47.89$4f8m12a/vc4f8 2006.182.08:14:47.89$vc4f8/valo=1,532.99 2006.182.08:14:47.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.08:14:47.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.08:14:47.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:47.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:14:47.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:14:47.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:14:47.89#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:14:47.89#ibcon#first serial, iclass 25, count 0 2006.182.08:14:47.89#ibcon#enter sib2, iclass 25, count 0 2006.182.08:14:47.89#ibcon#flushed, iclass 25, count 0 2006.182.08:14:47.89#ibcon#about to write, iclass 25, count 0 2006.182.08:14:47.89#ibcon#wrote, iclass 25, count 0 2006.182.08:14:47.89#ibcon#about to read 3, iclass 25, count 0 2006.182.08:14:47.93#ibcon#read 3, iclass 25, count 0 2006.182.08:14:47.93#ibcon#about to read 4, iclass 25, count 0 2006.182.08:14:47.93#ibcon#read 4, iclass 25, count 0 2006.182.08:14:47.93#ibcon#about to read 5, iclass 25, count 0 2006.182.08:14:47.93#ibcon#read 5, iclass 25, count 0 2006.182.08:14:47.93#ibcon#about to read 6, iclass 25, count 0 2006.182.08:14:47.93#ibcon#read 6, iclass 25, count 0 2006.182.08:14:47.93#ibcon#end of sib2, iclass 25, count 0 2006.182.08:14:47.93#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:14:47.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:14:47.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:14:47.93#ibcon#*before write, iclass 25, count 0 2006.182.08:14:47.93#ibcon#enter sib2, iclass 25, count 0 2006.182.08:14:47.93#ibcon#flushed, iclass 25, count 0 2006.182.08:14:47.93#ibcon#about to write, iclass 25, count 0 2006.182.08:14:47.93#ibcon#wrote, iclass 25, count 0 2006.182.08:14:47.93#ibcon#about to read 3, iclass 25, count 0 2006.182.08:14:47.96#abcon#[5=S1D000X0/0*\r\n] 2006.182.08:14:47.98#ibcon#read 3, iclass 25, count 0 2006.182.08:14:47.98#ibcon#about to read 4, iclass 25, count 0 2006.182.08:14:47.98#ibcon#read 4, iclass 25, count 0 2006.182.08:14:47.98#ibcon#about to read 5, iclass 25, count 0 2006.182.08:14:47.98#ibcon#read 5, iclass 25, count 0 2006.182.08:14:47.98#ibcon#about to read 6, iclass 25, count 0 2006.182.08:14:47.98#ibcon#read 6, iclass 25, count 0 2006.182.08:14:47.98#ibcon#end of sib2, iclass 25, count 0 2006.182.08:14:47.98#ibcon#*after write, iclass 25, count 0 2006.182.08:14:47.98#ibcon#*before return 0, iclass 25, count 0 2006.182.08:14:47.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:14:47.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:14:47.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:14:47.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:14:47.98$vc4f8/va=1,8 2006.182.08:14:47.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.08:14:47.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.08:14:47.98#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:47.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:47.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:47.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:47.98#ibcon#enter wrdev, iclass 28, count 2 2006.182.08:14:47.98#ibcon#first serial, iclass 28, count 2 2006.182.08:14:47.98#ibcon#enter sib2, iclass 28, count 2 2006.182.08:14:47.98#ibcon#flushed, iclass 28, count 2 2006.182.08:14:47.98#ibcon#about to write, iclass 28, count 2 2006.182.08:14:47.98#ibcon#wrote, iclass 28, count 2 2006.182.08:14:47.98#ibcon#about to read 3, iclass 28, count 2 2006.182.08:14:48.01#ibcon#read 3, iclass 28, count 2 2006.182.08:14:48.01#ibcon#about to read 4, iclass 28, count 2 2006.182.08:14:48.01#ibcon#read 4, iclass 28, count 2 2006.182.08:14:48.01#ibcon#about to read 5, iclass 28, count 2 2006.182.08:14:48.01#ibcon#read 5, iclass 28, count 2 2006.182.08:14:48.01#ibcon#about to read 6, iclass 28, count 2 2006.182.08:14:48.01#ibcon#read 6, iclass 28, count 2 2006.182.08:14:48.01#ibcon#end of sib2, iclass 28, count 2 2006.182.08:14:48.01#ibcon#*mode == 0, iclass 28, count 2 2006.182.08:14:48.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.08:14:48.01#ibcon#[25=AT01-08\r\n] 2006.182.08:14:48.01#ibcon#*before write, iclass 28, count 2 2006.182.08:14:48.01#ibcon#enter sib2, iclass 28, count 2 2006.182.08:14:48.01#ibcon#flushed, iclass 28, count 2 2006.182.08:14:48.01#ibcon#about to write, iclass 28, count 2 2006.182.08:14:48.01#ibcon#wrote, iclass 28, count 2 2006.182.08:14:48.01#ibcon#about to read 3, iclass 28, count 2 2006.182.08:14:48.04#ibcon#read 3, iclass 28, count 2 2006.182.08:14:48.04#ibcon#about to read 4, iclass 28, count 2 2006.182.08:14:48.04#ibcon#read 4, iclass 28, count 2 2006.182.08:14:48.04#ibcon#about to read 5, iclass 28, count 2 2006.182.08:14:48.04#ibcon#read 5, iclass 28, count 2 2006.182.08:14:48.04#ibcon#about to read 6, iclass 28, count 2 2006.182.08:14:48.04#ibcon#read 6, iclass 28, count 2 2006.182.08:14:48.04#ibcon#end of sib2, iclass 28, count 2 2006.182.08:14:48.04#ibcon#*after write, iclass 28, count 2 2006.182.08:14:48.04#ibcon#*before return 0, iclass 28, count 2 2006.182.08:14:48.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:48.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:48.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.08:14:48.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:48.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:48.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:48.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:48.16#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:14:48.16#ibcon#first serial, iclass 28, count 0 2006.182.08:14:48.16#ibcon#enter sib2, iclass 28, count 0 2006.182.08:14:48.16#ibcon#flushed, iclass 28, count 0 2006.182.08:14:48.16#ibcon#about to write, iclass 28, count 0 2006.182.08:14:48.16#ibcon#wrote, iclass 28, count 0 2006.182.08:14:48.16#ibcon#about to read 3, iclass 28, count 0 2006.182.08:14:48.18#ibcon#read 3, iclass 28, count 0 2006.182.08:14:48.18#ibcon#about to read 4, iclass 28, count 0 2006.182.08:14:48.18#ibcon#read 4, iclass 28, count 0 2006.182.08:14:48.18#ibcon#about to read 5, iclass 28, count 0 2006.182.08:14:48.18#ibcon#read 5, iclass 28, count 0 2006.182.08:14:48.18#ibcon#about to read 6, iclass 28, count 0 2006.182.08:14:48.18#ibcon#read 6, iclass 28, count 0 2006.182.08:14:48.18#ibcon#end of sib2, iclass 28, count 0 2006.182.08:14:48.18#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:14:48.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:14:48.18#ibcon#[25=USB\r\n] 2006.182.08:14:48.18#ibcon#*before write, iclass 28, count 0 2006.182.08:14:48.18#ibcon#enter sib2, iclass 28, count 0 2006.182.08:14:48.18#ibcon#flushed, iclass 28, count 0 2006.182.08:14:48.18#ibcon#about to write, iclass 28, count 0 2006.182.08:14:48.18#ibcon#wrote, iclass 28, count 0 2006.182.08:14:48.18#ibcon#about to read 3, iclass 28, count 0 2006.182.08:14:48.21#ibcon#read 3, iclass 28, count 0 2006.182.08:14:48.21#ibcon#about to read 4, iclass 28, count 0 2006.182.08:14:48.21#ibcon#read 4, iclass 28, count 0 2006.182.08:14:48.21#ibcon#about to read 5, iclass 28, count 0 2006.182.08:14:48.21#ibcon#read 5, iclass 28, count 0 2006.182.08:14:48.21#ibcon#about to read 6, iclass 28, count 0 2006.182.08:14:48.21#ibcon#read 6, iclass 28, count 0 2006.182.08:14:48.21#ibcon#end of sib2, iclass 28, count 0 2006.182.08:14:48.21#ibcon#*after write, iclass 28, count 0 2006.182.08:14:48.21#ibcon#*before return 0, iclass 28, count 0 2006.182.08:14:48.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:48.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:48.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:14:48.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:14:48.21$vc4f8/valo=2,572.99 2006.182.08:14:48.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.08:14:48.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.08:14:48.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:48.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:48.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:48.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:48.21#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:14:48.21#ibcon#first serial, iclass 30, count 0 2006.182.08:14:48.21#ibcon#enter sib2, iclass 30, count 0 2006.182.08:14:48.21#ibcon#flushed, iclass 30, count 0 2006.182.08:14:48.21#ibcon#about to write, iclass 30, count 0 2006.182.08:14:48.21#ibcon#wrote, iclass 30, count 0 2006.182.08:14:48.21#ibcon#about to read 3, iclass 30, count 0 2006.182.08:14:48.23#ibcon#read 3, iclass 30, count 0 2006.182.08:14:48.23#ibcon#about to read 4, iclass 30, count 0 2006.182.08:14:48.23#ibcon#read 4, iclass 30, count 0 2006.182.08:14:48.23#ibcon#about to read 5, iclass 30, count 0 2006.182.08:14:48.23#ibcon#read 5, iclass 30, count 0 2006.182.08:14:48.23#ibcon#about to read 6, iclass 30, count 0 2006.182.08:14:48.23#ibcon#read 6, iclass 30, count 0 2006.182.08:14:48.23#ibcon#end of sib2, iclass 30, count 0 2006.182.08:14:48.23#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:14:48.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:14:48.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:14:48.23#ibcon#*before write, iclass 30, count 0 2006.182.08:14:48.23#ibcon#enter sib2, iclass 30, count 0 2006.182.08:14:48.23#ibcon#flushed, iclass 30, count 0 2006.182.08:14:48.23#ibcon#about to write, iclass 30, count 0 2006.182.08:14:48.23#ibcon#wrote, iclass 30, count 0 2006.182.08:14:48.23#ibcon#about to read 3, iclass 30, count 0 2006.182.08:14:48.27#ibcon#read 3, iclass 30, count 0 2006.182.08:14:48.27#ibcon#about to read 4, iclass 30, count 0 2006.182.08:14:48.27#ibcon#read 4, iclass 30, count 0 2006.182.08:14:48.27#ibcon#about to read 5, iclass 30, count 0 2006.182.08:14:48.27#ibcon#read 5, iclass 30, count 0 2006.182.08:14:48.27#ibcon#about to read 6, iclass 30, count 0 2006.182.08:14:48.27#ibcon#read 6, iclass 30, count 0 2006.182.08:14:48.27#ibcon#end of sib2, iclass 30, count 0 2006.182.08:14:48.27#ibcon#*after write, iclass 30, count 0 2006.182.08:14:48.27#ibcon#*before return 0, iclass 30, count 0 2006.182.08:14:48.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:48.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:48.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:14:48.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:14:48.27$vc4f8/va=2,7 2006.182.08:14:48.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.08:14:48.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.08:14:48.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:48.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:48.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:48.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:48.33#ibcon#enter wrdev, iclass 32, count 2 2006.182.08:14:48.33#ibcon#first serial, iclass 32, count 2 2006.182.08:14:48.33#ibcon#enter sib2, iclass 32, count 2 2006.182.08:14:48.33#ibcon#flushed, iclass 32, count 2 2006.182.08:14:48.33#ibcon#about to write, iclass 32, count 2 2006.182.08:14:48.33#ibcon#wrote, iclass 32, count 2 2006.182.08:14:48.33#ibcon#about to read 3, iclass 32, count 2 2006.182.08:14:48.35#ibcon#read 3, iclass 32, count 2 2006.182.08:14:48.35#ibcon#about to read 4, iclass 32, count 2 2006.182.08:14:48.35#ibcon#read 4, iclass 32, count 2 2006.182.08:14:48.35#ibcon#about to read 5, iclass 32, count 2 2006.182.08:14:48.35#ibcon#read 5, iclass 32, count 2 2006.182.08:14:48.35#ibcon#about to read 6, iclass 32, count 2 2006.182.08:14:48.35#ibcon#read 6, iclass 32, count 2 2006.182.08:14:48.35#ibcon#end of sib2, iclass 32, count 2 2006.182.08:14:48.35#ibcon#*mode == 0, iclass 32, count 2 2006.182.08:14:48.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.08:14:48.35#ibcon#[25=AT02-07\r\n] 2006.182.08:14:48.35#ibcon#*before write, iclass 32, count 2 2006.182.08:14:48.35#ibcon#enter sib2, iclass 32, count 2 2006.182.08:14:48.35#ibcon#flushed, iclass 32, count 2 2006.182.08:14:48.35#ibcon#about to write, iclass 32, count 2 2006.182.08:14:48.35#ibcon#wrote, iclass 32, count 2 2006.182.08:14:48.35#ibcon#about to read 3, iclass 32, count 2 2006.182.08:14:48.38#ibcon#read 3, iclass 32, count 2 2006.182.08:14:48.38#ibcon#about to read 4, iclass 32, count 2 2006.182.08:14:48.38#ibcon#read 4, iclass 32, count 2 2006.182.08:14:48.38#ibcon#about to read 5, iclass 32, count 2 2006.182.08:14:48.38#ibcon#read 5, iclass 32, count 2 2006.182.08:14:48.38#ibcon#about to read 6, iclass 32, count 2 2006.182.08:14:48.38#ibcon#read 6, iclass 32, count 2 2006.182.08:14:48.38#ibcon#end of sib2, iclass 32, count 2 2006.182.08:14:48.38#ibcon#*after write, iclass 32, count 2 2006.182.08:14:48.38#ibcon#*before return 0, iclass 32, count 2 2006.182.08:14:48.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:48.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:48.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.08:14:48.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:48.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:48.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:48.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:48.51#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:14:48.51#ibcon#first serial, iclass 32, count 0 2006.182.08:14:48.51#ibcon#enter sib2, iclass 32, count 0 2006.182.08:14:48.51#ibcon#flushed, iclass 32, count 0 2006.182.08:14:48.51#ibcon#about to write, iclass 32, count 0 2006.182.08:14:48.51#ibcon#wrote, iclass 32, count 0 2006.182.08:14:48.51#ibcon#about to read 3, iclass 32, count 0 2006.182.08:14:48.52#ibcon#read 3, iclass 32, count 0 2006.182.08:14:48.52#ibcon#about to read 4, iclass 32, count 0 2006.182.08:14:48.52#ibcon#read 4, iclass 32, count 0 2006.182.08:14:48.52#ibcon#about to read 5, iclass 32, count 0 2006.182.08:14:48.52#ibcon#read 5, iclass 32, count 0 2006.182.08:14:48.52#ibcon#about to read 6, iclass 32, count 0 2006.182.08:14:48.52#ibcon#read 6, iclass 32, count 0 2006.182.08:14:48.52#ibcon#end of sib2, iclass 32, count 0 2006.182.08:14:48.52#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:14:48.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:14:48.52#ibcon#[25=USB\r\n] 2006.182.08:14:48.52#ibcon#*before write, iclass 32, count 0 2006.182.08:14:48.52#ibcon#enter sib2, iclass 32, count 0 2006.182.08:14:48.52#ibcon#flushed, iclass 32, count 0 2006.182.08:14:48.52#ibcon#about to write, iclass 32, count 0 2006.182.08:14:48.52#ibcon#wrote, iclass 32, count 0 2006.182.08:14:48.52#ibcon#about to read 3, iclass 32, count 0 2006.182.08:14:48.55#ibcon#read 3, iclass 32, count 0 2006.182.08:14:48.55#ibcon#about to read 4, iclass 32, count 0 2006.182.08:14:48.55#ibcon#read 4, iclass 32, count 0 2006.182.08:14:48.55#ibcon#about to read 5, iclass 32, count 0 2006.182.08:14:48.55#ibcon#read 5, iclass 32, count 0 2006.182.08:14:48.55#ibcon#about to read 6, iclass 32, count 0 2006.182.08:14:48.55#ibcon#read 6, iclass 32, count 0 2006.182.08:14:48.55#ibcon#end of sib2, iclass 32, count 0 2006.182.08:14:48.55#ibcon#*after write, iclass 32, count 0 2006.182.08:14:48.55#ibcon#*before return 0, iclass 32, count 0 2006.182.08:14:48.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:48.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:48.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:14:48.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:14:48.55$vc4f8/valo=3,672.99 2006.182.08:14:48.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.08:14:48.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.08:14:48.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:48.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:48.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:48.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:48.55#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:14:48.55#ibcon#first serial, iclass 34, count 0 2006.182.08:14:48.55#ibcon#enter sib2, iclass 34, count 0 2006.182.08:14:48.55#ibcon#flushed, iclass 34, count 0 2006.182.08:14:48.55#ibcon#about to write, iclass 34, count 0 2006.182.08:14:48.55#ibcon#wrote, iclass 34, count 0 2006.182.08:14:48.55#ibcon#about to read 3, iclass 34, count 0 2006.182.08:14:48.58#ibcon#read 3, iclass 34, count 0 2006.182.08:14:48.58#ibcon#about to read 4, iclass 34, count 0 2006.182.08:14:48.58#ibcon#read 4, iclass 34, count 0 2006.182.08:14:48.58#ibcon#about to read 5, iclass 34, count 0 2006.182.08:14:48.58#ibcon#read 5, iclass 34, count 0 2006.182.08:14:48.58#ibcon#about to read 6, iclass 34, count 0 2006.182.08:14:48.58#ibcon#read 6, iclass 34, count 0 2006.182.08:14:48.58#ibcon#end of sib2, iclass 34, count 0 2006.182.08:14:48.58#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:14:48.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:14:48.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:14:48.58#ibcon#*before write, iclass 34, count 0 2006.182.08:14:48.58#ibcon#enter sib2, iclass 34, count 0 2006.182.08:14:48.58#ibcon#flushed, iclass 34, count 0 2006.182.08:14:48.58#ibcon#about to write, iclass 34, count 0 2006.182.08:14:48.58#ibcon#wrote, iclass 34, count 0 2006.182.08:14:48.58#ibcon#about to read 3, iclass 34, count 0 2006.182.08:14:48.62#ibcon#read 3, iclass 34, count 0 2006.182.08:14:48.62#ibcon#about to read 4, iclass 34, count 0 2006.182.08:14:48.62#ibcon#read 4, iclass 34, count 0 2006.182.08:14:48.62#ibcon#about to read 5, iclass 34, count 0 2006.182.08:14:48.62#ibcon#read 5, iclass 34, count 0 2006.182.08:14:48.62#ibcon#about to read 6, iclass 34, count 0 2006.182.08:14:48.62#ibcon#read 6, iclass 34, count 0 2006.182.08:14:48.62#ibcon#end of sib2, iclass 34, count 0 2006.182.08:14:48.62#ibcon#*after write, iclass 34, count 0 2006.182.08:14:48.62#ibcon#*before return 0, iclass 34, count 0 2006.182.08:14:48.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:48.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:48.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:14:48.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:14:48.62$vc4f8/va=3,6 2006.182.08:14:48.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.182.08:14:48.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.182.08:14:48.62#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:48.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:48.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:48.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:48.67#ibcon#enter wrdev, iclass 36, count 2 2006.182.08:14:48.67#ibcon#first serial, iclass 36, count 2 2006.182.08:14:48.67#ibcon#enter sib2, iclass 36, count 2 2006.182.08:14:48.67#ibcon#flushed, iclass 36, count 2 2006.182.08:14:48.67#ibcon#about to write, iclass 36, count 2 2006.182.08:14:48.67#ibcon#wrote, iclass 36, count 2 2006.182.08:14:48.67#ibcon#about to read 3, iclass 36, count 2 2006.182.08:14:48.69#ibcon#read 3, iclass 36, count 2 2006.182.08:14:48.69#ibcon#about to read 4, iclass 36, count 2 2006.182.08:14:48.69#ibcon#read 4, iclass 36, count 2 2006.182.08:14:48.69#ibcon#about to read 5, iclass 36, count 2 2006.182.08:14:48.69#ibcon#read 5, iclass 36, count 2 2006.182.08:14:48.69#ibcon#about to read 6, iclass 36, count 2 2006.182.08:14:48.69#ibcon#read 6, iclass 36, count 2 2006.182.08:14:48.69#ibcon#end of sib2, iclass 36, count 2 2006.182.08:14:48.69#ibcon#*mode == 0, iclass 36, count 2 2006.182.08:14:48.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.182.08:14:48.69#ibcon#[25=AT03-06\r\n] 2006.182.08:14:48.69#ibcon#*before write, iclass 36, count 2 2006.182.08:14:48.69#ibcon#enter sib2, iclass 36, count 2 2006.182.08:14:48.69#ibcon#flushed, iclass 36, count 2 2006.182.08:14:48.69#ibcon#about to write, iclass 36, count 2 2006.182.08:14:48.69#ibcon#wrote, iclass 36, count 2 2006.182.08:14:48.69#ibcon#about to read 3, iclass 36, count 2 2006.182.08:14:48.72#ibcon#read 3, iclass 36, count 2 2006.182.08:14:48.72#ibcon#about to read 4, iclass 36, count 2 2006.182.08:14:48.72#ibcon#read 4, iclass 36, count 2 2006.182.08:14:48.72#ibcon#about to read 5, iclass 36, count 2 2006.182.08:14:48.72#ibcon#read 5, iclass 36, count 2 2006.182.08:14:48.72#ibcon#about to read 6, iclass 36, count 2 2006.182.08:14:48.72#ibcon#read 6, iclass 36, count 2 2006.182.08:14:48.72#ibcon#end of sib2, iclass 36, count 2 2006.182.08:14:48.72#ibcon#*after write, iclass 36, count 2 2006.182.08:14:48.72#ibcon#*before return 0, iclass 36, count 2 2006.182.08:14:48.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:48.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:48.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.182.08:14:48.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:48.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:48.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:48.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:48.84#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:14:48.84#ibcon#first serial, iclass 36, count 0 2006.182.08:14:48.84#ibcon#enter sib2, iclass 36, count 0 2006.182.08:14:48.84#ibcon#flushed, iclass 36, count 0 2006.182.08:14:48.84#ibcon#about to write, iclass 36, count 0 2006.182.08:14:48.84#ibcon#wrote, iclass 36, count 0 2006.182.08:14:48.84#ibcon#about to read 3, iclass 36, count 0 2006.182.08:14:48.86#ibcon#read 3, iclass 36, count 0 2006.182.08:14:48.86#ibcon#about to read 4, iclass 36, count 0 2006.182.08:14:48.86#ibcon#read 4, iclass 36, count 0 2006.182.08:14:48.86#ibcon#about to read 5, iclass 36, count 0 2006.182.08:14:48.86#ibcon#read 5, iclass 36, count 0 2006.182.08:14:48.86#ibcon#about to read 6, iclass 36, count 0 2006.182.08:14:48.86#ibcon#read 6, iclass 36, count 0 2006.182.08:14:48.86#ibcon#end of sib2, iclass 36, count 0 2006.182.08:14:48.86#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:14:48.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:14:48.86#ibcon#[25=USB\r\n] 2006.182.08:14:48.86#ibcon#*before write, iclass 36, count 0 2006.182.08:14:48.86#ibcon#enter sib2, iclass 36, count 0 2006.182.08:14:48.86#ibcon#flushed, iclass 36, count 0 2006.182.08:14:48.86#ibcon#about to write, iclass 36, count 0 2006.182.08:14:48.86#ibcon#wrote, iclass 36, count 0 2006.182.08:14:48.86#ibcon#about to read 3, iclass 36, count 0 2006.182.08:14:48.89#ibcon#read 3, iclass 36, count 0 2006.182.08:14:48.89#ibcon#about to read 4, iclass 36, count 0 2006.182.08:14:48.89#ibcon#read 4, iclass 36, count 0 2006.182.08:14:48.89#ibcon#about to read 5, iclass 36, count 0 2006.182.08:14:48.89#ibcon#read 5, iclass 36, count 0 2006.182.08:14:48.89#ibcon#about to read 6, iclass 36, count 0 2006.182.08:14:48.89#ibcon#read 6, iclass 36, count 0 2006.182.08:14:48.89#ibcon#end of sib2, iclass 36, count 0 2006.182.08:14:48.89#ibcon#*after write, iclass 36, count 0 2006.182.08:14:48.89#ibcon#*before return 0, iclass 36, count 0 2006.182.08:14:48.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:48.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:48.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:14:48.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:14:48.89$vc4f8/valo=4,832.99 2006.182.08:14:48.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.08:14:48.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.08:14:48.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:48.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:48.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:48.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:48.89#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:14:48.89#ibcon#first serial, iclass 38, count 0 2006.182.08:14:48.89#ibcon#enter sib2, iclass 38, count 0 2006.182.08:14:48.89#ibcon#flushed, iclass 38, count 0 2006.182.08:14:48.89#ibcon#about to write, iclass 38, count 0 2006.182.08:14:48.89#ibcon#wrote, iclass 38, count 0 2006.182.08:14:48.89#ibcon#about to read 3, iclass 38, count 0 2006.182.08:14:48.91#ibcon#read 3, iclass 38, count 0 2006.182.08:14:48.91#ibcon#about to read 4, iclass 38, count 0 2006.182.08:14:48.91#ibcon#read 4, iclass 38, count 0 2006.182.08:14:48.91#ibcon#about to read 5, iclass 38, count 0 2006.182.08:14:48.91#ibcon#read 5, iclass 38, count 0 2006.182.08:14:48.91#ibcon#about to read 6, iclass 38, count 0 2006.182.08:14:48.91#ibcon#read 6, iclass 38, count 0 2006.182.08:14:48.91#ibcon#end of sib2, iclass 38, count 0 2006.182.08:14:48.91#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:14:48.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:14:48.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:14:48.91#ibcon#*before write, iclass 38, count 0 2006.182.08:14:48.91#ibcon#enter sib2, iclass 38, count 0 2006.182.08:14:48.91#ibcon#flushed, iclass 38, count 0 2006.182.08:14:48.91#ibcon#about to write, iclass 38, count 0 2006.182.08:14:48.91#ibcon#wrote, iclass 38, count 0 2006.182.08:14:48.91#ibcon#about to read 3, iclass 38, count 0 2006.182.08:14:48.95#ibcon#read 3, iclass 38, count 0 2006.182.08:14:48.95#ibcon#about to read 4, iclass 38, count 0 2006.182.08:14:48.95#ibcon#read 4, iclass 38, count 0 2006.182.08:14:48.95#ibcon#about to read 5, iclass 38, count 0 2006.182.08:14:48.95#ibcon#read 5, iclass 38, count 0 2006.182.08:14:48.95#ibcon#about to read 6, iclass 38, count 0 2006.182.08:14:48.95#ibcon#read 6, iclass 38, count 0 2006.182.08:14:48.95#ibcon#end of sib2, iclass 38, count 0 2006.182.08:14:48.95#ibcon#*after write, iclass 38, count 0 2006.182.08:14:48.95#ibcon#*before return 0, iclass 38, count 0 2006.182.08:14:48.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:48.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:48.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:14:48.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:14:48.95$vc4f8/va=4,7 2006.182.08:14:48.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.08:14:48.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.08:14:48.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:48.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:49.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:49.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:49.01#ibcon#enter wrdev, iclass 40, count 2 2006.182.08:14:49.01#ibcon#first serial, iclass 40, count 2 2006.182.08:14:49.01#ibcon#enter sib2, iclass 40, count 2 2006.182.08:14:49.01#ibcon#flushed, iclass 40, count 2 2006.182.08:14:49.01#ibcon#about to write, iclass 40, count 2 2006.182.08:14:49.01#ibcon#wrote, iclass 40, count 2 2006.182.08:14:49.01#ibcon#about to read 3, iclass 40, count 2 2006.182.08:14:49.03#ibcon#read 3, iclass 40, count 2 2006.182.08:14:49.03#ibcon#about to read 4, iclass 40, count 2 2006.182.08:14:49.03#ibcon#read 4, iclass 40, count 2 2006.182.08:14:49.03#ibcon#about to read 5, iclass 40, count 2 2006.182.08:14:49.03#ibcon#read 5, iclass 40, count 2 2006.182.08:14:49.03#ibcon#about to read 6, iclass 40, count 2 2006.182.08:14:49.03#ibcon#read 6, iclass 40, count 2 2006.182.08:14:49.03#ibcon#end of sib2, iclass 40, count 2 2006.182.08:14:49.03#ibcon#*mode == 0, iclass 40, count 2 2006.182.08:14:49.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.08:14:49.03#ibcon#[25=AT04-07\r\n] 2006.182.08:14:49.03#ibcon#*before write, iclass 40, count 2 2006.182.08:14:49.03#ibcon#enter sib2, iclass 40, count 2 2006.182.08:14:49.03#ibcon#flushed, iclass 40, count 2 2006.182.08:14:49.03#ibcon#about to write, iclass 40, count 2 2006.182.08:14:49.03#ibcon#wrote, iclass 40, count 2 2006.182.08:14:49.03#ibcon#about to read 3, iclass 40, count 2 2006.182.08:14:49.06#ibcon#read 3, iclass 40, count 2 2006.182.08:14:49.06#ibcon#about to read 4, iclass 40, count 2 2006.182.08:14:49.06#ibcon#read 4, iclass 40, count 2 2006.182.08:14:49.06#ibcon#about to read 5, iclass 40, count 2 2006.182.08:14:49.06#ibcon#read 5, iclass 40, count 2 2006.182.08:14:49.06#ibcon#about to read 6, iclass 40, count 2 2006.182.08:14:49.06#ibcon#read 6, iclass 40, count 2 2006.182.08:14:49.06#ibcon#end of sib2, iclass 40, count 2 2006.182.08:14:49.06#ibcon#*after write, iclass 40, count 2 2006.182.08:14:49.06#ibcon#*before return 0, iclass 40, count 2 2006.182.08:14:49.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:49.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:49.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.08:14:49.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:49.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:49.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:49.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:49.18#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:14:49.18#ibcon#first serial, iclass 40, count 0 2006.182.08:14:49.18#ibcon#enter sib2, iclass 40, count 0 2006.182.08:14:49.18#ibcon#flushed, iclass 40, count 0 2006.182.08:14:49.18#ibcon#about to write, iclass 40, count 0 2006.182.08:14:49.18#ibcon#wrote, iclass 40, count 0 2006.182.08:14:49.18#ibcon#about to read 3, iclass 40, count 0 2006.182.08:14:49.20#ibcon#read 3, iclass 40, count 0 2006.182.08:14:49.20#ibcon#about to read 4, iclass 40, count 0 2006.182.08:14:49.20#ibcon#read 4, iclass 40, count 0 2006.182.08:14:49.20#ibcon#about to read 5, iclass 40, count 0 2006.182.08:14:49.20#ibcon#read 5, iclass 40, count 0 2006.182.08:14:49.20#ibcon#about to read 6, iclass 40, count 0 2006.182.08:14:49.20#ibcon#read 6, iclass 40, count 0 2006.182.08:14:49.20#ibcon#end of sib2, iclass 40, count 0 2006.182.08:14:49.20#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:14:49.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:14:49.20#ibcon#[25=USB\r\n] 2006.182.08:14:49.20#ibcon#*before write, iclass 40, count 0 2006.182.08:14:49.20#ibcon#enter sib2, iclass 40, count 0 2006.182.08:14:49.20#ibcon#flushed, iclass 40, count 0 2006.182.08:14:49.20#ibcon#about to write, iclass 40, count 0 2006.182.08:14:49.20#ibcon#wrote, iclass 40, count 0 2006.182.08:14:49.20#ibcon#about to read 3, iclass 40, count 0 2006.182.08:14:49.23#ibcon#read 3, iclass 40, count 0 2006.182.08:14:49.23#ibcon#about to read 4, iclass 40, count 0 2006.182.08:14:49.23#ibcon#read 4, iclass 40, count 0 2006.182.08:14:49.23#ibcon#about to read 5, iclass 40, count 0 2006.182.08:14:49.23#ibcon#read 5, iclass 40, count 0 2006.182.08:14:49.23#ibcon#about to read 6, iclass 40, count 0 2006.182.08:14:49.23#ibcon#read 6, iclass 40, count 0 2006.182.08:14:49.23#ibcon#end of sib2, iclass 40, count 0 2006.182.08:14:49.23#ibcon#*after write, iclass 40, count 0 2006.182.08:14:49.23#ibcon#*before return 0, iclass 40, count 0 2006.182.08:14:49.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:49.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:49.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:14:49.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:14:49.23$vc4f8/valo=5,652.99 2006.182.08:14:49.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.08:14:49.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.08:14:49.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:49.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:49.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:49.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:49.23#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:14:49.23#ibcon#first serial, iclass 4, count 0 2006.182.08:14:49.23#ibcon#enter sib2, iclass 4, count 0 2006.182.08:14:49.23#ibcon#flushed, iclass 4, count 0 2006.182.08:14:49.23#ibcon#about to write, iclass 4, count 0 2006.182.08:14:49.23#ibcon#wrote, iclass 4, count 0 2006.182.08:14:49.23#ibcon#about to read 3, iclass 4, count 0 2006.182.08:14:49.25#ibcon#read 3, iclass 4, count 0 2006.182.08:14:49.25#ibcon#about to read 4, iclass 4, count 0 2006.182.08:14:49.25#ibcon#read 4, iclass 4, count 0 2006.182.08:14:49.25#ibcon#about to read 5, iclass 4, count 0 2006.182.08:14:49.25#ibcon#read 5, iclass 4, count 0 2006.182.08:14:49.25#ibcon#about to read 6, iclass 4, count 0 2006.182.08:14:49.25#ibcon#read 6, iclass 4, count 0 2006.182.08:14:49.25#ibcon#end of sib2, iclass 4, count 0 2006.182.08:14:49.25#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:14:49.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:14:49.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:14:49.25#ibcon#*before write, iclass 4, count 0 2006.182.08:14:49.25#ibcon#enter sib2, iclass 4, count 0 2006.182.08:14:49.25#ibcon#flushed, iclass 4, count 0 2006.182.08:14:49.25#ibcon#about to write, iclass 4, count 0 2006.182.08:14:49.25#ibcon#wrote, iclass 4, count 0 2006.182.08:14:49.25#ibcon#about to read 3, iclass 4, count 0 2006.182.08:14:49.29#ibcon#read 3, iclass 4, count 0 2006.182.08:14:49.29#ibcon#about to read 4, iclass 4, count 0 2006.182.08:14:49.29#ibcon#read 4, iclass 4, count 0 2006.182.08:14:49.29#ibcon#about to read 5, iclass 4, count 0 2006.182.08:14:49.29#ibcon#read 5, iclass 4, count 0 2006.182.08:14:49.29#ibcon#about to read 6, iclass 4, count 0 2006.182.08:14:49.29#ibcon#read 6, iclass 4, count 0 2006.182.08:14:49.29#ibcon#end of sib2, iclass 4, count 0 2006.182.08:14:49.29#ibcon#*after write, iclass 4, count 0 2006.182.08:14:49.29#ibcon#*before return 0, iclass 4, count 0 2006.182.08:14:49.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:49.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:49.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:14:49.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:14:49.29$vc4f8/va=5,7 2006.182.08:14:49.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.08:14:49.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.08:14:49.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:49.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:49.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:49.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:49.35#ibcon#enter wrdev, iclass 6, count 2 2006.182.08:14:49.35#ibcon#first serial, iclass 6, count 2 2006.182.08:14:49.35#ibcon#enter sib2, iclass 6, count 2 2006.182.08:14:49.35#ibcon#flushed, iclass 6, count 2 2006.182.08:14:49.35#ibcon#about to write, iclass 6, count 2 2006.182.08:14:49.35#ibcon#wrote, iclass 6, count 2 2006.182.08:14:49.35#ibcon#about to read 3, iclass 6, count 2 2006.182.08:14:49.37#ibcon#read 3, iclass 6, count 2 2006.182.08:14:49.37#ibcon#about to read 4, iclass 6, count 2 2006.182.08:14:49.37#ibcon#read 4, iclass 6, count 2 2006.182.08:14:49.37#ibcon#about to read 5, iclass 6, count 2 2006.182.08:14:49.37#ibcon#read 5, iclass 6, count 2 2006.182.08:14:49.37#ibcon#about to read 6, iclass 6, count 2 2006.182.08:14:49.37#ibcon#read 6, iclass 6, count 2 2006.182.08:14:49.37#ibcon#end of sib2, iclass 6, count 2 2006.182.08:14:49.37#ibcon#*mode == 0, iclass 6, count 2 2006.182.08:14:49.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.08:14:49.37#ibcon#[25=AT05-07\r\n] 2006.182.08:14:49.37#ibcon#*before write, iclass 6, count 2 2006.182.08:14:49.37#ibcon#enter sib2, iclass 6, count 2 2006.182.08:14:49.37#ibcon#flushed, iclass 6, count 2 2006.182.08:14:49.37#ibcon#about to write, iclass 6, count 2 2006.182.08:14:49.37#ibcon#wrote, iclass 6, count 2 2006.182.08:14:49.37#ibcon#about to read 3, iclass 6, count 2 2006.182.08:14:49.40#ibcon#read 3, iclass 6, count 2 2006.182.08:14:49.40#ibcon#about to read 4, iclass 6, count 2 2006.182.08:14:49.40#ibcon#read 4, iclass 6, count 2 2006.182.08:14:49.40#ibcon#about to read 5, iclass 6, count 2 2006.182.08:14:49.40#ibcon#read 5, iclass 6, count 2 2006.182.08:14:49.40#ibcon#about to read 6, iclass 6, count 2 2006.182.08:14:49.40#ibcon#read 6, iclass 6, count 2 2006.182.08:14:49.40#ibcon#end of sib2, iclass 6, count 2 2006.182.08:14:49.40#ibcon#*after write, iclass 6, count 2 2006.182.08:14:49.40#ibcon#*before return 0, iclass 6, count 2 2006.182.08:14:49.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:49.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:49.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.08:14:49.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:49.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:49.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:49.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:49.52#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:14:49.52#ibcon#first serial, iclass 6, count 0 2006.182.08:14:49.52#ibcon#enter sib2, iclass 6, count 0 2006.182.08:14:49.52#ibcon#flushed, iclass 6, count 0 2006.182.08:14:49.52#ibcon#about to write, iclass 6, count 0 2006.182.08:14:49.52#ibcon#wrote, iclass 6, count 0 2006.182.08:14:49.52#ibcon#about to read 3, iclass 6, count 0 2006.182.08:14:49.54#ibcon#read 3, iclass 6, count 0 2006.182.08:14:49.54#ibcon#about to read 4, iclass 6, count 0 2006.182.08:14:49.54#ibcon#read 4, iclass 6, count 0 2006.182.08:14:49.54#ibcon#about to read 5, iclass 6, count 0 2006.182.08:14:49.54#ibcon#read 5, iclass 6, count 0 2006.182.08:14:49.54#ibcon#about to read 6, iclass 6, count 0 2006.182.08:14:49.54#ibcon#read 6, iclass 6, count 0 2006.182.08:14:49.54#ibcon#end of sib2, iclass 6, count 0 2006.182.08:14:49.54#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:14:49.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:14:49.54#ibcon#[25=USB\r\n] 2006.182.08:14:49.54#ibcon#*before write, iclass 6, count 0 2006.182.08:14:49.54#ibcon#enter sib2, iclass 6, count 0 2006.182.08:14:49.54#ibcon#flushed, iclass 6, count 0 2006.182.08:14:49.54#ibcon#about to write, iclass 6, count 0 2006.182.08:14:49.54#ibcon#wrote, iclass 6, count 0 2006.182.08:14:49.54#ibcon#about to read 3, iclass 6, count 0 2006.182.08:14:49.57#ibcon#read 3, iclass 6, count 0 2006.182.08:14:49.57#ibcon#about to read 4, iclass 6, count 0 2006.182.08:14:49.57#ibcon#read 4, iclass 6, count 0 2006.182.08:14:49.57#ibcon#about to read 5, iclass 6, count 0 2006.182.08:14:49.57#ibcon#read 5, iclass 6, count 0 2006.182.08:14:49.57#ibcon#about to read 6, iclass 6, count 0 2006.182.08:14:49.57#ibcon#read 6, iclass 6, count 0 2006.182.08:14:49.57#ibcon#end of sib2, iclass 6, count 0 2006.182.08:14:49.57#ibcon#*after write, iclass 6, count 0 2006.182.08:14:49.57#ibcon#*before return 0, iclass 6, count 0 2006.182.08:14:49.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:49.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:49.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:14:49.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:14:49.57$vc4f8/valo=6,772.99 2006.182.08:14:49.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.08:14:49.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.08:14:49.57#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:49.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:49.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:49.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:49.57#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:14:49.57#ibcon#first serial, iclass 10, count 0 2006.182.08:14:49.57#ibcon#enter sib2, iclass 10, count 0 2006.182.08:14:49.57#ibcon#flushed, iclass 10, count 0 2006.182.08:14:49.57#ibcon#about to write, iclass 10, count 0 2006.182.08:14:49.57#ibcon#wrote, iclass 10, count 0 2006.182.08:14:49.57#ibcon#about to read 3, iclass 10, count 0 2006.182.08:14:49.59#ibcon#read 3, iclass 10, count 0 2006.182.08:14:49.59#ibcon#about to read 4, iclass 10, count 0 2006.182.08:14:49.59#ibcon#read 4, iclass 10, count 0 2006.182.08:14:49.59#ibcon#about to read 5, iclass 10, count 0 2006.182.08:14:49.59#ibcon#read 5, iclass 10, count 0 2006.182.08:14:49.59#ibcon#about to read 6, iclass 10, count 0 2006.182.08:14:49.59#ibcon#read 6, iclass 10, count 0 2006.182.08:14:49.59#ibcon#end of sib2, iclass 10, count 0 2006.182.08:14:49.59#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:14:49.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:14:49.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:14:49.59#ibcon#*before write, iclass 10, count 0 2006.182.08:14:49.59#ibcon#enter sib2, iclass 10, count 0 2006.182.08:14:49.59#ibcon#flushed, iclass 10, count 0 2006.182.08:14:49.59#ibcon#about to write, iclass 10, count 0 2006.182.08:14:49.59#ibcon#wrote, iclass 10, count 0 2006.182.08:14:49.59#ibcon#about to read 3, iclass 10, count 0 2006.182.08:14:49.63#ibcon#read 3, iclass 10, count 0 2006.182.08:14:49.63#ibcon#about to read 4, iclass 10, count 0 2006.182.08:14:49.63#ibcon#read 4, iclass 10, count 0 2006.182.08:14:49.63#ibcon#about to read 5, iclass 10, count 0 2006.182.08:14:49.63#ibcon#read 5, iclass 10, count 0 2006.182.08:14:49.63#ibcon#about to read 6, iclass 10, count 0 2006.182.08:14:49.63#ibcon#read 6, iclass 10, count 0 2006.182.08:14:49.63#ibcon#end of sib2, iclass 10, count 0 2006.182.08:14:49.63#ibcon#*after write, iclass 10, count 0 2006.182.08:14:49.63#ibcon#*before return 0, iclass 10, count 0 2006.182.08:14:49.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:49.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:49.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:14:49.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:14:49.63$vc4f8/va=6,6 2006.182.08:14:49.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.08:14:49.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.08:14:49.63#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:49.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:14:49.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:14:49.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:14:49.69#ibcon#enter wrdev, iclass 12, count 2 2006.182.08:14:49.69#ibcon#first serial, iclass 12, count 2 2006.182.08:14:49.69#ibcon#enter sib2, iclass 12, count 2 2006.182.08:14:49.69#ibcon#flushed, iclass 12, count 2 2006.182.08:14:49.69#ibcon#about to write, iclass 12, count 2 2006.182.08:14:49.69#ibcon#wrote, iclass 12, count 2 2006.182.08:14:49.69#ibcon#about to read 3, iclass 12, count 2 2006.182.08:14:49.71#ibcon#read 3, iclass 12, count 2 2006.182.08:14:49.71#ibcon#about to read 4, iclass 12, count 2 2006.182.08:14:49.71#ibcon#read 4, iclass 12, count 2 2006.182.08:14:49.71#ibcon#about to read 5, iclass 12, count 2 2006.182.08:14:49.71#ibcon#read 5, iclass 12, count 2 2006.182.08:14:49.71#ibcon#about to read 6, iclass 12, count 2 2006.182.08:14:49.71#ibcon#read 6, iclass 12, count 2 2006.182.08:14:49.71#ibcon#end of sib2, iclass 12, count 2 2006.182.08:14:49.71#ibcon#*mode == 0, iclass 12, count 2 2006.182.08:14:49.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.08:14:49.71#ibcon#[25=AT06-06\r\n] 2006.182.08:14:49.71#ibcon#*before write, iclass 12, count 2 2006.182.08:14:49.71#ibcon#enter sib2, iclass 12, count 2 2006.182.08:14:49.71#ibcon#flushed, iclass 12, count 2 2006.182.08:14:49.71#ibcon#about to write, iclass 12, count 2 2006.182.08:14:49.71#ibcon#wrote, iclass 12, count 2 2006.182.08:14:49.71#ibcon#about to read 3, iclass 12, count 2 2006.182.08:14:49.74#ibcon#read 3, iclass 12, count 2 2006.182.08:14:49.74#ibcon#about to read 4, iclass 12, count 2 2006.182.08:14:49.74#ibcon#read 4, iclass 12, count 2 2006.182.08:14:49.74#ibcon#about to read 5, iclass 12, count 2 2006.182.08:14:49.74#ibcon#read 5, iclass 12, count 2 2006.182.08:14:49.74#ibcon#about to read 6, iclass 12, count 2 2006.182.08:14:49.74#ibcon#read 6, iclass 12, count 2 2006.182.08:14:49.74#ibcon#end of sib2, iclass 12, count 2 2006.182.08:14:49.74#ibcon#*after write, iclass 12, count 2 2006.182.08:14:49.74#ibcon#*before return 0, iclass 12, count 2 2006.182.08:14:49.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:14:49.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:14:49.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.08:14:49.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:49.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:14:49.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:14:49.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:14:49.86#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:14:49.86#ibcon#first serial, iclass 12, count 0 2006.182.08:14:49.86#ibcon#enter sib2, iclass 12, count 0 2006.182.08:14:49.86#ibcon#flushed, iclass 12, count 0 2006.182.08:14:49.86#ibcon#about to write, iclass 12, count 0 2006.182.08:14:49.86#ibcon#wrote, iclass 12, count 0 2006.182.08:14:49.86#ibcon#about to read 3, iclass 12, count 0 2006.182.08:14:49.88#ibcon#read 3, iclass 12, count 0 2006.182.08:14:49.88#ibcon#about to read 4, iclass 12, count 0 2006.182.08:14:49.88#ibcon#read 4, iclass 12, count 0 2006.182.08:14:49.88#ibcon#about to read 5, iclass 12, count 0 2006.182.08:14:49.88#ibcon#read 5, iclass 12, count 0 2006.182.08:14:49.88#ibcon#about to read 6, iclass 12, count 0 2006.182.08:14:49.88#ibcon#read 6, iclass 12, count 0 2006.182.08:14:49.88#ibcon#end of sib2, iclass 12, count 0 2006.182.08:14:49.88#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:14:49.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:14:49.88#ibcon#[25=USB\r\n] 2006.182.08:14:49.88#ibcon#*before write, iclass 12, count 0 2006.182.08:14:49.88#ibcon#enter sib2, iclass 12, count 0 2006.182.08:14:49.88#ibcon#flushed, iclass 12, count 0 2006.182.08:14:49.88#ibcon#about to write, iclass 12, count 0 2006.182.08:14:49.88#ibcon#wrote, iclass 12, count 0 2006.182.08:14:49.88#ibcon#about to read 3, iclass 12, count 0 2006.182.08:14:49.91#ibcon#read 3, iclass 12, count 0 2006.182.08:14:49.91#ibcon#about to read 4, iclass 12, count 0 2006.182.08:14:49.91#ibcon#read 4, iclass 12, count 0 2006.182.08:14:49.91#ibcon#about to read 5, iclass 12, count 0 2006.182.08:14:49.91#ibcon#read 5, iclass 12, count 0 2006.182.08:14:49.91#ibcon#about to read 6, iclass 12, count 0 2006.182.08:14:49.91#ibcon#read 6, iclass 12, count 0 2006.182.08:14:49.91#ibcon#end of sib2, iclass 12, count 0 2006.182.08:14:49.91#ibcon#*after write, iclass 12, count 0 2006.182.08:14:49.91#ibcon#*before return 0, iclass 12, count 0 2006.182.08:14:49.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:14:49.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:14:49.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:14:49.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:14:49.91$vc4f8/valo=7,832.99 2006.182.08:14:49.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.08:14:49.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.08:14:49.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:49.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:14:49.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:14:49.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:14:49.91#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:14:49.91#ibcon#first serial, iclass 14, count 0 2006.182.08:14:49.91#ibcon#enter sib2, iclass 14, count 0 2006.182.08:14:49.91#ibcon#flushed, iclass 14, count 0 2006.182.08:14:49.91#ibcon#about to write, iclass 14, count 0 2006.182.08:14:49.91#ibcon#wrote, iclass 14, count 0 2006.182.08:14:49.91#ibcon#about to read 3, iclass 14, count 0 2006.182.08:14:49.93#ibcon#read 3, iclass 14, count 0 2006.182.08:14:49.93#ibcon#about to read 4, iclass 14, count 0 2006.182.08:14:49.93#ibcon#read 4, iclass 14, count 0 2006.182.08:14:49.93#ibcon#about to read 5, iclass 14, count 0 2006.182.08:14:49.93#ibcon#read 5, iclass 14, count 0 2006.182.08:14:49.93#ibcon#about to read 6, iclass 14, count 0 2006.182.08:14:49.93#ibcon#read 6, iclass 14, count 0 2006.182.08:14:49.93#ibcon#end of sib2, iclass 14, count 0 2006.182.08:14:49.93#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:14:49.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:14:49.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:14:49.93#ibcon#*before write, iclass 14, count 0 2006.182.08:14:49.93#ibcon#enter sib2, iclass 14, count 0 2006.182.08:14:49.93#ibcon#flushed, iclass 14, count 0 2006.182.08:14:49.93#ibcon#about to write, iclass 14, count 0 2006.182.08:14:49.93#ibcon#wrote, iclass 14, count 0 2006.182.08:14:49.93#ibcon#about to read 3, iclass 14, count 0 2006.182.08:14:49.97#ibcon#read 3, iclass 14, count 0 2006.182.08:14:49.97#ibcon#about to read 4, iclass 14, count 0 2006.182.08:14:49.97#ibcon#read 4, iclass 14, count 0 2006.182.08:14:49.97#ibcon#about to read 5, iclass 14, count 0 2006.182.08:14:49.97#ibcon#read 5, iclass 14, count 0 2006.182.08:14:49.97#ibcon#about to read 6, iclass 14, count 0 2006.182.08:14:49.97#ibcon#read 6, iclass 14, count 0 2006.182.08:14:49.97#ibcon#end of sib2, iclass 14, count 0 2006.182.08:14:49.97#ibcon#*after write, iclass 14, count 0 2006.182.08:14:49.97#ibcon#*before return 0, iclass 14, count 0 2006.182.08:14:49.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:14:49.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:14:49.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:14:49.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:14:49.97$vc4f8/va=7,6 2006.182.08:14:49.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.08:14:49.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.08:14:49.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:49.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:14:50.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:14:50.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:14:50.03#ibcon#enter wrdev, iclass 16, count 2 2006.182.08:14:50.03#ibcon#first serial, iclass 16, count 2 2006.182.08:14:50.03#ibcon#enter sib2, iclass 16, count 2 2006.182.08:14:50.03#ibcon#flushed, iclass 16, count 2 2006.182.08:14:50.03#ibcon#about to write, iclass 16, count 2 2006.182.08:14:50.03#ibcon#wrote, iclass 16, count 2 2006.182.08:14:50.03#ibcon#about to read 3, iclass 16, count 2 2006.182.08:14:50.05#ibcon#read 3, iclass 16, count 2 2006.182.08:14:50.05#ibcon#about to read 4, iclass 16, count 2 2006.182.08:14:50.05#ibcon#read 4, iclass 16, count 2 2006.182.08:14:50.05#ibcon#about to read 5, iclass 16, count 2 2006.182.08:14:50.05#ibcon#read 5, iclass 16, count 2 2006.182.08:14:50.05#ibcon#about to read 6, iclass 16, count 2 2006.182.08:14:50.05#ibcon#read 6, iclass 16, count 2 2006.182.08:14:50.05#ibcon#end of sib2, iclass 16, count 2 2006.182.08:14:50.05#ibcon#*mode == 0, iclass 16, count 2 2006.182.08:14:50.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.08:14:50.05#ibcon#[25=AT07-06\r\n] 2006.182.08:14:50.05#ibcon#*before write, iclass 16, count 2 2006.182.08:14:50.05#ibcon#enter sib2, iclass 16, count 2 2006.182.08:14:50.05#ibcon#flushed, iclass 16, count 2 2006.182.08:14:50.05#ibcon#about to write, iclass 16, count 2 2006.182.08:14:50.05#ibcon#wrote, iclass 16, count 2 2006.182.08:14:50.05#ibcon#about to read 3, iclass 16, count 2 2006.182.08:14:50.08#ibcon#read 3, iclass 16, count 2 2006.182.08:14:50.08#ibcon#about to read 4, iclass 16, count 2 2006.182.08:14:50.08#ibcon#read 4, iclass 16, count 2 2006.182.08:14:50.08#ibcon#about to read 5, iclass 16, count 2 2006.182.08:14:50.08#ibcon#read 5, iclass 16, count 2 2006.182.08:14:50.08#ibcon#about to read 6, iclass 16, count 2 2006.182.08:14:50.08#ibcon#read 6, iclass 16, count 2 2006.182.08:14:50.08#ibcon#end of sib2, iclass 16, count 2 2006.182.08:14:50.08#ibcon#*after write, iclass 16, count 2 2006.182.08:14:50.08#ibcon#*before return 0, iclass 16, count 2 2006.182.08:14:50.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:14:50.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:14:50.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.08:14:50.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:50.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:14:50.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:14:50.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:14:50.20#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:14:50.20#ibcon#first serial, iclass 16, count 0 2006.182.08:14:50.20#ibcon#enter sib2, iclass 16, count 0 2006.182.08:14:50.20#ibcon#flushed, iclass 16, count 0 2006.182.08:14:50.20#ibcon#about to write, iclass 16, count 0 2006.182.08:14:50.20#ibcon#wrote, iclass 16, count 0 2006.182.08:14:50.20#ibcon#about to read 3, iclass 16, count 0 2006.182.08:14:50.22#ibcon#read 3, iclass 16, count 0 2006.182.08:14:50.22#ibcon#about to read 4, iclass 16, count 0 2006.182.08:14:50.22#ibcon#read 4, iclass 16, count 0 2006.182.08:14:50.22#ibcon#about to read 5, iclass 16, count 0 2006.182.08:14:50.22#ibcon#read 5, iclass 16, count 0 2006.182.08:14:50.22#ibcon#about to read 6, iclass 16, count 0 2006.182.08:14:50.22#ibcon#read 6, iclass 16, count 0 2006.182.08:14:50.22#ibcon#end of sib2, iclass 16, count 0 2006.182.08:14:50.22#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:14:50.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:14:50.22#ibcon#[25=USB\r\n] 2006.182.08:14:50.22#ibcon#*before write, iclass 16, count 0 2006.182.08:14:50.22#ibcon#enter sib2, iclass 16, count 0 2006.182.08:14:50.22#ibcon#flushed, iclass 16, count 0 2006.182.08:14:50.22#ibcon#about to write, iclass 16, count 0 2006.182.08:14:50.22#ibcon#wrote, iclass 16, count 0 2006.182.08:14:50.22#ibcon#about to read 3, iclass 16, count 0 2006.182.08:14:50.25#ibcon#read 3, iclass 16, count 0 2006.182.08:14:50.25#ibcon#about to read 4, iclass 16, count 0 2006.182.08:14:50.25#ibcon#read 4, iclass 16, count 0 2006.182.08:14:50.25#ibcon#about to read 5, iclass 16, count 0 2006.182.08:14:50.25#ibcon#read 5, iclass 16, count 0 2006.182.08:14:50.25#ibcon#about to read 6, iclass 16, count 0 2006.182.08:14:50.25#ibcon#read 6, iclass 16, count 0 2006.182.08:14:50.25#ibcon#end of sib2, iclass 16, count 0 2006.182.08:14:50.25#ibcon#*after write, iclass 16, count 0 2006.182.08:14:50.25#ibcon#*before return 0, iclass 16, count 0 2006.182.08:14:50.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:14:50.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:14:50.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:14:50.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:14:50.25$vc4f8/valo=8,852.99 2006.182.08:14:50.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.08:14:50.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.08:14:50.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:50.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:14:50.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:14:50.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:14:50.25#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:14:50.25#ibcon#first serial, iclass 18, count 0 2006.182.08:14:50.25#ibcon#enter sib2, iclass 18, count 0 2006.182.08:14:50.25#ibcon#flushed, iclass 18, count 0 2006.182.08:14:50.25#ibcon#about to write, iclass 18, count 0 2006.182.08:14:50.25#ibcon#wrote, iclass 18, count 0 2006.182.08:14:50.25#ibcon#about to read 3, iclass 18, count 0 2006.182.08:14:50.27#ibcon#read 3, iclass 18, count 0 2006.182.08:14:50.27#ibcon#about to read 4, iclass 18, count 0 2006.182.08:14:50.27#ibcon#read 4, iclass 18, count 0 2006.182.08:14:50.27#ibcon#about to read 5, iclass 18, count 0 2006.182.08:14:50.27#ibcon#read 5, iclass 18, count 0 2006.182.08:14:50.27#ibcon#about to read 6, iclass 18, count 0 2006.182.08:14:50.27#ibcon#read 6, iclass 18, count 0 2006.182.08:14:50.27#ibcon#end of sib2, iclass 18, count 0 2006.182.08:14:50.27#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:14:50.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:14:50.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:14:50.27#ibcon#*before write, iclass 18, count 0 2006.182.08:14:50.27#ibcon#enter sib2, iclass 18, count 0 2006.182.08:14:50.27#ibcon#flushed, iclass 18, count 0 2006.182.08:14:50.27#ibcon#about to write, iclass 18, count 0 2006.182.08:14:50.27#ibcon#wrote, iclass 18, count 0 2006.182.08:14:50.27#ibcon#about to read 3, iclass 18, count 0 2006.182.08:14:50.31#ibcon#read 3, iclass 18, count 0 2006.182.08:14:50.31#ibcon#about to read 4, iclass 18, count 0 2006.182.08:14:50.31#ibcon#read 4, iclass 18, count 0 2006.182.08:14:50.31#ibcon#about to read 5, iclass 18, count 0 2006.182.08:14:50.31#ibcon#read 5, iclass 18, count 0 2006.182.08:14:50.31#ibcon#about to read 6, iclass 18, count 0 2006.182.08:14:50.31#ibcon#read 6, iclass 18, count 0 2006.182.08:14:50.31#ibcon#end of sib2, iclass 18, count 0 2006.182.08:14:50.31#ibcon#*after write, iclass 18, count 0 2006.182.08:14:50.31#ibcon#*before return 0, iclass 18, count 0 2006.182.08:14:50.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:14:50.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:14:50.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:14:50.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:14:50.31$vc4f8/va=8,7 2006.182.08:14:50.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.08:14:50.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.08:14:50.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:50.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:14:50.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:14:50.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:14:50.37#ibcon#enter wrdev, iclass 20, count 2 2006.182.08:14:50.37#ibcon#first serial, iclass 20, count 2 2006.182.08:14:50.37#ibcon#enter sib2, iclass 20, count 2 2006.182.08:14:50.37#ibcon#flushed, iclass 20, count 2 2006.182.08:14:50.37#ibcon#about to write, iclass 20, count 2 2006.182.08:14:50.37#ibcon#wrote, iclass 20, count 2 2006.182.08:14:50.37#ibcon#about to read 3, iclass 20, count 2 2006.182.08:14:50.39#ibcon#read 3, iclass 20, count 2 2006.182.08:14:50.39#ibcon#about to read 4, iclass 20, count 2 2006.182.08:14:50.39#ibcon#read 4, iclass 20, count 2 2006.182.08:14:50.39#ibcon#about to read 5, iclass 20, count 2 2006.182.08:14:50.39#ibcon#read 5, iclass 20, count 2 2006.182.08:14:50.39#ibcon#about to read 6, iclass 20, count 2 2006.182.08:14:50.39#ibcon#read 6, iclass 20, count 2 2006.182.08:14:50.39#ibcon#end of sib2, iclass 20, count 2 2006.182.08:14:50.39#ibcon#*mode == 0, iclass 20, count 2 2006.182.08:14:50.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.08:14:50.39#ibcon#[25=AT08-07\r\n] 2006.182.08:14:50.39#ibcon#*before write, iclass 20, count 2 2006.182.08:14:50.39#ibcon#enter sib2, iclass 20, count 2 2006.182.08:14:50.39#ibcon#flushed, iclass 20, count 2 2006.182.08:14:50.39#ibcon#about to write, iclass 20, count 2 2006.182.08:14:50.39#ibcon#wrote, iclass 20, count 2 2006.182.08:14:50.39#ibcon#about to read 3, iclass 20, count 2 2006.182.08:14:50.42#ibcon#read 3, iclass 20, count 2 2006.182.08:14:50.42#ibcon#about to read 4, iclass 20, count 2 2006.182.08:14:50.42#ibcon#read 4, iclass 20, count 2 2006.182.08:14:50.42#ibcon#about to read 5, iclass 20, count 2 2006.182.08:14:50.42#ibcon#read 5, iclass 20, count 2 2006.182.08:14:50.42#ibcon#about to read 6, iclass 20, count 2 2006.182.08:14:50.42#ibcon#read 6, iclass 20, count 2 2006.182.08:14:50.42#ibcon#end of sib2, iclass 20, count 2 2006.182.08:14:50.42#ibcon#*after write, iclass 20, count 2 2006.182.08:14:50.42#ibcon#*before return 0, iclass 20, count 2 2006.182.08:14:50.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:14:50.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:14:50.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.08:14:50.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:50.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:14:50.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:14:50.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:14:50.54#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:14:50.54#ibcon#first serial, iclass 20, count 0 2006.182.08:14:50.54#ibcon#enter sib2, iclass 20, count 0 2006.182.08:14:50.54#ibcon#flushed, iclass 20, count 0 2006.182.08:14:50.54#ibcon#about to write, iclass 20, count 0 2006.182.08:14:50.54#ibcon#wrote, iclass 20, count 0 2006.182.08:14:50.54#ibcon#about to read 3, iclass 20, count 0 2006.182.08:14:50.56#ibcon#read 3, iclass 20, count 0 2006.182.08:14:50.56#ibcon#about to read 4, iclass 20, count 0 2006.182.08:14:50.56#ibcon#read 4, iclass 20, count 0 2006.182.08:14:50.56#ibcon#about to read 5, iclass 20, count 0 2006.182.08:14:50.56#ibcon#read 5, iclass 20, count 0 2006.182.08:14:50.56#ibcon#about to read 6, iclass 20, count 0 2006.182.08:14:50.56#ibcon#read 6, iclass 20, count 0 2006.182.08:14:50.56#ibcon#end of sib2, iclass 20, count 0 2006.182.08:14:50.56#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:14:50.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:14:50.56#ibcon#[25=USB\r\n] 2006.182.08:14:50.56#ibcon#*before write, iclass 20, count 0 2006.182.08:14:50.56#ibcon#enter sib2, iclass 20, count 0 2006.182.08:14:50.56#ibcon#flushed, iclass 20, count 0 2006.182.08:14:50.56#ibcon#about to write, iclass 20, count 0 2006.182.08:14:50.56#ibcon#wrote, iclass 20, count 0 2006.182.08:14:50.56#ibcon#about to read 3, iclass 20, count 0 2006.182.08:14:50.59#ibcon#read 3, iclass 20, count 0 2006.182.08:14:50.59#ibcon#about to read 4, iclass 20, count 0 2006.182.08:14:50.59#ibcon#read 4, iclass 20, count 0 2006.182.08:14:50.59#ibcon#about to read 5, iclass 20, count 0 2006.182.08:14:50.59#ibcon#read 5, iclass 20, count 0 2006.182.08:14:50.59#ibcon#about to read 6, iclass 20, count 0 2006.182.08:14:50.59#ibcon#read 6, iclass 20, count 0 2006.182.08:14:50.59#ibcon#end of sib2, iclass 20, count 0 2006.182.08:14:50.59#ibcon#*after write, iclass 20, count 0 2006.182.08:14:50.59#ibcon#*before return 0, iclass 20, count 0 2006.182.08:14:50.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:14:50.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:14:50.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:14:50.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:14:50.59$vc4f8/vblo=1,632.99 2006.182.08:14:50.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.08:14:50.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.08:14:50.59#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:50.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:14:50.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:14:50.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:14:50.59#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:14:50.59#ibcon#first serial, iclass 22, count 0 2006.182.08:14:50.59#ibcon#enter sib2, iclass 22, count 0 2006.182.08:14:50.59#ibcon#flushed, iclass 22, count 0 2006.182.08:14:50.59#ibcon#about to write, iclass 22, count 0 2006.182.08:14:50.59#ibcon#wrote, iclass 22, count 0 2006.182.08:14:50.59#ibcon#about to read 3, iclass 22, count 0 2006.182.08:14:50.61#ibcon#read 3, iclass 22, count 0 2006.182.08:14:50.61#ibcon#about to read 4, iclass 22, count 0 2006.182.08:14:50.61#ibcon#read 4, iclass 22, count 0 2006.182.08:14:50.61#ibcon#about to read 5, iclass 22, count 0 2006.182.08:14:50.61#ibcon#read 5, iclass 22, count 0 2006.182.08:14:50.61#ibcon#about to read 6, iclass 22, count 0 2006.182.08:14:50.61#ibcon#read 6, iclass 22, count 0 2006.182.08:14:50.61#ibcon#end of sib2, iclass 22, count 0 2006.182.08:14:50.61#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:14:50.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:14:50.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:14:50.61#ibcon#*before write, iclass 22, count 0 2006.182.08:14:50.61#ibcon#enter sib2, iclass 22, count 0 2006.182.08:14:50.61#ibcon#flushed, iclass 22, count 0 2006.182.08:14:50.61#ibcon#about to write, iclass 22, count 0 2006.182.08:14:50.61#ibcon#wrote, iclass 22, count 0 2006.182.08:14:50.61#ibcon#about to read 3, iclass 22, count 0 2006.182.08:14:50.65#ibcon#read 3, iclass 22, count 0 2006.182.08:14:50.65#ibcon#about to read 4, iclass 22, count 0 2006.182.08:14:50.65#ibcon#read 4, iclass 22, count 0 2006.182.08:14:50.65#ibcon#about to read 5, iclass 22, count 0 2006.182.08:14:50.65#ibcon#read 5, iclass 22, count 0 2006.182.08:14:50.65#ibcon#about to read 6, iclass 22, count 0 2006.182.08:14:50.65#ibcon#read 6, iclass 22, count 0 2006.182.08:14:50.65#ibcon#end of sib2, iclass 22, count 0 2006.182.08:14:50.65#ibcon#*after write, iclass 22, count 0 2006.182.08:14:50.65#ibcon#*before return 0, iclass 22, count 0 2006.182.08:14:50.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:14:50.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:14:50.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:14:50.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:14:50.65$vc4f8/vb=1,4 2006.182.08:14:50.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.08:14:50.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.08:14:50.65#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:50.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:14:50.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:14:50.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:14:50.65#ibcon#enter wrdev, iclass 24, count 2 2006.182.08:14:50.65#ibcon#first serial, iclass 24, count 2 2006.182.08:14:50.65#ibcon#enter sib2, iclass 24, count 2 2006.182.08:14:50.65#ibcon#flushed, iclass 24, count 2 2006.182.08:14:50.65#ibcon#about to write, iclass 24, count 2 2006.182.08:14:50.65#ibcon#wrote, iclass 24, count 2 2006.182.08:14:50.65#ibcon#about to read 3, iclass 24, count 2 2006.182.08:14:50.67#ibcon#read 3, iclass 24, count 2 2006.182.08:14:50.67#ibcon#about to read 4, iclass 24, count 2 2006.182.08:14:50.67#ibcon#read 4, iclass 24, count 2 2006.182.08:14:50.67#ibcon#about to read 5, iclass 24, count 2 2006.182.08:14:50.67#ibcon#read 5, iclass 24, count 2 2006.182.08:14:50.67#ibcon#about to read 6, iclass 24, count 2 2006.182.08:14:50.67#ibcon#read 6, iclass 24, count 2 2006.182.08:14:50.67#ibcon#end of sib2, iclass 24, count 2 2006.182.08:14:50.67#ibcon#*mode == 0, iclass 24, count 2 2006.182.08:14:50.67#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.08:14:50.67#ibcon#[27=AT01-04\r\n] 2006.182.08:14:50.67#ibcon#*before write, iclass 24, count 2 2006.182.08:14:50.67#ibcon#enter sib2, iclass 24, count 2 2006.182.08:14:50.67#ibcon#flushed, iclass 24, count 2 2006.182.08:14:50.67#ibcon#about to write, iclass 24, count 2 2006.182.08:14:50.67#ibcon#wrote, iclass 24, count 2 2006.182.08:14:50.67#ibcon#about to read 3, iclass 24, count 2 2006.182.08:14:50.70#ibcon#read 3, iclass 24, count 2 2006.182.08:14:50.70#ibcon#about to read 4, iclass 24, count 2 2006.182.08:14:50.70#ibcon#read 4, iclass 24, count 2 2006.182.08:14:50.70#ibcon#about to read 5, iclass 24, count 2 2006.182.08:14:50.70#ibcon#read 5, iclass 24, count 2 2006.182.08:14:50.70#ibcon#about to read 6, iclass 24, count 2 2006.182.08:14:50.70#ibcon#read 6, iclass 24, count 2 2006.182.08:14:50.70#ibcon#end of sib2, iclass 24, count 2 2006.182.08:14:50.70#ibcon#*after write, iclass 24, count 2 2006.182.08:14:50.70#ibcon#*before return 0, iclass 24, count 2 2006.182.08:14:50.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:14:50.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:14:50.70#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.08:14:50.70#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:50.70#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:14:50.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:14:50.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:14:50.82#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:14:50.82#ibcon#first serial, iclass 24, count 0 2006.182.08:14:50.82#ibcon#enter sib2, iclass 24, count 0 2006.182.08:14:50.82#ibcon#flushed, iclass 24, count 0 2006.182.08:14:50.82#ibcon#about to write, iclass 24, count 0 2006.182.08:14:50.82#ibcon#wrote, iclass 24, count 0 2006.182.08:14:50.82#ibcon#about to read 3, iclass 24, count 0 2006.182.08:14:50.84#ibcon#read 3, iclass 24, count 0 2006.182.08:14:50.84#ibcon#about to read 4, iclass 24, count 0 2006.182.08:14:50.84#ibcon#read 4, iclass 24, count 0 2006.182.08:14:50.84#ibcon#about to read 5, iclass 24, count 0 2006.182.08:14:50.84#ibcon#read 5, iclass 24, count 0 2006.182.08:14:50.84#ibcon#about to read 6, iclass 24, count 0 2006.182.08:14:50.84#ibcon#read 6, iclass 24, count 0 2006.182.08:14:50.84#ibcon#end of sib2, iclass 24, count 0 2006.182.08:14:50.84#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:14:50.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:14:50.84#ibcon#[27=USB\r\n] 2006.182.08:14:50.84#ibcon#*before write, iclass 24, count 0 2006.182.08:14:50.84#ibcon#enter sib2, iclass 24, count 0 2006.182.08:14:50.84#ibcon#flushed, iclass 24, count 0 2006.182.08:14:50.84#ibcon#about to write, iclass 24, count 0 2006.182.08:14:50.84#ibcon#wrote, iclass 24, count 0 2006.182.08:14:50.84#ibcon#about to read 3, iclass 24, count 0 2006.182.08:14:50.87#ibcon#read 3, iclass 24, count 0 2006.182.08:14:50.87#ibcon#about to read 4, iclass 24, count 0 2006.182.08:14:50.87#ibcon#read 4, iclass 24, count 0 2006.182.08:14:50.87#ibcon#about to read 5, iclass 24, count 0 2006.182.08:14:50.87#ibcon#read 5, iclass 24, count 0 2006.182.08:14:50.87#ibcon#about to read 6, iclass 24, count 0 2006.182.08:14:50.87#ibcon#read 6, iclass 24, count 0 2006.182.08:14:50.87#ibcon#end of sib2, iclass 24, count 0 2006.182.08:14:50.87#ibcon#*after write, iclass 24, count 0 2006.182.08:14:50.87#ibcon#*before return 0, iclass 24, count 0 2006.182.08:14:50.87#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:14:50.87#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:14:50.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:14:50.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:14:50.87$vc4f8/vblo=2,640.99 2006.182.08:14:50.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.08:14:50.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.08:14:50.87#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:50.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:14:50.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:14:50.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:14:50.87#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:14:50.87#ibcon#first serial, iclass 26, count 0 2006.182.08:14:50.87#ibcon#enter sib2, iclass 26, count 0 2006.182.08:14:50.87#ibcon#flushed, iclass 26, count 0 2006.182.08:14:50.87#ibcon#about to write, iclass 26, count 0 2006.182.08:14:50.87#ibcon#wrote, iclass 26, count 0 2006.182.08:14:50.87#ibcon#about to read 3, iclass 26, count 0 2006.182.08:14:50.89#ibcon#read 3, iclass 26, count 0 2006.182.08:14:50.89#ibcon#about to read 4, iclass 26, count 0 2006.182.08:14:50.89#ibcon#read 4, iclass 26, count 0 2006.182.08:14:50.89#ibcon#about to read 5, iclass 26, count 0 2006.182.08:14:50.89#ibcon#read 5, iclass 26, count 0 2006.182.08:14:50.89#ibcon#about to read 6, iclass 26, count 0 2006.182.08:14:50.89#ibcon#read 6, iclass 26, count 0 2006.182.08:14:50.89#ibcon#end of sib2, iclass 26, count 0 2006.182.08:14:50.89#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:14:50.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:14:50.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:14:50.89#ibcon#*before write, iclass 26, count 0 2006.182.08:14:50.89#ibcon#enter sib2, iclass 26, count 0 2006.182.08:14:50.89#ibcon#flushed, iclass 26, count 0 2006.182.08:14:50.89#ibcon#about to write, iclass 26, count 0 2006.182.08:14:50.89#ibcon#wrote, iclass 26, count 0 2006.182.08:14:50.89#ibcon#about to read 3, iclass 26, count 0 2006.182.08:14:50.93#ibcon#read 3, iclass 26, count 0 2006.182.08:14:50.93#ibcon#about to read 4, iclass 26, count 0 2006.182.08:14:50.93#ibcon#read 4, iclass 26, count 0 2006.182.08:14:50.93#ibcon#about to read 5, iclass 26, count 0 2006.182.08:14:50.93#ibcon#read 5, iclass 26, count 0 2006.182.08:14:50.93#ibcon#about to read 6, iclass 26, count 0 2006.182.08:14:50.93#ibcon#read 6, iclass 26, count 0 2006.182.08:14:50.93#ibcon#end of sib2, iclass 26, count 0 2006.182.08:14:50.93#ibcon#*after write, iclass 26, count 0 2006.182.08:14:50.93#ibcon#*before return 0, iclass 26, count 0 2006.182.08:14:50.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:14:50.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:14:50.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:14:50.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:14:50.93$vc4f8/vb=2,4 2006.182.08:14:50.93#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.08:14:50.93#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.08:14:50.93#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:50.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:50.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:50.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:50.99#ibcon#enter wrdev, iclass 28, count 2 2006.182.08:14:50.99#ibcon#first serial, iclass 28, count 2 2006.182.08:14:50.99#ibcon#enter sib2, iclass 28, count 2 2006.182.08:14:50.99#ibcon#flushed, iclass 28, count 2 2006.182.08:14:50.99#ibcon#about to write, iclass 28, count 2 2006.182.08:14:50.99#ibcon#wrote, iclass 28, count 2 2006.182.08:14:50.99#ibcon#about to read 3, iclass 28, count 2 2006.182.08:14:51.01#ibcon#read 3, iclass 28, count 2 2006.182.08:14:51.01#ibcon#about to read 4, iclass 28, count 2 2006.182.08:14:51.01#ibcon#read 4, iclass 28, count 2 2006.182.08:14:51.01#ibcon#about to read 5, iclass 28, count 2 2006.182.08:14:51.01#ibcon#read 5, iclass 28, count 2 2006.182.08:14:51.01#ibcon#about to read 6, iclass 28, count 2 2006.182.08:14:51.01#ibcon#read 6, iclass 28, count 2 2006.182.08:14:51.01#ibcon#end of sib2, iclass 28, count 2 2006.182.08:14:51.01#ibcon#*mode == 0, iclass 28, count 2 2006.182.08:14:51.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.08:14:51.01#ibcon#[27=AT02-04\r\n] 2006.182.08:14:51.01#ibcon#*before write, iclass 28, count 2 2006.182.08:14:51.01#ibcon#enter sib2, iclass 28, count 2 2006.182.08:14:51.01#ibcon#flushed, iclass 28, count 2 2006.182.08:14:51.01#ibcon#about to write, iclass 28, count 2 2006.182.08:14:51.01#ibcon#wrote, iclass 28, count 2 2006.182.08:14:51.01#ibcon#about to read 3, iclass 28, count 2 2006.182.08:14:51.04#ibcon#read 3, iclass 28, count 2 2006.182.08:14:51.04#ibcon#about to read 4, iclass 28, count 2 2006.182.08:14:51.04#ibcon#read 4, iclass 28, count 2 2006.182.08:14:51.04#ibcon#about to read 5, iclass 28, count 2 2006.182.08:14:51.04#ibcon#read 5, iclass 28, count 2 2006.182.08:14:51.04#ibcon#about to read 6, iclass 28, count 2 2006.182.08:14:51.04#ibcon#read 6, iclass 28, count 2 2006.182.08:14:51.04#ibcon#end of sib2, iclass 28, count 2 2006.182.08:14:51.04#ibcon#*after write, iclass 28, count 2 2006.182.08:14:51.04#ibcon#*before return 0, iclass 28, count 2 2006.182.08:14:51.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:51.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:14:51.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.08:14:51.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:51.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:51.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:51.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:51.16#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:14:51.16#ibcon#first serial, iclass 28, count 0 2006.182.08:14:51.16#ibcon#enter sib2, iclass 28, count 0 2006.182.08:14:51.16#ibcon#flushed, iclass 28, count 0 2006.182.08:14:51.16#ibcon#about to write, iclass 28, count 0 2006.182.08:14:51.16#ibcon#wrote, iclass 28, count 0 2006.182.08:14:51.16#ibcon#about to read 3, iclass 28, count 0 2006.182.08:14:51.18#ibcon#read 3, iclass 28, count 0 2006.182.08:14:51.18#ibcon#about to read 4, iclass 28, count 0 2006.182.08:14:51.18#ibcon#read 4, iclass 28, count 0 2006.182.08:14:51.18#ibcon#about to read 5, iclass 28, count 0 2006.182.08:14:51.18#ibcon#read 5, iclass 28, count 0 2006.182.08:14:51.18#ibcon#about to read 6, iclass 28, count 0 2006.182.08:14:51.18#ibcon#read 6, iclass 28, count 0 2006.182.08:14:51.18#ibcon#end of sib2, iclass 28, count 0 2006.182.08:14:51.18#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:14:51.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:14:51.18#ibcon#[27=USB\r\n] 2006.182.08:14:51.18#ibcon#*before write, iclass 28, count 0 2006.182.08:14:51.18#ibcon#enter sib2, iclass 28, count 0 2006.182.08:14:51.18#ibcon#flushed, iclass 28, count 0 2006.182.08:14:51.18#ibcon#about to write, iclass 28, count 0 2006.182.08:14:51.18#ibcon#wrote, iclass 28, count 0 2006.182.08:14:51.18#ibcon#about to read 3, iclass 28, count 0 2006.182.08:14:51.21#ibcon#read 3, iclass 28, count 0 2006.182.08:14:51.21#ibcon#about to read 4, iclass 28, count 0 2006.182.08:14:51.21#ibcon#read 4, iclass 28, count 0 2006.182.08:14:51.21#ibcon#about to read 5, iclass 28, count 0 2006.182.08:14:51.21#ibcon#read 5, iclass 28, count 0 2006.182.08:14:51.21#ibcon#about to read 6, iclass 28, count 0 2006.182.08:14:51.21#ibcon#read 6, iclass 28, count 0 2006.182.08:14:51.21#ibcon#end of sib2, iclass 28, count 0 2006.182.08:14:51.21#ibcon#*after write, iclass 28, count 0 2006.182.08:14:51.21#ibcon#*before return 0, iclass 28, count 0 2006.182.08:14:51.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:51.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:14:51.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:14:51.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:14:51.21$vc4f8/vblo=3,656.99 2006.182.08:14:51.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.08:14:51.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.08:14:51.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:51.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:51.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:51.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:51.21#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:14:51.21#ibcon#first serial, iclass 30, count 0 2006.182.08:14:51.21#ibcon#enter sib2, iclass 30, count 0 2006.182.08:14:51.21#ibcon#flushed, iclass 30, count 0 2006.182.08:14:51.21#ibcon#about to write, iclass 30, count 0 2006.182.08:14:51.21#ibcon#wrote, iclass 30, count 0 2006.182.08:14:51.21#ibcon#about to read 3, iclass 30, count 0 2006.182.08:14:51.23#ibcon#read 3, iclass 30, count 0 2006.182.08:14:51.23#ibcon#about to read 4, iclass 30, count 0 2006.182.08:14:51.23#ibcon#read 4, iclass 30, count 0 2006.182.08:14:51.23#ibcon#about to read 5, iclass 30, count 0 2006.182.08:14:51.23#ibcon#read 5, iclass 30, count 0 2006.182.08:14:51.23#ibcon#about to read 6, iclass 30, count 0 2006.182.08:14:51.23#ibcon#read 6, iclass 30, count 0 2006.182.08:14:51.23#ibcon#end of sib2, iclass 30, count 0 2006.182.08:14:51.23#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:14:51.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:14:51.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:14:51.23#ibcon#*before write, iclass 30, count 0 2006.182.08:14:51.23#ibcon#enter sib2, iclass 30, count 0 2006.182.08:14:51.23#ibcon#flushed, iclass 30, count 0 2006.182.08:14:51.23#ibcon#about to write, iclass 30, count 0 2006.182.08:14:51.23#ibcon#wrote, iclass 30, count 0 2006.182.08:14:51.23#ibcon#about to read 3, iclass 30, count 0 2006.182.08:14:51.27#ibcon#read 3, iclass 30, count 0 2006.182.08:14:51.27#ibcon#about to read 4, iclass 30, count 0 2006.182.08:14:51.27#ibcon#read 4, iclass 30, count 0 2006.182.08:14:51.27#ibcon#about to read 5, iclass 30, count 0 2006.182.08:14:51.27#ibcon#read 5, iclass 30, count 0 2006.182.08:14:51.27#ibcon#about to read 6, iclass 30, count 0 2006.182.08:14:51.27#ibcon#read 6, iclass 30, count 0 2006.182.08:14:51.27#ibcon#end of sib2, iclass 30, count 0 2006.182.08:14:51.27#ibcon#*after write, iclass 30, count 0 2006.182.08:14:51.27#ibcon#*before return 0, iclass 30, count 0 2006.182.08:14:51.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:51.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:14:51.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:14:51.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:14:51.27$vc4f8/vb=3,4 2006.182.08:14:51.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.08:14:51.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.08:14:51.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:51.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:51.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:51.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:51.33#ibcon#enter wrdev, iclass 32, count 2 2006.182.08:14:51.33#ibcon#first serial, iclass 32, count 2 2006.182.08:14:51.33#ibcon#enter sib2, iclass 32, count 2 2006.182.08:14:51.33#ibcon#flushed, iclass 32, count 2 2006.182.08:14:51.33#ibcon#about to write, iclass 32, count 2 2006.182.08:14:51.33#ibcon#wrote, iclass 32, count 2 2006.182.08:14:51.33#ibcon#about to read 3, iclass 32, count 2 2006.182.08:14:51.35#ibcon#read 3, iclass 32, count 2 2006.182.08:14:51.35#ibcon#about to read 4, iclass 32, count 2 2006.182.08:14:51.35#ibcon#read 4, iclass 32, count 2 2006.182.08:14:51.35#ibcon#about to read 5, iclass 32, count 2 2006.182.08:14:51.35#ibcon#read 5, iclass 32, count 2 2006.182.08:14:51.35#ibcon#about to read 6, iclass 32, count 2 2006.182.08:14:51.35#ibcon#read 6, iclass 32, count 2 2006.182.08:14:51.35#ibcon#end of sib2, iclass 32, count 2 2006.182.08:14:51.35#ibcon#*mode == 0, iclass 32, count 2 2006.182.08:14:51.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.08:14:51.35#ibcon#[27=AT03-04\r\n] 2006.182.08:14:51.35#ibcon#*before write, iclass 32, count 2 2006.182.08:14:51.35#ibcon#enter sib2, iclass 32, count 2 2006.182.08:14:51.35#ibcon#flushed, iclass 32, count 2 2006.182.08:14:51.35#ibcon#about to write, iclass 32, count 2 2006.182.08:14:51.35#ibcon#wrote, iclass 32, count 2 2006.182.08:14:51.35#ibcon#about to read 3, iclass 32, count 2 2006.182.08:14:51.38#ibcon#read 3, iclass 32, count 2 2006.182.08:14:51.38#ibcon#about to read 4, iclass 32, count 2 2006.182.08:14:51.38#ibcon#read 4, iclass 32, count 2 2006.182.08:14:51.38#ibcon#about to read 5, iclass 32, count 2 2006.182.08:14:51.38#ibcon#read 5, iclass 32, count 2 2006.182.08:14:51.38#ibcon#about to read 6, iclass 32, count 2 2006.182.08:14:51.38#ibcon#read 6, iclass 32, count 2 2006.182.08:14:51.38#ibcon#end of sib2, iclass 32, count 2 2006.182.08:14:51.38#ibcon#*after write, iclass 32, count 2 2006.182.08:14:51.38#ibcon#*before return 0, iclass 32, count 2 2006.182.08:14:51.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:51.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:14:51.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.08:14:51.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:51.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:51.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:51.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:51.50#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:14:51.50#ibcon#first serial, iclass 32, count 0 2006.182.08:14:51.50#ibcon#enter sib2, iclass 32, count 0 2006.182.08:14:51.50#ibcon#flushed, iclass 32, count 0 2006.182.08:14:51.50#ibcon#about to write, iclass 32, count 0 2006.182.08:14:51.50#ibcon#wrote, iclass 32, count 0 2006.182.08:14:51.50#ibcon#about to read 3, iclass 32, count 0 2006.182.08:14:51.52#ibcon#read 3, iclass 32, count 0 2006.182.08:14:51.52#ibcon#about to read 4, iclass 32, count 0 2006.182.08:14:51.52#ibcon#read 4, iclass 32, count 0 2006.182.08:14:51.52#ibcon#about to read 5, iclass 32, count 0 2006.182.08:14:51.52#ibcon#read 5, iclass 32, count 0 2006.182.08:14:51.52#ibcon#about to read 6, iclass 32, count 0 2006.182.08:14:51.52#ibcon#read 6, iclass 32, count 0 2006.182.08:14:51.52#ibcon#end of sib2, iclass 32, count 0 2006.182.08:14:51.52#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:14:51.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:14:51.52#ibcon#[27=USB\r\n] 2006.182.08:14:51.52#ibcon#*before write, iclass 32, count 0 2006.182.08:14:51.52#ibcon#enter sib2, iclass 32, count 0 2006.182.08:14:51.52#ibcon#flushed, iclass 32, count 0 2006.182.08:14:51.52#ibcon#about to write, iclass 32, count 0 2006.182.08:14:51.52#ibcon#wrote, iclass 32, count 0 2006.182.08:14:51.52#ibcon#about to read 3, iclass 32, count 0 2006.182.08:14:51.55#ibcon#read 3, iclass 32, count 0 2006.182.08:14:51.55#ibcon#about to read 4, iclass 32, count 0 2006.182.08:14:51.55#ibcon#read 4, iclass 32, count 0 2006.182.08:14:51.55#ibcon#about to read 5, iclass 32, count 0 2006.182.08:14:51.55#ibcon#read 5, iclass 32, count 0 2006.182.08:14:51.55#ibcon#about to read 6, iclass 32, count 0 2006.182.08:14:51.55#ibcon#read 6, iclass 32, count 0 2006.182.08:14:51.55#ibcon#end of sib2, iclass 32, count 0 2006.182.08:14:51.55#ibcon#*after write, iclass 32, count 0 2006.182.08:14:51.55#ibcon#*before return 0, iclass 32, count 0 2006.182.08:14:51.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:51.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:14:51.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:14:51.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:14:51.55$vc4f8/vblo=4,712.99 2006.182.08:14:51.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.08:14:51.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.08:14:51.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:51.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:51.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:51.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:51.55#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:14:51.55#ibcon#first serial, iclass 34, count 0 2006.182.08:14:51.55#ibcon#enter sib2, iclass 34, count 0 2006.182.08:14:51.55#ibcon#flushed, iclass 34, count 0 2006.182.08:14:51.55#ibcon#about to write, iclass 34, count 0 2006.182.08:14:51.55#ibcon#wrote, iclass 34, count 0 2006.182.08:14:51.55#ibcon#about to read 3, iclass 34, count 0 2006.182.08:14:51.57#ibcon#read 3, iclass 34, count 0 2006.182.08:14:51.57#ibcon#about to read 4, iclass 34, count 0 2006.182.08:14:51.57#ibcon#read 4, iclass 34, count 0 2006.182.08:14:51.57#ibcon#about to read 5, iclass 34, count 0 2006.182.08:14:51.57#ibcon#read 5, iclass 34, count 0 2006.182.08:14:51.57#ibcon#about to read 6, iclass 34, count 0 2006.182.08:14:51.57#ibcon#read 6, iclass 34, count 0 2006.182.08:14:51.57#ibcon#end of sib2, iclass 34, count 0 2006.182.08:14:51.57#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:14:51.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:14:51.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:14:51.57#ibcon#*before write, iclass 34, count 0 2006.182.08:14:51.57#ibcon#enter sib2, iclass 34, count 0 2006.182.08:14:51.57#ibcon#flushed, iclass 34, count 0 2006.182.08:14:51.57#ibcon#about to write, iclass 34, count 0 2006.182.08:14:51.57#ibcon#wrote, iclass 34, count 0 2006.182.08:14:51.57#ibcon#about to read 3, iclass 34, count 0 2006.182.08:14:51.61#ibcon#read 3, iclass 34, count 0 2006.182.08:14:51.61#ibcon#about to read 4, iclass 34, count 0 2006.182.08:14:51.61#ibcon#read 4, iclass 34, count 0 2006.182.08:14:51.61#ibcon#about to read 5, iclass 34, count 0 2006.182.08:14:51.61#ibcon#read 5, iclass 34, count 0 2006.182.08:14:51.61#ibcon#about to read 6, iclass 34, count 0 2006.182.08:14:51.61#ibcon#read 6, iclass 34, count 0 2006.182.08:14:51.61#ibcon#end of sib2, iclass 34, count 0 2006.182.08:14:51.61#ibcon#*after write, iclass 34, count 0 2006.182.08:14:51.61#ibcon#*before return 0, iclass 34, count 0 2006.182.08:14:51.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:51.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:14:51.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:14:51.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:14:51.61$vc4f8/vb=4,4 2006.182.08:14:51.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.182.08:14:51.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.182.08:14:51.61#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:51.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:51.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:51.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:51.67#ibcon#enter wrdev, iclass 36, count 2 2006.182.08:14:51.67#ibcon#first serial, iclass 36, count 2 2006.182.08:14:51.67#ibcon#enter sib2, iclass 36, count 2 2006.182.08:14:51.67#ibcon#flushed, iclass 36, count 2 2006.182.08:14:51.67#ibcon#about to write, iclass 36, count 2 2006.182.08:14:51.67#ibcon#wrote, iclass 36, count 2 2006.182.08:14:51.67#ibcon#about to read 3, iclass 36, count 2 2006.182.08:14:51.69#ibcon#read 3, iclass 36, count 2 2006.182.08:14:51.69#ibcon#about to read 4, iclass 36, count 2 2006.182.08:14:51.69#ibcon#read 4, iclass 36, count 2 2006.182.08:14:51.69#ibcon#about to read 5, iclass 36, count 2 2006.182.08:14:51.69#ibcon#read 5, iclass 36, count 2 2006.182.08:14:51.69#ibcon#about to read 6, iclass 36, count 2 2006.182.08:14:51.69#ibcon#read 6, iclass 36, count 2 2006.182.08:14:51.69#ibcon#end of sib2, iclass 36, count 2 2006.182.08:14:51.69#ibcon#*mode == 0, iclass 36, count 2 2006.182.08:14:51.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.182.08:14:51.69#ibcon#[27=AT04-04\r\n] 2006.182.08:14:51.69#ibcon#*before write, iclass 36, count 2 2006.182.08:14:51.69#ibcon#enter sib2, iclass 36, count 2 2006.182.08:14:51.69#ibcon#flushed, iclass 36, count 2 2006.182.08:14:51.69#ibcon#about to write, iclass 36, count 2 2006.182.08:14:51.69#ibcon#wrote, iclass 36, count 2 2006.182.08:14:51.69#ibcon#about to read 3, iclass 36, count 2 2006.182.08:14:51.72#ibcon#read 3, iclass 36, count 2 2006.182.08:14:51.72#ibcon#about to read 4, iclass 36, count 2 2006.182.08:14:51.72#ibcon#read 4, iclass 36, count 2 2006.182.08:14:51.72#ibcon#about to read 5, iclass 36, count 2 2006.182.08:14:51.72#ibcon#read 5, iclass 36, count 2 2006.182.08:14:51.72#ibcon#about to read 6, iclass 36, count 2 2006.182.08:14:51.72#ibcon#read 6, iclass 36, count 2 2006.182.08:14:51.72#ibcon#end of sib2, iclass 36, count 2 2006.182.08:14:51.72#ibcon#*after write, iclass 36, count 2 2006.182.08:14:51.72#ibcon#*before return 0, iclass 36, count 2 2006.182.08:14:51.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:51.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:14:51.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.182.08:14:51.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:51.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:51.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:51.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:51.84#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:14:51.84#ibcon#first serial, iclass 36, count 0 2006.182.08:14:51.84#ibcon#enter sib2, iclass 36, count 0 2006.182.08:14:51.84#ibcon#flushed, iclass 36, count 0 2006.182.08:14:51.84#ibcon#about to write, iclass 36, count 0 2006.182.08:14:51.84#ibcon#wrote, iclass 36, count 0 2006.182.08:14:51.84#ibcon#about to read 3, iclass 36, count 0 2006.182.08:14:51.86#ibcon#read 3, iclass 36, count 0 2006.182.08:14:51.86#ibcon#about to read 4, iclass 36, count 0 2006.182.08:14:51.86#ibcon#read 4, iclass 36, count 0 2006.182.08:14:51.86#ibcon#about to read 5, iclass 36, count 0 2006.182.08:14:51.86#ibcon#read 5, iclass 36, count 0 2006.182.08:14:51.86#ibcon#about to read 6, iclass 36, count 0 2006.182.08:14:51.86#ibcon#read 6, iclass 36, count 0 2006.182.08:14:51.86#ibcon#end of sib2, iclass 36, count 0 2006.182.08:14:51.86#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:14:51.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:14:51.86#ibcon#[27=USB\r\n] 2006.182.08:14:51.86#ibcon#*before write, iclass 36, count 0 2006.182.08:14:51.86#ibcon#enter sib2, iclass 36, count 0 2006.182.08:14:51.86#ibcon#flushed, iclass 36, count 0 2006.182.08:14:51.86#ibcon#about to write, iclass 36, count 0 2006.182.08:14:51.86#ibcon#wrote, iclass 36, count 0 2006.182.08:14:51.86#ibcon#about to read 3, iclass 36, count 0 2006.182.08:14:51.89#ibcon#read 3, iclass 36, count 0 2006.182.08:14:51.89#ibcon#about to read 4, iclass 36, count 0 2006.182.08:14:51.89#ibcon#read 4, iclass 36, count 0 2006.182.08:14:51.89#ibcon#about to read 5, iclass 36, count 0 2006.182.08:14:51.89#ibcon#read 5, iclass 36, count 0 2006.182.08:14:51.89#ibcon#about to read 6, iclass 36, count 0 2006.182.08:14:51.89#ibcon#read 6, iclass 36, count 0 2006.182.08:14:51.89#ibcon#end of sib2, iclass 36, count 0 2006.182.08:14:51.89#ibcon#*after write, iclass 36, count 0 2006.182.08:14:51.89#ibcon#*before return 0, iclass 36, count 0 2006.182.08:14:51.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:51.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:14:51.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:14:51.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:14:51.89$vc4f8/vblo=5,744.99 2006.182.08:14:51.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.08:14:51.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.08:14:51.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:51.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:51.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:51.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:51.89#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:14:51.89#ibcon#first serial, iclass 38, count 0 2006.182.08:14:51.89#ibcon#enter sib2, iclass 38, count 0 2006.182.08:14:51.89#ibcon#flushed, iclass 38, count 0 2006.182.08:14:51.89#ibcon#about to write, iclass 38, count 0 2006.182.08:14:51.89#ibcon#wrote, iclass 38, count 0 2006.182.08:14:51.89#ibcon#about to read 3, iclass 38, count 0 2006.182.08:14:51.92#ibcon#read 3, iclass 38, count 0 2006.182.08:14:51.92#ibcon#about to read 4, iclass 38, count 0 2006.182.08:14:51.92#ibcon#read 4, iclass 38, count 0 2006.182.08:14:51.92#ibcon#about to read 5, iclass 38, count 0 2006.182.08:14:51.92#ibcon#read 5, iclass 38, count 0 2006.182.08:14:51.92#ibcon#about to read 6, iclass 38, count 0 2006.182.08:14:51.92#ibcon#read 6, iclass 38, count 0 2006.182.08:14:51.92#ibcon#end of sib2, iclass 38, count 0 2006.182.08:14:51.92#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:14:51.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:14:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:14:51.92#ibcon#*before write, iclass 38, count 0 2006.182.08:14:51.92#ibcon#enter sib2, iclass 38, count 0 2006.182.08:14:51.92#ibcon#flushed, iclass 38, count 0 2006.182.08:14:51.92#ibcon#about to write, iclass 38, count 0 2006.182.08:14:51.92#ibcon#wrote, iclass 38, count 0 2006.182.08:14:51.92#ibcon#about to read 3, iclass 38, count 0 2006.182.08:14:51.96#ibcon#read 3, iclass 38, count 0 2006.182.08:14:51.96#ibcon#about to read 4, iclass 38, count 0 2006.182.08:14:51.96#ibcon#read 4, iclass 38, count 0 2006.182.08:14:51.96#ibcon#about to read 5, iclass 38, count 0 2006.182.08:14:51.96#ibcon#read 5, iclass 38, count 0 2006.182.08:14:51.96#ibcon#about to read 6, iclass 38, count 0 2006.182.08:14:51.96#ibcon#read 6, iclass 38, count 0 2006.182.08:14:51.96#ibcon#end of sib2, iclass 38, count 0 2006.182.08:14:51.96#ibcon#*after write, iclass 38, count 0 2006.182.08:14:51.96#ibcon#*before return 0, iclass 38, count 0 2006.182.08:14:51.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:51.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:14:51.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:14:51.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:14:51.96$vc4f8/vb=5,4 2006.182.08:14:51.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.08:14:51.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.08:14:51.96#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:51.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:52.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:52.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:52.01#ibcon#enter wrdev, iclass 40, count 2 2006.182.08:14:52.01#ibcon#first serial, iclass 40, count 2 2006.182.08:14:52.01#ibcon#enter sib2, iclass 40, count 2 2006.182.08:14:52.01#ibcon#flushed, iclass 40, count 2 2006.182.08:14:52.01#ibcon#about to write, iclass 40, count 2 2006.182.08:14:52.01#ibcon#wrote, iclass 40, count 2 2006.182.08:14:52.01#ibcon#about to read 3, iclass 40, count 2 2006.182.08:14:52.03#ibcon#read 3, iclass 40, count 2 2006.182.08:14:52.03#ibcon#about to read 4, iclass 40, count 2 2006.182.08:14:52.03#ibcon#read 4, iclass 40, count 2 2006.182.08:14:52.03#ibcon#about to read 5, iclass 40, count 2 2006.182.08:14:52.03#ibcon#read 5, iclass 40, count 2 2006.182.08:14:52.03#ibcon#about to read 6, iclass 40, count 2 2006.182.08:14:52.03#ibcon#read 6, iclass 40, count 2 2006.182.08:14:52.03#ibcon#end of sib2, iclass 40, count 2 2006.182.08:14:52.03#ibcon#*mode == 0, iclass 40, count 2 2006.182.08:14:52.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.08:14:52.03#ibcon#[27=AT05-04\r\n] 2006.182.08:14:52.03#ibcon#*before write, iclass 40, count 2 2006.182.08:14:52.03#ibcon#enter sib2, iclass 40, count 2 2006.182.08:14:52.03#ibcon#flushed, iclass 40, count 2 2006.182.08:14:52.03#ibcon#about to write, iclass 40, count 2 2006.182.08:14:52.03#ibcon#wrote, iclass 40, count 2 2006.182.08:14:52.03#ibcon#about to read 3, iclass 40, count 2 2006.182.08:14:52.06#ibcon#read 3, iclass 40, count 2 2006.182.08:14:52.06#ibcon#about to read 4, iclass 40, count 2 2006.182.08:14:52.06#ibcon#read 4, iclass 40, count 2 2006.182.08:14:52.06#ibcon#about to read 5, iclass 40, count 2 2006.182.08:14:52.06#ibcon#read 5, iclass 40, count 2 2006.182.08:14:52.06#ibcon#about to read 6, iclass 40, count 2 2006.182.08:14:52.06#ibcon#read 6, iclass 40, count 2 2006.182.08:14:52.06#ibcon#end of sib2, iclass 40, count 2 2006.182.08:14:52.06#ibcon#*after write, iclass 40, count 2 2006.182.08:14:52.06#ibcon#*before return 0, iclass 40, count 2 2006.182.08:14:52.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:52.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:14:52.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.08:14:52.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:52.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:52.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:52.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:52.18#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:14:52.18#ibcon#first serial, iclass 40, count 0 2006.182.08:14:52.18#ibcon#enter sib2, iclass 40, count 0 2006.182.08:14:52.18#ibcon#flushed, iclass 40, count 0 2006.182.08:14:52.18#ibcon#about to write, iclass 40, count 0 2006.182.08:14:52.18#ibcon#wrote, iclass 40, count 0 2006.182.08:14:52.18#ibcon#about to read 3, iclass 40, count 0 2006.182.08:14:52.20#ibcon#read 3, iclass 40, count 0 2006.182.08:14:52.20#ibcon#about to read 4, iclass 40, count 0 2006.182.08:14:52.20#ibcon#read 4, iclass 40, count 0 2006.182.08:14:52.20#ibcon#about to read 5, iclass 40, count 0 2006.182.08:14:52.20#ibcon#read 5, iclass 40, count 0 2006.182.08:14:52.20#ibcon#about to read 6, iclass 40, count 0 2006.182.08:14:52.20#ibcon#read 6, iclass 40, count 0 2006.182.08:14:52.20#ibcon#end of sib2, iclass 40, count 0 2006.182.08:14:52.20#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:14:52.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:14:52.20#ibcon#[27=USB\r\n] 2006.182.08:14:52.20#ibcon#*before write, iclass 40, count 0 2006.182.08:14:52.20#ibcon#enter sib2, iclass 40, count 0 2006.182.08:14:52.20#ibcon#flushed, iclass 40, count 0 2006.182.08:14:52.20#ibcon#about to write, iclass 40, count 0 2006.182.08:14:52.20#ibcon#wrote, iclass 40, count 0 2006.182.08:14:52.20#ibcon#about to read 3, iclass 40, count 0 2006.182.08:14:52.23#ibcon#read 3, iclass 40, count 0 2006.182.08:14:52.23#ibcon#about to read 4, iclass 40, count 0 2006.182.08:14:52.23#ibcon#read 4, iclass 40, count 0 2006.182.08:14:52.23#ibcon#about to read 5, iclass 40, count 0 2006.182.08:14:52.23#ibcon#read 5, iclass 40, count 0 2006.182.08:14:52.23#ibcon#about to read 6, iclass 40, count 0 2006.182.08:14:52.23#ibcon#read 6, iclass 40, count 0 2006.182.08:14:52.23#ibcon#end of sib2, iclass 40, count 0 2006.182.08:14:52.23#ibcon#*after write, iclass 40, count 0 2006.182.08:14:52.23#ibcon#*before return 0, iclass 40, count 0 2006.182.08:14:52.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:52.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:14:52.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:14:52.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:14:52.23$vc4f8/vblo=6,752.99 2006.182.08:14:52.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.08:14:52.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.08:14:52.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:14:52.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:52.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:52.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:52.23#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:14:52.23#ibcon#first serial, iclass 4, count 0 2006.182.08:14:52.23#ibcon#enter sib2, iclass 4, count 0 2006.182.08:14:52.23#ibcon#flushed, iclass 4, count 0 2006.182.08:14:52.23#ibcon#about to write, iclass 4, count 0 2006.182.08:14:52.23#ibcon#wrote, iclass 4, count 0 2006.182.08:14:52.23#ibcon#about to read 3, iclass 4, count 0 2006.182.08:14:52.25#ibcon#read 3, iclass 4, count 0 2006.182.08:14:52.25#ibcon#about to read 4, iclass 4, count 0 2006.182.08:14:52.25#ibcon#read 4, iclass 4, count 0 2006.182.08:14:52.25#ibcon#about to read 5, iclass 4, count 0 2006.182.08:14:52.25#ibcon#read 5, iclass 4, count 0 2006.182.08:14:52.25#ibcon#about to read 6, iclass 4, count 0 2006.182.08:14:52.25#ibcon#read 6, iclass 4, count 0 2006.182.08:14:52.25#ibcon#end of sib2, iclass 4, count 0 2006.182.08:14:52.25#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:14:52.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:14:52.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:14:52.25#ibcon#*before write, iclass 4, count 0 2006.182.08:14:52.25#ibcon#enter sib2, iclass 4, count 0 2006.182.08:14:52.25#ibcon#flushed, iclass 4, count 0 2006.182.08:14:52.25#ibcon#about to write, iclass 4, count 0 2006.182.08:14:52.25#ibcon#wrote, iclass 4, count 0 2006.182.08:14:52.25#ibcon#about to read 3, iclass 4, count 0 2006.182.08:14:52.29#ibcon#read 3, iclass 4, count 0 2006.182.08:14:52.29#ibcon#about to read 4, iclass 4, count 0 2006.182.08:14:52.29#ibcon#read 4, iclass 4, count 0 2006.182.08:14:52.29#ibcon#about to read 5, iclass 4, count 0 2006.182.08:14:52.29#ibcon#read 5, iclass 4, count 0 2006.182.08:14:52.29#ibcon#about to read 6, iclass 4, count 0 2006.182.08:14:52.29#ibcon#read 6, iclass 4, count 0 2006.182.08:14:52.29#ibcon#end of sib2, iclass 4, count 0 2006.182.08:14:52.29#ibcon#*after write, iclass 4, count 0 2006.182.08:14:52.29#ibcon#*before return 0, iclass 4, count 0 2006.182.08:14:52.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:52.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:14:52.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:14:52.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:14:52.29$vc4f8/vb=6,4 2006.182.08:14:52.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.08:14:52.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.08:14:52.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:14:52.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:52.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:52.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:52.35#ibcon#enter wrdev, iclass 6, count 2 2006.182.08:14:52.35#ibcon#first serial, iclass 6, count 2 2006.182.08:14:52.35#ibcon#enter sib2, iclass 6, count 2 2006.182.08:14:52.35#ibcon#flushed, iclass 6, count 2 2006.182.08:14:52.35#ibcon#about to write, iclass 6, count 2 2006.182.08:14:52.35#ibcon#wrote, iclass 6, count 2 2006.182.08:14:52.35#ibcon#about to read 3, iclass 6, count 2 2006.182.08:14:52.37#ibcon#read 3, iclass 6, count 2 2006.182.08:14:52.37#ibcon#about to read 4, iclass 6, count 2 2006.182.08:14:52.37#ibcon#read 4, iclass 6, count 2 2006.182.08:14:52.37#ibcon#about to read 5, iclass 6, count 2 2006.182.08:14:52.37#ibcon#read 5, iclass 6, count 2 2006.182.08:14:52.37#ibcon#about to read 6, iclass 6, count 2 2006.182.08:14:52.37#ibcon#read 6, iclass 6, count 2 2006.182.08:14:52.37#ibcon#end of sib2, iclass 6, count 2 2006.182.08:14:52.37#ibcon#*mode == 0, iclass 6, count 2 2006.182.08:14:52.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.08:14:52.37#ibcon#[27=AT06-04\r\n] 2006.182.08:14:52.37#ibcon#*before write, iclass 6, count 2 2006.182.08:14:52.37#ibcon#enter sib2, iclass 6, count 2 2006.182.08:14:52.37#ibcon#flushed, iclass 6, count 2 2006.182.08:14:52.37#ibcon#about to write, iclass 6, count 2 2006.182.08:14:52.37#ibcon#wrote, iclass 6, count 2 2006.182.08:14:52.37#ibcon#about to read 3, iclass 6, count 2 2006.182.08:14:52.40#ibcon#read 3, iclass 6, count 2 2006.182.08:14:52.40#ibcon#about to read 4, iclass 6, count 2 2006.182.08:14:52.40#ibcon#read 4, iclass 6, count 2 2006.182.08:14:52.40#ibcon#about to read 5, iclass 6, count 2 2006.182.08:14:52.40#ibcon#read 5, iclass 6, count 2 2006.182.08:14:52.40#ibcon#about to read 6, iclass 6, count 2 2006.182.08:14:52.40#ibcon#read 6, iclass 6, count 2 2006.182.08:14:52.40#ibcon#end of sib2, iclass 6, count 2 2006.182.08:14:52.40#ibcon#*after write, iclass 6, count 2 2006.182.08:14:52.40#ibcon#*before return 0, iclass 6, count 2 2006.182.08:14:52.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:52.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:14:52.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.08:14:52.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:14:52.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:52.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:52.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:52.52#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:14:52.52#ibcon#first serial, iclass 6, count 0 2006.182.08:14:52.52#ibcon#enter sib2, iclass 6, count 0 2006.182.08:14:52.52#ibcon#flushed, iclass 6, count 0 2006.182.08:14:52.52#ibcon#about to write, iclass 6, count 0 2006.182.08:14:52.52#ibcon#wrote, iclass 6, count 0 2006.182.08:14:52.52#ibcon#about to read 3, iclass 6, count 0 2006.182.08:14:52.54#ibcon#read 3, iclass 6, count 0 2006.182.08:14:52.54#ibcon#about to read 4, iclass 6, count 0 2006.182.08:14:52.54#ibcon#read 4, iclass 6, count 0 2006.182.08:14:52.54#ibcon#about to read 5, iclass 6, count 0 2006.182.08:14:52.54#ibcon#read 5, iclass 6, count 0 2006.182.08:14:52.54#ibcon#about to read 6, iclass 6, count 0 2006.182.08:14:52.54#ibcon#read 6, iclass 6, count 0 2006.182.08:14:52.54#ibcon#end of sib2, iclass 6, count 0 2006.182.08:14:52.54#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:14:52.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:14:52.54#ibcon#[27=USB\r\n] 2006.182.08:14:52.54#ibcon#*before write, iclass 6, count 0 2006.182.08:14:52.54#ibcon#enter sib2, iclass 6, count 0 2006.182.08:14:52.54#ibcon#flushed, iclass 6, count 0 2006.182.08:14:52.54#ibcon#about to write, iclass 6, count 0 2006.182.08:14:52.54#ibcon#wrote, iclass 6, count 0 2006.182.08:14:52.54#ibcon#about to read 3, iclass 6, count 0 2006.182.08:14:52.57#ibcon#read 3, iclass 6, count 0 2006.182.08:14:52.57#ibcon#about to read 4, iclass 6, count 0 2006.182.08:14:52.57#ibcon#read 4, iclass 6, count 0 2006.182.08:14:52.57#ibcon#about to read 5, iclass 6, count 0 2006.182.08:14:52.57#ibcon#read 5, iclass 6, count 0 2006.182.08:14:52.57#ibcon#about to read 6, iclass 6, count 0 2006.182.08:14:52.57#ibcon#read 6, iclass 6, count 0 2006.182.08:14:52.57#ibcon#end of sib2, iclass 6, count 0 2006.182.08:14:52.57#ibcon#*after write, iclass 6, count 0 2006.182.08:14:52.57#ibcon#*before return 0, iclass 6, count 0 2006.182.08:14:52.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:52.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:14:52.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:14:52.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:14:52.57$vc4f8/vabw=wide 2006.182.08:14:52.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.08:14:52.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.08:14:52.57#ibcon#ireg 8 cls_cnt 0 2006.182.08:14:52.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:52.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:52.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:52.57#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:14:52.57#ibcon#first serial, iclass 10, count 0 2006.182.08:14:52.57#ibcon#enter sib2, iclass 10, count 0 2006.182.08:14:52.57#ibcon#flushed, iclass 10, count 0 2006.182.08:14:52.57#ibcon#about to write, iclass 10, count 0 2006.182.08:14:52.57#ibcon#wrote, iclass 10, count 0 2006.182.08:14:52.57#ibcon#about to read 3, iclass 10, count 0 2006.182.08:14:52.59#ibcon#read 3, iclass 10, count 0 2006.182.08:14:52.59#ibcon#about to read 4, iclass 10, count 0 2006.182.08:14:52.59#ibcon#read 4, iclass 10, count 0 2006.182.08:14:52.59#ibcon#about to read 5, iclass 10, count 0 2006.182.08:14:52.59#ibcon#read 5, iclass 10, count 0 2006.182.08:14:52.59#ibcon#about to read 6, iclass 10, count 0 2006.182.08:14:52.59#ibcon#read 6, iclass 10, count 0 2006.182.08:14:52.59#ibcon#end of sib2, iclass 10, count 0 2006.182.08:14:52.59#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:14:52.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:14:52.59#ibcon#[25=BW32\r\n] 2006.182.08:14:52.59#ibcon#*before write, iclass 10, count 0 2006.182.08:14:52.59#ibcon#enter sib2, iclass 10, count 0 2006.182.08:14:52.59#ibcon#flushed, iclass 10, count 0 2006.182.08:14:52.59#ibcon#about to write, iclass 10, count 0 2006.182.08:14:52.59#ibcon#wrote, iclass 10, count 0 2006.182.08:14:52.59#ibcon#about to read 3, iclass 10, count 0 2006.182.08:14:52.62#ibcon#read 3, iclass 10, count 0 2006.182.08:14:52.62#ibcon#about to read 4, iclass 10, count 0 2006.182.08:14:52.62#ibcon#read 4, iclass 10, count 0 2006.182.08:14:52.62#ibcon#about to read 5, iclass 10, count 0 2006.182.08:14:52.62#ibcon#read 5, iclass 10, count 0 2006.182.08:14:52.62#ibcon#about to read 6, iclass 10, count 0 2006.182.08:14:52.62#ibcon#read 6, iclass 10, count 0 2006.182.08:14:52.62#ibcon#end of sib2, iclass 10, count 0 2006.182.08:14:52.62#ibcon#*after write, iclass 10, count 0 2006.182.08:14:52.62#ibcon#*before return 0, iclass 10, count 0 2006.182.08:14:52.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:52.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:14:52.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:14:52.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:14:52.62$vc4f8/vbbw=wide 2006.182.08:14:52.62#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.08:14:52.62#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.08:14:52.62#ibcon#ireg 8 cls_cnt 0 2006.182.08:14:52.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:14:52.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:14:52.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:14:52.69#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:14:52.69#ibcon#first serial, iclass 12, count 0 2006.182.08:14:52.69#ibcon#enter sib2, iclass 12, count 0 2006.182.08:14:52.69#ibcon#flushed, iclass 12, count 0 2006.182.08:14:52.69#ibcon#about to write, iclass 12, count 0 2006.182.08:14:52.69#ibcon#wrote, iclass 12, count 0 2006.182.08:14:52.69#ibcon#about to read 3, iclass 12, count 0 2006.182.08:14:52.71#ibcon#read 3, iclass 12, count 0 2006.182.08:14:52.71#ibcon#about to read 4, iclass 12, count 0 2006.182.08:14:52.71#ibcon#read 4, iclass 12, count 0 2006.182.08:14:52.71#ibcon#about to read 5, iclass 12, count 0 2006.182.08:14:52.71#ibcon#read 5, iclass 12, count 0 2006.182.08:14:52.71#ibcon#about to read 6, iclass 12, count 0 2006.182.08:14:52.71#ibcon#read 6, iclass 12, count 0 2006.182.08:14:52.71#ibcon#end of sib2, iclass 12, count 0 2006.182.08:14:52.71#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:14:52.71#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:14:52.71#ibcon#[27=BW32\r\n] 2006.182.08:14:52.71#ibcon#*before write, iclass 12, count 0 2006.182.08:14:52.71#ibcon#enter sib2, iclass 12, count 0 2006.182.08:14:52.71#ibcon#flushed, iclass 12, count 0 2006.182.08:14:52.71#ibcon#about to write, iclass 12, count 0 2006.182.08:14:52.71#ibcon#wrote, iclass 12, count 0 2006.182.08:14:52.71#ibcon#about to read 3, iclass 12, count 0 2006.182.08:14:52.74#ibcon#read 3, iclass 12, count 0 2006.182.08:14:52.74#ibcon#about to read 4, iclass 12, count 0 2006.182.08:14:52.74#ibcon#read 4, iclass 12, count 0 2006.182.08:14:52.74#ibcon#about to read 5, iclass 12, count 0 2006.182.08:14:52.74#ibcon#read 5, iclass 12, count 0 2006.182.08:14:52.74#ibcon#about to read 6, iclass 12, count 0 2006.182.08:14:52.74#ibcon#read 6, iclass 12, count 0 2006.182.08:14:52.74#ibcon#end of sib2, iclass 12, count 0 2006.182.08:14:52.74#ibcon#*after write, iclass 12, count 0 2006.182.08:14:52.74#ibcon#*before return 0, iclass 12, count 0 2006.182.08:14:52.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:14:52.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:14:52.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:14:52.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:14:52.74$4f8m12a/ifd4f 2006.182.08:14:52.74$ifd4f/lo= 2006.182.08:14:52.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:14:52.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:14:52.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:14:52.74$ifd4f/patch= 2006.182.08:14:52.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:14:52.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:14:52.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:14:52.74$4f8m12a/"form=m,16.000,1:2 2006.182.08:14:52.74$4f8m12a/"tpicd 2006.182.08:14:52.74$4f8m12a/echo=off 2006.182.08:14:52.74$4f8m12a/xlog=off 2006.182.08:14:52.74:!2006.182.08:15:20 2006.182.08:14:58.14#trakl#Source acquired 2006.182.08:14:59.14#flagr#flagr/antenna,acquired 2006.182.08:15:20.00:preob 2006.182.08:15:21.14/onsource/TRACKING 2006.182.08:15:21.14:!2006.182.08:15:30 2006.182.08:15:30.00:data_valid=on 2006.182.08:15:30.00:midob 2006.182.08:15:30.14/onsource/TRACKING 2006.182.08:15:30.14/wx/27.81,1002.9,83 2006.182.08:15:30.25/cable/+6.4647E-03 2006.182.08:15:31.34/va/01,08,usb,yes,29,31 2006.182.08:15:31.34/va/02,07,usb,yes,29,31 2006.182.08:15:31.34/va/03,06,usb,yes,31,31 2006.182.08:15:31.34/va/04,07,usb,yes,30,32 2006.182.08:15:31.34/va/05,07,usb,yes,31,33 2006.182.08:15:31.34/va/06,06,usb,yes,30,30 2006.182.08:15:31.34/va/07,06,usb,yes,31,30 2006.182.08:15:31.34/va/08,07,usb,yes,29,29 2006.182.08:15:31.57/valo/01,532.99,yes,locked 2006.182.08:15:31.57/valo/02,572.99,yes,locked 2006.182.08:15:31.57/valo/03,672.99,yes,locked 2006.182.08:15:31.57/valo/04,832.99,yes,locked 2006.182.08:15:31.57/valo/05,652.99,yes,locked 2006.182.08:15:31.57/valo/06,772.99,yes,locked 2006.182.08:15:31.57/valo/07,832.99,yes,locked 2006.182.08:15:31.57/valo/08,852.99,yes,locked 2006.182.08:15:32.66/vb/01,04,usb,yes,29,28 2006.182.08:15:32.66/vb/02,04,usb,yes,31,33 2006.182.08:15:32.66/vb/03,04,usb,yes,28,31 2006.182.08:15:32.66/vb/04,04,usb,yes,28,29 2006.182.08:15:32.66/vb/05,04,usb,yes,27,31 2006.182.08:15:32.66/vb/06,04,usb,yes,28,31 2006.182.08:15:32.66/vb/07,04,usb,yes,30,30 2006.182.08:15:32.66/vb/08,04,usb,yes,28,31 2006.182.08:15:32.90/vblo/01,632.99,yes,locked 2006.182.08:15:32.90/vblo/02,640.99,yes,locked 2006.182.08:15:32.90/vblo/03,656.99,yes,locked 2006.182.08:15:32.90/vblo/04,712.99,yes,locked 2006.182.08:15:32.90/vblo/05,744.99,yes,locked 2006.182.08:15:32.90/vblo/06,752.99,yes,locked 2006.182.08:15:32.90/vblo/07,734.99,yes,locked 2006.182.08:15:32.90/vblo/08,744.99,yes,locked 2006.182.08:15:33.05/vabw/8 2006.182.08:15:33.20/vbbw/8 2006.182.08:15:33.31/xfe/off,on,15.2 2006.182.08:15:33.69/ifatt/23,28,28,28 2006.182.08:15:34.07/fmout-gps/S +3.46E-07 2006.182.08:15:34.15:!2006.182.08:16:30 2006.182.08:16:30.00:data_valid=off 2006.182.08:16:30.00:postob 2006.182.08:16:30.14/cable/+6.4633E-03 2006.182.08:16:30.14/wx/27.80,1002.9,83 2006.182.08:16:31.08/fmout-gps/S +3.48E-07 2006.182.08:16:31.08:scan_name=182-0817,k06182,60 2006.182.08:16:31.09:source=1300+580,130252.47,574837.6,2000.0,cw 2006.182.08:16:31.14#flagr#flagr/antenna,new-source 2006.182.08:16:32.14:checkk5 2006.182.08:16:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:16:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:16:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:16:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:16:34.01/chk_obsdata//k5ts1/T1820815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:16:34.38/chk_obsdata//k5ts2/T1820815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:16:34.74/chk_obsdata//k5ts3/T1820815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:16:35.11/chk_obsdata//k5ts4/T1820815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:16:35.80/k5log//k5ts1_log_newline 2006.182.08:16:36.48/k5log//k5ts2_log_newline 2006.182.08:16:37.17/k5log//k5ts3_log_newline 2006.182.08:16:37.86/k5log//k5ts4_log_newline 2006.182.08:16:37.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:16:37.89:4f8m12a=2 2006.182.08:16:37.89$4f8m12a/echo=on 2006.182.08:16:37.89$4f8m12a/pcalon 2006.182.08:16:37.89$pcalon/"no phase cal control is implemented here 2006.182.08:16:37.89$4f8m12a/"tpicd=stop 2006.182.08:16:37.89$4f8m12a/vc4f8 2006.182.08:16:37.89$vc4f8/valo=1,532.99 2006.182.08:16:37.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.08:16:37.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.08:16:37.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:37.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:37.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:37.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:37.89#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:16:37.89#ibcon#first serial, iclass 19, count 0 2006.182.08:16:37.89#ibcon#enter sib2, iclass 19, count 0 2006.182.08:16:37.89#ibcon#flushed, iclass 19, count 0 2006.182.08:16:37.89#ibcon#about to write, iclass 19, count 0 2006.182.08:16:37.89#ibcon#wrote, iclass 19, count 0 2006.182.08:16:37.89#ibcon#about to read 3, iclass 19, count 0 2006.182.08:16:37.93#ibcon#read 3, iclass 19, count 0 2006.182.08:16:37.93#ibcon#about to read 4, iclass 19, count 0 2006.182.08:16:37.93#ibcon#read 4, iclass 19, count 0 2006.182.08:16:37.93#ibcon#about to read 5, iclass 19, count 0 2006.182.08:16:37.93#ibcon#read 5, iclass 19, count 0 2006.182.08:16:37.93#ibcon#about to read 6, iclass 19, count 0 2006.182.08:16:37.93#ibcon#read 6, iclass 19, count 0 2006.182.08:16:37.93#ibcon#end of sib2, iclass 19, count 0 2006.182.08:16:37.93#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:16:37.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:16:37.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:16:37.93#ibcon#*before write, iclass 19, count 0 2006.182.08:16:37.93#ibcon#enter sib2, iclass 19, count 0 2006.182.08:16:37.93#ibcon#flushed, iclass 19, count 0 2006.182.08:16:37.93#ibcon#about to write, iclass 19, count 0 2006.182.08:16:37.93#ibcon#wrote, iclass 19, count 0 2006.182.08:16:37.93#ibcon#about to read 3, iclass 19, count 0 2006.182.08:16:37.98#ibcon#read 3, iclass 19, count 0 2006.182.08:16:37.98#ibcon#about to read 4, iclass 19, count 0 2006.182.08:16:37.98#ibcon#read 4, iclass 19, count 0 2006.182.08:16:37.98#ibcon#about to read 5, iclass 19, count 0 2006.182.08:16:37.98#ibcon#read 5, iclass 19, count 0 2006.182.08:16:37.98#ibcon#about to read 6, iclass 19, count 0 2006.182.08:16:37.98#ibcon#read 6, iclass 19, count 0 2006.182.08:16:37.98#ibcon#end of sib2, iclass 19, count 0 2006.182.08:16:37.98#ibcon#*after write, iclass 19, count 0 2006.182.08:16:37.98#ibcon#*before return 0, iclass 19, count 0 2006.182.08:16:37.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:37.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:37.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:16:37.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:16:37.98$vc4f8/va=1,8 2006.182.08:16:37.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.08:16:37.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.08:16:37.98#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:37.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:37.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:37.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:37.98#ibcon#enter wrdev, iclass 21, count 2 2006.182.08:16:37.98#ibcon#first serial, iclass 21, count 2 2006.182.08:16:37.98#ibcon#enter sib2, iclass 21, count 2 2006.182.08:16:37.98#ibcon#flushed, iclass 21, count 2 2006.182.08:16:37.98#ibcon#about to write, iclass 21, count 2 2006.182.08:16:37.98#ibcon#wrote, iclass 21, count 2 2006.182.08:16:37.98#ibcon#about to read 3, iclass 21, count 2 2006.182.08:16:38.00#ibcon#read 3, iclass 21, count 2 2006.182.08:16:38.00#ibcon#about to read 4, iclass 21, count 2 2006.182.08:16:38.00#ibcon#read 4, iclass 21, count 2 2006.182.08:16:38.00#ibcon#about to read 5, iclass 21, count 2 2006.182.08:16:38.00#ibcon#read 5, iclass 21, count 2 2006.182.08:16:38.00#ibcon#about to read 6, iclass 21, count 2 2006.182.08:16:38.00#ibcon#read 6, iclass 21, count 2 2006.182.08:16:38.00#ibcon#end of sib2, iclass 21, count 2 2006.182.08:16:38.00#ibcon#*mode == 0, iclass 21, count 2 2006.182.08:16:38.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.08:16:38.00#ibcon#[25=AT01-08\r\n] 2006.182.08:16:38.00#ibcon#*before write, iclass 21, count 2 2006.182.08:16:38.00#ibcon#enter sib2, iclass 21, count 2 2006.182.08:16:38.00#ibcon#flushed, iclass 21, count 2 2006.182.08:16:38.00#ibcon#about to write, iclass 21, count 2 2006.182.08:16:38.00#ibcon#wrote, iclass 21, count 2 2006.182.08:16:38.00#ibcon#about to read 3, iclass 21, count 2 2006.182.08:16:38.03#ibcon#read 3, iclass 21, count 2 2006.182.08:16:38.03#ibcon#about to read 4, iclass 21, count 2 2006.182.08:16:38.03#ibcon#read 4, iclass 21, count 2 2006.182.08:16:38.03#ibcon#about to read 5, iclass 21, count 2 2006.182.08:16:38.03#ibcon#read 5, iclass 21, count 2 2006.182.08:16:38.03#ibcon#about to read 6, iclass 21, count 2 2006.182.08:16:38.03#ibcon#read 6, iclass 21, count 2 2006.182.08:16:38.03#ibcon#end of sib2, iclass 21, count 2 2006.182.08:16:38.03#ibcon#*after write, iclass 21, count 2 2006.182.08:16:38.03#ibcon#*before return 0, iclass 21, count 2 2006.182.08:16:38.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:38.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:38.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.08:16:38.03#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:38.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:38.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:38.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:38.15#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:16:38.15#ibcon#first serial, iclass 21, count 0 2006.182.08:16:38.15#ibcon#enter sib2, iclass 21, count 0 2006.182.08:16:38.15#ibcon#flushed, iclass 21, count 0 2006.182.08:16:38.15#ibcon#about to write, iclass 21, count 0 2006.182.08:16:38.15#ibcon#wrote, iclass 21, count 0 2006.182.08:16:38.15#ibcon#about to read 3, iclass 21, count 0 2006.182.08:16:38.17#ibcon#read 3, iclass 21, count 0 2006.182.08:16:38.17#ibcon#about to read 4, iclass 21, count 0 2006.182.08:16:38.17#ibcon#read 4, iclass 21, count 0 2006.182.08:16:38.17#ibcon#about to read 5, iclass 21, count 0 2006.182.08:16:38.17#ibcon#read 5, iclass 21, count 0 2006.182.08:16:38.17#ibcon#about to read 6, iclass 21, count 0 2006.182.08:16:38.17#ibcon#read 6, iclass 21, count 0 2006.182.08:16:38.17#ibcon#end of sib2, iclass 21, count 0 2006.182.08:16:38.17#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:16:38.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:16:38.17#ibcon#[25=USB\r\n] 2006.182.08:16:38.17#ibcon#*before write, iclass 21, count 0 2006.182.08:16:38.17#ibcon#enter sib2, iclass 21, count 0 2006.182.08:16:38.17#ibcon#flushed, iclass 21, count 0 2006.182.08:16:38.17#ibcon#about to write, iclass 21, count 0 2006.182.08:16:38.17#ibcon#wrote, iclass 21, count 0 2006.182.08:16:38.17#ibcon#about to read 3, iclass 21, count 0 2006.182.08:16:38.20#ibcon#read 3, iclass 21, count 0 2006.182.08:16:38.20#ibcon#about to read 4, iclass 21, count 0 2006.182.08:16:38.20#ibcon#read 4, iclass 21, count 0 2006.182.08:16:38.20#ibcon#about to read 5, iclass 21, count 0 2006.182.08:16:38.20#ibcon#read 5, iclass 21, count 0 2006.182.08:16:38.20#ibcon#about to read 6, iclass 21, count 0 2006.182.08:16:38.20#ibcon#read 6, iclass 21, count 0 2006.182.08:16:38.20#ibcon#end of sib2, iclass 21, count 0 2006.182.08:16:38.20#ibcon#*after write, iclass 21, count 0 2006.182.08:16:38.20#ibcon#*before return 0, iclass 21, count 0 2006.182.08:16:38.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:38.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:38.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:16:38.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:16:38.20$vc4f8/valo=2,572.99 2006.182.08:16:38.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.08:16:38.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.08:16:38.20#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:38.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:38.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:38.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:38.20#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:16:38.20#ibcon#first serial, iclass 23, count 0 2006.182.08:16:38.20#ibcon#enter sib2, iclass 23, count 0 2006.182.08:16:38.20#ibcon#flushed, iclass 23, count 0 2006.182.08:16:38.20#ibcon#about to write, iclass 23, count 0 2006.182.08:16:38.20#ibcon#wrote, iclass 23, count 0 2006.182.08:16:38.20#ibcon#about to read 3, iclass 23, count 0 2006.182.08:16:38.22#ibcon#read 3, iclass 23, count 0 2006.182.08:16:38.22#ibcon#about to read 4, iclass 23, count 0 2006.182.08:16:38.22#ibcon#read 4, iclass 23, count 0 2006.182.08:16:38.22#ibcon#about to read 5, iclass 23, count 0 2006.182.08:16:38.22#ibcon#read 5, iclass 23, count 0 2006.182.08:16:38.22#ibcon#about to read 6, iclass 23, count 0 2006.182.08:16:38.22#ibcon#read 6, iclass 23, count 0 2006.182.08:16:38.22#ibcon#end of sib2, iclass 23, count 0 2006.182.08:16:38.22#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:16:38.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:16:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:16:38.22#ibcon#*before write, iclass 23, count 0 2006.182.08:16:38.22#ibcon#enter sib2, iclass 23, count 0 2006.182.08:16:38.22#ibcon#flushed, iclass 23, count 0 2006.182.08:16:38.22#ibcon#about to write, iclass 23, count 0 2006.182.08:16:38.22#ibcon#wrote, iclass 23, count 0 2006.182.08:16:38.22#ibcon#about to read 3, iclass 23, count 0 2006.182.08:16:38.26#ibcon#read 3, iclass 23, count 0 2006.182.08:16:38.26#ibcon#about to read 4, iclass 23, count 0 2006.182.08:16:38.26#ibcon#read 4, iclass 23, count 0 2006.182.08:16:38.26#ibcon#about to read 5, iclass 23, count 0 2006.182.08:16:38.26#ibcon#read 5, iclass 23, count 0 2006.182.08:16:38.26#ibcon#about to read 6, iclass 23, count 0 2006.182.08:16:38.26#ibcon#read 6, iclass 23, count 0 2006.182.08:16:38.26#ibcon#end of sib2, iclass 23, count 0 2006.182.08:16:38.26#ibcon#*after write, iclass 23, count 0 2006.182.08:16:38.26#ibcon#*before return 0, iclass 23, count 0 2006.182.08:16:38.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:38.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:38.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:16:38.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:16:38.26$vc4f8/va=2,7 2006.182.08:16:38.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.08:16:38.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.08:16:38.26#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:38.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:38.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:38.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:38.33#ibcon#enter wrdev, iclass 25, count 2 2006.182.08:16:38.33#ibcon#first serial, iclass 25, count 2 2006.182.08:16:38.33#ibcon#enter sib2, iclass 25, count 2 2006.182.08:16:38.33#ibcon#flushed, iclass 25, count 2 2006.182.08:16:38.33#ibcon#about to write, iclass 25, count 2 2006.182.08:16:38.33#ibcon#wrote, iclass 25, count 2 2006.182.08:16:38.33#ibcon#about to read 3, iclass 25, count 2 2006.182.08:16:38.34#ibcon#read 3, iclass 25, count 2 2006.182.08:16:38.34#ibcon#about to read 4, iclass 25, count 2 2006.182.08:16:38.34#ibcon#read 4, iclass 25, count 2 2006.182.08:16:38.34#ibcon#about to read 5, iclass 25, count 2 2006.182.08:16:38.34#ibcon#read 5, iclass 25, count 2 2006.182.08:16:38.34#ibcon#about to read 6, iclass 25, count 2 2006.182.08:16:38.34#ibcon#read 6, iclass 25, count 2 2006.182.08:16:38.34#ibcon#end of sib2, iclass 25, count 2 2006.182.08:16:38.34#ibcon#*mode == 0, iclass 25, count 2 2006.182.08:16:38.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.08:16:38.34#ibcon#[25=AT02-07\r\n] 2006.182.08:16:38.34#ibcon#*before write, iclass 25, count 2 2006.182.08:16:38.34#ibcon#enter sib2, iclass 25, count 2 2006.182.08:16:38.34#ibcon#flushed, iclass 25, count 2 2006.182.08:16:38.34#ibcon#about to write, iclass 25, count 2 2006.182.08:16:38.34#ibcon#wrote, iclass 25, count 2 2006.182.08:16:38.34#ibcon#about to read 3, iclass 25, count 2 2006.182.08:16:38.37#ibcon#read 3, iclass 25, count 2 2006.182.08:16:38.37#ibcon#about to read 4, iclass 25, count 2 2006.182.08:16:38.37#ibcon#read 4, iclass 25, count 2 2006.182.08:16:38.37#ibcon#about to read 5, iclass 25, count 2 2006.182.08:16:38.37#ibcon#read 5, iclass 25, count 2 2006.182.08:16:38.37#ibcon#about to read 6, iclass 25, count 2 2006.182.08:16:38.37#ibcon#read 6, iclass 25, count 2 2006.182.08:16:38.37#ibcon#end of sib2, iclass 25, count 2 2006.182.08:16:38.37#ibcon#*after write, iclass 25, count 2 2006.182.08:16:38.37#ibcon#*before return 0, iclass 25, count 2 2006.182.08:16:38.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:38.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:38.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.08:16:38.37#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:38.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:38.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:38.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:38.49#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:16:38.49#ibcon#first serial, iclass 25, count 0 2006.182.08:16:38.49#ibcon#enter sib2, iclass 25, count 0 2006.182.08:16:38.49#ibcon#flushed, iclass 25, count 0 2006.182.08:16:38.49#ibcon#about to write, iclass 25, count 0 2006.182.08:16:38.49#ibcon#wrote, iclass 25, count 0 2006.182.08:16:38.49#ibcon#about to read 3, iclass 25, count 0 2006.182.08:16:38.51#ibcon#read 3, iclass 25, count 0 2006.182.08:16:38.51#ibcon#about to read 4, iclass 25, count 0 2006.182.08:16:38.51#ibcon#read 4, iclass 25, count 0 2006.182.08:16:38.51#ibcon#about to read 5, iclass 25, count 0 2006.182.08:16:38.51#ibcon#read 5, iclass 25, count 0 2006.182.08:16:38.51#ibcon#about to read 6, iclass 25, count 0 2006.182.08:16:38.51#ibcon#read 6, iclass 25, count 0 2006.182.08:16:38.51#ibcon#end of sib2, iclass 25, count 0 2006.182.08:16:38.51#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:16:38.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:16:38.51#ibcon#[25=USB\r\n] 2006.182.08:16:38.51#ibcon#*before write, iclass 25, count 0 2006.182.08:16:38.51#ibcon#enter sib2, iclass 25, count 0 2006.182.08:16:38.51#ibcon#flushed, iclass 25, count 0 2006.182.08:16:38.51#ibcon#about to write, iclass 25, count 0 2006.182.08:16:38.51#ibcon#wrote, iclass 25, count 0 2006.182.08:16:38.51#ibcon#about to read 3, iclass 25, count 0 2006.182.08:16:38.54#ibcon#read 3, iclass 25, count 0 2006.182.08:16:38.54#ibcon#about to read 4, iclass 25, count 0 2006.182.08:16:38.54#ibcon#read 4, iclass 25, count 0 2006.182.08:16:38.54#ibcon#about to read 5, iclass 25, count 0 2006.182.08:16:38.54#ibcon#read 5, iclass 25, count 0 2006.182.08:16:38.54#ibcon#about to read 6, iclass 25, count 0 2006.182.08:16:38.54#ibcon#read 6, iclass 25, count 0 2006.182.08:16:38.54#ibcon#end of sib2, iclass 25, count 0 2006.182.08:16:38.54#ibcon#*after write, iclass 25, count 0 2006.182.08:16:38.54#ibcon#*before return 0, iclass 25, count 0 2006.182.08:16:38.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:38.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:38.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:16:38.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:16:38.54$vc4f8/valo=3,672.99 2006.182.08:16:38.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.08:16:38.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.08:16:38.54#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:38.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:38.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:38.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:38.54#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:16:38.54#ibcon#first serial, iclass 27, count 0 2006.182.08:16:38.54#ibcon#enter sib2, iclass 27, count 0 2006.182.08:16:38.54#ibcon#flushed, iclass 27, count 0 2006.182.08:16:38.54#ibcon#about to write, iclass 27, count 0 2006.182.08:16:38.54#ibcon#wrote, iclass 27, count 0 2006.182.08:16:38.54#ibcon#about to read 3, iclass 27, count 0 2006.182.08:16:38.56#ibcon#read 3, iclass 27, count 0 2006.182.08:16:38.56#ibcon#about to read 4, iclass 27, count 0 2006.182.08:16:38.56#ibcon#read 4, iclass 27, count 0 2006.182.08:16:38.56#ibcon#about to read 5, iclass 27, count 0 2006.182.08:16:38.56#ibcon#read 5, iclass 27, count 0 2006.182.08:16:38.56#ibcon#about to read 6, iclass 27, count 0 2006.182.08:16:38.56#ibcon#read 6, iclass 27, count 0 2006.182.08:16:38.56#ibcon#end of sib2, iclass 27, count 0 2006.182.08:16:38.56#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:16:38.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:16:38.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:16:38.56#ibcon#*before write, iclass 27, count 0 2006.182.08:16:38.56#ibcon#enter sib2, iclass 27, count 0 2006.182.08:16:38.56#ibcon#flushed, iclass 27, count 0 2006.182.08:16:38.56#ibcon#about to write, iclass 27, count 0 2006.182.08:16:38.56#ibcon#wrote, iclass 27, count 0 2006.182.08:16:38.56#ibcon#about to read 3, iclass 27, count 0 2006.182.08:16:38.60#ibcon#read 3, iclass 27, count 0 2006.182.08:16:38.60#ibcon#about to read 4, iclass 27, count 0 2006.182.08:16:38.60#ibcon#read 4, iclass 27, count 0 2006.182.08:16:38.60#ibcon#about to read 5, iclass 27, count 0 2006.182.08:16:38.60#ibcon#read 5, iclass 27, count 0 2006.182.08:16:38.60#ibcon#about to read 6, iclass 27, count 0 2006.182.08:16:38.60#ibcon#read 6, iclass 27, count 0 2006.182.08:16:38.60#ibcon#end of sib2, iclass 27, count 0 2006.182.08:16:38.60#ibcon#*after write, iclass 27, count 0 2006.182.08:16:38.60#ibcon#*before return 0, iclass 27, count 0 2006.182.08:16:38.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:38.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:38.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:16:38.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:16:38.60$vc4f8/va=3,6 2006.182.08:16:38.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.08:16:38.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.08:16:38.60#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:38.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:38.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:38.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:38.67#ibcon#enter wrdev, iclass 29, count 2 2006.182.08:16:38.67#ibcon#first serial, iclass 29, count 2 2006.182.08:16:38.67#ibcon#enter sib2, iclass 29, count 2 2006.182.08:16:38.67#ibcon#flushed, iclass 29, count 2 2006.182.08:16:38.67#ibcon#about to write, iclass 29, count 2 2006.182.08:16:38.67#ibcon#wrote, iclass 29, count 2 2006.182.08:16:38.67#ibcon#about to read 3, iclass 29, count 2 2006.182.08:16:38.68#ibcon#read 3, iclass 29, count 2 2006.182.08:16:38.68#ibcon#about to read 4, iclass 29, count 2 2006.182.08:16:38.68#ibcon#read 4, iclass 29, count 2 2006.182.08:16:38.68#ibcon#about to read 5, iclass 29, count 2 2006.182.08:16:38.68#ibcon#read 5, iclass 29, count 2 2006.182.08:16:38.68#ibcon#about to read 6, iclass 29, count 2 2006.182.08:16:38.68#ibcon#read 6, iclass 29, count 2 2006.182.08:16:38.68#ibcon#end of sib2, iclass 29, count 2 2006.182.08:16:38.68#ibcon#*mode == 0, iclass 29, count 2 2006.182.08:16:38.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.08:16:38.68#ibcon#[25=AT03-06\r\n] 2006.182.08:16:38.68#ibcon#*before write, iclass 29, count 2 2006.182.08:16:38.68#ibcon#enter sib2, iclass 29, count 2 2006.182.08:16:38.68#ibcon#flushed, iclass 29, count 2 2006.182.08:16:38.68#ibcon#about to write, iclass 29, count 2 2006.182.08:16:38.68#ibcon#wrote, iclass 29, count 2 2006.182.08:16:38.68#ibcon#about to read 3, iclass 29, count 2 2006.182.08:16:38.71#ibcon#read 3, iclass 29, count 2 2006.182.08:16:38.71#ibcon#about to read 4, iclass 29, count 2 2006.182.08:16:38.71#ibcon#read 4, iclass 29, count 2 2006.182.08:16:38.71#ibcon#about to read 5, iclass 29, count 2 2006.182.08:16:38.71#ibcon#read 5, iclass 29, count 2 2006.182.08:16:38.71#ibcon#about to read 6, iclass 29, count 2 2006.182.08:16:38.71#ibcon#read 6, iclass 29, count 2 2006.182.08:16:38.71#ibcon#end of sib2, iclass 29, count 2 2006.182.08:16:38.71#ibcon#*after write, iclass 29, count 2 2006.182.08:16:38.71#ibcon#*before return 0, iclass 29, count 2 2006.182.08:16:38.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:38.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:38.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.08:16:38.71#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:38.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:38.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:38.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:38.83#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:16:38.83#ibcon#first serial, iclass 29, count 0 2006.182.08:16:38.83#ibcon#enter sib2, iclass 29, count 0 2006.182.08:16:38.83#ibcon#flushed, iclass 29, count 0 2006.182.08:16:38.83#ibcon#about to write, iclass 29, count 0 2006.182.08:16:38.83#ibcon#wrote, iclass 29, count 0 2006.182.08:16:38.83#ibcon#about to read 3, iclass 29, count 0 2006.182.08:16:38.85#ibcon#read 3, iclass 29, count 0 2006.182.08:16:38.85#ibcon#about to read 4, iclass 29, count 0 2006.182.08:16:38.85#ibcon#read 4, iclass 29, count 0 2006.182.08:16:38.85#ibcon#about to read 5, iclass 29, count 0 2006.182.08:16:38.85#ibcon#read 5, iclass 29, count 0 2006.182.08:16:38.85#ibcon#about to read 6, iclass 29, count 0 2006.182.08:16:38.85#ibcon#read 6, iclass 29, count 0 2006.182.08:16:38.85#ibcon#end of sib2, iclass 29, count 0 2006.182.08:16:38.85#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:16:38.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:16:38.85#ibcon#[25=USB\r\n] 2006.182.08:16:38.85#ibcon#*before write, iclass 29, count 0 2006.182.08:16:38.85#ibcon#enter sib2, iclass 29, count 0 2006.182.08:16:38.85#ibcon#flushed, iclass 29, count 0 2006.182.08:16:38.85#ibcon#about to write, iclass 29, count 0 2006.182.08:16:38.85#ibcon#wrote, iclass 29, count 0 2006.182.08:16:38.85#ibcon#about to read 3, iclass 29, count 0 2006.182.08:16:38.88#ibcon#read 3, iclass 29, count 0 2006.182.08:16:38.88#ibcon#about to read 4, iclass 29, count 0 2006.182.08:16:38.88#ibcon#read 4, iclass 29, count 0 2006.182.08:16:38.88#ibcon#about to read 5, iclass 29, count 0 2006.182.08:16:38.88#ibcon#read 5, iclass 29, count 0 2006.182.08:16:38.88#ibcon#about to read 6, iclass 29, count 0 2006.182.08:16:38.88#ibcon#read 6, iclass 29, count 0 2006.182.08:16:38.88#ibcon#end of sib2, iclass 29, count 0 2006.182.08:16:38.88#ibcon#*after write, iclass 29, count 0 2006.182.08:16:38.88#ibcon#*before return 0, iclass 29, count 0 2006.182.08:16:38.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:38.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:38.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:16:38.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:16:38.88$vc4f8/valo=4,832.99 2006.182.08:16:38.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.08:16:38.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.08:16:38.88#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:38.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:38.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:38.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:38.88#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:16:38.88#ibcon#first serial, iclass 31, count 0 2006.182.08:16:38.88#ibcon#enter sib2, iclass 31, count 0 2006.182.08:16:38.88#ibcon#flushed, iclass 31, count 0 2006.182.08:16:38.88#ibcon#about to write, iclass 31, count 0 2006.182.08:16:38.88#ibcon#wrote, iclass 31, count 0 2006.182.08:16:38.88#ibcon#about to read 3, iclass 31, count 0 2006.182.08:16:38.90#ibcon#read 3, iclass 31, count 0 2006.182.08:16:38.90#ibcon#about to read 4, iclass 31, count 0 2006.182.08:16:38.90#ibcon#read 4, iclass 31, count 0 2006.182.08:16:38.90#ibcon#about to read 5, iclass 31, count 0 2006.182.08:16:38.90#ibcon#read 5, iclass 31, count 0 2006.182.08:16:38.90#ibcon#about to read 6, iclass 31, count 0 2006.182.08:16:38.90#ibcon#read 6, iclass 31, count 0 2006.182.08:16:38.90#ibcon#end of sib2, iclass 31, count 0 2006.182.08:16:38.90#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:16:38.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:16:38.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:16:38.90#ibcon#*before write, iclass 31, count 0 2006.182.08:16:38.90#ibcon#enter sib2, iclass 31, count 0 2006.182.08:16:38.90#ibcon#flushed, iclass 31, count 0 2006.182.08:16:38.90#ibcon#about to write, iclass 31, count 0 2006.182.08:16:38.90#ibcon#wrote, iclass 31, count 0 2006.182.08:16:38.90#ibcon#about to read 3, iclass 31, count 0 2006.182.08:16:38.94#ibcon#read 3, iclass 31, count 0 2006.182.08:16:38.94#ibcon#about to read 4, iclass 31, count 0 2006.182.08:16:38.94#ibcon#read 4, iclass 31, count 0 2006.182.08:16:38.94#ibcon#about to read 5, iclass 31, count 0 2006.182.08:16:38.94#ibcon#read 5, iclass 31, count 0 2006.182.08:16:38.94#ibcon#about to read 6, iclass 31, count 0 2006.182.08:16:38.94#ibcon#read 6, iclass 31, count 0 2006.182.08:16:38.94#ibcon#end of sib2, iclass 31, count 0 2006.182.08:16:38.94#ibcon#*after write, iclass 31, count 0 2006.182.08:16:38.94#ibcon#*before return 0, iclass 31, count 0 2006.182.08:16:38.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:38.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:38.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:16:38.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:16:38.94$vc4f8/va=4,7 2006.182.08:16:38.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.08:16:38.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.08:16:38.94#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:38.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:39.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:39.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:39.00#ibcon#enter wrdev, iclass 33, count 2 2006.182.08:16:39.00#ibcon#first serial, iclass 33, count 2 2006.182.08:16:39.00#ibcon#enter sib2, iclass 33, count 2 2006.182.08:16:39.00#ibcon#flushed, iclass 33, count 2 2006.182.08:16:39.00#ibcon#about to write, iclass 33, count 2 2006.182.08:16:39.00#ibcon#wrote, iclass 33, count 2 2006.182.08:16:39.00#ibcon#about to read 3, iclass 33, count 2 2006.182.08:16:39.02#ibcon#read 3, iclass 33, count 2 2006.182.08:16:39.02#ibcon#about to read 4, iclass 33, count 2 2006.182.08:16:39.02#ibcon#read 4, iclass 33, count 2 2006.182.08:16:39.02#ibcon#about to read 5, iclass 33, count 2 2006.182.08:16:39.02#ibcon#read 5, iclass 33, count 2 2006.182.08:16:39.02#ibcon#about to read 6, iclass 33, count 2 2006.182.08:16:39.02#ibcon#read 6, iclass 33, count 2 2006.182.08:16:39.02#ibcon#end of sib2, iclass 33, count 2 2006.182.08:16:39.02#ibcon#*mode == 0, iclass 33, count 2 2006.182.08:16:39.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.08:16:39.02#ibcon#[25=AT04-07\r\n] 2006.182.08:16:39.02#ibcon#*before write, iclass 33, count 2 2006.182.08:16:39.02#ibcon#enter sib2, iclass 33, count 2 2006.182.08:16:39.02#ibcon#flushed, iclass 33, count 2 2006.182.08:16:39.02#ibcon#about to write, iclass 33, count 2 2006.182.08:16:39.02#ibcon#wrote, iclass 33, count 2 2006.182.08:16:39.02#ibcon#about to read 3, iclass 33, count 2 2006.182.08:16:39.05#ibcon#read 3, iclass 33, count 2 2006.182.08:16:39.05#ibcon#about to read 4, iclass 33, count 2 2006.182.08:16:39.05#ibcon#read 4, iclass 33, count 2 2006.182.08:16:39.05#ibcon#about to read 5, iclass 33, count 2 2006.182.08:16:39.05#ibcon#read 5, iclass 33, count 2 2006.182.08:16:39.05#ibcon#about to read 6, iclass 33, count 2 2006.182.08:16:39.05#ibcon#read 6, iclass 33, count 2 2006.182.08:16:39.05#ibcon#end of sib2, iclass 33, count 2 2006.182.08:16:39.05#ibcon#*after write, iclass 33, count 2 2006.182.08:16:39.05#ibcon#*before return 0, iclass 33, count 2 2006.182.08:16:39.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:39.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:39.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.08:16:39.05#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:39.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:39.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:39.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:39.17#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:16:39.17#ibcon#first serial, iclass 33, count 0 2006.182.08:16:39.17#ibcon#enter sib2, iclass 33, count 0 2006.182.08:16:39.17#ibcon#flushed, iclass 33, count 0 2006.182.08:16:39.17#ibcon#about to write, iclass 33, count 0 2006.182.08:16:39.17#ibcon#wrote, iclass 33, count 0 2006.182.08:16:39.17#ibcon#about to read 3, iclass 33, count 0 2006.182.08:16:39.19#ibcon#read 3, iclass 33, count 0 2006.182.08:16:39.19#ibcon#about to read 4, iclass 33, count 0 2006.182.08:16:39.19#ibcon#read 4, iclass 33, count 0 2006.182.08:16:39.19#ibcon#about to read 5, iclass 33, count 0 2006.182.08:16:39.19#ibcon#read 5, iclass 33, count 0 2006.182.08:16:39.19#ibcon#about to read 6, iclass 33, count 0 2006.182.08:16:39.19#ibcon#read 6, iclass 33, count 0 2006.182.08:16:39.19#ibcon#end of sib2, iclass 33, count 0 2006.182.08:16:39.19#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:16:39.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:16:39.19#ibcon#[25=USB\r\n] 2006.182.08:16:39.19#ibcon#*before write, iclass 33, count 0 2006.182.08:16:39.19#ibcon#enter sib2, iclass 33, count 0 2006.182.08:16:39.19#ibcon#flushed, iclass 33, count 0 2006.182.08:16:39.19#ibcon#about to write, iclass 33, count 0 2006.182.08:16:39.19#ibcon#wrote, iclass 33, count 0 2006.182.08:16:39.19#ibcon#about to read 3, iclass 33, count 0 2006.182.08:16:39.22#ibcon#read 3, iclass 33, count 0 2006.182.08:16:39.22#ibcon#about to read 4, iclass 33, count 0 2006.182.08:16:39.22#ibcon#read 4, iclass 33, count 0 2006.182.08:16:39.22#ibcon#about to read 5, iclass 33, count 0 2006.182.08:16:39.22#ibcon#read 5, iclass 33, count 0 2006.182.08:16:39.22#ibcon#about to read 6, iclass 33, count 0 2006.182.08:16:39.22#ibcon#read 6, iclass 33, count 0 2006.182.08:16:39.22#ibcon#end of sib2, iclass 33, count 0 2006.182.08:16:39.22#ibcon#*after write, iclass 33, count 0 2006.182.08:16:39.22#ibcon#*before return 0, iclass 33, count 0 2006.182.08:16:39.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:39.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:39.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:16:39.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:16:39.22$vc4f8/valo=5,652.99 2006.182.08:16:39.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.08:16:39.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.08:16:39.22#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:39.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:39.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:39.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:39.22#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:16:39.22#ibcon#first serial, iclass 35, count 0 2006.182.08:16:39.22#ibcon#enter sib2, iclass 35, count 0 2006.182.08:16:39.22#ibcon#flushed, iclass 35, count 0 2006.182.08:16:39.22#ibcon#about to write, iclass 35, count 0 2006.182.08:16:39.22#ibcon#wrote, iclass 35, count 0 2006.182.08:16:39.22#ibcon#about to read 3, iclass 35, count 0 2006.182.08:16:39.24#ibcon#read 3, iclass 35, count 0 2006.182.08:16:39.24#ibcon#about to read 4, iclass 35, count 0 2006.182.08:16:39.24#ibcon#read 4, iclass 35, count 0 2006.182.08:16:39.24#ibcon#about to read 5, iclass 35, count 0 2006.182.08:16:39.24#ibcon#read 5, iclass 35, count 0 2006.182.08:16:39.24#ibcon#about to read 6, iclass 35, count 0 2006.182.08:16:39.24#ibcon#read 6, iclass 35, count 0 2006.182.08:16:39.24#ibcon#end of sib2, iclass 35, count 0 2006.182.08:16:39.24#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:16:39.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:16:39.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:16:39.24#ibcon#*before write, iclass 35, count 0 2006.182.08:16:39.24#ibcon#enter sib2, iclass 35, count 0 2006.182.08:16:39.24#ibcon#flushed, iclass 35, count 0 2006.182.08:16:39.24#ibcon#about to write, iclass 35, count 0 2006.182.08:16:39.24#ibcon#wrote, iclass 35, count 0 2006.182.08:16:39.24#ibcon#about to read 3, iclass 35, count 0 2006.182.08:16:39.28#ibcon#read 3, iclass 35, count 0 2006.182.08:16:39.28#ibcon#about to read 4, iclass 35, count 0 2006.182.08:16:39.28#ibcon#read 4, iclass 35, count 0 2006.182.08:16:39.28#ibcon#about to read 5, iclass 35, count 0 2006.182.08:16:39.28#ibcon#read 5, iclass 35, count 0 2006.182.08:16:39.28#ibcon#about to read 6, iclass 35, count 0 2006.182.08:16:39.28#ibcon#read 6, iclass 35, count 0 2006.182.08:16:39.28#ibcon#end of sib2, iclass 35, count 0 2006.182.08:16:39.28#ibcon#*after write, iclass 35, count 0 2006.182.08:16:39.28#ibcon#*before return 0, iclass 35, count 0 2006.182.08:16:39.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:39.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:39.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:16:39.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:16:39.28$vc4f8/va=5,7 2006.182.08:16:39.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.08:16:39.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.08:16:39.28#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:39.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:39.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:39.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:39.34#ibcon#enter wrdev, iclass 37, count 2 2006.182.08:16:39.34#ibcon#first serial, iclass 37, count 2 2006.182.08:16:39.34#ibcon#enter sib2, iclass 37, count 2 2006.182.08:16:39.34#ibcon#flushed, iclass 37, count 2 2006.182.08:16:39.34#ibcon#about to write, iclass 37, count 2 2006.182.08:16:39.34#ibcon#wrote, iclass 37, count 2 2006.182.08:16:39.34#ibcon#about to read 3, iclass 37, count 2 2006.182.08:16:39.36#ibcon#read 3, iclass 37, count 2 2006.182.08:16:39.36#ibcon#about to read 4, iclass 37, count 2 2006.182.08:16:39.36#ibcon#read 4, iclass 37, count 2 2006.182.08:16:39.36#ibcon#about to read 5, iclass 37, count 2 2006.182.08:16:39.36#ibcon#read 5, iclass 37, count 2 2006.182.08:16:39.36#ibcon#about to read 6, iclass 37, count 2 2006.182.08:16:39.36#ibcon#read 6, iclass 37, count 2 2006.182.08:16:39.36#ibcon#end of sib2, iclass 37, count 2 2006.182.08:16:39.36#ibcon#*mode == 0, iclass 37, count 2 2006.182.08:16:39.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.08:16:39.36#ibcon#[25=AT05-07\r\n] 2006.182.08:16:39.36#ibcon#*before write, iclass 37, count 2 2006.182.08:16:39.36#ibcon#enter sib2, iclass 37, count 2 2006.182.08:16:39.36#ibcon#flushed, iclass 37, count 2 2006.182.08:16:39.36#ibcon#about to write, iclass 37, count 2 2006.182.08:16:39.36#ibcon#wrote, iclass 37, count 2 2006.182.08:16:39.36#ibcon#about to read 3, iclass 37, count 2 2006.182.08:16:39.39#ibcon#read 3, iclass 37, count 2 2006.182.08:16:39.39#ibcon#about to read 4, iclass 37, count 2 2006.182.08:16:39.39#ibcon#read 4, iclass 37, count 2 2006.182.08:16:39.39#ibcon#about to read 5, iclass 37, count 2 2006.182.08:16:39.39#ibcon#read 5, iclass 37, count 2 2006.182.08:16:39.39#ibcon#about to read 6, iclass 37, count 2 2006.182.08:16:39.39#ibcon#read 6, iclass 37, count 2 2006.182.08:16:39.39#ibcon#end of sib2, iclass 37, count 2 2006.182.08:16:39.39#ibcon#*after write, iclass 37, count 2 2006.182.08:16:39.39#ibcon#*before return 0, iclass 37, count 2 2006.182.08:16:39.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:39.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:39.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.08:16:39.39#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:39.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:39.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:39.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:39.51#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:16:39.51#ibcon#first serial, iclass 37, count 0 2006.182.08:16:39.51#ibcon#enter sib2, iclass 37, count 0 2006.182.08:16:39.51#ibcon#flushed, iclass 37, count 0 2006.182.08:16:39.51#ibcon#about to write, iclass 37, count 0 2006.182.08:16:39.51#ibcon#wrote, iclass 37, count 0 2006.182.08:16:39.51#ibcon#about to read 3, iclass 37, count 0 2006.182.08:16:39.53#ibcon#read 3, iclass 37, count 0 2006.182.08:16:39.53#ibcon#about to read 4, iclass 37, count 0 2006.182.08:16:39.53#ibcon#read 4, iclass 37, count 0 2006.182.08:16:39.53#ibcon#about to read 5, iclass 37, count 0 2006.182.08:16:39.53#ibcon#read 5, iclass 37, count 0 2006.182.08:16:39.53#ibcon#about to read 6, iclass 37, count 0 2006.182.08:16:39.53#ibcon#read 6, iclass 37, count 0 2006.182.08:16:39.53#ibcon#end of sib2, iclass 37, count 0 2006.182.08:16:39.53#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:16:39.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:16:39.53#ibcon#[25=USB\r\n] 2006.182.08:16:39.53#ibcon#*before write, iclass 37, count 0 2006.182.08:16:39.53#ibcon#enter sib2, iclass 37, count 0 2006.182.08:16:39.53#ibcon#flushed, iclass 37, count 0 2006.182.08:16:39.53#ibcon#about to write, iclass 37, count 0 2006.182.08:16:39.53#ibcon#wrote, iclass 37, count 0 2006.182.08:16:39.53#ibcon#about to read 3, iclass 37, count 0 2006.182.08:16:39.56#ibcon#read 3, iclass 37, count 0 2006.182.08:16:39.56#ibcon#about to read 4, iclass 37, count 0 2006.182.08:16:39.56#ibcon#read 4, iclass 37, count 0 2006.182.08:16:39.56#ibcon#about to read 5, iclass 37, count 0 2006.182.08:16:39.56#ibcon#read 5, iclass 37, count 0 2006.182.08:16:39.56#ibcon#about to read 6, iclass 37, count 0 2006.182.08:16:39.56#ibcon#read 6, iclass 37, count 0 2006.182.08:16:39.56#ibcon#end of sib2, iclass 37, count 0 2006.182.08:16:39.56#ibcon#*after write, iclass 37, count 0 2006.182.08:16:39.56#ibcon#*before return 0, iclass 37, count 0 2006.182.08:16:39.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:39.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:39.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:16:39.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:16:39.56$vc4f8/valo=6,772.99 2006.182.08:16:39.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.08:16:39.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.08:16:39.56#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:39.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:39.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:39.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:39.56#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:16:39.56#ibcon#first serial, iclass 39, count 0 2006.182.08:16:39.56#ibcon#enter sib2, iclass 39, count 0 2006.182.08:16:39.56#ibcon#flushed, iclass 39, count 0 2006.182.08:16:39.56#ibcon#about to write, iclass 39, count 0 2006.182.08:16:39.56#ibcon#wrote, iclass 39, count 0 2006.182.08:16:39.56#ibcon#about to read 3, iclass 39, count 0 2006.182.08:16:39.58#ibcon#read 3, iclass 39, count 0 2006.182.08:16:39.58#ibcon#about to read 4, iclass 39, count 0 2006.182.08:16:39.58#ibcon#read 4, iclass 39, count 0 2006.182.08:16:39.58#ibcon#about to read 5, iclass 39, count 0 2006.182.08:16:39.58#ibcon#read 5, iclass 39, count 0 2006.182.08:16:39.58#ibcon#about to read 6, iclass 39, count 0 2006.182.08:16:39.58#ibcon#read 6, iclass 39, count 0 2006.182.08:16:39.58#ibcon#end of sib2, iclass 39, count 0 2006.182.08:16:39.58#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:16:39.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:16:39.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:16:39.58#ibcon#*before write, iclass 39, count 0 2006.182.08:16:39.58#ibcon#enter sib2, iclass 39, count 0 2006.182.08:16:39.58#ibcon#flushed, iclass 39, count 0 2006.182.08:16:39.58#ibcon#about to write, iclass 39, count 0 2006.182.08:16:39.58#ibcon#wrote, iclass 39, count 0 2006.182.08:16:39.58#ibcon#about to read 3, iclass 39, count 0 2006.182.08:16:39.62#ibcon#read 3, iclass 39, count 0 2006.182.08:16:39.62#ibcon#about to read 4, iclass 39, count 0 2006.182.08:16:39.62#ibcon#read 4, iclass 39, count 0 2006.182.08:16:39.62#ibcon#about to read 5, iclass 39, count 0 2006.182.08:16:39.62#ibcon#read 5, iclass 39, count 0 2006.182.08:16:39.62#ibcon#about to read 6, iclass 39, count 0 2006.182.08:16:39.62#ibcon#read 6, iclass 39, count 0 2006.182.08:16:39.62#ibcon#end of sib2, iclass 39, count 0 2006.182.08:16:39.62#ibcon#*after write, iclass 39, count 0 2006.182.08:16:39.62#ibcon#*before return 0, iclass 39, count 0 2006.182.08:16:39.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:39.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:39.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:16:39.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:16:39.62$vc4f8/va=6,6 2006.182.08:16:39.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.08:16:39.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.08:16:39.62#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:39.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:39.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:39.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:39.68#ibcon#enter wrdev, iclass 3, count 2 2006.182.08:16:39.68#ibcon#first serial, iclass 3, count 2 2006.182.08:16:39.68#ibcon#enter sib2, iclass 3, count 2 2006.182.08:16:39.68#ibcon#flushed, iclass 3, count 2 2006.182.08:16:39.68#ibcon#about to write, iclass 3, count 2 2006.182.08:16:39.68#ibcon#wrote, iclass 3, count 2 2006.182.08:16:39.68#ibcon#about to read 3, iclass 3, count 2 2006.182.08:16:39.70#ibcon#read 3, iclass 3, count 2 2006.182.08:16:39.70#ibcon#about to read 4, iclass 3, count 2 2006.182.08:16:39.70#ibcon#read 4, iclass 3, count 2 2006.182.08:16:39.70#ibcon#about to read 5, iclass 3, count 2 2006.182.08:16:39.70#ibcon#read 5, iclass 3, count 2 2006.182.08:16:39.70#ibcon#about to read 6, iclass 3, count 2 2006.182.08:16:39.70#ibcon#read 6, iclass 3, count 2 2006.182.08:16:39.70#ibcon#end of sib2, iclass 3, count 2 2006.182.08:16:39.70#ibcon#*mode == 0, iclass 3, count 2 2006.182.08:16:39.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.08:16:39.70#ibcon#[25=AT06-06\r\n] 2006.182.08:16:39.70#ibcon#*before write, iclass 3, count 2 2006.182.08:16:39.70#ibcon#enter sib2, iclass 3, count 2 2006.182.08:16:39.70#ibcon#flushed, iclass 3, count 2 2006.182.08:16:39.70#ibcon#about to write, iclass 3, count 2 2006.182.08:16:39.70#ibcon#wrote, iclass 3, count 2 2006.182.08:16:39.70#ibcon#about to read 3, iclass 3, count 2 2006.182.08:16:39.73#ibcon#read 3, iclass 3, count 2 2006.182.08:16:39.73#ibcon#about to read 4, iclass 3, count 2 2006.182.08:16:39.73#ibcon#read 4, iclass 3, count 2 2006.182.08:16:39.73#ibcon#about to read 5, iclass 3, count 2 2006.182.08:16:39.73#ibcon#read 5, iclass 3, count 2 2006.182.08:16:39.73#ibcon#about to read 6, iclass 3, count 2 2006.182.08:16:39.73#ibcon#read 6, iclass 3, count 2 2006.182.08:16:39.73#ibcon#end of sib2, iclass 3, count 2 2006.182.08:16:39.73#ibcon#*after write, iclass 3, count 2 2006.182.08:16:39.73#ibcon#*before return 0, iclass 3, count 2 2006.182.08:16:39.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:39.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:39.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.08:16:39.73#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:39.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:39.75#abcon#<5=/07 1.0 2.4 27.80 831002.9\r\n> 2006.182.08:16:39.77#abcon#{5=INTERFACE CLEAR} 2006.182.08:16:39.83#abcon#[5=S1D000X0/0*\r\n] 2006.182.08:16:39.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:39.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:39.85#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:16:39.85#ibcon#first serial, iclass 3, count 0 2006.182.08:16:39.85#ibcon#enter sib2, iclass 3, count 0 2006.182.08:16:39.85#ibcon#flushed, iclass 3, count 0 2006.182.08:16:39.85#ibcon#about to write, iclass 3, count 0 2006.182.08:16:39.85#ibcon#wrote, iclass 3, count 0 2006.182.08:16:39.85#ibcon#about to read 3, iclass 3, count 0 2006.182.08:16:39.87#ibcon#read 3, iclass 3, count 0 2006.182.08:16:39.87#ibcon#about to read 4, iclass 3, count 0 2006.182.08:16:39.87#ibcon#read 4, iclass 3, count 0 2006.182.08:16:39.87#ibcon#about to read 5, iclass 3, count 0 2006.182.08:16:39.87#ibcon#read 5, iclass 3, count 0 2006.182.08:16:39.87#ibcon#about to read 6, iclass 3, count 0 2006.182.08:16:39.87#ibcon#read 6, iclass 3, count 0 2006.182.08:16:39.87#ibcon#end of sib2, iclass 3, count 0 2006.182.08:16:39.87#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:16:39.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:16:39.87#ibcon#[25=USB\r\n] 2006.182.08:16:39.87#ibcon#*before write, iclass 3, count 0 2006.182.08:16:39.87#ibcon#enter sib2, iclass 3, count 0 2006.182.08:16:39.87#ibcon#flushed, iclass 3, count 0 2006.182.08:16:39.87#ibcon#about to write, iclass 3, count 0 2006.182.08:16:39.87#ibcon#wrote, iclass 3, count 0 2006.182.08:16:39.87#ibcon#about to read 3, iclass 3, count 0 2006.182.08:16:39.90#ibcon#read 3, iclass 3, count 0 2006.182.08:16:39.90#ibcon#about to read 4, iclass 3, count 0 2006.182.08:16:39.90#ibcon#read 4, iclass 3, count 0 2006.182.08:16:39.90#ibcon#about to read 5, iclass 3, count 0 2006.182.08:16:39.90#ibcon#read 5, iclass 3, count 0 2006.182.08:16:39.90#ibcon#about to read 6, iclass 3, count 0 2006.182.08:16:39.90#ibcon#read 6, iclass 3, count 0 2006.182.08:16:39.90#ibcon#end of sib2, iclass 3, count 0 2006.182.08:16:39.90#ibcon#*after write, iclass 3, count 0 2006.182.08:16:39.90#ibcon#*before return 0, iclass 3, count 0 2006.182.08:16:39.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:39.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:39.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:16:39.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:16:39.90$vc4f8/valo=7,832.99 2006.182.08:16:39.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.08:16:39.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.08:16:39.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:39.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:16:39.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:16:39.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:16:39.90#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:16:39.90#ibcon#first serial, iclass 11, count 0 2006.182.08:16:39.90#ibcon#enter sib2, iclass 11, count 0 2006.182.08:16:39.90#ibcon#flushed, iclass 11, count 0 2006.182.08:16:39.90#ibcon#about to write, iclass 11, count 0 2006.182.08:16:39.90#ibcon#wrote, iclass 11, count 0 2006.182.08:16:39.90#ibcon#about to read 3, iclass 11, count 0 2006.182.08:16:39.92#ibcon#read 3, iclass 11, count 0 2006.182.08:16:39.92#ibcon#about to read 4, iclass 11, count 0 2006.182.08:16:39.92#ibcon#read 4, iclass 11, count 0 2006.182.08:16:39.92#ibcon#about to read 5, iclass 11, count 0 2006.182.08:16:39.92#ibcon#read 5, iclass 11, count 0 2006.182.08:16:39.92#ibcon#about to read 6, iclass 11, count 0 2006.182.08:16:39.92#ibcon#read 6, iclass 11, count 0 2006.182.08:16:39.92#ibcon#end of sib2, iclass 11, count 0 2006.182.08:16:39.92#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:16:39.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:16:39.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:16:39.92#ibcon#*before write, iclass 11, count 0 2006.182.08:16:39.92#ibcon#enter sib2, iclass 11, count 0 2006.182.08:16:39.92#ibcon#flushed, iclass 11, count 0 2006.182.08:16:39.92#ibcon#about to write, iclass 11, count 0 2006.182.08:16:39.92#ibcon#wrote, iclass 11, count 0 2006.182.08:16:39.92#ibcon#about to read 3, iclass 11, count 0 2006.182.08:16:39.96#ibcon#read 3, iclass 11, count 0 2006.182.08:16:39.96#ibcon#about to read 4, iclass 11, count 0 2006.182.08:16:39.96#ibcon#read 4, iclass 11, count 0 2006.182.08:16:39.96#ibcon#about to read 5, iclass 11, count 0 2006.182.08:16:39.96#ibcon#read 5, iclass 11, count 0 2006.182.08:16:39.96#ibcon#about to read 6, iclass 11, count 0 2006.182.08:16:39.96#ibcon#read 6, iclass 11, count 0 2006.182.08:16:39.96#ibcon#end of sib2, iclass 11, count 0 2006.182.08:16:39.96#ibcon#*after write, iclass 11, count 0 2006.182.08:16:39.96#ibcon#*before return 0, iclass 11, count 0 2006.182.08:16:39.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:16:39.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:16:39.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:16:39.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:16:39.96$vc4f8/va=7,6 2006.182.08:16:39.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.08:16:39.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.08:16:39.96#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:39.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:16:40.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:16:40.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:16:40.02#ibcon#enter wrdev, iclass 13, count 2 2006.182.08:16:40.02#ibcon#first serial, iclass 13, count 2 2006.182.08:16:40.02#ibcon#enter sib2, iclass 13, count 2 2006.182.08:16:40.02#ibcon#flushed, iclass 13, count 2 2006.182.08:16:40.02#ibcon#about to write, iclass 13, count 2 2006.182.08:16:40.02#ibcon#wrote, iclass 13, count 2 2006.182.08:16:40.02#ibcon#about to read 3, iclass 13, count 2 2006.182.08:16:40.04#ibcon#read 3, iclass 13, count 2 2006.182.08:16:40.04#ibcon#about to read 4, iclass 13, count 2 2006.182.08:16:40.04#ibcon#read 4, iclass 13, count 2 2006.182.08:16:40.04#ibcon#about to read 5, iclass 13, count 2 2006.182.08:16:40.04#ibcon#read 5, iclass 13, count 2 2006.182.08:16:40.04#ibcon#about to read 6, iclass 13, count 2 2006.182.08:16:40.04#ibcon#read 6, iclass 13, count 2 2006.182.08:16:40.04#ibcon#end of sib2, iclass 13, count 2 2006.182.08:16:40.04#ibcon#*mode == 0, iclass 13, count 2 2006.182.08:16:40.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.08:16:40.04#ibcon#[25=AT07-06\r\n] 2006.182.08:16:40.04#ibcon#*before write, iclass 13, count 2 2006.182.08:16:40.04#ibcon#enter sib2, iclass 13, count 2 2006.182.08:16:40.04#ibcon#flushed, iclass 13, count 2 2006.182.08:16:40.04#ibcon#about to write, iclass 13, count 2 2006.182.08:16:40.04#ibcon#wrote, iclass 13, count 2 2006.182.08:16:40.04#ibcon#about to read 3, iclass 13, count 2 2006.182.08:16:40.07#ibcon#read 3, iclass 13, count 2 2006.182.08:16:40.07#ibcon#about to read 4, iclass 13, count 2 2006.182.08:16:40.07#ibcon#read 4, iclass 13, count 2 2006.182.08:16:40.07#ibcon#about to read 5, iclass 13, count 2 2006.182.08:16:40.07#ibcon#read 5, iclass 13, count 2 2006.182.08:16:40.07#ibcon#about to read 6, iclass 13, count 2 2006.182.08:16:40.07#ibcon#read 6, iclass 13, count 2 2006.182.08:16:40.07#ibcon#end of sib2, iclass 13, count 2 2006.182.08:16:40.07#ibcon#*after write, iclass 13, count 2 2006.182.08:16:40.07#ibcon#*before return 0, iclass 13, count 2 2006.182.08:16:40.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:16:40.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:16:40.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.08:16:40.07#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:40.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:16:40.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:16:40.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:16:40.19#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:16:40.19#ibcon#first serial, iclass 13, count 0 2006.182.08:16:40.19#ibcon#enter sib2, iclass 13, count 0 2006.182.08:16:40.19#ibcon#flushed, iclass 13, count 0 2006.182.08:16:40.19#ibcon#about to write, iclass 13, count 0 2006.182.08:16:40.19#ibcon#wrote, iclass 13, count 0 2006.182.08:16:40.19#ibcon#about to read 3, iclass 13, count 0 2006.182.08:16:40.21#ibcon#read 3, iclass 13, count 0 2006.182.08:16:40.21#ibcon#about to read 4, iclass 13, count 0 2006.182.08:16:40.21#ibcon#read 4, iclass 13, count 0 2006.182.08:16:40.21#ibcon#about to read 5, iclass 13, count 0 2006.182.08:16:40.21#ibcon#read 5, iclass 13, count 0 2006.182.08:16:40.21#ibcon#about to read 6, iclass 13, count 0 2006.182.08:16:40.21#ibcon#read 6, iclass 13, count 0 2006.182.08:16:40.21#ibcon#end of sib2, iclass 13, count 0 2006.182.08:16:40.21#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:16:40.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:16:40.21#ibcon#[25=USB\r\n] 2006.182.08:16:40.21#ibcon#*before write, iclass 13, count 0 2006.182.08:16:40.21#ibcon#enter sib2, iclass 13, count 0 2006.182.08:16:40.21#ibcon#flushed, iclass 13, count 0 2006.182.08:16:40.21#ibcon#about to write, iclass 13, count 0 2006.182.08:16:40.21#ibcon#wrote, iclass 13, count 0 2006.182.08:16:40.21#ibcon#about to read 3, iclass 13, count 0 2006.182.08:16:40.24#ibcon#read 3, iclass 13, count 0 2006.182.08:16:40.24#ibcon#about to read 4, iclass 13, count 0 2006.182.08:16:40.24#ibcon#read 4, iclass 13, count 0 2006.182.08:16:40.24#ibcon#about to read 5, iclass 13, count 0 2006.182.08:16:40.24#ibcon#read 5, iclass 13, count 0 2006.182.08:16:40.24#ibcon#about to read 6, iclass 13, count 0 2006.182.08:16:40.24#ibcon#read 6, iclass 13, count 0 2006.182.08:16:40.24#ibcon#end of sib2, iclass 13, count 0 2006.182.08:16:40.24#ibcon#*after write, iclass 13, count 0 2006.182.08:16:40.24#ibcon#*before return 0, iclass 13, count 0 2006.182.08:16:40.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:16:40.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:16:40.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:16:40.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:16:40.24$vc4f8/valo=8,852.99 2006.182.08:16:40.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.08:16:40.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.08:16:40.24#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:40.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:16:40.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:16:40.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:16:40.24#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:16:40.24#ibcon#first serial, iclass 15, count 0 2006.182.08:16:40.24#ibcon#enter sib2, iclass 15, count 0 2006.182.08:16:40.24#ibcon#flushed, iclass 15, count 0 2006.182.08:16:40.24#ibcon#about to write, iclass 15, count 0 2006.182.08:16:40.24#ibcon#wrote, iclass 15, count 0 2006.182.08:16:40.24#ibcon#about to read 3, iclass 15, count 0 2006.182.08:16:40.26#ibcon#read 3, iclass 15, count 0 2006.182.08:16:40.26#ibcon#about to read 4, iclass 15, count 0 2006.182.08:16:40.26#ibcon#read 4, iclass 15, count 0 2006.182.08:16:40.26#ibcon#about to read 5, iclass 15, count 0 2006.182.08:16:40.26#ibcon#read 5, iclass 15, count 0 2006.182.08:16:40.26#ibcon#about to read 6, iclass 15, count 0 2006.182.08:16:40.26#ibcon#read 6, iclass 15, count 0 2006.182.08:16:40.26#ibcon#end of sib2, iclass 15, count 0 2006.182.08:16:40.26#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:16:40.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:16:40.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:16:40.26#ibcon#*before write, iclass 15, count 0 2006.182.08:16:40.26#ibcon#enter sib2, iclass 15, count 0 2006.182.08:16:40.26#ibcon#flushed, iclass 15, count 0 2006.182.08:16:40.26#ibcon#about to write, iclass 15, count 0 2006.182.08:16:40.26#ibcon#wrote, iclass 15, count 0 2006.182.08:16:40.26#ibcon#about to read 3, iclass 15, count 0 2006.182.08:16:40.30#ibcon#read 3, iclass 15, count 0 2006.182.08:16:40.30#ibcon#about to read 4, iclass 15, count 0 2006.182.08:16:40.30#ibcon#read 4, iclass 15, count 0 2006.182.08:16:40.30#ibcon#about to read 5, iclass 15, count 0 2006.182.08:16:40.30#ibcon#read 5, iclass 15, count 0 2006.182.08:16:40.30#ibcon#about to read 6, iclass 15, count 0 2006.182.08:16:40.30#ibcon#read 6, iclass 15, count 0 2006.182.08:16:40.30#ibcon#end of sib2, iclass 15, count 0 2006.182.08:16:40.30#ibcon#*after write, iclass 15, count 0 2006.182.08:16:40.30#ibcon#*before return 0, iclass 15, count 0 2006.182.08:16:40.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:16:40.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:16:40.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:16:40.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:16:40.30$vc4f8/va=8,7 2006.182.08:16:40.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.08:16:40.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.08:16:40.30#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:40.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:16:40.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:16:40.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:16:40.36#ibcon#enter wrdev, iclass 17, count 2 2006.182.08:16:40.36#ibcon#first serial, iclass 17, count 2 2006.182.08:16:40.36#ibcon#enter sib2, iclass 17, count 2 2006.182.08:16:40.36#ibcon#flushed, iclass 17, count 2 2006.182.08:16:40.36#ibcon#about to write, iclass 17, count 2 2006.182.08:16:40.36#ibcon#wrote, iclass 17, count 2 2006.182.08:16:40.36#ibcon#about to read 3, iclass 17, count 2 2006.182.08:16:40.38#ibcon#read 3, iclass 17, count 2 2006.182.08:16:40.38#ibcon#about to read 4, iclass 17, count 2 2006.182.08:16:40.38#ibcon#read 4, iclass 17, count 2 2006.182.08:16:40.38#ibcon#about to read 5, iclass 17, count 2 2006.182.08:16:40.38#ibcon#read 5, iclass 17, count 2 2006.182.08:16:40.38#ibcon#about to read 6, iclass 17, count 2 2006.182.08:16:40.38#ibcon#read 6, iclass 17, count 2 2006.182.08:16:40.38#ibcon#end of sib2, iclass 17, count 2 2006.182.08:16:40.38#ibcon#*mode == 0, iclass 17, count 2 2006.182.08:16:40.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.08:16:40.38#ibcon#[25=AT08-07\r\n] 2006.182.08:16:40.38#ibcon#*before write, iclass 17, count 2 2006.182.08:16:40.38#ibcon#enter sib2, iclass 17, count 2 2006.182.08:16:40.38#ibcon#flushed, iclass 17, count 2 2006.182.08:16:40.38#ibcon#about to write, iclass 17, count 2 2006.182.08:16:40.38#ibcon#wrote, iclass 17, count 2 2006.182.08:16:40.38#ibcon#about to read 3, iclass 17, count 2 2006.182.08:16:40.41#ibcon#read 3, iclass 17, count 2 2006.182.08:16:40.41#ibcon#about to read 4, iclass 17, count 2 2006.182.08:16:40.41#ibcon#read 4, iclass 17, count 2 2006.182.08:16:40.41#ibcon#about to read 5, iclass 17, count 2 2006.182.08:16:40.41#ibcon#read 5, iclass 17, count 2 2006.182.08:16:40.41#ibcon#about to read 6, iclass 17, count 2 2006.182.08:16:40.41#ibcon#read 6, iclass 17, count 2 2006.182.08:16:40.41#ibcon#end of sib2, iclass 17, count 2 2006.182.08:16:40.41#ibcon#*after write, iclass 17, count 2 2006.182.08:16:40.41#ibcon#*before return 0, iclass 17, count 2 2006.182.08:16:40.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:16:40.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:16:40.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.08:16:40.41#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:40.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:16:40.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:16:40.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:16:40.53#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:16:40.53#ibcon#first serial, iclass 17, count 0 2006.182.08:16:40.53#ibcon#enter sib2, iclass 17, count 0 2006.182.08:16:40.53#ibcon#flushed, iclass 17, count 0 2006.182.08:16:40.53#ibcon#about to write, iclass 17, count 0 2006.182.08:16:40.53#ibcon#wrote, iclass 17, count 0 2006.182.08:16:40.53#ibcon#about to read 3, iclass 17, count 0 2006.182.08:16:40.55#ibcon#read 3, iclass 17, count 0 2006.182.08:16:40.55#ibcon#about to read 4, iclass 17, count 0 2006.182.08:16:40.55#ibcon#read 4, iclass 17, count 0 2006.182.08:16:40.55#ibcon#about to read 5, iclass 17, count 0 2006.182.08:16:40.55#ibcon#read 5, iclass 17, count 0 2006.182.08:16:40.55#ibcon#about to read 6, iclass 17, count 0 2006.182.08:16:40.55#ibcon#read 6, iclass 17, count 0 2006.182.08:16:40.55#ibcon#end of sib2, iclass 17, count 0 2006.182.08:16:40.55#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:16:40.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:16:40.55#ibcon#[25=USB\r\n] 2006.182.08:16:40.55#ibcon#*before write, iclass 17, count 0 2006.182.08:16:40.55#ibcon#enter sib2, iclass 17, count 0 2006.182.08:16:40.55#ibcon#flushed, iclass 17, count 0 2006.182.08:16:40.55#ibcon#about to write, iclass 17, count 0 2006.182.08:16:40.55#ibcon#wrote, iclass 17, count 0 2006.182.08:16:40.55#ibcon#about to read 3, iclass 17, count 0 2006.182.08:16:40.58#ibcon#read 3, iclass 17, count 0 2006.182.08:16:40.58#ibcon#about to read 4, iclass 17, count 0 2006.182.08:16:40.58#ibcon#read 4, iclass 17, count 0 2006.182.08:16:40.58#ibcon#about to read 5, iclass 17, count 0 2006.182.08:16:40.58#ibcon#read 5, iclass 17, count 0 2006.182.08:16:40.58#ibcon#about to read 6, iclass 17, count 0 2006.182.08:16:40.58#ibcon#read 6, iclass 17, count 0 2006.182.08:16:40.58#ibcon#end of sib2, iclass 17, count 0 2006.182.08:16:40.58#ibcon#*after write, iclass 17, count 0 2006.182.08:16:40.58#ibcon#*before return 0, iclass 17, count 0 2006.182.08:16:40.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:16:40.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:16:40.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:16:40.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:16:40.58$vc4f8/vblo=1,632.99 2006.182.08:16:40.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.08:16:40.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.08:16:40.58#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:40.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:40.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:40.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:40.58#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:16:40.58#ibcon#first serial, iclass 19, count 0 2006.182.08:16:40.58#ibcon#enter sib2, iclass 19, count 0 2006.182.08:16:40.58#ibcon#flushed, iclass 19, count 0 2006.182.08:16:40.58#ibcon#about to write, iclass 19, count 0 2006.182.08:16:40.58#ibcon#wrote, iclass 19, count 0 2006.182.08:16:40.58#ibcon#about to read 3, iclass 19, count 0 2006.182.08:16:40.60#ibcon#read 3, iclass 19, count 0 2006.182.08:16:40.60#ibcon#about to read 4, iclass 19, count 0 2006.182.08:16:40.60#ibcon#read 4, iclass 19, count 0 2006.182.08:16:40.60#ibcon#about to read 5, iclass 19, count 0 2006.182.08:16:40.60#ibcon#read 5, iclass 19, count 0 2006.182.08:16:40.60#ibcon#about to read 6, iclass 19, count 0 2006.182.08:16:40.60#ibcon#read 6, iclass 19, count 0 2006.182.08:16:40.60#ibcon#end of sib2, iclass 19, count 0 2006.182.08:16:40.60#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:16:40.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:16:40.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:16:40.60#ibcon#*before write, iclass 19, count 0 2006.182.08:16:40.60#ibcon#enter sib2, iclass 19, count 0 2006.182.08:16:40.60#ibcon#flushed, iclass 19, count 0 2006.182.08:16:40.60#ibcon#about to write, iclass 19, count 0 2006.182.08:16:40.60#ibcon#wrote, iclass 19, count 0 2006.182.08:16:40.60#ibcon#about to read 3, iclass 19, count 0 2006.182.08:16:40.64#ibcon#read 3, iclass 19, count 0 2006.182.08:16:40.64#ibcon#about to read 4, iclass 19, count 0 2006.182.08:16:40.64#ibcon#read 4, iclass 19, count 0 2006.182.08:16:40.64#ibcon#about to read 5, iclass 19, count 0 2006.182.08:16:40.64#ibcon#read 5, iclass 19, count 0 2006.182.08:16:40.64#ibcon#about to read 6, iclass 19, count 0 2006.182.08:16:40.64#ibcon#read 6, iclass 19, count 0 2006.182.08:16:40.64#ibcon#end of sib2, iclass 19, count 0 2006.182.08:16:40.64#ibcon#*after write, iclass 19, count 0 2006.182.08:16:40.64#ibcon#*before return 0, iclass 19, count 0 2006.182.08:16:40.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:40.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:16:40.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:16:40.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:16:40.64$vc4f8/vb=1,4 2006.182.08:16:40.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.08:16:40.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.08:16:40.64#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:40.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:40.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:40.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:40.64#ibcon#enter wrdev, iclass 21, count 2 2006.182.08:16:40.64#ibcon#first serial, iclass 21, count 2 2006.182.08:16:40.64#ibcon#enter sib2, iclass 21, count 2 2006.182.08:16:40.64#ibcon#flushed, iclass 21, count 2 2006.182.08:16:40.64#ibcon#about to write, iclass 21, count 2 2006.182.08:16:40.64#ibcon#wrote, iclass 21, count 2 2006.182.08:16:40.64#ibcon#about to read 3, iclass 21, count 2 2006.182.08:16:40.66#ibcon#read 3, iclass 21, count 2 2006.182.08:16:40.66#ibcon#about to read 4, iclass 21, count 2 2006.182.08:16:40.66#ibcon#read 4, iclass 21, count 2 2006.182.08:16:40.66#ibcon#about to read 5, iclass 21, count 2 2006.182.08:16:40.66#ibcon#read 5, iclass 21, count 2 2006.182.08:16:40.66#ibcon#about to read 6, iclass 21, count 2 2006.182.08:16:40.66#ibcon#read 6, iclass 21, count 2 2006.182.08:16:40.66#ibcon#end of sib2, iclass 21, count 2 2006.182.08:16:40.66#ibcon#*mode == 0, iclass 21, count 2 2006.182.08:16:40.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.08:16:40.66#ibcon#[27=AT01-04\r\n] 2006.182.08:16:40.66#ibcon#*before write, iclass 21, count 2 2006.182.08:16:40.66#ibcon#enter sib2, iclass 21, count 2 2006.182.08:16:40.66#ibcon#flushed, iclass 21, count 2 2006.182.08:16:40.66#ibcon#about to write, iclass 21, count 2 2006.182.08:16:40.66#ibcon#wrote, iclass 21, count 2 2006.182.08:16:40.66#ibcon#about to read 3, iclass 21, count 2 2006.182.08:16:40.69#ibcon#read 3, iclass 21, count 2 2006.182.08:16:40.69#ibcon#about to read 4, iclass 21, count 2 2006.182.08:16:40.69#ibcon#read 4, iclass 21, count 2 2006.182.08:16:40.69#ibcon#about to read 5, iclass 21, count 2 2006.182.08:16:40.69#ibcon#read 5, iclass 21, count 2 2006.182.08:16:40.69#ibcon#about to read 6, iclass 21, count 2 2006.182.08:16:40.69#ibcon#read 6, iclass 21, count 2 2006.182.08:16:40.69#ibcon#end of sib2, iclass 21, count 2 2006.182.08:16:40.69#ibcon#*after write, iclass 21, count 2 2006.182.08:16:40.69#ibcon#*before return 0, iclass 21, count 2 2006.182.08:16:40.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:40.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:16:40.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.08:16:40.69#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:40.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:40.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:40.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:40.81#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:16:40.81#ibcon#first serial, iclass 21, count 0 2006.182.08:16:40.81#ibcon#enter sib2, iclass 21, count 0 2006.182.08:16:40.81#ibcon#flushed, iclass 21, count 0 2006.182.08:16:40.81#ibcon#about to write, iclass 21, count 0 2006.182.08:16:40.81#ibcon#wrote, iclass 21, count 0 2006.182.08:16:40.81#ibcon#about to read 3, iclass 21, count 0 2006.182.08:16:40.83#ibcon#read 3, iclass 21, count 0 2006.182.08:16:40.83#ibcon#about to read 4, iclass 21, count 0 2006.182.08:16:40.83#ibcon#read 4, iclass 21, count 0 2006.182.08:16:40.83#ibcon#about to read 5, iclass 21, count 0 2006.182.08:16:40.83#ibcon#read 5, iclass 21, count 0 2006.182.08:16:40.83#ibcon#about to read 6, iclass 21, count 0 2006.182.08:16:40.83#ibcon#read 6, iclass 21, count 0 2006.182.08:16:40.83#ibcon#end of sib2, iclass 21, count 0 2006.182.08:16:40.83#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:16:40.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:16:40.83#ibcon#[27=USB\r\n] 2006.182.08:16:40.83#ibcon#*before write, iclass 21, count 0 2006.182.08:16:40.83#ibcon#enter sib2, iclass 21, count 0 2006.182.08:16:40.83#ibcon#flushed, iclass 21, count 0 2006.182.08:16:40.83#ibcon#about to write, iclass 21, count 0 2006.182.08:16:40.83#ibcon#wrote, iclass 21, count 0 2006.182.08:16:40.83#ibcon#about to read 3, iclass 21, count 0 2006.182.08:16:40.86#ibcon#read 3, iclass 21, count 0 2006.182.08:16:40.86#ibcon#about to read 4, iclass 21, count 0 2006.182.08:16:40.86#ibcon#read 4, iclass 21, count 0 2006.182.08:16:40.86#ibcon#about to read 5, iclass 21, count 0 2006.182.08:16:40.86#ibcon#read 5, iclass 21, count 0 2006.182.08:16:40.86#ibcon#about to read 6, iclass 21, count 0 2006.182.08:16:40.86#ibcon#read 6, iclass 21, count 0 2006.182.08:16:40.86#ibcon#end of sib2, iclass 21, count 0 2006.182.08:16:40.86#ibcon#*after write, iclass 21, count 0 2006.182.08:16:40.86#ibcon#*before return 0, iclass 21, count 0 2006.182.08:16:40.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:40.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:16:40.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:16:40.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:16:40.86$vc4f8/vblo=2,640.99 2006.182.08:16:40.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.08:16:40.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.08:16:40.86#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:40.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:40.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:40.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:40.86#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:16:40.86#ibcon#first serial, iclass 23, count 0 2006.182.08:16:40.86#ibcon#enter sib2, iclass 23, count 0 2006.182.08:16:40.86#ibcon#flushed, iclass 23, count 0 2006.182.08:16:40.86#ibcon#about to write, iclass 23, count 0 2006.182.08:16:40.86#ibcon#wrote, iclass 23, count 0 2006.182.08:16:40.86#ibcon#about to read 3, iclass 23, count 0 2006.182.08:16:40.88#ibcon#read 3, iclass 23, count 0 2006.182.08:16:40.88#ibcon#about to read 4, iclass 23, count 0 2006.182.08:16:40.88#ibcon#read 4, iclass 23, count 0 2006.182.08:16:40.88#ibcon#about to read 5, iclass 23, count 0 2006.182.08:16:40.88#ibcon#read 5, iclass 23, count 0 2006.182.08:16:40.88#ibcon#about to read 6, iclass 23, count 0 2006.182.08:16:40.88#ibcon#read 6, iclass 23, count 0 2006.182.08:16:40.88#ibcon#end of sib2, iclass 23, count 0 2006.182.08:16:40.88#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:16:40.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:16:40.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:16:40.88#ibcon#*before write, iclass 23, count 0 2006.182.08:16:40.88#ibcon#enter sib2, iclass 23, count 0 2006.182.08:16:40.88#ibcon#flushed, iclass 23, count 0 2006.182.08:16:40.88#ibcon#about to write, iclass 23, count 0 2006.182.08:16:40.88#ibcon#wrote, iclass 23, count 0 2006.182.08:16:40.88#ibcon#about to read 3, iclass 23, count 0 2006.182.08:16:40.92#ibcon#read 3, iclass 23, count 0 2006.182.08:16:40.92#ibcon#about to read 4, iclass 23, count 0 2006.182.08:16:40.92#ibcon#read 4, iclass 23, count 0 2006.182.08:16:40.92#ibcon#about to read 5, iclass 23, count 0 2006.182.08:16:40.92#ibcon#read 5, iclass 23, count 0 2006.182.08:16:40.92#ibcon#about to read 6, iclass 23, count 0 2006.182.08:16:40.92#ibcon#read 6, iclass 23, count 0 2006.182.08:16:40.92#ibcon#end of sib2, iclass 23, count 0 2006.182.08:16:40.92#ibcon#*after write, iclass 23, count 0 2006.182.08:16:40.92#ibcon#*before return 0, iclass 23, count 0 2006.182.08:16:40.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:40.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:16:40.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:16:40.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:16:40.92$vc4f8/vb=2,4 2006.182.08:16:40.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.08:16:40.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.08:16:40.92#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:40.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:40.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:40.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:40.98#ibcon#enter wrdev, iclass 25, count 2 2006.182.08:16:40.98#ibcon#first serial, iclass 25, count 2 2006.182.08:16:40.98#ibcon#enter sib2, iclass 25, count 2 2006.182.08:16:40.98#ibcon#flushed, iclass 25, count 2 2006.182.08:16:40.98#ibcon#about to write, iclass 25, count 2 2006.182.08:16:40.98#ibcon#wrote, iclass 25, count 2 2006.182.08:16:40.98#ibcon#about to read 3, iclass 25, count 2 2006.182.08:16:41.00#ibcon#read 3, iclass 25, count 2 2006.182.08:16:41.00#ibcon#about to read 4, iclass 25, count 2 2006.182.08:16:41.00#ibcon#read 4, iclass 25, count 2 2006.182.08:16:41.00#ibcon#about to read 5, iclass 25, count 2 2006.182.08:16:41.00#ibcon#read 5, iclass 25, count 2 2006.182.08:16:41.00#ibcon#about to read 6, iclass 25, count 2 2006.182.08:16:41.00#ibcon#read 6, iclass 25, count 2 2006.182.08:16:41.00#ibcon#end of sib2, iclass 25, count 2 2006.182.08:16:41.00#ibcon#*mode == 0, iclass 25, count 2 2006.182.08:16:41.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.08:16:41.00#ibcon#[27=AT02-04\r\n] 2006.182.08:16:41.00#ibcon#*before write, iclass 25, count 2 2006.182.08:16:41.00#ibcon#enter sib2, iclass 25, count 2 2006.182.08:16:41.00#ibcon#flushed, iclass 25, count 2 2006.182.08:16:41.00#ibcon#about to write, iclass 25, count 2 2006.182.08:16:41.00#ibcon#wrote, iclass 25, count 2 2006.182.08:16:41.00#ibcon#about to read 3, iclass 25, count 2 2006.182.08:16:41.03#ibcon#read 3, iclass 25, count 2 2006.182.08:16:41.03#ibcon#about to read 4, iclass 25, count 2 2006.182.08:16:41.03#ibcon#read 4, iclass 25, count 2 2006.182.08:16:41.03#ibcon#about to read 5, iclass 25, count 2 2006.182.08:16:41.03#ibcon#read 5, iclass 25, count 2 2006.182.08:16:41.03#ibcon#about to read 6, iclass 25, count 2 2006.182.08:16:41.03#ibcon#read 6, iclass 25, count 2 2006.182.08:16:41.03#ibcon#end of sib2, iclass 25, count 2 2006.182.08:16:41.03#ibcon#*after write, iclass 25, count 2 2006.182.08:16:41.03#ibcon#*before return 0, iclass 25, count 2 2006.182.08:16:41.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:41.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:16:41.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.08:16:41.03#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:41.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:41.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:41.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:41.15#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:16:41.15#ibcon#first serial, iclass 25, count 0 2006.182.08:16:41.15#ibcon#enter sib2, iclass 25, count 0 2006.182.08:16:41.15#ibcon#flushed, iclass 25, count 0 2006.182.08:16:41.15#ibcon#about to write, iclass 25, count 0 2006.182.08:16:41.15#ibcon#wrote, iclass 25, count 0 2006.182.08:16:41.15#ibcon#about to read 3, iclass 25, count 0 2006.182.08:16:41.17#ibcon#read 3, iclass 25, count 0 2006.182.08:16:41.17#ibcon#about to read 4, iclass 25, count 0 2006.182.08:16:41.17#ibcon#read 4, iclass 25, count 0 2006.182.08:16:41.17#ibcon#about to read 5, iclass 25, count 0 2006.182.08:16:41.17#ibcon#read 5, iclass 25, count 0 2006.182.08:16:41.17#ibcon#about to read 6, iclass 25, count 0 2006.182.08:16:41.17#ibcon#read 6, iclass 25, count 0 2006.182.08:16:41.17#ibcon#end of sib2, iclass 25, count 0 2006.182.08:16:41.17#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:16:41.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:16:41.17#ibcon#[27=USB\r\n] 2006.182.08:16:41.17#ibcon#*before write, iclass 25, count 0 2006.182.08:16:41.17#ibcon#enter sib2, iclass 25, count 0 2006.182.08:16:41.17#ibcon#flushed, iclass 25, count 0 2006.182.08:16:41.17#ibcon#about to write, iclass 25, count 0 2006.182.08:16:41.17#ibcon#wrote, iclass 25, count 0 2006.182.08:16:41.17#ibcon#about to read 3, iclass 25, count 0 2006.182.08:16:41.20#ibcon#read 3, iclass 25, count 0 2006.182.08:16:41.20#ibcon#about to read 4, iclass 25, count 0 2006.182.08:16:41.20#ibcon#read 4, iclass 25, count 0 2006.182.08:16:41.20#ibcon#about to read 5, iclass 25, count 0 2006.182.08:16:41.20#ibcon#read 5, iclass 25, count 0 2006.182.08:16:41.20#ibcon#about to read 6, iclass 25, count 0 2006.182.08:16:41.20#ibcon#read 6, iclass 25, count 0 2006.182.08:16:41.20#ibcon#end of sib2, iclass 25, count 0 2006.182.08:16:41.20#ibcon#*after write, iclass 25, count 0 2006.182.08:16:41.20#ibcon#*before return 0, iclass 25, count 0 2006.182.08:16:41.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:41.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:16:41.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:16:41.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:16:41.20$vc4f8/vblo=3,656.99 2006.182.08:16:41.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.08:16:41.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.08:16:41.20#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:41.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:41.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:41.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:41.20#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:16:41.20#ibcon#first serial, iclass 27, count 0 2006.182.08:16:41.20#ibcon#enter sib2, iclass 27, count 0 2006.182.08:16:41.20#ibcon#flushed, iclass 27, count 0 2006.182.08:16:41.20#ibcon#about to write, iclass 27, count 0 2006.182.08:16:41.20#ibcon#wrote, iclass 27, count 0 2006.182.08:16:41.20#ibcon#about to read 3, iclass 27, count 0 2006.182.08:16:41.22#ibcon#read 3, iclass 27, count 0 2006.182.08:16:41.22#ibcon#about to read 4, iclass 27, count 0 2006.182.08:16:41.22#ibcon#read 4, iclass 27, count 0 2006.182.08:16:41.22#ibcon#about to read 5, iclass 27, count 0 2006.182.08:16:41.22#ibcon#read 5, iclass 27, count 0 2006.182.08:16:41.22#ibcon#about to read 6, iclass 27, count 0 2006.182.08:16:41.22#ibcon#read 6, iclass 27, count 0 2006.182.08:16:41.22#ibcon#end of sib2, iclass 27, count 0 2006.182.08:16:41.22#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:16:41.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:16:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:16:41.22#ibcon#*before write, iclass 27, count 0 2006.182.08:16:41.22#ibcon#enter sib2, iclass 27, count 0 2006.182.08:16:41.22#ibcon#flushed, iclass 27, count 0 2006.182.08:16:41.22#ibcon#about to write, iclass 27, count 0 2006.182.08:16:41.22#ibcon#wrote, iclass 27, count 0 2006.182.08:16:41.22#ibcon#about to read 3, iclass 27, count 0 2006.182.08:16:41.26#ibcon#read 3, iclass 27, count 0 2006.182.08:16:41.26#ibcon#about to read 4, iclass 27, count 0 2006.182.08:16:41.26#ibcon#read 4, iclass 27, count 0 2006.182.08:16:41.26#ibcon#about to read 5, iclass 27, count 0 2006.182.08:16:41.26#ibcon#read 5, iclass 27, count 0 2006.182.08:16:41.26#ibcon#about to read 6, iclass 27, count 0 2006.182.08:16:41.26#ibcon#read 6, iclass 27, count 0 2006.182.08:16:41.26#ibcon#end of sib2, iclass 27, count 0 2006.182.08:16:41.26#ibcon#*after write, iclass 27, count 0 2006.182.08:16:41.26#ibcon#*before return 0, iclass 27, count 0 2006.182.08:16:41.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:41.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:16:41.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:16:41.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:16:41.26$vc4f8/vb=3,4 2006.182.08:16:41.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.08:16:41.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.08:16:41.26#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:41.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:41.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:41.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:41.32#ibcon#enter wrdev, iclass 29, count 2 2006.182.08:16:41.32#ibcon#first serial, iclass 29, count 2 2006.182.08:16:41.32#ibcon#enter sib2, iclass 29, count 2 2006.182.08:16:41.32#ibcon#flushed, iclass 29, count 2 2006.182.08:16:41.32#ibcon#about to write, iclass 29, count 2 2006.182.08:16:41.32#ibcon#wrote, iclass 29, count 2 2006.182.08:16:41.32#ibcon#about to read 3, iclass 29, count 2 2006.182.08:16:41.34#ibcon#read 3, iclass 29, count 2 2006.182.08:16:41.34#ibcon#about to read 4, iclass 29, count 2 2006.182.08:16:41.34#ibcon#read 4, iclass 29, count 2 2006.182.08:16:41.34#ibcon#about to read 5, iclass 29, count 2 2006.182.08:16:41.34#ibcon#read 5, iclass 29, count 2 2006.182.08:16:41.34#ibcon#about to read 6, iclass 29, count 2 2006.182.08:16:41.34#ibcon#read 6, iclass 29, count 2 2006.182.08:16:41.34#ibcon#end of sib2, iclass 29, count 2 2006.182.08:16:41.34#ibcon#*mode == 0, iclass 29, count 2 2006.182.08:16:41.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.08:16:41.34#ibcon#[27=AT03-04\r\n] 2006.182.08:16:41.34#ibcon#*before write, iclass 29, count 2 2006.182.08:16:41.34#ibcon#enter sib2, iclass 29, count 2 2006.182.08:16:41.34#ibcon#flushed, iclass 29, count 2 2006.182.08:16:41.34#ibcon#about to write, iclass 29, count 2 2006.182.08:16:41.34#ibcon#wrote, iclass 29, count 2 2006.182.08:16:41.34#ibcon#about to read 3, iclass 29, count 2 2006.182.08:16:41.37#ibcon#read 3, iclass 29, count 2 2006.182.08:16:41.37#ibcon#about to read 4, iclass 29, count 2 2006.182.08:16:41.37#ibcon#read 4, iclass 29, count 2 2006.182.08:16:41.37#ibcon#about to read 5, iclass 29, count 2 2006.182.08:16:41.37#ibcon#read 5, iclass 29, count 2 2006.182.08:16:41.37#ibcon#about to read 6, iclass 29, count 2 2006.182.08:16:41.37#ibcon#read 6, iclass 29, count 2 2006.182.08:16:41.37#ibcon#end of sib2, iclass 29, count 2 2006.182.08:16:41.37#ibcon#*after write, iclass 29, count 2 2006.182.08:16:41.37#ibcon#*before return 0, iclass 29, count 2 2006.182.08:16:41.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:41.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:16:41.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.08:16:41.37#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:41.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:41.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:41.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:41.49#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:16:41.49#ibcon#first serial, iclass 29, count 0 2006.182.08:16:41.49#ibcon#enter sib2, iclass 29, count 0 2006.182.08:16:41.49#ibcon#flushed, iclass 29, count 0 2006.182.08:16:41.49#ibcon#about to write, iclass 29, count 0 2006.182.08:16:41.49#ibcon#wrote, iclass 29, count 0 2006.182.08:16:41.49#ibcon#about to read 3, iclass 29, count 0 2006.182.08:16:41.51#ibcon#read 3, iclass 29, count 0 2006.182.08:16:41.51#ibcon#about to read 4, iclass 29, count 0 2006.182.08:16:41.51#ibcon#read 4, iclass 29, count 0 2006.182.08:16:41.51#ibcon#about to read 5, iclass 29, count 0 2006.182.08:16:41.51#ibcon#read 5, iclass 29, count 0 2006.182.08:16:41.51#ibcon#about to read 6, iclass 29, count 0 2006.182.08:16:41.51#ibcon#read 6, iclass 29, count 0 2006.182.08:16:41.51#ibcon#end of sib2, iclass 29, count 0 2006.182.08:16:41.51#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:16:41.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:16:41.51#ibcon#[27=USB\r\n] 2006.182.08:16:41.51#ibcon#*before write, iclass 29, count 0 2006.182.08:16:41.51#ibcon#enter sib2, iclass 29, count 0 2006.182.08:16:41.51#ibcon#flushed, iclass 29, count 0 2006.182.08:16:41.51#ibcon#about to write, iclass 29, count 0 2006.182.08:16:41.51#ibcon#wrote, iclass 29, count 0 2006.182.08:16:41.51#ibcon#about to read 3, iclass 29, count 0 2006.182.08:16:41.54#ibcon#read 3, iclass 29, count 0 2006.182.08:16:41.54#ibcon#about to read 4, iclass 29, count 0 2006.182.08:16:41.54#ibcon#read 4, iclass 29, count 0 2006.182.08:16:41.54#ibcon#about to read 5, iclass 29, count 0 2006.182.08:16:41.54#ibcon#read 5, iclass 29, count 0 2006.182.08:16:41.54#ibcon#about to read 6, iclass 29, count 0 2006.182.08:16:41.54#ibcon#read 6, iclass 29, count 0 2006.182.08:16:41.54#ibcon#end of sib2, iclass 29, count 0 2006.182.08:16:41.54#ibcon#*after write, iclass 29, count 0 2006.182.08:16:41.54#ibcon#*before return 0, iclass 29, count 0 2006.182.08:16:41.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:41.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:16:41.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:16:41.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:16:41.54$vc4f8/vblo=4,712.99 2006.182.08:16:41.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.08:16:41.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.08:16:41.54#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:41.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:41.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:41.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:41.54#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:16:41.54#ibcon#first serial, iclass 31, count 0 2006.182.08:16:41.54#ibcon#enter sib2, iclass 31, count 0 2006.182.08:16:41.54#ibcon#flushed, iclass 31, count 0 2006.182.08:16:41.54#ibcon#about to write, iclass 31, count 0 2006.182.08:16:41.54#ibcon#wrote, iclass 31, count 0 2006.182.08:16:41.54#ibcon#about to read 3, iclass 31, count 0 2006.182.08:16:41.56#ibcon#read 3, iclass 31, count 0 2006.182.08:16:41.56#ibcon#about to read 4, iclass 31, count 0 2006.182.08:16:41.56#ibcon#read 4, iclass 31, count 0 2006.182.08:16:41.56#ibcon#about to read 5, iclass 31, count 0 2006.182.08:16:41.56#ibcon#read 5, iclass 31, count 0 2006.182.08:16:41.56#ibcon#about to read 6, iclass 31, count 0 2006.182.08:16:41.56#ibcon#read 6, iclass 31, count 0 2006.182.08:16:41.56#ibcon#end of sib2, iclass 31, count 0 2006.182.08:16:41.56#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:16:41.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:16:41.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:16:41.56#ibcon#*before write, iclass 31, count 0 2006.182.08:16:41.56#ibcon#enter sib2, iclass 31, count 0 2006.182.08:16:41.56#ibcon#flushed, iclass 31, count 0 2006.182.08:16:41.56#ibcon#about to write, iclass 31, count 0 2006.182.08:16:41.56#ibcon#wrote, iclass 31, count 0 2006.182.08:16:41.56#ibcon#about to read 3, iclass 31, count 0 2006.182.08:16:41.60#ibcon#read 3, iclass 31, count 0 2006.182.08:16:41.60#ibcon#about to read 4, iclass 31, count 0 2006.182.08:16:41.60#ibcon#read 4, iclass 31, count 0 2006.182.08:16:41.60#ibcon#about to read 5, iclass 31, count 0 2006.182.08:16:41.60#ibcon#read 5, iclass 31, count 0 2006.182.08:16:41.60#ibcon#about to read 6, iclass 31, count 0 2006.182.08:16:41.60#ibcon#read 6, iclass 31, count 0 2006.182.08:16:41.60#ibcon#end of sib2, iclass 31, count 0 2006.182.08:16:41.60#ibcon#*after write, iclass 31, count 0 2006.182.08:16:41.60#ibcon#*before return 0, iclass 31, count 0 2006.182.08:16:41.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:41.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:16:41.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:16:41.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:16:41.60$vc4f8/vb=4,4 2006.182.08:16:41.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.08:16:41.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.08:16:41.60#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:41.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:41.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:41.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:41.66#ibcon#enter wrdev, iclass 33, count 2 2006.182.08:16:41.66#ibcon#first serial, iclass 33, count 2 2006.182.08:16:41.66#ibcon#enter sib2, iclass 33, count 2 2006.182.08:16:41.66#ibcon#flushed, iclass 33, count 2 2006.182.08:16:41.66#ibcon#about to write, iclass 33, count 2 2006.182.08:16:41.66#ibcon#wrote, iclass 33, count 2 2006.182.08:16:41.66#ibcon#about to read 3, iclass 33, count 2 2006.182.08:16:41.68#ibcon#read 3, iclass 33, count 2 2006.182.08:16:41.68#ibcon#about to read 4, iclass 33, count 2 2006.182.08:16:41.68#ibcon#read 4, iclass 33, count 2 2006.182.08:16:41.68#ibcon#about to read 5, iclass 33, count 2 2006.182.08:16:41.68#ibcon#read 5, iclass 33, count 2 2006.182.08:16:41.68#ibcon#about to read 6, iclass 33, count 2 2006.182.08:16:41.68#ibcon#read 6, iclass 33, count 2 2006.182.08:16:41.68#ibcon#end of sib2, iclass 33, count 2 2006.182.08:16:41.68#ibcon#*mode == 0, iclass 33, count 2 2006.182.08:16:41.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.08:16:41.68#ibcon#[27=AT04-04\r\n] 2006.182.08:16:41.68#ibcon#*before write, iclass 33, count 2 2006.182.08:16:41.68#ibcon#enter sib2, iclass 33, count 2 2006.182.08:16:41.68#ibcon#flushed, iclass 33, count 2 2006.182.08:16:41.68#ibcon#about to write, iclass 33, count 2 2006.182.08:16:41.68#ibcon#wrote, iclass 33, count 2 2006.182.08:16:41.68#ibcon#about to read 3, iclass 33, count 2 2006.182.08:16:41.71#ibcon#read 3, iclass 33, count 2 2006.182.08:16:41.71#ibcon#about to read 4, iclass 33, count 2 2006.182.08:16:41.71#ibcon#read 4, iclass 33, count 2 2006.182.08:16:41.71#ibcon#about to read 5, iclass 33, count 2 2006.182.08:16:41.71#ibcon#read 5, iclass 33, count 2 2006.182.08:16:41.71#ibcon#about to read 6, iclass 33, count 2 2006.182.08:16:41.71#ibcon#read 6, iclass 33, count 2 2006.182.08:16:41.71#ibcon#end of sib2, iclass 33, count 2 2006.182.08:16:41.71#ibcon#*after write, iclass 33, count 2 2006.182.08:16:41.71#ibcon#*before return 0, iclass 33, count 2 2006.182.08:16:41.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:41.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:16:41.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.08:16:41.71#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:41.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:41.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:41.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:41.83#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:16:41.83#ibcon#first serial, iclass 33, count 0 2006.182.08:16:41.83#ibcon#enter sib2, iclass 33, count 0 2006.182.08:16:41.83#ibcon#flushed, iclass 33, count 0 2006.182.08:16:41.83#ibcon#about to write, iclass 33, count 0 2006.182.08:16:41.83#ibcon#wrote, iclass 33, count 0 2006.182.08:16:41.83#ibcon#about to read 3, iclass 33, count 0 2006.182.08:16:41.85#ibcon#read 3, iclass 33, count 0 2006.182.08:16:41.85#ibcon#about to read 4, iclass 33, count 0 2006.182.08:16:41.85#ibcon#read 4, iclass 33, count 0 2006.182.08:16:41.85#ibcon#about to read 5, iclass 33, count 0 2006.182.08:16:41.85#ibcon#read 5, iclass 33, count 0 2006.182.08:16:41.85#ibcon#about to read 6, iclass 33, count 0 2006.182.08:16:41.85#ibcon#read 6, iclass 33, count 0 2006.182.08:16:41.85#ibcon#end of sib2, iclass 33, count 0 2006.182.08:16:41.85#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:16:41.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:16:41.85#ibcon#[27=USB\r\n] 2006.182.08:16:41.85#ibcon#*before write, iclass 33, count 0 2006.182.08:16:41.85#ibcon#enter sib2, iclass 33, count 0 2006.182.08:16:41.85#ibcon#flushed, iclass 33, count 0 2006.182.08:16:41.85#ibcon#about to write, iclass 33, count 0 2006.182.08:16:41.85#ibcon#wrote, iclass 33, count 0 2006.182.08:16:41.85#ibcon#about to read 3, iclass 33, count 0 2006.182.08:16:41.88#ibcon#read 3, iclass 33, count 0 2006.182.08:16:41.88#ibcon#about to read 4, iclass 33, count 0 2006.182.08:16:41.88#ibcon#read 4, iclass 33, count 0 2006.182.08:16:41.88#ibcon#about to read 5, iclass 33, count 0 2006.182.08:16:41.88#ibcon#read 5, iclass 33, count 0 2006.182.08:16:41.88#ibcon#about to read 6, iclass 33, count 0 2006.182.08:16:41.88#ibcon#read 6, iclass 33, count 0 2006.182.08:16:41.88#ibcon#end of sib2, iclass 33, count 0 2006.182.08:16:41.88#ibcon#*after write, iclass 33, count 0 2006.182.08:16:41.88#ibcon#*before return 0, iclass 33, count 0 2006.182.08:16:41.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:41.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:16:41.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:16:41.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:16:41.88$vc4f8/vblo=5,744.99 2006.182.08:16:41.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.182.08:16:41.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.182.08:16:41.88#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:41.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:41.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:41.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:41.88#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:16:41.88#ibcon#first serial, iclass 35, count 0 2006.182.08:16:41.88#ibcon#enter sib2, iclass 35, count 0 2006.182.08:16:41.88#ibcon#flushed, iclass 35, count 0 2006.182.08:16:41.88#ibcon#about to write, iclass 35, count 0 2006.182.08:16:41.88#ibcon#wrote, iclass 35, count 0 2006.182.08:16:41.88#ibcon#about to read 3, iclass 35, count 0 2006.182.08:16:41.90#ibcon#read 3, iclass 35, count 0 2006.182.08:16:41.90#ibcon#about to read 4, iclass 35, count 0 2006.182.08:16:41.90#ibcon#read 4, iclass 35, count 0 2006.182.08:16:41.90#ibcon#about to read 5, iclass 35, count 0 2006.182.08:16:41.90#ibcon#read 5, iclass 35, count 0 2006.182.08:16:41.90#ibcon#about to read 6, iclass 35, count 0 2006.182.08:16:41.90#ibcon#read 6, iclass 35, count 0 2006.182.08:16:41.90#ibcon#end of sib2, iclass 35, count 0 2006.182.08:16:41.90#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:16:41.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:16:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:16:41.90#ibcon#*before write, iclass 35, count 0 2006.182.08:16:41.90#ibcon#enter sib2, iclass 35, count 0 2006.182.08:16:41.90#ibcon#flushed, iclass 35, count 0 2006.182.08:16:41.90#ibcon#about to write, iclass 35, count 0 2006.182.08:16:41.90#ibcon#wrote, iclass 35, count 0 2006.182.08:16:41.90#ibcon#about to read 3, iclass 35, count 0 2006.182.08:16:41.94#ibcon#read 3, iclass 35, count 0 2006.182.08:16:41.94#ibcon#about to read 4, iclass 35, count 0 2006.182.08:16:41.94#ibcon#read 4, iclass 35, count 0 2006.182.08:16:41.94#ibcon#about to read 5, iclass 35, count 0 2006.182.08:16:41.94#ibcon#read 5, iclass 35, count 0 2006.182.08:16:41.94#ibcon#about to read 6, iclass 35, count 0 2006.182.08:16:41.94#ibcon#read 6, iclass 35, count 0 2006.182.08:16:41.94#ibcon#end of sib2, iclass 35, count 0 2006.182.08:16:41.94#ibcon#*after write, iclass 35, count 0 2006.182.08:16:41.94#ibcon#*before return 0, iclass 35, count 0 2006.182.08:16:41.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:41.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.182.08:16:41.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:16:41.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:16:41.94$vc4f8/vb=5,4 2006.182.08:16:41.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.182.08:16:41.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.182.08:16:41.94#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:41.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:42.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:42.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:42.00#ibcon#enter wrdev, iclass 37, count 2 2006.182.08:16:42.00#ibcon#first serial, iclass 37, count 2 2006.182.08:16:42.00#ibcon#enter sib2, iclass 37, count 2 2006.182.08:16:42.00#ibcon#flushed, iclass 37, count 2 2006.182.08:16:42.00#ibcon#about to write, iclass 37, count 2 2006.182.08:16:42.00#ibcon#wrote, iclass 37, count 2 2006.182.08:16:42.00#ibcon#about to read 3, iclass 37, count 2 2006.182.08:16:42.02#ibcon#read 3, iclass 37, count 2 2006.182.08:16:42.02#ibcon#about to read 4, iclass 37, count 2 2006.182.08:16:42.02#ibcon#read 4, iclass 37, count 2 2006.182.08:16:42.02#ibcon#about to read 5, iclass 37, count 2 2006.182.08:16:42.02#ibcon#read 5, iclass 37, count 2 2006.182.08:16:42.02#ibcon#about to read 6, iclass 37, count 2 2006.182.08:16:42.02#ibcon#read 6, iclass 37, count 2 2006.182.08:16:42.02#ibcon#end of sib2, iclass 37, count 2 2006.182.08:16:42.02#ibcon#*mode == 0, iclass 37, count 2 2006.182.08:16:42.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.182.08:16:42.02#ibcon#[27=AT05-04\r\n] 2006.182.08:16:42.02#ibcon#*before write, iclass 37, count 2 2006.182.08:16:42.02#ibcon#enter sib2, iclass 37, count 2 2006.182.08:16:42.02#ibcon#flushed, iclass 37, count 2 2006.182.08:16:42.02#ibcon#about to write, iclass 37, count 2 2006.182.08:16:42.02#ibcon#wrote, iclass 37, count 2 2006.182.08:16:42.02#ibcon#about to read 3, iclass 37, count 2 2006.182.08:16:42.05#ibcon#read 3, iclass 37, count 2 2006.182.08:16:42.05#ibcon#about to read 4, iclass 37, count 2 2006.182.08:16:42.05#ibcon#read 4, iclass 37, count 2 2006.182.08:16:42.05#ibcon#about to read 5, iclass 37, count 2 2006.182.08:16:42.05#ibcon#read 5, iclass 37, count 2 2006.182.08:16:42.05#ibcon#about to read 6, iclass 37, count 2 2006.182.08:16:42.05#ibcon#read 6, iclass 37, count 2 2006.182.08:16:42.05#ibcon#end of sib2, iclass 37, count 2 2006.182.08:16:42.05#ibcon#*after write, iclass 37, count 2 2006.182.08:16:42.05#ibcon#*before return 0, iclass 37, count 2 2006.182.08:16:42.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:42.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.182.08:16:42.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.182.08:16:42.05#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:42.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:42.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:42.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:42.17#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:16:42.17#ibcon#first serial, iclass 37, count 0 2006.182.08:16:42.17#ibcon#enter sib2, iclass 37, count 0 2006.182.08:16:42.17#ibcon#flushed, iclass 37, count 0 2006.182.08:16:42.17#ibcon#about to write, iclass 37, count 0 2006.182.08:16:42.17#ibcon#wrote, iclass 37, count 0 2006.182.08:16:42.17#ibcon#about to read 3, iclass 37, count 0 2006.182.08:16:42.19#ibcon#read 3, iclass 37, count 0 2006.182.08:16:42.19#ibcon#about to read 4, iclass 37, count 0 2006.182.08:16:42.19#ibcon#read 4, iclass 37, count 0 2006.182.08:16:42.19#ibcon#about to read 5, iclass 37, count 0 2006.182.08:16:42.19#ibcon#read 5, iclass 37, count 0 2006.182.08:16:42.19#ibcon#about to read 6, iclass 37, count 0 2006.182.08:16:42.19#ibcon#read 6, iclass 37, count 0 2006.182.08:16:42.19#ibcon#end of sib2, iclass 37, count 0 2006.182.08:16:42.19#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:16:42.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:16:42.19#ibcon#[27=USB\r\n] 2006.182.08:16:42.19#ibcon#*before write, iclass 37, count 0 2006.182.08:16:42.19#ibcon#enter sib2, iclass 37, count 0 2006.182.08:16:42.19#ibcon#flushed, iclass 37, count 0 2006.182.08:16:42.19#ibcon#about to write, iclass 37, count 0 2006.182.08:16:42.19#ibcon#wrote, iclass 37, count 0 2006.182.08:16:42.19#ibcon#about to read 3, iclass 37, count 0 2006.182.08:16:42.22#ibcon#read 3, iclass 37, count 0 2006.182.08:16:42.22#ibcon#about to read 4, iclass 37, count 0 2006.182.08:16:42.22#ibcon#read 4, iclass 37, count 0 2006.182.08:16:42.22#ibcon#about to read 5, iclass 37, count 0 2006.182.08:16:42.22#ibcon#read 5, iclass 37, count 0 2006.182.08:16:42.22#ibcon#about to read 6, iclass 37, count 0 2006.182.08:16:42.22#ibcon#read 6, iclass 37, count 0 2006.182.08:16:42.22#ibcon#end of sib2, iclass 37, count 0 2006.182.08:16:42.22#ibcon#*after write, iclass 37, count 0 2006.182.08:16:42.22#ibcon#*before return 0, iclass 37, count 0 2006.182.08:16:42.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:42.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.182.08:16:42.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:16:42.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:16:42.22$vc4f8/vblo=6,752.99 2006.182.08:16:42.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.08:16:42.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.08:16:42.22#ibcon#ireg 17 cls_cnt 0 2006.182.08:16:42.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:42.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:42.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:42.22#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:16:42.22#ibcon#first serial, iclass 39, count 0 2006.182.08:16:42.22#ibcon#enter sib2, iclass 39, count 0 2006.182.08:16:42.22#ibcon#flushed, iclass 39, count 0 2006.182.08:16:42.22#ibcon#about to write, iclass 39, count 0 2006.182.08:16:42.22#ibcon#wrote, iclass 39, count 0 2006.182.08:16:42.22#ibcon#about to read 3, iclass 39, count 0 2006.182.08:16:42.24#ibcon#read 3, iclass 39, count 0 2006.182.08:16:42.24#ibcon#about to read 4, iclass 39, count 0 2006.182.08:16:42.24#ibcon#read 4, iclass 39, count 0 2006.182.08:16:42.24#ibcon#about to read 5, iclass 39, count 0 2006.182.08:16:42.24#ibcon#read 5, iclass 39, count 0 2006.182.08:16:42.24#ibcon#about to read 6, iclass 39, count 0 2006.182.08:16:42.24#ibcon#read 6, iclass 39, count 0 2006.182.08:16:42.24#ibcon#end of sib2, iclass 39, count 0 2006.182.08:16:42.24#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:16:42.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:16:42.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:16:42.24#ibcon#*before write, iclass 39, count 0 2006.182.08:16:42.24#ibcon#enter sib2, iclass 39, count 0 2006.182.08:16:42.24#ibcon#flushed, iclass 39, count 0 2006.182.08:16:42.24#ibcon#about to write, iclass 39, count 0 2006.182.08:16:42.24#ibcon#wrote, iclass 39, count 0 2006.182.08:16:42.24#ibcon#about to read 3, iclass 39, count 0 2006.182.08:16:42.28#ibcon#read 3, iclass 39, count 0 2006.182.08:16:42.28#ibcon#about to read 4, iclass 39, count 0 2006.182.08:16:42.28#ibcon#read 4, iclass 39, count 0 2006.182.08:16:42.28#ibcon#about to read 5, iclass 39, count 0 2006.182.08:16:42.28#ibcon#read 5, iclass 39, count 0 2006.182.08:16:42.28#ibcon#about to read 6, iclass 39, count 0 2006.182.08:16:42.28#ibcon#read 6, iclass 39, count 0 2006.182.08:16:42.28#ibcon#end of sib2, iclass 39, count 0 2006.182.08:16:42.28#ibcon#*after write, iclass 39, count 0 2006.182.08:16:42.28#ibcon#*before return 0, iclass 39, count 0 2006.182.08:16:42.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:42.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:16:42.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:16:42.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:16:42.28$vc4f8/vb=6,4 2006.182.08:16:42.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.08:16:42.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.08:16:42.28#ibcon#ireg 11 cls_cnt 2 2006.182.08:16:42.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:42.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:42.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:42.34#ibcon#enter wrdev, iclass 3, count 2 2006.182.08:16:42.34#ibcon#first serial, iclass 3, count 2 2006.182.08:16:42.34#ibcon#enter sib2, iclass 3, count 2 2006.182.08:16:42.34#ibcon#flushed, iclass 3, count 2 2006.182.08:16:42.34#ibcon#about to write, iclass 3, count 2 2006.182.08:16:42.34#ibcon#wrote, iclass 3, count 2 2006.182.08:16:42.34#ibcon#about to read 3, iclass 3, count 2 2006.182.08:16:42.36#ibcon#read 3, iclass 3, count 2 2006.182.08:16:42.36#ibcon#about to read 4, iclass 3, count 2 2006.182.08:16:42.36#ibcon#read 4, iclass 3, count 2 2006.182.08:16:42.36#ibcon#about to read 5, iclass 3, count 2 2006.182.08:16:42.36#ibcon#read 5, iclass 3, count 2 2006.182.08:16:42.36#ibcon#about to read 6, iclass 3, count 2 2006.182.08:16:42.36#ibcon#read 6, iclass 3, count 2 2006.182.08:16:42.36#ibcon#end of sib2, iclass 3, count 2 2006.182.08:16:42.36#ibcon#*mode == 0, iclass 3, count 2 2006.182.08:16:42.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.08:16:42.36#ibcon#[27=AT06-04\r\n] 2006.182.08:16:42.36#ibcon#*before write, iclass 3, count 2 2006.182.08:16:42.36#ibcon#enter sib2, iclass 3, count 2 2006.182.08:16:42.36#ibcon#flushed, iclass 3, count 2 2006.182.08:16:42.36#ibcon#about to write, iclass 3, count 2 2006.182.08:16:42.36#ibcon#wrote, iclass 3, count 2 2006.182.08:16:42.36#ibcon#about to read 3, iclass 3, count 2 2006.182.08:16:42.39#ibcon#read 3, iclass 3, count 2 2006.182.08:16:42.39#ibcon#about to read 4, iclass 3, count 2 2006.182.08:16:42.39#ibcon#read 4, iclass 3, count 2 2006.182.08:16:42.39#ibcon#about to read 5, iclass 3, count 2 2006.182.08:16:42.39#ibcon#read 5, iclass 3, count 2 2006.182.08:16:42.39#ibcon#about to read 6, iclass 3, count 2 2006.182.08:16:42.39#ibcon#read 6, iclass 3, count 2 2006.182.08:16:42.39#ibcon#end of sib2, iclass 3, count 2 2006.182.08:16:42.39#ibcon#*after write, iclass 3, count 2 2006.182.08:16:42.39#ibcon#*before return 0, iclass 3, count 2 2006.182.08:16:42.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:42.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:16:42.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.08:16:42.39#ibcon#ireg 7 cls_cnt 0 2006.182.08:16:42.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:42.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:42.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:42.51#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:16:42.51#ibcon#first serial, iclass 3, count 0 2006.182.08:16:42.51#ibcon#enter sib2, iclass 3, count 0 2006.182.08:16:42.51#ibcon#flushed, iclass 3, count 0 2006.182.08:16:42.51#ibcon#about to write, iclass 3, count 0 2006.182.08:16:42.51#ibcon#wrote, iclass 3, count 0 2006.182.08:16:42.51#ibcon#about to read 3, iclass 3, count 0 2006.182.08:16:42.53#ibcon#read 3, iclass 3, count 0 2006.182.08:16:42.53#ibcon#about to read 4, iclass 3, count 0 2006.182.08:16:42.53#ibcon#read 4, iclass 3, count 0 2006.182.08:16:42.53#ibcon#about to read 5, iclass 3, count 0 2006.182.08:16:42.53#ibcon#read 5, iclass 3, count 0 2006.182.08:16:42.53#ibcon#about to read 6, iclass 3, count 0 2006.182.08:16:42.53#ibcon#read 6, iclass 3, count 0 2006.182.08:16:42.53#ibcon#end of sib2, iclass 3, count 0 2006.182.08:16:42.53#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:16:42.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:16:42.53#ibcon#[27=USB\r\n] 2006.182.08:16:42.53#ibcon#*before write, iclass 3, count 0 2006.182.08:16:42.53#ibcon#enter sib2, iclass 3, count 0 2006.182.08:16:42.53#ibcon#flushed, iclass 3, count 0 2006.182.08:16:42.53#ibcon#about to write, iclass 3, count 0 2006.182.08:16:42.53#ibcon#wrote, iclass 3, count 0 2006.182.08:16:42.53#ibcon#about to read 3, iclass 3, count 0 2006.182.08:16:42.56#ibcon#read 3, iclass 3, count 0 2006.182.08:16:42.56#ibcon#about to read 4, iclass 3, count 0 2006.182.08:16:42.56#ibcon#read 4, iclass 3, count 0 2006.182.08:16:42.56#ibcon#about to read 5, iclass 3, count 0 2006.182.08:16:42.56#ibcon#read 5, iclass 3, count 0 2006.182.08:16:42.56#ibcon#about to read 6, iclass 3, count 0 2006.182.08:16:42.56#ibcon#read 6, iclass 3, count 0 2006.182.08:16:42.56#ibcon#end of sib2, iclass 3, count 0 2006.182.08:16:42.56#ibcon#*after write, iclass 3, count 0 2006.182.08:16:42.56#ibcon#*before return 0, iclass 3, count 0 2006.182.08:16:42.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:42.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:16:42.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:16:42.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:16:42.56$vc4f8/vabw=wide 2006.182.08:16:42.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.08:16:42.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.08:16:42.56#ibcon#ireg 8 cls_cnt 0 2006.182.08:16:42.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:16:42.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:16:42.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:16:42.56#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:16:42.56#ibcon#first serial, iclass 5, count 0 2006.182.08:16:42.56#ibcon#enter sib2, iclass 5, count 0 2006.182.08:16:42.56#ibcon#flushed, iclass 5, count 0 2006.182.08:16:42.56#ibcon#about to write, iclass 5, count 0 2006.182.08:16:42.56#ibcon#wrote, iclass 5, count 0 2006.182.08:16:42.56#ibcon#about to read 3, iclass 5, count 0 2006.182.08:16:42.58#ibcon#read 3, iclass 5, count 0 2006.182.08:16:42.58#ibcon#about to read 4, iclass 5, count 0 2006.182.08:16:42.58#ibcon#read 4, iclass 5, count 0 2006.182.08:16:42.58#ibcon#about to read 5, iclass 5, count 0 2006.182.08:16:42.58#ibcon#read 5, iclass 5, count 0 2006.182.08:16:42.58#ibcon#about to read 6, iclass 5, count 0 2006.182.08:16:42.58#ibcon#read 6, iclass 5, count 0 2006.182.08:16:42.58#ibcon#end of sib2, iclass 5, count 0 2006.182.08:16:42.58#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:16:42.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:16:42.58#ibcon#[25=BW32\r\n] 2006.182.08:16:42.58#ibcon#*before write, iclass 5, count 0 2006.182.08:16:42.58#ibcon#enter sib2, iclass 5, count 0 2006.182.08:16:42.58#ibcon#flushed, iclass 5, count 0 2006.182.08:16:42.58#ibcon#about to write, iclass 5, count 0 2006.182.08:16:42.58#ibcon#wrote, iclass 5, count 0 2006.182.08:16:42.58#ibcon#about to read 3, iclass 5, count 0 2006.182.08:16:42.61#ibcon#read 3, iclass 5, count 0 2006.182.08:16:42.61#ibcon#about to read 4, iclass 5, count 0 2006.182.08:16:42.61#ibcon#read 4, iclass 5, count 0 2006.182.08:16:42.61#ibcon#about to read 5, iclass 5, count 0 2006.182.08:16:42.61#ibcon#read 5, iclass 5, count 0 2006.182.08:16:42.61#ibcon#about to read 6, iclass 5, count 0 2006.182.08:16:42.61#ibcon#read 6, iclass 5, count 0 2006.182.08:16:42.61#ibcon#end of sib2, iclass 5, count 0 2006.182.08:16:42.61#ibcon#*after write, iclass 5, count 0 2006.182.08:16:42.61#ibcon#*before return 0, iclass 5, count 0 2006.182.08:16:42.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:16:42.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:16:42.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:16:42.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:16:42.61$vc4f8/vbbw=wide 2006.182.08:16:42.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.08:16:42.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.08:16:42.61#ibcon#ireg 8 cls_cnt 0 2006.182.08:16:42.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:16:42.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:16:42.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:16:42.68#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:16:42.68#ibcon#first serial, iclass 7, count 0 2006.182.08:16:42.68#ibcon#enter sib2, iclass 7, count 0 2006.182.08:16:42.68#ibcon#flushed, iclass 7, count 0 2006.182.08:16:42.68#ibcon#about to write, iclass 7, count 0 2006.182.08:16:42.68#ibcon#wrote, iclass 7, count 0 2006.182.08:16:42.68#ibcon#about to read 3, iclass 7, count 0 2006.182.08:16:42.70#ibcon#read 3, iclass 7, count 0 2006.182.08:16:42.70#ibcon#about to read 4, iclass 7, count 0 2006.182.08:16:42.70#ibcon#read 4, iclass 7, count 0 2006.182.08:16:42.70#ibcon#about to read 5, iclass 7, count 0 2006.182.08:16:42.70#ibcon#read 5, iclass 7, count 0 2006.182.08:16:42.70#ibcon#about to read 6, iclass 7, count 0 2006.182.08:16:42.70#ibcon#read 6, iclass 7, count 0 2006.182.08:16:42.70#ibcon#end of sib2, iclass 7, count 0 2006.182.08:16:42.70#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:16:42.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:16:42.70#ibcon#[27=BW32\r\n] 2006.182.08:16:42.70#ibcon#*before write, iclass 7, count 0 2006.182.08:16:42.70#ibcon#enter sib2, iclass 7, count 0 2006.182.08:16:42.70#ibcon#flushed, iclass 7, count 0 2006.182.08:16:42.70#ibcon#about to write, iclass 7, count 0 2006.182.08:16:42.70#ibcon#wrote, iclass 7, count 0 2006.182.08:16:42.70#ibcon#about to read 3, iclass 7, count 0 2006.182.08:16:42.73#ibcon#read 3, iclass 7, count 0 2006.182.08:16:42.73#ibcon#about to read 4, iclass 7, count 0 2006.182.08:16:42.73#ibcon#read 4, iclass 7, count 0 2006.182.08:16:42.73#ibcon#about to read 5, iclass 7, count 0 2006.182.08:16:42.73#ibcon#read 5, iclass 7, count 0 2006.182.08:16:42.73#ibcon#about to read 6, iclass 7, count 0 2006.182.08:16:42.73#ibcon#read 6, iclass 7, count 0 2006.182.08:16:42.73#ibcon#end of sib2, iclass 7, count 0 2006.182.08:16:42.73#ibcon#*after write, iclass 7, count 0 2006.182.08:16:42.73#ibcon#*before return 0, iclass 7, count 0 2006.182.08:16:42.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:16:42.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:16:42.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:16:42.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:16:42.73$4f8m12a/ifd4f 2006.182.08:16:42.73$ifd4f/lo= 2006.182.08:16:42.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:16:42.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:16:42.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:16:42.73$ifd4f/patch= 2006.182.08:16:42.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:16:42.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:16:42.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:16:42.73$4f8m12a/"form=m,16.000,1:2 2006.182.08:16:42.73$4f8m12a/"tpicd 2006.182.08:16:42.73$4f8m12a/echo=off 2006.182.08:16:42.73$4f8m12a/xlog=off 2006.182.08:16:42.73:!2006.182.08:17:10 2006.182.08:16:53.14#trakl#Source acquired 2006.182.08:16:55.14#flagr#flagr/antenna,acquired 2006.182.08:17:10.00:preob 2006.182.08:17:11.14/onsource/TRACKING 2006.182.08:17:11.14:!2006.182.08:17:20 2006.182.08:17:20.00:data_valid=on 2006.182.08:17:20.00:midob 2006.182.08:17:20.14/onsource/TRACKING 2006.182.08:17:20.14/wx/27.80,1002.9,82 2006.182.08:17:20.22/cable/+6.4625E-03 2006.182.08:17:21.31/va/01,08,usb,yes,28,30 2006.182.08:17:21.31/va/02,07,usb,yes,28,30 2006.182.08:17:21.31/va/03,06,usb,yes,30,30 2006.182.08:17:21.31/va/04,07,usb,yes,29,31 2006.182.08:17:21.31/va/05,07,usb,yes,30,32 2006.182.08:17:21.31/va/06,06,usb,yes,29,29 2006.182.08:17:21.31/va/07,06,usb,yes,30,29 2006.182.08:17:21.31/va/08,07,usb,yes,28,27 2006.182.08:17:21.54/valo/01,532.99,yes,locked 2006.182.08:17:21.54/valo/02,572.99,yes,locked 2006.182.08:17:21.54/valo/03,672.99,yes,locked 2006.182.08:17:21.54/valo/04,832.99,yes,locked 2006.182.08:17:21.54/valo/05,652.99,yes,locked 2006.182.08:17:21.54/valo/06,772.99,yes,locked 2006.182.08:17:21.54/valo/07,832.99,yes,locked 2006.182.08:17:21.54/valo/08,852.99,yes,locked 2006.182.08:17:22.63/vb/01,04,usb,yes,29,27 2006.182.08:17:22.63/vb/02,04,usb,yes,30,32 2006.182.08:17:22.63/vb/03,04,usb,yes,27,30 2006.182.08:17:22.63/vb/04,04,usb,yes,28,28 2006.182.08:17:22.63/vb/05,04,usb,yes,26,30 2006.182.08:17:22.63/vb/06,04,usb,yes,27,30 2006.182.08:17:22.63/vb/07,04,usb,yes,29,29 2006.182.08:17:22.63/vb/08,04,usb,yes,27,30 2006.182.08:17:22.86/vblo/01,632.99,yes,locked 2006.182.08:17:22.86/vblo/02,640.99,yes,locked 2006.182.08:17:22.86/vblo/03,656.99,yes,locked 2006.182.08:17:22.86/vblo/04,712.99,yes,locked 2006.182.08:17:22.86/vblo/05,744.99,yes,locked 2006.182.08:17:22.86/vblo/06,752.99,yes,locked 2006.182.08:17:22.86/vblo/07,734.99,yes,locked 2006.182.08:17:22.86/vblo/08,744.99,yes,locked 2006.182.08:17:23.01/vabw/8 2006.182.08:17:23.16/vbbw/8 2006.182.08:17:23.25/xfe/off,on,14.7 2006.182.08:17:23.64/ifatt/23,28,28,28 2006.182.08:17:24.08/fmout-gps/S +3.49E-07 2006.182.08:17:24.12:!2006.182.08:18:20 2006.182.08:18:20.00:data_valid=off 2006.182.08:18:20.00:postob 2006.182.08:18:20.17/cable/+6.4618E-03 2006.182.08:18:20.17/wx/27.79,1002.9,81 2006.182.08:18:21.08/fmout-gps/S +3.50E-07 2006.182.08:18:21.08:scan_name=182-0820,k06182,60 2006.182.08:18:21.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.182.08:18:21.14#flagr#flagr/antenna,new-source 2006.182.08:18:22.14:checkk5 2006.182.08:18:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:18:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:18:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:18:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:18:24.01/chk_obsdata//k5ts1/T1820817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:18:24.38/chk_obsdata//k5ts2/T1820817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:18:24.74/chk_obsdata//k5ts3/T1820817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:18:25.11/chk_obsdata//k5ts4/T1820817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:18:25.81/k5log//k5ts1_log_newline 2006.182.08:18:26.50/k5log//k5ts2_log_newline 2006.182.08:18:27.18/k5log//k5ts3_log_newline 2006.182.08:18:27.87/k5log//k5ts4_log_newline 2006.182.08:18:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:18:27.89:4f8m12a=3 2006.182.08:18:27.90$4f8m12a/echo=on 2006.182.08:18:27.90$4f8m12a/pcalon 2006.182.08:18:27.90$pcalon/"no phase cal control is implemented here 2006.182.08:18:27.90$4f8m12a/"tpicd=stop 2006.182.08:18:27.90$4f8m12a/vc4f8 2006.182.08:18:27.90$vc4f8/valo=1,532.99 2006.182.08:18:27.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.08:18:27.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.08:18:27.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:27.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:27.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:27.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:27.90#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:18:27.90#ibcon#first serial, iclass 16, count 0 2006.182.08:18:27.90#ibcon#enter sib2, iclass 16, count 0 2006.182.08:18:27.90#ibcon#flushed, iclass 16, count 0 2006.182.08:18:27.90#ibcon#about to write, iclass 16, count 0 2006.182.08:18:27.90#ibcon#wrote, iclass 16, count 0 2006.182.08:18:27.90#ibcon#about to read 3, iclass 16, count 0 2006.182.08:18:27.94#ibcon#read 3, iclass 16, count 0 2006.182.08:18:27.94#ibcon#about to read 4, iclass 16, count 0 2006.182.08:18:27.94#ibcon#read 4, iclass 16, count 0 2006.182.08:18:27.94#ibcon#about to read 5, iclass 16, count 0 2006.182.08:18:27.94#ibcon#read 5, iclass 16, count 0 2006.182.08:18:27.94#ibcon#about to read 6, iclass 16, count 0 2006.182.08:18:27.94#ibcon#read 6, iclass 16, count 0 2006.182.08:18:27.94#ibcon#end of sib2, iclass 16, count 0 2006.182.08:18:27.94#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:18:27.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:18:27.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:18:27.94#ibcon#*before write, iclass 16, count 0 2006.182.08:18:27.94#ibcon#enter sib2, iclass 16, count 0 2006.182.08:18:27.94#ibcon#flushed, iclass 16, count 0 2006.182.08:18:27.94#ibcon#about to write, iclass 16, count 0 2006.182.08:18:27.94#ibcon#wrote, iclass 16, count 0 2006.182.08:18:27.94#ibcon#about to read 3, iclass 16, count 0 2006.182.08:18:27.99#ibcon#read 3, iclass 16, count 0 2006.182.08:18:27.99#ibcon#about to read 4, iclass 16, count 0 2006.182.08:18:27.99#ibcon#read 4, iclass 16, count 0 2006.182.08:18:27.99#ibcon#about to read 5, iclass 16, count 0 2006.182.08:18:27.99#ibcon#read 5, iclass 16, count 0 2006.182.08:18:27.99#ibcon#about to read 6, iclass 16, count 0 2006.182.08:18:27.99#ibcon#read 6, iclass 16, count 0 2006.182.08:18:27.99#ibcon#end of sib2, iclass 16, count 0 2006.182.08:18:27.99#ibcon#*after write, iclass 16, count 0 2006.182.08:18:27.99#ibcon#*before return 0, iclass 16, count 0 2006.182.08:18:27.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:27.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:27.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:18:27.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:18:27.99$vc4f8/va=1,8 2006.182.08:18:27.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.08:18:27.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.08:18:27.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:27.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:27.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:27.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:27.99#ibcon#enter wrdev, iclass 18, count 2 2006.182.08:18:27.99#ibcon#first serial, iclass 18, count 2 2006.182.08:18:27.99#ibcon#enter sib2, iclass 18, count 2 2006.182.08:18:27.99#ibcon#flushed, iclass 18, count 2 2006.182.08:18:27.99#ibcon#about to write, iclass 18, count 2 2006.182.08:18:27.99#ibcon#wrote, iclass 18, count 2 2006.182.08:18:27.99#ibcon#about to read 3, iclass 18, count 2 2006.182.08:18:28.02#ibcon#read 3, iclass 18, count 2 2006.182.08:18:28.02#ibcon#about to read 4, iclass 18, count 2 2006.182.08:18:28.02#ibcon#read 4, iclass 18, count 2 2006.182.08:18:28.02#ibcon#about to read 5, iclass 18, count 2 2006.182.08:18:28.02#ibcon#read 5, iclass 18, count 2 2006.182.08:18:28.02#ibcon#about to read 6, iclass 18, count 2 2006.182.08:18:28.02#ibcon#read 6, iclass 18, count 2 2006.182.08:18:28.02#ibcon#end of sib2, iclass 18, count 2 2006.182.08:18:28.02#ibcon#*mode == 0, iclass 18, count 2 2006.182.08:18:28.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.08:18:28.02#ibcon#[25=AT01-08\r\n] 2006.182.08:18:28.02#ibcon#*before write, iclass 18, count 2 2006.182.08:18:28.02#ibcon#enter sib2, iclass 18, count 2 2006.182.08:18:28.02#ibcon#flushed, iclass 18, count 2 2006.182.08:18:28.02#ibcon#about to write, iclass 18, count 2 2006.182.08:18:28.02#ibcon#wrote, iclass 18, count 2 2006.182.08:18:28.02#ibcon#about to read 3, iclass 18, count 2 2006.182.08:18:28.05#ibcon#read 3, iclass 18, count 2 2006.182.08:18:28.05#ibcon#about to read 4, iclass 18, count 2 2006.182.08:18:28.05#ibcon#read 4, iclass 18, count 2 2006.182.08:18:28.05#ibcon#about to read 5, iclass 18, count 2 2006.182.08:18:28.05#ibcon#read 5, iclass 18, count 2 2006.182.08:18:28.05#ibcon#about to read 6, iclass 18, count 2 2006.182.08:18:28.05#ibcon#read 6, iclass 18, count 2 2006.182.08:18:28.05#ibcon#end of sib2, iclass 18, count 2 2006.182.08:18:28.05#ibcon#*after write, iclass 18, count 2 2006.182.08:18:28.05#ibcon#*before return 0, iclass 18, count 2 2006.182.08:18:28.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:28.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:28.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.08:18:28.05#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:28.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:28.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:28.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:28.17#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:18:28.17#ibcon#first serial, iclass 18, count 0 2006.182.08:18:28.17#ibcon#enter sib2, iclass 18, count 0 2006.182.08:18:28.17#ibcon#flushed, iclass 18, count 0 2006.182.08:18:28.17#ibcon#about to write, iclass 18, count 0 2006.182.08:18:28.17#ibcon#wrote, iclass 18, count 0 2006.182.08:18:28.17#ibcon#about to read 3, iclass 18, count 0 2006.182.08:18:28.19#ibcon#read 3, iclass 18, count 0 2006.182.08:18:28.19#ibcon#about to read 4, iclass 18, count 0 2006.182.08:18:28.19#ibcon#read 4, iclass 18, count 0 2006.182.08:18:28.19#ibcon#about to read 5, iclass 18, count 0 2006.182.08:18:28.19#ibcon#read 5, iclass 18, count 0 2006.182.08:18:28.19#ibcon#about to read 6, iclass 18, count 0 2006.182.08:18:28.19#ibcon#read 6, iclass 18, count 0 2006.182.08:18:28.19#ibcon#end of sib2, iclass 18, count 0 2006.182.08:18:28.19#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:18:28.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:18:28.19#ibcon#[25=USB\r\n] 2006.182.08:18:28.19#ibcon#*before write, iclass 18, count 0 2006.182.08:18:28.19#ibcon#enter sib2, iclass 18, count 0 2006.182.08:18:28.19#ibcon#flushed, iclass 18, count 0 2006.182.08:18:28.19#ibcon#about to write, iclass 18, count 0 2006.182.08:18:28.19#ibcon#wrote, iclass 18, count 0 2006.182.08:18:28.19#ibcon#about to read 3, iclass 18, count 0 2006.182.08:18:28.22#ibcon#read 3, iclass 18, count 0 2006.182.08:18:28.22#ibcon#about to read 4, iclass 18, count 0 2006.182.08:18:28.22#ibcon#read 4, iclass 18, count 0 2006.182.08:18:28.22#ibcon#about to read 5, iclass 18, count 0 2006.182.08:18:28.22#ibcon#read 5, iclass 18, count 0 2006.182.08:18:28.22#ibcon#about to read 6, iclass 18, count 0 2006.182.08:18:28.22#ibcon#read 6, iclass 18, count 0 2006.182.08:18:28.22#ibcon#end of sib2, iclass 18, count 0 2006.182.08:18:28.22#ibcon#*after write, iclass 18, count 0 2006.182.08:18:28.22#ibcon#*before return 0, iclass 18, count 0 2006.182.08:18:28.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:28.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:28.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:18:28.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:18:28.22$vc4f8/valo=2,572.99 2006.182.08:18:28.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.08:18:28.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.08:18:28.22#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:28.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:28.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:28.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:28.22#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:18:28.22#ibcon#first serial, iclass 20, count 0 2006.182.08:18:28.22#ibcon#enter sib2, iclass 20, count 0 2006.182.08:18:28.22#ibcon#flushed, iclass 20, count 0 2006.182.08:18:28.22#ibcon#about to write, iclass 20, count 0 2006.182.08:18:28.22#ibcon#wrote, iclass 20, count 0 2006.182.08:18:28.22#ibcon#about to read 3, iclass 20, count 0 2006.182.08:18:28.24#ibcon#read 3, iclass 20, count 0 2006.182.08:18:28.24#ibcon#about to read 4, iclass 20, count 0 2006.182.08:18:28.24#ibcon#read 4, iclass 20, count 0 2006.182.08:18:28.24#ibcon#about to read 5, iclass 20, count 0 2006.182.08:18:28.24#ibcon#read 5, iclass 20, count 0 2006.182.08:18:28.24#ibcon#about to read 6, iclass 20, count 0 2006.182.08:18:28.24#ibcon#read 6, iclass 20, count 0 2006.182.08:18:28.24#ibcon#end of sib2, iclass 20, count 0 2006.182.08:18:28.24#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:18:28.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:18:28.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:18:28.24#ibcon#*before write, iclass 20, count 0 2006.182.08:18:28.24#ibcon#enter sib2, iclass 20, count 0 2006.182.08:18:28.24#ibcon#flushed, iclass 20, count 0 2006.182.08:18:28.24#ibcon#about to write, iclass 20, count 0 2006.182.08:18:28.24#ibcon#wrote, iclass 20, count 0 2006.182.08:18:28.24#ibcon#about to read 3, iclass 20, count 0 2006.182.08:18:28.28#ibcon#read 3, iclass 20, count 0 2006.182.08:18:28.28#ibcon#about to read 4, iclass 20, count 0 2006.182.08:18:28.28#ibcon#read 4, iclass 20, count 0 2006.182.08:18:28.28#ibcon#about to read 5, iclass 20, count 0 2006.182.08:18:28.28#ibcon#read 5, iclass 20, count 0 2006.182.08:18:28.28#ibcon#about to read 6, iclass 20, count 0 2006.182.08:18:28.28#ibcon#read 6, iclass 20, count 0 2006.182.08:18:28.28#ibcon#end of sib2, iclass 20, count 0 2006.182.08:18:28.28#ibcon#*after write, iclass 20, count 0 2006.182.08:18:28.28#ibcon#*before return 0, iclass 20, count 0 2006.182.08:18:28.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:28.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:28.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:18:28.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:18:28.28$vc4f8/va=2,7 2006.182.08:18:28.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.08:18:28.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.08:18:28.28#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:28.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:28.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:28.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:28.34#ibcon#enter wrdev, iclass 22, count 2 2006.182.08:18:28.34#ibcon#first serial, iclass 22, count 2 2006.182.08:18:28.34#ibcon#enter sib2, iclass 22, count 2 2006.182.08:18:28.34#ibcon#flushed, iclass 22, count 2 2006.182.08:18:28.34#ibcon#about to write, iclass 22, count 2 2006.182.08:18:28.34#ibcon#wrote, iclass 22, count 2 2006.182.08:18:28.34#ibcon#about to read 3, iclass 22, count 2 2006.182.08:18:28.36#ibcon#read 3, iclass 22, count 2 2006.182.08:18:28.36#ibcon#about to read 4, iclass 22, count 2 2006.182.08:18:28.36#ibcon#read 4, iclass 22, count 2 2006.182.08:18:28.36#ibcon#about to read 5, iclass 22, count 2 2006.182.08:18:28.36#ibcon#read 5, iclass 22, count 2 2006.182.08:18:28.36#ibcon#about to read 6, iclass 22, count 2 2006.182.08:18:28.36#ibcon#read 6, iclass 22, count 2 2006.182.08:18:28.36#ibcon#end of sib2, iclass 22, count 2 2006.182.08:18:28.36#ibcon#*mode == 0, iclass 22, count 2 2006.182.08:18:28.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.08:18:28.36#ibcon#[25=AT02-07\r\n] 2006.182.08:18:28.36#ibcon#*before write, iclass 22, count 2 2006.182.08:18:28.36#ibcon#enter sib2, iclass 22, count 2 2006.182.08:18:28.36#ibcon#flushed, iclass 22, count 2 2006.182.08:18:28.36#ibcon#about to write, iclass 22, count 2 2006.182.08:18:28.36#ibcon#wrote, iclass 22, count 2 2006.182.08:18:28.36#ibcon#about to read 3, iclass 22, count 2 2006.182.08:18:28.39#ibcon#read 3, iclass 22, count 2 2006.182.08:18:28.39#ibcon#about to read 4, iclass 22, count 2 2006.182.08:18:28.39#ibcon#read 4, iclass 22, count 2 2006.182.08:18:28.39#ibcon#about to read 5, iclass 22, count 2 2006.182.08:18:28.39#ibcon#read 5, iclass 22, count 2 2006.182.08:18:28.39#ibcon#about to read 6, iclass 22, count 2 2006.182.08:18:28.39#ibcon#read 6, iclass 22, count 2 2006.182.08:18:28.39#ibcon#end of sib2, iclass 22, count 2 2006.182.08:18:28.39#ibcon#*after write, iclass 22, count 2 2006.182.08:18:28.39#ibcon#*before return 0, iclass 22, count 2 2006.182.08:18:28.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:28.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:28.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.08:18:28.39#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:28.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:28.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:28.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:28.51#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:18:28.51#ibcon#first serial, iclass 22, count 0 2006.182.08:18:28.51#ibcon#enter sib2, iclass 22, count 0 2006.182.08:18:28.51#ibcon#flushed, iclass 22, count 0 2006.182.08:18:28.51#ibcon#about to write, iclass 22, count 0 2006.182.08:18:28.51#ibcon#wrote, iclass 22, count 0 2006.182.08:18:28.51#ibcon#about to read 3, iclass 22, count 0 2006.182.08:18:28.53#ibcon#read 3, iclass 22, count 0 2006.182.08:18:28.53#ibcon#about to read 4, iclass 22, count 0 2006.182.08:18:28.53#ibcon#read 4, iclass 22, count 0 2006.182.08:18:28.53#ibcon#about to read 5, iclass 22, count 0 2006.182.08:18:28.53#ibcon#read 5, iclass 22, count 0 2006.182.08:18:28.53#ibcon#about to read 6, iclass 22, count 0 2006.182.08:18:28.53#ibcon#read 6, iclass 22, count 0 2006.182.08:18:28.53#ibcon#end of sib2, iclass 22, count 0 2006.182.08:18:28.53#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:18:28.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:18:28.53#ibcon#[25=USB\r\n] 2006.182.08:18:28.53#ibcon#*before write, iclass 22, count 0 2006.182.08:18:28.53#ibcon#enter sib2, iclass 22, count 0 2006.182.08:18:28.53#ibcon#flushed, iclass 22, count 0 2006.182.08:18:28.53#ibcon#about to write, iclass 22, count 0 2006.182.08:18:28.53#ibcon#wrote, iclass 22, count 0 2006.182.08:18:28.53#ibcon#about to read 3, iclass 22, count 0 2006.182.08:18:28.56#ibcon#read 3, iclass 22, count 0 2006.182.08:18:28.56#ibcon#about to read 4, iclass 22, count 0 2006.182.08:18:28.56#ibcon#read 4, iclass 22, count 0 2006.182.08:18:28.56#ibcon#about to read 5, iclass 22, count 0 2006.182.08:18:28.56#ibcon#read 5, iclass 22, count 0 2006.182.08:18:28.56#ibcon#about to read 6, iclass 22, count 0 2006.182.08:18:28.56#ibcon#read 6, iclass 22, count 0 2006.182.08:18:28.56#ibcon#end of sib2, iclass 22, count 0 2006.182.08:18:28.56#ibcon#*after write, iclass 22, count 0 2006.182.08:18:28.56#ibcon#*before return 0, iclass 22, count 0 2006.182.08:18:28.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:28.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:28.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:18:28.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:18:28.56$vc4f8/valo=3,672.99 2006.182.08:18:28.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.08:18:28.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.08:18:28.56#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:28.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:28.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:28.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:28.56#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:18:28.56#ibcon#first serial, iclass 24, count 0 2006.182.08:18:28.56#ibcon#enter sib2, iclass 24, count 0 2006.182.08:18:28.56#ibcon#flushed, iclass 24, count 0 2006.182.08:18:28.56#ibcon#about to write, iclass 24, count 0 2006.182.08:18:28.56#ibcon#wrote, iclass 24, count 0 2006.182.08:18:28.56#ibcon#about to read 3, iclass 24, count 0 2006.182.08:18:28.59#ibcon#read 3, iclass 24, count 0 2006.182.08:18:28.59#ibcon#about to read 4, iclass 24, count 0 2006.182.08:18:28.59#ibcon#read 4, iclass 24, count 0 2006.182.08:18:28.59#ibcon#about to read 5, iclass 24, count 0 2006.182.08:18:28.59#ibcon#read 5, iclass 24, count 0 2006.182.08:18:28.59#ibcon#about to read 6, iclass 24, count 0 2006.182.08:18:28.59#ibcon#read 6, iclass 24, count 0 2006.182.08:18:28.59#ibcon#end of sib2, iclass 24, count 0 2006.182.08:18:28.59#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:18:28.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:18:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:18:28.59#ibcon#*before write, iclass 24, count 0 2006.182.08:18:28.59#ibcon#enter sib2, iclass 24, count 0 2006.182.08:18:28.59#ibcon#flushed, iclass 24, count 0 2006.182.08:18:28.59#ibcon#about to write, iclass 24, count 0 2006.182.08:18:28.59#ibcon#wrote, iclass 24, count 0 2006.182.08:18:28.59#ibcon#about to read 3, iclass 24, count 0 2006.182.08:18:28.63#ibcon#read 3, iclass 24, count 0 2006.182.08:18:28.63#ibcon#about to read 4, iclass 24, count 0 2006.182.08:18:28.63#ibcon#read 4, iclass 24, count 0 2006.182.08:18:28.63#ibcon#about to read 5, iclass 24, count 0 2006.182.08:18:28.63#ibcon#read 5, iclass 24, count 0 2006.182.08:18:28.63#ibcon#about to read 6, iclass 24, count 0 2006.182.08:18:28.63#ibcon#read 6, iclass 24, count 0 2006.182.08:18:28.63#ibcon#end of sib2, iclass 24, count 0 2006.182.08:18:28.63#ibcon#*after write, iclass 24, count 0 2006.182.08:18:28.63#ibcon#*before return 0, iclass 24, count 0 2006.182.08:18:28.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:28.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:28.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:18:28.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:18:28.63$vc4f8/va=3,6 2006.182.08:18:28.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.08:18:28.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.08:18:28.63#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:28.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:18:28.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:18:28.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:18:28.68#ibcon#enter wrdev, iclass 26, count 2 2006.182.08:18:28.68#ibcon#first serial, iclass 26, count 2 2006.182.08:18:28.68#ibcon#enter sib2, iclass 26, count 2 2006.182.08:18:28.68#ibcon#flushed, iclass 26, count 2 2006.182.08:18:28.68#ibcon#about to write, iclass 26, count 2 2006.182.08:18:28.68#ibcon#wrote, iclass 26, count 2 2006.182.08:18:28.68#ibcon#about to read 3, iclass 26, count 2 2006.182.08:18:28.70#ibcon#read 3, iclass 26, count 2 2006.182.08:18:28.70#ibcon#about to read 4, iclass 26, count 2 2006.182.08:18:28.70#ibcon#read 4, iclass 26, count 2 2006.182.08:18:28.70#ibcon#about to read 5, iclass 26, count 2 2006.182.08:18:28.70#ibcon#read 5, iclass 26, count 2 2006.182.08:18:28.70#ibcon#about to read 6, iclass 26, count 2 2006.182.08:18:28.70#ibcon#read 6, iclass 26, count 2 2006.182.08:18:28.70#ibcon#end of sib2, iclass 26, count 2 2006.182.08:18:28.70#ibcon#*mode == 0, iclass 26, count 2 2006.182.08:18:28.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.08:18:28.70#ibcon#[25=AT03-06\r\n] 2006.182.08:18:28.70#ibcon#*before write, iclass 26, count 2 2006.182.08:18:28.70#ibcon#enter sib2, iclass 26, count 2 2006.182.08:18:28.70#ibcon#flushed, iclass 26, count 2 2006.182.08:18:28.70#ibcon#about to write, iclass 26, count 2 2006.182.08:18:28.70#ibcon#wrote, iclass 26, count 2 2006.182.08:18:28.70#ibcon#about to read 3, iclass 26, count 2 2006.182.08:18:28.73#ibcon#read 3, iclass 26, count 2 2006.182.08:18:28.73#ibcon#about to read 4, iclass 26, count 2 2006.182.08:18:28.73#ibcon#read 4, iclass 26, count 2 2006.182.08:18:28.73#ibcon#about to read 5, iclass 26, count 2 2006.182.08:18:28.73#ibcon#read 5, iclass 26, count 2 2006.182.08:18:28.73#ibcon#about to read 6, iclass 26, count 2 2006.182.08:18:28.73#ibcon#read 6, iclass 26, count 2 2006.182.08:18:28.73#ibcon#end of sib2, iclass 26, count 2 2006.182.08:18:28.73#ibcon#*after write, iclass 26, count 2 2006.182.08:18:28.73#ibcon#*before return 0, iclass 26, count 2 2006.182.08:18:28.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:18:28.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:18:28.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.08:18:28.73#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:28.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:18:28.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:18:28.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:18:28.85#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:18:28.85#ibcon#first serial, iclass 26, count 0 2006.182.08:18:28.85#ibcon#enter sib2, iclass 26, count 0 2006.182.08:18:28.85#ibcon#flushed, iclass 26, count 0 2006.182.08:18:28.85#ibcon#about to write, iclass 26, count 0 2006.182.08:18:28.85#ibcon#wrote, iclass 26, count 0 2006.182.08:18:28.85#ibcon#about to read 3, iclass 26, count 0 2006.182.08:18:28.87#ibcon#read 3, iclass 26, count 0 2006.182.08:18:28.87#ibcon#about to read 4, iclass 26, count 0 2006.182.08:18:28.87#ibcon#read 4, iclass 26, count 0 2006.182.08:18:28.87#ibcon#about to read 5, iclass 26, count 0 2006.182.08:18:28.87#ibcon#read 5, iclass 26, count 0 2006.182.08:18:28.87#ibcon#about to read 6, iclass 26, count 0 2006.182.08:18:28.87#ibcon#read 6, iclass 26, count 0 2006.182.08:18:28.87#ibcon#end of sib2, iclass 26, count 0 2006.182.08:18:28.87#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:18:28.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:18:28.87#ibcon#[25=USB\r\n] 2006.182.08:18:28.87#ibcon#*before write, iclass 26, count 0 2006.182.08:18:28.87#ibcon#enter sib2, iclass 26, count 0 2006.182.08:18:28.87#ibcon#flushed, iclass 26, count 0 2006.182.08:18:28.87#ibcon#about to write, iclass 26, count 0 2006.182.08:18:28.87#ibcon#wrote, iclass 26, count 0 2006.182.08:18:28.87#ibcon#about to read 3, iclass 26, count 0 2006.182.08:18:28.90#ibcon#read 3, iclass 26, count 0 2006.182.08:18:28.90#ibcon#about to read 4, iclass 26, count 0 2006.182.08:18:28.90#ibcon#read 4, iclass 26, count 0 2006.182.08:18:28.90#ibcon#about to read 5, iclass 26, count 0 2006.182.08:18:28.90#ibcon#read 5, iclass 26, count 0 2006.182.08:18:28.90#ibcon#about to read 6, iclass 26, count 0 2006.182.08:18:28.90#ibcon#read 6, iclass 26, count 0 2006.182.08:18:28.90#ibcon#end of sib2, iclass 26, count 0 2006.182.08:18:28.90#ibcon#*after write, iclass 26, count 0 2006.182.08:18:28.90#ibcon#*before return 0, iclass 26, count 0 2006.182.08:18:28.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:18:28.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:18:28.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:18:28.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:18:28.90$vc4f8/valo=4,832.99 2006.182.08:18:28.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.08:18:28.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.08:18:28.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:28.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:18:28.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:18:28.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:18:28.90#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:18:28.90#ibcon#first serial, iclass 28, count 0 2006.182.08:18:28.90#ibcon#enter sib2, iclass 28, count 0 2006.182.08:18:28.90#ibcon#flushed, iclass 28, count 0 2006.182.08:18:28.90#ibcon#about to write, iclass 28, count 0 2006.182.08:18:28.90#ibcon#wrote, iclass 28, count 0 2006.182.08:18:28.90#ibcon#about to read 3, iclass 28, count 0 2006.182.08:18:28.92#ibcon#read 3, iclass 28, count 0 2006.182.08:18:28.92#ibcon#about to read 4, iclass 28, count 0 2006.182.08:18:28.92#ibcon#read 4, iclass 28, count 0 2006.182.08:18:28.92#ibcon#about to read 5, iclass 28, count 0 2006.182.08:18:28.92#ibcon#read 5, iclass 28, count 0 2006.182.08:18:28.92#ibcon#about to read 6, iclass 28, count 0 2006.182.08:18:28.92#ibcon#read 6, iclass 28, count 0 2006.182.08:18:28.92#ibcon#end of sib2, iclass 28, count 0 2006.182.08:18:28.92#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:18:28.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:18:28.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:18:28.92#ibcon#*before write, iclass 28, count 0 2006.182.08:18:28.92#ibcon#enter sib2, iclass 28, count 0 2006.182.08:18:28.92#ibcon#flushed, iclass 28, count 0 2006.182.08:18:28.92#ibcon#about to write, iclass 28, count 0 2006.182.08:18:28.92#ibcon#wrote, iclass 28, count 0 2006.182.08:18:28.92#ibcon#about to read 3, iclass 28, count 0 2006.182.08:18:28.96#ibcon#read 3, iclass 28, count 0 2006.182.08:18:28.96#ibcon#about to read 4, iclass 28, count 0 2006.182.08:18:28.96#ibcon#read 4, iclass 28, count 0 2006.182.08:18:28.96#ibcon#about to read 5, iclass 28, count 0 2006.182.08:18:28.96#ibcon#read 5, iclass 28, count 0 2006.182.08:18:28.96#ibcon#about to read 6, iclass 28, count 0 2006.182.08:18:28.96#ibcon#read 6, iclass 28, count 0 2006.182.08:18:28.96#ibcon#end of sib2, iclass 28, count 0 2006.182.08:18:28.96#ibcon#*after write, iclass 28, count 0 2006.182.08:18:28.96#ibcon#*before return 0, iclass 28, count 0 2006.182.08:18:28.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:18:28.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:18:28.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:18:28.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:18:28.96$vc4f8/va=4,7 2006.182.08:18:28.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.08:18:28.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.08:18:28.96#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:28.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:18:29.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:18:29.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:18:29.02#ibcon#enter wrdev, iclass 30, count 2 2006.182.08:18:29.02#ibcon#first serial, iclass 30, count 2 2006.182.08:18:29.02#ibcon#enter sib2, iclass 30, count 2 2006.182.08:18:29.02#ibcon#flushed, iclass 30, count 2 2006.182.08:18:29.02#ibcon#about to write, iclass 30, count 2 2006.182.08:18:29.02#ibcon#wrote, iclass 30, count 2 2006.182.08:18:29.02#ibcon#about to read 3, iclass 30, count 2 2006.182.08:18:29.04#ibcon#read 3, iclass 30, count 2 2006.182.08:18:29.04#ibcon#about to read 4, iclass 30, count 2 2006.182.08:18:29.04#ibcon#read 4, iclass 30, count 2 2006.182.08:18:29.04#ibcon#about to read 5, iclass 30, count 2 2006.182.08:18:29.04#ibcon#read 5, iclass 30, count 2 2006.182.08:18:29.04#ibcon#about to read 6, iclass 30, count 2 2006.182.08:18:29.04#ibcon#read 6, iclass 30, count 2 2006.182.08:18:29.04#ibcon#end of sib2, iclass 30, count 2 2006.182.08:18:29.04#ibcon#*mode == 0, iclass 30, count 2 2006.182.08:18:29.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.08:18:29.04#ibcon#[25=AT04-07\r\n] 2006.182.08:18:29.04#ibcon#*before write, iclass 30, count 2 2006.182.08:18:29.04#ibcon#enter sib2, iclass 30, count 2 2006.182.08:18:29.04#ibcon#flushed, iclass 30, count 2 2006.182.08:18:29.04#ibcon#about to write, iclass 30, count 2 2006.182.08:18:29.04#ibcon#wrote, iclass 30, count 2 2006.182.08:18:29.04#ibcon#about to read 3, iclass 30, count 2 2006.182.08:18:29.07#ibcon#read 3, iclass 30, count 2 2006.182.08:18:29.07#ibcon#about to read 4, iclass 30, count 2 2006.182.08:18:29.07#ibcon#read 4, iclass 30, count 2 2006.182.08:18:29.07#ibcon#about to read 5, iclass 30, count 2 2006.182.08:18:29.07#ibcon#read 5, iclass 30, count 2 2006.182.08:18:29.07#ibcon#about to read 6, iclass 30, count 2 2006.182.08:18:29.07#ibcon#read 6, iclass 30, count 2 2006.182.08:18:29.07#ibcon#end of sib2, iclass 30, count 2 2006.182.08:18:29.07#ibcon#*after write, iclass 30, count 2 2006.182.08:18:29.07#ibcon#*before return 0, iclass 30, count 2 2006.182.08:18:29.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:18:29.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:18:29.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.08:18:29.07#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:29.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:18:29.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:18:29.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:18:29.19#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:18:29.19#ibcon#first serial, iclass 30, count 0 2006.182.08:18:29.19#ibcon#enter sib2, iclass 30, count 0 2006.182.08:18:29.19#ibcon#flushed, iclass 30, count 0 2006.182.08:18:29.19#ibcon#about to write, iclass 30, count 0 2006.182.08:18:29.19#ibcon#wrote, iclass 30, count 0 2006.182.08:18:29.19#ibcon#about to read 3, iclass 30, count 0 2006.182.08:18:29.21#ibcon#read 3, iclass 30, count 0 2006.182.08:18:29.21#ibcon#about to read 4, iclass 30, count 0 2006.182.08:18:29.21#ibcon#read 4, iclass 30, count 0 2006.182.08:18:29.21#ibcon#about to read 5, iclass 30, count 0 2006.182.08:18:29.21#ibcon#read 5, iclass 30, count 0 2006.182.08:18:29.21#ibcon#about to read 6, iclass 30, count 0 2006.182.08:18:29.21#ibcon#read 6, iclass 30, count 0 2006.182.08:18:29.21#ibcon#end of sib2, iclass 30, count 0 2006.182.08:18:29.21#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:18:29.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:18:29.21#ibcon#[25=USB\r\n] 2006.182.08:18:29.21#ibcon#*before write, iclass 30, count 0 2006.182.08:18:29.21#ibcon#enter sib2, iclass 30, count 0 2006.182.08:18:29.21#ibcon#flushed, iclass 30, count 0 2006.182.08:18:29.21#ibcon#about to write, iclass 30, count 0 2006.182.08:18:29.21#ibcon#wrote, iclass 30, count 0 2006.182.08:18:29.21#ibcon#about to read 3, iclass 30, count 0 2006.182.08:18:29.24#ibcon#read 3, iclass 30, count 0 2006.182.08:18:29.24#ibcon#about to read 4, iclass 30, count 0 2006.182.08:18:29.24#ibcon#read 4, iclass 30, count 0 2006.182.08:18:29.24#ibcon#about to read 5, iclass 30, count 0 2006.182.08:18:29.24#ibcon#read 5, iclass 30, count 0 2006.182.08:18:29.24#ibcon#about to read 6, iclass 30, count 0 2006.182.08:18:29.24#ibcon#read 6, iclass 30, count 0 2006.182.08:18:29.24#ibcon#end of sib2, iclass 30, count 0 2006.182.08:18:29.24#ibcon#*after write, iclass 30, count 0 2006.182.08:18:29.24#ibcon#*before return 0, iclass 30, count 0 2006.182.08:18:29.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:18:29.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:18:29.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:18:29.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:18:29.24$vc4f8/valo=5,652.99 2006.182.08:18:29.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.08:18:29.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.08:18:29.24#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:29.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:29.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:29.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:29.24#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:18:29.24#ibcon#first serial, iclass 32, count 0 2006.182.08:18:29.24#ibcon#enter sib2, iclass 32, count 0 2006.182.08:18:29.24#ibcon#flushed, iclass 32, count 0 2006.182.08:18:29.24#ibcon#about to write, iclass 32, count 0 2006.182.08:18:29.24#ibcon#wrote, iclass 32, count 0 2006.182.08:18:29.24#ibcon#about to read 3, iclass 32, count 0 2006.182.08:18:29.26#ibcon#read 3, iclass 32, count 0 2006.182.08:18:29.26#ibcon#about to read 4, iclass 32, count 0 2006.182.08:18:29.26#ibcon#read 4, iclass 32, count 0 2006.182.08:18:29.26#ibcon#about to read 5, iclass 32, count 0 2006.182.08:18:29.26#ibcon#read 5, iclass 32, count 0 2006.182.08:18:29.26#ibcon#about to read 6, iclass 32, count 0 2006.182.08:18:29.26#ibcon#read 6, iclass 32, count 0 2006.182.08:18:29.26#ibcon#end of sib2, iclass 32, count 0 2006.182.08:18:29.26#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:18:29.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:18:29.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:18:29.26#ibcon#*before write, iclass 32, count 0 2006.182.08:18:29.26#ibcon#enter sib2, iclass 32, count 0 2006.182.08:18:29.26#ibcon#flushed, iclass 32, count 0 2006.182.08:18:29.26#ibcon#about to write, iclass 32, count 0 2006.182.08:18:29.26#ibcon#wrote, iclass 32, count 0 2006.182.08:18:29.26#ibcon#about to read 3, iclass 32, count 0 2006.182.08:18:29.30#ibcon#read 3, iclass 32, count 0 2006.182.08:18:29.30#ibcon#about to read 4, iclass 32, count 0 2006.182.08:18:29.30#ibcon#read 4, iclass 32, count 0 2006.182.08:18:29.30#ibcon#about to read 5, iclass 32, count 0 2006.182.08:18:29.30#ibcon#read 5, iclass 32, count 0 2006.182.08:18:29.30#ibcon#about to read 6, iclass 32, count 0 2006.182.08:18:29.30#ibcon#read 6, iclass 32, count 0 2006.182.08:18:29.30#ibcon#end of sib2, iclass 32, count 0 2006.182.08:18:29.30#ibcon#*after write, iclass 32, count 0 2006.182.08:18:29.30#ibcon#*before return 0, iclass 32, count 0 2006.182.08:18:29.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:29.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:29.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:18:29.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:18:29.30$vc4f8/va=5,7 2006.182.08:18:29.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.08:18:29.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.08:18:29.30#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:29.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:29.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:29.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:29.36#ibcon#enter wrdev, iclass 34, count 2 2006.182.08:18:29.36#ibcon#first serial, iclass 34, count 2 2006.182.08:18:29.36#ibcon#enter sib2, iclass 34, count 2 2006.182.08:18:29.36#ibcon#flushed, iclass 34, count 2 2006.182.08:18:29.36#ibcon#about to write, iclass 34, count 2 2006.182.08:18:29.36#ibcon#wrote, iclass 34, count 2 2006.182.08:18:29.36#ibcon#about to read 3, iclass 34, count 2 2006.182.08:18:29.38#ibcon#read 3, iclass 34, count 2 2006.182.08:18:29.38#ibcon#about to read 4, iclass 34, count 2 2006.182.08:18:29.38#ibcon#read 4, iclass 34, count 2 2006.182.08:18:29.38#ibcon#about to read 5, iclass 34, count 2 2006.182.08:18:29.38#ibcon#read 5, iclass 34, count 2 2006.182.08:18:29.38#ibcon#about to read 6, iclass 34, count 2 2006.182.08:18:29.38#ibcon#read 6, iclass 34, count 2 2006.182.08:18:29.38#ibcon#end of sib2, iclass 34, count 2 2006.182.08:18:29.38#ibcon#*mode == 0, iclass 34, count 2 2006.182.08:18:29.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.08:18:29.38#ibcon#[25=AT05-07\r\n] 2006.182.08:18:29.38#ibcon#*before write, iclass 34, count 2 2006.182.08:18:29.38#ibcon#enter sib2, iclass 34, count 2 2006.182.08:18:29.38#ibcon#flushed, iclass 34, count 2 2006.182.08:18:29.38#ibcon#about to write, iclass 34, count 2 2006.182.08:18:29.38#ibcon#wrote, iclass 34, count 2 2006.182.08:18:29.38#ibcon#about to read 3, iclass 34, count 2 2006.182.08:18:29.41#ibcon#read 3, iclass 34, count 2 2006.182.08:18:29.41#ibcon#about to read 4, iclass 34, count 2 2006.182.08:18:29.41#ibcon#read 4, iclass 34, count 2 2006.182.08:18:29.41#ibcon#about to read 5, iclass 34, count 2 2006.182.08:18:29.41#ibcon#read 5, iclass 34, count 2 2006.182.08:18:29.41#ibcon#about to read 6, iclass 34, count 2 2006.182.08:18:29.41#ibcon#read 6, iclass 34, count 2 2006.182.08:18:29.41#ibcon#end of sib2, iclass 34, count 2 2006.182.08:18:29.41#ibcon#*after write, iclass 34, count 2 2006.182.08:18:29.41#ibcon#*before return 0, iclass 34, count 2 2006.182.08:18:29.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:29.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:29.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.08:18:29.41#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:29.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:29.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:29.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:29.53#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:18:29.53#ibcon#first serial, iclass 34, count 0 2006.182.08:18:29.53#ibcon#enter sib2, iclass 34, count 0 2006.182.08:18:29.53#ibcon#flushed, iclass 34, count 0 2006.182.08:18:29.53#ibcon#about to write, iclass 34, count 0 2006.182.08:18:29.53#ibcon#wrote, iclass 34, count 0 2006.182.08:18:29.53#ibcon#about to read 3, iclass 34, count 0 2006.182.08:18:29.55#ibcon#read 3, iclass 34, count 0 2006.182.08:18:29.55#ibcon#about to read 4, iclass 34, count 0 2006.182.08:18:29.55#ibcon#read 4, iclass 34, count 0 2006.182.08:18:29.55#ibcon#about to read 5, iclass 34, count 0 2006.182.08:18:29.55#ibcon#read 5, iclass 34, count 0 2006.182.08:18:29.55#ibcon#about to read 6, iclass 34, count 0 2006.182.08:18:29.55#ibcon#read 6, iclass 34, count 0 2006.182.08:18:29.55#ibcon#end of sib2, iclass 34, count 0 2006.182.08:18:29.55#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:18:29.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:18:29.55#ibcon#[25=USB\r\n] 2006.182.08:18:29.55#ibcon#*before write, iclass 34, count 0 2006.182.08:18:29.55#ibcon#enter sib2, iclass 34, count 0 2006.182.08:18:29.55#ibcon#flushed, iclass 34, count 0 2006.182.08:18:29.55#ibcon#about to write, iclass 34, count 0 2006.182.08:18:29.55#ibcon#wrote, iclass 34, count 0 2006.182.08:18:29.55#ibcon#about to read 3, iclass 34, count 0 2006.182.08:18:29.58#ibcon#read 3, iclass 34, count 0 2006.182.08:18:29.58#ibcon#about to read 4, iclass 34, count 0 2006.182.08:18:29.58#ibcon#read 4, iclass 34, count 0 2006.182.08:18:29.58#ibcon#about to read 5, iclass 34, count 0 2006.182.08:18:29.58#ibcon#read 5, iclass 34, count 0 2006.182.08:18:29.58#ibcon#about to read 6, iclass 34, count 0 2006.182.08:18:29.58#ibcon#read 6, iclass 34, count 0 2006.182.08:18:29.58#ibcon#end of sib2, iclass 34, count 0 2006.182.08:18:29.58#ibcon#*after write, iclass 34, count 0 2006.182.08:18:29.58#ibcon#*before return 0, iclass 34, count 0 2006.182.08:18:29.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:29.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:29.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:18:29.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:18:29.58$vc4f8/valo=6,772.99 2006.182.08:18:29.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.08:18:29.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.08:18:29.58#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:29.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:29.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:29.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:29.58#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:18:29.58#ibcon#first serial, iclass 36, count 0 2006.182.08:18:29.58#ibcon#enter sib2, iclass 36, count 0 2006.182.08:18:29.58#ibcon#flushed, iclass 36, count 0 2006.182.08:18:29.58#ibcon#about to write, iclass 36, count 0 2006.182.08:18:29.58#ibcon#wrote, iclass 36, count 0 2006.182.08:18:29.58#ibcon#about to read 3, iclass 36, count 0 2006.182.08:18:29.61#ibcon#read 3, iclass 36, count 0 2006.182.08:18:29.61#ibcon#about to read 4, iclass 36, count 0 2006.182.08:18:29.61#ibcon#read 4, iclass 36, count 0 2006.182.08:18:29.61#ibcon#about to read 5, iclass 36, count 0 2006.182.08:18:29.61#ibcon#read 5, iclass 36, count 0 2006.182.08:18:29.61#ibcon#about to read 6, iclass 36, count 0 2006.182.08:18:29.61#ibcon#read 6, iclass 36, count 0 2006.182.08:18:29.61#ibcon#end of sib2, iclass 36, count 0 2006.182.08:18:29.61#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:18:29.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:18:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:18:29.61#ibcon#*before write, iclass 36, count 0 2006.182.08:18:29.61#ibcon#enter sib2, iclass 36, count 0 2006.182.08:18:29.61#ibcon#flushed, iclass 36, count 0 2006.182.08:18:29.61#ibcon#about to write, iclass 36, count 0 2006.182.08:18:29.61#ibcon#wrote, iclass 36, count 0 2006.182.08:18:29.61#ibcon#about to read 3, iclass 36, count 0 2006.182.08:18:29.65#ibcon#read 3, iclass 36, count 0 2006.182.08:18:29.65#ibcon#about to read 4, iclass 36, count 0 2006.182.08:18:29.65#ibcon#read 4, iclass 36, count 0 2006.182.08:18:29.65#ibcon#about to read 5, iclass 36, count 0 2006.182.08:18:29.65#ibcon#read 5, iclass 36, count 0 2006.182.08:18:29.65#ibcon#about to read 6, iclass 36, count 0 2006.182.08:18:29.65#ibcon#read 6, iclass 36, count 0 2006.182.08:18:29.65#ibcon#end of sib2, iclass 36, count 0 2006.182.08:18:29.65#ibcon#*after write, iclass 36, count 0 2006.182.08:18:29.65#ibcon#*before return 0, iclass 36, count 0 2006.182.08:18:29.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:29.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:29.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:18:29.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:18:29.65$vc4f8/va=6,6 2006.182.08:18:29.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.08:18:29.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.08:18:29.65#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:29.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:29.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:29.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:29.70#ibcon#enter wrdev, iclass 38, count 2 2006.182.08:18:29.70#ibcon#first serial, iclass 38, count 2 2006.182.08:18:29.70#ibcon#enter sib2, iclass 38, count 2 2006.182.08:18:29.70#ibcon#flushed, iclass 38, count 2 2006.182.08:18:29.70#ibcon#about to write, iclass 38, count 2 2006.182.08:18:29.70#ibcon#wrote, iclass 38, count 2 2006.182.08:18:29.70#ibcon#about to read 3, iclass 38, count 2 2006.182.08:18:29.72#ibcon#read 3, iclass 38, count 2 2006.182.08:18:29.72#ibcon#about to read 4, iclass 38, count 2 2006.182.08:18:29.72#ibcon#read 4, iclass 38, count 2 2006.182.08:18:29.72#ibcon#about to read 5, iclass 38, count 2 2006.182.08:18:29.72#ibcon#read 5, iclass 38, count 2 2006.182.08:18:29.72#ibcon#about to read 6, iclass 38, count 2 2006.182.08:18:29.72#ibcon#read 6, iclass 38, count 2 2006.182.08:18:29.72#ibcon#end of sib2, iclass 38, count 2 2006.182.08:18:29.72#ibcon#*mode == 0, iclass 38, count 2 2006.182.08:18:29.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.08:18:29.72#ibcon#[25=AT06-06\r\n] 2006.182.08:18:29.72#ibcon#*before write, iclass 38, count 2 2006.182.08:18:29.72#ibcon#enter sib2, iclass 38, count 2 2006.182.08:18:29.72#ibcon#flushed, iclass 38, count 2 2006.182.08:18:29.72#ibcon#about to write, iclass 38, count 2 2006.182.08:18:29.72#ibcon#wrote, iclass 38, count 2 2006.182.08:18:29.72#ibcon#about to read 3, iclass 38, count 2 2006.182.08:18:29.75#ibcon#read 3, iclass 38, count 2 2006.182.08:18:29.75#ibcon#about to read 4, iclass 38, count 2 2006.182.08:18:29.75#ibcon#read 4, iclass 38, count 2 2006.182.08:18:29.75#ibcon#about to read 5, iclass 38, count 2 2006.182.08:18:29.75#ibcon#read 5, iclass 38, count 2 2006.182.08:18:29.75#ibcon#about to read 6, iclass 38, count 2 2006.182.08:18:29.75#ibcon#read 6, iclass 38, count 2 2006.182.08:18:29.75#ibcon#end of sib2, iclass 38, count 2 2006.182.08:18:29.75#ibcon#*after write, iclass 38, count 2 2006.182.08:18:29.75#ibcon#*before return 0, iclass 38, count 2 2006.182.08:18:29.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:29.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:29.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.08:18:29.75#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:29.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:29.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:29.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:29.87#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:18:29.87#ibcon#first serial, iclass 38, count 0 2006.182.08:18:29.87#ibcon#enter sib2, iclass 38, count 0 2006.182.08:18:29.87#ibcon#flushed, iclass 38, count 0 2006.182.08:18:29.87#ibcon#about to write, iclass 38, count 0 2006.182.08:18:29.87#ibcon#wrote, iclass 38, count 0 2006.182.08:18:29.87#ibcon#about to read 3, iclass 38, count 0 2006.182.08:18:29.89#ibcon#read 3, iclass 38, count 0 2006.182.08:18:29.89#ibcon#about to read 4, iclass 38, count 0 2006.182.08:18:29.89#ibcon#read 4, iclass 38, count 0 2006.182.08:18:29.89#ibcon#about to read 5, iclass 38, count 0 2006.182.08:18:29.89#ibcon#read 5, iclass 38, count 0 2006.182.08:18:29.89#ibcon#about to read 6, iclass 38, count 0 2006.182.08:18:29.89#ibcon#read 6, iclass 38, count 0 2006.182.08:18:29.89#ibcon#end of sib2, iclass 38, count 0 2006.182.08:18:29.89#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:18:29.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:18:29.89#ibcon#[25=USB\r\n] 2006.182.08:18:29.89#ibcon#*before write, iclass 38, count 0 2006.182.08:18:29.89#ibcon#enter sib2, iclass 38, count 0 2006.182.08:18:29.89#ibcon#flushed, iclass 38, count 0 2006.182.08:18:29.89#ibcon#about to write, iclass 38, count 0 2006.182.08:18:29.89#ibcon#wrote, iclass 38, count 0 2006.182.08:18:29.89#ibcon#about to read 3, iclass 38, count 0 2006.182.08:18:29.92#ibcon#read 3, iclass 38, count 0 2006.182.08:18:29.92#ibcon#about to read 4, iclass 38, count 0 2006.182.08:18:29.92#ibcon#read 4, iclass 38, count 0 2006.182.08:18:29.92#ibcon#about to read 5, iclass 38, count 0 2006.182.08:18:29.92#ibcon#read 5, iclass 38, count 0 2006.182.08:18:29.92#ibcon#about to read 6, iclass 38, count 0 2006.182.08:18:29.92#ibcon#read 6, iclass 38, count 0 2006.182.08:18:29.92#ibcon#end of sib2, iclass 38, count 0 2006.182.08:18:29.92#ibcon#*after write, iclass 38, count 0 2006.182.08:18:29.92#ibcon#*before return 0, iclass 38, count 0 2006.182.08:18:29.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:29.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:29.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:18:29.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:18:29.92$vc4f8/valo=7,832.99 2006.182.08:18:29.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.08:18:29.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.08:18:29.92#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:29.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:29.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:29.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:29.92#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:18:29.92#ibcon#first serial, iclass 40, count 0 2006.182.08:18:29.92#ibcon#enter sib2, iclass 40, count 0 2006.182.08:18:29.92#ibcon#flushed, iclass 40, count 0 2006.182.08:18:29.92#ibcon#about to write, iclass 40, count 0 2006.182.08:18:29.92#ibcon#wrote, iclass 40, count 0 2006.182.08:18:29.92#ibcon#about to read 3, iclass 40, count 0 2006.182.08:18:29.94#ibcon#read 3, iclass 40, count 0 2006.182.08:18:29.94#ibcon#about to read 4, iclass 40, count 0 2006.182.08:18:29.94#ibcon#read 4, iclass 40, count 0 2006.182.08:18:29.94#ibcon#about to read 5, iclass 40, count 0 2006.182.08:18:29.94#ibcon#read 5, iclass 40, count 0 2006.182.08:18:29.94#ibcon#about to read 6, iclass 40, count 0 2006.182.08:18:29.94#ibcon#read 6, iclass 40, count 0 2006.182.08:18:29.94#ibcon#end of sib2, iclass 40, count 0 2006.182.08:18:29.94#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:18:29.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:18:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:18:29.94#ibcon#*before write, iclass 40, count 0 2006.182.08:18:29.94#ibcon#enter sib2, iclass 40, count 0 2006.182.08:18:29.94#ibcon#flushed, iclass 40, count 0 2006.182.08:18:29.94#ibcon#about to write, iclass 40, count 0 2006.182.08:18:29.94#ibcon#wrote, iclass 40, count 0 2006.182.08:18:29.94#ibcon#about to read 3, iclass 40, count 0 2006.182.08:18:29.98#ibcon#read 3, iclass 40, count 0 2006.182.08:18:29.98#ibcon#about to read 4, iclass 40, count 0 2006.182.08:18:29.98#ibcon#read 4, iclass 40, count 0 2006.182.08:18:29.98#ibcon#about to read 5, iclass 40, count 0 2006.182.08:18:29.98#ibcon#read 5, iclass 40, count 0 2006.182.08:18:29.98#ibcon#about to read 6, iclass 40, count 0 2006.182.08:18:29.98#ibcon#read 6, iclass 40, count 0 2006.182.08:18:29.98#ibcon#end of sib2, iclass 40, count 0 2006.182.08:18:29.98#ibcon#*after write, iclass 40, count 0 2006.182.08:18:29.98#ibcon#*before return 0, iclass 40, count 0 2006.182.08:18:29.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:29.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:29.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:18:29.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:18:29.98$vc4f8/va=7,6 2006.182.08:18:29.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.08:18:29.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.08:18:29.98#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:29.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:18:30.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:18:30.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:18:30.04#ibcon#enter wrdev, iclass 4, count 2 2006.182.08:18:30.04#ibcon#first serial, iclass 4, count 2 2006.182.08:18:30.04#ibcon#enter sib2, iclass 4, count 2 2006.182.08:18:30.04#ibcon#flushed, iclass 4, count 2 2006.182.08:18:30.04#ibcon#about to write, iclass 4, count 2 2006.182.08:18:30.04#ibcon#wrote, iclass 4, count 2 2006.182.08:18:30.04#ibcon#about to read 3, iclass 4, count 2 2006.182.08:18:30.06#ibcon#read 3, iclass 4, count 2 2006.182.08:18:30.06#ibcon#about to read 4, iclass 4, count 2 2006.182.08:18:30.06#ibcon#read 4, iclass 4, count 2 2006.182.08:18:30.06#ibcon#about to read 5, iclass 4, count 2 2006.182.08:18:30.06#ibcon#read 5, iclass 4, count 2 2006.182.08:18:30.06#ibcon#about to read 6, iclass 4, count 2 2006.182.08:18:30.06#ibcon#read 6, iclass 4, count 2 2006.182.08:18:30.06#ibcon#end of sib2, iclass 4, count 2 2006.182.08:18:30.06#ibcon#*mode == 0, iclass 4, count 2 2006.182.08:18:30.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.08:18:30.06#ibcon#[25=AT07-06\r\n] 2006.182.08:18:30.06#ibcon#*before write, iclass 4, count 2 2006.182.08:18:30.06#ibcon#enter sib2, iclass 4, count 2 2006.182.08:18:30.06#ibcon#flushed, iclass 4, count 2 2006.182.08:18:30.06#ibcon#about to write, iclass 4, count 2 2006.182.08:18:30.06#ibcon#wrote, iclass 4, count 2 2006.182.08:18:30.06#ibcon#about to read 3, iclass 4, count 2 2006.182.08:18:30.09#ibcon#read 3, iclass 4, count 2 2006.182.08:18:30.09#ibcon#about to read 4, iclass 4, count 2 2006.182.08:18:30.09#ibcon#read 4, iclass 4, count 2 2006.182.08:18:30.09#ibcon#about to read 5, iclass 4, count 2 2006.182.08:18:30.09#ibcon#read 5, iclass 4, count 2 2006.182.08:18:30.09#ibcon#about to read 6, iclass 4, count 2 2006.182.08:18:30.09#ibcon#read 6, iclass 4, count 2 2006.182.08:18:30.09#ibcon#end of sib2, iclass 4, count 2 2006.182.08:18:30.09#ibcon#*after write, iclass 4, count 2 2006.182.08:18:30.09#ibcon#*before return 0, iclass 4, count 2 2006.182.08:18:30.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:18:30.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:18:30.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.08:18:30.09#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:30.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:18:30.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:18:30.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:18:30.21#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:18:30.21#ibcon#first serial, iclass 4, count 0 2006.182.08:18:30.21#ibcon#enter sib2, iclass 4, count 0 2006.182.08:18:30.21#ibcon#flushed, iclass 4, count 0 2006.182.08:18:30.21#ibcon#about to write, iclass 4, count 0 2006.182.08:18:30.21#ibcon#wrote, iclass 4, count 0 2006.182.08:18:30.21#ibcon#about to read 3, iclass 4, count 0 2006.182.08:18:30.23#ibcon#read 3, iclass 4, count 0 2006.182.08:18:30.23#ibcon#about to read 4, iclass 4, count 0 2006.182.08:18:30.23#ibcon#read 4, iclass 4, count 0 2006.182.08:18:30.23#ibcon#about to read 5, iclass 4, count 0 2006.182.08:18:30.23#ibcon#read 5, iclass 4, count 0 2006.182.08:18:30.23#ibcon#about to read 6, iclass 4, count 0 2006.182.08:18:30.23#ibcon#read 6, iclass 4, count 0 2006.182.08:18:30.23#ibcon#end of sib2, iclass 4, count 0 2006.182.08:18:30.23#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:18:30.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:18:30.23#ibcon#[25=USB\r\n] 2006.182.08:18:30.23#ibcon#*before write, iclass 4, count 0 2006.182.08:18:30.23#ibcon#enter sib2, iclass 4, count 0 2006.182.08:18:30.23#ibcon#flushed, iclass 4, count 0 2006.182.08:18:30.23#ibcon#about to write, iclass 4, count 0 2006.182.08:18:30.23#ibcon#wrote, iclass 4, count 0 2006.182.08:18:30.23#ibcon#about to read 3, iclass 4, count 0 2006.182.08:18:30.26#ibcon#read 3, iclass 4, count 0 2006.182.08:18:30.26#ibcon#about to read 4, iclass 4, count 0 2006.182.08:18:30.26#ibcon#read 4, iclass 4, count 0 2006.182.08:18:30.26#ibcon#about to read 5, iclass 4, count 0 2006.182.08:18:30.26#ibcon#read 5, iclass 4, count 0 2006.182.08:18:30.26#ibcon#about to read 6, iclass 4, count 0 2006.182.08:18:30.26#ibcon#read 6, iclass 4, count 0 2006.182.08:18:30.26#ibcon#end of sib2, iclass 4, count 0 2006.182.08:18:30.26#ibcon#*after write, iclass 4, count 0 2006.182.08:18:30.26#ibcon#*before return 0, iclass 4, count 0 2006.182.08:18:30.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:18:30.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:18:30.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:18:30.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:18:30.26$vc4f8/valo=8,852.99 2006.182.08:18:30.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.08:18:30.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.08:18:30.26#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:30.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:18:30.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:18:30.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:18:30.26#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:18:30.26#ibcon#first serial, iclass 6, count 0 2006.182.08:18:30.26#ibcon#enter sib2, iclass 6, count 0 2006.182.08:18:30.26#ibcon#flushed, iclass 6, count 0 2006.182.08:18:30.26#ibcon#about to write, iclass 6, count 0 2006.182.08:18:30.26#ibcon#wrote, iclass 6, count 0 2006.182.08:18:30.26#ibcon#about to read 3, iclass 6, count 0 2006.182.08:18:30.28#ibcon#read 3, iclass 6, count 0 2006.182.08:18:30.28#ibcon#about to read 4, iclass 6, count 0 2006.182.08:18:30.28#ibcon#read 4, iclass 6, count 0 2006.182.08:18:30.28#ibcon#about to read 5, iclass 6, count 0 2006.182.08:18:30.28#ibcon#read 5, iclass 6, count 0 2006.182.08:18:30.28#ibcon#about to read 6, iclass 6, count 0 2006.182.08:18:30.28#ibcon#read 6, iclass 6, count 0 2006.182.08:18:30.28#ibcon#end of sib2, iclass 6, count 0 2006.182.08:18:30.28#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:18:30.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:18:30.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:18:30.28#ibcon#*before write, iclass 6, count 0 2006.182.08:18:30.28#ibcon#enter sib2, iclass 6, count 0 2006.182.08:18:30.28#ibcon#flushed, iclass 6, count 0 2006.182.08:18:30.28#ibcon#about to write, iclass 6, count 0 2006.182.08:18:30.28#ibcon#wrote, iclass 6, count 0 2006.182.08:18:30.28#ibcon#about to read 3, iclass 6, count 0 2006.182.08:18:30.32#ibcon#read 3, iclass 6, count 0 2006.182.08:18:30.32#ibcon#about to read 4, iclass 6, count 0 2006.182.08:18:30.32#ibcon#read 4, iclass 6, count 0 2006.182.08:18:30.32#ibcon#about to read 5, iclass 6, count 0 2006.182.08:18:30.32#ibcon#read 5, iclass 6, count 0 2006.182.08:18:30.32#ibcon#about to read 6, iclass 6, count 0 2006.182.08:18:30.32#ibcon#read 6, iclass 6, count 0 2006.182.08:18:30.32#ibcon#end of sib2, iclass 6, count 0 2006.182.08:18:30.32#ibcon#*after write, iclass 6, count 0 2006.182.08:18:30.32#ibcon#*before return 0, iclass 6, count 0 2006.182.08:18:30.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:18:30.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:18:30.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:18:30.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:18:30.32$vc4f8/va=8,7 2006.182.08:18:30.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.08:18:30.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.08:18:30.32#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:30.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:18:30.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:18:30.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:18:30.38#ibcon#enter wrdev, iclass 10, count 2 2006.182.08:18:30.38#ibcon#first serial, iclass 10, count 2 2006.182.08:18:30.38#ibcon#enter sib2, iclass 10, count 2 2006.182.08:18:30.38#ibcon#flushed, iclass 10, count 2 2006.182.08:18:30.38#ibcon#about to write, iclass 10, count 2 2006.182.08:18:30.38#ibcon#wrote, iclass 10, count 2 2006.182.08:18:30.38#ibcon#about to read 3, iclass 10, count 2 2006.182.08:18:30.40#ibcon#read 3, iclass 10, count 2 2006.182.08:18:30.40#ibcon#about to read 4, iclass 10, count 2 2006.182.08:18:30.40#ibcon#read 4, iclass 10, count 2 2006.182.08:18:30.40#ibcon#about to read 5, iclass 10, count 2 2006.182.08:18:30.40#ibcon#read 5, iclass 10, count 2 2006.182.08:18:30.40#ibcon#about to read 6, iclass 10, count 2 2006.182.08:18:30.40#ibcon#read 6, iclass 10, count 2 2006.182.08:18:30.40#ibcon#end of sib2, iclass 10, count 2 2006.182.08:18:30.40#ibcon#*mode == 0, iclass 10, count 2 2006.182.08:18:30.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.08:18:30.40#ibcon#[25=AT08-07\r\n] 2006.182.08:18:30.40#ibcon#*before write, iclass 10, count 2 2006.182.08:18:30.40#ibcon#enter sib2, iclass 10, count 2 2006.182.08:18:30.40#ibcon#flushed, iclass 10, count 2 2006.182.08:18:30.40#ibcon#about to write, iclass 10, count 2 2006.182.08:18:30.40#ibcon#wrote, iclass 10, count 2 2006.182.08:18:30.40#ibcon#about to read 3, iclass 10, count 2 2006.182.08:18:30.43#ibcon#read 3, iclass 10, count 2 2006.182.08:18:30.43#ibcon#about to read 4, iclass 10, count 2 2006.182.08:18:30.43#ibcon#read 4, iclass 10, count 2 2006.182.08:18:30.43#ibcon#about to read 5, iclass 10, count 2 2006.182.08:18:30.43#ibcon#read 5, iclass 10, count 2 2006.182.08:18:30.43#ibcon#about to read 6, iclass 10, count 2 2006.182.08:18:30.43#ibcon#read 6, iclass 10, count 2 2006.182.08:18:30.43#ibcon#end of sib2, iclass 10, count 2 2006.182.08:18:30.43#ibcon#*after write, iclass 10, count 2 2006.182.08:18:30.43#ibcon#*before return 0, iclass 10, count 2 2006.182.08:18:30.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:18:30.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:18:30.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.08:18:30.43#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:30.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:18:30.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:18:30.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:18:30.55#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:18:30.55#ibcon#first serial, iclass 10, count 0 2006.182.08:18:30.55#ibcon#enter sib2, iclass 10, count 0 2006.182.08:18:30.55#ibcon#flushed, iclass 10, count 0 2006.182.08:18:30.55#ibcon#about to write, iclass 10, count 0 2006.182.08:18:30.55#ibcon#wrote, iclass 10, count 0 2006.182.08:18:30.55#ibcon#about to read 3, iclass 10, count 0 2006.182.08:18:30.57#ibcon#read 3, iclass 10, count 0 2006.182.08:18:30.57#ibcon#about to read 4, iclass 10, count 0 2006.182.08:18:30.57#ibcon#read 4, iclass 10, count 0 2006.182.08:18:30.57#ibcon#about to read 5, iclass 10, count 0 2006.182.08:18:30.57#ibcon#read 5, iclass 10, count 0 2006.182.08:18:30.57#ibcon#about to read 6, iclass 10, count 0 2006.182.08:18:30.57#ibcon#read 6, iclass 10, count 0 2006.182.08:18:30.57#ibcon#end of sib2, iclass 10, count 0 2006.182.08:18:30.57#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:18:30.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:18:30.57#ibcon#[25=USB\r\n] 2006.182.08:18:30.57#ibcon#*before write, iclass 10, count 0 2006.182.08:18:30.57#ibcon#enter sib2, iclass 10, count 0 2006.182.08:18:30.57#ibcon#flushed, iclass 10, count 0 2006.182.08:18:30.57#ibcon#about to write, iclass 10, count 0 2006.182.08:18:30.57#ibcon#wrote, iclass 10, count 0 2006.182.08:18:30.57#ibcon#about to read 3, iclass 10, count 0 2006.182.08:18:30.60#ibcon#read 3, iclass 10, count 0 2006.182.08:18:30.60#ibcon#about to read 4, iclass 10, count 0 2006.182.08:18:30.60#ibcon#read 4, iclass 10, count 0 2006.182.08:18:30.60#ibcon#about to read 5, iclass 10, count 0 2006.182.08:18:30.60#ibcon#read 5, iclass 10, count 0 2006.182.08:18:30.60#ibcon#about to read 6, iclass 10, count 0 2006.182.08:18:30.60#ibcon#read 6, iclass 10, count 0 2006.182.08:18:30.60#ibcon#end of sib2, iclass 10, count 0 2006.182.08:18:30.60#ibcon#*after write, iclass 10, count 0 2006.182.08:18:30.60#ibcon#*before return 0, iclass 10, count 0 2006.182.08:18:30.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:18:30.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:18:30.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:18:30.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:18:30.60$vc4f8/vblo=1,632.99 2006.182.08:18:30.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.08:18:30.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.08:18:30.60#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:30.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:18:30.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:18:30.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:18:30.60#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:18:30.60#ibcon#first serial, iclass 12, count 0 2006.182.08:18:30.60#ibcon#enter sib2, iclass 12, count 0 2006.182.08:18:30.60#ibcon#flushed, iclass 12, count 0 2006.182.08:18:30.60#ibcon#about to write, iclass 12, count 0 2006.182.08:18:30.60#ibcon#wrote, iclass 12, count 0 2006.182.08:18:30.60#ibcon#about to read 3, iclass 12, count 0 2006.182.08:18:30.62#ibcon#read 3, iclass 12, count 0 2006.182.08:18:30.62#ibcon#about to read 4, iclass 12, count 0 2006.182.08:18:30.62#ibcon#read 4, iclass 12, count 0 2006.182.08:18:30.62#ibcon#about to read 5, iclass 12, count 0 2006.182.08:18:30.62#ibcon#read 5, iclass 12, count 0 2006.182.08:18:30.62#ibcon#about to read 6, iclass 12, count 0 2006.182.08:18:30.62#ibcon#read 6, iclass 12, count 0 2006.182.08:18:30.62#ibcon#end of sib2, iclass 12, count 0 2006.182.08:18:30.62#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:18:30.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:18:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:18:30.62#ibcon#*before write, iclass 12, count 0 2006.182.08:18:30.62#ibcon#enter sib2, iclass 12, count 0 2006.182.08:18:30.62#ibcon#flushed, iclass 12, count 0 2006.182.08:18:30.62#ibcon#about to write, iclass 12, count 0 2006.182.08:18:30.62#ibcon#wrote, iclass 12, count 0 2006.182.08:18:30.62#ibcon#about to read 3, iclass 12, count 0 2006.182.08:18:30.66#ibcon#read 3, iclass 12, count 0 2006.182.08:18:30.66#ibcon#about to read 4, iclass 12, count 0 2006.182.08:18:30.66#ibcon#read 4, iclass 12, count 0 2006.182.08:18:30.66#ibcon#about to read 5, iclass 12, count 0 2006.182.08:18:30.66#ibcon#read 5, iclass 12, count 0 2006.182.08:18:30.66#ibcon#about to read 6, iclass 12, count 0 2006.182.08:18:30.66#ibcon#read 6, iclass 12, count 0 2006.182.08:18:30.66#ibcon#end of sib2, iclass 12, count 0 2006.182.08:18:30.66#ibcon#*after write, iclass 12, count 0 2006.182.08:18:30.66#ibcon#*before return 0, iclass 12, count 0 2006.182.08:18:30.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:18:30.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:18:30.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:18:30.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:18:30.66$vc4f8/vb=1,4 2006.182.08:18:30.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.08:18:30.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.08:18:30.66#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:30.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:18:30.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:18:30.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:18:30.66#ibcon#enter wrdev, iclass 14, count 2 2006.182.08:18:30.66#ibcon#first serial, iclass 14, count 2 2006.182.08:18:30.66#ibcon#enter sib2, iclass 14, count 2 2006.182.08:18:30.66#ibcon#flushed, iclass 14, count 2 2006.182.08:18:30.66#ibcon#about to write, iclass 14, count 2 2006.182.08:18:30.66#ibcon#wrote, iclass 14, count 2 2006.182.08:18:30.66#ibcon#about to read 3, iclass 14, count 2 2006.182.08:18:30.68#ibcon#read 3, iclass 14, count 2 2006.182.08:18:30.68#ibcon#about to read 4, iclass 14, count 2 2006.182.08:18:30.68#ibcon#read 4, iclass 14, count 2 2006.182.08:18:30.68#ibcon#about to read 5, iclass 14, count 2 2006.182.08:18:30.68#ibcon#read 5, iclass 14, count 2 2006.182.08:18:30.68#ibcon#about to read 6, iclass 14, count 2 2006.182.08:18:30.68#ibcon#read 6, iclass 14, count 2 2006.182.08:18:30.68#ibcon#end of sib2, iclass 14, count 2 2006.182.08:18:30.68#ibcon#*mode == 0, iclass 14, count 2 2006.182.08:18:30.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.08:18:30.68#ibcon#[27=AT01-04\r\n] 2006.182.08:18:30.68#ibcon#*before write, iclass 14, count 2 2006.182.08:18:30.68#ibcon#enter sib2, iclass 14, count 2 2006.182.08:18:30.68#ibcon#flushed, iclass 14, count 2 2006.182.08:18:30.68#ibcon#about to write, iclass 14, count 2 2006.182.08:18:30.68#ibcon#wrote, iclass 14, count 2 2006.182.08:18:30.68#ibcon#about to read 3, iclass 14, count 2 2006.182.08:18:30.71#ibcon#read 3, iclass 14, count 2 2006.182.08:18:30.71#ibcon#about to read 4, iclass 14, count 2 2006.182.08:18:30.71#ibcon#read 4, iclass 14, count 2 2006.182.08:18:30.71#ibcon#about to read 5, iclass 14, count 2 2006.182.08:18:30.71#ibcon#read 5, iclass 14, count 2 2006.182.08:18:30.71#ibcon#about to read 6, iclass 14, count 2 2006.182.08:18:30.71#ibcon#read 6, iclass 14, count 2 2006.182.08:18:30.71#ibcon#end of sib2, iclass 14, count 2 2006.182.08:18:30.71#ibcon#*after write, iclass 14, count 2 2006.182.08:18:30.71#ibcon#*before return 0, iclass 14, count 2 2006.182.08:18:30.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:18:30.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:18:30.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.08:18:30.71#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:30.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:18:30.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:18:30.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:18:30.83#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:18:30.83#ibcon#first serial, iclass 14, count 0 2006.182.08:18:30.83#ibcon#enter sib2, iclass 14, count 0 2006.182.08:18:30.83#ibcon#flushed, iclass 14, count 0 2006.182.08:18:30.83#ibcon#about to write, iclass 14, count 0 2006.182.08:18:30.83#ibcon#wrote, iclass 14, count 0 2006.182.08:18:30.83#ibcon#about to read 3, iclass 14, count 0 2006.182.08:18:30.85#ibcon#read 3, iclass 14, count 0 2006.182.08:18:30.85#ibcon#about to read 4, iclass 14, count 0 2006.182.08:18:30.85#ibcon#read 4, iclass 14, count 0 2006.182.08:18:30.85#ibcon#about to read 5, iclass 14, count 0 2006.182.08:18:30.85#ibcon#read 5, iclass 14, count 0 2006.182.08:18:30.85#ibcon#about to read 6, iclass 14, count 0 2006.182.08:18:30.85#ibcon#read 6, iclass 14, count 0 2006.182.08:18:30.85#ibcon#end of sib2, iclass 14, count 0 2006.182.08:18:30.85#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:18:30.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:18:30.85#ibcon#[27=USB\r\n] 2006.182.08:18:30.85#ibcon#*before write, iclass 14, count 0 2006.182.08:18:30.85#ibcon#enter sib2, iclass 14, count 0 2006.182.08:18:30.85#ibcon#flushed, iclass 14, count 0 2006.182.08:18:30.85#ibcon#about to write, iclass 14, count 0 2006.182.08:18:30.85#ibcon#wrote, iclass 14, count 0 2006.182.08:18:30.85#ibcon#about to read 3, iclass 14, count 0 2006.182.08:18:30.88#ibcon#read 3, iclass 14, count 0 2006.182.08:18:30.88#ibcon#about to read 4, iclass 14, count 0 2006.182.08:18:30.88#ibcon#read 4, iclass 14, count 0 2006.182.08:18:30.88#ibcon#about to read 5, iclass 14, count 0 2006.182.08:18:30.88#ibcon#read 5, iclass 14, count 0 2006.182.08:18:30.88#ibcon#about to read 6, iclass 14, count 0 2006.182.08:18:30.88#ibcon#read 6, iclass 14, count 0 2006.182.08:18:30.88#ibcon#end of sib2, iclass 14, count 0 2006.182.08:18:30.88#ibcon#*after write, iclass 14, count 0 2006.182.08:18:30.88#ibcon#*before return 0, iclass 14, count 0 2006.182.08:18:30.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:18:30.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:18:30.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:18:30.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:18:30.88$vc4f8/vblo=2,640.99 2006.182.08:18:30.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.08:18:30.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.08:18:30.88#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:30.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:30.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:30.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:30.88#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:18:30.88#ibcon#first serial, iclass 16, count 0 2006.182.08:18:30.88#ibcon#enter sib2, iclass 16, count 0 2006.182.08:18:30.88#ibcon#flushed, iclass 16, count 0 2006.182.08:18:30.88#ibcon#about to write, iclass 16, count 0 2006.182.08:18:30.88#ibcon#wrote, iclass 16, count 0 2006.182.08:18:30.88#ibcon#about to read 3, iclass 16, count 0 2006.182.08:18:30.90#ibcon#read 3, iclass 16, count 0 2006.182.08:18:30.90#ibcon#about to read 4, iclass 16, count 0 2006.182.08:18:30.90#ibcon#read 4, iclass 16, count 0 2006.182.08:18:30.90#ibcon#about to read 5, iclass 16, count 0 2006.182.08:18:30.90#ibcon#read 5, iclass 16, count 0 2006.182.08:18:30.90#ibcon#about to read 6, iclass 16, count 0 2006.182.08:18:30.90#ibcon#read 6, iclass 16, count 0 2006.182.08:18:30.90#ibcon#end of sib2, iclass 16, count 0 2006.182.08:18:30.90#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:18:30.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:18:30.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:18:30.90#ibcon#*before write, iclass 16, count 0 2006.182.08:18:30.90#ibcon#enter sib2, iclass 16, count 0 2006.182.08:18:30.90#ibcon#flushed, iclass 16, count 0 2006.182.08:18:30.90#ibcon#about to write, iclass 16, count 0 2006.182.08:18:30.90#ibcon#wrote, iclass 16, count 0 2006.182.08:18:30.90#ibcon#about to read 3, iclass 16, count 0 2006.182.08:18:30.94#ibcon#read 3, iclass 16, count 0 2006.182.08:18:30.94#ibcon#about to read 4, iclass 16, count 0 2006.182.08:18:30.94#ibcon#read 4, iclass 16, count 0 2006.182.08:18:30.94#ibcon#about to read 5, iclass 16, count 0 2006.182.08:18:30.94#ibcon#read 5, iclass 16, count 0 2006.182.08:18:30.94#ibcon#about to read 6, iclass 16, count 0 2006.182.08:18:30.94#ibcon#read 6, iclass 16, count 0 2006.182.08:18:30.94#ibcon#end of sib2, iclass 16, count 0 2006.182.08:18:30.94#ibcon#*after write, iclass 16, count 0 2006.182.08:18:30.94#ibcon#*before return 0, iclass 16, count 0 2006.182.08:18:30.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:30.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:18:30.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:18:30.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:18:30.94$vc4f8/vb=2,4 2006.182.08:18:30.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.08:18:30.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.08:18:30.94#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:30.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:31.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:31.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:31.00#ibcon#enter wrdev, iclass 18, count 2 2006.182.08:18:31.00#ibcon#first serial, iclass 18, count 2 2006.182.08:18:31.00#ibcon#enter sib2, iclass 18, count 2 2006.182.08:18:31.00#ibcon#flushed, iclass 18, count 2 2006.182.08:18:31.00#ibcon#about to write, iclass 18, count 2 2006.182.08:18:31.00#ibcon#wrote, iclass 18, count 2 2006.182.08:18:31.00#ibcon#about to read 3, iclass 18, count 2 2006.182.08:18:31.02#ibcon#read 3, iclass 18, count 2 2006.182.08:18:31.02#ibcon#about to read 4, iclass 18, count 2 2006.182.08:18:31.02#ibcon#read 4, iclass 18, count 2 2006.182.08:18:31.02#ibcon#about to read 5, iclass 18, count 2 2006.182.08:18:31.02#ibcon#read 5, iclass 18, count 2 2006.182.08:18:31.02#ibcon#about to read 6, iclass 18, count 2 2006.182.08:18:31.02#ibcon#read 6, iclass 18, count 2 2006.182.08:18:31.02#ibcon#end of sib2, iclass 18, count 2 2006.182.08:18:31.02#ibcon#*mode == 0, iclass 18, count 2 2006.182.08:18:31.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.08:18:31.02#ibcon#[27=AT02-04\r\n] 2006.182.08:18:31.02#ibcon#*before write, iclass 18, count 2 2006.182.08:18:31.02#ibcon#enter sib2, iclass 18, count 2 2006.182.08:18:31.02#ibcon#flushed, iclass 18, count 2 2006.182.08:18:31.02#ibcon#about to write, iclass 18, count 2 2006.182.08:18:31.02#ibcon#wrote, iclass 18, count 2 2006.182.08:18:31.02#ibcon#about to read 3, iclass 18, count 2 2006.182.08:18:31.05#ibcon#read 3, iclass 18, count 2 2006.182.08:18:31.05#ibcon#about to read 4, iclass 18, count 2 2006.182.08:18:31.05#ibcon#read 4, iclass 18, count 2 2006.182.08:18:31.05#ibcon#about to read 5, iclass 18, count 2 2006.182.08:18:31.05#ibcon#read 5, iclass 18, count 2 2006.182.08:18:31.05#ibcon#about to read 6, iclass 18, count 2 2006.182.08:18:31.05#ibcon#read 6, iclass 18, count 2 2006.182.08:18:31.05#ibcon#end of sib2, iclass 18, count 2 2006.182.08:18:31.05#ibcon#*after write, iclass 18, count 2 2006.182.08:18:31.05#ibcon#*before return 0, iclass 18, count 2 2006.182.08:18:31.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:31.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:18:31.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.08:18:31.05#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:31.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:31.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:31.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:31.17#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:18:31.17#ibcon#first serial, iclass 18, count 0 2006.182.08:18:31.17#ibcon#enter sib2, iclass 18, count 0 2006.182.08:18:31.17#ibcon#flushed, iclass 18, count 0 2006.182.08:18:31.17#ibcon#about to write, iclass 18, count 0 2006.182.08:18:31.17#ibcon#wrote, iclass 18, count 0 2006.182.08:18:31.17#ibcon#about to read 3, iclass 18, count 0 2006.182.08:18:31.20#ibcon#read 3, iclass 18, count 0 2006.182.08:18:31.20#ibcon#about to read 4, iclass 18, count 0 2006.182.08:18:31.20#ibcon#read 4, iclass 18, count 0 2006.182.08:18:31.20#ibcon#about to read 5, iclass 18, count 0 2006.182.08:18:31.20#ibcon#read 5, iclass 18, count 0 2006.182.08:18:31.20#ibcon#about to read 6, iclass 18, count 0 2006.182.08:18:31.20#ibcon#read 6, iclass 18, count 0 2006.182.08:18:31.20#ibcon#end of sib2, iclass 18, count 0 2006.182.08:18:31.20#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:18:31.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:18:31.20#ibcon#[27=USB\r\n] 2006.182.08:18:31.20#ibcon#*before write, iclass 18, count 0 2006.182.08:18:31.20#ibcon#enter sib2, iclass 18, count 0 2006.182.08:18:31.20#ibcon#flushed, iclass 18, count 0 2006.182.08:18:31.20#ibcon#about to write, iclass 18, count 0 2006.182.08:18:31.20#ibcon#wrote, iclass 18, count 0 2006.182.08:18:31.20#ibcon#about to read 3, iclass 18, count 0 2006.182.08:18:31.23#ibcon#read 3, iclass 18, count 0 2006.182.08:18:31.23#ibcon#about to read 4, iclass 18, count 0 2006.182.08:18:31.23#ibcon#read 4, iclass 18, count 0 2006.182.08:18:31.23#ibcon#about to read 5, iclass 18, count 0 2006.182.08:18:31.23#ibcon#read 5, iclass 18, count 0 2006.182.08:18:31.23#ibcon#about to read 6, iclass 18, count 0 2006.182.08:18:31.23#ibcon#read 6, iclass 18, count 0 2006.182.08:18:31.23#ibcon#end of sib2, iclass 18, count 0 2006.182.08:18:31.23#ibcon#*after write, iclass 18, count 0 2006.182.08:18:31.23#ibcon#*before return 0, iclass 18, count 0 2006.182.08:18:31.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:31.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:18:31.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:18:31.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:18:31.23$vc4f8/vblo=3,656.99 2006.182.08:18:31.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.08:18:31.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.08:18:31.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:31.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:31.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:31.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:31.23#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:18:31.23#ibcon#first serial, iclass 20, count 0 2006.182.08:18:31.23#ibcon#enter sib2, iclass 20, count 0 2006.182.08:18:31.23#ibcon#flushed, iclass 20, count 0 2006.182.08:18:31.23#ibcon#about to write, iclass 20, count 0 2006.182.08:18:31.23#ibcon#wrote, iclass 20, count 0 2006.182.08:18:31.23#ibcon#about to read 3, iclass 20, count 0 2006.182.08:18:31.25#ibcon#read 3, iclass 20, count 0 2006.182.08:18:31.25#ibcon#about to read 4, iclass 20, count 0 2006.182.08:18:31.25#ibcon#read 4, iclass 20, count 0 2006.182.08:18:31.25#ibcon#about to read 5, iclass 20, count 0 2006.182.08:18:31.25#ibcon#read 5, iclass 20, count 0 2006.182.08:18:31.25#ibcon#about to read 6, iclass 20, count 0 2006.182.08:18:31.25#ibcon#read 6, iclass 20, count 0 2006.182.08:18:31.25#ibcon#end of sib2, iclass 20, count 0 2006.182.08:18:31.25#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:18:31.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:18:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:18:31.25#ibcon#*before write, iclass 20, count 0 2006.182.08:18:31.25#ibcon#enter sib2, iclass 20, count 0 2006.182.08:18:31.25#ibcon#flushed, iclass 20, count 0 2006.182.08:18:31.25#ibcon#about to write, iclass 20, count 0 2006.182.08:18:31.25#ibcon#wrote, iclass 20, count 0 2006.182.08:18:31.25#ibcon#about to read 3, iclass 20, count 0 2006.182.08:18:31.29#ibcon#read 3, iclass 20, count 0 2006.182.08:18:31.29#ibcon#about to read 4, iclass 20, count 0 2006.182.08:18:31.29#ibcon#read 4, iclass 20, count 0 2006.182.08:18:31.29#ibcon#about to read 5, iclass 20, count 0 2006.182.08:18:31.29#ibcon#read 5, iclass 20, count 0 2006.182.08:18:31.29#ibcon#about to read 6, iclass 20, count 0 2006.182.08:18:31.29#ibcon#read 6, iclass 20, count 0 2006.182.08:18:31.29#ibcon#end of sib2, iclass 20, count 0 2006.182.08:18:31.29#ibcon#*after write, iclass 20, count 0 2006.182.08:18:31.29#ibcon#*before return 0, iclass 20, count 0 2006.182.08:18:31.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:31.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:18:31.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:18:31.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:18:31.29$vc4f8/vb=3,4 2006.182.08:18:31.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.08:18:31.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.08:18:31.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:31.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:31.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:31.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:31.35#ibcon#enter wrdev, iclass 22, count 2 2006.182.08:18:31.35#ibcon#first serial, iclass 22, count 2 2006.182.08:18:31.35#ibcon#enter sib2, iclass 22, count 2 2006.182.08:18:31.35#ibcon#flushed, iclass 22, count 2 2006.182.08:18:31.35#ibcon#about to write, iclass 22, count 2 2006.182.08:18:31.35#ibcon#wrote, iclass 22, count 2 2006.182.08:18:31.35#ibcon#about to read 3, iclass 22, count 2 2006.182.08:18:31.37#ibcon#read 3, iclass 22, count 2 2006.182.08:18:31.37#ibcon#about to read 4, iclass 22, count 2 2006.182.08:18:31.37#ibcon#read 4, iclass 22, count 2 2006.182.08:18:31.37#ibcon#about to read 5, iclass 22, count 2 2006.182.08:18:31.37#ibcon#read 5, iclass 22, count 2 2006.182.08:18:31.37#ibcon#about to read 6, iclass 22, count 2 2006.182.08:18:31.37#ibcon#read 6, iclass 22, count 2 2006.182.08:18:31.37#ibcon#end of sib2, iclass 22, count 2 2006.182.08:18:31.37#ibcon#*mode == 0, iclass 22, count 2 2006.182.08:18:31.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.08:18:31.37#ibcon#[27=AT03-04\r\n] 2006.182.08:18:31.37#ibcon#*before write, iclass 22, count 2 2006.182.08:18:31.37#ibcon#enter sib2, iclass 22, count 2 2006.182.08:18:31.37#ibcon#flushed, iclass 22, count 2 2006.182.08:18:31.37#ibcon#about to write, iclass 22, count 2 2006.182.08:18:31.37#ibcon#wrote, iclass 22, count 2 2006.182.08:18:31.37#ibcon#about to read 3, iclass 22, count 2 2006.182.08:18:31.40#ibcon#read 3, iclass 22, count 2 2006.182.08:18:31.40#ibcon#about to read 4, iclass 22, count 2 2006.182.08:18:31.40#ibcon#read 4, iclass 22, count 2 2006.182.08:18:31.40#ibcon#about to read 5, iclass 22, count 2 2006.182.08:18:31.40#ibcon#read 5, iclass 22, count 2 2006.182.08:18:31.40#ibcon#about to read 6, iclass 22, count 2 2006.182.08:18:31.40#ibcon#read 6, iclass 22, count 2 2006.182.08:18:31.40#ibcon#end of sib2, iclass 22, count 2 2006.182.08:18:31.40#ibcon#*after write, iclass 22, count 2 2006.182.08:18:31.40#ibcon#*before return 0, iclass 22, count 2 2006.182.08:18:31.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:31.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:18:31.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.08:18:31.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:31.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:31.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:31.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:31.52#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:18:31.52#ibcon#first serial, iclass 22, count 0 2006.182.08:18:31.52#ibcon#enter sib2, iclass 22, count 0 2006.182.08:18:31.52#ibcon#flushed, iclass 22, count 0 2006.182.08:18:31.52#ibcon#about to write, iclass 22, count 0 2006.182.08:18:31.52#ibcon#wrote, iclass 22, count 0 2006.182.08:18:31.52#ibcon#about to read 3, iclass 22, count 0 2006.182.08:18:31.54#ibcon#read 3, iclass 22, count 0 2006.182.08:18:31.54#ibcon#about to read 4, iclass 22, count 0 2006.182.08:18:31.54#ibcon#read 4, iclass 22, count 0 2006.182.08:18:31.54#ibcon#about to read 5, iclass 22, count 0 2006.182.08:18:31.54#ibcon#read 5, iclass 22, count 0 2006.182.08:18:31.54#ibcon#about to read 6, iclass 22, count 0 2006.182.08:18:31.54#ibcon#read 6, iclass 22, count 0 2006.182.08:18:31.54#ibcon#end of sib2, iclass 22, count 0 2006.182.08:18:31.54#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:18:31.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:18:31.54#ibcon#[27=USB\r\n] 2006.182.08:18:31.54#ibcon#*before write, iclass 22, count 0 2006.182.08:18:31.54#ibcon#enter sib2, iclass 22, count 0 2006.182.08:18:31.54#ibcon#flushed, iclass 22, count 0 2006.182.08:18:31.54#ibcon#about to write, iclass 22, count 0 2006.182.08:18:31.54#ibcon#wrote, iclass 22, count 0 2006.182.08:18:31.54#ibcon#about to read 3, iclass 22, count 0 2006.182.08:18:31.57#ibcon#read 3, iclass 22, count 0 2006.182.08:18:31.57#ibcon#about to read 4, iclass 22, count 0 2006.182.08:18:31.57#ibcon#read 4, iclass 22, count 0 2006.182.08:18:31.57#ibcon#about to read 5, iclass 22, count 0 2006.182.08:18:31.57#ibcon#read 5, iclass 22, count 0 2006.182.08:18:31.57#ibcon#about to read 6, iclass 22, count 0 2006.182.08:18:31.57#ibcon#read 6, iclass 22, count 0 2006.182.08:18:31.57#ibcon#end of sib2, iclass 22, count 0 2006.182.08:18:31.57#ibcon#*after write, iclass 22, count 0 2006.182.08:18:31.57#ibcon#*before return 0, iclass 22, count 0 2006.182.08:18:31.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:31.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:18:31.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:18:31.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:18:31.57$vc4f8/vblo=4,712.99 2006.182.08:18:31.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.08:18:31.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.08:18:31.57#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:31.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:31.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:31.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:31.57#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:18:31.57#ibcon#first serial, iclass 24, count 0 2006.182.08:18:31.57#ibcon#enter sib2, iclass 24, count 0 2006.182.08:18:31.57#ibcon#flushed, iclass 24, count 0 2006.182.08:18:31.57#ibcon#about to write, iclass 24, count 0 2006.182.08:18:31.57#ibcon#wrote, iclass 24, count 0 2006.182.08:18:31.57#ibcon#about to read 3, iclass 24, count 0 2006.182.08:18:31.59#ibcon#read 3, iclass 24, count 0 2006.182.08:18:31.59#ibcon#about to read 4, iclass 24, count 0 2006.182.08:18:31.59#ibcon#read 4, iclass 24, count 0 2006.182.08:18:31.59#ibcon#about to read 5, iclass 24, count 0 2006.182.08:18:31.59#ibcon#read 5, iclass 24, count 0 2006.182.08:18:31.59#ibcon#about to read 6, iclass 24, count 0 2006.182.08:18:31.59#ibcon#read 6, iclass 24, count 0 2006.182.08:18:31.59#ibcon#end of sib2, iclass 24, count 0 2006.182.08:18:31.59#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:18:31.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:18:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:18:31.59#ibcon#*before write, iclass 24, count 0 2006.182.08:18:31.59#ibcon#enter sib2, iclass 24, count 0 2006.182.08:18:31.59#ibcon#flushed, iclass 24, count 0 2006.182.08:18:31.59#ibcon#about to write, iclass 24, count 0 2006.182.08:18:31.59#ibcon#wrote, iclass 24, count 0 2006.182.08:18:31.59#ibcon#about to read 3, iclass 24, count 0 2006.182.08:18:31.62#abcon#<5=/07 0.9 2.6 27.78 821002.9\r\n> 2006.182.08:18:31.63#ibcon#read 3, iclass 24, count 0 2006.182.08:18:31.63#ibcon#about to read 4, iclass 24, count 0 2006.182.08:18:31.63#ibcon#read 4, iclass 24, count 0 2006.182.08:18:31.63#ibcon#about to read 5, iclass 24, count 0 2006.182.08:18:31.63#ibcon#read 5, iclass 24, count 0 2006.182.08:18:31.63#ibcon#about to read 6, iclass 24, count 0 2006.182.08:18:31.63#ibcon#read 6, iclass 24, count 0 2006.182.08:18:31.63#ibcon#end of sib2, iclass 24, count 0 2006.182.08:18:31.63#ibcon#*after write, iclass 24, count 0 2006.182.08:18:31.63#ibcon#*before return 0, iclass 24, count 0 2006.182.08:18:31.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:31.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:18:31.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:18:31.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:18:31.63$vc4f8/vb=4,4 2006.182.08:18:31.63#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.08:18:31.63#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.08:18:31.63#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:31.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:18:31.64#abcon#{5=INTERFACE CLEAR} 2006.182.08:18:31.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:18:31.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:18:31.69#ibcon#enter wrdev, iclass 29, count 2 2006.182.08:18:31.69#ibcon#first serial, iclass 29, count 2 2006.182.08:18:31.69#ibcon#enter sib2, iclass 29, count 2 2006.182.08:18:31.69#ibcon#flushed, iclass 29, count 2 2006.182.08:18:31.69#ibcon#about to write, iclass 29, count 2 2006.182.08:18:31.69#ibcon#wrote, iclass 29, count 2 2006.182.08:18:31.69#ibcon#about to read 3, iclass 29, count 2 2006.182.08:18:31.70#abcon#[5=S1D000X0/0*\r\n] 2006.182.08:18:31.71#ibcon#read 3, iclass 29, count 2 2006.182.08:18:31.71#ibcon#about to read 4, iclass 29, count 2 2006.182.08:18:31.71#ibcon#read 4, iclass 29, count 2 2006.182.08:18:31.71#ibcon#about to read 5, iclass 29, count 2 2006.182.08:18:31.71#ibcon#read 5, iclass 29, count 2 2006.182.08:18:31.71#ibcon#about to read 6, iclass 29, count 2 2006.182.08:18:31.71#ibcon#read 6, iclass 29, count 2 2006.182.08:18:31.71#ibcon#end of sib2, iclass 29, count 2 2006.182.08:18:31.71#ibcon#*mode == 0, iclass 29, count 2 2006.182.08:18:31.71#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.08:18:31.71#ibcon#[27=AT04-04\r\n] 2006.182.08:18:31.71#ibcon#*before write, iclass 29, count 2 2006.182.08:18:31.71#ibcon#enter sib2, iclass 29, count 2 2006.182.08:18:31.71#ibcon#flushed, iclass 29, count 2 2006.182.08:18:31.71#ibcon#about to write, iclass 29, count 2 2006.182.08:18:31.71#ibcon#wrote, iclass 29, count 2 2006.182.08:18:31.71#ibcon#about to read 3, iclass 29, count 2 2006.182.08:18:31.74#ibcon#read 3, iclass 29, count 2 2006.182.08:18:31.74#ibcon#about to read 4, iclass 29, count 2 2006.182.08:18:31.74#ibcon#read 4, iclass 29, count 2 2006.182.08:18:31.74#ibcon#about to read 5, iclass 29, count 2 2006.182.08:18:31.74#ibcon#read 5, iclass 29, count 2 2006.182.08:18:31.74#ibcon#about to read 6, iclass 29, count 2 2006.182.08:18:31.74#ibcon#read 6, iclass 29, count 2 2006.182.08:18:31.74#ibcon#end of sib2, iclass 29, count 2 2006.182.08:18:31.74#ibcon#*after write, iclass 29, count 2 2006.182.08:18:31.74#ibcon#*before return 0, iclass 29, count 2 2006.182.08:18:31.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:18:31.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:18:31.74#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.08:18:31.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:31.74#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:18:31.86#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:18:31.86#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:18:31.86#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:18:31.86#ibcon#first serial, iclass 29, count 0 2006.182.08:18:31.86#ibcon#enter sib2, iclass 29, count 0 2006.182.08:18:31.86#ibcon#flushed, iclass 29, count 0 2006.182.08:18:31.86#ibcon#about to write, iclass 29, count 0 2006.182.08:18:31.86#ibcon#wrote, iclass 29, count 0 2006.182.08:18:31.86#ibcon#about to read 3, iclass 29, count 0 2006.182.08:18:31.88#ibcon#read 3, iclass 29, count 0 2006.182.08:18:31.88#ibcon#about to read 4, iclass 29, count 0 2006.182.08:18:31.88#ibcon#read 4, iclass 29, count 0 2006.182.08:18:31.88#ibcon#about to read 5, iclass 29, count 0 2006.182.08:18:31.88#ibcon#read 5, iclass 29, count 0 2006.182.08:18:31.88#ibcon#about to read 6, iclass 29, count 0 2006.182.08:18:31.88#ibcon#read 6, iclass 29, count 0 2006.182.08:18:31.88#ibcon#end of sib2, iclass 29, count 0 2006.182.08:18:31.88#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:18:31.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:18:31.88#ibcon#[27=USB\r\n] 2006.182.08:18:31.88#ibcon#*before write, iclass 29, count 0 2006.182.08:18:31.88#ibcon#enter sib2, iclass 29, count 0 2006.182.08:18:31.88#ibcon#flushed, iclass 29, count 0 2006.182.08:18:31.88#ibcon#about to write, iclass 29, count 0 2006.182.08:18:31.88#ibcon#wrote, iclass 29, count 0 2006.182.08:18:31.88#ibcon#about to read 3, iclass 29, count 0 2006.182.08:18:31.91#ibcon#read 3, iclass 29, count 0 2006.182.08:18:31.91#ibcon#about to read 4, iclass 29, count 0 2006.182.08:18:31.91#ibcon#read 4, iclass 29, count 0 2006.182.08:18:31.91#ibcon#about to read 5, iclass 29, count 0 2006.182.08:18:31.91#ibcon#read 5, iclass 29, count 0 2006.182.08:18:31.91#ibcon#about to read 6, iclass 29, count 0 2006.182.08:18:31.91#ibcon#read 6, iclass 29, count 0 2006.182.08:18:31.91#ibcon#end of sib2, iclass 29, count 0 2006.182.08:18:31.91#ibcon#*after write, iclass 29, count 0 2006.182.08:18:31.91#ibcon#*before return 0, iclass 29, count 0 2006.182.08:18:31.91#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:18:31.91#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:18:31.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:18:31.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:18:31.91$vc4f8/vblo=5,744.99 2006.182.08:18:31.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.08:18:31.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.08:18:31.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:31.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:31.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:31.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:31.91#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:18:31.91#ibcon#first serial, iclass 32, count 0 2006.182.08:18:31.91#ibcon#enter sib2, iclass 32, count 0 2006.182.08:18:31.91#ibcon#flushed, iclass 32, count 0 2006.182.08:18:31.91#ibcon#about to write, iclass 32, count 0 2006.182.08:18:31.91#ibcon#wrote, iclass 32, count 0 2006.182.08:18:31.91#ibcon#about to read 3, iclass 32, count 0 2006.182.08:18:31.93#ibcon#read 3, iclass 32, count 0 2006.182.08:18:31.93#ibcon#about to read 4, iclass 32, count 0 2006.182.08:18:31.93#ibcon#read 4, iclass 32, count 0 2006.182.08:18:31.93#ibcon#about to read 5, iclass 32, count 0 2006.182.08:18:31.93#ibcon#read 5, iclass 32, count 0 2006.182.08:18:31.93#ibcon#about to read 6, iclass 32, count 0 2006.182.08:18:31.93#ibcon#read 6, iclass 32, count 0 2006.182.08:18:31.93#ibcon#end of sib2, iclass 32, count 0 2006.182.08:18:31.93#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:18:31.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:18:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:18:31.93#ibcon#*before write, iclass 32, count 0 2006.182.08:18:31.93#ibcon#enter sib2, iclass 32, count 0 2006.182.08:18:31.93#ibcon#flushed, iclass 32, count 0 2006.182.08:18:31.93#ibcon#about to write, iclass 32, count 0 2006.182.08:18:31.93#ibcon#wrote, iclass 32, count 0 2006.182.08:18:31.93#ibcon#about to read 3, iclass 32, count 0 2006.182.08:18:31.97#ibcon#read 3, iclass 32, count 0 2006.182.08:18:31.97#ibcon#about to read 4, iclass 32, count 0 2006.182.08:18:31.97#ibcon#read 4, iclass 32, count 0 2006.182.08:18:31.97#ibcon#about to read 5, iclass 32, count 0 2006.182.08:18:31.97#ibcon#read 5, iclass 32, count 0 2006.182.08:18:31.97#ibcon#about to read 6, iclass 32, count 0 2006.182.08:18:31.97#ibcon#read 6, iclass 32, count 0 2006.182.08:18:31.97#ibcon#end of sib2, iclass 32, count 0 2006.182.08:18:31.97#ibcon#*after write, iclass 32, count 0 2006.182.08:18:31.97#ibcon#*before return 0, iclass 32, count 0 2006.182.08:18:31.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:31.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:18:31.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:18:31.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:18:31.97$vc4f8/vb=5,4 2006.182.08:18:31.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.08:18:31.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.08:18:31.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:31.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:32.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:32.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:32.03#ibcon#enter wrdev, iclass 34, count 2 2006.182.08:18:32.03#ibcon#first serial, iclass 34, count 2 2006.182.08:18:32.03#ibcon#enter sib2, iclass 34, count 2 2006.182.08:18:32.03#ibcon#flushed, iclass 34, count 2 2006.182.08:18:32.03#ibcon#about to write, iclass 34, count 2 2006.182.08:18:32.03#ibcon#wrote, iclass 34, count 2 2006.182.08:18:32.03#ibcon#about to read 3, iclass 34, count 2 2006.182.08:18:32.05#ibcon#read 3, iclass 34, count 2 2006.182.08:18:32.05#ibcon#about to read 4, iclass 34, count 2 2006.182.08:18:32.05#ibcon#read 4, iclass 34, count 2 2006.182.08:18:32.05#ibcon#about to read 5, iclass 34, count 2 2006.182.08:18:32.05#ibcon#read 5, iclass 34, count 2 2006.182.08:18:32.05#ibcon#about to read 6, iclass 34, count 2 2006.182.08:18:32.05#ibcon#read 6, iclass 34, count 2 2006.182.08:18:32.05#ibcon#end of sib2, iclass 34, count 2 2006.182.08:18:32.05#ibcon#*mode == 0, iclass 34, count 2 2006.182.08:18:32.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.08:18:32.05#ibcon#[27=AT05-04\r\n] 2006.182.08:18:32.05#ibcon#*before write, iclass 34, count 2 2006.182.08:18:32.05#ibcon#enter sib2, iclass 34, count 2 2006.182.08:18:32.05#ibcon#flushed, iclass 34, count 2 2006.182.08:18:32.05#ibcon#about to write, iclass 34, count 2 2006.182.08:18:32.05#ibcon#wrote, iclass 34, count 2 2006.182.08:18:32.05#ibcon#about to read 3, iclass 34, count 2 2006.182.08:18:32.08#ibcon#read 3, iclass 34, count 2 2006.182.08:18:32.08#ibcon#about to read 4, iclass 34, count 2 2006.182.08:18:32.08#ibcon#read 4, iclass 34, count 2 2006.182.08:18:32.08#ibcon#about to read 5, iclass 34, count 2 2006.182.08:18:32.08#ibcon#read 5, iclass 34, count 2 2006.182.08:18:32.08#ibcon#about to read 6, iclass 34, count 2 2006.182.08:18:32.08#ibcon#read 6, iclass 34, count 2 2006.182.08:18:32.08#ibcon#end of sib2, iclass 34, count 2 2006.182.08:18:32.08#ibcon#*after write, iclass 34, count 2 2006.182.08:18:32.08#ibcon#*before return 0, iclass 34, count 2 2006.182.08:18:32.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:32.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:18:32.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.08:18:32.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:32.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:32.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:32.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:32.20#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:18:32.20#ibcon#first serial, iclass 34, count 0 2006.182.08:18:32.20#ibcon#enter sib2, iclass 34, count 0 2006.182.08:18:32.20#ibcon#flushed, iclass 34, count 0 2006.182.08:18:32.20#ibcon#about to write, iclass 34, count 0 2006.182.08:18:32.20#ibcon#wrote, iclass 34, count 0 2006.182.08:18:32.20#ibcon#about to read 3, iclass 34, count 0 2006.182.08:18:32.22#ibcon#read 3, iclass 34, count 0 2006.182.08:18:32.22#ibcon#about to read 4, iclass 34, count 0 2006.182.08:18:32.22#ibcon#read 4, iclass 34, count 0 2006.182.08:18:32.22#ibcon#about to read 5, iclass 34, count 0 2006.182.08:18:32.22#ibcon#read 5, iclass 34, count 0 2006.182.08:18:32.22#ibcon#about to read 6, iclass 34, count 0 2006.182.08:18:32.22#ibcon#read 6, iclass 34, count 0 2006.182.08:18:32.22#ibcon#end of sib2, iclass 34, count 0 2006.182.08:18:32.22#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:18:32.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:18:32.22#ibcon#[27=USB\r\n] 2006.182.08:18:32.22#ibcon#*before write, iclass 34, count 0 2006.182.08:18:32.22#ibcon#enter sib2, iclass 34, count 0 2006.182.08:18:32.22#ibcon#flushed, iclass 34, count 0 2006.182.08:18:32.22#ibcon#about to write, iclass 34, count 0 2006.182.08:18:32.22#ibcon#wrote, iclass 34, count 0 2006.182.08:18:32.22#ibcon#about to read 3, iclass 34, count 0 2006.182.08:18:32.25#ibcon#read 3, iclass 34, count 0 2006.182.08:18:32.25#ibcon#about to read 4, iclass 34, count 0 2006.182.08:18:32.25#ibcon#read 4, iclass 34, count 0 2006.182.08:18:32.25#ibcon#about to read 5, iclass 34, count 0 2006.182.08:18:32.25#ibcon#read 5, iclass 34, count 0 2006.182.08:18:32.25#ibcon#about to read 6, iclass 34, count 0 2006.182.08:18:32.25#ibcon#read 6, iclass 34, count 0 2006.182.08:18:32.25#ibcon#end of sib2, iclass 34, count 0 2006.182.08:18:32.25#ibcon#*after write, iclass 34, count 0 2006.182.08:18:32.25#ibcon#*before return 0, iclass 34, count 0 2006.182.08:18:32.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:32.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:18:32.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:18:32.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:18:32.25$vc4f8/vblo=6,752.99 2006.182.08:18:32.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.08:18:32.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.08:18:32.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:18:32.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:32.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:32.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:32.25#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:18:32.25#ibcon#first serial, iclass 36, count 0 2006.182.08:18:32.25#ibcon#enter sib2, iclass 36, count 0 2006.182.08:18:32.25#ibcon#flushed, iclass 36, count 0 2006.182.08:18:32.25#ibcon#about to write, iclass 36, count 0 2006.182.08:18:32.25#ibcon#wrote, iclass 36, count 0 2006.182.08:18:32.25#ibcon#about to read 3, iclass 36, count 0 2006.182.08:18:32.27#ibcon#read 3, iclass 36, count 0 2006.182.08:18:32.27#ibcon#about to read 4, iclass 36, count 0 2006.182.08:18:32.27#ibcon#read 4, iclass 36, count 0 2006.182.08:18:32.27#ibcon#about to read 5, iclass 36, count 0 2006.182.08:18:32.27#ibcon#read 5, iclass 36, count 0 2006.182.08:18:32.27#ibcon#about to read 6, iclass 36, count 0 2006.182.08:18:32.27#ibcon#read 6, iclass 36, count 0 2006.182.08:18:32.27#ibcon#end of sib2, iclass 36, count 0 2006.182.08:18:32.27#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:18:32.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:18:32.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:18:32.27#ibcon#*before write, iclass 36, count 0 2006.182.08:18:32.27#ibcon#enter sib2, iclass 36, count 0 2006.182.08:18:32.27#ibcon#flushed, iclass 36, count 0 2006.182.08:18:32.27#ibcon#about to write, iclass 36, count 0 2006.182.08:18:32.27#ibcon#wrote, iclass 36, count 0 2006.182.08:18:32.27#ibcon#about to read 3, iclass 36, count 0 2006.182.08:18:32.31#ibcon#read 3, iclass 36, count 0 2006.182.08:18:32.31#ibcon#about to read 4, iclass 36, count 0 2006.182.08:18:32.31#ibcon#read 4, iclass 36, count 0 2006.182.08:18:32.31#ibcon#about to read 5, iclass 36, count 0 2006.182.08:18:32.31#ibcon#read 5, iclass 36, count 0 2006.182.08:18:32.31#ibcon#about to read 6, iclass 36, count 0 2006.182.08:18:32.31#ibcon#read 6, iclass 36, count 0 2006.182.08:18:32.31#ibcon#end of sib2, iclass 36, count 0 2006.182.08:18:32.31#ibcon#*after write, iclass 36, count 0 2006.182.08:18:32.31#ibcon#*before return 0, iclass 36, count 0 2006.182.08:18:32.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:32.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:18:32.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:18:32.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:18:32.31$vc4f8/vb=6,4 2006.182.08:18:32.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.08:18:32.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.08:18:32.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:18:32.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:32.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:32.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:32.37#ibcon#enter wrdev, iclass 38, count 2 2006.182.08:18:32.37#ibcon#first serial, iclass 38, count 2 2006.182.08:18:32.37#ibcon#enter sib2, iclass 38, count 2 2006.182.08:18:32.37#ibcon#flushed, iclass 38, count 2 2006.182.08:18:32.37#ibcon#about to write, iclass 38, count 2 2006.182.08:18:32.37#ibcon#wrote, iclass 38, count 2 2006.182.08:18:32.37#ibcon#about to read 3, iclass 38, count 2 2006.182.08:18:32.39#ibcon#read 3, iclass 38, count 2 2006.182.08:18:32.39#ibcon#about to read 4, iclass 38, count 2 2006.182.08:18:32.39#ibcon#read 4, iclass 38, count 2 2006.182.08:18:32.39#ibcon#about to read 5, iclass 38, count 2 2006.182.08:18:32.39#ibcon#read 5, iclass 38, count 2 2006.182.08:18:32.39#ibcon#about to read 6, iclass 38, count 2 2006.182.08:18:32.39#ibcon#read 6, iclass 38, count 2 2006.182.08:18:32.39#ibcon#end of sib2, iclass 38, count 2 2006.182.08:18:32.39#ibcon#*mode == 0, iclass 38, count 2 2006.182.08:18:32.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.08:18:32.39#ibcon#[27=AT06-04\r\n] 2006.182.08:18:32.39#ibcon#*before write, iclass 38, count 2 2006.182.08:18:32.39#ibcon#enter sib2, iclass 38, count 2 2006.182.08:18:32.39#ibcon#flushed, iclass 38, count 2 2006.182.08:18:32.39#ibcon#about to write, iclass 38, count 2 2006.182.08:18:32.39#ibcon#wrote, iclass 38, count 2 2006.182.08:18:32.39#ibcon#about to read 3, iclass 38, count 2 2006.182.08:18:32.42#ibcon#read 3, iclass 38, count 2 2006.182.08:18:32.42#ibcon#about to read 4, iclass 38, count 2 2006.182.08:18:32.42#ibcon#read 4, iclass 38, count 2 2006.182.08:18:32.42#ibcon#about to read 5, iclass 38, count 2 2006.182.08:18:32.42#ibcon#read 5, iclass 38, count 2 2006.182.08:18:32.42#ibcon#about to read 6, iclass 38, count 2 2006.182.08:18:32.42#ibcon#read 6, iclass 38, count 2 2006.182.08:18:32.42#ibcon#end of sib2, iclass 38, count 2 2006.182.08:18:32.42#ibcon#*after write, iclass 38, count 2 2006.182.08:18:32.42#ibcon#*before return 0, iclass 38, count 2 2006.182.08:18:32.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:32.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:18:32.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.08:18:32.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:18:32.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:32.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:32.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:32.54#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:18:32.54#ibcon#first serial, iclass 38, count 0 2006.182.08:18:32.54#ibcon#enter sib2, iclass 38, count 0 2006.182.08:18:32.54#ibcon#flushed, iclass 38, count 0 2006.182.08:18:32.54#ibcon#about to write, iclass 38, count 0 2006.182.08:18:32.54#ibcon#wrote, iclass 38, count 0 2006.182.08:18:32.54#ibcon#about to read 3, iclass 38, count 0 2006.182.08:18:32.56#ibcon#read 3, iclass 38, count 0 2006.182.08:18:32.56#ibcon#about to read 4, iclass 38, count 0 2006.182.08:18:32.56#ibcon#read 4, iclass 38, count 0 2006.182.08:18:32.56#ibcon#about to read 5, iclass 38, count 0 2006.182.08:18:32.56#ibcon#read 5, iclass 38, count 0 2006.182.08:18:32.56#ibcon#about to read 6, iclass 38, count 0 2006.182.08:18:32.56#ibcon#read 6, iclass 38, count 0 2006.182.08:18:32.56#ibcon#end of sib2, iclass 38, count 0 2006.182.08:18:32.56#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:18:32.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:18:32.56#ibcon#[27=USB\r\n] 2006.182.08:18:32.56#ibcon#*before write, iclass 38, count 0 2006.182.08:18:32.56#ibcon#enter sib2, iclass 38, count 0 2006.182.08:18:32.56#ibcon#flushed, iclass 38, count 0 2006.182.08:18:32.56#ibcon#about to write, iclass 38, count 0 2006.182.08:18:32.56#ibcon#wrote, iclass 38, count 0 2006.182.08:18:32.56#ibcon#about to read 3, iclass 38, count 0 2006.182.08:18:32.59#ibcon#read 3, iclass 38, count 0 2006.182.08:18:32.59#ibcon#about to read 4, iclass 38, count 0 2006.182.08:18:32.59#ibcon#read 4, iclass 38, count 0 2006.182.08:18:32.59#ibcon#about to read 5, iclass 38, count 0 2006.182.08:18:32.59#ibcon#read 5, iclass 38, count 0 2006.182.08:18:32.59#ibcon#about to read 6, iclass 38, count 0 2006.182.08:18:32.59#ibcon#read 6, iclass 38, count 0 2006.182.08:18:32.59#ibcon#end of sib2, iclass 38, count 0 2006.182.08:18:32.59#ibcon#*after write, iclass 38, count 0 2006.182.08:18:32.59#ibcon#*before return 0, iclass 38, count 0 2006.182.08:18:32.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:32.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:18:32.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:18:32.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:18:32.59$vc4f8/vabw=wide 2006.182.08:18:32.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.08:18:32.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.08:18:32.59#ibcon#ireg 8 cls_cnt 0 2006.182.08:18:32.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:32.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:32.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:32.59#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:18:32.59#ibcon#first serial, iclass 40, count 0 2006.182.08:18:32.59#ibcon#enter sib2, iclass 40, count 0 2006.182.08:18:32.59#ibcon#flushed, iclass 40, count 0 2006.182.08:18:32.59#ibcon#about to write, iclass 40, count 0 2006.182.08:18:32.59#ibcon#wrote, iclass 40, count 0 2006.182.08:18:32.59#ibcon#about to read 3, iclass 40, count 0 2006.182.08:18:32.61#ibcon#read 3, iclass 40, count 0 2006.182.08:18:32.61#ibcon#about to read 4, iclass 40, count 0 2006.182.08:18:32.61#ibcon#read 4, iclass 40, count 0 2006.182.08:18:32.61#ibcon#about to read 5, iclass 40, count 0 2006.182.08:18:32.61#ibcon#read 5, iclass 40, count 0 2006.182.08:18:32.61#ibcon#about to read 6, iclass 40, count 0 2006.182.08:18:32.61#ibcon#read 6, iclass 40, count 0 2006.182.08:18:32.61#ibcon#end of sib2, iclass 40, count 0 2006.182.08:18:32.61#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:18:32.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:18:32.61#ibcon#[25=BW32\r\n] 2006.182.08:18:32.61#ibcon#*before write, iclass 40, count 0 2006.182.08:18:32.61#ibcon#enter sib2, iclass 40, count 0 2006.182.08:18:32.61#ibcon#flushed, iclass 40, count 0 2006.182.08:18:32.61#ibcon#about to write, iclass 40, count 0 2006.182.08:18:32.61#ibcon#wrote, iclass 40, count 0 2006.182.08:18:32.61#ibcon#about to read 3, iclass 40, count 0 2006.182.08:18:32.64#ibcon#read 3, iclass 40, count 0 2006.182.08:18:32.64#ibcon#about to read 4, iclass 40, count 0 2006.182.08:18:32.64#ibcon#read 4, iclass 40, count 0 2006.182.08:18:32.64#ibcon#about to read 5, iclass 40, count 0 2006.182.08:18:32.64#ibcon#read 5, iclass 40, count 0 2006.182.08:18:32.64#ibcon#about to read 6, iclass 40, count 0 2006.182.08:18:32.64#ibcon#read 6, iclass 40, count 0 2006.182.08:18:32.64#ibcon#end of sib2, iclass 40, count 0 2006.182.08:18:32.64#ibcon#*after write, iclass 40, count 0 2006.182.08:18:32.64#ibcon#*before return 0, iclass 40, count 0 2006.182.08:18:32.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:32.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:18:32.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:18:32.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:18:32.64$vc4f8/vbbw=wide 2006.182.08:18:32.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.08:18:32.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.08:18:32.64#ibcon#ireg 8 cls_cnt 0 2006.182.08:18:32.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:18:32.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:18:32.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:18:32.71#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:18:32.71#ibcon#first serial, iclass 4, count 0 2006.182.08:18:32.71#ibcon#enter sib2, iclass 4, count 0 2006.182.08:18:32.71#ibcon#flushed, iclass 4, count 0 2006.182.08:18:32.71#ibcon#about to write, iclass 4, count 0 2006.182.08:18:32.71#ibcon#wrote, iclass 4, count 0 2006.182.08:18:32.71#ibcon#about to read 3, iclass 4, count 0 2006.182.08:18:32.73#ibcon#read 3, iclass 4, count 0 2006.182.08:18:32.73#ibcon#about to read 4, iclass 4, count 0 2006.182.08:18:32.73#ibcon#read 4, iclass 4, count 0 2006.182.08:18:32.73#ibcon#about to read 5, iclass 4, count 0 2006.182.08:18:32.73#ibcon#read 5, iclass 4, count 0 2006.182.08:18:32.73#ibcon#about to read 6, iclass 4, count 0 2006.182.08:18:32.73#ibcon#read 6, iclass 4, count 0 2006.182.08:18:32.73#ibcon#end of sib2, iclass 4, count 0 2006.182.08:18:32.73#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:18:32.73#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:18:32.73#ibcon#[27=BW32\r\n] 2006.182.08:18:32.73#ibcon#*before write, iclass 4, count 0 2006.182.08:18:32.73#ibcon#enter sib2, iclass 4, count 0 2006.182.08:18:32.73#ibcon#flushed, iclass 4, count 0 2006.182.08:18:32.73#ibcon#about to write, iclass 4, count 0 2006.182.08:18:32.73#ibcon#wrote, iclass 4, count 0 2006.182.08:18:32.73#ibcon#about to read 3, iclass 4, count 0 2006.182.08:18:32.76#ibcon#read 3, iclass 4, count 0 2006.182.08:18:32.76#ibcon#about to read 4, iclass 4, count 0 2006.182.08:18:32.76#ibcon#read 4, iclass 4, count 0 2006.182.08:18:32.76#ibcon#about to read 5, iclass 4, count 0 2006.182.08:18:32.76#ibcon#read 5, iclass 4, count 0 2006.182.08:18:32.76#ibcon#about to read 6, iclass 4, count 0 2006.182.08:18:32.76#ibcon#read 6, iclass 4, count 0 2006.182.08:18:32.76#ibcon#end of sib2, iclass 4, count 0 2006.182.08:18:32.76#ibcon#*after write, iclass 4, count 0 2006.182.08:18:32.76#ibcon#*before return 0, iclass 4, count 0 2006.182.08:18:32.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:18:32.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:18:32.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:18:32.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:18:32.76$4f8m12a/ifd4f 2006.182.08:18:32.76$ifd4f/lo= 2006.182.08:18:32.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:18:32.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:18:32.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:18:32.76$ifd4f/patch= 2006.182.08:18:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:18:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:18:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:18:32.76$4f8m12a/"form=m,16.000,1:2 2006.182.08:18:32.76$4f8m12a/"tpicd 2006.182.08:18:32.76$4f8m12a/echo=off 2006.182.08:18:32.76$4f8m12a/xlog=off 2006.182.08:18:32.76:!2006.182.08:20:10 2006.182.08:18:39.14#trakl#Source acquired 2006.182.08:18:39.14#flagr#flagr/antenna,acquired 2006.182.08:20:10.00:preob 2006.182.08:20:10.13/onsource/TRACKING 2006.182.08:20:10.13:!2006.182.08:20:20 2006.182.08:20:20.00:data_valid=on 2006.182.08:20:20.00:midob 2006.182.08:20:21.13/onsource/TRACKING 2006.182.08:20:21.13/wx/27.76,1002.8,82 2006.182.08:20:21.22/cable/+6.4625E-03 2006.182.08:20:22.31/va/01,08,usb,yes,28,30 2006.182.08:20:22.31/va/02,07,usb,yes,28,30 2006.182.08:20:22.31/va/03,06,usb,yes,30,30 2006.182.08:20:22.31/va/04,07,usb,yes,29,31 2006.182.08:20:22.31/va/05,07,usb,yes,30,32 2006.182.08:20:22.31/va/06,06,usb,yes,29,29 2006.182.08:20:22.31/va/07,06,usb,yes,30,29 2006.182.08:20:22.31/va/08,07,usb,yes,28,28 2006.182.08:20:22.54/valo/01,532.99,yes,locked 2006.182.08:20:22.54/valo/02,572.99,yes,locked 2006.182.08:20:22.54/valo/03,672.99,yes,locked 2006.182.08:20:22.54/valo/04,832.99,yes,locked 2006.182.08:20:22.54/valo/05,652.99,yes,locked 2006.182.08:20:22.54/valo/06,772.99,yes,locked 2006.182.08:20:22.54/valo/07,832.99,yes,locked 2006.182.08:20:22.54/valo/08,852.99,yes,locked 2006.182.08:20:23.63/vb/01,04,usb,yes,29,27 2006.182.08:20:23.63/vb/02,04,usb,yes,30,32 2006.182.08:20:23.63/vb/03,04,usb,yes,27,30 2006.182.08:20:23.63/vb/04,04,usb,yes,28,28 2006.182.08:20:23.63/vb/05,04,usb,yes,26,30 2006.182.08:20:23.63/vb/06,04,usb,yes,27,30 2006.182.08:20:23.63/vb/07,04,usb,yes,29,29 2006.182.08:20:23.63/vb/08,04,usb,yes,27,30 2006.182.08:20:23.86/vblo/01,632.99,yes,locked 2006.182.08:20:23.86/vblo/02,640.99,yes,locked 2006.182.08:20:23.86/vblo/03,656.99,yes,locked 2006.182.08:20:23.86/vblo/04,712.99,yes,locked 2006.182.08:20:23.86/vblo/05,744.99,yes,locked 2006.182.08:20:23.86/vblo/06,752.99,yes,locked 2006.182.08:20:23.86/vblo/07,734.99,yes,locked 2006.182.08:20:23.86/vblo/08,744.99,yes,locked 2006.182.08:20:24.01/vabw/8 2006.182.08:20:24.16/vbbw/8 2006.182.08:20:24.25/xfe/off,on,15.2 2006.182.08:20:24.63/ifatt/23,28,28,28 2006.182.08:20:25.08/fmout-gps/S +3.52E-07 2006.182.08:20:25.12:!2006.182.08:21:20 2006.182.08:21:20.00:data_valid=off 2006.182.08:21:20.00:postob 2006.182.08:21:20.09/cable/+6.4619E-03 2006.182.08:21:20.09/wx/27.75,1002.9,80 2006.182.08:21:21.08/fmout-gps/S +3.52E-07 2006.182.08:21:21.08:scan_name=182-0823,k06182,60 2006.182.08:21:21.09:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.182.08:21:21.14#flagr#flagr/antenna,new-source 2006.182.08:21:22.14:checkk5 2006.182.08:21:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:21:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:21:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:21:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:21:24.02/chk_obsdata//k5ts1/T1820820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:21:24.39/chk_obsdata//k5ts2/T1820820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:21:24.76/chk_obsdata//k5ts3/T1820820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:21:25.12/chk_obsdata//k5ts4/T1820820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:21:25.83/k5log//k5ts1_log_newline 2006.182.08:21:26.52/k5log//k5ts2_log_newline 2006.182.08:21:27.21/k5log//k5ts3_log_newline 2006.182.08:21:27.90/k5log//k5ts4_log_newline 2006.182.08:21:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:21:27.93:4f8m12a=3 2006.182.08:21:27.93$4f8m12a/echo=on 2006.182.08:21:27.93$4f8m12a/pcalon 2006.182.08:21:27.93$pcalon/"no phase cal control is implemented here 2006.182.08:21:27.93$4f8m12a/"tpicd=stop 2006.182.08:21:27.93$4f8m12a/vc4f8 2006.182.08:21:27.93$vc4f8/valo=1,532.99 2006.182.08:21:27.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.08:21:27.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.08:21:27.93#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:27.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:27.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:27.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:27.93#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:21:27.93#ibcon#first serial, iclass 3, count 0 2006.182.08:21:27.93#ibcon#enter sib2, iclass 3, count 0 2006.182.08:21:27.93#ibcon#flushed, iclass 3, count 0 2006.182.08:21:27.93#ibcon#about to write, iclass 3, count 0 2006.182.08:21:27.93#ibcon#wrote, iclass 3, count 0 2006.182.08:21:27.93#ibcon#about to read 3, iclass 3, count 0 2006.182.08:21:27.97#ibcon#read 3, iclass 3, count 0 2006.182.08:21:27.97#ibcon#about to read 4, iclass 3, count 0 2006.182.08:21:27.97#ibcon#read 4, iclass 3, count 0 2006.182.08:21:27.97#ibcon#about to read 5, iclass 3, count 0 2006.182.08:21:27.97#ibcon#read 5, iclass 3, count 0 2006.182.08:21:27.97#ibcon#about to read 6, iclass 3, count 0 2006.182.08:21:27.97#ibcon#read 6, iclass 3, count 0 2006.182.08:21:27.97#ibcon#end of sib2, iclass 3, count 0 2006.182.08:21:27.97#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:21:27.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:21:27.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:21:27.97#ibcon#*before write, iclass 3, count 0 2006.182.08:21:27.97#ibcon#enter sib2, iclass 3, count 0 2006.182.08:21:27.97#ibcon#flushed, iclass 3, count 0 2006.182.08:21:27.97#ibcon#about to write, iclass 3, count 0 2006.182.08:21:27.97#ibcon#wrote, iclass 3, count 0 2006.182.08:21:27.97#ibcon#about to read 3, iclass 3, count 0 2006.182.08:21:28.02#ibcon#read 3, iclass 3, count 0 2006.182.08:21:28.02#ibcon#about to read 4, iclass 3, count 0 2006.182.08:21:28.02#ibcon#read 4, iclass 3, count 0 2006.182.08:21:28.02#ibcon#about to read 5, iclass 3, count 0 2006.182.08:21:28.02#ibcon#read 5, iclass 3, count 0 2006.182.08:21:28.02#ibcon#about to read 6, iclass 3, count 0 2006.182.08:21:28.02#ibcon#read 6, iclass 3, count 0 2006.182.08:21:28.02#ibcon#end of sib2, iclass 3, count 0 2006.182.08:21:28.02#ibcon#*after write, iclass 3, count 0 2006.182.08:21:28.02#ibcon#*before return 0, iclass 3, count 0 2006.182.08:21:28.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:28.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:28.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:21:28.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:21:28.02$vc4f8/va=1,8 2006.182.08:21:28.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.08:21:28.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.08:21:28.02#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:28.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:28.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:28.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:28.02#ibcon#enter wrdev, iclass 5, count 2 2006.182.08:21:28.02#ibcon#first serial, iclass 5, count 2 2006.182.08:21:28.02#ibcon#enter sib2, iclass 5, count 2 2006.182.08:21:28.02#ibcon#flushed, iclass 5, count 2 2006.182.08:21:28.02#ibcon#about to write, iclass 5, count 2 2006.182.08:21:28.02#ibcon#wrote, iclass 5, count 2 2006.182.08:21:28.02#ibcon#about to read 3, iclass 5, count 2 2006.182.08:21:28.04#ibcon#read 3, iclass 5, count 2 2006.182.08:21:28.04#ibcon#about to read 4, iclass 5, count 2 2006.182.08:21:28.04#ibcon#read 4, iclass 5, count 2 2006.182.08:21:28.04#ibcon#about to read 5, iclass 5, count 2 2006.182.08:21:28.04#ibcon#read 5, iclass 5, count 2 2006.182.08:21:28.04#ibcon#about to read 6, iclass 5, count 2 2006.182.08:21:28.04#ibcon#read 6, iclass 5, count 2 2006.182.08:21:28.04#ibcon#end of sib2, iclass 5, count 2 2006.182.08:21:28.04#ibcon#*mode == 0, iclass 5, count 2 2006.182.08:21:28.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.08:21:28.04#ibcon#[25=AT01-08\r\n] 2006.182.08:21:28.04#ibcon#*before write, iclass 5, count 2 2006.182.08:21:28.04#ibcon#enter sib2, iclass 5, count 2 2006.182.08:21:28.04#ibcon#flushed, iclass 5, count 2 2006.182.08:21:28.04#ibcon#about to write, iclass 5, count 2 2006.182.08:21:28.04#ibcon#wrote, iclass 5, count 2 2006.182.08:21:28.04#ibcon#about to read 3, iclass 5, count 2 2006.182.08:21:28.08#ibcon#read 3, iclass 5, count 2 2006.182.08:21:28.08#ibcon#about to read 4, iclass 5, count 2 2006.182.08:21:28.08#ibcon#read 4, iclass 5, count 2 2006.182.08:21:28.08#ibcon#about to read 5, iclass 5, count 2 2006.182.08:21:28.08#ibcon#read 5, iclass 5, count 2 2006.182.08:21:28.08#ibcon#about to read 6, iclass 5, count 2 2006.182.08:21:28.08#ibcon#read 6, iclass 5, count 2 2006.182.08:21:28.08#ibcon#end of sib2, iclass 5, count 2 2006.182.08:21:28.08#ibcon#*after write, iclass 5, count 2 2006.182.08:21:28.08#ibcon#*before return 0, iclass 5, count 2 2006.182.08:21:28.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:28.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:28.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.08:21:28.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:28.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:28.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:28.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:28.20#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:21:28.20#ibcon#first serial, iclass 5, count 0 2006.182.08:21:28.20#ibcon#enter sib2, iclass 5, count 0 2006.182.08:21:28.20#ibcon#flushed, iclass 5, count 0 2006.182.08:21:28.20#ibcon#about to write, iclass 5, count 0 2006.182.08:21:28.20#ibcon#wrote, iclass 5, count 0 2006.182.08:21:28.20#ibcon#about to read 3, iclass 5, count 0 2006.182.08:21:28.22#ibcon#read 3, iclass 5, count 0 2006.182.08:21:28.22#ibcon#about to read 4, iclass 5, count 0 2006.182.08:21:28.22#ibcon#read 4, iclass 5, count 0 2006.182.08:21:28.22#ibcon#about to read 5, iclass 5, count 0 2006.182.08:21:28.22#ibcon#read 5, iclass 5, count 0 2006.182.08:21:28.22#ibcon#about to read 6, iclass 5, count 0 2006.182.08:21:28.22#ibcon#read 6, iclass 5, count 0 2006.182.08:21:28.22#ibcon#end of sib2, iclass 5, count 0 2006.182.08:21:28.22#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:21:28.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:21:28.22#ibcon#[25=USB\r\n] 2006.182.08:21:28.22#ibcon#*before write, iclass 5, count 0 2006.182.08:21:28.22#ibcon#enter sib2, iclass 5, count 0 2006.182.08:21:28.22#ibcon#flushed, iclass 5, count 0 2006.182.08:21:28.22#ibcon#about to write, iclass 5, count 0 2006.182.08:21:28.22#ibcon#wrote, iclass 5, count 0 2006.182.08:21:28.22#ibcon#about to read 3, iclass 5, count 0 2006.182.08:21:28.25#ibcon#read 3, iclass 5, count 0 2006.182.08:21:28.25#ibcon#about to read 4, iclass 5, count 0 2006.182.08:21:28.25#ibcon#read 4, iclass 5, count 0 2006.182.08:21:28.25#ibcon#about to read 5, iclass 5, count 0 2006.182.08:21:28.25#ibcon#read 5, iclass 5, count 0 2006.182.08:21:28.25#ibcon#about to read 6, iclass 5, count 0 2006.182.08:21:28.25#ibcon#read 6, iclass 5, count 0 2006.182.08:21:28.25#ibcon#end of sib2, iclass 5, count 0 2006.182.08:21:28.25#ibcon#*after write, iclass 5, count 0 2006.182.08:21:28.25#ibcon#*before return 0, iclass 5, count 0 2006.182.08:21:28.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:28.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:28.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:21:28.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:21:28.25$vc4f8/valo=2,572.99 2006.182.08:21:28.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.08:21:28.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.08:21:28.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:28.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:28.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:28.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:28.25#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:21:28.25#ibcon#first serial, iclass 7, count 0 2006.182.08:21:28.25#ibcon#enter sib2, iclass 7, count 0 2006.182.08:21:28.25#ibcon#flushed, iclass 7, count 0 2006.182.08:21:28.25#ibcon#about to write, iclass 7, count 0 2006.182.08:21:28.25#ibcon#wrote, iclass 7, count 0 2006.182.08:21:28.25#ibcon#about to read 3, iclass 7, count 0 2006.182.08:21:28.27#ibcon#read 3, iclass 7, count 0 2006.182.08:21:28.27#ibcon#about to read 4, iclass 7, count 0 2006.182.08:21:28.27#ibcon#read 4, iclass 7, count 0 2006.182.08:21:28.27#ibcon#about to read 5, iclass 7, count 0 2006.182.08:21:28.27#ibcon#read 5, iclass 7, count 0 2006.182.08:21:28.27#ibcon#about to read 6, iclass 7, count 0 2006.182.08:21:28.27#ibcon#read 6, iclass 7, count 0 2006.182.08:21:28.27#ibcon#end of sib2, iclass 7, count 0 2006.182.08:21:28.27#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:21:28.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:21:28.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:21:28.27#ibcon#*before write, iclass 7, count 0 2006.182.08:21:28.27#ibcon#enter sib2, iclass 7, count 0 2006.182.08:21:28.27#ibcon#flushed, iclass 7, count 0 2006.182.08:21:28.27#ibcon#about to write, iclass 7, count 0 2006.182.08:21:28.27#ibcon#wrote, iclass 7, count 0 2006.182.08:21:28.27#ibcon#about to read 3, iclass 7, count 0 2006.182.08:21:28.31#ibcon#read 3, iclass 7, count 0 2006.182.08:21:28.31#ibcon#about to read 4, iclass 7, count 0 2006.182.08:21:28.31#ibcon#read 4, iclass 7, count 0 2006.182.08:21:28.31#ibcon#about to read 5, iclass 7, count 0 2006.182.08:21:28.31#ibcon#read 5, iclass 7, count 0 2006.182.08:21:28.31#ibcon#about to read 6, iclass 7, count 0 2006.182.08:21:28.31#ibcon#read 6, iclass 7, count 0 2006.182.08:21:28.31#ibcon#end of sib2, iclass 7, count 0 2006.182.08:21:28.31#ibcon#*after write, iclass 7, count 0 2006.182.08:21:28.31#ibcon#*before return 0, iclass 7, count 0 2006.182.08:21:28.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:28.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:28.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:21:28.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:21:28.31$vc4f8/va=2,7 2006.182.08:21:28.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.08:21:28.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.08:21:28.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:28.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:28.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:28.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:28.37#ibcon#enter wrdev, iclass 11, count 2 2006.182.08:21:28.37#ibcon#first serial, iclass 11, count 2 2006.182.08:21:28.37#ibcon#enter sib2, iclass 11, count 2 2006.182.08:21:28.37#ibcon#flushed, iclass 11, count 2 2006.182.08:21:28.37#ibcon#about to write, iclass 11, count 2 2006.182.08:21:28.37#ibcon#wrote, iclass 11, count 2 2006.182.08:21:28.37#ibcon#about to read 3, iclass 11, count 2 2006.182.08:21:28.39#ibcon#read 3, iclass 11, count 2 2006.182.08:21:28.39#ibcon#about to read 4, iclass 11, count 2 2006.182.08:21:28.39#ibcon#read 4, iclass 11, count 2 2006.182.08:21:28.39#ibcon#about to read 5, iclass 11, count 2 2006.182.08:21:28.39#ibcon#read 5, iclass 11, count 2 2006.182.08:21:28.39#ibcon#about to read 6, iclass 11, count 2 2006.182.08:21:28.39#ibcon#read 6, iclass 11, count 2 2006.182.08:21:28.39#ibcon#end of sib2, iclass 11, count 2 2006.182.08:21:28.39#ibcon#*mode == 0, iclass 11, count 2 2006.182.08:21:28.39#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.08:21:28.39#ibcon#[25=AT02-07\r\n] 2006.182.08:21:28.39#ibcon#*before write, iclass 11, count 2 2006.182.08:21:28.39#ibcon#enter sib2, iclass 11, count 2 2006.182.08:21:28.39#ibcon#flushed, iclass 11, count 2 2006.182.08:21:28.39#ibcon#about to write, iclass 11, count 2 2006.182.08:21:28.39#ibcon#wrote, iclass 11, count 2 2006.182.08:21:28.39#ibcon#about to read 3, iclass 11, count 2 2006.182.08:21:28.42#ibcon#read 3, iclass 11, count 2 2006.182.08:21:28.42#ibcon#about to read 4, iclass 11, count 2 2006.182.08:21:28.42#ibcon#read 4, iclass 11, count 2 2006.182.08:21:28.42#ibcon#about to read 5, iclass 11, count 2 2006.182.08:21:28.42#ibcon#read 5, iclass 11, count 2 2006.182.08:21:28.42#ibcon#about to read 6, iclass 11, count 2 2006.182.08:21:28.42#ibcon#read 6, iclass 11, count 2 2006.182.08:21:28.42#ibcon#end of sib2, iclass 11, count 2 2006.182.08:21:28.42#ibcon#*after write, iclass 11, count 2 2006.182.08:21:28.42#ibcon#*before return 0, iclass 11, count 2 2006.182.08:21:28.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:28.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:28.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.08:21:28.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:28.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:28.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:28.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:28.54#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:21:28.54#ibcon#first serial, iclass 11, count 0 2006.182.08:21:28.54#ibcon#enter sib2, iclass 11, count 0 2006.182.08:21:28.54#ibcon#flushed, iclass 11, count 0 2006.182.08:21:28.54#ibcon#about to write, iclass 11, count 0 2006.182.08:21:28.54#ibcon#wrote, iclass 11, count 0 2006.182.08:21:28.54#ibcon#about to read 3, iclass 11, count 0 2006.182.08:21:28.56#ibcon#read 3, iclass 11, count 0 2006.182.08:21:28.56#ibcon#about to read 4, iclass 11, count 0 2006.182.08:21:28.56#ibcon#read 4, iclass 11, count 0 2006.182.08:21:28.56#ibcon#about to read 5, iclass 11, count 0 2006.182.08:21:28.56#ibcon#read 5, iclass 11, count 0 2006.182.08:21:28.56#ibcon#about to read 6, iclass 11, count 0 2006.182.08:21:28.56#ibcon#read 6, iclass 11, count 0 2006.182.08:21:28.56#ibcon#end of sib2, iclass 11, count 0 2006.182.08:21:28.56#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:21:28.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:21:28.56#ibcon#[25=USB\r\n] 2006.182.08:21:28.56#ibcon#*before write, iclass 11, count 0 2006.182.08:21:28.56#ibcon#enter sib2, iclass 11, count 0 2006.182.08:21:28.56#ibcon#flushed, iclass 11, count 0 2006.182.08:21:28.56#ibcon#about to write, iclass 11, count 0 2006.182.08:21:28.56#ibcon#wrote, iclass 11, count 0 2006.182.08:21:28.56#ibcon#about to read 3, iclass 11, count 0 2006.182.08:21:28.59#ibcon#read 3, iclass 11, count 0 2006.182.08:21:28.59#ibcon#about to read 4, iclass 11, count 0 2006.182.08:21:28.59#ibcon#read 4, iclass 11, count 0 2006.182.08:21:28.59#ibcon#about to read 5, iclass 11, count 0 2006.182.08:21:28.59#ibcon#read 5, iclass 11, count 0 2006.182.08:21:28.59#ibcon#about to read 6, iclass 11, count 0 2006.182.08:21:28.59#ibcon#read 6, iclass 11, count 0 2006.182.08:21:28.59#ibcon#end of sib2, iclass 11, count 0 2006.182.08:21:28.59#ibcon#*after write, iclass 11, count 0 2006.182.08:21:28.59#ibcon#*before return 0, iclass 11, count 0 2006.182.08:21:28.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:28.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:28.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:21:28.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:21:28.59$vc4f8/valo=3,672.99 2006.182.08:21:28.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.08:21:28.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.08:21:28.59#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:28.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:28.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:28.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:28.59#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:21:28.59#ibcon#first serial, iclass 13, count 0 2006.182.08:21:28.59#ibcon#enter sib2, iclass 13, count 0 2006.182.08:21:28.59#ibcon#flushed, iclass 13, count 0 2006.182.08:21:28.59#ibcon#about to write, iclass 13, count 0 2006.182.08:21:28.59#ibcon#wrote, iclass 13, count 0 2006.182.08:21:28.59#ibcon#about to read 3, iclass 13, count 0 2006.182.08:21:28.61#ibcon#read 3, iclass 13, count 0 2006.182.08:21:28.61#ibcon#about to read 4, iclass 13, count 0 2006.182.08:21:28.61#ibcon#read 4, iclass 13, count 0 2006.182.08:21:28.61#ibcon#about to read 5, iclass 13, count 0 2006.182.08:21:28.61#ibcon#read 5, iclass 13, count 0 2006.182.08:21:28.61#ibcon#about to read 6, iclass 13, count 0 2006.182.08:21:28.61#ibcon#read 6, iclass 13, count 0 2006.182.08:21:28.61#ibcon#end of sib2, iclass 13, count 0 2006.182.08:21:28.61#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:21:28.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:21:28.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:21:28.61#ibcon#*before write, iclass 13, count 0 2006.182.08:21:28.61#ibcon#enter sib2, iclass 13, count 0 2006.182.08:21:28.61#ibcon#flushed, iclass 13, count 0 2006.182.08:21:28.61#ibcon#about to write, iclass 13, count 0 2006.182.08:21:28.61#ibcon#wrote, iclass 13, count 0 2006.182.08:21:28.61#ibcon#about to read 3, iclass 13, count 0 2006.182.08:21:28.66#ibcon#read 3, iclass 13, count 0 2006.182.08:21:28.66#ibcon#about to read 4, iclass 13, count 0 2006.182.08:21:28.66#ibcon#read 4, iclass 13, count 0 2006.182.08:21:28.66#ibcon#about to read 5, iclass 13, count 0 2006.182.08:21:28.66#ibcon#read 5, iclass 13, count 0 2006.182.08:21:28.66#ibcon#about to read 6, iclass 13, count 0 2006.182.08:21:28.66#ibcon#read 6, iclass 13, count 0 2006.182.08:21:28.66#ibcon#end of sib2, iclass 13, count 0 2006.182.08:21:28.66#ibcon#*after write, iclass 13, count 0 2006.182.08:21:28.66#ibcon#*before return 0, iclass 13, count 0 2006.182.08:21:28.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:28.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:28.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:21:28.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:21:28.66$vc4f8/va=3,6 2006.182.08:21:28.66#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.182.08:21:28.66#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.182.08:21:28.66#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:28.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:28.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:28.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:28.71#ibcon#enter wrdev, iclass 15, count 2 2006.182.08:21:28.71#ibcon#first serial, iclass 15, count 2 2006.182.08:21:28.71#ibcon#enter sib2, iclass 15, count 2 2006.182.08:21:28.71#ibcon#flushed, iclass 15, count 2 2006.182.08:21:28.71#ibcon#about to write, iclass 15, count 2 2006.182.08:21:28.71#ibcon#wrote, iclass 15, count 2 2006.182.08:21:28.71#ibcon#about to read 3, iclass 15, count 2 2006.182.08:21:28.73#ibcon#read 3, iclass 15, count 2 2006.182.08:21:28.73#ibcon#about to read 4, iclass 15, count 2 2006.182.08:21:28.73#ibcon#read 4, iclass 15, count 2 2006.182.08:21:28.73#ibcon#about to read 5, iclass 15, count 2 2006.182.08:21:28.73#ibcon#read 5, iclass 15, count 2 2006.182.08:21:28.73#ibcon#about to read 6, iclass 15, count 2 2006.182.08:21:28.73#ibcon#read 6, iclass 15, count 2 2006.182.08:21:28.73#ibcon#end of sib2, iclass 15, count 2 2006.182.08:21:28.73#ibcon#*mode == 0, iclass 15, count 2 2006.182.08:21:28.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.182.08:21:28.73#ibcon#[25=AT03-06\r\n] 2006.182.08:21:28.73#ibcon#*before write, iclass 15, count 2 2006.182.08:21:28.73#ibcon#enter sib2, iclass 15, count 2 2006.182.08:21:28.73#ibcon#flushed, iclass 15, count 2 2006.182.08:21:28.73#ibcon#about to write, iclass 15, count 2 2006.182.08:21:28.73#ibcon#wrote, iclass 15, count 2 2006.182.08:21:28.73#ibcon#about to read 3, iclass 15, count 2 2006.182.08:21:28.76#ibcon#read 3, iclass 15, count 2 2006.182.08:21:28.76#ibcon#about to read 4, iclass 15, count 2 2006.182.08:21:28.76#ibcon#read 4, iclass 15, count 2 2006.182.08:21:28.76#ibcon#about to read 5, iclass 15, count 2 2006.182.08:21:28.76#ibcon#read 5, iclass 15, count 2 2006.182.08:21:28.76#ibcon#about to read 6, iclass 15, count 2 2006.182.08:21:28.76#ibcon#read 6, iclass 15, count 2 2006.182.08:21:28.76#ibcon#end of sib2, iclass 15, count 2 2006.182.08:21:28.76#ibcon#*after write, iclass 15, count 2 2006.182.08:21:28.76#ibcon#*before return 0, iclass 15, count 2 2006.182.08:21:28.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:28.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:28.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.182.08:21:28.76#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:28.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:28.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:28.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:28.88#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:21:28.88#ibcon#first serial, iclass 15, count 0 2006.182.08:21:28.88#ibcon#enter sib2, iclass 15, count 0 2006.182.08:21:28.88#ibcon#flushed, iclass 15, count 0 2006.182.08:21:28.88#ibcon#about to write, iclass 15, count 0 2006.182.08:21:28.88#ibcon#wrote, iclass 15, count 0 2006.182.08:21:28.88#ibcon#about to read 3, iclass 15, count 0 2006.182.08:21:28.90#ibcon#read 3, iclass 15, count 0 2006.182.08:21:28.90#ibcon#about to read 4, iclass 15, count 0 2006.182.08:21:28.90#ibcon#read 4, iclass 15, count 0 2006.182.08:21:28.90#ibcon#about to read 5, iclass 15, count 0 2006.182.08:21:28.90#ibcon#read 5, iclass 15, count 0 2006.182.08:21:28.90#ibcon#about to read 6, iclass 15, count 0 2006.182.08:21:28.90#ibcon#read 6, iclass 15, count 0 2006.182.08:21:28.90#ibcon#end of sib2, iclass 15, count 0 2006.182.08:21:28.90#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:21:28.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:21:28.90#ibcon#[25=USB\r\n] 2006.182.08:21:28.90#ibcon#*before write, iclass 15, count 0 2006.182.08:21:28.90#ibcon#enter sib2, iclass 15, count 0 2006.182.08:21:28.90#ibcon#flushed, iclass 15, count 0 2006.182.08:21:28.90#ibcon#about to write, iclass 15, count 0 2006.182.08:21:28.90#ibcon#wrote, iclass 15, count 0 2006.182.08:21:28.90#ibcon#about to read 3, iclass 15, count 0 2006.182.08:21:28.93#ibcon#read 3, iclass 15, count 0 2006.182.08:21:28.93#ibcon#about to read 4, iclass 15, count 0 2006.182.08:21:28.93#ibcon#read 4, iclass 15, count 0 2006.182.08:21:28.93#ibcon#about to read 5, iclass 15, count 0 2006.182.08:21:28.93#ibcon#read 5, iclass 15, count 0 2006.182.08:21:28.93#ibcon#about to read 6, iclass 15, count 0 2006.182.08:21:28.93#ibcon#read 6, iclass 15, count 0 2006.182.08:21:28.93#ibcon#end of sib2, iclass 15, count 0 2006.182.08:21:28.93#ibcon#*after write, iclass 15, count 0 2006.182.08:21:28.93#ibcon#*before return 0, iclass 15, count 0 2006.182.08:21:28.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:28.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:28.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:21:28.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:21:28.93$vc4f8/valo=4,832.99 2006.182.08:21:28.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.08:21:28.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.08:21:28.93#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:28.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:28.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:28.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:28.93#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:21:28.93#ibcon#first serial, iclass 17, count 0 2006.182.08:21:28.93#ibcon#enter sib2, iclass 17, count 0 2006.182.08:21:28.93#ibcon#flushed, iclass 17, count 0 2006.182.08:21:28.93#ibcon#about to write, iclass 17, count 0 2006.182.08:21:28.93#ibcon#wrote, iclass 17, count 0 2006.182.08:21:28.93#ibcon#about to read 3, iclass 17, count 0 2006.182.08:21:28.95#ibcon#read 3, iclass 17, count 0 2006.182.08:21:28.95#ibcon#about to read 4, iclass 17, count 0 2006.182.08:21:28.95#ibcon#read 4, iclass 17, count 0 2006.182.08:21:28.95#ibcon#about to read 5, iclass 17, count 0 2006.182.08:21:28.95#ibcon#read 5, iclass 17, count 0 2006.182.08:21:28.95#ibcon#about to read 6, iclass 17, count 0 2006.182.08:21:28.95#ibcon#read 6, iclass 17, count 0 2006.182.08:21:28.95#ibcon#end of sib2, iclass 17, count 0 2006.182.08:21:28.95#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:21:28.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:21:28.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:21:28.95#ibcon#*before write, iclass 17, count 0 2006.182.08:21:28.95#ibcon#enter sib2, iclass 17, count 0 2006.182.08:21:28.95#ibcon#flushed, iclass 17, count 0 2006.182.08:21:28.95#ibcon#about to write, iclass 17, count 0 2006.182.08:21:28.95#ibcon#wrote, iclass 17, count 0 2006.182.08:21:28.95#ibcon#about to read 3, iclass 17, count 0 2006.182.08:21:28.99#ibcon#read 3, iclass 17, count 0 2006.182.08:21:28.99#ibcon#about to read 4, iclass 17, count 0 2006.182.08:21:28.99#ibcon#read 4, iclass 17, count 0 2006.182.08:21:28.99#ibcon#about to read 5, iclass 17, count 0 2006.182.08:21:28.99#ibcon#read 5, iclass 17, count 0 2006.182.08:21:28.99#ibcon#about to read 6, iclass 17, count 0 2006.182.08:21:28.99#ibcon#read 6, iclass 17, count 0 2006.182.08:21:28.99#ibcon#end of sib2, iclass 17, count 0 2006.182.08:21:28.99#ibcon#*after write, iclass 17, count 0 2006.182.08:21:28.99#ibcon#*before return 0, iclass 17, count 0 2006.182.08:21:28.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:28.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:28.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:21:28.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:21:28.99$vc4f8/va=4,7 2006.182.08:21:28.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.182.08:21:28.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.182.08:21:28.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:28.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:29.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:29.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:29.05#ibcon#enter wrdev, iclass 19, count 2 2006.182.08:21:29.05#ibcon#first serial, iclass 19, count 2 2006.182.08:21:29.05#ibcon#enter sib2, iclass 19, count 2 2006.182.08:21:29.05#ibcon#flushed, iclass 19, count 2 2006.182.08:21:29.05#ibcon#about to write, iclass 19, count 2 2006.182.08:21:29.05#ibcon#wrote, iclass 19, count 2 2006.182.08:21:29.05#ibcon#about to read 3, iclass 19, count 2 2006.182.08:21:29.07#ibcon#read 3, iclass 19, count 2 2006.182.08:21:29.07#ibcon#about to read 4, iclass 19, count 2 2006.182.08:21:29.07#ibcon#read 4, iclass 19, count 2 2006.182.08:21:29.07#ibcon#about to read 5, iclass 19, count 2 2006.182.08:21:29.07#ibcon#read 5, iclass 19, count 2 2006.182.08:21:29.07#ibcon#about to read 6, iclass 19, count 2 2006.182.08:21:29.07#ibcon#read 6, iclass 19, count 2 2006.182.08:21:29.07#ibcon#end of sib2, iclass 19, count 2 2006.182.08:21:29.07#ibcon#*mode == 0, iclass 19, count 2 2006.182.08:21:29.07#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.182.08:21:29.07#ibcon#[25=AT04-07\r\n] 2006.182.08:21:29.07#ibcon#*before write, iclass 19, count 2 2006.182.08:21:29.07#ibcon#enter sib2, iclass 19, count 2 2006.182.08:21:29.07#ibcon#flushed, iclass 19, count 2 2006.182.08:21:29.07#ibcon#about to write, iclass 19, count 2 2006.182.08:21:29.07#ibcon#wrote, iclass 19, count 2 2006.182.08:21:29.07#ibcon#about to read 3, iclass 19, count 2 2006.182.08:21:29.10#ibcon#read 3, iclass 19, count 2 2006.182.08:21:29.10#ibcon#about to read 4, iclass 19, count 2 2006.182.08:21:29.10#ibcon#read 4, iclass 19, count 2 2006.182.08:21:29.10#ibcon#about to read 5, iclass 19, count 2 2006.182.08:21:29.10#ibcon#read 5, iclass 19, count 2 2006.182.08:21:29.10#ibcon#about to read 6, iclass 19, count 2 2006.182.08:21:29.10#ibcon#read 6, iclass 19, count 2 2006.182.08:21:29.10#ibcon#end of sib2, iclass 19, count 2 2006.182.08:21:29.10#ibcon#*after write, iclass 19, count 2 2006.182.08:21:29.10#ibcon#*before return 0, iclass 19, count 2 2006.182.08:21:29.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:29.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:29.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.182.08:21:29.10#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:29.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:29.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:29.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:29.22#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:21:29.22#ibcon#first serial, iclass 19, count 0 2006.182.08:21:29.22#ibcon#enter sib2, iclass 19, count 0 2006.182.08:21:29.22#ibcon#flushed, iclass 19, count 0 2006.182.08:21:29.22#ibcon#about to write, iclass 19, count 0 2006.182.08:21:29.22#ibcon#wrote, iclass 19, count 0 2006.182.08:21:29.22#ibcon#about to read 3, iclass 19, count 0 2006.182.08:21:29.24#ibcon#read 3, iclass 19, count 0 2006.182.08:21:29.24#ibcon#about to read 4, iclass 19, count 0 2006.182.08:21:29.24#ibcon#read 4, iclass 19, count 0 2006.182.08:21:29.24#ibcon#about to read 5, iclass 19, count 0 2006.182.08:21:29.24#ibcon#read 5, iclass 19, count 0 2006.182.08:21:29.24#ibcon#about to read 6, iclass 19, count 0 2006.182.08:21:29.24#ibcon#read 6, iclass 19, count 0 2006.182.08:21:29.24#ibcon#end of sib2, iclass 19, count 0 2006.182.08:21:29.24#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:21:29.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:21:29.24#ibcon#[25=USB\r\n] 2006.182.08:21:29.24#ibcon#*before write, iclass 19, count 0 2006.182.08:21:29.24#ibcon#enter sib2, iclass 19, count 0 2006.182.08:21:29.24#ibcon#flushed, iclass 19, count 0 2006.182.08:21:29.24#ibcon#about to write, iclass 19, count 0 2006.182.08:21:29.24#ibcon#wrote, iclass 19, count 0 2006.182.08:21:29.24#ibcon#about to read 3, iclass 19, count 0 2006.182.08:21:29.27#ibcon#read 3, iclass 19, count 0 2006.182.08:21:29.27#ibcon#about to read 4, iclass 19, count 0 2006.182.08:21:29.27#ibcon#read 4, iclass 19, count 0 2006.182.08:21:29.27#ibcon#about to read 5, iclass 19, count 0 2006.182.08:21:29.27#ibcon#read 5, iclass 19, count 0 2006.182.08:21:29.27#ibcon#about to read 6, iclass 19, count 0 2006.182.08:21:29.27#ibcon#read 6, iclass 19, count 0 2006.182.08:21:29.27#ibcon#end of sib2, iclass 19, count 0 2006.182.08:21:29.27#ibcon#*after write, iclass 19, count 0 2006.182.08:21:29.27#ibcon#*before return 0, iclass 19, count 0 2006.182.08:21:29.27#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:29.27#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:29.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:21:29.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:21:29.27$vc4f8/valo=5,652.99 2006.182.08:21:29.27#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.08:21:29.27#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.08:21:29.27#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:29.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:29.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:29.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:29.27#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:21:29.27#ibcon#first serial, iclass 21, count 0 2006.182.08:21:29.27#ibcon#enter sib2, iclass 21, count 0 2006.182.08:21:29.27#ibcon#flushed, iclass 21, count 0 2006.182.08:21:29.27#ibcon#about to write, iclass 21, count 0 2006.182.08:21:29.27#ibcon#wrote, iclass 21, count 0 2006.182.08:21:29.27#ibcon#about to read 3, iclass 21, count 0 2006.182.08:21:29.29#ibcon#read 3, iclass 21, count 0 2006.182.08:21:29.29#ibcon#about to read 4, iclass 21, count 0 2006.182.08:21:29.29#ibcon#read 4, iclass 21, count 0 2006.182.08:21:29.29#ibcon#about to read 5, iclass 21, count 0 2006.182.08:21:29.29#ibcon#read 5, iclass 21, count 0 2006.182.08:21:29.29#ibcon#about to read 6, iclass 21, count 0 2006.182.08:21:29.29#ibcon#read 6, iclass 21, count 0 2006.182.08:21:29.29#ibcon#end of sib2, iclass 21, count 0 2006.182.08:21:29.29#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:21:29.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:21:29.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:21:29.29#ibcon#*before write, iclass 21, count 0 2006.182.08:21:29.29#ibcon#enter sib2, iclass 21, count 0 2006.182.08:21:29.29#ibcon#flushed, iclass 21, count 0 2006.182.08:21:29.29#ibcon#about to write, iclass 21, count 0 2006.182.08:21:29.29#ibcon#wrote, iclass 21, count 0 2006.182.08:21:29.29#ibcon#about to read 3, iclass 21, count 0 2006.182.08:21:29.33#ibcon#read 3, iclass 21, count 0 2006.182.08:21:29.33#ibcon#about to read 4, iclass 21, count 0 2006.182.08:21:29.33#ibcon#read 4, iclass 21, count 0 2006.182.08:21:29.33#ibcon#about to read 5, iclass 21, count 0 2006.182.08:21:29.33#ibcon#read 5, iclass 21, count 0 2006.182.08:21:29.33#ibcon#about to read 6, iclass 21, count 0 2006.182.08:21:29.33#ibcon#read 6, iclass 21, count 0 2006.182.08:21:29.33#ibcon#end of sib2, iclass 21, count 0 2006.182.08:21:29.33#ibcon#*after write, iclass 21, count 0 2006.182.08:21:29.33#ibcon#*before return 0, iclass 21, count 0 2006.182.08:21:29.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:29.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:29.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:21:29.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:21:29.33$vc4f8/va=5,7 2006.182.08:21:29.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.182.08:21:29.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.182.08:21:29.33#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:29.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:29.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:29.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:29.39#ibcon#enter wrdev, iclass 23, count 2 2006.182.08:21:29.39#ibcon#first serial, iclass 23, count 2 2006.182.08:21:29.39#ibcon#enter sib2, iclass 23, count 2 2006.182.08:21:29.39#ibcon#flushed, iclass 23, count 2 2006.182.08:21:29.39#ibcon#about to write, iclass 23, count 2 2006.182.08:21:29.39#ibcon#wrote, iclass 23, count 2 2006.182.08:21:29.39#ibcon#about to read 3, iclass 23, count 2 2006.182.08:21:29.41#ibcon#read 3, iclass 23, count 2 2006.182.08:21:29.41#ibcon#about to read 4, iclass 23, count 2 2006.182.08:21:29.41#ibcon#read 4, iclass 23, count 2 2006.182.08:21:29.41#ibcon#about to read 5, iclass 23, count 2 2006.182.08:21:29.41#ibcon#read 5, iclass 23, count 2 2006.182.08:21:29.41#ibcon#about to read 6, iclass 23, count 2 2006.182.08:21:29.41#ibcon#read 6, iclass 23, count 2 2006.182.08:21:29.41#ibcon#end of sib2, iclass 23, count 2 2006.182.08:21:29.41#ibcon#*mode == 0, iclass 23, count 2 2006.182.08:21:29.41#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.182.08:21:29.41#ibcon#[25=AT05-07\r\n] 2006.182.08:21:29.41#ibcon#*before write, iclass 23, count 2 2006.182.08:21:29.41#ibcon#enter sib2, iclass 23, count 2 2006.182.08:21:29.41#ibcon#flushed, iclass 23, count 2 2006.182.08:21:29.41#ibcon#about to write, iclass 23, count 2 2006.182.08:21:29.41#ibcon#wrote, iclass 23, count 2 2006.182.08:21:29.41#ibcon#about to read 3, iclass 23, count 2 2006.182.08:21:29.44#ibcon#read 3, iclass 23, count 2 2006.182.08:21:29.44#ibcon#about to read 4, iclass 23, count 2 2006.182.08:21:29.44#ibcon#read 4, iclass 23, count 2 2006.182.08:21:29.44#ibcon#about to read 5, iclass 23, count 2 2006.182.08:21:29.44#ibcon#read 5, iclass 23, count 2 2006.182.08:21:29.44#ibcon#about to read 6, iclass 23, count 2 2006.182.08:21:29.44#ibcon#read 6, iclass 23, count 2 2006.182.08:21:29.44#ibcon#end of sib2, iclass 23, count 2 2006.182.08:21:29.44#ibcon#*after write, iclass 23, count 2 2006.182.08:21:29.44#ibcon#*before return 0, iclass 23, count 2 2006.182.08:21:29.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:29.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:29.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.182.08:21:29.44#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:29.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:29.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:29.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:29.56#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:21:29.56#ibcon#first serial, iclass 23, count 0 2006.182.08:21:29.56#ibcon#enter sib2, iclass 23, count 0 2006.182.08:21:29.56#ibcon#flushed, iclass 23, count 0 2006.182.08:21:29.56#ibcon#about to write, iclass 23, count 0 2006.182.08:21:29.56#ibcon#wrote, iclass 23, count 0 2006.182.08:21:29.56#ibcon#about to read 3, iclass 23, count 0 2006.182.08:21:29.58#ibcon#read 3, iclass 23, count 0 2006.182.08:21:29.58#ibcon#about to read 4, iclass 23, count 0 2006.182.08:21:29.58#ibcon#read 4, iclass 23, count 0 2006.182.08:21:29.58#ibcon#about to read 5, iclass 23, count 0 2006.182.08:21:29.58#ibcon#read 5, iclass 23, count 0 2006.182.08:21:29.58#ibcon#about to read 6, iclass 23, count 0 2006.182.08:21:29.58#ibcon#read 6, iclass 23, count 0 2006.182.08:21:29.58#ibcon#end of sib2, iclass 23, count 0 2006.182.08:21:29.58#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:21:29.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:21:29.58#ibcon#[25=USB\r\n] 2006.182.08:21:29.58#ibcon#*before write, iclass 23, count 0 2006.182.08:21:29.58#ibcon#enter sib2, iclass 23, count 0 2006.182.08:21:29.58#ibcon#flushed, iclass 23, count 0 2006.182.08:21:29.58#ibcon#about to write, iclass 23, count 0 2006.182.08:21:29.58#ibcon#wrote, iclass 23, count 0 2006.182.08:21:29.58#ibcon#about to read 3, iclass 23, count 0 2006.182.08:21:29.61#ibcon#read 3, iclass 23, count 0 2006.182.08:21:29.61#ibcon#about to read 4, iclass 23, count 0 2006.182.08:21:29.61#ibcon#read 4, iclass 23, count 0 2006.182.08:21:29.61#ibcon#about to read 5, iclass 23, count 0 2006.182.08:21:29.61#ibcon#read 5, iclass 23, count 0 2006.182.08:21:29.61#ibcon#about to read 6, iclass 23, count 0 2006.182.08:21:29.61#ibcon#read 6, iclass 23, count 0 2006.182.08:21:29.61#ibcon#end of sib2, iclass 23, count 0 2006.182.08:21:29.61#ibcon#*after write, iclass 23, count 0 2006.182.08:21:29.61#ibcon#*before return 0, iclass 23, count 0 2006.182.08:21:29.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:29.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:29.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:21:29.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:21:29.61$vc4f8/valo=6,772.99 2006.182.08:21:29.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.08:21:29.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.08:21:29.61#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:29.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:29.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:29.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:29.61#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:21:29.61#ibcon#first serial, iclass 25, count 0 2006.182.08:21:29.61#ibcon#enter sib2, iclass 25, count 0 2006.182.08:21:29.61#ibcon#flushed, iclass 25, count 0 2006.182.08:21:29.61#ibcon#about to write, iclass 25, count 0 2006.182.08:21:29.61#ibcon#wrote, iclass 25, count 0 2006.182.08:21:29.61#ibcon#about to read 3, iclass 25, count 0 2006.182.08:21:29.63#ibcon#read 3, iclass 25, count 0 2006.182.08:21:29.63#ibcon#about to read 4, iclass 25, count 0 2006.182.08:21:29.63#ibcon#read 4, iclass 25, count 0 2006.182.08:21:29.63#ibcon#about to read 5, iclass 25, count 0 2006.182.08:21:29.63#ibcon#read 5, iclass 25, count 0 2006.182.08:21:29.63#ibcon#about to read 6, iclass 25, count 0 2006.182.08:21:29.63#ibcon#read 6, iclass 25, count 0 2006.182.08:21:29.63#ibcon#end of sib2, iclass 25, count 0 2006.182.08:21:29.63#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:21:29.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:21:29.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:21:29.63#ibcon#*before write, iclass 25, count 0 2006.182.08:21:29.63#ibcon#enter sib2, iclass 25, count 0 2006.182.08:21:29.63#ibcon#flushed, iclass 25, count 0 2006.182.08:21:29.63#ibcon#about to write, iclass 25, count 0 2006.182.08:21:29.63#ibcon#wrote, iclass 25, count 0 2006.182.08:21:29.63#ibcon#about to read 3, iclass 25, count 0 2006.182.08:21:29.68#ibcon#read 3, iclass 25, count 0 2006.182.08:21:29.68#ibcon#about to read 4, iclass 25, count 0 2006.182.08:21:29.68#ibcon#read 4, iclass 25, count 0 2006.182.08:21:29.68#ibcon#about to read 5, iclass 25, count 0 2006.182.08:21:29.68#ibcon#read 5, iclass 25, count 0 2006.182.08:21:29.68#ibcon#about to read 6, iclass 25, count 0 2006.182.08:21:29.68#ibcon#read 6, iclass 25, count 0 2006.182.08:21:29.68#ibcon#end of sib2, iclass 25, count 0 2006.182.08:21:29.68#ibcon#*after write, iclass 25, count 0 2006.182.08:21:29.68#ibcon#*before return 0, iclass 25, count 0 2006.182.08:21:29.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:29.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:29.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:21:29.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:21:29.68$vc4f8/va=6,6 2006.182.08:21:29.68#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.182.08:21:29.68#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.182.08:21:29.68#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:29.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:21:29.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:21:29.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:21:29.73#ibcon#enter wrdev, iclass 27, count 2 2006.182.08:21:29.73#ibcon#first serial, iclass 27, count 2 2006.182.08:21:29.73#ibcon#enter sib2, iclass 27, count 2 2006.182.08:21:29.73#ibcon#flushed, iclass 27, count 2 2006.182.08:21:29.73#ibcon#about to write, iclass 27, count 2 2006.182.08:21:29.73#ibcon#wrote, iclass 27, count 2 2006.182.08:21:29.73#ibcon#about to read 3, iclass 27, count 2 2006.182.08:21:29.75#ibcon#read 3, iclass 27, count 2 2006.182.08:21:29.75#ibcon#about to read 4, iclass 27, count 2 2006.182.08:21:29.75#ibcon#read 4, iclass 27, count 2 2006.182.08:21:29.75#ibcon#about to read 5, iclass 27, count 2 2006.182.08:21:29.75#ibcon#read 5, iclass 27, count 2 2006.182.08:21:29.75#ibcon#about to read 6, iclass 27, count 2 2006.182.08:21:29.75#ibcon#read 6, iclass 27, count 2 2006.182.08:21:29.75#ibcon#end of sib2, iclass 27, count 2 2006.182.08:21:29.75#ibcon#*mode == 0, iclass 27, count 2 2006.182.08:21:29.75#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.182.08:21:29.75#ibcon#[25=AT06-06\r\n] 2006.182.08:21:29.75#ibcon#*before write, iclass 27, count 2 2006.182.08:21:29.75#ibcon#enter sib2, iclass 27, count 2 2006.182.08:21:29.75#ibcon#flushed, iclass 27, count 2 2006.182.08:21:29.75#ibcon#about to write, iclass 27, count 2 2006.182.08:21:29.75#ibcon#wrote, iclass 27, count 2 2006.182.08:21:29.75#ibcon#about to read 3, iclass 27, count 2 2006.182.08:21:29.78#ibcon#read 3, iclass 27, count 2 2006.182.08:21:29.78#ibcon#about to read 4, iclass 27, count 2 2006.182.08:21:29.78#ibcon#read 4, iclass 27, count 2 2006.182.08:21:29.78#ibcon#about to read 5, iclass 27, count 2 2006.182.08:21:29.78#ibcon#read 5, iclass 27, count 2 2006.182.08:21:29.78#ibcon#about to read 6, iclass 27, count 2 2006.182.08:21:29.78#ibcon#read 6, iclass 27, count 2 2006.182.08:21:29.78#ibcon#end of sib2, iclass 27, count 2 2006.182.08:21:29.78#ibcon#*after write, iclass 27, count 2 2006.182.08:21:29.78#ibcon#*before return 0, iclass 27, count 2 2006.182.08:21:29.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:21:29.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.182.08:21:29.78#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.182.08:21:29.78#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:29.78#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:21:29.90#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:21:29.90#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:21:29.90#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:21:29.90#ibcon#first serial, iclass 27, count 0 2006.182.08:21:29.90#ibcon#enter sib2, iclass 27, count 0 2006.182.08:21:29.90#ibcon#flushed, iclass 27, count 0 2006.182.08:21:29.90#ibcon#about to write, iclass 27, count 0 2006.182.08:21:29.90#ibcon#wrote, iclass 27, count 0 2006.182.08:21:29.90#ibcon#about to read 3, iclass 27, count 0 2006.182.08:21:29.92#ibcon#read 3, iclass 27, count 0 2006.182.08:21:29.92#ibcon#about to read 4, iclass 27, count 0 2006.182.08:21:29.92#ibcon#read 4, iclass 27, count 0 2006.182.08:21:29.92#ibcon#about to read 5, iclass 27, count 0 2006.182.08:21:29.92#ibcon#read 5, iclass 27, count 0 2006.182.08:21:29.92#ibcon#about to read 6, iclass 27, count 0 2006.182.08:21:29.92#ibcon#read 6, iclass 27, count 0 2006.182.08:21:29.92#ibcon#end of sib2, iclass 27, count 0 2006.182.08:21:29.92#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:21:29.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:21:29.92#ibcon#[25=USB\r\n] 2006.182.08:21:29.92#ibcon#*before write, iclass 27, count 0 2006.182.08:21:29.92#ibcon#enter sib2, iclass 27, count 0 2006.182.08:21:29.92#ibcon#flushed, iclass 27, count 0 2006.182.08:21:29.92#ibcon#about to write, iclass 27, count 0 2006.182.08:21:29.92#ibcon#wrote, iclass 27, count 0 2006.182.08:21:29.92#ibcon#about to read 3, iclass 27, count 0 2006.182.08:21:29.95#ibcon#read 3, iclass 27, count 0 2006.182.08:21:29.95#ibcon#about to read 4, iclass 27, count 0 2006.182.08:21:29.95#ibcon#read 4, iclass 27, count 0 2006.182.08:21:29.95#ibcon#about to read 5, iclass 27, count 0 2006.182.08:21:29.95#ibcon#read 5, iclass 27, count 0 2006.182.08:21:29.95#ibcon#about to read 6, iclass 27, count 0 2006.182.08:21:29.95#ibcon#read 6, iclass 27, count 0 2006.182.08:21:29.95#ibcon#end of sib2, iclass 27, count 0 2006.182.08:21:29.95#ibcon#*after write, iclass 27, count 0 2006.182.08:21:29.95#ibcon#*before return 0, iclass 27, count 0 2006.182.08:21:29.95#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:21:29.95#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.182.08:21:29.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:21:29.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:21:29.95$vc4f8/valo=7,832.99 2006.182.08:21:29.95#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.08:21:29.95#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.08:21:29.95#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:29.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:21:29.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:21:29.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:21:29.95#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:21:29.95#ibcon#first serial, iclass 29, count 0 2006.182.08:21:29.95#ibcon#enter sib2, iclass 29, count 0 2006.182.08:21:29.95#ibcon#flushed, iclass 29, count 0 2006.182.08:21:29.95#ibcon#about to write, iclass 29, count 0 2006.182.08:21:29.95#ibcon#wrote, iclass 29, count 0 2006.182.08:21:29.95#ibcon#about to read 3, iclass 29, count 0 2006.182.08:21:29.97#ibcon#read 3, iclass 29, count 0 2006.182.08:21:29.97#ibcon#about to read 4, iclass 29, count 0 2006.182.08:21:29.97#ibcon#read 4, iclass 29, count 0 2006.182.08:21:29.97#ibcon#about to read 5, iclass 29, count 0 2006.182.08:21:29.97#ibcon#read 5, iclass 29, count 0 2006.182.08:21:29.97#ibcon#about to read 6, iclass 29, count 0 2006.182.08:21:29.97#ibcon#read 6, iclass 29, count 0 2006.182.08:21:29.97#ibcon#end of sib2, iclass 29, count 0 2006.182.08:21:29.97#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:21:29.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:21:29.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:21:29.97#ibcon#*before write, iclass 29, count 0 2006.182.08:21:29.97#ibcon#enter sib2, iclass 29, count 0 2006.182.08:21:29.97#ibcon#flushed, iclass 29, count 0 2006.182.08:21:29.97#ibcon#about to write, iclass 29, count 0 2006.182.08:21:29.97#ibcon#wrote, iclass 29, count 0 2006.182.08:21:29.97#ibcon#about to read 3, iclass 29, count 0 2006.182.08:21:30.01#ibcon#read 3, iclass 29, count 0 2006.182.08:21:30.01#ibcon#about to read 4, iclass 29, count 0 2006.182.08:21:30.01#ibcon#read 4, iclass 29, count 0 2006.182.08:21:30.01#ibcon#about to read 5, iclass 29, count 0 2006.182.08:21:30.01#ibcon#read 5, iclass 29, count 0 2006.182.08:21:30.01#ibcon#about to read 6, iclass 29, count 0 2006.182.08:21:30.01#ibcon#read 6, iclass 29, count 0 2006.182.08:21:30.01#ibcon#end of sib2, iclass 29, count 0 2006.182.08:21:30.01#ibcon#*after write, iclass 29, count 0 2006.182.08:21:30.01#ibcon#*before return 0, iclass 29, count 0 2006.182.08:21:30.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:21:30.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:21:30.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:21:30.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:21:30.01$vc4f8/va=7,6 2006.182.08:21:30.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.182.08:21:30.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.182.08:21:30.01#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:30.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:21:30.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:21:30.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:21:30.07#ibcon#enter wrdev, iclass 31, count 2 2006.182.08:21:30.07#ibcon#first serial, iclass 31, count 2 2006.182.08:21:30.07#ibcon#enter sib2, iclass 31, count 2 2006.182.08:21:30.07#ibcon#flushed, iclass 31, count 2 2006.182.08:21:30.07#ibcon#about to write, iclass 31, count 2 2006.182.08:21:30.07#ibcon#wrote, iclass 31, count 2 2006.182.08:21:30.07#ibcon#about to read 3, iclass 31, count 2 2006.182.08:21:30.09#ibcon#read 3, iclass 31, count 2 2006.182.08:21:30.09#ibcon#about to read 4, iclass 31, count 2 2006.182.08:21:30.09#ibcon#read 4, iclass 31, count 2 2006.182.08:21:30.09#ibcon#about to read 5, iclass 31, count 2 2006.182.08:21:30.09#ibcon#read 5, iclass 31, count 2 2006.182.08:21:30.09#ibcon#about to read 6, iclass 31, count 2 2006.182.08:21:30.09#ibcon#read 6, iclass 31, count 2 2006.182.08:21:30.09#ibcon#end of sib2, iclass 31, count 2 2006.182.08:21:30.09#ibcon#*mode == 0, iclass 31, count 2 2006.182.08:21:30.09#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.182.08:21:30.09#ibcon#[25=AT07-06\r\n] 2006.182.08:21:30.09#ibcon#*before write, iclass 31, count 2 2006.182.08:21:30.09#ibcon#enter sib2, iclass 31, count 2 2006.182.08:21:30.09#ibcon#flushed, iclass 31, count 2 2006.182.08:21:30.09#ibcon#about to write, iclass 31, count 2 2006.182.08:21:30.09#ibcon#wrote, iclass 31, count 2 2006.182.08:21:30.09#ibcon#about to read 3, iclass 31, count 2 2006.182.08:21:30.12#ibcon#read 3, iclass 31, count 2 2006.182.08:21:30.12#ibcon#about to read 4, iclass 31, count 2 2006.182.08:21:30.12#ibcon#read 4, iclass 31, count 2 2006.182.08:21:30.12#ibcon#about to read 5, iclass 31, count 2 2006.182.08:21:30.12#ibcon#read 5, iclass 31, count 2 2006.182.08:21:30.12#ibcon#about to read 6, iclass 31, count 2 2006.182.08:21:30.12#ibcon#read 6, iclass 31, count 2 2006.182.08:21:30.12#ibcon#end of sib2, iclass 31, count 2 2006.182.08:21:30.12#ibcon#*after write, iclass 31, count 2 2006.182.08:21:30.12#ibcon#*before return 0, iclass 31, count 2 2006.182.08:21:30.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:21:30.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.182.08:21:30.12#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.182.08:21:30.12#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:30.12#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:21:30.24#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:21:30.24#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:21:30.24#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:21:30.24#ibcon#first serial, iclass 31, count 0 2006.182.08:21:30.24#ibcon#enter sib2, iclass 31, count 0 2006.182.08:21:30.24#ibcon#flushed, iclass 31, count 0 2006.182.08:21:30.24#ibcon#about to write, iclass 31, count 0 2006.182.08:21:30.24#ibcon#wrote, iclass 31, count 0 2006.182.08:21:30.24#ibcon#about to read 3, iclass 31, count 0 2006.182.08:21:30.26#ibcon#read 3, iclass 31, count 0 2006.182.08:21:30.26#ibcon#about to read 4, iclass 31, count 0 2006.182.08:21:30.26#ibcon#read 4, iclass 31, count 0 2006.182.08:21:30.26#ibcon#about to read 5, iclass 31, count 0 2006.182.08:21:30.26#ibcon#read 5, iclass 31, count 0 2006.182.08:21:30.26#ibcon#about to read 6, iclass 31, count 0 2006.182.08:21:30.26#ibcon#read 6, iclass 31, count 0 2006.182.08:21:30.26#ibcon#end of sib2, iclass 31, count 0 2006.182.08:21:30.26#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:21:30.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:21:30.26#ibcon#[25=USB\r\n] 2006.182.08:21:30.26#ibcon#*before write, iclass 31, count 0 2006.182.08:21:30.26#ibcon#enter sib2, iclass 31, count 0 2006.182.08:21:30.26#ibcon#flushed, iclass 31, count 0 2006.182.08:21:30.26#ibcon#about to write, iclass 31, count 0 2006.182.08:21:30.26#ibcon#wrote, iclass 31, count 0 2006.182.08:21:30.26#ibcon#about to read 3, iclass 31, count 0 2006.182.08:21:30.29#ibcon#read 3, iclass 31, count 0 2006.182.08:21:30.29#ibcon#about to read 4, iclass 31, count 0 2006.182.08:21:30.29#ibcon#read 4, iclass 31, count 0 2006.182.08:21:30.29#ibcon#about to read 5, iclass 31, count 0 2006.182.08:21:30.29#ibcon#read 5, iclass 31, count 0 2006.182.08:21:30.29#ibcon#about to read 6, iclass 31, count 0 2006.182.08:21:30.29#ibcon#read 6, iclass 31, count 0 2006.182.08:21:30.29#ibcon#end of sib2, iclass 31, count 0 2006.182.08:21:30.29#ibcon#*after write, iclass 31, count 0 2006.182.08:21:30.29#ibcon#*before return 0, iclass 31, count 0 2006.182.08:21:30.29#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:21:30.29#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.182.08:21:30.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:21:30.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:21:30.29$vc4f8/valo=8,852.99 2006.182.08:21:30.29#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.182.08:21:30.29#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.182.08:21:30.29#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:30.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:21:30.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:21:30.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:21:30.29#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:21:30.29#ibcon#first serial, iclass 33, count 0 2006.182.08:21:30.29#ibcon#enter sib2, iclass 33, count 0 2006.182.08:21:30.29#ibcon#flushed, iclass 33, count 0 2006.182.08:21:30.29#ibcon#about to write, iclass 33, count 0 2006.182.08:21:30.29#ibcon#wrote, iclass 33, count 0 2006.182.08:21:30.29#ibcon#about to read 3, iclass 33, count 0 2006.182.08:21:30.31#ibcon#read 3, iclass 33, count 0 2006.182.08:21:30.31#ibcon#about to read 4, iclass 33, count 0 2006.182.08:21:30.31#ibcon#read 4, iclass 33, count 0 2006.182.08:21:30.31#ibcon#about to read 5, iclass 33, count 0 2006.182.08:21:30.31#ibcon#read 5, iclass 33, count 0 2006.182.08:21:30.31#ibcon#about to read 6, iclass 33, count 0 2006.182.08:21:30.31#ibcon#read 6, iclass 33, count 0 2006.182.08:21:30.31#ibcon#end of sib2, iclass 33, count 0 2006.182.08:21:30.31#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:21:30.31#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:21:30.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:21:30.31#ibcon#*before write, iclass 33, count 0 2006.182.08:21:30.31#ibcon#enter sib2, iclass 33, count 0 2006.182.08:21:30.31#ibcon#flushed, iclass 33, count 0 2006.182.08:21:30.31#ibcon#about to write, iclass 33, count 0 2006.182.08:21:30.31#ibcon#wrote, iclass 33, count 0 2006.182.08:21:30.31#ibcon#about to read 3, iclass 33, count 0 2006.182.08:21:30.36#ibcon#read 3, iclass 33, count 0 2006.182.08:21:30.36#ibcon#about to read 4, iclass 33, count 0 2006.182.08:21:30.36#ibcon#read 4, iclass 33, count 0 2006.182.08:21:30.36#ibcon#about to read 5, iclass 33, count 0 2006.182.08:21:30.36#ibcon#read 5, iclass 33, count 0 2006.182.08:21:30.36#ibcon#about to read 6, iclass 33, count 0 2006.182.08:21:30.36#ibcon#read 6, iclass 33, count 0 2006.182.08:21:30.36#ibcon#end of sib2, iclass 33, count 0 2006.182.08:21:30.36#ibcon#*after write, iclass 33, count 0 2006.182.08:21:30.36#ibcon#*before return 0, iclass 33, count 0 2006.182.08:21:30.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:21:30.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.182.08:21:30.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:21:30.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:21:30.36$vc4f8/va=8,7 2006.182.08:21:30.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.182.08:21:30.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.182.08:21:30.36#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:30.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:21:30.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:21:30.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:21:30.41#ibcon#enter wrdev, iclass 35, count 2 2006.182.08:21:30.41#ibcon#first serial, iclass 35, count 2 2006.182.08:21:30.41#ibcon#enter sib2, iclass 35, count 2 2006.182.08:21:30.41#ibcon#flushed, iclass 35, count 2 2006.182.08:21:30.41#ibcon#about to write, iclass 35, count 2 2006.182.08:21:30.41#ibcon#wrote, iclass 35, count 2 2006.182.08:21:30.41#ibcon#about to read 3, iclass 35, count 2 2006.182.08:21:30.43#ibcon#read 3, iclass 35, count 2 2006.182.08:21:30.43#ibcon#about to read 4, iclass 35, count 2 2006.182.08:21:30.43#ibcon#read 4, iclass 35, count 2 2006.182.08:21:30.43#ibcon#about to read 5, iclass 35, count 2 2006.182.08:21:30.43#ibcon#read 5, iclass 35, count 2 2006.182.08:21:30.43#ibcon#about to read 6, iclass 35, count 2 2006.182.08:21:30.43#ibcon#read 6, iclass 35, count 2 2006.182.08:21:30.43#ibcon#end of sib2, iclass 35, count 2 2006.182.08:21:30.43#ibcon#*mode == 0, iclass 35, count 2 2006.182.08:21:30.43#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.182.08:21:30.43#ibcon#[25=AT08-07\r\n] 2006.182.08:21:30.43#ibcon#*before write, iclass 35, count 2 2006.182.08:21:30.43#ibcon#enter sib2, iclass 35, count 2 2006.182.08:21:30.43#ibcon#flushed, iclass 35, count 2 2006.182.08:21:30.43#ibcon#about to write, iclass 35, count 2 2006.182.08:21:30.43#ibcon#wrote, iclass 35, count 2 2006.182.08:21:30.43#ibcon#about to read 3, iclass 35, count 2 2006.182.08:21:30.46#ibcon#read 3, iclass 35, count 2 2006.182.08:21:30.46#ibcon#about to read 4, iclass 35, count 2 2006.182.08:21:30.46#ibcon#read 4, iclass 35, count 2 2006.182.08:21:30.46#ibcon#about to read 5, iclass 35, count 2 2006.182.08:21:30.46#ibcon#read 5, iclass 35, count 2 2006.182.08:21:30.46#ibcon#about to read 6, iclass 35, count 2 2006.182.08:21:30.46#ibcon#read 6, iclass 35, count 2 2006.182.08:21:30.46#ibcon#end of sib2, iclass 35, count 2 2006.182.08:21:30.46#ibcon#*after write, iclass 35, count 2 2006.182.08:21:30.46#ibcon#*before return 0, iclass 35, count 2 2006.182.08:21:30.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:21:30.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.182.08:21:30.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.182.08:21:30.46#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:30.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:21:30.58#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:21:30.58#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:21:30.58#ibcon#enter wrdev, iclass 35, count 0 2006.182.08:21:30.58#ibcon#first serial, iclass 35, count 0 2006.182.08:21:30.58#ibcon#enter sib2, iclass 35, count 0 2006.182.08:21:30.58#ibcon#flushed, iclass 35, count 0 2006.182.08:21:30.58#ibcon#about to write, iclass 35, count 0 2006.182.08:21:30.58#ibcon#wrote, iclass 35, count 0 2006.182.08:21:30.58#ibcon#about to read 3, iclass 35, count 0 2006.182.08:21:30.60#ibcon#read 3, iclass 35, count 0 2006.182.08:21:30.60#ibcon#about to read 4, iclass 35, count 0 2006.182.08:21:30.60#ibcon#read 4, iclass 35, count 0 2006.182.08:21:30.60#ibcon#about to read 5, iclass 35, count 0 2006.182.08:21:30.60#ibcon#read 5, iclass 35, count 0 2006.182.08:21:30.60#ibcon#about to read 6, iclass 35, count 0 2006.182.08:21:30.60#ibcon#read 6, iclass 35, count 0 2006.182.08:21:30.60#ibcon#end of sib2, iclass 35, count 0 2006.182.08:21:30.60#ibcon#*mode == 0, iclass 35, count 0 2006.182.08:21:30.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.182.08:21:30.60#ibcon#[25=USB\r\n] 2006.182.08:21:30.60#ibcon#*before write, iclass 35, count 0 2006.182.08:21:30.60#ibcon#enter sib2, iclass 35, count 0 2006.182.08:21:30.60#ibcon#flushed, iclass 35, count 0 2006.182.08:21:30.60#ibcon#about to write, iclass 35, count 0 2006.182.08:21:30.60#ibcon#wrote, iclass 35, count 0 2006.182.08:21:30.60#ibcon#about to read 3, iclass 35, count 0 2006.182.08:21:30.63#ibcon#read 3, iclass 35, count 0 2006.182.08:21:30.63#ibcon#about to read 4, iclass 35, count 0 2006.182.08:21:30.63#ibcon#read 4, iclass 35, count 0 2006.182.08:21:30.63#ibcon#about to read 5, iclass 35, count 0 2006.182.08:21:30.63#ibcon#read 5, iclass 35, count 0 2006.182.08:21:30.63#ibcon#about to read 6, iclass 35, count 0 2006.182.08:21:30.63#ibcon#read 6, iclass 35, count 0 2006.182.08:21:30.63#ibcon#end of sib2, iclass 35, count 0 2006.182.08:21:30.63#ibcon#*after write, iclass 35, count 0 2006.182.08:21:30.63#ibcon#*before return 0, iclass 35, count 0 2006.182.08:21:30.63#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:21:30.63#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.182.08:21:30.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.182.08:21:30.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.182.08:21:30.63$vc4f8/vblo=1,632.99 2006.182.08:21:30.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.182.08:21:30.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.182.08:21:30.63#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:30.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:21:30.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:21:30.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:21:30.63#ibcon#enter wrdev, iclass 37, count 0 2006.182.08:21:30.63#ibcon#first serial, iclass 37, count 0 2006.182.08:21:30.63#ibcon#enter sib2, iclass 37, count 0 2006.182.08:21:30.63#ibcon#flushed, iclass 37, count 0 2006.182.08:21:30.63#ibcon#about to write, iclass 37, count 0 2006.182.08:21:30.63#ibcon#wrote, iclass 37, count 0 2006.182.08:21:30.63#ibcon#about to read 3, iclass 37, count 0 2006.182.08:21:30.65#ibcon#read 3, iclass 37, count 0 2006.182.08:21:30.65#ibcon#about to read 4, iclass 37, count 0 2006.182.08:21:30.65#ibcon#read 4, iclass 37, count 0 2006.182.08:21:30.65#ibcon#about to read 5, iclass 37, count 0 2006.182.08:21:30.65#ibcon#read 5, iclass 37, count 0 2006.182.08:21:30.65#ibcon#about to read 6, iclass 37, count 0 2006.182.08:21:30.65#ibcon#read 6, iclass 37, count 0 2006.182.08:21:30.65#ibcon#end of sib2, iclass 37, count 0 2006.182.08:21:30.65#ibcon#*mode == 0, iclass 37, count 0 2006.182.08:21:30.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.182.08:21:30.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:21:30.65#ibcon#*before write, iclass 37, count 0 2006.182.08:21:30.65#ibcon#enter sib2, iclass 37, count 0 2006.182.08:21:30.65#ibcon#flushed, iclass 37, count 0 2006.182.08:21:30.65#ibcon#about to write, iclass 37, count 0 2006.182.08:21:30.65#ibcon#wrote, iclass 37, count 0 2006.182.08:21:30.65#ibcon#about to read 3, iclass 37, count 0 2006.182.08:21:30.69#ibcon#read 3, iclass 37, count 0 2006.182.08:21:30.69#ibcon#about to read 4, iclass 37, count 0 2006.182.08:21:30.69#ibcon#read 4, iclass 37, count 0 2006.182.08:21:30.69#ibcon#about to read 5, iclass 37, count 0 2006.182.08:21:30.69#ibcon#read 5, iclass 37, count 0 2006.182.08:21:30.69#ibcon#about to read 6, iclass 37, count 0 2006.182.08:21:30.69#ibcon#read 6, iclass 37, count 0 2006.182.08:21:30.69#ibcon#end of sib2, iclass 37, count 0 2006.182.08:21:30.69#ibcon#*after write, iclass 37, count 0 2006.182.08:21:30.69#ibcon#*before return 0, iclass 37, count 0 2006.182.08:21:30.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:21:30.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.182.08:21:30.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.182.08:21:30.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.182.08:21:30.69$vc4f8/vb=1,4 2006.182.08:21:30.69#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.182.08:21:30.69#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.182.08:21:30.69#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:30.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:21:30.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:21:30.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:21:30.69#ibcon#enter wrdev, iclass 39, count 2 2006.182.08:21:30.69#ibcon#first serial, iclass 39, count 2 2006.182.08:21:30.69#ibcon#enter sib2, iclass 39, count 2 2006.182.08:21:30.69#ibcon#flushed, iclass 39, count 2 2006.182.08:21:30.69#ibcon#about to write, iclass 39, count 2 2006.182.08:21:30.69#ibcon#wrote, iclass 39, count 2 2006.182.08:21:30.69#ibcon#about to read 3, iclass 39, count 2 2006.182.08:21:30.71#ibcon#read 3, iclass 39, count 2 2006.182.08:21:30.71#ibcon#about to read 4, iclass 39, count 2 2006.182.08:21:30.71#ibcon#read 4, iclass 39, count 2 2006.182.08:21:30.71#ibcon#about to read 5, iclass 39, count 2 2006.182.08:21:30.71#ibcon#read 5, iclass 39, count 2 2006.182.08:21:30.71#ibcon#about to read 6, iclass 39, count 2 2006.182.08:21:30.71#ibcon#read 6, iclass 39, count 2 2006.182.08:21:30.71#ibcon#end of sib2, iclass 39, count 2 2006.182.08:21:30.71#ibcon#*mode == 0, iclass 39, count 2 2006.182.08:21:30.71#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.182.08:21:30.71#ibcon#[27=AT01-04\r\n] 2006.182.08:21:30.71#ibcon#*before write, iclass 39, count 2 2006.182.08:21:30.71#ibcon#enter sib2, iclass 39, count 2 2006.182.08:21:30.71#ibcon#flushed, iclass 39, count 2 2006.182.08:21:30.71#ibcon#about to write, iclass 39, count 2 2006.182.08:21:30.71#ibcon#wrote, iclass 39, count 2 2006.182.08:21:30.71#ibcon#about to read 3, iclass 39, count 2 2006.182.08:21:30.74#ibcon#read 3, iclass 39, count 2 2006.182.08:21:30.74#ibcon#about to read 4, iclass 39, count 2 2006.182.08:21:30.74#ibcon#read 4, iclass 39, count 2 2006.182.08:21:30.74#ibcon#about to read 5, iclass 39, count 2 2006.182.08:21:30.74#ibcon#read 5, iclass 39, count 2 2006.182.08:21:30.74#ibcon#about to read 6, iclass 39, count 2 2006.182.08:21:30.74#ibcon#read 6, iclass 39, count 2 2006.182.08:21:30.74#ibcon#end of sib2, iclass 39, count 2 2006.182.08:21:30.74#ibcon#*after write, iclass 39, count 2 2006.182.08:21:30.74#ibcon#*before return 0, iclass 39, count 2 2006.182.08:21:30.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:21:30.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.182.08:21:30.74#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.182.08:21:30.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:30.74#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:21:30.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:21:30.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:21:30.86#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:21:30.86#ibcon#first serial, iclass 39, count 0 2006.182.08:21:30.86#ibcon#enter sib2, iclass 39, count 0 2006.182.08:21:30.86#ibcon#flushed, iclass 39, count 0 2006.182.08:21:30.86#ibcon#about to write, iclass 39, count 0 2006.182.08:21:30.86#ibcon#wrote, iclass 39, count 0 2006.182.08:21:30.86#ibcon#about to read 3, iclass 39, count 0 2006.182.08:21:30.88#ibcon#read 3, iclass 39, count 0 2006.182.08:21:30.88#ibcon#about to read 4, iclass 39, count 0 2006.182.08:21:30.88#ibcon#read 4, iclass 39, count 0 2006.182.08:21:30.88#ibcon#about to read 5, iclass 39, count 0 2006.182.08:21:30.88#ibcon#read 5, iclass 39, count 0 2006.182.08:21:30.88#ibcon#about to read 6, iclass 39, count 0 2006.182.08:21:30.88#ibcon#read 6, iclass 39, count 0 2006.182.08:21:30.88#ibcon#end of sib2, iclass 39, count 0 2006.182.08:21:30.88#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:21:30.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:21:30.88#ibcon#[27=USB\r\n] 2006.182.08:21:30.88#ibcon#*before write, iclass 39, count 0 2006.182.08:21:30.88#ibcon#enter sib2, iclass 39, count 0 2006.182.08:21:30.88#ibcon#flushed, iclass 39, count 0 2006.182.08:21:30.88#ibcon#about to write, iclass 39, count 0 2006.182.08:21:30.88#ibcon#wrote, iclass 39, count 0 2006.182.08:21:30.88#ibcon#about to read 3, iclass 39, count 0 2006.182.08:21:30.91#ibcon#read 3, iclass 39, count 0 2006.182.08:21:30.91#ibcon#about to read 4, iclass 39, count 0 2006.182.08:21:30.91#ibcon#read 4, iclass 39, count 0 2006.182.08:21:30.91#ibcon#about to read 5, iclass 39, count 0 2006.182.08:21:30.91#ibcon#read 5, iclass 39, count 0 2006.182.08:21:30.91#ibcon#about to read 6, iclass 39, count 0 2006.182.08:21:30.91#ibcon#read 6, iclass 39, count 0 2006.182.08:21:30.91#ibcon#end of sib2, iclass 39, count 0 2006.182.08:21:30.91#ibcon#*after write, iclass 39, count 0 2006.182.08:21:30.91#ibcon#*before return 0, iclass 39, count 0 2006.182.08:21:30.91#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:21:30.91#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.182.08:21:30.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:21:30.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:21:30.91$vc4f8/vblo=2,640.99 2006.182.08:21:30.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.182.08:21:30.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.182.08:21:30.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:30.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:30.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:30.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:30.91#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:21:30.91#ibcon#first serial, iclass 3, count 0 2006.182.08:21:30.91#ibcon#enter sib2, iclass 3, count 0 2006.182.08:21:30.91#ibcon#flushed, iclass 3, count 0 2006.182.08:21:30.91#ibcon#about to write, iclass 3, count 0 2006.182.08:21:30.91#ibcon#wrote, iclass 3, count 0 2006.182.08:21:30.91#ibcon#about to read 3, iclass 3, count 0 2006.182.08:21:30.93#ibcon#read 3, iclass 3, count 0 2006.182.08:21:30.93#ibcon#about to read 4, iclass 3, count 0 2006.182.08:21:30.93#ibcon#read 4, iclass 3, count 0 2006.182.08:21:30.93#ibcon#about to read 5, iclass 3, count 0 2006.182.08:21:30.93#ibcon#read 5, iclass 3, count 0 2006.182.08:21:30.93#ibcon#about to read 6, iclass 3, count 0 2006.182.08:21:30.93#ibcon#read 6, iclass 3, count 0 2006.182.08:21:30.93#ibcon#end of sib2, iclass 3, count 0 2006.182.08:21:30.93#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:21:30.93#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:21:30.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:21:30.93#ibcon#*before write, iclass 3, count 0 2006.182.08:21:30.93#ibcon#enter sib2, iclass 3, count 0 2006.182.08:21:30.93#ibcon#flushed, iclass 3, count 0 2006.182.08:21:30.93#ibcon#about to write, iclass 3, count 0 2006.182.08:21:30.93#ibcon#wrote, iclass 3, count 0 2006.182.08:21:30.93#ibcon#about to read 3, iclass 3, count 0 2006.182.08:21:30.97#ibcon#read 3, iclass 3, count 0 2006.182.08:21:30.97#ibcon#about to read 4, iclass 3, count 0 2006.182.08:21:30.97#ibcon#read 4, iclass 3, count 0 2006.182.08:21:30.97#ibcon#about to read 5, iclass 3, count 0 2006.182.08:21:30.97#ibcon#read 5, iclass 3, count 0 2006.182.08:21:30.97#ibcon#about to read 6, iclass 3, count 0 2006.182.08:21:30.97#ibcon#read 6, iclass 3, count 0 2006.182.08:21:30.97#ibcon#end of sib2, iclass 3, count 0 2006.182.08:21:30.97#ibcon#*after write, iclass 3, count 0 2006.182.08:21:30.97#ibcon#*before return 0, iclass 3, count 0 2006.182.08:21:30.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:30.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.182.08:21:30.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:21:30.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:21:30.97$vc4f8/vb=2,4 2006.182.08:21:30.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.182.08:21:30.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.182.08:21:30.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:30.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:31.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:31.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:31.03#ibcon#enter wrdev, iclass 5, count 2 2006.182.08:21:31.03#ibcon#first serial, iclass 5, count 2 2006.182.08:21:31.03#ibcon#enter sib2, iclass 5, count 2 2006.182.08:21:31.03#ibcon#flushed, iclass 5, count 2 2006.182.08:21:31.03#ibcon#about to write, iclass 5, count 2 2006.182.08:21:31.03#ibcon#wrote, iclass 5, count 2 2006.182.08:21:31.03#ibcon#about to read 3, iclass 5, count 2 2006.182.08:21:31.05#ibcon#read 3, iclass 5, count 2 2006.182.08:21:31.05#ibcon#about to read 4, iclass 5, count 2 2006.182.08:21:31.05#ibcon#read 4, iclass 5, count 2 2006.182.08:21:31.05#ibcon#about to read 5, iclass 5, count 2 2006.182.08:21:31.05#ibcon#read 5, iclass 5, count 2 2006.182.08:21:31.05#ibcon#about to read 6, iclass 5, count 2 2006.182.08:21:31.05#ibcon#read 6, iclass 5, count 2 2006.182.08:21:31.05#ibcon#end of sib2, iclass 5, count 2 2006.182.08:21:31.05#ibcon#*mode == 0, iclass 5, count 2 2006.182.08:21:31.05#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.182.08:21:31.05#ibcon#[27=AT02-04\r\n] 2006.182.08:21:31.05#ibcon#*before write, iclass 5, count 2 2006.182.08:21:31.05#ibcon#enter sib2, iclass 5, count 2 2006.182.08:21:31.05#ibcon#flushed, iclass 5, count 2 2006.182.08:21:31.05#ibcon#about to write, iclass 5, count 2 2006.182.08:21:31.05#ibcon#wrote, iclass 5, count 2 2006.182.08:21:31.05#ibcon#about to read 3, iclass 5, count 2 2006.182.08:21:31.08#ibcon#read 3, iclass 5, count 2 2006.182.08:21:31.08#ibcon#about to read 4, iclass 5, count 2 2006.182.08:21:31.08#ibcon#read 4, iclass 5, count 2 2006.182.08:21:31.08#ibcon#about to read 5, iclass 5, count 2 2006.182.08:21:31.08#ibcon#read 5, iclass 5, count 2 2006.182.08:21:31.08#ibcon#about to read 6, iclass 5, count 2 2006.182.08:21:31.08#ibcon#read 6, iclass 5, count 2 2006.182.08:21:31.08#ibcon#end of sib2, iclass 5, count 2 2006.182.08:21:31.08#ibcon#*after write, iclass 5, count 2 2006.182.08:21:31.08#ibcon#*before return 0, iclass 5, count 2 2006.182.08:21:31.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:31.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.182.08:21:31.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.182.08:21:31.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:31.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:31.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:31.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:31.20#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:21:31.20#ibcon#first serial, iclass 5, count 0 2006.182.08:21:31.20#ibcon#enter sib2, iclass 5, count 0 2006.182.08:21:31.20#ibcon#flushed, iclass 5, count 0 2006.182.08:21:31.20#ibcon#about to write, iclass 5, count 0 2006.182.08:21:31.20#ibcon#wrote, iclass 5, count 0 2006.182.08:21:31.20#ibcon#about to read 3, iclass 5, count 0 2006.182.08:21:31.23#ibcon#read 3, iclass 5, count 0 2006.182.08:21:31.23#ibcon#about to read 4, iclass 5, count 0 2006.182.08:21:31.23#ibcon#read 4, iclass 5, count 0 2006.182.08:21:31.23#ibcon#about to read 5, iclass 5, count 0 2006.182.08:21:31.23#ibcon#read 5, iclass 5, count 0 2006.182.08:21:31.23#ibcon#about to read 6, iclass 5, count 0 2006.182.08:21:31.23#ibcon#read 6, iclass 5, count 0 2006.182.08:21:31.23#ibcon#end of sib2, iclass 5, count 0 2006.182.08:21:31.23#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:21:31.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:21:31.23#ibcon#[27=USB\r\n] 2006.182.08:21:31.23#ibcon#*before write, iclass 5, count 0 2006.182.08:21:31.23#ibcon#enter sib2, iclass 5, count 0 2006.182.08:21:31.23#ibcon#flushed, iclass 5, count 0 2006.182.08:21:31.23#ibcon#about to write, iclass 5, count 0 2006.182.08:21:31.23#ibcon#wrote, iclass 5, count 0 2006.182.08:21:31.23#ibcon#about to read 3, iclass 5, count 0 2006.182.08:21:31.26#ibcon#read 3, iclass 5, count 0 2006.182.08:21:31.26#ibcon#about to read 4, iclass 5, count 0 2006.182.08:21:31.26#ibcon#read 4, iclass 5, count 0 2006.182.08:21:31.26#ibcon#about to read 5, iclass 5, count 0 2006.182.08:21:31.26#ibcon#read 5, iclass 5, count 0 2006.182.08:21:31.26#ibcon#about to read 6, iclass 5, count 0 2006.182.08:21:31.26#ibcon#read 6, iclass 5, count 0 2006.182.08:21:31.26#ibcon#end of sib2, iclass 5, count 0 2006.182.08:21:31.26#ibcon#*after write, iclass 5, count 0 2006.182.08:21:31.26#ibcon#*before return 0, iclass 5, count 0 2006.182.08:21:31.26#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:31.26#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.182.08:21:31.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:21:31.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:21:31.26$vc4f8/vblo=3,656.99 2006.182.08:21:31.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.182.08:21:31.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.182.08:21:31.26#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:31.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:31.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:31.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:31.26#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:21:31.26#ibcon#first serial, iclass 7, count 0 2006.182.08:21:31.26#ibcon#enter sib2, iclass 7, count 0 2006.182.08:21:31.26#ibcon#flushed, iclass 7, count 0 2006.182.08:21:31.26#ibcon#about to write, iclass 7, count 0 2006.182.08:21:31.26#ibcon#wrote, iclass 7, count 0 2006.182.08:21:31.26#ibcon#about to read 3, iclass 7, count 0 2006.182.08:21:31.28#ibcon#read 3, iclass 7, count 0 2006.182.08:21:31.28#ibcon#about to read 4, iclass 7, count 0 2006.182.08:21:31.28#ibcon#read 4, iclass 7, count 0 2006.182.08:21:31.28#ibcon#about to read 5, iclass 7, count 0 2006.182.08:21:31.28#ibcon#read 5, iclass 7, count 0 2006.182.08:21:31.28#ibcon#about to read 6, iclass 7, count 0 2006.182.08:21:31.28#ibcon#read 6, iclass 7, count 0 2006.182.08:21:31.28#ibcon#end of sib2, iclass 7, count 0 2006.182.08:21:31.28#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:21:31.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:21:31.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:21:31.28#ibcon#*before write, iclass 7, count 0 2006.182.08:21:31.28#ibcon#enter sib2, iclass 7, count 0 2006.182.08:21:31.28#ibcon#flushed, iclass 7, count 0 2006.182.08:21:31.28#ibcon#about to write, iclass 7, count 0 2006.182.08:21:31.28#ibcon#wrote, iclass 7, count 0 2006.182.08:21:31.28#ibcon#about to read 3, iclass 7, count 0 2006.182.08:21:31.32#ibcon#read 3, iclass 7, count 0 2006.182.08:21:31.32#ibcon#about to read 4, iclass 7, count 0 2006.182.08:21:31.32#ibcon#read 4, iclass 7, count 0 2006.182.08:21:31.32#ibcon#about to read 5, iclass 7, count 0 2006.182.08:21:31.32#ibcon#read 5, iclass 7, count 0 2006.182.08:21:31.32#ibcon#about to read 6, iclass 7, count 0 2006.182.08:21:31.32#ibcon#read 6, iclass 7, count 0 2006.182.08:21:31.32#ibcon#end of sib2, iclass 7, count 0 2006.182.08:21:31.32#ibcon#*after write, iclass 7, count 0 2006.182.08:21:31.32#ibcon#*before return 0, iclass 7, count 0 2006.182.08:21:31.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:31.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.182.08:21:31.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:21:31.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:21:31.32$vc4f8/vb=3,4 2006.182.08:21:31.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.182.08:21:31.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.182.08:21:31.32#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:31.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:31.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:31.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:31.38#ibcon#enter wrdev, iclass 11, count 2 2006.182.08:21:31.38#ibcon#first serial, iclass 11, count 2 2006.182.08:21:31.38#ibcon#enter sib2, iclass 11, count 2 2006.182.08:21:31.38#ibcon#flushed, iclass 11, count 2 2006.182.08:21:31.38#ibcon#about to write, iclass 11, count 2 2006.182.08:21:31.38#ibcon#wrote, iclass 11, count 2 2006.182.08:21:31.38#ibcon#about to read 3, iclass 11, count 2 2006.182.08:21:31.40#ibcon#read 3, iclass 11, count 2 2006.182.08:21:31.40#ibcon#about to read 4, iclass 11, count 2 2006.182.08:21:31.40#ibcon#read 4, iclass 11, count 2 2006.182.08:21:31.40#ibcon#about to read 5, iclass 11, count 2 2006.182.08:21:31.40#ibcon#read 5, iclass 11, count 2 2006.182.08:21:31.40#ibcon#about to read 6, iclass 11, count 2 2006.182.08:21:31.40#ibcon#read 6, iclass 11, count 2 2006.182.08:21:31.40#ibcon#end of sib2, iclass 11, count 2 2006.182.08:21:31.40#ibcon#*mode == 0, iclass 11, count 2 2006.182.08:21:31.40#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.182.08:21:31.40#ibcon#[27=AT03-04\r\n] 2006.182.08:21:31.40#ibcon#*before write, iclass 11, count 2 2006.182.08:21:31.40#ibcon#enter sib2, iclass 11, count 2 2006.182.08:21:31.40#ibcon#flushed, iclass 11, count 2 2006.182.08:21:31.40#ibcon#about to write, iclass 11, count 2 2006.182.08:21:31.40#ibcon#wrote, iclass 11, count 2 2006.182.08:21:31.40#ibcon#about to read 3, iclass 11, count 2 2006.182.08:21:31.43#ibcon#read 3, iclass 11, count 2 2006.182.08:21:31.43#ibcon#about to read 4, iclass 11, count 2 2006.182.08:21:31.43#ibcon#read 4, iclass 11, count 2 2006.182.08:21:31.43#ibcon#about to read 5, iclass 11, count 2 2006.182.08:21:31.43#ibcon#read 5, iclass 11, count 2 2006.182.08:21:31.43#ibcon#about to read 6, iclass 11, count 2 2006.182.08:21:31.43#ibcon#read 6, iclass 11, count 2 2006.182.08:21:31.43#ibcon#end of sib2, iclass 11, count 2 2006.182.08:21:31.43#ibcon#*after write, iclass 11, count 2 2006.182.08:21:31.43#ibcon#*before return 0, iclass 11, count 2 2006.182.08:21:31.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:31.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.182.08:21:31.43#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.182.08:21:31.43#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:31.43#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:31.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:31.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:31.55#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:21:31.55#ibcon#first serial, iclass 11, count 0 2006.182.08:21:31.55#ibcon#enter sib2, iclass 11, count 0 2006.182.08:21:31.55#ibcon#flushed, iclass 11, count 0 2006.182.08:21:31.55#ibcon#about to write, iclass 11, count 0 2006.182.08:21:31.55#ibcon#wrote, iclass 11, count 0 2006.182.08:21:31.55#ibcon#about to read 3, iclass 11, count 0 2006.182.08:21:31.57#ibcon#read 3, iclass 11, count 0 2006.182.08:21:31.57#ibcon#about to read 4, iclass 11, count 0 2006.182.08:21:31.57#ibcon#read 4, iclass 11, count 0 2006.182.08:21:31.57#ibcon#about to read 5, iclass 11, count 0 2006.182.08:21:31.57#ibcon#read 5, iclass 11, count 0 2006.182.08:21:31.57#ibcon#about to read 6, iclass 11, count 0 2006.182.08:21:31.57#ibcon#read 6, iclass 11, count 0 2006.182.08:21:31.57#ibcon#end of sib2, iclass 11, count 0 2006.182.08:21:31.57#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:21:31.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:21:31.57#ibcon#[27=USB\r\n] 2006.182.08:21:31.57#ibcon#*before write, iclass 11, count 0 2006.182.08:21:31.57#ibcon#enter sib2, iclass 11, count 0 2006.182.08:21:31.57#ibcon#flushed, iclass 11, count 0 2006.182.08:21:31.57#ibcon#about to write, iclass 11, count 0 2006.182.08:21:31.57#ibcon#wrote, iclass 11, count 0 2006.182.08:21:31.57#ibcon#about to read 3, iclass 11, count 0 2006.182.08:21:31.60#ibcon#read 3, iclass 11, count 0 2006.182.08:21:31.60#ibcon#about to read 4, iclass 11, count 0 2006.182.08:21:31.60#ibcon#read 4, iclass 11, count 0 2006.182.08:21:31.60#ibcon#about to read 5, iclass 11, count 0 2006.182.08:21:31.60#ibcon#read 5, iclass 11, count 0 2006.182.08:21:31.60#ibcon#about to read 6, iclass 11, count 0 2006.182.08:21:31.60#ibcon#read 6, iclass 11, count 0 2006.182.08:21:31.60#ibcon#end of sib2, iclass 11, count 0 2006.182.08:21:31.60#ibcon#*after write, iclass 11, count 0 2006.182.08:21:31.60#ibcon#*before return 0, iclass 11, count 0 2006.182.08:21:31.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:31.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.182.08:21:31.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:21:31.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:21:31.60$vc4f8/vblo=4,712.99 2006.182.08:21:31.60#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.182.08:21:31.60#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.182.08:21:31.60#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:31.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:31.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:31.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:31.60#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:21:31.60#ibcon#first serial, iclass 13, count 0 2006.182.08:21:31.60#ibcon#enter sib2, iclass 13, count 0 2006.182.08:21:31.60#ibcon#flushed, iclass 13, count 0 2006.182.08:21:31.60#ibcon#about to write, iclass 13, count 0 2006.182.08:21:31.60#ibcon#wrote, iclass 13, count 0 2006.182.08:21:31.60#ibcon#about to read 3, iclass 13, count 0 2006.182.08:21:31.62#ibcon#read 3, iclass 13, count 0 2006.182.08:21:31.62#ibcon#about to read 4, iclass 13, count 0 2006.182.08:21:31.62#ibcon#read 4, iclass 13, count 0 2006.182.08:21:31.62#ibcon#about to read 5, iclass 13, count 0 2006.182.08:21:31.62#ibcon#read 5, iclass 13, count 0 2006.182.08:21:31.62#ibcon#about to read 6, iclass 13, count 0 2006.182.08:21:31.62#ibcon#read 6, iclass 13, count 0 2006.182.08:21:31.62#ibcon#end of sib2, iclass 13, count 0 2006.182.08:21:31.62#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:21:31.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:21:31.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:21:31.62#ibcon#*before write, iclass 13, count 0 2006.182.08:21:31.62#ibcon#enter sib2, iclass 13, count 0 2006.182.08:21:31.62#ibcon#flushed, iclass 13, count 0 2006.182.08:21:31.62#ibcon#about to write, iclass 13, count 0 2006.182.08:21:31.62#ibcon#wrote, iclass 13, count 0 2006.182.08:21:31.62#ibcon#about to read 3, iclass 13, count 0 2006.182.08:21:31.66#ibcon#read 3, iclass 13, count 0 2006.182.08:21:31.66#ibcon#about to read 4, iclass 13, count 0 2006.182.08:21:31.66#ibcon#read 4, iclass 13, count 0 2006.182.08:21:31.66#ibcon#about to read 5, iclass 13, count 0 2006.182.08:21:31.66#ibcon#read 5, iclass 13, count 0 2006.182.08:21:31.66#ibcon#about to read 6, iclass 13, count 0 2006.182.08:21:31.66#ibcon#read 6, iclass 13, count 0 2006.182.08:21:31.66#ibcon#end of sib2, iclass 13, count 0 2006.182.08:21:31.66#ibcon#*after write, iclass 13, count 0 2006.182.08:21:31.66#ibcon#*before return 0, iclass 13, count 0 2006.182.08:21:31.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:31.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.182.08:21:31.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:21:31.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:21:31.66$vc4f8/vb=4,4 2006.182.08:21:31.66#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.182.08:21:31.66#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.182.08:21:31.66#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:31.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:31.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:31.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:31.72#ibcon#enter wrdev, iclass 15, count 2 2006.182.08:21:31.72#ibcon#first serial, iclass 15, count 2 2006.182.08:21:31.72#ibcon#enter sib2, iclass 15, count 2 2006.182.08:21:31.72#ibcon#flushed, iclass 15, count 2 2006.182.08:21:31.72#ibcon#about to write, iclass 15, count 2 2006.182.08:21:31.72#ibcon#wrote, iclass 15, count 2 2006.182.08:21:31.72#ibcon#about to read 3, iclass 15, count 2 2006.182.08:21:31.74#ibcon#read 3, iclass 15, count 2 2006.182.08:21:31.74#ibcon#about to read 4, iclass 15, count 2 2006.182.08:21:31.74#ibcon#read 4, iclass 15, count 2 2006.182.08:21:31.74#ibcon#about to read 5, iclass 15, count 2 2006.182.08:21:31.74#ibcon#read 5, iclass 15, count 2 2006.182.08:21:31.74#ibcon#about to read 6, iclass 15, count 2 2006.182.08:21:31.74#ibcon#read 6, iclass 15, count 2 2006.182.08:21:31.74#ibcon#end of sib2, iclass 15, count 2 2006.182.08:21:31.74#ibcon#*mode == 0, iclass 15, count 2 2006.182.08:21:31.74#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.182.08:21:31.74#ibcon#[27=AT04-04\r\n] 2006.182.08:21:31.74#ibcon#*before write, iclass 15, count 2 2006.182.08:21:31.74#ibcon#enter sib2, iclass 15, count 2 2006.182.08:21:31.74#ibcon#flushed, iclass 15, count 2 2006.182.08:21:31.74#ibcon#about to write, iclass 15, count 2 2006.182.08:21:31.74#ibcon#wrote, iclass 15, count 2 2006.182.08:21:31.74#ibcon#about to read 3, iclass 15, count 2 2006.182.08:21:31.77#ibcon#read 3, iclass 15, count 2 2006.182.08:21:31.77#ibcon#about to read 4, iclass 15, count 2 2006.182.08:21:31.77#ibcon#read 4, iclass 15, count 2 2006.182.08:21:31.77#ibcon#about to read 5, iclass 15, count 2 2006.182.08:21:31.77#ibcon#read 5, iclass 15, count 2 2006.182.08:21:31.77#ibcon#about to read 6, iclass 15, count 2 2006.182.08:21:31.77#ibcon#read 6, iclass 15, count 2 2006.182.08:21:31.77#ibcon#end of sib2, iclass 15, count 2 2006.182.08:21:31.77#ibcon#*after write, iclass 15, count 2 2006.182.08:21:31.77#ibcon#*before return 0, iclass 15, count 2 2006.182.08:21:31.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:31.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.182.08:21:31.77#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.182.08:21:31.77#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:31.77#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:31.89#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:31.89#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:31.89#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:21:31.89#ibcon#first serial, iclass 15, count 0 2006.182.08:21:31.89#ibcon#enter sib2, iclass 15, count 0 2006.182.08:21:31.89#ibcon#flushed, iclass 15, count 0 2006.182.08:21:31.89#ibcon#about to write, iclass 15, count 0 2006.182.08:21:31.89#ibcon#wrote, iclass 15, count 0 2006.182.08:21:31.89#ibcon#about to read 3, iclass 15, count 0 2006.182.08:21:31.91#ibcon#read 3, iclass 15, count 0 2006.182.08:21:31.91#ibcon#about to read 4, iclass 15, count 0 2006.182.08:21:31.91#ibcon#read 4, iclass 15, count 0 2006.182.08:21:31.91#ibcon#about to read 5, iclass 15, count 0 2006.182.08:21:31.91#ibcon#read 5, iclass 15, count 0 2006.182.08:21:31.91#ibcon#about to read 6, iclass 15, count 0 2006.182.08:21:31.91#ibcon#read 6, iclass 15, count 0 2006.182.08:21:31.91#ibcon#end of sib2, iclass 15, count 0 2006.182.08:21:31.91#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:21:31.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:21:31.91#ibcon#[27=USB\r\n] 2006.182.08:21:31.91#ibcon#*before write, iclass 15, count 0 2006.182.08:21:31.91#ibcon#enter sib2, iclass 15, count 0 2006.182.08:21:31.91#ibcon#flushed, iclass 15, count 0 2006.182.08:21:31.91#ibcon#about to write, iclass 15, count 0 2006.182.08:21:31.91#ibcon#wrote, iclass 15, count 0 2006.182.08:21:31.91#ibcon#about to read 3, iclass 15, count 0 2006.182.08:21:31.94#ibcon#read 3, iclass 15, count 0 2006.182.08:21:31.94#ibcon#about to read 4, iclass 15, count 0 2006.182.08:21:31.94#ibcon#read 4, iclass 15, count 0 2006.182.08:21:31.94#ibcon#about to read 5, iclass 15, count 0 2006.182.08:21:31.94#ibcon#read 5, iclass 15, count 0 2006.182.08:21:31.94#ibcon#about to read 6, iclass 15, count 0 2006.182.08:21:31.94#ibcon#read 6, iclass 15, count 0 2006.182.08:21:31.94#ibcon#end of sib2, iclass 15, count 0 2006.182.08:21:31.94#ibcon#*after write, iclass 15, count 0 2006.182.08:21:31.94#ibcon#*before return 0, iclass 15, count 0 2006.182.08:21:31.94#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:31.94#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.182.08:21:31.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:21:31.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:21:31.94$vc4f8/vblo=5,744.99 2006.182.08:21:31.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.182.08:21:31.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.182.08:21:31.94#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:31.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:31.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:31.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:31.94#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:21:31.94#ibcon#first serial, iclass 17, count 0 2006.182.08:21:31.94#ibcon#enter sib2, iclass 17, count 0 2006.182.08:21:31.94#ibcon#flushed, iclass 17, count 0 2006.182.08:21:31.94#ibcon#about to write, iclass 17, count 0 2006.182.08:21:31.94#ibcon#wrote, iclass 17, count 0 2006.182.08:21:31.94#ibcon#about to read 3, iclass 17, count 0 2006.182.08:21:31.96#ibcon#read 3, iclass 17, count 0 2006.182.08:21:31.96#ibcon#about to read 4, iclass 17, count 0 2006.182.08:21:31.96#ibcon#read 4, iclass 17, count 0 2006.182.08:21:31.96#ibcon#about to read 5, iclass 17, count 0 2006.182.08:21:31.96#ibcon#read 5, iclass 17, count 0 2006.182.08:21:31.96#ibcon#about to read 6, iclass 17, count 0 2006.182.08:21:31.96#ibcon#read 6, iclass 17, count 0 2006.182.08:21:31.96#ibcon#end of sib2, iclass 17, count 0 2006.182.08:21:31.96#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:21:31.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:21:31.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:21:31.96#ibcon#*before write, iclass 17, count 0 2006.182.08:21:31.96#ibcon#enter sib2, iclass 17, count 0 2006.182.08:21:31.96#ibcon#flushed, iclass 17, count 0 2006.182.08:21:31.96#ibcon#about to write, iclass 17, count 0 2006.182.08:21:31.96#ibcon#wrote, iclass 17, count 0 2006.182.08:21:31.96#ibcon#about to read 3, iclass 17, count 0 2006.182.08:21:32.01#ibcon#read 3, iclass 17, count 0 2006.182.08:21:32.01#ibcon#about to read 4, iclass 17, count 0 2006.182.08:21:32.01#ibcon#read 4, iclass 17, count 0 2006.182.08:21:32.01#ibcon#about to read 5, iclass 17, count 0 2006.182.08:21:32.01#ibcon#read 5, iclass 17, count 0 2006.182.08:21:32.01#ibcon#about to read 6, iclass 17, count 0 2006.182.08:21:32.01#ibcon#read 6, iclass 17, count 0 2006.182.08:21:32.01#ibcon#end of sib2, iclass 17, count 0 2006.182.08:21:32.01#ibcon#*after write, iclass 17, count 0 2006.182.08:21:32.01#ibcon#*before return 0, iclass 17, count 0 2006.182.08:21:32.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:32.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.182.08:21:32.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:21:32.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:21:32.01$vc4f8/vb=5,4 2006.182.08:21:32.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.182.08:21:32.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.182.08:21:32.01#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:32.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:32.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:32.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:32.06#ibcon#enter wrdev, iclass 19, count 2 2006.182.08:21:32.06#ibcon#first serial, iclass 19, count 2 2006.182.08:21:32.06#ibcon#enter sib2, iclass 19, count 2 2006.182.08:21:32.06#ibcon#flushed, iclass 19, count 2 2006.182.08:21:32.06#ibcon#about to write, iclass 19, count 2 2006.182.08:21:32.06#ibcon#wrote, iclass 19, count 2 2006.182.08:21:32.06#ibcon#about to read 3, iclass 19, count 2 2006.182.08:21:32.08#ibcon#read 3, iclass 19, count 2 2006.182.08:21:32.08#ibcon#about to read 4, iclass 19, count 2 2006.182.08:21:32.08#ibcon#read 4, iclass 19, count 2 2006.182.08:21:32.08#ibcon#about to read 5, iclass 19, count 2 2006.182.08:21:32.08#ibcon#read 5, iclass 19, count 2 2006.182.08:21:32.08#ibcon#about to read 6, iclass 19, count 2 2006.182.08:21:32.08#ibcon#read 6, iclass 19, count 2 2006.182.08:21:32.08#ibcon#end of sib2, iclass 19, count 2 2006.182.08:21:32.08#ibcon#*mode == 0, iclass 19, count 2 2006.182.08:21:32.08#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.182.08:21:32.08#ibcon#[27=AT05-04\r\n] 2006.182.08:21:32.08#ibcon#*before write, iclass 19, count 2 2006.182.08:21:32.08#ibcon#enter sib2, iclass 19, count 2 2006.182.08:21:32.08#ibcon#flushed, iclass 19, count 2 2006.182.08:21:32.08#ibcon#about to write, iclass 19, count 2 2006.182.08:21:32.08#ibcon#wrote, iclass 19, count 2 2006.182.08:21:32.08#ibcon#about to read 3, iclass 19, count 2 2006.182.08:21:32.11#ibcon#read 3, iclass 19, count 2 2006.182.08:21:32.11#ibcon#about to read 4, iclass 19, count 2 2006.182.08:21:32.11#ibcon#read 4, iclass 19, count 2 2006.182.08:21:32.11#ibcon#about to read 5, iclass 19, count 2 2006.182.08:21:32.11#ibcon#read 5, iclass 19, count 2 2006.182.08:21:32.11#ibcon#about to read 6, iclass 19, count 2 2006.182.08:21:32.11#ibcon#read 6, iclass 19, count 2 2006.182.08:21:32.11#ibcon#end of sib2, iclass 19, count 2 2006.182.08:21:32.11#ibcon#*after write, iclass 19, count 2 2006.182.08:21:32.11#ibcon#*before return 0, iclass 19, count 2 2006.182.08:21:32.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:32.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.182.08:21:32.11#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.182.08:21:32.11#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:32.11#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:32.23#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:32.23#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:32.23#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:21:32.23#ibcon#first serial, iclass 19, count 0 2006.182.08:21:32.23#ibcon#enter sib2, iclass 19, count 0 2006.182.08:21:32.23#ibcon#flushed, iclass 19, count 0 2006.182.08:21:32.23#ibcon#about to write, iclass 19, count 0 2006.182.08:21:32.23#ibcon#wrote, iclass 19, count 0 2006.182.08:21:32.23#ibcon#about to read 3, iclass 19, count 0 2006.182.08:21:32.25#ibcon#read 3, iclass 19, count 0 2006.182.08:21:32.25#ibcon#about to read 4, iclass 19, count 0 2006.182.08:21:32.25#ibcon#read 4, iclass 19, count 0 2006.182.08:21:32.25#ibcon#about to read 5, iclass 19, count 0 2006.182.08:21:32.25#ibcon#read 5, iclass 19, count 0 2006.182.08:21:32.25#ibcon#about to read 6, iclass 19, count 0 2006.182.08:21:32.25#ibcon#read 6, iclass 19, count 0 2006.182.08:21:32.25#ibcon#end of sib2, iclass 19, count 0 2006.182.08:21:32.25#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:21:32.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:21:32.25#ibcon#[27=USB\r\n] 2006.182.08:21:32.25#ibcon#*before write, iclass 19, count 0 2006.182.08:21:32.25#ibcon#enter sib2, iclass 19, count 0 2006.182.08:21:32.25#ibcon#flushed, iclass 19, count 0 2006.182.08:21:32.25#ibcon#about to write, iclass 19, count 0 2006.182.08:21:32.25#ibcon#wrote, iclass 19, count 0 2006.182.08:21:32.25#ibcon#about to read 3, iclass 19, count 0 2006.182.08:21:32.28#ibcon#read 3, iclass 19, count 0 2006.182.08:21:32.28#ibcon#about to read 4, iclass 19, count 0 2006.182.08:21:32.28#ibcon#read 4, iclass 19, count 0 2006.182.08:21:32.28#ibcon#about to read 5, iclass 19, count 0 2006.182.08:21:32.28#ibcon#read 5, iclass 19, count 0 2006.182.08:21:32.28#ibcon#about to read 6, iclass 19, count 0 2006.182.08:21:32.28#ibcon#read 6, iclass 19, count 0 2006.182.08:21:32.28#ibcon#end of sib2, iclass 19, count 0 2006.182.08:21:32.28#ibcon#*after write, iclass 19, count 0 2006.182.08:21:32.28#ibcon#*before return 0, iclass 19, count 0 2006.182.08:21:32.28#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:32.28#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.182.08:21:32.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:21:32.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:21:32.28$vc4f8/vblo=6,752.99 2006.182.08:21:32.28#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.182.08:21:32.28#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.182.08:21:32.28#ibcon#ireg 17 cls_cnt 0 2006.182.08:21:32.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:32.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:32.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:32.28#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:21:32.28#ibcon#first serial, iclass 21, count 0 2006.182.08:21:32.28#ibcon#enter sib2, iclass 21, count 0 2006.182.08:21:32.28#ibcon#flushed, iclass 21, count 0 2006.182.08:21:32.28#ibcon#about to write, iclass 21, count 0 2006.182.08:21:32.28#ibcon#wrote, iclass 21, count 0 2006.182.08:21:32.28#ibcon#about to read 3, iclass 21, count 0 2006.182.08:21:32.30#ibcon#read 3, iclass 21, count 0 2006.182.08:21:32.30#ibcon#about to read 4, iclass 21, count 0 2006.182.08:21:32.30#ibcon#read 4, iclass 21, count 0 2006.182.08:21:32.30#ibcon#about to read 5, iclass 21, count 0 2006.182.08:21:32.30#ibcon#read 5, iclass 21, count 0 2006.182.08:21:32.30#ibcon#about to read 6, iclass 21, count 0 2006.182.08:21:32.30#ibcon#read 6, iclass 21, count 0 2006.182.08:21:32.30#ibcon#end of sib2, iclass 21, count 0 2006.182.08:21:32.30#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:21:32.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:21:32.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:21:32.30#ibcon#*before write, iclass 21, count 0 2006.182.08:21:32.30#ibcon#enter sib2, iclass 21, count 0 2006.182.08:21:32.30#ibcon#flushed, iclass 21, count 0 2006.182.08:21:32.30#ibcon#about to write, iclass 21, count 0 2006.182.08:21:32.30#ibcon#wrote, iclass 21, count 0 2006.182.08:21:32.30#ibcon#about to read 3, iclass 21, count 0 2006.182.08:21:32.34#ibcon#read 3, iclass 21, count 0 2006.182.08:21:32.34#ibcon#about to read 4, iclass 21, count 0 2006.182.08:21:32.34#ibcon#read 4, iclass 21, count 0 2006.182.08:21:32.34#ibcon#about to read 5, iclass 21, count 0 2006.182.08:21:32.34#ibcon#read 5, iclass 21, count 0 2006.182.08:21:32.34#ibcon#about to read 6, iclass 21, count 0 2006.182.08:21:32.34#ibcon#read 6, iclass 21, count 0 2006.182.08:21:32.34#ibcon#end of sib2, iclass 21, count 0 2006.182.08:21:32.34#ibcon#*after write, iclass 21, count 0 2006.182.08:21:32.34#ibcon#*before return 0, iclass 21, count 0 2006.182.08:21:32.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:32.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.182.08:21:32.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:21:32.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:21:32.34$vc4f8/vb=6,4 2006.182.08:21:32.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.182.08:21:32.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.182.08:21:32.34#ibcon#ireg 11 cls_cnt 2 2006.182.08:21:32.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:32.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:32.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:32.40#ibcon#enter wrdev, iclass 23, count 2 2006.182.08:21:32.40#ibcon#first serial, iclass 23, count 2 2006.182.08:21:32.40#ibcon#enter sib2, iclass 23, count 2 2006.182.08:21:32.40#ibcon#flushed, iclass 23, count 2 2006.182.08:21:32.40#ibcon#about to write, iclass 23, count 2 2006.182.08:21:32.40#ibcon#wrote, iclass 23, count 2 2006.182.08:21:32.40#ibcon#about to read 3, iclass 23, count 2 2006.182.08:21:32.42#ibcon#read 3, iclass 23, count 2 2006.182.08:21:32.42#ibcon#about to read 4, iclass 23, count 2 2006.182.08:21:32.42#ibcon#read 4, iclass 23, count 2 2006.182.08:21:32.42#ibcon#about to read 5, iclass 23, count 2 2006.182.08:21:32.42#ibcon#read 5, iclass 23, count 2 2006.182.08:21:32.42#ibcon#about to read 6, iclass 23, count 2 2006.182.08:21:32.42#ibcon#read 6, iclass 23, count 2 2006.182.08:21:32.42#ibcon#end of sib2, iclass 23, count 2 2006.182.08:21:32.42#ibcon#*mode == 0, iclass 23, count 2 2006.182.08:21:32.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.182.08:21:32.42#ibcon#[27=AT06-04\r\n] 2006.182.08:21:32.42#ibcon#*before write, iclass 23, count 2 2006.182.08:21:32.42#ibcon#enter sib2, iclass 23, count 2 2006.182.08:21:32.42#ibcon#flushed, iclass 23, count 2 2006.182.08:21:32.42#ibcon#about to write, iclass 23, count 2 2006.182.08:21:32.42#ibcon#wrote, iclass 23, count 2 2006.182.08:21:32.42#ibcon#about to read 3, iclass 23, count 2 2006.182.08:21:32.45#ibcon#read 3, iclass 23, count 2 2006.182.08:21:32.45#ibcon#about to read 4, iclass 23, count 2 2006.182.08:21:32.45#ibcon#read 4, iclass 23, count 2 2006.182.08:21:32.45#ibcon#about to read 5, iclass 23, count 2 2006.182.08:21:32.45#ibcon#read 5, iclass 23, count 2 2006.182.08:21:32.45#ibcon#about to read 6, iclass 23, count 2 2006.182.08:21:32.45#ibcon#read 6, iclass 23, count 2 2006.182.08:21:32.45#ibcon#end of sib2, iclass 23, count 2 2006.182.08:21:32.45#ibcon#*after write, iclass 23, count 2 2006.182.08:21:32.45#ibcon#*before return 0, iclass 23, count 2 2006.182.08:21:32.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:32.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.182.08:21:32.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.182.08:21:32.45#ibcon#ireg 7 cls_cnt 0 2006.182.08:21:32.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:32.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:32.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:32.57#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:21:32.57#ibcon#first serial, iclass 23, count 0 2006.182.08:21:32.57#ibcon#enter sib2, iclass 23, count 0 2006.182.08:21:32.57#ibcon#flushed, iclass 23, count 0 2006.182.08:21:32.57#ibcon#about to write, iclass 23, count 0 2006.182.08:21:32.57#ibcon#wrote, iclass 23, count 0 2006.182.08:21:32.57#ibcon#about to read 3, iclass 23, count 0 2006.182.08:21:32.59#ibcon#read 3, iclass 23, count 0 2006.182.08:21:32.59#ibcon#about to read 4, iclass 23, count 0 2006.182.08:21:32.59#ibcon#read 4, iclass 23, count 0 2006.182.08:21:32.59#ibcon#about to read 5, iclass 23, count 0 2006.182.08:21:32.59#ibcon#read 5, iclass 23, count 0 2006.182.08:21:32.59#ibcon#about to read 6, iclass 23, count 0 2006.182.08:21:32.59#ibcon#read 6, iclass 23, count 0 2006.182.08:21:32.59#ibcon#end of sib2, iclass 23, count 0 2006.182.08:21:32.59#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:21:32.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:21:32.59#ibcon#[27=USB\r\n] 2006.182.08:21:32.59#ibcon#*before write, iclass 23, count 0 2006.182.08:21:32.59#ibcon#enter sib2, iclass 23, count 0 2006.182.08:21:32.59#ibcon#flushed, iclass 23, count 0 2006.182.08:21:32.59#ibcon#about to write, iclass 23, count 0 2006.182.08:21:32.59#ibcon#wrote, iclass 23, count 0 2006.182.08:21:32.59#ibcon#about to read 3, iclass 23, count 0 2006.182.08:21:32.62#ibcon#read 3, iclass 23, count 0 2006.182.08:21:32.62#ibcon#about to read 4, iclass 23, count 0 2006.182.08:21:32.62#ibcon#read 4, iclass 23, count 0 2006.182.08:21:32.62#ibcon#about to read 5, iclass 23, count 0 2006.182.08:21:32.62#ibcon#read 5, iclass 23, count 0 2006.182.08:21:32.62#ibcon#about to read 6, iclass 23, count 0 2006.182.08:21:32.62#ibcon#read 6, iclass 23, count 0 2006.182.08:21:32.62#ibcon#end of sib2, iclass 23, count 0 2006.182.08:21:32.62#ibcon#*after write, iclass 23, count 0 2006.182.08:21:32.62#ibcon#*before return 0, iclass 23, count 0 2006.182.08:21:32.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:32.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.182.08:21:32.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:21:32.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:21:32.62$vc4f8/vabw=wide 2006.182.08:21:32.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.182.08:21:32.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.182.08:21:32.62#ibcon#ireg 8 cls_cnt 0 2006.182.08:21:32.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:32.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:32.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:32.62#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:21:32.62#ibcon#first serial, iclass 25, count 0 2006.182.08:21:32.62#ibcon#enter sib2, iclass 25, count 0 2006.182.08:21:32.62#ibcon#flushed, iclass 25, count 0 2006.182.08:21:32.62#ibcon#about to write, iclass 25, count 0 2006.182.08:21:32.62#ibcon#wrote, iclass 25, count 0 2006.182.08:21:32.62#ibcon#about to read 3, iclass 25, count 0 2006.182.08:21:32.64#ibcon#read 3, iclass 25, count 0 2006.182.08:21:32.64#ibcon#about to read 4, iclass 25, count 0 2006.182.08:21:32.64#ibcon#read 4, iclass 25, count 0 2006.182.08:21:32.64#ibcon#about to read 5, iclass 25, count 0 2006.182.08:21:32.64#ibcon#read 5, iclass 25, count 0 2006.182.08:21:32.64#ibcon#about to read 6, iclass 25, count 0 2006.182.08:21:32.64#ibcon#read 6, iclass 25, count 0 2006.182.08:21:32.64#ibcon#end of sib2, iclass 25, count 0 2006.182.08:21:32.64#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:21:32.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:21:32.64#ibcon#[25=BW32\r\n] 2006.182.08:21:32.64#ibcon#*before write, iclass 25, count 0 2006.182.08:21:32.64#ibcon#enter sib2, iclass 25, count 0 2006.182.08:21:32.64#ibcon#flushed, iclass 25, count 0 2006.182.08:21:32.64#ibcon#about to write, iclass 25, count 0 2006.182.08:21:32.64#ibcon#wrote, iclass 25, count 0 2006.182.08:21:32.64#ibcon#about to read 3, iclass 25, count 0 2006.182.08:21:32.67#ibcon#read 3, iclass 25, count 0 2006.182.08:21:32.67#ibcon#about to read 4, iclass 25, count 0 2006.182.08:21:32.67#ibcon#read 4, iclass 25, count 0 2006.182.08:21:32.67#ibcon#about to read 5, iclass 25, count 0 2006.182.08:21:32.67#ibcon#read 5, iclass 25, count 0 2006.182.08:21:32.67#ibcon#about to read 6, iclass 25, count 0 2006.182.08:21:32.67#ibcon#read 6, iclass 25, count 0 2006.182.08:21:32.67#ibcon#end of sib2, iclass 25, count 0 2006.182.08:21:32.67#ibcon#*after write, iclass 25, count 0 2006.182.08:21:32.67#ibcon#*before return 0, iclass 25, count 0 2006.182.08:21:32.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:32.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.182.08:21:32.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:21:32.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:21:32.67$vc4f8/vbbw=wide 2006.182.08:21:32.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.08:21:32.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.08:21:32.67#ibcon#ireg 8 cls_cnt 0 2006.182.08:21:32.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:21:32.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:21:32.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:21:32.74#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:21:32.74#ibcon#first serial, iclass 27, count 0 2006.182.08:21:32.74#ibcon#enter sib2, iclass 27, count 0 2006.182.08:21:32.74#ibcon#flushed, iclass 27, count 0 2006.182.08:21:32.74#ibcon#about to write, iclass 27, count 0 2006.182.08:21:32.74#ibcon#wrote, iclass 27, count 0 2006.182.08:21:32.74#ibcon#about to read 3, iclass 27, count 0 2006.182.08:21:32.76#ibcon#read 3, iclass 27, count 0 2006.182.08:21:32.76#ibcon#about to read 4, iclass 27, count 0 2006.182.08:21:32.76#ibcon#read 4, iclass 27, count 0 2006.182.08:21:32.76#ibcon#about to read 5, iclass 27, count 0 2006.182.08:21:32.76#ibcon#read 5, iclass 27, count 0 2006.182.08:21:32.76#ibcon#about to read 6, iclass 27, count 0 2006.182.08:21:32.76#ibcon#read 6, iclass 27, count 0 2006.182.08:21:32.76#ibcon#end of sib2, iclass 27, count 0 2006.182.08:21:32.76#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:21:32.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:21:32.76#ibcon#[27=BW32\r\n] 2006.182.08:21:32.76#ibcon#*before write, iclass 27, count 0 2006.182.08:21:32.76#ibcon#enter sib2, iclass 27, count 0 2006.182.08:21:32.76#ibcon#flushed, iclass 27, count 0 2006.182.08:21:32.76#ibcon#about to write, iclass 27, count 0 2006.182.08:21:32.76#ibcon#wrote, iclass 27, count 0 2006.182.08:21:32.76#ibcon#about to read 3, iclass 27, count 0 2006.182.08:21:32.79#ibcon#read 3, iclass 27, count 0 2006.182.08:21:32.79#ibcon#about to read 4, iclass 27, count 0 2006.182.08:21:32.79#ibcon#read 4, iclass 27, count 0 2006.182.08:21:32.79#ibcon#about to read 5, iclass 27, count 0 2006.182.08:21:32.79#ibcon#read 5, iclass 27, count 0 2006.182.08:21:32.79#ibcon#about to read 6, iclass 27, count 0 2006.182.08:21:32.79#ibcon#read 6, iclass 27, count 0 2006.182.08:21:32.79#ibcon#end of sib2, iclass 27, count 0 2006.182.08:21:32.79#ibcon#*after write, iclass 27, count 0 2006.182.08:21:32.79#ibcon#*before return 0, iclass 27, count 0 2006.182.08:21:32.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:21:32.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:21:32.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:21:32.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:21:32.79$4f8m12a/ifd4f 2006.182.08:21:32.79$ifd4f/lo= 2006.182.08:21:32.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:21:32.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:21:32.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:21:32.79$ifd4f/patch= 2006.182.08:21:32.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:21:32.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:21:32.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:21:32.79$4f8m12a/"form=m,16.000,1:2 2006.182.08:21:32.79$4f8m12a/"tpicd 2006.182.08:21:32.79$4f8m12a/echo=off 2006.182.08:21:32.79$4f8m12a/xlog=off 2006.182.08:21:32.79:!2006.182.08:23:40 2006.182.08:22:01.14#trakl#Source acquired 2006.182.08:22:03.14#flagr#flagr/antenna,acquired 2006.182.08:23:40.00:preob 2006.182.08:23:40.14/onsource/TRACKING 2006.182.08:23:40.14:!2006.182.08:23:50 2006.182.08:23:50.00:data_valid=on 2006.182.08:23:50.00:midob 2006.182.08:23:51.14/onsource/TRACKING 2006.182.08:23:51.14/wx/27.70,1002.9,80 2006.182.08:23:51.32/cable/+6.4639E-03 2006.182.08:23:52.41/va/01,08,usb,yes,30,31 2006.182.08:23:52.41/va/02,07,usb,yes,30,31 2006.182.08:23:52.41/va/03,06,usb,yes,31,32 2006.182.08:23:52.41/va/04,07,usb,yes,31,33 2006.182.08:23:52.41/va/05,07,usb,yes,32,34 2006.182.08:23:52.41/va/06,06,usb,yes,31,31 2006.182.08:23:52.41/va/07,06,usb,yes,31,31 2006.182.08:23:52.41/va/08,07,usb,yes,30,29 2006.182.08:23:52.64/valo/01,532.99,yes,locked 2006.182.08:23:52.64/valo/02,572.99,yes,locked 2006.182.08:23:52.64/valo/03,672.99,yes,locked 2006.182.08:23:52.64/valo/04,832.99,yes,locked 2006.182.08:23:52.64/valo/05,652.99,yes,locked 2006.182.08:23:52.64/valo/06,772.99,yes,locked 2006.182.08:23:52.64/valo/07,832.99,yes,locked 2006.182.08:23:52.64/valo/08,852.99,yes,locked 2006.182.08:23:53.73/vb/01,04,usb,yes,30,28 2006.182.08:23:53.73/vb/02,04,usb,yes,31,33 2006.182.08:23:53.73/vb/03,04,usb,yes,28,31 2006.182.08:23:53.73/vb/04,04,usb,yes,29,29 2006.182.08:23:53.73/vb/05,04,usb,yes,27,31 2006.182.08:23:53.73/vb/06,04,usb,yes,28,31 2006.182.08:23:53.73/vb/07,04,usb,yes,30,30 2006.182.08:23:53.73/vb/08,04,usb,yes,28,31 2006.182.08:23:53.97/vblo/01,632.99,yes,locked 2006.182.08:23:53.97/vblo/02,640.99,yes,locked 2006.182.08:23:53.97/vblo/03,656.99,yes,locked 2006.182.08:23:53.97/vblo/04,712.99,yes,locked 2006.182.08:23:53.97/vblo/05,744.99,yes,locked 2006.182.08:23:53.97/vblo/06,752.99,yes,locked 2006.182.08:23:53.97/vblo/07,734.99,yes,locked 2006.182.08:23:53.97/vblo/08,744.99,yes,locked 2006.182.08:23:54.12/vabw/8 2006.182.08:23:54.27/vbbw/8 2006.182.08:23:54.36/xfe/off,on,14.5 2006.182.08:23:54.76/ifatt/23,28,28,28 2006.182.08:23:55.08/fmout-gps/S +3.52E-07 2006.182.08:23:55.12:!2006.182.08:24:50 2006.182.08:24:50.00:data_valid=off 2006.182.08:24:50.00:postob 2006.182.08:24:50.08/cable/+6.4622E-03 2006.182.08:24:50.09/wx/27.67,1002.9,80 2006.182.08:24:51.08/fmout-gps/S +3.51E-07 2006.182.08:24:51.08:scan_name=182-0825,k06182,60 2006.182.08:24:51.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.182.08:24:51.14#flagr#flagr/antenna,new-source 2006.182.08:24:52.14:checkk5 2006.182.08:24:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:24:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:24:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:24:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:24:54.00/chk_obsdata//k5ts1/T1820823??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:24:54.37/chk_obsdata//k5ts2/T1820823??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:24:54.74/chk_obsdata//k5ts3/T1820823??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:24:55.10/chk_obsdata//k5ts4/T1820823??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:24:55.79/k5log//k5ts1_log_newline 2006.182.08:24:56.48/k5log//k5ts2_log_newline 2006.182.08:24:57.17/k5log//k5ts3_log_newline 2006.182.08:24:57.85/k5log//k5ts4_log_newline 2006.182.08:24:57.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:24:57.88:4f8m12a=3 2006.182.08:24:57.88$4f8m12a/echo=on 2006.182.08:24:57.88$4f8m12a/pcalon 2006.182.08:24:57.88$pcalon/"no phase cal control is implemented here 2006.182.08:24:57.88$4f8m12a/"tpicd=stop 2006.182.08:24:57.88$4f8m12a/vc4f8 2006.182.08:24:57.88$vc4f8/valo=1,532.99 2006.182.08:24:57.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.08:24:57.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.08:24:57.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:24:57.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:24:57.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:24:57.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:24:57.89#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:24:57.89#ibcon#first serial, iclass 38, count 0 2006.182.08:24:57.89#ibcon#enter sib2, iclass 38, count 0 2006.182.08:24:57.89#ibcon#flushed, iclass 38, count 0 2006.182.08:24:57.89#ibcon#about to write, iclass 38, count 0 2006.182.08:24:57.89#ibcon#wrote, iclass 38, count 0 2006.182.08:24:57.89#ibcon#about to read 3, iclass 38, count 0 2006.182.08:24:57.92#ibcon#read 3, iclass 38, count 0 2006.182.08:24:57.92#ibcon#about to read 4, iclass 38, count 0 2006.182.08:24:57.92#ibcon#read 4, iclass 38, count 0 2006.182.08:24:57.92#ibcon#about to read 5, iclass 38, count 0 2006.182.08:24:57.92#ibcon#read 5, iclass 38, count 0 2006.182.08:24:57.92#ibcon#about to read 6, iclass 38, count 0 2006.182.08:24:57.92#ibcon#read 6, iclass 38, count 0 2006.182.08:24:57.92#ibcon#end of sib2, iclass 38, count 0 2006.182.08:24:57.92#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:24:57.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:24:57.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:24:57.92#ibcon#*before write, iclass 38, count 0 2006.182.08:24:57.92#ibcon#enter sib2, iclass 38, count 0 2006.182.08:24:57.92#ibcon#flushed, iclass 38, count 0 2006.182.08:24:57.92#ibcon#about to write, iclass 38, count 0 2006.182.08:24:57.92#ibcon#wrote, iclass 38, count 0 2006.182.08:24:57.92#ibcon#about to read 3, iclass 38, count 0 2006.182.08:24:57.97#ibcon#read 3, iclass 38, count 0 2006.182.08:24:57.97#ibcon#about to read 4, iclass 38, count 0 2006.182.08:24:57.97#ibcon#read 4, iclass 38, count 0 2006.182.08:24:57.97#ibcon#about to read 5, iclass 38, count 0 2006.182.08:24:57.97#ibcon#read 5, iclass 38, count 0 2006.182.08:24:57.97#ibcon#about to read 6, iclass 38, count 0 2006.182.08:24:57.97#ibcon#read 6, iclass 38, count 0 2006.182.08:24:57.97#ibcon#end of sib2, iclass 38, count 0 2006.182.08:24:57.97#ibcon#*after write, iclass 38, count 0 2006.182.08:24:57.97#ibcon#*before return 0, iclass 38, count 0 2006.182.08:24:57.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:24:57.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:24:57.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:24:57.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:24:57.97$vc4f8/va=1,8 2006.182.08:24:57.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.08:24:57.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.08:24:57.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:24:57.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:24:57.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:24:57.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:24:57.97#ibcon#enter wrdev, iclass 40, count 2 2006.182.08:24:57.97#ibcon#first serial, iclass 40, count 2 2006.182.08:24:57.97#ibcon#enter sib2, iclass 40, count 2 2006.182.08:24:57.97#ibcon#flushed, iclass 40, count 2 2006.182.08:24:57.97#ibcon#about to write, iclass 40, count 2 2006.182.08:24:57.97#ibcon#wrote, iclass 40, count 2 2006.182.08:24:57.97#ibcon#about to read 3, iclass 40, count 2 2006.182.08:24:57.99#ibcon#read 3, iclass 40, count 2 2006.182.08:24:57.99#ibcon#about to read 4, iclass 40, count 2 2006.182.08:24:57.99#ibcon#read 4, iclass 40, count 2 2006.182.08:24:57.99#ibcon#about to read 5, iclass 40, count 2 2006.182.08:24:57.99#ibcon#read 5, iclass 40, count 2 2006.182.08:24:57.99#ibcon#about to read 6, iclass 40, count 2 2006.182.08:24:57.99#ibcon#read 6, iclass 40, count 2 2006.182.08:24:57.99#ibcon#end of sib2, iclass 40, count 2 2006.182.08:24:57.99#ibcon#*mode == 0, iclass 40, count 2 2006.182.08:24:57.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.08:24:57.99#ibcon#[25=AT01-08\r\n] 2006.182.08:24:57.99#ibcon#*before write, iclass 40, count 2 2006.182.08:24:57.99#ibcon#enter sib2, iclass 40, count 2 2006.182.08:24:57.99#ibcon#flushed, iclass 40, count 2 2006.182.08:24:57.99#ibcon#about to write, iclass 40, count 2 2006.182.08:24:57.99#ibcon#wrote, iclass 40, count 2 2006.182.08:24:57.99#ibcon#about to read 3, iclass 40, count 2 2006.182.08:24:58.02#ibcon#read 3, iclass 40, count 2 2006.182.08:24:58.02#ibcon#about to read 4, iclass 40, count 2 2006.182.08:24:58.02#ibcon#read 4, iclass 40, count 2 2006.182.08:24:58.02#ibcon#about to read 5, iclass 40, count 2 2006.182.08:24:58.02#ibcon#read 5, iclass 40, count 2 2006.182.08:24:58.02#ibcon#about to read 6, iclass 40, count 2 2006.182.08:24:58.02#ibcon#read 6, iclass 40, count 2 2006.182.08:24:58.02#ibcon#end of sib2, iclass 40, count 2 2006.182.08:24:58.02#ibcon#*after write, iclass 40, count 2 2006.182.08:24:58.02#ibcon#*before return 0, iclass 40, count 2 2006.182.08:24:58.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:24:58.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:24:58.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.08:24:58.02#ibcon#ireg 7 cls_cnt 0 2006.182.08:24:58.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:24:58.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:24:58.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:24:58.14#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:24:58.14#ibcon#first serial, iclass 40, count 0 2006.182.08:24:58.14#ibcon#enter sib2, iclass 40, count 0 2006.182.08:24:58.14#ibcon#flushed, iclass 40, count 0 2006.182.08:24:58.14#ibcon#about to write, iclass 40, count 0 2006.182.08:24:58.14#ibcon#wrote, iclass 40, count 0 2006.182.08:24:58.14#ibcon#about to read 3, iclass 40, count 0 2006.182.08:24:58.16#ibcon#read 3, iclass 40, count 0 2006.182.08:24:58.16#ibcon#about to read 4, iclass 40, count 0 2006.182.08:24:58.16#ibcon#read 4, iclass 40, count 0 2006.182.08:24:58.16#ibcon#about to read 5, iclass 40, count 0 2006.182.08:24:58.16#ibcon#read 5, iclass 40, count 0 2006.182.08:24:58.16#ibcon#about to read 6, iclass 40, count 0 2006.182.08:24:58.16#ibcon#read 6, iclass 40, count 0 2006.182.08:24:58.16#ibcon#end of sib2, iclass 40, count 0 2006.182.08:24:58.16#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:24:58.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:24:58.16#ibcon#[25=USB\r\n] 2006.182.08:24:58.16#ibcon#*before write, iclass 40, count 0 2006.182.08:24:58.16#ibcon#enter sib2, iclass 40, count 0 2006.182.08:24:58.16#ibcon#flushed, iclass 40, count 0 2006.182.08:24:58.16#ibcon#about to write, iclass 40, count 0 2006.182.08:24:58.16#ibcon#wrote, iclass 40, count 0 2006.182.08:24:58.16#ibcon#about to read 3, iclass 40, count 0 2006.182.08:24:58.19#ibcon#read 3, iclass 40, count 0 2006.182.08:24:58.19#ibcon#about to read 4, iclass 40, count 0 2006.182.08:24:58.19#ibcon#read 4, iclass 40, count 0 2006.182.08:24:58.19#ibcon#about to read 5, iclass 40, count 0 2006.182.08:24:58.19#ibcon#read 5, iclass 40, count 0 2006.182.08:24:58.19#ibcon#about to read 6, iclass 40, count 0 2006.182.08:24:58.19#ibcon#read 6, iclass 40, count 0 2006.182.08:24:58.19#ibcon#end of sib2, iclass 40, count 0 2006.182.08:24:58.19#ibcon#*after write, iclass 40, count 0 2006.182.08:24:58.19#ibcon#*before return 0, iclass 40, count 0 2006.182.08:24:58.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:24:58.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:24:58.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:24:58.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:24:58.19$vc4f8/valo=2,572.99 2006.182.08:24:58.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.08:24:58.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.08:24:58.19#ibcon#ireg 17 cls_cnt 0 2006.182.08:24:58.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:24:58.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:24:58.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:24:58.19#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:24:58.19#ibcon#first serial, iclass 4, count 0 2006.182.08:24:58.19#ibcon#enter sib2, iclass 4, count 0 2006.182.08:24:58.19#ibcon#flushed, iclass 4, count 0 2006.182.08:24:58.19#ibcon#about to write, iclass 4, count 0 2006.182.08:24:58.19#ibcon#wrote, iclass 4, count 0 2006.182.08:24:58.19#ibcon#about to read 3, iclass 4, count 0 2006.182.08:24:58.21#ibcon#read 3, iclass 4, count 0 2006.182.08:24:58.21#ibcon#about to read 4, iclass 4, count 0 2006.182.08:24:58.21#ibcon#read 4, iclass 4, count 0 2006.182.08:24:58.21#ibcon#about to read 5, iclass 4, count 0 2006.182.08:24:58.21#ibcon#read 5, iclass 4, count 0 2006.182.08:24:58.21#ibcon#about to read 6, iclass 4, count 0 2006.182.08:24:58.21#ibcon#read 6, iclass 4, count 0 2006.182.08:24:58.21#ibcon#end of sib2, iclass 4, count 0 2006.182.08:24:58.21#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:24:58.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:24:58.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:24:58.21#ibcon#*before write, iclass 4, count 0 2006.182.08:24:58.21#ibcon#enter sib2, iclass 4, count 0 2006.182.08:24:58.21#ibcon#flushed, iclass 4, count 0 2006.182.08:24:58.21#ibcon#about to write, iclass 4, count 0 2006.182.08:24:58.21#ibcon#wrote, iclass 4, count 0 2006.182.08:24:58.21#ibcon#about to read 3, iclass 4, count 0 2006.182.08:24:58.26#ibcon#read 3, iclass 4, count 0 2006.182.08:24:58.26#ibcon#about to read 4, iclass 4, count 0 2006.182.08:24:58.26#ibcon#read 4, iclass 4, count 0 2006.182.08:24:58.26#ibcon#about to read 5, iclass 4, count 0 2006.182.08:24:58.26#ibcon#read 5, iclass 4, count 0 2006.182.08:24:58.26#ibcon#about to read 6, iclass 4, count 0 2006.182.08:24:58.26#ibcon#read 6, iclass 4, count 0 2006.182.08:24:58.26#ibcon#end of sib2, iclass 4, count 0 2006.182.08:24:58.26#ibcon#*after write, iclass 4, count 0 2006.182.08:24:58.26#ibcon#*before return 0, iclass 4, count 0 2006.182.08:24:58.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:24:58.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:24:58.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:24:58.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:24:58.26$vc4f8/va=2,7 2006.182.08:24:58.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.08:24:58.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.08:24:58.26#ibcon#ireg 11 cls_cnt 2 2006.182.08:24:58.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:24:58.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:24:58.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:24:58.31#ibcon#enter wrdev, iclass 6, count 2 2006.182.08:24:58.31#ibcon#first serial, iclass 6, count 2 2006.182.08:24:58.31#ibcon#enter sib2, iclass 6, count 2 2006.182.08:24:58.31#ibcon#flushed, iclass 6, count 2 2006.182.08:24:58.31#ibcon#about to write, iclass 6, count 2 2006.182.08:24:58.31#ibcon#wrote, iclass 6, count 2 2006.182.08:24:58.31#ibcon#about to read 3, iclass 6, count 2 2006.182.08:24:58.33#ibcon#read 3, iclass 6, count 2 2006.182.08:24:58.33#ibcon#about to read 4, iclass 6, count 2 2006.182.08:24:58.33#ibcon#read 4, iclass 6, count 2 2006.182.08:24:58.33#ibcon#about to read 5, iclass 6, count 2 2006.182.08:24:58.33#ibcon#read 5, iclass 6, count 2 2006.182.08:24:58.33#ibcon#about to read 6, iclass 6, count 2 2006.182.08:24:58.33#ibcon#read 6, iclass 6, count 2 2006.182.08:24:58.33#ibcon#end of sib2, iclass 6, count 2 2006.182.08:24:58.33#ibcon#*mode == 0, iclass 6, count 2 2006.182.08:24:58.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.08:24:58.33#ibcon#[25=AT02-07\r\n] 2006.182.08:24:58.33#ibcon#*before write, iclass 6, count 2 2006.182.08:24:58.33#ibcon#enter sib2, iclass 6, count 2 2006.182.08:24:58.33#ibcon#flushed, iclass 6, count 2 2006.182.08:24:58.33#ibcon#about to write, iclass 6, count 2 2006.182.08:24:58.33#ibcon#wrote, iclass 6, count 2 2006.182.08:24:58.33#ibcon#about to read 3, iclass 6, count 2 2006.182.08:24:58.36#ibcon#read 3, iclass 6, count 2 2006.182.08:24:58.36#ibcon#about to read 4, iclass 6, count 2 2006.182.08:24:58.36#ibcon#read 4, iclass 6, count 2 2006.182.08:24:58.36#ibcon#about to read 5, iclass 6, count 2 2006.182.08:24:58.36#ibcon#read 5, iclass 6, count 2 2006.182.08:24:58.36#ibcon#about to read 6, iclass 6, count 2 2006.182.08:24:58.36#ibcon#read 6, iclass 6, count 2 2006.182.08:24:58.36#ibcon#end of sib2, iclass 6, count 2 2006.182.08:24:58.36#ibcon#*after write, iclass 6, count 2 2006.182.08:24:58.36#ibcon#*before return 0, iclass 6, count 2 2006.182.08:24:58.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:24:58.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:24:58.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.08:24:58.36#ibcon#ireg 7 cls_cnt 0 2006.182.08:24:58.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:24:58.39#abcon#<5=/08 0.8 2.6 27.67 811002.9\r\n> 2006.182.08:24:58.41#abcon#{5=INTERFACE CLEAR} 2006.182.08:24:58.47#abcon#[5=S1D000X0/0*\r\n] 2006.182.08:24:58.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:24:58.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:24:58.48#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:24:58.48#ibcon#first serial, iclass 6, count 0 2006.182.08:24:58.48#ibcon#enter sib2, iclass 6, count 0 2006.182.08:24:58.48#ibcon#flushed, iclass 6, count 0 2006.182.08:24:58.48#ibcon#about to write, iclass 6, count 0 2006.182.08:24:58.48#ibcon#wrote, iclass 6, count 0 2006.182.08:24:58.48#ibcon#about to read 3, iclass 6, count 0 2006.182.08:24:58.51#ibcon#read 3, iclass 6, count 0 2006.182.08:24:58.51#ibcon#about to read 4, iclass 6, count 0 2006.182.08:24:58.51#ibcon#read 4, iclass 6, count 0 2006.182.08:24:58.51#ibcon#about to read 5, iclass 6, count 0 2006.182.08:24:58.51#ibcon#read 5, iclass 6, count 0 2006.182.08:24:58.51#ibcon#about to read 6, iclass 6, count 0 2006.182.08:24:58.51#ibcon#read 6, iclass 6, count 0 2006.182.08:24:58.51#ibcon#end of sib2, iclass 6, count 0 2006.182.08:24:58.51#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:24:58.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:24:58.51#ibcon#[25=USB\r\n] 2006.182.08:24:58.51#ibcon#*before write, iclass 6, count 0 2006.182.08:24:58.51#ibcon#enter sib2, iclass 6, count 0 2006.182.08:24:58.51#ibcon#flushed, iclass 6, count 0 2006.182.08:24:58.51#ibcon#about to write, iclass 6, count 0 2006.182.08:24:58.51#ibcon#wrote, iclass 6, count 0 2006.182.08:24:58.51#ibcon#about to read 3, iclass 6, count 0 2006.182.08:24:58.54#ibcon#read 3, iclass 6, count 0 2006.182.08:24:58.54#ibcon#about to read 4, iclass 6, count 0 2006.182.08:24:58.54#ibcon#read 4, iclass 6, count 0 2006.182.08:24:58.54#ibcon#about to read 5, iclass 6, count 0 2006.182.08:24:58.54#ibcon#read 5, iclass 6, count 0 2006.182.08:24:58.54#ibcon#about to read 6, iclass 6, count 0 2006.182.08:24:58.54#ibcon#read 6, iclass 6, count 0 2006.182.08:24:58.54#ibcon#end of sib2, iclass 6, count 0 2006.182.08:24:58.54#ibcon#*after write, iclass 6, count 0 2006.182.08:24:58.54#ibcon#*before return 0, iclass 6, count 0 2006.182.08:24:58.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:24:58.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:24:58.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:24:58.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:24:58.54$vc4f8/valo=3,672.99 2006.182.08:24:58.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.08:24:58.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.08:24:58.54#ibcon#ireg 17 cls_cnt 0 2006.182.08:24:58.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:24:58.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:24:58.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:24:58.54#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:24:58.54#ibcon#first serial, iclass 14, count 0 2006.182.08:24:58.54#ibcon#enter sib2, iclass 14, count 0 2006.182.08:24:58.54#ibcon#flushed, iclass 14, count 0 2006.182.08:24:58.54#ibcon#about to write, iclass 14, count 0 2006.182.08:24:58.54#ibcon#wrote, iclass 14, count 0 2006.182.08:24:58.54#ibcon#about to read 3, iclass 14, count 0 2006.182.08:24:58.56#ibcon#read 3, iclass 14, count 0 2006.182.08:24:58.56#ibcon#about to read 4, iclass 14, count 0 2006.182.08:24:58.56#ibcon#read 4, iclass 14, count 0 2006.182.08:24:58.56#ibcon#about to read 5, iclass 14, count 0 2006.182.08:24:58.56#ibcon#read 5, iclass 14, count 0 2006.182.08:24:58.56#ibcon#about to read 6, iclass 14, count 0 2006.182.08:24:58.56#ibcon#read 6, iclass 14, count 0 2006.182.08:24:58.56#ibcon#end of sib2, iclass 14, count 0 2006.182.08:24:58.56#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:24:58.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:24:58.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:24:58.56#ibcon#*before write, iclass 14, count 0 2006.182.08:24:58.56#ibcon#enter sib2, iclass 14, count 0 2006.182.08:24:58.56#ibcon#flushed, iclass 14, count 0 2006.182.08:24:58.56#ibcon#about to write, iclass 14, count 0 2006.182.08:24:58.56#ibcon#wrote, iclass 14, count 0 2006.182.08:24:58.56#ibcon#about to read 3, iclass 14, count 0 2006.182.08:24:58.60#ibcon#read 3, iclass 14, count 0 2006.182.08:24:58.60#ibcon#about to read 4, iclass 14, count 0 2006.182.08:24:58.60#ibcon#read 4, iclass 14, count 0 2006.182.08:24:58.60#ibcon#about to read 5, iclass 14, count 0 2006.182.08:24:58.60#ibcon#read 5, iclass 14, count 0 2006.182.08:24:58.60#ibcon#about to read 6, iclass 14, count 0 2006.182.08:24:58.60#ibcon#read 6, iclass 14, count 0 2006.182.08:24:58.60#ibcon#end of sib2, iclass 14, count 0 2006.182.08:24:58.60#ibcon#*after write, iclass 14, count 0 2006.182.08:24:58.60#ibcon#*before return 0, iclass 14, count 0 2006.182.08:24:58.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:24:58.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:24:58.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:24:58.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:24:58.60$vc4f8/va=3,6 2006.182.08:24:58.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.08:24:58.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.08:24:58.60#ibcon#ireg 11 cls_cnt 2 2006.182.08:24:58.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:24:58.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:24:58.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:24:58.66#ibcon#enter wrdev, iclass 16, count 2 2006.182.08:24:58.66#ibcon#first serial, iclass 16, count 2 2006.182.08:24:58.66#ibcon#enter sib2, iclass 16, count 2 2006.182.08:24:58.66#ibcon#flushed, iclass 16, count 2 2006.182.08:24:58.66#ibcon#about to write, iclass 16, count 2 2006.182.08:24:58.66#ibcon#wrote, iclass 16, count 2 2006.182.08:24:58.66#ibcon#about to read 3, iclass 16, count 2 2006.182.08:24:58.68#ibcon#read 3, iclass 16, count 2 2006.182.08:24:58.68#ibcon#about to read 4, iclass 16, count 2 2006.182.08:24:58.68#ibcon#read 4, iclass 16, count 2 2006.182.08:24:58.68#ibcon#about to read 5, iclass 16, count 2 2006.182.08:24:58.68#ibcon#read 5, iclass 16, count 2 2006.182.08:24:58.68#ibcon#about to read 6, iclass 16, count 2 2006.182.08:24:58.68#ibcon#read 6, iclass 16, count 2 2006.182.08:24:58.68#ibcon#end of sib2, iclass 16, count 2 2006.182.08:24:58.68#ibcon#*mode == 0, iclass 16, count 2 2006.182.08:24:58.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.08:24:58.68#ibcon#[25=AT03-06\r\n] 2006.182.08:24:58.68#ibcon#*before write, iclass 16, count 2 2006.182.08:24:58.68#ibcon#enter sib2, iclass 16, count 2 2006.182.08:24:58.68#ibcon#flushed, iclass 16, count 2 2006.182.08:24:58.68#ibcon#about to write, iclass 16, count 2 2006.182.08:24:58.68#ibcon#wrote, iclass 16, count 2 2006.182.08:24:58.68#ibcon#about to read 3, iclass 16, count 2 2006.182.08:24:58.71#ibcon#read 3, iclass 16, count 2 2006.182.08:24:58.71#ibcon#about to read 4, iclass 16, count 2 2006.182.08:24:58.71#ibcon#read 4, iclass 16, count 2 2006.182.08:24:58.71#ibcon#about to read 5, iclass 16, count 2 2006.182.08:24:58.71#ibcon#read 5, iclass 16, count 2 2006.182.08:24:58.71#ibcon#about to read 6, iclass 16, count 2 2006.182.08:24:58.71#ibcon#read 6, iclass 16, count 2 2006.182.08:24:58.71#ibcon#end of sib2, iclass 16, count 2 2006.182.08:24:58.71#ibcon#*after write, iclass 16, count 2 2006.182.08:24:58.71#ibcon#*before return 0, iclass 16, count 2 2006.182.08:24:58.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:24:58.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:24:58.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.08:24:58.71#ibcon#ireg 7 cls_cnt 0 2006.182.08:24:58.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:24:58.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:24:58.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:24:58.83#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:24:58.83#ibcon#first serial, iclass 16, count 0 2006.182.08:24:58.83#ibcon#enter sib2, iclass 16, count 0 2006.182.08:24:58.83#ibcon#flushed, iclass 16, count 0 2006.182.08:24:58.83#ibcon#about to write, iclass 16, count 0 2006.182.08:24:58.83#ibcon#wrote, iclass 16, count 0 2006.182.08:24:58.83#ibcon#about to read 3, iclass 16, count 0 2006.182.08:24:58.85#ibcon#read 3, iclass 16, count 0 2006.182.08:24:58.85#ibcon#about to read 4, iclass 16, count 0 2006.182.08:24:58.85#ibcon#read 4, iclass 16, count 0 2006.182.08:24:58.85#ibcon#about to read 5, iclass 16, count 0 2006.182.08:24:58.85#ibcon#read 5, iclass 16, count 0 2006.182.08:24:58.85#ibcon#about to read 6, iclass 16, count 0 2006.182.08:24:58.85#ibcon#read 6, iclass 16, count 0 2006.182.08:24:58.85#ibcon#end of sib2, iclass 16, count 0 2006.182.08:24:58.85#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:24:58.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:24:58.85#ibcon#[25=USB\r\n] 2006.182.08:24:58.85#ibcon#*before write, iclass 16, count 0 2006.182.08:24:58.85#ibcon#enter sib2, iclass 16, count 0 2006.182.08:24:58.85#ibcon#flushed, iclass 16, count 0 2006.182.08:24:58.85#ibcon#about to write, iclass 16, count 0 2006.182.08:24:58.85#ibcon#wrote, iclass 16, count 0 2006.182.08:24:58.85#ibcon#about to read 3, iclass 16, count 0 2006.182.08:24:58.88#ibcon#read 3, iclass 16, count 0 2006.182.08:24:58.88#ibcon#about to read 4, iclass 16, count 0 2006.182.08:24:58.88#ibcon#read 4, iclass 16, count 0 2006.182.08:24:58.88#ibcon#about to read 5, iclass 16, count 0 2006.182.08:24:58.88#ibcon#read 5, iclass 16, count 0 2006.182.08:24:58.88#ibcon#about to read 6, iclass 16, count 0 2006.182.08:24:58.88#ibcon#read 6, iclass 16, count 0 2006.182.08:24:58.88#ibcon#end of sib2, iclass 16, count 0 2006.182.08:24:58.88#ibcon#*after write, iclass 16, count 0 2006.182.08:24:58.88#ibcon#*before return 0, iclass 16, count 0 2006.182.08:24:58.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:24:58.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:24:58.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:24:58.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:24:58.88$vc4f8/valo=4,832.99 2006.182.08:24:58.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.08:24:58.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.08:24:58.88#ibcon#ireg 17 cls_cnt 0 2006.182.08:24:58.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:24:58.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:24:58.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:24:58.88#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:24:58.88#ibcon#first serial, iclass 18, count 0 2006.182.08:24:58.88#ibcon#enter sib2, iclass 18, count 0 2006.182.08:24:58.88#ibcon#flushed, iclass 18, count 0 2006.182.08:24:58.88#ibcon#about to write, iclass 18, count 0 2006.182.08:24:58.88#ibcon#wrote, iclass 18, count 0 2006.182.08:24:58.88#ibcon#about to read 3, iclass 18, count 0 2006.182.08:24:58.90#ibcon#read 3, iclass 18, count 0 2006.182.08:24:58.90#ibcon#about to read 4, iclass 18, count 0 2006.182.08:24:58.90#ibcon#read 4, iclass 18, count 0 2006.182.08:24:58.90#ibcon#about to read 5, iclass 18, count 0 2006.182.08:24:58.90#ibcon#read 5, iclass 18, count 0 2006.182.08:24:58.90#ibcon#about to read 6, iclass 18, count 0 2006.182.08:24:58.90#ibcon#read 6, iclass 18, count 0 2006.182.08:24:58.90#ibcon#end of sib2, iclass 18, count 0 2006.182.08:24:58.90#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:24:58.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:24:58.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:24:58.90#ibcon#*before write, iclass 18, count 0 2006.182.08:24:58.90#ibcon#enter sib2, iclass 18, count 0 2006.182.08:24:58.90#ibcon#flushed, iclass 18, count 0 2006.182.08:24:58.90#ibcon#about to write, iclass 18, count 0 2006.182.08:24:58.90#ibcon#wrote, iclass 18, count 0 2006.182.08:24:58.90#ibcon#about to read 3, iclass 18, count 0 2006.182.08:24:58.94#ibcon#read 3, iclass 18, count 0 2006.182.08:24:58.94#ibcon#about to read 4, iclass 18, count 0 2006.182.08:24:58.94#ibcon#read 4, iclass 18, count 0 2006.182.08:24:58.94#ibcon#about to read 5, iclass 18, count 0 2006.182.08:24:58.94#ibcon#read 5, iclass 18, count 0 2006.182.08:24:58.94#ibcon#about to read 6, iclass 18, count 0 2006.182.08:24:58.94#ibcon#read 6, iclass 18, count 0 2006.182.08:24:58.94#ibcon#end of sib2, iclass 18, count 0 2006.182.08:24:58.94#ibcon#*after write, iclass 18, count 0 2006.182.08:24:58.94#ibcon#*before return 0, iclass 18, count 0 2006.182.08:24:58.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:24:58.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:24:58.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:24:58.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:24:58.94$vc4f8/va=4,7 2006.182.08:24:58.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.08:24:58.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.08:24:58.94#ibcon#ireg 11 cls_cnt 2 2006.182.08:24:58.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:24:59.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:24:59.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:24:59.00#ibcon#enter wrdev, iclass 20, count 2 2006.182.08:24:59.00#ibcon#first serial, iclass 20, count 2 2006.182.08:24:59.00#ibcon#enter sib2, iclass 20, count 2 2006.182.08:24:59.00#ibcon#flushed, iclass 20, count 2 2006.182.08:24:59.00#ibcon#about to write, iclass 20, count 2 2006.182.08:24:59.00#ibcon#wrote, iclass 20, count 2 2006.182.08:24:59.00#ibcon#about to read 3, iclass 20, count 2 2006.182.08:24:59.02#ibcon#read 3, iclass 20, count 2 2006.182.08:24:59.02#ibcon#about to read 4, iclass 20, count 2 2006.182.08:24:59.02#ibcon#read 4, iclass 20, count 2 2006.182.08:24:59.02#ibcon#about to read 5, iclass 20, count 2 2006.182.08:24:59.02#ibcon#read 5, iclass 20, count 2 2006.182.08:24:59.02#ibcon#about to read 6, iclass 20, count 2 2006.182.08:24:59.02#ibcon#read 6, iclass 20, count 2 2006.182.08:24:59.02#ibcon#end of sib2, iclass 20, count 2 2006.182.08:24:59.02#ibcon#*mode == 0, iclass 20, count 2 2006.182.08:24:59.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.08:24:59.02#ibcon#[25=AT04-07\r\n] 2006.182.08:24:59.02#ibcon#*before write, iclass 20, count 2 2006.182.08:24:59.02#ibcon#enter sib2, iclass 20, count 2 2006.182.08:24:59.02#ibcon#flushed, iclass 20, count 2 2006.182.08:24:59.02#ibcon#about to write, iclass 20, count 2 2006.182.08:24:59.02#ibcon#wrote, iclass 20, count 2 2006.182.08:24:59.02#ibcon#about to read 3, iclass 20, count 2 2006.182.08:24:59.05#ibcon#read 3, iclass 20, count 2 2006.182.08:24:59.05#ibcon#about to read 4, iclass 20, count 2 2006.182.08:24:59.05#ibcon#read 4, iclass 20, count 2 2006.182.08:24:59.05#ibcon#about to read 5, iclass 20, count 2 2006.182.08:24:59.05#ibcon#read 5, iclass 20, count 2 2006.182.08:24:59.05#ibcon#about to read 6, iclass 20, count 2 2006.182.08:24:59.05#ibcon#read 6, iclass 20, count 2 2006.182.08:24:59.05#ibcon#end of sib2, iclass 20, count 2 2006.182.08:24:59.05#ibcon#*after write, iclass 20, count 2 2006.182.08:24:59.05#ibcon#*before return 0, iclass 20, count 2 2006.182.08:24:59.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:24:59.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:24:59.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.08:24:59.05#ibcon#ireg 7 cls_cnt 0 2006.182.08:24:59.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:24:59.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:24:59.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:24:59.17#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:24:59.17#ibcon#first serial, iclass 20, count 0 2006.182.08:24:59.17#ibcon#enter sib2, iclass 20, count 0 2006.182.08:24:59.17#ibcon#flushed, iclass 20, count 0 2006.182.08:24:59.17#ibcon#about to write, iclass 20, count 0 2006.182.08:24:59.17#ibcon#wrote, iclass 20, count 0 2006.182.08:24:59.17#ibcon#about to read 3, iclass 20, count 0 2006.182.08:24:59.19#ibcon#read 3, iclass 20, count 0 2006.182.08:24:59.19#ibcon#about to read 4, iclass 20, count 0 2006.182.08:24:59.19#ibcon#read 4, iclass 20, count 0 2006.182.08:24:59.19#ibcon#about to read 5, iclass 20, count 0 2006.182.08:24:59.19#ibcon#read 5, iclass 20, count 0 2006.182.08:24:59.19#ibcon#about to read 6, iclass 20, count 0 2006.182.08:24:59.19#ibcon#read 6, iclass 20, count 0 2006.182.08:24:59.19#ibcon#end of sib2, iclass 20, count 0 2006.182.08:24:59.19#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:24:59.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:24:59.19#ibcon#[25=USB\r\n] 2006.182.08:24:59.19#ibcon#*before write, iclass 20, count 0 2006.182.08:24:59.19#ibcon#enter sib2, iclass 20, count 0 2006.182.08:24:59.19#ibcon#flushed, iclass 20, count 0 2006.182.08:24:59.19#ibcon#about to write, iclass 20, count 0 2006.182.08:24:59.19#ibcon#wrote, iclass 20, count 0 2006.182.08:24:59.19#ibcon#about to read 3, iclass 20, count 0 2006.182.08:24:59.22#ibcon#read 3, iclass 20, count 0 2006.182.08:24:59.22#ibcon#about to read 4, iclass 20, count 0 2006.182.08:24:59.22#ibcon#read 4, iclass 20, count 0 2006.182.08:24:59.22#ibcon#about to read 5, iclass 20, count 0 2006.182.08:24:59.22#ibcon#read 5, iclass 20, count 0 2006.182.08:24:59.22#ibcon#about to read 6, iclass 20, count 0 2006.182.08:24:59.22#ibcon#read 6, iclass 20, count 0 2006.182.08:24:59.22#ibcon#end of sib2, iclass 20, count 0 2006.182.08:24:59.22#ibcon#*after write, iclass 20, count 0 2006.182.08:24:59.22#ibcon#*before return 0, iclass 20, count 0 2006.182.08:24:59.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:24:59.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:24:59.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:24:59.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:24:59.22$vc4f8/valo=5,652.99 2006.182.08:24:59.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.08:24:59.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.08:24:59.22#ibcon#ireg 17 cls_cnt 0 2006.182.08:24:59.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:24:59.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:24:59.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:24:59.22#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:24:59.22#ibcon#first serial, iclass 22, count 0 2006.182.08:24:59.22#ibcon#enter sib2, iclass 22, count 0 2006.182.08:24:59.22#ibcon#flushed, iclass 22, count 0 2006.182.08:24:59.22#ibcon#about to write, iclass 22, count 0 2006.182.08:24:59.22#ibcon#wrote, iclass 22, count 0 2006.182.08:24:59.22#ibcon#about to read 3, iclass 22, count 0 2006.182.08:24:59.24#ibcon#read 3, iclass 22, count 0 2006.182.08:24:59.24#ibcon#about to read 4, iclass 22, count 0 2006.182.08:24:59.24#ibcon#read 4, iclass 22, count 0 2006.182.08:24:59.24#ibcon#about to read 5, iclass 22, count 0 2006.182.08:24:59.24#ibcon#read 5, iclass 22, count 0 2006.182.08:24:59.24#ibcon#about to read 6, iclass 22, count 0 2006.182.08:24:59.24#ibcon#read 6, iclass 22, count 0 2006.182.08:24:59.24#ibcon#end of sib2, iclass 22, count 0 2006.182.08:24:59.24#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:24:59.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:24:59.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:24:59.24#ibcon#*before write, iclass 22, count 0 2006.182.08:24:59.24#ibcon#enter sib2, iclass 22, count 0 2006.182.08:24:59.24#ibcon#flushed, iclass 22, count 0 2006.182.08:24:59.24#ibcon#about to write, iclass 22, count 0 2006.182.08:24:59.24#ibcon#wrote, iclass 22, count 0 2006.182.08:24:59.24#ibcon#about to read 3, iclass 22, count 0 2006.182.08:24:59.28#ibcon#read 3, iclass 22, count 0 2006.182.08:24:59.28#ibcon#about to read 4, iclass 22, count 0 2006.182.08:24:59.28#ibcon#read 4, iclass 22, count 0 2006.182.08:24:59.28#ibcon#about to read 5, iclass 22, count 0 2006.182.08:24:59.28#ibcon#read 5, iclass 22, count 0 2006.182.08:24:59.28#ibcon#about to read 6, iclass 22, count 0 2006.182.08:24:59.28#ibcon#read 6, iclass 22, count 0 2006.182.08:24:59.28#ibcon#end of sib2, iclass 22, count 0 2006.182.08:24:59.28#ibcon#*after write, iclass 22, count 0 2006.182.08:24:59.28#ibcon#*before return 0, iclass 22, count 0 2006.182.08:24:59.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:24:59.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:24:59.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:24:59.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:24:59.28$vc4f8/va=5,7 2006.182.08:24:59.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.08:24:59.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.08:24:59.28#ibcon#ireg 11 cls_cnt 2 2006.182.08:24:59.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:24:59.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:24:59.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:24:59.34#ibcon#enter wrdev, iclass 24, count 2 2006.182.08:24:59.34#ibcon#first serial, iclass 24, count 2 2006.182.08:24:59.34#ibcon#enter sib2, iclass 24, count 2 2006.182.08:24:59.34#ibcon#flushed, iclass 24, count 2 2006.182.08:24:59.34#ibcon#about to write, iclass 24, count 2 2006.182.08:24:59.34#ibcon#wrote, iclass 24, count 2 2006.182.08:24:59.34#ibcon#about to read 3, iclass 24, count 2 2006.182.08:24:59.36#ibcon#read 3, iclass 24, count 2 2006.182.08:24:59.36#ibcon#about to read 4, iclass 24, count 2 2006.182.08:24:59.36#ibcon#read 4, iclass 24, count 2 2006.182.08:24:59.36#ibcon#about to read 5, iclass 24, count 2 2006.182.08:24:59.36#ibcon#read 5, iclass 24, count 2 2006.182.08:24:59.36#ibcon#about to read 6, iclass 24, count 2 2006.182.08:24:59.36#ibcon#read 6, iclass 24, count 2 2006.182.08:24:59.36#ibcon#end of sib2, iclass 24, count 2 2006.182.08:24:59.36#ibcon#*mode == 0, iclass 24, count 2 2006.182.08:24:59.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.08:24:59.36#ibcon#[25=AT05-07\r\n] 2006.182.08:24:59.36#ibcon#*before write, iclass 24, count 2 2006.182.08:24:59.36#ibcon#enter sib2, iclass 24, count 2 2006.182.08:24:59.36#ibcon#flushed, iclass 24, count 2 2006.182.08:24:59.36#ibcon#about to write, iclass 24, count 2 2006.182.08:24:59.36#ibcon#wrote, iclass 24, count 2 2006.182.08:24:59.36#ibcon#about to read 3, iclass 24, count 2 2006.182.08:24:59.39#ibcon#read 3, iclass 24, count 2 2006.182.08:24:59.39#ibcon#about to read 4, iclass 24, count 2 2006.182.08:24:59.39#ibcon#read 4, iclass 24, count 2 2006.182.08:24:59.39#ibcon#about to read 5, iclass 24, count 2 2006.182.08:24:59.39#ibcon#read 5, iclass 24, count 2 2006.182.08:24:59.39#ibcon#about to read 6, iclass 24, count 2 2006.182.08:24:59.39#ibcon#read 6, iclass 24, count 2 2006.182.08:24:59.39#ibcon#end of sib2, iclass 24, count 2 2006.182.08:24:59.39#ibcon#*after write, iclass 24, count 2 2006.182.08:24:59.39#ibcon#*before return 0, iclass 24, count 2 2006.182.08:24:59.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:24:59.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:24:59.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.08:24:59.39#ibcon#ireg 7 cls_cnt 0 2006.182.08:24:59.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:24:59.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:24:59.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:24:59.51#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:24:59.51#ibcon#first serial, iclass 24, count 0 2006.182.08:24:59.51#ibcon#enter sib2, iclass 24, count 0 2006.182.08:24:59.51#ibcon#flushed, iclass 24, count 0 2006.182.08:24:59.51#ibcon#about to write, iclass 24, count 0 2006.182.08:24:59.51#ibcon#wrote, iclass 24, count 0 2006.182.08:24:59.51#ibcon#about to read 3, iclass 24, count 0 2006.182.08:24:59.53#ibcon#read 3, iclass 24, count 0 2006.182.08:24:59.53#ibcon#about to read 4, iclass 24, count 0 2006.182.08:24:59.53#ibcon#read 4, iclass 24, count 0 2006.182.08:24:59.53#ibcon#about to read 5, iclass 24, count 0 2006.182.08:24:59.53#ibcon#read 5, iclass 24, count 0 2006.182.08:24:59.53#ibcon#about to read 6, iclass 24, count 0 2006.182.08:24:59.53#ibcon#read 6, iclass 24, count 0 2006.182.08:24:59.53#ibcon#end of sib2, iclass 24, count 0 2006.182.08:24:59.53#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:24:59.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:24:59.53#ibcon#[25=USB\r\n] 2006.182.08:24:59.53#ibcon#*before write, iclass 24, count 0 2006.182.08:24:59.53#ibcon#enter sib2, iclass 24, count 0 2006.182.08:24:59.53#ibcon#flushed, iclass 24, count 0 2006.182.08:24:59.53#ibcon#about to write, iclass 24, count 0 2006.182.08:24:59.53#ibcon#wrote, iclass 24, count 0 2006.182.08:24:59.53#ibcon#about to read 3, iclass 24, count 0 2006.182.08:24:59.56#ibcon#read 3, iclass 24, count 0 2006.182.08:24:59.56#ibcon#about to read 4, iclass 24, count 0 2006.182.08:24:59.56#ibcon#read 4, iclass 24, count 0 2006.182.08:24:59.56#ibcon#about to read 5, iclass 24, count 0 2006.182.08:24:59.56#ibcon#read 5, iclass 24, count 0 2006.182.08:24:59.56#ibcon#about to read 6, iclass 24, count 0 2006.182.08:24:59.56#ibcon#read 6, iclass 24, count 0 2006.182.08:24:59.56#ibcon#end of sib2, iclass 24, count 0 2006.182.08:24:59.56#ibcon#*after write, iclass 24, count 0 2006.182.08:24:59.56#ibcon#*before return 0, iclass 24, count 0 2006.182.08:24:59.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:24:59.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:24:59.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:24:59.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:24:59.56$vc4f8/valo=6,772.99 2006.182.08:24:59.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.08:24:59.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.08:24:59.56#ibcon#ireg 17 cls_cnt 0 2006.182.08:24:59.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:24:59.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:24:59.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:24:59.56#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:24:59.56#ibcon#first serial, iclass 26, count 0 2006.182.08:24:59.56#ibcon#enter sib2, iclass 26, count 0 2006.182.08:24:59.56#ibcon#flushed, iclass 26, count 0 2006.182.08:24:59.56#ibcon#about to write, iclass 26, count 0 2006.182.08:24:59.56#ibcon#wrote, iclass 26, count 0 2006.182.08:24:59.56#ibcon#about to read 3, iclass 26, count 0 2006.182.08:24:59.58#ibcon#read 3, iclass 26, count 0 2006.182.08:24:59.58#ibcon#about to read 4, iclass 26, count 0 2006.182.08:24:59.58#ibcon#read 4, iclass 26, count 0 2006.182.08:24:59.58#ibcon#about to read 5, iclass 26, count 0 2006.182.08:24:59.58#ibcon#read 5, iclass 26, count 0 2006.182.08:24:59.58#ibcon#about to read 6, iclass 26, count 0 2006.182.08:24:59.58#ibcon#read 6, iclass 26, count 0 2006.182.08:24:59.58#ibcon#end of sib2, iclass 26, count 0 2006.182.08:24:59.58#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:24:59.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:24:59.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:24:59.58#ibcon#*before write, iclass 26, count 0 2006.182.08:24:59.58#ibcon#enter sib2, iclass 26, count 0 2006.182.08:24:59.58#ibcon#flushed, iclass 26, count 0 2006.182.08:24:59.58#ibcon#about to write, iclass 26, count 0 2006.182.08:24:59.58#ibcon#wrote, iclass 26, count 0 2006.182.08:24:59.58#ibcon#about to read 3, iclass 26, count 0 2006.182.08:24:59.62#ibcon#read 3, iclass 26, count 0 2006.182.08:24:59.62#ibcon#about to read 4, iclass 26, count 0 2006.182.08:24:59.62#ibcon#read 4, iclass 26, count 0 2006.182.08:24:59.62#ibcon#about to read 5, iclass 26, count 0 2006.182.08:24:59.62#ibcon#read 5, iclass 26, count 0 2006.182.08:24:59.62#ibcon#about to read 6, iclass 26, count 0 2006.182.08:24:59.62#ibcon#read 6, iclass 26, count 0 2006.182.08:24:59.62#ibcon#end of sib2, iclass 26, count 0 2006.182.08:24:59.62#ibcon#*after write, iclass 26, count 0 2006.182.08:24:59.62#ibcon#*before return 0, iclass 26, count 0 2006.182.08:24:59.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:24:59.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:24:59.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:24:59.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:24:59.62$vc4f8/va=6,6 2006.182.08:24:59.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.182.08:24:59.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.182.08:24:59.62#ibcon#ireg 11 cls_cnt 2 2006.182.08:24:59.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:24:59.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:24:59.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:24:59.68#ibcon#enter wrdev, iclass 28, count 2 2006.182.08:24:59.68#ibcon#first serial, iclass 28, count 2 2006.182.08:24:59.68#ibcon#enter sib2, iclass 28, count 2 2006.182.08:24:59.68#ibcon#flushed, iclass 28, count 2 2006.182.08:24:59.68#ibcon#about to write, iclass 28, count 2 2006.182.08:24:59.68#ibcon#wrote, iclass 28, count 2 2006.182.08:24:59.68#ibcon#about to read 3, iclass 28, count 2 2006.182.08:24:59.70#ibcon#read 3, iclass 28, count 2 2006.182.08:24:59.70#ibcon#about to read 4, iclass 28, count 2 2006.182.08:24:59.70#ibcon#read 4, iclass 28, count 2 2006.182.08:24:59.70#ibcon#about to read 5, iclass 28, count 2 2006.182.08:24:59.70#ibcon#read 5, iclass 28, count 2 2006.182.08:24:59.70#ibcon#about to read 6, iclass 28, count 2 2006.182.08:24:59.70#ibcon#read 6, iclass 28, count 2 2006.182.08:24:59.70#ibcon#end of sib2, iclass 28, count 2 2006.182.08:24:59.70#ibcon#*mode == 0, iclass 28, count 2 2006.182.08:24:59.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.182.08:24:59.70#ibcon#[25=AT06-06\r\n] 2006.182.08:24:59.70#ibcon#*before write, iclass 28, count 2 2006.182.08:24:59.70#ibcon#enter sib2, iclass 28, count 2 2006.182.08:24:59.70#ibcon#flushed, iclass 28, count 2 2006.182.08:24:59.70#ibcon#about to write, iclass 28, count 2 2006.182.08:24:59.70#ibcon#wrote, iclass 28, count 2 2006.182.08:24:59.70#ibcon#about to read 3, iclass 28, count 2 2006.182.08:24:59.74#ibcon#read 3, iclass 28, count 2 2006.182.08:24:59.74#ibcon#about to read 4, iclass 28, count 2 2006.182.08:24:59.74#ibcon#read 4, iclass 28, count 2 2006.182.08:24:59.74#ibcon#about to read 5, iclass 28, count 2 2006.182.08:24:59.74#ibcon#read 5, iclass 28, count 2 2006.182.08:24:59.74#ibcon#about to read 6, iclass 28, count 2 2006.182.08:24:59.74#ibcon#read 6, iclass 28, count 2 2006.182.08:24:59.74#ibcon#end of sib2, iclass 28, count 2 2006.182.08:24:59.74#ibcon#*after write, iclass 28, count 2 2006.182.08:24:59.74#ibcon#*before return 0, iclass 28, count 2 2006.182.08:24:59.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:24:59.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.182.08:24:59.74#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.182.08:24:59.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:24:59.74#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:24:59.86#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:24:59.86#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:24:59.86#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:24:59.86#ibcon#first serial, iclass 28, count 0 2006.182.08:24:59.86#ibcon#enter sib2, iclass 28, count 0 2006.182.08:24:59.86#ibcon#flushed, iclass 28, count 0 2006.182.08:24:59.86#ibcon#about to write, iclass 28, count 0 2006.182.08:24:59.86#ibcon#wrote, iclass 28, count 0 2006.182.08:24:59.86#ibcon#about to read 3, iclass 28, count 0 2006.182.08:24:59.88#ibcon#read 3, iclass 28, count 0 2006.182.08:24:59.88#ibcon#about to read 4, iclass 28, count 0 2006.182.08:24:59.88#ibcon#read 4, iclass 28, count 0 2006.182.08:24:59.88#ibcon#about to read 5, iclass 28, count 0 2006.182.08:24:59.88#ibcon#read 5, iclass 28, count 0 2006.182.08:24:59.88#ibcon#about to read 6, iclass 28, count 0 2006.182.08:24:59.88#ibcon#read 6, iclass 28, count 0 2006.182.08:24:59.88#ibcon#end of sib2, iclass 28, count 0 2006.182.08:24:59.88#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:24:59.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:24:59.88#ibcon#[25=USB\r\n] 2006.182.08:24:59.88#ibcon#*before write, iclass 28, count 0 2006.182.08:24:59.88#ibcon#enter sib2, iclass 28, count 0 2006.182.08:24:59.88#ibcon#flushed, iclass 28, count 0 2006.182.08:24:59.88#ibcon#about to write, iclass 28, count 0 2006.182.08:24:59.88#ibcon#wrote, iclass 28, count 0 2006.182.08:24:59.88#ibcon#about to read 3, iclass 28, count 0 2006.182.08:24:59.91#ibcon#read 3, iclass 28, count 0 2006.182.08:24:59.91#ibcon#about to read 4, iclass 28, count 0 2006.182.08:24:59.91#ibcon#read 4, iclass 28, count 0 2006.182.08:24:59.91#ibcon#about to read 5, iclass 28, count 0 2006.182.08:24:59.91#ibcon#read 5, iclass 28, count 0 2006.182.08:24:59.91#ibcon#about to read 6, iclass 28, count 0 2006.182.08:24:59.91#ibcon#read 6, iclass 28, count 0 2006.182.08:24:59.91#ibcon#end of sib2, iclass 28, count 0 2006.182.08:24:59.91#ibcon#*after write, iclass 28, count 0 2006.182.08:24:59.91#ibcon#*before return 0, iclass 28, count 0 2006.182.08:24:59.91#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:24:59.91#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.182.08:24:59.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:24:59.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:24:59.91$vc4f8/valo=7,832.99 2006.182.08:24:59.91#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.182.08:24:59.91#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.182.08:24:59.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:24:59.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:24:59.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:24:59.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:24:59.91#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:24:59.91#ibcon#first serial, iclass 30, count 0 2006.182.08:24:59.91#ibcon#enter sib2, iclass 30, count 0 2006.182.08:24:59.91#ibcon#flushed, iclass 30, count 0 2006.182.08:24:59.91#ibcon#about to write, iclass 30, count 0 2006.182.08:24:59.91#ibcon#wrote, iclass 30, count 0 2006.182.08:24:59.91#ibcon#about to read 3, iclass 30, count 0 2006.182.08:24:59.93#ibcon#read 3, iclass 30, count 0 2006.182.08:24:59.93#ibcon#about to read 4, iclass 30, count 0 2006.182.08:24:59.93#ibcon#read 4, iclass 30, count 0 2006.182.08:24:59.93#ibcon#about to read 5, iclass 30, count 0 2006.182.08:24:59.93#ibcon#read 5, iclass 30, count 0 2006.182.08:24:59.93#ibcon#about to read 6, iclass 30, count 0 2006.182.08:24:59.93#ibcon#read 6, iclass 30, count 0 2006.182.08:24:59.93#ibcon#end of sib2, iclass 30, count 0 2006.182.08:24:59.93#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:24:59.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:24:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:24:59.93#ibcon#*before write, iclass 30, count 0 2006.182.08:24:59.93#ibcon#enter sib2, iclass 30, count 0 2006.182.08:24:59.93#ibcon#flushed, iclass 30, count 0 2006.182.08:24:59.93#ibcon#about to write, iclass 30, count 0 2006.182.08:24:59.93#ibcon#wrote, iclass 30, count 0 2006.182.08:24:59.93#ibcon#about to read 3, iclass 30, count 0 2006.182.08:24:59.97#ibcon#read 3, iclass 30, count 0 2006.182.08:24:59.97#ibcon#about to read 4, iclass 30, count 0 2006.182.08:24:59.97#ibcon#read 4, iclass 30, count 0 2006.182.08:24:59.97#ibcon#about to read 5, iclass 30, count 0 2006.182.08:24:59.97#ibcon#read 5, iclass 30, count 0 2006.182.08:24:59.97#ibcon#about to read 6, iclass 30, count 0 2006.182.08:24:59.97#ibcon#read 6, iclass 30, count 0 2006.182.08:24:59.97#ibcon#end of sib2, iclass 30, count 0 2006.182.08:24:59.97#ibcon#*after write, iclass 30, count 0 2006.182.08:24:59.97#ibcon#*before return 0, iclass 30, count 0 2006.182.08:24:59.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:24:59.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.182.08:24:59.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:24:59.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:24:59.97$vc4f8/va=7,6 2006.182.08:24:59.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.182.08:24:59.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.182.08:24:59.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:24:59.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:25:00.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:25:00.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:25:00.03#ibcon#enter wrdev, iclass 32, count 2 2006.182.08:25:00.03#ibcon#first serial, iclass 32, count 2 2006.182.08:25:00.03#ibcon#enter sib2, iclass 32, count 2 2006.182.08:25:00.03#ibcon#flushed, iclass 32, count 2 2006.182.08:25:00.03#ibcon#about to write, iclass 32, count 2 2006.182.08:25:00.03#ibcon#wrote, iclass 32, count 2 2006.182.08:25:00.03#ibcon#about to read 3, iclass 32, count 2 2006.182.08:25:00.05#ibcon#read 3, iclass 32, count 2 2006.182.08:25:00.05#ibcon#about to read 4, iclass 32, count 2 2006.182.08:25:00.05#ibcon#read 4, iclass 32, count 2 2006.182.08:25:00.05#ibcon#about to read 5, iclass 32, count 2 2006.182.08:25:00.05#ibcon#read 5, iclass 32, count 2 2006.182.08:25:00.05#ibcon#about to read 6, iclass 32, count 2 2006.182.08:25:00.05#ibcon#read 6, iclass 32, count 2 2006.182.08:25:00.05#ibcon#end of sib2, iclass 32, count 2 2006.182.08:25:00.05#ibcon#*mode == 0, iclass 32, count 2 2006.182.08:25:00.05#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.182.08:25:00.05#ibcon#[25=AT07-06\r\n] 2006.182.08:25:00.05#ibcon#*before write, iclass 32, count 2 2006.182.08:25:00.05#ibcon#enter sib2, iclass 32, count 2 2006.182.08:25:00.05#ibcon#flushed, iclass 32, count 2 2006.182.08:25:00.05#ibcon#about to write, iclass 32, count 2 2006.182.08:25:00.05#ibcon#wrote, iclass 32, count 2 2006.182.08:25:00.05#ibcon#about to read 3, iclass 32, count 2 2006.182.08:25:00.08#ibcon#read 3, iclass 32, count 2 2006.182.08:25:00.08#ibcon#about to read 4, iclass 32, count 2 2006.182.08:25:00.08#ibcon#read 4, iclass 32, count 2 2006.182.08:25:00.08#ibcon#about to read 5, iclass 32, count 2 2006.182.08:25:00.08#ibcon#read 5, iclass 32, count 2 2006.182.08:25:00.08#ibcon#about to read 6, iclass 32, count 2 2006.182.08:25:00.08#ibcon#read 6, iclass 32, count 2 2006.182.08:25:00.08#ibcon#end of sib2, iclass 32, count 2 2006.182.08:25:00.08#ibcon#*after write, iclass 32, count 2 2006.182.08:25:00.08#ibcon#*before return 0, iclass 32, count 2 2006.182.08:25:00.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:25:00.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.182.08:25:00.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.182.08:25:00.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:25:00.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:25:00.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:25:00.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:25:00.20#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:25:00.20#ibcon#first serial, iclass 32, count 0 2006.182.08:25:00.20#ibcon#enter sib2, iclass 32, count 0 2006.182.08:25:00.20#ibcon#flushed, iclass 32, count 0 2006.182.08:25:00.20#ibcon#about to write, iclass 32, count 0 2006.182.08:25:00.20#ibcon#wrote, iclass 32, count 0 2006.182.08:25:00.20#ibcon#about to read 3, iclass 32, count 0 2006.182.08:25:00.22#ibcon#read 3, iclass 32, count 0 2006.182.08:25:00.22#ibcon#about to read 4, iclass 32, count 0 2006.182.08:25:00.22#ibcon#read 4, iclass 32, count 0 2006.182.08:25:00.22#ibcon#about to read 5, iclass 32, count 0 2006.182.08:25:00.22#ibcon#read 5, iclass 32, count 0 2006.182.08:25:00.22#ibcon#about to read 6, iclass 32, count 0 2006.182.08:25:00.22#ibcon#read 6, iclass 32, count 0 2006.182.08:25:00.22#ibcon#end of sib2, iclass 32, count 0 2006.182.08:25:00.22#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:25:00.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:25:00.22#ibcon#[25=USB\r\n] 2006.182.08:25:00.22#ibcon#*before write, iclass 32, count 0 2006.182.08:25:00.22#ibcon#enter sib2, iclass 32, count 0 2006.182.08:25:00.22#ibcon#flushed, iclass 32, count 0 2006.182.08:25:00.22#ibcon#about to write, iclass 32, count 0 2006.182.08:25:00.22#ibcon#wrote, iclass 32, count 0 2006.182.08:25:00.22#ibcon#about to read 3, iclass 32, count 0 2006.182.08:25:00.25#ibcon#read 3, iclass 32, count 0 2006.182.08:25:00.25#ibcon#about to read 4, iclass 32, count 0 2006.182.08:25:00.25#ibcon#read 4, iclass 32, count 0 2006.182.08:25:00.25#ibcon#about to read 5, iclass 32, count 0 2006.182.08:25:00.25#ibcon#read 5, iclass 32, count 0 2006.182.08:25:00.25#ibcon#about to read 6, iclass 32, count 0 2006.182.08:25:00.25#ibcon#read 6, iclass 32, count 0 2006.182.08:25:00.25#ibcon#end of sib2, iclass 32, count 0 2006.182.08:25:00.25#ibcon#*after write, iclass 32, count 0 2006.182.08:25:00.25#ibcon#*before return 0, iclass 32, count 0 2006.182.08:25:00.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:25:00.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.182.08:25:00.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:25:00.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:25:00.25$vc4f8/valo=8,852.99 2006.182.08:25:00.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.182.08:25:00.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.182.08:25:00.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:25:00.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:25:00.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:25:00.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:25:00.25#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:25:00.25#ibcon#first serial, iclass 34, count 0 2006.182.08:25:00.25#ibcon#enter sib2, iclass 34, count 0 2006.182.08:25:00.25#ibcon#flushed, iclass 34, count 0 2006.182.08:25:00.25#ibcon#about to write, iclass 34, count 0 2006.182.08:25:00.25#ibcon#wrote, iclass 34, count 0 2006.182.08:25:00.25#ibcon#about to read 3, iclass 34, count 0 2006.182.08:25:00.27#ibcon#read 3, iclass 34, count 0 2006.182.08:25:00.27#ibcon#about to read 4, iclass 34, count 0 2006.182.08:25:00.27#ibcon#read 4, iclass 34, count 0 2006.182.08:25:00.27#ibcon#about to read 5, iclass 34, count 0 2006.182.08:25:00.27#ibcon#read 5, iclass 34, count 0 2006.182.08:25:00.27#ibcon#about to read 6, iclass 34, count 0 2006.182.08:25:00.27#ibcon#read 6, iclass 34, count 0 2006.182.08:25:00.27#ibcon#end of sib2, iclass 34, count 0 2006.182.08:25:00.27#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:25:00.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:25:00.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:25:00.27#ibcon#*before write, iclass 34, count 0 2006.182.08:25:00.27#ibcon#enter sib2, iclass 34, count 0 2006.182.08:25:00.27#ibcon#flushed, iclass 34, count 0 2006.182.08:25:00.27#ibcon#about to write, iclass 34, count 0 2006.182.08:25:00.27#ibcon#wrote, iclass 34, count 0 2006.182.08:25:00.27#ibcon#about to read 3, iclass 34, count 0 2006.182.08:25:00.31#ibcon#read 3, iclass 34, count 0 2006.182.08:25:00.31#ibcon#about to read 4, iclass 34, count 0 2006.182.08:25:00.31#ibcon#read 4, iclass 34, count 0 2006.182.08:25:00.31#ibcon#about to read 5, iclass 34, count 0 2006.182.08:25:00.31#ibcon#read 5, iclass 34, count 0 2006.182.08:25:00.31#ibcon#about to read 6, iclass 34, count 0 2006.182.08:25:00.31#ibcon#read 6, iclass 34, count 0 2006.182.08:25:00.31#ibcon#end of sib2, iclass 34, count 0 2006.182.08:25:00.31#ibcon#*after write, iclass 34, count 0 2006.182.08:25:00.31#ibcon#*before return 0, iclass 34, count 0 2006.182.08:25:00.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:25:00.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.182.08:25:00.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:25:00.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:25:00.31$vc4f8/va=8,7 2006.182.08:25:00.31#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.182.08:25:00.31#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.182.08:25:00.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:25:00.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:25:00.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:25:00.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:25:00.37#ibcon#enter wrdev, iclass 36, count 2 2006.182.08:25:00.37#ibcon#first serial, iclass 36, count 2 2006.182.08:25:00.37#ibcon#enter sib2, iclass 36, count 2 2006.182.08:25:00.37#ibcon#flushed, iclass 36, count 2 2006.182.08:25:00.37#ibcon#about to write, iclass 36, count 2 2006.182.08:25:00.37#ibcon#wrote, iclass 36, count 2 2006.182.08:25:00.37#ibcon#about to read 3, iclass 36, count 2 2006.182.08:25:00.39#ibcon#read 3, iclass 36, count 2 2006.182.08:25:00.39#ibcon#about to read 4, iclass 36, count 2 2006.182.08:25:00.39#ibcon#read 4, iclass 36, count 2 2006.182.08:25:00.39#ibcon#about to read 5, iclass 36, count 2 2006.182.08:25:00.39#ibcon#read 5, iclass 36, count 2 2006.182.08:25:00.39#ibcon#about to read 6, iclass 36, count 2 2006.182.08:25:00.39#ibcon#read 6, iclass 36, count 2 2006.182.08:25:00.39#ibcon#end of sib2, iclass 36, count 2 2006.182.08:25:00.39#ibcon#*mode == 0, iclass 36, count 2 2006.182.08:25:00.39#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.182.08:25:00.39#ibcon#[25=AT08-07\r\n] 2006.182.08:25:00.39#ibcon#*before write, iclass 36, count 2 2006.182.08:25:00.39#ibcon#enter sib2, iclass 36, count 2 2006.182.08:25:00.39#ibcon#flushed, iclass 36, count 2 2006.182.08:25:00.39#ibcon#about to write, iclass 36, count 2 2006.182.08:25:00.39#ibcon#wrote, iclass 36, count 2 2006.182.08:25:00.39#ibcon#about to read 3, iclass 36, count 2 2006.182.08:25:00.42#ibcon#read 3, iclass 36, count 2 2006.182.08:25:00.42#ibcon#about to read 4, iclass 36, count 2 2006.182.08:25:00.42#ibcon#read 4, iclass 36, count 2 2006.182.08:25:00.42#ibcon#about to read 5, iclass 36, count 2 2006.182.08:25:00.42#ibcon#read 5, iclass 36, count 2 2006.182.08:25:00.42#ibcon#about to read 6, iclass 36, count 2 2006.182.08:25:00.42#ibcon#read 6, iclass 36, count 2 2006.182.08:25:00.42#ibcon#end of sib2, iclass 36, count 2 2006.182.08:25:00.42#ibcon#*after write, iclass 36, count 2 2006.182.08:25:00.42#ibcon#*before return 0, iclass 36, count 2 2006.182.08:25:00.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:25:00.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.182.08:25:00.42#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.182.08:25:00.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:25:00.42#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:25:00.54#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:25:00.54#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:25:00.54#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:25:00.54#ibcon#first serial, iclass 36, count 0 2006.182.08:25:00.54#ibcon#enter sib2, iclass 36, count 0 2006.182.08:25:00.54#ibcon#flushed, iclass 36, count 0 2006.182.08:25:00.54#ibcon#about to write, iclass 36, count 0 2006.182.08:25:00.54#ibcon#wrote, iclass 36, count 0 2006.182.08:25:00.54#ibcon#about to read 3, iclass 36, count 0 2006.182.08:25:00.56#ibcon#read 3, iclass 36, count 0 2006.182.08:25:00.56#ibcon#about to read 4, iclass 36, count 0 2006.182.08:25:00.56#ibcon#read 4, iclass 36, count 0 2006.182.08:25:00.56#ibcon#about to read 5, iclass 36, count 0 2006.182.08:25:00.56#ibcon#read 5, iclass 36, count 0 2006.182.08:25:00.56#ibcon#about to read 6, iclass 36, count 0 2006.182.08:25:00.56#ibcon#read 6, iclass 36, count 0 2006.182.08:25:00.56#ibcon#end of sib2, iclass 36, count 0 2006.182.08:25:00.56#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:25:00.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:25:00.56#ibcon#[25=USB\r\n] 2006.182.08:25:00.56#ibcon#*before write, iclass 36, count 0 2006.182.08:25:00.56#ibcon#enter sib2, iclass 36, count 0 2006.182.08:25:00.56#ibcon#flushed, iclass 36, count 0 2006.182.08:25:00.56#ibcon#about to write, iclass 36, count 0 2006.182.08:25:00.56#ibcon#wrote, iclass 36, count 0 2006.182.08:25:00.56#ibcon#about to read 3, iclass 36, count 0 2006.182.08:25:00.59#ibcon#read 3, iclass 36, count 0 2006.182.08:25:00.59#ibcon#about to read 4, iclass 36, count 0 2006.182.08:25:00.59#ibcon#read 4, iclass 36, count 0 2006.182.08:25:00.59#ibcon#about to read 5, iclass 36, count 0 2006.182.08:25:00.59#ibcon#read 5, iclass 36, count 0 2006.182.08:25:00.59#ibcon#about to read 6, iclass 36, count 0 2006.182.08:25:00.59#ibcon#read 6, iclass 36, count 0 2006.182.08:25:00.59#ibcon#end of sib2, iclass 36, count 0 2006.182.08:25:00.59#ibcon#*after write, iclass 36, count 0 2006.182.08:25:00.59#ibcon#*before return 0, iclass 36, count 0 2006.182.08:25:00.59#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:25:00.59#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.182.08:25:00.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:25:00.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:25:00.59$vc4f8/vblo=1,632.99 2006.182.08:25:00.59#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.08:25:00.59#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.08:25:00.59#ibcon#ireg 17 cls_cnt 0 2006.182.08:25:00.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:25:00.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:25:00.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:25:00.59#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:25:00.59#ibcon#first serial, iclass 38, count 0 2006.182.08:25:00.59#ibcon#enter sib2, iclass 38, count 0 2006.182.08:25:00.59#ibcon#flushed, iclass 38, count 0 2006.182.08:25:00.59#ibcon#about to write, iclass 38, count 0 2006.182.08:25:00.59#ibcon#wrote, iclass 38, count 0 2006.182.08:25:00.59#ibcon#about to read 3, iclass 38, count 0 2006.182.08:25:00.61#ibcon#read 3, iclass 38, count 0 2006.182.08:25:00.61#ibcon#about to read 4, iclass 38, count 0 2006.182.08:25:00.61#ibcon#read 4, iclass 38, count 0 2006.182.08:25:00.61#ibcon#about to read 5, iclass 38, count 0 2006.182.08:25:00.61#ibcon#read 5, iclass 38, count 0 2006.182.08:25:00.61#ibcon#about to read 6, iclass 38, count 0 2006.182.08:25:00.61#ibcon#read 6, iclass 38, count 0 2006.182.08:25:00.61#ibcon#end of sib2, iclass 38, count 0 2006.182.08:25:00.61#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:25:00.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:25:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:25:00.61#ibcon#*before write, iclass 38, count 0 2006.182.08:25:00.61#ibcon#enter sib2, iclass 38, count 0 2006.182.08:25:00.61#ibcon#flushed, iclass 38, count 0 2006.182.08:25:00.61#ibcon#about to write, iclass 38, count 0 2006.182.08:25:00.61#ibcon#wrote, iclass 38, count 0 2006.182.08:25:00.61#ibcon#about to read 3, iclass 38, count 0 2006.182.08:25:00.65#ibcon#read 3, iclass 38, count 0 2006.182.08:25:00.65#ibcon#about to read 4, iclass 38, count 0 2006.182.08:25:00.65#ibcon#read 4, iclass 38, count 0 2006.182.08:25:00.65#ibcon#about to read 5, iclass 38, count 0 2006.182.08:25:00.65#ibcon#read 5, iclass 38, count 0 2006.182.08:25:00.65#ibcon#about to read 6, iclass 38, count 0 2006.182.08:25:00.65#ibcon#read 6, iclass 38, count 0 2006.182.08:25:00.65#ibcon#end of sib2, iclass 38, count 0 2006.182.08:25:00.65#ibcon#*after write, iclass 38, count 0 2006.182.08:25:00.65#ibcon#*before return 0, iclass 38, count 0 2006.182.08:25:00.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:25:00.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:25:00.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:25:00.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:25:00.65$vc4f8/vb=1,4 2006.182.08:25:00.65#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.182.08:25:00.65#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.182.08:25:00.65#ibcon#ireg 11 cls_cnt 2 2006.182.08:25:00.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:25:00.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:25:00.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:25:00.65#ibcon#enter wrdev, iclass 40, count 2 2006.182.08:25:00.65#ibcon#first serial, iclass 40, count 2 2006.182.08:25:00.65#ibcon#enter sib2, iclass 40, count 2 2006.182.08:25:00.65#ibcon#flushed, iclass 40, count 2 2006.182.08:25:00.65#ibcon#about to write, iclass 40, count 2 2006.182.08:25:00.65#ibcon#wrote, iclass 40, count 2 2006.182.08:25:00.65#ibcon#about to read 3, iclass 40, count 2 2006.182.08:25:00.67#ibcon#read 3, iclass 40, count 2 2006.182.08:25:00.67#ibcon#about to read 4, iclass 40, count 2 2006.182.08:25:00.67#ibcon#read 4, iclass 40, count 2 2006.182.08:25:00.67#ibcon#about to read 5, iclass 40, count 2 2006.182.08:25:00.67#ibcon#read 5, iclass 40, count 2 2006.182.08:25:00.67#ibcon#about to read 6, iclass 40, count 2 2006.182.08:25:00.67#ibcon#read 6, iclass 40, count 2 2006.182.08:25:00.67#ibcon#end of sib2, iclass 40, count 2 2006.182.08:25:00.67#ibcon#*mode == 0, iclass 40, count 2 2006.182.08:25:00.67#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.182.08:25:00.67#ibcon#[27=AT01-04\r\n] 2006.182.08:25:00.67#ibcon#*before write, iclass 40, count 2 2006.182.08:25:00.67#ibcon#enter sib2, iclass 40, count 2 2006.182.08:25:00.67#ibcon#flushed, iclass 40, count 2 2006.182.08:25:00.67#ibcon#about to write, iclass 40, count 2 2006.182.08:25:00.67#ibcon#wrote, iclass 40, count 2 2006.182.08:25:00.67#ibcon#about to read 3, iclass 40, count 2 2006.182.08:25:00.70#ibcon#read 3, iclass 40, count 2 2006.182.08:25:00.70#ibcon#about to read 4, iclass 40, count 2 2006.182.08:25:00.70#ibcon#read 4, iclass 40, count 2 2006.182.08:25:00.70#ibcon#about to read 5, iclass 40, count 2 2006.182.08:25:00.70#ibcon#read 5, iclass 40, count 2 2006.182.08:25:00.70#ibcon#about to read 6, iclass 40, count 2 2006.182.08:25:00.70#ibcon#read 6, iclass 40, count 2 2006.182.08:25:00.70#ibcon#end of sib2, iclass 40, count 2 2006.182.08:25:00.70#ibcon#*after write, iclass 40, count 2 2006.182.08:25:00.70#ibcon#*before return 0, iclass 40, count 2 2006.182.08:25:00.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:25:00.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.182.08:25:00.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.182.08:25:00.70#ibcon#ireg 7 cls_cnt 0 2006.182.08:25:00.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:25:00.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:25:00.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:25:00.82#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:25:00.82#ibcon#first serial, iclass 40, count 0 2006.182.08:25:00.82#ibcon#enter sib2, iclass 40, count 0 2006.182.08:25:00.82#ibcon#flushed, iclass 40, count 0 2006.182.08:25:00.82#ibcon#about to write, iclass 40, count 0 2006.182.08:25:00.82#ibcon#wrote, iclass 40, count 0 2006.182.08:25:00.82#ibcon#about to read 3, iclass 40, count 0 2006.182.08:25:00.84#ibcon#read 3, iclass 40, count 0 2006.182.08:25:00.84#ibcon#about to read 4, iclass 40, count 0 2006.182.08:25:00.84#ibcon#read 4, iclass 40, count 0 2006.182.08:25:00.84#ibcon#about to read 5, iclass 40, count 0 2006.182.08:25:00.84#ibcon#read 5, iclass 40, count 0 2006.182.08:25:00.84#ibcon#about to read 6, iclass 40, count 0 2006.182.08:25:00.84#ibcon#read 6, iclass 40, count 0 2006.182.08:25:00.84#ibcon#end of sib2, iclass 40, count 0 2006.182.08:25:00.84#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:25:00.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:25:00.84#ibcon#[27=USB\r\n] 2006.182.08:25:00.84#ibcon#*before write, iclass 40, count 0 2006.182.08:25:00.84#ibcon#enter sib2, iclass 40, count 0 2006.182.08:25:00.84#ibcon#flushed, iclass 40, count 0 2006.182.08:25:00.84#ibcon#about to write, iclass 40, count 0 2006.182.08:25:00.84#ibcon#wrote, iclass 40, count 0 2006.182.08:25:00.84#ibcon#about to read 3, iclass 40, count 0 2006.182.08:25:00.87#ibcon#read 3, iclass 40, count 0 2006.182.08:25:00.87#ibcon#about to read 4, iclass 40, count 0 2006.182.08:25:00.87#ibcon#read 4, iclass 40, count 0 2006.182.08:25:00.87#ibcon#about to read 5, iclass 40, count 0 2006.182.08:25:00.87#ibcon#read 5, iclass 40, count 0 2006.182.08:25:00.87#ibcon#about to read 6, iclass 40, count 0 2006.182.08:25:00.87#ibcon#read 6, iclass 40, count 0 2006.182.08:25:00.87#ibcon#end of sib2, iclass 40, count 0 2006.182.08:25:00.87#ibcon#*after write, iclass 40, count 0 2006.182.08:25:00.87#ibcon#*before return 0, iclass 40, count 0 2006.182.08:25:00.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:25:00.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.182.08:25:00.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:25:00.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:25:00.87$vc4f8/vblo=2,640.99 2006.182.08:25:00.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.182.08:25:00.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.182.08:25:00.87#ibcon#ireg 17 cls_cnt 0 2006.182.08:25:00.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:25:00.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:25:00.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:25:00.87#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:25:00.87#ibcon#first serial, iclass 4, count 0 2006.182.08:25:00.87#ibcon#enter sib2, iclass 4, count 0 2006.182.08:25:00.87#ibcon#flushed, iclass 4, count 0 2006.182.08:25:00.87#ibcon#about to write, iclass 4, count 0 2006.182.08:25:00.87#ibcon#wrote, iclass 4, count 0 2006.182.08:25:00.87#ibcon#about to read 3, iclass 4, count 0 2006.182.08:25:00.89#ibcon#read 3, iclass 4, count 0 2006.182.08:25:00.89#ibcon#about to read 4, iclass 4, count 0 2006.182.08:25:00.89#ibcon#read 4, iclass 4, count 0 2006.182.08:25:00.89#ibcon#about to read 5, iclass 4, count 0 2006.182.08:25:00.89#ibcon#read 5, iclass 4, count 0 2006.182.08:25:00.89#ibcon#about to read 6, iclass 4, count 0 2006.182.08:25:00.89#ibcon#read 6, iclass 4, count 0 2006.182.08:25:00.89#ibcon#end of sib2, iclass 4, count 0 2006.182.08:25:00.89#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:25:00.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:25:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:25:00.89#ibcon#*before write, iclass 4, count 0 2006.182.08:25:00.89#ibcon#enter sib2, iclass 4, count 0 2006.182.08:25:00.89#ibcon#flushed, iclass 4, count 0 2006.182.08:25:00.89#ibcon#about to write, iclass 4, count 0 2006.182.08:25:00.89#ibcon#wrote, iclass 4, count 0 2006.182.08:25:00.89#ibcon#about to read 3, iclass 4, count 0 2006.182.08:25:00.93#ibcon#read 3, iclass 4, count 0 2006.182.08:25:00.93#ibcon#about to read 4, iclass 4, count 0 2006.182.08:25:00.93#ibcon#read 4, iclass 4, count 0 2006.182.08:25:00.93#ibcon#about to read 5, iclass 4, count 0 2006.182.08:25:00.93#ibcon#read 5, iclass 4, count 0 2006.182.08:25:00.93#ibcon#about to read 6, iclass 4, count 0 2006.182.08:25:00.93#ibcon#read 6, iclass 4, count 0 2006.182.08:25:00.93#ibcon#end of sib2, iclass 4, count 0 2006.182.08:25:00.93#ibcon#*after write, iclass 4, count 0 2006.182.08:25:00.93#ibcon#*before return 0, iclass 4, count 0 2006.182.08:25:00.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:25:00.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.182.08:25:00.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:25:00.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:25:00.93$vc4f8/vb=2,4 2006.182.08:25:00.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.182.08:25:00.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.182.08:25:00.93#ibcon#ireg 11 cls_cnt 2 2006.182.08:25:00.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:25:00.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:25:00.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:25:00.99#ibcon#enter wrdev, iclass 6, count 2 2006.182.08:25:00.99#ibcon#first serial, iclass 6, count 2 2006.182.08:25:00.99#ibcon#enter sib2, iclass 6, count 2 2006.182.08:25:00.99#ibcon#flushed, iclass 6, count 2 2006.182.08:25:00.99#ibcon#about to write, iclass 6, count 2 2006.182.08:25:00.99#ibcon#wrote, iclass 6, count 2 2006.182.08:25:00.99#ibcon#about to read 3, iclass 6, count 2 2006.182.08:25:01.01#ibcon#read 3, iclass 6, count 2 2006.182.08:25:01.01#ibcon#about to read 4, iclass 6, count 2 2006.182.08:25:01.01#ibcon#read 4, iclass 6, count 2 2006.182.08:25:01.01#ibcon#about to read 5, iclass 6, count 2 2006.182.08:25:01.01#ibcon#read 5, iclass 6, count 2 2006.182.08:25:01.01#ibcon#about to read 6, iclass 6, count 2 2006.182.08:25:01.01#ibcon#read 6, iclass 6, count 2 2006.182.08:25:01.01#ibcon#end of sib2, iclass 6, count 2 2006.182.08:25:01.01#ibcon#*mode == 0, iclass 6, count 2 2006.182.08:25:01.01#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.182.08:25:01.01#ibcon#[27=AT02-04\r\n] 2006.182.08:25:01.01#ibcon#*before write, iclass 6, count 2 2006.182.08:25:01.01#ibcon#enter sib2, iclass 6, count 2 2006.182.08:25:01.01#ibcon#flushed, iclass 6, count 2 2006.182.08:25:01.01#ibcon#about to write, iclass 6, count 2 2006.182.08:25:01.01#ibcon#wrote, iclass 6, count 2 2006.182.08:25:01.01#ibcon#about to read 3, iclass 6, count 2 2006.182.08:25:01.04#ibcon#read 3, iclass 6, count 2 2006.182.08:25:01.04#ibcon#about to read 4, iclass 6, count 2 2006.182.08:25:01.04#ibcon#read 4, iclass 6, count 2 2006.182.08:25:01.04#ibcon#about to read 5, iclass 6, count 2 2006.182.08:25:01.04#ibcon#read 5, iclass 6, count 2 2006.182.08:25:01.04#ibcon#about to read 6, iclass 6, count 2 2006.182.08:25:01.04#ibcon#read 6, iclass 6, count 2 2006.182.08:25:01.04#ibcon#end of sib2, iclass 6, count 2 2006.182.08:25:01.04#ibcon#*after write, iclass 6, count 2 2006.182.08:25:01.04#ibcon#*before return 0, iclass 6, count 2 2006.182.08:25:01.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:25:01.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.182.08:25:01.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.182.08:25:01.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:25:01.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:25:01.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:25:01.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:25:01.16#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:25:01.16#ibcon#first serial, iclass 6, count 0 2006.182.08:25:01.16#ibcon#enter sib2, iclass 6, count 0 2006.182.08:25:01.16#ibcon#flushed, iclass 6, count 0 2006.182.08:25:01.16#ibcon#about to write, iclass 6, count 0 2006.182.08:25:01.16#ibcon#wrote, iclass 6, count 0 2006.182.08:25:01.16#ibcon#about to read 3, iclass 6, count 0 2006.182.08:25:01.18#ibcon#read 3, iclass 6, count 0 2006.182.08:25:01.18#ibcon#about to read 4, iclass 6, count 0 2006.182.08:25:01.18#ibcon#read 4, iclass 6, count 0 2006.182.08:25:01.18#ibcon#about to read 5, iclass 6, count 0 2006.182.08:25:01.18#ibcon#read 5, iclass 6, count 0 2006.182.08:25:01.18#ibcon#about to read 6, iclass 6, count 0 2006.182.08:25:01.18#ibcon#read 6, iclass 6, count 0 2006.182.08:25:01.18#ibcon#end of sib2, iclass 6, count 0 2006.182.08:25:01.18#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:25:01.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:25:01.18#ibcon#[27=USB\r\n] 2006.182.08:25:01.18#ibcon#*before write, iclass 6, count 0 2006.182.08:25:01.18#ibcon#enter sib2, iclass 6, count 0 2006.182.08:25:01.18#ibcon#flushed, iclass 6, count 0 2006.182.08:25:01.18#ibcon#about to write, iclass 6, count 0 2006.182.08:25:01.18#ibcon#wrote, iclass 6, count 0 2006.182.08:25:01.18#ibcon#about to read 3, iclass 6, count 0 2006.182.08:25:01.21#ibcon#read 3, iclass 6, count 0 2006.182.08:25:01.21#ibcon#about to read 4, iclass 6, count 0 2006.182.08:25:01.21#ibcon#read 4, iclass 6, count 0 2006.182.08:25:01.21#ibcon#about to read 5, iclass 6, count 0 2006.182.08:25:01.21#ibcon#read 5, iclass 6, count 0 2006.182.08:25:01.21#ibcon#about to read 6, iclass 6, count 0 2006.182.08:25:01.21#ibcon#read 6, iclass 6, count 0 2006.182.08:25:01.21#ibcon#end of sib2, iclass 6, count 0 2006.182.08:25:01.21#ibcon#*after write, iclass 6, count 0 2006.182.08:25:01.21#ibcon#*before return 0, iclass 6, count 0 2006.182.08:25:01.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:25:01.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.182.08:25:01.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:25:01.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:25:01.21$vc4f8/vblo=3,656.99 2006.182.08:25:01.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.182.08:25:01.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.182.08:25:01.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:25:01.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:25:01.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:25:01.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:25:01.21#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:25:01.21#ibcon#first serial, iclass 10, count 0 2006.182.08:25:01.21#ibcon#enter sib2, iclass 10, count 0 2006.182.08:25:01.21#ibcon#flushed, iclass 10, count 0 2006.182.08:25:01.21#ibcon#about to write, iclass 10, count 0 2006.182.08:25:01.21#ibcon#wrote, iclass 10, count 0 2006.182.08:25:01.21#ibcon#about to read 3, iclass 10, count 0 2006.182.08:25:01.23#ibcon#read 3, iclass 10, count 0 2006.182.08:25:01.23#ibcon#about to read 4, iclass 10, count 0 2006.182.08:25:01.23#ibcon#read 4, iclass 10, count 0 2006.182.08:25:01.23#ibcon#about to read 5, iclass 10, count 0 2006.182.08:25:01.23#ibcon#read 5, iclass 10, count 0 2006.182.08:25:01.23#ibcon#about to read 6, iclass 10, count 0 2006.182.08:25:01.23#ibcon#read 6, iclass 10, count 0 2006.182.08:25:01.23#ibcon#end of sib2, iclass 10, count 0 2006.182.08:25:01.23#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:25:01.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:25:01.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:25:01.23#ibcon#*before write, iclass 10, count 0 2006.182.08:25:01.23#ibcon#enter sib2, iclass 10, count 0 2006.182.08:25:01.23#ibcon#flushed, iclass 10, count 0 2006.182.08:25:01.23#ibcon#about to write, iclass 10, count 0 2006.182.08:25:01.23#ibcon#wrote, iclass 10, count 0 2006.182.08:25:01.23#ibcon#about to read 3, iclass 10, count 0 2006.182.08:25:01.27#ibcon#read 3, iclass 10, count 0 2006.182.08:25:01.27#ibcon#about to read 4, iclass 10, count 0 2006.182.08:25:01.27#ibcon#read 4, iclass 10, count 0 2006.182.08:25:01.27#ibcon#about to read 5, iclass 10, count 0 2006.182.08:25:01.27#ibcon#read 5, iclass 10, count 0 2006.182.08:25:01.27#ibcon#about to read 6, iclass 10, count 0 2006.182.08:25:01.27#ibcon#read 6, iclass 10, count 0 2006.182.08:25:01.27#ibcon#end of sib2, iclass 10, count 0 2006.182.08:25:01.27#ibcon#*after write, iclass 10, count 0 2006.182.08:25:01.27#ibcon#*before return 0, iclass 10, count 0 2006.182.08:25:01.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:25:01.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.182.08:25:01.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:25:01.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:25:01.27$vc4f8/vb=3,4 2006.182.08:25:01.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.182.08:25:01.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.182.08:25:01.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:25:01.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:25:01.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:25:01.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:25:01.33#ibcon#enter wrdev, iclass 12, count 2 2006.182.08:25:01.33#ibcon#first serial, iclass 12, count 2 2006.182.08:25:01.33#ibcon#enter sib2, iclass 12, count 2 2006.182.08:25:01.33#ibcon#flushed, iclass 12, count 2 2006.182.08:25:01.33#ibcon#about to write, iclass 12, count 2 2006.182.08:25:01.33#ibcon#wrote, iclass 12, count 2 2006.182.08:25:01.33#ibcon#about to read 3, iclass 12, count 2 2006.182.08:25:01.35#ibcon#read 3, iclass 12, count 2 2006.182.08:25:01.35#ibcon#about to read 4, iclass 12, count 2 2006.182.08:25:01.35#ibcon#read 4, iclass 12, count 2 2006.182.08:25:01.35#ibcon#about to read 5, iclass 12, count 2 2006.182.08:25:01.35#ibcon#read 5, iclass 12, count 2 2006.182.08:25:01.35#ibcon#about to read 6, iclass 12, count 2 2006.182.08:25:01.35#ibcon#read 6, iclass 12, count 2 2006.182.08:25:01.35#ibcon#end of sib2, iclass 12, count 2 2006.182.08:25:01.35#ibcon#*mode == 0, iclass 12, count 2 2006.182.08:25:01.35#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.182.08:25:01.35#ibcon#[27=AT03-04\r\n] 2006.182.08:25:01.35#ibcon#*before write, iclass 12, count 2 2006.182.08:25:01.35#ibcon#enter sib2, iclass 12, count 2 2006.182.08:25:01.35#ibcon#flushed, iclass 12, count 2 2006.182.08:25:01.35#ibcon#about to write, iclass 12, count 2 2006.182.08:25:01.35#ibcon#wrote, iclass 12, count 2 2006.182.08:25:01.35#ibcon#about to read 3, iclass 12, count 2 2006.182.08:25:01.38#ibcon#read 3, iclass 12, count 2 2006.182.08:25:01.38#ibcon#about to read 4, iclass 12, count 2 2006.182.08:25:01.38#ibcon#read 4, iclass 12, count 2 2006.182.08:25:01.38#ibcon#about to read 5, iclass 12, count 2 2006.182.08:25:01.38#ibcon#read 5, iclass 12, count 2 2006.182.08:25:01.38#ibcon#about to read 6, iclass 12, count 2 2006.182.08:25:01.38#ibcon#read 6, iclass 12, count 2 2006.182.08:25:01.38#ibcon#end of sib2, iclass 12, count 2 2006.182.08:25:01.38#ibcon#*after write, iclass 12, count 2 2006.182.08:25:01.38#ibcon#*before return 0, iclass 12, count 2 2006.182.08:25:01.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:25:01.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.182.08:25:01.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.182.08:25:01.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:25:01.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:25:01.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:25:01.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:25:01.50#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:25:01.50#ibcon#first serial, iclass 12, count 0 2006.182.08:25:01.50#ibcon#enter sib2, iclass 12, count 0 2006.182.08:25:01.50#ibcon#flushed, iclass 12, count 0 2006.182.08:25:01.50#ibcon#about to write, iclass 12, count 0 2006.182.08:25:01.50#ibcon#wrote, iclass 12, count 0 2006.182.08:25:01.50#ibcon#about to read 3, iclass 12, count 0 2006.182.08:25:01.52#ibcon#read 3, iclass 12, count 0 2006.182.08:25:01.52#ibcon#about to read 4, iclass 12, count 0 2006.182.08:25:01.52#ibcon#read 4, iclass 12, count 0 2006.182.08:25:01.52#ibcon#about to read 5, iclass 12, count 0 2006.182.08:25:01.52#ibcon#read 5, iclass 12, count 0 2006.182.08:25:01.52#ibcon#about to read 6, iclass 12, count 0 2006.182.08:25:01.52#ibcon#read 6, iclass 12, count 0 2006.182.08:25:01.52#ibcon#end of sib2, iclass 12, count 0 2006.182.08:25:01.52#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:25:01.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:25:01.52#ibcon#[27=USB\r\n] 2006.182.08:25:01.52#ibcon#*before write, iclass 12, count 0 2006.182.08:25:01.52#ibcon#enter sib2, iclass 12, count 0 2006.182.08:25:01.52#ibcon#flushed, iclass 12, count 0 2006.182.08:25:01.52#ibcon#about to write, iclass 12, count 0 2006.182.08:25:01.52#ibcon#wrote, iclass 12, count 0 2006.182.08:25:01.52#ibcon#about to read 3, iclass 12, count 0 2006.182.08:25:01.55#ibcon#read 3, iclass 12, count 0 2006.182.08:25:01.55#ibcon#about to read 4, iclass 12, count 0 2006.182.08:25:01.55#ibcon#read 4, iclass 12, count 0 2006.182.08:25:01.55#ibcon#about to read 5, iclass 12, count 0 2006.182.08:25:01.55#ibcon#read 5, iclass 12, count 0 2006.182.08:25:01.55#ibcon#about to read 6, iclass 12, count 0 2006.182.08:25:01.55#ibcon#read 6, iclass 12, count 0 2006.182.08:25:01.55#ibcon#end of sib2, iclass 12, count 0 2006.182.08:25:01.55#ibcon#*after write, iclass 12, count 0 2006.182.08:25:01.55#ibcon#*before return 0, iclass 12, count 0 2006.182.08:25:01.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:25:01.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.182.08:25:01.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:25:01.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:25:01.55$vc4f8/vblo=4,712.99 2006.182.08:25:01.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.182.08:25:01.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.182.08:25:01.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:25:01.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:25:01.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:25:01.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:25:01.55#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:25:01.55#ibcon#first serial, iclass 14, count 0 2006.182.08:25:01.55#ibcon#enter sib2, iclass 14, count 0 2006.182.08:25:01.55#ibcon#flushed, iclass 14, count 0 2006.182.08:25:01.55#ibcon#about to write, iclass 14, count 0 2006.182.08:25:01.55#ibcon#wrote, iclass 14, count 0 2006.182.08:25:01.55#ibcon#about to read 3, iclass 14, count 0 2006.182.08:25:01.57#ibcon#read 3, iclass 14, count 0 2006.182.08:25:01.57#ibcon#about to read 4, iclass 14, count 0 2006.182.08:25:01.57#ibcon#read 4, iclass 14, count 0 2006.182.08:25:01.57#ibcon#about to read 5, iclass 14, count 0 2006.182.08:25:01.57#ibcon#read 5, iclass 14, count 0 2006.182.08:25:01.57#ibcon#about to read 6, iclass 14, count 0 2006.182.08:25:01.57#ibcon#read 6, iclass 14, count 0 2006.182.08:25:01.57#ibcon#end of sib2, iclass 14, count 0 2006.182.08:25:01.57#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:25:01.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:25:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:25:01.57#ibcon#*before write, iclass 14, count 0 2006.182.08:25:01.57#ibcon#enter sib2, iclass 14, count 0 2006.182.08:25:01.57#ibcon#flushed, iclass 14, count 0 2006.182.08:25:01.57#ibcon#about to write, iclass 14, count 0 2006.182.08:25:01.57#ibcon#wrote, iclass 14, count 0 2006.182.08:25:01.57#ibcon#about to read 3, iclass 14, count 0 2006.182.08:25:01.61#ibcon#read 3, iclass 14, count 0 2006.182.08:25:01.61#ibcon#about to read 4, iclass 14, count 0 2006.182.08:25:01.61#ibcon#read 4, iclass 14, count 0 2006.182.08:25:01.61#ibcon#about to read 5, iclass 14, count 0 2006.182.08:25:01.61#ibcon#read 5, iclass 14, count 0 2006.182.08:25:01.61#ibcon#about to read 6, iclass 14, count 0 2006.182.08:25:01.61#ibcon#read 6, iclass 14, count 0 2006.182.08:25:01.61#ibcon#end of sib2, iclass 14, count 0 2006.182.08:25:01.61#ibcon#*after write, iclass 14, count 0 2006.182.08:25:01.61#ibcon#*before return 0, iclass 14, count 0 2006.182.08:25:01.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:25:01.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.182.08:25:01.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:25:01.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:25:01.61$vc4f8/vb=4,4 2006.182.08:25:01.61#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.182.08:25:01.61#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.182.08:25:01.61#ibcon#ireg 11 cls_cnt 2 2006.182.08:25:01.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:25:01.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:25:01.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:25:01.67#ibcon#enter wrdev, iclass 16, count 2 2006.182.08:25:01.67#ibcon#first serial, iclass 16, count 2 2006.182.08:25:01.67#ibcon#enter sib2, iclass 16, count 2 2006.182.08:25:01.67#ibcon#flushed, iclass 16, count 2 2006.182.08:25:01.67#ibcon#about to write, iclass 16, count 2 2006.182.08:25:01.67#ibcon#wrote, iclass 16, count 2 2006.182.08:25:01.67#ibcon#about to read 3, iclass 16, count 2 2006.182.08:25:01.69#ibcon#read 3, iclass 16, count 2 2006.182.08:25:01.69#ibcon#about to read 4, iclass 16, count 2 2006.182.08:25:01.69#ibcon#read 4, iclass 16, count 2 2006.182.08:25:01.69#ibcon#about to read 5, iclass 16, count 2 2006.182.08:25:01.69#ibcon#read 5, iclass 16, count 2 2006.182.08:25:01.69#ibcon#about to read 6, iclass 16, count 2 2006.182.08:25:01.69#ibcon#read 6, iclass 16, count 2 2006.182.08:25:01.69#ibcon#end of sib2, iclass 16, count 2 2006.182.08:25:01.69#ibcon#*mode == 0, iclass 16, count 2 2006.182.08:25:01.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.182.08:25:01.69#ibcon#[27=AT04-04\r\n] 2006.182.08:25:01.69#ibcon#*before write, iclass 16, count 2 2006.182.08:25:01.69#ibcon#enter sib2, iclass 16, count 2 2006.182.08:25:01.69#ibcon#flushed, iclass 16, count 2 2006.182.08:25:01.69#ibcon#about to write, iclass 16, count 2 2006.182.08:25:01.69#ibcon#wrote, iclass 16, count 2 2006.182.08:25:01.69#ibcon#about to read 3, iclass 16, count 2 2006.182.08:25:01.72#ibcon#read 3, iclass 16, count 2 2006.182.08:25:01.72#ibcon#about to read 4, iclass 16, count 2 2006.182.08:25:01.72#ibcon#read 4, iclass 16, count 2 2006.182.08:25:01.72#ibcon#about to read 5, iclass 16, count 2 2006.182.08:25:01.72#ibcon#read 5, iclass 16, count 2 2006.182.08:25:01.72#ibcon#about to read 6, iclass 16, count 2 2006.182.08:25:01.72#ibcon#read 6, iclass 16, count 2 2006.182.08:25:01.72#ibcon#end of sib2, iclass 16, count 2 2006.182.08:25:01.72#ibcon#*after write, iclass 16, count 2 2006.182.08:25:01.72#ibcon#*before return 0, iclass 16, count 2 2006.182.08:25:01.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:25:01.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.182.08:25:01.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.182.08:25:01.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:25:01.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:25:01.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:25:01.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:25:01.84#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:25:01.84#ibcon#first serial, iclass 16, count 0 2006.182.08:25:01.84#ibcon#enter sib2, iclass 16, count 0 2006.182.08:25:01.84#ibcon#flushed, iclass 16, count 0 2006.182.08:25:01.84#ibcon#about to write, iclass 16, count 0 2006.182.08:25:01.84#ibcon#wrote, iclass 16, count 0 2006.182.08:25:01.84#ibcon#about to read 3, iclass 16, count 0 2006.182.08:25:01.86#ibcon#read 3, iclass 16, count 0 2006.182.08:25:01.86#ibcon#about to read 4, iclass 16, count 0 2006.182.08:25:01.86#ibcon#read 4, iclass 16, count 0 2006.182.08:25:01.86#ibcon#about to read 5, iclass 16, count 0 2006.182.08:25:01.86#ibcon#read 5, iclass 16, count 0 2006.182.08:25:01.86#ibcon#about to read 6, iclass 16, count 0 2006.182.08:25:01.86#ibcon#read 6, iclass 16, count 0 2006.182.08:25:01.86#ibcon#end of sib2, iclass 16, count 0 2006.182.08:25:01.86#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:25:01.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:25:01.86#ibcon#[27=USB\r\n] 2006.182.08:25:01.86#ibcon#*before write, iclass 16, count 0 2006.182.08:25:01.86#ibcon#enter sib2, iclass 16, count 0 2006.182.08:25:01.86#ibcon#flushed, iclass 16, count 0 2006.182.08:25:01.86#ibcon#about to write, iclass 16, count 0 2006.182.08:25:01.86#ibcon#wrote, iclass 16, count 0 2006.182.08:25:01.86#ibcon#about to read 3, iclass 16, count 0 2006.182.08:25:01.89#ibcon#read 3, iclass 16, count 0 2006.182.08:25:01.89#ibcon#about to read 4, iclass 16, count 0 2006.182.08:25:01.89#ibcon#read 4, iclass 16, count 0 2006.182.08:25:01.89#ibcon#about to read 5, iclass 16, count 0 2006.182.08:25:01.89#ibcon#read 5, iclass 16, count 0 2006.182.08:25:01.89#ibcon#about to read 6, iclass 16, count 0 2006.182.08:25:01.89#ibcon#read 6, iclass 16, count 0 2006.182.08:25:01.89#ibcon#end of sib2, iclass 16, count 0 2006.182.08:25:01.89#ibcon#*after write, iclass 16, count 0 2006.182.08:25:01.89#ibcon#*before return 0, iclass 16, count 0 2006.182.08:25:01.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:25:01.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.182.08:25:01.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:25:01.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:25:01.89$vc4f8/vblo=5,744.99 2006.182.08:25:01.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.182.08:25:01.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.182.08:25:01.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:25:01.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:25:01.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:25:01.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:25:01.89#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:25:01.89#ibcon#first serial, iclass 18, count 0 2006.182.08:25:01.89#ibcon#enter sib2, iclass 18, count 0 2006.182.08:25:01.89#ibcon#flushed, iclass 18, count 0 2006.182.08:25:01.89#ibcon#about to write, iclass 18, count 0 2006.182.08:25:01.89#ibcon#wrote, iclass 18, count 0 2006.182.08:25:01.89#ibcon#about to read 3, iclass 18, count 0 2006.182.08:25:01.91#ibcon#read 3, iclass 18, count 0 2006.182.08:25:01.91#ibcon#about to read 4, iclass 18, count 0 2006.182.08:25:01.91#ibcon#read 4, iclass 18, count 0 2006.182.08:25:01.91#ibcon#about to read 5, iclass 18, count 0 2006.182.08:25:01.91#ibcon#read 5, iclass 18, count 0 2006.182.08:25:01.91#ibcon#about to read 6, iclass 18, count 0 2006.182.08:25:01.91#ibcon#read 6, iclass 18, count 0 2006.182.08:25:01.91#ibcon#end of sib2, iclass 18, count 0 2006.182.08:25:01.91#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:25:01.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:25:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:25:01.91#ibcon#*before write, iclass 18, count 0 2006.182.08:25:01.91#ibcon#enter sib2, iclass 18, count 0 2006.182.08:25:01.91#ibcon#flushed, iclass 18, count 0 2006.182.08:25:01.91#ibcon#about to write, iclass 18, count 0 2006.182.08:25:01.91#ibcon#wrote, iclass 18, count 0 2006.182.08:25:01.91#ibcon#about to read 3, iclass 18, count 0 2006.182.08:25:01.95#ibcon#read 3, iclass 18, count 0 2006.182.08:25:01.95#ibcon#about to read 4, iclass 18, count 0 2006.182.08:25:01.95#ibcon#read 4, iclass 18, count 0 2006.182.08:25:01.95#ibcon#about to read 5, iclass 18, count 0 2006.182.08:25:01.95#ibcon#read 5, iclass 18, count 0 2006.182.08:25:01.95#ibcon#about to read 6, iclass 18, count 0 2006.182.08:25:01.95#ibcon#read 6, iclass 18, count 0 2006.182.08:25:01.95#ibcon#end of sib2, iclass 18, count 0 2006.182.08:25:01.95#ibcon#*after write, iclass 18, count 0 2006.182.08:25:01.95#ibcon#*before return 0, iclass 18, count 0 2006.182.08:25:01.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:25:01.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.182.08:25:01.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:25:01.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:25:01.95$vc4f8/vb=5,4 2006.182.08:25:01.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.182.08:25:01.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.182.08:25:01.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:25:01.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:25:02.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:25:02.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:25:02.01#ibcon#enter wrdev, iclass 20, count 2 2006.182.08:25:02.01#ibcon#first serial, iclass 20, count 2 2006.182.08:25:02.01#ibcon#enter sib2, iclass 20, count 2 2006.182.08:25:02.01#ibcon#flushed, iclass 20, count 2 2006.182.08:25:02.01#ibcon#about to write, iclass 20, count 2 2006.182.08:25:02.01#ibcon#wrote, iclass 20, count 2 2006.182.08:25:02.01#ibcon#about to read 3, iclass 20, count 2 2006.182.08:25:02.03#ibcon#read 3, iclass 20, count 2 2006.182.08:25:02.03#ibcon#about to read 4, iclass 20, count 2 2006.182.08:25:02.03#ibcon#read 4, iclass 20, count 2 2006.182.08:25:02.03#ibcon#about to read 5, iclass 20, count 2 2006.182.08:25:02.03#ibcon#read 5, iclass 20, count 2 2006.182.08:25:02.03#ibcon#about to read 6, iclass 20, count 2 2006.182.08:25:02.03#ibcon#read 6, iclass 20, count 2 2006.182.08:25:02.03#ibcon#end of sib2, iclass 20, count 2 2006.182.08:25:02.03#ibcon#*mode == 0, iclass 20, count 2 2006.182.08:25:02.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.182.08:25:02.03#ibcon#[27=AT05-04\r\n] 2006.182.08:25:02.03#ibcon#*before write, iclass 20, count 2 2006.182.08:25:02.03#ibcon#enter sib2, iclass 20, count 2 2006.182.08:25:02.03#ibcon#flushed, iclass 20, count 2 2006.182.08:25:02.03#ibcon#about to write, iclass 20, count 2 2006.182.08:25:02.03#ibcon#wrote, iclass 20, count 2 2006.182.08:25:02.03#ibcon#about to read 3, iclass 20, count 2 2006.182.08:25:02.06#ibcon#read 3, iclass 20, count 2 2006.182.08:25:02.06#ibcon#about to read 4, iclass 20, count 2 2006.182.08:25:02.06#ibcon#read 4, iclass 20, count 2 2006.182.08:25:02.06#ibcon#about to read 5, iclass 20, count 2 2006.182.08:25:02.06#ibcon#read 5, iclass 20, count 2 2006.182.08:25:02.06#ibcon#about to read 6, iclass 20, count 2 2006.182.08:25:02.06#ibcon#read 6, iclass 20, count 2 2006.182.08:25:02.06#ibcon#end of sib2, iclass 20, count 2 2006.182.08:25:02.06#ibcon#*after write, iclass 20, count 2 2006.182.08:25:02.06#ibcon#*before return 0, iclass 20, count 2 2006.182.08:25:02.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:25:02.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.182.08:25:02.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.182.08:25:02.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:25:02.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:25:02.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:25:02.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:25:02.18#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:25:02.18#ibcon#first serial, iclass 20, count 0 2006.182.08:25:02.18#ibcon#enter sib2, iclass 20, count 0 2006.182.08:25:02.18#ibcon#flushed, iclass 20, count 0 2006.182.08:25:02.18#ibcon#about to write, iclass 20, count 0 2006.182.08:25:02.18#ibcon#wrote, iclass 20, count 0 2006.182.08:25:02.18#ibcon#about to read 3, iclass 20, count 0 2006.182.08:25:02.21#ibcon#read 3, iclass 20, count 0 2006.182.08:25:02.21#ibcon#about to read 4, iclass 20, count 0 2006.182.08:25:02.21#ibcon#read 4, iclass 20, count 0 2006.182.08:25:02.21#ibcon#about to read 5, iclass 20, count 0 2006.182.08:25:02.21#ibcon#read 5, iclass 20, count 0 2006.182.08:25:02.21#ibcon#about to read 6, iclass 20, count 0 2006.182.08:25:02.21#ibcon#read 6, iclass 20, count 0 2006.182.08:25:02.21#ibcon#end of sib2, iclass 20, count 0 2006.182.08:25:02.21#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:25:02.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:25:02.21#ibcon#[27=USB\r\n] 2006.182.08:25:02.21#ibcon#*before write, iclass 20, count 0 2006.182.08:25:02.21#ibcon#enter sib2, iclass 20, count 0 2006.182.08:25:02.21#ibcon#flushed, iclass 20, count 0 2006.182.08:25:02.21#ibcon#about to write, iclass 20, count 0 2006.182.08:25:02.21#ibcon#wrote, iclass 20, count 0 2006.182.08:25:02.21#ibcon#about to read 3, iclass 20, count 0 2006.182.08:25:02.24#ibcon#read 3, iclass 20, count 0 2006.182.08:25:02.24#ibcon#about to read 4, iclass 20, count 0 2006.182.08:25:02.24#ibcon#read 4, iclass 20, count 0 2006.182.08:25:02.24#ibcon#about to read 5, iclass 20, count 0 2006.182.08:25:02.24#ibcon#read 5, iclass 20, count 0 2006.182.08:25:02.24#ibcon#about to read 6, iclass 20, count 0 2006.182.08:25:02.24#ibcon#read 6, iclass 20, count 0 2006.182.08:25:02.24#ibcon#end of sib2, iclass 20, count 0 2006.182.08:25:02.24#ibcon#*after write, iclass 20, count 0 2006.182.08:25:02.24#ibcon#*before return 0, iclass 20, count 0 2006.182.08:25:02.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:25:02.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.182.08:25:02.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:25:02.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:25:02.24$vc4f8/vblo=6,752.99 2006.182.08:25:02.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.182.08:25:02.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.182.08:25:02.24#ibcon#ireg 17 cls_cnt 0 2006.182.08:25:02.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:25:02.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:25:02.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:25:02.24#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:25:02.24#ibcon#first serial, iclass 22, count 0 2006.182.08:25:02.24#ibcon#enter sib2, iclass 22, count 0 2006.182.08:25:02.24#ibcon#flushed, iclass 22, count 0 2006.182.08:25:02.24#ibcon#about to write, iclass 22, count 0 2006.182.08:25:02.24#ibcon#wrote, iclass 22, count 0 2006.182.08:25:02.24#ibcon#about to read 3, iclass 22, count 0 2006.182.08:25:02.26#ibcon#read 3, iclass 22, count 0 2006.182.08:25:02.26#ibcon#about to read 4, iclass 22, count 0 2006.182.08:25:02.26#ibcon#read 4, iclass 22, count 0 2006.182.08:25:02.26#ibcon#about to read 5, iclass 22, count 0 2006.182.08:25:02.26#ibcon#read 5, iclass 22, count 0 2006.182.08:25:02.26#ibcon#about to read 6, iclass 22, count 0 2006.182.08:25:02.26#ibcon#read 6, iclass 22, count 0 2006.182.08:25:02.26#ibcon#end of sib2, iclass 22, count 0 2006.182.08:25:02.26#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:25:02.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:25:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:25:02.26#ibcon#*before write, iclass 22, count 0 2006.182.08:25:02.26#ibcon#enter sib2, iclass 22, count 0 2006.182.08:25:02.26#ibcon#flushed, iclass 22, count 0 2006.182.08:25:02.26#ibcon#about to write, iclass 22, count 0 2006.182.08:25:02.26#ibcon#wrote, iclass 22, count 0 2006.182.08:25:02.26#ibcon#about to read 3, iclass 22, count 0 2006.182.08:25:02.30#ibcon#read 3, iclass 22, count 0 2006.182.08:25:02.30#ibcon#about to read 4, iclass 22, count 0 2006.182.08:25:02.30#ibcon#read 4, iclass 22, count 0 2006.182.08:25:02.30#ibcon#about to read 5, iclass 22, count 0 2006.182.08:25:02.30#ibcon#read 5, iclass 22, count 0 2006.182.08:25:02.30#ibcon#about to read 6, iclass 22, count 0 2006.182.08:25:02.30#ibcon#read 6, iclass 22, count 0 2006.182.08:25:02.30#ibcon#end of sib2, iclass 22, count 0 2006.182.08:25:02.30#ibcon#*after write, iclass 22, count 0 2006.182.08:25:02.30#ibcon#*before return 0, iclass 22, count 0 2006.182.08:25:02.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:25:02.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.182.08:25:02.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:25:02.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:25:02.30$vc4f8/vb=6,4 2006.182.08:25:02.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.182.08:25:02.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.182.08:25:02.30#ibcon#ireg 11 cls_cnt 2 2006.182.08:25:02.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:25:02.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:25:02.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:25:02.36#ibcon#enter wrdev, iclass 24, count 2 2006.182.08:25:02.36#ibcon#first serial, iclass 24, count 2 2006.182.08:25:02.36#ibcon#enter sib2, iclass 24, count 2 2006.182.08:25:02.36#ibcon#flushed, iclass 24, count 2 2006.182.08:25:02.36#ibcon#about to write, iclass 24, count 2 2006.182.08:25:02.36#ibcon#wrote, iclass 24, count 2 2006.182.08:25:02.36#ibcon#about to read 3, iclass 24, count 2 2006.182.08:25:02.38#ibcon#read 3, iclass 24, count 2 2006.182.08:25:02.38#ibcon#about to read 4, iclass 24, count 2 2006.182.08:25:02.38#ibcon#read 4, iclass 24, count 2 2006.182.08:25:02.38#ibcon#about to read 5, iclass 24, count 2 2006.182.08:25:02.38#ibcon#read 5, iclass 24, count 2 2006.182.08:25:02.38#ibcon#about to read 6, iclass 24, count 2 2006.182.08:25:02.38#ibcon#read 6, iclass 24, count 2 2006.182.08:25:02.38#ibcon#end of sib2, iclass 24, count 2 2006.182.08:25:02.38#ibcon#*mode == 0, iclass 24, count 2 2006.182.08:25:02.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.182.08:25:02.38#ibcon#[27=AT06-04\r\n] 2006.182.08:25:02.38#ibcon#*before write, iclass 24, count 2 2006.182.08:25:02.38#ibcon#enter sib2, iclass 24, count 2 2006.182.08:25:02.38#ibcon#flushed, iclass 24, count 2 2006.182.08:25:02.38#ibcon#about to write, iclass 24, count 2 2006.182.08:25:02.38#ibcon#wrote, iclass 24, count 2 2006.182.08:25:02.38#ibcon#about to read 3, iclass 24, count 2 2006.182.08:25:02.41#ibcon#read 3, iclass 24, count 2 2006.182.08:25:02.41#ibcon#about to read 4, iclass 24, count 2 2006.182.08:25:02.41#ibcon#read 4, iclass 24, count 2 2006.182.08:25:02.41#ibcon#about to read 5, iclass 24, count 2 2006.182.08:25:02.41#ibcon#read 5, iclass 24, count 2 2006.182.08:25:02.41#ibcon#about to read 6, iclass 24, count 2 2006.182.08:25:02.41#ibcon#read 6, iclass 24, count 2 2006.182.08:25:02.41#ibcon#end of sib2, iclass 24, count 2 2006.182.08:25:02.41#ibcon#*after write, iclass 24, count 2 2006.182.08:25:02.41#ibcon#*before return 0, iclass 24, count 2 2006.182.08:25:02.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:25:02.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.182.08:25:02.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.182.08:25:02.41#ibcon#ireg 7 cls_cnt 0 2006.182.08:25:02.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:25:02.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:25:02.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:25:02.53#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:25:02.53#ibcon#first serial, iclass 24, count 0 2006.182.08:25:02.53#ibcon#enter sib2, iclass 24, count 0 2006.182.08:25:02.53#ibcon#flushed, iclass 24, count 0 2006.182.08:25:02.53#ibcon#about to write, iclass 24, count 0 2006.182.08:25:02.53#ibcon#wrote, iclass 24, count 0 2006.182.08:25:02.53#ibcon#about to read 3, iclass 24, count 0 2006.182.08:25:02.55#ibcon#read 3, iclass 24, count 0 2006.182.08:25:02.55#ibcon#about to read 4, iclass 24, count 0 2006.182.08:25:02.55#ibcon#read 4, iclass 24, count 0 2006.182.08:25:02.55#ibcon#about to read 5, iclass 24, count 0 2006.182.08:25:02.55#ibcon#read 5, iclass 24, count 0 2006.182.08:25:02.55#ibcon#about to read 6, iclass 24, count 0 2006.182.08:25:02.55#ibcon#read 6, iclass 24, count 0 2006.182.08:25:02.55#ibcon#end of sib2, iclass 24, count 0 2006.182.08:25:02.55#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:25:02.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:25:02.55#ibcon#[27=USB\r\n] 2006.182.08:25:02.55#ibcon#*before write, iclass 24, count 0 2006.182.08:25:02.55#ibcon#enter sib2, iclass 24, count 0 2006.182.08:25:02.55#ibcon#flushed, iclass 24, count 0 2006.182.08:25:02.55#ibcon#about to write, iclass 24, count 0 2006.182.08:25:02.55#ibcon#wrote, iclass 24, count 0 2006.182.08:25:02.55#ibcon#about to read 3, iclass 24, count 0 2006.182.08:25:02.58#ibcon#read 3, iclass 24, count 0 2006.182.08:25:02.58#ibcon#about to read 4, iclass 24, count 0 2006.182.08:25:02.58#ibcon#read 4, iclass 24, count 0 2006.182.08:25:02.58#ibcon#about to read 5, iclass 24, count 0 2006.182.08:25:02.58#ibcon#read 5, iclass 24, count 0 2006.182.08:25:02.58#ibcon#about to read 6, iclass 24, count 0 2006.182.08:25:02.58#ibcon#read 6, iclass 24, count 0 2006.182.08:25:02.58#ibcon#end of sib2, iclass 24, count 0 2006.182.08:25:02.58#ibcon#*after write, iclass 24, count 0 2006.182.08:25:02.58#ibcon#*before return 0, iclass 24, count 0 2006.182.08:25:02.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:25:02.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.182.08:25:02.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:25:02.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:25:02.58$vc4f8/vabw=wide 2006.182.08:25:02.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.182.08:25:02.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.182.08:25:02.58#ibcon#ireg 8 cls_cnt 0 2006.182.08:25:02.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:25:02.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:25:02.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:25:02.58#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:25:02.58#ibcon#first serial, iclass 26, count 0 2006.182.08:25:02.58#ibcon#enter sib2, iclass 26, count 0 2006.182.08:25:02.58#ibcon#flushed, iclass 26, count 0 2006.182.08:25:02.58#ibcon#about to write, iclass 26, count 0 2006.182.08:25:02.58#ibcon#wrote, iclass 26, count 0 2006.182.08:25:02.58#ibcon#about to read 3, iclass 26, count 0 2006.182.08:25:02.60#ibcon#read 3, iclass 26, count 0 2006.182.08:25:02.60#ibcon#about to read 4, iclass 26, count 0 2006.182.08:25:02.60#ibcon#read 4, iclass 26, count 0 2006.182.08:25:02.60#ibcon#about to read 5, iclass 26, count 0 2006.182.08:25:02.60#ibcon#read 5, iclass 26, count 0 2006.182.08:25:02.60#ibcon#about to read 6, iclass 26, count 0 2006.182.08:25:02.60#ibcon#read 6, iclass 26, count 0 2006.182.08:25:02.60#ibcon#end of sib2, iclass 26, count 0 2006.182.08:25:02.60#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:25:02.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:25:02.60#ibcon#[25=BW32\r\n] 2006.182.08:25:02.60#ibcon#*before write, iclass 26, count 0 2006.182.08:25:02.60#ibcon#enter sib2, iclass 26, count 0 2006.182.08:25:02.60#ibcon#flushed, iclass 26, count 0 2006.182.08:25:02.60#ibcon#about to write, iclass 26, count 0 2006.182.08:25:02.60#ibcon#wrote, iclass 26, count 0 2006.182.08:25:02.60#ibcon#about to read 3, iclass 26, count 0 2006.182.08:25:02.63#ibcon#read 3, iclass 26, count 0 2006.182.08:25:02.63#ibcon#about to read 4, iclass 26, count 0 2006.182.08:25:02.63#ibcon#read 4, iclass 26, count 0 2006.182.08:25:02.63#ibcon#about to read 5, iclass 26, count 0 2006.182.08:25:02.63#ibcon#read 5, iclass 26, count 0 2006.182.08:25:02.63#ibcon#about to read 6, iclass 26, count 0 2006.182.08:25:02.63#ibcon#read 6, iclass 26, count 0 2006.182.08:25:02.63#ibcon#end of sib2, iclass 26, count 0 2006.182.08:25:02.63#ibcon#*after write, iclass 26, count 0 2006.182.08:25:02.63#ibcon#*before return 0, iclass 26, count 0 2006.182.08:25:02.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:25:02.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.182.08:25:02.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:25:02.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:25:02.63$vc4f8/vbbw=wide 2006.182.08:25:02.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.08:25:02.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.08:25:02.63#ibcon#ireg 8 cls_cnt 0 2006.182.08:25:02.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:25:02.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:25:02.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:25:02.70#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:25:02.70#ibcon#first serial, iclass 28, count 0 2006.182.08:25:02.70#ibcon#enter sib2, iclass 28, count 0 2006.182.08:25:02.70#ibcon#flushed, iclass 28, count 0 2006.182.08:25:02.70#ibcon#about to write, iclass 28, count 0 2006.182.08:25:02.70#ibcon#wrote, iclass 28, count 0 2006.182.08:25:02.70#ibcon#about to read 3, iclass 28, count 0 2006.182.08:25:02.72#ibcon#read 3, iclass 28, count 0 2006.182.08:25:02.72#ibcon#about to read 4, iclass 28, count 0 2006.182.08:25:02.72#ibcon#read 4, iclass 28, count 0 2006.182.08:25:02.72#ibcon#about to read 5, iclass 28, count 0 2006.182.08:25:02.72#ibcon#read 5, iclass 28, count 0 2006.182.08:25:02.72#ibcon#about to read 6, iclass 28, count 0 2006.182.08:25:02.72#ibcon#read 6, iclass 28, count 0 2006.182.08:25:02.72#ibcon#end of sib2, iclass 28, count 0 2006.182.08:25:02.72#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:25:02.72#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:25:02.72#ibcon#[27=BW32\r\n] 2006.182.08:25:02.72#ibcon#*before write, iclass 28, count 0 2006.182.08:25:02.72#ibcon#enter sib2, iclass 28, count 0 2006.182.08:25:02.72#ibcon#flushed, iclass 28, count 0 2006.182.08:25:02.72#ibcon#about to write, iclass 28, count 0 2006.182.08:25:02.72#ibcon#wrote, iclass 28, count 0 2006.182.08:25:02.72#ibcon#about to read 3, iclass 28, count 0 2006.182.08:25:02.75#ibcon#read 3, iclass 28, count 0 2006.182.08:25:02.75#ibcon#about to read 4, iclass 28, count 0 2006.182.08:25:02.75#ibcon#read 4, iclass 28, count 0 2006.182.08:25:02.75#ibcon#about to read 5, iclass 28, count 0 2006.182.08:25:02.75#ibcon#read 5, iclass 28, count 0 2006.182.08:25:02.75#ibcon#about to read 6, iclass 28, count 0 2006.182.08:25:02.75#ibcon#read 6, iclass 28, count 0 2006.182.08:25:02.75#ibcon#end of sib2, iclass 28, count 0 2006.182.08:25:02.75#ibcon#*after write, iclass 28, count 0 2006.182.08:25:02.75#ibcon#*before return 0, iclass 28, count 0 2006.182.08:25:02.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:25:02.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:25:02.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:25:02.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:25:02.75$4f8m12a/ifd4f 2006.182.08:25:02.75$ifd4f/lo= 2006.182.08:25:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:25:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:25:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:25:02.75$ifd4f/patch= 2006.182.08:25:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:25:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:25:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:25:02.75$4f8m12a/"form=m,16.000,1:2 2006.182.08:25:02.75$4f8m12a/"tpicd 2006.182.08:25:02.75$4f8m12a/echo=off 2006.182.08:25:02.75$4f8m12a/xlog=off 2006.182.08:25:02.75:!2006.182.08:25:40 2006.182.08:25:18.14#trakl#Source acquired 2006.182.08:25:18.14#flagr#flagr/antenna,acquired 2006.182.08:25:40.00:preob 2006.182.08:25:40.14/onsource/TRACKING 2006.182.08:25:40.14:!2006.182.08:25:50 2006.182.08:25:50.00:data_valid=on 2006.182.08:25:50.00:midob 2006.182.08:25:51.14/onsource/TRACKING 2006.182.08:25:51.14/wx/27.65,1002.9,81 2006.182.08:25:51.25/cable/+6.4629E-03 2006.182.08:25:52.34/va/01,08,usb,yes,30,31 2006.182.08:25:52.34/va/02,07,usb,yes,30,31 2006.182.08:25:52.34/va/03,06,usb,yes,31,32 2006.182.08:25:52.34/va/04,07,usb,yes,31,33 2006.182.08:25:52.34/va/05,07,usb,yes,32,33 2006.182.08:25:52.34/va/06,06,usb,yes,31,31 2006.182.08:25:52.34/va/07,06,usb,yes,31,31 2006.182.08:25:52.34/va/08,07,usb,yes,30,29 2006.182.08:25:52.57/valo/01,532.99,yes,locked 2006.182.08:25:52.57/valo/02,572.99,yes,locked 2006.182.08:25:52.57/valo/03,672.99,yes,locked 2006.182.08:25:52.57/valo/04,832.99,yes,locked 2006.182.08:25:52.57/valo/05,652.99,yes,locked 2006.182.08:25:52.57/valo/06,772.99,yes,locked 2006.182.08:25:52.57/valo/07,832.99,yes,locked 2006.182.08:25:52.57/valo/08,852.99,yes,locked 2006.182.08:25:53.66/vb/01,04,usb,yes,30,28 2006.182.08:25:53.66/vb/02,04,usb,yes,31,33 2006.182.08:25:53.66/vb/03,04,usb,yes,28,32 2006.182.08:25:53.66/vb/04,04,usb,yes,29,29 2006.182.08:25:53.66/vb/05,04,usb,yes,27,31 2006.182.08:25:53.66/vb/06,04,usb,yes,28,31 2006.182.08:25:53.66/vb/07,04,usb,yes,30,30 2006.182.08:25:53.66/vb/08,04,usb,yes,28,31 2006.182.08:25:53.90/vblo/01,632.99,yes,locked 2006.182.08:25:53.90/vblo/02,640.99,yes,locked 2006.182.08:25:53.90/vblo/03,656.99,yes,locked 2006.182.08:25:53.90/vblo/04,712.99,yes,locked 2006.182.08:25:53.90/vblo/05,744.99,yes,locked 2006.182.08:25:53.90/vblo/06,752.99,yes,locked 2006.182.08:25:53.90/vblo/07,734.99,yes,locked 2006.182.08:25:53.90/vblo/08,744.99,yes,locked 2006.182.08:25:54.05/vabw/8 2006.182.08:25:54.20/vbbw/8 2006.182.08:25:54.29/xfe/off,on,14.2 2006.182.08:25:54.67/ifatt/23,28,28,28 2006.182.08:25:55.08/fmout-gps/S +3.51E-07 2006.182.08:25:55.15:!2006.182.08:26:50 2006.182.08:26:50.00:data_valid=off 2006.182.08:26:50.00:postob 2006.182.08:26:50.20/cable/+6.4642E-03 2006.182.08:26:50.20/wx/27.64,1002.9,80 2006.182.08:26:51.08/fmout-gps/S +3.50E-07 2006.182.08:26:51.08:scan_name=182-0828,k06182,60 2006.182.08:26:51.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.182.08:26:51.14#flagr#flagr/antenna,new-source 2006.182.08:26:52.14:checkk5 2006.182.08:26:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:26:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:26:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:26:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:26:54.01/chk_obsdata//k5ts1/T1820825??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:26:54.38/chk_obsdata//k5ts2/T1820825??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:26:54.75/chk_obsdata//k5ts3/T1820825??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:26:55.11/chk_obsdata//k5ts4/T1820825??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:26:55.81/k5log//k5ts1_log_newline 2006.182.08:26:56.50/k5log//k5ts2_log_newline 2006.182.08:26:57.19/k5log//k5ts3_log_newline 2006.182.08:26:57.87/k5log//k5ts4_log_newline 2006.182.08:26:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:26:57.90:4f8m12a=3 2006.182.08:26:57.90$4f8m12a/echo=on 2006.182.08:26:57.90$4f8m12a/pcalon 2006.182.08:26:57.90$pcalon/"no phase cal control is implemented here 2006.182.08:26:57.90$4f8m12a/"tpicd=stop 2006.182.08:26:57.90$4f8m12a/vc4f8 2006.182.08:26:57.90$vc4f8/valo=1,532.99 2006.182.08:26:57.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.08:26:57.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.08:26:57.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:26:57.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:26:57.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:26:57.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:26:57.90#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:26:57.90#ibcon#first serial, iclass 39, count 0 2006.182.08:26:57.90#ibcon#enter sib2, iclass 39, count 0 2006.182.08:26:57.90#ibcon#flushed, iclass 39, count 0 2006.182.08:26:57.90#ibcon#about to write, iclass 39, count 0 2006.182.08:26:57.90#ibcon#wrote, iclass 39, count 0 2006.182.08:26:57.90#ibcon#about to read 3, iclass 39, count 0 2006.182.08:26:57.94#ibcon#read 3, iclass 39, count 0 2006.182.08:26:57.94#ibcon#about to read 4, iclass 39, count 0 2006.182.08:26:57.94#ibcon#read 4, iclass 39, count 0 2006.182.08:26:57.94#ibcon#about to read 5, iclass 39, count 0 2006.182.08:26:57.94#ibcon#read 5, iclass 39, count 0 2006.182.08:26:57.94#ibcon#about to read 6, iclass 39, count 0 2006.182.08:26:57.94#ibcon#read 6, iclass 39, count 0 2006.182.08:26:57.94#ibcon#end of sib2, iclass 39, count 0 2006.182.08:26:57.94#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:26:57.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:26:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:26:57.94#ibcon#*before write, iclass 39, count 0 2006.182.08:26:57.94#ibcon#enter sib2, iclass 39, count 0 2006.182.08:26:57.94#ibcon#flushed, iclass 39, count 0 2006.182.08:26:57.94#ibcon#about to write, iclass 39, count 0 2006.182.08:26:57.94#ibcon#wrote, iclass 39, count 0 2006.182.08:26:57.94#ibcon#about to read 3, iclass 39, count 0 2006.182.08:26:57.99#ibcon#read 3, iclass 39, count 0 2006.182.08:26:57.99#ibcon#about to read 4, iclass 39, count 0 2006.182.08:26:57.99#ibcon#read 4, iclass 39, count 0 2006.182.08:26:57.99#ibcon#about to read 5, iclass 39, count 0 2006.182.08:26:57.99#ibcon#read 5, iclass 39, count 0 2006.182.08:26:57.99#ibcon#about to read 6, iclass 39, count 0 2006.182.08:26:57.99#ibcon#read 6, iclass 39, count 0 2006.182.08:26:57.99#ibcon#end of sib2, iclass 39, count 0 2006.182.08:26:57.99#ibcon#*after write, iclass 39, count 0 2006.182.08:26:57.99#ibcon#*before return 0, iclass 39, count 0 2006.182.08:26:57.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:26:57.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:26:57.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:26:57.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:26:57.99$vc4f8/va=1,8 2006.182.08:26:57.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.08:26:57.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.08:26:57.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:26:57.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:26:57.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:26:57.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:26:57.99#ibcon#enter wrdev, iclass 3, count 2 2006.182.08:26:57.99#ibcon#first serial, iclass 3, count 2 2006.182.08:26:57.99#ibcon#enter sib2, iclass 3, count 2 2006.182.08:26:57.99#ibcon#flushed, iclass 3, count 2 2006.182.08:26:57.99#ibcon#about to write, iclass 3, count 2 2006.182.08:26:57.99#ibcon#wrote, iclass 3, count 2 2006.182.08:26:57.99#ibcon#about to read 3, iclass 3, count 2 2006.182.08:26:58.01#ibcon#read 3, iclass 3, count 2 2006.182.08:26:58.01#ibcon#about to read 4, iclass 3, count 2 2006.182.08:26:58.01#ibcon#read 4, iclass 3, count 2 2006.182.08:26:58.01#ibcon#about to read 5, iclass 3, count 2 2006.182.08:26:58.01#ibcon#read 5, iclass 3, count 2 2006.182.08:26:58.01#ibcon#about to read 6, iclass 3, count 2 2006.182.08:26:58.01#ibcon#read 6, iclass 3, count 2 2006.182.08:26:58.01#ibcon#end of sib2, iclass 3, count 2 2006.182.08:26:58.01#ibcon#*mode == 0, iclass 3, count 2 2006.182.08:26:58.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.08:26:58.01#ibcon#[25=AT01-08\r\n] 2006.182.08:26:58.01#ibcon#*before write, iclass 3, count 2 2006.182.08:26:58.01#ibcon#enter sib2, iclass 3, count 2 2006.182.08:26:58.01#ibcon#flushed, iclass 3, count 2 2006.182.08:26:58.01#ibcon#about to write, iclass 3, count 2 2006.182.08:26:58.01#ibcon#wrote, iclass 3, count 2 2006.182.08:26:58.01#ibcon#about to read 3, iclass 3, count 2 2006.182.08:26:58.04#ibcon#read 3, iclass 3, count 2 2006.182.08:26:58.04#ibcon#about to read 4, iclass 3, count 2 2006.182.08:26:58.04#ibcon#read 4, iclass 3, count 2 2006.182.08:26:58.04#ibcon#about to read 5, iclass 3, count 2 2006.182.08:26:58.04#ibcon#read 5, iclass 3, count 2 2006.182.08:26:58.04#ibcon#about to read 6, iclass 3, count 2 2006.182.08:26:58.04#ibcon#read 6, iclass 3, count 2 2006.182.08:26:58.04#ibcon#end of sib2, iclass 3, count 2 2006.182.08:26:58.04#ibcon#*after write, iclass 3, count 2 2006.182.08:26:58.04#ibcon#*before return 0, iclass 3, count 2 2006.182.08:26:58.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:26:58.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:26:58.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.08:26:58.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:26:58.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:26:58.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:26:58.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:26:58.16#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:26:58.16#ibcon#first serial, iclass 3, count 0 2006.182.08:26:58.16#ibcon#enter sib2, iclass 3, count 0 2006.182.08:26:58.16#ibcon#flushed, iclass 3, count 0 2006.182.08:26:58.16#ibcon#about to write, iclass 3, count 0 2006.182.08:26:58.16#ibcon#wrote, iclass 3, count 0 2006.182.08:26:58.16#ibcon#about to read 3, iclass 3, count 0 2006.182.08:26:58.18#ibcon#read 3, iclass 3, count 0 2006.182.08:26:58.18#ibcon#about to read 4, iclass 3, count 0 2006.182.08:26:58.18#ibcon#read 4, iclass 3, count 0 2006.182.08:26:58.18#ibcon#about to read 5, iclass 3, count 0 2006.182.08:26:58.18#ibcon#read 5, iclass 3, count 0 2006.182.08:26:58.18#ibcon#about to read 6, iclass 3, count 0 2006.182.08:26:58.18#ibcon#read 6, iclass 3, count 0 2006.182.08:26:58.18#ibcon#end of sib2, iclass 3, count 0 2006.182.08:26:58.18#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:26:58.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:26:58.18#ibcon#[25=USB\r\n] 2006.182.08:26:58.18#ibcon#*before write, iclass 3, count 0 2006.182.08:26:58.18#ibcon#enter sib2, iclass 3, count 0 2006.182.08:26:58.18#ibcon#flushed, iclass 3, count 0 2006.182.08:26:58.18#ibcon#about to write, iclass 3, count 0 2006.182.08:26:58.18#ibcon#wrote, iclass 3, count 0 2006.182.08:26:58.18#ibcon#about to read 3, iclass 3, count 0 2006.182.08:26:58.21#ibcon#read 3, iclass 3, count 0 2006.182.08:26:58.21#ibcon#about to read 4, iclass 3, count 0 2006.182.08:26:58.21#ibcon#read 4, iclass 3, count 0 2006.182.08:26:58.21#ibcon#about to read 5, iclass 3, count 0 2006.182.08:26:58.21#ibcon#read 5, iclass 3, count 0 2006.182.08:26:58.21#ibcon#about to read 6, iclass 3, count 0 2006.182.08:26:58.21#ibcon#read 6, iclass 3, count 0 2006.182.08:26:58.21#ibcon#end of sib2, iclass 3, count 0 2006.182.08:26:58.21#ibcon#*after write, iclass 3, count 0 2006.182.08:26:58.21#ibcon#*before return 0, iclass 3, count 0 2006.182.08:26:58.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:26:58.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:26:58.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:26:58.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:26:58.21$vc4f8/valo=2,572.99 2006.182.08:26:58.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.08:26:58.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.08:26:58.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:26:58.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:26:58.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:26:58.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:26:58.21#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:26:58.21#ibcon#first serial, iclass 5, count 0 2006.182.08:26:58.21#ibcon#enter sib2, iclass 5, count 0 2006.182.08:26:58.21#ibcon#flushed, iclass 5, count 0 2006.182.08:26:58.21#ibcon#about to write, iclass 5, count 0 2006.182.08:26:58.21#ibcon#wrote, iclass 5, count 0 2006.182.08:26:58.21#ibcon#about to read 3, iclass 5, count 0 2006.182.08:26:58.23#ibcon#read 3, iclass 5, count 0 2006.182.08:26:58.23#ibcon#about to read 4, iclass 5, count 0 2006.182.08:26:58.23#ibcon#read 4, iclass 5, count 0 2006.182.08:26:58.23#ibcon#about to read 5, iclass 5, count 0 2006.182.08:26:58.23#ibcon#read 5, iclass 5, count 0 2006.182.08:26:58.23#ibcon#about to read 6, iclass 5, count 0 2006.182.08:26:58.23#ibcon#read 6, iclass 5, count 0 2006.182.08:26:58.23#ibcon#end of sib2, iclass 5, count 0 2006.182.08:26:58.23#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:26:58.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:26:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:26:58.23#ibcon#*before write, iclass 5, count 0 2006.182.08:26:58.23#ibcon#enter sib2, iclass 5, count 0 2006.182.08:26:58.23#ibcon#flushed, iclass 5, count 0 2006.182.08:26:58.23#ibcon#about to write, iclass 5, count 0 2006.182.08:26:58.23#ibcon#wrote, iclass 5, count 0 2006.182.08:26:58.23#ibcon#about to read 3, iclass 5, count 0 2006.182.08:26:58.27#ibcon#read 3, iclass 5, count 0 2006.182.08:26:58.27#ibcon#about to read 4, iclass 5, count 0 2006.182.08:26:58.27#ibcon#read 4, iclass 5, count 0 2006.182.08:26:58.27#ibcon#about to read 5, iclass 5, count 0 2006.182.08:26:58.27#ibcon#read 5, iclass 5, count 0 2006.182.08:26:58.27#ibcon#about to read 6, iclass 5, count 0 2006.182.08:26:58.27#ibcon#read 6, iclass 5, count 0 2006.182.08:26:58.27#ibcon#end of sib2, iclass 5, count 0 2006.182.08:26:58.27#ibcon#*after write, iclass 5, count 0 2006.182.08:26:58.27#ibcon#*before return 0, iclass 5, count 0 2006.182.08:26:58.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:26:58.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:26:58.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:26:58.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:26:58.27$vc4f8/va=2,7 2006.182.08:26:58.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.08:26:58.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.08:26:58.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:26:58.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:26:58.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:26:58.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:26:58.33#ibcon#enter wrdev, iclass 7, count 2 2006.182.08:26:58.33#ibcon#first serial, iclass 7, count 2 2006.182.08:26:58.33#ibcon#enter sib2, iclass 7, count 2 2006.182.08:26:58.33#ibcon#flushed, iclass 7, count 2 2006.182.08:26:58.33#ibcon#about to write, iclass 7, count 2 2006.182.08:26:58.33#ibcon#wrote, iclass 7, count 2 2006.182.08:26:58.33#ibcon#about to read 3, iclass 7, count 2 2006.182.08:26:58.35#ibcon#read 3, iclass 7, count 2 2006.182.08:26:58.35#ibcon#about to read 4, iclass 7, count 2 2006.182.08:26:58.35#ibcon#read 4, iclass 7, count 2 2006.182.08:26:58.35#ibcon#about to read 5, iclass 7, count 2 2006.182.08:26:58.35#ibcon#read 5, iclass 7, count 2 2006.182.08:26:58.35#ibcon#about to read 6, iclass 7, count 2 2006.182.08:26:58.35#ibcon#read 6, iclass 7, count 2 2006.182.08:26:58.35#ibcon#end of sib2, iclass 7, count 2 2006.182.08:26:58.35#ibcon#*mode == 0, iclass 7, count 2 2006.182.08:26:58.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.08:26:58.35#ibcon#[25=AT02-07\r\n] 2006.182.08:26:58.35#ibcon#*before write, iclass 7, count 2 2006.182.08:26:58.35#ibcon#enter sib2, iclass 7, count 2 2006.182.08:26:58.35#ibcon#flushed, iclass 7, count 2 2006.182.08:26:58.35#ibcon#about to write, iclass 7, count 2 2006.182.08:26:58.35#ibcon#wrote, iclass 7, count 2 2006.182.08:26:58.35#ibcon#about to read 3, iclass 7, count 2 2006.182.08:26:58.38#ibcon#read 3, iclass 7, count 2 2006.182.08:26:58.38#ibcon#about to read 4, iclass 7, count 2 2006.182.08:26:58.38#ibcon#read 4, iclass 7, count 2 2006.182.08:26:58.38#ibcon#about to read 5, iclass 7, count 2 2006.182.08:26:58.38#ibcon#read 5, iclass 7, count 2 2006.182.08:26:58.38#ibcon#about to read 6, iclass 7, count 2 2006.182.08:26:58.38#ibcon#read 6, iclass 7, count 2 2006.182.08:26:58.38#ibcon#end of sib2, iclass 7, count 2 2006.182.08:26:58.38#ibcon#*after write, iclass 7, count 2 2006.182.08:26:58.38#ibcon#*before return 0, iclass 7, count 2 2006.182.08:26:58.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:26:58.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:26:58.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.08:26:58.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:26:58.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:26:58.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:26:58.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:26:58.50#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:26:58.50#ibcon#first serial, iclass 7, count 0 2006.182.08:26:58.50#ibcon#enter sib2, iclass 7, count 0 2006.182.08:26:58.50#ibcon#flushed, iclass 7, count 0 2006.182.08:26:58.50#ibcon#about to write, iclass 7, count 0 2006.182.08:26:58.50#ibcon#wrote, iclass 7, count 0 2006.182.08:26:58.50#ibcon#about to read 3, iclass 7, count 0 2006.182.08:26:58.52#ibcon#read 3, iclass 7, count 0 2006.182.08:26:58.52#ibcon#about to read 4, iclass 7, count 0 2006.182.08:26:58.52#ibcon#read 4, iclass 7, count 0 2006.182.08:26:58.52#ibcon#about to read 5, iclass 7, count 0 2006.182.08:26:58.52#ibcon#read 5, iclass 7, count 0 2006.182.08:26:58.52#ibcon#about to read 6, iclass 7, count 0 2006.182.08:26:58.52#ibcon#read 6, iclass 7, count 0 2006.182.08:26:58.52#ibcon#end of sib2, iclass 7, count 0 2006.182.08:26:58.52#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:26:58.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:26:58.52#ibcon#[25=USB\r\n] 2006.182.08:26:58.52#ibcon#*before write, iclass 7, count 0 2006.182.08:26:58.52#ibcon#enter sib2, iclass 7, count 0 2006.182.08:26:58.52#ibcon#flushed, iclass 7, count 0 2006.182.08:26:58.52#ibcon#about to write, iclass 7, count 0 2006.182.08:26:58.52#ibcon#wrote, iclass 7, count 0 2006.182.08:26:58.52#ibcon#about to read 3, iclass 7, count 0 2006.182.08:26:58.55#ibcon#read 3, iclass 7, count 0 2006.182.08:26:58.55#ibcon#about to read 4, iclass 7, count 0 2006.182.08:26:58.55#ibcon#read 4, iclass 7, count 0 2006.182.08:26:58.55#ibcon#about to read 5, iclass 7, count 0 2006.182.08:26:58.55#ibcon#read 5, iclass 7, count 0 2006.182.08:26:58.55#ibcon#about to read 6, iclass 7, count 0 2006.182.08:26:58.55#ibcon#read 6, iclass 7, count 0 2006.182.08:26:58.55#ibcon#end of sib2, iclass 7, count 0 2006.182.08:26:58.55#ibcon#*after write, iclass 7, count 0 2006.182.08:26:58.55#ibcon#*before return 0, iclass 7, count 0 2006.182.08:26:58.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:26:58.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:26:58.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:26:58.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:26:58.55$vc4f8/valo=3,672.99 2006.182.08:26:58.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.08:26:58.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.08:26:58.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:26:58.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:26:58.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:26:58.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:26:58.55#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:26:58.55#ibcon#first serial, iclass 11, count 0 2006.182.08:26:58.55#ibcon#enter sib2, iclass 11, count 0 2006.182.08:26:58.55#ibcon#flushed, iclass 11, count 0 2006.182.08:26:58.55#ibcon#about to write, iclass 11, count 0 2006.182.08:26:58.55#ibcon#wrote, iclass 11, count 0 2006.182.08:26:58.55#ibcon#about to read 3, iclass 11, count 0 2006.182.08:26:58.57#ibcon#read 3, iclass 11, count 0 2006.182.08:26:58.57#ibcon#about to read 4, iclass 11, count 0 2006.182.08:26:58.57#ibcon#read 4, iclass 11, count 0 2006.182.08:26:58.57#ibcon#about to read 5, iclass 11, count 0 2006.182.08:26:58.57#ibcon#read 5, iclass 11, count 0 2006.182.08:26:58.57#ibcon#about to read 6, iclass 11, count 0 2006.182.08:26:58.57#ibcon#read 6, iclass 11, count 0 2006.182.08:26:58.57#ibcon#end of sib2, iclass 11, count 0 2006.182.08:26:58.57#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:26:58.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:26:58.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:26:58.57#ibcon#*before write, iclass 11, count 0 2006.182.08:26:58.57#ibcon#enter sib2, iclass 11, count 0 2006.182.08:26:58.57#ibcon#flushed, iclass 11, count 0 2006.182.08:26:58.57#ibcon#about to write, iclass 11, count 0 2006.182.08:26:58.57#ibcon#wrote, iclass 11, count 0 2006.182.08:26:58.57#ibcon#about to read 3, iclass 11, count 0 2006.182.08:26:58.62#ibcon#read 3, iclass 11, count 0 2006.182.08:26:58.62#ibcon#about to read 4, iclass 11, count 0 2006.182.08:26:58.62#ibcon#read 4, iclass 11, count 0 2006.182.08:26:58.62#ibcon#about to read 5, iclass 11, count 0 2006.182.08:26:58.62#ibcon#read 5, iclass 11, count 0 2006.182.08:26:58.62#ibcon#about to read 6, iclass 11, count 0 2006.182.08:26:58.62#ibcon#read 6, iclass 11, count 0 2006.182.08:26:58.62#ibcon#end of sib2, iclass 11, count 0 2006.182.08:26:58.62#ibcon#*after write, iclass 11, count 0 2006.182.08:26:58.62#ibcon#*before return 0, iclass 11, count 0 2006.182.08:26:58.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:26:58.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:26:58.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:26:58.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:26:58.62$vc4f8/va=3,6 2006.182.08:26:58.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.08:26:58.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.08:26:58.62#ibcon#ireg 11 cls_cnt 2 2006.182.08:26:58.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:26:58.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:26:58.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:26:58.67#ibcon#enter wrdev, iclass 13, count 2 2006.182.08:26:58.67#ibcon#first serial, iclass 13, count 2 2006.182.08:26:58.67#ibcon#enter sib2, iclass 13, count 2 2006.182.08:26:58.67#ibcon#flushed, iclass 13, count 2 2006.182.08:26:58.67#ibcon#about to write, iclass 13, count 2 2006.182.08:26:58.67#ibcon#wrote, iclass 13, count 2 2006.182.08:26:58.67#ibcon#about to read 3, iclass 13, count 2 2006.182.08:26:58.69#ibcon#read 3, iclass 13, count 2 2006.182.08:26:58.69#ibcon#about to read 4, iclass 13, count 2 2006.182.08:26:58.69#ibcon#read 4, iclass 13, count 2 2006.182.08:26:58.69#ibcon#about to read 5, iclass 13, count 2 2006.182.08:26:58.69#ibcon#read 5, iclass 13, count 2 2006.182.08:26:58.69#ibcon#about to read 6, iclass 13, count 2 2006.182.08:26:58.69#ibcon#read 6, iclass 13, count 2 2006.182.08:26:58.69#ibcon#end of sib2, iclass 13, count 2 2006.182.08:26:58.69#ibcon#*mode == 0, iclass 13, count 2 2006.182.08:26:58.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.08:26:58.69#ibcon#[25=AT03-06\r\n] 2006.182.08:26:58.69#ibcon#*before write, iclass 13, count 2 2006.182.08:26:58.69#ibcon#enter sib2, iclass 13, count 2 2006.182.08:26:58.69#ibcon#flushed, iclass 13, count 2 2006.182.08:26:58.69#ibcon#about to write, iclass 13, count 2 2006.182.08:26:58.69#ibcon#wrote, iclass 13, count 2 2006.182.08:26:58.69#ibcon#about to read 3, iclass 13, count 2 2006.182.08:26:58.72#ibcon#read 3, iclass 13, count 2 2006.182.08:26:58.72#ibcon#about to read 4, iclass 13, count 2 2006.182.08:26:58.72#ibcon#read 4, iclass 13, count 2 2006.182.08:26:58.72#ibcon#about to read 5, iclass 13, count 2 2006.182.08:26:58.72#ibcon#read 5, iclass 13, count 2 2006.182.08:26:58.72#ibcon#about to read 6, iclass 13, count 2 2006.182.08:26:58.72#ibcon#read 6, iclass 13, count 2 2006.182.08:26:58.72#ibcon#end of sib2, iclass 13, count 2 2006.182.08:26:58.72#ibcon#*after write, iclass 13, count 2 2006.182.08:26:58.72#ibcon#*before return 0, iclass 13, count 2 2006.182.08:26:58.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:26:58.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:26:58.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.08:26:58.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:26:58.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:26:58.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:26:58.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:26:58.84#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:26:58.84#ibcon#first serial, iclass 13, count 0 2006.182.08:26:58.84#ibcon#enter sib2, iclass 13, count 0 2006.182.08:26:58.84#ibcon#flushed, iclass 13, count 0 2006.182.08:26:58.84#ibcon#about to write, iclass 13, count 0 2006.182.08:26:58.84#ibcon#wrote, iclass 13, count 0 2006.182.08:26:58.84#ibcon#about to read 3, iclass 13, count 0 2006.182.08:26:58.86#ibcon#read 3, iclass 13, count 0 2006.182.08:26:58.86#ibcon#about to read 4, iclass 13, count 0 2006.182.08:26:58.86#ibcon#read 4, iclass 13, count 0 2006.182.08:26:58.86#ibcon#about to read 5, iclass 13, count 0 2006.182.08:26:58.86#ibcon#read 5, iclass 13, count 0 2006.182.08:26:58.86#ibcon#about to read 6, iclass 13, count 0 2006.182.08:26:58.86#ibcon#read 6, iclass 13, count 0 2006.182.08:26:58.86#ibcon#end of sib2, iclass 13, count 0 2006.182.08:26:58.86#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:26:58.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:26:58.86#ibcon#[25=USB\r\n] 2006.182.08:26:58.86#ibcon#*before write, iclass 13, count 0 2006.182.08:26:58.86#ibcon#enter sib2, iclass 13, count 0 2006.182.08:26:58.86#ibcon#flushed, iclass 13, count 0 2006.182.08:26:58.86#ibcon#about to write, iclass 13, count 0 2006.182.08:26:58.86#ibcon#wrote, iclass 13, count 0 2006.182.08:26:58.86#ibcon#about to read 3, iclass 13, count 0 2006.182.08:26:58.89#ibcon#read 3, iclass 13, count 0 2006.182.08:26:58.89#ibcon#about to read 4, iclass 13, count 0 2006.182.08:26:58.89#ibcon#read 4, iclass 13, count 0 2006.182.08:26:58.89#ibcon#about to read 5, iclass 13, count 0 2006.182.08:26:58.89#ibcon#read 5, iclass 13, count 0 2006.182.08:26:58.89#ibcon#about to read 6, iclass 13, count 0 2006.182.08:26:58.89#ibcon#read 6, iclass 13, count 0 2006.182.08:26:58.89#ibcon#end of sib2, iclass 13, count 0 2006.182.08:26:58.89#ibcon#*after write, iclass 13, count 0 2006.182.08:26:58.89#ibcon#*before return 0, iclass 13, count 0 2006.182.08:26:58.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:26:58.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:26:58.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:26:58.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:26:58.89$vc4f8/valo=4,832.99 2006.182.08:26:58.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.08:26:58.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.08:26:58.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:26:58.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:26:58.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:26:58.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:26:58.89#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:26:58.89#ibcon#first serial, iclass 15, count 0 2006.182.08:26:58.89#ibcon#enter sib2, iclass 15, count 0 2006.182.08:26:58.89#ibcon#flushed, iclass 15, count 0 2006.182.08:26:58.89#ibcon#about to write, iclass 15, count 0 2006.182.08:26:58.89#ibcon#wrote, iclass 15, count 0 2006.182.08:26:58.89#ibcon#about to read 3, iclass 15, count 0 2006.182.08:26:58.91#ibcon#read 3, iclass 15, count 0 2006.182.08:26:58.91#ibcon#about to read 4, iclass 15, count 0 2006.182.08:26:58.91#ibcon#read 4, iclass 15, count 0 2006.182.08:26:58.91#ibcon#about to read 5, iclass 15, count 0 2006.182.08:26:58.91#ibcon#read 5, iclass 15, count 0 2006.182.08:26:58.91#ibcon#about to read 6, iclass 15, count 0 2006.182.08:26:58.91#ibcon#read 6, iclass 15, count 0 2006.182.08:26:58.91#ibcon#end of sib2, iclass 15, count 0 2006.182.08:26:58.91#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:26:58.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:26:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:26:58.91#ibcon#*before write, iclass 15, count 0 2006.182.08:26:58.91#ibcon#enter sib2, iclass 15, count 0 2006.182.08:26:58.91#ibcon#flushed, iclass 15, count 0 2006.182.08:26:58.91#ibcon#about to write, iclass 15, count 0 2006.182.08:26:58.91#ibcon#wrote, iclass 15, count 0 2006.182.08:26:58.91#ibcon#about to read 3, iclass 15, count 0 2006.182.08:26:58.95#ibcon#read 3, iclass 15, count 0 2006.182.08:26:58.95#ibcon#about to read 4, iclass 15, count 0 2006.182.08:26:58.95#ibcon#read 4, iclass 15, count 0 2006.182.08:26:58.95#ibcon#about to read 5, iclass 15, count 0 2006.182.08:26:58.95#ibcon#read 5, iclass 15, count 0 2006.182.08:26:58.95#ibcon#about to read 6, iclass 15, count 0 2006.182.08:26:58.95#ibcon#read 6, iclass 15, count 0 2006.182.08:26:58.95#ibcon#end of sib2, iclass 15, count 0 2006.182.08:26:58.95#ibcon#*after write, iclass 15, count 0 2006.182.08:26:58.95#ibcon#*before return 0, iclass 15, count 0 2006.182.08:26:58.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:26:58.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:26:58.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:26:58.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:26:58.95$vc4f8/va=4,7 2006.182.08:26:58.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.08:26:58.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.08:26:58.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:26:58.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:26:59.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:26:59.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:26:59.01#ibcon#enter wrdev, iclass 17, count 2 2006.182.08:26:59.01#ibcon#first serial, iclass 17, count 2 2006.182.08:26:59.01#ibcon#enter sib2, iclass 17, count 2 2006.182.08:26:59.01#ibcon#flushed, iclass 17, count 2 2006.182.08:26:59.01#ibcon#about to write, iclass 17, count 2 2006.182.08:26:59.01#ibcon#wrote, iclass 17, count 2 2006.182.08:26:59.01#ibcon#about to read 3, iclass 17, count 2 2006.182.08:26:59.03#ibcon#read 3, iclass 17, count 2 2006.182.08:26:59.03#ibcon#about to read 4, iclass 17, count 2 2006.182.08:26:59.03#ibcon#read 4, iclass 17, count 2 2006.182.08:26:59.03#ibcon#about to read 5, iclass 17, count 2 2006.182.08:26:59.03#ibcon#read 5, iclass 17, count 2 2006.182.08:26:59.03#ibcon#about to read 6, iclass 17, count 2 2006.182.08:26:59.03#ibcon#read 6, iclass 17, count 2 2006.182.08:26:59.03#ibcon#end of sib2, iclass 17, count 2 2006.182.08:26:59.03#ibcon#*mode == 0, iclass 17, count 2 2006.182.08:26:59.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.08:26:59.03#ibcon#[25=AT04-07\r\n] 2006.182.08:26:59.03#ibcon#*before write, iclass 17, count 2 2006.182.08:26:59.03#ibcon#enter sib2, iclass 17, count 2 2006.182.08:26:59.03#ibcon#flushed, iclass 17, count 2 2006.182.08:26:59.03#ibcon#about to write, iclass 17, count 2 2006.182.08:26:59.03#ibcon#wrote, iclass 17, count 2 2006.182.08:26:59.03#ibcon#about to read 3, iclass 17, count 2 2006.182.08:26:59.06#ibcon#read 3, iclass 17, count 2 2006.182.08:26:59.06#ibcon#about to read 4, iclass 17, count 2 2006.182.08:26:59.06#ibcon#read 4, iclass 17, count 2 2006.182.08:26:59.06#ibcon#about to read 5, iclass 17, count 2 2006.182.08:26:59.06#ibcon#read 5, iclass 17, count 2 2006.182.08:26:59.06#ibcon#about to read 6, iclass 17, count 2 2006.182.08:26:59.06#ibcon#read 6, iclass 17, count 2 2006.182.08:26:59.06#ibcon#end of sib2, iclass 17, count 2 2006.182.08:26:59.06#ibcon#*after write, iclass 17, count 2 2006.182.08:26:59.06#ibcon#*before return 0, iclass 17, count 2 2006.182.08:26:59.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:26:59.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:26:59.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.08:26:59.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:26:59.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:26:59.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:26:59.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:26:59.18#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:26:59.18#ibcon#first serial, iclass 17, count 0 2006.182.08:26:59.18#ibcon#enter sib2, iclass 17, count 0 2006.182.08:26:59.18#ibcon#flushed, iclass 17, count 0 2006.182.08:26:59.18#ibcon#about to write, iclass 17, count 0 2006.182.08:26:59.18#ibcon#wrote, iclass 17, count 0 2006.182.08:26:59.18#ibcon#about to read 3, iclass 17, count 0 2006.182.08:26:59.20#ibcon#read 3, iclass 17, count 0 2006.182.08:26:59.20#ibcon#about to read 4, iclass 17, count 0 2006.182.08:26:59.20#ibcon#read 4, iclass 17, count 0 2006.182.08:26:59.20#ibcon#about to read 5, iclass 17, count 0 2006.182.08:26:59.20#ibcon#read 5, iclass 17, count 0 2006.182.08:26:59.20#ibcon#about to read 6, iclass 17, count 0 2006.182.08:26:59.20#ibcon#read 6, iclass 17, count 0 2006.182.08:26:59.20#ibcon#end of sib2, iclass 17, count 0 2006.182.08:26:59.20#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:26:59.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:26:59.20#ibcon#[25=USB\r\n] 2006.182.08:26:59.20#ibcon#*before write, iclass 17, count 0 2006.182.08:26:59.20#ibcon#enter sib2, iclass 17, count 0 2006.182.08:26:59.20#ibcon#flushed, iclass 17, count 0 2006.182.08:26:59.20#ibcon#about to write, iclass 17, count 0 2006.182.08:26:59.20#ibcon#wrote, iclass 17, count 0 2006.182.08:26:59.20#ibcon#about to read 3, iclass 17, count 0 2006.182.08:26:59.23#ibcon#read 3, iclass 17, count 0 2006.182.08:26:59.23#ibcon#about to read 4, iclass 17, count 0 2006.182.08:26:59.23#ibcon#read 4, iclass 17, count 0 2006.182.08:26:59.23#ibcon#about to read 5, iclass 17, count 0 2006.182.08:26:59.23#ibcon#read 5, iclass 17, count 0 2006.182.08:26:59.23#ibcon#about to read 6, iclass 17, count 0 2006.182.08:26:59.23#ibcon#read 6, iclass 17, count 0 2006.182.08:26:59.23#ibcon#end of sib2, iclass 17, count 0 2006.182.08:26:59.23#ibcon#*after write, iclass 17, count 0 2006.182.08:26:59.23#ibcon#*before return 0, iclass 17, count 0 2006.182.08:26:59.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:26:59.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:26:59.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:26:59.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:26:59.23$vc4f8/valo=5,652.99 2006.182.08:26:59.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.08:26:59.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.08:26:59.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:26:59.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:26:59.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:26:59.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:26:59.23#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:26:59.23#ibcon#first serial, iclass 19, count 0 2006.182.08:26:59.23#ibcon#enter sib2, iclass 19, count 0 2006.182.08:26:59.23#ibcon#flushed, iclass 19, count 0 2006.182.08:26:59.23#ibcon#about to write, iclass 19, count 0 2006.182.08:26:59.23#ibcon#wrote, iclass 19, count 0 2006.182.08:26:59.23#ibcon#about to read 3, iclass 19, count 0 2006.182.08:26:59.25#ibcon#read 3, iclass 19, count 0 2006.182.08:26:59.25#ibcon#about to read 4, iclass 19, count 0 2006.182.08:26:59.25#ibcon#read 4, iclass 19, count 0 2006.182.08:26:59.25#ibcon#about to read 5, iclass 19, count 0 2006.182.08:26:59.25#ibcon#read 5, iclass 19, count 0 2006.182.08:26:59.25#ibcon#about to read 6, iclass 19, count 0 2006.182.08:26:59.25#ibcon#read 6, iclass 19, count 0 2006.182.08:26:59.25#ibcon#end of sib2, iclass 19, count 0 2006.182.08:26:59.25#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:26:59.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:26:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:26:59.25#ibcon#*before write, iclass 19, count 0 2006.182.08:26:59.25#ibcon#enter sib2, iclass 19, count 0 2006.182.08:26:59.25#ibcon#flushed, iclass 19, count 0 2006.182.08:26:59.25#ibcon#about to write, iclass 19, count 0 2006.182.08:26:59.25#ibcon#wrote, iclass 19, count 0 2006.182.08:26:59.25#ibcon#about to read 3, iclass 19, count 0 2006.182.08:26:59.29#ibcon#read 3, iclass 19, count 0 2006.182.08:26:59.29#ibcon#about to read 4, iclass 19, count 0 2006.182.08:26:59.29#ibcon#read 4, iclass 19, count 0 2006.182.08:26:59.29#ibcon#about to read 5, iclass 19, count 0 2006.182.08:26:59.29#ibcon#read 5, iclass 19, count 0 2006.182.08:26:59.29#ibcon#about to read 6, iclass 19, count 0 2006.182.08:26:59.29#ibcon#read 6, iclass 19, count 0 2006.182.08:26:59.29#ibcon#end of sib2, iclass 19, count 0 2006.182.08:26:59.29#ibcon#*after write, iclass 19, count 0 2006.182.08:26:59.29#ibcon#*before return 0, iclass 19, count 0 2006.182.08:26:59.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:26:59.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:26:59.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:26:59.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:26:59.29$vc4f8/va=5,7 2006.182.08:26:59.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.08:26:59.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.08:26:59.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:26:59.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:26:59.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:26:59.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:26:59.35#ibcon#enter wrdev, iclass 21, count 2 2006.182.08:26:59.35#ibcon#first serial, iclass 21, count 2 2006.182.08:26:59.35#ibcon#enter sib2, iclass 21, count 2 2006.182.08:26:59.35#ibcon#flushed, iclass 21, count 2 2006.182.08:26:59.35#ibcon#about to write, iclass 21, count 2 2006.182.08:26:59.35#ibcon#wrote, iclass 21, count 2 2006.182.08:26:59.35#ibcon#about to read 3, iclass 21, count 2 2006.182.08:26:59.37#ibcon#read 3, iclass 21, count 2 2006.182.08:26:59.37#ibcon#about to read 4, iclass 21, count 2 2006.182.08:26:59.37#ibcon#read 4, iclass 21, count 2 2006.182.08:26:59.37#ibcon#about to read 5, iclass 21, count 2 2006.182.08:26:59.37#ibcon#read 5, iclass 21, count 2 2006.182.08:26:59.37#ibcon#about to read 6, iclass 21, count 2 2006.182.08:26:59.37#ibcon#read 6, iclass 21, count 2 2006.182.08:26:59.37#ibcon#end of sib2, iclass 21, count 2 2006.182.08:26:59.37#ibcon#*mode == 0, iclass 21, count 2 2006.182.08:26:59.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.08:26:59.37#ibcon#[25=AT05-07\r\n] 2006.182.08:26:59.37#ibcon#*before write, iclass 21, count 2 2006.182.08:26:59.37#ibcon#enter sib2, iclass 21, count 2 2006.182.08:26:59.37#ibcon#flushed, iclass 21, count 2 2006.182.08:26:59.37#ibcon#about to write, iclass 21, count 2 2006.182.08:26:59.37#ibcon#wrote, iclass 21, count 2 2006.182.08:26:59.37#ibcon#about to read 3, iclass 21, count 2 2006.182.08:26:59.40#ibcon#read 3, iclass 21, count 2 2006.182.08:26:59.40#ibcon#about to read 4, iclass 21, count 2 2006.182.08:26:59.40#ibcon#read 4, iclass 21, count 2 2006.182.08:26:59.40#ibcon#about to read 5, iclass 21, count 2 2006.182.08:26:59.40#ibcon#read 5, iclass 21, count 2 2006.182.08:26:59.40#ibcon#about to read 6, iclass 21, count 2 2006.182.08:26:59.40#ibcon#read 6, iclass 21, count 2 2006.182.08:26:59.40#ibcon#end of sib2, iclass 21, count 2 2006.182.08:26:59.40#ibcon#*after write, iclass 21, count 2 2006.182.08:26:59.40#ibcon#*before return 0, iclass 21, count 2 2006.182.08:26:59.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:26:59.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:26:59.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.08:26:59.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:26:59.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:26:59.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:26:59.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:26:59.52#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:26:59.52#ibcon#first serial, iclass 21, count 0 2006.182.08:26:59.52#ibcon#enter sib2, iclass 21, count 0 2006.182.08:26:59.52#ibcon#flushed, iclass 21, count 0 2006.182.08:26:59.52#ibcon#about to write, iclass 21, count 0 2006.182.08:26:59.52#ibcon#wrote, iclass 21, count 0 2006.182.08:26:59.52#ibcon#about to read 3, iclass 21, count 0 2006.182.08:26:59.54#ibcon#read 3, iclass 21, count 0 2006.182.08:26:59.54#ibcon#about to read 4, iclass 21, count 0 2006.182.08:26:59.54#ibcon#read 4, iclass 21, count 0 2006.182.08:26:59.54#ibcon#about to read 5, iclass 21, count 0 2006.182.08:26:59.54#ibcon#read 5, iclass 21, count 0 2006.182.08:26:59.54#ibcon#about to read 6, iclass 21, count 0 2006.182.08:26:59.54#ibcon#read 6, iclass 21, count 0 2006.182.08:26:59.54#ibcon#end of sib2, iclass 21, count 0 2006.182.08:26:59.54#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:26:59.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:26:59.54#ibcon#[25=USB\r\n] 2006.182.08:26:59.54#ibcon#*before write, iclass 21, count 0 2006.182.08:26:59.54#ibcon#enter sib2, iclass 21, count 0 2006.182.08:26:59.54#ibcon#flushed, iclass 21, count 0 2006.182.08:26:59.54#ibcon#about to write, iclass 21, count 0 2006.182.08:26:59.54#ibcon#wrote, iclass 21, count 0 2006.182.08:26:59.54#ibcon#about to read 3, iclass 21, count 0 2006.182.08:26:59.57#ibcon#read 3, iclass 21, count 0 2006.182.08:26:59.57#ibcon#about to read 4, iclass 21, count 0 2006.182.08:26:59.57#ibcon#read 4, iclass 21, count 0 2006.182.08:26:59.57#ibcon#about to read 5, iclass 21, count 0 2006.182.08:26:59.57#ibcon#read 5, iclass 21, count 0 2006.182.08:26:59.57#ibcon#about to read 6, iclass 21, count 0 2006.182.08:26:59.57#ibcon#read 6, iclass 21, count 0 2006.182.08:26:59.57#ibcon#end of sib2, iclass 21, count 0 2006.182.08:26:59.57#ibcon#*after write, iclass 21, count 0 2006.182.08:26:59.57#ibcon#*before return 0, iclass 21, count 0 2006.182.08:26:59.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:26:59.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:26:59.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:26:59.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:26:59.57$vc4f8/valo=6,772.99 2006.182.08:26:59.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.08:26:59.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.08:26:59.57#ibcon#ireg 17 cls_cnt 0 2006.182.08:26:59.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:26:59.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:26:59.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:26:59.57#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:26:59.57#ibcon#first serial, iclass 23, count 0 2006.182.08:26:59.57#ibcon#enter sib2, iclass 23, count 0 2006.182.08:26:59.57#ibcon#flushed, iclass 23, count 0 2006.182.08:26:59.57#ibcon#about to write, iclass 23, count 0 2006.182.08:26:59.57#ibcon#wrote, iclass 23, count 0 2006.182.08:26:59.57#ibcon#about to read 3, iclass 23, count 0 2006.182.08:26:59.59#ibcon#read 3, iclass 23, count 0 2006.182.08:26:59.59#ibcon#about to read 4, iclass 23, count 0 2006.182.08:26:59.59#ibcon#read 4, iclass 23, count 0 2006.182.08:26:59.59#ibcon#about to read 5, iclass 23, count 0 2006.182.08:26:59.59#ibcon#read 5, iclass 23, count 0 2006.182.08:26:59.59#ibcon#about to read 6, iclass 23, count 0 2006.182.08:26:59.59#ibcon#read 6, iclass 23, count 0 2006.182.08:26:59.59#ibcon#end of sib2, iclass 23, count 0 2006.182.08:26:59.59#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:26:59.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:26:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:26:59.59#ibcon#*before write, iclass 23, count 0 2006.182.08:26:59.59#ibcon#enter sib2, iclass 23, count 0 2006.182.08:26:59.59#ibcon#flushed, iclass 23, count 0 2006.182.08:26:59.59#ibcon#about to write, iclass 23, count 0 2006.182.08:26:59.59#ibcon#wrote, iclass 23, count 0 2006.182.08:26:59.59#ibcon#about to read 3, iclass 23, count 0 2006.182.08:26:59.64#ibcon#read 3, iclass 23, count 0 2006.182.08:26:59.64#ibcon#about to read 4, iclass 23, count 0 2006.182.08:26:59.64#ibcon#read 4, iclass 23, count 0 2006.182.08:26:59.64#ibcon#about to read 5, iclass 23, count 0 2006.182.08:26:59.64#ibcon#read 5, iclass 23, count 0 2006.182.08:26:59.64#ibcon#about to read 6, iclass 23, count 0 2006.182.08:26:59.64#ibcon#read 6, iclass 23, count 0 2006.182.08:26:59.64#ibcon#end of sib2, iclass 23, count 0 2006.182.08:26:59.64#ibcon#*after write, iclass 23, count 0 2006.182.08:26:59.64#ibcon#*before return 0, iclass 23, count 0 2006.182.08:26:59.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:26:59.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:26:59.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:26:59.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:26:59.64$vc4f8/va=6,6 2006.182.08:26:59.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.08:26:59.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.08:26:59.64#ibcon#ireg 11 cls_cnt 2 2006.182.08:26:59.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:26:59.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:26:59.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:26:59.69#ibcon#enter wrdev, iclass 25, count 2 2006.182.08:26:59.69#ibcon#first serial, iclass 25, count 2 2006.182.08:26:59.69#ibcon#enter sib2, iclass 25, count 2 2006.182.08:26:59.69#ibcon#flushed, iclass 25, count 2 2006.182.08:26:59.69#ibcon#about to write, iclass 25, count 2 2006.182.08:26:59.69#ibcon#wrote, iclass 25, count 2 2006.182.08:26:59.69#ibcon#about to read 3, iclass 25, count 2 2006.182.08:26:59.71#ibcon#read 3, iclass 25, count 2 2006.182.08:26:59.71#ibcon#about to read 4, iclass 25, count 2 2006.182.08:26:59.71#ibcon#read 4, iclass 25, count 2 2006.182.08:26:59.71#ibcon#about to read 5, iclass 25, count 2 2006.182.08:26:59.71#ibcon#read 5, iclass 25, count 2 2006.182.08:26:59.71#ibcon#about to read 6, iclass 25, count 2 2006.182.08:26:59.71#ibcon#read 6, iclass 25, count 2 2006.182.08:26:59.71#ibcon#end of sib2, iclass 25, count 2 2006.182.08:26:59.71#ibcon#*mode == 0, iclass 25, count 2 2006.182.08:26:59.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.08:26:59.71#ibcon#[25=AT06-06\r\n] 2006.182.08:26:59.71#ibcon#*before write, iclass 25, count 2 2006.182.08:26:59.71#ibcon#enter sib2, iclass 25, count 2 2006.182.08:26:59.71#ibcon#flushed, iclass 25, count 2 2006.182.08:26:59.71#ibcon#about to write, iclass 25, count 2 2006.182.08:26:59.71#ibcon#wrote, iclass 25, count 2 2006.182.08:26:59.71#ibcon#about to read 3, iclass 25, count 2 2006.182.08:26:59.74#ibcon#read 3, iclass 25, count 2 2006.182.08:26:59.74#ibcon#about to read 4, iclass 25, count 2 2006.182.08:26:59.74#ibcon#read 4, iclass 25, count 2 2006.182.08:26:59.74#ibcon#about to read 5, iclass 25, count 2 2006.182.08:26:59.74#ibcon#read 5, iclass 25, count 2 2006.182.08:26:59.74#ibcon#about to read 6, iclass 25, count 2 2006.182.08:26:59.74#ibcon#read 6, iclass 25, count 2 2006.182.08:26:59.74#ibcon#end of sib2, iclass 25, count 2 2006.182.08:26:59.74#ibcon#*after write, iclass 25, count 2 2006.182.08:26:59.74#ibcon#*before return 0, iclass 25, count 2 2006.182.08:26:59.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:26:59.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:26:59.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.08:26:59.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:26:59.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:26:59.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:26:59.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:26:59.86#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:26:59.86#ibcon#first serial, iclass 25, count 0 2006.182.08:26:59.86#ibcon#enter sib2, iclass 25, count 0 2006.182.08:26:59.86#ibcon#flushed, iclass 25, count 0 2006.182.08:26:59.86#ibcon#about to write, iclass 25, count 0 2006.182.08:26:59.86#ibcon#wrote, iclass 25, count 0 2006.182.08:26:59.86#ibcon#about to read 3, iclass 25, count 0 2006.182.08:26:59.88#ibcon#read 3, iclass 25, count 0 2006.182.08:26:59.88#ibcon#about to read 4, iclass 25, count 0 2006.182.08:26:59.88#ibcon#read 4, iclass 25, count 0 2006.182.08:26:59.88#ibcon#about to read 5, iclass 25, count 0 2006.182.08:26:59.88#ibcon#read 5, iclass 25, count 0 2006.182.08:26:59.88#ibcon#about to read 6, iclass 25, count 0 2006.182.08:26:59.88#ibcon#read 6, iclass 25, count 0 2006.182.08:26:59.88#ibcon#end of sib2, iclass 25, count 0 2006.182.08:26:59.88#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:26:59.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:26:59.88#ibcon#[25=USB\r\n] 2006.182.08:26:59.88#ibcon#*before write, iclass 25, count 0 2006.182.08:26:59.88#ibcon#enter sib2, iclass 25, count 0 2006.182.08:26:59.88#ibcon#flushed, iclass 25, count 0 2006.182.08:26:59.88#ibcon#about to write, iclass 25, count 0 2006.182.08:26:59.88#ibcon#wrote, iclass 25, count 0 2006.182.08:26:59.88#ibcon#about to read 3, iclass 25, count 0 2006.182.08:26:59.91#ibcon#read 3, iclass 25, count 0 2006.182.08:26:59.91#ibcon#about to read 4, iclass 25, count 0 2006.182.08:26:59.91#ibcon#read 4, iclass 25, count 0 2006.182.08:26:59.91#ibcon#about to read 5, iclass 25, count 0 2006.182.08:26:59.91#ibcon#read 5, iclass 25, count 0 2006.182.08:26:59.91#ibcon#about to read 6, iclass 25, count 0 2006.182.08:26:59.91#ibcon#read 6, iclass 25, count 0 2006.182.08:26:59.91#ibcon#end of sib2, iclass 25, count 0 2006.182.08:26:59.91#ibcon#*after write, iclass 25, count 0 2006.182.08:26:59.91#ibcon#*before return 0, iclass 25, count 0 2006.182.08:26:59.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:26:59.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:26:59.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:26:59.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:26:59.91$vc4f8/valo=7,832.99 2006.182.08:26:59.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.08:26:59.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.08:26:59.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:26:59.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:26:59.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:26:59.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:26:59.91#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:26:59.91#ibcon#first serial, iclass 27, count 0 2006.182.08:26:59.91#ibcon#enter sib2, iclass 27, count 0 2006.182.08:26:59.91#ibcon#flushed, iclass 27, count 0 2006.182.08:26:59.91#ibcon#about to write, iclass 27, count 0 2006.182.08:26:59.91#ibcon#wrote, iclass 27, count 0 2006.182.08:26:59.91#ibcon#about to read 3, iclass 27, count 0 2006.182.08:26:59.93#ibcon#read 3, iclass 27, count 0 2006.182.08:26:59.93#ibcon#about to read 4, iclass 27, count 0 2006.182.08:26:59.93#ibcon#read 4, iclass 27, count 0 2006.182.08:26:59.93#ibcon#about to read 5, iclass 27, count 0 2006.182.08:26:59.93#ibcon#read 5, iclass 27, count 0 2006.182.08:26:59.93#ibcon#about to read 6, iclass 27, count 0 2006.182.08:26:59.93#ibcon#read 6, iclass 27, count 0 2006.182.08:26:59.93#ibcon#end of sib2, iclass 27, count 0 2006.182.08:26:59.93#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:26:59.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:26:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:26:59.93#ibcon#*before write, iclass 27, count 0 2006.182.08:26:59.93#ibcon#enter sib2, iclass 27, count 0 2006.182.08:26:59.93#ibcon#flushed, iclass 27, count 0 2006.182.08:26:59.93#ibcon#about to write, iclass 27, count 0 2006.182.08:26:59.93#ibcon#wrote, iclass 27, count 0 2006.182.08:26:59.93#ibcon#about to read 3, iclass 27, count 0 2006.182.08:26:59.97#ibcon#read 3, iclass 27, count 0 2006.182.08:26:59.97#ibcon#about to read 4, iclass 27, count 0 2006.182.08:26:59.97#ibcon#read 4, iclass 27, count 0 2006.182.08:26:59.97#ibcon#about to read 5, iclass 27, count 0 2006.182.08:26:59.97#ibcon#read 5, iclass 27, count 0 2006.182.08:26:59.97#ibcon#about to read 6, iclass 27, count 0 2006.182.08:26:59.97#ibcon#read 6, iclass 27, count 0 2006.182.08:26:59.97#ibcon#end of sib2, iclass 27, count 0 2006.182.08:26:59.97#ibcon#*after write, iclass 27, count 0 2006.182.08:26:59.97#ibcon#*before return 0, iclass 27, count 0 2006.182.08:26:59.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:26:59.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:26:59.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:26:59.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:26:59.97$vc4f8/va=7,6 2006.182.08:26:59.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.182.08:26:59.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.182.08:26:59.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:26:59.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:27:00.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:27:00.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:27:00.03#ibcon#enter wrdev, iclass 29, count 2 2006.182.08:27:00.03#ibcon#first serial, iclass 29, count 2 2006.182.08:27:00.03#ibcon#enter sib2, iclass 29, count 2 2006.182.08:27:00.03#ibcon#flushed, iclass 29, count 2 2006.182.08:27:00.03#ibcon#about to write, iclass 29, count 2 2006.182.08:27:00.03#ibcon#wrote, iclass 29, count 2 2006.182.08:27:00.03#ibcon#about to read 3, iclass 29, count 2 2006.182.08:27:00.05#ibcon#read 3, iclass 29, count 2 2006.182.08:27:00.05#ibcon#about to read 4, iclass 29, count 2 2006.182.08:27:00.05#ibcon#read 4, iclass 29, count 2 2006.182.08:27:00.05#ibcon#about to read 5, iclass 29, count 2 2006.182.08:27:00.05#ibcon#read 5, iclass 29, count 2 2006.182.08:27:00.05#ibcon#about to read 6, iclass 29, count 2 2006.182.08:27:00.05#ibcon#read 6, iclass 29, count 2 2006.182.08:27:00.05#ibcon#end of sib2, iclass 29, count 2 2006.182.08:27:00.05#ibcon#*mode == 0, iclass 29, count 2 2006.182.08:27:00.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.182.08:27:00.05#ibcon#[25=AT07-06\r\n] 2006.182.08:27:00.05#ibcon#*before write, iclass 29, count 2 2006.182.08:27:00.05#ibcon#enter sib2, iclass 29, count 2 2006.182.08:27:00.05#ibcon#flushed, iclass 29, count 2 2006.182.08:27:00.05#ibcon#about to write, iclass 29, count 2 2006.182.08:27:00.05#ibcon#wrote, iclass 29, count 2 2006.182.08:27:00.05#ibcon#about to read 3, iclass 29, count 2 2006.182.08:27:00.08#ibcon#read 3, iclass 29, count 2 2006.182.08:27:00.08#ibcon#about to read 4, iclass 29, count 2 2006.182.08:27:00.08#ibcon#read 4, iclass 29, count 2 2006.182.08:27:00.08#ibcon#about to read 5, iclass 29, count 2 2006.182.08:27:00.08#ibcon#read 5, iclass 29, count 2 2006.182.08:27:00.08#ibcon#about to read 6, iclass 29, count 2 2006.182.08:27:00.08#ibcon#read 6, iclass 29, count 2 2006.182.08:27:00.08#ibcon#end of sib2, iclass 29, count 2 2006.182.08:27:00.08#ibcon#*after write, iclass 29, count 2 2006.182.08:27:00.08#ibcon#*before return 0, iclass 29, count 2 2006.182.08:27:00.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:27:00.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.182.08:27:00.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.182.08:27:00.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:27:00.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:27:00.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:27:00.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:27:00.20#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:27:00.20#ibcon#first serial, iclass 29, count 0 2006.182.08:27:00.20#ibcon#enter sib2, iclass 29, count 0 2006.182.08:27:00.20#ibcon#flushed, iclass 29, count 0 2006.182.08:27:00.20#ibcon#about to write, iclass 29, count 0 2006.182.08:27:00.20#ibcon#wrote, iclass 29, count 0 2006.182.08:27:00.20#ibcon#about to read 3, iclass 29, count 0 2006.182.08:27:00.22#ibcon#read 3, iclass 29, count 0 2006.182.08:27:00.22#ibcon#about to read 4, iclass 29, count 0 2006.182.08:27:00.22#ibcon#read 4, iclass 29, count 0 2006.182.08:27:00.22#ibcon#about to read 5, iclass 29, count 0 2006.182.08:27:00.22#ibcon#read 5, iclass 29, count 0 2006.182.08:27:00.22#ibcon#about to read 6, iclass 29, count 0 2006.182.08:27:00.22#ibcon#read 6, iclass 29, count 0 2006.182.08:27:00.22#ibcon#end of sib2, iclass 29, count 0 2006.182.08:27:00.22#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:27:00.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:27:00.22#ibcon#[25=USB\r\n] 2006.182.08:27:00.22#ibcon#*before write, iclass 29, count 0 2006.182.08:27:00.22#ibcon#enter sib2, iclass 29, count 0 2006.182.08:27:00.22#ibcon#flushed, iclass 29, count 0 2006.182.08:27:00.22#ibcon#about to write, iclass 29, count 0 2006.182.08:27:00.22#ibcon#wrote, iclass 29, count 0 2006.182.08:27:00.22#ibcon#about to read 3, iclass 29, count 0 2006.182.08:27:00.25#ibcon#read 3, iclass 29, count 0 2006.182.08:27:00.25#ibcon#about to read 4, iclass 29, count 0 2006.182.08:27:00.25#ibcon#read 4, iclass 29, count 0 2006.182.08:27:00.25#ibcon#about to read 5, iclass 29, count 0 2006.182.08:27:00.25#ibcon#read 5, iclass 29, count 0 2006.182.08:27:00.25#ibcon#about to read 6, iclass 29, count 0 2006.182.08:27:00.25#ibcon#read 6, iclass 29, count 0 2006.182.08:27:00.25#ibcon#end of sib2, iclass 29, count 0 2006.182.08:27:00.25#ibcon#*after write, iclass 29, count 0 2006.182.08:27:00.25#ibcon#*before return 0, iclass 29, count 0 2006.182.08:27:00.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:27:00.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.182.08:27:00.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:27:00.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:27:00.25$vc4f8/valo=8,852.99 2006.182.08:27:00.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.182.08:27:00.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.182.08:27:00.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:27:00.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:27:00.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:27:00.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:27:00.25#ibcon#enter wrdev, iclass 31, count 0 2006.182.08:27:00.25#ibcon#first serial, iclass 31, count 0 2006.182.08:27:00.25#ibcon#enter sib2, iclass 31, count 0 2006.182.08:27:00.25#ibcon#flushed, iclass 31, count 0 2006.182.08:27:00.25#ibcon#about to write, iclass 31, count 0 2006.182.08:27:00.25#ibcon#wrote, iclass 31, count 0 2006.182.08:27:00.25#ibcon#about to read 3, iclass 31, count 0 2006.182.08:27:00.27#ibcon#read 3, iclass 31, count 0 2006.182.08:27:00.27#ibcon#about to read 4, iclass 31, count 0 2006.182.08:27:00.27#ibcon#read 4, iclass 31, count 0 2006.182.08:27:00.27#ibcon#about to read 5, iclass 31, count 0 2006.182.08:27:00.27#ibcon#read 5, iclass 31, count 0 2006.182.08:27:00.27#ibcon#about to read 6, iclass 31, count 0 2006.182.08:27:00.27#ibcon#read 6, iclass 31, count 0 2006.182.08:27:00.27#ibcon#end of sib2, iclass 31, count 0 2006.182.08:27:00.27#ibcon#*mode == 0, iclass 31, count 0 2006.182.08:27:00.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.182.08:27:00.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:27:00.27#ibcon#*before write, iclass 31, count 0 2006.182.08:27:00.27#ibcon#enter sib2, iclass 31, count 0 2006.182.08:27:00.27#ibcon#flushed, iclass 31, count 0 2006.182.08:27:00.27#ibcon#about to write, iclass 31, count 0 2006.182.08:27:00.27#ibcon#wrote, iclass 31, count 0 2006.182.08:27:00.27#ibcon#about to read 3, iclass 31, count 0 2006.182.08:27:00.31#ibcon#read 3, iclass 31, count 0 2006.182.08:27:00.31#ibcon#about to read 4, iclass 31, count 0 2006.182.08:27:00.31#ibcon#read 4, iclass 31, count 0 2006.182.08:27:00.31#ibcon#about to read 5, iclass 31, count 0 2006.182.08:27:00.31#ibcon#read 5, iclass 31, count 0 2006.182.08:27:00.31#ibcon#about to read 6, iclass 31, count 0 2006.182.08:27:00.31#ibcon#read 6, iclass 31, count 0 2006.182.08:27:00.31#ibcon#end of sib2, iclass 31, count 0 2006.182.08:27:00.31#ibcon#*after write, iclass 31, count 0 2006.182.08:27:00.31#ibcon#*before return 0, iclass 31, count 0 2006.182.08:27:00.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:27:00.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.182.08:27:00.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.182.08:27:00.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.182.08:27:00.31$vc4f8/va=8,7 2006.182.08:27:00.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.182.08:27:00.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.182.08:27:00.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:27:00.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:27:00.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:27:00.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:27:00.37#ibcon#enter wrdev, iclass 33, count 2 2006.182.08:27:00.37#ibcon#first serial, iclass 33, count 2 2006.182.08:27:00.37#ibcon#enter sib2, iclass 33, count 2 2006.182.08:27:00.37#ibcon#flushed, iclass 33, count 2 2006.182.08:27:00.37#ibcon#about to write, iclass 33, count 2 2006.182.08:27:00.37#ibcon#wrote, iclass 33, count 2 2006.182.08:27:00.37#ibcon#about to read 3, iclass 33, count 2 2006.182.08:27:00.39#ibcon#read 3, iclass 33, count 2 2006.182.08:27:00.39#ibcon#about to read 4, iclass 33, count 2 2006.182.08:27:00.39#ibcon#read 4, iclass 33, count 2 2006.182.08:27:00.39#ibcon#about to read 5, iclass 33, count 2 2006.182.08:27:00.39#ibcon#read 5, iclass 33, count 2 2006.182.08:27:00.39#ibcon#about to read 6, iclass 33, count 2 2006.182.08:27:00.39#ibcon#read 6, iclass 33, count 2 2006.182.08:27:00.39#ibcon#end of sib2, iclass 33, count 2 2006.182.08:27:00.39#ibcon#*mode == 0, iclass 33, count 2 2006.182.08:27:00.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.182.08:27:00.39#ibcon#[25=AT08-07\r\n] 2006.182.08:27:00.39#ibcon#*before write, iclass 33, count 2 2006.182.08:27:00.39#ibcon#enter sib2, iclass 33, count 2 2006.182.08:27:00.39#ibcon#flushed, iclass 33, count 2 2006.182.08:27:00.39#ibcon#about to write, iclass 33, count 2 2006.182.08:27:00.39#ibcon#wrote, iclass 33, count 2 2006.182.08:27:00.39#ibcon#about to read 3, iclass 33, count 2 2006.182.08:27:00.42#ibcon#read 3, iclass 33, count 2 2006.182.08:27:00.42#ibcon#about to read 4, iclass 33, count 2 2006.182.08:27:00.42#ibcon#read 4, iclass 33, count 2 2006.182.08:27:00.42#ibcon#about to read 5, iclass 33, count 2 2006.182.08:27:00.42#ibcon#read 5, iclass 33, count 2 2006.182.08:27:00.42#ibcon#about to read 6, iclass 33, count 2 2006.182.08:27:00.42#ibcon#read 6, iclass 33, count 2 2006.182.08:27:00.42#ibcon#end of sib2, iclass 33, count 2 2006.182.08:27:00.42#ibcon#*after write, iclass 33, count 2 2006.182.08:27:00.42#ibcon#*before return 0, iclass 33, count 2 2006.182.08:27:00.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:27:00.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.182.08:27:00.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.182.08:27:00.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:27:00.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:27:00.45#abcon#<5=/08 1.0 2.6 27.63 801002.9\r\n> 2006.182.08:27:00.47#abcon#{5=INTERFACE CLEAR} 2006.182.08:27:00.53#abcon#[5=S1D000X0/0*\r\n] 2006.182.08:27:00.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:27:00.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:27:00.54#ibcon#enter wrdev, iclass 33, count 0 2006.182.08:27:00.54#ibcon#first serial, iclass 33, count 0 2006.182.08:27:00.54#ibcon#enter sib2, iclass 33, count 0 2006.182.08:27:00.54#ibcon#flushed, iclass 33, count 0 2006.182.08:27:00.54#ibcon#about to write, iclass 33, count 0 2006.182.08:27:00.54#ibcon#wrote, iclass 33, count 0 2006.182.08:27:00.54#ibcon#about to read 3, iclass 33, count 0 2006.182.08:27:00.56#ibcon#read 3, iclass 33, count 0 2006.182.08:27:00.56#ibcon#about to read 4, iclass 33, count 0 2006.182.08:27:00.56#ibcon#read 4, iclass 33, count 0 2006.182.08:27:00.56#ibcon#about to read 5, iclass 33, count 0 2006.182.08:27:00.56#ibcon#read 5, iclass 33, count 0 2006.182.08:27:00.56#ibcon#about to read 6, iclass 33, count 0 2006.182.08:27:00.56#ibcon#read 6, iclass 33, count 0 2006.182.08:27:00.56#ibcon#end of sib2, iclass 33, count 0 2006.182.08:27:00.56#ibcon#*mode == 0, iclass 33, count 0 2006.182.08:27:00.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.182.08:27:00.56#ibcon#[25=USB\r\n] 2006.182.08:27:00.56#ibcon#*before write, iclass 33, count 0 2006.182.08:27:00.56#ibcon#enter sib2, iclass 33, count 0 2006.182.08:27:00.56#ibcon#flushed, iclass 33, count 0 2006.182.08:27:00.56#ibcon#about to write, iclass 33, count 0 2006.182.08:27:00.56#ibcon#wrote, iclass 33, count 0 2006.182.08:27:00.56#ibcon#about to read 3, iclass 33, count 0 2006.182.08:27:00.59#ibcon#read 3, iclass 33, count 0 2006.182.08:27:00.59#ibcon#about to read 4, iclass 33, count 0 2006.182.08:27:00.59#ibcon#read 4, iclass 33, count 0 2006.182.08:27:00.59#ibcon#about to read 5, iclass 33, count 0 2006.182.08:27:00.59#ibcon#read 5, iclass 33, count 0 2006.182.08:27:00.59#ibcon#about to read 6, iclass 33, count 0 2006.182.08:27:00.59#ibcon#read 6, iclass 33, count 0 2006.182.08:27:00.59#ibcon#end of sib2, iclass 33, count 0 2006.182.08:27:00.59#ibcon#*after write, iclass 33, count 0 2006.182.08:27:00.59#ibcon#*before return 0, iclass 33, count 0 2006.182.08:27:00.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:27:00.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.182.08:27:00.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.182.08:27:00.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.182.08:27:00.59$vc4f8/vblo=1,632.99 2006.182.08:27:00.59#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.182.08:27:00.59#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.182.08:27:00.59#ibcon#ireg 17 cls_cnt 0 2006.182.08:27:00.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:27:00.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:27:00.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:27:00.59#ibcon#enter wrdev, iclass 39, count 0 2006.182.08:27:00.59#ibcon#first serial, iclass 39, count 0 2006.182.08:27:00.59#ibcon#enter sib2, iclass 39, count 0 2006.182.08:27:00.59#ibcon#flushed, iclass 39, count 0 2006.182.08:27:00.59#ibcon#about to write, iclass 39, count 0 2006.182.08:27:00.59#ibcon#wrote, iclass 39, count 0 2006.182.08:27:00.59#ibcon#about to read 3, iclass 39, count 0 2006.182.08:27:00.61#ibcon#read 3, iclass 39, count 0 2006.182.08:27:00.61#ibcon#about to read 4, iclass 39, count 0 2006.182.08:27:00.61#ibcon#read 4, iclass 39, count 0 2006.182.08:27:00.61#ibcon#about to read 5, iclass 39, count 0 2006.182.08:27:00.61#ibcon#read 5, iclass 39, count 0 2006.182.08:27:00.61#ibcon#about to read 6, iclass 39, count 0 2006.182.08:27:00.61#ibcon#read 6, iclass 39, count 0 2006.182.08:27:00.61#ibcon#end of sib2, iclass 39, count 0 2006.182.08:27:00.61#ibcon#*mode == 0, iclass 39, count 0 2006.182.08:27:00.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.182.08:27:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:27:00.61#ibcon#*before write, iclass 39, count 0 2006.182.08:27:00.61#ibcon#enter sib2, iclass 39, count 0 2006.182.08:27:00.61#ibcon#flushed, iclass 39, count 0 2006.182.08:27:00.61#ibcon#about to write, iclass 39, count 0 2006.182.08:27:00.61#ibcon#wrote, iclass 39, count 0 2006.182.08:27:00.61#ibcon#about to read 3, iclass 39, count 0 2006.182.08:27:00.65#ibcon#read 3, iclass 39, count 0 2006.182.08:27:00.65#ibcon#about to read 4, iclass 39, count 0 2006.182.08:27:00.65#ibcon#read 4, iclass 39, count 0 2006.182.08:27:00.65#ibcon#about to read 5, iclass 39, count 0 2006.182.08:27:00.65#ibcon#read 5, iclass 39, count 0 2006.182.08:27:00.65#ibcon#about to read 6, iclass 39, count 0 2006.182.08:27:00.65#ibcon#read 6, iclass 39, count 0 2006.182.08:27:00.65#ibcon#end of sib2, iclass 39, count 0 2006.182.08:27:00.65#ibcon#*after write, iclass 39, count 0 2006.182.08:27:00.65#ibcon#*before return 0, iclass 39, count 0 2006.182.08:27:00.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:27:00.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.182.08:27:00.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.182.08:27:00.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.182.08:27:00.65$vc4f8/vb=1,4 2006.182.08:27:00.65#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.182.08:27:00.65#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.182.08:27:00.65#ibcon#ireg 11 cls_cnt 2 2006.182.08:27:00.65#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:27:00.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:27:00.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:27:00.65#ibcon#enter wrdev, iclass 3, count 2 2006.182.08:27:00.65#ibcon#first serial, iclass 3, count 2 2006.182.08:27:00.65#ibcon#enter sib2, iclass 3, count 2 2006.182.08:27:00.65#ibcon#flushed, iclass 3, count 2 2006.182.08:27:00.65#ibcon#about to write, iclass 3, count 2 2006.182.08:27:00.65#ibcon#wrote, iclass 3, count 2 2006.182.08:27:00.65#ibcon#about to read 3, iclass 3, count 2 2006.182.08:27:00.67#ibcon#read 3, iclass 3, count 2 2006.182.08:27:00.67#ibcon#about to read 4, iclass 3, count 2 2006.182.08:27:00.67#ibcon#read 4, iclass 3, count 2 2006.182.08:27:00.67#ibcon#about to read 5, iclass 3, count 2 2006.182.08:27:00.67#ibcon#read 5, iclass 3, count 2 2006.182.08:27:00.67#ibcon#about to read 6, iclass 3, count 2 2006.182.08:27:00.67#ibcon#read 6, iclass 3, count 2 2006.182.08:27:00.67#ibcon#end of sib2, iclass 3, count 2 2006.182.08:27:00.67#ibcon#*mode == 0, iclass 3, count 2 2006.182.08:27:00.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.182.08:27:00.67#ibcon#[27=AT01-04\r\n] 2006.182.08:27:00.67#ibcon#*before write, iclass 3, count 2 2006.182.08:27:00.67#ibcon#enter sib2, iclass 3, count 2 2006.182.08:27:00.67#ibcon#flushed, iclass 3, count 2 2006.182.08:27:00.67#ibcon#about to write, iclass 3, count 2 2006.182.08:27:00.67#ibcon#wrote, iclass 3, count 2 2006.182.08:27:00.67#ibcon#about to read 3, iclass 3, count 2 2006.182.08:27:00.70#ibcon#read 3, iclass 3, count 2 2006.182.08:27:00.70#ibcon#about to read 4, iclass 3, count 2 2006.182.08:27:00.70#ibcon#read 4, iclass 3, count 2 2006.182.08:27:00.70#ibcon#about to read 5, iclass 3, count 2 2006.182.08:27:00.70#ibcon#read 5, iclass 3, count 2 2006.182.08:27:00.70#ibcon#about to read 6, iclass 3, count 2 2006.182.08:27:00.70#ibcon#read 6, iclass 3, count 2 2006.182.08:27:00.70#ibcon#end of sib2, iclass 3, count 2 2006.182.08:27:00.70#ibcon#*after write, iclass 3, count 2 2006.182.08:27:00.70#ibcon#*before return 0, iclass 3, count 2 2006.182.08:27:00.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:27:00.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.182.08:27:00.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.182.08:27:00.70#ibcon#ireg 7 cls_cnt 0 2006.182.08:27:00.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:27:00.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:27:00.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:27:00.82#ibcon#enter wrdev, iclass 3, count 0 2006.182.08:27:00.82#ibcon#first serial, iclass 3, count 0 2006.182.08:27:00.82#ibcon#enter sib2, iclass 3, count 0 2006.182.08:27:00.82#ibcon#flushed, iclass 3, count 0 2006.182.08:27:00.82#ibcon#about to write, iclass 3, count 0 2006.182.08:27:00.82#ibcon#wrote, iclass 3, count 0 2006.182.08:27:00.82#ibcon#about to read 3, iclass 3, count 0 2006.182.08:27:00.84#ibcon#read 3, iclass 3, count 0 2006.182.08:27:00.84#ibcon#about to read 4, iclass 3, count 0 2006.182.08:27:00.84#ibcon#read 4, iclass 3, count 0 2006.182.08:27:00.84#ibcon#about to read 5, iclass 3, count 0 2006.182.08:27:00.84#ibcon#read 5, iclass 3, count 0 2006.182.08:27:00.84#ibcon#about to read 6, iclass 3, count 0 2006.182.08:27:00.84#ibcon#read 6, iclass 3, count 0 2006.182.08:27:00.84#ibcon#end of sib2, iclass 3, count 0 2006.182.08:27:00.84#ibcon#*mode == 0, iclass 3, count 0 2006.182.08:27:00.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.182.08:27:00.84#ibcon#[27=USB\r\n] 2006.182.08:27:00.84#ibcon#*before write, iclass 3, count 0 2006.182.08:27:00.84#ibcon#enter sib2, iclass 3, count 0 2006.182.08:27:00.84#ibcon#flushed, iclass 3, count 0 2006.182.08:27:00.84#ibcon#about to write, iclass 3, count 0 2006.182.08:27:00.84#ibcon#wrote, iclass 3, count 0 2006.182.08:27:00.84#ibcon#about to read 3, iclass 3, count 0 2006.182.08:27:00.87#ibcon#read 3, iclass 3, count 0 2006.182.08:27:00.87#ibcon#about to read 4, iclass 3, count 0 2006.182.08:27:00.87#ibcon#read 4, iclass 3, count 0 2006.182.08:27:00.87#ibcon#about to read 5, iclass 3, count 0 2006.182.08:27:00.87#ibcon#read 5, iclass 3, count 0 2006.182.08:27:00.87#ibcon#about to read 6, iclass 3, count 0 2006.182.08:27:00.87#ibcon#read 6, iclass 3, count 0 2006.182.08:27:00.87#ibcon#end of sib2, iclass 3, count 0 2006.182.08:27:00.87#ibcon#*after write, iclass 3, count 0 2006.182.08:27:00.87#ibcon#*before return 0, iclass 3, count 0 2006.182.08:27:00.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:27:00.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.182.08:27:00.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.182.08:27:00.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.182.08:27:00.87$vc4f8/vblo=2,640.99 2006.182.08:27:00.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.182.08:27:00.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.182.08:27:00.87#ibcon#ireg 17 cls_cnt 0 2006.182.08:27:00.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:27:00.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:27:00.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:27:00.87#ibcon#enter wrdev, iclass 5, count 0 2006.182.08:27:00.87#ibcon#first serial, iclass 5, count 0 2006.182.08:27:00.87#ibcon#enter sib2, iclass 5, count 0 2006.182.08:27:00.87#ibcon#flushed, iclass 5, count 0 2006.182.08:27:00.87#ibcon#about to write, iclass 5, count 0 2006.182.08:27:00.87#ibcon#wrote, iclass 5, count 0 2006.182.08:27:00.87#ibcon#about to read 3, iclass 5, count 0 2006.182.08:27:00.89#ibcon#read 3, iclass 5, count 0 2006.182.08:27:00.89#ibcon#about to read 4, iclass 5, count 0 2006.182.08:27:00.89#ibcon#read 4, iclass 5, count 0 2006.182.08:27:00.89#ibcon#about to read 5, iclass 5, count 0 2006.182.08:27:00.89#ibcon#read 5, iclass 5, count 0 2006.182.08:27:00.89#ibcon#about to read 6, iclass 5, count 0 2006.182.08:27:00.89#ibcon#read 6, iclass 5, count 0 2006.182.08:27:00.89#ibcon#end of sib2, iclass 5, count 0 2006.182.08:27:00.89#ibcon#*mode == 0, iclass 5, count 0 2006.182.08:27:00.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.182.08:27:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:27:00.89#ibcon#*before write, iclass 5, count 0 2006.182.08:27:00.89#ibcon#enter sib2, iclass 5, count 0 2006.182.08:27:00.89#ibcon#flushed, iclass 5, count 0 2006.182.08:27:00.89#ibcon#about to write, iclass 5, count 0 2006.182.08:27:00.89#ibcon#wrote, iclass 5, count 0 2006.182.08:27:00.89#ibcon#about to read 3, iclass 5, count 0 2006.182.08:27:00.93#ibcon#read 3, iclass 5, count 0 2006.182.08:27:00.93#ibcon#about to read 4, iclass 5, count 0 2006.182.08:27:00.93#ibcon#read 4, iclass 5, count 0 2006.182.08:27:00.93#ibcon#about to read 5, iclass 5, count 0 2006.182.08:27:00.93#ibcon#read 5, iclass 5, count 0 2006.182.08:27:00.93#ibcon#about to read 6, iclass 5, count 0 2006.182.08:27:00.93#ibcon#read 6, iclass 5, count 0 2006.182.08:27:00.93#ibcon#end of sib2, iclass 5, count 0 2006.182.08:27:00.93#ibcon#*after write, iclass 5, count 0 2006.182.08:27:00.93#ibcon#*before return 0, iclass 5, count 0 2006.182.08:27:00.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:27:00.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.182.08:27:00.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.182.08:27:00.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.182.08:27:00.93$vc4f8/vb=2,4 2006.182.08:27:00.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.182.08:27:00.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.182.08:27:00.93#ibcon#ireg 11 cls_cnt 2 2006.182.08:27:00.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:27:00.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:27:00.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:27:00.99#ibcon#enter wrdev, iclass 7, count 2 2006.182.08:27:00.99#ibcon#first serial, iclass 7, count 2 2006.182.08:27:00.99#ibcon#enter sib2, iclass 7, count 2 2006.182.08:27:00.99#ibcon#flushed, iclass 7, count 2 2006.182.08:27:00.99#ibcon#about to write, iclass 7, count 2 2006.182.08:27:00.99#ibcon#wrote, iclass 7, count 2 2006.182.08:27:00.99#ibcon#about to read 3, iclass 7, count 2 2006.182.08:27:01.01#ibcon#read 3, iclass 7, count 2 2006.182.08:27:01.01#ibcon#about to read 4, iclass 7, count 2 2006.182.08:27:01.01#ibcon#read 4, iclass 7, count 2 2006.182.08:27:01.01#ibcon#about to read 5, iclass 7, count 2 2006.182.08:27:01.01#ibcon#read 5, iclass 7, count 2 2006.182.08:27:01.01#ibcon#about to read 6, iclass 7, count 2 2006.182.08:27:01.01#ibcon#read 6, iclass 7, count 2 2006.182.08:27:01.01#ibcon#end of sib2, iclass 7, count 2 2006.182.08:27:01.01#ibcon#*mode == 0, iclass 7, count 2 2006.182.08:27:01.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.182.08:27:01.01#ibcon#[27=AT02-04\r\n] 2006.182.08:27:01.01#ibcon#*before write, iclass 7, count 2 2006.182.08:27:01.01#ibcon#enter sib2, iclass 7, count 2 2006.182.08:27:01.01#ibcon#flushed, iclass 7, count 2 2006.182.08:27:01.01#ibcon#about to write, iclass 7, count 2 2006.182.08:27:01.01#ibcon#wrote, iclass 7, count 2 2006.182.08:27:01.01#ibcon#about to read 3, iclass 7, count 2 2006.182.08:27:01.04#ibcon#read 3, iclass 7, count 2 2006.182.08:27:01.04#ibcon#about to read 4, iclass 7, count 2 2006.182.08:27:01.04#ibcon#read 4, iclass 7, count 2 2006.182.08:27:01.04#ibcon#about to read 5, iclass 7, count 2 2006.182.08:27:01.04#ibcon#read 5, iclass 7, count 2 2006.182.08:27:01.04#ibcon#about to read 6, iclass 7, count 2 2006.182.08:27:01.04#ibcon#read 6, iclass 7, count 2 2006.182.08:27:01.04#ibcon#end of sib2, iclass 7, count 2 2006.182.08:27:01.04#ibcon#*after write, iclass 7, count 2 2006.182.08:27:01.04#ibcon#*before return 0, iclass 7, count 2 2006.182.08:27:01.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:27:01.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.182.08:27:01.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.182.08:27:01.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:27:01.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:27:01.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:27:01.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:27:01.16#ibcon#enter wrdev, iclass 7, count 0 2006.182.08:27:01.16#ibcon#first serial, iclass 7, count 0 2006.182.08:27:01.16#ibcon#enter sib2, iclass 7, count 0 2006.182.08:27:01.16#ibcon#flushed, iclass 7, count 0 2006.182.08:27:01.16#ibcon#about to write, iclass 7, count 0 2006.182.08:27:01.16#ibcon#wrote, iclass 7, count 0 2006.182.08:27:01.16#ibcon#about to read 3, iclass 7, count 0 2006.182.08:27:01.18#ibcon#read 3, iclass 7, count 0 2006.182.08:27:01.18#ibcon#about to read 4, iclass 7, count 0 2006.182.08:27:01.18#ibcon#read 4, iclass 7, count 0 2006.182.08:27:01.18#ibcon#about to read 5, iclass 7, count 0 2006.182.08:27:01.18#ibcon#read 5, iclass 7, count 0 2006.182.08:27:01.18#ibcon#about to read 6, iclass 7, count 0 2006.182.08:27:01.18#ibcon#read 6, iclass 7, count 0 2006.182.08:27:01.18#ibcon#end of sib2, iclass 7, count 0 2006.182.08:27:01.18#ibcon#*mode == 0, iclass 7, count 0 2006.182.08:27:01.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.182.08:27:01.18#ibcon#[27=USB\r\n] 2006.182.08:27:01.18#ibcon#*before write, iclass 7, count 0 2006.182.08:27:01.18#ibcon#enter sib2, iclass 7, count 0 2006.182.08:27:01.18#ibcon#flushed, iclass 7, count 0 2006.182.08:27:01.18#ibcon#about to write, iclass 7, count 0 2006.182.08:27:01.18#ibcon#wrote, iclass 7, count 0 2006.182.08:27:01.18#ibcon#about to read 3, iclass 7, count 0 2006.182.08:27:01.21#ibcon#read 3, iclass 7, count 0 2006.182.08:27:01.21#ibcon#about to read 4, iclass 7, count 0 2006.182.08:27:01.21#ibcon#read 4, iclass 7, count 0 2006.182.08:27:01.21#ibcon#about to read 5, iclass 7, count 0 2006.182.08:27:01.21#ibcon#read 5, iclass 7, count 0 2006.182.08:27:01.21#ibcon#about to read 6, iclass 7, count 0 2006.182.08:27:01.21#ibcon#read 6, iclass 7, count 0 2006.182.08:27:01.21#ibcon#end of sib2, iclass 7, count 0 2006.182.08:27:01.21#ibcon#*after write, iclass 7, count 0 2006.182.08:27:01.21#ibcon#*before return 0, iclass 7, count 0 2006.182.08:27:01.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:27:01.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.182.08:27:01.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.182.08:27:01.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.182.08:27:01.21$vc4f8/vblo=3,656.99 2006.182.08:27:01.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.182.08:27:01.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.182.08:27:01.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:27:01.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:27:01.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:27:01.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:27:01.21#ibcon#enter wrdev, iclass 11, count 0 2006.182.08:27:01.21#ibcon#first serial, iclass 11, count 0 2006.182.08:27:01.21#ibcon#enter sib2, iclass 11, count 0 2006.182.08:27:01.21#ibcon#flushed, iclass 11, count 0 2006.182.08:27:01.21#ibcon#about to write, iclass 11, count 0 2006.182.08:27:01.21#ibcon#wrote, iclass 11, count 0 2006.182.08:27:01.21#ibcon#about to read 3, iclass 11, count 0 2006.182.08:27:01.23#ibcon#read 3, iclass 11, count 0 2006.182.08:27:01.23#ibcon#about to read 4, iclass 11, count 0 2006.182.08:27:01.23#ibcon#read 4, iclass 11, count 0 2006.182.08:27:01.23#ibcon#about to read 5, iclass 11, count 0 2006.182.08:27:01.23#ibcon#read 5, iclass 11, count 0 2006.182.08:27:01.23#ibcon#about to read 6, iclass 11, count 0 2006.182.08:27:01.23#ibcon#read 6, iclass 11, count 0 2006.182.08:27:01.23#ibcon#end of sib2, iclass 11, count 0 2006.182.08:27:01.23#ibcon#*mode == 0, iclass 11, count 0 2006.182.08:27:01.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.182.08:27:01.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:27:01.23#ibcon#*before write, iclass 11, count 0 2006.182.08:27:01.23#ibcon#enter sib2, iclass 11, count 0 2006.182.08:27:01.23#ibcon#flushed, iclass 11, count 0 2006.182.08:27:01.23#ibcon#about to write, iclass 11, count 0 2006.182.08:27:01.23#ibcon#wrote, iclass 11, count 0 2006.182.08:27:01.23#ibcon#about to read 3, iclass 11, count 0 2006.182.08:27:01.27#ibcon#read 3, iclass 11, count 0 2006.182.08:27:01.27#ibcon#about to read 4, iclass 11, count 0 2006.182.08:27:01.27#ibcon#read 4, iclass 11, count 0 2006.182.08:27:01.27#ibcon#about to read 5, iclass 11, count 0 2006.182.08:27:01.27#ibcon#read 5, iclass 11, count 0 2006.182.08:27:01.27#ibcon#about to read 6, iclass 11, count 0 2006.182.08:27:01.27#ibcon#read 6, iclass 11, count 0 2006.182.08:27:01.27#ibcon#end of sib2, iclass 11, count 0 2006.182.08:27:01.27#ibcon#*after write, iclass 11, count 0 2006.182.08:27:01.27#ibcon#*before return 0, iclass 11, count 0 2006.182.08:27:01.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:27:01.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.182.08:27:01.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.182.08:27:01.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.182.08:27:01.27$vc4f8/vb=3,4 2006.182.08:27:01.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.182.08:27:01.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.182.08:27:01.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:27:01.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:27:01.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:27:01.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:27:01.33#ibcon#enter wrdev, iclass 13, count 2 2006.182.08:27:01.33#ibcon#first serial, iclass 13, count 2 2006.182.08:27:01.33#ibcon#enter sib2, iclass 13, count 2 2006.182.08:27:01.33#ibcon#flushed, iclass 13, count 2 2006.182.08:27:01.33#ibcon#about to write, iclass 13, count 2 2006.182.08:27:01.33#ibcon#wrote, iclass 13, count 2 2006.182.08:27:01.33#ibcon#about to read 3, iclass 13, count 2 2006.182.08:27:01.35#ibcon#read 3, iclass 13, count 2 2006.182.08:27:01.35#ibcon#about to read 4, iclass 13, count 2 2006.182.08:27:01.35#ibcon#read 4, iclass 13, count 2 2006.182.08:27:01.35#ibcon#about to read 5, iclass 13, count 2 2006.182.08:27:01.35#ibcon#read 5, iclass 13, count 2 2006.182.08:27:01.35#ibcon#about to read 6, iclass 13, count 2 2006.182.08:27:01.35#ibcon#read 6, iclass 13, count 2 2006.182.08:27:01.35#ibcon#end of sib2, iclass 13, count 2 2006.182.08:27:01.35#ibcon#*mode == 0, iclass 13, count 2 2006.182.08:27:01.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.182.08:27:01.35#ibcon#[27=AT03-04\r\n] 2006.182.08:27:01.35#ibcon#*before write, iclass 13, count 2 2006.182.08:27:01.35#ibcon#enter sib2, iclass 13, count 2 2006.182.08:27:01.35#ibcon#flushed, iclass 13, count 2 2006.182.08:27:01.35#ibcon#about to write, iclass 13, count 2 2006.182.08:27:01.35#ibcon#wrote, iclass 13, count 2 2006.182.08:27:01.35#ibcon#about to read 3, iclass 13, count 2 2006.182.08:27:01.38#ibcon#read 3, iclass 13, count 2 2006.182.08:27:01.38#ibcon#about to read 4, iclass 13, count 2 2006.182.08:27:01.38#ibcon#read 4, iclass 13, count 2 2006.182.08:27:01.38#ibcon#about to read 5, iclass 13, count 2 2006.182.08:27:01.38#ibcon#read 5, iclass 13, count 2 2006.182.08:27:01.38#ibcon#about to read 6, iclass 13, count 2 2006.182.08:27:01.38#ibcon#read 6, iclass 13, count 2 2006.182.08:27:01.38#ibcon#end of sib2, iclass 13, count 2 2006.182.08:27:01.38#ibcon#*after write, iclass 13, count 2 2006.182.08:27:01.38#ibcon#*before return 0, iclass 13, count 2 2006.182.08:27:01.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:27:01.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.182.08:27:01.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.182.08:27:01.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:27:01.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:27:01.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:27:01.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:27:01.50#ibcon#enter wrdev, iclass 13, count 0 2006.182.08:27:01.50#ibcon#first serial, iclass 13, count 0 2006.182.08:27:01.50#ibcon#enter sib2, iclass 13, count 0 2006.182.08:27:01.50#ibcon#flushed, iclass 13, count 0 2006.182.08:27:01.50#ibcon#about to write, iclass 13, count 0 2006.182.08:27:01.50#ibcon#wrote, iclass 13, count 0 2006.182.08:27:01.50#ibcon#about to read 3, iclass 13, count 0 2006.182.08:27:01.52#ibcon#read 3, iclass 13, count 0 2006.182.08:27:01.52#ibcon#about to read 4, iclass 13, count 0 2006.182.08:27:01.52#ibcon#read 4, iclass 13, count 0 2006.182.08:27:01.52#ibcon#about to read 5, iclass 13, count 0 2006.182.08:27:01.52#ibcon#read 5, iclass 13, count 0 2006.182.08:27:01.52#ibcon#about to read 6, iclass 13, count 0 2006.182.08:27:01.52#ibcon#read 6, iclass 13, count 0 2006.182.08:27:01.52#ibcon#end of sib2, iclass 13, count 0 2006.182.08:27:01.52#ibcon#*mode == 0, iclass 13, count 0 2006.182.08:27:01.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.182.08:27:01.52#ibcon#[27=USB\r\n] 2006.182.08:27:01.52#ibcon#*before write, iclass 13, count 0 2006.182.08:27:01.52#ibcon#enter sib2, iclass 13, count 0 2006.182.08:27:01.52#ibcon#flushed, iclass 13, count 0 2006.182.08:27:01.52#ibcon#about to write, iclass 13, count 0 2006.182.08:27:01.52#ibcon#wrote, iclass 13, count 0 2006.182.08:27:01.52#ibcon#about to read 3, iclass 13, count 0 2006.182.08:27:01.55#ibcon#read 3, iclass 13, count 0 2006.182.08:27:01.55#ibcon#about to read 4, iclass 13, count 0 2006.182.08:27:01.55#ibcon#read 4, iclass 13, count 0 2006.182.08:27:01.55#ibcon#about to read 5, iclass 13, count 0 2006.182.08:27:01.55#ibcon#read 5, iclass 13, count 0 2006.182.08:27:01.55#ibcon#about to read 6, iclass 13, count 0 2006.182.08:27:01.55#ibcon#read 6, iclass 13, count 0 2006.182.08:27:01.55#ibcon#end of sib2, iclass 13, count 0 2006.182.08:27:01.55#ibcon#*after write, iclass 13, count 0 2006.182.08:27:01.55#ibcon#*before return 0, iclass 13, count 0 2006.182.08:27:01.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:27:01.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.182.08:27:01.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.182.08:27:01.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.182.08:27:01.55$vc4f8/vblo=4,712.99 2006.182.08:27:01.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.182.08:27:01.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.182.08:27:01.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:27:01.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:27:01.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:27:01.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:27:01.55#ibcon#enter wrdev, iclass 15, count 0 2006.182.08:27:01.55#ibcon#first serial, iclass 15, count 0 2006.182.08:27:01.55#ibcon#enter sib2, iclass 15, count 0 2006.182.08:27:01.55#ibcon#flushed, iclass 15, count 0 2006.182.08:27:01.55#ibcon#about to write, iclass 15, count 0 2006.182.08:27:01.55#ibcon#wrote, iclass 15, count 0 2006.182.08:27:01.55#ibcon#about to read 3, iclass 15, count 0 2006.182.08:27:01.57#ibcon#read 3, iclass 15, count 0 2006.182.08:27:01.57#ibcon#about to read 4, iclass 15, count 0 2006.182.08:27:01.57#ibcon#read 4, iclass 15, count 0 2006.182.08:27:01.57#ibcon#about to read 5, iclass 15, count 0 2006.182.08:27:01.57#ibcon#read 5, iclass 15, count 0 2006.182.08:27:01.57#ibcon#about to read 6, iclass 15, count 0 2006.182.08:27:01.57#ibcon#read 6, iclass 15, count 0 2006.182.08:27:01.57#ibcon#end of sib2, iclass 15, count 0 2006.182.08:27:01.57#ibcon#*mode == 0, iclass 15, count 0 2006.182.08:27:01.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.182.08:27:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:27:01.57#ibcon#*before write, iclass 15, count 0 2006.182.08:27:01.57#ibcon#enter sib2, iclass 15, count 0 2006.182.08:27:01.57#ibcon#flushed, iclass 15, count 0 2006.182.08:27:01.57#ibcon#about to write, iclass 15, count 0 2006.182.08:27:01.57#ibcon#wrote, iclass 15, count 0 2006.182.08:27:01.57#ibcon#about to read 3, iclass 15, count 0 2006.182.08:27:01.61#ibcon#read 3, iclass 15, count 0 2006.182.08:27:01.61#ibcon#about to read 4, iclass 15, count 0 2006.182.08:27:01.61#ibcon#read 4, iclass 15, count 0 2006.182.08:27:01.61#ibcon#about to read 5, iclass 15, count 0 2006.182.08:27:01.61#ibcon#read 5, iclass 15, count 0 2006.182.08:27:01.61#ibcon#about to read 6, iclass 15, count 0 2006.182.08:27:01.61#ibcon#read 6, iclass 15, count 0 2006.182.08:27:01.61#ibcon#end of sib2, iclass 15, count 0 2006.182.08:27:01.61#ibcon#*after write, iclass 15, count 0 2006.182.08:27:01.61#ibcon#*before return 0, iclass 15, count 0 2006.182.08:27:01.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:27:01.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.182.08:27:01.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.182.08:27:01.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.182.08:27:01.61$vc4f8/vb=4,4 2006.182.08:27:01.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.182.08:27:01.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.182.08:27:01.61#ibcon#ireg 11 cls_cnt 2 2006.182.08:27:01.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:27:01.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:27:01.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:27:01.67#ibcon#enter wrdev, iclass 17, count 2 2006.182.08:27:01.67#ibcon#first serial, iclass 17, count 2 2006.182.08:27:01.67#ibcon#enter sib2, iclass 17, count 2 2006.182.08:27:01.67#ibcon#flushed, iclass 17, count 2 2006.182.08:27:01.67#ibcon#about to write, iclass 17, count 2 2006.182.08:27:01.67#ibcon#wrote, iclass 17, count 2 2006.182.08:27:01.67#ibcon#about to read 3, iclass 17, count 2 2006.182.08:27:01.69#ibcon#read 3, iclass 17, count 2 2006.182.08:27:01.69#ibcon#about to read 4, iclass 17, count 2 2006.182.08:27:01.69#ibcon#read 4, iclass 17, count 2 2006.182.08:27:01.69#ibcon#about to read 5, iclass 17, count 2 2006.182.08:27:01.69#ibcon#read 5, iclass 17, count 2 2006.182.08:27:01.69#ibcon#about to read 6, iclass 17, count 2 2006.182.08:27:01.69#ibcon#read 6, iclass 17, count 2 2006.182.08:27:01.69#ibcon#end of sib2, iclass 17, count 2 2006.182.08:27:01.69#ibcon#*mode == 0, iclass 17, count 2 2006.182.08:27:01.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.182.08:27:01.69#ibcon#[27=AT04-04\r\n] 2006.182.08:27:01.69#ibcon#*before write, iclass 17, count 2 2006.182.08:27:01.69#ibcon#enter sib2, iclass 17, count 2 2006.182.08:27:01.69#ibcon#flushed, iclass 17, count 2 2006.182.08:27:01.69#ibcon#about to write, iclass 17, count 2 2006.182.08:27:01.69#ibcon#wrote, iclass 17, count 2 2006.182.08:27:01.69#ibcon#about to read 3, iclass 17, count 2 2006.182.08:27:01.72#ibcon#read 3, iclass 17, count 2 2006.182.08:27:01.72#ibcon#about to read 4, iclass 17, count 2 2006.182.08:27:01.72#ibcon#read 4, iclass 17, count 2 2006.182.08:27:01.72#ibcon#about to read 5, iclass 17, count 2 2006.182.08:27:01.72#ibcon#read 5, iclass 17, count 2 2006.182.08:27:01.72#ibcon#about to read 6, iclass 17, count 2 2006.182.08:27:01.72#ibcon#read 6, iclass 17, count 2 2006.182.08:27:01.72#ibcon#end of sib2, iclass 17, count 2 2006.182.08:27:01.72#ibcon#*after write, iclass 17, count 2 2006.182.08:27:01.72#ibcon#*before return 0, iclass 17, count 2 2006.182.08:27:01.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:27:01.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.182.08:27:01.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.182.08:27:01.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:27:01.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:27:01.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:27:01.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:27:01.84#ibcon#enter wrdev, iclass 17, count 0 2006.182.08:27:01.84#ibcon#first serial, iclass 17, count 0 2006.182.08:27:01.84#ibcon#enter sib2, iclass 17, count 0 2006.182.08:27:01.84#ibcon#flushed, iclass 17, count 0 2006.182.08:27:01.84#ibcon#about to write, iclass 17, count 0 2006.182.08:27:01.84#ibcon#wrote, iclass 17, count 0 2006.182.08:27:01.84#ibcon#about to read 3, iclass 17, count 0 2006.182.08:27:01.86#ibcon#read 3, iclass 17, count 0 2006.182.08:27:01.86#ibcon#about to read 4, iclass 17, count 0 2006.182.08:27:01.86#ibcon#read 4, iclass 17, count 0 2006.182.08:27:01.86#ibcon#about to read 5, iclass 17, count 0 2006.182.08:27:01.86#ibcon#read 5, iclass 17, count 0 2006.182.08:27:01.86#ibcon#about to read 6, iclass 17, count 0 2006.182.08:27:01.86#ibcon#read 6, iclass 17, count 0 2006.182.08:27:01.86#ibcon#end of sib2, iclass 17, count 0 2006.182.08:27:01.86#ibcon#*mode == 0, iclass 17, count 0 2006.182.08:27:01.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.182.08:27:01.86#ibcon#[27=USB\r\n] 2006.182.08:27:01.86#ibcon#*before write, iclass 17, count 0 2006.182.08:27:01.86#ibcon#enter sib2, iclass 17, count 0 2006.182.08:27:01.86#ibcon#flushed, iclass 17, count 0 2006.182.08:27:01.86#ibcon#about to write, iclass 17, count 0 2006.182.08:27:01.86#ibcon#wrote, iclass 17, count 0 2006.182.08:27:01.86#ibcon#about to read 3, iclass 17, count 0 2006.182.08:27:01.89#ibcon#read 3, iclass 17, count 0 2006.182.08:27:01.89#ibcon#about to read 4, iclass 17, count 0 2006.182.08:27:01.89#ibcon#read 4, iclass 17, count 0 2006.182.08:27:01.89#ibcon#about to read 5, iclass 17, count 0 2006.182.08:27:01.89#ibcon#read 5, iclass 17, count 0 2006.182.08:27:01.89#ibcon#about to read 6, iclass 17, count 0 2006.182.08:27:01.89#ibcon#read 6, iclass 17, count 0 2006.182.08:27:01.89#ibcon#end of sib2, iclass 17, count 0 2006.182.08:27:01.89#ibcon#*after write, iclass 17, count 0 2006.182.08:27:01.89#ibcon#*before return 0, iclass 17, count 0 2006.182.08:27:01.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:27:01.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.182.08:27:01.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.182.08:27:01.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.182.08:27:01.89$vc4f8/vblo=5,744.99 2006.182.08:27:01.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.182.08:27:01.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.182.08:27:01.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:27:01.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:27:01.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:27:01.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:27:01.89#ibcon#enter wrdev, iclass 19, count 0 2006.182.08:27:01.89#ibcon#first serial, iclass 19, count 0 2006.182.08:27:01.89#ibcon#enter sib2, iclass 19, count 0 2006.182.08:27:01.89#ibcon#flushed, iclass 19, count 0 2006.182.08:27:01.89#ibcon#about to write, iclass 19, count 0 2006.182.08:27:01.89#ibcon#wrote, iclass 19, count 0 2006.182.08:27:01.89#ibcon#about to read 3, iclass 19, count 0 2006.182.08:27:01.91#ibcon#read 3, iclass 19, count 0 2006.182.08:27:01.91#ibcon#about to read 4, iclass 19, count 0 2006.182.08:27:01.91#ibcon#read 4, iclass 19, count 0 2006.182.08:27:01.91#ibcon#about to read 5, iclass 19, count 0 2006.182.08:27:01.91#ibcon#read 5, iclass 19, count 0 2006.182.08:27:01.91#ibcon#about to read 6, iclass 19, count 0 2006.182.08:27:01.91#ibcon#read 6, iclass 19, count 0 2006.182.08:27:01.91#ibcon#end of sib2, iclass 19, count 0 2006.182.08:27:01.91#ibcon#*mode == 0, iclass 19, count 0 2006.182.08:27:01.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.182.08:27:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:27:01.91#ibcon#*before write, iclass 19, count 0 2006.182.08:27:01.91#ibcon#enter sib2, iclass 19, count 0 2006.182.08:27:01.91#ibcon#flushed, iclass 19, count 0 2006.182.08:27:01.91#ibcon#about to write, iclass 19, count 0 2006.182.08:27:01.91#ibcon#wrote, iclass 19, count 0 2006.182.08:27:01.91#ibcon#about to read 3, iclass 19, count 0 2006.182.08:27:01.95#ibcon#read 3, iclass 19, count 0 2006.182.08:27:01.95#ibcon#about to read 4, iclass 19, count 0 2006.182.08:27:01.95#ibcon#read 4, iclass 19, count 0 2006.182.08:27:01.95#ibcon#about to read 5, iclass 19, count 0 2006.182.08:27:01.95#ibcon#read 5, iclass 19, count 0 2006.182.08:27:01.95#ibcon#about to read 6, iclass 19, count 0 2006.182.08:27:01.95#ibcon#read 6, iclass 19, count 0 2006.182.08:27:01.95#ibcon#end of sib2, iclass 19, count 0 2006.182.08:27:01.95#ibcon#*after write, iclass 19, count 0 2006.182.08:27:01.95#ibcon#*before return 0, iclass 19, count 0 2006.182.08:27:01.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:27:01.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.182.08:27:01.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.182.08:27:01.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.182.08:27:01.95$vc4f8/vb=5,4 2006.182.08:27:01.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.182.08:27:01.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.182.08:27:01.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:27:01.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:27:02.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:27:02.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:27:02.01#ibcon#enter wrdev, iclass 21, count 2 2006.182.08:27:02.01#ibcon#first serial, iclass 21, count 2 2006.182.08:27:02.01#ibcon#enter sib2, iclass 21, count 2 2006.182.08:27:02.01#ibcon#flushed, iclass 21, count 2 2006.182.08:27:02.01#ibcon#about to write, iclass 21, count 2 2006.182.08:27:02.01#ibcon#wrote, iclass 21, count 2 2006.182.08:27:02.01#ibcon#about to read 3, iclass 21, count 2 2006.182.08:27:02.03#ibcon#read 3, iclass 21, count 2 2006.182.08:27:02.03#ibcon#about to read 4, iclass 21, count 2 2006.182.08:27:02.03#ibcon#read 4, iclass 21, count 2 2006.182.08:27:02.03#ibcon#about to read 5, iclass 21, count 2 2006.182.08:27:02.03#ibcon#read 5, iclass 21, count 2 2006.182.08:27:02.03#ibcon#about to read 6, iclass 21, count 2 2006.182.08:27:02.03#ibcon#read 6, iclass 21, count 2 2006.182.08:27:02.03#ibcon#end of sib2, iclass 21, count 2 2006.182.08:27:02.03#ibcon#*mode == 0, iclass 21, count 2 2006.182.08:27:02.03#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.182.08:27:02.03#ibcon#[27=AT05-04\r\n] 2006.182.08:27:02.03#ibcon#*before write, iclass 21, count 2 2006.182.08:27:02.03#ibcon#enter sib2, iclass 21, count 2 2006.182.08:27:02.03#ibcon#flushed, iclass 21, count 2 2006.182.08:27:02.03#ibcon#about to write, iclass 21, count 2 2006.182.08:27:02.03#ibcon#wrote, iclass 21, count 2 2006.182.08:27:02.03#ibcon#about to read 3, iclass 21, count 2 2006.182.08:27:02.06#ibcon#read 3, iclass 21, count 2 2006.182.08:27:02.06#ibcon#about to read 4, iclass 21, count 2 2006.182.08:27:02.06#ibcon#read 4, iclass 21, count 2 2006.182.08:27:02.06#ibcon#about to read 5, iclass 21, count 2 2006.182.08:27:02.06#ibcon#read 5, iclass 21, count 2 2006.182.08:27:02.06#ibcon#about to read 6, iclass 21, count 2 2006.182.08:27:02.06#ibcon#read 6, iclass 21, count 2 2006.182.08:27:02.06#ibcon#end of sib2, iclass 21, count 2 2006.182.08:27:02.06#ibcon#*after write, iclass 21, count 2 2006.182.08:27:02.06#ibcon#*before return 0, iclass 21, count 2 2006.182.08:27:02.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:27:02.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.182.08:27:02.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.182.08:27:02.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:27:02.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:27:02.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:27:02.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:27:02.18#ibcon#enter wrdev, iclass 21, count 0 2006.182.08:27:02.18#ibcon#first serial, iclass 21, count 0 2006.182.08:27:02.18#ibcon#enter sib2, iclass 21, count 0 2006.182.08:27:02.18#ibcon#flushed, iclass 21, count 0 2006.182.08:27:02.18#ibcon#about to write, iclass 21, count 0 2006.182.08:27:02.18#ibcon#wrote, iclass 21, count 0 2006.182.08:27:02.18#ibcon#about to read 3, iclass 21, count 0 2006.182.08:27:02.20#ibcon#read 3, iclass 21, count 0 2006.182.08:27:02.20#ibcon#about to read 4, iclass 21, count 0 2006.182.08:27:02.20#ibcon#read 4, iclass 21, count 0 2006.182.08:27:02.20#ibcon#about to read 5, iclass 21, count 0 2006.182.08:27:02.20#ibcon#read 5, iclass 21, count 0 2006.182.08:27:02.20#ibcon#about to read 6, iclass 21, count 0 2006.182.08:27:02.20#ibcon#read 6, iclass 21, count 0 2006.182.08:27:02.20#ibcon#end of sib2, iclass 21, count 0 2006.182.08:27:02.20#ibcon#*mode == 0, iclass 21, count 0 2006.182.08:27:02.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.182.08:27:02.20#ibcon#[27=USB\r\n] 2006.182.08:27:02.20#ibcon#*before write, iclass 21, count 0 2006.182.08:27:02.20#ibcon#enter sib2, iclass 21, count 0 2006.182.08:27:02.20#ibcon#flushed, iclass 21, count 0 2006.182.08:27:02.20#ibcon#about to write, iclass 21, count 0 2006.182.08:27:02.20#ibcon#wrote, iclass 21, count 0 2006.182.08:27:02.20#ibcon#about to read 3, iclass 21, count 0 2006.182.08:27:02.23#ibcon#read 3, iclass 21, count 0 2006.182.08:27:02.23#ibcon#about to read 4, iclass 21, count 0 2006.182.08:27:02.23#ibcon#read 4, iclass 21, count 0 2006.182.08:27:02.23#ibcon#about to read 5, iclass 21, count 0 2006.182.08:27:02.23#ibcon#read 5, iclass 21, count 0 2006.182.08:27:02.23#ibcon#about to read 6, iclass 21, count 0 2006.182.08:27:02.23#ibcon#read 6, iclass 21, count 0 2006.182.08:27:02.23#ibcon#end of sib2, iclass 21, count 0 2006.182.08:27:02.23#ibcon#*after write, iclass 21, count 0 2006.182.08:27:02.23#ibcon#*before return 0, iclass 21, count 0 2006.182.08:27:02.23#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:27:02.23#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.182.08:27:02.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.182.08:27:02.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.182.08:27:02.23$vc4f8/vblo=6,752.99 2006.182.08:27:02.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.182.08:27:02.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.182.08:27:02.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:27:02.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:27:02.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:27:02.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:27:02.23#ibcon#enter wrdev, iclass 23, count 0 2006.182.08:27:02.23#ibcon#first serial, iclass 23, count 0 2006.182.08:27:02.23#ibcon#enter sib2, iclass 23, count 0 2006.182.08:27:02.23#ibcon#flushed, iclass 23, count 0 2006.182.08:27:02.23#ibcon#about to write, iclass 23, count 0 2006.182.08:27:02.23#ibcon#wrote, iclass 23, count 0 2006.182.08:27:02.23#ibcon#about to read 3, iclass 23, count 0 2006.182.08:27:02.25#ibcon#read 3, iclass 23, count 0 2006.182.08:27:02.25#ibcon#about to read 4, iclass 23, count 0 2006.182.08:27:02.25#ibcon#read 4, iclass 23, count 0 2006.182.08:27:02.25#ibcon#about to read 5, iclass 23, count 0 2006.182.08:27:02.25#ibcon#read 5, iclass 23, count 0 2006.182.08:27:02.25#ibcon#about to read 6, iclass 23, count 0 2006.182.08:27:02.25#ibcon#read 6, iclass 23, count 0 2006.182.08:27:02.25#ibcon#end of sib2, iclass 23, count 0 2006.182.08:27:02.25#ibcon#*mode == 0, iclass 23, count 0 2006.182.08:27:02.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.182.08:27:02.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:27:02.25#ibcon#*before write, iclass 23, count 0 2006.182.08:27:02.25#ibcon#enter sib2, iclass 23, count 0 2006.182.08:27:02.25#ibcon#flushed, iclass 23, count 0 2006.182.08:27:02.25#ibcon#about to write, iclass 23, count 0 2006.182.08:27:02.25#ibcon#wrote, iclass 23, count 0 2006.182.08:27:02.25#ibcon#about to read 3, iclass 23, count 0 2006.182.08:27:02.29#ibcon#read 3, iclass 23, count 0 2006.182.08:27:02.29#ibcon#about to read 4, iclass 23, count 0 2006.182.08:27:02.29#ibcon#read 4, iclass 23, count 0 2006.182.08:27:02.29#ibcon#about to read 5, iclass 23, count 0 2006.182.08:27:02.29#ibcon#read 5, iclass 23, count 0 2006.182.08:27:02.29#ibcon#about to read 6, iclass 23, count 0 2006.182.08:27:02.29#ibcon#read 6, iclass 23, count 0 2006.182.08:27:02.29#ibcon#end of sib2, iclass 23, count 0 2006.182.08:27:02.29#ibcon#*after write, iclass 23, count 0 2006.182.08:27:02.29#ibcon#*before return 0, iclass 23, count 0 2006.182.08:27:02.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:27:02.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.182.08:27:02.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.182.08:27:02.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.182.08:27:02.29$vc4f8/vb=6,4 2006.182.08:27:02.29#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.182.08:27:02.29#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.182.08:27:02.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:27:02.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:27:02.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:27:02.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:27:02.35#ibcon#enter wrdev, iclass 25, count 2 2006.182.08:27:02.35#ibcon#first serial, iclass 25, count 2 2006.182.08:27:02.35#ibcon#enter sib2, iclass 25, count 2 2006.182.08:27:02.35#ibcon#flushed, iclass 25, count 2 2006.182.08:27:02.35#ibcon#about to write, iclass 25, count 2 2006.182.08:27:02.35#ibcon#wrote, iclass 25, count 2 2006.182.08:27:02.35#ibcon#about to read 3, iclass 25, count 2 2006.182.08:27:02.37#ibcon#read 3, iclass 25, count 2 2006.182.08:27:02.37#ibcon#about to read 4, iclass 25, count 2 2006.182.08:27:02.37#ibcon#read 4, iclass 25, count 2 2006.182.08:27:02.37#ibcon#about to read 5, iclass 25, count 2 2006.182.08:27:02.37#ibcon#read 5, iclass 25, count 2 2006.182.08:27:02.37#ibcon#about to read 6, iclass 25, count 2 2006.182.08:27:02.37#ibcon#read 6, iclass 25, count 2 2006.182.08:27:02.37#ibcon#end of sib2, iclass 25, count 2 2006.182.08:27:02.37#ibcon#*mode == 0, iclass 25, count 2 2006.182.08:27:02.37#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.182.08:27:02.37#ibcon#[27=AT06-04\r\n] 2006.182.08:27:02.37#ibcon#*before write, iclass 25, count 2 2006.182.08:27:02.37#ibcon#enter sib2, iclass 25, count 2 2006.182.08:27:02.37#ibcon#flushed, iclass 25, count 2 2006.182.08:27:02.37#ibcon#about to write, iclass 25, count 2 2006.182.08:27:02.37#ibcon#wrote, iclass 25, count 2 2006.182.08:27:02.37#ibcon#about to read 3, iclass 25, count 2 2006.182.08:27:02.40#ibcon#read 3, iclass 25, count 2 2006.182.08:27:02.40#ibcon#about to read 4, iclass 25, count 2 2006.182.08:27:02.40#ibcon#read 4, iclass 25, count 2 2006.182.08:27:02.40#ibcon#about to read 5, iclass 25, count 2 2006.182.08:27:02.40#ibcon#read 5, iclass 25, count 2 2006.182.08:27:02.40#ibcon#about to read 6, iclass 25, count 2 2006.182.08:27:02.40#ibcon#read 6, iclass 25, count 2 2006.182.08:27:02.40#ibcon#end of sib2, iclass 25, count 2 2006.182.08:27:02.40#ibcon#*after write, iclass 25, count 2 2006.182.08:27:02.40#ibcon#*before return 0, iclass 25, count 2 2006.182.08:27:02.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:27:02.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.182.08:27:02.40#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.182.08:27:02.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:27:02.40#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:27:02.52#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:27:02.52#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:27:02.52#ibcon#enter wrdev, iclass 25, count 0 2006.182.08:27:02.52#ibcon#first serial, iclass 25, count 0 2006.182.08:27:02.52#ibcon#enter sib2, iclass 25, count 0 2006.182.08:27:02.52#ibcon#flushed, iclass 25, count 0 2006.182.08:27:02.52#ibcon#about to write, iclass 25, count 0 2006.182.08:27:02.52#ibcon#wrote, iclass 25, count 0 2006.182.08:27:02.52#ibcon#about to read 3, iclass 25, count 0 2006.182.08:27:02.54#ibcon#read 3, iclass 25, count 0 2006.182.08:27:02.54#ibcon#about to read 4, iclass 25, count 0 2006.182.08:27:02.54#ibcon#read 4, iclass 25, count 0 2006.182.08:27:02.54#ibcon#about to read 5, iclass 25, count 0 2006.182.08:27:02.54#ibcon#read 5, iclass 25, count 0 2006.182.08:27:02.54#ibcon#about to read 6, iclass 25, count 0 2006.182.08:27:02.54#ibcon#read 6, iclass 25, count 0 2006.182.08:27:02.54#ibcon#end of sib2, iclass 25, count 0 2006.182.08:27:02.54#ibcon#*mode == 0, iclass 25, count 0 2006.182.08:27:02.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.182.08:27:02.54#ibcon#[27=USB\r\n] 2006.182.08:27:02.54#ibcon#*before write, iclass 25, count 0 2006.182.08:27:02.54#ibcon#enter sib2, iclass 25, count 0 2006.182.08:27:02.54#ibcon#flushed, iclass 25, count 0 2006.182.08:27:02.54#ibcon#about to write, iclass 25, count 0 2006.182.08:27:02.54#ibcon#wrote, iclass 25, count 0 2006.182.08:27:02.54#ibcon#about to read 3, iclass 25, count 0 2006.182.08:27:02.57#ibcon#read 3, iclass 25, count 0 2006.182.08:27:02.57#ibcon#about to read 4, iclass 25, count 0 2006.182.08:27:02.57#ibcon#read 4, iclass 25, count 0 2006.182.08:27:02.57#ibcon#about to read 5, iclass 25, count 0 2006.182.08:27:02.57#ibcon#read 5, iclass 25, count 0 2006.182.08:27:02.57#ibcon#about to read 6, iclass 25, count 0 2006.182.08:27:02.57#ibcon#read 6, iclass 25, count 0 2006.182.08:27:02.57#ibcon#end of sib2, iclass 25, count 0 2006.182.08:27:02.57#ibcon#*after write, iclass 25, count 0 2006.182.08:27:02.57#ibcon#*before return 0, iclass 25, count 0 2006.182.08:27:02.57#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:27:02.57#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.182.08:27:02.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.182.08:27:02.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.182.08:27:02.57$vc4f8/vabw=wide 2006.182.08:27:02.57#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.182.08:27:02.57#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.182.08:27:02.57#ibcon#ireg 8 cls_cnt 0 2006.182.08:27:02.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:27:02.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:27:02.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:27:02.57#ibcon#enter wrdev, iclass 27, count 0 2006.182.08:27:02.57#ibcon#first serial, iclass 27, count 0 2006.182.08:27:02.57#ibcon#enter sib2, iclass 27, count 0 2006.182.08:27:02.57#ibcon#flushed, iclass 27, count 0 2006.182.08:27:02.57#ibcon#about to write, iclass 27, count 0 2006.182.08:27:02.57#ibcon#wrote, iclass 27, count 0 2006.182.08:27:02.57#ibcon#about to read 3, iclass 27, count 0 2006.182.08:27:02.59#ibcon#read 3, iclass 27, count 0 2006.182.08:27:02.59#ibcon#about to read 4, iclass 27, count 0 2006.182.08:27:02.59#ibcon#read 4, iclass 27, count 0 2006.182.08:27:02.59#ibcon#about to read 5, iclass 27, count 0 2006.182.08:27:02.59#ibcon#read 5, iclass 27, count 0 2006.182.08:27:02.59#ibcon#about to read 6, iclass 27, count 0 2006.182.08:27:02.59#ibcon#read 6, iclass 27, count 0 2006.182.08:27:02.59#ibcon#end of sib2, iclass 27, count 0 2006.182.08:27:02.59#ibcon#*mode == 0, iclass 27, count 0 2006.182.08:27:02.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.182.08:27:02.59#ibcon#[25=BW32\r\n] 2006.182.08:27:02.59#ibcon#*before write, iclass 27, count 0 2006.182.08:27:02.59#ibcon#enter sib2, iclass 27, count 0 2006.182.08:27:02.59#ibcon#flushed, iclass 27, count 0 2006.182.08:27:02.59#ibcon#about to write, iclass 27, count 0 2006.182.08:27:02.59#ibcon#wrote, iclass 27, count 0 2006.182.08:27:02.59#ibcon#about to read 3, iclass 27, count 0 2006.182.08:27:02.62#ibcon#read 3, iclass 27, count 0 2006.182.08:27:02.62#ibcon#about to read 4, iclass 27, count 0 2006.182.08:27:02.62#ibcon#read 4, iclass 27, count 0 2006.182.08:27:02.62#ibcon#about to read 5, iclass 27, count 0 2006.182.08:27:02.62#ibcon#read 5, iclass 27, count 0 2006.182.08:27:02.62#ibcon#about to read 6, iclass 27, count 0 2006.182.08:27:02.62#ibcon#read 6, iclass 27, count 0 2006.182.08:27:02.62#ibcon#end of sib2, iclass 27, count 0 2006.182.08:27:02.62#ibcon#*after write, iclass 27, count 0 2006.182.08:27:02.62#ibcon#*before return 0, iclass 27, count 0 2006.182.08:27:02.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:27:02.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.182.08:27:02.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.182.08:27:02.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.182.08:27:02.62$vc4f8/vbbw=wide 2006.182.08:27:02.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.182.08:27:02.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.182.08:27:02.62#ibcon#ireg 8 cls_cnt 0 2006.182.08:27:02.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:27:02.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:27:02.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:27:02.69#ibcon#enter wrdev, iclass 29, count 0 2006.182.08:27:02.69#ibcon#first serial, iclass 29, count 0 2006.182.08:27:02.69#ibcon#enter sib2, iclass 29, count 0 2006.182.08:27:02.69#ibcon#flushed, iclass 29, count 0 2006.182.08:27:02.69#ibcon#about to write, iclass 29, count 0 2006.182.08:27:02.69#ibcon#wrote, iclass 29, count 0 2006.182.08:27:02.69#ibcon#about to read 3, iclass 29, count 0 2006.182.08:27:02.71#ibcon#read 3, iclass 29, count 0 2006.182.08:27:02.71#ibcon#about to read 4, iclass 29, count 0 2006.182.08:27:02.71#ibcon#read 4, iclass 29, count 0 2006.182.08:27:02.71#ibcon#about to read 5, iclass 29, count 0 2006.182.08:27:02.71#ibcon#read 5, iclass 29, count 0 2006.182.08:27:02.71#ibcon#about to read 6, iclass 29, count 0 2006.182.08:27:02.71#ibcon#read 6, iclass 29, count 0 2006.182.08:27:02.71#ibcon#end of sib2, iclass 29, count 0 2006.182.08:27:02.71#ibcon#*mode == 0, iclass 29, count 0 2006.182.08:27:02.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.182.08:27:02.71#ibcon#[27=BW32\r\n] 2006.182.08:27:02.71#ibcon#*before write, iclass 29, count 0 2006.182.08:27:02.71#ibcon#enter sib2, iclass 29, count 0 2006.182.08:27:02.71#ibcon#flushed, iclass 29, count 0 2006.182.08:27:02.71#ibcon#about to write, iclass 29, count 0 2006.182.08:27:02.71#ibcon#wrote, iclass 29, count 0 2006.182.08:27:02.71#ibcon#about to read 3, iclass 29, count 0 2006.182.08:27:02.74#ibcon#read 3, iclass 29, count 0 2006.182.08:27:02.74#ibcon#about to read 4, iclass 29, count 0 2006.182.08:27:02.74#ibcon#read 4, iclass 29, count 0 2006.182.08:27:02.74#ibcon#about to read 5, iclass 29, count 0 2006.182.08:27:02.74#ibcon#read 5, iclass 29, count 0 2006.182.08:27:02.74#ibcon#about to read 6, iclass 29, count 0 2006.182.08:27:02.74#ibcon#read 6, iclass 29, count 0 2006.182.08:27:02.74#ibcon#end of sib2, iclass 29, count 0 2006.182.08:27:02.74#ibcon#*after write, iclass 29, count 0 2006.182.08:27:02.74#ibcon#*before return 0, iclass 29, count 0 2006.182.08:27:02.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:27:02.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.182.08:27:02.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.182.08:27:02.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.182.08:27:02.74$4f8m12a/ifd4f 2006.182.08:27:02.74$ifd4f/lo= 2006.182.08:27:02.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:27:02.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:27:02.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:27:02.74$ifd4f/patch= 2006.182.08:27:02.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:27:02.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:27:02.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:27:02.74$4f8m12a/"form=m,16.000,1:2 2006.182.08:27:02.74$4f8m12a/"tpicd 2006.182.08:27:02.74$4f8m12a/echo=off 2006.182.08:27:02.74$4f8m12a/xlog=off 2006.182.08:27:02.74:!2006.182.08:28:10 2006.182.08:27:49.13#trakl#Source acquired 2006.182.08:27:51.13#flagr#flagr/antenna,acquired 2006.182.08:28:10.00:preob 2006.182.08:28:10.13/onsource/TRACKING 2006.182.08:28:10.13:!2006.182.08:28:20 2006.182.08:28:20.00:data_valid=on 2006.182.08:28:20.00:midob 2006.182.08:28:21.13/onsource/TRACKING 2006.182.08:28:21.13/wx/27.61,1002.9,80 2006.182.08:28:21.20/cable/+6.4635E-03 2006.182.08:28:22.29/va/01,08,usb,yes,29,31 2006.182.08:28:22.29/va/02,07,usb,yes,29,31 2006.182.08:28:22.29/va/03,06,usb,yes,31,31 2006.182.08:28:22.29/va/04,07,usb,yes,30,32 2006.182.08:28:22.29/va/05,07,usb,yes,31,33 2006.182.08:28:22.29/va/06,06,usb,yes,30,30 2006.182.08:28:22.29/va/07,06,usb,yes,31,31 2006.182.08:28:22.29/va/08,07,usb,yes,29,29 2006.182.08:28:22.52/valo/01,532.99,yes,locked 2006.182.08:28:22.52/valo/02,572.99,yes,locked 2006.182.08:28:22.52/valo/03,672.99,yes,locked 2006.182.08:28:22.52/valo/04,832.99,yes,locked 2006.182.08:28:22.52/valo/05,652.99,yes,locked 2006.182.08:28:22.52/valo/06,772.99,yes,locked 2006.182.08:28:22.52/valo/07,832.99,yes,locked 2006.182.08:28:22.52/valo/08,852.99,yes,locked 2006.182.08:28:23.61/vb/01,04,usb,yes,29,28 2006.182.08:28:23.61/vb/02,04,usb,yes,31,32 2006.182.08:28:23.61/vb/03,04,usb,yes,27,31 2006.182.08:28:23.61/vb/04,04,usb,yes,28,29 2006.182.08:28:23.61/vb/05,04,usb,yes,27,31 2006.182.08:28:23.61/vb/06,04,usb,yes,28,31 2006.182.08:28:23.61/vb/07,04,usb,yes,30,30 2006.182.08:28:23.61/vb/08,04,usb,yes,28,31 2006.182.08:28:23.84/vblo/01,632.99,yes,locked 2006.182.08:28:23.84/vblo/02,640.99,yes,locked 2006.182.08:28:23.84/vblo/03,656.99,yes,locked 2006.182.08:28:23.84/vblo/04,712.99,yes,locked 2006.182.08:28:23.84/vblo/05,744.99,yes,locked 2006.182.08:28:23.84/vblo/06,752.99,yes,locked 2006.182.08:28:23.84/vblo/07,734.99,yes,locked 2006.182.08:28:23.84/vblo/08,744.99,yes,locked 2006.182.08:28:23.99/vabw/8 2006.182.08:28:24.14/vbbw/8 2006.182.08:28:24.23/xfe/off,on,15.0 2006.182.08:28:24.60/ifatt/23,28,28,28 2006.182.08:28:25.08/fmout-gps/S +3.48E-07 2006.182.08:28:25.12:!2006.182.08:29:20 2006.182.08:29:20.00:data_valid=off 2006.182.08:29:20.00:postob 2006.182.08:29:20.18/cable/+6.4619E-03 2006.182.08:29:20.18/wx/27.59,1002.9,80 2006.182.08:29:21.08/fmout-gps/S +3.48E-07 2006.182.08:29:21.08:scan_name=182-0830,k06182,60 2006.182.08:29:21.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.182.08:29:21.13#flagr#flagr/antenna,new-source 2006.182.08:29:22.13:checkk5 2006.182.08:29:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.182.08:29:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.182.08:29:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.182.08:29:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.182.08:29:24.01/chk_obsdata//k5ts1/T1820828??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:29:24.38/chk_obsdata//k5ts2/T1820828??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:29:24.75/chk_obsdata//k5ts3/T1820828??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:29:25.11/chk_obsdata//k5ts4/T1820828??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.182.08:29:25.81/k5log//k5ts1_log_newline 2006.182.08:29:26.50/k5log//k5ts2_log_newline 2006.182.08:29:27.19/k5log//k5ts3_log_newline 2006.182.08:29:27.87/k5log//k5ts4_log_newline 2006.182.08:29:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:29:27.90:4f8m12a=3 2006.182.08:29:27.90$4f8m12a/echo=on 2006.182.08:29:27.90$4f8m12a/pcalon 2006.182.08:29:27.90$pcalon/"no phase cal control is implemented here 2006.182.08:29:27.90$4f8m12a/"tpicd=stop 2006.182.08:29:27.90$4f8m12a/vc4f8 2006.182.08:29:27.90$vc4f8/valo=1,532.99 2006.182.08:29:27.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.08:29:27.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.08:29:27.90#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:27.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:27.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:27.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:27.90#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:29:27.90#ibcon#first serial, iclass 16, count 0 2006.182.08:29:27.90#ibcon#enter sib2, iclass 16, count 0 2006.182.08:29:27.90#ibcon#flushed, iclass 16, count 0 2006.182.08:29:27.90#ibcon#about to write, iclass 16, count 0 2006.182.08:29:27.90#ibcon#wrote, iclass 16, count 0 2006.182.08:29:27.90#ibcon#about to read 3, iclass 16, count 0 2006.182.08:29:27.94#ibcon#read 3, iclass 16, count 0 2006.182.08:29:27.94#ibcon#about to read 4, iclass 16, count 0 2006.182.08:29:27.94#ibcon#read 4, iclass 16, count 0 2006.182.08:29:27.94#ibcon#about to read 5, iclass 16, count 0 2006.182.08:29:27.94#ibcon#read 5, iclass 16, count 0 2006.182.08:29:27.94#ibcon#about to read 6, iclass 16, count 0 2006.182.08:29:27.94#ibcon#read 6, iclass 16, count 0 2006.182.08:29:27.94#ibcon#end of sib2, iclass 16, count 0 2006.182.08:29:27.94#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:29:27.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:29:27.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.182.08:29:27.94#ibcon#*before write, iclass 16, count 0 2006.182.08:29:27.94#ibcon#enter sib2, iclass 16, count 0 2006.182.08:29:27.94#ibcon#flushed, iclass 16, count 0 2006.182.08:29:27.94#ibcon#about to write, iclass 16, count 0 2006.182.08:29:27.94#ibcon#wrote, iclass 16, count 0 2006.182.08:29:27.94#ibcon#about to read 3, iclass 16, count 0 2006.182.08:29:27.99#ibcon#read 3, iclass 16, count 0 2006.182.08:29:27.99#ibcon#about to read 4, iclass 16, count 0 2006.182.08:29:27.99#ibcon#read 4, iclass 16, count 0 2006.182.08:29:27.99#ibcon#about to read 5, iclass 16, count 0 2006.182.08:29:27.99#ibcon#read 5, iclass 16, count 0 2006.182.08:29:27.99#ibcon#about to read 6, iclass 16, count 0 2006.182.08:29:27.99#ibcon#read 6, iclass 16, count 0 2006.182.08:29:27.99#ibcon#end of sib2, iclass 16, count 0 2006.182.08:29:27.99#ibcon#*after write, iclass 16, count 0 2006.182.08:29:27.99#ibcon#*before return 0, iclass 16, count 0 2006.182.08:29:27.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:27.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:27.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:29:27.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:29:27.99$vc4f8/va=1,8 2006.182.08:29:27.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.08:29:27.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.08:29:27.99#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:27.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:27.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:27.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:27.99#ibcon#enter wrdev, iclass 18, count 2 2006.182.08:29:27.99#ibcon#first serial, iclass 18, count 2 2006.182.08:29:27.99#ibcon#enter sib2, iclass 18, count 2 2006.182.08:29:27.99#ibcon#flushed, iclass 18, count 2 2006.182.08:29:27.99#ibcon#about to write, iclass 18, count 2 2006.182.08:29:27.99#ibcon#wrote, iclass 18, count 2 2006.182.08:29:27.99#ibcon#about to read 3, iclass 18, count 2 2006.182.08:29:28.01#ibcon#read 3, iclass 18, count 2 2006.182.08:29:28.01#ibcon#about to read 4, iclass 18, count 2 2006.182.08:29:28.01#ibcon#read 4, iclass 18, count 2 2006.182.08:29:28.01#ibcon#about to read 5, iclass 18, count 2 2006.182.08:29:28.01#ibcon#read 5, iclass 18, count 2 2006.182.08:29:28.01#ibcon#about to read 6, iclass 18, count 2 2006.182.08:29:28.01#ibcon#read 6, iclass 18, count 2 2006.182.08:29:28.01#ibcon#end of sib2, iclass 18, count 2 2006.182.08:29:28.01#ibcon#*mode == 0, iclass 18, count 2 2006.182.08:29:28.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.08:29:28.01#ibcon#[25=AT01-08\r\n] 2006.182.08:29:28.01#ibcon#*before write, iclass 18, count 2 2006.182.08:29:28.01#ibcon#enter sib2, iclass 18, count 2 2006.182.08:29:28.01#ibcon#flushed, iclass 18, count 2 2006.182.08:29:28.01#ibcon#about to write, iclass 18, count 2 2006.182.08:29:28.01#ibcon#wrote, iclass 18, count 2 2006.182.08:29:28.01#ibcon#about to read 3, iclass 18, count 2 2006.182.08:29:28.04#ibcon#read 3, iclass 18, count 2 2006.182.08:29:28.04#ibcon#about to read 4, iclass 18, count 2 2006.182.08:29:28.04#ibcon#read 4, iclass 18, count 2 2006.182.08:29:28.04#ibcon#about to read 5, iclass 18, count 2 2006.182.08:29:28.04#ibcon#read 5, iclass 18, count 2 2006.182.08:29:28.04#ibcon#about to read 6, iclass 18, count 2 2006.182.08:29:28.04#ibcon#read 6, iclass 18, count 2 2006.182.08:29:28.04#ibcon#end of sib2, iclass 18, count 2 2006.182.08:29:28.04#ibcon#*after write, iclass 18, count 2 2006.182.08:29:28.04#ibcon#*before return 0, iclass 18, count 2 2006.182.08:29:28.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:28.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:28.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.08:29:28.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:28.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:28.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:28.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:28.16#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:29:28.16#ibcon#first serial, iclass 18, count 0 2006.182.08:29:28.16#ibcon#enter sib2, iclass 18, count 0 2006.182.08:29:28.16#ibcon#flushed, iclass 18, count 0 2006.182.08:29:28.16#ibcon#about to write, iclass 18, count 0 2006.182.08:29:28.16#ibcon#wrote, iclass 18, count 0 2006.182.08:29:28.16#ibcon#about to read 3, iclass 18, count 0 2006.182.08:29:28.18#ibcon#read 3, iclass 18, count 0 2006.182.08:29:28.18#ibcon#about to read 4, iclass 18, count 0 2006.182.08:29:28.18#ibcon#read 4, iclass 18, count 0 2006.182.08:29:28.18#ibcon#about to read 5, iclass 18, count 0 2006.182.08:29:28.18#ibcon#read 5, iclass 18, count 0 2006.182.08:29:28.18#ibcon#about to read 6, iclass 18, count 0 2006.182.08:29:28.18#ibcon#read 6, iclass 18, count 0 2006.182.08:29:28.18#ibcon#end of sib2, iclass 18, count 0 2006.182.08:29:28.18#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:29:28.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:29:28.18#ibcon#[25=USB\r\n] 2006.182.08:29:28.18#ibcon#*before write, iclass 18, count 0 2006.182.08:29:28.18#ibcon#enter sib2, iclass 18, count 0 2006.182.08:29:28.18#ibcon#flushed, iclass 18, count 0 2006.182.08:29:28.18#ibcon#about to write, iclass 18, count 0 2006.182.08:29:28.18#ibcon#wrote, iclass 18, count 0 2006.182.08:29:28.18#ibcon#about to read 3, iclass 18, count 0 2006.182.08:29:28.21#ibcon#read 3, iclass 18, count 0 2006.182.08:29:28.21#ibcon#about to read 4, iclass 18, count 0 2006.182.08:29:28.21#ibcon#read 4, iclass 18, count 0 2006.182.08:29:28.21#ibcon#about to read 5, iclass 18, count 0 2006.182.08:29:28.21#ibcon#read 5, iclass 18, count 0 2006.182.08:29:28.21#ibcon#about to read 6, iclass 18, count 0 2006.182.08:29:28.21#ibcon#read 6, iclass 18, count 0 2006.182.08:29:28.21#ibcon#end of sib2, iclass 18, count 0 2006.182.08:29:28.21#ibcon#*after write, iclass 18, count 0 2006.182.08:29:28.21#ibcon#*before return 0, iclass 18, count 0 2006.182.08:29:28.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:28.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:28.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:29:28.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:29:28.21$vc4f8/valo=2,572.99 2006.182.08:29:28.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.08:29:28.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.08:29:28.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:28.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:28.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:28.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:28.21#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:29:28.21#ibcon#first serial, iclass 20, count 0 2006.182.08:29:28.21#ibcon#enter sib2, iclass 20, count 0 2006.182.08:29:28.21#ibcon#flushed, iclass 20, count 0 2006.182.08:29:28.21#ibcon#about to write, iclass 20, count 0 2006.182.08:29:28.21#ibcon#wrote, iclass 20, count 0 2006.182.08:29:28.21#ibcon#about to read 3, iclass 20, count 0 2006.182.08:29:28.23#ibcon#read 3, iclass 20, count 0 2006.182.08:29:28.23#ibcon#about to read 4, iclass 20, count 0 2006.182.08:29:28.23#ibcon#read 4, iclass 20, count 0 2006.182.08:29:28.23#ibcon#about to read 5, iclass 20, count 0 2006.182.08:29:28.23#ibcon#read 5, iclass 20, count 0 2006.182.08:29:28.23#ibcon#about to read 6, iclass 20, count 0 2006.182.08:29:28.23#ibcon#read 6, iclass 20, count 0 2006.182.08:29:28.23#ibcon#end of sib2, iclass 20, count 0 2006.182.08:29:28.23#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:29:28.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:29:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.182.08:29:28.23#ibcon#*before write, iclass 20, count 0 2006.182.08:29:28.23#ibcon#enter sib2, iclass 20, count 0 2006.182.08:29:28.23#ibcon#flushed, iclass 20, count 0 2006.182.08:29:28.23#ibcon#about to write, iclass 20, count 0 2006.182.08:29:28.23#ibcon#wrote, iclass 20, count 0 2006.182.08:29:28.23#ibcon#about to read 3, iclass 20, count 0 2006.182.08:29:28.27#ibcon#read 3, iclass 20, count 0 2006.182.08:29:28.27#ibcon#about to read 4, iclass 20, count 0 2006.182.08:29:28.27#ibcon#read 4, iclass 20, count 0 2006.182.08:29:28.27#ibcon#about to read 5, iclass 20, count 0 2006.182.08:29:28.27#ibcon#read 5, iclass 20, count 0 2006.182.08:29:28.27#ibcon#about to read 6, iclass 20, count 0 2006.182.08:29:28.27#ibcon#read 6, iclass 20, count 0 2006.182.08:29:28.27#ibcon#end of sib2, iclass 20, count 0 2006.182.08:29:28.27#ibcon#*after write, iclass 20, count 0 2006.182.08:29:28.27#ibcon#*before return 0, iclass 20, count 0 2006.182.08:29:28.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:28.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:28.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:29:28.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:29:28.27$vc4f8/va=2,7 2006.182.08:29:28.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.08:29:28.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.08:29:28.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:28.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:28.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:28.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:28.33#ibcon#enter wrdev, iclass 22, count 2 2006.182.08:29:28.33#ibcon#first serial, iclass 22, count 2 2006.182.08:29:28.33#ibcon#enter sib2, iclass 22, count 2 2006.182.08:29:28.33#ibcon#flushed, iclass 22, count 2 2006.182.08:29:28.33#ibcon#about to write, iclass 22, count 2 2006.182.08:29:28.33#ibcon#wrote, iclass 22, count 2 2006.182.08:29:28.33#ibcon#about to read 3, iclass 22, count 2 2006.182.08:29:28.35#ibcon#read 3, iclass 22, count 2 2006.182.08:29:28.35#ibcon#about to read 4, iclass 22, count 2 2006.182.08:29:28.35#ibcon#read 4, iclass 22, count 2 2006.182.08:29:28.35#ibcon#about to read 5, iclass 22, count 2 2006.182.08:29:28.35#ibcon#read 5, iclass 22, count 2 2006.182.08:29:28.35#ibcon#about to read 6, iclass 22, count 2 2006.182.08:29:28.35#ibcon#read 6, iclass 22, count 2 2006.182.08:29:28.35#ibcon#end of sib2, iclass 22, count 2 2006.182.08:29:28.35#ibcon#*mode == 0, iclass 22, count 2 2006.182.08:29:28.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.08:29:28.35#ibcon#[25=AT02-07\r\n] 2006.182.08:29:28.35#ibcon#*before write, iclass 22, count 2 2006.182.08:29:28.35#ibcon#enter sib2, iclass 22, count 2 2006.182.08:29:28.35#ibcon#flushed, iclass 22, count 2 2006.182.08:29:28.35#ibcon#about to write, iclass 22, count 2 2006.182.08:29:28.35#ibcon#wrote, iclass 22, count 2 2006.182.08:29:28.35#ibcon#about to read 3, iclass 22, count 2 2006.182.08:29:28.38#ibcon#read 3, iclass 22, count 2 2006.182.08:29:28.38#ibcon#about to read 4, iclass 22, count 2 2006.182.08:29:28.38#ibcon#read 4, iclass 22, count 2 2006.182.08:29:28.38#ibcon#about to read 5, iclass 22, count 2 2006.182.08:29:28.38#ibcon#read 5, iclass 22, count 2 2006.182.08:29:28.38#ibcon#about to read 6, iclass 22, count 2 2006.182.08:29:28.38#ibcon#read 6, iclass 22, count 2 2006.182.08:29:28.38#ibcon#end of sib2, iclass 22, count 2 2006.182.08:29:28.38#ibcon#*after write, iclass 22, count 2 2006.182.08:29:28.38#ibcon#*before return 0, iclass 22, count 2 2006.182.08:29:28.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:28.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:28.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.08:29:28.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:28.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:28.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:28.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:28.50#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:29:28.50#ibcon#first serial, iclass 22, count 0 2006.182.08:29:28.50#ibcon#enter sib2, iclass 22, count 0 2006.182.08:29:28.50#ibcon#flushed, iclass 22, count 0 2006.182.08:29:28.50#ibcon#about to write, iclass 22, count 0 2006.182.08:29:28.50#ibcon#wrote, iclass 22, count 0 2006.182.08:29:28.50#ibcon#about to read 3, iclass 22, count 0 2006.182.08:29:28.52#ibcon#read 3, iclass 22, count 0 2006.182.08:29:28.52#ibcon#about to read 4, iclass 22, count 0 2006.182.08:29:28.52#ibcon#read 4, iclass 22, count 0 2006.182.08:29:28.52#ibcon#about to read 5, iclass 22, count 0 2006.182.08:29:28.52#ibcon#read 5, iclass 22, count 0 2006.182.08:29:28.52#ibcon#about to read 6, iclass 22, count 0 2006.182.08:29:28.52#ibcon#read 6, iclass 22, count 0 2006.182.08:29:28.52#ibcon#end of sib2, iclass 22, count 0 2006.182.08:29:28.52#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:29:28.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:29:28.52#ibcon#[25=USB\r\n] 2006.182.08:29:28.52#ibcon#*before write, iclass 22, count 0 2006.182.08:29:28.52#ibcon#enter sib2, iclass 22, count 0 2006.182.08:29:28.52#ibcon#flushed, iclass 22, count 0 2006.182.08:29:28.52#ibcon#about to write, iclass 22, count 0 2006.182.08:29:28.52#ibcon#wrote, iclass 22, count 0 2006.182.08:29:28.52#ibcon#about to read 3, iclass 22, count 0 2006.182.08:29:28.55#ibcon#read 3, iclass 22, count 0 2006.182.08:29:28.55#ibcon#about to read 4, iclass 22, count 0 2006.182.08:29:28.55#ibcon#read 4, iclass 22, count 0 2006.182.08:29:28.55#ibcon#about to read 5, iclass 22, count 0 2006.182.08:29:28.55#ibcon#read 5, iclass 22, count 0 2006.182.08:29:28.55#ibcon#about to read 6, iclass 22, count 0 2006.182.08:29:28.55#ibcon#read 6, iclass 22, count 0 2006.182.08:29:28.55#ibcon#end of sib2, iclass 22, count 0 2006.182.08:29:28.55#ibcon#*after write, iclass 22, count 0 2006.182.08:29:28.55#ibcon#*before return 0, iclass 22, count 0 2006.182.08:29:28.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:28.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:28.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:29:28.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:29:28.55$vc4f8/valo=3,672.99 2006.182.08:29:28.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.08:29:28.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.08:29:28.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:28.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:28.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:28.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:28.55#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:29:28.55#ibcon#first serial, iclass 24, count 0 2006.182.08:29:28.55#ibcon#enter sib2, iclass 24, count 0 2006.182.08:29:28.55#ibcon#flushed, iclass 24, count 0 2006.182.08:29:28.55#ibcon#about to write, iclass 24, count 0 2006.182.08:29:28.55#ibcon#wrote, iclass 24, count 0 2006.182.08:29:28.55#ibcon#about to read 3, iclass 24, count 0 2006.182.08:29:28.57#ibcon#read 3, iclass 24, count 0 2006.182.08:29:28.57#ibcon#about to read 4, iclass 24, count 0 2006.182.08:29:28.57#ibcon#read 4, iclass 24, count 0 2006.182.08:29:28.57#ibcon#about to read 5, iclass 24, count 0 2006.182.08:29:28.57#ibcon#read 5, iclass 24, count 0 2006.182.08:29:28.57#ibcon#about to read 6, iclass 24, count 0 2006.182.08:29:28.57#ibcon#read 6, iclass 24, count 0 2006.182.08:29:28.57#ibcon#end of sib2, iclass 24, count 0 2006.182.08:29:28.57#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:29:28.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:29:28.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.182.08:29:28.57#ibcon#*before write, iclass 24, count 0 2006.182.08:29:28.57#ibcon#enter sib2, iclass 24, count 0 2006.182.08:29:28.57#ibcon#flushed, iclass 24, count 0 2006.182.08:29:28.57#ibcon#about to write, iclass 24, count 0 2006.182.08:29:28.57#ibcon#wrote, iclass 24, count 0 2006.182.08:29:28.57#ibcon#about to read 3, iclass 24, count 0 2006.182.08:29:28.61#ibcon#read 3, iclass 24, count 0 2006.182.08:29:28.61#ibcon#about to read 4, iclass 24, count 0 2006.182.08:29:28.61#ibcon#read 4, iclass 24, count 0 2006.182.08:29:28.61#ibcon#about to read 5, iclass 24, count 0 2006.182.08:29:28.61#ibcon#read 5, iclass 24, count 0 2006.182.08:29:28.61#ibcon#about to read 6, iclass 24, count 0 2006.182.08:29:28.61#ibcon#read 6, iclass 24, count 0 2006.182.08:29:28.61#ibcon#end of sib2, iclass 24, count 0 2006.182.08:29:28.61#ibcon#*after write, iclass 24, count 0 2006.182.08:29:28.61#ibcon#*before return 0, iclass 24, count 0 2006.182.08:29:28.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:28.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:28.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:29:28.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:29:28.61$vc4f8/va=3,6 2006.182.08:29:28.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.08:29:28.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.08:29:28.61#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:28.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:28.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:28.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:28.67#ibcon#enter wrdev, iclass 26, count 2 2006.182.08:29:28.67#ibcon#first serial, iclass 26, count 2 2006.182.08:29:28.67#ibcon#enter sib2, iclass 26, count 2 2006.182.08:29:28.67#ibcon#flushed, iclass 26, count 2 2006.182.08:29:28.67#ibcon#about to write, iclass 26, count 2 2006.182.08:29:28.67#ibcon#wrote, iclass 26, count 2 2006.182.08:29:28.67#ibcon#about to read 3, iclass 26, count 2 2006.182.08:29:28.69#ibcon#read 3, iclass 26, count 2 2006.182.08:29:28.69#ibcon#about to read 4, iclass 26, count 2 2006.182.08:29:28.69#ibcon#read 4, iclass 26, count 2 2006.182.08:29:28.69#ibcon#about to read 5, iclass 26, count 2 2006.182.08:29:28.69#ibcon#read 5, iclass 26, count 2 2006.182.08:29:28.69#ibcon#about to read 6, iclass 26, count 2 2006.182.08:29:28.69#ibcon#read 6, iclass 26, count 2 2006.182.08:29:28.69#ibcon#end of sib2, iclass 26, count 2 2006.182.08:29:28.69#ibcon#*mode == 0, iclass 26, count 2 2006.182.08:29:28.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.08:29:28.69#ibcon#[25=AT03-06\r\n] 2006.182.08:29:28.69#ibcon#*before write, iclass 26, count 2 2006.182.08:29:28.69#ibcon#enter sib2, iclass 26, count 2 2006.182.08:29:28.69#ibcon#flushed, iclass 26, count 2 2006.182.08:29:28.69#ibcon#about to write, iclass 26, count 2 2006.182.08:29:28.69#ibcon#wrote, iclass 26, count 2 2006.182.08:29:28.69#ibcon#about to read 3, iclass 26, count 2 2006.182.08:29:28.72#ibcon#read 3, iclass 26, count 2 2006.182.08:29:28.72#ibcon#about to read 4, iclass 26, count 2 2006.182.08:29:28.72#ibcon#read 4, iclass 26, count 2 2006.182.08:29:28.72#ibcon#about to read 5, iclass 26, count 2 2006.182.08:29:28.72#ibcon#read 5, iclass 26, count 2 2006.182.08:29:28.72#ibcon#about to read 6, iclass 26, count 2 2006.182.08:29:28.72#ibcon#read 6, iclass 26, count 2 2006.182.08:29:28.72#ibcon#end of sib2, iclass 26, count 2 2006.182.08:29:28.72#ibcon#*after write, iclass 26, count 2 2006.182.08:29:28.72#ibcon#*before return 0, iclass 26, count 2 2006.182.08:29:28.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:28.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:28.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.08:29:28.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:28.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:28.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:28.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:28.84#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:29:28.84#ibcon#first serial, iclass 26, count 0 2006.182.08:29:28.84#ibcon#enter sib2, iclass 26, count 0 2006.182.08:29:28.84#ibcon#flushed, iclass 26, count 0 2006.182.08:29:28.84#ibcon#about to write, iclass 26, count 0 2006.182.08:29:28.84#ibcon#wrote, iclass 26, count 0 2006.182.08:29:28.84#ibcon#about to read 3, iclass 26, count 0 2006.182.08:29:28.86#ibcon#read 3, iclass 26, count 0 2006.182.08:29:28.86#ibcon#about to read 4, iclass 26, count 0 2006.182.08:29:28.86#ibcon#read 4, iclass 26, count 0 2006.182.08:29:28.86#ibcon#about to read 5, iclass 26, count 0 2006.182.08:29:28.86#ibcon#read 5, iclass 26, count 0 2006.182.08:29:28.86#ibcon#about to read 6, iclass 26, count 0 2006.182.08:29:28.86#ibcon#read 6, iclass 26, count 0 2006.182.08:29:28.86#ibcon#end of sib2, iclass 26, count 0 2006.182.08:29:28.86#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:29:28.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:29:28.86#ibcon#[25=USB\r\n] 2006.182.08:29:28.86#ibcon#*before write, iclass 26, count 0 2006.182.08:29:28.86#ibcon#enter sib2, iclass 26, count 0 2006.182.08:29:28.86#ibcon#flushed, iclass 26, count 0 2006.182.08:29:28.86#ibcon#about to write, iclass 26, count 0 2006.182.08:29:28.86#ibcon#wrote, iclass 26, count 0 2006.182.08:29:28.86#ibcon#about to read 3, iclass 26, count 0 2006.182.08:29:28.89#ibcon#read 3, iclass 26, count 0 2006.182.08:29:28.89#ibcon#about to read 4, iclass 26, count 0 2006.182.08:29:28.89#ibcon#read 4, iclass 26, count 0 2006.182.08:29:28.89#ibcon#about to read 5, iclass 26, count 0 2006.182.08:29:28.89#ibcon#read 5, iclass 26, count 0 2006.182.08:29:28.89#ibcon#about to read 6, iclass 26, count 0 2006.182.08:29:28.89#ibcon#read 6, iclass 26, count 0 2006.182.08:29:28.89#ibcon#end of sib2, iclass 26, count 0 2006.182.08:29:28.89#ibcon#*after write, iclass 26, count 0 2006.182.08:29:28.89#ibcon#*before return 0, iclass 26, count 0 2006.182.08:29:28.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:28.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:28.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:29:28.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:29:28.89$vc4f8/valo=4,832.99 2006.182.08:29:28.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.08:29:28.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.08:29:28.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:28.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:28.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:28.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:28.89#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:29:28.89#ibcon#first serial, iclass 28, count 0 2006.182.08:29:28.89#ibcon#enter sib2, iclass 28, count 0 2006.182.08:29:28.89#ibcon#flushed, iclass 28, count 0 2006.182.08:29:28.89#ibcon#about to write, iclass 28, count 0 2006.182.08:29:28.89#ibcon#wrote, iclass 28, count 0 2006.182.08:29:28.89#ibcon#about to read 3, iclass 28, count 0 2006.182.08:29:28.91#ibcon#read 3, iclass 28, count 0 2006.182.08:29:28.91#ibcon#about to read 4, iclass 28, count 0 2006.182.08:29:28.91#ibcon#read 4, iclass 28, count 0 2006.182.08:29:28.91#ibcon#about to read 5, iclass 28, count 0 2006.182.08:29:28.91#ibcon#read 5, iclass 28, count 0 2006.182.08:29:28.91#ibcon#about to read 6, iclass 28, count 0 2006.182.08:29:28.91#ibcon#read 6, iclass 28, count 0 2006.182.08:29:28.91#ibcon#end of sib2, iclass 28, count 0 2006.182.08:29:28.91#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:29:28.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:29:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.182.08:29:28.91#ibcon#*before write, iclass 28, count 0 2006.182.08:29:28.91#ibcon#enter sib2, iclass 28, count 0 2006.182.08:29:28.91#ibcon#flushed, iclass 28, count 0 2006.182.08:29:28.91#ibcon#about to write, iclass 28, count 0 2006.182.08:29:28.91#ibcon#wrote, iclass 28, count 0 2006.182.08:29:28.91#ibcon#about to read 3, iclass 28, count 0 2006.182.08:29:28.95#ibcon#read 3, iclass 28, count 0 2006.182.08:29:28.95#ibcon#about to read 4, iclass 28, count 0 2006.182.08:29:28.95#ibcon#read 4, iclass 28, count 0 2006.182.08:29:28.95#ibcon#about to read 5, iclass 28, count 0 2006.182.08:29:28.95#ibcon#read 5, iclass 28, count 0 2006.182.08:29:28.95#ibcon#about to read 6, iclass 28, count 0 2006.182.08:29:28.95#ibcon#read 6, iclass 28, count 0 2006.182.08:29:28.95#ibcon#end of sib2, iclass 28, count 0 2006.182.08:29:28.95#ibcon#*after write, iclass 28, count 0 2006.182.08:29:28.95#ibcon#*before return 0, iclass 28, count 0 2006.182.08:29:28.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:28.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:28.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:29:28.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:29:28.95$vc4f8/va=4,7 2006.182.08:29:28.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.08:29:28.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.08:29:28.95#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:28.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:29.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:29.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:29.01#ibcon#enter wrdev, iclass 30, count 2 2006.182.08:29:29.01#ibcon#first serial, iclass 30, count 2 2006.182.08:29:29.01#ibcon#enter sib2, iclass 30, count 2 2006.182.08:29:29.01#ibcon#flushed, iclass 30, count 2 2006.182.08:29:29.01#ibcon#about to write, iclass 30, count 2 2006.182.08:29:29.01#ibcon#wrote, iclass 30, count 2 2006.182.08:29:29.01#ibcon#about to read 3, iclass 30, count 2 2006.182.08:29:29.03#ibcon#read 3, iclass 30, count 2 2006.182.08:29:29.03#ibcon#about to read 4, iclass 30, count 2 2006.182.08:29:29.03#ibcon#read 4, iclass 30, count 2 2006.182.08:29:29.03#ibcon#about to read 5, iclass 30, count 2 2006.182.08:29:29.03#ibcon#read 5, iclass 30, count 2 2006.182.08:29:29.03#ibcon#about to read 6, iclass 30, count 2 2006.182.08:29:29.03#ibcon#read 6, iclass 30, count 2 2006.182.08:29:29.03#ibcon#end of sib2, iclass 30, count 2 2006.182.08:29:29.03#ibcon#*mode == 0, iclass 30, count 2 2006.182.08:29:29.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.08:29:29.03#ibcon#[25=AT04-07\r\n] 2006.182.08:29:29.03#ibcon#*before write, iclass 30, count 2 2006.182.08:29:29.03#ibcon#enter sib2, iclass 30, count 2 2006.182.08:29:29.03#ibcon#flushed, iclass 30, count 2 2006.182.08:29:29.03#ibcon#about to write, iclass 30, count 2 2006.182.08:29:29.03#ibcon#wrote, iclass 30, count 2 2006.182.08:29:29.03#ibcon#about to read 3, iclass 30, count 2 2006.182.08:29:29.06#ibcon#read 3, iclass 30, count 2 2006.182.08:29:29.06#ibcon#about to read 4, iclass 30, count 2 2006.182.08:29:29.06#ibcon#read 4, iclass 30, count 2 2006.182.08:29:29.06#ibcon#about to read 5, iclass 30, count 2 2006.182.08:29:29.06#ibcon#read 5, iclass 30, count 2 2006.182.08:29:29.06#ibcon#about to read 6, iclass 30, count 2 2006.182.08:29:29.06#ibcon#read 6, iclass 30, count 2 2006.182.08:29:29.06#ibcon#end of sib2, iclass 30, count 2 2006.182.08:29:29.06#ibcon#*after write, iclass 30, count 2 2006.182.08:29:29.06#ibcon#*before return 0, iclass 30, count 2 2006.182.08:29:29.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:29.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:29.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.08:29:29.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:29.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:29.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:29.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:29.18#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:29:29.18#ibcon#first serial, iclass 30, count 0 2006.182.08:29:29.18#ibcon#enter sib2, iclass 30, count 0 2006.182.08:29:29.18#ibcon#flushed, iclass 30, count 0 2006.182.08:29:29.18#ibcon#about to write, iclass 30, count 0 2006.182.08:29:29.18#ibcon#wrote, iclass 30, count 0 2006.182.08:29:29.18#ibcon#about to read 3, iclass 30, count 0 2006.182.08:29:29.20#ibcon#read 3, iclass 30, count 0 2006.182.08:29:29.20#ibcon#about to read 4, iclass 30, count 0 2006.182.08:29:29.20#ibcon#read 4, iclass 30, count 0 2006.182.08:29:29.20#ibcon#about to read 5, iclass 30, count 0 2006.182.08:29:29.20#ibcon#read 5, iclass 30, count 0 2006.182.08:29:29.20#ibcon#about to read 6, iclass 30, count 0 2006.182.08:29:29.20#ibcon#read 6, iclass 30, count 0 2006.182.08:29:29.20#ibcon#end of sib2, iclass 30, count 0 2006.182.08:29:29.20#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:29:29.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:29:29.20#ibcon#[25=USB\r\n] 2006.182.08:29:29.20#ibcon#*before write, iclass 30, count 0 2006.182.08:29:29.20#ibcon#enter sib2, iclass 30, count 0 2006.182.08:29:29.20#ibcon#flushed, iclass 30, count 0 2006.182.08:29:29.20#ibcon#about to write, iclass 30, count 0 2006.182.08:29:29.20#ibcon#wrote, iclass 30, count 0 2006.182.08:29:29.20#ibcon#about to read 3, iclass 30, count 0 2006.182.08:29:29.23#ibcon#read 3, iclass 30, count 0 2006.182.08:29:29.23#ibcon#about to read 4, iclass 30, count 0 2006.182.08:29:29.23#ibcon#read 4, iclass 30, count 0 2006.182.08:29:29.23#ibcon#about to read 5, iclass 30, count 0 2006.182.08:29:29.23#ibcon#read 5, iclass 30, count 0 2006.182.08:29:29.23#ibcon#about to read 6, iclass 30, count 0 2006.182.08:29:29.23#ibcon#read 6, iclass 30, count 0 2006.182.08:29:29.23#ibcon#end of sib2, iclass 30, count 0 2006.182.08:29:29.23#ibcon#*after write, iclass 30, count 0 2006.182.08:29:29.23#ibcon#*before return 0, iclass 30, count 0 2006.182.08:29:29.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:29.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:29.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:29:29.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:29:29.23$vc4f8/valo=5,652.99 2006.182.08:29:29.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.08:29:29.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.08:29:29.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:29.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:29.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:29.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:29.23#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:29:29.23#ibcon#first serial, iclass 32, count 0 2006.182.08:29:29.23#ibcon#enter sib2, iclass 32, count 0 2006.182.08:29:29.23#ibcon#flushed, iclass 32, count 0 2006.182.08:29:29.23#ibcon#about to write, iclass 32, count 0 2006.182.08:29:29.23#ibcon#wrote, iclass 32, count 0 2006.182.08:29:29.23#ibcon#about to read 3, iclass 32, count 0 2006.182.08:29:29.25#ibcon#read 3, iclass 32, count 0 2006.182.08:29:29.25#ibcon#about to read 4, iclass 32, count 0 2006.182.08:29:29.25#ibcon#read 4, iclass 32, count 0 2006.182.08:29:29.25#ibcon#about to read 5, iclass 32, count 0 2006.182.08:29:29.25#ibcon#read 5, iclass 32, count 0 2006.182.08:29:29.25#ibcon#about to read 6, iclass 32, count 0 2006.182.08:29:29.25#ibcon#read 6, iclass 32, count 0 2006.182.08:29:29.25#ibcon#end of sib2, iclass 32, count 0 2006.182.08:29:29.25#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:29:29.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:29:29.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.182.08:29:29.25#ibcon#*before write, iclass 32, count 0 2006.182.08:29:29.25#ibcon#enter sib2, iclass 32, count 0 2006.182.08:29:29.25#ibcon#flushed, iclass 32, count 0 2006.182.08:29:29.25#ibcon#about to write, iclass 32, count 0 2006.182.08:29:29.25#ibcon#wrote, iclass 32, count 0 2006.182.08:29:29.25#ibcon#about to read 3, iclass 32, count 0 2006.182.08:29:29.29#ibcon#read 3, iclass 32, count 0 2006.182.08:29:29.29#ibcon#about to read 4, iclass 32, count 0 2006.182.08:29:29.29#ibcon#read 4, iclass 32, count 0 2006.182.08:29:29.29#ibcon#about to read 5, iclass 32, count 0 2006.182.08:29:29.29#ibcon#read 5, iclass 32, count 0 2006.182.08:29:29.29#ibcon#about to read 6, iclass 32, count 0 2006.182.08:29:29.29#ibcon#read 6, iclass 32, count 0 2006.182.08:29:29.29#ibcon#end of sib2, iclass 32, count 0 2006.182.08:29:29.29#ibcon#*after write, iclass 32, count 0 2006.182.08:29:29.29#ibcon#*before return 0, iclass 32, count 0 2006.182.08:29:29.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:29.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:29.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:29:29.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:29:29.29$vc4f8/va=5,7 2006.182.08:29:29.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.08:29:29.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.08:29:29.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:29.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:29.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:29.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:29.35#ibcon#enter wrdev, iclass 34, count 2 2006.182.08:29:29.35#ibcon#first serial, iclass 34, count 2 2006.182.08:29:29.35#ibcon#enter sib2, iclass 34, count 2 2006.182.08:29:29.35#ibcon#flushed, iclass 34, count 2 2006.182.08:29:29.35#ibcon#about to write, iclass 34, count 2 2006.182.08:29:29.35#ibcon#wrote, iclass 34, count 2 2006.182.08:29:29.35#ibcon#about to read 3, iclass 34, count 2 2006.182.08:29:29.37#ibcon#read 3, iclass 34, count 2 2006.182.08:29:29.37#ibcon#about to read 4, iclass 34, count 2 2006.182.08:29:29.37#ibcon#read 4, iclass 34, count 2 2006.182.08:29:29.37#ibcon#about to read 5, iclass 34, count 2 2006.182.08:29:29.37#ibcon#read 5, iclass 34, count 2 2006.182.08:29:29.37#ibcon#about to read 6, iclass 34, count 2 2006.182.08:29:29.37#ibcon#read 6, iclass 34, count 2 2006.182.08:29:29.37#ibcon#end of sib2, iclass 34, count 2 2006.182.08:29:29.37#ibcon#*mode == 0, iclass 34, count 2 2006.182.08:29:29.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.08:29:29.37#ibcon#[25=AT05-07\r\n] 2006.182.08:29:29.37#ibcon#*before write, iclass 34, count 2 2006.182.08:29:29.37#ibcon#enter sib2, iclass 34, count 2 2006.182.08:29:29.37#ibcon#flushed, iclass 34, count 2 2006.182.08:29:29.37#ibcon#about to write, iclass 34, count 2 2006.182.08:29:29.37#ibcon#wrote, iclass 34, count 2 2006.182.08:29:29.37#ibcon#about to read 3, iclass 34, count 2 2006.182.08:29:29.40#ibcon#read 3, iclass 34, count 2 2006.182.08:29:29.40#ibcon#about to read 4, iclass 34, count 2 2006.182.08:29:29.40#ibcon#read 4, iclass 34, count 2 2006.182.08:29:29.40#ibcon#about to read 5, iclass 34, count 2 2006.182.08:29:29.40#ibcon#read 5, iclass 34, count 2 2006.182.08:29:29.40#ibcon#about to read 6, iclass 34, count 2 2006.182.08:29:29.40#ibcon#read 6, iclass 34, count 2 2006.182.08:29:29.40#ibcon#end of sib2, iclass 34, count 2 2006.182.08:29:29.40#ibcon#*after write, iclass 34, count 2 2006.182.08:29:29.40#ibcon#*before return 0, iclass 34, count 2 2006.182.08:29:29.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:29.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:29.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.08:29:29.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:29.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:29.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:29.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:29.52#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:29:29.52#ibcon#first serial, iclass 34, count 0 2006.182.08:29:29.52#ibcon#enter sib2, iclass 34, count 0 2006.182.08:29:29.52#ibcon#flushed, iclass 34, count 0 2006.182.08:29:29.52#ibcon#about to write, iclass 34, count 0 2006.182.08:29:29.52#ibcon#wrote, iclass 34, count 0 2006.182.08:29:29.52#ibcon#about to read 3, iclass 34, count 0 2006.182.08:29:29.54#ibcon#read 3, iclass 34, count 0 2006.182.08:29:29.54#ibcon#about to read 4, iclass 34, count 0 2006.182.08:29:29.54#ibcon#read 4, iclass 34, count 0 2006.182.08:29:29.54#ibcon#about to read 5, iclass 34, count 0 2006.182.08:29:29.54#ibcon#read 5, iclass 34, count 0 2006.182.08:29:29.54#ibcon#about to read 6, iclass 34, count 0 2006.182.08:29:29.54#ibcon#read 6, iclass 34, count 0 2006.182.08:29:29.54#ibcon#end of sib2, iclass 34, count 0 2006.182.08:29:29.54#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:29:29.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:29:29.54#ibcon#[25=USB\r\n] 2006.182.08:29:29.54#ibcon#*before write, iclass 34, count 0 2006.182.08:29:29.54#ibcon#enter sib2, iclass 34, count 0 2006.182.08:29:29.54#ibcon#flushed, iclass 34, count 0 2006.182.08:29:29.54#ibcon#about to write, iclass 34, count 0 2006.182.08:29:29.54#ibcon#wrote, iclass 34, count 0 2006.182.08:29:29.54#ibcon#about to read 3, iclass 34, count 0 2006.182.08:29:29.57#ibcon#read 3, iclass 34, count 0 2006.182.08:29:29.57#ibcon#about to read 4, iclass 34, count 0 2006.182.08:29:29.57#ibcon#read 4, iclass 34, count 0 2006.182.08:29:29.57#ibcon#about to read 5, iclass 34, count 0 2006.182.08:29:29.57#ibcon#read 5, iclass 34, count 0 2006.182.08:29:29.57#ibcon#about to read 6, iclass 34, count 0 2006.182.08:29:29.57#ibcon#read 6, iclass 34, count 0 2006.182.08:29:29.57#ibcon#end of sib2, iclass 34, count 0 2006.182.08:29:29.57#ibcon#*after write, iclass 34, count 0 2006.182.08:29:29.57#ibcon#*before return 0, iclass 34, count 0 2006.182.08:29:29.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:29.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:29.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:29:29.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:29:29.57$vc4f8/valo=6,772.99 2006.182.08:29:29.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.08:29:29.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.08:29:29.57#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:29.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:29.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:29.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:29.57#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:29:29.57#ibcon#first serial, iclass 36, count 0 2006.182.08:29:29.57#ibcon#enter sib2, iclass 36, count 0 2006.182.08:29:29.57#ibcon#flushed, iclass 36, count 0 2006.182.08:29:29.57#ibcon#about to write, iclass 36, count 0 2006.182.08:29:29.57#ibcon#wrote, iclass 36, count 0 2006.182.08:29:29.57#ibcon#about to read 3, iclass 36, count 0 2006.182.08:29:29.59#ibcon#read 3, iclass 36, count 0 2006.182.08:29:29.59#ibcon#about to read 4, iclass 36, count 0 2006.182.08:29:29.59#ibcon#read 4, iclass 36, count 0 2006.182.08:29:29.59#ibcon#about to read 5, iclass 36, count 0 2006.182.08:29:29.59#ibcon#read 5, iclass 36, count 0 2006.182.08:29:29.59#ibcon#about to read 6, iclass 36, count 0 2006.182.08:29:29.59#ibcon#read 6, iclass 36, count 0 2006.182.08:29:29.59#ibcon#end of sib2, iclass 36, count 0 2006.182.08:29:29.59#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:29:29.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:29:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.182.08:29:29.59#ibcon#*before write, iclass 36, count 0 2006.182.08:29:29.59#ibcon#enter sib2, iclass 36, count 0 2006.182.08:29:29.59#ibcon#flushed, iclass 36, count 0 2006.182.08:29:29.59#ibcon#about to write, iclass 36, count 0 2006.182.08:29:29.59#ibcon#wrote, iclass 36, count 0 2006.182.08:29:29.59#ibcon#about to read 3, iclass 36, count 0 2006.182.08:29:29.63#ibcon#read 3, iclass 36, count 0 2006.182.08:29:29.63#ibcon#about to read 4, iclass 36, count 0 2006.182.08:29:29.63#ibcon#read 4, iclass 36, count 0 2006.182.08:29:29.63#ibcon#about to read 5, iclass 36, count 0 2006.182.08:29:29.63#ibcon#read 5, iclass 36, count 0 2006.182.08:29:29.63#ibcon#about to read 6, iclass 36, count 0 2006.182.08:29:29.63#ibcon#read 6, iclass 36, count 0 2006.182.08:29:29.63#ibcon#end of sib2, iclass 36, count 0 2006.182.08:29:29.63#ibcon#*after write, iclass 36, count 0 2006.182.08:29:29.63#ibcon#*before return 0, iclass 36, count 0 2006.182.08:29:29.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:29.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:29.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:29:29.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:29:29.63$vc4f8/va=6,6 2006.182.08:29:29.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.182.08:29:29.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.182.08:29:29.63#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:29.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:29:29.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:29:29.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:29:29.69#ibcon#enter wrdev, iclass 38, count 2 2006.182.08:29:29.69#ibcon#first serial, iclass 38, count 2 2006.182.08:29:29.69#ibcon#enter sib2, iclass 38, count 2 2006.182.08:29:29.69#ibcon#flushed, iclass 38, count 2 2006.182.08:29:29.69#ibcon#about to write, iclass 38, count 2 2006.182.08:29:29.69#ibcon#wrote, iclass 38, count 2 2006.182.08:29:29.69#ibcon#about to read 3, iclass 38, count 2 2006.182.08:29:29.71#ibcon#read 3, iclass 38, count 2 2006.182.08:29:29.71#ibcon#about to read 4, iclass 38, count 2 2006.182.08:29:29.71#ibcon#read 4, iclass 38, count 2 2006.182.08:29:29.71#ibcon#about to read 5, iclass 38, count 2 2006.182.08:29:29.71#ibcon#read 5, iclass 38, count 2 2006.182.08:29:29.71#ibcon#about to read 6, iclass 38, count 2 2006.182.08:29:29.71#ibcon#read 6, iclass 38, count 2 2006.182.08:29:29.71#ibcon#end of sib2, iclass 38, count 2 2006.182.08:29:29.71#ibcon#*mode == 0, iclass 38, count 2 2006.182.08:29:29.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.182.08:29:29.71#ibcon#[25=AT06-06\r\n] 2006.182.08:29:29.71#ibcon#*before write, iclass 38, count 2 2006.182.08:29:29.71#ibcon#enter sib2, iclass 38, count 2 2006.182.08:29:29.71#ibcon#flushed, iclass 38, count 2 2006.182.08:29:29.71#ibcon#about to write, iclass 38, count 2 2006.182.08:29:29.71#ibcon#wrote, iclass 38, count 2 2006.182.08:29:29.71#ibcon#about to read 3, iclass 38, count 2 2006.182.08:29:29.74#ibcon#read 3, iclass 38, count 2 2006.182.08:29:29.74#ibcon#about to read 4, iclass 38, count 2 2006.182.08:29:29.74#ibcon#read 4, iclass 38, count 2 2006.182.08:29:29.74#ibcon#about to read 5, iclass 38, count 2 2006.182.08:29:29.74#ibcon#read 5, iclass 38, count 2 2006.182.08:29:29.74#ibcon#about to read 6, iclass 38, count 2 2006.182.08:29:29.74#ibcon#read 6, iclass 38, count 2 2006.182.08:29:29.74#ibcon#end of sib2, iclass 38, count 2 2006.182.08:29:29.74#ibcon#*after write, iclass 38, count 2 2006.182.08:29:29.74#ibcon#*before return 0, iclass 38, count 2 2006.182.08:29:29.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:29:29.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.182.08:29:29.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.182.08:29:29.74#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:29.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:29:29.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:29:29.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:29:29.86#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:29:29.86#ibcon#first serial, iclass 38, count 0 2006.182.08:29:29.86#ibcon#enter sib2, iclass 38, count 0 2006.182.08:29:29.86#ibcon#flushed, iclass 38, count 0 2006.182.08:29:29.86#ibcon#about to write, iclass 38, count 0 2006.182.08:29:29.86#ibcon#wrote, iclass 38, count 0 2006.182.08:29:29.86#ibcon#about to read 3, iclass 38, count 0 2006.182.08:29:29.88#ibcon#read 3, iclass 38, count 0 2006.182.08:29:29.88#ibcon#about to read 4, iclass 38, count 0 2006.182.08:29:29.88#ibcon#read 4, iclass 38, count 0 2006.182.08:29:29.88#ibcon#about to read 5, iclass 38, count 0 2006.182.08:29:29.88#ibcon#read 5, iclass 38, count 0 2006.182.08:29:29.88#ibcon#about to read 6, iclass 38, count 0 2006.182.08:29:29.88#ibcon#read 6, iclass 38, count 0 2006.182.08:29:29.88#ibcon#end of sib2, iclass 38, count 0 2006.182.08:29:29.88#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:29:29.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:29:29.88#ibcon#[25=USB\r\n] 2006.182.08:29:29.88#ibcon#*before write, iclass 38, count 0 2006.182.08:29:29.88#ibcon#enter sib2, iclass 38, count 0 2006.182.08:29:29.88#ibcon#flushed, iclass 38, count 0 2006.182.08:29:29.88#ibcon#about to write, iclass 38, count 0 2006.182.08:29:29.88#ibcon#wrote, iclass 38, count 0 2006.182.08:29:29.88#ibcon#about to read 3, iclass 38, count 0 2006.182.08:29:29.91#ibcon#read 3, iclass 38, count 0 2006.182.08:29:29.91#ibcon#about to read 4, iclass 38, count 0 2006.182.08:29:29.91#ibcon#read 4, iclass 38, count 0 2006.182.08:29:29.91#ibcon#about to read 5, iclass 38, count 0 2006.182.08:29:29.91#ibcon#read 5, iclass 38, count 0 2006.182.08:29:29.91#ibcon#about to read 6, iclass 38, count 0 2006.182.08:29:29.91#ibcon#read 6, iclass 38, count 0 2006.182.08:29:29.91#ibcon#end of sib2, iclass 38, count 0 2006.182.08:29:29.91#ibcon#*after write, iclass 38, count 0 2006.182.08:29:29.91#ibcon#*before return 0, iclass 38, count 0 2006.182.08:29:29.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:29:29.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.182.08:29:29.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:29:29.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:29:29.91$vc4f8/valo=7,832.99 2006.182.08:29:29.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.182.08:29:29.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.182.08:29:29.91#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:29.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:29:29.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:29:29.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:29:29.91#ibcon#enter wrdev, iclass 40, count 0 2006.182.08:29:29.91#ibcon#first serial, iclass 40, count 0 2006.182.08:29:29.91#ibcon#enter sib2, iclass 40, count 0 2006.182.08:29:29.91#ibcon#flushed, iclass 40, count 0 2006.182.08:29:29.91#ibcon#about to write, iclass 40, count 0 2006.182.08:29:29.91#ibcon#wrote, iclass 40, count 0 2006.182.08:29:29.91#ibcon#about to read 3, iclass 40, count 0 2006.182.08:29:29.93#ibcon#read 3, iclass 40, count 0 2006.182.08:29:29.93#ibcon#about to read 4, iclass 40, count 0 2006.182.08:29:29.93#ibcon#read 4, iclass 40, count 0 2006.182.08:29:29.93#ibcon#about to read 5, iclass 40, count 0 2006.182.08:29:29.93#ibcon#read 5, iclass 40, count 0 2006.182.08:29:29.93#ibcon#about to read 6, iclass 40, count 0 2006.182.08:29:29.93#ibcon#read 6, iclass 40, count 0 2006.182.08:29:29.93#ibcon#end of sib2, iclass 40, count 0 2006.182.08:29:29.93#ibcon#*mode == 0, iclass 40, count 0 2006.182.08:29:29.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.182.08:29:29.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.182.08:29:29.93#ibcon#*before write, iclass 40, count 0 2006.182.08:29:29.93#ibcon#enter sib2, iclass 40, count 0 2006.182.08:29:29.93#ibcon#flushed, iclass 40, count 0 2006.182.08:29:29.93#ibcon#about to write, iclass 40, count 0 2006.182.08:29:29.93#ibcon#wrote, iclass 40, count 0 2006.182.08:29:29.93#ibcon#about to read 3, iclass 40, count 0 2006.182.08:29:29.97#ibcon#read 3, iclass 40, count 0 2006.182.08:29:29.97#ibcon#about to read 4, iclass 40, count 0 2006.182.08:29:29.97#ibcon#read 4, iclass 40, count 0 2006.182.08:29:29.97#ibcon#about to read 5, iclass 40, count 0 2006.182.08:29:29.97#ibcon#read 5, iclass 40, count 0 2006.182.08:29:29.97#ibcon#about to read 6, iclass 40, count 0 2006.182.08:29:29.97#ibcon#read 6, iclass 40, count 0 2006.182.08:29:29.97#ibcon#end of sib2, iclass 40, count 0 2006.182.08:29:29.97#ibcon#*after write, iclass 40, count 0 2006.182.08:29:29.97#ibcon#*before return 0, iclass 40, count 0 2006.182.08:29:29.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:29:29.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.182.08:29:29.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.182.08:29:29.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.182.08:29:29.97$vc4f8/va=7,6 2006.182.08:29:29.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.182.08:29:29.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.182.08:29:29.97#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:29.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:29:30.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:29:30.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:29:30.03#ibcon#enter wrdev, iclass 4, count 2 2006.182.08:29:30.03#ibcon#first serial, iclass 4, count 2 2006.182.08:29:30.03#ibcon#enter sib2, iclass 4, count 2 2006.182.08:29:30.03#ibcon#flushed, iclass 4, count 2 2006.182.08:29:30.03#ibcon#about to write, iclass 4, count 2 2006.182.08:29:30.03#ibcon#wrote, iclass 4, count 2 2006.182.08:29:30.03#ibcon#about to read 3, iclass 4, count 2 2006.182.08:29:30.05#ibcon#read 3, iclass 4, count 2 2006.182.08:29:30.05#ibcon#about to read 4, iclass 4, count 2 2006.182.08:29:30.05#ibcon#read 4, iclass 4, count 2 2006.182.08:29:30.05#ibcon#about to read 5, iclass 4, count 2 2006.182.08:29:30.05#ibcon#read 5, iclass 4, count 2 2006.182.08:29:30.05#ibcon#about to read 6, iclass 4, count 2 2006.182.08:29:30.05#ibcon#read 6, iclass 4, count 2 2006.182.08:29:30.05#ibcon#end of sib2, iclass 4, count 2 2006.182.08:29:30.05#ibcon#*mode == 0, iclass 4, count 2 2006.182.08:29:30.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.182.08:29:30.05#ibcon#[25=AT07-06\r\n] 2006.182.08:29:30.05#ibcon#*before write, iclass 4, count 2 2006.182.08:29:30.05#ibcon#enter sib2, iclass 4, count 2 2006.182.08:29:30.05#ibcon#flushed, iclass 4, count 2 2006.182.08:29:30.05#ibcon#about to write, iclass 4, count 2 2006.182.08:29:30.05#ibcon#wrote, iclass 4, count 2 2006.182.08:29:30.05#ibcon#about to read 3, iclass 4, count 2 2006.182.08:29:30.08#ibcon#read 3, iclass 4, count 2 2006.182.08:29:30.08#ibcon#about to read 4, iclass 4, count 2 2006.182.08:29:30.08#ibcon#read 4, iclass 4, count 2 2006.182.08:29:30.08#ibcon#about to read 5, iclass 4, count 2 2006.182.08:29:30.08#ibcon#read 5, iclass 4, count 2 2006.182.08:29:30.08#ibcon#about to read 6, iclass 4, count 2 2006.182.08:29:30.08#ibcon#read 6, iclass 4, count 2 2006.182.08:29:30.08#ibcon#end of sib2, iclass 4, count 2 2006.182.08:29:30.08#ibcon#*after write, iclass 4, count 2 2006.182.08:29:30.08#ibcon#*before return 0, iclass 4, count 2 2006.182.08:29:30.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:29:30.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.182.08:29:30.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.182.08:29:30.08#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:30.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:29:30.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:29:30.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:29:30.20#ibcon#enter wrdev, iclass 4, count 0 2006.182.08:29:30.20#ibcon#first serial, iclass 4, count 0 2006.182.08:29:30.20#ibcon#enter sib2, iclass 4, count 0 2006.182.08:29:30.20#ibcon#flushed, iclass 4, count 0 2006.182.08:29:30.20#ibcon#about to write, iclass 4, count 0 2006.182.08:29:30.20#ibcon#wrote, iclass 4, count 0 2006.182.08:29:30.20#ibcon#about to read 3, iclass 4, count 0 2006.182.08:29:30.22#ibcon#read 3, iclass 4, count 0 2006.182.08:29:30.22#ibcon#about to read 4, iclass 4, count 0 2006.182.08:29:30.22#ibcon#read 4, iclass 4, count 0 2006.182.08:29:30.22#ibcon#about to read 5, iclass 4, count 0 2006.182.08:29:30.22#ibcon#read 5, iclass 4, count 0 2006.182.08:29:30.22#ibcon#about to read 6, iclass 4, count 0 2006.182.08:29:30.22#ibcon#read 6, iclass 4, count 0 2006.182.08:29:30.22#ibcon#end of sib2, iclass 4, count 0 2006.182.08:29:30.22#ibcon#*mode == 0, iclass 4, count 0 2006.182.08:29:30.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.182.08:29:30.22#ibcon#[25=USB\r\n] 2006.182.08:29:30.22#ibcon#*before write, iclass 4, count 0 2006.182.08:29:30.22#ibcon#enter sib2, iclass 4, count 0 2006.182.08:29:30.22#ibcon#flushed, iclass 4, count 0 2006.182.08:29:30.22#ibcon#about to write, iclass 4, count 0 2006.182.08:29:30.22#ibcon#wrote, iclass 4, count 0 2006.182.08:29:30.22#ibcon#about to read 3, iclass 4, count 0 2006.182.08:29:30.25#ibcon#read 3, iclass 4, count 0 2006.182.08:29:30.25#ibcon#about to read 4, iclass 4, count 0 2006.182.08:29:30.25#ibcon#read 4, iclass 4, count 0 2006.182.08:29:30.25#ibcon#about to read 5, iclass 4, count 0 2006.182.08:29:30.25#ibcon#read 5, iclass 4, count 0 2006.182.08:29:30.25#ibcon#about to read 6, iclass 4, count 0 2006.182.08:29:30.25#ibcon#read 6, iclass 4, count 0 2006.182.08:29:30.25#ibcon#end of sib2, iclass 4, count 0 2006.182.08:29:30.25#ibcon#*after write, iclass 4, count 0 2006.182.08:29:30.25#ibcon#*before return 0, iclass 4, count 0 2006.182.08:29:30.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:29:30.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.182.08:29:30.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.182.08:29:30.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.182.08:29:30.25$vc4f8/valo=8,852.99 2006.182.08:29:30.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.182.08:29:30.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.182.08:29:30.25#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:30.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:29:30.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:29:30.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:29:30.25#ibcon#enter wrdev, iclass 6, count 0 2006.182.08:29:30.25#ibcon#first serial, iclass 6, count 0 2006.182.08:29:30.25#ibcon#enter sib2, iclass 6, count 0 2006.182.08:29:30.25#ibcon#flushed, iclass 6, count 0 2006.182.08:29:30.25#ibcon#about to write, iclass 6, count 0 2006.182.08:29:30.25#ibcon#wrote, iclass 6, count 0 2006.182.08:29:30.25#ibcon#about to read 3, iclass 6, count 0 2006.182.08:29:30.27#ibcon#read 3, iclass 6, count 0 2006.182.08:29:30.27#ibcon#about to read 4, iclass 6, count 0 2006.182.08:29:30.27#ibcon#read 4, iclass 6, count 0 2006.182.08:29:30.27#ibcon#about to read 5, iclass 6, count 0 2006.182.08:29:30.27#ibcon#read 5, iclass 6, count 0 2006.182.08:29:30.27#ibcon#about to read 6, iclass 6, count 0 2006.182.08:29:30.27#ibcon#read 6, iclass 6, count 0 2006.182.08:29:30.27#ibcon#end of sib2, iclass 6, count 0 2006.182.08:29:30.27#ibcon#*mode == 0, iclass 6, count 0 2006.182.08:29:30.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.182.08:29:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.182.08:29:30.27#ibcon#*before write, iclass 6, count 0 2006.182.08:29:30.27#ibcon#enter sib2, iclass 6, count 0 2006.182.08:29:30.27#ibcon#flushed, iclass 6, count 0 2006.182.08:29:30.27#ibcon#about to write, iclass 6, count 0 2006.182.08:29:30.27#ibcon#wrote, iclass 6, count 0 2006.182.08:29:30.27#ibcon#about to read 3, iclass 6, count 0 2006.182.08:29:30.31#ibcon#read 3, iclass 6, count 0 2006.182.08:29:30.31#ibcon#about to read 4, iclass 6, count 0 2006.182.08:29:30.31#ibcon#read 4, iclass 6, count 0 2006.182.08:29:30.31#ibcon#about to read 5, iclass 6, count 0 2006.182.08:29:30.31#ibcon#read 5, iclass 6, count 0 2006.182.08:29:30.31#ibcon#about to read 6, iclass 6, count 0 2006.182.08:29:30.31#ibcon#read 6, iclass 6, count 0 2006.182.08:29:30.31#ibcon#end of sib2, iclass 6, count 0 2006.182.08:29:30.31#ibcon#*after write, iclass 6, count 0 2006.182.08:29:30.31#ibcon#*before return 0, iclass 6, count 0 2006.182.08:29:30.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:29:30.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.182.08:29:30.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.182.08:29:30.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.182.08:29:30.31$vc4f8/va=8,7 2006.182.08:29:30.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.182.08:29:30.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.182.08:29:30.31#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:30.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:29:30.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:29:30.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:29:30.37#ibcon#enter wrdev, iclass 10, count 2 2006.182.08:29:30.37#ibcon#first serial, iclass 10, count 2 2006.182.08:29:30.37#ibcon#enter sib2, iclass 10, count 2 2006.182.08:29:30.37#ibcon#flushed, iclass 10, count 2 2006.182.08:29:30.37#ibcon#about to write, iclass 10, count 2 2006.182.08:29:30.37#ibcon#wrote, iclass 10, count 2 2006.182.08:29:30.37#ibcon#about to read 3, iclass 10, count 2 2006.182.08:29:30.39#ibcon#read 3, iclass 10, count 2 2006.182.08:29:30.39#ibcon#about to read 4, iclass 10, count 2 2006.182.08:29:30.39#ibcon#read 4, iclass 10, count 2 2006.182.08:29:30.39#ibcon#about to read 5, iclass 10, count 2 2006.182.08:29:30.39#ibcon#read 5, iclass 10, count 2 2006.182.08:29:30.39#ibcon#about to read 6, iclass 10, count 2 2006.182.08:29:30.39#ibcon#read 6, iclass 10, count 2 2006.182.08:29:30.39#ibcon#end of sib2, iclass 10, count 2 2006.182.08:29:30.39#ibcon#*mode == 0, iclass 10, count 2 2006.182.08:29:30.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.182.08:29:30.39#ibcon#[25=AT08-07\r\n] 2006.182.08:29:30.39#ibcon#*before write, iclass 10, count 2 2006.182.08:29:30.39#ibcon#enter sib2, iclass 10, count 2 2006.182.08:29:30.39#ibcon#flushed, iclass 10, count 2 2006.182.08:29:30.39#ibcon#about to write, iclass 10, count 2 2006.182.08:29:30.39#ibcon#wrote, iclass 10, count 2 2006.182.08:29:30.39#ibcon#about to read 3, iclass 10, count 2 2006.182.08:29:30.42#ibcon#read 3, iclass 10, count 2 2006.182.08:29:30.42#ibcon#about to read 4, iclass 10, count 2 2006.182.08:29:30.42#ibcon#read 4, iclass 10, count 2 2006.182.08:29:30.42#ibcon#about to read 5, iclass 10, count 2 2006.182.08:29:30.42#ibcon#read 5, iclass 10, count 2 2006.182.08:29:30.42#ibcon#about to read 6, iclass 10, count 2 2006.182.08:29:30.42#ibcon#read 6, iclass 10, count 2 2006.182.08:29:30.42#ibcon#end of sib2, iclass 10, count 2 2006.182.08:29:30.42#ibcon#*after write, iclass 10, count 2 2006.182.08:29:30.42#ibcon#*before return 0, iclass 10, count 2 2006.182.08:29:30.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:29:30.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.182.08:29:30.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.182.08:29:30.42#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:30.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:29:30.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:29:30.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:29:30.54#ibcon#enter wrdev, iclass 10, count 0 2006.182.08:29:30.54#ibcon#first serial, iclass 10, count 0 2006.182.08:29:30.54#ibcon#enter sib2, iclass 10, count 0 2006.182.08:29:30.54#ibcon#flushed, iclass 10, count 0 2006.182.08:29:30.54#ibcon#about to write, iclass 10, count 0 2006.182.08:29:30.54#ibcon#wrote, iclass 10, count 0 2006.182.08:29:30.54#ibcon#about to read 3, iclass 10, count 0 2006.182.08:29:30.56#ibcon#read 3, iclass 10, count 0 2006.182.08:29:30.56#ibcon#about to read 4, iclass 10, count 0 2006.182.08:29:30.56#ibcon#read 4, iclass 10, count 0 2006.182.08:29:30.56#ibcon#about to read 5, iclass 10, count 0 2006.182.08:29:30.56#ibcon#read 5, iclass 10, count 0 2006.182.08:29:30.56#ibcon#about to read 6, iclass 10, count 0 2006.182.08:29:30.56#ibcon#read 6, iclass 10, count 0 2006.182.08:29:30.56#ibcon#end of sib2, iclass 10, count 0 2006.182.08:29:30.56#ibcon#*mode == 0, iclass 10, count 0 2006.182.08:29:30.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.182.08:29:30.56#ibcon#[25=USB\r\n] 2006.182.08:29:30.56#ibcon#*before write, iclass 10, count 0 2006.182.08:29:30.56#ibcon#enter sib2, iclass 10, count 0 2006.182.08:29:30.56#ibcon#flushed, iclass 10, count 0 2006.182.08:29:30.56#ibcon#about to write, iclass 10, count 0 2006.182.08:29:30.56#ibcon#wrote, iclass 10, count 0 2006.182.08:29:30.56#ibcon#about to read 3, iclass 10, count 0 2006.182.08:29:30.59#ibcon#read 3, iclass 10, count 0 2006.182.08:29:30.59#ibcon#about to read 4, iclass 10, count 0 2006.182.08:29:30.59#ibcon#read 4, iclass 10, count 0 2006.182.08:29:30.59#ibcon#about to read 5, iclass 10, count 0 2006.182.08:29:30.59#ibcon#read 5, iclass 10, count 0 2006.182.08:29:30.59#ibcon#about to read 6, iclass 10, count 0 2006.182.08:29:30.59#ibcon#read 6, iclass 10, count 0 2006.182.08:29:30.59#ibcon#end of sib2, iclass 10, count 0 2006.182.08:29:30.59#ibcon#*after write, iclass 10, count 0 2006.182.08:29:30.59#ibcon#*before return 0, iclass 10, count 0 2006.182.08:29:30.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:29:30.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.182.08:29:30.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.182.08:29:30.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.182.08:29:30.59$vc4f8/vblo=1,632.99 2006.182.08:29:30.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.182.08:29:30.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.182.08:29:30.59#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:30.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:29:30.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:29:30.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:29:30.59#ibcon#enter wrdev, iclass 12, count 0 2006.182.08:29:30.59#ibcon#first serial, iclass 12, count 0 2006.182.08:29:30.59#ibcon#enter sib2, iclass 12, count 0 2006.182.08:29:30.59#ibcon#flushed, iclass 12, count 0 2006.182.08:29:30.59#ibcon#about to write, iclass 12, count 0 2006.182.08:29:30.59#ibcon#wrote, iclass 12, count 0 2006.182.08:29:30.59#ibcon#about to read 3, iclass 12, count 0 2006.182.08:29:30.61#ibcon#read 3, iclass 12, count 0 2006.182.08:29:30.61#ibcon#about to read 4, iclass 12, count 0 2006.182.08:29:30.61#ibcon#read 4, iclass 12, count 0 2006.182.08:29:30.61#ibcon#about to read 5, iclass 12, count 0 2006.182.08:29:30.61#ibcon#read 5, iclass 12, count 0 2006.182.08:29:30.61#ibcon#about to read 6, iclass 12, count 0 2006.182.08:29:30.61#ibcon#read 6, iclass 12, count 0 2006.182.08:29:30.61#ibcon#end of sib2, iclass 12, count 0 2006.182.08:29:30.61#ibcon#*mode == 0, iclass 12, count 0 2006.182.08:29:30.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.182.08:29:30.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.182.08:29:30.61#ibcon#*before write, iclass 12, count 0 2006.182.08:29:30.61#ibcon#enter sib2, iclass 12, count 0 2006.182.08:29:30.61#ibcon#flushed, iclass 12, count 0 2006.182.08:29:30.61#ibcon#about to write, iclass 12, count 0 2006.182.08:29:30.61#ibcon#wrote, iclass 12, count 0 2006.182.08:29:30.61#ibcon#about to read 3, iclass 12, count 0 2006.182.08:29:30.65#ibcon#read 3, iclass 12, count 0 2006.182.08:29:30.65#ibcon#about to read 4, iclass 12, count 0 2006.182.08:29:30.65#ibcon#read 4, iclass 12, count 0 2006.182.08:29:30.65#ibcon#about to read 5, iclass 12, count 0 2006.182.08:29:30.65#ibcon#read 5, iclass 12, count 0 2006.182.08:29:30.65#ibcon#about to read 6, iclass 12, count 0 2006.182.08:29:30.65#ibcon#read 6, iclass 12, count 0 2006.182.08:29:30.65#ibcon#end of sib2, iclass 12, count 0 2006.182.08:29:30.65#ibcon#*after write, iclass 12, count 0 2006.182.08:29:30.65#ibcon#*before return 0, iclass 12, count 0 2006.182.08:29:30.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:29:30.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.182.08:29:30.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.182.08:29:30.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.182.08:29:30.65$vc4f8/vb=1,4 2006.182.08:29:30.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.182.08:29:30.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.182.08:29:30.65#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:30.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:29:30.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:29:30.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:29:30.65#ibcon#enter wrdev, iclass 14, count 2 2006.182.08:29:30.65#ibcon#first serial, iclass 14, count 2 2006.182.08:29:30.65#ibcon#enter sib2, iclass 14, count 2 2006.182.08:29:30.65#ibcon#flushed, iclass 14, count 2 2006.182.08:29:30.65#ibcon#about to write, iclass 14, count 2 2006.182.08:29:30.65#ibcon#wrote, iclass 14, count 2 2006.182.08:29:30.65#ibcon#about to read 3, iclass 14, count 2 2006.182.08:29:30.67#ibcon#read 3, iclass 14, count 2 2006.182.08:29:30.67#ibcon#about to read 4, iclass 14, count 2 2006.182.08:29:30.67#ibcon#read 4, iclass 14, count 2 2006.182.08:29:30.67#ibcon#about to read 5, iclass 14, count 2 2006.182.08:29:30.67#ibcon#read 5, iclass 14, count 2 2006.182.08:29:30.67#ibcon#about to read 6, iclass 14, count 2 2006.182.08:29:30.67#ibcon#read 6, iclass 14, count 2 2006.182.08:29:30.67#ibcon#end of sib2, iclass 14, count 2 2006.182.08:29:30.67#ibcon#*mode == 0, iclass 14, count 2 2006.182.08:29:30.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.182.08:29:30.67#ibcon#[27=AT01-04\r\n] 2006.182.08:29:30.67#ibcon#*before write, iclass 14, count 2 2006.182.08:29:30.67#ibcon#enter sib2, iclass 14, count 2 2006.182.08:29:30.67#ibcon#flushed, iclass 14, count 2 2006.182.08:29:30.67#ibcon#about to write, iclass 14, count 2 2006.182.08:29:30.67#ibcon#wrote, iclass 14, count 2 2006.182.08:29:30.67#ibcon#about to read 3, iclass 14, count 2 2006.182.08:29:30.70#ibcon#read 3, iclass 14, count 2 2006.182.08:29:30.70#ibcon#about to read 4, iclass 14, count 2 2006.182.08:29:30.70#ibcon#read 4, iclass 14, count 2 2006.182.08:29:30.70#ibcon#about to read 5, iclass 14, count 2 2006.182.08:29:30.70#ibcon#read 5, iclass 14, count 2 2006.182.08:29:30.70#ibcon#about to read 6, iclass 14, count 2 2006.182.08:29:30.70#ibcon#read 6, iclass 14, count 2 2006.182.08:29:30.70#ibcon#end of sib2, iclass 14, count 2 2006.182.08:29:30.70#ibcon#*after write, iclass 14, count 2 2006.182.08:29:30.70#ibcon#*before return 0, iclass 14, count 2 2006.182.08:29:30.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:29:30.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.182.08:29:30.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.182.08:29:30.70#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:30.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:29:30.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:29:30.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:29:30.82#ibcon#enter wrdev, iclass 14, count 0 2006.182.08:29:30.82#ibcon#first serial, iclass 14, count 0 2006.182.08:29:30.82#ibcon#enter sib2, iclass 14, count 0 2006.182.08:29:30.82#ibcon#flushed, iclass 14, count 0 2006.182.08:29:30.82#ibcon#about to write, iclass 14, count 0 2006.182.08:29:30.82#ibcon#wrote, iclass 14, count 0 2006.182.08:29:30.82#ibcon#about to read 3, iclass 14, count 0 2006.182.08:29:30.84#ibcon#read 3, iclass 14, count 0 2006.182.08:29:30.84#ibcon#about to read 4, iclass 14, count 0 2006.182.08:29:30.84#ibcon#read 4, iclass 14, count 0 2006.182.08:29:30.84#ibcon#about to read 5, iclass 14, count 0 2006.182.08:29:30.84#ibcon#read 5, iclass 14, count 0 2006.182.08:29:30.84#ibcon#about to read 6, iclass 14, count 0 2006.182.08:29:30.84#ibcon#read 6, iclass 14, count 0 2006.182.08:29:30.84#ibcon#end of sib2, iclass 14, count 0 2006.182.08:29:30.84#ibcon#*mode == 0, iclass 14, count 0 2006.182.08:29:30.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.182.08:29:30.84#ibcon#[27=USB\r\n] 2006.182.08:29:30.84#ibcon#*before write, iclass 14, count 0 2006.182.08:29:30.84#ibcon#enter sib2, iclass 14, count 0 2006.182.08:29:30.84#ibcon#flushed, iclass 14, count 0 2006.182.08:29:30.84#ibcon#about to write, iclass 14, count 0 2006.182.08:29:30.84#ibcon#wrote, iclass 14, count 0 2006.182.08:29:30.84#ibcon#about to read 3, iclass 14, count 0 2006.182.08:29:30.87#ibcon#read 3, iclass 14, count 0 2006.182.08:29:30.87#ibcon#about to read 4, iclass 14, count 0 2006.182.08:29:30.87#ibcon#read 4, iclass 14, count 0 2006.182.08:29:30.87#ibcon#about to read 5, iclass 14, count 0 2006.182.08:29:30.87#ibcon#read 5, iclass 14, count 0 2006.182.08:29:30.87#ibcon#about to read 6, iclass 14, count 0 2006.182.08:29:30.87#ibcon#read 6, iclass 14, count 0 2006.182.08:29:30.87#ibcon#end of sib2, iclass 14, count 0 2006.182.08:29:30.87#ibcon#*after write, iclass 14, count 0 2006.182.08:29:30.87#ibcon#*before return 0, iclass 14, count 0 2006.182.08:29:30.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:29:30.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.182.08:29:30.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.182.08:29:30.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.182.08:29:30.87$vc4f8/vblo=2,640.99 2006.182.08:29:30.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.182.08:29:30.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.182.08:29:30.87#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:30.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:30.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:30.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:30.87#ibcon#enter wrdev, iclass 16, count 0 2006.182.08:29:30.87#ibcon#first serial, iclass 16, count 0 2006.182.08:29:30.87#ibcon#enter sib2, iclass 16, count 0 2006.182.08:29:30.87#ibcon#flushed, iclass 16, count 0 2006.182.08:29:30.87#ibcon#about to write, iclass 16, count 0 2006.182.08:29:30.87#ibcon#wrote, iclass 16, count 0 2006.182.08:29:30.87#ibcon#about to read 3, iclass 16, count 0 2006.182.08:29:30.89#ibcon#read 3, iclass 16, count 0 2006.182.08:29:30.89#ibcon#about to read 4, iclass 16, count 0 2006.182.08:29:30.89#ibcon#read 4, iclass 16, count 0 2006.182.08:29:30.89#ibcon#about to read 5, iclass 16, count 0 2006.182.08:29:30.89#ibcon#read 5, iclass 16, count 0 2006.182.08:29:30.89#ibcon#about to read 6, iclass 16, count 0 2006.182.08:29:30.89#ibcon#read 6, iclass 16, count 0 2006.182.08:29:30.89#ibcon#end of sib2, iclass 16, count 0 2006.182.08:29:30.89#ibcon#*mode == 0, iclass 16, count 0 2006.182.08:29:30.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.182.08:29:30.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.182.08:29:30.89#ibcon#*before write, iclass 16, count 0 2006.182.08:29:30.89#ibcon#enter sib2, iclass 16, count 0 2006.182.08:29:30.89#ibcon#flushed, iclass 16, count 0 2006.182.08:29:30.89#ibcon#about to write, iclass 16, count 0 2006.182.08:29:30.89#ibcon#wrote, iclass 16, count 0 2006.182.08:29:30.89#ibcon#about to read 3, iclass 16, count 0 2006.182.08:29:30.93#ibcon#read 3, iclass 16, count 0 2006.182.08:29:30.93#ibcon#about to read 4, iclass 16, count 0 2006.182.08:29:30.93#ibcon#read 4, iclass 16, count 0 2006.182.08:29:30.93#ibcon#about to read 5, iclass 16, count 0 2006.182.08:29:30.93#ibcon#read 5, iclass 16, count 0 2006.182.08:29:30.93#ibcon#about to read 6, iclass 16, count 0 2006.182.08:29:30.93#ibcon#read 6, iclass 16, count 0 2006.182.08:29:30.93#ibcon#end of sib2, iclass 16, count 0 2006.182.08:29:30.93#ibcon#*after write, iclass 16, count 0 2006.182.08:29:30.93#ibcon#*before return 0, iclass 16, count 0 2006.182.08:29:30.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:30.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.182.08:29:30.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.182.08:29:30.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.182.08:29:30.93$vc4f8/vb=2,4 2006.182.08:29:30.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.182.08:29:30.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.182.08:29:30.93#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:30.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:30.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:30.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:30.99#ibcon#enter wrdev, iclass 18, count 2 2006.182.08:29:30.99#ibcon#first serial, iclass 18, count 2 2006.182.08:29:30.99#ibcon#enter sib2, iclass 18, count 2 2006.182.08:29:30.99#ibcon#flushed, iclass 18, count 2 2006.182.08:29:30.99#ibcon#about to write, iclass 18, count 2 2006.182.08:29:30.99#ibcon#wrote, iclass 18, count 2 2006.182.08:29:30.99#ibcon#about to read 3, iclass 18, count 2 2006.182.08:29:31.01#ibcon#read 3, iclass 18, count 2 2006.182.08:29:31.01#ibcon#about to read 4, iclass 18, count 2 2006.182.08:29:31.01#ibcon#read 4, iclass 18, count 2 2006.182.08:29:31.01#ibcon#about to read 5, iclass 18, count 2 2006.182.08:29:31.01#ibcon#read 5, iclass 18, count 2 2006.182.08:29:31.01#ibcon#about to read 6, iclass 18, count 2 2006.182.08:29:31.01#ibcon#read 6, iclass 18, count 2 2006.182.08:29:31.01#ibcon#end of sib2, iclass 18, count 2 2006.182.08:29:31.01#ibcon#*mode == 0, iclass 18, count 2 2006.182.08:29:31.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.182.08:29:31.01#ibcon#[27=AT02-04\r\n] 2006.182.08:29:31.01#ibcon#*before write, iclass 18, count 2 2006.182.08:29:31.01#ibcon#enter sib2, iclass 18, count 2 2006.182.08:29:31.01#ibcon#flushed, iclass 18, count 2 2006.182.08:29:31.01#ibcon#about to write, iclass 18, count 2 2006.182.08:29:31.01#ibcon#wrote, iclass 18, count 2 2006.182.08:29:31.01#ibcon#about to read 3, iclass 18, count 2 2006.182.08:29:31.04#ibcon#read 3, iclass 18, count 2 2006.182.08:29:31.04#ibcon#about to read 4, iclass 18, count 2 2006.182.08:29:31.04#ibcon#read 4, iclass 18, count 2 2006.182.08:29:31.04#ibcon#about to read 5, iclass 18, count 2 2006.182.08:29:31.04#ibcon#read 5, iclass 18, count 2 2006.182.08:29:31.04#ibcon#about to read 6, iclass 18, count 2 2006.182.08:29:31.04#ibcon#read 6, iclass 18, count 2 2006.182.08:29:31.04#ibcon#end of sib2, iclass 18, count 2 2006.182.08:29:31.04#ibcon#*after write, iclass 18, count 2 2006.182.08:29:31.04#ibcon#*before return 0, iclass 18, count 2 2006.182.08:29:31.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:31.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.182.08:29:31.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.182.08:29:31.04#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:31.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:31.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:31.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:31.16#ibcon#enter wrdev, iclass 18, count 0 2006.182.08:29:31.16#ibcon#first serial, iclass 18, count 0 2006.182.08:29:31.16#ibcon#enter sib2, iclass 18, count 0 2006.182.08:29:31.16#ibcon#flushed, iclass 18, count 0 2006.182.08:29:31.16#ibcon#about to write, iclass 18, count 0 2006.182.08:29:31.16#ibcon#wrote, iclass 18, count 0 2006.182.08:29:31.16#ibcon#about to read 3, iclass 18, count 0 2006.182.08:29:31.18#ibcon#read 3, iclass 18, count 0 2006.182.08:29:31.18#ibcon#about to read 4, iclass 18, count 0 2006.182.08:29:31.18#ibcon#read 4, iclass 18, count 0 2006.182.08:29:31.18#ibcon#about to read 5, iclass 18, count 0 2006.182.08:29:31.18#ibcon#read 5, iclass 18, count 0 2006.182.08:29:31.18#ibcon#about to read 6, iclass 18, count 0 2006.182.08:29:31.18#ibcon#read 6, iclass 18, count 0 2006.182.08:29:31.18#ibcon#end of sib2, iclass 18, count 0 2006.182.08:29:31.18#ibcon#*mode == 0, iclass 18, count 0 2006.182.08:29:31.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.182.08:29:31.18#ibcon#[27=USB\r\n] 2006.182.08:29:31.18#ibcon#*before write, iclass 18, count 0 2006.182.08:29:31.18#ibcon#enter sib2, iclass 18, count 0 2006.182.08:29:31.18#ibcon#flushed, iclass 18, count 0 2006.182.08:29:31.18#ibcon#about to write, iclass 18, count 0 2006.182.08:29:31.18#ibcon#wrote, iclass 18, count 0 2006.182.08:29:31.18#ibcon#about to read 3, iclass 18, count 0 2006.182.08:29:31.21#ibcon#read 3, iclass 18, count 0 2006.182.08:29:31.21#ibcon#about to read 4, iclass 18, count 0 2006.182.08:29:31.21#ibcon#read 4, iclass 18, count 0 2006.182.08:29:31.21#ibcon#about to read 5, iclass 18, count 0 2006.182.08:29:31.21#ibcon#read 5, iclass 18, count 0 2006.182.08:29:31.21#ibcon#about to read 6, iclass 18, count 0 2006.182.08:29:31.21#ibcon#read 6, iclass 18, count 0 2006.182.08:29:31.21#ibcon#end of sib2, iclass 18, count 0 2006.182.08:29:31.21#ibcon#*after write, iclass 18, count 0 2006.182.08:29:31.21#ibcon#*before return 0, iclass 18, count 0 2006.182.08:29:31.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:31.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.182.08:29:31.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.182.08:29:31.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.182.08:29:31.21$vc4f8/vblo=3,656.99 2006.182.08:29:31.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.182.08:29:31.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.182.08:29:31.21#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:31.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:31.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:31.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:31.21#ibcon#enter wrdev, iclass 20, count 0 2006.182.08:29:31.21#ibcon#first serial, iclass 20, count 0 2006.182.08:29:31.21#ibcon#enter sib2, iclass 20, count 0 2006.182.08:29:31.21#ibcon#flushed, iclass 20, count 0 2006.182.08:29:31.21#ibcon#about to write, iclass 20, count 0 2006.182.08:29:31.21#ibcon#wrote, iclass 20, count 0 2006.182.08:29:31.21#ibcon#about to read 3, iclass 20, count 0 2006.182.08:29:31.23#ibcon#read 3, iclass 20, count 0 2006.182.08:29:31.23#ibcon#about to read 4, iclass 20, count 0 2006.182.08:29:31.23#ibcon#read 4, iclass 20, count 0 2006.182.08:29:31.23#ibcon#about to read 5, iclass 20, count 0 2006.182.08:29:31.23#ibcon#read 5, iclass 20, count 0 2006.182.08:29:31.23#ibcon#about to read 6, iclass 20, count 0 2006.182.08:29:31.23#ibcon#read 6, iclass 20, count 0 2006.182.08:29:31.23#ibcon#end of sib2, iclass 20, count 0 2006.182.08:29:31.23#ibcon#*mode == 0, iclass 20, count 0 2006.182.08:29:31.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.182.08:29:31.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.182.08:29:31.23#ibcon#*before write, iclass 20, count 0 2006.182.08:29:31.23#ibcon#enter sib2, iclass 20, count 0 2006.182.08:29:31.23#ibcon#flushed, iclass 20, count 0 2006.182.08:29:31.23#ibcon#about to write, iclass 20, count 0 2006.182.08:29:31.23#ibcon#wrote, iclass 20, count 0 2006.182.08:29:31.23#ibcon#about to read 3, iclass 20, count 0 2006.182.08:29:31.27#ibcon#read 3, iclass 20, count 0 2006.182.08:29:31.27#ibcon#about to read 4, iclass 20, count 0 2006.182.08:29:31.27#ibcon#read 4, iclass 20, count 0 2006.182.08:29:31.27#ibcon#about to read 5, iclass 20, count 0 2006.182.08:29:31.27#ibcon#read 5, iclass 20, count 0 2006.182.08:29:31.27#ibcon#about to read 6, iclass 20, count 0 2006.182.08:29:31.27#ibcon#read 6, iclass 20, count 0 2006.182.08:29:31.27#ibcon#end of sib2, iclass 20, count 0 2006.182.08:29:31.27#ibcon#*after write, iclass 20, count 0 2006.182.08:29:31.27#ibcon#*before return 0, iclass 20, count 0 2006.182.08:29:31.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:31.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.182.08:29:31.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.182.08:29:31.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.182.08:29:31.27$vc4f8/vb=3,4 2006.182.08:29:31.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.182.08:29:31.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.182.08:29:31.27#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:31.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:31.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:31.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:31.33#ibcon#enter wrdev, iclass 22, count 2 2006.182.08:29:31.33#ibcon#first serial, iclass 22, count 2 2006.182.08:29:31.33#ibcon#enter sib2, iclass 22, count 2 2006.182.08:29:31.33#ibcon#flushed, iclass 22, count 2 2006.182.08:29:31.33#ibcon#about to write, iclass 22, count 2 2006.182.08:29:31.33#ibcon#wrote, iclass 22, count 2 2006.182.08:29:31.33#ibcon#about to read 3, iclass 22, count 2 2006.182.08:29:31.35#ibcon#read 3, iclass 22, count 2 2006.182.08:29:31.35#ibcon#about to read 4, iclass 22, count 2 2006.182.08:29:31.35#ibcon#read 4, iclass 22, count 2 2006.182.08:29:31.35#ibcon#about to read 5, iclass 22, count 2 2006.182.08:29:31.35#ibcon#read 5, iclass 22, count 2 2006.182.08:29:31.35#ibcon#about to read 6, iclass 22, count 2 2006.182.08:29:31.35#ibcon#read 6, iclass 22, count 2 2006.182.08:29:31.35#ibcon#end of sib2, iclass 22, count 2 2006.182.08:29:31.35#ibcon#*mode == 0, iclass 22, count 2 2006.182.08:29:31.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.182.08:29:31.35#ibcon#[27=AT03-04\r\n] 2006.182.08:29:31.35#ibcon#*before write, iclass 22, count 2 2006.182.08:29:31.35#ibcon#enter sib2, iclass 22, count 2 2006.182.08:29:31.35#ibcon#flushed, iclass 22, count 2 2006.182.08:29:31.35#ibcon#about to write, iclass 22, count 2 2006.182.08:29:31.35#ibcon#wrote, iclass 22, count 2 2006.182.08:29:31.35#ibcon#about to read 3, iclass 22, count 2 2006.182.08:29:31.38#ibcon#read 3, iclass 22, count 2 2006.182.08:29:31.38#ibcon#about to read 4, iclass 22, count 2 2006.182.08:29:31.38#ibcon#read 4, iclass 22, count 2 2006.182.08:29:31.38#ibcon#about to read 5, iclass 22, count 2 2006.182.08:29:31.38#ibcon#read 5, iclass 22, count 2 2006.182.08:29:31.38#ibcon#about to read 6, iclass 22, count 2 2006.182.08:29:31.38#ibcon#read 6, iclass 22, count 2 2006.182.08:29:31.38#ibcon#end of sib2, iclass 22, count 2 2006.182.08:29:31.38#ibcon#*after write, iclass 22, count 2 2006.182.08:29:31.38#ibcon#*before return 0, iclass 22, count 2 2006.182.08:29:31.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:31.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.182.08:29:31.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.182.08:29:31.38#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:31.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:31.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:31.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:31.50#ibcon#enter wrdev, iclass 22, count 0 2006.182.08:29:31.50#ibcon#first serial, iclass 22, count 0 2006.182.08:29:31.50#ibcon#enter sib2, iclass 22, count 0 2006.182.08:29:31.50#ibcon#flushed, iclass 22, count 0 2006.182.08:29:31.50#ibcon#about to write, iclass 22, count 0 2006.182.08:29:31.50#ibcon#wrote, iclass 22, count 0 2006.182.08:29:31.50#ibcon#about to read 3, iclass 22, count 0 2006.182.08:29:31.52#ibcon#read 3, iclass 22, count 0 2006.182.08:29:31.52#ibcon#about to read 4, iclass 22, count 0 2006.182.08:29:31.52#ibcon#read 4, iclass 22, count 0 2006.182.08:29:31.52#ibcon#about to read 5, iclass 22, count 0 2006.182.08:29:31.52#ibcon#read 5, iclass 22, count 0 2006.182.08:29:31.52#ibcon#about to read 6, iclass 22, count 0 2006.182.08:29:31.52#ibcon#read 6, iclass 22, count 0 2006.182.08:29:31.52#ibcon#end of sib2, iclass 22, count 0 2006.182.08:29:31.52#ibcon#*mode == 0, iclass 22, count 0 2006.182.08:29:31.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.182.08:29:31.52#ibcon#[27=USB\r\n] 2006.182.08:29:31.52#ibcon#*before write, iclass 22, count 0 2006.182.08:29:31.52#ibcon#enter sib2, iclass 22, count 0 2006.182.08:29:31.52#ibcon#flushed, iclass 22, count 0 2006.182.08:29:31.52#ibcon#about to write, iclass 22, count 0 2006.182.08:29:31.52#ibcon#wrote, iclass 22, count 0 2006.182.08:29:31.52#ibcon#about to read 3, iclass 22, count 0 2006.182.08:29:31.55#ibcon#read 3, iclass 22, count 0 2006.182.08:29:31.55#ibcon#about to read 4, iclass 22, count 0 2006.182.08:29:31.55#ibcon#read 4, iclass 22, count 0 2006.182.08:29:31.55#ibcon#about to read 5, iclass 22, count 0 2006.182.08:29:31.55#ibcon#read 5, iclass 22, count 0 2006.182.08:29:31.55#ibcon#about to read 6, iclass 22, count 0 2006.182.08:29:31.55#ibcon#read 6, iclass 22, count 0 2006.182.08:29:31.55#ibcon#end of sib2, iclass 22, count 0 2006.182.08:29:31.55#ibcon#*after write, iclass 22, count 0 2006.182.08:29:31.55#ibcon#*before return 0, iclass 22, count 0 2006.182.08:29:31.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:31.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.182.08:29:31.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.182.08:29:31.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.182.08:29:31.55$vc4f8/vblo=4,712.99 2006.182.08:29:31.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.182.08:29:31.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.182.08:29:31.55#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:31.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:31.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:31.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:31.55#ibcon#enter wrdev, iclass 24, count 0 2006.182.08:29:31.55#ibcon#first serial, iclass 24, count 0 2006.182.08:29:31.55#ibcon#enter sib2, iclass 24, count 0 2006.182.08:29:31.55#ibcon#flushed, iclass 24, count 0 2006.182.08:29:31.55#ibcon#about to write, iclass 24, count 0 2006.182.08:29:31.55#ibcon#wrote, iclass 24, count 0 2006.182.08:29:31.55#ibcon#about to read 3, iclass 24, count 0 2006.182.08:29:31.57#ibcon#read 3, iclass 24, count 0 2006.182.08:29:31.57#ibcon#about to read 4, iclass 24, count 0 2006.182.08:29:31.57#ibcon#read 4, iclass 24, count 0 2006.182.08:29:31.57#ibcon#about to read 5, iclass 24, count 0 2006.182.08:29:31.57#ibcon#read 5, iclass 24, count 0 2006.182.08:29:31.57#ibcon#about to read 6, iclass 24, count 0 2006.182.08:29:31.57#ibcon#read 6, iclass 24, count 0 2006.182.08:29:31.57#ibcon#end of sib2, iclass 24, count 0 2006.182.08:29:31.57#ibcon#*mode == 0, iclass 24, count 0 2006.182.08:29:31.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.182.08:29:31.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.182.08:29:31.57#ibcon#*before write, iclass 24, count 0 2006.182.08:29:31.57#ibcon#enter sib2, iclass 24, count 0 2006.182.08:29:31.57#ibcon#flushed, iclass 24, count 0 2006.182.08:29:31.57#ibcon#about to write, iclass 24, count 0 2006.182.08:29:31.57#ibcon#wrote, iclass 24, count 0 2006.182.08:29:31.57#ibcon#about to read 3, iclass 24, count 0 2006.182.08:29:31.61#ibcon#read 3, iclass 24, count 0 2006.182.08:29:31.61#ibcon#about to read 4, iclass 24, count 0 2006.182.08:29:31.61#ibcon#read 4, iclass 24, count 0 2006.182.08:29:31.61#ibcon#about to read 5, iclass 24, count 0 2006.182.08:29:31.61#ibcon#read 5, iclass 24, count 0 2006.182.08:29:31.61#ibcon#about to read 6, iclass 24, count 0 2006.182.08:29:31.61#ibcon#read 6, iclass 24, count 0 2006.182.08:29:31.61#ibcon#end of sib2, iclass 24, count 0 2006.182.08:29:31.61#ibcon#*after write, iclass 24, count 0 2006.182.08:29:31.61#ibcon#*before return 0, iclass 24, count 0 2006.182.08:29:31.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:31.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.182.08:29:31.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.182.08:29:31.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.182.08:29:31.61$vc4f8/vb=4,4 2006.182.08:29:31.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.182.08:29:31.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.182.08:29:31.61#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:31.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:31.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:31.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:31.67#ibcon#enter wrdev, iclass 26, count 2 2006.182.08:29:31.67#ibcon#first serial, iclass 26, count 2 2006.182.08:29:31.67#ibcon#enter sib2, iclass 26, count 2 2006.182.08:29:31.67#ibcon#flushed, iclass 26, count 2 2006.182.08:29:31.67#ibcon#about to write, iclass 26, count 2 2006.182.08:29:31.67#ibcon#wrote, iclass 26, count 2 2006.182.08:29:31.67#ibcon#about to read 3, iclass 26, count 2 2006.182.08:29:31.69#ibcon#read 3, iclass 26, count 2 2006.182.08:29:31.69#ibcon#about to read 4, iclass 26, count 2 2006.182.08:29:31.69#ibcon#read 4, iclass 26, count 2 2006.182.08:29:31.69#ibcon#about to read 5, iclass 26, count 2 2006.182.08:29:31.69#ibcon#read 5, iclass 26, count 2 2006.182.08:29:31.69#ibcon#about to read 6, iclass 26, count 2 2006.182.08:29:31.69#ibcon#read 6, iclass 26, count 2 2006.182.08:29:31.69#ibcon#end of sib2, iclass 26, count 2 2006.182.08:29:31.69#ibcon#*mode == 0, iclass 26, count 2 2006.182.08:29:31.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.182.08:29:31.69#ibcon#[27=AT04-04\r\n] 2006.182.08:29:31.69#ibcon#*before write, iclass 26, count 2 2006.182.08:29:31.69#ibcon#enter sib2, iclass 26, count 2 2006.182.08:29:31.69#ibcon#flushed, iclass 26, count 2 2006.182.08:29:31.69#ibcon#about to write, iclass 26, count 2 2006.182.08:29:31.69#ibcon#wrote, iclass 26, count 2 2006.182.08:29:31.69#ibcon#about to read 3, iclass 26, count 2 2006.182.08:29:31.72#ibcon#read 3, iclass 26, count 2 2006.182.08:29:31.72#ibcon#about to read 4, iclass 26, count 2 2006.182.08:29:31.72#ibcon#read 4, iclass 26, count 2 2006.182.08:29:31.72#ibcon#about to read 5, iclass 26, count 2 2006.182.08:29:31.72#ibcon#read 5, iclass 26, count 2 2006.182.08:29:31.72#ibcon#about to read 6, iclass 26, count 2 2006.182.08:29:31.72#ibcon#read 6, iclass 26, count 2 2006.182.08:29:31.72#ibcon#end of sib2, iclass 26, count 2 2006.182.08:29:31.72#ibcon#*after write, iclass 26, count 2 2006.182.08:29:31.72#ibcon#*before return 0, iclass 26, count 2 2006.182.08:29:31.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:31.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.182.08:29:31.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.182.08:29:31.72#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:31.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:31.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:31.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:31.84#ibcon#enter wrdev, iclass 26, count 0 2006.182.08:29:31.84#ibcon#first serial, iclass 26, count 0 2006.182.08:29:31.84#ibcon#enter sib2, iclass 26, count 0 2006.182.08:29:31.84#ibcon#flushed, iclass 26, count 0 2006.182.08:29:31.84#ibcon#about to write, iclass 26, count 0 2006.182.08:29:31.84#ibcon#wrote, iclass 26, count 0 2006.182.08:29:31.84#ibcon#about to read 3, iclass 26, count 0 2006.182.08:29:31.86#ibcon#read 3, iclass 26, count 0 2006.182.08:29:31.86#ibcon#about to read 4, iclass 26, count 0 2006.182.08:29:31.86#ibcon#read 4, iclass 26, count 0 2006.182.08:29:31.86#ibcon#about to read 5, iclass 26, count 0 2006.182.08:29:31.86#ibcon#read 5, iclass 26, count 0 2006.182.08:29:31.86#ibcon#about to read 6, iclass 26, count 0 2006.182.08:29:31.86#ibcon#read 6, iclass 26, count 0 2006.182.08:29:31.86#ibcon#end of sib2, iclass 26, count 0 2006.182.08:29:31.86#ibcon#*mode == 0, iclass 26, count 0 2006.182.08:29:31.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.182.08:29:31.86#ibcon#[27=USB\r\n] 2006.182.08:29:31.86#ibcon#*before write, iclass 26, count 0 2006.182.08:29:31.86#ibcon#enter sib2, iclass 26, count 0 2006.182.08:29:31.86#ibcon#flushed, iclass 26, count 0 2006.182.08:29:31.86#ibcon#about to write, iclass 26, count 0 2006.182.08:29:31.86#ibcon#wrote, iclass 26, count 0 2006.182.08:29:31.86#ibcon#about to read 3, iclass 26, count 0 2006.182.08:29:31.89#ibcon#read 3, iclass 26, count 0 2006.182.08:29:31.89#ibcon#about to read 4, iclass 26, count 0 2006.182.08:29:31.89#ibcon#read 4, iclass 26, count 0 2006.182.08:29:31.89#ibcon#about to read 5, iclass 26, count 0 2006.182.08:29:31.89#ibcon#read 5, iclass 26, count 0 2006.182.08:29:31.89#ibcon#about to read 6, iclass 26, count 0 2006.182.08:29:31.89#ibcon#read 6, iclass 26, count 0 2006.182.08:29:31.89#ibcon#end of sib2, iclass 26, count 0 2006.182.08:29:31.89#ibcon#*after write, iclass 26, count 0 2006.182.08:29:31.89#ibcon#*before return 0, iclass 26, count 0 2006.182.08:29:31.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:31.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.182.08:29:31.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.182.08:29:31.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.182.08:29:31.89$vc4f8/vblo=5,744.99 2006.182.08:29:31.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.182.08:29:31.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.182.08:29:31.89#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:31.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:31.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:31.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:31.89#ibcon#enter wrdev, iclass 28, count 0 2006.182.08:29:31.89#ibcon#first serial, iclass 28, count 0 2006.182.08:29:31.89#ibcon#enter sib2, iclass 28, count 0 2006.182.08:29:31.89#ibcon#flushed, iclass 28, count 0 2006.182.08:29:31.89#ibcon#about to write, iclass 28, count 0 2006.182.08:29:31.89#ibcon#wrote, iclass 28, count 0 2006.182.08:29:31.89#ibcon#about to read 3, iclass 28, count 0 2006.182.08:29:31.91#ibcon#read 3, iclass 28, count 0 2006.182.08:29:31.91#ibcon#about to read 4, iclass 28, count 0 2006.182.08:29:31.91#ibcon#read 4, iclass 28, count 0 2006.182.08:29:31.91#ibcon#about to read 5, iclass 28, count 0 2006.182.08:29:31.91#ibcon#read 5, iclass 28, count 0 2006.182.08:29:31.91#ibcon#about to read 6, iclass 28, count 0 2006.182.08:29:31.91#ibcon#read 6, iclass 28, count 0 2006.182.08:29:31.91#ibcon#end of sib2, iclass 28, count 0 2006.182.08:29:31.91#ibcon#*mode == 0, iclass 28, count 0 2006.182.08:29:31.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.182.08:29:31.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.182.08:29:31.91#ibcon#*before write, iclass 28, count 0 2006.182.08:29:31.91#ibcon#enter sib2, iclass 28, count 0 2006.182.08:29:31.91#ibcon#flushed, iclass 28, count 0 2006.182.08:29:31.91#ibcon#about to write, iclass 28, count 0 2006.182.08:29:31.91#ibcon#wrote, iclass 28, count 0 2006.182.08:29:31.91#ibcon#about to read 3, iclass 28, count 0 2006.182.08:29:31.96#ibcon#read 3, iclass 28, count 0 2006.182.08:29:31.96#ibcon#about to read 4, iclass 28, count 0 2006.182.08:29:31.96#ibcon#read 4, iclass 28, count 0 2006.182.08:29:31.96#ibcon#about to read 5, iclass 28, count 0 2006.182.08:29:31.96#ibcon#read 5, iclass 28, count 0 2006.182.08:29:31.96#ibcon#about to read 6, iclass 28, count 0 2006.182.08:29:31.96#ibcon#read 6, iclass 28, count 0 2006.182.08:29:31.96#ibcon#end of sib2, iclass 28, count 0 2006.182.08:29:31.96#ibcon#*after write, iclass 28, count 0 2006.182.08:29:31.96#ibcon#*before return 0, iclass 28, count 0 2006.182.08:29:31.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:31.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.182.08:29:31.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.182.08:29:31.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.182.08:29:31.96$vc4f8/vb=5,4 2006.182.08:29:31.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.182.08:29:31.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.182.08:29:31.96#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:31.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:32.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:32.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:32.01#ibcon#enter wrdev, iclass 30, count 2 2006.182.08:29:32.01#ibcon#first serial, iclass 30, count 2 2006.182.08:29:32.01#ibcon#enter sib2, iclass 30, count 2 2006.182.08:29:32.01#ibcon#flushed, iclass 30, count 2 2006.182.08:29:32.01#ibcon#about to write, iclass 30, count 2 2006.182.08:29:32.01#ibcon#wrote, iclass 30, count 2 2006.182.08:29:32.01#ibcon#about to read 3, iclass 30, count 2 2006.182.08:29:32.03#ibcon#read 3, iclass 30, count 2 2006.182.08:29:32.03#ibcon#about to read 4, iclass 30, count 2 2006.182.08:29:32.03#ibcon#read 4, iclass 30, count 2 2006.182.08:29:32.03#ibcon#about to read 5, iclass 30, count 2 2006.182.08:29:32.03#ibcon#read 5, iclass 30, count 2 2006.182.08:29:32.03#ibcon#about to read 6, iclass 30, count 2 2006.182.08:29:32.03#ibcon#read 6, iclass 30, count 2 2006.182.08:29:32.03#ibcon#end of sib2, iclass 30, count 2 2006.182.08:29:32.03#ibcon#*mode == 0, iclass 30, count 2 2006.182.08:29:32.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.182.08:29:32.03#ibcon#[27=AT05-04\r\n] 2006.182.08:29:32.03#ibcon#*before write, iclass 30, count 2 2006.182.08:29:32.03#ibcon#enter sib2, iclass 30, count 2 2006.182.08:29:32.03#ibcon#flushed, iclass 30, count 2 2006.182.08:29:32.03#ibcon#about to write, iclass 30, count 2 2006.182.08:29:32.03#ibcon#wrote, iclass 30, count 2 2006.182.08:29:32.03#ibcon#about to read 3, iclass 30, count 2 2006.182.08:29:32.06#ibcon#read 3, iclass 30, count 2 2006.182.08:29:32.06#ibcon#about to read 4, iclass 30, count 2 2006.182.08:29:32.06#ibcon#read 4, iclass 30, count 2 2006.182.08:29:32.06#ibcon#about to read 5, iclass 30, count 2 2006.182.08:29:32.06#ibcon#read 5, iclass 30, count 2 2006.182.08:29:32.06#ibcon#about to read 6, iclass 30, count 2 2006.182.08:29:32.06#ibcon#read 6, iclass 30, count 2 2006.182.08:29:32.06#ibcon#end of sib2, iclass 30, count 2 2006.182.08:29:32.06#ibcon#*after write, iclass 30, count 2 2006.182.08:29:32.06#ibcon#*before return 0, iclass 30, count 2 2006.182.08:29:32.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:32.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.182.08:29:32.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.182.08:29:32.06#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:32.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:32.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:32.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:32.18#ibcon#enter wrdev, iclass 30, count 0 2006.182.08:29:32.18#ibcon#first serial, iclass 30, count 0 2006.182.08:29:32.18#ibcon#enter sib2, iclass 30, count 0 2006.182.08:29:32.18#ibcon#flushed, iclass 30, count 0 2006.182.08:29:32.18#ibcon#about to write, iclass 30, count 0 2006.182.08:29:32.18#ibcon#wrote, iclass 30, count 0 2006.182.08:29:32.18#ibcon#about to read 3, iclass 30, count 0 2006.182.08:29:32.20#ibcon#read 3, iclass 30, count 0 2006.182.08:29:32.20#ibcon#about to read 4, iclass 30, count 0 2006.182.08:29:32.20#ibcon#read 4, iclass 30, count 0 2006.182.08:29:32.20#ibcon#about to read 5, iclass 30, count 0 2006.182.08:29:32.20#ibcon#read 5, iclass 30, count 0 2006.182.08:29:32.20#ibcon#about to read 6, iclass 30, count 0 2006.182.08:29:32.20#ibcon#read 6, iclass 30, count 0 2006.182.08:29:32.20#ibcon#end of sib2, iclass 30, count 0 2006.182.08:29:32.20#ibcon#*mode == 0, iclass 30, count 0 2006.182.08:29:32.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.182.08:29:32.20#ibcon#[27=USB\r\n] 2006.182.08:29:32.20#ibcon#*before write, iclass 30, count 0 2006.182.08:29:32.20#ibcon#enter sib2, iclass 30, count 0 2006.182.08:29:32.20#ibcon#flushed, iclass 30, count 0 2006.182.08:29:32.20#ibcon#about to write, iclass 30, count 0 2006.182.08:29:32.20#ibcon#wrote, iclass 30, count 0 2006.182.08:29:32.20#ibcon#about to read 3, iclass 30, count 0 2006.182.08:29:32.23#ibcon#read 3, iclass 30, count 0 2006.182.08:29:32.23#ibcon#about to read 4, iclass 30, count 0 2006.182.08:29:32.23#ibcon#read 4, iclass 30, count 0 2006.182.08:29:32.23#ibcon#about to read 5, iclass 30, count 0 2006.182.08:29:32.23#ibcon#read 5, iclass 30, count 0 2006.182.08:29:32.23#ibcon#about to read 6, iclass 30, count 0 2006.182.08:29:32.23#ibcon#read 6, iclass 30, count 0 2006.182.08:29:32.23#ibcon#end of sib2, iclass 30, count 0 2006.182.08:29:32.23#ibcon#*after write, iclass 30, count 0 2006.182.08:29:32.23#ibcon#*before return 0, iclass 30, count 0 2006.182.08:29:32.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:32.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.182.08:29:32.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.182.08:29:32.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.182.08:29:32.23$vc4f8/vblo=6,752.99 2006.182.08:29:32.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.182.08:29:32.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.182.08:29:32.23#ibcon#ireg 17 cls_cnt 0 2006.182.08:29:32.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:32.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:32.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:32.23#ibcon#enter wrdev, iclass 32, count 0 2006.182.08:29:32.23#ibcon#first serial, iclass 32, count 0 2006.182.08:29:32.23#ibcon#enter sib2, iclass 32, count 0 2006.182.08:29:32.23#ibcon#flushed, iclass 32, count 0 2006.182.08:29:32.23#ibcon#about to write, iclass 32, count 0 2006.182.08:29:32.23#ibcon#wrote, iclass 32, count 0 2006.182.08:29:32.23#ibcon#about to read 3, iclass 32, count 0 2006.182.08:29:32.25#ibcon#read 3, iclass 32, count 0 2006.182.08:29:32.25#ibcon#about to read 4, iclass 32, count 0 2006.182.08:29:32.25#ibcon#read 4, iclass 32, count 0 2006.182.08:29:32.25#ibcon#about to read 5, iclass 32, count 0 2006.182.08:29:32.25#ibcon#read 5, iclass 32, count 0 2006.182.08:29:32.25#ibcon#about to read 6, iclass 32, count 0 2006.182.08:29:32.25#ibcon#read 6, iclass 32, count 0 2006.182.08:29:32.25#ibcon#end of sib2, iclass 32, count 0 2006.182.08:29:32.25#ibcon#*mode == 0, iclass 32, count 0 2006.182.08:29:32.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.182.08:29:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.182.08:29:32.25#ibcon#*before write, iclass 32, count 0 2006.182.08:29:32.25#ibcon#enter sib2, iclass 32, count 0 2006.182.08:29:32.25#ibcon#flushed, iclass 32, count 0 2006.182.08:29:32.25#ibcon#about to write, iclass 32, count 0 2006.182.08:29:32.25#ibcon#wrote, iclass 32, count 0 2006.182.08:29:32.25#ibcon#about to read 3, iclass 32, count 0 2006.182.08:29:32.29#ibcon#read 3, iclass 32, count 0 2006.182.08:29:32.29#ibcon#about to read 4, iclass 32, count 0 2006.182.08:29:32.29#ibcon#read 4, iclass 32, count 0 2006.182.08:29:32.29#ibcon#about to read 5, iclass 32, count 0 2006.182.08:29:32.29#ibcon#read 5, iclass 32, count 0 2006.182.08:29:32.29#ibcon#about to read 6, iclass 32, count 0 2006.182.08:29:32.29#ibcon#read 6, iclass 32, count 0 2006.182.08:29:32.29#ibcon#end of sib2, iclass 32, count 0 2006.182.08:29:32.29#ibcon#*after write, iclass 32, count 0 2006.182.08:29:32.29#ibcon#*before return 0, iclass 32, count 0 2006.182.08:29:32.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:32.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.182.08:29:32.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.182.08:29:32.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.182.08:29:32.29$vc4f8/vb=6,4 2006.182.08:29:32.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.182.08:29:32.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.182.08:29:32.29#ibcon#ireg 11 cls_cnt 2 2006.182.08:29:32.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:32.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:32.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:32.35#ibcon#enter wrdev, iclass 34, count 2 2006.182.08:29:32.35#ibcon#first serial, iclass 34, count 2 2006.182.08:29:32.35#ibcon#enter sib2, iclass 34, count 2 2006.182.08:29:32.35#ibcon#flushed, iclass 34, count 2 2006.182.08:29:32.35#ibcon#about to write, iclass 34, count 2 2006.182.08:29:32.35#ibcon#wrote, iclass 34, count 2 2006.182.08:29:32.35#ibcon#about to read 3, iclass 34, count 2 2006.182.08:29:32.37#ibcon#read 3, iclass 34, count 2 2006.182.08:29:32.37#ibcon#about to read 4, iclass 34, count 2 2006.182.08:29:32.37#ibcon#read 4, iclass 34, count 2 2006.182.08:29:32.37#ibcon#about to read 5, iclass 34, count 2 2006.182.08:29:32.37#ibcon#read 5, iclass 34, count 2 2006.182.08:29:32.37#ibcon#about to read 6, iclass 34, count 2 2006.182.08:29:32.37#ibcon#read 6, iclass 34, count 2 2006.182.08:29:32.37#ibcon#end of sib2, iclass 34, count 2 2006.182.08:29:32.37#ibcon#*mode == 0, iclass 34, count 2 2006.182.08:29:32.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.182.08:29:32.37#ibcon#[27=AT06-04\r\n] 2006.182.08:29:32.37#ibcon#*before write, iclass 34, count 2 2006.182.08:29:32.37#ibcon#enter sib2, iclass 34, count 2 2006.182.08:29:32.37#ibcon#flushed, iclass 34, count 2 2006.182.08:29:32.37#ibcon#about to write, iclass 34, count 2 2006.182.08:29:32.37#ibcon#wrote, iclass 34, count 2 2006.182.08:29:32.37#ibcon#about to read 3, iclass 34, count 2 2006.182.08:29:32.40#ibcon#read 3, iclass 34, count 2 2006.182.08:29:32.40#ibcon#about to read 4, iclass 34, count 2 2006.182.08:29:32.40#ibcon#read 4, iclass 34, count 2 2006.182.08:29:32.40#ibcon#about to read 5, iclass 34, count 2 2006.182.08:29:32.40#ibcon#read 5, iclass 34, count 2 2006.182.08:29:32.40#ibcon#about to read 6, iclass 34, count 2 2006.182.08:29:32.40#ibcon#read 6, iclass 34, count 2 2006.182.08:29:32.40#ibcon#end of sib2, iclass 34, count 2 2006.182.08:29:32.40#ibcon#*after write, iclass 34, count 2 2006.182.08:29:32.40#ibcon#*before return 0, iclass 34, count 2 2006.182.08:29:32.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:32.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.182.08:29:32.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.182.08:29:32.40#ibcon#ireg 7 cls_cnt 0 2006.182.08:29:32.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:32.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:32.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:32.52#ibcon#enter wrdev, iclass 34, count 0 2006.182.08:29:32.52#ibcon#first serial, iclass 34, count 0 2006.182.08:29:32.52#ibcon#enter sib2, iclass 34, count 0 2006.182.08:29:32.52#ibcon#flushed, iclass 34, count 0 2006.182.08:29:32.52#ibcon#about to write, iclass 34, count 0 2006.182.08:29:32.52#ibcon#wrote, iclass 34, count 0 2006.182.08:29:32.52#ibcon#about to read 3, iclass 34, count 0 2006.182.08:29:32.54#ibcon#read 3, iclass 34, count 0 2006.182.08:29:32.54#ibcon#about to read 4, iclass 34, count 0 2006.182.08:29:32.54#ibcon#read 4, iclass 34, count 0 2006.182.08:29:32.54#ibcon#about to read 5, iclass 34, count 0 2006.182.08:29:32.54#ibcon#read 5, iclass 34, count 0 2006.182.08:29:32.54#ibcon#about to read 6, iclass 34, count 0 2006.182.08:29:32.54#ibcon#read 6, iclass 34, count 0 2006.182.08:29:32.54#ibcon#end of sib2, iclass 34, count 0 2006.182.08:29:32.54#ibcon#*mode == 0, iclass 34, count 0 2006.182.08:29:32.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.182.08:29:32.54#ibcon#[27=USB\r\n] 2006.182.08:29:32.54#ibcon#*before write, iclass 34, count 0 2006.182.08:29:32.54#ibcon#enter sib2, iclass 34, count 0 2006.182.08:29:32.54#ibcon#flushed, iclass 34, count 0 2006.182.08:29:32.54#ibcon#about to write, iclass 34, count 0 2006.182.08:29:32.54#ibcon#wrote, iclass 34, count 0 2006.182.08:29:32.54#ibcon#about to read 3, iclass 34, count 0 2006.182.08:29:32.57#ibcon#read 3, iclass 34, count 0 2006.182.08:29:32.57#ibcon#about to read 4, iclass 34, count 0 2006.182.08:29:32.57#ibcon#read 4, iclass 34, count 0 2006.182.08:29:32.57#ibcon#about to read 5, iclass 34, count 0 2006.182.08:29:32.57#ibcon#read 5, iclass 34, count 0 2006.182.08:29:32.57#ibcon#about to read 6, iclass 34, count 0 2006.182.08:29:32.57#ibcon#read 6, iclass 34, count 0 2006.182.08:29:32.57#ibcon#end of sib2, iclass 34, count 0 2006.182.08:29:32.57#ibcon#*after write, iclass 34, count 0 2006.182.08:29:32.57#ibcon#*before return 0, iclass 34, count 0 2006.182.08:29:32.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:32.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.182.08:29:32.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.182.08:29:32.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.182.08:29:32.57$vc4f8/vabw=wide 2006.182.08:29:32.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.182.08:29:32.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.182.08:29:32.57#ibcon#ireg 8 cls_cnt 0 2006.182.08:29:32.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:32.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:32.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:32.57#ibcon#enter wrdev, iclass 36, count 0 2006.182.08:29:32.57#ibcon#first serial, iclass 36, count 0 2006.182.08:29:32.57#ibcon#enter sib2, iclass 36, count 0 2006.182.08:29:32.57#ibcon#flushed, iclass 36, count 0 2006.182.08:29:32.57#ibcon#about to write, iclass 36, count 0 2006.182.08:29:32.57#ibcon#wrote, iclass 36, count 0 2006.182.08:29:32.57#ibcon#about to read 3, iclass 36, count 0 2006.182.08:29:32.59#ibcon#read 3, iclass 36, count 0 2006.182.08:29:32.59#ibcon#about to read 4, iclass 36, count 0 2006.182.08:29:32.59#ibcon#read 4, iclass 36, count 0 2006.182.08:29:32.59#ibcon#about to read 5, iclass 36, count 0 2006.182.08:29:32.59#ibcon#read 5, iclass 36, count 0 2006.182.08:29:32.59#ibcon#about to read 6, iclass 36, count 0 2006.182.08:29:32.59#ibcon#read 6, iclass 36, count 0 2006.182.08:29:32.59#ibcon#end of sib2, iclass 36, count 0 2006.182.08:29:32.59#ibcon#*mode == 0, iclass 36, count 0 2006.182.08:29:32.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.182.08:29:32.59#ibcon#[25=BW32\r\n] 2006.182.08:29:32.59#ibcon#*before write, iclass 36, count 0 2006.182.08:29:32.59#ibcon#enter sib2, iclass 36, count 0 2006.182.08:29:32.59#ibcon#flushed, iclass 36, count 0 2006.182.08:29:32.59#ibcon#about to write, iclass 36, count 0 2006.182.08:29:32.59#ibcon#wrote, iclass 36, count 0 2006.182.08:29:32.59#ibcon#about to read 3, iclass 36, count 0 2006.182.08:29:32.63#ibcon#read 3, iclass 36, count 0 2006.182.08:29:32.63#ibcon#about to read 4, iclass 36, count 0 2006.182.08:29:32.63#ibcon#read 4, iclass 36, count 0 2006.182.08:29:32.63#ibcon#about to read 5, iclass 36, count 0 2006.182.08:29:32.63#ibcon#read 5, iclass 36, count 0 2006.182.08:29:32.63#ibcon#about to read 6, iclass 36, count 0 2006.182.08:29:32.63#ibcon#read 6, iclass 36, count 0 2006.182.08:29:32.63#ibcon#end of sib2, iclass 36, count 0 2006.182.08:29:32.63#ibcon#*after write, iclass 36, count 0 2006.182.08:29:32.63#ibcon#*before return 0, iclass 36, count 0 2006.182.08:29:32.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:32.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.182.08:29:32.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.182.08:29:32.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.182.08:29:32.63$vc4f8/vbbw=wide 2006.182.08:29:32.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.182.08:29:32.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.182.08:29:32.63#ibcon#ireg 8 cls_cnt 0 2006.182.08:29:32.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:29:32.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:29:32.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:29:32.69#ibcon#enter wrdev, iclass 38, count 0 2006.182.08:29:32.69#ibcon#first serial, iclass 38, count 0 2006.182.08:29:32.69#ibcon#enter sib2, iclass 38, count 0 2006.182.08:29:32.69#ibcon#flushed, iclass 38, count 0 2006.182.08:29:32.69#ibcon#about to write, iclass 38, count 0 2006.182.08:29:32.69#ibcon#wrote, iclass 38, count 0 2006.182.08:29:32.69#ibcon#about to read 3, iclass 38, count 0 2006.182.08:29:32.71#ibcon#read 3, iclass 38, count 0 2006.182.08:29:32.71#ibcon#about to read 4, iclass 38, count 0 2006.182.08:29:32.71#ibcon#read 4, iclass 38, count 0 2006.182.08:29:32.71#ibcon#about to read 5, iclass 38, count 0 2006.182.08:29:32.71#ibcon#read 5, iclass 38, count 0 2006.182.08:29:32.71#ibcon#about to read 6, iclass 38, count 0 2006.182.08:29:32.71#ibcon#read 6, iclass 38, count 0 2006.182.08:29:32.71#ibcon#end of sib2, iclass 38, count 0 2006.182.08:29:32.71#ibcon#*mode == 0, iclass 38, count 0 2006.182.08:29:32.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.182.08:29:32.71#ibcon#[27=BW32\r\n] 2006.182.08:29:32.71#ibcon#*before write, iclass 38, count 0 2006.182.08:29:32.71#ibcon#enter sib2, iclass 38, count 0 2006.182.08:29:32.71#ibcon#flushed, iclass 38, count 0 2006.182.08:29:32.71#ibcon#about to write, iclass 38, count 0 2006.182.08:29:32.71#ibcon#wrote, iclass 38, count 0 2006.182.08:29:32.71#ibcon#about to read 3, iclass 38, count 0 2006.182.08:29:32.74#ibcon#read 3, iclass 38, count 0 2006.182.08:29:32.74#ibcon#about to read 4, iclass 38, count 0 2006.182.08:29:32.74#ibcon#read 4, iclass 38, count 0 2006.182.08:29:32.74#ibcon#about to read 5, iclass 38, count 0 2006.182.08:29:32.74#ibcon#read 5, iclass 38, count 0 2006.182.08:29:32.74#ibcon#about to read 6, iclass 38, count 0 2006.182.08:29:32.74#ibcon#read 6, iclass 38, count 0 2006.182.08:29:32.74#ibcon#end of sib2, iclass 38, count 0 2006.182.08:29:32.74#ibcon#*after write, iclass 38, count 0 2006.182.08:29:32.74#ibcon#*before return 0, iclass 38, count 0 2006.182.08:29:32.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:29:32.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.182.08:29:32.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.182.08:29:32.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.182.08:29:32.74$4f8m12a/ifd4f 2006.182.08:29:32.74$ifd4f/lo= 2006.182.08:29:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.182.08:29:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.182.08:29:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.182.08:29:32.74$ifd4f/patch= 2006.182.08:29:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.182.08:29:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.182.08:29:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.182.08:29:32.74$4f8m12a/"form=m,16.000,1:2 2006.182.08:29:32.74$4f8m12a/"tpicd 2006.182.08:29:32.74$4f8m12a/echo=off 2006.182.08:29:32.74$4f8m12a/xlog=off 2006.182.08:29:32.74:!2006.182.08:30:00 2006.182.08:29:42.14#trakl#Source acquired 2006.182.08:29:42.14#flagr#flagr/antenna,acquired 2006.182.08:30:00.00:preob 2006.182.08:30:01.14/onsource/TRACKING 2006.182.08:30:01.14:!2006.182.08:30:10 2006.182.08:30:10.00:data_valid=on 2006.182.08:30:10.00:midob 2006.182.08:30:10.14/onsource/TRACKING 2006.182.08:30:10.14/wx/27.58,1002.9,80 2006.182.08:30:10.30/cable/+6.4624E-03 2006.182.08:30:11.39/va/01,08,usb,yes,34,36 2006.182.08:30:11.39/va/02,07,usb,yes,34,36 2006.182.08:30:11.39/va/03,06,usb,yes,36,36 2006.182.08:30:11.39/va/04,07,usb,yes,35,38 2006.182.08:30:11.39/va/05,07,usb,yes,37,39 2006.182.08:30:11.39/va/06,06,usb,yes,36,36 2006.182.08:30:11.39/va/07,06,usb,yes,36,36 2006.182.08:30:11.39/va/08,07,usb,yes,35,34 2006.182.08:30:11.62/valo/01,532.99,yes,locked 2006.182.08:30:11.62/valo/02,572.99,yes,locked 2006.182.08:30:11.62/valo/03,672.99,yes,locked 2006.182.08:30:11.62/valo/04,832.99,yes,locked 2006.182.08:30:11.62/valo/05,652.99,yes,locked 2006.182.08:30:11.62/valo/06,772.99,yes,locked 2006.182.08:30:11.62/valo/07,832.99,yes,locked 2006.182.08:30:11.62/valo/08,852.99,yes,locked 2006.182.08:30:12.71/vb/01,04,usb,yes,32,31 2006.182.08:30:12.71/vb/02,04,usb,yes,34,36 2006.182.08:30:12.71/vb/03,04,usb,yes,30,34 2006.182.08:30:12.71/vb/04,04,usb,yes,32,32 2006.182.08:30:12.71/vb/05,04,usb,yes,30,34 2006.182.08:30:12.71/vb/06,04,usb,yes,31,34 2006.182.08:30:12.71/vb/07,04,usb,yes,33,33 2006.182.08:30:12.71/vb/08,04,usb,yes,30,34 2006.182.08:30:12.95/vblo/01,632.99,yes,locked 2006.182.08:30:12.95/vblo/02,640.99,yes,locked 2006.182.08:30:12.95/vblo/03,656.99,yes,locked 2006.182.08:30:12.95/vblo/04,712.99,yes,locked 2006.182.08:30:12.95/vblo/05,744.99,yes,locked 2006.182.08:30:12.95/vblo/06,752.99,yes,locked 2006.182.08:30:12.95/vblo/07,734.99,yes,locked 2006.182.08:30:12.95/vblo/08,744.99,yes,locked 2006.182.08:30:13.10/vabw/8 2006.182.08:30:13.25/vbbw/8 2006.182.08:30:13.34/xfe/off,on,15.2 2006.182.08:30:13.71/ifatt/23,28,28,28 2006.182.08:30:14.08/fmout-gps/S +3.49E-07 2006.182.08:30:14.15:!2006.182.08:31:10 2006.182.08:31:10.00:data_valid=off 2006.182.08:31:10.00:postob 2006.182.08:31:10.21/cable/+6.4613E-03 2006.182.08:31:10.21/wx/27.56,1002.8,80 2006.182.08:31:11.08/fmout-gps/S +3.48E-07 2006.182.08:31:11.08:checkk5last 2006.182.08:31:11.08&checkk5last/chk_obsdata=1 2006.182.08:31:11.09&checkk5last/chk_obsdata=2 2006.182.08:31:11.09&checkk5last/chk_obsdata=3 2006.182.08:31:11.09&checkk5last/chk_obsdata=4 2006.182.08:31:11.10&checkk5last/k5log=1 2006.182.08:31:11.10&checkk5last/k5log=2 2006.182.08:31:11.10&checkk5last/k5log=3 2006.182.08:31:11.11&checkk5last/k5log=4 2006.182.08:31:11.11&checkk5last/obsinfo 2006.182.08:31:11.49/chk_obsdata//k5ts1/T1820830??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.182.08:31:11.86/chk_obsdata//k5ts2/T1820830??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.182.08:31:12.23/chk_obsdata//k5ts3/T1820830??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.182.08:31:12.61/chk_obsdata//k5ts4/T1820830??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.182.08:31:13.30/k5log//k5ts1_log_newline 2006.182.08:31:13.99/k5log//k5ts2_log_newline 2006.182.08:31:14.68/k5log//k5ts3_log_newline 2006.182.08:31:15.37/k5log//k5ts4_log_newline 2006.182.08:31:15.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.182.08:31:15.39:"sched_end 2006.182.08:31:15.39:source=idle 2006.182.08:31:16.14#flagr#flagr/antenna,new-source 2006.182.08:31:16.14:stow 2006.182.08:31:16.14&stow/source=idle 2006.182.08:31:16.14&stow/"this is stow command. 2006.182.08:31:16.14&stow/antenna=m3 2006.182.08:31:20.01:!+10m 2006.182.08:41:20.02:standby 2006.182.08:41:20.02&standby/"this is standby command. 2006.182.08:41:20.02&standby/antenna=m0 2006.182.08:41:21.01:sy=cp /usr2/log/k06182ts.log /usr2/log_backup/ 2006.182.08:41:21.10:log=k06183ts