2006.175.08:39:40.10:Log Opened: Mark IV Field System Version 9.7.7 2006.175.08:39:40.11:location,TSUKUB32,-140.09,36.10,61.0 2006.175.08:39:40.11:horizon1,0.,5.,360. 2006.175.08:39:40.11:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.175.08:39:40.12:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.175.08:39:40.12:drivev11,330,270,no 2006.175.08:39:40.12:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.175.08:39:40.13:drivev13,15.000,268,10.000,10.000,10.000 2006.175.08:39:40.13:drivev21,330,270,no 2006.175.08:39:40.13:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.175.08:39:40.14:drivev23,15.000,268,10.000,10.000,10.000 2006.175.08:39:40.14:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.175.08:39:40.19:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.175.08:39:40.19:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.175.08:39:40.19:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.175.08:39:40.20:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.175.08:39:40.20:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.175.08:39:40.20:time,-0.364,101.533,rate 2006.175.08:39:40.21:flagr,200 2006.175.08:39:40.21:proc=k06176ts 2006.175.08:39:40.22:" k06176 2006 tsukub32 t ts 2006.175.08:39:40.22:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.175.08:39:40.22:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.175.08:39:40.27:" 108 tsukub32 14 17400 2006.175.08:39:40.27:" drudg version 050216 compiled under fs 9.7.07 2006.175.08:39:40.28:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.175.08:39:40.28:!2006.176.06:29:50 2006.176.02:10:20.99?ERROR st -97 Trouble decoding pressure data 2006.176.02:10:20.99#wxget#05 2.8 4.8 23.82 871010.2 2006.176.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.176.06:29:50.02:!2006.176.07:19:50 2006.176.07:19:50.00:unstow 2006.176.07:19:50.00&unstow/antenna=e 2006.176.07:19:50.00&unstow/!+10s 2006.176.07:19:50.00&unstow/antenna=m2 2006.176.07:20:02.01:scan_name=176-0730,k06176,60 2006.176.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.176.07:20:03.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.176.07:20:03.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.176.07:20:03.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.176.07:20:03.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.176.07:20:03.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.176.07:20:03.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.176.07:20:04.14:ready_k5 2006.176.07:20:04.14&ready_k5/obsinfo=st 2006.176.07:20:04.14&ready_k5/autoobs=1 2006.176.07:20:04.14&ready_k5/autoobs=2 2006.176.07:20:04.14&ready_k5/autoobs=3 2006.176.07:20:04.14&ready_k5/autoobs=4 2006.176.07:20:04.14&ready_k5/obsinfo 2006.176.07:20:04.14#flagr#flagr/antenna,new-source 2006.176.07:20:04.15/obsinfo=st/error_log.tmp was not found (or not removed). 2006.176.07:20:07.40/autoobs//k5ts1/ autoobs started! 2006.176.07:20:10.58/autoobs//k5ts2/ autoobs started! 2006.176.07:20:13.74/autoobs//k5ts3/ autoobs started! 2006.176.07:20:16.88/autoobs//k5ts4/ autoobs started! 2006.176.07:20:16.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:20:16.90:4f8m12a=1 2006.176.07:20:16.90&4f8m12a/xlog=on 2006.176.07:20:16.90&4f8m12a/echo=on 2006.176.07:20:16.90&4f8m12a/pcalon 2006.176.07:20:16.90&4f8m12a/"tpicd=stop 2006.176.07:20:16.90&4f8m12a/vc4f8 2006.176.07:20:16.90&4f8m12a/ifd4f 2006.176.07:20:16.90&4f8m12a/"form=m,16.000,1:2 2006.176.07:20:16.90&4f8m12a/"tpicd 2006.176.07:20:16.90&4f8m12a/echo=off 2006.176.07:20:16.90&4f8m12a/xlog=off 2006.176.07:20:16.90$4f8m12a/echo=on 2006.176.07:20:16.91$4f8m12a/pcalon 2006.176.07:20:16.91&pcalon/"no phase cal control is implemented here 2006.176.07:20:16.91$pcalon/"no phase cal control is implemented here 2006.176.07:20:16.91$4f8m12a/"tpicd=stop 2006.176.07:20:16.91$4f8m12a/vc4f8 2006.176.07:20:16.91&vc4f8/valo=1,532.99 2006.176.07:20:16.91&vc4f8/va=1,8 2006.176.07:20:16.91&vc4f8/valo=2,572.99 2006.176.07:20:16.91&vc4f8/va=2,7 2006.176.07:20:16.91&vc4f8/valo=3,672.99 2006.176.07:20:16.91&vc4f8/va=3,6 2006.176.07:20:16.91&vc4f8/valo=4,832.99 2006.176.07:20:16.91&vc4f8/va=4,7 2006.176.07:20:16.91&vc4f8/valo=5,652.99 2006.176.07:20:16.91&vc4f8/va=5,7 2006.176.07:20:16.91&vc4f8/valo=6,772.99 2006.176.07:20:16.91&vc4f8/va=6,6 2006.176.07:20:16.91&vc4f8/valo=7,832.99 2006.176.07:20:16.91&vc4f8/va=7,6 2006.176.07:20:16.91&vc4f8/valo=8,852.99 2006.176.07:20:16.91&vc4f8/va=8,6 2006.176.07:20:16.91&vc4f8/vblo=1,632.99 2006.176.07:20:16.91&vc4f8/vb=1,4 2006.176.07:20:16.91&vc4f8/vblo=2,640.99 2006.176.07:20:16.91&vc4f8/vb=2,4 2006.176.07:20:16.91&vc4f8/vblo=3,656.99 2006.176.07:20:16.91&vc4f8/vb=3,4 2006.176.07:20:16.91&vc4f8/vblo=4,712.99 2006.176.07:20:16.91&vc4f8/vb=4,4 2006.176.07:20:16.91&vc4f8/vblo=5,744.99 2006.176.07:20:16.91&vc4f8/vb=5,4 2006.176.07:20:16.91&vc4f8/vblo=6,752.99 2006.176.07:20:16.91&vc4f8/vb=6,4 2006.176.07:20:16.91&vc4f8/vabw=wide 2006.176.07:20:16.91&vc4f8/vbbw=wide 2006.176.07:20:16.91$vc4f8/valo=1,532.99 2006.176.07:20:16.95#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.07:20:16.95#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.07:20:16.95#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:16.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:16.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:16.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:16.95#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:20:16.95#ibcon#first serial, iclass 27, count 0 2006.176.07:20:16.95#ibcon#enter sib2, iclass 27, count 0 2006.176.07:20:16.95#ibcon#flushed, iclass 27, count 0 2006.176.07:20:16.95#ibcon#about to write, iclass 27, count 0 2006.176.07:20:16.95#ibcon#wrote, iclass 27, count 0 2006.176.07:20:16.95#ibcon#about to read 3, iclass 27, count 0 2006.176.07:20:16.96#ibcon#read 3, iclass 27, count 0 2006.176.07:20:16.96#ibcon#about to read 4, iclass 27, count 0 2006.176.07:20:16.96#ibcon#read 4, iclass 27, count 0 2006.176.07:20:16.96#ibcon#about to read 5, iclass 27, count 0 2006.176.07:20:16.96#ibcon#read 5, iclass 27, count 0 2006.176.07:20:16.96#ibcon#about to read 6, iclass 27, count 0 2006.176.07:20:16.96#ibcon#read 6, iclass 27, count 0 2006.176.07:20:16.96#ibcon#end of sib2, iclass 27, count 0 2006.176.07:20:16.96#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:20:16.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:20:16.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:20:16.96#ibcon#*before write, iclass 27, count 0 2006.176.07:20:16.96#ibcon#enter sib2, iclass 27, count 0 2006.176.07:20:16.96#ibcon#flushed, iclass 27, count 0 2006.176.07:20:16.96#ibcon#about to write, iclass 27, count 0 2006.176.07:20:16.96#ibcon#wrote, iclass 27, count 0 2006.176.07:20:16.96#ibcon#about to read 3, iclass 27, count 0 2006.176.07:20:17.02#ibcon#read 3, iclass 27, count 0 2006.176.07:20:17.02#ibcon#about to read 4, iclass 27, count 0 2006.176.07:20:17.02#ibcon#read 4, iclass 27, count 0 2006.176.07:20:17.02#ibcon#about to read 5, iclass 27, count 0 2006.176.07:20:17.02#ibcon#read 5, iclass 27, count 0 2006.176.07:20:17.02#ibcon#about to read 6, iclass 27, count 0 2006.176.07:20:17.02#ibcon#read 6, iclass 27, count 0 2006.176.07:20:17.02#ibcon#end of sib2, iclass 27, count 0 2006.176.07:20:17.02#ibcon#*after write, iclass 27, count 0 2006.176.07:20:17.02#ibcon#*before return 0, iclass 27, count 0 2006.176.07:20:17.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:17.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:17.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:20:17.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:20:17.02$vc4f8/va=1,8 2006.176.07:20:17.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.07:20:17.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.07:20:17.02#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:17.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:17.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:17.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:17.02#ibcon#enter wrdev, iclass 29, count 2 2006.176.07:20:17.02#ibcon#first serial, iclass 29, count 2 2006.176.07:20:17.02#ibcon#enter sib2, iclass 29, count 2 2006.176.07:20:17.02#ibcon#flushed, iclass 29, count 2 2006.176.07:20:17.02#ibcon#about to write, iclass 29, count 2 2006.176.07:20:17.02#ibcon#wrote, iclass 29, count 2 2006.176.07:20:17.02#ibcon#about to read 3, iclass 29, count 2 2006.176.07:20:17.03#ibcon#read 3, iclass 29, count 2 2006.176.07:20:17.04#ibcon#about to read 4, iclass 29, count 2 2006.176.07:20:17.04#ibcon#read 4, iclass 29, count 2 2006.176.07:20:17.04#ibcon#about to read 5, iclass 29, count 2 2006.176.07:20:17.04#ibcon#read 5, iclass 29, count 2 2006.176.07:20:17.04#ibcon#about to read 6, iclass 29, count 2 2006.176.07:20:17.04#ibcon#read 6, iclass 29, count 2 2006.176.07:20:17.04#ibcon#end of sib2, iclass 29, count 2 2006.176.07:20:17.04#ibcon#*mode == 0, iclass 29, count 2 2006.176.07:20:17.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.07:20:17.04#ibcon#[25=AT01-08\r\n] 2006.176.07:20:17.04#ibcon#*before write, iclass 29, count 2 2006.176.07:20:17.04#ibcon#enter sib2, iclass 29, count 2 2006.176.07:20:17.04#ibcon#flushed, iclass 29, count 2 2006.176.07:20:17.04#ibcon#about to write, iclass 29, count 2 2006.176.07:20:17.04#ibcon#wrote, iclass 29, count 2 2006.176.07:20:17.04#ibcon#about to read 3, iclass 29, count 2 2006.176.07:20:17.06#ibcon#read 3, iclass 29, count 2 2006.176.07:20:17.06#ibcon#about to read 4, iclass 29, count 2 2006.176.07:20:17.06#ibcon#read 4, iclass 29, count 2 2006.176.07:20:17.06#ibcon#about to read 5, iclass 29, count 2 2006.176.07:20:17.06#ibcon#read 5, iclass 29, count 2 2006.176.07:20:17.06#ibcon#about to read 6, iclass 29, count 2 2006.176.07:20:17.06#ibcon#read 6, iclass 29, count 2 2006.176.07:20:17.06#ibcon#end of sib2, iclass 29, count 2 2006.176.07:20:17.06#ibcon#*after write, iclass 29, count 2 2006.176.07:20:17.06#ibcon#*before return 0, iclass 29, count 2 2006.176.07:20:17.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:17.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:17.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.07:20:17.06#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:17.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:17.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:17.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:17.18#ibcon#enter wrdev, iclass 29, count 0 2006.176.07:20:17.18#ibcon#first serial, iclass 29, count 0 2006.176.07:20:17.18#ibcon#enter sib2, iclass 29, count 0 2006.176.07:20:17.18#ibcon#flushed, iclass 29, count 0 2006.176.07:20:17.18#ibcon#about to write, iclass 29, count 0 2006.176.07:20:17.18#ibcon#wrote, iclass 29, count 0 2006.176.07:20:17.18#ibcon#about to read 3, iclass 29, count 0 2006.176.07:20:17.20#ibcon#read 3, iclass 29, count 0 2006.176.07:20:17.20#ibcon#about to read 4, iclass 29, count 0 2006.176.07:20:17.20#ibcon#read 4, iclass 29, count 0 2006.176.07:20:17.20#ibcon#about to read 5, iclass 29, count 0 2006.176.07:20:17.20#ibcon#read 5, iclass 29, count 0 2006.176.07:20:17.20#ibcon#about to read 6, iclass 29, count 0 2006.176.07:20:17.20#ibcon#read 6, iclass 29, count 0 2006.176.07:20:17.20#ibcon#end of sib2, iclass 29, count 0 2006.176.07:20:17.20#ibcon#*mode == 0, iclass 29, count 0 2006.176.07:20:17.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.07:20:17.20#ibcon#[25=USB\r\n] 2006.176.07:20:17.20#ibcon#*before write, iclass 29, count 0 2006.176.07:20:17.20#ibcon#enter sib2, iclass 29, count 0 2006.176.07:20:17.20#ibcon#flushed, iclass 29, count 0 2006.176.07:20:17.20#ibcon#about to write, iclass 29, count 0 2006.176.07:20:17.20#ibcon#wrote, iclass 29, count 0 2006.176.07:20:17.20#ibcon#about to read 3, iclass 29, count 0 2006.176.07:20:17.23#ibcon#read 3, iclass 29, count 0 2006.176.07:20:17.23#ibcon#about to read 4, iclass 29, count 0 2006.176.07:20:17.23#ibcon#read 4, iclass 29, count 0 2006.176.07:20:17.23#ibcon#about to read 5, iclass 29, count 0 2006.176.07:20:17.23#ibcon#read 5, iclass 29, count 0 2006.176.07:20:17.23#ibcon#about to read 6, iclass 29, count 0 2006.176.07:20:17.23#ibcon#read 6, iclass 29, count 0 2006.176.07:20:17.23#ibcon#end of sib2, iclass 29, count 0 2006.176.07:20:17.23#ibcon#*after write, iclass 29, count 0 2006.176.07:20:17.23#ibcon#*before return 0, iclass 29, count 0 2006.176.07:20:17.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:17.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:17.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.07:20:17.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.07:20:17.23$vc4f8/valo=2,572.99 2006.176.07:20:17.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.07:20:17.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.07:20:17.23#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:17.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:17.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:17.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:17.23#ibcon#enter wrdev, iclass 31, count 0 2006.176.07:20:17.23#ibcon#first serial, iclass 31, count 0 2006.176.07:20:17.23#ibcon#enter sib2, iclass 31, count 0 2006.176.07:20:17.23#ibcon#flushed, iclass 31, count 0 2006.176.07:20:17.23#ibcon#about to write, iclass 31, count 0 2006.176.07:20:17.23#ibcon#wrote, iclass 31, count 0 2006.176.07:20:17.23#ibcon#about to read 3, iclass 31, count 0 2006.176.07:20:17.25#ibcon#read 3, iclass 31, count 0 2006.176.07:20:17.25#ibcon#about to read 4, iclass 31, count 0 2006.176.07:20:17.25#ibcon#read 4, iclass 31, count 0 2006.176.07:20:17.25#ibcon#about to read 5, iclass 31, count 0 2006.176.07:20:17.25#ibcon#read 5, iclass 31, count 0 2006.176.07:20:17.25#ibcon#about to read 6, iclass 31, count 0 2006.176.07:20:17.25#ibcon#read 6, iclass 31, count 0 2006.176.07:20:17.25#ibcon#end of sib2, iclass 31, count 0 2006.176.07:20:17.25#ibcon#*mode == 0, iclass 31, count 0 2006.176.07:20:17.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.07:20:17.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:20:17.25#ibcon#*before write, iclass 31, count 0 2006.176.07:20:17.25#ibcon#enter sib2, iclass 31, count 0 2006.176.07:20:17.25#ibcon#flushed, iclass 31, count 0 2006.176.07:20:17.25#ibcon#about to write, iclass 31, count 0 2006.176.07:20:17.25#ibcon#wrote, iclass 31, count 0 2006.176.07:20:17.25#ibcon#about to read 3, iclass 31, count 0 2006.176.07:20:17.29#ibcon#read 3, iclass 31, count 0 2006.176.07:20:17.29#ibcon#about to read 4, iclass 31, count 0 2006.176.07:20:17.29#ibcon#read 4, iclass 31, count 0 2006.176.07:20:17.29#ibcon#about to read 5, iclass 31, count 0 2006.176.07:20:17.29#ibcon#read 5, iclass 31, count 0 2006.176.07:20:17.29#ibcon#about to read 6, iclass 31, count 0 2006.176.07:20:17.29#ibcon#read 6, iclass 31, count 0 2006.176.07:20:17.29#ibcon#end of sib2, iclass 31, count 0 2006.176.07:20:17.29#ibcon#*after write, iclass 31, count 0 2006.176.07:20:17.29#ibcon#*before return 0, iclass 31, count 0 2006.176.07:20:17.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:17.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:17.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.07:20:17.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.07:20:17.29$vc4f8/va=2,7 2006.176.07:20:17.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.176.07:20:17.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.176.07:20:17.29#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:17.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:17.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:17.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:17.35#ibcon#enter wrdev, iclass 33, count 2 2006.176.07:20:17.35#ibcon#first serial, iclass 33, count 2 2006.176.07:20:17.35#ibcon#enter sib2, iclass 33, count 2 2006.176.07:20:17.35#ibcon#flushed, iclass 33, count 2 2006.176.07:20:17.35#ibcon#about to write, iclass 33, count 2 2006.176.07:20:17.35#ibcon#wrote, iclass 33, count 2 2006.176.07:20:17.35#ibcon#about to read 3, iclass 33, count 2 2006.176.07:20:17.37#ibcon#read 3, iclass 33, count 2 2006.176.07:20:17.37#ibcon#about to read 4, iclass 33, count 2 2006.176.07:20:17.37#ibcon#read 4, iclass 33, count 2 2006.176.07:20:17.37#ibcon#about to read 5, iclass 33, count 2 2006.176.07:20:17.37#ibcon#read 5, iclass 33, count 2 2006.176.07:20:17.37#ibcon#about to read 6, iclass 33, count 2 2006.176.07:20:17.37#ibcon#read 6, iclass 33, count 2 2006.176.07:20:17.37#ibcon#end of sib2, iclass 33, count 2 2006.176.07:20:17.37#ibcon#*mode == 0, iclass 33, count 2 2006.176.07:20:17.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.176.07:20:17.37#ibcon#[25=AT02-07\r\n] 2006.176.07:20:17.37#ibcon#*before write, iclass 33, count 2 2006.176.07:20:17.37#ibcon#enter sib2, iclass 33, count 2 2006.176.07:20:17.37#ibcon#flushed, iclass 33, count 2 2006.176.07:20:17.37#ibcon#about to write, iclass 33, count 2 2006.176.07:20:17.37#ibcon#wrote, iclass 33, count 2 2006.176.07:20:17.37#ibcon#about to read 3, iclass 33, count 2 2006.176.07:20:17.41#ibcon#read 3, iclass 33, count 2 2006.176.07:20:17.41#ibcon#about to read 4, iclass 33, count 2 2006.176.07:20:17.41#ibcon#read 4, iclass 33, count 2 2006.176.07:20:17.41#ibcon#about to read 5, iclass 33, count 2 2006.176.07:20:17.41#ibcon#read 5, iclass 33, count 2 2006.176.07:20:17.41#ibcon#about to read 6, iclass 33, count 2 2006.176.07:20:17.41#ibcon#read 6, iclass 33, count 2 2006.176.07:20:17.41#ibcon#end of sib2, iclass 33, count 2 2006.176.07:20:17.41#ibcon#*after write, iclass 33, count 2 2006.176.07:20:17.41#ibcon#*before return 0, iclass 33, count 2 2006.176.07:20:17.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:17.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:17.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.176.07:20:17.41#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:17.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:17.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:17.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:17.52#ibcon#enter wrdev, iclass 33, count 0 2006.176.07:20:17.52#ibcon#first serial, iclass 33, count 0 2006.176.07:20:17.52#ibcon#enter sib2, iclass 33, count 0 2006.176.07:20:17.52#ibcon#flushed, iclass 33, count 0 2006.176.07:20:17.52#ibcon#about to write, iclass 33, count 0 2006.176.07:20:17.52#ibcon#wrote, iclass 33, count 0 2006.176.07:20:17.52#ibcon#about to read 3, iclass 33, count 0 2006.176.07:20:17.54#ibcon#read 3, iclass 33, count 0 2006.176.07:20:17.54#ibcon#about to read 4, iclass 33, count 0 2006.176.07:20:17.54#ibcon#read 4, iclass 33, count 0 2006.176.07:20:17.54#ibcon#about to read 5, iclass 33, count 0 2006.176.07:20:17.54#ibcon#read 5, iclass 33, count 0 2006.176.07:20:17.54#ibcon#about to read 6, iclass 33, count 0 2006.176.07:20:17.54#ibcon#read 6, iclass 33, count 0 2006.176.07:20:17.54#ibcon#end of sib2, iclass 33, count 0 2006.176.07:20:17.54#ibcon#*mode == 0, iclass 33, count 0 2006.176.07:20:17.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.07:20:17.54#ibcon#[25=USB\r\n] 2006.176.07:20:17.54#ibcon#*before write, iclass 33, count 0 2006.176.07:20:17.54#ibcon#enter sib2, iclass 33, count 0 2006.176.07:20:17.54#ibcon#flushed, iclass 33, count 0 2006.176.07:20:17.54#ibcon#about to write, iclass 33, count 0 2006.176.07:20:17.54#ibcon#wrote, iclass 33, count 0 2006.176.07:20:17.54#ibcon#about to read 3, iclass 33, count 0 2006.176.07:20:17.57#ibcon#read 3, iclass 33, count 0 2006.176.07:20:17.57#ibcon#about to read 4, iclass 33, count 0 2006.176.07:20:17.57#ibcon#read 4, iclass 33, count 0 2006.176.07:20:17.57#ibcon#about to read 5, iclass 33, count 0 2006.176.07:20:17.57#ibcon#read 5, iclass 33, count 0 2006.176.07:20:17.57#ibcon#about to read 6, iclass 33, count 0 2006.176.07:20:17.57#ibcon#read 6, iclass 33, count 0 2006.176.07:20:17.57#ibcon#end of sib2, iclass 33, count 0 2006.176.07:20:17.57#ibcon#*after write, iclass 33, count 0 2006.176.07:20:17.57#ibcon#*before return 0, iclass 33, count 0 2006.176.07:20:17.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:17.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:17.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.07:20:17.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.07:20:17.57$vc4f8/valo=3,672.99 2006.176.07:20:17.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.07:20:17.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.07:20:17.57#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:17.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:20:17.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:20:17.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:20:17.57#ibcon#enter wrdev, iclass 35, count 0 2006.176.07:20:17.57#ibcon#first serial, iclass 35, count 0 2006.176.07:20:17.57#ibcon#enter sib2, iclass 35, count 0 2006.176.07:20:17.57#ibcon#flushed, iclass 35, count 0 2006.176.07:20:17.57#ibcon#about to write, iclass 35, count 0 2006.176.07:20:17.57#ibcon#wrote, iclass 35, count 0 2006.176.07:20:17.57#ibcon#about to read 3, iclass 35, count 0 2006.176.07:20:17.59#ibcon#read 3, iclass 35, count 0 2006.176.07:20:17.59#ibcon#about to read 4, iclass 35, count 0 2006.176.07:20:17.59#ibcon#read 4, iclass 35, count 0 2006.176.07:20:17.59#ibcon#about to read 5, iclass 35, count 0 2006.176.07:20:17.59#ibcon#read 5, iclass 35, count 0 2006.176.07:20:17.59#ibcon#about to read 6, iclass 35, count 0 2006.176.07:20:17.59#ibcon#read 6, iclass 35, count 0 2006.176.07:20:17.59#ibcon#end of sib2, iclass 35, count 0 2006.176.07:20:17.59#ibcon#*mode == 0, iclass 35, count 0 2006.176.07:20:17.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.07:20:17.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:20:17.59#ibcon#*before write, iclass 35, count 0 2006.176.07:20:17.59#ibcon#enter sib2, iclass 35, count 0 2006.176.07:20:17.59#ibcon#flushed, iclass 35, count 0 2006.176.07:20:17.59#ibcon#about to write, iclass 35, count 0 2006.176.07:20:17.59#ibcon#wrote, iclass 35, count 0 2006.176.07:20:17.59#ibcon#about to read 3, iclass 35, count 0 2006.176.07:20:17.63#ibcon#read 3, iclass 35, count 0 2006.176.07:20:17.63#ibcon#about to read 4, iclass 35, count 0 2006.176.07:20:17.63#ibcon#read 4, iclass 35, count 0 2006.176.07:20:17.63#ibcon#about to read 5, iclass 35, count 0 2006.176.07:20:17.63#ibcon#read 5, iclass 35, count 0 2006.176.07:20:17.63#ibcon#about to read 6, iclass 35, count 0 2006.176.07:20:17.63#ibcon#read 6, iclass 35, count 0 2006.176.07:20:17.63#ibcon#end of sib2, iclass 35, count 0 2006.176.07:20:17.63#ibcon#*after write, iclass 35, count 0 2006.176.07:20:17.63#ibcon#*before return 0, iclass 35, count 0 2006.176.07:20:17.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:20:17.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:20:17.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.07:20:17.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.07:20:17.63$vc4f8/va=3,6 2006.176.07:20:17.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.176.07:20:17.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.176.07:20:17.63#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:17.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:20:17.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:20:17.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:20:17.69#ibcon#enter wrdev, iclass 37, count 2 2006.176.07:20:17.69#ibcon#first serial, iclass 37, count 2 2006.176.07:20:17.69#ibcon#enter sib2, iclass 37, count 2 2006.176.07:20:17.69#ibcon#flushed, iclass 37, count 2 2006.176.07:20:17.69#ibcon#about to write, iclass 37, count 2 2006.176.07:20:17.69#ibcon#wrote, iclass 37, count 2 2006.176.07:20:17.69#ibcon#about to read 3, iclass 37, count 2 2006.176.07:20:17.72#ibcon#read 3, iclass 37, count 2 2006.176.07:20:17.72#ibcon#about to read 4, iclass 37, count 2 2006.176.07:20:17.72#ibcon#read 4, iclass 37, count 2 2006.176.07:20:17.72#ibcon#about to read 5, iclass 37, count 2 2006.176.07:20:17.72#ibcon#read 5, iclass 37, count 2 2006.176.07:20:17.72#ibcon#about to read 6, iclass 37, count 2 2006.176.07:20:17.72#ibcon#read 6, iclass 37, count 2 2006.176.07:20:17.72#ibcon#end of sib2, iclass 37, count 2 2006.176.07:20:17.72#ibcon#*mode == 0, iclass 37, count 2 2006.176.07:20:17.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.176.07:20:17.72#ibcon#[25=AT03-06\r\n] 2006.176.07:20:17.72#ibcon#*before write, iclass 37, count 2 2006.176.07:20:17.72#ibcon#enter sib2, iclass 37, count 2 2006.176.07:20:17.72#ibcon#flushed, iclass 37, count 2 2006.176.07:20:17.72#ibcon#about to write, iclass 37, count 2 2006.176.07:20:17.72#ibcon#wrote, iclass 37, count 2 2006.176.07:20:17.72#ibcon#about to read 3, iclass 37, count 2 2006.176.07:20:17.74#ibcon#read 3, iclass 37, count 2 2006.176.07:20:17.74#ibcon#about to read 4, iclass 37, count 2 2006.176.07:20:17.74#ibcon#read 4, iclass 37, count 2 2006.176.07:20:17.74#ibcon#about to read 5, iclass 37, count 2 2006.176.07:20:17.74#ibcon#read 5, iclass 37, count 2 2006.176.07:20:17.74#ibcon#about to read 6, iclass 37, count 2 2006.176.07:20:17.74#ibcon#read 6, iclass 37, count 2 2006.176.07:20:17.74#ibcon#end of sib2, iclass 37, count 2 2006.176.07:20:17.74#ibcon#*after write, iclass 37, count 2 2006.176.07:20:17.74#ibcon#*before return 0, iclass 37, count 2 2006.176.07:20:17.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:20:17.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:20:17.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.176.07:20:17.74#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:17.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:20:17.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:20:17.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:20:17.86#ibcon#enter wrdev, iclass 37, count 0 2006.176.07:20:17.86#ibcon#first serial, iclass 37, count 0 2006.176.07:20:17.86#ibcon#enter sib2, iclass 37, count 0 2006.176.07:20:17.86#ibcon#flushed, iclass 37, count 0 2006.176.07:20:17.86#ibcon#about to write, iclass 37, count 0 2006.176.07:20:17.86#ibcon#wrote, iclass 37, count 0 2006.176.07:20:17.86#ibcon#about to read 3, iclass 37, count 0 2006.176.07:20:17.88#ibcon#read 3, iclass 37, count 0 2006.176.07:20:17.88#ibcon#about to read 4, iclass 37, count 0 2006.176.07:20:17.88#ibcon#read 4, iclass 37, count 0 2006.176.07:20:17.88#ibcon#about to read 5, iclass 37, count 0 2006.176.07:20:17.88#ibcon#read 5, iclass 37, count 0 2006.176.07:20:17.88#ibcon#about to read 6, iclass 37, count 0 2006.176.07:20:17.88#ibcon#read 6, iclass 37, count 0 2006.176.07:20:17.88#ibcon#end of sib2, iclass 37, count 0 2006.176.07:20:17.88#ibcon#*mode == 0, iclass 37, count 0 2006.176.07:20:17.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.07:20:17.88#ibcon#[25=USB\r\n] 2006.176.07:20:17.88#ibcon#*before write, iclass 37, count 0 2006.176.07:20:17.88#ibcon#enter sib2, iclass 37, count 0 2006.176.07:20:17.88#ibcon#flushed, iclass 37, count 0 2006.176.07:20:17.88#ibcon#about to write, iclass 37, count 0 2006.176.07:20:17.88#ibcon#wrote, iclass 37, count 0 2006.176.07:20:17.88#ibcon#about to read 3, iclass 37, count 0 2006.176.07:20:17.91#ibcon#read 3, iclass 37, count 0 2006.176.07:20:17.91#ibcon#about to read 4, iclass 37, count 0 2006.176.07:20:17.91#ibcon#read 4, iclass 37, count 0 2006.176.07:20:17.91#ibcon#about to read 5, iclass 37, count 0 2006.176.07:20:17.91#ibcon#read 5, iclass 37, count 0 2006.176.07:20:17.91#ibcon#about to read 6, iclass 37, count 0 2006.176.07:20:17.91#ibcon#read 6, iclass 37, count 0 2006.176.07:20:17.91#ibcon#end of sib2, iclass 37, count 0 2006.176.07:20:17.91#ibcon#*after write, iclass 37, count 0 2006.176.07:20:17.91#ibcon#*before return 0, iclass 37, count 0 2006.176.07:20:17.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:20:17.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:20:17.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.07:20:17.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.07:20:17.91$vc4f8/valo=4,832.99 2006.176.07:20:17.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.07:20:17.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.07:20:17.91#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:17.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:20:17.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:20:17.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:20:17.91#ibcon#enter wrdev, iclass 39, count 0 2006.176.07:20:17.91#ibcon#first serial, iclass 39, count 0 2006.176.07:20:17.91#ibcon#enter sib2, iclass 39, count 0 2006.176.07:20:17.91#ibcon#flushed, iclass 39, count 0 2006.176.07:20:17.91#ibcon#about to write, iclass 39, count 0 2006.176.07:20:17.91#ibcon#wrote, iclass 39, count 0 2006.176.07:20:17.91#ibcon#about to read 3, iclass 39, count 0 2006.176.07:20:17.93#ibcon#read 3, iclass 39, count 0 2006.176.07:20:17.93#ibcon#about to read 4, iclass 39, count 0 2006.176.07:20:17.93#ibcon#read 4, iclass 39, count 0 2006.176.07:20:17.93#ibcon#about to read 5, iclass 39, count 0 2006.176.07:20:17.93#ibcon#read 5, iclass 39, count 0 2006.176.07:20:17.93#ibcon#about to read 6, iclass 39, count 0 2006.176.07:20:17.93#ibcon#read 6, iclass 39, count 0 2006.176.07:20:17.93#ibcon#end of sib2, iclass 39, count 0 2006.176.07:20:17.93#ibcon#*mode == 0, iclass 39, count 0 2006.176.07:20:17.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.07:20:17.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:20:17.93#ibcon#*before write, iclass 39, count 0 2006.176.07:20:17.93#ibcon#enter sib2, iclass 39, count 0 2006.176.07:20:17.93#ibcon#flushed, iclass 39, count 0 2006.176.07:20:17.93#ibcon#about to write, iclass 39, count 0 2006.176.07:20:17.93#ibcon#wrote, iclass 39, count 0 2006.176.07:20:17.93#ibcon#about to read 3, iclass 39, count 0 2006.176.07:20:17.97#ibcon#read 3, iclass 39, count 0 2006.176.07:20:17.97#ibcon#about to read 4, iclass 39, count 0 2006.176.07:20:17.97#ibcon#read 4, iclass 39, count 0 2006.176.07:20:17.97#ibcon#about to read 5, iclass 39, count 0 2006.176.07:20:17.97#ibcon#read 5, iclass 39, count 0 2006.176.07:20:17.97#ibcon#about to read 6, iclass 39, count 0 2006.176.07:20:17.97#ibcon#read 6, iclass 39, count 0 2006.176.07:20:17.97#ibcon#end of sib2, iclass 39, count 0 2006.176.07:20:17.97#ibcon#*after write, iclass 39, count 0 2006.176.07:20:17.97#ibcon#*before return 0, iclass 39, count 0 2006.176.07:20:17.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:20:17.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:20:17.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.07:20:17.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.07:20:17.97$vc4f8/va=4,7 2006.176.07:20:17.97#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.07:20:17.97#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.07:20:17.97#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:17.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:18.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:18.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:18.03#ibcon#enter wrdev, iclass 3, count 2 2006.176.07:20:18.03#ibcon#first serial, iclass 3, count 2 2006.176.07:20:18.03#ibcon#enter sib2, iclass 3, count 2 2006.176.07:20:18.03#ibcon#flushed, iclass 3, count 2 2006.176.07:20:18.03#ibcon#about to write, iclass 3, count 2 2006.176.07:20:18.03#ibcon#wrote, iclass 3, count 2 2006.176.07:20:18.03#ibcon#about to read 3, iclass 3, count 2 2006.176.07:20:18.05#ibcon#read 3, iclass 3, count 2 2006.176.07:20:18.05#ibcon#about to read 4, iclass 3, count 2 2006.176.07:20:18.05#ibcon#read 4, iclass 3, count 2 2006.176.07:20:18.05#ibcon#about to read 5, iclass 3, count 2 2006.176.07:20:18.05#ibcon#read 5, iclass 3, count 2 2006.176.07:20:18.05#ibcon#about to read 6, iclass 3, count 2 2006.176.07:20:18.05#ibcon#read 6, iclass 3, count 2 2006.176.07:20:18.05#ibcon#end of sib2, iclass 3, count 2 2006.176.07:20:18.05#ibcon#*mode == 0, iclass 3, count 2 2006.176.07:20:18.05#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.07:20:18.05#ibcon#[25=AT04-07\r\n] 2006.176.07:20:18.05#ibcon#*before write, iclass 3, count 2 2006.176.07:20:18.05#ibcon#enter sib2, iclass 3, count 2 2006.176.07:20:18.05#ibcon#flushed, iclass 3, count 2 2006.176.07:20:18.05#ibcon#about to write, iclass 3, count 2 2006.176.07:20:18.05#ibcon#wrote, iclass 3, count 2 2006.176.07:20:18.05#ibcon#about to read 3, iclass 3, count 2 2006.176.07:20:18.08#ibcon#read 3, iclass 3, count 2 2006.176.07:20:18.08#ibcon#about to read 4, iclass 3, count 2 2006.176.07:20:18.08#ibcon#read 4, iclass 3, count 2 2006.176.07:20:18.08#ibcon#about to read 5, iclass 3, count 2 2006.176.07:20:18.08#ibcon#read 5, iclass 3, count 2 2006.176.07:20:18.08#ibcon#about to read 6, iclass 3, count 2 2006.176.07:20:18.08#ibcon#read 6, iclass 3, count 2 2006.176.07:20:18.08#ibcon#end of sib2, iclass 3, count 2 2006.176.07:20:18.08#ibcon#*after write, iclass 3, count 2 2006.176.07:20:18.08#ibcon#*before return 0, iclass 3, count 2 2006.176.07:20:18.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:18.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:18.08#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.07:20:18.08#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:18.08#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:18.20#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:18.20#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:18.20#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:20:18.20#ibcon#first serial, iclass 3, count 0 2006.176.07:20:18.20#ibcon#enter sib2, iclass 3, count 0 2006.176.07:20:18.20#ibcon#flushed, iclass 3, count 0 2006.176.07:20:18.20#ibcon#about to write, iclass 3, count 0 2006.176.07:20:18.20#ibcon#wrote, iclass 3, count 0 2006.176.07:20:18.20#ibcon#about to read 3, iclass 3, count 0 2006.176.07:20:18.22#ibcon#read 3, iclass 3, count 0 2006.176.07:20:18.22#ibcon#about to read 4, iclass 3, count 0 2006.176.07:20:18.22#ibcon#read 4, iclass 3, count 0 2006.176.07:20:18.22#ibcon#about to read 5, iclass 3, count 0 2006.176.07:20:18.22#ibcon#read 5, iclass 3, count 0 2006.176.07:20:18.22#ibcon#about to read 6, iclass 3, count 0 2006.176.07:20:18.22#ibcon#read 6, iclass 3, count 0 2006.176.07:20:18.22#ibcon#end of sib2, iclass 3, count 0 2006.176.07:20:18.22#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:20:18.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:20:18.22#ibcon#[25=USB\r\n] 2006.176.07:20:18.22#ibcon#*before write, iclass 3, count 0 2006.176.07:20:18.22#ibcon#enter sib2, iclass 3, count 0 2006.176.07:20:18.22#ibcon#flushed, iclass 3, count 0 2006.176.07:20:18.22#ibcon#about to write, iclass 3, count 0 2006.176.07:20:18.22#ibcon#wrote, iclass 3, count 0 2006.176.07:20:18.22#ibcon#about to read 3, iclass 3, count 0 2006.176.07:20:18.25#ibcon#read 3, iclass 3, count 0 2006.176.07:20:18.25#ibcon#about to read 4, iclass 3, count 0 2006.176.07:20:18.25#ibcon#read 4, iclass 3, count 0 2006.176.07:20:18.25#ibcon#about to read 5, iclass 3, count 0 2006.176.07:20:18.25#ibcon#read 5, iclass 3, count 0 2006.176.07:20:18.25#ibcon#about to read 6, iclass 3, count 0 2006.176.07:20:18.25#ibcon#read 6, iclass 3, count 0 2006.176.07:20:18.25#ibcon#end of sib2, iclass 3, count 0 2006.176.07:20:18.25#ibcon#*after write, iclass 3, count 0 2006.176.07:20:18.25#ibcon#*before return 0, iclass 3, count 0 2006.176.07:20:18.25#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:18.25#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:18.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:20:18.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:20:18.25$vc4f8/valo=5,652.99 2006.176.07:20:18.25#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.07:20:18.25#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.07:20:18.25#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:18.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:18.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:18.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:18.25#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:20:18.25#ibcon#first serial, iclass 5, count 0 2006.176.07:20:18.25#ibcon#enter sib2, iclass 5, count 0 2006.176.07:20:18.25#ibcon#flushed, iclass 5, count 0 2006.176.07:20:18.25#ibcon#about to write, iclass 5, count 0 2006.176.07:20:18.25#ibcon#wrote, iclass 5, count 0 2006.176.07:20:18.25#ibcon#about to read 3, iclass 5, count 0 2006.176.07:20:18.27#ibcon#read 3, iclass 5, count 0 2006.176.07:20:18.27#ibcon#about to read 4, iclass 5, count 0 2006.176.07:20:18.27#ibcon#read 4, iclass 5, count 0 2006.176.07:20:18.27#ibcon#about to read 5, iclass 5, count 0 2006.176.07:20:18.27#ibcon#read 5, iclass 5, count 0 2006.176.07:20:18.27#ibcon#about to read 6, iclass 5, count 0 2006.176.07:20:18.27#ibcon#read 6, iclass 5, count 0 2006.176.07:20:18.27#ibcon#end of sib2, iclass 5, count 0 2006.176.07:20:18.27#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:20:18.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:20:18.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:20:18.27#ibcon#*before write, iclass 5, count 0 2006.176.07:20:18.27#ibcon#enter sib2, iclass 5, count 0 2006.176.07:20:18.27#ibcon#flushed, iclass 5, count 0 2006.176.07:20:18.27#ibcon#about to write, iclass 5, count 0 2006.176.07:20:18.27#ibcon#wrote, iclass 5, count 0 2006.176.07:20:18.27#ibcon#about to read 3, iclass 5, count 0 2006.176.07:20:18.31#ibcon#read 3, iclass 5, count 0 2006.176.07:20:18.31#ibcon#about to read 4, iclass 5, count 0 2006.176.07:20:18.31#ibcon#read 4, iclass 5, count 0 2006.176.07:20:18.31#ibcon#about to read 5, iclass 5, count 0 2006.176.07:20:18.31#ibcon#read 5, iclass 5, count 0 2006.176.07:20:18.31#ibcon#about to read 6, iclass 5, count 0 2006.176.07:20:18.31#ibcon#read 6, iclass 5, count 0 2006.176.07:20:18.31#ibcon#end of sib2, iclass 5, count 0 2006.176.07:20:18.31#ibcon#*after write, iclass 5, count 0 2006.176.07:20:18.31#ibcon#*before return 0, iclass 5, count 0 2006.176.07:20:18.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:18.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:18.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:20:18.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:20:18.31$vc4f8/va=5,7 2006.176.07:20:18.31#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.07:20:18.31#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.07:20:18.31#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:18.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:18.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:18.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:18.37#ibcon#enter wrdev, iclass 7, count 2 2006.176.07:20:18.37#ibcon#first serial, iclass 7, count 2 2006.176.07:20:18.37#ibcon#enter sib2, iclass 7, count 2 2006.176.07:20:18.37#ibcon#flushed, iclass 7, count 2 2006.176.07:20:18.37#ibcon#about to write, iclass 7, count 2 2006.176.07:20:18.37#ibcon#wrote, iclass 7, count 2 2006.176.07:20:18.37#ibcon#about to read 3, iclass 7, count 2 2006.176.07:20:18.39#ibcon#read 3, iclass 7, count 2 2006.176.07:20:18.39#ibcon#about to read 4, iclass 7, count 2 2006.176.07:20:18.39#ibcon#read 4, iclass 7, count 2 2006.176.07:20:18.39#ibcon#about to read 5, iclass 7, count 2 2006.176.07:20:18.39#ibcon#read 5, iclass 7, count 2 2006.176.07:20:18.39#ibcon#about to read 6, iclass 7, count 2 2006.176.07:20:18.39#ibcon#read 6, iclass 7, count 2 2006.176.07:20:18.39#ibcon#end of sib2, iclass 7, count 2 2006.176.07:20:18.39#ibcon#*mode == 0, iclass 7, count 2 2006.176.07:20:18.39#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.07:20:18.39#ibcon#[25=AT05-07\r\n] 2006.176.07:20:18.39#ibcon#*before write, iclass 7, count 2 2006.176.07:20:18.39#ibcon#enter sib2, iclass 7, count 2 2006.176.07:20:18.39#ibcon#flushed, iclass 7, count 2 2006.176.07:20:18.39#ibcon#about to write, iclass 7, count 2 2006.176.07:20:18.39#ibcon#wrote, iclass 7, count 2 2006.176.07:20:18.39#ibcon#about to read 3, iclass 7, count 2 2006.176.07:20:18.43#ibcon#read 3, iclass 7, count 2 2006.176.07:20:18.43#ibcon#about to read 4, iclass 7, count 2 2006.176.07:20:18.43#ibcon#read 4, iclass 7, count 2 2006.176.07:20:18.43#ibcon#about to read 5, iclass 7, count 2 2006.176.07:20:18.43#ibcon#read 5, iclass 7, count 2 2006.176.07:20:18.43#ibcon#about to read 6, iclass 7, count 2 2006.176.07:20:18.43#ibcon#read 6, iclass 7, count 2 2006.176.07:20:18.43#ibcon#end of sib2, iclass 7, count 2 2006.176.07:20:18.43#ibcon#*after write, iclass 7, count 2 2006.176.07:20:18.43#ibcon#*before return 0, iclass 7, count 2 2006.176.07:20:18.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:18.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:18.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.07:20:18.43#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:18.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:18.54#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:18.54#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:18.54#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:20:18.54#ibcon#first serial, iclass 7, count 0 2006.176.07:20:18.54#ibcon#enter sib2, iclass 7, count 0 2006.176.07:20:18.54#ibcon#flushed, iclass 7, count 0 2006.176.07:20:18.54#ibcon#about to write, iclass 7, count 0 2006.176.07:20:18.54#ibcon#wrote, iclass 7, count 0 2006.176.07:20:18.54#ibcon#about to read 3, iclass 7, count 0 2006.176.07:20:18.56#ibcon#read 3, iclass 7, count 0 2006.176.07:20:18.56#ibcon#about to read 4, iclass 7, count 0 2006.176.07:20:18.56#ibcon#read 4, iclass 7, count 0 2006.176.07:20:18.56#ibcon#about to read 5, iclass 7, count 0 2006.176.07:20:18.56#ibcon#read 5, iclass 7, count 0 2006.176.07:20:18.56#ibcon#about to read 6, iclass 7, count 0 2006.176.07:20:18.56#ibcon#read 6, iclass 7, count 0 2006.176.07:20:18.56#ibcon#end of sib2, iclass 7, count 0 2006.176.07:20:18.56#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:20:18.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:20:18.56#ibcon#[25=USB\r\n] 2006.176.07:20:18.56#ibcon#*before write, iclass 7, count 0 2006.176.07:20:18.56#ibcon#enter sib2, iclass 7, count 0 2006.176.07:20:18.56#ibcon#flushed, iclass 7, count 0 2006.176.07:20:18.56#ibcon#about to write, iclass 7, count 0 2006.176.07:20:18.56#ibcon#wrote, iclass 7, count 0 2006.176.07:20:18.56#ibcon#about to read 3, iclass 7, count 0 2006.176.07:20:18.59#ibcon#read 3, iclass 7, count 0 2006.176.07:20:18.59#ibcon#about to read 4, iclass 7, count 0 2006.176.07:20:18.59#ibcon#read 4, iclass 7, count 0 2006.176.07:20:18.59#ibcon#about to read 5, iclass 7, count 0 2006.176.07:20:18.59#ibcon#read 5, iclass 7, count 0 2006.176.07:20:18.59#ibcon#about to read 6, iclass 7, count 0 2006.176.07:20:18.59#ibcon#read 6, iclass 7, count 0 2006.176.07:20:18.59#ibcon#end of sib2, iclass 7, count 0 2006.176.07:20:18.59#ibcon#*after write, iclass 7, count 0 2006.176.07:20:18.59#ibcon#*before return 0, iclass 7, count 0 2006.176.07:20:18.59#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:18.59#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:18.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:20:18.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:20:18.59$vc4f8/valo=6,772.99 2006.176.07:20:18.59#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.07:20:18.59#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.07:20:18.59#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:18.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:18.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:18.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:18.59#ibcon#enter wrdev, iclass 11, count 0 2006.176.07:20:18.59#ibcon#first serial, iclass 11, count 0 2006.176.07:20:18.59#ibcon#enter sib2, iclass 11, count 0 2006.176.07:20:18.59#ibcon#flushed, iclass 11, count 0 2006.176.07:20:18.59#ibcon#about to write, iclass 11, count 0 2006.176.07:20:18.59#ibcon#wrote, iclass 11, count 0 2006.176.07:20:18.59#ibcon#about to read 3, iclass 11, count 0 2006.176.07:20:18.61#ibcon#read 3, iclass 11, count 0 2006.176.07:20:18.61#ibcon#about to read 4, iclass 11, count 0 2006.176.07:20:18.61#ibcon#read 4, iclass 11, count 0 2006.176.07:20:18.61#ibcon#about to read 5, iclass 11, count 0 2006.176.07:20:18.61#ibcon#read 5, iclass 11, count 0 2006.176.07:20:18.61#ibcon#about to read 6, iclass 11, count 0 2006.176.07:20:18.61#ibcon#read 6, iclass 11, count 0 2006.176.07:20:18.61#ibcon#end of sib2, iclass 11, count 0 2006.176.07:20:18.61#ibcon#*mode == 0, iclass 11, count 0 2006.176.07:20:18.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.07:20:18.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:20:18.61#ibcon#*before write, iclass 11, count 0 2006.176.07:20:18.61#ibcon#enter sib2, iclass 11, count 0 2006.176.07:20:18.61#ibcon#flushed, iclass 11, count 0 2006.176.07:20:18.61#ibcon#about to write, iclass 11, count 0 2006.176.07:20:18.61#ibcon#wrote, iclass 11, count 0 2006.176.07:20:18.61#ibcon#about to read 3, iclass 11, count 0 2006.176.07:20:18.65#ibcon#read 3, iclass 11, count 0 2006.176.07:20:18.65#ibcon#about to read 4, iclass 11, count 0 2006.176.07:20:18.65#ibcon#read 4, iclass 11, count 0 2006.176.07:20:18.65#ibcon#about to read 5, iclass 11, count 0 2006.176.07:20:18.65#ibcon#read 5, iclass 11, count 0 2006.176.07:20:18.65#ibcon#about to read 6, iclass 11, count 0 2006.176.07:20:18.65#ibcon#read 6, iclass 11, count 0 2006.176.07:20:18.65#ibcon#end of sib2, iclass 11, count 0 2006.176.07:20:18.65#ibcon#*after write, iclass 11, count 0 2006.176.07:20:18.65#ibcon#*before return 0, iclass 11, count 0 2006.176.07:20:18.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:18.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:18.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.07:20:18.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.07:20:18.65$vc4f8/va=6,6 2006.176.07:20:18.65#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.07:20:18.65#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.07:20:18.65#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:18.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:18.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:18.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:18.71#ibcon#enter wrdev, iclass 13, count 2 2006.176.07:20:18.71#ibcon#first serial, iclass 13, count 2 2006.176.07:20:18.71#ibcon#enter sib2, iclass 13, count 2 2006.176.07:20:18.71#ibcon#flushed, iclass 13, count 2 2006.176.07:20:18.71#ibcon#about to write, iclass 13, count 2 2006.176.07:20:18.71#ibcon#wrote, iclass 13, count 2 2006.176.07:20:18.71#ibcon#about to read 3, iclass 13, count 2 2006.176.07:20:18.73#ibcon#read 3, iclass 13, count 2 2006.176.07:20:18.73#ibcon#about to read 4, iclass 13, count 2 2006.176.07:20:18.73#ibcon#read 4, iclass 13, count 2 2006.176.07:20:18.73#ibcon#about to read 5, iclass 13, count 2 2006.176.07:20:18.73#ibcon#read 5, iclass 13, count 2 2006.176.07:20:18.73#ibcon#about to read 6, iclass 13, count 2 2006.176.07:20:18.73#ibcon#read 6, iclass 13, count 2 2006.176.07:20:18.73#ibcon#end of sib2, iclass 13, count 2 2006.176.07:20:18.73#ibcon#*mode == 0, iclass 13, count 2 2006.176.07:20:18.73#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.07:20:18.73#ibcon#[25=AT06-06\r\n] 2006.176.07:20:18.73#ibcon#*before write, iclass 13, count 2 2006.176.07:20:18.73#ibcon#enter sib2, iclass 13, count 2 2006.176.07:20:18.73#ibcon#flushed, iclass 13, count 2 2006.176.07:20:18.73#ibcon#about to write, iclass 13, count 2 2006.176.07:20:18.73#ibcon#wrote, iclass 13, count 2 2006.176.07:20:18.73#ibcon#about to read 3, iclass 13, count 2 2006.176.07:20:18.76#ibcon#read 3, iclass 13, count 2 2006.176.07:20:18.76#ibcon#about to read 4, iclass 13, count 2 2006.176.07:20:18.76#ibcon#read 4, iclass 13, count 2 2006.176.07:20:18.76#ibcon#about to read 5, iclass 13, count 2 2006.176.07:20:18.76#ibcon#read 5, iclass 13, count 2 2006.176.07:20:18.76#ibcon#about to read 6, iclass 13, count 2 2006.176.07:20:18.76#ibcon#read 6, iclass 13, count 2 2006.176.07:20:18.76#ibcon#end of sib2, iclass 13, count 2 2006.176.07:20:18.76#ibcon#*after write, iclass 13, count 2 2006.176.07:20:18.76#ibcon#*before return 0, iclass 13, count 2 2006.176.07:20:18.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:18.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:18.76#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.07:20:18.76#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:18.76#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:18.88#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:18.88#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:18.88#ibcon#enter wrdev, iclass 13, count 0 2006.176.07:20:18.88#ibcon#first serial, iclass 13, count 0 2006.176.07:20:18.88#ibcon#enter sib2, iclass 13, count 0 2006.176.07:20:18.88#ibcon#flushed, iclass 13, count 0 2006.176.07:20:18.88#ibcon#about to write, iclass 13, count 0 2006.176.07:20:18.88#ibcon#wrote, iclass 13, count 0 2006.176.07:20:18.88#ibcon#about to read 3, iclass 13, count 0 2006.176.07:20:18.90#ibcon#read 3, iclass 13, count 0 2006.176.07:20:18.90#ibcon#about to read 4, iclass 13, count 0 2006.176.07:20:18.90#ibcon#read 4, iclass 13, count 0 2006.176.07:20:18.90#ibcon#about to read 5, iclass 13, count 0 2006.176.07:20:18.90#ibcon#read 5, iclass 13, count 0 2006.176.07:20:18.90#ibcon#about to read 6, iclass 13, count 0 2006.176.07:20:18.90#ibcon#read 6, iclass 13, count 0 2006.176.07:20:18.90#ibcon#end of sib2, iclass 13, count 0 2006.176.07:20:18.90#ibcon#*mode == 0, iclass 13, count 0 2006.176.07:20:18.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.07:20:18.90#ibcon#[25=USB\r\n] 2006.176.07:20:18.90#ibcon#*before write, iclass 13, count 0 2006.176.07:20:18.90#ibcon#enter sib2, iclass 13, count 0 2006.176.07:20:18.90#ibcon#flushed, iclass 13, count 0 2006.176.07:20:18.90#ibcon#about to write, iclass 13, count 0 2006.176.07:20:18.90#ibcon#wrote, iclass 13, count 0 2006.176.07:20:18.90#ibcon#about to read 3, iclass 13, count 0 2006.176.07:20:18.93#ibcon#read 3, iclass 13, count 0 2006.176.07:20:18.93#ibcon#about to read 4, iclass 13, count 0 2006.176.07:20:18.93#ibcon#read 4, iclass 13, count 0 2006.176.07:20:18.93#ibcon#about to read 5, iclass 13, count 0 2006.176.07:20:18.93#ibcon#read 5, iclass 13, count 0 2006.176.07:20:18.93#ibcon#about to read 6, iclass 13, count 0 2006.176.07:20:18.93#ibcon#read 6, iclass 13, count 0 2006.176.07:20:18.93#ibcon#end of sib2, iclass 13, count 0 2006.176.07:20:18.93#ibcon#*after write, iclass 13, count 0 2006.176.07:20:18.93#ibcon#*before return 0, iclass 13, count 0 2006.176.07:20:18.93#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:18.93#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:18.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.07:20:18.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.07:20:18.93$vc4f8/valo=7,832.99 2006.176.07:20:18.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.07:20:18.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.07:20:18.93#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:18.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:18.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:18.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:18.93#ibcon#enter wrdev, iclass 15, count 0 2006.176.07:20:18.93#ibcon#first serial, iclass 15, count 0 2006.176.07:20:18.93#ibcon#enter sib2, iclass 15, count 0 2006.176.07:20:18.93#ibcon#flushed, iclass 15, count 0 2006.176.07:20:18.93#ibcon#about to write, iclass 15, count 0 2006.176.07:20:18.93#ibcon#wrote, iclass 15, count 0 2006.176.07:20:18.93#ibcon#about to read 3, iclass 15, count 0 2006.176.07:20:18.95#ibcon#read 3, iclass 15, count 0 2006.176.07:20:18.95#ibcon#about to read 4, iclass 15, count 0 2006.176.07:20:18.95#ibcon#read 4, iclass 15, count 0 2006.176.07:20:18.95#ibcon#about to read 5, iclass 15, count 0 2006.176.07:20:18.95#ibcon#read 5, iclass 15, count 0 2006.176.07:20:18.95#ibcon#about to read 6, iclass 15, count 0 2006.176.07:20:18.95#ibcon#read 6, iclass 15, count 0 2006.176.07:20:18.95#ibcon#end of sib2, iclass 15, count 0 2006.176.07:20:18.95#ibcon#*mode == 0, iclass 15, count 0 2006.176.07:20:18.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.07:20:18.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:20:18.95#ibcon#*before write, iclass 15, count 0 2006.176.07:20:18.95#ibcon#enter sib2, iclass 15, count 0 2006.176.07:20:18.95#ibcon#flushed, iclass 15, count 0 2006.176.07:20:18.95#ibcon#about to write, iclass 15, count 0 2006.176.07:20:18.95#ibcon#wrote, iclass 15, count 0 2006.176.07:20:18.95#ibcon#about to read 3, iclass 15, count 0 2006.176.07:20:18.99#ibcon#read 3, iclass 15, count 0 2006.176.07:20:18.99#ibcon#about to read 4, iclass 15, count 0 2006.176.07:20:18.99#ibcon#read 4, iclass 15, count 0 2006.176.07:20:18.99#ibcon#about to read 5, iclass 15, count 0 2006.176.07:20:18.99#ibcon#read 5, iclass 15, count 0 2006.176.07:20:18.99#ibcon#about to read 6, iclass 15, count 0 2006.176.07:20:18.99#ibcon#read 6, iclass 15, count 0 2006.176.07:20:18.99#ibcon#end of sib2, iclass 15, count 0 2006.176.07:20:18.99#ibcon#*after write, iclass 15, count 0 2006.176.07:20:18.99#ibcon#*before return 0, iclass 15, count 0 2006.176.07:20:18.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:18.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:18.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.07:20:18.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.07:20:18.99$vc4f8/va=7,6 2006.176.07:20:18.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.176.07:20:18.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.176.07:20:18.99#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:18.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:20:19.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:20:19.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:20:19.05#ibcon#enter wrdev, iclass 17, count 2 2006.176.07:20:19.05#ibcon#first serial, iclass 17, count 2 2006.176.07:20:19.05#ibcon#enter sib2, iclass 17, count 2 2006.176.07:20:19.05#ibcon#flushed, iclass 17, count 2 2006.176.07:20:19.05#ibcon#about to write, iclass 17, count 2 2006.176.07:20:19.05#ibcon#wrote, iclass 17, count 2 2006.176.07:20:19.05#ibcon#about to read 3, iclass 17, count 2 2006.176.07:20:19.07#ibcon#read 3, iclass 17, count 2 2006.176.07:20:19.07#ibcon#about to read 4, iclass 17, count 2 2006.176.07:20:19.07#ibcon#read 4, iclass 17, count 2 2006.176.07:20:19.07#ibcon#about to read 5, iclass 17, count 2 2006.176.07:20:19.07#ibcon#read 5, iclass 17, count 2 2006.176.07:20:19.07#ibcon#about to read 6, iclass 17, count 2 2006.176.07:20:19.07#ibcon#read 6, iclass 17, count 2 2006.176.07:20:19.07#ibcon#end of sib2, iclass 17, count 2 2006.176.07:20:19.07#ibcon#*mode == 0, iclass 17, count 2 2006.176.07:20:19.07#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.176.07:20:19.07#ibcon#[25=AT07-06\r\n] 2006.176.07:20:19.07#ibcon#*before write, iclass 17, count 2 2006.176.07:20:19.07#ibcon#enter sib2, iclass 17, count 2 2006.176.07:20:19.07#ibcon#flushed, iclass 17, count 2 2006.176.07:20:19.07#ibcon#about to write, iclass 17, count 2 2006.176.07:20:19.07#ibcon#wrote, iclass 17, count 2 2006.176.07:20:19.07#ibcon#about to read 3, iclass 17, count 2 2006.176.07:20:19.10#ibcon#read 3, iclass 17, count 2 2006.176.07:20:19.10#ibcon#about to read 4, iclass 17, count 2 2006.176.07:20:19.10#ibcon#read 4, iclass 17, count 2 2006.176.07:20:19.10#ibcon#about to read 5, iclass 17, count 2 2006.176.07:20:19.10#ibcon#read 5, iclass 17, count 2 2006.176.07:20:19.10#ibcon#about to read 6, iclass 17, count 2 2006.176.07:20:19.10#ibcon#read 6, iclass 17, count 2 2006.176.07:20:19.10#ibcon#end of sib2, iclass 17, count 2 2006.176.07:20:19.10#ibcon#*after write, iclass 17, count 2 2006.176.07:20:19.10#ibcon#*before return 0, iclass 17, count 2 2006.176.07:20:19.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:20:19.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:20:19.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.176.07:20:19.10#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:19.10#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:20:19.22#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:20:19.22#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:20:19.22#ibcon#enter wrdev, iclass 17, count 0 2006.176.07:20:19.22#ibcon#first serial, iclass 17, count 0 2006.176.07:20:19.22#ibcon#enter sib2, iclass 17, count 0 2006.176.07:20:19.22#ibcon#flushed, iclass 17, count 0 2006.176.07:20:19.22#ibcon#about to write, iclass 17, count 0 2006.176.07:20:19.22#ibcon#wrote, iclass 17, count 0 2006.176.07:20:19.22#ibcon#about to read 3, iclass 17, count 0 2006.176.07:20:19.24#ibcon#read 3, iclass 17, count 0 2006.176.07:20:19.24#ibcon#about to read 4, iclass 17, count 0 2006.176.07:20:19.24#ibcon#read 4, iclass 17, count 0 2006.176.07:20:19.24#ibcon#about to read 5, iclass 17, count 0 2006.176.07:20:19.24#ibcon#read 5, iclass 17, count 0 2006.176.07:20:19.24#ibcon#about to read 6, iclass 17, count 0 2006.176.07:20:19.24#ibcon#read 6, iclass 17, count 0 2006.176.07:20:19.24#ibcon#end of sib2, iclass 17, count 0 2006.176.07:20:19.24#ibcon#*mode == 0, iclass 17, count 0 2006.176.07:20:19.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.07:20:19.24#ibcon#[25=USB\r\n] 2006.176.07:20:19.24#ibcon#*before write, iclass 17, count 0 2006.176.07:20:19.24#ibcon#enter sib2, iclass 17, count 0 2006.176.07:20:19.24#ibcon#flushed, iclass 17, count 0 2006.176.07:20:19.24#ibcon#about to write, iclass 17, count 0 2006.176.07:20:19.24#ibcon#wrote, iclass 17, count 0 2006.176.07:20:19.24#ibcon#about to read 3, iclass 17, count 0 2006.176.07:20:19.27#ibcon#read 3, iclass 17, count 0 2006.176.07:20:19.27#ibcon#about to read 4, iclass 17, count 0 2006.176.07:20:19.27#ibcon#read 4, iclass 17, count 0 2006.176.07:20:19.27#ibcon#about to read 5, iclass 17, count 0 2006.176.07:20:19.27#ibcon#read 5, iclass 17, count 0 2006.176.07:20:19.27#ibcon#about to read 6, iclass 17, count 0 2006.176.07:20:19.27#ibcon#read 6, iclass 17, count 0 2006.176.07:20:19.27#ibcon#end of sib2, iclass 17, count 0 2006.176.07:20:19.27#ibcon#*after write, iclass 17, count 0 2006.176.07:20:19.27#ibcon#*before return 0, iclass 17, count 0 2006.176.07:20:19.27#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:20:19.27#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:20:19.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.07:20:19.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.07:20:19.27$vc4f8/valo=8,852.99 2006.176.07:20:19.27#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.176.07:20:19.27#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.176.07:20:19.27#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:19.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:20:19.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:20:19.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:20:19.27#ibcon#enter wrdev, iclass 19, count 0 2006.176.07:20:19.27#ibcon#first serial, iclass 19, count 0 2006.176.07:20:19.27#ibcon#enter sib2, iclass 19, count 0 2006.176.07:20:19.27#ibcon#flushed, iclass 19, count 0 2006.176.07:20:19.27#ibcon#about to write, iclass 19, count 0 2006.176.07:20:19.27#ibcon#wrote, iclass 19, count 0 2006.176.07:20:19.27#ibcon#about to read 3, iclass 19, count 0 2006.176.07:20:19.29#ibcon#read 3, iclass 19, count 0 2006.176.07:20:19.29#ibcon#about to read 4, iclass 19, count 0 2006.176.07:20:19.29#ibcon#read 4, iclass 19, count 0 2006.176.07:20:19.29#ibcon#about to read 5, iclass 19, count 0 2006.176.07:20:19.29#ibcon#read 5, iclass 19, count 0 2006.176.07:20:19.29#ibcon#about to read 6, iclass 19, count 0 2006.176.07:20:19.29#ibcon#read 6, iclass 19, count 0 2006.176.07:20:19.29#ibcon#end of sib2, iclass 19, count 0 2006.176.07:20:19.29#ibcon#*mode == 0, iclass 19, count 0 2006.176.07:20:19.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.07:20:19.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:20:19.29#ibcon#*before write, iclass 19, count 0 2006.176.07:20:19.29#ibcon#enter sib2, iclass 19, count 0 2006.176.07:20:19.29#ibcon#flushed, iclass 19, count 0 2006.176.07:20:19.29#ibcon#about to write, iclass 19, count 0 2006.176.07:20:19.29#ibcon#wrote, iclass 19, count 0 2006.176.07:20:19.29#ibcon#about to read 3, iclass 19, count 0 2006.176.07:20:19.33#ibcon#read 3, iclass 19, count 0 2006.176.07:20:19.33#ibcon#about to read 4, iclass 19, count 0 2006.176.07:20:19.33#ibcon#read 4, iclass 19, count 0 2006.176.07:20:19.33#ibcon#about to read 5, iclass 19, count 0 2006.176.07:20:19.33#ibcon#read 5, iclass 19, count 0 2006.176.07:20:19.33#ibcon#about to read 6, iclass 19, count 0 2006.176.07:20:19.33#ibcon#read 6, iclass 19, count 0 2006.176.07:20:19.33#ibcon#end of sib2, iclass 19, count 0 2006.176.07:20:19.33#ibcon#*after write, iclass 19, count 0 2006.176.07:20:19.33#ibcon#*before return 0, iclass 19, count 0 2006.176.07:20:19.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:20:19.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:20:19.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.07:20:19.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.07:20:19.33$vc4f8/va=8,6 2006.176.07:20:19.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.176.07:20:19.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.176.07:20:19.33#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:19.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:20:19.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:20:19.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:20:19.39#ibcon#enter wrdev, iclass 21, count 2 2006.176.07:20:19.39#ibcon#first serial, iclass 21, count 2 2006.176.07:20:19.39#ibcon#enter sib2, iclass 21, count 2 2006.176.07:20:19.39#ibcon#flushed, iclass 21, count 2 2006.176.07:20:19.39#ibcon#about to write, iclass 21, count 2 2006.176.07:20:19.39#ibcon#wrote, iclass 21, count 2 2006.176.07:20:19.39#ibcon#about to read 3, iclass 21, count 2 2006.176.07:20:19.41#ibcon#read 3, iclass 21, count 2 2006.176.07:20:19.41#ibcon#about to read 4, iclass 21, count 2 2006.176.07:20:19.41#ibcon#read 4, iclass 21, count 2 2006.176.07:20:19.41#ibcon#about to read 5, iclass 21, count 2 2006.176.07:20:19.41#ibcon#read 5, iclass 21, count 2 2006.176.07:20:19.41#ibcon#about to read 6, iclass 21, count 2 2006.176.07:20:19.41#ibcon#read 6, iclass 21, count 2 2006.176.07:20:19.41#ibcon#end of sib2, iclass 21, count 2 2006.176.07:20:19.41#ibcon#*mode == 0, iclass 21, count 2 2006.176.07:20:19.41#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.176.07:20:19.41#ibcon#[25=AT08-06\r\n] 2006.176.07:20:19.41#ibcon#*before write, iclass 21, count 2 2006.176.07:20:19.41#ibcon#enter sib2, iclass 21, count 2 2006.176.07:20:19.41#ibcon#flushed, iclass 21, count 2 2006.176.07:20:19.41#ibcon#about to write, iclass 21, count 2 2006.176.07:20:19.41#ibcon#wrote, iclass 21, count 2 2006.176.07:20:19.41#ibcon#about to read 3, iclass 21, count 2 2006.176.07:20:19.44#ibcon#read 3, iclass 21, count 2 2006.176.07:20:19.44#ibcon#about to read 4, iclass 21, count 2 2006.176.07:20:19.44#ibcon#read 4, iclass 21, count 2 2006.176.07:20:19.44#ibcon#about to read 5, iclass 21, count 2 2006.176.07:20:19.44#ibcon#read 5, iclass 21, count 2 2006.176.07:20:19.44#ibcon#about to read 6, iclass 21, count 2 2006.176.07:20:19.44#ibcon#read 6, iclass 21, count 2 2006.176.07:20:19.44#ibcon#end of sib2, iclass 21, count 2 2006.176.07:20:19.44#ibcon#*after write, iclass 21, count 2 2006.176.07:20:19.44#ibcon#*before return 0, iclass 21, count 2 2006.176.07:20:19.44#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:20:19.44#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:20:19.44#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.176.07:20:19.44#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:19.44#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:20:19.56#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:20:19.56#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:20:19.56#ibcon#enter wrdev, iclass 21, count 0 2006.176.07:20:19.56#ibcon#first serial, iclass 21, count 0 2006.176.07:20:19.56#ibcon#enter sib2, iclass 21, count 0 2006.176.07:20:19.56#ibcon#flushed, iclass 21, count 0 2006.176.07:20:19.56#ibcon#about to write, iclass 21, count 0 2006.176.07:20:19.56#ibcon#wrote, iclass 21, count 0 2006.176.07:20:19.56#ibcon#about to read 3, iclass 21, count 0 2006.176.07:20:19.58#ibcon#read 3, iclass 21, count 0 2006.176.07:20:19.58#ibcon#about to read 4, iclass 21, count 0 2006.176.07:20:19.58#ibcon#read 4, iclass 21, count 0 2006.176.07:20:19.58#ibcon#about to read 5, iclass 21, count 0 2006.176.07:20:19.58#ibcon#read 5, iclass 21, count 0 2006.176.07:20:19.58#ibcon#about to read 6, iclass 21, count 0 2006.176.07:20:19.58#ibcon#read 6, iclass 21, count 0 2006.176.07:20:19.58#ibcon#end of sib2, iclass 21, count 0 2006.176.07:20:19.58#ibcon#*mode == 0, iclass 21, count 0 2006.176.07:20:19.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.07:20:19.58#ibcon#[25=USB\r\n] 2006.176.07:20:19.58#ibcon#*before write, iclass 21, count 0 2006.176.07:20:19.58#ibcon#enter sib2, iclass 21, count 0 2006.176.07:20:19.58#ibcon#flushed, iclass 21, count 0 2006.176.07:20:19.58#ibcon#about to write, iclass 21, count 0 2006.176.07:20:19.58#ibcon#wrote, iclass 21, count 0 2006.176.07:20:19.58#ibcon#about to read 3, iclass 21, count 0 2006.176.07:20:19.61#ibcon#read 3, iclass 21, count 0 2006.176.07:20:19.61#ibcon#about to read 4, iclass 21, count 0 2006.176.07:20:19.61#ibcon#read 4, iclass 21, count 0 2006.176.07:20:19.61#ibcon#about to read 5, iclass 21, count 0 2006.176.07:20:19.61#ibcon#read 5, iclass 21, count 0 2006.176.07:20:19.61#ibcon#about to read 6, iclass 21, count 0 2006.176.07:20:19.61#ibcon#read 6, iclass 21, count 0 2006.176.07:20:19.61#ibcon#end of sib2, iclass 21, count 0 2006.176.07:20:19.61#ibcon#*after write, iclass 21, count 0 2006.176.07:20:19.61#ibcon#*before return 0, iclass 21, count 0 2006.176.07:20:19.61#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:20:19.61#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:20:19.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.07:20:19.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.07:20:19.61$vc4f8/vblo=1,632.99 2006.176.07:20:19.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.07:20:19.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.07:20:19.61#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:19.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:20:19.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:20:19.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:20:19.61#ibcon#enter wrdev, iclass 23, count 0 2006.176.07:20:19.61#ibcon#first serial, iclass 23, count 0 2006.176.07:20:19.61#ibcon#enter sib2, iclass 23, count 0 2006.176.07:20:19.61#ibcon#flushed, iclass 23, count 0 2006.176.07:20:19.61#ibcon#about to write, iclass 23, count 0 2006.176.07:20:19.61#ibcon#wrote, iclass 23, count 0 2006.176.07:20:19.61#ibcon#about to read 3, iclass 23, count 0 2006.176.07:20:19.63#ibcon#read 3, iclass 23, count 0 2006.176.07:20:19.63#ibcon#about to read 4, iclass 23, count 0 2006.176.07:20:19.63#ibcon#read 4, iclass 23, count 0 2006.176.07:20:19.63#ibcon#about to read 5, iclass 23, count 0 2006.176.07:20:19.63#ibcon#read 5, iclass 23, count 0 2006.176.07:20:19.63#ibcon#about to read 6, iclass 23, count 0 2006.176.07:20:19.63#ibcon#read 6, iclass 23, count 0 2006.176.07:20:19.63#ibcon#end of sib2, iclass 23, count 0 2006.176.07:20:19.63#ibcon#*mode == 0, iclass 23, count 0 2006.176.07:20:19.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.07:20:19.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:20:19.63#ibcon#*before write, iclass 23, count 0 2006.176.07:20:19.63#ibcon#enter sib2, iclass 23, count 0 2006.176.07:20:19.63#ibcon#flushed, iclass 23, count 0 2006.176.07:20:19.63#ibcon#about to write, iclass 23, count 0 2006.176.07:20:19.63#ibcon#wrote, iclass 23, count 0 2006.176.07:20:19.63#ibcon#about to read 3, iclass 23, count 0 2006.176.07:20:19.67#ibcon#read 3, iclass 23, count 0 2006.176.07:20:19.67#ibcon#about to read 4, iclass 23, count 0 2006.176.07:20:19.67#ibcon#read 4, iclass 23, count 0 2006.176.07:20:19.67#ibcon#about to read 5, iclass 23, count 0 2006.176.07:20:19.67#ibcon#read 5, iclass 23, count 0 2006.176.07:20:19.67#ibcon#about to read 6, iclass 23, count 0 2006.176.07:20:19.67#ibcon#read 6, iclass 23, count 0 2006.176.07:20:19.67#ibcon#end of sib2, iclass 23, count 0 2006.176.07:20:19.67#ibcon#*after write, iclass 23, count 0 2006.176.07:20:19.67#ibcon#*before return 0, iclass 23, count 0 2006.176.07:20:19.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:20:19.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:20:19.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.07:20:19.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.07:20:19.67$vc4f8/vb=1,4 2006.176.07:20:19.67#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.176.07:20:19.67#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.176.07:20:19.67#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:19.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:20:19.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:20:19.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:20:19.67#ibcon#enter wrdev, iclass 25, count 2 2006.176.07:20:19.67#ibcon#first serial, iclass 25, count 2 2006.176.07:20:19.67#ibcon#enter sib2, iclass 25, count 2 2006.176.07:20:19.67#ibcon#flushed, iclass 25, count 2 2006.176.07:20:19.67#ibcon#about to write, iclass 25, count 2 2006.176.07:20:19.67#ibcon#wrote, iclass 25, count 2 2006.176.07:20:19.67#ibcon#about to read 3, iclass 25, count 2 2006.176.07:20:19.69#ibcon#read 3, iclass 25, count 2 2006.176.07:20:19.69#ibcon#about to read 4, iclass 25, count 2 2006.176.07:20:19.69#ibcon#read 4, iclass 25, count 2 2006.176.07:20:19.69#ibcon#about to read 5, iclass 25, count 2 2006.176.07:20:19.69#ibcon#read 5, iclass 25, count 2 2006.176.07:20:19.69#ibcon#about to read 6, iclass 25, count 2 2006.176.07:20:19.69#ibcon#read 6, iclass 25, count 2 2006.176.07:20:19.69#ibcon#end of sib2, iclass 25, count 2 2006.176.07:20:19.69#ibcon#*mode == 0, iclass 25, count 2 2006.176.07:20:19.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.176.07:20:19.69#ibcon#[27=AT01-04\r\n] 2006.176.07:20:19.69#ibcon#*before write, iclass 25, count 2 2006.176.07:20:19.69#ibcon#enter sib2, iclass 25, count 2 2006.176.07:20:19.69#ibcon#flushed, iclass 25, count 2 2006.176.07:20:19.69#ibcon#about to write, iclass 25, count 2 2006.176.07:20:19.69#ibcon#wrote, iclass 25, count 2 2006.176.07:20:19.69#ibcon#about to read 3, iclass 25, count 2 2006.176.07:20:19.72#ibcon#read 3, iclass 25, count 2 2006.176.07:20:19.72#ibcon#about to read 4, iclass 25, count 2 2006.176.07:20:19.72#ibcon#read 4, iclass 25, count 2 2006.176.07:20:19.72#ibcon#about to read 5, iclass 25, count 2 2006.176.07:20:19.72#ibcon#read 5, iclass 25, count 2 2006.176.07:20:19.72#ibcon#about to read 6, iclass 25, count 2 2006.176.07:20:19.72#ibcon#read 6, iclass 25, count 2 2006.176.07:20:19.72#ibcon#end of sib2, iclass 25, count 2 2006.176.07:20:19.72#ibcon#*after write, iclass 25, count 2 2006.176.07:20:19.72#ibcon#*before return 0, iclass 25, count 2 2006.176.07:20:19.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:20:19.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:20:19.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.176.07:20:19.72#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:19.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:20:19.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:20:19.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:20:19.84#ibcon#enter wrdev, iclass 25, count 0 2006.176.07:20:19.84#ibcon#first serial, iclass 25, count 0 2006.176.07:20:19.84#ibcon#enter sib2, iclass 25, count 0 2006.176.07:20:19.84#ibcon#flushed, iclass 25, count 0 2006.176.07:20:19.84#ibcon#about to write, iclass 25, count 0 2006.176.07:20:19.84#ibcon#wrote, iclass 25, count 0 2006.176.07:20:19.84#ibcon#about to read 3, iclass 25, count 0 2006.176.07:20:19.86#ibcon#read 3, iclass 25, count 0 2006.176.07:20:19.86#ibcon#about to read 4, iclass 25, count 0 2006.176.07:20:19.86#ibcon#read 4, iclass 25, count 0 2006.176.07:20:19.86#ibcon#about to read 5, iclass 25, count 0 2006.176.07:20:19.86#ibcon#read 5, iclass 25, count 0 2006.176.07:20:19.86#ibcon#about to read 6, iclass 25, count 0 2006.176.07:20:19.86#ibcon#read 6, iclass 25, count 0 2006.176.07:20:19.86#ibcon#end of sib2, iclass 25, count 0 2006.176.07:20:19.86#ibcon#*mode == 0, iclass 25, count 0 2006.176.07:20:19.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.07:20:19.86#ibcon#[27=USB\r\n] 2006.176.07:20:19.86#ibcon#*before write, iclass 25, count 0 2006.176.07:20:19.86#ibcon#enter sib2, iclass 25, count 0 2006.176.07:20:19.86#ibcon#flushed, iclass 25, count 0 2006.176.07:20:19.86#ibcon#about to write, iclass 25, count 0 2006.176.07:20:19.86#ibcon#wrote, iclass 25, count 0 2006.176.07:20:19.86#ibcon#about to read 3, iclass 25, count 0 2006.176.07:20:19.89#ibcon#read 3, iclass 25, count 0 2006.176.07:20:19.89#ibcon#about to read 4, iclass 25, count 0 2006.176.07:20:19.89#ibcon#read 4, iclass 25, count 0 2006.176.07:20:19.89#ibcon#about to read 5, iclass 25, count 0 2006.176.07:20:19.89#ibcon#read 5, iclass 25, count 0 2006.176.07:20:19.89#ibcon#about to read 6, iclass 25, count 0 2006.176.07:20:19.89#ibcon#read 6, iclass 25, count 0 2006.176.07:20:19.89#ibcon#end of sib2, iclass 25, count 0 2006.176.07:20:19.89#ibcon#*after write, iclass 25, count 0 2006.176.07:20:19.89#ibcon#*before return 0, iclass 25, count 0 2006.176.07:20:19.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:20:19.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:20:19.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.07:20:19.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.07:20:19.89$vc4f8/vblo=2,640.99 2006.176.07:20:19.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.07:20:19.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.07:20:19.89#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:19.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:19.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:19.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:19.89#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:20:19.89#ibcon#first serial, iclass 27, count 0 2006.176.07:20:19.89#ibcon#enter sib2, iclass 27, count 0 2006.176.07:20:19.89#ibcon#flushed, iclass 27, count 0 2006.176.07:20:19.89#ibcon#about to write, iclass 27, count 0 2006.176.07:20:19.89#ibcon#wrote, iclass 27, count 0 2006.176.07:20:19.89#ibcon#about to read 3, iclass 27, count 0 2006.176.07:20:19.91#ibcon#read 3, iclass 27, count 0 2006.176.07:20:19.91#ibcon#about to read 4, iclass 27, count 0 2006.176.07:20:19.91#ibcon#read 4, iclass 27, count 0 2006.176.07:20:19.91#ibcon#about to read 5, iclass 27, count 0 2006.176.07:20:19.91#ibcon#read 5, iclass 27, count 0 2006.176.07:20:19.91#ibcon#about to read 6, iclass 27, count 0 2006.176.07:20:19.91#ibcon#read 6, iclass 27, count 0 2006.176.07:20:19.91#ibcon#end of sib2, iclass 27, count 0 2006.176.07:20:19.91#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:20:19.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:20:19.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:20:19.91#ibcon#*before write, iclass 27, count 0 2006.176.07:20:19.91#ibcon#enter sib2, iclass 27, count 0 2006.176.07:20:19.91#ibcon#flushed, iclass 27, count 0 2006.176.07:20:19.91#ibcon#about to write, iclass 27, count 0 2006.176.07:20:19.91#ibcon#wrote, iclass 27, count 0 2006.176.07:20:19.91#ibcon#about to read 3, iclass 27, count 0 2006.176.07:20:19.95#ibcon#read 3, iclass 27, count 0 2006.176.07:20:19.95#ibcon#about to read 4, iclass 27, count 0 2006.176.07:20:19.95#ibcon#read 4, iclass 27, count 0 2006.176.07:20:19.95#ibcon#about to read 5, iclass 27, count 0 2006.176.07:20:19.95#ibcon#read 5, iclass 27, count 0 2006.176.07:20:19.95#ibcon#about to read 6, iclass 27, count 0 2006.176.07:20:19.95#ibcon#read 6, iclass 27, count 0 2006.176.07:20:19.95#ibcon#end of sib2, iclass 27, count 0 2006.176.07:20:19.95#ibcon#*after write, iclass 27, count 0 2006.176.07:20:19.95#ibcon#*before return 0, iclass 27, count 0 2006.176.07:20:19.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:19.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:20:19.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:20:19.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:20:19.95$vc4f8/vb=2,4 2006.176.07:20:19.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.07:20:19.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.07:20:19.95#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:19.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:20.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:20.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:20.01#ibcon#enter wrdev, iclass 29, count 2 2006.176.07:20:20.01#ibcon#first serial, iclass 29, count 2 2006.176.07:20:20.01#ibcon#enter sib2, iclass 29, count 2 2006.176.07:20:20.01#ibcon#flushed, iclass 29, count 2 2006.176.07:20:20.01#ibcon#about to write, iclass 29, count 2 2006.176.07:20:20.01#ibcon#wrote, iclass 29, count 2 2006.176.07:20:20.01#ibcon#about to read 3, iclass 29, count 2 2006.176.07:20:20.03#ibcon#read 3, iclass 29, count 2 2006.176.07:20:20.03#ibcon#about to read 4, iclass 29, count 2 2006.176.07:20:20.03#ibcon#read 4, iclass 29, count 2 2006.176.07:20:20.03#ibcon#about to read 5, iclass 29, count 2 2006.176.07:20:20.03#ibcon#read 5, iclass 29, count 2 2006.176.07:20:20.03#ibcon#about to read 6, iclass 29, count 2 2006.176.07:20:20.03#ibcon#read 6, iclass 29, count 2 2006.176.07:20:20.03#ibcon#end of sib2, iclass 29, count 2 2006.176.07:20:20.03#ibcon#*mode == 0, iclass 29, count 2 2006.176.07:20:20.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.07:20:20.03#ibcon#[27=AT02-04\r\n] 2006.176.07:20:20.03#ibcon#*before write, iclass 29, count 2 2006.176.07:20:20.03#ibcon#enter sib2, iclass 29, count 2 2006.176.07:20:20.03#ibcon#flushed, iclass 29, count 2 2006.176.07:20:20.03#ibcon#about to write, iclass 29, count 2 2006.176.07:20:20.03#ibcon#wrote, iclass 29, count 2 2006.176.07:20:20.03#ibcon#about to read 3, iclass 29, count 2 2006.176.07:20:20.06#ibcon#read 3, iclass 29, count 2 2006.176.07:20:20.06#ibcon#about to read 4, iclass 29, count 2 2006.176.07:20:20.06#ibcon#read 4, iclass 29, count 2 2006.176.07:20:20.06#ibcon#about to read 5, iclass 29, count 2 2006.176.07:20:20.06#ibcon#read 5, iclass 29, count 2 2006.176.07:20:20.06#ibcon#about to read 6, iclass 29, count 2 2006.176.07:20:20.06#ibcon#read 6, iclass 29, count 2 2006.176.07:20:20.06#ibcon#end of sib2, iclass 29, count 2 2006.176.07:20:20.06#ibcon#*after write, iclass 29, count 2 2006.176.07:20:20.06#ibcon#*before return 0, iclass 29, count 2 2006.176.07:20:20.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:20.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:20:20.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.07:20:20.06#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:20.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:20.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:20.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:20.18#ibcon#enter wrdev, iclass 29, count 0 2006.176.07:20:20.18#ibcon#first serial, iclass 29, count 0 2006.176.07:20:20.18#ibcon#enter sib2, iclass 29, count 0 2006.176.07:20:20.18#ibcon#flushed, iclass 29, count 0 2006.176.07:20:20.18#ibcon#about to write, iclass 29, count 0 2006.176.07:20:20.18#ibcon#wrote, iclass 29, count 0 2006.176.07:20:20.18#ibcon#about to read 3, iclass 29, count 0 2006.176.07:20:20.20#ibcon#read 3, iclass 29, count 0 2006.176.07:20:20.20#ibcon#about to read 4, iclass 29, count 0 2006.176.07:20:20.20#ibcon#read 4, iclass 29, count 0 2006.176.07:20:20.20#ibcon#about to read 5, iclass 29, count 0 2006.176.07:20:20.20#ibcon#read 5, iclass 29, count 0 2006.176.07:20:20.20#ibcon#about to read 6, iclass 29, count 0 2006.176.07:20:20.20#ibcon#read 6, iclass 29, count 0 2006.176.07:20:20.20#ibcon#end of sib2, iclass 29, count 0 2006.176.07:20:20.20#ibcon#*mode == 0, iclass 29, count 0 2006.176.07:20:20.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.07:20:20.20#ibcon#[27=USB\r\n] 2006.176.07:20:20.20#ibcon#*before write, iclass 29, count 0 2006.176.07:20:20.20#ibcon#enter sib2, iclass 29, count 0 2006.176.07:20:20.20#ibcon#flushed, iclass 29, count 0 2006.176.07:20:20.20#ibcon#about to write, iclass 29, count 0 2006.176.07:20:20.20#ibcon#wrote, iclass 29, count 0 2006.176.07:20:20.20#ibcon#about to read 3, iclass 29, count 0 2006.176.07:20:20.23#ibcon#read 3, iclass 29, count 0 2006.176.07:20:20.23#ibcon#about to read 4, iclass 29, count 0 2006.176.07:20:20.23#ibcon#read 4, iclass 29, count 0 2006.176.07:20:20.23#ibcon#about to read 5, iclass 29, count 0 2006.176.07:20:20.23#ibcon#read 5, iclass 29, count 0 2006.176.07:20:20.23#ibcon#about to read 6, iclass 29, count 0 2006.176.07:20:20.23#ibcon#read 6, iclass 29, count 0 2006.176.07:20:20.23#ibcon#end of sib2, iclass 29, count 0 2006.176.07:20:20.23#ibcon#*after write, iclass 29, count 0 2006.176.07:20:20.23#ibcon#*before return 0, iclass 29, count 0 2006.176.07:20:20.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:20.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:20:20.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.07:20:20.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.07:20:20.23$vc4f8/vblo=3,656.99 2006.176.07:20:20.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.07:20:20.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.07:20:20.23#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:20.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:20.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:20.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:20.23#ibcon#enter wrdev, iclass 31, count 0 2006.176.07:20:20.23#ibcon#first serial, iclass 31, count 0 2006.176.07:20:20.23#ibcon#enter sib2, iclass 31, count 0 2006.176.07:20:20.23#ibcon#flushed, iclass 31, count 0 2006.176.07:20:20.23#ibcon#about to write, iclass 31, count 0 2006.176.07:20:20.23#ibcon#wrote, iclass 31, count 0 2006.176.07:20:20.23#ibcon#about to read 3, iclass 31, count 0 2006.176.07:20:20.25#ibcon#read 3, iclass 31, count 0 2006.176.07:20:20.25#ibcon#about to read 4, iclass 31, count 0 2006.176.07:20:20.25#ibcon#read 4, iclass 31, count 0 2006.176.07:20:20.25#ibcon#about to read 5, iclass 31, count 0 2006.176.07:20:20.25#ibcon#read 5, iclass 31, count 0 2006.176.07:20:20.25#ibcon#about to read 6, iclass 31, count 0 2006.176.07:20:20.25#ibcon#read 6, iclass 31, count 0 2006.176.07:20:20.25#ibcon#end of sib2, iclass 31, count 0 2006.176.07:20:20.25#ibcon#*mode == 0, iclass 31, count 0 2006.176.07:20:20.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.07:20:20.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:20:20.25#ibcon#*before write, iclass 31, count 0 2006.176.07:20:20.25#ibcon#enter sib2, iclass 31, count 0 2006.176.07:20:20.25#ibcon#flushed, iclass 31, count 0 2006.176.07:20:20.25#ibcon#about to write, iclass 31, count 0 2006.176.07:20:20.25#ibcon#wrote, iclass 31, count 0 2006.176.07:20:20.25#ibcon#about to read 3, iclass 31, count 0 2006.176.07:20:20.29#ibcon#read 3, iclass 31, count 0 2006.176.07:20:20.29#ibcon#about to read 4, iclass 31, count 0 2006.176.07:20:20.29#ibcon#read 4, iclass 31, count 0 2006.176.07:20:20.29#ibcon#about to read 5, iclass 31, count 0 2006.176.07:20:20.29#ibcon#read 5, iclass 31, count 0 2006.176.07:20:20.29#ibcon#about to read 6, iclass 31, count 0 2006.176.07:20:20.29#ibcon#read 6, iclass 31, count 0 2006.176.07:20:20.29#ibcon#end of sib2, iclass 31, count 0 2006.176.07:20:20.29#ibcon#*after write, iclass 31, count 0 2006.176.07:20:20.29#ibcon#*before return 0, iclass 31, count 0 2006.176.07:20:20.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:20.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:20:20.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.07:20:20.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.07:20:20.29$vc4f8/vb=3,4 2006.176.07:20:20.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.176.07:20:20.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.176.07:20:20.29#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:20.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:20.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:20.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:20.35#ibcon#enter wrdev, iclass 33, count 2 2006.176.07:20:20.35#ibcon#first serial, iclass 33, count 2 2006.176.07:20:20.35#ibcon#enter sib2, iclass 33, count 2 2006.176.07:20:20.35#ibcon#flushed, iclass 33, count 2 2006.176.07:20:20.35#ibcon#about to write, iclass 33, count 2 2006.176.07:20:20.35#ibcon#wrote, iclass 33, count 2 2006.176.07:20:20.35#ibcon#about to read 3, iclass 33, count 2 2006.176.07:20:20.37#ibcon#read 3, iclass 33, count 2 2006.176.07:20:20.37#ibcon#about to read 4, iclass 33, count 2 2006.176.07:20:20.37#ibcon#read 4, iclass 33, count 2 2006.176.07:20:20.37#ibcon#about to read 5, iclass 33, count 2 2006.176.07:20:20.37#ibcon#read 5, iclass 33, count 2 2006.176.07:20:20.37#ibcon#about to read 6, iclass 33, count 2 2006.176.07:20:20.37#ibcon#read 6, iclass 33, count 2 2006.176.07:20:20.37#ibcon#end of sib2, iclass 33, count 2 2006.176.07:20:20.37#ibcon#*mode == 0, iclass 33, count 2 2006.176.07:20:20.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.176.07:20:20.37#ibcon#[27=AT03-04\r\n] 2006.176.07:20:20.37#ibcon#*before write, iclass 33, count 2 2006.176.07:20:20.37#ibcon#enter sib2, iclass 33, count 2 2006.176.07:20:20.37#ibcon#flushed, iclass 33, count 2 2006.176.07:20:20.37#ibcon#about to write, iclass 33, count 2 2006.176.07:20:20.37#ibcon#wrote, iclass 33, count 2 2006.176.07:20:20.37#ibcon#about to read 3, iclass 33, count 2 2006.176.07:20:20.40#ibcon#read 3, iclass 33, count 2 2006.176.07:20:20.40#ibcon#about to read 4, iclass 33, count 2 2006.176.07:20:20.40#ibcon#read 4, iclass 33, count 2 2006.176.07:20:20.40#ibcon#about to read 5, iclass 33, count 2 2006.176.07:20:20.40#ibcon#read 5, iclass 33, count 2 2006.176.07:20:20.40#ibcon#about to read 6, iclass 33, count 2 2006.176.07:20:20.40#ibcon#read 6, iclass 33, count 2 2006.176.07:20:20.40#ibcon#end of sib2, iclass 33, count 2 2006.176.07:20:20.40#ibcon#*after write, iclass 33, count 2 2006.176.07:20:20.40#ibcon#*before return 0, iclass 33, count 2 2006.176.07:20:20.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:20.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:20:20.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.176.07:20:20.40#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:20.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:20.51#abcon#<5=/05 4.1 7.0 24.09 911008.2\r\n> 2006.176.07:20:20.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:20.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:20.52#ibcon#enter wrdev, iclass 33, count 0 2006.176.07:20:20.52#ibcon#first serial, iclass 33, count 0 2006.176.07:20:20.52#ibcon#enter sib2, iclass 33, count 0 2006.176.07:20:20.52#ibcon#flushed, iclass 33, count 0 2006.176.07:20:20.52#ibcon#about to write, iclass 33, count 0 2006.176.07:20:20.52#ibcon#wrote, iclass 33, count 0 2006.176.07:20:20.52#ibcon#about to read 3, iclass 33, count 0 2006.176.07:20:20.53#abcon#{5=INTERFACE CLEAR} 2006.176.07:20:20.54#ibcon#read 3, iclass 33, count 0 2006.176.07:20:20.54#ibcon#about to read 4, iclass 33, count 0 2006.176.07:20:20.54#ibcon#read 4, iclass 33, count 0 2006.176.07:20:20.54#ibcon#about to read 5, iclass 33, count 0 2006.176.07:20:20.54#ibcon#read 5, iclass 33, count 0 2006.176.07:20:20.54#ibcon#about to read 6, iclass 33, count 0 2006.176.07:20:20.54#ibcon#read 6, iclass 33, count 0 2006.176.07:20:20.54#ibcon#end of sib2, iclass 33, count 0 2006.176.07:20:20.54#ibcon#*mode == 0, iclass 33, count 0 2006.176.07:20:20.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.07:20:20.54#ibcon#[27=USB\r\n] 2006.176.07:20:20.54#ibcon#*before write, iclass 33, count 0 2006.176.07:20:20.54#ibcon#enter sib2, iclass 33, count 0 2006.176.07:20:20.54#ibcon#flushed, iclass 33, count 0 2006.176.07:20:20.54#ibcon#about to write, iclass 33, count 0 2006.176.07:20:20.54#ibcon#wrote, iclass 33, count 0 2006.176.07:20:20.54#ibcon#about to read 3, iclass 33, count 0 2006.176.07:20:20.57#ibcon#read 3, iclass 33, count 0 2006.176.07:20:20.57#ibcon#about to read 4, iclass 33, count 0 2006.176.07:20:20.57#ibcon#read 4, iclass 33, count 0 2006.176.07:20:20.57#ibcon#about to read 5, iclass 33, count 0 2006.176.07:20:20.57#ibcon#read 5, iclass 33, count 0 2006.176.07:20:20.57#ibcon#about to read 6, iclass 33, count 0 2006.176.07:20:20.57#ibcon#read 6, iclass 33, count 0 2006.176.07:20:20.57#ibcon#end of sib2, iclass 33, count 0 2006.176.07:20:20.57#ibcon#*after write, iclass 33, count 0 2006.176.07:20:20.57#ibcon#*before return 0, iclass 33, count 0 2006.176.07:20:20.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:20.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:20:20.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.07:20:20.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.07:20:20.57$vc4f8/vblo=4,712.99 2006.176.07:20:20.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.07:20:20.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.07:20:20.57#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:20.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:20:20.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:20:20.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:20:20.57#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:20:20.57#ibcon#first serial, iclass 38, count 0 2006.176.07:20:20.57#ibcon#enter sib2, iclass 38, count 0 2006.176.07:20:20.57#ibcon#flushed, iclass 38, count 0 2006.176.07:20:20.57#ibcon#about to write, iclass 38, count 0 2006.176.07:20:20.57#ibcon#wrote, iclass 38, count 0 2006.176.07:20:20.57#ibcon#about to read 3, iclass 38, count 0 2006.176.07:20:20.59#ibcon#read 3, iclass 38, count 0 2006.176.07:20:20.59#ibcon#about to read 4, iclass 38, count 0 2006.176.07:20:20.59#ibcon#read 4, iclass 38, count 0 2006.176.07:20:20.59#ibcon#about to read 5, iclass 38, count 0 2006.176.07:20:20.59#ibcon#read 5, iclass 38, count 0 2006.176.07:20:20.59#ibcon#about to read 6, iclass 38, count 0 2006.176.07:20:20.59#ibcon#read 6, iclass 38, count 0 2006.176.07:20:20.59#ibcon#end of sib2, iclass 38, count 0 2006.176.07:20:20.59#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:20:20.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:20:20.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:20:20.59#ibcon#*before write, iclass 38, count 0 2006.176.07:20:20.59#ibcon#enter sib2, iclass 38, count 0 2006.176.07:20:20.59#ibcon#flushed, iclass 38, count 0 2006.176.07:20:20.59#ibcon#about to write, iclass 38, count 0 2006.176.07:20:20.59#ibcon#wrote, iclass 38, count 0 2006.176.07:20:20.59#ibcon#about to read 3, iclass 38, count 0 2006.176.07:20:20.59#abcon#[5=S1D000X0/0*\r\n] 2006.176.07:20:20.63#ibcon#read 3, iclass 38, count 0 2006.176.07:20:20.63#ibcon#about to read 4, iclass 38, count 0 2006.176.07:20:20.63#ibcon#read 4, iclass 38, count 0 2006.176.07:20:20.63#ibcon#about to read 5, iclass 38, count 0 2006.176.07:20:20.63#ibcon#read 5, iclass 38, count 0 2006.176.07:20:20.63#ibcon#about to read 6, iclass 38, count 0 2006.176.07:20:20.63#ibcon#read 6, iclass 38, count 0 2006.176.07:20:20.63#ibcon#end of sib2, iclass 38, count 0 2006.176.07:20:20.63#ibcon#*after write, iclass 38, count 0 2006.176.07:20:20.63#ibcon#*before return 0, iclass 38, count 0 2006.176.07:20:20.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:20:20.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:20:20.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:20:20.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:20:20.63$vc4f8/vb=4,4 2006.176.07:20:20.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.07:20:20.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.07:20:20.63#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:20.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:20.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:20.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:20.69#ibcon#enter wrdev, iclass 3, count 2 2006.176.07:20:20.69#ibcon#first serial, iclass 3, count 2 2006.176.07:20:20.69#ibcon#enter sib2, iclass 3, count 2 2006.176.07:20:20.69#ibcon#flushed, iclass 3, count 2 2006.176.07:20:20.69#ibcon#about to write, iclass 3, count 2 2006.176.07:20:20.69#ibcon#wrote, iclass 3, count 2 2006.176.07:20:20.69#ibcon#about to read 3, iclass 3, count 2 2006.176.07:20:20.71#ibcon#read 3, iclass 3, count 2 2006.176.07:20:20.71#ibcon#about to read 4, iclass 3, count 2 2006.176.07:20:20.71#ibcon#read 4, iclass 3, count 2 2006.176.07:20:20.71#ibcon#about to read 5, iclass 3, count 2 2006.176.07:20:20.71#ibcon#read 5, iclass 3, count 2 2006.176.07:20:20.71#ibcon#about to read 6, iclass 3, count 2 2006.176.07:20:20.71#ibcon#read 6, iclass 3, count 2 2006.176.07:20:20.71#ibcon#end of sib2, iclass 3, count 2 2006.176.07:20:20.71#ibcon#*mode == 0, iclass 3, count 2 2006.176.07:20:20.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.07:20:20.71#ibcon#[27=AT04-04\r\n] 2006.176.07:20:20.71#ibcon#*before write, iclass 3, count 2 2006.176.07:20:20.71#ibcon#enter sib2, iclass 3, count 2 2006.176.07:20:20.71#ibcon#flushed, iclass 3, count 2 2006.176.07:20:20.71#ibcon#about to write, iclass 3, count 2 2006.176.07:20:20.71#ibcon#wrote, iclass 3, count 2 2006.176.07:20:20.71#ibcon#about to read 3, iclass 3, count 2 2006.176.07:20:20.74#ibcon#read 3, iclass 3, count 2 2006.176.07:20:20.74#ibcon#about to read 4, iclass 3, count 2 2006.176.07:20:20.74#ibcon#read 4, iclass 3, count 2 2006.176.07:20:20.74#ibcon#about to read 5, iclass 3, count 2 2006.176.07:20:20.74#ibcon#read 5, iclass 3, count 2 2006.176.07:20:20.74#ibcon#about to read 6, iclass 3, count 2 2006.176.07:20:20.74#ibcon#read 6, iclass 3, count 2 2006.176.07:20:20.74#ibcon#end of sib2, iclass 3, count 2 2006.176.07:20:20.74#ibcon#*after write, iclass 3, count 2 2006.176.07:20:20.74#ibcon#*before return 0, iclass 3, count 2 2006.176.07:20:20.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:20.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:20:20.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.07:20:20.74#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:20.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:20.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:20.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:20.86#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:20:20.86#ibcon#first serial, iclass 3, count 0 2006.176.07:20:20.86#ibcon#enter sib2, iclass 3, count 0 2006.176.07:20:20.86#ibcon#flushed, iclass 3, count 0 2006.176.07:20:20.86#ibcon#about to write, iclass 3, count 0 2006.176.07:20:20.86#ibcon#wrote, iclass 3, count 0 2006.176.07:20:20.86#ibcon#about to read 3, iclass 3, count 0 2006.176.07:20:20.88#ibcon#read 3, iclass 3, count 0 2006.176.07:20:20.88#ibcon#about to read 4, iclass 3, count 0 2006.176.07:20:20.88#ibcon#read 4, iclass 3, count 0 2006.176.07:20:20.88#ibcon#about to read 5, iclass 3, count 0 2006.176.07:20:20.88#ibcon#read 5, iclass 3, count 0 2006.176.07:20:20.88#ibcon#about to read 6, iclass 3, count 0 2006.176.07:20:20.88#ibcon#read 6, iclass 3, count 0 2006.176.07:20:20.88#ibcon#end of sib2, iclass 3, count 0 2006.176.07:20:20.88#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:20:20.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:20:20.88#ibcon#[27=USB\r\n] 2006.176.07:20:20.88#ibcon#*before write, iclass 3, count 0 2006.176.07:20:20.88#ibcon#enter sib2, iclass 3, count 0 2006.176.07:20:20.88#ibcon#flushed, iclass 3, count 0 2006.176.07:20:20.88#ibcon#about to write, iclass 3, count 0 2006.176.07:20:20.88#ibcon#wrote, iclass 3, count 0 2006.176.07:20:20.88#ibcon#about to read 3, iclass 3, count 0 2006.176.07:20:20.91#ibcon#read 3, iclass 3, count 0 2006.176.07:20:20.91#ibcon#about to read 4, iclass 3, count 0 2006.176.07:20:20.91#ibcon#read 4, iclass 3, count 0 2006.176.07:20:20.91#ibcon#about to read 5, iclass 3, count 0 2006.176.07:20:20.91#ibcon#read 5, iclass 3, count 0 2006.176.07:20:20.91#ibcon#about to read 6, iclass 3, count 0 2006.176.07:20:20.91#ibcon#read 6, iclass 3, count 0 2006.176.07:20:20.91#ibcon#end of sib2, iclass 3, count 0 2006.176.07:20:20.91#ibcon#*after write, iclass 3, count 0 2006.176.07:20:20.91#ibcon#*before return 0, iclass 3, count 0 2006.176.07:20:20.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:20.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:20:20.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:20:20.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:20:20.91$vc4f8/vblo=5,744.99 2006.176.07:20:20.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.07:20:20.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.07:20:20.91#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:20.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:20.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:20.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:20.91#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:20:20.91#ibcon#first serial, iclass 5, count 0 2006.176.07:20:20.91#ibcon#enter sib2, iclass 5, count 0 2006.176.07:20:20.91#ibcon#flushed, iclass 5, count 0 2006.176.07:20:20.91#ibcon#about to write, iclass 5, count 0 2006.176.07:20:20.91#ibcon#wrote, iclass 5, count 0 2006.176.07:20:20.91#ibcon#about to read 3, iclass 5, count 0 2006.176.07:20:20.93#ibcon#read 3, iclass 5, count 0 2006.176.07:20:20.93#ibcon#about to read 4, iclass 5, count 0 2006.176.07:20:20.93#ibcon#read 4, iclass 5, count 0 2006.176.07:20:20.93#ibcon#about to read 5, iclass 5, count 0 2006.176.07:20:20.93#ibcon#read 5, iclass 5, count 0 2006.176.07:20:20.93#ibcon#about to read 6, iclass 5, count 0 2006.176.07:20:20.93#ibcon#read 6, iclass 5, count 0 2006.176.07:20:20.93#ibcon#end of sib2, iclass 5, count 0 2006.176.07:20:20.93#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:20:20.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:20:20.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:20:20.93#ibcon#*before write, iclass 5, count 0 2006.176.07:20:20.93#ibcon#enter sib2, iclass 5, count 0 2006.176.07:20:20.93#ibcon#flushed, iclass 5, count 0 2006.176.07:20:20.93#ibcon#about to write, iclass 5, count 0 2006.176.07:20:20.93#ibcon#wrote, iclass 5, count 0 2006.176.07:20:20.93#ibcon#about to read 3, iclass 5, count 0 2006.176.07:20:20.97#ibcon#read 3, iclass 5, count 0 2006.176.07:20:20.97#ibcon#about to read 4, iclass 5, count 0 2006.176.07:20:20.97#ibcon#read 4, iclass 5, count 0 2006.176.07:20:20.97#ibcon#about to read 5, iclass 5, count 0 2006.176.07:20:20.97#ibcon#read 5, iclass 5, count 0 2006.176.07:20:20.97#ibcon#about to read 6, iclass 5, count 0 2006.176.07:20:20.97#ibcon#read 6, iclass 5, count 0 2006.176.07:20:20.97#ibcon#end of sib2, iclass 5, count 0 2006.176.07:20:20.97#ibcon#*after write, iclass 5, count 0 2006.176.07:20:20.97#ibcon#*before return 0, iclass 5, count 0 2006.176.07:20:20.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:20.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:20:20.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:20:20.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:20:20.97$vc4f8/vb=5,4 2006.176.07:20:20.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.07:20:20.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.07:20:20.97#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:20.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:21.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:21.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:21.03#ibcon#enter wrdev, iclass 7, count 2 2006.176.07:20:21.03#ibcon#first serial, iclass 7, count 2 2006.176.07:20:21.03#ibcon#enter sib2, iclass 7, count 2 2006.176.07:20:21.03#ibcon#flushed, iclass 7, count 2 2006.176.07:20:21.03#ibcon#about to write, iclass 7, count 2 2006.176.07:20:21.03#ibcon#wrote, iclass 7, count 2 2006.176.07:20:21.03#ibcon#about to read 3, iclass 7, count 2 2006.176.07:20:21.05#ibcon#read 3, iclass 7, count 2 2006.176.07:20:21.05#ibcon#about to read 4, iclass 7, count 2 2006.176.07:20:21.05#ibcon#read 4, iclass 7, count 2 2006.176.07:20:21.05#ibcon#about to read 5, iclass 7, count 2 2006.176.07:20:21.05#ibcon#read 5, iclass 7, count 2 2006.176.07:20:21.05#ibcon#about to read 6, iclass 7, count 2 2006.176.07:20:21.05#ibcon#read 6, iclass 7, count 2 2006.176.07:20:21.05#ibcon#end of sib2, iclass 7, count 2 2006.176.07:20:21.05#ibcon#*mode == 0, iclass 7, count 2 2006.176.07:20:21.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.07:20:21.05#ibcon#[27=AT05-04\r\n] 2006.176.07:20:21.05#ibcon#*before write, iclass 7, count 2 2006.176.07:20:21.05#ibcon#enter sib2, iclass 7, count 2 2006.176.07:20:21.05#ibcon#flushed, iclass 7, count 2 2006.176.07:20:21.05#ibcon#about to write, iclass 7, count 2 2006.176.07:20:21.05#ibcon#wrote, iclass 7, count 2 2006.176.07:20:21.05#ibcon#about to read 3, iclass 7, count 2 2006.176.07:20:21.08#ibcon#read 3, iclass 7, count 2 2006.176.07:20:21.08#ibcon#about to read 4, iclass 7, count 2 2006.176.07:20:21.08#ibcon#read 4, iclass 7, count 2 2006.176.07:20:21.08#ibcon#about to read 5, iclass 7, count 2 2006.176.07:20:21.08#ibcon#read 5, iclass 7, count 2 2006.176.07:20:21.08#ibcon#about to read 6, iclass 7, count 2 2006.176.07:20:21.08#ibcon#read 6, iclass 7, count 2 2006.176.07:20:21.08#ibcon#end of sib2, iclass 7, count 2 2006.176.07:20:21.08#ibcon#*after write, iclass 7, count 2 2006.176.07:20:21.08#ibcon#*before return 0, iclass 7, count 2 2006.176.07:20:21.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:21.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:20:21.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.07:20:21.08#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:21.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:21.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:21.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:21.20#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:20:21.20#ibcon#first serial, iclass 7, count 0 2006.176.07:20:21.20#ibcon#enter sib2, iclass 7, count 0 2006.176.07:20:21.20#ibcon#flushed, iclass 7, count 0 2006.176.07:20:21.20#ibcon#about to write, iclass 7, count 0 2006.176.07:20:21.20#ibcon#wrote, iclass 7, count 0 2006.176.07:20:21.20#ibcon#about to read 3, iclass 7, count 0 2006.176.07:20:21.22#ibcon#read 3, iclass 7, count 0 2006.176.07:20:21.22#ibcon#about to read 4, iclass 7, count 0 2006.176.07:20:21.22#ibcon#read 4, iclass 7, count 0 2006.176.07:20:21.22#ibcon#about to read 5, iclass 7, count 0 2006.176.07:20:21.22#ibcon#read 5, iclass 7, count 0 2006.176.07:20:21.22#ibcon#about to read 6, iclass 7, count 0 2006.176.07:20:21.22#ibcon#read 6, iclass 7, count 0 2006.176.07:20:21.22#ibcon#end of sib2, iclass 7, count 0 2006.176.07:20:21.22#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:20:21.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:20:21.22#ibcon#[27=USB\r\n] 2006.176.07:20:21.22#ibcon#*before write, iclass 7, count 0 2006.176.07:20:21.22#ibcon#enter sib2, iclass 7, count 0 2006.176.07:20:21.22#ibcon#flushed, iclass 7, count 0 2006.176.07:20:21.22#ibcon#about to write, iclass 7, count 0 2006.176.07:20:21.22#ibcon#wrote, iclass 7, count 0 2006.176.07:20:21.22#ibcon#about to read 3, iclass 7, count 0 2006.176.07:20:21.25#ibcon#read 3, iclass 7, count 0 2006.176.07:20:21.25#ibcon#about to read 4, iclass 7, count 0 2006.176.07:20:21.25#ibcon#read 4, iclass 7, count 0 2006.176.07:20:21.25#ibcon#about to read 5, iclass 7, count 0 2006.176.07:20:21.25#ibcon#read 5, iclass 7, count 0 2006.176.07:20:21.25#ibcon#about to read 6, iclass 7, count 0 2006.176.07:20:21.25#ibcon#read 6, iclass 7, count 0 2006.176.07:20:21.25#ibcon#end of sib2, iclass 7, count 0 2006.176.07:20:21.25#ibcon#*after write, iclass 7, count 0 2006.176.07:20:21.25#ibcon#*before return 0, iclass 7, count 0 2006.176.07:20:21.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:21.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:20:21.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:20:21.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:20:21.25$vc4f8/vblo=6,752.99 2006.176.07:20:21.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.07:20:21.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.07:20:21.25#ibcon#ireg 17 cls_cnt 0 2006.176.07:20:21.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:21.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:21.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:21.25#ibcon#enter wrdev, iclass 11, count 0 2006.176.07:20:21.25#ibcon#first serial, iclass 11, count 0 2006.176.07:20:21.25#ibcon#enter sib2, iclass 11, count 0 2006.176.07:20:21.25#ibcon#flushed, iclass 11, count 0 2006.176.07:20:21.25#ibcon#about to write, iclass 11, count 0 2006.176.07:20:21.25#ibcon#wrote, iclass 11, count 0 2006.176.07:20:21.25#ibcon#about to read 3, iclass 11, count 0 2006.176.07:20:21.27#ibcon#read 3, iclass 11, count 0 2006.176.07:20:21.27#ibcon#about to read 4, iclass 11, count 0 2006.176.07:20:21.27#ibcon#read 4, iclass 11, count 0 2006.176.07:20:21.27#ibcon#about to read 5, iclass 11, count 0 2006.176.07:20:21.27#ibcon#read 5, iclass 11, count 0 2006.176.07:20:21.27#ibcon#about to read 6, iclass 11, count 0 2006.176.07:20:21.27#ibcon#read 6, iclass 11, count 0 2006.176.07:20:21.27#ibcon#end of sib2, iclass 11, count 0 2006.176.07:20:21.27#ibcon#*mode == 0, iclass 11, count 0 2006.176.07:20:21.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.07:20:21.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:20:21.27#ibcon#*before write, iclass 11, count 0 2006.176.07:20:21.27#ibcon#enter sib2, iclass 11, count 0 2006.176.07:20:21.27#ibcon#flushed, iclass 11, count 0 2006.176.07:20:21.27#ibcon#about to write, iclass 11, count 0 2006.176.07:20:21.27#ibcon#wrote, iclass 11, count 0 2006.176.07:20:21.27#ibcon#about to read 3, iclass 11, count 0 2006.176.07:20:21.31#ibcon#read 3, iclass 11, count 0 2006.176.07:20:21.31#ibcon#about to read 4, iclass 11, count 0 2006.176.07:20:21.31#ibcon#read 4, iclass 11, count 0 2006.176.07:20:21.31#ibcon#about to read 5, iclass 11, count 0 2006.176.07:20:21.31#ibcon#read 5, iclass 11, count 0 2006.176.07:20:21.31#ibcon#about to read 6, iclass 11, count 0 2006.176.07:20:21.31#ibcon#read 6, iclass 11, count 0 2006.176.07:20:21.31#ibcon#end of sib2, iclass 11, count 0 2006.176.07:20:21.31#ibcon#*after write, iclass 11, count 0 2006.176.07:20:21.31#ibcon#*before return 0, iclass 11, count 0 2006.176.07:20:21.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:21.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:20:21.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.07:20:21.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.07:20:21.31$vc4f8/vb=6,4 2006.176.07:20:21.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.07:20:21.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.07:20:21.31#ibcon#ireg 11 cls_cnt 2 2006.176.07:20:21.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:21.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:21.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:21.37#ibcon#enter wrdev, iclass 13, count 2 2006.176.07:20:21.37#ibcon#first serial, iclass 13, count 2 2006.176.07:20:21.37#ibcon#enter sib2, iclass 13, count 2 2006.176.07:20:21.37#ibcon#flushed, iclass 13, count 2 2006.176.07:20:21.37#ibcon#about to write, iclass 13, count 2 2006.176.07:20:21.37#ibcon#wrote, iclass 13, count 2 2006.176.07:20:21.37#ibcon#about to read 3, iclass 13, count 2 2006.176.07:20:21.39#ibcon#read 3, iclass 13, count 2 2006.176.07:20:21.39#ibcon#about to read 4, iclass 13, count 2 2006.176.07:20:21.39#ibcon#read 4, iclass 13, count 2 2006.176.07:20:21.39#ibcon#about to read 5, iclass 13, count 2 2006.176.07:20:21.39#ibcon#read 5, iclass 13, count 2 2006.176.07:20:21.39#ibcon#about to read 6, iclass 13, count 2 2006.176.07:20:21.39#ibcon#read 6, iclass 13, count 2 2006.176.07:20:21.39#ibcon#end of sib2, iclass 13, count 2 2006.176.07:20:21.39#ibcon#*mode == 0, iclass 13, count 2 2006.176.07:20:21.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.07:20:21.39#ibcon#[27=AT06-04\r\n] 2006.176.07:20:21.39#ibcon#*before write, iclass 13, count 2 2006.176.07:20:21.39#ibcon#enter sib2, iclass 13, count 2 2006.176.07:20:21.39#ibcon#flushed, iclass 13, count 2 2006.176.07:20:21.39#ibcon#about to write, iclass 13, count 2 2006.176.07:20:21.39#ibcon#wrote, iclass 13, count 2 2006.176.07:20:21.39#ibcon#about to read 3, iclass 13, count 2 2006.176.07:20:21.42#ibcon#read 3, iclass 13, count 2 2006.176.07:20:21.42#ibcon#about to read 4, iclass 13, count 2 2006.176.07:20:21.42#ibcon#read 4, iclass 13, count 2 2006.176.07:20:21.42#ibcon#about to read 5, iclass 13, count 2 2006.176.07:20:21.42#ibcon#read 5, iclass 13, count 2 2006.176.07:20:21.42#ibcon#about to read 6, iclass 13, count 2 2006.176.07:20:21.42#ibcon#read 6, iclass 13, count 2 2006.176.07:20:21.42#ibcon#end of sib2, iclass 13, count 2 2006.176.07:20:21.42#ibcon#*after write, iclass 13, count 2 2006.176.07:20:21.42#ibcon#*before return 0, iclass 13, count 2 2006.176.07:20:21.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:21.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:20:21.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.07:20:21.42#ibcon#ireg 7 cls_cnt 0 2006.176.07:20:21.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:21.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:21.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:21.54#ibcon#enter wrdev, iclass 13, count 0 2006.176.07:20:21.54#ibcon#first serial, iclass 13, count 0 2006.176.07:20:21.54#ibcon#enter sib2, iclass 13, count 0 2006.176.07:20:21.54#ibcon#flushed, iclass 13, count 0 2006.176.07:20:21.54#ibcon#about to write, iclass 13, count 0 2006.176.07:20:21.54#ibcon#wrote, iclass 13, count 0 2006.176.07:20:21.54#ibcon#about to read 3, iclass 13, count 0 2006.176.07:20:21.56#ibcon#read 3, iclass 13, count 0 2006.176.07:20:21.56#ibcon#about to read 4, iclass 13, count 0 2006.176.07:20:21.56#ibcon#read 4, iclass 13, count 0 2006.176.07:20:21.56#ibcon#about to read 5, iclass 13, count 0 2006.176.07:20:21.56#ibcon#read 5, iclass 13, count 0 2006.176.07:20:21.56#ibcon#about to read 6, iclass 13, count 0 2006.176.07:20:21.56#ibcon#read 6, iclass 13, count 0 2006.176.07:20:21.56#ibcon#end of sib2, iclass 13, count 0 2006.176.07:20:21.56#ibcon#*mode == 0, iclass 13, count 0 2006.176.07:20:21.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.07:20:21.56#ibcon#[27=USB\r\n] 2006.176.07:20:21.56#ibcon#*before write, iclass 13, count 0 2006.176.07:20:21.56#ibcon#enter sib2, iclass 13, count 0 2006.176.07:20:21.56#ibcon#flushed, iclass 13, count 0 2006.176.07:20:21.56#ibcon#about to write, iclass 13, count 0 2006.176.07:20:21.56#ibcon#wrote, iclass 13, count 0 2006.176.07:20:21.56#ibcon#about to read 3, iclass 13, count 0 2006.176.07:20:21.59#ibcon#read 3, iclass 13, count 0 2006.176.07:20:21.59#ibcon#about to read 4, iclass 13, count 0 2006.176.07:20:21.59#ibcon#read 4, iclass 13, count 0 2006.176.07:20:21.59#ibcon#about to read 5, iclass 13, count 0 2006.176.07:20:21.59#ibcon#read 5, iclass 13, count 0 2006.176.07:20:21.59#ibcon#about to read 6, iclass 13, count 0 2006.176.07:20:21.59#ibcon#read 6, iclass 13, count 0 2006.176.07:20:21.59#ibcon#end of sib2, iclass 13, count 0 2006.176.07:20:21.59#ibcon#*after write, iclass 13, count 0 2006.176.07:20:21.59#ibcon#*before return 0, iclass 13, count 0 2006.176.07:20:21.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:21.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:20:21.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.07:20:21.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.07:20:21.59$vc4f8/vabw=wide 2006.176.07:20:21.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.07:20:21.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.07:20:21.59#ibcon#ireg 8 cls_cnt 0 2006.176.07:20:21.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:21.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:21.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:21.59#ibcon#enter wrdev, iclass 15, count 0 2006.176.07:20:21.59#ibcon#first serial, iclass 15, count 0 2006.176.07:20:21.59#ibcon#enter sib2, iclass 15, count 0 2006.176.07:20:21.59#ibcon#flushed, iclass 15, count 0 2006.176.07:20:21.59#ibcon#about to write, iclass 15, count 0 2006.176.07:20:21.59#ibcon#wrote, iclass 15, count 0 2006.176.07:20:21.59#ibcon#about to read 3, iclass 15, count 0 2006.176.07:20:21.61#ibcon#read 3, iclass 15, count 0 2006.176.07:20:21.61#ibcon#about to read 4, iclass 15, count 0 2006.176.07:20:21.61#ibcon#read 4, iclass 15, count 0 2006.176.07:20:21.61#ibcon#about to read 5, iclass 15, count 0 2006.176.07:20:21.61#ibcon#read 5, iclass 15, count 0 2006.176.07:20:21.61#ibcon#about to read 6, iclass 15, count 0 2006.176.07:20:21.61#ibcon#read 6, iclass 15, count 0 2006.176.07:20:21.61#ibcon#end of sib2, iclass 15, count 0 2006.176.07:20:21.61#ibcon#*mode == 0, iclass 15, count 0 2006.176.07:20:21.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.07:20:21.61#ibcon#[25=BW32\r\n] 2006.176.07:20:21.61#ibcon#*before write, iclass 15, count 0 2006.176.07:20:21.61#ibcon#enter sib2, iclass 15, count 0 2006.176.07:20:21.61#ibcon#flushed, iclass 15, count 0 2006.176.07:20:21.61#ibcon#about to write, iclass 15, count 0 2006.176.07:20:21.61#ibcon#wrote, iclass 15, count 0 2006.176.07:20:21.61#ibcon#about to read 3, iclass 15, count 0 2006.176.07:20:21.64#ibcon#read 3, iclass 15, count 0 2006.176.07:20:21.64#ibcon#about to read 4, iclass 15, count 0 2006.176.07:20:21.64#ibcon#read 4, iclass 15, count 0 2006.176.07:20:21.64#ibcon#about to read 5, iclass 15, count 0 2006.176.07:20:21.64#ibcon#read 5, iclass 15, count 0 2006.176.07:20:21.64#ibcon#about to read 6, iclass 15, count 0 2006.176.07:20:21.64#ibcon#read 6, iclass 15, count 0 2006.176.07:20:21.64#ibcon#end of sib2, iclass 15, count 0 2006.176.07:20:21.64#ibcon#*after write, iclass 15, count 0 2006.176.07:20:21.64#ibcon#*before return 0, iclass 15, count 0 2006.176.07:20:21.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:21.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:20:21.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.07:20:21.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.07:20:21.64$vc4f8/vbbw=wide 2006.176.07:20:21.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.07:20:21.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.07:20:21.64#ibcon#ireg 8 cls_cnt 0 2006.176.07:20:21.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:20:21.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:20:21.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:20:21.71#ibcon#enter wrdev, iclass 17, count 0 2006.176.07:20:21.71#ibcon#first serial, iclass 17, count 0 2006.176.07:20:21.71#ibcon#enter sib2, iclass 17, count 0 2006.176.07:20:21.71#ibcon#flushed, iclass 17, count 0 2006.176.07:20:21.71#ibcon#about to write, iclass 17, count 0 2006.176.07:20:21.71#ibcon#wrote, iclass 17, count 0 2006.176.07:20:21.71#ibcon#about to read 3, iclass 17, count 0 2006.176.07:20:21.73#ibcon#read 3, iclass 17, count 0 2006.176.07:20:21.73#ibcon#about to read 4, iclass 17, count 0 2006.176.07:20:21.73#ibcon#read 4, iclass 17, count 0 2006.176.07:20:21.73#ibcon#about to read 5, iclass 17, count 0 2006.176.07:20:21.73#ibcon#read 5, iclass 17, count 0 2006.176.07:20:21.73#ibcon#about to read 6, iclass 17, count 0 2006.176.07:20:21.73#ibcon#read 6, iclass 17, count 0 2006.176.07:20:21.73#ibcon#end of sib2, iclass 17, count 0 2006.176.07:20:21.73#ibcon#*mode == 0, iclass 17, count 0 2006.176.07:20:21.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.07:20:21.73#ibcon#[27=BW32\r\n] 2006.176.07:20:21.73#ibcon#*before write, iclass 17, count 0 2006.176.07:20:21.73#ibcon#enter sib2, iclass 17, count 0 2006.176.07:20:21.73#ibcon#flushed, iclass 17, count 0 2006.176.07:20:21.73#ibcon#about to write, iclass 17, count 0 2006.176.07:20:21.73#ibcon#wrote, iclass 17, count 0 2006.176.07:20:21.73#ibcon#about to read 3, iclass 17, count 0 2006.176.07:20:21.76#ibcon#read 3, iclass 17, count 0 2006.176.07:20:21.76#ibcon#about to read 4, iclass 17, count 0 2006.176.07:20:21.76#ibcon#read 4, iclass 17, count 0 2006.176.07:20:21.76#ibcon#about to read 5, iclass 17, count 0 2006.176.07:20:21.76#ibcon#read 5, iclass 17, count 0 2006.176.07:20:21.76#ibcon#about to read 6, iclass 17, count 0 2006.176.07:20:21.76#ibcon#read 6, iclass 17, count 0 2006.176.07:20:21.76#ibcon#end of sib2, iclass 17, count 0 2006.176.07:20:21.76#ibcon#*after write, iclass 17, count 0 2006.176.07:20:21.76#ibcon#*before return 0, iclass 17, count 0 2006.176.07:20:21.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:20:21.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:20:21.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.07:20:21.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.07:20:21.76$4f8m12a/ifd4f 2006.176.07:20:21.76&ifd4f/lo= 2006.176.07:20:21.76&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:20:21.76&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:20:21.76&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:20:21.76&ifd4f/patch= 2006.176.07:20:21.76&ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:20:21.76&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:20:21.76&ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:20:21.76$ifd4f/lo= 2006.176.07:20:21.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:20:21.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:20:21.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:20:21.77$ifd4f/patch= 2006.176.07:20:21.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:20:21.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:20:21.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:20:21.77$4f8m12a/"form=m,16.000,1:2 2006.176.07:20:21.77$4f8m12a/"tpicd 2006.176.07:20:21.77$4f8m12a/echo=off 2006.176.07:20:21.77$4f8m12a/xlog=off 2006.176.07:20:21.77:!2006.176.07:29:50 2006.176.07:20:38.14#trakl#Source acquired 2006.176.07:20:38.14#flagr#flagr/antenna,acquired 2006.176.07:29:50.00:preob 2006.176.07:29:50.00&preob/onsource 2006.176.07:29:51.14/onsource/TRACKING 2006.176.07:29:51.14:!2006.176.07:30:00 2006.176.07:30:00.00:data_valid=on 2006.176.07:30:00.00:midob 2006.176.07:30:00.00&midob/onsource 2006.176.07:30:00.00&midob/wx 2006.176.07:30:00.00&midob/cable 2006.176.07:30:00.00&midob/va 2006.176.07:30:00.00&midob/valo 2006.176.07:30:00.00&midob/vb 2006.176.07:30:00.00&midob/vblo 2006.176.07:30:00.00&midob/vabw 2006.176.07:30:00.00&midob/vbbw 2006.176.07:30:00.00&midob/"form 2006.176.07:30:00.00&midob/xfe 2006.176.07:30:00.00&midob/ifatt 2006.176.07:30:00.00&midob/clockoff 2006.176.07:30:00.00&midob/sy=logmail 2006.176.07:30:00.00&midob/"sy=run setcl adapt & 2006.176.07:30:00.14/onsource/TRACKING 2006.176.07:30:00.14/wx/24.01,1008.3,91 2006.176.07:30:00.22/cable/+6.4933E-03 2006.176.07:30:01.31/va/01,08,usb,yes,29,31 2006.176.07:30:01.31/va/02,07,usb,yes,30,31 2006.176.07:30:01.31/va/03,06,usb,yes,31,31 2006.176.07:30:01.31/va/04,07,usb,yes,30,33 2006.176.07:30:01.31/va/05,07,usb,yes,32,34 2006.176.07:30:01.31/va/06,06,usb,yes,31,31 2006.176.07:30:01.31/va/07,06,usb,yes,32,31 2006.176.07:30:01.31/va/08,06,usb,yes,34,33 2006.176.07:30:01.54/valo/01,532.99,yes,locked 2006.176.07:30:01.54/valo/02,572.99,yes,locked 2006.176.07:30:01.54/valo/03,672.99,yes,locked 2006.176.07:30:01.54/valo/04,832.99,yes,locked 2006.176.07:30:01.54/valo/05,652.99,yes,locked 2006.176.07:30:01.54/valo/06,772.99,yes,locked 2006.176.07:30:01.54/valo/07,832.99,yes,locked 2006.176.07:30:01.54/valo/08,852.99,yes,locked 2006.176.07:30:02.63/vb/01,04,usb,yes,29,28 2006.176.07:30:02.63/vb/02,04,usb,yes,31,33 2006.176.07:30:02.63/vb/03,04,usb,yes,28,31 2006.176.07:30:02.63/vb/04,04,usb,yes,28,29 2006.176.07:30:02.63/vb/05,04,usb,yes,27,31 2006.176.07:30:02.63/vb/06,04,usb,yes,28,31 2006.176.07:30:02.63/vb/07,04,usb,yes,30,30 2006.176.07:30:02.63/vb/08,04,usb,yes,28,31 2006.176.07:30:02.87/vblo/01,632.99,yes,locked 2006.176.07:30:02.87/vblo/02,640.99,yes,locked 2006.176.07:30:02.87/vblo/03,656.99,yes,locked 2006.176.07:30:02.87/vblo/04,712.99,yes,locked 2006.176.07:30:02.87/vblo/05,744.99,yes,locked 2006.176.07:30:02.87/vblo/06,752.99,yes,locked 2006.176.07:30:02.87/vblo/07,734.99,yes,locked 2006.176.07:30:02.87/vblo/08,744.99,yes,locked 2006.176.07:30:03.02/vabw/8 2006.176.07:30:03.17/vbbw/8 2006.176.07:30:03.26/xfe/off,on,15.0 2006.176.07:30:03.64/ifatt/23,28,28,28 2006.176.07:30:03.64&clockoff/"gps-fmout=1p 2006.176.07:30:03.64&clockoff/fmout-gps=1p 2006.176.07:30:04.07/fmout-gps/S +3.72E-07 2006.176.07:30:04.14:!2006.176.07:31:00 2006.176.07:31:00.01:data_valid=off 2006.176.07:31:00.02:postob 2006.176.07:31:00.02&postob/cable 2006.176.07:31:00.02&postob/wx 2006.176.07:31:00.03&postob/clockoff 2006.176.07:31:00.21/cable/+6.4910E-03 2006.176.07:31:00.21/wx/24.00,1008.3,90 2006.176.07:31:00.30/fmout-gps/S +3.72E-07 2006.176.07:31:00.30:scan_name=176-0733,k06176,60 2006.176.07:31:00.30:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.176.07:31:01.14#flagr#flagr/antenna,new-source 2006.176.07:31:01.15:checkk5 2006.176.07:31:01.15&checkk5/chk_autoobs=1 2006.176.07:31:01.15&checkk5/chk_autoobs=2 2006.176.07:31:01.16&checkk5/chk_autoobs=3 2006.176.07:31:01.16&checkk5/chk_autoobs=4 2006.176.07:31:01.16&checkk5/chk_obsdata=1 2006.176.07:31:01.16&checkk5/chk_obsdata=2 2006.176.07:31:01.16&checkk5/chk_obsdata=3 2006.176.07:31:01.16&checkk5/chk_obsdata=4 2006.176.07:31:01.16&checkk5/k5log=1 2006.176.07:31:01.16&checkk5/k5log=2 2006.176.07:31:01.16&checkk5/k5log=3 2006.176.07:31:01.16&checkk5/k5log=4 2006.176.07:31:01.16&checkk5/obsinfo 2006.176.07:31:01.56/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:31:01.96/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:31:02.34/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:31:02.73/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:31:03.10/chk_obsdata//k5ts1/T1760730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:31:03.48/chk_obsdata//k5ts2/T1760730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:31:03.85/chk_obsdata//k5ts3/T1760730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:31:04.22/chk_obsdata//k5ts4/T1760730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:31:04.93/k5log//k5ts1_log_newline 2006.176.07:31:05.62/k5log//k5ts2_log_newline 2006.176.07:31:06.31/k5log//k5ts3_log_newline 2006.176.07:31:07.00/k5log//k5ts4_log_newline 2006.176.07:31:07.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:31:07.02:4f8m12a=1 2006.176.07:31:07.02$4f8m12a/echo=on 2006.176.07:31:07.02$4f8m12a/pcalon 2006.176.07:31:07.02$pcalon/"no phase cal control is implemented here 2006.176.07:31:07.02$4f8m12a/"tpicd=stop 2006.176.07:31:07.02$4f8m12a/vc4f8 2006.176.07:31:07.02$vc4f8/valo=1,532.99 2006.176.07:31:07.03#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.07:31:07.03#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.07:31:07.03#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:07.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:07.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:07.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:07.03#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:31:07.03#ibcon#first serial, iclass 20, count 0 2006.176.07:31:07.03#ibcon#enter sib2, iclass 20, count 0 2006.176.07:31:07.03#ibcon#flushed, iclass 20, count 0 2006.176.07:31:07.03#ibcon#about to write, iclass 20, count 0 2006.176.07:31:07.03#ibcon#wrote, iclass 20, count 0 2006.176.07:31:07.03#ibcon#about to read 3, iclass 20, count 0 2006.176.07:31:07.07#ibcon#read 3, iclass 20, count 0 2006.176.07:31:07.07#ibcon#about to read 4, iclass 20, count 0 2006.176.07:31:07.07#ibcon#read 4, iclass 20, count 0 2006.176.07:31:07.07#ibcon#about to read 5, iclass 20, count 0 2006.176.07:31:07.07#ibcon#read 5, iclass 20, count 0 2006.176.07:31:07.07#ibcon#about to read 6, iclass 20, count 0 2006.176.07:31:07.07#ibcon#read 6, iclass 20, count 0 2006.176.07:31:07.07#ibcon#end of sib2, iclass 20, count 0 2006.176.07:31:07.07#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:31:07.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:31:07.07#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:31:07.07#ibcon#*before write, iclass 20, count 0 2006.176.07:31:07.07#ibcon#enter sib2, iclass 20, count 0 2006.176.07:31:07.07#ibcon#flushed, iclass 20, count 0 2006.176.07:31:07.07#ibcon#about to write, iclass 20, count 0 2006.176.07:31:07.07#ibcon#wrote, iclass 20, count 0 2006.176.07:31:07.07#ibcon#about to read 3, iclass 20, count 0 2006.176.07:31:07.11#ibcon#read 3, iclass 20, count 0 2006.176.07:31:07.11#ibcon#about to read 4, iclass 20, count 0 2006.176.07:31:07.11#ibcon#read 4, iclass 20, count 0 2006.176.07:31:07.11#ibcon#about to read 5, iclass 20, count 0 2006.176.07:31:07.11#ibcon#read 5, iclass 20, count 0 2006.176.07:31:07.11#ibcon#about to read 6, iclass 20, count 0 2006.176.07:31:07.11#ibcon#read 6, iclass 20, count 0 2006.176.07:31:07.11#ibcon#end of sib2, iclass 20, count 0 2006.176.07:31:07.11#ibcon#*after write, iclass 20, count 0 2006.176.07:31:07.11#ibcon#*before return 0, iclass 20, count 0 2006.176.07:31:07.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:07.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:07.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:31:07.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:31:07.11$vc4f8/va=1,8 2006.176.07:31:07.11#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.07:31:07.11#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.07:31:07.11#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:07.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:07.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:07.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:07.11#ibcon#enter wrdev, iclass 22, count 2 2006.176.07:31:07.11#ibcon#first serial, iclass 22, count 2 2006.176.07:31:07.11#ibcon#enter sib2, iclass 22, count 2 2006.176.07:31:07.11#ibcon#flushed, iclass 22, count 2 2006.176.07:31:07.11#ibcon#about to write, iclass 22, count 2 2006.176.07:31:07.11#ibcon#wrote, iclass 22, count 2 2006.176.07:31:07.11#ibcon#about to read 3, iclass 22, count 2 2006.176.07:31:07.13#ibcon#read 3, iclass 22, count 2 2006.176.07:31:07.13#ibcon#about to read 4, iclass 22, count 2 2006.176.07:31:07.13#ibcon#read 4, iclass 22, count 2 2006.176.07:31:07.13#ibcon#about to read 5, iclass 22, count 2 2006.176.07:31:07.13#ibcon#read 5, iclass 22, count 2 2006.176.07:31:07.13#ibcon#about to read 6, iclass 22, count 2 2006.176.07:31:07.13#ibcon#read 6, iclass 22, count 2 2006.176.07:31:07.13#ibcon#end of sib2, iclass 22, count 2 2006.176.07:31:07.13#ibcon#*mode == 0, iclass 22, count 2 2006.176.07:31:07.13#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.07:31:07.13#ibcon#[25=AT01-08\r\n] 2006.176.07:31:07.13#ibcon#*before write, iclass 22, count 2 2006.176.07:31:07.13#ibcon#enter sib2, iclass 22, count 2 2006.176.07:31:07.13#ibcon#flushed, iclass 22, count 2 2006.176.07:31:07.13#ibcon#about to write, iclass 22, count 2 2006.176.07:31:07.13#ibcon#wrote, iclass 22, count 2 2006.176.07:31:07.13#ibcon#about to read 3, iclass 22, count 2 2006.176.07:31:07.17#ibcon#read 3, iclass 22, count 2 2006.176.07:31:07.17#ibcon#about to read 4, iclass 22, count 2 2006.176.07:31:07.17#ibcon#read 4, iclass 22, count 2 2006.176.07:31:07.17#ibcon#about to read 5, iclass 22, count 2 2006.176.07:31:07.17#ibcon#read 5, iclass 22, count 2 2006.176.07:31:07.17#ibcon#about to read 6, iclass 22, count 2 2006.176.07:31:07.17#ibcon#read 6, iclass 22, count 2 2006.176.07:31:07.17#ibcon#end of sib2, iclass 22, count 2 2006.176.07:31:07.17#ibcon#*after write, iclass 22, count 2 2006.176.07:31:07.17#ibcon#*before return 0, iclass 22, count 2 2006.176.07:31:07.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:07.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:07.17#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.07:31:07.17#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:07.17#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:07.28#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:07.28#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:07.28#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:31:07.28#ibcon#first serial, iclass 22, count 0 2006.176.07:31:07.28#ibcon#enter sib2, iclass 22, count 0 2006.176.07:31:07.28#ibcon#flushed, iclass 22, count 0 2006.176.07:31:07.28#ibcon#about to write, iclass 22, count 0 2006.176.07:31:07.28#ibcon#wrote, iclass 22, count 0 2006.176.07:31:07.28#ibcon#about to read 3, iclass 22, count 0 2006.176.07:31:07.30#ibcon#read 3, iclass 22, count 0 2006.176.07:31:07.30#ibcon#about to read 4, iclass 22, count 0 2006.176.07:31:07.30#ibcon#read 4, iclass 22, count 0 2006.176.07:31:07.30#ibcon#about to read 5, iclass 22, count 0 2006.176.07:31:07.30#ibcon#read 5, iclass 22, count 0 2006.176.07:31:07.30#ibcon#about to read 6, iclass 22, count 0 2006.176.07:31:07.30#ibcon#read 6, iclass 22, count 0 2006.176.07:31:07.30#ibcon#end of sib2, iclass 22, count 0 2006.176.07:31:07.30#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:31:07.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:31:07.30#ibcon#[25=USB\r\n] 2006.176.07:31:07.30#ibcon#*before write, iclass 22, count 0 2006.176.07:31:07.30#ibcon#enter sib2, iclass 22, count 0 2006.176.07:31:07.30#ibcon#flushed, iclass 22, count 0 2006.176.07:31:07.30#ibcon#about to write, iclass 22, count 0 2006.176.07:31:07.30#ibcon#wrote, iclass 22, count 0 2006.176.07:31:07.30#ibcon#about to read 3, iclass 22, count 0 2006.176.07:31:07.33#ibcon#read 3, iclass 22, count 0 2006.176.07:31:07.33#ibcon#about to read 4, iclass 22, count 0 2006.176.07:31:07.33#ibcon#read 4, iclass 22, count 0 2006.176.07:31:07.33#ibcon#about to read 5, iclass 22, count 0 2006.176.07:31:07.33#ibcon#read 5, iclass 22, count 0 2006.176.07:31:07.33#ibcon#about to read 6, iclass 22, count 0 2006.176.07:31:07.33#ibcon#read 6, iclass 22, count 0 2006.176.07:31:07.33#ibcon#end of sib2, iclass 22, count 0 2006.176.07:31:07.33#ibcon#*after write, iclass 22, count 0 2006.176.07:31:07.33#ibcon#*before return 0, iclass 22, count 0 2006.176.07:31:07.33#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:07.33#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:07.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:31:07.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:31:07.33$vc4f8/valo=2,572.99 2006.176.07:31:07.33#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.07:31:07.33#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.07:31:07.33#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:07.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:07.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:07.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:07.33#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:31:07.33#ibcon#first serial, iclass 24, count 0 2006.176.07:31:07.33#ibcon#enter sib2, iclass 24, count 0 2006.176.07:31:07.33#ibcon#flushed, iclass 24, count 0 2006.176.07:31:07.33#ibcon#about to write, iclass 24, count 0 2006.176.07:31:07.33#ibcon#wrote, iclass 24, count 0 2006.176.07:31:07.33#ibcon#about to read 3, iclass 24, count 0 2006.176.07:31:07.35#ibcon#read 3, iclass 24, count 0 2006.176.07:31:07.35#ibcon#about to read 4, iclass 24, count 0 2006.176.07:31:07.35#ibcon#read 4, iclass 24, count 0 2006.176.07:31:07.35#ibcon#about to read 5, iclass 24, count 0 2006.176.07:31:07.35#ibcon#read 5, iclass 24, count 0 2006.176.07:31:07.35#ibcon#about to read 6, iclass 24, count 0 2006.176.07:31:07.35#ibcon#read 6, iclass 24, count 0 2006.176.07:31:07.35#ibcon#end of sib2, iclass 24, count 0 2006.176.07:31:07.35#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:31:07.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:31:07.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:31:07.35#ibcon#*before write, iclass 24, count 0 2006.176.07:31:07.35#ibcon#enter sib2, iclass 24, count 0 2006.176.07:31:07.35#ibcon#flushed, iclass 24, count 0 2006.176.07:31:07.35#ibcon#about to write, iclass 24, count 0 2006.176.07:31:07.35#ibcon#wrote, iclass 24, count 0 2006.176.07:31:07.35#ibcon#about to read 3, iclass 24, count 0 2006.176.07:31:07.39#ibcon#read 3, iclass 24, count 0 2006.176.07:31:07.39#ibcon#about to read 4, iclass 24, count 0 2006.176.07:31:07.39#ibcon#read 4, iclass 24, count 0 2006.176.07:31:07.39#ibcon#about to read 5, iclass 24, count 0 2006.176.07:31:07.39#ibcon#read 5, iclass 24, count 0 2006.176.07:31:07.39#ibcon#about to read 6, iclass 24, count 0 2006.176.07:31:07.39#ibcon#read 6, iclass 24, count 0 2006.176.07:31:07.39#ibcon#end of sib2, iclass 24, count 0 2006.176.07:31:07.39#ibcon#*after write, iclass 24, count 0 2006.176.07:31:07.39#ibcon#*before return 0, iclass 24, count 0 2006.176.07:31:07.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:07.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:07.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:31:07.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:31:07.39$vc4f8/va=2,7 2006.176.07:31:07.39#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.07:31:07.39#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.07:31:07.39#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:07.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:07.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:07.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:07.45#ibcon#enter wrdev, iclass 26, count 2 2006.176.07:31:07.45#ibcon#first serial, iclass 26, count 2 2006.176.07:31:07.45#ibcon#enter sib2, iclass 26, count 2 2006.176.07:31:07.45#ibcon#flushed, iclass 26, count 2 2006.176.07:31:07.45#ibcon#about to write, iclass 26, count 2 2006.176.07:31:07.45#ibcon#wrote, iclass 26, count 2 2006.176.07:31:07.45#ibcon#about to read 3, iclass 26, count 2 2006.176.07:31:07.48#ibcon#read 3, iclass 26, count 2 2006.176.07:31:07.48#ibcon#about to read 4, iclass 26, count 2 2006.176.07:31:07.48#ibcon#read 4, iclass 26, count 2 2006.176.07:31:07.48#ibcon#about to read 5, iclass 26, count 2 2006.176.07:31:07.48#ibcon#read 5, iclass 26, count 2 2006.176.07:31:07.48#ibcon#about to read 6, iclass 26, count 2 2006.176.07:31:07.48#ibcon#read 6, iclass 26, count 2 2006.176.07:31:07.48#ibcon#end of sib2, iclass 26, count 2 2006.176.07:31:07.48#ibcon#*mode == 0, iclass 26, count 2 2006.176.07:31:07.48#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.07:31:07.48#ibcon#[25=AT02-07\r\n] 2006.176.07:31:07.48#ibcon#*before write, iclass 26, count 2 2006.176.07:31:07.48#ibcon#enter sib2, iclass 26, count 2 2006.176.07:31:07.48#ibcon#flushed, iclass 26, count 2 2006.176.07:31:07.48#ibcon#about to write, iclass 26, count 2 2006.176.07:31:07.48#ibcon#wrote, iclass 26, count 2 2006.176.07:31:07.48#ibcon#about to read 3, iclass 26, count 2 2006.176.07:31:07.50#ibcon#read 3, iclass 26, count 2 2006.176.07:31:07.50#ibcon#about to read 4, iclass 26, count 2 2006.176.07:31:07.50#ibcon#read 4, iclass 26, count 2 2006.176.07:31:07.50#ibcon#about to read 5, iclass 26, count 2 2006.176.07:31:07.50#ibcon#read 5, iclass 26, count 2 2006.176.07:31:07.50#ibcon#about to read 6, iclass 26, count 2 2006.176.07:31:07.50#ibcon#read 6, iclass 26, count 2 2006.176.07:31:07.50#ibcon#end of sib2, iclass 26, count 2 2006.176.07:31:07.50#ibcon#*after write, iclass 26, count 2 2006.176.07:31:07.50#ibcon#*before return 0, iclass 26, count 2 2006.176.07:31:07.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:07.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:07.50#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.07:31:07.50#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:07.50#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:07.62#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:07.62#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:07.62#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:31:07.62#ibcon#first serial, iclass 26, count 0 2006.176.07:31:07.62#ibcon#enter sib2, iclass 26, count 0 2006.176.07:31:07.62#ibcon#flushed, iclass 26, count 0 2006.176.07:31:07.62#ibcon#about to write, iclass 26, count 0 2006.176.07:31:07.62#ibcon#wrote, iclass 26, count 0 2006.176.07:31:07.62#ibcon#about to read 3, iclass 26, count 0 2006.176.07:31:07.64#ibcon#read 3, iclass 26, count 0 2006.176.07:31:07.64#ibcon#about to read 4, iclass 26, count 0 2006.176.07:31:07.64#ibcon#read 4, iclass 26, count 0 2006.176.07:31:07.64#ibcon#about to read 5, iclass 26, count 0 2006.176.07:31:07.64#ibcon#read 5, iclass 26, count 0 2006.176.07:31:07.64#ibcon#about to read 6, iclass 26, count 0 2006.176.07:31:07.64#ibcon#read 6, iclass 26, count 0 2006.176.07:31:07.64#ibcon#end of sib2, iclass 26, count 0 2006.176.07:31:07.64#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:31:07.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:31:07.64#ibcon#[25=USB\r\n] 2006.176.07:31:07.64#ibcon#*before write, iclass 26, count 0 2006.176.07:31:07.64#ibcon#enter sib2, iclass 26, count 0 2006.176.07:31:07.64#ibcon#flushed, iclass 26, count 0 2006.176.07:31:07.64#ibcon#about to write, iclass 26, count 0 2006.176.07:31:07.64#ibcon#wrote, iclass 26, count 0 2006.176.07:31:07.64#ibcon#about to read 3, iclass 26, count 0 2006.176.07:31:07.67#ibcon#read 3, iclass 26, count 0 2006.176.07:31:07.67#ibcon#about to read 4, iclass 26, count 0 2006.176.07:31:07.67#ibcon#read 4, iclass 26, count 0 2006.176.07:31:07.67#ibcon#about to read 5, iclass 26, count 0 2006.176.07:31:07.67#ibcon#read 5, iclass 26, count 0 2006.176.07:31:07.67#ibcon#about to read 6, iclass 26, count 0 2006.176.07:31:07.67#ibcon#read 6, iclass 26, count 0 2006.176.07:31:07.67#ibcon#end of sib2, iclass 26, count 0 2006.176.07:31:07.67#ibcon#*after write, iclass 26, count 0 2006.176.07:31:07.67#ibcon#*before return 0, iclass 26, count 0 2006.176.07:31:07.67#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:07.67#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:07.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:31:07.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:31:07.67$vc4f8/valo=3,672.99 2006.176.07:31:07.67#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.07:31:07.67#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.07:31:07.67#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:07.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:07.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:07.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:07.67#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:31:07.67#ibcon#first serial, iclass 28, count 0 2006.176.07:31:07.67#ibcon#enter sib2, iclass 28, count 0 2006.176.07:31:07.67#ibcon#flushed, iclass 28, count 0 2006.176.07:31:07.67#ibcon#about to write, iclass 28, count 0 2006.176.07:31:07.67#ibcon#wrote, iclass 28, count 0 2006.176.07:31:07.67#ibcon#about to read 3, iclass 28, count 0 2006.176.07:31:07.69#ibcon#read 3, iclass 28, count 0 2006.176.07:31:07.69#ibcon#about to read 4, iclass 28, count 0 2006.176.07:31:07.69#ibcon#read 4, iclass 28, count 0 2006.176.07:31:07.69#ibcon#about to read 5, iclass 28, count 0 2006.176.07:31:07.69#ibcon#read 5, iclass 28, count 0 2006.176.07:31:07.69#ibcon#about to read 6, iclass 28, count 0 2006.176.07:31:07.69#ibcon#read 6, iclass 28, count 0 2006.176.07:31:07.69#ibcon#end of sib2, iclass 28, count 0 2006.176.07:31:07.69#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:31:07.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:31:07.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:31:07.69#ibcon#*before write, iclass 28, count 0 2006.176.07:31:07.69#ibcon#enter sib2, iclass 28, count 0 2006.176.07:31:07.69#ibcon#flushed, iclass 28, count 0 2006.176.07:31:07.69#ibcon#about to write, iclass 28, count 0 2006.176.07:31:07.69#ibcon#wrote, iclass 28, count 0 2006.176.07:31:07.69#ibcon#about to read 3, iclass 28, count 0 2006.176.07:31:07.73#ibcon#read 3, iclass 28, count 0 2006.176.07:31:07.73#ibcon#about to read 4, iclass 28, count 0 2006.176.07:31:07.73#ibcon#read 4, iclass 28, count 0 2006.176.07:31:07.73#ibcon#about to read 5, iclass 28, count 0 2006.176.07:31:07.73#ibcon#read 5, iclass 28, count 0 2006.176.07:31:07.73#ibcon#about to read 6, iclass 28, count 0 2006.176.07:31:07.73#ibcon#read 6, iclass 28, count 0 2006.176.07:31:07.73#ibcon#end of sib2, iclass 28, count 0 2006.176.07:31:07.73#ibcon#*after write, iclass 28, count 0 2006.176.07:31:07.73#ibcon#*before return 0, iclass 28, count 0 2006.176.07:31:07.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:07.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:07.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:31:07.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:31:07.73$vc4f8/va=3,6 2006.176.07:31:07.73#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.07:31:07.73#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.07:31:07.73#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:07.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:07.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:07.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:07.79#ibcon#enter wrdev, iclass 30, count 2 2006.176.07:31:07.79#ibcon#first serial, iclass 30, count 2 2006.176.07:31:07.79#ibcon#enter sib2, iclass 30, count 2 2006.176.07:31:07.79#ibcon#flushed, iclass 30, count 2 2006.176.07:31:07.79#ibcon#about to write, iclass 30, count 2 2006.176.07:31:07.79#ibcon#wrote, iclass 30, count 2 2006.176.07:31:07.79#ibcon#about to read 3, iclass 30, count 2 2006.176.07:31:07.82#ibcon#read 3, iclass 30, count 2 2006.176.07:31:07.82#ibcon#about to read 4, iclass 30, count 2 2006.176.07:31:07.82#ibcon#read 4, iclass 30, count 2 2006.176.07:31:07.82#ibcon#about to read 5, iclass 30, count 2 2006.176.07:31:07.82#ibcon#read 5, iclass 30, count 2 2006.176.07:31:07.82#ibcon#about to read 6, iclass 30, count 2 2006.176.07:31:07.82#ibcon#read 6, iclass 30, count 2 2006.176.07:31:07.82#ibcon#end of sib2, iclass 30, count 2 2006.176.07:31:07.82#ibcon#*mode == 0, iclass 30, count 2 2006.176.07:31:07.82#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.07:31:07.82#ibcon#[25=AT03-06\r\n] 2006.176.07:31:07.82#ibcon#*before write, iclass 30, count 2 2006.176.07:31:07.82#ibcon#enter sib2, iclass 30, count 2 2006.176.07:31:07.82#ibcon#flushed, iclass 30, count 2 2006.176.07:31:07.82#ibcon#about to write, iclass 30, count 2 2006.176.07:31:07.82#ibcon#wrote, iclass 30, count 2 2006.176.07:31:07.82#ibcon#about to read 3, iclass 30, count 2 2006.176.07:31:07.84#ibcon#read 3, iclass 30, count 2 2006.176.07:31:07.84#ibcon#about to read 4, iclass 30, count 2 2006.176.07:31:07.84#ibcon#read 4, iclass 30, count 2 2006.176.07:31:07.84#ibcon#about to read 5, iclass 30, count 2 2006.176.07:31:07.84#ibcon#read 5, iclass 30, count 2 2006.176.07:31:07.84#ibcon#about to read 6, iclass 30, count 2 2006.176.07:31:07.84#ibcon#read 6, iclass 30, count 2 2006.176.07:31:07.84#ibcon#end of sib2, iclass 30, count 2 2006.176.07:31:07.84#ibcon#*after write, iclass 30, count 2 2006.176.07:31:07.84#ibcon#*before return 0, iclass 30, count 2 2006.176.07:31:07.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:07.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:07.84#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.07:31:07.84#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:07.84#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:07.96#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:07.96#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:07.96#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:31:07.96#ibcon#first serial, iclass 30, count 0 2006.176.07:31:07.96#ibcon#enter sib2, iclass 30, count 0 2006.176.07:31:07.96#ibcon#flushed, iclass 30, count 0 2006.176.07:31:07.96#ibcon#about to write, iclass 30, count 0 2006.176.07:31:07.96#ibcon#wrote, iclass 30, count 0 2006.176.07:31:07.96#ibcon#about to read 3, iclass 30, count 0 2006.176.07:31:07.98#ibcon#read 3, iclass 30, count 0 2006.176.07:31:07.98#ibcon#about to read 4, iclass 30, count 0 2006.176.07:31:07.98#ibcon#read 4, iclass 30, count 0 2006.176.07:31:07.98#ibcon#about to read 5, iclass 30, count 0 2006.176.07:31:07.98#ibcon#read 5, iclass 30, count 0 2006.176.07:31:07.98#ibcon#about to read 6, iclass 30, count 0 2006.176.07:31:07.98#ibcon#read 6, iclass 30, count 0 2006.176.07:31:07.98#ibcon#end of sib2, iclass 30, count 0 2006.176.07:31:07.98#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:31:07.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:31:07.98#ibcon#[25=USB\r\n] 2006.176.07:31:07.98#ibcon#*before write, iclass 30, count 0 2006.176.07:31:07.98#ibcon#enter sib2, iclass 30, count 0 2006.176.07:31:07.98#ibcon#flushed, iclass 30, count 0 2006.176.07:31:07.98#ibcon#about to write, iclass 30, count 0 2006.176.07:31:07.98#ibcon#wrote, iclass 30, count 0 2006.176.07:31:07.98#ibcon#about to read 3, iclass 30, count 0 2006.176.07:31:08.01#ibcon#read 3, iclass 30, count 0 2006.176.07:31:08.01#ibcon#about to read 4, iclass 30, count 0 2006.176.07:31:08.01#ibcon#read 4, iclass 30, count 0 2006.176.07:31:08.01#ibcon#about to read 5, iclass 30, count 0 2006.176.07:31:08.01#ibcon#read 5, iclass 30, count 0 2006.176.07:31:08.01#ibcon#about to read 6, iclass 30, count 0 2006.176.07:31:08.01#ibcon#read 6, iclass 30, count 0 2006.176.07:31:08.01#ibcon#end of sib2, iclass 30, count 0 2006.176.07:31:08.01#ibcon#*after write, iclass 30, count 0 2006.176.07:31:08.01#ibcon#*before return 0, iclass 30, count 0 2006.176.07:31:08.01#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:08.01#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:08.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:31:08.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:31:08.01$vc4f8/valo=4,832.99 2006.176.07:31:08.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.07:31:08.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.07:31:08.01#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:08.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:08.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:08.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:08.01#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:31:08.01#ibcon#first serial, iclass 32, count 0 2006.176.07:31:08.01#ibcon#enter sib2, iclass 32, count 0 2006.176.07:31:08.01#ibcon#flushed, iclass 32, count 0 2006.176.07:31:08.01#ibcon#about to write, iclass 32, count 0 2006.176.07:31:08.01#ibcon#wrote, iclass 32, count 0 2006.176.07:31:08.01#ibcon#about to read 3, iclass 32, count 0 2006.176.07:31:08.03#ibcon#read 3, iclass 32, count 0 2006.176.07:31:08.03#ibcon#about to read 4, iclass 32, count 0 2006.176.07:31:08.03#ibcon#read 4, iclass 32, count 0 2006.176.07:31:08.03#ibcon#about to read 5, iclass 32, count 0 2006.176.07:31:08.03#ibcon#read 5, iclass 32, count 0 2006.176.07:31:08.03#ibcon#about to read 6, iclass 32, count 0 2006.176.07:31:08.03#ibcon#read 6, iclass 32, count 0 2006.176.07:31:08.03#ibcon#end of sib2, iclass 32, count 0 2006.176.07:31:08.03#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:31:08.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:31:08.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:31:08.03#ibcon#*before write, iclass 32, count 0 2006.176.07:31:08.03#ibcon#enter sib2, iclass 32, count 0 2006.176.07:31:08.03#ibcon#flushed, iclass 32, count 0 2006.176.07:31:08.03#ibcon#about to write, iclass 32, count 0 2006.176.07:31:08.03#ibcon#wrote, iclass 32, count 0 2006.176.07:31:08.03#ibcon#about to read 3, iclass 32, count 0 2006.176.07:31:08.07#ibcon#read 3, iclass 32, count 0 2006.176.07:31:08.07#ibcon#about to read 4, iclass 32, count 0 2006.176.07:31:08.07#ibcon#read 4, iclass 32, count 0 2006.176.07:31:08.07#ibcon#about to read 5, iclass 32, count 0 2006.176.07:31:08.07#ibcon#read 5, iclass 32, count 0 2006.176.07:31:08.07#ibcon#about to read 6, iclass 32, count 0 2006.176.07:31:08.07#ibcon#read 6, iclass 32, count 0 2006.176.07:31:08.07#ibcon#end of sib2, iclass 32, count 0 2006.176.07:31:08.07#ibcon#*after write, iclass 32, count 0 2006.176.07:31:08.07#ibcon#*before return 0, iclass 32, count 0 2006.176.07:31:08.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:08.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:08.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:31:08.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:31:08.07$vc4f8/va=4,7 2006.176.07:31:08.07#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.07:31:08.07#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.07:31:08.07#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:08.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:08.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:08.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:08.13#ibcon#enter wrdev, iclass 34, count 2 2006.176.07:31:08.13#ibcon#first serial, iclass 34, count 2 2006.176.07:31:08.13#ibcon#enter sib2, iclass 34, count 2 2006.176.07:31:08.13#ibcon#flushed, iclass 34, count 2 2006.176.07:31:08.13#ibcon#about to write, iclass 34, count 2 2006.176.07:31:08.13#ibcon#wrote, iclass 34, count 2 2006.176.07:31:08.13#ibcon#about to read 3, iclass 34, count 2 2006.176.07:31:08.15#ibcon#read 3, iclass 34, count 2 2006.176.07:31:08.15#ibcon#about to read 4, iclass 34, count 2 2006.176.07:31:08.15#ibcon#read 4, iclass 34, count 2 2006.176.07:31:08.15#ibcon#about to read 5, iclass 34, count 2 2006.176.07:31:08.15#ibcon#read 5, iclass 34, count 2 2006.176.07:31:08.15#ibcon#about to read 6, iclass 34, count 2 2006.176.07:31:08.15#ibcon#read 6, iclass 34, count 2 2006.176.07:31:08.15#ibcon#end of sib2, iclass 34, count 2 2006.176.07:31:08.15#ibcon#*mode == 0, iclass 34, count 2 2006.176.07:31:08.15#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.07:31:08.15#ibcon#[25=AT04-07\r\n] 2006.176.07:31:08.15#ibcon#*before write, iclass 34, count 2 2006.176.07:31:08.15#ibcon#enter sib2, iclass 34, count 2 2006.176.07:31:08.15#ibcon#flushed, iclass 34, count 2 2006.176.07:31:08.15#ibcon#about to write, iclass 34, count 2 2006.176.07:31:08.15#ibcon#wrote, iclass 34, count 2 2006.176.07:31:08.15#ibcon#about to read 3, iclass 34, count 2 2006.176.07:31:08.18#ibcon#read 3, iclass 34, count 2 2006.176.07:31:08.18#ibcon#about to read 4, iclass 34, count 2 2006.176.07:31:08.18#ibcon#read 4, iclass 34, count 2 2006.176.07:31:08.18#ibcon#about to read 5, iclass 34, count 2 2006.176.07:31:08.18#ibcon#read 5, iclass 34, count 2 2006.176.07:31:08.18#ibcon#about to read 6, iclass 34, count 2 2006.176.07:31:08.18#ibcon#read 6, iclass 34, count 2 2006.176.07:31:08.18#ibcon#end of sib2, iclass 34, count 2 2006.176.07:31:08.18#ibcon#*after write, iclass 34, count 2 2006.176.07:31:08.18#ibcon#*before return 0, iclass 34, count 2 2006.176.07:31:08.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:08.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:08.18#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.07:31:08.18#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:08.18#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:08.30#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:08.30#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:08.30#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:31:08.30#ibcon#first serial, iclass 34, count 0 2006.176.07:31:08.30#ibcon#enter sib2, iclass 34, count 0 2006.176.07:31:08.30#ibcon#flushed, iclass 34, count 0 2006.176.07:31:08.30#ibcon#about to write, iclass 34, count 0 2006.176.07:31:08.30#ibcon#wrote, iclass 34, count 0 2006.176.07:31:08.30#ibcon#about to read 3, iclass 34, count 0 2006.176.07:31:08.32#ibcon#read 3, iclass 34, count 0 2006.176.07:31:08.32#ibcon#about to read 4, iclass 34, count 0 2006.176.07:31:08.32#ibcon#read 4, iclass 34, count 0 2006.176.07:31:08.32#ibcon#about to read 5, iclass 34, count 0 2006.176.07:31:08.32#ibcon#read 5, iclass 34, count 0 2006.176.07:31:08.32#ibcon#about to read 6, iclass 34, count 0 2006.176.07:31:08.32#ibcon#read 6, iclass 34, count 0 2006.176.07:31:08.32#ibcon#end of sib2, iclass 34, count 0 2006.176.07:31:08.32#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:31:08.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:31:08.32#ibcon#[25=USB\r\n] 2006.176.07:31:08.32#ibcon#*before write, iclass 34, count 0 2006.176.07:31:08.32#ibcon#enter sib2, iclass 34, count 0 2006.176.07:31:08.32#ibcon#flushed, iclass 34, count 0 2006.176.07:31:08.32#ibcon#about to write, iclass 34, count 0 2006.176.07:31:08.32#ibcon#wrote, iclass 34, count 0 2006.176.07:31:08.32#ibcon#about to read 3, iclass 34, count 0 2006.176.07:31:08.35#ibcon#read 3, iclass 34, count 0 2006.176.07:31:08.35#ibcon#about to read 4, iclass 34, count 0 2006.176.07:31:08.35#ibcon#read 4, iclass 34, count 0 2006.176.07:31:08.35#ibcon#about to read 5, iclass 34, count 0 2006.176.07:31:08.35#ibcon#read 5, iclass 34, count 0 2006.176.07:31:08.35#ibcon#about to read 6, iclass 34, count 0 2006.176.07:31:08.35#ibcon#read 6, iclass 34, count 0 2006.176.07:31:08.35#ibcon#end of sib2, iclass 34, count 0 2006.176.07:31:08.35#ibcon#*after write, iclass 34, count 0 2006.176.07:31:08.35#ibcon#*before return 0, iclass 34, count 0 2006.176.07:31:08.35#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:08.35#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:08.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:31:08.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:31:08.35$vc4f8/valo=5,652.99 2006.176.07:31:08.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.07:31:08.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.07:31:08.35#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:08.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:08.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:08.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:08.35#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:31:08.35#ibcon#first serial, iclass 36, count 0 2006.176.07:31:08.35#ibcon#enter sib2, iclass 36, count 0 2006.176.07:31:08.35#ibcon#flushed, iclass 36, count 0 2006.176.07:31:08.35#ibcon#about to write, iclass 36, count 0 2006.176.07:31:08.35#ibcon#wrote, iclass 36, count 0 2006.176.07:31:08.35#ibcon#about to read 3, iclass 36, count 0 2006.176.07:31:08.37#ibcon#read 3, iclass 36, count 0 2006.176.07:31:08.37#ibcon#about to read 4, iclass 36, count 0 2006.176.07:31:08.37#ibcon#read 4, iclass 36, count 0 2006.176.07:31:08.37#ibcon#about to read 5, iclass 36, count 0 2006.176.07:31:08.37#ibcon#read 5, iclass 36, count 0 2006.176.07:31:08.37#ibcon#about to read 6, iclass 36, count 0 2006.176.07:31:08.37#ibcon#read 6, iclass 36, count 0 2006.176.07:31:08.37#ibcon#end of sib2, iclass 36, count 0 2006.176.07:31:08.37#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:31:08.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:31:08.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:31:08.37#ibcon#*before write, iclass 36, count 0 2006.176.07:31:08.37#ibcon#enter sib2, iclass 36, count 0 2006.176.07:31:08.37#ibcon#flushed, iclass 36, count 0 2006.176.07:31:08.37#ibcon#about to write, iclass 36, count 0 2006.176.07:31:08.37#ibcon#wrote, iclass 36, count 0 2006.176.07:31:08.37#ibcon#about to read 3, iclass 36, count 0 2006.176.07:31:08.41#ibcon#read 3, iclass 36, count 0 2006.176.07:31:08.41#ibcon#about to read 4, iclass 36, count 0 2006.176.07:31:08.41#ibcon#read 4, iclass 36, count 0 2006.176.07:31:08.41#ibcon#about to read 5, iclass 36, count 0 2006.176.07:31:08.41#ibcon#read 5, iclass 36, count 0 2006.176.07:31:08.41#ibcon#about to read 6, iclass 36, count 0 2006.176.07:31:08.41#ibcon#read 6, iclass 36, count 0 2006.176.07:31:08.41#ibcon#end of sib2, iclass 36, count 0 2006.176.07:31:08.41#ibcon#*after write, iclass 36, count 0 2006.176.07:31:08.41#ibcon#*before return 0, iclass 36, count 0 2006.176.07:31:08.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:08.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:08.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:31:08.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:31:08.41$vc4f8/va=5,7 2006.176.07:31:08.41#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.07:31:08.41#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.07:31:08.41#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:08.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:08.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:08.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:08.47#ibcon#enter wrdev, iclass 38, count 2 2006.176.07:31:08.47#ibcon#first serial, iclass 38, count 2 2006.176.07:31:08.47#ibcon#enter sib2, iclass 38, count 2 2006.176.07:31:08.47#ibcon#flushed, iclass 38, count 2 2006.176.07:31:08.47#ibcon#about to write, iclass 38, count 2 2006.176.07:31:08.47#ibcon#wrote, iclass 38, count 2 2006.176.07:31:08.47#ibcon#about to read 3, iclass 38, count 2 2006.176.07:31:08.49#ibcon#read 3, iclass 38, count 2 2006.176.07:31:08.49#ibcon#about to read 4, iclass 38, count 2 2006.176.07:31:08.49#ibcon#read 4, iclass 38, count 2 2006.176.07:31:08.49#ibcon#about to read 5, iclass 38, count 2 2006.176.07:31:08.49#ibcon#read 5, iclass 38, count 2 2006.176.07:31:08.49#ibcon#about to read 6, iclass 38, count 2 2006.176.07:31:08.49#ibcon#read 6, iclass 38, count 2 2006.176.07:31:08.49#ibcon#end of sib2, iclass 38, count 2 2006.176.07:31:08.49#ibcon#*mode == 0, iclass 38, count 2 2006.176.07:31:08.49#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.07:31:08.49#ibcon#[25=AT05-07\r\n] 2006.176.07:31:08.49#ibcon#*before write, iclass 38, count 2 2006.176.07:31:08.49#ibcon#enter sib2, iclass 38, count 2 2006.176.07:31:08.49#ibcon#flushed, iclass 38, count 2 2006.176.07:31:08.49#ibcon#about to write, iclass 38, count 2 2006.176.07:31:08.49#ibcon#wrote, iclass 38, count 2 2006.176.07:31:08.49#ibcon#about to read 3, iclass 38, count 2 2006.176.07:31:08.52#ibcon#read 3, iclass 38, count 2 2006.176.07:31:08.52#ibcon#about to read 4, iclass 38, count 2 2006.176.07:31:08.52#ibcon#read 4, iclass 38, count 2 2006.176.07:31:08.52#ibcon#about to read 5, iclass 38, count 2 2006.176.07:31:08.52#ibcon#read 5, iclass 38, count 2 2006.176.07:31:08.52#ibcon#about to read 6, iclass 38, count 2 2006.176.07:31:08.52#ibcon#read 6, iclass 38, count 2 2006.176.07:31:08.52#ibcon#end of sib2, iclass 38, count 2 2006.176.07:31:08.52#ibcon#*after write, iclass 38, count 2 2006.176.07:31:08.52#ibcon#*before return 0, iclass 38, count 2 2006.176.07:31:08.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:08.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:08.52#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.07:31:08.52#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:08.52#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:08.64#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:08.64#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:08.64#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:31:08.64#ibcon#first serial, iclass 38, count 0 2006.176.07:31:08.64#ibcon#enter sib2, iclass 38, count 0 2006.176.07:31:08.64#ibcon#flushed, iclass 38, count 0 2006.176.07:31:08.64#ibcon#about to write, iclass 38, count 0 2006.176.07:31:08.64#ibcon#wrote, iclass 38, count 0 2006.176.07:31:08.64#ibcon#about to read 3, iclass 38, count 0 2006.176.07:31:08.66#ibcon#read 3, iclass 38, count 0 2006.176.07:31:08.66#ibcon#about to read 4, iclass 38, count 0 2006.176.07:31:08.66#ibcon#read 4, iclass 38, count 0 2006.176.07:31:08.66#ibcon#about to read 5, iclass 38, count 0 2006.176.07:31:08.66#ibcon#read 5, iclass 38, count 0 2006.176.07:31:08.66#ibcon#about to read 6, iclass 38, count 0 2006.176.07:31:08.66#ibcon#read 6, iclass 38, count 0 2006.176.07:31:08.66#ibcon#end of sib2, iclass 38, count 0 2006.176.07:31:08.66#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:31:08.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:31:08.66#ibcon#[25=USB\r\n] 2006.176.07:31:08.66#ibcon#*before write, iclass 38, count 0 2006.176.07:31:08.66#ibcon#enter sib2, iclass 38, count 0 2006.176.07:31:08.66#ibcon#flushed, iclass 38, count 0 2006.176.07:31:08.66#ibcon#about to write, iclass 38, count 0 2006.176.07:31:08.66#ibcon#wrote, iclass 38, count 0 2006.176.07:31:08.66#ibcon#about to read 3, iclass 38, count 0 2006.176.07:31:08.69#ibcon#read 3, iclass 38, count 0 2006.176.07:31:08.69#ibcon#about to read 4, iclass 38, count 0 2006.176.07:31:08.69#ibcon#read 4, iclass 38, count 0 2006.176.07:31:08.69#ibcon#about to read 5, iclass 38, count 0 2006.176.07:31:08.69#ibcon#read 5, iclass 38, count 0 2006.176.07:31:08.69#ibcon#about to read 6, iclass 38, count 0 2006.176.07:31:08.69#ibcon#read 6, iclass 38, count 0 2006.176.07:31:08.69#ibcon#end of sib2, iclass 38, count 0 2006.176.07:31:08.69#ibcon#*after write, iclass 38, count 0 2006.176.07:31:08.69#ibcon#*before return 0, iclass 38, count 0 2006.176.07:31:08.69#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:08.69#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:08.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:31:08.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:31:08.69$vc4f8/valo=6,772.99 2006.176.07:31:08.69#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.07:31:08.69#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.07:31:08.69#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:08.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:31:08.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:31:08.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:31:08.69#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:31:08.69#ibcon#first serial, iclass 40, count 0 2006.176.07:31:08.69#ibcon#enter sib2, iclass 40, count 0 2006.176.07:31:08.69#ibcon#flushed, iclass 40, count 0 2006.176.07:31:08.69#ibcon#about to write, iclass 40, count 0 2006.176.07:31:08.69#ibcon#wrote, iclass 40, count 0 2006.176.07:31:08.69#ibcon#about to read 3, iclass 40, count 0 2006.176.07:31:08.71#ibcon#read 3, iclass 40, count 0 2006.176.07:31:08.71#ibcon#about to read 4, iclass 40, count 0 2006.176.07:31:08.71#ibcon#read 4, iclass 40, count 0 2006.176.07:31:08.71#ibcon#about to read 5, iclass 40, count 0 2006.176.07:31:08.71#ibcon#read 5, iclass 40, count 0 2006.176.07:31:08.71#ibcon#about to read 6, iclass 40, count 0 2006.176.07:31:08.71#ibcon#read 6, iclass 40, count 0 2006.176.07:31:08.71#ibcon#end of sib2, iclass 40, count 0 2006.176.07:31:08.71#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:31:08.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:31:08.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:31:08.71#ibcon#*before write, iclass 40, count 0 2006.176.07:31:08.71#ibcon#enter sib2, iclass 40, count 0 2006.176.07:31:08.71#ibcon#flushed, iclass 40, count 0 2006.176.07:31:08.71#ibcon#about to write, iclass 40, count 0 2006.176.07:31:08.71#ibcon#wrote, iclass 40, count 0 2006.176.07:31:08.71#ibcon#about to read 3, iclass 40, count 0 2006.176.07:31:08.75#ibcon#read 3, iclass 40, count 0 2006.176.07:31:08.75#ibcon#about to read 4, iclass 40, count 0 2006.176.07:31:08.75#ibcon#read 4, iclass 40, count 0 2006.176.07:31:08.75#ibcon#about to read 5, iclass 40, count 0 2006.176.07:31:08.75#ibcon#read 5, iclass 40, count 0 2006.176.07:31:08.75#ibcon#about to read 6, iclass 40, count 0 2006.176.07:31:08.75#ibcon#read 6, iclass 40, count 0 2006.176.07:31:08.75#ibcon#end of sib2, iclass 40, count 0 2006.176.07:31:08.75#ibcon#*after write, iclass 40, count 0 2006.176.07:31:08.75#ibcon#*before return 0, iclass 40, count 0 2006.176.07:31:08.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:31:08.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:31:08.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:31:08.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:31:08.75$vc4f8/va=6,6 2006.176.07:31:08.75#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.07:31:08.75#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.07:31:08.75#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:08.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:31:08.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:31:08.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:31:08.81#ibcon#enter wrdev, iclass 4, count 2 2006.176.07:31:08.81#ibcon#first serial, iclass 4, count 2 2006.176.07:31:08.81#ibcon#enter sib2, iclass 4, count 2 2006.176.07:31:08.81#ibcon#flushed, iclass 4, count 2 2006.176.07:31:08.81#ibcon#about to write, iclass 4, count 2 2006.176.07:31:08.81#ibcon#wrote, iclass 4, count 2 2006.176.07:31:08.81#ibcon#about to read 3, iclass 4, count 2 2006.176.07:31:08.83#ibcon#read 3, iclass 4, count 2 2006.176.07:31:08.83#ibcon#about to read 4, iclass 4, count 2 2006.176.07:31:08.83#ibcon#read 4, iclass 4, count 2 2006.176.07:31:08.83#ibcon#about to read 5, iclass 4, count 2 2006.176.07:31:08.83#ibcon#read 5, iclass 4, count 2 2006.176.07:31:08.83#ibcon#about to read 6, iclass 4, count 2 2006.176.07:31:08.83#ibcon#read 6, iclass 4, count 2 2006.176.07:31:08.83#ibcon#end of sib2, iclass 4, count 2 2006.176.07:31:08.83#ibcon#*mode == 0, iclass 4, count 2 2006.176.07:31:08.83#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.07:31:08.83#ibcon#[25=AT06-06\r\n] 2006.176.07:31:08.83#ibcon#*before write, iclass 4, count 2 2006.176.07:31:08.83#ibcon#enter sib2, iclass 4, count 2 2006.176.07:31:08.83#ibcon#flushed, iclass 4, count 2 2006.176.07:31:08.83#ibcon#about to write, iclass 4, count 2 2006.176.07:31:08.83#ibcon#wrote, iclass 4, count 2 2006.176.07:31:08.83#ibcon#about to read 3, iclass 4, count 2 2006.176.07:31:08.86#ibcon#read 3, iclass 4, count 2 2006.176.07:31:08.86#ibcon#about to read 4, iclass 4, count 2 2006.176.07:31:08.86#ibcon#read 4, iclass 4, count 2 2006.176.07:31:08.86#ibcon#about to read 5, iclass 4, count 2 2006.176.07:31:08.86#ibcon#read 5, iclass 4, count 2 2006.176.07:31:08.86#ibcon#about to read 6, iclass 4, count 2 2006.176.07:31:08.86#ibcon#read 6, iclass 4, count 2 2006.176.07:31:08.86#ibcon#end of sib2, iclass 4, count 2 2006.176.07:31:08.86#ibcon#*after write, iclass 4, count 2 2006.176.07:31:08.86#ibcon#*before return 0, iclass 4, count 2 2006.176.07:31:08.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:31:08.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:31:08.86#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.07:31:08.86#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:08.86#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:31:08.98#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:31:08.98#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:31:08.98#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:31:08.98#ibcon#first serial, iclass 4, count 0 2006.176.07:31:08.98#ibcon#enter sib2, iclass 4, count 0 2006.176.07:31:08.98#ibcon#flushed, iclass 4, count 0 2006.176.07:31:08.98#ibcon#about to write, iclass 4, count 0 2006.176.07:31:08.98#ibcon#wrote, iclass 4, count 0 2006.176.07:31:08.98#ibcon#about to read 3, iclass 4, count 0 2006.176.07:31:09.00#ibcon#read 3, iclass 4, count 0 2006.176.07:31:09.00#ibcon#about to read 4, iclass 4, count 0 2006.176.07:31:09.00#ibcon#read 4, iclass 4, count 0 2006.176.07:31:09.00#ibcon#about to read 5, iclass 4, count 0 2006.176.07:31:09.00#ibcon#read 5, iclass 4, count 0 2006.176.07:31:09.00#ibcon#about to read 6, iclass 4, count 0 2006.176.07:31:09.00#ibcon#read 6, iclass 4, count 0 2006.176.07:31:09.00#ibcon#end of sib2, iclass 4, count 0 2006.176.07:31:09.00#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:31:09.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:31:09.00#ibcon#[25=USB\r\n] 2006.176.07:31:09.00#ibcon#*before write, iclass 4, count 0 2006.176.07:31:09.00#ibcon#enter sib2, iclass 4, count 0 2006.176.07:31:09.00#ibcon#flushed, iclass 4, count 0 2006.176.07:31:09.00#ibcon#about to write, iclass 4, count 0 2006.176.07:31:09.00#ibcon#wrote, iclass 4, count 0 2006.176.07:31:09.00#ibcon#about to read 3, iclass 4, count 0 2006.176.07:31:09.03#ibcon#read 3, iclass 4, count 0 2006.176.07:31:09.03#ibcon#about to read 4, iclass 4, count 0 2006.176.07:31:09.03#ibcon#read 4, iclass 4, count 0 2006.176.07:31:09.03#ibcon#about to read 5, iclass 4, count 0 2006.176.07:31:09.03#ibcon#read 5, iclass 4, count 0 2006.176.07:31:09.03#ibcon#about to read 6, iclass 4, count 0 2006.176.07:31:09.03#ibcon#read 6, iclass 4, count 0 2006.176.07:31:09.03#ibcon#end of sib2, iclass 4, count 0 2006.176.07:31:09.03#ibcon#*after write, iclass 4, count 0 2006.176.07:31:09.03#ibcon#*before return 0, iclass 4, count 0 2006.176.07:31:09.03#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:31:09.03#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:31:09.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:31:09.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:31:09.03$vc4f8/valo=7,832.99 2006.176.07:31:09.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.07:31:09.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.07:31:09.03#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:09.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:31:09.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:31:09.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:31:09.03#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:31:09.03#ibcon#first serial, iclass 6, count 0 2006.176.07:31:09.03#ibcon#enter sib2, iclass 6, count 0 2006.176.07:31:09.03#ibcon#flushed, iclass 6, count 0 2006.176.07:31:09.03#ibcon#about to write, iclass 6, count 0 2006.176.07:31:09.03#ibcon#wrote, iclass 6, count 0 2006.176.07:31:09.03#ibcon#about to read 3, iclass 6, count 0 2006.176.07:31:09.05#ibcon#read 3, iclass 6, count 0 2006.176.07:31:09.05#ibcon#about to read 4, iclass 6, count 0 2006.176.07:31:09.05#ibcon#read 4, iclass 6, count 0 2006.176.07:31:09.05#ibcon#about to read 5, iclass 6, count 0 2006.176.07:31:09.05#ibcon#read 5, iclass 6, count 0 2006.176.07:31:09.05#ibcon#about to read 6, iclass 6, count 0 2006.176.07:31:09.05#ibcon#read 6, iclass 6, count 0 2006.176.07:31:09.05#ibcon#end of sib2, iclass 6, count 0 2006.176.07:31:09.05#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:31:09.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:31:09.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:31:09.05#ibcon#*before write, iclass 6, count 0 2006.176.07:31:09.05#ibcon#enter sib2, iclass 6, count 0 2006.176.07:31:09.05#ibcon#flushed, iclass 6, count 0 2006.176.07:31:09.05#ibcon#about to write, iclass 6, count 0 2006.176.07:31:09.05#ibcon#wrote, iclass 6, count 0 2006.176.07:31:09.05#ibcon#about to read 3, iclass 6, count 0 2006.176.07:31:09.09#ibcon#read 3, iclass 6, count 0 2006.176.07:31:09.09#ibcon#about to read 4, iclass 6, count 0 2006.176.07:31:09.09#ibcon#read 4, iclass 6, count 0 2006.176.07:31:09.09#ibcon#about to read 5, iclass 6, count 0 2006.176.07:31:09.09#ibcon#read 5, iclass 6, count 0 2006.176.07:31:09.09#ibcon#about to read 6, iclass 6, count 0 2006.176.07:31:09.09#ibcon#read 6, iclass 6, count 0 2006.176.07:31:09.09#ibcon#end of sib2, iclass 6, count 0 2006.176.07:31:09.09#ibcon#*after write, iclass 6, count 0 2006.176.07:31:09.09#ibcon#*before return 0, iclass 6, count 0 2006.176.07:31:09.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:31:09.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:31:09.09#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:31:09.09#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:31:09.09$vc4f8/va=7,6 2006.176.07:31:09.09#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.07:31:09.09#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.07:31:09.09#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:09.09#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:31:09.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:31:09.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:31:09.15#ibcon#enter wrdev, iclass 10, count 2 2006.176.07:31:09.15#ibcon#first serial, iclass 10, count 2 2006.176.07:31:09.15#ibcon#enter sib2, iclass 10, count 2 2006.176.07:31:09.15#ibcon#flushed, iclass 10, count 2 2006.176.07:31:09.15#ibcon#about to write, iclass 10, count 2 2006.176.07:31:09.15#ibcon#wrote, iclass 10, count 2 2006.176.07:31:09.15#ibcon#about to read 3, iclass 10, count 2 2006.176.07:31:09.17#ibcon#read 3, iclass 10, count 2 2006.176.07:31:09.17#ibcon#about to read 4, iclass 10, count 2 2006.176.07:31:09.17#ibcon#read 4, iclass 10, count 2 2006.176.07:31:09.17#ibcon#about to read 5, iclass 10, count 2 2006.176.07:31:09.17#ibcon#read 5, iclass 10, count 2 2006.176.07:31:09.17#ibcon#about to read 6, iclass 10, count 2 2006.176.07:31:09.17#ibcon#read 6, iclass 10, count 2 2006.176.07:31:09.17#ibcon#end of sib2, iclass 10, count 2 2006.176.07:31:09.17#ibcon#*mode == 0, iclass 10, count 2 2006.176.07:31:09.17#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.07:31:09.17#ibcon#[25=AT07-06\r\n] 2006.176.07:31:09.17#ibcon#*before write, iclass 10, count 2 2006.176.07:31:09.17#ibcon#enter sib2, iclass 10, count 2 2006.176.07:31:09.17#ibcon#flushed, iclass 10, count 2 2006.176.07:31:09.17#ibcon#about to write, iclass 10, count 2 2006.176.07:31:09.17#ibcon#wrote, iclass 10, count 2 2006.176.07:31:09.17#ibcon#about to read 3, iclass 10, count 2 2006.176.07:31:09.20#ibcon#read 3, iclass 10, count 2 2006.176.07:31:09.20#ibcon#about to read 4, iclass 10, count 2 2006.176.07:31:09.20#ibcon#read 4, iclass 10, count 2 2006.176.07:31:09.20#ibcon#about to read 5, iclass 10, count 2 2006.176.07:31:09.20#ibcon#read 5, iclass 10, count 2 2006.176.07:31:09.20#ibcon#about to read 6, iclass 10, count 2 2006.176.07:31:09.20#ibcon#read 6, iclass 10, count 2 2006.176.07:31:09.20#ibcon#end of sib2, iclass 10, count 2 2006.176.07:31:09.20#ibcon#*after write, iclass 10, count 2 2006.176.07:31:09.20#ibcon#*before return 0, iclass 10, count 2 2006.176.07:31:09.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:31:09.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:31:09.20#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.07:31:09.20#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:09.20#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:31:09.32#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:31:09.32#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:31:09.32#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:31:09.32#ibcon#first serial, iclass 10, count 0 2006.176.07:31:09.32#ibcon#enter sib2, iclass 10, count 0 2006.176.07:31:09.32#ibcon#flushed, iclass 10, count 0 2006.176.07:31:09.32#ibcon#about to write, iclass 10, count 0 2006.176.07:31:09.32#ibcon#wrote, iclass 10, count 0 2006.176.07:31:09.32#ibcon#about to read 3, iclass 10, count 0 2006.176.07:31:09.34#ibcon#read 3, iclass 10, count 0 2006.176.07:31:09.34#ibcon#about to read 4, iclass 10, count 0 2006.176.07:31:09.34#ibcon#read 4, iclass 10, count 0 2006.176.07:31:09.34#ibcon#about to read 5, iclass 10, count 0 2006.176.07:31:09.34#ibcon#read 5, iclass 10, count 0 2006.176.07:31:09.34#ibcon#about to read 6, iclass 10, count 0 2006.176.07:31:09.34#ibcon#read 6, iclass 10, count 0 2006.176.07:31:09.34#ibcon#end of sib2, iclass 10, count 0 2006.176.07:31:09.34#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:31:09.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:31:09.34#ibcon#[25=USB\r\n] 2006.176.07:31:09.34#ibcon#*before write, iclass 10, count 0 2006.176.07:31:09.34#ibcon#enter sib2, iclass 10, count 0 2006.176.07:31:09.34#ibcon#flushed, iclass 10, count 0 2006.176.07:31:09.34#ibcon#about to write, iclass 10, count 0 2006.176.07:31:09.34#ibcon#wrote, iclass 10, count 0 2006.176.07:31:09.34#ibcon#about to read 3, iclass 10, count 0 2006.176.07:31:09.37#ibcon#read 3, iclass 10, count 0 2006.176.07:31:09.37#ibcon#about to read 4, iclass 10, count 0 2006.176.07:31:09.37#ibcon#read 4, iclass 10, count 0 2006.176.07:31:09.37#ibcon#about to read 5, iclass 10, count 0 2006.176.07:31:09.37#ibcon#read 5, iclass 10, count 0 2006.176.07:31:09.37#ibcon#about to read 6, iclass 10, count 0 2006.176.07:31:09.37#ibcon#read 6, iclass 10, count 0 2006.176.07:31:09.37#ibcon#end of sib2, iclass 10, count 0 2006.176.07:31:09.37#ibcon#*after write, iclass 10, count 0 2006.176.07:31:09.37#ibcon#*before return 0, iclass 10, count 0 2006.176.07:31:09.37#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:31:09.37#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:31:09.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:31:09.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:31:09.37$vc4f8/valo=8,852.99 2006.176.07:31:09.37#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.07:31:09.37#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.07:31:09.37#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:09.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:31:09.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:31:09.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:31:09.37#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:31:09.37#ibcon#first serial, iclass 12, count 0 2006.176.07:31:09.37#ibcon#enter sib2, iclass 12, count 0 2006.176.07:31:09.37#ibcon#flushed, iclass 12, count 0 2006.176.07:31:09.37#ibcon#about to write, iclass 12, count 0 2006.176.07:31:09.37#ibcon#wrote, iclass 12, count 0 2006.176.07:31:09.37#ibcon#about to read 3, iclass 12, count 0 2006.176.07:31:09.39#ibcon#read 3, iclass 12, count 0 2006.176.07:31:09.39#ibcon#about to read 4, iclass 12, count 0 2006.176.07:31:09.39#ibcon#read 4, iclass 12, count 0 2006.176.07:31:09.39#ibcon#about to read 5, iclass 12, count 0 2006.176.07:31:09.39#ibcon#read 5, iclass 12, count 0 2006.176.07:31:09.39#ibcon#about to read 6, iclass 12, count 0 2006.176.07:31:09.39#ibcon#read 6, iclass 12, count 0 2006.176.07:31:09.39#ibcon#end of sib2, iclass 12, count 0 2006.176.07:31:09.39#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:31:09.39#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:31:09.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:31:09.39#ibcon#*before write, iclass 12, count 0 2006.176.07:31:09.39#ibcon#enter sib2, iclass 12, count 0 2006.176.07:31:09.39#ibcon#flushed, iclass 12, count 0 2006.176.07:31:09.39#ibcon#about to write, iclass 12, count 0 2006.176.07:31:09.39#ibcon#wrote, iclass 12, count 0 2006.176.07:31:09.39#ibcon#about to read 3, iclass 12, count 0 2006.176.07:31:09.43#ibcon#read 3, iclass 12, count 0 2006.176.07:31:09.43#ibcon#about to read 4, iclass 12, count 0 2006.176.07:31:09.43#ibcon#read 4, iclass 12, count 0 2006.176.07:31:09.43#ibcon#about to read 5, iclass 12, count 0 2006.176.07:31:09.43#ibcon#read 5, iclass 12, count 0 2006.176.07:31:09.43#ibcon#about to read 6, iclass 12, count 0 2006.176.07:31:09.43#ibcon#read 6, iclass 12, count 0 2006.176.07:31:09.43#ibcon#end of sib2, iclass 12, count 0 2006.176.07:31:09.43#ibcon#*after write, iclass 12, count 0 2006.176.07:31:09.43#ibcon#*before return 0, iclass 12, count 0 2006.176.07:31:09.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:31:09.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:31:09.43#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:31:09.43#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:31:09.43$vc4f8/va=8,6 2006.176.07:31:09.43#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.07:31:09.43#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.07:31:09.43#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:09.43#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:31:09.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:31:09.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:31:09.49#ibcon#enter wrdev, iclass 14, count 2 2006.176.07:31:09.49#ibcon#first serial, iclass 14, count 2 2006.176.07:31:09.49#ibcon#enter sib2, iclass 14, count 2 2006.176.07:31:09.49#ibcon#flushed, iclass 14, count 2 2006.176.07:31:09.49#ibcon#about to write, iclass 14, count 2 2006.176.07:31:09.49#ibcon#wrote, iclass 14, count 2 2006.176.07:31:09.49#ibcon#about to read 3, iclass 14, count 2 2006.176.07:31:09.51#ibcon#read 3, iclass 14, count 2 2006.176.07:31:09.51#ibcon#about to read 4, iclass 14, count 2 2006.176.07:31:09.52#ibcon#read 4, iclass 14, count 2 2006.176.07:31:09.52#ibcon#about to read 5, iclass 14, count 2 2006.176.07:31:09.52#ibcon#read 5, iclass 14, count 2 2006.176.07:31:09.52#ibcon#about to read 6, iclass 14, count 2 2006.176.07:31:09.52#ibcon#read 6, iclass 14, count 2 2006.176.07:31:09.52#ibcon#end of sib2, iclass 14, count 2 2006.176.07:31:09.52#ibcon#*mode == 0, iclass 14, count 2 2006.176.07:31:09.52#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.07:31:09.52#ibcon#[25=AT08-06\r\n] 2006.176.07:31:09.52#ibcon#*before write, iclass 14, count 2 2006.176.07:31:09.52#ibcon#enter sib2, iclass 14, count 2 2006.176.07:31:09.52#ibcon#flushed, iclass 14, count 2 2006.176.07:31:09.52#ibcon#about to write, iclass 14, count 2 2006.176.07:31:09.52#ibcon#wrote, iclass 14, count 2 2006.176.07:31:09.52#ibcon#about to read 3, iclass 14, count 2 2006.176.07:31:09.54#ibcon#read 3, iclass 14, count 2 2006.176.07:31:09.54#ibcon#about to read 4, iclass 14, count 2 2006.176.07:31:09.54#ibcon#read 4, iclass 14, count 2 2006.176.07:31:09.54#ibcon#about to read 5, iclass 14, count 2 2006.176.07:31:09.54#ibcon#read 5, iclass 14, count 2 2006.176.07:31:09.54#ibcon#about to read 6, iclass 14, count 2 2006.176.07:31:09.54#ibcon#read 6, iclass 14, count 2 2006.176.07:31:09.54#ibcon#end of sib2, iclass 14, count 2 2006.176.07:31:09.54#ibcon#*after write, iclass 14, count 2 2006.176.07:31:09.54#ibcon#*before return 0, iclass 14, count 2 2006.176.07:31:09.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:31:09.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:31:09.54#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.07:31:09.54#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:09.54#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:31:09.66#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:31:09.66#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:31:09.66#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:31:09.66#ibcon#first serial, iclass 14, count 0 2006.176.07:31:09.66#ibcon#enter sib2, iclass 14, count 0 2006.176.07:31:09.66#ibcon#flushed, iclass 14, count 0 2006.176.07:31:09.66#ibcon#about to write, iclass 14, count 0 2006.176.07:31:09.66#ibcon#wrote, iclass 14, count 0 2006.176.07:31:09.66#ibcon#about to read 3, iclass 14, count 0 2006.176.07:31:09.68#ibcon#read 3, iclass 14, count 0 2006.176.07:31:09.68#ibcon#about to read 4, iclass 14, count 0 2006.176.07:31:09.68#ibcon#read 4, iclass 14, count 0 2006.176.07:31:09.68#ibcon#about to read 5, iclass 14, count 0 2006.176.07:31:09.68#ibcon#read 5, iclass 14, count 0 2006.176.07:31:09.68#ibcon#about to read 6, iclass 14, count 0 2006.176.07:31:09.68#ibcon#read 6, iclass 14, count 0 2006.176.07:31:09.68#ibcon#end of sib2, iclass 14, count 0 2006.176.07:31:09.68#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:31:09.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:31:09.68#ibcon#[25=USB\r\n] 2006.176.07:31:09.68#ibcon#*before write, iclass 14, count 0 2006.176.07:31:09.68#ibcon#enter sib2, iclass 14, count 0 2006.176.07:31:09.68#ibcon#flushed, iclass 14, count 0 2006.176.07:31:09.68#ibcon#about to write, iclass 14, count 0 2006.176.07:31:09.68#ibcon#wrote, iclass 14, count 0 2006.176.07:31:09.68#ibcon#about to read 3, iclass 14, count 0 2006.176.07:31:09.71#ibcon#read 3, iclass 14, count 0 2006.176.07:31:09.71#ibcon#about to read 4, iclass 14, count 0 2006.176.07:31:09.71#ibcon#read 4, iclass 14, count 0 2006.176.07:31:09.71#ibcon#about to read 5, iclass 14, count 0 2006.176.07:31:09.71#ibcon#read 5, iclass 14, count 0 2006.176.07:31:09.71#ibcon#about to read 6, iclass 14, count 0 2006.176.07:31:09.71#ibcon#read 6, iclass 14, count 0 2006.176.07:31:09.71#ibcon#end of sib2, iclass 14, count 0 2006.176.07:31:09.71#ibcon#*after write, iclass 14, count 0 2006.176.07:31:09.71#ibcon#*before return 0, iclass 14, count 0 2006.176.07:31:09.71#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:31:09.71#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:31:09.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:31:09.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:31:09.71$vc4f8/vblo=1,632.99 2006.176.07:31:09.71#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:31:09.71#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:31:09.71#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:09.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:31:09.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:31:09.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:31:09.71#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:31:09.71#ibcon#first serial, iclass 16, count 0 2006.176.07:31:09.71#ibcon#enter sib2, iclass 16, count 0 2006.176.07:31:09.71#ibcon#flushed, iclass 16, count 0 2006.176.07:31:09.71#ibcon#about to write, iclass 16, count 0 2006.176.07:31:09.71#ibcon#wrote, iclass 16, count 0 2006.176.07:31:09.71#ibcon#about to read 3, iclass 16, count 0 2006.176.07:31:09.73#ibcon#read 3, iclass 16, count 0 2006.176.07:31:09.73#ibcon#about to read 4, iclass 16, count 0 2006.176.07:31:09.73#ibcon#read 4, iclass 16, count 0 2006.176.07:31:09.73#ibcon#about to read 5, iclass 16, count 0 2006.176.07:31:09.73#ibcon#read 5, iclass 16, count 0 2006.176.07:31:09.73#ibcon#about to read 6, iclass 16, count 0 2006.176.07:31:09.73#ibcon#read 6, iclass 16, count 0 2006.176.07:31:09.73#ibcon#end of sib2, iclass 16, count 0 2006.176.07:31:09.73#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:31:09.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:31:09.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:31:09.73#ibcon#*before write, iclass 16, count 0 2006.176.07:31:09.73#ibcon#enter sib2, iclass 16, count 0 2006.176.07:31:09.73#ibcon#flushed, iclass 16, count 0 2006.176.07:31:09.73#ibcon#about to write, iclass 16, count 0 2006.176.07:31:09.73#ibcon#wrote, iclass 16, count 0 2006.176.07:31:09.73#ibcon#about to read 3, iclass 16, count 0 2006.176.07:31:09.77#ibcon#read 3, iclass 16, count 0 2006.176.07:31:09.77#ibcon#about to read 4, iclass 16, count 0 2006.176.07:31:09.77#ibcon#read 4, iclass 16, count 0 2006.176.07:31:09.77#ibcon#about to read 5, iclass 16, count 0 2006.176.07:31:09.77#ibcon#read 5, iclass 16, count 0 2006.176.07:31:09.77#ibcon#about to read 6, iclass 16, count 0 2006.176.07:31:09.77#ibcon#read 6, iclass 16, count 0 2006.176.07:31:09.77#ibcon#end of sib2, iclass 16, count 0 2006.176.07:31:09.77#ibcon#*after write, iclass 16, count 0 2006.176.07:31:09.77#ibcon#*before return 0, iclass 16, count 0 2006.176.07:31:09.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:31:09.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:31:09.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:31:09.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:31:09.77$vc4f8/vb=1,4 2006.176.07:31:09.77#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.07:31:09.77#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.07:31:09.77#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:09.77#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:31:09.77#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:31:09.77#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:31:09.77#ibcon#enter wrdev, iclass 18, count 2 2006.176.07:31:09.77#ibcon#first serial, iclass 18, count 2 2006.176.07:31:09.77#ibcon#enter sib2, iclass 18, count 2 2006.176.07:31:09.77#ibcon#flushed, iclass 18, count 2 2006.176.07:31:09.77#ibcon#about to write, iclass 18, count 2 2006.176.07:31:09.77#ibcon#wrote, iclass 18, count 2 2006.176.07:31:09.77#ibcon#about to read 3, iclass 18, count 2 2006.176.07:31:09.79#ibcon#read 3, iclass 18, count 2 2006.176.07:31:09.79#ibcon#about to read 4, iclass 18, count 2 2006.176.07:31:09.79#ibcon#read 4, iclass 18, count 2 2006.176.07:31:09.79#ibcon#about to read 5, iclass 18, count 2 2006.176.07:31:09.79#ibcon#read 5, iclass 18, count 2 2006.176.07:31:09.79#ibcon#about to read 6, iclass 18, count 2 2006.176.07:31:09.79#ibcon#read 6, iclass 18, count 2 2006.176.07:31:09.79#ibcon#end of sib2, iclass 18, count 2 2006.176.07:31:09.79#ibcon#*mode == 0, iclass 18, count 2 2006.176.07:31:09.79#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.07:31:09.79#ibcon#[27=AT01-04\r\n] 2006.176.07:31:09.79#ibcon#*before write, iclass 18, count 2 2006.176.07:31:09.79#ibcon#enter sib2, iclass 18, count 2 2006.176.07:31:09.79#ibcon#flushed, iclass 18, count 2 2006.176.07:31:09.79#ibcon#about to write, iclass 18, count 2 2006.176.07:31:09.79#ibcon#wrote, iclass 18, count 2 2006.176.07:31:09.79#ibcon#about to read 3, iclass 18, count 2 2006.176.07:31:09.82#ibcon#read 3, iclass 18, count 2 2006.176.07:31:09.82#ibcon#about to read 4, iclass 18, count 2 2006.176.07:31:09.82#ibcon#read 4, iclass 18, count 2 2006.176.07:31:09.82#ibcon#about to read 5, iclass 18, count 2 2006.176.07:31:09.82#ibcon#read 5, iclass 18, count 2 2006.176.07:31:09.82#ibcon#about to read 6, iclass 18, count 2 2006.176.07:31:09.82#ibcon#read 6, iclass 18, count 2 2006.176.07:31:09.82#ibcon#end of sib2, iclass 18, count 2 2006.176.07:31:09.82#ibcon#*after write, iclass 18, count 2 2006.176.07:31:09.82#ibcon#*before return 0, iclass 18, count 2 2006.176.07:31:09.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:31:09.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:31:09.82#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.07:31:09.82#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:09.82#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:31:09.94#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:31:09.94#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:31:09.94#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:31:09.94#ibcon#first serial, iclass 18, count 0 2006.176.07:31:09.94#ibcon#enter sib2, iclass 18, count 0 2006.176.07:31:09.94#ibcon#flushed, iclass 18, count 0 2006.176.07:31:09.94#ibcon#about to write, iclass 18, count 0 2006.176.07:31:09.94#ibcon#wrote, iclass 18, count 0 2006.176.07:31:09.94#ibcon#about to read 3, iclass 18, count 0 2006.176.07:31:09.96#ibcon#read 3, iclass 18, count 0 2006.176.07:31:09.96#ibcon#about to read 4, iclass 18, count 0 2006.176.07:31:09.96#ibcon#read 4, iclass 18, count 0 2006.176.07:31:09.96#ibcon#about to read 5, iclass 18, count 0 2006.176.07:31:09.96#ibcon#read 5, iclass 18, count 0 2006.176.07:31:09.96#ibcon#about to read 6, iclass 18, count 0 2006.176.07:31:09.96#ibcon#read 6, iclass 18, count 0 2006.176.07:31:09.96#ibcon#end of sib2, iclass 18, count 0 2006.176.07:31:09.96#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:31:09.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:31:09.96#ibcon#[27=USB\r\n] 2006.176.07:31:09.96#ibcon#*before write, iclass 18, count 0 2006.176.07:31:09.96#ibcon#enter sib2, iclass 18, count 0 2006.176.07:31:09.96#ibcon#flushed, iclass 18, count 0 2006.176.07:31:09.96#ibcon#about to write, iclass 18, count 0 2006.176.07:31:09.96#ibcon#wrote, iclass 18, count 0 2006.176.07:31:09.96#ibcon#about to read 3, iclass 18, count 0 2006.176.07:31:09.99#ibcon#read 3, iclass 18, count 0 2006.176.07:31:09.99#ibcon#about to read 4, iclass 18, count 0 2006.176.07:31:09.99#ibcon#read 4, iclass 18, count 0 2006.176.07:31:09.99#ibcon#about to read 5, iclass 18, count 0 2006.176.07:31:09.99#ibcon#read 5, iclass 18, count 0 2006.176.07:31:09.99#ibcon#about to read 6, iclass 18, count 0 2006.176.07:31:09.99#ibcon#read 6, iclass 18, count 0 2006.176.07:31:09.99#ibcon#end of sib2, iclass 18, count 0 2006.176.07:31:09.99#ibcon#*after write, iclass 18, count 0 2006.176.07:31:09.99#ibcon#*before return 0, iclass 18, count 0 2006.176.07:31:09.99#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:31:09.99#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:31:09.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:31:09.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:31:09.99$vc4f8/vblo=2,640.99 2006.176.07:31:09.99#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.07:31:09.99#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.07:31:09.99#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:09.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:09.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:09.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:09.99#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:31:09.99#ibcon#first serial, iclass 20, count 0 2006.176.07:31:09.99#ibcon#enter sib2, iclass 20, count 0 2006.176.07:31:09.99#ibcon#flushed, iclass 20, count 0 2006.176.07:31:09.99#ibcon#about to write, iclass 20, count 0 2006.176.07:31:09.99#ibcon#wrote, iclass 20, count 0 2006.176.07:31:09.99#ibcon#about to read 3, iclass 20, count 0 2006.176.07:31:10.01#ibcon#read 3, iclass 20, count 0 2006.176.07:31:10.01#ibcon#about to read 4, iclass 20, count 0 2006.176.07:31:10.01#ibcon#read 4, iclass 20, count 0 2006.176.07:31:10.01#ibcon#about to read 5, iclass 20, count 0 2006.176.07:31:10.01#ibcon#read 5, iclass 20, count 0 2006.176.07:31:10.01#ibcon#about to read 6, iclass 20, count 0 2006.176.07:31:10.01#ibcon#read 6, iclass 20, count 0 2006.176.07:31:10.01#ibcon#end of sib2, iclass 20, count 0 2006.176.07:31:10.01#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:31:10.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:31:10.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:31:10.01#ibcon#*before write, iclass 20, count 0 2006.176.07:31:10.01#ibcon#enter sib2, iclass 20, count 0 2006.176.07:31:10.01#ibcon#flushed, iclass 20, count 0 2006.176.07:31:10.01#ibcon#about to write, iclass 20, count 0 2006.176.07:31:10.01#ibcon#wrote, iclass 20, count 0 2006.176.07:31:10.01#ibcon#about to read 3, iclass 20, count 0 2006.176.07:31:10.05#ibcon#read 3, iclass 20, count 0 2006.176.07:31:10.05#ibcon#about to read 4, iclass 20, count 0 2006.176.07:31:10.05#ibcon#read 4, iclass 20, count 0 2006.176.07:31:10.05#ibcon#about to read 5, iclass 20, count 0 2006.176.07:31:10.05#ibcon#read 5, iclass 20, count 0 2006.176.07:31:10.05#ibcon#about to read 6, iclass 20, count 0 2006.176.07:31:10.05#ibcon#read 6, iclass 20, count 0 2006.176.07:31:10.05#ibcon#end of sib2, iclass 20, count 0 2006.176.07:31:10.05#ibcon#*after write, iclass 20, count 0 2006.176.07:31:10.05#ibcon#*before return 0, iclass 20, count 0 2006.176.07:31:10.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:10.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:31:10.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:31:10.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:31:10.05$vc4f8/vb=2,4 2006.176.07:31:10.05#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.07:31:10.05#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.07:31:10.05#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:10.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:10.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:10.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:10.11#ibcon#enter wrdev, iclass 22, count 2 2006.176.07:31:10.11#ibcon#first serial, iclass 22, count 2 2006.176.07:31:10.11#ibcon#enter sib2, iclass 22, count 2 2006.176.07:31:10.11#ibcon#flushed, iclass 22, count 2 2006.176.07:31:10.11#ibcon#about to write, iclass 22, count 2 2006.176.07:31:10.11#ibcon#wrote, iclass 22, count 2 2006.176.07:31:10.11#ibcon#about to read 3, iclass 22, count 2 2006.176.07:31:10.14#ibcon#read 3, iclass 22, count 2 2006.176.07:31:10.14#ibcon#about to read 4, iclass 22, count 2 2006.176.07:31:10.14#ibcon#read 4, iclass 22, count 2 2006.176.07:31:10.14#ibcon#about to read 5, iclass 22, count 2 2006.176.07:31:10.14#ibcon#read 5, iclass 22, count 2 2006.176.07:31:10.14#ibcon#about to read 6, iclass 22, count 2 2006.176.07:31:10.14#ibcon#read 6, iclass 22, count 2 2006.176.07:31:10.14#ibcon#end of sib2, iclass 22, count 2 2006.176.07:31:10.14#ibcon#*mode == 0, iclass 22, count 2 2006.176.07:31:10.14#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.07:31:10.14#ibcon#[27=AT02-04\r\n] 2006.176.07:31:10.14#ibcon#*before write, iclass 22, count 2 2006.176.07:31:10.14#ibcon#enter sib2, iclass 22, count 2 2006.176.07:31:10.14#ibcon#flushed, iclass 22, count 2 2006.176.07:31:10.14#ibcon#about to write, iclass 22, count 2 2006.176.07:31:10.14#ibcon#wrote, iclass 22, count 2 2006.176.07:31:10.14#ibcon#about to read 3, iclass 22, count 2 2006.176.07:31:10.17#ibcon#read 3, iclass 22, count 2 2006.176.07:31:10.17#ibcon#about to read 4, iclass 22, count 2 2006.176.07:31:10.17#ibcon#read 4, iclass 22, count 2 2006.176.07:31:10.17#ibcon#about to read 5, iclass 22, count 2 2006.176.07:31:10.17#ibcon#read 5, iclass 22, count 2 2006.176.07:31:10.17#ibcon#about to read 6, iclass 22, count 2 2006.176.07:31:10.17#ibcon#read 6, iclass 22, count 2 2006.176.07:31:10.17#ibcon#end of sib2, iclass 22, count 2 2006.176.07:31:10.17#ibcon#*after write, iclass 22, count 2 2006.176.07:31:10.17#ibcon#*before return 0, iclass 22, count 2 2006.176.07:31:10.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:10.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:31:10.17#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.07:31:10.17#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:10.17#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:10.29#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:10.29#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:10.29#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:31:10.29#ibcon#first serial, iclass 22, count 0 2006.176.07:31:10.29#ibcon#enter sib2, iclass 22, count 0 2006.176.07:31:10.29#ibcon#flushed, iclass 22, count 0 2006.176.07:31:10.29#ibcon#about to write, iclass 22, count 0 2006.176.07:31:10.29#ibcon#wrote, iclass 22, count 0 2006.176.07:31:10.29#ibcon#about to read 3, iclass 22, count 0 2006.176.07:31:10.31#ibcon#read 3, iclass 22, count 0 2006.176.07:31:10.31#ibcon#about to read 4, iclass 22, count 0 2006.176.07:31:10.31#ibcon#read 4, iclass 22, count 0 2006.176.07:31:10.31#ibcon#about to read 5, iclass 22, count 0 2006.176.07:31:10.31#ibcon#read 5, iclass 22, count 0 2006.176.07:31:10.31#ibcon#about to read 6, iclass 22, count 0 2006.176.07:31:10.31#ibcon#read 6, iclass 22, count 0 2006.176.07:31:10.31#ibcon#end of sib2, iclass 22, count 0 2006.176.07:31:10.31#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:31:10.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:31:10.31#ibcon#[27=USB\r\n] 2006.176.07:31:10.31#ibcon#*before write, iclass 22, count 0 2006.176.07:31:10.31#ibcon#enter sib2, iclass 22, count 0 2006.176.07:31:10.31#ibcon#flushed, iclass 22, count 0 2006.176.07:31:10.31#ibcon#about to write, iclass 22, count 0 2006.176.07:31:10.31#ibcon#wrote, iclass 22, count 0 2006.176.07:31:10.31#ibcon#about to read 3, iclass 22, count 0 2006.176.07:31:10.34#ibcon#read 3, iclass 22, count 0 2006.176.07:31:10.34#ibcon#about to read 4, iclass 22, count 0 2006.176.07:31:10.34#ibcon#read 4, iclass 22, count 0 2006.176.07:31:10.34#ibcon#about to read 5, iclass 22, count 0 2006.176.07:31:10.34#ibcon#read 5, iclass 22, count 0 2006.176.07:31:10.34#ibcon#about to read 6, iclass 22, count 0 2006.176.07:31:10.34#ibcon#read 6, iclass 22, count 0 2006.176.07:31:10.34#ibcon#end of sib2, iclass 22, count 0 2006.176.07:31:10.34#ibcon#*after write, iclass 22, count 0 2006.176.07:31:10.34#ibcon#*before return 0, iclass 22, count 0 2006.176.07:31:10.34#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:10.34#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:31:10.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:31:10.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:31:10.34$vc4f8/vblo=3,656.99 2006.176.07:31:10.34#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.07:31:10.34#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.07:31:10.34#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:10.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:10.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:10.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:10.34#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:31:10.34#ibcon#first serial, iclass 24, count 0 2006.176.07:31:10.34#ibcon#enter sib2, iclass 24, count 0 2006.176.07:31:10.34#ibcon#flushed, iclass 24, count 0 2006.176.07:31:10.34#ibcon#about to write, iclass 24, count 0 2006.176.07:31:10.34#ibcon#wrote, iclass 24, count 0 2006.176.07:31:10.34#ibcon#about to read 3, iclass 24, count 0 2006.176.07:31:10.36#ibcon#read 3, iclass 24, count 0 2006.176.07:31:10.36#ibcon#about to read 4, iclass 24, count 0 2006.176.07:31:10.36#ibcon#read 4, iclass 24, count 0 2006.176.07:31:10.36#ibcon#about to read 5, iclass 24, count 0 2006.176.07:31:10.36#ibcon#read 5, iclass 24, count 0 2006.176.07:31:10.36#ibcon#about to read 6, iclass 24, count 0 2006.176.07:31:10.36#ibcon#read 6, iclass 24, count 0 2006.176.07:31:10.36#ibcon#end of sib2, iclass 24, count 0 2006.176.07:31:10.36#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:31:10.36#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:31:10.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:31:10.36#ibcon#*before write, iclass 24, count 0 2006.176.07:31:10.36#ibcon#enter sib2, iclass 24, count 0 2006.176.07:31:10.36#ibcon#flushed, iclass 24, count 0 2006.176.07:31:10.36#ibcon#about to write, iclass 24, count 0 2006.176.07:31:10.36#ibcon#wrote, iclass 24, count 0 2006.176.07:31:10.36#ibcon#about to read 3, iclass 24, count 0 2006.176.07:31:10.40#ibcon#read 3, iclass 24, count 0 2006.176.07:31:10.40#ibcon#about to read 4, iclass 24, count 0 2006.176.07:31:10.40#ibcon#read 4, iclass 24, count 0 2006.176.07:31:10.40#ibcon#about to read 5, iclass 24, count 0 2006.176.07:31:10.40#ibcon#read 5, iclass 24, count 0 2006.176.07:31:10.40#ibcon#about to read 6, iclass 24, count 0 2006.176.07:31:10.40#ibcon#read 6, iclass 24, count 0 2006.176.07:31:10.40#ibcon#end of sib2, iclass 24, count 0 2006.176.07:31:10.40#ibcon#*after write, iclass 24, count 0 2006.176.07:31:10.40#ibcon#*before return 0, iclass 24, count 0 2006.176.07:31:10.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:10.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:31:10.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:31:10.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:31:10.40$vc4f8/vb=3,4 2006.176.07:31:10.40#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.07:31:10.40#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.07:31:10.40#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:10.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:10.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:10.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:10.46#ibcon#enter wrdev, iclass 26, count 2 2006.176.07:31:10.46#ibcon#first serial, iclass 26, count 2 2006.176.07:31:10.46#ibcon#enter sib2, iclass 26, count 2 2006.176.07:31:10.46#ibcon#flushed, iclass 26, count 2 2006.176.07:31:10.46#ibcon#about to write, iclass 26, count 2 2006.176.07:31:10.46#ibcon#wrote, iclass 26, count 2 2006.176.07:31:10.46#ibcon#about to read 3, iclass 26, count 2 2006.176.07:31:10.48#ibcon#read 3, iclass 26, count 2 2006.176.07:31:10.48#ibcon#about to read 4, iclass 26, count 2 2006.176.07:31:10.48#ibcon#read 4, iclass 26, count 2 2006.176.07:31:10.48#ibcon#about to read 5, iclass 26, count 2 2006.176.07:31:10.48#ibcon#read 5, iclass 26, count 2 2006.176.07:31:10.48#ibcon#about to read 6, iclass 26, count 2 2006.176.07:31:10.48#ibcon#read 6, iclass 26, count 2 2006.176.07:31:10.48#ibcon#end of sib2, iclass 26, count 2 2006.176.07:31:10.48#ibcon#*mode == 0, iclass 26, count 2 2006.176.07:31:10.48#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.07:31:10.48#ibcon#[27=AT03-04\r\n] 2006.176.07:31:10.48#ibcon#*before write, iclass 26, count 2 2006.176.07:31:10.48#ibcon#enter sib2, iclass 26, count 2 2006.176.07:31:10.48#ibcon#flushed, iclass 26, count 2 2006.176.07:31:10.48#ibcon#about to write, iclass 26, count 2 2006.176.07:31:10.48#ibcon#wrote, iclass 26, count 2 2006.176.07:31:10.48#ibcon#about to read 3, iclass 26, count 2 2006.176.07:31:10.51#ibcon#read 3, iclass 26, count 2 2006.176.07:31:10.51#ibcon#about to read 4, iclass 26, count 2 2006.176.07:31:10.51#ibcon#read 4, iclass 26, count 2 2006.176.07:31:10.51#ibcon#about to read 5, iclass 26, count 2 2006.176.07:31:10.51#ibcon#read 5, iclass 26, count 2 2006.176.07:31:10.51#ibcon#about to read 6, iclass 26, count 2 2006.176.07:31:10.51#ibcon#read 6, iclass 26, count 2 2006.176.07:31:10.51#ibcon#end of sib2, iclass 26, count 2 2006.176.07:31:10.51#ibcon#*after write, iclass 26, count 2 2006.176.07:31:10.51#ibcon#*before return 0, iclass 26, count 2 2006.176.07:31:10.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:10.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:31:10.51#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.07:31:10.51#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:10.51#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:10.63#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:10.63#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:10.63#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:31:10.63#ibcon#first serial, iclass 26, count 0 2006.176.07:31:10.63#ibcon#enter sib2, iclass 26, count 0 2006.176.07:31:10.63#ibcon#flushed, iclass 26, count 0 2006.176.07:31:10.63#ibcon#about to write, iclass 26, count 0 2006.176.07:31:10.63#ibcon#wrote, iclass 26, count 0 2006.176.07:31:10.63#ibcon#about to read 3, iclass 26, count 0 2006.176.07:31:10.65#ibcon#read 3, iclass 26, count 0 2006.176.07:31:10.65#ibcon#about to read 4, iclass 26, count 0 2006.176.07:31:10.65#ibcon#read 4, iclass 26, count 0 2006.176.07:31:10.65#ibcon#about to read 5, iclass 26, count 0 2006.176.07:31:10.65#ibcon#read 5, iclass 26, count 0 2006.176.07:31:10.65#ibcon#about to read 6, iclass 26, count 0 2006.176.07:31:10.65#ibcon#read 6, iclass 26, count 0 2006.176.07:31:10.65#ibcon#end of sib2, iclass 26, count 0 2006.176.07:31:10.65#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:31:10.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:31:10.65#ibcon#[27=USB\r\n] 2006.176.07:31:10.65#ibcon#*before write, iclass 26, count 0 2006.176.07:31:10.65#ibcon#enter sib2, iclass 26, count 0 2006.176.07:31:10.65#ibcon#flushed, iclass 26, count 0 2006.176.07:31:10.65#ibcon#about to write, iclass 26, count 0 2006.176.07:31:10.65#ibcon#wrote, iclass 26, count 0 2006.176.07:31:10.65#ibcon#about to read 3, iclass 26, count 0 2006.176.07:31:10.68#ibcon#read 3, iclass 26, count 0 2006.176.07:31:10.68#ibcon#about to read 4, iclass 26, count 0 2006.176.07:31:10.68#ibcon#read 4, iclass 26, count 0 2006.176.07:31:10.68#ibcon#about to read 5, iclass 26, count 0 2006.176.07:31:10.68#ibcon#read 5, iclass 26, count 0 2006.176.07:31:10.68#ibcon#about to read 6, iclass 26, count 0 2006.176.07:31:10.68#ibcon#read 6, iclass 26, count 0 2006.176.07:31:10.68#ibcon#end of sib2, iclass 26, count 0 2006.176.07:31:10.68#ibcon#*after write, iclass 26, count 0 2006.176.07:31:10.68#ibcon#*before return 0, iclass 26, count 0 2006.176.07:31:10.68#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:10.68#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:31:10.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:31:10.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:31:10.68$vc4f8/vblo=4,712.99 2006.176.07:31:10.68#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.07:31:10.68#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.07:31:10.68#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:10.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:10.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:10.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:10.68#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:31:10.68#ibcon#first serial, iclass 28, count 0 2006.176.07:31:10.68#ibcon#enter sib2, iclass 28, count 0 2006.176.07:31:10.68#ibcon#flushed, iclass 28, count 0 2006.176.07:31:10.68#ibcon#about to write, iclass 28, count 0 2006.176.07:31:10.68#ibcon#wrote, iclass 28, count 0 2006.176.07:31:10.68#ibcon#about to read 3, iclass 28, count 0 2006.176.07:31:10.70#ibcon#read 3, iclass 28, count 0 2006.176.07:31:10.70#ibcon#about to read 4, iclass 28, count 0 2006.176.07:31:10.70#ibcon#read 4, iclass 28, count 0 2006.176.07:31:10.70#ibcon#about to read 5, iclass 28, count 0 2006.176.07:31:10.70#ibcon#read 5, iclass 28, count 0 2006.176.07:31:10.70#ibcon#about to read 6, iclass 28, count 0 2006.176.07:31:10.70#ibcon#read 6, iclass 28, count 0 2006.176.07:31:10.70#ibcon#end of sib2, iclass 28, count 0 2006.176.07:31:10.70#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:31:10.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:31:10.70#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:31:10.70#ibcon#*before write, iclass 28, count 0 2006.176.07:31:10.70#ibcon#enter sib2, iclass 28, count 0 2006.176.07:31:10.70#ibcon#flushed, iclass 28, count 0 2006.176.07:31:10.70#ibcon#about to write, iclass 28, count 0 2006.176.07:31:10.70#ibcon#wrote, iclass 28, count 0 2006.176.07:31:10.70#ibcon#about to read 3, iclass 28, count 0 2006.176.07:31:10.74#ibcon#read 3, iclass 28, count 0 2006.176.07:31:10.74#ibcon#about to read 4, iclass 28, count 0 2006.176.07:31:10.74#ibcon#read 4, iclass 28, count 0 2006.176.07:31:10.74#ibcon#about to read 5, iclass 28, count 0 2006.176.07:31:10.74#ibcon#read 5, iclass 28, count 0 2006.176.07:31:10.74#ibcon#about to read 6, iclass 28, count 0 2006.176.07:31:10.74#ibcon#read 6, iclass 28, count 0 2006.176.07:31:10.74#ibcon#end of sib2, iclass 28, count 0 2006.176.07:31:10.74#ibcon#*after write, iclass 28, count 0 2006.176.07:31:10.74#ibcon#*before return 0, iclass 28, count 0 2006.176.07:31:10.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:10.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:31:10.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:31:10.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:31:10.74$vc4f8/vb=4,4 2006.176.07:31:10.74#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.07:31:10.74#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.07:31:10.74#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:10.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:10.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:10.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:10.80#ibcon#enter wrdev, iclass 30, count 2 2006.176.07:31:10.80#ibcon#first serial, iclass 30, count 2 2006.176.07:31:10.80#ibcon#enter sib2, iclass 30, count 2 2006.176.07:31:10.80#ibcon#flushed, iclass 30, count 2 2006.176.07:31:10.80#ibcon#about to write, iclass 30, count 2 2006.176.07:31:10.80#ibcon#wrote, iclass 30, count 2 2006.176.07:31:10.80#ibcon#about to read 3, iclass 30, count 2 2006.176.07:31:10.82#ibcon#read 3, iclass 30, count 2 2006.176.07:31:10.82#ibcon#about to read 4, iclass 30, count 2 2006.176.07:31:10.82#ibcon#read 4, iclass 30, count 2 2006.176.07:31:10.82#ibcon#about to read 5, iclass 30, count 2 2006.176.07:31:10.82#ibcon#read 5, iclass 30, count 2 2006.176.07:31:10.82#ibcon#about to read 6, iclass 30, count 2 2006.176.07:31:10.82#ibcon#read 6, iclass 30, count 2 2006.176.07:31:10.82#ibcon#end of sib2, iclass 30, count 2 2006.176.07:31:10.82#ibcon#*mode == 0, iclass 30, count 2 2006.176.07:31:10.82#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.07:31:10.82#ibcon#[27=AT04-04\r\n] 2006.176.07:31:10.82#ibcon#*before write, iclass 30, count 2 2006.176.07:31:10.82#ibcon#enter sib2, iclass 30, count 2 2006.176.07:31:10.82#ibcon#flushed, iclass 30, count 2 2006.176.07:31:10.82#ibcon#about to write, iclass 30, count 2 2006.176.07:31:10.82#ibcon#wrote, iclass 30, count 2 2006.176.07:31:10.82#ibcon#about to read 3, iclass 30, count 2 2006.176.07:31:10.85#ibcon#read 3, iclass 30, count 2 2006.176.07:31:10.85#ibcon#about to read 4, iclass 30, count 2 2006.176.07:31:10.85#ibcon#read 4, iclass 30, count 2 2006.176.07:31:10.85#ibcon#about to read 5, iclass 30, count 2 2006.176.07:31:10.85#ibcon#read 5, iclass 30, count 2 2006.176.07:31:10.85#ibcon#about to read 6, iclass 30, count 2 2006.176.07:31:10.85#ibcon#read 6, iclass 30, count 2 2006.176.07:31:10.85#ibcon#end of sib2, iclass 30, count 2 2006.176.07:31:10.85#ibcon#*after write, iclass 30, count 2 2006.176.07:31:10.85#ibcon#*before return 0, iclass 30, count 2 2006.176.07:31:10.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:10.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:31:10.85#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.07:31:10.85#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:10.85#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:10.97#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:10.97#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:10.97#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:31:10.97#ibcon#first serial, iclass 30, count 0 2006.176.07:31:10.97#ibcon#enter sib2, iclass 30, count 0 2006.176.07:31:10.97#ibcon#flushed, iclass 30, count 0 2006.176.07:31:10.97#ibcon#about to write, iclass 30, count 0 2006.176.07:31:10.97#ibcon#wrote, iclass 30, count 0 2006.176.07:31:10.97#ibcon#about to read 3, iclass 30, count 0 2006.176.07:31:10.99#ibcon#read 3, iclass 30, count 0 2006.176.07:31:10.99#ibcon#about to read 4, iclass 30, count 0 2006.176.07:31:10.99#ibcon#read 4, iclass 30, count 0 2006.176.07:31:10.99#ibcon#about to read 5, iclass 30, count 0 2006.176.07:31:10.99#ibcon#read 5, iclass 30, count 0 2006.176.07:31:10.99#ibcon#about to read 6, iclass 30, count 0 2006.176.07:31:10.99#ibcon#read 6, iclass 30, count 0 2006.176.07:31:10.99#ibcon#end of sib2, iclass 30, count 0 2006.176.07:31:10.99#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:31:10.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:31:10.99#ibcon#[27=USB\r\n] 2006.176.07:31:10.99#ibcon#*before write, iclass 30, count 0 2006.176.07:31:10.99#ibcon#enter sib2, iclass 30, count 0 2006.176.07:31:10.99#ibcon#flushed, iclass 30, count 0 2006.176.07:31:10.99#ibcon#about to write, iclass 30, count 0 2006.176.07:31:10.99#ibcon#wrote, iclass 30, count 0 2006.176.07:31:10.99#ibcon#about to read 3, iclass 30, count 0 2006.176.07:31:11.02#ibcon#read 3, iclass 30, count 0 2006.176.07:31:11.02#ibcon#about to read 4, iclass 30, count 0 2006.176.07:31:11.02#ibcon#read 4, iclass 30, count 0 2006.176.07:31:11.02#ibcon#about to read 5, iclass 30, count 0 2006.176.07:31:11.02#ibcon#read 5, iclass 30, count 0 2006.176.07:31:11.02#ibcon#about to read 6, iclass 30, count 0 2006.176.07:31:11.02#ibcon#read 6, iclass 30, count 0 2006.176.07:31:11.02#ibcon#end of sib2, iclass 30, count 0 2006.176.07:31:11.02#ibcon#*after write, iclass 30, count 0 2006.176.07:31:11.02#ibcon#*before return 0, iclass 30, count 0 2006.176.07:31:11.02#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:11.02#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:31:11.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:31:11.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:31:11.02$vc4f8/vblo=5,744.99 2006.176.07:31:11.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.07:31:11.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.07:31:11.02#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:11.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:11.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:11.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:11.02#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:31:11.02#ibcon#first serial, iclass 32, count 0 2006.176.07:31:11.02#ibcon#enter sib2, iclass 32, count 0 2006.176.07:31:11.02#ibcon#flushed, iclass 32, count 0 2006.176.07:31:11.02#ibcon#about to write, iclass 32, count 0 2006.176.07:31:11.02#ibcon#wrote, iclass 32, count 0 2006.176.07:31:11.02#ibcon#about to read 3, iclass 32, count 0 2006.176.07:31:11.04#ibcon#read 3, iclass 32, count 0 2006.176.07:31:11.04#ibcon#about to read 4, iclass 32, count 0 2006.176.07:31:11.04#ibcon#read 4, iclass 32, count 0 2006.176.07:31:11.04#ibcon#about to read 5, iclass 32, count 0 2006.176.07:31:11.04#ibcon#read 5, iclass 32, count 0 2006.176.07:31:11.04#ibcon#about to read 6, iclass 32, count 0 2006.176.07:31:11.04#ibcon#read 6, iclass 32, count 0 2006.176.07:31:11.04#ibcon#end of sib2, iclass 32, count 0 2006.176.07:31:11.04#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:31:11.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:31:11.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:31:11.04#ibcon#*before write, iclass 32, count 0 2006.176.07:31:11.04#ibcon#enter sib2, iclass 32, count 0 2006.176.07:31:11.04#ibcon#flushed, iclass 32, count 0 2006.176.07:31:11.04#ibcon#about to write, iclass 32, count 0 2006.176.07:31:11.04#ibcon#wrote, iclass 32, count 0 2006.176.07:31:11.04#ibcon#about to read 3, iclass 32, count 0 2006.176.07:31:11.08#ibcon#read 3, iclass 32, count 0 2006.176.07:31:11.08#ibcon#about to read 4, iclass 32, count 0 2006.176.07:31:11.08#ibcon#read 4, iclass 32, count 0 2006.176.07:31:11.08#ibcon#about to read 5, iclass 32, count 0 2006.176.07:31:11.08#ibcon#read 5, iclass 32, count 0 2006.176.07:31:11.08#ibcon#about to read 6, iclass 32, count 0 2006.176.07:31:11.08#ibcon#read 6, iclass 32, count 0 2006.176.07:31:11.08#ibcon#end of sib2, iclass 32, count 0 2006.176.07:31:11.08#ibcon#*after write, iclass 32, count 0 2006.176.07:31:11.08#ibcon#*before return 0, iclass 32, count 0 2006.176.07:31:11.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:11.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:31:11.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:31:11.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:31:11.08$vc4f8/vb=5,4 2006.176.07:31:11.08#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.07:31:11.08#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.07:31:11.08#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:11.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:11.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:11.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:11.14#ibcon#enter wrdev, iclass 34, count 2 2006.176.07:31:11.14#ibcon#first serial, iclass 34, count 2 2006.176.07:31:11.14#ibcon#enter sib2, iclass 34, count 2 2006.176.07:31:11.14#ibcon#flushed, iclass 34, count 2 2006.176.07:31:11.14#ibcon#about to write, iclass 34, count 2 2006.176.07:31:11.14#ibcon#wrote, iclass 34, count 2 2006.176.07:31:11.14#ibcon#about to read 3, iclass 34, count 2 2006.176.07:31:11.17#ibcon#read 3, iclass 34, count 2 2006.176.07:31:11.17#ibcon#about to read 4, iclass 34, count 2 2006.176.07:31:11.17#ibcon#read 4, iclass 34, count 2 2006.176.07:31:11.17#ibcon#about to read 5, iclass 34, count 2 2006.176.07:31:11.17#ibcon#read 5, iclass 34, count 2 2006.176.07:31:11.17#ibcon#about to read 6, iclass 34, count 2 2006.176.07:31:11.17#ibcon#read 6, iclass 34, count 2 2006.176.07:31:11.17#ibcon#end of sib2, iclass 34, count 2 2006.176.07:31:11.17#ibcon#*mode == 0, iclass 34, count 2 2006.176.07:31:11.17#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.07:31:11.17#ibcon#[27=AT05-04\r\n] 2006.176.07:31:11.17#ibcon#*before write, iclass 34, count 2 2006.176.07:31:11.17#ibcon#enter sib2, iclass 34, count 2 2006.176.07:31:11.17#ibcon#flushed, iclass 34, count 2 2006.176.07:31:11.17#ibcon#about to write, iclass 34, count 2 2006.176.07:31:11.17#ibcon#wrote, iclass 34, count 2 2006.176.07:31:11.17#ibcon#about to read 3, iclass 34, count 2 2006.176.07:31:11.20#ibcon#read 3, iclass 34, count 2 2006.176.07:31:11.20#ibcon#about to read 4, iclass 34, count 2 2006.176.07:31:11.20#ibcon#read 4, iclass 34, count 2 2006.176.07:31:11.20#ibcon#about to read 5, iclass 34, count 2 2006.176.07:31:11.20#ibcon#read 5, iclass 34, count 2 2006.176.07:31:11.20#ibcon#about to read 6, iclass 34, count 2 2006.176.07:31:11.20#ibcon#read 6, iclass 34, count 2 2006.176.07:31:11.20#ibcon#end of sib2, iclass 34, count 2 2006.176.07:31:11.20#ibcon#*after write, iclass 34, count 2 2006.176.07:31:11.20#ibcon#*before return 0, iclass 34, count 2 2006.176.07:31:11.20#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:11.20#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:31:11.20#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.07:31:11.20#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:11.20#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:11.32#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:11.32#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:11.32#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:31:11.32#ibcon#first serial, iclass 34, count 0 2006.176.07:31:11.32#ibcon#enter sib2, iclass 34, count 0 2006.176.07:31:11.32#ibcon#flushed, iclass 34, count 0 2006.176.07:31:11.32#ibcon#about to write, iclass 34, count 0 2006.176.07:31:11.32#ibcon#wrote, iclass 34, count 0 2006.176.07:31:11.32#ibcon#about to read 3, iclass 34, count 0 2006.176.07:31:11.34#ibcon#read 3, iclass 34, count 0 2006.176.07:31:11.34#ibcon#about to read 4, iclass 34, count 0 2006.176.07:31:11.34#ibcon#read 4, iclass 34, count 0 2006.176.07:31:11.34#ibcon#about to read 5, iclass 34, count 0 2006.176.07:31:11.34#ibcon#read 5, iclass 34, count 0 2006.176.07:31:11.34#ibcon#about to read 6, iclass 34, count 0 2006.176.07:31:11.34#ibcon#read 6, iclass 34, count 0 2006.176.07:31:11.34#ibcon#end of sib2, iclass 34, count 0 2006.176.07:31:11.34#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:31:11.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:31:11.34#ibcon#[27=USB\r\n] 2006.176.07:31:11.34#ibcon#*before write, iclass 34, count 0 2006.176.07:31:11.34#ibcon#enter sib2, iclass 34, count 0 2006.176.07:31:11.34#ibcon#flushed, iclass 34, count 0 2006.176.07:31:11.34#ibcon#about to write, iclass 34, count 0 2006.176.07:31:11.34#ibcon#wrote, iclass 34, count 0 2006.176.07:31:11.34#ibcon#about to read 3, iclass 34, count 0 2006.176.07:31:11.37#ibcon#read 3, iclass 34, count 0 2006.176.07:31:11.37#ibcon#about to read 4, iclass 34, count 0 2006.176.07:31:11.37#ibcon#read 4, iclass 34, count 0 2006.176.07:31:11.37#ibcon#about to read 5, iclass 34, count 0 2006.176.07:31:11.37#ibcon#read 5, iclass 34, count 0 2006.176.07:31:11.37#ibcon#about to read 6, iclass 34, count 0 2006.176.07:31:11.37#ibcon#read 6, iclass 34, count 0 2006.176.07:31:11.37#ibcon#end of sib2, iclass 34, count 0 2006.176.07:31:11.37#ibcon#*after write, iclass 34, count 0 2006.176.07:31:11.37#ibcon#*before return 0, iclass 34, count 0 2006.176.07:31:11.37#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:11.37#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:31:11.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:31:11.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:31:11.37$vc4f8/vblo=6,752.99 2006.176.07:31:11.37#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.07:31:11.37#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.07:31:11.37#ibcon#ireg 17 cls_cnt 0 2006.176.07:31:11.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:11.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:11.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:11.37#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:31:11.37#ibcon#first serial, iclass 36, count 0 2006.176.07:31:11.37#ibcon#enter sib2, iclass 36, count 0 2006.176.07:31:11.37#ibcon#flushed, iclass 36, count 0 2006.176.07:31:11.37#ibcon#about to write, iclass 36, count 0 2006.176.07:31:11.37#ibcon#wrote, iclass 36, count 0 2006.176.07:31:11.37#ibcon#about to read 3, iclass 36, count 0 2006.176.07:31:11.39#ibcon#read 3, iclass 36, count 0 2006.176.07:31:11.39#ibcon#about to read 4, iclass 36, count 0 2006.176.07:31:11.39#ibcon#read 4, iclass 36, count 0 2006.176.07:31:11.39#ibcon#about to read 5, iclass 36, count 0 2006.176.07:31:11.39#ibcon#read 5, iclass 36, count 0 2006.176.07:31:11.39#ibcon#about to read 6, iclass 36, count 0 2006.176.07:31:11.39#ibcon#read 6, iclass 36, count 0 2006.176.07:31:11.39#ibcon#end of sib2, iclass 36, count 0 2006.176.07:31:11.39#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:31:11.39#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:31:11.39#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:31:11.39#ibcon#*before write, iclass 36, count 0 2006.176.07:31:11.39#ibcon#enter sib2, iclass 36, count 0 2006.176.07:31:11.39#ibcon#flushed, iclass 36, count 0 2006.176.07:31:11.39#ibcon#about to write, iclass 36, count 0 2006.176.07:31:11.39#ibcon#wrote, iclass 36, count 0 2006.176.07:31:11.39#ibcon#about to read 3, iclass 36, count 0 2006.176.07:31:11.43#ibcon#read 3, iclass 36, count 0 2006.176.07:31:11.43#ibcon#about to read 4, iclass 36, count 0 2006.176.07:31:11.43#ibcon#read 4, iclass 36, count 0 2006.176.07:31:11.43#ibcon#about to read 5, iclass 36, count 0 2006.176.07:31:11.43#ibcon#read 5, iclass 36, count 0 2006.176.07:31:11.43#ibcon#about to read 6, iclass 36, count 0 2006.176.07:31:11.43#ibcon#read 6, iclass 36, count 0 2006.176.07:31:11.43#ibcon#end of sib2, iclass 36, count 0 2006.176.07:31:11.43#ibcon#*after write, iclass 36, count 0 2006.176.07:31:11.43#ibcon#*before return 0, iclass 36, count 0 2006.176.07:31:11.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:11.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:31:11.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:31:11.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:31:11.43$vc4f8/vb=6,4 2006.176.07:31:11.43#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.07:31:11.43#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.07:31:11.43#ibcon#ireg 11 cls_cnt 2 2006.176.07:31:11.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:11.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:11.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:11.49#ibcon#enter wrdev, iclass 38, count 2 2006.176.07:31:11.49#ibcon#first serial, iclass 38, count 2 2006.176.07:31:11.49#ibcon#enter sib2, iclass 38, count 2 2006.176.07:31:11.49#ibcon#flushed, iclass 38, count 2 2006.176.07:31:11.49#ibcon#about to write, iclass 38, count 2 2006.176.07:31:11.49#ibcon#wrote, iclass 38, count 2 2006.176.07:31:11.49#ibcon#about to read 3, iclass 38, count 2 2006.176.07:31:11.51#ibcon#read 3, iclass 38, count 2 2006.176.07:31:11.51#ibcon#about to read 4, iclass 38, count 2 2006.176.07:31:11.51#ibcon#read 4, iclass 38, count 2 2006.176.07:31:11.51#ibcon#about to read 5, iclass 38, count 2 2006.176.07:31:11.51#ibcon#read 5, iclass 38, count 2 2006.176.07:31:11.51#ibcon#about to read 6, iclass 38, count 2 2006.176.07:31:11.51#ibcon#read 6, iclass 38, count 2 2006.176.07:31:11.51#ibcon#end of sib2, iclass 38, count 2 2006.176.07:31:11.51#ibcon#*mode == 0, iclass 38, count 2 2006.176.07:31:11.51#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.07:31:11.51#ibcon#[27=AT06-04\r\n] 2006.176.07:31:11.51#ibcon#*before write, iclass 38, count 2 2006.176.07:31:11.51#ibcon#enter sib2, iclass 38, count 2 2006.176.07:31:11.51#ibcon#flushed, iclass 38, count 2 2006.176.07:31:11.51#ibcon#about to write, iclass 38, count 2 2006.176.07:31:11.51#ibcon#wrote, iclass 38, count 2 2006.176.07:31:11.51#ibcon#about to read 3, iclass 38, count 2 2006.176.07:31:11.54#ibcon#read 3, iclass 38, count 2 2006.176.07:31:11.54#ibcon#about to read 4, iclass 38, count 2 2006.176.07:31:11.54#ibcon#read 4, iclass 38, count 2 2006.176.07:31:11.54#ibcon#about to read 5, iclass 38, count 2 2006.176.07:31:11.54#ibcon#read 5, iclass 38, count 2 2006.176.07:31:11.54#ibcon#about to read 6, iclass 38, count 2 2006.176.07:31:11.54#ibcon#read 6, iclass 38, count 2 2006.176.07:31:11.54#ibcon#end of sib2, iclass 38, count 2 2006.176.07:31:11.54#ibcon#*after write, iclass 38, count 2 2006.176.07:31:11.54#ibcon#*before return 0, iclass 38, count 2 2006.176.07:31:11.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:11.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:31:11.54#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.07:31:11.54#ibcon#ireg 7 cls_cnt 0 2006.176.07:31:11.54#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:11.66#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:11.66#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:11.66#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:31:11.66#ibcon#first serial, iclass 38, count 0 2006.176.07:31:11.66#ibcon#enter sib2, iclass 38, count 0 2006.176.07:31:11.66#ibcon#flushed, iclass 38, count 0 2006.176.07:31:11.66#ibcon#about to write, iclass 38, count 0 2006.176.07:31:11.66#ibcon#wrote, iclass 38, count 0 2006.176.07:31:11.66#ibcon#about to read 3, iclass 38, count 0 2006.176.07:31:11.68#ibcon#read 3, iclass 38, count 0 2006.176.07:31:11.68#ibcon#about to read 4, iclass 38, count 0 2006.176.07:31:11.68#ibcon#read 4, iclass 38, count 0 2006.176.07:31:11.68#ibcon#about to read 5, iclass 38, count 0 2006.176.07:31:11.68#ibcon#read 5, iclass 38, count 0 2006.176.07:31:11.68#ibcon#about to read 6, iclass 38, count 0 2006.176.07:31:11.68#ibcon#read 6, iclass 38, count 0 2006.176.07:31:11.68#ibcon#end of sib2, iclass 38, count 0 2006.176.07:31:11.68#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:31:11.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:31:11.68#ibcon#[27=USB\r\n] 2006.176.07:31:11.68#ibcon#*before write, iclass 38, count 0 2006.176.07:31:11.68#ibcon#enter sib2, iclass 38, count 0 2006.176.07:31:11.68#ibcon#flushed, iclass 38, count 0 2006.176.07:31:11.68#ibcon#about to write, iclass 38, count 0 2006.176.07:31:11.68#ibcon#wrote, iclass 38, count 0 2006.176.07:31:11.68#ibcon#about to read 3, iclass 38, count 0 2006.176.07:31:11.71#ibcon#read 3, iclass 38, count 0 2006.176.07:31:11.71#ibcon#about to read 4, iclass 38, count 0 2006.176.07:31:11.71#ibcon#read 4, iclass 38, count 0 2006.176.07:31:11.71#ibcon#about to read 5, iclass 38, count 0 2006.176.07:31:11.71#ibcon#read 5, iclass 38, count 0 2006.176.07:31:11.71#ibcon#about to read 6, iclass 38, count 0 2006.176.07:31:11.71#ibcon#read 6, iclass 38, count 0 2006.176.07:31:11.71#ibcon#end of sib2, iclass 38, count 0 2006.176.07:31:11.71#ibcon#*after write, iclass 38, count 0 2006.176.07:31:11.71#ibcon#*before return 0, iclass 38, count 0 2006.176.07:31:11.71#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:11.71#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:31:11.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:31:11.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:31:11.71$vc4f8/vabw=wide 2006.176.07:31:11.71#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.07:31:11.71#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.07:31:11.71#ibcon#ireg 8 cls_cnt 0 2006.176.07:31:11.71#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:31:11.71#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:31:11.71#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:31:11.71#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:31:11.71#ibcon#first serial, iclass 3, count 0 2006.176.07:31:11.71#ibcon#enter sib2, iclass 3, count 0 2006.176.07:31:11.71#ibcon#flushed, iclass 3, count 0 2006.176.07:31:11.71#ibcon#about to write, iclass 3, count 0 2006.176.07:31:11.71#ibcon#wrote, iclass 3, count 0 2006.176.07:31:11.71#ibcon#about to read 3, iclass 3, count 0 2006.176.07:31:11.72#abcon#<5=/05 3.7 6.4 24.00 911008.3\r\n> 2006.176.07:31:11.73#ibcon#read 3, iclass 3, count 0 2006.176.07:31:11.73#ibcon#about to read 4, iclass 3, count 0 2006.176.07:31:11.73#ibcon#read 4, iclass 3, count 0 2006.176.07:31:11.73#ibcon#about to read 5, iclass 3, count 0 2006.176.07:31:11.73#ibcon#read 5, iclass 3, count 0 2006.176.07:31:11.73#ibcon#about to read 6, iclass 3, count 0 2006.176.07:31:11.73#ibcon#read 6, iclass 3, count 0 2006.176.07:31:11.73#ibcon#end of sib2, iclass 3, count 0 2006.176.07:31:11.73#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:31:11.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:31:11.73#ibcon#[25=BW32\r\n] 2006.176.07:31:11.73#ibcon#*before write, iclass 3, count 0 2006.176.07:31:11.73#ibcon#enter sib2, iclass 3, count 0 2006.176.07:31:11.73#ibcon#flushed, iclass 3, count 0 2006.176.07:31:11.73#ibcon#about to write, iclass 3, count 0 2006.176.07:31:11.73#ibcon#wrote, iclass 3, count 0 2006.176.07:31:11.73#ibcon#about to read 3, iclass 3, count 0 2006.176.07:31:11.74#abcon#{5=INTERFACE CLEAR} 2006.176.07:31:11.76#ibcon#read 3, iclass 3, count 0 2006.176.07:31:11.76#ibcon#about to read 4, iclass 3, count 0 2006.176.07:31:11.76#ibcon#read 4, iclass 3, count 0 2006.176.07:31:11.76#ibcon#about to read 5, iclass 3, count 0 2006.176.07:31:11.76#ibcon#read 5, iclass 3, count 0 2006.176.07:31:11.76#ibcon#about to read 6, iclass 3, count 0 2006.176.07:31:11.76#ibcon#read 6, iclass 3, count 0 2006.176.07:31:11.76#ibcon#end of sib2, iclass 3, count 0 2006.176.07:31:11.76#ibcon#*after write, iclass 3, count 0 2006.176.07:31:11.76#ibcon#*before return 0, iclass 3, count 0 2006.176.07:31:11.76#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:31:11.76#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:31:11.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:31:11.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:31:11.76$vc4f8/vbbw=wide 2006.176.07:31:11.76#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.07:31:11.76#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.07:31:11.76#ibcon#ireg 8 cls_cnt 0 2006.176.07:31:11.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:31:11.80#abcon#[5=S1D000X0/0*\r\n] 2006.176.07:31:11.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:31:11.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:31:11.83#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:31:11.83#ibcon#first serial, iclass 7, count 0 2006.176.07:31:11.83#ibcon#enter sib2, iclass 7, count 0 2006.176.07:31:11.83#ibcon#flushed, iclass 7, count 0 2006.176.07:31:11.83#ibcon#about to write, iclass 7, count 0 2006.176.07:31:11.83#ibcon#wrote, iclass 7, count 0 2006.176.07:31:11.83#ibcon#about to read 3, iclass 7, count 0 2006.176.07:31:11.85#ibcon#read 3, iclass 7, count 0 2006.176.07:31:11.85#ibcon#about to read 4, iclass 7, count 0 2006.176.07:31:11.85#ibcon#read 4, iclass 7, count 0 2006.176.07:31:11.85#ibcon#about to read 5, iclass 7, count 0 2006.176.07:31:11.85#ibcon#read 5, iclass 7, count 0 2006.176.07:31:11.85#ibcon#about to read 6, iclass 7, count 0 2006.176.07:31:11.85#ibcon#read 6, iclass 7, count 0 2006.176.07:31:11.85#ibcon#end of sib2, iclass 7, count 0 2006.176.07:31:11.85#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:31:11.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:31:11.85#ibcon#[27=BW32\r\n] 2006.176.07:31:11.85#ibcon#*before write, iclass 7, count 0 2006.176.07:31:11.85#ibcon#enter sib2, iclass 7, count 0 2006.176.07:31:11.85#ibcon#flushed, iclass 7, count 0 2006.176.07:31:11.85#ibcon#about to write, iclass 7, count 0 2006.176.07:31:11.85#ibcon#wrote, iclass 7, count 0 2006.176.07:31:11.85#ibcon#about to read 3, iclass 7, count 0 2006.176.07:31:11.88#ibcon#read 3, iclass 7, count 0 2006.176.07:31:11.88#ibcon#about to read 4, iclass 7, count 0 2006.176.07:31:11.88#ibcon#read 4, iclass 7, count 0 2006.176.07:31:11.88#ibcon#about to read 5, iclass 7, count 0 2006.176.07:31:11.88#ibcon#read 5, iclass 7, count 0 2006.176.07:31:11.88#ibcon#about to read 6, iclass 7, count 0 2006.176.07:31:11.88#ibcon#read 6, iclass 7, count 0 2006.176.07:31:11.88#ibcon#end of sib2, iclass 7, count 0 2006.176.07:31:11.88#ibcon#*after write, iclass 7, count 0 2006.176.07:31:11.88#ibcon#*before return 0, iclass 7, count 0 2006.176.07:31:11.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:31:11.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:31:11.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:31:11.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:31:11.88$4f8m12a/ifd4f 2006.176.07:31:11.88$ifd4f/lo= 2006.176.07:31:11.88$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:31:11.88$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:31:11.88$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:31:11.88$ifd4f/patch= 2006.176.07:31:11.88$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:31:11.88$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:31:11.88$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:31:11.88$4f8m12a/"form=m,16.000,1:2 2006.176.07:31:11.88$4f8m12a/"tpicd 2006.176.07:31:11.88$4f8m12a/echo=off 2006.176.07:31:11.88$4f8m12a/xlog=off 2006.176.07:31:11.88:!2006.176.07:33:20 2006.176.07:31:50.14#trakl#Source acquired 2006.176.07:31:51.14#flagr#flagr/antenna,acquired 2006.176.07:33:20.00:preob 2006.176.07:33:20.13/onsource/TRACKING 2006.176.07:33:20.13:!2006.176.07:33:30 2006.176.07:33:30.00:data_valid=on 2006.176.07:33:30.00:midob 2006.176.07:33:30.13/onsource/TRACKING 2006.176.07:33:30.13/wx/23.99,1008.3,90 2006.176.07:33:30.25/cable/+6.4932E-03 2006.176.07:33:31.34/va/01,08,usb,yes,29,30 2006.176.07:33:31.34/va/02,07,usb,yes,29,30 2006.176.07:33:31.34/va/03,06,usb,yes,30,31 2006.176.07:33:31.34/va/04,07,usb,yes,30,32 2006.176.07:33:31.34/va/05,07,usb,yes,31,33 2006.176.07:33:31.34/va/06,06,usb,yes,30,30 2006.176.07:33:31.34/va/07,06,usb,yes,30,30 2006.176.07:33:31.34/va/08,06,usb,yes,33,32 2006.176.07:33:31.57/valo/01,532.99,yes,locked 2006.176.07:33:31.57/valo/02,572.99,yes,locked 2006.176.07:33:31.57/valo/03,672.99,yes,locked 2006.176.07:33:31.57/valo/04,832.99,yes,locked 2006.176.07:33:31.57/valo/05,652.99,yes,locked 2006.176.07:33:31.57/valo/06,772.99,yes,locked 2006.176.07:33:31.57/valo/07,832.99,yes,locked 2006.176.07:33:31.57/valo/08,852.99,yes,locked 2006.176.07:33:32.66/vb/01,04,usb,yes,29,28 2006.176.07:33:32.66/vb/02,04,usb,yes,31,32 2006.176.07:33:32.66/vb/03,04,usb,yes,27,31 2006.176.07:33:32.66/vb/04,04,usb,yes,28,28 2006.176.07:33:32.66/vb/05,04,usb,yes,27,30 2006.176.07:33:32.66/vb/06,04,usb,yes,28,30 2006.176.07:33:32.66/vb/07,04,usb,yes,30,29 2006.176.07:33:32.66/vb/08,04,usb,yes,27,30 2006.176.07:33:32.89/vblo/01,632.99,yes,locked 2006.176.07:33:32.89/vblo/02,640.99,yes,locked 2006.176.07:33:32.89/vblo/03,656.99,yes,locked 2006.176.07:33:32.89/vblo/04,712.99,yes,locked 2006.176.07:33:32.89/vblo/05,744.99,yes,locked 2006.176.07:33:32.89/vblo/06,752.99,yes,locked 2006.176.07:33:32.89/vblo/07,734.99,yes,locked 2006.176.07:33:32.89/vblo/08,744.99,yes,locked 2006.176.07:33:33.04/vabw/8 2006.176.07:33:33.19/vbbw/8 2006.176.07:33:33.28/xfe/off,on,15.2 2006.176.07:33:33.67/ifatt/23,28,28,28 2006.176.07:33:34.07/fmout-gps/S +3.72E-07 2006.176.07:33:34.15:!2006.176.07:34:30 2006.176.07:34:30.00:data_valid=off 2006.176.07:34:30.00:postob 2006.176.07:34:30.16/cable/+6.4935E-03 2006.176.07:34:30.16/wx/23.99,1008.4,91 2006.176.07:34:31.07/fmout-gps/S +3.72E-07 2006.176.07:34:31.07:scan_name=176-0735,k06176,60 2006.176.07:34:31.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.176.07:34:31.14#flagr#flagr/antenna,new-source 2006.176.07:34:32.14:checkk5 2006.176.07:34:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:34:32.93/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:34:33.30/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:34:33.68/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:34:34.05/chk_obsdata//k5ts1/T1760733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:34:34.42/chk_obsdata//k5ts2/T1760733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:34:34.79/chk_obsdata//k5ts3/T1760733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:34:35.17/chk_obsdata//k5ts4/T1760733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:34:35.86/k5log//k5ts1_log_newline 2006.176.07:34:36.56/k5log//k5ts2_log_newline 2006.176.07:34:37.26/k5log//k5ts3_log_newline 2006.176.07:34:37.95/k5log//k5ts4_log_newline 2006.176.07:34:37.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:34:37.97:4f8m12a=1 2006.176.07:34:37.97$4f8m12a/echo=on 2006.176.07:34:37.97$4f8m12a/pcalon 2006.176.07:34:37.97$pcalon/"no phase cal control is implemented here 2006.176.07:34:37.97$4f8m12a/"tpicd=stop 2006.176.07:34:37.97$4f8m12a/vc4f8 2006.176.07:34:37.97$vc4f8/valo=1,532.99 2006.176.07:34:37.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.07:34:37.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.07:34:37.97#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:37.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:37.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:37.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:37.97#ibcon#enter wrdev, iclass 21, count 0 2006.176.07:34:37.97#ibcon#first serial, iclass 21, count 0 2006.176.07:34:37.97#ibcon#enter sib2, iclass 21, count 0 2006.176.07:34:37.97#ibcon#flushed, iclass 21, count 0 2006.176.07:34:37.97#ibcon#about to write, iclass 21, count 0 2006.176.07:34:37.97#ibcon#wrote, iclass 21, count 0 2006.176.07:34:37.97#ibcon#about to read 3, iclass 21, count 0 2006.176.07:34:38.02#ibcon#read 3, iclass 21, count 0 2006.176.07:34:38.02#ibcon#about to read 4, iclass 21, count 0 2006.176.07:34:38.02#ibcon#read 4, iclass 21, count 0 2006.176.07:34:38.02#ibcon#about to read 5, iclass 21, count 0 2006.176.07:34:38.02#ibcon#read 5, iclass 21, count 0 2006.176.07:34:38.02#ibcon#about to read 6, iclass 21, count 0 2006.176.07:34:38.02#ibcon#read 6, iclass 21, count 0 2006.176.07:34:38.02#ibcon#end of sib2, iclass 21, count 0 2006.176.07:34:38.02#ibcon#*mode == 0, iclass 21, count 0 2006.176.07:34:38.02#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.07:34:38.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:34:38.02#ibcon#*before write, iclass 21, count 0 2006.176.07:34:38.02#ibcon#enter sib2, iclass 21, count 0 2006.176.07:34:38.02#ibcon#flushed, iclass 21, count 0 2006.176.07:34:38.02#ibcon#about to write, iclass 21, count 0 2006.176.07:34:38.02#ibcon#wrote, iclass 21, count 0 2006.176.07:34:38.02#ibcon#about to read 3, iclass 21, count 0 2006.176.07:34:38.06#ibcon#read 3, iclass 21, count 0 2006.176.07:34:38.06#ibcon#about to read 4, iclass 21, count 0 2006.176.07:34:38.06#ibcon#read 4, iclass 21, count 0 2006.176.07:34:38.06#ibcon#about to read 5, iclass 21, count 0 2006.176.07:34:38.06#ibcon#read 5, iclass 21, count 0 2006.176.07:34:38.06#ibcon#about to read 6, iclass 21, count 0 2006.176.07:34:38.06#ibcon#read 6, iclass 21, count 0 2006.176.07:34:38.06#ibcon#end of sib2, iclass 21, count 0 2006.176.07:34:38.06#ibcon#*after write, iclass 21, count 0 2006.176.07:34:38.06#ibcon#*before return 0, iclass 21, count 0 2006.176.07:34:38.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:38.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:38.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.07:34:38.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.07:34:38.06$vc4f8/va=1,8 2006.176.07:34:38.06#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.07:34:38.06#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.07:34:38.06#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:38.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:38.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:38.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:38.06#ibcon#enter wrdev, iclass 23, count 2 2006.176.07:34:38.06#ibcon#first serial, iclass 23, count 2 2006.176.07:34:38.06#ibcon#enter sib2, iclass 23, count 2 2006.176.07:34:38.06#ibcon#flushed, iclass 23, count 2 2006.176.07:34:38.06#ibcon#about to write, iclass 23, count 2 2006.176.07:34:38.06#ibcon#wrote, iclass 23, count 2 2006.176.07:34:38.06#ibcon#about to read 3, iclass 23, count 2 2006.176.07:34:38.08#ibcon#read 3, iclass 23, count 2 2006.176.07:34:38.08#ibcon#about to read 4, iclass 23, count 2 2006.176.07:34:38.08#ibcon#read 4, iclass 23, count 2 2006.176.07:34:38.08#ibcon#about to read 5, iclass 23, count 2 2006.176.07:34:38.08#ibcon#read 5, iclass 23, count 2 2006.176.07:34:38.08#ibcon#about to read 6, iclass 23, count 2 2006.176.07:34:38.08#ibcon#read 6, iclass 23, count 2 2006.176.07:34:38.08#ibcon#end of sib2, iclass 23, count 2 2006.176.07:34:38.08#ibcon#*mode == 0, iclass 23, count 2 2006.176.07:34:38.08#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.07:34:38.08#ibcon#[25=AT01-08\r\n] 2006.176.07:34:38.08#ibcon#*before write, iclass 23, count 2 2006.176.07:34:38.08#ibcon#enter sib2, iclass 23, count 2 2006.176.07:34:38.08#ibcon#flushed, iclass 23, count 2 2006.176.07:34:38.08#ibcon#about to write, iclass 23, count 2 2006.176.07:34:38.08#ibcon#wrote, iclass 23, count 2 2006.176.07:34:38.08#ibcon#about to read 3, iclass 23, count 2 2006.176.07:34:38.11#ibcon#read 3, iclass 23, count 2 2006.176.07:34:38.11#ibcon#about to read 4, iclass 23, count 2 2006.176.07:34:38.11#ibcon#read 4, iclass 23, count 2 2006.176.07:34:38.11#ibcon#about to read 5, iclass 23, count 2 2006.176.07:34:38.11#ibcon#read 5, iclass 23, count 2 2006.176.07:34:38.11#ibcon#about to read 6, iclass 23, count 2 2006.176.07:34:38.11#ibcon#read 6, iclass 23, count 2 2006.176.07:34:38.11#ibcon#end of sib2, iclass 23, count 2 2006.176.07:34:38.11#ibcon#*after write, iclass 23, count 2 2006.176.07:34:38.11#ibcon#*before return 0, iclass 23, count 2 2006.176.07:34:38.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:38.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:38.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.07:34:38.11#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:38.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:38.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:38.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:38.23#ibcon#enter wrdev, iclass 23, count 0 2006.176.07:34:38.23#ibcon#first serial, iclass 23, count 0 2006.176.07:34:38.23#ibcon#enter sib2, iclass 23, count 0 2006.176.07:34:38.23#ibcon#flushed, iclass 23, count 0 2006.176.07:34:38.23#ibcon#about to write, iclass 23, count 0 2006.176.07:34:38.23#ibcon#wrote, iclass 23, count 0 2006.176.07:34:38.23#ibcon#about to read 3, iclass 23, count 0 2006.176.07:34:38.25#ibcon#read 3, iclass 23, count 0 2006.176.07:34:38.25#ibcon#about to read 4, iclass 23, count 0 2006.176.07:34:38.25#ibcon#read 4, iclass 23, count 0 2006.176.07:34:38.25#ibcon#about to read 5, iclass 23, count 0 2006.176.07:34:38.25#ibcon#read 5, iclass 23, count 0 2006.176.07:34:38.25#ibcon#about to read 6, iclass 23, count 0 2006.176.07:34:38.25#ibcon#read 6, iclass 23, count 0 2006.176.07:34:38.25#ibcon#end of sib2, iclass 23, count 0 2006.176.07:34:38.25#ibcon#*mode == 0, iclass 23, count 0 2006.176.07:34:38.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.07:34:38.25#ibcon#[25=USB\r\n] 2006.176.07:34:38.25#ibcon#*before write, iclass 23, count 0 2006.176.07:34:38.25#ibcon#enter sib2, iclass 23, count 0 2006.176.07:34:38.25#ibcon#flushed, iclass 23, count 0 2006.176.07:34:38.25#ibcon#about to write, iclass 23, count 0 2006.176.07:34:38.25#ibcon#wrote, iclass 23, count 0 2006.176.07:34:38.25#ibcon#about to read 3, iclass 23, count 0 2006.176.07:34:38.28#ibcon#read 3, iclass 23, count 0 2006.176.07:34:38.28#ibcon#about to read 4, iclass 23, count 0 2006.176.07:34:38.28#ibcon#read 4, iclass 23, count 0 2006.176.07:34:38.28#ibcon#about to read 5, iclass 23, count 0 2006.176.07:34:38.28#ibcon#read 5, iclass 23, count 0 2006.176.07:34:38.28#ibcon#about to read 6, iclass 23, count 0 2006.176.07:34:38.28#ibcon#read 6, iclass 23, count 0 2006.176.07:34:38.28#ibcon#end of sib2, iclass 23, count 0 2006.176.07:34:38.28#ibcon#*after write, iclass 23, count 0 2006.176.07:34:38.28#ibcon#*before return 0, iclass 23, count 0 2006.176.07:34:38.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:38.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:38.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.07:34:38.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.07:34:38.28$vc4f8/valo=2,572.99 2006.176.07:34:38.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.07:34:38.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.07:34:38.28#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:38.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:38.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:38.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:38.28#ibcon#enter wrdev, iclass 25, count 0 2006.176.07:34:38.28#ibcon#first serial, iclass 25, count 0 2006.176.07:34:38.28#ibcon#enter sib2, iclass 25, count 0 2006.176.07:34:38.28#ibcon#flushed, iclass 25, count 0 2006.176.07:34:38.28#ibcon#about to write, iclass 25, count 0 2006.176.07:34:38.28#ibcon#wrote, iclass 25, count 0 2006.176.07:34:38.28#ibcon#about to read 3, iclass 25, count 0 2006.176.07:34:38.30#ibcon#read 3, iclass 25, count 0 2006.176.07:34:38.30#ibcon#about to read 4, iclass 25, count 0 2006.176.07:34:38.30#ibcon#read 4, iclass 25, count 0 2006.176.07:34:38.30#ibcon#about to read 5, iclass 25, count 0 2006.176.07:34:38.30#ibcon#read 5, iclass 25, count 0 2006.176.07:34:38.30#ibcon#about to read 6, iclass 25, count 0 2006.176.07:34:38.30#ibcon#read 6, iclass 25, count 0 2006.176.07:34:38.30#ibcon#end of sib2, iclass 25, count 0 2006.176.07:34:38.30#ibcon#*mode == 0, iclass 25, count 0 2006.176.07:34:38.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.07:34:38.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:34:38.30#ibcon#*before write, iclass 25, count 0 2006.176.07:34:38.30#ibcon#enter sib2, iclass 25, count 0 2006.176.07:34:38.30#ibcon#flushed, iclass 25, count 0 2006.176.07:34:38.30#ibcon#about to write, iclass 25, count 0 2006.176.07:34:38.30#ibcon#wrote, iclass 25, count 0 2006.176.07:34:38.30#ibcon#about to read 3, iclass 25, count 0 2006.176.07:34:38.34#ibcon#read 3, iclass 25, count 0 2006.176.07:34:38.34#ibcon#about to read 4, iclass 25, count 0 2006.176.07:34:38.34#ibcon#read 4, iclass 25, count 0 2006.176.07:34:38.34#ibcon#about to read 5, iclass 25, count 0 2006.176.07:34:38.34#ibcon#read 5, iclass 25, count 0 2006.176.07:34:38.34#ibcon#about to read 6, iclass 25, count 0 2006.176.07:34:38.34#ibcon#read 6, iclass 25, count 0 2006.176.07:34:38.34#ibcon#end of sib2, iclass 25, count 0 2006.176.07:34:38.34#ibcon#*after write, iclass 25, count 0 2006.176.07:34:38.34#ibcon#*before return 0, iclass 25, count 0 2006.176.07:34:38.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:38.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:38.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.07:34:38.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.07:34:38.34$vc4f8/va=2,7 2006.176.07:34:38.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.07:34:38.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.07:34:38.34#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:38.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:38.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:38.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:38.40#ibcon#enter wrdev, iclass 27, count 2 2006.176.07:34:38.40#ibcon#first serial, iclass 27, count 2 2006.176.07:34:38.40#ibcon#enter sib2, iclass 27, count 2 2006.176.07:34:38.40#ibcon#flushed, iclass 27, count 2 2006.176.07:34:38.40#ibcon#about to write, iclass 27, count 2 2006.176.07:34:38.40#ibcon#wrote, iclass 27, count 2 2006.176.07:34:38.40#ibcon#about to read 3, iclass 27, count 2 2006.176.07:34:38.42#ibcon#read 3, iclass 27, count 2 2006.176.07:34:38.42#ibcon#about to read 4, iclass 27, count 2 2006.176.07:34:38.42#ibcon#read 4, iclass 27, count 2 2006.176.07:34:38.42#ibcon#about to read 5, iclass 27, count 2 2006.176.07:34:38.42#ibcon#read 5, iclass 27, count 2 2006.176.07:34:38.42#ibcon#about to read 6, iclass 27, count 2 2006.176.07:34:38.42#ibcon#read 6, iclass 27, count 2 2006.176.07:34:38.42#ibcon#end of sib2, iclass 27, count 2 2006.176.07:34:38.42#ibcon#*mode == 0, iclass 27, count 2 2006.176.07:34:38.42#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.07:34:38.42#ibcon#[25=AT02-07\r\n] 2006.176.07:34:38.42#ibcon#*before write, iclass 27, count 2 2006.176.07:34:38.42#ibcon#enter sib2, iclass 27, count 2 2006.176.07:34:38.42#ibcon#flushed, iclass 27, count 2 2006.176.07:34:38.42#ibcon#about to write, iclass 27, count 2 2006.176.07:34:38.42#ibcon#wrote, iclass 27, count 2 2006.176.07:34:38.42#ibcon#about to read 3, iclass 27, count 2 2006.176.07:34:38.45#ibcon#read 3, iclass 27, count 2 2006.176.07:34:38.45#ibcon#about to read 4, iclass 27, count 2 2006.176.07:34:38.45#ibcon#read 4, iclass 27, count 2 2006.176.07:34:38.45#ibcon#about to read 5, iclass 27, count 2 2006.176.07:34:38.45#ibcon#read 5, iclass 27, count 2 2006.176.07:34:38.45#ibcon#about to read 6, iclass 27, count 2 2006.176.07:34:38.45#ibcon#read 6, iclass 27, count 2 2006.176.07:34:38.45#ibcon#end of sib2, iclass 27, count 2 2006.176.07:34:38.45#ibcon#*after write, iclass 27, count 2 2006.176.07:34:38.45#ibcon#*before return 0, iclass 27, count 2 2006.176.07:34:38.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:38.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:38.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.07:34:38.45#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:38.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:38.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:38.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:38.57#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:34:38.57#ibcon#first serial, iclass 27, count 0 2006.176.07:34:38.57#ibcon#enter sib2, iclass 27, count 0 2006.176.07:34:38.57#ibcon#flushed, iclass 27, count 0 2006.176.07:34:38.57#ibcon#about to write, iclass 27, count 0 2006.176.07:34:38.57#ibcon#wrote, iclass 27, count 0 2006.176.07:34:38.57#ibcon#about to read 3, iclass 27, count 0 2006.176.07:34:38.59#ibcon#read 3, iclass 27, count 0 2006.176.07:34:38.59#ibcon#about to read 4, iclass 27, count 0 2006.176.07:34:38.59#ibcon#read 4, iclass 27, count 0 2006.176.07:34:38.59#ibcon#about to read 5, iclass 27, count 0 2006.176.07:34:38.59#ibcon#read 5, iclass 27, count 0 2006.176.07:34:38.59#ibcon#about to read 6, iclass 27, count 0 2006.176.07:34:38.59#ibcon#read 6, iclass 27, count 0 2006.176.07:34:38.59#ibcon#end of sib2, iclass 27, count 0 2006.176.07:34:38.59#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:34:38.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:34:38.59#ibcon#[25=USB\r\n] 2006.176.07:34:38.59#ibcon#*before write, iclass 27, count 0 2006.176.07:34:38.59#ibcon#enter sib2, iclass 27, count 0 2006.176.07:34:38.59#ibcon#flushed, iclass 27, count 0 2006.176.07:34:38.59#ibcon#about to write, iclass 27, count 0 2006.176.07:34:38.59#ibcon#wrote, iclass 27, count 0 2006.176.07:34:38.59#ibcon#about to read 3, iclass 27, count 0 2006.176.07:34:38.62#ibcon#read 3, iclass 27, count 0 2006.176.07:34:38.62#ibcon#about to read 4, iclass 27, count 0 2006.176.07:34:38.62#ibcon#read 4, iclass 27, count 0 2006.176.07:34:38.62#ibcon#about to read 5, iclass 27, count 0 2006.176.07:34:38.62#ibcon#read 5, iclass 27, count 0 2006.176.07:34:38.62#ibcon#about to read 6, iclass 27, count 0 2006.176.07:34:38.62#ibcon#read 6, iclass 27, count 0 2006.176.07:34:38.62#ibcon#end of sib2, iclass 27, count 0 2006.176.07:34:38.62#ibcon#*after write, iclass 27, count 0 2006.176.07:34:38.62#ibcon#*before return 0, iclass 27, count 0 2006.176.07:34:38.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:38.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:38.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:34:38.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:34:38.62$vc4f8/valo=3,672.99 2006.176.07:34:38.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.07:34:38.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.07:34:38.62#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:38.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:38.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:38.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:38.62#ibcon#enter wrdev, iclass 29, count 0 2006.176.07:34:38.62#ibcon#first serial, iclass 29, count 0 2006.176.07:34:38.62#ibcon#enter sib2, iclass 29, count 0 2006.176.07:34:38.62#ibcon#flushed, iclass 29, count 0 2006.176.07:34:38.62#ibcon#about to write, iclass 29, count 0 2006.176.07:34:38.62#ibcon#wrote, iclass 29, count 0 2006.176.07:34:38.62#ibcon#about to read 3, iclass 29, count 0 2006.176.07:34:38.64#ibcon#read 3, iclass 29, count 0 2006.176.07:34:38.64#ibcon#about to read 4, iclass 29, count 0 2006.176.07:34:38.64#ibcon#read 4, iclass 29, count 0 2006.176.07:34:38.64#ibcon#about to read 5, iclass 29, count 0 2006.176.07:34:38.64#ibcon#read 5, iclass 29, count 0 2006.176.07:34:38.64#ibcon#about to read 6, iclass 29, count 0 2006.176.07:34:38.64#ibcon#read 6, iclass 29, count 0 2006.176.07:34:38.64#ibcon#end of sib2, iclass 29, count 0 2006.176.07:34:38.64#ibcon#*mode == 0, iclass 29, count 0 2006.176.07:34:38.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.07:34:38.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:34:38.64#ibcon#*before write, iclass 29, count 0 2006.176.07:34:38.64#ibcon#enter sib2, iclass 29, count 0 2006.176.07:34:38.64#ibcon#flushed, iclass 29, count 0 2006.176.07:34:38.64#ibcon#about to write, iclass 29, count 0 2006.176.07:34:38.64#ibcon#wrote, iclass 29, count 0 2006.176.07:34:38.64#ibcon#about to read 3, iclass 29, count 0 2006.176.07:34:38.68#ibcon#read 3, iclass 29, count 0 2006.176.07:34:38.68#ibcon#about to read 4, iclass 29, count 0 2006.176.07:34:38.68#ibcon#read 4, iclass 29, count 0 2006.176.07:34:38.68#ibcon#about to read 5, iclass 29, count 0 2006.176.07:34:38.68#ibcon#read 5, iclass 29, count 0 2006.176.07:34:38.68#ibcon#about to read 6, iclass 29, count 0 2006.176.07:34:38.68#ibcon#read 6, iclass 29, count 0 2006.176.07:34:38.68#ibcon#end of sib2, iclass 29, count 0 2006.176.07:34:38.68#ibcon#*after write, iclass 29, count 0 2006.176.07:34:38.68#ibcon#*before return 0, iclass 29, count 0 2006.176.07:34:38.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:38.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:38.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.07:34:38.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.07:34:38.68$vc4f8/va=3,6 2006.176.07:34:38.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.07:34:38.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.07:34:38.68#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:38.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:38.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:38.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:38.74#ibcon#enter wrdev, iclass 31, count 2 2006.176.07:34:38.74#ibcon#first serial, iclass 31, count 2 2006.176.07:34:38.74#ibcon#enter sib2, iclass 31, count 2 2006.176.07:34:38.74#ibcon#flushed, iclass 31, count 2 2006.176.07:34:38.74#ibcon#about to write, iclass 31, count 2 2006.176.07:34:38.74#ibcon#wrote, iclass 31, count 2 2006.176.07:34:38.74#ibcon#about to read 3, iclass 31, count 2 2006.176.07:34:38.76#ibcon#read 3, iclass 31, count 2 2006.176.07:34:38.76#ibcon#about to read 4, iclass 31, count 2 2006.176.07:34:38.76#ibcon#read 4, iclass 31, count 2 2006.176.07:34:38.76#ibcon#about to read 5, iclass 31, count 2 2006.176.07:34:38.76#ibcon#read 5, iclass 31, count 2 2006.176.07:34:38.76#ibcon#about to read 6, iclass 31, count 2 2006.176.07:34:38.76#ibcon#read 6, iclass 31, count 2 2006.176.07:34:38.76#ibcon#end of sib2, iclass 31, count 2 2006.176.07:34:38.76#ibcon#*mode == 0, iclass 31, count 2 2006.176.07:34:38.76#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.07:34:38.76#ibcon#[25=AT03-06\r\n] 2006.176.07:34:38.76#ibcon#*before write, iclass 31, count 2 2006.176.07:34:38.76#ibcon#enter sib2, iclass 31, count 2 2006.176.07:34:38.76#ibcon#flushed, iclass 31, count 2 2006.176.07:34:38.76#ibcon#about to write, iclass 31, count 2 2006.176.07:34:38.76#ibcon#wrote, iclass 31, count 2 2006.176.07:34:38.76#ibcon#about to read 3, iclass 31, count 2 2006.176.07:34:38.79#ibcon#read 3, iclass 31, count 2 2006.176.07:34:38.79#ibcon#about to read 4, iclass 31, count 2 2006.176.07:34:38.79#ibcon#read 4, iclass 31, count 2 2006.176.07:34:38.79#ibcon#about to read 5, iclass 31, count 2 2006.176.07:34:38.79#ibcon#read 5, iclass 31, count 2 2006.176.07:34:38.79#ibcon#about to read 6, iclass 31, count 2 2006.176.07:34:38.79#ibcon#read 6, iclass 31, count 2 2006.176.07:34:38.79#ibcon#end of sib2, iclass 31, count 2 2006.176.07:34:38.79#ibcon#*after write, iclass 31, count 2 2006.176.07:34:38.79#ibcon#*before return 0, iclass 31, count 2 2006.176.07:34:38.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:38.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:38.79#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.07:34:38.79#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:38.79#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:38.91#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:38.91#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:38.91#ibcon#enter wrdev, iclass 31, count 0 2006.176.07:34:38.91#ibcon#first serial, iclass 31, count 0 2006.176.07:34:38.91#ibcon#enter sib2, iclass 31, count 0 2006.176.07:34:38.91#ibcon#flushed, iclass 31, count 0 2006.176.07:34:38.91#ibcon#about to write, iclass 31, count 0 2006.176.07:34:38.91#ibcon#wrote, iclass 31, count 0 2006.176.07:34:38.91#ibcon#about to read 3, iclass 31, count 0 2006.176.07:34:38.93#ibcon#read 3, iclass 31, count 0 2006.176.07:34:38.93#ibcon#about to read 4, iclass 31, count 0 2006.176.07:34:38.93#ibcon#read 4, iclass 31, count 0 2006.176.07:34:38.93#ibcon#about to read 5, iclass 31, count 0 2006.176.07:34:38.93#ibcon#read 5, iclass 31, count 0 2006.176.07:34:38.93#ibcon#about to read 6, iclass 31, count 0 2006.176.07:34:38.93#ibcon#read 6, iclass 31, count 0 2006.176.07:34:38.93#ibcon#end of sib2, iclass 31, count 0 2006.176.07:34:38.93#ibcon#*mode == 0, iclass 31, count 0 2006.176.07:34:38.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.07:34:38.93#ibcon#[25=USB\r\n] 2006.176.07:34:38.93#ibcon#*before write, iclass 31, count 0 2006.176.07:34:38.93#ibcon#enter sib2, iclass 31, count 0 2006.176.07:34:38.93#ibcon#flushed, iclass 31, count 0 2006.176.07:34:38.93#ibcon#about to write, iclass 31, count 0 2006.176.07:34:38.93#ibcon#wrote, iclass 31, count 0 2006.176.07:34:38.93#ibcon#about to read 3, iclass 31, count 0 2006.176.07:34:38.96#ibcon#read 3, iclass 31, count 0 2006.176.07:34:38.96#ibcon#about to read 4, iclass 31, count 0 2006.176.07:34:38.96#ibcon#read 4, iclass 31, count 0 2006.176.07:34:38.96#ibcon#about to read 5, iclass 31, count 0 2006.176.07:34:38.96#ibcon#read 5, iclass 31, count 0 2006.176.07:34:38.96#ibcon#about to read 6, iclass 31, count 0 2006.176.07:34:38.96#ibcon#read 6, iclass 31, count 0 2006.176.07:34:38.96#ibcon#end of sib2, iclass 31, count 0 2006.176.07:34:38.96#ibcon#*after write, iclass 31, count 0 2006.176.07:34:38.96#ibcon#*before return 0, iclass 31, count 0 2006.176.07:34:38.96#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:38.96#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:38.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.07:34:38.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.07:34:38.96$vc4f8/valo=4,832.99 2006.176.07:34:38.96#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.07:34:38.96#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.07:34:38.96#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:38.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:38.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:38.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:38.96#ibcon#enter wrdev, iclass 33, count 0 2006.176.07:34:38.96#ibcon#first serial, iclass 33, count 0 2006.176.07:34:38.96#ibcon#enter sib2, iclass 33, count 0 2006.176.07:34:38.96#ibcon#flushed, iclass 33, count 0 2006.176.07:34:38.96#ibcon#about to write, iclass 33, count 0 2006.176.07:34:38.96#ibcon#wrote, iclass 33, count 0 2006.176.07:34:38.96#ibcon#about to read 3, iclass 33, count 0 2006.176.07:34:38.98#ibcon#read 3, iclass 33, count 0 2006.176.07:34:38.98#ibcon#about to read 4, iclass 33, count 0 2006.176.07:34:38.98#ibcon#read 4, iclass 33, count 0 2006.176.07:34:38.98#ibcon#about to read 5, iclass 33, count 0 2006.176.07:34:38.98#ibcon#read 5, iclass 33, count 0 2006.176.07:34:38.98#ibcon#about to read 6, iclass 33, count 0 2006.176.07:34:38.98#ibcon#read 6, iclass 33, count 0 2006.176.07:34:38.98#ibcon#end of sib2, iclass 33, count 0 2006.176.07:34:38.98#ibcon#*mode == 0, iclass 33, count 0 2006.176.07:34:38.98#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.07:34:38.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:34:38.98#ibcon#*before write, iclass 33, count 0 2006.176.07:34:38.98#ibcon#enter sib2, iclass 33, count 0 2006.176.07:34:38.98#ibcon#flushed, iclass 33, count 0 2006.176.07:34:38.98#ibcon#about to write, iclass 33, count 0 2006.176.07:34:38.98#ibcon#wrote, iclass 33, count 0 2006.176.07:34:38.98#ibcon#about to read 3, iclass 33, count 0 2006.176.07:34:39.02#ibcon#read 3, iclass 33, count 0 2006.176.07:34:39.02#ibcon#about to read 4, iclass 33, count 0 2006.176.07:34:39.02#ibcon#read 4, iclass 33, count 0 2006.176.07:34:39.02#ibcon#about to read 5, iclass 33, count 0 2006.176.07:34:39.02#ibcon#read 5, iclass 33, count 0 2006.176.07:34:39.02#ibcon#about to read 6, iclass 33, count 0 2006.176.07:34:39.02#ibcon#read 6, iclass 33, count 0 2006.176.07:34:39.02#ibcon#end of sib2, iclass 33, count 0 2006.176.07:34:39.02#ibcon#*after write, iclass 33, count 0 2006.176.07:34:39.02#ibcon#*before return 0, iclass 33, count 0 2006.176.07:34:39.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:39.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:39.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.07:34:39.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.07:34:39.02$vc4f8/va=4,7 2006.176.07:34:39.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.176.07:34:39.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.176.07:34:39.02#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:39.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:39.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:39.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:39.08#ibcon#enter wrdev, iclass 35, count 2 2006.176.07:34:39.08#ibcon#first serial, iclass 35, count 2 2006.176.07:34:39.08#ibcon#enter sib2, iclass 35, count 2 2006.176.07:34:39.08#ibcon#flushed, iclass 35, count 2 2006.176.07:34:39.08#ibcon#about to write, iclass 35, count 2 2006.176.07:34:39.08#ibcon#wrote, iclass 35, count 2 2006.176.07:34:39.08#ibcon#about to read 3, iclass 35, count 2 2006.176.07:34:39.10#ibcon#read 3, iclass 35, count 2 2006.176.07:34:39.10#ibcon#about to read 4, iclass 35, count 2 2006.176.07:34:39.10#ibcon#read 4, iclass 35, count 2 2006.176.07:34:39.10#ibcon#about to read 5, iclass 35, count 2 2006.176.07:34:39.10#ibcon#read 5, iclass 35, count 2 2006.176.07:34:39.10#ibcon#about to read 6, iclass 35, count 2 2006.176.07:34:39.10#ibcon#read 6, iclass 35, count 2 2006.176.07:34:39.10#ibcon#end of sib2, iclass 35, count 2 2006.176.07:34:39.10#ibcon#*mode == 0, iclass 35, count 2 2006.176.07:34:39.10#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.176.07:34:39.10#ibcon#[25=AT04-07\r\n] 2006.176.07:34:39.10#ibcon#*before write, iclass 35, count 2 2006.176.07:34:39.10#ibcon#enter sib2, iclass 35, count 2 2006.176.07:34:39.10#ibcon#flushed, iclass 35, count 2 2006.176.07:34:39.10#ibcon#about to write, iclass 35, count 2 2006.176.07:34:39.10#ibcon#wrote, iclass 35, count 2 2006.176.07:34:39.10#ibcon#about to read 3, iclass 35, count 2 2006.176.07:34:39.13#ibcon#read 3, iclass 35, count 2 2006.176.07:34:39.13#ibcon#about to read 4, iclass 35, count 2 2006.176.07:34:39.13#ibcon#read 4, iclass 35, count 2 2006.176.07:34:39.13#ibcon#about to read 5, iclass 35, count 2 2006.176.07:34:39.13#ibcon#read 5, iclass 35, count 2 2006.176.07:34:39.13#ibcon#about to read 6, iclass 35, count 2 2006.176.07:34:39.13#ibcon#read 6, iclass 35, count 2 2006.176.07:34:39.13#ibcon#end of sib2, iclass 35, count 2 2006.176.07:34:39.13#ibcon#*after write, iclass 35, count 2 2006.176.07:34:39.13#ibcon#*before return 0, iclass 35, count 2 2006.176.07:34:39.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:39.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:39.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.176.07:34:39.13#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:39.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:39.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:39.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:39.25#ibcon#enter wrdev, iclass 35, count 0 2006.176.07:34:39.25#ibcon#first serial, iclass 35, count 0 2006.176.07:34:39.25#ibcon#enter sib2, iclass 35, count 0 2006.176.07:34:39.25#ibcon#flushed, iclass 35, count 0 2006.176.07:34:39.25#ibcon#about to write, iclass 35, count 0 2006.176.07:34:39.25#ibcon#wrote, iclass 35, count 0 2006.176.07:34:39.25#ibcon#about to read 3, iclass 35, count 0 2006.176.07:34:39.27#ibcon#read 3, iclass 35, count 0 2006.176.07:34:39.27#ibcon#about to read 4, iclass 35, count 0 2006.176.07:34:39.27#ibcon#read 4, iclass 35, count 0 2006.176.07:34:39.27#ibcon#about to read 5, iclass 35, count 0 2006.176.07:34:39.27#ibcon#read 5, iclass 35, count 0 2006.176.07:34:39.27#ibcon#about to read 6, iclass 35, count 0 2006.176.07:34:39.27#ibcon#read 6, iclass 35, count 0 2006.176.07:34:39.27#ibcon#end of sib2, iclass 35, count 0 2006.176.07:34:39.27#ibcon#*mode == 0, iclass 35, count 0 2006.176.07:34:39.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.07:34:39.27#ibcon#[25=USB\r\n] 2006.176.07:34:39.27#ibcon#*before write, iclass 35, count 0 2006.176.07:34:39.27#ibcon#enter sib2, iclass 35, count 0 2006.176.07:34:39.27#ibcon#flushed, iclass 35, count 0 2006.176.07:34:39.27#ibcon#about to write, iclass 35, count 0 2006.176.07:34:39.27#ibcon#wrote, iclass 35, count 0 2006.176.07:34:39.27#ibcon#about to read 3, iclass 35, count 0 2006.176.07:34:39.30#ibcon#read 3, iclass 35, count 0 2006.176.07:34:39.30#ibcon#about to read 4, iclass 35, count 0 2006.176.07:34:39.30#ibcon#read 4, iclass 35, count 0 2006.176.07:34:39.30#ibcon#about to read 5, iclass 35, count 0 2006.176.07:34:39.30#ibcon#read 5, iclass 35, count 0 2006.176.07:34:39.30#ibcon#about to read 6, iclass 35, count 0 2006.176.07:34:39.30#ibcon#read 6, iclass 35, count 0 2006.176.07:34:39.30#ibcon#end of sib2, iclass 35, count 0 2006.176.07:34:39.30#ibcon#*after write, iclass 35, count 0 2006.176.07:34:39.30#ibcon#*before return 0, iclass 35, count 0 2006.176.07:34:39.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:39.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:39.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.07:34:39.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.07:34:39.30$vc4f8/valo=5,652.99 2006.176.07:34:39.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.176.07:34:39.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.176.07:34:39.30#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:39.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:39.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:39.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:39.30#ibcon#enter wrdev, iclass 37, count 0 2006.176.07:34:39.30#ibcon#first serial, iclass 37, count 0 2006.176.07:34:39.30#ibcon#enter sib2, iclass 37, count 0 2006.176.07:34:39.30#ibcon#flushed, iclass 37, count 0 2006.176.07:34:39.30#ibcon#about to write, iclass 37, count 0 2006.176.07:34:39.30#ibcon#wrote, iclass 37, count 0 2006.176.07:34:39.30#ibcon#about to read 3, iclass 37, count 0 2006.176.07:34:39.32#ibcon#read 3, iclass 37, count 0 2006.176.07:34:39.32#ibcon#about to read 4, iclass 37, count 0 2006.176.07:34:39.32#ibcon#read 4, iclass 37, count 0 2006.176.07:34:39.32#ibcon#about to read 5, iclass 37, count 0 2006.176.07:34:39.32#ibcon#read 5, iclass 37, count 0 2006.176.07:34:39.32#ibcon#about to read 6, iclass 37, count 0 2006.176.07:34:39.32#ibcon#read 6, iclass 37, count 0 2006.176.07:34:39.32#ibcon#end of sib2, iclass 37, count 0 2006.176.07:34:39.32#ibcon#*mode == 0, iclass 37, count 0 2006.176.07:34:39.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.07:34:39.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:34:39.32#ibcon#*before write, iclass 37, count 0 2006.176.07:34:39.32#ibcon#enter sib2, iclass 37, count 0 2006.176.07:34:39.32#ibcon#flushed, iclass 37, count 0 2006.176.07:34:39.32#ibcon#about to write, iclass 37, count 0 2006.176.07:34:39.32#ibcon#wrote, iclass 37, count 0 2006.176.07:34:39.32#ibcon#about to read 3, iclass 37, count 0 2006.176.07:34:39.36#ibcon#read 3, iclass 37, count 0 2006.176.07:34:39.36#ibcon#about to read 4, iclass 37, count 0 2006.176.07:34:39.36#ibcon#read 4, iclass 37, count 0 2006.176.07:34:39.36#ibcon#about to read 5, iclass 37, count 0 2006.176.07:34:39.36#ibcon#read 5, iclass 37, count 0 2006.176.07:34:39.36#ibcon#about to read 6, iclass 37, count 0 2006.176.07:34:39.36#ibcon#read 6, iclass 37, count 0 2006.176.07:34:39.36#ibcon#end of sib2, iclass 37, count 0 2006.176.07:34:39.36#ibcon#*after write, iclass 37, count 0 2006.176.07:34:39.36#ibcon#*before return 0, iclass 37, count 0 2006.176.07:34:39.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:39.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:39.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.07:34:39.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.07:34:39.36$vc4f8/va=5,7 2006.176.07:34:39.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.176.07:34:39.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.176.07:34:39.36#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:39.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:39.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:39.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:39.42#ibcon#enter wrdev, iclass 39, count 2 2006.176.07:34:39.42#ibcon#first serial, iclass 39, count 2 2006.176.07:34:39.42#ibcon#enter sib2, iclass 39, count 2 2006.176.07:34:39.42#ibcon#flushed, iclass 39, count 2 2006.176.07:34:39.42#ibcon#about to write, iclass 39, count 2 2006.176.07:34:39.42#ibcon#wrote, iclass 39, count 2 2006.176.07:34:39.42#ibcon#about to read 3, iclass 39, count 2 2006.176.07:34:39.44#ibcon#read 3, iclass 39, count 2 2006.176.07:34:39.44#ibcon#about to read 4, iclass 39, count 2 2006.176.07:34:39.44#ibcon#read 4, iclass 39, count 2 2006.176.07:34:39.44#ibcon#about to read 5, iclass 39, count 2 2006.176.07:34:39.44#ibcon#read 5, iclass 39, count 2 2006.176.07:34:39.44#ibcon#about to read 6, iclass 39, count 2 2006.176.07:34:39.44#ibcon#read 6, iclass 39, count 2 2006.176.07:34:39.44#ibcon#end of sib2, iclass 39, count 2 2006.176.07:34:39.44#ibcon#*mode == 0, iclass 39, count 2 2006.176.07:34:39.44#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.176.07:34:39.44#ibcon#[25=AT05-07\r\n] 2006.176.07:34:39.44#ibcon#*before write, iclass 39, count 2 2006.176.07:34:39.44#ibcon#enter sib2, iclass 39, count 2 2006.176.07:34:39.44#ibcon#flushed, iclass 39, count 2 2006.176.07:34:39.44#ibcon#about to write, iclass 39, count 2 2006.176.07:34:39.44#ibcon#wrote, iclass 39, count 2 2006.176.07:34:39.44#ibcon#about to read 3, iclass 39, count 2 2006.176.07:34:39.47#ibcon#read 3, iclass 39, count 2 2006.176.07:34:39.47#ibcon#about to read 4, iclass 39, count 2 2006.176.07:34:39.47#ibcon#read 4, iclass 39, count 2 2006.176.07:34:39.47#ibcon#about to read 5, iclass 39, count 2 2006.176.07:34:39.47#ibcon#read 5, iclass 39, count 2 2006.176.07:34:39.47#ibcon#about to read 6, iclass 39, count 2 2006.176.07:34:39.47#ibcon#read 6, iclass 39, count 2 2006.176.07:34:39.47#ibcon#end of sib2, iclass 39, count 2 2006.176.07:34:39.47#ibcon#*after write, iclass 39, count 2 2006.176.07:34:39.47#ibcon#*before return 0, iclass 39, count 2 2006.176.07:34:39.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:39.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:39.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.176.07:34:39.47#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:39.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:39.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:39.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:39.59#ibcon#enter wrdev, iclass 39, count 0 2006.176.07:34:39.59#ibcon#first serial, iclass 39, count 0 2006.176.07:34:39.59#ibcon#enter sib2, iclass 39, count 0 2006.176.07:34:39.59#ibcon#flushed, iclass 39, count 0 2006.176.07:34:39.59#ibcon#about to write, iclass 39, count 0 2006.176.07:34:39.59#ibcon#wrote, iclass 39, count 0 2006.176.07:34:39.59#ibcon#about to read 3, iclass 39, count 0 2006.176.07:34:39.61#ibcon#read 3, iclass 39, count 0 2006.176.07:34:39.61#ibcon#about to read 4, iclass 39, count 0 2006.176.07:34:39.61#ibcon#read 4, iclass 39, count 0 2006.176.07:34:39.61#ibcon#about to read 5, iclass 39, count 0 2006.176.07:34:39.61#ibcon#read 5, iclass 39, count 0 2006.176.07:34:39.61#ibcon#about to read 6, iclass 39, count 0 2006.176.07:34:39.61#ibcon#read 6, iclass 39, count 0 2006.176.07:34:39.61#ibcon#end of sib2, iclass 39, count 0 2006.176.07:34:39.61#ibcon#*mode == 0, iclass 39, count 0 2006.176.07:34:39.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.07:34:39.61#ibcon#[25=USB\r\n] 2006.176.07:34:39.61#ibcon#*before write, iclass 39, count 0 2006.176.07:34:39.61#ibcon#enter sib2, iclass 39, count 0 2006.176.07:34:39.61#ibcon#flushed, iclass 39, count 0 2006.176.07:34:39.61#ibcon#about to write, iclass 39, count 0 2006.176.07:34:39.61#ibcon#wrote, iclass 39, count 0 2006.176.07:34:39.61#ibcon#about to read 3, iclass 39, count 0 2006.176.07:34:39.64#ibcon#read 3, iclass 39, count 0 2006.176.07:34:39.64#ibcon#about to read 4, iclass 39, count 0 2006.176.07:34:39.64#ibcon#read 4, iclass 39, count 0 2006.176.07:34:39.64#ibcon#about to read 5, iclass 39, count 0 2006.176.07:34:39.64#ibcon#read 5, iclass 39, count 0 2006.176.07:34:39.64#ibcon#about to read 6, iclass 39, count 0 2006.176.07:34:39.64#ibcon#read 6, iclass 39, count 0 2006.176.07:34:39.64#ibcon#end of sib2, iclass 39, count 0 2006.176.07:34:39.64#ibcon#*after write, iclass 39, count 0 2006.176.07:34:39.64#ibcon#*before return 0, iclass 39, count 0 2006.176.07:34:39.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:39.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:39.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.07:34:39.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.07:34:39.64$vc4f8/valo=6,772.99 2006.176.07:34:39.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.07:34:39.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.07:34:39.64#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:39.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:39.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:39.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:39.64#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:34:39.64#ibcon#first serial, iclass 3, count 0 2006.176.07:34:39.64#ibcon#enter sib2, iclass 3, count 0 2006.176.07:34:39.64#ibcon#flushed, iclass 3, count 0 2006.176.07:34:39.64#ibcon#about to write, iclass 3, count 0 2006.176.07:34:39.64#ibcon#wrote, iclass 3, count 0 2006.176.07:34:39.64#ibcon#about to read 3, iclass 3, count 0 2006.176.07:34:39.66#ibcon#read 3, iclass 3, count 0 2006.176.07:34:39.66#ibcon#about to read 4, iclass 3, count 0 2006.176.07:34:39.66#ibcon#read 4, iclass 3, count 0 2006.176.07:34:39.66#ibcon#about to read 5, iclass 3, count 0 2006.176.07:34:39.66#ibcon#read 5, iclass 3, count 0 2006.176.07:34:39.66#ibcon#about to read 6, iclass 3, count 0 2006.176.07:34:39.66#ibcon#read 6, iclass 3, count 0 2006.176.07:34:39.66#ibcon#end of sib2, iclass 3, count 0 2006.176.07:34:39.66#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:34:39.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:34:39.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:34:39.66#ibcon#*before write, iclass 3, count 0 2006.176.07:34:39.66#ibcon#enter sib2, iclass 3, count 0 2006.176.07:34:39.66#ibcon#flushed, iclass 3, count 0 2006.176.07:34:39.66#ibcon#about to write, iclass 3, count 0 2006.176.07:34:39.66#ibcon#wrote, iclass 3, count 0 2006.176.07:34:39.66#ibcon#about to read 3, iclass 3, count 0 2006.176.07:34:39.70#ibcon#read 3, iclass 3, count 0 2006.176.07:34:39.70#ibcon#about to read 4, iclass 3, count 0 2006.176.07:34:39.70#ibcon#read 4, iclass 3, count 0 2006.176.07:34:39.70#ibcon#about to read 5, iclass 3, count 0 2006.176.07:34:39.70#ibcon#read 5, iclass 3, count 0 2006.176.07:34:39.70#ibcon#about to read 6, iclass 3, count 0 2006.176.07:34:39.70#ibcon#read 6, iclass 3, count 0 2006.176.07:34:39.70#ibcon#end of sib2, iclass 3, count 0 2006.176.07:34:39.70#ibcon#*after write, iclass 3, count 0 2006.176.07:34:39.70#ibcon#*before return 0, iclass 3, count 0 2006.176.07:34:39.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:39.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:39.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:34:39.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:34:39.70$vc4f8/va=6,6 2006.176.07:34:39.70#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.176.07:34:39.70#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.176.07:34:39.70#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:39.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:34:39.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:34:39.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:34:39.76#ibcon#enter wrdev, iclass 5, count 2 2006.176.07:34:39.76#ibcon#first serial, iclass 5, count 2 2006.176.07:34:39.76#ibcon#enter sib2, iclass 5, count 2 2006.176.07:34:39.76#ibcon#flushed, iclass 5, count 2 2006.176.07:34:39.76#ibcon#about to write, iclass 5, count 2 2006.176.07:34:39.76#ibcon#wrote, iclass 5, count 2 2006.176.07:34:39.76#ibcon#about to read 3, iclass 5, count 2 2006.176.07:34:39.78#ibcon#read 3, iclass 5, count 2 2006.176.07:34:39.78#ibcon#about to read 4, iclass 5, count 2 2006.176.07:34:39.78#ibcon#read 4, iclass 5, count 2 2006.176.07:34:39.78#ibcon#about to read 5, iclass 5, count 2 2006.176.07:34:39.78#ibcon#read 5, iclass 5, count 2 2006.176.07:34:39.78#ibcon#about to read 6, iclass 5, count 2 2006.176.07:34:39.78#ibcon#read 6, iclass 5, count 2 2006.176.07:34:39.78#ibcon#end of sib2, iclass 5, count 2 2006.176.07:34:39.78#ibcon#*mode == 0, iclass 5, count 2 2006.176.07:34:39.78#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.176.07:34:39.78#ibcon#[25=AT06-06\r\n] 2006.176.07:34:39.78#ibcon#*before write, iclass 5, count 2 2006.176.07:34:39.78#ibcon#enter sib2, iclass 5, count 2 2006.176.07:34:39.78#ibcon#flushed, iclass 5, count 2 2006.176.07:34:39.78#ibcon#about to write, iclass 5, count 2 2006.176.07:34:39.78#ibcon#wrote, iclass 5, count 2 2006.176.07:34:39.78#ibcon#about to read 3, iclass 5, count 2 2006.176.07:34:39.81#ibcon#read 3, iclass 5, count 2 2006.176.07:34:39.81#ibcon#about to read 4, iclass 5, count 2 2006.176.07:34:39.81#ibcon#read 4, iclass 5, count 2 2006.176.07:34:39.81#ibcon#about to read 5, iclass 5, count 2 2006.176.07:34:39.81#ibcon#read 5, iclass 5, count 2 2006.176.07:34:39.81#ibcon#about to read 6, iclass 5, count 2 2006.176.07:34:39.81#ibcon#read 6, iclass 5, count 2 2006.176.07:34:39.81#ibcon#end of sib2, iclass 5, count 2 2006.176.07:34:39.81#ibcon#*after write, iclass 5, count 2 2006.176.07:34:39.81#ibcon#*before return 0, iclass 5, count 2 2006.176.07:34:39.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:34:39.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:34:39.81#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.176.07:34:39.81#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:39.81#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:34:39.93#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:34:39.93#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:34:39.93#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:34:39.93#ibcon#first serial, iclass 5, count 0 2006.176.07:34:39.93#ibcon#enter sib2, iclass 5, count 0 2006.176.07:34:39.93#ibcon#flushed, iclass 5, count 0 2006.176.07:34:39.93#ibcon#about to write, iclass 5, count 0 2006.176.07:34:39.93#ibcon#wrote, iclass 5, count 0 2006.176.07:34:39.93#ibcon#about to read 3, iclass 5, count 0 2006.176.07:34:39.95#ibcon#read 3, iclass 5, count 0 2006.176.07:34:39.95#ibcon#about to read 4, iclass 5, count 0 2006.176.07:34:39.95#ibcon#read 4, iclass 5, count 0 2006.176.07:34:39.95#ibcon#about to read 5, iclass 5, count 0 2006.176.07:34:39.95#ibcon#read 5, iclass 5, count 0 2006.176.07:34:39.95#ibcon#about to read 6, iclass 5, count 0 2006.176.07:34:39.95#ibcon#read 6, iclass 5, count 0 2006.176.07:34:39.95#ibcon#end of sib2, iclass 5, count 0 2006.176.07:34:39.95#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:34:39.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:34:39.95#ibcon#[25=USB\r\n] 2006.176.07:34:39.95#ibcon#*before write, iclass 5, count 0 2006.176.07:34:39.95#ibcon#enter sib2, iclass 5, count 0 2006.176.07:34:39.95#ibcon#flushed, iclass 5, count 0 2006.176.07:34:39.95#ibcon#about to write, iclass 5, count 0 2006.176.07:34:39.95#ibcon#wrote, iclass 5, count 0 2006.176.07:34:39.95#ibcon#about to read 3, iclass 5, count 0 2006.176.07:34:39.98#ibcon#read 3, iclass 5, count 0 2006.176.07:34:39.98#ibcon#about to read 4, iclass 5, count 0 2006.176.07:34:39.98#ibcon#read 4, iclass 5, count 0 2006.176.07:34:39.98#ibcon#about to read 5, iclass 5, count 0 2006.176.07:34:39.98#ibcon#read 5, iclass 5, count 0 2006.176.07:34:39.98#ibcon#about to read 6, iclass 5, count 0 2006.176.07:34:39.98#ibcon#read 6, iclass 5, count 0 2006.176.07:34:39.98#ibcon#end of sib2, iclass 5, count 0 2006.176.07:34:39.98#ibcon#*after write, iclass 5, count 0 2006.176.07:34:39.98#ibcon#*before return 0, iclass 5, count 0 2006.176.07:34:39.98#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:34:39.98#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:34:39.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:34:39.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:34:39.98$vc4f8/valo=7,832.99 2006.176.07:34:39.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.07:34:39.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.07:34:39.98#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:39.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:34:39.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:34:39.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:34:39.98#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:34:39.98#ibcon#first serial, iclass 7, count 0 2006.176.07:34:39.98#ibcon#enter sib2, iclass 7, count 0 2006.176.07:34:39.98#ibcon#flushed, iclass 7, count 0 2006.176.07:34:39.98#ibcon#about to write, iclass 7, count 0 2006.176.07:34:39.98#ibcon#wrote, iclass 7, count 0 2006.176.07:34:39.98#ibcon#about to read 3, iclass 7, count 0 2006.176.07:34:40.00#ibcon#read 3, iclass 7, count 0 2006.176.07:34:40.00#ibcon#about to read 4, iclass 7, count 0 2006.176.07:34:40.00#ibcon#read 4, iclass 7, count 0 2006.176.07:34:40.00#ibcon#about to read 5, iclass 7, count 0 2006.176.07:34:40.00#ibcon#read 5, iclass 7, count 0 2006.176.07:34:40.00#ibcon#about to read 6, iclass 7, count 0 2006.176.07:34:40.00#ibcon#read 6, iclass 7, count 0 2006.176.07:34:40.00#ibcon#end of sib2, iclass 7, count 0 2006.176.07:34:40.00#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:34:40.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:34:40.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:34:40.00#ibcon#*before write, iclass 7, count 0 2006.176.07:34:40.00#ibcon#enter sib2, iclass 7, count 0 2006.176.07:34:40.00#ibcon#flushed, iclass 7, count 0 2006.176.07:34:40.00#ibcon#about to write, iclass 7, count 0 2006.176.07:34:40.00#ibcon#wrote, iclass 7, count 0 2006.176.07:34:40.00#ibcon#about to read 3, iclass 7, count 0 2006.176.07:34:40.04#ibcon#read 3, iclass 7, count 0 2006.176.07:34:40.04#ibcon#about to read 4, iclass 7, count 0 2006.176.07:34:40.04#ibcon#read 4, iclass 7, count 0 2006.176.07:34:40.04#ibcon#about to read 5, iclass 7, count 0 2006.176.07:34:40.04#ibcon#read 5, iclass 7, count 0 2006.176.07:34:40.04#ibcon#about to read 6, iclass 7, count 0 2006.176.07:34:40.04#ibcon#read 6, iclass 7, count 0 2006.176.07:34:40.04#ibcon#end of sib2, iclass 7, count 0 2006.176.07:34:40.04#ibcon#*after write, iclass 7, count 0 2006.176.07:34:40.04#ibcon#*before return 0, iclass 7, count 0 2006.176.07:34:40.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:34:40.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:34:40.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:34:40.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:34:40.04$vc4f8/va=7,6 2006.176.07:34:40.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.176.07:34:40.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.176.07:34:40.04#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:40.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:34:40.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:34:40.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:34:40.10#ibcon#enter wrdev, iclass 11, count 2 2006.176.07:34:40.10#ibcon#first serial, iclass 11, count 2 2006.176.07:34:40.10#ibcon#enter sib2, iclass 11, count 2 2006.176.07:34:40.10#ibcon#flushed, iclass 11, count 2 2006.176.07:34:40.10#ibcon#about to write, iclass 11, count 2 2006.176.07:34:40.10#ibcon#wrote, iclass 11, count 2 2006.176.07:34:40.10#ibcon#about to read 3, iclass 11, count 2 2006.176.07:34:40.12#ibcon#read 3, iclass 11, count 2 2006.176.07:34:40.12#ibcon#about to read 4, iclass 11, count 2 2006.176.07:34:40.12#ibcon#read 4, iclass 11, count 2 2006.176.07:34:40.12#ibcon#about to read 5, iclass 11, count 2 2006.176.07:34:40.12#ibcon#read 5, iclass 11, count 2 2006.176.07:34:40.12#ibcon#about to read 6, iclass 11, count 2 2006.176.07:34:40.12#ibcon#read 6, iclass 11, count 2 2006.176.07:34:40.12#ibcon#end of sib2, iclass 11, count 2 2006.176.07:34:40.12#ibcon#*mode == 0, iclass 11, count 2 2006.176.07:34:40.12#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.176.07:34:40.12#ibcon#[25=AT07-06\r\n] 2006.176.07:34:40.12#ibcon#*before write, iclass 11, count 2 2006.176.07:34:40.12#ibcon#enter sib2, iclass 11, count 2 2006.176.07:34:40.12#ibcon#flushed, iclass 11, count 2 2006.176.07:34:40.12#ibcon#about to write, iclass 11, count 2 2006.176.07:34:40.12#ibcon#wrote, iclass 11, count 2 2006.176.07:34:40.12#ibcon#about to read 3, iclass 11, count 2 2006.176.07:34:40.15#ibcon#read 3, iclass 11, count 2 2006.176.07:34:40.15#ibcon#about to read 4, iclass 11, count 2 2006.176.07:34:40.15#ibcon#read 4, iclass 11, count 2 2006.176.07:34:40.15#ibcon#about to read 5, iclass 11, count 2 2006.176.07:34:40.15#ibcon#read 5, iclass 11, count 2 2006.176.07:34:40.15#ibcon#about to read 6, iclass 11, count 2 2006.176.07:34:40.15#ibcon#read 6, iclass 11, count 2 2006.176.07:34:40.15#ibcon#end of sib2, iclass 11, count 2 2006.176.07:34:40.15#ibcon#*after write, iclass 11, count 2 2006.176.07:34:40.15#ibcon#*before return 0, iclass 11, count 2 2006.176.07:34:40.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:34:40.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:34:40.15#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.176.07:34:40.15#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:40.15#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:34:40.27#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:34:40.27#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:34:40.27#ibcon#enter wrdev, iclass 11, count 0 2006.176.07:34:40.27#ibcon#first serial, iclass 11, count 0 2006.176.07:34:40.27#ibcon#enter sib2, iclass 11, count 0 2006.176.07:34:40.27#ibcon#flushed, iclass 11, count 0 2006.176.07:34:40.27#ibcon#about to write, iclass 11, count 0 2006.176.07:34:40.27#ibcon#wrote, iclass 11, count 0 2006.176.07:34:40.27#ibcon#about to read 3, iclass 11, count 0 2006.176.07:34:40.29#ibcon#read 3, iclass 11, count 0 2006.176.07:34:40.29#ibcon#about to read 4, iclass 11, count 0 2006.176.07:34:40.29#ibcon#read 4, iclass 11, count 0 2006.176.07:34:40.29#ibcon#about to read 5, iclass 11, count 0 2006.176.07:34:40.29#ibcon#read 5, iclass 11, count 0 2006.176.07:34:40.29#ibcon#about to read 6, iclass 11, count 0 2006.176.07:34:40.29#ibcon#read 6, iclass 11, count 0 2006.176.07:34:40.29#ibcon#end of sib2, iclass 11, count 0 2006.176.07:34:40.29#ibcon#*mode == 0, iclass 11, count 0 2006.176.07:34:40.29#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.07:34:40.29#ibcon#[25=USB\r\n] 2006.176.07:34:40.29#ibcon#*before write, iclass 11, count 0 2006.176.07:34:40.29#ibcon#enter sib2, iclass 11, count 0 2006.176.07:34:40.29#ibcon#flushed, iclass 11, count 0 2006.176.07:34:40.29#ibcon#about to write, iclass 11, count 0 2006.176.07:34:40.29#ibcon#wrote, iclass 11, count 0 2006.176.07:34:40.29#ibcon#about to read 3, iclass 11, count 0 2006.176.07:34:40.32#ibcon#read 3, iclass 11, count 0 2006.176.07:34:40.32#ibcon#about to read 4, iclass 11, count 0 2006.176.07:34:40.32#ibcon#read 4, iclass 11, count 0 2006.176.07:34:40.32#ibcon#about to read 5, iclass 11, count 0 2006.176.07:34:40.32#ibcon#read 5, iclass 11, count 0 2006.176.07:34:40.32#ibcon#about to read 6, iclass 11, count 0 2006.176.07:34:40.32#ibcon#read 6, iclass 11, count 0 2006.176.07:34:40.32#ibcon#end of sib2, iclass 11, count 0 2006.176.07:34:40.32#ibcon#*after write, iclass 11, count 0 2006.176.07:34:40.32#ibcon#*before return 0, iclass 11, count 0 2006.176.07:34:40.32#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:34:40.32#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:34:40.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.07:34:40.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.07:34:40.32$vc4f8/valo=8,852.99 2006.176.07:34:40.32#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.07:34:40.32#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.07:34:40.32#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:40.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:34:40.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:34:40.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:34:40.32#ibcon#enter wrdev, iclass 13, count 0 2006.176.07:34:40.32#ibcon#first serial, iclass 13, count 0 2006.176.07:34:40.32#ibcon#enter sib2, iclass 13, count 0 2006.176.07:34:40.32#ibcon#flushed, iclass 13, count 0 2006.176.07:34:40.32#ibcon#about to write, iclass 13, count 0 2006.176.07:34:40.32#ibcon#wrote, iclass 13, count 0 2006.176.07:34:40.32#ibcon#about to read 3, iclass 13, count 0 2006.176.07:34:40.34#ibcon#read 3, iclass 13, count 0 2006.176.07:34:40.34#ibcon#about to read 4, iclass 13, count 0 2006.176.07:34:40.34#ibcon#read 4, iclass 13, count 0 2006.176.07:34:40.34#ibcon#about to read 5, iclass 13, count 0 2006.176.07:34:40.34#ibcon#read 5, iclass 13, count 0 2006.176.07:34:40.34#ibcon#about to read 6, iclass 13, count 0 2006.176.07:34:40.34#ibcon#read 6, iclass 13, count 0 2006.176.07:34:40.34#ibcon#end of sib2, iclass 13, count 0 2006.176.07:34:40.34#ibcon#*mode == 0, iclass 13, count 0 2006.176.07:34:40.34#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.07:34:40.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:34:40.34#ibcon#*before write, iclass 13, count 0 2006.176.07:34:40.34#ibcon#enter sib2, iclass 13, count 0 2006.176.07:34:40.34#ibcon#flushed, iclass 13, count 0 2006.176.07:34:40.34#ibcon#about to write, iclass 13, count 0 2006.176.07:34:40.34#ibcon#wrote, iclass 13, count 0 2006.176.07:34:40.34#ibcon#about to read 3, iclass 13, count 0 2006.176.07:34:40.38#ibcon#read 3, iclass 13, count 0 2006.176.07:34:40.38#ibcon#about to read 4, iclass 13, count 0 2006.176.07:34:40.38#ibcon#read 4, iclass 13, count 0 2006.176.07:34:40.38#ibcon#about to read 5, iclass 13, count 0 2006.176.07:34:40.38#ibcon#read 5, iclass 13, count 0 2006.176.07:34:40.38#ibcon#about to read 6, iclass 13, count 0 2006.176.07:34:40.38#ibcon#read 6, iclass 13, count 0 2006.176.07:34:40.38#ibcon#end of sib2, iclass 13, count 0 2006.176.07:34:40.38#ibcon#*after write, iclass 13, count 0 2006.176.07:34:40.38#ibcon#*before return 0, iclass 13, count 0 2006.176.07:34:40.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:34:40.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:34:40.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.07:34:40.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.07:34:40.38$vc4f8/va=8,6 2006.176.07:34:40.38#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.176.07:34:40.38#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.176.07:34:40.38#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:40.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:34:40.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:34:40.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:34:40.44#ibcon#enter wrdev, iclass 15, count 2 2006.176.07:34:40.44#ibcon#first serial, iclass 15, count 2 2006.176.07:34:40.44#ibcon#enter sib2, iclass 15, count 2 2006.176.07:34:40.44#ibcon#flushed, iclass 15, count 2 2006.176.07:34:40.44#ibcon#about to write, iclass 15, count 2 2006.176.07:34:40.44#ibcon#wrote, iclass 15, count 2 2006.176.07:34:40.44#ibcon#about to read 3, iclass 15, count 2 2006.176.07:34:40.46#ibcon#read 3, iclass 15, count 2 2006.176.07:34:40.46#ibcon#about to read 4, iclass 15, count 2 2006.176.07:34:40.46#ibcon#read 4, iclass 15, count 2 2006.176.07:34:40.46#ibcon#about to read 5, iclass 15, count 2 2006.176.07:34:40.46#ibcon#read 5, iclass 15, count 2 2006.176.07:34:40.46#ibcon#about to read 6, iclass 15, count 2 2006.176.07:34:40.46#ibcon#read 6, iclass 15, count 2 2006.176.07:34:40.46#ibcon#end of sib2, iclass 15, count 2 2006.176.07:34:40.46#ibcon#*mode == 0, iclass 15, count 2 2006.176.07:34:40.46#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.176.07:34:40.46#ibcon#[25=AT08-06\r\n] 2006.176.07:34:40.46#ibcon#*before write, iclass 15, count 2 2006.176.07:34:40.46#ibcon#enter sib2, iclass 15, count 2 2006.176.07:34:40.46#ibcon#flushed, iclass 15, count 2 2006.176.07:34:40.46#ibcon#about to write, iclass 15, count 2 2006.176.07:34:40.46#ibcon#wrote, iclass 15, count 2 2006.176.07:34:40.46#ibcon#about to read 3, iclass 15, count 2 2006.176.07:34:40.49#ibcon#read 3, iclass 15, count 2 2006.176.07:34:40.49#ibcon#about to read 4, iclass 15, count 2 2006.176.07:34:40.49#ibcon#read 4, iclass 15, count 2 2006.176.07:34:40.49#ibcon#about to read 5, iclass 15, count 2 2006.176.07:34:40.49#ibcon#read 5, iclass 15, count 2 2006.176.07:34:40.49#ibcon#about to read 6, iclass 15, count 2 2006.176.07:34:40.49#ibcon#read 6, iclass 15, count 2 2006.176.07:34:40.49#ibcon#end of sib2, iclass 15, count 2 2006.176.07:34:40.49#ibcon#*after write, iclass 15, count 2 2006.176.07:34:40.49#ibcon#*before return 0, iclass 15, count 2 2006.176.07:34:40.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:34:40.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:34:40.49#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.176.07:34:40.49#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:40.49#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:34:40.61#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:34:40.61#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:34:40.61#ibcon#enter wrdev, iclass 15, count 0 2006.176.07:34:40.61#ibcon#first serial, iclass 15, count 0 2006.176.07:34:40.61#ibcon#enter sib2, iclass 15, count 0 2006.176.07:34:40.61#ibcon#flushed, iclass 15, count 0 2006.176.07:34:40.61#ibcon#about to write, iclass 15, count 0 2006.176.07:34:40.61#ibcon#wrote, iclass 15, count 0 2006.176.07:34:40.61#ibcon#about to read 3, iclass 15, count 0 2006.176.07:34:40.63#ibcon#read 3, iclass 15, count 0 2006.176.07:34:40.63#ibcon#about to read 4, iclass 15, count 0 2006.176.07:34:40.63#ibcon#read 4, iclass 15, count 0 2006.176.07:34:40.63#ibcon#about to read 5, iclass 15, count 0 2006.176.07:34:40.63#ibcon#read 5, iclass 15, count 0 2006.176.07:34:40.63#ibcon#about to read 6, iclass 15, count 0 2006.176.07:34:40.63#ibcon#read 6, iclass 15, count 0 2006.176.07:34:40.63#ibcon#end of sib2, iclass 15, count 0 2006.176.07:34:40.63#ibcon#*mode == 0, iclass 15, count 0 2006.176.07:34:40.63#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.07:34:40.63#ibcon#[25=USB\r\n] 2006.176.07:34:40.63#ibcon#*before write, iclass 15, count 0 2006.176.07:34:40.63#ibcon#enter sib2, iclass 15, count 0 2006.176.07:34:40.63#ibcon#flushed, iclass 15, count 0 2006.176.07:34:40.63#ibcon#about to write, iclass 15, count 0 2006.176.07:34:40.63#ibcon#wrote, iclass 15, count 0 2006.176.07:34:40.63#ibcon#about to read 3, iclass 15, count 0 2006.176.07:34:40.66#ibcon#read 3, iclass 15, count 0 2006.176.07:34:40.66#ibcon#about to read 4, iclass 15, count 0 2006.176.07:34:40.66#ibcon#read 4, iclass 15, count 0 2006.176.07:34:40.66#ibcon#about to read 5, iclass 15, count 0 2006.176.07:34:40.66#ibcon#read 5, iclass 15, count 0 2006.176.07:34:40.66#ibcon#about to read 6, iclass 15, count 0 2006.176.07:34:40.66#ibcon#read 6, iclass 15, count 0 2006.176.07:34:40.66#ibcon#end of sib2, iclass 15, count 0 2006.176.07:34:40.66#ibcon#*after write, iclass 15, count 0 2006.176.07:34:40.66#ibcon#*before return 0, iclass 15, count 0 2006.176.07:34:40.66#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:34:40.66#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:34:40.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.07:34:40.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.07:34:40.66$vc4f8/vblo=1,632.99 2006.176.07:34:40.66#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.07:34:40.66#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.07:34:40.66#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:40.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:34:40.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:34:40.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:34:40.66#ibcon#enter wrdev, iclass 17, count 0 2006.176.07:34:40.66#ibcon#first serial, iclass 17, count 0 2006.176.07:34:40.66#ibcon#enter sib2, iclass 17, count 0 2006.176.07:34:40.66#ibcon#flushed, iclass 17, count 0 2006.176.07:34:40.66#ibcon#about to write, iclass 17, count 0 2006.176.07:34:40.66#ibcon#wrote, iclass 17, count 0 2006.176.07:34:40.66#ibcon#about to read 3, iclass 17, count 0 2006.176.07:34:40.68#ibcon#read 3, iclass 17, count 0 2006.176.07:34:40.68#ibcon#about to read 4, iclass 17, count 0 2006.176.07:34:40.68#ibcon#read 4, iclass 17, count 0 2006.176.07:34:40.68#ibcon#about to read 5, iclass 17, count 0 2006.176.07:34:40.68#ibcon#read 5, iclass 17, count 0 2006.176.07:34:40.68#ibcon#about to read 6, iclass 17, count 0 2006.176.07:34:40.68#ibcon#read 6, iclass 17, count 0 2006.176.07:34:40.68#ibcon#end of sib2, iclass 17, count 0 2006.176.07:34:40.68#ibcon#*mode == 0, iclass 17, count 0 2006.176.07:34:40.68#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.07:34:40.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:34:40.68#ibcon#*before write, iclass 17, count 0 2006.176.07:34:40.68#ibcon#enter sib2, iclass 17, count 0 2006.176.07:34:40.68#ibcon#flushed, iclass 17, count 0 2006.176.07:34:40.68#ibcon#about to write, iclass 17, count 0 2006.176.07:34:40.68#ibcon#wrote, iclass 17, count 0 2006.176.07:34:40.68#ibcon#about to read 3, iclass 17, count 0 2006.176.07:34:40.72#ibcon#read 3, iclass 17, count 0 2006.176.07:34:40.72#ibcon#about to read 4, iclass 17, count 0 2006.176.07:34:40.72#ibcon#read 4, iclass 17, count 0 2006.176.07:34:40.72#ibcon#about to read 5, iclass 17, count 0 2006.176.07:34:40.72#ibcon#read 5, iclass 17, count 0 2006.176.07:34:40.72#ibcon#about to read 6, iclass 17, count 0 2006.176.07:34:40.72#ibcon#read 6, iclass 17, count 0 2006.176.07:34:40.72#ibcon#end of sib2, iclass 17, count 0 2006.176.07:34:40.72#ibcon#*after write, iclass 17, count 0 2006.176.07:34:40.72#ibcon#*before return 0, iclass 17, count 0 2006.176.07:34:40.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:34:40.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:34:40.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.07:34:40.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.07:34:40.72$vc4f8/vb=1,4 2006.176.07:34:40.72#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.176.07:34:40.72#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.176.07:34:40.72#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:40.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:34:40.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:34:40.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:34:40.72#ibcon#enter wrdev, iclass 19, count 2 2006.176.07:34:40.72#ibcon#first serial, iclass 19, count 2 2006.176.07:34:40.72#ibcon#enter sib2, iclass 19, count 2 2006.176.07:34:40.72#ibcon#flushed, iclass 19, count 2 2006.176.07:34:40.72#ibcon#about to write, iclass 19, count 2 2006.176.07:34:40.72#ibcon#wrote, iclass 19, count 2 2006.176.07:34:40.72#ibcon#about to read 3, iclass 19, count 2 2006.176.07:34:40.74#ibcon#read 3, iclass 19, count 2 2006.176.07:34:40.74#ibcon#about to read 4, iclass 19, count 2 2006.176.07:34:40.74#ibcon#read 4, iclass 19, count 2 2006.176.07:34:40.74#ibcon#about to read 5, iclass 19, count 2 2006.176.07:34:40.74#ibcon#read 5, iclass 19, count 2 2006.176.07:34:40.74#ibcon#about to read 6, iclass 19, count 2 2006.176.07:34:40.74#ibcon#read 6, iclass 19, count 2 2006.176.07:34:40.74#ibcon#end of sib2, iclass 19, count 2 2006.176.07:34:40.74#ibcon#*mode == 0, iclass 19, count 2 2006.176.07:34:40.74#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.176.07:34:40.74#ibcon#[27=AT01-04\r\n] 2006.176.07:34:40.74#ibcon#*before write, iclass 19, count 2 2006.176.07:34:40.74#ibcon#enter sib2, iclass 19, count 2 2006.176.07:34:40.74#ibcon#flushed, iclass 19, count 2 2006.176.07:34:40.74#ibcon#about to write, iclass 19, count 2 2006.176.07:34:40.74#ibcon#wrote, iclass 19, count 2 2006.176.07:34:40.74#ibcon#about to read 3, iclass 19, count 2 2006.176.07:34:40.77#ibcon#read 3, iclass 19, count 2 2006.176.07:34:40.77#ibcon#about to read 4, iclass 19, count 2 2006.176.07:34:40.77#ibcon#read 4, iclass 19, count 2 2006.176.07:34:40.77#ibcon#about to read 5, iclass 19, count 2 2006.176.07:34:40.77#ibcon#read 5, iclass 19, count 2 2006.176.07:34:40.77#ibcon#about to read 6, iclass 19, count 2 2006.176.07:34:40.77#ibcon#read 6, iclass 19, count 2 2006.176.07:34:40.77#ibcon#end of sib2, iclass 19, count 2 2006.176.07:34:40.77#ibcon#*after write, iclass 19, count 2 2006.176.07:34:40.77#ibcon#*before return 0, iclass 19, count 2 2006.176.07:34:40.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:34:40.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:34:40.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.176.07:34:40.77#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:40.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:34:40.89#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:34:40.89#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:34:40.89#ibcon#enter wrdev, iclass 19, count 0 2006.176.07:34:40.89#ibcon#first serial, iclass 19, count 0 2006.176.07:34:40.89#ibcon#enter sib2, iclass 19, count 0 2006.176.07:34:40.89#ibcon#flushed, iclass 19, count 0 2006.176.07:34:40.89#ibcon#about to write, iclass 19, count 0 2006.176.07:34:40.89#ibcon#wrote, iclass 19, count 0 2006.176.07:34:40.89#ibcon#about to read 3, iclass 19, count 0 2006.176.07:34:40.91#ibcon#read 3, iclass 19, count 0 2006.176.07:34:40.91#ibcon#about to read 4, iclass 19, count 0 2006.176.07:34:40.91#ibcon#read 4, iclass 19, count 0 2006.176.07:34:40.91#ibcon#about to read 5, iclass 19, count 0 2006.176.07:34:40.91#ibcon#read 5, iclass 19, count 0 2006.176.07:34:40.91#ibcon#about to read 6, iclass 19, count 0 2006.176.07:34:40.91#ibcon#read 6, iclass 19, count 0 2006.176.07:34:40.91#ibcon#end of sib2, iclass 19, count 0 2006.176.07:34:40.91#ibcon#*mode == 0, iclass 19, count 0 2006.176.07:34:40.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.07:34:40.91#ibcon#[27=USB\r\n] 2006.176.07:34:40.91#ibcon#*before write, iclass 19, count 0 2006.176.07:34:40.91#ibcon#enter sib2, iclass 19, count 0 2006.176.07:34:40.91#ibcon#flushed, iclass 19, count 0 2006.176.07:34:40.91#ibcon#about to write, iclass 19, count 0 2006.176.07:34:40.91#ibcon#wrote, iclass 19, count 0 2006.176.07:34:40.91#ibcon#about to read 3, iclass 19, count 0 2006.176.07:34:40.94#ibcon#read 3, iclass 19, count 0 2006.176.07:34:40.94#ibcon#about to read 4, iclass 19, count 0 2006.176.07:34:40.94#ibcon#read 4, iclass 19, count 0 2006.176.07:34:40.94#ibcon#about to read 5, iclass 19, count 0 2006.176.07:34:40.94#ibcon#read 5, iclass 19, count 0 2006.176.07:34:40.94#ibcon#about to read 6, iclass 19, count 0 2006.176.07:34:40.94#ibcon#read 6, iclass 19, count 0 2006.176.07:34:40.94#ibcon#end of sib2, iclass 19, count 0 2006.176.07:34:40.94#ibcon#*after write, iclass 19, count 0 2006.176.07:34:40.94#ibcon#*before return 0, iclass 19, count 0 2006.176.07:34:40.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:34:40.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:34:40.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.07:34:40.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.07:34:40.94$vc4f8/vblo=2,640.99 2006.176.07:34:40.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.07:34:40.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.07:34:40.94#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:40.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:40.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:40.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:40.94#ibcon#enter wrdev, iclass 21, count 0 2006.176.07:34:40.94#ibcon#first serial, iclass 21, count 0 2006.176.07:34:40.94#ibcon#enter sib2, iclass 21, count 0 2006.176.07:34:40.94#ibcon#flushed, iclass 21, count 0 2006.176.07:34:40.94#ibcon#about to write, iclass 21, count 0 2006.176.07:34:40.94#ibcon#wrote, iclass 21, count 0 2006.176.07:34:40.94#ibcon#about to read 3, iclass 21, count 0 2006.176.07:34:40.96#ibcon#read 3, iclass 21, count 0 2006.176.07:34:40.96#ibcon#about to read 4, iclass 21, count 0 2006.176.07:34:40.96#ibcon#read 4, iclass 21, count 0 2006.176.07:34:40.96#ibcon#about to read 5, iclass 21, count 0 2006.176.07:34:40.96#ibcon#read 5, iclass 21, count 0 2006.176.07:34:40.96#ibcon#about to read 6, iclass 21, count 0 2006.176.07:34:40.96#ibcon#read 6, iclass 21, count 0 2006.176.07:34:40.96#ibcon#end of sib2, iclass 21, count 0 2006.176.07:34:40.96#ibcon#*mode == 0, iclass 21, count 0 2006.176.07:34:40.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.07:34:40.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:34:40.96#ibcon#*before write, iclass 21, count 0 2006.176.07:34:40.96#ibcon#enter sib2, iclass 21, count 0 2006.176.07:34:40.96#ibcon#flushed, iclass 21, count 0 2006.176.07:34:40.96#ibcon#about to write, iclass 21, count 0 2006.176.07:34:40.96#ibcon#wrote, iclass 21, count 0 2006.176.07:34:40.96#ibcon#about to read 3, iclass 21, count 0 2006.176.07:34:41.00#ibcon#read 3, iclass 21, count 0 2006.176.07:34:41.00#ibcon#about to read 4, iclass 21, count 0 2006.176.07:34:41.00#ibcon#read 4, iclass 21, count 0 2006.176.07:34:41.00#ibcon#about to read 5, iclass 21, count 0 2006.176.07:34:41.00#ibcon#read 5, iclass 21, count 0 2006.176.07:34:41.00#ibcon#about to read 6, iclass 21, count 0 2006.176.07:34:41.00#ibcon#read 6, iclass 21, count 0 2006.176.07:34:41.00#ibcon#end of sib2, iclass 21, count 0 2006.176.07:34:41.00#ibcon#*after write, iclass 21, count 0 2006.176.07:34:41.00#ibcon#*before return 0, iclass 21, count 0 2006.176.07:34:41.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:41.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:34:41.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.07:34:41.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.07:34:41.00$vc4f8/vb=2,4 2006.176.07:34:41.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.07:34:41.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.07:34:41.00#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:41.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:41.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:41.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:41.06#ibcon#enter wrdev, iclass 23, count 2 2006.176.07:34:41.06#ibcon#first serial, iclass 23, count 2 2006.176.07:34:41.06#ibcon#enter sib2, iclass 23, count 2 2006.176.07:34:41.06#ibcon#flushed, iclass 23, count 2 2006.176.07:34:41.06#ibcon#about to write, iclass 23, count 2 2006.176.07:34:41.06#ibcon#wrote, iclass 23, count 2 2006.176.07:34:41.06#ibcon#about to read 3, iclass 23, count 2 2006.176.07:34:41.08#ibcon#read 3, iclass 23, count 2 2006.176.07:34:41.08#ibcon#about to read 4, iclass 23, count 2 2006.176.07:34:41.08#ibcon#read 4, iclass 23, count 2 2006.176.07:34:41.08#ibcon#about to read 5, iclass 23, count 2 2006.176.07:34:41.08#ibcon#read 5, iclass 23, count 2 2006.176.07:34:41.08#ibcon#about to read 6, iclass 23, count 2 2006.176.07:34:41.08#ibcon#read 6, iclass 23, count 2 2006.176.07:34:41.08#ibcon#end of sib2, iclass 23, count 2 2006.176.07:34:41.08#ibcon#*mode == 0, iclass 23, count 2 2006.176.07:34:41.08#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.07:34:41.08#ibcon#[27=AT02-04\r\n] 2006.176.07:34:41.08#ibcon#*before write, iclass 23, count 2 2006.176.07:34:41.08#ibcon#enter sib2, iclass 23, count 2 2006.176.07:34:41.08#ibcon#flushed, iclass 23, count 2 2006.176.07:34:41.08#ibcon#about to write, iclass 23, count 2 2006.176.07:34:41.08#ibcon#wrote, iclass 23, count 2 2006.176.07:34:41.08#ibcon#about to read 3, iclass 23, count 2 2006.176.07:34:41.11#ibcon#read 3, iclass 23, count 2 2006.176.07:34:41.11#ibcon#about to read 4, iclass 23, count 2 2006.176.07:34:41.11#ibcon#read 4, iclass 23, count 2 2006.176.07:34:41.11#ibcon#about to read 5, iclass 23, count 2 2006.176.07:34:41.11#ibcon#read 5, iclass 23, count 2 2006.176.07:34:41.11#ibcon#about to read 6, iclass 23, count 2 2006.176.07:34:41.11#ibcon#read 6, iclass 23, count 2 2006.176.07:34:41.11#ibcon#end of sib2, iclass 23, count 2 2006.176.07:34:41.11#ibcon#*after write, iclass 23, count 2 2006.176.07:34:41.11#ibcon#*before return 0, iclass 23, count 2 2006.176.07:34:41.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:41.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:34:41.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.07:34:41.11#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:41.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:41.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:41.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:41.23#ibcon#enter wrdev, iclass 23, count 0 2006.176.07:34:41.23#ibcon#first serial, iclass 23, count 0 2006.176.07:34:41.23#ibcon#enter sib2, iclass 23, count 0 2006.176.07:34:41.23#ibcon#flushed, iclass 23, count 0 2006.176.07:34:41.23#ibcon#about to write, iclass 23, count 0 2006.176.07:34:41.23#ibcon#wrote, iclass 23, count 0 2006.176.07:34:41.23#ibcon#about to read 3, iclass 23, count 0 2006.176.07:34:41.25#ibcon#read 3, iclass 23, count 0 2006.176.07:34:41.25#ibcon#about to read 4, iclass 23, count 0 2006.176.07:34:41.25#ibcon#read 4, iclass 23, count 0 2006.176.07:34:41.25#ibcon#about to read 5, iclass 23, count 0 2006.176.07:34:41.25#ibcon#read 5, iclass 23, count 0 2006.176.07:34:41.25#ibcon#about to read 6, iclass 23, count 0 2006.176.07:34:41.25#ibcon#read 6, iclass 23, count 0 2006.176.07:34:41.25#ibcon#end of sib2, iclass 23, count 0 2006.176.07:34:41.25#ibcon#*mode == 0, iclass 23, count 0 2006.176.07:34:41.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.07:34:41.25#ibcon#[27=USB\r\n] 2006.176.07:34:41.25#ibcon#*before write, iclass 23, count 0 2006.176.07:34:41.25#ibcon#enter sib2, iclass 23, count 0 2006.176.07:34:41.25#ibcon#flushed, iclass 23, count 0 2006.176.07:34:41.25#ibcon#about to write, iclass 23, count 0 2006.176.07:34:41.25#ibcon#wrote, iclass 23, count 0 2006.176.07:34:41.25#ibcon#about to read 3, iclass 23, count 0 2006.176.07:34:41.28#ibcon#read 3, iclass 23, count 0 2006.176.07:34:41.28#ibcon#about to read 4, iclass 23, count 0 2006.176.07:34:41.28#ibcon#read 4, iclass 23, count 0 2006.176.07:34:41.28#ibcon#about to read 5, iclass 23, count 0 2006.176.07:34:41.28#ibcon#read 5, iclass 23, count 0 2006.176.07:34:41.28#ibcon#about to read 6, iclass 23, count 0 2006.176.07:34:41.28#ibcon#read 6, iclass 23, count 0 2006.176.07:34:41.28#ibcon#end of sib2, iclass 23, count 0 2006.176.07:34:41.28#ibcon#*after write, iclass 23, count 0 2006.176.07:34:41.28#ibcon#*before return 0, iclass 23, count 0 2006.176.07:34:41.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:41.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:34:41.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.07:34:41.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.07:34:41.28$vc4f8/vblo=3,656.99 2006.176.07:34:41.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.07:34:41.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.07:34:41.28#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:41.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:41.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:41.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:41.28#ibcon#enter wrdev, iclass 25, count 0 2006.176.07:34:41.28#ibcon#first serial, iclass 25, count 0 2006.176.07:34:41.28#ibcon#enter sib2, iclass 25, count 0 2006.176.07:34:41.28#ibcon#flushed, iclass 25, count 0 2006.176.07:34:41.28#ibcon#about to write, iclass 25, count 0 2006.176.07:34:41.28#ibcon#wrote, iclass 25, count 0 2006.176.07:34:41.28#ibcon#about to read 3, iclass 25, count 0 2006.176.07:34:41.30#ibcon#read 3, iclass 25, count 0 2006.176.07:34:41.30#ibcon#about to read 4, iclass 25, count 0 2006.176.07:34:41.30#ibcon#read 4, iclass 25, count 0 2006.176.07:34:41.30#ibcon#about to read 5, iclass 25, count 0 2006.176.07:34:41.30#ibcon#read 5, iclass 25, count 0 2006.176.07:34:41.30#ibcon#about to read 6, iclass 25, count 0 2006.176.07:34:41.30#ibcon#read 6, iclass 25, count 0 2006.176.07:34:41.30#ibcon#end of sib2, iclass 25, count 0 2006.176.07:34:41.30#ibcon#*mode == 0, iclass 25, count 0 2006.176.07:34:41.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.07:34:41.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:34:41.30#ibcon#*before write, iclass 25, count 0 2006.176.07:34:41.30#ibcon#enter sib2, iclass 25, count 0 2006.176.07:34:41.30#ibcon#flushed, iclass 25, count 0 2006.176.07:34:41.30#ibcon#about to write, iclass 25, count 0 2006.176.07:34:41.30#ibcon#wrote, iclass 25, count 0 2006.176.07:34:41.30#ibcon#about to read 3, iclass 25, count 0 2006.176.07:34:41.34#ibcon#read 3, iclass 25, count 0 2006.176.07:34:41.34#ibcon#about to read 4, iclass 25, count 0 2006.176.07:34:41.34#ibcon#read 4, iclass 25, count 0 2006.176.07:34:41.34#ibcon#about to read 5, iclass 25, count 0 2006.176.07:34:41.34#ibcon#read 5, iclass 25, count 0 2006.176.07:34:41.34#ibcon#about to read 6, iclass 25, count 0 2006.176.07:34:41.34#ibcon#read 6, iclass 25, count 0 2006.176.07:34:41.34#ibcon#end of sib2, iclass 25, count 0 2006.176.07:34:41.34#ibcon#*after write, iclass 25, count 0 2006.176.07:34:41.34#ibcon#*before return 0, iclass 25, count 0 2006.176.07:34:41.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:41.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:34:41.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.07:34:41.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.07:34:41.34$vc4f8/vb=3,4 2006.176.07:34:41.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.07:34:41.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.07:34:41.34#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:41.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:41.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:41.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:41.40#ibcon#enter wrdev, iclass 27, count 2 2006.176.07:34:41.40#ibcon#first serial, iclass 27, count 2 2006.176.07:34:41.40#ibcon#enter sib2, iclass 27, count 2 2006.176.07:34:41.40#ibcon#flushed, iclass 27, count 2 2006.176.07:34:41.40#ibcon#about to write, iclass 27, count 2 2006.176.07:34:41.40#ibcon#wrote, iclass 27, count 2 2006.176.07:34:41.40#ibcon#about to read 3, iclass 27, count 2 2006.176.07:34:41.42#ibcon#read 3, iclass 27, count 2 2006.176.07:34:41.42#ibcon#about to read 4, iclass 27, count 2 2006.176.07:34:41.42#ibcon#read 4, iclass 27, count 2 2006.176.07:34:41.42#ibcon#about to read 5, iclass 27, count 2 2006.176.07:34:41.42#ibcon#read 5, iclass 27, count 2 2006.176.07:34:41.42#ibcon#about to read 6, iclass 27, count 2 2006.176.07:34:41.42#ibcon#read 6, iclass 27, count 2 2006.176.07:34:41.42#ibcon#end of sib2, iclass 27, count 2 2006.176.07:34:41.42#ibcon#*mode == 0, iclass 27, count 2 2006.176.07:34:41.42#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.07:34:41.42#ibcon#[27=AT03-04\r\n] 2006.176.07:34:41.42#ibcon#*before write, iclass 27, count 2 2006.176.07:34:41.42#ibcon#enter sib2, iclass 27, count 2 2006.176.07:34:41.42#ibcon#flushed, iclass 27, count 2 2006.176.07:34:41.42#ibcon#about to write, iclass 27, count 2 2006.176.07:34:41.42#ibcon#wrote, iclass 27, count 2 2006.176.07:34:41.42#ibcon#about to read 3, iclass 27, count 2 2006.176.07:34:41.45#ibcon#read 3, iclass 27, count 2 2006.176.07:34:41.45#ibcon#about to read 4, iclass 27, count 2 2006.176.07:34:41.45#ibcon#read 4, iclass 27, count 2 2006.176.07:34:41.45#ibcon#about to read 5, iclass 27, count 2 2006.176.07:34:41.45#ibcon#read 5, iclass 27, count 2 2006.176.07:34:41.45#ibcon#about to read 6, iclass 27, count 2 2006.176.07:34:41.45#ibcon#read 6, iclass 27, count 2 2006.176.07:34:41.45#ibcon#end of sib2, iclass 27, count 2 2006.176.07:34:41.45#ibcon#*after write, iclass 27, count 2 2006.176.07:34:41.45#ibcon#*before return 0, iclass 27, count 2 2006.176.07:34:41.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:41.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:34:41.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.07:34:41.45#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:41.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:41.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:41.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:41.57#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:34:41.57#ibcon#first serial, iclass 27, count 0 2006.176.07:34:41.57#ibcon#enter sib2, iclass 27, count 0 2006.176.07:34:41.57#ibcon#flushed, iclass 27, count 0 2006.176.07:34:41.57#ibcon#about to write, iclass 27, count 0 2006.176.07:34:41.57#ibcon#wrote, iclass 27, count 0 2006.176.07:34:41.57#ibcon#about to read 3, iclass 27, count 0 2006.176.07:34:41.59#ibcon#read 3, iclass 27, count 0 2006.176.07:34:41.59#ibcon#about to read 4, iclass 27, count 0 2006.176.07:34:41.59#ibcon#read 4, iclass 27, count 0 2006.176.07:34:41.59#ibcon#about to read 5, iclass 27, count 0 2006.176.07:34:41.59#ibcon#read 5, iclass 27, count 0 2006.176.07:34:41.59#ibcon#about to read 6, iclass 27, count 0 2006.176.07:34:41.59#ibcon#read 6, iclass 27, count 0 2006.176.07:34:41.59#ibcon#end of sib2, iclass 27, count 0 2006.176.07:34:41.59#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:34:41.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:34:41.59#ibcon#[27=USB\r\n] 2006.176.07:34:41.59#ibcon#*before write, iclass 27, count 0 2006.176.07:34:41.59#ibcon#enter sib2, iclass 27, count 0 2006.176.07:34:41.59#ibcon#flushed, iclass 27, count 0 2006.176.07:34:41.59#ibcon#about to write, iclass 27, count 0 2006.176.07:34:41.59#ibcon#wrote, iclass 27, count 0 2006.176.07:34:41.59#ibcon#about to read 3, iclass 27, count 0 2006.176.07:34:41.62#ibcon#read 3, iclass 27, count 0 2006.176.07:34:41.62#ibcon#about to read 4, iclass 27, count 0 2006.176.07:34:41.62#ibcon#read 4, iclass 27, count 0 2006.176.07:34:41.62#ibcon#about to read 5, iclass 27, count 0 2006.176.07:34:41.62#ibcon#read 5, iclass 27, count 0 2006.176.07:34:41.62#ibcon#about to read 6, iclass 27, count 0 2006.176.07:34:41.62#ibcon#read 6, iclass 27, count 0 2006.176.07:34:41.62#ibcon#end of sib2, iclass 27, count 0 2006.176.07:34:41.62#ibcon#*after write, iclass 27, count 0 2006.176.07:34:41.62#ibcon#*before return 0, iclass 27, count 0 2006.176.07:34:41.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:41.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:34:41.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:34:41.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:34:41.62$vc4f8/vblo=4,712.99 2006.176.07:34:41.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.07:34:41.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.07:34:41.62#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:41.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:41.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:41.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:41.62#ibcon#enter wrdev, iclass 29, count 0 2006.176.07:34:41.62#ibcon#first serial, iclass 29, count 0 2006.176.07:34:41.62#ibcon#enter sib2, iclass 29, count 0 2006.176.07:34:41.62#ibcon#flushed, iclass 29, count 0 2006.176.07:34:41.62#ibcon#about to write, iclass 29, count 0 2006.176.07:34:41.62#ibcon#wrote, iclass 29, count 0 2006.176.07:34:41.62#ibcon#about to read 3, iclass 29, count 0 2006.176.07:34:41.64#ibcon#read 3, iclass 29, count 0 2006.176.07:34:41.64#ibcon#about to read 4, iclass 29, count 0 2006.176.07:34:41.64#ibcon#read 4, iclass 29, count 0 2006.176.07:34:41.64#ibcon#about to read 5, iclass 29, count 0 2006.176.07:34:41.64#ibcon#read 5, iclass 29, count 0 2006.176.07:34:41.64#ibcon#about to read 6, iclass 29, count 0 2006.176.07:34:41.64#ibcon#read 6, iclass 29, count 0 2006.176.07:34:41.64#ibcon#end of sib2, iclass 29, count 0 2006.176.07:34:41.64#ibcon#*mode == 0, iclass 29, count 0 2006.176.07:34:41.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.07:34:41.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:34:41.64#ibcon#*before write, iclass 29, count 0 2006.176.07:34:41.64#ibcon#enter sib2, iclass 29, count 0 2006.176.07:34:41.64#ibcon#flushed, iclass 29, count 0 2006.176.07:34:41.64#ibcon#about to write, iclass 29, count 0 2006.176.07:34:41.64#ibcon#wrote, iclass 29, count 0 2006.176.07:34:41.64#ibcon#about to read 3, iclass 29, count 0 2006.176.07:34:41.68#ibcon#read 3, iclass 29, count 0 2006.176.07:34:41.68#ibcon#about to read 4, iclass 29, count 0 2006.176.07:34:41.68#ibcon#read 4, iclass 29, count 0 2006.176.07:34:41.68#ibcon#about to read 5, iclass 29, count 0 2006.176.07:34:41.68#ibcon#read 5, iclass 29, count 0 2006.176.07:34:41.68#ibcon#about to read 6, iclass 29, count 0 2006.176.07:34:41.68#ibcon#read 6, iclass 29, count 0 2006.176.07:34:41.68#ibcon#end of sib2, iclass 29, count 0 2006.176.07:34:41.68#ibcon#*after write, iclass 29, count 0 2006.176.07:34:41.68#ibcon#*before return 0, iclass 29, count 0 2006.176.07:34:41.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:41.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:34:41.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.07:34:41.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.07:34:41.68$vc4f8/vb=4,4 2006.176.07:34:41.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.07:34:41.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.07:34:41.68#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:41.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:41.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:41.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:41.74#ibcon#enter wrdev, iclass 31, count 2 2006.176.07:34:41.74#ibcon#first serial, iclass 31, count 2 2006.176.07:34:41.74#ibcon#enter sib2, iclass 31, count 2 2006.176.07:34:41.74#ibcon#flushed, iclass 31, count 2 2006.176.07:34:41.74#ibcon#about to write, iclass 31, count 2 2006.176.07:34:41.74#ibcon#wrote, iclass 31, count 2 2006.176.07:34:41.74#ibcon#about to read 3, iclass 31, count 2 2006.176.07:34:41.76#ibcon#read 3, iclass 31, count 2 2006.176.07:34:41.76#ibcon#about to read 4, iclass 31, count 2 2006.176.07:34:41.76#ibcon#read 4, iclass 31, count 2 2006.176.07:34:41.76#ibcon#about to read 5, iclass 31, count 2 2006.176.07:34:41.76#ibcon#read 5, iclass 31, count 2 2006.176.07:34:41.76#ibcon#about to read 6, iclass 31, count 2 2006.176.07:34:41.76#ibcon#read 6, iclass 31, count 2 2006.176.07:34:41.76#ibcon#end of sib2, iclass 31, count 2 2006.176.07:34:41.76#ibcon#*mode == 0, iclass 31, count 2 2006.176.07:34:41.76#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.07:34:41.76#ibcon#[27=AT04-04\r\n] 2006.176.07:34:41.76#ibcon#*before write, iclass 31, count 2 2006.176.07:34:41.76#ibcon#enter sib2, iclass 31, count 2 2006.176.07:34:41.76#ibcon#flushed, iclass 31, count 2 2006.176.07:34:41.76#ibcon#about to write, iclass 31, count 2 2006.176.07:34:41.76#ibcon#wrote, iclass 31, count 2 2006.176.07:34:41.76#ibcon#about to read 3, iclass 31, count 2 2006.176.07:34:41.79#ibcon#read 3, iclass 31, count 2 2006.176.07:34:41.79#ibcon#about to read 4, iclass 31, count 2 2006.176.07:34:41.79#ibcon#read 4, iclass 31, count 2 2006.176.07:34:41.79#ibcon#about to read 5, iclass 31, count 2 2006.176.07:34:41.79#ibcon#read 5, iclass 31, count 2 2006.176.07:34:41.79#ibcon#about to read 6, iclass 31, count 2 2006.176.07:34:41.79#ibcon#read 6, iclass 31, count 2 2006.176.07:34:41.79#ibcon#end of sib2, iclass 31, count 2 2006.176.07:34:41.79#ibcon#*after write, iclass 31, count 2 2006.176.07:34:41.79#ibcon#*before return 0, iclass 31, count 2 2006.176.07:34:41.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:41.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:34:41.79#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.07:34:41.79#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:41.79#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:41.91#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:41.91#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:41.91#ibcon#enter wrdev, iclass 31, count 0 2006.176.07:34:41.91#ibcon#first serial, iclass 31, count 0 2006.176.07:34:41.91#ibcon#enter sib2, iclass 31, count 0 2006.176.07:34:41.91#ibcon#flushed, iclass 31, count 0 2006.176.07:34:41.91#ibcon#about to write, iclass 31, count 0 2006.176.07:34:41.91#ibcon#wrote, iclass 31, count 0 2006.176.07:34:41.91#ibcon#about to read 3, iclass 31, count 0 2006.176.07:34:41.93#ibcon#read 3, iclass 31, count 0 2006.176.07:34:41.93#ibcon#about to read 4, iclass 31, count 0 2006.176.07:34:41.93#ibcon#read 4, iclass 31, count 0 2006.176.07:34:41.93#ibcon#about to read 5, iclass 31, count 0 2006.176.07:34:41.93#ibcon#read 5, iclass 31, count 0 2006.176.07:34:41.93#ibcon#about to read 6, iclass 31, count 0 2006.176.07:34:41.93#ibcon#read 6, iclass 31, count 0 2006.176.07:34:41.93#ibcon#end of sib2, iclass 31, count 0 2006.176.07:34:41.93#ibcon#*mode == 0, iclass 31, count 0 2006.176.07:34:41.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.07:34:41.93#ibcon#[27=USB\r\n] 2006.176.07:34:41.93#ibcon#*before write, iclass 31, count 0 2006.176.07:34:41.93#ibcon#enter sib2, iclass 31, count 0 2006.176.07:34:41.93#ibcon#flushed, iclass 31, count 0 2006.176.07:34:41.93#ibcon#about to write, iclass 31, count 0 2006.176.07:34:41.93#ibcon#wrote, iclass 31, count 0 2006.176.07:34:41.93#ibcon#about to read 3, iclass 31, count 0 2006.176.07:34:41.96#ibcon#read 3, iclass 31, count 0 2006.176.07:34:41.96#ibcon#about to read 4, iclass 31, count 0 2006.176.07:34:41.96#ibcon#read 4, iclass 31, count 0 2006.176.07:34:41.96#ibcon#about to read 5, iclass 31, count 0 2006.176.07:34:41.96#ibcon#read 5, iclass 31, count 0 2006.176.07:34:41.96#ibcon#about to read 6, iclass 31, count 0 2006.176.07:34:41.96#ibcon#read 6, iclass 31, count 0 2006.176.07:34:41.96#ibcon#end of sib2, iclass 31, count 0 2006.176.07:34:41.96#ibcon#*after write, iclass 31, count 0 2006.176.07:34:41.96#ibcon#*before return 0, iclass 31, count 0 2006.176.07:34:41.96#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:41.96#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:34:41.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.07:34:41.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.07:34:41.96$vc4f8/vblo=5,744.99 2006.176.07:34:41.96#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.07:34:41.96#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.07:34:41.96#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:41.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:41.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:41.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:41.96#ibcon#enter wrdev, iclass 33, count 0 2006.176.07:34:41.96#ibcon#first serial, iclass 33, count 0 2006.176.07:34:41.96#ibcon#enter sib2, iclass 33, count 0 2006.176.07:34:41.96#ibcon#flushed, iclass 33, count 0 2006.176.07:34:41.96#ibcon#about to write, iclass 33, count 0 2006.176.07:34:41.96#ibcon#wrote, iclass 33, count 0 2006.176.07:34:41.96#ibcon#about to read 3, iclass 33, count 0 2006.176.07:34:41.98#ibcon#read 3, iclass 33, count 0 2006.176.07:34:41.98#ibcon#about to read 4, iclass 33, count 0 2006.176.07:34:41.98#ibcon#read 4, iclass 33, count 0 2006.176.07:34:41.98#ibcon#about to read 5, iclass 33, count 0 2006.176.07:34:41.98#ibcon#read 5, iclass 33, count 0 2006.176.07:34:41.98#ibcon#about to read 6, iclass 33, count 0 2006.176.07:34:41.98#ibcon#read 6, iclass 33, count 0 2006.176.07:34:41.98#ibcon#end of sib2, iclass 33, count 0 2006.176.07:34:41.98#ibcon#*mode == 0, iclass 33, count 0 2006.176.07:34:41.98#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.07:34:41.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:34:41.98#ibcon#*before write, iclass 33, count 0 2006.176.07:34:41.98#ibcon#enter sib2, iclass 33, count 0 2006.176.07:34:41.98#ibcon#flushed, iclass 33, count 0 2006.176.07:34:41.98#ibcon#about to write, iclass 33, count 0 2006.176.07:34:41.98#ibcon#wrote, iclass 33, count 0 2006.176.07:34:41.98#ibcon#about to read 3, iclass 33, count 0 2006.176.07:34:42.02#ibcon#read 3, iclass 33, count 0 2006.176.07:34:42.02#ibcon#about to read 4, iclass 33, count 0 2006.176.07:34:42.02#ibcon#read 4, iclass 33, count 0 2006.176.07:34:42.02#ibcon#about to read 5, iclass 33, count 0 2006.176.07:34:42.02#ibcon#read 5, iclass 33, count 0 2006.176.07:34:42.02#ibcon#about to read 6, iclass 33, count 0 2006.176.07:34:42.02#ibcon#read 6, iclass 33, count 0 2006.176.07:34:42.02#ibcon#end of sib2, iclass 33, count 0 2006.176.07:34:42.02#ibcon#*after write, iclass 33, count 0 2006.176.07:34:42.02#ibcon#*before return 0, iclass 33, count 0 2006.176.07:34:42.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:42.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:34:42.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.07:34:42.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.07:34:42.02$vc4f8/vb=5,4 2006.176.07:34:42.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.176.07:34:42.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.176.07:34:42.02#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:42.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:42.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:42.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:42.08#ibcon#enter wrdev, iclass 35, count 2 2006.176.07:34:42.08#ibcon#first serial, iclass 35, count 2 2006.176.07:34:42.08#ibcon#enter sib2, iclass 35, count 2 2006.176.07:34:42.08#ibcon#flushed, iclass 35, count 2 2006.176.07:34:42.08#ibcon#about to write, iclass 35, count 2 2006.176.07:34:42.08#ibcon#wrote, iclass 35, count 2 2006.176.07:34:42.08#ibcon#about to read 3, iclass 35, count 2 2006.176.07:34:42.10#ibcon#read 3, iclass 35, count 2 2006.176.07:34:42.10#ibcon#about to read 4, iclass 35, count 2 2006.176.07:34:42.10#ibcon#read 4, iclass 35, count 2 2006.176.07:34:42.10#ibcon#about to read 5, iclass 35, count 2 2006.176.07:34:42.10#ibcon#read 5, iclass 35, count 2 2006.176.07:34:42.10#ibcon#about to read 6, iclass 35, count 2 2006.176.07:34:42.10#ibcon#read 6, iclass 35, count 2 2006.176.07:34:42.10#ibcon#end of sib2, iclass 35, count 2 2006.176.07:34:42.10#ibcon#*mode == 0, iclass 35, count 2 2006.176.07:34:42.10#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.176.07:34:42.10#ibcon#[27=AT05-04\r\n] 2006.176.07:34:42.10#ibcon#*before write, iclass 35, count 2 2006.176.07:34:42.10#ibcon#enter sib2, iclass 35, count 2 2006.176.07:34:42.10#ibcon#flushed, iclass 35, count 2 2006.176.07:34:42.10#ibcon#about to write, iclass 35, count 2 2006.176.07:34:42.10#ibcon#wrote, iclass 35, count 2 2006.176.07:34:42.10#ibcon#about to read 3, iclass 35, count 2 2006.176.07:34:42.13#ibcon#read 3, iclass 35, count 2 2006.176.07:34:42.13#ibcon#about to read 4, iclass 35, count 2 2006.176.07:34:42.13#ibcon#read 4, iclass 35, count 2 2006.176.07:34:42.13#ibcon#about to read 5, iclass 35, count 2 2006.176.07:34:42.13#ibcon#read 5, iclass 35, count 2 2006.176.07:34:42.13#ibcon#about to read 6, iclass 35, count 2 2006.176.07:34:42.13#ibcon#read 6, iclass 35, count 2 2006.176.07:34:42.13#ibcon#end of sib2, iclass 35, count 2 2006.176.07:34:42.13#ibcon#*after write, iclass 35, count 2 2006.176.07:34:42.13#ibcon#*before return 0, iclass 35, count 2 2006.176.07:34:42.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:42.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:34:42.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.176.07:34:42.13#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:42.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:42.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:42.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:42.25#ibcon#enter wrdev, iclass 35, count 0 2006.176.07:34:42.25#ibcon#first serial, iclass 35, count 0 2006.176.07:34:42.25#ibcon#enter sib2, iclass 35, count 0 2006.176.07:34:42.25#ibcon#flushed, iclass 35, count 0 2006.176.07:34:42.25#ibcon#about to write, iclass 35, count 0 2006.176.07:34:42.25#ibcon#wrote, iclass 35, count 0 2006.176.07:34:42.25#ibcon#about to read 3, iclass 35, count 0 2006.176.07:34:42.27#ibcon#read 3, iclass 35, count 0 2006.176.07:34:42.27#ibcon#about to read 4, iclass 35, count 0 2006.176.07:34:42.27#ibcon#read 4, iclass 35, count 0 2006.176.07:34:42.27#ibcon#about to read 5, iclass 35, count 0 2006.176.07:34:42.27#ibcon#read 5, iclass 35, count 0 2006.176.07:34:42.27#ibcon#about to read 6, iclass 35, count 0 2006.176.07:34:42.27#ibcon#read 6, iclass 35, count 0 2006.176.07:34:42.27#ibcon#end of sib2, iclass 35, count 0 2006.176.07:34:42.27#ibcon#*mode == 0, iclass 35, count 0 2006.176.07:34:42.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.07:34:42.27#ibcon#[27=USB\r\n] 2006.176.07:34:42.27#ibcon#*before write, iclass 35, count 0 2006.176.07:34:42.27#ibcon#enter sib2, iclass 35, count 0 2006.176.07:34:42.27#ibcon#flushed, iclass 35, count 0 2006.176.07:34:42.27#ibcon#about to write, iclass 35, count 0 2006.176.07:34:42.27#ibcon#wrote, iclass 35, count 0 2006.176.07:34:42.27#ibcon#about to read 3, iclass 35, count 0 2006.176.07:34:42.30#ibcon#read 3, iclass 35, count 0 2006.176.07:34:42.30#ibcon#about to read 4, iclass 35, count 0 2006.176.07:34:42.30#ibcon#read 4, iclass 35, count 0 2006.176.07:34:42.30#ibcon#about to read 5, iclass 35, count 0 2006.176.07:34:42.30#ibcon#read 5, iclass 35, count 0 2006.176.07:34:42.30#ibcon#about to read 6, iclass 35, count 0 2006.176.07:34:42.30#ibcon#read 6, iclass 35, count 0 2006.176.07:34:42.30#ibcon#end of sib2, iclass 35, count 0 2006.176.07:34:42.30#ibcon#*after write, iclass 35, count 0 2006.176.07:34:42.30#ibcon#*before return 0, iclass 35, count 0 2006.176.07:34:42.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:42.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:34:42.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.07:34:42.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.07:34:42.30$vc4f8/vblo=6,752.99 2006.176.07:34:42.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.176.07:34:42.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.176.07:34:42.30#ibcon#ireg 17 cls_cnt 0 2006.176.07:34:42.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:42.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:42.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:42.30#ibcon#enter wrdev, iclass 37, count 0 2006.176.07:34:42.30#ibcon#first serial, iclass 37, count 0 2006.176.07:34:42.30#ibcon#enter sib2, iclass 37, count 0 2006.176.07:34:42.30#ibcon#flushed, iclass 37, count 0 2006.176.07:34:42.30#ibcon#about to write, iclass 37, count 0 2006.176.07:34:42.30#ibcon#wrote, iclass 37, count 0 2006.176.07:34:42.30#ibcon#about to read 3, iclass 37, count 0 2006.176.07:34:42.32#ibcon#read 3, iclass 37, count 0 2006.176.07:34:42.32#ibcon#about to read 4, iclass 37, count 0 2006.176.07:34:42.32#ibcon#read 4, iclass 37, count 0 2006.176.07:34:42.32#ibcon#about to read 5, iclass 37, count 0 2006.176.07:34:42.32#ibcon#read 5, iclass 37, count 0 2006.176.07:34:42.32#ibcon#about to read 6, iclass 37, count 0 2006.176.07:34:42.32#ibcon#read 6, iclass 37, count 0 2006.176.07:34:42.32#ibcon#end of sib2, iclass 37, count 0 2006.176.07:34:42.32#ibcon#*mode == 0, iclass 37, count 0 2006.176.07:34:42.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.07:34:42.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:34:42.32#ibcon#*before write, iclass 37, count 0 2006.176.07:34:42.32#ibcon#enter sib2, iclass 37, count 0 2006.176.07:34:42.32#ibcon#flushed, iclass 37, count 0 2006.176.07:34:42.32#ibcon#about to write, iclass 37, count 0 2006.176.07:34:42.32#ibcon#wrote, iclass 37, count 0 2006.176.07:34:42.32#ibcon#about to read 3, iclass 37, count 0 2006.176.07:34:42.36#ibcon#read 3, iclass 37, count 0 2006.176.07:34:42.36#ibcon#about to read 4, iclass 37, count 0 2006.176.07:34:42.36#ibcon#read 4, iclass 37, count 0 2006.176.07:34:42.36#ibcon#about to read 5, iclass 37, count 0 2006.176.07:34:42.36#ibcon#read 5, iclass 37, count 0 2006.176.07:34:42.36#ibcon#about to read 6, iclass 37, count 0 2006.176.07:34:42.36#ibcon#read 6, iclass 37, count 0 2006.176.07:34:42.36#ibcon#end of sib2, iclass 37, count 0 2006.176.07:34:42.36#ibcon#*after write, iclass 37, count 0 2006.176.07:34:42.36#ibcon#*before return 0, iclass 37, count 0 2006.176.07:34:42.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:42.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:34:42.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.07:34:42.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.07:34:42.36$vc4f8/vb=6,4 2006.176.07:34:42.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.176.07:34:42.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.176.07:34:42.36#ibcon#ireg 11 cls_cnt 2 2006.176.07:34:42.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:42.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:42.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:42.42#ibcon#enter wrdev, iclass 39, count 2 2006.176.07:34:42.42#ibcon#first serial, iclass 39, count 2 2006.176.07:34:42.42#ibcon#enter sib2, iclass 39, count 2 2006.176.07:34:42.42#ibcon#flushed, iclass 39, count 2 2006.176.07:34:42.42#ibcon#about to write, iclass 39, count 2 2006.176.07:34:42.42#ibcon#wrote, iclass 39, count 2 2006.176.07:34:42.42#ibcon#about to read 3, iclass 39, count 2 2006.176.07:34:42.44#ibcon#read 3, iclass 39, count 2 2006.176.07:34:42.44#ibcon#about to read 4, iclass 39, count 2 2006.176.07:34:42.44#ibcon#read 4, iclass 39, count 2 2006.176.07:34:42.44#ibcon#about to read 5, iclass 39, count 2 2006.176.07:34:42.44#ibcon#read 5, iclass 39, count 2 2006.176.07:34:42.44#ibcon#about to read 6, iclass 39, count 2 2006.176.07:34:42.44#ibcon#read 6, iclass 39, count 2 2006.176.07:34:42.44#ibcon#end of sib2, iclass 39, count 2 2006.176.07:34:42.44#ibcon#*mode == 0, iclass 39, count 2 2006.176.07:34:42.44#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.176.07:34:42.44#ibcon#[27=AT06-04\r\n] 2006.176.07:34:42.44#ibcon#*before write, iclass 39, count 2 2006.176.07:34:42.44#ibcon#enter sib2, iclass 39, count 2 2006.176.07:34:42.44#ibcon#flushed, iclass 39, count 2 2006.176.07:34:42.44#ibcon#about to write, iclass 39, count 2 2006.176.07:34:42.44#ibcon#wrote, iclass 39, count 2 2006.176.07:34:42.44#ibcon#about to read 3, iclass 39, count 2 2006.176.07:34:42.47#ibcon#read 3, iclass 39, count 2 2006.176.07:34:42.47#ibcon#about to read 4, iclass 39, count 2 2006.176.07:34:42.47#ibcon#read 4, iclass 39, count 2 2006.176.07:34:42.47#ibcon#about to read 5, iclass 39, count 2 2006.176.07:34:42.47#ibcon#read 5, iclass 39, count 2 2006.176.07:34:42.47#ibcon#about to read 6, iclass 39, count 2 2006.176.07:34:42.47#ibcon#read 6, iclass 39, count 2 2006.176.07:34:42.47#ibcon#end of sib2, iclass 39, count 2 2006.176.07:34:42.47#ibcon#*after write, iclass 39, count 2 2006.176.07:34:42.47#ibcon#*before return 0, iclass 39, count 2 2006.176.07:34:42.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:42.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:34:42.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.176.07:34:42.47#ibcon#ireg 7 cls_cnt 0 2006.176.07:34:42.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:42.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:42.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:42.59#ibcon#enter wrdev, iclass 39, count 0 2006.176.07:34:42.59#ibcon#first serial, iclass 39, count 0 2006.176.07:34:42.59#ibcon#enter sib2, iclass 39, count 0 2006.176.07:34:42.59#ibcon#flushed, iclass 39, count 0 2006.176.07:34:42.59#ibcon#about to write, iclass 39, count 0 2006.176.07:34:42.59#ibcon#wrote, iclass 39, count 0 2006.176.07:34:42.59#ibcon#about to read 3, iclass 39, count 0 2006.176.07:34:42.61#ibcon#read 3, iclass 39, count 0 2006.176.07:34:42.61#ibcon#about to read 4, iclass 39, count 0 2006.176.07:34:42.61#ibcon#read 4, iclass 39, count 0 2006.176.07:34:42.61#ibcon#about to read 5, iclass 39, count 0 2006.176.07:34:42.61#ibcon#read 5, iclass 39, count 0 2006.176.07:34:42.61#ibcon#about to read 6, iclass 39, count 0 2006.176.07:34:42.61#ibcon#read 6, iclass 39, count 0 2006.176.07:34:42.61#ibcon#end of sib2, iclass 39, count 0 2006.176.07:34:42.61#ibcon#*mode == 0, iclass 39, count 0 2006.176.07:34:42.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.07:34:42.61#ibcon#[27=USB\r\n] 2006.176.07:34:42.61#ibcon#*before write, iclass 39, count 0 2006.176.07:34:42.61#ibcon#enter sib2, iclass 39, count 0 2006.176.07:34:42.61#ibcon#flushed, iclass 39, count 0 2006.176.07:34:42.61#ibcon#about to write, iclass 39, count 0 2006.176.07:34:42.61#ibcon#wrote, iclass 39, count 0 2006.176.07:34:42.61#ibcon#about to read 3, iclass 39, count 0 2006.176.07:34:42.64#ibcon#read 3, iclass 39, count 0 2006.176.07:34:42.64#ibcon#about to read 4, iclass 39, count 0 2006.176.07:34:42.64#ibcon#read 4, iclass 39, count 0 2006.176.07:34:42.64#ibcon#about to read 5, iclass 39, count 0 2006.176.07:34:42.64#ibcon#read 5, iclass 39, count 0 2006.176.07:34:42.64#ibcon#about to read 6, iclass 39, count 0 2006.176.07:34:42.64#ibcon#read 6, iclass 39, count 0 2006.176.07:34:42.64#ibcon#end of sib2, iclass 39, count 0 2006.176.07:34:42.64#ibcon#*after write, iclass 39, count 0 2006.176.07:34:42.64#ibcon#*before return 0, iclass 39, count 0 2006.176.07:34:42.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:42.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:34:42.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.07:34:42.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.07:34:42.64$vc4f8/vabw=wide 2006.176.07:34:42.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.07:34:42.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.07:34:42.64#ibcon#ireg 8 cls_cnt 0 2006.176.07:34:42.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:42.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:42.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:42.64#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:34:42.64#ibcon#first serial, iclass 3, count 0 2006.176.07:34:42.64#ibcon#enter sib2, iclass 3, count 0 2006.176.07:34:42.64#ibcon#flushed, iclass 3, count 0 2006.176.07:34:42.64#ibcon#about to write, iclass 3, count 0 2006.176.07:34:42.64#ibcon#wrote, iclass 3, count 0 2006.176.07:34:42.64#ibcon#about to read 3, iclass 3, count 0 2006.176.07:34:42.66#ibcon#read 3, iclass 3, count 0 2006.176.07:34:42.66#ibcon#about to read 4, iclass 3, count 0 2006.176.07:34:42.66#ibcon#read 4, iclass 3, count 0 2006.176.07:34:42.66#ibcon#about to read 5, iclass 3, count 0 2006.176.07:34:42.66#ibcon#read 5, iclass 3, count 0 2006.176.07:34:42.66#ibcon#about to read 6, iclass 3, count 0 2006.176.07:34:42.66#ibcon#read 6, iclass 3, count 0 2006.176.07:34:42.66#ibcon#end of sib2, iclass 3, count 0 2006.176.07:34:42.66#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:34:42.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:34:42.66#ibcon#[25=BW32\r\n] 2006.176.07:34:42.66#ibcon#*before write, iclass 3, count 0 2006.176.07:34:42.66#ibcon#enter sib2, iclass 3, count 0 2006.176.07:34:42.66#ibcon#flushed, iclass 3, count 0 2006.176.07:34:42.66#ibcon#about to write, iclass 3, count 0 2006.176.07:34:42.66#ibcon#wrote, iclass 3, count 0 2006.176.07:34:42.66#ibcon#about to read 3, iclass 3, count 0 2006.176.07:34:42.69#ibcon#read 3, iclass 3, count 0 2006.176.07:34:42.69#ibcon#about to read 4, iclass 3, count 0 2006.176.07:34:42.69#ibcon#read 4, iclass 3, count 0 2006.176.07:34:42.69#ibcon#about to read 5, iclass 3, count 0 2006.176.07:34:42.69#ibcon#read 5, iclass 3, count 0 2006.176.07:34:42.69#ibcon#about to read 6, iclass 3, count 0 2006.176.07:34:42.69#ibcon#read 6, iclass 3, count 0 2006.176.07:34:42.69#ibcon#end of sib2, iclass 3, count 0 2006.176.07:34:42.69#ibcon#*after write, iclass 3, count 0 2006.176.07:34:42.69#ibcon#*before return 0, iclass 3, count 0 2006.176.07:34:42.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:42.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:34:42.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:34:42.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:34:42.69$vc4f8/vbbw=wide 2006.176.07:34:42.69#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.07:34:42.69#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.07:34:42.69#ibcon#ireg 8 cls_cnt 0 2006.176.07:34:42.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:34:42.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:34:42.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:34:42.76#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:34:42.76#ibcon#first serial, iclass 5, count 0 2006.176.07:34:42.76#ibcon#enter sib2, iclass 5, count 0 2006.176.07:34:42.76#ibcon#flushed, iclass 5, count 0 2006.176.07:34:42.76#ibcon#about to write, iclass 5, count 0 2006.176.07:34:42.76#ibcon#wrote, iclass 5, count 0 2006.176.07:34:42.76#ibcon#about to read 3, iclass 5, count 0 2006.176.07:34:42.78#ibcon#read 3, iclass 5, count 0 2006.176.07:34:42.78#ibcon#about to read 4, iclass 5, count 0 2006.176.07:34:42.78#ibcon#read 4, iclass 5, count 0 2006.176.07:34:42.78#ibcon#about to read 5, iclass 5, count 0 2006.176.07:34:42.78#ibcon#read 5, iclass 5, count 0 2006.176.07:34:42.78#ibcon#about to read 6, iclass 5, count 0 2006.176.07:34:42.78#ibcon#read 6, iclass 5, count 0 2006.176.07:34:42.78#ibcon#end of sib2, iclass 5, count 0 2006.176.07:34:42.78#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:34:42.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:34:42.78#ibcon#[27=BW32\r\n] 2006.176.07:34:42.78#ibcon#*before write, iclass 5, count 0 2006.176.07:34:42.78#ibcon#enter sib2, iclass 5, count 0 2006.176.07:34:42.78#ibcon#flushed, iclass 5, count 0 2006.176.07:34:42.78#ibcon#about to write, iclass 5, count 0 2006.176.07:34:42.78#ibcon#wrote, iclass 5, count 0 2006.176.07:34:42.78#ibcon#about to read 3, iclass 5, count 0 2006.176.07:34:42.81#ibcon#read 3, iclass 5, count 0 2006.176.07:34:42.81#ibcon#about to read 4, iclass 5, count 0 2006.176.07:34:42.81#ibcon#read 4, iclass 5, count 0 2006.176.07:34:42.81#ibcon#about to read 5, iclass 5, count 0 2006.176.07:34:42.81#ibcon#read 5, iclass 5, count 0 2006.176.07:34:42.81#ibcon#about to read 6, iclass 5, count 0 2006.176.07:34:42.81#ibcon#read 6, iclass 5, count 0 2006.176.07:34:42.81#ibcon#end of sib2, iclass 5, count 0 2006.176.07:34:42.81#ibcon#*after write, iclass 5, count 0 2006.176.07:34:42.81#ibcon#*before return 0, iclass 5, count 0 2006.176.07:34:42.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:34:42.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:34:42.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:34:42.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:34:42.81$4f8m12a/ifd4f 2006.176.07:34:42.81$ifd4f/lo= 2006.176.07:34:42.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:34:42.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:34:42.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:34:42.81$ifd4f/patch= 2006.176.07:34:42.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:34:42.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:34:42.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:34:42.81$4f8m12a/"form=m,16.000,1:2 2006.176.07:34:42.81$4f8m12a/"tpicd 2006.176.07:34:42.81$4f8m12a/echo=off 2006.176.07:34:42.81$4f8m12a/xlog=off 2006.176.07:34:42.81:!2006.176.07:35:10 2006.176.07:34:52.14#trakl#Source acquired 2006.176.07:34:52.14#flagr#flagr/antenna,acquired 2006.176.07:35:10.00:preob 2006.176.07:35:11.14/onsource/TRACKING 2006.176.07:35:11.14:!2006.176.07:35:20 2006.176.07:35:20.00:data_valid=on 2006.176.07:35:20.00:midob 2006.176.07:35:20.14/onsource/TRACKING 2006.176.07:35:20.14/wx/23.98,1008.4,91 2006.176.07:35:20.25/cable/+6.4951E-03 2006.176.07:35:21.34/va/01,08,usb,yes,29,30 2006.176.07:35:21.34/va/02,07,usb,yes,29,30 2006.176.07:35:21.34/va/03,06,usb,yes,30,31 2006.176.07:35:21.34/va/04,07,usb,yes,30,32 2006.176.07:35:21.34/va/05,07,usb,yes,31,33 2006.176.07:35:21.34/va/06,06,usb,yes,30,30 2006.176.07:35:21.34/va/07,06,usb,yes,30,30 2006.176.07:35:21.34/va/08,06,usb,yes,33,32 2006.176.07:35:21.57/valo/01,532.99,yes,locked 2006.176.07:35:21.57/valo/02,572.99,yes,locked 2006.176.07:35:21.57/valo/03,672.99,yes,locked 2006.176.07:35:21.57/valo/04,832.99,yes,locked 2006.176.07:35:21.57/valo/05,652.99,yes,locked 2006.176.07:35:21.57/valo/06,772.99,yes,locked 2006.176.07:35:21.57/valo/07,832.99,yes,locked 2006.176.07:35:21.57/valo/08,852.99,yes,locked 2006.176.07:35:22.66/vb/01,04,usb,yes,29,28 2006.176.07:35:22.66/vb/02,04,usb,yes,31,32 2006.176.07:35:22.66/vb/03,04,usb,yes,27,31 2006.176.07:35:22.66/vb/04,04,usb,yes,28,28 2006.176.07:35:22.66/vb/05,04,usb,yes,26,30 2006.176.07:35:22.66/vb/06,04,usb,yes,27,30 2006.176.07:35:22.66/vb/07,04,usb,yes,29,29 2006.176.07:35:22.66/vb/08,04,usb,yes,27,30 2006.176.07:35:22.89/vblo/01,632.99,yes,locked 2006.176.07:35:22.89/vblo/02,640.99,yes,locked 2006.176.07:35:22.89/vblo/03,656.99,yes,locked 2006.176.07:35:22.89/vblo/04,712.99,yes,locked 2006.176.07:35:22.89/vblo/05,744.99,yes,locked 2006.176.07:35:22.89/vblo/06,752.99,yes,locked 2006.176.07:35:22.89/vblo/07,734.99,yes,locked 2006.176.07:35:22.89/vblo/08,744.99,yes,locked 2006.176.07:35:23.04/vabw/8 2006.176.07:35:23.19/vbbw/8 2006.176.07:35:23.28/xfe/off,on,15.0 2006.176.07:35:23.67/ifatt/23,28,28,28 2006.176.07:35:24.07/fmout-gps/S +3.72E-07 2006.176.07:35:24.15:!2006.176.07:36:20 2006.176.07:36:20.00:data_valid=off 2006.176.07:36:20.00:postob 2006.176.07:36:20.16/cable/+6.4921E-03 2006.176.07:36:20.16/wx/23.97,1008.4,91 2006.176.07:36:21.07/fmout-gps/S +3.72E-07 2006.176.07:36:21.07:scan_name=176-0737,k06176,60 2006.176.07:36:21.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.176.07:36:21.14#flagr#flagr/antenna,new-source 2006.176.07:36:22.14:checkk5 2006.176.07:36:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:36:22.92/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:36:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:36:23.67/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:36:24.04/chk_obsdata//k5ts1/T1760735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:36:24.41/chk_obsdata//k5ts2/T1760735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:36:24.79/chk_obsdata//k5ts3/T1760735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:36:25.16/chk_obsdata//k5ts4/T1760735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:36:25.85/k5log//k5ts1_log_newline 2006.176.07:36:26.54/k5log//k5ts2_log_newline 2006.176.07:36:27.23/k5log//k5ts3_log_newline 2006.176.07:36:27.93/k5log//k5ts4_log_newline 2006.176.07:36:27.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:36:27.95:4f8m12a=1 2006.176.07:36:27.95$4f8m12a/echo=on 2006.176.07:36:27.95$4f8m12a/pcalon 2006.176.07:36:27.95$pcalon/"no phase cal control is implemented here 2006.176.07:36:27.95$4f8m12a/"tpicd=stop 2006.176.07:36:27.95$4f8m12a/vc4f8 2006.176.07:36:27.95$vc4f8/valo=1,532.99 2006.176.07:36:27.95#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.07:36:27.95#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.07:36:27.95#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:27.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:27.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:27.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:27.95#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:36:27.95#ibcon#first serial, iclass 18, count 0 2006.176.07:36:27.95#ibcon#enter sib2, iclass 18, count 0 2006.176.07:36:27.95#ibcon#flushed, iclass 18, count 0 2006.176.07:36:27.95#ibcon#about to write, iclass 18, count 0 2006.176.07:36:27.96#ibcon#wrote, iclass 18, count 0 2006.176.07:36:27.96#ibcon#about to read 3, iclass 18, count 0 2006.176.07:36:28.00#ibcon#read 3, iclass 18, count 0 2006.176.07:36:28.00#ibcon#about to read 4, iclass 18, count 0 2006.176.07:36:28.00#ibcon#read 4, iclass 18, count 0 2006.176.07:36:28.00#ibcon#about to read 5, iclass 18, count 0 2006.176.07:36:28.00#ibcon#read 5, iclass 18, count 0 2006.176.07:36:28.00#ibcon#about to read 6, iclass 18, count 0 2006.176.07:36:28.00#ibcon#read 6, iclass 18, count 0 2006.176.07:36:28.00#ibcon#end of sib2, iclass 18, count 0 2006.176.07:36:28.00#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:36:28.00#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:36:28.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:36:28.00#ibcon#*before write, iclass 18, count 0 2006.176.07:36:28.00#ibcon#enter sib2, iclass 18, count 0 2006.176.07:36:28.00#ibcon#flushed, iclass 18, count 0 2006.176.07:36:28.00#ibcon#about to write, iclass 18, count 0 2006.176.07:36:28.00#ibcon#wrote, iclass 18, count 0 2006.176.07:36:28.00#ibcon#about to read 3, iclass 18, count 0 2006.176.07:36:28.05#ibcon#read 3, iclass 18, count 0 2006.176.07:36:28.05#ibcon#about to read 4, iclass 18, count 0 2006.176.07:36:28.05#ibcon#read 4, iclass 18, count 0 2006.176.07:36:28.05#ibcon#about to read 5, iclass 18, count 0 2006.176.07:36:28.05#ibcon#read 5, iclass 18, count 0 2006.176.07:36:28.05#ibcon#about to read 6, iclass 18, count 0 2006.176.07:36:28.05#ibcon#read 6, iclass 18, count 0 2006.176.07:36:28.05#ibcon#end of sib2, iclass 18, count 0 2006.176.07:36:28.05#ibcon#*after write, iclass 18, count 0 2006.176.07:36:28.05#ibcon#*before return 0, iclass 18, count 0 2006.176.07:36:28.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:28.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:28.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:36:28.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:36:28.05$vc4f8/va=1,8 2006.176.07:36:28.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.07:36:28.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.07:36:28.05#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:28.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:28.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:28.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:28.05#ibcon#enter wrdev, iclass 20, count 2 2006.176.07:36:28.05#ibcon#first serial, iclass 20, count 2 2006.176.07:36:28.05#ibcon#enter sib2, iclass 20, count 2 2006.176.07:36:28.05#ibcon#flushed, iclass 20, count 2 2006.176.07:36:28.05#ibcon#about to write, iclass 20, count 2 2006.176.07:36:28.05#ibcon#wrote, iclass 20, count 2 2006.176.07:36:28.05#ibcon#about to read 3, iclass 20, count 2 2006.176.07:36:28.07#ibcon#read 3, iclass 20, count 2 2006.176.07:36:28.07#ibcon#about to read 4, iclass 20, count 2 2006.176.07:36:28.07#ibcon#read 4, iclass 20, count 2 2006.176.07:36:28.07#ibcon#about to read 5, iclass 20, count 2 2006.176.07:36:28.07#ibcon#read 5, iclass 20, count 2 2006.176.07:36:28.07#ibcon#about to read 6, iclass 20, count 2 2006.176.07:36:28.07#ibcon#read 6, iclass 20, count 2 2006.176.07:36:28.07#ibcon#end of sib2, iclass 20, count 2 2006.176.07:36:28.07#ibcon#*mode == 0, iclass 20, count 2 2006.176.07:36:28.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.07:36:28.07#ibcon#[25=AT01-08\r\n] 2006.176.07:36:28.07#ibcon#*before write, iclass 20, count 2 2006.176.07:36:28.07#ibcon#enter sib2, iclass 20, count 2 2006.176.07:36:28.07#ibcon#flushed, iclass 20, count 2 2006.176.07:36:28.07#ibcon#about to write, iclass 20, count 2 2006.176.07:36:28.07#ibcon#wrote, iclass 20, count 2 2006.176.07:36:28.07#ibcon#about to read 3, iclass 20, count 2 2006.176.07:36:28.10#ibcon#read 3, iclass 20, count 2 2006.176.07:36:28.10#ibcon#about to read 4, iclass 20, count 2 2006.176.07:36:28.10#ibcon#read 4, iclass 20, count 2 2006.176.07:36:28.10#ibcon#about to read 5, iclass 20, count 2 2006.176.07:36:28.10#ibcon#read 5, iclass 20, count 2 2006.176.07:36:28.10#ibcon#about to read 6, iclass 20, count 2 2006.176.07:36:28.10#ibcon#read 6, iclass 20, count 2 2006.176.07:36:28.10#ibcon#end of sib2, iclass 20, count 2 2006.176.07:36:28.10#ibcon#*after write, iclass 20, count 2 2006.176.07:36:28.10#ibcon#*before return 0, iclass 20, count 2 2006.176.07:36:28.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:28.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:28.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.07:36:28.10#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:28.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:28.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:28.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:28.22#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:36:28.22#ibcon#first serial, iclass 20, count 0 2006.176.07:36:28.22#ibcon#enter sib2, iclass 20, count 0 2006.176.07:36:28.22#ibcon#flushed, iclass 20, count 0 2006.176.07:36:28.22#ibcon#about to write, iclass 20, count 0 2006.176.07:36:28.22#ibcon#wrote, iclass 20, count 0 2006.176.07:36:28.22#ibcon#about to read 3, iclass 20, count 0 2006.176.07:36:28.24#ibcon#read 3, iclass 20, count 0 2006.176.07:36:28.24#ibcon#about to read 4, iclass 20, count 0 2006.176.07:36:28.24#ibcon#read 4, iclass 20, count 0 2006.176.07:36:28.24#ibcon#about to read 5, iclass 20, count 0 2006.176.07:36:28.24#ibcon#read 5, iclass 20, count 0 2006.176.07:36:28.24#ibcon#about to read 6, iclass 20, count 0 2006.176.07:36:28.24#ibcon#read 6, iclass 20, count 0 2006.176.07:36:28.24#ibcon#end of sib2, iclass 20, count 0 2006.176.07:36:28.24#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:36:28.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:36:28.24#ibcon#[25=USB\r\n] 2006.176.07:36:28.24#ibcon#*before write, iclass 20, count 0 2006.176.07:36:28.24#ibcon#enter sib2, iclass 20, count 0 2006.176.07:36:28.24#ibcon#flushed, iclass 20, count 0 2006.176.07:36:28.24#ibcon#about to write, iclass 20, count 0 2006.176.07:36:28.24#ibcon#wrote, iclass 20, count 0 2006.176.07:36:28.24#ibcon#about to read 3, iclass 20, count 0 2006.176.07:36:28.28#ibcon#read 3, iclass 20, count 0 2006.176.07:36:28.28#ibcon#about to read 4, iclass 20, count 0 2006.176.07:36:28.28#ibcon#read 4, iclass 20, count 0 2006.176.07:36:28.28#ibcon#about to read 5, iclass 20, count 0 2006.176.07:36:28.28#ibcon#read 5, iclass 20, count 0 2006.176.07:36:28.28#ibcon#about to read 6, iclass 20, count 0 2006.176.07:36:28.28#ibcon#read 6, iclass 20, count 0 2006.176.07:36:28.28#ibcon#end of sib2, iclass 20, count 0 2006.176.07:36:28.28#ibcon#*after write, iclass 20, count 0 2006.176.07:36:28.28#ibcon#*before return 0, iclass 20, count 0 2006.176.07:36:28.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:28.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:28.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:36:28.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:36:28.28$vc4f8/valo=2,572.99 2006.176.07:36:28.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.07:36:28.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.07:36:28.28#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:28.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:28.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:28.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:28.28#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:36:28.28#ibcon#first serial, iclass 22, count 0 2006.176.07:36:28.28#ibcon#enter sib2, iclass 22, count 0 2006.176.07:36:28.28#ibcon#flushed, iclass 22, count 0 2006.176.07:36:28.28#ibcon#about to write, iclass 22, count 0 2006.176.07:36:28.28#ibcon#wrote, iclass 22, count 0 2006.176.07:36:28.28#ibcon#about to read 3, iclass 22, count 0 2006.176.07:36:28.29#ibcon#read 3, iclass 22, count 0 2006.176.07:36:28.29#ibcon#about to read 4, iclass 22, count 0 2006.176.07:36:28.29#ibcon#read 4, iclass 22, count 0 2006.176.07:36:28.29#ibcon#about to read 5, iclass 22, count 0 2006.176.07:36:28.29#ibcon#read 5, iclass 22, count 0 2006.176.07:36:28.29#ibcon#about to read 6, iclass 22, count 0 2006.176.07:36:28.29#ibcon#read 6, iclass 22, count 0 2006.176.07:36:28.29#ibcon#end of sib2, iclass 22, count 0 2006.176.07:36:28.29#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:36:28.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:36:28.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:36:28.29#ibcon#*before write, iclass 22, count 0 2006.176.07:36:28.29#ibcon#enter sib2, iclass 22, count 0 2006.176.07:36:28.29#ibcon#flushed, iclass 22, count 0 2006.176.07:36:28.29#ibcon#about to write, iclass 22, count 0 2006.176.07:36:28.29#ibcon#wrote, iclass 22, count 0 2006.176.07:36:28.29#ibcon#about to read 3, iclass 22, count 0 2006.176.07:36:28.33#ibcon#read 3, iclass 22, count 0 2006.176.07:36:28.33#ibcon#about to read 4, iclass 22, count 0 2006.176.07:36:28.33#ibcon#read 4, iclass 22, count 0 2006.176.07:36:28.33#ibcon#about to read 5, iclass 22, count 0 2006.176.07:36:28.33#ibcon#read 5, iclass 22, count 0 2006.176.07:36:28.33#ibcon#about to read 6, iclass 22, count 0 2006.176.07:36:28.33#ibcon#read 6, iclass 22, count 0 2006.176.07:36:28.33#ibcon#end of sib2, iclass 22, count 0 2006.176.07:36:28.33#ibcon#*after write, iclass 22, count 0 2006.176.07:36:28.33#ibcon#*before return 0, iclass 22, count 0 2006.176.07:36:28.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:28.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:28.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:36:28.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:36:28.33$vc4f8/va=2,7 2006.176.07:36:28.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.07:36:28.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.07:36:28.33#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:28.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:28.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:28.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:28.40#ibcon#enter wrdev, iclass 24, count 2 2006.176.07:36:28.40#ibcon#first serial, iclass 24, count 2 2006.176.07:36:28.40#ibcon#enter sib2, iclass 24, count 2 2006.176.07:36:28.40#ibcon#flushed, iclass 24, count 2 2006.176.07:36:28.40#ibcon#about to write, iclass 24, count 2 2006.176.07:36:28.40#ibcon#wrote, iclass 24, count 2 2006.176.07:36:28.40#ibcon#about to read 3, iclass 24, count 2 2006.176.07:36:28.42#ibcon#read 3, iclass 24, count 2 2006.176.07:36:28.42#ibcon#about to read 4, iclass 24, count 2 2006.176.07:36:28.42#ibcon#read 4, iclass 24, count 2 2006.176.07:36:28.42#ibcon#about to read 5, iclass 24, count 2 2006.176.07:36:28.42#ibcon#read 5, iclass 24, count 2 2006.176.07:36:28.42#ibcon#about to read 6, iclass 24, count 2 2006.176.07:36:28.42#ibcon#read 6, iclass 24, count 2 2006.176.07:36:28.42#ibcon#end of sib2, iclass 24, count 2 2006.176.07:36:28.42#ibcon#*mode == 0, iclass 24, count 2 2006.176.07:36:28.42#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.07:36:28.42#ibcon#[25=AT02-07\r\n] 2006.176.07:36:28.42#ibcon#*before write, iclass 24, count 2 2006.176.07:36:28.42#ibcon#enter sib2, iclass 24, count 2 2006.176.07:36:28.42#ibcon#flushed, iclass 24, count 2 2006.176.07:36:28.42#ibcon#about to write, iclass 24, count 2 2006.176.07:36:28.42#ibcon#wrote, iclass 24, count 2 2006.176.07:36:28.42#ibcon#about to read 3, iclass 24, count 2 2006.176.07:36:28.45#ibcon#read 3, iclass 24, count 2 2006.176.07:36:28.45#ibcon#about to read 4, iclass 24, count 2 2006.176.07:36:28.45#ibcon#read 4, iclass 24, count 2 2006.176.07:36:28.45#ibcon#about to read 5, iclass 24, count 2 2006.176.07:36:28.45#ibcon#read 5, iclass 24, count 2 2006.176.07:36:28.45#ibcon#about to read 6, iclass 24, count 2 2006.176.07:36:28.45#ibcon#read 6, iclass 24, count 2 2006.176.07:36:28.45#ibcon#end of sib2, iclass 24, count 2 2006.176.07:36:28.45#ibcon#*after write, iclass 24, count 2 2006.176.07:36:28.45#ibcon#*before return 0, iclass 24, count 2 2006.176.07:36:28.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:28.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:28.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.07:36:28.45#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:28.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:28.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:28.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:28.57#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:36:28.57#ibcon#first serial, iclass 24, count 0 2006.176.07:36:28.57#ibcon#enter sib2, iclass 24, count 0 2006.176.07:36:28.57#ibcon#flushed, iclass 24, count 0 2006.176.07:36:28.57#ibcon#about to write, iclass 24, count 0 2006.176.07:36:28.57#ibcon#wrote, iclass 24, count 0 2006.176.07:36:28.57#ibcon#about to read 3, iclass 24, count 0 2006.176.07:36:28.59#ibcon#read 3, iclass 24, count 0 2006.176.07:36:28.59#ibcon#about to read 4, iclass 24, count 0 2006.176.07:36:28.59#ibcon#read 4, iclass 24, count 0 2006.176.07:36:28.59#ibcon#about to read 5, iclass 24, count 0 2006.176.07:36:28.59#ibcon#read 5, iclass 24, count 0 2006.176.07:36:28.59#ibcon#about to read 6, iclass 24, count 0 2006.176.07:36:28.59#ibcon#read 6, iclass 24, count 0 2006.176.07:36:28.59#ibcon#end of sib2, iclass 24, count 0 2006.176.07:36:28.59#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:36:28.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:36:28.59#ibcon#[25=USB\r\n] 2006.176.07:36:28.59#ibcon#*before write, iclass 24, count 0 2006.176.07:36:28.59#ibcon#enter sib2, iclass 24, count 0 2006.176.07:36:28.59#ibcon#flushed, iclass 24, count 0 2006.176.07:36:28.59#ibcon#about to write, iclass 24, count 0 2006.176.07:36:28.59#ibcon#wrote, iclass 24, count 0 2006.176.07:36:28.59#ibcon#about to read 3, iclass 24, count 0 2006.176.07:36:28.62#ibcon#read 3, iclass 24, count 0 2006.176.07:36:28.62#ibcon#about to read 4, iclass 24, count 0 2006.176.07:36:28.62#ibcon#read 4, iclass 24, count 0 2006.176.07:36:28.62#ibcon#about to read 5, iclass 24, count 0 2006.176.07:36:28.62#ibcon#read 5, iclass 24, count 0 2006.176.07:36:28.62#ibcon#about to read 6, iclass 24, count 0 2006.176.07:36:28.62#ibcon#read 6, iclass 24, count 0 2006.176.07:36:28.62#ibcon#end of sib2, iclass 24, count 0 2006.176.07:36:28.62#ibcon#*after write, iclass 24, count 0 2006.176.07:36:28.62#ibcon#*before return 0, iclass 24, count 0 2006.176.07:36:28.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:28.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:28.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:36:28.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:36:28.62$vc4f8/valo=3,672.99 2006.176.07:36:28.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.07:36:28.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.07:36:28.62#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:28.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:28.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:28.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:28.62#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:36:28.62#ibcon#first serial, iclass 26, count 0 2006.176.07:36:28.62#ibcon#enter sib2, iclass 26, count 0 2006.176.07:36:28.62#ibcon#flushed, iclass 26, count 0 2006.176.07:36:28.62#ibcon#about to write, iclass 26, count 0 2006.176.07:36:28.62#ibcon#wrote, iclass 26, count 0 2006.176.07:36:28.62#ibcon#about to read 3, iclass 26, count 0 2006.176.07:36:28.64#ibcon#read 3, iclass 26, count 0 2006.176.07:36:28.64#ibcon#about to read 4, iclass 26, count 0 2006.176.07:36:28.64#ibcon#read 4, iclass 26, count 0 2006.176.07:36:28.64#ibcon#about to read 5, iclass 26, count 0 2006.176.07:36:28.64#ibcon#read 5, iclass 26, count 0 2006.176.07:36:28.64#ibcon#about to read 6, iclass 26, count 0 2006.176.07:36:28.64#ibcon#read 6, iclass 26, count 0 2006.176.07:36:28.64#ibcon#end of sib2, iclass 26, count 0 2006.176.07:36:28.64#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:36:28.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:36:28.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:36:28.64#ibcon#*before write, iclass 26, count 0 2006.176.07:36:28.64#ibcon#enter sib2, iclass 26, count 0 2006.176.07:36:28.64#ibcon#flushed, iclass 26, count 0 2006.176.07:36:28.64#ibcon#about to write, iclass 26, count 0 2006.176.07:36:28.64#ibcon#wrote, iclass 26, count 0 2006.176.07:36:28.64#ibcon#about to read 3, iclass 26, count 0 2006.176.07:36:28.68#ibcon#read 3, iclass 26, count 0 2006.176.07:36:28.68#ibcon#about to read 4, iclass 26, count 0 2006.176.07:36:28.68#ibcon#read 4, iclass 26, count 0 2006.176.07:36:28.68#ibcon#about to read 5, iclass 26, count 0 2006.176.07:36:28.68#ibcon#read 5, iclass 26, count 0 2006.176.07:36:28.68#ibcon#about to read 6, iclass 26, count 0 2006.176.07:36:28.68#ibcon#read 6, iclass 26, count 0 2006.176.07:36:28.68#ibcon#end of sib2, iclass 26, count 0 2006.176.07:36:28.68#ibcon#*after write, iclass 26, count 0 2006.176.07:36:28.68#ibcon#*before return 0, iclass 26, count 0 2006.176.07:36:28.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:28.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:28.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:36:28.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:36:28.68$vc4f8/va=3,6 2006.176.07:36:28.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.07:36:28.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.07:36:28.68#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:28.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:28.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:28.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:28.74#ibcon#enter wrdev, iclass 28, count 2 2006.176.07:36:28.74#ibcon#first serial, iclass 28, count 2 2006.176.07:36:28.74#ibcon#enter sib2, iclass 28, count 2 2006.176.07:36:28.74#ibcon#flushed, iclass 28, count 2 2006.176.07:36:28.74#ibcon#about to write, iclass 28, count 2 2006.176.07:36:28.74#ibcon#wrote, iclass 28, count 2 2006.176.07:36:28.74#ibcon#about to read 3, iclass 28, count 2 2006.176.07:36:28.76#ibcon#read 3, iclass 28, count 2 2006.176.07:36:28.76#ibcon#about to read 4, iclass 28, count 2 2006.176.07:36:28.76#ibcon#read 4, iclass 28, count 2 2006.176.07:36:28.76#ibcon#about to read 5, iclass 28, count 2 2006.176.07:36:28.76#ibcon#read 5, iclass 28, count 2 2006.176.07:36:28.76#ibcon#about to read 6, iclass 28, count 2 2006.176.07:36:28.76#ibcon#read 6, iclass 28, count 2 2006.176.07:36:28.76#ibcon#end of sib2, iclass 28, count 2 2006.176.07:36:28.76#ibcon#*mode == 0, iclass 28, count 2 2006.176.07:36:28.76#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.07:36:28.76#ibcon#[25=AT03-06\r\n] 2006.176.07:36:28.76#ibcon#*before write, iclass 28, count 2 2006.176.07:36:28.76#ibcon#enter sib2, iclass 28, count 2 2006.176.07:36:28.76#ibcon#flushed, iclass 28, count 2 2006.176.07:36:28.76#ibcon#about to write, iclass 28, count 2 2006.176.07:36:28.76#ibcon#wrote, iclass 28, count 2 2006.176.07:36:28.76#ibcon#about to read 3, iclass 28, count 2 2006.176.07:36:28.79#ibcon#read 3, iclass 28, count 2 2006.176.07:36:28.79#ibcon#about to read 4, iclass 28, count 2 2006.176.07:36:28.79#ibcon#read 4, iclass 28, count 2 2006.176.07:36:28.79#ibcon#about to read 5, iclass 28, count 2 2006.176.07:36:28.79#ibcon#read 5, iclass 28, count 2 2006.176.07:36:28.79#ibcon#about to read 6, iclass 28, count 2 2006.176.07:36:28.79#ibcon#read 6, iclass 28, count 2 2006.176.07:36:28.79#ibcon#end of sib2, iclass 28, count 2 2006.176.07:36:28.79#ibcon#*after write, iclass 28, count 2 2006.176.07:36:28.79#ibcon#*before return 0, iclass 28, count 2 2006.176.07:36:28.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:28.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:28.79#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.07:36:28.79#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:28.79#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:28.91#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:28.91#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:28.91#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:36:28.91#ibcon#first serial, iclass 28, count 0 2006.176.07:36:28.91#ibcon#enter sib2, iclass 28, count 0 2006.176.07:36:28.91#ibcon#flushed, iclass 28, count 0 2006.176.07:36:28.91#ibcon#about to write, iclass 28, count 0 2006.176.07:36:28.91#ibcon#wrote, iclass 28, count 0 2006.176.07:36:28.91#ibcon#about to read 3, iclass 28, count 0 2006.176.07:36:28.93#ibcon#read 3, iclass 28, count 0 2006.176.07:36:28.93#ibcon#about to read 4, iclass 28, count 0 2006.176.07:36:28.93#ibcon#read 4, iclass 28, count 0 2006.176.07:36:28.93#ibcon#about to read 5, iclass 28, count 0 2006.176.07:36:28.93#ibcon#read 5, iclass 28, count 0 2006.176.07:36:28.93#ibcon#about to read 6, iclass 28, count 0 2006.176.07:36:28.93#ibcon#read 6, iclass 28, count 0 2006.176.07:36:28.93#ibcon#end of sib2, iclass 28, count 0 2006.176.07:36:28.93#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:36:28.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:36:28.93#ibcon#[25=USB\r\n] 2006.176.07:36:28.93#ibcon#*before write, iclass 28, count 0 2006.176.07:36:28.93#ibcon#enter sib2, iclass 28, count 0 2006.176.07:36:28.93#ibcon#flushed, iclass 28, count 0 2006.176.07:36:28.93#ibcon#about to write, iclass 28, count 0 2006.176.07:36:28.93#ibcon#wrote, iclass 28, count 0 2006.176.07:36:28.93#ibcon#about to read 3, iclass 28, count 0 2006.176.07:36:28.96#ibcon#read 3, iclass 28, count 0 2006.176.07:36:28.96#ibcon#about to read 4, iclass 28, count 0 2006.176.07:36:28.96#ibcon#read 4, iclass 28, count 0 2006.176.07:36:28.96#ibcon#about to read 5, iclass 28, count 0 2006.176.07:36:28.96#ibcon#read 5, iclass 28, count 0 2006.176.07:36:28.96#ibcon#about to read 6, iclass 28, count 0 2006.176.07:36:28.96#ibcon#read 6, iclass 28, count 0 2006.176.07:36:28.96#ibcon#end of sib2, iclass 28, count 0 2006.176.07:36:28.96#ibcon#*after write, iclass 28, count 0 2006.176.07:36:28.96#ibcon#*before return 0, iclass 28, count 0 2006.176.07:36:28.96#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:28.96#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:28.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:36:28.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:36:28.96$vc4f8/valo=4,832.99 2006.176.07:36:28.96#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.07:36:28.96#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.07:36:28.96#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:28.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:28.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:28.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:28.96#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:36:28.96#ibcon#first serial, iclass 30, count 0 2006.176.07:36:28.96#ibcon#enter sib2, iclass 30, count 0 2006.176.07:36:28.96#ibcon#flushed, iclass 30, count 0 2006.176.07:36:28.96#ibcon#about to write, iclass 30, count 0 2006.176.07:36:28.96#ibcon#wrote, iclass 30, count 0 2006.176.07:36:28.96#ibcon#about to read 3, iclass 30, count 0 2006.176.07:36:28.98#ibcon#read 3, iclass 30, count 0 2006.176.07:36:28.98#ibcon#about to read 4, iclass 30, count 0 2006.176.07:36:28.98#ibcon#read 4, iclass 30, count 0 2006.176.07:36:28.98#ibcon#about to read 5, iclass 30, count 0 2006.176.07:36:28.98#ibcon#read 5, iclass 30, count 0 2006.176.07:36:28.98#ibcon#about to read 6, iclass 30, count 0 2006.176.07:36:28.98#ibcon#read 6, iclass 30, count 0 2006.176.07:36:28.98#ibcon#end of sib2, iclass 30, count 0 2006.176.07:36:28.98#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:36:28.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:36:28.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:36:28.98#ibcon#*before write, iclass 30, count 0 2006.176.07:36:28.98#ibcon#enter sib2, iclass 30, count 0 2006.176.07:36:28.98#ibcon#flushed, iclass 30, count 0 2006.176.07:36:28.98#ibcon#about to write, iclass 30, count 0 2006.176.07:36:28.98#ibcon#wrote, iclass 30, count 0 2006.176.07:36:28.98#ibcon#about to read 3, iclass 30, count 0 2006.176.07:36:29.02#ibcon#read 3, iclass 30, count 0 2006.176.07:36:29.02#ibcon#about to read 4, iclass 30, count 0 2006.176.07:36:29.02#ibcon#read 4, iclass 30, count 0 2006.176.07:36:29.02#ibcon#about to read 5, iclass 30, count 0 2006.176.07:36:29.02#ibcon#read 5, iclass 30, count 0 2006.176.07:36:29.02#ibcon#about to read 6, iclass 30, count 0 2006.176.07:36:29.02#ibcon#read 6, iclass 30, count 0 2006.176.07:36:29.02#ibcon#end of sib2, iclass 30, count 0 2006.176.07:36:29.02#ibcon#*after write, iclass 30, count 0 2006.176.07:36:29.02#ibcon#*before return 0, iclass 30, count 0 2006.176.07:36:29.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:29.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:29.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:36:29.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:36:29.02$vc4f8/va=4,7 2006.176.07:36:29.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.176.07:36:29.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.176.07:36:29.02#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:29.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:29.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:29.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:29.08#ibcon#enter wrdev, iclass 32, count 2 2006.176.07:36:29.08#ibcon#first serial, iclass 32, count 2 2006.176.07:36:29.08#ibcon#enter sib2, iclass 32, count 2 2006.176.07:36:29.08#ibcon#flushed, iclass 32, count 2 2006.176.07:36:29.08#ibcon#about to write, iclass 32, count 2 2006.176.07:36:29.08#ibcon#wrote, iclass 32, count 2 2006.176.07:36:29.08#ibcon#about to read 3, iclass 32, count 2 2006.176.07:36:29.10#ibcon#read 3, iclass 32, count 2 2006.176.07:36:29.10#ibcon#about to read 4, iclass 32, count 2 2006.176.07:36:29.10#ibcon#read 4, iclass 32, count 2 2006.176.07:36:29.10#ibcon#about to read 5, iclass 32, count 2 2006.176.07:36:29.10#ibcon#read 5, iclass 32, count 2 2006.176.07:36:29.10#ibcon#about to read 6, iclass 32, count 2 2006.176.07:36:29.10#ibcon#read 6, iclass 32, count 2 2006.176.07:36:29.10#ibcon#end of sib2, iclass 32, count 2 2006.176.07:36:29.10#ibcon#*mode == 0, iclass 32, count 2 2006.176.07:36:29.10#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.176.07:36:29.10#ibcon#[25=AT04-07\r\n] 2006.176.07:36:29.10#ibcon#*before write, iclass 32, count 2 2006.176.07:36:29.10#ibcon#enter sib2, iclass 32, count 2 2006.176.07:36:29.10#ibcon#flushed, iclass 32, count 2 2006.176.07:36:29.10#ibcon#about to write, iclass 32, count 2 2006.176.07:36:29.10#ibcon#wrote, iclass 32, count 2 2006.176.07:36:29.10#ibcon#about to read 3, iclass 32, count 2 2006.176.07:36:29.13#ibcon#read 3, iclass 32, count 2 2006.176.07:36:29.13#ibcon#about to read 4, iclass 32, count 2 2006.176.07:36:29.13#ibcon#read 4, iclass 32, count 2 2006.176.07:36:29.13#ibcon#about to read 5, iclass 32, count 2 2006.176.07:36:29.13#ibcon#read 5, iclass 32, count 2 2006.176.07:36:29.13#ibcon#about to read 6, iclass 32, count 2 2006.176.07:36:29.13#ibcon#read 6, iclass 32, count 2 2006.176.07:36:29.13#ibcon#end of sib2, iclass 32, count 2 2006.176.07:36:29.13#ibcon#*after write, iclass 32, count 2 2006.176.07:36:29.13#ibcon#*before return 0, iclass 32, count 2 2006.176.07:36:29.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:29.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:29.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.176.07:36:29.13#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:29.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:29.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:29.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:29.25#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:36:29.25#ibcon#first serial, iclass 32, count 0 2006.176.07:36:29.25#ibcon#enter sib2, iclass 32, count 0 2006.176.07:36:29.25#ibcon#flushed, iclass 32, count 0 2006.176.07:36:29.25#ibcon#about to write, iclass 32, count 0 2006.176.07:36:29.25#ibcon#wrote, iclass 32, count 0 2006.176.07:36:29.25#ibcon#about to read 3, iclass 32, count 0 2006.176.07:36:29.27#ibcon#read 3, iclass 32, count 0 2006.176.07:36:29.27#ibcon#about to read 4, iclass 32, count 0 2006.176.07:36:29.27#ibcon#read 4, iclass 32, count 0 2006.176.07:36:29.27#ibcon#about to read 5, iclass 32, count 0 2006.176.07:36:29.27#ibcon#read 5, iclass 32, count 0 2006.176.07:36:29.27#ibcon#about to read 6, iclass 32, count 0 2006.176.07:36:29.27#ibcon#read 6, iclass 32, count 0 2006.176.07:36:29.27#ibcon#end of sib2, iclass 32, count 0 2006.176.07:36:29.27#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:36:29.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:36:29.27#ibcon#[25=USB\r\n] 2006.176.07:36:29.27#ibcon#*before write, iclass 32, count 0 2006.176.07:36:29.27#ibcon#enter sib2, iclass 32, count 0 2006.176.07:36:29.27#ibcon#flushed, iclass 32, count 0 2006.176.07:36:29.27#ibcon#about to write, iclass 32, count 0 2006.176.07:36:29.27#ibcon#wrote, iclass 32, count 0 2006.176.07:36:29.27#ibcon#about to read 3, iclass 32, count 0 2006.176.07:36:29.30#ibcon#read 3, iclass 32, count 0 2006.176.07:36:29.30#ibcon#about to read 4, iclass 32, count 0 2006.176.07:36:29.30#ibcon#read 4, iclass 32, count 0 2006.176.07:36:29.30#ibcon#about to read 5, iclass 32, count 0 2006.176.07:36:29.30#ibcon#read 5, iclass 32, count 0 2006.176.07:36:29.30#ibcon#about to read 6, iclass 32, count 0 2006.176.07:36:29.30#ibcon#read 6, iclass 32, count 0 2006.176.07:36:29.30#ibcon#end of sib2, iclass 32, count 0 2006.176.07:36:29.30#ibcon#*after write, iclass 32, count 0 2006.176.07:36:29.30#ibcon#*before return 0, iclass 32, count 0 2006.176.07:36:29.30#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:29.30#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:29.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:36:29.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:36:29.30$vc4f8/valo=5,652.99 2006.176.07:36:29.30#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.07:36:29.30#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.07:36:29.30#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:29.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:29.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:29.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:29.30#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:36:29.30#ibcon#first serial, iclass 34, count 0 2006.176.07:36:29.30#ibcon#enter sib2, iclass 34, count 0 2006.176.07:36:29.30#ibcon#flushed, iclass 34, count 0 2006.176.07:36:29.30#ibcon#about to write, iclass 34, count 0 2006.176.07:36:29.30#ibcon#wrote, iclass 34, count 0 2006.176.07:36:29.30#ibcon#about to read 3, iclass 34, count 0 2006.176.07:36:29.32#ibcon#read 3, iclass 34, count 0 2006.176.07:36:29.32#ibcon#about to read 4, iclass 34, count 0 2006.176.07:36:29.32#ibcon#read 4, iclass 34, count 0 2006.176.07:36:29.32#ibcon#about to read 5, iclass 34, count 0 2006.176.07:36:29.32#ibcon#read 5, iclass 34, count 0 2006.176.07:36:29.32#ibcon#about to read 6, iclass 34, count 0 2006.176.07:36:29.32#ibcon#read 6, iclass 34, count 0 2006.176.07:36:29.32#ibcon#end of sib2, iclass 34, count 0 2006.176.07:36:29.32#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:36:29.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:36:29.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:36:29.32#ibcon#*before write, iclass 34, count 0 2006.176.07:36:29.32#ibcon#enter sib2, iclass 34, count 0 2006.176.07:36:29.32#ibcon#flushed, iclass 34, count 0 2006.176.07:36:29.32#ibcon#about to write, iclass 34, count 0 2006.176.07:36:29.32#ibcon#wrote, iclass 34, count 0 2006.176.07:36:29.32#ibcon#about to read 3, iclass 34, count 0 2006.176.07:36:29.36#ibcon#read 3, iclass 34, count 0 2006.176.07:36:29.36#ibcon#about to read 4, iclass 34, count 0 2006.176.07:36:29.36#ibcon#read 4, iclass 34, count 0 2006.176.07:36:29.36#ibcon#about to read 5, iclass 34, count 0 2006.176.07:36:29.36#ibcon#read 5, iclass 34, count 0 2006.176.07:36:29.36#ibcon#about to read 6, iclass 34, count 0 2006.176.07:36:29.36#ibcon#read 6, iclass 34, count 0 2006.176.07:36:29.36#ibcon#end of sib2, iclass 34, count 0 2006.176.07:36:29.36#ibcon#*after write, iclass 34, count 0 2006.176.07:36:29.36#ibcon#*before return 0, iclass 34, count 0 2006.176.07:36:29.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:29.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:29.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:36:29.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:36:29.36$vc4f8/va=5,7 2006.176.07:36:29.36#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.176.07:36:29.36#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.176.07:36:29.36#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:29.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:29.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:29.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:29.42#ibcon#enter wrdev, iclass 36, count 2 2006.176.07:36:29.42#ibcon#first serial, iclass 36, count 2 2006.176.07:36:29.42#ibcon#enter sib2, iclass 36, count 2 2006.176.07:36:29.42#ibcon#flushed, iclass 36, count 2 2006.176.07:36:29.42#ibcon#about to write, iclass 36, count 2 2006.176.07:36:29.42#ibcon#wrote, iclass 36, count 2 2006.176.07:36:29.42#ibcon#about to read 3, iclass 36, count 2 2006.176.07:36:29.44#ibcon#read 3, iclass 36, count 2 2006.176.07:36:29.44#ibcon#about to read 4, iclass 36, count 2 2006.176.07:36:29.44#ibcon#read 4, iclass 36, count 2 2006.176.07:36:29.44#ibcon#about to read 5, iclass 36, count 2 2006.176.07:36:29.44#ibcon#read 5, iclass 36, count 2 2006.176.07:36:29.44#ibcon#about to read 6, iclass 36, count 2 2006.176.07:36:29.44#ibcon#read 6, iclass 36, count 2 2006.176.07:36:29.44#ibcon#end of sib2, iclass 36, count 2 2006.176.07:36:29.44#ibcon#*mode == 0, iclass 36, count 2 2006.176.07:36:29.44#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.176.07:36:29.44#ibcon#[25=AT05-07\r\n] 2006.176.07:36:29.44#ibcon#*before write, iclass 36, count 2 2006.176.07:36:29.44#ibcon#enter sib2, iclass 36, count 2 2006.176.07:36:29.44#ibcon#flushed, iclass 36, count 2 2006.176.07:36:29.44#ibcon#about to write, iclass 36, count 2 2006.176.07:36:29.44#ibcon#wrote, iclass 36, count 2 2006.176.07:36:29.44#ibcon#about to read 3, iclass 36, count 2 2006.176.07:36:29.47#ibcon#read 3, iclass 36, count 2 2006.176.07:36:29.47#ibcon#about to read 4, iclass 36, count 2 2006.176.07:36:29.47#ibcon#read 4, iclass 36, count 2 2006.176.07:36:29.47#ibcon#about to read 5, iclass 36, count 2 2006.176.07:36:29.47#ibcon#read 5, iclass 36, count 2 2006.176.07:36:29.47#ibcon#about to read 6, iclass 36, count 2 2006.176.07:36:29.47#ibcon#read 6, iclass 36, count 2 2006.176.07:36:29.47#ibcon#end of sib2, iclass 36, count 2 2006.176.07:36:29.47#ibcon#*after write, iclass 36, count 2 2006.176.07:36:29.47#ibcon#*before return 0, iclass 36, count 2 2006.176.07:36:29.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:29.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:29.47#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.176.07:36:29.47#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:29.47#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:29.59#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:29.59#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:29.59#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:36:29.59#ibcon#first serial, iclass 36, count 0 2006.176.07:36:29.59#ibcon#enter sib2, iclass 36, count 0 2006.176.07:36:29.59#ibcon#flushed, iclass 36, count 0 2006.176.07:36:29.59#ibcon#about to write, iclass 36, count 0 2006.176.07:36:29.59#ibcon#wrote, iclass 36, count 0 2006.176.07:36:29.59#ibcon#about to read 3, iclass 36, count 0 2006.176.07:36:29.61#ibcon#read 3, iclass 36, count 0 2006.176.07:36:29.61#ibcon#about to read 4, iclass 36, count 0 2006.176.07:36:29.61#ibcon#read 4, iclass 36, count 0 2006.176.07:36:29.61#ibcon#about to read 5, iclass 36, count 0 2006.176.07:36:29.61#ibcon#read 5, iclass 36, count 0 2006.176.07:36:29.61#ibcon#about to read 6, iclass 36, count 0 2006.176.07:36:29.61#ibcon#read 6, iclass 36, count 0 2006.176.07:36:29.61#ibcon#end of sib2, iclass 36, count 0 2006.176.07:36:29.61#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:36:29.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:36:29.61#ibcon#[25=USB\r\n] 2006.176.07:36:29.61#ibcon#*before write, iclass 36, count 0 2006.176.07:36:29.61#ibcon#enter sib2, iclass 36, count 0 2006.176.07:36:29.61#ibcon#flushed, iclass 36, count 0 2006.176.07:36:29.61#ibcon#about to write, iclass 36, count 0 2006.176.07:36:29.61#ibcon#wrote, iclass 36, count 0 2006.176.07:36:29.61#ibcon#about to read 3, iclass 36, count 0 2006.176.07:36:29.64#ibcon#read 3, iclass 36, count 0 2006.176.07:36:29.64#ibcon#about to read 4, iclass 36, count 0 2006.176.07:36:29.64#ibcon#read 4, iclass 36, count 0 2006.176.07:36:29.64#ibcon#about to read 5, iclass 36, count 0 2006.176.07:36:29.64#ibcon#read 5, iclass 36, count 0 2006.176.07:36:29.64#ibcon#about to read 6, iclass 36, count 0 2006.176.07:36:29.64#ibcon#read 6, iclass 36, count 0 2006.176.07:36:29.64#ibcon#end of sib2, iclass 36, count 0 2006.176.07:36:29.64#ibcon#*after write, iclass 36, count 0 2006.176.07:36:29.64#ibcon#*before return 0, iclass 36, count 0 2006.176.07:36:29.64#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:29.64#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:29.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:36:29.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:36:29.64$vc4f8/valo=6,772.99 2006.176.07:36:29.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.07:36:29.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.07:36:29.64#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:29.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:29.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:29.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:29.64#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:36:29.64#ibcon#first serial, iclass 38, count 0 2006.176.07:36:29.64#ibcon#enter sib2, iclass 38, count 0 2006.176.07:36:29.64#ibcon#flushed, iclass 38, count 0 2006.176.07:36:29.64#ibcon#about to write, iclass 38, count 0 2006.176.07:36:29.64#ibcon#wrote, iclass 38, count 0 2006.176.07:36:29.64#ibcon#about to read 3, iclass 38, count 0 2006.176.07:36:29.66#ibcon#read 3, iclass 38, count 0 2006.176.07:36:29.66#ibcon#about to read 4, iclass 38, count 0 2006.176.07:36:29.66#ibcon#read 4, iclass 38, count 0 2006.176.07:36:29.66#ibcon#about to read 5, iclass 38, count 0 2006.176.07:36:29.66#ibcon#read 5, iclass 38, count 0 2006.176.07:36:29.66#ibcon#about to read 6, iclass 38, count 0 2006.176.07:36:29.66#ibcon#read 6, iclass 38, count 0 2006.176.07:36:29.66#ibcon#end of sib2, iclass 38, count 0 2006.176.07:36:29.66#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:36:29.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:36:29.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:36:29.66#ibcon#*before write, iclass 38, count 0 2006.176.07:36:29.66#ibcon#enter sib2, iclass 38, count 0 2006.176.07:36:29.66#ibcon#flushed, iclass 38, count 0 2006.176.07:36:29.66#ibcon#about to write, iclass 38, count 0 2006.176.07:36:29.66#ibcon#wrote, iclass 38, count 0 2006.176.07:36:29.66#ibcon#about to read 3, iclass 38, count 0 2006.176.07:36:29.70#ibcon#read 3, iclass 38, count 0 2006.176.07:36:29.70#ibcon#about to read 4, iclass 38, count 0 2006.176.07:36:29.70#ibcon#read 4, iclass 38, count 0 2006.176.07:36:29.70#ibcon#about to read 5, iclass 38, count 0 2006.176.07:36:29.70#ibcon#read 5, iclass 38, count 0 2006.176.07:36:29.70#ibcon#about to read 6, iclass 38, count 0 2006.176.07:36:29.70#ibcon#read 6, iclass 38, count 0 2006.176.07:36:29.70#ibcon#end of sib2, iclass 38, count 0 2006.176.07:36:29.70#ibcon#*after write, iclass 38, count 0 2006.176.07:36:29.70#ibcon#*before return 0, iclass 38, count 0 2006.176.07:36:29.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:29.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:29.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:36:29.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:36:29.70$vc4f8/va=6,6 2006.176.07:36:29.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.07:36:29.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.07:36:29.70#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:29.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:36:29.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:36:29.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:36:29.76#ibcon#enter wrdev, iclass 40, count 2 2006.176.07:36:29.76#ibcon#first serial, iclass 40, count 2 2006.176.07:36:29.76#ibcon#enter sib2, iclass 40, count 2 2006.176.07:36:29.76#ibcon#flushed, iclass 40, count 2 2006.176.07:36:29.76#ibcon#about to write, iclass 40, count 2 2006.176.07:36:29.76#ibcon#wrote, iclass 40, count 2 2006.176.07:36:29.76#ibcon#about to read 3, iclass 40, count 2 2006.176.07:36:29.78#ibcon#read 3, iclass 40, count 2 2006.176.07:36:29.78#ibcon#about to read 4, iclass 40, count 2 2006.176.07:36:29.78#ibcon#read 4, iclass 40, count 2 2006.176.07:36:29.78#ibcon#about to read 5, iclass 40, count 2 2006.176.07:36:29.78#ibcon#read 5, iclass 40, count 2 2006.176.07:36:29.78#ibcon#about to read 6, iclass 40, count 2 2006.176.07:36:29.78#ibcon#read 6, iclass 40, count 2 2006.176.07:36:29.78#ibcon#end of sib2, iclass 40, count 2 2006.176.07:36:29.78#ibcon#*mode == 0, iclass 40, count 2 2006.176.07:36:29.78#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.07:36:29.78#ibcon#[25=AT06-06\r\n] 2006.176.07:36:29.78#ibcon#*before write, iclass 40, count 2 2006.176.07:36:29.78#ibcon#enter sib2, iclass 40, count 2 2006.176.07:36:29.78#ibcon#flushed, iclass 40, count 2 2006.176.07:36:29.78#ibcon#about to write, iclass 40, count 2 2006.176.07:36:29.78#ibcon#wrote, iclass 40, count 2 2006.176.07:36:29.78#ibcon#about to read 3, iclass 40, count 2 2006.176.07:36:29.81#ibcon#read 3, iclass 40, count 2 2006.176.07:36:29.81#ibcon#about to read 4, iclass 40, count 2 2006.176.07:36:29.81#ibcon#read 4, iclass 40, count 2 2006.176.07:36:29.81#ibcon#about to read 5, iclass 40, count 2 2006.176.07:36:29.81#ibcon#read 5, iclass 40, count 2 2006.176.07:36:29.81#ibcon#about to read 6, iclass 40, count 2 2006.176.07:36:29.81#ibcon#read 6, iclass 40, count 2 2006.176.07:36:29.81#ibcon#end of sib2, iclass 40, count 2 2006.176.07:36:29.81#ibcon#*after write, iclass 40, count 2 2006.176.07:36:29.81#ibcon#*before return 0, iclass 40, count 2 2006.176.07:36:29.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:36:29.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:36:29.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.07:36:29.81#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:29.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:36:29.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:36:29.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:36:29.93#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:36:29.93#ibcon#first serial, iclass 40, count 0 2006.176.07:36:29.93#ibcon#enter sib2, iclass 40, count 0 2006.176.07:36:29.93#ibcon#flushed, iclass 40, count 0 2006.176.07:36:29.93#ibcon#about to write, iclass 40, count 0 2006.176.07:36:29.93#ibcon#wrote, iclass 40, count 0 2006.176.07:36:29.93#ibcon#about to read 3, iclass 40, count 0 2006.176.07:36:29.95#ibcon#read 3, iclass 40, count 0 2006.176.07:36:29.95#ibcon#about to read 4, iclass 40, count 0 2006.176.07:36:29.95#ibcon#read 4, iclass 40, count 0 2006.176.07:36:29.95#ibcon#about to read 5, iclass 40, count 0 2006.176.07:36:29.95#ibcon#read 5, iclass 40, count 0 2006.176.07:36:29.95#ibcon#about to read 6, iclass 40, count 0 2006.176.07:36:29.95#ibcon#read 6, iclass 40, count 0 2006.176.07:36:29.95#ibcon#end of sib2, iclass 40, count 0 2006.176.07:36:29.95#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:36:29.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:36:29.95#ibcon#[25=USB\r\n] 2006.176.07:36:29.95#ibcon#*before write, iclass 40, count 0 2006.176.07:36:29.95#ibcon#enter sib2, iclass 40, count 0 2006.176.07:36:29.95#ibcon#flushed, iclass 40, count 0 2006.176.07:36:29.95#ibcon#about to write, iclass 40, count 0 2006.176.07:36:29.95#ibcon#wrote, iclass 40, count 0 2006.176.07:36:29.95#ibcon#about to read 3, iclass 40, count 0 2006.176.07:36:29.98#ibcon#read 3, iclass 40, count 0 2006.176.07:36:29.98#ibcon#about to read 4, iclass 40, count 0 2006.176.07:36:29.98#ibcon#read 4, iclass 40, count 0 2006.176.07:36:29.98#ibcon#about to read 5, iclass 40, count 0 2006.176.07:36:29.98#ibcon#read 5, iclass 40, count 0 2006.176.07:36:29.98#ibcon#about to read 6, iclass 40, count 0 2006.176.07:36:29.98#ibcon#read 6, iclass 40, count 0 2006.176.07:36:29.98#ibcon#end of sib2, iclass 40, count 0 2006.176.07:36:29.98#ibcon#*after write, iclass 40, count 0 2006.176.07:36:29.98#ibcon#*before return 0, iclass 40, count 0 2006.176.07:36:29.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:36:29.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:36:29.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:36:29.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:36:29.98$vc4f8/valo=7,832.99 2006.176.07:36:29.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.07:36:29.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.07:36:29.98#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:29.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:36:29.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:36:29.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:36:29.98#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:36:29.98#ibcon#first serial, iclass 4, count 0 2006.176.07:36:29.98#ibcon#enter sib2, iclass 4, count 0 2006.176.07:36:29.98#ibcon#flushed, iclass 4, count 0 2006.176.07:36:29.98#ibcon#about to write, iclass 4, count 0 2006.176.07:36:29.98#ibcon#wrote, iclass 4, count 0 2006.176.07:36:29.98#ibcon#about to read 3, iclass 4, count 0 2006.176.07:36:30.00#ibcon#read 3, iclass 4, count 0 2006.176.07:36:30.00#ibcon#about to read 4, iclass 4, count 0 2006.176.07:36:30.00#ibcon#read 4, iclass 4, count 0 2006.176.07:36:30.00#ibcon#about to read 5, iclass 4, count 0 2006.176.07:36:30.00#ibcon#read 5, iclass 4, count 0 2006.176.07:36:30.00#ibcon#about to read 6, iclass 4, count 0 2006.176.07:36:30.00#ibcon#read 6, iclass 4, count 0 2006.176.07:36:30.00#ibcon#end of sib2, iclass 4, count 0 2006.176.07:36:30.00#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:36:30.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:36:30.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:36:30.00#ibcon#*before write, iclass 4, count 0 2006.176.07:36:30.00#ibcon#enter sib2, iclass 4, count 0 2006.176.07:36:30.00#ibcon#flushed, iclass 4, count 0 2006.176.07:36:30.00#ibcon#about to write, iclass 4, count 0 2006.176.07:36:30.00#ibcon#wrote, iclass 4, count 0 2006.176.07:36:30.00#ibcon#about to read 3, iclass 4, count 0 2006.176.07:36:30.04#ibcon#read 3, iclass 4, count 0 2006.176.07:36:30.04#ibcon#about to read 4, iclass 4, count 0 2006.176.07:36:30.04#ibcon#read 4, iclass 4, count 0 2006.176.07:36:30.04#ibcon#about to read 5, iclass 4, count 0 2006.176.07:36:30.04#ibcon#read 5, iclass 4, count 0 2006.176.07:36:30.04#ibcon#about to read 6, iclass 4, count 0 2006.176.07:36:30.04#ibcon#read 6, iclass 4, count 0 2006.176.07:36:30.04#ibcon#end of sib2, iclass 4, count 0 2006.176.07:36:30.04#ibcon#*after write, iclass 4, count 0 2006.176.07:36:30.04#ibcon#*before return 0, iclass 4, count 0 2006.176.07:36:30.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:36:30.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:36:30.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:36:30.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:36:30.04$vc4f8/va=7,6 2006.176.07:36:30.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.07:36:30.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.07:36:30.04#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:30.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:36:30.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:36:30.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:36:30.10#ibcon#enter wrdev, iclass 6, count 2 2006.176.07:36:30.10#ibcon#first serial, iclass 6, count 2 2006.176.07:36:30.10#ibcon#enter sib2, iclass 6, count 2 2006.176.07:36:30.10#ibcon#flushed, iclass 6, count 2 2006.176.07:36:30.10#ibcon#about to write, iclass 6, count 2 2006.176.07:36:30.10#ibcon#wrote, iclass 6, count 2 2006.176.07:36:30.10#ibcon#about to read 3, iclass 6, count 2 2006.176.07:36:30.12#ibcon#read 3, iclass 6, count 2 2006.176.07:36:30.12#ibcon#about to read 4, iclass 6, count 2 2006.176.07:36:30.12#ibcon#read 4, iclass 6, count 2 2006.176.07:36:30.12#ibcon#about to read 5, iclass 6, count 2 2006.176.07:36:30.12#ibcon#read 5, iclass 6, count 2 2006.176.07:36:30.12#ibcon#about to read 6, iclass 6, count 2 2006.176.07:36:30.12#ibcon#read 6, iclass 6, count 2 2006.176.07:36:30.12#ibcon#end of sib2, iclass 6, count 2 2006.176.07:36:30.12#ibcon#*mode == 0, iclass 6, count 2 2006.176.07:36:30.12#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.07:36:30.12#ibcon#[25=AT07-06\r\n] 2006.176.07:36:30.12#ibcon#*before write, iclass 6, count 2 2006.176.07:36:30.12#ibcon#enter sib2, iclass 6, count 2 2006.176.07:36:30.12#ibcon#flushed, iclass 6, count 2 2006.176.07:36:30.12#ibcon#about to write, iclass 6, count 2 2006.176.07:36:30.12#ibcon#wrote, iclass 6, count 2 2006.176.07:36:30.12#ibcon#about to read 3, iclass 6, count 2 2006.176.07:36:30.15#ibcon#read 3, iclass 6, count 2 2006.176.07:36:30.15#ibcon#about to read 4, iclass 6, count 2 2006.176.07:36:30.15#ibcon#read 4, iclass 6, count 2 2006.176.07:36:30.15#ibcon#about to read 5, iclass 6, count 2 2006.176.07:36:30.15#ibcon#read 5, iclass 6, count 2 2006.176.07:36:30.15#ibcon#about to read 6, iclass 6, count 2 2006.176.07:36:30.15#ibcon#read 6, iclass 6, count 2 2006.176.07:36:30.15#ibcon#end of sib2, iclass 6, count 2 2006.176.07:36:30.15#ibcon#*after write, iclass 6, count 2 2006.176.07:36:30.15#ibcon#*before return 0, iclass 6, count 2 2006.176.07:36:30.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:36:30.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:36:30.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.07:36:30.15#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:30.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:36:30.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:36:30.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:36:30.27#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:36:30.27#ibcon#first serial, iclass 6, count 0 2006.176.07:36:30.27#ibcon#enter sib2, iclass 6, count 0 2006.176.07:36:30.27#ibcon#flushed, iclass 6, count 0 2006.176.07:36:30.27#ibcon#about to write, iclass 6, count 0 2006.176.07:36:30.27#ibcon#wrote, iclass 6, count 0 2006.176.07:36:30.27#ibcon#about to read 3, iclass 6, count 0 2006.176.07:36:30.29#ibcon#read 3, iclass 6, count 0 2006.176.07:36:30.29#ibcon#about to read 4, iclass 6, count 0 2006.176.07:36:30.29#ibcon#read 4, iclass 6, count 0 2006.176.07:36:30.29#ibcon#about to read 5, iclass 6, count 0 2006.176.07:36:30.29#ibcon#read 5, iclass 6, count 0 2006.176.07:36:30.29#ibcon#about to read 6, iclass 6, count 0 2006.176.07:36:30.29#ibcon#read 6, iclass 6, count 0 2006.176.07:36:30.29#ibcon#end of sib2, iclass 6, count 0 2006.176.07:36:30.29#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:36:30.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:36:30.29#ibcon#[25=USB\r\n] 2006.176.07:36:30.29#ibcon#*before write, iclass 6, count 0 2006.176.07:36:30.29#ibcon#enter sib2, iclass 6, count 0 2006.176.07:36:30.29#ibcon#flushed, iclass 6, count 0 2006.176.07:36:30.29#ibcon#about to write, iclass 6, count 0 2006.176.07:36:30.29#ibcon#wrote, iclass 6, count 0 2006.176.07:36:30.29#ibcon#about to read 3, iclass 6, count 0 2006.176.07:36:30.33#ibcon#read 3, iclass 6, count 0 2006.176.07:36:30.33#ibcon#about to read 4, iclass 6, count 0 2006.176.07:36:30.33#ibcon#read 4, iclass 6, count 0 2006.176.07:36:30.33#ibcon#about to read 5, iclass 6, count 0 2006.176.07:36:30.33#ibcon#read 5, iclass 6, count 0 2006.176.07:36:30.33#ibcon#about to read 6, iclass 6, count 0 2006.176.07:36:30.33#ibcon#read 6, iclass 6, count 0 2006.176.07:36:30.33#ibcon#end of sib2, iclass 6, count 0 2006.176.07:36:30.33#ibcon#*after write, iclass 6, count 0 2006.176.07:36:30.33#ibcon#*before return 0, iclass 6, count 0 2006.176.07:36:30.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:36:30.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:36:30.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:36:30.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:36:30.33$vc4f8/valo=8,852.99 2006.176.07:36:30.33#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.07:36:30.33#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.07:36:30.33#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:30.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:36:30.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:36:30.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:36:30.33#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:36:30.33#ibcon#first serial, iclass 10, count 0 2006.176.07:36:30.33#ibcon#enter sib2, iclass 10, count 0 2006.176.07:36:30.33#ibcon#flushed, iclass 10, count 0 2006.176.07:36:30.33#ibcon#about to write, iclass 10, count 0 2006.176.07:36:30.33#ibcon#wrote, iclass 10, count 0 2006.176.07:36:30.33#ibcon#about to read 3, iclass 10, count 0 2006.176.07:36:30.34#ibcon#read 3, iclass 10, count 0 2006.176.07:36:30.34#ibcon#about to read 4, iclass 10, count 0 2006.176.07:36:30.34#ibcon#read 4, iclass 10, count 0 2006.176.07:36:30.34#ibcon#about to read 5, iclass 10, count 0 2006.176.07:36:30.34#ibcon#read 5, iclass 10, count 0 2006.176.07:36:30.34#ibcon#about to read 6, iclass 10, count 0 2006.176.07:36:30.34#ibcon#read 6, iclass 10, count 0 2006.176.07:36:30.34#ibcon#end of sib2, iclass 10, count 0 2006.176.07:36:30.34#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:36:30.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:36:30.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:36:30.34#ibcon#*before write, iclass 10, count 0 2006.176.07:36:30.34#ibcon#enter sib2, iclass 10, count 0 2006.176.07:36:30.34#ibcon#flushed, iclass 10, count 0 2006.176.07:36:30.34#ibcon#about to write, iclass 10, count 0 2006.176.07:36:30.34#ibcon#wrote, iclass 10, count 0 2006.176.07:36:30.34#ibcon#about to read 3, iclass 10, count 0 2006.176.07:36:30.38#ibcon#read 3, iclass 10, count 0 2006.176.07:36:30.38#ibcon#about to read 4, iclass 10, count 0 2006.176.07:36:30.38#ibcon#read 4, iclass 10, count 0 2006.176.07:36:30.38#ibcon#about to read 5, iclass 10, count 0 2006.176.07:36:30.38#ibcon#read 5, iclass 10, count 0 2006.176.07:36:30.38#ibcon#about to read 6, iclass 10, count 0 2006.176.07:36:30.38#ibcon#read 6, iclass 10, count 0 2006.176.07:36:30.38#ibcon#end of sib2, iclass 10, count 0 2006.176.07:36:30.38#ibcon#*after write, iclass 10, count 0 2006.176.07:36:30.38#ibcon#*before return 0, iclass 10, count 0 2006.176.07:36:30.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:36:30.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:36:30.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:36:30.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:36:30.38$vc4f8/va=8,6 2006.176.07:36:30.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.07:36:30.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.07:36:30.38#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:30.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:36:30.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:36:30.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:36:30.45#ibcon#enter wrdev, iclass 12, count 2 2006.176.07:36:30.45#ibcon#first serial, iclass 12, count 2 2006.176.07:36:30.45#ibcon#enter sib2, iclass 12, count 2 2006.176.07:36:30.45#ibcon#flushed, iclass 12, count 2 2006.176.07:36:30.45#ibcon#about to write, iclass 12, count 2 2006.176.07:36:30.45#ibcon#wrote, iclass 12, count 2 2006.176.07:36:30.45#ibcon#about to read 3, iclass 12, count 2 2006.176.07:36:30.47#ibcon#read 3, iclass 12, count 2 2006.176.07:36:30.47#ibcon#about to read 4, iclass 12, count 2 2006.176.07:36:30.47#ibcon#read 4, iclass 12, count 2 2006.176.07:36:30.47#ibcon#about to read 5, iclass 12, count 2 2006.176.07:36:30.47#ibcon#read 5, iclass 12, count 2 2006.176.07:36:30.47#ibcon#about to read 6, iclass 12, count 2 2006.176.07:36:30.47#ibcon#read 6, iclass 12, count 2 2006.176.07:36:30.47#ibcon#end of sib2, iclass 12, count 2 2006.176.07:36:30.47#ibcon#*mode == 0, iclass 12, count 2 2006.176.07:36:30.47#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.07:36:30.47#ibcon#[25=AT08-06\r\n] 2006.176.07:36:30.47#ibcon#*before write, iclass 12, count 2 2006.176.07:36:30.47#ibcon#enter sib2, iclass 12, count 2 2006.176.07:36:30.47#ibcon#flushed, iclass 12, count 2 2006.176.07:36:30.47#ibcon#about to write, iclass 12, count 2 2006.176.07:36:30.47#ibcon#wrote, iclass 12, count 2 2006.176.07:36:30.47#ibcon#about to read 3, iclass 12, count 2 2006.176.07:36:30.50#ibcon#read 3, iclass 12, count 2 2006.176.07:36:30.50#ibcon#about to read 4, iclass 12, count 2 2006.176.07:36:30.50#ibcon#read 4, iclass 12, count 2 2006.176.07:36:30.50#ibcon#about to read 5, iclass 12, count 2 2006.176.07:36:30.50#ibcon#read 5, iclass 12, count 2 2006.176.07:36:30.50#ibcon#about to read 6, iclass 12, count 2 2006.176.07:36:30.50#ibcon#read 6, iclass 12, count 2 2006.176.07:36:30.50#ibcon#end of sib2, iclass 12, count 2 2006.176.07:36:30.50#ibcon#*after write, iclass 12, count 2 2006.176.07:36:30.50#ibcon#*before return 0, iclass 12, count 2 2006.176.07:36:30.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:36:30.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:36:30.50#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.07:36:30.50#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:30.50#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:36:30.62#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:36:30.62#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:36:30.62#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:36:30.62#ibcon#first serial, iclass 12, count 0 2006.176.07:36:30.62#ibcon#enter sib2, iclass 12, count 0 2006.176.07:36:30.62#ibcon#flushed, iclass 12, count 0 2006.176.07:36:30.62#ibcon#about to write, iclass 12, count 0 2006.176.07:36:30.62#ibcon#wrote, iclass 12, count 0 2006.176.07:36:30.62#ibcon#about to read 3, iclass 12, count 0 2006.176.07:36:30.64#ibcon#read 3, iclass 12, count 0 2006.176.07:36:30.64#ibcon#about to read 4, iclass 12, count 0 2006.176.07:36:30.64#ibcon#read 4, iclass 12, count 0 2006.176.07:36:30.64#ibcon#about to read 5, iclass 12, count 0 2006.176.07:36:30.64#ibcon#read 5, iclass 12, count 0 2006.176.07:36:30.64#ibcon#about to read 6, iclass 12, count 0 2006.176.07:36:30.64#ibcon#read 6, iclass 12, count 0 2006.176.07:36:30.64#ibcon#end of sib2, iclass 12, count 0 2006.176.07:36:30.64#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:36:30.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:36:30.64#ibcon#[25=USB\r\n] 2006.176.07:36:30.64#ibcon#*before write, iclass 12, count 0 2006.176.07:36:30.64#ibcon#enter sib2, iclass 12, count 0 2006.176.07:36:30.64#ibcon#flushed, iclass 12, count 0 2006.176.07:36:30.64#ibcon#about to write, iclass 12, count 0 2006.176.07:36:30.64#ibcon#wrote, iclass 12, count 0 2006.176.07:36:30.64#ibcon#about to read 3, iclass 12, count 0 2006.176.07:36:30.67#ibcon#read 3, iclass 12, count 0 2006.176.07:36:30.67#ibcon#about to read 4, iclass 12, count 0 2006.176.07:36:30.67#ibcon#read 4, iclass 12, count 0 2006.176.07:36:30.67#ibcon#about to read 5, iclass 12, count 0 2006.176.07:36:30.67#ibcon#read 5, iclass 12, count 0 2006.176.07:36:30.67#ibcon#about to read 6, iclass 12, count 0 2006.176.07:36:30.67#ibcon#read 6, iclass 12, count 0 2006.176.07:36:30.67#ibcon#end of sib2, iclass 12, count 0 2006.176.07:36:30.67#ibcon#*after write, iclass 12, count 0 2006.176.07:36:30.67#ibcon#*before return 0, iclass 12, count 0 2006.176.07:36:30.67#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:36:30.67#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:36:30.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:36:30.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:36:30.67$vc4f8/vblo=1,632.99 2006.176.07:36:30.67#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.07:36:30.67#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.07:36:30.67#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:30.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:36:30.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:36:30.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:36:30.67#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:36:30.67#ibcon#first serial, iclass 14, count 0 2006.176.07:36:30.67#ibcon#enter sib2, iclass 14, count 0 2006.176.07:36:30.67#ibcon#flushed, iclass 14, count 0 2006.176.07:36:30.67#ibcon#about to write, iclass 14, count 0 2006.176.07:36:30.67#ibcon#wrote, iclass 14, count 0 2006.176.07:36:30.67#ibcon#about to read 3, iclass 14, count 0 2006.176.07:36:30.69#ibcon#read 3, iclass 14, count 0 2006.176.07:36:30.69#ibcon#about to read 4, iclass 14, count 0 2006.176.07:36:30.69#ibcon#read 4, iclass 14, count 0 2006.176.07:36:30.69#ibcon#about to read 5, iclass 14, count 0 2006.176.07:36:30.69#ibcon#read 5, iclass 14, count 0 2006.176.07:36:30.69#ibcon#about to read 6, iclass 14, count 0 2006.176.07:36:30.69#ibcon#read 6, iclass 14, count 0 2006.176.07:36:30.69#ibcon#end of sib2, iclass 14, count 0 2006.176.07:36:30.69#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:36:30.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:36:30.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:36:30.69#ibcon#*before write, iclass 14, count 0 2006.176.07:36:30.69#ibcon#enter sib2, iclass 14, count 0 2006.176.07:36:30.69#ibcon#flushed, iclass 14, count 0 2006.176.07:36:30.69#ibcon#about to write, iclass 14, count 0 2006.176.07:36:30.69#ibcon#wrote, iclass 14, count 0 2006.176.07:36:30.69#ibcon#about to read 3, iclass 14, count 0 2006.176.07:36:30.73#ibcon#read 3, iclass 14, count 0 2006.176.07:36:30.73#ibcon#about to read 4, iclass 14, count 0 2006.176.07:36:30.73#ibcon#read 4, iclass 14, count 0 2006.176.07:36:30.73#ibcon#about to read 5, iclass 14, count 0 2006.176.07:36:30.73#ibcon#read 5, iclass 14, count 0 2006.176.07:36:30.73#ibcon#about to read 6, iclass 14, count 0 2006.176.07:36:30.73#ibcon#read 6, iclass 14, count 0 2006.176.07:36:30.73#ibcon#end of sib2, iclass 14, count 0 2006.176.07:36:30.73#ibcon#*after write, iclass 14, count 0 2006.176.07:36:30.73#ibcon#*before return 0, iclass 14, count 0 2006.176.07:36:30.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:36:30.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:36:30.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:36:30.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:36:30.73$vc4f8/vb=1,4 2006.176.07:36:30.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.07:36:30.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.07:36:30.73#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:30.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:36:30.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:36:30.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:36:30.73#ibcon#enter wrdev, iclass 16, count 2 2006.176.07:36:30.73#ibcon#first serial, iclass 16, count 2 2006.176.07:36:30.73#ibcon#enter sib2, iclass 16, count 2 2006.176.07:36:30.73#ibcon#flushed, iclass 16, count 2 2006.176.07:36:30.73#ibcon#about to write, iclass 16, count 2 2006.176.07:36:30.73#ibcon#wrote, iclass 16, count 2 2006.176.07:36:30.73#ibcon#about to read 3, iclass 16, count 2 2006.176.07:36:30.75#ibcon#read 3, iclass 16, count 2 2006.176.07:36:30.75#ibcon#about to read 4, iclass 16, count 2 2006.176.07:36:30.75#ibcon#read 4, iclass 16, count 2 2006.176.07:36:30.75#ibcon#about to read 5, iclass 16, count 2 2006.176.07:36:30.75#ibcon#read 5, iclass 16, count 2 2006.176.07:36:30.75#ibcon#about to read 6, iclass 16, count 2 2006.176.07:36:30.75#ibcon#read 6, iclass 16, count 2 2006.176.07:36:30.75#ibcon#end of sib2, iclass 16, count 2 2006.176.07:36:30.75#ibcon#*mode == 0, iclass 16, count 2 2006.176.07:36:30.75#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.07:36:30.75#ibcon#[27=AT01-04\r\n] 2006.176.07:36:30.75#ibcon#*before write, iclass 16, count 2 2006.176.07:36:30.75#ibcon#enter sib2, iclass 16, count 2 2006.176.07:36:30.75#ibcon#flushed, iclass 16, count 2 2006.176.07:36:30.75#ibcon#about to write, iclass 16, count 2 2006.176.07:36:30.75#ibcon#wrote, iclass 16, count 2 2006.176.07:36:30.75#ibcon#about to read 3, iclass 16, count 2 2006.176.07:36:30.78#ibcon#read 3, iclass 16, count 2 2006.176.07:36:30.78#ibcon#about to read 4, iclass 16, count 2 2006.176.07:36:30.78#ibcon#read 4, iclass 16, count 2 2006.176.07:36:30.78#ibcon#about to read 5, iclass 16, count 2 2006.176.07:36:30.78#ibcon#read 5, iclass 16, count 2 2006.176.07:36:30.78#ibcon#about to read 6, iclass 16, count 2 2006.176.07:36:30.78#ibcon#read 6, iclass 16, count 2 2006.176.07:36:30.78#ibcon#end of sib2, iclass 16, count 2 2006.176.07:36:30.78#ibcon#*after write, iclass 16, count 2 2006.176.07:36:30.78#ibcon#*before return 0, iclass 16, count 2 2006.176.07:36:30.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:36:30.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:36:30.78#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.07:36:30.78#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:30.78#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:36:30.90#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:36:30.90#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:36:30.90#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:36:30.90#ibcon#first serial, iclass 16, count 0 2006.176.07:36:30.90#ibcon#enter sib2, iclass 16, count 0 2006.176.07:36:30.90#ibcon#flushed, iclass 16, count 0 2006.176.07:36:30.90#ibcon#about to write, iclass 16, count 0 2006.176.07:36:30.90#ibcon#wrote, iclass 16, count 0 2006.176.07:36:30.90#ibcon#about to read 3, iclass 16, count 0 2006.176.07:36:30.92#ibcon#read 3, iclass 16, count 0 2006.176.07:36:30.92#ibcon#about to read 4, iclass 16, count 0 2006.176.07:36:30.92#ibcon#read 4, iclass 16, count 0 2006.176.07:36:30.92#ibcon#about to read 5, iclass 16, count 0 2006.176.07:36:30.92#ibcon#read 5, iclass 16, count 0 2006.176.07:36:30.92#ibcon#about to read 6, iclass 16, count 0 2006.176.07:36:30.92#ibcon#read 6, iclass 16, count 0 2006.176.07:36:30.92#ibcon#end of sib2, iclass 16, count 0 2006.176.07:36:30.92#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:36:30.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:36:30.92#ibcon#[27=USB\r\n] 2006.176.07:36:30.92#ibcon#*before write, iclass 16, count 0 2006.176.07:36:30.92#ibcon#enter sib2, iclass 16, count 0 2006.176.07:36:30.92#ibcon#flushed, iclass 16, count 0 2006.176.07:36:30.92#ibcon#about to write, iclass 16, count 0 2006.176.07:36:30.92#ibcon#wrote, iclass 16, count 0 2006.176.07:36:30.92#ibcon#about to read 3, iclass 16, count 0 2006.176.07:36:30.95#ibcon#read 3, iclass 16, count 0 2006.176.07:36:30.95#ibcon#about to read 4, iclass 16, count 0 2006.176.07:36:30.95#ibcon#read 4, iclass 16, count 0 2006.176.07:36:30.95#ibcon#about to read 5, iclass 16, count 0 2006.176.07:36:30.95#ibcon#read 5, iclass 16, count 0 2006.176.07:36:30.95#ibcon#about to read 6, iclass 16, count 0 2006.176.07:36:30.95#ibcon#read 6, iclass 16, count 0 2006.176.07:36:30.95#ibcon#end of sib2, iclass 16, count 0 2006.176.07:36:30.95#ibcon#*after write, iclass 16, count 0 2006.176.07:36:30.95#ibcon#*before return 0, iclass 16, count 0 2006.176.07:36:30.95#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:36:30.95#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:36:30.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:36:30.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:36:30.95$vc4f8/vblo=2,640.99 2006.176.07:36:30.95#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.07:36:30.95#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.07:36:30.95#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:30.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:30.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:30.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:30.95#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:36:30.95#ibcon#first serial, iclass 18, count 0 2006.176.07:36:30.95#ibcon#enter sib2, iclass 18, count 0 2006.176.07:36:30.95#ibcon#flushed, iclass 18, count 0 2006.176.07:36:30.95#ibcon#about to write, iclass 18, count 0 2006.176.07:36:30.95#ibcon#wrote, iclass 18, count 0 2006.176.07:36:30.95#ibcon#about to read 3, iclass 18, count 0 2006.176.07:36:30.97#ibcon#read 3, iclass 18, count 0 2006.176.07:36:30.97#ibcon#about to read 4, iclass 18, count 0 2006.176.07:36:30.97#ibcon#read 4, iclass 18, count 0 2006.176.07:36:30.97#ibcon#about to read 5, iclass 18, count 0 2006.176.07:36:30.97#ibcon#read 5, iclass 18, count 0 2006.176.07:36:30.97#ibcon#about to read 6, iclass 18, count 0 2006.176.07:36:30.97#ibcon#read 6, iclass 18, count 0 2006.176.07:36:30.97#ibcon#end of sib2, iclass 18, count 0 2006.176.07:36:30.97#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:36:30.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:36:30.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:36:30.97#ibcon#*before write, iclass 18, count 0 2006.176.07:36:30.97#ibcon#enter sib2, iclass 18, count 0 2006.176.07:36:30.97#ibcon#flushed, iclass 18, count 0 2006.176.07:36:30.97#ibcon#about to write, iclass 18, count 0 2006.176.07:36:30.97#ibcon#wrote, iclass 18, count 0 2006.176.07:36:30.97#ibcon#about to read 3, iclass 18, count 0 2006.176.07:36:31.01#ibcon#read 3, iclass 18, count 0 2006.176.07:36:31.01#ibcon#about to read 4, iclass 18, count 0 2006.176.07:36:31.01#ibcon#read 4, iclass 18, count 0 2006.176.07:36:31.01#ibcon#about to read 5, iclass 18, count 0 2006.176.07:36:31.01#ibcon#read 5, iclass 18, count 0 2006.176.07:36:31.01#ibcon#about to read 6, iclass 18, count 0 2006.176.07:36:31.01#ibcon#read 6, iclass 18, count 0 2006.176.07:36:31.01#ibcon#end of sib2, iclass 18, count 0 2006.176.07:36:31.01#ibcon#*after write, iclass 18, count 0 2006.176.07:36:31.01#ibcon#*before return 0, iclass 18, count 0 2006.176.07:36:31.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:31.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:36:31.01#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:36:31.01#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:36:31.01$vc4f8/vb=2,4 2006.176.07:36:31.01#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.07:36:31.01#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.07:36:31.01#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:31.01#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:31.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:31.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:31.07#ibcon#enter wrdev, iclass 20, count 2 2006.176.07:36:31.07#ibcon#first serial, iclass 20, count 2 2006.176.07:36:31.07#ibcon#enter sib2, iclass 20, count 2 2006.176.07:36:31.07#ibcon#flushed, iclass 20, count 2 2006.176.07:36:31.07#ibcon#about to write, iclass 20, count 2 2006.176.07:36:31.07#ibcon#wrote, iclass 20, count 2 2006.176.07:36:31.07#ibcon#about to read 3, iclass 20, count 2 2006.176.07:36:31.09#ibcon#read 3, iclass 20, count 2 2006.176.07:36:31.09#ibcon#about to read 4, iclass 20, count 2 2006.176.07:36:31.09#ibcon#read 4, iclass 20, count 2 2006.176.07:36:31.09#ibcon#about to read 5, iclass 20, count 2 2006.176.07:36:31.09#ibcon#read 5, iclass 20, count 2 2006.176.07:36:31.09#ibcon#about to read 6, iclass 20, count 2 2006.176.07:36:31.09#ibcon#read 6, iclass 20, count 2 2006.176.07:36:31.09#ibcon#end of sib2, iclass 20, count 2 2006.176.07:36:31.09#ibcon#*mode == 0, iclass 20, count 2 2006.176.07:36:31.09#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.07:36:31.09#ibcon#[27=AT02-04\r\n] 2006.176.07:36:31.09#ibcon#*before write, iclass 20, count 2 2006.176.07:36:31.09#ibcon#enter sib2, iclass 20, count 2 2006.176.07:36:31.09#ibcon#flushed, iclass 20, count 2 2006.176.07:36:31.09#ibcon#about to write, iclass 20, count 2 2006.176.07:36:31.09#ibcon#wrote, iclass 20, count 2 2006.176.07:36:31.09#ibcon#about to read 3, iclass 20, count 2 2006.176.07:36:31.12#ibcon#read 3, iclass 20, count 2 2006.176.07:36:31.12#ibcon#about to read 4, iclass 20, count 2 2006.176.07:36:31.12#ibcon#read 4, iclass 20, count 2 2006.176.07:36:31.12#ibcon#about to read 5, iclass 20, count 2 2006.176.07:36:31.12#ibcon#read 5, iclass 20, count 2 2006.176.07:36:31.12#ibcon#about to read 6, iclass 20, count 2 2006.176.07:36:31.12#ibcon#read 6, iclass 20, count 2 2006.176.07:36:31.12#ibcon#end of sib2, iclass 20, count 2 2006.176.07:36:31.12#ibcon#*after write, iclass 20, count 2 2006.176.07:36:31.12#ibcon#*before return 0, iclass 20, count 2 2006.176.07:36:31.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:31.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:36:31.12#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.07:36:31.12#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:31.12#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:31.24#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:31.24#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:31.24#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:36:31.24#ibcon#first serial, iclass 20, count 0 2006.176.07:36:31.24#ibcon#enter sib2, iclass 20, count 0 2006.176.07:36:31.24#ibcon#flushed, iclass 20, count 0 2006.176.07:36:31.24#ibcon#about to write, iclass 20, count 0 2006.176.07:36:31.24#ibcon#wrote, iclass 20, count 0 2006.176.07:36:31.24#ibcon#about to read 3, iclass 20, count 0 2006.176.07:36:31.26#ibcon#read 3, iclass 20, count 0 2006.176.07:36:31.26#ibcon#about to read 4, iclass 20, count 0 2006.176.07:36:31.26#ibcon#read 4, iclass 20, count 0 2006.176.07:36:31.26#ibcon#about to read 5, iclass 20, count 0 2006.176.07:36:31.26#ibcon#read 5, iclass 20, count 0 2006.176.07:36:31.26#ibcon#about to read 6, iclass 20, count 0 2006.176.07:36:31.26#ibcon#read 6, iclass 20, count 0 2006.176.07:36:31.26#ibcon#end of sib2, iclass 20, count 0 2006.176.07:36:31.26#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:36:31.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:36:31.26#ibcon#[27=USB\r\n] 2006.176.07:36:31.26#ibcon#*before write, iclass 20, count 0 2006.176.07:36:31.26#ibcon#enter sib2, iclass 20, count 0 2006.176.07:36:31.26#ibcon#flushed, iclass 20, count 0 2006.176.07:36:31.26#ibcon#about to write, iclass 20, count 0 2006.176.07:36:31.26#ibcon#wrote, iclass 20, count 0 2006.176.07:36:31.26#ibcon#about to read 3, iclass 20, count 0 2006.176.07:36:31.29#ibcon#read 3, iclass 20, count 0 2006.176.07:36:31.29#ibcon#about to read 4, iclass 20, count 0 2006.176.07:36:31.29#ibcon#read 4, iclass 20, count 0 2006.176.07:36:31.29#ibcon#about to read 5, iclass 20, count 0 2006.176.07:36:31.29#ibcon#read 5, iclass 20, count 0 2006.176.07:36:31.29#ibcon#about to read 6, iclass 20, count 0 2006.176.07:36:31.29#ibcon#read 6, iclass 20, count 0 2006.176.07:36:31.29#ibcon#end of sib2, iclass 20, count 0 2006.176.07:36:31.29#ibcon#*after write, iclass 20, count 0 2006.176.07:36:31.29#ibcon#*before return 0, iclass 20, count 0 2006.176.07:36:31.29#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:31.29#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:36:31.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:36:31.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:36:31.29$vc4f8/vblo=3,656.99 2006.176.07:36:31.29#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.07:36:31.29#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.07:36:31.29#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:31.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:31.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:31.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:31.29#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:36:31.29#ibcon#first serial, iclass 22, count 0 2006.176.07:36:31.29#ibcon#enter sib2, iclass 22, count 0 2006.176.07:36:31.29#ibcon#flushed, iclass 22, count 0 2006.176.07:36:31.29#ibcon#about to write, iclass 22, count 0 2006.176.07:36:31.29#ibcon#wrote, iclass 22, count 0 2006.176.07:36:31.29#ibcon#about to read 3, iclass 22, count 0 2006.176.07:36:31.31#ibcon#read 3, iclass 22, count 0 2006.176.07:36:31.31#ibcon#about to read 4, iclass 22, count 0 2006.176.07:36:31.31#ibcon#read 4, iclass 22, count 0 2006.176.07:36:31.31#ibcon#about to read 5, iclass 22, count 0 2006.176.07:36:31.31#ibcon#read 5, iclass 22, count 0 2006.176.07:36:31.31#ibcon#about to read 6, iclass 22, count 0 2006.176.07:36:31.31#ibcon#read 6, iclass 22, count 0 2006.176.07:36:31.31#ibcon#end of sib2, iclass 22, count 0 2006.176.07:36:31.31#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:36:31.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:36:31.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:36:31.31#ibcon#*before write, iclass 22, count 0 2006.176.07:36:31.31#ibcon#enter sib2, iclass 22, count 0 2006.176.07:36:31.31#ibcon#flushed, iclass 22, count 0 2006.176.07:36:31.31#ibcon#about to write, iclass 22, count 0 2006.176.07:36:31.31#ibcon#wrote, iclass 22, count 0 2006.176.07:36:31.31#ibcon#about to read 3, iclass 22, count 0 2006.176.07:36:31.35#ibcon#read 3, iclass 22, count 0 2006.176.07:36:31.35#ibcon#about to read 4, iclass 22, count 0 2006.176.07:36:31.35#ibcon#read 4, iclass 22, count 0 2006.176.07:36:31.35#ibcon#about to read 5, iclass 22, count 0 2006.176.07:36:31.35#ibcon#read 5, iclass 22, count 0 2006.176.07:36:31.35#ibcon#about to read 6, iclass 22, count 0 2006.176.07:36:31.35#ibcon#read 6, iclass 22, count 0 2006.176.07:36:31.35#ibcon#end of sib2, iclass 22, count 0 2006.176.07:36:31.35#ibcon#*after write, iclass 22, count 0 2006.176.07:36:31.35#ibcon#*before return 0, iclass 22, count 0 2006.176.07:36:31.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:31.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:36:31.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:36:31.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:36:31.35$vc4f8/vb=3,4 2006.176.07:36:31.35#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.07:36:31.35#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.07:36:31.35#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:31.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:31.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:31.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:31.41#ibcon#enter wrdev, iclass 24, count 2 2006.176.07:36:31.41#ibcon#first serial, iclass 24, count 2 2006.176.07:36:31.41#ibcon#enter sib2, iclass 24, count 2 2006.176.07:36:31.41#ibcon#flushed, iclass 24, count 2 2006.176.07:36:31.41#ibcon#about to write, iclass 24, count 2 2006.176.07:36:31.41#ibcon#wrote, iclass 24, count 2 2006.176.07:36:31.41#ibcon#about to read 3, iclass 24, count 2 2006.176.07:36:31.43#ibcon#read 3, iclass 24, count 2 2006.176.07:36:31.43#ibcon#about to read 4, iclass 24, count 2 2006.176.07:36:31.43#ibcon#read 4, iclass 24, count 2 2006.176.07:36:31.43#ibcon#about to read 5, iclass 24, count 2 2006.176.07:36:31.43#ibcon#read 5, iclass 24, count 2 2006.176.07:36:31.43#ibcon#about to read 6, iclass 24, count 2 2006.176.07:36:31.43#ibcon#read 6, iclass 24, count 2 2006.176.07:36:31.43#ibcon#end of sib2, iclass 24, count 2 2006.176.07:36:31.43#ibcon#*mode == 0, iclass 24, count 2 2006.176.07:36:31.43#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.07:36:31.43#ibcon#[27=AT03-04\r\n] 2006.176.07:36:31.43#ibcon#*before write, iclass 24, count 2 2006.176.07:36:31.43#ibcon#enter sib2, iclass 24, count 2 2006.176.07:36:31.43#ibcon#flushed, iclass 24, count 2 2006.176.07:36:31.43#ibcon#about to write, iclass 24, count 2 2006.176.07:36:31.43#ibcon#wrote, iclass 24, count 2 2006.176.07:36:31.43#ibcon#about to read 3, iclass 24, count 2 2006.176.07:36:31.46#ibcon#read 3, iclass 24, count 2 2006.176.07:36:31.46#ibcon#about to read 4, iclass 24, count 2 2006.176.07:36:31.46#ibcon#read 4, iclass 24, count 2 2006.176.07:36:31.46#ibcon#about to read 5, iclass 24, count 2 2006.176.07:36:31.46#ibcon#read 5, iclass 24, count 2 2006.176.07:36:31.46#ibcon#about to read 6, iclass 24, count 2 2006.176.07:36:31.46#ibcon#read 6, iclass 24, count 2 2006.176.07:36:31.46#ibcon#end of sib2, iclass 24, count 2 2006.176.07:36:31.46#ibcon#*after write, iclass 24, count 2 2006.176.07:36:31.46#ibcon#*before return 0, iclass 24, count 2 2006.176.07:36:31.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:31.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:36:31.46#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.07:36:31.46#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:31.46#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:31.58#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:31.58#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:31.58#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:36:31.58#ibcon#first serial, iclass 24, count 0 2006.176.07:36:31.58#ibcon#enter sib2, iclass 24, count 0 2006.176.07:36:31.58#ibcon#flushed, iclass 24, count 0 2006.176.07:36:31.58#ibcon#about to write, iclass 24, count 0 2006.176.07:36:31.58#ibcon#wrote, iclass 24, count 0 2006.176.07:36:31.58#ibcon#about to read 3, iclass 24, count 0 2006.176.07:36:31.60#ibcon#read 3, iclass 24, count 0 2006.176.07:36:31.60#ibcon#about to read 4, iclass 24, count 0 2006.176.07:36:31.60#ibcon#read 4, iclass 24, count 0 2006.176.07:36:31.60#ibcon#about to read 5, iclass 24, count 0 2006.176.07:36:31.60#ibcon#read 5, iclass 24, count 0 2006.176.07:36:31.60#ibcon#about to read 6, iclass 24, count 0 2006.176.07:36:31.60#ibcon#read 6, iclass 24, count 0 2006.176.07:36:31.60#ibcon#end of sib2, iclass 24, count 0 2006.176.07:36:31.60#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:36:31.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:36:31.60#ibcon#[27=USB\r\n] 2006.176.07:36:31.60#ibcon#*before write, iclass 24, count 0 2006.176.07:36:31.60#ibcon#enter sib2, iclass 24, count 0 2006.176.07:36:31.60#ibcon#flushed, iclass 24, count 0 2006.176.07:36:31.60#ibcon#about to write, iclass 24, count 0 2006.176.07:36:31.60#ibcon#wrote, iclass 24, count 0 2006.176.07:36:31.60#ibcon#about to read 3, iclass 24, count 0 2006.176.07:36:31.63#ibcon#read 3, iclass 24, count 0 2006.176.07:36:31.63#ibcon#about to read 4, iclass 24, count 0 2006.176.07:36:31.63#ibcon#read 4, iclass 24, count 0 2006.176.07:36:31.63#ibcon#about to read 5, iclass 24, count 0 2006.176.07:36:31.63#ibcon#read 5, iclass 24, count 0 2006.176.07:36:31.63#ibcon#about to read 6, iclass 24, count 0 2006.176.07:36:31.63#ibcon#read 6, iclass 24, count 0 2006.176.07:36:31.63#ibcon#end of sib2, iclass 24, count 0 2006.176.07:36:31.63#ibcon#*after write, iclass 24, count 0 2006.176.07:36:31.63#ibcon#*before return 0, iclass 24, count 0 2006.176.07:36:31.63#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:31.63#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:36:31.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:36:31.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:36:31.63$vc4f8/vblo=4,712.99 2006.176.07:36:31.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.07:36:31.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.07:36:31.63#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:31.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:31.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:31.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:31.63#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:36:31.63#ibcon#first serial, iclass 26, count 0 2006.176.07:36:31.63#ibcon#enter sib2, iclass 26, count 0 2006.176.07:36:31.63#ibcon#flushed, iclass 26, count 0 2006.176.07:36:31.63#ibcon#about to write, iclass 26, count 0 2006.176.07:36:31.63#ibcon#wrote, iclass 26, count 0 2006.176.07:36:31.63#ibcon#about to read 3, iclass 26, count 0 2006.176.07:36:31.65#ibcon#read 3, iclass 26, count 0 2006.176.07:36:31.65#ibcon#about to read 4, iclass 26, count 0 2006.176.07:36:31.65#ibcon#read 4, iclass 26, count 0 2006.176.07:36:31.65#ibcon#about to read 5, iclass 26, count 0 2006.176.07:36:31.65#ibcon#read 5, iclass 26, count 0 2006.176.07:36:31.65#ibcon#about to read 6, iclass 26, count 0 2006.176.07:36:31.65#ibcon#read 6, iclass 26, count 0 2006.176.07:36:31.65#ibcon#end of sib2, iclass 26, count 0 2006.176.07:36:31.65#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:36:31.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:36:31.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:36:31.65#ibcon#*before write, iclass 26, count 0 2006.176.07:36:31.65#ibcon#enter sib2, iclass 26, count 0 2006.176.07:36:31.65#ibcon#flushed, iclass 26, count 0 2006.176.07:36:31.65#ibcon#about to write, iclass 26, count 0 2006.176.07:36:31.65#ibcon#wrote, iclass 26, count 0 2006.176.07:36:31.65#ibcon#about to read 3, iclass 26, count 0 2006.176.07:36:31.69#ibcon#read 3, iclass 26, count 0 2006.176.07:36:31.69#ibcon#about to read 4, iclass 26, count 0 2006.176.07:36:31.69#ibcon#read 4, iclass 26, count 0 2006.176.07:36:31.69#ibcon#about to read 5, iclass 26, count 0 2006.176.07:36:31.69#ibcon#read 5, iclass 26, count 0 2006.176.07:36:31.69#ibcon#about to read 6, iclass 26, count 0 2006.176.07:36:31.69#ibcon#read 6, iclass 26, count 0 2006.176.07:36:31.69#ibcon#end of sib2, iclass 26, count 0 2006.176.07:36:31.69#ibcon#*after write, iclass 26, count 0 2006.176.07:36:31.69#ibcon#*before return 0, iclass 26, count 0 2006.176.07:36:31.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:31.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:36:31.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:36:31.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:36:31.69$vc4f8/vb=4,4 2006.176.07:36:31.69#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.07:36:31.69#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.07:36:31.69#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:31.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:31.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:31.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:31.75#ibcon#enter wrdev, iclass 28, count 2 2006.176.07:36:31.75#ibcon#first serial, iclass 28, count 2 2006.176.07:36:31.75#ibcon#enter sib2, iclass 28, count 2 2006.176.07:36:31.75#ibcon#flushed, iclass 28, count 2 2006.176.07:36:31.75#ibcon#about to write, iclass 28, count 2 2006.176.07:36:31.75#ibcon#wrote, iclass 28, count 2 2006.176.07:36:31.75#ibcon#about to read 3, iclass 28, count 2 2006.176.07:36:31.77#ibcon#read 3, iclass 28, count 2 2006.176.07:36:31.77#ibcon#about to read 4, iclass 28, count 2 2006.176.07:36:31.77#ibcon#read 4, iclass 28, count 2 2006.176.07:36:31.77#ibcon#about to read 5, iclass 28, count 2 2006.176.07:36:31.77#ibcon#read 5, iclass 28, count 2 2006.176.07:36:31.77#ibcon#about to read 6, iclass 28, count 2 2006.176.07:36:31.77#ibcon#read 6, iclass 28, count 2 2006.176.07:36:31.77#ibcon#end of sib2, iclass 28, count 2 2006.176.07:36:31.77#ibcon#*mode == 0, iclass 28, count 2 2006.176.07:36:31.77#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.07:36:31.77#ibcon#[27=AT04-04\r\n] 2006.176.07:36:31.77#ibcon#*before write, iclass 28, count 2 2006.176.07:36:31.77#ibcon#enter sib2, iclass 28, count 2 2006.176.07:36:31.77#ibcon#flushed, iclass 28, count 2 2006.176.07:36:31.77#ibcon#about to write, iclass 28, count 2 2006.176.07:36:31.77#ibcon#wrote, iclass 28, count 2 2006.176.07:36:31.77#ibcon#about to read 3, iclass 28, count 2 2006.176.07:36:31.80#ibcon#read 3, iclass 28, count 2 2006.176.07:36:31.80#ibcon#about to read 4, iclass 28, count 2 2006.176.07:36:31.80#ibcon#read 4, iclass 28, count 2 2006.176.07:36:31.80#ibcon#about to read 5, iclass 28, count 2 2006.176.07:36:31.80#ibcon#read 5, iclass 28, count 2 2006.176.07:36:31.80#ibcon#about to read 6, iclass 28, count 2 2006.176.07:36:31.80#ibcon#read 6, iclass 28, count 2 2006.176.07:36:31.80#ibcon#end of sib2, iclass 28, count 2 2006.176.07:36:31.80#ibcon#*after write, iclass 28, count 2 2006.176.07:36:31.80#ibcon#*before return 0, iclass 28, count 2 2006.176.07:36:31.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:31.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:36:31.80#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.07:36:31.80#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:31.80#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:31.92#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:31.92#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:31.92#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:36:31.92#ibcon#first serial, iclass 28, count 0 2006.176.07:36:31.92#ibcon#enter sib2, iclass 28, count 0 2006.176.07:36:31.92#ibcon#flushed, iclass 28, count 0 2006.176.07:36:31.92#ibcon#about to write, iclass 28, count 0 2006.176.07:36:31.92#ibcon#wrote, iclass 28, count 0 2006.176.07:36:31.92#ibcon#about to read 3, iclass 28, count 0 2006.176.07:36:31.94#ibcon#read 3, iclass 28, count 0 2006.176.07:36:31.94#ibcon#about to read 4, iclass 28, count 0 2006.176.07:36:31.94#ibcon#read 4, iclass 28, count 0 2006.176.07:36:31.94#ibcon#about to read 5, iclass 28, count 0 2006.176.07:36:31.94#ibcon#read 5, iclass 28, count 0 2006.176.07:36:31.94#ibcon#about to read 6, iclass 28, count 0 2006.176.07:36:31.94#ibcon#read 6, iclass 28, count 0 2006.176.07:36:31.94#ibcon#end of sib2, iclass 28, count 0 2006.176.07:36:31.94#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:36:31.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:36:31.94#ibcon#[27=USB\r\n] 2006.176.07:36:31.94#ibcon#*before write, iclass 28, count 0 2006.176.07:36:31.94#ibcon#enter sib2, iclass 28, count 0 2006.176.07:36:31.94#ibcon#flushed, iclass 28, count 0 2006.176.07:36:31.94#ibcon#about to write, iclass 28, count 0 2006.176.07:36:31.94#ibcon#wrote, iclass 28, count 0 2006.176.07:36:31.94#ibcon#about to read 3, iclass 28, count 0 2006.176.07:36:31.97#ibcon#read 3, iclass 28, count 0 2006.176.07:36:31.97#ibcon#about to read 4, iclass 28, count 0 2006.176.07:36:31.97#ibcon#read 4, iclass 28, count 0 2006.176.07:36:31.97#ibcon#about to read 5, iclass 28, count 0 2006.176.07:36:31.97#ibcon#read 5, iclass 28, count 0 2006.176.07:36:31.97#ibcon#about to read 6, iclass 28, count 0 2006.176.07:36:31.97#ibcon#read 6, iclass 28, count 0 2006.176.07:36:31.97#ibcon#end of sib2, iclass 28, count 0 2006.176.07:36:31.97#ibcon#*after write, iclass 28, count 0 2006.176.07:36:31.97#ibcon#*before return 0, iclass 28, count 0 2006.176.07:36:31.97#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:31.97#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:36:31.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:36:31.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:36:31.97$vc4f8/vblo=5,744.99 2006.176.07:36:31.97#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.07:36:31.97#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.07:36:31.97#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:31.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:31.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:31.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:31.97#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:36:31.97#ibcon#first serial, iclass 30, count 0 2006.176.07:36:31.97#ibcon#enter sib2, iclass 30, count 0 2006.176.07:36:31.97#ibcon#flushed, iclass 30, count 0 2006.176.07:36:31.97#ibcon#about to write, iclass 30, count 0 2006.176.07:36:31.97#ibcon#wrote, iclass 30, count 0 2006.176.07:36:31.97#ibcon#about to read 3, iclass 30, count 0 2006.176.07:36:31.99#ibcon#read 3, iclass 30, count 0 2006.176.07:36:31.99#ibcon#about to read 4, iclass 30, count 0 2006.176.07:36:31.99#ibcon#read 4, iclass 30, count 0 2006.176.07:36:31.99#ibcon#about to read 5, iclass 30, count 0 2006.176.07:36:31.99#ibcon#read 5, iclass 30, count 0 2006.176.07:36:31.99#ibcon#about to read 6, iclass 30, count 0 2006.176.07:36:31.99#ibcon#read 6, iclass 30, count 0 2006.176.07:36:31.99#ibcon#end of sib2, iclass 30, count 0 2006.176.07:36:31.99#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:36:31.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:36:31.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:36:31.99#ibcon#*before write, iclass 30, count 0 2006.176.07:36:31.99#ibcon#enter sib2, iclass 30, count 0 2006.176.07:36:31.99#ibcon#flushed, iclass 30, count 0 2006.176.07:36:31.99#ibcon#about to write, iclass 30, count 0 2006.176.07:36:31.99#ibcon#wrote, iclass 30, count 0 2006.176.07:36:31.99#ibcon#about to read 3, iclass 30, count 0 2006.176.07:36:32.03#ibcon#read 3, iclass 30, count 0 2006.176.07:36:32.03#ibcon#about to read 4, iclass 30, count 0 2006.176.07:36:32.03#ibcon#read 4, iclass 30, count 0 2006.176.07:36:32.03#ibcon#about to read 5, iclass 30, count 0 2006.176.07:36:32.03#ibcon#read 5, iclass 30, count 0 2006.176.07:36:32.03#ibcon#about to read 6, iclass 30, count 0 2006.176.07:36:32.03#ibcon#read 6, iclass 30, count 0 2006.176.07:36:32.03#ibcon#end of sib2, iclass 30, count 0 2006.176.07:36:32.03#ibcon#*after write, iclass 30, count 0 2006.176.07:36:32.03#ibcon#*before return 0, iclass 30, count 0 2006.176.07:36:32.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:32.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:36:32.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:36:32.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:36:32.03$vc4f8/vb=5,4 2006.176.07:36:32.03#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.176.07:36:32.03#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.176.07:36:32.03#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:32.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:32.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:32.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:32.09#ibcon#enter wrdev, iclass 32, count 2 2006.176.07:36:32.09#ibcon#first serial, iclass 32, count 2 2006.176.07:36:32.09#ibcon#enter sib2, iclass 32, count 2 2006.176.07:36:32.09#ibcon#flushed, iclass 32, count 2 2006.176.07:36:32.09#ibcon#about to write, iclass 32, count 2 2006.176.07:36:32.09#ibcon#wrote, iclass 32, count 2 2006.176.07:36:32.09#ibcon#about to read 3, iclass 32, count 2 2006.176.07:36:32.11#ibcon#read 3, iclass 32, count 2 2006.176.07:36:32.11#ibcon#about to read 4, iclass 32, count 2 2006.176.07:36:32.11#ibcon#read 4, iclass 32, count 2 2006.176.07:36:32.11#ibcon#about to read 5, iclass 32, count 2 2006.176.07:36:32.11#ibcon#read 5, iclass 32, count 2 2006.176.07:36:32.11#ibcon#about to read 6, iclass 32, count 2 2006.176.07:36:32.11#ibcon#read 6, iclass 32, count 2 2006.176.07:36:32.11#ibcon#end of sib2, iclass 32, count 2 2006.176.07:36:32.11#ibcon#*mode == 0, iclass 32, count 2 2006.176.07:36:32.11#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.176.07:36:32.11#ibcon#[27=AT05-04\r\n] 2006.176.07:36:32.11#ibcon#*before write, iclass 32, count 2 2006.176.07:36:32.11#ibcon#enter sib2, iclass 32, count 2 2006.176.07:36:32.11#ibcon#flushed, iclass 32, count 2 2006.176.07:36:32.11#ibcon#about to write, iclass 32, count 2 2006.176.07:36:32.11#ibcon#wrote, iclass 32, count 2 2006.176.07:36:32.11#ibcon#about to read 3, iclass 32, count 2 2006.176.07:36:32.14#ibcon#read 3, iclass 32, count 2 2006.176.07:36:32.14#ibcon#about to read 4, iclass 32, count 2 2006.176.07:36:32.14#ibcon#read 4, iclass 32, count 2 2006.176.07:36:32.14#ibcon#about to read 5, iclass 32, count 2 2006.176.07:36:32.14#ibcon#read 5, iclass 32, count 2 2006.176.07:36:32.14#ibcon#about to read 6, iclass 32, count 2 2006.176.07:36:32.14#ibcon#read 6, iclass 32, count 2 2006.176.07:36:32.14#ibcon#end of sib2, iclass 32, count 2 2006.176.07:36:32.14#ibcon#*after write, iclass 32, count 2 2006.176.07:36:32.14#ibcon#*before return 0, iclass 32, count 2 2006.176.07:36:32.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:32.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:36:32.14#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.176.07:36:32.14#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:32.14#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:32.26#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:32.26#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:32.26#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:36:32.26#ibcon#first serial, iclass 32, count 0 2006.176.07:36:32.26#ibcon#enter sib2, iclass 32, count 0 2006.176.07:36:32.26#ibcon#flushed, iclass 32, count 0 2006.176.07:36:32.26#ibcon#about to write, iclass 32, count 0 2006.176.07:36:32.26#ibcon#wrote, iclass 32, count 0 2006.176.07:36:32.26#ibcon#about to read 3, iclass 32, count 0 2006.176.07:36:32.28#ibcon#read 3, iclass 32, count 0 2006.176.07:36:32.28#ibcon#about to read 4, iclass 32, count 0 2006.176.07:36:32.28#ibcon#read 4, iclass 32, count 0 2006.176.07:36:32.28#ibcon#about to read 5, iclass 32, count 0 2006.176.07:36:32.28#ibcon#read 5, iclass 32, count 0 2006.176.07:36:32.28#ibcon#about to read 6, iclass 32, count 0 2006.176.07:36:32.28#ibcon#read 6, iclass 32, count 0 2006.176.07:36:32.28#ibcon#end of sib2, iclass 32, count 0 2006.176.07:36:32.28#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:36:32.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:36:32.28#ibcon#[27=USB\r\n] 2006.176.07:36:32.28#ibcon#*before write, iclass 32, count 0 2006.176.07:36:32.28#ibcon#enter sib2, iclass 32, count 0 2006.176.07:36:32.28#ibcon#flushed, iclass 32, count 0 2006.176.07:36:32.28#ibcon#about to write, iclass 32, count 0 2006.176.07:36:32.28#ibcon#wrote, iclass 32, count 0 2006.176.07:36:32.28#ibcon#about to read 3, iclass 32, count 0 2006.176.07:36:32.31#ibcon#read 3, iclass 32, count 0 2006.176.07:36:32.31#ibcon#about to read 4, iclass 32, count 0 2006.176.07:36:32.31#ibcon#read 4, iclass 32, count 0 2006.176.07:36:32.31#ibcon#about to read 5, iclass 32, count 0 2006.176.07:36:32.31#ibcon#read 5, iclass 32, count 0 2006.176.07:36:32.31#ibcon#about to read 6, iclass 32, count 0 2006.176.07:36:32.31#ibcon#read 6, iclass 32, count 0 2006.176.07:36:32.31#ibcon#end of sib2, iclass 32, count 0 2006.176.07:36:32.31#ibcon#*after write, iclass 32, count 0 2006.176.07:36:32.31#ibcon#*before return 0, iclass 32, count 0 2006.176.07:36:32.31#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:32.31#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:36:32.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:36:32.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:36:32.31$vc4f8/vblo=6,752.99 2006.176.07:36:32.31#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.07:36:32.31#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.07:36:32.31#ibcon#ireg 17 cls_cnt 0 2006.176.07:36:32.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:32.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:32.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:32.31#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:36:32.31#ibcon#first serial, iclass 34, count 0 2006.176.07:36:32.31#ibcon#enter sib2, iclass 34, count 0 2006.176.07:36:32.31#ibcon#flushed, iclass 34, count 0 2006.176.07:36:32.31#ibcon#about to write, iclass 34, count 0 2006.176.07:36:32.31#ibcon#wrote, iclass 34, count 0 2006.176.07:36:32.31#ibcon#about to read 3, iclass 34, count 0 2006.176.07:36:32.33#ibcon#read 3, iclass 34, count 0 2006.176.07:36:32.33#ibcon#about to read 4, iclass 34, count 0 2006.176.07:36:32.33#ibcon#read 4, iclass 34, count 0 2006.176.07:36:32.33#ibcon#about to read 5, iclass 34, count 0 2006.176.07:36:32.33#ibcon#read 5, iclass 34, count 0 2006.176.07:36:32.33#ibcon#about to read 6, iclass 34, count 0 2006.176.07:36:32.33#ibcon#read 6, iclass 34, count 0 2006.176.07:36:32.33#ibcon#end of sib2, iclass 34, count 0 2006.176.07:36:32.33#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:36:32.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:36:32.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:36:32.33#ibcon#*before write, iclass 34, count 0 2006.176.07:36:32.33#ibcon#enter sib2, iclass 34, count 0 2006.176.07:36:32.33#ibcon#flushed, iclass 34, count 0 2006.176.07:36:32.33#ibcon#about to write, iclass 34, count 0 2006.176.07:36:32.33#ibcon#wrote, iclass 34, count 0 2006.176.07:36:32.33#ibcon#about to read 3, iclass 34, count 0 2006.176.07:36:32.37#ibcon#read 3, iclass 34, count 0 2006.176.07:36:32.37#ibcon#about to read 4, iclass 34, count 0 2006.176.07:36:32.37#ibcon#read 4, iclass 34, count 0 2006.176.07:36:32.37#ibcon#about to read 5, iclass 34, count 0 2006.176.07:36:32.37#ibcon#read 5, iclass 34, count 0 2006.176.07:36:32.37#ibcon#about to read 6, iclass 34, count 0 2006.176.07:36:32.37#ibcon#read 6, iclass 34, count 0 2006.176.07:36:32.37#ibcon#end of sib2, iclass 34, count 0 2006.176.07:36:32.37#ibcon#*after write, iclass 34, count 0 2006.176.07:36:32.37#ibcon#*before return 0, iclass 34, count 0 2006.176.07:36:32.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:32.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:36:32.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:36:32.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:36:32.37$vc4f8/vb=6,4 2006.176.07:36:32.37#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.176.07:36:32.37#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.176.07:36:32.37#ibcon#ireg 11 cls_cnt 2 2006.176.07:36:32.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:32.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:32.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:32.43#ibcon#enter wrdev, iclass 36, count 2 2006.176.07:36:32.43#ibcon#first serial, iclass 36, count 2 2006.176.07:36:32.43#ibcon#enter sib2, iclass 36, count 2 2006.176.07:36:32.43#ibcon#flushed, iclass 36, count 2 2006.176.07:36:32.43#ibcon#about to write, iclass 36, count 2 2006.176.07:36:32.43#ibcon#wrote, iclass 36, count 2 2006.176.07:36:32.43#ibcon#about to read 3, iclass 36, count 2 2006.176.07:36:32.45#ibcon#read 3, iclass 36, count 2 2006.176.07:36:32.45#ibcon#about to read 4, iclass 36, count 2 2006.176.07:36:32.45#ibcon#read 4, iclass 36, count 2 2006.176.07:36:32.45#ibcon#about to read 5, iclass 36, count 2 2006.176.07:36:32.45#ibcon#read 5, iclass 36, count 2 2006.176.07:36:32.45#ibcon#about to read 6, iclass 36, count 2 2006.176.07:36:32.45#ibcon#read 6, iclass 36, count 2 2006.176.07:36:32.45#ibcon#end of sib2, iclass 36, count 2 2006.176.07:36:32.45#ibcon#*mode == 0, iclass 36, count 2 2006.176.07:36:32.45#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.176.07:36:32.45#ibcon#[27=AT06-04\r\n] 2006.176.07:36:32.45#ibcon#*before write, iclass 36, count 2 2006.176.07:36:32.45#ibcon#enter sib2, iclass 36, count 2 2006.176.07:36:32.45#ibcon#flushed, iclass 36, count 2 2006.176.07:36:32.45#ibcon#about to write, iclass 36, count 2 2006.176.07:36:32.45#ibcon#wrote, iclass 36, count 2 2006.176.07:36:32.45#ibcon#about to read 3, iclass 36, count 2 2006.176.07:36:32.48#ibcon#read 3, iclass 36, count 2 2006.176.07:36:32.48#ibcon#about to read 4, iclass 36, count 2 2006.176.07:36:32.48#ibcon#read 4, iclass 36, count 2 2006.176.07:36:32.48#ibcon#about to read 5, iclass 36, count 2 2006.176.07:36:32.48#ibcon#read 5, iclass 36, count 2 2006.176.07:36:32.48#ibcon#about to read 6, iclass 36, count 2 2006.176.07:36:32.48#ibcon#read 6, iclass 36, count 2 2006.176.07:36:32.48#ibcon#end of sib2, iclass 36, count 2 2006.176.07:36:32.48#ibcon#*after write, iclass 36, count 2 2006.176.07:36:32.48#ibcon#*before return 0, iclass 36, count 2 2006.176.07:36:32.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:32.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:36:32.48#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.176.07:36:32.48#ibcon#ireg 7 cls_cnt 0 2006.176.07:36:32.48#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:32.60#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:32.60#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:32.60#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:36:32.60#ibcon#first serial, iclass 36, count 0 2006.176.07:36:32.60#ibcon#enter sib2, iclass 36, count 0 2006.176.07:36:32.60#ibcon#flushed, iclass 36, count 0 2006.176.07:36:32.60#ibcon#about to write, iclass 36, count 0 2006.176.07:36:32.60#ibcon#wrote, iclass 36, count 0 2006.176.07:36:32.60#ibcon#about to read 3, iclass 36, count 0 2006.176.07:36:32.62#ibcon#read 3, iclass 36, count 0 2006.176.07:36:32.62#ibcon#about to read 4, iclass 36, count 0 2006.176.07:36:32.62#ibcon#read 4, iclass 36, count 0 2006.176.07:36:32.62#ibcon#about to read 5, iclass 36, count 0 2006.176.07:36:32.62#ibcon#read 5, iclass 36, count 0 2006.176.07:36:32.62#ibcon#about to read 6, iclass 36, count 0 2006.176.07:36:32.62#ibcon#read 6, iclass 36, count 0 2006.176.07:36:32.62#ibcon#end of sib2, iclass 36, count 0 2006.176.07:36:32.62#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:36:32.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:36:32.62#ibcon#[27=USB\r\n] 2006.176.07:36:32.62#ibcon#*before write, iclass 36, count 0 2006.176.07:36:32.62#ibcon#enter sib2, iclass 36, count 0 2006.176.07:36:32.62#ibcon#flushed, iclass 36, count 0 2006.176.07:36:32.62#ibcon#about to write, iclass 36, count 0 2006.176.07:36:32.62#ibcon#wrote, iclass 36, count 0 2006.176.07:36:32.62#ibcon#about to read 3, iclass 36, count 0 2006.176.07:36:32.65#ibcon#read 3, iclass 36, count 0 2006.176.07:36:32.65#ibcon#about to read 4, iclass 36, count 0 2006.176.07:36:32.65#ibcon#read 4, iclass 36, count 0 2006.176.07:36:32.65#ibcon#about to read 5, iclass 36, count 0 2006.176.07:36:32.65#ibcon#read 5, iclass 36, count 0 2006.176.07:36:32.65#ibcon#about to read 6, iclass 36, count 0 2006.176.07:36:32.65#ibcon#read 6, iclass 36, count 0 2006.176.07:36:32.65#ibcon#end of sib2, iclass 36, count 0 2006.176.07:36:32.65#ibcon#*after write, iclass 36, count 0 2006.176.07:36:32.65#ibcon#*before return 0, iclass 36, count 0 2006.176.07:36:32.65#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:32.65#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:36:32.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:36:32.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:36:32.65$vc4f8/vabw=wide 2006.176.07:36:32.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.07:36:32.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.07:36:32.65#ibcon#ireg 8 cls_cnt 0 2006.176.07:36:32.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:32.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:32.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:32.65#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:36:32.65#ibcon#first serial, iclass 38, count 0 2006.176.07:36:32.65#ibcon#enter sib2, iclass 38, count 0 2006.176.07:36:32.65#ibcon#flushed, iclass 38, count 0 2006.176.07:36:32.65#ibcon#about to write, iclass 38, count 0 2006.176.07:36:32.65#ibcon#wrote, iclass 38, count 0 2006.176.07:36:32.65#ibcon#about to read 3, iclass 38, count 0 2006.176.07:36:32.67#ibcon#read 3, iclass 38, count 0 2006.176.07:36:32.67#ibcon#about to read 4, iclass 38, count 0 2006.176.07:36:32.67#ibcon#read 4, iclass 38, count 0 2006.176.07:36:32.67#ibcon#about to read 5, iclass 38, count 0 2006.176.07:36:32.67#ibcon#read 5, iclass 38, count 0 2006.176.07:36:32.67#ibcon#about to read 6, iclass 38, count 0 2006.176.07:36:32.67#ibcon#read 6, iclass 38, count 0 2006.176.07:36:32.67#ibcon#end of sib2, iclass 38, count 0 2006.176.07:36:32.67#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:36:32.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:36:32.67#ibcon#[25=BW32\r\n] 2006.176.07:36:32.67#ibcon#*before write, iclass 38, count 0 2006.176.07:36:32.67#ibcon#enter sib2, iclass 38, count 0 2006.176.07:36:32.67#ibcon#flushed, iclass 38, count 0 2006.176.07:36:32.67#ibcon#about to write, iclass 38, count 0 2006.176.07:36:32.67#ibcon#wrote, iclass 38, count 0 2006.176.07:36:32.67#ibcon#about to read 3, iclass 38, count 0 2006.176.07:36:32.70#ibcon#read 3, iclass 38, count 0 2006.176.07:36:32.70#ibcon#about to read 4, iclass 38, count 0 2006.176.07:36:32.70#ibcon#read 4, iclass 38, count 0 2006.176.07:36:32.70#ibcon#about to read 5, iclass 38, count 0 2006.176.07:36:32.70#ibcon#read 5, iclass 38, count 0 2006.176.07:36:32.70#ibcon#about to read 6, iclass 38, count 0 2006.176.07:36:32.70#ibcon#read 6, iclass 38, count 0 2006.176.07:36:32.70#ibcon#end of sib2, iclass 38, count 0 2006.176.07:36:32.70#ibcon#*after write, iclass 38, count 0 2006.176.07:36:32.70#ibcon#*before return 0, iclass 38, count 0 2006.176.07:36:32.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:32.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:36:32.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:36:32.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:36:32.71$vc4f8/vbbw=wide 2006.176.07:36:32.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.07:36:32.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.07:36:32.71#ibcon#ireg 8 cls_cnt 0 2006.176.07:36:32.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:36:32.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:36:32.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:36:32.76#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:36:32.76#ibcon#first serial, iclass 40, count 0 2006.176.07:36:32.76#ibcon#enter sib2, iclass 40, count 0 2006.176.07:36:32.76#ibcon#flushed, iclass 40, count 0 2006.176.07:36:32.76#ibcon#about to write, iclass 40, count 0 2006.176.07:36:32.76#ibcon#wrote, iclass 40, count 0 2006.176.07:36:32.76#ibcon#about to read 3, iclass 40, count 0 2006.176.07:36:32.78#ibcon#read 3, iclass 40, count 0 2006.176.07:36:32.78#ibcon#about to read 4, iclass 40, count 0 2006.176.07:36:32.78#ibcon#read 4, iclass 40, count 0 2006.176.07:36:32.78#ibcon#about to read 5, iclass 40, count 0 2006.176.07:36:32.78#ibcon#read 5, iclass 40, count 0 2006.176.07:36:32.78#ibcon#about to read 6, iclass 40, count 0 2006.176.07:36:32.78#ibcon#read 6, iclass 40, count 0 2006.176.07:36:32.78#ibcon#end of sib2, iclass 40, count 0 2006.176.07:36:32.78#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:36:32.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:36:32.78#ibcon#[27=BW32\r\n] 2006.176.07:36:32.78#ibcon#*before write, iclass 40, count 0 2006.176.07:36:32.78#ibcon#enter sib2, iclass 40, count 0 2006.176.07:36:32.78#ibcon#flushed, iclass 40, count 0 2006.176.07:36:32.78#ibcon#about to write, iclass 40, count 0 2006.176.07:36:32.78#ibcon#wrote, iclass 40, count 0 2006.176.07:36:32.78#ibcon#about to read 3, iclass 40, count 0 2006.176.07:36:32.81#ibcon#read 3, iclass 40, count 0 2006.176.07:36:32.81#ibcon#about to read 4, iclass 40, count 0 2006.176.07:36:32.81#ibcon#read 4, iclass 40, count 0 2006.176.07:36:32.81#ibcon#about to read 5, iclass 40, count 0 2006.176.07:36:32.81#ibcon#read 5, iclass 40, count 0 2006.176.07:36:32.81#ibcon#about to read 6, iclass 40, count 0 2006.176.07:36:32.81#ibcon#read 6, iclass 40, count 0 2006.176.07:36:32.81#ibcon#end of sib2, iclass 40, count 0 2006.176.07:36:32.81#ibcon#*after write, iclass 40, count 0 2006.176.07:36:32.81#ibcon#*before return 0, iclass 40, count 0 2006.176.07:36:32.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:36:32.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:36:32.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:36:32.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:36:32.81$4f8m12a/ifd4f 2006.176.07:36:32.81$ifd4f/lo= 2006.176.07:36:32.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:36:32.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:36:32.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:36:32.81$ifd4f/patch= 2006.176.07:36:32.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:36:32.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:36:32.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:36:32.81$4f8m12a/"form=m,16.000,1:2 2006.176.07:36:32.81$4f8m12a/"tpicd 2006.176.07:36:32.81$4f8m12a/echo=off 2006.176.07:36:32.81$4f8m12a/xlog=off 2006.176.07:36:32.81:!2006.176.07:37:00 2006.176.07:36:47.14#trakl#Source acquired 2006.176.07:36:48.14#flagr#flagr/antenna,acquired 2006.176.07:37:00.00:preob 2006.176.07:37:01.14/onsource/TRACKING 2006.176.07:37:01.14:!2006.176.07:37:10 2006.176.07:37:10.00:data_valid=on 2006.176.07:37:10.00:midob 2006.176.07:37:10.14/onsource/TRACKING 2006.176.07:37:10.14/wx/23.96,1008.4,91 2006.176.07:37:10.22/cable/+6.4950E-03 2006.176.07:37:11.31/va/01,08,usb,yes,30,31 2006.176.07:37:11.31/va/02,07,usb,yes,30,31 2006.176.07:37:11.31/va/03,06,usb,yes,31,32 2006.176.07:37:11.31/va/04,07,usb,yes,31,33 2006.176.07:37:11.31/va/05,07,usb,yes,32,34 2006.176.07:37:11.31/va/06,06,usb,yes,31,31 2006.176.07:37:11.31/va/07,06,usb,yes,32,31 2006.176.07:37:11.31/va/08,06,usb,yes,34,33 2006.176.07:37:11.54/valo/01,532.99,yes,locked 2006.176.07:37:11.54/valo/02,572.99,yes,locked 2006.176.07:37:11.54/valo/03,672.99,yes,locked 2006.176.07:37:11.54/valo/04,832.99,yes,locked 2006.176.07:37:11.54/valo/05,652.99,yes,locked 2006.176.07:37:11.54/valo/06,772.99,yes,locked 2006.176.07:37:11.54/valo/07,832.99,yes,locked 2006.176.07:37:11.54/valo/08,852.99,yes,locked 2006.176.07:37:12.63/vb/01,04,usb,yes,30,28 2006.176.07:37:12.63/vb/02,04,usb,yes,31,33 2006.176.07:37:12.63/vb/03,04,usb,yes,28,32 2006.176.07:37:12.63/vb/04,04,usb,yes,29,29 2006.176.07:37:12.63/vb/05,04,usb,yes,27,31 2006.176.07:37:12.63/vb/06,04,usb,yes,28,31 2006.176.07:37:12.63/vb/07,04,usb,yes,30,30 2006.176.07:37:12.63/vb/08,04,usb,yes,28,31 2006.176.07:37:12.86/vblo/01,632.99,yes,locked 2006.176.07:37:12.86/vblo/02,640.99,yes,locked 2006.176.07:37:12.86/vblo/03,656.99,yes,locked 2006.176.07:37:12.86/vblo/04,712.99,yes,locked 2006.176.07:37:12.86/vblo/05,744.99,yes,locked 2006.176.07:37:12.86/vblo/06,752.99,yes,locked 2006.176.07:37:12.86/vblo/07,734.99,yes,locked 2006.176.07:37:12.86/vblo/08,744.99,yes,locked 2006.176.07:37:13.01/vabw/8 2006.176.07:37:13.16/vbbw/8 2006.176.07:37:13.25/xfe/off,on,15.2 2006.176.07:37:13.64/ifatt/23,28,28,28 2006.176.07:37:14.07/fmout-gps/S +3.73E-07 2006.176.07:37:14.11:!2006.176.07:38:10 2006.176.07:38:10.01:data_valid=off 2006.176.07:38:10.01:postob 2006.176.07:38:10.25/cable/+6.4944E-03 2006.176.07:38:10.25/wx/23.95,1008.4,91 2006.176.07:38:11.08/fmout-gps/S +3.72E-07 2006.176.07:38:11.08:scan_name=176-0739,k06176,60 2006.176.07:38:11.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.176.07:38:11.14#flagr#flagr/antenna,new-source 2006.176.07:38:12.14:checkk5 2006.176.07:38:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:38:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:38:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:38:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:38:14.02/chk_obsdata//k5ts1/T1760737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:38:14.39/chk_obsdata//k5ts2/T1760737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:38:14.77/chk_obsdata//k5ts3/T1760737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:38:15.14/chk_obsdata//k5ts4/T1760737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:38:15.83/k5log//k5ts1_log_newline 2006.176.07:38:16.53/k5log//k5ts2_log_newline 2006.176.07:38:17.22/k5log//k5ts3_log_newline 2006.176.07:38:17.88/k5log//k5ts4_log_newline 2006.176.07:38:17.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:38:17.90:4f8m12a=1 2006.176.07:38:17.90$4f8m12a/echo=on 2006.176.07:38:17.90$4f8m12a/pcalon 2006.176.07:38:17.90$pcalon/"no phase cal control is implemented here 2006.176.07:38:17.90$4f8m12a/"tpicd=stop 2006.176.07:38:17.90$4f8m12a/vc4f8 2006.176.07:38:17.90$vc4f8/valo=1,532.99 2006.176.07:38:17.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.07:38:17.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.07:38:17.90#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:17.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:17.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:17.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:17.90#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:38:17.90#ibcon#first serial, iclass 4, count 0 2006.176.07:38:17.90#ibcon#enter sib2, iclass 4, count 0 2006.176.07:38:17.90#ibcon#flushed, iclass 4, count 0 2006.176.07:38:17.90#ibcon#about to write, iclass 4, count 0 2006.176.07:38:17.90#ibcon#wrote, iclass 4, count 0 2006.176.07:38:17.90#ibcon#about to read 3, iclass 4, count 0 2006.176.07:38:17.95#ibcon#read 3, iclass 4, count 0 2006.176.07:38:17.95#ibcon#about to read 4, iclass 4, count 0 2006.176.07:38:17.95#ibcon#read 4, iclass 4, count 0 2006.176.07:38:17.95#ibcon#about to read 5, iclass 4, count 0 2006.176.07:38:17.95#ibcon#read 5, iclass 4, count 0 2006.176.07:38:17.95#ibcon#about to read 6, iclass 4, count 0 2006.176.07:38:17.95#ibcon#read 6, iclass 4, count 0 2006.176.07:38:17.95#ibcon#end of sib2, iclass 4, count 0 2006.176.07:38:17.95#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:38:17.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:38:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:38:17.95#ibcon#*before write, iclass 4, count 0 2006.176.07:38:17.95#ibcon#enter sib2, iclass 4, count 0 2006.176.07:38:17.95#ibcon#flushed, iclass 4, count 0 2006.176.07:38:17.95#ibcon#about to write, iclass 4, count 0 2006.176.07:38:17.95#ibcon#wrote, iclass 4, count 0 2006.176.07:38:17.95#ibcon#about to read 3, iclass 4, count 0 2006.176.07:38:17.99#ibcon#read 3, iclass 4, count 0 2006.176.07:38:17.99#ibcon#about to read 4, iclass 4, count 0 2006.176.07:38:17.99#ibcon#read 4, iclass 4, count 0 2006.176.07:38:17.99#ibcon#about to read 5, iclass 4, count 0 2006.176.07:38:17.99#ibcon#read 5, iclass 4, count 0 2006.176.07:38:17.99#ibcon#about to read 6, iclass 4, count 0 2006.176.07:38:17.99#ibcon#read 6, iclass 4, count 0 2006.176.07:38:17.99#ibcon#end of sib2, iclass 4, count 0 2006.176.07:38:17.99#ibcon#*after write, iclass 4, count 0 2006.176.07:38:17.99#ibcon#*before return 0, iclass 4, count 0 2006.176.07:38:17.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:17.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:17.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:38:17.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:38:17.99$vc4f8/va=1,8 2006.176.07:38:17.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.07:38:17.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.07:38:17.99#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:17.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:17.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:17.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:17.99#ibcon#enter wrdev, iclass 6, count 2 2006.176.07:38:17.99#ibcon#first serial, iclass 6, count 2 2006.176.07:38:17.99#ibcon#enter sib2, iclass 6, count 2 2006.176.07:38:17.99#ibcon#flushed, iclass 6, count 2 2006.176.07:38:17.99#ibcon#about to write, iclass 6, count 2 2006.176.07:38:17.99#ibcon#wrote, iclass 6, count 2 2006.176.07:38:17.99#ibcon#about to read 3, iclass 6, count 2 2006.176.07:38:18.01#ibcon#read 3, iclass 6, count 2 2006.176.07:38:18.01#ibcon#about to read 4, iclass 6, count 2 2006.176.07:38:18.01#ibcon#read 4, iclass 6, count 2 2006.176.07:38:18.01#ibcon#about to read 5, iclass 6, count 2 2006.176.07:38:18.01#ibcon#read 5, iclass 6, count 2 2006.176.07:38:18.01#ibcon#about to read 6, iclass 6, count 2 2006.176.07:38:18.01#ibcon#read 6, iclass 6, count 2 2006.176.07:38:18.01#ibcon#end of sib2, iclass 6, count 2 2006.176.07:38:18.01#ibcon#*mode == 0, iclass 6, count 2 2006.176.07:38:18.01#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.07:38:18.01#ibcon#[25=AT01-08\r\n] 2006.176.07:38:18.01#ibcon#*before write, iclass 6, count 2 2006.176.07:38:18.01#ibcon#enter sib2, iclass 6, count 2 2006.176.07:38:18.01#ibcon#flushed, iclass 6, count 2 2006.176.07:38:18.01#ibcon#about to write, iclass 6, count 2 2006.176.07:38:18.01#ibcon#wrote, iclass 6, count 2 2006.176.07:38:18.01#ibcon#about to read 3, iclass 6, count 2 2006.176.07:38:18.04#ibcon#read 3, iclass 6, count 2 2006.176.07:38:18.04#ibcon#about to read 4, iclass 6, count 2 2006.176.07:38:18.04#ibcon#read 4, iclass 6, count 2 2006.176.07:38:18.04#ibcon#about to read 5, iclass 6, count 2 2006.176.07:38:18.04#ibcon#read 5, iclass 6, count 2 2006.176.07:38:18.04#ibcon#about to read 6, iclass 6, count 2 2006.176.07:38:18.04#ibcon#read 6, iclass 6, count 2 2006.176.07:38:18.04#ibcon#end of sib2, iclass 6, count 2 2006.176.07:38:18.04#ibcon#*after write, iclass 6, count 2 2006.176.07:38:18.04#ibcon#*before return 0, iclass 6, count 2 2006.176.07:38:18.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:18.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:18.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.07:38:18.04#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:18.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:18.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:18.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:18.16#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:38:18.16#ibcon#first serial, iclass 6, count 0 2006.176.07:38:18.16#ibcon#enter sib2, iclass 6, count 0 2006.176.07:38:18.16#ibcon#flushed, iclass 6, count 0 2006.176.07:38:18.16#ibcon#about to write, iclass 6, count 0 2006.176.07:38:18.16#ibcon#wrote, iclass 6, count 0 2006.176.07:38:18.16#ibcon#about to read 3, iclass 6, count 0 2006.176.07:38:18.18#ibcon#read 3, iclass 6, count 0 2006.176.07:38:18.18#ibcon#about to read 4, iclass 6, count 0 2006.176.07:38:18.18#ibcon#read 4, iclass 6, count 0 2006.176.07:38:18.18#ibcon#about to read 5, iclass 6, count 0 2006.176.07:38:18.18#ibcon#read 5, iclass 6, count 0 2006.176.07:38:18.18#ibcon#about to read 6, iclass 6, count 0 2006.176.07:38:18.18#ibcon#read 6, iclass 6, count 0 2006.176.07:38:18.18#ibcon#end of sib2, iclass 6, count 0 2006.176.07:38:18.18#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:38:18.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:38:18.18#ibcon#[25=USB\r\n] 2006.176.07:38:18.18#ibcon#*before write, iclass 6, count 0 2006.176.07:38:18.18#ibcon#enter sib2, iclass 6, count 0 2006.176.07:38:18.18#ibcon#flushed, iclass 6, count 0 2006.176.07:38:18.18#ibcon#about to write, iclass 6, count 0 2006.176.07:38:18.18#ibcon#wrote, iclass 6, count 0 2006.176.07:38:18.18#ibcon#about to read 3, iclass 6, count 0 2006.176.07:38:18.21#ibcon#read 3, iclass 6, count 0 2006.176.07:38:18.21#ibcon#about to read 4, iclass 6, count 0 2006.176.07:38:18.21#ibcon#read 4, iclass 6, count 0 2006.176.07:38:18.21#ibcon#about to read 5, iclass 6, count 0 2006.176.07:38:18.21#ibcon#read 5, iclass 6, count 0 2006.176.07:38:18.21#ibcon#about to read 6, iclass 6, count 0 2006.176.07:38:18.21#ibcon#read 6, iclass 6, count 0 2006.176.07:38:18.21#ibcon#end of sib2, iclass 6, count 0 2006.176.07:38:18.21#ibcon#*after write, iclass 6, count 0 2006.176.07:38:18.21#ibcon#*before return 0, iclass 6, count 0 2006.176.07:38:18.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:18.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:18.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:38:18.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:38:18.21$vc4f8/valo=2,572.99 2006.176.07:38:18.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.07:38:18.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.07:38:18.21#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:18.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:18.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:18.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:18.21#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:38:18.21#ibcon#first serial, iclass 10, count 0 2006.176.07:38:18.21#ibcon#enter sib2, iclass 10, count 0 2006.176.07:38:18.21#ibcon#flushed, iclass 10, count 0 2006.176.07:38:18.21#ibcon#about to write, iclass 10, count 0 2006.176.07:38:18.21#ibcon#wrote, iclass 10, count 0 2006.176.07:38:18.21#ibcon#about to read 3, iclass 10, count 0 2006.176.07:38:18.23#ibcon#read 3, iclass 10, count 0 2006.176.07:38:18.23#ibcon#about to read 4, iclass 10, count 0 2006.176.07:38:18.23#ibcon#read 4, iclass 10, count 0 2006.176.07:38:18.23#ibcon#about to read 5, iclass 10, count 0 2006.176.07:38:18.23#ibcon#read 5, iclass 10, count 0 2006.176.07:38:18.23#ibcon#about to read 6, iclass 10, count 0 2006.176.07:38:18.23#ibcon#read 6, iclass 10, count 0 2006.176.07:38:18.23#ibcon#end of sib2, iclass 10, count 0 2006.176.07:38:18.23#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:38:18.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:38:18.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:38:18.23#ibcon#*before write, iclass 10, count 0 2006.176.07:38:18.23#ibcon#enter sib2, iclass 10, count 0 2006.176.07:38:18.23#ibcon#flushed, iclass 10, count 0 2006.176.07:38:18.23#ibcon#about to write, iclass 10, count 0 2006.176.07:38:18.23#ibcon#wrote, iclass 10, count 0 2006.176.07:38:18.23#ibcon#about to read 3, iclass 10, count 0 2006.176.07:38:18.27#ibcon#read 3, iclass 10, count 0 2006.176.07:38:18.27#ibcon#about to read 4, iclass 10, count 0 2006.176.07:38:18.27#ibcon#read 4, iclass 10, count 0 2006.176.07:38:18.27#ibcon#about to read 5, iclass 10, count 0 2006.176.07:38:18.27#ibcon#read 5, iclass 10, count 0 2006.176.07:38:18.27#ibcon#about to read 6, iclass 10, count 0 2006.176.07:38:18.27#ibcon#read 6, iclass 10, count 0 2006.176.07:38:18.27#ibcon#end of sib2, iclass 10, count 0 2006.176.07:38:18.27#ibcon#*after write, iclass 10, count 0 2006.176.07:38:18.27#ibcon#*before return 0, iclass 10, count 0 2006.176.07:38:18.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:18.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:18.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:38:18.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:38:18.27$vc4f8/va=2,7 2006.176.07:38:18.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.07:38:18.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.07:38:18.27#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:18.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:18.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:18.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:18.33#ibcon#enter wrdev, iclass 12, count 2 2006.176.07:38:18.33#ibcon#first serial, iclass 12, count 2 2006.176.07:38:18.33#ibcon#enter sib2, iclass 12, count 2 2006.176.07:38:18.33#ibcon#flushed, iclass 12, count 2 2006.176.07:38:18.33#ibcon#about to write, iclass 12, count 2 2006.176.07:38:18.33#ibcon#wrote, iclass 12, count 2 2006.176.07:38:18.33#ibcon#about to read 3, iclass 12, count 2 2006.176.07:38:18.35#ibcon#read 3, iclass 12, count 2 2006.176.07:38:18.35#ibcon#about to read 4, iclass 12, count 2 2006.176.07:38:18.35#ibcon#read 4, iclass 12, count 2 2006.176.07:38:18.35#ibcon#about to read 5, iclass 12, count 2 2006.176.07:38:18.35#ibcon#read 5, iclass 12, count 2 2006.176.07:38:18.35#ibcon#about to read 6, iclass 12, count 2 2006.176.07:38:18.35#ibcon#read 6, iclass 12, count 2 2006.176.07:38:18.35#ibcon#end of sib2, iclass 12, count 2 2006.176.07:38:18.35#ibcon#*mode == 0, iclass 12, count 2 2006.176.07:38:18.35#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.07:38:18.35#ibcon#[25=AT02-07\r\n] 2006.176.07:38:18.35#ibcon#*before write, iclass 12, count 2 2006.176.07:38:18.35#ibcon#enter sib2, iclass 12, count 2 2006.176.07:38:18.35#ibcon#flushed, iclass 12, count 2 2006.176.07:38:18.35#ibcon#about to write, iclass 12, count 2 2006.176.07:38:18.35#ibcon#wrote, iclass 12, count 2 2006.176.07:38:18.35#ibcon#about to read 3, iclass 12, count 2 2006.176.07:38:18.39#ibcon#read 3, iclass 12, count 2 2006.176.07:38:18.39#ibcon#about to read 4, iclass 12, count 2 2006.176.07:38:18.39#ibcon#read 4, iclass 12, count 2 2006.176.07:38:18.39#ibcon#about to read 5, iclass 12, count 2 2006.176.07:38:18.39#ibcon#read 5, iclass 12, count 2 2006.176.07:38:18.39#ibcon#about to read 6, iclass 12, count 2 2006.176.07:38:18.39#ibcon#read 6, iclass 12, count 2 2006.176.07:38:18.39#ibcon#end of sib2, iclass 12, count 2 2006.176.07:38:18.39#ibcon#*after write, iclass 12, count 2 2006.176.07:38:18.39#ibcon#*before return 0, iclass 12, count 2 2006.176.07:38:18.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:18.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:18.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.07:38:18.39#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:18.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:18.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:18.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:18.51#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:38:18.51#ibcon#first serial, iclass 12, count 0 2006.176.07:38:18.51#ibcon#enter sib2, iclass 12, count 0 2006.176.07:38:18.51#ibcon#flushed, iclass 12, count 0 2006.176.07:38:18.51#ibcon#about to write, iclass 12, count 0 2006.176.07:38:18.51#ibcon#wrote, iclass 12, count 0 2006.176.07:38:18.51#ibcon#about to read 3, iclass 12, count 0 2006.176.07:38:18.53#ibcon#read 3, iclass 12, count 0 2006.176.07:38:18.53#ibcon#about to read 4, iclass 12, count 0 2006.176.07:38:18.53#ibcon#read 4, iclass 12, count 0 2006.176.07:38:18.53#ibcon#about to read 5, iclass 12, count 0 2006.176.07:38:18.53#ibcon#read 5, iclass 12, count 0 2006.176.07:38:18.53#ibcon#about to read 6, iclass 12, count 0 2006.176.07:38:18.53#ibcon#read 6, iclass 12, count 0 2006.176.07:38:18.53#ibcon#end of sib2, iclass 12, count 0 2006.176.07:38:18.53#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:38:18.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:38:18.53#ibcon#[25=USB\r\n] 2006.176.07:38:18.53#ibcon#*before write, iclass 12, count 0 2006.176.07:38:18.53#ibcon#enter sib2, iclass 12, count 0 2006.176.07:38:18.53#ibcon#flushed, iclass 12, count 0 2006.176.07:38:18.53#ibcon#about to write, iclass 12, count 0 2006.176.07:38:18.53#ibcon#wrote, iclass 12, count 0 2006.176.07:38:18.53#ibcon#about to read 3, iclass 12, count 0 2006.176.07:38:18.56#ibcon#read 3, iclass 12, count 0 2006.176.07:38:18.56#ibcon#about to read 4, iclass 12, count 0 2006.176.07:38:18.56#ibcon#read 4, iclass 12, count 0 2006.176.07:38:18.56#ibcon#about to read 5, iclass 12, count 0 2006.176.07:38:18.56#ibcon#read 5, iclass 12, count 0 2006.176.07:38:18.56#ibcon#about to read 6, iclass 12, count 0 2006.176.07:38:18.56#ibcon#read 6, iclass 12, count 0 2006.176.07:38:18.56#ibcon#end of sib2, iclass 12, count 0 2006.176.07:38:18.56#ibcon#*after write, iclass 12, count 0 2006.176.07:38:18.56#ibcon#*before return 0, iclass 12, count 0 2006.176.07:38:18.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:18.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:18.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:38:18.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:38:18.56$vc4f8/valo=3,672.99 2006.176.07:38:18.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.07:38:18.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.07:38:18.56#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:18.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:18.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:18.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:18.56#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:38:18.56#ibcon#first serial, iclass 14, count 0 2006.176.07:38:18.56#ibcon#enter sib2, iclass 14, count 0 2006.176.07:38:18.56#ibcon#flushed, iclass 14, count 0 2006.176.07:38:18.56#ibcon#about to write, iclass 14, count 0 2006.176.07:38:18.56#ibcon#wrote, iclass 14, count 0 2006.176.07:38:18.56#ibcon#about to read 3, iclass 14, count 0 2006.176.07:38:18.58#ibcon#read 3, iclass 14, count 0 2006.176.07:38:18.58#ibcon#about to read 4, iclass 14, count 0 2006.176.07:38:18.58#ibcon#read 4, iclass 14, count 0 2006.176.07:38:18.58#ibcon#about to read 5, iclass 14, count 0 2006.176.07:38:18.58#ibcon#read 5, iclass 14, count 0 2006.176.07:38:18.58#ibcon#about to read 6, iclass 14, count 0 2006.176.07:38:18.58#ibcon#read 6, iclass 14, count 0 2006.176.07:38:18.58#ibcon#end of sib2, iclass 14, count 0 2006.176.07:38:18.58#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:38:18.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:38:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:38:18.58#ibcon#*before write, iclass 14, count 0 2006.176.07:38:18.58#ibcon#enter sib2, iclass 14, count 0 2006.176.07:38:18.58#ibcon#flushed, iclass 14, count 0 2006.176.07:38:18.58#ibcon#about to write, iclass 14, count 0 2006.176.07:38:18.58#ibcon#wrote, iclass 14, count 0 2006.176.07:38:18.58#ibcon#about to read 3, iclass 14, count 0 2006.176.07:38:18.62#ibcon#read 3, iclass 14, count 0 2006.176.07:38:18.62#ibcon#about to read 4, iclass 14, count 0 2006.176.07:38:18.62#ibcon#read 4, iclass 14, count 0 2006.176.07:38:18.62#ibcon#about to read 5, iclass 14, count 0 2006.176.07:38:18.62#ibcon#read 5, iclass 14, count 0 2006.176.07:38:18.62#ibcon#about to read 6, iclass 14, count 0 2006.176.07:38:18.62#ibcon#read 6, iclass 14, count 0 2006.176.07:38:18.62#ibcon#end of sib2, iclass 14, count 0 2006.176.07:38:18.62#ibcon#*after write, iclass 14, count 0 2006.176.07:38:18.62#ibcon#*before return 0, iclass 14, count 0 2006.176.07:38:18.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:18.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:18.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:38:18.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:38:18.62$vc4f8/va=3,6 2006.176.07:38:18.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.07:38:18.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.07:38:18.62#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:18.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:18.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:18.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:18.68#ibcon#enter wrdev, iclass 16, count 2 2006.176.07:38:18.68#ibcon#first serial, iclass 16, count 2 2006.176.07:38:18.68#ibcon#enter sib2, iclass 16, count 2 2006.176.07:38:18.68#ibcon#flushed, iclass 16, count 2 2006.176.07:38:18.68#ibcon#about to write, iclass 16, count 2 2006.176.07:38:18.68#ibcon#wrote, iclass 16, count 2 2006.176.07:38:18.68#ibcon#about to read 3, iclass 16, count 2 2006.176.07:38:18.70#ibcon#read 3, iclass 16, count 2 2006.176.07:38:18.70#ibcon#about to read 4, iclass 16, count 2 2006.176.07:38:18.70#ibcon#read 4, iclass 16, count 2 2006.176.07:38:18.70#ibcon#about to read 5, iclass 16, count 2 2006.176.07:38:18.70#ibcon#read 5, iclass 16, count 2 2006.176.07:38:18.70#ibcon#about to read 6, iclass 16, count 2 2006.176.07:38:18.70#ibcon#read 6, iclass 16, count 2 2006.176.07:38:18.70#ibcon#end of sib2, iclass 16, count 2 2006.176.07:38:18.70#ibcon#*mode == 0, iclass 16, count 2 2006.176.07:38:18.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.07:38:18.70#ibcon#[25=AT03-06\r\n] 2006.176.07:38:18.70#ibcon#*before write, iclass 16, count 2 2006.176.07:38:18.70#ibcon#enter sib2, iclass 16, count 2 2006.176.07:38:18.70#ibcon#flushed, iclass 16, count 2 2006.176.07:38:18.70#ibcon#about to write, iclass 16, count 2 2006.176.07:38:18.70#ibcon#wrote, iclass 16, count 2 2006.176.07:38:18.70#ibcon#about to read 3, iclass 16, count 2 2006.176.07:38:18.73#ibcon#read 3, iclass 16, count 2 2006.176.07:38:18.73#ibcon#about to read 4, iclass 16, count 2 2006.176.07:38:18.73#ibcon#read 4, iclass 16, count 2 2006.176.07:38:18.73#ibcon#about to read 5, iclass 16, count 2 2006.176.07:38:18.73#ibcon#read 5, iclass 16, count 2 2006.176.07:38:18.73#ibcon#about to read 6, iclass 16, count 2 2006.176.07:38:18.73#ibcon#read 6, iclass 16, count 2 2006.176.07:38:18.73#ibcon#end of sib2, iclass 16, count 2 2006.176.07:38:18.73#ibcon#*after write, iclass 16, count 2 2006.176.07:38:18.73#ibcon#*before return 0, iclass 16, count 2 2006.176.07:38:18.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:18.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:18.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.07:38:18.73#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:18.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:18.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:18.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:18.85#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:38:18.85#ibcon#first serial, iclass 16, count 0 2006.176.07:38:18.85#ibcon#enter sib2, iclass 16, count 0 2006.176.07:38:18.85#ibcon#flushed, iclass 16, count 0 2006.176.07:38:18.85#ibcon#about to write, iclass 16, count 0 2006.176.07:38:18.85#ibcon#wrote, iclass 16, count 0 2006.176.07:38:18.85#ibcon#about to read 3, iclass 16, count 0 2006.176.07:38:18.87#ibcon#read 3, iclass 16, count 0 2006.176.07:38:18.87#ibcon#about to read 4, iclass 16, count 0 2006.176.07:38:18.87#ibcon#read 4, iclass 16, count 0 2006.176.07:38:18.87#ibcon#about to read 5, iclass 16, count 0 2006.176.07:38:18.87#ibcon#read 5, iclass 16, count 0 2006.176.07:38:18.87#ibcon#about to read 6, iclass 16, count 0 2006.176.07:38:18.87#ibcon#read 6, iclass 16, count 0 2006.176.07:38:18.87#ibcon#end of sib2, iclass 16, count 0 2006.176.07:38:18.87#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:38:18.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:38:18.87#ibcon#[25=USB\r\n] 2006.176.07:38:18.87#ibcon#*before write, iclass 16, count 0 2006.176.07:38:18.87#ibcon#enter sib2, iclass 16, count 0 2006.176.07:38:18.87#ibcon#flushed, iclass 16, count 0 2006.176.07:38:18.87#ibcon#about to write, iclass 16, count 0 2006.176.07:38:18.87#ibcon#wrote, iclass 16, count 0 2006.176.07:38:18.87#ibcon#about to read 3, iclass 16, count 0 2006.176.07:38:18.90#ibcon#read 3, iclass 16, count 0 2006.176.07:38:18.90#ibcon#about to read 4, iclass 16, count 0 2006.176.07:38:18.90#ibcon#read 4, iclass 16, count 0 2006.176.07:38:18.90#ibcon#about to read 5, iclass 16, count 0 2006.176.07:38:18.90#ibcon#read 5, iclass 16, count 0 2006.176.07:38:18.90#ibcon#about to read 6, iclass 16, count 0 2006.176.07:38:18.90#ibcon#read 6, iclass 16, count 0 2006.176.07:38:18.90#ibcon#end of sib2, iclass 16, count 0 2006.176.07:38:18.90#ibcon#*after write, iclass 16, count 0 2006.176.07:38:18.90#ibcon#*before return 0, iclass 16, count 0 2006.176.07:38:18.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:18.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:18.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:38:18.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:38:18.90$vc4f8/valo=4,832.99 2006.176.07:38:18.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.07:38:18.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.07:38:18.90#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:18.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:38:18.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:38:18.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:38:18.90#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:38:18.90#ibcon#first serial, iclass 18, count 0 2006.176.07:38:18.90#ibcon#enter sib2, iclass 18, count 0 2006.176.07:38:18.90#ibcon#flushed, iclass 18, count 0 2006.176.07:38:18.90#ibcon#about to write, iclass 18, count 0 2006.176.07:38:18.90#ibcon#wrote, iclass 18, count 0 2006.176.07:38:18.90#ibcon#about to read 3, iclass 18, count 0 2006.176.07:38:18.92#ibcon#read 3, iclass 18, count 0 2006.176.07:38:18.92#ibcon#about to read 4, iclass 18, count 0 2006.176.07:38:18.92#ibcon#read 4, iclass 18, count 0 2006.176.07:38:18.92#ibcon#about to read 5, iclass 18, count 0 2006.176.07:38:18.92#ibcon#read 5, iclass 18, count 0 2006.176.07:38:18.92#ibcon#about to read 6, iclass 18, count 0 2006.176.07:38:18.92#ibcon#read 6, iclass 18, count 0 2006.176.07:38:18.92#ibcon#end of sib2, iclass 18, count 0 2006.176.07:38:18.92#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:38:18.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:38:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:38:18.92#ibcon#*before write, iclass 18, count 0 2006.176.07:38:18.92#ibcon#enter sib2, iclass 18, count 0 2006.176.07:38:18.92#ibcon#flushed, iclass 18, count 0 2006.176.07:38:18.92#ibcon#about to write, iclass 18, count 0 2006.176.07:38:18.92#ibcon#wrote, iclass 18, count 0 2006.176.07:38:18.92#ibcon#about to read 3, iclass 18, count 0 2006.176.07:38:18.96#ibcon#read 3, iclass 18, count 0 2006.176.07:38:18.96#ibcon#about to read 4, iclass 18, count 0 2006.176.07:38:18.96#ibcon#read 4, iclass 18, count 0 2006.176.07:38:18.96#ibcon#about to read 5, iclass 18, count 0 2006.176.07:38:18.96#ibcon#read 5, iclass 18, count 0 2006.176.07:38:18.96#ibcon#about to read 6, iclass 18, count 0 2006.176.07:38:18.96#ibcon#read 6, iclass 18, count 0 2006.176.07:38:18.96#ibcon#end of sib2, iclass 18, count 0 2006.176.07:38:18.96#ibcon#*after write, iclass 18, count 0 2006.176.07:38:18.96#ibcon#*before return 0, iclass 18, count 0 2006.176.07:38:18.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:38:18.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:38:18.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:38:18.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:38:18.96$vc4f8/va=4,7 2006.176.07:38:18.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.07:38:18.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.07:38:18.96#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:18.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:38:19.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:38:19.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:38:19.02#ibcon#enter wrdev, iclass 20, count 2 2006.176.07:38:19.02#ibcon#first serial, iclass 20, count 2 2006.176.07:38:19.02#ibcon#enter sib2, iclass 20, count 2 2006.176.07:38:19.02#ibcon#flushed, iclass 20, count 2 2006.176.07:38:19.02#ibcon#about to write, iclass 20, count 2 2006.176.07:38:19.02#ibcon#wrote, iclass 20, count 2 2006.176.07:38:19.02#ibcon#about to read 3, iclass 20, count 2 2006.176.07:38:19.04#ibcon#read 3, iclass 20, count 2 2006.176.07:38:19.04#ibcon#about to read 4, iclass 20, count 2 2006.176.07:38:19.04#ibcon#read 4, iclass 20, count 2 2006.176.07:38:19.04#ibcon#about to read 5, iclass 20, count 2 2006.176.07:38:19.04#ibcon#read 5, iclass 20, count 2 2006.176.07:38:19.04#ibcon#about to read 6, iclass 20, count 2 2006.176.07:38:19.04#ibcon#read 6, iclass 20, count 2 2006.176.07:38:19.04#ibcon#end of sib2, iclass 20, count 2 2006.176.07:38:19.04#ibcon#*mode == 0, iclass 20, count 2 2006.176.07:38:19.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.07:38:19.04#ibcon#[25=AT04-07\r\n] 2006.176.07:38:19.04#ibcon#*before write, iclass 20, count 2 2006.176.07:38:19.04#ibcon#enter sib2, iclass 20, count 2 2006.176.07:38:19.04#ibcon#flushed, iclass 20, count 2 2006.176.07:38:19.04#ibcon#about to write, iclass 20, count 2 2006.176.07:38:19.04#ibcon#wrote, iclass 20, count 2 2006.176.07:38:19.04#ibcon#about to read 3, iclass 20, count 2 2006.176.07:38:19.07#ibcon#read 3, iclass 20, count 2 2006.176.07:38:19.07#ibcon#about to read 4, iclass 20, count 2 2006.176.07:38:19.07#ibcon#read 4, iclass 20, count 2 2006.176.07:38:19.07#ibcon#about to read 5, iclass 20, count 2 2006.176.07:38:19.07#ibcon#read 5, iclass 20, count 2 2006.176.07:38:19.07#ibcon#about to read 6, iclass 20, count 2 2006.176.07:38:19.07#ibcon#read 6, iclass 20, count 2 2006.176.07:38:19.07#ibcon#end of sib2, iclass 20, count 2 2006.176.07:38:19.07#ibcon#*after write, iclass 20, count 2 2006.176.07:38:19.07#ibcon#*before return 0, iclass 20, count 2 2006.176.07:38:19.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:38:19.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:38:19.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.07:38:19.07#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:19.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:38:19.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:38:19.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:38:19.19#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:38:19.19#ibcon#first serial, iclass 20, count 0 2006.176.07:38:19.19#ibcon#enter sib2, iclass 20, count 0 2006.176.07:38:19.19#ibcon#flushed, iclass 20, count 0 2006.176.07:38:19.19#ibcon#about to write, iclass 20, count 0 2006.176.07:38:19.19#ibcon#wrote, iclass 20, count 0 2006.176.07:38:19.19#ibcon#about to read 3, iclass 20, count 0 2006.176.07:38:19.21#ibcon#read 3, iclass 20, count 0 2006.176.07:38:19.21#ibcon#about to read 4, iclass 20, count 0 2006.176.07:38:19.21#ibcon#read 4, iclass 20, count 0 2006.176.07:38:19.21#ibcon#about to read 5, iclass 20, count 0 2006.176.07:38:19.21#ibcon#read 5, iclass 20, count 0 2006.176.07:38:19.21#ibcon#about to read 6, iclass 20, count 0 2006.176.07:38:19.21#ibcon#read 6, iclass 20, count 0 2006.176.07:38:19.21#ibcon#end of sib2, iclass 20, count 0 2006.176.07:38:19.21#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:38:19.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:38:19.21#ibcon#[25=USB\r\n] 2006.176.07:38:19.21#ibcon#*before write, iclass 20, count 0 2006.176.07:38:19.21#ibcon#enter sib2, iclass 20, count 0 2006.176.07:38:19.21#ibcon#flushed, iclass 20, count 0 2006.176.07:38:19.21#ibcon#about to write, iclass 20, count 0 2006.176.07:38:19.21#ibcon#wrote, iclass 20, count 0 2006.176.07:38:19.21#ibcon#about to read 3, iclass 20, count 0 2006.176.07:38:19.24#ibcon#read 3, iclass 20, count 0 2006.176.07:38:19.24#ibcon#about to read 4, iclass 20, count 0 2006.176.07:38:19.24#ibcon#read 4, iclass 20, count 0 2006.176.07:38:19.24#ibcon#about to read 5, iclass 20, count 0 2006.176.07:38:19.24#ibcon#read 5, iclass 20, count 0 2006.176.07:38:19.24#ibcon#about to read 6, iclass 20, count 0 2006.176.07:38:19.24#ibcon#read 6, iclass 20, count 0 2006.176.07:38:19.24#ibcon#end of sib2, iclass 20, count 0 2006.176.07:38:19.24#ibcon#*after write, iclass 20, count 0 2006.176.07:38:19.24#ibcon#*before return 0, iclass 20, count 0 2006.176.07:38:19.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:38:19.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:38:19.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:38:19.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:38:19.24$vc4f8/valo=5,652.99 2006.176.07:38:19.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.07:38:19.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.07:38:19.24#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:19.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:19.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:19.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:19.24#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:38:19.24#ibcon#first serial, iclass 22, count 0 2006.176.07:38:19.24#ibcon#enter sib2, iclass 22, count 0 2006.176.07:38:19.24#ibcon#flushed, iclass 22, count 0 2006.176.07:38:19.24#ibcon#about to write, iclass 22, count 0 2006.176.07:38:19.24#ibcon#wrote, iclass 22, count 0 2006.176.07:38:19.24#ibcon#about to read 3, iclass 22, count 0 2006.176.07:38:19.26#ibcon#read 3, iclass 22, count 0 2006.176.07:38:19.26#ibcon#about to read 4, iclass 22, count 0 2006.176.07:38:19.26#ibcon#read 4, iclass 22, count 0 2006.176.07:38:19.26#ibcon#about to read 5, iclass 22, count 0 2006.176.07:38:19.26#ibcon#read 5, iclass 22, count 0 2006.176.07:38:19.26#ibcon#about to read 6, iclass 22, count 0 2006.176.07:38:19.26#ibcon#read 6, iclass 22, count 0 2006.176.07:38:19.26#ibcon#end of sib2, iclass 22, count 0 2006.176.07:38:19.26#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:38:19.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:38:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:38:19.26#ibcon#*before write, iclass 22, count 0 2006.176.07:38:19.26#ibcon#enter sib2, iclass 22, count 0 2006.176.07:38:19.26#ibcon#flushed, iclass 22, count 0 2006.176.07:38:19.26#ibcon#about to write, iclass 22, count 0 2006.176.07:38:19.26#ibcon#wrote, iclass 22, count 0 2006.176.07:38:19.26#ibcon#about to read 3, iclass 22, count 0 2006.176.07:38:19.30#ibcon#read 3, iclass 22, count 0 2006.176.07:38:19.30#ibcon#about to read 4, iclass 22, count 0 2006.176.07:38:19.30#ibcon#read 4, iclass 22, count 0 2006.176.07:38:19.30#ibcon#about to read 5, iclass 22, count 0 2006.176.07:38:19.30#ibcon#read 5, iclass 22, count 0 2006.176.07:38:19.30#ibcon#about to read 6, iclass 22, count 0 2006.176.07:38:19.30#ibcon#read 6, iclass 22, count 0 2006.176.07:38:19.30#ibcon#end of sib2, iclass 22, count 0 2006.176.07:38:19.30#ibcon#*after write, iclass 22, count 0 2006.176.07:38:19.30#ibcon#*before return 0, iclass 22, count 0 2006.176.07:38:19.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:19.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:19.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:38:19.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:38:19.30$vc4f8/va=5,7 2006.176.07:38:19.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.07:38:19.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.07:38:19.30#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:19.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:19.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:19.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:19.36#ibcon#enter wrdev, iclass 24, count 2 2006.176.07:38:19.36#ibcon#first serial, iclass 24, count 2 2006.176.07:38:19.36#ibcon#enter sib2, iclass 24, count 2 2006.176.07:38:19.36#ibcon#flushed, iclass 24, count 2 2006.176.07:38:19.36#ibcon#about to write, iclass 24, count 2 2006.176.07:38:19.36#ibcon#wrote, iclass 24, count 2 2006.176.07:38:19.36#ibcon#about to read 3, iclass 24, count 2 2006.176.07:38:19.38#ibcon#read 3, iclass 24, count 2 2006.176.07:38:19.38#ibcon#about to read 4, iclass 24, count 2 2006.176.07:38:19.38#ibcon#read 4, iclass 24, count 2 2006.176.07:38:19.38#ibcon#about to read 5, iclass 24, count 2 2006.176.07:38:19.38#ibcon#read 5, iclass 24, count 2 2006.176.07:38:19.38#ibcon#about to read 6, iclass 24, count 2 2006.176.07:38:19.38#ibcon#read 6, iclass 24, count 2 2006.176.07:38:19.38#ibcon#end of sib2, iclass 24, count 2 2006.176.07:38:19.38#ibcon#*mode == 0, iclass 24, count 2 2006.176.07:38:19.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.07:38:19.38#ibcon#[25=AT05-07\r\n] 2006.176.07:38:19.38#ibcon#*before write, iclass 24, count 2 2006.176.07:38:19.38#ibcon#enter sib2, iclass 24, count 2 2006.176.07:38:19.38#ibcon#flushed, iclass 24, count 2 2006.176.07:38:19.38#ibcon#about to write, iclass 24, count 2 2006.176.07:38:19.38#ibcon#wrote, iclass 24, count 2 2006.176.07:38:19.38#ibcon#about to read 3, iclass 24, count 2 2006.176.07:38:19.41#ibcon#read 3, iclass 24, count 2 2006.176.07:38:19.41#ibcon#about to read 4, iclass 24, count 2 2006.176.07:38:19.41#ibcon#read 4, iclass 24, count 2 2006.176.07:38:19.41#ibcon#about to read 5, iclass 24, count 2 2006.176.07:38:19.41#ibcon#read 5, iclass 24, count 2 2006.176.07:38:19.41#ibcon#about to read 6, iclass 24, count 2 2006.176.07:38:19.41#ibcon#read 6, iclass 24, count 2 2006.176.07:38:19.41#ibcon#end of sib2, iclass 24, count 2 2006.176.07:38:19.41#ibcon#*after write, iclass 24, count 2 2006.176.07:38:19.41#ibcon#*before return 0, iclass 24, count 2 2006.176.07:38:19.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:19.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:19.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.07:38:19.41#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:19.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:19.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:19.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:19.53#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:38:19.53#ibcon#first serial, iclass 24, count 0 2006.176.07:38:19.53#ibcon#enter sib2, iclass 24, count 0 2006.176.07:38:19.53#ibcon#flushed, iclass 24, count 0 2006.176.07:38:19.53#ibcon#about to write, iclass 24, count 0 2006.176.07:38:19.53#ibcon#wrote, iclass 24, count 0 2006.176.07:38:19.53#ibcon#about to read 3, iclass 24, count 0 2006.176.07:38:19.55#ibcon#read 3, iclass 24, count 0 2006.176.07:38:19.55#ibcon#about to read 4, iclass 24, count 0 2006.176.07:38:19.55#ibcon#read 4, iclass 24, count 0 2006.176.07:38:19.55#ibcon#about to read 5, iclass 24, count 0 2006.176.07:38:19.55#ibcon#read 5, iclass 24, count 0 2006.176.07:38:19.55#ibcon#about to read 6, iclass 24, count 0 2006.176.07:38:19.55#ibcon#read 6, iclass 24, count 0 2006.176.07:38:19.55#ibcon#end of sib2, iclass 24, count 0 2006.176.07:38:19.55#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:38:19.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:38:19.55#ibcon#[25=USB\r\n] 2006.176.07:38:19.55#ibcon#*before write, iclass 24, count 0 2006.176.07:38:19.55#ibcon#enter sib2, iclass 24, count 0 2006.176.07:38:19.55#ibcon#flushed, iclass 24, count 0 2006.176.07:38:19.55#ibcon#about to write, iclass 24, count 0 2006.176.07:38:19.55#ibcon#wrote, iclass 24, count 0 2006.176.07:38:19.55#ibcon#about to read 3, iclass 24, count 0 2006.176.07:38:19.58#ibcon#read 3, iclass 24, count 0 2006.176.07:38:19.58#ibcon#about to read 4, iclass 24, count 0 2006.176.07:38:19.58#ibcon#read 4, iclass 24, count 0 2006.176.07:38:19.58#ibcon#about to read 5, iclass 24, count 0 2006.176.07:38:19.58#ibcon#read 5, iclass 24, count 0 2006.176.07:38:19.58#ibcon#about to read 6, iclass 24, count 0 2006.176.07:38:19.58#ibcon#read 6, iclass 24, count 0 2006.176.07:38:19.58#ibcon#end of sib2, iclass 24, count 0 2006.176.07:38:19.58#ibcon#*after write, iclass 24, count 0 2006.176.07:38:19.58#ibcon#*before return 0, iclass 24, count 0 2006.176.07:38:19.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:19.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:19.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:38:19.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:38:19.58$vc4f8/valo=6,772.99 2006.176.07:38:19.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.07:38:19.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.07:38:19.58#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:19.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:19.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:19.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:19.58#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:38:19.58#ibcon#first serial, iclass 26, count 0 2006.176.07:38:19.58#ibcon#enter sib2, iclass 26, count 0 2006.176.07:38:19.58#ibcon#flushed, iclass 26, count 0 2006.176.07:38:19.58#ibcon#about to write, iclass 26, count 0 2006.176.07:38:19.58#ibcon#wrote, iclass 26, count 0 2006.176.07:38:19.58#ibcon#about to read 3, iclass 26, count 0 2006.176.07:38:19.60#ibcon#read 3, iclass 26, count 0 2006.176.07:38:19.60#ibcon#about to read 4, iclass 26, count 0 2006.176.07:38:19.60#ibcon#read 4, iclass 26, count 0 2006.176.07:38:19.60#ibcon#about to read 5, iclass 26, count 0 2006.176.07:38:19.60#ibcon#read 5, iclass 26, count 0 2006.176.07:38:19.60#ibcon#about to read 6, iclass 26, count 0 2006.176.07:38:19.60#ibcon#read 6, iclass 26, count 0 2006.176.07:38:19.60#ibcon#end of sib2, iclass 26, count 0 2006.176.07:38:19.60#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:38:19.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:38:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:38:19.60#ibcon#*before write, iclass 26, count 0 2006.176.07:38:19.60#ibcon#enter sib2, iclass 26, count 0 2006.176.07:38:19.60#ibcon#flushed, iclass 26, count 0 2006.176.07:38:19.60#ibcon#about to write, iclass 26, count 0 2006.176.07:38:19.60#ibcon#wrote, iclass 26, count 0 2006.176.07:38:19.60#ibcon#about to read 3, iclass 26, count 0 2006.176.07:38:19.64#ibcon#read 3, iclass 26, count 0 2006.176.07:38:19.64#ibcon#about to read 4, iclass 26, count 0 2006.176.07:38:19.64#ibcon#read 4, iclass 26, count 0 2006.176.07:38:19.64#ibcon#about to read 5, iclass 26, count 0 2006.176.07:38:19.64#ibcon#read 5, iclass 26, count 0 2006.176.07:38:19.64#ibcon#about to read 6, iclass 26, count 0 2006.176.07:38:19.64#ibcon#read 6, iclass 26, count 0 2006.176.07:38:19.64#ibcon#end of sib2, iclass 26, count 0 2006.176.07:38:19.64#ibcon#*after write, iclass 26, count 0 2006.176.07:38:19.64#ibcon#*before return 0, iclass 26, count 0 2006.176.07:38:19.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:19.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:19.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:38:19.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:38:19.64$vc4f8/va=6,6 2006.176.07:38:19.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.07:38:19.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.07:38:19.64#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:19.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:19.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:19.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:19.70#ibcon#enter wrdev, iclass 28, count 2 2006.176.07:38:19.70#ibcon#first serial, iclass 28, count 2 2006.176.07:38:19.70#ibcon#enter sib2, iclass 28, count 2 2006.176.07:38:19.70#ibcon#flushed, iclass 28, count 2 2006.176.07:38:19.70#ibcon#about to write, iclass 28, count 2 2006.176.07:38:19.70#ibcon#wrote, iclass 28, count 2 2006.176.07:38:19.70#ibcon#about to read 3, iclass 28, count 2 2006.176.07:38:19.72#ibcon#read 3, iclass 28, count 2 2006.176.07:38:19.72#ibcon#about to read 4, iclass 28, count 2 2006.176.07:38:19.72#ibcon#read 4, iclass 28, count 2 2006.176.07:38:19.72#ibcon#about to read 5, iclass 28, count 2 2006.176.07:38:19.72#ibcon#read 5, iclass 28, count 2 2006.176.07:38:19.72#ibcon#about to read 6, iclass 28, count 2 2006.176.07:38:19.72#ibcon#read 6, iclass 28, count 2 2006.176.07:38:19.72#ibcon#end of sib2, iclass 28, count 2 2006.176.07:38:19.72#ibcon#*mode == 0, iclass 28, count 2 2006.176.07:38:19.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.07:38:19.72#ibcon#[25=AT06-06\r\n] 2006.176.07:38:19.72#ibcon#*before write, iclass 28, count 2 2006.176.07:38:19.72#ibcon#enter sib2, iclass 28, count 2 2006.176.07:38:19.72#ibcon#flushed, iclass 28, count 2 2006.176.07:38:19.72#ibcon#about to write, iclass 28, count 2 2006.176.07:38:19.72#ibcon#wrote, iclass 28, count 2 2006.176.07:38:19.72#ibcon#about to read 3, iclass 28, count 2 2006.176.07:38:19.75#ibcon#read 3, iclass 28, count 2 2006.176.07:38:19.75#ibcon#about to read 4, iclass 28, count 2 2006.176.07:38:19.75#ibcon#read 4, iclass 28, count 2 2006.176.07:38:19.75#ibcon#about to read 5, iclass 28, count 2 2006.176.07:38:19.75#ibcon#read 5, iclass 28, count 2 2006.176.07:38:19.75#ibcon#about to read 6, iclass 28, count 2 2006.176.07:38:19.75#ibcon#read 6, iclass 28, count 2 2006.176.07:38:19.75#ibcon#end of sib2, iclass 28, count 2 2006.176.07:38:19.75#ibcon#*after write, iclass 28, count 2 2006.176.07:38:19.75#ibcon#*before return 0, iclass 28, count 2 2006.176.07:38:19.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:19.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:19.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.07:38:19.75#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:19.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:19.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:19.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:19.87#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:38:19.87#ibcon#first serial, iclass 28, count 0 2006.176.07:38:19.87#ibcon#enter sib2, iclass 28, count 0 2006.176.07:38:19.87#ibcon#flushed, iclass 28, count 0 2006.176.07:38:19.87#ibcon#about to write, iclass 28, count 0 2006.176.07:38:19.87#ibcon#wrote, iclass 28, count 0 2006.176.07:38:19.87#ibcon#about to read 3, iclass 28, count 0 2006.176.07:38:19.89#ibcon#read 3, iclass 28, count 0 2006.176.07:38:19.89#ibcon#about to read 4, iclass 28, count 0 2006.176.07:38:19.89#ibcon#read 4, iclass 28, count 0 2006.176.07:38:19.89#ibcon#about to read 5, iclass 28, count 0 2006.176.07:38:19.89#ibcon#read 5, iclass 28, count 0 2006.176.07:38:19.89#ibcon#about to read 6, iclass 28, count 0 2006.176.07:38:19.89#ibcon#read 6, iclass 28, count 0 2006.176.07:38:19.89#ibcon#end of sib2, iclass 28, count 0 2006.176.07:38:19.89#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:38:19.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:38:19.89#ibcon#[25=USB\r\n] 2006.176.07:38:19.89#ibcon#*before write, iclass 28, count 0 2006.176.07:38:19.89#ibcon#enter sib2, iclass 28, count 0 2006.176.07:38:19.89#ibcon#flushed, iclass 28, count 0 2006.176.07:38:19.89#ibcon#about to write, iclass 28, count 0 2006.176.07:38:19.89#ibcon#wrote, iclass 28, count 0 2006.176.07:38:19.89#ibcon#about to read 3, iclass 28, count 0 2006.176.07:38:19.92#ibcon#read 3, iclass 28, count 0 2006.176.07:38:19.92#ibcon#about to read 4, iclass 28, count 0 2006.176.07:38:19.92#ibcon#read 4, iclass 28, count 0 2006.176.07:38:19.92#ibcon#about to read 5, iclass 28, count 0 2006.176.07:38:19.92#ibcon#read 5, iclass 28, count 0 2006.176.07:38:19.92#ibcon#about to read 6, iclass 28, count 0 2006.176.07:38:19.92#ibcon#read 6, iclass 28, count 0 2006.176.07:38:19.92#ibcon#end of sib2, iclass 28, count 0 2006.176.07:38:19.92#ibcon#*after write, iclass 28, count 0 2006.176.07:38:19.92#ibcon#*before return 0, iclass 28, count 0 2006.176.07:38:19.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:19.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:19.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:38:19.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:38:19.92$vc4f8/valo=7,832.99 2006.176.07:38:19.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.07:38:19.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.07:38:19.92#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:19.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:19.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:19.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:19.92#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:38:19.92#ibcon#first serial, iclass 30, count 0 2006.176.07:38:19.92#ibcon#enter sib2, iclass 30, count 0 2006.176.07:38:19.92#ibcon#flushed, iclass 30, count 0 2006.176.07:38:19.92#ibcon#about to write, iclass 30, count 0 2006.176.07:38:19.92#ibcon#wrote, iclass 30, count 0 2006.176.07:38:19.92#ibcon#about to read 3, iclass 30, count 0 2006.176.07:38:19.94#ibcon#read 3, iclass 30, count 0 2006.176.07:38:19.94#ibcon#about to read 4, iclass 30, count 0 2006.176.07:38:19.94#ibcon#read 4, iclass 30, count 0 2006.176.07:38:19.94#ibcon#about to read 5, iclass 30, count 0 2006.176.07:38:19.94#ibcon#read 5, iclass 30, count 0 2006.176.07:38:19.94#ibcon#about to read 6, iclass 30, count 0 2006.176.07:38:19.94#ibcon#read 6, iclass 30, count 0 2006.176.07:38:19.94#ibcon#end of sib2, iclass 30, count 0 2006.176.07:38:19.94#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:38:19.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:38:19.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:38:19.94#ibcon#*before write, iclass 30, count 0 2006.176.07:38:19.94#ibcon#enter sib2, iclass 30, count 0 2006.176.07:38:19.94#ibcon#flushed, iclass 30, count 0 2006.176.07:38:19.94#ibcon#about to write, iclass 30, count 0 2006.176.07:38:19.94#ibcon#wrote, iclass 30, count 0 2006.176.07:38:19.94#ibcon#about to read 3, iclass 30, count 0 2006.176.07:38:19.98#ibcon#read 3, iclass 30, count 0 2006.176.07:38:19.98#ibcon#about to read 4, iclass 30, count 0 2006.176.07:38:19.98#ibcon#read 4, iclass 30, count 0 2006.176.07:38:19.98#ibcon#about to read 5, iclass 30, count 0 2006.176.07:38:19.98#ibcon#read 5, iclass 30, count 0 2006.176.07:38:19.98#ibcon#about to read 6, iclass 30, count 0 2006.176.07:38:19.98#ibcon#read 6, iclass 30, count 0 2006.176.07:38:19.98#ibcon#end of sib2, iclass 30, count 0 2006.176.07:38:19.98#ibcon#*after write, iclass 30, count 0 2006.176.07:38:19.98#ibcon#*before return 0, iclass 30, count 0 2006.176.07:38:19.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:19.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:19.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:38:19.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:38:19.98$vc4f8/va=7,6 2006.176.07:38:19.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.176.07:38:19.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.176.07:38:19.98#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:19.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:38:20.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:38:20.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:38:20.04#ibcon#enter wrdev, iclass 32, count 2 2006.176.07:38:20.04#ibcon#first serial, iclass 32, count 2 2006.176.07:38:20.04#ibcon#enter sib2, iclass 32, count 2 2006.176.07:38:20.04#ibcon#flushed, iclass 32, count 2 2006.176.07:38:20.04#ibcon#about to write, iclass 32, count 2 2006.176.07:38:20.04#ibcon#wrote, iclass 32, count 2 2006.176.07:38:20.04#ibcon#about to read 3, iclass 32, count 2 2006.176.07:38:20.06#ibcon#read 3, iclass 32, count 2 2006.176.07:38:20.06#ibcon#about to read 4, iclass 32, count 2 2006.176.07:38:20.06#ibcon#read 4, iclass 32, count 2 2006.176.07:38:20.06#ibcon#about to read 5, iclass 32, count 2 2006.176.07:38:20.06#ibcon#read 5, iclass 32, count 2 2006.176.07:38:20.06#ibcon#about to read 6, iclass 32, count 2 2006.176.07:38:20.06#ibcon#read 6, iclass 32, count 2 2006.176.07:38:20.06#ibcon#end of sib2, iclass 32, count 2 2006.176.07:38:20.06#ibcon#*mode == 0, iclass 32, count 2 2006.176.07:38:20.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.176.07:38:20.06#ibcon#[25=AT07-06\r\n] 2006.176.07:38:20.06#ibcon#*before write, iclass 32, count 2 2006.176.07:38:20.06#ibcon#enter sib2, iclass 32, count 2 2006.176.07:38:20.06#ibcon#flushed, iclass 32, count 2 2006.176.07:38:20.06#ibcon#about to write, iclass 32, count 2 2006.176.07:38:20.06#ibcon#wrote, iclass 32, count 2 2006.176.07:38:20.06#ibcon#about to read 3, iclass 32, count 2 2006.176.07:38:20.09#ibcon#read 3, iclass 32, count 2 2006.176.07:38:20.09#ibcon#about to read 4, iclass 32, count 2 2006.176.07:38:20.09#ibcon#read 4, iclass 32, count 2 2006.176.07:38:20.09#ibcon#about to read 5, iclass 32, count 2 2006.176.07:38:20.09#ibcon#read 5, iclass 32, count 2 2006.176.07:38:20.09#ibcon#about to read 6, iclass 32, count 2 2006.176.07:38:20.09#ibcon#read 6, iclass 32, count 2 2006.176.07:38:20.09#ibcon#end of sib2, iclass 32, count 2 2006.176.07:38:20.09#ibcon#*after write, iclass 32, count 2 2006.176.07:38:20.09#ibcon#*before return 0, iclass 32, count 2 2006.176.07:38:20.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:38:20.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:38:20.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.176.07:38:20.09#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:20.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:38:20.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:38:20.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:38:20.21#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:38:20.21#ibcon#first serial, iclass 32, count 0 2006.176.07:38:20.21#ibcon#enter sib2, iclass 32, count 0 2006.176.07:38:20.21#ibcon#flushed, iclass 32, count 0 2006.176.07:38:20.21#ibcon#about to write, iclass 32, count 0 2006.176.07:38:20.21#ibcon#wrote, iclass 32, count 0 2006.176.07:38:20.21#ibcon#about to read 3, iclass 32, count 0 2006.176.07:38:20.25#ibcon#read 3, iclass 32, count 0 2006.176.07:38:20.25#ibcon#about to read 4, iclass 32, count 0 2006.176.07:38:20.25#ibcon#read 4, iclass 32, count 0 2006.176.07:38:20.25#ibcon#about to read 5, iclass 32, count 0 2006.176.07:38:20.25#ibcon#read 5, iclass 32, count 0 2006.176.07:38:20.25#ibcon#about to read 6, iclass 32, count 0 2006.176.07:38:20.25#ibcon#read 6, iclass 32, count 0 2006.176.07:38:20.25#ibcon#end of sib2, iclass 32, count 0 2006.176.07:38:20.25#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:38:20.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:38:20.25#ibcon#[25=USB\r\n] 2006.176.07:38:20.25#ibcon#*before write, iclass 32, count 0 2006.176.07:38:20.25#ibcon#enter sib2, iclass 32, count 0 2006.176.07:38:20.25#ibcon#flushed, iclass 32, count 0 2006.176.07:38:20.25#ibcon#about to write, iclass 32, count 0 2006.176.07:38:20.25#ibcon#wrote, iclass 32, count 0 2006.176.07:38:20.25#ibcon#about to read 3, iclass 32, count 0 2006.176.07:38:20.28#ibcon#read 3, iclass 32, count 0 2006.176.07:38:20.28#ibcon#about to read 4, iclass 32, count 0 2006.176.07:38:20.28#ibcon#read 4, iclass 32, count 0 2006.176.07:38:20.28#ibcon#about to read 5, iclass 32, count 0 2006.176.07:38:20.28#ibcon#read 5, iclass 32, count 0 2006.176.07:38:20.28#ibcon#about to read 6, iclass 32, count 0 2006.176.07:38:20.28#ibcon#read 6, iclass 32, count 0 2006.176.07:38:20.28#ibcon#end of sib2, iclass 32, count 0 2006.176.07:38:20.28#ibcon#*after write, iclass 32, count 0 2006.176.07:38:20.28#ibcon#*before return 0, iclass 32, count 0 2006.176.07:38:20.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:38:20.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:38:20.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:38:20.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:38:20.28$vc4f8/valo=8,852.99 2006.176.07:38:20.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.07:38:20.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.07:38:20.28#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:20.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:38:20.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:38:20.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:38:20.28#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:38:20.28#ibcon#first serial, iclass 34, count 0 2006.176.07:38:20.28#ibcon#enter sib2, iclass 34, count 0 2006.176.07:38:20.28#ibcon#flushed, iclass 34, count 0 2006.176.07:38:20.28#ibcon#about to write, iclass 34, count 0 2006.176.07:38:20.28#ibcon#wrote, iclass 34, count 0 2006.176.07:38:20.28#ibcon#about to read 3, iclass 34, count 0 2006.176.07:38:20.30#ibcon#read 3, iclass 34, count 0 2006.176.07:38:20.30#ibcon#about to read 4, iclass 34, count 0 2006.176.07:38:20.30#ibcon#read 4, iclass 34, count 0 2006.176.07:38:20.30#ibcon#about to read 5, iclass 34, count 0 2006.176.07:38:20.30#ibcon#read 5, iclass 34, count 0 2006.176.07:38:20.30#ibcon#about to read 6, iclass 34, count 0 2006.176.07:38:20.30#ibcon#read 6, iclass 34, count 0 2006.176.07:38:20.30#ibcon#end of sib2, iclass 34, count 0 2006.176.07:38:20.30#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:38:20.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:38:20.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:38:20.30#ibcon#*before write, iclass 34, count 0 2006.176.07:38:20.30#ibcon#enter sib2, iclass 34, count 0 2006.176.07:38:20.30#ibcon#flushed, iclass 34, count 0 2006.176.07:38:20.30#ibcon#about to write, iclass 34, count 0 2006.176.07:38:20.30#ibcon#wrote, iclass 34, count 0 2006.176.07:38:20.30#ibcon#about to read 3, iclass 34, count 0 2006.176.07:38:20.34#ibcon#read 3, iclass 34, count 0 2006.176.07:38:20.34#ibcon#about to read 4, iclass 34, count 0 2006.176.07:38:20.34#ibcon#read 4, iclass 34, count 0 2006.176.07:38:20.34#ibcon#about to read 5, iclass 34, count 0 2006.176.07:38:20.34#ibcon#read 5, iclass 34, count 0 2006.176.07:38:20.34#ibcon#about to read 6, iclass 34, count 0 2006.176.07:38:20.34#ibcon#read 6, iclass 34, count 0 2006.176.07:38:20.34#ibcon#end of sib2, iclass 34, count 0 2006.176.07:38:20.34#ibcon#*after write, iclass 34, count 0 2006.176.07:38:20.34#ibcon#*before return 0, iclass 34, count 0 2006.176.07:38:20.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:38:20.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:38:20.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:38:20.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:38:20.34$vc4f8/va=8,6 2006.176.07:38:20.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.176.07:38:20.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.176.07:38:20.34#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:20.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:38:20.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:38:20.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:38:20.40#ibcon#enter wrdev, iclass 36, count 2 2006.176.07:38:20.40#ibcon#first serial, iclass 36, count 2 2006.176.07:38:20.40#ibcon#enter sib2, iclass 36, count 2 2006.176.07:38:20.40#ibcon#flushed, iclass 36, count 2 2006.176.07:38:20.40#ibcon#about to write, iclass 36, count 2 2006.176.07:38:20.40#ibcon#wrote, iclass 36, count 2 2006.176.07:38:20.40#ibcon#about to read 3, iclass 36, count 2 2006.176.07:38:20.42#ibcon#read 3, iclass 36, count 2 2006.176.07:38:20.42#ibcon#about to read 4, iclass 36, count 2 2006.176.07:38:20.42#ibcon#read 4, iclass 36, count 2 2006.176.07:38:20.42#ibcon#about to read 5, iclass 36, count 2 2006.176.07:38:20.42#ibcon#read 5, iclass 36, count 2 2006.176.07:38:20.42#ibcon#about to read 6, iclass 36, count 2 2006.176.07:38:20.42#ibcon#read 6, iclass 36, count 2 2006.176.07:38:20.42#ibcon#end of sib2, iclass 36, count 2 2006.176.07:38:20.42#ibcon#*mode == 0, iclass 36, count 2 2006.176.07:38:20.42#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.176.07:38:20.42#ibcon#[25=AT08-06\r\n] 2006.176.07:38:20.42#ibcon#*before write, iclass 36, count 2 2006.176.07:38:20.42#ibcon#enter sib2, iclass 36, count 2 2006.176.07:38:20.42#ibcon#flushed, iclass 36, count 2 2006.176.07:38:20.42#ibcon#about to write, iclass 36, count 2 2006.176.07:38:20.42#ibcon#wrote, iclass 36, count 2 2006.176.07:38:20.42#ibcon#about to read 3, iclass 36, count 2 2006.176.07:38:20.45#ibcon#read 3, iclass 36, count 2 2006.176.07:38:20.45#ibcon#about to read 4, iclass 36, count 2 2006.176.07:38:20.45#ibcon#read 4, iclass 36, count 2 2006.176.07:38:20.45#ibcon#about to read 5, iclass 36, count 2 2006.176.07:38:20.45#ibcon#read 5, iclass 36, count 2 2006.176.07:38:20.45#ibcon#about to read 6, iclass 36, count 2 2006.176.07:38:20.45#ibcon#read 6, iclass 36, count 2 2006.176.07:38:20.45#ibcon#end of sib2, iclass 36, count 2 2006.176.07:38:20.45#ibcon#*after write, iclass 36, count 2 2006.176.07:38:20.45#ibcon#*before return 0, iclass 36, count 2 2006.176.07:38:20.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:38:20.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:38:20.45#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.176.07:38:20.45#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:20.45#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:38:20.57#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:38:20.57#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:38:20.57#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:38:20.57#ibcon#first serial, iclass 36, count 0 2006.176.07:38:20.57#ibcon#enter sib2, iclass 36, count 0 2006.176.07:38:20.57#ibcon#flushed, iclass 36, count 0 2006.176.07:38:20.57#ibcon#about to write, iclass 36, count 0 2006.176.07:38:20.57#ibcon#wrote, iclass 36, count 0 2006.176.07:38:20.57#ibcon#about to read 3, iclass 36, count 0 2006.176.07:38:20.59#ibcon#read 3, iclass 36, count 0 2006.176.07:38:20.59#ibcon#about to read 4, iclass 36, count 0 2006.176.07:38:20.59#ibcon#read 4, iclass 36, count 0 2006.176.07:38:20.59#ibcon#about to read 5, iclass 36, count 0 2006.176.07:38:20.59#ibcon#read 5, iclass 36, count 0 2006.176.07:38:20.59#ibcon#about to read 6, iclass 36, count 0 2006.176.07:38:20.59#ibcon#read 6, iclass 36, count 0 2006.176.07:38:20.59#ibcon#end of sib2, iclass 36, count 0 2006.176.07:38:20.59#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:38:20.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:38:20.59#ibcon#[25=USB\r\n] 2006.176.07:38:20.59#ibcon#*before write, iclass 36, count 0 2006.176.07:38:20.59#ibcon#enter sib2, iclass 36, count 0 2006.176.07:38:20.59#ibcon#flushed, iclass 36, count 0 2006.176.07:38:20.59#ibcon#about to write, iclass 36, count 0 2006.176.07:38:20.59#ibcon#wrote, iclass 36, count 0 2006.176.07:38:20.59#ibcon#about to read 3, iclass 36, count 0 2006.176.07:38:20.62#ibcon#read 3, iclass 36, count 0 2006.176.07:38:20.62#ibcon#about to read 4, iclass 36, count 0 2006.176.07:38:20.62#ibcon#read 4, iclass 36, count 0 2006.176.07:38:20.62#ibcon#about to read 5, iclass 36, count 0 2006.176.07:38:20.62#ibcon#read 5, iclass 36, count 0 2006.176.07:38:20.62#ibcon#about to read 6, iclass 36, count 0 2006.176.07:38:20.62#ibcon#read 6, iclass 36, count 0 2006.176.07:38:20.62#ibcon#end of sib2, iclass 36, count 0 2006.176.07:38:20.62#ibcon#*after write, iclass 36, count 0 2006.176.07:38:20.62#ibcon#*before return 0, iclass 36, count 0 2006.176.07:38:20.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:38:20.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:38:20.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:38:20.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:38:20.62$vc4f8/vblo=1,632.99 2006.176.07:38:20.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.07:38:20.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.07:38:20.62#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:20.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:38:20.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:38:20.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:38:20.62#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:38:20.62#ibcon#first serial, iclass 38, count 0 2006.176.07:38:20.62#ibcon#enter sib2, iclass 38, count 0 2006.176.07:38:20.62#ibcon#flushed, iclass 38, count 0 2006.176.07:38:20.62#ibcon#about to write, iclass 38, count 0 2006.176.07:38:20.62#ibcon#wrote, iclass 38, count 0 2006.176.07:38:20.62#ibcon#about to read 3, iclass 38, count 0 2006.176.07:38:20.64#ibcon#read 3, iclass 38, count 0 2006.176.07:38:20.64#ibcon#about to read 4, iclass 38, count 0 2006.176.07:38:20.64#ibcon#read 4, iclass 38, count 0 2006.176.07:38:20.64#ibcon#about to read 5, iclass 38, count 0 2006.176.07:38:20.64#ibcon#read 5, iclass 38, count 0 2006.176.07:38:20.64#ibcon#about to read 6, iclass 38, count 0 2006.176.07:38:20.64#ibcon#read 6, iclass 38, count 0 2006.176.07:38:20.64#ibcon#end of sib2, iclass 38, count 0 2006.176.07:38:20.64#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:38:20.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:38:20.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:38:20.64#ibcon#*before write, iclass 38, count 0 2006.176.07:38:20.64#ibcon#enter sib2, iclass 38, count 0 2006.176.07:38:20.64#ibcon#flushed, iclass 38, count 0 2006.176.07:38:20.64#ibcon#about to write, iclass 38, count 0 2006.176.07:38:20.64#ibcon#wrote, iclass 38, count 0 2006.176.07:38:20.64#ibcon#about to read 3, iclass 38, count 0 2006.176.07:38:20.68#ibcon#read 3, iclass 38, count 0 2006.176.07:38:20.68#ibcon#about to read 4, iclass 38, count 0 2006.176.07:38:20.68#ibcon#read 4, iclass 38, count 0 2006.176.07:38:20.68#ibcon#about to read 5, iclass 38, count 0 2006.176.07:38:20.68#ibcon#read 5, iclass 38, count 0 2006.176.07:38:20.68#ibcon#about to read 6, iclass 38, count 0 2006.176.07:38:20.68#ibcon#read 6, iclass 38, count 0 2006.176.07:38:20.68#ibcon#end of sib2, iclass 38, count 0 2006.176.07:38:20.68#ibcon#*after write, iclass 38, count 0 2006.176.07:38:20.68#ibcon#*before return 0, iclass 38, count 0 2006.176.07:38:20.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:38:20.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:38:20.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:38:20.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:38:20.68$vc4f8/vb=1,4 2006.176.07:38:20.68#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.07:38:20.68#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.07:38:20.68#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:20.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:38:20.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:38:20.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:38:20.68#ibcon#enter wrdev, iclass 40, count 2 2006.176.07:38:20.68#ibcon#first serial, iclass 40, count 2 2006.176.07:38:20.68#ibcon#enter sib2, iclass 40, count 2 2006.176.07:38:20.68#ibcon#flushed, iclass 40, count 2 2006.176.07:38:20.68#ibcon#about to write, iclass 40, count 2 2006.176.07:38:20.68#ibcon#wrote, iclass 40, count 2 2006.176.07:38:20.68#ibcon#about to read 3, iclass 40, count 2 2006.176.07:38:20.70#ibcon#read 3, iclass 40, count 2 2006.176.07:38:20.70#ibcon#about to read 4, iclass 40, count 2 2006.176.07:38:20.70#ibcon#read 4, iclass 40, count 2 2006.176.07:38:20.70#ibcon#about to read 5, iclass 40, count 2 2006.176.07:38:20.70#ibcon#read 5, iclass 40, count 2 2006.176.07:38:20.70#ibcon#about to read 6, iclass 40, count 2 2006.176.07:38:20.70#ibcon#read 6, iclass 40, count 2 2006.176.07:38:20.70#ibcon#end of sib2, iclass 40, count 2 2006.176.07:38:20.70#ibcon#*mode == 0, iclass 40, count 2 2006.176.07:38:20.70#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.07:38:20.70#ibcon#[27=AT01-04\r\n] 2006.176.07:38:20.70#ibcon#*before write, iclass 40, count 2 2006.176.07:38:20.70#ibcon#enter sib2, iclass 40, count 2 2006.176.07:38:20.70#ibcon#flushed, iclass 40, count 2 2006.176.07:38:20.70#ibcon#about to write, iclass 40, count 2 2006.176.07:38:20.70#ibcon#wrote, iclass 40, count 2 2006.176.07:38:20.70#ibcon#about to read 3, iclass 40, count 2 2006.176.07:38:20.73#ibcon#read 3, iclass 40, count 2 2006.176.07:38:20.73#ibcon#about to read 4, iclass 40, count 2 2006.176.07:38:20.73#ibcon#read 4, iclass 40, count 2 2006.176.07:38:20.73#ibcon#about to read 5, iclass 40, count 2 2006.176.07:38:20.73#ibcon#read 5, iclass 40, count 2 2006.176.07:38:20.73#ibcon#about to read 6, iclass 40, count 2 2006.176.07:38:20.73#ibcon#read 6, iclass 40, count 2 2006.176.07:38:20.73#ibcon#end of sib2, iclass 40, count 2 2006.176.07:38:20.73#ibcon#*after write, iclass 40, count 2 2006.176.07:38:20.73#ibcon#*before return 0, iclass 40, count 2 2006.176.07:38:20.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:38:20.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:38:20.73#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.07:38:20.73#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:20.73#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:38:20.85#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:38:20.85#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:38:20.85#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:38:20.85#ibcon#first serial, iclass 40, count 0 2006.176.07:38:20.85#ibcon#enter sib2, iclass 40, count 0 2006.176.07:38:20.85#ibcon#flushed, iclass 40, count 0 2006.176.07:38:20.85#ibcon#about to write, iclass 40, count 0 2006.176.07:38:20.85#ibcon#wrote, iclass 40, count 0 2006.176.07:38:20.85#ibcon#about to read 3, iclass 40, count 0 2006.176.07:38:20.87#ibcon#read 3, iclass 40, count 0 2006.176.07:38:20.87#ibcon#about to read 4, iclass 40, count 0 2006.176.07:38:20.87#ibcon#read 4, iclass 40, count 0 2006.176.07:38:20.87#ibcon#about to read 5, iclass 40, count 0 2006.176.07:38:20.87#ibcon#read 5, iclass 40, count 0 2006.176.07:38:20.87#ibcon#about to read 6, iclass 40, count 0 2006.176.07:38:20.87#ibcon#read 6, iclass 40, count 0 2006.176.07:38:20.87#ibcon#end of sib2, iclass 40, count 0 2006.176.07:38:20.87#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:38:20.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:38:20.87#ibcon#[27=USB\r\n] 2006.176.07:38:20.87#ibcon#*before write, iclass 40, count 0 2006.176.07:38:20.87#ibcon#enter sib2, iclass 40, count 0 2006.176.07:38:20.87#ibcon#flushed, iclass 40, count 0 2006.176.07:38:20.87#ibcon#about to write, iclass 40, count 0 2006.176.07:38:20.87#ibcon#wrote, iclass 40, count 0 2006.176.07:38:20.87#ibcon#about to read 3, iclass 40, count 0 2006.176.07:38:20.90#ibcon#read 3, iclass 40, count 0 2006.176.07:38:20.90#ibcon#about to read 4, iclass 40, count 0 2006.176.07:38:20.90#ibcon#read 4, iclass 40, count 0 2006.176.07:38:20.90#ibcon#about to read 5, iclass 40, count 0 2006.176.07:38:20.90#ibcon#read 5, iclass 40, count 0 2006.176.07:38:20.90#ibcon#about to read 6, iclass 40, count 0 2006.176.07:38:20.90#ibcon#read 6, iclass 40, count 0 2006.176.07:38:20.90#ibcon#end of sib2, iclass 40, count 0 2006.176.07:38:20.90#ibcon#*after write, iclass 40, count 0 2006.176.07:38:20.90#ibcon#*before return 0, iclass 40, count 0 2006.176.07:38:20.90#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:38:20.90#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:38:20.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:38:20.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:38:20.90$vc4f8/vblo=2,640.99 2006.176.07:38:20.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.07:38:20.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.07:38:20.90#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:20.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:20.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:20.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:20.90#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:38:20.90#ibcon#first serial, iclass 4, count 0 2006.176.07:38:20.90#ibcon#enter sib2, iclass 4, count 0 2006.176.07:38:20.90#ibcon#flushed, iclass 4, count 0 2006.176.07:38:20.90#ibcon#about to write, iclass 4, count 0 2006.176.07:38:20.90#ibcon#wrote, iclass 4, count 0 2006.176.07:38:20.90#ibcon#about to read 3, iclass 4, count 0 2006.176.07:38:20.92#ibcon#read 3, iclass 4, count 0 2006.176.07:38:20.92#ibcon#about to read 4, iclass 4, count 0 2006.176.07:38:20.92#ibcon#read 4, iclass 4, count 0 2006.176.07:38:20.92#ibcon#about to read 5, iclass 4, count 0 2006.176.07:38:20.92#ibcon#read 5, iclass 4, count 0 2006.176.07:38:20.92#ibcon#about to read 6, iclass 4, count 0 2006.176.07:38:20.92#ibcon#read 6, iclass 4, count 0 2006.176.07:38:20.92#ibcon#end of sib2, iclass 4, count 0 2006.176.07:38:20.92#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:38:20.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:38:20.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:38:20.92#ibcon#*before write, iclass 4, count 0 2006.176.07:38:20.92#ibcon#enter sib2, iclass 4, count 0 2006.176.07:38:20.92#ibcon#flushed, iclass 4, count 0 2006.176.07:38:20.92#ibcon#about to write, iclass 4, count 0 2006.176.07:38:20.92#ibcon#wrote, iclass 4, count 0 2006.176.07:38:20.92#ibcon#about to read 3, iclass 4, count 0 2006.176.07:38:20.96#ibcon#read 3, iclass 4, count 0 2006.176.07:38:20.96#ibcon#about to read 4, iclass 4, count 0 2006.176.07:38:20.96#ibcon#read 4, iclass 4, count 0 2006.176.07:38:20.96#ibcon#about to read 5, iclass 4, count 0 2006.176.07:38:20.96#ibcon#read 5, iclass 4, count 0 2006.176.07:38:20.96#ibcon#about to read 6, iclass 4, count 0 2006.176.07:38:20.96#ibcon#read 6, iclass 4, count 0 2006.176.07:38:20.96#ibcon#end of sib2, iclass 4, count 0 2006.176.07:38:20.96#ibcon#*after write, iclass 4, count 0 2006.176.07:38:20.96#ibcon#*before return 0, iclass 4, count 0 2006.176.07:38:20.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:20.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:38:20.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:38:20.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:38:20.96$vc4f8/vb=2,4 2006.176.07:38:20.96#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.07:38:20.96#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.07:38:20.96#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:20.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:21.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:21.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:21.02#ibcon#enter wrdev, iclass 6, count 2 2006.176.07:38:21.02#ibcon#first serial, iclass 6, count 2 2006.176.07:38:21.02#ibcon#enter sib2, iclass 6, count 2 2006.176.07:38:21.02#ibcon#flushed, iclass 6, count 2 2006.176.07:38:21.02#ibcon#about to write, iclass 6, count 2 2006.176.07:38:21.02#ibcon#wrote, iclass 6, count 2 2006.176.07:38:21.02#ibcon#about to read 3, iclass 6, count 2 2006.176.07:38:21.04#ibcon#read 3, iclass 6, count 2 2006.176.07:38:21.04#ibcon#about to read 4, iclass 6, count 2 2006.176.07:38:21.04#ibcon#read 4, iclass 6, count 2 2006.176.07:38:21.04#ibcon#about to read 5, iclass 6, count 2 2006.176.07:38:21.04#ibcon#read 5, iclass 6, count 2 2006.176.07:38:21.04#ibcon#about to read 6, iclass 6, count 2 2006.176.07:38:21.04#ibcon#read 6, iclass 6, count 2 2006.176.07:38:21.04#ibcon#end of sib2, iclass 6, count 2 2006.176.07:38:21.04#ibcon#*mode == 0, iclass 6, count 2 2006.176.07:38:21.04#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.07:38:21.04#ibcon#[27=AT02-04\r\n] 2006.176.07:38:21.04#ibcon#*before write, iclass 6, count 2 2006.176.07:38:21.04#ibcon#enter sib2, iclass 6, count 2 2006.176.07:38:21.04#ibcon#flushed, iclass 6, count 2 2006.176.07:38:21.04#ibcon#about to write, iclass 6, count 2 2006.176.07:38:21.04#ibcon#wrote, iclass 6, count 2 2006.176.07:38:21.04#ibcon#about to read 3, iclass 6, count 2 2006.176.07:38:21.07#ibcon#read 3, iclass 6, count 2 2006.176.07:38:21.07#ibcon#about to read 4, iclass 6, count 2 2006.176.07:38:21.07#ibcon#read 4, iclass 6, count 2 2006.176.07:38:21.07#ibcon#about to read 5, iclass 6, count 2 2006.176.07:38:21.07#ibcon#read 5, iclass 6, count 2 2006.176.07:38:21.07#ibcon#about to read 6, iclass 6, count 2 2006.176.07:38:21.07#ibcon#read 6, iclass 6, count 2 2006.176.07:38:21.07#ibcon#end of sib2, iclass 6, count 2 2006.176.07:38:21.07#ibcon#*after write, iclass 6, count 2 2006.176.07:38:21.07#ibcon#*before return 0, iclass 6, count 2 2006.176.07:38:21.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:21.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:38:21.07#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.07:38:21.07#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:21.07#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:21.19#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:21.19#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:21.19#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:38:21.19#ibcon#first serial, iclass 6, count 0 2006.176.07:38:21.19#ibcon#enter sib2, iclass 6, count 0 2006.176.07:38:21.19#ibcon#flushed, iclass 6, count 0 2006.176.07:38:21.19#ibcon#about to write, iclass 6, count 0 2006.176.07:38:21.19#ibcon#wrote, iclass 6, count 0 2006.176.07:38:21.19#ibcon#about to read 3, iclass 6, count 0 2006.176.07:38:21.21#ibcon#read 3, iclass 6, count 0 2006.176.07:38:21.21#ibcon#about to read 4, iclass 6, count 0 2006.176.07:38:21.21#ibcon#read 4, iclass 6, count 0 2006.176.07:38:21.21#ibcon#about to read 5, iclass 6, count 0 2006.176.07:38:21.21#ibcon#read 5, iclass 6, count 0 2006.176.07:38:21.21#ibcon#about to read 6, iclass 6, count 0 2006.176.07:38:21.21#ibcon#read 6, iclass 6, count 0 2006.176.07:38:21.21#ibcon#end of sib2, iclass 6, count 0 2006.176.07:38:21.21#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:38:21.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:38:21.21#ibcon#[27=USB\r\n] 2006.176.07:38:21.21#ibcon#*before write, iclass 6, count 0 2006.176.07:38:21.21#ibcon#enter sib2, iclass 6, count 0 2006.176.07:38:21.21#ibcon#flushed, iclass 6, count 0 2006.176.07:38:21.21#ibcon#about to write, iclass 6, count 0 2006.176.07:38:21.21#ibcon#wrote, iclass 6, count 0 2006.176.07:38:21.21#ibcon#about to read 3, iclass 6, count 0 2006.176.07:38:21.24#ibcon#read 3, iclass 6, count 0 2006.176.07:38:21.24#ibcon#about to read 4, iclass 6, count 0 2006.176.07:38:21.24#ibcon#read 4, iclass 6, count 0 2006.176.07:38:21.24#ibcon#about to read 5, iclass 6, count 0 2006.176.07:38:21.24#ibcon#read 5, iclass 6, count 0 2006.176.07:38:21.24#ibcon#about to read 6, iclass 6, count 0 2006.176.07:38:21.24#ibcon#read 6, iclass 6, count 0 2006.176.07:38:21.24#ibcon#end of sib2, iclass 6, count 0 2006.176.07:38:21.24#ibcon#*after write, iclass 6, count 0 2006.176.07:38:21.24#ibcon#*before return 0, iclass 6, count 0 2006.176.07:38:21.24#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:21.24#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:38:21.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:38:21.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:38:21.24$vc4f8/vblo=3,656.99 2006.176.07:38:21.24#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.07:38:21.24#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.07:38:21.24#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:21.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:21.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:21.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:21.24#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:38:21.24#ibcon#first serial, iclass 10, count 0 2006.176.07:38:21.24#ibcon#enter sib2, iclass 10, count 0 2006.176.07:38:21.24#ibcon#flushed, iclass 10, count 0 2006.176.07:38:21.24#ibcon#about to write, iclass 10, count 0 2006.176.07:38:21.24#ibcon#wrote, iclass 10, count 0 2006.176.07:38:21.24#ibcon#about to read 3, iclass 10, count 0 2006.176.07:38:21.26#ibcon#read 3, iclass 10, count 0 2006.176.07:38:21.26#ibcon#about to read 4, iclass 10, count 0 2006.176.07:38:21.26#ibcon#read 4, iclass 10, count 0 2006.176.07:38:21.26#ibcon#about to read 5, iclass 10, count 0 2006.176.07:38:21.26#ibcon#read 5, iclass 10, count 0 2006.176.07:38:21.26#ibcon#about to read 6, iclass 10, count 0 2006.176.07:38:21.26#ibcon#read 6, iclass 10, count 0 2006.176.07:38:21.26#ibcon#end of sib2, iclass 10, count 0 2006.176.07:38:21.26#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:38:21.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:38:21.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:38:21.26#ibcon#*before write, iclass 10, count 0 2006.176.07:38:21.26#ibcon#enter sib2, iclass 10, count 0 2006.176.07:38:21.26#ibcon#flushed, iclass 10, count 0 2006.176.07:38:21.26#ibcon#about to write, iclass 10, count 0 2006.176.07:38:21.26#ibcon#wrote, iclass 10, count 0 2006.176.07:38:21.26#ibcon#about to read 3, iclass 10, count 0 2006.176.07:38:21.30#ibcon#read 3, iclass 10, count 0 2006.176.07:38:21.30#ibcon#about to read 4, iclass 10, count 0 2006.176.07:38:21.30#ibcon#read 4, iclass 10, count 0 2006.176.07:38:21.30#ibcon#about to read 5, iclass 10, count 0 2006.176.07:38:21.30#ibcon#read 5, iclass 10, count 0 2006.176.07:38:21.30#ibcon#about to read 6, iclass 10, count 0 2006.176.07:38:21.30#ibcon#read 6, iclass 10, count 0 2006.176.07:38:21.30#ibcon#end of sib2, iclass 10, count 0 2006.176.07:38:21.30#ibcon#*after write, iclass 10, count 0 2006.176.07:38:21.30#ibcon#*before return 0, iclass 10, count 0 2006.176.07:38:21.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:21.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:38:21.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:38:21.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:38:21.30$vc4f8/vb=3,4 2006.176.07:38:21.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.07:38:21.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.07:38:21.30#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:21.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:21.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:21.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:21.36#ibcon#enter wrdev, iclass 12, count 2 2006.176.07:38:21.36#ibcon#first serial, iclass 12, count 2 2006.176.07:38:21.36#ibcon#enter sib2, iclass 12, count 2 2006.176.07:38:21.36#ibcon#flushed, iclass 12, count 2 2006.176.07:38:21.36#ibcon#about to write, iclass 12, count 2 2006.176.07:38:21.36#ibcon#wrote, iclass 12, count 2 2006.176.07:38:21.36#ibcon#about to read 3, iclass 12, count 2 2006.176.07:38:21.38#ibcon#read 3, iclass 12, count 2 2006.176.07:38:21.38#ibcon#about to read 4, iclass 12, count 2 2006.176.07:38:21.38#ibcon#read 4, iclass 12, count 2 2006.176.07:38:21.38#ibcon#about to read 5, iclass 12, count 2 2006.176.07:38:21.38#ibcon#read 5, iclass 12, count 2 2006.176.07:38:21.38#ibcon#about to read 6, iclass 12, count 2 2006.176.07:38:21.38#ibcon#read 6, iclass 12, count 2 2006.176.07:38:21.38#ibcon#end of sib2, iclass 12, count 2 2006.176.07:38:21.38#ibcon#*mode == 0, iclass 12, count 2 2006.176.07:38:21.38#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.07:38:21.38#ibcon#[27=AT03-04\r\n] 2006.176.07:38:21.38#ibcon#*before write, iclass 12, count 2 2006.176.07:38:21.38#ibcon#enter sib2, iclass 12, count 2 2006.176.07:38:21.38#ibcon#flushed, iclass 12, count 2 2006.176.07:38:21.38#ibcon#about to write, iclass 12, count 2 2006.176.07:38:21.38#ibcon#wrote, iclass 12, count 2 2006.176.07:38:21.38#ibcon#about to read 3, iclass 12, count 2 2006.176.07:38:21.41#ibcon#read 3, iclass 12, count 2 2006.176.07:38:21.41#ibcon#about to read 4, iclass 12, count 2 2006.176.07:38:21.41#ibcon#read 4, iclass 12, count 2 2006.176.07:38:21.41#ibcon#about to read 5, iclass 12, count 2 2006.176.07:38:21.41#ibcon#read 5, iclass 12, count 2 2006.176.07:38:21.41#ibcon#about to read 6, iclass 12, count 2 2006.176.07:38:21.41#ibcon#read 6, iclass 12, count 2 2006.176.07:38:21.41#ibcon#end of sib2, iclass 12, count 2 2006.176.07:38:21.41#ibcon#*after write, iclass 12, count 2 2006.176.07:38:21.41#ibcon#*before return 0, iclass 12, count 2 2006.176.07:38:21.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:21.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:38:21.41#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.07:38:21.41#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:21.41#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:21.53#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:21.53#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:21.53#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:38:21.53#ibcon#first serial, iclass 12, count 0 2006.176.07:38:21.53#ibcon#enter sib2, iclass 12, count 0 2006.176.07:38:21.53#ibcon#flushed, iclass 12, count 0 2006.176.07:38:21.53#ibcon#about to write, iclass 12, count 0 2006.176.07:38:21.53#ibcon#wrote, iclass 12, count 0 2006.176.07:38:21.53#ibcon#about to read 3, iclass 12, count 0 2006.176.07:38:21.55#ibcon#read 3, iclass 12, count 0 2006.176.07:38:21.55#ibcon#about to read 4, iclass 12, count 0 2006.176.07:38:21.55#ibcon#read 4, iclass 12, count 0 2006.176.07:38:21.55#ibcon#about to read 5, iclass 12, count 0 2006.176.07:38:21.55#ibcon#read 5, iclass 12, count 0 2006.176.07:38:21.55#ibcon#about to read 6, iclass 12, count 0 2006.176.07:38:21.55#ibcon#read 6, iclass 12, count 0 2006.176.07:38:21.55#ibcon#end of sib2, iclass 12, count 0 2006.176.07:38:21.55#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:38:21.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:38:21.55#ibcon#[27=USB\r\n] 2006.176.07:38:21.55#ibcon#*before write, iclass 12, count 0 2006.176.07:38:21.55#ibcon#enter sib2, iclass 12, count 0 2006.176.07:38:21.55#ibcon#flushed, iclass 12, count 0 2006.176.07:38:21.55#ibcon#about to write, iclass 12, count 0 2006.176.07:38:21.55#ibcon#wrote, iclass 12, count 0 2006.176.07:38:21.55#ibcon#about to read 3, iclass 12, count 0 2006.176.07:38:21.58#ibcon#read 3, iclass 12, count 0 2006.176.07:38:21.58#ibcon#about to read 4, iclass 12, count 0 2006.176.07:38:21.58#ibcon#read 4, iclass 12, count 0 2006.176.07:38:21.58#ibcon#about to read 5, iclass 12, count 0 2006.176.07:38:21.58#ibcon#read 5, iclass 12, count 0 2006.176.07:38:21.58#ibcon#about to read 6, iclass 12, count 0 2006.176.07:38:21.58#ibcon#read 6, iclass 12, count 0 2006.176.07:38:21.58#ibcon#end of sib2, iclass 12, count 0 2006.176.07:38:21.58#ibcon#*after write, iclass 12, count 0 2006.176.07:38:21.58#ibcon#*before return 0, iclass 12, count 0 2006.176.07:38:21.58#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:21.58#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:38:21.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:38:21.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:38:21.58$vc4f8/vblo=4,712.99 2006.176.07:38:21.58#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.07:38:21.58#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.07:38:21.58#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:21.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:21.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:21.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:21.58#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:38:21.58#ibcon#first serial, iclass 14, count 0 2006.176.07:38:21.58#ibcon#enter sib2, iclass 14, count 0 2006.176.07:38:21.58#ibcon#flushed, iclass 14, count 0 2006.176.07:38:21.58#ibcon#about to write, iclass 14, count 0 2006.176.07:38:21.58#ibcon#wrote, iclass 14, count 0 2006.176.07:38:21.58#ibcon#about to read 3, iclass 14, count 0 2006.176.07:38:21.60#ibcon#read 3, iclass 14, count 0 2006.176.07:38:21.60#ibcon#about to read 4, iclass 14, count 0 2006.176.07:38:21.60#ibcon#read 4, iclass 14, count 0 2006.176.07:38:21.60#ibcon#about to read 5, iclass 14, count 0 2006.176.07:38:21.60#ibcon#read 5, iclass 14, count 0 2006.176.07:38:21.60#ibcon#about to read 6, iclass 14, count 0 2006.176.07:38:21.60#ibcon#read 6, iclass 14, count 0 2006.176.07:38:21.60#ibcon#end of sib2, iclass 14, count 0 2006.176.07:38:21.60#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:38:21.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:38:21.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:38:21.60#ibcon#*before write, iclass 14, count 0 2006.176.07:38:21.60#ibcon#enter sib2, iclass 14, count 0 2006.176.07:38:21.60#ibcon#flushed, iclass 14, count 0 2006.176.07:38:21.60#ibcon#about to write, iclass 14, count 0 2006.176.07:38:21.60#ibcon#wrote, iclass 14, count 0 2006.176.07:38:21.60#ibcon#about to read 3, iclass 14, count 0 2006.176.07:38:21.64#ibcon#read 3, iclass 14, count 0 2006.176.07:38:21.64#ibcon#about to read 4, iclass 14, count 0 2006.176.07:38:21.64#ibcon#read 4, iclass 14, count 0 2006.176.07:38:21.64#ibcon#about to read 5, iclass 14, count 0 2006.176.07:38:21.64#ibcon#read 5, iclass 14, count 0 2006.176.07:38:21.64#ibcon#about to read 6, iclass 14, count 0 2006.176.07:38:21.64#ibcon#read 6, iclass 14, count 0 2006.176.07:38:21.64#ibcon#end of sib2, iclass 14, count 0 2006.176.07:38:21.64#ibcon#*after write, iclass 14, count 0 2006.176.07:38:21.64#ibcon#*before return 0, iclass 14, count 0 2006.176.07:38:21.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:21.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:38:21.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:38:21.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:38:21.64$vc4f8/vb=4,4 2006.176.07:38:21.64#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.07:38:21.64#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.07:38:21.64#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:21.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:21.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:21.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:21.70#ibcon#enter wrdev, iclass 16, count 2 2006.176.07:38:21.70#ibcon#first serial, iclass 16, count 2 2006.176.07:38:21.70#ibcon#enter sib2, iclass 16, count 2 2006.176.07:38:21.70#ibcon#flushed, iclass 16, count 2 2006.176.07:38:21.70#ibcon#about to write, iclass 16, count 2 2006.176.07:38:21.70#ibcon#wrote, iclass 16, count 2 2006.176.07:38:21.70#ibcon#about to read 3, iclass 16, count 2 2006.176.07:38:21.71#abcon#<5=/04 3.2 5.8 23.94 911008.4\r\n> 2006.176.07:38:21.72#ibcon#read 3, iclass 16, count 2 2006.176.07:38:21.72#ibcon#about to read 4, iclass 16, count 2 2006.176.07:38:21.72#ibcon#read 4, iclass 16, count 2 2006.176.07:38:21.72#ibcon#about to read 5, iclass 16, count 2 2006.176.07:38:21.72#ibcon#read 5, iclass 16, count 2 2006.176.07:38:21.72#ibcon#about to read 6, iclass 16, count 2 2006.176.07:38:21.72#ibcon#read 6, iclass 16, count 2 2006.176.07:38:21.72#ibcon#end of sib2, iclass 16, count 2 2006.176.07:38:21.72#ibcon#*mode == 0, iclass 16, count 2 2006.176.07:38:21.72#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.07:38:21.72#ibcon#[27=AT04-04\r\n] 2006.176.07:38:21.72#ibcon#*before write, iclass 16, count 2 2006.176.07:38:21.72#ibcon#enter sib2, iclass 16, count 2 2006.176.07:38:21.72#ibcon#flushed, iclass 16, count 2 2006.176.07:38:21.72#ibcon#about to write, iclass 16, count 2 2006.176.07:38:21.72#ibcon#wrote, iclass 16, count 2 2006.176.07:38:21.72#ibcon#about to read 3, iclass 16, count 2 2006.176.07:38:21.73#abcon#{5=INTERFACE CLEAR} 2006.176.07:38:21.75#ibcon#read 3, iclass 16, count 2 2006.176.07:38:21.75#ibcon#about to read 4, iclass 16, count 2 2006.176.07:38:21.75#ibcon#read 4, iclass 16, count 2 2006.176.07:38:21.75#ibcon#about to read 5, iclass 16, count 2 2006.176.07:38:21.75#ibcon#read 5, iclass 16, count 2 2006.176.07:38:21.75#ibcon#about to read 6, iclass 16, count 2 2006.176.07:38:21.75#ibcon#read 6, iclass 16, count 2 2006.176.07:38:21.75#ibcon#end of sib2, iclass 16, count 2 2006.176.07:38:21.75#ibcon#*after write, iclass 16, count 2 2006.176.07:38:21.75#ibcon#*before return 0, iclass 16, count 2 2006.176.07:38:21.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:21.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:38:21.75#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.07:38:21.75#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:21.75#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:21.79#abcon#[5=S1D000X0/0*\r\n] 2006.176.07:38:21.87#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:21.87#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:21.87#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:38:21.87#ibcon#first serial, iclass 16, count 0 2006.176.07:38:21.87#ibcon#enter sib2, iclass 16, count 0 2006.176.07:38:21.87#ibcon#flushed, iclass 16, count 0 2006.176.07:38:21.87#ibcon#about to write, iclass 16, count 0 2006.176.07:38:21.87#ibcon#wrote, iclass 16, count 0 2006.176.07:38:21.87#ibcon#about to read 3, iclass 16, count 0 2006.176.07:38:21.89#ibcon#read 3, iclass 16, count 0 2006.176.07:38:21.89#ibcon#about to read 4, iclass 16, count 0 2006.176.07:38:21.89#ibcon#read 4, iclass 16, count 0 2006.176.07:38:21.89#ibcon#about to read 5, iclass 16, count 0 2006.176.07:38:21.89#ibcon#read 5, iclass 16, count 0 2006.176.07:38:21.89#ibcon#about to read 6, iclass 16, count 0 2006.176.07:38:21.89#ibcon#read 6, iclass 16, count 0 2006.176.07:38:21.89#ibcon#end of sib2, iclass 16, count 0 2006.176.07:38:21.89#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:38:21.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:38:21.89#ibcon#[27=USB\r\n] 2006.176.07:38:21.89#ibcon#*before write, iclass 16, count 0 2006.176.07:38:21.89#ibcon#enter sib2, iclass 16, count 0 2006.176.07:38:21.89#ibcon#flushed, iclass 16, count 0 2006.176.07:38:21.89#ibcon#about to write, iclass 16, count 0 2006.176.07:38:21.89#ibcon#wrote, iclass 16, count 0 2006.176.07:38:21.89#ibcon#about to read 3, iclass 16, count 0 2006.176.07:38:21.92#ibcon#read 3, iclass 16, count 0 2006.176.07:38:21.92#ibcon#about to read 4, iclass 16, count 0 2006.176.07:38:21.92#ibcon#read 4, iclass 16, count 0 2006.176.07:38:21.92#ibcon#about to read 5, iclass 16, count 0 2006.176.07:38:21.92#ibcon#read 5, iclass 16, count 0 2006.176.07:38:21.92#ibcon#about to read 6, iclass 16, count 0 2006.176.07:38:21.92#ibcon#read 6, iclass 16, count 0 2006.176.07:38:21.92#ibcon#end of sib2, iclass 16, count 0 2006.176.07:38:21.92#ibcon#*after write, iclass 16, count 0 2006.176.07:38:21.92#ibcon#*before return 0, iclass 16, count 0 2006.176.07:38:21.92#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:21.92#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:38:21.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:38:21.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:38:21.92$vc4f8/vblo=5,744.99 2006.176.07:38:21.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.07:38:21.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.07:38:21.92#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:21.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:21.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:21.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:21.92#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:38:21.92#ibcon#first serial, iclass 22, count 0 2006.176.07:38:21.92#ibcon#enter sib2, iclass 22, count 0 2006.176.07:38:21.92#ibcon#flushed, iclass 22, count 0 2006.176.07:38:21.92#ibcon#about to write, iclass 22, count 0 2006.176.07:38:21.92#ibcon#wrote, iclass 22, count 0 2006.176.07:38:21.92#ibcon#about to read 3, iclass 22, count 0 2006.176.07:38:21.94#ibcon#read 3, iclass 22, count 0 2006.176.07:38:21.94#ibcon#about to read 4, iclass 22, count 0 2006.176.07:38:21.94#ibcon#read 4, iclass 22, count 0 2006.176.07:38:21.94#ibcon#about to read 5, iclass 22, count 0 2006.176.07:38:21.94#ibcon#read 5, iclass 22, count 0 2006.176.07:38:21.94#ibcon#about to read 6, iclass 22, count 0 2006.176.07:38:21.94#ibcon#read 6, iclass 22, count 0 2006.176.07:38:21.94#ibcon#end of sib2, iclass 22, count 0 2006.176.07:38:21.94#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:38:21.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:38:21.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:38:21.94#ibcon#*before write, iclass 22, count 0 2006.176.07:38:21.94#ibcon#enter sib2, iclass 22, count 0 2006.176.07:38:21.94#ibcon#flushed, iclass 22, count 0 2006.176.07:38:21.94#ibcon#about to write, iclass 22, count 0 2006.176.07:38:21.94#ibcon#wrote, iclass 22, count 0 2006.176.07:38:21.94#ibcon#about to read 3, iclass 22, count 0 2006.176.07:38:21.98#ibcon#read 3, iclass 22, count 0 2006.176.07:38:21.98#ibcon#about to read 4, iclass 22, count 0 2006.176.07:38:21.98#ibcon#read 4, iclass 22, count 0 2006.176.07:38:21.98#ibcon#about to read 5, iclass 22, count 0 2006.176.07:38:21.98#ibcon#read 5, iclass 22, count 0 2006.176.07:38:21.98#ibcon#about to read 6, iclass 22, count 0 2006.176.07:38:21.98#ibcon#read 6, iclass 22, count 0 2006.176.07:38:21.98#ibcon#end of sib2, iclass 22, count 0 2006.176.07:38:21.98#ibcon#*after write, iclass 22, count 0 2006.176.07:38:21.98#ibcon#*before return 0, iclass 22, count 0 2006.176.07:38:21.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:21.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:38:21.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:38:21.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:38:21.98$vc4f8/vb=5,4 2006.176.07:38:21.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.07:38:21.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.07:38:21.98#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:21.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:22.04#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:22.04#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:22.04#ibcon#enter wrdev, iclass 24, count 2 2006.176.07:38:22.04#ibcon#first serial, iclass 24, count 2 2006.176.07:38:22.04#ibcon#enter sib2, iclass 24, count 2 2006.176.07:38:22.04#ibcon#flushed, iclass 24, count 2 2006.176.07:38:22.04#ibcon#about to write, iclass 24, count 2 2006.176.07:38:22.04#ibcon#wrote, iclass 24, count 2 2006.176.07:38:22.04#ibcon#about to read 3, iclass 24, count 2 2006.176.07:38:22.06#ibcon#read 3, iclass 24, count 2 2006.176.07:38:22.06#ibcon#about to read 4, iclass 24, count 2 2006.176.07:38:22.06#ibcon#read 4, iclass 24, count 2 2006.176.07:38:22.06#ibcon#about to read 5, iclass 24, count 2 2006.176.07:38:22.06#ibcon#read 5, iclass 24, count 2 2006.176.07:38:22.06#ibcon#about to read 6, iclass 24, count 2 2006.176.07:38:22.06#ibcon#read 6, iclass 24, count 2 2006.176.07:38:22.06#ibcon#end of sib2, iclass 24, count 2 2006.176.07:38:22.06#ibcon#*mode == 0, iclass 24, count 2 2006.176.07:38:22.06#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.07:38:22.06#ibcon#[27=AT05-04\r\n] 2006.176.07:38:22.06#ibcon#*before write, iclass 24, count 2 2006.176.07:38:22.06#ibcon#enter sib2, iclass 24, count 2 2006.176.07:38:22.06#ibcon#flushed, iclass 24, count 2 2006.176.07:38:22.06#ibcon#about to write, iclass 24, count 2 2006.176.07:38:22.06#ibcon#wrote, iclass 24, count 2 2006.176.07:38:22.06#ibcon#about to read 3, iclass 24, count 2 2006.176.07:38:22.09#ibcon#read 3, iclass 24, count 2 2006.176.07:38:22.09#ibcon#about to read 4, iclass 24, count 2 2006.176.07:38:22.09#ibcon#read 4, iclass 24, count 2 2006.176.07:38:22.09#ibcon#about to read 5, iclass 24, count 2 2006.176.07:38:22.09#ibcon#read 5, iclass 24, count 2 2006.176.07:38:22.09#ibcon#about to read 6, iclass 24, count 2 2006.176.07:38:22.09#ibcon#read 6, iclass 24, count 2 2006.176.07:38:22.09#ibcon#end of sib2, iclass 24, count 2 2006.176.07:38:22.09#ibcon#*after write, iclass 24, count 2 2006.176.07:38:22.09#ibcon#*before return 0, iclass 24, count 2 2006.176.07:38:22.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:22.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:38:22.09#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.07:38:22.09#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:22.09#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:22.21#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:22.21#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:22.21#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:38:22.21#ibcon#first serial, iclass 24, count 0 2006.176.07:38:22.21#ibcon#enter sib2, iclass 24, count 0 2006.176.07:38:22.21#ibcon#flushed, iclass 24, count 0 2006.176.07:38:22.21#ibcon#about to write, iclass 24, count 0 2006.176.07:38:22.21#ibcon#wrote, iclass 24, count 0 2006.176.07:38:22.21#ibcon#about to read 3, iclass 24, count 0 2006.176.07:38:22.23#ibcon#read 3, iclass 24, count 0 2006.176.07:38:22.23#ibcon#about to read 4, iclass 24, count 0 2006.176.07:38:22.23#ibcon#read 4, iclass 24, count 0 2006.176.07:38:22.23#ibcon#about to read 5, iclass 24, count 0 2006.176.07:38:22.23#ibcon#read 5, iclass 24, count 0 2006.176.07:38:22.23#ibcon#about to read 6, iclass 24, count 0 2006.176.07:38:22.23#ibcon#read 6, iclass 24, count 0 2006.176.07:38:22.23#ibcon#end of sib2, iclass 24, count 0 2006.176.07:38:22.23#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:38:22.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:38:22.23#ibcon#[27=USB\r\n] 2006.176.07:38:22.23#ibcon#*before write, iclass 24, count 0 2006.176.07:38:22.23#ibcon#enter sib2, iclass 24, count 0 2006.176.07:38:22.23#ibcon#flushed, iclass 24, count 0 2006.176.07:38:22.23#ibcon#about to write, iclass 24, count 0 2006.176.07:38:22.23#ibcon#wrote, iclass 24, count 0 2006.176.07:38:22.23#ibcon#about to read 3, iclass 24, count 0 2006.176.07:38:22.26#ibcon#read 3, iclass 24, count 0 2006.176.07:38:22.26#ibcon#about to read 4, iclass 24, count 0 2006.176.07:38:22.26#ibcon#read 4, iclass 24, count 0 2006.176.07:38:22.26#ibcon#about to read 5, iclass 24, count 0 2006.176.07:38:22.26#ibcon#read 5, iclass 24, count 0 2006.176.07:38:22.26#ibcon#about to read 6, iclass 24, count 0 2006.176.07:38:22.26#ibcon#read 6, iclass 24, count 0 2006.176.07:38:22.26#ibcon#end of sib2, iclass 24, count 0 2006.176.07:38:22.26#ibcon#*after write, iclass 24, count 0 2006.176.07:38:22.26#ibcon#*before return 0, iclass 24, count 0 2006.176.07:38:22.26#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:22.26#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:38:22.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:38:22.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:38:22.26$vc4f8/vblo=6,752.99 2006.176.07:38:22.26#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.07:38:22.26#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.07:38:22.26#ibcon#ireg 17 cls_cnt 0 2006.176.07:38:22.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:22.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:22.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:22.26#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:38:22.26#ibcon#first serial, iclass 26, count 0 2006.176.07:38:22.26#ibcon#enter sib2, iclass 26, count 0 2006.176.07:38:22.26#ibcon#flushed, iclass 26, count 0 2006.176.07:38:22.26#ibcon#about to write, iclass 26, count 0 2006.176.07:38:22.26#ibcon#wrote, iclass 26, count 0 2006.176.07:38:22.26#ibcon#about to read 3, iclass 26, count 0 2006.176.07:38:22.28#ibcon#read 3, iclass 26, count 0 2006.176.07:38:22.28#ibcon#about to read 4, iclass 26, count 0 2006.176.07:38:22.28#ibcon#read 4, iclass 26, count 0 2006.176.07:38:22.28#ibcon#about to read 5, iclass 26, count 0 2006.176.07:38:22.28#ibcon#read 5, iclass 26, count 0 2006.176.07:38:22.28#ibcon#about to read 6, iclass 26, count 0 2006.176.07:38:22.28#ibcon#read 6, iclass 26, count 0 2006.176.07:38:22.28#ibcon#end of sib2, iclass 26, count 0 2006.176.07:38:22.28#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:38:22.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:38:22.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:38:22.28#ibcon#*before write, iclass 26, count 0 2006.176.07:38:22.28#ibcon#enter sib2, iclass 26, count 0 2006.176.07:38:22.28#ibcon#flushed, iclass 26, count 0 2006.176.07:38:22.28#ibcon#about to write, iclass 26, count 0 2006.176.07:38:22.28#ibcon#wrote, iclass 26, count 0 2006.176.07:38:22.28#ibcon#about to read 3, iclass 26, count 0 2006.176.07:38:22.32#ibcon#read 3, iclass 26, count 0 2006.176.07:38:22.32#ibcon#about to read 4, iclass 26, count 0 2006.176.07:38:22.32#ibcon#read 4, iclass 26, count 0 2006.176.07:38:22.32#ibcon#about to read 5, iclass 26, count 0 2006.176.07:38:22.32#ibcon#read 5, iclass 26, count 0 2006.176.07:38:22.32#ibcon#about to read 6, iclass 26, count 0 2006.176.07:38:22.32#ibcon#read 6, iclass 26, count 0 2006.176.07:38:22.32#ibcon#end of sib2, iclass 26, count 0 2006.176.07:38:22.32#ibcon#*after write, iclass 26, count 0 2006.176.07:38:22.32#ibcon#*before return 0, iclass 26, count 0 2006.176.07:38:22.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:22.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:38:22.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:38:22.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:38:22.32$vc4f8/vb=6,4 2006.176.07:38:22.32#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.07:38:22.32#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.07:38:22.32#ibcon#ireg 11 cls_cnt 2 2006.176.07:38:22.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:22.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:22.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:22.38#ibcon#enter wrdev, iclass 28, count 2 2006.176.07:38:22.38#ibcon#first serial, iclass 28, count 2 2006.176.07:38:22.38#ibcon#enter sib2, iclass 28, count 2 2006.176.07:38:22.38#ibcon#flushed, iclass 28, count 2 2006.176.07:38:22.38#ibcon#about to write, iclass 28, count 2 2006.176.07:38:22.38#ibcon#wrote, iclass 28, count 2 2006.176.07:38:22.38#ibcon#about to read 3, iclass 28, count 2 2006.176.07:38:22.40#ibcon#read 3, iclass 28, count 2 2006.176.07:38:22.40#ibcon#about to read 4, iclass 28, count 2 2006.176.07:38:22.40#ibcon#read 4, iclass 28, count 2 2006.176.07:38:22.40#ibcon#about to read 5, iclass 28, count 2 2006.176.07:38:22.40#ibcon#read 5, iclass 28, count 2 2006.176.07:38:22.40#ibcon#about to read 6, iclass 28, count 2 2006.176.07:38:22.40#ibcon#read 6, iclass 28, count 2 2006.176.07:38:22.40#ibcon#end of sib2, iclass 28, count 2 2006.176.07:38:22.40#ibcon#*mode == 0, iclass 28, count 2 2006.176.07:38:22.40#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.07:38:22.40#ibcon#[27=AT06-04\r\n] 2006.176.07:38:22.40#ibcon#*before write, iclass 28, count 2 2006.176.07:38:22.40#ibcon#enter sib2, iclass 28, count 2 2006.176.07:38:22.40#ibcon#flushed, iclass 28, count 2 2006.176.07:38:22.40#ibcon#about to write, iclass 28, count 2 2006.176.07:38:22.40#ibcon#wrote, iclass 28, count 2 2006.176.07:38:22.40#ibcon#about to read 3, iclass 28, count 2 2006.176.07:38:22.43#ibcon#read 3, iclass 28, count 2 2006.176.07:38:22.43#ibcon#about to read 4, iclass 28, count 2 2006.176.07:38:22.43#ibcon#read 4, iclass 28, count 2 2006.176.07:38:22.43#ibcon#about to read 5, iclass 28, count 2 2006.176.07:38:22.43#ibcon#read 5, iclass 28, count 2 2006.176.07:38:22.43#ibcon#about to read 6, iclass 28, count 2 2006.176.07:38:22.43#ibcon#read 6, iclass 28, count 2 2006.176.07:38:22.43#ibcon#end of sib2, iclass 28, count 2 2006.176.07:38:22.43#ibcon#*after write, iclass 28, count 2 2006.176.07:38:22.43#ibcon#*before return 0, iclass 28, count 2 2006.176.07:38:22.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:22.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:38:22.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.07:38:22.43#ibcon#ireg 7 cls_cnt 0 2006.176.07:38:22.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:22.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:22.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:22.55#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:38:22.55#ibcon#first serial, iclass 28, count 0 2006.176.07:38:22.55#ibcon#enter sib2, iclass 28, count 0 2006.176.07:38:22.55#ibcon#flushed, iclass 28, count 0 2006.176.07:38:22.55#ibcon#about to write, iclass 28, count 0 2006.176.07:38:22.55#ibcon#wrote, iclass 28, count 0 2006.176.07:38:22.55#ibcon#about to read 3, iclass 28, count 0 2006.176.07:38:22.57#ibcon#read 3, iclass 28, count 0 2006.176.07:38:22.57#ibcon#about to read 4, iclass 28, count 0 2006.176.07:38:22.57#ibcon#read 4, iclass 28, count 0 2006.176.07:38:22.57#ibcon#about to read 5, iclass 28, count 0 2006.176.07:38:22.57#ibcon#read 5, iclass 28, count 0 2006.176.07:38:22.57#ibcon#about to read 6, iclass 28, count 0 2006.176.07:38:22.57#ibcon#read 6, iclass 28, count 0 2006.176.07:38:22.57#ibcon#end of sib2, iclass 28, count 0 2006.176.07:38:22.57#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:38:22.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:38:22.57#ibcon#[27=USB\r\n] 2006.176.07:38:22.57#ibcon#*before write, iclass 28, count 0 2006.176.07:38:22.57#ibcon#enter sib2, iclass 28, count 0 2006.176.07:38:22.57#ibcon#flushed, iclass 28, count 0 2006.176.07:38:22.57#ibcon#about to write, iclass 28, count 0 2006.176.07:38:22.57#ibcon#wrote, iclass 28, count 0 2006.176.07:38:22.57#ibcon#about to read 3, iclass 28, count 0 2006.176.07:38:22.60#ibcon#read 3, iclass 28, count 0 2006.176.07:38:22.60#ibcon#about to read 4, iclass 28, count 0 2006.176.07:38:22.60#ibcon#read 4, iclass 28, count 0 2006.176.07:38:22.60#ibcon#about to read 5, iclass 28, count 0 2006.176.07:38:22.60#ibcon#read 5, iclass 28, count 0 2006.176.07:38:22.60#ibcon#about to read 6, iclass 28, count 0 2006.176.07:38:22.60#ibcon#read 6, iclass 28, count 0 2006.176.07:38:22.60#ibcon#end of sib2, iclass 28, count 0 2006.176.07:38:22.60#ibcon#*after write, iclass 28, count 0 2006.176.07:38:22.60#ibcon#*before return 0, iclass 28, count 0 2006.176.07:38:22.60#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:22.60#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:38:22.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:38:22.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:38:22.60$vc4f8/vabw=wide 2006.176.07:38:22.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.07:38:22.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.07:38:22.60#ibcon#ireg 8 cls_cnt 0 2006.176.07:38:22.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:22.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:22.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:22.60#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:38:22.60#ibcon#first serial, iclass 30, count 0 2006.176.07:38:22.60#ibcon#enter sib2, iclass 30, count 0 2006.176.07:38:22.60#ibcon#flushed, iclass 30, count 0 2006.176.07:38:22.60#ibcon#about to write, iclass 30, count 0 2006.176.07:38:22.60#ibcon#wrote, iclass 30, count 0 2006.176.07:38:22.60#ibcon#about to read 3, iclass 30, count 0 2006.176.07:38:22.62#ibcon#read 3, iclass 30, count 0 2006.176.07:38:22.62#ibcon#about to read 4, iclass 30, count 0 2006.176.07:38:22.62#ibcon#read 4, iclass 30, count 0 2006.176.07:38:22.62#ibcon#about to read 5, iclass 30, count 0 2006.176.07:38:22.62#ibcon#read 5, iclass 30, count 0 2006.176.07:38:22.62#ibcon#about to read 6, iclass 30, count 0 2006.176.07:38:22.62#ibcon#read 6, iclass 30, count 0 2006.176.07:38:22.62#ibcon#end of sib2, iclass 30, count 0 2006.176.07:38:22.62#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:38:22.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:38:22.62#ibcon#[25=BW32\r\n] 2006.176.07:38:22.62#ibcon#*before write, iclass 30, count 0 2006.176.07:38:22.62#ibcon#enter sib2, iclass 30, count 0 2006.176.07:38:22.62#ibcon#flushed, iclass 30, count 0 2006.176.07:38:22.62#ibcon#about to write, iclass 30, count 0 2006.176.07:38:22.62#ibcon#wrote, iclass 30, count 0 2006.176.07:38:22.62#ibcon#about to read 3, iclass 30, count 0 2006.176.07:38:22.65#ibcon#read 3, iclass 30, count 0 2006.176.07:38:22.65#ibcon#about to read 4, iclass 30, count 0 2006.176.07:38:22.65#ibcon#read 4, iclass 30, count 0 2006.176.07:38:22.65#ibcon#about to read 5, iclass 30, count 0 2006.176.07:38:22.65#ibcon#read 5, iclass 30, count 0 2006.176.07:38:22.65#ibcon#about to read 6, iclass 30, count 0 2006.176.07:38:22.65#ibcon#read 6, iclass 30, count 0 2006.176.07:38:22.65#ibcon#end of sib2, iclass 30, count 0 2006.176.07:38:22.65#ibcon#*after write, iclass 30, count 0 2006.176.07:38:22.65#ibcon#*before return 0, iclass 30, count 0 2006.176.07:38:22.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:22.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:38:22.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:38:22.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:38:22.65$vc4f8/vbbw=wide 2006.176.07:38:22.65#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.07:38:22.65#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.07:38:22.65#ibcon#ireg 8 cls_cnt 0 2006.176.07:38:22.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:38:22.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:38:22.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:38:22.72#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:38:22.72#ibcon#first serial, iclass 32, count 0 2006.176.07:38:22.72#ibcon#enter sib2, iclass 32, count 0 2006.176.07:38:22.72#ibcon#flushed, iclass 32, count 0 2006.176.07:38:22.72#ibcon#about to write, iclass 32, count 0 2006.176.07:38:22.72#ibcon#wrote, iclass 32, count 0 2006.176.07:38:22.72#ibcon#about to read 3, iclass 32, count 0 2006.176.07:38:22.74#ibcon#read 3, iclass 32, count 0 2006.176.07:38:22.74#ibcon#about to read 4, iclass 32, count 0 2006.176.07:38:22.74#ibcon#read 4, iclass 32, count 0 2006.176.07:38:22.74#ibcon#about to read 5, iclass 32, count 0 2006.176.07:38:22.74#ibcon#read 5, iclass 32, count 0 2006.176.07:38:22.74#ibcon#about to read 6, iclass 32, count 0 2006.176.07:38:22.74#ibcon#read 6, iclass 32, count 0 2006.176.07:38:22.74#ibcon#end of sib2, iclass 32, count 0 2006.176.07:38:22.74#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:38:22.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:38:22.74#ibcon#[27=BW32\r\n] 2006.176.07:38:22.74#ibcon#*before write, iclass 32, count 0 2006.176.07:38:22.74#ibcon#enter sib2, iclass 32, count 0 2006.176.07:38:22.74#ibcon#flushed, iclass 32, count 0 2006.176.07:38:22.74#ibcon#about to write, iclass 32, count 0 2006.176.07:38:22.74#ibcon#wrote, iclass 32, count 0 2006.176.07:38:22.74#ibcon#about to read 3, iclass 32, count 0 2006.176.07:38:22.77#ibcon#read 3, iclass 32, count 0 2006.176.07:38:22.77#ibcon#about to read 4, iclass 32, count 0 2006.176.07:38:22.77#ibcon#read 4, iclass 32, count 0 2006.176.07:38:22.77#ibcon#about to read 5, iclass 32, count 0 2006.176.07:38:22.77#ibcon#read 5, iclass 32, count 0 2006.176.07:38:22.77#ibcon#about to read 6, iclass 32, count 0 2006.176.07:38:22.77#ibcon#read 6, iclass 32, count 0 2006.176.07:38:22.77#ibcon#end of sib2, iclass 32, count 0 2006.176.07:38:22.77#ibcon#*after write, iclass 32, count 0 2006.176.07:38:22.77#ibcon#*before return 0, iclass 32, count 0 2006.176.07:38:22.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:38:22.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:38:22.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:38:22.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:38:22.77$4f8m12a/ifd4f 2006.176.07:38:22.77$ifd4f/lo= 2006.176.07:38:22.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:38:22.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:38:22.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:38:22.77$ifd4f/patch= 2006.176.07:38:22.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:38:22.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:38:22.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:38:22.77$4f8m12a/"form=m,16.000,1:2 2006.176.07:38:22.77$4f8m12a/"tpicd 2006.176.07:38:22.77$4f8m12a/echo=off 2006.176.07:38:22.77$4f8m12a/xlog=off 2006.176.07:38:22.77:!2006.176.07:38:50 2006.176.07:38:32.14#trakl#Source acquired 2006.176.07:38:32.14#flagr#flagr/antenna,acquired 2006.176.07:38:50.00:preob 2006.176.07:38:51.14/onsource/TRACKING 2006.176.07:38:51.14:!2006.176.07:39:00 2006.176.07:39:00.00:data_valid=on 2006.176.07:39:00.00:midob 2006.176.07:39:00.14/onsource/TRACKING 2006.176.07:39:00.14/wx/23.94,1008.4,92 2006.176.07:39:00.25/cable/+6.4935E-03 2006.176.07:39:01.34/va/01,08,usb,yes,29,31 2006.176.07:39:01.34/va/02,07,usb,yes,29,30 2006.176.07:39:01.34/va/03,06,usb,yes,31,31 2006.176.07:39:01.34/va/04,07,usb,yes,30,32 2006.176.07:39:01.34/va/05,07,usb,yes,31,33 2006.176.07:39:01.34/va/06,06,usb,yes,30,30 2006.176.07:39:01.34/va/07,06,usb,yes,31,30 2006.176.07:39:01.34/va/08,06,usb,yes,33,32 2006.176.07:39:01.57/valo/01,532.99,yes,locked 2006.176.07:39:01.57/valo/02,572.99,yes,locked 2006.176.07:39:01.57/valo/03,672.99,yes,locked 2006.176.07:39:01.57/valo/04,832.99,yes,locked 2006.176.07:39:01.57/valo/05,652.99,yes,locked 2006.176.07:39:01.57/valo/06,772.99,yes,locked 2006.176.07:39:01.57/valo/07,832.99,yes,locked 2006.176.07:39:01.57/valo/08,852.99,yes,locked 2006.176.07:39:02.66/vb/01,04,usb,yes,29,28 2006.176.07:39:02.66/vb/02,04,usb,yes,31,32 2006.176.07:39:02.66/vb/03,04,usb,yes,27,31 2006.176.07:39:02.66/vb/04,04,usb,yes,28,28 2006.176.07:39:02.66/vb/05,04,usb,yes,27,31 2006.176.07:39:02.66/vb/06,04,usb,yes,28,30 2006.176.07:39:02.66/vb/07,04,usb,yes,30,29 2006.176.07:39:02.66/vb/08,04,usb,yes,27,31 2006.176.07:39:02.89/vblo/01,632.99,yes,locked 2006.176.07:39:02.89/vblo/02,640.99,yes,locked 2006.176.07:39:02.89/vblo/03,656.99,yes,locked 2006.176.07:39:02.89/vblo/04,712.99,yes,locked 2006.176.07:39:02.89/vblo/05,744.99,yes,locked 2006.176.07:39:02.89/vblo/06,752.99,yes,locked 2006.176.07:39:02.89/vblo/07,734.99,yes,locked 2006.176.07:39:02.89/vblo/08,744.99,yes,locked 2006.176.07:39:03.04/vabw/8 2006.176.07:39:03.19/vbbw/8 2006.176.07:39:03.28/xfe/off,on,15.0 2006.176.07:39:03.66/ifatt/23,28,28,28 2006.176.07:39:04.08/fmout-gps/S +3.73E-07 2006.176.07:39:04.16:!2006.176.07:40:00 2006.176.07:40:00.00:data_valid=off 2006.176.07:40:00.00:postob 2006.176.07:40:00.09/cable/+6.4924E-03 2006.176.07:40:00.09/wx/23.93,1008.4,92 2006.176.07:40:01.07/fmout-gps/S +3.74E-07 2006.176.07:40:01.07:scan_name=176-0740,k06176,60 2006.176.07:40:01.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.176.07:40:01.14#flagr#flagr/antenna,new-source 2006.176.07:40:02.14:checkk5 2006.176.07:40:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:40:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:40:04.02/chk_obsdata//k5ts1/T1760739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:40:04.39/chk_obsdata//k5ts2/T1760739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:40:04.77/chk_obsdata//k5ts3/T1760739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:40:05.14/chk_obsdata//k5ts4/T1760739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:40:05.85/k5log//k5ts1_log_newline 2006.176.07:40:06.54/k5log//k5ts2_log_newline 2006.176.07:40:07.24/k5log//k5ts3_log_newline 2006.176.07:40:07.93/k5log//k5ts4_log_newline 2006.176.07:40:07.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:40:07.95:4f8m12a=1 2006.176.07:40:07.95$4f8m12a/echo=on 2006.176.07:40:07.95$4f8m12a/pcalon 2006.176.07:40:07.95$pcalon/"no phase cal control is implemented here 2006.176.07:40:07.95$4f8m12a/"tpicd=stop 2006.176.07:40:07.95$4f8m12a/vc4f8 2006.176.07:40:07.95$vc4f8/valo=1,532.99 2006.176.07:40:07.95#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.07:40:07.95#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.07:40:07.95#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:07.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:07.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:07.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:07.95#ibcon#enter wrdev, iclass 39, count 0 2006.176.07:40:07.95#ibcon#first serial, iclass 39, count 0 2006.176.07:40:07.95#ibcon#enter sib2, iclass 39, count 0 2006.176.07:40:07.95#ibcon#flushed, iclass 39, count 0 2006.176.07:40:07.95#ibcon#about to write, iclass 39, count 0 2006.176.07:40:07.95#ibcon#wrote, iclass 39, count 0 2006.176.07:40:07.95#ibcon#about to read 3, iclass 39, count 0 2006.176.07:40:07.97#ibcon#read 3, iclass 39, count 0 2006.176.07:40:07.97#ibcon#about to read 4, iclass 39, count 0 2006.176.07:40:07.97#ibcon#read 4, iclass 39, count 0 2006.176.07:40:07.97#ibcon#about to read 5, iclass 39, count 0 2006.176.07:40:07.97#ibcon#read 5, iclass 39, count 0 2006.176.07:40:07.97#ibcon#about to read 6, iclass 39, count 0 2006.176.07:40:07.97#ibcon#read 6, iclass 39, count 0 2006.176.07:40:07.97#ibcon#end of sib2, iclass 39, count 0 2006.176.07:40:07.97#ibcon#*mode == 0, iclass 39, count 0 2006.176.07:40:07.97#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.07:40:07.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:40:07.97#ibcon#*before write, iclass 39, count 0 2006.176.07:40:07.97#ibcon#enter sib2, iclass 39, count 0 2006.176.07:40:07.97#ibcon#flushed, iclass 39, count 0 2006.176.07:40:07.97#ibcon#about to write, iclass 39, count 0 2006.176.07:40:07.97#ibcon#wrote, iclass 39, count 0 2006.176.07:40:07.97#ibcon#about to read 3, iclass 39, count 0 2006.176.07:40:08.02#ibcon#read 3, iclass 39, count 0 2006.176.07:40:08.02#ibcon#about to read 4, iclass 39, count 0 2006.176.07:40:08.02#ibcon#read 4, iclass 39, count 0 2006.176.07:40:08.02#ibcon#about to read 5, iclass 39, count 0 2006.176.07:40:08.02#ibcon#read 5, iclass 39, count 0 2006.176.07:40:08.02#ibcon#about to read 6, iclass 39, count 0 2006.176.07:40:08.02#ibcon#read 6, iclass 39, count 0 2006.176.07:40:08.02#ibcon#end of sib2, iclass 39, count 0 2006.176.07:40:08.02#ibcon#*after write, iclass 39, count 0 2006.176.07:40:08.02#ibcon#*before return 0, iclass 39, count 0 2006.176.07:40:08.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:08.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:08.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.07:40:08.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.07:40:08.02$vc4f8/va=1,8 2006.176.07:40:08.02#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.07:40:08.02#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.07:40:08.02#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:08.02#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:08.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:08.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:08.02#ibcon#enter wrdev, iclass 3, count 2 2006.176.07:40:08.02#ibcon#first serial, iclass 3, count 2 2006.176.07:40:08.02#ibcon#enter sib2, iclass 3, count 2 2006.176.07:40:08.02#ibcon#flushed, iclass 3, count 2 2006.176.07:40:08.02#ibcon#about to write, iclass 3, count 2 2006.176.07:40:08.02#ibcon#wrote, iclass 3, count 2 2006.176.07:40:08.02#ibcon#about to read 3, iclass 3, count 2 2006.176.07:40:08.04#ibcon#read 3, iclass 3, count 2 2006.176.07:40:08.04#ibcon#about to read 4, iclass 3, count 2 2006.176.07:40:08.04#ibcon#read 4, iclass 3, count 2 2006.176.07:40:08.04#ibcon#about to read 5, iclass 3, count 2 2006.176.07:40:08.04#ibcon#read 5, iclass 3, count 2 2006.176.07:40:08.04#ibcon#about to read 6, iclass 3, count 2 2006.176.07:40:08.04#ibcon#read 6, iclass 3, count 2 2006.176.07:40:08.04#ibcon#end of sib2, iclass 3, count 2 2006.176.07:40:08.04#ibcon#*mode == 0, iclass 3, count 2 2006.176.07:40:08.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.07:40:08.04#ibcon#[25=AT01-08\r\n] 2006.176.07:40:08.04#ibcon#*before write, iclass 3, count 2 2006.176.07:40:08.04#ibcon#enter sib2, iclass 3, count 2 2006.176.07:40:08.04#ibcon#flushed, iclass 3, count 2 2006.176.07:40:08.04#ibcon#about to write, iclass 3, count 2 2006.176.07:40:08.04#ibcon#wrote, iclass 3, count 2 2006.176.07:40:08.04#ibcon#about to read 3, iclass 3, count 2 2006.176.07:40:08.07#ibcon#read 3, iclass 3, count 2 2006.176.07:40:08.07#ibcon#about to read 4, iclass 3, count 2 2006.176.07:40:08.07#ibcon#read 4, iclass 3, count 2 2006.176.07:40:08.07#ibcon#about to read 5, iclass 3, count 2 2006.176.07:40:08.07#ibcon#read 5, iclass 3, count 2 2006.176.07:40:08.07#ibcon#about to read 6, iclass 3, count 2 2006.176.07:40:08.07#ibcon#read 6, iclass 3, count 2 2006.176.07:40:08.07#ibcon#end of sib2, iclass 3, count 2 2006.176.07:40:08.07#ibcon#*after write, iclass 3, count 2 2006.176.07:40:08.07#ibcon#*before return 0, iclass 3, count 2 2006.176.07:40:08.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:08.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:08.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.07:40:08.07#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:08.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:08.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:08.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:08.19#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:40:08.19#ibcon#first serial, iclass 3, count 0 2006.176.07:40:08.19#ibcon#enter sib2, iclass 3, count 0 2006.176.07:40:08.19#ibcon#flushed, iclass 3, count 0 2006.176.07:40:08.19#ibcon#about to write, iclass 3, count 0 2006.176.07:40:08.19#ibcon#wrote, iclass 3, count 0 2006.176.07:40:08.19#ibcon#about to read 3, iclass 3, count 0 2006.176.07:40:08.21#ibcon#read 3, iclass 3, count 0 2006.176.07:40:08.21#ibcon#about to read 4, iclass 3, count 0 2006.176.07:40:08.21#ibcon#read 4, iclass 3, count 0 2006.176.07:40:08.21#ibcon#about to read 5, iclass 3, count 0 2006.176.07:40:08.21#ibcon#read 5, iclass 3, count 0 2006.176.07:40:08.21#ibcon#about to read 6, iclass 3, count 0 2006.176.07:40:08.21#ibcon#read 6, iclass 3, count 0 2006.176.07:40:08.21#ibcon#end of sib2, iclass 3, count 0 2006.176.07:40:08.21#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:40:08.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:40:08.21#ibcon#[25=USB\r\n] 2006.176.07:40:08.21#ibcon#*before write, iclass 3, count 0 2006.176.07:40:08.21#ibcon#enter sib2, iclass 3, count 0 2006.176.07:40:08.21#ibcon#flushed, iclass 3, count 0 2006.176.07:40:08.21#ibcon#about to write, iclass 3, count 0 2006.176.07:40:08.21#ibcon#wrote, iclass 3, count 0 2006.176.07:40:08.21#ibcon#about to read 3, iclass 3, count 0 2006.176.07:40:08.24#ibcon#read 3, iclass 3, count 0 2006.176.07:40:08.24#ibcon#about to read 4, iclass 3, count 0 2006.176.07:40:08.24#ibcon#read 4, iclass 3, count 0 2006.176.07:40:08.24#ibcon#about to read 5, iclass 3, count 0 2006.176.07:40:08.24#ibcon#read 5, iclass 3, count 0 2006.176.07:40:08.24#ibcon#about to read 6, iclass 3, count 0 2006.176.07:40:08.24#ibcon#read 6, iclass 3, count 0 2006.176.07:40:08.24#ibcon#end of sib2, iclass 3, count 0 2006.176.07:40:08.24#ibcon#*after write, iclass 3, count 0 2006.176.07:40:08.24#ibcon#*before return 0, iclass 3, count 0 2006.176.07:40:08.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:08.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:08.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:40:08.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:40:08.24$vc4f8/valo=2,572.99 2006.176.07:40:08.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.07:40:08.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.07:40:08.24#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:08.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:08.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:08.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:08.24#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:40:08.24#ibcon#first serial, iclass 5, count 0 2006.176.07:40:08.24#ibcon#enter sib2, iclass 5, count 0 2006.176.07:40:08.24#ibcon#flushed, iclass 5, count 0 2006.176.07:40:08.24#ibcon#about to write, iclass 5, count 0 2006.176.07:40:08.24#ibcon#wrote, iclass 5, count 0 2006.176.07:40:08.24#ibcon#about to read 3, iclass 5, count 0 2006.176.07:40:08.26#ibcon#read 3, iclass 5, count 0 2006.176.07:40:08.26#ibcon#about to read 4, iclass 5, count 0 2006.176.07:40:08.26#ibcon#read 4, iclass 5, count 0 2006.176.07:40:08.26#ibcon#about to read 5, iclass 5, count 0 2006.176.07:40:08.26#ibcon#read 5, iclass 5, count 0 2006.176.07:40:08.26#ibcon#about to read 6, iclass 5, count 0 2006.176.07:40:08.26#ibcon#read 6, iclass 5, count 0 2006.176.07:40:08.26#ibcon#end of sib2, iclass 5, count 0 2006.176.07:40:08.26#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:40:08.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:40:08.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:40:08.26#ibcon#*before write, iclass 5, count 0 2006.176.07:40:08.26#ibcon#enter sib2, iclass 5, count 0 2006.176.07:40:08.26#ibcon#flushed, iclass 5, count 0 2006.176.07:40:08.26#ibcon#about to write, iclass 5, count 0 2006.176.07:40:08.26#ibcon#wrote, iclass 5, count 0 2006.176.07:40:08.26#ibcon#about to read 3, iclass 5, count 0 2006.176.07:40:08.30#ibcon#read 3, iclass 5, count 0 2006.176.07:40:08.30#ibcon#about to read 4, iclass 5, count 0 2006.176.07:40:08.30#ibcon#read 4, iclass 5, count 0 2006.176.07:40:08.30#ibcon#about to read 5, iclass 5, count 0 2006.176.07:40:08.30#ibcon#read 5, iclass 5, count 0 2006.176.07:40:08.30#ibcon#about to read 6, iclass 5, count 0 2006.176.07:40:08.30#ibcon#read 6, iclass 5, count 0 2006.176.07:40:08.30#ibcon#end of sib2, iclass 5, count 0 2006.176.07:40:08.30#ibcon#*after write, iclass 5, count 0 2006.176.07:40:08.30#ibcon#*before return 0, iclass 5, count 0 2006.176.07:40:08.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:08.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:08.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:40:08.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:40:08.30$vc4f8/va=2,7 2006.176.07:40:08.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.07:40:08.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.07:40:08.30#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:08.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:08.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:08.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:08.36#ibcon#enter wrdev, iclass 7, count 2 2006.176.07:40:08.36#ibcon#first serial, iclass 7, count 2 2006.176.07:40:08.36#ibcon#enter sib2, iclass 7, count 2 2006.176.07:40:08.36#ibcon#flushed, iclass 7, count 2 2006.176.07:40:08.36#ibcon#about to write, iclass 7, count 2 2006.176.07:40:08.36#ibcon#wrote, iclass 7, count 2 2006.176.07:40:08.36#ibcon#about to read 3, iclass 7, count 2 2006.176.07:40:08.38#ibcon#read 3, iclass 7, count 2 2006.176.07:40:08.38#ibcon#about to read 4, iclass 7, count 2 2006.176.07:40:08.38#ibcon#read 4, iclass 7, count 2 2006.176.07:40:08.38#ibcon#about to read 5, iclass 7, count 2 2006.176.07:40:08.38#ibcon#read 5, iclass 7, count 2 2006.176.07:40:08.38#ibcon#about to read 6, iclass 7, count 2 2006.176.07:40:08.38#ibcon#read 6, iclass 7, count 2 2006.176.07:40:08.38#ibcon#end of sib2, iclass 7, count 2 2006.176.07:40:08.38#ibcon#*mode == 0, iclass 7, count 2 2006.176.07:40:08.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.07:40:08.38#ibcon#[25=AT02-07\r\n] 2006.176.07:40:08.38#ibcon#*before write, iclass 7, count 2 2006.176.07:40:08.38#ibcon#enter sib2, iclass 7, count 2 2006.176.07:40:08.38#ibcon#flushed, iclass 7, count 2 2006.176.07:40:08.38#ibcon#about to write, iclass 7, count 2 2006.176.07:40:08.38#ibcon#wrote, iclass 7, count 2 2006.176.07:40:08.38#ibcon#about to read 3, iclass 7, count 2 2006.176.07:40:08.41#ibcon#read 3, iclass 7, count 2 2006.176.07:40:08.41#ibcon#about to read 4, iclass 7, count 2 2006.176.07:40:08.41#ibcon#read 4, iclass 7, count 2 2006.176.07:40:08.41#ibcon#about to read 5, iclass 7, count 2 2006.176.07:40:08.41#ibcon#read 5, iclass 7, count 2 2006.176.07:40:08.41#ibcon#about to read 6, iclass 7, count 2 2006.176.07:40:08.41#ibcon#read 6, iclass 7, count 2 2006.176.07:40:08.41#ibcon#end of sib2, iclass 7, count 2 2006.176.07:40:08.41#ibcon#*after write, iclass 7, count 2 2006.176.07:40:08.41#ibcon#*before return 0, iclass 7, count 2 2006.176.07:40:08.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:08.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:08.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.07:40:08.41#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:08.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:08.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:08.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:08.53#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:40:08.53#ibcon#first serial, iclass 7, count 0 2006.176.07:40:08.53#ibcon#enter sib2, iclass 7, count 0 2006.176.07:40:08.53#ibcon#flushed, iclass 7, count 0 2006.176.07:40:08.53#ibcon#about to write, iclass 7, count 0 2006.176.07:40:08.53#ibcon#wrote, iclass 7, count 0 2006.176.07:40:08.53#ibcon#about to read 3, iclass 7, count 0 2006.176.07:40:08.55#ibcon#read 3, iclass 7, count 0 2006.176.07:40:08.55#ibcon#about to read 4, iclass 7, count 0 2006.176.07:40:08.55#ibcon#read 4, iclass 7, count 0 2006.176.07:40:08.55#ibcon#about to read 5, iclass 7, count 0 2006.176.07:40:08.55#ibcon#read 5, iclass 7, count 0 2006.176.07:40:08.55#ibcon#about to read 6, iclass 7, count 0 2006.176.07:40:08.55#ibcon#read 6, iclass 7, count 0 2006.176.07:40:08.55#ibcon#end of sib2, iclass 7, count 0 2006.176.07:40:08.55#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:40:08.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:40:08.55#ibcon#[25=USB\r\n] 2006.176.07:40:08.55#ibcon#*before write, iclass 7, count 0 2006.176.07:40:08.55#ibcon#enter sib2, iclass 7, count 0 2006.176.07:40:08.55#ibcon#flushed, iclass 7, count 0 2006.176.07:40:08.55#ibcon#about to write, iclass 7, count 0 2006.176.07:40:08.55#ibcon#wrote, iclass 7, count 0 2006.176.07:40:08.55#ibcon#about to read 3, iclass 7, count 0 2006.176.07:40:08.58#ibcon#read 3, iclass 7, count 0 2006.176.07:40:08.58#ibcon#about to read 4, iclass 7, count 0 2006.176.07:40:08.58#ibcon#read 4, iclass 7, count 0 2006.176.07:40:08.58#ibcon#about to read 5, iclass 7, count 0 2006.176.07:40:08.58#ibcon#read 5, iclass 7, count 0 2006.176.07:40:08.58#ibcon#about to read 6, iclass 7, count 0 2006.176.07:40:08.58#ibcon#read 6, iclass 7, count 0 2006.176.07:40:08.58#ibcon#end of sib2, iclass 7, count 0 2006.176.07:40:08.58#ibcon#*after write, iclass 7, count 0 2006.176.07:40:08.58#ibcon#*before return 0, iclass 7, count 0 2006.176.07:40:08.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:08.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:08.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:40:08.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:40:08.58$vc4f8/valo=3,672.99 2006.176.07:40:08.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.07:40:08.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.07:40:08.58#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:08.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:08.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:08.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:08.59#ibcon#enter wrdev, iclass 11, count 0 2006.176.07:40:08.59#ibcon#first serial, iclass 11, count 0 2006.176.07:40:08.59#ibcon#enter sib2, iclass 11, count 0 2006.176.07:40:08.59#ibcon#flushed, iclass 11, count 0 2006.176.07:40:08.59#ibcon#about to write, iclass 11, count 0 2006.176.07:40:08.59#ibcon#wrote, iclass 11, count 0 2006.176.07:40:08.59#ibcon#about to read 3, iclass 11, count 0 2006.176.07:40:08.60#ibcon#read 3, iclass 11, count 0 2006.176.07:40:08.60#ibcon#about to read 4, iclass 11, count 0 2006.176.07:40:08.60#ibcon#read 4, iclass 11, count 0 2006.176.07:40:08.60#ibcon#about to read 5, iclass 11, count 0 2006.176.07:40:08.60#ibcon#read 5, iclass 11, count 0 2006.176.07:40:08.60#ibcon#about to read 6, iclass 11, count 0 2006.176.07:40:08.60#ibcon#read 6, iclass 11, count 0 2006.176.07:40:08.60#ibcon#end of sib2, iclass 11, count 0 2006.176.07:40:08.60#ibcon#*mode == 0, iclass 11, count 0 2006.176.07:40:08.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.07:40:08.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:40:08.60#ibcon#*before write, iclass 11, count 0 2006.176.07:40:08.60#ibcon#enter sib2, iclass 11, count 0 2006.176.07:40:08.60#ibcon#flushed, iclass 11, count 0 2006.176.07:40:08.60#ibcon#about to write, iclass 11, count 0 2006.176.07:40:08.60#ibcon#wrote, iclass 11, count 0 2006.176.07:40:08.60#ibcon#about to read 3, iclass 11, count 0 2006.176.07:40:08.64#ibcon#read 3, iclass 11, count 0 2006.176.07:40:08.64#ibcon#about to read 4, iclass 11, count 0 2006.176.07:40:08.64#ibcon#read 4, iclass 11, count 0 2006.176.07:40:08.64#ibcon#about to read 5, iclass 11, count 0 2006.176.07:40:08.64#ibcon#read 5, iclass 11, count 0 2006.176.07:40:08.64#ibcon#about to read 6, iclass 11, count 0 2006.176.07:40:08.64#ibcon#read 6, iclass 11, count 0 2006.176.07:40:08.64#ibcon#end of sib2, iclass 11, count 0 2006.176.07:40:08.64#ibcon#*after write, iclass 11, count 0 2006.176.07:40:08.64#ibcon#*before return 0, iclass 11, count 0 2006.176.07:40:08.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:08.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:08.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.07:40:08.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.07:40:08.64$vc4f8/va=3,6 2006.176.07:40:08.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.07:40:08.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.07:40:08.64#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:08.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:08.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:08.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:08.70#ibcon#enter wrdev, iclass 13, count 2 2006.176.07:40:08.70#ibcon#first serial, iclass 13, count 2 2006.176.07:40:08.70#ibcon#enter sib2, iclass 13, count 2 2006.176.07:40:08.70#ibcon#flushed, iclass 13, count 2 2006.176.07:40:08.70#ibcon#about to write, iclass 13, count 2 2006.176.07:40:08.70#ibcon#wrote, iclass 13, count 2 2006.176.07:40:08.70#ibcon#about to read 3, iclass 13, count 2 2006.176.07:40:08.72#ibcon#read 3, iclass 13, count 2 2006.176.07:40:08.72#ibcon#about to read 4, iclass 13, count 2 2006.176.07:40:08.72#ibcon#read 4, iclass 13, count 2 2006.176.07:40:08.72#ibcon#about to read 5, iclass 13, count 2 2006.176.07:40:08.72#ibcon#read 5, iclass 13, count 2 2006.176.07:40:08.72#ibcon#about to read 6, iclass 13, count 2 2006.176.07:40:08.72#ibcon#read 6, iclass 13, count 2 2006.176.07:40:08.72#ibcon#end of sib2, iclass 13, count 2 2006.176.07:40:08.72#ibcon#*mode == 0, iclass 13, count 2 2006.176.07:40:08.72#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.07:40:08.72#ibcon#[25=AT03-06\r\n] 2006.176.07:40:08.72#ibcon#*before write, iclass 13, count 2 2006.176.07:40:08.72#ibcon#enter sib2, iclass 13, count 2 2006.176.07:40:08.72#ibcon#flushed, iclass 13, count 2 2006.176.07:40:08.72#ibcon#about to write, iclass 13, count 2 2006.176.07:40:08.72#ibcon#wrote, iclass 13, count 2 2006.176.07:40:08.72#ibcon#about to read 3, iclass 13, count 2 2006.176.07:40:08.76#ibcon#read 3, iclass 13, count 2 2006.176.07:40:08.76#ibcon#about to read 4, iclass 13, count 2 2006.176.07:40:08.76#ibcon#read 4, iclass 13, count 2 2006.176.07:40:08.76#ibcon#about to read 5, iclass 13, count 2 2006.176.07:40:08.76#ibcon#read 5, iclass 13, count 2 2006.176.07:40:08.76#ibcon#about to read 6, iclass 13, count 2 2006.176.07:40:08.76#ibcon#read 6, iclass 13, count 2 2006.176.07:40:08.76#ibcon#end of sib2, iclass 13, count 2 2006.176.07:40:08.76#ibcon#*after write, iclass 13, count 2 2006.176.07:40:08.76#ibcon#*before return 0, iclass 13, count 2 2006.176.07:40:08.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:08.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:08.76#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.07:40:08.76#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:08.76#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:08.88#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:08.88#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:08.88#ibcon#enter wrdev, iclass 13, count 0 2006.176.07:40:08.88#ibcon#first serial, iclass 13, count 0 2006.176.07:40:08.88#ibcon#enter sib2, iclass 13, count 0 2006.176.07:40:08.88#ibcon#flushed, iclass 13, count 0 2006.176.07:40:08.88#ibcon#about to write, iclass 13, count 0 2006.176.07:40:08.88#ibcon#wrote, iclass 13, count 0 2006.176.07:40:08.88#ibcon#about to read 3, iclass 13, count 0 2006.176.07:40:08.90#ibcon#read 3, iclass 13, count 0 2006.176.07:40:08.90#ibcon#about to read 4, iclass 13, count 0 2006.176.07:40:08.90#ibcon#read 4, iclass 13, count 0 2006.176.07:40:08.90#ibcon#about to read 5, iclass 13, count 0 2006.176.07:40:08.90#ibcon#read 5, iclass 13, count 0 2006.176.07:40:08.90#ibcon#about to read 6, iclass 13, count 0 2006.176.07:40:08.90#ibcon#read 6, iclass 13, count 0 2006.176.07:40:08.90#ibcon#end of sib2, iclass 13, count 0 2006.176.07:40:08.90#ibcon#*mode == 0, iclass 13, count 0 2006.176.07:40:08.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.07:40:08.90#ibcon#[25=USB\r\n] 2006.176.07:40:08.90#ibcon#*before write, iclass 13, count 0 2006.176.07:40:08.90#ibcon#enter sib2, iclass 13, count 0 2006.176.07:40:08.90#ibcon#flushed, iclass 13, count 0 2006.176.07:40:08.90#ibcon#about to write, iclass 13, count 0 2006.176.07:40:08.90#ibcon#wrote, iclass 13, count 0 2006.176.07:40:08.90#ibcon#about to read 3, iclass 13, count 0 2006.176.07:40:08.93#ibcon#read 3, iclass 13, count 0 2006.176.07:40:08.93#ibcon#about to read 4, iclass 13, count 0 2006.176.07:40:08.93#ibcon#read 4, iclass 13, count 0 2006.176.07:40:08.93#ibcon#about to read 5, iclass 13, count 0 2006.176.07:40:08.93#ibcon#read 5, iclass 13, count 0 2006.176.07:40:08.93#ibcon#about to read 6, iclass 13, count 0 2006.176.07:40:08.93#ibcon#read 6, iclass 13, count 0 2006.176.07:40:08.93#ibcon#end of sib2, iclass 13, count 0 2006.176.07:40:08.93#ibcon#*after write, iclass 13, count 0 2006.176.07:40:08.93#ibcon#*before return 0, iclass 13, count 0 2006.176.07:40:08.93#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:08.93#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:08.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.07:40:08.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.07:40:08.93$vc4f8/valo=4,832.99 2006.176.07:40:08.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.07:40:08.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.07:40:08.93#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:08.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:08.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:08.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:08.93#ibcon#enter wrdev, iclass 15, count 0 2006.176.07:40:08.93#ibcon#first serial, iclass 15, count 0 2006.176.07:40:08.93#ibcon#enter sib2, iclass 15, count 0 2006.176.07:40:08.93#ibcon#flushed, iclass 15, count 0 2006.176.07:40:08.93#ibcon#about to write, iclass 15, count 0 2006.176.07:40:08.93#ibcon#wrote, iclass 15, count 0 2006.176.07:40:08.93#ibcon#about to read 3, iclass 15, count 0 2006.176.07:40:08.95#ibcon#read 3, iclass 15, count 0 2006.176.07:40:08.95#ibcon#about to read 4, iclass 15, count 0 2006.176.07:40:08.95#ibcon#read 4, iclass 15, count 0 2006.176.07:40:08.95#ibcon#about to read 5, iclass 15, count 0 2006.176.07:40:08.95#ibcon#read 5, iclass 15, count 0 2006.176.07:40:08.95#ibcon#about to read 6, iclass 15, count 0 2006.176.07:40:08.95#ibcon#read 6, iclass 15, count 0 2006.176.07:40:08.95#ibcon#end of sib2, iclass 15, count 0 2006.176.07:40:08.95#ibcon#*mode == 0, iclass 15, count 0 2006.176.07:40:08.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.07:40:08.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:40:08.95#ibcon#*before write, iclass 15, count 0 2006.176.07:40:08.95#ibcon#enter sib2, iclass 15, count 0 2006.176.07:40:08.95#ibcon#flushed, iclass 15, count 0 2006.176.07:40:08.95#ibcon#about to write, iclass 15, count 0 2006.176.07:40:08.95#ibcon#wrote, iclass 15, count 0 2006.176.07:40:08.95#ibcon#about to read 3, iclass 15, count 0 2006.176.07:40:08.99#ibcon#read 3, iclass 15, count 0 2006.176.07:40:08.99#ibcon#about to read 4, iclass 15, count 0 2006.176.07:40:08.99#ibcon#read 4, iclass 15, count 0 2006.176.07:40:08.99#ibcon#about to read 5, iclass 15, count 0 2006.176.07:40:08.99#ibcon#read 5, iclass 15, count 0 2006.176.07:40:08.99#ibcon#about to read 6, iclass 15, count 0 2006.176.07:40:08.99#ibcon#read 6, iclass 15, count 0 2006.176.07:40:08.99#ibcon#end of sib2, iclass 15, count 0 2006.176.07:40:08.99#ibcon#*after write, iclass 15, count 0 2006.176.07:40:08.99#ibcon#*before return 0, iclass 15, count 0 2006.176.07:40:08.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:08.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:08.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.07:40:08.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.07:40:08.99$vc4f8/va=4,7 2006.176.07:40:08.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.176.07:40:08.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.176.07:40:08.99#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:08.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:09.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:09.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:09.05#ibcon#enter wrdev, iclass 17, count 2 2006.176.07:40:09.05#ibcon#first serial, iclass 17, count 2 2006.176.07:40:09.05#ibcon#enter sib2, iclass 17, count 2 2006.176.07:40:09.05#ibcon#flushed, iclass 17, count 2 2006.176.07:40:09.05#ibcon#about to write, iclass 17, count 2 2006.176.07:40:09.05#ibcon#wrote, iclass 17, count 2 2006.176.07:40:09.05#ibcon#about to read 3, iclass 17, count 2 2006.176.07:40:09.07#ibcon#read 3, iclass 17, count 2 2006.176.07:40:09.07#ibcon#about to read 4, iclass 17, count 2 2006.176.07:40:09.07#ibcon#read 4, iclass 17, count 2 2006.176.07:40:09.07#ibcon#about to read 5, iclass 17, count 2 2006.176.07:40:09.07#ibcon#read 5, iclass 17, count 2 2006.176.07:40:09.07#ibcon#about to read 6, iclass 17, count 2 2006.176.07:40:09.07#ibcon#read 6, iclass 17, count 2 2006.176.07:40:09.07#ibcon#end of sib2, iclass 17, count 2 2006.176.07:40:09.07#ibcon#*mode == 0, iclass 17, count 2 2006.176.07:40:09.07#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.176.07:40:09.07#ibcon#[25=AT04-07\r\n] 2006.176.07:40:09.07#ibcon#*before write, iclass 17, count 2 2006.176.07:40:09.07#ibcon#enter sib2, iclass 17, count 2 2006.176.07:40:09.07#ibcon#flushed, iclass 17, count 2 2006.176.07:40:09.07#ibcon#about to write, iclass 17, count 2 2006.176.07:40:09.07#ibcon#wrote, iclass 17, count 2 2006.176.07:40:09.07#ibcon#about to read 3, iclass 17, count 2 2006.176.07:40:09.10#ibcon#read 3, iclass 17, count 2 2006.176.07:40:09.10#ibcon#about to read 4, iclass 17, count 2 2006.176.07:40:09.10#ibcon#read 4, iclass 17, count 2 2006.176.07:40:09.10#ibcon#about to read 5, iclass 17, count 2 2006.176.07:40:09.10#ibcon#read 5, iclass 17, count 2 2006.176.07:40:09.10#ibcon#about to read 6, iclass 17, count 2 2006.176.07:40:09.10#ibcon#read 6, iclass 17, count 2 2006.176.07:40:09.10#ibcon#end of sib2, iclass 17, count 2 2006.176.07:40:09.10#ibcon#*after write, iclass 17, count 2 2006.176.07:40:09.10#ibcon#*before return 0, iclass 17, count 2 2006.176.07:40:09.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:09.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:09.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.176.07:40:09.10#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:09.10#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:09.22#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:09.22#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:09.22#ibcon#enter wrdev, iclass 17, count 0 2006.176.07:40:09.22#ibcon#first serial, iclass 17, count 0 2006.176.07:40:09.22#ibcon#enter sib2, iclass 17, count 0 2006.176.07:40:09.22#ibcon#flushed, iclass 17, count 0 2006.176.07:40:09.22#ibcon#about to write, iclass 17, count 0 2006.176.07:40:09.22#ibcon#wrote, iclass 17, count 0 2006.176.07:40:09.22#ibcon#about to read 3, iclass 17, count 0 2006.176.07:40:09.24#ibcon#read 3, iclass 17, count 0 2006.176.07:40:09.24#ibcon#about to read 4, iclass 17, count 0 2006.176.07:40:09.24#ibcon#read 4, iclass 17, count 0 2006.176.07:40:09.24#ibcon#about to read 5, iclass 17, count 0 2006.176.07:40:09.24#ibcon#read 5, iclass 17, count 0 2006.176.07:40:09.24#ibcon#about to read 6, iclass 17, count 0 2006.176.07:40:09.24#ibcon#read 6, iclass 17, count 0 2006.176.07:40:09.24#ibcon#end of sib2, iclass 17, count 0 2006.176.07:40:09.24#ibcon#*mode == 0, iclass 17, count 0 2006.176.07:40:09.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.07:40:09.24#ibcon#[25=USB\r\n] 2006.176.07:40:09.24#ibcon#*before write, iclass 17, count 0 2006.176.07:40:09.24#ibcon#enter sib2, iclass 17, count 0 2006.176.07:40:09.24#ibcon#flushed, iclass 17, count 0 2006.176.07:40:09.24#ibcon#about to write, iclass 17, count 0 2006.176.07:40:09.24#ibcon#wrote, iclass 17, count 0 2006.176.07:40:09.24#ibcon#about to read 3, iclass 17, count 0 2006.176.07:40:09.27#ibcon#read 3, iclass 17, count 0 2006.176.07:40:09.27#ibcon#about to read 4, iclass 17, count 0 2006.176.07:40:09.27#ibcon#read 4, iclass 17, count 0 2006.176.07:40:09.27#ibcon#about to read 5, iclass 17, count 0 2006.176.07:40:09.27#ibcon#read 5, iclass 17, count 0 2006.176.07:40:09.27#ibcon#about to read 6, iclass 17, count 0 2006.176.07:40:09.27#ibcon#read 6, iclass 17, count 0 2006.176.07:40:09.27#ibcon#end of sib2, iclass 17, count 0 2006.176.07:40:09.27#ibcon#*after write, iclass 17, count 0 2006.176.07:40:09.27#ibcon#*before return 0, iclass 17, count 0 2006.176.07:40:09.27#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:09.27#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:09.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.07:40:09.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.07:40:09.27$vc4f8/valo=5,652.99 2006.176.07:40:09.27#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.176.07:40:09.27#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.176.07:40:09.27#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:09.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:09.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:09.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:09.27#ibcon#enter wrdev, iclass 19, count 0 2006.176.07:40:09.27#ibcon#first serial, iclass 19, count 0 2006.176.07:40:09.27#ibcon#enter sib2, iclass 19, count 0 2006.176.07:40:09.27#ibcon#flushed, iclass 19, count 0 2006.176.07:40:09.27#ibcon#about to write, iclass 19, count 0 2006.176.07:40:09.27#ibcon#wrote, iclass 19, count 0 2006.176.07:40:09.27#ibcon#about to read 3, iclass 19, count 0 2006.176.07:40:09.29#ibcon#read 3, iclass 19, count 0 2006.176.07:40:09.29#ibcon#about to read 4, iclass 19, count 0 2006.176.07:40:09.29#ibcon#read 4, iclass 19, count 0 2006.176.07:40:09.29#ibcon#about to read 5, iclass 19, count 0 2006.176.07:40:09.29#ibcon#read 5, iclass 19, count 0 2006.176.07:40:09.29#ibcon#about to read 6, iclass 19, count 0 2006.176.07:40:09.29#ibcon#read 6, iclass 19, count 0 2006.176.07:40:09.29#ibcon#end of sib2, iclass 19, count 0 2006.176.07:40:09.29#ibcon#*mode == 0, iclass 19, count 0 2006.176.07:40:09.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.07:40:09.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:40:09.29#ibcon#*before write, iclass 19, count 0 2006.176.07:40:09.29#ibcon#enter sib2, iclass 19, count 0 2006.176.07:40:09.29#ibcon#flushed, iclass 19, count 0 2006.176.07:40:09.29#ibcon#about to write, iclass 19, count 0 2006.176.07:40:09.29#ibcon#wrote, iclass 19, count 0 2006.176.07:40:09.29#ibcon#about to read 3, iclass 19, count 0 2006.176.07:40:09.33#ibcon#read 3, iclass 19, count 0 2006.176.07:40:09.33#ibcon#about to read 4, iclass 19, count 0 2006.176.07:40:09.33#ibcon#read 4, iclass 19, count 0 2006.176.07:40:09.33#ibcon#about to read 5, iclass 19, count 0 2006.176.07:40:09.33#ibcon#read 5, iclass 19, count 0 2006.176.07:40:09.33#ibcon#about to read 6, iclass 19, count 0 2006.176.07:40:09.33#ibcon#read 6, iclass 19, count 0 2006.176.07:40:09.33#ibcon#end of sib2, iclass 19, count 0 2006.176.07:40:09.33#ibcon#*after write, iclass 19, count 0 2006.176.07:40:09.33#ibcon#*before return 0, iclass 19, count 0 2006.176.07:40:09.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:09.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:09.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.07:40:09.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.07:40:09.33$vc4f8/va=5,7 2006.176.07:40:09.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.176.07:40:09.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.176.07:40:09.33#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:09.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:09.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:09.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:09.39#ibcon#enter wrdev, iclass 21, count 2 2006.176.07:40:09.39#ibcon#first serial, iclass 21, count 2 2006.176.07:40:09.39#ibcon#enter sib2, iclass 21, count 2 2006.176.07:40:09.39#ibcon#flushed, iclass 21, count 2 2006.176.07:40:09.39#ibcon#about to write, iclass 21, count 2 2006.176.07:40:09.39#ibcon#wrote, iclass 21, count 2 2006.176.07:40:09.39#ibcon#about to read 3, iclass 21, count 2 2006.176.07:40:09.41#ibcon#read 3, iclass 21, count 2 2006.176.07:40:09.41#ibcon#about to read 4, iclass 21, count 2 2006.176.07:40:09.41#ibcon#read 4, iclass 21, count 2 2006.176.07:40:09.41#ibcon#about to read 5, iclass 21, count 2 2006.176.07:40:09.41#ibcon#read 5, iclass 21, count 2 2006.176.07:40:09.41#ibcon#about to read 6, iclass 21, count 2 2006.176.07:40:09.41#ibcon#read 6, iclass 21, count 2 2006.176.07:40:09.41#ibcon#end of sib2, iclass 21, count 2 2006.176.07:40:09.41#ibcon#*mode == 0, iclass 21, count 2 2006.176.07:40:09.41#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.176.07:40:09.41#ibcon#[25=AT05-07\r\n] 2006.176.07:40:09.41#ibcon#*before write, iclass 21, count 2 2006.176.07:40:09.41#ibcon#enter sib2, iclass 21, count 2 2006.176.07:40:09.41#ibcon#flushed, iclass 21, count 2 2006.176.07:40:09.41#ibcon#about to write, iclass 21, count 2 2006.176.07:40:09.41#ibcon#wrote, iclass 21, count 2 2006.176.07:40:09.41#ibcon#about to read 3, iclass 21, count 2 2006.176.07:40:09.44#ibcon#read 3, iclass 21, count 2 2006.176.07:40:09.44#ibcon#about to read 4, iclass 21, count 2 2006.176.07:40:09.44#ibcon#read 4, iclass 21, count 2 2006.176.07:40:09.44#ibcon#about to read 5, iclass 21, count 2 2006.176.07:40:09.44#ibcon#read 5, iclass 21, count 2 2006.176.07:40:09.44#ibcon#about to read 6, iclass 21, count 2 2006.176.07:40:09.44#ibcon#read 6, iclass 21, count 2 2006.176.07:40:09.44#ibcon#end of sib2, iclass 21, count 2 2006.176.07:40:09.44#ibcon#*after write, iclass 21, count 2 2006.176.07:40:09.44#ibcon#*before return 0, iclass 21, count 2 2006.176.07:40:09.44#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:09.44#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:09.44#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.176.07:40:09.44#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:09.44#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:09.56#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:09.56#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:09.56#ibcon#enter wrdev, iclass 21, count 0 2006.176.07:40:09.56#ibcon#first serial, iclass 21, count 0 2006.176.07:40:09.56#ibcon#enter sib2, iclass 21, count 0 2006.176.07:40:09.56#ibcon#flushed, iclass 21, count 0 2006.176.07:40:09.56#ibcon#about to write, iclass 21, count 0 2006.176.07:40:09.56#ibcon#wrote, iclass 21, count 0 2006.176.07:40:09.56#ibcon#about to read 3, iclass 21, count 0 2006.176.07:40:09.58#ibcon#read 3, iclass 21, count 0 2006.176.07:40:09.58#ibcon#about to read 4, iclass 21, count 0 2006.176.07:40:09.58#ibcon#read 4, iclass 21, count 0 2006.176.07:40:09.58#ibcon#about to read 5, iclass 21, count 0 2006.176.07:40:09.58#ibcon#read 5, iclass 21, count 0 2006.176.07:40:09.58#ibcon#about to read 6, iclass 21, count 0 2006.176.07:40:09.58#ibcon#read 6, iclass 21, count 0 2006.176.07:40:09.58#ibcon#end of sib2, iclass 21, count 0 2006.176.07:40:09.58#ibcon#*mode == 0, iclass 21, count 0 2006.176.07:40:09.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.07:40:09.58#ibcon#[25=USB\r\n] 2006.176.07:40:09.58#ibcon#*before write, iclass 21, count 0 2006.176.07:40:09.58#ibcon#enter sib2, iclass 21, count 0 2006.176.07:40:09.58#ibcon#flushed, iclass 21, count 0 2006.176.07:40:09.58#ibcon#about to write, iclass 21, count 0 2006.176.07:40:09.58#ibcon#wrote, iclass 21, count 0 2006.176.07:40:09.58#ibcon#about to read 3, iclass 21, count 0 2006.176.07:40:09.61#ibcon#read 3, iclass 21, count 0 2006.176.07:40:09.61#ibcon#about to read 4, iclass 21, count 0 2006.176.07:40:09.61#ibcon#read 4, iclass 21, count 0 2006.176.07:40:09.61#ibcon#about to read 5, iclass 21, count 0 2006.176.07:40:09.61#ibcon#read 5, iclass 21, count 0 2006.176.07:40:09.61#ibcon#about to read 6, iclass 21, count 0 2006.176.07:40:09.61#ibcon#read 6, iclass 21, count 0 2006.176.07:40:09.61#ibcon#end of sib2, iclass 21, count 0 2006.176.07:40:09.61#ibcon#*after write, iclass 21, count 0 2006.176.07:40:09.61#ibcon#*before return 0, iclass 21, count 0 2006.176.07:40:09.61#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:09.61#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:09.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.07:40:09.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.07:40:09.61$vc4f8/valo=6,772.99 2006.176.07:40:09.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.07:40:09.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.07:40:09.61#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:09.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:09.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:09.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:09.62#ibcon#enter wrdev, iclass 23, count 0 2006.176.07:40:09.62#ibcon#first serial, iclass 23, count 0 2006.176.07:40:09.62#ibcon#enter sib2, iclass 23, count 0 2006.176.07:40:09.62#ibcon#flushed, iclass 23, count 0 2006.176.07:40:09.62#ibcon#about to write, iclass 23, count 0 2006.176.07:40:09.62#ibcon#wrote, iclass 23, count 0 2006.176.07:40:09.62#ibcon#about to read 3, iclass 23, count 0 2006.176.07:40:09.63#ibcon#read 3, iclass 23, count 0 2006.176.07:40:09.63#ibcon#about to read 4, iclass 23, count 0 2006.176.07:40:09.63#ibcon#read 4, iclass 23, count 0 2006.176.07:40:09.63#ibcon#about to read 5, iclass 23, count 0 2006.176.07:40:09.63#ibcon#read 5, iclass 23, count 0 2006.176.07:40:09.63#ibcon#about to read 6, iclass 23, count 0 2006.176.07:40:09.63#ibcon#read 6, iclass 23, count 0 2006.176.07:40:09.63#ibcon#end of sib2, iclass 23, count 0 2006.176.07:40:09.63#ibcon#*mode == 0, iclass 23, count 0 2006.176.07:40:09.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.07:40:09.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:40:09.63#ibcon#*before write, iclass 23, count 0 2006.176.07:40:09.63#ibcon#enter sib2, iclass 23, count 0 2006.176.07:40:09.63#ibcon#flushed, iclass 23, count 0 2006.176.07:40:09.63#ibcon#about to write, iclass 23, count 0 2006.176.07:40:09.63#ibcon#wrote, iclass 23, count 0 2006.176.07:40:09.63#ibcon#about to read 3, iclass 23, count 0 2006.176.07:40:09.67#ibcon#read 3, iclass 23, count 0 2006.176.07:40:09.67#ibcon#about to read 4, iclass 23, count 0 2006.176.07:40:09.67#ibcon#read 4, iclass 23, count 0 2006.176.07:40:09.67#ibcon#about to read 5, iclass 23, count 0 2006.176.07:40:09.67#ibcon#read 5, iclass 23, count 0 2006.176.07:40:09.67#ibcon#about to read 6, iclass 23, count 0 2006.176.07:40:09.67#ibcon#read 6, iclass 23, count 0 2006.176.07:40:09.67#ibcon#end of sib2, iclass 23, count 0 2006.176.07:40:09.67#ibcon#*after write, iclass 23, count 0 2006.176.07:40:09.67#ibcon#*before return 0, iclass 23, count 0 2006.176.07:40:09.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:09.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:09.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.07:40:09.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.07:40:09.67$vc4f8/va=6,6 2006.176.07:40:09.67#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.176.07:40:09.67#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.176.07:40:09.67#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:09.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:40:09.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:40:09.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:40:09.73#ibcon#enter wrdev, iclass 25, count 2 2006.176.07:40:09.73#ibcon#first serial, iclass 25, count 2 2006.176.07:40:09.73#ibcon#enter sib2, iclass 25, count 2 2006.176.07:40:09.73#ibcon#flushed, iclass 25, count 2 2006.176.07:40:09.73#ibcon#about to write, iclass 25, count 2 2006.176.07:40:09.73#ibcon#wrote, iclass 25, count 2 2006.176.07:40:09.73#ibcon#about to read 3, iclass 25, count 2 2006.176.07:40:09.75#ibcon#read 3, iclass 25, count 2 2006.176.07:40:09.75#ibcon#about to read 4, iclass 25, count 2 2006.176.07:40:09.75#ibcon#read 4, iclass 25, count 2 2006.176.07:40:09.75#ibcon#about to read 5, iclass 25, count 2 2006.176.07:40:09.75#ibcon#read 5, iclass 25, count 2 2006.176.07:40:09.75#ibcon#about to read 6, iclass 25, count 2 2006.176.07:40:09.75#ibcon#read 6, iclass 25, count 2 2006.176.07:40:09.75#ibcon#end of sib2, iclass 25, count 2 2006.176.07:40:09.75#ibcon#*mode == 0, iclass 25, count 2 2006.176.07:40:09.75#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.176.07:40:09.75#ibcon#[25=AT06-06\r\n] 2006.176.07:40:09.75#ibcon#*before write, iclass 25, count 2 2006.176.07:40:09.75#ibcon#enter sib2, iclass 25, count 2 2006.176.07:40:09.75#ibcon#flushed, iclass 25, count 2 2006.176.07:40:09.75#ibcon#about to write, iclass 25, count 2 2006.176.07:40:09.75#ibcon#wrote, iclass 25, count 2 2006.176.07:40:09.75#ibcon#about to read 3, iclass 25, count 2 2006.176.07:40:09.78#ibcon#read 3, iclass 25, count 2 2006.176.07:40:09.78#ibcon#about to read 4, iclass 25, count 2 2006.176.07:40:09.78#ibcon#read 4, iclass 25, count 2 2006.176.07:40:09.78#ibcon#about to read 5, iclass 25, count 2 2006.176.07:40:09.78#ibcon#read 5, iclass 25, count 2 2006.176.07:40:09.78#ibcon#about to read 6, iclass 25, count 2 2006.176.07:40:09.78#ibcon#read 6, iclass 25, count 2 2006.176.07:40:09.78#ibcon#end of sib2, iclass 25, count 2 2006.176.07:40:09.78#ibcon#*after write, iclass 25, count 2 2006.176.07:40:09.78#ibcon#*before return 0, iclass 25, count 2 2006.176.07:40:09.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:40:09.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:40:09.78#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.176.07:40:09.78#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:09.78#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:40:09.90#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:40:09.90#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:40:09.90#ibcon#enter wrdev, iclass 25, count 0 2006.176.07:40:09.90#ibcon#first serial, iclass 25, count 0 2006.176.07:40:09.90#ibcon#enter sib2, iclass 25, count 0 2006.176.07:40:09.90#ibcon#flushed, iclass 25, count 0 2006.176.07:40:09.90#ibcon#about to write, iclass 25, count 0 2006.176.07:40:09.90#ibcon#wrote, iclass 25, count 0 2006.176.07:40:09.90#ibcon#about to read 3, iclass 25, count 0 2006.176.07:40:09.92#ibcon#read 3, iclass 25, count 0 2006.176.07:40:09.92#ibcon#about to read 4, iclass 25, count 0 2006.176.07:40:09.92#ibcon#read 4, iclass 25, count 0 2006.176.07:40:09.92#ibcon#about to read 5, iclass 25, count 0 2006.176.07:40:09.92#ibcon#read 5, iclass 25, count 0 2006.176.07:40:09.92#ibcon#about to read 6, iclass 25, count 0 2006.176.07:40:09.92#ibcon#read 6, iclass 25, count 0 2006.176.07:40:09.92#ibcon#end of sib2, iclass 25, count 0 2006.176.07:40:09.92#ibcon#*mode == 0, iclass 25, count 0 2006.176.07:40:09.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.07:40:09.92#ibcon#[25=USB\r\n] 2006.176.07:40:09.92#ibcon#*before write, iclass 25, count 0 2006.176.07:40:09.92#ibcon#enter sib2, iclass 25, count 0 2006.176.07:40:09.92#ibcon#flushed, iclass 25, count 0 2006.176.07:40:09.92#ibcon#about to write, iclass 25, count 0 2006.176.07:40:09.92#ibcon#wrote, iclass 25, count 0 2006.176.07:40:09.92#ibcon#about to read 3, iclass 25, count 0 2006.176.07:40:09.95#ibcon#read 3, iclass 25, count 0 2006.176.07:40:09.95#ibcon#about to read 4, iclass 25, count 0 2006.176.07:40:09.95#ibcon#read 4, iclass 25, count 0 2006.176.07:40:09.95#ibcon#about to read 5, iclass 25, count 0 2006.176.07:40:09.95#ibcon#read 5, iclass 25, count 0 2006.176.07:40:09.95#ibcon#about to read 6, iclass 25, count 0 2006.176.07:40:09.95#ibcon#read 6, iclass 25, count 0 2006.176.07:40:09.95#ibcon#end of sib2, iclass 25, count 0 2006.176.07:40:09.95#ibcon#*after write, iclass 25, count 0 2006.176.07:40:09.95#ibcon#*before return 0, iclass 25, count 0 2006.176.07:40:09.95#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:40:09.95#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:40:09.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.07:40:09.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.07:40:09.95$vc4f8/valo=7,832.99 2006.176.07:40:09.95#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.07:40:09.95#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.07:40:09.95#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:09.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:40:09.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:40:09.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:40:09.95#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:40:09.95#ibcon#first serial, iclass 27, count 0 2006.176.07:40:09.95#ibcon#enter sib2, iclass 27, count 0 2006.176.07:40:09.95#ibcon#flushed, iclass 27, count 0 2006.176.07:40:09.95#ibcon#about to write, iclass 27, count 0 2006.176.07:40:09.95#ibcon#wrote, iclass 27, count 0 2006.176.07:40:09.95#ibcon#about to read 3, iclass 27, count 0 2006.176.07:40:09.97#ibcon#read 3, iclass 27, count 0 2006.176.07:40:09.97#ibcon#about to read 4, iclass 27, count 0 2006.176.07:40:09.97#ibcon#read 4, iclass 27, count 0 2006.176.07:40:09.97#ibcon#about to read 5, iclass 27, count 0 2006.176.07:40:09.97#ibcon#read 5, iclass 27, count 0 2006.176.07:40:09.97#ibcon#about to read 6, iclass 27, count 0 2006.176.07:40:09.97#ibcon#read 6, iclass 27, count 0 2006.176.07:40:09.97#ibcon#end of sib2, iclass 27, count 0 2006.176.07:40:09.97#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:40:09.97#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:40:09.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:40:09.97#ibcon#*before write, iclass 27, count 0 2006.176.07:40:09.97#ibcon#enter sib2, iclass 27, count 0 2006.176.07:40:09.97#ibcon#flushed, iclass 27, count 0 2006.176.07:40:09.97#ibcon#about to write, iclass 27, count 0 2006.176.07:40:09.97#ibcon#wrote, iclass 27, count 0 2006.176.07:40:09.97#ibcon#about to read 3, iclass 27, count 0 2006.176.07:40:10.01#ibcon#read 3, iclass 27, count 0 2006.176.07:40:10.01#ibcon#about to read 4, iclass 27, count 0 2006.176.07:40:10.01#ibcon#read 4, iclass 27, count 0 2006.176.07:40:10.01#ibcon#about to read 5, iclass 27, count 0 2006.176.07:40:10.01#ibcon#read 5, iclass 27, count 0 2006.176.07:40:10.01#ibcon#about to read 6, iclass 27, count 0 2006.176.07:40:10.01#ibcon#read 6, iclass 27, count 0 2006.176.07:40:10.01#ibcon#end of sib2, iclass 27, count 0 2006.176.07:40:10.01#ibcon#*after write, iclass 27, count 0 2006.176.07:40:10.01#ibcon#*before return 0, iclass 27, count 0 2006.176.07:40:10.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:40:10.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:40:10.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:40:10.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:40:10.01$vc4f8/va=7,6 2006.176.07:40:10.01#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.07:40:10.01#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.07:40:10.01#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:10.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:40:10.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:40:10.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:40:10.07#ibcon#enter wrdev, iclass 29, count 2 2006.176.07:40:10.07#ibcon#first serial, iclass 29, count 2 2006.176.07:40:10.07#ibcon#enter sib2, iclass 29, count 2 2006.176.07:40:10.07#ibcon#flushed, iclass 29, count 2 2006.176.07:40:10.07#ibcon#about to write, iclass 29, count 2 2006.176.07:40:10.07#ibcon#wrote, iclass 29, count 2 2006.176.07:40:10.07#ibcon#about to read 3, iclass 29, count 2 2006.176.07:40:10.09#ibcon#read 3, iclass 29, count 2 2006.176.07:40:10.09#ibcon#about to read 4, iclass 29, count 2 2006.176.07:40:10.09#ibcon#read 4, iclass 29, count 2 2006.176.07:40:10.09#ibcon#about to read 5, iclass 29, count 2 2006.176.07:40:10.09#ibcon#read 5, iclass 29, count 2 2006.176.07:40:10.09#ibcon#about to read 6, iclass 29, count 2 2006.176.07:40:10.09#ibcon#read 6, iclass 29, count 2 2006.176.07:40:10.09#ibcon#end of sib2, iclass 29, count 2 2006.176.07:40:10.09#ibcon#*mode == 0, iclass 29, count 2 2006.176.07:40:10.09#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.07:40:10.09#ibcon#[25=AT07-06\r\n] 2006.176.07:40:10.09#ibcon#*before write, iclass 29, count 2 2006.176.07:40:10.09#ibcon#enter sib2, iclass 29, count 2 2006.176.07:40:10.09#ibcon#flushed, iclass 29, count 2 2006.176.07:40:10.09#ibcon#about to write, iclass 29, count 2 2006.176.07:40:10.09#ibcon#wrote, iclass 29, count 2 2006.176.07:40:10.09#ibcon#about to read 3, iclass 29, count 2 2006.176.07:40:10.12#ibcon#read 3, iclass 29, count 2 2006.176.07:40:10.12#ibcon#about to read 4, iclass 29, count 2 2006.176.07:40:10.12#ibcon#read 4, iclass 29, count 2 2006.176.07:40:10.12#ibcon#about to read 5, iclass 29, count 2 2006.176.07:40:10.12#ibcon#read 5, iclass 29, count 2 2006.176.07:40:10.12#ibcon#about to read 6, iclass 29, count 2 2006.176.07:40:10.12#ibcon#read 6, iclass 29, count 2 2006.176.07:40:10.12#ibcon#end of sib2, iclass 29, count 2 2006.176.07:40:10.12#ibcon#*after write, iclass 29, count 2 2006.176.07:40:10.12#ibcon#*before return 0, iclass 29, count 2 2006.176.07:40:10.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:40:10.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:40:10.12#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.07:40:10.12#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:10.12#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:40:10.24#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:40:10.24#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:40:10.24#ibcon#enter wrdev, iclass 29, count 0 2006.176.07:40:10.24#ibcon#first serial, iclass 29, count 0 2006.176.07:40:10.24#ibcon#enter sib2, iclass 29, count 0 2006.176.07:40:10.24#ibcon#flushed, iclass 29, count 0 2006.176.07:40:10.24#ibcon#about to write, iclass 29, count 0 2006.176.07:40:10.24#ibcon#wrote, iclass 29, count 0 2006.176.07:40:10.24#ibcon#about to read 3, iclass 29, count 0 2006.176.07:40:10.26#ibcon#read 3, iclass 29, count 0 2006.176.07:40:10.26#ibcon#about to read 4, iclass 29, count 0 2006.176.07:40:10.26#ibcon#read 4, iclass 29, count 0 2006.176.07:40:10.26#ibcon#about to read 5, iclass 29, count 0 2006.176.07:40:10.26#ibcon#read 5, iclass 29, count 0 2006.176.07:40:10.26#ibcon#about to read 6, iclass 29, count 0 2006.176.07:40:10.26#ibcon#read 6, iclass 29, count 0 2006.176.07:40:10.26#ibcon#end of sib2, iclass 29, count 0 2006.176.07:40:10.26#ibcon#*mode == 0, iclass 29, count 0 2006.176.07:40:10.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.07:40:10.26#ibcon#[25=USB\r\n] 2006.176.07:40:10.26#ibcon#*before write, iclass 29, count 0 2006.176.07:40:10.26#ibcon#enter sib2, iclass 29, count 0 2006.176.07:40:10.26#ibcon#flushed, iclass 29, count 0 2006.176.07:40:10.26#ibcon#about to write, iclass 29, count 0 2006.176.07:40:10.26#ibcon#wrote, iclass 29, count 0 2006.176.07:40:10.26#ibcon#about to read 3, iclass 29, count 0 2006.176.07:40:10.29#ibcon#read 3, iclass 29, count 0 2006.176.07:40:10.29#ibcon#about to read 4, iclass 29, count 0 2006.176.07:40:10.29#ibcon#read 4, iclass 29, count 0 2006.176.07:40:10.29#ibcon#about to read 5, iclass 29, count 0 2006.176.07:40:10.29#ibcon#read 5, iclass 29, count 0 2006.176.07:40:10.29#ibcon#about to read 6, iclass 29, count 0 2006.176.07:40:10.29#ibcon#read 6, iclass 29, count 0 2006.176.07:40:10.29#ibcon#end of sib2, iclass 29, count 0 2006.176.07:40:10.29#ibcon#*after write, iclass 29, count 0 2006.176.07:40:10.29#ibcon#*before return 0, iclass 29, count 0 2006.176.07:40:10.29#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:40:10.29#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:40:10.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.07:40:10.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.07:40:10.29$vc4f8/valo=8,852.99 2006.176.07:40:10.29#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.07:40:10.29#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.07:40:10.29#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:10.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:40:10.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:40:10.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:40:10.29#ibcon#enter wrdev, iclass 31, count 0 2006.176.07:40:10.29#ibcon#first serial, iclass 31, count 0 2006.176.07:40:10.29#ibcon#enter sib2, iclass 31, count 0 2006.176.07:40:10.29#ibcon#flushed, iclass 31, count 0 2006.176.07:40:10.29#ibcon#about to write, iclass 31, count 0 2006.176.07:40:10.29#ibcon#wrote, iclass 31, count 0 2006.176.07:40:10.29#ibcon#about to read 3, iclass 31, count 0 2006.176.07:40:10.31#ibcon#read 3, iclass 31, count 0 2006.176.07:40:10.31#ibcon#about to read 4, iclass 31, count 0 2006.176.07:40:10.31#ibcon#read 4, iclass 31, count 0 2006.176.07:40:10.31#ibcon#about to read 5, iclass 31, count 0 2006.176.07:40:10.31#ibcon#read 5, iclass 31, count 0 2006.176.07:40:10.31#ibcon#about to read 6, iclass 31, count 0 2006.176.07:40:10.31#ibcon#read 6, iclass 31, count 0 2006.176.07:40:10.31#ibcon#end of sib2, iclass 31, count 0 2006.176.07:40:10.31#ibcon#*mode == 0, iclass 31, count 0 2006.176.07:40:10.31#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.07:40:10.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:40:10.31#ibcon#*before write, iclass 31, count 0 2006.176.07:40:10.31#ibcon#enter sib2, iclass 31, count 0 2006.176.07:40:10.31#ibcon#flushed, iclass 31, count 0 2006.176.07:40:10.31#ibcon#about to write, iclass 31, count 0 2006.176.07:40:10.31#ibcon#wrote, iclass 31, count 0 2006.176.07:40:10.31#ibcon#about to read 3, iclass 31, count 0 2006.176.07:40:10.35#ibcon#read 3, iclass 31, count 0 2006.176.07:40:10.35#ibcon#about to read 4, iclass 31, count 0 2006.176.07:40:10.35#ibcon#read 4, iclass 31, count 0 2006.176.07:40:10.35#ibcon#about to read 5, iclass 31, count 0 2006.176.07:40:10.35#ibcon#read 5, iclass 31, count 0 2006.176.07:40:10.35#ibcon#about to read 6, iclass 31, count 0 2006.176.07:40:10.35#ibcon#read 6, iclass 31, count 0 2006.176.07:40:10.35#ibcon#end of sib2, iclass 31, count 0 2006.176.07:40:10.35#ibcon#*after write, iclass 31, count 0 2006.176.07:40:10.35#ibcon#*before return 0, iclass 31, count 0 2006.176.07:40:10.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:40:10.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:40:10.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.07:40:10.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.07:40:10.35$vc4f8/va=8,6 2006.176.07:40:10.35#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.176.07:40:10.35#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.176.07:40:10.35#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:10.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:40:10.41#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:40:10.41#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:40:10.41#ibcon#enter wrdev, iclass 33, count 2 2006.176.07:40:10.41#ibcon#first serial, iclass 33, count 2 2006.176.07:40:10.41#ibcon#enter sib2, iclass 33, count 2 2006.176.07:40:10.41#ibcon#flushed, iclass 33, count 2 2006.176.07:40:10.41#ibcon#about to write, iclass 33, count 2 2006.176.07:40:10.41#ibcon#wrote, iclass 33, count 2 2006.176.07:40:10.41#ibcon#about to read 3, iclass 33, count 2 2006.176.07:40:10.43#ibcon#read 3, iclass 33, count 2 2006.176.07:40:10.43#ibcon#about to read 4, iclass 33, count 2 2006.176.07:40:10.43#ibcon#read 4, iclass 33, count 2 2006.176.07:40:10.43#ibcon#about to read 5, iclass 33, count 2 2006.176.07:40:10.43#ibcon#read 5, iclass 33, count 2 2006.176.07:40:10.43#ibcon#about to read 6, iclass 33, count 2 2006.176.07:40:10.43#ibcon#read 6, iclass 33, count 2 2006.176.07:40:10.43#ibcon#end of sib2, iclass 33, count 2 2006.176.07:40:10.43#ibcon#*mode == 0, iclass 33, count 2 2006.176.07:40:10.43#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.176.07:40:10.43#ibcon#[25=AT08-06\r\n] 2006.176.07:40:10.43#ibcon#*before write, iclass 33, count 2 2006.176.07:40:10.43#ibcon#enter sib2, iclass 33, count 2 2006.176.07:40:10.43#ibcon#flushed, iclass 33, count 2 2006.176.07:40:10.43#ibcon#about to write, iclass 33, count 2 2006.176.07:40:10.43#ibcon#wrote, iclass 33, count 2 2006.176.07:40:10.43#ibcon#about to read 3, iclass 33, count 2 2006.176.07:40:10.46#ibcon#read 3, iclass 33, count 2 2006.176.07:40:10.46#ibcon#about to read 4, iclass 33, count 2 2006.176.07:40:10.46#ibcon#read 4, iclass 33, count 2 2006.176.07:40:10.46#ibcon#about to read 5, iclass 33, count 2 2006.176.07:40:10.46#ibcon#read 5, iclass 33, count 2 2006.176.07:40:10.46#ibcon#about to read 6, iclass 33, count 2 2006.176.07:40:10.46#ibcon#read 6, iclass 33, count 2 2006.176.07:40:10.46#ibcon#end of sib2, iclass 33, count 2 2006.176.07:40:10.46#ibcon#*after write, iclass 33, count 2 2006.176.07:40:10.46#ibcon#*before return 0, iclass 33, count 2 2006.176.07:40:10.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:40:10.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:40:10.46#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.176.07:40:10.46#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:10.46#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:40:10.58#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:40:10.58#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:40:10.58#ibcon#enter wrdev, iclass 33, count 0 2006.176.07:40:10.58#ibcon#first serial, iclass 33, count 0 2006.176.07:40:10.58#ibcon#enter sib2, iclass 33, count 0 2006.176.07:40:10.58#ibcon#flushed, iclass 33, count 0 2006.176.07:40:10.58#ibcon#about to write, iclass 33, count 0 2006.176.07:40:10.58#ibcon#wrote, iclass 33, count 0 2006.176.07:40:10.58#ibcon#about to read 3, iclass 33, count 0 2006.176.07:40:10.60#ibcon#read 3, iclass 33, count 0 2006.176.07:40:10.60#ibcon#about to read 4, iclass 33, count 0 2006.176.07:40:10.60#ibcon#read 4, iclass 33, count 0 2006.176.07:40:10.60#ibcon#about to read 5, iclass 33, count 0 2006.176.07:40:10.60#ibcon#read 5, iclass 33, count 0 2006.176.07:40:10.60#ibcon#about to read 6, iclass 33, count 0 2006.176.07:40:10.60#ibcon#read 6, iclass 33, count 0 2006.176.07:40:10.60#ibcon#end of sib2, iclass 33, count 0 2006.176.07:40:10.60#ibcon#*mode == 0, iclass 33, count 0 2006.176.07:40:10.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.07:40:10.60#ibcon#[25=USB\r\n] 2006.176.07:40:10.60#ibcon#*before write, iclass 33, count 0 2006.176.07:40:10.60#ibcon#enter sib2, iclass 33, count 0 2006.176.07:40:10.60#ibcon#flushed, iclass 33, count 0 2006.176.07:40:10.60#ibcon#about to write, iclass 33, count 0 2006.176.07:40:10.60#ibcon#wrote, iclass 33, count 0 2006.176.07:40:10.60#ibcon#about to read 3, iclass 33, count 0 2006.176.07:40:10.63#ibcon#read 3, iclass 33, count 0 2006.176.07:40:10.63#ibcon#about to read 4, iclass 33, count 0 2006.176.07:40:10.63#ibcon#read 4, iclass 33, count 0 2006.176.07:40:10.63#ibcon#about to read 5, iclass 33, count 0 2006.176.07:40:10.63#ibcon#read 5, iclass 33, count 0 2006.176.07:40:10.63#ibcon#about to read 6, iclass 33, count 0 2006.176.07:40:10.63#ibcon#read 6, iclass 33, count 0 2006.176.07:40:10.63#ibcon#end of sib2, iclass 33, count 0 2006.176.07:40:10.63#ibcon#*after write, iclass 33, count 0 2006.176.07:40:10.63#ibcon#*before return 0, iclass 33, count 0 2006.176.07:40:10.63#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:40:10.63#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:40:10.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.07:40:10.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.07:40:10.63$vc4f8/vblo=1,632.99 2006.176.07:40:10.63#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.07:40:10.63#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.07:40:10.63#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:10.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:40:10.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:40:10.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:40:10.63#ibcon#enter wrdev, iclass 35, count 0 2006.176.07:40:10.63#ibcon#first serial, iclass 35, count 0 2006.176.07:40:10.63#ibcon#enter sib2, iclass 35, count 0 2006.176.07:40:10.63#ibcon#flushed, iclass 35, count 0 2006.176.07:40:10.63#ibcon#about to write, iclass 35, count 0 2006.176.07:40:10.63#ibcon#wrote, iclass 35, count 0 2006.176.07:40:10.63#ibcon#about to read 3, iclass 35, count 0 2006.176.07:40:10.65#ibcon#read 3, iclass 35, count 0 2006.176.07:40:10.65#ibcon#about to read 4, iclass 35, count 0 2006.176.07:40:10.65#ibcon#read 4, iclass 35, count 0 2006.176.07:40:10.65#ibcon#about to read 5, iclass 35, count 0 2006.176.07:40:10.65#ibcon#read 5, iclass 35, count 0 2006.176.07:40:10.65#ibcon#about to read 6, iclass 35, count 0 2006.176.07:40:10.65#ibcon#read 6, iclass 35, count 0 2006.176.07:40:10.65#ibcon#end of sib2, iclass 35, count 0 2006.176.07:40:10.65#ibcon#*mode == 0, iclass 35, count 0 2006.176.07:40:10.65#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.07:40:10.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:40:10.65#ibcon#*before write, iclass 35, count 0 2006.176.07:40:10.65#ibcon#enter sib2, iclass 35, count 0 2006.176.07:40:10.65#ibcon#flushed, iclass 35, count 0 2006.176.07:40:10.65#ibcon#about to write, iclass 35, count 0 2006.176.07:40:10.65#ibcon#wrote, iclass 35, count 0 2006.176.07:40:10.65#ibcon#about to read 3, iclass 35, count 0 2006.176.07:40:10.69#ibcon#read 3, iclass 35, count 0 2006.176.07:40:10.69#ibcon#about to read 4, iclass 35, count 0 2006.176.07:40:10.69#ibcon#read 4, iclass 35, count 0 2006.176.07:40:10.69#ibcon#about to read 5, iclass 35, count 0 2006.176.07:40:10.69#ibcon#read 5, iclass 35, count 0 2006.176.07:40:10.69#ibcon#about to read 6, iclass 35, count 0 2006.176.07:40:10.69#ibcon#read 6, iclass 35, count 0 2006.176.07:40:10.69#ibcon#end of sib2, iclass 35, count 0 2006.176.07:40:10.69#ibcon#*after write, iclass 35, count 0 2006.176.07:40:10.69#ibcon#*before return 0, iclass 35, count 0 2006.176.07:40:10.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:40:10.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:40:10.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.07:40:10.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.07:40:10.69$vc4f8/vb=1,4 2006.176.07:40:10.69#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.176.07:40:10.69#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.176.07:40:10.69#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:10.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:40:10.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:40:10.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:40:10.69#ibcon#enter wrdev, iclass 37, count 2 2006.176.07:40:10.69#ibcon#first serial, iclass 37, count 2 2006.176.07:40:10.69#ibcon#enter sib2, iclass 37, count 2 2006.176.07:40:10.69#ibcon#flushed, iclass 37, count 2 2006.176.07:40:10.69#ibcon#about to write, iclass 37, count 2 2006.176.07:40:10.69#ibcon#wrote, iclass 37, count 2 2006.176.07:40:10.69#ibcon#about to read 3, iclass 37, count 2 2006.176.07:40:10.71#ibcon#read 3, iclass 37, count 2 2006.176.07:40:10.71#ibcon#about to read 4, iclass 37, count 2 2006.176.07:40:10.71#ibcon#read 4, iclass 37, count 2 2006.176.07:40:10.71#ibcon#about to read 5, iclass 37, count 2 2006.176.07:40:10.71#ibcon#read 5, iclass 37, count 2 2006.176.07:40:10.71#ibcon#about to read 6, iclass 37, count 2 2006.176.07:40:10.71#ibcon#read 6, iclass 37, count 2 2006.176.07:40:10.71#ibcon#end of sib2, iclass 37, count 2 2006.176.07:40:10.71#ibcon#*mode == 0, iclass 37, count 2 2006.176.07:40:10.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.176.07:40:10.71#ibcon#[27=AT01-04\r\n] 2006.176.07:40:10.71#ibcon#*before write, iclass 37, count 2 2006.176.07:40:10.71#ibcon#enter sib2, iclass 37, count 2 2006.176.07:40:10.71#ibcon#flushed, iclass 37, count 2 2006.176.07:40:10.71#ibcon#about to write, iclass 37, count 2 2006.176.07:40:10.71#ibcon#wrote, iclass 37, count 2 2006.176.07:40:10.71#ibcon#about to read 3, iclass 37, count 2 2006.176.07:40:10.74#ibcon#read 3, iclass 37, count 2 2006.176.07:40:10.74#ibcon#about to read 4, iclass 37, count 2 2006.176.07:40:10.74#ibcon#read 4, iclass 37, count 2 2006.176.07:40:10.74#ibcon#about to read 5, iclass 37, count 2 2006.176.07:40:10.74#ibcon#read 5, iclass 37, count 2 2006.176.07:40:10.74#ibcon#about to read 6, iclass 37, count 2 2006.176.07:40:10.74#ibcon#read 6, iclass 37, count 2 2006.176.07:40:10.74#ibcon#end of sib2, iclass 37, count 2 2006.176.07:40:10.74#ibcon#*after write, iclass 37, count 2 2006.176.07:40:10.74#ibcon#*before return 0, iclass 37, count 2 2006.176.07:40:10.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:40:10.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:40:10.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.176.07:40:10.74#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:10.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:40:10.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:40:10.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:40:10.86#ibcon#enter wrdev, iclass 37, count 0 2006.176.07:40:10.86#ibcon#first serial, iclass 37, count 0 2006.176.07:40:10.86#ibcon#enter sib2, iclass 37, count 0 2006.176.07:40:10.86#ibcon#flushed, iclass 37, count 0 2006.176.07:40:10.86#ibcon#about to write, iclass 37, count 0 2006.176.07:40:10.86#ibcon#wrote, iclass 37, count 0 2006.176.07:40:10.86#ibcon#about to read 3, iclass 37, count 0 2006.176.07:40:10.88#ibcon#read 3, iclass 37, count 0 2006.176.07:40:10.88#ibcon#about to read 4, iclass 37, count 0 2006.176.07:40:10.88#ibcon#read 4, iclass 37, count 0 2006.176.07:40:10.88#ibcon#about to read 5, iclass 37, count 0 2006.176.07:40:10.88#ibcon#read 5, iclass 37, count 0 2006.176.07:40:10.88#ibcon#about to read 6, iclass 37, count 0 2006.176.07:40:10.88#ibcon#read 6, iclass 37, count 0 2006.176.07:40:10.88#ibcon#end of sib2, iclass 37, count 0 2006.176.07:40:10.88#ibcon#*mode == 0, iclass 37, count 0 2006.176.07:40:10.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.07:40:10.88#ibcon#[27=USB\r\n] 2006.176.07:40:10.88#ibcon#*before write, iclass 37, count 0 2006.176.07:40:10.88#ibcon#enter sib2, iclass 37, count 0 2006.176.07:40:10.88#ibcon#flushed, iclass 37, count 0 2006.176.07:40:10.88#ibcon#about to write, iclass 37, count 0 2006.176.07:40:10.88#ibcon#wrote, iclass 37, count 0 2006.176.07:40:10.88#ibcon#about to read 3, iclass 37, count 0 2006.176.07:40:10.91#ibcon#read 3, iclass 37, count 0 2006.176.07:40:10.91#ibcon#about to read 4, iclass 37, count 0 2006.176.07:40:10.91#ibcon#read 4, iclass 37, count 0 2006.176.07:40:10.91#ibcon#about to read 5, iclass 37, count 0 2006.176.07:40:10.91#ibcon#read 5, iclass 37, count 0 2006.176.07:40:10.91#ibcon#about to read 6, iclass 37, count 0 2006.176.07:40:10.91#ibcon#read 6, iclass 37, count 0 2006.176.07:40:10.91#ibcon#end of sib2, iclass 37, count 0 2006.176.07:40:10.91#ibcon#*after write, iclass 37, count 0 2006.176.07:40:10.91#ibcon#*before return 0, iclass 37, count 0 2006.176.07:40:10.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:40:10.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:40:10.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.07:40:10.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.07:40:10.91$vc4f8/vblo=2,640.99 2006.176.07:40:10.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.07:40:10.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.07:40:10.91#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:10.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:10.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:10.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:10.91#ibcon#enter wrdev, iclass 39, count 0 2006.176.07:40:10.91#ibcon#first serial, iclass 39, count 0 2006.176.07:40:10.91#ibcon#enter sib2, iclass 39, count 0 2006.176.07:40:10.91#ibcon#flushed, iclass 39, count 0 2006.176.07:40:10.91#ibcon#about to write, iclass 39, count 0 2006.176.07:40:10.91#ibcon#wrote, iclass 39, count 0 2006.176.07:40:10.91#ibcon#about to read 3, iclass 39, count 0 2006.176.07:40:10.93#ibcon#read 3, iclass 39, count 0 2006.176.07:40:10.93#ibcon#about to read 4, iclass 39, count 0 2006.176.07:40:10.93#ibcon#read 4, iclass 39, count 0 2006.176.07:40:10.93#ibcon#about to read 5, iclass 39, count 0 2006.176.07:40:10.93#ibcon#read 5, iclass 39, count 0 2006.176.07:40:10.93#ibcon#about to read 6, iclass 39, count 0 2006.176.07:40:10.93#ibcon#read 6, iclass 39, count 0 2006.176.07:40:10.93#ibcon#end of sib2, iclass 39, count 0 2006.176.07:40:10.93#ibcon#*mode == 0, iclass 39, count 0 2006.176.07:40:10.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.07:40:10.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:40:10.93#ibcon#*before write, iclass 39, count 0 2006.176.07:40:10.93#ibcon#enter sib2, iclass 39, count 0 2006.176.07:40:10.93#ibcon#flushed, iclass 39, count 0 2006.176.07:40:10.93#ibcon#about to write, iclass 39, count 0 2006.176.07:40:10.93#ibcon#wrote, iclass 39, count 0 2006.176.07:40:10.93#ibcon#about to read 3, iclass 39, count 0 2006.176.07:40:10.97#ibcon#read 3, iclass 39, count 0 2006.176.07:40:10.97#ibcon#about to read 4, iclass 39, count 0 2006.176.07:40:10.97#ibcon#read 4, iclass 39, count 0 2006.176.07:40:10.97#ibcon#about to read 5, iclass 39, count 0 2006.176.07:40:10.97#ibcon#read 5, iclass 39, count 0 2006.176.07:40:10.97#ibcon#about to read 6, iclass 39, count 0 2006.176.07:40:10.97#ibcon#read 6, iclass 39, count 0 2006.176.07:40:10.97#ibcon#end of sib2, iclass 39, count 0 2006.176.07:40:10.97#ibcon#*after write, iclass 39, count 0 2006.176.07:40:10.97#ibcon#*before return 0, iclass 39, count 0 2006.176.07:40:10.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:10.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:40:10.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.07:40:10.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.07:40:10.97$vc4f8/vb=2,4 2006.176.07:40:10.97#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.07:40:10.97#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.07:40:10.97#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:10.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:11.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:11.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:11.03#ibcon#enter wrdev, iclass 3, count 2 2006.176.07:40:11.03#ibcon#first serial, iclass 3, count 2 2006.176.07:40:11.03#ibcon#enter sib2, iclass 3, count 2 2006.176.07:40:11.03#ibcon#flushed, iclass 3, count 2 2006.176.07:40:11.03#ibcon#about to write, iclass 3, count 2 2006.176.07:40:11.03#ibcon#wrote, iclass 3, count 2 2006.176.07:40:11.03#ibcon#about to read 3, iclass 3, count 2 2006.176.07:40:11.05#ibcon#read 3, iclass 3, count 2 2006.176.07:40:11.05#ibcon#about to read 4, iclass 3, count 2 2006.176.07:40:11.05#ibcon#read 4, iclass 3, count 2 2006.176.07:40:11.05#ibcon#about to read 5, iclass 3, count 2 2006.176.07:40:11.05#ibcon#read 5, iclass 3, count 2 2006.176.07:40:11.05#ibcon#about to read 6, iclass 3, count 2 2006.176.07:40:11.05#ibcon#read 6, iclass 3, count 2 2006.176.07:40:11.05#ibcon#end of sib2, iclass 3, count 2 2006.176.07:40:11.05#ibcon#*mode == 0, iclass 3, count 2 2006.176.07:40:11.05#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.07:40:11.05#ibcon#[27=AT02-04\r\n] 2006.176.07:40:11.05#ibcon#*before write, iclass 3, count 2 2006.176.07:40:11.05#ibcon#enter sib2, iclass 3, count 2 2006.176.07:40:11.05#ibcon#flushed, iclass 3, count 2 2006.176.07:40:11.05#ibcon#about to write, iclass 3, count 2 2006.176.07:40:11.05#ibcon#wrote, iclass 3, count 2 2006.176.07:40:11.05#ibcon#about to read 3, iclass 3, count 2 2006.176.07:40:11.08#ibcon#read 3, iclass 3, count 2 2006.176.07:40:11.08#ibcon#about to read 4, iclass 3, count 2 2006.176.07:40:11.08#ibcon#read 4, iclass 3, count 2 2006.176.07:40:11.08#ibcon#about to read 5, iclass 3, count 2 2006.176.07:40:11.08#ibcon#read 5, iclass 3, count 2 2006.176.07:40:11.08#ibcon#about to read 6, iclass 3, count 2 2006.176.07:40:11.08#ibcon#read 6, iclass 3, count 2 2006.176.07:40:11.08#ibcon#end of sib2, iclass 3, count 2 2006.176.07:40:11.08#ibcon#*after write, iclass 3, count 2 2006.176.07:40:11.08#ibcon#*before return 0, iclass 3, count 2 2006.176.07:40:11.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:11.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:40:11.08#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.07:40:11.08#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:11.08#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:11.20#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:11.20#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:11.20#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:40:11.20#ibcon#first serial, iclass 3, count 0 2006.176.07:40:11.20#ibcon#enter sib2, iclass 3, count 0 2006.176.07:40:11.20#ibcon#flushed, iclass 3, count 0 2006.176.07:40:11.20#ibcon#about to write, iclass 3, count 0 2006.176.07:40:11.20#ibcon#wrote, iclass 3, count 0 2006.176.07:40:11.20#ibcon#about to read 3, iclass 3, count 0 2006.176.07:40:11.22#ibcon#read 3, iclass 3, count 0 2006.176.07:40:11.22#ibcon#about to read 4, iclass 3, count 0 2006.176.07:40:11.22#ibcon#read 4, iclass 3, count 0 2006.176.07:40:11.22#ibcon#about to read 5, iclass 3, count 0 2006.176.07:40:11.22#ibcon#read 5, iclass 3, count 0 2006.176.07:40:11.22#ibcon#about to read 6, iclass 3, count 0 2006.176.07:40:11.22#ibcon#read 6, iclass 3, count 0 2006.176.07:40:11.22#ibcon#end of sib2, iclass 3, count 0 2006.176.07:40:11.22#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:40:11.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:40:11.22#ibcon#[27=USB\r\n] 2006.176.07:40:11.22#ibcon#*before write, iclass 3, count 0 2006.176.07:40:11.22#ibcon#enter sib2, iclass 3, count 0 2006.176.07:40:11.22#ibcon#flushed, iclass 3, count 0 2006.176.07:40:11.22#ibcon#about to write, iclass 3, count 0 2006.176.07:40:11.22#ibcon#wrote, iclass 3, count 0 2006.176.07:40:11.22#ibcon#about to read 3, iclass 3, count 0 2006.176.07:40:11.25#ibcon#read 3, iclass 3, count 0 2006.176.07:40:11.25#ibcon#about to read 4, iclass 3, count 0 2006.176.07:40:11.25#ibcon#read 4, iclass 3, count 0 2006.176.07:40:11.25#ibcon#about to read 5, iclass 3, count 0 2006.176.07:40:11.25#ibcon#read 5, iclass 3, count 0 2006.176.07:40:11.25#ibcon#about to read 6, iclass 3, count 0 2006.176.07:40:11.25#ibcon#read 6, iclass 3, count 0 2006.176.07:40:11.25#ibcon#end of sib2, iclass 3, count 0 2006.176.07:40:11.25#ibcon#*after write, iclass 3, count 0 2006.176.07:40:11.25#ibcon#*before return 0, iclass 3, count 0 2006.176.07:40:11.25#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:11.25#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:40:11.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:40:11.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:40:11.25$vc4f8/vblo=3,656.99 2006.176.07:40:11.25#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.07:40:11.25#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.07:40:11.25#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:11.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:11.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:11.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:11.25#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:40:11.25#ibcon#first serial, iclass 5, count 0 2006.176.07:40:11.25#ibcon#enter sib2, iclass 5, count 0 2006.176.07:40:11.25#ibcon#flushed, iclass 5, count 0 2006.176.07:40:11.25#ibcon#about to write, iclass 5, count 0 2006.176.07:40:11.25#ibcon#wrote, iclass 5, count 0 2006.176.07:40:11.25#ibcon#about to read 3, iclass 5, count 0 2006.176.07:40:11.27#ibcon#read 3, iclass 5, count 0 2006.176.07:40:11.27#ibcon#about to read 4, iclass 5, count 0 2006.176.07:40:11.27#ibcon#read 4, iclass 5, count 0 2006.176.07:40:11.27#ibcon#about to read 5, iclass 5, count 0 2006.176.07:40:11.27#ibcon#read 5, iclass 5, count 0 2006.176.07:40:11.27#ibcon#about to read 6, iclass 5, count 0 2006.176.07:40:11.27#ibcon#read 6, iclass 5, count 0 2006.176.07:40:11.27#ibcon#end of sib2, iclass 5, count 0 2006.176.07:40:11.27#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:40:11.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:40:11.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:40:11.27#ibcon#*before write, iclass 5, count 0 2006.176.07:40:11.27#ibcon#enter sib2, iclass 5, count 0 2006.176.07:40:11.27#ibcon#flushed, iclass 5, count 0 2006.176.07:40:11.27#ibcon#about to write, iclass 5, count 0 2006.176.07:40:11.27#ibcon#wrote, iclass 5, count 0 2006.176.07:40:11.27#ibcon#about to read 3, iclass 5, count 0 2006.176.07:40:11.31#ibcon#read 3, iclass 5, count 0 2006.176.07:40:11.31#ibcon#about to read 4, iclass 5, count 0 2006.176.07:40:11.31#ibcon#read 4, iclass 5, count 0 2006.176.07:40:11.31#ibcon#about to read 5, iclass 5, count 0 2006.176.07:40:11.31#ibcon#read 5, iclass 5, count 0 2006.176.07:40:11.31#ibcon#about to read 6, iclass 5, count 0 2006.176.07:40:11.31#ibcon#read 6, iclass 5, count 0 2006.176.07:40:11.31#ibcon#end of sib2, iclass 5, count 0 2006.176.07:40:11.31#ibcon#*after write, iclass 5, count 0 2006.176.07:40:11.31#ibcon#*before return 0, iclass 5, count 0 2006.176.07:40:11.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:11.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:40:11.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:40:11.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:40:11.31$vc4f8/vb=3,4 2006.176.07:40:11.31#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.07:40:11.31#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.07:40:11.31#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:11.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:11.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:11.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:11.37#ibcon#enter wrdev, iclass 7, count 2 2006.176.07:40:11.37#ibcon#first serial, iclass 7, count 2 2006.176.07:40:11.37#ibcon#enter sib2, iclass 7, count 2 2006.176.07:40:11.37#ibcon#flushed, iclass 7, count 2 2006.176.07:40:11.37#ibcon#about to write, iclass 7, count 2 2006.176.07:40:11.37#ibcon#wrote, iclass 7, count 2 2006.176.07:40:11.37#ibcon#about to read 3, iclass 7, count 2 2006.176.07:40:11.39#ibcon#read 3, iclass 7, count 2 2006.176.07:40:11.39#ibcon#about to read 4, iclass 7, count 2 2006.176.07:40:11.39#ibcon#read 4, iclass 7, count 2 2006.176.07:40:11.39#ibcon#about to read 5, iclass 7, count 2 2006.176.07:40:11.39#ibcon#read 5, iclass 7, count 2 2006.176.07:40:11.39#ibcon#about to read 6, iclass 7, count 2 2006.176.07:40:11.39#ibcon#read 6, iclass 7, count 2 2006.176.07:40:11.39#ibcon#end of sib2, iclass 7, count 2 2006.176.07:40:11.39#ibcon#*mode == 0, iclass 7, count 2 2006.176.07:40:11.39#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.07:40:11.39#ibcon#[27=AT03-04\r\n] 2006.176.07:40:11.39#ibcon#*before write, iclass 7, count 2 2006.176.07:40:11.39#ibcon#enter sib2, iclass 7, count 2 2006.176.07:40:11.39#ibcon#flushed, iclass 7, count 2 2006.176.07:40:11.39#ibcon#about to write, iclass 7, count 2 2006.176.07:40:11.39#ibcon#wrote, iclass 7, count 2 2006.176.07:40:11.39#ibcon#about to read 3, iclass 7, count 2 2006.176.07:40:11.42#ibcon#read 3, iclass 7, count 2 2006.176.07:40:11.42#ibcon#about to read 4, iclass 7, count 2 2006.176.07:40:11.42#ibcon#read 4, iclass 7, count 2 2006.176.07:40:11.42#ibcon#about to read 5, iclass 7, count 2 2006.176.07:40:11.42#ibcon#read 5, iclass 7, count 2 2006.176.07:40:11.42#ibcon#about to read 6, iclass 7, count 2 2006.176.07:40:11.42#ibcon#read 6, iclass 7, count 2 2006.176.07:40:11.42#ibcon#end of sib2, iclass 7, count 2 2006.176.07:40:11.42#ibcon#*after write, iclass 7, count 2 2006.176.07:40:11.42#ibcon#*before return 0, iclass 7, count 2 2006.176.07:40:11.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:11.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:40:11.42#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.07:40:11.42#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:11.42#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:11.54#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:11.54#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:11.54#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:40:11.54#ibcon#first serial, iclass 7, count 0 2006.176.07:40:11.54#ibcon#enter sib2, iclass 7, count 0 2006.176.07:40:11.54#ibcon#flushed, iclass 7, count 0 2006.176.07:40:11.54#ibcon#about to write, iclass 7, count 0 2006.176.07:40:11.54#ibcon#wrote, iclass 7, count 0 2006.176.07:40:11.54#ibcon#about to read 3, iclass 7, count 0 2006.176.07:40:11.56#ibcon#read 3, iclass 7, count 0 2006.176.07:40:11.56#ibcon#about to read 4, iclass 7, count 0 2006.176.07:40:11.56#ibcon#read 4, iclass 7, count 0 2006.176.07:40:11.56#ibcon#about to read 5, iclass 7, count 0 2006.176.07:40:11.56#ibcon#read 5, iclass 7, count 0 2006.176.07:40:11.56#ibcon#about to read 6, iclass 7, count 0 2006.176.07:40:11.56#ibcon#read 6, iclass 7, count 0 2006.176.07:40:11.56#ibcon#end of sib2, iclass 7, count 0 2006.176.07:40:11.56#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:40:11.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:40:11.56#ibcon#[27=USB\r\n] 2006.176.07:40:11.56#ibcon#*before write, iclass 7, count 0 2006.176.07:40:11.56#ibcon#enter sib2, iclass 7, count 0 2006.176.07:40:11.56#ibcon#flushed, iclass 7, count 0 2006.176.07:40:11.56#ibcon#about to write, iclass 7, count 0 2006.176.07:40:11.56#ibcon#wrote, iclass 7, count 0 2006.176.07:40:11.56#ibcon#about to read 3, iclass 7, count 0 2006.176.07:40:11.59#ibcon#read 3, iclass 7, count 0 2006.176.07:40:11.59#ibcon#about to read 4, iclass 7, count 0 2006.176.07:40:11.59#ibcon#read 4, iclass 7, count 0 2006.176.07:40:11.59#ibcon#about to read 5, iclass 7, count 0 2006.176.07:40:11.59#ibcon#read 5, iclass 7, count 0 2006.176.07:40:11.59#ibcon#about to read 6, iclass 7, count 0 2006.176.07:40:11.59#ibcon#read 6, iclass 7, count 0 2006.176.07:40:11.59#ibcon#end of sib2, iclass 7, count 0 2006.176.07:40:11.59#ibcon#*after write, iclass 7, count 0 2006.176.07:40:11.59#ibcon#*before return 0, iclass 7, count 0 2006.176.07:40:11.59#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:11.59#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:40:11.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:40:11.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:40:11.59$vc4f8/vblo=4,712.99 2006.176.07:40:11.59#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.07:40:11.59#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.07:40:11.59#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:11.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:11.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:11.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:11.59#ibcon#enter wrdev, iclass 11, count 0 2006.176.07:40:11.59#ibcon#first serial, iclass 11, count 0 2006.176.07:40:11.59#ibcon#enter sib2, iclass 11, count 0 2006.176.07:40:11.59#ibcon#flushed, iclass 11, count 0 2006.176.07:40:11.59#ibcon#about to write, iclass 11, count 0 2006.176.07:40:11.59#ibcon#wrote, iclass 11, count 0 2006.176.07:40:11.59#ibcon#about to read 3, iclass 11, count 0 2006.176.07:40:11.61#ibcon#read 3, iclass 11, count 0 2006.176.07:40:11.61#ibcon#about to read 4, iclass 11, count 0 2006.176.07:40:11.61#ibcon#read 4, iclass 11, count 0 2006.176.07:40:11.61#ibcon#about to read 5, iclass 11, count 0 2006.176.07:40:11.61#ibcon#read 5, iclass 11, count 0 2006.176.07:40:11.61#ibcon#about to read 6, iclass 11, count 0 2006.176.07:40:11.61#ibcon#read 6, iclass 11, count 0 2006.176.07:40:11.61#ibcon#end of sib2, iclass 11, count 0 2006.176.07:40:11.61#ibcon#*mode == 0, iclass 11, count 0 2006.176.07:40:11.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.07:40:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:40:11.61#ibcon#*before write, iclass 11, count 0 2006.176.07:40:11.61#ibcon#enter sib2, iclass 11, count 0 2006.176.07:40:11.61#ibcon#flushed, iclass 11, count 0 2006.176.07:40:11.61#ibcon#about to write, iclass 11, count 0 2006.176.07:40:11.61#ibcon#wrote, iclass 11, count 0 2006.176.07:40:11.61#ibcon#about to read 3, iclass 11, count 0 2006.176.07:40:11.65#ibcon#read 3, iclass 11, count 0 2006.176.07:40:11.65#ibcon#about to read 4, iclass 11, count 0 2006.176.07:40:11.65#ibcon#read 4, iclass 11, count 0 2006.176.07:40:11.65#ibcon#about to read 5, iclass 11, count 0 2006.176.07:40:11.65#ibcon#read 5, iclass 11, count 0 2006.176.07:40:11.65#ibcon#about to read 6, iclass 11, count 0 2006.176.07:40:11.65#ibcon#read 6, iclass 11, count 0 2006.176.07:40:11.65#ibcon#end of sib2, iclass 11, count 0 2006.176.07:40:11.65#ibcon#*after write, iclass 11, count 0 2006.176.07:40:11.65#ibcon#*before return 0, iclass 11, count 0 2006.176.07:40:11.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:11.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:40:11.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.07:40:11.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.07:40:11.65$vc4f8/vb=4,4 2006.176.07:40:11.65#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.07:40:11.65#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.07:40:11.65#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:11.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:11.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:11.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:11.71#ibcon#enter wrdev, iclass 13, count 2 2006.176.07:40:11.71#ibcon#first serial, iclass 13, count 2 2006.176.07:40:11.71#ibcon#enter sib2, iclass 13, count 2 2006.176.07:40:11.71#ibcon#flushed, iclass 13, count 2 2006.176.07:40:11.71#ibcon#about to write, iclass 13, count 2 2006.176.07:40:11.71#ibcon#wrote, iclass 13, count 2 2006.176.07:40:11.71#ibcon#about to read 3, iclass 13, count 2 2006.176.07:40:11.73#ibcon#read 3, iclass 13, count 2 2006.176.07:40:11.73#ibcon#about to read 4, iclass 13, count 2 2006.176.07:40:11.73#ibcon#read 4, iclass 13, count 2 2006.176.07:40:11.73#ibcon#about to read 5, iclass 13, count 2 2006.176.07:40:11.73#ibcon#read 5, iclass 13, count 2 2006.176.07:40:11.73#ibcon#about to read 6, iclass 13, count 2 2006.176.07:40:11.73#ibcon#read 6, iclass 13, count 2 2006.176.07:40:11.73#ibcon#end of sib2, iclass 13, count 2 2006.176.07:40:11.73#ibcon#*mode == 0, iclass 13, count 2 2006.176.07:40:11.73#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.07:40:11.73#ibcon#[27=AT04-04\r\n] 2006.176.07:40:11.73#ibcon#*before write, iclass 13, count 2 2006.176.07:40:11.73#ibcon#enter sib2, iclass 13, count 2 2006.176.07:40:11.73#ibcon#flushed, iclass 13, count 2 2006.176.07:40:11.73#ibcon#about to write, iclass 13, count 2 2006.176.07:40:11.73#ibcon#wrote, iclass 13, count 2 2006.176.07:40:11.73#ibcon#about to read 3, iclass 13, count 2 2006.176.07:40:11.76#ibcon#read 3, iclass 13, count 2 2006.176.07:40:11.76#ibcon#about to read 4, iclass 13, count 2 2006.176.07:40:11.76#ibcon#read 4, iclass 13, count 2 2006.176.07:40:11.76#ibcon#about to read 5, iclass 13, count 2 2006.176.07:40:11.76#ibcon#read 5, iclass 13, count 2 2006.176.07:40:11.76#ibcon#about to read 6, iclass 13, count 2 2006.176.07:40:11.76#ibcon#read 6, iclass 13, count 2 2006.176.07:40:11.76#ibcon#end of sib2, iclass 13, count 2 2006.176.07:40:11.76#ibcon#*after write, iclass 13, count 2 2006.176.07:40:11.76#ibcon#*before return 0, iclass 13, count 2 2006.176.07:40:11.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:11.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:40:11.76#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.07:40:11.76#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:11.76#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:11.88#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:11.88#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:11.88#ibcon#enter wrdev, iclass 13, count 0 2006.176.07:40:11.88#ibcon#first serial, iclass 13, count 0 2006.176.07:40:11.88#ibcon#enter sib2, iclass 13, count 0 2006.176.07:40:11.88#ibcon#flushed, iclass 13, count 0 2006.176.07:40:11.88#ibcon#about to write, iclass 13, count 0 2006.176.07:40:11.88#ibcon#wrote, iclass 13, count 0 2006.176.07:40:11.88#ibcon#about to read 3, iclass 13, count 0 2006.176.07:40:11.90#ibcon#read 3, iclass 13, count 0 2006.176.07:40:11.90#ibcon#about to read 4, iclass 13, count 0 2006.176.07:40:11.90#ibcon#read 4, iclass 13, count 0 2006.176.07:40:11.90#ibcon#about to read 5, iclass 13, count 0 2006.176.07:40:11.90#ibcon#read 5, iclass 13, count 0 2006.176.07:40:11.90#ibcon#about to read 6, iclass 13, count 0 2006.176.07:40:11.90#ibcon#read 6, iclass 13, count 0 2006.176.07:40:11.90#ibcon#end of sib2, iclass 13, count 0 2006.176.07:40:11.90#ibcon#*mode == 0, iclass 13, count 0 2006.176.07:40:11.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.07:40:11.90#ibcon#[27=USB\r\n] 2006.176.07:40:11.90#ibcon#*before write, iclass 13, count 0 2006.176.07:40:11.90#ibcon#enter sib2, iclass 13, count 0 2006.176.07:40:11.90#ibcon#flushed, iclass 13, count 0 2006.176.07:40:11.90#ibcon#about to write, iclass 13, count 0 2006.176.07:40:11.90#ibcon#wrote, iclass 13, count 0 2006.176.07:40:11.90#ibcon#about to read 3, iclass 13, count 0 2006.176.07:40:11.93#ibcon#read 3, iclass 13, count 0 2006.176.07:40:11.93#ibcon#about to read 4, iclass 13, count 0 2006.176.07:40:11.93#ibcon#read 4, iclass 13, count 0 2006.176.07:40:11.93#ibcon#about to read 5, iclass 13, count 0 2006.176.07:40:11.93#ibcon#read 5, iclass 13, count 0 2006.176.07:40:11.93#ibcon#about to read 6, iclass 13, count 0 2006.176.07:40:11.93#ibcon#read 6, iclass 13, count 0 2006.176.07:40:11.93#ibcon#end of sib2, iclass 13, count 0 2006.176.07:40:11.93#ibcon#*after write, iclass 13, count 0 2006.176.07:40:11.93#ibcon#*before return 0, iclass 13, count 0 2006.176.07:40:11.93#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:11.93#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:40:11.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.07:40:11.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.07:40:11.93$vc4f8/vblo=5,744.99 2006.176.07:40:11.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.07:40:11.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.07:40:11.93#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:11.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:11.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:11.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:11.94#ibcon#enter wrdev, iclass 15, count 0 2006.176.07:40:11.94#ibcon#first serial, iclass 15, count 0 2006.176.07:40:11.94#ibcon#enter sib2, iclass 15, count 0 2006.176.07:40:11.94#ibcon#flushed, iclass 15, count 0 2006.176.07:40:11.94#ibcon#about to write, iclass 15, count 0 2006.176.07:40:11.94#ibcon#wrote, iclass 15, count 0 2006.176.07:40:11.94#ibcon#about to read 3, iclass 15, count 0 2006.176.07:40:11.95#ibcon#read 3, iclass 15, count 0 2006.176.07:40:11.95#ibcon#about to read 4, iclass 15, count 0 2006.176.07:40:11.95#ibcon#read 4, iclass 15, count 0 2006.176.07:40:11.95#ibcon#about to read 5, iclass 15, count 0 2006.176.07:40:11.95#ibcon#read 5, iclass 15, count 0 2006.176.07:40:11.95#ibcon#about to read 6, iclass 15, count 0 2006.176.07:40:11.95#ibcon#read 6, iclass 15, count 0 2006.176.07:40:11.95#ibcon#end of sib2, iclass 15, count 0 2006.176.07:40:11.95#ibcon#*mode == 0, iclass 15, count 0 2006.176.07:40:11.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.07:40:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:40:11.95#ibcon#*before write, iclass 15, count 0 2006.176.07:40:11.95#ibcon#enter sib2, iclass 15, count 0 2006.176.07:40:11.95#ibcon#flushed, iclass 15, count 0 2006.176.07:40:11.95#ibcon#about to write, iclass 15, count 0 2006.176.07:40:11.95#ibcon#wrote, iclass 15, count 0 2006.176.07:40:11.95#ibcon#about to read 3, iclass 15, count 0 2006.176.07:40:11.99#ibcon#read 3, iclass 15, count 0 2006.176.07:40:11.99#ibcon#about to read 4, iclass 15, count 0 2006.176.07:40:11.99#ibcon#read 4, iclass 15, count 0 2006.176.07:40:11.99#ibcon#about to read 5, iclass 15, count 0 2006.176.07:40:11.99#ibcon#read 5, iclass 15, count 0 2006.176.07:40:11.99#ibcon#about to read 6, iclass 15, count 0 2006.176.07:40:11.99#ibcon#read 6, iclass 15, count 0 2006.176.07:40:11.99#ibcon#end of sib2, iclass 15, count 0 2006.176.07:40:11.99#ibcon#*after write, iclass 15, count 0 2006.176.07:40:11.99#ibcon#*before return 0, iclass 15, count 0 2006.176.07:40:11.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:11.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:40:11.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.07:40:11.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.07:40:11.99$vc4f8/vb=5,4 2006.176.07:40:11.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.176.07:40:11.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.176.07:40:11.99#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:11.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:12.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:12.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:12.05#ibcon#enter wrdev, iclass 17, count 2 2006.176.07:40:12.05#ibcon#first serial, iclass 17, count 2 2006.176.07:40:12.05#ibcon#enter sib2, iclass 17, count 2 2006.176.07:40:12.05#ibcon#flushed, iclass 17, count 2 2006.176.07:40:12.05#ibcon#about to write, iclass 17, count 2 2006.176.07:40:12.05#ibcon#wrote, iclass 17, count 2 2006.176.07:40:12.05#ibcon#about to read 3, iclass 17, count 2 2006.176.07:40:12.07#ibcon#read 3, iclass 17, count 2 2006.176.07:40:12.07#ibcon#about to read 4, iclass 17, count 2 2006.176.07:40:12.07#ibcon#read 4, iclass 17, count 2 2006.176.07:40:12.07#ibcon#about to read 5, iclass 17, count 2 2006.176.07:40:12.07#ibcon#read 5, iclass 17, count 2 2006.176.07:40:12.07#ibcon#about to read 6, iclass 17, count 2 2006.176.07:40:12.07#ibcon#read 6, iclass 17, count 2 2006.176.07:40:12.07#ibcon#end of sib2, iclass 17, count 2 2006.176.07:40:12.07#ibcon#*mode == 0, iclass 17, count 2 2006.176.07:40:12.07#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.176.07:40:12.07#ibcon#[27=AT05-04\r\n] 2006.176.07:40:12.07#ibcon#*before write, iclass 17, count 2 2006.176.07:40:12.07#ibcon#enter sib2, iclass 17, count 2 2006.176.07:40:12.07#ibcon#flushed, iclass 17, count 2 2006.176.07:40:12.07#ibcon#about to write, iclass 17, count 2 2006.176.07:40:12.07#ibcon#wrote, iclass 17, count 2 2006.176.07:40:12.07#ibcon#about to read 3, iclass 17, count 2 2006.176.07:40:12.10#ibcon#read 3, iclass 17, count 2 2006.176.07:40:12.10#ibcon#about to read 4, iclass 17, count 2 2006.176.07:40:12.10#ibcon#read 4, iclass 17, count 2 2006.176.07:40:12.10#ibcon#about to read 5, iclass 17, count 2 2006.176.07:40:12.10#ibcon#read 5, iclass 17, count 2 2006.176.07:40:12.10#ibcon#about to read 6, iclass 17, count 2 2006.176.07:40:12.10#ibcon#read 6, iclass 17, count 2 2006.176.07:40:12.10#ibcon#end of sib2, iclass 17, count 2 2006.176.07:40:12.10#ibcon#*after write, iclass 17, count 2 2006.176.07:40:12.10#ibcon#*before return 0, iclass 17, count 2 2006.176.07:40:12.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:12.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:40:12.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.176.07:40:12.10#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:12.10#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:12.22#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:12.22#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:12.22#ibcon#enter wrdev, iclass 17, count 0 2006.176.07:40:12.22#ibcon#first serial, iclass 17, count 0 2006.176.07:40:12.22#ibcon#enter sib2, iclass 17, count 0 2006.176.07:40:12.22#ibcon#flushed, iclass 17, count 0 2006.176.07:40:12.22#ibcon#about to write, iclass 17, count 0 2006.176.07:40:12.22#ibcon#wrote, iclass 17, count 0 2006.176.07:40:12.22#ibcon#about to read 3, iclass 17, count 0 2006.176.07:40:12.24#ibcon#read 3, iclass 17, count 0 2006.176.07:40:12.24#ibcon#about to read 4, iclass 17, count 0 2006.176.07:40:12.24#ibcon#read 4, iclass 17, count 0 2006.176.07:40:12.24#ibcon#about to read 5, iclass 17, count 0 2006.176.07:40:12.24#ibcon#read 5, iclass 17, count 0 2006.176.07:40:12.24#ibcon#about to read 6, iclass 17, count 0 2006.176.07:40:12.24#ibcon#read 6, iclass 17, count 0 2006.176.07:40:12.24#ibcon#end of sib2, iclass 17, count 0 2006.176.07:40:12.24#ibcon#*mode == 0, iclass 17, count 0 2006.176.07:40:12.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.07:40:12.24#ibcon#[27=USB\r\n] 2006.176.07:40:12.24#ibcon#*before write, iclass 17, count 0 2006.176.07:40:12.24#ibcon#enter sib2, iclass 17, count 0 2006.176.07:40:12.24#ibcon#flushed, iclass 17, count 0 2006.176.07:40:12.24#ibcon#about to write, iclass 17, count 0 2006.176.07:40:12.24#ibcon#wrote, iclass 17, count 0 2006.176.07:40:12.24#ibcon#about to read 3, iclass 17, count 0 2006.176.07:40:12.27#ibcon#read 3, iclass 17, count 0 2006.176.07:40:12.27#ibcon#about to read 4, iclass 17, count 0 2006.176.07:40:12.27#ibcon#read 4, iclass 17, count 0 2006.176.07:40:12.27#ibcon#about to read 5, iclass 17, count 0 2006.176.07:40:12.27#ibcon#read 5, iclass 17, count 0 2006.176.07:40:12.27#ibcon#about to read 6, iclass 17, count 0 2006.176.07:40:12.27#ibcon#read 6, iclass 17, count 0 2006.176.07:40:12.27#ibcon#end of sib2, iclass 17, count 0 2006.176.07:40:12.27#ibcon#*after write, iclass 17, count 0 2006.176.07:40:12.27#ibcon#*before return 0, iclass 17, count 0 2006.176.07:40:12.27#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:12.27#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:40:12.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.07:40:12.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.07:40:12.27$vc4f8/vblo=6,752.99 2006.176.07:40:12.27#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.176.07:40:12.27#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.176.07:40:12.27#ibcon#ireg 17 cls_cnt 0 2006.176.07:40:12.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:12.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:12.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:12.27#ibcon#enter wrdev, iclass 19, count 0 2006.176.07:40:12.27#ibcon#first serial, iclass 19, count 0 2006.176.07:40:12.27#ibcon#enter sib2, iclass 19, count 0 2006.176.07:40:12.27#ibcon#flushed, iclass 19, count 0 2006.176.07:40:12.27#ibcon#about to write, iclass 19, count 0 2006.176.07:40:12.27#ibcon#wrote, iclass 19, count 0 2006.176.07:40:12.27#ibcon#about to read 3, iclass 19, count 0 2006.176.07:40:12.29#ibcon#read 3, iclass 19, count 0 2006.176.07:40:12.29#ibcon#about to read 4, iclass 19, count 0 2006.176.07:40:12.29#ibcon#read 4, iclass 19, count 0 2006.176.07:40:12.29#ibcon#about to read 5, iclass 19, count 0 2006.176.07:40:12.29#ibcon#read 5, iclass 19, count 0 2006.176.07:40:12.29#ibcon#about to read 6, iclass 19, count 0 2006.176.07:40:12.29#ibcon#read 6, iclass 19, count 0 2006.176.07:40:12.29#ibcon#end of sib2, iclass 19, count 0 2006.176.07:40:12.29#ibcon#*mode == 0, iclass 19, count 0 2006.176.07:40:12.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.07:40:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:40:12.29#ibcon#*before write, iclass 19, count 0 2006.176.07:40:12.29#ibcon#enter sib2, iclass 19, count 0 2006.176.07:40:12.29#ibcon#flushed, iclass 19, count 0 2006.176.07:40:12.29#ibcon#about to write, iclass 19, count 0 2006.176.07:40:12.29#ibcon#wrote, iclass 19, count 0 2006.176.07:40:12.29#ibcon#about to read 3, iclass 19, count 0 2006.176.07:40:12.33#ibcon#read 3, iclass 19, count 0 2006.176.07:40:12.33#ibcon#about to read 4, iclass 19, count 0 2006.176.07:40:12.33#ibcon#read 4, iclass 19, count 0 2006.176.07:40:12.33#ibcon#about to read 5, iclass 19, count 0 2006.176.07:40:12.33#ibcon#read 5, iclass 19, count 0 2006.176.07:40:12.33#ibcon#about to read 6, iclass 19, count 0 2006.176.07:40:12.33#ibcon#read 6, iclass 19, count 0 2006.176.07:40:12.33#ibcon#end of sib2, iclass 19, count 0 2006.176.07:40:12.33#ibcon#*after write, iclass 19, count 0 2006.176.07:40:12.33#ibcon#*before return 0, iclass 19, count 0 2006.176.07:40:12.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:12.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:40:12.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.07:40:12.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.07:40:12.33$vc4f8/vb=6,4 2006.176.07:40:12.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.176.07:40:12.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.176.07:40:12.33#ibcon#ireg 11 cls_cnt 2 2006.176.07:40:12.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:12.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:12.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:12.39#ibcon#enter wrdev, iclass 21, count 2 2006.176.07:40:12.39#ibcon#first serial, iclass 21, count 2 2006.176.07:40:12.39#ibcon#enter sib2, iclass 21, count 2 2006.176.07:40:12.39#ibcon#flushed, iclass 21, count 2 2006.176.07:40:12.39#ibcon#about to write, iclass 21, count 2 2006.176.07:40:12.39#ibcon#wrote, iclass 21, count 2 2006.176.07:40:12.39#ibcon#about to read 3, iclass 21, count 2 2006.176.07:40:12.41#ibcon#read 3, iclass 21, count 2 2006.176.07:40:12.41#ibcon#about to read 4, iclass 21, count 2 2006.176.07:40:12.41#ibcon#read 4, iclass 21, count 2 2006.176.07:40:12.41#ibcon#about to read 5, iclass 21, count 2 2006.176.07:40:12.41#ibcon#read 5, iclass 21, count 2 2006.176.07:40:12.41#ibcon#about to read 6, iclass 21, count 2 2006.176.07:40:12.41#ibcon#read 6, iclass 21, count 2 2006.176.07:40:12.41#ibcon#end of sib2, iclass 21, count 2 2006.176.07:40:12.41#ibcon#*mode == 0, iclass 21, count 2 2006.176.07:40:12.41#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.176.07:40:12.41#ibcon#[27=AT06-04\r\n] 2006.176.07:40:12.41#ibcon#*before write, iclass 21, count 2 2006.176.07:40:12.41#ibcon#enter sib2, iclass 21, count 2 2006.176.07:40:12.41#ibcon#flushed, iclass 21, count 2 2006.176.07:40:12.41#ibcon#about to write, iclass 21, count 2 2006.176.07:40:12.41#ibcon#wrote, iclass 21, count 2 2006.176.07:40:12.41#ibcon#about to read 3, iclass 21, count 2 2006.176.07:40:12.44#ibcon#read 3, iclass 21, count 2 2006.176.07:40:12.44#ibcon#about to read 4, iclass 21, count 2 2006.176.07:40:12.44#ibcon#read 4, iclass 21, count 2 2006.176.07:40:12.44#ibcon#about to read 5, iclass 21, count 2 2006.176.07:40:12.44#ibcon#read 5, iclass 21, count 2 2006.176.07:40:12.44#ibcon#about to read 6, iclass 21, count 2 2006.176.07:40:12.44#ibcon#read 6, iclass 21, count 2 2006.176.07:40:12.44#ibcon#end of sib2, iclass 21, count 2 2006.176.07:40:12.44#ibcon#*after write, iclass 21, count 2 2006.176.07:40:12.44#ibcon#*before return 0, iclass 21, count 2 2006.176.07:40:12.44#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:12.44#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:40:12.44#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.176.07:40:12.44#ibcon#ireg 7 cls_cnt 0 2006.176.07:40:12.44#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:12.56#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:12.56#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:12.56#ibcon#enter wrdev, iclass 21, count 0 2006.176.07:40:12.56#ibcon#first serial, iclass 21, count 0 2006.176.07:40:12.56#ibcon#enter sib2, iclass 21, count 0 2006.176.07:40:12.56#ibcon#flushed, iclass 21, count 0 2006.176.07:40:12.56#ibcon#about to write, iclass 21, count 0 2006.176.07:40:12.56#ibcon#wrote, iclass 21, count 0 2006.176.07:40:12.56#ibcon#about to read 3, iclass 21, count 0 2006.176.07:40:12.58#ibcon#read 3, iclass 21, count 0 2006.176.07:40:12.58#ibcon#about to read 4, iclass 21, count 0 2006.176.07:40:12.58#ibcon#read 4, iclass 21, count 0 2006.176.07:40:12.58#ibcon#about to read 5, iclass 21, count 0 2006.176.07:40:12.58#ibcon#read 5, iclass 21, count 0 2006.176.07:40:12.58#ibcon#about to read 6, iclass 21, count 0 2006.176.07:40:12.58#ibcon#read 6, iclass 21, count 0 2006.176.07:40:12.58#ibcon#end of sib2, iclass 21, count 0 2006.176.07:40:12.58#ibcon#*mode == 0, iclass 21, count 0 2006.176.07:40:12.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.07:40:12.58#ibcon#[27=USB\r\n] 2006.176.07:40:12.58#ibcon#*before write, iclass 21, count 0 2006.176.07:40:12.58#ibcon#enter sib2, iclass 21, count 0 2006.176.07:40:12.58#ibcon#flushed, iclass 21, count 0 2006.176.07:40:12.58#ibcon#about to write, iclass 21, count 0 2006.176.07:40:12.58#ibcon#wrote, iclass 21, count 0 2006.176.07:40:12.58#ibcon#about to read 3, iclass 21, count 0 2006.176.07:40:12.61#ibcon#read 3, iclass 21, count 0 2006.176.07:40:12.61#ibcon#about to read 4, iclass 21, count 0 2006.176.07:40:12.61#ibcon#read 4, iclass 21, count 0 2006.176.07:40:12.61#ibcon#about to read 5, iclass 21, count 0 2006.176.07:40:12.61#ibcon#read 5, iclass 21, count 0 2006.176.07:40:12.61#ibcon#about to read 6, iclass 21, count 0 2006.176.07:40:12.61#ibcon#read 6, iclass 21, count 0 2006.176.07:40:12.61#ibcon#end of sib2, iclass 21, count 0 2006.176.07:40:12.61#ibcon#*after write, iclass 21, count 0 2006.176.07:40:12.61#ibcon#*before return 0, iclass 21, count 0 2006.176.07:40:12.61#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:12.61#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:40:12.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.07:40:12.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.07:40:12.61$vc4f8/vabw=wide 2006.176.07:40:12.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.07:40:12.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.07:40:12.61#ibcon#ireg 8 cls_cnt 0 2006.176.07:40:12.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:12.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:12.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:12.61#ibcon#enter wrdev, iclass 23, count 0 2006.176.07:40:12.61#ibcon#first serial, iclass 23, count 0 2006.176.07:40:12.61#ibcon#enter sib2, iclass 23, count 0 2006.176.07:40:12.61#ibcon#flushed, iclass 23, count 0 2006.176.07:40:12.61#ibcon#about to write, iclass 23, count 0 2006.176.07:40:12.61#ibcon#wrote, iclass 23, count 0 2006.176.07:40:12.61#ibcon#about to read 3, iclass 23, count 0 2006.176.07:40:12.63#ibcon#read 3, iclass 23, count 0 2006.176.07:40:12.63#ibcon#about to read 4, iclass 23, count 0 2006.176.07:40:12.63#ibcon#read 4, iclass 23, count 0 2006.176.07:40:12.63#ibcon#about to read 5, iclass 23, count 0 2006.176.07:40:12.63#ibcon#read 5, iclass 23, count 0 2006.176.07:40:12.63#ibcon#about to read 6, iclass 23, count 0 2006.176.07:40:12.63#ibcon#read 6, iclass 23, count 0 2006.176.07:40:12.63#ibcon#end of sib2, iclass 23, count 0 2006.176.07:40:12.63#ibcon#*mode == 0, iclass 23, count 0 2006.176.07:40:12.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.07:40:12.63#ibcon#[25=BW32\r\n] 2006.176.07:40:12.63#ibcon#*before write, iclass 23, count 0 2006.176.07:40:12.63#ibcon#enter sib2, iclass 23, count 0 2006.176.07:40:12.63#ibcon#flushed, iclass 23, count 0 2006.176.07:40:12.63#ibcon#about to write, iclass 23, count 0 2006.176.07:40:12.63#ibcon#wrote, iclass 23, count 0 2006.176.07:40:12.63#ibcon#about to read 3, iclass 23, count 0 2006.176.07:40:12.66#ibcon#read 3, iclass 23, count 0 2006.176.07:40:12.66#ibcon#about to read 4, iclass 23, count 0 2006.176.07:40:12.66#ibcon#read 4, iclass 23, count 0 2006.176.07:40:12.66#ibcon#about to read 5, iclass 23, count 0 2006.176.07:40:12.66#ibcon#read 5, iclass 23, count 0 2006.176.07:40:12.66#ibcon#about to read 6, iclass 23, count 0 2006.176.07:40:12.66#ibcon#read 6, iclass 23, count 0 2006.176.07:40:12.66#ibcon#end of sib2, iclass 23, count 0 2006.176.07:40:12.66#ibcon#*after write, iclass 23, count 0 2006.176.07:40:12.66#ibcon#*before return 0, iclass 23, count 0 2006.176.07:40:12.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:12.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:40:12.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.07:40:12.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.07:40:12.66$vc4f8/vbbw=wide 2006.176.07:40:12.66#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.07:40:12.66#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.07:40:12.66#ibcon#ireg 8 cls_cnt 0 2006.176.07:40:12.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:40:12.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:40:12.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:40:12.73#ibcon#enter wrdev, iclass 25, count 0 2006.176.07:40:12.73#ibcon#first serial, iclass 25, count 0 2006.176.07:40:12.73#ibcon#enter sib2, iclass 25, count 0 2006.176.07:40:12.73#ibcon#flushed, iclass 25, count 0 2006.176.07:40:12.73#ibcon#about to write, iclass 25, count 0 2006.176.07:40:12.73#ibcon#wrote, iclass 25, count 0 2006.176.07:40:12.73#ibcon#about to read 3, iclass 25, count 0 2006.176.07:40:12.75#ibcon#read 3, iclass 25, count 0 2006.176.07:40:12.75#ibcon#about to read 4, iclass 25, count 0 2006.176.07:40:12.75#ibcon#read 4, iclass 25, count 0 2006.176.07:40:12.75#ibcon#about to read 5, iclass 25, count 0 2006.176.07:40:12.75#ibcon#read 5, iclass 25, count 0 2006.176.07:40:12.75#ibcon#about to read 6, iclass 25, count 0 2006.176.07:40:12.75#ibcon#read 6, iclass 25, count 0 2006.176.07:40:12.75#ibcon#end of sib2, iclass 25, count 0 2006.176.07:40:12.75#ibcon#*mode == 0, iclass 25, count 0 2006.176.07:40:12.75#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.07:40:12.75#ibcon#[27=BW32\r\n] 2006.176.07:40:12.75#ibcon#*before write, iclass 25, count 0 2006.176.07:40:12.75#ibcon#enter sib2, iclass 25, count 0 2006.176.07:40:12.75#ibcon#flushed, iclass 25, count 0 2006.176.07:40:12.75#ibcon#about to write, iclass 25, count 0 2006.176.07:40:12.75#ibcon#wrote, iclass 25, count 0 2006.176.07:40:12.75#ibcon#about to read 3, iclass 25, count 0 2006.176.07:40:12.78#ibcon#read 3, iclass 25, count 0 2006.176.07:40:12.78#ibcon#about to read 4, iclass 25, count 0 2006.176.07:40:12.78#ibcon#read 4, iclass 25, count 0 2006.176.07:40:12.78#ibcon#about to read 5, iclass 25, count 0 2006.176.07:40:12.78#ibcon#read 5, iclass 25, count 0 2006.176.07:40:12.78#ibcon#about to read 6, iclass 25, count 0 2006.176.07:40:12.78#ibcon#read 6, iclass 25, count 0 2006.176.07:40:12.78#ibcon#end of sib2, iclass 25, count 0 2006.176.07:40:12.78#ibcon#*after write, iclass 25, count 0 2006.176.07:40:12.78#ibcon#*before return 0, iclass 25, count 0 2006.176.07:40:12.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:40:12.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:40:12.78#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.07:40:12.78#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.07:40:12.78$4f8m12a/ifd4f 2006.176.07:40:12.78$ifd4f/lo= 2006.176.07:40:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:40:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:40:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:40:12.78$ifd4f/patch= 2006.176.07:40:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:40:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:40:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:40:12.78$4f8m12a/"form=m,16.000,1:2 2006.176.07:40:12.78$4f8m12a/"tpicd 2006.176.07:40:12.78$4f8m12a/echo=off 2006.176.07:40:12.78$4f8m12a/xlog=off 2006.176.07:40:12.78:!2006.176.07:40:40 2006.176.07:40:24.14#trakl#Source acquired 2006.176.07:40:25.14#flagr#flagr/antenna,acquired 2006.176.07:40:40.00:preob 2006.176.07:40:41.14/onsource/TRACKING 2006.176.07:40:41.14:!2006.176.07:40:50 2006.176.07:40:50.00:data_valid=on 2006.176.07:40:50.00:midob 2006.176.07:40:50.13/onsource/TRACKING 2006.176.07:40:50.13/wx/23.93,1008.4,91 2006.176.07:40:50.22/cable/+6.4944E-03 2006.176.07:40:51.31/va/01,08,usb,yes,28,30 2006.176.07:40:51.31/va/02,07,usb,yes,29,30 2006.176.07:40:51.31/va/03,06,usb,yes,30,30 2006.176.07:40:51.31/va/04,07,usb,yes,29,32 2006.176.07:40:51.31/va/05,07,usb,yes,31,32 2006.176.07:40:51.31/va/06,06,usb,yes,30,30 2006.176.07:40:51.31/va/07,06,usb,yes,30,30 2006.176.07:40:51.31/va/08,06,usb,yes,32,32 2006.176.07:40:51.54/valo/01,532.99,yes,locked 2006.176.07:40:51.54/valo/02,572.99,yes,locked 2006.176.07:40:51.54/valo/03,672.99,yes,locked 2006.176.07:40:51.54/valo/04,832.99,yes,locked 2006.176.07:40:51.54/valo/05,652.99,yes,locked 2006.176.07:40:51.54/valo/06,772.99,yes,locked 2006.176.07:40:51.54/valo/07,832.99,yes,locked 2006.176.07:40:51.54/valo/08,852.99,yes,locked 2006.176.07:40:52.63/vb/01,04,usb,yes,29,27 2006.176.07:40:52.63/vb/02,04,usb,yes,30,32 2006.176.07:40:52.63/vb/03,04,usb,yes,27,30 2006.176.07:40:52.63/vb/04,04,usb,yes,28,28 2006.176.07:40:52.63/vb/05,04,usb,yes,26,30 2006.176.07:40:52.63/vb/06,04,usb,yes,27,30 2006.176.07:40:52.63/vb/07,04,usb,yes,29,29 2006.176.07:40:52.63/vb/08,04,usb,yes,27,30 2006.176.07:40:52.87/vblo/01,632.99,yes,locked 2006.176.07:40:52.87/vblo/02,640.99,yes,locked 2006.176.07:40:52.87/vblo/03,656.99,yes,locked 2006.176.07:40:52.87/vblo/04,712.99,yes,locked 2006.176.07:40:52.87/vblo/05,744.99,yes,locked 2006.176.07:40:52.87/vblo/06,752.99,yes,locked 2006.176.07:40:52.87/vblo/07,734.99,yes,locked 2006.176.07:40:52.87/vblo/08,744.99,yes,locked 2006.176.07:40:53.02/vabw/8 2006.176.07:40:53.17/vbbw/8 2006.176.07:40:53.26/xfe/off,on,14.5 2006.176.07:40:53.64/ifatt/23,28,28,28 2006.176.07:40:54.08/fmout-gps/S +3.74E-07 2006.176.07:40:54.12:!2006.176.07:41:50 2006.176.07:41:50.01:data_valid=off 2006.176.07:41:50.01:postob 2006.176.07:41:50.13/cable/+6.4912E-03 2006.176.07:41:50.13/wx/23.92,1008.4,91 2006.176.07:41:51.08/fmout-gps/S +3.74E-07 2006.176.07:41:51.08:scan_name=176-0743,k06176,130 2006.176.07:41:51.09:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.176.07:41:51.13#flagr#flagr/antenna,new-source 2006.176.07:41:52.13:checkk5 2006.176.07:41:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:41:52.87/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:41:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:41:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:41:54.01/chk_obsdata//k5ts1/T1760740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:41:54.37/chk_obsdata//k5ts2/T1760740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:41:54.75/chk_obsdata//k5ts3/T1760740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:41:55.14/chk_obsdata//k5ts4/T1760740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:41:55.83/k5log//k5ts1_log_newline 2006.176.07:41:56.53/k5log//k5ts2_log_newline 2006.176.07:41:57.22/k5log//k5ts3_log_newline 2006.176.07:41:57.91/k5log//k5ts4_log_newline 2006.176.07:41:57.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:41:57.93:4f8m12a=1 2006.176.07:41:57.93$4f8m12a/echo=on 2006.176.07:41:57.93$4f8m12a/pcalon 2006.176.07:41:57.93$pcalon/"no phase cal control is implemented here 2006.176.07:41:57.93$4f8m12a/"tpicd=stop 2006.176.07:41:57.93$4f8m12a/vc4f8 2006.176.07:41:57.93$vc4f8/valo=1,532.99 2006.176.07:41:57.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.07:41:57.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.07:41:57.93#ibcon#ireg 17 cls_cnt 0 2006.176.07:41:57.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:41:57.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:41:57.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:41:57.93#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:41:57.93#ibcon#first serial, iclass 36, count 0 2006.176.07:41:57.93#ibcon#enter sib2, iclass 36, count 0 2006.176.07:41:57.93#ibcon#flushed, iclass 36, count 0 2006.176.07:41:57.93#ibcon#about to write, iclass 36, count 0 2006.176.07:41:57.93#ibcon#wrote, iclass 36, count 0 2006.176.07:41:57.93#ibcon#about to read 3, iclass 36, count 0 2006.176.07:41:57.95#ibcon#read 3, iclass 36, count 0 2006.176.07:41:57.95#ibcon#about to read 4, iclass 36, count 0 2006.176.07:41:57.95#ibcon#read 4, iclass 36, count 0 2006.176.07:41:57.95#ibcon#about to read 5, iclass 36, count 0 2006.176.07:41:57.95#ibcon#read 5, iclass 36, count 0 2006.176.07:41:57.95#ibcon#about to read 6, iclass 36, count 0 2006.176.07:41:57.95#ibcon#read 6, iclass 36, count 0 2006.176.07:41:57.95#ibcon#end of sib2, iclass 36, count 0 2006.176.07:41:57.95#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:41:57.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:41:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:41:57.95#ibcon#*before write, iclass 36, count 0 2006.176.07:41:57.95#ibcon#enter sib2, iclass 36, count 0 2006.176.07:41:57.95#ibcon#flushed, iclass 36, count 0 2006.176.07:41:57.95#ibcon#about to write, iclass 36, count 0 2006.176.07:41:57.95#ibcon#wrote, iclass 36, count 0 2006.176.07:41:57.95#ibcon#about to read 3, iclass 36, count 0 2006.176.07:41:58.00#ibcon#read 3, iclass 36, count 0 2006.176.07:41:58.00#ibcon#about to read 4, iclass 36, count 0 2006.176.07:41:58.00#ibcon#read 4, iclass 36, count 0 2006.176.07:41:58.00#ibcon#about to read 5, iclass 36, count 0 2006.176.07:41:58.00#ibcon#read 5, iclass 36, count 0 2006.176.07:41:58.00#ibcon#about to read 6, iclass 36, count 0 2006.176.07:41:58.00#ibcon#read 6, iclass 36, count 0 2006.176.07:41:58.00#ibcon#end of sib2, iclass 36, count 0 2006.176.07:41:58.00#ibcon#*after write, iclass 36, count 0 2006.176.07:41:58.00#ibcon#*before return 0, iclass 36, count 0 2006.176.07:41:58.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:41:58.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:41:58.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:41:58.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:41:58.00$vc4f8/va=1,8 2006.176.07:41:58.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.07:41:58.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.07:41:58.00#ibcon#ireg 11 cls_cnt 2 2006.176.07:41:58.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:41:58.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:41:58.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:41:58.00#ibcon#enter wrdev, iclass 38, count 2 2006.176.07:41:58.00#ibcon#first serial, iclass 38, count 2 2006.176.07:41:58.00#ibcon#enter sib2, iclass 38, count 2 2006.176.07:41:58.00#ibcon#flushed, iclass 38, count 2 2006.176.07:41:58.00#ibcon#about to write, iclass 38, count 2 2006.176.07:41:58.00#ibcon#wrote, iclass 38, count 2 2006.176.07:41:58.00#ibcon#about to read 3, iclass 38, count 2 2006.176.07:41:58.02#ibcon#read 3, iclass 38, count 2 2006.176.07:41:58.02#ibcon#about to read 4, iclass 38, count 2 2006.176.07:41:58.02#ibcon#read 4, iclass 38, count 2 2006.176.07:41:58.02#ibcon#about to read 5, iclass 38, count 2 2006.176.07:41:58.02#ibcon#read 5, iclass 38, count 2 2006.176.07:41:58.02#ibcon#about to read 6, iclass 38, count 2 2006.176.07:41:58.02#ibcon#read 6, iclass 38, count 2 2006.176.07:41:58.02#ibcon#end of sib2, iclass 38, count 2 2006.176.07:41:58.02#ibcon#*mode == 0, iclass 38, count 2 2006.176.07:41:58.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.07:41:58.02#ibcon#[25=AT01-08\r\n] 2006.176.07:41:58.02#ibcon#*before write, iclass 38, count 2 2006.176.07:41:58.02#ibcon#enter sib2, iclass 38, count 2 2006.176.07:41:58.02#ibcon#flushed, iclass 38, count 2 2006.176.07:41:58.02#ibcon#about to write, iclass 38, count 2 2006.176.07:41:58.02#ibcon#wrote, iclass 38, count 2 2006.176.07:41:58.02#ibcon#about to read 3, iclass 38, count 2 2006.176.07:41:58.05#ibcon#read 3, iclass 38, count 2 2006.176.07:41:58.05#ibcon#about to read 4, iclass 38, count 2 2006.176.07:41:58.05#ibcon#read 4, iclass 38, count 2 2006.176.07:41:58.05#ibcon#about to read 5, iclass 38, count 2 2006.176.07:41:58.05#ibcon#read 5, iclass 38, count 2 2006.176.07:41:58.05#ibcon#about to read 6, iclass 38, count 2 2006.176.07:41:58.05#ibcon#read 6, iclass 38, count 2 2006.176.07:41:58.05#ibcon#end of sib2, iclass 38, count 2 2006.176.07:41:58.05#ibcon#*after write, iclass 38, count 2 2006.176.07:41:58.05#ibcon#*before return 0, iclass 38, count 2 2006.176.07:41:58.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:41:58.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:41:58.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.07:41:58.05#ibcon#ireg 7 cls_cnt 0 2006.176.07:41:58.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:41:58.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:41:58.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:41:58.17#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:41:58.17#ibcon#first serial, iclass 38, count 0 2006.176.07:41:58.17#ibcon#enter sib2, iclass 38, count 0 2006.176.07:41:58.17#ibcon#flushed, iclass 38, count 0 2006.176.07:41:58.17#ibcon#about to write, iclass 38, count 0 2006.176.07:41:58.17#ibcon#wrote, iclass 38, count 0 2006.176.07:41:58.17#ibcon#about to read 3, iclass 38, count 0 2006.176.07:41:58.19#ibcon#read 3, iclass 38, count 0 2006.176.07:41:58.19#ibcon#about to read 4, iclass 38, count 0 2006.176.07:41:58.19#ibcon#read 4, iclass 38, count 0 2006.176.07:41:58.19#ibcon#about to read 5, iclass 38, count 0 2006.176.07:41:58.19#ibcon#read 5, iclass 38, count 0 2006.176.07:41:58.19#ibcon#about to read 6, iclass 38, count 0 2006.176.07:41:58.19#ibcon#read 6, iclass 38, count 0 2006.176.07:41:58.19#ibcon#end of sib2, iclass 38, count 0 2006.176.07:41:58.19#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:41:58.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:41:58.19#ibcon#[25=USB\r\n] 2006.176.07:41:58.19#ibcon#*before write, iclass 38, count 0 2006.176.07:41:58.19#ibcon#enter sib2, iclass 38, count 0 2006.176.07:41:58.19#ibcon#flushed, iclass 38, count 0 2006.176.07:41:58.19#ibcon#about to write, iclass 38, count 0 2006.176.07:41:58.19#ibcon#wrote, iclass 38, count 0 2006.176.07:41:58.19#ibcon#about to read 3, iclass 38, count 0 2006.176.07:41:58.22#ibcon#read 3, iclass 38, count 0 2006.176.07:41:58.22#ibcon#about to read 4, iclass 38, count 0 2006.176.07:41:58.22#ibcon#read 4, iclass 38, count 0 2006.176.07:41:58.22#ibcon#about to read 5, iclass 38, count 0 2006.176.07:41:58.22#ibcon#read 5, iclass 38, count 0 2006.176.07:41:58.22#ibcon#about to read 6, iclass 38, count 0 2006.176.07:41:58.22#ibcon#read 6, iclass 38, count 0 2006.176.07:41:58.22#ibcon#end of sib2, iclass 38, count 0 2006.176.07:41:58.22#ibcon#*after write, iclass 38, count 0 2006.176.07:41:58.22#ibcon#*before return 0, iclass 38, count 0 2006.176.07:41:58.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:41:58.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:41:58.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:41:58.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:41:58.22$vc4f8/valo=2,572.99 2006.176.07:41:58.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.07:41:58.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.07:41:58.22#ibcon#ireg 17 cls_cnt 0 2006.176.07:41:58.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:41:58.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:41:58.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:41:58.22#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:41:58.22#ibcon#first serial, iclass 40, count 0 2006.176.07:41:58.22#ibcon#enter sib2, iclass 40, count 0 2006.176.07:41:58.22#ibcon#flushed, iclass 40, count 0 2006.176.07:41:58.22#ibcon#about to write, iclass 40, count 0 2006.176.07:41:58.22#ibcon#wrote, iclass 40, count 0 2006.176.07:41:58.22#ibcon#about to read 3, iclass 40, count 0 2006.176.07:41:58.24#ibcon#read 3, iclass 40, count 0 2006.176.07:41:58.24#ibcon#about to read 4, iclass 40, count 0 2006.176.07:41:58.24#ibcon#read 4, iclass 40, count 0 2006.176.07:41:58.24#ibcon#about to read 5, iclass 40, count 0 2006.176.07:41:58.24#ibcon#read 5, iclass 40, count 0 2006.176.07:41:58.24#ibcon#about to read 6, iclass 40, count 0 2006.176.07:41:58.24#ibcon#read 6, iclass 40, count 0 2006.176.07:41:58.24#ibcon#end of sib2, iclass 40, count 0 2006.176.07:41:58.24#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:41:58.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:41:58.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:41:58.24#ibcon#*before write, iclass 40, count 0 2006.176.07:41:58.24#ibcon#enter sib2, iclass 40, count 0 2006.176.07:41:58.24#ibcon#flushed, iclass 40, count 0 2006.176.07:41:58.24#ibcon#about to write, iclass 40, count 0 2006.176.07:41:58.24#ibcon#wrote, iclass 40, count 0 2006.176.07:41:58.24#ibcon#about to read 3, iclass 40, count 0 2006.176.07:41:58.28#ibcon#read 3, iclass 40, count 0 2006.176.07:41:58.28#ibcon#about to read 4, iclass 40, count 0 2006.176.07:41:58.28#ibcon#read 4, iclass 40, count 0 2006.176.07:41:58.28#ibcon#about to read 5, iclass 40, count 0 2006.176.07:41:58.28#ibcon#read 5, iclass 40, count 0 2006.176.07:41:58.28#ibcon#about to read 6, iclass 40, count 0 2006.176.07:41:58.28#ibcon#read 6, iclass 40, count 0 2006.176.07:41:58.28#ibcon#end of sib2, iclass 40, count 0 2006.176.07:41:58.28#ibcon#*after write, iclass 40, count 0 2006.176.07:41:58.28#ibcon#*before return 0, iclass 40, count 0 2006.176.07:41:58.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:41:58.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:41:58.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:41:58.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:41:58.28$vc4f8/va=2,7 2006.176.07:41:58.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.07:41:58.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.07:41:58.28#ibcon#ireg 11 cls_cnt 2 2006.176.07:41:58.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:41:58.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:41:58.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:41:58.34#ibcon#enter wrdev, iclass 4, count 2 2006.176.07:41:58.34#ibcon#first serial, iclass 4, count 2 2006.176.07:41:58.34#ibcon#enter sib2, iclass 4, count 2 2006.176.07:41:58.34#ibcon#flushed, iclass 4, count 2 2006.176.07:41:58.34#ibcon#about to write, iclass 4, count 2 2006.176.07:41:58.34#ibcon#wrote, iclass 4, count 2 2006.176.07:41:58.34#ibcon#about to read 3, iclass 4, count 2 2006.176.07:41:58.36#ibcon#read 3, iclass 4, count 2 2006.176.07:41:58.36#ibcon#about to read 4, iclass 4, count 2 2006.176.07:41:58.36#ibcon#read 4, iclass 4, count 2 2006.176.07:41:58.36#ibcon#about to read 5, iclass 4, count 2 2006.176.07:41:58.36#ibcon#read 5, iclass 4, count 2 2006.176.07:41:58.36#ibcon#about to read 6, iclass 4, count 2 2006.176.07:41:58.36#ibcon#read 6, iclass 4, count 2 2006.176.07:41:58.36#ibcon#end of sib2, iclass 4, count 2 2006.176.07:41:58.36#ibcon#*mode == 0, iclass 4, count 2 2006.176.07:41:58.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.07:41:58.36#ibcon#[25=AT02-07\r\n] 2006.176.07:41:58.36#ibcon#*before write, iclass 4, count 2 2006.176.07:41:58.36#ibcon#enter sib2, iclass 4, count 2 2006.176.07:41:58.36#ibcon#flushed, iclass 4, count 2 2006.176.07:41:58.36#ibcon#about to write, iclass 4, count 2 2006.176.07:41:58.36#ibcon#wrote, iclass 4, count 2 2006.176.07:41:58.36#ibcon#about to read 3, iclass 4, count 2 2006.176.07:41:58.39#ibcon#read 3, iclass 4, count 2 2006.176.07:41:58.39#ibcon#about to read 4, iclass 4, count 2 2006.176.07:41:58.39#ibcon#read 4, iclass 4, count 2 2006.176.07:41:58.39#ibcon#about to read 5, iclass 4, count 2 2006.176.07:41:58.39#ibcon#read 5, iclass 4, count 2 2006.176.07:41:58.39#ibcon#about to read 6, iclass 4, count 2 2006.176.07:41:58.39#ibcon#read 6, iclass 4, count 2 2006.176.07:41:58.39#ibcon#end of sib2, iclass 4, count 2 2006.176.07:41:58.39#ibcon#*after write, iclass 4, count 2 2006.176.07:41:58.39#ibcon#*before return 0, iclass 4, count 2 2006.176.07:41:58.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:41:58.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:41:58.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.07:41:58.39#ibcon#ireg 7 cls_cnt 0 2006.176.07:41:58.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:41:58.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:41:58.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:41:58.51#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:41:58.51#ibcon#first serial, iclass 4, count 0 2006.176.07:41:58.51#ibcon#enter sib2, iclass 4, count 0 2006.176.07:41:58.51#ibcon#flushed, iclass 4, count 0 2006.176.07:41:58.51#ibcon#about to write, iclass 4, count 0 2006.176.07:41:58.51#ibcon#wrote, iclass 4, count 0 2006.176.07:41:58.51#ibcon#about to read 3, iclass 4, count 0 2006.176.07:41:58.53#ibcon#read 3, iclass 4, count 0 2006.176.07:41:58.53#ibcon#about to read 4, iclass 4, count 0 2006.176.07:41:58.53#ibcon#read 4, iclass 4, count 0 2006.176.07:41:58.53#ibcon#about to read 5, iclass 4, count 0 2006.176.07:41:58.53#ibcon#read 5, iclass 4, count 0 2006.176.07:41:58.53#ibcon#about to read 6, iclass 4, count 0 2006.176.07:41:58.53#ibcon#read 6, iclass 4, count 0 2006.176.07:41:58.53#ibcon#end of sib2, iclass 4, count 0 2006.176.07:41:58.53#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:41:58.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:41:58.53#ibcon#[25=USB\r\n] 2006.176.07:41:58.53#ibcon#*before write, iclass 4, count 0 2006.176.07:41:58.53#ibcon#enter sib2, iclass 4, count 0 2006.176.07:41:58.53#ibcon#flushed, iclass 4, count 0 2006.176.07:41:58.53#ibcon#about to write, iclass 4, count 0 2006.176.07:41:58.53#ibcon#wrote, iclass 4, count 0 2006.176.07:41:58.53#ibcon#about to read 3, iclass 4, count 0 2006.176.07:41:58.56#ibcon#read 3, iclass 4, count 0 2006.176.07:41:58.56#ibcon#about to read 4, iclass 4, count 0 2006.176.07:41:58.56#ibcon#read 4, iclass 4, count 0 2006.176.07:41:58.56#ibcon#about to read 5, iclass 4, count 0 2006.176.07:41:58.56#ibcon#read 5, iclass 4, count 0 2006.176.07:41:58.56#ibcon#about to read 6, iclass 4, count 0 2006.176.07:41:58.56#ibcon#read 6, iclass 4, count 0 2006.176.07:41:58.56#ibcon#end of sib2, iclass 4, count 0 2006.176.07:41:58.56#ibcon#*after write, iclass 4, count 0 2006.176.07:41:58.56#ibcon#*before return 0, iclass 4, count 0 2006.176.07:41:58.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:41:58.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:41:58.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:41:58.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:41:58.56$vc4f8/valo=3,672.99 2006.176.07:41:58.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.07:41:58.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.07:41:58.56#ibcon#ireg 17 cls_cnt 0 2006.176.07:41:58.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:41:58.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:41:58.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:41:58.56#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:41:58.56#ibcon#first serial, iclass 6, count 0 2006.176.07:41:58.56#ibcon#enter sib2, iclass 6, count 0 2006.176.07:41:58.56#ibcon#flushed, iclass 6, count 0 2006.176.07:41:58.56#ibcon#about to write, iclass 6, count 0 2006.176.07:41:58.56#ibcon#wrote, iclass 6, count 0 2006.176.07:41:58.56#ibcon#about to read 3, iclass 6, count 0 2006.176.07:41:58.58#ibcon#read 3, iclass 6, count 0 2006.176.07:41:58.58#ibcon#about to read 4, iclass 6, count 0 2006.176.07:41:58.58#ibcon#read 4, iclass 6, count 0 2006.176.07:41:58.58#ibcon#about to read 5, iclass 6, count 0 2006.176.07:41:58.58#ibcon#read 5, iclass 6, count 0 2006.176.07:41:58.58#ibcon#about to read 6, iclass 6, count 0 2006.176.07:41:58.58#ibcon#read 6, iclass 6, count 0 2006.176.07:41:58.58#ibcon#end of sib2, iclass 6, count 0 2006.176.07:41:58.58#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:41:58.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:41:58.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:41:58.58#ibcon#*before write, iclass 6, count 0 2006.176.07:41:58.58#ibcon#enter sib2, iclass 6, count 0 2006.176.07:41:58.58#ibcon#flushed, iclass 6, count 0 2006.176.07:41:58.58#ibcon#about to write, iclass 6, count 0 2006.176.07:41:58.58#ibcon#wrote, iclass 6, count 0 2006.176.07:41:58.58#ibcon#about to read 3, iclass 6, count 0 2006.176.07:41:58.62#ibcon#read 3, iclass 6, count 0 2006.176.07:41:58.62#ibcon#about to read 4, iclass 6, count 0 2006.176.07:41:58.62#ibcon#read 4, iclass 6, count 0 2006.176.07:41:58.62#ibcon#about to read 5, iclass 6, count 0 2006.176.07:41:58.62#ibcon#read 5, iclass 6, count 0 2006.176.07:41:58.62#ibcon#about to read 6, iclass 6, count 0 2006.176.07:41:58.62#ibcon#read 6, iclass 6, count 0 2006.176.07:41:58.62#ibcon#end of sib2, iclass 6, count 0 2006.176.07:41:58.62#ibcon#*after write, iclass 6, count 0 2006.176.07:41:58.62#ibcon#*before return 0, iclass 6, count 0 2006.176.07:41:58.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:41:58.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:41:58.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:41:58.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:41:58.62$vc4f8/va=3,6 2006.176.07:41:58.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.07:41:58.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.07:41:58.62#ibcon#ireg 11 cls_cnt 2 2006.176.07:41:58.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:41:58.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:41:58.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:41:58.68#ibcon#enter wrdev, iclass 10, count 2 2006.176.07:41:58.68#ibcon#first serial, iclass 10, count 2 2006.176.07:41:58.68#ibcon#enter sib2, iclass 10, count 2 2006.176.07:41:58.68#ibcon#flushed, iclass 10, count 2 2006.176.07:41:58.68#ibcon#about to write, iclass 10, count 2 2006.176.07:41:58.68#ibcon#wrote, iclass 10, count 2 2006.176.07:41:58.68#ibcon#about to read 3, iclass 10, count 2 2006.176.07:41:58.70#ibcon#read 3, iclass 10, count 2 2006.176.07:41:58.70#ibcon#about to read 4, iclass 10, count 2 2006.176.07:41:58.70#ibcon#read 4, iclass 10, count 2 2006.176.07:41:58.70#ibcon#about to read 5, iclass 10, count 2 2006.176.07:41:58.70#ibcon#read 5, iclass 10, count 2 2006.176.07:41:58.70#ibcon#about to read 6, iclass 10, count 2 2006.176.07:41:58.70#ibcon#read 6, iclass 10, count 2 2006.176.07:41:58.70#ibcon#end of sib2, iclass 10, count 2 2006.176.07:41:58.70#ibcon#*mode == 0, iclass 10, count 2 2006.176.07:41:58.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.07:41:58.70#ibcon#[25=AT03-06\r\n] 2006.176.07:41:58.70#ibcon#*before write, iclass 10, count 2 2006.176.07:41:58.70#ibcon#enter sib2, iclass 10, count 2 2006.176.07:41:58.70#ibcon#flushed, iclass 10, count 2 2006.176.07:41:58.70#ibcon#about to write, iclass 10, count 2 2006.176.07:41:58.70#ibcon#wrote, iclass 10, count 2 2006.176.07:41:58.70#ibcon#about to read 3, iclass 10, count 2 2006.176.07:41:58.73#ibcon#read 3, iclass 10, count 2 2006.176.07:41:58.73#ibcon#about to read 4, iclass 10, count 2 2006.176.07:41:58.73#ibcon#read 4, iclass 10, count 2 2006.176.07:41:58.73#ibcon#about to read 5, iclass 10, count 2 2006.176.07:41:58.73#ibcon#read 5, iclass 10, count 2 2006.176.07:41:58.73#ibcon#about to read 6, iclass 10, count 2 2006.176.07:41:58.73#ibcon#read 6, iclass 10, count 2 2006.176.07:41:58.73#ibcon#end of sib2, iclass 10, count 2 2006.176.07:41:58.73#ibcon#*after write, iclass 10, count 2 2006.176.07:41:58.73#ibcon#*before return 0, iclass 10, count 2 2006.176.07:41:58.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:41:58.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:41:58.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.07:41:58.73#ibcon#ireg 7 cls_cnt 0 2006.176.07:41:58.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:41:58.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:41:58.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:41:58.85#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:41:58.85#ibcon#first serial, iclass 10, count 0 2006.176.07:41:58.85#ibcon#enter sib2, iclass 10, count 0 2006.176.07:41:58.85#ibcon#flushed, iclass 10, count 0 2006.176.07:41:58.85#ibcon#about to write, iclass 10, count 0 2006.176.07:41:58.85#ibcon#wrote, iclass 10, count 0 2006.176.07:41:58.85#ibcon#about to read 3, iclass 10, count 0 2006.176.07:41:58.87#ibcon#read 3, iclass 10, count 0 2006.176.07:41:58.87#ibcon#about to read 4, iclass 10, count 0 2006.176.07:41:58.87#ibcon#read 4, iclass 10, count 0 2006.176.07:41:58.87#ibcon#about to read 5, iclass 10, count 0 2006.176.07:41:58.87#ibcon#read 5, iclass 10, count 0 2006.176.07:41:58.87#ibcon#about to read 6, iclass 10, count 0 2006.176.07:41:58.87#ibcon#read 6, iclass 10, count 0 2006.176.07:41:58.87#ibcon#end of sib2, iclass 10, count 0 2006.176.07:41:58.87#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:41:58.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:41:58.87#ibcon#[25=USB\r\n] 2006.176.07:41:58.87#ibcon#*before write, iclass 10, count 0 2006.176.07:41:58.87#ibcon#enter sib2, iclass 10, count 0 2006.176.07:41:58.87#ibcon#flushed, iclass 10, count 0 2006.176.07:41:58.87#ibcon#about to write, iclass 10, count 0 2006.176.07:41:58.87#ibcon#wrote, iclass 10, count 0 2006.176.07:41:58.87#ibcon#about to read 3, iclass 10, count 0 2006.176.07:41:58.90#ibcon#read 3, iclass 10, count 0 2006.176.07:41:58.90#ibcon#about to read 4, iclass 10, count 0 2006.176.07:41:58.90#ibcon#read 4, iclass 10, count 0 2006.176.07:41:58.90#ibcon#about to read 5, iclass 10, count 0 2006.176.07:41:58.90#ibcon#read 5, iclass 10, count 0 2006.176.07:41:58.90#ibcon#about to read 6, iclass 10, count 0 2006.176.07:41:58.90#ibcon#read 6, iclass 10, count 0 2006.176.07:41:58.90#ibcon#end of sib2, iclass 10, count 0 2006.176.07:41:58.90#ibcon#*after write, iclass 10, count 0 2006.176.07:41:58.90#ibcon#*before return 0, iclass 10, count 0 2006.176.07:41:58.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:41:58.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:41:58.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:41:58.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:41:58.90$vc4f8/valo=4,832.99 2006.176.07:41:58.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.07:41:58.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.07:41:58.90#ibcon#ireg 17 cls_cnt 0 2006.176.07:41:58.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:41:58.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:41:58.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:41:58.90#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:41:58.90#ibcon#first serial, iclass 12, count 0 2006.176.07:41:58.90#ibcon#enter sib2, iclass 12, count 0 2006.176.07:41:58.90#ibcon#flushed, iclass 12, count 0 2006.176.07:41:58.90#ibcon#about to write, iclass 12, count 0 2006.176.07:41:58.90#ibcon#wrote, iclass 12, count 0 2006.176.07:41:58.90#ibcon#about to read 3, iclass 12, count 0 2006.176.07:41:58.92#ibcon#read 3, iclass 12, count 0 2006.176.07:41:58.92#ibcon#about to read 4, iclass 12, count 0 2006.176.07:41:58.92#ibcon#read 4, iclass 12, count 0 2006.176.07:41:58.92#ibcon#about to read 5, iclass 12, count 0 2006.176.07:41:58.92#ibcon#read 5, iclass 12, count 0 2006.176.07:41:58.92#ibcon#about to read 6, iclass 12, count 0 2006.176.07:41:58.92#ibcon#read 6, iclass 12, count 0 2006.176.07:41:58.92#ibcon#end of sib2, iclass 12, count 0 2006.176.07:41:58.92#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:41:58.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:41:58.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:41:58.92#ibcon#*before write, iclass 12, count 0 2006.176.07:41:58.92#ibcon#enter sib2, iclass 12, count 0 2006.176.07:41:58.92#ibcon#flushed, iclass 12, count 0 2006.176.07:41:58.92#ibcon#about to write, iclass 12, count 0 2006.176.07:41:58.92#ibcon#wrote, iclass 12, count 0 2006.176.07:41:58.92#ibcon#about to read 3, iclass 12, count 0 2006.176.07:41:58.96#ibcon#read 3, iclass 12, count 0 2006.176.07:41:58.96#ibcon#about to read 4, iclass 12, count 0 2006.176.07:41:58.96#ibcon#read 4, iclass 12, count 0 2006.176.07:41:58.96#ibcon#about to read 5, iclass 12, count 0 2006.176.07:41:58.96#ibcon#read 5, iclass 12, count 0 2006.176.07:41:58.96#ibcon#about to read 6, iclass 12, count 0 2006.176.07:41:58.96#ibcon#read 6, iclass 12, count 0 2006.176.07:41:58.96#ibcon#end of sib2, iclass 12, count 0 2006.176.07:41:58.96#ibcon#*after write, iclass 12, count 0 2006.176.07:41:58.96#ibcon#*before return 0, iclass 12, count 0 2006.176.07:41:58.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:41:58.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:41:58.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:41:58.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:41:58.96$vc4f8/va=4,7 2006.176.07:41:58.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.07:41:58.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.07:41:58.96#ibcon#ireg 11 cls_cnt 2 2006.176.07:41:58.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:41:59.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:41:59.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:41:59.02#ibcon#enter wrdev, iclass 14, count 2 2006.176.07:41:59.02#ibcon#first serial, iclass 14, count 2 2006.176.07:41:59.02#ibcon#enter sib2, iclass 14, count 2 2006.176.07:41:59.02#ibcon#flushed, iclass 14, count 2 2006.176.07:41:59.02#ibcon#about to write, iclass 14, count 2 2006.176.07:41:59.02#ibcon#wrote, iclass 14, count 2 2006.176.07:41:59.02#ibcon#about to read 3, iclass 14, count 2 2006.176.07:41:59.04#ibcon#read 3, iclass 14, count 2 2006.176.07:41:59.04#ibcon#about to read 4, iclass 14, count 2 2006.176.07:41:59.04#ibcon#read 4, iclass 14, count 2 2006.176.07:41:59.04#ibcon#about to read 5, iclass 14, count 2 2006.176.07:41:59.04#ibcon#read 5, iclass 14, count 2 2006.176.07:41:59.04#ibcon#about to read 6, iclass 14, count 2 2006.176.07:41:59.04#ibcon#read 6, iclass 14, count 2 2006.176.07:41:59.04#ibcon#end of sib2, iclass 14, count 2 2006.176.07:41:59.04#ibcon#*mode == 0, iclass 14, count 2 2006.176.07:41:59.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.07:41:59.04#ibcon#[25=AT04-07\r\n] 2006.176.07:41:59.04#ibcon#*before write, iclass 14, count 2 2006.176.07:41:59.04#ibcon#enter sib2, iclass 14, count 2 2006.176.07:41:59.04#ibcon#flushed, iclass 14, count 2 2006.176.07:41:59.04#ibcon#about to write, iclass 14, count 2 2006.176.07:41:59.04#ibcon#wrote, iclass 14, count 2 2006.176.07:41:59.04#ibcon#about to read 3, iclass 14, count 2 2006.176.07:41:59.07#ibcon#read 3, iclass 14, count 2 2006.176.07:41:59.07#ibcon#about to read 4, iclass 14, count 2 2006.176.07:41:59.07#ibcon#read 4, iclass 14, count 2 2006.176.07:41:59.07#ibcon#about to read 5, iclass 14, count 2 2006.176.07:41:59.07#ibcon#read 5, iclass 14, count 2 2006.176.07:41:59.07#ibcon#about to read 6, iclass 14, count 2 2006.176.07:41:59.07#ibcon#read 6, iclass 14, count 2 2006.176.07:41:59.07#ibcon#end of sib2, iclass 14, count 2 2006.176.07:41:59.07#ibcon#*after write, iclass 14, count 2 2006.176.07:41:59.07#ibcon#*before return 0, iclass 14, count 2 2006.176.07:41:59.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:41:59.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:41:59.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.07:41:59.07#ibcon#ireg 7 cls_cnt 0 2006.176.07:41:59.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:41:59.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:41:59.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:41:59.19#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:41:59.19#ibcon#first serial, iclass 14, count 0 2006.176.07:41:59.19#ibcon#enter sib2, iclass 14, count 0 2006.176.07:41:59.19#ibcon#flushed, iclass 14, count 0 2006.176.07:41:59.19#ibcon#about to write, iclass 14, count 0 2006.176.07:41:59.19#ibcon#wrote, iclass 14, count 0 2006.176.07:41:59.19#ibcon#about to read 3, iclass 14, count 0 2006.176.07:41:59.21#ibcon#read 3, iclass 14, count 0 2006.176.07:41:59.21#ibcon#about to read 4, iclass 14, count 0 2006.176.07:41:59.21#ibcon#read 4, iclass 14, count 0 2006.176.07:41:59.21#ibcon#about to read 5, iclass 14, count 0 2006.176.07:41:59.21#ibcon#read 5, iclass 14, count 0 2006.176.07:41:59.21#ibcon#about to read 6, iclass 14, count 0 2006.176.07:41:59.21#ibcon#read 6, iclass 14, count 0 2006.176.07:41:59.21#ibcon#end of sib2, iclass 14, count 0 2006.176.07:41:59.21#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:41:59.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:41:59.21#ibcon#[25=USB\r\n] 2006.176.07:41:59.21#ibcon#*before write, iclass 14, count 0 2006.176.07:41:59.21#ibcon#enter sib2, iclass 14, count 0 2006.176.07:41:59.21#ibcon#flushed, iclass 14, count 0 2006.176.07:41:59.21#ibcon#about to write, iclass 14, count 0 2006.176.07:41:59.21#ibcon#wrote, iclass 14, count 0 2006.176.07:41:59.21#ibcon#about to read 3, iclass 14, count 0 2006.176.07:41:59.24#ibcon#read 3, iclass 14, count 0 2006.176.07:41:59.24#ibcon#about to read 4, iclass 14, count 0 2006.176.07:41:59.24#ibcon#read 4, iclass 14, count 0 2006.176.07:41:59.24#ibcon#about to read 5, iclass 14, count 0 2006.176.07:41:59.24#ibcon#read 5, iclass 14, count 0 2006.176.07:41:59.24#ibcon#about to read 6, iclass 14, count 0 2006.176.07:41:59.24#ibcon#read 6, iclass 14, count 0 2006.176.07:41:59.24#ibcon#end of sib2, iclass 14, count 0 2006.176.07:41:59.24#ibcon#*after write, iclass 14, count 0 2006.176.07:41:59.24#ibcon#*before return 0, iclass 14, count 0 2006.176.07:41:59.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:41:59.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:41:59.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:41:59.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:41:59.24$vc4f8/valo=5,652.99 2006.176.07:41:59.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:41:59.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:41:59.24#ibcon#ireg 17 cls_cnt 0 2006.176.07:41:59.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:41:59.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:41:59.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:41:59.24#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:41:59.24#ibcon#first serial, iclass 16, count 0 2006.176.07:41:59.24#ibcon#enter sib2, iclass 16, count 0 2006.176.07:41:59.24#ibcon#flushed, iclass 16, count 0 2006.176.07:41:59.24#ibcon#about to write, iclass 16, count 0 2006.176.07:41:59.24#ibcon#wrote, iclass 16, count 0 2006.176.07:41:59.24#ibcon#about to read 3, iclass 16, count 0 2006.176.07:41:59.26#ibcon#read 3, iclass 16, count 0 2006.176.07:41:59.26#ibcon#about to read 4, iclass 16, count 0 2006.176.07:41:59.26#ibcon#read 4, iclass 16, count 0 2006.176.07:41:59.26#ibcon#about to read 5, iclass 16, count 0 2006.176.07:41:59.26#ibcon#read 5, iclass 16, count 0 2006.176.07:41:59.26#ibcon#about to read 6, iclass 16, count 0 2006.176.07:41:59.26#ibcon#read 6, iclass 16, count 0 2006.176.07:41:59.26#ibcon#end of sib2, iclass 16, count 0 2006.176.07:41:59.26#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:41:59.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:41:59.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:41:59.26#ibcon#*before write, iclass 16, count 0 2006.176.07:41:59.26#ibcon#enter sib2, iclass 16, count 0 2006.176.07:41:59.26#ibcon#flushed, iclass 16, count 0 2006.176.07:41:59.26#ibcon#about to write, iclass 16, count 0 2006.176.07:41:59.26#ibcon#wrote, iclass 16, count 0 2006.176.07:41:59.26#ibcon#about to read 3, iclass 16, count 0 2006.176.07:41:59.30#ibcon#read 3, iclass 16, count 0 2006.176.07:41:59.30#ibcon#about to read 4, iclass 16, count 0 2006.176.07:41:59.30#ibcon#read 4, iclass 16, count 0 2006.176.07:41:59.30#ibcon#about to read 5, iclass 16, count 0 2006.176.07:41:59.30#ibcon#read 5, iclass 16, count 0 2006.176.07:41:59.30#ibcon#about to read 6, iclass 16, count 0 2006.176.07:41:59.30#ibcon#read 6, iclass 16, count 0 2006.176.07:41:59.30#ibcon#end of sib2, iclass 16, count 0 2006.176.07:41:59.30#ibcon#*after write, iclass 16, count 0 2006.176.07:41:59.30#ibcon#*before return 0, iclass 16, count 0 2006.176.07:41:59.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:41:59.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:41:59.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:41:59.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:41:59.30$vc4f8/va=5,7 2006.176.07:41:59.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.07:41:59.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.07:41:59.30#ibcon#ireg 11 cls_cnt 2 2006.176.07:41:59.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:41:59.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:41:59.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:41:59.36#ibcon#enter wrdev, iclass 18, count 2 2006.176.07:41:59.36#ibcon#first serial, iclass 18, count 2 2006.176.07:41:59.36#ibcon#enter sib2, iclass 18, count 2 2006.176.07:41:59.36#ibcon#flushed, iclass 18, count 2 2006.176.07:41:59.36#ibcon#about to write, iclass 18, count 2 2006.176.07:41:59.36#ibcon#wrote, iclass 18, count 2 2006.176.07:41:59.36#ibcon#about to read 3, iclass 18, count 2 2006.176.07:41:59.38#ibcon#read 3, iclass 18, count 2 2006.176.07:41:59.38#ibcon#about to read 4, iclass 18, count 2 2006.176.07:41:59.38#ibcon#read 4, iclass 18, count 2 2006.176.07:41:59.38#ibcon#about to read 5, iclass 18, count 2 2006.176.07:41:59.38#ibcon#read 5, iclass 18, count 2 2006.176.07:41:59.38#ibcon#about to read 6, iclass 18, count 2 2006.176.07:41:59.38#ibcon#read 6, iclass 18, count 2 2006.176.07:41:59.38#ibcon#end of sib2, iclass 18, count 2 2006.176.07:41:59.38#ibcon#*mode == 0, iclass 18, count 2 2006.176.07:41:59.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.07:41:59.38#ibcon#[25=AT05-07\r\n] 2006.176.07:41:59.38#ibcon#*before write, iclass 18, count 2 2006.176.07:41:59.38#ibcon#enter sib2, iclass 18, count 2 2006.176.07:41:59.38#ibcon#flushed, iclass 18, count 2 2006.176.07:41:59.38#ibcon#about to write, iclass 18, count 2 2006.176.07:41:59.38#ibcon#wrote, iclass 18, count 2 2006.176.07:41:59.38#ibcon#about to read 3, iclass 18, count 2 2006.176.07:41:59.41#ibcon#read 3, iclass 18, count 2 2006.176.07:41:59.41#ibcon#about to read 4, iclass 18, count 2 2006.176.07:41:59.41#ibcon#read 4, iclass 18, count 2 2006.176.07:41:59.41#ibcon#about to read 5, iclass 18, count 2 2006.176.07:41:59.41#ibcon#read 5, iclass 18, count 2 2006.176.07:41:59.41#ibcon#about to read 6, iclass 18, count 2 2006.176.07:41:59.41#ibcon#read 6, iclass 18, count 2 2006.176.07:41:59.41#ibcon#end of sib2, iclass 18, count 2 2006.176.07:41:59.41#ibcon#*after write, iclass 18, count 2 2006.176.07:41:59.41#ibcon#*before return 0, iclass 18, count 2 2006.176.07:41:59.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:41:59.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:41:59.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.07:41:59.41#ibcon#ireg 7 cls_cnt 0 2006.176.07:41:59.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:41:59.53#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:41:59.53#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:41:59.53#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:41:59.53#ibcon#first serial, iclass 18, count 0 2006.176.07:41:59.53#ibcon#enter sib2, iclass 18, count 0 2006.176.07:41:59.53#ibcon#flushed, iclass 18, count 0 2006.176.07:41:59.53#ibcon#about to write, iclass 18, count 0 2006.176.07:41:59.53#ibcon#wrote, iclass 18, count 0 2006.176.07:41:59.53#ibcon#about to read 3, iclass 18, count 0 2006.176.07:41:59.55#ibcon#read 3, iclass 18, count 0 2006.176.07:41:59.55#ibcon#about to read 4, iclass 18, count 0 2006.176.07:41:59.55#ibcon#read 4, iclass 18, count 0 2006.176.07:41:59.55#ibcon#about to read 5, iclass 18, count 0 2006.176.07:41:59.55#ibcon#read 5, iclass 18, count 0 2006.176.07:41:59.55#ibcon#about to read 6, iclass 18, count 0 2006.176.07:41:59.55#ibcon#read 6, iclass 18, count 0 2006.176.07:41:59.55#ibcon#end of sib2, iclass 18, count 0 2006.176.07:41:59.55#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:41:59.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:41:59.55#ibcon#[25=USB\r\n] 2006.176.07:41:59.55#ibcon#*before write, iclass 18, count 0 2006.176.07:41:59.55#ibcon#enter sib2, iclass 18, count 0 2006.176.07:41:59.55#ibcon#flushed, iclass 18, count 0 2006.176.07:41:59.55#ibcon#about to write, iclass 18, count 0 2006.176.07:41:59.55#ibcon#wrote, iclass 18, count 0 2006.176.07:41:59.55#ibcon#about to read 3, iclass 18, count 0 2006.176.07:41:59.58#ibcon#read 3, iclass 18, count 0 2006.176.07:41:59.58#ibcon#about to read 4, iclass 18, count 0 2006.176.07:41:59.58#ibcon#read 4, iclass 18, count 0 2006.176.07:41:59.58#ibcon#about to read 5, iclass 18, count 0 2006.176.07:41:59.58#ibcon#read 5, iclass 18, count 0 2006.176.07:41:59.58#ibcon#about to read 6, iclass 18, count 0 2006.176.07:41:59.58#ibcon#read 6, iclass 18, count 0 2006.176.07:41:59.58#ibcon#end of sib2, iclass 18, count 0 2006.176.07:41:59.58#ibcon#*after write, iclass 18, count 0 2006.176.07:41:59.58#ibcon#*before return 0, iclass 18, count 0 2006.176.07:41:59.58#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:41:59.58#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:41:59.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:41:59.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:41:59.58$vc4f8/valo=6,772.99 2006.176.07:41:59.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.07:41:59.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.07:41:59.58#ibcon#ireg 17 cls_cnt 0 2006.176.07:41:59.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:41:59.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:41:59.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:41:59.58#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:41:59.58#ibcon#first serial, iclass 20, count 0 2006.176.07:41:59.58#ibcon#enter sib2, iclass 20, count 0 2006.176.07:41:59.58#ibcon#flushed, iclass 20, count 0 2006.176.07:41:59.58#ibcon#about to write, iclass 20, count 0 2006.176.07:41:59.58#ibcon#wrote, iclass 20, count 0 2006.176.07:41:59.58#ibcon#about to read 3, iclass 20, count 0 2006.176.07:41:59.60#ibcon#read 3, iclass 20, count 0 2006.176.07:41:59.60#ibcon#about to read 4, iclass 20, count 0 2006.176.07:41:59.60#ibcon#read 4, iclass 20, count 0 2006.176.07:41:59.60#ibcon#about to read 5, iclass 20, count 0 2006.176.07:41:59.60#ibcon#read 5, iclass 20, count 0 2006.176.07:41:59.60#ibcon#about to read 6, iclass 20, count 0 2006.176.07:41:59.60#ibcon#read 6, iclass 20, count 0 2006.176.07:41:59.60#ibcon#end of sib2, iclass 20, count 0 2006.176.07:41:59.60#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:41:59.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:41:59.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:41:59.60#ibcon#*before write, iclass 20, count 0 2006.176.07:41:59.60#ibcon#enter sib2, iclass 20, count 0 2006.176.07:41:59.60#ibcon#flushed, iclass 20, count 0 2006.176.07:41:59.60#ibcon#about to write, iclass 20, count 0 2006.176.07:41:59.60#ibcon#wrote, iclass 20, count 0 2006.176.07:41:59.60#ibcon#about to read 3, iclass 20, count 0 2006.176.07:41:59.64#ibcon#read 3, iclass 20, count 0 2006.176.07:41:59.64#ibcon#about to read 4, iclass 20, count 0 2006.176.07:41:59.64#ibcon#read 4, iclass 20, count 0 2006.176.07:41:59.64#ibcon#about to read 5, iclass 20, count 0 2006.176.07:41:59.64#ibcon#read 5, iclass 20, count 0 2006.176.07:41:59.64#ibcon#about to read 6, iclass 20, count 0 2006.176.07:41:59.64#ibcon#read 6, iclass 20, count 0 2006.176.07:41:59.64#ibcon#end of sib2, iclass 20, count 0 2006.176.07:41:59.64#ibcon#*after write, iclass 20, count 0 2006.176.07:41:59.64#ibcon#*before return 0, iclass 20, count 0 2006.176.07:41:59.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:41:59.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:41:59.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:41:59.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:41:59.64$vc4f8/va=6,6 2006.176.07:41:59.64#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.07:41:59.64#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.07:41:59.64#ibcon#ireg 11 cls_cnt 2 2006.176.07:41:59.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:41:59.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:41:59.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:41:59.70#ibcon#enter wrdev, iclass 22, count 2 2006.176.07:41:59.70#ibcon#first serial, iclass 22, count 2 2006.176.07:41:59.70#ibcon#enter sib2, iclass 22, count 2 2006.176.07:41:59.70#ibcon#flushed, iclass 22, count 2 2006.176.07:41:59.70#ibcon#about to write, iclass 22, count 2 2006.176.07:41:59.70#ibcon#wrote, iclass 22, count 2 2006.176.07:41:59.70#ibcon#about to read 3, iclass 22, count 2 2006.176.07:41:59.72#ibcon#read 3, iclass 22, count 2 2006.176.07:41:59.72#ibcon#about to read 4, iclass 22, count 2 2006.176.07:41:59.72#ibcon#read 4, iclass 22, count 2 2006.176.07:41:59.72#ibcon#about to read 5, iclass 22, count 2 2006.176.07:41:59.72#ibcon#read 5, iclass 22, count 2 2006.176.07:41:59.72#ibcon#about to read 6, iclass 22, count 2 2006.176.07:41:59.72#ibcon#read 6, iclass 22, count 2 2006.176.07:41:59.72#ibcon#end of sib2, iclass 22, count 2 2006.176.07:41:59.72#ibcon#*mode == 0, iclass 22, count 2 2006.176.07:41:59.72#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.07:41:59.72#ibcon#[25=AT06-06\r\n] 2006.176.07:41:59.72#ibcon#*before write, iclass 22, count 2 2006.176.07:41:59.72#ibcon#enter sib2, iclass 22, count 2 2006.176.07:41:59.72#ibcon#flushed, iclass 22, count 2 2006.176.07:41:59.72#ibcon#about to write, iclass 22, count 2 2006.176.07:41:59.72#ibcon#wrote, iclass 22, count 2 2006.176.07:41:59.72#ibcon#about to read 3, iclass 22, count 2 2006.176.07:41:59.75#ibcon#read 3, iclass 22, count 2 2006.176.07:41:59.75#ibcon#about to read 4, iclass 22, count 2 2006.176.07:41:59.75#ibcon#read 4, iclass 22, count 2 2006.176.07:41:59.75#ibcon#about to read 5, iclass 22, count 2 2006.176.07:41:59.75#ibcon#read 5, iclass 22, count 2 2006.176.07:41:59.75#ibcon#about to read 6, iclass 22, count 2 2006.176.07:41:59.75#ibcon#read 6, iclass 22, count 2 2006.176.07:41:59.75#ibcon#end of sib2, iclass 22, count 2 2006.176.07:41:59.75#ibcon#*after write, iclass 22, count 2 2006.176.07:41:59.75#ibcon#*before return 0, iclass 22, count 2 2006.176.07:41:59.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:41:59.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:41:59.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.07:41:59.75#ibcon#ireg 7 cls_cnt 0 2006.176.07:41:59.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:41:59.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:41:59.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:41:59.87#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:41:59.87#ibcon#first serial, iclass 22, count 0 2006.176.07:41:59.87#ibcon#enter sib2, iclass 22, count 0 2006.176.07:41:59.87#ibcon#flushed, iclass 22, count 0 2006.176.07:41:59.87#ibcon#about to write, iclass 22, count 0 2006.176.07:41:59.87#ibcon#wrote, iclass 22, count 0 2006.176.07:41:59.87#ibcon#about to read 3, iclass 22, count 0 2006.176.07:41:59.89#ibcon#read 3, iclass 22, count 0 2006.176.07:41:59.89#ibcon#about to read 4, iclass 22, count 0 2006.176.07:41:59.89#ibcon#read 4, iclass 22, count 0 2006.176.07:41:59.89#ibcon#about to read 5, iclass 22, count 0 2006.176.07:41:59.89#ibcon#read 5, iclass 22, count 0 2006.176.07:41:59.89#ibcon#about to read 6, iclass 22, count 0 2006.176.07:41:59.89#ibcon#read 6, iclass 22, count 0 2006.176.07:41:59.89#ibcon#end of sib2, iclass 22, count 0 2006.176.07:41:59.89#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:41:59.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:41:59.89#ibcon#[25=USB\r\n] 2006.176.07:41:59.89#ibcon#*before write, iclass 22, count 0 2006.176.07:41:59.89#ibcon#enter sib2, iclass 22, count 0 2006.176.07:41:59.89#ibcon#flushed, iclass 22, count 0 2006.176.07:41:59.89#ibcon#about to write, iclass 22, count 0 2006.176.07:41:59.89#ibcon#wrote, iclass 22, count 0 2006.176.07:41:59.89#ibcon#about to read 3, iclass 22, count 0 2006.176.07:41:59.92#ibcon#read 3, iclass 22, count 0 2006.176.07:41:59.92#ibcon#about to read 4, iclass 22, count 0 2006.176.07:41:59.92#ibcon#read 4, iclass 22, count 0 2006.176.07:41:59.92#ibcon#about to read 5, iclass 22, count 0 2006.176.07:41:59.92#ibcon#read 5, iclass 22, count 0 2006.176.07:41:59.92#ibcon#about to read 6, iclass 22, count 0 2006.176.07:41:59.92#ibcon#read 6, iclass 22, count 0 2006.176.07:41:59.92#ibcon#end of sib2, iclass 22, count 0 2006.176.07:41:59.92#ibcon#*after write, iclass 22, count 0 2006.176.07:41:59.92#ibcon#*before return 0, iclass 22, count 0 2006.176.07:41:59.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:41:59.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:41:59.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:41:59.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:41:59.92$vc4f8/valo=7,832.99 2006.176.07:41:59.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.07:41:59.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.07:41:59.92#ibcon#ireg 17 cls_cnt 0 2006.176.07:41:59.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:41:59.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:41:59.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:41:59.92#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:41:59.92#ibcon#first serial, iclass 24, count 0 2006.176.07:41:59.92#ibcon#enter sib2, iclass 24, count 0 2006.176.07:41:59.92#ibcon#flushed, iclass 24, count 0 2006.176.07:41:59.92#ibcon#about to write, iclass 24, count 0 2006.176.07:41:59.92#ibcon#wrote, iclass 24, count 0 2006.176.07:41:59.92#ibcon#about to read 3, iclass 24, count 0 2006.176.07:41:59.94#ibcon#read 3, iclass 24, count 0 2006.176.07:41:59.94#ibcon#about to read 4, iclass 24, count 0 2006.176.07:41:59.94#ibcon#read 4, iclass 24, count 0 2006.176.07:41:59.94#ibcon#about to read 5, iclass 24, count 0 2006.176.07:41:59.94#ibcon#read 5, iclass 24, count 0 2006.176.07:41:59.94#ibcon#about to read 6, iclass 24, count 0 2006.176.07:41:59.94#ibcon#read 6, iclass 24, count 0 2006.176.07:41:59.94#ibcon#end of sib2, iclass 24, count 0 2006.176.07:41:59.94#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:41:59.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:41:59.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:41:59.94#ibcon#*before write, iclass 24, count 0 2006.176.07:41:59.94#ibcon#enter sib2, iclass 24, count 0 2006.176.07:41:59.94#ibcon#flushed, iclass 24, count 0 2006.176.07:41:59.94#ibcon#about to write, iclass 24, count 0 2006.176.07:41:59.94#ibcon#wrote, iclass 24, count 0 2006.176.07:41:59.94#ibcon#about to read 3, iclass 24, count 0 2006.176.07:41:59.98#ibcon#read 3, iclass 24, count 0 2006.176.07:41:59.98#ibcon#about to read 4, iclass 24, count 0 2006.176.07:41:59.98#ibcon#read 4, iclass 24, count 0 2006.176.07:41:59.98#ibcon#about to read 5, iclass 24, count 0 2006.176.07:41:59.98#ibcon#read 5, iclass 24, count 0 2006.176.07:41:59.98#ibcon#about to read 6, iclass 24, count 0 2006.176.07:41:59.98#ibcon#read 6, iclass 24, count 0 2006.176.07:41:59.98#ibcon#end of sib2, iclass 24, count 0 2006.176.07:41:59.98#ibcon#*after write, iclass 24, count 0 2006.176.07:41:59.98#ibcon#*before return 0, iclass 24, count 0 2006.176.07:41:59.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:41:59.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:41:59.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:41:59.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:41:59.98$vc4f8/va=7,6 2006.176.07:41:59.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.07:41:59.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.07:41:59.98#ibcon#ireg 11 cls_cnt 2 2006.176.07:41:59.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:42:00.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:42:00.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:42:00.04#ibcon#enter wrdev, iclass 26, count 2 2006.176.07:42:00.04#ibcon#first serial, iclass 26, count 2 2006.176.07:42:00.04#ibcon#enter sib2, iclass 26, count 2 2006.176.07:42:00.04#ibcon#flushed, iclass 26, count 2 2006.176.07:42:00.04#ibcon#about to write, iclass 26, count 2 2006.176.07:42:00.04#ibcon#wrote, iclass 26, count 2 2006.176.07:42:00.04#ibcon#about to read 3, iclass 26, count 2 2006.176.07:42:00.06#ibcon#read 3, iclass 26, count 2 2006.176.07:42:00.06#ibcon#about to read 4, iclass 26, count 2 2006.176.07:42:00.06#ibcon#read 4, iclass 26, count 2 2006.176.07:42:00.06#ibcon#about to read 5, iclass 26, count 2 2006.176.07:42:00.06#ibcon#read 5, iclass 26, count 2 2006.176.07:42:00.06#ibcon#about to read 6, iclass 26, count 2 2006.176.07:42:00.06#ibcon#read 6, iclass 26, count 2 2006.176.07:42:00.06#ibcon#end of sib2, iclass 26, count 2 2006.176.07:42:00.06#ibcon#*mode == 0, iclass 26, count 2 2006.176.07:42:00.06#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.07:42:00.06#ibcon#[25=AT07-06\r\n] 2006.176.07:42:00.06#ibcon#*before write, iclass 26, count 2 2006.176.07:42:00.06#ibcon#enter sib2, iclass 26, count 2 2006.176.07:42:00.06#ibcon#flushed, iclass 26, count 2 2006.176.07:42:00.06#ibcon#about to write, iclass 26, count 2 2006.176.07:42:00.06#ibcon#wrote, iclass 26, count 2 2006.176.07:42:00.06#ibcon#about to read 3, iclass 26, count 2 2006.176.07:42:00.09#ibcon#read 3, iclass 26, count 2 2006.176.07:42:00.09#ibcon#about to read 4, iclass 26, count 2 2006.176.07:42:00.09#ibcon#read 4, iclass 26, count 2 2006.176.07:42:00.09#ibcon#about to read 5, iclass 26, count 2 2006.176.07:42:00.09#ibcon#read 5, iclass 26, count 2 2006.176.07:42:00.09#ibcon#about to read 6, iclass 26, count 2 2006.176.07:42:00.09#ibcon#read 6, iclass 26, count 2 2006.176.07:42:00.09#ibcon#end of sib2, iclass 26, count 2 2006.176.07:42:00.09#ibcon#*after write, iclass 26, count 2 2006.176.07:42:00.09#ibcon#*before return 0, iclass 26, count 2 2006.176.07:42:00.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:42:00.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:42:00.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.07:42:00.09#ibcon#ireg 7 cls_cnt 0 2006.176.07:42:00.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:42:00.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:42:00.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:42:00.21#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:42:00.21#ibcon#first serial, iclass 26, count 0 2006.176.07:42:00.21#ibcon#enter sib2, iclass 26, count 0 2006.176.07:42:00.21#ibcon#flushed, iclass 26, count 0 2006.176.07:42:00.21#ibcon#about to write, iclass 26, count 0 2006.176.07:42:00.21#ibcon#wrote, iclass 26, count 0 2006.176.07:42:00.21#ibcon#about to read 3, iclass 26, count 0 2006.176.07:42:00.23#ibcon#read 3, iclass 26, count 0 2006.176.07:42:00.23#ibcon#about to read 4, iclass 26, count 0 2006.176.07:42:00.23#ibcon#read 4, iclass 26, count 0 2006.176.07:42:00.23#ibcon#about to read 5, iclass 26, count 0 2006.176.07:42:00.23#ibcon#read 5, iclass 26, count 0 2006.176.07:42:00.23#ibcon#about to read 6, iclass 26, count 0 2006.176.07:42:00.23#ibcon#read 6, iclass 26, count 0 2006.176.07:42:00.23#ibcon#end of sib2, iclass 26, count 0 2006.176.07:42:00.23#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:42:00.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:42:00.23#ibcon#[25=USB\r\n] 2006.176.07:42:00.23#ibcon#*before write, iclass 26, count 0 2006.176.07:42:00.23#ibcon#enter sib2, iclass 26, count 0 2006.176.07:42:00.23#ibcon#flushed, iclass 26, count 0 2006.176.07:42:00.23#ibcon#about to write, iclass 26, count 0 2006.176.07:42:00.23#ibcon#wrote, iclass 26, count 0 2006.176.07:42:00.23#ibcon#about to read 3, iclass 26, count 0 2006.176.07:42:00.26#ibcon#read 3, iclass 26, count 0 2006.176.07:42:00.26#ibcon#about to read 4, iclass 26, count 0 2006.176.07:42:00.26#ibcon#read 4, iclass 26, count 0 2006.176.07:42:00.26#ibcon#about to read 5, iclass 26, count 0 2006.176.07:42:00.26#ibcon#read 5, iclass 26, count 0 2006.176.07:42:00.26#ibcon#about to read 6, iclass 26, count 0 2006.176.07:42:00.26#ibcon#read 6, iclass 26, count 0 2006.176.07:42:00.26#ibcon#end of sib2, iclass 26, count 0 2006.176.07:42:00.26#ibcon#*after write, iclass 26, count 0 2006.176.07:42:00.26#ibcon#*before return 0, iclass 26, count 0 2006.176.07:42:00.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:42:00.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:42:00.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:42:00.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:42:00.26$vc4f8/valo=8,852.99 2006.176.07:42:00.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.07:42:00.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.07:42:00.26#ibcon#ireg 17 cls_cnt 0 2006.176.07:42:00.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:42:00.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:42:00.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:42:00.26#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:42:00.26#ibcon#first serial, iclass 28, count 0 2006.176.07:42:00.26#ibcon#enter sib2, iclass 28, count 0 2006.176.07:42:00.26#ibcon#flushed, iclass 28, count 0 2006.176.07:42:00.26#ibcon#about to write, iclass 28, count 0 2006.176.07:42:00.26#ibcon#wrote, iclass 28, count 0 2006.176.07:42:00.26#ibcon#about to read 3, iclass 28, count 0 2006.176.07:42:00.28#ibcon#read 3, iclass 28, count 0 2006.176.07:42:00.28#ibcon#about to read 4, iclass 28, count 0 2006.176.07:42:00.28#ibcon#read 4, iclass 28, count 0 2006.176.07:42:00.28#ibcon#about to read 5, iclass 28, count 0 2006.176.07:42:00.28#ibcon#read 5, iclass 28, count 0 2006.176.07:42:00.28#ibcon#about to read 6, iclass 28, count 0 2006.176.07:42:00.28#ibcon#read 6, iclass 28, count 0 2006.176.07:42:00.28#ibcon#end of sib2, iclass 28, count 0 2006.176.07:42:00.28#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:42:00.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:42:00.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:42:00.28#ibcon#*before write, iclass 28, count 0 2006.176.07:42:00.28#ibcon#enter sib2, iclass 28, count 0 2006.176.07:42:00.28#ibcon#flushed, iclass 28, count 0 2006.176.07:42:00.28#ibcon#about to write, iclass 28, count 0 2006.176.07:42:00.28#ibcon#wrote, iclass 28, count 0 2006.176.07:42:00.28#ibcon#about to read 3, iclass 28, count 0 2006.176.07:42:00.32#ibcon#read 3, iclass 28, count 0 2006.176.07:42:00.32#ibcon#about to read 4, iclass 28, count 0 2006.176.07:42:00.32#ibcon#read 4, iclass 28, count 0 2006.176.07:42:00.32#ibcon#about to read 5, iclass 28, count 0 2006.176.07:42:00.32#ibcon#read 5, iclass 28, count 0 2006.176.07:42:00.32#ibcon#about to read 6, iclass 28, count 0 2006.176.07:42:00.32#ibcon#read 6, iclass 28, count 0 2006.176.07:42:00.32#ibcon#end of sib2, iclass 28, count 0 2006.176.07:42:00.32#ibcon#*after write, iclass 28, count 0 2006.176.07:42:00.32#ibcon#*before return 0, iclass 28, count 0 2006.176.07:42:00.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:42:00.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:42:00.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:42:00.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:42:00.32$vc4f8/va=8,6 2006.176.07:42:00.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.07:42:00.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.07:42:00.32#ibcon#ireg 11 cls_cnt 2 2006.176.07:42:00.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:42:00.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:42:00.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:42:00.38#ibcon#enter wrdev, iclass 30, count 2 2006.176.07:42:00.38#ibcon#first serial, iclass 30, count 2 2006.176.07:42:00.38#ibcon#enter sib2, iclass 30, count 2 2006.176.07:42:00.38#ibcon#flushed, iclass 30, count 2 2006.176.07:42:00.38#ibcon#about to write, iclass 30, count 2 2006.176.07:42:00.38#ibcon#wrote, iclass 30, count 2 2006.176.07:42:00.38#ibcon#about to read 3, iclass 30, count 2 2006.176.07:42:00.40#ibcon#read 3, iclass 30, count 2 2006.176.07:42:00.40#ibcon#about to read 4, iclass 30, count 2 2006.176.07:42:00.40#ibcon#read 4, iclass 30, count 2 2006.176.07:42:00.40#ibcon#about to read 5, iclass 30, count 2 2006.176.07:42:00.40#ibcon#read 5, iclass 30, count 2 2006.176.07:42:00.40#ibcon#about to read 6, iclass 30, count 2 2006.176.07:42:00.40#ibcon#read 6, iclass 30, count 2 2006.176.07:42:00.40#ibcon#end of sib2, iclass 30, count 2 2006.176.07:42:00.40#ibcon#*mode == 0, iclass 30, count 2 2006.176.07:42:00.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.07:42:00.40#ibcon#[25=AT08-06\r\n] 2006.176.07:42:00.40#ibcon#*before write, iclass 30, count 2 2006.176.07:42:00.40#ibcon#enter sib2, iclass 30, count 2 2006.176.07:42:00.40#ibcon#flushed, iclass 30, count 2 2006.176.07:42:00.40#ibcon#about to write, iclass 30, count 2 2006.176.07:42:00.40#ibcon#wrote, iclass 30, count 2 2006.176.07:42:00.40#ibcon#about to read 3, iclass 30, count 2 2006.176.07:42:00.43#ibcon#read 3, iclass 30, count 2 2006.176.07:42:00.43#ibcon#about to read 4, iclass 30, count 2 2006.176.07:42:00.43#ibcon#read 4, iclass 30, count 2 2006.176.07:42:00.43#ibcon#about to read 5, iclass 30, count 2 2006.176.07:42:00.43#ibcon#read 5, iclass 30, count 2 2006.176.07:42:00.43#ibcon#about to read 6, iclass 30, count 2 2006.176.07:42:00.43#ibcon#read 6, iclass 30, count 2 2006.176.07:42:00.43#ibcon#end of sib2, iclass 30, count 2 2006.176.07:42:00.43#ibcon#*after write, iclass 30, count 2 2006.176.07:42:00.43#ibcon#*before return 0, iclass 30, count 2 2006.176.07:42:00.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:42:00.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:42:00.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.07:42:00.43#ibcon#ireg 7 cls_cnt 0 2006.176.07:42:00.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:42:00.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:42:00.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:42:00.55#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:42:00.55#ibcon#first serial, iclass 30, count 0 2006.176.07:42:00.55#ibcon#enter sib2, iclass 30, count 0 2006.176.07:42:00.55#ibcon#flushed, iclass 30, count 0 2006.176.07:42:00.55#ibcon#about to write, iclass 30, count 0 2006.176.07:42:00.55#ibcon#wrote, iclass 30, count 0 2006.176.07:42:00.55#ibcon#about to read 3, iclass 30, count 0 2006.176.07:42:00.57#ibcon#read 3, iclass 30, count 0 2006.176.07:42:00.57#ibcon#about to read 4, iclass 30, count 0 2006.176.07:42:00.57#ibcon#read 4, iclass 30, count 0 2006.176.07:42:00.57#ibcon#about to read 5, iclass 30, count 0 2006.176.07:42:00.57#ibcon#read 5, iclass 30, count 0 2006.176.07:42:00.57#ibcon#about to read 6, iclass 30, count 0 2006.176.07:42:00.57#ibcon#read 6, iclass 30, count 0 2006.176.07:42:00.57#ibcon#end of sib2, iclass 30, count 0 2006.176.07:42:00.57#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:42:00.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:42:00.57#ibcon#[25=USB\r\n] 2006.176.07:42:00.57#ibcon#*before write, iclass 30, count 0 2006.176.07:42:00.57#ibcon#enter sib2, iclass 30, count 0 2006.176.07:42:00.57#ibcon#flushed, iclass 30, count 0 2006.176.07:42:00.57#ibcon#about to write, iclass 30, count 0 2006.176.07:42:00.57#ibcon#wrote, iclass 30, count 0 2006.176.07:42:00.57#ibcon#about to read 3, iclass 30, count 0 2006.176.07:42:00.60#ibcon#read 3, iclass 30, count 0 2006.176.07:42:00.60#ibcon#about to read 4, iclass 30, count 0 2006.176.07:42:00.60#ibcon#read 4, iclass 30, count 0 2006.176.07:42:00.60#ibcon#about to read 5, iclass 30, count 0 2006.176.07:42:00.60#ibcon#read 5, iclass 30, count 0 2006.176.07:42:00.60#ibcon#about to read 6, iclass 30, count 0 2006.176.07:42:00.60#ibcon#read 6, iclass 30, count 0 2006.176.07:42:00.60#ibcon#end of sib2, iclass 30, count 0 2006.176.07:42:00.60#ibcon#*after write, iclass 30, count 0 2006.176.07:42:00.60#ibcon#*before return 0, iclass 30, count 0 2006.176.07:42:00.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:42:00.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:42:00.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:42:00.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:42:00.60$vc4f8/vblo=1,632.99 2006.176.07:42:00.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.07:42:00.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.07:42:00.60#ibcon#ireg 17 cls_cnt 0 2006.176.07:42:00.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:42:00.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:42:00.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:42:00.60#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:42:00.60#ibcon#first serial, iclass 32, count 0 2006.176.07:42:00.60#ibcon#enter sib2, iclass 32, count 0 2006.176.07:42:00.60#ibcon#flushed, iclass 32, count 0 2006.176.07:42:00.60#ibcon#about to write, iclass 32, count 0 2006.176.07:42:00.60#ibcon#wrote, iclass 32, count 0 2006.176.07:42:00.60#ibcon#about to read 3, iclass 32, count 0 2006.176.07:42:00.62#ibcon#read 3, iclass 32, count 0 2006.176.07:42:00.62#ibcon#about to read 4, iclass 32, count 0 2006.176.07:42:00.62#ibcon#read 4, iclass 32, count 0 2006.176.07:42:00.62#ibcon#about to read 5, iclass 32, count 0 2006.176.07:42:00.62#ibcon#read 5, iclass 32, count 0 2006.176.07:42:00.62#ibcon#about to read 6, iclass 32, count 0 2006.176.07:42:00.62#ibcon#read 6, iclass 32, count 0 2006.176.07:42:00.62#ibcon#end of sib2, iclass 32, count 0 2006.176.07:42:00.62#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:42:00.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:42:00.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:42:00.62#ibcon#*before write, iclass 32, count 0 2006.176.07:42:00.62#ibcon#enter sib2, iclass 32, count 0 2006.176.07:42:00.62#ibcon#flushed, iclass 32, count 0 2006.176.07:42:00.62#ibcon#about to write, iclass 32, count 0 2006.176.07:42:00.62#ibcon#wrote, iclass 32, count 0 2006.176.07:42:00.62#ibcon#about to read 3, iclass 32, count 0 2006.176.07:42:00.66#ibcon#read 3, iclass 32, count 0 2006.176.07:42:00.66#ibcon#about to read 4, iclass 32, count 0 2006.176.07:42:00.66#ibcon#read 4, iclass 32, count 0 2006.176.07:42:00.66#ibcon#about to read 5, iclass 32, count 0 2006.176.07:42:00.66#ibcon#read 5, iclass 32, count 0 2006.176.07:42:00.66#ibcon#about to read 6, iclass 32, count 0 2006.176.07:42:00.66#ibcon#read 6, iclass 32, count 0 2006.176.07:42:00.66#ibcon#end of sib2, iclass 32, count 0 2006.176.07:42:00.66#ibcon#*after write, iclass 32, count 0 2006.176.07:42:00.66#ibcon#*before return 0, iclass 32, count 0 2006.176.07:42:00.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:42:00.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:42:00.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:42:00.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:42:00.66$vc4f8/vb=1,4 2006.176.07:42:00.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.07:42:00.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.07:42:00.66#ibcon#ireg 11 cls_cnt 2 2006.176.07:42:00.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:42:00.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:42:00.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:42:00.66#ibcon#enter wrdev, iclass 34, count 2 2006.176.07:42:00.66#ibcon#first serial, iclass 34, count 2 2006.176.07:42:00.66#ibcon#enter sib2, iclass 34, count 2 2006.176.07:42:00.66#ibcon#flushed, iclass 34, count 2 2006.176.07:42:00.66#ibcon#about to write, iclass 34, count 2 2006.176.07:42:00.66#ibcon#wrote, iclass 34, count 2 2006.176.07:42:00.66#ibcon#about to read 3, iclass 34, count 2 2006.176.07:42:00.68#ibcon#read 3, iclass 34, count 2 2006.176.07:42:00.68#ibcon#about to read 4, iclass 34, count 2 2006.176.07:42:00.68#ibcon#read 4, iclass 34, count 2 2006.176.07:42:00.68#ibcon#about to read 5, iclass 34, count 2 2006.176.07:42:00.68#ibcon#read 5, iclass 34, count 2 2006.176.07:42:00.68#ibcon#about to read 6, iclass 34, count 2 2006.176.07:42:00.68#ibcon#read 6, iclass 34, count 2 2006.176.07:42:00.68#ibcon#end of sib2, iclass 34, count 2 2006.176.07:42:00.68#ibcon#*mode == 0, iclass 34, count 2 2006.176.07:42:00.68#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.07:42:00.68#ibcon#[27=AT01-04\r\n] 2006.176.07:42:00.68#ibcon#*before write, iclass 34, count 2 2006.176.07:42:00.68#ibcon#enter sib2, iclass 34, count 2 2006.176.07:42:00.68#ibcon#flushed, iclass 34, count 2 2006.176.07:42:00.68#ibcon#about to write, iclass 34, count 2 2006.176.07:42:00.68#ibcon#wrote, iclass 34, count 2 2006.176.07:42:00.68#ibcon#about to read 3, iclass 34, count 2 2006.176.07:42:00.71#ibcon#read 3, iclass 34, count 2 2006.176.07:42:00.71#ibcon#about to read 4, iclass 34, count 2 2006.176.07:42:00.71#ibcon#read 4, iclass 34, count 2 2006.176.07:42:00.71#ibcon#about to read 5, iclass 34, count 2 2006.176.07:42:00.71#ibcon#read 5, iclass 34, count 2 2006.176.07:42:00.71#ibcon#about to read 6, iclass 34, count 2 2006.176.07:42:00.71#ibcon#read 6, iclass 34, count 2 2006.176.07:42:00.71#ibcon#end of sib2, iclass 34, count 2 2006.176.07:42:00.71#ibcon#*after write, iclass 34, count 2 2006.176.07:42:00.71#ibcon#*before return 0, iclass 34, count 2 2006.176.07:42:00.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:42:00.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:42:00.71#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.07:42:00.71#ibcon#ireg 7 cls_cnt 0 2006.176.07:42:00.71#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:42:00.83#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:42:00.83#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:42:00.83#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:42:00.83#ibcon#first serial, iclass 34, count 0 2006.176.07:42:00.83#ibcon#enter sib2, iclass 34, count 0 2006.176.07:42:00.83#ibcon#flushed, iclass 34, count 0 2006.176.07:42:00.83#ibcon#about to write, iclass 34, count 0 2006.176.07:42:00.83#ibcon#wrote, iclass 34, count 0 2006.176.07:42:00.83#ibcon#about to read 3, iclass 34, count 0 2006.176.07:42:00.85#ibcon#read 3, iclass 34, count 0 2006.176.07:42:00.85#ibcon#about to read 4, iclass 34, count 0 2006.176.07:42:00.85#ibcon#read 4, iclass 34, count 0 2006.176.07:42:00.85#ibcon#about to read 5, iclass 34, count 0 2006.176.07:42:00.85#ibcon#read 5, iclass 34, count 0 2006.176.07:42:00.85#ibcon#about to read 6, iclass 34, count 0 2006.176.07:42:00.85#ibcon#read 6, iclass 34, count 0 2006.176.07:42:00.85#ibcon#end of sib2, iclass 34, count 0 2006.176.07:42:00.85#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:42:00.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:42:00.85#ibcon#[27=USB\r\n] 2006.176.07:42:00.85#ibcon#*before write, iclass 34, count 0 2006.176.07:42:00.85#ibcon#enter sib2, iclass 34, count 0 2006.176.07:42:00.85#ibcon#flushed, iclass 34, count 0 2006.176.07:42:00.85#ibcon#about to write, iclass 34, count 0 2006.176.07:42:00.85#ibcon#wrote, iclass 34, count 0 2006.176.07:42:00.85#ibcon#about to read 3, iclass 34, count 0 2006.176.07:42:00.88#ibcon#read 3, iclass 34, count 0 2006.176.07:42:00.88#ibcon#about to read 4, iclass 34, count 0 2006.176.07:42:00.88#ibcon#read 4, iclass 34, count 0 2006.176.07:42:00.88#ibcon#about to read 5, iclass 34, count 0 2006.176.07:42:00.88#ibcon#read 5, iclass 34, count 0 2006.176.07:42:00.88#ibcon#about to read 6, iclass 34, count 0 2006.176.07:42:00.88#ibcon#read 6, iclass 34, count 0 2006.176.07:42:00.88#ibcon#end of sib2, iclass 34, count 0 2006.176.07:42:00.88#ibcon#*after write, iclass 34, count 0 2006.176.07:42:00.88#ibcon#*before return 0, iclass 34, count 0 2006.176.07:42:00.88#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:42:00.88#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:42:00.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:42:00.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:42:00.88$vc4f8/vblo=2,640.99 2006.176.07:42:00.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.07:42:00.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.07:42:00.88#ibcon#ireg 17 cls_cnt 0 2006.176.07:42:00.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:42:00.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:42:00.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:42:00.88#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:42:00.88#ibcon#first serial, iclass 36, count 0 2006.176.07:42:00.88#ibcon#enter sib2, iclass 36, count 0 2006.176.07:42:00.88#ibcon#flushed, iclass 36, count 0 2006.176.07:42:00.88#ibcon#about to write, iclass 36, count 0 2006.176.07:42:00.88#ibcon#wrote, iclass 36, count 0 2006.176.07:42:00.88#ibcon#about to read 3, iclass 36, count 0 2006.176.07:42:00.90#ibcon#read 3, iclass 36, count 0 2006.176.07:42:00.90#ibcon#about to read 4, iclass 36, count 0 2006.176.07:42:00.90#ibcon#read 4, iclass 36, count 0 2006.176.07:42:00.90#ibcon#about to read 5, iclass 36, count 0 2006.176.07:42:00.90#ibcon#read 5, iclass 36, count 0 2006.176.07:42:00.90#ibcon#about to read 6, iclass 36, count 0 2006.176.07:42:00.90#ibcon#read 6, iclass 36, count 0 2006.176.07:42:00.90#ibcon#end of sib2, iclass 36, count 0 2006.176.07:42:00.90#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:42:00.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:42:00.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:42:00.90#ibcon#*before write, iclass 36, count 0 2006.176.07:42:00.90#ibcon#enter sib2, iclass 36, count 0 2006.176.07:42:00.90#ibcon#flushed, iclass 36, count 0 2006.176.07:42:00.90#ibcon#about to write, iclass 36, count 0 2006.176.07:42:00.90#ibcon#wrote, iclass 36, count 0 2006.176.07:42:00.90#ibcon#about to read 3, iclass 36, count 0 2006.176.07:42:00.94#ibcon#read 3, iclass 36, count 0 2006.176.07:42:00.94#ibcon#about to read 4, iclass 36, count 0 2006.176.07:42:00.94#ibcon#read 4, iclass 36, count 0 2006.176.07:42:00.94#ibcon#about to read 5, iclass 36, count 0 2006.176.07:42:00.94#ibcon#read 5, iclass 36, count 0 2006.176.07:42:00.94#ibcon#about to read 6, iclass 36, count 0 2006.176.07:42:00.94#ibcon#read 6, iclass 36, count 0 2006.176.07:42:00.94#ibcon#end of sib2, iclass 36, count 0 2006.176.07:42:00.94#ibcon#*after write, iclass 36, count 0 2006.176.07:42:00.94#ibcon#*before return 0, iclass 36, count 0 2006.176.07:42:00.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:42:00.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:42:00.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:42:00.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:42:00.94$vc4f8/vb=2,4 2006.176.07:42:00.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.07:42:00.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.07:42:00.94#ibcon#ireg 11 cls_cnt 2 2006.176.07:42:00.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:42:01.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:42:01.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:42:01.00#ibcon#enter wrdev, iclass 38, count 2 2006.176.07:42:01.00#ibcon#first serial, iclass 38, count 2 2006.176.07:42:01.00#ibcon#enter sib2, iclass 38, count 2 2006.176.07:42:01.00#ibcon#flushed, iclass 38, count 2 2006.176.07:42:01.00#ibcon#about to write, iclass 38, count 2 2006.176.07:42:01.00#ibcon#wrote, iclass 38, count 2 2006.176.07:42:01.00#ibcon#about to read 3, iclass 38, count 2 2006.176.07:42:01.02#ibcon#read 3, iclass 38, count 2 2006.176.07:42:01.02#ibcon#about to read 4, iclass 38, count 2 2006.176.07:42:01.02#ibcon#read 4, iclass 38, count 2 2006.176.07:42:01.02#ibcon#about to read 5, iclass 38, count 2 2006.176.07:42:01.02#ibcon#read 5, iclass 38, count 2 2006.176.07:42:01.02#ibcon#about to read 6, iclass 38, count 2 2006.176.07:42:01.02#ibcon#read 6, iclass 38, count 2 2006.176.07:42:01.02#ibcon#end of sib2, iclass 38, count 2 2006.176.07:42:01.02#ibcon#*mode == 0, iclass 38, count 2 2006.176.07:42:01.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.07:42:01.02#ibcon#[27=AT02-04\r\n] 2006.176.07:42:01.02#ibcon#*before write, iclass 38, count 2 2006.176.07:42:01.02#ibcon#enter sib2, iclass 38, count 2 2006.176.07:42:01.02#ibcon#flushed, iclass 38, count 2 2006.176.07:42:01.02#ibcon#about to write, iclass 38, count 2 2006.176.07:42:01.02#ibcon#wrote, iclass 38, count 2 2006.176.07:42:01.02#ibcon#about to read 3, iclass 38, count 2 2006.176.07:42:01.05#ibcon#read 3, iclass 38, count 2 2006.176.07:42:01.05#ibcon#about to read 4, iclass 38, count 2 2006.176.07:42:01.05#ibcon#read 4, iclass 38, count 2 2006.176.07:42:01.05#ibcon#about to read 5, iclass 38, count 2 2006.176.07:42:01.05#ibcon#read 5, iclass 38, count 2 2006.176.07:42:01.05#ibcon#about to read 6, iclass 38, count 2 2006.176.07:42:01.05#ibcon#read 6, iclass 38, count 2 2006.176.07:42:01.05#ibcon#end of sib2, iclass 38, count 2 2006.176.07:42:01.05#ibcon#*after write, iclass 38, count 2 2006.176.07:42:01.05#ibcon#*before return 0, iclass 38, count 2 2006.176.07:42:01.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:42:01.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:42:01.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.07:42:01.05#ibcon#ireg 7 cls_cnt 0 2006.176.07:42:01.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:42:01.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:42:01.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:42:01.17#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:42:01.17#ibcon#first serial, iclass 38, count 0 2006.176.07:42:01.17#ibcon#enter sib2, iclass 38, count 0 2006.176.07:42:01.17#ibcon#flushed, iclass 38, count 0 2006.176.07:42:01.17#ibcon#about to write, iclass 38, count 0 2006.176.07:42:01.17#ibcon#wrote, iclass 38, count 0 2006.176.07:42:01.17#ibcon#about to read 3, iclass 38, count 0 2006.176.07:42:01.20#ibcon#read 3, iclass 38, count 0 2006.176.07:42:01.20#ibcon#about to read 4, iclass 38, count 0 2006.176.07:42:01.20#ibcon#read 4, iclass 38, count 0 2006.176.07:42:01.20#ibcon#about to read 5, iclass 38, count 0 2006.176.07:42:01.20#ibcon#read 5, iclass 38, count 0 2006.176.07:42:01.20#ibcon#about to read 6, iclass 38, count 0 2006.176.07:42:01.20#ibcon#read 6, iclass 38, count 0 2006.176.07:42:01.20#ibcon#end of sib2, iclass 38, count 0 2006.176.07:42:01.20#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:42:01.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:42:01.20#ibcon#[27=USB\r\n] 2006.176.07:42:01.20#ibcon#*before write, iclass 38, count 0 2006.176.07:42:01.20#ibcon#enter sib2, iclass 38, count 0 2006.176.07:42:01.20#ibcon#flushed, iclass 38, count 0 2006.176.07:42:01.20#ibcon#about to write, iclass 38, count 0 2006.176.07:42:01.20#ibcon#wrote, iclass 38, count 0 2006.176.07:42:01.20#ibcon#about to read 3, iclass 38, count 0 2006.176.07:42:01.23#ibcon#read 3, iclass 38, count 0 2006.176.07:42:01.23#ibcon#about to read 4, iclass 38, count 0 2006.176.07:42:01.23#ibcon#read 4, iclass 38, count 0 2006.176.07:42:01.23#ibcon#about to read 5, iclass 38, count 0 2006.176.07:42:01.23#ibcon#read 5, iclass 38, count 0 2006.176.07:42:01.23#ibcon#about to read 6, iclass 38, count 0 2006.176.07:42:01.23#ibcon#read 6, iclass 38, count 0 2006.176.07:42:01.23#ibcon#end of sib2, iclass 38, count 0 2006.176.07:42:01.23#ibcon#*after write, iclass 38, count 0 2006.176.07:42:01.23#ibcon#*before return 0, iclass 38, count 0 2006.176.07:42:01.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:42:01.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:42:01.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:42:01.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:42:01.23$vc4f8/vblo=3,656.99 2006.176.07:42:01.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.07:42:01.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.07:42:01.23#ibcon#ireg 17 cls_cnt 0 2006.176.07:42:01.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:42:01.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:42:01.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:42:01.23#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:42:01.23#ibcon#first serial, iclass 40, count 0 2006.176.07:42:01.23#ibcon#enter sib2, iclass 40, count 0 2006.176.07:42:01.23#ibcon#flushed, iclass 40, count 0 2006.176.07:42:01.23#ibcon#about to write, iclass 40, count 0 2006.176.07:42:01.23#ibcon#wrote, iclass 40, count 0 2006.176.07:42:01.23#ibcon#about to read 3, iclass 40, count 0 2006.176.07:42:01.25#ibcon#read 3, iclass 40, count 0 2006.176.07:42:01.25#ibcon#about to read 4, iclass 40, count 0 2006.176.07:42:01.25#ibcon#read 4, iclass 40, count 0 2006.176.07:42:01.25#ibcon#about to read 5, iclass 40, count 0 2006.176.07:42:01.25#ibcon#read 5, iclass 40, count 0 2006.176.07:42:01.25#ibcon#about to read 6, iclass 40, count 0 2006.176.07:42:01.25#ibcon#read 6, iclass 40, count 0 2006.176.07:42:01.25#ibcon#end of sib2, iclass 40, count 0 2006.176.07:42:01.25#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:42:01.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:42:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:42:01.25#ibcon#*before write, iclass 40, count 0 2006.176.07:42:01.25#ibcon#enter sib2, iclass 40, count 0 2006.176.07:42:01.25#ibcon#flushed, iclass 40, count 0 2006.176.07:42:01.25#ibcon#about to write, iclass 40, count 0 2006.176.07:42:01.25#ibcon#wrote, iclass 40, count 0 2006.176.07:42:01.25#ibcon#about to read 3, iclass 40, count 0 2006.176.07:42:01.29#ibcon#read 3, iclass 40, count 0 2006.176.07:42:01.29#ibcon#about to read 4, iclass 40, count 0 2006.176.07:42:01.29#ibcon#read 4, iclass 40, count 0 2006.176.07:42:01.29#ibcon#about to read 5, iclass 40, count 0 2006.176.07:42:01.29#ibcon#read 5, iclass 40, count 0 2006.176.07:42:01.29#ibcon#about to read 6, iclass 40, count 0 2006.176.07:42:01.29#ibcon#read 6, iclass 40, count 0 2006.176.07:42:01.29#ibcon#end of sib2, iclass 40, count 0 2006.176.07:42:01.29#ibcon#*after write, iclass 40, count 0 2006.176.07:42:01.29#ibcon#*before return 0, iclass 40, count 0 2006.176.07:42:01.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:42:01.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:42:01.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:42:01.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:42:01.29$vc4f8/vb=3,4 2006.176.07:42:01.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.07:42:01.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.07:42:01.29#ibcon#ireg 11 cls_cnt 2 2006.176.07:42:01.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:42:01.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:42:01.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:42:01.35#ibcon#enter wrdev, iclass 4, count 2 2006.176.07:42:01.35#ibcon#first serial, iclass 4, count 2 2006.176.07:42:01.35#ibcon#enter sib2, iclass 4, count 2 2006.176.07:42:01.35#ibcon#flushed, iclass 4, count 2 2006.176.07:42:01.35#ibcon#about to write, iclass 4, count 2 2006.176.07:42:01.35#ibcon#wrote, iclass 4, count 2 2006.176.07:42:01.35#ibcon#about to read 3, iclass 4, count 2 2006.176.07:42:01.37#ibcon#read 3, iclass 4, count 2 2006.176.07:42:01.37#ibcon#about to read 4, iclass 4, count 2 2006.176.07:42:01.37#ibcon#read 4, iclass 4, count 2 2006.176.07:42:01.37#ibcon#about to read 5, iclass 4, count 2 2006.176.07:42:01.37#ibcon#read 5, iclass 4, count 2 2006.176.07:42:01.37#ibcon#about to read 6, iclass 4, count 2 2006.176.07:42:01.37#ibcon#read 6, iclass 4, count 2 2006.176.07:42:01.37#ibcon#end of sib2, iclass 4, count 2 2006.176.07:42:01.37#ibcon#*mode == 0, iclass 4, count 2 2006.176.07:42:01.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.07:42:01.37#ibcon#[27=AT03-04\r\n] 2006.176.07:42:01.37#ibcon#*before write, iclass 4, count 2 2006.176.07:42:01.37#ibcon#enter sib2, iclass 4, count 2 2006.176.07:42:01.37#ibcon#flushed, iclass 4, count 2 2006.176.07:42:01.37#ibcon#about to write, iclass 4, count 2 2006.176.07:42:01.37#ibcon#wrote, iclass 4, count 2 2006.176.07:42:01.37#ibcon#about to read 3, iclass 4, count 2 2006.176.07:42:01.40#ibcon#read 3, iclass 4, count 2 2006.176.07:42:01.40#ibcon#about to read 4, iclass 4, count 2 2006.176.07:42:01.40#ibcon#read 4, iclass 4, count 2 2006.176.07:42:01.40#ibcon#about to read 5, iclass 4, count 2 2006.176.07:42:01.40#ibcon#read 5, iclass 4, count 2 2006.176.07:42:01.40#ibcon#about to read 6, iclass 4, count 2 2006.176.07:42:01.40#ibcon#read 6, iclass 4, count 2 2006.176.07:42:01.40#ibcon#end of sib2, iclass 4, count 2 2006.176.07:42:01.40#ibcon#*after write, iclass 4, count 2 2006.176.07:42:01.40#ibcon#*before return 0, iclass 4, count 2 2006.176.07:42:01.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:42:01.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:42:01.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.07:42:01.40#ibcon#ireg 7 cls_cnt 0 2006.176.07:42:01.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:42:01.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:42:01.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:42:01.52#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:42:01.52#ibcon#first serial, iclass 4, count 0 2006.176.07:42:01.52#ibcon#enter sib2, iclass 4, count 0 2006.176.07:42:01.52#ibcon#flushed, iclass 4, count 0 2006.176.07:42:01.52#ibcon#about to write, iclass 4, count 0 2006.176.07:42:01.52#ibcon#wrote, iclass 4, count 0 2006.176.07:42:01.52#ibcon#about to read 3, iclass 4, count 0 2006.176.07:42:01.54#ibcon#read 3, iclass 4, count 0 2006.176.07:42:01.54#ibcon#about to read 4, iclass 4, count 0 2006.176.07:42:01.54#ibcon#read 4, iclass 4, count 0 2006.176.07:42:01.54#ibcon#about to read 5, iclass 4, count 0 2006.176.07:42:01.54#ibcon#read 5, iclass 4, count 0 2006.176.07:42:01.54#ibcon#about to read 6, iclass 4, count 0 2006.176.07:42:01.54#ibcon#read 6, iclass 4, count 0 2006.176.07:42:01.54#ibcon#end of sib2, iclass 4, count 0 2006.176.07:42:01.54#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:42:01.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:42:01.54#ibcon#[27=USB\r\n] 2006.176.07:42:01.54#ibcon#*before write, iclass 4, count 0 2006.176.07:42:01.54#ibcon#enter sib2, iclass 4, count 0 2006.176.07:42:01.54#ibcon#flushed, iclass 4, count 0 2006.176.07:42:01.54#ibcon#about to write, iclass 4, count 0 2006.176.07:42:01.54#ibcon#wrote, iclass 4, count 0 2006.176.07:42:01.54#ibcon#about to read 3, iclass 4, count 0 2006.176.07:42:01.57#ibcon#read 3, iclass 4, count 0 2006.176.07:42:01.57#ibcon#about to read 4, iclass 4, count 0 2006.176.07:42:01.57#ibcon#read 4, iclass 4, count 0 2006.176.07:42:01.57#ibcon#about to read 5, iclass 4, count 0 2006.176.07:42:01.57#ibcon#read 5, iclass 4, count 0 2006.176.07:42:01.57#ibcon#about to read 6, iclass 4, count 0 2006.176.07:42:01.57#ibcon#read 6, iclass 4, count 0 2006.176.07:42:01.57#ibcon#end of sib2, iclass 4, count 0 2006.176.07:42:01.57#ibcon#*after write, iclass 4, count 0 2006.176.07:42:01.57#ibcon#*before return 0, iclass 4, count 0 2006.176.07:42:01.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:42:01.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:42:01.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:42:01.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:42:01.57$vc4f8/vblo=4,712.99 2006.176.07:42:01.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.07:42:01.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.07:42:01.57#ibcon#ireg 17 cls_cnt 0 2006.176.07:42:01.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:42:01.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:42:01.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:42:01.57#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:42:01.57#ibcon#first serial, iclass 6, count 0 2006.176.07:42:01.57#ibcon#enter sib2, iclass 6, count 0 2006.176.07:42:01.57#ibcon#flushed, iclass 6, count 0 2006.176.07:42:01.57#ibcon#about to write, iclass 6, count 0 2006.176.07:42:01.57#ibcon#wrote, iclass 6, count 0 2006.176.07:42:01.57#ibcon#about to read 3, iclass 6, count 0 2006.176.07:42:01.59#ibcon#read 3, iclass 6, count 0 2006.176.07:42:01.59#ibcon#about to read 4, iclass 6, count 0 2006.176.07:42:01.59#ibcon#read 4, iclass 6, count 0 2006.176.07:42:01.59#ibcon#about to read 5, iclass 6, count 0 2006.176.07:42:01.59#ibcon#read 5, iclass 6, count 0 2006.176.07:42:01.59#ibcon#about to read 6, iclass 6, count 0 2006.176.07:42:01.59#ibcon#read 6, iclass 6, count 0 2006.176.07:42:01.59#ibcon#end of sib2, iclass 6, count 0 2006.176.07:42:01.59#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:42:01.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:42:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:42:01.59#ibcon#*before write, iclass 6, count 0 2006.176.07:42:01.59#ibcon#enter sib2, iclass 6, count 0 2006.176.07:42:01.59#ibcon#flushed, iclass 6, count 0 2006.176.07:42:01.59#ibcon#about to write, iclass 6, count 0 2006.176.07:42:01.59#ibcon#wrote, iclass 6, count 0 2006.176.07:42:01.59#ibcon#about to read 3, iclass 6, count 0 2006.176.07:42:01.63#ibcon#read 3, iclass 6, count 0 2006.176.07:42:01.63#ibcon#about to read 4, iclass 6, count 0 2006.176.07:42:01.63#ibcon#read 4, iclass 6, count 0 2006.176.07:42:01.63#ibcon#about to read 5, iclass 6, count 0 2006.176.07:42:01.63#ibcon#read 5, iclass 6, count 0 2006.176.07:42:01.63#ibcon#about to read 6, iclass 6, count 0 2006.176.07:42:01.63#ibcon#read 6, iclass 6, count 0 2006.176.07:42:01.63#ibcon#end of sib2, iclass 6, count 0 2006.176.07:42:01.63#ibcon#*after write, iclass 6, count 0 2006.176.07:42:01.63#ibcon#*before return 0, iclass 6, count 0 2006.176.07:42:01.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:42:01.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:42:01.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:42:01.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:42:01.63$vc4f8/vb=4,4 2006.176.07:42:01.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.07:42:01.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.07:42:01.63#ibcon#ireg 11 cls_cnt 2 2006.176.07:42:01.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:42:01.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:42:01.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:42:01.69#ibcon#enter wrdev, iclass 10, count 2 2006.176.07:42:01.69#ibcon#first serial, iclass 10, count 2 2006.176.07:42:01.69#ibcon#enter sib2, iclass 10, count 2 2006.176.07:42:01.69#ibcon#flushed, iclass 10, count 2 2006.176.07:42:01.69#ibcon#about to write, iclass 10, count 2 2006.176.07:42:01.69#ibcon#wrote, iclass 10, count 2 2006.176.07:42:01.69#ibcon#about to read 3, iclass 10, count 2 2006.176.07:42:01.71#ibcon#read 3, iclass 10, count 2 2006.176.07:42:01.71#ibcon#about to read 4, iclass 10, count 2 2006.176.07:42:01.71#ibcon#read 4, iclass 10, count 2 2006.176.07:42:01.71#ibcon#about to read 5, iclass 10, count 2 2006.176.07:42:01.71#ibcon#read 5, iclass 10, count 2 2006.176.07:42:01.71#ibcon#about to read 6, iclass 10, count 2 2006.176.07:42:01.71#ibcon#read 6, iclass 10, count 2 2006.176.07:42:01.71#ibcon#end of sib2, iclass 10, count 2 2006.176.07:42:01.71#ibcon#*mode == 0, iclass 10, count 2 2006.176.07:42:01.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.07:42:01.71#ibcon#[27=AT04-04\r\n] 2006.176.07:42:01.71#ibcon#*before write, iclass 10, count 2 2006.176.07:42:01.71#ibcon#enter sib2, iclass 10, count 2 2006.176.07:42:01.71#ibcon#flushed, iclass 10, count 2 2006.176.07:42:01.71#ibcon#about to write, iclass 10, count 2 2006.176.07:42:01.71#ibcon#wrote, iclass 10, count 2 2006.176.07:42:01.71#ibcon#about to read 3, iclass 10, count 2 2006.176.07:42:01.74#ibcon#read 3, iclass 10, count 2 2006.176.07:42:01.74#ibcon#about to read 4, iclass 10, count 2 2006.176.07:42:01.74#ibcon#read 4, iclass 10, count 2 2006.176.07:42:01.74#ibcon#about to read 5, iclass 10, count 2 2006.176.07:42:01.74#ibcon#read 5, iclass 10, count 2 2006.176.07:42:01.74#ibcon#about to read 6, iclass 10, count 2 2006.176.07:42:01.74#ibcon#read 6, iclass 10, count 2 2006.176.07:42:01.74#ibcon#end of sib2, iclass 10, count 2 2006.176.07:42:01.74#ibcon#*after write, iclass 10, count 2 2006.176.07:42:01.74#ibcon#*before return 0, iclass 10, count 2 2006.176.07:42:01.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:42:01.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:42:01.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.07:42:01.74#ibcon#ireg 7 cls_cnt 0 2006.176.07:42:01.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:42:01.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:42:01.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:42:01.86#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:42:01.86#ibcon#first serial, iclass 10, count 0 2006.176.07:42:01.86#ibcon#enter sib2, iclass 10, count 0 2006.176.07:42:01.86#ibcon#flushed, iclass 10, count 0 2006.176.07:42:01.86#ibcon#about to write, iclass 10, count 0 2006.176.07:42:01.86#ibcon#wrote, iclass 10, count 0 2006.176.07:42:01.86#ibcon#about to read 3, iclass 10, count 0 2006.176.07:42:01.88#ibcon#read 3, iclass 10, count 0 2006.176.07:42:01.88#ibcon#about to read 4, iclass 10, count 0 2006.176.07:42:01.88#ibcon#read 4, iclass 10, count 0 2006.176.07:42:01.88#ibcon#about to read 5, iclass 10, count 0 2006.176.07:42:01.88#ibcon#read 5, iclass 10, count 0 2006.176.07:42:01.88#ibcon#about to read 6, iclass 10, count 0 2006.176.07:42:01.88#ibcon#read 6, iclass 10, count 0 2006.176.07:42:01.88#ibcon#end of sib2, iclass 10, count 0 2006.176.07:42:01.88#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:42:01.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:42:01.88#ibcon#[27=USB\r\n] 2006.176.07:42:01.88#ibcon#*before write, iclass 10, count 0 2006.176.07:42:01.88#ibcon#enter sib2, iclass 10, count 0 2006.176.07:42:01.88#ibcon#flushed, iclass 10, count 0 2006.176.07:42:01.88#ibcon#about to write, iclass 10, count 0 2006.176.07:42:01.88#ibcon#wrote, iclass 10, count 0 2006.176.07:42:01.88#ibcon#about to read 3, iclass 10, count 0 2006.176.07:42:01.91#ibcon#read 3, iclass 10, count 0 2006.176.07:42:01.91#ibcon#about to read 4, iclass 10, count 0 2006.176.07:42:01.91#ibcon#read 4, iclass 10, count 0 2006.176.07:42:01.91#ibcon#about to read 5, iclass 10, count 0 2006.176.07:42:01.91#ibcon#read 5, iclass 10, count 0 2006.176.07:42:01.91#ibcon#about to read 6, iclass 10, count 0 2006.176.07:42:01.91#ibcon#read 6, iclass 10, count 0 2006.176.07:42:01.91#ibcon#end of sib2, iclass 10, count 0 2006.176.07:42:01.91#ibcon#*after write, iclass 10, count 0 2006.176.07:42:01.91#ibcon#*before return 0, iclass 10, count 0 2006.176.07:42:01.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:42:01.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:42:01.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:42:01.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:42:01.91$vc4f8/vblo=5,744.99 2006.176.07:42:01.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.07:42:01.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.07:42:01.91#ibcon#ireg 17 cls_cnt 0 2006.176.07:42:01.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:42:01.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:42:01.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:42:01.91#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:42:01.91#ibcon#first serial, iclass 12, count 0 2006.176.07:42:01.91#ibcon#enter sib2, iclass 12, count 0 2006.176.07:42:01.91#ibcon#flushed, iclass 12, count 0 2006.176.07:42:01.91#ibcon#about to write, iclass 12, count 0 2006.176.07:42:01.91#ibcon#wrote, iclass 12, count 0 2006.176.07:42:01.91#ibcon#about to read 3, iclass 12, count 0 2006.176.07:42:01.93#ibcon#read 3, iclass 12, count 0 2006.176.07:42:01.93#ibcon#about to read 4, iclass 12, count 0 2006.176.07:42:01.93#ibcon#read 4, iclass 12, count 0 2006.176.07:42:01.93#ibcon#about to read 5, iclass 12, count 0 2006.176.07:42:01.93#ibcon#read 5, iclass 12, count 0 2006.176.07:42:01.93#ibcon#about to read 6, iclass 12, count 0 2006.176.07:42:01.93#ibcon#read 6, iclass 12, count 0 2006.176.07:42:01.93#ibcon#end of sib2, iclass 12, count 0 2006.176.07:42:01.93#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:42:01.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:42:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:42:01.93#ibcon#*before write, iclass 12, count 0 2006.176.07:42:01.93#ibcon#enter sib2, iclass 12, count 0 2006.176.07:42:01.93#ibcon#flushed, iclass 12, count 0 2006.176.07:42:01.93#ibcon#about to write, iclass 12, count 0 2006.176.07:42:01.93#ibcon#wrote, iclass 12, count 0 2006.176.07:42:01.93#ibcon#about to read 3, iclass 12, count 0 2006.176.07:42:01.97#ibcon#read 3, iclass 12, count 0 2006.176.07:42:01.97#ibcon#about to read 4, iclass 12, count 0 2006.176.07:42:01.97#ibcon#read 4, iclass 12, count 0 2006.176.07:42:01.97#ibcon#about to read 5, iclass 12, count 0 2006.176.07:42:01.97#ibcon#read 5, iclass 12, count 0 2006.176.07:42:01.97#ibcon#about to read 6, iclass 12, count 0 2006.176.07:42:01.97#ibcon#read 6, iclass 12, count 0 2006.176.07:42:01.97#ibcon#end of sib2, iclass 12, count 0 2006.176.07:42:01.97#ibcon#*after write, iclass 12, count 0 2006.176.07:42:01.97#ibcon#*before return 0, iclass 12, count 0 2006.176.07:42:01.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:42:01.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:42:01.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:42:01.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:42:01.97$vc4f8/vb=5,4 2006.176.07:42:01.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.07:42:01.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.07:42:01.97#ibcon#ireg 11 cls_cnt 2 2006.176.07:42:01.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:42:02.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:42:02.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:42:02.03#ibcon#enter wrdev, iclass 14, count 2 2006.176.07:42:02.03#ibcon#first serial, iclass 14, count 2 2006.176.07:42:02.03#ibcon#enter sib2, iclass 14, count 2 2006.176.07:42:02.03#ibcon#flushed, iclass 14, count 2 2006.176.07:42:02.03#ibcon#about to write, iclass 14, count 2 2006.176.07:42:02.03#ibcon#wrote, iclass 14, count 2 2006.176.07:42:02.03#ibcon#about to read 3, iclass 14, count 2 2006.176.07:42:02.05#ibcon#read 3, iclass 14, count 2 2006.176.07:42:02.05#ibcon#about to read 4, iclass 14, count 2 2006.176.07:42:02.05#ibcon#read 4, iclass 14, count 2 2006.176.07:42:02.05#ibcon#about to read 5, iclass 14, count 2 2006.176.07:42:02.05#ibcon#read 5, iclass 14, count 2 2006.176.07:42:02.05#ibcon#about to read 6, iclass 14, count 2 2006.176.07:42:02.05#ibcon#read 6, iclass 14, count 2 2006.176.07:42:02.05#ibcon#end of sib2, iclass 14, count 2 2006.176.07:42:02.05#ibcon#*mode == 0, iclass 14, count 2 2006.176.07:42:02.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.07:42:02.05#ibcon#[27=AT05-04\r\n] 2006.176.07:42:02.05#ibcon#*before write, iclass 14, count 2 2006.176.07:42:02.05#ibcon#enter sib2, iclass 14, count 2 2006.176.07:42:02.05#ibcon#flushed, iclass 14, count 2 2006.176.07:42:02.05#ibcon#about to write, iclass 14, count 2 2006.176.07:42:02.05#ibcon#wrote, iclass 14, count 2 2006.176.07:42:02.05#ibcon#about to read 3, iclass 14, count 2 2006.176.07:42:02.09#ibcon#read 3, iclass 14, count 2 2006.176.07:42:02.09#ibcon#about to read 4, iclass 14, count 2 2006.176.07:42:02.09#ibcon#read 4, iclass 14, count 2 2006.176.07:42:02.09#ibcon#about to read 5, iclass 14, count 2 2006.176.07:42:02.09#ibcon#read 5, iclass 14, count 2 2006.176.07:42:02.09#ibcon#about to read 6, iclass 14, count 2 2006.176.07:42:02.09#ibcon#read 6, iclass 14, count 2 2006.176.07:42:02.09#ibcon#end of sib2, iclass 14, count 2 2006.176.07:42:02.09#ibcon#*after write, iclass 14, count 2 2006.176.07:42:02.09#ibcon#*before return 0, iclass 14, count 2 2006.176.07:42:02.09#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:42:02.09#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:42:02.09#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.07:42:02.09#ibcon#ireg 7 cls_cnt 0 2006.176.07:42:02.09#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:42:02.21#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:42:02.21#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:42:02.21#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:42:02.21#ibcon#first serial, iclass 14, count 0 2006.176.07:42:02.21#ibcon#enter sib2, iclass 14, count 0 2006.176.07:42:02.21#ibcon#flushed, iclass 14, count 0 2006.176.07:42:02.21#ibcon#about to write, iclass 14, count 0 2006.176.07:42:02.21#ibcon#wrote, iclass 14, count 0 2006.176.07:42:02.21#ibcon#about to read 3, iclass 14, count 0 2006.176.07:42:02.23#ibcon#read 3, iclass 14, count 0 2006.176.07:42:02.23#ibcon#about to read 4, iclass 14, count 0 2006.176.07:42:02.23#ibcon#read 4, iclass 14, count 0 2006.176.07:42:02.23#ibcon#about to read 5, iclass 14, count 0 2006.176.07:42:02.23#ibcon#read 5, iclass 14, count 0 2006.176.07:42:02.23#ibcon#about to read 6, iclass 14, count 0 2006.176.07:42:02.23#ibcon#read 6, iclass 14, count 0 2006.176.07:42:02.23#ibcon#end of sib2, iclass 14, count 0 2006.176.07:42:02.23#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:42:02.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:42:02.23#ibcon#[27=USB\r\n] 2006.176.07:42:02.23#ibcon#*before write, iclass 14, count 0 2006.176.07:42:02.23#ibcon#enter sib2, iclass 14, count 0 2006.176.07:42:02.23#ibcon#flushed, iclass 14, count 0 2006.176.07:42:02.23#ibcon#about to write, iclass 14, count 0 2006.176.07:42:02.23#ibcon#wrote, iclass 14, count 0 2006.176.07:42:02.23#ibcon#about to read 3, iclass 14, count 0 2006.176.07:42:02.26#ibcon#read 3, iclass 14, count 0 2006.176.07:42:02.26#ibcon#about to read 4, iclass 14, count 0 2006.176.07:42:02.26#ibcon#read 4, iclass 14, count 0 2006.176.07:42:02.26#ibcon#about to read 5, iclass 14, count 0 2006.176.07:42:02.26#ibcon#read 5, iclass 14, count 0 2006.176.07:42:02.26#ibcon#about to read 6, iclass 14, count 0 2006.176.07:42:02.26#ibcon#read 6, iclass 14, count 0 2006.176.07:42:02.26#ibcon#end of sib2, iclass 14, count 0 2006.176.07:42:02.26#ibcon#*after write, iclass 14, count 0 2006.176.07:42:02.26#ibcon#*before return 0, iclass 14, count 0 2006.176.07:42:02.26#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:42:02.26#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:42:02.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:42:02.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:42:02.26$vc4f8/vblo=6,752.99 2006.176.07:42:02.26#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:42:02.26#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:42:02.26#ibcon#ireg 17 cls_cnt 0 2006.176.07:42:02.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:42:02.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:42:02.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:42:02.26#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:42:02.26#ibcon#first serial, iclass 16, count 0 2006.176.07:42:02.26#ibcon#enter sib2, iclass 16, count 0 2006.176.07:42:02.26#ibcon#flushed, iclass 16, count 0 2006.176.07:42:02.26#ibcon#about to write, iclass 16, count 0 2006.176.07:42:02.26#ibcon#wrote, iclass 16, count 0 2006.176.07:42:02.26#ibcon#about to read 3, iclass 16, count 0 2006.176.07:42:02.28#ibcon#read 3, iclass 16, count 0 2006.176.07:42:02.28#ibcon#about to read 4, iclass 16, count 0 2006.176.07:42:02.28#ibcon#read 4, iclass 16, count 0 2006.176.07:42:02.28#ibcon#about to read 5, iclass 16, count 0 2006.176.07:42:02.28#ibcon#read 5, iclass 16, count 0 2006.176.07:42:02.28#ibcon#about to read 6, iclass 16, count 0 2006.176.07:42:02.28#ibcon#read 6, iclass 16, count 0 2006.176.07:42:02.28#ibcon#end of sib2, iclass 16, count 0 2006.176.07:42:02.28#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:42:02.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:42:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:42:02.28#ibcon#*before write, iclass 16, count 0 2006.176.07:42:02.28#ibcon#enter sib2, iclass 16, count 0 2006.176.07:42:02.28#ibcon#flushed, iclass 16, count 0 2006.176.07:42:02.28#ibcon#about to write, iclass 16, count 0 2006.176.07:42:02.28#ibcon#wrote, iclass 16, count 0 2006.176.07:42:02.28#ibcon#about to read 3, iclass 16, count 0 2006.176.07:42:02.32#ibcon#read 3, iclass 16, count 0 2006.176.07:42:02.32#ibcon#about to read 4, iclass 16, count 0 2006.176.07:42:02.32#ibcon#read 4, iclass 16, count 0 2006.176.07:42:02.32#ibcon#about to read 5, iclass 16, count 0 2006.176.07:42:02.32#ibcon#read 5, iclass 16, count 0 2006.176.07:42:02.32#ibcon#about to read 6, iclass 16, count 0 2006.176.07:42:02.32#ibcon#read 6, iclass 16, count 0 2006.176.07:42:02.32#ibcon#end of sib2, iclass 16, count 0 2006.176.07:42:02.32#ibcon#*after write, iclass 16, count 0 2006.176.07:42:02.32#ibcon#*before return 0, iclass 16, count 0 2006.176.07:42:02.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:42:02.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:42:02.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:42:02.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:42:02.32$vc4f8/vb=6,4 2006.176.07:42:02.32#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.07:42:02.32#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.07:42:02.32#ibcon#ireg 11 cls_cnt 2 2006.176.07:42:02.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:42:02.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:42:02.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:42:02.38#ibcon#enter wrdev, iclass 18, count 2 2006.176.07:42:02.38#ibcon#first serial, iclass 18, count 2 2006.176.07:42:02.38#ibcon#enter sib2, iclass 18, count 2 2006.176.07:42:02.38#ibcon#flushed, iclass 18, count 2 2006.176.07:42:02.38#ibcon#about to write, iclass 18, count 2 2006.176.07:42:02.38#ibcon#wrote, iclass 18, count 2 2006.176.07:42:02.38#ibcon#about to read 3, iclass 18, count 2 2006.176.07:42:02.40#ibcon#read 3, iclass 18, count 2 2006.176.07:42:02.40#ibcon#about to read 4, iclass 18, count 2 2006.176.07:42:02.40#ibcon#read 4, iclass 18, count 2 2006.176.07:42:02.40#ibcon#about to read 5, iclass 18, count 2 2006.176.07:42:02.40#ibcon#read 5, iclass 18, count 2 2006.176.07:42:02.40#ibcon#about to read 6, iclass 18, count 2 2006.176.07:42:02.40#ibcon#read 6, iclass 18, count 2 2006.176.07:42:02.40#ibcon#end of sib2, iclass 18, count 2 2006.176.07:42:02.40#ibcon#*mode == 0, iclass 18, count 2 2006.176.07:42:02.40#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.07:42:02.40#ibcon#[27=AT06-04\r\n] 2006.176.07:42:02.40#ibcon#*before write, iclass 18, count 2 2006.176.07:42:02.40#ibcon#enter sib2, iclass 18, count 2 2006.176.07:42:02.40#ibcon#flushed, iclass 18, count 2 2006.176.07:42:02.40#ibcon#about to write, iclass 18, count 2 2006.176.07:42:02.40#ibcon#wrote, iclass 18, count 2 2006.176.07:42:02.40#ibcon#about to read 3, iclass 18, count 2 2006.176.07:42:02.43#ibcon#read 3, iclass 18, count 2 2006.176.07:42:02.43#ibcon#about to read 4, iclass 18, count 2 2006.176.07:42:02.43#ibcon#read 4, iclass 18, count 2 2006.176.07:42:02.43#ibcon#about to read 5, iclass 18, count 2 2006.176.07:42:02.43#ibcon#read 5, iclass 18, count 2 2006.176.07:42:02.43#ibcon#about to read 6, iclass 18, count 2 2006.176.07:42:02.43#ibcon#read 6, iclass 18, count 2 2006.176.07:42:02.43#ibcon#end of sib2, iclass 18, count 2 2006.176.07:42:02.43#ibcon#*after write, iclass 18, count 2 2006.176.07:42:02.43#ibcon#*before return 0, iclass 18, count 2 2006.176.07:42:02.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:42:02.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:42:02.43#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.07:42:02.43#ibcon#ireg 7 cls_cnt 0 2006.176.07:42:02.43#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:42:02.55#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:42:02.55#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:42:02.55#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:42:02.55#ibcon#first serial, iclass 18, count 0 2006.176.07:42:02.55#ibcon#enter sib2, iclass 18, count 0 2006.176.07:42:02.55#ibcon#flushed, iclass 18, count 0 2006.176.07:42:02.55#ibcon#about to write, iclass 18, count 0 2006.176.07:42:02.55#ibcon#wrote, iclass 18, count 0 2006.176.07:42:02.55#ibcon#about to read 3, iclass 18, count 0 2006.176.07:42:02.57#ibcon#read 3, iclass 18, count 0 2006.176.07:42:02.57#ibcon#about to read 4, iclass 18, count 0 2006.176.07:42:02.57#ibcon#read 4, iclass 18, count 0 2006.176.07:42:02.57#ibcon#about to read 5, iclass 18, count 0 2006.176.07:42:02.57#ibcon#read 5, iclass 18, count 0 2006.176.07:42:02.57#ibcon#about to read 6, iclass 18, count 0 2006.176.07:42:02.57#ibcon#read 6, iclass 18, count 0 2006.176.07:42:02.57#ibcon#end of sib2, iclass 18, count 0 2006.176.07:42:02.57#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:42:02.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:42:02.57#ibcon#[27=USB\r\n] 2006.176.07:42:02.57#ibcon#*before write, iclass 18, count 0 2006.176.07:42:02.57#ibcon#enter sib2, iclass 18, count 0 2006.176.07:42:02.57#ibcon#flushed, iclass 18, count 0 2006.176.07:42:02.57#ibcon#about to write, iclass 18, count 0 2006.176.07:42:02.57#ibcon#wrote, iclass 18, count 0 2006.176.07:42:02.57#ibcon#about to read 3, iclass 18, count 0 2006.176.07:42:02.60#ibcon#read 3, iclass 18, count 0 2006.176.07:42:02.60#ibcon#about to read 4, iclass 18, count 0 2006.176.07:42:02.60#ibcon#read 4, iclass 18, count 0 2006.176.07:42:02.60#ibcon#about to read 5, iclass 18, count 0 2006.176.07:42:02.60#ibcon#read 5, iclass 18, count 0 2006.176.07:42:02.60#ibcon#about to read 6, iclass 18, count 0 2006.176.07:42:02.60#ibcon#read 6, iclass 18, count 0 2006.176.07:42:02.60#ibcon#end of sib2, iclass 18, count 0 2006.176.07:42:02.60#ibcon#*after write, iclass 18, count 0 2006.176.07:42:02.60#ibcon#*before return 0, iclass 18, count 0 2006.176.07:42:02.60#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:42:02.60#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:42:02.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:42:02.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:42:02.60$vc4f8/vabw=wide 2006.176.07:42:02.60#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.07:42:02.60#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.07:42:02.60#ibcon#ireg 8 cls_cnt 0 2006.176.07:42:02.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:42:02.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:42:02.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:42:02.60#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:42:02.60#ibcon#first serial, iclass 20, count 0 2006.176.07:42:02.60#ibcon#enter sib2, iclass 20, count 0 2006.176.07:42:02.60#ibcon#flushed, iclass 20, count 0 2006.176.07:42:02.60#ibcon#about to write, iclass 20, count 0 2006.176.07:42:02.60#ibcon#wrote, iclass 20, count 0 2006.176.07:42:02.60#ibcon#about to read 3, iclass 20, count 0 2006.176.07:42:02.62#ibcon#read 3, iclass 20, count 0 2006.176.07:42:02.62#ibcon#about to read 4, iclass 20, count 0 2006.176.07:42:02.62#ibcon#read 4, iclass 20, count 0 2006.176.07:42:02.62#ibcon#about to read 5, iclass 20, count 0 2006.176.07:42:02.62#ibcon#read 5, iclass 20, count 0 2006.176.07:42:02.62#ibcon#about to read 6, iclass 20, count 0 2006.176.07:42:02.62#ibcon#read 6, iclass 20, count 0 2006.176.07:42:02.62#ibcon#end of sib2, iclass 20, count 0 2006.176.07:42:02.62#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:42:02.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:42:02.62#ibcon#[25=BW32\r\n] 2006.176.07:42:02.62#ibcon#*before write, iclass 20, count 0 2006.176.07:42:02.62#ibcon#enter sib2, iclass 20, count 0 2006.176.07:42:02.62#ibcon#flushed, iclass 20, count 0 2006.176.07:42:02.62#ibcon#about to write, iclass 20, count 0 2006.176.07:42:02.62#ibcon#wrote, iclass 20, count 0 2006.176.07:42:02.62#ibcon#about to read 3, iclass 20, count 0 2006.176.07:42:02.65#ibcon#read 3, iclass 20, count 0 2006.176.07:42:02.65#ibcon#about to read 4, iclass 20, count 0 2006.176.07:42:02.65#ibcon#read 4, iclass 20, count 0 2006.176.07:42:02.65#ibcon#about to read 5, iclass 20, count 0 2006.176.07:42:02.65#ibcon#read 5, iclass 20, count 0 2006.176.07:42:02.65#ibcon#about to read 6, iclass 20, count 0 2006.176.07:42:02.65#ibcon#read 6, iclass 20, count 0 2006.176.07:42:02.65#ibcon#end of sib2, iclass 20, count 0 2006.176.07:42:02.65#ibcon#*after write, iclass 20, count 0 2006.176.07:42:02.65#ibcon#*before return 0, iclass 20, count 0 2006.176.07:42:02.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:42:02.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:42:02.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:42:02.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:42:02.65$vc4f8/vbbw=wide 2006.176.07:42:02.65#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.07:42:02.65#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.07:42:02.65#ibcon#ireg 8 cls_cnt 0 2006.176.07:42:02.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:42:02.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:42:02.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:42:02.72#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:42:02.72#ibcon#first serial, iclass 22, count 0 2006.176.07:42:02.72#ibcon#enter sib2, iclass 22, count 0 2006.176.07:42:02.72#ibcon#flushed, iclass 22, count 0 2006.176.07:42:02.72#ibcon#about to write, iclass 22, count 0 2006.176.07:42:02.72#ibcon#wrote, iclass 22, count 0 2006.176.07:42:02.72#ibcon#about to read 3, iclass 22, count 0 2006.176.07:42:02.74#ibcon#read 3, iclass 22, count 0 2006.176.07:42:02.74#ibcon#about to read 4, iclass 22, count 0 2006.176.07:42:02.74#ibcon#read 4, iclass 22, count 0 2006.176.07:42:02.74#ibcon#about to read 5, iclass 22, count 0 2006.176.07:42:02.74#ibcon#read 5, iclass 22, count 0 2006.176.07:42:02.74#ibcon#about to read 6, iclass 22, count 0 2006.176.07:42:02.74#ibcon#read 6, iclass 22, count 0 2006.176.07:42:02.74#ibcon#end of sib2, iclass 22, count 0 2006.176.07:42:02.74#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:42:02.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:42:02.74#ibcon#[27=BW32\r\n] 2006.176.07:42:02.74#ibcon#*before write, iclass 22, count 0 2006.176.07:42:02.74#ibcon#enter sib2, iclass 22, count 0 2006.176.07:42:02.74#ibcon#flushed, iclass 22, count 0 2006.176.07:42:02.74#ibcon#about to write, iclass 22, count 0 2006.176.07:42:02.74#ibcon#wrote, iclass 22, count 0 2006.176.07:42:02.74#ibcon#about to read 3, iclass 22, count 0 2006.176.07:42:02.77#ibcon#read 3, iclass 22, count 0 2006.176.07:42:02.77#ibcon#about to read 4, iclass 22, count 0 2006.176.07:42:02.77#ibcon#read 4, iclass 22, count 0 2006.176.07:42:02.77#ibcon#about to read 5, iclass 22, count 0 2006.176.07:42:02.77#ibcon#read 5, iclass 22, count 0 2006.176.07:42:02.77#ibcon#about to read 6, iclass 22, count 0 2006.176.07:42:02.77#ibcon#read 6, iclass 22, count 0 2006.176.07:42:02.77#ibcon#end of sib2, iclass 22, count 0 2006.176.07:42:02.77#ibcon#*after write, iclass 22, count 0 2006.176.07:42:02.77#ibcon#*before return 0, iclass 22, count 0 2006.176.07:42:02.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:42:02.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:42:02.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:42:02.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:42:02.77$4f8m12a/ifd4f 2006.176.07:42:02.77$ifd4f/lo= 2006.176.07:42:02.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:42:02.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:42:02.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:42:02.77$ifd4f/patch= 2006.176.07:42:02.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:42:02.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:42:02.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:42:02.77$4f8m12a/"form=m,16.000,1:2 2006.176.07:42:02.77$4f8m12a/"tpicd 2006.176.07:42:02.77$4f8m12a/echo=off 2006.176.07:42:02.77$4f8m12a/xlog=off 2006.176.07:42:02.77:!2006.176.07:43:00 2006.176.07:42:35.13#trakl#Source acquired 2006.176.07:42:36.13#flagr#flagr/antenna,acquired 2006.176.07:43:00.00:preob 2006.176.07:43:01.14/onsource/TRACKING 2006.176.07:43:01.14:!2006.176.07:43:10 2006.176.07:43:10.00:data_valid=on 2006.176.07:43:10.00:midob 2006.176.07:43:10.14/onsource/TRACKING 2006.176.07:43:10.14/wx/23.92,1008.4,91 2006.176.07:43:10.21/cable/+6.4945E-03 2006.176.07:43:11.30/va/01,08,usb,yes,29,31 2006.176.07:43:11.30/va/02,07,usb,yes,29,30 2006.176.07:43:11.30/va/03,06,usb,yes,31,31 2006.176.07:43:11.30/va/04,07,usb,yes,30,32 2006.176.07:43:11.30/va/05,07,usb,yes,31,33 2006.176.07:43:11.30/va/06,06,usb,yes,30,30 2006.176.07:43:11.30/va/07,06,usb,yes,31,30 2006.176.07:43:11.30/va/08,06,usb,yes,33,32 2006.176.07:43:11.53/valo/01,532.99,yes,locked 2006.176.07:43:11.53/valo/02,572.99,yes,locked 2006.176.07:43:11.53/valo/03,672.99,yes,locked 2006.176.07:43:11.53/valo/04,832.99,yes,locked 2006.176.07:43:11.53/valo/05,652.99,yes,locked 2006.176.07:43:11.53/valo/06,772.99,yes,locked 2006.176.07:43:11.53/valo/07,832.99,yes,locked 2006.176.07:43:11.53/valo/08,852.99,yes,locked 2006.176.07:43:12.62/vb/01,04,usb,yes,29,28 2006.176.07:43:12.62/vb/02,04,usb,yes,31,32 2006.176.07:43:12.62/vb/03,04,usb,yes,27,31 2006.176.07:43:12.62/vb/04,04,usb,yes,28,28 2006.176.07:43:12.62/vb/05,04,usb,yes,27,31 2006.176.07:43:12.62/vb/06,04,usb,yes,28,30 2006.176.07:43:12.62/vb/07,04,usb,yes,30,29 2006.176.07:43:12.62/vb/08,04,usb,yes,27,31 2006.176.07:43:12.85/vblo/01,632.99,yes,locked 2006.176.07:43:12.85/vblo/02,640.99,yes,locked 2006.176.07:43:12.85/vblo/03,656.99,yes,locked 2006.176.07:43:12.85/vblo/04,712.99,yes,locked 2006.176.07:43:12.85/vblo/05,744.99,yes,locked 2006.176.07:43:12.85/vblo/06,752.99,yes,locked 2006.176.07:43:12.85/vblo/07,734.99,yes,locked 2006.176.07:43:12.85/vblo/08,744.99,yes,locked 2006.176.07:43:13.00/vabw/8 2006.176.07:43:13.15/vbbw/8 2006.176.07:43:13.27/xfe/off,on,14.2 2006.176.07:43:13.66/ifatt/23,28,28,28 2006.176.07:43:14.08/fmout-gps/S +3.74E-07 2006.176.07:43:14.15:!2006.176.07:45:20 2006.176.07:45:20.00:data_valid=off 2006.176.07:45:20.00:postob 2006.176.07:45:20.14/cable/+6.4935E-03 2006.176.07:45:20.14/wx/23.91,1008.4,91 2006.176.07:45:21.08/fmout-gps/S +3.75E-07 2006.176.07:45:21.08:scan_name=176-0746,k06176,60 2006.176.07:45:21.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.176.07:45:22.14#flagr#flagr/antenna,new-source 2006.176.07:45:22.14:checkk5 2006.176.07:45:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:45:22.93/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:45:23.34/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:45:23.78/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:45:24.16/chk_obsdata//k5ts1/T1760743??a.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.176.07:45:24.52/chk_obsdata//k5ts2/T1760743??b.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.176.07:45:24.89/chk_obsdata//k5ts3/T1760743??c.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.176.07:45:25.26/chk_obsdata//k5ts4/T1760743??d.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.176.07:45:25.95/k5log//k5ts1_log_newline 2006.176.07:45:26.66/k5log//k5ts2_log_newline 2006.176.07:45:27.37/k5log//k5ts3_log_newline 2006.176.07:45:28.06/k5log//k5ts4_log_newline 2006.176.07:45:28.08/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:45:28.08:4f8m12a=1 2006.176.07:45:28.09$4f8m12a/echo=on 2006.176.07:45:28.09$4f8m12a/pcalon 2006.176.07:45:28.09$pcalon/"no phase cal control is implemented here 2006.176.07:45:28.09$4f8m12a/"tpicd=stop 2006.176.07:45:28.09$4f8m12a/vc4f8 2006.176.07:45:28.09$vc4f8/valo=1,532.99 2006.176.07:45:28.09#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.07:45:28.09#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.07:45:28.09#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:28.09#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:28.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:28.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:28.09#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:45:28.09#ibcon#first serial, iclass 28, count 0 2006.176.07:45:28.09#ibcon#enter sib2, iclass 28, count 0 2006.176.07:45:28.09#ibcon#flushed, iclass 28, count 0 2006.176.07:45:28.09#ibcon#about to write, iclass 28, count 0 2006.176.07:45:28.09#ibcon#wrote, iclass 28, count 0 2006.176.07:45:28.09#ibcon#about to read 3, iclass 28, count 0 2006.176.07:45:28.13#ibcon#read 3, iclass 28, count 0 2006.176.07:45:28.13#ibcon#about to read 4, iclass 28, count 0 2006.176.07:45:28.13#ibcon#read 4, iclass 28, count 0 2006.176.07:45:28.13#ibcon#about to read 5, iclass 28, count 0 2006.176.07:45:28.13#ibcon#read 5, iclass 28, count 0 2006.176.07:45:28.13#ibcon#about to read 6, iclass 28, count 0 2006.176.07:45:28.13#ibcon#read 6, iclass 28, count 0 2006.176.07:45:28.13#ibcon#end of sib2, iclass 28, count 0 2006.176.07:45:28.13#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:45:28.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:45:28.13#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:45:28.13#ibcon#*before write, iclass 28, count 0 2006.176.07:45:28.13#ibcon#enter sib2, iclass 28, count 0 2006.176.07:45:28.13#ibcon#flushed, iclass 28, count 0 2006.176.07:45:28.13#ibcon#about to write, iclass 28, count 0 2006.176.07:45:28.13#ibcon#wrote, iclass 28, count 0 2006.176.07:45:28.13#ibcon#about to read 3, iclass 28, count 0 2006.176.07:45:28.18#ibcon#read 3, iclass 28, count 0 2006.176.07:45:28.18#ibcon#about to read 4, iclass 28, count 0 2006.176.07:45:28.18#ibcon#read 4, iclass 28, count 0 2006.176.07:45:28.18#ibcon#about to read 5, iclass 28, count 0 2006.176.07:45:28.18#ibcon#read 5, iclass 28, count 0 2006.176.07:45:28.18#ibcon#about to read 6, iclass 28, count 0 2006.176.07:45:28.18#ibcon#read 6, iclass 28, count 0 2006.176.07:45:28.18#ibcon#end of sib2, iclass 28, count 0 2006.176.07:45:28.18#ibcon#*after write, iclass 28, count 0 2006.176.07:45:28.18#ibcon#*before return 0, iclass 28, count 0 2006.176.07:45:28.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:28.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:28.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:45:28.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:45:28.18$vc4f8/va=1,8 2006.176.07:45:28.18#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.07:45:28.18#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.07:45:28.18#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:28.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:28.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:28.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:28.18#ibcon#enter wrdev, iclass 30, count 2 2006.176.07:45:28.18#ibcon#first serial, iclass 30, count 2 2006.176.07:45:28.18#ibcon#enter sib2, iclass 30, count 2 2006.176.07:45:28.18#ibcon#flushed, iclass 30, count 2 2006.176.07:45:28.18#ibcon#about to write, iclass 30, count 2 2006.176.07:45:28.18#ibcon#wrote, iclass 30, count 2 2006.176.07:45:28.18#ibcon#about to read 3, iclass 30, count 2 2006.176.07:45:28.20#ibcon#read 3, iclass 30, count 2 2006.176.07:45:28.20#ibcon#about to read 4, iclass 30, count 2 2006.176.07:45:28.20#ibcon#read 4, iclass 30, count 2 2006.176.07:45:28.20#ibcon#about to read 5, iclass 30, count 2 2006.176.07:45:28.20#ibcon#read 5, iclass 30, count 2 2006.176.07:45:28.20#ibcon#about to read 6, iclass 30, count 2 2006.176.07:45:28.20#ibcon#read 6, iclass 30, count 2 2006.176.07:45:28.20#ibcon#end of sib2, iclass 30, count 2 2006.176.07:45:28.20#ibcon#*mode == 0, iclass 30, count 2 2006.176.07:45:28.20#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.07:45:28.20#ibcon#[25=AT01-08\r\n] 2006.176.07:45:28.20#ibcon#*before write, iclass 30, count 2 2006.176.07:45:28.20#ibcon#enter sib2, iclass 30, count 2 2006.176.07:45:28.20#ibcon#flushed, iclass 30, count 2 2006.176.07:45:28.20#ibcon#about to write, iclass 30, count 2 2006.176.07:45:28.20#ibcon#wrote, iclass 30, count 2 2006.176.07:45:28.20#ibcon#about to read 3, iclass 30, count 2 2006.176.07:45:28.23#ibcon#read 3, iclass 30, count 2 2006.176.07:45:28.23#ibcon#about to read 4, iclass 30, count 2 2006.176.07:45:28.23#ibcon#read 4, iclass 30, count 2 2006.176.07:45:28.23#ibcon#about to read 5, iclass 30, count 2 2006.176.07:45:28.23#ibcon#read 5, iclass 30, count 2 2006.176.07:45:28.23#ibcon#about to read 6, iclass 30, count 2 2006.176.07:45:28.23#ibcon#read 6, iclass 30, count 2 2006.176.07:45:28.23#ibcon#end of sib2, iclass 30, count 2 2006.176.07:45:28.23#ibcon#*after write, iclass 30, count 2 2006.176.07:45:28.23#ibcon#*before return 0, iclass 30, count 2 2006.176.07:45:28.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:28.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:28.23#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.07:45:28.23#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:28.23#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:28.35#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:28.35#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:28.35#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:45:28.35#ibcon#first serial, iclass 30, count 0 2006.176.07:45:28.35#ibcon#enter sib2, iclass 30, count 0 2006.176.07:45:28.35#ibcon#flushed, iclass 30, count 0 2006.176.07:45:28.35#ibcon#about to write, iclass 30, count 0 2006.176.07:45:28.35#ibcon#wrote, iclass 30, count 0 2006.176.07:45:28.35#ibcon#about to read 3, iclass 30, count 0 2006.176.07:45:28.37#ibcon#read 3, iclass 30, count 0 2006.176.07:45:28.37#ibcon#about to read 4, iclass 30, count 0 2006.176.07:45:28.37#ibcon#read 4, iclass 30, count 0 2006.176.07:45:28.37#ibcon#about to read 5, iclass 30, count 0 2006.176.07:45:28.37#ibcon#read 5, iclass 30, count 0 2006.176.07:45:28.37#ibcon#about to read 6, iclass 30, count 0 2006.176.07:45:28.37#ibcon#read 6, iclass 30, count 0 2006.176.07:45:28.37#ibcon#end of sib2, iclass 30, count 0 2006.176.07:45:28.37#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:45:28.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:45:28.37#ibcon#[25=USB\r\n] 2006.176.07:45:28.37#ibcon#*before write, iclass 30, count 0 2006.176.07:45:28.37#ibcon#enter sib2, iclass 30, count 0 2006.176.07:45:28.37#ibcon#flushed, iclass 30, count 0 2006.176.07:45:28.37#ibcon#about to write, iclass 30, count 0 2006.176.07:45:28.37#ibcon#wrote, iclass 30, count 0 2006.176.07:45:28.37#ibcon#about to read 3, iclass 30, count 0 2006.176.07:45:28.40#ibcon#read 3, iclass 30, count 0 2006.176.07:45:28.40#ibcon#about to read 4, iclass 30, count 0 2006.176.07:45:28.40#ibcon#read 4, iclass 30, count 0 2006.176.07:45:28.40#ibcon#about to read 5, iclass 30, count 0 2006.176.07:45:28.40#ibcon#read 5, iclass 30, count 0 2006.176.07:45:28.40#ibcon#about to read 6, iclass 30, count 0 2006.176.07:45:28.40#ibcon#read 6, iclass 30, count 0 2006.176.07:45:28.40#ibcon#end of sib2, iclass 30, count 0 2006.176.07:45:28.40#ibcon#*after write, iclass 30, count 0 2006.176.07:45:28.40#ibcon#*before return 0, iclass 30, count 0 2006.176.07:45:28.40#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:28.40#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:28.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:45:28.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:45:28.40$vc4f8/valo=2,572.99 2006.176.07:45:28.40#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.07:45:28.40#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.07:45:28.40#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:28.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:28.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:28.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:28.40#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:45:28.40#ibcon#first serial, iclass 32, count 0 2006.176.07:45:28.40#ibcon#enter sib2, iclass 32, count 0 2006.176.07:45:28.40#ibcon#flushed, iclass 32, count 0 2006.176.07:45:28.40#ibcon#about to write, iclass 32, count 0 2006.176.07:45:28.40#ibcon#wrote, iclass 32, count 0 2006.176.07:45:28.40#ibcon#about to read 3, iclass 32, count 0 2006.176.07:45:28.42#ibcon#read 3, iclass 32, count 0 2006.176.07:45:28.42#ibcon#about to read 4, iclass 32, count 0 2006.176.07:45:28.42#ibcon#read 4, iclass 32, count 0 2006.176.07:45:28.42#ibcon#about to read 5, iclass 32, count 0 2006.176.07:45:28.42#ibcon#read 5, iclass 32, count 0 2006.176.07:45:28.42#ibcon#about to read 6, iclass 32, count 0 2006.176.07:45:28.42#ibcon#read 6, iclass 32, count 0 2006.176.07:45:28.42#ibcon#end of sib2, iclass 32, count 0 2006.176.07:45:28.42#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:45:28.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:45:28.42#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:45:28.42#ibcon#*before write, iclass 32, count 0 2006.176.07:45:28.42#ibcon#enter sib2, iclass 32, count 0 2006.176.07:45:28.42#ibcon#flushed, iclass 32, count 0 2006.176.07:45:28.42#ibcon#about to write, iclass 32, count 0 2006.176.07:45:28.42#ibcon#wrote, iclass 32, count 0 2006.176.07:45:28.42#ibcon#about to read 3, iclass 32, count 0 2006.176.07:45:28.46#ibcon#read 3, iclass 32, count 0 2006.176.07:45:28.46#ibcon#about to read 4, iclass 32, count 0 2006.176.07:45:28.46#ibcon#read 4, iclass 32, count 0 2006.176.07:45:28.46#ibcon#about to read 5, iclass 32, count 0 2006.176.07:45:28.46#ibcon#read 5, iclass 32, count 0 2006.176.07:45:28.46#ibcon#about to read 6, iclass 32, count 0 2006.176.07:45:28.46#ibcon#read 6, iclass 32, count 0 2006.176.07:45:28.46#ibcon#end of sib2, iclass 32, count 0 2006.176.07:45:28.46#ibcon#*after write, iclass 32, count 0 2006.176.07:45:28.46#ibcon#*before return 0, iclass 32, count 0 2006.176.07:45:28.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:28.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:28.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:45:28.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:45:28.46$vc4f8/va=2,7 2006.176.07:45:28.46#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.07:45:28.46#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.07:45:28.46#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:28.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:28.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:28.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:28.52#ibcon#enter wrdev, iclass 34, count 2 2006.176.07:45:28.52#ibcon#first serial, iclass 34, count 2 2006.176.07:45:28.52#ibcon#enter sib2, iclass 34, count 2 2006.176.07:45:28.52#ibcon#flushed, iclass 34, count 2 2006.176.07:45:28.52#ibcon#about to write, iclass 34, count 2 2006.176.07:45:28.52#ibcon#wrote, iclass 34, count 2 2006.176.07:45:28.52#ibcon#about to read 3, iclass 34, count 2 2006.176.07:45:28.54#ibcon#read 3, iclass 34, count 2 2006.176.07:45:28.54#ibcon#about to read 4, iclass 34, count 2 2006.176.07:45:28.54#ibcon#read 4, iclass 34, count 2 2006.176.07:45:28.54#ibcon#about to read 5, iclass 34, count 2 2006.176.07:45:28.54#ibcon#read 5, iclass 34, count 2 2006.176.07:45:28.54#ibcon#about to read 6, iclass 34, count 2 2006.176.07:45:28.54#ibcon#read 6, iclass 34, count 2 2006.176.07:45:28.54#ibcon#end of sib2, iclass 34, count 2 2006.176.07:45:28.54#ibcon#*mode == 0, iclass 34, count 2 2006.176.07:45:28.54#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.07:45:28.54#ibcon#[25=AT02-07\r\n] 2006.176.07:45:28.54#ibcon#*before write, iclass 34, count 2 2006.176.07:45:28.54#ibcon#enter sib2, iclass 34, count 2 2006.176.07:45:28.54#ibcon#flushed, iclass 34, count 2 2006.176.07:45:28.54#ibcon#about to write, iclass 34, count 2 2006.176.07:45:28.54#ibcon#wrote, iclass 34, count 2 2006.176.07:45:28.54#ibcon#about to read 3, iclass 34, count 2 2006.176.07:45:28.57#ibcon#read 3, iclass 34, count 2 2006.176.07:45:28.57#ibcon#about to read 4, iclass 34, count 2 2006.176.07:45:28.57#ibcon#read 4, iclass 34, count 2 2006.176.07:45:28.57#ibcon#about to read 5, iclass 34, count 2 2006.176.07:45:28.57#ibcon#read 5, iclass 34, count 2 2006.176.07:45:28.57#ibcon#about to read 6, iclass 34, count 2 2006.176.07:45:28.57#ibcon#read 6, iclass 34, count 2 2006.176.07:45:28.57#ibcon#end of sib2, iclass 34, count 2 2006.176.07:45:28.57#ibcon#*after write, iclass 34, count 2 2006.176.07:45:28.57#ibcon#*before return 0, iclass 34, count 2 2006.176.07:45:28.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:28.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:28.57#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.07:45:28.57#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:28.57#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:28.69#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:28.69#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:28.69#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:45:28.69#ibcon#first serial, iclass 34, count 0 2006.176.07:45:28.69#ibcon#enter sib2, iclass 34, count 0 2006.176.07:45:28.69#ibcon#flushed, iclass 34, count 0 2006.176.07:45:28.69#ibcon#about to write, iclass 34, count 0 2006.176.07:45:28.69#ibcon#wrote, iclass 34, count 0 2006.176.07:45:28.69#ibcon#about to read 3, iclass 34, count 0 2006.176.07:45:28.71#ibcon#read 3, iclass 34, count 0 2006.176.07:45:28.71#ibcon#about to read 4, iclass 34, count 0 2006.176.07:45:28.71#ibcon#read 4, iclass 34, count 0 2006.176.07:45:28.71#ibcon#about to read 5, iclass 34, count 0 2006.176.07:45:28.71#ibcon#read 5, iclass 34, count 0 2006.176.07:45:28.71#ibcon#about to read 6, iclass 34, count 0 2006.176.07:45:28.71#ibcon#read 6, iclass 34, count 0 2006.176.07:45:28.71#ibcon#end of sib2, iclass 34, count 0 2006.176.07:45:28.71#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:45:28.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:45:28.71#ibcon#[25=USB\r\n] 2006.176.07:45:28.71#ibcon#*before write, iclass 34, count 0 2006.176.07:45:28.71#ibcon#enter sib2, iclass 34, count 0 2006.176.07:45:28.71#ibcon#flushed, iclass 34, count 0 2006.176.07:45:28.71#ibcon#about to write, iclass 34, count 0 2006.176.07:45:28.71#ibcon#wrote, iclass 34, count 0 2006.176.07:45:28.71#ibcon#about to read 3, iclass 34, count 0 2006.176.07:45:28.74#ibcon#read 3, iclass 34, count 0 2006.176.07:45:28.74#ibcon#about to read 4, iclass 34, count 0 2006.176.07:45:28.74#ibcon#read 4, iclass 34, count 0 2006.176.07:45:28.74#ibcon#about to read 5, iclass 34, count 0 2006.176.07:45:28.74#ibcon#read 5, iclass 34, count 0 2006.176.07:45:28.74#ibcon#about to read 6, iclass 34, count 0 2006.176.07:45:28.74#ibcon#read 6, iclass 34, count 0 2006.176.07:45:28.74#ibcon#end of sib2, iclass 34, count 0 2006.176.07:45:28.74#ibcon#*after write, iclass 34, count 0 2006.176.07:45:28.74#ibcon#*before return 0, iclass 34, count 0 2006.176.07:45:28.74#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:28.74#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:28.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:45:28.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:45:28.74$vc4f8/valo=3,672.99 2006.176.07:45:28.74#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.07:45:28.74#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.07:45:28.74#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:28.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:45:28.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:45:28.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:45:28.74#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:45:28.74#ibcon#first serial, iclass 36, count 0 2006.176.07:45:28.74#ibcon#enter sib2, iclass 36, count 0 2006.176.07:45:28.74#ibcon#flushed, iclass 36, count 0 2006.176.07:45:28.74#ibcon#about to write, iclass 36, count 0 2006.176.07:45:28.74#ibcon#wrote, iclass 36, count 0 2006.176.07:45:28.74#ibcon#about to read 3, iclass 36, count 0 2006.176.07:45:28.76#ibcon#read 3, iclass 36, count 0 2006.176.07:45:28.76#ibcon#about to read 4, iclass 36, count 0 2006.176.07:45:28.76#ibcon#read 4, iclass 36, count 0 2006.176.07:45:28.76#ibcon#about to read 5, iclass 36, count 0 2006.176.07:45:28.76#ibcon#read 5, iclass 36, count 0 2006.176.07:45:28.76#ibcon#about to read 6, iclass 36, count 0 2006.176.07:45:28.76#ibcon#read 6, iclass 36, count 0 2006.176.07:45:28.76#ibcon#end of sib2, iclass 36, count 0 2006.176.07:45:28.76#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:45:28.76#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:45:28.76#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:45:28.76#ibcon#*before write, iclass 36, count 0 2006.176.07:45:28.76#ibcon#enter sib2, iclass 36, count 0 2006.176.07:45:28.76#ibcon#flushed, iclass 36, count 0 2006.176.07:45:28.76#ibcon#about to write, iclass 36, count 0 2006.176.07:45:28.76#ibcon#wrote, iclass 36, count 0 2006.176.07:45:28.76#ibcon#about to read 3, iclass 36, count 0 2006.176.07:45:28.80#ibcon#read 3, iclass 36, count 0 2006.176.07:45:28.80#ibcon#about to read 4, iclass 36, count 0 2006.176.07:45:28.80#ibcon#read 4, iclass 36, count 0 2006.176.07:45:28.80#ibcon#about to read 5, iclass 36, count 0 2006.176.07:45:28.80#ibcon#read 5, iclass 36, count 0 2006.176.07:45:28.80#ibcon#about to read 6, iclass 36, count 0 2006.176.07:45:28.80#ibcon#read 6, iclass 36, count 0 2006.176.07:45:28.80#ibcon#end of sib2, iclass 36, count 0 2006.176.07:45:28.80#ibcon#*after write, iclass 36, count 0 2006.176.07:45:28.80#ibcon#*before return 0, iclass 36, count 0 2006.176.07:45:28.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:45:28.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:45:28.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:45:28.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:45:28.80$vc4f8/va=3,6 2006.176.07:45:28.80#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.07:45:28.80#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.07:45:28.80#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:28.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:45:28.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:45:28.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:45:28.86#ibcon#enter wrdev, iclass 38, count 2 2006.176.07:45:28.86#ibcon#first serial, iclass 38, count 2 2006.176.07:45:28.86#ibcon#enter sib2, iclass 38, count 2 2006.176.07:45:28.86#ibcon#flushed, iclass 38, count 2 2006.176.07:45:28.86#ibcon#about to write, iclass 38, count 2 2006.176.07:45:28.86#ibcon#wrote, iclass 38, count 2 2006.176.07:45:28.86#ibcon#about to read 3, iclass 38, count 2 2006.176.07:45:28.88#ibcon#read 3, iclass 38, count 2 2006.176.07:45:28.88#ibcon#about to read 4, iclass 38, count 2 2006.176.07:45:28.88#ibcon#read 4, iclass 38, count 2 2006.176.07:45:28.88#ibcon#about to read 5, iclass 38, count 2 2006.176.07:45:28.88#ibcon#read 5, iclass 38, count 2 2006.176.07:45:28.88#ibcon#about to read 6, iclass 38, count 2 2006.176.07:45:28.88#ibcon#read 6, iclass 38, count 2 2006.176.07:45:28.88#ibcon#end of sib2, iclass 38, count 2 2006.176.07:45:28.88#ibcon#*mode == 0, iclass 38, count 2 2006.176.07:45:28.88#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.07:45:28.88#ibcon#[25=AT03-06\r\n] 2006.176.07:45:28.88#ibcon#*before write, iclass 38, count 2 2006.176.07:45:28.88#ibcon#enter sib2, iclass 38, count 2 2006.176.07:45:28.88#ibcon#flushed, iclass 38, count 2 2006.176.07:45:28.88#ibcon#about to write, iclass 38, count 2 2006.176.07:45:28.88#ibcon#wrote, iclass 38, count 2 2006.176.07:45:28.88#ibcon#about to read 3, iclass 38, count 2 2006.176.07:45:28.91#ibcon#read 3, iclass 38, count 2 2006.176.07:45:28.91#ibcon#about to read 4, iclass 38, count 2 2006.176.07:45:28.91#ibcon#read 4, iclass 38, count 2 2006.176.07:45:28.91#ibcon#about to read 5, iclass 38, count 2 2006.176.07:45:28.91#ibcon#read 5, iclass 38, count 2 2006.176.07:45:28.91#ibcon#about to read 6, iclass 38, count 2 2006.176.07:45:28.91#ibcon#read 6, iclass 38, count 2 2006.176.07:45:28.91#ibcon#end of sib2, iclass 38, count 2 2006.176.07:45:28.91#ibcon#*after write, iclass 38, count 2 2006.176.07:45:28.91#ibcon#*before return 0, iclass 38, count 2 2006.176.07:45:28.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:45:28.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:45:28.91#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.07:45:28.91#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:28.91#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:45:29.03#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:45:29.03#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:45:29.03#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:45:29.03#ibcon#first serial, iclass 38, count 0 2006.176.07:45:29.03#ibcon#enter sib2, iclass 38, count 0 2006.176.07:45:29.03#ibcon#flushed, iclass 38, count 0 2006.176.07:45:29.03#ibcon#about to write, iclass 38, count 0 2006.176.07:45:29.03#ibcon#wrote, iclass 38, count 0 2006.176.07:45:29.03#ibcon#about to read 3, iclass 38, count 0 2006.176.07:45:29.05#ibcon#read 3, iclass 38, count 0 2006.176.07:45:29.05#ibcon#about to read 4, iclass 38, count 0 2006.176.07:45:29.05#ibcon#read 4, iclass 38, count 0 2006.176.07:45:29.05#ibcon#about to read 5, iclass 38, count 0 2006.176.07:45:29.05#ibcon#read 5, iclass 38, count 0 2006.176.07:45:29.05#ibcon#about to read 6, iclass 38, count 0 2006.176.07:45:29.05#ibcon#read 6, iclass 38, count 0 2006.176.07:45:29.05#ibcon#end of sib2, iclass 38, count 0 2006.176.07:45:29.05#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:45:29.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:45:29.05#ibcon#[25=USB\r\n] 2006.176.07:45:29.05#ibcon#*before write, iclass 38, count 0 2006.176.07:45:29.05#ibcon#enter sib2, iclass 38, count 0 2006.176.07:45:29.05#ibcon#flushed, iclass 38, count 0 2006.176.07:45:29.05#ibcon#about to write, iclass 38, count 0 2006.176.07:45:29.05#ibcon#wrote, iclass 38, count 0 2006.176.07:45:29.05#ibcon#about to read 3, iclass 38, count 0 2006.176.07:45:29.08#ibcon#read 3, iclass 38, count 0 2006.176.07:45:29.08#ibcon#about to read 4, iclass 38, count 0 2006.176.07:45:29.08#ibcon#read 4, iclass 38, count 0 2006.176.07:45:29.08#ibcon#about to read 5, iclass 38, count 0 2006.176.07:45:29.08#ibcon#read 5, iclass 38, count 0 2006.176.07:45:29.08#ibcon#about to read 6, iclass 38, count 0 2006.176.07:45:29.08#ibcon#read 6, iclass 38, count 0 2006.176.07:45:29.08#ibcon#end of sib2, iclass 38, count 0 2006.176.07:45:29.08#ibcon#*after write, iclass 38, count 0 2006.176.07:45:29.08#ibcon#*before return 0, iclass 38, count 0 2006.176.07:45:29.08#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:45:29.08#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:45:29.08#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:45:29.08#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:45:29.08$vc4f8/valo=4,832.99 2006.176.07:45:29.08#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.07:45:29.08#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.07:45:29.08#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:29.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:45:29.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:45:29.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:45:29.08#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:45:29.08#ibcon#first serial, iclass 40, count 0 2006.176.07:45:29.08#ibcon#enter sib2, iclass 40, count 0 2006.176.07:45:29.08#ibcon#flushed, iclass 40, count 0 2006.176.07:45:29.08#ibcon#about to write, iclass 40, count 0 2006.176.07:45:29.08#ibcon#wrote, iclass 40, count 0 2006.176.07:45:29.08#ibcon#about to read 3, iclass 40, count 0 2006.176.07:45:29.10#ibcon#read 3, iclass 40, count 0 2006.176.07:45:29.10#ibcon#about to read 4, iclass 40, count 0 2006.176.07:45:29.10#ibcon#read 4, iclass 40, count 0 2006.176.07:45:29.10#ibcon#about to read 5, iclass 40, count 0 2006.176.07:45:29.10#ibcon#read 5, iclass 40, count 0 2006.176.07:45:29.10#ibcon#about to read 6, iclass 40, count 0 2006.176.07:45:29.10#ibcon#read 6, iclass 40, count 0 2006.176.07:45:29.10#ibcon#end of sib2, iclass 40, count 0 2006.176.07:45:29.10#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:45:29.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:45:29.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:45:29.10#ibcon#*before write, iclass 40, count 0 2006.176.07:45:29.10#ibcon#enter sib2, iclass 40, count 0 2006.176.07:45:29.10#ibcon#flushed, iclass 40, count 0 2006.176.07:45:29.10#ibcon#about to write, iclass 40, count 0 2006.176.07:45:29.10#ibcon#wrote, iclass 40, count 0 2006.176.07:45:29.10#ibcon#about to read 3, iclass 40, count 0 2006.176.07:45:29.14#ibcon#read 3, iclass 40, count 0 2006.176.07:45:29.14#ibcon#about to read 4, iclass 40, count 0 2006.176.07:45:29.14#ibcon#read 4, iclass 40, count 0 2006.176.07:45:29.14#ibcon#about to read 5, iclass 40, count 0 2006.176.07:45:29.14#ibcon#read 5, iclass 40, count 0 2006.176.07:45:29.14#ibcon#about to read 6, iclass 40, count 0 2006.176.07:45:29.14#ibcon#read 6, iclass 40, count 0 2006.176.07:45:29.14#ibcon#end of sib2, iclass 40, count 0 2006.176.07:45:29.14#ibcon#*after write, iclass 40, count 0 2006.176.07:45:29.14#ibcon#*before return 0, iclass 40, count 0 2006.176.07:45:29.14#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:45:29.14#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:45:29.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:45:29.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:45:29.14$vc4f8/va=4,7 2006.176.07:45:29.14#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.07:45:29.14#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.07:45:29.14#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:29.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:29.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:29.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:29.20#ibcon#enter wrdev, iclass 4, count 2 2006.176.07:45:29.20#ibcon#first serial, iclass 4, count 2 2006.176.07:45:29.20#ibcon#enter sib2, iclass 4, count 2 2006.176.07:45:29.20#ibcon#flushed, iclass 4, count 2 2006.176.07:45:29.20#ibcon#about to write, iclass 4, count 2 2006.176.07:45:29.20#ibcon#wrote, iclass 4, count 2 2006.176.07:45:29.20#ibcon#about to read 3, iclass 4, count 2 2006.176.07:45:29.22#ibcon#read 3, iclass 4, count 2 2006.176.07:45:29.22#ibcon#about to read 4, iclass 4, count 2 2006.176.07:45:29.22#ibcon#read 4, iclass 4, count 2 2006.176.07:45:29.22#ibcon#about to read 5, iclass 4, count 2 2006.176.07:45:29.22#ibcon#read 5, iclass 4, count 2 2006.176.07:45:29.22#ibcon#about to read 6, iclass 4, count 2 2006.176.07:45:29.22#ibcon#read 6, iclass 4, count 2 2006.176.07:45:29.22#ibcon#end of sib2, iclass 4, count 2 2006.176.07:45:29.22#ibcon#*mode == 0, iclass 4, count 2 2006.176.07:45:29.22#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.07:45:29.22#ibcon#[25=AT04-07\r\n] 2006.176.07:45:29.22#ibcon#*before write, iclass 4, count 2 2006.176.07:45:29.22#ibcon#enter sib2, iclass 4, count 2 2006.176.07:45:29.22#ibcon#flushed, iclass 4, count 2 2006.176.07:45:29.22#ibcon#about to write, iclass 4, count 2 2006.176.07:45:29.22#ibcon#wrote, iclass 4, count 2 2006.176.07:45:29.22#ibcon#about to read 3, iclass 4, count 2 2006.176.07:45:29.25#ibcon#read 3, iclass 4, count 2 2006.176.07:45:29.25#ibcon#about to read 4, iclass 4, count 2 2006.176.07:45:29.25#ibcon#read 4, iclass 4, count 2 2006.176.07:45:29.25#ibcon#about to read 5, iclass 4, count 2 2006.176.07:45:29.25#ibcon#read 5, iclass 4, count 2 2006.176.07:45:29.25#ibcon#about to read 6, iclass 4, count 2 2006.176.07:45:29.25#ibcon#read 6, iclass 4, count 2 2006.176.07:45:29.25#ibcon#end of sib2, iclass 4, count 2 2006.176.07:45:29.25#ibcon#*after write, iclass 4, count 2 2006.176.07:45:29.25#ibcon#*before return 0, iclass 4, count 2 2006.176.07:45:29.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:29.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:29.25#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.07:45:29.25#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:29.25#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:29.37#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:29.37#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:29.37#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:45:29.37#ibcon#first serial, iclass 4, count 0 2006.176.07:45:29.37#ibcon#enter sib2, iclass 4, count 0 2006.176.07:45:29.37#ibcon#flushed, iclass 4, count 0 2006.176.07:45:29.37#ibcon#about to write, iclass 4, count 0 2006.176.07:45:29.37#ibcon#wrote, iclass 4, count 0 2006.176.07:45:29.37#ibcon#about to read 3, iclass 4, count 0 2006.176.07:45:29.39#ibcon#read 3, iclass 4, count 0 2006.176.07:45:29.39#ibcon#about to read 4, iclass 4, count 0 2006.176.07:45:29.39#ibcon#read 4, iclass 4, count 0 2006.176.07:45:29.39#ibcon#about to read 5, iclass 4, count 0 2006.176.07:45:29.39#ibcon#read 5, iclass 4, count 0 2006.176.07:45:29.39#ibcon#about to read 6, iclass 4, count 0 2006.176.07:45:29.39#ibcon#read 6, iclass 4, count 0 2006.176.07:45:29.39#ibcon#end of sib2, iclass 4, count 0 2006.176.07:45:29.39#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:45:29.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:45:29.39#ibcon#[25=USB\r\n] 2006.176.07:45:29.39#ibcon#*before write, iclass 4, count 0 2006.176.07:45:29.39#ibcon#enter sib2, iclass 4, count 0 2006.176.07:45:29.39#ibcon#flushed, iclass 4, count 0 2006.176.07:45:29.39#ibcon#about to write, iclass 4, count 0 2006.176.07:45:29.39#ibcon#wrote, iclass 4, count 0 2006.176.07:45:29.39#ibcon#about to read 3, iclass 4, count 0 2006.176.07:45:29.42#ibcon#read 3, iclass 4, count 0 2006.176.07:45:29.42#ibcon#about to read 4, iclass 4, count 0 2006.176.07:45:29.42#ibcon#read 4, iclass 4, count 0 2006.176.07:45:29.42#ibcon#about to read 5, iclass 4, count 0 2006.176.07:45:29.42#ibcon#read 5, iclass 4, count 0 2006.176.07:45:29.42#ibcon#about to read 6, iclass 4, count 0 2006.176.07:45:29.42#ibcon#read 6, iclass 4, count 0 2006.176.07:45:29.42#ibcon#end of sib2, iclass 4, count 0 2006.176.07:45:29.42#ibcon#*after write, iclass 4, count 0 2006.176.07:45:29.42#ibcon#*before return 0, iclass 4, count 0 2006.176.07:45:29.42#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:29.42#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:29.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:45:29.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:45:29.42$vc4f8/valo=5,652.99 2006.176.07:45:29.42#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.07:45:29.42#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.07:45:29.42#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:29.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:29.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:29.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:29.42#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:45:29.42#ibcon#first serial, iclass 6, count 0 2006.176.07:45:29.42#ibcon#enter sib2, iclass 6, count 0 2006.176.07:45:29.42#ibcon#flushed, iclass 6, count 0 2006.176.07:45:29.42#ibcon#about to write, iclass 6, count 0 2006.176.07:45:29.42#ibcon#wrote, iclass 6, count 0 2006.176.07:45:29.42#ibcon#about to read 3, iclass 6, count 0 2006.176.07:45:29.44#ibcon#read 3, iclass 6, count 0 2006.176.07:45:29.44#ibcon#about to read 4, iclass 6, count 0 2006.176.07:45:29.44#ibcon#read 4, iclass 6, count 0 2006.176.07:45:29.44#ibcon#about to read 5, iclass 6, count 0 2006.176.07:45:29.44#ibcon#read 5, iclass 6, count 0 2006.176.07:45:29.44#ibcon#about to read 6, iclass 6, count 0 2006.176.07:45:29.44#ibcon#read 6, iclass 6, count 0 2006.176.07:45:29.44#ibcon#end of sib2, iclass 6, count 0 2006.176.07:45:29.44#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:45:29.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:45:29.44#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:45:29.44#ibcon#*before write, iclass 6, count 0 2006.176.07:45:29.44#ibcon#enter sib2, iclass 6, count 0 2006.176.07:45:29.44#ibcon#flushed, iclass 6, count 0 2006.176.07:45:29.44#ibcon#about to write, iclass 6, count 0 2006.176.07:45:29.44#ibcon#wrote, iclass 6, count 0 2006.176.07:45:29.44#ibcon#about to read 3, iclass 6, count 0 2006.176.07:45:29.48#ibcon#read 3, iclass 6, count 0 2006.176.07:45:29.48#ibcon#about to read 4, iclass 6, count 0 2006.176.07:45:29.48#ibcon#read 4, iclass 6, count 0 2006.176.07:45:29.48#ibcon#about to read 5, iclass 6, count 0 2006.176.07:45:29.48#ibcon#read 5, iclass 6, count 0 2006.176.07:45:29.48#ibcon#about to read 6, iclass 6, count 0 2006.176.07:45:29.48#ibcon#read 6, iclass 6, count 0 2006.176.07:45:29.48#ibcon#end of sib2, iclass 6, count 0 2006.176.07:45:29.48#ibcon#*after write, iclass 6, count 0 2006.176.07:45:29.48#ibcon#*before return 0, iclass 6, count 0 2006.176.07:45:29.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:29.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:29.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:45:29.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:45:29.48$vc4f8/va=5,7 2006.176.07:45:29.48#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.07:45:29.48#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.07:45:29.48#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:29.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:29.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:29.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:29.54#ibcon#enter wrdev, iclass 10, count 2 2006.176.07:45:29.54#ibcon#first serial, iclass 10, count 2 2006.176.07:45:29.54#ibcon#enter sib2, iclass 10, count 2 2006.176.07:45:29.54#ibcon#flushed, iclass 10, count 2 2006.176.07:45:29.54#ibcon#about to write, iclass 10, count 2 2006.176.07:45:29.54#ibcon#wrote, iclass 10, count 2 2006.176.07:45:29.54#ibcon#about to read 3, iclass 10, count 2 2006.176.07:45:29.56#ibcon#read 3, iclass 10, count 2 2006.176.07:45:29.56#ibcon#about to read 4, iclass 10, count 2 2006.176.07:45:29.56#ibcon#read 4, iclass 10, count 2 2006.176.07:45:29.56#ibcon#about to read 5, iclass 10, count 2 2006.176.07:45:29.56#ibcon#read 5, iclass 10, count 2 2006.176.07:45:29.56#ibcon#about to read 6, iclass 10, count 2 2006.176.07:45:29.56#ibcon#read 6, iclass 10, count 2 2006.176.07:45:29.56#ibcon#end of sib2, iclass 10, count 2 2006.176.07:45:29.56#ibcon#*mode == 0, iclass 10, count 2 2006.176.07:45:29.56#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.07:45:29.56#ibcon#[25=AT05-07\r\n] 2006.176.07:45:29.56#ibcon#*before write, iclass 10, count 2 2006.176.07:45:29.56#ibcon#enter sib2, iclass 10, count 2 2006.176.07:45:29.56#ibcon#flushed, iclass 10, count 2 2006.176.07:45:29.56#ibcon#about to write, iclass 10, count 2 2006.176.07:45:29.56#ibcon#wrote, iclass 10, count 2 2006.176.07:45:29.56#ibcon#about to read 3, iclass 10, count 2 2006.176.07:45:29.59#ibcon#read 3, iclass 10, count 2 2006.176.07:45:29.59#ibcon#about to read 4, iclass 10, count 2 2006.176.07:45:29.59#ibcon#read 4, iclass 10, count 2 2006.176.07:45:29.59#ibcon#about to read 5, iclass 10, count 2 2006.176.07:45:29.59#ibcon#read 5, iclass 10, count 2 2006.176.07:45:29.59#ibcon#about to read 6, iclass 10, count 2 2006.176.07:45:29.59#ibcon#read 6, iclass 10, count 2 2006.176.07:45:29.59#ibcon#end of sib2, iclass 10, count 2 2006.176.07:45:29.59#ibcon#*after write, iclass 10, count 2 2006.176.07:45:29.59#ibcon#*before return 0, iclass 10, count 2 2006.176.07:45:29.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:29.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:29.59#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.07:45:29.59#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:29.59#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:29.71#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:29.71#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:29.71#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:45:29.71#ibcon#first serial, iclass 10, count 0 2006.176.07:45:29.71#ibcon#enter sib2, iclass 10, count 0 2006.176.07:45:29.71#ibcon#flushed, iclass 10, count 0 2006.176.07:45:29.71#ibcon#about to write, iclass 10, count 0 2006.176.07:45:29.71#ibcon#wrote, iclass 10, count 0 2006.176.07:45:29.71#ibcon#about to read 3, iclass 10, count 0 2006.176.07:45:29.73#ibcon#read 3, iclass 10, count 0 2006.176.07:45:29.73#ibcon#about to read 4, iclass 10, count 0 2006.176.07:45:29.73#ibcon#read 4, iclass 10, count 0 2006.176.07:45:29.73#ibcon#about to read 5, iclass 10, count 0 2006.176.07:45:29.73#ibcon#read 5, iclass 10, count 0 2006.176.07:45:29.73#ibcon#about to read 6, iclass 10, count 0 2006.176.07:45:29.73#ibcon#read 6, iclass 10, count 0 2006.176.07:45:29.73#ibcon#end of sib2, iclass 10, count 0 2006.176.07:45:29.73#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:45:29.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:45:29.73#ibcon#[25=USB\r\n] 2006.176.07:45:29.73#ibcon#*before write, iclass 10, count 0 2006.176.07:45:29.73#ibcon#enter sib2, iclass 10, count 0 2006.176.07:45:29.73#ibcon#flushed, iclass 10, count 0 2006.176.07:45:29.73#ibcon#about to write, iclass 10, count 0 2006.176.07:45:29.73#ibcon#wrote, iclass 10, count 0 2006.176.07:45:29.73#ibcon#about to read 3, iclass 10, count 0 2006.176.07:45:29.76#ibcon#read 3, iclass 10, count 0 2006.176.07:45:29.76#ibcon#about to read 4, iclass 10, count 0 2006.176.07:45:29.76#ibcon#read 4, iclass 10, count 0 2006.176.07:45:29.76#ibcon#about to read 5, iclass 10, count 0 2006.176.07:45:29.76#ibcon#read 5, iclass 10, count 0 2006.176.07:45:29.76#ibcon#about to read 6, iclass 10, count 0 2006.176.07:45:29.76#ibcon#read 6, iclass 10, count 0 2006.176.07:45:29.76#ibcon#end of sib2, iclass 10, count 0 2006.176.07:45:29.76#ibcon#*after write, iclass 10, count 0 2006.176.07:45:29.76#ibcon#*before return 0, iclass 10, count 0 2006.176.07:45:29.76#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:29.76#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:29.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:45:29.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:45:29.76$vc4f8/valo=6,772.99 2006.176.07:45:29.76#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.07:45:29.76#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.07:45:29.76#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:29.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:29.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:29.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:29.76#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:45:29.76#ibcon#first serial, iclass 12, count 0 2006.176.07:45:29.76#ibcon#enter sib2, iclass 12, count 0 2006.176.07:45:29.76#ibcon#flushed, iclass 12, count 0 2006.176.07:45:29.76#ibcon#about to write, iclass 12, count 0 2006.176.07:45:29.76#ibcon#wrote, iclass 12, count 0 2006.176.07:45:29.76#ibcon#about to read 3, iclass 12, count 0 2006.176.07:45:29.78#ibcon#read 3, iclass 12, count 0 2006.176.07:45:29.78#ibcon#about to read 4, iclass 12, count 0 2006.176.07:45:29.78#ibcon#read 4, iclass 12, count 0 2006.176.07:45:29.78#ibcon#about to read 5, iclass 12, count 0 2006.176.07:45:29.78#ibcon#read 5, iclass 12, count 0 2006.176.07:45:29.78#ibcon#about to read 6, iclass 12, count 0 2006.176.07:45:29.78#ibcon#read 6, iclass 12, count 0 2006.176.07:45:29.78#ibcon#end of sib2, iclass 12, count 0 2006.176.07:45:29.78#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:45:29.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:45:29.78#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:45:29.78#ibcon#*before write, iclass 12, count 0 2006.176.07:45:29.78#ibcon#enter sib2, iclass 12, count 0 2006.176.07:45:29.78#ibcon#flushed, iclass 12, count 0 2006.176.07:45:29.78#ibcon#about to write, iclass 12, count 0 2006.176.07:45:29.78#ibcon#wrote, iclass 12, count 0 2006.176.07:45:29.78#ibcon#about to read 3, iclass 12, count 0 2006.176.07:45:29.82#ibcon#read 3, iclass 12, count 0 2006.176.07:45:29.82#ibcon#about to read 4, iclass 12, count 0 2006.176.07:45:29.82#ibcon#read 4, iclass 12, count 0 2006.176.07:45:29.82#ibcon#about to read 5, iclass 12, count 0 2006.176.07:45:29.82#ibcon#read 5, iclass 12, count 0 2006.176.07:45:29.82#ibcon#about to read 6, iclass 12, count 0 2006.176.07:45:29.82#ibcon#read 6, iclass 12, count 0 2006.176.07:45:29.82#ibcon#end of sib2, iclass 12, count 0 2006.176.07:45:29.82#ibcon#*after write, iclass 12, count 0 2006.176.07:45:29.82#ibcon#*before return 0, iclass 12, count 0 2006.176.07:45:29.82#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:29.82#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:29.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:45:29.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:45:29.82$vc4f8/va=6,6 2006.176.07:45:29.82#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.07:45:29.82#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.07:45:29.82#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:29.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:29.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:29.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:29.88#ibcon#enter wrdev, iclass 14, count 2 2006.176.07:45:29.88#ibcon#first serial, iclass 14, count 2 2006.176.07:45:29.88#ibcon#enter sib2, iclass 14, count 2 2006.176.07:45:29.88#ibcon#flushed, iclass 14, count 2 2006.176.07:45:29.88#ibcon#about to write, iclass 14, count 2 2006.176.07:45:29.88#ibcon#wrote, iclass 14, count 2 2006.176.07:45:29.88#ibcon#about to read 3, iclass 14, count 2 2006.176.07:45:29.90#ibcon#read 3, iclass 14, count 2 2006.176.07:45:29.90#ibcon#about to read 4, iclass 14, count 2 2006.176.07:45:29.90#ibcon#read 4, iclass 14, count 2 2006.176.07:45:29.90#ibcon#about to read 5, iclass 14, count 2 2006.176.07:45:29.90#ibcon#read 5, iclass 14, count 2 2006.176.07:45:29.90#ibcon#about to read 6, iclass 14, count 2 2006.176.07:45:29.90#ibcon#read 6, iclass 14, count 2 2006.176.07:45:29.90#ibcon#end of sib2, iclass 14, count 2 2006.176.07:45:29.90#ibcon#*mode == 0, iclass 14, count 2 2006.176.07:45:29.90#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.07:45:29.90#ibcon#[25=AT06-06\r\n] 2006.176.07:45:29.90#ibcon#*before write, iclass 14, count 2 2006.176.07:45:29.90#ibcon#enter sib2, iclass 14, count 2 2006.176.07:45:29.90#ibcon#flushed, iclass 14, count 2 2006.176.07:45:29.90#ibcon#about to write, iclass 14, count 2 2006.176.07:45:29.90#ibcon#wrote, iclass 14, count 2 2006.176.07:45:29.90#ibcon#about to read 3, iclass 14, count 2 2006.176.07:45:29.93#ibcon#read 3, iclass 14, count 2 2006.176.07:45:29.93#ibcon#about to read 4, iclass 14, count 2 2006.176.07:45:29.93#ibcon#read 4, iclass 14, count 2 2006.176.07:45:29.93#ibcon#about to read 5, iclass 14, count 2 2006.176.07:45:29.93#ibcon#read 5, iclass 14, count 2 2006.176.07:45:29.93#ibcon#about to read 6, iclass 14, count 2 2006.176.07:45:29.93#ibcon#read 6, iclass 14, count 2 2006.176.07:45:29.93#ibcon#end of sib2, iclass 14, count 2 2006.176.07:45:29.93#ibcon#*after write, iclass 14, count 2 2006.176.07:45:29.93#ibcon#*before return 0, iclass 14, count 2 2006.176.07:45:29.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:29.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:29.93#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.07:45:29.93#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:29.93#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:30.05#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:30.05#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:30.05#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:45:30.05#ibcon#first serial, iclass 14, count 0 2006.176.07:45:30.05#ibcon#enter sib2, iclass 14, count 0 2006.176.07:45:30.05#ibcon#flushed, iclass 14, count 0 2006.176.07:45:30.05#ibcon#about to write, iclass 14, count 0 2006.176.07:45:30.05#ibcon#wrote, iclass 14, count 0 2006.176.07:45:30.05#ibcon#about to read 3, iclass 14, count 0 2006.176.07:45:30.07#ibcon#read 3, iclass 14, count 0 2006.176.07:45:30.07#ibcon#about to read 4, iclass 14, count 0 2006.176.07:45:30.07#ibcon#read 4, iclass 14, count 0 2006.176.07:45:30.07#ibcon#about to read 5, iclass 14, count 0 2006.176.07:45:30.07#ibcon#read 5, iclass 14, count 0 2006.176.07:45:30.07#ibcon#about to read 6, iclass 14, count 0 2006.176.07:45:30.07#ibcon#read 6, iclass 14, count 0 2006.176.07:45:30.07#ibcon#end of sib2, iclass 14, count 0 2006.176.07:45:30.07#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:45:30.07#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:45:30.07#ibcon#[25=USB\r\n] 2006.176.07:45:30.07#ibcon#*before write, iclass 14, count 0 2006.176.07:45:30.07#ibcon#enter sib2, iclass 14, count 0 2006.176.07:45:30.07#ibcon#flushed, iclass 14, count 0 2006.176.07:45:30.07#ibcon#about to write, iclass 14, count 0 2006.176.07:45:30.07#ibcon#wrote, iclass 14, count 0 2006.176.07:45:30.07#ibcon#about to read 3, iclass 14, count 0 2006.176.07:45:30.10#ibcon#read 3, iclass 14, count 0 2006.176.07:45:30.10#ibcon#about to read 4, iclass 14, count 0 2006.176.07:45:30.10#ibcon#read 4, iclass 14, count 0 2006.176.07:45:30.10#ibcon#about to read 5, iclass 14, count 0 2006.176.07:45:30.10#ibcon#read 5, iclass 14, count 0 2006.176.07:45:30.10#ibcon#about to read 6, iclass 14, count 0 2006.176.07:45:30.10#ibcon#read 6, iclass 14, count 0 2006.176.07:45:30.10#ibcon#end of sib2, iclass 14, count 0 2006.176.07:45:30.10#ibcon#*after write, iclass 14, count 0 2006.176.07:45:30.10#ibcon#*before return 0, iclass 14, count 0 2006.176.07:45:30.10#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:30.10#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:30.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:45:30.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:45:30.10$vc4f8/valo=7,832.99 2006.176.07:45:30.10#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:45:30.10#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:45:30.10#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:30.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:30.10#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:30.10#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:30.10#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:45:30.10#ibcon#first serial, iclass 16, count 0 2006.176.07:45:30.10#ibcon#enter sib2, iclass 16, count 0 2006.176.07:45:30.10#ibcon#flushed, iclass 16, count 0 2006.176.07:45:30.10#ibcon#about to write, iclass 16, count 0 2006.176.07:45:30.10#ibcon#wrote, iclass 16, count 0 2006.176.07:45:30.10#ibcon#about to read 3, iclass 16, count 0 2006.176.07:45:30.12#ibcon#read 3, iclass 16, count 0 2006.176.07:45:30.12#ibcon#about to read 4, iclass 16, count 0 2006.176.07:45:30.12#ibcon#read 4, iclass 16, count 0 2006.176.07:45:30.12#ibcon#about to read 5, iclass 16, count 0 2006.176.07:45:30.12#ibcon#read 5, iclass 16, count 0 2006.176.07:45:30.12#ibcon#about to read 6, iclass 16, count 0 2006.176.07:45:30.12#ibcon#read 6, iclass 16, count 0 2006.176.07:45:30.12#ibcon#end of sib2, iclass 16, count 0 2006.176.07:45:30.12#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:45:30.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:45:30.12#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:45:30.12#ibcon#*before write, iclass 16, count 0 2006.176.07:45:30.12#ibcon#enter sib2, iclass 16, count 0 2006.176.07:45:30.12#ibcon#flushed, iclass 16, count 0 2006.176.07:45:30.12#ibcon#about to write, iclass 16, count 0 2006.176.07:45:30.12#ibcon#wrote, iclass 16, count 0 2006.176.07:45:30.12#ibcon#about to read 3, iclass 16, count 0 2006.176.07:45:30.16#ibcon#read 3, iclass 16, count 0 2006.176.07:45:30.16#ibcon#about to read 4, iclass 16, count 0 2006.176.07:45:30.16#ibcon#read 4, iclass 16, count 0 2006.176.07:45:30.16#ibcon#about to read 5, iclass 16, count 0 2006.176.07:45:30.16#ibcon#read 5, iclass 16, count 0 2006.176.07:45:30.16#ibcon#about to read 6, iclass 16, count 0 2006.176.07:45:30.16#ibcon#read 6, iclass 16, count 0 2006.176.07:45:30.16#ibcon#end of sib2, iclass 16, count 0 2006.176.07:45:30.16#ibcon#*after write, iclass 16, count 0 2006.176.07:45:30.16#ibcon#*before return 0, iclass 16, count 0 2006.176.07:45:30.16#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:30.16#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:30.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:45:30.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:45:30.16$vc4f8/va=7,6 2006.176.07:45:30.16#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.07:45:30.16#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.07:45:30.16#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:30.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:45:30.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:45:30.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:45:30.22#ibcon#enter wrdev, iclass 18, count 2 2006.176.07:45:30.22#ibcon#first serial, iclass 18, count 2 2006.176.07:45:30.22#ibcon#enter sib2, iclass 18, count 2 2006.176.07:45:30.22#ibcon#flushed, iclass 18, count 2 2006.176.07:45:30.22#ibcon#about to write, iclass 18, count 2 2006.176.07:45:30.22#ibcon#wrote, iclass 18, count 2 2006.176.07:45:30.22#ibcon#about to read 3, iclass 18, count 2 2006.176.07:45:30.24#ibcon#read 3, iclass 18, count 2 2006.176.07:45:30.24#ibcon#about to read 4, iclass 18, count 2 2006.176.07:45:30.24#ibcon#read 4, iclass 18, count 2 2006.176.07:45:30.24#ibcon#about to read 5, iclass 18, count 2 2006.176.07:45:30.24#ibcon#read 5, iclass 18, count 2 2006.176.07:45:30.24#ibcon#about to read 6, iclass 18, count 2 2006.176.07:45:30.24#ibcon#read 6, iclass 18, count 2 2006.176.07:45:30.24#ibcon#end of sib2, iclass 18, count 2 2006.176.07:45:30.24#ibcon#*mode == 0, iclass 18, count 2 2006.176.07:45:30.24#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.07:45:30.24#ibcon#[25=AT07-06\r\n] 2006.176.07:45:30.24#ibcon#*before write, iclass 18, count 2 2006.176.07:45:30.24#ibcon#enter sib2, iclass 18, count 2 2006.176.07:45:30.24#ibcon#flushed, iclass 18, count 2 2006.176.07:45:30.24#ibcon#about to write, iclass 18, count 2 2006.176.07:45:30.24#ibcon#wrote, iclass 18, count 2 2006.176.07:45:30.24#ibcon#about to read 3, iclass 18, count 2 2006.176.07:45:30.27#ibcon#read 3, iclass 18, count 2 2006.176.07:45:30.27#ibcon#about to read 4, iclass 18, count 2 2006.176.07:45:30.27#ibcon#read 4, iclass 18, count 2 2006.176.07:45:30.27#ibcon#about to read 5, iclass 18, count 2 2006.176.07:45:30.27#ibcon#read 5, iclass 18, count 2 2006.176.07:45:30.27#ibcon#about to read 6, iclass 18, count 2 2006.176.07:45:30.27#ibcon#read 6, iclass 18, count 2 2006.176.07:45:30.27#ibcon#end of sib2, iclass 18, count 2 2006.176.07:45:30.27#ibcon#*after write, iclass 18, count 2 2006.176.07:45:30.27#ibcon#*before return 0, iclass 18, count 2 2006.176.07:45:30.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:45:30.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:45:30.27#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.07:45:30.27#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:30.27#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:45:30.39#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:45:30.39#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:45:30.39#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:45:30.39#ibcon#first serial, iclass 18, count 0 2006.176.07:45:30.39#ibcon#enter sib2, iclass 18, count 0 2006.176.07:45:30.39#ibcon#flushed, iclass 18, count 0 2006.176.07:45:30.39#ibcon#about to write, iclass 18, count 0 2006.176.07:45:30.39#ibcon#wrote, iclass 18, count 0 2006.176.07:45:30.39#ibcon#about to read 3, iclass 18, count 0 2006.176.07:45:30.41#ibcon#read 3, iclass 18, count 0 2006.176.07:45:30.41#ibcon#about to read 4, iclass 18, count 0 2006.176.07:45:30.41#ibcon#read 4, iclass 18, count 0 2006.176.07:45:30.41#ibcon#about to read 5, iclass 18, count 0 2006.176.07:45:30.41#ibcon#read 5, iclass 18, count 0 2006.176.07:45:30.41#ibcon#about to read 6, iclass 18, count 0 2006.176.07:45:30.41#ibcon#read 6, iclass 18, count 0 2006.176.07:45:30.41#ibcon#end of sib2, iclass 18, count 0 2006.176.07:45:30.41#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:45:30.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:45:30.41#ibcon#[25=USB\r\n] 2006.176.07:45:30.41#ibcon#*before write, iclass 18, count 0 2006.176.07:45:30.41#ibcon#enter sib2, iclass 18, count 0 2006.176.07:45:30.41#ibcon#flushed, iclass 18, count 0 2006.176.07:45:30.41#ibcon#about to write, iclass 18, count 0 2006.176.07:45:30.41#ibcon#wrote, iclass 18, count 0 2006.176.07:45:30.41#ibcon#about to read 3, iclass 18, count 0 2006.176.07:45:30.44#ibcon#read 3, iclass 18, count 0 2006.176.07:45:30.44#ibcon#about to read 4, iclass 18, count 0 2006.176.07:45:30.44#ibcon#read 4, iclass 18, count 0 2006.176.07:45:30.44#ibcon#about to read 5, iclass 18, count 0 2006.176.07:45:30.44#ibcon#read 5, iclass 18, count 0 2006.176.07:45:30.44#ibcon#about to read 6, iclass 18, count 0 2006.176.07:45:30.44#ibcon#read 6, iclass 18, count 0 2006.176.07:45:30.44#ibcon#end of sib2, iclass 18, count 0 2006.176.07:45:30.44#ibcon#*after write, iclass 18, count 0 2006.176.07:45:30.44#ibcon#*before return 0, iclass 18, count 0 2006.176.07:45:30.44#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:45:30.44#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:45:30.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:45:30.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:45:30.44$vc4f8/valo=8,852.99 2006.176.07:45:30.44#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.07:45:30.44#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.07:45:30.44#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:30.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:45:30.44#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:45:30.44#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:45:30.44#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:45:30.44#ibcon#first serial, iclass 20, count 0 2006.176.07:45:30.44#ibcon#enter sib2, iclass 20, count 0 2006.176.07:45:30.44#ibcon#flushed, iclass 20, count 0 2006.176.07:45:30.44#ibcon#about to write, iclass 20, count 0 2006.176.07:45:30.44#ibcon#wrote, iclass 20, count 0 2006.176.07:45:30.44#ibcon#about to read 3, iclass 20, count 0 2006.176.07:45:30.46#ibcon#read 3, iclass 20, count 0 2006.176.07:45:30.46#ibcon#about to read 4, iclass 20, count 0 2006.176.07:45:30.46#ibcon#read 4, iclass 20, count 0 2006.176.07:45:30.46#ibcon#about to read 5, iclass 20, count 0 2006.176.07:45:30.46#ibcon#read 5, iclass 20, count 0 2006.176.07:45:30.46#ibcon#about to read 6, iclass 20, count 0 2006.176.07:45:30.46#ibcon#read 6, iclass 20, count 0 2006.176.07:45:30.46#ibcon#end of sib2, iclass 20, count 0 2006.176.07:45:30.46#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:45:30.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:45:30.46#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:45:30.46#ibcon#*before write, iclass 20, count 0 2006.176.07:45:30.46#ibcon#enter sib2, iclass 20, count 0 2006.176.07:45:30.46#ibcon#flushed, iclass 20, count 0 2006.176.07:45:30.46#ibcon#about to write, iclass 20, count 0 2006.176.07:45:30.46#ibcon#wrote, iclass 20, count 0 2006.176.07:45:30.46#ibcon#about to read 3, iclass 20, count 0 2006.176.07:45:30.50#ibcon#read 3, iclass 20, count 0 2006.176.07:45:30.50#ibcon#about to read 4, iclass 20, count 0 2006.176.07:45:30.50#ibcon#read 4, iclass 20, count 0 2006.176.07:45:30.50#ibcon#about to read 5, iclass 20, count 0 2006.176.07:45:30.50#ibcon#read 5, iclass 20, count 0 2006.176.07:45:30.50#ibcon#about to read 6, iclass 20, count 0 2006.176.07:45:30.50#ibcon#read 6, iclass 20, count 0 2006.176.07:45:30.50#ibcon#end of sib2, iclass 20, count 0 2006.176.07:45:30.50#ibcon#*after write, iclass 20, count 0 2006.176.07:45:30.50#ibcon#*before return 0, iclass 20, count 0 2006.176.07:45:30.50#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:45:30.50#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:45:30.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:45:30.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:45:30.50$vc4f8/va=8,6 2006.176.07:45:30.50#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.07:45:30.50#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.07:45:30.50#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:30.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:45:30.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:45:30.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:45:30.56#ibcon#enter wrdev, iclass 22, count 2 2006.176.07:45:30.56#ibcon#first serial, iclass 22, count 2 2006.176.07:45:30.56#ibcon#enter sib2, iclass 22, count 2 2006.176.07:45:30.56#ibcon#flushed, iclass 22, count 2 2006.176.07:45:30.56#ibcon#about to write, iclass 22, count 2 2006.176.07:45:30.56#ibcon#wrote, iclass 22, count 2 2006.176.07:45:30.56#ibcon#about to read 3, iclass 22, count 2 2006.176.07:45:30.58#ibcon#read 3, iclass 22, count 2 2006.176.07:45:30.58#ibcon#about to read 4, iclass 22, count 2 2006.176.07:45:30.58#ibcon#read 4, iclass 22, count 2 2006.176.07:45:30.58#ibcon#about to read 5, iclass 22, count 2 2006.176.07:45:30.58#ibcon#read 5, iclass 22, count 2 2006.176.07:45:30.58#ibcon#about to read 6, iclass 22, count 2 2006.176.07:45:30.58#ibcon#read 6, iclass 22, count 2 2006.176.07:45:30.58#ibcon#end of sib2, iclass 22, count 2 2006.176.07:45:30.58#ibcon#*mode == 0, iclass 22, count 2 2006.176.07:45:30.58#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.07:45:30.58#ibcon#[25=AT08-06\r\n] 2006.176.07:45:30.58#ibcon#*before write, iclass 22, count 2 2006.176.07:45:30.58#ibcon#enter sib2, iclass 22, count 2 2006.176.07:45:30.58#ibcon#flushed, iclass 22, count 2 2006.176.07:45:30.58#ibcon#about to write, iclass 22, count 2 2006.176.07:45:30.58#ibcon#wrote, iclass 22, count 2 2006.176.07:45:30.58#ibcon#about to read 3, iclass 22, count 2 2006.176.07:45:30.61#ibcon#read 3, iclass 22, count 2 2006.176.07:45:30.61#ibcon#about to read 4, iclass 22, count 2 2006.176.07:45:30.61#ibcon#read 4, iclass 22, count 2 2006.176.07:45:30.61#ibcon#about to read 5, iclass 22, count 2 2006.176.07:45:30.61#ibcon#read 5, iclass 22, count 2 2006.176.07:45:30.61#ibcon#about to read 6, iclass 22, count 2 2006.176.07:45:30.61#ibcon#read 6, iclass 22, count 2 2006.176.07:45:30.61#ibcon#end of sib2, iclass 22, count 2 2006.176.07:45:30.61#ibcon#*after write, iclass 22, count 2 2006.176.07:45:30.61#ibcon#*before return 0, iclass 22, count 2 2006.176.07:45:30.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:45:30.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:45:30.61#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.07:45:30.61#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:30.61#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:45:30.73#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:45:30.73#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:45:30.73#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:45:30.73#ibcon#first serial, iclass 22, count 0 2006.176.07:45:30.73#ibcon#enter sib2, iclass 22, count 0 2006.176.07:45:30.73#ibcon#flushed, iclass 22, count 0 2006.176.07:45:30.73#ibcon#about to write, iclass 22, count 0 2006.176.07:45:30.73#ibcon#wrote, iclass 22, count 0 2006.176.07:45:30.73#ibcon#about to read 3, iclass 22, count 0 2006.176.07:45:30.75#ibcon#read 3, iclass 22, count 0 2006.176.07:45:30.75#ibcon#about to read 4, iclass 22, count 0 2006.176.07:45:30.75#ibcon#read 4, iclass 22, count 0 2006.176.07:45:30.75#ibcon#about to read 5, iclass 22, count 0 2006.176.07:45:30.75#ibcon#read 5, iclass 22, count 0 2006.176.07:45:30.75#ibcon#about to read 6, iclass 22, count 0 2006.176.07:45:30.75#ibcon#read 6, iclass 22, count 0 2006.176.07:45:30.75#ibcon#end of sib2, iclass 22, count 0 2006.176.07:45:30.75#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:45:30.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:45:30.75#ibcon#[25=USB\r\n] 2006.176.07:45:30.75#ibcon#*before write, iclass 22, count 0 2006.176.07:45:30.75#ibcon#enter sib2, iclass 22, count 0 2006.176.07:45:30.75#ibcon#flushed, iclass 22, count 0 2006.176.07:45:30.75#ibcon#about to write, iclass 22, count 0 2006.176.07:45:30.75#ibcon#wrote, iclass 22, count 0 2006.176.07:45:30.75#ibcon#about to read 3, iclass 22, count 0 2006.176.07:45:30.78#ibcon#read 3, iclass 22, count 0 2006.176.07:45:30.78#ibcon#about to read 4, iclass 22, count 0 2006.176.07:45:30.78#ibcon#read 4, iclass 22, count 0 2006.176.07:45:30.78#ibcon#about to read 5, iclass 22, count 0 2006.176.07:45:30.78#ibcon#read 5, iclass 22, count 0 2006.176.07:45:30.78#ibcon#about to read 6, iclass 22, count 0 2006.176.07:45:30.78#ibcon#read 6, iclass 22, count 0 2006.176.07:45:30.78#ibcon#end of sib2, iclass 22, count 0 2006.176.07:45:30.78#ibcon#*after write, iclass 22, count 0 2006.176.07:45:30.78#ibcon#*before return 0, iclass 22, count 0 2006.176.07:45:30.78#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:45:30.78#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:45:30.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:45:30.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:45:30.78$vc4f8/vblo=1,632.99 2006.176.07:45:30.78#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.07:45:30.78#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.07:45:30.78#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:30.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:45:30.78#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:45:30.78#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:45:30.78#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:45:30.78#ibcon#first serial, iclass 24, count 0 2006.176.07:45:30.78#ibcon#enter sib2, iclass 24, count 0 2006.176.07:45:30.78#ibcon#flushed, iclass 24, count 0 2006.176.07:45:30.78#ibcon#about to write, iclass 24, count 0 2006.176.07:45:30.78#ibcon#wrote, iclass 24, count 0 2006.176.07:45:30.78#ibcon#about to read 3, iclass 24, count 0 2006.176.07:45:30.80#ibcon#read 3, iclass 24, count 0 2006.176.07:45:30.80#ibcon#about to read 4, iclass 24, count 0 2006.176.07:45:30.80#ibcon#read 4, iclass 24, count 0 2006.176.07:45:30.80#ibcon#about to read 5, iclass 24, count 0 2006.176.07:45:30.80#ibcon#read 5, iclass 24, count 0 2006.176.07:45:30.80#ibcon#about to read 6, iclass 24, count 0 2006.176.07:45:30.80#ibcon#read 6, iclass 24, count 0 2006.176.07:45:30.80#ibcon#end of sib2, iclass 24, count 0 2006.176.07:45:30.80#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:45:30.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:45:30.80#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:45:30.80#ibcon#*before write, iclass 24, count 0 2006.176.07:45:30.80#ibcon#enter sib2, iclass 24, count 0 2006.176.07:45:30.80#ibcon#flushed, iclass 24, count 0 2006.176.07:45:30.80#ibcon#about to write, iclass 24, count 0 2006.176.07:45:30.80#ibcon#wrote, iclass 24, count 0 2006.176.07:45:30.80#ibcon#about to read 3, iclass 24, count 0 2006.176.07:45:30.84#ibcon#read 3, iclass 24, count 0 2006.176.07:45:30.84#ibcon#about to read 4, iclass 24, count 0 2006.176.07:45:30.84#ibcon#read 4, iclass 24, count 0 2006.176.07:45:30.84#ibcon#about to read 5, iclass 24, count 0 2006.176.07:45:30.84#ibcon#read 5, iclass 24, count 0 2006.176.07:45:30.84#ibcon#about to read 6, iclass 24, count 0 2006.176.07:45:30.84#ibcon#read 6, iclass 24, count 0 2006.176.07:45:30.84#ibcon#end of sib2, iclass 24, count 0 2006.176.07:45:30.84#ibcon#*after write, iclass 24, count 0 2006.176.07:45:30.84#ibcon#*before return 0, iclass 24, count 0 2006.176.07:45:30.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:45:30.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:45:30.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:45:30.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:45:30.84$vc4f8/vb=1,4 2006.176.07:45:30.84#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.07:45:30.84#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.07:45:30.84#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:30.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:45:30.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:45:30.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:45:30.84#ibcon#enter wrdev, iclass 26, count 2 2006.176.07:45:30.84#ibcon#first serial, iclass 26, count 2 2006.176.07:45:30.84#ibcon#enter sib2, iclass 26, count 2 2006.176.07:45:30.84#ibcon#flushed, iclass 26, count 2 2006.176.07:45:30.84#ibcon#about to write, iclass 26, count 2 2006.176.07:45:30.84#ibcon#wrote, iclass 26, count 2 2006.176.07:45:30.84#ibcon#about to read 3, iclass 26, count 2 2006.176.07:45:30.86#ibcon#read 3, iclass 26, count 2 2006.176.07:45:30.86#ibcon#about to read 4, iclass 26, count 2 2006.176.07:45:30.86#ibcon#read 4, iclass 26, count 2 2006.176.07:45:30.86#ibcon#about to read 5, iclass 26, count 2 2006.176.07:45:30.86#ibcon#read 5, iclass 26, count 2 2006.176.07:45:30.86#ibcon#about to read 6, iclass 26, count 2 2006.176.07:45:30.86#ibcon#read 6, iclass 26, count 2 2006.176.07:45:30.86#ibcon#end of sib2, iclass 26, count 2 2006.176.07:45:30.86#ibcon#*mode == 0, iclass 26, count 2 2006.176.07:45:30.86#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.07:45:30.86#ibcon#[27=AT01-04\r\n] 2006.176.07:45:30.86#ibcon#*before write, iclass 26, count 2 2006.176.07:45:30.86#ibcon#enter sib2, iclass 26, count 2 2006.176.07:45:30.86#ibcon#flushed, iclass 26, count 2 2006.176.07:45:30.86#ibcon#about to write, iclass 26, count 2 2006.176.07:45:30.86#ibcon#wrote, iclass 26, count 2 2006.176.07:45:30.86#ibcon#about to read 3, iclass 26, count 2 2006.176.07:45:30.89#ibcon#read 3, iclass 26, count 2 2006.176.07:45:30.89#ibcon#about to read 4, iclass 26, count 2 2006.176.07:45:30.89#ibcon#read 4, iclass 26, count 2 2006.176.07:45:30.89#ibcon#about to read 5, iclass 26, count 2 2006.176.07:45:30.89#ibcon#read 5, iclass 26, count 2 2006.176.07:45:30.89#ibcon#about to read 6, iclass 26, count 2 2006.176.07:45:30.89#ibcon#read 6, iclass 26, count 2 2006.176.07:45:30.89#ibcon#end of sib2, iclass 26, count 2 2006.176.07:45:30.89#ibcon#*after write, iclass 26, count 2 2006.176.07:45:30.89#ibcon#*before return 0, iclass 26, count 2 2006.176.07:45:30.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:45:30.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:45:30.89#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.07:45:30.89#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:30.89#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:45:31.01#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:45:31.01#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:45:31.01#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:45:31.01#ibcon#first serial, iclass 26, count 0 2006.176.07:45:31.01#ibcon#enter sib2, iclass 26, count 0 2006.176.07:45:31.01#ibcon#flushed, iclass 26, count 0 2006.176.07:45:31.01#ibcon#about to write, iclass 26, count 0 2006.176.07:45:31.01#ibcon#wrote, iclass 26, count 0 2006.176.07:45:31.01#ibcon#about to read 3, iclass 26, count 0 2006.176.07:45:31.03#ibcon#read 3, iclass 26, count 0 2006.176.07:45:31.03#ibcon#about to read 4, iclass 26, count 0 2006.176.07:45:31.03#ibcon#read 4, iclass 26, count 0 2006.176.07:45:31.03#ibcon#about to read 5, iclass 26, count 0 2006.176.07:45:31.03#ibcon#read 5, iclass 26, count 0 2006.176.07:45:31.03#ibcon#about to read 6, iclass 26, count 0 2006.176.07:45:31.03#ibcon#read 6, iclass 26, count 0 2006.176.07:45:31.03#ibcon#end of sib2, iclass 26, count 0 2006.176.07:45:31.03#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:45:31.03#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:45:31.03#ibcon#[27=USB\r\n] 2006.176.07:45:31.03#ibcon#*before write, iclass 26, count 0 2006.176.07:45:31.03#ibcon#enter sib2, iclass 26, count 0 2006.176.07:45:31.03#ibcon#flushed, iclass 26, count 0 2006.176.07:45:31.03#ibcon#about to write, iclass 26, count 0 2006.176.07:45:31.03#ibcon#wrote, iclass 26, count 0 2006.176.07:45:31.03#ibcon#about to read 3, iclass 26, count 0 2006.176.07:45:31.06#ibcon#read 3, iclass 26, count 0 2006.176.07:45:31.06#ibcon#about to read 4, iclass 26, count 0 2006.176.07:45:31.06#ibcon#read 4, iclass 26, count 0 2006.176.07:45:31.06#ibcon#about to read 5, iclass 26, count 0 2006.176.07:45:31.06#ibcon#read 5, iclass 26, count 0 2006.176.07:45:31.06#ibcon#about to read 6, iclass 26, count 0 2006.176.07:45:31.06#ibcon#read 6, iclass 26, count 0 2006.176.07:45:31.06#ibcon#end of sib2, iclass 26, count 0 2006.176.07:45:31.06#ibcon#*after write, iclass 26, count 0 2006.176.07:45:31.06#ibcon#*before return 0, iclass 26, count 0 2006.176.07:45:31.06#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:45:31.06#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:45:31.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:45:31.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:45:31.06$vc4f8/vblo=2,640.99 2006.176.07:45:31.06#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.07:45:31.06#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.07:45:31.06#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:31.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:31.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:31.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:31.06#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:45:31.06#ibcon#first serial, iclass 28, count 0 2006.176.07:45:31.06#ibcon#enter sib2, iclass 28, count 0 2006.176.07:45:31.06#ibcon#flushed, iclass 28, count 0 2006.176.07:45:31.06#ibcon#about to write, iclass 28, count 0 2006.176.07:45:31.06#ibcon#wrote, iclass 28, count 0 2006.176.07:45:31.06#ibcon#about to read 3, iclass 28, count 0 2006.176.07:45:31.08#ibcon#read 3, iclass 28, count 0 2006.176.07:45:31.08#ibcon#about to read 4, iclass 28, count 0 2006.176.07:45:31.08#ibcon#read 4, iclass 28, count 0 2006.176.07:45:31.08#ibcon#about to read 5, iclass 28, count 0 2006.176.07:45:31.08#ibcon#read 5, iclass 28, count 0 2006.176.07:45:31.08#ibcon#about to read 6, iclass 28, count 0 2006.176.07:45:31.08#ibcon#read 6, iclass 28, count 0 2006.176.07:45:31.08#ibcon#end of sib2, iclass 28, count 0 2006.176.07:45:31.08#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:45:31.08#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:45:31.08#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:45:31.08#ibcon#*before write, iclass 28, count 0 2006.176.07:45:31.08#ibcon#enter sib2, iclass 28, count 0 2006.176.07:45:31.08#ibcon#flushed, iclass 28, count 0 2006.176.07:45:31.08#ibcon#about to write, iclass 28, count 0 2006.176.07:45:31.08#ibcon#wrote, iclass 28, count 0 2006.176.07:45:31.08#ibcon#about to read 3, iclass 28, count 0 2006.176.07:45:31.12#ibcon#read 3, iclass 28, count 0 2006.176.07:45:31.12#ibcon#about to read 4, iclass 28, count 0 2006.176.07:45:31.12#ibcon#read 4, iclass 28, count 0 2006.176.07:45:31.12#ibcon#about to read 5, iclass 28, count 0 2006.176.07:45:31.12#ibcon#read 5, iclass 28, count 0 2006.176.07:45:31.12#ibcon#about to read 6, iclass 28, count 0 2006.176.07:45:31.12#ibcon#read 6, iclass 28, count 0 2006.176.07:45:31.12#ibcon#end of sib2, iclass 28, count 0 2006.176.07:45:31.12#ibcon#*after write, iclass 28, count 0 2006.176.07:45:31.12#ibcon#*before return 0, iclass 28, count 0 2006.176.07:45:31.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:31.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:45:31.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:45:31.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:45:31.12$vc4f8/vb=2,4 2006.176.07:45:31.12#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.07:45:31.12#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.07:45:31.12#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:31.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:31.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:31.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:31.18#ibcon#enter wrdev, iclass 30, count 2 2006.176.07:45:31.18#ibcon#first serial, iclass 30, count 2 2006.176.07:45:31.18#ibcon#enter sib2, iclass 30, count 2 2006.176.07:45:31.18#ibcon#flushed, iclass 30, count 2 2006.176.07:45:31.18#ibcon#about to write, iclass 30, count 2 2006.176.07:45:31.18#ibcon#wrote, iclass 30, count 2 2006.176.07:45:31.18#ibcon#about to read 3, iclass 30, count 2 2006.176.07:45:31.20#ibcon#read 3, iclass 30, count 2 2006.176.07:45:31.20#ibcon#about to read 4, iclass 30, count 2 2006.176.07:45:31.20#ibcon#read 4, iclass 30, count 2 2006.176.07:45:31.20#ibcon#about to read 5, iclass 30, count 2 2006.176.07:45:31.20#ibcon#read 5, iclass 30, count 2 2006.176.07:45:31.20#ibcon#about to read 6, iclass 30, count 2 2006.176.07:45:31.20#ibcon#read 6, iclass 30, count 2 2006.176.07:45:31.20#ibcon#end of sib2, iclass 30, count 2 2006.176.07:45:31.20#ibcon#*mode == 0, iclass 30, count 2 2006.176.07:45:31.20#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.07:45:31.20#ibcon#[27=AT02-04\r\n] 2006.176.07:45:31.20#ibcon#*before write, iclass 30, count 2 2006.176.07:45:31.20#ibcon#enter sib2, iclass 30, count 2 2006.176.07:45:31.20#ibcon#flushed, iclass 30, count 2 2006.176.07:45:31.20#ibcon#about to write, iclass 30, count 2 2006.176.07:45:31.20#ibcon#wrote, iclass 30, count 2 2006.176.07:45:31.20#ibcon#about to read 3, iclass 30, count 2 2006.176.07:45:31.23#ibcon#read 3, iclass 30, count 2 2006.176.07:45:31.23#ibcon#about to read 4, iclass 30, count 2 2006.176.07:45:31.23#ibcon#read 4, iclass 30, count 2 2006.176.07:45:31.23#ibcon#about to read 5, iclass 30, count 2 2006.176.07:45:31.23#ibcon#read 5, iclass 30, count 2 2006.176.07:45:31.23#ibcon#about to read 6, iclass 30, count 2 2006.176.07:45:31.23#ibcon#read 6, iclass 30, count 2 2006.176.07:45:31.23#ibcon#end of sib2, iclass 30, count 2 2006.176.07:45:31.23#ibcon#*after write, iclass 30, count 2 2006.176.07:45:31.23#ibcon#*before return 0, iclass 30, count 2 2006.176.07:45:31.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:31.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:45:31.23#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.07:45:31.23#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:31.23#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:31.35#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:31.35#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:31.35#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:45:31.35#ibcon#first serial, iclass 30, count 0 2006.176.07:45:31.35#ibcon#enter sib2, iclass 30, count 0 2006.176.07:45:31.35#ibcon#flushed, iclass 30, count 0 2006.176.07:45:31.35#ibcon#about to write, iclass 30, count 0 2006.176.07:45:31.35#ibcon#wrote, iclass 30, count 0 2006.176.07:45:31.35#ibcon#about to read 3, iclass 30, count 0 2006.176.07:45:31.37#ibcon#read 3, iclass 30, count 0 2006.176.07:45:31.37#ibcon#about to read 4, iclass 30, count 0 2006.176.07:45:31.37#ibcon#read 4, iclass 30, count 0 2006.176.07:45:31.37#ibcon#about to read 5, iclass 30, count 0 2006.176.07:45:31.37#ibcon#read 5, iclass 30, count 0 2006.176.07:45:31.37#ibcon#about to read 6, iclass 30, count 0 2006.176.07:45:31.37#ibcon#read 6, iclass 30, count 0 2006.176.07:45:31.37#ibcon#end of sib2, iclass 30, count 0 2006.176.07:45:31.37#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:45:31.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:45:31.37#ibcon#[27=USB\r\n] 2006.176.07:45:31.37#ibcon#*before write, iclass 30, count 0 2006.176.07:45:31.37#ibcon#enter sib2, iclass 30, count 0 2006.176.07:45:31.37#ibcon#flushed, iclass 30, count 0 2006.176.07:45:31.37#ibcon#about to write, iclass 30, count 0 2006.176.07:45:31.37#ibcon#wrote, iclass 30, count 0 2006.176.07:45:31.37#ibcon#about to read 3, iclass 30, count 0 2006.176.07:45:31.40#ibcon#read 3, iclass 30, count 0 2006.176.07:45:31.40#ibcon#about to read 4, iclass 30, count 0 2006.176.07:45:31.40#ibcon#read 4, iclass 30, count 0 2006.176.07:45:31.40#ibcon#about to read 5, iclass 30, count 0 2006.176.07:45:31.40#ibcon#read 5, iclass 30, count 0 2006.176.07:45:31.40#ibcon#about to read 6, iclass 30, count 0 2006.176.07:45:31.40#ibcon#read 6, iclass 30, count 0 2006.176.07:45:31.40#ibcon#end of sib2, iclass 30, count 0 2006.176.07:45:31.40#ibcon#*after write, iclass 30, count 0 2006.176.07:45:31.40#ibcon#*before return 0, iclass 30, count 0 2006.176.07:45:31.40#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:31.40#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:45:31.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:45:31.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:45:31.40$vc4f8/vblo=3,656.99 2006.176.07:45:31.40#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.07:45:31.40#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.07:45:31.40#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:31.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:31.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:31.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:31.40#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:45:31.40#ibcon#first serial, iclass 32, count 0 2006.176.07:45:31.40#ibcon#enter sib2, iclass 32, count 0 2006.176.07:45:31.40#ibcon#flushed, iclass 32, count 0 2006.176.07:45:31.40#ibcon#about to write, iclass 32, count 0 2006.176.07:45:31.40#ibcon#wrote, iclass 32, count 0 2006.176.07:45:31.40#ibcon#about to read 3, iclass 32, count 0 2006.176.07:45:31.42#ibcon#read 3, iclass 32, count 0 2006.176.07:45:31.42#ibcon#about to read 4, iclass 32, count 0 2006.176.07:45:31.42#ibcon#read 4, iclass 32, count 0 2006.176.07:45:31.42#ibcon#about to read 5, iclass 32, count 0 2006.176.07:45:31.42#ibcon#read 5, iclass 32, count 0 2006.176.07:45:31.42#ibcon#about to read 6, iclass 32, count 0 2006.176.07:45:31.42#ibcon#read 6, iclass 32, count 0 2006.176.07:45:31.42#ibcon#end of sib2, iclass 32, count 0 2006.176.07:45:31.42#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:45:31.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:45:31.42#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:45:31.42#ibcon#*before write, iclass 32, count 0 2006.176.07:45:31.42#ibcon#enter sib2, iclass 32, count 0 2006.176.07:45:31.42#ibcon#flushed, iclass 32, count 0 2006.176.07:45:31.42#ibcon#about to write, iclass 32, count 0 2006.176.07:45:31.42#ibcon#wrote, iclass 32, count 0 2006.176.07:45:31.42#ibcon#about to read 3, iclass 32, count 0 2006.176.07:45:31.46#ibcon#read 3, iclass 32, count 0 2006.176.07:45:31.46#ibcon#about to read 4, iclass 32, count 0 2006.176.07:45:31.46#ibcon#read 4, iclass 32, count 0 2006.176.07:45:31.46#ibcon#about to read 5, iclass 32, count 0 2006.176.07:45:31.46#ibcon#read 5, iclass 32, count 0 2006.176.07:45:31.46#ibcon#about to read 6, iclass 32, count 0 2006.176.07:45:31.46#ibcon#read 6, iclass 32, count 0 2006.176.07:45:31.46#ibcon#end of sib2, iclass 32, count 0 2006.176.07:45:31.46#ibcon#*after write, iclass 32, count 0 2006.176.07:45:31.46#ibcon#*before return 0, iclass 32, count 0 2006.176.07:45:31.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:31.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:45:31.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:45:31.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:45:31.46$vc4f8/vb=3,4 2006.176.07:45:31.46#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.07:45:31.46#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.07:45:31.46#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:31.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:31.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:31.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:31.52#ibcon#enter wrdev, iclass 34, count 2 2006.176.07:45:31.52#ibcon#first serial, iclass 34, count 2 2006.176.07:45:31.52#ibcon#enter sib2, iclass 34, count 2 2006.176.07:45:31.52#ibcon#flushed, iclass 34, count 2 2006.176.07:45:31.52#ibcon#about to write, iclass 34, count 2 2006.176.07:45:31.52#ibcon#wrote, iclass 34, count 2 2006.176.07:45:31.52#ibcon#about to read 3, iclass 34, count 2 2006.176.07:45:31.54#ibcon#read 3, iclass 34, count 2 2006.176.07:45:31.54#ibcon#about to read 4, iclass 34, count 2 2006.176.07:45:31.54#ibcon#read 4, iclass 34, count 2 2006.176.07:45:31.54#ibcon#about to read 5, iclass 34, count 2 2006.176.07:45:31.54#ibcon#read 5, iclass 34, count 2 2006.176.07:45:31.54#ibcon#about to read 6, iclass 34, count 2 2006.176.07:45:31.54#ibcon#read 6, iclass 34, count 2 2006.176.07:45:31.54#ibcon#end of sib2, iclass 34, count 2 2006.176.07:45:31.54#ibcon#*mode == 0, iclass 34, count 2 2006.176.07:45:31.54#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.07:45:31.54#ibcon#[27=AT03-04\r\n] 2006.176.07:45:31.54#ibcon#*before write, iclass 34, count 2 2006.176.07:45:31.54#ibcon#enter sib2, iclass 34, count 2 2006.176.07:45:31.54#ibcon#flushed, iclass 34, count 2 2006.176.07:45:31.54#ibcon#about to write, iclass 34, count 2 2006.176.07:45:31.54#ibcon#wrote, iclass 34, count 2 2006.176.07:45:31.54#ibcon#about to read 3, iclass 34, count 2 2006.176.07:45:31.57#ibcon#read 3, iclass 34, count 2 2006.176.07:45:31.57#ibcon#about to read 4, iclass 34, count 2 2006.176.07:45:31.57#ibcon#read 4, iclass 34, count 2 2006.176.07:45:31.57#ibcon#about to read 5, iclass 34, count 2 2006.176.07:45:31.57#ibcon#read 5, iclass 34, count 2 2006.176.07:45:31.57#ibcon#about to read 6, iclass 34, count 2 2006.176.07:45:31.57#ibcon#read 6, iclass 34, count 2 2006.176.07:45:31.57#ibcon#end of sib2, iclass 34, count 2 2006.176.07:45:31.57#ibcon#*after write, iclass 34, count 2 2006.176.07:45:31.57#ibcon#*before return 0, iclass 34, count 2 2006.176.07:45:31.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:31.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:45:31.57#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.07:45:31.57#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:31.57#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:31.68#abcon#<5=/04 2.7 4.8 23.90 911008.4\r\n> 2006.176.07:45:31.69#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:31.69#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:31.69#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:45:31.69#ibcon#first serial, iclass 34, count 0 2006.176.07:45:31.69#ibcon#enter sib2, iclass 34, count 0 2006.176.07:45:31.69#ibcon#flushed, iclass 34, count 0 2006.176.07:45:31.69#ibcon#about to write, iclass 34, count 0 2006.176.07:45:31.69#ibcon#wrote, iclass 34, count 0 2006.176.07:45:31.69#ibcon#about to read 3, iclass 34, count 0 2006.176.07:45:31.70#abcon#{5=INTERFACE CLEAR} 2006.176.07:45:31.71#ibcon#read 3, iclass 34, count 0 2006.176.07:45:31.71#ibcon#about to read 4, iclass 34, count 0 2006.176.07:45:31.71#ibcon#read 4, iclass 34, count 0 2006.176.07:45:31.71#ibcon#about to read 5, iclass 34, count 0 2006.176.07:45:31.71#ibcon#read 5, iclass 34, count 0 2006.176.07:45:31.71#ibcon#about to read 6, iclass 34, count 0 2006.176.07:45:31.71#ibcon#read 6, iclass 34, count 0 2006.176.07:45:31.71#ibcon#end of sib2, iclass 34, count 0 2006.176.07:45:31.71#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:45:31.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:45:31.71#ibcon#[27=USB\r\n] 2006.176.07:45:31.71#ibcon#*before write, iclass 34, count 0 2006.176.07:45:31.71#ibcon#enter sib2, iclass 34, count 0 2006.176.07:45:31.71#ibcon#flushed, iclass 34, count 0 2006.176.07:45:31.71#ibcon#about to write, iclass 34, count 0 2006.176.07:45:31.71#ibcon#wrote, iclass 34, count 0 2006.176.07:45:31.71#ibcon#about to read 3, iclass 34, count 0 2006.176.07:45:31.74#ibcon#read 3, iclass 34, count 0 2006.176.07:45:31.74#ibcon#about to read 4, iclass 34, count 0 2006.176.07:45:31.74#ibcon#read 4, iclass 34, count 0 2006.176.07:45:31.74#ibcon#about to read 5, iclass 34, count 0 2006.176.07:45:31.74#ibcon#read 5, iclass 34, count 0 2006.176.07:45:31.74#ibcon#about to read 6, iclass 34, count 0 2006.176.07:45:31.74#ibcon#read 6, iclass 34, count 0 2006.176.07:45:31.74#ibcon#end of sib2, iclass 34, count 0 2006.176.07:45:31.74#ibcon#*after write, iclass 34, count 0 2006.176.07:45:31.74#ibcon#*before return 0, iclass 34, count 0 2006.176.07:45:31.74#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:31.74#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:45:31.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:45:31.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:45:31.74$vc4f8/vblo=4,712.99 2006.176.07:45:31.74#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.07:45:31.74#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.07:45:31.74#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:31.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:45:31.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:45:31.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:45:31.74#ibcon#enter wrdev, iclass 39, count 0 2006.176.07:45:31.74#ibcon#first serial, iclass 39, count 0 2006.176.07:45:31.74#ibcon#enter sib2, iclass 39, count 0 2006.176.07:45:31.74#ibcon#flushed, iclass 39, count 0 2006.176.07:45:31.74#ibcon#about to write, iclass 39, count 0 2006.176.07:45:31.74#ibcon#wrote, iclass 39, count 0 2006.176.07:45:31.74#ibcon#about to read 3, iclass 39, count 0 2006.176.07:45:31.76#ibcon#read 3, iclass 39, count 0 2006.176.07:45:31.76#ibcon#about to read 4, iclass 39, count 0 2006.176.07:45:31.76#ibcon#read 4, iclass 39, count 0 2006.176.07:45:31.76#ibcon#about to read 5, iclass 39, count 0 2006.176.07:45:31.76#ibcon#read 5, iclass 39, count 0 2006.176.07:45:31.76#ibcon#about to read 6, iclass 39, count 0 2006.176.07:45:31.76#ibcon#read 6, iclass 39, count 0 2006.176.07:45:31.76#ibcon#end of sib2, iclass 39, count 0 2006.176.07:45:31.76#ibcon#*mode == 0, iclass 39, count 0 2006.176.07:45:31.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.07:45:31.76#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:45:31.76#ibcon#*before write, iclass 39, count 0 2006.176.07:45:31.76#ibcon#enter sib2, iclass 39, count 0 2006.176.07:45:31.76#ibcon#flushed, iclass 39, count 0 2006.176.07:45:31.76#ibcon#about to write, iclass 39, count 0 2006.176.07:45:31.76#ibcon#wrote, iclass 39, count 0 2006.176.07:45:31.76#ibcon#about to read 3, iclass 39, count 0 2006.176.07:45:31.76#abcon#[5=S1D000X0/0*\r\n] 2006.176.07:45:31.80#ibcon#read 3, iclass 39, count 0 2006.176.07:45:31.80#ibcon#about to read 4, iclass 39, count 0 2006.176.07:45:31.80#ibcon#read 4, iclass 39, count 0 2006.176.07:45:31.80#ibcon#about to read 5, iclass 39, count 0 2006.176.07:45:31.80#ibcon#read 5, iclass 39, count 0 2006.176.07:45:31.80#ibcon#about to read 6, iclass 39, count 0 2006.176.07:45:31.80#ibcon#read 6, iclass 39, count 0 2006.176.07:45:31.80#ibcon#end of sib2, iclass 39, count 0 2006.176.07:45:31.80#ibcon#*after write, iclass 39, count 0 2006.176.07:45:31.80#ibcon#*before return 0, iclass 39, count 0 2006.176.07:45:31.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:45:31.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:45:31.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.07:45:31.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.07:45:31.80$vc4f8/vb=4,4 2006.176.07:45:31.80#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.07:45:31.80#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.07:45:31.80#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:31.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:31.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:31.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:31.86#ibcon#enter wrdev, iclass 4, count 2 2006.176.07:45:31.86#ibcon#first serial, iclass 4, count 2 2006.176.07:45:31.86#ibcon#enter sib2, iclass 4, count 2 2006.176.07:45:31.86#ibcon#flushed, iclass 4, count 2 2006.176.07:45:31.86#ibcon#about to write, iclass 4, count 2 2006.176.07:45:31.86#ibcon#wrote, iclass 4, count 2 2006.176.07:45:31.86#ibcon#about to read 3, iclass 4, count 2 2006.176.07:45:31.88#ibcon#read 3, iclass 4, count 2 2006.176.07:45:31.88#ibcon#about to read 4, iclass 4, count 2 2006.176.07:45:31.88#ibcon#read 4, iclass 4, count 2 2006.176.07:45:31.88#ibcon#about to read 5, iclass 4, count 2 2006.176.07:45:31.88#ibcon#read 5, iclass 4, count 2 2006.176.07:45:31.88#ibcon#about to read 6, iclass 4, count 2 2006.176.07:45:31.88#ibcon#read 6, iclass 4, count 2 2006.176.07:45:31.88#ibcon#end of sib2, iclass 4, count 2 2006.176.07:45:31.88#ibcon#*mode == 0, iclass 4, count 2 2006.176.07:45:31.88#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.07:45:31.88#ibcon#[27=AT04-04\r\n] 2006.176.07:45:31.88#ibcon#*before write, iclass 4, count 2 2006.176.07:45:31.88#ibcon#enter sib2, iclass 4, count 2 2006.176.07:45:31.88#ibcon#flushed, iclass 4, count 2 2006.176.07:45:31.88#ibcon#about to write, iclass 4, count 2 2006.176.07:45:31.88#ibcon#wrote, iclass 4, count 2 2006.176.07:45:31.88#ibcon#about to read 3, iclass 4, count 2 2006.176.07:45:31.91#ibcon#read 3, iclass 4, count 2 2006.176.07:45:31.91#ibcon#about to read 4, iclass 4, count 2 2006.176.07:45:31.91#ibcon#read 4, iclass 4, count 2 2006.176.07:45:31.91#ibcon#about to read 5, iclass 4, count 2 2006.176.07:45:31.91#ibcon#read 5, iclass 4, count 2 2006.176.07:45:31.91#ibcon#about to read 6, iclass 4, count 2 2006.176.07:45:31.91#ibcon#read 6, iclass 4, count 2 2006.176.07:45:31.91#ibcon#end of sib2, iclass 4, count 2 2006.176.07:45:31.91#ibcon#*after write, iclass 4, count 2 2006.176.07:45:31.91#ibcon#*before return 0, iclass 4, count 2 2006.176.07:45:31.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:31.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:45:31.91#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.07:45:31.91#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:31.91#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:32.03#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:32.03#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:32.03#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:45:32.03#ibcon#first serial, iclass 4, count 0 2006.176.07:45:32.03#ibcon#enter sib2, iclass 4, count 0 2006.176.07:45:32.03#ibcon#flushed, iclass 4, count 0 2006.176.07:45:32.03#ibcon#about to write, iclass 4, count 0 2006.176.07:45:32.03#ibcon#wrote, iclass 4, count 0 2006.176.07:45:32.03#ibcon#about to read 3, iclass 4, count 0 2006.176.07:45:32.05#ibcon#read 3, iclass 4, count 0 2006.176.07:45:32.05#ibcon#about to read 4, iclass 4, count 0 2006.176.07:45:32.05#ibcon#read 4, iclass 4, count 0 2006.176.07:45:32.05#ibcon#about to read 5, iclass 4, count 0 2006.176.07:45:32.05#ibcon#read 5, iclass 4, count 0 2006.176.07:45:32.05#ibcon#about to read 6, iclass 4, count 0 2006.176.07:45:32.05#ibcon#read 6, iclass 4, count 0 2006.176.07:45:32.05#ibcon#end of sib2, iclass 4, count 0 2006.176.07:45:32.05#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:45:32.05#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:45:32.05#ibcon#[27=USB\r\n] 2006.176.07:45:32.05#ibcon#*before write, iclass 4, count 0 2006.176.07:45:32.05#ibcon#enter sib2, iclass 4, count 0 2006.176.07:45:32.05#ibcon#flushed, iclass 4, count 0 2006.176.07:45:32.05#ibcon#about to write, iclass 4, count 0 2006.176.07:45:32.05#ibcon#wrote, iclass 4, count 0 2006.176.07:45:32.05#ibcon#about to read 3, iclass 4, count 0 2006.176.07:45:32.08#ibcon#read 3, iclass 4, count 0 2006.176.07:45:32.08#ibcon#about to read 4, iclass 4, count 0 2006.176.07:45:32.08#ibcon#read 4, iclass 4, count 0 2006.176.07:45:32.08#ibcon#about to read 5, iclass 4, count 0 2006.176.07:45:32.08#ibcon#read 5, iclass 4, count 0 2006.176.07:45:32.08#ibcon#about to read 6, iclass 4, count 0 2006.176.07:45:32.08#ibcon#read 6, iclass 4, count 0 2006.176.07:45:32.08#ibcon#end of sib2, iclass 4, count 0 2006.176.07:45:32.08#ibcon#*after write, iclass 4, count 0 2006.176.07:45:32.08#ibcon#*before return 0, iclass 4, count 0 2006.176.07:45:32.08#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:32.08#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:45:32.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:45:32.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:45:32.08$vc4f8/vblo=5,744.99 2006.176.07:45:32.08#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.07:45:32.08#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.07:45:32.08#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:32.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:32.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:32.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:32.08#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:45:32.08#ibcon#first serial, iclass 6, count 0 2006.176.07:45:32.08#ibcon#enter sib2, iclass 6, count 0 2006.176.07:45:32.08#ibcon#flushed, iclass 6, count 0 2006.176.07:45:32.08#ibcon#about to write, iclass 6, count 0 2006.176.07:45:32.08#ibcon#wrote, iclass 6, count 0 2006.176.07:45:32.08#ibcon#about to read 3, iclass 6, count 0 2006.176.07:45:32.10#ibcon#read 3, iclass 6, count 0 2006.176.07:45:32.10#ibcon#about to read 4, iclass 6, count 0 2006.176.07:45:32.10#ibcon#read 4, iclass 6, count 0 2006.176.07:45:32.10#ibcon#about to read 5, iclass 6, count 0 2006.176.07:45:32.10#ibcon#read 5, iclass 6, count 0 2006.176.07:45:32.10#ibcon#about to read 6, iclass 6, count 0 2006.176.07:45:32.10#ibcon#read 6, iclass 6, count 0 2006.176.07:45:32.10#ibcon#end of sib2, iclass 6, count 0 2006.176.07:45:32.10#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:45:32.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:45:32.10#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:45:32.10#ibcon#*before write, iclass 6, count 0 2006.176.07:45:32.10#ibcon#enter sib2, iclass 6, count 0 2006.176.07:45:32.10#ibcon#flushed, iclass 6, count 0 2006.176.07:45:32.10#ibcon#about to write, iclass 6, count 0 2006.176.07:45:32.10#ibcon#wrote, iclass 6, count 0 2006.176.07:45:32.10#ibcon#about to read 3, iclass 6, count 0 2006.176.07:45:32.14#ibcon#read 3, iclass 6, count 0 2006.176.07:45:32.14#ibcon#about to read 4, iclass 6, count 0 2006.176.07:45:32.14#ibcon#read 4, iclass 6, count 0 2006.176.07:45:32.14#ibcon#about to read 5, iclass 6, count 0 2006.176.07:45:32.14#ibcon#read 5, iclass 6, count 0 2006.176.07:45:32.14#ibcon#about to read 6, iclass 6, count 0 2006.176.07:45:32.14#ibcon#read 6, iclass 6, count 0 2006.176.07:45:32.14#ibcon#end of sib2, iclass 6, count 0 2006.176.07:45:32.14#ibcon#*after write, iclass 6, count 0 2006.176.07:45:32.14#ibcon#*before return 0, iclass 6, count 0 2006.176.07:45:32.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:32.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:45:32.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:45:32.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:45:32.14$vc4f8/vb=5,4 2006.176.07:45:32.14#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.07:45:32.14#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.07:45:32.14#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:32.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:32.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:32.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:32.20#ibcon#enter wrdev, iclass 10, count 2 2006.176.07:45:32.20#ibcon#first serial, iclass 10, count 2 2006.176.07:45:32.20#ibcon#enter sib2, iclass 10, count 2 2006.176.07:45:32.20#ibcon#flushed, iclass 10, count 2 2006.176.07:45:32.20#ibcon#about to write, iclass 10, count 2 2006.176.07:45:32.20#ibcon#wrote, iclass 10, count 2 2006.176.07:45:32.20#ibcon#about to read 3, iclass 10, count 2 2006.176.07:45:32.22#ibcon#read 3, iclass 10, count 2 2006.176.07:45:32.22#ibcon#about to read 4, iclass 10, count 2 2006.176.07:45:32.22#ibcon#read 4, iclass 10, count 2 2006.176.07:45:32.22#ibcon#about to read 5, iclass 10, count 2 2006.176.07:45:32.22#ibcon#read 5, iclass 10, count 2 2006.176.07:45:32.22#ibcon#about to read 6, iclass 10, count 2 2006.176.07:45:32.22#ibcon#read 6, iclass 10, count 2 2006.176.07:45:32.22#ibcon#end of sib2, iclass 10, count 2 2006.176.07:45:32.22#ibcon#*mode == 0, iclass 10, count 2 2006.176.07:45:32.22#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.07:45:32.22#ibcon#[27=AT05-04\r\n] 2006.176.07:45:32.22#ibcon#*before write, iclass 10, count 2 2006.176.07:45:32.22#ibcon#enter sib2, iclass 10, count 2 2006.176.07:45:32.22#ibcon#flushed, iclass 10, count 2 2006.176.07:45:32.22#ibcon#about to write, iclass 10, count 2 2006.176.07:45:32.22#ibcon#wrote, iclass 10, count 2 2006.176.07:45:32.22#ibcon#about to read 3, iclass 10, count 2 2006.176.07:45:32.25#ibcon#read 3, iclass 10, count 2 2006.176.07:45:32.25#ibcon#about to read 4, iclass 10, count 2 2006.176.07:45:32.25#ibcon#read 4, iclass 10, count 2 2006.176.07:45:32.25#ibcon#about to read 5, iclass 10, count 2 2006.176.07:45:32.25#ibcon#read 5, iclass 10, count 2 2006.176.07:45:32.25#ibcon#about to read 6, iclass 10, count 2 2006.176.07:45:32.25#ibcon#read 6, iclass 10, count 2 2006.176.07:45:32.25#ibcon#end of sib2, iclass 10, count 2 2006.176.07:45:32.25#ibcon#*after write, iclass 10, count 2 2006.176.07:45:32.25#ibcon#*before return 0, iclass 10, count 2 2006.176.07:45:32.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:32.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:45:32.25#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.07:45:32.25#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:32.25#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:32.37#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:32.37#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:32.37#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:45:32.37#ibcon#first serial, iclass 10, count 0 2006.176.07:45:32.37#ibcon#enter sib2, iclass 10, count 0 2006.176.07:45:32.37#ibcon#flushed, iclass 10, count 0 2006.176.07:45:32.37#ibcon#about to write, iclass 10, count 0 2006.176.07:45:32.37#ibcon#wrote, iclass 10, count 0 2006.176.07:45:32.37#ibcon#about to read 3, iclass 10, count 0 2006.176.07:45:32.39#ibcon#read 3, iclass 10, count 0 2006.176.07:45:32.39#ibcon#about to read 4, iclass 10, count 0 2006.176.07:45:32.39#ibcon#read 4, iclass 10, count 0 2006.176.07:45:32.39#ibcon#about to read 5, iclass 10, count 0 2006.176.07:45:32.39#ibcon#read 5, iclass 10, count 0 2006.176.07:45:32.39#ibcon#about to read 6, iclass 10, count 0 2006.176.07:45:32.39#ibcon#read 6, iclass 10, count 0 2006.176.07:45:32.39#ibcon#end of sib2, iclass 10, count 0 2006.176.07:45:32.39#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:45:32.39#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:45:32.39#ibcon#[27=USB\r\n] 2006.176.07:45:32.39#ibcon#*before write, iclass 10, count 0 2006.176.07:45:32.39#ibcon#enter sib2, iclass 10, count 0 2006.176.07:45:32.39#ibcon#flushed, iclass 10, count 0 2006.176.07:45:32.39#ibcon#about to write, iclass 10, count 0 2006.176.07:45:32.39#ibcon#wrote, iclass 10, count 0 2006.176.07:45:32.39#ibcon#about to read 3, iclass 10, count 0 2006.176.07:45:32.42#ibcon#read 3, iclass 10, count 0 2006.176.07:45:32.42#ibcon#about to read 4, iclass 10, count 0 2006.176.07:45:32.42#ibcon#read 4, iclass 10, count 0 2006.176.07:45:32.42#ibcon#about to read 5, iclass 10, count 0 2006.176.07:45:32.42#ibcon#read 5, iclass 10, count 0 2006.176.07:45:32.42#ibcon#about to read 6, iclass 10, count 0 2006.176.07:45:32.42#ibcon#read 6, iclass 10, count 0 2006.176.07:45:32.42#ibcon#end of sib2, iclass 10, count 0 2006.176.07:45:32.42#ibcon#*after write, iclass 10, count 0 2006.176.07:45:32.42#ibcon#*before return 0, iclass 10, count 0 2006.176.07:45:32.42#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:32.42#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:45:32.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:45:32.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:45:32.42$vc4f8/vblo=6,752.99 2006.176.07:45:32.42#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.07:45:32.42#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.07:45:32.42#ibcon#ireg 17 cls_cnt 0 2006.176.07:45:32.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:32.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:32.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:32.42#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:45:32.42#ibcon#first serial, iclass 12, count 0 2006.176.07:45:32.42#ibcon#enter sib2, iclass 12, count 0 2006.176.07:45:32.42#ibcon#flushed, iclass 12, count 0 2006.176.07:45:32.42#ibcon#about to write, iclass 12, count 0 2006.176.07:45:32.42#ibcon#wrote, iclass 12, count 0 2006.176.07:45:32.42#ibcon#about to read 3, iclass 12, count 0 2006.176.07:45:32.44#ibcon#read 3, iclass 12, count 0 2006.176.07:45:32.44#ibcon#about to read 4, iclass 12, count 0 2006.176.07:45:32.44#ibcon#read 4, iclass 12, count 0 2006.176.07:45:32.44#ibcon#about to read 5, iclass 12, count 0 2006.176.07:45:32.44#ibcon#read 5, iclass 12, count 0 2006.176.07:45:32.44#ibcon#about to read 6, iclass 12, count 0 2006.176.07:45:32.44#ibcon#read 6, iclass 12, count 0 2006.176.07:45:32.44#ibcon#end of sib2, iclass 12, count 0 2006.176.07:45:32.44#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:45:32.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:45:32.44#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:45:32.44#ibcon#*before write, iclass 12, count 0 2006.176.07:45:32.44#ibcon#enter sib2, iclass 12, count 0 2006.176.07:45:32.44#ibcon#flushed, iclass 12, count 0 2006.176.07:45:32.44#ibcon#about to write, iclass 12, count 0 2006.176.07:45:32.44#ibcon#wrote, iclass 12, count 0 2006.176.07:45:32.44#ibcon#about to read 3, iclass 12, count 0 2006.176.07:45:32.48#ibcon#read 3, iclass 12, count 0 2006.176.07:45:32.48#ibcon#about to read 4, iclass 12, count 0 2006.176.07:45:32.48#ibcon#read 4, iclass 12, count 0 2006.176.07:45:32.48#ibcon#about to read 5, iclass 12, count 0 2006.176.07:45:32.48#ibcon#read 5, iclass 12, count 0 2006.176.07:45:32.48#ibcon#about to read 6, iclass 12, count 0 2006.176.07:45:32.48#ibcon#read 6, iclass 12, count 0 2006.176.07:45:32.48#ibcon#end of sib2, iclass 12, count 0 2006.176.07:45:32.48#ibcon#*after write, iclass 12, count 0 2006.176.07:45:32.48#ibcon#*before return 0, iclass 12, count 0 2006.176.07:45:32.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:32.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:45:32.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:45:32.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:45:32.48$vc4f8/vb=6,4 2006.176.07:45:32.48#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.07:45:32.48#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.07:45:32.48#ibcon#ireg 11 cls_cnt 2 2006.176.07:45:32.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:32.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:32.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:32.54#ibcon#enter wrdev, iclass 14, count 2 2006.176.07:45:32.54#ibcon#first serial, iclass 14, count 2 2006.176.07:45:32.54#ibcon#enter sib2, iclass 14, count 2 2006.176.07:45:32.54#ibcon#flushed, iclass 14, count 2 2006.176.07:45:32.54#ibcon#about to write, iclass 14, count 2 2006.176.07:45:32.54#ibcon#wrote, iclass 14, count 2 2006.176.07:45:32.54#ibcon#about to read 3, iclass 14, count 2 2006.176.07:45:32.56#ibcon#read 3, iclass 14, count 2 2006.176.07:45:32.56#ibcon#about to read 4, iclass 14, count 2 2006.176.07:45:32.56#ibcon#read 4, iclass 14, count 2 2006.176.07:45:32.56#ibcon#about to read 5, iclass 14, count 2 2006.176.07:45:32.56#ibcon#read 5, iclass 14, count 2 2006.176.07:45:32.56#ibcon#about to read 6, iclass 14, count 2 2006.176.07:45:32.56#ibcon#read 6, iclass 14, count 2 2006.176.07:45:32.56#ibcon#end of sib2, iclass 14, count 2 2006.176.07:45:32.56#ibcon#*mode == 0, iclass 14, count 2 2006.176.07:45:32.56#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.07:45:32.56#ibcon#[27=AT06-04\r\n] 2006.176.07:45:32.56#ibcon#*before write, iclass 14, count 2 2006.176.07:45:32.56#ibcon#enter sib2, iclass 14, count 2 2006.176.07:45:32.56#ibcon#flushed, iclass 14, count 2 2006.176.07:45:32.56#ibcon#about to write, iclass 14, count 2 2006.176.07:45:32.56#ibcon#wrote, iclass 14, count 2 2006.176.07:45:32.56#ibcon#about to read 3, iclass 14, count 2 2006.176.07:45:32.59#ibcon#read 3, iclass 14, count 2 2006.176.07:45:32.59#ibcon#about to read 4, iclass 14, count 2 2006.176.07:45:32.59#ibcon#read 4, iclass 14, count 2 2006.176.07:45:32.59#ibcon#about to read 5, iclass 14, count 2 2006.176.07:45:32.59#ibcon#read 5, iclass 14, count 2 2006.176.07:45:32.59#ibcon#about to read 6, iclass 14, count 2 2006.176.07:45:32.59#ibcon#read 6, iclass 14, count 2 2006.176.07:45:32.59#ibcon#end of sib2, iclass 14, count 2 2006.176.07:45:32.59#ibcon#*after write, iclass 14, count 2 2006.176.07:45:32.59#ibcon#*before return 0, iclass 14, count 2 2006.176.07:45:32.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:32.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:45:32.59#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.07:45:32.59#ibcon#ireg 7 cls_cnt 0 2006.176.07:45:32.59#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:32.71#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:32.71#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:32.71#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:45:32.71#ibcon#first serial, iclass 14, count 0 2006.176.07:45:32.71#ibcon#enter sib2, iclass 14, count 0 2006.176.07:45:32.71#ibcon#flushed, iclass 14, count 0 2006.176.07:45:32.71#ibcon#about to write, iclass 14, count 0 2006.176.07:45:32.71#ibcon#wrote, iclass 14, count 0 2006.176.07:45:32.71#ibcon#about to read 3, iclass 14, count 0 2006.176.07:45:32.73#ibcon#read 3, iclass 14, count 0 2006.176.07:45:32.73#ibcon#about to read 4, iclass 14, count 0 2006.176.07:45:32.73#ibcon#read 4, iclass 14, count 0 2006.176.07:45:32.73#ibcon#about to read 5, iclass 14, count 0 2006.176.07:45:32.73#ibcon#read 5, iclass 14, count 0 2006.176.07:45:32.73#ibcon#about to read 6, iclass 14, count 0 2006.176.07:45:32.73#ibcon#read 6, iclass 14, count 0 2006.176.07:45:32.73#ibcon#end of sib2, iclass 14, count 0 2006.176.07:45:32.73#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:45:32.73#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:45:32.73#ibcon#[27=USB\r\n] 2006.176.07:45:32.73#ibcon#*before write, iclass 14, count 0 2006.176.07:45:32.73#ibcon#enter sib2, iclass 14, count 0 2006.176.07:45:32.73#ibcon#flushed, iclass 14, count 0 2006.176.07:45:32.73#ibcon#about to write, iclass 14, count 0 2006.176.07:45:32.73#ibcon#wrote, iclass 14, count 0 2006.176.07:45:32.73#ibcon#about to read 3, iclass 14, count 0 2006.176.07:45:32.76#ibcon#read 3, iclass 14, count 0 2006.176.07:45:32.76#ibcon#about to read 4, iclass 14, count 0 2006.176.07:45:32.76#ibcon#read 4, iclass 14, count 0 2006.176.07:45:32.76#ibcon#about to read 5, iclass 14, count 0 2006.176.07:45:32.76#ibcon#read 5, iclass 14, count 0 2006.176.07:45:32.76#ibcon#about to read 6, iclass 14, count 0 2006.176.07:45:32.76#ibcon#read 6, iclass 14, count 0 2006.176.07:45:32.76#ibcon#end of sib2, iclass 14, count 0 2006.176.07:45:32.76#ibcon#*after write, iclass 14, count 0 2006.176.07:45:32.76#ibcon#*before return 0, iclass 14, count 0 2006.176.07:45:32.76#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:32.76#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:45:32.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:45:32.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:45:32.76$vc4f8/vabw=wide 2006.176.07:45:32.76#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:45:32.76#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:45:32.76#ibcon#ireg 8 cls_cnt 0 2006.176.07:45:32.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:32.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:32.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:32.76#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:45:32.76#ibcon#first serial, iclass 16, count 0 2006.176.07:45:32.76#ibcon#enter sib2, iclass 16, count 0 2006.176.07:45:32.76#ibcon#flushed, iclass 16, count 0 2006.176.07:45:32.76#ibcon#about to write, iclass 16, count 0 2006.176.07:45:32.76#ibcon#wrote, iclass 16, count 0 2006.176.07:45:32.76#ibcon#about to read 3, iclass 16, count 0 2006.176.07:45:32.78#ibcon#read 3, iclass 16, count 0 2006.176.07:45:32.78#ibcon#about to read 4, iclass 16, count 0 2006.176.07:45:32.78#ibcon#read 4, iclass 16, count 0 2006.176.07:45:32.78#ibcon#about to read 5, iclass 16, count 0 2006.176.07:45:32.78#ibcon#read 5, iclass 16, count 0 2006.176.07:45:32.78#ibcon#about to read 6, iclass 16, count 0 2006.176.07:45:32.78#ibcon#read 6, iclass 16, count 0 2006.176.07:45:32.78#ibcon#end of sib2, iclass 16, count 0 2006.176.07:45:32.78#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:45:32.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:45:32.78#ibcon#[25=BW32\r\n] 2006.176.07:45:32.78#ibcon#*before write, iclass 16, count 0 2006.176.07:45:32.78#ibcon#enter sib2, iclass 16, count 0 2006.176.07:45:32.78#ibcon#flushed, iclass 16, count 0 2006.176.07:45:32.78#ibcon#about to write, iclass 16, count 0 2006.176.07:45:32.78#ibcon#wrote, iclass 16, count 0 2006.176.07:45:32.78#ibcon#about to read 3, iclass 16, count 0 2006.176.07:45:32.81#ibcon#read 3, iclass 16, count 0 2006.176.07:45:32.81#ibcon#about to read 4, iclass 16, count 0 2006.176.07:45:32.81#ibcon#read 4, iclass 16, count 0 2006.176.07:45:32.81#ibcon#about to read 5, iclass 16, count 0 2006.176.07:45:32.81#ibcon#read 5, iclass 16, count 0 2006.176.07:45:32.81#ibcon#about to read 6, iclass 16, count 0 2006.176.07:45:32.81#ibcon#read 6, iclass 16, count 0 2006.176.07:45:32.81#ibcon#end of sib2, iclass 16, count 0 2006.176.07:45:32.81#ibcon#*after write, iclass 16, count 0 2006.176.07:45:32.81#ibcon#*before return 0, iclass 16, count 0 2006.176.07:45:32.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:32.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:45:32.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:45:32.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:45:32.81$vc4f8/vbbw=wide 2006.176.07:45:32.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.07:45:32.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.07:45:32.81#ibcon#ireg 8 cls_cnt 0 2006.176.07:45:32.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:45:32.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:45:32.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:45:32.88#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:45:32.88#ibcon#first serial, iclass 18, count 0 2006.176.07:45:32.88#ibcon#enter sib2, iclass 18, count 0 2006.176.07:45:32.88#ibcon#flushed, iclass 18, count 0 2006.176.07:45:32.88#ibcon#about to write, iclass 18, count 0 2006.176.07:45:32.88#ibcon#wrote, iclass 18, count 0 2006.176.07:45:32.88#ibcon#about to read 3, iclass 18, count 0 2006.176.07:45:32.90#ibcon#read 3, iclass 18, count 0 2006.176.07:45:32.90#ibcon#about to read 4, iclass 18, count 0 2006.176.07:45:32.90#ibcon#read 4, iclass 18, count 0 2006.176.07:45:32.90#ibcon#about to read 5, iclass 18, count 0 2006.176.07:45:32.90#ibcon#read 5, iclass 18, count 0 2006.176.07:45:32.90#ibcon#about to read 6, iclass 18, count 0 2006.176.07:45:32.90#ibcon#read 6, iclass 18, count 0 2006.176.07:45:32.90#ibcon#end of sib2, iclass 18, count 0 2006.176.07:45:32.90#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:45:32.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:45:32.90#ibcon#[27=BW32\r\n] 2006.176.07:45:32.90#ibcon#*before write, iclass 18, count 0 2006.176.07:45:32.90#ibcon#enter sib2, iclass 18, count 0 2006.176.07:45:32.90#ibcon#flushed, iclass 18, count 0 2006.176.07:45:32.90#ibcon#about to write, iclass 18, count 0 2006.176.07:45:32.90#ibcon#wrote, iclass 18, count 0 2006.176.07:45:32.90#ibcon#about to read 3, iclass 18, count 0 2006.176.07:45:32.93#ibcon#read 3, iclass 18, count 0 2006.176.07:45:32.93#ibcon#about to read 4, iclass 18, count 0 2006.176.07:45:32.93#ibcon#read 4, iclass 18, count 0 2006.176.07:45:32.93#ibcon#about to read 5, iclass 18, count 0 2006.176.07:45:32.93#ibcon#read 5, iclass 18, count 0 2006.176.07:45:32.93#ibcon#about to read 6, iclass 18, count 0 2006.176.07:45:32.93#ibcon#read 6, iclass 18, count 0 2006.176.07:45:32.93#ibcon#end of sib2, iclass 18, count 0 2006.176.07:45:32.93#ibcon#*after write, iclass 18, count 0 2006.176.07:45:32.93#ibcon#*before return 0, iclass 18, count 0 2006.176.07:45:32.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:45:32.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:45:32.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:45:32.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:45:32.93$4f8m12a/ifd4f 2006.176.07:45:32.93$ifd4f/lo= 2006.176.07:45:32.93$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:45:32.93$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:45:32.93$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:45:32.93$ifd4f/patch= 2006.176.07:45:32.93$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:45:32.93$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:45:32.93$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:45:32.93$4f8m12a/"form=m,16.000,1:2 2006.176.07:45:32.93$4f8m12a/"tpicd 2006.176.07:45:32.93$4f8m12a/echo=off 2006.176.07:45:32.93$4f8m12a/xlog=off 2006.176.07:45:32.93:!2006.176.07:46:40 2006.176.07:46:15.14#trakl#Source acquired 2006.176.07:46:17.14#flagr#flagr/antenna,acquired 2006.176.07:46:40.00:preob 2006.176.07:46:40.14/onsource/TRACKING 2006.176.07:46:40.14:!2006.176.07:46:50 2006.176.07:46:50.00:data_valid=on 2006.176.07:46:50.00:midob 2006.176.07:46:50.14/onsource/TRACKING 2006.176.07:46:50.14/wx/23.90,1008.4,91 2006.176.07:46:50.21/cable/+6.4936E-03 2006.176.07:46:51.30/va/01,08,usb,yes,30,32 2006.176.07:46:51.30/va/02,07,usb,yes,30,32 2006.176.07:46:51.30/va/03,06,usb,yes,32,32 2006.176.07:46:51.30/va/04,07,usb,yes,31,33 2006.176.07:46:51.30/va/05,07,usb,yes,33,35 2006.176.07:46:51.30/va/06,06,usb,yes,32,32 2006.176.07:46:51.30/va/07,06,usb,yes,32,32 2006.176.07:46:51.30/va/08,06,usb,yes,35,34 2006.176.07:46:51.53/valo/01,532.99,yes,locked 2006.176.07:46:51.53/valo/02,572.99,yes,locked 2006.176.07:46:51.53/valo/03,672.99,yes,locked 2006.176.07:46:51.53/valo/04,832.99,yes,locked 2006.176.07:46:51.53/valo/05,652.99,yes,locked 2006.176.07:46:51.53/valo/06,772.99,yes,locked 2006.176.07:46:51.53/valo/07,832.99,yes,locked 2006.176.07:46:51.53/valo/08,852.99,yes,locked 2006.176.07:46:52.62/vb/01,04,usb,yes,29,28 2006.176.07:46:52.62/vb/02,04,usb,yes,31,32 2006.176.07:46:52.62/vb/03,04,usb,yes,27,31 2006.176.07:46:52.62/vb/04,04,usb,yes,28,28 2006.176.07:46:52.62/vb/05,04,usb,yes,27,31 2006.176.07:46:52.62/vb/06,04,usb,yes,28,30 2006.176.07:46:52.62/vb/07,04,usb,yes,30,30 2006.176.07:46:52.62/vb/08,04,usb,yes,27,31 2006.176.07:46:52.85/vblo/01,632.99,yes,locked 2006.176.07:46:52.85/vblo/02,640.99,yes,locked 2006.176.07:46:52.85/vblo/03,656.99,yes,locked 2006.176.07:46:52.85/vblo/04,712.99,yes,locked 2006.176.07:46:52.85/vblo/05,744.99,yes,locked 2006.176.07:46:52.85/vblo/06,752.99,yes,locked 2006.176.07:46:52.85/vblo/07,734.99,yes,locked 2006.176.07:46:52.85/vblo/08,744.99,yes,locked 2006.176.07:46:53.00/vabw/8 2006.176.07:46:53.15/vbbw/8 2006.176.07:46:53.24/xfe/off,on,15.2 2006.176.07:46:53.61/ifatt/23,28,28,28 2006.176.07:46:54.08/fmout-gps/S +3.74E-07 2006.176.07:46:54.15:!2006.176.07:47:50 2006.176.07:47:50.00:data_valid=off 2006.176.07:47:50.00:postob 2006.176.07:47:50.13/cable/+6.4929E-03 2006.176.07:47:50.13/wx/23.89,1008.4,91 2006.176.07:47:51.08/fmout-gps/S +3.74E-07 2006.176.07:47:51.08:scan_name=176-0748,k06176,60 2006.176.07:47:51.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.176.07:47:51.14#flagr#flagr/antenna,new-source 2006.176.07:47:52.14:checkk5 2006.176.07:47:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:47:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:47:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:47:53.69/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:47:54.06/chk_obsdata//k5ts1/T1760746??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:47:54.44/chk_obsdata//k5ts2/T1760746??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:47:54.81/chk_obsdata//k5ts3/T1760746??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:47:55.18/chk_obsdata//k5ts4/T1760746??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:47:55.87/k5log//k5ts1_log_newline 2006.176.07:47:56.58/k5log//k5ts2_log_newline 2006.176.07:47:57.29/k5log//k5ts3_log_newline 2006.176.07:47:58.00/k5log//k5ts4_log_newline 2006.176.07:47:58.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:47:58.02:4f8m12a=1 2006.176.07:47:58.02$4f8m12a/echo=on 2006.176.07:47:58.02$4f8m12a/pcalon 2006.176.07:47:58.02$pcalon/"no phase cal control is implemented here 2006.176.07:47:58.02$4f8m12a/"tpicd=stop 2006.176.07:47:58.03$4f8m12a/vc4f8 2006.176.07:47:58.03$vc4f8/valo=1,532.99 2006.176.07:47:58.03#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.07:47:58.03#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.07:47:58.03#ibcon#ireg 17 cls_cnt 0 2006.176.07:47:58.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:47:58.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:47:58.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:47:58.03#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:47:58.03#ibcon#first serial, iclass 3, count 0 2006.176.07:47:58.03#ibcon#enter sib2, iclass 3, count 0 2006.176.07:47:58.03#ibcon#flushed, iclass 3, count 0 2006.176.07:47:58.03#ibcon#about to write, iclass 3, count 0 2006.176.07:47:58.03#ibcon#wrote, iclass 3, count 0 2006.176.07:47:58.03#ibcon#about to read 3, iclass 3, count 0 2006.176.07:47:58.07#ibcon#read 3, iclass 3, count 0 2006.176.07:47:58.07#ibcon#about to read 4, iclass 3, count 0 2006.176.07:47:58.07#ibcon#read 4, iclass 3, count 0 2006.176.07:47:58.07#ibcon#about to read 5, iclass 3, count 0 2006.176.07:47:58.07#ibcon#read 5, iclass 3, count 0 2006.176.07:47:58.07#ibcon#about to read 6, iclass 3, count 0 2006.176.07:47:58.07#ibcon#read 6, iclass 3, count 0 2006.176.07:47:58.07#ibcon#end of sib2, iclass 3, count 0 2006.176.07:47:58.07#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:47:58.07#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:47:58.07#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:47:58.07#ibcon#*before write, iclass 3, count 0 2006.176.07:47:58.07#ibcon#enter sib2, iclass 3, count 0 2006.176.07:47:58.07#ibcon#flushed, iclass 3, count 0 2006.176.07:47:58.07#ibcon#about to write, iclass 3, count 0 2006.176.07:47:58.07#ibcon#wrote, iclass 3, count 0 2006.176.07:47:58.07#ibcon#about to read 3, iclass 3, count 0 2006.176.07:47:58.12#ibcon#read 3, iclass 3, count 0 2006.176.07:47:58.12#ibcon#about to read 4, iclass 3, count 0 2006.176.07:47:58.12#ibcon#read 4, iclass 3, count 0 2006.176.07:47:58.12#ibcon#about to read 5, iclass 3, count 0 2006.176.07:47:58.12#ibcon#read 5, iclass 3, count 0 2006.176.07:47:58.12#ibcon#about to read 6, iclass 3, count 0 2006.176.07:47:58.12#ibcon#read 6, iclass 3, count 0 2006.176.07:47:58.12#ibcon#end of sib2, iclass 3, count 0 2006.176.07:47:58.12#ibcon#*after write, iclass 3, count 0 2006.176.07:47:58.12#ibcon#*before return 0, iclass 3, count 0 2006.176.07:47:58.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:47:58.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:47:58.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:47:58.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:47:58.12$vc4f8/va=1,8 2006.176.07:47:58.12#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.176.07:47:58.12#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.176.07:47:58.12#ibcon#ireg 11 cls_cnt 2 2006.176.07:47:58.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:47:58.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:47:58.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:47:58.12#ibcon#enter wrdev, iclass 5, count 2 2006.176.07:47:58.12#ibcon#first serial, iclass 5, count 2 2006.176.07:47:58.12#ibcon#enter sib2, iclass 5, count 2 2006.176.07:47:58.12#ibcon#flushed, iclass 5, count 2 2006.176.07:47:58.12#ibcon#about to write, iclass 5, count 2 2006.176.07:47:58.12#ibcon#wrote, iclass 5, count 2 2006.176.07:47:58.12#ibcon#about to read 3, iclass 5, count 2 2006.176.07:47:58.14#ibcon#read 3, iclass 5, count 2 2006.176.07:47:58.14#ibcon#about to read 4, iclass 5, count 2 2006.176.07:47:58.14#ibcon#read 4, iclass 5, count 2 2006.176.07:47:58.14#ibcon#about to read 5, iclass 5, count 2 2006.176.07:47:58.14#ibcon#read 5, iclass 5, count 2 2006.176.07:47:58.14#ibcon#about to read 6, iclass 5, count 2 2006.176.07:47:58.14#ibcon#read 6, iclass 5, count 2 2006.176.07:47:58.14#ibcon#end of sib2, iclass 5, count 2 2006.176.07:47:58.14#ibcon#*mode == 0, iclass 5, count 2 2006.176.07:47:58.14#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.176.07:47:58.14#ibcon#[25=AT01-08\r\n] 2006.176.07:47:58.14#ibcon#*before write, iclass 5, count 2 2006.176.07:47:58.14#ibcon#enter sib2, iclass 5, count 2 2006.176.07:47:58.14#ibcon#flushed, iclass 5, count 2 2006.176.07:47:58.14#ibcon#about to write, iclass 5, count 2 2006.176.07:47:58.14#ibcon#wrote, iclass 5, count 2 2006.176.07:47:58.14#ibcon#about to read 3, iclass 5, count 2 2006.176.07:47:58.17#ibcon#read 3, iclass 5, count 2 2006.176.07:47:58.17#ibcon#about to read 4, iclass 5, count 2 2006.176.07:47:58.17#ibcon#read 4, iclass 5, count 2 2006.176.07:47:58.17#ibcon#about to read 5, iclass 5, count 2 2006.176.07:47:58.17#ibcon#read 5, iclass 5, count 2 2006.176.07:47:58.17#ibcon#about to read 6, iclass 5, count 2 2006.176.07:47:58.17#ibcon#read 6, iclass 5, count 2 2006.176.07:47:58.17#ibcon#end of sib2, iclass 5, count 2 2006.176.07:47:58.17#ibcon#*after write, iclass 5, count 2 2006.176.07:47:58.17#ibcon#*before return 0, iclass 5, count 2 2006.176.07:47:58.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:47:58.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:47:58.17#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.176.07:47:58.17#ibcon#ireg 7 cls_cnt 0 2006.176.07:47:58.17#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:47:58.29#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:47:58.29#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:47:58.29#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:47:58.29#ibcon#first serial, iclass 5, count 0 2006.176.07:47:58.29#ibcon#enter sib2, iclass 5, count 0 2006.176.07:47:58.29#ibcon#flushed, iclass 5, count 0 2006.176.07:47:58.29#ibcon#about to write, iclass 5, count 0 2006.176.07:47:58.29#ibcon#wrote, iclass 5, count 0 2006.176.07:47:58.29#ibcon#about to read 3, iclass 5, count 0 2006.176.07:47:58.31#ibcon#read 3, iclass 5, count 0 2006.176.07:47:58.31#ibcon#about to read 4, iclass 5, count 0 2006.176.07:47:58.31#ibcon#read 4, iclass 5, count 0 2006.176.07:47:58.31#ibcon#about to read 5, iclass 5, count 0 2006.176.07:47:58.31#ibcon#read 5, iclass 5, count 0 2006.176.07:47:58.31#ibcon#about to read 6, iclass 5, count 0 2006.176.07:47:58.31#ibcon#read 6, iclass 5, count 0 2006.176.07:47:58.31#ibcon#end of sib2, iclass 5, count 0 2006.176.07:47:58.31#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:47:58.31#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:47:58.31#ibcon#[25=USB\r\n] 2006.176.07:47:58.31#ibcon#*before write, iclass 5, count 0 2006.176.07:47:58.31#ibcon#enter sib2, iclass 5, count 0 2006.176.07:47:58.31#ibcon#flushed, iclass 5, count 0 2006.176.07:47:58.31#ibcon#about to write, iclass 5, count 0 2006.176.07:47:58.31#ibcon#wrote, iclass 5, count 0 2006.176.07:47:58.31#ibcon#about to read 3, iclass 5, count 0 2006.176.07:47:58.34#ibcon#read 3, iclass 5, count 0 2006.176.07:47:58.34#ibcon#about to read 4, iclass 5, count 0 2006.176.07:47:58.34#ibcon#read 4, iclass 5, count 0 2006.176.07:47:58.34#ibcon#about to read 5, iclass 5, count 0 2006.176.07:47:58.34#ibcon#read 5, iclass 5, count 0 2006.176.07:47:58.34#ibcon#about to read 6, iclass 5, count 0 2006.176.07:47:58.34#ibcon#read 6, iclass 5, count 0 2006.176.07:47:58.34#ibcon#end of sib2, iclass 5, count 0 2006.176.07:47:58.34#ibcon#*after write, iclass 5, count 0 2006.176.07:47:58.34#ibcon#*before return 0, iclass 5, count 0 2006.176.07:47:58.34#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:47:58.34#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:47:58.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:47:58.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:47:58.34$vc4f8/valo=2,572.99 2006.176.07:47:58.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.07:47:58.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.07:47:58.34#ibcon#ireg 17 cls_cnt 0 2006.176.07:47:58.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:47:58.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:47:58.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:47:58.34#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:47:58.34#ibcon#first serial, iclass 7, count 0 2006.176.07:47:58.34#ibcon#enter sib2, iclass 7, count 0 2006.176.07:47:58.34#ibcon#flushed, iclass 7, count 0 2006.176.07:47:58.34#ibcon#about to write, iclass 7, count 0 2006.176.07:47:58.34#ibcon#wrote, iclass 7, count 0 2006.176.07:47:58.34#ibcon#about to read 3, iclass 7, count 0 2006.176.07:47:58.36#ibcon#read 3, iclass 7, count 0 2006.176.07:47:58.36#ibcon#about to read 4, iclass 7, count 0 2006.176.07:47:58.36#ibcon#read 4, iclass 7, count 0 2006.176.07:47:58.36#ibcon#about to read 5, iclass 7, count 0 2006.176.07:47:58.36#ibcon#read 5, iclass 7, count 0 2006.176.07:47:58.36#ibcon#about to read 6, iclass 7, count 0 2006.176.07:47:58.36#ibcon#read 6, iclass 7, count 0 2006.176.07:47:58.36#ibcon#end of sib2, iclass 7, count 0 2006.176.07:47:58.36#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:47:58.36#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:47:58.36#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:47:58.36#ibcon#*before write, iclass 7, count 0 2006.176.07:47:58.36#ibcon#enter sib2, iclass 7, count 0 2006.176.07:47:58.36#ibcon#flushed, iclass 7, count 0 2006.176.07:47:58.36#ibcon#about to write, iclass 7, count 0 2006.176.07:47:58.36#ibcon#wrote, iclass 7, count 0 2006.176.07:47:58.36#ibcon#about to read 3, iclass 7, count 0 2006.176.07:47:58.40#ibcon#read 3, iclass 7, count 0 2006.176.07:47:58.40#ibcon#about to read 4, iclass 7, count 0 2006.176.07:47:58.40#ibcon#read 4, iclass 7, count 0 2006.176.07:47:58.40#ibcon#about to read 5, iclass 7, count 0 2006.176.07:47:58.40#ibcon#read 5, iclass 7, count 0 2006.176.07:47:58.40#ibcon#about to read 6, iclass 7, count 0 2006.176.07:47:58.40#ibcon#read 6, iclass 7, count 0 2006.176.07:47:58.40#ibcon#end of sib2, iclass 7, count 0 2006.176.07:47:58.40#ibcon#*after write, iclass 7, count 0 2006.176.07:47:58.40#ibcon#*before return 0, iclass 7, count 0 2006.176.07:47:58.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:47:58.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:47:58.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:47:58.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:47:58.40$vc4f8/va=2,7 2006.176.07:47:58.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.176.07:47:58.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.176.07:47:58.40#ibcon#ireg 11 cls_cnt 2 2006.176.07:47:58.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:47:58.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:47:58.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:47:58.46#ibcon#enter wrdev, iclass 11, count 2 2006.176.07:47:58.46#ibcon#first serial, iclass 11, count 2 2006.176.07:47:58.46#ibcon#enter sib2, iclass 11, count 2 2006.176.07:47:58.46#ibcon#flushed, iclass 11, count 2 2006.176.07:47:58.46#ibcon#about to write, iclass 11, count 2 2006.176.07:47:58.46#ibcon#wrote, iclass 11, count 2 2006.176.07:47:58.46#ibcon#about to read 3, iclass 11, count 2 2006.176.07:47:58.48#ibcon#read 3, iclass 11, count 2 2006.176.07:47:58.48#ibcon#about to read 4, iclass 11, count 2 2006.176.07:47:58.48#ibcon#read 4, iclass 11, count 2 2006.176.07:47:58.48#ibcon#about to read 5, iclass 11, count 2 2006.176.07:47:58.48#ibcon#read 5, iclass 11, count 2 2006.176.07:47:58.48#ibcon#about to read 6, iclass 11, count 2 2006.176.07:47:58.48#ibcon#read 6, iclass 11, count 2 2006.176.07:47:58.48#ibcon#end of sib2, iclass 11, count 2 2006.176.07:47:58.48#ibcon#*mode == 0, iclass 11, count 2 2006.176.07:47:58.48#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.176.07:47:58.48#ibcon#[25=AT02-07\r\n] 2006.176.07:47:58.48#ibcon#*before write, iclass 11, count 2 2006.176.07:47:58.48#ibcon#enter sib2, iclass 11, count 2 2006.176.07:47:58.48#ibcon#flushed, iclass 11, count 2 2006.176.07:47:58.48#ibcon#about to write, iclass 11, count 2 2006.176.07:47:58.48#ibcon#wrote, iclass 11, count 2 2006.176.07:47:58.48#ibcon#about to read 3, iclass 11, count 2 2006.176.07:47:58.51#ibcon#read 3, iclass 11, count 2 2006.176.07:47:58.51#ibcon#about to read 4, iclass 11, count 2 2006.176.07:47:58.51#ibcon#read 4, iclass 11, count 2 2006.176.07:47:58.51#ibcon#about to read 5, iclass 11, count 2 2006.176.07:47:58.51#ibcon#read 5, iclass 11, count 2 2006.176.07:47:58.51#ibcon#about to read 6, iclass 11, count 2 2006.176.07:47:58.51#ibcon#read 6, iclass 11, count 2 2006.176.07:47:58.51#ibcon#end of sib2, iclass 11, count 2 2006.176.07:47:58.51#ibcon#*after write, iclass 11, count 2 2006.176.07:47:58.51#ibcon#*before return 0, iclass 11, count 2 2006.176.07:47:58.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:47:58.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:47:58.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.176.07:47:58.51#ibcon#ireg 7 cls_cnt 0 2006.176.07:47:58.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:47:58.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:47:58.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:47:58.63#ibcon#enter wrdev, iclass 11, count 0 2006.176.07:47:58.63#ibcon#first serial, iclass 11, count 0 2006.176.07:47:58.63#ibcon#enter sib2, iclass 11, count 0 2006.176.07:47:58.63#ibcon#flushed, iclass 11, count 0 2006.176.07:47:58.63#ibcon#about to write, iclass 11, count 0 2006.176.07:47:58.63#ibcon#wrote, iclass 11, count 0 2006.176.07:47:58.63#ibcon#about to read 3, iclass 11, count 0 2006.176.07:47:58.65#ibcon#read 3, iclass 11, count 0 2006.176.07:47:58.65#ibcon#about to read 4, iclass 11, count 0 2006.176.07:47:58.65#ibcon#read 4, iclass 11, count 0 2006.176.07:47:58.65#ibcon#about to read 5, iclass 11, count 0 2006.176.07:47:58.65#ibcon#read 5, iclass 11, count 0 2006.176.07:47:58.65#ibcon#about to read 6, iclass 11, count 0 2006.176.07:47:58.65#ibcon#read 6, iclass 11, count 0 2006.176.07:47:58.65#ibcon#end of sib2, iclass 11, count 0 2006.176.07:47:58.65#ibcon#*mode == 0, iclass 11, count 0 2006.176.07:47:58.65#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.07:47:58.65#ibcon#[25=USB\r\n] 2006.176.07:47:58.65#ibcon#*before write, iclass 11, count 0 2006.176.07:47:58.65#ibcon#enter sib2, iclass 11, count 0 2006.176.07:47:58.65#ibcon#flushed, iclass 11, count 0 2006.176.07:47:58.65#ibcon#about to write, iclass 11, count 0 2006.176.07:47:58.65#ibcon#wrote, iclass 11, count 0 2006.176.07:47:58.65#ibcon#about to read 3, iclass 11, count 0 2006.176.07:47:58.68#ibcon#read 3, iclass 11, count 0 2006.176.07:47:58.68#ibcon#about to read 4, iclass 11, count 0 2006.176.07:47:58.68#ibcon#read 4, iclass 11, count 0 2006.176.07:47:58.68#ibcon#about to read 5, iclass 11, count 0 2006.176.07:47:58.68#ibcon#read 5, iclass 11, count 0 2006.176.07:47:58.68#ibcon#about to read 6, iclass 11, count 0 2006.176.07:47:58.68#ibcon#read 6, iclass 11, count 0 2006.176.07:47:58.68#ibcon#end of sib2, iclass 11, count 0 2006.176.07:47:58.68#ibcon#*after write, iclass 11, count 0 2006.176.07:47:58.68#ibcon#*before return 0, iclass 11, count 0 2006.176.07:47:58.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:47:58.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:47:58.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.07:47:58.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.07:47:58.68$vc4f8/valo=3,672.99 2006.176.07:47:58.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.07:47:58.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.07:47:58.68#ibcon#ireg 17 cls_cnt 0 2006.176.07:47:58.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:47:58.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:47:58.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:47:58.68#ibcon#enter wrdev, iclass 13, count 0 2006.176.07:47:58.68#ibcon#first serial, iclass 13, count 0 2006.176.07:47:58.68#ibcon#enter sib2, iclass 13, count 0 2006.176.07:47:58.68#ibcon#flushed, iclass 13, count 0 2006.176.07:47:58.68#ibcon#about to write, iclass 13, count 0 2006.176.07:47:58.68#ibcon#wrote, iclass 13, count 0 2006.176.07:47:58.68#ibcon#about to read 3, iclass 13, count 0 2006.176.07:47:58.70#ibcon#read 3, iclass 13, count 0 2006.176.07:47:58.70#ibcon#about to read 4, iclass 13, count 0 2006.176.07:47:58.70#ibcon#read 4, iclass 13, count 0 2006.176.07:47:58.70#ibcon#about to read 5, iclass 13, count 0 2006.176.07:47:58.70#ibcon#read 5, iclass 13, count 0 2006.176.07:47:58.70#ibcon#about to read 6, iclass 13, count 0 2006.176.07:47:58.70#ibcon#read 6, iclass 13, count 0 2006.176.07:47:58.70#ibcon#end of sib2, iclass 13, count 0 2006.176.07:47:58.70#ibcon#*mode == 0, iclass 13, count 0 2006.176.07:47:58.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.07:47:58.70#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:47:58.70#ibcon#*before write, iclass 13, count 0 2006.176.07:47:58.70#ibcon#enter sib2, iclass 13, count 0 2006.176.07:47:58.70#ibcon#flushed, iclass 13, count 0 2006.176.07:47:58.70#ibcon#about to write, iclass 13, count 0 2006.176.07:47:58.70#ibcon#wrote, iclass 13, count 0 2006.176.07:47:58.70#ibcon#about to read 3, iclass 13, count 0 2006.176.07:47:58.74#ibcon#read 3, iclass 13, count 0 2006.176.07:47:58.74#ibcon#about to read 4, iclass 13, count 0 2006.176.07:47:58.74#ibcon#read 4, iclass 13, count 0 2006.176.07:47:58.74#ibcon#about to read 5, iclass 13, count 0 2006.176.07:47:58.74#ibcon#read 5, iclass 13, count 0 2006.176.07:47:58.74#ibcon#about to read 6, iclass 13, count 0 2006.176.07:47:58.74#ibcon#read 6, iclass 13, count 0 2006.176.07:47:58.74#ibcon#end of sib2, iclass 13, count 0 2006.176.07:47:58.74#ibcon#*after write, iclass 13, count 0 2006.176.07:47:58.74#ibcon#*before return 0, iclass 13, count 0 2006.176.07:47:58.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:47:58.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:47:58.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.07:47:58.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.07:47:58.74$vc4f8/va=3,6 2006.176.07:47:58.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.176.07:47:58.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.176.07:47:58.74#ibcon#ireg 11 cls_cnt 2 2006.176.07:47:58.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:47:58.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:47:58.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:47:58.80#ibcon#enter wrdev, iclass 15, count 2 2006.176.07:47:58.80#ibcon#first serial, iclass 15, count 2 2006.176.07:47:58.80#ibcon#enter sib2, iclass 15, count 2 2006.176.07:47:58.80#ibcon#flushed, iclass 15, count 2 2006.176.07:47:58.80#ibcon#about to write, iclass 15, count 2 2006.176.07:47:58.80#ibcon#wrote, iclass 15, count 2 2006.176.07:47:58.80#ibcon#about to read 3, iclass 15, count 2 2006.176.07:47:58.82#ibcon#read 3, iclass 15, count 2 2006.176.07:47:58.82#ibcon#about to read 4, iclass 15, count 2 2006.176.07:47:58.82#ibcon#read 4, iclass 15, count 2 2006.176.07:47:58.82#ibcon#about to read 5, iclass 15, count 2 2006.176.07:47:58.82#ibcon#read 5, iclass 15, count 2 2006.176.07:47:58.82#ibcon#about to read 6, iclass 15, count 2 2006.176.07:47:58.82#ibcon#read 6, iclass 15, count 2 2006.176.07:47:58.82#ibcon#end of sib2, iclass 15, count 2 2006.176.07:47:58.82#ibcon#*mode == 0, iclass 15, count 2 2006.176.07:47:58.82#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.176.07:47:58.82#ibcon#[25=AT03-06\r\n] 2006.176.07:47:58.82#ibcon#*before write, iclass 15, count 2 2006.176.07:47:58.82#ibcon#enter sib2, iclass 15, count 2 2006.176.07:47:58.82#ibcon#flushed, iclass 15, count 2 2006.176.07:47:58.82#ibcon#about to write, iclass 15, count 2 2006.176.07:47:58.82#ibcon#wrote, iclass 15, count 2 2006.176.07:47:58.82#ibcon#about to read 3, iclass 15, count 2 2006.176.07:47:58.85#ibcon#read 3, iclass 15, count 2 2006.176.07:47:58.85#ibcon#about to read 4, iclass 15, count 2 2006.176.07:47:58.85#ibcon#read 4, iclass 15, count 2 2006.176.07:47:58.85#ibcon#about to read 5, iclass 15, count 2 2006.176.07:47:58.85#ibcon#read 5, iclass 15, count 2 2006.176.07:47:58.85#ibcon#about to read 6, iclass 15, count 2 2006.176.07:47:58.85#ibcon#read 6, iclass 15, count 2 2006.176.07:47:58.85#ibcon#end of sib2, iclass 15, count 2 2006.176.07:47:58.85#ibcon#*after write, iclass 15, count 2 2006.176.07:47:58.85#ibcon#*before return 0, iclass 15, count 2 2006.176.07:47:58.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:47:58.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:47:58.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.176.07:47:58.85#ibcon#ireg 7 cls_cnt 0 2006.176.07:47:58.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:47:58.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:47:58.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:47:58.97#ibcon#enter wrdev, iclass 15, count 0 2006.176.07:47:58.97#ibcon#first serial, iclass 15, count 0 2006.176.07:47:58.97#ibcon#enter sib2, iclass 15, count 0 2006.176.07:47:58.97#ibcon#flushed, iclass 15, count 0 2006.176.07:47:58.97#ibcon#about to write, iclass 15, count 0 2006.176.07:47:58.97#ibcon#wrote, iclass 15, count 0 2006.176.07:47:58.97#ibcon#about to read 3, iclass 15, count 0 2006.176.07:47:58.99#ibcon#read 3, iclass 15, count 0 2006.176.07:47:58.99#ibcon#about to read 4, iclass 15, count 0 2006.176.07:47:58.99#ibcon#read 4, iclass 15, count 0 2006.176.07:47:58.99#ibcon#about to read 5, iclass 15, count 0 2006.176.07:47:58.99#ibcon#read 5, iclass 15, count 0 2006.176.07:47:58.99#ibcon#about to read 6, iclass 15, count 0 2006.176.07:47:58.99#ibcon#read 6, iclass 15, count 0 2006.176.07:47:58.99#ibcon#end of sib2, iclass 15, count 0 2006.176.07:47:58.99#ibcon#*mode == 0, iclass 15, count 0 2006.176.07:47:58.99#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.07:47:58.99#ibcon#[25=USB\r\n] 2006.176.07:47:58.99#ibcon#*before write, iclass 15, count 0 2006.176.07:47:58.99#ibcon#enter sib2, iclass 15, count 0 2006.176.07:47:58.99#ibcon#flushed, iclass 15, count 0 2006.176.07:47:58.99#ibcon#about to write, iclass 15, count 0 2006.176.07:47:58.99#ibcon#wrote, iclass 15, count 0 2006.176.07:47:58.99#ibcon#about to read 3, iclass 15, count 0 2006.176.07:47:59.02#ibcon#read 3, iclass 15, count 0 2006.176.07:47:59.02#ibcon#about to read 4, iclass 15, count 0 2006.176.07:47:59.02#ibcon#read 4, iclass 15, count 0 2006.176.07:47:59.02#ibcon#about to read 5, iclass 15, count 0 2006.176.07:47:59.02#ibcon#read 5, iclass 15, count 0 2006.176.07:47:59.02#ibcon#about to read 6, iclass 15, count 0 2006.176.07:47:59.02#ibcon#read 6, iclass 15, count 0 2006.176.07:47:59.02#ibcon#end of sib2, iclass 15, count 0 2006.176.07:47:59.02#ibcon#*after write, iclass 15, count 0 2006.176.07:47:59.02#ibcon#*before return 0, iclass 15, count 0 2006.176.07:47:59.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:47:59.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:47:59.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.07:47:59.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.07:47:59.02$vc4f8/valo=4,832.99 2006.176.07:47:59.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.07:47:59.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.07:47:59.02#ibcon#ireg 17 cls_cnt 0 2006.176.07:47:59.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:47:59.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:47:59.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:47:59.02#ibcon#enter wrdev, iclass 17, count 0 2006.176.07:47:59.02#ibcon#first serial, iclass 17, count 0 2006.176.07:47:59.02#ibcon#enter sib2, iclass 17, count 0 2006.176.07:47:59.02#ibcon#flushed, iclass 17, count 0 2006.176.07:47:59.02#ibcon#about to write, iclass 17, count 0 2006.176.07:47:59.02#ibcon#wrote, iclass 17, count 0 2006.176.07:47:59.02#ibcon#about to read 3, iclass 17, count 0 2006.176.07:47:59.04#ibcon#read 3, iclass 17, count 0 2006.176.07:47:59.04#ibcon#about to read 4, iclass 17, count 0 2006.176.07:47:59.04#ibcon#read 4, iclass 17, count 0 2006.176.07:47:59.04#ibcon#about to read 5, iclass 17, count 0 2006.176.07:47:59.04#ibcon#read 5, iclass 17, count 0 2006.176.07:47:59.04#ibcon#about to read 6, iclass 17, count 0 2006.176.07:47:59.04#ibcon#read 6, iclass 17, count 0 2006.176.07:47:59.04#ibcon#end of sib2, iclass 17, count 0 2006.176.07:47:59.04#ibcon#*mode == 0, iclass 17, count 0 2006.176.07:47:59.04#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.07:47:59.04#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:47:59.04#ibcon#*before write, iclass 17, count 0 2006.176.07:47:59.04#ibcon#enter sib2, iclass 17, count 0 2006.176.07:47:59.04#ibcon#flushed, iclass 17, count 0 2006.176.07:47:59.04#ibcon#about to write, iclass 17, count 0 2006.176.07:47:59.04#ibcon#wrote, iclass 17, count 0 2006.176.07:47:59.04#ibcon#about to read 3, iclass 17, count 0 2006.176.07:47:59.08#ibcon#read 3, iclass 17, count 0 2006.176.07:47:59.08#ibcon#about to read 4, iclass 17, count 0 2006.176.07:47:59.08#ibcon#read 4, iclass 17, count 0 2006.176.07:47:59.08#ibcon#about to read 5, iclass 17, count 0 2006.176.07:47:59.08#ibcon#read 5, iclass 17, count 0 2006.176.07:47:59.08#ibcon#about to read 6, iclass 17, count 0 2006.176.07:47:59.08#ibcon#read 6, iclass 17, count 0 2006.176.07:47:59.08#ibcon#end of sib2, iclass 17, count 0 2006.176.07:47:59.08#ibcon#*after write, iclass 17, count 0 2006.176.07:47:59.08#ibcon#*before return 0, iclass 17, count 0 2006.176.07:47:59.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:47:59.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:47:59.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.07:47:59.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.07:47:59.08$vc4f8/va=4,7 2006.176.07:47:59.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.176.07:47:59.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.176.07:47:59.08#ibcon#ireg 11 cls_cnt 2 2006.176.07:47:59.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:47:59.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:47:59.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:47:59.14#ibcon#enter wrdev, iclass 19, count 2 2006.176.07:47:59.14#ibcon#first serial, iclass 19, count 2 2006.176.07:47:59.14#ibcon#enter sib2, iclass 19, count 2 2006.176.07:47:59.14#ibcon#flushed, iclass 19, count 2 2006.176.07:47:59.14#ibcon#about to write, iclass 19, count 2 2006.176.07:47:59.14#ibcon#wrote, iclass 19, count 2 2006.176.07:47:59.14#ibcon#about to read 3, iclass 19, count 2 2006.176.07:47:59.16#ibcon#read 3, iclass 19, count 2 2006.176.07:47:59.16#ibcon#about to read 4, iclass 19, count 2 2006.176.07:47:59.16#ibcon#read 4, iclass 19, count 2 2006.176.07:47:59.16#ibcon#about to read 5, iclass 19, count 2 2006.176.07:47:59.16#ibcon#read 5, iclass 19, count 2 2006.176.07:47:59.16#ibcon#about to read 6, iclass 19, count 2 2006.176.07:47:59.16#ibcon#read 6, iclass 19, count 2 2006.176.07:47:59.16#ibcon#end of sib2, iclass 19, count 2 2006.176.07:47:59.16#ibcon#*mode == 0, iclass 19, count 2 2006.176.07:47:59.16#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.176.07:47:59.16#ibcon#[25=AT04-07\r\n] 2006.176.07:47:59.16#ibcon#*before write, iclass 19, count 2 2006.176.07:47:59.16#ibcon#enter sib2, iclass 19, count 2 2006.176.07:47:59.16#ibcon#flushed, iclass 19, count 2 2006.176.07:47:59.16#ibcon#about to write, iclass 19, count 2 2006.176.07:47:59.16#ibcon#wrote, iclass 19, count 2 2006.176.07:47:59.16#ibcon#about to read 3, iclass 19, count 2 2006.176.07:47:59.19#ibcon#read 3, iclass 19, count 2 2006.176.07:47:59.19#ibcon#about to read 4, iclass 19, count 2 2006.176.07:47:59.19#ibcon#read 4, iclass 19, count 2 2006.176.07:47:59.19#ibcon#about to read 5, iclass 19, count 2 2006.176.07:47:59.19#ibcon#read 5, iclass 19, count 2 2006.176.07:47:59.19#ibcon#about to read 6, iclass 19, count 2 2006.176.07:47:59.19#ibcon#read 6, iclass 19, count 2 2006.176.07:47:59.19#ibcon#end of sib2, iclass 19, count 2 2006.176.07:47:59.19#ibcon#*after write, iclass 19, count 2 2006.176.07:47:59.19#ibcon#*before return 0, iclass 19, count 2 2006.176.07:47:59.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:47:59.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:47:59.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.176.07:47:59.19#ibcon#ireg 7 cls_cnt 0 2006.176.07:47:59.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:47:59.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:47:59.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:47:59.31#ibcon#enter wrdev, iclass 19, count 0 2006.176.07:47:59.31#ibcon#first serial, iclass 19, count 0 2006.176.07:47:59.31#ibcon#enter sib2, iclass 19, count 0 2006.176.07:47:59.31#ibcon#flushed, iclass 19, count 0 2006.176.07:47:59.31#ibcon#about to write, iclass 19, count 0 2006.176.07:47:59.31#ibcon#wrote, iclass 19, count 0 2006.176.07:47:59.31#ibcon#about to read 3, iclass 19, count 0 2006.176.07:47:59.33#ibcon#read 3, iclass 19, count 0 2006.176.07:47:59.33#ibcon#about to read 4, iclass 19, count 0 2006.176.07:47:59.33#ibcon#read 4, iclass 19, count 0 2006.176.07:47:59.33#ibcon#about to read 5, iclass 19, count 0 2006.176.07:47:59.33#ibcon#read 5, iclass 19, count 0 2006.176.07:47:59.33#ibcon#about to read 6, iclass 19, count 0 2006.176.07:47:59.33#ibcon#read 6, iclass 19, count 0 2006.176.07:47:59.33#ibcon#end of sib2, iclass 19, count 0 2006.176.07:47:59.33#ibcon#*mode == 0, iclass 19, count 0 2006.176.07:47:59.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.07:47:59.33#ibcon#[25=USB\r\n] 2006.176.07:47:59.33#ibcon#*before write, iclass 19, count 0 2006.176.07:47:59.33#ibcon#enter sib2, iclass 19, count 0 2006.176.07:47:59.33#ibcon#flushed, iclass 19, count 0 2006.176.07:47:59.33#ibcon#about to write, iclass 19, count 0 2006.176.07:47:59.33#ibcon#wrote, iclass 19, count 0 2006.176.07:47:59.33#ibcon#about to read 3, iclass 19, count 0 2006.176.07:47:59.36#ibcon#read 3, iclass 19, count 0 2006.176.07:47:59.36#ibcon#about to read 4, iclass 19, count 0 2006.176.07:47:59.36#ibcon#read 4, iclass 19, count 0 2006.176.07:47:59.36#ibcon#about to read 5, iclass 19, count 0 2006.176.07:47:59.36#ibcon#read 5, iclass 19, count 0 2006.176.07:47:59.36#ibcon#about to read 6, iclass 19, count 0 2006.176.07:47:59.36#ibcon#read 6, iclass 19, count 0 2006.176.07:47:59.36#ibcon#end of sib2, iclass 19, count 0 2006.176.07:47:59.36#ibcon#*after write, iclass 19, count 0 2006.176.07:47:59.36#ibcon#*before return 0, iclass 19, count 0 2006.176.07:47:59.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:47:59.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:47:59.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.07:47:59.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.07:47:59.36$vc4f8/valo=5,652.99 2006.176.07:47:59.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.07:47:59.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.07:47:59.36#ibcon#ireg 17 cls_cnt 0 2006.176.07:47:59.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:47:59.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:47:59.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:47:59.36#ibcon#enter wrdev, iclass 21, count 0 2006.176.07:47:59.36#ibcon#first serial, iclass 21, count 0 2006.176.07:47:59.36#ibcon#enter sib2, iclass 21, count 0 2006.176.07:47:59.36#ibcon#flushed, iclass 21, count 0 2006.176.07:47:59.36#ibcon#about to write, iclass 21, count 0 2006.176.07:47:59.36#ibcon#wrote, iclass 21, count 0 2006.176.07:47:59.36#ibcon#about to read 3, iclass 21, count 0 2006.176.07:47:59.38#ibcon#read 3, iclass 21, count 0 2006.176.07:47:59.38#ibcon#about to read 4, iclass 21, count 0 2006.176.07:47:59.38#ibcon#read 4, iclass 21, count 0 2006.176.07:47:59.38#ibcon#about to read 5, iclass 21, count 0 2006.176.07:47:59.38#ibcon#read 5, iclass 21, count 0 2006.176.07:47:59.38#ibcon#about to read 6, iclass 21, count 0 2006.176.07:47:59.38#ibcon#read 6, iclass 21, count 0 2006.176.07:47:59.38#ibcon#end of sib2, iclass 21, count 0 2006.176.07:47:59.38#ibcon#*mode == 0, iclass 21, count 0 2006.176.07:47:59.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.07:47:59.38#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:47:59.38#ibcon#*before write, iclass 21, count 0 2006.176.07:47:59.38#ibcon#enter sib2, iclass 21, count 0 2006.176.07:47:59.38#ibcon#flushed, iclass 21, count 0 2006.176.07:47:59.38#ibcon#about to write, iclass 21, count 0 2006.176.07:47:59.38#ibcon#wrote, iclass 21, count 0 2006.176.07:47:59.38#ibcon#about to read 3, iclass 21, count 0 2006.176.07:47:59.42#ibcon#read 3, iclass 21, count 0 2006.176.07:47:59.42#ibcon#about to read 4, iclass 21, count 0 2006.176.07:47:59.42#ibcon#read 4, iclass 21, count 0 2006.176.07:47:59.42#ibcon#about to read 5, iclass 21, count 0 2006.176.07:47:59.42#ibcon#read 5, iclass 21, count 0 2006.176.07:47:59.42#ibcon#about to read 6, iclass 21, count 0 2006.176.07:47:59.42#ibcon#read 6, iclass 21, count 0 2006.176.07:47:59.42#ibcon#end of sib2, iclass 21, count 0 2006.176.07:47:59.42#ibcon#*after write, iclass 21, count 0 2006.176.07:47:59.42#ibcon#*before return 0, iclass 21, count 0 2006.176.07:47:59.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:47:59.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:47:59.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.07:47:59.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.07:47:59.42$vc4f8/va=5,7 2006.176.07:47:59.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.07:47:59.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.07:47:59.42#ibcon#ireg 11 cls_cnt 2 2006.176.07:47:59.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:47:59.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:47:59.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:47:59.48#ibcon#enter wrdev, iclass 23, count 2 2006.176.07:47:59.48#ibcon#first serial, iclass 23, count 2 2006.176.07:47:59.48#ibcon#enter sib2, iclass 23, count 2 2006.176.07:47:59.48#ibcon#flushed, iclass 23, count 2 2006.176.07:47:59.48#ibcon#about to write, iclass 23, count 2 2006.176.07:47:59.48#ibcon#wrote, iclass 23, count 2 2006.176.07:47:59.48#ibcon#about to read 3, iclass 23, count 2 2006.176.07:47:59.50#ibcon#read 3, iclass 23, count 2 2006.176.07:47:59.50#ibcon#about to read 4, iclass 23, count 2 2006.176.07:47:59.50#ibcon#read 4, iclass 23, count 2 2006.176.07:47:59.50#ibcon#about to read 5, iclass 23, count 2 2006.176.07:47:59.50#ibcon#read 5, iclass 23, count 2 2006.176.07:47:59.50#ibcon#about to read 6, iclass 23, count 2 2006.176.07:47:59.50#ibcon#read 6, iclass 23, count 2 2006.176.07:47:59.50#ibcon#end of sib2, iclass 23, count 2 2006.176.07:47:59.50#ibcon#*mode == 0, iclass 23, count 2 2006.176.07:47:59.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.07:47:59.50#ibcon#[25=AT05-07\r\n] 2006.176.07:47:59.50#ibcon#*before write, iclass 23, count 2 2006.176.07:47:59.50#ibcon#enter sib2, iclass 23, count 2 2006.176.07:47:59.50#ibcon#flushed, iclass 23, count 2 2006.176.07:47:59.50#ibcon#about to write, iclass 23, count 2 2006.176.07:47:59.50#ibcon#wrote, iclass 23, count 2 2006.176.07:47:59.50#ibcon#about to read 3, iclass 23, count 2 2006.176.07:47:59.53#ibcon#read 3, iclass 23, count 2 2006.176.07:47:59.53#ibcon#about to read 4, iclass 23, count 2 2006.176.07:47:59.53#ibcon#read 4, iclass 23, count 2 2006.176.07:47:59.53#ibcon#about to read 5, iclass 23, count 2 2006.176.07:47:59.53#ibcon#read 5, iclass 23, count 2 2006.176.07:47:59.53#ibcon#about to read 6, iclass 23, count 2 2006.176.07:47:59.53#ibcon#read 6, iclass 23, count 2 2006.176.07:47:59.53#ibcon#end of sib2, iclass 23, count 2 2006.176.07:47:59.53#ibcon#*after write, iclass 23, count 2 2006.176.07:47:59.53#ibcon#*before return 0, iclass 23, count 2 2006.176.07:47:59.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:47:59.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:47:59.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.07:47:59.53#ibcon#ireg 7 cls_cnt 0 2006.176.07:47:59.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:47:59.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:47:59.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:47:59.65#ibcon#enter wrdev, iclass 23, count 0 2006.176.07:47:59.65#ibcon#first serial, iclass 23, count 0 2006.176.07:47:59.65#ibcon#enter sib2, iclass 23, count 0 2006.176.07:47:59.65#ibcon#flushed, iclass 23, count 0 2006.176.07:47:59.65#ibcon#about to write, iclass 23, count 0 2006.176.07:47:59.65#ibcon#wrote, iclass 23, count 0 2006.176.07:47:59.65#ibcon#about to read 3, iclass 23, count 0 2006.176.07:47:59.67#ibcon#read 3, iclass 23, count 0 2006.176.07:47:59.67#ibcon#about to read 4, iclass 23, count 0 2006.176.07:47:59.67#ibcon#read 4, iclass 23, count 0 2006.176.07:47:59.67#ibcon#about to read 5, iclass 23, count 0 2006.176.07:47:59.67#ibcon#read 5, iclass 23, count 0 2006.176.07:47:59.67#ibcon#about to read 6, iclass 23, count 0 2006.176.07:47:59.67#ibcon#read 6, iclass 23, count 0 2006.176.07:47:59.67#ibcon#end of sib2, iclass 23, count 0 2006.176.07:47:59.67#ibcon#*mode == 0, iclass 23, count 0 2006.176.07:47:59.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.07:47:59.67#ibcon#[25=USB\r\n] 2006.176.07:47:59.67#ibcon#*before write, iclass 23, count 0 2006.176.07:47:59.67#ibcon#enter sib2, iclass 23, count 0 2006.176.07:47:59.67#ibcon#flushed, iclass 23, count 0 2006.176.07:47:59.67#ibcon#about to write, iclass 23, count 0 2006.176.07:47:59.67#ibcon#wrote, iclass 23, count 0 2006.176.07:47:59.67#ibcon#about to read 3, iclass 23, count 0 2006.176.07:47:59.70#ibcon#read 3, iclass 23, count 0 2006.176.07:47:59.70#ibcon#about to read 4, iclass 23, count 0 2006.176.07:47:59.70#ibcon#read 4, iclass 23, count 0 2006.176.07:47:59.70#ibcon#about to read 5, iclass 23, count 0 2006.176.07:47:59.70#ibcon#read 5, iclass 23, count 0 2006.176.07:47:59.70#ibcon#about to read 6, iclass 23, count 0 2006.176.07:47:59.70#ibcon#read 6, iclass 23, count 0 2006.176.07:47:59.70#ibcon#end of sib2, iclass 23, count 0 2006.176.07:47:59.70#ibcon#*after write, iclass 23, count 0 2006.176.07:47:59.70#ibcon#*before return 0, iclass 23, count 0 2006.176.07:47:59.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:47:59.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:47:59.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.07:47:59.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.07:47:59.70$vc4f8/valo=6,772.99 2006.176.07:47:59.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.07:47:59.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.07:47:59.70#ibcon#ireg 17 cls_cnt 0 2006.176.07:47:59.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:47:59.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:47:59.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:47:59.70#ibcon#enter wrdev, iclass 25, count 0 2006.176.07:47:59.70#ibcon#first serial, iclass 25, count 0 2006.176.07:47:59.70#ibcon#enter sib2, iclass 25, count 0 2006.176.07:47:59.70#ibcon#flushed, iclass 25, count 0 2006.176.07:47:59.70#ibcon#about to write, iclass 25, count 0 2006.176.07:47:59.70#ibcon#wrote, iclass 25, count 0 2006.176.07:47:59.70#ibcon#about to read 3, iclass 25, count 0 2006.176.07:47:59.72#ibcon#read 3, iclass 25, count 0 2006.176.07:47:59.72#ibcon#about to read 4, iclass 25, count 0 2006.176.07:47:59.72#ibcon#read 4, iclass 25, count 0 2006.176.07:47:59.72#ibcon#about to read 5, iclass 25, count 0 2006.176.07:47:59.72#ibcon#read 5, iclass 25, count 0 2006.176.07:47:59.72#ibcon#about to read 6, iclass 25, count 0 2006.176.07:47:59.72#ibcon#read 6, iclass 25, count 0 2006.176.07:47:59.72#ibcon#end of sib2, iclass 25, count 0 2006.176.07:47:59.72#ibcon#*mode == 0, iclass 25, count 0 2006.176.07:47:59.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.07:47:59.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:47:59.72#ibcon#*before write, iclass 25, count 0 2006.176.07:47:59.72#ibcon#enter sib2, iclass 25, count 0 2006.176.07:47:59.72#ibcon#flushed, iclass 25, count 0 2006.176.07:47:59.72#ibcon#about to write, iclass 25, count 0 2006.176.07:47:59.72#ibcon#wrote, iclass 25, count 0 2006.176.07:47:59.72#ibcon#about to read 3, iclass 25, count 0 2006.176.07:47:59.76#ibcon#read 3, iclass 25, count 0 2006.176.07:47:59.76#ibcon#about to read 4, iclass 25, count 0 2006.176.07:47:59.76#ibcon#read 4, iclass 25, count 0 2006.176.07:47:59.76#ibcon#about to read 5, iclass 25, count 0 2006.176.07:47:59.76#ibcon#read 5, iclass 25, count 0 2006.176.07:47:59.76#ibcon#about to read 6, iclass 25, count 0 2006.176.07:47:59.76#ibcon#read 6, iclass 25, count 0 2006.176.07:47:59.76#ibcon#end of sib2, iclass 25, count 0 2006.176.07:47:59.76#ibcon#*after write, iclass 25, count 0 2006.176.07:47:59.76#ibcon#*before return 0, iclass 25, count 0 2006.176.07:47:59.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:47:59.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:47:59.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.07:47:59.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.07:47:59.76$vc4f8/va=6,6 2006.176.07:47:59.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.07:47:59.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.07:47:59.76#ibcon#ireg 11 cls_cnt 2 2006.176.07:47:59.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:47:59.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:47:59.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:47:59.82#ibcon#enter wrdev, iclass 27, count 2 2006.176.07:47:59.82#ibcon#first serial, iclass 27, count 2 2006.176.07:47:59.82#ibcon#enter sib2, iclass 27, count 2 2006.176.07:47:59.82#ibcon#flushed, iclass 27, count 2 2006.176.07:47:59.82#ibcon#about to write, iclass 27, count 2 2006.176.07:47:59.82#ibcon#wrote, iclass 27, count 2 2006.176.07:47:59.82#ibcon#about to read 3, iclass 27, count 2 2006.176.07:47:59.84#ibcon#read 3, iclass 27, count 2 2006.176.07:47:59.84#ibcon#about to read 4, iclass 27, count 2 2006.176.07:47:59.84#ibcon#read 4, iclass 27, count 2 2006.176.07:47:59.84#ibcon#about to read 5, iclass 27, count 2 2006.176.07:47:59.84#ibcon#read 5, iclass 27, count 2 2006.176.07:47:59.84#ibcon#about to read 6, iclass 27, count 2 2006.176.07:47:59.84#ibcon#read 6, iclass 27, count 2 2006.176.07:47:59.84#ibcon#end of sib2, iclass 27, count 2 2006.176.07:47:59.84#ibcon#*mode == 0, iclass 27, count 2 2006.176.07:47:59.84#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.07:47:59.84#ibcon#[25=AT06-06\r\n] 2006.176.07:47:59.84#ibcon#*before write, iclass 27, count 2 2006.176.07:47:59.84#ibcon#enter sib2, iclass 27, count 2 2006.176.07:47:59.84#ibcon#flushed, iclass 27, count 2 2006.176.07:47:59.84#ibcon#about to write, iclass 27, count 2 2006.176.07:47:59.84#ibcon#wrote, iclass 27, count 2 2006.176.07:47:59.84#ibcon#about to read 3, iclass 27, count 2 2006.176.07:47:59.87#ibcon#read 3, iclass 27, count 2 2006.176.07:47:59.87#ibcon#about to read 4, iclass 27, count 2 2006.176.07:47:59.87#ibcon#read 4, iclass 27, count 2 2006.176.07:47:59.87#ibcon#about to read 5, iclass 27, count 2 2006.176.07:47:59.87#ibcon#read 5, iclass 27, count 2 2006.176.07:47:59.87#ibcon#about to read 6, iclass 27, count 2 2006.176.07:47:59.87#ibcon#read 6, iclass 27, count 2 2006.176.07:47:59.87#ibcon#end of sib2, iclass 27, count 2 2006.176.07:47:59.87#ibcon#*after write, iclass 27, count 2 2006.176.07:47:59.87#ibcon#*before return 0, iclass 27, count 2 2006.176.07:47:59.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:47:59.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:47:59.87#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.07:47:59.87#ibcon#ireg 7 cls_cnt 0 2006.176.07:47:59.87#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:47:59.99#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:47:59.99#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:47:59.99#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:47:59.99#ibcon#first serial, iclass 27, count 0 2006.176.07:47:59.99#ibcon#enter sib2, iclass 27, count 0 2006.176.07:47:59.99#ibcon#flushed, iclass 27, count 0 2006.176.07:47:59.99#ibcon#about to write, iclass 27, count 0 2006.176.07:47:59.99#ibcon#wrote, iclass 27, count 0 2006.176.07:47:59.99#ibcon#about to read 3, iclass 27, count 0 2006.176.07:48:00.01#ibcon#read 3, iclass 27, count 0 2006.176.07:48:00.01#ibcon#about to read 4, iclass 27, count 0 2006.176.07:48:00.01#ibcon#read 4, iclass 27, count 0 2006.176.07:48:00.01#ibcon#about to read 5, iclass 27, count 0 2006.176.07:48:00.01#ibcon#read 5, iclass 27, count 0 2006.176.07:48:00.01#ibcon#about to read 6, iclass 27, count 0 2006.176.07:48:00.01#ibcon#read 6, iclass 27, count 0 2006.176.07:48:00.01#ibcon#end of sib2, iclass 27, count 0 2006.176.07:48:00.01#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:48:00.01#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:48:00.01#ibcon#[25=USB\r\n] 2006.176.07:48:00.01#ibcon#*before write, iclass 27, count 0 2006.176.07:48:00.01#ibcon#enter sib2, iclass 27, count 0 2006.176.07:48:00.01#ibcon#flushed, iclass 27, count 0 2006.176.07:48:00.01#ibcon#about to write, iclass 27, count 0 2006.176.07:48:00.01#ibcon#wrote, iclass 27, count 0 2006.176.07:48:00.01#ibcon#about to read 3, iclass 27, count 0 2006.176.07:48:00.04#ibcon#read 3, iclass 27, count 0 2006.176.07:48:00.04#ibcon#about to read 4, iclass 27, count 0 2006.176.07:48:00.04#ibcon#read 4, iclass 27, count 0 2006.176.07:48:00.04#ibcon#about to read 5, iclass 27, count 0 2006.176.07:48:00.04#ibcon#read 5, iclass 27, count 0 2006.176.07:48:00.04#ibcon#about to read 6, iclass 27, count 0 2006.176.07:48:00.04#ibcon#read 6, iclass 27, count 0 2006.176.07:48:00.04#ibcon#end of sib2, iclass 27, count 0 2006.176.07:48:00.04#ibcon#*after write, iclass 27, count 0 2006.176.07:48:00.04#ibcon#*before return 0, iclass 27, count 0 2006.176.07:48:00.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:48:00.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:48:00.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:48:00.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:48:00.04$vc4f8/valo=7,832.99 2006.176.07:48:00.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.07:48:00.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.07:48:00.04#ibcon#ireg 17 cls_cnt 0 2006.176.07:48:00.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:48:00.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:48:00.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:48:00.04#ibcon#enter wrdev, iclass 29, count 0 2006.176.07:48:00.04#ibcon#first serial, iclass 29, count 0 2006.176.07:48:00.04#ibcon#enter sib2, iclass 29, count 0 2006.176.07:48:00.04#ibcon#flushed, iclass 29, count 0 2006.176.07:48:00.04#ibcon#about to write, iclass 29, count 0 2006.176.07:48:00.04#ibcon#wrote, iclass 29, count 0 2006.176.07:48:00.04#ibcon#about to read 3, iclass 29, count 0 2006.176.07:48:00.06#ibcon#read 3, iclass 29, count 0 2006.176.07:48:00.06#ibcon#about to read 4, iclass 29, count 0 2006.176.07:48:00.06#ibcon#read 4, iclass 29, count 0 2006.176.07:48:00.06#ibcon#about to read 5, iclass 29, count 0 2006.176.07:48:00.06#ibcon#read 5, iclass 29, count 0 2006.176.07:48:00.06#ibcon#about to read 6, iclass 29, count 0 2006.176.07:48:00.06#ibcon#read 6, iclass 29, count 0 2006.176.07:48:00.06#ibcon#end of sib2, iclass 29, count 0 2006.176.07:48:00.06#ibcon#*mode == 0, iclass 29, count 0 2006.176.07:48:00.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.07:48:00.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:48:00.06#ibcon#*before write, iclass 29, count 0 2006.176.07:48:00.06#ibcon#enter sib2, iclass 29, count 0 2006.176.07:48:00.06#ibcon#flushed, iclass 29, count 0 2006.176.07:48:00.06#ibcon#about to write, iclass 29, count 0 2006.176.07:48:00.06#ibcon#wrote, iclass 29, count 0 2006.176.07:48:00.06#ibcon#about to read 3, iclass 29, count 0 2006.176.07:48:00.10#ibcon#read 3, iclass 29, count 0 2006.176.07:48:00.10#ibcon#about to read 4, iclass 29, count 0 2006.176.07:48:00.10#ibcon#read 4, iclass 29, count 0 2006.176.07:48:00.10#ibcon#about to read 5, iclass 29, count 0 2006.176.07:48:00.10#ibcon#read 5, iclass 29, count 0 2006.176.07:48:00.10#ibcon#about to read 6, iclass 29, count 0 2006.176.07:48:00.10#ibcon#read 6, iclass 29, count 0 2006.176.07:48:00.10#ibcon#end of sib2, iclass 29, count 0 2006.176.07:48:00.10#ibcon#*after write, iclass 29, count 0 2006.176.07:48:00.10#ibcon#*before return 0, iclass 29, count 0 2006.176.07:48:00.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:48:00.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.07:48:00.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.07:48:00.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.07:48:00.10$vc4f8/va=7,6 2006.176.07:48:00.10#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.07:48:00.10#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.07:48:00.10#ibcon#ireg 11 cls_cnt 2 2006.176.07:48:00.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:48:00.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:48:00.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:48:00.16#ibcon#enter wrdev, iclass 31, count 2 2006.176.07:48:00.16#ibcon#first serial, iclass 31, count 2 2006.176.07:48:00.16#ibcon#enter sib2, iclass 31, count 2 2006.176.07:48:00.16#ibcon#flushed, iclass 31, count 2 2006.176.07:48:00.16#ibcon#about to write, iclass 31, count 2 2006.176.07:48:00.16#ibcon#wrote, iclass 31, count 2 2006.176.07:48:00.16#ibcon#about to read 3, iclass 31, count 2 2006.176.07:48:00.18#ibcon#read 3, iclass 31, count 2 2006.176.07:48:00.18#ibcon#about to read 4, iclass 31, count 2 2006.176.07:48:00.18#ibcon#read 4, iclass 31, count 2 2006.176.07:48:00.18#ibcon#about to read 5, iclass 31, count 2 2006.176.07:48:00.18#ibcon#read 5, iclass 31, count 2 2006.176.07:48:00.18#ibcon#about to read 6, iclass 31, count 2 2006.176.07:48:00.18#ibcon#read 6, iclass 31, count 2 2006.176.07:48:00.18#ibcon#end of sib2, iclass 31, count 2 2006.176.07:48:00.18#ibcon#*mode == 0, iclass 31, count 2 2006.176.07:48:00.18#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.07:48:00.18#ibcon#[25=AT07-06\r\n] 2006.176.07:48:00.18#ibcon#*before write, iclass 31, count 2 2006.176.07:48:00.18#ibcon#enter sib2, iclass 31, count 2 2006.176.07:48:00.18#ibcon#flushed, iclass 31, count 2 2006.176.07:48:00.18#ibcon#about to write, iclass 31, count 2 2006.176.07:48:00.18#ibcon#wrote, iclass 31, count 2 2006.176.07:48:00.18#ibcon#about to read 3, iclass 31, count 2 2006.176.07:48:00.22#ibcon#read 3, iclass 31, count 2 2006.176.07:48:00.22#ibcon#about to read 4, iclass 31, count 2 2006.176.07:48:00.22#ibcon#read 4, iclass 31, count 2 2006.176.07:48:00.22#ibcon#about to read 5, iclass 31, count 2 2006.176.07:48:00.22#ibcon#read 5, iclass 31, count 2 2006.176.07:48:00.22#ibcon#about to read 6, iclass 31, count 2 2006.176.07:48:00.22#ibcon#read 6, iclass 31, count 2 2006.176.07:48:00.22#ibcon#end of sib2, iclass 31, count 2 2006.176.07:48:00.22#ibcon#*after write, iclass 31, count 2 2006.176.07:48:00.22#ibcon#*before return 0, iclass 31, count 2 2006.176.07:48:00.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:48:00.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.07:48:00.22#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.07:48:00.22#ibcon#ireg 7 cls_cnt 0 2006.176.07:48:00.22#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:48:00.34#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:48:00.34#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:48:00.34#ibcon#enter wrdev, iclass 31, count 0 2006.176.07:48:00.34#ibcon#first serial, iclass 31, count 0 2006.176.07:48:00.34#ibcon#enter sib2, iclass 31, count 0 2006.176.07:48:00.34#ibcon#flushed, iclass 31, count 0 2006.176.07:48:00.34#ibcon#about to write, iclass 31, count 0 2006.176.07:48:00.34#ibcon#wrote, iclass 31, count 0 2006.176.07:48:00.34#ibcon#about to read 3, iclass 31, count 0 2006.176.07:48:00.36#ibcon#read 3, iclass 31, count 0 2006.176.07:48:00.36#ibcon#about to read 4, iclass 31, count 0 2006.176.07:48:00.36#ibcon#read 4, iclass 31, count 0 2006.176.07:48:00.36#ibcon#about to read 5, iclass 31, count 0 2006.176.07:48:00.36#ibcon#read 5, iclass 31, count 0 2006.176.07:48:00.36#ibcon#about to read 6, iclass 31, count 0 2006.176.07:48:00.36#ibcon#read 6, iclass 31, count 0 2006.176.07:48:00.36#ibcon#end of sib2, iclass 31, count 0 2006.176.07:48:00.36#ibcon#*mode == 0, iclass 31, count 0 2006.176.07:48:00.36#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.07:48:00.36#ibcon#[25=USB\r\n] 2006.176.07:48:00.36#ibcon#*before write, iclass 31, count 0 2006.176.07:48:00.36#ibcon#enter sib2, iclass 31, count 0 2006.176.07:48:00.36#ibcon#flushed, iclass 31, count 0 2006.176.07:48:00.36#ibcon#about to write, iclass 31, count 0 2006.176.07:48:00.36#ibcon#wrote, iclass 31, count 0 2006.176.07:48:00.36#ibcon#about to read 3, iclass 31, count 0 2006.176.07:48:00.39#ibcon#read 3, iclass 31, count 0 2006.176.07:48:00.39#ibcon#about to read 4, iclass 31, count 0 2006.176.07:48:00.39#ibcon#read 4, iclass 31, count 0 2006.176.07:48:00.39#ibcon#about to read 5, iclass 31, count 0 2006.176.07:48:00.39#ibcon#read 5, iclass 31, count 0 2006.176.07:48:00.39#ibcon#about to read 6, iclass 31, count 0 2006.176.07:48:00.39#ibcon#read 6, iclass 31, count 0 2006.176.07:48:00.39#ibcon#end of sib2, iclass 31, count 0 2006.176.07:48:00.39#ibcon#*after write, iclass 31, count 0 2006.176.07:48:00.39#ibcon#*before return 0, iclass 31, count 0 2006.176.07:48:00.39#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:48:00.39#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.07:48:00.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.07:48:00.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.07:48:00.39$vc4f8/valo=8,852.99 2006.176.07:48:00.39#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.07:48:00.39#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.07:48:00.39#ibcon#ireg 17 cls_cnt 0 2006.176.07:48:00.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:48:00.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:48:00.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:48:00.39#ibcon#enter wrdev, iclass 33, count 0 2006.176.07:48:00.39#ibcon#first serial, iclass 33, count 0 2006.176.07:48:00.39#ibcon#enter sib2, iclass 33, count 0 2006.176.07:48:00.39#ibcon#flushed, iclass 33, count 0 2006.176.07:48:00.39#ibcon#about to write, iclass 33, count 0 2006.176.07:48:00.39#ibcon#wrote, iclass 33, count 0 2006.176.07:48:00.39#ibcon#about to read 3, iclass 33, count 0 2006.176.07:48:00.41#ibcon#read 3, iclass 33, count 0 2006.176.07:48:00.41#ibcon#about to read 4, iclass 33, count 0 2006.176.07:48:00.41#ibcon#read 4, iclass 33, count 0 2006.176.07:48:00.41#ibcon#about to read 5, iclass 33, count 0 2006.176.07:48:00.41#ibcon#read 5, iclass 33, count 0 2006.176.07:48:00.41#ibcon#about to read 6, iclass 33, count 0 2006.176.07:48:00.41#ibcon#read 6, iclass 33, count 0 2006.176.07:48:00.41#ibcon#end of sib2, iclass 33, count 0 2006.176.07:48:00.41#ibcon#*mode == 0, iclass 33, count 0 2006.176.07:48:00.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.07:48:00.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:48:00.41#ibcon#*before write, iclass 33, count 0 2006.176.07:48:00.41#ibcon#enter sib2, iclass 33, count 0 2006.176.07:48:00.41#ibcon#flushed, iclass 33, count 0 2006.176.07:48:00.41#ibcon#about to write, iclass 33, count 0 2006.176.07:48:00.41#ibcon#wrote, iclass 33, count 0 2006.176.07:48:00.41#ibcon#about to read 3, iclass 33, count 0 2006.176.07:48:00.45#ibcon#read 3, iclass 33, count 0 2006.176.07:48:00.45#ibcon#about to read 4, iclass 33, count 0 2006.176.07:48:00.45#ibcon#read 4, iclass 33, count 0 2006.176.07:48:00.45#ibcon#about to read 5, iclass 33, count 0 2006.176.07:48:00.45#ibcon#read 5, iclass 33, count 0 2006.176.07:48:00.45#ibcon#about to read 6, iclass 33, count 0 2006.176.07:48:00.45#ibcon#read 6, iclass 33, count 0 2006.176.07:48:00.45#ibcon#end of sib2, iclass 33, count 0 2006.176.07:48:00.45#ibcon#*after write, iclass 33, count 0 2006.176.07:48:00.45#ibcon#*before return 0, iclass 33, count 0 2006.176.07:48:00.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:48:00.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.07:48:00.45#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.07:48:00.45#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.07:48:00.45$vc4f8/va=8,6 2006.176.07:48:00.45#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.176.07:48:00.45#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.176.07:48:00.45#ibcon#ireg 11 cls_cnt 2 2006.176.07:48:00.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:48:00.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:48:00.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:48:00.51#ibcon#enter wrdev, iclass 35, count 2 2006.176.07:48:00.51#ibcon#first serial, iclass 35, count 2 2006.176.07:48:00.51#ibcon#enter sib2, iclass 35, count 2 2006.176.07:48:00.51#ibcon#flushed, iclass 35, count 2 2006.176.07:48:00.51#ibcon#about to write, iclass 35, count 2 2006.176.07:48:00.51#ibcon#wrote, iclass 35, count 2 2006.176.07:48:00.51#ibcon#about to read 3, iclass 35, count 2 2006.176.07:48:00.53#ibcon#read 3, iclass 35, count 2 2006.176.07:48:00.53#ibcon#about to read 4, iclass 35, count 2 2006.176.07:48:00.53#ibcon#read 4, iclass 35, count 2 2006.176.07:48:00.53#ibcon#about to read 5, iclass 35, count 2 2006.176.07:48:00.53#ibcon#read 5, iclass 35, count 2 2006.176.07:48:00.53#ibcon#about to read 6, iclass 35, count 2 2006.176.07:48:00.53#ibcon#read 6, iclass 35, count 2 2006.176.07:48:00.53#ibcon#end of sib2, iclass 35, count 2 2006.176.07:48:00.53#ibcon#*mode == 0, iclass 35, count 2 2006.176.07:48:00.53#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.176.07:48:00.53#ibcon#[25=AT08-06\r\n] 2006.176.07:48:00.53#ibcon#*before write, iclass 35, count 2 2006.176.07:48:00.53#ibcon#enter sib2, iclass 35, count 2 2006.176.07:48:00.53#ibcon#flushed, iclass 35, count 2 2006.176.07:48:00.53#ibcon#about to write, iclass 35, count 2 2006.176.07:48:00.53#ibcon#wrote, iclass 35, count 2 2006.176.07:48:00.53#ibcon#about to read 3, iclass 35, count 2 2006.176.07:48:00.56#ibcon#read 3, iclass 35, count 2 2006.176.07:48:00.56#ibcon#about to read 4, iclass 35, count 2 2006.176.07:48:00.56#ibcon#read 4, iclass 35, count 2 2006.176.07:48:00.56#ibcon#about to read 5, iclass 35, count 2 2006.176.07:48:00.56#ibcon#read 5, iclass 35, count 2 2006.176.07:48:00.56#ibcon#about to read 6, iclass 35, count 2 2006.176.07:48:00.56#ibcon#read 6, iclass 35, count 2 2006.176.07:48:00.56#ibcon#end of sib2, iclass 35, count 2 2006.176.07:48:00.56#ibcon#*after write, iclass 35, count 2 2006.176.07:48:00.56#ibcon#*before return 0, iclass 35, count 2 2006.176.07:48:00.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:48:00.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.176.07:48:00.56#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.176.07:48:00.56#ibcon#ireg 7 cls_cnt 0 2006.176.07:48:00.56#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:48:00.68#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:48:00.68#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:48:00.68#ibcon#enter wrdev, iclass 35, count 0 2006.176.07:48:00.68#ibcon#first serial, iclass 35, count 0 2006.176.07:48:00.68#ibcon#enter sib2, iclass 35, count 0 2006.176.07:48:00.68#ibcon#flushed, iclass 35, count 0 2006.176.07:48:00.68#ibcon#about to write, iclass 35, count 0 2006.176.07:48:00.68#ibcon#wrote, iclass 35, count 0 2006.176.07:48:00.68#ibcon#about to read 3, iclass 35, count 0 2006.176.07:48:00.70#ibcon#read 3, iclass 35, count 0 2006.176.07:48:00.70#ibcon#about to read 4, iclass 35, count 0 2006.176.07:48:00.70#ibcon#read 4, iclass 35, count 0 2006.176.07:48:00.70#ibcon#about to read 5, iclass 35, count 0 2006.176.07:48:00.70#ibcon#read 5, iclass 35, count 0 2006.176.07:48:00.70#ibcon#about to read 6, iclass 35, count 0 2006.176.07:48:00.70#ibcon#read 6, iclass 35, count 0 2006.176.07:48:00.70#ibcon#end of sib2, iclass 35, count 0 2006.176.07:48:00.70#ibcon#*mode == 0, iclass 35, count 0 2006.176.07:48:00.70#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.07:48:00.70#ibcon#[25=USB\r\n] 2006.176.07:48:00.70#ibcon#*before write, iclass 35, count 0 2006.176.07:48:00.70#ibcon#enter sib2, iclass 35, count 0 2006.176.07:48:00.70#ibcon#flushed, iclass 35, count 0 2006.176.07:48:00.70#ibcon#about to write, iclass 35, count 0 2006.176.07:48:00.70#ibcon#wrote, iclass 35, count 0 2006.176.07:48:00.70#ibcon#about to read 3, iclass 35, count 0 2006.176.07:48:00.73#ibcon#read 3, iclass 35, count 0 2006.176.07:48:00.73#ibcon#about to read 4, iclass 35, count 0 2006.176.07:48:00.73#ibcon#read 4, iclass 35, count 0 2006.176.07:48:00.73#ibcon#about to read 5, iclass 35, count 0 2006.176.07:48:00.73#ibcon#read 5, iclass 35, count 0 2006.176.07:48:00.73#ibcon#about to read 6, iclass 35, count 0 2006.176.07:48:00.73#ibcon#read 6, iclass 35, count 0 2006.176.07:48:00.73#ibcon#end of sib2, iclass 35, count 0 2006.176.07:48:00.73#ibcon#*after write, iclass 35, count 0 2006.176.07:48:00.73#ibcon#*before return 0, iclass 35, count 0 2006.176.07:48:00.73#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:48:00.73#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.176.07:48:00.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.07:48:00.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.07:48:00.73$vc4f8/vblo=1,632.99 2006.176.07:48:00.73#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.176.07:48:00.73#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.176.07:48:00.73#ibcon#ireg 17 cls_cnt 0 2006.176.07:48:00.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:48:00.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:48:00.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:48:00.73#ibcon#enter wrdev, iclass 37, count 0 2006.176.07:48:00.73#ibcon#first serial, iclass 37, count 0 2006.176.07:48:00.73#ibcon#enter sib2, iclass 37, count 0 2006.176.07:48:00.73#ibcon#flushed, iclass 37, count 0 2006.176.07:48:00.73#ibcon#about to write, iclass 37, count 0 2006.176.07:48:00.73#ibcon#wrote, iclass 37, count 0 2006.176.07:48:00.73#ibcon#about to read 3, iclass 37, count 0 2006.176.07:48:00.75#ibcon#read 3, iclass 37, count 0 2006.176.07:48:00.75#ibcon#about to read 4, iclass 37, count 0 2006.176.07:48:00.75#ibcon#read 4, iclass 37, count 0 2006.176.07:48:00.75#ibcon#about to read 5, iclass 37, count 0 2006.176.07:48:00.75#ibcon#read 5, iclass 37, count 0 2006.176.07:48:00.75#ibcon#about to read 6, iclass 37, count 0 2006.176.07:48:00.75#ibcon#read 6, iclass 37, count 0 2006.176.07:48:00.75#ibcon#end of sib2, iclass 37, count 0 2006.176.07:48:00.75#ibcon#*mode == 0, iclass 37, count 0 2006.176.07:48:00.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.07:48:00.75#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:48:00.75#ibcon#*before write, iclass 37, count 0 2006.176.07:48:00.75#ibcon#enter sib2, iclass 37, count 0 2006.176.07:48:00.75#ibcon#flushed, iclass 37, count 0 2006.176.07:48:00.75#ibcon#about to write, iclass 37, count 0 2006.176.07:48:00.75#ibcon#wrote, iclass 37, count 0 2006.176.07:48:00.75#ibcon#about to read 3, iclass 37, count 0 2006.176.07:48:00.79#ibcon#read 3, iclass 37, count 0 2006.176.07:48:00.79#ibcon#about to read 4, iclass 37, count 0 2006.176.07:48:00.79#ibcon#read 4, iclass 37, count 0 2006.176.07:48:00.79#ibcon#about to read 5, iclass 37, count 0 2006.176.07:48:00.79#ibcon#read 5, iclass 37, count 0 2006.176.07:48:00.79#ibcon#about to read 6, iclass 37, count 0 2006.176.07:48:00.79#ibcon#read 6, iclass 37, count 0 2006.176.07:48:00.79#ibcon#end of sib2, iclass 37, count 0 2006.176.07:48:00.79#ibcon#*after write, iclass 37, count 0 2006.176.07:48:00.79#ibcon#*before return 0, iclass 37, count 0 2006.176.07:48:00.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:48:00.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.176.07:48:00.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.07:48:00.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.07:48:00.79$vc4f8/vb=1,4 2006.176.07:48:00.79#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.176.07:48:00.79#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.176.07:48:00.79#ibcon#ireg 11 cls_cnt 2 2006.176.07:48:00.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:48:00.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:48:00.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:48:00.79#ibcon#enter wrdev, iclass 39, count 2 2006.176.07:48:00.79#ibcon#first serial, iclass 39, count 2 2006.176.07:48:00.79#ibcon#enter sib2, iclass 39, count 2 2006.176.07:48:00.79#ibcon#flushed, iclass 39, count 2 2006.176.07:48:00.79#ibcon#about to write, iclass 39, count 2 2006.176.07:48:00.79#ibcon#wrote, iclass 39, count 2 2006.176.07:48:00.79#ibcon#about to read 3, iclass 39, count 2 2006.176.07:48:00.81#ibcon#read 3, iclass 39, count 2 2006.176.07:48:00.81#ibcon#about to read 4, iclass 39, count 2 2006.176.07:48:00.81#ibcon#read 4, iclass 39, count 2 2006.176.07:48:00.81#ibcon#about to read 5, iclass 39, count 2 2006.176.07:48:00.81#ibcon#read 5, iclass 39, count 2 2006.176.07:48:00.81#ibcon#about to read 6, iclass 39, count 2 2006.176.07:48:00.81#ibcon#read 6, iclass 39, count 2 2006.176.07:48:00.81#ibcon#end of sib2, iclass 39, count 2 2006.176.07:48:00.81#ibcon#*mode == 0, iclass 39, count 2 2006.176.07:48:00.81#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.176.07:48:00.81#ibcon#[27=AT01-04\r\n] 2006.176.07:48:00.81#ibcon#*before write, iclass 39, count 2 2006.176.07:48:00.81#ibcon#enter sib2, iclass 39, count 2 2006.176.07:48:00.81#ibcon#flushed, iclass 39, count 2 2006.176.07:48:00.81#ibcon#about to write, iclass 39, count 2 2006.176.07:48:00.81#ibcon#wrote, iclass 39, count 2 2006.176.07:48:00.81#ibcon#about to read 3, iclass 39, count 2 2006.176.07:48:00.84#ibcon#read 3, iclass 39, count 2 2006.176.07:48:00.84#ibcon#about to read 4, iclass 39, count 2 2006.176.07:48:00.84#ibcon#read 4, iclass 39, count 2 2006.176.07:48:00.84#ibcon#about to read 5, iclass 39, count 2 2006.176.07:48:00.84#ibcon#read 5, iclass 39, count 2 2006.176.07:48:00.84#ibcon#about to read 6, iclass 39, count 2 2006.176.07:48:00.84#ibcon#read 6, iclass 39, count 2 2006.176.07:48:00.84#ibcon#end of sib2, iclass 39, count 2 2006.176.07:48:00.84#ibcon#*after write, iclass 39, count 2 2006.176.07:48:00.84#ibcon#*before return 0, iclass 39, count 2 2006.176.07:48:00.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:48:00.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.176.07:48:00.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.176.07:48:00.84#ibcon#ireg 7 cls_cnt 0 2006.176.07:48:00.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:48:00.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:48:00.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:48:00.96#ibcon#enter wrdev, iclass 39, count 0 2006.176.07:48:00.96#ibcon#first serial, iclass 39, count 0 2006.176.07:48:00.96#ibcon#enter sib2, iclass 39, count 0 2006.176.07:48:00.96#ibcon#flushed, iclass 39, count 0 2006.176.07:48:00.96#ibcon#about to write, iclass 39, count 0 2006.176.07:48:00.96#ibcon#wrote, iclass 39, count 0 2006.176.07:48:00.96#ibcon#about to read 3, iclass 39, count 0 2006.176.07:48:00.98#ibcon#read 3, iclass 39, count 0 2006.176.07:48:00.98#ibcon#about to read 4, iclass 39, count 0 2006.176.07:48:00.98#ibcon#read 4, iclass 39, count 0 2006.176.07:48:00.98#ibcon#about to read 5, iclass 39, count 0 2006.176.07:48:00.98#ibcon#read 5, iclass 39, count 0 2006.176.07:48:00.98#ibcon#about to read 6, iclass 39, count 0 2006.176.07:48:00.98#ibcon#read 6, iclass 39, count 0 2006.176.07:48:00.98#ibcon#end of sib2, iclass 39, count 0 2006.176.07:48:00.98#ibcon#*mode == 0, iclass 39, count 0 2006.176.07:48:00.98#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.07:48:00.98#ibcon#[27=USB\r\n] 2006.176.07:48:00.98#ibcon#*before write, iclass 39, count 0 2006.176.07:48:00.98#ibcon#enter sib2, iclass 39, count 0 2006.176.07:48:00.98#ibcon#flushed, iclass 39, count 0 2006.176.07:48:00.98#ibcon#about to write, iclass 39, count 0 2006.176.07:48:00.98#ibcon#wrote, iclass 39, count 0 2006.176.07:48:00.98#ibcon#about to read 3, iclass 39, count 0 2006.176.07:48:01.01#ibcon#read 3, iclass 39, count 0 2006.176.07:48:01.01#ibcon#about to read 4, iclass 39, count 0 2006.176.07:48:01.01#ibcon#read 4, iclass 39, count 0 2006.176.07:48:01.01#ibcon#about to read 5, iclass 39, count 0 2006.176.07:48:01.01#ibcon#read 5, iclass 39, count 0 2006.176.07:48:01.01#ibcon#about to read 6, iclass 39, count 0 2006.176.07:48:01.01#ibcon#read 6, iclass 39, count 0 2006.176.07:48:01.01#ibcon#end of sib2, iclass 39, count 0 2006.176.07:48:01.01#ibcon#*after write, iclass 39, count 0 2006.176.07:48:01.01#ibcon#*before return 0, iclass 39, count 0 2006.176.07:48:01.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:48:01.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.176.07:48:01.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.07:48:01.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.07:48:01.01$vc4f8/vblo=2,640.99 2006.176.07:48:01.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.07:48:01.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.07:48:01.01#ibcon#ireg 17 cls_cnt 0 2006.176.07:48:01.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:48:01.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:48:01.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:48:01.01#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:48:01.01#ibcon#first serial, iclass 3, count 0 2006.176.07:48:01.01#ibcon#enter sib2, iclass 3, count 0 2006.176.07:48:01.01#ibcon#flushed, iclass 3, count 0 2006.176.07:48:01.01#ibcon#about to write, iclass 3, count 0 2006.176.07:48:01.01#ibcon#wrote, iclass 3, count 0 2006.176.07:48:01.01#ibcon#about to read 3, iclass 3, count 0 2006.176.07:48:01.03#ibcon#read 3, iclass 3, count 0 2006.176.07:48:01.03#ibcon#about to read 4, iclass 3, count 0 2006.176.07:48:01.03#ibcon#read 4, iclass 3, count 0 2006.176.07:48:01.03#ibcon#about to read 5, iclass 3, count 0 2006.176.07:48:01.03#ibcon#read 5, iclass 3, count 0 2006.176.07:48:01.03#ibcon#about to read 6, iclass 3, count 0 2006.176.07:48:01.03#ibcon#read 6, iclass 3, count 0 2006.176.07:48:01.03#ibcon#end of sib2, iclass 3, count 0 2006.176.07:48:01.03#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:48:01.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:48:01.03#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:48:01.03#ibcon#*before write, iclass 3, count 0 2006.176.07:48:01.03#ibcon#enter sib2, iclass 3, count 0 2006.176.07:48:01.03#ibcon#flushed, iclass 3, count 0 2006.176.07:48:01.03#ibcon#about to write, iclass 3, count 0 2006.176.07:48:01.03#ibcon#wrote, iclass 3, count 0 2006.176.07:48:01.03#ibcon#about to read 3, iclass 3, count 0 2006.176.07:48:01.07#ibcon#read 3, iclass 3, count 0 2006.176.07:48:01.07#ibcon#about to read 4, iclass 3, count 0 2006.176.07:48:01.07#ibcon#read 4, iclass 3, count 0 2006.176.07:48:01.07#ibcon#about to read 5, iclass 3, count 0 2006.176.07:48:01.07#ibcon#read 5, iclass 3, count 0 2006.176.07:48:01.07#ibcon#about to read 6, iclass 3, count 0 2006.176.07:48:01.07#ibcon#read 6, iclass 3, count 0 2006.176.07:48:01.07#ibcon#end of sib2, iclass 3, count 0 2006.176.07:48:01.07#ibcon#*after write, iclass 3, count 0 2006.176.07:48:01.07#ibcon#*before return 0, iclass 3, count 0 2006.176.07:48:01.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:48:01.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.07:48:01.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:48:01.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:48:01.07$vc4f8/vb=2,4 2006.176.07:48:01.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.176.07:48:01.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.176.07:48:01.07#ibcon#ireg 11 cls_cnt 2 2006.176.07:48:01.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:48:01.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:48:01.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:48:01.13#ibcon#enter wrdev, iclass 5, count 2 2006.176.07:48:01.13#ibcon#first serial, iclass 5, count 2 2006.176.07:48:01.13#ibcon#enter sib2, iclass 5, count 2 2006.176.07:48:01.13#ibcon#flushed, iclass 5, count 2 2006.176.07:48:01.13#ibcon#about to write, iclass 5, count 2 2006.176.07:48:01.13#ibcon#wrote, iclass 5, count 2 2006.176.07:48:01.13#ibcon#about to read 3, iclass 5, count 2 2006.176.07:48:01.15#ibcon#read 3, iclass 5, count 2 2006.176.07:48:01.15#ibcon#about to read 4, iclass 5, count 2 2006.176.07:48:01.15#ibcon#read 4, iclass 5, count 2 2006.176.07:48:01.15#ibcon#about to read 5, iclass 5, count 2 2006.176.07:48:01.15#ibcon#read 5, iclass 5, count 2 2006.176.07:48:01.15#ibcon#about to read 6, iclass 5, count 2 2006.176.07:48:01.15#ibcon#read 6, iclass 5, count 2 2006.176.07:48:01.15#ibcon#end of sib2, iclass 5, count 2 2006.176.07:48:01.15#ibcon#*mode == 0, iclass 5, count 2 2006.176.07:48:01.15#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.176.07:48:01.15#ibcon#[27=AT02-04\r\n] 2006.176.07:48:01.15#ibcon#*before write, iclass 5, count 2 2006.176.07:48:01.15#ibcon#enter sib2, iclass 5, count 2 2006.176.07:48:01.15#ibcon#flushed, iclass 5, count 2 2006.176.07:48:01.15#ibcon#about to write, iclass 5, count 2 2006.176.07:48:01.15#ibcon#wrote, iclass 5, count 2 2006.176.07:48:01.15#ibcon#about to read 3, iclass 5, count 2 2006.176.07:48:01.18#ibcon#read 3, iclass 5, count 2 2006.176.07:48:01.18#ibcon#about to read 4, iclass 5, count 2 2006.176.07:48:01.18#ibcon#read 4, iclass 5, count 2 2006.176.07:48:01.18#ibcon#about to read 5, iclass 5, count 2 2006.176.07:48:01.18#ibcon#read 5, iclass 5, count 2 2006.176.07:48:01.18#ibcon#about to read 6, iclass 5, count 2 2006.176.07:48:01.18#ibcon#read 6, iclass 5, count 2 2006.176.07:48:01.18#ibcon#end of sib2, iclass 5, count 2 2006.176.07:48:01.18#ibcon#*after write, iclass 5, count 2 2006.176.07:48:01.18#ibcon#*before return 0, iclass 5, count 2 2006.176.07:48:01.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:48:01.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.176.07:48:01.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.176.07:48:01.18#ibcon#ireg 7 cls_cnt 0 2006.176.07:48:01.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:48:01.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:48:01.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:48:01.30#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:48:01.30#ibcon#first serial, iclass 5, count 0 2006.176.07:48:01.30#ibcon#enter sib2, iclass 5, count 0 2006.176.07:48:01.30#ibcon#flushed, iclass 5, count 0 2006.176.07:48:01.30#ibcon#about to write, iclass 5, count 0 2006.176.07:48:01.30#ibcon#wrote, iclass 5, count 0 2006.176.07:48:01.30#ibcon#about to read 3, iclass 5, count 0 2006.176.07:48:01.32#ibcon#read 3, iclass 5, count 0 2006.176.07:48:01.32#ibcon#about to read 4, iclass 5, count 0 2006.176.07:48:01.32#ibcon#read 4, iclass 5, count 0 2006.176.07:48:01.32#ibcon#about to read 5, iclass 5, count 0 2006.176.07:48:01.32#ibcon#read 5, iclass 5, count 0 2006.176.07:48:01.32#ibcon#about to read 6, iclass 5, count 0 2006.176.07:48:01.32#ibcon#read 6, iclass 5, count 0 2006.176.07:48:01.32#ibcon#end of sib2, iclass 5, count 0 2006.176.07:48:01.32#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:48:01.32#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:48:01.32#ibcon#[27=USB\r\n] 2006.176.07:48:01.32#ibcon#*before write, iclass 5, count 0 2006.176.07:48:01.32#ibcon#enter sib2, iclass 5, count 0 2006.176.07:48:01.32#ibcon#flushed, iclass 5, count 0 2006.176.07:48:01.32#ibcon#about to write, iclass 5, count 0 2006.176.07:48:01.32#ibcon#wrote, iclass 5, count 0 2006.176.07:48:01.32#ibcon#about to read 3, iclass 5, count 0 2006.176.07:48:01.35#ibcon#read 3, iclass 5, count 0 2006.176.07:48:01.35#ibcon#about to read 4, iclass 5, count 0 2006.176.07:48:01.35#ibcon#read 4, iclass 5, count 0 2006.176.07:48:01.35#ibcon#about to read 5, iclass 5, count 0 2006.176.07:48:01.35#ibcon#read 5, iclass 5, count 0 2006.176.07:48:01.35#ibcon#about to read 6, iclass 5, count 0 2006.176.07:48:01.35#ibcon#read 6, iclass 5, count 0 2006.176.07:48:01.35#ibcon#end of sib2, iclass 5, count 0 2006.176.07:48:01.35#ibcon#*after write, iclass 5, count 0 2006.176.07:48:01.35#ibcon#*before return 0, iclass 5, count 0 2006.176.07:48:01.35#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:48:01.35#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.176.07:48:01.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:48:01.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:48:01.35$vc4f8/vblo=3,656.99 2006.176.07:48:01.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.07:48:01.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.07:48:01.35#ibcon#ireg 17 cls_cnt 0 2006.176.07:48:01.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:48:01.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:48:01.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:48:01.35#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:48:01.35#ibcon#first serial, iclass 7, count 0 2006.176.07:48:01.35#ibcon#enter sib2, iclass 7, count 0 2006.176.07:48:01.35#ibcon#flushed, iclass 7, count 0 2006.176.07:48:01.35#ibcon#about to write, iclass 7, count 0 2006.176.07:48:01.35#ibcon#wrote, iclass 7, count 0 2006.176.07:48:01.35#ibcon#about to read 3, iclass 7, count 0 2006.176.07:48:01.37#ibcon#read 3, iclass 7, count 0 2006.176.07:48:01.37#ibcon#about to read 4, iclass 7, count 0 2006.176.07:48:01.37#ibcon#read 4, iclass 7, count 0 2006.176.07:48:01.37#ibcon#about to read 5, iclass 7, count 0 2006.176.07:48:01.37#ibcon#read 5, iclass 7, count 0 2006.176.07:48:01.37#ibcon#about to read 6, iclass 7, count 0 2006.176.07:48:01.37#ibcon#read 6, iclass 7, count 0 2006.176.07:48:01.37#ibcon#end of sib2, iclass 7, count 0 2006.176.07:48:01.37#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:48:01.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:48:01.37#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:48:01.37#ibcon#*before write, iclass 7, count 0 2006.176.07:48:01.37#ibcon#enter sib2, iclass 7, count 0 2006.176.07:48:01.37#ibcon#flushed, iclass 7, count 0 2006.176.07:48:01.37#ibcon#about to write, iclass 7, count 0 2006.176.07:48:01.37#ibcon#wrote, iclass 7, count 0 2006.176.07:48:01.37#ibcon#about to read 3, iclass 7, count 0 2006.176.07:48:01.41#ibcon#read 3, iclass 7, count 0 2006.176.07:48:01.41#ibcon#about to read 4, iclass 7, count 0 2006.176.07:48:01.41#ibcon#read 4, iclass 7, count 0 2006.176.07:48:01.41#ibcon#about to read 5, iclass 7, count 0 2006.176.07:48:01.41#ibcon#read 5, iclass 7, count 0 2006.176.07:48:01.41#ibcon#about to read 6, iclass 7, count 0 2006.176.07:48:01.41#ibcon#read 6, iclass 7, count 0 2006.176.07:48:01.41#ibcon#end of sib2, iclass 7, count 0 2006.176.07:48:01.41#ibcon#*after write, iclass 7, count 0 2006.176.07:48:01.41#ibcon#*before return 0, iclass 7, count 0 2006.176.07:48:01.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:48:01.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.07:48:01.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:48:01.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:48:01.41$vc4f8/vb=3,4 2006.176.07:48:01.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.176.07:48:01.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.176.07:48:01.41#ibcon#ireg 11 cls_cnt 2 2006.176.07:48:01.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:48:01.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:48:01.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:48:01.47#ibcon#enter wrdev, iclass 11, count 2 2006.176.07:48:01.47#ibcon#first serial, iclass 11, count 2 2006.176.07:48:01.47#ibcon#enter sib2, iclass 11, count 2 2006.176.07:48:01.47#ibcon#flushed, iclass 11, count 2 2006.176.07:48:01.47#ibcon#about to write, iclass 11, count 2 2006.176.07:48:01.47#ibcon#wrote, iclass 11, count 2 2006.176.07:48:01.47#ibcon#about to read 3, iclass 11, count 2 2006.176.07:48:01.49#ibcon#read 3, iclass 11, count 2 2006.176.07:48:01.49#ibcon#about to read 4, iclass 11, count 2 2006.176.07:48:01.49#ibcon#read 4, iclass 11, count 2 2006.176.07:48:01.49#ibcon#about to read 5, iclass 11, count 2 2006.176.07:48:01.49#ibcon#read 5, iclass 11, count 2 2006.176.07:48:01.49#ibcon#about to read 6, iclass 11, count 2 2006.176.07:48:01.49#ibcon#read 6, iclass 11, count 2 2006.176.07:48:01.49#ibcon#end of sib2, iclass 11, count 2 2006.176.07:48:01.49#ibcon#*mode == 0, iclass 11, count 2 2006.176.07:48:01.49#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.176.07:48:01.49#ibcon#[27=AT03-04\r\n] 2006.176.07:48:01.49#ibcon#*before write, iclass 11, count 2 2006.176.07:48:01.49#ibcon#enter sib2, iclass 11, count 2 2006.176.07:48:01.49#ibcon#flushed, iclass 11, count 2 2006.176.07:48:01.49#ibcon#about to write, iclass 11, count 2 2006.176.07:48:01.49#ibcon#wrote, iclass 11, count 2 2006.176.07:48:01.49#ibcon#about to read 3, iclass 11, count 2 2006.176.07:48:01.52#ibcon#read 3, iclass 11, count 2 2006.176.07:48:01.52#ibcon#about to read 4, iclass 11, count 2 2006.176.07:48:01.52#ibcon#read 4, iclass 11, count 2 2006.176.07:48:01.52#ibcon#about to read 5, iclass 11, count 2 2006.176.07:48:01.52#ibcon#read 5, iclass 11, count 2 2006.176.07:48:01.52#ibcon#about to read 6, iclass 11, count 2 2006.176.07:48:01.52#ibcon#read 6, iclass 11, count 2 2006.176.07:48:01.52#ibcon#end of sib2, iclass 11, count 2 2006.176.07:48:01.52#ibcon#*after write, iclass 11, count 2 2006.176.07:48:01.52#ibcon#*before return 0, iclass 11, count 2 2006.176.07:48:01.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:48:01.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.176.07:48:01.52#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.176.07:48:01.52#ibcon#ireg 7 cls_cnt 0 2006.176.07:48:01.52#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:48:01.64#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:48:01.64#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:48:01.64#ibcon#enter wrdev, iclass 11, count 0 2006.176.07:48:01.64#ibcon#first serial, iclass 11, count 0 2006.176.07:48:01.64#ibcon#enter sib2, iclass 11, count 0 2006.176.07:48:01.64#ibcon#flushed, iclass 11, count 0 2006.176.07:48:01.64#ibcon#about to write, iclass 11, count 0 2006.176.07:48:01.64#ibcon#wrote, iclass 11, count 0 2006.176.07:48:01.64#ibcon#about to read 3, iclass 11, count 0 2006.176.07:48:01.66#ibcon#read 3, iclass 11, count 0 2006.176.07:48:01.66#ibcon#about to read 4, iclass 11, count 0 2006.176.07:48:01.66#ibcon#read 4, iclass 11, count 0 2006.176.07:48:01.66#ibcon#about to read 5, iclass 11, count 0 2006.176.07:48:01.66#ibcon#read 5, iclass 11, count 0 2006.176.07:48:01.66#ibcon#about to read 6, iclass 11, count 0 2006.176.07:48:01.66#ibcon#read 6, iclass 11, count 0 2006.176.07:48:01.66#ibcon#end of sib2, iclass 11, count 0 2006.176.07:48:01.66#ibcon#*mode == 0, iclass 11, count 0 2006.176.07:48:01.66#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.07:48:01.66#ibcon#[27=USB\r\n] 2006.176.07:48:01.66#ibcon#*before write, iclass 11, count 0 2006.176.07:48:01.66#ibcon#enter sib2, iclass 11, count 0 2006.176.07:48:01.66#ibcon#flushed, iclass 11, count 0 2006.176.07:48:01.66#ibcon#about to write, iclass 11, count 0 2006.176.07:48:01.66#ibcon#wrote, iclass 11, count 0 2006.176.07:48:01.66#ibcon#about to read 3, iclass 11, count 0 2006.176.07:48:01.69#ibcon#read 3, iclass 11, count 0 2006.176.07:48:01.69#ibcon#about to read 4, iclass 11, count 0 2006.176.07:48:01.69#ibcon#read 4, iclass 11, count 0 2006.176.07:48:01.69#ibcon#about to read 5, iclass 11, count 0 2006.176.07:48:01.69#ibcon#read 5, iclass 11, count 0 2006.176.07:48:01.69#ibcon#about to read 6, iclass 11, count 0 2006.176.07:48:01.69#ibcon#read 6, iclass 11, count 0 2006.176.07:48:01.69#ibcon#end of sib2, iclass 11, count 0 2006.176.07:48:01.69#ibcon#*after write, iclass 11, count 0 2006.176.07:48:01.69#ibcon#*before return 0, iclass 11, count 0 2006.176.07:48:01.69#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:48:01.69#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.176.07:48:01.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.07:48:01.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.07:48:01.69$vc4f8/vblo=4,712.99 2006.176.07:48:01.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.07:48:01.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.07:48:01.69#ibcon#ireg 17 cls_cnt 0 2006.176.07:48:01.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:48:01.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:48:01.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:48:01.69#ibcon#enter wrdev, iclass 13, count 0 2006.176.07:48:01.69#ibcon#first serial, iclass 13, count 0 2006.176.07:48:01.69#ibcon#enter sib2, iclass 13, count 0 2006.176.07:48:01.69#ibcon#flushed, iclass 13, count 0 2006.176.07:48:01.69#ibcon#about to write, iclass 13, count 0 2006.176.07:48:01.69#ibcon#wrote, iclass 13, count 0 2006.176.07:48:01.69#ibcon#about to read 3, iclass 13, count 0 2006.176.07:48:01.71#ibcon#read 3, iclass 13, count 0 2006.176.07:48:01.71#ibcon#about to read 4, iclass 13, count 0 2006.176.07:48:01.71#ibcon#read 4, iclass 13, count 0 2006.176.07:48:01.71#ibcon#about to read 5, iclass 13, count 0 2006.176.07:48:01.71#ibcon#read 5, iclass 13, count 0 2006.176.07:48:01.71#ibcon#about to read 6, iclass 13, count 0 2006.176.07:48:01.71#ibcon#read 6, iclass 13, count 0 2006.176.07:48:01.71#ibcon#end of sib2, iclass 13, count 0 2006.176.07:48:01.71#ibcon#*mode == 0, iclass 13, count 0 2006.176.07:48:01.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.07:48:01.71#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:48:01.71#ibcon#*before write, iclass 13, count 0 2006.176.07:48:01.71#ibcon#enter sib2, iclass 13, count 0 2006.176.07:48:01.71#ibcon#flushed, iclass 13, count 0 2006.176.07:48:01.71#ibcon#about to write, iclass 13, count 0 2006.176.07:48:01.71#ibcon#wrote, iclass 13, count 0 2006.176.07:48:01.71#ibcon#about to read 3, iclass 13, count 0 2006.176.07:48:01.75#ibcon#read 3, iclass 13, count 0 2006.176.07:48:01.75#ibcon#about to read 4, iclass 13, count 0 2006.176.07:48:01.75#ibcon#read 4, iclass 13, count 0 2006.176.07:48:01.75#ibcon#about to read 5, iclass 13, count 0 2006.176.07:48:01.75#ibcon#read 5, iclass 13, count 0 2006.176.07:48:01.75#ibcon#about to read 6, iclass 13, count 0 2006.176.07:48:01.75#ibcon#read 6, iclass 13, count 0 2006.176.07:48:01.75#ibcon#end of sib2, iclass 13, count 0 2006.176.07:48:01.75#ibcon#*after write, iclass 13, count 0 2006.176.07:48:01.75#ibcon#*before return 0, iclass 13, count 0 2006.176.07:48:01.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:48:01.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:48:01.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.07:48:01.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.07:48:01.75$vc4f8/vb=4,4 2006.176.07:48:01.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.176.07:48:01.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.176.07:48:01.75#ibcon#ireg 11 cls_cnt 2 2006.176.07:48:01.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:48:01.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:48:01.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:48:01.81#ibcon#enter wrdev, iclass 15, count 2 2006.176.07:48:01.81#ibcon#first serial, iclass 15, count 2 2006.176.07:48:01.81#ibcon#enter sib2, iclass 15, count 2 2006.176.07:48:01.81#ibcon#flushed, iclass 15, count 2 2006.176.07:48:01.81#ibcon#about to write, iclass 15, count 2 2006.176.07:48:01.81#ibcon#wrote, iclass 15, count 2 2006.176.07:48:01.81#ibcon#about to read 3, iclass 15, count 2 2006.176.07:48:01.83#ibcon#read 3, iclass 15, count 2 2006.176.07:48:01.83#ibcon#about to read 4, iclass 15, count 2 2006.176.07:48:01.83#ibcon#read 4, iclass 15, count 2 2006.176.07:48:01.83#ibcon#about to read 5, iclass 15, count 2 2006.176.07:48:01.83#ibcon#read 5, iclass 15, count 2 2006.176.07:48:01.83#ibcon#about to read 6, iclass 15, count 2 2006.176.07:48:01.83#ibcon#read 6, iclass 15, count 2 2006.176.07:48:01.83#ibcon#end of sib2, iclass 15, count 2 2006.176.07:48:01.83#ibcon#*mode == 0, iclass 15, count 2 2006.176.07:48:01.83#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.176.07:48:01.83#ibcon#[27=AT04-04\r\n] 2006.176.07:48:01.83#ibcon#*before write, iclass 15, count 2 2006.176.07:48:01.83#ibcon#enter sib2, iclass 15, count 2 2006.176.07:48:01.83#ibcon#flushed, iclass 15, count 2 2006.176.07:48:01.83#ibcon#about to write, iclass 15, count 2 2006.176.07:48:01.83#ibcon#wrote, iclass 15, count 2 2006.176.07:48:01.83#ibcon#about to read 3, iclass 15, count 2 2006.176.07:48:01.86#ibcon#read 3, iclass 15, count 2 2006.176.07:48:01.86#ibcon#about to read 4, iclass 15, count 2 2006.176.07:48:01.86#ibcon#read 4, iclass 15, count 2 2006.176.07:48:01.86#ibcon#about to read 5, iclass 15, count 2 2006.176.07:48:01.86#ibcon#read 5, iclass 15, count 2 2006.176.07:48:01.86#ibcon#about to read 6, iclass 15, count 2 2006.176.07:48:01.86#ibcon#read 6, iclass 15, count 2 2006.176.07:48:01.86#ibcon#end of sib2, iclass 15, count 2 2006.176.07:48:01.86#ibcon#*after write, iclass 15, count 2 2006.176.07:48:01.86#ibcon#*before return 0, iclass 15, count 2 2006.176.07:48:01.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:48:01.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.176.07:48:01.86#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.176.07:48:01.86#ibcon#ireg 7 cls_cnt 0 2006.176.07:48:01.86#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:48:01.98#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:48:01.98#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:48:01.98#ibcon#enter wrdev, iclass 15, count 0 2006.176.07:48:01.98#ibcon#first serial, iclass 15, count 0 2006.176.07:48:01.98#ibcon#enter sib2, iclass 15, count 0 2006.176.07:48:01.98#ibcon#flushed, iclass 15, count 0 2006.176.07:48:01.98#ibcon#about to write, iclass 15, count 0 2006.176.07:48:01.98#ibcon#wrote, iclass 15, count 0 2006.176.07:48:01.98#ibcon#about to read 3, iclass 15, count 0 2006.176.07:48:02.00#ibcon#read 3, iclass 15, count 0 2006.176.07:48:02.00#ibcon#about to read 4, iclass 15, count 0 2006.176.07:48:02.00#ibcon#read 4, iclass 15, count 0 2006.176.07:48:02.00#ibcon#about to read 5, iclass 15, count 0 2006.176.07:48:02.00#ibcon#read 5, iclass 15, count 0 2006.176.07:48:02.00#ibcon#about to read 6, iclass 15, count 0 2006.176.07:48:02.00#ibcon#read 6, iclass 15, count 0 2006.176.07:48:02.00#ibcon#end of sib2, iclass 15, count 0 2006.176.07:48:02.00#ibcon#*mode == 0, iclass 15, count 0 2006.176.07:48:02.00#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.07:48:02.00#ibcon#[27=USB\r\n] 2006.176.07:48:02.00#ibcon#*before write, iclass 15, count 0 2006.176.07:48:02.00#ibcon#enter sib2, iclass 15, count 0 2006.176.07:48:02.00#ibcon#flushed, iclass 15, count 0 2006.176.07:48:02.00#ibcon#about to write, iclass 15, count 0 2006.176.07:48:02.00#ibcon#wrote, iclass 15, count 0 2006.176.07:48:02.00#ibcon#about to read 3, iclass 15, count 0 2006.176.07:48:02.03#ibcon#read 3, iclass 15, count 0 2006.176.07:48:02.03#ibcon#about to read 4, iclass 15, count 0 2006.176.07:48:02.03#ibcon#read 4, iclass 15, count 0 2006.176.07:48:02.03#ibcon#about to read 5, iclass 15, count 0 2006.176.07:48:02.03#ibcon#read 5, iclass 15, count 0 2006.176.07:48:02.03#ibcon#about to read 6, iclass 15, count 0 2006.176.07:48:02.03#ibcon#read 6, iclass 15, count 0 2006.176.07:48:02.03#ibcon#end of sib2, iclass 15, count 0 2006.176.07:48:02.03#ibcon#*after write, iclass 15, count 0 2006.176.07:48:02.03#ibcon#*before return 0, iclass 15, count 0 2006.176.07:48:02.03#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:48:02.03#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.176.07:48:02.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.07:48:02.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.07:48:02.03$vc4f8/vblo=5,744.99 2006.176.07:48:02.03#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.07:48:02.03#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.07:48:02.03#ibcon#ireg 17 cls_cnt 0 2006.176.07:48:02.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:48:02.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:48:02.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:48:02.03#ibcon#enter wrdev, iclass 17, count 0 2006.176.07:48:02.03#ibcon#first serial, iclass 17, count 0 2006.176.07:48:02.03#ibcon#enter sib2, iclass 17, count 0 2006.176.07:48:02.03#ibcon#flushed, iclass 17, count 0 2006.176.07:48:02.03#ibcon#about to write, iclass 17, count 0 2006.176.07:48:02.03#ibcon#wrote, iclass 17, count 0 2006.176.07:48:02.03#ibcon#about to read 3, iclass 17, count 0 2006.176.07:48:02.05#ibcon#read 3, iclass 17, count 0 2006.176.07:48:02.05#ibcon#about to read 4, iclass 17, count 0 2006.176.07:48:02.05#ibcon#read 4, iclass 17, count 0 2006.176.07:48:02.05#ibcon#about to read 5, iclass 17, count 0 2006.176.07:48:02.05#ibcon#read 5, iclass 17, count 0 2006.176.07:48:02.05#ibcon#about to read 6, iclass 17, count 0 2006.176.07:48:02.05#ibcon#read 6, iclass 17, count 0 2006.176.07:48:02.05#ibcon#end of sib2, iclass 17, count 0 2006.176.07:48:02.05#ibcon#*mode == 0, iclass 17, count 0 2006.176.07:48:02.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.07:48:02.05#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:48:02.05#ibcon#*before write, iclass 17, count 0 2006.176.07:48:02.05#ibcon#enter sib2, iclass 17, count 0 2006.176.07:48:02.05#ibcon#flushed, iclass 17, count 0 2006.176.07:48:02.05#ibcon#about to write, iclass 17, count 0 2006.176.07:48:02.05#ibcon#wrote, iclass 17, count 0 2006.176.07:48:02.05#ibcon#about to read 3, iclass 17, count 0 2006.176.07:48:02.09#ibcon#read 3, iclass 17, count 0 2006.176.07:48:02.09#ibcon#about to read 4, iclass 17, count 0 2006.176.07:48:02.09#ibcon#read 4, iclass 17, count 0 2006.176.07:48:02.09#ibcon#about to read 5, iclass 17, count 0 2006.176.07:48:02.09#ibcon#read 5, iclass 17, count 0 2006.176.07:48:02.09#ibcon#about to read 6, iclass 17, count 0 2006.176.07:48:02.09#ibcon#read 6, iclass 17, count 0 2006.176.07:48:02.09#ibcon#end of sib2, iclass 17, count 0 2006.176.07:48:02.09#ibcon#*after write, iclass 17, count 0 2006.176.07:48:02.09#ibcon#*before return 0, iclass 17, count 0 2006.176.07:48:02.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:48:02.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.07:48:02.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.07:48:02.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.07:48:02.09$vc4f8/vb=5,4 2006.176.07:48:02.09#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.176.07:48:02.09#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.176.07:48:02.09#ibcon#ireg 11 cls_cnt 2 2006.176.07:48:02.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:48:02.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:48:02.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:48:02.15#ibcon#enter wrdev, iclass 19, count 2 2006.176.07:48:02.15#ibcon#first serial, iclass 19, count 2 2006.176.07:48:02.15#ibcon#enter sib2, iclass 19, count 2 2006.176.07:48:02.15#ibcon#flushed, iclass 19, count 2 2006.176.07:48:02.15#ibcon#about to write, iclass 19, count 2 2006.176.07:48:02.15#ibcon#wrote, iclass 19, count 2 2006.176.07:48:02.15#ibcon#about to read 3, iclass 19, count 2 2006.176.07:48:02.17#ibcon#read 3, iclass 19, count 2 2006.176.07:48:02.17#ibcon#about to read 4, iclass 19, count 2 2006.176.07:48:02.17#ibcon#read 4, iclass 19, count 2 2006.176.07:48:02.17#ibcon#about to read 5, iclass 19, count 2 2006.176.07:48:02.17#ibcon#read 5, iclass 19, count 2 2006.176.07:48:02.17#ibcon#about to read 6, iclass 19, count 2 2006.176.07:48:02.17#ibcon#read 6, iclass 19, count 2 2006.176.07:48:02.17#ibcon#end of sib2, iclass 19, count 2 2006.176.07:48:02.17#ibcon#*mode == 0, iclass 19, count 2 2006.176.07:48:02.17#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.176.07:48:02.17#ibcon#[27=AT05-04\r\n] 2006.176.07:48:02.17#ibcon#*before write, iclass 19, count 2 2006.176.07:48:02.17#ibcon#enter sib2, iclass 19, count 2 2006.176.07:48:02.17#ibcon#flushed, iclass 19, count 2 2006.176.07:48:02.17#ibcon#about to write, iclass 19, count 2 2006.176.07:48:02.17#ibcon#wrote, iclass 19, count 2 2006.176.07:48:02.17#ibcon#about to read 3, iclass 19, count 2 2006.176.07:48:02.20#ibcon#read 3, iclass 19, count 2 2006.176.07:48:02.20#ibcon#about to read 4, iclass 19, count 2 2006.176.07:48:02.20#ibcon#read 4, iclass 19, count 2 2006.176.07:48:02.20#ibcon#about to read 5, iclass 19, count 2 2006.176.07:48:02.20#ibcon#read 5, iclass 19, count 2 2006.176.07:48:02.20#ibcon#about to read 6, iclass 19, count 2 2006.176.07:48:02.20#ibcon#read 6, iclass 19, count 2 2006.176.07:48:02.20#ibcon#end of sib2, iclass 19, count 2 2006.176.07:48:02.20#ibcon#*after write, iclass 19, count 2 2006.176.07:48:02.20#ibcon#*before return 0, iclass 19, count 2 2006.176.07:48:02.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:48:02.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.176.07:48:02.20#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.176.07:48:02.20#ibcon#ireg 7 cls_cnt 0 2006.176.07:48:02.20#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:48:02.32#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:48:02.32#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:48:02.32#ibcon#enter wrdev, iclass 19, count 0 2006.176.07:48:02.32#ibcon#first serial, iclass 19, count 0 2006.176.07:48:02.32#ibcon#enter sib2, iclass 19, count 0 2006.176.07:48:02.32#ibcon#flushed, iclass 19, count 0 2006.176.07:48:02.32#ibcon#about to write, iclass 19, count 0 2006.176.07:48:02.32#ibcon#wrote, iclass 19, count 0 2006.176.07:48:02.32#ibcon#about to read 3, iclass 19, count 0 2006.176.07:48:02.34#ibcon#read 3, iclass 19, count 0 2006.176.07:48:02.34#ibcon#about to read 4, iclass 19, count 0 2006.176.07:48:02.34#ibcon#read 4, iclass 19, count 0 2006.176.07:48:02.34#ibcon#about to read 5, iclass 19, count 0 2006.176.07:48:02.34#ibcon#read 5, iclass 19, count 0 2006.176.07:48:02.34#ibcon#about to read 6, iclass 19, count 0 2006.176.07:48:02.34#ibcon#read 6, iclass 19, count 0 2006.176.07:48:02.34#ibcon#end of sib2, iclass 19, count 0 2006.176.07:48:02.34#ibcon#*mode == 0, iclass 19, count 0 2006.176.07:48:02.34#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.07:48:02.34#ibcon#[27=USB\r\n] 2006.176.07:48:02.34#ibcon#*before write, iclass 19, count 0 2006.176.07:48:02.34#ibcon#enter sib2, iclass 19, count 0 2006.176.07:48:02.34#ibcon#flushed, iclass 19, count 0 2006.176.07:48:02.34#ibcon#about to write, iclass 19, count 0 2006.176.07:48:02.34#ibcon#wrote, iclass 19, count 0 2006.176.07:48:02.34#ibcon#about to read 3, iclass 19, count 0 2006.176.07:48:02.37#ibcon#read 3, iclass 19, count 0 2006.176.07:48:02.37#ibcon#about to read 4, iclass 19, count 0 2006.176.07:48:02.37#ibcon#read 4, iclass 19, count 0 2006.176.07:48:02.37#ibcon#about to read 5, iclass 19, count 0 2006.176.07:48:02.37#ibcon#read 5, iclass 19, count 0 2006.176.07:48:02.37#ibcon#about to read 6, iclass 19, count 0 2006.176.07:48:02.37#ibcon#read 6, iclass 19, count 0 2006.176.07:48:02.37#ibcon#end of sib2, iclass 19, count 0 2006.176.07:48:02.37#ibcon#*after write, iclass 19, count 0 2006.176.07:48:02.37#ibcon#*before return 0, iclass 19, count 0 2006.176.07:48:02.37#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:48:02.37#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.176.07:48:02.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.07:48:02.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.07:48:02.37$vc4f8/vblo=6,752.99 2006.176.07:48:02.37#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.07:48:02.37#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.07:48:02.37#ibcon#ireg 17 cls_cnt 0 2006.176.07:48:02.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:48:02.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:48:02.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:48:02.37#ibcon#enter wrdev, iclass 21, count 0 2006.176.07:48:02.37#ibcon#first serial, iclass 21, count 0 2006.176.07:48:02.37#ibcon#enter sib2, iclass 21, count 0 2006.176.07:48:02.37#ibcon#flushed, iclass 21, count 0 2006.176.07:48:02.37#ibcon#about to write, iclass 21, count 0 2006.176.07:48:02.37#ibcon#wrote, iclass 21, count 0 2006.176.07:48:02.37#ibcon#about to read 3, iclass 21, count 0 2006.176.07:48:02.39#ibcon#read 3, iclass 21, count 0 2006.176.07:48:02.39#ibcon#about to read 4, iclass 21, count 0 2006.176.07:48:02.39#ibcon#read 4, iclass 21, count 0 2006.176.07:48:02.39#ibcon#about to read 5, iclass 21, count 0 2006.176.07:48:02.39#ibcon#read 5, iclass 21, count 0 2006.176.07:48:02.39#ibcon#about to read 6, iclass 21, count 0 2006.176.07:48:02.39#ibcon#read 6, iclass 21, count 0 2006.176.07:48:02.39#ibcon#end of sib2, iclass 21, count 0 2006.176.07:48:02.39#ibcon#*mode == 0, iclass 21, count 0 2006.176.07:48:02.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.07:48:02.39#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:48:02.39#ibcon#*before write, iclass 21, count 0 2006.176.07:48:02.39#ibcon#enter sib2, iclass 21, count 0 2006.176.07:48:02.39#ibcon#flushed, iclass 21, count 0 2006.176.07:48:02.39#ibcon#about to write, iclass 21, count 0 2006.176.07:48:02.39#ibcon#wrote, iclass 21, count 0 2006.176.07:48:02.39#ibcon#about to read 3, iclass 21, count 0 2006.176.07:48:02.43#ibcon#read 3, iclass 21, count 0 2006.176.07:48:02.43#ibcon#about to read 4, iclass 21, count 0 2006.176.07:48:02.43#ibcon#read 4, iclass 21, count 0 2006.176.07:48:02.43#ibcon#about to read 5, iclass 21, count 0 2006.176.07:48:02.43#ibcon#read 5, iclass 21, count 0 2006.176.07:48:02.43#ibcon#about to read 6, iclass 21, count 0 2006.176.07:48:02.43#ibcon#read 6, iclass 21, count 0 2006.176.07:48:02.43#ibcon#end of sib2, iclass 21, count 0 2006.176.07:48:02.43#ibcon#*after write, iclass 21, count 0 2006.176.07:48:02.43#ibcon#*before return 0, iclass 21, count 0 2006.176.07:48:02.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:48:02.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.07:48:02.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.07:48:02.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.07:48:02.43$vc4f8/vb=6,4 2006.176.07:48:02.43#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.07:48:02.43#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.07:48:02.43#ibcon#ireg 11 cls_cnt 2 2006.176.07:48:02.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:48:02.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:48:02.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:48:02.49#ibcon#enter wrdev, iclass 23, count 2 2006.176.07:48:02.49#ibcon#first serial, iclass 23, count 2 2006.176.07:48:02.49#ibcon#enter sib2, iclass 23, count 2 2006.176.07:48:02.49#ibcon#flushed, iclass 23, count 2 2006.176.07:48:02.49#ibcon#about to write, iclass 23, count 2 2006.176.07:48:02.49#ibcon#wrote, iclass 23, count 2 2006.176.07:48:02.49#ibcon#about to read 3, iclass 23, count 2 2006.176.07:48:02.51#ibcon#read 3, iclass 23, count 2 2006.176.07:48:02.51#ibcon#about to read 4, iclass 23, count 2 2006.176.07:48:02.51#ibcon#read 4, iclass 23, count 2 2006.176.07:48:02.51#ibcon#about to read 5, iclass 23, count 2 2006.176.07:48:02.51#ibcon#read 5, iclass 23, count 2 2006.176.07:48:02.51#ibcon#about to read 6, iclass 23, count 2 2006.176.07:48:02.51#ibcon#read 6, iclass 23, count 2 2006.176.07:48:02.51#ibcon#end of sib2, iclass 23, count 2 2006.176.07:48:02.51#ibcon#*mode == 0, iclass 23, count 2 2006.176.07:48:02.51#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.07:48:02.51#ibcon#[27=AT06-04\r\n] 2006.176.07:48:02.51#ibcon#*before write, iclass 23, count 2 2006.176.07:48:02.51#ibcon#enter sib2, iclass 23, count 2 2006.176.07:48:02.51#ibcon#flushed, iclass 23, count 2 2006.176.07:48:02.51#ibcon#about to write, iclass 23, count 2 2006.176.07:48:02.51#ibcon#wrote, iclass 23, count 2 2006.176.07:48:02.51#ibcon#about to read 3, iclass 23, count 2 2006.176.07:48:02.54#ibcon#read 3, iclass 23, count 2 2006.176.07:48:02.54#ibcon#about to read 4, iclass 23, count 2 2006.176.07:48:02.54#ibcon#read 4, iclass 23, count 2 2006.176.07:48:02.54#ibcon#about to read 5, iclass 23, count 2 2006.176.07:48:02.54#ibcon#read 5, iclass 23, count 2 2006.176.07:48:02.54#ibcon#about to read 6, iclass 23, count 2 2006.176.07:48:02.54#ibcon#read 6, iclass 23, count 2 2006.176.07:48:02.54#ibcon#end of sib2, iclass 23, count 2 2006.176.07:48:02.54#ibcon#*after write, iclass 23, count 2 2006.176.07:48:02.54#ibcon#*before return 0, iclass 23, count 2 2006.176.07:48:02.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:48:02.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.07:48:02.54#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.07:48:02.54#ibcon#ireg 7 cls_cnt 0 2006.176.07:48:02.54#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:48:02.66#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:48:02.66#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:48:02.66#ibcon#enter wrdev, iclass 23, count 0 2006.176.07:48:02.66#ibcon#first serial, iclass 23, count 0 2006.176.07:48:02.66#ibcon#enter sib2, iclass 23, count 0 2006.176.07:48:02.66#ibcon#flushed, iclass 23, count 0 2006.176.07:48:02.66#ibcon#about to write, iclass 23, count 0 2006.176.07:48:02.66#ibcon#wrote, iclass 23, count 0 2006.176.07:48:02.66#ibcon#about to read 3, iclass 23, count 0 2006.176.07:48:02.68#ibcon#read 3, iclass 23, count 0 2006.176.07:48:02.68#ibcon#about to read 4, iclass 23, count 0 2006.176.07:48:02.68#ibcon#read 4, iclass 23, count 0 2006.176.07:48:02.68#ibcon#about to read 5, iclass 23, count 0 2006.176.07:48:02.68#ibcon#read 5, iclass 23, count 0 2006.176.07:48:02.68#ibcon#about to read 6, iclass 23, count 0 2006.176.07:48:02.68#ibcon#read 6, iclass 23, count 0 2006.176.07:48:02.68#ibcon#end of sib2, iclass 23, count 0 2006.176.07:48:02.68#ibcon#*mode == 0, iclass 23, count 0 2006.176.07:48:02.68#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.07:48:02.68#ibcon#[27=USB\r\n] 2006.176.07:48:02.68#ibcon#*before write, iclass 23, count 0 2006.176.07:48:02.68#ibcon#enter sib2, iclass 23, count 0 2006.176.07:48:02.68#ibcon#flushed, iclass 23, count 0 2006.176.07:48:02.68#ibcon#about to write, iclass 23, count 0 2006.176.07:48:02.68#ibcon#wrote, iclass 23, count 0 2006.176.07:48:02.68#ibcon#about to read 3, iclass 23, count 0 2006.176.07:48:02.71#ibcon#read 3, iclass 23, count 0 2006.176.07:48:02.71#ibcon#about to read 4, iclass 23, count 0 2006.176.07:48:02.71#ibcon#read 4, iclass 23, count 0 2006.176.07:48:02.71#ibcon#about to read 5, iclass 23, count 0 2006.176.07:48:02.71#ibcon#read 5, iclass 23, count 0 2006.176.07:48:02.71#ibcon#about to read 6, iclass 23, count 0 2006.176.07:48:02.71#ibcon#read 6, iclass 23, count 0 2006.176.07:48:02.71#ibcon#end of sib2, iclass 23, count 0 2006.176.07:48:02.71#ibcon#*after write, iclass 23, count 0 2006.176.07:48:02.71#ibcon#*before return 0, iclass 23, count 0 2006.176.07:48:02.71#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:48:02.71#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.07:48:02.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.07:48:02.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.07:48:02.71$vc4f8/vabw=wide 2006.176.07:48:02.71#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.07:48:02.71#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.07:48:02.71#ibcon#ireg 8 cls_cnt 0 2006.176.07:48:02.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:48:02.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:48:02.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:48:02.71#ibcon#enter wrdev, iclass 25, count 0 2006.176.07:48:02.71#ibcon#first serial, iclass 25, count 0 2006.176.07:48:02.71#ibcon#enter sib2, iclass 25, count 0 2006.176.07:48:02.71#ibcon#flushed, iclass 25, count 0 2006.176.07:48:02.71#ibcon#about to write, iclass 25, count 0 2006.176.07:48:02.71#ibcon#wrote, iclass 25, count 0 2006.176.07:48:02.71#ibcon#about to read 3, iclass 25, count 0 2006.176.07:48:02.73#ibcon#read 3, iclass 25, count 0 2006.176.07:48:02.73#ibcon#about to read 4, iclass 25, count 0 2006.176.07:48:02.73#ibcon#read 4, iclass 25, count 0 2006.176.07:48:02.73#ibcon#about to read 5, iclass 25, count 0 2006.176.07:48:02.73#ibcon#read 5, iclass 25, count 0 2006.176.07:48:02.73#ibcon#about to read 6, iclass 25, count 0 2006.176.07:48:02.73#ibcon#read 6, iclass 25, count 0 2006.176.07:48:02.73#ibcon#end of sib2, iclass 25, count 0 2006.176.07:48:02.73#ibcon#*mode == 0, iclass 25, count 0 2006.176.07:48:02.73#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.07:48:02.73#ibcon#[25=BW32\r\n] 2006.176.07:48:02.73#ibcon#*before write, iclass 25, count 0 2006.176.07:48:02.73#ibcon#enter sib2, iclass 25, count 0 2006.176.07:48:02.73#ibcon#flushed, iclass 25, count 0 2006.176.07:48:02.73#ibcon#about to write, iclass 25, count 0 2006.176.07:48:02.73#ibcon#wrote, iclass 25, count 0 2006.176.07:48:02.73#ibcon#about to read 3, iclass 25, count 0 2006.176.07:48:02.76#ibcon#read 3, iclass 25, count 0 2006.176.07:48:02.76#ibcon#about to read 4, iclass 25, count 0 2006.176.07:48:02.76#ibcon#read 4, iclass 25, count 0 2006.176.07:48:02.76#ibcon#about to read 5, iclass 25, count 0 2006.176.07:48:02.76#ibcon#read 5, iclass 25, count 0 2006.176.07:48:02.76#ibcon#about to read 6, iclass 25, count 0 2006.176.07:48:02.76#ibcon#read 6, iclass 25, count 0 2006.176.07:48:02.76#ibcon#end of sib2, iclass 25, count 0 2006.176.07:48:02.76#ibcon#*after write, iclass 25, count 0 2006.176.07:48:02.76#ibcon#*before return 0, iclass 25, count 0 2006.176.07:48:02.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:48:02.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.07:48:02.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.07:48:02.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.07:48:02.76$vc4f8/vbbw=wide 2006.176.07:48:02.76#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.07:48:02.76#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.07:48:02.76#ibcon#ireg 8 cls_cnt 0 2006.176.07:48:02.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:48:02.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:48:02.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:48:02.83#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:48:02.83#ibcon#first serial, iclass 27, count 0 2006.176.07:48:02.83#ibcon#enter sib2, iclass 27, count 0 2006.176.07:48:02.83#ibcon#flushed, iclass 27, count 0 2006.176.07:48:02.83#ibcon#about to write, iclass 27, count 0 2006.176.07:48:02.83#ibcon#wrote, iclass 27, count 0 2006.176.07:48:02.83#ibcon#about to read 3, iclass 27, count 0 2006.176.07:48:02.85#ibcon#read 3, iclass 27, count 0 2006.176.07:48:02.85#ibcon#about to read 4, iclass 27, count 0 2006.176.07:48:02.85#ibcon#read 4, iclass 27, count 0 2006.176.07:48:02.85#ibcon#about to read 5, iclass 27, count 0 2006.176.07:48:02.85#ibcon#read 5, iclass 27, count 0 2006.176.07:48:02.85#ibcon#about to read 6, iclass 27, count 0 2006.176.07:48:02.85#ibcon#read 6, iclass 27, count 0 2006.176.07:48:02.85#ibcon#end of sib2, iclass 27, count 0 2006.176.07:48:02.85#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:48:02.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:48:02.85#ibcon#[27=BW32\r\n] 2006.176.07:48:02.85#ibcon#*before write, iclass 27, count 0 2006.176.07:48:02.85#ibcon#enter sib2, iclass 27, count 0 2006.176.07:48:02.85#ibcon#flushed, iclass 27, count 0 2006.176.07:48:02.85#ibcon#about to write, iclass 27, count 0 2006.176.07:48:02.85#ibcon#wrote, iclass 27, count 0 2006.176.07:48:02.85#ibcon#about to read 3, iclass 27, count 0 2006.176.07:48:02.88#ibcon#read 3, iclass 27, count 0 2006.176.07:48:02.88#ibcon#about to read 4, iclass 27, count 0 2006.176.07:48:02.88#ibcon#read 4, iclass 27, count 0 2006.176.07:48:02.88#ibcon#about to read 5, iclass 27, count 0 2006.176.07:48:02.88#ibcon#read 5, iclass 27, count 0 2006.176.07:48:02.88#ibcon#about to read 6, iclass 27, count 0 2006.176.07:48:02.88#ibcon#read 6, iclass 27, count 0 2006.176.07:48:02.88#ibcon#end of sib2, iclass 27, count 0 2006.176.07:48:02.88#ibcon#*after write, iclass 27, count 0 2006.176.07:48:02.88#ibcon#*before return 0, iclass 27, count 0 2006.176.07:48:02.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:48:02.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:48:02.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:48:02.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:48:02.88$4f8m12a/ifd4f 2006.176.07:48:02.88$ifd4f/lo= 2006.176.07:48:02.88$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:48:02.88$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:48:02.88$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:48:02.88$ifd4f/patch= 2006.176.07:48:02.88$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:48:02.88$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:48:02.88$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:48:02.88$4f8m12a/"form=m,16.000,1:2 2006.176.07:48:02.88$4f8m12a/"tpicd 2006.176.07:48:02.88$4f8m12a/echo=off 2006.176.07:48:02.88$4f8m12a/xlog=off 2006.176.07:48:02.88:!2006.176.07:48:30 2006.176.07:48:15.14#trakl#Source acquired 2006.176.07:48:15.14#flagr#flagr/antenna,acquired 2006.176.07:48:30.00:preob 2006.176.07:48:31.14/onsource/TRACKING 2006.176.07:48:31.14:!2006.176.07:48:40 2006.176.07:48:40.00:data_valid=on 2006.176.07:48:40.00:midob 2006.176.07:48:40.14/onsource/TRACKING 2006.176.07:48:40.14/wx/23.89,1008.4,91 2006.176.07:48:40.25/cable/+6.4920E-03 2006.176.07:48:41.34/va/01,08,usb,yes,28,30 2006.176.07:48:41.34/va/02,07,usb,yes,28,30 2006.176.07:48:41.34/va/03,06,usb,yes,30,30 2006.176.07:48:41.34/va/04,07,usb,yes,29,31 2006.176.07:48:41.34/va/05,07,usb,yes,30,32 2006.176.07:48:41.34/va/06,06,usb,yes,30,29 2006.176.07:48:41.34/va/07,06,usb,yes,30,30 2006.176.07:48:41.34/va/08,06,usb,yes,32,32 2006.176.07:48:41.57/valo/01,532.99,yes,locked 2006.176.07:48:41.57/valo/02,572.99,yes,locked 2006.176.07:48:41.57/valo/03,672.99,yes,locked 2006.176.07:48:41.57/valo/04,832.99,yes,locked 2006.176.07:48:41.57/valo/05,652.99,yes,locked 2006.176.07:48:41.57/valo/06,772.99,yes,locked 2006.176.07:48:41.57/valo/07,832.99,yes,locked 2006.176.07:48:41.57/valo/08,852.99,yes,locked 2006.176.07:48:42.66/vb/01,04,usb,yes,28,27 2006.176.07:48:42.66/vb/02,04,usb,yes,30,31 2006.176.07:48:42.66/vb/03,04,usb,yes,27,30 2006.176.07:48:42.66/vb/04,04,usb,yes,27,27 2006.176.07:48:42.66/vb/05,04,usb,yes,26,30 2006.176.07:48:42.66/vb/06,04,usb,yes,27,30 2006.176.07:48:42.66/vb/07,04,usb,yes,29,29 2006.176.07:48:42.66/vb/08,04,usb,yes,27,30 2006.176.07:48:42.89/vblo/01,632.99,yes,locked 2006.176.07:48:42.89/vblo/02,640.99,yes,locked 2006.176.07:48:42.89/vblo/03,656.99,yes,locked 2006.176.07:48:42.89/vblo/04,712.99,yes,locked 2006.176.07:48:42.89/vblo/05,744.99,yes,locked 2006.176.07:48:42.89/vblo/06,752.99,yes,locked 2006.176.07:48:42.89/vblo/07,734.99,yes,locked 2006.176.07:48:42.89/vblo/08,744.99,yes,locked 2006.176.07:48:43.04/vabw/8 2006.176.07:48:43.19/vbbw/8 2006.176.07:48:43.28/xfe/off,on,15.2 2006.176.07:48:43.66/ifatt/23,28,28,28 2006.176.07:48:44.07/fmout-gps/S +3.74E-07 2006.176.07:48:44.14:!2006.176.07:49:40 2006.176.07:49:40.00:data_valid=off 2006.176.07:49:40.00:postob 2006.176.07:49:40.06/cable/+6.4928E-03 2006.176.07:49:40.06/wx/23.88,1008.4,92 2006.176.07:49:41.08/fmout-gps/S +3.73E-07 2006.176.07:49:41.08:scan_name=176-0750,k06176,60 2006.176.07:49:41.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.176.07:49:41.13#flagr#flagr/antenna,new-source 2006.176.07:49:42.13:checkk5 2006.176.07:49:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:49:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:49:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:49:43.70/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:49:44.07/chk_obsdata//k5ts1/T1760748??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:49:44.44/chk_obsdata//k5ts2/T1760748??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:49:44.80/chk_obsdata//k5ts3/T1760748??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:49:45.17/chk_obsdata//k5ts4/T1760748??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:49:45.86/k5log//k5ts1_log_newline 2006.176.07:49:46.56/k5log//k5ts2_log_newline 2006.176.07:49:47.24/k5log//k5ts3_log_newline 2006.176.07:49:47.93/k5log//k5ts4_log_newline 2006.176.07:49:47.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:49:47.95:4f8m12a=1 2006.176.07:49:47.95$4f8m12a/echo=on 2006.176.07:49:47.95$4f8m12a/pcalon 2006.176.07:49:47.95$pcalon/"no phase cal control is implemented here 2006.176.07:49:47.95$4f8m12a/"tpicd=stop 2006.176.07:49:47.95$4f8m12a/vc4f8 2006.176.07:49:47.95$vc4f8/valo=1,532.99 2006.176.07:49:47.96#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.07:49:47.96#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.07:49:47.96#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:47.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:47.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:47.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:47.96#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:49:47.96#ibcon#first serial, iclass 38, count 0 2006.176.07:49:47.96#ibcon#enter sib2, iclass 38, count 0 2006.176.07:49:47.96#ibcon#flushed, iclass 38, count 0 2006.176.07:49:47.96#ibcon#about to write, iclass 38, count 0 2006.176.07:49:47.96#ibcon#wrote, iclass 38, count 0 2006.176.07:49:47.96#ibcon#about to read 3, iclass 38, count 0 2006.176.07:49:48.00#ibcon#read 3, iclass 38, count 0 2006.176.07:49:48.00#ibcon#about to read 4, iclass 38, count 0 2006.176.07:49:48.00#ibcon#read 4, iclass 38, count 0 2006.176.07:49:48.00#ibcon#about to read 5, iclass 38, count 0 2006.176.07:49:48.00#ibcon#read 5, iclass 38, count 0 2006.176.07:49:48.00#ibcon#about to read 6, iclass 38, count 0 2006.176.07:49:48.00#ibcon#read 6, iclass 38, count 0 2006.176.07:49:48.00#ibcon#end of sib2, iclass 38, count 0 2006.176.07:49:48.00#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:49:48.00#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:49:48.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:49:48.00#ibcon#*before write, iclass 38, count 0 2006.176.07:49:48.00#ibcon#enter sib2, iclass 38, count 0 2006.176.07:49:48.00#ibcon#flushed, iclass 38, count 0 2006.176.07:49:48.00#ibcon#about to write, iclass 38, count 0 2006.176.07:49:48.00#ibcon#wrote, iclass 38, count 0 2006.176.07:49:48.00#ibcon#about to read 3, iclass 38, count 0 2006.176.07:49:48.05#ibcon#read 3, iclass 38, count 0 2006.176.07:49:48.05#ibcon#about to read 4, iclass 38, count 0 2006.176.07:49:48.05#ibcon#read 4, iclass 38, count 0 2006.176.07:49:48.05#ibcon#about to read 5, iclass 38, count 0 2006.176.07:49:48.05#ibcon#read 5, iclass 38, count 0 2006.176.07:49:48.05#ibcon#about to read 6, iclass 38, count 0 2006.176.07:49:48.05#ibcon#read 6, iclass 38, count 0 2006.176.07:49:48.05#ibcon#end of sib2, iclass 38, count 0 2006.176.07:49:48.05#ibcon#*after write, iclass 38, count 0 2006.176.07:49:48.05#ibcon#*before return 0, iclass 38, count 0 2006.176.07:49:48.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:48.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:48.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:49:48.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:49:48.05$vc4f8/va=1,8 2006.176.07:49:48.05#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.07:49:48.05#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.07:49:48.05#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:48.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:48.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:48.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:48.05#ibcon#enter wrdev, iclass 40, count 2 2006.176.07:49:48.05#ibcon#first serial, iclass 40, count 2 2006.176.07:49:48.05#ibcon#enter sib2, iclass 40, count 2 2006.176.07:49:48.05#ibcon#flushed, iclass 40, count 2 2006.176.07:49:48.05#ibcon#about to write, iclass 40, count 2 2006.176.07:49:48.05#ibcon#wrote, iclass 40, count 2 2006.176.07:49:48.05#ibcon#about to read 3, iclass 40, count 2 2006.176.07:49:48.07#ibcon#read 3, iclass 40, count 2 2006.176.07:49:48.07#ibcon#about to read 4, iclass 40, count 2 2006.176.07:49:48.07#ibcon#read 4, iclass 40, count 2 2006.176.07:49:48.07#ibcon#about to read 5, iclass 40, count 2 2006.176.07:49:48.07#ibcon#read 5, iclass 40, count 2 2006.176.07:49:48.07#ibcon#about to read 6, iclass 40, count 2 2006.176.07:49:48.07#ibcon#read 6, iclass 40, count 2 2006.176.07:49:48.07#ibcon#end of sib2, iclass 40, count 2 2006.176.07:49:48.07#ibcon#*mode == 0, iclass 40, count 2 2006.176.07:49:48.07#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.07:49:48.07#ibcon#[25=AT01-08\r\n] 2006.176.07:49:48.07#ibcon#*before write, iclass 40, count 2 2006.176.07:49:48.07#ibcon#enter sib2, iclass 40, count 2 2006.176.07:49:48.07#ibcon#flushed, iclass 40, count 2 2006.176.07:49:48.07#ibcon#about to write, iclass 40, count 2 2006.176.07:49:48.07#ibcon#wrote, iclass 40, count 2 2006.176.07:49:48.07#ibcon#about to read 3, iclass 40, count 2 2006.176.07:49:48.10#ibcon#read 3, iclass 40, count 2 2006.176.07:49:48.10#ibcon#about to read 4, iclass 40, count 2 2006.176.07:49:48.10#ibcon#read 4, iclass 40, count 2 2006.176.07:49:48.10#ibcon#about to read 5, iclass 40, count 2 2006.176.07:49:48.10#ibcon#read 5, iclass 40, count 2 2006.176.07:49:48.10#ibcon#about to read 6, iclass 40, count 2 2006.176.07:49:48.10#ibcon#read 6, iclass 40, count 2 2006.176.07:49:48.10#ibcon#end of sib2, iclass 40, count 2 2006.176.07:49:48.10#ibcon#*after write, iclass 40, count 2 2006.176.07:49:48.10#ibcon#*before return 0, iclass 40, count 2 2006.176.07:49:48.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:48.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:48.10#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.07:49:48.10#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:48.10#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:48.22#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:48.22#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:48.22#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:49:48.22#ibcon#first serial, iclass 40, count 0 2006.176.07:49:48.22#ibcon#enter sib2, iclass 40, count 0 2006.176.07:49:48.22#ibcon#flushed, iclass 40, count 0 2006.176.07:49:48.22#ibcon#about to write, iclass 40, count 0 2006.176.07:49:48.22#ibcon#wrote, iclass 40, count 0 2006.176.07:49:48.22#ibcon#about to read 3, iclass 40, count 0 2006.176.07:49:48.24#ibcon#read 3, iclass 40, count 0 2006.176.07:49:48.24#ibcon#about to read 4, iclass 40, count 0 2006.176.07:49:48.24#ibcon#read 4, iclass 40, count 0 2006.176.07:49:48.24#ibcon#about to read 5, iclass 40, count 0 2006.176.07:49:48.24#ibcon#read 5, iclass 40, count 0 2006.176.07:49:48.24#ibcon#about to read 6, iclass 40, count 0 2006.176.07:49:48.24#ibcon#read 6, iclass 40, count 0 2006.176.07:49:48.24#ibcon#end of sib2, iclass 40, count 0 2006.176.07:49:48.24#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:49:48.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:49:48.24#ibcon#[25=USB\r\n] 2006.176.07:49:48.24#ibcon#*before write, iclass 40, count 0 2006.176.07:49:48.24#ibcon#enter sib2, iclass 40, count 0 2006.176.07:49:48.24#ibcon#flushed, iclass 40, count 0 2006.176.07:49:48.24#ibcon#about to write, iclass 40, count 0 2006.176.07:49:48.24#ibcon#wrote, iclass 40, count 0 2006.176.07:49:48.24#ibcon#about to read 3, iclass 40, count 0 2006.176.07:49:48.27#ibcon#read 3, iclass 40, count 0 2006.176.07:49:48.27#ibcon#about to read 4, iclass 40, count 0 2006.176.07:49:48.27#ibcon#read 4, iclass 40, count 0 2006.176.07:49:48.27#ibcon#about to read 5, iclass 40, count 0 2006.176.07:49:48.27#ibcon#read 5, iclass 40, count 0 2006.176.07:49:48.27#ibcon#about to read 6, iclass 40, count 0 2006.176.07:49:48.27#ibcon#read 6, iclass 40, count 0 2006.176.07:49:48.27#ibcon#end of sib2, iclass 40, count 0 2006.176.07:49:48.27#ibcon#*after write, iclass 40, count 0 2006.176.07:49:48.27#ibcon#*before return 0, iclass 40, count 0 2006.176.07:49:48.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:48.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:48.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:49:48.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:49:48.27$vc4f8/valo=2,572.99 2006.176.07:49:48.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.07:49:48.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.07:49:48.27#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:48.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:48.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:48.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:48.27#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:49:48.27#ibcon#first serial, iclass 4, count 0 2006.176.07:49:48.27#ibcon#enter sib2, iclass 4, count 0 2006.176.07:49:48.27#ibcon#flushed, iclass 4, count 0 2006.176.07:49:48.27#ibcon#about to write, iclass 4, count 0 2006.176.07:49:48.27#ibcon#wrote, iclass 4, count 0 2006.176.07:49:48.27#ibcon#about to read 3, iclass 4, count 0 2006.176.07:49:48.29#ibcon#read 3, iclass 4, count 0 2006.176.07:49:48.29#ibcon#about to read 4, iclass 4, count 0 2006.176.07:49:48.29#ibcon#read 4, iclass 4, count 0 2006.176.07:49:48.29#ibcon#about to read 5, iclass 4, count 0 2006.176.07:49:48.29#ibcon#read 5, iclass 4, count 0 2006.176.07:49:48.29#ibcon#about to read 6, iclass 4, count 0 2006.176.07:49:48.29#ibcon#read 6, iclass 4, count 0 2006.176.07:49:48.29#ibcon#end of sib2, iclass 4, count 0 2006.176.07:49:48.29#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:49:48.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:49:48.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:49:48.29#ibcon#*before write, iclass 4, count 0 2006.176.07:49:48.29#ibcon#enter sib2, iclass 4, count 0 2006.176.07:49:48.29#ibcon#flushed, iclass 4, count 0 2006.176.07:49:48.29#ibcon#about to write, iclass 4, count 0 2006.176.07:49:48.29#ibcon#wrote, iclass 4, count 0 2006.176.07:49:48.29#ibcon#about to read 3, iclass 4, count 0 2006.176.07:49:48.33#ibcon#read 3, iclass 4, count 0 2006.176.07:49:48.33#ibcon#about to read 4, iclass 4, count 0 2006.176.07:49:48.33#ibcon#read 4, iclass 4, count 0 2006.176.07:49:48.33#ibcon#about to read 5, iclass 4, count 0 2006.176.07:49:48.33#ibcon#read 5, iclass 4, count 0 2006.176.07:49:48.33#ibcon#about to read 6, iclass 4, count 0 2006.176.07:49:48.33#ibcon#read 6, iclass 4, count 0 2006.176.07:49:48.33#ibcon#end of sib2, iclass 4, count 0 2006.176.07:49:48.33#ibcon#*after write, iclass 4, count 0 2006.176.07:49:48.33#ibcon#*before return 0, iclass 4, count 0 2006.176.07:49:48.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:48.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:48.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:49:48.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:49:48.33$vc4f8/va=2,7 2006.176.07:49:48.33#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.07:49:48.33#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.07:49:48.33#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:48.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:48.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:48.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:48.39#ibcon#enter wrdev, iclass 6, count 2 2006.176.07:49:48.39#ibcon#first serial, iclass 6, count 2 2006.176.07:49:48.39#ibcon#enter sib2, iclass 6, count 2 2006.176.07:49:48.39#ibcon#flushed, iclass 6, count 2 2006.176.07:49:48.39#ibcon#about to write, iclass 6, count 2 2006.176.07:49:48.39#ibcon#wrote, iclass 6, count 2 2006.176.07:49:48.39#ibcon#about to read 3, iclass 6, count 2 2006.176.07:49:48.41#ibcon#read 3, iclass 6, count 2 2006.176.07:49:48.41#ibcon#about to read 4, iclass 6, count 2 2006.176.07:49:48.41#ibcon#read 4, iclass 6, count 2 2006.176.07:49:48.41#ibcon#about to read 5, iclass 6, count 2 2006.176.07:49:48.41#ibcon#read 5, iclass 6, count 2 2006.176.07:49:48.41#ibcon#about to read 6, iclass 6, count 2 2006.176.07:49:48.41#ibcon#read 6, iclass 6, count 2 2006.176.07:49:48.41#ibcon#end of sib2, iclass 6, count 2 2006.176.07:49:48.41#ibcon#*mode == 0, iclass 6, count 2 2006.176.07:49:48.41#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.07:49:48.41#ibcon#[25=AT02-07\r\n] 2006.176.07:49:48.41#ibcon#*before write, iclass 6, count 2 2006.176.07:49:48.41#ibcon#enter sib2, iclass 6, count 2 2006.176.07:49:48.41#ibcon#flushed, iclass 6, count 2 2006.176.07:49:48.41#ibcon#about to write, iclass 6, count 2 2006.176.07:49:48.41#ibcon#wrote, iclass 6, count 2 2006.176.07:49:48.41#ibcon#about to read 3, iclass 6, count 2 2006.176.07:49:48.44#ibcon#read 3, iclass 6, count 2 2006.176.07:49:48.44#ibcon#about to read 4, iclass 6, count 2 2006.176.07:49:48.44#ibcon#read 4, iclass 6, count 2 2006.176.07:49:48.44#ibcon#about to read 5, iclass 6, count 2 2006.176.07:49:48.44#ibcon#read 5, iclass 6, count 2 2006.176.07:49:48.44#ibcon#about to read 6, iclass 6, count 2 2006.176.07:49:48.44#ibcon#read 6, iclass 6, count 2 2006.176.07:49:48.44#ibcon#end of sib2, iclass 6, count 2 2006.176.07:49:48.44#ibcon#*after write, iclass 6, count 2 2006.176.07:49:48.44#ibcon#*before return 0, iclass 6, count 2 2006.176.07:49:48.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:48.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:48.44#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.07:49:48.44#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:48.44#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:48.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:48.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:48.56#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:49:48.56#ibcon#first serial, iclass 6, count 0 2006.176.07:49:48.56#ibcon#enter sib2, iclass 6, count 0 2006.176.07:49:48.56#ibcon#flushed, iclass 6, count 0 2006.176.07:49:48.56#ibcon#about to write, iclass 6, count 0 2006.176.07:49:48.56#ibcon#wrote, iclass 6, count 0 2006.176.07:49:48.56#ibcon#about to read 3, iclass 6, count 0 2006.176.07:49:48.58#ibcon#read 3, iclass 6, count 0 2006.176.07:49:48.58#ibcon#about to read 4, iclass 6, count 0 2006.176.07:49:48.58#ibcon#read 4, iclass 6, count 0 2006.176.07:49:48.58#ibcon#about to read 5, iclass 6, count 0 2006.176.07:49:48.58#ibcon#read 5, iclass 6, count 0 2006.176.07:49:48.58#ibcon#about to read 6, iclass 6, count 0 2006.176.07:49:48.58#ibcon#read 6, iclass 6, count 0 2006.176.07:49:48.58#ibcon#end of sib2, iclass 6, count 0 2006.176.07:49:48.58#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:49:48.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:49:48.58#ibcon#[25=USB\r\n] 2006.176.07:49:48.58#ibcon#*before write, iclass 6, count 0 2006.176.07:49:48.58#ibcon#enter sib2, iclass 6, count 0 2006.176.07:49:48.58#ibcon#flushed, iclass 6, count 0 2006.176.07:49:48.58#ibcon#about to write, iclass 6, count 0 2006.176.07:49:48.58#ibcon#wrote, iclass 6, count 0 2006.176.07:49:48.58#ibcon#about to read 3, iclass 6, count 0 2006.176.07:49:48.61#ibcon#read 3, iclass 6, count 0 2006.176.07:49:48.61#ibcon#about to read 4, iclass 6, count 0 2006.176.07:49:48.61#ibcon#read 4, iclass 6, count 0 2006.176.07:49:48.61#ibcon#about to read 5, iclass 6, count 0 2006.176.07:49:48.61#ibcon#read 5, iclass 6, count 0 2006.176.07:49:48.61#ibcon#about to read 6, iclass 6, count 0 2006.176.07:49:48.61#ibcon#read 6, iclass 6, count 0 2006.176.07:49:48.61#ibcon#end of sib2, iclass 6, count 0 2006.176.07:49:48.61#ibcon#*after write, iclass 6, count 0 2006.176.07:49:48.61#ibcon#*before return 0, iclass 6, count 0 2006.176.07:49:48.61#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:48.61#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:48.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:49:48.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:49:48.61$vc4f8/valo=3,672.99 2006.176.07:49:48.61#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.07:49:48.61#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.07:49:48.61#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:48.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:48.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:48.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:48.61#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:49:48.61#ibcon#first serial, iclass 10, count 0 2006.176.07:49:48.61#ibcon#enter sib2, iclass 10, count 0 2006.176.07:49:48.61#ibcon#flushed, iclass 10, count 0 2006.176.07:49:48.61#ibcon#about to write, iclass 10, count 0 2006.176.07:49:48.61#ibcon#wrote, iclass 10, count 0 2006.176.07:49:48.61#ibcon#about to read 3, iclass 10, count 0 2006.176.07:49:48.63#ibcon#read 3, iclass 10, count 0 2006.176.07:49:48.63#ibcon#about to read 4, iclass 10, count 0 2006.176.07:49:48.63#ibcon#read 4, iclass 10, count 0 2006.176.07:49:48.63#ibcon#about to read 5, iclass 10, count 0 2006.176.07:49:48.63#ibcon#read 5, iclass 10, count 0 2006.176.07:49:48.63#ibcon#about to read 6, iclass 10, count 0 2006.176.07:49:48.63#ibcon#read 6, iclass 10, count 0 2006.176.07:49:48.63#ibcon#end of sib2, iclass 10, count 0 2006.176.07:49:48.63#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:49:48.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:49:48.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:49:48.63#ibcon#*before write, iclass 10, count 0 2006.176.07:49:48.63#ibcon#enter sib2, iclass 10, count 0 2006.176.07:49:48.63#ibcon#flushed, iclass 10, count 0 2006.176.07:49:48.63#ibcon#about to write, iclass 10, count 0 2006.176.07:49:48.63#ibcon#wrote, iclass 10, count 0 2006.176.07:49:48.63#ibcon#about to read 3, iclass 10, count 0 2006.176.07:49:48.67#ibcon#read 3, iclass 10, count 0 2006.176.07:49:48.67#ibcon#about to read 4, iclass 10, count 0 2006.176.07:49:48.67#ibcon#read 4, iclass 10, count 0 2006.176.07:49:48.67#ibcon#about to read 5, iclass 10, count 0 2006.176.07:49:48.67#ibcon#read 5, iclass 10, count 0 2006.176.07:49:48.67#ibcon#about to read 6, iclass 10, count 0 2006.176.07:49:48.67#ibcon#read 6, iclass 10, count 0 2006.176.07:49:48.67#ibcon#end of sib2, iclass 10, count 0 2006.176.07:49:48.67#ibcon#*after write, iclass 10, count 0 2006.176.07:49:48.67#ibcon#*before return 0, iclass 10, count 0 2006.176.07:49:48.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:48.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:48.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:49:48.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:49:48.67$vc4f8/va=3,6 2006.176.07:49:48.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.07:49:48.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.07:49:48.67#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:48.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:48.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:48.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:48.73#ibcon#enter wrdev, iclass 12, count 2 2006.176.07:49:48.73#ibcon#first serial, iclass 12, count 2 2006.176.07:49:48.73#ibcon#enter sib2, iclass 12, count 2 2006.176.07:49:48.73#ibcon#flushed, iclass 12, count 2 2006.176.07:49:48.73#ibcon#about to write, iclass 12, count 2 2006.176.07:49:48.73#ibcon#wrote, iclass 12, count 2 2006.176.07:49:48.73#ibcon#about to read 3, iclass 12, count 2 2006.176.07:49:48.75#ibcon#read 3, iclass 12, count 2 2006.176.07:49:48.75#ibcon#about to read 4, iclass 12, count 2 2006.176.07:49:48.75#ibcon#read 4, iclass 12, count 2 2006.176.07:49:48.75#ibcon#about to read 5, iclass 12, count 2 2006.176.07:49:48.75#ibcon#read 5, iclass 12, count 2 2006.176.07:49:48.75#ibcon#about to read 6, iclass 12, count 2 2006.176.07:49:48.75#ibcon#read 6, iclass 12, count 2 2006.176.07:49:48.75#ibcon#end of sib2, iclass 12, count 2 2006.176.07:49:48.75#ibcon#*mode == 0, iclass 12, count 2 2006.176.07:49:48.75#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.07:49:48.75#ibcon#[25=AT03-06\r\n] 2006.176.07:49:48.75#ibcon#*before write, iclass 12, count 2 2006.176.07:49:48.75#ibcon#enter sib2, iclass 12, count 2 2006.176.07:49:48.75#ibcon#flushed, iclass 12, count 2 2006.176.07:49:48.75#ibcon#about to write, iclass 12, count 2 2006.176.07:49:48.75#ibcon#wrote, iclass 12, count 2 2006.176.07:49:48.75#ibcon#about to read 3, iclass 12, count 2 2006.176.07:49:48.79#ibcon#read 3, iclass 12, count 2 2006.176.07:49:48.79#ibcon#about to read 4, iclass 12, count 2 2006.176.07:49:48.79#ibcon#read 4, iclass 12, count 2 2006.176.07:49:48.79#ibcon#about to read 5, iclass 12, count 2 2006.176.07:49:48.79#ibcon#read 5, iclass 12, count 2 2006.176.07:49:48.79#ibcon#about to read 6, iclass 12, count 2 2006.176.07:49:48.79#ibcon#read 6, iclass 12, count 2 2006.176.07:49:48.79#ibcon#end of sib2, iclass 12, count 2 2006.176.07:49:48.79#ibcon#*after write, iclass 12, count 2 2006.176.07:49:48.79#ibcon#*before return 0, iclass 12, count 2 2006.176.07:49:48.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:48.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:48.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.07:49:48.79#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:48.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:48.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:48.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:48.91#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:49:48.91#ibcon#first serial, iclass 12, count 0 2006.176.07:49:48.91#ibcon#enter sib2, iclass 12, count 0 2006.176.07:49:48.91#ibcon#flushed, iclass 12, count 0 2006.176.07:49:48.91#ibcon#about to write, iclass 12, count 0 2006.176.07:49:48.91#ibcon#wrote, iclass 12, count 0 2006.176.07:49:48.91#ibcon#about to read 3, iclass 12, count 0 2006.176.07:49:48.93#ibcon#read 3, iclass 12, count 0 2006.176.07:49:48.93#ibcon#about to read 4, iclass 12, count 0 2006.176.07:49:48.93#ibcon#read 4, iclass 12, count 0 2006.176.07:49:48.93#ibcon#about to read 5, iclass 12, count 0 2006.176.07:49:48.93#ibcon#read 5, iclass 12, count 0 2006.176.07:49:48.93#ibcon#about to read 6, iclass 12, count 0 2006.176.07:49:48.93#ibcon#read 6, iclass 12, count 0 2006.176.07:49:48.93#ibcon#end of sib2, iclass 12, count 0 2006.176.07:49:48.93#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:49:48.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:49:48.93#ibcon#[25=USB\r\n] 2006.176.07:49:48.93#ibcon#*before write, iclass 12, count 0 2006.176.07:49:48.93#ibcon#enter sib2, iclass 12, count 0 2006.176.07:49:48.93#ibcon#flushed, iclass 12, count 0 2006.176.07:49:48.93#ibcon#about to write, iclass 12, count 0 2006.176.07:49:48.93#ibcon#wrote, iclass 12, count 0 2006.176.07:49:48.93#ibcon#about to read 3, iclass 12, count 0 2006.176.07:49:48.96#ibcon#read 3, iclass 12, count 0 2006.176.07:49:48.96#ibcon#about to read 4, iclass 12, count 0 2006.176.07:49:48.96#ibcon#read 4, iclass 12, count 0 2006.176.07:49:48.96#ibcon#about to read 5, iclass 12, count 0 2006.176.07:49:48.96#ibcon#read 5, iclass 12, count 0 2006.176.07:49:48.96#ibcon#about to read 6, iclass 12, count 0 2006.176.07:49:48.96#ibcon#read 6, iclass 12, count 0 2006.176.07:49:48.96#ibcon#end of sib2, iclass 12, count 0 2006.176.07:49:48.96#ibcon#*after write, iclass 12, count 0 2006.176.07:49:48.96#ibcon#*before return 0, iclass 12, count 0 2006.176.07:49:48.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:48.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:48.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:49:48.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:49:48.96$vc4f8/valo=4,832.99 2006.176.07:49:48.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.07:49:48.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.07:49:48.96#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:48.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:48.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:48.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:48.96#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:49:48.96#ibcon#first serial, iclass 14, count 0 2006.176.07:49:48.96#ibcon#enter sib2, iclass 14, count 0 2006.176.07:49:48.96#ibcon#flushed, iclass 14, count 0 2006.176.07:49:48.96#ibcon#about to write, iclass 14, count 0 2006.176.07:49:48.96#ibcon#wrote, iclass 14, count 0 2006.176.07:49:48.96#ibcon#about to read 3, iclass 14, count 0 2006.176.07:49:48.98#ibcon#read 3, iclass 14, count 0 2006.176.07:49:48.98#ibcon#about to read 4, iclass 14, count 0 2006.176.07:49:48.98#ibcon#read 4, iclass 14, count 0 2006.176.07:49:48.98#ibcon#about to read 5, iclass 14, count 0 2006.176.07:49:48.98#ibcon#read 5, iclass 14, count 0 2006.176.07:49:48.98#ibcon#about to read 6, iclass 14, count 0 2006.176.07:49:48.98#ibcon#read 6, iclass 14, count 0 2006.176.07:49:48.98#ibcon#end of sib2, iclass 14, count 0 2006.176.07:49:48.98#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:49:48.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:49:48.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:49:48.98#ibcon#*before write, iclass 14, count 0 2006.176.07:49:48.98#ibcon#enter sib2, iclass 14, count 0 2006.176.07:49:48.98#ibcon#flushed, iclass 14, count 0 2006.176.07:49:48.98#ibcon#about to write, iclass 14, count 0 2006.176.07:49:48.98#ibcon#wrote, iclass 14, count 0 2006.176.07:49:48.98#ibcon#about to read 3, iclass 14, count 0 2006.176.07:49:49.02#ibcon#read 3, iclass 14, count 0 2006.176.07:49:49.02#ibcon#about to read 4, iclass 14, count 0 2006.176.07:49:49.02#ibcon#read 4, iclass 14, count 0 2006.176.07:49:49.02#ibcon#about to read 5, iclass 14, count 0 2006.176.07:49:49.02#ibcon#read 5, iclass 14, count 0 2006.176.07:49:49.02#ibcon#about to read 6, iclass 14, count 0 2006.176.07:49:49.02#ibcon#read 6, iclass 14, count 0 2006.176.07:49:49.02#ibcon#end of sib2, iclass 14, count 0 2006.176.07:49:49.02#ibcon#*after write, iclass 14, count 0 2006.176.07:49:49.02#ibcon#*before return 0, iclass 14, count 0 2006.176.07:49:49.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:49.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:49.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:49:49.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:49:49.02$vc4f8/va=4,7 2006.176.07:49:49.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.07:49:49.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.07:49:49.02#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:49.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:49.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:49.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:49.08#ibcon#enter wrdev, iclass 16, count 2 2006.176.07:49:49.08#ibcon#first serial, iclass 16, count 2 2006.176.07:49:49.08#ibcon#enter sib2, iclass 16, count 2 2006.176.07:49:49.08#ibcon#flushed, iclass 16, count 2 2006.176.07:49:49.08#ibcon#about to write, iclass 16, count 2 2006.176.07:49:49.08#ibcon#wrote, iclass 16, count 2 2006.176.07:49:49.08#ibcon#about to read 3, iclass 16, count 2 2006.176.07:49:49.10#ibcon#read 3, iclass 16, count 2 2006.176.07:49:49.10#ibcon#about to read 4, iclass 16, count 2 2006.176.07:49:49.10#ibcon#read 4, iclass 16, count 2 2006.176.07:49:49.10#ibcon#about to read 5, iclass 16, count 2 2006.176.07:49:49.10#ibcon#read 5, iclass 16, count 2 2006.176.07:49:49.10#ibcon#about to read 6, iclass 16, count 2 2006.176.07:49:49.10#ibcon#read 6, iclass 16, count 2 2006.176.07:49:49.10#ibcon#end of sib2, iclass 16, count 2 2006.176.07:49:49.10#ibcon#*mode == 0, iclass 16, count 2 2006.176.07:49:49.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.07:49:49.10#ibcon#[25=AT04-07\r\n] 2006.176.07:49:49.10#ibcon#*before write, iclass 16, count 2 2006.176.07:49:49.10#ibcon#enter sib2, iclass 16, count 2 2006.176.07:49:49.10#ibcon#flushed, iclass 16, count 2 2006.176.07:49:49.10#ibcon#about to write, iclass 16, count 2 2006.176.07:49:49.10#ibcon#wrote, iclass 16, count 2 2006.176.07:49:49.10#ibcon#about to read 3, iclass 16, count 2 2006.176.07:49:49.13#ibcon#read 3, iclass 16, count 2 2006.176.07:49:49.13#ibcon#about to read 4, iclass 16, count 2 2006.176.07:49:49.13#ibcon#read 4, iclass 16, count 2 2006.176.07:49:49.13#ibcon#about to read 5, iclass 16, count 2 2006.176.07:49:49.13#ibcon#read 5, iclass 16, count 2 2006.176.07:49:49.13#ibcon#about to read 6, iclass 16, count 2 2006.176.07:49:49.13#ibcon#read 6, iclass 16, count 2 2006.176.07:49:49.13#ibcon#end of sib2, iclass 16, count 2 2006.176.07:49:49.13#ibcon#*after write, iclass 16, count 2 2006.176.07:49:49.13#ibcon#*before return 0, iclass 16, count 2 2006.176.07:49:49.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:49.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:49.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.07:49:49.13#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:49.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:49.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:49.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:49.25#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:49:49.25#ibcon#first serial, iclass 16, count 0 2006.176.07:49:49.25#ibcon#enter sib2, iclass 16, count 0 2006.176.07:49:49.25#ibcon#flushed, iclass 16, count 0 2006.176.07:49:49.25#ibcon#about to write, iclass 16, count 0 2006.176.07:49:49.25#ibcon#wrote, iclass 16, count 0 2006.176.07:49:49.25#ibcon#about to read 3, iclass 16, count 0 2006.176.07:49:49.27#ibcon#read 3, iclass 16, count 0 2006.176.07:49:49.27#ibcon#about to read 4, iclass 16, count 0 2006.176.07:49:49.27#ibcon#read 4, iclass 16, count 0 2006.176.07:49:49.27#ibcon#about to read 5, iclass 16, count 0 2006.176.07:49:49.27#ibcon#read 5, iclass 16, count 0 2006.176.07:49:49.27#ibcon#about to read 6, iclass 16, count 0 2006.176.07:49:49.27#ibcon#read 6, iclass 16, count 0 2006.176.07:49:49.27#ibcon#end of sib2, iclass 16, count 0 2006.176.07:49:49.27#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:49:49.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:49:49.27#ibcon#[25=USB\r\n] 2006.176.07:49:49.27#ibcon#*before write, iclass 16, count 0 2006.176.07:49:49.27#ibcon#enter sib2, iclass 16, count 0 2006.176.07:49:49.27#ibcon#flushed, iclass 16, count 0 2006.176.07:49:49.27#ibcon#about to write, iclass 16, count 0 2006.176.07:49:49.27#ibcon#wrote, iclass 16, count 0 2006.176.07:49:49.27#ibcon#about to read 3, iclass 16, count 0 2006.176.07:49:49.30#ibcon#read 3, iclass 16, count 0 2006.176.07:49:49.30#ibcon#about to read 4, iclass 16, count 0 2006.176.07:49:49.30#ibcon#read 4, iclass 16, count 0 2006.176.07:49:49.30#ibcon#about to read 5, iclass 16, count 0 2006.176.07:49:49.30#ibcon#read 5, iclass 16, count 0 2006.176.07:49:49.30#ibcon#about to read 6, iclass 16, count 0 2006.176.07:49:49.30#ibcon#read 6, iclass 16, count 0 2006.176.07:49:49.30#ibcon#end of sib2, iclass 16, count 0 2006.176.07:49:49.30#ibcon#*after write, iclass 16, count 0 2006.176.07:49:49.30#ibcon#*before return 0, iclass 16, count 0 2006.176.07:49:49.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:49.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:49.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:49:49.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:49:49.30$vc4f8/valo=5,652.99 2006.176.07:49:49.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.07:49:49.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.07:49:49.30#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:49.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:49.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:49.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:49.30#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:49:49.30#ibcon#first serial, iclass 18, count 0 2006.176.07:49:49.30#ibcon#enter sib2, iclass 18, count 0 2006.176.07:49:49.30#ibcon#flushed, iclass 18, count 0 2006.176.07:49:49.30#ibcon#about to write, iclass 18, count 0 2006.176.07:49:49.30#ibcon#wrote, iclass 18, count 0 2006.176.07:49:49.30#ibcon#about to read 3, iclass 18, count 0 2006.176.07:49:49.32#ibcon#read 3, iclass 18, count 0 2006.176.07:49:49.32#ibcon#about to read 4, iclass 18, count 0 2006.176.07:49:49.32#ibcon#read 4, iclass 18, count 0 2006.176.07:49:49.32#ibcon#about to read 5, iclass 18, count 0 2006.176.07:49:49.32#ibcon#read 5, iclass 18, count 0 2006.176.07:49:49.32#ibcon#about to read 6, iclass 18, count 0 2006.176.07:49:49.32#ibcon#read 6, iclass 18, count 0 2006.176.07:49:49.32#ibcon#end of sib2, iclass 18, count 0 2006.176.07:49:49.32#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:49:49.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:49:49.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:49:49.32#ibcon#*before write, iclass 18, count 0 2006.176.07:49:49.32#ibcon#enter sib2, iclass 18, count 0 2006.176.07:49:49.32#ibcon#flushed, iclass 18, count 0 2006.176.07:49:49.32#ibcon#about to write, iclass 18, count 0 2006.176.07:49:49.32#ibcon#wrote, iclass 18, count 0 2006.176.07:49:49.32#ibcon#about to read 3, iclass 18, count 0 2006.176.07:49:49.36#ibcon#read 3, iclass 18, count 0 2006.176.07:49:49.36#ibcon#about to read 4, iclass 18, count 0 2006.176.07:49:49.36#ibcon#read 4, iclass 18, count 0 2006.176.07:49:49.36#ibcon#about to read 5, iclass 18, count 0 2006.176.07:49:49.36#ibcon#read 5, iclass 18, count 0 2006.176.07:49:49.36#ibcon#about to read 6, iclass 18, count 0 2006.176.07:49:49.36#ibcon#read 6, iclass 18, count 0 2006.176.07:49:49.36#ibcon#end of sib2, iclass 18, count 0 2006.176.07:49:49.36#ibcon#*after write, iclass 18, count 0 2006.176.07:49:49.36#ibcon#*before return 0, iclass 18, count 0 2006.176.07:49:49.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:49.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:49.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:49:49.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:49:49.36$vc4f8/va=5,7 2006.176.07:49:49.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.07:49:49.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.07:49:49.36#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:49.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:49.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:49.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:49.42#ibcon#enter wrdev, iclass 20, count 2 2006.176.07:49:49.42#ibcon#first serial, iclass 20, count 2 2006.176.07:49:49.42#ibcon#enter sib2, iclass 20, count 2 2006.176.07:49:49.42#ibcon#flushed, iclass 20, count 2 2006.176.07:49:49.42#ibcon#about to write, iclass 20, count 2 2006.176.07:49:49.42#ibcon#wrote, iclass 20, count 2 2006.176.07:49:49.42#ibcon#about to read 3, iclass 20, count 2 2006.176.07:49:49.44#ibcon#read 3, iclass 20, count 2 2006.176.07:49:49.44#ibcon#about to read 4, iclass 20, count 2 2006.176.07:49:49.44#ibcon#read 4, iclass 20, count 2 2006.176.07:49:49.44#ibcon#about to read 5, iclass 20, count 2 2006.176.07:49:49.44#ibcon#read 5, iclass 20, count 2 2006.176.07:49:49.44#ibcon#about to read 6, iclass 20, count 2 2006.176.07:49:49.44#ibcon#read 6, iclass 20, count 2 2006.176.07:49:49.44#ibcon#end of sib2, iclass 20, count 2 2006.176.07:49:49.44#ibcon#*mode == 0, iclass 20, count 2 2006.176.07:49:49.44#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.07:49:49.44#ibcon#[25=AT05-07\r\n] 2006.176.07:49:49.44#ibcon#*before write, iclass 20, count 2 2006.176.07:49:49.44#ibcon#enter sib2, iclass 20, count 2 2006.176.07:49:49.44#ibcon#flushed, iclass 20, count 2 2006.176.07:49:49.44#ibcon#about to write, iclass 20, count 2 2006.176.07:49:49.44#ibcon#wrote, iclass 20, count 2 2006.176.07:49:49.44#ibcon#about to read 3, iclass 20, count 2 2006.176.07:49:49.47#ibcon#read 3, iclass 20, count 2 2006.176.07:49:49.47#ibcon#about to read 4, iclass 20, count 2 2006.176.07:49:49.47#ibcon#read 4, iclass 20, count 2 2006.176.07:49:49.47#ibcon#about to read 5, iclass 20, count 2 2006.176.07:49:49.47#ibcon#read 5, iclass 20, count 2 2006.176.07:49:49.47#ibcon#about to read 6, iclass 20, count 2 2006.176.07:49:49.47#ibcon#read 6, iclass 20, count 2 2006.176.07:49:49.47#ibcon#end of sib2, iclass 20, count 2 2006.176.07:49:49.47#ibcon#*after write, iclass 20, count 2 2006.176.07:49:49.47#ibcon#*before return 0, iclass 20, count 2 2006.176.07:49:49.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:49.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:49.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.07:49:49.47#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:49.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:49.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:49.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:49.59#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:49:49.59#ibcon#first serial, iclass 20, count 0 2006.176.07:49:49.59#ibcon#enter sib2, iclass 20, count 0 2006.176.07:49:49.59#ibcon#flushed, iclass 20, count 0 2006.176.07:49:49.59#ibcon#about to write, iclass 20, count 0 2006.176.07:49:49.59#ibcon#wrote, iclass 20, count 0 2006.176.07:49:49.59#ibcon#about to read 3, iclass 20, count 0 2006.176.07:49:49.61#ibcon#read 3, iclass 20, count 0 2006.176.07:49:49.61#ibcon#about to read 4, iclass 20, count 0 2006.176.07:49:49.61#ibcon#read 4, iclass 20, count 0 2006.176.07:49:49.61#ibcon#about to read 5, iclass 20, count 0 2006.176.07:49:49.61#ibcon#read 5, iclass 20, count 0 2006.176.07:49:49.61#ibcon#about to read 6, iclass 20, count 0 2006.176.07:49:49.61#ibcon#read 6, iclass 20, count 0 2006.176.07:49:49.61#ibcon#end of sib2, iclass 20, count 0 2006.176.07:49:49.61#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:49:49.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:49:49.61#ibcon#[25=USB\r\n] 2006.176.07:49:49.61#ibcon#*before write, iclass 20, count 0 2006.176.07:49:49.61#ibcon#enter sib2, iclass 20, count 0 2006.176.07:49:49.61#ibcon#flushed, iclass 20, count 0 2006.176.07:49:49.61#ibcon#about to write, iclass 20, count 0 2006.176.07:49:49.61#ibcon#wrote, iclass 20, count 0 2006.176.07:49:49.61#ibcon#about to read 3, iclass 20, count 0 2006.176.07:49:49.64#ibcon#read 3, iclass 20, count 0 2006.176.07:49:49.64#ibcon#about to read 4, iclass 20, count 0 2006.176.07:49:49.64#ibcon#read 4, iclass 20, count 0 2006.176.07:49:49.64#ibcon#about to read 5, iclass 20, count 0 2006.176.07:49:49.64#ibcon#read 5, iclass 20, count 0 2006.176.07:49:49.64#ibcon#about to read 6, iclass 20, count 0 2006.176.07:49:49.64#ibcon#read 6, iclass 20, count 0 2006.176.07:49:49.64#ibcon#end of sib2, iclass 20, count 0 2006.176.07:49:49.64#ibcon#*after write, iclass 20, count 0 2006.176.07:49:49.64#ibcon#*before return 0, iclass 20, count 0 2006.176.07:49:49.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:49.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:49.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:49:49.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:49:49.64$vc4f8/valo=6,772.99 2006.176.07:49:49.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.07:49:49.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.07:49:49.64#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:49.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:49.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:49.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:49.64#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:49:49.64#ibcon#first serial, iclass 22, count 0 2006.176.07:49:49.64#ibcon#enter sib2, iclass 22, count 0 2006.176.07:49:49.64#ibcon#flushed, iclass 22, count 0 2006.176.07:49:49.64#ibcon#about to write, iclass 22, count 0 2006.176.07:49:49.64#ibcon#wrote, iclass 22, count 0 2006.176.07:49:49.64#ibcon#about to read 3, iclass 22, count 0 2006.176.07:49:49.66#ibcon#read 3, iclass 22, count 0 2006.176.07:49:49.66#ibcon#about to read 4, iclass 22, count 0 2006.176.07:49:49.66#ibcon#read 4, iclass 22, count 0 2006.176.07:49:49.66#ibcon#about to read 5, iclass 22, count 0 2006.176.07:49:49.66#ibcon#read 5, iclass 22, count 0 2006.176.07:49:49.66#ibcon#about to read 6, iclass 22, count 0 2006.176.07:49:49.66#ibcon#read 6, iclass 22, count 0 2006.176.07:49:49.66#ibcon#end of sib2, iclass 22, count 0 2006.176.07:49:49.66#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:49:49.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:49:49.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:49:49.66#ibcon#*before write, iclass 22, count 0 2006.176.07:49:49.66#ibcon#enter sib2, iclass 22, count 0 2006.176.07:49:49.66#ibcon#flushed, iclass 22, count 0 2006.176.07:49:49.66#ibcon#about to write, iclass 22, count 0 2006.176.07:49:49.66#ibcon#wrote, iclass 22, count 0 2006.176.07:49:49.66#ibcon#about to read 3, iclass 22, count 0 2006.176.07:49:49.70#ibcon#read 3, iclass 22, count 0 2006.176.07:49:49.70#ibcon#about to read 4, iclass 22, count 0 2006.176.07:49:49.70#ibcon#read 4, iclass 22, count 0 2006.176.07:49:49.70#ibcon#about to read 5, iclass 22, count 0 2006.176.07:49:49.70#ibcon#read 5, iclass 22, count 0 2006.176.07:49:49.70#ibcon#about to read 6, iclass 22, count 0 2006.176.07:49:49.70#ibcon#read 6, iclass 22, count 0 2006.176.07:49:49.70#ibcon#end of sib2, iclass 22, count 0 2006.176.07:49:49.70#ibcon#*after write, iclass 22, count 0 2006.176.07:49:49.70#ibcon#*before return 0, iclass 22, count 0 2006.176.07:49:49.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:49.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:49.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:49:49.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:49:49.70$vc4f8/va=6,6 2006.176.07:49:49.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.07:49:49.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.07:49:49.70#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:49.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:49:49.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:49:49.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:49:49.76#ibcon#enter wrdev, iclass 24, count 2 2006.176.07:49:49.76#ibcon#first serial, iclass 24, count 2 2006.176.07:49:49.76#ibcon#enter sib2, iclass 24, count 2 2006.176.07:49:49.76#ibcon#flushed, iclass 24, count 2 2006.176.07:49:49.76#ibcon#about to write, iclass 24, count 2 2006.176.07:49:49.76#ibcon#wrote, iclass 24, count 2 2006.176.07:49:49.76#ibcon#about to read 3, iclass 24, count 2 2006.176.07:49:49.78#ibcon#read 3, iclass 24, count 2 2006.176.07:49:49.78#ibcon#about to read 4, iclass 24, count 2 2006.176.07:49:49.78#ibcon#read 4, iclass 24, count 2 2006.176.07:49:49.78#ibcon#about to read 5, iclass 24, count 2 2006.176.07:49:49.78#ibcon#read 5, iclass 24, count 2 2006.176.07:49:49.78#ibcon#about to read 6, iclass 24, count 2 2006.176.07:49:49.78#ibcon#read 6, iclass 24, count 2 2006.176.07:49:49.78#ibcon#end of sib2, iclass 24, count 2 2006.176.07:49:49.78#ibcon#*mode == 0, iclass 24, count 2 2006.176.07:49:49.78#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.07:49:49.78#ibcon#[25=AT06-06\r\n] 2006.176.07:49:49.78#ibcon#*before write, iclass 24, count 2 2006.176.07:49:49.78#ibcon#enter sib2, iclass 24, count 2 2006.176.07:49:49.78#ibcon#flushed, iclass 24, count 2 2006.176.07:49:49.78#ibcon#about to write, iclass 24, count 2 2006.176.07:49:49.78#ibcon#wrote, iclass 24, count 2 2006.176.07:49:49.78#ibcon#about to read 3, iclass 24, count 2 2006.176.07:49:49.81#ibcon#read 3, iclass 24, count 2 2006.176.07:49:49.81#ibcon#about to read 4, iclass 24, count 2 2006.176.07:49:49.81#ibcon#read 4, iclass 24, count 2 2006.176.07:49:49.81#ibcon#about to read 5, iclass 24, count 2 2006.176.07:49:49.81#ibcon#read 5, iclass 24, count 2 2006.176.07:49:49.81#ibcon#about to read 6, iclass 24, count 2 2006.176.07:49:49.81#ibcon#read 6, iclass 24, count 2 2006.176.07:49:49.81#ibcon#end of sib2, iclass 24, count 2 2006.176.07:49:49.81#ibcon#*after write, iclass 24, count 2 2006.176.07:49:49.81#ibcon#*before return 0, iclass 24, count 2 2006.176.07:49:49.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:49:49.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.07:49:49.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.07:49:49.81#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:49.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:49:49.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:49:49.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:49:49.93#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:49:49.93#ibcon#first serial, iclass 24, count 0 2006.176.07:49:49.93#ibcon#enter sib2, iclass 24, count 0 2006.176.07:49:49.93#ibcon#flushed, iclass 24, count 0 2006.176.07:49:49.93#ibcon#about to write, iclass 24, count 0 2006.176.07:49:49.93#ibcon#wrote, iclass 24, count 0 2006.176.07:49:49.93#ibcon#about to read 3, iclass 24, count 0 2006.176.07:49:49.95#ibcon#read 3, iclass 24, count 0 2006.176.07:49:49.95#ibcon#about to read 4, iclass 24, count 0 2006.176.07:49:49.95#ibcon#read 4, iclass 24, count 0 2006.176.07:49:49.95#ibcon#about to read 5, iclass 24, count 0 2006.176.07:49:49.95#ibcon#read 5, iclass 24, count 0 2006.176.07:49:49.95#ibcon#about to read 6, iclass 24, count 0 2006.176.07:49:49.95#ibcon#read 6, iclass 24, count 0 2006.176.07:49:49.95#ibcon#end of sib2, iclass 24, count 0 2006.176.07:49:49.95#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:49:49.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:49:49.95#ibcon#[25=USB\r\n] 2006.176.07:49:49.95#ibcon#*before write, iclass 24, count 0 2006.176.07:49:49.95#ibcon#enter sib2, iclass 24, count 0 2006.176.07:49:49.95#ibcon#flushed, iclass 24, count 0 2006.176.07:49:49.95#ibcon#about to write, iclass 24, count 0 2006.176.07:49:49.95#ibcon#wrote, iclass 24, count 0 2006.176.07:49:49.95#ibcon#about to read 3, iclass 24, count 0 2006.176.07:49:49.98#ibcon#read 3, iclass 24, count 0 2006.176.07:49:49.98#ibcon#about to read 4, iclass 24, count 0 2006.176.07:49:49.98#ibcon#read 4, iclass 24, count 0 2006.176.07:49:49.98#ibcon#about to read 5, iclass 24, count 0 2006.176.07:49:49.98#ibcon#read 5, iclass 24, count 0 2006.176.07:49:49.98#ibcon#about to read 6, iclass 24, count 0 2006.176.07:49:49.98#ibcon#read 6, iclass 24, count 0 2006.176.07:49:49.98#ibcon#end of sib2, iclass 24, count 0 2006.176.07:49:49.98#ibcon#*after write, iclass 24, count 0 2006.176.07:49:49.98#ibcon#*before return 0, iclass 24, count 0 2006.176.07:49:49.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:49:49.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.07:49:49.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:49:49.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:49:49.98$vc4f8/valo=7,832.99 2006.176.07:49:49.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.07:49:49.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.07:49:49.98#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:49.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:49:49.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:49:49.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:49:49.98#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:49:49.98#ibcon#first serial, iclass 26, count 0 2006.176.07:49:49.98#ibcon#enter sib2, iclass 26, count 0 2006.176.07:49:49.98#ibcon#flushed, iclass 26, count 0 2006.176.07:49:49.98#ibcon#about to write, iclass 26, count 0 2006.176.07:49:49.98#ibcon#wrote, iclass 26, count 0 2006.176.07:49:49.98#ibcon#about to read 3, iclass 26, count 0 2006.176.07:49:50.00#ibcon#read 3, iclass 26, count 0 2006.176.07:49:50.00#ibcon#about to read 4, iclass 26, count 0 2006.176.07:49:50.00#ibcon#read 4, iclass 26, count 0 2006.176.07:49:50.00#ibcon#about to read 5, iclass 26, count 0 2006.176.07:49:50.00#ibcon#read 5, iclass 26, count 0 2006.176.07:49:50.00#ibcon#about to read 6, iclass 26, count 0 2006.176.07:49:50.00#ibcon#read 6, iclass 26, count 0 2006.176.07:49:50.00#ibcon#end of sib2, iclass 26, count 0 2006.176.07:49:50.00#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:49:50.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:49:50.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:49:50.00#ibcon#*before write, iclass 26, count 0 2006.176.07:49:50.00#ibcon#enter sib2, iclass 26, count 0 2006.176.07:49:50.00#ibcon#flushed, iclass 26, count 0 2006.176.07:49:50.00#ibcon#about to write, iclass 26, count 0 2006.176.07:49:50.00#ibcon#wrote, iclass 26, count 0 2006.176.07:49:50.00#ibcon#about to read 3, iclass 26, count 0 2006.176.07:49:50.04#ibcon#read 3, iclass 26, count 0 2006.176.07:49:50.04#ibcon#about to read 4, iclass 26, count 0 2006.176.07:49:50.04#ibcon#read 4, iclass 26, count 0 2006.176.07:49:50.04#ibcon#about to read 5, iclass 26, count 0 2006.176.07:49:50.04#ibcon#read 5, iclass 26, count 0 2006.176.07:49:50.04#ibcon#about to read 6, iclass 26, count 0 2006.176.07:49:50.04#ibcon#read 6, iclass 26, count 0 2006.176.07:49:50.04#ibcon#end of sib2, iclass 26, count 0 2006.176.07:49:50.04#ibcon#*after write, iclass 26, count 0 2006.176.07:49:50.04#ibcon#*before return 0, iclass 26, count 0 2006.176.07:49:50.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:49:50.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.07:49:50.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:49:50.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:49:50.04$vc4f8/va=7,6 2006.176.07:49:50.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.07:49:50.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.07:49:50.04#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:50.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:49:50.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:49:50.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:49:50.10#ibcon#enter wrdev, iclass 28, count 2 2006.176.07:49:50.10#ibcon#first serial, iclass 28, count 2 2006.176.07:49:50.10#ibcon#enter sib2, iclass 28, count 2 2006.176.07:49:50.10#ibcon#flushed, iclass 28, count 2 2006.176.07:49:50.10#ibcon#about to write, iclass 28, count 2 2006.176.07:49:50.10#ibcon#wrote, iclass 28, count 2 2006.176.07:49:50.10#ibcon#about to read 3, iclass 28, count 2 2006.176.07:49:50.12#ibcon#read 3, iclass 28, count 2 2006.176.07:49:50.12#ibcon#about to read 4, iclass 28, count 2 2006.176.07:49:50.12#ibcon#read 4, iclass 28, count 2 2006.176.07:49:50.12#ibcon#about to read 5, iclass 28, count 2 2006.176.07:49:50.12#ibcon#read 5, iclass 28, count 2 2006.176.07:49:50.12#ibcon#about to read 6, iclass 28, count 2 2006.176.07:49:50.12#ibcon#read 6, iclass 28, count 2 2006.176.07:49:50.12#ibcon#end of sib2, iclass 28, count 2 2006.176.07:49:50.12#ibcon#*mode == 0, iclass 28, count 2 2006.176.07:49:50.12#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.07:49:50.12#ibcon#[25=AT07-06\r\n] 2006.176.07:49:50.12#ibcon#*before write, iclass 28, count 2 2006.176.07:49:50.12#ibcon#enter sib2, iclass 28, count 2 2006.176.07:49:50.12#ibcon#flushed, iclass 28, count 2 2006.176.07:49:50.12#ibcon#about to write, iclass 28, count 2 2006.176.07:49:50.12#ibcon#wrote, iclass 28, count 2 2006.176.07:49:50.12#ibcon#about to read 3, iclass 28, count 2 2006.176.07:49:50.15#ibcon#read 3, iclass 28, count 2 2006.176.07:49:50.15#ibcon#about to read 4, iclass 28, count 2 2006.176.07:49:50.15#ibcon#read 4, iclass 28, count 2 2006.176.07:49:50.15#ibcon#about to read 5, iclass 28, count 2 2006.176.07:49:50.15#ibcon#read 5, iclass 28, count 2 2006.176.07:49:50.15#ibcon#about to read 6, iclass 28, count 2 2006.176.07:49:50.15#ibcon#read 6, iclass 28, count 2 2006.176.07:49:50.15#ibcon#end of sib2, iclass 28, count 2 2006.176.07:49:50.15#ibcon#*after write, iclass 28, count 2 2006.176.07:49:50.15#ibcon#*before return 0, iclass 28, count 2 2006.176.07:49:50.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:49:50.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.07:49:50.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.07:49:50.15#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:50.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:49:50.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:49:50.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:49:50.27#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:49:50.27#ibcon#first serial, iclass 28, count 0 2006.176.07:49:50.27#ibcon#enter sib2, iclass 28, count 0 2006.176.07:49:50.27#ibcon#flushed, iclass 28, count 0 2006.176.07:49:50.27#ibcon#about to write, iclass 28, count 0 2006.176.07:49:50.27#ibcon#wrote, iclass 28, count 0 2006.176.07:49:50.27#ibcon#about to read 3, iclass 28, count 0 2006.176.07:49:50.29#ibcon#read 3, iclass 28, count 0 2006.176.07:49:50.29#ibcon#about to read 4, iclass 28, count 0 2006.176.07:49:50.29#ibcon#read 4, iclass 28, count 0 2006.176.07:49:50.29#ibcon#about to read 5, iclass 28, count 0 2006.176.07:49:50.29#ibcon#read 5, iclass 28, count 0 2006.176.07:49:50.29#ibcon#about to read 6, iclass 28, count 0 2006.176.07:49:50.29#ibcon#read 6, iclass 28, count 0 2006.176.07:49:50.29#ibcon#end of sib2, iclass 28, count 0 2006.176.07:49:50.29#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:49:50.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:49:50.29#ibcon#[25=USB\r\n] 2006.176.07:49:50.29#ibcon#*before write, iclass 28, count 0 2006.176.07:49:50.29#ibcon#enter sib2, iclass 28, count 0 2006.176.07:49:50.29#ibcon#flushed, iclass 28, count 0 2006.176.07:49:50.29#ibcon#about to write, iclass 28, count 0 2006.176.07:49:50.29#ibcon#wrote, iclass 28, count 0 2006.176.07:49:50.29#ibcon#about to read 3, iclass 28, count 0 2006.176.07:49:50.32#ibcon#read 3, iclass 28, count 0 2006.176.07:49:50.32#ibcon#about to read 4, iclass 28, count 0 2006.176.07:49:50.32#ibcon#read 4, iclass 28, count 0 2006.176.07:49:50.32#ibcon#about to read 5, iclass 28, count 0 2006.176.07:49:50.32#ibcon#read 5, iclass 28, count 0 2006.176.07:49:50.32#ibcon#about to read 6, iclass 28, count 0 2006.176.07:49:50.32#ibcon#read 6, iclass 28, count 0 2006.176.07:49:50.32#ibcon#end of sib2, iclass 28, count 0 2006.176.07:49:50.32#ibcon#*after write, iclass 28, count 0 2006.176.07:49:50.32#ibcon#*before return 0, iclass 28, count 0 2006.176.07:49:50.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:49:50.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.07:49:50.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:49:50.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:49:50.32$vc4f8/valo=8,852.99 2006.176.07:49:50.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.07:49:50.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.07:49:50.32#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:50.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:49:50.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:49:50.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:49:50.32#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:49:50.32#ibcon#first serial, iclass 30, count 0 2006.176.07:49:50.32#ibcon#enter sib2, iclass 30, count 0 2006.176.07:49:50.32#ibcon#flushed, iclass 30, count 0 2006.176.07:49:50.32#ibcon#about to write, iclass 30, count 0 2006.176.07:49:50.32#ibcon#wrote, iclass 30, count 0 2006.176.07:49:50.32#ibcon#about to read 3, iclass 30, count 0 2006.176.07:49:50.34#ibcon#read 3, iclass 30, count 0 2006.176.07:49:50.34#ibcon#about to read 4, iclass 30, count 0 2006.176.07:49:50.34#ibcon#read 4, iclass 30, count 0 2006.176.07:49:50.34#ibcon#about to read 5, iclass 30, count 0 2006.176.07:49:50.34#ibcon#read 5, iclass 30, count 0 2006.176.07:49:50.34#ibcon#about to read 6, iclass 30, count 0 2006.176.07:49:50.34#ibcon#read 6, iclass 30, count 0 2006.176.07:49:50.34#ibcon#end of sib2, iclass 30, count 0 2006.176.07:49:50.34#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:49:50.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:49:50.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:49:50.34#ibcon#*before write, iclass 30, count 0 2006.176.07:49:50.34#ibcon#enter sib2, iclass 30, count 0 2006.176.07:49:50.34#ibcon#flushed, iclass 30, count 0 2006.176.07:49:50.34#ibcon#about to write, iclass 30, count 0 2006.176.07:49:50.34#ibcon#wrote, iclass 30, count 0 2006.176.07:49:50.34#ibcon#about to read 3, iclass 30, count 0 2006.176.07:49:50.38#ibcon#read 3, iclass 30, count 0 2006.176.07:49:50.38#ibcon#about to read 4, iclass 30, count 0 2006.176.07:49:50.38#ibcon#read 4, iclass 30, count 0 2006.176.07:49:50.38#ibcon#about to read 5, iclass 30, count 0 2006.176.07:49:50.38#ibcon#read 5, iclass 30, count 0 2006.176.07:49:50.38#ibcon#about to read 6, iclass 30, count 0 2006.176.07:49:50.38#ibcon#read 6, iclass 30, count 0 2006.176.07:49:50.38#ibcon#end of sib2, iclass 30, count 0 2006.176.07:49:50.38#ibcon#*after write, iclass 30, count 0 2006.176.07:49:50.38#ibcon#*before return 0, iclass 30, count 0 2006.176.07:49:50.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:49:50.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:49:50.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:49:50.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:49:50.38$vc4f8/va=8,6 2006.176.07:49:50.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.176.07:49:50.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.176.07:49:50.38#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:50.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:49:50.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:49:50.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:49:50.44#ibcon#enter wrdev, iclass 32, count 2 2006.176.07:49:50.44#ibcon#first serial, iclass 32, count 2 2006.176.07:49:50.44#ibcon#enter sib2, iclass 32, count 2 2006.176.07:49:50.44#ibcon#flushed, iclass 32, count 2 2006.176.07:49:50.44#ibcon#about to write, iclass 32, count 2 2006.176.07:49:50.44#ibcon#wrote, iclass 32, count 2 2006.176.07:49:50.44#ibcon#about to read 3, iclass 32, count 2 2006.176.07:49:50.46#ibcon#read 3, iclass 32, count 2 2006.176.07:49:50.46#ibcon#about to read 4, iclass 32, count 2 2006.176.07:49:50.46#ibcon#read 4, iclass 32, count 2 2006.176.07:49:50.46#ibcon#about to read 5, iclass 32, count 2 2006.176.07:49:50.46#ibcon#read 5, iclass 32, count 2 2006.176.07:49:50.46#ibcon#about to read 6, iclass 32, count 2 2006.176.07:49:50.46#ibcon#read 6, iclass 32, count 2 2006.176.07:49:50.46#ibcon#end of sib2, iclass 32, count 2 2006.176.07:49:50.46#ibcon#*mode == 0, iclass 32, count 2 2006.176.07:49:50.46#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.176.07:49:50.46#ibcon#[25=AT08-06\r\n] 2006.176.07:49:50.46#ibcon#*before write, iclass 32, count 2 2006.176.07:49:50.46#ibcon#enter sib2, iclass 32, count 2 2006.176.07:49:50.46#ibcon#flushed, iclass 32, count 2 2006.176.07:49:50.46#ibcon#about to write, iclass 32, count 2 2006.176.07:49:50.46#ibcon#wrote, iclass 32, count 2 2006.176.07:49:50.46#ibcon#about to read 3, iclass 32, count 2 2006.176.07:49:50.49#ibcon#read 3, iclass 32, count 2 2006.176.07:49:50.49#ibcon#about to read 4, iclass 32, count 2 2006.176.07:49:50.49#ibcon#read 4, iclass 32, count 2 2006.176.07:49:50.49#ibcon#about to read 5, iclass 32, count 2 2006.176.07:49:50.49#ibcon#read 5, iclass 32, count 2 2006.176.07:49:50.49#ibcon#about to read 6, iclass 32, count 2 2006.176.07:49:50.49#ibcon#read 6, iclass 32, count 2 2006.176.07:49:50.49#ibcon#end of sib2, iclass 32, count 2 2006.176.07:49:50.49#ibcon#*after write, iclass 32, count 2 2006.176.07:49:50.49#ibcon#*before return 0, iclass 32, count 2 2006.176.07:49:50.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:49:50.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:49:50.49#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.176.07:49:50.49#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:50.49#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:49:50.61#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:49:50.61#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:49:50.61#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:49:50.61#ibcon#first serial, iclass 32, count 0 2006.176.07:49:50.61#ibcon#enter sib2, iclass 32, count 0 2006.176.07:49:50.61#ibcon#flushed, iclass 32, count 0 2006.176.07:49:50.61#ibcon#about to write, iclass 32, count 0 2006.176.07:49:50.61#ibcon#wrote, iclass 32, count 0 2006.176.07:49:50.61#ibcon#about to read 3, iclass 32, count 0 2006.176.07:49:50.63#ibcon#read 3, iclass 32, count 0 2006.176.07:49:50.63#ibcon#about to read 4, iclass 32, count 0 2006.176.07:49:50.63#ibcon#read 4, iclass 32, count 0 2006.176.07:49:50.63#ibcon#about to read 5, iclass 32, count 0 2006.176.07:49:50.63#ibcon#read 5, iclass 32, count 0 2006.176.07:49:50.63#ibcon#about to read 6, iclass 32, count 0 2006.176.07:49:50.63#ibcon#read 6, iclass 32, count 0 2006.176.07:49:50.63#ibcon#end of sib2, iclass 32, count 0 2006.176.07:49:50.63#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:49:50.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:49:50.63#ibcon#[25=USB\r\n] 2006.176.07:49:50.63#ibcon#*before write, iclass 32, count 0 2006.176.07:49:50.63#ibcon#enter sib2, iclass 32, count 0 2006.176.07:49:50.63#ibcon#flushed, iclass 32, count 0 2006.176.07:49:50.63#ibcon#about to write, iclass 32, count 0 2006.176.07:49:50.63#ibcon#wrote, iclass 32, count 0 2006.176.07:49:50.63#ibcon#about to read 3, iclass 32, count 0 2006.176.07:49:50.66#ibcon#read 3, iclass 32, count 0 2006.176.07:49:50.66#ibcon#about to read 4, iclass 32, count 0 2006.176.07:49:50.66#ibcon#read 4, iclass 32, count 0 2006.176.07:49:50.66#ibcon#about to read 5, iclass 32, count 0 2006.176.07:49:50.66#ibcon#read 5, iclass 32, count 0 2006.176.07:49:50.66#ibcon#about to read 6, iclass 32, count 0 2006.176.07:49:50.66#ibcon#read 6, iclass 32, count 0 2006.176.07:49:50.66#ibcon#end of sib2, iclass 32, count 0 2006.176.07:49:50.66#ibcon#*after write, iclass 32, count 0 2006.176.07:49:50.66#ibcon#*before return 0, iclass 32, count 0 2006.176.07:49:50.66#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:49:50.66#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:49:50.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:49:50.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:49:50.66$vc4f8/vblo=1,632.99 2006.176.07:49:50.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.07:49:50.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.07:49:50.66#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:50.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:49:50.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:49:50.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:49:50.66#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:49:50.66#ibcon#first serial, iclass 34, count 0 2006.176.07:49:50.66#ibcon#enter sib2, iclass 34, count 0 2006.176.07:49:50.66#ibcon#flushed, iclass 34, count 0 2006.176.07:49:50.66#ibcon#about to write, iclass 34, count 0 2006.176.07:49:50.66#ibcon#wrote, iclass 34, count 0 2006.176.07:49:50.66#ibcon#about to read 3, iclass 34, count 0 2006.176.07:49:50.68#ibcon#read 3, iclass 34, count 0 2006.176.07:49:50.68#ibcon#about to read 4, iclass 34, count 0 2006.176.07:49:50.68#ibcon#read 4, iclass 34, count 0 2006.176.07:49:50.68#ibcon#about to read 5, iclass 34, count 0 2006.176.07:49:50.68#ibcon#read 5, iclass 34, count 0 2006.176.07:49:50.68#ibcon#about to read 6, iclass 34, count 0 2006.176.07:49:50.68#ibcon#read 6, iclass 34, count 0 2006.176.07:49:50.68#ibcon#end of sib2, iclass 34, count 0 2006.176.07:49:50.68#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:49:50.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:49:50.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:49:50.68#ibcon#*before write, iclass 34, count 0 2006.176.07:49:50.68#ibcon#enter sib2, iclass 34, count 0 2006.176.07:49:50.68#ibcon#flushed, iclass 34, count 0 2006.176.07:49:50.68#ibcon#about to write, iclass 34, count 0 2006.176.07:49:50.68#ibcon#wrote, iclass 34, count 0 2006.176.07:49:50.68#ibcon#about to read 3, iclass 34, count 0 2006.176.07:49:50.72#ibcon#read 3, iclass 34, count 0 2006.176.07:49:50.72#ibcon#about to read 4, iclass 34, count 0 2006.176.07:49:50.72#ibcon#read 4, iclass 34, count 0 2006.176.07:49:50.72#ibcon#about to read 5, iclass 34, count 0 2006.176.07:49:50.72#ibcon#read 5, iclass 34, count 0 2006.176.07:49:50.72#ibcon#about to read 6, iclass 34, count 0 2006.176.07:49:50.72#ibcon#read 6, iclass 34, count 0 2006.176.07:49:50.72#ibcon#end of sib2, iclass 34, count 0 2006.176.07:49:50.72#ibcon#*after write, iclass 34, count 0 2006.176.07:49:50.72#ibcon#*before return 0, iclass 34, count 0 2006.176.07:49:50.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:49:50.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:49:50.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:49:50.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:49:50.72$vc4f8/vb=1,4 2006.176.07:49:50.72#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.176.07:49:50.72#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.176.07:49:50.72#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:50.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:49:50.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:49:50.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:49:50.72#ibcon#enter wrdev, iclass 36, count 2 2006.176.07:49:50.72#ibcon#first serial, iclass 36, count 2 2006.176.07:49:50.72#ibcon#enter sib2, iclass 36, count 2 2006.176.07:49:50.72#ibcon#flushed, iclass 36, count 2 2006.176.07:49:50.72#ibcon#about to write, iclass 36, count 2 2006.176.07:49:50.72#ibcon#wrote, iclass 36, count 2 2006.176.07:49:50.72#ibcon#about to read 3, iclass 36, count 2 2006.176.07:49:50.74#ibcon#read 3, iclass 36, count 2 2006.176.07:49:50.74#ibcon#about to read 4, iclass 36, count 2 2006.176.07:49:50.74#ibcon#read 4, iclass 36, count 2 2006.176.07:49:50.74#ibcon#about to read 5, iclass 36, count 2 2006.176.07:49:50.74#ibcon#read 5, iclass 36, count 2 2006.176.07:49:50.74#ibcon#about to read 6, iclass 36, count 2 2006.176.07:49:50.74#ibcon#read 6, iclass 36, count 2 2006.176.07:49:50.74#ibcon#end of sib2, iclass 36, count 2 2006.176.07:49:50.74#ibcon#*mode == 0, iclass 36, count 2 2006.176.07:49:50.74#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.176.07:49:50.74#ibcon#[27=AT01-04\r\n] 2006.176.07:49:50.74#ibcon#*before write, iclass 36, count 2 2006.176.07:49:50.74#ibcon#enter sib2, iclass 36, count 2 2006.176.07:49:50.74#ibcon#flushed, iclass 36, count 2 2006.176.07:49:50.74#ibcon#about to write, iclass 36, count 2 2006.176.07:49:50.74#ibcon#wrote, iclass 36, count 2 2006.176.07:49:50.74#ibcon#about to read 3, iclass 36, count 2 2006.176.07:49:50.77#ibcon#read 3, iclass 36, count 2 2006.176.07:49:50.77#ibcon#about to read 4, iclass 36, count 2 2006.176.07:49:50.77#ibcon#read 4, iclass 36, count 2 2006.176.07:49:50.77#ibcon#about to read 5, iclass 36, count 2 2006.176.07:49:50.77#ibcon#read 5, iclass 36, count 2 2006.176.07:49:50.77#ibcon#about to read 6, iclass 36, count 2 2006.176.07:49:50.77#ibcon#read 6, iclass 36, count 2 2006.176.07:49:50.77#ibcon#end of sib2, iclass 36, count 2 2006.176.07:49:50.77#ibcon#*after write, iclass 36, count 2 2006.176.07:49:50.77#ibcon#*before return 0, iclass 36, count 2 2006.176.07:49:50.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:49:50.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:49:50.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.176.07:49:50.77#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:50.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:49:50.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:49:50.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:49:50.89#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:49:50.89#ibcon#first serial, iclass 36, count 0 2006.176.07:49:50.89#ibcon#enter sib2, iclass 36, count 0 2006.176.07:49:50.89#ibcon#flushed, iclass 36, count 0 2006.176.07:49:50.89#ibcon#about to write, iclass 36, count 0 2006.176.07:49:50.89#ibcon#wrote, iclass 36, count 0 2006.176.07:49:50.89#ibcon#about to read 3, iclass 36, count 0 2006.176.07:49:50.91#ibcon#read 3, iclass 36, count 0 2006.176.07:49:50.91#ibcon#about to read 4, iclass 36, count 0 2006.176.07:49:50.91#ibcon#read 4, iclass 36, count 0 2006.176.07:49:50.91#ibcon#about to read 5, iclass 36, count 0 2006.176.07:49:50.91#ibcon#read 5, iclass 36, count 0 2006.176.07:49:50.91#ibcon#about to read 6, iclass 36, count 0 2006.176.07:49:50.91#ibcon#read 6, iclass 36, count 0 2006.176.07:49:50.91#ibcon#end of sib2, iclass 36, count 0 2006.176.07:49:50.91#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:49:50.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:49:50.91#ibcon#[27=USB\r\n] 2006.176.07:49:50.91#ibcon#*before write, iclass 36, count 0 2006.176.07:49:50.91#ibcon#enter sib2, iclass 36, count 0 2006.176.07:49:50.91#ibcon#flushed, iclass 36, count 0 2006.176.07:49:50.91#ibcon#about to write, iclass 36, count 0 2006.176.07:49:50.91#ibcon#wrote, iclass 36, count 0 2006.176.07:49:50.91#ibcon#about to read 3, iclass 36, count 0 2006.176.07:49:50.94#ibcon#read 3, iclass 36, count 0 2006.176.07:49:50.94#ibcon#about to read 4, iclass 36, count 0 2006.176.07:49:50.94#ibcon#read 4, iclass 36, count 0 2006.176.07:49:50.94#ibcon#about to read 5, iclass 36, count 0 2006.176.07:49:50.94#ibcon#read 5, iclass 36, count 0 2006.176.07:49:50.94#ibcon#about to read 6, iclass 36, count 0 2006.176.07:49:50.94#ibcon#read 6, iclass 36, count 0 2006.176.07:49:50.94#ibcon#end of sib2, iclass 36, count 0 2006.176.07:49:50.94#ibcon#*after write, iclass 36, count 0 2006.176.07:49:50.94#ibcon#*before return 0, iclass 36, count 0 2006.176.07:49:50.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:49:50.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:49:50.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:49:50.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:49:50.94$vc4f8/vblo=2,640.99 2006.176.07:49:50.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.07:49:50.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.07:49:50.94#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:50.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:50.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:50.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:50.94#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:49:50.94#ibcon#first serial, iclass 38, count 0 2006.176.07:49:50.94#ibcon#enter sib2, iclass 38, count 0 2006.176.07:49:50.94#ibcon#flushed, iclass 38, count 0 2006.176.07:49:50.94#ibcon#about to write, iclass 38, count 0 2006.176.07:49:50.94#ibcon#wrote, iclass 38, count 0 2006.176.07:49:50.94#ibcon#about to read 3, iclass 38, count 0 2006.176.07:49:50.96#ibcon#read 3, iclass 38, count 0 2006.176.07:49:50.96#ibcon#about to read 4, iclass 38, count 0 2006.176.07:49:50.96#ibcon#read 4, iclass 38, count 0 2006.176.07:49:50.96#ibcon#about to read 5, iclass 38, count 0 2006.176.07:49:50.96#ibcon#read 5, iclass 38, count 0 2006.176.07:49:50.96#ibcon#about to read 6, iclass 38, count 0 2006.176.07:49:50.96#ibcon#read 6, iclass 38, count 0 2006.176.07:49:50.96#ibcon#end of sib2, iclass 38, count 0 2006.176.07:49:50.96#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:49:50.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:49:50.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:49:50.96#ibcon#*before write, iclass 38, count 0 2006.176.07:49:50.96#ibcon#enter sib2, iclass 38, count 0 2006.176.07:49:50.96#ibcon#flushed, iclass 38, count 0 2006.176.07:49:50.96#ibcon#about to write, iclass 38, count 0 2006.176.07:49:50.96#ibcon#wrote, iclass 38, count 0 2006.176.07:49:50.96#ibcon#about to read 3, iclass 38, count 0 2006.176.07:49:51.00#ibcon#read 3, iclass 38, count 0 2006.176.07:49:51.00#ibcon#about to read 4, iclass 38, count 0 2006.176.07:49:51.00#ibcon#read 4, iclass 38, count 0 2006.176.07:49:51.00#ibcon#about to read 5, iclass 38, count 0 2006.176.07:49:51.00#ibcon#read 5, iclass 38, count 0 2006.176.07:49:51.00#ibcon#about to read 6, iclass 38, count 0 2006.176.07:49:51.00#ibcon#read 6, iclass 38, count 0 2006.176.07:49:51.00#ibcon#end of sib2, iclass 38, count 0 2006.176.07:49:51.00#ibcon#*after write, iclass 38, count 0 2006.176.07:49:51.00#ibcon#*before return 0, iclass 38, count 0 2006.176.07:49:51.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:51.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:49:51.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:49:51.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:49:51.00$vc4f8/vb=2,4 2006.176.07:49:51.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.07:49:51.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.07:49:51.00#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:51.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:51.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:51.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:51.06#ibcon#enter wrdev, iclass 40, count 2 2006.176.07:49:51.06#ibcon#first serial, iclass 40, count 2 2006.176.07:49:51.06#ibcon#enter sib2, iclass 40, count 2 2006.176.07:49:51.06#ibcon#flushed, iclass 40, count 2 2006.176.07:49:51.06#ibcon#about to write, iclass 40, count 2 2006.176.07:49:51.06#ibcon#wrote, iclass 40, count 2 2006.176.07:49:51.06#ibcon#about to read 3, iclass 40, count 2 2006.176.07:49:51.08#ibcon#read 3, iclass 40, count 2 2006.176.07:49:51.08#ibcon#about to read 4, iclass 40, count 2 2006.176.07:49:51.08#ibcon#read 4, iclass 40, count 2 2006.176.07:49:51.08#ibcon#about to read 5, iclass 40, count 2 2006.176.07:49:51.08#ibcon#read 5, iclass 40, count 2 2006.176.07:49:51.08#ibcon#about to read 6, iclass 40, count 2 2006.176.07:49:51.08#ibcon#read 6, iclass 40, count 2 2006.176.07:49:51.08#ibcon#end of sib2, iclass 40, count 2 2006.176.07:49:51.08#ibcon#*mode == 0, iclass 40, count 2 2006.176.07:49:51.08#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.07:49:51.08#ibcon#[27=AT02-04\r\n] 2006.176.07:49:51.08#ibcon#*before write, iclass 40, count 2 2006.176.07:49:51.08#ibcon#enter sib2, iclass 40, count 2 2006.176.07:49:51.08#ibcon#flushed, iclass 40, count 2 2006.176.07:49:51.08#ibcon#about to write, iclass 40, count 2 2006.176.07:49:51.08#ibcon#wrote, iclass 40, count 2 2006.176.07:49:51.08#ibcon#about to read 3, iclass 40, count 2 2006.176.07:49:51.12#ibcon#read 3, iclass 40, count 2 2006.176.07:49:51.12#ibcon#about to read 4, iclass 40, count 2 2006.176.07:49:51.12#ibcon#read 4, iclass 40, count 2 2006.176.07:49:51.12#ibcon#about to read 5, iclass 40, count 2 2006.176.07:49:51.12#ibcon#read 5, iclass 40, count 2 2006.176.07:49:51.12#ibcon#about to read 6, iclass 40, count 2 2006.176.07:49:51.12#ibcon#read 6, iclass 40, count 2 2006.176.07:49:51.12#ibcon#end of sib2, iclass 40, count 2 2006.176.07:49:51.12#ibcon#*after write, iclass 40, count 2 2006.176.07:49:51.12#ibcon#*before return 0, iclass 40, count 2 2006.176.07:49:51.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:51.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:49:51.12#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.07:49:51.12#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:51.12#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:51.24#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:51.24#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:51.24#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:49:51.24#ibcon#first serial, iclass 40, count 0 2006.176.07:49:51.24#ibcon#enter sib2, iclass 40, count 0 2006.176.07:49:51.24#ibcon#flushed, iclass 40, count 0 2006.176.07:49:51.24#ibcon#about to write, iclass 40, count 0 2006.176.07:49:51.24#ibcon#wrote, iclass 40, count 0 2006.176.07:49:51.24#ibcon#about to read 3, iclass 40, count 0 2006.176.07:49:51.26#ibcon#read 3, iclass 40, count 0 2006.176.07:49:51.26#ibcon#about to read 4, iclass 40, count 0 2006.176.07:49:51.26#ibcon#read 4, iclass 40, count 0 2006.176.07:49:51.26#ibcon#about to read 5, iclass 40, count 0 2006.176.07:49:51.26#ibcon#read 5, iclass 40, count 0 2006.176.07:49:51.26#ibcon#about to read 6, iclass 40, count 0 2006.176.07:49:51.26#ibcon#read 6, iclass 40, count 0 2006.176.07:49:51.26#ibcon#end of sib2, iclass 40, count 0 2006.176.07:49:51.26#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:49:51.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:49:51.26#ibcon#[27=USB\r\n] 2006.176.07:49:51.26#ibcon#*before write, iclass 40, count 0 2006.176.07:49:51.26#ibcon#enter sib2, iclass 40, count 0 2006.176.07:49:51.26#ibcon#flushed, iclass 40, count 0 2006.176.07:49:51.26#ibcon#about to write, iclass 40, count 0 2006.176.07:49:51.26#ibcon#wrote, iclass 40, count 0 2006.176.07:49:51.26#ibcon#about to read 3, iclass 40, count 0 2006.176.07:49:51.29#ibcon#read 3, iclass 40, count 0 2006.176.07:49:51.29#ibcon#about to read 4, iclass 40, count 0 2006.176.07:49:51.29#ibcon#read 4, iclass 40, count 0 2006.176.07:49:51.29#ibcon#about to read 5, iclass 40, count 0 2006.176.07:49:51.29#ibcon#read 5, iclass 40, count 0 2006.176.07:49:51.29#ibcon#about to read 6, iclass 40, count 0 2006.176.07:49:51.29#ibcon#read 6, iclass 40, count 0 2006.176.07:49:51.29#ibcon#end of sib2, iclass 40, count 0 2006.176.07:49:51.29#ibcon#*after write, iclass 40, count 0 2006.176.07:49:51.29#ibcon#*before return 0, iclass 40, count 0 2006.176.07:49:51.29#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:51.29#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:49:51.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:49:51.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:49:51.29$vc4f8/vblo=3,656.99 2006.176.07:49:51.29#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.07:49:51.29#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.07:49:51.29#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:51.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:51.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:51.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:51.29#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:49:51.29#ibcon#first serial, iclass 4, count 0 2006.176.07:49:51.29#ibcon#enter sib2, iclass 4, count 0 2006.176.07:49:51.29#ibcon#flushed, iclass 4, count 0 2006.176.07:49:51.29#ibcon#about to write, iclass 4, count 0 2006.176.07:49:51.29#ibcon#wrote, iclass 4, count 0 2006.176.07:49:51.29#ibcon#about to read 3, iclass 4, count 0 2006.176.07:49:51.31#ibcon#read 3, iclass 4, count 0 2006.176.07:49:51.31#ibcon#about to read 4, iclass 4, count 0 2006.176.07:49:51.31#ibcon#read 4, iclass 4, count 0 2006.176.07:49:51.31#ibcon#about to read 5, iclass 4, count 0 2006.176.07:49:51.31#ibcon#read 5, iclass 4, count 0 2006.176.07:49:51.31#ibcon#about to read 6, iclass 4, count 0 2006.176.07:49:51.31#ibcon#read 6, iclass 4, count 0 2006.176.07:49:51.31#ibcon#end of sib2, iclass 4, count 0 2006.176.07:49:51.31#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:49:51.31#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:49:51.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:49:51.31#ibcon#*before write, iclass 4, count 0 2006.176.07:49:51.31#ibcon#enter sib2, iclass 4, count 0 2006.176.07:49:51.31#ibcon#flushed, iclass 4, count 0 2006.176.07:49:51.31#ibcon#about to write, iclass 4, count 0 2006.176.07:49:51.31#ibcon#wrote, iclass 4, count 0 2006.176.07:49:51.31#ibcon#about to read 3, iclass 4, count 0 2006.176.07:49:51.35#ibcon#read 3, iclass 4, count 0 2006.176.07:49:51.35#ibcon#about to read 4, iclass 4, count 0 2006.176.07:49:51.35#ibcon#read 4, iclass 4, count 0 2006.176.07:49:51.35#ibcon#about to read 5, iclass 4, count 0 2006.176.07:49:51.35#ibcon#read 5, iclass 4, count 0 2006.176.07:49:51.35#ibcon#about to read 6, iclass 4, count 0 2006.176.07:49:51.35#ibcon#read 6, iclass 4, count 0 2006.176.07:49:51.35#ibcon#end of sib2, iclass 4, count 0 2006.176.07:49:51.35#ibcon#*after write, iclass 4, count 0 2006.176.07:49:51.35#ibcon#*before return 0, iclass 4, count 0 2006.176.07:49:51.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:51.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:49:51.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:49:51.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:49:51.35$vc4f8/vb=3,4 2006.176.07:49:51.35#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.07:49:51.35#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.07:49:51.35#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:51.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:51.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:51.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:51.41#ibcon#enter wrdev, iclass 6, count 2 2006.176.07:49:51.41#ibcon#first serial, iclass 6, count 2 2006.176.07:49:51.41#ibcon#enter sib2, iclass 6, count 2 2006.176.07:49:51.41#ibcon#flushed, iclass 6, count 2 2006.176.07:49:51.41#ibcon#about to write, iclass 6, count 2 2006.176.07:49:51.41#ibcon#wrote, iclass 6, count 2 2006.176.07:49:51.41#ibcon#about to read 3, iclass 6, count 2 2006.176.07:49:51.43#ibcon#read 3, iclass 6, count 2 2006.176.07:49:51.43#ibcon#about to read 4, iclass 6, count 2 2006.176.07:49:51.43#ibcon#read 4, iclass 6, count 2 2006.176.07:49:51.43#ibcon#about to read 5, iclass 6, count 2 2006.176.07:49:51.43#ibcon#read 5, iclass 6, count 2 2006.176.07:49:51.43#ibcon#about to read 6, iclass 6, count 2 2006.176.07:49:51.43#ibcon#read 6, iclass 6, count 2 2006.176.07:49:51.43#ibcon#end of sib2, iclass 6, count 2 2006.176.07:49:51.43#ibcon#*mode == 0, iclass 6, count 2 2006.176.07:49:51.43#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.07:49:51.43#ibcon#[27=AT03-04\r\n] 2006.176.07:49:51.43#ibcon#*before write, iclass 6, count 2 2006.176.07:49:51.43#ibcon#enter sib2, iclass 6, count 2 2006.176.07:49:51.43#ibcon#flushed, iclass 6, count 2 2006.176.07:49:51.43#ibcon#about to write, iclass 6, count 2 2006.176.07:49:51.43#ibcon#wrote, iclass 6, count 2 2006.176.07:49:51.43#ibcon#about to read 3, iclass 6, count 2 2006.176.07:49:51.46#ibcon#read 3, iclass 6, count 2 2006.176.07:49:51.46#ibcon#about to read 4, iclass 6, count 2 2006.176.07:49:51.46#ibcon#read 4, iclass 6, count 2 2006.176.07:49:51.46#ibcon#about to read 5, iclass 6, count 2 2006.176.07:49:51.46#ibcon#read 5, iclass 6, count 2 2006.176.07:49:51.46#ibcon#about to read 6, iclass 6, count 2 2006.176.07:49:51.46#ibcon#read 6, iclass 6, count 2 2006.176.07:49:51.46#ibcon#end of sib2, iclass 6, count 2 2006.176.07:49:51.46#ibcon#*after write, iclass 6, count 2 2006.176.07:49:51.46#ibcon#*before return 0, iclass 6, count 2 2006.176.07:49:51.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:51.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:49:51.46#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.07:49:51.46#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:51.46#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:51.58#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:51.58#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:51.58#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:49:51.58#ibcon#first serial, iclass 6, count 0 2006.176.07:49:51.58#ibcon#enter sib2, iclass 6, count 0 2006.176.07:49:51.58#ibcon#flushed, iclass 6, count 0 2006.176.07:49:51.58#ibcon#about to write, iclass 6, count 0 2006.176.07:49:51.58#ibcon#wrote, iclass 6, count 0 2006.176.07:49:51.58#ibcon#about to read 3, iclass 6, count 0 2006.176.07:49:51.60#ibcon#read 3, iclass 6, count 0 2006.176.07:49:51.60#ibcon#about to read 4, iclass 6, count 0 2006.176.07:49:51.60#ibcon#read 4, iclass 6, count 0 2006.176.07:49:51.60#ibcon#about to read 5, iclass 6, count 0 2006.176.07:49:51.60#ibcon#read 5, iclass 6, count 0 2006.176.07:49:51.60#ibcon#about to read 6, iclass 6, count 0 2006.176.07:49:51.60#ibcon#read 6, iclass 6, count 0 2006.176.07:49:51.60#ibcon#end of sib2, iclass 6, count 0 2006.176.07:49:51.60#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:49:51.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:49:51.60#ibcon#[27=USB\r\n] 2006.176.07:49:51.60#ibcon#*before write, iclass 6, count 0 2006.176.07:49:51.60#ibcon#enter sib2, iclass 6, count 0 2006.176.07:49:51.60#ibcon#flushed, iclass 6, count 0 2006.176.07:49:51.60#ibcon#about to write, iclass 6, count 0 2006.176.07:49:51.60#ibcon#wrote, iclass 6, count 0 2006.176.07:49:51.60#ibcon#about to read 3, iclass 6, count 0 2006.176.07:49:51.63#ibcon#read 3, iclass 6, count 0 2006.176.07:49:51.63#ibcon#about to read 4, iclass 6, count 0 2006.176.07:49:51.63#ibcon#read 4, iclass 6, count 0 2006.176.07:49:51.63#ibcon#about to read 5, iclass 6, count 0 2006.176.07:49:51.63#ibcon#read 5, iclass 6, count 0 2006.176.07:49:51.63#ibcon#about to read 6, iclass 6, count 0 2006.176.07:49:51.63#ibcon#read 6, iclass 6, count 0 2006.176.07:49:51.63#ibcon#end of sib2, iclass 6, count 0 2006.176.07:49:51.63#ibcon#*after write, iclass 6, count 0 2006.176.07:49:51.63#ibcon#*before return 0, iclass 6, count 0 2006.176.07:49:51.63#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:51.63#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:49:51.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:49:51.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:49:51.63$vc4f8/vblo=4,712.99 2006.176.07:49:51.63#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.07:49:51.63#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.07:49:51.63#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:51.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:51.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:51.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:51.63#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:49:51.63#ibcon#first serial, iclass 10, count 0 2006.176.07:49:51.63#ibcon#enter sib2, iclass 10, count 0 2006.176.07:49:51.63#ibcon#flushed, iclass 10, count 0 2006.176.07:49:51.63#ibcon#about to write, iclass 10, count 0 2006.176.07:49:51.63#ibcon#wrote, iclass 10, count 0 2006.176.07:49:51.63#ibcon#about to read 3, iclass 10, count 0 2006.176.07:49:51.65#ibcon#read 3, iclass 10, count 0 2006.176.07:49:51.65#ibcon#about to read 4, iclass 10, count 0 2006.176.07:49:51.65#ibcon#read 4, iclass 10, count 0 2006.176.07:49:51.65#ibcon#about to read 5, iclass 10, count 0 2006.176.07:49:51.65#ibcon#read 5, iclass 10, count 0 2006.176.07:49:51.65#ibcon#about to read 6, iclass 10, count 0 2006.176.07:49:51.65#ibcon#read 6, iclass 10, count 0 2006.176.07:49:51.65#ibcon#end of sib2, iclass 10, count 0 2006.176.07:49:51.65#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:49:51.65#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:49:51.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:49:51.65#ibcon#*before write, iclass 10, count 0 2006.176.07:49:51.65#ibcon#enter sib2, iclass 10, count 0 2006.176.07:49:51.65#ibcon#flushed, iclass 10, count 0 2006.176.07:49:51.65#ibcon#about to write, iclass 10, count 0 2006.176.07:49:51.65#ibcon#wrote, iclass 10, count 0 2006.176.07:49:51.65#ibcon#about to read 3, iclass 10, count 0 2006.176.07:49:51.69#ibcon#read 3, iclass 10, count 0 2006.176.07:49:51.69#ibcon#about to read 4, iclass 10, count 0 2006.176.07:49:51.69#ibcon#read 4, iclass 10, count 0 2006.176.07:49:51.69#ibcon#about to read 5, iclass 10, count 0 2006.176.07:49:51.69#ibcon#read 5, iclass 10, count 0 2006.176.07:49:51.69#ibcon#about to read 6, iclass 10, count 0 2006.176.07:49:51.69#ibcon#read 6, iclass 10, count 0 2006.176.07:49:51.69#ibcon#end of sib2, iclass 10, count 0 2006.176.07:49:51.69#ibcon#*after write, iclass 10, count 0 2006.176.07:49:51.69#ibcon#*before return 0, iclass 10, count 0 2006.176.07:49:51.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:51.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:49:51.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:49:51.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:49:51.69$vc4f8/vb=4,4 2006.176.07:49:51.69#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.07:49:51.69#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.07:49:51.69#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:51.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:51.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:51.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:51.75#ibcon#enter wrdev, iclass 12, count 2 2006.176.07:49:51.75#ibcon#first serial, iclass 12, count 2 2006.176.07:49:51.75#ibcon#enter sib2, iclass 12, count 2 2006.176.07:49:51.75#ibcon#flushed, iclass 12, count 2 2006.176.07:49:51.75#ibcon#about to write, iclass 12, count 2 2006.176.07:49:51.75#ibcon#wrote, iclass 12, count 2 2006.176.07:49:51.75#ibcon#about to read 3, iclass 12, count 2 2006.176.07:49:51.77#ibcon#read 3, iclass 12, count 2 2006.176.07:49:51.77#ibcon#about to read 4, iclass 12, count 2 2006.176.07:49:51.77#ibcon#read 4, iclass 12, count 2 2006.176.07:49:51.77#ibcon#about to read 5, iclass 12, count 2 2006.176.07:49:51.77#ibcon#read 5, iclass 12, count 2 2006.176.07:49:51.77#ibcon#about to read 6, iclass 12, count 2 2006.176.07:49:51.77#ibcon#read 6, iclass 12, count 2 2006.176.07:49:51.77#ibcon#end of sib2, iclass 12, count 2 2006.176.07:49:51.77#ibcon#*mode == 0, iclass 12, count 2 2006.176.07:49:51.77#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.07:49:51.77#ibcon#[27=AT04-04\r\n] 2006.176.07:49:51.77#ibcon#*before write, iclass 12, count 2 2006.176.07:49:51.77#ibcon#enter sib2, iclass 12, count 2 2006.176.07:49:51.77#ibcon#flushed, iclass 12, count 2 2006.176.07:49:51.77#ibcon#about to write, iclass 12, count 2 2006.176.07:49:51.77#ibcon#wrote, iclass 12, count 2 2006.176.07:49:51.77#ibcon#about to read 3, iclass 12, count 2 2006.176.07:49:51.80#ibcon#read 3, iclass 12, count 2 2006.176.07:49:51.80#ibcon#about to read 4, iclass 12, count 2 2006.176.07:49:51.80#ibcon#read 4, iclass 12, count 2 2006.176.07:49:51.80#ibcon#about to read 5, iclass 12, count 2 2006.176.07:49:51.80#ibcon#read 5, iclass 12, count 2 2006.176.07:49:51.80#ibcon#about to read 6, iclass 12, count 2 2006.176.07:49:51.80#ibcon#read 6, iclass 12, count 2 2006.176.07:49:51.80#ibcon#end of sib2, iclass 12, count 2 2006.176.07:49:51.80#ibcon#*after write, iclass 12, count 2 2006.176.07:49:51.80#ibcon#*before return 0, iclass 12, count 2 2006.176.07:49:51.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:51.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:49:51.80#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.07:49:51.80#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:51.80#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:51.92#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:51.92#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:51.92#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:49:51.92#ibcon#first serial, iclass 12, count 0 2006.176.07:49:51.92#ibcon#enter sib2, iclass 12, count 0 2006.176.07:49:51.92#ibcon#flushed, iclass 12, count 0 2006.176.07:49:51.92#ibcon#about to write, iclass 12, count 0 2006.176.07:49:51.92#ibcon#wrote, iclass 12, count 0 2006.176.07:49:51.92#ibcon#about to read 3, iclass 12, count 0 2006.176.07:49:51.94#ibcon#read 3, iclass 12, count 0 2006.176.07:49:51.94#ibcon#about to read 4, iclass 12, count 0 2006.176.07:49:51.94#ibcon#read 4, iclass 12, count 0 2006.176.07:49:51.94#ibcon#about to read 5, iclass 12, count 0 2006.176.07:49:51.94#ibcon#read 5, iclass 12, count 0 2006.176.07:49:51.94#ibcon#about to read 6, iclass 12, count 0 2006.176.07:49:51.94#ibcon#read 6, iclass 12, count 0 2006.176.07:49:51.94#ibcon#end of sib2, iclass 12, count 0 2006.176.07:49:51.94#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:49:51.94#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:49:51.94#ibcon#[27=USB\r\n] 2006.176.07:49:51.94#ibcon#*before write, iclass 12, count 0 2006.176.07:49:51.94#ibcon#enter sib2, iclass 12, count 0 2006.176.07:49:51.94#ibcon#flushed, iclass 12, count 0 2006.176.07:49:51.94#ibcon#about to write, iclass 12, count 0 2006.176.07:49:51.94#ibcon#wrote, iclass 12, count 0 2006.176.07:49:51.94#ibcon#about to read 3, iclass 12, count 0 2006.176.07:49:51.97#ibcon#read 3, iclass 12, count 0 2006.176.07:49:51.97#ibcon#about to read 4, iclass 12, count 0 2006.176.07:49:51.97#ibcon#read 4, iclass 12, count 0 2006.176.07:49:51.97#ibcon#about to read 5, iclass 12, count 0 2006.176.07:49:51.97#ibcon#read 5, iclass 12, count 0 2006.176.07:49:51.97#ibcon#about to read 6, iclass 12, count 0 2006.176.07:49:51.97#ibcon#read 6, iclass 12, count 0 2006.176.07:49:51.97#ibcon#end of sib2, iclass 12, count 0 2006.176.07:49:51.97#ibcon#*after write, iclass 12, count 0 2006.176.07:49:51.97#ibcon#*before return 0, iclass 12, count 0 2006.176.07:49:51.97#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:51.97#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:49:51.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:49:51.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:49:51.97$vc4f8/vblo=5,744.99 2006.176.07:49:51.97#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.07:49:51.97#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.07:49:51.97#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:51.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:51.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:51.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:51.97#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:49:51.97#ibcon#first serial, iclass 14, count 0 2006.176.07:49:51.97#ibcon#enter sib2, iclass 14, count 0 2006.176.07:49:51.97#ibcon#flushed, iclass 14, count 0 2006.176.07:49:51.97#ibcon#about to write, iclass 14, count 0 2006.176.07:49:51.97#ibcon#wrote, iclass 14, count 0 2006.176.07:49:51.97#ibcon#about to read 3, iclass 14, count 0 2006.176.07:49:51.99#ibcon#read 3, iclass 14, count 0 2006.176.07:49:51.99#ibcon#about to read 4, iclass 14, count 0 2006.176.07:49:51.99#ibcon#read 4, iclass 14, count 0 2006.176.07:49:51.99#ibcon#about to read 5, iclass 14, count 0 2006.176.07:49:51.99#ibcon#read 5, iclass 14, count 0 2006.176.07:49:51.99#ibcon#about to read 6, iclass 14, count 0 2006.176.07:49:51.99#ibcon#read 6, iclass 14, count 0 2006.176.07:49:51.99#ibcon#end of sib2, iclass 14, count 0 2006.176.07:49:51.99#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:49:51.99#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:49:51.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:49:51.99#ibcon#*before write, iclass 14, count 0 2006.176.07:49:51.99#ibcon#enter sib2, iclass 14, count 0 2006.176.07:49:51.99#ibcon#flushed, iclass 14, count 0 2006.176.07:49:51.99#ibcon#about to write, iclass 14, count 0 2006.176.07:49:51.99#ibcon#wrote, iclass 14, count 0 2006.176.07:49:51.99#ibcon#about to read 3, iclass 14, count 0 2006.176.07:49:52.03#ibcon#read 3, iclass 14, count 0 2006.176.07:49:52.03#ibcon#about to read 4, iclass 14, count 0 2006.176.07:49:52.03#ibcon#read 4, iclass 14, count 0 2006.176.07:49:52.03#ibcon#about to read 5, iclass 14, count 0 2006.176.07:49:52.03#ibcon#read 5, iclass 14, count 0 2006.176.07:49:52.03#ibcon#about to read 6, iclass 14, count 0 2006.176.07:49:52.03#ibcon#read 6, iclass 14, count 0 2006.176.07:49:52.03#ibcon#end of sib2, iclass 14, count 0 2006.176.07:49:52.03#ibcon#*after write, iclass 14, count 0 2006.176.07:49:52.03#ibcon#*before return 0, iclass 14, count 0 2006.176.07:49:52.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:52.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:49:52.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:49:52.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:49:52.03$vc4f8/vb=5,4 2006.176.07:49:52.03#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.07:49:52.03#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.07:49:52.03#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:52.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:52.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:52.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:52.09#ibcon#enter wrdev, iclass 16, count 2 2006.176.07:49:52.09#ibcon#first serial, iclass 16, count 2 2006.176.07:49:52.09#ibcon#enter sib2, iclass 16, count 2 2006.176.07:49:52.09#ibcon#flushed, iclass 16, count 2 2006.176.07:49:52.09#ibcon#about to write, iclass 16, count 2 2006.176.07:49:52.09#ibcon#wrote, iclass 16, count 2 2006.176.07:49:52.09#ibcon#about to read 3, iclass 16, count 2 2006.176.07:49:52.11#ibcon#read 3, iclass 16, count 2 2006.176.07:49:52.11#ibcon#about to read 4, iclass 16, count 2 2006.176.07:49:52.11#ibcon#read 4, iclass 16, count 2 2006.176.07:49:52.11#ibcon#about to read 5, iclass 16, count 2 2006.176.07:49:52.11#ibcon#read 5, iclass 16, count 2 2006.176.07:49:52.11#ibcon#about to read 6, iclass 16, count 2 2006.176.07:49:52.11#ibcon#read 6, iclass 16, count 2 2006.176.07:49:52.11#ibcon#end of sib2, iclass 16, count 2 2006.176.07:49:52.11#ibcon#*mode == 0, iclass 16, count 2 2006.176.07:49:52.11#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.07:49:52.11#ibcon#[27=AT05-04\r\n] 2006.176.07:49:52.11#ibcon#*before write, iclass 16, count 2 2006.176.07:49:52.11#ibcon#enter sib2, iclass 16, count 2 2006.176.07:49:52.11#ibcon#flushed, iclass 16, count 2 2006.176.07:49:52.11#ibcon#about to write, iclass 16, count 2 2006.176.07:49:52.11#ibcon#wrote, iclass 16, count 2 2006.176.07:49:52.11#ibcon#about to read 3, iclass 16, count 2 2006.176.07:49:52.14#ibcon#read 3, iclass 16, count 2 2006.176.07:49:52.14#ibcon#about to read 4, iclass 16, count 2 2006.176.07:49:52.14#ibcon#read 4, iclass 16, count 2 2006.176.07:49:52.14#ibcon#about to read 5, iclass 16, count 2 2006.176.07:49:52.14#ibcon#read 5, iclass 16, count 2 2006.176.07:49:52.14#ibcon#about to read 6, iclass 16, count 2 2006.176.07:49:52.14#ibcon#read 6, iclass 16, count 2 2006.176.07:49:52.14#ibcon#end of sib2, iclass 16, count 2 2006.176.07:49:52.14#ibcon#*after write, iclass 16, count 2 2006.176.07:49:52.14#ibcon#*before return 0, iclass 16, count 2 2006.176.07:49:52.14#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:52.14#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.07:49:52.14#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.07:49:52.14#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:52.14#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:52.26#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:52.26#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:52.26#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:49:52.26#ibcon#first serial, iclass 16, count 0 2006.176.07:49:52.26#ibcon#enter sib2, iclass 16, count 0 2006.176.07:49:52.26#ibcon#flushed, iclass 16, count 0 2006.176.07:49:52.26#ibcon#about to write, iclass 16, count 0 2006.176.07:49:52.26#ibcon#wrote, iclass 16, count 0 2006.176.07:49:52.26#ibcon#about to read 3, iclass 16, count 0 2006.176.07:49:52.28#ibcon#read 3, iclass 16, count 0 2006.176.07:49:52.28#ibcon#about to read 4, iclass 16, count 0 2006.176.07:49:52.28#ibcon#read 4, iclass 16, count 0 2006.176.07:49:52.28#ibcon#about to read 5, iclass 16, count 0 2006.176.07:49:52.28#ibcon#read 5, iclass 16, count 0 2006.176.07:49:52.28#ibcon#about to read 6, iclass 16, count 0 2006.176.07:49:52.28#ibcon#read 6, iclass 16, count 0 2006.176.07:49:52.28#ibcon#end of sib2, iclass 16, count 0 2006.176.07:49:52.28#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:49:52.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:49:52.28#ibcon#[27=USB\r\n] 2006.176.07:49:52.28#ibcon#*before write, iclass 16, count 0 2006.176.07:49:52.28#ibcon#enter sib2, iclass 16, count 0 2006.176.07:49:52.28#ibcon#flushed, iclass 16, count 0 2006.176.07:49:52.28#ibcon#about to write, iclass 16, count 0 2006.176.07:49:52.28#ibcon#wrote, iclass 16, count 0 2006.176.07:49:52.28#ibcon#about to read 3, iclass 16, count 0 2006.176.07:49:52.31#ibcon#read 3, iclass 16, count 0 2006.176.07:49:52.31#ibcon#about to read 4, iclass 16, count 0 2006.176.07:49:52.31#ibcon#read 4, iclass 16, count 0 2006.176.07:49:52.31#ibcon#about to read 5, iclass 16, count 0 2006.176.07:49:52.31#ibcon#read 5, iclass 16, count 0 2006.176.07:49:52.31#ibcon#about to read 6, iclass 16, count 0 2006.176.07:49:52.31#ibcon#read 6, iclass 16, count 0 2006.176.07:49:52.31#ibcon#end of sib2, iclass 16, count 0 2006.176.07:49:52.31#ibcon#*after write, iclass 16, count 0 2006.176.07:49:52.31#ibcon#*before return 0, iclass 16, count 0 2006.176.07:49:52.31#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:52.31#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.07:49:52.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:49:52.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:49:52.31$vc4f8/vblo=6,752.99 2006.176.07:49:52.31#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.07:49:52.31#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.07:49:52.31#ibcon#ireg 17 cls_cnt 0 2006.176.07:49:52.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:52.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:52.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:52.31#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:49:52.31#ibcon#first serial, iclass 18, count 0 2006.176.07:49:52.31#ibcon#enter sib2, iclass 18, count 0 2006.176.07:49:52.31#ibcon#flushed, iclass 18, count 0 2006.176.07:49:52.31#ibcon#about to write, iclass 18, count 0 2006.176.07:49:52.31#ibcon#wrote, iclass 18, count 0 2006.176.07:49:52.31#ibcon#about to read 3, iclass 18, count 0 2006.176.07:49:52.33#ibcon#read 3, iclass 18, count 0 2006.176.07:49:52.33#ibcon#about to read 4, iclass 18, count 0 2006.176.07:49:52.33#ibcon#read 4, iclass 18, count 0 2006.176.07:49:52.33#ibcon#about to read 5, iclass 18, count 0 2006.176.07:49:52.33#ibcon#read 5, iclass 18, count 0 2006.176.07:49:52.33#ibcon#about to read 6, iclass 18, count 0 2006.176.07:49:52.33#ibcon#read 6, iclass 18, count 0 2006.176.07:49:52.33#ibcon#end of sib2, iclass 18, count 0 2006.176.07:49:52.33#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:49:52.33#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:49:52.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:49:52.33#ibcon#*before write, iclass 18, count 0 2006.176.07:49:52.33#ibcon#enter sib2, iclass 18, count 0 2006.176.07:49:52.33#ibcon#flushed, iclass 18, count 0 2006.176.07:49:52.33#ibcon#about to write, iclass 18, count 0 2006.176.07:49:52.33#ibcon#wrote, iclass 18, count 0 2006.176.07:49:52.33#ibcon#about to read 3, iclass 18, count 0 2006.176.07:49:52.37#ibcon#read 3, iclass 18, count 0 2006.176.07:49:52.37#ibcon#about to read 4, iclass 18, count 0 2006.176.07:49:52.37#ibcon#read 4, iclass 18, count 0 2006.176.07:49:52.37#ibcon#about to read 5, iclass 18, count 0 2006.176.07:49:52.37#ibcon#read 5, iclass 18, count 0 2006.176.07:49:52.37#ibcon#about to read 6, iclass 18, count 0 2006.176.07:49:52.37#ibcon#read 6, iclass 18, count 0 2006.176.07:49:52.37#ibcon#end of sib2, iclass 18, count 0 2006.176.07:49:52.37#ibcon#*after write, iclass 18, count 0 2006.176.07:49:52.37#ibcon#*before return 0, iclass 18, count 0 2006.176.07:49:52.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:52.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.07:49:52.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:49:52.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:49:52.37$vc4f8/vb=6,4 2006.176.07:49:52.37#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.07:49:52.37#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.07:49:52.37#ibcon#ireg 11 cls_cnt 2 2006.176.07:49:52.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:52.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:52.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:52.43#ibcon#enter wrdev, iclass 20, count 2 2006.176.07:49:52.43#ibcon#first serial, iclass 20, count 2 2006.176.07:49:52.43#ibcon#enter sib2, iclass 20, count 2 2006.176.07:49:52.43#ibcon#flushed, iclass 20, count 2 2006.176.07:49:52.43#ibcon#about to write, iclass 20, count 2 2006.176.07:49:52.43#ibcon#wrote, iclass 20, count 2 2006.176.07:49:52.43#ibcon#about to read 3, iclass 20, count 2 2006.176.07:49:52.45#ibcon#read 3, iclass 20, count 2 2006.176.07:49:52.45#ibcon#about to read 4, iclass 20, count 2 2006.176.07:49:52.45#ibcon#read 4, iclass 20, count 2 2006.176.07:49:52.45#ibcon#about to read 5, iclass 20, count 2 2006.176.07:49:52.45#ibcon#read 5, iclass 20, count 2 2006.176.07:49:52.45#ibcon#about to read 6, iclass 20, count 2 2006.176.07:49:52.45#ibcon#read 6, iclass 20, count 2 2006.176.07:49:52.45#ibcon#end of sib2, iclass 20, count 2 2006.176.07:49:52.45#ibcon#*mode == 0, iclass 20, count 2 2006.176.07:49:52.45#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.07:49:52.45#ibcon#[27=AT06-04\r\n] 2006.176.07:49:52.45#ibcon#*before write, iclass 20, count 2 2006.176.07:49:52.45#ibcon#enter sib2, iclass 20, count 2 2006.176.07:49:52.45#ibcon#flushed, iclass 20, count 2 2006.176.07:49:52.45#ibcon#about to write, iclass 20, count 2 2006.176.07:49:52.45#ibcon#wrote, iclass 20, count 2 2006.176.07:49:52.45#ibcon#about to read 3, iclass 20, count 2 2006.176.07:49:52.48#ibcon#read 3, iclass 20, count 2 2006.176.07:49:52.48#ibcon#about to read 4, iclass 20, count 2 2006.176.07:49:52.48#ibcon#read 4, iclass 20, count 2 2006.176.07:49:52.48#ibcon#about to read 5, iclass 20, count 2 2006.176.07:49:52.48#ibcon#read 5, iclass 20, count 2 2006.176.07:49:52.48#ibcon#about to read 6, iclass 20, count 2 2006.176.07:49:52.48#ibcon#read 6, iclass 20, count 2 2006.176.07:49:52.48#ibcon#end of sib2, iclass 20, count 2 2006.176.07:49:52.48#ibcon#*after write, iclass 20, count 2 2006.176.07:49:52.48#ibcon#*before return 0, iclass 20, count 2 2006.176.07:49:52.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:52.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.07:49:52.48#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.07:49:52.48#ibcon#ireg 7 cls_cnt 0 2006.176.07:49:52.48#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:52.60#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:52.60#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:52.60#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:49:52.60#ibcon#first serial, iclass 20, count 0 2006.176.07:49:52.60#ibcon#enter sib2, iclass 20, count 0 2006.176.07:49:52.60#ibcon#flushed, iclass 20, count 0 2006.176.07:49:52.60#ibcon#about to write, iclass 20, count 0 2006.176.07:49:52.60#ibcon#wrote, iclass 20, count 0 2006.176.07:49:52.60#ibcon#about to read 3, iclass 20, count 0 2006.176.07:49:52.62#ibcon#read 3, iclass 20, count 0 2006.176.07:49:52.62#ibcon#about to read 4, iclass 20, count 0 2006.176.07:49:52.62#ibcon#read 4, iclass 20, count 0 2006.176.07:49:52.62#ibcon#about to read 5, iclass 20, count 0 2006.176.07:49:52.62#ibcon#read 5, iclass 20, count 0 2006.176.07:49:52.62#ibcon#about to read 6, iclass 20, count 0 2006.176.07:49:52.62#ibcon#read 6, iclass 20, count 0 2006.176.07:49:52.62#ibcon#end of sib2, iclass 20, count 0 2006.176.07:49:52.62#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:49:52.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:49:52.62#ibcon#[27=USB\r\n] 2006.176.07:49:52.62#ibcon#*before write, iclass 20, count 0 2006.176.07:49:52.62#ibcon#enter sib2, iclass 20, count 0 2006.176.07:49:52.62#ibcon#flushed, iclass 20, count 0 2006.176.07:49:52.62#ibcon#about to write, iclass 20, count 0 2006.176.07:49:52.62#ibcon#wrote, iclass 20, count 0 2006.176.07:49:52.62#ibcon#about to read 3, iclass 20, count 0 2006.176.07:49:52.65#ibcon#read 3, iclass 20, count 0 2006.176.07:49:52.65#ibcon#about to read 4, iclass 20, count 0 2006.176.07:49:52.65#ibcon#read 4, iclass 20, count 0 2006.176.07:49:52.65#ibcon#about to read 5, iclass 20, count 0 2006.176.07:49:52.65#ibcon#read 5, iclass 20, count 0 2006.176.07:49:52.65#ibcon#about to read 6, iclass 20, count 0 2006.176.07:49:52.65#ibcon#read 6, iclass 20, count 0 2006.176.07:49:52.65#ibcon#end of sib2, iclass 20, count 0 2006.176.07:49:52.65#ibcon#*after write, iclass 20, count 0 2006.176.07:49:52.65#ibcon#*before return 0, iclass 20, count 0 2006.176.07:49:52.65#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:52.65#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.07:49:52.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:49:52.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:49:52.65$vc4f8/vabw=wide 2006.176.07:49:52.65#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.07:49:52.65#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.07:49:52.65#ibcon#ireg 8 cls_cnt 0 2006.176.07:49:52.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:52.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:52.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:52.65#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:49:52.65#ibcon#first serial, iclass 22, count 0 2006.176.07:49:52.65#ibcon#enter sib2, iclass 22, count 0 2006.176.07:49:52.65#ibcon#flushed, iclass 22, count 0 2006.176.07:49:52.65#ibcon#about to write, iclass 22, count 0 2006.176.07:49:52.65#ibcon#wrote, iclass 22, count 0 2006.176.07:49:52.65#ibcon#about to read 3, iclass 22, count 0 2006.176.07:49:52.67#ibcon#read 3, iclass 22, count 0 2006.176.07:49:52.67#ibcon#about to read 4, iclass 22, count 0 2006.176.07:49:52.67#ibcon#read 4, iclass 22, count 0 2006.176.07:49:52.67#ibcon#about to read 5, iclass 22, count 0 2006.176.07:49:52.67#ibcon#read 5, iclass 22, count 0 2006.176.07:49:52.67#ibcon#about to read 6, iclass 22, count 0 2006.176.07:49:52.67#ibcon#read 6, iclass 22, count 0 2006.176.07:49:52.67#ibcon#end of sib2, iclass 22, count 0 2006.176.07:49:52.67#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:49:52.67#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:49:52.67#ibcon#[25=BW32\r\n] 2006.176.07:49:52.67#ibcon#*before write, iclass 22, count 0 2006.176.07:49:52.67#ibcon#enter sib2, iclass 22, count 0 2006.176.07:49:52.67#ibcon#flushed, iclass 22, count 0 2006.176.07:49:52.67#ibcon#about to write, iclass 22, count 0 2006.176.07:49:52.67#ibcon#wrote, iclass 22, count 0 2006.176.07:49:52.67#ibcon#about to read 3, iclass 22, count 0 2006.176.07:49:52.70#ibcon#read 3, iclass 22, count 0 2006.176.07:49:52.70#ibcon#about to read 4, iclass 22, count 0 2006.176.07:49:52.70#ibcon#read 4, iclass 22, count 0 2006.176.07:49:52.70#ibcon#about to read 5, iclass 22, count 0 2006.176.07:49:52.70#ibcon#read 5, iclass 22, count 0 2006.176.07:49:52.70#ibcon#about to read 6, iclass 22, count 0 2006.176.07:49:52.70#ibcon#read 6, iclass 22, count 0 2006.176.07:49:52.70#ibcon#end of sib2, iclass 22, count 0 2006.176.07:49:52.70#ibcon#*after write, iclass 22, count 0 2006.176.07:49:52.70#ibcon#*before return 0, iclass 22, count 0 2006.176.07:49:52.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:52.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.07:49:52.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:49:52.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:49:52.70$vc4f8/vbbw=wide 2006.176.07:49:52.70#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.07:49:52.70#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.07:49:52.70#ibcon#ireg 8 cls_cnt 0 2006.176.07:49:52.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:49:52.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:49:52.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:49:52.77#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:49:52.77#ibcon#first serial, iclass 24, count 0 2006.176.07:49:52.77#ibcon#enter sib2, iclass 24, count 0 2006.176.07:49:52.77#ibcon#flushed, iclass 24, count 0 2006.176.07:49:52.77#ibcon#about to write, iclass 24, count 0 2006.176.07:49:52.77#ibcon#wrote, iclass 24, count 0 2006.176.07:49:52.77#ibcon#about to read 3, iclass 24, count 0 2006.176.07:49:52.79#ibcon#read 3, iclass 24, count 0 2006.176.07:49:52.79#ibcon#about to read 4, iclass 24, count 0 2006.176.07:49:52.79#ibcon#read 4, iclass 24, count 0 2006.176.07:49:52.79#ibcon#about to read 5, iclass 24, count 0 2006.176.07:49:52.79#ibcon#read 5, iclass 24, count 0 2006.176.07:49:52.79#ibcon#about to read 6, iclass 24, count 0 2006.176.07:49:52.79#ibcon#read 6, iclass 24, count 0 2006.176.07:49:52.79#ibcon#end of sib2, iclass 24, count 0 2006.176.07:49:52.79#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:49:52.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:49:52.79#ibcon#[27=BW32\r\n] 2006.176.07:49:52.79#ibcon#*before write, iclass 24, count 0 2006.176.07:49:52.79#ibcon#enter sib2, iclass 24, count 0 2006.176.07:49:52.79#ibcon#flushed, iclass 24, count 0 2006.176.07:49:52.79#ibcon#about to write, iclass 24, count 0 2006.176.07:49:52.79#ibcon#wrote, iclass 24, count 0 2006.176.07:49:52.79#ibcon#about to read 3, iclass 24, count 0 2006.176.07:49:52.82#ibcon#read 3, iclass 24, count 0 2006.176.07:49:52.82#ibcon#about to read 4, iclass 24, count 0 2006.176.07:49:52.82#ibcon#read 4, iclass 24, count 0 2006.176.07:49:52.82#ibcon#about to read 5, iclass 24, count 0 2006.176.07:49:52.82#ibcon#read 5, iclass 24, count 0 2006.176.07:49:52.82#ibcon#about to read 6, iclass 24, count 0 2006.176.07:49:52.82#ibcon#read 6, iclass 24, count 0 2006.176.07:49:52.82#ibcon#end of sib2, iclass 24, count 0 2006.176.07:49:52.82#ibcon#*after write, iclass 24, count 0 2006.176.07:49:52.82#ibcon#*before return 0, iclass 24, count 0 2006.176.07:49:52.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:49:52.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:49:52.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:49:52.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:49:52.82$4f8m12a/ifd4f 2006.176.07:49:52.82$ifd4f/lo= 2006.176.07:49:52.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:49:52.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:49:52.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:49:52.82$ifd4f/patch= 2006.176.07:49:52.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:49:52.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:49:52.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:49:52.82$4f8m12a/"form=m,16.000,1:2 2006.176.07:49:52.82$4f8m12a/"tpicd 2006.176.07:49:52.82$4f8m12a/echo=off 2006.176.07:49:52.82$4f8m12a/xlog=off 2006.176.07:49:52.82:!2006.176.07:50:20 2006.176.07:50:04.13#trakl#Source acquired 2006.176.07:50:05.13#flagr#flagr/antenna,acquired 2006.176.07:50:20.00:preob 2006.176.07:50:21.13/onsource/TRACKING 2006.176.07:50:21.13:!2006.176.07:50:30 2006.176.07:50:30.00:data_valid=on 2006.176.07:50:30.00:midob 2006.176.07:50:30.13/onsource/TRACKING 2006.176.07:50:30.13/wx/23.87,1008.3,91 2006.176.07:50:30.21/cable/+6.4929E-03 2006.176.07:50:31.30/va/01,08,usb,yes,29,31 2006.176.07:50:31.30/va/02,07,usb,yes,29,31 2006.176.07:50:31.30/va/03,06,usb,yes,31,31 2006.176.07:50:31.30/va/04,07,usb,yes,30,32 2006.176.07:50:31.30/va/05,07,usb,yes,31,33 2006.176.07:50:31.30/va/06,06,usb,yes,31,30 2006.176.07:50:31.30/va/07,06,usb,yes,31,31 2006.176.07:50:31.30/va/08,06,usb,yes,33,33 2006.176.07:50:31.53/valo/01,532.99,yes,locked 2006.176.07:50:31.53/valo/02,572.99,yes,locked 2006.176.07:50:31.53/valo/03,672.99,yes,locked 2006.176.07:50:31.53/valo/04,832.99,yes,locked 2006.176.07:50:31.53/valo/05,652.99,yes,locked 2006.176.07:50:31.53/valo/06,772.99,yes,locked 2006.176.07:50:31.53/valo/07,832.99,yes,locked 2006.176.07:50:31.53/valo/08,852.99,yes,locked 2006.176.07:50:32.62/vb/01,04,usb,yes,29,28 2006.176.07:50:32.62/vb/02,04,usb,yes,31,32 2006.176.07:50:32.62/vb/03,04,usb,yes,27,31 2006.176.07:50:32.62/vb/04,04,usb,yes,28,28 2006.176.07:50:32.62/vb/05,04,usb,yes,27,31 2006.176.07:50:32.62/vb/06,04,usb,yes,28,30 2006.176.07:50:32.62/vb/07,04,usb,yes,30,30 2006.176.07:50:32.62/vb/08,04,usb,yes,27,31 2006.176.07:50:32.86/vblo/01,632.99,yes,locked 2006.176.07:50:32.86/vblo/02,640.99,yes,locked 2006.176.07:50:32.86/vblo/03,656.99,yes,locked 2006.176.07:50:32.86/vblo/04,712.99,yes,locked 2006.176.07:50:32.86/vblo/05,744.99,yes,locked 2006.176.07:50:32.86/vblo/06,752.99,yes,locked 2006.176.07:50:32.86/vblo/07,734.99,yes,locked 2006.176.07:50:32.86/vblo/08,744.99,yes,locked 2006.176.07:50:33.01/vabw/8 2006.176.07:50:33.16/vbbw/8 2006.176.07:50:33.25/xfe/off,on,16.0 2006.176.07:50:33.62/ifatt/23,28,28,28 2006.176.07:50:34.08/fmout-gps/S +3.74E-07 2006.176.07:50:34.15:!2006.176.07:51:30 2006.176.07:51:30.00:data_valid=off 2006.176.07:51:30.00:postob 2006.176.07:51:30.22/cable/+6.4931E-03 2006.176.07:51:30.22/wx/23.87,1008.4,92 2006.176.07:51:31.08/fmout-gps/S +3.75E-07 2006.176.07:51:31.08:scan_name=176-0752,k06176,60 2006.176.07:51:31.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.176.07:51:31.14#flagr#flagr/antenna,new-source 2006.176.07:51:32.14:checkk5 2006.176.07:51:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:51:32.87/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:51:33.25/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:51:33.68/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:51:34.05/chk_obsdata//k5ts1/T1760750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:51:34.42/chk_obsdata//k5ts2/T1760750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:51:34.78/chk_obsdata//k5ts3/T1760750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:51:35.15/chk_obsdata//k5ts4/T1760750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:51:35.85/k5log//k5ts1_log_newline 2006.176.07:51:36.54/k5log//k5ts2_log_newline 2006.176.07:51:37.22/k5log//k5ts3_log_newline 2006.176.07:51:37.91/k5log//k5ts4_log_newline 2006.176.07:51:37.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:51:37.94:4f8m12a=1 2006.176.07:51:37.94$4f8m12a/echo=on 2006.176.07:51:37.94$4f8m12a/pcalon 2006.176.07:51:37.94$pcalon/"no phase cal control is implemented here 2006.176.07:51:37.94$4f8m12a/"tpicd=stop 2006.176.07:51:37.94$4f8m12a/vc4f8 2006.176.07:51:37.94$vc4f8/valo=1,532.99 2006.176.07:51:37.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.07:51:37.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.07:51:37.94#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:37.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:51:37.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:51:37.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:51:37.94#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:51:37.94#ibcon#first serial, iclass 28, count 0 2006.176.07:51:37.94#ibcon#enter sib2, iclass 28, count 0 2006.176.07:51:37.94#ibcon#flushed, iclass 28, count 0 2006.176.07:51:37.94#ibcon#about to write, iclass 28, count 0 2006.176.07:51:37.94#ibcon#wrote, iclass 28, count 0 2006.176.07:51:37.94#ibcon#about to read 3, iclass 28, count 0 2006.176.07:51:37.98#ibcon#read 3, iclass 28, count 0 2006.176.07:51:37.98#ibcon#about to read 4, iclass 28, count 0 2006.176.07:51:37.98#ibcon#read 4, iclass 28, count 0 2006.176.07:51:37.98#ibcon#about to read 5, iclass 28, count 0 2006.176.07:51:37.98#ibcon#read 5, iclass 28, count 0 2006.176.07:51:37.98#ibcon#about to read 6, iclass 28, count 0 2006.176.07:51:37.98#ibcon#read 6, iclass 28, count 0 2006.176.07:51:37.98#ibcon#end of sib2, iclass 28, count 0 2006.176.07:51:37.98#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:51:37.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:51:37.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:51:37.98#ibcon#*before write, iclass 28, count 0 2006.176.07:51:37.98#ibcon#enter sib2, iclass 28, count 0 2006.176.07:51:37.98#ibcon#flushed, iclass 28, count 0 2006.176.07:51:37.98#ibcon#about to write, iclass 28, count 0 2006.176.07:51:37.98#ibcon#wrote, iclass 28, count 0 2006.176.07:51:37.98#ibcon#about to read 3, iclass 28, count 0 2006.176.07:51:38.03#ibcon#read 3, iclass 28, count 0 2006.176.07:51:38.03#ibcon#about to read 4, iclass 28, count 0 2006.176.07:51:38.03#ibcon#read 4, iclass 28, count 0 2006.176.07:51:38.03#ibcon#about to read 5, iclass 28, count 0 2006.176.07:51:38.03#ibcon#read 5, iclass 28, count 0 2006.176.07:51:38.03#ibcon#about to read 6, iclass 28, count 0 2006.176.07:51:38.03#ibcon#read 6, iclass 28, count 0 2006.176.07:51:38.03#ibcon#end of sib2, iclass 28, count 0 2006.176.07:51:38.03#ibcon#*after write, iclass 28, count 0 2006.176.07:51:38.03#ibcon#*before return 0, iclass 28, count 0 2006.176.07:51:38.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:51:38.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:51:38.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:51:38.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:51:38.03$vc4f8/va=1,8 2006.176.07:51:38.03#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.07:51:38.03#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.07:51:38.03#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:38.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:51:38.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:51:38.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:51:38.03#ibcon#enter wrdev, iclass 30, count 2 2006.176.07:51:38.03#ibcon#first serial, iclass 30, count 2 2006.176.07:51:38.03#ibcon#enter sib2, iclass 30, count 2 2006.176.07:51:38.03#ibcon#flushed, iclass 30, count 2 2006.176.07:51:38.03#ibcon#about to write, iclass 30, count 2 2006.176.07:51:38.03#ibcon#wrote, iclass 30, count 2 2006.176.07:51:38.03#ibcon#about to read 3, iclass 30, count 2 2006.176.07:51:38.05#ibcon#read 3, iclass 30, count 2 2006.176.07:51:38.05#ibcon#about to read 4, iclass 30, count 2 2006.176.07:51:38.05#ibcon#read 4, iclass 30, count 2 2006.176.07:51:38.05#ibcon#about to read 5, iclass 30, count 2 2006.176.07:51:38.05#ibcon#read 5, iclass 30, count 2 2006.176.07:51:38.05#ibcon#about to read 6, iclass 30, count 2 2006.176.07:51:38.05#ibcon#read 6, iclass 30, count 2 2006.176.07:51:38.05#ibcon#end of sib2, iclass 30, count 2 2006.176.07:51:38.05#ibcon#*mode == 0, iclass 30, count 2 2006.176.07:51:38.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.07:51:38.05#ibcon#[25=AT01-08\r\n] 2006.176.07:51:38.05#ibcon#*before write, iclass 30, count 2 2006.176.07:51:38.05#ibcon#enter sib2, iclass 30, count 2 2006.176.07:51:38.05#ibcon#flushed, iclass 30, count 2 2006.176.07:51:38.05#ibcon#about to write, iclass 30, count 2 2006.176.07:51:38.05#ibcon#wrote, iclass 30, count 2 2006.176.07:51:38.05#ibcon#about to read 3, iclass 30, count 2 2006.176.07:51:38.08#ibcon#read 3, iclass 30, count 2 2006.176.07:51:38.08#ibcon#about to read 4, iclass 30, count 2 2006.176.07:51:38.08#ibcon#read 4, iclass 30, count 2 2006.176.07:51:38.08#ibcon#about to read 5, iclass 30, count 2 2006.176.07:51:38.08#ibcon#read 5, iclass 30, count 2 2006.176.07:51:38.08#ibcon#about to read 6, iclass 30, count 2 2006.176.07:51:38.08#ibcon#read 6, iclass 30, count 2 2006.176.07:51:38.08#ibcon#end of sib2, iclass 30, count 2 2006.176.07:51:38.08#ibcon#*after write, iclass 30, count 2 2006.176.07:51:38.08#ibcon#*before return 0, iclass 30, count 2 2006.176.07:51:38.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:51:38.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:51:38.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.07:51:38.08#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:38.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:51:38.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:51:38.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:51:38.20#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:51:38.20#ibcon#first serial, iclass 30, count 0 2006.176.07:51:38.20#ibcon#enter sib2, iclass 30, count 0 2006.176.07:51:38.20#ibcon#flushed, iclass 30, count 0 2006.176.07:51:38.20#ibcon#about to write, iclass 30, count 0 2006.176.07:51:38.20#ibcon#wrote, iclass 30, count 0 2006.176.07:51:38.20#ibcon#about to read 3, iclass 30, count 0 2006.176.07:51:38.22#ibcon#read 3, iclass 30, count 0 2006.176.07:51:38.22#ibcon#about to read 4, iclass 30, count 0 2006.176.07:51:38.22#ibcon#read 4, iclass 30, count 0 2006.176.07:51:38.22#ibcon#about to read 5, iclass 30, count 0 2006.176.07:51:38.22#ibcon#read 5, iclass 30, count 0 2006.176.07:51:38.22#ibcon#about to read 6, iclass 30, count 0 2006.176.07:51:38.22#ibcon#read 6, iclass 30, count 0 2006.176.07:51:38.22#ibcon#end of sib2, iclass 30, count 0 2006.176.07:51:38.22#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:51:38.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:51:38.22#ibcon#[25=USB\r\n] 2006.176.07:51:38.22#ibcon#*before write, iclass 30, count 0 2006.176.07:51:38.22#ibcon#enter sib2, iclass 30, count 0 2006.176.07:51:38.22#ibcon#flushed, iclass 30, count 0 2006.176.07:51:38.22#ibcon#about to write, iclass 30, count 0 2006.176.07:51:38.22#ibcon#wrote, iclass 30, count 0 2006.176.07:51:38.22#ibcon#about to read 3, iclass 30, count 0 2006.176.07:51:38.25#ibcon#read 3, iclass 30, count 0 2006.176.07:51:38.25#ibcon#about to read 4, iclass 30, count 0 2006.176.07:51:38.25#ibcon#read 4, iclass 30, count 0 2006.176.07:51:38.25#ibcon#about to read 5, iclass 30, count 0 2006.176.07:51:38.25#ibcon#read 5, iclass 30, count 0 2006.176.07:51:38.25#ibcon#about to read 6, iclass 30, count 0 2006.176.07:51:38.25#ibcon#read 6, iclass 30, count 0 2006.176.07:51:38.25#ibcon#end of sib2, iclass 30, count 0 2006.176.07:51:38.25#ibcon#*after write, iclass 30, count 0 2006.176.07:51:38.25#ibcon#*before return 0, iclass 30, count 0 2006.176.07:51:38.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:51:38.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:51:38.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:51:38.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:51:38.25$vc4f8/valo=2,572.99 2006.176.07:51:38.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.07:51:38.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.07:51:38.25#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:38.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:51:38.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:51:38.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:51:38.25#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:51:38.25#ibcon#first serial, iclass 32, count 0 2006.176.07:51:38.25#ibcon#enter sib2, iclass 32, count 0 2006.176.07:51:38.25#ibcon#flushed, iclass 32, count 0 2006.176.07:51:38.25#ibcon#about to write, iclass 32, count 0 2006.176.07:51:38.25#ibcon#wrote, iclass 32, count 0 2006.176.07:51:38.25#ibcon#about to read 3, iclass 32, count 0 2006.176.07:51:38.27#ibcon#read 3, iclass 32, count 0 2006.176.07:51:38.27#ibcon#about to read 4, iclass 32, count 0 2006.176.07:51:38.27#ibcon#read 4, iclass 32, count 0 2006.176.07:51:38.27#ibcon#about to read 5, iclass 32, count 0 2006.176.07:51:38.27#ibcon#read 5, iclass 32, count 0 2006.176.07:51:38.27#ibcon#about to read 6, iclass 32, count 0 2006.176.07:51:38.27#ibcon#read 6, iclass 32, count 0 2006.176.07:51:38.27#ibcon#end of sib2, iclass 32, count 0 2006.176.07:51:38.27#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:51:38.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:51:38.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:51:38.27#ibcon#*before write, iclass 32, count 0 2006.176.07:51:38.27#ibcon#enter sib2, iclass 32, count 0 2006.176.07:51:38.27#ibcon#flushed, iclass 32, count 0 2006.176.07:51:38.27#ibcon#about to write, iclass 32, count 0 2006.176.07:51:38.27#ibcon#wrote, iclass 32, count 0 2006.176.07:51:38.27#ibcon#about to read 3, iclass 32, count 0 2006.176.07:51:38.31#ibcon#read 3, iclass 32, count 0 2006.176.07:51:38.31#ibcon#about to read 4, iclass 32, count 0 2006.176.07:51:38.31#ibcon#read 4, iclass 32, count 0 2006.176.07:51:38.31#ibcon#about to read 5, iclass 32, count 0 2006.176.07:51:38.31#ibcon#read 5, iclass 32, count 0 2006.176.07:51:38.31#ibcon#about to read 6, iclass 32, count 0 2006.176.07:51:38.31#ibcon#read 6, iclass 32, count 0 2006.176.07:51:38.31#ibcon#end of sib2, iclass 32, count 0 2006.176.07:51:38.31#ibcon#*after write, iclass 32, count 0 2006.176.07:51:38.31#ibcon#*before return 0, iclass 32, count 0 2006.176.07:51:38.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:51:38.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:51:38.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:51:38.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:51:38.31$vc4f8/va=2,7 2006.176.07:51:38.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.07:51:38.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.07:51:38.31#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:38.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:51:38.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:51:38.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:51:38.37#ibcon#enter wrdev, iclass 34, count 2 2006.176.07:51:38.37#ibcon#first serial, iclass 34, count 2 2006.176.07:51:38.37#ibcon#enter sib2, iclass 34, count 2 2006.176.07:51:38.37#ibcon#flushed, iclass 34, count 2 2006.176.07:51:38.37#ibcon#about to write, iclass 34, count 2 2006.176.07:51:38.37#ibcon#wrote, iclass 34, count 2 2006.176.07:51:38.37#ibcon#about to read 3, iclass 34, count 2 2006.176.07:51:38.39#ibcon#read 3, iclass 34, count 2 2006.176.07:51:38.39#ibcon#about to read 4, iclass 34, count 2 2006.176.07:51:38.39#ibcon#read 4, iclass 34, count 2 2006.176.07:51:38.39#ibcon#about to read 5, iclass 34, count 2 2006.176.07:51:38.39#ibcon#read 5, iclass 34, count 2 2006.176.07:51:38.39#ibcon#about to read 6, iclass 34, count 2 2006.176.07:51:38.39#ibcon#read 6, iclass 34, count 2 2006.176.07:51:38.39#ibcon#end of sib2, iclass 34, count 2 2006.176.07:51:38.39#ibcon#*mode == 0, iclass 34, count 2 2006.176.07:51:38.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.07:51:38.39#ibcon#[25=AT02-07\r\n] 2006.176.07:51:38.39#ibcon#*before write, iclass 34, count 2 2006.176.07:51:38.39#ibcon#enter sib2, iclass 34, count 2 2006.176.07:51:38.39#ibcon#flushed, iclass 34, count 2 2006.176.07:51:38.39#ibcon#about to write, iclass 34, count 2 2006.176.07:51:38.39#ibcon#wrote, iclass 34, count 2 2006.176.07:51:38.39#ibcon#about to read 3, iclass 34, count 2 2006.176.07:51:38.42#ibcon#read 3, iclass 34, count 2 2006.176.07:51:38.42#ibcon#about to read 4, iclass 34, count 2 2006.176.07:51:38.42#ibcon#read 4, iclass 34, count 2 2006.176.07:51:38.42#ibcon#about to read 5, iclass 34, count 2 2006.176.07:51:38.42#ibcon#read 5, iclass 34, count 2 2006.176.07:51:38.42#ibcon#about to read 6, iclass 34, count 2 2006.176.07:51:38.42#ibcon#read 6, iclass 34, count 2 2006.176.07:51:38.42#ibcon#end of sib2, iclass 34, count 2 2006.176.07:51:38.42#ibcon#*after write, iclass 34, count 2 2006.176.07:51:38.42#ibcon#*before return 0, iclass 34, count 2 2006.176.07:51:38.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:51:38.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:51:38.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.07:51:38.42#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:38.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:51:38.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:51:38.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:51:38.54#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:51:38.54#ibcon#first serial, iclass 34, count 0 2006.176.07:51:38.54#ibcon#enter sib2, iclass 34, count 0 2006.176.07:51:38.54#ibcon#flushed, iclass 34, count 0 2006.176.07:51:38.54#ibcon#about to write, iclass 34, count 0 2006.176.07:51:38.54#ibcon#wrote, iclass 34, count 0 2006.176.07:51:38.54#ibcon#about to read 3, iclass 34, count 0 2006.176.07:51:38.56#ibcon#read 3, iclass 34, count 0 2006.176.07:51:38.56#ibcon#about to read 4, iclass 34, count 0 2006.176.07:51:38.56#ibcon#read 4, iclass 34, count 0 2006.176.07:51:38.56#ibcon#about to read 5, iclass 34, count 0 2006.176.07:51:38.56#ibcon#read 5, iclass 34, count 0 2006.176.07:51:38.56#ibcon#about to read 6, iclass 34, count 0 2006.176.07:51:38.56#ibcon#read 6, iclass 34, count 0 2006.176.07:51:38.56#ibcon#end of sib2, iclass 34, count 0 2006.176.07:51:38.56#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:51:38.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:51:38.56#ibcon#[25=USB\r\n] 2006.176.07:51:38.56#ibcon#*before write, iclass 34, count 0 2006.176.07:51:38.56#ibcon#enter sib2, iclass 34, count 0 2006.176.07:51:38.56#ibcon#flushed, iclass 34, count 0 2006.176.07:51:38.56#ibcon#about to write, iclass 34, count 0 2006.176.07:51:38.56#ibcon#wrote, iclass 34, count 0 2006.176.07:51:38.56#ibcon#about to read 3, iclass 34, count 0 2006.176.07:51:38.59#ibcon#read 3, iclass 34, count 0 2006.176.07:51:38.59#ibcon#about to read 4, iclass 34, count 0 2006.176.07:51:38.59#ibcon#read 4, iclass 34, count 0 2006.176.07:51:38.59#ibcon#about to read 5, iclass 34, count 0 2006.176.07:51:38.59#ibcon#read 5, iclass 34, count 0 2006.176.07:51:38.59#ibcon#about to read 6, iclass 34, count 0 2006.176.07:51:38.59#ibcon#read 6, iclass 34, count 0 2006.176.07:51:38.59#ibcon#end of sib2, iclass 34, count 0 2006.176.07:51:38.59#ibcon#*after write, iclass 34, count 0 2006.176.07:51:38.59#ibcon#*before return 0, iclass 34, count 0 2006.176.07:51:38.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:51:38.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:51:38.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:51:38.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:51:38.59$vc4f8/valo=3,672.99 2006.176.07:51:38.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.07:51:38.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.07:51:38.59#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:38.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:51:38.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:51:38.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:51:38.59#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:51:38.59#ibcon#first serial, iclass 36, count 0 2006.176.07:51:38.59#ibcon#enter sib2, iclass 36, count 0 2006.176.07:51:38.59#ibcon#flushed, iclass 36, count 0 2006.176.07:51:38.59#ibcon#about to write, iclass 36, count 0 2006.176.07:51:38.59#ibcon#wrote, iclass 36, count 0 2006.176.07:51:38.59#ibcon#about to read 3, iclass 36, count 0 2006.176.07:51:38.61#ibcon#read 3, iclass 36, count 0 2006.176.07:51:38.61#ibcon#about to read 4, iclass 36, count 0 2006.176.07:51:38.61#ibcon#read 4, iclass 36, count 0 2006.176.07:51:38.61#ibcon#about to read 5, iclass 36, count 0 2006.176.07:51:38.61#ibcon#read 5, iclass 36, count 0 2006.176.07:51:38.61#ibcon#about to read 6, iclass 36, count 0 2006.176.07:51:38.61#ibcon#read 6, iclass 36, count 0 2006.176.07:51:38.61#ibcon#end of sib2, iclass 36, count 0 2006.176.07:51:38.61#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:51:38.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:51:38.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:51:38.61#ibcon#*before write, iclass 36, count 0 2006.176.07:51:38.61#ibcon#enter sib2, iclass 36, count 0 2006.176.07:51:38.61#ibcon#flushed, iclass 36, count 0 2006.176.07:51:38.61#ibcon#about to write, iclass 36, count 0 2006.176.07:51:38.61#ibcon#wrote, iclass 36, count 0 2006.176.07:51:38.61#ibcon#about to read 3, iclass 36, count 0 2006.176.07:51:38.65#ibcon#read 3, iclass 36, count 0 2006.176.07:51:38.65#ibcon#about to read 4, iclass 36, count 0 2006.176.07:51:38.65#ibcon#read 4, iclass 36, count 0 2006.176.07:51:38.65#ibcon#about to read 5, iclass 36, count 0 2006.176.07:51:38.65#ibcon#read 5, iclass 36, count 0 2006.176.07:51:38.65#ibcon#about to read 6, iclass 36, count 0 2006.176.07:51:38.65#ibcon#read 6, iclass 36, count 0 2006.176.07:51:38.65#ibcon#end of sib2, iclass 36, count 0 2006.176.07:51:38.65#ibcon#*after write, iclass 36, count 0 2006.176.07:51:38.65#ibcon#*before return 0, iclass 36, count 0 2006.176.07:51:38.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:51:38.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:51:38.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:51:38.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:51:38.65$vc4f8/va=3,6 2006.176.07:51:38.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.07:51:38.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.07:51:38.65#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:38.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:51:38.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:51:38.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:51:38.71#ibcon#enter wrdev, iclass 38, count 2 2006.176.07:51:38.71#ibcon#first serial, iclass 38, count 2 2006.176.07:51:38.71#ibcon#enter sib2, iclass 38, count 2 2006.176.07:51:38.71#ibcon#flushed, iclass 38, count 2 2006.176.07:51:38.71#ibcon#about to write, iclass 38, count 2 2006.176.07:51:38.71#ibcon#wrote, iclass 38, count 2 2006.176.07:51:38.71#ibcon#about to read 3, iclass 38, count 2 2006.176.07:51:38.73#ibcon#read 3, iclass 38, count 2 2006.176.07:51:38.73#ibcon#about to read 4, iclass 38, count 2 2006.176.07:51:38.73#ibcon#read 4, iclass 38, count 2 2006.176.07:51:38.73#ibcon#about to read 5, iclass 38, count 2 2006.176.07:51:38.73#ibcon#read 5, iclass 38, count 2 2006.176.07:51:38.73#ibcon#about to read 6, iclass 38, count 2 2006.176.07:51:38.73#ibcon#read 6, iclass 38, count 2 2006.176.07:51:38.73#ibcon#end of sib2, iclass 38, count 2 2006.176.07:51:38.73#ibcon#*mode == 0, iclass 38, count 2 2006.176.07:51:38.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.07:51:38.73#ibcon#[25=AT03-06\r\n] 2006.176.07:51:38.73#ibcon#*before write, iclass 38, count 2 2006.176.07:51:38.73#ibcon#enter sib2, iclass 38, count 2 2006.176.07:51:38.73#ibcon#flushed, iclass 38, count 2 2006.176.07:51:38.73#ibcon#about to write, iclass 38, count 2 2006.176.07:51:38.73#ibcon#wrote, iclass 38, count 2 2006.176.07:51:38.73#ibcon#about to read 3, iclass 38, count 2 2006.176.07:51:38.76#ibcon#read 3, iclass 38, count 2 2006.176.07:51:38.76#ibcon#about to read 4, iclass 38, count 2 2006.176.07:51:38.76#ibcon#read 4, iclass 38, count 2 2006.176.07:51:38.76#ibcon#about to read 5, iclass 38, count 2 2006.176.07:51:38.76#ibcon#read 5, iclass 38, count 2 2006.176.07:51:38.76#ibcon#about to read 6, iclass 38, count 2 2006.176.07:51:38.76#ibcon#read 6, iclass 38, count 2 2006.176.07:51:38.76#ibcon#end of sib2, iclass 38, count 2 2006.176.07:51:38.76#ibcon#*after write, iclass 38, count 2 2006.176.07:51:38.76#ibcon#*before return 0, iclass 38, count 2 2006.176.07:51:38.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:51:38.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:51:38.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.07:51:38.76#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:38.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:51:38.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:51:38.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:51:38.88#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:51:38.88#ibcon#first serial, iclass 38, count 0 2006.176.07:51:38.88#ibcon#enter sib2, iclass 38, count 0 2006.176.07:51:38.88#ibcon#flushed, iclass 38, count 0 2006.176.07:51:38.88#ibcon#about to write, iclass 38, count 0 2006.176.07:51:38.88#ibcon#wrote, iclass 38, count 0 2006.176.07:51:38.88#ibcon#about to read 3, iclass 38, count 0 2006.176.07:51:38.90#ibcon#read 3, iclass 38, count 0 2006.176.07:51:38.90#ibcon#about to read 4, iclass 38, count 0 2006.176.07:51:38.90#ibcon#read 4, iclass 38, count 0 2006.176.07:51:38.90#ibcon#about to read 5, iclass 38, count 0 2006.176.07:51:38.90#ibcon#read 5, iclass 38, count 0 2006.176.07:51:38.90#ibcon#about to read 6, iclass 38, count 0 2006.176.07:51:38.90#ibcon#read 6, iclass 38, count 0 2006.176.07:51:38.90#ibcon#end of sib2, iclass 38, count 0 2006.176.07:51:38.90#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:51:38.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:51:38.90#ibcon#[25=USB\r\n] 2006.176.07:51:38.90#ibcon#*before write, iclass 38, count 0 2006.176.07:51:38.90#ibcon#enter sib2, iclass 38, count 0 2006.176.07:51:38.90#ibcon#flushed, iclass 38, count 0 2006.176.07:51:38.90#ibcon#about to write, iclass 38, count 0 2006.176.07:51:38.90#ibcon#wrote, iclass 38, count 0 2006.176.07:51:38.90#ibcon#about to read 3, iclass 38, count 0 2006.176.07:51:38.93#ibcon#read 3, iclass 38, count 0 2006.176.07:51:38.93#ibcon#about to read 4, iclass 38, count 0 2006.176.07:51:38.93#ibcon#read 4, iclass 38, count 0 2006.176.07:51:38.93#ibcon#about to read 5, iclass 38, count 0 2006.176.07:51:38.93#ibcon#read 5, iclass 38, count 0 2006.176.07:51:38.93#ibcon#about to read 6, iclass 38, count 0 2006.176.07:51:38.93#ibcon#read 6, iclass 38, count 0 2006.176.07:51:38.93#ibcon#end of sib2, iclass 38, count 0 2006.176.07:51:38.93#ibcon#*after write, iclass 38, count 0 2006.176.07:51:38.93#ibcon#*before return 0, iclass 38, count 0 2006.176.07:51:38.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:51:38.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:51:38.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:51:38.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:51:38.93$vc4f8/valo=4,832.99 2006.176.07:51:38.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.07:51:38.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.07:51:38.93#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:38.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:51:38.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:51:38.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:51:38.93#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:51:38.93#ibcon#first serial, iclass 40, count 0 2006.176.07:51:38.93#ibcon#enter sib2, iclass 40, count 0 2006.176.07:51:38.93#ibcon#flushed, iclass 40, count 0 2006.176.07:51:38.93#ibcon#about to write, iclass 40, count 0 2006.176.07:51:38.93#ibcon#wrote, iclass 40, count 0 2006.176.07:51:38.93#ibcon#about to read 3, iclass 40, count 0 2006.176.07:51:38.95#ibcon#read 3, iclass 40, count 0 2006.176.07:51:38.95#ibcon#about to read 4, iclass 40, count 0 2006.176.07:51:38.95#ibcon#read 4, iclass 40, count 0 2006.176.07:51:38.95#ibcon#about to read 5, iclass 40, count 0 2006.176.07:51:38.95#ibcon#read 5, iclass 40, count 0 2006.176.07:51:38.95#ibcon#about to read 6, iclass 40, count 0 2006.176.07:51:38.95#ibcon#read 6, iclass 40, count 0 2006.176.07:51:38.95#ibcon#end of sib2, iclass 40, count 0 2006.176.07:51:38.95#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:51:38.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:51:38.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:51:38.95#ibcon#*before write, iclass 40, count 0 2006.176.07:51:38.95#ibcon#enter sib2, iclass 40, count 0 2006.176.07:51:38.95#ibcon#flushed, iclass 40, count 0 2006.176.07:51:38.95#ibcon#about to write, iclass 40, count 0 2006.176.07:51:38.95#ibcon#wrote, iclass 40, count 0 2006.176.07:51:38.95#ibcon#about to read 3, iclass 40, count 0 2006.176.07:51:38.99#ibcon#read 3, iclass 40, count 0 2006.176.07:51:38.99#ibcon#about to read 4, iclass 40, count 0 2006.176.07:51:38.99#ibcon#read 4, iclass 40, count 0 2006.176.07:51:38.99#ibcon#about to read 5, iclass 40, count 0 2006.176.07:51:38.99#ibcon#read 5, iclass 40, count 0 2006.176.07:51:38.99#ibcon#about to read 6, iclass 40, count 0 2006.176.07:51:38.99#ibcon#read 6, iclass 40, count 0 2006.176.07:51:38.99#ibcon#end of sib2, iclass 40, count 0 2006.176.07:51:38.99#ibcon#*after write, iclass 40, count 0 2006.176.07:51:38.99#ibcon#*before return 0, iclass 40, count 0 2006.176.07:51:38.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:51:38.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:51:38.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:51:38.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:51:38.99$vc4f8/va=4,7 2006.176.07:51:38.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.07:51:38.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.07:51:38.99#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:38.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:51:39.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:51:39.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:51:39.05#ibcon#enter wrdev, iclass 4, count 2 2006.176.07:51:39.05#ibcon#first serial, iclass 4, count 2 2006.176.07:51:39.05#ibcon#enter sib2, iclass 4, count 2 2006.176.07:51:39.05#ibcon#flushed, iclass 4, count 2 2006.176.07:51:39.05#ibcon#about to write, iclass 4, count 2 2006.176.07:51:39.05#ibcon#wrote, iclass 4, count 2 2006.176.07:51:39.05#ibcon#about to read 3, iclass 4, count 2 2006.176.07:51:39.07#ibcon#read 3, iclass 4, count 2 2006.176.07:51:39.07#ibcon#about to read 4, iclass 4, count 2 2006.176.07:51:39.07#ibcon#read 4, iclass 4, count 2 2006.176.07:51:39.07#ibcon#about to read 5, iclass 4, count 2 2006.176.07:51:39.07#ibcon#read 5, iclass 4, count 2 2006.176.07:51:39.07#ibcon#about to read 6, iclass 4, count 2 2006.176.07:51:39.07#ibcon#read 6, iclass 4, count 2 2006.176.07:51:39.07#ibcon#end of sib2, iclass 4, count 2 2006.176.07:51:39.07#ibcon#*mode == 0, iclass 4, count 2 2006.176.07:51:39.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.07:51:39.07#ibcon#[25=AT04-07\r\n] 2006.176.07:51:39.07#ibcon#*before write, iclass 4, count 2 2006.176.07:51:39.07#ibcon#enter sib2, iclass 4, count 2 2006.176.07:51:39.07#ibcon#flushed, iclass 4, count 2 2006.176.07:51:39.07#ibcon#about to write, iclass 4, count 2 2006.176.07:51:39.07#ibcon#wrote, iclass 4, count 2 2006.176.07:51:39.07#ibcon#about to read 3, iclass 4, count 2 2006.176.07:51:39.10#ibcon#read 3, iclass 4, count 2 2006.176.07:51:39.10#ibcon#about to read 4, iclass 4, count 2 2006.176.07:51:39.10#ibcon#read 4, iclass 4, count 2 2006.176.07:51:39.10#ibcon#about to read 5, iclass 4, count 2 2006.176.07:51:39.10#ibcon#read 5, iclass 4, count 2 2006.176.07:51:39.10#ibcon#about to read 6, iclass 4, count 2 2006.176.07:51:39.10#ibcon#read 6, iclass 4, count 2 2006.176.07:51:39.10#ibcon#end of sib2, iclass 4, count 2 2006.176.07:51:39.10#ibcon#*after write, iclass 4, count 2 2006.176.07:51:39.10#ibcon#*before return 0, iclass 4, count 2 2006.176.07:51:39.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:51:39.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:51:39.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.07:51:39.10#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:39.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:51:39.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:51:39.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:51:39.22#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:51:39.22#ibcon#first serial, iclass 4, count 0 2006.176.07:51:39.22#ibcon#enter sib2, iclass 4, count 0 2006.176.07:51:39.22#ibcon#flushed, iclass 4, count 0 2006.176.07:51:39.22#ibcon#about to write, iclass 4, count 0 2006.176.07:51:39.22#ibcon#wrote, iclass 4, count 0 2006.176.07:51:39.22#ibcon#about to read 3, iclass 4, count 0 2006.176.07:51:39.24#ibcon#read 3, iclass 4, count 0 2006.176.07:51:39.24#ibcon#about to read 4, iclass 4, count 0 2006.176.07:51:39.24#ibcon#read 4, iclass 4, count 0 2006.176.07:51:39.24#ibcon#about to read 5, iclass 4, count 0 2006.176.07:51:39.24#ibcon#read 5, iclass 4, count 0 2006.176.07:51:39.24#ibcon#about to read 6, iclass 4, count 0 2006.176.07:51:39.24#ibcon#read 6, iclass 4, count 0 2006.176.07:51:39.24#ibcon#end of sib2, iclass 4, count 0 2006.176.07:51:39.24#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:51:39.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:51:39.24#ibcon#[25=USB\r\n] 2006.176.07:51:39.24#ibcon#*before write, iclass 4, count 0 2006.176.07:51:39.24#ibcon#enter sib2, iclass 4, count 0 2006.176.07:51:39.24#ibcon#flushed, iclass 4, count 0 2006.176.07:51:39.24#ibcon#about to write, iclass 4, count 0 2006.176.07:51:39.24#ibcon#wrote, iclass 4, count 0 2006.176.07:51:39.24#ibcon#about to read 3, iclass 4, count 0 2006.176.07:51:39.27#ibcon#read 3, iclass 4, count 0 2006.176.07:51:39.27#ibcon#about to read 4, iclass 4, count 0 2006.176.07:51:39.27#ibcon#read 4, iclass 4, count 0 2006.176.07:51:39.27#ibcon#about to read 5, iclass 4, count 0 2006.176.07:51:39.27#ibcon#read 5, iclass 4, count 0 2006.176.07:51:39.27#ibcon#about to read 6, iclass 4, count 0 2006.176.07:51:39.27#ibcon#read 6, iclass 4, count 0 2006.176.07:51:39.27#ibcon#end of sib2, iclass 4, count 0 2006.176.07:51:39.27#ibcon#*after write, iclass 4, count 0 2006.176.07:51:39.27#ibcon#*before return 0, iclass 4, count 0 2006.176.07:51:39.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:51:39.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:51:39.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:51:39.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:51:39.27$vc4f8/valo=5,652.99 2006.176.07:51:39.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.07:51:39.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.07:51:39.27#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:39.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:51:39.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:51:39.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:51:39.27#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:51:39.27#ibcon#first serial, iclass 6, count 0 2006.176.07:51:39.27#ibcon#enter sib2, iclass 6, count 0 2006.176.07:51:39.27#ibcon#flushed, iclass 6, count 0 2006.176.07:51:39.27#ibcon#about to write, iclass 6, count 0 2006.176.07:51:39.27#ibcon#wrote, iclass 6, count 0 2006.176.07:51:39.27#ibcon#about to read 3, iclass 6, count 0 2006.176.07:51:39.29#ibcon#read 3, iclass 6, count 0 2006.176.07:51:39.29#ibcon#about to read 4, iclass 6, count 0 2006.176.07:51:39.29#ibcon#read 4, iclass 6, count 0 2006.176.07:51:39.29#ibcon#about to read 5, iclass 6, count 0 2006.176.07:51:39.29#ibcon#read 5, iclass 6, count 0 2006.176.07:51:39.29#ibcon#about to read 6, iclass 6, count 0 2006.176.07:51:39.29#ibcon#read 6, iclass 6, count 0 2006.176.07:51:39.29#ibcon#end of sib2, iclass 6, count 0 2006.176.07:51:39.29#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:51:39.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:51:39.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:51:39.29#ibcon#*before write, iclass 6, count 0 2006.176.07:51:39.29#ibcon#enter sib2, iclass 6, count 0 2006.176.07:51:39.29#ibcon#flushed, iclass 6, count 0 2006.176.07:51:39.29#ibcon#about to write, iclass 6, count 0 2006.176.07:51:39.29#ibcon#wrote, iclass 6, count 0 2006.176.07:51:39.29#ibcon#about to read 3, iclass 6, count 0 2006.176.07:51:39.33#ibcon#read 3, iclass 6, count 0 2006.176.07:51:39.33#ibcon#about to read 4, iclass 6, count 0 2006.176.07:51:39.33#ibcon#read 4, iclass 6, count 0 2006.176.07:51:39.33#ibcon#about to read 5, iclass 6, count 0 2006.176.07:51:39.33#ibcon#read 5, iclass 6, count 0 2006.176.07:51:39.33#ibcon#about to read 6, iclass 6, count 0 2006.176.07:51:39.33#ibcon#read 6, iclass 6, count 0 2006.176.07:51:39.33#ibcon#end of sib2, iclass 6, count 0 2006.176.07:51:39.33#ibcon#*after write, iclass 6, count 0 2006.176.07:51:39.33#ibcon#*before return 0, iclass 6, count 0 2006.176.07:51:39.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:51:39.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:51:39.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:51:39.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:51:39.33$vc4f8/va=5,7 2006.176.07:51:39.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.07:51:39.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.07:51:39.33#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:39.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:51:39.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:51:39.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:51:39.39#ibcon#enter wrdev, iclass 10, count 2 2006.176.07:51:39.39#ibcon#first serial, iclass 10, count 2 2006.176.07:51:39.39#ibcon#enter sib2, iclass 10, count 2 2006.176.07:51:39.39#ibcon#flushed, iclass 10, count 2 2006.176.07:51:39.39#ibcon#about to write, iclass 10, count 2 2006.176.07:51:39.39#ibcon#wrote, iclass 10, count 2 2006.176.07:51:39.39#ibcon#about to read 3, iclass 10, count 2 2006.176.07:51:39.41#ibcon#read 3, iclass 10, count 2 2006.176.07:51:39.41#ibcon#about to read 4, iclass 10, count 2 2006.176.07:51:39.41#ibcon#read 4, iclass 10, count 2 2006.176.07:51:39.41#ibcon#about to read 5, iclass 10, count 2 2006.176.07:51:39.41#ibcon#read 5, iclass 10, count 2 2006.176.07:51:39.41#ibcon#about to read 6, iclass 10, count 2 2006.176.07:51:39.41#ibcon#read 6, iclass 10, count 2 2006.176.07:51:39.41#ibcon#end of sib2, iclass 10, count 2 2006.176.07:51:39.41#ibcon#*mode == 0, iclass 10, count 2 2006.176.07:51:39.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.07:51:39.41#ibcon#[25=AT05-07\r\n] 2006.176.07:51:39.41#ibcon#*before write, iclass 10, count 2 2006.176.07:51:39.41#ibcon#enter sib2, iclass 10, count 2 2006.176.07:51:39.41#ibcon#flushed, iclass 10, count 2 2006.176.07:51:39.41#ibcon#about to write, iclass 10, count 2 2006.176.07:51:39.41#ibcon#wrote, iclass 10, count 2 2006.176.07:51:39.41#ibcon#about to read 3, iclass 10, count 2 2006.176.07:51:39.44#ibcon#read 3, iclass 10, count 2 2006.176.07:51:39.44#ibcon#about to read 4, iclass 10, count 2 2006.176.07:51:39.44#ibcon#read 4, iclass 10, count 2 2006.176.07:51:39.44#ibcon#about to read 5, iclass 10, count 2 2006.176.07:51:39.44#ibcon#read 5, iclass 10, count 2 2006.176.07:51:39.44#ibcon#about to read 6, iclass 10, count 2 2006.176.07:51:39.44#ibcon#read 6, iclass 10, count 2 2006.176.07:51:39.44#ibcon#end of sib2, iclass 10, count 2 2006.176.07:51:39.44#ibcon#*after write, iclass 10, count 2 2006.176.07:51:39.44#ibcon#*before return 0, iclass 10, count 2 2006.176.07:51:39.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:51:39.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:51:39.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.07:51:39.44#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:39.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:51:39.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:51:39.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:51:39.56#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:51:39.56#ibcon#first serial, iclass 10, count 0 2006.176.07:51:39.56#ibcon#enter sib2, iclass 10, count 0 2006.176.07:51:39.56#ibcon#flushed, iclass 10, count 0 2006.176.07:51:39.56#ibcon#about to write, iclass 10, count 0 2006.176.07:51:39.56#ibcon#wrote, iclass 10, count 0 2006.176.07:51:39.56#ibcon#about to read 3, iclass 10, count 0 2006.176.07:51:39.58#ibcon#read 3, iclass 10, count 0 2006.176.07:51:39.58#ibcon#about to read 4, iclass 10, count 0 2006.176.07:51:39.58#ibcon#read 4, iclass 10, count 0 2006.176.07:51:39.58#ibcon#about to read 5, iclass 10, count 0 2006.176.07:51:39.58#ibcon#read 5, iclass 10, count 0 2006.176.07:51:39.58#ibcon#about to read 6, iclass 10, count 0 2006.176.07:51:39.58#ibcon#read 6, iclass 10, count 0 2006.176.07:51:39.58#ibcon#end of sib2, iclass 10, count 0 2006.176.07:51:39.58#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:51:39.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:51:39.58#ibcon#[25=USB\r\n] 2006.176.07:51:39.58#ibcon#*before write, iclass 10, count 0 2006.176.07:51:39.58#ibcon#enter sib2, iclass 10, count 0 2006.176.07:51:39.58#ibcon#flushed, iclass 10, count 0 2006.176.07:51:39.58#ibcon#about to write, iclass 10, count 0 2006.176.07:51:39.58#ibcon#wrote, iclass 10, count 0 2006.176.07:51:39.58#ibcon#about to read 3, iclass 10, count 0 2006.176.07:51:39.61#ibcon#read 3, iclass 10, count 0 2006.176.07:51:39.61#ibcon#about to read 4, iclass 10, count 0 2006.176.07:51:39.61#ibcon#read 4, iclass 10, count 0 2006.176.07:51:39.61#ibcon#about to read 5, iclass 10, count 0 2006.176.07:51:39.61#ibcon#read 5, iclass 10, count 0 2006.176.07:51:39.61#ibcon#about to read 6, iclass 10, count 0 2006.176.07:51:39.61#ibcon#read 6, iclass 10, count 0 2006.176.07:51:39.61#ibcon#end of sib2, iclass 10, count 0 2006.176.07:51:39.61#ibcon#*after write, iclass 10, count 0 2006.176.07:51:39.61#ibcon#*before return 0, iclass 10, count 0 2006.176.07:51:39.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:51:39.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:51:39.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:51:39.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:51:39.61$vc4f8/valo=6,772.99 2006.176.07:51:39.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.07:51:39.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.07:51:39.61#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:39.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:51:39.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:51:39.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:51:39.61#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:51:39.61#ibcon#first serial, iclass 12, count 0 2006.176.07:51:39.61#ibcon#enter sib2, iclass 12, count 0 2006.176.07:51:39.61#ibcon#flushed, iclass 12, count 0 2006.176.07:51:39.61#ibcon#about to write, iclass 12, count 0 2006.176.07:51:39.61#ibcon#wrote, iclass 12, count 0 2006.176.07:51:39.61#ibcon#about to read 3, iclass 12, count 0 2006.176.07:51:39.63#ibcon#read 3, iclass 12, count 0 2006.176.07:51:39.63#ibcon#about to read 4, iclass 12, count 0 2006.176.07:51:39.63#ibcon#read 4, iclass 12, count 0 2006.176.07:51:39.63#ibcon#about to read 5, iclass 12, count 0 2006.176.07:51:39.63#ibcon#read 5, iclass 12, count 0 2006.176.07:51:39.63#ibcon#about to read 6, iclass 12, count 0 2006.176.07:51:39.63#ibcon#read 6, iclass 12, count 0 2006.176.07:51:39.63#ibcon#end of sib2, iclass 12, count 0 2006.176.07:51:39.63#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:51:39.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:51:39.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:51:39.63#ibcon#*before write, iclass 12, count 0 2006.176.07:51:39.63#ibcon#enter sib2, iclass 12, count 0 2006.176.07:51:39.63#ibcon#flushed, iclass 12, count 0 2006.176.07:51:39.63#ibcon#about to write, iclass 12, count 0 2006.176.07:51:39.63#ibcon#wrote, iclass 12, count 0 2006.176.07:51:39.63#ibcon#about to read 3, iclass 12, count 0 2006.176.07:51:39.67#ibcon#read 3, iclass 12, count 0 2006.176.07:51:39.67#ibcon#about to read 4, iclass 12, count 0 2006.176.07:51:39.67#ibcon#read 4, iclass 12, count 0 2006.176.07:51:39.67#ibcon#about to read 5, iclass 12, count 0 2006.176.07:51:39.67#ibcon#read 5, iclass 12, count 0 2006.176.07:51:39.67#ibcon#about to read 6, iclass 12, count 0 2006.176.07:51:39.67#ibcon#read 6, iclass 12, count 0 2006.176.07:51:39.67#ibcon#end of sib2, iclass 12, count 0 2006.176.07:51:39.67#ibcon#*after write, iclass 12, count 0 2006.176.07:51:39.67#ibcon#*before return 0, iclass 12, count 0 2006.176.07:51:39.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:51:39.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:51:39.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:51:39.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:51:39.67$vc4f8/va=6,6 2006.176.07:51:39.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.07:51:39.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.07:51:39.67#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:39.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:51:39.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:51:39.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:51:39.73#ibcon#enter wrdev, iclass 14, count 2 2006.176.07:51:39.73#ibcon#first serial, iclass 14, count 2 2006.176.07:51:39.73#ibcon#enter sib2, iclass 14, count 2 2006.176.07:51:39.73#ibcon#flushed, iclass 14, count 2 2006.176.07:51:39.73#ibcon#about to write, iclass 14, count 2 2006.176.07:51:39.73#ibcon#wrote, iclass 14, count 2 2006.176.07:51:39.73#ibcon#about to read 3, iclass 14, count 2 2006.176.07:51:39.75#ibcon#read 3, iclass 14, count 2 2006.176.07:51:39.75#ibcon#about to read 4, iclass 14, count 2 2006.176.07:51:39.75#ibcon#read 4, iclass 14, count 2 2006.176.07:51:39.75#ibcon#about to read 5, iclass 14, count 2 2006.176.07:51:39.75#ibcon#read 5, iclass 14, count 2 2006.176.07:51:39.75#ibcon#about to read 6, iclass 14, count 2 2006.176.07:51:39.75#ibcon#read 6, iclass 14, count 2 2006.176.07:51:39.75#ibcon#end of sib2, iclass 14, count 2 2006.176.07:51:39.75#ibcon#*mode == 0, iclass 14, count 2 2006.176.07:51:39.75#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.07:51:39.75#ibcon#[25=AT06-06\r\n] 2006.176.07:51:39.75#ibcon#*before write, iclass 14, count 2 2006.176.07:51:39.75#ibcon#enter sib2, iclass 14, count 2 2006.176.07:51:39.75#ibcon#flushed, iclass 14, count 2 2006.176.07:51:39.75#ibcon#about to write, iclass 14, count 2 2006.176.07:51:39.75#ibcon#wrote, iclass 14, count 2 2006.176.07:51:39.75#ibcon#about to read 3, iclass 14, count 2 2006.176.07:51:39.78#ibcon#read 3, iclass 14, count 2 2006.176.07:51:39.78#ibcon#about to read 4, iclass 14, count 2 2006.176.07:51:39.78#ibcon#read 4, iclass 14, count 2 2006.176.07:51:39.78#ibcon#about to read 5, iclass 14, count 2 2006.176.07:51:39.78#ibcon#read 5, iclass 14, count 2 2006.176.07:51:39.78#ibcon#about to read 6, iclass 14, count 2 2006.176.07:51:39.78#ibcon#read 6, iclass 14, count 2 2006.176.07:51:39.78#ibcon#end of sib2, iclass 14, count 2 2006.176.07:51:39.78#ibcon#*after write, iclass 14, count 2 2006.176.07:51:39.78#ibcon#*before return 0, iclass 14, count 2 2006.176.07:51:39.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:51:39.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:51:39.78#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.07:51:39.78#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:39.78#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:51:39.90#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:51:39.90#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:51:39.90#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:51:39.90#ibcon#first serial, iclass 14, count 0 2006.176.07:51:39.90#ibcon#enter sib2, iclass 14, count 0 2006.176.07:51:39.90#ibcon#flushed, iclass 14, count 0 2006.176.07:51:39.90#ibcon#about to write, iclass 14, count 0 2006.176.07:51:39.90#ibcon#wrote, iclass 14, count 0 2006.176.07:51:39.90#ibcon#about to read 3, iclass 14, count 0 2006.176.07:51:39.92#ibcon#read 3, iclass 14, count 0 2006.176.07:51:39.92#ibcon#about to read 4, iclass 14, count 0 2006.176.07:51:39.92#ibcon#read 4, iclass 14, count 0 2006.176.07:51:39.92#ibcon#about to read 5, iclass 14, count 0 2006.176.07:51:39.92#ibcon#read 5, iclass 14, count 0 2006.176.07:51:39.92#ibcon#about to read 6, iclass 14, count 0 2006.176.07:51:39.92#ibcon#read 6, iclass 14, count 0 2006.176.07:51:39.92#ibcon#end of sib2, iclass 14, count 0 2006.176.07:51:39.92#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:51:39.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:51:39.92#ibcon#[25=USB\r\n] 2006.176.07:51:39.92#ibcon#*before write, iclass 14, count 0 2006.176.07:51:39.92#ibcon#enter sib2, iclass 14, count 0 2006.176.07:51:39.92#ibcon#flushed, iclass 14, count 0 2006.176.07:51:39.92#ibcon#about to write, iclass 14, count 0 2006.176.07:51:39.92#ibcon#wrote, iclass 14, count 0 2006.176.07:51:39.92#ibcon#about to read 3, iclass 14, count 0 2006.176.07:51:39.95#ibcon#read 3, iclass 14, count 0 2006.176.07:51:39.95#ibcon#about to read 4, iclass 14, count 0 2006.176.07:51:39.95#ibcon#read 4, iclass 14, count 0 2006.176.07:51:39.95#ibcon#about to read 5, iclass 14, count 0 2006.176.07:51:39.95#ibcon#read 5, iclass 14, count 0 2006.176.07:51:39.95#ibcon#about to read 6, iclass 14, count 0 2006.176.07:51:39.95#ibcon#read 6, iclass 14, count 0 2006.176.07:51:39.95#ibcon#end of sib2, iclass 14, count 0 2006.176.07:51:39.95#ibcon#*after write, iclass 14, count 0 2006.176.07:51:39.95#ibcon#*before return 0, iclass 14, count 0 2006.176.07:51:39.95#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:51:39.95#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:51:39.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:51:39.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:51:39.95$vc4f8/valo=7,832.99 2006.176.07:51:39.95#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:51:39.95#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:51:39.95#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:39.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:39.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:39.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:39.95#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:51:39.95#ibcon#first serial, iclass 16, count 0 2006.176.07:51:39.95#ibcon#enter sib2, iclass 16, count 0 2006.176.07:51:39.95#ibcon#flushed, iclass 16, count 0 2006.176.07:51:39.95#ibcon#about to write, iclass 16, count 0 2006.176.07:51:39.95#ibcon#wrote, iclass 16, count 0 2006.176.07:51:39.95#ibcon#about to read 3, iclass 16, count 0 2006.176.07:51:39.97#ibcon#read 3, iclass 16, count 0 2006.176.07:51:39.97#ibcon#about to read 4, iclass 16, count 0 2006.176.07:51:39.97#ibcon#read 4, iclass 16, count 0 2006.176.07:51:39.97#ibcon#about to read 5, iclass 16, count 0 2006.176.07:51:39.97#ibcon#read 5, iclass 16, count 0 2006.176.07:51:39.97#ibcon#about to read 6, iclass 16, count 0 2006.176.07:51:39.97#ibcon#read 6, iclass 16, count 0 2006.176.07:51:39.97#ibcon#end of sib2, iclass 16, count 0 2006.176.07:51:39.97#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:51:39.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:51:39.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:51:39.97#ibcon#*before write, iclass 16, count 0 2006.176.07:51:39.97#ibcon#enter sib2, iclass 16, count 0 2006.176.07:51:39.97#ibcon#flushed, iclass 16, count 0 2006.176.07:51:39.97#ibcon#about to write, iclass 16, count 0 2006.176.07:51:39.97#ibcon#wrote, iclass 16, count 0 2006.176.07:51:39.97#ibcon#about to read 3, iclass 16, count 0 2006.176.07:51:40.01#ibcon#read 3, iclass 16, count 0 2006.176.07:51:40.01#ibcon#about to read 4, iclass 16, count 0 2006.176.07:51:40.01#ibcon#read 4, iclass 16, count 0 2006.176.07:51:40.01#ibcon#about to read 5, iclass 16, count 0 2006.176.07:51:40.01#ibcon#read 5, iclass 16, count 0 2006.176.07:51:40.01#ibcon#about to read 6, iclass 16, count 0 2006.176.07:51:40.01#ibcon#read 6, iclass 16, count 0 2006.176.07:51:40.01#ibcon#end of sib2, iclass 16, count 0 2006.176.07:51:40.01#ibcon#*after write, iclass 16, count 0 2006.176.07:51:40.01#ibcon#*before return 0, iclass 16, count 0 2006.176.07:51:40.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:40.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:40.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:51:40.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:51:40.01$vc4f8/va=7,6 2006.176.07:51:40.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.07:51:40.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.07:51:40.01#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:40.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:51:40.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:51:40.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:51:40.07#ibcon#enter wrdev, iclass 18, count 2 2006.176.07:51:40.07#ibcon#first serial, iclass 18, count 2 2006.176.07:51:40.07#ibcon#enter sib2, iclass 18, count 2 2006.176.07:51:40.07#ibcon#flushed, iclass 18, count 2 2006.176.07:51:40.07#ibcon#about to write, iclass 18, count 2 2006.176.07:51:40.07#ibcon#wrote, iclass 18, count 2 2006.176.07:51:40.07#ibcon#about to read 3, iclass 18, count 2 2006.176.07:51:40.09#ibcon#read 3, iclass 18, count 2 2006.176.07:51:40.09#ibcon#about to read 4, iclass 18, count 2 2006.176.07:51:40.09#ibcon#read 4, iclass 18, count 2 2006.176.07:51:40.09#ibcon#about to read 5, iclass 18, count 2 2006.176.07:51:40.09#ibcon#read 5, iclass 18, count 2 2006.176.07:51:40.09#ibcon#about to read 6, iclass 18, count 2 2006.176.07:51:40.09#ibcon#read 6, iclass 18, count 2 2006.176.07:51:40.09#ibcon#end of sib2, iclass 18, count 2 2006.176.07:51:40.09#ibcon#*mode == 0, iclass 18, count 2 2006.176.07:51:40.09#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.07:51:40.09#ibcon#[25=AT07-06\r\n] 2006.176.07:51:40.09#ibcon#*before write, iclass 18, count 2 2006.176.07:51:40.09#ibcon#enter sib2, iclass 18, count 2 2006.176.07:51:40.09#ibcon#flushed, iclass 18, count 2 2006.176.07:51:40.09#ibcon#about to write, iclass 18, count 2 2006.176.07:51:40.09#ibcon#wrote, iclass 18, count 2 2006.176.07:51:40.09#ibcon#about to read 3, iclass 18, count 2 2006.176.07:51:40.12#ibcon#read 3, iclass 18, count 2 2006.176.07:51:40.12#ibcon#about to read 4, iclass 18, count 2 2006.176.07:51:40.12#ibcon#read 4, iclass 18, count 2 2006.176.07:51:40.12#ibcon#about to read 5, iclass 18, count 2 2006.176.07:51:40.12#ibcon#read 5, iclass 18, count 2 2006.176.07:51:40.12#ibcon#about to read 6, iclass 18, count 2 2006.176.07:51:40.12#ibcon#read 6, iclass 18, count 2 2006.176.07:51:40.12#ibcon#end of sib2, iclass 18, count 2 2006.176.07:51:40.12#ibcon#*after write, iclass 18, count 2 2006.176.07:51:40.12#ibcon#*before return 0, iclass 18, count 2 2006.176.07:51:40.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:51:40.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:51:40.12#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.07:51:40.12#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:40.12#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:51:40.24#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:51:40.24#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:51:40.24#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:51:40.24#ibcon#first serial, iclass 18, count 0 2006.176.07:51:40.24#ibcon#enter sib2, iclass 18, count 0 2006.176.07:51:40.24#ibcon#flushed, iclass 18, count 0 2006.176.07:51:40.24#ibcon#about to write, iclass 18, count 0 2006.176.07:51:40.24#ibcon#wrote, iclass 18, count 0 2006.176.07:51:40.24#ibcon#about to read 3, iclass 18, count 0 2006.176.07:51:40.26#ibcon#read 3, iclass 18, count 0 2006.176.07:51:40.26#ibcon#about to read 4, iclass 18, count 0 2006.176.07:51:40.26#ibcon#read 4, iclass 18, count 0 2006.176.07:51:40.26#ibcon#about to read 5, iclass 18, count 0 2006.176.07:51:40.26#ibcon#read 5, iclass 18, count 0 2006.176.07:51:40.26#ibcon#about to read 6, iclass 18, count 0 2006.176.07:51:40.26#ibcon#read 6, iclass 18, count 0 2006.176.07:51:40.26#ibcon#end of sib2, iclass 18, count 0 2006.176.07:51:40.26#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:51:40.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:51:40.26#ibcon#[25=USB\r\n] 2006.176.07:51:40.26#ibcon#*before write, iclass 18, count 0 2006.176.07:51:40.26#ibcon#enter sib2, iclass 18, count 0 2006.176.07:51:40.26#ibcon#flushed, iclass 18, count 0 2006.176.07:51:40.26#ibcon#about to write, iclass 18, count 0 2006.176.07:51:40.26#ibcon#wrote, iclass 18, count 0 2006.176.07:51:40.26#ibcon#about to read 3, iclass 18, count 0 2006.176.07:51:40.29#ibcon#read 3, iclass 18, count 0 2006.176.07:51:40.29#ibcon#about to read 4, iclass 18, count 0 2006.176.07:51:40.29#ibcon#read 4, iclass 18, count 0 2006.176.07:51:40.29#ibcon#about to read 5, iclass 18, count 0 2006.176.07:51:40.29#ibcon#read 5, iclass 18, count 0 2006.176.07:51:40.29#ibcon#about to read 6, iclass 18, count 0 2006.176.07:51:40.29#ibcon#read 6, iclass 18, count 0 2006.176.07:51:40.29#ibcon#end of sib2, iclass 18, count 0 2006.176.07:51:40.29#ibcon#*after write, iclass 18, count 0 2006.176.07:51:40.29#ibcon#*before return 0, iclass 18, count 0 2006.176.07:51:40.29#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:51:40.29#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:51:40.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:51:40.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:51:40.29$vc4f8/valo=8,852.99 2006.176.07:51:40.29#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.07:51:40.29#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.07:51:40.29#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:40.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:51:40.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:51:40.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:51:40.29#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:51:40.29#ibcon#first serial, iclass 20, count 0 2006.176.07:51:40.29#ibcon#enter sib2, iclass 20, count 0 2006.176.07:51:40.29#ibcon#flushed, iclass 20, count 0 2006.176.07:51:40.29#ibcon#about to write, iclass 20, count 0 2006.176.07:51:40.29#ibcon#wrote, iclass 20, count 0 2006.176.07:51:40.29#ibcon#about to read 3, iclass 20, count 0 2006.176.07:51:40.31#ibcon#read 3, iclass 20, count 0 2006.176.07:51:40.31#ibcon#about to read 4, iclass 20, count 0 2006.176.07:51:40.31#ibcon#read 4, iclass 20, count 0 2006.176.07:51:40.31#ibcon#about to read 5, iclass 20, count 0 2006.176.07:51:40.31#ibcon#read 5, iclass 20, count 0 2006.176.07:51:40.31#ibcon#about to read 6, iclass 20, count 0 2006.176.07:51:40.31#ibcon#read 6, iclass 20, count 0 2006.176.07:51:40.31#ibcon#end of sib2, iclass 20, count 0 2006.176.07:51:40.31#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:51:40.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:51:40.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:51:40.31#ibcon#*before write, iclass 20, count 0 2006.176.07:51:40.31#ibcon#enter sib2, iclass 20, count 0 2006.176.07:51:40.31#ibcon#flushed, iclass 20, count 0 2006.176.07:51:40.31#ibcon#about to write, iclass 20, count 0 2006.176.07:51:40.31#ibcon#wrote, iclass 20, count 0 2006.176.07:51:40.31#ibcon#about to read 3, iclass 20, count 0 2006.176.07:51:40.35#ibcon#read 3, iclass 20, count 0 2006.176.07:51:40.35#ibcon#about to read 4, iclass 20, count 0 2006.176.07:51:40.35#ibcon#read 4, iclass 20, count 0 2006.176.07:51:40.35#ibcon#about to read 5, iclass 20, count 0 2006.176.07:51:40.35#ibcon#read 5, iclass 20, count 0 2006.176.07:51:40.35#ibcon#about to read 6, iclass 20, count 0 2006.176.07:51:40.35#ibcon#read 6, iclass 20, count 0 2006.176.07:51:40.35#ibcon#end of sib2, iclass 20, count 0 2006.176.07:51:40.35#ibcon#*after write, iclass 20, count 0 2006.176.07:51:40.35#ibcon#*before return 0, iclass 20, count 0 2006.176.07:51:40.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:51:40.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:51:40.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:51:40.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:51:40.35$vc4f8/va=8,6 2006.176.07:51:40.35#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.07:51:40.35#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.07:51:40.35#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:40.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:51:40.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:51:40.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:51:40.41#ibcon#enter wrdev, iclass 22, count 2 2006.176.07:51:40.41#ibcon#first serial, iclass 22, count 2 2006.176.07:51:40.41#ibcon#enter sib2, iclass 22, count 2 2006.176.07:51:40.41#ibcon#flushed, iclass 22, count 2 2006.176.07:51:40.41#ibcon#about to write, iclass 22, count 2 2006.176.07:51:40.41#ibcon#wrote, iclass 22, count 2 2006.176.07:51:40.41#ibcon#about to read 3, iclass 22, count 2 2006.176.07:51:40.43#ibcon#read 3, iclass 22, count 2 2006.176.07:51:40.43#ibcon#about to read 4, iclass 22, count 2 2006.176.07:51:40.43#ibcon#read 4, iclass 22, count 2 2006.176.07:51:40.43#ibcon#about to read 5, iclass 22, count 2 2006.176.07:51:40.43#ibcon#read 5, iclass 22, count 2 2006.176.07:51:40.43#ibcon#about to read 6, iclass 22, count 2 2006.176.07:51:40.43#ibcon#read 6, iclass 22, count 2 2006.176.07:51:40.43#ibcon#end of sib2, iclass 22, count 2 2006.176.07:51:40.43#ibcon#*mode == 0, iclass 22, count 2 2006.176.07:51:40.43#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.07:51:40.43#ibcon#[25=AT08-06\r\n] 2006.176.07:51:40.43#ibcon#*before write, iclass 22, count 2 2006.176.07:51:40.43#ibcon#enter sib2, iclass 22, count 2 2006.176.07:51:40.43#ibcon#flushed, iclass 22, count 2 2006.176.07:51:40.43#ibcon#about to write, iclass 22, count 2 2006.176.07:51:40.43#ibcon#wrote, iclass 22, count 2 2006.176.07:51:40.43#ibcon#about to read 3, iclass 22, count 2 2006.176.07:51:40.46#ibcon#read 3, iclass 22, count 2 2006.176.07:51:40.46#ibcon#about to read 4, iclass 22, count 2 2006.176.07:51:40.46#ibcon#read 4, iclass 22, count 2 2006.176.07:51:40.46#ibcon#about to read 5, iclass 22, count 2 2006.176.07:51:40.46#ibcon#read 5, iclass 22, count 2 2006.176.07:51:40.46#ibcon#about to read 6, iclass 22, count 2 2006.176.07:51:40.46#ibcon#read 6, iclass 22, count 2 2006.176.07:51:40.46#ibcon#end of sib2, iclass 22, count 2 2006.176.07:51:40.46#ibcon#*after write, iclass 22, count 2 2006.176.07:51:40.46#ibcon#*before return 0, iclass 22, count 2 2006.176.07:51:40.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:51:40.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:51:40.46#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.07:51:40.46#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:40.46#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:51:40.58#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:51:40.58#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:51:40.58#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:51:40.58#ibcon#first serial, iclass 22, count 0 2006.176.07:51:40.58#ibcon#enter sib2, iclass 22, count 0 2006.176.07:51:40.58#ibcon#flushed, iclass 22, count 0 2006.176.07:51:40.58#ibcon#about to write, iclass 22, count 0 2006.176.07:51:40.58#ibcon#wrote, iclass 22, count 0 2006.176.07:51:40.58#ibcon#about to read 3, iclass 22, count 0 2006.176.07:51:40.60#ibcon#read 3, iclass 22, count 0 2006.176.07:51:40.60#ibcon#about to read 4, iclass 22, count 0 2006.176.07:51:40.60#ibcon#read 4, iclass 22, count 0 2006.176.07:51:40.60#ibcon#about to read 5, iclass 22, count 0 2006.176.07:51:40.60#ibcon#read 5, iclass 22, count 0 2006.176.07:51:40.60#ibcon#about to read 6, iclass 22, count 0 2006.176.07:51:40.60#ibcon#read 6, iclass 22, count 0 2006.176.07:51:40.60#ibcon#end of sib2, iclass 22, count 0 2006.176.07:51:40.60#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:51:40.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:51:40.60#ibcon#[25=USB\r\n] 2006.176.07:51:40.60#ibcon#*before write, iclass 22, count 0 2006.176.07:51:40.60#ibcon#enter sib2, iclass 22, count 0 2006.176.07:51:40.60#ibcon#flushed, iclass 22, count 0 2006.176.07:51:40.60#ibcon#about to write, iclass 22, count 0 2006.176.07:51:40.60#ibcon#wrote, iclass 22, count 0 2006.176.07:51:40.60#ibcon#about to read 3, iclass 22, count 0 2006.176.07:51:40.63#ibcon#read 3, iclass 22, count 0 2006.176.07:51:40.63#ibcon#about to read 4, iclass 22, count 0 2006.176.07:51:40.63#ibcon#read 4, iclass 22, count 0 2006.176.07:51:40.63#ibcon#about to read 5, iclass 22, count 0 2006.176.07:51:40.63#ibcon#read 5, iclass 22, count 0 2006.176.07:51:40.63#ibcon#about to read 6, iclass 22, count 0 2006.176.07:51:40.63#ibcon#read 6, iclass 22, count 0 2006.176.07:51:40.63#ibcon#end of sib2, iclass 22, count 0 2006.176.07:51:40.63#ibcon#*after write, iclass 22, count 0 2006.176.07:51:40.63#ibcon#*before return 0, iclass 22, count 0 2006.176.07:51:40.63#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:51:40.63#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:51:40.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:51:40.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:51:40.63$vc4f8/vblo=1,632.99 2006.176.07:51:40.63#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.07:51:40.63#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.07:51:40.63#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:40.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:51:40.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:51:40.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:51:40.63#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:51:40.63#ibcon#first serial, iclass 24, count 0 2006.176.07:51:40.63#ibcon#enter sib2, iclass 24, count 0 2006.176.07:51:40.63#ibcon#flushed, iclass 24, count 0 2006.176.07:51:40.63#ibcon#about to write, iclass 24, count 0 2006.176.07:51:40.63#ibcon#wrote, iclass 24, count 0 2006.176.07:51:40.63#ibcon#about to read 3, iclass 24, count 0 2006.176.07:51:40.65#ibcon#read 3, iclass 24, count 0 2006.176.07:51:40.65#ibcon#about to read 4, iclass 24, count 0 2006.176.07:51:40.65#ibcon#read 4, iclass 24, count 0 2006.176.07:51:40.65#ibcon#about to read 5, iclass 24, count 0 2006.176.07:51:40.65#ibcon#read 5, iclass 24, count 0 2006.176.07:51:40.65#ibcon#about to read 6, iclass 24, count 0 2006.176.07:51:40.65#ibcon#read 6, iclass 24, count 0 2006.176.07:51:40.65#ibcon#end of sib2, iclass 24, count 0 2006.176.07:51:40.65#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:51:40.65#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:51:40.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:51:40.65#ibcon#*before write, iclass 24, count 0 2006.176.07:51:40.65#ibcon#enter sib2, iclass 24, count 0 2006.176.07:51:40.65#ibcon#flushed, iclass 24, count 0 2006.176.07:51:40.65#ibcon#about to write, iclass 24, count 0 2006.176.07:51:40.65#ibcon#wrote, iclass 24, count 0 2006.176.07:51:40.65#ibcon#about to read 3, iclass 24, count 0 2006.176.07:51:40.69#abcon#{5=INTERFACE CLEAR} 2006.176.07:51:40.69#ibcon#read 3, iclass 24, count 0 2006.176.07:51:40.69#ibcon#about to read 4, iclass 24, count 0 2006.176.07:51:40.69#ibcon#read 4, iclass 24, count 0 2006.176.07:51:40.69#ibcon#about to read 5, iclass 24, count 0 2006.176.07:51:40.69#ibcon#read 5, iclass 24, count 0 2006.176.07:51:40.69#ibcon#about to read 6, iclass 24, count 0 2006.176.07:51:40.69#ibcon#read 6, iclass 24, count 0 2006.176.07:51:40.69#ibcon#end of sib2, iclass 24, count 0 2006.176.07:51:40.69#ibcon#*after write, iclass 24, count 0 2006.176.07:51:40.69#ibcon#*before return 0, iclass 24, count 0 2006.176.07:51:40.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:51:40.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:51:40.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:51:40.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:51:40.69$vc4f8/vb=1,4 2006.176.07:51:40.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.07:51:40.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.07:51:40.69#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:40.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:51:40.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:51:40.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:51:40.69#ibcon#enter wrdev, iclass 27, count 2 2006.176.07:51:40.69#ibcon#first serial, iclass 27, count 2 2006.176.07:51:40.69#ibcon#enter sib2, iclass 27, count 2 2006.176.07:51:40.69#ibcon#flushed, iclass 27, count 2 2006.176.07:51:40.69#ibcon#about to write, iclass 27, count 2 2006.176.07:51:40.69#ibcon#wrote, iclass 27, count 2 2006.176.07:51:40.69#ibcon#about to read 3, iclass 27, count 2 2006.176.07:51:40.71#ibcon#read 3, iclass 27, count 2 2006.176.07:51:40.71#ibcon#about to read 4, iclass 27, count 2 2006.176.07:51:40.71#ibcon#read 4, iclass 27, count 2 2006.176.07:51:40.71#ibcon#about to read 5, iclass 27, count 2 2006.176.07:51:40.71#ibcon#read 5, iclass 27, count 2 2006.176.07:51:40.71#ibcon#about to read 6, iclass 27, count 2 2006.176.07:51:40.71#ibcon#read 6, iclass 27, count 2 2006.176.07:51:40.71#ibcon#end of sib2, iclass 27, count 2 2006.176.07:51:40.71#ibcon#*mode == 0, iclass 27, count 2 2006.176.07:51:40.71#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.07:51:40.71#ibcon#[27=AT01-04\r\n] 2006.176.07:51:40.71#ibcon#*before write, iclass 27, count 2 2006.176.07:51:40.71#ibcon#enter sib2, iclass 27, count 2 2006.176.07:51:40.71#ibcon#flushed, iclass 27, count 2 2006.176.07:51:40.71#ibcon#about to write, iclass 27, count 2 2006.176.07:51:40.71#ibcon#wrote, iclass 27, count 2 2006.176.07:51:40.71#ibcon#about to read 3, iclass 27, count 2 2006.176.07:51:40.74#ibcon#read 3, iclass 27, count 2 2006.176.07:51:40.74#ibcon#about to read 4, iclass 27, count 2 2006.176.07:51:40.74#ibcon#read 4, iclass 27, count 2 2006.176.07:51:40.74#ibcon#about to read 5, iclass 27, count 2 2006.176.07:51:40.74#ibcon#read 5, iclass 27, count 2 2006.176.07:51:40.74#ibcon#about to read 6, iclass 27, count 2 2006.176.07:51:40.74#ibcon#read 6, iclass 27, count 2 2006.176.07:51:40.74#ibcon#end of sib2, iclass 27, count 2 2006.176.07:51:40.74#ibcon#*after write, iclass 27, count 2 2006.176.07:51:40.74#ibcon#*before return 0, iclass 27, count 2 2006.176.07:51:40.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:51:40.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.07:51:40.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.07:51:40.74#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:40.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:51:40.75#abcon#[5=S1D000X0/0*\r\n] 2006.176.07:51:40.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:51:40.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:51:40.86#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:51:40.86#ibcon#first serial, iclass 27, count 0 2006.176.07:51:40.86#ibcon#enter sib2, iclass 27, count 0 2006.176.07:51:40.86#ibcon#flushed, iclass 27, count 0 2006.176.07:51:40.86#ibcon#about to write, iclass 27, count 0 2006.176.07:51:40.86#ibcon#wrote, iclass 27, count 0 2006.176.07:51:40.86#ibcon#about to read 3, iclass 27, count 0 2006.176.07:51:40.88#ibcon#read 3, iclass 27, count 0 2006.176.07:51:40.88#ibcon#about to read 4, iclass 27, count 0 2006.176.07:51:40.88#ibcon#read 4, iclass 27, count 0 2006.176.07:51:40.88#ibcon#about to read 5, iclass 27, count 0 2006.176.07:51:40.88#ibcon#read 5, iclass 27, count 0 2006.176.07:51:40.88#ibcon#about to read 6, iclass 27, count 0 2006.176.07:51:40.88#ibcon#read 6, iclass 27, count 0 2006.176.07:51:40.88#ibcon#end of sib2, iclass 27, count 0 2006.176.07:51:40.88#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:51:40.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:51:40.88#ibcon#[27=USB\r\n] 2006.176.07:51:40.88#ibcon#*before write, iclass 27, count 0 2006.176.07:51:40.88#ibcon#enter sib2, iclass 27, count 0 2006.176.07:51:40.88#ibcon#flushed, iclass 27, count 0 2006.176.07:51:40.88#ibcon#about to write, iclass 27, count 0 2006.176.07:51:40.88#ibcon#wrote, iclass 27, count 0 2006.176.07:51:40.88#ibcon#about to read 3, iclass 27, count 0 2006.176.07:51:40.91#ibcon#read 3, iclass 27, count 0 2006.176.07:51:40.91#ibcon#about to read 4, iclass 27, count 0 2006.176.07:51:40.91#ibcon#read 4, iclass 27, count 0 2006.176.07:51:40.91#ibcon#about to read 5, iclass 27, count 0 2006.176.07:51:40.91#ibcon#read 5, iclass 27, count 0 2006.176.07:51:40.91#ibcon#about to read 6, iclass 27, count 0 2006.176.07:51:40.91#ibcon#read 6, iclass 27, count 0 2006.176.07:51:40.91#ibcon#end of sib2, iclass 27, count 0 2006.176.07:51:40.91#ibcon#*after write, iclass 27, count 0 2006.176.07:51:40.91#ibcon#*before return 0, iclass 27, count 0 2006.176.07:51:40.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:51:40.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.07:51:40.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:51:40.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:51:40.91$vc4f8/vblo=2,640.99 2006.176.07:51:40.91#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.07:51:40.91#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.07:51:40.91#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:40.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:51:40.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:51:40.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:51:40.91#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:51:40.91#ibcon#first serial, iclass 30, count 0 2006.176.07:51:40.91#ibcon#enter sib2, iclass 30, count 0 2006.176.07:51:40.91#ibcon#flushed, iclass 30, count 0 2006.176.07:51:40.91#ibcon#about to write, iclass 30, count 0 2006.176.07:51:40.91#ibcon#wrote, iclass 30, count 0 2006.176.07:51:40.91#ibcon#about to read 3, iclass 30, count 0 2006.176.07:51:40.93#ibcon#read 3, iclass 30, count 0 2006.176.07:51:40.93#ibcon#about to read 4, iclass 30, count 0 2006.176.07:51:40.93#ibcon#read 4, iclass 30, count 0 2006.176.07:51:40.93#ibcon#about to read 5, iclass 30, count 0 2006.176.07:51:40.93#ibcon#read 5, iclass 30, count 0 2006.176.07:51:40.93#ibcon#about to read 6, iclass 30, count 0 2006.176.07:51:40.93#ibcon#read 6, iclass 30, count 0 2006.176.07:51:40.93#ibcon#end of sib2, iclass 30, count 0 2006.176.07:51:40.93#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:51:40.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:51:40.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:51:40.93#ibcon#*before write, iclass 30, count 0 2006.176.07:51:40.93#ibcon#enter sib2, iclass 30, count 0 2006.176.07:51:40.93#ibcon#flushed, iclass 30, count 0 2006.176.07:51:40.93#ibcon#about to write, iclass 30, count 0 2006.176.07:51:40.93#ibcon#wrote, iclass 30, count 0 2006.176.07:51:40.93#ibcon#about to read 3, iclass 30, count 0 2006.176.07:51:40.97#ibcon#read 3, iclass 30, count 0 2006.176.07:51:40.97#ibcon#about to read 4, iclass 30, count 0 2006.176.07:51:40.97#ibcon#read 4, iclass 30, count 0 2006.176.07:51:40.97#ibcon#about to read 5, iclass 30, count 0 2006.176.07:51:40.97#ibcon#read 5, iclass 30, count 0 2006.176.07:51:40.97#ibcon#about to read 6, iclass 30, count 0 2006.176.07:51:40.97#ibcon#read 6, iclass 30, count 0 2006.176.07:51:40.97#ibcon#end of sib2, iclass 30, count 0 2006.176.07:51:40.97#ibcon#*after write, iclass 30, count 0 2006.176.07:51:40.97#ibcon#*before return 0, iclass 30, count 0 2006.176.07:51:40.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:51:40.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.07:51:40.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:51:40.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:51:40.97$vc4f8/vb=2,4 2006.176.07:51:40.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.176.07:51:40.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.176.07:51:40.97#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:40.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:51:41.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:51:41.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:51:41.03#ibcon#enter wrdev, iclass 32, count 2 2006.176.07:51:41.03#ibcon#first serial, iclass 32, count 2 2006.176.07:51:41.03#ibcon#enter sib2, iclass 32, count 2 2006.176.07:51:41.03#ibcon#flushed, iclass 32, count 2 2006.176.07:51:41.03#ibcon#about to write, iclass 32, count 2 2006.176.07:51:41.03#ibcon#wrote, iclass 32, count 2 2006.176.07:51:41.03#ibcon#about to read 3, iclass 32, count 2 2006.176.07:51:41.05#ibcon#read 3, iclass 32, count 2 2006.176.07:51:41.05#ibcon#about to read 4, iclass 32, count 2 2006.176.07:51:41.05#ibcon#read 4, iclass 32, count 2 2006.176.07:51:41.05#ibcon#about to read 5, iclass 32, count 2 2006.176.07:51:41.05#ibcon#read 5, iclass 32, count 2 2006.176.07:51:41.05#ibcon#about to read 6, iclass 32, count 2 2006.176.07:51:41.05#ibcon#read 6, iclass 32, count 2 2006.176.07:51:41.05#ibcon#end of sib2, iclass 32, count 2 2006.176.07:51:41.05#ibcon#*mode == 0, iclass 32, count 2 2006.176.07:51:41.05#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.176.07:51:41.05#ibcon#[27=AT02-04\r\n] 2006.176.07:51:41.05#ibcon#*before write, iclass 32, count 2 2006.176.07:51:41.05#ibcon#enter sib2, iclass 32, count 2 2006.176.07:51:41.05#ibcon#flushed, iclass 32, count 2 2006.176.07:51:41.05#ibcon#about to write, iclass 32, count 2 2006.176.07:51:41.05#ibcon#wrote, iclass 32, count 2 2006.176.07:51:41.05#ibcon#about to read 3, iclass 32, count 2 2006.176.07:51:41.08#ibcon#read 3, iclass 32, count 2 2006.176.07:51:41.08#ibcon#about to read 4, iclass 32, count 2 2006.176.07:51:41.08#ibcon#read 4, iclass 32, count 2 2006.176.07:51:41.08#ibcon#about to read 5, iclass 32, count 2 2006.176.07:51:41.08#ibcon#read 5, iclass 32, count 2 2006.176.07:51:41.08#ibcon#about to read 6, iclass 32, count 2 2006.176.07:51:41.08#ibcon#read 6, iclass 32, count 2 2006.176.07:51:41.08#ibcon#end of sib2, iclass 32, count 2 2006.176.07:51:41.08#ibcon#*after write, iclass 32, count 2 2006.176.07:51:41.08#ibcon#*before return 0, iclass 32, count 2 2006.176.07:51:41.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:51:41.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.176.07:51:41.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.176.07:51:41.08#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:41.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:51:41.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:51:41.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:51:41.20#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:51:41.20#ibcon#first serial, iclass 32, count 0 2006.176.07:51:41.20#ibcon#enter sib2, iclass 32, count 0 2006.176.07:51:41.20#ibcon#flushed, iclass 32, count 0 2006.176.07:51:41.20#ibcon#about to write, iclass 32, count 0 2006.176.07:51:41.20#ibcon#wrote, iclass 32, count 0 2006.176.07:51:41.20#ibcon#about to read 3, iclass 32, count 0 2006.176.07:51:41.22#ibcon#read 3, iclass 32, count 0 2006.176.07:51:41.22#ibcon#about to read 4, iclass 32, count 0 2006.176.07:51:41.22#ibcon#read 4, iclass 32, count 0 2006.176.07:51:41.22#ibcon#about to read 5, iclass 32, count 0 2006.176.07:51:41.22#ibcon#read 5, iclass 32, count 0 2006.176.07:51:41.22#ibcon#about to read 6, iclass 32, count 0 2006.176.07:51:41.22#ibcon#read 6, iclass 32, count 0 2006.176.07:51:41.22#ibcon#end of sib2, iclass 32, count 0 2006.176.07:51:41.22#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:51:41.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:51:41.22#ibcon#[27=USB\r\n] 2006.176.07:51:41.22#ibcon#*before write, iclass 32, count 0 2006.176.07:51:41.22#ibcon#enter sib2, iclass 32, count 0 2006.176.07:51:41.22#ibcon#flushed, iclass 32, count 0 2006.176.07:51:41.22#ibcon#about to write, iclass 32, count 0 2006.176.07:51:41.22#ibcon#wrote, iclass 32, count 0 2006.176.07:51:41.22#ibcon#about to read 3, iclass 32, count 0 2006.176.07:51:41.25#ibcon#read 3, iclass 32, count 0 2006.176.07:51:41.25#ibcon#about to read 4, iclass 32, count 0 2006.176.07:51:41.25#ibcon#read 4, iclass 32, count 0 2006.176.07:51:41.25#ibcon#about to read 5, iclass 32, count 0 2006.176.07:51:41.25#ibcon#read 5, iclass 32, count 0 2006.176.07:51:41.25#ibcon#about to read 6, iclass 32, count 0 2006.176.07:51:41.25#ibcon#read 6, iclass 32, count 0 2006.176.07:51:41.25#ibcon#end of sib2, iclass 32, count 0 2006.176.07:51:41.25#ibcon#*after write, iclass 32, count 0 2006.176.07:51:41.25#ibcon#*before return 0, iclass 32, count 0 2006.176.07:51:41.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:51:41.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.176.07:51:41.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:51:41.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:51:41.25$vc4f8/vblo=3,656.99 2006.176.07:51:41.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.07:51:41.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.07:51:41.25#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:41.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:51:41.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:51:41.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:51:41.25#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:51:41.25#ibcon#first serial, iclass 34, count 0 2006.176.07:51:41.25#ibcon#enter sib2, iclass 34, count 0 2006.176.07:51:41.25#ibcon#flushed, iclass 34, count 0 2006.176.07:51:41.25#ibcon#about to write, iclass 34, count 0 2006.176.07:51:41.25#ibcon#wrote, iclass 34, count 0 2006.176.07:51:41.25#ibcon#about to read 3, iclass 34, count 0 2006.176.07:51:41.27#ibcon#read 3, iclass 34, count 0 2006.176.07:51:41.27#ibcon#about to read 4, iclass 34, count 0 2006.176.07:51:41.27#ibcon#read 4, iclass 34, count 0 2006.176.07:51:41.27#ibcon#about to read 5, iclass 34, count 0 2006.176.07:51:41.27#ibcon#read 5, iclass 34, count 0 2006.176.07:51:41.27#ibcon#about to read 6, iclass 34, count 0 2006.176.07:51:41.27#ibcon#read 6, iclass 34, count 0 2006.176.07:51:41.27#ibcon#end of sib2, iclass 34, count 0 2006.176.07:51:41.27#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:51:41.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:51:41.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:51:41.27#ibcon#*before write, iclass 34, count 0 2006.176.07:51:41.27#ibcon#enter sib2, iclass 34, count 0 2006.176.07:51:41.27#ibcon#flushed, iclass 34, count 0 2006.176.07:51:41.27#ibcon#about to write, iclass 34, count 0 2006.176.07:51:41.27#ibcon#wrote, iclass 34, count 0 2006.176.07:51:41.27#ibcon#about to read 3, iclass 34, count 0 2006.176.07:51:41.31#ibcon#read 3, iclass 34, count 0 2006.176.07:51:41.31#ibcon#about to read 4, iclass 34, count 0 2006.176.07:51:41.31#ibcon#read 4, iclass 34, count 0 2006.176.07:51:41.31#ibcon#about to read 5, iclass 34, count 0 2006.176.07:51:41.31#ibcon#read 5, iclass 34, count 0 2006.176.07:51:41.31#ibcon#about to read 6, iclass 34, count 0 2006.176.07:51:41.31#ibcon#read 6, iclass 34, count 0 2006.176.07:51:41.31#ibcon#end of sib2, iclass 34, count 0 2006.176.07:51:41.31#ibcon#*after write, iclass 34, count 0 2006.176.07:51:41.31#ibcon#*before return 0, iclass 34, count 0 2006.176.07:51:41.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:51:41.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:51:41.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:51:41.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:51:41.31$vc4f8/vb=3,4 2006.176.07:51:41.31#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.176.07:51:41.31#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.176.07:51:41.31#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:41.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:51:41.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:51:41.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:51:41.37#ibcon#enter wrdev, iclass 36, count 2 2006.176.07:51:41.37#ibcon#first serial, iclass 36, count 2 2006.176.07:51:41.37#ibcon#enter sib2, iclass 36, count 2 2006.176.07:51:41.37#ibcon#flushed, iclass 36, count 2 2006.176.07:51:41.37#ibcon#about to write, iclass 36, count 2 2006.176.07:51:41.37#ibcon#wrote, iclass 36, count 2 2006.176.07:51:41.37#ibcon#about to read 3, iclass 36, count 2 2006.176.07:51:41.39#ibcon#read 3, iclass 36, count 2 2006.176.07:51:41.39#ibcon#about to read 4, iclass 36, count 2 2006.176.07:51:41.39#ibcon#read 4, iclass 36, count 2 2006.176.07:51:41.39#ibcon#about to read 5, iclass 36, count 2 2006.176.07:51:41.39#ibcon#read 5, iclass 36, count 2 2006.176.07:51:41.39#ibcon#about to read 6, iclass 36, count 2 2006.176.07:51:41.39#ibcon#read 6, iclass 36, count 2 2006.176.07:51:41.39#ibcon#end of sib2, iclass 36, count 2 2006.176.07:51:41.39#ibcon#*mode == 0, iclass 36, count 2 2006.176.07:51:41.39#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.176.07:51:41.39#ibcon#[27=AT03-04\r\n] 2006.176.07:51:41.39#ibcon#*before write, iclass 36, count 2 2006.176.07:51:41.39#ibcon#enter sib2, iclass 36, count 2 2006.176.07:51:41.39#ibcon#flushed, iclass 36, count 2 2006.176.07:51:41.39#ibcon#about to write, iclass 36, count 2 2006.176.07:51:41.39#ibcon#wrote, iclass 36, count 2 2006.176.07:51:41.39#ibcon#about to read 3, iclass 36, count 2 2006.176.07:51:41.42#ibcon#read 3, iclass 36, count 2 2006.176.07:51:41.42#ibcon#about to read 4, iclass 36, count 2 2006.176.07:51:41.42#ibcon#read 4, iclass 36, count 2 2006.176.07:51:41.42#ibcon#about to read 5, iclass 36, count 2 2006.176.07:51:41.42#ibcon#read 5, iclass 36, count 2 2006.176.07:51:41.42#ibcon#about to read 6, iclass 36, count 2 2006.176.07:51:41.42#ibcon#read 6, iclass 36, count 2 2006.176.07:51:41.42#ibcon#end of sib2, iclass 36, count 2 2006.176.07:51:41.42#ibcon#*after write, iclass 36, count 2 2006.176.07:51:41.42#ibcon#*before return 0, iclass 36, count 2 2006.176.07:51:41.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:51:41.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.176.07:51:41.42#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.176.07:51:41.42#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:41.42#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:51:41.54#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:51:41.54#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:51:41.54#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:51:41.54#ibcon#first serial, iclass 36, count 0 2006.176.07:51:41.54#ibcon#enter sib2, iclass 36, count 0 2006.176.07:51:41.54#ibcon#flushed, iclass 36, count 0 2006.176.07:51:41.54#ibcon#about to write, iclass 36, count 0 2006.176.07:51:41.54#ibcon#wrote, iclass 36, count 0 2006.176.07:51:41.54#ibcon#about to read 3, iclass 36, count 0 2006.176.07:51:41.56#ibcon#read 3, iclass 36, count 0 2006.176.07:51:41.56#ibcon#about to read 4, iclass 36, count 0 2006.176.07:51:41.56#ibcon#read 4, iclass 36, count 0 2006.176.07:51:41.56#ibcon#about to read 5, iclass 36, count 0 2006.176.07:51:41.56#ibcon#read 5, iclass 36, count 0 2006.176.07:51:41.56#ibcon#about to read 6, iclass 36, count 0 2006.176.07:51:41.56#ibcon#read 6, iclass 36, count 0 2006.176.07:51:41.56#ibcon#end of sib2, iclass 36, count 0 2006.176.07:51:41.56#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:51:41.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:51:41.56#ibcon#[27=USB\r\n] 2006.176.07:51:41.56#ibcon#*before write, iclass 36, count 0 2006.176.07:51:41.56#ibcon#enter sib2, iclass 36, count 0 2006.176.07:51:41.56#ibcon#flushed, iclass 36, count 0 2006.176.07:51:41.56#ibcon#about to write, iclass 36, count 0 2006.176.07:51:41.56#ibcon#wrote, iclass 36, count 0 2006.176.07:51:41.56#ibcon#about to read 3, iclass 36, count 0 2006.176.07:51:41.59#ibcon#read 3, iclass 36, count 0 2006.176.07:51:41.59#ibcon#about to read 4, iclass 36, count 0 2006.176.07:51:41.59#ibcon#read 4, iclass 36, count 0 2006.176.07:51:41.59#ibcon#about to read 5, iclass 36, count 0 2006.176.07:51:41.59#ibcon#read 5, iclass 36, count 0 2006.176.07:51:41.59#ibcon#about to read 6, iclass 36, count 0 2006.176.07:51:41.59#ibcon#read 6, iclass 36, count 0 2006.176.07:51:41.59#ibcon#end of sib2, iclass 36, count 0 2006.176.07:51:41.59#ibcon#*after write, iclass 36, count 0 2006.176.07:51:41.59#ibcon#*before return 0, iclass 36, count 0 2006.176.07:51:41.59#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:51:41.59#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.176.07:51:41.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:51:41.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:51:41.59$vc4f8/vblo=4,712.99 2006.176.07:51:41.59#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.07:51:41.59#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.07:51:41.59#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:41.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:51:41.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:51:41.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:51:41.59#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:51:41.59#ibcon#first serial, iclass 38, count 0 2006.176.07:51:41.59#ibcon#enter sib2, iclass 38, count 0 2006.176.07:51:41.59#ibcon#flushed, iclass 38, count 0 2006.176.07:51:41.59#ibcon#about to write, iclass 38, count 0 2006.176.07:51:41.59#ibcon#wrote, iclass 38, count 0 2006.176.07:51:41.59#ibcon#about to read 3, iclass 38, count 0 2006.176.07:51:41.61#ibcon#read 3, iclass 38, count 0 2006.176.07:51:41.61#ibcon#about to read 4, iclass 38, count 0 2006.176.07:51:41.61#ibcon#read 4, iclass 38, count 0 2006.176.07:51:41.61#ibcon#about to read 5, iclass 38, count 0 2006.176.07:51:41.61#ibcon#read 5, iclass 38, count 0 2006.176.07:51:41.61#ibcon#about to read 6, iclass 38, count 0 2006.176.07:51:41.61#ibcon#read 6, iclass 38, count 0 2006.176.07:51:41.61#ibcon#end of sib2, iclass 38, count 0 2006.176.07:51:41.61#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:51:41.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:51:41.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:51:41.61#ibcon#*before write, iclass 38, count 0 2006.176.07:51:41.61#ibcon#enter sib2, iclass 38, count 0 2006.176.07:51:41.61#ibcon#flushed, iclass 38, count 0 2006.176.07:51:41.61#ibcon#about to write, iclass 38, count 0 2006.176.07:51:41.61#ibcon#wrote, iclass 38, count 0 2006.176.07:51:41.61#ibcon#about to read 3, iclass 38, count 0 2006.176.07:51:41.65#ibcon#read 3, iclass 38, count 0 2006.176.07:51:41.65#ibcon#about to read 4, iclass 38, count 0 2006.176.07:51:41.65#ibcon#read 4, iclass 38, count 0 2006.176.07:51:41.65#ibcon#about to read 5, iclass 38, count 0 2006.176.07:51:41.65#ibcon#read 5, iclass 38, count 0 2006.176.07:51:41.65#ibcon#about to read 6, iclass 38, count 0 2006.176.07:51:41.65#ibcon#read 6, iclass 38, count 0 2006.176.07:51:41.65#ibcon#end of sib2, iclass 38, count 0 2006.176.07:51:41.65#ibcon#*after write, iclass 38, count 0 2006.176.07:51:41.65#ibcon#*before return 0, iclass 38, count 0 2006.176.07:51:41.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:51:41.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.07:51:41.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:51:41.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:51:41.65$vc4f8/vb=4,4 2006.176.07:51:41.65#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.07:51:41.65#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.07:51:41.65#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:41.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:51:41.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:51:41.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:51:41.71#ibcon#enter wrdev, iclass 40, count 2 2006.176.07:51:41.71#ibcon#first serial, iclass 40, count 2 2006.176.07:51:41.71#ibcon#enter sib2, iclass 40, count 2 2006.176.07:51:41.71#ibcon#flushed, iclass 40, count 2 2006.176.07:51:41.71#ibcon#about to write, iclass 40, count 2 2006.176.07:51:41.71#ibcon#wrote, iclass 40, count 2 2006.176.07:51:41.71#ibcon#about to read 3, iclass 40, count 2 2006.176.07:51:41.73#ibcon#read 3, iclass 40, count 2 2006.176.07:51:41.73#ibcon#about to read 4, iclass 40, count 2 2006.176.07:51:41.73#ibcon#read 4, iclass 40, count 2 2006.176.07:51:41.73#ibcon#about to read 5, iclass 40, count 2 2006.176.07:51:41.73#ibcon#read 5, iclass 40, count 2 2006.176.07:51:41.73#ibcon#about to read 6, iclass 40, count 2 2006.176.07:51:41.73#ibcon#read 6, iclass 40, count 2 2006.176.07:51:41.73#ibcon#end of sib2, iclass 40, count 2 2006.176.07:51:41.73#ibcon#*mode == 0, iclass 40, count 2 2006.176.07:51:41.73#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.07:51:41.73#ibcon#[27=AT04-04\r\n] 2006.176.07:51:41.73#ibcon#*before write, iclass 40, count 2 2006.176.07:51:41.73#ibcon#enter sib2, iclass 40, count 2 2006.176.07:51:41.73#ibcon#flushed, iclass 40, count 2 2006.176.07:51:41.73#ibcon#about to write, iclass 40, count 2 2006.176.07:51:41.73#ibcon#wrote, iclass 40, count 2 2006.176.07:51:41.73#ibcon#about to read 3, iclass 40, count 2 2006.176.07:51:41.76#ibcon#read 3, iclass 40, count 2 2006.176.07:51:41.76#ibcon#about to read 4, iclass 40, count 2 2006.176.07:51:41.76#ibcon#read 4, iclass 40, count 2 2006.176.07:51:41.76#ibcon#about to read 5, iclass 40, count 2 2006.176.07:51:41.76#ibcon#read 5, iclass 40, count 2 2006.176.07:51:41.76#ibcon#about to read 6, iclass 40, count 2 2006.176.07:51:41.76#ibcon#read 6, iclass 40, count 2 2006.176.07:51:41.76#ibcon#end of sib2, iclass 40, count 2 2006.176.07:51:41.76#ibcon#*after write, iclass 40, count 2 2006.176.07:51:41.76#ibcon#*before return 0, iclass 40, count 2 2006.176.07:51:41.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:51:41.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.07:51:41.76#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.07:51:41.76#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:41.76#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:51:41.88#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:51:41.88#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:51:41.88#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:51:41.88#ibcon#first serial, iclass 40, count 0 2006.176.07:51:41.88#ibcon#enter sib2, iclass 40, count 0 2006.176.07:51:41.88#ibcon#flushed, iclass 40, count 0 2006.176.07:51:41.88#ibcon#about to write, iclass 40, count 0 2006.176.07:51:41.88#ibcon#wrote, iclass 40, count 0 2006.176.07:51:41.88#ibcon#about to read 3, iclass 40, count 0 2006.176.07:51:41.90#ibcon#read 3, iclass 40, count 0 2006.176.07:51:41.90#ibcon#about to read 4, iclass 40, count 0 2006.176.07:51:41.90#ibcon#read 4, iclass 40, count 0 2006.176.07:51:41.90#ibcon#about to read 5, iclass 40, count 0 2006.176.07:51:41.90#ibcon#read 5, iclass 40, count 0 2006.176.07:51:41.90#ibcon#about to read 6, iclass 40, count 0 2006.176.07:51:41.90#ibcon#read 6, iclass 40, count 0 2006.176.07:51:41.90#ibcon#end of sib2, iclass 40, count 0 2006.176.07:51:41.90#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:51:41.90#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:51:41.90#ibcon#[27=USB\r\n] 2006.176.07:51:41.90#ibcon#*before write, iclass 40, count 0 2006.176.07:51:41.90#ibcon#enter sib2, iclass 40, count 0 2006.176.07:51:41.90#ibcon#flushed, iclass 40, count 0 2006.176.07:51:41.90#ibcon#about to write, iclass 40, count 0 2006.176.07:51:41.90#ibcon#wrote, iclass 40, count 0 2006.176.07:51:41.90#ibcon#about to read 3, iclass 40, count 0 2006.176.07:51:41.93#ibcon#read 3, iclass 40, count 0 2006.176.07:51:41.93#ibcon#about to read 4, iclass 40, count 0 2006.176.07:51:41.93#ibcon#read 4, iclass 40, count 0 2006.176.07:51:41.93#ibcon#about to read 5, iclass 40, count 0 2006.176.07:51:41.93#ibcon#read 5, iclass 40, count 0 2006.176.07:51:41.93#ibcon#about to read 6, iclass 40, count 0 2006.176.07:51:41.93#ibcon#read 6, iclass 40, count 0 2006.176.07:51:41.93#ibcon#end of sib2, iclass 40, count 0 2006.176.07:51:41.93#ibcon#*after write, iclass 40, count 0 2006.176.07:51:41.93#ibcon#*before return 0, iclass 40, count 0 2006.176.07:51:41.93#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:51:41.93#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.07:51:41.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:51:41.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:51:41.93$vc4f8/vblo=5,744.99 2006.176.07:51:41.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.07:51:41.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.07:51:41.93#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:41.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:51:41.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:51:41.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:51:41.93#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:51:41.93#ibcon#first serial, iclass 4, count 0 2006.176.07:51:41.93#ibcon#enter sib2, iclass 4, count 0 2006.176.07:51:41.93#ibcon#flushed, iclass 4, count 0 2006.176.07:51:41.93#ibcon#about to write, iclass 4, count 0 2006.176.07:51:41.93#ibcon#wrote, iclass 4, count 0 2006.176.07:51:41.93#ibcon#about to read 3, iclass 4, count 0 2006.176.07:51:41.95#ibcon#read 3, iclass 4, count 0 2006.176.07:51:41.95#ibcon#about to read 4, iclass 4, count 0 2006.176.07:51:41.95#ibcon#read 4, iclass 4, count 0 2006.176.07:51:41.95#ibcon#about to read 5, iclass 4, count 0 2006.176.07:51:41.95#ibcon#read 5, iclass 4, count 0 2006.176.07:51:41.95#ibcon#about to read 6, iclass 4, count 0 2006.176.07:51:41.95#ibcon#read 6, iclass 4, count 0 2006.176.07:51:41.95#ibcon#end of sib2, iclass 4, count 0 2006.176.07:51:41.95#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:51:41.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:51:41.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:51:41.95#ibcon#*before write, iclass 4, count 0 2006.176.07:51:41.95#ibcon#enter sib2, iclass 4, count 0 2006.176.07:51:41.95#ibcon#flushed, iclass 4, count 0 2006.176.07:51:41.95#ibcon#about to write, iclass 4, count 0 2006.176.07:51:41.95#ibcon#wrote, iclass 4, count 0 2006.176.07:51:41.95#ibcon#about to read 3, iclass 4, count 0 2006.176.07:51:41.99#ibcon#read 3, iclass 4, count 0 2006.176.07:51:41.99#ibcon#about to read 4, iclass 4, count 0 2006.176.07:51:41.99#ibcon#read 4, iclass 4, count 0 2006.176.07:51:41.99#ibcon#about to read 5, iclass 4, count 0 2006.176.07:51:41.99#ibcon#read 5, iclass 4, count 0 2006.176.07:51:41.99#ibcon#about to read 6, iclass 4, count 0 2006.176.07:51:41.99#ibcon#read 6, iclass 4, count 0 2006.176.07:51:41.99#ibcon#end of sib2, iclass 4, count 0 2006.176.07:51:41.99#ibcon#*after write, iclass 4, count 0 2006.176.07:51:41.99#ibcon#*before return 0, iclass 4, count 0 2006.176.07:51:41.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:51:41.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.07:51:41.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:51:41.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:51:41.99$vc4f8/vb=5,4 2006.176.07:51:41.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.07:51:41.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.07:51:41.99#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:41.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:51:42.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:51:42.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:51:42.05#ibcon#enter wrdev, iclass 6, count 2 2006.176.07:51:42.05#ibcon#first serial, iclass 6, count 2 2006.176.07:51:42.05#ibcon#enter sib2, iclass 6, count 2 2006.176.07:51:42.05#ibcon#flushed, iclass 6, count 2 2006.176.07:51:42.05#ibcon#about to write, iclass 6, count 2 2006.176.07:51:42.05#ibcon#wrote, iclass 6, count 2 2006.176.07:51:42.05#ibcon#about to read 3, iclass 6, count 2 2006.176.07:51:42.07#ibcon#read 3, iclass 6, count 2 2006.176.07:51:42.07#ibcon#about to read 4, iclass 6, count 2 2006.176.07:51:42.07#ibcon#read 4, iclass 6, count 2 2006.176.07:51:42.07#ibcon#about to read 5, iclass 6, count 2 2006.176.07:51:42.07#ibcon#read 5, iclass 6, count 2 2006.176.07:51:42.07#ibcon#about to read 6, iclass 6, count 2 2006.176.07:51:42.07#ibcon#read 6, iclass 6, count 2 2006.176.07:51:42.07#ibcon#end of sib2, iclass 6, count 2 2006.176.07:51:42.07#ibcon#*mode == 0, iclass 6, count 2 2006.176.07:51:42.07#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.07:51:42.07#ibcon#[27=AT05-04\r\n] 2006.176.07:51:42.07#ibcon#*before write, iclass 6, count 2 2006.176.07:51:42.07#ibcon#enter sib2, iclass 6, count 2 2006.176.07:51:42.07#ibcon#flushed, iclass 6, count 2 2006.176.07:51:42.07#ibcon#about to write, iclass 6, count 2 2006.176.07:51:42.07#ibcon#wrote, iclass 6, count 2 2006.176.07:51:42.07#ibcon#about to read 3, iclass 6, count 2 2006.176.07:51:42.10#ibcon#read 3, iclass 6, count 2 2006.176.07:51:42.10#ibcon#about to read 4, iclass 6, count 2 2006.176.07:51:42.10#ibcon#read 4, iclass 6, count 2 2006.176.07:51:42.10#ibcon#about to read 5, iclass 6, count 2 2006.176.07:51:42.10#ibcon#read 5, iclass 6, count 2 2006.176.07:51:42.10#ibcon#about to read 6, iclass 6, count 2 2006.176.07:51:42.10#ibcon#read 6, iclass 6, count 2 2006.176.07:51:42.10#ibcon#end of sib2, iclass 6, count 2 2006.176.07:51:42.10#ibcon#*after write, iclass 6, count 2 2006.176.07:51:42.10#ibcon#*before return 0, iclass 6, count 2 2006.176.07:51:42.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:51:42.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.07:51:42.10#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.07:51:42.10#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:42.10#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:51:42.22#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:51:42.22#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:51:42.22#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:51:42.22#ibcon#first serial, iclass 6, count 0 2006.176.07:51:42.22#ibcon#enter sib2, iclass 6, count 0 2006.176.07:51:42.22#ibcon#flushed, iclass 6, count 0 2006.176.07:51:42.22#ibcon#about to write, iclass 6, count 0 2006.176.07:51:42.22#ibcon#wrote, iclass 6, count 0 2006.176.07:51:42.22#ibcon#about to read 3, iclass 6, count 0 2006.176.07:51:42.24#ibcon#read 3, iclass 6, count 0 2006.176.07:51:42.24#ibcon#about to read 4, iclass 6, count 0 2006.176.07:51:42.24#ibcon#read 4, iclass 6, count 0 2006.176.07:51:42.24#ibcon#about to read 5, iclass 6, count 0 2006.176.07:51:42.24#ibcon#read 5, iclass 6, count 0 2006.176.07:51:42.24#ibcon#about to read 6, iclass 6, count 0 2006.176.07:51:42.24#ibcon#read 6, iclass 6, count 0 2006.176.07:51:42.24#ibcon#end of sib2, iclass 6, count 0 2006.176.07:51:42.24#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:51:42.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:51:42.24#ibcon#[27=USB\r\n] 2006.176.07:51:42.24#ibcon#*before write, iclass 6, count 0 2006.176.07:51:42.24#ibcon#enter sib2, iclass 6, count 0 2006.176.07:51:42.24#ibcon#flushed, iclass 6, count 0 2006.176.07:51:42.24#ibcon#about to write, iclass 6, count 0 2006.176.07:51:42.24#ibcon#wrote, iclass 6, count 0 2006.176.07:51:42.24#ibcon#about to read 3, iclass 6, count 0 2006.176.07:51:42.27#ibcon#read 3, iclass 6, count 0 2006.176.07:51:42.27#ibcon#about to read 4, iclass 6, count 0 2006.176.07:51:42.27#ibcon#read 4, iclass 6, count 0 2006.176.07:51:42.27#ibcon#about to read 5, iclass 6, count 0 2006.176.07:51:42.27#ibcon#read 5, iclass 6, count 0 2006.176.07:51:42.27#ibcon#about to read 6, iclass 6, count 0 2006.176.07:51:42.27#ibcon#read 6, iclass 6, count 0 2006.176.07:51:42.27#ibcon#end of sib2, iclass 6, count 0 2006.176.07:51:42.27#ibcon#*after write, iclass 6, count 0 2006.176.07:51:42.27#ibcon#*before return 0, iclass 6, count 0 2006.176.07:51:42.27#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:51:42.27#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.07:51:42.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:51:42.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:51:42.27$vc4f8/vblo=6,752.99 2006.176.07:51:42.27#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.07:51:42.27#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.07:51:42.27#ibcon#ireg 17 cls_cnt 0 2006.176.07:51:42.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:51:42.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:51:42.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:51:42.27#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:51:42.27#ibcon#first serial, iclass 10, count 0 2006.176.07:51:42.27#ibcon#enter sib2, iclass 10, count 0 2006.176.07:51:42.27#ibcon#flushed, iclass 10, count 0 2006.176.07:51:42.27#ibcon#about to write, iclass 10, count 0 2006.176.07:51:42.27#ibcon#wrote, iclass 10, count 0 2006.176.07:51:42.27#ibcon#about to read 3, iclass 10, count 0 2006.176.07:51:42.29#ibcon#read 3, iclass 10, count 0 2006.176.07:51:42.29#ibcon#about to read 4, iclass 10, count 0 2006.176.07:51:42.29#ibcon#read 4, iclass 10, count 0 2006.176.07:51:42.29#ibcon#about to read 5, iclass 10, count 0 2006.176.07:51:42.29#ibcon#read 5, iclass 10, count 0 2006.176.07:51:42.29#ibcon#about to read 6, iclass 10, count 0 2006.176.07:51:42.29#ibcon#read 6, iclass 10, count 0 2006.176.07:51:42.29#ibcon#end of sib2, iclass 10, count 0 2006.176.07:51:42.29#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:51:42.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:51:42.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:51:42.29#ibcon#*before write, iclass 10, count 0 2006.176.07:51:42.29#ibcon#enter sib2, iclass 10, count 0 2006.176.07:51:42.29#ibcon#flushed, iclass 10, count 0 2006.176.07:51:42.29#ibcon#about to write, iclass 10, count 0 2006.176.07:51:42.29#ibcon#wrote, iclass 10, count 0 2006.176.07:51:42.29#ibcon#about to read 3, iclass 10, count 0 2006.176.07:51:42.33#ibcon#read 3, iclass 10, count 0 2006.176.07:51:42.33#ibcon#about to read 4, iclass 10, count 0 2006.176.07:51:42.33#ibcon#read 4, iclass 10, count 0 2006.176.07:51:42.33#ibcon#about to read 5, iclass 10, count 0 2006.176.07:51:42.33#ibcon#read 5, iclass 10, count 0 2006.176.07:51:42.33#ibcon#about to read 6, iclass 10, count 0 2006.176.07:51:42.33#ibcon#read 6, iclass 10, count 0 2006.176.07:51:42.33#ibcon#end of sib2, iclass 10, count 0 2006.176.07:51:42.33#ibcon#*after write, iclass 10, count 0 2006.176.07:51:42.33#ibcon#*before return 0, iclass 10, count 0 2006.176.07:51:42.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:51:42.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.07:51:42.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:51:42.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:51:42.33$vc4f8/vb=6,4 2006.176.07:51:42.33#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.07:51:42.33#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.07:51:42.33#ibcon#ireg 11 cls_cnt 2 2006.176.07:51:42.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:51:42.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:51:42.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:51:42.39#ibcon#enter wrdev, iclass 12, count 2 2006.176.07:51:42.39#ibcon#first serial, iclass 12, count 2 2006.176.07:51:42.39#ibcon#enter sib2, iclass 12, count 2 2006.176.07:51:42.39#ibcon#flushed, iclass 12, count 2 2006.176.07:51:42.39#ibcon#about to write, iclass 12, count 2 2006.176.07:51:42.39#ibcon#wrote, iclass 12, count 2 2006.176.07:51:42.39#ibcon#about to read 3, iclass 12, count 2 2006.176.07:51:42.41#ibcon#read 3, iclass 12, count 2 2006.176.07:51:42.41#ibcon#about to read 4, iclass 12, count 2 2006.176.07:51:42.41#ibcon#read 4, iclass 12, count 2 2006.176.07:51:42.41#ibcon#about to read 5, iclass 12, count 2 2006.176.07:51:42.41#ibcon#read 5, iclass 12, count 2 2006.176.07:51:42.41#ibcon#about to read 6, iclass 12, count 2 2006.176.07:51:42.41#ibcon#read 6, iclass 12, count 2 2006.176.07:51:42.41#ibcon#end of sib2, iclass 12, count 2 2006.176.07:51:42.41#ibcon#*mode == 0, iclass 12, count 2 2006.176.07:51:42.41#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.07:51:42.41#ibcon#[27=AT06-04\r\n] 2006.176.07:51:42.41#ibcon#*before write, iclass 12, count 2 2006.176.07:51:42.41#ibcon#enter sib2, iclass 12, count 2 2006.176.07:51:42.41#ibcon#flushed, iclass 12, count 2 2006.176.07:51:42.41#ibcon#about to write, iclass 12, count 2 2006.176.07:51:42.41#ibcon#wrote, iclass 12, count 2 2006.176.07:51:42.41#ibcon#about to read 3, iclass 12, count 2 2006.176.07:51:42.44#ibcon#read 3, iclass 12, count 2 2006.176.07:51:42.44#ibcon#about to read 4, iclass 12, count 2 2006.176.07:51:42.44#ibcon#read 4, iclass 12, count 2 2006.176.07:51:42.44#ibcon#about to read 5, iclass 12, count 2 2006.176.07:51:42.44#ibcon#read 5, iclass 12, count 2 2006.176.07:51:42.44#ibcon#about to read 6, iclass 12, count 2 2006.176.07:51:42.44#ibcon#read 6, iclass 12, count 2 2006.176.07:51:42.44#ibcon#end of sib2, iclass 12, count 2 2006.176.07:51:42.44#ibcon#*after write, iclass 12, count 2 2006.176.07:51:42.44#ibcon#*before return 0, iclass 12, count 2 2006.176.07:51:42.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:51:42.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.07:51:42.44#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.07:51:42.44#ibcon#ireg 7 cls_cnt 0 2006.176.07:51:42.44#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:51:42.56#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:51:42.56#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:51:42.56#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:51:42.56#ibcon#first serial, iclass 12, count 0 2006.176.07:51:42.56#ibcon#enter sib2, iclass 12, count 0 2006.176.07:51:42.56#ibcon#flushed, iclass 12, count 0 2006.176.07:51:42.56#ibcon#about to write, iclass 12, count 0 2006.176.07:51:42.56#ibcon#wrote, iclass 12, count 0 2006.176.07:51:42.56#ibcon#about to read 3, iclass 12, count 0 2006.176.07:51:42.58#ibcon#read 3, iclass 12, count 0 2006.176.07:51:42.58#ibcon#about to read 4, iclass 12, count 0 2006.176.07:51:42.58#ibcon#read 4, iclass 12, count 0 2006.176.07:51:42.58#ibcon#about to read 5, iclass 12, count 0 2006.176.07:51:42.58#ibcon#read 5, iclass 12, count 0 2006.176.07:51:42.58#ibcon#about to read 6, iclass 12, count 0 2006.176.07:51:42.58#ibcon#read 6, iclass 12, count 0 2006.176.07:51:42.58#ibcon#end of sib2, iclass 12, count 0 2006.176.07:51:42.58#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:51:42.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:51:42.58#ibcon#[27=USB\r\n] 2006.176.07:51:42.58#ibcon#*before write, iclass 12, count 0 2006.176.07:51:42.58#ibcon#enter sib2, iclass 12, count 0 2006.176.07:51:42.58#ibcon#flushed, iclass 12, count 0 2006.176.07:51:42.58#ibcon#about to write, iclass 12, count 0 2006.176.07:51:42.58#ibcon#wrote, iclass 12, count 0 2006.176.07:51:42.58#ibcon#about to read 3, iclass 12, count 0 2006.176.07:51:42.61#ibcon#read 3, iclass 12, count 0 2006.176.07:51:42.61#ibcon#about to read 4, iclass 12, count 0 2006.176.07:51:42.61#ibcon#read 4, iclass 12, count 0 2006.176.07:51:42.61#ibcon#about to read 5, iclass 12, count 0 2006.176.07:51:42.61#ibcon#read 5, iclass 12, count 0 2006.176.07:51:42.61#ibcon#about to read 6, iclass 12, count 0 2006.176.07:51:42.61#ibcon#read 6, iclass 12, count 0 2006.176.07:51:42.61#ibcon#end of sib2, iclass 12, count 0 2006.176.07:51:42.61#ibcon#*after write, iclass 12, count 0 2006.176.07:51:42.61#ibcon#*before return 0, iclass 12, count 0 2006.176.07:51:42.61#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:51:42.61#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.07:51:42.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:51:42.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:51:42.61$vc4f8/vabw=wide 2006.176.07:51:42.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.07:51:42.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.07:51:42.61#ibcon#ireg 8 cls_cnt 0 2006.176.07:51:42.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:51:42.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:51:42.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:51:42.61#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:51:42.61#ibcon#first serial, iclass 14, count 0 2006.176.07:51:42.61#ibcon#enter sib2, iclass 14, count 0 2006.176.07:51:42.61#ibcon#flushed, iclass 14, count 0 2006.176.07:51:42.61#ibcon#about to write, iclass 14, count 0 2006.176.07:51:42.61#ibcon#wrote, iclass 14, count 0 2006.176.07:51:42.61#ibcon#about to read 3, iclass 14, count 0 2006.176.07:51:42.63#ibcon#read 3, iclass 14, count 0 2006.176.07:51:42.63#ibcon#about to read 4, iclass 14, count 0 2006.176.07:51:42.63#ibcon#read 4, iclass 14, count 0 2006.176.07:51:42.63#ibcon#about to read 5, iclass 14, count 0 2006.176.07:51:42.63#ibcon#read 5, iclass 14, count 0 2006.176.07:51:42.63#ibcon#about to read 6, iclass 14, count 0 2006.176.07:51:42.63#ibcon#read 6, iclass 14, count 0 2006.176.07:51:42.63#ibcon#end of sib2, iclass 14, count 0 2006.176.07:51:42.63#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:51:42.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:51:42.63#ibcon#[25=BW32\r\n] 2006.176.07:51:42.63#ibcon#*before write, iclass 14, count 0 2006.176.07:51:42.63#ibcon#enter sib2, iclass 14, count 0 2006.176.07:51:42.63#ibcon#flushed, iclass 14, count 0 2006.176.07:51:42.63#ibcon#about to write, iclass 14, count 0 2006.176.07:51:42.63#ibcon#wrote, iclass 14, count 0 2006.176.07:51:42.63#ibcon#about to read 3, iclass 14, count 0 2006.176.07:51:42.66#ibcon#read 3, iclass 14, count 0 2006.176.07:51:42.66#ibcon#about to read 4, iclass 14, count 0 2006.176.07:51:42.66#ibcon#read 4, iclass 14, count 0 2006.176.07:51:42.66#ibcon#about to read 5, iclass 14, count 0 2006.176.07:51:42.66#ibcon#read 5, iclass 14, count 0 2006.176.07:51:42.66#ibcon#about to read 6, iclass 14, count 0 2006.176.07:51:42.66#ibcon#read 6, iclass 14, count 0 2006.176.07:51:42.66#ibcon#end of sib2, iclass 14, count 0 2006.176.07:51:42.66#ibcon#*after write, iclass 14, count 0 2006.176.07:51:42.66#ibcon#*before return 0, iclass 14, count 0 2006.176.07:51:42.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:51:42.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.07:51:42.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:51:42.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:51:42.66$vc4f8/vbbw=wide 2006.176.07:51:42.66#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:51:42.66#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:51:42.66#ibcon#ireg 8 cls_cnt 0 2006.176.07:51:42.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:42.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:42.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:42.73#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:51:42.73#ibcon#first serial, iclass 16, count 0 2006.176.07:51:42.73#ibcon#enter sib2, iclass 16, count 0 2006.176.07:51:42.73#ibcon#flushed, iclass 16, count 0 2006.176.07:51:42.73#ibcon#about to write, iclass 16, count 0 2006.176.07:51:42.73#ibcon#wrote, iclass 16, count 0 2006.176.07:51:42.73#ibcon#about to read 3, iclass 16, count 0 2006.176.07:51:42.75#ibcon#read 3, iclass 16, count 0 2006.176.07:51:42.75#ibcon#about to read 4, iclass 16, count 0 2006.176.07:51:42.75#ibcon#read 4, iclass 16, count 0 2006.176.07:51:42.75#ibcon#about to read 5, iclass 16, count 0 2006.176.07:51:42.75#ibcon#read 5, iclass 16, count 0 2006.176.07:51:42.75#ibcon#about to read 6, iclass 16, count 0 2006.176.07:51:42.75#ibcon#read 6, iclass 16, count 0 2006.176.07:51:42.75#ibcon#end of sib2, iclass 16, count 0 2006.176.07:51:42.75#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:51:42.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:51:42.75#ibcon#[27=BW32\r\n] 2006.176.07:51:42.75#ibcon#*before write, iclass 16, count 0 2006.176.07:51:42.75#ibcon#enter sib2, iclass 16, count 0 2006.176.07:51:42.75#ibcon#flushed, iclass 16, count 0 2006.176.07:51:42.75#ibcon#about to write, iclass 16, count 0 2006.176.07:51:42.75#ibcon#wrote, iclass 16, count 0 2006.176.07:51:42.75#ibcon#about to read 3, iclass 16, count 0 2006.176.07:51:42.78#ibcon#read 3, iclass 16, count 0 2006.176.07:51:42.78#ibcon#about to read 4, iclass 16, count 0 2006.176.07:51:42.78#ibcon#read 4, iclass 16, count 0 2006.176.07:51:42.78#ibcon#about to read 5, iclass 16, count 0 2006.176.07:51:42.78#ibcon#read 5, iclass 16, count 0 2006.176.07:51:42.78#ibcon#about to read 6, iclass 16, count 0 2006.176.07:51:42.78#ibcon#read 6, iclass 16, count 0 2006.176.07:51:42.78#ibcon#end of sib2, iclass 16, count 0 2006.176.07:51:42.78#ibcon#*after write, iclass 16, count 0 2006.176.07:51:42.78#ibcon#*before return 0, iclass 16, count 0 2006.176.07:51:42.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:42.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:51:42.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:51:42.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:51:42.78$4f8m12a/ifd4f 2006.176.07:51:42.78$ifd4f/lo= 2006.176.07:51:42.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:51:42.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:51:42.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:51:42.78$ifd4f/patch= 2006.176.07:51:42.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:51:42.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:51:42.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:51:42.78$4f8m12a/"form=m,16.000,1:2 2006.176.07:51:42.78$4f8m12a/"tpicd 2006.176.07:51:42.78$4f8m12a/echo=off 2006.176.07:51:42.78$4f8m12a/xlog=off 2006.176.07:51:42.78:!2006.176.07:52:20 2006.176.07:52:04.14#trakl#Source acquired 2006.176.07:52:04.14#flagr#flagr/antenna,acquired 2006.176.07:52:20.00:preob 2006.176.07:52:20.14/onsource/TRACKING 2006.176.07:52:20.14:!2006.176.07:52:30 2006.176.07:52:30.02:data_valid=on 2006.176.07:52:30.02:midob 2006.176.07:52:31.14/onsource/TRACKING 2006.176.07:52:31.14/wx/23.87,1008.4,91 2006.176.07:52:31.34/cable/+6.4933E-03 2006.176.07:52:32.43/va/01,08,usb,yes,29,31 2006.176.07:52:32.43/va/02,07,usb,yes,29,31 2006.176.07:52:32.43/va/03,06,usb,yes,31,31 2006.176.07:52:32.43/va/04,07,usb,yes,30,32 2006.176.07:52:32.43/va/05,07,usb,yes,32,33 2006.176.07:52:32.43/va/06,06,usb,yes,31,30 2006.176.07:52:32.43/va/07,06,usb,yes,31,31 2006.176.07:52:32.43/va/08,06,usb,yes,33,33 2006.176.07:52:32.66/valo/01,532.99,yes,locked 2006.176.07:52:32.66/valo/02,572.99,yes,locked 2006.176.07:52:32.66/valo/03,672.99,yes,locked 2006.176.07:52:32.66/valo/04,832.99,yes,locked 2006.176.07:52:32.66/valo/05,652.99,yes,locked 2006.176.07:52:32.66/valo/06,772.99,yes,locked 2006.176.07:52:32.66/valo/07,832.99,yes,locked 2006.176.07:52:32.66/valo/08,852.99,yes,locked 2006.176.07:52:33.75/vb/01,04,usb,yes,29,28 2006.176.07:52:33.75/vb/02,04,usb,yes,31,32 2006.176.07:52:33.75/vb/03,04,usb,yes,27,31 2006.176.07:52:33.75/vb/04,04,usb,yes,28,28 2006.176.07:52:33.75/vb/05,04,usb,yes,27,31 2006.176.07:52:33.75/vb/06,04,usb,yes,28,30 2006.176.07:52:33.75/vb/07,04,usb,yes,30,29 2006.176.07:52:33.75/vb/08,04,usb,yes,27,30 2006.176.07:52:33.99/vblo/01,632.99,yes,locked 2006.176.07:52:33.99/vblo/02,640.99,yes,locked 2006.176.07:52:33.99/vblo/03,656.99,yes,locked 2006.176.07:52:33.99/vblo/04,712.99,yes,locked 2006.176.07:52:33.99/vblo/05,744.99,yes,locked 2006.176.07:52:33.99/vblo/06,752.99,yes,locked 2006.176.07:52:33.99/vblo/07,734.99,yes,locked 2006.176.07:52:33.99/vblo/08,744.99,yes,locked 2006.176.07:52:34.14/vabw/8 2006.176.07:52:34.29/vbbw/8 2006.176.07:52:34.38/xfe/off,on,15.2 2006.176.07:52:34.76/ifatt/23,28,28,28 2006.176.07:52:35.08/fmout-gps/S +3.75E-07 2006.176.07:52:35.15:!2006.176.07:53:30 2006.176.07:53:30.02:data_valid=off 2006.176.07:53:30.02:postob 2006.176.07:53:30.10/cable/+6.4937E-03 2006.176.07:53:30.10/wx/23.86,1008.4,91 2006.176.07:53:31.08/fmout-gps/S +3.74E-07 2006.176.07:53:31.08:scan_name=176-0755,k06176,60 2006.176.07:53:31.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.176.07:53:31.16#flagr#flagr/antenna,new-source 2006.176.07:53:32.14:checkk5 2006.176.07:53:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:53:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:53:33.30/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:53:33.71/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:53:34.09/chk_obsdata//k5ts1/T1760752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:53:34.46/chk_obsdata//k5ts2/T1760752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:53:34.82/chk_obsdata//k5ts3/T1760752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:53:35.21/chk_obsdata//k5ts4/T1760752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:53:35.91/k5log//k5ts1_log_newline 2006.176.07:53:36.60/k5log//k5ts2_log_newline 2006.176.07:53:37.29/k5log//k5ts3_log_newline 2006.176.07:53:37.97/k5log//k5ts4_log_newline 2006.176.07:53:37.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:53:37.99:4f8m12a=2 2006.176.07:53:37.99$4f8m12a/echo=on 2006.176.07:53:37.99$4f8m12a/pcalon 2006.176.07:53:37.99$pcalon/"no phase cal control is implemented here 2006.176.07:53:37.99$4f8m12a/"tpicd=stop 2006.176.07:53:37.99$4f8m12a/vc4f8 2006.176.07:53:37.99$vc4f8/valo=1,532.99 2006.176.07:53:38.00#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.07:53:38.00#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.07:53:38.00#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:38.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:38.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:38.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:38.00#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:53:38.00#ibcon#first serial, iclass 27, count 0 2006.176.07:53:38.00#ibcon#enter sib2, iclass 27, count 0 2006.176.07:53:38.00#ibcon#flushed, iclass 27, count 0 2006.176.07:53:38.00#ibcon#about to write, iclass 27, count 0 2006.176.07:53:38.00#ibcon#wrote, iclass 27, count 0 2006.176.07:53:38.00#ibcon#about to read 3, iclass 27, count 0 2006.176.07:53:38.04#ibcon#read 3, iclass 27, count 0 2006.176.07:53:38.04#ibcon#about to read 4, iclass 27, count 0 2006.176.07:53:38.04#ibcon#read 4, iclass 27, count 0 2006.176.07:53:38.04#ibcon#about to read 5, iclass 27, count 0 2006.176.07:53:38.04#ibcon#read 5, iclass 27, count 0 2006.176.07:53:38.04#ibcon#about to read 6, iclass 27, count 0 2006.176.07:53:38.04#ibcon#read 6, iclass 27, count 0 2006.176.07:53:38.04#ibcon#end of sib2, iclass 27, count 0 2006.176.07:53:38.04#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:53:38.04#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:53:38.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:53:38.04#ibcon#*before write, iclass 27, count 0 2006.176.07:53:38.04#ibcon#enter sib2, iclass 27, count 0 2006.176.07:53:38.04#ibcon#flushed, iclass 27, count 0 2006.176.07:53:38.04#ibcon#about to write, iclass 27, count 0 2006.176.07:53:38.04#ibcon#wrote, iclass 27, count 0 2006.176.07:53:38.04#ibcon#about to read 3, iclass 27, count 0 2006.176.07:53:38.08#ibcon#read 3, iclass 27, count 0 2006.176.07:53:38.08#ibcon#about to read 4, iclass 27, count 0 2006.176.07:53:38.08#ibcon#read 4, iclass 27, count 0 2006.176.07:53:38.08#ibcon#about to read 5, iclass 27, count 0 2006.176.07:53:38.08#ibcon#read 5, iclass 27, count 0 2006.176.07:53:38.08#ibcon#about to read 6, iclass 27, count 0 2006.176.07:53:38.08#ibcon#read 6, iclass 27, count 0 2006.176.07:53:38.08#ibcon#end of sib2, iclass 27, count 0 2006.176.07:53:38.08#ibcon#*after write, iclass 27, count 0 2006.176.07:53:38.08#ibcon#*before return 0, iclass 27, count 0 2006.176.07:53:38.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:38.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:38.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:53:38.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:53:38.09$vc4f8/va=1,8 2006.176.07:53:38.09#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.07:53:38.09#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.07:53:38.09#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:38.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:38.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:38.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:38.09#ibcon#enter wrdev, iclass 29, count 2 2006.176.07:53:38.09#ibcon#first serial, iclass 29, count 2 2006.176.07:53:38.09#ibcon#enter sib2, iclass 29, count 2 2006.176.07:53:38.09#ibcon#flushed, iclass 29, count 2 2006.176.07:53:38.09#ibcon#about to write, iclass 29, count 2 2006.176.07:53:38.09#ibcon#wrote, iclass 29, count 2 2006.176.07:53:38.09#ibcon#about to read 3, iclass 29, count 2 2006.176.07:53:38.10#ibcon#read 3, iclass 29, count 2 2006.176.07:53:38.10#ibcon#about to read 4, iclass 29, count 2 2006.176.07:53:38.10#ibcon#read 4, iclass 29, count 2 2006.176.07:53:38.10#ibcon#about to read 5, iclass 29, count 2 2006.176.07:53:38.10#ibcon#read 5, iclass 29, count 2 2006.176.07:53:38.10#ibcon#about to read 6, iclass 29, count 2 2006.176.07:53:38.10#ibcon#read 6, iclass 29, count 2 2006.176.07:53:38.10#ibcon#end of sib2, iclass 29, count 2 2006.176.07:53:38.10#ibcon#*mode == 0, iclass 29, count 2 2006.176.07:53:38.10#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.07:53:38.10#ibcon#[25=AT01-08\r\n] 2006.176.07:53:38.10#ibcon#*before write, iclass 29, count 2 2006.176.07:53:38.10#ibcon#enter sib2, iclass 29, count 2 2006.176.07:53:38.11#ibcon#flushed, iclass 29, count 2 2006.176.07:53:38.11#ibcon#about to write, iclass 29, count 2 2006.176.07:53:38.11#ibcon#wrote, iclass 29, count 2 2006.176.07:53:38.11#ibcon#about to read 3, iclass 29, count 2 2006.176.07:53:38.14#ibcon#read 3, iclass 29, count 2 2006.176.07:53:38.14#ibcon#about to read 4, iclass 29, count 2 2006.176.07:53:38.14#ibcon#read 4, iclass 29, count 2 2006.176.07:53:38.14#ibcon#about to read 5, iclass 29, count 2 2006.176.07:53:38.14#ibcon#read 5, iclass 29, count 2 2006.176.07:53:38.14#ibcon#about to read 6, iclass 29, count 2 2006.176.07:53:38.14#ibcon#read 6, iclass 29, count 2 2006.176.07:53:38.14#ibcon#end of sib2, iclass 29, count 2 2006.176.07:53:38.14#ibcon#*after write, iclass 29, count 2 2006.176.07:53:38.14#ibcon#*before return 0, iclass 29, count 2 2006.176.07:53:38.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:38.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:38.14#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.07:53:38.14#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:38.14#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:38.25#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:38.25#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:38.25#ibcon#enter wrdev, iclass 29, count 0 2006.176.07:53:38.25#ibcon#first serial, iclass 29, count 0 2006.176.07:53:38.25#ibcon#enter sib2, iclass 29, count 0 2006.176.07:53:38.25#ibcon#flushed, iclass 29, count 0 2006.176.07:53:38.25#ibcon#about to write, iclass 29, count 0 2006.176.07:53:38.25#ibcon#wrote, iclass 29, count 0 2006.176.07:53:38.25#ibcon#about to read 3, iclass 29, count 0 2006.176.07:53:38.27#ibcon#read 3, iclass 29, count 0 2006.176.07:53:38.27#ibcon#about to read 4, iclass 29, count 0 2006.176.07:53:38.27#ibcon#read 4, iclass 29, count 0 2006.176.07:53:38.27#ibcon#about to read 5, iclass 29, count 0 2006.176.07:53:38.27#ibcon#read 5, iclass 29, count 0 2006.176.07:53:38.27#ibcon#about to read 6, iclass 29, count 0 2006.176.07:53:38.27#ibcon#read 6, iclass 29, count 0 2006.176.07:53:38.27#ibcon#end of sib2, iclass 29, count 0 2006.176.07:53:38.27#ibcon#*mode == 0, iclass 29, count 0 2006.176.07:53:38.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.07:53:38.27#ibcon#[25=USB\r\n] 2006.176.07:53:38.27#ibcon#*before write, iclass 29, count 0 2006.176.07:53:38.27#ibcon#enter sib2, iclass 29, count 0 2006.176.07:53:38.27#ibcon#flushed, iclass 29, count 0 2006.176.07:53:38.27#ibcon#about to write, iclass 29, count 0 2006.176.07:53:38.28#ibcon#wrote, iclass 29, count 0 2006.176.07:53:38.28#ibcon#about to read 3, iclass 29, count 0 2006.176.07:53:38.30#ibcon#read 3, iclass 29, count 0 2006.176.07:53:38.30#ibcon#about to read 4, iclass 29, count 0 2006.176.07:53:38.30#ibcon#read 4, iclass 29, count 0 2006.176.07:53:38.30#ibcon#about to read 5, iclass 29, count 0 2006.176.07:53:38.30#ibcon#read 5, iclass 29, count 0 2006.176.07:53:38.30#ibcon#about to read 6, iclass 29, count 0 2006.176.07:53:38.30#ibcon#read 6, iclass 29, count 0 2006.176.07:53:38.30#ibcon#end of sib2, iclass 29, count 0 2006.176.07:53:38.30#ibcon#*after write, iclass 29, count 0 2006.176.07:53:38.30#ibcon#*before return 0, iclass 29, count 0 2006.176.07:53:38.30#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:38.30#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:38.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.07:53:38.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.07:53:38.31$vc4f8/valo=2,572.99 2006.176.07:53:38.31#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.07:53:38.31#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.07:53:38.31#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:38.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:38.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:38.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:38.31#ibcon#enter wrdev, iclass 31, count 0 2006.176.07:53:38.31#ibcon#first serial, iclass 31, count 0 2006.176.07:53:38.31#ibcon#enter sib2, iclass 31, count 0 2006.176.07:53:38.31#ibcon#flushed, iclass 31, count 0 2006.176.07:53:38.31#ibcon#about to write, iclass 31, count 0 2006.176.07:53:38.31#ibcon#wrote, iclass 31, count 0 2006.176.07:53:38.31#ibcon#about to read 3, iclass 31, count 0 2006.176.07:53:38.33#ibcon#read 3, iclass 31, count 0 2006.176.07:53:38.33#ibcon#about to read 4, iclass 31, count 0 2006.176.07:53:38.33#ibcon#read 4, iclass 31, count 0 2006.176.07:53:38.33#ibcon#about to read 5, iclass 31, count 0 2006.176.07:53:38.33#ibcon#read 5, iclass 31, count 0 2006.176.07:53:38.33#ibcon#about to read 6, iclass 31, count 0 2006.176.07:53:38.33#ibcon#read 6, iclass 31, count 0 2006.176.07:53:38.33#ibcon#end of sib2, iclass 31, count 0 2006.176.07:53:38.33#ibcon#*mode == 0, iclass 31, count 0 2006.176.07:53:38.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.07:53:38.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:53:38.33#ibcon#*before write, iclass 31, count 0 2006.176.07:53:38.33#ibcon#enter sib2, iclass 31, count 0 2006.176.07:53:38.33#ibcon#flushed, iclass 31, count 0 2006.176.07:53:38.33#ibcon#about to write, iclass 31, count 0 2006.176.07:53:38.33#ibcon#wrote, iclass 31, count 0 2006.176.07:53:38.33#ibcon#about to read 3, iclass 31, count 0 2006.176.07:53:38.36#ibcon#read 3, iclass 31, count 0 2006.176.07:53:38.36#ibcon#about to read 4, iclass 31, count 0 2006.176.07:53:38.36#ibcon#read 4, iclass 31, count 0 2006.176.07:53:38.36#ibcon#about to read 5, iclass 31, count 0 2006.176.07:53:38.36#ibcon#read 5, iclass 31, count 0 2006.176.07:53:38.36#ibcon#about to read 6, iclass 31, count 0 2006.176.07:53:38.36#ibcon#read 6, iclass 31, count 0 2006.176.07:53:38.36#ibcon#end of sib2, iclass 31, count 0 2006.176.07:53:38.36#ibcon#*after write, iclass 31, count 0 2006.176.07:53:38.36#ibcon#*before return 0, iclass 31, count 0 2006.176.07:53:38.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:38.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:38.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.07:53:38.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.07:53:38.37$vc4f8/va=2,7 2006.176.07:53:38.37#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.176.07:53:38.37#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.176.07:53:38.37#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:38.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:38.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:38.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:38.42#ibcon#enter wrdev, iclass 33, count 2 2006.176.07:53:38.42#ibcon#first serial, iclass 33, count 2 2006.176.07:53:38.42#ibcon#enter sib2, iclass 33, count 2 2006.176.07:53:38.42#ibcon#flushed, iclass 33, count 2 2006.176.07:53:38.42#ibcon#about to write, iclass 33, count 2 2006.176.07:53:38.42#ibcon#wrote, iclass 33, count 2 2006.176.07:53:38.42#ibcon#about to read 3, iclass 33, count 2 2006.176.07:53:38.44#ibcon#read 3, iclass 33, count 2 2006.176.07:53:38.44#ibcon#about to read 4, iclass 33, count 2 2006.176.07:53:38.44#ibcon#read 4, iclass 33, count 2 2006.176.07:53:38.44#ibcon#about to read 5, iclass 33, count 2 2006.176.07:53:38.44#ibcon#read 5, iclass 33, count 2 2006.176.07:53:38.44#ibcon#about to read 6, iclass 33, count 2 2006.176.07:53:38.44#ibcon#read 6, iclass 33, count 2 2006.176.07:53:38.44#ibcon#end of sib2, iclass 33, count 2 2006.176.07:53:38.44#ibcon#*mode == 0, iclass 33, count 2 2006.176.07:53:38.44#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.176.07:53:38.44#ibcon#[25=AT02-07\r\n] 2006.176.07:53:38.44#ibcon#*before write, iclass 33, count 2 2006.176.07:53:38.44#ibcon#enter sib2, iclass 33, count 2 2006.176.07:53:38.44#ibcon#flushed, iclass 33, count 2 2006.176.07:53:38.44#ibcon#about to write, iclass 33, count 2 2006.176.07:53:38.44#ibcon#wrote, iclass 33, count 2 2006.176.07:53:38.44#ibcon#about to read 3, iclass 33, count 2 2006.176.07:53:38.46#ibcon#read 3, iclass 33, count 2 2006.176.07:53:38.46#ibcon#about to read 4, iclass 33, count 2 2006.176.07:53:38.46#ibcon#read 4, iclass 33, count 2 2006.176.07:53:38.46#ibcon#about to read 5, iclass 33, count 2 2006.176.07:53:38.46#ibcon#read 5, iclass 33, count 2 2006.176.07:53:38.46#ibcon#about to read 6, iclass 33, count 2 2006.176.07:53:38.46#ibcon#read 6, iclass 33, count 2 2006.176.07:53:38.46#ibcon#end of sib2, iclass 33, count 2 2006.176.07:53:38.46#ibcon#*after write, iclass 33, count 2 2006.176.07:53:38.46#ibcon#*before return 0, iclass 33, count 2 2006.176.07:53:38.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:38.47#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:38.47#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.176.07:53:38.47#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:38.47#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:38.58#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:38.58#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:38.58#ibcon#enter wrdev, iclass 33, count 0 2006.176.07:53:38.58#ibcon#first serial, iclass 33, count 0 2006.176.07:53:38.58#ibcon#enter sib2, iclass 33, count 0 2006.176.07:53:38.58#ibcon#flushed, iclass 33, count 0 2006.176.07:53:38.58#ibcon#about to write, iclass 33, count 0 2006.176.07:53:38.58#ibcon#wrote, iclass 33, count 0 2006.176.07:53:38.58#ibcon#about to read 3, iclass 33, count 0 2006.176.07:53:38.60#ibcon#read 3, iclass 33, count 0 2006.176.07:53:38.60#ibcon#about to read 4, iclass 33, count 0 2006.176.07:53:38.60#ibcon#read 4, iclass 33, count 0 2006.176.07:53:38.60#ibcon#about to read 5, iclass 33, count 0 2006.176.07:53:38.60#ibcon#read 5, iclass 33, count 0 2006.176.07:53:38.60#ibcon#about to read 6, iclass 33, count 0 2006.176.07:53:38.60#ibcon#read 6, iclass 33, count 0 2006.176.07:53:38.60#ibcon#end of sib2, iclass 33, count 0 2006.176.07:53:38.60#ibcon#*mode == 0, iclass 33, count 0 2006.176.07:53:38.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.07:53:38.60#ibcon#[25=USB\r\n] 2006.176.07:53:38.60#ibcon#*before write, iclass 33, count 0 2006.176.07:53:38.60#ibcon#enter sib2, iclass 33, count 0 2006.176.07:53:38.60#ibcon#flushed, iclass 33, count 0 2006.176.07:53:38.60#ibcon#about to write, iclass 33, count 0 2006.176.07:53:38.61#ibcon#wrote, iclass 33, count 0 2006.176.07:53:38.61#ibcon#about to read 3, iclass 33, count 0 2006.176.07:53:38.63#ibcon#read 3, iclass 33, count 0 2006.176.07:53:38.63#ibcon#about to read 4, iclass 33, count 0 2006.176.07:53:38.63#ibcon#read 4, iclass 33, count 0 2006.176.07:53:38.63#ibcon#about to read 5, iclass 33, count 0 2006.176.07:53:38.63#ibcon#read 5, iclass 33, count 0 2006.176.07:53:38.63#ibcon#about to read 6, iclass 33, count 0 2006.176.07:53:38.63#ibcon#read 6, iclass 33, count 0 2006.176.07:53:38.63#ibcon#end of sib2, iclass 33, count 0 2006.176.07:53:38.63#ibcon#*after write, iclass 33, count 0 2006.176.07:53:38.63#ibcon#*before return 0, iclass 33, count 0 2006.176.07:53:38.63#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:38.63#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:38.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.07:53:38.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.07:53:38.64$vc4f8/valo=3,672.99 2006.176.07:53:38.64#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.07:53:38.64#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.07:53:38.64#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:38.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:38.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:38.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:38.64#ibcon#enter wrdev, iclass 35, count 0 2006.176.07:53:38.64#ibcon#first serial, iclass 35, count 0 2006.176.07:53:38.64#ibcon#enter sib2, iclass 35, count 0 2006.176.07:53:38.64#ibcon#flushed, iclass 35, count 0 2006.176.07:53:38.64#ibcon#about to write, iclass 35, count 0 2006.176.07:53:38.64#ibcon#wrote, iclass 35, count 0 2006.176.07:53:38.64#ibcon#about to read 3, iclass 35, count 0 2006.176.07:53:38.66#ibcon#read 3, iclass 35, count 0 2006.176.07:53:38.66#ibcon#about to read 4, iclass 35, count 0 2006.176.07:53:38.66#ibcon#read 4, iclass 35, count 0 2006.176.07:53:38.66#ibcon#about to read 5, iclass 35, count 0 2006.176.07:53:38.66#ibcon#read 5, iclass 35, count 0 2006.176.07:53:38.66#ibcon#about to read 6, iclass 35, count 0 2006.176.07:53:38.66#ibcon#read 6, iclass 35, count 0 2006.176.07:53:38.66#ibcon#end of sib2, iclass 35, count 0 2006.176.07:53:38.66#ibcon#*mode == 0, iclass 35, count 0 2006.176.07:53:38.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.07:53:38.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:53:38.66#ibcon#*before write, iclass 35, count 0 2006.176.07:53:38.66#ibcon#enter sib2, iclass 35, count 0 2006.176.07:53:38.66#ibcon#flushed, iclass 35, count 0 2006.176.07:53:38.66#ibcon#about to write, iclass 35, count 0 2006.176.07:53:38.66#ibcon#wrote, iclass 35, count 0 2006.176.07:53:38.66#ibcon#about to read 3, iclass 35, count 0 2006.176.07:53:38.69#ibcon#read 3, iclass 35, count 0 2006.176.07:53:38.69#ibcon#about to read 4, iclass 35, count 0 2006.176.07:53:38.69#ibcon#read 4, iclass 35, count 0 2006.176.07:53:38.69#ibcon#about to read 5, iclass 35, count 0 2006.176.07:53:38.69#ibcon#read 5, iclass 35, count 0 2006.176.07:53:38.69#ibcon#about to read 6, iclass 35, count 0 2006.176.07:53:38.69#ibcon#read 6, iclass 35, count 0 2006.176.07:53:38.69#ibcon#end of sib2, iclass 35, count 0 2006.176.07:53:38.69#ibcon#*after write, iclass 35, count 0 2006.176.07:53:38.69#ibcon#*before return 0, iclass 35, count 0 2006.176.07:53:38.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:38.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:38.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.07:53:38.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.07:53:38.70$vc4f8/va=3,6 2006.176.07:53:38.70#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.176.07:53:38.70#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.176.07:53:38.70#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:38.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:38.75#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:38.75#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:38.75#ibcon#enter wrdev, iclass 37, count 2 2006.176.07:53:38.75#ibcon#first serial, iclass 37, count 2 2006.176.07:53:38.75#ibcon#enter sib2, iclass 37, count 2 2006.176.07:53:38.75#ibcon#flushed, iclass 37, count 2 2006.176.07:53:38.75#ibcon#about to write, iclass 37, count 2 2006.176.07:53:38.75#ibcon#wrote, iclass 37, count 2 2006.176.07:53:38.75#ibcon#about to read 3, iclass 37, count 2 2006.176.07:53:38.77#ibcon#read 3, iclass 37, count 2 2006.176.07:53:38.77#ibcon#about to read 4, iclass 37, count 2 2006.176.07:53:38.77#ibcon#read 4, iclass 37, count 2 2006.176.07:53:38.77#ibcon#about to read 5, iclass 37, count 2 2006.176.07:53:38.77#ibcon#read 5, iclass 37, count 2 2006.176.07:53:38.77#ibcon#about to read 6, iclass 37, count 2 2006.176.07:53:38.77#ibcon#read 6, iclass 37, count 2 2006.176.07:53:38.77#ibcon#end of sib2, iclass 37, count 2 2006.176.07:53:38.77#ibcon#*mode == 0, iclass 37, count 2 2006.176.07:53:38.77#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.176.07:53:38.77#ibcon#[25=AT03-06\r\n] 2006.176.07:53:38.77#ibcon#*before write, iclass 37, count 2 2006.176.07:53:38.77#ibcon#enter sib2, iclass 37, count 2 2006.176.07:53:38.77#ibcon#flushed, iclass 37, count 2 2006.176.07:53:38.77#ibcon#about to write, iclass 37, count 2 2006.176.07:53:38.77#ibcon#wrote, iclass 37, count 2 2006.176.07:53:38.77#ibcon#about to read 3, iclass 37, count 2 2006.176.07:53:38.79#ibcon#read 3, iclass 37, count 2 2006.176.07:53:38.79#ibcon#about to read 4, iclass 37, count 2 2006.176.07:53:38.79#ibcon#read 4, iclass 37, count 2 2006.176.07:53:38.79#ibcon#about to read 5, iclass 37, count 2 2006.176.07:53:38.79#ibcon#read 5, iclass 37, count 2 2006.176.07:53:38.79#ibcon#about to read 6, iclass 37, count 2 2006.176.07:53:38.79#ibcon#read 6, iclass 37, count 2 2006.176.07:53:38.79#ibcon#end of sib2, iclass 37, count 2 2006.176.07:53:38.79#ibcon#*after write, iclass 37, count 2 2006.176.07:53:38.79#ibcon#*before return 0, iclass 37, count 2 2006.176.07:53:38.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:38.80#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:38.80#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.176.07:53:38.80#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:38.80#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:38.91#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:38.91#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:38.91#ibcon#enter wrdev, iclass 37, count 0 2006.176.07:53:38.91#ibcon#first serial, iclass 37, count 0 2006.176.07:53:38.91#ibcon#enter sib2, iclass 37, count 0 2006.176.07:53:38.91#ibcon#flushed, iclass 37, count 0 2006.176.07:53:38.91#ibcon#about to write, iclass 37, count 0 2006.176.07:53:38.91#ibcon#wrote, iclass 37, count 0 2006.176.07:53:38.91#ibcon#about to read 3, iclass 37, count 0 2006.176.07:53:38.93#ibcon#read 3, iclass 37, count 0 2006.176.07:53:38.93#ibcon#about to read 4, iclass 37, count 0 2006.176.07:53:38.93#ibcon#read 4, iclass 37, count 0 2006.176.07:53:38.93#ibcon#about to read 5, iclass 37, count 0 2006.176.07:53:38.93#ibcon#read 5, iclass 37, count 0 2006.176.07:53:38.93#ibcon#about to read 6, iclass 37, count 0 2006.176.07:53:38.93#ibcon#read 6, iclass 37, count 0 2006.176.07:53:38.93#ibcon#end of sib2, iclass 37, count 0 2006.176.07:53:38.93#ibcon#*mode == 0, iclass 37, count 0 2006.176.07:53:38.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.07:53:38.93#ibcon#[25=USB\r\n] 2006.176.07:53:38.93#ibcon#*before write, iclass 37, count 0 2006.176.07:53:38.93#ibcon#enter sib2, iclass 37, count 0 2006.176.07:53:38.93#ibcon#flushed, iclass 37, count 0 2006.176.07:53:38.93#ibcon#about to write, iclass 37, count 0 2006.176.07:53:38.94#ibcon#wrote, iclass 37, count 0 2006.176.07:53:38.94#ibcon#about to read 3, iclass 37, count 0 2006.176.07:53:38.96#ibcon#read 3, iclass 37, count 0 2006.176.07:53:38.96#ibcon#about to read 4, iclass 37, count 0 2006.176.07:53:38.96#ibcon#read 4, iclass 37, count 0 2006.176.07:53:38.96#ibcon#about to read 5, iclass 37, count 0 2006.176.07:53:38.96#ibcon#read 5, iclass 37, count 0 2006.176.07:53:38.96#ibcon#about to read 6, iclass 37, count 0 2006.176.07:53:38.96#ibcon#read 6, iclass 37, count 0 2006.176.07:53:38.96#ibcon#end of sib2, iclass 37, count 0 2006.176.07:53:38.96#ibcon#*after write, iclass 37, count 0 2006.176.07:53:38.96#ibcon#*before return 0, iclass 37, count 0 2006.176.07:53:38.96#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:38.96#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:38.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.07:53:38.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.07:53:38.97$vc4f8/valo=4,832.99 2006.176.07:53:38.97#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.07:53:38.97#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.07:53:38.97#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:38.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:38.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:38.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:38.97#ibcon#enter wrdev, iclass 39, count 0 2006.176.07:53:38.97#ibcon#first serial, iclass 39, count 0 2006.176.07:53:38.97#ibcon#enter sib2, iclass 39, count 0 2006.176.07:53:38.97#ibcon#flushed, iclass 39, count 0 2006.176.07:53:38.97#ibcon#about to write, iclass 39, count 0 2006.176.07:53:38.97#ibcon#wrote, iclass 39, count 0 2006.176.07:53:38.97#ibcon#about to read 3, iclass 39, count 0 2006.176.07:53:38.98#ibcon#read 3, iclass 39, count 0 2006.176.07:53:38.98#ibcon#about to read 4, iclass 39, count 0 2006.176.07:53:38.98#ibcon#read 4, iclass 39, count 0 2006.176.07:53:38.98#ibcon#about to read 5, iclass 39, count 0 2006.176.07:53:38.98#ibcon#read 5, iclass 39, count 0 2006.176.07:53:38.98#ibcon#about to read 6, iclass 39, count 0 2006.176.07:53:38.98#ibcon#read 6, iclass 39, count 0 2006.176.07:53:38.98#ibcon#end of sib2, iclass 39, count 0 2006.176.07:53:38.98#ibcon#*mode == 0, iclass 39, count 0 2006.176.07:53:38.98#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.07:53:38.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:53:38.98#ibcon#*before write, iclass 39, count 0 2006.176.07:53:38.98#ibcon#enter sib2, iclass 39, count 0 2006.176.07:53:38.98#ibcon#flushed, iclass 39, count 0 2006.176.07:53:38.98#ibcon#about to write, iclass 39, count 0 2006.176.07:53:38.99#ibcon#wrote, iclass 39, count 0 2006.176.07:53:38.99#ibcon#about to read 3, iclass 39, count 0 2006.176.07:53:39.02#ibcon#read 3, iclass 39, count 0 2006.176.07:53:39.02#ibcon#about to read 4, iclass 39, count 0 2006.176.07:53:39.02#ibcon#read 4, iclass 39, count 0 2006.176.07:53:39.02#ibcon#about to read 5, iclass 39, count 0 2006.176.07:53:39.02#ibcon#read 5, iclass 39, count 0 2006.176.07:53:39.02#ibcon#about to read 6, iclass 39, count 0 2006.176.07:53:39.02#ibcon#read 6, iclass 39, count 0 2006.176.07:53:39.02#ibcon#end of sib2, iclass 39, count 0 2006.176.07:53:39.02#ibcon#*after write, iclass 39, count 0 2006.176.07:53:39.02#ibcon#*before return 0, iclass 39, count 0 2006.176.07:53:39.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:39.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:39.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.07:53:39.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.07:53:39.03$vc4f8/va=4,7 2006.176.07:53:39.03#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.07:53:39.03#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.07:53:39.03#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:39.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:39.07#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:39.07#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:39.07#ibcon#enter wrdev, iclass 3, count 2 2006.176.07:53:39.07#ibcon#first serial, iclass 3, count 2 2006.176.07:53:39.07#ibcon#enter sib2, iclass 3, count 2 2006.176.07:53:39.07#ibcon#flushed, iclass 3, count 2 2006.176.07:53:39.07#ibcon#about to write, iclass 3, count 2 2006.176.07:53:39.07#ibcon#wrote, iclass 3, count 2 2006.176.07:53:39.07#ibcon#about to read 3, iclass 3, count 2 2006.176.07:53:39.09#ibcon#read 3, iclass 3, count 2 2006.176.07:53:39.09#ibcon#about to read 4, iclass 3, count 2 2006.176.07:53:39.09#ibcon#read 4, iclass 3, count 2 2006.176.07:53:39.09#ibcon#about to read 5, iclass 3, count 2 2006.176.07:53:39.09#ibcon#read 5, iclass 3, count 2 2006.176.07:53:39.09#ibcon#about to read 6, iclass 3, count 2 2006.176.07:53:39.09#ibcon#read 6, iclass 3, count 2 2006.176.07:53:39.09#ibcon#end of sib2, iclass 3, count 2 2006.176.07:53:39.09#ibcon#*mode == 0, iclass 3, count 2 2006.176.07:53:39.09#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.07:53:39.09#ibcon#[25=AT04-07\r\n] 2006.176.07:53:39.09#ibcon#*before write, iclass 3, count 2 2006.176.07:53:39.09#ibcon#enter sib2, iclass 3, count 2 2006.176.07:53:39.09#ibcon#flushed, iclass 3, count 2 2006.176.07:53:39.09#ibcon#about to write, iclass 3, count 2 2006.176.07:53:39.10#ibcon#wrote, iclass 3, count 2 2006.176.07:53:39.10#ibcon#about to read 3, iclass 3, count 2 2006.176.07:53:39.12#ibcon#read 3, iclass 3, count 2 2006.176.07:53:39.12#ibcon#about to read 4, iclass 3, count 2 2006.176.07:53:39.12#ibcon#read 4, iclass 3, count 2 2006.176.07:53:39.12#ibcon#about to read 5, iclass 3, count 2 2006.176.07:53:39.12#ibcon#read 5, iclass 3, count 2 2006.176.07:53:39.12#ibcon#about to read 6, iclass 3, count 2 2006.176.07:53:39.12#ibcon#read 6, iclass 3, count 2 2006.176.07:53:39.12#ibcon#end of sib2, iclass 3, count 2 2006.176.07:53:39.12#ibcon#*after write, iclass 3, count 2 2006.176.07:53:39.12#ibcon#*before return 0, iclass 3, count 2 2006.176.07:53:39.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:39.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:39.12#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.07:53:39.12#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:39.13#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:39.23#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:39.23#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:39.23#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:53:39.23#ibcon#first serial, iclass 3, count 0 2006.176.07:53:39.23#ibcon#enter sib2, iclass 3, count 0 2006.176.07:53:39.23#ibcon#flushed, iclass 3, count 0 2006.176.07:53:39.23#ibcon#about to write, iclass 3, count 0 2006.176.07:53:39.23#ibcon#wrote, iclass 3, count 0 2006.176.07:53:39.23#ibcon#about to read 3, iclass 3, count 0 2006.176.07:53:39.25#ibcon#read 3, iclass 3, count 0 2006.176.07:53:39.25#ibcon#about to read 4, iclass 3, count 0 2006.176.07:53:39.25#ibcon#read 4, iclass 3, count 0 2006.176.07:53:39.25#ibcon#about to read 5, iclass 3, count 0 2006.176.07:53:39.25#ibcon#read 5, iclass 3, count 0 2006.176.07:53:39.25#ibcon#about to read 6, iclass 3, count 0 2006.176.07:53:39.25#ibcon#read 6, iclass 3, count 0 2006.176.07:53:39.25#ibcon#end of sib2, iclass 3, count 0 2006.176.07:53:39.25#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:53:39.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:53:39.25#ibcon#[25=USB\r\n] 2006.176.07:53:39.25#ibcon#*before write, iclass 3, count 0 2006.176.07:53:39.25#ibcon#enter sib2, iclass 3, count 0 2006.176.07:53:39.25#ibcon#flushed, iclass 3, count 0 2006.176.07:53:39.25#ibcon#about to write, iclass 3, count 0 2006.176.07:53:39.26#ibcon#wrote, iclass 3, count 0 2006.176.07:53:39.26#ibcon#about to read 3, iclass 3, count 0 2006.176.07:53:39.28#ibcon#read 3, iclass 3, count 0 2006.176.07:53:39.28#ibcon#about to read 4, iclass 3, count 0 2006.176.07:53:39.28#ibcon#read 4, iclass 3, count 0 2006.176.07:53:39.28#ibcon#about to read 5, iclass 3, count 0 2006.176.07:53:39.28#ibcon#read 5, iclass 3, count 0 2006.176.07:53:39.28#ibcon#about to read 6, iclass 3, count 0 2006.176.07:53:39.28#ibcon#read 6, iclass 3, count 0 2006.176.07:53:39.28#ibcon#end of sib2, iclass 3, count 0 2006.176.07:53:39.28#ibcon#*after write, iclass 3, count 0 2006.176.07:53:39.28#ibcon#*before return 0, iclass 3, count 0 2006.176.07:53:39.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:39.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:39.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:53:39.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:53:39.29$vc4f8/valo=5,652.99 2006.176.07:53:39.29#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.07:53:39.29#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.07:53:39.29#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:39.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:39.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:39.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:39.29#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:53:39.29#ibcon#first serial, iclass 5, count 0 2006.176.07:53:39.29#ibcon#enter sib2, iclass 5, count 0 2006.176.07:53:39.29#ibcon#flushed, iclass 5, count 0 2006.176.07:53:39.29#ibcon#about to write, iclass 5, count 0 2006.176.07:53:39.29#ibcon#wrote, iclass 5, count 0 2006.176.07:53:39.29#ibcon#about to read 3, iclass 5, count 0 2006.176.07:53:39.30#ibcon#read 3, iclass 5, count 0 2006.176.07:53:39.30#ibcon#about to read 4, iclass 5, count 0 2006.176.07:53:39.30#ibcon#read 4, iclass 5, count 0 2006.176.07:53:39.30#ibcon#about to read 5, iclass 5, count 0 2006.176.07:53:39.30#ibcon#read 5, iclass 5, count 0 2006.176.07:53:39.30#ibcon#about to read 6, iclass 5, count 0 2006.176.07:53:39.30#ibcon#read 6, iclass 5, count 0 2006.176.07:53:39.30#ibcon#end of sib2, iclass 5, count 0 2006.176.07:53:39.30#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:53:39.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:53:39.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:53:39.30#ibcon#*before write, iclass 5, count 0 2006.176.07:53:39.30#ibcon#enter sib2, iclass 5, count 0 2006.176.07:53:39.30#ibcon#flushed, iclass 5, count 0 2006.176.07:53:39.30#ibcon#about to write, iclass 5, count 0 2006.176.07:53:39.31#ibcon#wrote, iclass 5, count 0 2006.176.07:53:39.31#ibcon#about to read 3, iclass 5, count 0 2006.176.07:53:39.34#ibcon#read 3, iclass 5, count 0 2006.176.07:53:39.34#ibcon#about to read 4, iclass 5, count 0 2006.176.07:53:39.34#ibcon#read 4, iclass 5, count 0 2006.176.07:53:39.34#ibcon#about to read 5, iclass 5, count 0 2006.176.07:53:39.34#ibcon#read 5, iclass 5, count 0 2006.176.07:53:39.34#ibcon#about to read 6, iclass 5, count 0 2006.176.07:53:39.34#ibcon#read 6, iclass 5, count 0 2006.176.07:53:39.34#ibcon#end of sib2, iclass 5, count 0 2006.176.07:53:39.34#ibcon#*after write, iclass 5, count 0 2006.176.07:53:39.34#ibcon#*before return 0, iclass 5, count 0 2006.176.07:53:39.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:39.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:39.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:53:39.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:53:39.35$vc4f8/va=5,7 2006.176.07:53:39.35#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.07:53:39.35#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.07:53:39.35#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:39.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:39.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:39.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:39.39#ibcon#enter wrdev, iclass 7, count 2 2006.176.07:53:39.39#ibcon#first serial, iclass 7, count 2 2006.176.07:53:39.39#ibcon#enter sib2, iclass 7, count 2 2006.176.07:53:39.39#ibcon#flushed, iclass 7, count 2 2006.176.07:53:39.39#ibcon#about to write, iclass 7, count 2 2006.176.07:53:39.39#ibcon#wrote, iclass 7, count 2 2006.176.07:53:39.39#ibcon#about to read 3, iclass 7, count 2 2006.176.07:53:39.41#ibcon#read 3, iclass 7, count 2 2006.176.07:53:39.41#ibcon#about to read 4, iclass 7, count 2 2006.176.07:53:39.41#ibcon#read 4, iclass 7, count 2 2006.176.07:53:39.41#ibcon#about to read 5, iclass 7, count 2 2006.176.07:53:39.41#ibcon#read 5, iclass 7, count 2 2006.176.07:53:39.41#ibcon#about to read 6, iclass 7, count 2 2006.176.07:53:39.41#ibcon#read 6, iclass 7, count 2 2006.176.07:53:39.41#ibcon#end of sib2, iclass 7, count 2 2006.176.07:53:39.41#ibcon#*mode == 0, iclass 7, count 2 2006.176.07:53:39.41#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.07:53:39.41#ibcon#[25=AT05-07\r\n] 2006.176.07:53:39.41#ibcon#*before write, iclass 7, count 2 2006.176.07:53:39.41#ibcon#enter sib2, iclass 7, count 2 2006.176.07:53:39.41#ibcon#flushed, iclass 7, count 2 2006.176.07:53:39.41#ibcon#about to write, iclass 7, count 2 2006.176.07:53:39.42#ibcon#wrote, iclass 7, count 2 2006.176.07:53:39.42#ibcon#about to read 3, iclass 7, count 2 2006.176.07:53:39.44#ibcon#read 3, iclass 7, count 2 2006.176.07:53:39.44#ibcon#about to read 4, iclass 7, count 2 2006.176.07:53:39.44#ibcon#read 4, iclass 7, count 2 2006.176.07:53:39.44#ibcon#about to read 5, iclass 7, count 2 2006.176.07:53:39.44#ibcon#read 5, iclass 7, count 2 2006.176.07:53:39.44#ibcon#about to read 6, iclass 7, count 2 2006.176.07:53:39.44#ibcon#read 6, iclass 7, count 2 2006.176.07:53:39.44#ibcon#end of sib2, iclass 7, count 2 2006.176.07:53:39.44#ibcon#*after write, iclass 7, count 2 2006.176.07:53:39.44#ibcon#*before return 0, iclass 7, count 2 2006.176.07:53:39.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:39.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:39.44#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.07:53:39.44#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:39.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:39.56#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:39.56#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:39.56#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:53:39.56#ibcon#first serial, iclass 7, count 0 2006.176.07:53:39.56#ibcon#enter sib2, iclass 7, count 0 2006.176.07:53:39.56#ibcon#flushed, iclass 7, count 0 2006.176.07:53:39.56#ibcon#about to write, iclass 7, count 0 2006.176.07:53:39.56#ibcon#wrote, iclass 7, count 0 2006.176.07:53:39.56#ibcon#about to read 3, iclass 7, count 0 2006.176.07:53:39.58#ibcon#read 3, iclass 7, count 0 2006.176.07:53:39.58#ibcon#about to read 4, iclass 7, count 0 2006.176.07:53:39.58#ibcon#read 4, iclass 7, count 0 2006.176.07:53:39.58#ibcon#about to read 5, iclass 7, count 0 2006.176.07:53:39.58#ibcon#read 5, iclass 7, count 0 2006.176.07:53:39.58#ibcon#about to read 6, iclass 7, count 0 2006.176.07:53:39.58#ibcon#read 6, iclass 7, count 0 2006.176.07:53:39.58#ibcon#end of sib2, iclass 7, count 0 2006.176.07:53:39.58#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:53:39.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:53:39.58#ibcon#[25=USB\r\n] 2006.176.07:53:39.58#ibcon#*before write, iclass 7, count 0 2006.176.07:53:39.58#ibcon#enter sib2, iclass 7, count 0 2006.176.07:53:39.58#ibcon#flushed, iclass 7, count 0 2006.176.07:53:39.58#ibcon#about to write, iclass 7, count 0 2006.176.07:53:39.59#ibcon#wrote, iclass 7, count 0 2006.176.07:53:39.59#ibcon#about to read 3, iclass 7, count 0 2006.176.07:53:39.61#ibcon#read 3, iclass 7, count 0 2006.176.07:53:39.61#ibcon#about to read 4, iclass 7, count 0 2006.176.07:53:39.61#ibcon#read 4, iclass 7, count 0 2006.176.07:53:39.61#ibcon#about to read 5, iclass 7, count 0 2006.176.07:53:39.61#ibcon#read 5, iclass 7, count 0 2006.176.07:53:39.61#ibcon#about to read 6, iclass 7, count 0 2006.176.07:53:39.61#ibcon#read 6, iclass 7, count 0 2006.176.07:53:39.61#ibcon#end of sib2, iclass 7, count 0 2006.176.07:53:39.61#ibcon#*after write, iclass 7, count 0 2006.176.07:53:39.61#ibcon#*before return 0, iclass 7, count 0 2006.176.07:53:39.61#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:39.61#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:39.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:53:39.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:53:39.62$vc4f8/valo=6,772.99 2006.176.07:53:39.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.07:53:39.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.07:53:39.62#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:39.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:39.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:39.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:39.62#ibcon#enter wrdev, iclass 11, count 0 2006.176.07:53:39.62#ibcon#first serial, iclass 11, count 0 2006.176.07:53:39.62#ibcon#enter sib2, iclass 11, count 0 2006.176.07:53:39.62#ibcon#flushed, iclass 11, count 0 2006.176.07:53:39.62#ibcon#about to write, iclass 11, count 0 2006.176.07:53:39.62#ibcon#wrote, iclass 11, count 0 2006.176.07:53:39.62#ibcon#about to read 3, iclass 11, count 0 2006.176.07:53:39.64#ibcon#read 3, iclass 11, count 0 2006.176.07:53:39.64#ibcon#about to read 4, iclass 11, count 0 2006.176.07:53:39.64#ibcon#read 4, iclass 11, count 0 2006.176.07:53:39.64#ibcon#about to read 5, iclass 11, count 0 2006.176.07:53:39.64#ibcon#read 5, iclass 11, count 0 2006.176.07:53:39.64#ibcon#about to read 6, iclass 11, count 0 2006.176.07:53:39.64#ibcon#read 6, iclass 11, count 0 2006.176.07:53:39.64#ibcon#end of sib2, iclass 11, count 0 2006.176.07:53:39.64#ibcon#*mode == 0, iclass 11, count 0 2006.176.07:53:39.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.07:53:39.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:53:39.64#ibcon#*before write, iclass 11, count 0 2006.176.07:53:39.64#ibcon#enter sib2, iclass 11, count 0 2006.176.07:53:39.64#ibcon#flushed, iclass 11, count 0 2006.176.07:53:39.64#ibcon#about to write, iclass 11, count 0 2006.176.07:53:39.64#ibcon#wrote, iclass 11, count 0 2006.176.07:53:39.64#ibcon#about to read 3, iclass 11, count 0 2006.176.07:53:39.67#ibcon#read 3, iclass 11, count 0 2006.176.07:53:39.67#ibcon#about to read 4, iclass 11, count 0 2006.176.07:53:39.67#ibcon#read 4, iclass 11, count 0 2006.176.07:53:39.67#ibcon#about to read 5, iclass 11, count 0 2006.176.07:53:39.67#ibcon#read 5, iclass 11, count 0 2006.176.07:53:39.67#ibcon#about to read 6, iclass 11, count 0 2006.176.07:53:39.67#ibcon#read 6, iclass 11, count 0 2006.176.07:53:39.67#ibcon#end of sib2, iclass 11, count 0 2006.176.07:53:39.67#ibcon#*after write, iclass 11, count 0 2006.176.07:53:39.67#ibcon#*before return 0, iclass 11, count 0 2006.176.07:53:39.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:39.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:39.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.07:53:39.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.07:53:39.68$vc4f8/va=6,6 2006.176.07:53:39.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.07:53:39.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.07:53:39.68#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:39.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:53:39.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:53:39.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:53:39.73#ibcon#enter wrdev, iclass 13, count 2 2006.176.07:53:39.73#ibcon#first serial, iclass 13, count 2 2006.176.07:53:39.73#ibcon#enter sib2, iclass 13, count 2 2006.176.07:53:39.73#ibcon#flushed, iclass 13, count 2 2006.176.07:53:39.73#ibcon#about to write, iclass 13, count 2 2006.176.07:53:39.73#ibcon#wrote, iclass 13, count 2 2006.176.07:53:39.73#ibcon#about to read 3, iclass 13, count 2 2006.176.07:53:39.74#ibcon#read 3, iclass 13, count 2 2006.176.07:53:39.74#ibcon#about to read 4, iclass 13, count 2 2006.176.07:53:39.74#ibcon#read 4, iclass 13, count 2 2006.176.07:53:39.74#ibcon#about to read 5, iclass 13, count 2 2006.176.07:53:39.74#ibcon#read 5, iclass 13, count 2 2006.176.07:53:39.74#ibcon#about to read 6, iclass 13, count 2 2006.176.07:53:39.74#ibcon#read 6, iclass 13, count 2 2006.176.07:53:39.74#ibcon#end of sib2, iclass 13, count 2 2006.176.07:53:39.74#ibcon#*mode == 0, iclass 13, count 2 2006.176.07:53:39.74#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.07:53:39.74#ibcon#[25=AT06-06\r\n] 2006.176.07:53:39.74#ibcon#*before write, iclass 13, count 2 2006.176.07:53:39.74#ibcon#enter sib2, iclass 13, count 2 2006.176.07:53:39.74#ibcon#flushed, iclass 13, count 2 2006.176.07:53:39.74#ibcon#about to write, iclass 13, count 2 2006.176.07:53:39.75#ibcon#wrote, iclass 13, count 2 2006.176.07:53:39.75#ibcon#about to read 3, iclass 13, count 2 2006.176.07:53:39.77#ibcon#read 3, iclass 13, count 2 2006.176.07:53:39.77#ibcon#about to read 4, iclass 13, count 2 2006.176.07:53:39.77#ibcon#read 4, iclass 13, count 2 2006.176.07:53:39.77#ibcon#about to read 5, iclass 13, count 2 2006.176.07:53:39.77#ibcon#read 5, iclass 13, count 2 2006.176.07:53:39.77#ibcon#about to read 6, iclass 13, count 2 2006.176.07:53:39.77#ibcon#read 6, iclass 13, count 2 2006.176.07:53:39.77#ibcon#end of sib2, iclass 13, count 2 2006.176.07:53:39.77#ibcon#*after write, iclass 13, count 2 2006.176.07:53:39.77#ibcon#*before return 0, iclass 13, count 2 2006.176.07:53:39.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:53:39.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.07:53:39.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.07:53:39.77#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:39.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:53:39.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:53:39.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:53:39.89#ibcon#enter wrdev, iclass 13, count 0 2006.176.07:53:39.89#ibcon#first serial, iclass 13, count 0 2006.176.07:53:39.89#ibcon#enter sib2, iclass 13, count 0 2006.176.07:53:39.89#ibcon#flushed, iclass 13, count 0 2006.176.07:53:39.89#ibcon#about to write, iclass 13, count 0 2006.176.07:53:39.89#ibcon#wrote, iclass 13, count 0 2006.176.07:53:39.89#ibcon#about to read 3, iclass 13, count 0 2006.176.07:53:39.91#ibcon#read 3, iclass 13, count 0 2006.176.07:53:39.91#ibcon#about to read 4, iclass 13, count 0 2006.176.07:53:39.91#ibcon#read 4, iclass 13, count 0 2006.176.07:53:39.91#ibcon#about to read 5, iclass 13, count 0 2006.176.07:53:39.91#ibcon#read 5, iclass 13, count 0 2006.176.07:53:39.91#ibcon#about to read 6, iclass 13, count 0 2006.176.07:53:39.91#ibcon#read 6, iclass 13, count 0 2006.176.07:53:39.91#ibcon#end of sib2, iclass 13, count 0 2006.176.07:53:39.91#ibcon#*mode == 0, iclass 13, count 0 2006.176.07:53:39.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.07:53:39.91#ibcon#[25=USB\r\n] 2006.176.07:53:39.91#ibcon#*before write, iclass 13, count 0 2006.176.07:53:39.91#ibcon#enter sib2, iclass 13, count 0 2006.176.07:53:39.91#ibcon#flushed, iclass 13, count 0 2006.176.07:53:39.91#ibcon#about to write, iclass 13, count 0 2006.176.07:53:39.92#ibcon#wrote, iclass 13, count 0 2006.176.07:53:39.92#ibcon#about to read 3, iclass 13, count 0 2006.176.07:53:39.94#ibcon#read 3, iclass 13, count 0 2006.176.07:53:39.94#ibcon#about to read 4, iclass 13, count 0 2006.176.07:53:39.94#ibcon#read 4, iclass 13, count 0 2006.176.07:53:39.94#ibcon#about to read 5, iclass 13, count 0 2006.176.07:53:39.94#ibcon#read 5, iclass 13, count 0 2006.176.07:53:39.94#ibcon#about to read 6, iclass 13, count 0 2006.176.07:53:39.94#ibcon#read 6, iclass 13, count 0 2006.176.07:53:39.94#ibcon#end of sib2, iclass 13, count 0 2006.176.07:53:39.94#ibcon#*after write, iclass 13, count 0 2006.176.07:53:39.94#ibcon#*before return 0, iclass 13, count 0 2006.176.07:53:39.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:53:39.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.07:53:39.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.07:53:39.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.07:53:39.95$vc4f8/valo=7,832.99 2006.176.07:53:39.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.07:53:39.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.07:53:39.95#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:39.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:53:39.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:53:39.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:53:39.95#ibcon#enter wrdev, iclass 15, count 0 2006.176.07:53:39.95#ibcon#first serial, iclass 15, count 0 2006.176.07:53:39.95#ibcon#enter sib2, iclass 15, count 0 2006.176.07:53:39.95#ibcon#flushed, iclass 15, count 0 2006.176.07:53:39.95#ibcon#about to write, iclass 15, count 0 2006.176.07:53:39.95#ibcon#wrote, iclass 15, count 0 2006.176.07:53:39.95#ibcon#about to read 3, iclass 15, count 0 2006.176.07:53:39.96#ibcon#read 3, iclass 15, count 0 2006.176.07:53:39.96#ibcon#about to read 4, iclass 15, count 0 2006.176.07:53:39.96#ibcon#read 4, iclass 15, count 0 2006.176.07:53:39.96#ibcon#about to read 5, iclass 15, count 0 2006.176.07:53:39.96#ibcon#read 5, iclass 15, count 0 2006.176.07:53:39.96#ibcon#about to read 6, iclass 15, count 0 2006.176.07:53:39.96#ibcon#read 6, iclass 15, count 0 2006.176.07:53:39.96#ibcon#end of sib2, iclass 15, count 0 2006.176.07:53:39.96#ibcon#*mode == 0, iclass 15, count 0 2006.176.07:53:39.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.07:53:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:53:39.96#ibcon#*before write, iclass 15, count 0 2006.176.07:53:39.96#ibcon#enter sib2, iclass 15, count 0 2006.176.07:53:39.96#ibcon#flushed, iclass 15, count 0 2006.176.07:53:39.96#ibcon#about to write, iclass 15, count 0 2006.176.07:53:39.97#ibcon#wrote, iclass 15, count 0 2006.176.07:53:39.97#ibcon#about to read 3, iclass 15, count 0 2006.176.07:53:40.00#ibcon#read 3, iclass 15, count 0 2006.176.07:53:40.00#ibcon#about to read 4, iclass 15, count 0 2006.176.07:53:40.00#ibcon#read 4, iclass 15, count 0 2006.176.07:53:40.00#ibcon#about to read 5, iclass 15, count 0 2006.176.07:53:40.00#ibcon#read 5, iclass 15, count 0 2006.176.07:53:40.00#ibcon#about to read 6, iclass 15, count 0 2006.176.07:53:40.00#ibcon#read 6, iclass 15, count 0 2006.176.07:53:40.00#ibcon#end of sib2, iclass 15, count 0 2006.176.07:53:40.00#ibcon#*after write, iclass 15, count 0 2006.176.07:53:40.00#ibcon#*before return 0, iclass 15, count 0 2006.176.07:53:40.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:53:40.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.07:53:40.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.07:53:40.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.07:53:40.01$vc4f8/va=7,6 2006.176.07:53:40.01#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.176.07:53:40.01#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.176.07:53:40.01#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:40.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:53:40.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:53:40.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:53:40.05#ibcon#enter wrdev, iclass 17, count 2 2006.176.07:53:40.05#ibcon#first serial, iclass 17, count 2 2006.176.07:53:40.05#ibcon#enter sib2, iclass 17, count 2 2006.176.07:53:40.05#ibcon#flushed, iclass 17, count 2 2006.176.07:53:40.05#ibcon#about to write, iclass 17, count 2 2006.176.07:53:40.05#ibcon#wrote, iclass 17, count 2 2006.176.07:53:40.05#ibcon#about to read 3, iclass 17, count 2 2006.176.07:53:40.07#ibcon#read 3, iclass 17, count 2 2006.176.07:53:40.07#ibcon#about to read 4, iclass 17, count 2 2006.176.07:53:40.07#ibcon#read 4, iclass 17, count 2 2006.176.07:53:40.07#ibcon#about to read 5, iclass 17, count 2 2006.176.07:53:40.07#ibcon#read 5, iclass 17, count 2 2006.176.07:53:40.07#ibcon#about to read 6, iclass 17, count 2 2006.176.07:53:40.07#ibcon#read 6, iclass 17, count 2 2006.176.07:53:40.07#ibcon#end of sib2, iclass 17, count 2 2006.176.07:53:40.07#ibcon#*mode == 0, iclass 17, count 2 2006.176.07:53:40.07#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.176.07:53:40.07#ibcon#[25=AT07-06\r\n] 2006.176.07:53:40.07#ibcon#*before write, iclass 17, count 2 2006.176.07:53:40.07#ibcon#enter sib2, iclass 17, count 2 2006.176.07:53:40.07#ibcon#flushed, iclass 17, count 2 2006.176.07:53:40.07#ibcon#about to write, iclass 17, count 2 2006.176.07:53:40.08#ibcon#wrote, iclass 17, count 2 2006.176.07:53:40.08#ibcon#about to read 3, iclass 17, count 2 2006.176.07:53:40.10#ibcon#read 3, iclass 17, count 2 2006.176.07:53:40.10#ibcon#about to read 4, iclass 17, count 2 2006.176.07:53:40.10#ibcon#read 4, iclass 17, count 2 2006.176.07:53:40.10#ibcon#about to read 5, iclass 17, count 2 2006.176.07:53:40.10#ibcon#read 5, iclass 17, count 2 2006.176.07:53:40.10#ibcon#about to read 6, iclass 17, count 2 2006.176.07:53:40.10#ibcon#read 6, iclass 17, count 2 2006.176.07:53:40.10#ibcon#end of sib2, iclass 17, count 2 2006.176.07:53:40.10#ibcon#*after write, iclass 17, count 2 2006.176.07:53:40.10#ibcon#*before return 0, iclass 17, count 2 2006.176.07:53:40.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:53:40.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.176.07:53:40.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.176.07:53:40.10#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:40.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:53:40.22#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:53:40.22#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:53:40.22#ibcon#enter wrdev, iclass 17, count 0 2006.176.07:53:40.22#ibcon#first serial, iclass 17, count 0 2006.176.07:53:40.22#ibcon#enter sib2, iclass 17, count 0 2006.176.07:53:40.22#ibcon#flushed, iclass 17, count 0 2006.176.07:53:40.22#ibcon#about to write, iclass 17, count 0 2006.176.07:53:40.22#ibcon#wrote, iclass 17, count 0 2006.176.07:53:40.22#ibcon#about to read 3, iclass 17, count 0 2006.176.07:53:40.24#ibcon#read 3, iclass 17, count 0 2006.176.07:53:40.24#ibcon#about to read 4, iclass 17, count 0 2006.176.07:53:40.24#ibcon#read 4, iclass 17, count 0 2006.176.07:53:40.24#ibcon#about to read 5, iclass 17, count 0 2006.176.07:53:40.24#ibcon#read 5, iclass 17, count 0 2006.176.07:53:40.24#ibcon#about to read 6, iclass 17, count 0 2006.176.07:53:40.24#ibcon#read 6, iclass 17, count 0 2006.176.07:53:40.24#ibcon#end of sib2, iclass 17, count 0 2006.176.07:53:40.24#ibcon#*mode == 0, iclass 17, count 0 2006.176.07:53:40.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.07:53:40.24#ibcon#[25=USB\r\n] 2006.176.07:53:40.24#ibcon#*before write, iclass 17, count 0 2006.176.07:53:40.24#ibcon#enter sib2, iclass 17, count 0 2006.176.07:53:40.24#ibcon#flushed, iclass 17, count 0 2006.176.07:53:40.24#ibcon#about to write, iclass 17, count 0 2006.176.07:53:40.25#ibcon#wrote, iclass 17, count 0 2006.176.07:53:40.25#ibcon#about to read 3, iclass 17, count 0 2006.176.07:53:40.27#ibcon#read 3, iclass 17, count 0 2006.176.07:53:40.27#ibcon#about to read 4, iclass 17, count 0 2006.176.07:53:40.27#ibcon#read 4, iclass 17, count 0 2006.176.07:53:40.27#ibcon#about to read 5, iclass 17, count 0 2006.176.07:53:40.27#ibcon#read 5, iclass 17, count 0 2006.176.07:53:40.27#ibcon#about to read 6, iclass 17, count 0 2006.176.07:53:40.27#ibcon#read 6, iclass 17, count 0 2006.176.07:53:40.27#ibcon#end of sib2, iclass 17, count 0 2006.176.07:53:40.27#ibcon#*after write, iclass 17, count 0 2006.176.07:53:40.27#ibcon#*before return 0, iclass 17, count 0 2006.176.07:53:40.27#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:53:40.27#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.176.07:53:40.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.07:53:40.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.07:53:40.28$vc4f8/valo=8,852.99 2006.176.07:53:40.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.176.07:53:40.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.176.07:53:40.28#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:40.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:53:40.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:53:40.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:53:40.28#ibcon#enter wrdev, iclass 19, count 0 2006.176.07:53:40.28#ibcon#first serial, iclass 19, count 0 2006.176.07:53:40.28#ibcon#enter sib2, iclass 19, count 0 2006.176.07:53:40.28#ibcon#flushed, iclass 19, count 0 2006.176.07:53:40.28#ibcon#about to write, iclass 19, count 0 2006.176.07:53:40.28#ibcon#wrote, iclass 19, count 0 2006.176.07:53:40.28#ibcon#about to read 3, iclass 19, count 0 2006.176.07:53:40.29#ibcon#read 3, iclass 19, count 0 2006.176.07:53:40.29#ibcon#about to read 4, iclass 19, count 0 2006.176.07:53:40.29#ibcon#read 4, iclass 19, count 0 2006.176.07:53:40.29#ibcon#about to read 5, iclass 19, count 0 2006.176.07:53:40.29#ibcon#read 5, iclass 19, count 0 2006.176.07:53:40.29#ibcon#about to read 6, iclass 19, count 0 2006.176.07:53:40.29#ibcon#read 6, iclass 19, count 0 2006.176.07:53:40.29#ibcon#end of sib2, iclass 19, count 0 2006.176.07:53:40.29#ibcon#*mode == 0, iclass 19, count 0 2006.176.07:53:40.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.07:53:40.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:53:40.29#ibcon#*before write, iclass 19, count 0 2006.176.07:53:40.29#ibcon#enter sib2, iclass 19, count 0 2006.176.07:53:40.29#ibcon#flushed, iclass 19, count 0 2006.176.07:53:40.29#ibcon#about to write, iclass 19, count 0 2006.176.07:53:40.30#ibcon#wrote, iclass 19, count 0 2006.176.07:53:40.30#ibcon#about to read 3, iclass 19, count 0 2006.176.07:53:40.33#ibcon#read 3, iclass 19, count 0 2006.176.07:53:40.33#ibcon#about to read 4, iclass 19, count 0 2006.176.07:53:40.33#ibcon#read 4, iclass 19, count 0 2006.176.07:53:40.33#ibcon#about to read 5, iclass 19, count 0 2006.176.07:53:40.33#ibcon#read 5, iclass 19, count 0 2006.176.07:53:40.33#ibcon#about to read 6, iclass 19, count 0 2006.176.07:53:40.33#ibcon#read 6, iclass 19, count 0 2006.176.07:53:40.33#ibcon#end of sib2, iclass 19, count 0 2006.176.07:53:40.33#ibcon#*after write, iclass 19, count 0 2006.176.07:53:40.33#ibcon#*before return 0, iclass 19, count 0 2006.176.07:53:40.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:53:40.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.176.07:53:40.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.07:53:40.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.07:53:40.34$vc4f8/va=8,6 2006.176.07:53:40.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.176.07:53:40.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.176.07:53:40.34#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:40.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:53:40.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:53:40.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:53:40.39#ibcon#enter wrdev, iclass 21, count 2 2006.176.07:53:40.39#ibcon#first serial, iclass 21, count 2 2006.176.07:53:40.39#ibcon#enter sib2, iclass 21, count 2 2006.176.07:53:40.39#ibcon#flushed, iclass 21, count 2 2006.176.07:53:40.39#ibcon#about to write, iclass 21, count 2 2006.176.07:53:40.39#ibcon#wrote, iclass 21, count 2 2006.176.07:53:40.39#ibcon#about to read 3, iclass 21, count 2 2006.176.07:53:40.41#ibcon#read 3, iclass 21, count 2 2006.176.07:53:40.41#ibcon#about to read 4, iclass 21, count 2 2006.176.07:53:40.41#ibcon#read 4, iclass 21, count 2 2006.176.07:53:40.41#ibcon#about to read 5, iclass 21, count 2 2006.176.07:53:40.41#ibcon#read 5, iclass 21, count 2 2006.176.07:53:40.41#ibcon#about to read 6, iclass 21, count 2 2006.176.07:53:40.41#ibcon#read 6, iclass 21, count 2 2006.176.07:53:40.41#ibcon#end of sib2, iclass 21, count 2 2006.176.07:53:40.41#ibcon#*mode == 0, iclass 21, count 2 2006.176.07:53:40.41#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.176.07:53:40.41#ibcon#[25=AT08-06\r\n] 2006.176.07:53:40.41#ibcon#*before write, iclass 21, count 2 2006.176.07:53:40.41#ibcon#enter sib2, iclass 21, count 2 2006.176.07:53:40.41#ibcon#flushed, iclass 21, count 2 2006.176.07:53:40.41#ibcon#about to write, iclass 21, count 2 2006.176.07:53:40.41#ibcon#wrote, iclass 21, count 2 2006.176.07:53:40.41#ibcon#about to read 3, iclass 21, count 2 2006.176.07:53:40.43#ibcon#read 3, iclass 21, count 2 2006.176.07:53:40.43#ibcon#about to read 4, iclass 21, count 2 2006.176.07:53:40.43#ibcon#read 4, iclass 21, count 2 2006.176.07:53:40.43#ibcon#about to read 5, iclass 21, count 2 2006.176.07:53:40.43#ibcon#read 5, iclass 21, count 2 2006.176.07:53:40.43#ibcon#about to read 6, iclass 21, count 2 2006.176.07:53:40.43#ibcon#read 6, iclass 21, count 2 2006.176.07:53:40.43#ibcon#end of sib2, iclass 21, count 2 2006.176.07:53:40.43#ibcon#*after write, iclass 21, count 2 2006.176.07:53:40.43#ibcon#*before return 0, iclass 21, count 2 2006.176.07:53:40.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:53:40.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.176.07:53:40.44#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.176.07:53:40.44#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:40.44#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:53:40.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:53:40.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:53:40.54#ibcon#enter wrdev, iclass 21, count 0 2006.176.07:53:40.54#ibcon#first serial, iclass 21, count 0 2006.176.07:53:40.54#ibcon#enter sib2, iclass 21, count 0 2006.176.07:53:40.54#ibcon#flushed, iclass 21, count 0 2006.176.07:53:40.54#ibcon#about to write, iclass 21, count 0 2006.176.07:53:40.54#ibcon#wrote, iclass 21, count 0 2006.176.07:53:40.54#ibcon#about to read 3, iclass 21, count 0 2006.176.07:53:40.56#ibcon#read 3, iclass 21, count 0 2006.176.07:53:40.56#ibcon#about to read 4, iclass 21, count 0 2006.176.07:53:40.56#ibcon#read 4, iclass 21, count 0 2006.176.07:53:40.56#ibcon#about to read 5, iclass 21, count 0 2006.176.07:53:40.56#ibcon#read 5, iclass 21, count 0 2006.176.07:53:40.56#ibcon#about to read 6, iclass 21, count 0 2006.176.07:53:40.56#ibcon#read 6, iclass 21, count 0 2006.176.07:53:40.56#ibcon#end of sib2, iclass 21, count 0 2006.176.07:53:40.56#ibcon#*mode == 0, iclass 21, count 0 2006.176.07:53:40.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.07:53:40.56#ibcon#[25=USB\r\n] 2006.176.07:53:40.56#ibcon#*before write, iclass 21, count 0 2006.176.07:53:40.56#ibcon#enter sib2, iclass 21, count 0 2006.176.07:53:40.56#ibcon#flushed, iclass 21, count 0 2006.176.07:53:40.56#ibcon#about to write, iclass 21, count 0 2006.176.07:53:40.57#ibcon#wrote, iclass 21, count 0 2006.176.07:53:40.57#ibcon#about to read 3, iclass 21, count 0 2006.176.07:53:40.59#ibcon#read 3, iclass 21, count 0 2006.176.07:53:40.59#ibcon#about to read 4, iclass 21, count 0 2006.176.07:53:40.59#ibcon#read 4, iclass 21, count 0 2006.176.07:53:40.59#ibcon#about to read 5, iclass 21, count 0 2006.176.07:53:40.59#ibcon#read 5, iclass 21, count 0 2006.176.07:53:40.59#ibcon#about to read 6, iclass 21, count 0 2006.176.07:53:40.59#ibcon#read 6, iclass 21, count 0 2006.176.07:53:40.59#ibcon#end of sib2, iclass 21, count 0 2006.176.07:53:40.59#ibcon#*after write, iclass 21, count 0 2006.176.07:53:40.59#ibcon#*before return 0, iclass 21, count 0 2006.176.07:53:40.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:53:40.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.176.07:53:40.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.07:53:40.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.07:53:40.60$vc4f8/vblo=1,632.99 2006.176.07:53:40.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.07:53:40.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.07:53:40.60#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:40.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:53:40.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:53:40.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:53:40.60#ibcon#enter wrdev, iclass 23, count 0 2006.176.07:53:40.60#ibcon#first serial, iclass 23, count 0 2006.176.07:53:40.60#ibcon#enter sib2, iclass 23, count 0 2006.176.07:53:40.60#ibcon#flushed, iclass 23, count 0 2006.176.07:53:40.60#ibcon#about to write, iclass 23, count 0 2006.176.07:53:40.60#ibcon#wrote, iclass 23, count 0 2006.176.07:53:40.60#ibcon#about to read 3, iclass 23, count 0 2006.176.07:53:40.61#ibcon#read 3, iclass 23, count 0 2006.176.07:53:40.61#ibcon#about to read 4, iclass 23, count 0 2006.176.07:53:40.61#ibcon#read 4, iclass 23, count 0 2006.176.07:53:40.61#ibcon#about to read 5, iclass 23, count 0 2006.176.07:53:40.61#ibcon#read 5, iclass 23, count 0 2006.176.07:53:40.61#ibcon#about to read 6, iclass 23, count 0 2006.176.07:53:40.61#ibcon#read 6, iclass 23, count 0 2006.176.07:53:40.61#ibcon#end of sib2, iclass 23, count 0 2006.176.07:53:40.61#ibcon#*mode == 0, iclass 23, count 0 2006.176.07:53:40.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.07:53:40.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:53:40.61#ibcon#*before write, iclass 23, count 0 2006.176.07:53:40.61#ibcon#enter sib2, iclass 23, count 0 2006.176.07:53:40.61#ibcon#flushed, iclass 23, count 0 2006.176.07:53:40.61#ibcon#about to write, iclass 23, count 0 2006.176.07:53:40.62#ibcon#wrote, iclass 23, count 0 2006.176.07:53:40.62#ibcon#about to read 3, iclass 23, count 0 2006.176.07:53:40.65#ibcon#read 3, iclass 23, count 0 2006.176.07:53:40.65#ibcon#about to read 4, iclass 23, count 0 2006.176.07:53:40.65#ibcon#read 4, iclass 23, count 0 2006.176.07:53:40.65#ibcon#about to read 5, iclass 23, count 0 2006.176.07:53:40.65#ibcon#read 5, iclass 23, count 0 2006.176.07:53:40.65#ibcon#about to read 6, iclass 23, count 0 2006.176.07:53:40.65#ibcon#read 6, iclass 23, count 0 2006.176.07:53:40.65#ibcon#end of sib2, iclass 23, count 0 2006.176.07:53:40.65#ibcon#*after write, iclass 23, count 0 2006.176.07:53:40.65#ibcon#*before return 0, iclass 23, count 0 2006.176.07:53:40.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:53:40.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.07:53:40.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.07:53:40.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.07:53:40.66$vc4f8/vb=1,4 2006.176.07:53:40.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.176.07:53:40.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.176.07:53:40.66#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:40.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:53:40.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:53:40.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:53:40.66#ibcon#enter wrdev, iclass 25, count 2 2006.176.07:53:40.66#ibcon#first serial, iclass 25, count 2 2006.176.07:53:40.66#ibcon#enter sib2, iclass 25, count 2 2006.176.07:53:40.66#ibcon#flushed, iclass 25, count 2 2006.176.07:53:40.66#ibcon#about to write, iclass 25, count 2 2006.176.07:53:40.66#ibcon#wrote, iclass 25, count 2 2006.176.07:53:40.66#ibcon#about to read 3, iclass 25, count 2 2006.176.07:53:40.67#ibcon#read 3, iclass 25, count 2 2006.176.07:53:40.67#ibcon#about to read 4, iclass 25, count 2 2006.176.07:53:40.67#ibcon#read 4, iclass 25, count 2 2006.176.07:53:40.67#ibcon#about to read 5, iclass 25, count 2 2006.176.07:53:40.67#ibcon#read 5, iclass 25, count 2 2006.176.07:53:40.67#ibcon#about to read 6, iclass 25, count 2 2006.176.07:53:40.67#ibcon#read 6, iclass 25, count 2 2006.176.07:53:40.67#ibcon#end of sib2, iclass 25, count 2 2006.176.07:53:40.67#ibcon#*mode == 0, iclass 25, count 2 2006.176.07:53:40.67#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.176.07:53:40.67#ibcon#[27=AT01-04\r\n] 2006.176.07:53:40.67#ibcon#*before write, iclass 25, count 2 2006.176.07:53:40.67#ibcon#enter sib2, iclass 25, count 2 2006.176.07:53:40.67#ibcon#flushed, iclass 25, count 2 2006.176.07:53:40.67#ibcon#about to write, iclass 25, count 2 2006.176.07:53:40.68#ibcon#wrote, iclass 25, count 2 2006.176.07:53:40.68#ibcon#about to read 3, iclass 25, count 2 2006.176.07:53:40.70#ibcon#read 3, iclass 25, count 2 2006.176.07:53:40.70#ibcon#about to read 4, iclass 25, count 2 2006.176.07:53:40.70#ibcon#read 4, iclass 25, count 2 2006.176.07:53:40.70#ibcon#about to read 5, iclass 25, count 2 2006.176.07:53:40.70#ibcon#read 5, iclass 25, count 2 2006.176.07:53:40.70#ibcon#about to read 6, iclass 25, count 2 2006.176.07:53:40.70#ibcon#read 6, iclass 25, count 2 2006.176.07:53:40.70#ibcon#end of sib2, iclass 25, count 2 2006.176.07:53:40.70#ibcon#*after write, iclass 25, count 2 2006.176.07:53:40.70#ibcon#*before return 0, iclass 25, count 2 2006.176.07:53:40.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:53:40.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.176.07:53:40.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.176.07:53:40.70#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:40.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:53:40.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:53:40.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:53:40.82#ibcon#enter wrdev, iclass 25, count 0 2006.176.07:53:40.82#ibcon#first serial, iclass 25, count 0 2006.176.07:53:40.82#ibcon#enter sib2, iclass 25, count 0 2006.176.07:53:40.82#ibcon#flushed, iclass 25, count 0 2006.176.07:53:40.82#ibcon#about to write, iclass 25, count 0 2006.176.07:53:40.82#ibcon#wrote, iclass 25, count 0 2006.176.07:53:40.82#ibcon#about to read 3, iclass 25, count 0 2006.176.07:53:40.84#ibcon#read 3, iclass 25, count 0 2006.176.07:53:40.84#ibcon#about to read 4, iclass 25, count 0 2006.176.07:53:40.84#ibcon#read 4, iclass 25, count 0 2006.176.07:53:40.84#ibcon#about to read 5, iclass 25, count 0 2006.176.07:53:40.84#ibcon#read 5, iclass 25, count 0 2006.176.07:53:40.84#ibcon#about to read 6, iclass 25, count 0 2006.176.07:53:40.84#ibcon#read 6, iclass 25, count 0 2006.176.07:53:40.84#ibcon#end of sib2, iclass 25, count 0 2006.176.07:53:40.84#ibcon#*mode == 0, iclass 25, count 0 2006.176.07:53:40.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.07:53:40.84#ibcon#[27=USB\r\n] 2006.176.07:53:40.84#ibcon#*before write, iclass 25, count 0 2006.176.07:53:40.85#ibcon#enter sib2, iclass 25, count 0 2006.176.07:53:40.85#ibcon#flushed, iclass 25, count 0 2006.176.07:53:40.85#ibcon#about to write, iclass 25, count 0 2006.176.07:53:40.85#ibcon#wrote, iclass 25, count 0 2006.176.07:53:40.85#ibcon#about to read 3, iclass 25, count 0 2006.176.07:53:40.87#ibcon#read 3, iclass 25, count 0 2006.176.07:53:40.87#ibcon#about to read 4, iclass 25, count 0 2006.176.07:53:40.87#ibcon#read 4, iclass 25, count 0 2006.176.07:53:40.87#ibcon#about to read 5, iclass 25, count 0 2006.176.07:53:40.87#ibcon#read 5, iclass 25, count 0 2006.176.07:53:40.87#ibcon#about to read 6, iclass 25, count 0 2006.176.07:53:40.87#ibcon#read 6, iclass 25, count 0 2006.176.07:53:40.87#ibcon#end of sib2, iclass 25, count 0 2006.176.07:53:40.87#ibcon#*after write, iclass 25, count 0 2006.176.07:53:40.87#ibcon#*before return 0, iclass 25, count 0 2006.176.07:53:40.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:53:40.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.176.07:53:40.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.07:53:40.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.07:53:40.88$vc4f8/vblo=2,640.99 2006.176.07:53:40.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.07:53:40.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.07:53:40.88#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:40.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:40.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:40.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:40.88#ibcon#enter wrdev, iclass 27, count 0 2006.176.07:53:40.88#ibcon#first serial, iclass 27, count 0 2006.176.07:53:40.88#ibcon#enter sib2, iclass 27, count 0 2006.176.07:53:40.88#ibcon#flushed, iclass 27, count 0 2006.176.07:53:40.88#ibcon#about to write, iclass 27, count 0 2006.176.07:53:40.88#ibcon#wrote, iclass 27, count 0 2006.176.07:53:40.88#ibcon#about to read 3, iclass 27, count 0 2006.176.07:53:40.89#ibcon#read 3, iclass 27, count 0 2006.176.07:53:40.89#ibcon#about to read 4, iclass 27, count 0 2006.176.07:53:40.89#ibcon#read 4, iclass 27, count 0 2006.176.07:53:40.89#ibcon#about to read 5, iclass 27, count 0 2006.176.07:53:40.89#ibcon#read 5, iclass 27, count 0 2006.176.07:53:40.89#ibcon#about to read 6, iclass 27, count 0 2006.176.07:53:40.89#ibcon#read 6, iclass 27, count 0 2006.176.07:53:40.89#ibcon#end of sib2, iclass 27, count 0 2006.176.07:53:40.89#ibcon#*mode == 0, iclass 27, count 0 2006.176.07:53:40.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.07:53:40.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:53:40.89#ibcon#*before write, iclass 27, count 0 2006.176.07:53:40.89#ibcon#enter sib2, iclass 27, count 0 2006.176.07:53:40.89#ibcon#flushed, iclass 27, count 0 2006.176.07:53:40.89#ibcon#about to write, iclass 27, count 0 2006.176.07:53:40.90#ibcon#wrote, iclass 27, count 0 2006.176.07:53:40.90#ibcon#about to read 3, iclass 27, count 0 2006.176.07:53:40.93#ibcon#read 3, iclass 27, count 0 2006.176.07:53:40.93#ibcon#about to read 4, iclass 27, count 0 2006.176.07:53:40.93#ibcon#read 4, iclass 27, count 0 2006.176.07:53:40.93#ibcon#about to read 5, iclass 27, count 0 2006.176.07:53:40.93#ibcon#read 5, iclass 27, count 0 2006.176.07:53:40.93#ibcon#about to read 6, iclass 27, count 0 2006.176.07:53:40.93#ibcon#read 6, iclass 27, count 0 2006.176.07:53:40.93#ibcon#end of sib2, iclass 27, count 0 2006.176.07:53:40.93#ibcon#*after write, iclass 27, count 0 2006.176.07:53:40.93#ibcon#*before return 0, iclass 27, count 0 2006.176.07:53:40.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:40.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.07:53:40.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.07:53:40.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.07:53:40.94$vc4f8/vb=2,4 2006.176.07:53:40.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.07:53:40.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.07:53:40.94#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:40.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:40.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:40.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:40.98#ibcon#enter wrdev, iclass 29, count 2 2006.176.07:53:40.98#ibcon#first serial, iclass 29, count 2 2006.176.07:53:40.98#ibcon#enter sib2, iclass 29, count 2 2006.176.07:53:40.98#ibcon#flushed, iclass 29, count 2 2006.176.07:53:40.98#ibcon#about to write, iclass 29, count 2 2006.176.07:53:40.98#ibcon#wrote, iclass 29, count 2 2006.176.07:53:40.98#ibcon#about to read 3, iclass 29, count 2 2006.176.07:53:41.00#ibcon#read 3, iclass 29, count 2 2006.176.07:53:41.00#ibcon#about to read 4, iclass 29, count 2 2006.176.07:53:41.00#ibcon#read 4, iclass 29, count 2 2006.176.07:53:41.00#ibcon#about to read 5, iclass 29, count 2 2006.176.07:53:41.00#ibcon#read 5, iclass 29, count 2 2006.176.07:53:41.00#ibcon#about to read 6, iclass 29, count 2 2006.176.07:53:41.00#ibcon#read 6, iclass 29, count 2 2006.176.07:53:41.00#ibcon#end of sib2, iclass 29, count 2 2006.176.07:53:41.00#ibcon#*mode == 0, iclass 29, count 2 2006.176.07:53:41.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.07:53:41.00#ibcon#[27=AT02-04\r\n] 2006.176.07:53:41.00#ibcon#*before write, iclass 29, count 2 2006.176.07:53:41.00#ibcon#enter sib2, iclass 29, count 2 2006.176.07:53:41.00#ibcon#flushed, iclass 29, count 2 2006.176.07:53:41.00#ibcon#about to write, iclass 29, count 2 2006.176.07:53:41.01#ibcon#wrote, iclass 29, count 2 2006.176.07:53:41.01#ibcon#about to read 3, iclass 29, count 2 2006.176.07:53:41.03#ibcon#read 3, iclass 29, count 2 2006.176.07:53:41.03#ibcon#about to read 4, iclass 29, count 2 2006.176.07:53:41.03#ibcon#read 4, iclass 29, count 2 2006.176.07:53:41.03#ibcon#about to read 5, iclass 29, count 2 2006.176.07:53:41.03#ibcon#read 5, iclass 29, count 2 2006.176.07:53:41.03#ibcon#about to read 6, iclass 29, count 2 2006.176.07:53:41.03#ibcon#read 6, iclass 29, count 2 2006.176.07:53:41.03#ibcon#end of sib2, iclass 29, count 2 2006.176.07:53:41.03#ibcon#*after write, iclass 29, count 2 2006.176.07:53:41.03#ibcon#*before return 0, iclass 29, count 2 2006.176.07:53:41.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:41.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.07:53:41.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.07:53:41.03#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:41.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:41.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:41.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:41.15#ibcon#enter wrdev, iclass 29, count 0 2006.176.07:53:41.15#ibcon#first serial, iclass 29, count 0 2006.176.07:53:41.15#ibcon#enter sib2, iclass 29, count 0 2006.176.07:53:41.15#ibcon#flushed, iclass 29, count 0 2006.176.07:53:41.15#ibcon#about to write, iclass 29, count 0 2006.176.07:53:41.15#ibcon#wrote, iclass 29, count 0 2006.176.07:53:41.15#ibcon#about to read 3, iclass 29, count 0 2006.176.07:53:41.16#ibcon#read 3, iclass 29, count 0 2006.176.07:53:41.16#ibcon#about to read 4, iclass 29, count 0 2006.176.07:53:41.16#ibcon#read 4, iclass 29, count 0 2006.176.07:53:41.16#ibcon#about to read 5, iclass 29, count 0 2006.176.07:53:41.16#ibcon#read 5, iclass 29, count 0 2006.176.07:53:41.16#ibcon#about to read 6, iclass 29, count 0 2006.176.07:53:41.16#ibcon#read 6, iclass 29, count 0 2006.176.07:53:41.16#ibcon#end of sib2, iclass 29, count 0 2006.176.07:53:41.16#ibcon#*mode == 0, iclass 29, count 0 2006.176.07:53:41.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.07:53:41.16#ibcon#[27=USB\r\n] 2006.176.07:53:41.16#ibcon#*before write, iclass 29, count 0 2006.176.07:53:41.16#ibcon#enter sib2, iclass 29, count 0 2006.176.07:53:41.16#ibcon#flushed, iclass 29, count 0 2006.176.07:53:41.16#ibcon#about to write, iclass 29, count 0 2006.176.07:53:41.17#ibcon#wrote, iclass 29, count 0 2006.176.07:53:41.17#ibcon#about to read 3, iclass 29, count 0 2006.176.07:53:41.19#ibcon#read 3, iclass 29, count 0 2006.176.07:53:41.19#ibcon#about to read 4, iclass 29, count 0 2006.176.07:53:41.19#ibcon#read 4, iclass 29, count 0 2006.176.07:53:41.19#ibcon#about to read 5, iclass 29, count 0 2006.176.07:53:41.19#ibcon#read 5, iclass 29, count 0 2006.176.07:53:41.19#ibcon#about to read 6, iclass 29, count 0 2006.176.07:53:41.19#ibcon#read 6, iclass 29, count 0 2006.176.07:53:41.19#ibcon#end of sib2, iclass 29, count 0 2006.176.07:53:41.19#ibcon#*after write, iclass 29, count 0 2006.176.07:53:41.19#ibcon#*before return 0, iclass 29, count 0 2006.176.07:53:41.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:41.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.07:53:41.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.07:53:41.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.07:53:41.20$vc4f8/vblo=3,656.99 2006.176.07:53:41.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.07:53:41.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.07:53:41.20#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:41.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:41.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:41.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:41.20#ibcon#enter wrdev, iclass 31, count 0 2006.176.07:53:41.20#ibcon#first serial, iclass 31, count 0 2006.176.07:53:41.20#ibcon#enter sib2, iclass 31, count 0 2006.176.07:53:41.20#ibcon#flushed, iclass 31, count 0 2006.176.07:53:41.20#ibcon#about to write, iclass 31, count 0 2006.176.07:53:41.20#ibcon#wrote, iclass 31, count 0 2006.176.07:53:41.20#ibcon#about to read 3, iclass 31, count 0 2006.176.07:53:41.22#ibcon#read 3, iclass 31, count 0 2006.176.07:53:41.22#ibcon#about to read 4, iclass 31, count 0 2006.176.07:53:41.22#ibcon#read 4, iclass 31, count 0 2006.176.07:53:41.22#ibcon#about to read 5, iclass 31, count 0 2006.176.07:53:41.22#ibcon#read 5, iclass 31, count 0 2006.176.07:53:41.22#ibcon#about to read 6, iclass 31, count 0 2006.176.07:53:41.22#ibcon#read 6, iclass 31, count 0 2006.176.07:53:41.22#ibcon#end of sib2, iclass 31, count 0 2006.176.07:53:41.22#ibcon#*mode == 0, iclass 31, count 0 2006.176.07:53:41.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.07:53:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:53:41.22#ibcon#*before write, iclass 31, count 0 2006.176.07:53:41.22#ibcon#enter sib2, iclass 31, count 0 2006.176.07:53:41.22#ibcon#flushed, iclass 31, count 0 2006.176.07:53:41.22#ibcon#about to write, iclass 31, count 0 2006.176.07:53:41.22#ibcon#wrote, iclass 31, count 0 2006.176.07:53:41.22#ibcon#about to read 3, iclass 31, count 0 2006.176.07:53:41.25#ibcon#read 3, iclass 31, count 0 2006.176.07:53:41.25#ibcon#about to read 4, iclass 31, count 0 2006.176.07:53:41.25#ibcon#read 4, iclass 31, count 0 2006.176.07:53:41.25#ibcon#about to read 5, iclass 31, count 0 2006.176.07:53:41.25#ibcon#read 5, iclass 31, count 0 2006.176.07:53:41.25#ibcon#about to read 6, iclass 31, count 0 2006.176.07:53:41.25#ibcon#read 6, iclass 31, count 0 2006.176.07:53:41.25#ibcon#end of sib2, iclass 31, count 0 2006.176.07:53:41.25#ibcon#*after write, iclass 31, count 0 2006.176.07:53:41.25#ibcon#*before return 0, iclass 31, count 0 2006.176.07:53:41.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:41.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.07:53:41.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.07:53:41.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.07:53:41.26$vc4f8/vb=3,4 2006.176.07:53:41.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.176.07:53:41.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.176.07:53:41.26#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:41.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:41.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:41.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:41.30#ibcon#enter wrdev, iclass 33, count 2 2006.176.07:53:41.30#ibcon#first serial, iclass 33, count 2 2006.176.07:53:41.30#ibcon#enter sib2, iclass 33, count 2 2006.176.07:53:41.30#ibcon#flushed, iclass 33, count 2 2006.176.07:53:41.30#ibcon#about to write, iclass 33, count 2 2006.176.07:53:41.30#ibcon#wrote, iclass 33, count 2 2006.176.07:53:41.30#ibcon#about to read 3, iclass 33, count 2 2006.176.07:53:41.32#ibcon#read 3, iclass 33, count 2 2006.176.07:53:41.32#ibcon#about to read 4, iclass 33, count 2 2006.176.07:53:41.32#ibcon#read 4, iclass 33, count 2 2006.176.07:53:41.32#ibcon#about to read 5, iclass 33, count 2 2006.176.07:53:41.32#ibcon#read 5, iclass 33, count 2 2006.176.07:53:41.32#ibcon#about to read 6, iclass 33, count 2 2006.176.07:53:41.32#ibcon#read 6, iclass 33, count 2 2006.176.07:53:41.32#ibcon#end of sib2, iclass 33, count 2 2006.176.07:53:41.32#ibcon#*mode == 0, iclass 33, count 2 2006.176.07:53:41.32#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.176.07:53:41.32#ibcon#[27=AT03-04\r\n] 2006.176.07:53:41.32#ibcon#*before write, iclass 33, count 2 2006.176.07:53:41.32#ibcon#enter sib2, iclass 33, count 2 2006.176.07:53:41.32#ibcon#flushed, iclass 33, count 2 2006.176.07:53:41.33#ibcon#about to write, iclass 33, count 2 2006.176.07:53:41.33#ibcon#wrote, iclass 33, count 2 2006.176.07:53:41.33#ibcon#about to read 3, iclass 33, count 2 2006.176.07:53:41.35#ibcon#read 3, iclass 33, count 2 2006.176.07:53:41.35#ibcon#about to read 4, iclass 33, count 2 2006.176.07:53:41.35#ibcon#read 4, iclass 33, count 2 2006.176.07:53:41.35#ibcon#about to read 5, iclass 33, count 2 2006.176.07:53:41.35#ibcon#read 5, iclass 33, count 2 2006.176.07:53:41.35#ibcon#about to read 6, iclass 33, count 2 2006.176.07:53:41.35#ibcon#read 6, iclass 33, count 2 2006.176.07:53:41.35#ibcon#end of sib2, iclass 33, count 2 2006.176.07:53:41.35#ibcon#*after write, iclass 33, count 2 2006.176.07:53:41.35#ibcon#*before return 0, iclass 33, count 2 2006.176.07:53:41.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:41.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.176.07:53:41.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.176.07:53:41.35#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:41.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:41.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:41.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:41.47#ibcon#enter wrdev, iclass 33, count 0 2006.176.07:53:41.47#ibcon#first serial, iclass 33, count 0 2006.176.07:53:41.47#ibcon#enter sib2, iclass 33, count 0 2006.176.07:53:41.47#ibcon#flushed, iclass 33, count 0 2006.176.07:53:41.47#ibcon#about to write, iclass 33, count 0 2006.176.07:53:41.47#ibcon#wrote, iclass 33, count 0 2006.176.07:53:41.47#ibcon#about to read 3, iclass 33, count 0 2006.176.07:53:41.49#ibcon#read 3, iclass 33, count 0 2006.176.07:53:41.49#ibcon#about to read 4, iclass 33, count 0 2006.176.07:53:41.49#ibcon#read 4, iclass 33, count 0 2006.176.07:53:41.49#ibcon#about to read 5, iclass 33, count 0 2006.176.07:53:41.49#ibcon#read 5, iclass 33, count 0 2006.176.07:53:41.49#ibcon#about to read 6, iclass 33, count 0 2006.176.07:53:41.49#ibcon#read 6, iclass 33, count 0 2006.176.07:53:41.49#ibcon#end of sib2, iclass 33, count 0 2006.176.07:53:41.49#ibcon#*mode == 0, iclass 33, count 0 2006.176.07:53:41.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.07:53:41.49#ibcon#[27=USB\r\n] 2006.176.07:53:41.49#ibcon#*before write, iclass 33, count 0 2006.176.07:53:41.49#ibcon#enter sib2, iclass 33, count 0 2006.176.07:53:41.49#ibcon#flushed, iclass 33, count 0 2006.176.07:53:41.49#ibcon#about to write, iclass 33, count 0 2006.176.07:53:41.50#ibcon#wrote, iclass 33, count 0 2006.176.07:53:41.50#ibcon#about to read 3, iclass 33, count 0 2006.176.07:53:41.52#ibcon#read 3, iclass 33, count 0 2006.176.07:53:41.52#ibcon#about to read 4, iclass 33, count 0 2006.176.07:53:41.52#ibcon#read 4, iclass 33, count 0 2006.176.07:53:41.52#ibcon#about to read 5, iclass 33, count 0 2006.176.07:53:41.52#ibcon#read 5, iclass 33, count 0 2006.176.07:53:41.52#ibcon#about to read 6, iclass 33, count 0 2006.176.07:53:41.52#ibcon#read 6, iclass 33, count 0 2006.176.07:53:41.52#ibcon#end of sib2, iclass 33, count 0 2006.176.07:53:41.52#ibcon#*after write, iclass 33, count 0 2006.176.07:53:41.52#ibcon#*before return 0, iclass 33, count 0 2006.176.07:53:41.52#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:41.52#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.176.07:53:41.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.07:53:41.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.07:53:41.53$vc4f8/vblo=4,712.99 2006.176.07:53:41.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.07:53:41.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.07:53:41.53#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:41.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:41.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:41.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:41.53#ibcon#enter wrdev, iclass 35, count 0 2006.176.07:53:41.53#ibcon#first serial, iclass 35, count 0 2006.176.07:53:41.53#ibcon#enter sib2, iclass 35, count 0 2006.176.07:53:41.53#ibcon#flushed, iclass 35, count 0 2006.176.07:53:41.53#ibcon#about to write, iclass 35, count 0 2006.176.07:53:41.53#ibcon#wrote, iclass 35, count 0 2006.176.07:53:41.53#ibcon#about to read 3, iclass 35, count 0 2006.176.07:53:41.54#ibcon#read 3, iclass 35, count 0 2006.176.07:53:41.54#ibcon#about to read 4, iclass 35, count 0 2006.176.07:53:41.54#ibcon#read 4, iclass 35, count 0 2006.176.07:53:41.54#ibcon#about to read 5, iclass 35, count 0 2006.176.07:53:41.54#ibcon#read 5, iclass 35, count 0 2006.176.07:53:41.54#ibcon#about to read 6, iclass 35, count 0 2006.176.07:53:41.54#ibcon#read 6, iclass 35, count 0 2006.176.07:53:41.54#ibcon#end of sib2, iclass 35, count 0 2006.176.07:53:41.54#ibcon#*mode == 0, iclass 35, count 0 2006.176.07:53:41.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.07:53:41.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:53:41.54#ibcon#*before write, iclass 35, count 0 2006.176.07:53:41.54#ibcon#enter sib2, iclass 35, count 0 2006.176.07:53:41.54#ibcon#flushed, iclass 35, count 0 2006.176.07:53:41.54#ibcon#about to write, iclass 35, count 0 2006.176.07:53:41.55#ibcon#wrote, iclass 35, count 0 2006.176.07:53:41.55#ibcon#about to read 3, iclass 35, count 0 2006.176.07:53:41.58#ibcon#read 3, iclass 35, count 0 2006.176.07:53:41.58#ibcon#about to read 4, iclass 35, count 0 2006.176.07:53:41.58#ibcon#read 4, iclass 35, count 0 2006.176.07:53:41.58#ibcon#about to read 5, iclass 35, count 0 2006.176.07:53:41.58#ibcon#read 5, iclass 35, count 0 2006.176.07:53:41.58#ibcon#about to read 6, iclass 35, count 0 2006.176.07:53:41.58#ibcon#read 6, iclass 35, count 0 2006.176.07:53:41.58#ibcon#end of sib2, iclass 35, count 0 2006.176.07:53:41.58#ibcon#*after write, iclass 35, count 0 2006.176.07:53:41.58#ibcon#*before return 0, iclass 35, count 0 2006.176.07:53:41.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:41.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.07:53:41.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.07:53:41.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.07:53:41.59$vc4f8/vb=4,4 2006.176.07:53:41.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.176.07:53:41.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.176.07:53:41.59#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:41.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:41.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:41.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:41.63#ibcon#enter wrdev, iclass 37, count 2 2006.176.07:53:41.63#ibcon#first serial, iclass 37, count 2 2006.176.07:53:41.63#ibcon#enter sib2, iclass 37, count 2 2006.176.07:53:41.63#ibcon#flushed, iclass 37, count 2 2006.176.07:53:41.63#ibcon#about to write, iclass 37, count 2 2006.176.07:53:41.63#ibcon#wrote, iclass 37, count 2 2006.176.07:53:41.63#ibcon#about to read 3, iclass 37, count 2 2006.176.07:53:41.65#ibcon#read 3, iclass 37, count 2 2006.176.07:53:41.65#ibcon#about to read 4, iclass 37, count 2 2006.176.07:53:41.65#ibcon#read 4, iclass 37, count 2 2006.176.07:53:41.65#ibcon#about to read 5, iclass 37, count 2 2006.176.07:53:41.65#ibcon#read 5, iclass 37, count 2 2006.176.07:53:41.65#ibcon#about to read 6, iclass 37, count 2 2006.176.07:53:41.65#ibcon#read 6, iclass 37, count 2 2006.176.07:53:41.65#ibcon#end of sib2, iclass 37, count 2 2006.176.07:53:41.65#ibcon#*mode == 0, iclass 37, count 2 2006.176.07:53:41.65#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.176.07:53:41.65#ibcon#[27=AT04-04\r\n] 2006.176.07:53:41.65#ibcon#*before write, iclass 37, count 2 2006.176.07:53:41.65#ibcon#enter sib2, iclass 37, count 2 2006.176.07:53:41.65#ibcon#flushed, iclass 37, count 2 2006.176.07:53:41.65#ibcon#about to write, iclass 37, count 2 2006.176.07:53:41.66#ibcon#wrote, iclass 37, count 2 2006.176.07:53:41.66#ibcon#about to read 3, iclass 37, count 2 2006.176.07:53:41.68#ibcon#read 3, iclass 37, count 2 2006.176.07:53:41.68#ibcon#about to read 4, iclass 37, count 2 2006.176.07:53:41.68#ibcon#read 4, iclass 37, count 2 2006.176.07:53:41.68#ibcon#about to read 5, iclass 37, count 2 2006.176.07:53:41.68#ibcon#read 5, iclass 37, count 2 2006.176.07:53:41.68#ibcon#about to read 6, iclass 37, count 2 2006.176.07:53:41.68#ibcon#read 6, iclass 37, count 2 2006.176.07:53:41.68#ibcon#end of sib2, iclass 37, count 2 2006.176.07:53:41.68#ibcon#*after write, iclass 37, count 2 2006.176.07:53:41.68#ibcon#*before return 0, iclass 37, count 2 2006.176.07:53:41.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:41.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.176.07:53:41.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.176.07:53:41.68#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:41.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:41.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:41.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:41.80#ibcon#enter wrdev, iclass 37, count 0 2006.176.07:53:41.80#ibcon#first serial, iclass 37, count 0 2006.176.07:53:41.80#ibcon#enter sib2, iclass 37, count 0 2006.176.07:53:41.80#ibcon#flushed, iclass 37, count 0 2006.176.07:53:41.80#ibcon#about to write, iclass 37, count 0 2006.176.07:53:41.80#ibcon#wrote, iclass 37, count 0 2006.176.07:53:41.80#ibcon#about to read 3, iclass 37, count 0 2006.176.07:53:41.82#ibcon#read 3, iclass 37, count 0 2006.176.07:53:41.82#ibcon#about to read 4, iclass 37, count 0 2006.176.07:53:41.82#ibcon#read 4, iclass 37, count 0 2006.176.07:53:41.82#ibcon#about to read 5, iclass 37, count 0 2006.176.07:53:41.82#ibcon#read 5, iclass 37, count 0 2006.176.07:53:41.82#ibcon#about to read 6, iclass 37, count 0 2006.176.07:53:41.82#ibcon#read 6, iclass 37, count 0 2006.176.07:53:41.82#ibcon#end of sib2, iclass 37, count 0 2006.176.07:53:41.82#ibcon#*mode == 0, iclass 37, count 0 2006.176.07:53:41.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.07:53:41.82#ibcon#[27=USB\r\n] 2006.176.07:53:41.82#ibcon#*before write, iclass 37, count 0 2006.176.07:53:41.82#ibcon#enter sib2, iclass 37, count 0 2006.176.07:53:41.82#ibcon#flushed, iclass 37, count 0 2006.176.07:53:41.82#ibcon#about to write, iclass 37, count 0 2006.176.07:53:41.83#ibcon#wrote, iclass 37, count 0 2006.176.07:53:41.83#ibcon#about to read 3, iclass 37, count 0 2006.176.07:53:41.85#ibcon#read 3, iclass 37, count 0 2006.176.07:53:41.85#ibcon#about to read 4, iclass 37, count 0 2006.176.07:53:41.85#ibcon#read 4, iclass 37, count 0 2006.176.07:53:41.85#ibcon#about to read 5, iclass 37, count 0 2006.176.07:53:41.85#ibcon#read 5, iclass 37, count 0 2006.176.07:53:41.85#ibcon#about to read 6, iclass 37, count 0 2006.176.07:53:41.85#ibcon#read 6, iclass 37, count 0 2006.176.07:53:41.85#ibcon#end of sib2, iclass 37, count 0 2006.176.07:53:41.85#ibcon#*after write, iclass 37, count 0 2006.176.07:53:41.85#ibcon#*before return 0, iclass 37, count 0 2006.176.07:53:41.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:41.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.176.07:53:41.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.07:53:41.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.07:53:41.86$vc4f8/vblo=5,744.99 2006.176.07:53:41.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.07:53:41.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.07:53:41.86#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:41.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:41.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:41.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:41.86#ibcon#enter wrdev, iclass 39, count 0 2006.176.07:53:41.86#ibcon#first serial, iclass 39, count 0 2006.176.07:53:41.86#ibcon#enter sib2, iclass 39, count 0 2006.176.07:53:41.86#ibcon#flushed, iclass 39, count 0 2006.176.07:53:41.86#ibcon#about to write, iclass 39, count 0 2006.176.07:53:41.86#ibcon#wrote, iclass 39, count 0 2006.176.07:53:41.86#ibcon#about to read 3, iclass 39, count 0 2006.176.07:53:41.87#ibcon#read 3, iclass 39, count 0 2006.176.07:53:41.87#ibcon#about to read 4, iclass 39, count 0 2006.176.07:53:41.87#ibcon#read 4, iclass 39, count 0 2006.176.07:53:41.87#ibcon#about to read 5, iclass 39, count 0 2006.176.07:53:41.87#ibcon#read 5, iclass 39, count 0 2006.176.07:53:41.87#ibcon#about to read 6, iclass 39, count 0 2006.176.07:53:41.87#ibcon#read 6, iclass 39, count 0 2006.176.07:53:41.87#ibcon#end of sib2, iclass 39, count 0 2006.176.07:53:41.87#ibcon#*mode == 0, iclass 39, count 0 2006.176.07:53:41.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.07:53:41.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:53:41.87#ibcon#*before write, iclass 39, count 0 2006.176.07:53:41.87#ibcon#enter sib2, iclass 39, count 0 2006.176.07:53:41.87#ibcon#flushed, iclass 39, count 0 2006.176.07:53:41.87#ibcon#about to write, iclass 39, count 0 2006.176.07:53:41.88#ibcon#wrote, iclass 39, count 0 2006.176.07:53:41.88#ibcon#about to read 3, iclass 39, count 0 2006.176.07:53:41.91#ibcon#read 3, iclass 39, count 0 2006.176.07:53:41.91#ibcon#about to read 4, iclass 39, count 0 2006.176.07:53:41.91#ibcon#read 4, iclass 39, count 0 2006.176.07:53:41.91#ibcon#about to read 5, iclass 39, count 0 2006.176.07:53:41.91#ibcon#read 5, iclass 39, count 0 2006.176.07:53:41.91#ibcon#about to read 6, iclass 39, count 0 2006.176.07:53:41.91#ibcon#read 6, iclass 39, count 0 2006.176.07:53:41.91#ibcon#end of sib2, iclass 39, count 0 2006.176.07:53:41.91#ibcon#*after write, iclass 39, count 0 2006.176.07:53:41.91#ibcon#*before return 0, iclass 39, count 0 2006.176.07:53:41.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:41.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.07:53:41.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.07:53:41.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.07:53:41.92$vc4f8/vb=5,4 2006.176.07:53:41.92#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.07:53:41.92#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.07:53:41.92#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:41.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:41.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:41.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:41.97#ibcon#enter wrdev, iclass 3, count 2 2006.176.07:53:41.97#ibcon#first serial, iclass 3, count 2 2006.176.07:53:41.97#ibcon#enter sib2, iclass 3, count 2 2006.176.07:53:41.97#ibcon#flushed, iclass 3, count 2 2006.176.07:53:41.97#ibcon#about to write, iclass 3, count 2 2006.176.07:53:41.97#ibcon#wrote, iclass 3, count 2 2006.176.07:53:41.97#ibcon#about to read 3, iclass 3, count 2 2006.176.07:53:41.99#ibcon#read 3, iclass 3, count 2 2006.176.07:53:41.99#ibcon#about to read 4, iclass 3, count 2 2006.176.07:53:41.99#ibcon#read 4, iclass 3, count 2 2006.176.07:53:41.99#ibcon#about to read 5, iclass 3, count 2 2006.176.07:53:41.99#ibcon#read 5, iclass 3, count 2 2006.176.07:53:41.99#ibcon#about to read 6, iclass 3, count 2 2006.176.07:53:41.99#ibcon#read 6, iclass 3, count 2 2006.176.07:53:41.99#ibcon#end of sib2, iclass 3, count 2 2006.176.07:53:41.99#ibcon#*mode == 0, iclass 3, count 2 2006.176.07:53:41.99#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.07:53:41.99#ibcon#[27=AT05-04\r\n] 2006.176.07:53:41.99#ibcon#*before write, iclass 3, count 2 2006.176.07:53:41.99#ibcon#enter sib2, iclass 3, count 2 2006.176.07:53:41.99#ibcon#flushed, iclass 3, count 2 2006.176.07:53:41.99#ibcon#about to write, iclass 3, count 2 2006.176.07:53:41.99#ibcon#wrote, iclass 3, count 2 2006.176.07:53:41.99#ibcon#about to read 3, iclass 3, count 2 2006.176.07:53:42.02#ibcon#read 3, iclass 3, count 2 2006.176.07:53:42.02#ibcon#about to read 4, iclass 3, count 2 2006.176.07:53:42.02#ibcon#read 4, iclass 3, count 2 2006.176.07:53:42.02#ibcon#about to read 5, iclass 3, count 2 2006.176.07:53:42.02#ibcon#read 5, iclass 3, count 2 2006.176.07:53:42.02#ibcon#about to read 6, iclass 3, count 2 2006.176.07:53:42.02#ibcon#read 6, iclass 3, count 2 2006.176.07:53:42.02#ibcon#end of sib2, iclass 3, count 2 2006.176.07:53:42.02#ibcon#*after write, iclass 3, count 2 2006.176.07:53:42.02#ibcon#*before return 0, iclass 3, count 2 2006.176.07:53:42.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:42.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.07:53:42.02#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.07:53:42.02#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:42.02#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:42.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:42.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:42.13#ibcon#enter wrdev, iclass 3, count 0 2006.176.07:53:42.13#ibcon#first serial, iclass 3, count 0 2006.176.07:53:42.13#ibcon#enter sib2, iclass 3, count 0 2006.176.07:53:42.13#ibcon#flushed, iclass 3, count 0 2006.176.07:53:42.13#ibcon#about to write, iclass 3, count 0 2006.176.07:53:42.13#ibcon#wrote, iclass 3, count 0 2006.176.07:53:42.13#ibcon#about to read 3, iclass 3, count 0 2006.176.07:53:42.15#ibcon#read 3, iclass 3, count 0 2006.176.07:53:42.15#ibcon#about to read 4, iclass 3, count 0 2006.176.07:53:42.15#ibcon#read 4, iclass 3, count 0 2006.176.07:53:42.15#ibcon#about to read 5, iclass 3, count 0 2006.176.07:53:42.15#ibcon#read 5, iclass 3, count 0 2006.176.07:53:42.15#ibcon#about to read 6, iclass 3, count 0 2006.176.07:53:42.15#ibcon#read 6, iclass 3, count 0 2006.176.07:53:42.15#ibcon#end of sib2, iclass 3, count 0 2006.176.07:53:42.15#ibcon#*mode == 0, iclass 3, count 0 2006.176.07:53:42.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.07:53:42.15#ibcon#[27=USB\r\n] 2006.176.07:53:42.15#ibcon#*before write, iclass 3, count 0 2006.176.07:53:42.15#ibcon#enter sib2, iclass 3, count 0 2006.176.07:53:42.15#ibcon#flushed, iclass 3, count 0 2006.176.07:53:42.15#ibcon#about to write, iclass 3, count 0 2006.176.07:53:42.16#ibcon#wrote, iclass 3, count 0 2006.176.07:53:42.16#ibcon#about to read 3, iclass 3, count 0 2006.176.07:53:42.18#ibcon#read 3, iclass 3, count 0 2006.176.07:53:42.18#ibcon#about to read 4, iclass 3, count 0 2006.176.07:53:42.18#ibcon#read 4, iclass 3, count 0 2006.176.07:53:42.18#ibcon#about to read 5, iclass 3, count 0 2006.176.07:53:42.18#ibcon#read 5, iclass 3, count 0 2006.176.07:53:42.18#ibcon#about to read 6, iclass 3, count 0 2006.176.07:53:42.18#ibcon#read 6, iclass 3, count 0 2006.176.07:53:42.18#ibcon#end of sib2, iclass 3, count 0 2006.176.07:53:42.18#ibcon#*after write, iclass 3, count 0 2006.176.07:53:42.18#ibcon#*before return 0, iclass 3, count 0 2006.176.07:53:42.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:42.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.07:53:42.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.07:53:42.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.07:53:42.19$vc4f8/vblo=6,752.99 2006.176.07:53:42.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.07:53:42.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.07:53:42.19#ibcon#ireg 17 cls_cnt 0 2006.176.07:53:42.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:42.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:42.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:42.19#ibcon#enter wrdev, iclass 5, count 0 2006.176.07:53:42.19#ibcon#first serial, iclass 5, count 0 2006.176.07:53:42.19#ibcon#enter sib2, iclass 5, count 0 2006.176.07:53:42.19#ibcon#flushed, iclass 5, count 0 2006.176.07:53:42.19#ibcon#about to write, iclass 5, count 0 2006.176.07:53:42.19#ibcon#wrote, iclass 5, count 0 2006.176.07:53:42.19#ibcon#about to read 3, iclass 5, count 0 2006.176.07:53:42.20#ibcon#read 3, iclass 5, count 0 2006.176.07:53:42.20#ibcon#about to read 4, iclass 5, count 0 2006.176.07:53:42.20#ibcon#read 4, iclass 5, count 0 2006.176.07:53:42.20#ibcon#about to read 5, iclass 5, count 0 2006.176.07:53:42.20#ibcon#read 5, iclass 5, count 0 2006.176.07:53:42.20#ibcon#about to read 6, iclass 5, count 0 2006.176.07:53:42.20#ibcon#read 6, iclass 5, count 0 2006.176.07:53:42.20#ibcon#end of sib2, iclass 5, count 0 2006.176.07:53:42.20#ibcon#*mode == 0, iclass 5, count 0 2006.176.07:53:42.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.07:53:42.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:53:42.20#ibcon#*before write, iclass 5, count 0 2006.176.07:53:42.20#ibcon#enter sib2, iclass 5, count 0 2006.176.07:53:42.20#ibcon#flushed, iclass 5, count 0 2006.176.07:53:42.20#ibcon#about to write, iclass 5, count 0 2006.176.07:53:42.21#ibcon#wrote, iclass 5, count 0 2006.176.07:53:42.21#ibcon#about to read 3, iclass 5, count 0 2006.176.07:53:42.24#ibcon#read 3, iclass 5, count 0 2006.176.07:53:42.24#ibcon#about to read 4, iclass 5, count 0 2006.176.07:53:42.24#ibcon#read 4, iclass 5, count 0 2006.176.07:53:42.24#ibcon#about to read 5, iclass 5, count 0 2006.176.07:53:42.24#ibcon#read 5, iclass 5, count 0 2006.176.07:53:42.24#ibcon#about to read 6, iclass 5, count 0 2006.176.07:53:42.24#ibcon#read 6, iclass 5, count 0 2006.176.07:53:42.24#ibcon#end of sib2, iclass 5, count 0 2006.176.07:53:42.24#ibcon#*after write, iclass 5, count 0 2006.176.07:53:42.24#ibcon#*before return 0, iclass 5, count 0 2006.176.07:53:42.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:42.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.07:53:42.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.07:53:42.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.07:53:42.25$vc4f8/vb=6,4 2006.176.07:53:42.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.07:53:42.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.07:53:42.25#ibcon#ireg 11 cls_cnt 2 2006.176.07:53:42.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:42.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:42.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:42.29#ibcon#enter wrdev, iclass 7, count 2 2006.176.07:53:42.29#ibcon#first serial, iclass 7, count 2 2006.176.07:53:42.29#ibcon#enter sib2, iclass 7, count 2 2006.176.07:53:42.29#ibcon#flushed, iclass 7, count 2 2006.176.07:53:42.29#ibcon#about to write, iclass 7, count 2 2006.176.07:53:42.29#ibcon#wrote, iclass 7, count 2 2006.176.07:53:42.29#ibcon#about to read 3, iclass 7, count 2 2006.176.07:53:42.31#ibcon#read 3, iclass 7, count 2 2006.176.07:53:42.31#ibcon#about to read 4, iclass 7, count 2 2006.176.07:53:42.31#ibcon#read 4, iclass 7, count 2 2006.176.07:53:42.31#ibcon#about to read 5, iclass 7, count 2 2006.176.07:53:42.31#ibcon#read 5, iclass 7, count 2 2006.176.07:53:42.31#ibcon#about to read 6, iclass 7, count 2 2006.176.07:53:42.31#ibcon#read 6, iclass 7, count 2 2006.176.07:53:42.31#ibcon#end of sib2, iclass 7, count 2 2006.176.07:53:42.31#ibcon#*mode == 0, iclass 7, count 2 2006.176.07:53:42.31#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.07:53:42.31#ibcon#[27=AT06-04\r\n] 2006.176.07:53:42.31#ibcon#*before write, iclass 7, count 2 2006.176.07:53:42.31#ibcon#enter sib2, iclass 7, count 2 2006.176.07:53:42.31#ibcon#flushed, iclass 7, count 2 2006.176.07:53:42.31#ibcon#about to write, iclass 7, count 2 2006.176.07:53:42.32#ibcon#wrote, iclass 7, count 2 2006.176.07:53:42.32#ibcon#about to read 3, iclass 7, count 2 2006.176.07:53:42.34#ibcon#read 3, iclass 7, count 2 2006.176.07:53:42.34#ibcon#about to read 4, iclass 7, count 2 2006.176.07:53:42.34#ibcon#read 4, iclass 7, count 2 2006.176.07:53:42.34#ibcon#about to read 5, iclass 7, count 2 2006.176.07:53:42.34#ibcon#read 5, iclass 7, count 2 2006.176.07:53:42.34#ibcon#about to read 6, iclass 7, count 2 2006.176.07:53:42.34#ibcon#read 6, iclass 7, count 2 2006.176.07:53:42.34#ibcon#end of sib2, iclass 7, count 2 2006.176.07:53:42.34#ibcon#*after write, iclass 7, count 2 2006.176.07:53:42.34#ibcon#*before return 0, iclass 7, count 2 2006.176.07:53:42.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:42.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.07:53:42.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.07:53:42.34#ibcon#ireg 7 cls_cnt 0 2006.176.07:53:42.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:42.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:42.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:42.46#ibcon#enter wrdev, iclass 7, count 0 2006.176.07:53:42.46#ibcon#first serial, iclass 7, count 0 2006.176.07:53:42.46#ibcon#enter sib2, iclass 7, count 0 2006.176.07:53:42.46#ibcon#flushed, iclass 7, count 0 2006.176.07:53:42.46#ibcon#about to write, iclass 7, count 0 2006.176.07:53:42.46#ibcon#wrote, iclass 7, count 0 2006.176.07:53:42.46#ibcon#about to read 3, iclass 7, count 0 2006.176.07:53:42.48#ibcon#read 3, iclass 7, count 0 2006.176.07:53:42.48#ibcon#about to read 4, iclass 7, count 0 2006.176.07:53:42.48#ibcon#read 4, iclass 7, count 0 2006.176.07:53:42.48#ibcon#about to read 5, iclass 7, count 0 2006.176.07:53:42.48#ibcon#read 5, iclass 7, count 0 2006.176.07:53:42.48#ibcon#about to read 6, iclass 7, count 0 2006.176.07:53:42.48#ibcon#read 6, iclass 7, count 0 2006.176.07:53:42.48#ibcon#end of sib2, iclass 7, count 0 2006.176.07:53:42.48#ibcon#*mode == 0, iclass 7, count 0 2006.176.07:53:42.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.07:53:42.48#ibcon#[27=USB\r\n] 2006.176.07:53:42.48#ibcon#*before write, iclass 7, count 0 2006.176.07:53:42.48#ibcon#enter sib2, iclass 7, count 0 2006.176.07:53:42.48#ibcon#flushed, iclass 7, count 0 2006.176.07:53:42.48#ibcon#about to write, iclass 7, count 0 2006.176.07:53:42.49#ibcon#wrote, iclass 7, count 0 2006.176.07:53:42.49#ibcon#about to read 3, iclass 7, count 0 2006.176.07:53:42.51#ibcon#read 3, iclass 7, count 0 2006.176.07:53:42.51#ibcon#about to read 4, iclass 7, count 0 2006.176.07:53:42.51#ibcon#read 4, iclass 7, count 0 2006.176.07:53:42.51#ibcon#about to read 5, iclass 7, count 0 2006.176.07:53:42.51#ibcon#read 5, iclass 7, count 0 2006.176.07:53:42.51#ibcon#about to read 6, iclass 7, count 0 2006.176.07:53:42.51#ibcon#read 6, iclass 7, count 0 2006.176.07:53:42.51#ibcon#end of sib2, iclass 7, count 0 2006.176.07:53:42.51#ibcon#*after write, iclass 7, count 0 2006.176.07:53:42.51#ibcon#*before return 0, iclass 7, count 0 2006.176.07:53:42.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:42.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.07:53:42.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.07:53:42.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.07:53:42.52$vc4f8/vabw=wide 2006.176.07:53:42.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.07:53:42.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.07:53:42.52#ibcon#ireg 8 cls_cnt 0 2006.176.07:53:42.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:42.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:42.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:42.52#ibcon#enter wrdev, iclass 11, count 0 2006.176.07:53:42.52#ibcon#first serial, iclass 11, count 0 2006.176.07:53:42.52#ibcon#enter sib2, iclass 11, count 0 2006.176.07:53:42.52#ibcon#flushed, iclass 11, count 0 2006.176.07:53:42.52#ibcon#about to write, iclass 11, count 0 2006.176.07:53:42.52#ibcon#wrote, iclass 11, count 0 2006.176.07:53:42.52#ibcon#about to read 3, iclass 11, count 0 2006.176.07:53:42.53#ibcon#read 3, iclass 11, count 0 2006.176.07:53:42.53#ibcon#about to read 4, iclass 11, count 0 2006.176.07:53:42.53#ibcon#read 4, iclass 11, count 0 2006.176.07:53:42.53#ibcon#about to read 5, iclass 11, count 0 2006.176.07:53:42.53#ibcon#read 5, iclass 11, count 0 2006.176.07:53:42.53#ibcon#about to read 6, iclass 11, count 0 2006.176.07:53:42.53#ibcon#read 6, iclass 11, count 0 2006.176.07:53:42.53#ibcon#end of sib2, iclass 11, count 0 2006.176.07:53:42.53#ibcon#*mode == 0, iclass 11, count 0 2006.176.07:53:42.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.07:53:42.53#ibcon#[25=BW32\r\n] 2006.176.07:53:42.53#ibcon#*before write, iclass 11, count 0 2006.176.07:53:42.53#ibcon#enter sib2, iclass 11, count 0 2006.176.07:53:42.53#ibcon#flushed, iclass 11, count 0 2006.176.07:53:42.53#ibcon#about to write, iclass 11, count 0 2006.176.07:53:42.54#ibcon#wrote, iclass 11, count 0 2006.176.07:53:42.54#ibcon#about to read 3, iclass 11, count 0 2006.176.07:53:42.56#ibcon#read 3, iclass 11, count 0 2006.176.07:53:42.56#ibcon#about to read 4, iclass 11, count 0 2006.176.07:53:42.56#ibcon#read 4, iclass 11, count 0 2006.176.07:53:42.56#ibcon#about to read 5, iclass 11, count 0 2006.176.07:53:42.56#ibcon#read 5, iclass 11, count 0 2006.176.07:53:42.56#ibcon#about to read 6, iclass 11, count 0 2006.176.07:53:42.56#ibcon#read 6, iclass 11, count 0 2006.176.07:53:42.56#ibcon#end of sib2, iclass 11, count 0 2006.176.07:53:42.56#ibcon#*after write, iclass 11, count 0 2006.176.07:53:42.56#ibcon#*before return 0, iclass 11, count 0 2006.176.07:53:42.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:42.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.07:53:42.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.07:53:42.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.07:53:42.57$vc4f8/vbbw=wide 2006.176.07:53:42.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.07:53:42.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.07:53:42.57#ibcon#ireg 8 cls_cnt 0 2006.176.07:53:42.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:53:42.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:53:42.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:53:42.62#ibcon#enter wrdev, iclass 13, count 0 2006.176.07:53:42.62#ibcon#first serial, iclass 13, count 0 2006.176.07:53:42.62#ibcon#enter sib2, iclass 13, count 0 2006.176.07:53:42.62#ibcon#flushed, iclass 13, count 0 2006.176.07:53:42.62#ibcon#about to write, iclass 13, count 0 2006.176.07:53:42.62#ibcon#wrote, iclass 13, count 0 2006.176.07:53:42.62#ibcon#about to read 3, iclass 13, count 0 2006.176.07:53:42.64#ibcon#read 3, iclass 13, count 0 2006.176.07:53:42.64#ibcon#about to read 4, iclass 13, count 0 2006.176.07:53:42.64#ibcon#read 4, iclass 13, count 0 2006.176.07:53:42.64#ibcon#about to read 5, iclass 13, count 0 2006.176.07:53:42.64#ibcon#read 5, iclass 13, count 0 2006.176.07:53:42.64#ibcon#about to read 6, iclass 13, count 0 2006.176.07:53:42.64#ibcon#read 6, iclass 13, count 0 2006.176.07:53:42.64#ibcon#end of sib2, iclass 13, count 0 2006.176.07:53:42.64#ibcon#*mode == 0, iclass 13, count 0 2006.176.07:53:42.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.07:53:42.64#ibcon#[27=BW32\r\n] 2006.176.07:53:42.64#ibcon#*before write, iclass 13, count 0 2006.176.07:53:42.64#ibcon#enter sib2, iclass 13, count 0 2006.176.07:53:42.64#ibcon#flushed, iclass 13, count 0 2006.176.07:53:42.65#ibcon#about to write, iclass 13, count 0 2006.176.07:53:42.65#ibcon#wrote, iclass 13, count 0 2006.176.07:53:42.65#ibcon#about to read 3, iclass 13, count 0 2006.176.07:53:42.67#ibcon#read 3, iclass 13, count 0 2006.176.07:53:42.67#ibcon#about to read 4, iclass 13, count 0 2006.176.07:53:42.67#ibcon#read 4, iclass 13, count 0 2006.176.07:53:42.67#ibcon#about to read 5, iclass 13, count 0 2006.176.07:53:42.67#ibcon#read 5, iclass 13, count 0 2006.176.07:53:42.67#ibcon#about to read 6, iclass 13, count 0 2006.176.07:53:42.67#ibcon#read 6, iclass 13, count 0 2006.176.07:53:42.67#ibcon#end of sib2, iclass 13, count 0 2006.176.07:53:42.67#ibcon#*after write, iclass 13, count 0 2006.176.07:53:42.67#ibcon#*before return 0, iclass 13, count 0 2006.176.07:53:42.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:53:42.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.07:53:42.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.07:53:42.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.07:53:42.68$4f8m12a/ifd4f 2006.176.07:53:42.68$ifd4f/lo= 2006.176.07:53:42.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:53:42.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:53:42.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:53:42.68$ifd4f/patch= 2006.176.07:53:42.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:53:42.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:53:42.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:53:42.68$4f8m12a/"form=m,16.000,1:2 2006.176.07:53:42.68$4f8m12a/"tpicd 2006.176.07:53:42.68$4f8m12a/echo=off 2006.176.07:53:42.68$4f8m12a/xlog=off 2006.176.07:53:42.68:!2006.176.07:55:10 2006.176.07:53:42.71#abcon#<5=/05 3.3 5.5 23.86 911008.4\r\n> 2006.176.07:53:47.14#trakl#Source acquired 2006.176.07:53:49.15#flagr#flagr/antenna,acquired 2006.176.07:55:10.02:preob 2006.176.07:55:11.15/onsource/TRACKING 2006.176.07:55:11.15:!2006.176.07:55:20 2006.176.07:55:20.01:data_valid=on 2006.176.07:55:20.02:midob 2006.176.07:55:21.14/onsource/TRACKING 2006.176.07:55:21.15/wx/23.86,1008.5,91 2006.176.07:55:21.33/cable/+6.4950E-03 2006.176.07:55:22.42/va/01,08,usb,yes,30,32 2006.176.07:55:22.42/va/02,07,usb,yes,30,32 2006.176.07:55:22.42/va/03,06,usb,yes,32,32 2006.176.07:55:22.42/va/04,07,usb,yes,31,33 2006.176.07:55:22.42/va/05,07,usb,yes,33,34 2006.176.07:55:22.42/va/06,06,usb,yes,32,32 2006.176.07:55:22.42/va/07,06,usb,yes,32,32 2006.176.07:55:22.42/va/08,06,usb,yes,35,34 2006.176.07:55:22.65/valo/01,532.99,yes,locked 2006.176.07:55:22.65/valo/02,572.99,yes,locked 2006.176.07:55:22.65/valo/03,672.99,yes,locked 2006.176.07:55:22.65/valo/04,832.99,yes,locked 2006.176.07:55:22.65/valo/05,652.99,yes,locked 2006.176.07:55:22.65/valo/06,772.99,yes,locked 2006.176.07:55:22.65/valo/07,832.99,yes,locked 2006.176.07:55:22.65/valo/08,852.99,yes,locked 2006.176.07:55:23.74/vb/01,04,usb,yes,30,28 2006.176.07:55:23.74/vb/02,04,usb,yes,32,33 2006.176.07:55:23.74/vb/03,04,usb,yes,28,32 2006.176.07:55:23.74/vb/04,04,usb,yes,29,29 2006.176.07:55:23.74/vb/05,04,usb,yes,27,31 2006.176.07:55:23.74/vb/06,04,usb,yes,28,31 2006.176.07:55:23.74/vb/07,04,usb,yes,30,30 2006.176.07:55:23.74/vb/08,04,usb,yes,28,31 2006.176.07:55:23.97/vblo/01,632.99,yes,locked 2006.176.07:55:23.97/vblo/02,640.99,yes,locked 2006.176.07:55:23.97/vblo/03,656.99,yes,locked 2006.176.07:55:23.97/vblo/04,712.99,yes,locked 2006.176.07:55:23.97/vblo/05,744.99,yes,locked 2006.176.07:55:23.97/vblo/06,752.99,yes,locked 2006.176.07:55:23.97/vblo/07,734.99,yes,locked 2006.176.07:55:23.97/vblo/08,744.99,yes,locked 2006.176.07:55:24.12/vabw/8 2006.176.07:55:24.27/vbbw/8 2006.176.07:55:24.36/xfe/off,on,15.0 2006.176.07:55:24.75/ifatt/23,28,28,28 2006.176.07:55:25.07/fmout-gps/S +3.75E-07 2006.176.07:55:25.12:!2006.176.07:56:20 2006.176.07:56:20.01:data_valid=off 2006.176.07:56:20.02:postob 2006.176.07:56:20.16/cable/+6.4937E-03 2006.176.07:56:20.17/wx/23.86,1008.5,92 2006.176.07:56:21.07/fmout-gps/S +3.76E-07 2006.176.07:56:21.08:scan_name=176-0758,k06176,60 2006.176.07:56:21.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.176.07:56:22.14#flagr#flagr/antenna,new-source 2006.176.07:56:22.15:checkk5 2006.176.07:56:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:56:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:56:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:56:23.73/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:56:24.11/chk_obsdata//k5ts1/T1760755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:56:24.48/chk_obsdata//k5ts2/T1760755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:56:24.85/chk_obsdata//k5ts3/T1760755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:56:25.22/chk_obsdata//k5ts4/T1760755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:56:25.91/k5log//k5ts1_log_newline 2006.176.07:56:26.60/k5log//k5ts2_log_newline 2006.176.07:56:27.29/k5log//k5ts3_log_newline 2006.176.07:56:27.98/k5log//k5ts4_log_newline 2006.176.07:56:28.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:56:28.01:4f8m12a=2 2006.176.07:56:28.01$4f8m12a/echo=on 2006.176.07:56:28.01$4f8m12a/pcalon 2006.176.07:56:28.01$pcalon/"no phase cal control is implemented here 2006.176.07:56:28.01$4f8m12a/"tpicd=stop 2006.176.07:56:28.01$4f8m12a/vc4f8 2006.176.07:56:28.01$vc4f8/valo=1,532.99 2006.176.07:56:28.01#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.07:56:28.01#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.07:56:28.01#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:28.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:28.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:28.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:28.01#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:56:28.01#ibcon#first serial, iclass 12, count 0 2006.176.07:56:28.01#ibcon#enter sib2, iclass 12, count 0 2006.176.07:56:28.01#ibcon#flushed, iclass 12, count 0 2006.176.07:56:28.01#ibcon#about to write, iclass 12, count 0 2006.176.07:56:28.01#ibcon#wrote, iclass 12, count 0 2006.176.07:56:28.01#ibcon#about to read 3, iclass 12, count 0 2006.176.07:56:28.05#ibcon#read 3, iclass 12, count 0 2006.176.07:56:28.05#ibcon#about to read 4, iclass 12, count 0 2006.176.07:56:28.05#ibcon#read 4, iclass 12, count 0 2006.176.07:56:28.05#ibcon#about to read 5, iclass 12, count 0 2006.176.07:56:28.05#ibcon#read 5, iclass 12, count 0 2006.176.07:56:28.05#ibcon#about to read 6, iclass 12, count 0 2006.176.07:56:28.05#ibcon#read 6, iclass 12, count 0 2006.176.07:56:28.05#ibcon#end of sib2, iclass 12, count 0 2006.176.07:56:28.05#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:56:28.05#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:56:28.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:56:28.05#ibcon#*before write, iclass 12, count 0 2006.176.07:56:28.05#ibcon#enter sib2, iclass 12, count 0 2006.176.07:56:28.05#ibcon#flushed, iclass 12, count 0 2006.176.07:56:28.05#ibcon#about to write, iclass 12, count 0 2006.176.07:56:28.05#ibcon#wrote, iclass 12, count 0 2006.176.07:56:28.05#ibcon#about to read 3, iclass 12, count 0 2006.176.07:56:28.09#ibcon#read 3, iclass 12, count 0 2006.176.07:56:28.09#ibcon#about to read 4, iclass 12, count 0 2006.176.07:56:28.09#ibcon#read 4, iclass 12, count 0 2006.176.07:56:28.09#ibcon#about to read 5, iclass 12, count 0 2006.176.07:56:28.09#ibcon#read 5, iclass 12, count 0 2006.176.07:56:28.09#ibcon#about to read 6, iclass 12, count 0 2006.176.07:56:28.09#ibcon#read 6, iclass 12, count 0 2006.176.07:56:28.09#ibcon#end of sib2, iclass 12, count 0 2006.176.07:56:28.09#ibcon#*after write, iclass 12, count 0 2006.176.07:56:28.09#ibcon#*before return 0, iclass 12, count 0 2006.176.07:56:28.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:28.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:28.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:56:28.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:56:28.09$vc4f8/va=1,8 2006.176.07:56:28.09#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.07:56:28.09#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.07:56:28.09#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:28.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:28.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:28.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:28.09#ibcon#enter wrdev, iclass 14, count 2 2006.176.07:56:28.09#ibcon#first serial, iclass 14, count 2 2006.176.07:56:28.09#ibcon#enter sib2, iclass 14, count 2 2006.176.07:56:28.09#ibcon#flushed, iclass 14, count 2 2006.176.07:56:28.09#ibcon#about to write, iclass 14, count 2 2006.176.07:56:28.09#ibcon#wrote, iclass 14, count 2 2006.176.07:56:28.09#ibcon#about to read 3, iclass 14, count 2 2006.176.07:56:28.12#ibcon#read 3, iclass 14, count 2 2006.176.07:56:28.12#ibcon#about to read 4, iclass 14, count 2 2006.176.07:56:28.12#ibcon#read 4, iclass 14, count 2 2006.176.07:56:28.12#ibcon#about to read 5, iclass 14, count 2 2006.176.07:56:28.12#ibcon#read 5, iclass 14, count 2 2006.176.07:56:28.12#ibcon#about to read 6, iclass 14, count 2 2006.176.07:56:28.12#ibcon#read 6, iclass 14, count 2 2006.176.07:56:28.12#ibcon#end of sib2, iclass 14, count 2 2006.176.07:56:28.12#ibcon#*mode == 0, iclass 14, count 2 2006.176.07:56:28.12#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.07:56:28.12#ibcon#[25=AT01-08\r\n] 2006.176.07:56:28.12#ibcon#*before write, iclass 14, count 2 2006.176.07:56:28.12#ibcon#enter sib2, iclass 14, count 2 2006.176.07:56:28.12#ibcon#flushed, iclass 14, count 2 2006.176.07:56:28.12#ibcon#about to write, iclass 14, count 2 2006.176.07:56:28.12#ibcon#wrote, iclass 14, count 2 2006.176.07:56:28.12#ibcon#about to read 3, iclass 14, count 2 2006.176.07:56:28.15#ibcon#read 3, iclass 14, count 2 2006.176.07:56:28.15#ibcon#about to read 4, iclass 14, count 2 2006.176.07:56:28.15#ibcon#read 4, iclass 14, count 2 2006.176.07:56:28.15#ibcon#about to read 5, iclass 14, count 2 2006.176.07:56:28.15#ibcon#read 5, iclass 14, count 2 2006.176.07:56:28.15#ibcon#about to read 6, iclass 14, count 2 2006.176.07:56:28.15#ibcon#read 6, iclass 14, count 2 2006.176.07:56:28.15#ibcon#end of sib2, iclass 14, count 2 2006.176.07:56:28.15#ibcon#*after write, iclass 14, count 2 2006.176.07:56:28.15#ibcon#*before return 0, iclass 14, count 2 2006.176.07:56:28.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:28.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:28.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.07:56:28.15#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:28.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:28.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:28.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:28.27#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:56:28.27#ibcon#first serial, iclass 14, count 0 2006.176.07:56:28.27#ibcon#enter sib2, iclass 14, count 0 2006.176.07:56:28.27#ibcon#flushed, iclass 14, count 0 2006.176.07:56:28.27#ibcon#about to write, iclass 14, count 0 2006.176.07:56:28.27#ibcon#wrote, iclass 14, count 0 2006.176.07:56:28.27#ibcon#about to read 3, iclass 14, count 0 2006.176.07:56:28.29#ibcon#read 3, iclass 14, count 0 2006.176.07:56:28.29#ibcon#about to read 4, iclass 14, count 0 2006.176.07:56:28.29#ibcon#read 4, iclass 14, count 0 2006.176.07:56:28.29#ibcon#about to read 5, iclass 14, count 0 2006.176.07:56:28.29#ibcon#read 5, iclass 14, count 0 2006.176.07:56:28.29#ibcon#about to read 6, iclass 14, count 0 2006.176.07:56:28.29#ibcon#read 6, iclass 14, count 0 2006.176.07:56:28.29#ibcon#end of sib2, iclass 14, count 0 2006.176.07:56:28.29#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:56:28.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:56:28.29#ibcon#[25=USB\r\n] 2006.176.07:56:28.29#ibcon#*before write, iclass 14, count 0 2006.176.07:56:28.29#ibcon#enter sib2, iclass 14, count 0 2006.176.07:56:28.29#ibcon#flushed, iclass 14, count 0 2006.176.07:56:28.29#ibcon#about to write, iclass 14, count 0 2006.176.07:56:28.29#ibcon#wrote, iclass 14, count 0 2006.176.07:56:28.29#ibcon#about to read 3, iclass 14, count 0 2006.176.07:56:28.32#ibcon#read 3, iclass 14, count 0 2006.176.07:56:28.32#ibcon#about to read 4, iclass 14, count 0 2006.176.07:56:28.32#ibcon#read 4, iclass 14, count 0 2006.176.07:56:28.32#ibcon#about to read 5, iclass 14, count 0 2006.176.07:56:28.32#ibcon#read 5, iclass 14, count 0 2006.176.07:56:28.32#ibcon#about to read 6, iclass 14, count 0 2006.176.07:56:28.32#ibcon#read 6, iclass 14, count 0 2006.176.07:56:28.32#ibcon#end of sib2, iclass 14, count 0 2006.176.07:56:28.32#ibcon#*after write, iclass 14, count 0 2006.176.07:56:28.32#ibcon#*before return 0, iclass 14, count 0 2006.176.07:56:28.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:28.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:28.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:56:28.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:56:28.32$vc4f8/valo=2,572.99 2006.176.07:56:28.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:56:28.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:56:28.32#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:28.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:28.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:28.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:28.32#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:56:28.32#ibcon#first serial, iclass 16, count 0 2006.176.07:56:28.32#ibcon#enter sib2, iclass 16, count 0 2006.176.07:56:28.32#ibcon#flushed, iclass 16, count 0 2006.176.07:56:28.32#ibcon#about to write, iclass 16, count 0 2006.176.07:56:28.32#ibcon#wrote, iclass 16, count 0 2006.176.07:56:28.32#ibcon#about to read 3, iclass 16, count 0 2006.176.07:56:28.34#ibcon#read 3, iclass 16, count 0 2006.176.07:56:28.34#ibcon#about to read 4, iclass 16, count 0 2006.176.07:56:28.34#ibcon#read 4, iclass 16, count 0 2006.176.07:56:28.34#ibcon#about to read 5, iclass 16, count 0 2006.176.07:56:28.34#ibcon#read 5, iclass 16, count 0 2006.176.07:56:28.34#ibcon#about to read 6, iclass 16, count 0 2006.176.07:56:28.34#ibcon#read 6, iclass 16, count 0 2006.176.07:56:28.34#ibcon#end of sib2, iclass 16, count 0 2006.176.07:56:28.34#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:56:28.34#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:56:28.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:56:28.34#ibcon#*before write, iclass 16, count 0 2006.176.07:56:28.34#ibcon#enter sib2, iclass 16, count 0 2006.176.07:56:28.34#ibcon#flushed, iclass 16, count 0 2006.176.07:56:28.34#ibcon#about to write, iclass 16, count 0 2006.176.07:56:28.34#ibcon#wrote, iclass 16, count 0 2006.176.07:56:28.34#ibcon#about to read 3, iclass 16, count 0 2006.176.07:56:28.38#ibcon#read 3, iclass 16, count 0 2006.176.07:56:28.38#ibcon#about to read 4, iclass 16, count 0 2006.176.07:56:28.38#ibcon#read 4, iclass 16, count 0 2006.176.07:56:28.38#ibcon#about to read 5, iclass 16, count 0 2006.176.07:56:28.38#ibcon#read 5, iclass 16, count 0 2006.176.07:56:28.38#ibcon#about to read 6, iclass 16, count 0 2006.176.07:56:28.38#ibcon#read 6, iclass 16, count 0 2006.176.07:56:28.38#ibcon#end of sib2, iclass 16, count 0 2006.176.07:56:28.38#ibcon#*after write, iclass 16, count 0 2006.176.07:56:28.38#ibcon#*before return 0, iclass 16, count 0 2006.176.07:56:28.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:28.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:28.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:56:28.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:56:28.38$vc4f8/va=2,7 2006.176.07:56:28.38#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.07:56:28.38#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.07:56:28.38#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:28.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:28.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:28.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:28.44#ibcon#enter wrdev, iclass 18, count 2 2006.176.07:56:28.44#ibcon#first serial, iclass 18, count 2 2006.176.07:56:28.44#ibcon#enter sib2, iclass 18, count 2 2006.176.07:56:28.44#ibcon#flushed, iclass 18, count 2 2006.176.07:56:28.44#ibcon#about to write, iclass 18, count 2 2006.176.07:56:28.44#ibcon#wrote, iclass 18, count 2 2006.176.07:56:28.44#ibcon#about to read 3, iclass 18, count 2 2006.176.07:56:28.47#ibcon#read 3, iclass 18, count 2 2006.176.07:56:28.47#ibcon#about to read 4, iclass 18, count 2 2006.176.07:56:28.47#ibcon#read 4, iclass 18, count 2 2006.176.07:56:28.47#ibcon#about to read 5, iclass 18, count 2 2006.176.07:56:28.47#ibcon#read 5, iclass 18, count 2 2006.176.07:56:28.47#ibcon#about to read 6, iclass 18, count 2 2006.176.07:56:28.47#ibcon#read 6, iclass 18, count 2 2006.176.07:56:28.47#ibcon#end of sib2, iclass 18, count 2 2006.176.07:56:28.47#ibcon#*mode == 0, iclass 18, count 2 2006.176.07:56:28.47#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.07:56:28.47#ibcon#[25=AT02-07\r\n] 2006.176.07:56:28.47#ibcon#*before write, iclass 18, count 2 2006.176.07:56:28.47#ibcon#enter sib2, iclass 18, count 2 2006.176.07:56:28.47#ibcon#flushed, iclass 18, count 2 2006.176.07:56:28.47#ibcon#about to write, iclass 18, count 2 2006.176.07:56:28.47#ibcon#wrote, iclass 18, count 2 2006.176.07:56:28.47#ibcon#about to read 3, iclass 18, count 2 2006.176.07:56:28.49#ibcon#read 3, iclass 18, count 2 2006.176.07:56:28.49#ibcon#about to read 4, iclass 18, count 2 2006.176.07:56:28.49#ibcon#read 4, iclass 18, count 2 2006.176.07:56:28.49#ibcon#about to read 5, iclass 18, count 2 2006.176.07:56:28.49#ibcon#read 5, iclass 18, count 2 2006.176.07:56:28.49#ibcon#about to read 6, iclass 18, count 2 2006.176.07:56:28.49#ibcon#read 6, iclass 18, count 2 2006.176.07:56:28.49#ibcon#end of sib2, iclass 18, count 2 2006.176.07:56:28.49#ibcon#*after write, iclass 18, count 2 2006.176.07:56:28.49#ibcon#*before return 0, iclass 18, count 2 2006.176.07:56:28.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:28.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:28.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.07:56:28.49#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:28.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:28.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:28.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:28.61#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:56:28.61#ibcon#first serial, iclass 18, count 0 2006.176.07:56:28.61#ibcon#enter sib2, iclass 18, count 0 2006.176.07:56:28.61#ibcon#flushed, iclass 18, count 0 2006.176.07:56:28.61#ibcon#about to write, iclass 18, count 0 2006.176.07:56:28.61#ibcon#wrote, iclass 18, count 0 2006.176.07:56:28.61#ibcon#about to read 3, iclass 18, count 0 2006.176.07:56:28.63#ibcon#read 3, iclass 18, count 0 2006.176.07:56:28.63#ibcon#about to read 4, iclass 18, count 0 2006.176.07:56:28.63#ibcon#read 4, iclass 18, count 0 2006.176.07:56:28.63#ibcon#about to read 5, iclass 18, count 0 2006.176.07:56:28.63#ibcon#read 5, iclass 18, count 0 2006.176.07:56:28.63#ibcon#about to read 6, iclass 18, count 0 2006.176.07:56:28.63#ibcon#read 6, iclass 18, count 0 2006.176.07:56:28.63#ibcon#end of sib2, iclass 18, count 0 2006.176.07:56:28.63#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:56:28.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:56:28.63#ibcon#[25=USB\r\n] 2006.176.07:56:28.63#ibcon#*before write, iclass 18, count 0 2006.176.07:56:28.63#ibcon#enter sib2, iclass 18, count 0 2006.176.07:56:28.63#ibcon#flushed, iclass 18, count 0 2006.176.07:56:28.63#ibcon#about to write, iclass 18, count 0 2006.176.07:56:28.63#ibcon#wrote, iclass 18, count 0 2006.176.07:56:28.63#ibcon#about to read 3, iclass 18, count 0 2006.176.07:56:28.66#ibcon#read 3, iclass 18, count 0 2006.176.07:56:28.66#ibcon#about to read 4, iclass 18, count 0 2006.176.07:56:28.66#ibcon#read 4, iclass 18, count 0 2006.176.07:56:28.66#ibcon#about to read 5, iclass 18, count 0 2006.176.07:56:28.66#ibcon#read 5, iclass 18, count 0 2006.176.07:56:28.66#ibcon#about to read 6, iclass 18, count 0 2006.176.07:56:28.66#ibcon#read 6, iclass 18, count 0 2006.176.07:56:28.66#ibcon#end of sib2, iclass 18, count 0 2006.176.07:56:28.66#ibcon#*after write, iclass 18, count 0 2006.176.07:56:28.66#ibcon#*before return 0, iclass 18, count 0 2006.176.07:56:28.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:28.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:28.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:56:28.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:56:28.66$vc4f8/valo=3,672.99 2006.176.07:56:28.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.07:56:28.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.07:56:28.66#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:28.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:28.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:28.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:28.66#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:56:28.66#ibcon#first serial, iclass 20, count 0 2006.176.07:56:28.66#ibcon#enter sib2, iclass 20, count 0 2006.176.07:56:28.66#ibcon#flushed, iclass 20, count 0 2006.176.07:56:28.66#ibcon#about to write, iclass 20, count 0 2006.176.07:56:28.66#ibcon#wrote, iclass 20, count 0 2006.176.07:56:28.66#ibcon#about to read 3, iclass 20, count 0 2006.176.07:56:28.68#ibcon#read 3, iclass 20, count 0 2006.176.07:56:28.68#ibcon#about to read 4, iclass 20, count 0 2006.176.07:56:28.68#ibcon#read 4, iclass 20, count 0 2006.176.07:56:28.68#ibcon#about to read 5, iclass 20, count 0 2006.176.07:56:28.68#ibcon#read 5, iclass 20, count 0 2006.176.07:56:28.68#ibcon#about to read 6, iclass 20, count 0 2006.176.07:56:28.68#ibcon#read 6, iclass 20, count 0 2006.176.07:56:28.68#ibcon#end of sib2, iclass 20, count 0 2006.176.07:56:28.68#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:56:28.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:56:28.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:56:28.68#ibcon#*before write, iclass 20, count 0 2006.176.07:56:28.68#ibcon#enter sib2, iclass 20, count 0 2006.176.07:56:28.68#ibcon#flushed, iclass 20, count 0 2006.176.07:56:28.68#ibcon#about to write, iclass 20, count 0 2006.176.07:56:28.68#ibcon#wrote, iclass 20, count 0 2006.176.07:56:28.68#ibcon#about to read 3, iclass 20, count 0 2006.176.07:56:28.72#ibcon#read 3, iclass 20, count 0 2006.176.07:56:28.72#ibcon#about to read 4, iclass 20, count 0 2006.176.07:56:28.72#ibcon#read 4, iclass 20, count 0 2006.176.07:56:28.72#ibcon#about to read 5, iclass 20, count 0 2006.176.07:56:28.72#ibcon#read 5, iclass 20, count 0 2006.176.07:56:28.72#ibcon#about to read 6, iclass 20, count 0 2006.176.07:56:28.72#ibcon#read 6, iclass 20, count 0 2006.176.07:56:28.72#ibcon#end of sib2, iclass 20, count 0 2006.176.07:56:28.72#ibcon#*after write, iclass 20, count 0 2006.176.07:56:28.72#ibcon#*before return 0, iclass 20, count 0 2006.176.07:56:28.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:28.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:28.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:56:28.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:56:28.72$vc4f8/va=3,6 2006.176.07:56:28.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.07:56:28.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.07:56:28.72#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:28.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:28.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:28.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:28.78#ibcon#enter wrdev, iclass 22, count 2 2006.176.07:56:28.78#ibcon#first serial, iclass 22, count 2 2006.176.07:56:28.78#ibcon#enter sib2, iclass 22, count 2 2006.176.07:56:28.78#ibcon#flushed, iclass 22, count 2 2006.176.07:56:28.78#ibcon#about to write, iclass 22, count 2 2006.176.07:56:28.78#ibcon#wrote, iclass 22, count 2 2006.176.07:56:28.78#ibcon#about to read 3, iclass 22, count 2 2006.176.07:56:28.81#ibcon#read 3, iclass 22, count 2 2006.176.07:56:28.81#ibcon#about to read 4, iclass 22, count 2 2006.176.07:56:28.81#ibcon#read 4, iclass 22, count 2 2006.176.07:56:28.81#ibcon#about to read 5, iclass 22, count 2 2006.176.07:56:28.81#ibcon#read 5, iclass 22, count 2 2006.176.07:56:28.81#ibcon#about to read 6, iclass 22, count 2 2006.176.07:56:28.81#ibcon#read 6, iclass 22, count 2 2006.176.07:56:28.81#ibcon#end of sib2, iclass 22, count 2 2006.176.07:56:28.81#ibcon#*mode == 0, iclass 22, count 2 2006.176.07:56:28.81#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.07:56:28.81#ibcon#[25=AT03-06\r\n] 2006.176.07:56:28.81#ibcon#*before write, iclass 22, count 2 2006.176.07:56:28.81#ibcon#enter sib2, iclass 22, count 2 2006.176.07:56:28.81#ibcon#flushed, iclass 22, count 2 2006.176.07:56:28.81#ibcon#about to write, iclass 22, count 2 2006.176.07:56:28.81#ibcon#wrote, iclass 22, count 2 2006.176.07:56:28.81#ibcon#about to read 3, iclass 22, count 2 2006.176.07:56:28.83#ibcon#read 3, iclass 22, count 2 2006.176.07:56:28.83#ibcon#about to read 4, iclass 22, count 2 2006.176.07:56:28.83#ibcon#read 4, iclass 22, count 2 2006.176.07:56:28.83#ibcon#about to read 5, iclass 22, count 2 2006.176.07:56:28.83#ibcon#read 5, iclass 22, count 2 2006.176.07:56:28.83#ibcon#about to read 6, iclass 22, count 2 2006.176.07:56:28.83#ibcon#read 6, iclass 22, count 2 2006.176.07:56:28.83#ibcon#end of sib2, iclass 22, count 2 2006.176.07:56:28.83#ibcon#*after write, iclass 22, count 2 2006.176.07:56:28.83#ibcon#*before return 0, iclass 22, count 2 2006.176.07:56:28.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:28.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:28.83#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.07:56:28.83#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:28.83#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:28.95#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:28.95#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:28.95#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:56:28.95#ibcon#first serial, iclass 22, count 0 2006.176.07:56:28.95#ibcon#enter sib2, iclass 22, count 0 2006.176.07:56:28.95#ibcon#flushed, iclass 22, count 0 2006.176.07:56:28.95#ibcon#about to write, iclass 22, count 0 2006.176.07:56:28.95#ibcon#wrote, iclass 22, count 0 2006.176.07:56:28.95#ibcon#about to read 3, iclass 22, count 0 2006.176.07:56:28.97#ibcon#read 3, iclass 22, count 0 2006.176.07:56:28.97#ibcon#about to read 4, iclass 22, count 0 2006.176.07:56:28.97#ibcon#read 4, iclass 22, count 0 2006.176.07:56:28.97#ibcon#about to read 5, iclass 22, count 0 2006.176.07:56:28.97#ibcon#read 5, iclass 22, count 0 2006.176.07:56:28.97#ibcon#about to read 6, iclass 22, count 0 2006.176.07:56:28.97#ibcon#read 6, iclass 22, count 0 2006.176.07:56:28.97#ibcon#end of sib2, iclass 22, count 0 2006.176.07:56:28.97#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:56:28.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:56:28.97#ibcon#[25=USB\r\n] 2006.176.07:56:28.97#ibcon#*before write, iclass 22, count 0 2006.176.07:56:28.97#ibcon#enter sib2, iclass 22, count 0 2006.176.07:56:28.97#ibcon#flushed, iclass 22, count 0 2006.176.07:56:28.97#ibcon#about to write, iclass 22, count 0 2006.176.07:56:28.97#ibcon#wrote, iclass 22, count 0 2006.176.07:56:28.97#ibcon#about to read 3, iclass 22, count 0 2006.176.07:56:29.00#ibcon#read 3, iclass 22, count 0 2006.176.07:56:29.00#ibcon#about to read 4, iclass 22, count 0 2006.176.07:56:29.00#ibcon#read 4, iclass 22, count 0 2006.176.07:56:29.00#ibcon#about to read 5, iclass 22, count 0 2006.176.07:56:29.00#ibcon#read 5, iclass 22, count 0 2006.176.07:56:29.00#ibcon#about to read 6, iclass 22, count 0 2006.176.07:56:29.00#ibcon#read 6, iclass 22, count 0 2006.176.07:56:29.00#ibcon#end of sib2, iclass 22, count 0 2006.176.07:56:29.00#ibcon#*after write, iclass 22, count 0 2006.176.07:56:29.00#ibcon#*before return 0, iclass 22, count 0 2006.176.07:56:29.00#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:29.00#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:29.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:56:29.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:56:29.00$vc4f8/valo=4,832.99 2006.176.07:56:29.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.07:56:29.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.07:56:29.00#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:29.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:29.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:29.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:29.00#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:56:29.00#ibcon#first serial, iclass 24, count 0 2006.176.07:56:29.00#ibcon#enter sib2, iclass 24, count 0 2006.176.07:56:29.00#ibcon#flushed, iclass 24, count 0 2006.176.07:56:29.00#ibcon#about to write, iclass 24, count 0 2006.176.07:56:29.00#ibcon#wrote, iclass 24, count 0 2006.176.07:56:29.00#ibcon#about to read 3, iclass 24, count 0 2006.176.07:56:29.02#ibcon#read 3, iclass 24, count 0 2006.176.07:56:29.02#ibcon#about to read 4, iclass 24, count 0 2006.176.07:56:29.02#ibcon#read 4, iclass 24, count 0 2006.176.07:56:29.02#ibcon#about to read 5, iclass 24, count 0 2006.176.07:56:29.02#ibcon#read 5, iclass 24, count 0 2006.176.07:56:29.02#ibcon#about to read 6, iclass 24, count 0 2006.176.07:56:29.02#ibcon#read 6, iclass 24, count 0 2006.176.07:56:29.02#ibcon#end of sib2, iclass 24, count 0 2006.176.07:56:29.02#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:56:29.02#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:56:29.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:56:29.02#ibcon#*before write, iclass 24, count 0 2006.176.07:56:29.02#ibcon#enter sib2, iclass 24, count 0 2006.176.07:56:29.02#ibcon#flushed, iclass 24, count 0 2006.176.07:56:29.02#ibcon#about to write, iclass 24, count 0 2006.176.07:56:29.02#ibcon#wrote, iclass 24, count 0 2006.176.07:56:29.02#ibcon#about to read 3, iclass 24, count 0 2006.176.07:56:29.06#ibcon#read 3, iclass 24, count 0 2006.176.07:56:29.06#ibcon#about to read 4, iclass 24, count 0 2006.176.07:56:29.06#ibcon#read 4, iclass 24, count 0 2006.176.07:56:29.06#ibcon#about to read 5, iclass 24, count 0 2006.176.07:56:29.06#ibcon#read 5, iclass 24, count 0 2006.176.07:56:29.06#ibcon#about to read 6, iclass 24, count 0 2006.176.07:56:29.06#ibcon#read 6, iclass 24, count 0 2006.176.07:56:29.06#ibcon#end of sib2, iclass 24, count 0 2006.176.07:56:29.06#ibcon#*after write, iclass 24, count 0 2006.176.07:56:29.06#ibcon#*before return 0, iclass 24, count 0 2006.176.07:56:29.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:29.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:29.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:56:29.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:56:29.06$vc4f8/va=4,7 2006.176.07:56:29.06#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.07:56:29.06#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.07:56:29.06#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:29.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:29.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:29.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:29.12#ibcon#enter wrdev, iclass 26, count 2 2006.176.07:56:29.12#ibcon#first serial, iclass 26, count 2 2006.176.07:56:29.12#ibcon#enter sib2, iclass 26, count 2 2006.176.07:56:29.12#ibcon#flushed, iclass 26, count 2 2006.176.07:56:29.12#ibcon#about to write, iclass 26, count 2 2006.176.07:56:29.12#ibcon#wrote, iclass 26, count 2 2006.176.07:56:29.12#ibcon#about to read 3, iclass 26, count 2 2006.176.07:56:29.14#ibcon#read 3, iclass 26, count 2 2006.176.07:56:29.14#ibcon#about to read 4, iclass 26, count 2 2006.176.07:56:29.14#ibcon#read 4, iclass 26, count 2 2006.176.07:56:29.14#ibcon#about to read 5, iclass 26, count 2 2006.176.07:56:29.14#ibcon#read 5, iclass 26, count 2 2006.176.07:56:29.14#ibcon#about to read 6, iclass 26, count 2 2006.176.07:56:29.14#ibcon#read 6, iclass 26, count 2 2006.176.07:56:29.14#ibcon#end of sib2, iclass 26, count 2 2006.176.07:56:29.14#ibcon#*mode == 0, iclass 26, count 2 2006.176.07:56:29.14#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.07:56:29.14#ibcon#[25=AT04-07\r\n] 2006.176.07:56:29.14#ibcon#*before write, iclass 26, count 2 2006.176.07:56:29.14#ibcon#enter sib2, iclass 26, count 2 2006.176.07:56:29.14#ibcon#flushed, iclass 26, count 2 2006.176.07:56:29.14#ibcon#about to write, iclass 26, count 2 2006.176.07:56:29.14#ibcon#wrote, iclass 26, count 2 2006.176.07:56:29.14#ibcon#about to read 3, iclass 26, count 2 2006.176.07:56:29.17#ibcon#read 3, iclass 26, count 2 2006.176.07:56:29.17#ibcon#about to read 4, iclass 26, count 2 2006.176.07:56:29.17#ibcon#read 4, iclass 26, count 2 2006.176.07:56:29.17#ibcon#about to read 5, iclass 26, count 2 2006.176.07:56:29.17#ibcon#read 5, iclass 26, count 2 2006.176.07:56:29.17#ibcon#about to read 6, iclass 26, count 2 2006.176.07:56:29.17#ibcon#read 6, iclass 26, count 2 2006.176.07:56:29.17#ibcon#end of sib2, iclass 26, count 2 2006.176.07:56:29.17#ibcon#*after write, iclass 26, count 2 2006.176.07:56:29.17#ibcon#*before return 0, iclass 26, count 2 2006.176.07:56:29.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:29.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:29.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.07:56:29.17#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:29.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:29.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:29.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:29.29#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:56:29.29#ibcon#first serial, iclass 26, count 0 2006.176.07:56:29.29#ibcon#enter sib2, iclass 26, count 0 2006.176.07:56:29.29#ibcon#flushed, iclass 26, count 0 2006.176.07:56:29.29#ibcon#about to write, iclass 26, count 0 2006.176.07:56:29.29#ibcon#wrote, iclass 26, count 0 2006.176.07:56:29.29#ibcon#about to read 3, iclass 26, count 0 2006.176.07:56:29.31#ibcon#read 3, iclass 26, count 0 2006.176.07:56:29.31#ibcon#about to read 4, iclass 26, count 0 2006.176.07:56:29.31#ibcon#read 4, iclass 26, count 0 2006.176.07:56:29.31#ibcon#about to read 5, iclass 26, count 0 2006.176.07:56:29.31#ibcon#read 5, iclass 26, count 0 2006.176.07:56:29.31#ibcon#about to read 6, iclass 26, count 0 2006.176.07:56:29.31#ibcon#read 6, iclass 26, count 0 2006.176.07:56:29.31#ibcon#end of sib2, iclass 26, count 0 2006.176.07:56:29.31#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:56:29.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:56:29.31#ibcon#[25=USB\r\n] 2006.176.07:56:29.31#ibcon#*before write, iclass 26, count 0 2006.176.07:56:29.31#ibcon#enter sib2, iclass 26, count 0 2006.176.07:56:29.31#ibcon#flushed, iclass 26, count 0 2006.176.07:56:29.31#ibcon#about to write, iclass 26, count 0 2006.176.07:56:29.31#ibcon#wrote, iclass 26, count 0 2006.176.07:56:29.31#ibcon#about to read 3, iclass 26, count 0 2006.176.07:56:29.34#ibcon#read 3, iclass 26, count 0 2006.176.07:56:29.34#ibcon#about to read 4, iclass 26, count 0 2006.176.07:56:29.34#ibcon#read 4, iclass 26, count 0 2006.176.07:56:29.34#ibcon#about to read 5, iclass 26, count 0 2006.176.07:56:29.34#ibcon#read 5, iclass 26, count 0 2006.176.07:56:29.34#ibcon#about to read 6, iclass 26, count 0 2006.176.07:56:29.34#ibcon#read 6, iclass 26, count 0 2006.176.07:56:29.34#ibcon#end of sib2, iclass 26, count 0 2006.176.07:56:29.34#ibcon#*after write, iclass 26, count 0 2006.176.07:56:29.34#ibcon#*before return 0, iclass 26, count 0 2006.176.07:56:29.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:29.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:29.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:56:29.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:56:29.34$vc4f8/valo=5,652.99 2006.176.07:56:29.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.07:56:29.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.07:56:29.34#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:29.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:29.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:29.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:29.34#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:56:29.34#ibcon#first serial, iclass 28, count 0 2006.176.07:56:29.34#ibcon#enter sib2, iclass 28, count 0 2006.176.07:56:29.34#ibcon#flushed, iclass 28, count 0 2006.176.07:56:29.34#ibcon#about to write, iclass 28, count 0 2006.176.07:56:29.34#ibcon#wrote, iclass 28, count 0 2006.176.07:56:29.34#ibcon#about to read 3, iclass 28, count 0 2006.176.07:56:29.36#ibcon#read 3, iclass 28, count 0 2006.176.07:56:29.36#ibcon#about to read 4, iclass 28, count 0 2006.176.07:56:29.36#ibcon#read 4, iclass 28, count 0 2006.176.07:56:29.36#ibcon#about to read 5, iclass 28, count 0 2006.176.07:56:29.36#ibcon#read 5, iclass 28, count 0 2006.176.07:56:29.36#ibcon#about to read 6, iclass 28, count 0 2006.176.07:56:29.36#ibcon#read 6, iclass 28, count 0 2006.176.07:56:29.36#ibcon#end of sib2, iclass 28, count 0 2006.176.07:56:29.36#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:56:29.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:56:29.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:56:29.36#ibcon#*before write, iclass 28, count 0 2006.176.07:56:29.36#ibcon#enter sib2, iclass 28, count 0 2006.176.07:56:29.36#ibcon#flushed, iclass 28, count 0 2006.176.07:56:29.36#ibcon#about to write, iclass 28, count 0 2006.176.07:56:29.36#ibcon#wrote, iclass 28, count 0 2006.176.07:56:29.36#ibcon#about to read 3, iclass 28, count 0 2006.176.07:56:29.40#ibcon#read 3, iclass 28, count 0 2006.176.07:56:29.40#ibcon#about to read 4, iclass 28, count 0 2006.176.07:56:29.40#ibcon#read 4, iclass 28, count 0 2006.176.07:56:29.40#ibcon#about to read 5, iclass 28, count 0 2006.176.07:56:29.40#ibcon#read 5, iclass 28, count 0 2006.176.07:56:29.40#ibcon#about to read 6, iclass 28, count 0 2006.176.07:56:29.40#ibcon#read 6, iclass 28, count 0 2006.176.07:56:29.40#ibcon#end of sib2, iclass 28, count 0 2006.176.07:56:29.40#ibcon#*after write, iclass 28, count 0 2006.176.07:56:29.40#ibcon#*before return 0, iclass 28, count 0 2006.176.07:56:29.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:29.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:29.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:56:29.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:56:29.40$vc4f8/va=5,7 2006.176.07:56:29.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.07:56:29.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.07:56:29.40#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:29.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:29.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:29.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:29.46#ibcon#enter wrdev, iclass 30, count 2 2006.176.07:56:29.46#ibcon#first serial, iclass 30, count 2 2006.176.07:56:29.46#ibcon#enter sib2, iclass 30, count 2 2006.176.07:56:29.46#ibcon#flushed, iclass 30, count 2 2006.176.07:56:29.46#ibcon#about to write, iclass 30, count 2 2006.176.07:56:29.46#ibcon#wrote, iclass 30, count 2 2006.176.07:56:29.46#ibcon#about to read 3, iclass 30, count 2 2006.176.07:56:29.48#ibcon#read 3, iclass 30, count 2 2006.176.07:56:29.48#ibcon#about to read 4, iclass 30, count 2 2006.176.07:56:29.48#ibcon#read 4, iclass 30, count 2 2006.176.07:56:29.48#ibcon#about to read 5, iclass 30, count 2 2006.176.07:56:29.48#ibcon#read 5, iclass 30, count 2 2006.176.07:56:29.48#ibcon#about to read 6, iclass 30, count 2 2006.176.07:56:29.48#ibcon#read 6, iclass 30, count 2 2006.176.07:56:29.48#ibcon#end of sib2, iclass 30, count 2 2006.176.07:56:29.48#ibcon#*mode == 0, iclass 30, count 2 2006.176.07:56:29.48#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.07:56:29.48#ibcon#[25=AT05-07\r\n] 2006.176.07:56:29.48#ibcon#*before write, iclass 30, count 2 2006.176.07:56:29.48#ibcon#enter sib2, iclass 30, count 2 2006.176.07:56:29.48#ibcon#flushed, iclass 30, count 2 2006.176.07:56:29.48#ibcon#about to write, iclass 30, count 2 2006.176.07:56:29.48#ibcon#wrote, iclass 30, count 2 2006.176.07:56:29.48#ibcon#about to read 3, iclass 30, count 2 2006.176.07:56:29.51#ibcon#read 3, iclass 30, count 2 2006.176.07:56:29.51#ibcon#about to read 4, iclass 30, count 2 2006.176.07:56:29.51#ibcon#read 4, iclass 30, count 2 2006.176.07:56:29.51#ibcon#about to read 5, iclass 30, count 2 2006.176.07:56:29.51#ibcon#read 5, iclass 30, count 2 2006.176.07:56:29.51#ibcon#about to read 6, iclass 30, count 2 2006.176.07:56:29.51#ibcon#read 6, iclass 30, count 2 2006.176.07:56:29.51#ibcon#end of sib2, iclass 30, count 2 2006.176.07:56:29.51#ibcon#*after write, iclass 30, count 2 2006.176.07:56:29.51#ibcon#*before return 0, iclass 30, count 2 2006.176.07:56:29.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:29.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:29.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.07:56:29.51#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:29.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:29.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:29.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:29.63#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:56:29.63#ibcon#first serial, iclass 30, count 0 2006.176.07:56:29.63#ibcon#enter sib2, iclass 30, count 0 2006.176.07:56:29.63#ibcon#flushed, iclass 30, count 0 2006.176.07:56:29.63#ibcon#about to write, iclass 30, count 0 2006.176.07:56:29.63#ibcon#wrote, iclass 30, count 0 2006.176.07:56:29.63#ibcon#about to read 3, iclass 30, count 0 2006.176.07:56:29.65#ibcon#read 3, iclass 30, count 0 2006.176.07:56:29.65#ibcon#about to read 4, iclass 30, count 0 2006.176.07:56:29.65#ibcon#read 4, iclass 30, count 0 2006.176.07:56:29.65#ibcon#about to read 5, iclass 30, count 0 2006.176.07:56:29.65#ibcon#read 5, iclass 30, count 0 2006.176.07:56:29.65#ibcon#about to read 6, iclass 30, count 0 2006.176.07:56:29.65#ibcon#read 6, iclass 30, count 0 2006.176.07:56:29.65#ibcon#end of sib2, iclass 30, count 0 2006.176.07:56:29.65#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:56:29.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:56:29.65#ibcon#[25=USB\r\n] 2006.176.07:56:29.65#ibcon#*before write, iclass 30, count 0 2006.176.07:56:29.65#ibcon#enter sib2, iclass 30, count 0 2006.176.07:56:29.65#ibcon#flushed, iclass 30, count 0 2006.176.07:56:29.65#ibcon#about to write, iclass 30, count 0 2006.176.07:56:29.65#ibcon#wrote, iclass 30, count 0 2006.176.07:56:29.65#ibcon#about to read 3, iclass 30, count 0 2006.176.07:56:29.68#ibcon#read 3, iclass 30, count 0 2006.176.07:56:29.68#ibcon#about to read 4, iclass 30, count 0 2006.176.07:56:29.68#ibcon#read 4, iclass 30, count 0 2006.176.07:56:29.68#ibcon#about to read 5, iclass 30, count 0 2006.176.07:56:29.68#ibcon#read 5, iclass 30, count 0 2006.176.07:56:29.68#ibcon#about to read 6, iclass 30, count 0 2006.176.07:56:29.68#ibcon#read 6, iclass 30, count 0 2006.176.07:56:29.68#ibcon#end of sib2, iclass 30, count 0 2006.176.07:56:29.68#ibcon#*after write, iclass 30, count 0 2006.176.07:56:29.68#ibcon#*before return 0, iclass 30, count 0 2006.176.07:56:29.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:29.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:29.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:56:29.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:56:29.68$vc4f8/valo=6,772.99 2006.176.07:56:29.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.07:56:29.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.07:56:29.68#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:29.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:29.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:29.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:29.68#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:56:29.68#ibcon#first serial, iclass 32, count 0 2006.176.07:56:29.68#ibcon#enter sib2, iclass 32, count 0 2006.176.07:56:29.68#ibcon#flushed, iclass 32, count 0 2006.176.07:56:29.68#ibcon#about to write, iclass 32, count 0 2006.176.07:56:29.68#ibcon#wrote, iclass 32, count 0 2006.176.07:56:29.68#ibcon#about to read 3, iclass 32, count 0 2006.176.07:56:29.70#ibcon#read 3, iclass 32, count 0 2006.176.07:56:29.70#ibcon#about to read 4, iclass 32, count 0 2006.176.07:56:29.70#ibcon#read 4, iclass 32, count 0 2006.176.07:56:29.70#ibcon#about to read 5, iclass 32, count 0 2006.176.07:56:29.70#ibcon#read 5, iclass 32, count 0 2006.176.07:56:29.70#ibcon#about to read 6, iclass 32, count 0 2006.176.07:56:29.70#ibcon#read 6, iclass 32, count 0 2006.176.07:56:29.70#ibcon#end of sib2, iclass 32, count 0 2006.176.07:56:29.70#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:56:29.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:56:29.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:56:29.70#ibcon#*before write, iclass 32, count 0 2006.176.07:56:29.70#ibcon#enter sib2, iclass 32, count 0 2006.176.07:56:29.70#ibcon#flushed, iclass 32, count 0 2006.176.07:56:29.70#ibcon#about to write, iclass 32, count 0 2006.176.07:56:29.70#ibcon#wrote, iclass 32, count 0 2006.176.07:56:29.70#ibcon#about to read 3, iclass 32, count 0 2006.176.07:56:29.74#ibcon#read 3, iclass 32, count 0 2006.176.07:56:29.74#ibcon#about to read 4, iclass 32, count 0 2006.176.07:56:29.74#ibcon#read 4, iclass 32, count 0 2006.176.07:56:29.74#ibcon#about to read 5, iclass 32, count 0 2006.176.07:56:29.74#ibcon#read 5, iclass 32, count 0 2006.176.07:56:29.74#ibcon#about to read 6, iclass 32, count 0 2006.176.07:56:29.74#ibcon#read 6, iclass 32, count 0 2006.176.07:56:29.74#ibcon#end of sib2, iclass 32, count 0 2006.176.07:56:29.74#ibcon#*after write, iclass 32, count 0 2006.176.07:56:29.74#ibcon#*before return 0, iclass 32, count 0 2006.176.07:56:29.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:29.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:29.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:56:29.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:56:29.74$vc4f8/va=6,6 2006.176.07:56:29.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.07:56:29.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.07:56:29.74#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:29.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:56:29.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:56:29.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:56:29.80#ibcon#enter wrdev, iclass 34, count 2 2006.176.07:56:29.80#ibcon#first serial, iclass 34, count 2 2006.176.07:56:29.80#ibcon#enter sib2, iclass 34, count 2 2006.176.07:56:29.80#ibcon#flushed, iclass 34, count 2 2006.176.07:56:29.80#ibcon#about to write, iclass 34, count 2 2006.176.07:56:29.80#ibcon#wrote, iclass 34, count 2 2006.176.07:56:29.80#ibcon#about to read 3, iclass 34, count 2 2006.176.07:56:29.82#ibcon#read 3, iclass 34, count 2 2006.176.07:56:29.82#ibcon#about to read 4, iclass 34, count 2 2006.176.07:56:29.82#ibcon#read 4, iclass 34, count 2 2006.176.07:56:29.82#ibcon#about to read 5, iclass 34, count 2 2006.176.07:56:29.82#ibcon#read 5, iclass 34, count 2 2006.176.07:56:29.82#ibcon#about to read 6, iclass 34, count 2 2006.176.07:56:29.82#ibcon#read 6, iclass 34, count 2 2006.176.07:56:29.82#ibcon#end of sib2, iclass 34, count 2 2006.176.07:56:29.82#ibcon#*mode == 0, iclass 34, count 2 2006.176.07:56:29.82#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.07:56:29.82#ibcon#[25=AT06-06\r\n] 2006.176.07:56:29.82#ibcon#*before write, iclass 34, count 2 2006.176.07:56:29.82#ibcon#enter sib2, iclass 34, count 2 2006.176.07:56:29.82#ibcon#flushed, iclass 34, count 2 2006.176.07:56:29.82#ibcon#about to write, iclass 34, count 2 2006.176.07:56:29.82#ibcon#wrote, iclass 34, count 2 2006.176.07:56:29.82#ibcon#about to read 3, iclass 34, count 2 2006.176.07:56:29.85#ibcon#read 3, iclass 34, count 2 2006.176.07:56:29.85#ibcon#about to read 4, iclass 34, count 2 2006.176.07:56:29.85#ibcon#read 4, iclass 34, count 2 2006.176.07:56:29.85#ibcon#about to read 5, iclass 34, count 2 2006.176.07:56:29.85#ibcon#read 5, iclass 34, count 2 2006.176.07:56:29.85#ibcon#about to read 6, iclass 34, count 2 2006.176.07:56:29.85#ibcon#read 6, iclass 34, count 2 2006.176.07:56:29.85#ibcon#end of sib2, iclass 34, count 2 2006.176.07:56:29.85#ibcon#*after write, iclass 34, count 2 2006.176.07:56:29.85#ibcon#*before return 0, iclass 34, count 2 2006.176.07:56:29.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:56:29.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.07:56:29.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.07:56:29.85#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:29.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:56:29.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:56:29.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:56:29.97#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:56:29.97#ibcon#first serial, iclass 34, count 0 2006.176.07:56:29.97#ibcon#enter sib2, iclass 34, count 0 2006.176.07:56:29.97#ibcon#flushed, iclass 34, count 0 2006.176.07:56:29.97#ibcon#about to write, iclass 34, count 0 2006.176.07:56:29.97#ibcon#wrote, iclass 34, count 0 2006.176.07:56:29.97#ibcon#about to read 3, iclass 34, count 0 2006.176.07:56:29.99#ibcon#read 3, iclass 34, count 0 2006.176.07:56:29.99#ibcon#about to read 4, iclass 34, count 0 2006.176.07:56:29.99#ibcon#read 4, iclass 34, count 0 2006.176.07:56:29.99#ibcon#about to read 5, iclass 34, count 0 2006.176.07:56:29.99#ibcon#read 5, iclass 34, count 0 2006.176.07:56:29.99#ibcon#about to read 6, iclass 34, count 0 2006.176.07:56:29.99#ibcon#read 6, iclass 34, count 0 2006.176.07:56:29.99#ibcon#end of sib2, iclass 34, count 0 2006.176.07:56:29.99#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:56:29.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:56:29.99#ibcon#[25=USB\r\n] 2006.176.07:56:29.99#ibcon#*before write, iclass 34, count 0 2006.176.07:56:29.99#ibcon#enter sib2, iclass 34, count 0 2006.176.07:56:29.99#ibcon#flushed, iclass 34, count 0 2006.176.07:56:29.99#ibcon#about to write, iclass 34, count 0 2006.176.07:56:29.99#ibcon#wrote, iclass 34, count 0 2006.176.07:56:29.99#ibcon#about to read 3, iclass 34, count 0 2006.176.07:56:30.02#ibcon#read 3, iclass 34, count 0 2006.176.07:56:30.02#ibcon#about to read 4, iclass 34, count 0 2006.176.07:56:30.02#ibcon#read 4, iclass 34, count 0 2006.176.07:56:30.02#ibcon#about to read 5, iclass 34, count 0 2006.176.07:56:30.02#ibcon#read 5, iclass 34, count 0 2006.176.07:56:30.02#ibcon#about to read 6, iclass 34, count 0 2006.176.07:56:30.02#ibcon#read 6, iclass 34, count 0 2006.176.07:56:30.02#ibcon#end of sib2, iclass 34, count 0 2006.176.07:56:30.02#ibcon#*after write, iclass 34, count 0 2006.176.07:56:30.02#ibcon#*before return 0, iclass 34, count 0 2006.176.07:56:30.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:56:30.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.07:56:30.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:56:30.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:56:30.02$vc4f8/valo=7,832.99 2006.176.07:56:30.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.07:56:30.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.07:56:30.02#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:30.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:56:30.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:56:30.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:56:30.02#ibcon#enter wrdev, iclass 36, count 0 2006.176.07:56:30.02#ibcon#first serial, iclass 36, count 0 2006.176.07:56:30.02#ibcon#enter sib2, iclass 36, count 0 2006.176.07:56:30.02#ibcon#flushed, iclass 36, count 0 2006.176.07:56:30.02#ibcon#about to write, iclass 36, count 0 2006.176.07:56:30.02#ibcon#wrote, iclass 36, count 0 2006.176.07:56:30.02#ibcon#about to read 3, iclass 36, count 0 2006.176.07:56:30.04#ibcon#read 3, iclass 36, count 0 2006.176.07:56:30.04#ibcon#about to read 4, iclass 36, count 0 2006.176.07:56:30.04#ibcon#read 4, iclass 36, count 0 2006.176.07:56:30.04#ibcon#about to read 5, iclass 36, count 0 2006.176.07:56:30.04#ibcon#read 5, iclass 36, count 0 2006.176.07:56:30.04#ibcon#about to read 6, iclass 36, count 0 2006.176.07:56:30.04#ibcon#read 6, iclass 36, count 0 2006.176.07:56:30.04#ibcon#end of sib2, iclass 36, count 0 2006.176.07:56:30.04#ibcon#*mode == 0, iclass 36, count 0 2006.176.07:56:30.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.07:56:30.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:56:30.04#ibcon#*before write, iclass 36, count 0 2006.176.07:56:30.04#ibcon#enter sib2, iclass 36, count 0 2006.176.07:56:30.04#ibcon#flushed, iclass 36, count 0 2006.176.07:56:30.04#ibcon#about to write, iclass 36, count 0 2006.176.07:56:30.04#ibcon#wrote, iclass 36, count 0 2006.176.07:56:30.04#ibcon#about to read 3, iclass 36, count 0 2006.176.07:56:30.08#ibcon#read 3, iclass 36, count 0 2006.176.07:56:30.08#ibcon#about to read 4, iclass 36, count 0 2006.176.07:56:30.08#ibcon#read 4, iclass 36, count 0 2006.176.07:56:30.08#ibcon#about to read 5, iclass 36, count 0 2006.176.07:56:30.08#ibcon#read 5, iclass 36, count 0 2006.176.07:56:30.08#ibcon#about to read 6, iclass 36, count 0 2006.176.07:56:30.08#ibcon#read 6, iclass 36, count 0 2006.176.07:56:30.08#ibcon#end of sib2, iclass 36, count 0 2006.176.07:56:30.08#ibcon#*after write, iclass 36, count 0 2006.176.07:56:30.08#ibcon#*before return 0, iclass 36, count 0 2006.176.07:56:30.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:56:30.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.07:56:30.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.07:56:30.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.07:56:30.08$vc4f8/va=7,6 2006.176.07:56:30.08#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.07:56:30.08#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.07:56:30.08#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:30.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:56:30.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:56:30.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:56:30.14#ibcon#enter wrdev, iclass 38, count 2 2006.176.07:56:30.14#ibcon#first serial, iclass 38, count 2 2006.176.07:56:30.14#ibcon#enter sib2, iclass 38, count 2 2006.176.07:56:30.14#ibcon#flushed, iclass 38, count 2 2006.176.07:56:30.14#ibcon#about to write, iclass 38, count 2 2006.176.07:56:30.14#ibcon#wrote, iclass 38, count 2 2006.176.07:56:30.14#ibcon#about to read 3, iclass 38, count 2 2006.176.07:56:30.16#ibcon#read 3, iclass 38, count 2 2006.176.07:56:30.16#ibcon#about to read 4, iclass 38, count 2 2006.176.07:56:30.16#ibcon#read 4, iclass 38, count 2 2006.176.07:56:30.16#ibcon#about to read 5, iclass 38, count 2 2006.176.07:56:30.16#ibcon#read 5, iclass 38, count 2 2006.176.07:56:30.16#ibcon#about to read 6, iclass 38, count 2 2006.176.07:56:30.16#ibcon#read 6, iclass 38, count 2 2006.176.07:56:30.16#ibcon#end of sib2, iclass 38, count 2 2006.176.07:56:30.16#ibcon#*mode == 0, iclass 38, count 2 2006.176.07:56:30.16#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.07:56:30.16#ibcon#[25=AT07-06\r\n] 2006.176.07:56:30.16#ibcon#*before write, iclass 38, count 2 2006.176.07:56:30.16#ibcon#enter sib2, iclass 38, count 2 2006.176.07:56:30.16#ibcon#flushed, iclass 38, count 2 2006.176.07:56:30.16#ibcon#about to write, iclass 38, count 2 2006.176.07:56:30.16#ibcon#wrote, iclass 38, count 2 2006.176.07:56:30.16#ibcon#about to read 3, iclass 38, count 2 2006.176.07:56:30.19#ibcon#read 3, iclass 38, count 2 2006.176.07:56:30.19#ibcon#about to read 4, iclass 38, count 2 2006.176.07:56:30.19#ibcon#read 4, iclass 38, count 2 2006.176.07:56:30.19#ibcon#about to read 5, iclass 38, count 2 2006.176.07:56:30.19#ibcon#read 5, iclass 38, count 2 2006.176.07:56:30.19#ibcon#about to read 6, iclass 38, count 2 2006.176.07:56:30.19#ibcon#read 6, iclass 38, count 2 2006.176.07:56:30.19#ibcon#end of sib2, iclass 38, count 2 2006.176.07:56:30.19#ibcon#*after write, iclass 38, count 2 2006.176.07:56:30.19#ibcon#*before return 0, iclass 38, count 2 2006.176.07:56:30.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:56:30.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.07:56:30.19#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.07:56:30.19#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:30.19#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:56:30.31#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:56:30.31#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:56:30.31#ibcon#enter wrdev, iclass 38, count 0 2006.176.07:56:30.31#ibcon#first serial, iclass 38, count 0 2006.176.07:56:30.31#ibcon#enter sib2, iclass 38, count 0 2006.176.07:56:30.31#ibcon#flushed, iclass 38, count 0 2006.176.07:56:30.31#ibcon#about to write, iclass 38, count 0 2006.176.07:56:30.31#ibcon#wrote, iclass 38, count 0 2006.176.07:56:30.31#ibcon#about to read 3, iclass 38, count 0 2006.176.07:56:30.33#ibcon#read 3, iclass 38, count 0 2006.176.07:56:30.33#ibcon#about to read 4, iclass 38, count 0 2006.176.07:56:30.33#ibcon#read 4, iclass 38, count 0 2006.176.07:56:30.33#ibcon#about to read 5, iclass 38, count 0 2006.176.07:56:30.33#ibcon#read 5, iclass 38, count 0 2006.176.07:56:30.33#ibcon#about to read 6, iclass 38, count 0 2006.176.07:56:30.33#ibcon#read 6, iclass 38, count 0 2006.176.07:56:30.33#ibcon#end of sib2, iclass 38, count 0 2006.176.07:56:30.33#ibcon#*mode == 0, iclass 38, count 0 2006.176.07:56:30.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.07:56:30.33#ibcon#[25=USB\r\n] 2006.176.07:56:30.33#ibcon#*before write, iclass 38, count 0 2006.176.07:56:30.33#ibcon#enter sib2, iclass 38, count 0 2006.176.07:56:30.33#ibcon#flushed, iclass 38, count 0 2006.176.07:56:30.33#ibcon#about to write, iclass 38, count 0 2006.176.07:56:30.33#ibcon#wrote, iclass 38, count 0 2006.176.07:56:30.33#ibcon#about to read 3, iclass 38, count 0 2006.176.07:56:30.36#ibcon#read 3, iclass 38, count 0 2006.176.07:56:30.36#ibcon#about to read 4, iclass 38, count 0 2006.176.07:56:30.36#ibcon#read 4, iclass 38, count 0 2006.176.07:56:30.36#ibcon#about to read 5, iclass 38, count 0 2006.176.07:56:30.36#ibcon#read 5, iclass 38, count 0 2006.176.07:56:30.36#ibcon#about to read 6, iclass 38, count 0 2006.176.07:56:30.36#ibcon#read 6, iclass 38, count 0 2006.176.07:56:30.36#ibcon#end of sib2, iclass 38, count 0 2006.176.07:56:30.36#ibcon#*after write, iclass 38, count 0 2006.176.07:56:30.36#ibcon#*before return 0, iclass 38, count 0 2006.176.07:56:30.36#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:56:30.36#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.07:56:30.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.07:56:30.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.07:56:30.36$vc4f8/valo=8,852.99 2006.176.07:56:30.36#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.07:56:30.36#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.07:56:30.36#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:30.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:56:30.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:56:30.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:56:30.36#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:56:30.36#ibcon#first serial, iclass 40, count 0 2006.176.07:56:30.36#ibcon#enter sib2, iclass 40, count 0 2006.176.07:56:30.36#ibcon#flushed, iclass 40, count 0 2006.176.07:56:30.36#ibcon#about to write, iclass 40, count 0 2006.176.07:56:30.36#ibcon#wrote, iclass 40, count 0 2006.176.07:56:30.36#ibcon#about to read 3, iclass 40, count 0 2006.176.07:56:30.38#ibcon#read 3, iclass 40, count 0 2006.176.07:56:30.38#ibcon#about to read 4, iclass 40, count 0 2006.176.07:56:30.38#ibcon#read 4, iclass 40, count 0 2006.176.07:56:30.38#ibcon#about to read 5, iclass 40, count 0 2006.176.07:56:30.38#ibcon#read 5, iclass 40, count 0 2006.176.07:56:30.38#ibcon#about to read 6, iclass 40, count 0 2006.176.07:56:30.38#ibcon#read 6, iclass 40, count 0 2006.176.07:56:30.38#ibcon#end of sib2, iclass 40, count 0 2006.176.07:56:30.38#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:56:30.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:56:30.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.07:56:30.38#ibcon#*before write, iclass 40, count 0 2006.176.07:56:30.38#ibcon#enter sib2, iclass 40, count 0 2006.176.07:56:30.38#ibcon#flushed, iclass 40, count 0 2006.176.07:56:30.38#ibcon#about to write, iclass 40, count 0 2006.176.07:56:30.38#ibcon#wrote, iclass 40, count 0 2006.176.07:56:30.38#ibcon#about to read 3, iclass 40, count 0 2006.176.07:56:30.42#ibcon#read 3, iclass 40, count 0 2006.176.07:56:30.42#ibcon#about to read 4, iclass 40, count 0 2006.176.07:56:30.42#ibcon#read 4, iclass 40, count 0 2006.176.07:56:30.42#ibcon#about to read 5, iclass 40, count 0 2006.176.07:56:30.42#ibcon#read 5, iclass 40, count 0 2006.176.07:56:30.42#ibcon#about to read 6, iclass 40, count 0 2006.176.07:56:30.42#ibcon#read 6, iclass 40, count 0 2006.176.07:56:30.42#ibcon#end of sib2, iclass 40, count 0 2006.176.07:56:30.42#ibcon#*after write, iclass 40, count 0 2006.176.07:56:30.42#ibcon#*before return 0, iclass 40, count 0 2006.176.07:56:30.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:56:30.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:56:30.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:56:30.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:56:30.42$vc4f8/va=8,6 2006.176.07:56:30.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.07:56:30.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.07:56:30.42#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:30.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:56:30.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:56:30.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:56:30.48#ibcon#enter wrdev, iclass 4, count 2 2006.176.07:56:30.48#ibcon#first serial, iclass 4, count 2 2006.176.07:56:30.48#ibcon#enter sib2, iclass 4, count 2 2006.176.07:56:30.48#ibcon#flushed, iclass 4, count 2 2006.176.07:56:30.48#ibcon#about to write, iclass 4, count 2 2006.176.07:56:30.48#ibcon#wrote, iclass 4, count 2 2006.176.07:56:30.48#ibcon#about to read 3, iclass 4, count 2 2006.176.07:56:30.51#ibcon#read 3, iclass 4, count 2 2006.176.07:56:30.51#ibcon#about to read 4, iclass 4, count 2 2006.176.07:56:30.51#ibcon#read 4, iclass 4, count 2 2006.176.07:56:30.51#ibcon#about to read 5, iclass 4, count 2 2006.176.07:56:30.51#ibcon#read 5, iclass 4, count 2 2006.176.07:56:30.51#ibcon#about to read 6, iclass 4, count 2 2006.176.07:56:30.51#ibcon#read 6, iclass 4, count 2 2006.176.07:56:30.51#ibcon#end of sib2, iclass 4, count 2 2006.176.07:56:30.51#ibcon#*mode == 0, iclass 4, count 2 2006.176.07:56:30.51#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.07:56:30.51#ibcon#[25=AT08-06\r\n] 2006.176.07:56:30.51#ibcon#*before write, iclass 4, count 2 2006.176.07:56:30.51#ibcon#enter sib2, iclass 4, count 2 2006.176.07:56:30.51#ibcon#flushed, iclass 4, count 2 2006.176.07:56:30.51#ibcon#about to write, iclass 4, count 2 2006.176.07:56:30.51#ibcon#wrote, iclass 4, count 2 2006.176.07:56:30.51#ibcon#about to read 3, iclass 4, count 2 2006.176.07:56:30.53#ibcon#read 3, iclass 4, count 2 2006.176.07:56:30.53#ibcon#about to read 4, iclass 4, count 2 2006.176.07:56:30.53#ibcon#read 4, iclass 4, count 2 2006.176.07:56:30.53#ibcon#about to read 5, iclass 4, count 2 2006.176.07:56:30.53#ibcon#read 5, iclass 4, count 2 2006.176.07:56:30.53#ibcon#about to read 6, iclass 4, count 2 2006.176.07:56:30.53#ibcon#read 6, iclass 4, count 2 2006.176.07:56:30.53#ibcon#end of sib2, iclass 4, count 2 2006.176.07:56:30.53#ibcon#*after write, iclass 4, count 2 2006.176.07:56:30.53#ibcon#*before return 0, iclass 4, count 2 2006.176.07:56:30.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:56:30.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:56:30.53#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.07:56:30.53#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:30.53#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:56:30.65#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:56:30.65#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:56:30.65#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:56:30.65#ibcon#first serial, iclass 4, count 0 2006.176.07:56:30.65#ibcon#enter sib2, iclass 4, count 0 2006.176.07:56:30.65#ibcon#flushed, iclass 4, count 0 2006.176.07:56:30.65#ibcon#about to write, iclass 4, count 0 2006.176.07:56:30.65#ibcon#wrote, iclass 4, count 0 2006.176.07:56:30.65#ibcon#about to read 3, iclass 4, count 0 2006.176.07:56:30.67#ibcon#read 3, iclass 4, count 0 2006.176.07:56:30.67#ibcon#about to read 4, iclass 4, count 0 2006.176.07:56:30.67#ibcon#read 4, iclass 4, count 0 2006.176.07:56:30.67#ibcon#about to read 5, iclass 4, count 0 2006.176.07:56:30.67#ibcon#read 5, iclass 4, count 0 2006.176.07:56:30.67#ibcon#about to read 6, iclass 4, count 0 2006.176.07:56:30.67#ibcon#read 6, iclass 4, count 0 2006.176.07:56:30.67#ibcon#end of sib2, iclass 4, count 0 2006.176.07:56:30.67#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:56:30.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:56:30.67#ibcon#[25=USB\r\n] 2006.176.07:56:30.67#ibcon#*before write, iclass 4, count 0 2006.176.07:56:30.67#ibcon#enter sib2, iclass 4, count 0 2006.176.07:56:30.67#ibcon#flushed, iclass 4, count 0 2006.176.07:56:30.67#ibcon#about to write, iclass 4, count 0 2006.176.07:56:30.67#ibcon#wrote, iclass 4, count 0 2006.176.07:56:30.67#ibcon#about to read 3, iclass 4, count 0 2006.176.07:56:30.70#ibcon#read 3, iclass 4, count 0 2006.176.07:56:30.70#ibcon#about to read 4, iclass 4, count 0 2006.176.07:56:30.70#ibcon#read 4, iclass 4, count 0 2006.176.07:56:30.70#ibcon#about to read 5, iclass 4, count 0 2006.176.07:56:30.70#ibcon#read 5, iclass 4, count 0 2006.176.07:56:30.70#ibcon#about to read 6, iclass 4, count 0 2006.176.07:56:30.70#ibcon#read 6, iclass 4, count 0 2006.176.07:56:30.70#ibcon#end of sib2, iclass 4, count 0 2006.176.07:56:30.70#ibcon#*after write, iclass 4, count 0 2006.176.07:56:30.70#ibcon#*before return 0, iclass 4, count 0 2006.176.07:56:30.70#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:56:30.70#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:56:30.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:56:30.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:56:30.70$vc4f8/vblo=1,632.99 2006.176.07:56:30.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.07:56:30.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.07:56:30.70#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:30.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:56:30.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:56:30.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:56:30.70#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:56:30.70#ibcon#first serial, iclass 6, count 0 2006.176.07:56:30.70#ibcon#enter sib2, iclass 6, count 0 2006.176.07:56:30.70#ibcon#flushed, iclass 6, count 0 2006.176.07:56:30.70#ibcon#about to write, iclass 6, count 0 2006.176.07:56:30.70#ibcon#wrote, iclass 6, count 0 2006.176.07:56:30.70#ibcon#about to read 3, iclass 6, count 0 2006.176.07:56:30.72#ibcon#read 3, iclass 6, count 0 2006.176.07:56:30.72#ibcon#about to read 4, iclass 6, count 0 2006.176.07:56:30.72#ibcon#read 4, iclass 6, count 0 2006.176.07:56:30.72#ibcon#about to read 5, iclass 6, count 0 2006.176.07:56:30.72#ibcon#read 5, iclass 6, count 0 2006.176.07:56:30.72#ibcon#about to read 6, iclass 6, count 0 2006.176.07:56:30.72#ibcon#read 6, iclass 6, count 0 2006.176.07:56:30.72#ibcon#end of sib2, iclass 6, count 0 2006.176.07:56:30.72#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:56:30.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:56:30.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.07:56:30.72#ibcon#*before write, iclass 6, count 0 2006.176.07:56:30.72#ibcon#enter sib2, iclass 6, count 0 2006.176.07:56:30.72#ibcon#flushed, iclass 6, count 0 2006.176.07:56:30.72#ibcon#about to write, iclass 6, count 0 2006.176.07:56:30.72#ibcon#wrote, iclass 6, count 0 2006.176.07:56:30.72#ibcon#about to read 3, iclass 6, count 0 2006.176.07:56:30.76#ibcon#read 3, iclass 6, count 0 2006.176.07:56:30.76#ibcon#about to read 4, iclass 6, count 0 2006.176.07:56:30.76#ibcon#read 4, iclass 6, count 0 2006.176.07:56:30.76#ibcon#about to read 5, iclass 6, count 0 2006.176.07:56:30.76#ibcon#read 5, iclass 6, count 0 2006.176.07:56:30.76#ibcon#about to read 6, iclass 6, count 0 2006.176.07:56:30.76#ibcon#read 6, iclass 6, count 0 2006.176.07:56:30.76#ibcon#end of sib2, iclass 6, count 0 2006.176.07:56:30.76#ibcon#*after write, iclass 6, count 0 2006.176.07:56:30.76#ibcon#*before return 0, iclass 6, count 0 2006.176.07:56:30.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:56:30.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:56:30.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:56:30.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:56:30.76$vc4f8/vb=1,4 2006.176.07:56:30.76#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.07:56:30.76#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.07:56:30.76#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:30.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:56:30.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:56:30.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:56:30.76#ibcon#enter wrdev, iclass 10, count 2 2006.176.07:56:30.76#ibcon#first serial, iclass 10, count 2 2006.176.07:56:30.76#ibcon#enter sib2, iclass 10, count 2 2006.176.07:56:30.76#ibcon#flushed, iclass 10, count 2 2006.176.07:56:30.76#ibcon#about to write, iclass 10, count 2 2006.176.07:56:30.76#ibcon#wrote, iclass 10, count 2 2006.176.07:56:30.76#ibcon#about to read 3, iclass 10, count 2 2006.176.07:56:30.78#ibcon#read 3, iclass 10, count 2 2006.176.07:56:30.78#ibcon#about to read 4, iclass 10, count 2 2006.176.07:56:30.78#ibcon#read 4, iclass 10, count 2 2006.176.07:56:30.78#ibcon#about to read 5, iclass 10, count 2 2006.176.07:56:30.78#ibcon#read 5, iclass 10, count 2 2006.176.07:56:30.78#ibcon#about to read 6, iclass 10, count 2 2006.176.07:56:30.78#ibcon#read 6, iclass 10, count 2 2006.176.07:56:30.78#ibcon#end of sib2, iclass 10, count 2 2006.176.07:56:30.78#ibcon#*mode == 0, iclass 10, count 2 2006.176.07:56:30.78#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.07:56:30.78#ibcon#[27=AT01-04\r\n] 2006.176.07:56:30.78#ibcon#*before write, iclass 10, count 2 2006.176.07:56:30.78#ibcon#enter sib2, iclass 10, count 2 2006.176.07:56:30.78#ibcon#flushed, iclass 10, count 2 2006.176.07:56:30.78#ibcon#about to write, iclass 10, count 2 2006.176.07:56:30.78#ibcon#wrote, iclass 10, count 2 2006.176.07:56:30.78#ibcon#about to read 3, iclass 10, count 2 2006.176.07:56:30.81#ibcon#read 3, iclass 10, count 2 2006.176.07:56:30.81#ibcon#about to read 4, iclass 10, count 2 2006.176.07:56:30.81#ibcon#read 4, iclass 10, count 2 2006.176.07:56:30.81#ibcon#about to read 5, iclass 10, count 2 2006.176.07:56:30.81#ibcon#read 5, iclass 10, count 2 2006.176.07:56:30.81#ibcon#about to read 6, iclass 10, count 2 2006.176.07:56:30.81#ibcon#read 6, iclass 10, count 2 2006.176.07:56:30.81#ibcon#end of sib2, iclass 10, count 2 2006.176.07:56:30.81#ibcon#*after write, iclass 10, count 2 2006.176.07:56:30.81#ibcon#*before return 0, iclass 10, count 2 2006.176.07:56:30.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:56:30.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:56:30.81#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.07:56:30.81#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:30.81#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:56:30.93#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:56:30.93#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:56:30.93#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:56:30.93#ibcon#first serial, iclass 10, count 0 2006.176.07:56:30.93#ibcon#enter sib2, iclass 10, count 0 2006.176.07:56:30.93#ibcon#flushed, iclass 10, count 0 2006.176.07:56:30.93#ibcon#about to write, iclass 10, count 0 2006.176.07:56:30.93#ibcon#wrote, iclass 10, count 0 2006.176.07:56:30.93#ibcon#about to read 3, iclass 10, count 0 2006.176.07:56:30.95#ibcon#read 3, iclass 10, count 0 2006.176.07:56:30.95#ibcon#about to read 4, iclass 10, count 0 2006.176.07:56:30.95#ibcon#read 4, iclass 10, count 0 2006.176.07:56:30.95#ibcon#about to read 5, iclass 10, count 0 2006.176.07:56:30.95#ibcon#read 5, iclass 10, count 0 2006.176.07:56:30.95#ibcon#about to read 6, iclass 10, count 0 2006.176.07:56:30.95#ibcon#read 6, iclass 10, count 0 2006.176.07:56:30.95#ibcon#end of sib2, iclass 10, count 0 2006.176.07:56:30.95#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:56:30.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:56:30.95#ibcon#[27=USB\r\n] 2006.176.07:56:30.95#ibcon#*before write, iclass 10, count 0 2006.176.07:56:30.95#ibcon#enter sib2, iclass 10, count 0 2006.176.07:56:30.95#ibcon#flushed, iclass 10, count 0 2006.176.07:56:30.95#ibcon#about to write, iclass 10, count 0 2006.176.07:56:30.95#ibcon#wrote, iclass 10, count 0 2006.176.07:56:30.95#ibcon#about to read 3, iclass 10, count 0 2006.176.07:56:30.98#ibcon#read 3, iclass 10, count 0 2006.176.07:56:30.98#ibcon#about to read 4, iclass 10, count 0 2006.176.07:56:30.98#ibcon#read 4, iclass 10, count 0 2006.176.07:56:30.98#ibcon#about to read 5, iclass 10, count 0 2006.176.07:56:30.98#ibcon#read 5, iclass 10, count 0 2006.176.07:56:30.98#ibcon#about to read 6, iclass 10, count 0 2006.176.07:56:30.98#ibcon#read 6, iclass 10, count 0 2006.176.07:56:30.98#ibcon#end of sib2, iclass 10, count 0 2006.176.07:56:30.98#ibcon#*after write, iclass 10, count 0 2006.176.07:56:30.98#ibcon#*before return 0, iclass 10, count 0 2006.176.07:56:30.98#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:56:30.98#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:56:30.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:56:30.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:56:30.98$vc4f8/vblo=2,640.99 2006.176.07:56:30.98#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.07:56:30.98#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.07:56:30.98#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:30.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:30.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:30.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:30.98#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:56:30.98#ibcon#first serial, iclass 12, count 0 2006.176.07:56:30.98#ibcon#enter sib2, iclass 12, count 0 2006.176.07:56:30.98#ibcon#flushed, iclass 12, count 0 2006.176.07:56:30.98#ibcon#about to write, iclass 12, count 0 2006.176.07:56:30.98#ibcon#wrote, iclass 12, count 0 2006.176.07:56:30.98#ibcon#about to read 3, iclass 12, count 0 2006.176.07:56:31.00#ibcon#read 3, iclass 12, count 0 2006.176.07:56:31.00#ibcon#about to read 4, iclass 12, count 0 2006.176.07:56:31.00#ibcon#read 4, iclass 12, count 0 2006.176.07:56:31.00#ibcon#about to read 5, iclass 12, count 0 2006.176.07:56:31.00#ibcon#read 5, iclass 12, count 0 2006.176.07:56:31.00#ibcon#about to read 6, iclass 12, count 0 2006.176.07:56:31.00#ibcon#read 6, iclass 12, count 0 2006.176.07:56:31.00#ibcon#end of sib2, iclass 12, count 0 2006.176.07:56:31.00#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:56:31.00#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:56:31.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.07:56:31.00#ibcon#*before write, iclass 12, count 0 2006.176.07:56:31.00#ibcon#enter sib2, iclass 12, count 0 2006.176.07:56:31.00#ibcon#flushed, iclass 12, count 0 2006.176.07:56:31.00#ibcon#about to write, iclass 12, count 0 2006.176.07:56:31.00#ibcon#wrote, iclass 12, count 0 2006.176.07:56:31.00#ibcon#about to read 3, iclass 12, count 0 2006.176.07:56:31.04#ibcon#read 3, iclass 12, count 0 2006.176.07:56:31.04#ibcon#about to read 4, iclass 12, count 0 2006.176.07:56:31.04#ibcon#read 4, iclass 12, count 0 2006.176.07:56:31.04#ibcon#about to read 5, iclass 12, count 0 2006.176.07:56:31.04#ibcon#read 5, iclass 12, count 0 2006.176.07:56:31.04#ibcon#about to read 6, iclass 12, count 0 2006.176.07:56:31.04#ibcon#read 6, iclass 12, count 0 2006.176.07:56:31.04#ibcon#end of sib2, iclass 12, count 0 2006.176.07:56:31.04#ibcon#*after write, iclass 12, count 0 2006.176.07:56:31.04#ibcon#*before return 0, iclass 12, count 0 2006.176.07:56:31.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:31.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:56:31.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:56:31.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:56:31.04$vc4f8/vb=2,4 2006.176.07:56:31.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.07:56:31.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.07:56:31.04#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:31.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:31.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:31.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:31.10#ibcon#enter wrdev, iclass 14, count 2 2006.176.07:56:31.10#ibcon#first serial, iclass 14, count 2 2006.176.07:56:31.10#ibcon#enter sib2, iclass 14, count 2 2006.176.07:56:31.10#ibcon#flushed, iclass 14, count 2 2006.176.07:56:31.10#ibcon#about to write, iclass 14, count 2 2006.176.07:56:31.10#ibcon#wrote, iclass 14, count 2 2006.176.07:56:31.10#ibcon#about to read 3, iclass 14, count 2 2006.176.07:56:31.12#ibcon#read 3, iclass 14, count 2 2006.176.07:56:31.12#ibcon#about to read 4, iclass 14, count 2 2006.176.07:56:31.12#ibcon#read 4, iclass 14, count 2 2006.176.07:56:31.12#ibcon#about to read 5, iclass 14, count 2 2006.176.07:56:31.12#ibcon#read 5, iclass 14, count 2 2006.176.07:56:31.12#ibcon#about to read 6, iclass 14, count 2 2006.176.07:56:31.12#ibcon#read 6, iclass 14, count 2 2006.176.07:56:31.12#ibcon#end of sib2, iclass 14, count 2 2006.176.07:56:31.12#ibcon#*mode == 0, iclass 14, count 2 2006.176.07:56:31.12#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.07:56:31.12#ibcon#[27=AT02-04\r\n] 2006.176.07:56:31.12#ibcon#*before write, iclass 14, count 2 2006.176.07:56:31.12#ibcon#enter sib2, iclass 14, count 2 2006.176.07:56:31.12#ibcon#flushed, iclass 14, count 2 2006.176.07:56:31.12#ibcon#about to write, iclass 14, count 2 2006.176.07:56:31.12#ibcon#wrote, iclass 14, count 2 2006.176.07:56:31.12#ibcon#about to read 3, iclass 14, count 2 2006.176.07:56:31.15#ibcon#read 3, iclass 14, count 2 2006.176.07:56:31.15#ibcon#about to read 4, iclass 14, count 2 2006.176.07:56:31.15#ibcon#read 4, iclass 14, count 2 2006.176.07:56:31.15#ibcon#about to read 5, iclass 14, count 2 2006.176.07:56:31.15#ibcon#read 5, iclass 14, count 2 2006.176.07:56:31.15#ibcon#about to read 6, iclass 14, count 2 2006.176.07:56:31.15#ibcon#read 6, iclass 14, count 2 2006.176.07:56:31.15#ibcon#end of sib2, iclass 14, count 2 2006.176.07:56:31.15#ibcon#*after write, iclass 14, count 2 2006.176.07:56:31.15#ibcon#*before return 0, iclass 14, count 2 2006.176.07:56:31.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:31.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:56:31.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.07:56:31.15#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:31.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:31.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:31.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:31.27#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:56:31.27#ibcon#first serial, iclass 14, count 0 2006.176.07:56:31.27#ibcon#enter sib2, iclass 14, count 0 2006.176.07:56:31.27#ibcon#flushed, iclass 14, count 0 2006.176.07:56:31.27#ibcon#about to write, iclass 14, count 0 2006.176.07:56:31.27#ibcon#wrote, iclass 14, count 0 2006.176.07:56:31.27#ibcon#about to read 3, iclass 14, count 0 2006.176.07:56:31.29#ibcon#read 3, iclass 14, count 0 2006.176.07:56:31.29#ibcon#about to read 4, iclass 14, count 0 2006.176.07:56:31.29#ibcon#read 4, iclass 14, count 0 2006.176.07:56:31.29#ibcon#about to read 5, iclass 14, count 0 2006.176.07:56:31.29#ibcon#read 5, iclass 14, count 0 2006.176.07:56:31.29#ibcon#about to read 6, iclass 14, count 0 2006.176.07:56:31.29#ibcon#read 6, iclass 14, count 0 2006.176.07:56:31.29#ibcon#end of sib2, iclass 14, count 0 2006.176.07:56:31.29#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:56:31.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:56:31.29#ibcon#[27=USB\r\n] 2006.176.07:56:31.29#ibcon#*before write, iclass 14, count 0 2006.176.07:56:31.29#ibcon#enter sib2, iclass 14, count 0 2006.176.07:56:31.29#ibcon#flushed, iclass 14, count 0 2006.176.07:56:31.29#ibcon#about to write, iclass 14, count 0 2006.176.07:56:31.29#ibcon#wrote, iclass 14, count 0 2006.176.07:56:31.29#ibcon#about to read 3, iclass 14, count 0 2006.176.07:56:31.32#ibcon#read 3, iclass 14, count 0 2006.176.07:56:31.32#ibcon#about to read 4, iclass 14, count 0 2006.176.07:56:31.32#ibcon#read 4, iclass 14, count 0 2006.176.07:56:31.32#ibcon#about to read 5, iclass 14, count 0 2006.176.07:56:31.32#ibcon#read 5, iclass 14, count 0 2006.176.07:56:31.32#ibcon#about to read 6, iclass 14, count 0 2006.176.07:56:31.32#ibcon#read 6, iclass 14, count 0 2006.176.07:56:31.32#ibcon#end of sib2, iclass 14, count 0 2006.176.07:56:31.32#ibcon#*after write, iclass 14, count 0 2006.176.07:56:31.32#ibcon#*before return 0, iclass 14, count 0 2006.176.07:56:31.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:31.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:56:31.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:56:31.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:56:31.32$vc4f8/vblo=3,656.99 2006.176.07:56:31.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:56:31.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:56:31.32#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:31.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:31.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:31.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:31.32#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:56:31.32#ibcon#first serial, iclass 16, count 0 2006.176.07:56:31.32#ibcon#enter sib2, iclass 16, count 0 2006.176.07:56:31.32#ibcon#flushed, iclass 16, count 0 2006.176.07:56:31.32#ibcon#about to write, iclass 16, count 0 2006.176.07:56:31.32#ibcon#wrote, iclass 16, count 0 2006.176.07:56:31.32#ibcon#about to read 3, iclass 16, count 0 2006.176.07:56:31.34#ibcon#read 3, iclass 16, count 0 2006.176.07:56:31.34#ibcon#about to read 4, iclass 16, count 0 2006.176.07:56:31.34#ibcon#read 4, iclass 16, count 0 2006.176.07:56:31.34#ibcon#about to read 5, iclass 16, count 0 2006.176.07:56:31.34#ibcon#read 5, iclass 16, count 0 2006.176.07:56:31.34#ibcon#about to read 6, iclass 16, count 0 2006.176.07:56:31.34#ibcon#read 6, iclass 16, count 0 2006.176.07:56:31.34#ibcon#end of sib2, iclass 16, count 0 2006.176.07:56:31.34#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:56:31.34#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:56:31.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.07:56:31.34#ibcon#*before write, iclass 16, count 0 2006.176.07:56:31.34#ibcon#enter sib2, iclass 16, count 0 2006.176.07:56:31.34#ibcon#flushed, iclass 16, count 0 2006.176.07:56:31.34#ibcon#about to write, iclass 16, count 0 2006.176.07:56:31.34#ibcon#wrote, iclass 16, count 0 2006.176.07:56:31.34#ibcon#about to read 3, iclass 16, count 0 2006.176.07:56:31.38#ibcon#read 3, iclass 16, count 0 2006.176.07:56:31.38#ibcon#about to read 4, iclass 16, count 0 2006.176.07:56:31.38#ibcon#read 4, iclass 16, count 0 2006.176.07:56:31.38#ibcon#about to read 5, iclass 16, count 0 2006.176.07:56:31.38#ibcon#read 5, iclass 16, count 0 2006.176.07:56:31.38#ibcon#about to read 6, iclass 16, count 0 2006.176.07:56:31.38#ibcon#read 6, iclass 16, count 0 2006.176.07:56:31.38#ibcon#end of sib2, iclass 16, count 0 2006.176.07:56:31.38#ibcon#*after write, iclass 16, count 0 2006.176.07:56:31.38#ibcon#*before return 0, iclass 16, count 0 2006.176.07:56:31.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:31.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:56:31.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:56:31.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:56:31.38$vc4f8/vb=3,4 2006.176.07:56:31.38#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.07:56:31.38#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.07:56:31.38#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:31.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:31.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:31.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:31.44#ibcon#enter wrdev, iclass 18, count 2 2006.176.07:56:31.44#ibcon#first serial, iclass 18, count 2 2006.176.07:56:31.44#ibcon#enter sib2, iclass 18, count 2 2006.176.07:56:31.44#ibcon#flushed, iclass 18, count 2 2006.176.07:56:31.44#ibcon#about to write, iclass 18, count 2 2006.176.07:56:31.44#ibcon#wrote, iclass 18, count 2 2006.176.07:56:31.44#ibcon#about to read 3, iclass 18, count 2 2006.176.07:56:31.46#ibcon#read 3, iclass 18, count 2 2006.176.07:56:31.46#ibcon#about to read 4, iclass 18, count 2 2006.176.07:56:31.46#ibcon#read 4, iclass 18, count 2 2006.176.07:56:31.46#ibcon#about to read 5, iclass 18, count 2 2006.176.07:56:31.46#ibcon#read 5, iclass 18, count 2 2006.176.07:56:31.46#ibcon#about to read 6, iclass 18, count 2 2006.176.07:56:31.46#ibcon#read 6, iclass 18, count 2 2006.176.07:56:31.46#ibcon#end of sib2, iclass 18, count 2 2006.176.07:56:31.46#ibcon#*mode == 0, iclass 18, count 2 2006.176.07:56:31.46#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.07:56:31.46#ibcon#[27=AT03-04\r\n] 2006.176.07:56:31.46#ibcon#*before write, iclass 18, count 2 2006.176.07:56:31.46#ibcon#enter sib2, iclass 18, count 2 2006.176.07:56:31.46#ibcon#flushed, iclass 18, count 2 2006.176.07:56:31.46#ibcon#about to write, iclass 18, count 2 2006.176.07:56:31.46#ibcon#wrote, iclass 18, count 2 2006.176.07:56:31.46#ibcon#about to read 3, iclass 18, count 2 2006.176.07:56:31.49#ibcon#read 3, iclass 18, count 2 2006.176.07:56:31.49#ibcon#about to read 4, iclass 18, count 2 2006.176.07:56:31.49#ibcon#read 4, iclass 18, count 2 2006.176.07:56:31.49#ibcon#about to read 5, iclass 18, count 2 2006.176.07:56:31.49#ibcon#read 5, iclass 18, count 2 2006.176.07:56:31.49#ibcon#about to read 6, iclass 18, count 2 2006.176.07:56:31.49#ibcon#read 6, iclass 18, count 2 2006.176.07:56:31.49#ibcon#end of sib2, iclass 18, count 2 2006.176.07:56:31.49#ibcon#*after write, iclass 18, count 2 2006.176.07:56:31.49#ibcon#*before return 0, iclass 18, count 2 2006.176.07:56:31.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:31.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:56:31.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.07:56:31.49#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:31.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:31.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:31.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:31.61#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:56:31.61#ibcon#first serial, iclass 18, count 0 2006.176.07:56:31.61#ibcon#enter sib2, iclass 18, count 0 2006.176.07:56:31.61#ibcon#flushed, iclass 18, count 0 2006.176.07:56:31.61#ibcon#about to write, iclass 18, count 0 2006.176.07:56:31.61#ibcon#wrote, iclass 18, count 0 2006.176.07:56:31.61#ibcon#about to read 3, iclass 18, count 0 2006.176.07:56:31.63#ibcon#read 3, iclass 18, count 0 2006.176.07:56:31.63#ibcon#about to read 4, iclass 18, count 0 2006.176.07:56:31.63#ibcon#read 4, iclass 18, count 0 2006.176.07:56:31.63#ibcon#about to read 5, iclass 18, count 0 2006.176.07:56:31.63#ibcon#read 5, iclass 18, count 0 2006.176.07:56:31.63#ibcon#about to read 6, iclass 18, count 0 2006.176.07:56:31.63#ibcon#read 6, iclass 18, count 0 2006.176.07:56:31.63#ibcon#end of sib2, iclass 18, count 0 2006.176.07:56:31.63#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:56:31.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:56:31.63#ibcon#[27=USB\r\n] 2006.176.07:56:31.63#ibcon#*before write, iclass 18, count 0 2006.176.07:56:31.63#ibcon#enter sib2, iclass 18, count 0 2006.176.07:56:31.63#ibcon#flushed, iclass 18, count 0 2006.176.07:56:31.63#ibcon#about to write, iclass 18, count 0 2006.176.07:56:31.63#ibcon#wrote, iclass 18, count 0 2006.176.07:56:31.63#ibcon#about to read 3, iclass 18, count 0 2006.176.07:56:31.66#ibcon#read 3, iclass 18, count 0 2006.176.07:56:31.66#ibcon#about to read 4, iclass 18, count 0 2006.176.07:56:31.66#ibcon#read 4, iclass 18, count 0 2006.176.07:56:31.66#ibcon#about to read 5, iclass 18, count 0 2006.176.07:56:31.66#ibcon#read 5, iclass 18, count 0 2006.176.07:56:31.66#ibcon#about to read 6, iclass 18, count 0 2006.176.07:56:31.66#ibcon#read 6, iclass 18, count 0 2006.176.07:56:31.66#ibcon#end of sib2, iclass 18, count 0 2006.176.07:56:31.66#ibcon#*after write, iclass 18, count 0 2006.176.07:56:31.66#ibcon#*before return 0, iclass 18, count 0 2006.176.07:56:31.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:31.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:56:31.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:56:31.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:56:31.66$vc4f8/vblo=4,712.99 2006.176.07:56:31.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.07:56:31.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.07:56:31.66#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:31.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:31.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:31.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:31.66#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:56:31.66#ibcon#first serial, iclass 20, count 0 2006.176.07:56:31.66#ibcon#enter sib2, iclass 20, count 0 2006.176.07:56:31.66#ibcon#flushed, iclass 20, count 0 2006.176.07:56:31.66#ibcon#about to write, iclass 20, count 0 2006.176.07:56:31.66#ibcon#wrote, iclass 20, count 0 2006.176.07:56:31.66#ibcon#about to read 3, iclass 20, count 0 2006.176.07:56:31.68#ibcon#read 3, iclass 20, count 0 2006.176.07:56:31.68#ibcon#about to read 4, iclass 20, count 0 2006.176.07:56:31.68#ibcon#read 4, iclass 20, count 0 2006.176.07:56:31.68#ibcon#about to read 5, iclass 20, count 0 2006.176.07:56:31.68#ibcon#read 5, iclass 20, count 0 2006.176.07:56:31.68#ibcon#about to read 6, iclass 20, count 0 2006.176.07:56:31.68#ibcon#read 6, iclass 20, count 0 2006.176.07:56:31.68#ibcon#end of sib2, iclass 20, count 0 2006.176.07:56:31.68#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:56:31.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:56:31.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.07:56:31.68#ibcon#*before write, iclass 20, count 0 2006.176.07:56:31.68#ibcon#enter sib2, iclass 20, count 0 2006.176.07:56:31.68#ibcon#flushed, iclass 20, count 0 2006.176.07:56:31.68#ibcon#about to write, iclass 20, count 0 2006.176.07:56:31.68#ibcon#wrote, iclass 20, count 0 2006.176.07:56:31.68#ibcon#about to read 3, iclass 20, count 0 2006.176.07:56:31.72#ibcon#read 3, iclass 20, count 0 2006.176.07:56:31.72#ibcon#about to read 4, iclass 20, count 0 2006.176.07:56:31.72#ibcon#read 4, iclass 20, count 0 2006.176.07:56:31.72#ibcon#about to read 5, iclass 20, count 0 2006.176.07:56:31.72#ibcon#read 5, iclass 20, count 0 2006.176.07:56:31.72#ibcon#about to read 6, iclass 20, count 0 2006.176.07:56:31.72#ibcon#read 6, iclass 20, count 0 2006.176.07:56:31.72#ibcon#end of sib2, iclass 20, count 0 2006.176.07:56:31.72#ibcon#*after write, iclass 20, count 0 2006.176.07:56:31.72#ibcon#*before return 0, iclass 20, count 0 2006.176.07:56:31.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:31.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:56:31.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:56:31.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:56:31.72$vc4f8/vb=4,4 2006.176.07:56:31.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.07:56:31.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.07:56:31.72#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:31.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:31.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:31.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:31.78#ibcon#enter wrdev, iclass 22, count 2 2006.176.07:56:31.78#ibcon#first serial, iclass 22, count 2 2006.176.07:56:31.78#ibcon#enter sib2, iclass 22, count 2 2006.176.07:56:31.78#ibcon#flushed, iclass 22, count 2 2006.176.07:56:31.78#ibcon#about to write, iclass 22, count 2 2006.176.07:56:31.78#ibcon#wrote, iclass 22, count 2 2006.176.07:56:31.78#ibcon#about to read 3, iclass 22, count 2 2006.176.07:56:31.80#ibcon#read 3, iclass 22, count 2 2006.176.07:56:31.80#ibcon#about to read 4, iclass 22, count 2 2006.176.07:56:31.80#ibcon#read 4, iclass 22, count 2 2006.176.07:56:31.80#ibcon#about to read 5, iclass 22, count 2 2006.176.07:56:31.80#ibcon#read 5, iclass 22, count 2 2006.176.07:56:31.80#ibcon#about to read 6, iclass 22, count 2 2006.176.07:56:31.80#ibcon#read 6, iclass 22, count 2 2006.176.07:56:31.80#ibcon#end of sib2, iclass 22, count 2 2006.176.07:56:31.80#ibcon#*mode == 0, iclass 22, count 2 2006.176.07:56:31.80#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.07:56:31.80#ibcon#[27=AT04-04\r\n] 2006.176.07:56:31.80#ibcon#*before write, iclass 22, count 2 2006.176.07:56:31.80#ibcon#enter sib2, iclass 22, count 2 2006.176.07:56:31.80#ibcon#flushed, iclass 22, count 2 2006.176.07:56:31.80#ibcon#about to write, iclass 22, count 2 2006.176.07:56:31.80#ibcon#wrote, iclass 22, count 2 2006.176.07:56:31.80#ibcon#about to read 3, iclass 22, count 2 2006.176.07:56:31.83#ibcon#read 3, iclass 22, count 2 2006.176.07:56:31.83#ibcon#about to read 4, iclass 22, count 2 2006.176.07:56:31.83#ibcon#read 4, iclass 22, count 2 2006.176.07:56:31.83#ibcon#about to read 5, iclass 22, count 2 2006.176.07:56:31.83#ibcon#read 5, iclass 22, count 2 2006.176.07:56:31.83#ibcon#about to read 6, iclass 22, count 2 2006.176.07:56:31.83#ibcon#read 6, iclass 22, count 2 2006.176.07:56:31.83#ibcon#end of sib2, iclass 22, count 2 2006.176.07:56:31.83#ibcon#*after write, iclass 22, count 2 2006.176.07:56:31.83#ibcon#*before return 0, iclass 22, count 2 2006.176.07:56:31.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:31.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:56:31.83#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.07:56:31.83#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:31.83#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:31.95#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:31.95#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:31.95#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:56:31.95#ibcon#first serial, iclass 22, count 0 2006.176.07:56:31.95#ibcon#enter sib2, iclass 22, count 0 2006.176.07:56:31.95#ibcon#flushed, iclass 22, count 0 2006.176.07:56:31.95#ibcon#about to write, iclass 22, count 0 2006.176.07:56:31.95#ibcon#wrote, iclass 22, count 0 2006.176.07:56:31.95#ibcon#about to read 3, iclass 22, count 0 2006.176.07:56:31.97#ibcon#read 3, iclass 22, count 0 2006.176.07:56:31.97#ibcon#about to read 4, iclass 22, count 0 2006.176.07:56:31.97#ibcon#read 4, iclass 22, count 0 2006.176.07:56:31.97#ibcon#about to read 5, iclass 22, count 0 2006.176.07:56:31.97#ibcon#read 5, iclass 22, count 0 2006.176.07:56:31.97#ibcon#about to read 6, iclass 22, count 0 2006.176.07:56:31.97#ibcon#read 6, iclass 22, count 0 2006.176.07:56:31.97#ibcon#end of sib2, iclass 22, count 0 2006.176.07:56:31.97#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:56:31.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:56:31.97#ibcon#[27=USB\r\n] 2006.176.07:56:31.97#ibcon#*before write, iclass 22, count 0 2006.176.07:56:31.97#ibcon#enter sib2, iclass 22, count 0 2006.176.07:56:31.97#ibcon#flushed, iclass 22, count 0 2006.176.07:56:31.97#ibcon#about to write, iclass 22, count 0 2006.176.07:56:31.97#ibcon#wrote, iclass 22, count 0 2006.176.07:56:31.97#ibcon#about to read 3, iclass 22, count 0 2006.176.07:56:32.00#ibcon#read 3, iclass 22, count 0 2006.176.07:56:32.00#ibcon#about to read 4, iclass 22, count 0 2006.176.07:56:32.00#ibcon#read 4, iclass 22, count 0 2006.176.07:56:32.00#ibcon#about to read 5, iclass 22, count 0 2006.176.07:56:32.00#ibcon#read 5, iclass 22, count 0 2006.176.07:56:32.00#ibcon#about to read 6, iclass 22, count 0 2006.176.07:56:32.00#ibcon#read 6, iclass 22, count 0 2006.176.07:56:32.00#ibcon#end of sib2, iclass 22, count 0 2006.176.07:56:32.00#ibcon#*after write, iclass 22, count 0 2006.176.07:56:32.00#ibcon#*before return 0, iclass 22, count 0 2006.176.07:56:32.00#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:32.00#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:56:32.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:56:32.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:56:32.00$vc4f8/vblo=5,744.99 2006.176.07:56:32.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.07:56:32.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.07:56:32.00#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:32.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:32.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:32.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:32.00#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:56:32.00#ibcon#first serial, iclass 24, count 0 2006.176.07:56:32.00#ibcon#enter sib2, iclass 24, count 0 2006.176.07:56:32.00#ibcon#flushed, iclass 24, count 0 2006.176.07:56:32.00#ibcon#about to write, iclass 24, count 0 2006.176.07:56:32.00#ibcon#wrote, iclass 24, count 0 2006.176.07:56:32.00#ibcon#about to read 3, iclass 24, count 0 2006.176.07:56:32.02#ibcon#read 3, iclass 24, count 0 2006.176.07:56:32.02#ibcon#about to read 4, iclass 24, count 0 2006.176.07:56:32.02#ibcon#read 4, iclass 24, count 0 2006.176.07:56:32.02#ibcon#about to read 5, iclass 24, count 0 2006.176.07:56:32.02#ibcon#read 5, iclass 24, count 0 2006.176.07:56:32.02#ibcon#about to read 6, iclass 24, count 0 2006.176.07:56:32.02#ibcon#read 6, iclass 24, count 0 2006.176.07:56:32.02#ibcon#end of sib2, iclass 24, count 0 2006.176.07:56:32.02#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:56:32.02#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:56:32.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.07:56:32.02#ibcon#*before write, iclass 24, count 0 2006.176.07:56:32.02#ibcon#enter sib2, iclass 24, count 0 2006.176.07:56:32.02#ibcon#flushed, iclass 24, count 0 2006.176.07:56:32.02#ibcon#about to write, iclass 24, count 0 2006.176.07:56:32.02#ibcon#wrote, iclass 24, count 0 2006.176.07:56:32.02#ibcon#about to read 3, iclass 24, count 0 2006.176.07:56:32.06#ibcon#read 3, iclass 24, count 0 2006.176.07:56:32.06#ibcon#about to read 4, iclass 24, count 0 2006.176.07:56:32.06#ibcon#read 4, iclass 24, count 0 2006.176.07:56:32.06#ibcon#about to read 5, iclass 24, count 0 2006.176.07:56:32.06#ibcon#read 5, iclass 24, count 0 2006.176.07:56:32.06#ibcon#about to read 6, iclass 24, count 0 2006.176.07:56:32.06#ibcon#read 6, iclass 24, count 0 2006.176.07:56:32.06#ibcon#end of sib2, iclass 24, count 0 2006.176.07:56:32.06#ibcon#*after write, iclass 24, count 0 2006.176.07:56:32.06#ibcon#*before return 0, iclass 24, count 0 2006.176.07:56:32.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:32.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:56:32.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:56:32.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:56:32.06$vc4f8/vb=5,4 2006.176.07:56:32.06#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.07:56:32.06#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.07:56:32.06#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:32.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:32.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:32.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:32.12#ibcon#enter wrdev, iclass 26, count 2 2006.176.07:56:32.12#ibcon#first serial, iclass 26, count 2 2006.176.07:56:32.12#ibcon#enter sib2, iclass 26, count 2 2006.176.07:56:32.12#ibcon#flushed, iclass 26, count 2 2006.176.07:56:32.12#ibcon#about to write, iclass 26, count 2 2006.176.07:56:32.12#ibcon#wrote, iclass 26, count 2 2006.176.07:56:32.12#ibcon#about to read 3, iclass 26, count 2 2006.176.07:56:32.14#ibcon#read 3, iclass 26, count 2 2006.176.07:56:32.14#ibcon#about to read 4, iclass 26, count 2 2006.176.07:56:32.14#ibcon#read 4, iclass 26, count 2 2006.176.07:56:32.14#ibcon#about to read 5, iclass 26, count 2 2006.176.07:56:32.14#ibcon#read 5, iclass 26, count 2 2006.176.07:56:32.14#ibcon#about to read 6, iclass 26, count 2 2006.176.07:56:32.14#ibcon#read 6, iclass 26, count 2 2006.176.07:56:32.14#ibcon#end of sib2, iclass 26, count 2 2006.176.07:56:32.14#ibcon#*mode == 0, iclass 26, count 2 2006.176.07:56:32.14#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.07:56:32.14#ibcon#[27=AT05-04\r\n] 2006.176.07:56:32.14#ibcon#*before write, iclass 26, count 2 2006.176.07:56:32.14#ibcon#enter sib2, iclass 26, count 2 2006.176.07:56:32.14#ibcon#flushed, iclass 26, count 2 2006.176.07:56:32.14#ibcon#about to write, iclass 26, count 2 2006.176.07:56:32.14#ibcon#wrote, iclass 26, count 2 2006.176.07:56:32.14#ibcon#about to read 3, iclass 26, count 2 2006.176.07:56:32.17#ibcon#read 3, iclass 26, count 2 2006.176.07:56:32.17#ibcon#about to read 4, iclass 26, count 2 2006.176.07:56:32.17#ibcon#read 4, iclass 26, count 2 2006.176.07:56:32.17#ibcon#about to read 5, iclass 26, count 2 2006.176.07:56:32.17#ibcon#read 5, iclass 26, count 2 2006.176.07:56:32.17#ibcon#about to read 6, iclass 26, count 2 2006.176.07:56:32.17#ibcon#read 6, iclass 26, count 2 2006.176.07:56:32.17#ibcon#end of sib2, iclass 26, count 2 2006.176.07:56:32.17#ibcon#*after write, iclass 26, count 2 2006.176.07:56:32.17#ibcon#*before return 0, iclass 26, count 2 2006.176.07:56:32.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:32.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:56:32.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.07:56:32.17#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:32.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:32.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:32.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:32.29#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:56:32.29#ibcon#first serial, iclass 26, count 0 2006.176.07:56:32.29#ibcon#enter sib2, iclass 26, count 0 2006.176.07:56:32.29#ibcon#flushed, iclass 26, count 0 2006.176.07:56:32.29#ibcon#about to write, iclass 26, count 0 2006.176.07:56:32.29#ibcon#wrote, iclass 26, count 0 2006.176.07:56:32.29#ibcon#about to read 3, iclass 26, count 0 2006.176.07:56:32.31#ibcon#read 3, iclass 26, count 0 2006.176.07:56:32.31#ibcon#about to read 4, iclass 26, count 0 2006.176.07:56:32.31#ibcon#read 4, iclass 26, count 0 2006.176.07:56:32.31#ibcon#about to read 5, iclass 26, count 0 2006.176.07:56:32.31#ibcon#read 5, iclass 26, count 0 2006.176.07:56:32.31#ibcon#about to read 6, iclass 26, count 0 2006.176.07:56:32.31#ibcon#read 6, iclass 26, count 0 2006.176.07:56:32.31#ibcon#end of sib2, iclass 26, count 0 2006.176.07:56:32.31#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:56:32.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:56:32.31#ibcon#[27=USB\r\n] 2006.176.07:56:32.31#ibcon#*before write, iclass 26, count 0 2006.176.07:56:32.31#ibcon#enter sib2, iclass 26, count 0 2006.176.07:56:32.31#ibcon#flushed, iclass 26, count 0 2006.176.07:56:32.31#ibcon#about to write, iclass 26, count 0 2006.176.07:56:32.31#ibcon#wrote, iclass 26, count 0 2006.176.07:56:32.31#ibcon#about to read 3, iclass 26, count 0 2006.176.07:56:32.34#ibcon#read 3, iclass 26, count 0 2006.176.07:56:32.34#ibcon#about to read 4, iclass 26, count 0 2006.176.07:56:32.34#ibcon#read 4, iclass 26, count 0 2006.176.07:56:32.34#ibcon#about to read 5, iclass 26, count 0 2006.176.07:56:32.34#ibcon#read 5, iclass 26, count 0 2006.176.07:56:32.34#ibcon#about to read 6, iclass 26, count 0 2006.176.07:56:32.34#ibcon#read 6, iclass 26, count 0 2006.176.07:56:32.34#ibcon#end of sib2, iclass 26, count 0 2006.176.07:56:32.34#ibcon#*after write, iclass 26, count 0 2006.176.07:56:32.34#ibcon#*before return 0, iclass 26, count 0 2006.176.07:56:32.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:32.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:56:32.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:56:32.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:56:32.34$vc4f8/vblo=6,752.99 2006.176.07:56:32.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.07:56:32.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.07:56:32.34#ibcon#ireg 17 cls_cnt 0 2006.176.07:56:32.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:32.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:32.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:32.34#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:56:32.34#ibcon#first serial, iclass 28, count 0 2006.176.07:56:32.34#ibcon#enter sib2, iclass 28, count 0 2006.176.07:56:32.34#ibcon#flushed, iclass 28, count 0 2006.176.07:56:32.34#ibcon#about to write, iclass 28, count 0 2006.176.07:56:32.34#ibcon#wrote, iclass 28, count 0 2006.176.07:56:32.34#ibcon#about to read 3, iclass 28, count 0 2006.176.07:56:32.36#ibcon#read 3, iclass 28, count 0 2006.176.07:56:32.36#ibcon#about to read 4, iclass 28, count 0 2006.176.07:56:32.36#ibcon#read 4, iclass 28, count 0 2006.176.07:56:32.36#ibcon#about to read 5, iclass 28, count 0 2006.176.07:56:32.36#ibcon#read 5, iclass 28, count 0 2006.176.07:56:32.36#ibcon#about to read 6, iclass 28, count 0 2006.176.07:56:32.36#ibcon#read 6, iclass 28, count 0 2006.176.07:56:32.36#ibcon#end of sib2, iclass 28, count 0 2006.176.07:56:32.36#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:56:32.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:56:32.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.07:56:32.36#ibcon#*before write, iclass 28, count 0 2006.176.07:56:32.36#ibcon#enter sib2, iclass 28, count 0 2006.176.07:56:32.36#ibcon#flushed, iclass 28, count 0 2006.176.07:56:32.36#ibcon#about to write, iclass 28, count 0 2006.176.07:56:32.36#ibcon#wrote, iclass 28, count 0 2006.176.07:56:32.36#ibcon#about to read 3, iclass 28, count 0 2006.176.07:56:32.40#ibcon#read 3, iclass 28, count 0 2006.176.07:56:32.40#ibcon#about to read 4, iclass 28, count 0 2006.176.07:56:32.40#ibcon#read 4, iclass 28, count 0 2006.176.07:56:32.40#ibcon#about to read 5, iclass 28, count 0 2006.176.07:56:32.40#ibcon#read 5, iclass 28, count 0 2006.176.07:56:32.40#ibcon#about to read 6, iclass 28, count 0 2006.176.07:56:32.40#ibcon#read 6, iclass 28, count 0 2006.176.07:56:32.40#ibcon#end of sib2, iclass 28, count 0 2006.176.07:56:32.40#ibcon#*after write, iclass 28, count 0 2006.176.07:56:32.40#ibcon#*before return 0, iclass 28, count 0 2006.176.07:56:32.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:32.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:56:32.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.07:56:32.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.07:56:32.40$vc4f8/vb=6,4 2006.176.07:56:32.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.07:56:32.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.07:56:32.40#ibcon#ireg 11 cls_cnt 2 2006.176.07:56:32.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:32.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:32.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:32.46#ibcon#enter wrdev, iclass 30, count 2 2006.176.07:56:32.46#ibcon#first serial, iclass 30, count 2 2006.176.07:56:32.46#ibcon#enter sib2, iclass 30, count 2 2006.176.07:56:32.46#ibcon#flushed, iclass 30, count 2 2006.176.07:56:32.46#ibcon#about to write, iclass 30, count 2 2006.176.07:56:32.46#ibcon#wrote, iclass 30, count 2 2006.176.07:56:32.46#ibcon#about to read 3, iclass 30, count 2 2006.176.07:56:32.48#ibcon#read 3, iclass 30, count 2 2006.176.07:56:32.48#ibcon#about to read 4, iclass 30, count 2 2006.176.07:56:32.48#ibcon#read 4, iclass 30, count 2 2006.176.07:56:32.48#ibcon#about to read 5, iclass 30, count 2 2006.176.07:56:32.48#ibcon#read 5, iclass 30, count 2 2006.176.07:56:32.48#ibcon#about to read 6, iclass 30, count 2 2006.176.07:56:32.48#ibcon#read 6, iclass 30, count 2 2006.176.07:56:32.48#ibcon#end of sib2, iclass 30, count 2 2006.176.07:56:32.48#ibcon#*mode == 0, iclass 30, count 2 2006.176.07:56:32.48#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.07:56:32.48#ibcon#[27=AT06-04\r\n] 2006.176.07:56:32.48#ibcon#*before write, iclass 30, count 2 2006.176.07:56:32.48#ibcon#enter sib2, iclass 30, count 2 2006.176.07:56:32.48#ibcon#flushed, iclass 30, count 2 2006.176.07:56:32.48#ibcon#about to write, iclass 30, count 2 2006.176.07:56:32.48#ibcon#wrote, iclass 30, count 2 2006.176.07:56:32.48#ibcon#about to read 3, iclass 30, count 2 2006.176.07:56:32.51#ibcon#read 3, iclass 30, count 2 2006.176.07:56:32.51#ibcon#about to read 4, iclass 30, count 2 2006.176.07:56:32.51#ibcon#read 4, iclass 30, count 2 2006.176.07:56:32.51#ibcon#about to read 5, iclass 30, count 2 2006.176.07:56:32.51#ibcon#read 5, iclass 30, count 2 2006.176.07:56:32.51#ibcon#about to read 6, iclass 30, count 2 2006.176.07:56:32.51#ibcon#read 6, iclass 30, count 2 2006.176.07:56:32.51#ibcon#end of sib2, iclass 30, count 2 2006.176.07:56:32.51#ibcon#*after write, iclass 30, count 2 2006.176.07:56:32.51#ibcon#*before return 0, iclass 30, count 2 2006.176.07:56:32.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:32.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.07:56:32.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.07:56:32.51#ibcon#ireg 7 cls_cnt 0 2006.176.07:56:32.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:32.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:32.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:32.63#ibcon#enter wrdev, iclass 30, count 0 2006.176.07:56:32.63#ibcon#first serial, iclass 30, count 0 2006.176.07:56:32.63#ibcon#enter sib2, iclass 30, count 0 2006.176.07:56:32.63#ibcon#flushed, iclass 30, count 0 2006.176.07:56:32.63#ibcon#about to write, iclass 30, count 0 2006.176.07:56:32.63#ibcon#wrote, iclass 30, count 0 2006.176.07:56:32.63#ibcon#about to read 3, iclass 30, count 0 2006.176.07:56:32.65#ibcon#read 3, iclass 30, count 0 2006.176.07:56:32.65#ibcon#about to read 4, iclass 30, count 0 2006.176.07:56:32.65#ibcon#read 4, iclass 30, count 0 2006.176.07:56:32.65#ibcon#about to read 5, iclass 30, count 0 2006.176.07:56:32.65#ibcon#read 5, iclass 30, count 0 2006.176.07:56:32.65#ibcon#about to read 6, iclass 30, count 0 2006.176.07:56:32.65#ibcon#read 6, iclass 30, count 0 2006.176.07:56:32.65#ibcon#end of sib2, iclass 30, count 0 2006.176.07:56:32.65#ibcon#*mode == 0, iclass 30, count 0 2006.176.07:56:32.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.07:56:32.65#ibcon#[27=USB\r\n] 2006.176.07:56:32.65#ibcon#*before write, iclass 30, count 0 2006.176.07:56:32.65#ibcon#enter sib2, iclass 30, count 0 2006.176.07:56:32.65#ibcon#flushed, iclass 30, count 0 2006.176.07:56:32.65#ibcon#about to write, iclass 30, count 0 2006.176.07:56:32.65#ibcon#wrote, iclass 30, count 0 2006.176.07:56:32.65#ibcon#about to read 3, iclass 30, count 0 2006.176.07:56:32.68#ibcon#read 3, iclass 30, count 0 2006.176.07:56:32.68#ibcon#about to read 4, iclass 30, count 0 2006.176.07:56:32.68#ibcon#read 4, iclass 30, count 0 2006.176.07:56:32.68#ibcon#about to read 5, iclass 30, count 0 2006.176.07:56:32.68#ibcon#read 5, iclass 30, count 0 2006.176.07:56:32.68#ibcon#about to read 6, iclass 30, count 0 2006.176.07:56:32.68#ibcon#read 6, iclass 30, count 0 2006.176.07:56:32.68#ibcon#end of sib2, iclass 30, count 0 2006.176.07:56:32.68#ibcon#*after write, iclass 30, count 0 2006.176.07:56:32.68#ibcon#*before return 0, iclass 30, count 0 2006.176.07:56:32.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:32.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.07:56:32.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.07:56:32.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.07:56:32.68$vc4f8/vabw=wide 2006.176.07:56:32.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.07:56:32.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.07:56:32.68#ibcon#ireg 8 cls_cnt 0 2006.176.07:56:32.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:32.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:32.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:32.68#ibcon#enter wrdev, iclass 32, count 0 2006.176.07:56:32.68#ibcon#first serial, iclass 32, count 0 2006.176.07:56:32.68#ibcon#enter sib2, iclass 32, count 0 2006.176.07:56:32.68#ibcon#flushed, iclass 32, count 0 2006.176.07:56:32.68#ibcon#about to write, iclass 32, count 0 2006.176.07:56:32.68#ibcon#wrote, iclass 32, count 0 2006.176.07:56:32.68#ibcon#about to read 3, iclass 32, count 0 2006.176.07:56:32.70#ibcon#read 3, iclass 32, count 0 2006.176.07:56:32.70#ibcon#about to read 4, iclass 32, count 0 2006.176.07:56:32.70#ibcon#read 4, iclass 32, count 0 2006.176.07:56:32.70#ibcon#about to read 5, iclass 32, count 0 2006.176.07:56:32.70#ibcon#read 5, iclass 32, count 0 2006.176.07:56:32.70#ibcon#about to read 6, iclass 32, count 0 2006.176.07:56:32.70#ibcon#read 6, iclass 32, count 0 2006.176.07:56:32.70#ibcon#end of sib2, iclass 32, count 0 2006.176.07:56:32.70#ibcon#*mode == 0, iclass 32, count 0 2006.176.07:56:32.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.07:56:32.70#ibcon#[25=BW32\r\n] 2006.176.07:56:32.70#ibcon#*before write, iclass 32, count 0 2006.176.07:56:32.70#ibcon#enter sib2, iclass 32, count 0 2006.176.07:56:32.70#ibcon#flushed, iclass 32, count 0 2006.176.07:56:32.70#ibcon#about to write, iclass 32, count 0 2006.176.07:56:32.70#ibcon#wrote, iclass 32, count 0 2006.176.07:56:32.70#ibcon#about to read 3, iclass 32, count 0 2006.176.07:56:32.73#ibcon#read 3, iclass 32, count 0 2006.176.07:56:32.73#ibcon#about to read 4, iclass 32, count 0 2006.176.07:56:32.73#ibcon#read 4, iclass 32, count 0 2006.176.07:56:32.73#ibcon#about to read 5, iclass 32, count 0 2006.176.07:56:32.73#ibcon#read 5, iclass 32, count 0 2006.176.07:56:32.73#ibcon#about to read 6, iclass 32, count 0 2006.176.07:56:32.73#ibcon#read 6, iclass 32, count 0 2006.176.07:56:32.73#ibcon#end of sib2, iclass 32, count 0 2006.176.07:56:32.73#ibcon#*after write, iclass 32, count 0 2006.176.07:56:32.73#ibcon#*before return 0, iclass 32, count 0 2006.176.07:56:32.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:32.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.07:56:32.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.07:56:32.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.07:56:32.73$vc4f8/vbbw=wide 2006.176.07:56:32.73#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.07:56:32.73#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.07:56:32.73#ibcon#ireg 8 cls_cnt 0 2006.176.07:56:32.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:56:32.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:56:32.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:56:32.80#ibcon#enter wrdev, iclass 34, count 0 2006.176.07:56:32.80#ibcon#first serial, iclass 34, count 0 2006.176.07:56:32.80#ibcon#enter sib2, iclass 34, count 0 2006.176.07:56:32.80#ibcon#flushed, iclass 34, count 0 2006.176.07:56:32.80#ibcon#about to write, iclass 34, count 0 2006.176.07:56:32.80#ibcon#wrote, iclass 34, count 0 2006.176.07:56:32.80#ibcon#about to read 3, iclass 34, count 0 2006.176.07:56:32.82#ibcon#read 3, iclass 34, count 0 2006.176.07:56:32.82#ibcon#about to read 4, iclass 34, count 0 2006.176.07:56:32.82#ibcon#read 4, iclass 34, count 0 2006.176.07:56:32.82#ibcon#about to read 5, iclass 34, count 0 2006.176.07:56:32.82#ibcon#read 5, iclass 34, count 0 2006.176.07:56:32.82#ibcon#about to read 6, iclass 34, count 0 2006.176.07:56:32.82#ibcon#read 6, iclass 34, count 0 2006.176.07:56:32.82#ibcon#end of sib2, iclass 34, count 0 2006.176.07:56:32.82#ibcon#*mode == 0, iclass 34, count 0 2006.176.07:56:32.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.07:56:32.82#ibcon#[27=BW32\r\n] 2006.176.07:56:32.82#ibcon#*before write, iclass 34, count 0 2006.176.07:56:32.82#ibcon#enter sib2, iclass 34, count 0 2006.176.07:56:32.82#ibcon#flushed, iclass 34, count 0 2006.176.07:56:32.82#ibcon#about to write, iclass 34, count 0 2006.176.07:56:32.82#ibcon#wrote, iclass 34, count 0 2006.176.07:56:32.82#ibcon#about to read 3, iclass 34, count 0 2006.176.07:56:32.85#ibcon#read 3, iclass 34, count 0 2006.176.07:56:32.85#ibcon#about to read 4, iclass 34, count 0 2006.176.07:56:32.85#ibcon#read 4, iclass 34, count 0 2006.176.07:56:32.85#ibcon#about to read 5, iclass 34, count 0 2006.176.07:56:32.85#ibcon#read 5, iclass 34, count 0 2006.176.07:56:32.85#ibcon#about to read 6, iclass 34, count 0 2006.176.07:56:32.85#ibcon#read 6, iclass 34, count 0 2006.176.07:56:32.85#ibcon#end of sib2, iclass 34, count 0 2006.176.07:56:32.85#ibcon#*after write, iclass 34, count 0 2006.176.07:56:32.85#ibcon#*before return 0, iclass 34, count 0 2006.176.07:56:32.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:56:32.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.07:56:32.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.07:56:32.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.07:56:32.85$4f8m12a/ifd4f 2006.176.07:56:32.85$ifd4f/lo= 2006.176.07:56:32.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.07:56:32.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.07:56:32.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.07:56:32.86$ifd4f/patch= 2006.176.07:56:32.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.07:56:32.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.07:56:32.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.07:56:32.86$4f8m12a/"form=m,16.000,1:2 2006.176.07:56:32.86$4f8m12a/"tpicd 2006.176.07:56:32.86$4f8m12a/echo=off 2006.176.07:56:32.86$4f8m12a/xlog=off 2006.176.07:56:32.86:!2006.176.07:58:40 2006.176.07:56:57.14#trakl#Source acquired 2006.176.07:56:57.14#flagr#flagr/antenna,acquired 2006.176.07:58:40.01:preob 2006.176.07:58:41.13/onsource/TRACKING 2006.176.07:58:41.13:!2006.176.07:58:50 2006.176.07:58:50.00:data_valid=on 2006.176.07:58:50.00:midob 2006.176.07:58:50.13/onsource/TRACKING 2006.176.07:58:50.13/wx/23.85,1008.6,92 2006.176.07:58:50.21/cable/+6.4952E-03 2006.176.07:58:51.30/va/01,08,usb,yes,29,31 2006.176.07:58:51.30/va/02,07,usb,yes,30,31 2006.176.07:58:51.30/va/03,06,usb,yes,31,31 2006.176.07:58:51.30/va/04,07,usb,yes,30,32 2006.176.07:58:51.30/va/05,07,usb,yes,32,34 2006.176.07:58:51.30/va/06,06,usb,yes,31,31 2006.176.07:58:51.30/va/07,06,usb,yes,32,31 2006.176.07:58:51.30/va/08,06,usb,yes,34,33 2006.176.07:58:51.53/valo/01,532.99,yes,locked 2006.176.07:58:51.53/valo/02,572.99,yes,locked 2006.176.07:58:51.53/valo/03,672.99,yes,locked 2006.176.07:58:51.53/valo/04,832.99,yes,locked 2006.176.07:58:51.53/valo/05,652.99,yes,locked 2006.176.07:58:51.53/valo/06,772.99,yes,locked 2006.176.07:58:51.53/valo/07,832.99,yes,locked 2006.176.07:58:51.53/valo/08,852.99,yes,locked 2006.176.07:58:52.62/vb/01,04,usb,yes,29,28 2006.176.07:58:52.62/vb/02,04,usb,yes,31,33 2006.176.07:58:52.62/vb/03,04,usb,yes,28,31 2006.176.07:58:52.62/vb/04,04,usb,yes,28,29 2006.176.07:58:52.62/vb/05,04,usb,yes,27,31 2006.176.07:58:52.62/vb/06,04,usb,yes,28,31 2006.176.07:58:52.62/vb/07,04,usb,yes,30,30 2006.176.07:58:52.62/vb/08,04,usb,yes,28,31 2006.176.07:58:52.85/vblo/01,632.99,yes,locked 2006.176.07:58:52.85/vblo/02,640.99,yes,locked 2006.176.07:58:52.85/vblo/03,656.99,yes,locked 2006.176.07:58:52.85/vblo/04,712.99,yes,locked 2006.176.07:58:52.85/vblo/05,744.99,yes,locked 2006.176.07:58:52.85/vblo/06,752.99,yes,locked 2006.176.07:58:52.85/vblo/07,734.99,yes,locked 2006.176.07:58:52.85/vblo/08,744.99,yes,locked 2006.176.07:58:53.00/vabw/8 2006.176.07:58:53.15/vbbw/8 2006.176.07:58:53.24/xfe/off,on,14.2 2006.176.07:58:53.62/ifatt/23,28,28,28 2006.176.07:58:54.07/fmout-gps/S +3.74E-07 2006.176.07:58:54.12:!2006.176.07:59:50 2006.176.07:59:50.01:data_valid=off 2006.176.07:59:50.02:postob 2006.176.07:59:50.21/cable/+6.4949E-03 2006.176.07:59:50.22/wx/23.85,1008.6,92 2006.176.07:59:51.07/fmout-gps/S +3.73E-07 2006.176.07:59:51.08:scan_name=176-0801,k06176,60 2006.176.07:59:51.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.176.07:59:52.14#flagr#flagr/antenna,new-source 2006.176.07:59:52.15:checkk5 2006.176.07:59:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.176.07:59:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.176.07:59:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.176.07:59:53.68/chk_autoobs//k5ts4/ autoobs is running! 2006.176.07:59:54.05/chk_obsdata//k5ts1/T1760758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:59:54.42/chk_obsdata//k5ts2/T1760758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:59:54.79/chk_obsdata//k5ts3/T1760758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:59:55.16/chk_obsdata//k5ts4/T1760758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.07:59:55.86/k5log//k5ts1_log_newline 2006.176.07:59:56.55/k5log//k5ts2_log_newline 2006.176.07:59:57.24/k5log//k5ts3_log_newline 2006.176.07:59:57.93/k5log//k5ts4_log_newline 2006.176.07:59:57.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.07:59:57.95:4f8m12a=2 2006.176.07:59:57.95$4f8m12a/echo=on 2006.176.07:59:57.95$4f8m12a/pcalon 2006.176.07:59:57.95$pcalon/"no phase cal control is implemented here 2006.176.07:59:57.95$4f8m12a/"tpicd=stop 2006.176.07:59:57.95$4f8m12a/vc4f8 2006.176.07:59:57.95$vc4f8/valo=1,532.99 2006.176.07:59:57.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.07:59:57.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.07:59:57.96#ibcon#ireg 17 cls_cnt 0 2006.176.07:59:57.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:59:57.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:59:57.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:59:57.96#ibcon#enter wrdev, iclass 40, count 0 2006.176.07:59:57.96#ibcon#first serial, iclass 40, count 0 2006.176.07:59:57.96#ibcon#enter sib2, iclass 40, count 0 2006.176.07:59:57.96#ibcon#flushed, iclass 40, count 0 2006.176.07:59:57.96#ibcon#about to write, iclass 40, count 0 2006.176.07:59:57.96#ibcon#wrote, iclass 40, count 0 2006.176.07:59:57.96#ibcon#about to read 3, iclass 40, count 0 2006.176.07:59:58.00#ibcon#read 3, iclass 40, count 0 2006.176.07:59:58.00#ibcon#about to read 4, iclass 40, count 0 2006.176.07:59:58.00#ibcon#read 4, iclass 40, count 0 2006.176.07:59:58.00#ibcon#about to read 5, iclass 40, count 0 2006.176.07:59:58.00#ibcon#read 5, iclass 40, count 0 2006.176.07:59:58.00#ibcon#about to read 6, iclass 40, count 0 2006.176.07:59:58.00#ibcon#read 6, iclass 40, count 0 2006.176.07:59:58.00#ibcon#end of sib2, iclass 40, count 0 2006.176.07:59:58.00#ibcon#*mode == 0, iclass 40, count 0 2006.176.07:59:58.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.07:59:58.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.07:59:58.00#ibcon#*before write, iclass 40, count 0 2006.176.07:59:58.00#ibcon#enter sib2, iclass 40, count 0 2006.176.07:59:58.00#ibcon#flushed, iclass 40, count 0 2006.176.07:59:58.00#ibcon#about to write, iclass 40, count 0 2006.176.07:59:58.00#ibcon#wrote, iclass 40, count 0 2006.176.07:59:58.00#ibcon#about to read 3, iclass 40, count 0 2006.176.07:59:58.04#ibcon#read 3, iclass 40, count 0 2006.176.07:59:58.04#ibcon#about to read 4, iclass 40, count 0 2006.176.07:59:58.04#ibcon#read 4, iclass 40, count 0 2006.176.07:59:58.04#ibcon#about to read 5, iclass 40, count 0 2006.176.07:59:58.04#ibcon#read 5, iclass 40, count 0 2006.176.07:59:58.04#ibcon#about to read 6, iclass 40, count 0 2006.176.07:59:58.04#ibcon#read 6, iclass 40, count 0 2006.176.07:59:58.04#ibcon#end of sib2, iclass 40, count 0 2006.176.07:59:58.04#ibcon#*after write, iclass 40, count 0 2006.176.07:59:58.04#ibcon#*before return 0, iclass 40, count 0 2006.176.07:59:58.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:59:58.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.07:59:58.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.07:59:58.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.07:59:58.04$vc4f8/va=1,8 2006.176.07:59:58.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.07:59:58.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.07:59:58.04#ibcon#ireg 11 cls_cnt 2 2006.176.07:59:58.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:59:58.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:59:58.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:59:58.04#ibcon#enter wrdev, iclass 4, count 2 2006.176.07:59:58.04#ibcon#first serial, iclass 4, count 2 2006.176.07:59:58.04#ibcon#enter sib2, iclass 4, count 2 2006.176.07:59:58.04#ibcon#flushed, iclass 4, count 2 2006.176.07:59:58.04#ibcon#about to write, iclass 4, count 2 2006.176.07:59:58.04#ibcon#wrote, iclass 4, count 2 2006.176.07:59:58.04#ibcon#about to read 3, iclass 4, count 2 2006.176.07:59:58.06#ibcon#read 3, iclass 4, count 2 2006.176.07:59:58.06#ibcon#about to read 4, iclass 4, count 2 2006.176.07:59:58.06#ibcon#read 4, iclass 4, count 2 2006.176.07:59:58.06#ibcon#about to read 5, iclass 4, count 2 2006.176.07:59:58.06#ibcon#read 5, iclass 4, count 2 2006.176.07:59:58.06#ibcon#about to read 6, iclass 4, count 2 2006.176.07:59:58.06#ibcon#read 6, iclass 4, count 2 2006.176.07:59:58.06#ibcon#end of sib2, iclass 4, count 2 2006.176.07:59:58.06#ibcon#*mode == 0, iclass 4, count 2 2006.176.07:59:58.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.07:59:58.06#ibcon#[25=AT01-08\r\n] 2006.176.07:59:58.06#ibcon#*before write, iclass 4, count 2 2006.176.07:59:58.06#ibcon#enter sib2, iclass 4, count 2 2006.176.07:59:58.06#ibcon#flushed, iclass 4, count 2 2006.176.07:59:58.06#ibcon#about to write, iclass 4, count 2 2006.176.07:59:58.06#ibcon#wrote, iclass 4, count 2 2006.176.07:59:58.06#ibcon#about to read 3, iclass 4, count 2 2006.176.07:59:58.09#ibcon#read 3, iclass 4, count 2 2006.176.07:59:58.09#ibcon#about to read 4, iclass 4, count 2 2006.176.07:59:58.09#ibcon#read 4, iclass 4, count 2 2006.176.07:59:58.09#ibcon#about to read 5, iclass 4, count 2 2006.176.07:59:58.09#ibcon#read 5, iclass 4, count 2 2006.176.07:59:58.09#ibcon#about to read 6, iclass 4, count 2 2006.176.07:59:58.09#ibcon#read 6, iclass 4, count 2 2006.176.07:59:58.09#ibcon#end of sib2, iclass 4, count 2 2006.176.07:59:58.09#ibcon#*after write, iclass 4, count 2 2006.176.07:59:58.09#ibcon#*before return 0, iclass 4, count 2 2006.176.07:59:58.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:59:58.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.07:59:58.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.07:59:58.09#ibcon#ireg 7 cls_cnt 0 2006.176.07:59:58.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:59:58.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:59:58.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:59:58.21#ibcon#enter wrdev, iclass 4, count 0 2006.176.07:59:58.21#ibcon#first serial, iclass 4, count 0 2006.176.07:59:58.21#ibcon#enter sib2, iclass 4, count 0 2006.176.07:59:58.21#ibcon#flushed, iclass 4, count 0 2006.176.07:59:58.21#ibcon#about to write, iclass 4, count 0 2006.176.07:59:58.21#ibcon#wrote, iclass 4, count 0 2006.176.07:59:58.21#ibcon#about to read 3, iclass 4, count 0 2006.176.07:59:58.23#ibcon#read 3, iclass 4, count 0 2006.176.07:59:58.23#ibcon#about to read 4, iclass 4, count 0 2006.176.07:59:58.23#ibcon#read 4, iclass 4, count 0 2006.176.07:59:58.23#ibcon#about to read 5, iclass 4, count 0 2006.176.07:59:58.23#ibcon#read 5, iclass 4, count 0 2006.176.07:59:58.23#ibcon#about to read 6, iclass 4, count 0 2006.176.07:59:58.23#ibcon#read 6, iclass 4, count 0 2006.176.07:59:58.23#ibcon#end of sib2, iclass 4, count 0 2006.176.07:59:58.23#ibcon#*mode == 0, iclass 4, count 0 2006.176.07:59:58.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.07:59:58.23#ibcon#[25=USB\r\n] 2006.176.07:59:58.23#ibcon#*before write, iclass 4, count 0 2006.176.07:59:58.23#ibcon#enter sib2, iclass 4, count 0 2006.176.07:59:58.23#ibcon#flushed, iclass 4, count 0 2006.176.07:59:58.23#ibcon#about to write, iclass 4, count 0 2006.176.07:59:58.23#ibcon#wrote, iclass 4, count 0 2006.176.07:59:58.23#ibcon#about to read 3, iclass 4, count 0 2006.176.07:59:58.26#ibcon#read 3, iclass 4, count 0 2006.176.07:59:58.26#ibcon#about to read 4, iclass 4, count 0 2006.176.07:59:58.26#ibcon#read 4, iclass 4, count 0 2006.176.07:59:58.26#ibcon#about to read 5, iclass 4, count 0 2006.176.07:59:58.26#ibcon#read 5, iclass 4, count 0 2006.176.07:59:58.26#ibcon#about to read 6, iclass 4, count 0 2006.176.07:59:58.26#ibcon#read 6, iclass 4, count 0 2006.176.07:59:58.26#ibcon#end of sib2, iclass 4, count 0 2006.176.07:59:58.26#ibcon#*after write, iclass 4, count 0 2006.176.07:59:58.26#ibcon#*before return 0, iclass 4, count 0 2006.176.07:59:58.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:59:58.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.07:59:58.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.07:59:58.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.07:59:58.26$vc4f8/valo=2,572.99 2006.176.07:59:58.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.07:59:58.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.07:59:58.26#ibcon#ireg 17 cls_cnt 0 2006.176.07:59:58.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:59:58.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:59:58.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:59:58.26#ibcon#enter wrdev, iclass 6, count 0 2006.176.07:59:58.26#ibcon#first serial, iclass 6, count 0 2006.176.07:59:58.26#ibcon#enter sib2, iclass 6, count 0 2006.176.07:59:58.26#ibcon#flushed, iclass 6, count 0 2006.176.07:59:58.26#ibcon#about to write, iclass 6, count 0 2006.176.07:59:58.26#ibcon#wrote, iclass 6, count 0 2006.176.07:59:58.26#ibcon#about to read 3, iclass 6, count 0 2006.176.07:59:58.28#ibcon#read 3, iclass 6, count 0 2006.176.07:59:58.28#ibcon#about to read 4, iclass 6, count 0 2006.176.07:59:58.28#ibcon#read 4, iclass 6, count 0 2006.176.07:59:58.28#ibcon#about to read 5, iclass 6, count 0 2006.176.07:59:58.28#ibcon#read 5, iclass 6, count 0 2006.176.07:59:58.28#ibcon#about to read 6, iclass 6, count 0 2006.176.07:59:58.28#ibcon#read 6, iclass 6, count 0 2006.176.07:59:58.28#ibcon#end of sib2, iclass 6, count 0 2006.176.07:59:58.28#ibcon#*mode == 0, iclass 6, count 0 2006.176.07:59:58.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.07:59:58.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.07:59:58.28#ibcon#*before write, iclass 6, count 0 2006.176.07:59:58.28#ibcon#enter sib2, iclass 6, count 0 2006.176.07:59:58.28#ibcon#flushed, iclass 6, count 0 2006.176.07:59:58.28#ibcon#about to write, iclass 6, count 0 2006.176.07:59:58.28#ibcon#wrote, iclass 6, count 0 2006.176.07:59:58.28#ibcon#about to read 3, iclass 6, count 0 2006.176.07:59:58.32#ibcon#read 3, iclass 6, count 0 2006.176.07:59:58.32#ibcon#about to read 4, iclass 6, count 0 2006.176.07:59:58.32#ibcon#read 4, iclass 6, count 0 2006.176.07:59:58.32#ibcon#about to read 5, iclass 6, count 0 2006.176.07:59:58.32#ibcon#read 5, iclass 6, count 0 2006.176.07:59:58.32#ibcon#about to read 6, iclass 6, count 0 2006.176.07:59:58.32#ibcon#read 6, iclass 6, count 0 2006.176.07:59:58.32#ibcon#end of sib2, iclass 6, count 0 2006.176.07:59:58.32#ibcon#*after write, iclass 6, count 0 2006.176.07:59:58.32#ibcon#*before return 0, iclass 6, count 0 2006.176.07:59:58.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:59:58.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.07:59:58.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.07:59:58.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.07:59:58.32$vc4f8/va=2,7 2006.176.07:59:58.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.07:59:58.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.07:59:58.32#ibcon#ireg 11 cls_cnt 2 2006.176.07:59:58.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:59:58.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:59:58.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:59:58.38#ibcon#enter wrdev, iclass 10, count 2 2006.176.07:59:58.38#ibcon#first serial, iclass 10, count 2 2006.176.07:59:58.38#ibcon#enter sib2, iclass 10, count 2 2006.176.07:59:58.38#ibcon#flushed, iclass 10, count 2 2006.176.07:59:58.38#ibcon#about to write, iclass 10, count 2 2006.176.07:59:58.38#ibcon#wrote, iclass 10, count 2 2006.176.07:59:58.38#ibcon#about to read 3, iclass 10, count 2 2006.176.07:59:58.41#ibcon#read 3, iclass 10, count 2 2006.176.07:59:58.41#ibcon#about to read 4, iclass 10, count 2 2006.176.07:59:58.41#ibcon#read 4, iclass 10, count 2 2006.176.07:59:58.41#ibcon#about to read 5, iclass 10, count 2 2006.176.07:59:58.41#ibcon#read 5, iclass 10, count 2 2006.176.07:59:58.41#ibcon#about to read 6, iclass 10, count 2 2006.176.07:59:58.41#ibcon#read 6, iclass 10, count 2 2006.176.07:59:58.41#ibcon#end of sib2, iclass 10, count 2 2006.176.07:59:58.41#ibcon#*mode == 0, iclass 10, count 2 2006.176.07:59:58.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.07:59:58.41#ibcon#[25=AT02-07\r\n] 2006.176.07:59:58.41#ibcon#*before write, iclass 10, count 2 2006.176.07:59:58.41#ibcon#enter sib2, iclass 10, count 2 2006.176.07:59:58.41#ibcon#flushed, iclass 10, count 2 2006.176.07:59:58.41#ibcon#about to write, iclass 10, count 2 2006.176.07:59:58.41#ibcon#wrote, iclass 10, count 2 2006.176.07:59:58.41#ibcon#about to read 3, iclass 10, count 2 2006.176.07:59:58.43#ibcon#read 3, iclass 10, count 2 2006.176.07:59:58.43#ibcon#about to read 4, iclass 10, count 2 2006.176.07:59:58.43#ibcon#read 4, iclass 10, count 2 2006.176.07:59:58.43#ibcon#about to read 5, iclass 10, count 2 2006.176.07:59:58.43#ibcon#read 5, iclass 10, count 2 2006.176.07:59:58.43#ibcon#about to read 6, iclass 10, count 2 2006.176.07:59:58.43#ibcon#read 6, iclass 10, count 2 2006.176.07:59:58.43#ibcon#end of sib2, iclass 10, count 2 2006.176.07:59:58.43#ibcon#*after write, iclass 10, count 2 2006.176.07:59:58.43#ibcon#*before return 0, iclass 10, count 2 2006.176.07:59:58.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:59:58.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.07:59:58.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.07:59:58.43#ibcon#ireg 7 cls_cnt 0 2006.176.07:59:58.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:59:58.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:59:58.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:59:58.55#ibcon#enter wrdev, iclass 10, count 0 2006.176.07:59:58.55#ibcon#first serial, iclass 10, count 0 2006.176.07:59:58.55#ibcon#enter sib2, iclass 10, count 0 2006.176.07:59:58.55#ibcon#flushed, iclass 10, count 0 2006.176.07:59:58.55#ibcon#about to write, iclass 10, count 0 2006.176.07:59:58.55#ibcon#wrote, iclass 10, count 0 2006.176.07:59:58.55#ibcon#about to read 3, iclass 10, count 0 2006.176.07:59:58.57#ibcon#read 3, iclass 10, count 0 2006.176.07:59:58.57#ibcon#about to read 4, iclass 10, count 0 2006.176.07:59:58.57#ibcon#read 4, iclass 10, count 0 2006.176.07:59:58.57#ibcon#about to read 5, iclass 10, count 0 2006.176.07:59:58.57#ibcon#read 5, iclass 10, count 0 2006.176.07:59:58.57#ibcon#about to read 6, iclass 10, count 0 2006.176.07:59:58.57#ibcon#read 6, iclass 10, count 0 2006.176.07:59:58.57#ibcon#end of sib2, iclass 10, count 0 2006.176.07:59:58.57#ibcon#*mode == 0, iclass 10, count 0 2006.176.07:59:58.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.07:59:58.57#ibcon#[25=USB\r\n] 2006.176.07:59:58.57#ibcon#*before write, iclass 10, count 0 2006.176.07:59:58.57#ibcon#enter sib2, iclass 10, count 0 2006.176.07:59:58.57#ibcon#flushed, iclass 10, count 0 2006.176.07:59:58.57#ibcon#about to write, iclass 10, count 0 2006.176.07:59:58.57#ibcon#wrote, iclass 10, count 0 2006.176.07:59:58.57#ibcon#about to read 3, iclass 10, count 0 2006.176.07:59:58.60#ibcon#read 3, iclass 10, count 0 2006.176.07:59:58.60#ibcon#about to read 4, iclass 10, count 0 2006.176.07:59:58.60#ibcon#read 4, iclass 10, count 0 2006.176.07:59:58.60#ibcon#about to read 5, iclass 10, count 0 2006.176.07:59:58.60#ibcon#read 5, iclass 10, count 0 2006.176.07:59:58.60#ibcon#about to read 6, iclass 10, count 0 2006.176.07:59:58.60#ibcon#read 6, iclass 10, count 0 2006.176.07:59:58.60#ibcon#end of sib2, iclass 10, count 0 2006.176.07:59:58.60#ibcon#*after write, iclass 10, count 0 2006.176.07:59:58.60#ibcon#*before return 0, iclass 10, count 0 2006.176.07:59:58.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:59:58.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.07:59:58.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.07:59:58.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.07:59:58.60$vc4f8/valo=3,672.99 2006.176.07:59:58.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.07:59:58.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.07:59:58.60#ibcon#ireg 17 cls_cnt 0 2006.176.07:59:58.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:59:58.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:59:58.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:59:58.60#ibcon#enter wrdev, iclass 12, count 0 2006.176.07:59:58.60#ibcon#first serial, iclass 12, count 0 2006.176.07:59:58.60#ibcon#enter sib2, iclass 12, count 0 2006.176.07:59:58.60#ibcon#flushed, iclass 12, count 0 2006.176.07:59:58.60#ibcon#about to write, iclass 12, count 0 2006.176.07:59:58.60#ibcon#wrote, iclass 12, count 0 2006.176.07:59:58.60#ibcon#about to read 3, iclass 12, count 0 2006.176.07:59:58.62#ibcon#read 3, iclass 12, count 0 2006.176.07:59:58.62#ibcon#about to read 4, iclass 12, count 0 2006.176.07:59:58.62#ibcon#read 4, iclass 12, count 0 2006.176.07:59:58.62#ibcon#about to read 5, iclass 12, count 0 2006.176.07:59:58.62#ibcon#read 5, iclass 12, count 0 2006.176.07:59:58.62#ibcon#about to read 6, iclass 12, count 0 2006.176.07:59:58.62#ibcon#read 6, iclass 12, count 0 2006.176.07:59:58.62#ibcon#end of sib2, iclass 12, count 0 2006.176.07:59:58.62#ibcon#*mode == 0, iclass 12, count 0 2006.176.07:59:58.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.07:59:58.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.07:59:58.62#ibcon#*before write, iclass 12, count 0 2006.176.07:59:58.62#ibcon#enter sib2, iclass 12, count 0 2006.176.07:59:58.62#ibcon#flushed, iclass 12, count 0 2006.176.07:59:58.62#ibcon#about to write, iclass 12, count 0 2006.176.07:59:58.62#ibcon#wrote, iclass 12, count 0 2006.176.07:59:58.62#ibcon#about to read 3, iclass 12, count 0 2006.176.07:59:58.66#ibcon#read 3, iclass 12, count 0 2006.176.07:59:58.66#ibcon#about to read 4, iclass 12, count 0 2006.176.07:59:58.66#ibcon#read 4, iclass 12, count 0 2006.176.07:59:58.66#ibcon#about to read 5, iclass 12, count 0 2006.176.07:59:58.66#ibcon#read 5, iclass 12, count 0 2006.176.07:59:58.66#ibcon#about to read 6, iclass 12, count 0 2006.176.07:59:58.66#ibcon#read 6, iclass 12, count 0 2006.176.07:59:58.66#ibcon#end of sib2, iclass 12, count 0 2006.176.07:59:58.66#ibcon#*after write, iclass 12, count 0 2006.176.07:59:58.66#ibcon#*before return 0, iclass 12, count 0 2006.176.07:59:58.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:59:58.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.07:59:58.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.07:59:58.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.07:59:58.66$vc4f8/va=3,6 2006.176.07:59:58.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.07:59:58.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.07:59:58.66#ibcon#ireg 11 cls_cnt 2 2006.176.07:59:58.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:59:58.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:59:58.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:59:58.72#ibcon#enter wrdev, iclass 14, count 2 2006.176.07:59:58.72#ibcon#first serial, iclass 14, count 2 2006.176.07:59:58.72#ibcon#enter sib2, iclass 14, count 2 2006.176.07:59:58.72#ibcon#flushed, iclass 14, count 2 2006.176.07:59:58.72#ibcon#about to write, iclass 14, count 2 2006.176.07:59:58.72#ibcon#wrote, iclass 14, count 2 2006.176.07:59:58.72#ibcon#about to read 3, iclass 14, count 2 2006.176.07:59:58.75#ibcon#read 3, iclass 14, count 2 2006.176.07:59:58.75#ibcon#about to read 4, iclass 14, count 2 2006.176.07:59:58.75#ibcon#read 4, iclass 14, count 2 2006.176.07:59:58.75#ibcon#about to read 5, iclass 14, count 2 2006.176.07:59:58.75#ibcon#read 5, iclass 14, count 2 2006.176.07:59:58.75#ibcon#about to read 6, iclass 14, count 2 2006.176.07:59:58.75#ibcon#read 6, iclass 14, count 2 2006.176.07:59:58.75#ibcon#end of sib2, iclass 14, count 2 2006.176.07:59:58.75#ibcon#*mode == 0, iclass 14, count 2 2006.176.07:59:58.75#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.07:59:58.75#ibcon#[25=AT03-06\r\n] 2006.176.07:59:58.75#ibcon#*before write, iclass 14, count 2 2006.176.07:59:58.75#ibcon#enter sib2, iclass 14, count 2 2006.176.07:59:58.75#ibcon#flushed, iclass 14, count 2 2006.176.07:59:58.75#ibcon#about to write, iclass 14, count 2 2006.176.07:59:58.75#ibcon#wrote, iclass 14, count 2 2006.176.07:59:58.75#ibcon#about to read 3, iclass 14, count 2 2006.176.07:59:58.77#ibcon#read 3, iclass 14, count 2 2006.176.07:59:58.77#ibcon#about to read 4, iclass 14, count 2 2006.176.07:59:58.77#ibcon#read 4, iclass 14, count 2 2006.176.07:59:58.77#ibcon#about to read 5, iclass 14, count 2 2006.176.07:59:58.77#ibcon#read 5, iclass 14, count 2 2006.176.07:59:58.77#ibcon#about to read 6, iclass 14, count 2 2006.176.07:59:58.77#ibcon#read 6, iclass 14, count 2 2006.176.07:59:58.77#ibcon#end of sib2, iclass 14, count 2 2006.176.07:59:58.77#ibcon#*after write, iclass 14, count 2 2006.176.07:59:58.77#ibcon#*before return 0, iclass 14, count 2 2006.176.07:59:58.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:59:58.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.07:59:58.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.07:59:58.77#ibcon#ireg 7 cls_cnt 0 2006.176.07:59:58.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:59:58.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:59:58.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:59:58.89#ibcon#enter wrdev, iclass 14, count 0 2006.176.07:59:58.89#ibcon#first serial, iclass 14, count 0 2006.176.07:59:58.89#ibcon#enter sib2, iclass 14, count 0 2006.176.07:59:58.89#ibcon#flushed, iclass 14, count 0 2006.176.07:59:58.89#ibcon#about to write, iclass 14, count 0 2006.176.07:59:58.89#ibcon#wrote, iclass 14, count 0 2006.176.07:59:58.89#ibcon#about to read 3, iclass 14, count 0 2006.176.07:59:58.91#ibcon#read 3, iclass 14, count 0 2006.176.07:59:58.91#ibcon#about to read 4, iclass 14, count 0 2006.176.07:59:58.91#ibcon#read 4, iclass 14, count 0 2006.176.07:59:58.91#ibcon#about to read 5, iclass 14, count 0 2006.176.07:59:58.91#ibcon#read 5, iclass 14, count 0 2006.176.07:59:58.91#ibcon#about to read 6, iclass 14, count 0 2006.176.07:59:58.91#ibcon#read 6, iclass 14, count 0 2006.176.07:59:58.91#ibcon#end of sib2, iclass 14, count 0 2006.176.07:59:58.91#ibcon#*mode == 0, iclass 14, count 0 2006.176.07:59:58.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.07:59:58.91#ibcon#[25=USB\r\n] 2006.176.07:59:58.91#ibcon#*before write, iclass 14, count 0 2006.176.07:59:58.91#ibcon#enter sib2, iclass 14, count 0 2006.176.07:59:58.91#ibcon#flushed, iclass 14, count 0 2006.176.07:59:58.91#ibcon#about to write, iclass 14, count 0 2006.176.07:59:58.91#ibcon#wrote, iclass 14, count 0 2006.176.07:59:58.91#ibcon#about to read 3, iclass 14, count 0 2006.176.07:59:58.94#ibcon#read 3, iclass 14, count 0 2006.176.07:59:58.94#ibcon#about to read 4, iclass 14, count 0 2006.176.07:59:58.94#ibcon#read 4, iclass 14, count 0 2006.176.07:59:58.94#ibcon#about to read 5, iclass 14, count 0 2006.176.07:59:58.94#ibcon#read 5, iclass 14, count 0 2006.176.07:59:58.94#ibcon#about to read 6, iclass 14, count 0 2006.176.07:59:58.94#ibcon#read 6, iclass 14, count 0 2006.176.07:59:58.94#ibcon#end of sib2, iclass 14, count 0 2006.176.07:59:58.94#ibcon#*after write, iclass 14, count 0 2006.176.07:59:58.94#ibcon#*before return 0, iclass 14, count 0 2006.176.07:59:58.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:59:58.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.07:59:58.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.07:59:58.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.07:59:58.94$vc4f8/valo=4,832.99 2006.176.07:59:58.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.07:59:58.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.07:59:58.94#ibcon#ireg 17 cls_cnt 0 2006.176.07:59:58.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:59:58.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:59:58.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:59:58.94#ibcon#enter wrdev, iclass 16, count 0 2006.176.07:59:58.94#ibcon#first serial, iclass 16, count 0 2006.176.07:59:58.94#ibcon#enter sib2, iclass 16, count 0 2006.176.07:59:58.94#ibcon#flushed, iclass 16, count 0 2006.176.07:59:58.94#ibcon#about to write, iclass 16, count 0 2006.176.07:59:58.94#ibcon#wrote, iclass 16, count 0 2006.176.07:59:58.94#ibcon#about to read 3, iclass 16, count 0 2006.176.07:59:58.96#ibcon#read 3, iclass 16, count 0 2006.176.07:59:58.96#ibcon#about to read 4, iclass 16, count 0 2006.176.07:59:58.96#ibcon#read 4, iclass 16, count 0 2006.176.07:59:58.96#ibcon#about to read 5, iclass 16, count 0 2006.176.07:59:58.96#ibcon#read 5, iclass 16, count 0 2006.176.07:59:58.96#ibcon#about to read 6, iclass 16, count 0 2006.176.07:59:58.96#ibcon#read 6, iclass 16, count 0 2006.176.07:59:58.96#ibcon#end of sib2, iclass 16, count 0 2006.176.07:59:58.96#ibcon#*mode == 0, iclass 16, count 0 2006.176.07:59:58.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.07:59:58.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.07:59:58.96#ibcon#*before write, iclass 16, count 0 2006.176.07:59:58.96#ibcon#enter sib2, iclass 16, count 0 2006.176.07:59:58.96#ibcon#flushed, iclass 16, count 0 2006.176.07:59:58.96#ibcon#about to write, iclass 16, count 0 2006.176.07:59:58.96#ibcon#wrote, iclass 16, count 0 2006.176.07:59:58.96#ibcon#about to read 3, iclass 16, count 0 2006.176.07:59:59.00#ibcon#read 3, iclass 16, count 0 2006.176.07:59:59.00#ibcon#about to read 4, iclass 16, count 0 2006.176.07:59:59.00#ibcon#read 4, iclass 16, count 0 2006.176.07:59:59.00#ibcon#about to read 5, iclass 16, count 0 2006.176.07:59:59.00#ibcon#read 5, iclass 16, count 0 2006.176.07:59:59.00#ibcon#about to read 6, iclass 16, count 0 2006.176.07:59:59.00#ibcon#read 6, iclass 16, count 0 2006.176.07:59:59.00#ibcon#end of sib2, iclass 16, count 0 2006.176.07:59:59.00#ibcon#*after write, iclass 16, count 0 2006.176.07:59:59.00#ibcon#*before return 0, iclass 16, count 0 2006.176.07:59:59.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:59:59.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.07:59:59.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.07:59:59.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.07:59:59.00$vc4f8/va=4,7 2006.176.07:59:59.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.07:59:59.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.07:59:59.00#ibcon#ireg 11 cls_cnt 2 2006.176.07:59:59.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:59:59.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:59:59.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:59:59.06#ibcon#enter wrdev, iclass 18, count 2 2006.176.07:59:59.06#ibcon#first serial, iclass 18, count 2 2006.176.07:59:59.06#ibcon#enter sib2, iclass 18, count 2 2006.176.07:59:59.06#ibcon#flushed, iclass 18, count 2 2006.176.07:59:59.06#ibcon#about to write, iclass 18, count 2 2006.176.07:59:59.06#ibcon#wrote, iclass 18, count 2 2006.176.07:59:59.06#ibcon#about to read 3, iclass 18, count 2 2006.176.07:59:59.08#ibcon#read 3, iclass 18, count 2 2006.176.07:59:59.08#ibcon#about to read 4, iclass 18, count 2 2006.176.07:59:59.08#ibcon#read 4, iclass 18, count 2 2006.176.07:59:59.08#ibcon#about to read 5, iclass 18, count 2 2006.176.07:59:59.08#ibcon#read 5, iclass 18, count 2 2006.176.07:59:59.08#ibcon#about to read 6, iclass 18, count 2 2006.176.07:59:59.08#ibcon#read 6, iclass 18, count 2 2006.176.07:59:59.08#ibcon#end of sib2, iclass 18, count 2 2006.176.07:59:59.08#ibcon#*mode == 0, iclass 18, count 2 2006.176.07:59:59.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.07:59:59.08#ibcon#[25=AT04-07\r\n] 2006.176.07:59:59.08#ibcon#*before write, iclass 18, count 2 2006.176.07:59:59.08#ibcon#enter sib2, iclass 18, count 2 2006.176.07:59:59.08#ibcon#flushed, iclass 18, count 2 2006.176.07:59:59.08#ibcon#about to write, iclass 18, count 2 2006.176.07:59:59.08#ibcon#wrote, iclass 18, count 2 2006.176.07:59:59.08#ibcon#about to read 3, iclass 18, count 2 2006.176.07:59:59.11#ibcon#read 3, iclass 18, count 2 2006.176.07:59:59.11#ibcon#about to read 4, iclass 18, count 2 2006.176.07:59:59.11#ibcon#read 4, iclass 18, count 2 2006.176.07:59:59.11#ibcon#about to read 5, iclass 18, count 2 2006.176.07:59:59.11#ibcon#read 5, iclass 18, count 2 2006.176.07:59:59.11#ibcon#about to read 6, iclass 18, count 2 2006.176.07:59:59.11#ibcon#read 6, iclass 18, count 2 2006.176.07:59:59.11#ibcon#end of sib2, iclass 18, count 2 2006.176.07:59:59.11#ibcon#*after write, iclass 18, count 2 2006.176.07:59:59.11#ibcon#*before return 0, iclass 18, count 2 2006.176.07:59:59.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:59:59.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.07:59:59.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.07:59:59.11#ibcon#ireg 7 cls_cnt 0 2006.176.07:59:59.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:59:59.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:59:59.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:59:59.23#ibcon#enter wrdev, iclass 18, count 0 2006.176.07:59:59.23#ibcon#first serial, iclass 18, count 0 2006.176.07:59:59.23#ibcon#enter sib2, iclass 18, count 0 2006.176.07:59:59.23#ibcon#flushed, iclass 18, count 0 2006.176.07:59:59.23#ibcon#about to write, iclass 18, count 0 2006.176.07:59:59.23#ibcon#wrote, iclass 18, count 0 2006.176.07:59:59.23#ibcon#about to read 3, iclass 18, count 0 2006.176.07:59:59.25#ibcon#read 3, iclass 18, count 0 2006.176.07:59:59.25#ibcon#about to read 4, iclass 18, count 0 2006.176.07:59:59.25#ibcon#read 4, iclass 18, count 0 2006.176.07:59:59.25#ibcon#about to read 5, iclass 18, count 0 2006.176.07:59:59.25#ibcon#read 5, iclass 18, count 0 2006.176.07:59:59.25#ibcon#about to read 6, iclass 18, count 0 2006.176.07:59:59.25#ibcon#read 6, iclass 18, count 0 2006.176.07:59:59.25#ibcon#end of sib2, iclass 18, count 0 2006.176.07:59:59.25#ibcon#*mode == 0, iclass 18, count 0 2006.176.07:59:59.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.07:59:59.25#ibcon#[25=USB\r\n] 2006.176.07:59:59.25#ibcon#*before write, iclass 18, count 0 2006.176.07:59:59.25#ibcon#enter sib2, iclass 18, count 0 2006.176.07:59:59.25#ibcon#flushed, iclass 18, count 0 2006.176.07:59:59.25#ibcon#about to write, iclass 18, count 0 2006.176.07:59:59.25#ibcon#wrote, iclass 18, count 0 2006.176.07:59:59.25#ibcon#about to read 3, iclass 18, count 0 2006.176.07:59:59.28#ibcon#read 3, iclass 18, count 0 2006.176.07:59:59.28#ibcon#about to read 4, iclass 18, count 0 2006.176.07:59:59.28#ibcon#read 4, iclass 18, count 0 2006.176.07:59:59.28#ibcon#about to read 5, iclass 18, count 0 2006.176.07:59:59.28#ibcon#read 5, iclass 18, count 0 2006.176.07:59:59.28#ibcon#about to read 6, iclass 18, count 0 2006.176.07:59:59.28#ibcon#read 6, iclass 18, count 0 2006.176.07:59:59.28#ibcon#end of sib2, iclass 18, count 0 2006.176.07:59:59.28#ibcon#*after write, iclass 18, count 0 2006.176.07:59:59.28#ibcon#*before return 0, iclass 18, count 0 2006.176.07:59:59.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:59:59.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.07:59:59.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.07:59:59.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.07:59:59.28$vc4f8/valo=5,652.99 2006.176.07:59:59.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.07:59:59.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.07:59:59.28#ibcon#ireg 17 cls_cnt 0 2006.176.07:59:59.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:59:59.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:59:59.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:59:59.28#ibcon#enter wrdev, iclass 20, count 0 2006.176.07:59:59.28#ibcon#first serial, iclass 20, count 0 2006.176.07:59:59.28#ibcon#enter sib2, iclass 20, count 0 2006.176.07:59:59.28#ibcon#flushed, iclass 20, count 0 2006.176.07:59:59.28#ibcon#about to write, iclass 20, count 0 2006.176.07:59:59.28#ibcon#wrote, iclass 20, count 0 2006.176.07:59:59.28#ibcon#about to read 3, iclass 20, count 0 2006.176.07:59:59.30#ibcon#read 3, iclass 20, count 0 2006.176.07:59:59.30#ibcon#about to read 4, iclass 20, count 0 2006.176.07:59:59.30#ibcon#read 4, iclass 20, count 0 2006.176.07:59:59.30#ibcon#about to read 5, iclass 20, count 0 2006.176.07:59:59.30#ibcon#read 5, iclass 20, count 0 2006.176.07:59:59.30#ibcon#about to read 6, iclass 20, count 0 2006.176.07:59:59.30#ibcon#read 6, iclass 20, count 0 2006.176.07:59:59.30#ibcon#end of sib2, iclass 20, count 0 2006.176.07:59:59.30#ibcon#*mode == 0, iclass 20, count 0 2006.176.07:59:59.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.07:59:59.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.07:59:59.30#ibcon#*before write, iclass 20, count 0 2006.176.07:59:59.30#ibcon#enter sib2, iclass 20, count 0 2006.176.07:59:59.30#ibcon#flushed, iclass 20, count 0 2006.176.07:59:59.30#ibcon#about to write, iclass 20, count 0 2006.176.07:59:59.30#ibcon#wrote, iclass 20, count 0 2006.176.07:59:59.30#ibcon#about to read 3, iclass 20, count 0 2006.176.07:59:59.34#ibcon#read 3, iclass 20, count 0 2006.176.07:59:59.34#ibcon#about to read 4, iclass 20, count 0 2006.176.07:59:59.34#ibcon#read 4, iclass 20, count 0 2006.176.07:59:59.34#ibcon#about to read 5, iclass 20, count 0 2006.176.07:59:59.34#ibcon#read 5, iclass 20, count 0 2006.176.07:59:59.34#ibcon#about to read 6, iclass 20, count 0 2006.176.07:59:59.34#ibcon#read 6, iclass 20, count 0 2006.176.07:59:59.34#ibcon#end of sib2, iclass 20, count 0 2006.176.07:59:59.34#ibcon#*after write, iclass 20, count 0 2006.176.07:59:59.34#ibcon#*before return 0, iclass 20, count 0 2006.176.07:59:59.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:59:59.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.07:59:59.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.07:59:59.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.07:59:59.34$vc4f8/va=5,7 2006.176.07:59:59.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.07:59:59.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.07:59:59.34#ibcon#ireg 11 cls_cnt 2 2006.176.07:59:59.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:59:59.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:59:59.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:59:59.40#ibcon#enter wrdev, iclass 22, count 2 2006.176.07:59:59.40#ibcon#first serial, iclass 22, count 2 2006.176.07:59:59.40#ibcon#enter sib2, iclass 22, count 2 2006.176.07:59:59.40#ibcon#flushed, iclass 22, count 2 2006.176.07:59:59.40#ibcon#about to write, iclass 22, count 2 2006.176.07:59:59.40#ibcon#wrote, iclass 22, count 2 2006.176.07:59:59.40#ibcon#about to read 3, iclass 22, count 2 2006.176.07:59:59.42#ibcon#read 3, iclass 22, count 2 2006.176.07:59:59.42#ibcon#about to read 4, iclass 22, count 2 2006.176.07:59:59.42#ibcon#read 4, iclass 22, count 2 2006.176.07:59:59.42#ibcon#about to read 5, iclass 22, count 2 2006.176.07:59:59.42#ibcon#read 5, iclass 22, count 2 2006.176.07:59:59.42#ibcon#about to read 6, iclass 22, count 2 2006.176.07:59:59.42#ibcon#read 6, iclass 22, count 2 2006.176.07:59:59.42#ibcon#end of sib2, iclass 22, count 2 2006.176.07:59:59.42#ibcon#*mode == 0, iclass 22, count 2 2006.176.07:59:59.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.07:59:59.42#ibcon#[25=AT05-07\r\n] 2006.176.07:59:59.42#ibcon#*before write, iclass 22, count 2 2006.176.07:59:59.42#ibcon#enter sib2, iclass 22, count 2 2006.176.07:59:59.42#ibcon#flushed, iclass 22, count 2 2006.176.07:59:59.42#ibcon#about to write, iclass 22, count 2 2006.176.07:59:59.42#ibcon#wrote, iclass 22, count 2 2006.176.07:59:59.42#ibcon#about to read 3, iclass 22, count 2 2006.176.07:59:59.45#ibcon#read 3, iclass 22, count 2 2006.176.07:59:59.45#ibcon#about to read 4, iclass 22, count 2 2006.176.07:59:59.45#ibcon#read 4, iclass 22, count 2 2006.176.07:59:59.45#ibcon#about to read 5, iclass 22, count 2 2006.176.07:59:59.45#ibcon#read 5, iclass 22, count 2 2006.176.07:59:59.45#ibcon#about to read 6, iclass 22, count 2 2006.176.07:59:59.45#ibcon#read 6, iclass 22, count 2 2006.176.07:59:59.45#ibcon#end of sib2, iclass 22, count 2 2006.176.07:59:59.45#ibcon#*after write, iclass 22, count 2 2006.176.07:59:59.45#ibcon#*before return 0, iclass 22, count 2 2006.176.07:59:59.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:59:59.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.07:59:59.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.07:59:59.45#ibcon#ireg 7 cls_cnt 0 2006.176.07:59:59.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:59:59.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:59:59.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:59:59.57#ibcon#enter wrdev, iclass 22, count 0 2006.176.07:59:59.57#ibcon#first serial, iclass 22, count 0 2006.176.07:59:59.57#ibcon#enter sib2, iclass 22, count 0 2006.176.07:59:59.57#ibcon#flushed, iclass 22, count 0 2006.176.07:59:59.57#ibcon#about to write, iclass 22, count 0 2006.176.07:59:59.57#ibcon#wrote, iclass 22, count 0 2006.176.07:59:59.57#ibcon#about to read 3, iclass 22, count 0 2006.176.07:59:59.59#ibcon#read 3, iclass 22, count 0 2006.176.07:59:59.59#ibcon#about to read 4, iclass 22, count 0 2006.176.07:59:59.59#ibcon#read 4, iclass 22, count 0 2006.176.07:59:59.59#ibcon#about to read 5, iclass 22, count 0 2006.176.07:59:59.59#ibcon#read 5, iclass 22, count 0 2006.176.07:59:59.59#ibcon#about to read 6, iclass 22, count 0 2006.176.07:59:59.59#ibcon#read 6, iclass 22, count 0 2006.176.07:59:59.59#ibcon#end of sib2, iclass 22, count 0 2006.176.07:59:59.59#ibcon#*mode == 0, iclass 22, count 0 2006.176.07:59:59.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.07:59:59.59#ibcon#[25=USB\r\n] 2006.176.07:59:59.59#ibcon#*before write, iclass 22, count 0 2006.176.07:59:59.59#ibcon#enter sib2, iclass 22, count 0 2006.176.07:59:59.59#ibcon#flushed, iclass 22, count 0 2006.176.07:59:59.59#ibcon#about to write, iclass 22, count 0 2006.176.07:59:59.59#ibcon#wrote, iclass 22, count 0 2006.176.07:59:59.59#ibcon#about to read 3, iclass 22, count 0 2006.176.07:59:59.62#ibcon#read 3, iclass 22, count 0 2006.176.07:59:59.62#ibcon#about to read 4, iclass 22, count 0 2006.176.07:59:59.62#ibcon#read 4, iclass 22, count 0 2006.176.07:59:59.62#ibcon#about to read 5, iclass 22, count 0 2006.176.07:59:59.62#ibcon#read 5, iclass 22, count 0 2006.176.07:59:59.62#ibcon#about to read 6, iclass 22, count 0 2006.176.07:59:59.62#ibcon#read 6, iclass 22, count 0 2006.176.07:59:59.62#ibcon#end of sib2, iclass 22, count 0 2006.176.07:59:59.62#ibcon#*after write, iclass 22, count 0 2006.176.07:59:59.62#ibcon#*before return 0, iclass 22, count 0 2006.176.07:59:59.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:59:59.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.07:59:59.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.07:59:59.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.07:59:59.62$vc4f8/valo=6,772.99 2006.176.07:59:59.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.07:59:59.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.07:59:59.62#ibcon#ireg 17 cls_cnt 0 2006.176.07:59:59.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:59:59.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:59:59.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:59:59.62#ibcon#enter wrdev, iclass 24, count 0 2006.176.07:59:59.62#ibcon#first serial, iclass 24, count 0 2006.176.07:59:59.62#ibcon#enter sib2, iclass 24, count 0 2006.176.07:59:59.62#ibcon#flushed, iclass 24, count 0 2006.176.07:59:59.62#ibcon#about to write, iclass 24, count 0 2006.176.07:59:59.62#ibcon#wrote, iclass 24, count 0 2006.176.07:59:59.62#ibcon#about to read 3, iclass 24, count 0 2006.176.07:59:59.64#ibcon#read 3, iclass 24, count 0 2006.176.07:59:59.64#ibcon#about to read 4, iclass 24, count 0 2006.176.07:59:59.64#ibcon#read 4, iclass 24, count 0 2006.176.07:59:59.64#ibcon#about to read 5, iclass 24, count 0 2006.176.07:59:59.64#ibcon#read 5, iclass 24, count 0 2006.176.07:59:59.64#ibcon#about to read 6, iclass 24, count 0 2006.176.07:59:59.64#ibcon#read 6, iclass 24, count 0 2006.176.07:59:59.64#ibcon#end of sib2, iclass 24, count 0 2006.176.07:59:59.64#ibcon#*mode == 0, iclass 24, count 0 2006.176.07:59:59.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.07:59:59.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.07:59:59.64#ibcon#*before write, iclass 24, count 0 2006.176.07:59:59.64#ibcon#enter sib2, iclass 24, count 0 2006.176.07:59:59.64#ibcon#flushed, iclass 24, count 0 2006.176.07:59:59.64#ibcon#about to write, iclass 24, count 0 2006.176.07:59:59.64#ibcon#wrote, iclass 24, count 0 2006.176.07:59:59.64#ibcon#about to read 3, iclass 24, count 0 2006.176.07:59:59.68#ibcon#read 3, iclass 24, count 0 2006.176.07:59:59.68#ibcon#about to read 4, iclass 24, count 0 2006.176.07:59:59.68#ibcon#read 4, iclass 24, count 0 2006.176.07:59:59.68#ibcon#about to read 5, iclass 24, count 0 2006.176.07:59:59.68#ibcon#read 5, iclass 24, count 0 2006.176.07:59:59.68#ibcon#about to read 6, iclass 24, count 0 2006.176.07:59:59.68#ibcon#read 6, iclass 24, count 0 2006.176.07:59:59.68#ibcon#end of sib2, iclass 24, count 0 2006.176.07:59:59.68#ibcon#*after write, iclass 24, count 0 2006.176.07:59:59.68#ibcon#*before return 0, iclass 24, count 0 2006.176.07:59:59.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:59:59.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.07:59:59.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.07:59:59.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.07:59:59.68$vc4f8/va=6,6 2006.176.07:59:59.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.07:59:59.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.07:59:59.68#ibcon#ireg 11 cls_cnt 2 2006.176.07:59:59.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:59:59.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:59:59.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:59:59.74#ibcon#enter wrdev, iclass 26, count 2 2006.176.07:59:59.74#ibcon#first serial, iclass 26, count 2 2006.176.07:59:59.74#ibcon#enter sib2, iclass 26, count 2 2006.176.07:59:59.74#ibcon#flushed, iclass 26, count 2 2006.176.07:59:59.74#ibcon#about to write, iclass 26, count 2 2006.176.07:59:59.74#ibcon#wrote, iclass 26, count 2 2006.176.07:59:59.74#ibcon#about to read 3, iclass 26, count 2 2006.176.07:59:59.77#ibcon#read 3, iclass 26, count 2 2006.176.07:59:59.77#ibcon#about to read 4, iclass 26, count 2 2006.176.07:59:59.77#ibcon#read 4, iclass 26, count 2 2006.176.07:59:59.77#ibcon#about to read 5, iclass 26, count 2 2006.176.07:59:59.77#ibcon#read 5, iclass 26, count 2 2006.176.07:59:59.77#ibcon#about to read 6, iclass 26, count 2 2006.176.07:59:59.77#ibcon#read 6, iclass 26, count 2 2006.176.07:59:59.77#ibcon#end of sib2, iclass 26, count 2 2006.176.07:59:59.77#ibcon#*mode == 0, iclass 26, count 2 2006.176.07:59:59.77#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.07:59:59.77#ibcon#[25=AT06-06\r\n] 2006.176.07:59:59.77#ibcon#*before write, iclass 26, count 2 2006.176.07:59:59.77#ibcon#enter sib2, iclass 26, count 2 2006.176.07:59:59.77#ibcon#flushed, iclass 26, count 2 2006.176.07:59:59.77#ibcon#about to write, iclass 26, count 2 2006.176.07:59:59.77#ibcon#wrote, iclass 26, count 2 2006.176.07:59:59.77#ibcon#about to read 3, iclass 26, count 2 2006.176.07:59:59.79#ibcon#read 3, iclass 26, count 2 2006.176.07:59:59.79#ibcon#about to read 4, iclass 26, count 2 2006.176.07:59:59.79#ibcon#read 4, iclass 26, count 2 2006.176.07:59:59.79#ibcon#about to read 5, iclass 26, count 2 2006.176.07:59:59.79#ibcon#read 5, iclass 26, count 2 2006.176.07:59:59.79#ibcon#about to read 6, iclass 26, count 2 2006.176.07:59:59.79#ibcon#read 6, iclass 26, count 2 2006.176.07:59:59.79#ibcon#end of sib2, iclass 26, count 2 2006.176.07:59:59.79#ibcon#*after write, iclass 26, count 2 2006.176.07:59:59.79#ibcon#*before return 0, iclass 26, count 2 2006.176.07:59:59.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:59:59.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.07:59:59.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.07:59:59.79#ibcon#ireg 7 cls_cnt 0 2006.176.07:59:59.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:59:59.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:59:59.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:59:59.91#ibcon#enter wrdev, iclass 26, count 0 2006.176.07:59:59.91#ibcon#first serial, iclass 26, count 0 2006.176.07:59:59.91#ibcon#enter sib2, iclass 26, count 0 2006.176.07:59:59.91#ibcon#flushed, iclass 26, count 0 2006.176.07:59:59.91#ibcon#about to write, iclass 26, count 0 2006.176.07:59:59.91#ibcon#wrote, iclass 26, count 0 2006.176.07:59:59.91#ibcon#about to read 3, iclass 26, count 0 2006.176.07:59:59.93#ibcon#read 3, iclass 26, count 0 2006.176.07:59:59.93#ibcon#about to read 4, iclass 26, count 0 2006.176.07:59:59.93#ibcon#read 4, iclass 26, count 0 2006.176.07:59:59.93#ibcon#about to read 5, iclass 26, count 0 2006.176.07:59:59.93#ibcon#read 5, iclass 26, count 0 2006.176.07:59:59.93#ibcon#about to read 6, iclass 26, count 0 2006.176.07:59:59.93#ibcon#read 6, iclass 26, count 0 2006.176.07:59:59.93#ibcon#end of sib2, iclass 26, count 0 2006.176.07:59:59.93#ibcon#*mode == 0, iclass 26, count 0 2006.176.07:59:59.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.07:59:59.93#ibcon#[25=USB\r\n] 2006.176.07:59:59.93#ibcon#*before write, iclass 26, count 0 2006.176.07:59:59.93#ibcon#enter sib2, iclass 26, count 0 2006.176.07:59:59.93#ibcon#flushed, iclass 26, count 0 2006.176.07:59:59.93#ibcon#about to write, iclass 26, count 0 2006.176.07:59:59.93#ibcon#wrote, iclass 26, count 0 2006.176.07:59:59.93#ibcon#about to read 3, iclass 26, count 0 2006.176.07:59:59.96#ibcon#read 3, iclass 26, count 0 2006.176.07:59:59.96#ibcon#about to read 4, iclass 26, count 0 2006.176.07:59:59.96#ibcon#read 4, iclass 26, count 0 2006.176.07:59:59.96#ibcon#about to read 5, iclass 26, count 0 2006.176.07:59:59.96#ibcon#read 5, iclass 26, count 0 2006.176.07:59:59.96#ibcon#about to read 6, iclass 26, count 0 2006.176.07:59:59.96#ibcon#read 6, iclass 26, count 0 2006.176.07:59:59.96#ibcon#end of sib2, iclass 26, count 0 2006.176.07:59:59.96#ibcon#*after write, iclass 26, count 0 2006.176.07:59:59.96#ibcon#*before return 0, iclass 26, count 0 2006.176.07:59:59.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:59:59.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.07:59:59.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.07:59:59.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.07:59:59.96$vc4f8/valo=7,832.99 2006.176.07:59:59.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.07:59:59.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.07:59:59.96#ibcon#ireg 17 cls_cnt 0 2006.176.07:59:59.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:59:59.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:59:59.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.07:59:59.96#ibcon#enter wrdev, iclass 28, count 0 2006.176.07:59:59.96#ibcon#first serial, iclass 28, count 0 2006.176.07:59:59.96#ibcon#enter sib2, iclass 28, count 0 2006.176.07:59:59.96#ibcon#flushed, iclass 28, count 0 2006.176.07:59:59.96#ibcon#about to write, iclass 28, count 0 2006.176.07:59:59.96#ibcon#wrote, iclass 28, count 0 2006.176.07:59:59.96#ibcon#about to read 3, iclass 28, count 0 2006.176.07:59:59.98#ibcon#read 3, iclass 28, count 0 2006.176.07:59:59.98#ibcon#about to read 4, iclass 28, count 0 2006.176.07:59:59.98#ibcon#read 4, iclass 28, count 0 2006.176.07:59:59.98#ibcon#about to read 5, iclass 28, count 0 2006.176.07:59:59.98#ibcon#read 5, iclass 28, count 0 2006.176.07:59:59.98#ibcon#about to read 6, iclass 28, count 0 2006.176.07:59:59.98#ibcon#read 6, iclass 28, count 0 2006.176.07:59:59.98#ibcon#end of sib2, iclass 28, count 0 2006.176.07:59:59.98#ibcon#*mode == 0, iclass 28, count 0 2006.176.07:59:59.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.07:59:59.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.07:59:59.98#ibcon#*before write, iclass 28, count 0 2006.176.07:59:59.98#ibcon#enter sib2, iclass 28, count 0 2006.176.07:59:59.98#ibcon#flushed, iclass 28, count 0 2006.176.07:59:59.98#ibcon#about to write, iclass 28, count 0 2006.176.07:59:59.98#ibcon#wrote, iclass 28, count 0 2006.176.07:59:59.98#ibcon#about to read 3, iclass 28, count 0 2006.176.08:00:00.02#ibcon#read 3, iclass 28, count 0 2006.176.08:00:00.02#ibcon#about to read 4, iclass 28, count 0 2006.176.08:00:00.02#ibcon#read 4, iclass 28, count 0 2006.176.08:00:00.02#ibcon#about to read 5, iclass 28, count 0 2006.176.08:00:00.02#ibcon#read 5, iclass 28, count 0 2006.176.08:00:00.02#ibcon#about to read 6, iclass 28, count 0 2006.176.08:00:00.02#ibcon#read 6, iclass 28, count 0 2006.176.08:00:00.02#ibcon#end of sib2, iclass 28, count 0 2006.176.08:00:00.02#ibcon#*after write, iclass 28, count 0 2006.176.08:00:00.02#ibcon#*before return 0, iclass 28, count 0 2006.176.08:00:00.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:00:00.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:00:00.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:00:00.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:00:00.02$vc4f8/va=7,6 2006.176.08:00:00.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.08:00:00.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.08:00:00.02#ibcon#ireg 11 cls_cnt 2 2006.176.08:00:00.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:00:00.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:00:00.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:00:00.08#ibcon#enter wrdev, iclass 30, count 2 2006.176.08:00:00.08#ibcon#first serial, iclass 30, count 2 2006.176.08:00:00.08#ibcon#enter sib2, iclass 30, count 2 2006.176.08:00:00.08#ibcon#flushed, iclass 30, count 2 2006.176.08:00:00.08#ibcon#about to write, iclass 30, count 2 2006.176.08:00:00.08#ibcon#wrote, iclass 30, count 2 2006.176.08:00:00.08#ibcon#about to read 3, iclass 30, count 2 2006.176.08:00:00.10#ibcon#read 3, iclass 30, count 2 2006.176.08:00:00.10#ibcon#about to read 4, iclass 30, count 2 2006.176.08:00:00.10#ibcon#read 4, iclass 30, count 2 2006.176.08:00:00.10#ibcon#about to read 5, iclass 30, count 2 2006.176.08:00:00.10#ibcon#read 5, iclass 30, count 2 2006.176.08:00:00.10#ibcon#about to read 6, iclass 30, count 2 2006.176.08:00:00.10#ibcon#read 6, iclass 30, count 2 2006.176.08:00:00.10#ibcon#end of sib2, iclass 30, count 2 2006.176.08:00:00.10#ibcon#*mode == 0, iclass 30, count 2 2006.176.08:00:00.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.08:00:00.10#ibcon#[25=AT07-06\r\n] 2006.176.08:00:00.10#ibcon#*before write, iclass 30, count 2 2006.176.08:00:00.10#ibcon#enter sib2, iclass 30, count 2 2006.176.08:00:00.10#ibcon#flushed, iclass 30, count 2 2006.176.08:00:00.10#ibcon#about to write, iclass 30, count 2 2006.176.08:00:00.10#ibcon#wrote, iclass 30, count 2 2006.176.08:00:00.10#ibcon#about to read 3, iclass 30, count 2 2006.176.08:00:00.13#ibcon#read 3, iclass 30, count 2 2006.176.08:00:00.13#ibcon#about to read 4, iclass 30, count 2 2006.176.08:00:00.13#ibcon#read 4, iclass 30, count 2 2006.176.08:00:00.13#ibcon#about to read 5, iclass 30, count 2 2006.176.08:00:00.13#ibcon#read 5, iclass 30, count 2 2006.176.08:00:00.13#ibcon#about to read 6, iclass 30, count 2 2006.176.08:00:00.13#ibcon#read 6, iclass 30, count 2 2006.176.08:00:00.13#ibcon#end of sib2, iclass 30, count 2 2006.176.08:00:00.13#ibcon#*after write, iclass 30, count 2 2006.176.08:00:00.13#ibcon#*before return 0, iclass 30, count 2 2006.176.08:00:00.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:00:00.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:00:00.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.08:00:00.13#ibcon#ireg 7 cls_cnt 0 2006.176.08:00:00.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:00:00.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:00:00.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:00:00.25#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:00:00.25#ibcon#first serial, iclass 30, count 0 2006.176.08:00:00.25#ibcon#enter sib2, iclass 30, count 0 2006.176.08:00:00.25#ibcon#flushed, iclass 30, count 0 2006.176.08:00:00.25#ibcon#about to write, iclass 30, count 0 2006.176.08:00:00.25#ibcon#wrote, iclass 30, count 0 2006.176.08:00:00.25#ibcon#about to read 3, iclass 30, count 0 2006.176.08:00:00.27#ibcon#read 3, iclass 30, count 0 2006.176.08:00:00.27#ibcon#about to read 4, iclass 30, count 0 2006.176.08:00:00.27#ibcon#read 4, iclass 30, count 0 2006.176.08:00:00.27#ibcon#about to read 5, iclass 30, count 0 2006.176.08:00:00.27#ibcon#read 5, iclass 30, count 0 2006.176.08:00:00.27#ibcon#about to read 6, iclass 30, count 0 2006.176.08:00:00.27#ibcon#read 6, iclass 30, count 0 2006.176.08:00:00.27#ibcon#end of sib2, iclass 30, count 0 2006.176.08:00:00.27#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:00:00.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:00:00.27#ibcon#[25=USB\r\n] 2006.176.08:00:00.27#ibcon#*before write, iclass 30, count 0 2006.176.08:00:00.27#ibcon#enter sib2, iclass 30, count 0 2006.176.08:00:00.27#ibcon#flushed, iclass 30, count 0 2006.176.08:00:00.27#ibcon#about to write, iclass 30, count 0 2006.176.08:00:00.27#ibcon#wrote, iclass 30, count 0 2006.176.08:00:00.27#ibcon#about to read 3, iclass 30, count 0 2006.176.08:00:00.30#ibcon#read 3, iclass 30, count 0 2006.176.08:00:00.30#ibcon#about to read 4, iclass 30, count 0 2006.176.08:00:00.30#ibcon#read 4, iclass 30, count 0 2006.176.08:00:00.30#ibcon#about to read 5, iclass 30, count 0 2006.176.08:00:00.30#ibcon#read 5, iclass 30, count 0 2006.176.08:00:00.30#ibcon#about to read 6, iclass 30, count 0 2006.176.08:00:00.30#ibcon#read 6, iclass 30, count 0 2006.176.08:00:00.30#ibcon#end of sib2, iclass 30, count 0 2006.176.08:00:00.30#ibcon#*after write, iclass 30, count 0 2006.176.08:00:00.30#ibcon#*before return 0, iclass 30, count 0 2006.176.08:00:00.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:00:00.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:00:00.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:00:00.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:00:00.30$vc4f8/valo=8,852.99 2006.176.08:00:00.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.08:00:00.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.08:00:00.30#ibcon#ireg 17 cls_cnt 0 2006.176.08:00:00.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:00:00.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:00:00.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:00:00.30#ibcon#enter wrdev, iclass 32, count 0 2006.176.08:00:00.30#ibcon#first serial, iclass 32, count 0 2006.176.08:00:00.30#ibcon#enter sib2, iclass 32, count 0 2006.176.08:00:00.30#ibcon#flushed, iclass 32, count 0 2006.176.08:00:00.30#ibcon#about to write, iclass 32, count 0 2006.176.08:00:00.30#ibcon#wrote, iclass 32, count 0 2006.176.08:00:00.30#ibcon#about to read 3, iclass 32, count 0 2006.176.08:00:00.32#ibcon#read 3, iclass 32, count 0 2006.176.08:00:00.32#ibcon#about to read 4, iclass 32, count 0 2006.176.08:00:00.32#ibcon#read 4, iclass 32, count 0 2006.176.08:00:00.32#ibcon#about to read 5, iclass 32, count 0 2006.176.08:00:00.32#ibcon#read 5, iclass 32, count 0 2006.176.08:00:00.32#ibcon#about to read 6, iclass 32, count 0 2006.176.08:00:00.32#ibcon#read 6, iclass 32, count 0 2006.176.08:00:00.32#ibcon#end of sib2, iclass 32, count 0 2006.176.08:00:00.32#ibcon#*mode == 0, iclass 32, count 0 2006.176.08:00:00.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.08:00:00.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:00:00.32#ibcon#*before write, iclass 32, count 0 2006.176.08:00:00.32#ibcon#enter sib2, iclass 32, count 0 2006.176.08:00:00.32#ibcon#flushed, iclass 32, count 0 2006.176.08:00:00.32#ibcon#about to write, iclass 32, count 0 2006.176.08:00:00.32#ibcon#wrote, iclass 32, count 0 2006.176.08:00:00.32#ibcon#about to read 3, iclass 32, count 0 2006.176.08:00:00.36#ibcon#read 3, iclass 32, count 0 2006.176.08:00:00.36#ibcon#about to read 4, iclass 32, count 0 2006.176.08:00:00.36#ibcon#read 4, iclass 32, count 0 2006.176.08:00:00.36#ibcon#about to read 5, iclass 32, count 0 2006.176.08:00:00.36#ibcon#read 5, iclass 32, count 0 2006.176.08:00:00.36#ibcon#about to read 6, iclass 32, count 0 2006.176.08:00:00.36#ibcon#read 6, iclass 32, count 0 2006.176.08:00:00.36#ibcon#end of sib2, iclass 32, count 0 2006.176.08:00:00.36#ibcon#*after write, iclass 32, count 0 2006.176.08:00:00.36#ibcon#*before return 0, iclass 32, count 0 2006.176.08:00:00.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:00:00.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:00:00.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.08:00:00.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.08:00:00.36$vc4f8/va=8,6 2006.176.08:00:00.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.08:00:00.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.08:00:00.36#ibcon#ireg 11 cls_cnt 2 2006.176.08:00:00.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:00:00.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:00:00.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:00:00.42#ibcon#enter wrdev, iclass 34, count 2 2006.176.08:00:00.42#ibcon#first serial, iclass 34, count 2 2006.176.08:00:00.42#ibcon#enter sib2, iclass 34, count 2 2006.176.08:00:00.42#ibcon#flushed, iclass 34, count 2 2006.176.08:00:00.42#ibcon#about to write, iclass 34, count 2 2006.176.08:00:00.42#ibcon#wrote, iclass 34, count 2 2006.176.08:00:00.42#ibcon#about to read 3, iclass 34, count 2 2006.176.08:00:00.44#ibcon#read 3, iclass 34, count 2 2006.176.08:00:00.44#ibcon#about to read 4, iclass 34, count 2 2006.176.08:00:00.44#ibcon#read 4, iclass 34, count 2 2006.176.08:00:00.44#ibcon#about to read 5, iclass 34, count 2 2006.176.08:00:00.44#ibcon#read 5, iclass 34, count 2 2006.176.08:00:00.44#ibcon#about to read 6, iclass 34, count 2 2006.176.08:00:00.44#ibcon#read 6, iclass 34, count 2 2006.176.08:00:00.44#ibcon#end of sib2, iclass 34, count 2 2006.176.08:00:00.44#ibcon#*mode == 0, iclass 34, count 2 2006.176.08:00:00.44#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.08:00:00.44#ibcon#[25=AT08-06\r\n] 2006.176.08:00:00.44#ibcon#*before write, iclass 34, count 2 2006.176.08:00:00.44#ibcon#enter sib2, iclass 34, count 2 2006.176.08:00:00.44#ibcon#flushed, iclass 34, count 2 2006.176.08:00:00.44#ibcon#about to write, iclass 34, count 2 2006.176.08:00:00.44#ibcon#wrote, iclass 34, count 2 2006.176.08:00:00.44#ibcon#about to read 3, iclass 34, count 2 2006.176.08:00:00.47#ibcon#read 3, iclass 34, count 2 2006.176.08:00:00.47#ibcon#about to read 4, iclass 34, count 2 2006.176.08:00:00.47#ibcon#read 4, iclass 34, count 2 2006.176.08:00:00.47#ibcon#about to read 5, iclass 34, count 2 2006.176.08:00:00.47#ibcon#read 5, iclass 34, count 2 2006.176.08:00:00.47#ibcon#about to read 6, iclass 34, count 2 2006.176.08:00:00.47#ibcon#read 6, iclass 34, count 2 2006.176.08:00:00.47#ibcon#end of sib2, iclass 34, count 2 2006.176.08:00:00.47#ibcon#*after write, iclass 34, count 2 2006.176.08:00:00.47#ibcon#*before return 0, iclass 34, count 2 2006.176.08:00:00.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:00:00.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:00:00.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.08:00:00.47#ibcon#ireg 7 cls_cnt 0 2006.176.08:00:00.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:00:00.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:00:00.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:00:00.59#ibcon#enter wrdev, iclass 34, count 0 2006.176.08:00:00.59#ibcon#first serial, iclass 34, count 0 2006.176.08:00:00.59#ibcon#enter sib2, iclass 34, count 0 2006.176.08:00:00.59#ibcon#flushed, iclass 34, count 0 2006.176.08:00:00.59#ibcon#about to write, iclass 34, count 0 2006.176.08:00:00.59#ibcon#wrote, iclass 34, count 0 2006.176.08:00:00.59#ibcon#about to read 3, iclass 34, count 0 2006.176.08:00:00.61#ibcon#read 3, iclass 34, count 0 2006.176.08:00:00.61#ibcon#about to read 4, iclass 34, count 0 2006.176.08:00:00.61#ibcon#read 4, iclass 34, count 0 2006.176.08:00:00.61#ibcon#about to read 5, iclass 34, count 0 2006.176.08:00:00.61#ibcon#read 5, iclass 34, count 0 2006.176.08:00:00.61#ibcon#about to read 6, iclass 34, count 0 2006.176.08:00:00.61#ibcon#read 6, iclass 34, count 0 2006.176.08:00:00.61#ibcon#end of sib2, iclass 34, count 0 2006.176.08:00:00.61#ibcon#*mode == 0, iclass 34, count 0 2006.176.08:00:00.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.08:00:00.61#ibcon#[25=USB\r\n] 2006.176.08:00:00.61#ibcon#*before write, iclass 34, count 0 2006.176.08:00:00.61#ibcon#enter sib2, iclass 34, count 0 2006.176.08:00:00.61#ibcon#flushed, iclass 34, count 0 2006.176.08:00:00.61#ibcon#about to write, iclass 34, count 0 2006.176.08:00:00.61#ibcon#wrote, iclass 34, count 0 2006.176.08:00:00.61#ibcon#about to read 3, iclass 34, count 0 2006.176.08:00:00.64#ibcon#read 3, iclass 34, count 0 2006.176.08:00:00.64#ibcon#about to read 4, iclass 34, count 0 2006.176.08:00:00.64#ibcon#read 4, iclass 34, count 0 2006.176.08:00:00.64#ibcon#about to read 5, iclass 34, count 0 2006.176.08:00:00.64#ibcon#read 5, iclass 34, count 0 2006.176.08:00:00.64#ibcon#about to read 6, iclass 34, count 0 2006.176.08:00:00.64#ibcon#read 6, iclass 34, count 0 2006.176.08:00:00.64#ibcon#end of sib2, iclass 34, count 0 2006.176.08:00:00.64#ibcon#*after write, iclass 34, count 0 2006.176.08:00:00.64#ibcon#*before return 0, iclass 34, count 0 2006.176.08:00:00.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:00:00.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:00:00.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.08:00:00.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.08:00:00.64$vc4f8/vblo=1,632.99 2006.176.08:00:00.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.08:00:00.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.08:00:00.64#ibcon#ireg 17 cls_cnt 0 2006.176.08:00:00.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:00:00.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:00:00.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:00:00.64#ibcon#enter wrdev, iclass 36, count 0 2006.176.08:00:00.64#ibcon#first serial, iclass 36, count 0 2006.176.08:00:00.64#ibcon#enter sib2, iclass 36, count 0 2006.176.08:00:00.64#ibcon#flushed, iclass 36, count 0 2006.176.08:00:00.64#ibcon#about to write, iclass 36, count 0 2006.176.08:00:00.64#ibcon#wrote, iclass 36, count 0 2006.176.08:00:00.64#ibcon#about to read 3, iclass 36, count 0 2006.176.08:00:00.66#ibcon#read 3, iclass 36, count 0 2006.176.08:00:00.66#ibcon#about to read 4, iclass 36, count 0 2006.176.08:00:00.66#ibcon#read 4, iclass 36, count 0 2006.176.08:00:00.66#ibcon#about to read 5, iclass 36, count 0 2006.176.08:00:00.66#ibcon#read 5, iclass 36, count 0 2006.176.08:00:00.66#ibcon#about to read 6, iclass 36, count 0 2006.176.08:00:00.66#ibcon#read 6, iclass 36, count 0 2006.176.08:00:00.66#ibcon#end of sib2, iclass 36, count 0 2006.176.08:00:00.66#ibcon#*mode == 0, iclass 36, count 0 2006.176.08:00:00.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.08:00:00.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:00:00.66#ibcon#*before write, iclass 36, count 0 2006.176.08:00:00.66#ibcon#enter sib2, iclass 36, count 0 2006.176.08:00:00.66#ibcon#flushed, iclass 36, count 0 2006.176.08:00:00.66#ibcon#about to write, iclass 36, count 0 2006.176.08:00:00.66#ibcon#wrote, iclass 36, count 0 2006.176.08:00:00.66#ibcon#about to read 3, iclass 36, count 0 2006.176.08:00:00.70#ibcon#read 3, iclass 36, count 0 2006.176.08:00:00.70#ibcon#about to read 4, iclass 36, count 0 2006.176.08:00:00.70#ibcon#read 4, iclass 36, count 0 2006.176.08:00:00.70#ibcon#about to read 5, iclass 36, count 0 2006.176.08:00:00.70#ibcon#read 5, iclass 36, count 0 2006.176.08:00:00.70#ibcon#about to read 6, iclass 36, count 0 2006.176.08:00:00.70#ibcon#read 6, iclass 36, count 0 2006.176.08:00:00.70#ibcon#end of sib2, iclass 36, count 0 2006.176.08:00:00.70#ibcon#*after write, iclass 36, count 0 2006.176.08:00:00.70#ibcon#*before return 0, iclass 36, count 0 2006.176.08:00:00.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:00:00.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:00:00.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.08:00:00.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.08:00:00.70$vc4f8/vb=1,4 2006.176.08:00:00.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.08:00:00.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.08:00:00.70#ibcon#ireg 11 cls_cnt 2 2006.176.08:00:00.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:00:00.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:00:00.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:00:00.70#ibcon#enter wrdev, iclass 38, count 2 2006.176.08:00:00.70#ibcon#first serial, iclass 38, count 2 2006.176.08:00:00.70#ibcon#enter sib2, iclass 38, count 2 2006.176.08:00:00.70#ibcon#flushed, iclass 38, count 2 2006.176.08:00:00.70#ibcon#about to write, iclass 38, count 2 2006.176.08:00:00.70#ibcon#wrote, iclass 38, count 2 2006.176.08:00:00.70#ibcon#about to read 3, iclass 38, count 2 2006.176.08:00:00.72#ibcon#read 3, iclass 38, count 2 2006.176.08:00:00.72#ibcon#about to read 4, iclass 38, count 2 2006.176.08:00:00.72#ibcon#read 4, iclass 38, count 2 2006.176.08:00:00.72#ibcon#about to read 5, iclass 38, count 2 2006.176.08:00:00.72#ibcon#read 5, iclass 38, count 2 2006.176.08:00:00.72#ibcon#about to read 6, iclass 38, count 2 2006.176.08:00:00.72#ibcon#read 6, iclass 38, count 2 2006.176.08:00:00.72#ibcon#end of sib2, iclass 38, count 2 2006.176.08:00:00.72#ibcon#*mode == 0, iclass 38, count 2 2006.176.08:00:00.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.08:00:00.72#ibcon#[27=AT01-04\r\n] 2006.176.08:00:00.72#ibcon#*before write, iclass 38, count 2 2006.176.08:00:00.72#ibcon#enter sib2, iclass 38, count 2 2006.176.08:00:00.72#ibcon#flushed, iclass 38, count 2 2006.176.08:00:00.72#ibcon#about to write, iclass 38, count 2 2006.176.08:00:00.72#ibcon#wrote, iclass 38, count 2 2006.176.08:00:00.72#ibcon#about to read 3, iclass 38, count 2 2006.176.08:00:00.76#ibcon#read 3, iclass 38, count 2 2006.176.08:00:00.76#ibcon#about to read 4, iclass 38, count 2 2006.176.08:00:00.76#ibcon#read 4, iclass 38, count 2 2006.176.08:00:00.76#ibcon#about to read 5, iclass 38, count 2 2006.176.08:00:00.76#ibcon#read 5, iclass 38, count 2 2006.176.08:00:00.76#ibcon#about to read 6, iclass 38, count 2 2006.176.08:00:00.76#ibcon#read 6, iclass 38, count 2 2006.176.08:00:00.76#ibcon#end of sib2, iclass 38, count 2 2006.176.08:00:00.76#ibcon#*after write, iclass 38, count 2 2006.176.08:00:00.76#ibcon#*before return 0, iclass 38, count 2 2006.176.08:00:00.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:00:00.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:00:00.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.08:00:00.76#ibcon#ireg 7 cls_cnt 0 2006.176.08:00:00.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:00:00.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:00:00.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:00:00.87#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:00:00.87#ibcon#first serial, iclass 38, count 0 2006.176.08:00:00.87#ibcon#enter sib2, iclass 38, count 0 2006.176.08:00:00.87#ibcon#flushed, iclass 38, count 0 2006.176.08:00:00.87#ibcon#about to write, iclass 38, count 0 2006.176.08:00:00.87#ibcon#wrote, iclass 38, count 0 2006.176.08:00:00.87#ibcon#about to read 3, iclass 38, count 0 2006.176.08:00:00.89#ibcon#read 3, iclass 38, count 0 2006.176.08:00:00.89#ibcon#about to read 4, iclass 38, count 0 2006.176.08:00:00.89#ibcon#read 4, iclass 38, count 0 2006.176.08:00:00.89#ibcon#about to read 5, iclass 38, count 0 2006.176.08:00:00.89#ibcon#read 5, iclass 38, count 0 2006.176.08:00:00.89#ibcon#about to read 6, iclass 38, count 0 2006.176.08:00:00.89#ibcon#read 6, iclass 38, count 0 2006.176.08:00:00.89#ibcon#end of sib2, iclass 38, count 0 2006.176.08:00:00.89#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:00:00.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:00:00.89#ibcon#[27=USB\r\n] 2006.176.08:00:00.89#ibcon#*before write, iclass 38, count 0 2006.176.08:00:00.89#ibcon#enter sib2, iclass 38, count 0 2006.176.08:00:00.89#ibcon#flushed, iclass 38, count 0 2006.176.08:00:00.89#ibcon#about to write, iclass 38, count 0 2006.176.08:00:00.89#ibcon#wrote, iclass 38, count 0 2006.176.08:00:00.89#ibcon#about to read 3, iclass 38, count 0 2006.176.08:00:00.92#ibcon#read 3, iclass 38, count 0 2006.176.08:00:00.92#ibcon#about to read 4, iclass 38, count 0 2006.176.08:00:00.92#ibcon#read 4, iclass 38, count 0 2006.176.08:00:00.92#ibcon#about to read 5, iclass 38, count 0 2006.176.08:00:00.92#ibcon#read 5, iclass 38, count 0 2006.176.08:00:00.92#ibcon#about to read 6, iclass 38, count 0 2006.176.08:00:00.92#ibcon#read 6, iclass 38, count 0 2006.176.08:00:00.92#ibcon#end of sib2, iclass 38, count 0 2006.176.08:00:00.92#ibcon#*after write, iclass 38, count 0 2006.176.08:00:00.92#ibcon#*before return 0, iclass 38, count 0 2006.176.08:00:00.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:00:00.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:00:00.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:00:00.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:00:00.92$vc4f8/vblo=2,640.99 2006.176.08:00:00.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.08:00:00.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.08:00:00.92#ibcon#ireg 17 cls_cnt 0 2006.176.08:00:00.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:00:00.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:00:00.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:00:00.92#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:00:00.92#ibcon#first serial, iclass 40, count 0 2006.176.08:00:00.92#ibcon#enter sib2, iclass 40, count 0 2006.176.08:00:00.92#ibcon#flushed, iclass 40, count 0 2006.176.08:00:00.92#ibcon#about to write, iclass 40, count 0 2006.176.08:00:00.92#ibcon#wrote, iclass 40, count 0 2006.176.08:00:00.92#ibcon#about to read 3, iclass 40, count 0 2006.176.08:00:00.94#ibcon#read 3, iclass 40, count 0 2006.176.08:00:00.94#ibcon#about to read 4, iclass 40, count 0 2006.176.08:00:00.94#ibcon#read 4, iclass 40, count 0 2006.176.08:00:00.94#ibcon#about to read 5, iclass 40, count 0 2006.176.08:00:00.94#ibcon#read 5, iclass 40, count 0 2006.176.08:00:00.94#ibcon#about to read 6, iclass 40, count 0 2006.176.08:00:00.94#ibcon#read 6, iclass 40, count 0 2006.176.08:00:00.94#ibcon#end of sib2, iclass 40, count 0 2006.176.08:00:00.94#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:00:00.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:00:00.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:00:00.94#ibcon#*before write, iclass 40, count 0 2006.176.08:00:00.94#ibcon#enter sib2, iclass 40, count 0 2006.176.08:00:00.94#ibcon#flushed, iclass 40, count 0 2006.176.08:00:00.94#ibcon#about to write, iclass 40, count 0 2006.176.08:00:00.94#ibcon#wrote, iclass 40, count 0 2006.176.08:00:00.94#ibcon#about to read 3, iclass 40, count 0 2006.176.08:00:00.98#ibcon#read 3, iclass 40, count 0 2006.176.08:00:00.98#ibcon#about to read 4, iclass 40, count 0 2006.176.08:00:00.98#ibcon#read 4, iclass 40, count 0 2006.176.08:00:00.98#ibcon#about to read 5, iclass 40, count 0 2006.176.08:00:00.98#ibcon#read 5, iclass 40, count 0 2006.176.08:00:00.98#ibcon#about to read 6, iclass 40, count 0 2006.176.08:00:00.98#ibcon#read 6, iclass 40, count 0 2006.176.08:00:00.98#ibcon#end of sib2, iclass 40, count 0 2006.176.08:00:00.98#ibcon#*after write, iclass 40, count 0 2006.176.08:00:00.98#ibcon#*before return 0, iclass 40, count 0 2006.176.08:00:00.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:00:00.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:00:00.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:00:00.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:00:00.98$vc4f8/vb=2,4 2006.176.08:00:00.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.08:00:00.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.08:00:00.98#ibcon#ireg 11 cls_cnt 2 2006.176.08:00:00.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:00:01.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:00:01.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:00:01.04#ibcon#enter wrdev, iclass 4, count 2 2006.176.08:00:01.04#ibcon#first serial, iclass 4, count 2 2006.176.08:00:01.04#ibcon#enter sib2, iclass 4, count 2 2006.176.08:00:01.04#ibcon#flushed, iclass 4, count 2 2006.176.08:00:01.04#ibcon#about to write, iclass 4, count 2 2006.176.08:00:01.04#ibcon#wrote, iclass 4, count 2 2006.176.08:00:01.04#ibcon#about to read 3, iclass 4, count 2 2006.176.08:00:01.06#ibcon#read 3, iclass 4, count 2 2006.176.08:00:01.06#ibcon#about to read 4, iclass 4, count 2 2006.176.08:00:01.06#ibcon#read 4, iclass 4, count 2 2006.176.08:00:01.06#ibcon#about to read 5, iclass 4, count 2 2006.176.08:00:01.06#ibcon#read 5, iclass 4, count 2 2006.176.08:00:01.06#ibcon#about to read 6, iclass 4, count 2 2006.176.08:00:01.06#ibcon#read 6, iclass 4, count 2 2006.176.08:00:01.06#ibcon#end of sib2, iclass 4, count 2 2006.176.08:00:01.06#ibcon#*mode == 0, iclass 4, count 2 2006.176.08:00:01.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.08:00:01.06#ibcon#[27=AT02-04\r\n] 2006.176.08:00:01.06#ibcon#*before write, iclass 4, count 2 2006.176.08:00:01.06#ibcon#enter sib2, iclass 4, count 2 2006.176.08:00:01.06#ibcon#flushed, iclass 4, count 2 2006.176.08:00:01.06#ibcon#about to write, iclass 4, count 2 2006.176.08:00:01.06#ibcon#wrote, iclass 4, count 2 2006.176.08:00:01.06#ibcon#about to read 3, iclass 4, count 2 2006.176.08:00:01.09#ibcon#read 3, iclass 4, count 2 2006.176.08:00:01.09#ibcon#about to read 4, iclass 4, count 2 2006.176.08:00:01.09#ibcon#read 4, iclass 4, count 2 2006.176.08:00:01.09#ibcon#about to read 5, iclass 4, count 2 2006.176.08:00:01.09#ibcon#read 5, iclass 4, count 2 2006.176.08:00:01.09#ibcon#about to read 6, iclass 4, count 2 2006.176.08:00:01.09#ibcon#read 6, iclass 4, count 2 2006.176.08:00:01.09#ibcon#end of sib2, iclass 4, count 2 2006.176.08:00:01.09#ibcon#*after write, iclass 4, count 2 2006.176.08:00:01.09#ibcon#*before return 0, iclass 4, count 2 2006.176.08:00:01.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:00:01.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:00:01.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.08:00:01.09#ibcon#ireg 7 cls_cnt 0 2006.176.08:00:01.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:00:01.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:00:01.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:00:01.21#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:00:01.21#ibcon#first serial, iclass 4, count 0 2006.176.08:00:01.21#ibcon#enter sib2, iclass 4, count 0 2006.176.08:00:01.21#ibcon#flushed, iclass 4, count 0 2006.176.08:00:01.21#ibcon#about to write, iclass 4, count 0 2006.176.08:00:01.21#ibcon#wrote, iclass 4, count 0 2006.176.08:00:01.21#ibcon#about to read 3, iclass 4, count 0 2006.176.08:00:01.23#ibcon#read 3, iclass 4, count 0 2006.176.08:00:01.23#ibcon#about to read 4, iclass 4, count 0 2006.176.08:00:01.23#ibcon#read 4, iclass 4, count 0 2006.176.08:00:01.23#ibcon#about to read 5, iclass 4, count 0 2006.176.08:00:01.23#ibcon#read 5, iclass 4, count 0 2006.176.08:00:01.23#ibcon#about to read 6, iclass 4, count 0 2006.176.08:00:01.23#ibcon#read 6, iclass 4, count 0 2006.176.08:00:01.23#ibcon#end of sib2, iclass 4, count 0 2006.176.08:00:01.23#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:00:01.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:00:01.23#ibcon#[27=USB\r\n] 2006.176.08:00:01.23#ibcon#*before write, iclass 4, count 0 2006.176.08:00:01.23#ibcon#enter sib2, iclass 4, count 0 2006.176.08:00:01.23#ibcon#flushed, iclass 4, count 0 2006.176.08:00:01.23#ibcon#about to write, iclass 4, count 0 2006.176.08:00:01.23#ibcon#wrote, iclass 4, count 0 2006.176.08:00:01.23#ibcon#about to read 3, iclass 4, count 0 2006.176.08:00:01.26#ibcon#read 3, iclass 4, count 0 2006.176.08:00:01.26#ibcon#about to read 4, iclass 4, count 0 2006.176.08:00:01.26#ibcon#read 4, iclass 4, count 0 2006.176.08:00:01.26#ibcon#about to read 5, iclass 4, count 0 2006.176.08:00:01.26#ibcon#read 5, iclass 4, count 0 2006.176.08:00:01.26#ibcon#about to read 6, iclass 4, count 0 2006.176.08:00:01.26#ibcon#read 6, iclass 4, count 0 2006.176.08:00:01.26#ibcon#end of sib2, iclass 4, count 0 2006.176.08:00:01.26#ibcon#*after write, iclass 4, count 0 2006.176.08:00:01.26#ibcon#*before return 0, iclass 4, count 0 2006.176.08:00:01.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:00:01.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:00:01.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:00:01.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:00:01.26$vc4f8/vblo=3,656.99 2006.176.08:00:01.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.08:00:01.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.08:00:01.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:00:01.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:00:01.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:00:01.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:00:01.26#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:00:01.26#ibcon#first serial, iclass 6, count 0 2006.176.08:00:01.26#ibcon#enter sib2, iclass 6, count 0 2006.176.08:00:01.26#ibcon#flushed, iclass 6, count 0 2006.176.08:00:01.26#ibcon#about to write, iclass 6, count 0 2006.176.08:00:01.26#ibcon#wrote, iclass 6, count 0 2006.176.08:00:01.26#ibcon#about to read 3, iclass 6, count 0 2006.176.08:00:01.28#ibcon#read 3, iclass 6, count 0 2006.176.08:00:01.28#ibcon#about to read 4, iclass 6, count 0 2006.176.08:00:01.28#ibcon#read 4, iclass 6, count 0 2006.176.08:00:01.28#ibcon#about to read 5, iclass 6, count 0 2006.176.08:00:01.28#ibcon#read 5, iclass 6, count 0 2006.176.08:00:01.28#ibcon#about to read 6, iclass 6, count 0 2006.176.08:00:01.28#ibcon#read 6, iclass 6, count 0 2006.176.08:00:01.28#ibcon#end of sib2, iclass 6, count 0 2006.176.08:00:01.28#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:00:01.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:00:01.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:00:01.28#ibcon#*before write, iclass 6, count 0 2006.176.08:00:01.28#ibcon#enter sib2, iclass 6, count 0 2006.176.08:00:01.28#ibcon#flushed, iclass 6, count 0 2006.176.08:00:01.28#ibcon#about to write, iclass 6, count 0 2006.176.08:00:01.28#ibcon#wrote, iclass 6, count 0 2006.176.08:00:01.28#ibcon#about to read 3, iclass 6, count 0 2006.176.08:00:01.32#ibcon#read 3, iclass 6, count 0 2006.176.08:00:01.32#ibcon#about to read 4, iclass 6, count 0 2006.176.08:00:01.32#ibcon#read 4, iclass 6, count 0 2006.176.08:00:01.32#ibcon#about to read 5, iclass 6, count 0 2006.176.08:00:01.32#ibcon#read 5, iclass 6, count 0 2006.176.08:00:01.32#ibcon#about to read 6, iclass 6, count 0 2006.176.08:00:01.32#ibcon#read 6, iclass 6, count 0 2006.176.08:00:01.32#ibcon#end of sib2, iclass 6, count 0 2006.176.08:00:01.32#ibcon#*after write, iclass 6, count 0 2006.176.08:00:01.32#ibcon#*before return 0, iclass 6, count 0 2006.176.08:00:01.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:00:01.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:00:01.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:00:01.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:00:01.32$vc4f8/vb=3,4 2006.176.08:00:01.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.08:00:01.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.08:00:01.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:00:01.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:00:01.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:00:01.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:00:01.38#ibcon#enter wrdev, iclass 10, count 2 2006.176.08:00:01.38#ibcon#first serial, iclass 10, count 2 2006.176.08:00:01.38#ibcon#enter sib2, iclass 10, count 2 2006.176.08:00:01.38#ibcon#flushed, iclass 10, count 2 2006.176.08:00:01.38#ibcon#about to write, iclass 10, count 2 2006.176.08:00:01.38#ibcon#wrote, iclass 10, count 2 2006.176.08:00:01.38#ibcon#about to read 3, iclass 10, count 2 2006.176.08:00:01.40#ibcon#read 3, iclass 10, count 2 2006.176.08:00:01.40#ibcon#about to read 4, iclass 10, count 2 2006.176.08:00:01.40#ibcon#read 4, iclass 10, count 2 2006.176.08:00:01.40#ibcon#about to read 5, iclass 10, count 2 2006.176.08:00:01.40#ibcon#read 5, iclass 10, count 2 2006.176.08:00:01.40#ibcon#about to read 6, iclass 10, count 2 2006.176.08:00:01.40#ibcon#read 6, iclass 10, count 2 2006.176.08:00:01.40#ibcon#end of sib2, iclass 10, count 2 2006.176.08:00:01.40#ibcon#*mode == 0, iclass 10, count 2 2006.176.08:00:01.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.08:00:01.40#ibcon#[27=AT03-04\r\n] 2006.176.08:00:01.40#ibcon#*before write, iclass 10, count 2 2006.176.08:00:01.40#ibcon#enter sib2, iclass 10, count 2 2006.176.08:00:01.40#ibcon#flushed, iclass 10, count 2 2006.176.08:00:01.40#ibcon#about to write, iclass 10, count 2 2006.176.08:00:01.40#ibcon#wrote, iclass 10, count 2 2006.176.08:00:01.40#ibcon#about to read 3, iclass 10, count 2 2006.176.08:00:01.43#ibcon#read 3, iclass 10, count 2 2006.176.08:00:01.43#ibcon#about to read 4, iclass 10, count 2 2006.176.08:00:01.43#ibcon#read 4, iclass 10, count 2 2006.176.08:00:01.43#ibcon#about to read 5, iclass 10, count 2 2006.176.08:00:01.43#ibcon#read 5, iclass 10, count 2 2006.176.08:00:01.43#ibcon#about to read 6, iclass 10, count 2 2006.176.08:00:01.43#ibcon#read 6, iclass 10, count 2 2006.176.08:00:01.43#ibcon#end of sib2, iclass 10, count 2 2006.176.08:00:01.43#ibcon#*after write, iclass 10, count 2 2006.176.08:00:01.43#ibcon#*before return 0, iclass 10, count 2 2006.176.08:00:01.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:00:01.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:00:01.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.08:00:01.43#ibcon#ireg 7 cls_cnt 0 2006.176.08:00:01.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:00:01.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:00:01.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:00:01.55#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:00:01.55#ibcon#first serial, iclass 10, count 0 2006.176.08:00:01.55#ibcon#enter sib2, iclass 10, count 0 2006.176.08:00:01.55#ibcon#flushed, iclass 10, count 0 2006.176.08:00:01.55#ibcon#about to write, iclass 10, count 0 2006.176.08:00:01.55#ibcon#wrote, iclass 10, count 0 2006.176.08:00:01.55#ibcon#about to read 3, iclass 10, count 0 2006.176.08:00:01.57#ibcon#read 3, iclass 10, count 0 2006.176.08:00:01.57#ibcon#about to read 4, iclass 10, count 0 2006.176.08:00:01.57#ibcon#read 4, iclass 10, count 0 2006.176.08:00:01.57#ibcon#about to read 5, iclass 10, count 0 2006.176.08:00:01.57#ibcon#read 5, iclass 10, count 0 2006.176.08:00:01.57#ibcon#about to read 6, iclass 10, count 0 2006.176.08:00:01.57#ibcon#read 6, iclass 10, count 0 2006.176.08:00:01.57#ibcon#end of sib2, iclass 10, count 0 2006.176.08:00:01.57#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:00:01.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:00:01.57#ibcon#[27=USB\r\n] 2006.176.08:00:01.57#ibcon#*before write, iclass 10, count 0 2006.176.08:00:01.57#ibcon#enter sib2, iclass 10, count 0 2006.176.08:00:01.57#ibcon#flushed, iclass 10, count 0 2006.176.08:00:01.57#ibcon#about to write, iclass 10, count 0 2006.176.08:00:01.57#ibcon#wrote, iclass 10, count 0 2006.176.08:00:01.57#ibcon#about to read 3, iclass 10, count 0 2006.176.08:00:01.60#ibcon#read 3, iclass 10, count 0 2006.176.08:00:01.60#ibcon#about to read 4, iclass 10, count 0 2006.176.08:00:01.60#ibcon#read 4, iclass 10, count 0 2006.176.08:00:01.60#ibcon#about to read 5, iclass 10, count 0 2006.176.08:00:01.60#ibcon#read 5, iclass 10, count 0 2006.176.08:00:01.60#ibcon#about to read 6, iclass 10, count 0 2006.176.08:00:01.60#ibcon#read 6, iclass 10, count 0 2006.176.08:00:01.60#ibcon#end of sib2, iclass 10, count 0 2006.176.08:00:01.60#ibcon#*after write, iclass 10, count 0 2006.176.08:00:01.60#ibcon#*before return 0, iclass 10, count 0 2006.176.08:00:01.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:00:01.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:00:01.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:00:01.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:00:01.60$vc4f8/vblo=4,712.99 2006.176.08:00:01.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.08:00:01.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.08:00:01.60#ibcon#ireg 17 cls_cnt 0 2006.176.08:00:01.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:00:01.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:00:01.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:00:01.60#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:00:01.60#ibcon#first serial, iclass 12, count 0 2006.176.08:00:01.60#ibcon#enter sib2, iclass 12, count 0 2006.176.08:00:01.60#ibcon#flushed, iclass 12, count 0 2006.176.08:00:01.60#ibcon#about to write, iclass 12, count 0 2006.176.08:00:01.60#ibcon#wrote, iclass 12, count 0 2006.176.08:00:01.60#ibcon#about to read 3, iclass 12, count 0 2006.176.08:00:01.62#ibcon#read 3, iclass 12, count 0 2006.176.08:00:01.62#ibcon#about to read 4, iclass 12, count 0 2006.176.08:00:01.62#ibcon#read 4, iclass 12, count 0 2006.176.08:00:01.62#ibcon#about to read 5, iclass 12, count 0 2006.176.08:00:01.62#ibcon#read 5, iclass 12, count 0 2006.176.08:00:01.62#ibcon#about to read 6, iclass 12, count 0 2006.176.08:00:01.62#ibcon#read 6, iclass 12, count 0 2006.176.08:00:01.62#ibcon#end of sib2, iclass 12, count 0 2006.176.08:00:01.62#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:00:01.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:00:01.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:00:01.62#ibcon#*before write, iclass 12, count 0 2006.176.08:00:01.62#ibcon#enter sib2, iclass 12, count 0 2006.176.08:00:01.62#ibcon#flushed, iclass 12, count 0 2006.176.08:00:01.62#ibcon#about to write, iclass 12, count 0 2006.176.08:00:01.62#ibcon#wrote, iclass 12, count 0 2006.176.08:00:01.62#ibcon#about to read 3, iclass 12, count 0 2006.176.08:00:01.66#ibcon#read 3, iclass 12, count 0 2006.176.08:00:01.66#ibcon#about to read 4, iclass 12, count 0 2006.176.08:00:01.66#ibcon#read 4, iclass 12, count 0 2006.176.08:00:01.66#ibcon#about to read 5, iclass 12, count 0 2006.176.08:00:01.66#ibcon#read 5, iclass 12, count 0 2006.176.08:00:01.66#ibcon#about to read 6, iclass 12, count 0 2006.176.08:00:01.66#ibcon#read 6, iclass 12, count 0 2006.176.08:00:01.66#ibcon#end of sib2, iclass 12, count 0 2006.176.08:00:01.66#ibcon#*after write, iclass 12, count 0 2006.176.08:00:01.66#ibcon#*before return 0, iclass 12, count 0 2006.176.08:00:01.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:00:01.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:00:01.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:00:01.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:00:01.66$vc4f8/vb=4,4 2006.176.08:00:01.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.08:00:01.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.08:00:01.66#ibcon#ireg 11 cls_cnt 2 2006.176.08:00:01.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:00:01.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:00:01.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:00:01.72#ibcon#enter wrdev, iclass 14, count 2 2006.176.08:00:01.72#ibcon#first serial, iclass 14, count 2 2006.176.08:00:01.72#ibcon#enter sib2, iclass 14, count 2 2006.176.08:00:01.72#ibcon#flushed, iclass 14, count 2 2006.176.08:00:01.72#ibcon#about to write, iclass 14, count 2 2006.176.08:00:01.72#ibcon#wrote, iclass 14, count 2 2006.176.08:00:01.72#ibcon#about to read 3, iclass 14, count 2 2006.176.08:00:01.74#ibcon#read 3, iclass 14, count 2 2006.176.08:00:01.74#ibcon#about to read 4, iclass 14, count 2 2006.176.08:00:01.74#ibcon#read 4, iclass 14, count 2 2006.176.08:00:01.74#ibcon#about to read 5, iclass 14, count 2 2006.176.08:00:01.74#ibcon#read 5, iclass 14, count 2 2006.176.08:00:01.74#ibcon#about to read 6, iclass 14, count 2 2006.176.08:00:01.74#ibcon#read 6, iclass 14, count 2 2006.176.08:00:01.74#ibcon#end of sib2, iclass 14, count 2 2006.176.08:00:01.74#ibcon#*mode == 0, iclass 14, count 2 2006.176.08:00:01.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.08:00:01.74#ibcon#[27=AT04-04\r\n] 2006.176.08:00:01.74#ibcon#*before write, iclass 14, count 2 2006.176.08:00:01.74#ibcon#enter sib2, iclass 14, count 2 2006.176.08:00:01.74#ibcon#flushed, iclass 14, count 2 2006.176.08:00:01.74#ibcon#about to write, iclass 14, count 2 2006.176.08:00:01.74#ibcon#wrote, iclass 14, count 2 2006.176.08:00:01.74#ibcon#about to read 3, iclass 14, count 2 2006.176.08:00:01.77#ibcon#read 3, iclass 14, count 2 2006.176.08:00:01.77#ibcon#about to read 4, iclass 14, count 2 2006.176.08:00:01.77#ibcon#read 4, iclass 14, count 2 2006.176.08:00:01.77#ibcon#about to read 5, iclass 14, count 2 2006.176.08:00:01.77#ibcon#read 5, iclass 14, count 2 2006.176.08:00:01.77#ibcon#about to read 6, iclass 14, count 2 2006.176.08:00:01.77#ibcon#read 6, iclass 14, count 2 2006.176.08:00:01.77#ibcon#end of sib2, iclass 14, count 2 2006.176.08:00:01.77#ibcon#*after write, iclass 14, count 2 2006.176.08:00:01.77#ibcon#*before return 0, iclass 14, count 2 2006.176.08:00:01.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:00:01.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:00:01.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.08:00:01.77#ibcon#ireg 7 cls_cnt 0 2006.176.08:00:01.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:00:01.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:00:01.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:00:01.89#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:00:01.89#ibcon#first serial, iclass 14, count 0 2006.176.08:00:01.89#ibcon#enter sib2, iclass 14, count 0 2006.176.08:00:01.89#ibcon#flushed, iclass 14, count 0 2006.176.08:00:01.89#ibcon#about to write, iclass 14, count 0 2006.176.08:00:01.89#ibcon#wrote, iclass 14, count 0 2006.176.08:00:01.89#ibcon#about to read 3, iclass 14, count 0 2006.176.08:00:01.91#ibcon#read 3, iclass 14, count 0 2006.176.08:00:01.91#ibcon#about to read 4, iclass 14, count 0 2006.176.08:00:01.91#ibcon#read 4, iclass 14, count 0 2006.176.08:00:01.91#ibcon#about to read 5, iclass 14, count 0 2006.176.08:00:01.91#ibcon#read 5, iclass 14, count 0 2006.176.08:00:01.91#ibcon#about to read 6, iclass 14, count 0 2006.176.08:00:01.91#ibcon#read 6, iclass 14, count 0 2006.176.08:00:01.91#ibcon#end of sib2, iclass 14, count 0 2006.176.08:00:01.91#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:00:01.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:00:01.91#ibcon#[27=USB\r\n] 2006.176.08:00:01.91#ibcon#*before write, iclass 14, count 0 2006.176.08:00:01.91#ibcon#enter sib2, iclass 14, count 0 2006.176.08:00:01.91#ibcon#flushed, iclass 14, count 0 2006.176.08:00:01.91#ibcon#about to write, iclass 14, count 0 2006.176.08:00:01.91#ibcon#wrote, iclass 14, count 0 2006.176.08:00:01.91#ibcon#about to read 3, iclass 14, count 0 2006.176.08:00:01.94#ibcon#read 3, iclass 14, count 0 2006.176.08:00:01.94#ibcon#about to read 4, iclass 14, count 0 2006.176.08:00:01.94#ibcon#read 4, iclass 14, count 0 2006.176.08:00:01.94#ibcon#about to read 5, iclass 14, count 0 2006.176.08:00:01.94#ibcon#read 5, iclass 14, count 0 2006.176.08:00:01.94#ibcon#about to read 6, iclass 14, count 0 2006.176.08:00:01.94#ibcon#read 6, iclass 14, count 0 2006.176.08:00:01.94#ibcon#end of sib2, iclass 14, count 0 2006.176.08:00:01.94#ibcon#*after write, iclass 14, count 0 2006.176.08:00:01.94#ibcon#*before return 0, iclass 14, count 0 2006.176.08:00:01.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:00:01.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:00:01.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:00:01.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:00:01.94$vc4f8/vblo=5,744.99 2006.176.08:00:01.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.08:00:01.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.08:00:01.94#ibcon#ireg 17 cls_cnt 0 2006.176.08:00:01.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:00:01.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:00:01.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:00:01.94#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:00:01.94#ibcon#first serial, iclass 16, count 0 2006.176.08:00:01.94#ibcon#enter sib2, iclass 16, count 0 2006.176.08:00:01.94#ibcon#flushed, iclass 16, count 0 2006.176.08:00:01.94#ibcon#about to write, iclass 16, count 0 2006.176.08:00:01.94#ibcon#wrote, iclass 16, count 0 2006.176.08:00:01.94#ibcon#about to read 3, iclass 16, count 0 2006.176.08:00:01.96#ibcon#read 3, iclass 16, count 0 2006.176.08:00:01.96#ibcon#about to read 4, iclass 16, count 0 2006.176.08:00:01.96#ibcon#read 4, iclass 16, count 0 2006.176.08:00:01.96#ibcon#about to read 5, iclass 16, count 0 2006.176.08:00:01.96#ibcon#read 5, iclass 16, count 0 2006.176.08:00:01.96#ibcon#about to read 6, iclass 16, count 0 2006.176.08:00:01.96#ibcon#read 6, iclass 16, count 0 2006.176.08:00:01.96#ibcon#end of sib2, iclass 16, count 0 2006.176.08:00:01.96#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:00:01.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:00:01.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:00:01.96#ibcon#*before write, iclass 16, count 0 2006.176.08:00:01.96#ibcon#enter sib2, iclass 16, count 0 2006.176.08:00:01.96#ibcon#flushed, iclass 16, count 0 2006.176.08:00:01.96#ibcon#about to write, iclass 16, count 0 2006.176.08:00:01.96#ibcon#wrote, iclass 16, count 0 2006.176.08:00:01.96#ibcon#about to read 3, iclass 16, count 0 2006.176.08:00:02.00#ibcon#read 3, iclass 16, count 0 2006.176.08:00:02.00#ibcon#about to read 4, iclass 16, count 0 2006.176.08:00:02.00#ibcon#read 4, iclass 16, count 0 2006.176.08:00:02.00#ibcon#about to read 5, iclass 16, count 0 2006.176.08:00:02.00#ibcon#read 5, iclass 16, count 0 2006.176.08:00:02.00#ibcon#about to read 6, iclass 16, count 0 2006.176.08:00:02.00#ibcon#read 6, iclass 16, count 0 2006.176.08:00:02.00#ibcon#end of sib2, iclass 16, count 0 2006.176.08:00:02.00#ibcon#*after write, iclass 16, count 0 2006.176.08:00:02.00#ibcon#*before return 0, iclass 16, count 0 2006.176.08:00:02.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:00:02.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:00:02.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:00:02.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:00:02.00$vc4f8/vb=5,4 2006.176.08:00:02.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.08:00:02.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.08:00:02.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:00:02.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:00:02.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:00:02.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:00:02.06#ibcon#enter wrdev, iclass 18, count 2 2006.176.08:00:02.06#ibcon#first serial, iclass 18, count 2 2006.176.08:00:02.06#ibcon#enter sib2, iclass 18, count 2 2006.176.08:00:02.06#ibcon#flushed, iclass 18, count 2 2006.176.08:00:02.06#ibcon#about to write, iclass 18, count 2 2006.176.08:00:02.06#ibcon#wrote, iclass 18, count 2 2006.176.08:00:02.06#ibcon#about to read 3, iclass 18, count 2 2006.176.08:00:02.08#ibcon#read 3, iclass 18, count 2 2006.176.08:00:02.08#ibcon#about to read 4, iclass 18, count 2 2006.176.08:00:02.08#ibcon#read 4, iclass 18, count 2 2006.176.08:00:02.08#ibcon#about to read 5, iclass 18, count 2 2006.176.08:00:02.08#ibcon#read 5, iclass 18, count 2 2006.176.08:00:02.08#ibcon#about to read 6, iclass 18, count 2 2006.176.08:00:02.08#ibcon#read 6, iclass 18, count 2 2006.176.08:00:02.08#ibcon#end of sib2, iclass 18, count 2 2006.176.08:00:02.08#ibcon#*mode == 0, iclass 18, count 2 2006.176.08:00:02.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.08:00:02.08#ibcon#[27=AT05-04\r\n] 2006.176.08:00:02.08#ibcon#*before write, iclass 18, count 2 2006.176.08:00:02.08#ibcon#enter sib2, iclass 18, count 2 2006.176.08:00:02.08#ibcon#flushed, iclass 18, count 2 2006.176.08:00:02.08#ibcon#about to write, iclass 18, count 2 2006.176.08:00:02.08#ibcon#wrote, iclass 18, count 2 2006.176.08:00:02.08#ibcon#about to read 3, iclass 18, count 2 2006.176.08:00:02.11#ibcon#read 3, iclass 18, count 2 2006.176.08:00:02.11#ibcon#about to read 4, iclass 18, count 2 2006.176.08:00:02.11#ibcon#read 4, iclass 18, count 2 2006.176.08:00:02.11#ibcon#about to read 5, iclass 18, count 2 2006.176.08:00:02.11#ibcon#read 5, iclass 18, count 2 2006.176.08:00:02.11#ibcon#about to read 6, iclass 18, count 2 2006.176.08:00:02.11#ibcon#read 6, iclass 18, count 2 2006.176.08:00:02.11#ibcon#end of sib2, iclass 18, count 2 2006.176.08:00:02.11#ibcon#*after write, iclass 18, count 2 2006.176.08:00:02.11#ibcon#*before return 0, iclass 18, count 2 2006.176.08:00:02.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:00:02.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:00:02.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.08:00:02.11#ibcon#ireg 7 cls_cnt 0 2006.176.08:00:02.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:00:02.23#abcon#<5=/05 3.2 5.5 23.85 921008.5\r\n> 2006.176.08:00:02.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:00:02.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:00:02.23#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:00:02.23#ibcon#first serial, iclass 18, count 0 2006.176.08:00:02.23#ibcon#enter sib2, iclass 18, count 0 2006.176.08:00:02.23#ibcon#flushed, iclass 18, count 0 2006.176.08:00:02.23#ibcon#about to write, iclass 18, count 0 2006.176.08:00:02.23#ibcon#wrote, iclass 18, count 0 2006.176.08:00:02.23#ibcon#about to read 3, iclass 18, count 0 2006.176.08:00:02.25#ibcon#read 3, iclass 18, count 0 2006.176.08:00:02.25#ibcon#about to read 4, iclass 18, count 0 2006.176.08:00:02.25#ibcon#read 4, iclass 18, count 0 2006.176.08:00:02.25#ibcon#about to read 5, iclass 18, count 0 2006.176.08:00:02.25#ibcon#read 5, iclass 18, count 0 2006.176.08:00:02.25#ibcon#about to read 6, iclass 18, count 0 2006.176.08:00:02.25#ibcon#read 6, iclass 18, count 0 2006.176.08:00:02.25#ibcon#end of sib2, iclass 18, count 0 2006.176.08:00:02.25#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:00:02.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:00:02.25#ibcon#[27=USB\r\n] 2006.176.08:00:02.25#ibcon#*before write, iclass 18, count 0 2006.176.08:00:02.25#ibcon#enter sib2, iclass 18, count 0 2006.176.08:00:02.25#ibcon#flushed, iclass 18, count 0 2006.176.08:00:02.25#ibcon#about to write, iclass 18, count 0 2006.176.08:00:02.25#ibcon#wrote, iclass 18, count 0 2006.176.08:00:02.25#ibcon#about to read 3, iclass 18, count 0 2006.176.08:00:02.25#abcon#{5=INTERFACE CLEAR} 2006.176.08:00:02.28#ibcon#read 3, iclass 18, count 0 2006.176.08:00:02.28#ibcon#about to read 4, iclass 18, count 0 2006.176.08:00:02.28#ibcon#read 4, iclass 18, count 0 2006.176.08:00:02.28#ibcon#about to read 5, iclass 18, count 0 2006.176.08:00:02.28#ibcon#read 5, iclass 18, count 0 2006.176.08:00:02.28#ibcon#about to read 6, iclass 18, count 0 2006.176.08:00:02.28#ibcon#read 6, iclass 18, count 0 2006.176.08:00:02.28#ibcon#end of sib2, iclass 18, count 0 2006.176.08:00:02.28#ibcon#*after write, iclass 18, count 0 2006.176.08:00:02.28#ibcon#*before return 0, iclass 18, count 0 2006.176.08:00:02.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:00:02.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:00:02.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:00:02.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:00:02.28$vc4f8/vblo=6,752.99 2006.176.08:00:02.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.08:00:02.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.08:00:02.28#ibcon#ireg 17 cls_cnt 0 2006.176.08:00:02.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:00:02.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:00:02.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:00:02.28#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:00:02.28#ibcon#first serial, iclass 23, count 0 2006.176.08:00:02.28#ibcon#enter sib2, iclass 23, count 0 2006.176.08:00:02.28#ibcon#flushed, iclass 23, count 0 2006.176.08:00:02.28#ibcon#about to write, iclass 23, count 0 2006.176.08:00:02.28#ibcon#wrote, iclass 23, count 0 2006.176.08:00:02.28#ibcon#about to read 3, iclass 23, count 0 2006.176.08:00:02.30#ibcon#read 3, iclass 23, count 0 2006.176.08:00:02.30#ibcon#about to read 4, iclass 23, count 0 2006.176.08:00:02.30#ibcon#read 4, iclass 23, count 0 2006.176.08:00:02.30#ibcon#about to read 5, iclass 23, count 0 2006.176.08:00:02.30#ibcon#read 5, iclass 23, count 0 2006.176.08:00:02.30#ibcon#about to read 6, iclass 23, count 0 2006.176.08:00:02.30#ibcon#read 6, iclass 23, count 0 2006.176.08:00:02.30#ibcon#end of sib2, iclass 23, count 0 2006.176.08:00:02.30#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:00:02.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:00:02.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:00:02.30#ibcon#*before write, iclass 23, count 0 2006.176.08:00:02.30#ibcon#enter sib2, iclass 23, count 0 2006.176.08:00:02.30#ibcon#flushed, iclass 23, count 0 2006.176.08:00:02.30#ibcon#about to write, iclass 23, count 0 2006.176.08:00:02.30#ibcon#wrote, iclass 23, count 0 2006.176.08:00:02.30#ibcon#about to read 3, iclass 23, count 0 2006.176.08:00:02.31#abcon#[5=S1D000X0/0*\r\n] 2006.176.08:00:02.34#ibcon#read 3, iclass 23, count 0 2006.176.08:00:02.34#ibcon#about to read 4, iclass 23, count 0 2006.176.08:00:02.34#ibcon#read 4, iclass 23, count 0 2006.176.08:00:02.34#ibcon#about to read 5, iclass 23, count 0 2006.176.08:00:02.34#ibcon#read 5, iclass 23, count 0 2006.176.08:00:02.34#ibcon#about to read 6, iclass 23, count 0 2006.176.08:00:02.34#ibcon#read 6, iclass 23, count 0 2006.176.08:00:02.34#ibcon#end of sib2, iclass 23, count 0 2006.176.08:00:02.34#ibcon#*after write, iclass 23, count 0 2006.176.08:00:02.34#ibcon#*before return 0, iclass 23, count 0 2006.176.08:00:02.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:00:02.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:00:02.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:00:02.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:00:02.34$vc4f8/vb=6,4 2006.176.08:00:02.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.08:00:02.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.08:00:02.34#ibcon#ireg 11 cls_cnt 2 2006.176.08:00:02.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:00:02.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:00:02.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:00:02.41#ibcon#enter wrdev, iclass 26, count 2 2006.176.08:00:02.41#ibcon#first serial, iclass 26, count 2 2006.176.08:00:02.41#ibcon#enter sib2, iclass 26, count 2 2006.176.08:00:02.41#ibcon#flushed, iclass 26, count 2 2006.176.08:00:02.41#ibcon#about to write, iclass 26, count 2 2006.176.08:00:02.41#ibcon#wrote, iclass 26, count 2 2006.176.08:00:02.41#ibcon#about to read 3, iclass 26, count 2 2006.176.08:00:02.42#ibcon#read 3, iclass 26, count 2 2006.176.08:00:02.42#ibcon#about to read 4, iclass 26, count 2 2006.176.08:00:02.42#ibcon#read 4, iclass 26, count 2 2006.176.08:00:02.42#ibcon#about to read 5, iclass 26, count 2 2006.176.08:00:02.42#ibcon#read 5, iclass 26, count 2 2006.176.08:00:02.42#ibcon#about to read 6, iclass 26, count 2 2006.176.08:00:02.42#ibcon#read 6, iclass 26, count 2 2006.176.08:00:02.42#ibcon#end of sib2, iclass 26, count 2 2006.176.08:00:02.42#ibcon#*mode == 0, iclass 26, count 2 2006.176.08:00:02.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.08:00:02.42#ibcon#[27=AT06-04\r\n] 2006.176.08:00:02.42#ibcon#*before write, iclass 26, count 2 2006.176.08:00:02.42#ibcon#enter sib2, iclass 26, count 2 2006.176.08:00:02.42#ibcon#flushed, iclass 26, count 2 2006.176.08:00:02.42#ibcon#about to write, iclass 26, count 2 2006.176.08:00:02.42#ibcon#wrote, iclass 26, count 2 2006.176.08:00:02.42#ibcon#about to read 3, iclass 26, count 2 2006.176.08:00:02.45#ibcon#read 3, iclass 26, count 2 2006.176.08:00:02.45#ibcon#about to read 4, iclass 26, count 2 2006.176.08:00:02.45#ibcon#read 4, iclass 26, count 2 2006.176.08:00:02.45#ibcon#about to read 5, iclass 26, count 2 2006.176.08:00:02.45#ibcon#read 5, iclass 26, count 2 2006.176.08:00:02.45#ibcon#about to read 6, iclass 26, count 2 2006.176.08:00:02.45#ibcon#read 6, iclass 26, count 2 2006.176.08:00:02.45#ibcon#end of sib2, iclass 26, count 2 2006.176.08:00:02.45#ibcon#*after write, iclass 26, count 2 2006.176.08:00:02.45#ibcon#*before return 0, iclass 26, count 2 2006.176.08:00:02.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:00:02.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:00:02.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.08:00:02.45#ibcon#ireg 7 cls_cnt 0 2006.176.08:00:02.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:00:02.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:00:02.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:00:02.57#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:00:02.57#ibcon#first serial, iclass 26, count 0 2006.176.08:00:02.57#ibcon#enter sib2, iclass 26, count 0 2006.176.08:00:02.57#ibcon#flushed, iclass 26, count 0 2006.176.08:00:02.57#ibcon#about to write, iclass 26, count 0 2006.176.08:00:02.57#ibcon#wrote, iclass 26, count 0 2006.176.08:00:02.57#ibcon#about to read 3, iclass 26, count 0 2006.176.08:00:02.59#ibcon#read 3, iclass 26, count 0 2006.176.08:00:02.59#ibcon#about to read 4, iclass 26, count 0 2006.176.08:00:02.59#ibcon#read 4, iclass 26, count 0 2006.176.08:00:02.59#ibcon#about to read 5, iclass 26, count 0 2006.176.08:00:02.59#ibcon#read 5, iclass 26, count 0 2006.176.08:00:02.59#ibcon#about to read 6, iclass 26, count 0 2006.176.08:00:02.59#ibcon#read 6, iclass 26, count 0 2006.176.08:00:02.59#ibcon#end of sib2, iclass 26, count 0 2006.176.08:00:02.59#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:00:02.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:00:02.59#ibcon#[27=USB\r\n] 2006.176.08:00:02.59#ibcon#*before write, iclass 26, count 0 2006.176.08:00:02.59#ibcon#enter sib2, iclass 26, count 0 2006.176.08:00:02.59#ibcon#flushed, iclass 26, count 0 2006.176.08:00:02.59#ibcon#about to write, iclass 26, count 0 2006.176.08:00:02.59#ibcon#wrote, iclass 26, count 0 2006.176.08:00:02.59#ibcon#about to read 3, iclass 26, count 0 2006.176.08:00:02.62#ibcon#read 3, iclass 26, count 0 2006.176.08:00:02.62#ibcon#about to read 4, iclass 26, count 0 2006.176.08:00:02.62#ibcon#read 4, iclass 26, count 0 2006.176.08:00:02.62#ibcon#about to read 5, iclass 26, count 0 2006.176.08:00:02.62#ibcon#read 5, iclass 26, count 0 2006.176.08:00:02.62#ibcon#about to read 6, iclass 26, count 0 2006.176.08:00:02.62#ibcon#read 6, iclass 26, count 0 2006.176.08:00:02.62#ibcon#end of sib2, iclass 26, count 0 2006.176.08:00:02.62#ibcon#*after write, iclass 26, count 0 2006.176.08:00:02.62#ibcon#*before return 0, iclass 26, count 0 2006.176.08:00:02.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:00:02.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:00:02.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:00:02.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:00:02.62$vc4f8/vabw=wide 2006.176.08:00:02.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.08:00:02.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.08:00:02.62#ibcon#ireg 8 cls_cnt 0 2006.176.08:00:02.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:00:02.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:00:02.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:00:02.62#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:00:02.62#ibcon#first serial, iclass 28, count 0 2006.176.08:00:02.62#ibcon#enter sib2, iclass 28, count 0 2006.176.08:00:02.62#ibcon#flushed, iclass 28, count 0 2006.176.08:00:02.62#ibcon#about to write, iclass 28, count 0 2006.176.08:00:02.62#ibcon#wrote, iclass 28, count 0 2006.176.08:00:02.62#ibcon#about to read 3, iclass 28, count 0 2006.176.08:00:02.64#ibcon#read 3, iclass 28, count 0 2006.176.08:00:02.64#ibcon#about to read 4, iclass 28, count 0 2006.176.08:00:02.64#ibcon#read 4, iclass 28, count 0 2006.176.08:00:02.64#ibcon#about to read 5, iclass 28, count 0 2006.176.08:00:02.64#ibcon#read 5, iclass 28, count 0 2006.176.08:00:02.64#ibcon#about to read 6, iclass 28, count 0 2006.176.08:00:02.64#ibcon#read 6, iclass 28, count 0 2006.176.08:00:02.64#ibcon#end of sib2, iclass 28, count 0 2006.176.08:00:02.64#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:00:02.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:00:02.64#ibcon#[25=BW32\r\n] 2006.176.08:00:02.64#ibcon#*before write, iclass 28, count 0 2006.176.08:00:02.64#ibcon#enter sib2, iclass 28, count 0 2006.176.08:00:02.64#ibcon#flushed, iclass 28, count 0 2006.176.08:00:02.64#ibcon#about to write, iclass 28, count 0 2006.176.08:00:02.64#ibcon#wrote, iclass 28, count 0 2006.176.08:00:02.64#ibcon#about to read 3, iclass 28, count 0 2006.176.08:00:02.67#ibcon#read 3, iclass 28, count 0 2006.176.08:00:02.67#ibcon#about to read 4, iclass 28, count 0 2006.176.08:00:02.67#ibcon#read 4, iclass 28, count 0 2006.176.08:00:02.67#ibcon#about to read 5, iclass 28, count 0 2006.176.08:00:02.67#ibcon#read 5, iclass 28, count 0 2006.176.08:00:02.67#ibcon#about to read 6, iclass 28, count 0 2006.176.08:00:02.67#ibcon#read 6, iclass 28, count 0 2006.176.08:00:02.67#ibcon#end of sib2, iclass 28, count 0 2006.176.08:00:02.67#ibcon#*after write, iclass 28, count 0 2006.176.08:00:02.67#ibcon#*before return 0, iclass 28, count 0 2006.176.08:00:02.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:00:02.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:00:02.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:00:02.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:00:02.67$vc4f8/vbbw=wide 2006.176.08:00:02.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.08:00:02.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.08:00:02.67#ibcon#ireg 8 cls_cnt 0 2006.176.08:00:02.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:00:02.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:00:02.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:00:02.74#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:00:02.74#ibcon#first serial, iclass 30, count 0 2006.176.08:00:02.74#ibcon#enter sib2, iclass 30, count 0 2006.176.08:00:02.74#ibcon#flushed, iclass 30, count 0 2006.176.08:00:02.74#ibcon#about to write, iclass 30, count 0 2006.176.08:00:02.74#ibcon#wrote, iclass 30, count 0 2006.176.08:00:02.74#ibcon#about to read 3, iclass 30, count 0 2006.176.08:00:02.76#ibcon#read 3, iclass 30, count 0 2006.176.08:00:02.76#ibcon#about to read 4, iclass 30, count 0 2006.176.08:00:02.76#ibcon#read 4, iclass 30, count 0 2006.176.08:00:02.76#ibcon#about to read 5, iclass 30, count 0 2006.176.08:00:02.76#ibcon#read 5, iclass 30, count 0 2006.176.08:00:02.76#ibcon#about to read 6, iclass 30, count 0 2006.176.08:00:02.76#ibcon#read 6, iclass 30, count 0 2006.176.08:00:02.76#ibcon#end of sib2, iclass 30, count 0 2006.176.08:00:02.76#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:00:02.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:00:02.76#ibcon#[27=BW32\r\n] 2006.176.08:00:02.76#ibcon#*before write, iclass 30, count 0 2006.176.08:00:02.76#ibcon#enter sib2, iclass 30, count 0 2006.176.08:00:02.76#ibcon#flushed, iclass 30, count 0 2006.176.08:00:02.76#ibcon#about to write, iclass 30, count 0 2006.176.08:00:02.76#ibcon#wrote, iclass 30, count 0 2006.176.08:00:02.76#ibcon#about to read 3, iclass 30, count 0 2006.176.08:00:02.79#ibcon#read 3, iclass 30, count 0 2006.176.08:00:02.79#ibcon#about to read 4, iclass 30, count 0 2006.176.08:00:02.79#ibcon#read 4, iclass 30, count 0 2006.176.08:00:02.79#ibcon#about to read 5, iclass 30, count 0 2006.176.08:00:02.79#ibcon#read 5, iclass 30, count 0 2006.176.08:00:02.79#ibcon#about to read 6, iclass 30, count 0 2006.176.08:00:02.79#ibcon#read 6, iclass 30, count 0 2006.176.08:00:02.79#ibcon#end of sib2, iclass 30, count 0 2006.176.08:00:02.79#ibcon#*after write, iclass 30, count 0 2006.176.08:00:02.79#ibcon#*before return 0, iclass 30, count 0 2006.176.08:00:02.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:00:02.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:00:02.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:00:02.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:00:02.79$4f8m12a/ifd4f 2006.176.08:00:02.79$ifd4f/lo= 2006.176.08:00:02.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:00:02.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:00:02.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:00:02.79$ifd4f/patch= 2006.176.08:00:02.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:00:02.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:00:02.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:00:02.80$4f8m12a/"form=m,16.000,1:2 2006.176.08:00:02.80$4f8m12a/"tpicd 2006.176.08:00:02.80$4f8m12a/echo=off 2006.176.08:00:02.80$4f8m12a/xlog=off 2006.176.08:00:02.80:!2006.176.08:01:00 2006.176.08:00:40.14#trakl#Source acquired 2006.176.08:00:41.14#flagr#flagr/antenna,acquired 2006.176.08:01:00.01:preob 2006.176.08:01:01.14/onsource/TRACKING 2006.176.08:01:01.14:!2006.176.08:01:10 2006.176.08:01:10.00:data_valid=on 2006.176.08:01:10.00:midob 2006.176.08:01:10.14/onsource/TRACKING 2006.176.08:01:10.14/wx/23.85,1008.5,92 2006.176.08:01:10.20/cable/+6.4964E-03 2006.176.08:01:11.29/va/01,08,usb,yes,29,31 2006.176.08:01:11.29/va/02,07,usb,yes,29,31 2006.176.08:01:11.29/va/03,06,usb,yes,31,31 2006.176.08:01:11.29/va/04,07,usb,yes,30,32 2006.176.08:01:11.29/va/05,07,usb,yes,31,33 2006.176.08:01:11.29/va/06,06,usb,yes,30,30 2006.176.08:01:11.29/va/07,06,usb,yes,31,31 2006.176.08:01:11.29/va/08,06,usb,yes,33,32 2006.176.08:01:11.52/valo/01,532.99,yes,locked 2006.176.08:01:11.52/valo/02,572.99,yes,locked 2006.176.08:01:11.52/valo/03,672.99,yes,locked 2006.176.08:01:11.52/valo/04,832.99,yes,locked 2006.176.08:01:11.52/valo/05,652.99,yes,locked 2006.176.08:01:11.52/valo/06,772.99,yes,locked 2006.176.08:01:11.52/valo/07,832.99,yes,locked 2006.176.08:01:11.52/valo/08,852.99,yes,locked 2006.176.08:01:12.61/vb/01,04,usb,yes,29,28 2006.176.08:01:12.61/vb/02,04,usb,yes,31,32 2006.176.08:01:12.61/vb/03,04,usb,yes,27,31 2006.176.08:01:12.61/vb/04,04,usb,yes,28,28 2006.176.08:01:12.61/vb/05,04,usb,yes,27,30 2006.176.08:01:12.61/vb/06,04,usb,yes,28,30 2006.176.08:01:12.61/vb/07,04,usb,yes,29,29 2006.176.08:01:12.61/vb/08,04,usb,yes,27,30 2006.176.08:01:12.85/vblo/01,632.99,yes,locked 2006.176.08:01:12.85/vblo/02,640.99,yes,locked 2006.176.08:01:12.85/vblo/03,656.99,yes,locked 2006.176.08:01:12.85/vblo/04,712.99,yes,locked 2006.176.08:01:12.85/vblo/05,744.99,yes,locked 2006.176.08:01:12.85/vblo/06,752.99,yes,locked 2006.176.08:01:12.85/vblo/07,734.99,yes,locked 2006.176.08:01:12.85/vblo/08,744.99,yes,locked 2006.176.08:01:13.00/vabw/8 2006.176.08:01:13.15/vbbw/8 2006.176.08:01:13.24/xfe/off,on,14.5 2006.176.08:01:13.61/ifatt/23,28,28,28 2006.176.08:01:14.07/fmout-gps/S +3.73E-07 2006.176.08:01:14.15:!2006.176.08:02:10 2006.176.08:02:10.00:data_valid=off 2006.176.08:02:10.01:postob 2006.176.08:02:10.21/cable/+6.4947E-03 2006.176.08:02:10.22/wx/23.85,1008.6,92 2006.176.08:02:11.07/fmout-gps/S +3.73E-07 2006.176.08:02:11.08:scan_name=176-0803,k06176,60 2006.176.08:02:11.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.176.08:02:12.14#flagr#flagr/antenna,new-source 2006.176.08:02:12.15:checkk5 2006.176.08:02:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:02:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:02:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:02:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:02:14.03/chk_obsdata//k5ts1/T1760801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:02:14.40/chk_obsdata//k5ts2/T1760801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:02:14.77/chk_obsdata//k5ts3/T1760801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:02:15.14/chk_obsdata//k5ts4/T1760801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:02:15.85/k5log//k5ts1_log_newline 2006.176.08:02:16.53/k5log//k5ts2_log_newline 2006.176.08:02:17.22/k5log//k5ts3_log_newline 2006.176.08:02:17.91/k5log//k5ts4_log_newline 2006.176.08:02:17.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:02:17.94:4f8m12a=2 2006.176.08:02:17.94$4f8m12a/echo=on 2006.176.08:02:17.94$4f8m12a/pcalon 2006.176.08:02:17.94$pcalon/"no phase cal control is implemented here 2006.176.08:02:17.94$4f8m12a/"tpicd=stop 2006.176.08:02:17.94$4f8m12a/vc4f8 2006.176.08:02:17.94$vc4f8/valo=1,532.99 2006.176.08:02:17.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.08:02:17.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.08:02:17.94#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:17.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:17.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:17.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:17.94#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:02:17.94#ibcon#first serial, iclass 13, count 0 2006.176.08:02:17.94#ibcon#enter sib2, iclass 13, count 0 2006.176.08:02:17.94#ibcon#flushed, iclass 13, count 0 2006.176.08:02:17.94#ibcon#about to write, iclass 13, count 0 2006.176.08:02:17.94#ibcon#wrote, iclass 13, count 0 2006.176.08:02:17.94#ibcon#about to read 3, iclass 13, count 0 2006.176.08:02:17.95#ibcon#read 3, iclass 13, count 0 2006.176.08:02:17.95#ibcon#about to read 4, iclass 13, count 0 2006.176.08:02:17.95#ibcon#read 4, iclass 13, count 0 2006.176.08:02:17.95#ibcon#about to read 5, iclass 13, count 0 2006.176.08:02:17.95#ibcon#read 5, iclass 13, count 0 2006.176.08:02:17.95#ibcon#about to read 6, iclass 13, count 0 2006.176.08:02:17.95#ibcon#read 6, iclass 13, count 0 2006.176.08:02:17.95#ibcon#end of sib2, iclass 13, count 0 2006.176.08:02:17.95#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:02:17.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:02:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:02:17.95#ibcon#*before write, iclass 13, count 0 2006.176.08:02:17.95#ibcon#enter sib2, iclass 13, count 0 2006.176.08:02:17.95#ibcon#flushed, iclass 13, count 0 2006.176.08:02:17.95#ibcon#about to write, iclass 13, count 0 2006.176.08:02:17.95#ibcon#wrote, iclass 13, count 0 2006.176.08:02:17.95#ibcon#about to read 3, iclass 13, count 0 2006.176.08:02:18.00#ibcon#read 3, iclass 13, count 0 2006.176.08:02:18.00#ibcon#about to read 4, iclass 13, count 0 2006.176.08:02:18.00#ibcon#read 4, iclass 13, count 0 2006.176.08:02:18.00#ibcon#about to read 5, iclass 13, count 0 2006.176.08:02:18.00#ibcon#read 5, iclass 13, count 0 2006.176.08:02:18.00#ibcon#about to read 6, iclass 13, count 0 2006.176.08:02:18.00#ibcon#read 6, iclass 13, count 0 2006.176.08:02:18.00#ibcon#end of sib2, iclass 13, count 0 2006.176.08:02:18.00#ibcon#*after write, iclass 13, count 0 2006.176.08:02:18.00#ibcon#*before return 0, iclass 13, count 0 2006.176.08:02:18.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:18.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:18.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:02:18.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:02:18.00$vc4f8/va=1,8 2006.176.08:02:18.00#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.176.08:02:18.00#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.176.08:02:18.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:18.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:18.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:18.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:18.00#ibcon#enter wrdev, iclass 15, count 2 2006.176.08:02:18.00#ibcon#first serial, iclass 15, count 2 2006.176.08:02:18.00#ibcon#enter sib2, iclass 15, count 2 2006.176.08:02:18.00#ibcon#flushed, iclass 15, count 2 2006.176.08:02:18.00#ibcon#about to write, iclass 15, count 2 2006.176.08:02:18.00#ibcon#wrote, iclass 15, count 2 2006.176.08:02:18.00#ibcon#about to read 3, iclass 15, count 2 2006.176.08:02:18.02#ibcon#read 3, iclass 15, count 2 2006.176.08:02:18.02#ibcon#about to read 4, iclass 15, count 2 2006.176.08:02:18.02#ibcon#read 4, iclass 15, count 2 2006.176.08:02:18.02#ibcon#about to read 5, iclass 15, count 2 2006.176.08:02:18.02#ibcon#read 5, iclass 15, count 2 2006.176.08:02:18.02#ibcon#about to read 6, iclass 15, count 2 2006.176.08:02:18.02#ibcon#read 6, iclass 15, count 2 2006.176.08:02:18.02#ibcon#end of sib2, iclass 15, count 2 2006.176.08:02:18.02#ibcon#*mode == 0, iclass 15, count 2 2006.176.08:02:18.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.176.08:02:18.02#ibcon#[25=AT01-08\r\n] 2006.176.08:02:18.02#ibcon#*before write, iclass 15, count 2 2006.176.08:02:18.02#ibcon#enter sib2, iclass 15, count 2 2006.176.08:02:18.02#ibcon#flushed, iclass 15, count 2 2006.176.08:02:18.02#ibcon#about to write, iclass 15, count 2 2006.176.08:02:18.02#ibcon#wrote, iclass 15, count 2 2006.176.08:02:18.02#ibcon#about to read 3, iclass 15, count 2 2006.176.08:02:18.05#ibcon#read 3, iclass 15, count 2 2006.176.08:02:18.05#ibcon#about to read 4, iclass 15, count 2 2006.176.08:02:18.05#ibcon#read 4, iclass 15, count 2 2006.176.08:02:18.05#ibcon#about to read 5, iclass 15, count 2 2006.176.08:02:18.05#ibcon#read 5, iclass 15, count 2 2006.176.08:02:18.05#ibcon#about to read 6, iclass 15, count 2 2006.176.08:02:18.05#ibcon#read 6, iclass 15, count 2 2006.176.08:02:18.05#ibcon#end of sib2, iclass 15, count 2 2006.176.08:02:18.05#ibcon#*after write, iclass 15, count 2 2006.176.08:02:18.05#ibcon#*before return 0, iclass 15, count 2 2006.176.08:02:18.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:18.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:18.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.176.08:02:18.05#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:18.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:18.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:18.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:18.17#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:02:18.17#ibcon#first serial, iclass 15, count 0 2006.176.08:02:18.17#ibcon#enter sib2, iclass 15, count 0 2006.176.08:02:18.17#ibcon#flushed, iclass 15, count 0 2006.176.08:02:18.17#ibcon#about to write, iclass 15, count 0 2006.176.08:02:18.17#ibcon#wrote, iclass 15, count 0 2006.176.08:02:18.17#ibcon#about to read 3, iclass 15, count 0 2006.176.08:02:18.19#ibcon#read 3, iclass 15, count 0 2006.176.08:02:18.19#ibcon#about to read 4, iclass 15, count 0 2006.176.08:02:18.19#ibcon#read 4, iclass 15, count 0 2006.176.08:02:18.19#ibcon#about to read 5, iclass 15, count 0 2006.176.08:02:18.19#ibcon#read 5, iclass 15, count 0 2006.176.08:02:18.19#ibcon#about to read 6, iclass 15, count 0 2006.176.08:02:18.19#ibcon#read 6, iclass 15, count 0 2006.176.08:02:18.19#ibcon#end of sib2, iclass 15, count 0 2006.176.08:02:18.19#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:02:18.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:02:18.19#ibcon#[25=USB\r\n] 2006.176.08:02:18.19#ibcon#*before write, iclass 15, count 0 2006.176.08:02:18.19#ibcon#enter sib2, iclass 15, count 0 2006.176.08:02:18.19#ibcon#flushed, iclass 15, count 0 2006.176.08:02:18.19#ibcon#about to write, iclass 15, count 0 2006.176.08:02:18.19#ibcon#wrote, iclass 15, count 0 2006.176.08:02:18.19#ibcon#about to read 3, iclass 15, count 0 2006.176.08:02:18.22#ibcon#read 3, iclass 15, count 0 2006.176.08:02:18.22#ibcon#about to read 4, iclass 15, count 0 2006.176.08:02:18.22#ibcon#read 4, iclass 15, count 0 2006.176.08:02:18.22#ibcon#about to read 5, iclass 15, count 0 2006.176.08:02:18.22#ibcon#read 5, iclass 15, count 0 2006.176.08:02:18.22#ibcon#about to read 6, iclass 15, count 0 2006.176.08:02:18.22#ibcon#read 6, iclass 15, count 0 2006.176.08:02:18.22#ibcon#end of sib2, iclass 15, count 0 2006.176.08:02:18.22#ibcon#*after write, iclass 15, count 0 2006.176.08:02:18.22#ibcon#*before return 0, iclass 15, count 0 2006.176.08:02:18.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:18.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:18.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:02:18.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:02:18.22$vc4f8/valo=2,572.99 2006.176.08:02:18.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.08:02:18.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.08:02:18.22#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:18.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:18.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:18.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:18.22#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:02:18.22#ibcon#first serial, iclass 17, count 0 2006.176.08:02:18.22#ibcon#enter sib2, iclass 17, count 0 2006.176.08:02:18.22#ibcon#flushed, iclass 17, count 0 2006.176.08:02:18.22#ibcon#about to write, iclass 17, count 0 2006.176.08:02:18.22#ibcon#wrote, iclass 17, count 0 2006.176.08:02:18.22#ibcon#about to read 3, iclass 17, count 0 2006.176.08:02:18.24#ibcon#read 3, iclass 17, count 0 2006.176.08:02:18.24#ibcon#about to read 4, iclass 17, count 0 2006.176.08:02:18.24#ibcon#read 4, iclass 17, count 0 2006.176.08:02:18.24#ibcon#about to read 5, iclass 17, count 0 2006.176.08:02:18.24#ibcon#read 5, iclass 17, count 0 2006.176.08:02:18.24#ibcon#about to read 6, iclass 17, count 0 2006.176.08:02:18.24#ibcon#read 6, iclass 17, count 0 2006.176.08:02:18.24#ibcon#end of sib2, iclass 17, count 0 2006.176.08:02:18.24#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:02:18.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:02:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:02:18.24#ibcon#*before write, iclass 17, count 0 2006.176.08:02:18.24#ibcon#enter sib2, iclass 17, count 0 2006.176.08:02:18.24#ibcon#flushed, iclass 17, count 0 2006.176.08:02:18.24#ibcon#about to write, iclass 17, count 0 2006.176.08:02:18.24#ibcon#wrote, iclass 17, count 0 2006.176.08:02:18.24#ibcon#about to read 3, iclass 17, count 0 2006.176.08:02:18.28#ibcon#read 3, iclass 17, count 0 2006.176.08:02:18.28#ibcon#about to read 4, iclass 17, count 0 2006.176.08:02:18.28#ibcon#read 4, iclass 17, count 0 2006.176.08:02:18.28#ibcon#about to read 5, iclass 17, count 0 2006.176.08:02:18.28#ibcon#read 5, iclass 17, count 0 2006.176.08:02:18.28#ibcon#about to read 6, iclass 17, count 0 2006.176.08:02:18.28#ibcon#read 6, iclass 17, count 0 2006.176.08:02:18.28#ibcon#end of sib2, iclass 17, count 0 2006.176.08:02:18.28#ibcon#*after write, iclass 17, count 0 2006.176.08:02:18.28#ibcon#*before return 0, iclass 17, count 0 2006.176.08:02:18.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:18.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:18.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:02:18.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:02:18.28$vc4f8/va=2,7 2006.176.08:02:18.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.176.08:02:18.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.176.08:02:18.28#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:18.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:18.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:18.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:18.34#ibcon#enter wrdev, iclass 19, count 2 2006.176.08:02:18.34#ibcon#first serial, iclass 19, count 2 2006.176.08:02:18.34#ibcon#enter sib2, iclass 19, count 2 2006.176.08:02:18.34#ibcon#flushed, iclass 19, count 2 2006.176.08:02:18.34#ibcon#about to write, iclass 19, count 2 2006.176.08:02:18.34#ibcon#wrote, iclass 19, count 2 2006.176.08:02:18.34#ibcon#about to read 3, iclass 19, count 2 2006.176.08:02:18.37#ibcon#read 3, iclass 19, count 2 2006.176.08:02:18.37#ibcon#about to read 4, iclass 19, count 2 2006.176.08:02:18.37#ibcon#read 4, iclass 19, count 2 2006.176.08:02:18.37#ibcon#about to read 5, iclass 19, count 2 2006.176.08:02:18.37#ibcon#read 5, iclass 19, count 2 2006.176.08:02:18.37#ibcon#about to read 6, iclass 19, count 2 2006.176.08:02:18.37#ibcon#read 6, iclass 19, count 2 2006.176.08:02:18.37#ibcon#end of sib2, iclass 19, count 2 2006.176.08:02:18.37#ibcon#*mode == 0, iclass 19, count 2 2006.176.08:02:18.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.176.08:02:18.37#ibcon#[25=AT02-07\r\n] 2006.176.08:02:18.37#ibcon#*before write, iclass 19, count 2 2006.176.08:02:18.37#ibcon#enter sib2, iclass 19, count 2 2006.176.08:02:18.37#ibcon#flushed, iclass 19, count 2 2006.176.08:02:18.37#ibcon#about to write, iclass 19, count 2 2006.176.08:02:18.37#ibcon#wrote, iclass 19, count 2 2006.176.08:02:18.37#ibcon#about to read 3, iclass 19, count 2 2006.176.08:02:18.39#ibcon#read 3, iclass 19, count 2 2006.176.08:02:18.39#ibcon#about to read 4, iclass 19, count 2 2006.176.08:02:18.39#ibcon#read 4, iclass 19, count 2 2006.176.08:02:18.39#ibcon#about to read 5, iclass 19, count 2 2006.176.08:02:18.39#ibcon#read 5, iclass 19, count 2 2006.176.08:02:18.39#ibcon#about to read 6, iclass 19, count 2 2006.176.08:02:18.39#ibcon#read 6, iclass 19, count 2 2006.176.08:02:18.39#ibcon#end of sib2, iclass 19, count 2 2006.176.08:02:18.39#ibcon#*after write, iclass 19, count 2 2006.176.08:02:18.39#ibcon#*before return 0, iclass 19, count 2 2006.176.08:02:18.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:18.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:18.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.176.08:02:18.39#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:18.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:18.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:18.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:18.51#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:02:18.51#ibcon#first serial, iclass 19, count 0 2006.176.08:02:18.51#ibcon#enter sib2, iclass 19, count 0 2006.176.08:02:18.51#ibcon#flushed, iclass 19, count 0 2006.176.08:02:18.51#ibcon#about to write, iclass 19, count 0 2006.176.08:02:18.51#ibcon#wrote, iclass 19, count 0 2006.176.08:02:18.51#ibcon#about to read 3, iclass 19, count 0 2006.176.08:02:18.53#ibcon#read 3, iclass 19, count 0 2006.176.08:02:18.53#ibcon#about to read 4, iclass 19, count 0 2006.176.08:02:18.53#ibcon#read 4, iclass 19, count 0 2006.176.08:02:18.53#ibcon#about to read 5, iclass 19, count 0 2006.176.08:02:18.53#ibcon#read 5, iclass 19, count 0 2006.176.08:02:18.53#ibcon#about to read 6, iclass 19, count 0 2006.176.08:02:18.53#ibcon#read 6, iclass 19, count 0 2006.176.08:02:18.53#ibcon#end of sib2, iclass 19, count 0 2006.176.08:02:18.53#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:02:18.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:02:18.53#ibcon#[25=USB\r\n] 2006.176.08:02:18.53#ibcon#*before write, iclass 19, count 0 2006.176.08:02:18.53#ibcon#enter sib2, iclass 19, count 0 2006.176.08:02:18.53#ibcon#flushed, iclass 19, count 0 2006.176.08:02:18.53#ibcon#about to write, iclass 19, count 0 2006.176.08:02:18.53#ibcon#wrote, iclass 19, count 0 2006.176.08:02:18.53#ibcon#about to read 3, iclass 19, count 0 2006.176.08:02:18.57#ibcon#read 3, iclass 19, count 0 2006.176.08:02:18.57#ibcon#about to read 4, iclass 19, count 0 2006.176.08:02:18.57#ibcon#read 4, iclass 19, count 0 2006.176.08:02:18.57#ibcon#about to read 5, iclass 19, count 0 2006.176.08:02:18.57#ibcon#read 5, iclass 19, count 0 2006.176.08:02:18.57#ibcon#about to read 6, iclass 19, count 0 2006.176.08:02:18.57#ibcon#read 6, iclass 19, count 0 2006.176.08:02:18.57#ibcon#end of sib2, iclass 19, count 0 2006.176.08:02:18.57#ibcon#*after write, iclass 19, count 0 2006.176.08:02:18.57#ibcon#*before return 0, iclass 19, count 0 2006.176.08:02:18.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:18.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:18.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:02:18.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:02:18.57$vc4f8/valo=3,672.99 2006.176.08:02:18.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.08:02:18.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.08:02:18.57#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:18.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:18.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:18.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:18.57#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:02:18.57#ibcon#first serial, iclass 21, count 0 2006.176.08:02:18.57#ibcon#enter sib2, iclass 21, count 0 2006.176.08:02:18.57#ibcon#flushed, iclass 21, count 0 2006.176.08:02:18.57#ibcon#about to write, iclass 21, count 0 2006.176.08:02:18.57#ibcon#wrote, iclass 21, count 0 2006.176.08:02:18.57#ibcon#about to read 3, iclass 21, count 0 2006.176.08:02:18.58#ibcon#read 3, iclass 21, count 0 2006.176.08:02:18.58#ibcon#about to read 4, iclass 21, count 0 2006.176.08:02:18.58#ibcon#read 4, iclass 21, count 0 2006.176.08:02:18.58#ibcon#about to read 5, iclass 21, count 0 2006.176.08:02:18.58#ibcon#read 5, iclass 21, count 0 2006.176.08:02:18.58#ibcon#about to read 6, iclass 21, count 0 2006.176.08:02:18.58#ibcon#read 6, iclass 21, count 0 2006.176.08:02:18.58#ibcon#end of sib2, iclass 21, count 0 2006.176.08:02:18.58#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:02:18.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:02:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:02:18.58#ibcon#*before write, iclass 21, count 0 2006.176.08:02:18.58#ibcon#enter sib2, iclass 21, count 0 2006.176.08:02:18.58#ibcon#flushed, iclass 21, count 0 2006.176.08:02:18.58#ibcon#about to write, iclass 21, count 0 2006.176.08:02:18.58#ibcon#wrote, iclass 21, count 0 2006.176.08:02:18.58#ibcon#about to read 3, iclass 21, count 0 2006.176.08:02:18.62#ibcon#read 3, iclass 21, count 0 2006.176.08:02:18.62#ibcon#about to read 4, iclass 21, count 0 2006.176.08:02:18.62#ibcon#read 4, iclass 21, count 0 2006.176.08:02:18.62#ibcon#about to read 5, iclass 21, count 0 2006.176.08:02:18.62#ibcon#read 5, iclass 21, count 0 2006.176.08:02:18.62#ibcon#about to read 6, iclass 21, count 0 2006.176.08:02:18.62#ibcon#read 6, iclass 21, count 0 2006.176.08:02:18.62#ibcon#end of sib2, iclass 21, count 0 2006.176.08:02:18.62#ibcon#*after write, iclass 21, count 0 2006.176.08:02:18.62#ibcon#*before return 0, iclass 21, count 0 2006.176.08:02:18.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:18.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:18.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:02:18.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:02:18.62$vc4f8/va=3,6 2006.176.08:02:18.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.08:02:18.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.08:02:18.62#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:18.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:18.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:18.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:18.70#ibcon#enter wrdev, iclass 23, count 2 2006.176.08:02:18.70#ibcon#first serial, iclass 23, count 2 2006.176.08:02:18.70#ibcon#enter sib2, iclass 23, count 2 2006.176.08:02:18.70#ibcon#flushed, iclass 23, count 2 2006.176.08:02:18.70#ibcon#about to write, iclass 23, count 2 2006.176.08:02:18.70#ibcon#wrote, iclass 23, count 2 2006.176.08:02:18.70#ibcon#about to read 3, iclass 23, count 2 2006.176.08:02:18.71#ibcon#read 3, iclass 23, count 2 2006.176.08:02:18.71#ibcon#about to read 4, iclass 23, count 2 2006.176.08:02:18.71#ibcon#read 4, iclass 23, count 2 2006.176.08:02:18.71#ibcon#about to read 5, iclass 23, count 2 2006.176.08:02:18.71#ibcon#read 5, iclass 23, count 2 2006.176.08:02:18.71#ibcon#about to read 6, iclass 23, count 2 2006.176.08:02:18.71#ibcon#read 6, iclass 23, count 2 2006.176.08:02:18.71#ibcon#end of sib2, iclass 23, count 2 2006.176.08:02:18.71#ibcon#*mode == 0, iclass 23, count 2 2006.176.08:02:18.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.08:02:18.71#ibcon#[25=AT03-06\r\n] 2006.176.08:02:18.71#ibcon#*before write, iclass 23, count 2 2006.176.08:02:18.71#ibcon#enter sib2, iclass 23, count 2 2006.176.08:02:18.71#ibcon#flushed, iclass 23, count 2 2006.176.08:02:18.71#ibcon#about to write, iclass 23, count 2 2006.176.08:02:18.71#ibcon#wrote, iclass 23, count 2 2006.176.08:02:18.71#ibcon#about to read 3, iclass 23, count 2 2006.176.08:02:18.74#ibcon#read 3, iclass 23, count 2 2006.176.08:02:18.74#ibcon#about to read 4, iclass 23, count 2 2006.176.08:02:18.74#ibcon#read 4, iclass 23, count 2 2006.176.08:02:18.74#ibcon#about to read 5, iclass 23, count 2 2006.176.08:02:18.74#ibcon#read 5, iclass 23, count 2 2006.176.08:02:18.74#ibcon#about to read 6, iclass 23, count 2 2006.176.08:02:18.74#ibcon#read 6, iclass 23, count 2 2006.176.08:02:18.74#ibcon#end of sib2, iclass 23, count 2 2006.176.08:02:18.74#ibcon#*after write, iclass 23, count 2 2006.176.08:02:18.74#ibcon#*before return 0, iclass 23, count 2 2006.176.08:02:18.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:18.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:18.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.08:02:18.74#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:18.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:18.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:18.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:18.86#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:02:18.86#ibcon#first serial, iclass 23, count 0 2006.176.08:02:18.86#ibcon#enter sib2, iclass 23, count 0 2006.176.08:02:18.86#ibcon#flushed, iclass 23, count 0 2006.176.08:02:18.86#ibcon#about to write, iclass 23, count 0 2006.176.08:02:18.86#ibcon#wrote, iclass 23, count 0 2006.176.08:02:18.86#ibcon#about to read 3, iclass 23, count 0 2006.176.08:02:18.88#ibcon#read 3, iclass 23, count 0 2006.176.08:02:18.88#ibcon#about to read 4, iclass 23, count 0 2006.176.08:02:18.88#ibcon#read 4, iclass 23, count 0 2006.176.08:02:18.88#ibcon#about to read 5, iclass 23, count 0 2006.176.08:02:18.88#ibcon#read 5, iclass 23, count 0 2006.176.08:02:18.88#ibcon#about to read 6, iclass 23, count 0 2006.176.08:02:18.88#ibcon#read 6, iclass 23, count 0 2006.176.08:02:18.88#ibcon#end of sib2, iclass 23, count 0 2006.176.08:02:18.88#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:02:18.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:02:18.88#ibcon#[25=USB\r\n] 2006.176.08:02:18.88#ibcon#*before write, iclass 23, count 0 2006.176.08:02:18.88#ibcon#enter sib2, iclass 23, count 0 2006.176.08:02:18.88#ibcon#flushed, iclass 23, count 0 2006.176.08:02:18.88#ibcon#about to write, iclass 23, count 0 2006.176.08:02:18.88#ibcon#wrote, iclass 23, count 0 2006.176.08:02:18.88#ibcon#about to read 3, iclass 23, count 0 2006.176.08:02:18.91#ibcon#read 3, iclass 23, count 0 2006.176.08:02:18.91#ibcon#about to read 4, iclass 23, count 0 2006.176.08:02:18.91#ibcon#read 4, iclass 23, count 0 2006.176.08:02:18.91#ibcon#about to read 5, iclass 23, count 0 2006.176.08:02:18.91#ibcon#read 5, iclass 23, count 0 2006.176.08:02:18.91#ibcon#about to read 6, iclass 23, count 0 2006.176.08:02:18.91#ibcon#read 6, iclass 23, count 0 2006.176.08:02:18.91#ibcon#end of sib2, iclass 23, count 0 2006.176.08:02:18.91#ibcon#*after write, iclass 23, count 0 2006.176.08:02:18.91#ibcon#*before return 0, iclass 23, count 0 2006.176.08:02:18.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:18.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:18.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:02:18.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:02:18.91$vc4f8/valo=4,832.99 2006.176.08:02:18.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.08:02:18.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.08:02:18.91#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:18.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:18.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:18.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:18.91#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:02:18.91#ibcon#first serial, iclass 25, count 0 2006.176.08:02:18.91#ibcon#enter sib2, iclass 25, count 0 2006.176.08:02:18.91#ibcon#flushed, iclass 25, count 0 2006.176.08:02:18.91#ibcon#about to write, iclass 25, count 0 2006.176.08:02:18.91#ibcon#wrote, iclass 25, count 0 2006.176.08:02:18.91#ibcon#about to read 3, iclass 25, count 0 2006.176.08:02:18.93#ibcon#read 3, iclass 25, count 0 2006.176.08:02:18.93#ibcon#about to read 4, iclass 25, count 0 2006.176.08:02:18.93#ibcon#read 4, iclass 25, count 0 2006.176.08:02:18.93#ibcon#about to read 5, iclass 25, count 0 2006.176.08:02:18.93#ibcon#read 5, iclass 25, count 0 2006.176.08:02:18.93#ibcon#about to read 6, iclass 25, count 0 2006.176.08:02:18.93#ibcon#read 6, iclass 25, count 0 2006.176.08:02:18.93#ibcon#end of sib2, iclass 25, count 0 2006.176.08:02:18.93#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:02:18.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:02:18.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:02:18.93#ibcon#*before write, iclass 25, count 0 2006.176.08:02:18.93#ibcon#enter sib2, iclass 25, count 0 2006.176.08:02:18.93#ibcon#flushed, iclass 25, count 0 2006.176.08:02:18.93#ibcon#about to write, iclass 25, count 0 2006.176.08:02:18.93#ibcon#wrote, iclass 25, count 0 2006.176.08:02:18.93#ibcon#about to read 3, iclass 25, count 0 2006.176.08:02:18.97#ibcon#read 3, iclass 25, count 0 2006.176.08:02:18.97#ibcon#about to read 4, iclass 25, count 0 2006.176.08:02:18.97#ibcon#read 4, iclass 25, count 0 2006.176.08:02:18.97#ibcon#about to read 5, iclass 25, count 0 2006.176.08:02:18.97#ibcon#read 5, iclass 25, count 0 2006.176.08:02:18.97#ibcon#about to read 6, iclass 25, count 0 2006.176.08:02:18.97#ibcon#read 6, iclass 25, count 0 2006.176.08:02:18.97#ibcon#end of sib2, iclass 25, count 0 2006.176.08:02:18.97#ibcon#*after write, iclass 25, count 0 2006.176.08:02:18.97#ibcon#*before return 0, iclass 25, count 0 2006.176.08:02:18.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:18.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:18.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:02:18.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:02:18.97$vc4f8/va=4,7 2006.176.08:02:18.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.08:02:18.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.08:02:18.97#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:18.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:19.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:19.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:19.03#ibcon#enter wrdev, iclass 27, count 2 2006.176.08:02:19.03#ibcon#first serial, iclass 27, count 2 2006.176.08:02:19.03#ibcon#enter sib2, iclass 27, count 2 2006.176.08:02:19.03#ibcon#flushed, iclass 27, count 2 2006.176.08:02:19.03#ibcon#about to write, iclass 27, count 2 2006.176.08:02:19.03#ibcon#wrote, iclass 27, count 2 2006.176.08:02:19.03#ibcon#about to read 3, iclass 27, count 2 2006.176.08:02:19.05#ibcon#read 3, iclass 27, count 2 2006.176.08:02:19.05#ibcon#about to read 4, iclass 27, count 2 2006.176.08:02:19.05#ibcon#read 4, iclass 27, count 2 2006.176.08:02:19.05#ibcon#about to read 5, iclass 27, count 2 2006.176.08:02:19.05#ibcon#read 5, iclass 27, count 2 2006.176.08:02:19.05#ibcon#about to read 6, iclass 27, count 2 2006.176.08:02:19.05#ibcon#read 6, iclass 27, count 2 2006.176.08:02:19.05#ibcon#end of sib2, iclass 27, count 2 2006.176.08:02:19.05#ibcon#*mode == 0, iclass 27, count 2 2006.176.08:02:19.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.08:02:19.05#ibcon#[25=AT04-07\r\n] 2006.176.08:02:19.05#ibcon#*before write, iclass 27, count 2 2006.176.08:02:19.05#ibcon#enter sib2, iclass 27, count 2 2006.176.08:02:19.05#ibcon#flushed, iclass 27, count 2 2006.176.08:02:19.05#ibcon#about to write, iclass 27, count 2 2006.176.08:02:19.05#ibcon#wrote, iclass 27, count 2 2006.176.08:02:19.05#ibcon#about to read 3, iclass 27, count 2 2006.176.08:02:19.08#ibcon#read 3, iclass 27, count 2 2006.176.08:02:19.08#ibcon#about to read 4, iclass 27, count 2 2006.176.08:02:19.08#ibcon#read 4, iclass 27, count 2 2006.176.08:02:19.08#ibcon#about to read 5, iclass 27, count 2 2006.176.08:02:19.08#ibcon#read 5, iclass 27, count 2 2006.176.08:02:19.08#ibcon#about to read 6, iclass 27, count 2 2006.176.08:02:19.08#ibcon#read 6, iclass 27, count 2 2006.176.08:02:19.08#ibcon#end of sib2, iclass 27, count 2 2006.176.08:02:19.08#ibcon#*after write, iclass 27, count 2 2006.176.08:02:19.08#ibcon#*before return 0, iclass 27, count 2 2006.176.08:02:19.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:19.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:19.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.08:02:19.08#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:19.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:19.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:19.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:19.20#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:02:19.20#ibcon#first serial, iclass 27, count 0 2006.176.08:02:19.20#ibcon#enter sib2, iclass 27, count 0 2006.176.08:02:19.20#ibcon#flushed, iclass 27, count 0 2006.176.08:02:19.20#ibcon#about to write, iclass 27, count 0 2006.176.08:02:19.20#ibcon#wrote, iclass 27, count 0 2006.176.08:02:19.20#ibcon#about to read 3, iclass 27, count 0 2006.176.08:02:19.22#ibcon#read 3, iclass 27, count 0 2006.176.08:02:19.22#ibcon#about to read 4, iclass 27, count 0 2006.176.08:02:19.22#ibcon#read 4, iclass 27, count 0 2006.176.08:02:19.22#ibcon#about to read 5, iclass 27, count 0 2006.176.08:02:19.22#ibcon#read 5, iclass 27, count 0 2006.176.08:02:19.22#ibcon#about to read 6, iclass 27, count 0 2006.176.08:02:19.22#ibcon#read 6, iclass 27, count 0 2006.176.08:02:19.22#ibcon#end of sib2, iclass 27, count 0 2006.176.08:02:19.22#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:02:19.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:02:19.22#ibcon#[25=USB\r\n] 2006.176.08:02:19.22#ibcon#*before write, iclass 27, count 0 2006.176.08:02:19.22#ibcon#enter sib2, iclass 27, count 0 2006.176.08:02:19.22#ibcon#flushed, iclass 27, count 0 2006.176.08:02:19.22#ibcon#about to write, iclass 27, count 0 2006.176.08:02:19.22#ibcon#wrote, iclass 27, count 0 2006.176.08:02:19.22#ibcon#about to read 3, iclass 27, count 0 2006.176.08:02:19.25#ibcon#read 3, iclass 27, count 0 2006.176.08:02:19.25#ibcon#about to read 4, iclass 27, count 0 2006.176.08:02:19.25#ibcon#read 4, iclass 27, count 0 2006.176.08:02:19.25#ibcon#about to read 5, iclass 27, count 0 2006.176.08:02:19.25#ibcon#read 5, iclass 27, count 0 2006.176.08:02:19.25#ibcon#about to read 6, iclass 27, count 0 2006.176.08:02:19.25#ibcon#read 6, iclass 27, count 0 2006.176.08:02:19.25#ibcon#end of sib2, iclass 27, count 0 2006.176.08:02:19.25#ibcon#*after write, iclass 27, count 0 2006.176.08:02:19.25#ibcon#*before return 0, iclass 27, count 0 2006.176.08:02:19.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:19.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:19.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:02:19.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:02:19.25$vc4f8/valo=5,652.99 2006.176.08:02:19.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.08:02:19.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.08:02:19.25#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:19.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:19.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:19.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:19.25#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:02:19.25#ibcon#first serial, iclass 29, count 0 2006.176.08:02:19.25#ibcon#enter sib2, iclass 29, count 0 2006.176.08:02:19.25#ibcon#flushed, iclass 29, count 0 2006.176.08:02:19.25#ibcon#about to write, iclass 29, count 0 2006.176.08:02:19.25#ibcon#wrote, iclass 29, count 0 2006.176.08:02:19.25#ibcon#about to read 3, iclass 29, count 0 2006.176.08:02:19.27#ibcon#read 3, iclass 29, count 0 2006.176.08:02:19.27#ibcon#about to read 4, iclass 29, count 0 2006.176.08:02:19.27#ibcon#read 4, iclass 29, count 0 2006.176.08:02:19.27#ibcon#about to read 5, iclass 29, count 0 2006.176.08:02:19.27#ibcon#read 5, iclass 29, count 0 2006.176.08:02:19.27#ibcon#about to read 6, iclass 29, count 0 2006.176.08:02:19.27#ibcon#read 6, iclass 29, count 0 2006.176.08:02:19.27#ibcon#end of sib2, iclass 29, count 0 2006.176.08:02:19.27#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:02:19.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:02:19.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:02:19.27#ibcon#*before write, iclass 29, count 0 2006.176.08:02:19.27#ibcon#enter sib2, iclass 29, count 0 2006.176.08:02:19.27#ibcon#flushed, iclass 29, count 0 2006.176.08:02:19.27#ibcon#about to write, iclass 29, count 0 2006.176.08:02:19.27#ibcon#wrote, iclass 29, count 0 2006.176.08:02:19.27#ibcon#about to read 3, iclass 29, count 0 2006.176.08:02:19.31#ibcon#read 3, iclass 29, count 0 2006.176.08:02:19.31#ibcon#about to read 4, iclass 29, count 0 2006.176.08:02:19.31#ibcon#read 4, iclass 29, count 0 2006.176.08:02:19.31#ibcon#about to read 5, iclass 29, count 0 2006.176.08:02:19.31#ibcon#read 5, iclass 29, count 0 2006.176.08:02:19.31#ibcon#about to read 6, iclass 29, count 0 2006.176.08:02:19.31#ibcon#read 6, iclass 29, count 0 2006.176.08:02:19.31#ibcon#end of sib2, iclass 29, count 0 2006.176.08:02:19.31#ibcon#*after write, iclass 29, count 0 2006.176.08:02:19.31#ibcon#*before return 0, iclass 29, count 0 2006.176.08:02:19.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:19.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:19.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:02:19.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:02:19.31$vc4f8/va=5,7 2006.176.08:02:19.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.08:02:19.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.08:02:19.31#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:19.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:19.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:19.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:19.37#ibcon#enter wrdev, iclass 31, count 2 2006.176.08:02:19.37#ibcon#first serial, iclass 31, count 2 2006.176.08:02:19.37#ibcon#enter sib2, iclass 31, count 2 2006.176.08:02:19.37#ibcon#flushed, iclass 31, count 2 2006.176.08:02:19.37#ibcon#about to write, iclass 31, count 2 2006.176.08:02:19.37#ibcon#wrote, iclass 31, count 2 2006.176.08:02:19.37#ibcon#about to read 3, iclass 31, count 2 2006.176.08:02:19.39#ibcon#read 3, iclass 31, count 2 2006.176.08:02:19.39#ibcon#about to read 4, iclass 31, count 2 2006.176.08:02:19.39#ibcon#read 4, iclass 31, count 2 2006.176.08:02:19.39#ibcon#about to read 5, iclass 31, count 2 2006.176.08:02:19.39#ibcon#read 5, iclass 31, count 2 2006.176.08:02:19.39#ibcon#about to read 6, iclass 31, count 2 2006.176.08:02:19.39#ibcon#read 6, iclass 31, count 2 2006.176.08:02:19.39#ibcon#end of sib2, iclass 31, count 2 2006.176.08:02:19.39#ibcon#*mode == 0, iclass 31, count 2 2006.176.08:02:19.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.08:02:19.39#ibcon#[25=AT05-07\r\n] 2006.176.08:02:19.39#ibcon#*before write, iclass 31, count 2 2006.176.08:02:19.39#ibcon#enter sib2, iclass 31, count 2 2006.176.08:02:19.39#ibcon#flushed, iclass 31, count 2 2006.176.08:02:19.39#ibcon#about to write, iclass 31, count 2 2006.176.08:02:19.39#ibcon#wrote, iclass 31, count 2 2006.176.08:02:19.39#ibcon#about to read 3, iclass 31, count 2 2006.176.08:02:19.42#ibcon#read 3, iclass 31, count 2 2006.176.08:02:19.42#ibcon#about to read 4, iclass 31, count 2 2006.176.08:02:19.42#ibcon#read 4, iclass 31, count 2 2006.176.08:02:19.42#ibcon#about to read 5, iclass 31, count 2 2006.176.08:02:19.42#ibcon#read 5, iclass 31, count 2 2006.176.08:02:19.42#ibcon#about to read 6, iclass 31, count 2 2006.176.08:02:19.42#ibcon#read 6, iclass 31, count 2 2006.176.08:02:19.42#ibcon#end of sib2, iclass 31, count 2 2006.176.08:02:19.42#ibcon#*after write, iclass 31, count 2 2006.176.08:02:19.42#ibcon#*before return 0, iclass 31, count 2 2006.176.08:02:19.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:19.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:19.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.08:02:19.42#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:19.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:19.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:19.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:19.54#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:02:19.54#ibcon#first serial, iclass 31, count 0 2006.176.08:02:19.54#ibcon#enter sib2, iclass 31, count 0 2006.176.08:02:19.54#ibcon#flushed, iclass 31, count 0 2006.176.08:02:19.54#ibcon#about to write, iclass 31, count 0 2006.176.08:02:19.54#ibcon#wrote, iclass 31, count 0 2006.176.08:02:19.54#ibcon#about to read 3, iclass 31, count 0 2006.176.08:02:19.56#ibcon#read 3, iclass 31, count 0 2006.176.08:02:19.56#ibcon#about to read 4, iclass 31, count 0 2006.176.08:02:19.56#ibcon#read 4, iclass 31, count 0 2006.176.08:02:19.56#ibcon#about to read 5, iclass 31, count 0 2006.176.08:02:19.56#ibcon#read 5, iclass 31, count 0 2006.176.08:02:19.56#ibcon#about to read 6, iclass 31, count 0 2006.176.08:02:19.56#ibcon#read 6, iclass 31, count 0 2006.176.08:02:19.56#ibcon#end of sib2, iclass 31, count 0 2006.176.08:02:19.56#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:02:19.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:02:19.56#ibcon#[25=USB\r\n] 2006.176.08:02:19.56#ibcon#*before write, iclass 31, count 0 2006.176.08:02:19.56#ibcon#enter sib2, iclass 31, count 0 2006.176.08:02:19.56#ibcon#flushed, iclass 31, count 0 2006.176.08:02:19.56#ibcon#about to write, iclass 31, count 0 2006.176.08:02:19.56#ibcon#wrote, iclass 31, count 0 2006.176.08:02:19.56#ibcon#about to read 3, iclass 31, count 0 2006.176.08:02:19.59#ibcon#read 3, iclass 31, count 0 2006.176.08:02:19.59#ibcon#about to read 4, iclass 31, count 0 2006.176.08:02:19.59#ibcon#read 4, iclass 31, count 0 2006.176.08:02:19.59#ibcon#about to read 5, iclass 31, count 0 2006.176.08:02:19.59#ibcon#read 5, iclass 31, count 0 2006.176.08:02:19.59#ibcon#about to read 6, iclass 31, count 0 2006.176.08:02:19.59#ibcon#read 6, iclass 31, count 0 2006.176.08:02:19.59#ibcon#end of sib2, iclass 31, count 0 2006.176.08:02:19.59#ibcon#*after write, iclass 31, count 0 2006.176.08:02:19.59#ibcon#*before return 0, iclass 31, count 0 2006.176.08:02:19.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:19.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:19.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:02:19.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:02:19.59$vc4f8/valo=6,772.99 2006.176.08:02:19.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.08:02:19.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.08:02:19.59#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:19.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:19.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:19.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:19.59#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:02:19.59#ibcon#first serial, iclass 33, count 0 2006.176.08:02:19.59#ibcon#enter sib2, iclass 33, count 0 2006.176.08:02:19.59#ibcon#flushed, iclass 33, count 0 2006.176.08:02:19.59#ibcon#about to write, iclass 33, count 0 2006.176.08:02:19.59#ibcon#wrote, iclass 33, count 0 2006.176.08:02:19.59#ibcon#about to read 3, iclass 33, count 0 2006.176.08:02:19.61#ibcon#read 3, iclass 33, count 0 2006.176.08:02:19.61#ibcon#about to read 4, iclass 33, count 0 2006.176.08:02:19.61#ibcon#read 4, iclass 33, count 0 2006.176.08:02:19.61#ibcon#about to read 5, iclass 33, count 0 2006.176.08:02:19.61#ibcon#read 5, iclass 33, count 0 2006.176.08:02:19.61#ibcon#about to read 6, iclass 33, count 0 2006.176.08:02:19.61#ibcon#read 6, iclass 33, count 0 2006.176.08:02:19.61#ibcon#end of sib2, iclass 33, count 0 2006.176.08:02:19.61#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:02:19.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:02:19.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:02:19.61#ibcon#*before write, iclass 33, count 0 2006.176.08:02:19.61#ibcon#enter sib2, iclass 33, count 0 2006.176.08:02:19.61#ibcon#flushed, iclass 33, count 0 2006.176.08:02:19.61#ibcon#about to write, iclass 33, count 0 2006.176.08:02:19.61#ibcon#wrote, iclass 33, count 0 2006.176.08:02:19.61#ibcon#about to read 3, iclass 33, count 0 2006.176.08:02:19.65#ibcon#read 3, iclass 33, count 0 2006.176.08:02:19.65#ibcon#about to read 4, iclass 33, count 0 2006.176.08:02:19.65#ibcon#read 4, iclass 33, count 0 2006.176.08:02:19.65#ibcon#about to read 5, iclass 33, count 0 2006.176.08:02:19.65#ibcon#read 5, iclass 33, count 0 2006.176.08:02:19.65#ibcon#about to read 6, iclass 33, count 0 2006.176.08:02:19.65#ibcon#read 6, iclass 33, count 0 2006.176.08:02:19.65#ibcon#end of sib2, iclass 33, count 0 2006.176.08:02:19.65#ibcon#*after write, iclass 33, count 0 2006.176.08:02:19.65#ibcon#*before return 0, iclass 33, count 0 2006.176.08:02:19.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:19.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:19.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:02:19.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:02:19.65$vc4f8/va=6,6 2006.176.08:02:19.65#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.176.08:02:19.65#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.176.08:02:19.65#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:19.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:02:19.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:02:19.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:02:19.71#ibcon#enter wrdev, iclass 35, count 2 2006.176.08:02:19.71#ibcon#first serial, iclass 35, count 2 2006.176.08:02:19.71#ibcon#enter sib2, iclass 35, count 2 2006.176.08:02:19.71#ibcon#flushed, iclass 35, count 2 2006.176.08:02:19.71#ibcon#about to write, iclass 35, count 2 2006.176.08:02:19.71#ibcon#wrote, iclass 35, count 2 2006.176.08:02:19.71#ibcon#about to read 3, iclass 35, count 2 2006.176.08:02:19.73#ibcon#read 3, iclass 35, count 2 2006.176.08:02:19.73#ibcon#about to read 4, iclass 35, count 2 2006.176.08:02:19.73#ibcon#read 4, iclass 35, count 2 2006.176.08:02:19.73#ibcon#about to read 5, iclass 35, count 2 2006.176.08:02:19.73#ibcon#read 5, iclass 35, count 2 2006.176.08:02:19.73#ibcon#about to read 6, iclass 35, count 2 2006.176.08:02:19.73#ibcon#read 6, iclass 35, count 2 2006.176.08:02:19.73#ibcon#end of sib2, iclass 35, count 2 2006.176.08:02:19.73#ibcon#*mode == 0, iclass 35, count 2 2006.176.08:02:19.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.176.08:02:19.73#ibcon#[25=AT06-06\r\n] 2006.176.08:02:19.73#ibcon#*before write, iclass 35, count 2 2006.176.08:02:19.73#ibcon#enter sib2, iclass 35, count 2 2006.176.08:02:19.73#ibcon#flushed, iclass 35, count 2 2006.176.08:02:19.73#ibcon#about to write, iclass 35, count 2 2006.176.08:02:19.73#ibcon#wrote, iclass 35, count 2 2006.176.08:02:19.73#ibcon#about to read 3, iclass 35, count 2 2006.176.08:02:19.76#ibcon#read 3, iclass 35, count 2 2006.176.08:02:19.76#ibcon#about to read 4, iclass 35, count 2 2006.176.08:02:19.76#ibcon#read 4, iclass 35, count 2 2006.176.08:02:19.76#ibcon#about to read 5, iclass 35, count 2 2006.176.08:02:19.76#ibcon#read 5, iclass 35, count 2 2006.176.08:02:19.76#ibcon#about to read 6, iclass 35, count 2 2006.176.08:02:19.76#ibcon#read 6, iclass 35, count 2 2006.176.08:02:19.76#ibcon#end of sib2, iclass 35, count 2 2006.176.08:02:19.76#ibcon#*after write, iclass 35, count 2 2006.176.08:02:19.76#ibcon#*before return 0, iclass 35, count 2 2006.176.08:02:19.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:02:19.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:02:19.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.176.08:02:19.76#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:19.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:02:19.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:02:19.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:02:19.88#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:02:19.88#ibcon#first serial, iclass 35, count 0 2006.176.08:02:19.88#ibcon#enter sib2, iclass 35, count 0 2006.176.08:02:19.88#ibcon#flushed, iclass 35, count 0 2006.176.08:02:19.88#ibcon#about to write, iclass 35, count 0 2006.176.08:02:19.88#ibcon#wrote, iclass 35, count 0 2006.176.08:02:19.88#ibcon#about to read 3, iclass 35, count 0 2006.176.08:02:19.90#ibcon#read 3, iclass 35, count 0 2006.176.08:02:19.90#ibcon#about to read 4, iclass 35, count 0 2006.176.08:02:19.90#ibcon#read 4, iclass 35, count 0 2006.176.08:02:19.90#ibcon#about to read 5, iclass 35, count 0 2006.176.08:02:19.90#ibcon#read 5, iclass 35, count 0 2006.176.08:02:19.90#ibcon#about to read 6, iclass 35, count 0 2006.176.08:02:19.90#ibcon#read 6, iclass 35, count 0 2006.176.08:02:19.90#ibcon#end of sib2, iclass 35, count 0 2006.176.08:02:19.90#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:02:19.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:02:19.90#ibcon#[25=USB\r\n] 2006.176.08:02:19.90#ibcon#*before write, iclass 35, count 0 2006.176.08:02:19.90#ibcon#enter sib2, iclass 35, count 0 2006.176.08:02:19.90#ibcon#flushed, iclass 35, count 0 2006.176.08:02:19.90#ibcon#about to write, iclass 35, count 0 2006.176.08:02:19.90#ibcon#wrote, iclass 35, count 0 2006.176.08:02:19.90#ibcon#about to read 3, iclass 35, count 0 2006.176.08:02:19.93#ibcon#read 3, iclass 35, count 0 2006.176.08:02:19.93#ibcon#about to read 4, iclass 35, count 0 2006.176.08:02:19.93#ibcon#read 4, iclass 35, count 0 2006.176.08:02:19.93#ibcon#about to read 5, iclass 35, count 0 2006.176.08:02:19.93#ibcon#read 5, iclass 35, count 0 2006.176.08:02:19.93#ibcon#about to read 6, iclass 35, count 0 2006.176.08:02:19.93#ibcon#read 6, iclass 35, count 0 2006.176.08:02:19.93#ibcon#end of sib2, iclass 35, count 0 2006.176.08:02:19.93#ibcon#*after write, iclass 35, count 0 2006.176.08:02:19.93#ibcon#*before return 0, iclass 35, count 0 2006.176.08:02:19.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:02:19.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:02:19.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:02:19.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:02:19.93$vc4f8/valo=7,832.99 2006.176.08:02:19.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.176.08:02:19.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.176.08:02:19.93#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:19.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:02:19.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:02:19.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:02:19.93#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:02:19.93#ibcon#first serial, iclass 37, count 0 2006.176.08:02:19.93#ibcon#enter sib2, iclass 37, count 0 2006.176.08:02:19.93#ibcon#flushed, iclass 37, count 0 2006.176.08:02:19.93#ibcon#about to write, iclass 37, count 0 2006.176.08:02:19.93#ibcon#wrote, iclass 37, count 0 2006.176.08:02:19.93#ibcon#about to read 3, iclass 37, count 0 2006.176.08:02:19.95#ibcon#read 3, iclass 37, count 0 2006.176.08:02:19.95#ibcon#about to read 4, iclass 37, count 0 2006.176.08:02:19.95#ibcon#read 4, iclass 37, count 0 2006.176.08:02:19.95#ibcon#about to read 5, iclass 37, count 0 2006.176.08:02:19.95#ibcon#read 5, iclass 37, count 0 2006.176.08:02:19.95#ibcon#about to read 6, iclass 37, count 0 2006.176.08:02:19.95#ibcon#read 6, iclass 37, count 0 2006.176.08:02:19.95#ibcon#end of sib2, iclass 37, count 0 2006.176.08:02:19.95#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:02:19.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:02:19.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:02:19.95#ibcon#*before write, iclass 37, count 0 2006.176.08:02:19.95#ibcon#enter sib2, iclass 37, count 0 2006.176.08:02:19.95#ibcon#flushed, iclass 37, count 0 2006.176.08:02:19.95#ibcon#about to write, iclass 37, count 0 2006.176.08:02:19.95#ibcon#wrote, iclass 37, count 0 2006.176.08:02:19.95#ibcon#about to read 3, iclass 37, count 0 2006.176.08:02:19.99#ibcon#read 3, iclass 37, count 0 2006.176.08:02:19.99#ibcon#about to read 4, iclass 37, count 0 2006.176.08:02:19.99#ibcon#read 4, iclass 37, count 0 2006.176.08:02:19.99#ibcon#about to read 5, iclass 37, count 0 2006.176.08:02:19.99#ibcon#read 5, iclass 37, count 0 2006.176.08:02:19.99#ibcon#about to read 6, iclass 37, count 0 2006.176.08:02:19.99#ibcon#read 6, iclass 37, count 0 2006.176.08:02:19.99#ibcon#end of sib2, iclass 37, count 0 2006.176.08:02:19.99#ibcon#*after write, iclass 37, count 0 2006.176.08:02:19.99#ibcon#*before return 0, iclass 37, count 0 2006.176.08:02:19.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:02:19.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:02:19.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:02:19.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:02:19.99$vc4f8/va=7,6 2006.176.08:02:19.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.176.08:02:19.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.176.08:02:19.99#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:19.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:02:20.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:02:20.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:02:20.05#ibcon#enter wrdev, iclass 39, count 2 2006.176.08:02:20.05#ibcon#first serial, iclass 39, count 2 2006.176.08:02:20.05#ibcon#enter sib2, iclass 39, count 2 2006.176.08:02:20.05#ibcon#flushed, iclass 39, count 2 2006.176.08:02:20.05#ibcon#about to write, iclass 39, count 2 2006.176.08:02:20.05#ibcon#wrote, iclass 39, count 2 2006.176.08:02:20.05#ibcon#about to read 3, iclass 39, count 2 2006.176.08:02:20.07#ibcon#read 3, iclass 39, count 2 2006.176.08:02:20.07#ibcon#about to read 4, iclass 39, count 2 2006.176.08:02:20.07#ibcon#read 4, iclass 39, count 2 2006.176.08:02:20.07#ibcon#about to read 5, iclass 39, count 2 2006.176.08:02:20.07#ibcon#read 5, iclass 39, count 2 2006.176.08:02:20.07#ibcon#about to read 6, iclass 39, count 2 2006.176.08:02:20.07#ibcon#read 6, iclass 39, count 2 2006.176.08:02:20.07#ibcon#end of sib2, iclass 39, count 2 2006.176.08:02:20.07#ibcon#*mode == 0, iclass 39, count 2 2006.176.08:02:20.07#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.176.08:02:20.07#ibcon#[25=AT07-06\r\n] 2006.176.08:02:20.07#ibcon#*before write, iclass 39, count 2 2006.176.08:02:20.07#ibcon#enter sib2, iclass 39, count 2 2006.176.08:02:20.07#ibcon#flushed, iclass 39, count 2 2006.176.08:02:20.07#ibcon#about to write, iclass 39, count 2 2006.176.08:02:20.07#ibcon#wrote, iclass 39, count 2 2006.176.08:02:20.07#ibcon#about to read 3, iclass 39, count 2 2006.176.08:02:20.10#ibcon#read 3, iclass 39, count 2 2006.176.08:02:20.10#ibcon#about to read 4, iclass 39, count 2 2006.176.08:02:20.10#ibcon#read 4, iclass 39, count 2 2006.176.08:02:20.10#ibcon#about to read 5, iclass 39, count 2 2006.176.08:02:20.10#ibcon#read 5, iclass 39, count 2 2006.176.08:02:20.10#ibcon#about to read 6, iclass 39, count 2 2006.176.08:02:20.10#ibcon#read 6, iclass 39, count 2 2006.176.08:02:20.10#ibcon#end of sib2, iclass 39, count 2 2006.176.08:02:20.10#ibcon#*after write, iclass 39, count 2 2006.176.08:02:20.10#ibcon#*before return 0, iclass 39, count 2 2006.176.08:02:20.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:02:20.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:02:20.10#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.176.08:02:20.10#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:20.10#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:02:20.22#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:02:20.22#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:02:20.22#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:02:20.22#ibcon#first serial, iclass 39, count 0 2006.176.08:02:20.22#ibcon#enter sib2, iclass 39, count 0 2006.176.08:02:20.22#ibcon#flushed, iclass 39, count 0 2006.176.08:02:20.22#ibcon#about to write, iclass 39, count 0 2006.176.08:02:20.22#ibcon#wrote, iclass 39, count 0 2006.176.08:02:20.22#ibcon#about to read 3, iclass 39, count 0 2006.176.08:02:20.24#ibcon#read 3, iclass 39, count 0 2006.176.08:02:20.24#ibcon#about to read 4, iclass 39, count 0 2006.176.08:02:20.24#ibcon#read 4, iclass 39, count 0 2006.176.08:02:20.24#ibcon#about to read 5, iclass 39, count 0 2006.176.08:02:20.24#ibcon#read 5, iclass 39, count 0 2006.176.08:02:20.24#ibcon#about to read 6, iclass 39, count 0 2006.176.08:02:20.24#ibcon#read 6, iclass 39, count 0 2006.176.08:02:20.24#ibcon#end of sib2, iclass 39, count 0 2006.176.08:02:20.24#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:02:20.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:02:20.24#ibcon#[25=USB\r\n] 2006.176.08:02:20.24#ibcon#*before write, iclass 39, count 0 2006.176.08:02:20.24#ibcon#enter sib2, iclass 39, count 0 2006.176.08:02:20.24#ibcon#flushed, iclass 39, count 0 2006.176.08:02:20.24#ibcon#about to write, iclass 39, count 0 2006.176.08:02:20.24#ibcon#wrote, iclass 39, count 0 2006.176.08:02:20.24#ibcon#about to read 3, iclass 39, count 0 2006.176.08:02:20.27#ibcon#read 3, iclass 39, count 0 2006.176.08:02:20.27#ibcon#about to read 4, iclass 39, count 0 2006.176.08:02:20.27#ibcon#read 4, iclass 39, count 0 2006.176.08:02:20.27#ibcon#about to read 5, iclass 39, count 0 2006.176.08:02:20.27#ibcon#read 5, iclass 39, count 0 2006.176.08:02:20.27#ibcon#about to read 6, iclass 39, count 0 2006.176.08:02:20.27#ibcon#read 6, iclass 39, count 0 2006.176.08:02:20.27#ibcon#end of sib2, iclass 39, count 0 2006.176.08:02:20.27#ibcon#*after write, iclass 39, count 0 2006.176.08:02:20.27#ibcon#*before return 0, iclass 39, count 0 2006.176.08:02:20.27#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:02:20.27#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:02:20.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:02:20.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:02:20.27$vc4f8/valo=8,852.99 2006.176.08:02:20.27#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.08:02:20.27#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.08:02:20.27#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:20.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:02:20.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:02:20.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:02:20.27#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:02:20.27#ibcon#first serial, iclass 3, count 0 2006.176.08:02:20.27#ibcon#enter sib2, iclass 3, count 0 2006.176.08:02:20.27#ibcon#flushed, iclass 3, count 0 2006.176.08:02:20.27#ibcon#about to write, iclass 3, count 0 2006.176.08:02:20.27#ibcon#wrote, iclass 3, count 0 2006.176.08:02:20.27#ibcon#about to read 3, iclass 3, count 0 2006.176.08:02:20.29#ibcon#read 3, iclass 3, count 0 2006.176.08:02:20.29#ibcon#about to read 4, iclass 3, count 0 2006.176.08:02:20.29#ibcon#read 4, iclass 3, count 0 2006.176.08:02:20.29#ibcon#about to read 5, iclass 3, count 0 2006.176.08:02:20.29#ibcon#read 5, iclass 3, count 0 2006.176.08:02:20.29#ibcon#about to read 6, iclass 3, count 0 2006.176.08:02:20.29#ibcon#read 6, iclass 3, count 0 2006.176.08:02:20.29#ibcon#end of sib2, iclass 3, count 0 2006.176.08:02:20.29#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:02:20.29#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:02:20.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:02:20.29#ibcon#*before write, iclass 3, count 0 2006.176.08:02:20.29#ibcon#enter sib2, iclass 3, count 0 2006.176.08:02:20.29#ibcon#flushed, iclass 3, count 0 2006.176.08:02:20.29#ibcon#about to write, iclass 3, count 0 2006.176.08:02:20.29#ibcon#wrote, iclass 3, count 0 2006.176.08:02:20.29#ibcon#about to read 3, iclass 3, count 0 2006.176.08:02:20.33#ibcon#read 3, iclass 3, count 0 2006.176.08:02:20.33#ibcon#about to read 4, iclass 3, count 0 2006.176.08:02:20.33#ibcon#read 4, iclass 3, count 0 2006.176.08:02:20.33#ibcon#about to read 5, iclass 3, count 0 2006.176.08:02:20.33#ibcon#read 5, iclass 3, count 0 2006.176.08:02:20.33#ibcon#about to read 6, iclass 3, count 0 2006.176.08:02:20.33#ibcon#read 6, iclass 3, count 0 2006.176.08:02:20.33#ibcon#end of sib2, iclass 3, count 0 2006.176.08:02:20.33#ibcon#*after write, iclass 3, count 0 2006.176.08:02:20.33#ibcon#*before return 0, iclass 3, count 0 2006.176.08:02:20.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:02:20.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:02:20.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:02:20.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:02:20.33$vc4f8/va=8,6 2006.176.08:02:20.33#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.176.08:02:20.33#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.176.08:02:20.33#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:20.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:02:20.39#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:02:20.39#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:02:20.39#ibcon#enter wrdev, iclass 5, count 2 2006.176.08:02:20.39#ibcon#first serial, iclass 5, count 2 2006.176.08:02:20.39#ibcon#enter sib2, iclass 5, count 2 2006.176.08:02:20.39#ibcon#flushed, iclass 5, count 2 2006.176.08:02:20.39#ibcon#about to write, iclass 5, count 2 2006.176.08:02:20.39#ibcon#wrote, iclass 5, count 2 2006.176.08:02:20.39#ibcon#about to read 3, iclass 5, count 2 2006.176.08:02:20.41#ibcon#read 3, iclass 5, count 2 2006.176.08:02:20.41#ibcon#about to read 4, iclass 5, count 2 2006.176.08:02:20.41#ibcon#read 4, iclass 5, count 2 2006.176.08:02:20.41#ibcon#about to read 5, iclass 5, count 2 2006.176.08:02:20.41#ibcon#read 5, iclass 5, count 2 2006.176.08:02:20.41#ibcon#about to read 6, iclass 5, count 2 2006.176.08:02:20.41#ibcon#read 6, iclass 5, count 2 2006.176.08:02:20.41#ibcon#end of sib2, iclass 5, count 2 2006.176.08:02:20.41#ibcon#*mode == 0, iclass 5, count 2 2006.176.08:02:20.41#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.176.08:02:20.41#ibcon#[25=AT08-06\r\n] 2006.176.08:02:20.41#ibcon#*before write, iclass 5, count 2 2006.176.08:02:20.41#ibcon#enter sib2, iclass 5, count 2 2006.176.08:02:20.41#ibcon#flushed, iclass 5, count 2 2006.176.08:02:20.41#ibcon#about to write, iclass 5, count 2 2006.176.08:02:20.41#ibcon#wrote, iclass 5, count 2 2006.176.08:02:20.41#ibcon#about to read 3, iclass 5, count 2 2006.176.08:02:20.45#ibcon#read 3, iclass 5, count 2 2006.176.08:02:20.45#ibcon#about to read 4, iclass 5, count 2 2006.176.08:02:20.45#ibcon#read 4, iclass 5, count 2 2006.176.08:02:20.45#ibcon#about to read 5, iclass 5, count 2 2006.176.08:02:20.45#ibcon#read 5, iclass 5, count 2 2006.176.08:02:20.45#ibcon#about to read 6, iclass 5, count 2 2006.176.08:02:20.45#ibcon#read 6, iclass 5, count 2 2006.176.08:02:20.45#ibcon#end of sib2, iclass 5, count 2 2006.176.08:02:20.45#ibcon#*after write, iclass 5, count 2 2006.176.08:02:20.45#ibcon#*before return 0, iclass 5, count 2 2006.176.08:02:20.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:02:20.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:02:20.45#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.176.08:02:20.45#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:20.45#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:02:20.56#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:02:20.56#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:02:20.56#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:02:20.56#ibcon#first serial, iclass 5, count 0 2006.176.08:02:20.56#ibcon#enter sib2, iclass 5, count 0 2006.176.08:02:20.56#ibcon#flushed, iclass 5, count 0 2006.176.08:02:20.56#ibcon#about to write, iclass 5, count 0 2006.176.08:02:20.56#ibcon#wrote, iclass 5, count 0 2006.176.08:02:20.56#ibcon#about to read 3, iclass 5, count 0 2006.176.08:02:20.58#ibcon#read 3, iclass 5, count 0 2006.176.08:02:20.58#ibcon#about to read 4, iclass 5, count 0 2006.176.08:02:20.58#ibcon#read 4, iclass 5, count 0 2006.176.08:02:20.58#ibcon#about to read 5, iclass 5, count 0 2006.176.08:02:20.58#ibcon#read 5, iclass 5, count 0 2006.176.08:02:20.58#ibcon#about to read 6, iclass 5, count 0 2006.176.08:02:20.58#ibcon#read 6, iclass 5, count 0 2006.176.08:02:20.58#ibcon#end of sib2, iclass 5, count 0 2006.176.08:02:20.58#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:02:20.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:02:20.58#ibcon#[25=USB\r\n] 2006.176.08:02:20.58#ibcon#*before write, iclass 5, count 0 2006.176.08:02:20.58#ibcon#enter sib2, iclass 5, count 0 2006.176.08:02:20.58#ibcon#flushed, iclass 5, count 0 2006.176.08:02:20.58#ibcon#about to write, iclass 5, count 0 2006.176.08:02:20.58#ibcon#wrote, iclass 5, count 0 2006.176.08:02:20.58#ibcon#about to read 3, iclass 5, count 0 2006.176.08:02:20.61#ibcon#read 3, iclass 5, count 0 2006.176.08:02:20.61#ibcon#about to read 4, iclass 5, count 0 2006.176.08:02:20.61#ibcon#read 4, iclass 5, count 0 2006.176.08:02:20.61#ibcon#about to read 5, iclass 5, count 0 2006.176.08:02:20.61#ibcon#read 5, iclass 5, count 0 2006.176.08:02:20.61#ibcon#about to read 6, iclass 5, count 0 2006.176.08:02:20.61#ibcon#read 6, iclass 5, count 0 2006.176.08:02:20.61#ibcon#end of sib2, iclass 5, count 0 2006.176.08:02:20.61#ibcon#*after write, iclass 5, count 0 2006.176.08:02:20.61#ibcon#*before return 0, iclass 5, count 0 2006.176.08:02:20.61#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:02:20.61#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:02:20.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:02:20.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:02:20.61$vc4f8/vblo=1,632.99 2006.176.08:02:20.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.08:02:20.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.08:02:20.61#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:20.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:02:20.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:02:20.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:02:20.61#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:02:20.61#ibcon#first serial, iclass 7, count 0 2006.176.08:02:20.61#ibcon#enter sib2, iclass 7, count 0 2006.176.08:02:20.61#ibcon#flushed, iclass 7, count 0 2006.176.08:02:20.61#ibcon#about to write, iclass 7, count 0 2006.176.08:02:20.61#ibcon#wrote, iclass 7, count 0 2006.176.08:02:20.61#ibcon#about to read 3, iclass 7, count 0 2006.176.08:02:20.63#ibcon#read 3, iclass 7, count 0 2006.176.08:02:20.63#ibcon#about to read 4, iclass 7, count 0 2006.176.08:02:20.63#ibcon#read 4, iclass 7, count 0 2006.176.08:02:20.63#ibcon#about to read 5, iclass 7, count 0 2006.176.08:02:20.63#ibcon#read 5, iclass 7, count 0 2006.176.08:02:20.63#ibcon#about to read 6, iclass 7, count 0 2006.176.08:02:20.63#ibcon#read 6, iclass 7, count 0 2006.176.08:02:20.63#ibcon#end of sib2, iclass 7, count 0 2006.176.08:02:20.63#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:02:20.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:02:20.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:02:20.63#ibcon#*before write, iclass 7, count 0 2006.176.08:02:20.63#ibcon#enter sib2, iclass 7, count 0 2006.176.08:02:20.63#ibcon#flushed, iclass 7, count 0 2006.176.08:02:20.63#ibcon#about to write, iclass 7, count 0 2006.176.08:02:20.63#ibcon#wrote, iclass 7, count 0 2006.176.08:02:20.63#ibcon#about to read 3, iclass 7, count 0 2006.176.08:02:20.67#ibcon#read 3, iclass 7, count 0 2006.176.08:02:20.67#ibcon#about to read 4, iclass 7, count 0 2006.176.08:02:20.67#ibcon#read 4, iclass 7, count 0 2006.176.08:02:20.67#ibcon#about to read 5, iclass 7, count 0 2006.176.08:02:20.67#ibcon#read 5, iclass 7, count 0 2006.176.08:02:20.67#ibcon#about to read 6, iclass 7, count 0 2006.176.08:02:20.67#ibcon#read 6, iclass 7, count 0 2006.176.08:02:20.67#ibcon#end of sib2, iclass 7, count 0 2006.176.08:02:20.67#ibcon#*after write, iclass 7, count 0 2006.176.08:02:20.67#ibcon#*before return 0, iclass 7, count 0 2006.176.08:02:20.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:02:20.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:02:20.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:02:20.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:02:20.67$vc4f8/vb=1,4 2006.176.08:02:20.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.176.08:02:20.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.176.08:02:20.67#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:20.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:02:20.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:02:20.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:02:20.67#ibcon#enter wrdev, iclass 11, count 2 2006.176.08:02:20.67#ibcon#first serial, iclass 11, count 2 2006.176.08:02:20.67#ibcon#enter sib2, iclass 11, count 2 2006.176.08:02:20.67#ibcon#flushed, iclass 11, count 2 2006.176.08:02:20.67#ibcon#about to write, iclass 11, count 2 2006.176.08:02:20.67#ibcon#wrote, iclass 11, count 2 2006.176.08:02:20.67#ibcon#about to read 3, iclass 11, count 2 2006.176.08:02:20.69#ibcon#read 3, iclass 11, count 2 2006.176.08:02:20.69#ibcon#about to read 4, iclass 11, count 2 2006.176.08:02:20.69#ibcon#read 4, iclass 11, count 2 2006.176.08:02:20.69#ibcon#about to read 5, iclass 11, count 2 2006.176.08:02:20.69#ibcon#read 5, iclass 11, count 2 2006.176.08:02:20.69#ibcon#about to read 6, iclass 11, count 2 2006.176.08:02:20.69#ibcon#read 6, iclass 11, count 2 2006.176.08:02:20.69#ibcon#end of sib2, iclass 11, count 2 2006.176.08:02:20.69#ibcon#*mode == 0, iclass 11, count 2 2006.176.08:02:20.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.176.08:02:20.69#ibcon#[27=AT01-04\r\n] 2006.176.08:02:20.69#ibcon#*before write, iclass 11, count 2 2006.176.08:02:20.69#ibcon#enter sib2, iclass 11, count 2 2006.176.08:02:20.69#ibcon#flushed, iclass 11, count 2 2006.176.08:02:20.69#ibcon#about to write, iclass 11, count 2 2006.176.08:02:20.69#ibcon#wrote, iclass 11, count 2 2006.176.08:02:20.69#ibcon#about to read 3, iclass 11, count 2 2006.176.08:02:20.72#ibcon#read 3, iclass 11, count 2 2006.176.08:02:20.72#ibcon#about to read 4, iclass 11, count 2 2006.176.08:02:20.72#ibcon#read 4, iclass 11, count 2 2006.176.08:02:20.72#ibcon#about to read 5, iclass 11, count 2 2006.176.08:02:20.72#ibcon#read 5, iclass 11, count 2 2006.176.08:02:20.72#ibcon#about to read 6, iclass 11, count 2 2006.176.08:02:20.72#ibcon#read 6, iclass 11, count 2 2006.176.08:02:20.72#ibcon#end of sib2, iclass 11, count 2 2006.176.08:02:20.72#ibcon#*after write, iclass 11, count 2 2006.176.08:02:20.72#ibcon#*before return 0, iclass 11, count 2 2006.176.08:02:20.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:02:20.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:02:20.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.176.08:02:20.72#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:20.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:02:20.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:02:20.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:02:20.84#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:02:20.84#ibcon#first serial, iclass 11, count 0 2006.176.08:02:20.84#ibcon#enter sib2, iclass 11, count 0 2006.176.08:02:20.84#ibcon#flushed, iclass 11, count 0 2006.176.08:02:20.84#ibcon#about to write, iclass 11, count 0 2006.176.08:02:20.84#ibcon#wrote, iclass 11, count 0 2006.176.08:02:20.84#ibcon#about to read 3, iclass 11, count 0 2006.176.08:02:20.86#ibcon#read 3, iclass 11, count 0 2006.176.08:02:20.86#ibcon#about to read 4, iclass 11, count 0 2006.176.08:02:20.86#ibcon#read 4, iclass 11, count 0 2006.176.08:02:20.86#ibcon#about to read 5, iclass 11, count 0 2006.176.08:02:20.86#ibcon#read 5, iclass 11, count 0 2006.176.08:02:20.86#ibcon#about to read 6, iclass 11, count 0 2006.176.08:02:20.86#ibcon#read 6, iclass 11, count 0 2006.176.08:02:20.86#ibcon#end of sib2, iclass 11, count 0 2006.176.08:02:20.86#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:02:20.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:02:20.86#ibcon#[27=USB\r\n] 2006.176.08:02:20.86#ibcon#*before write, iclass 11, count 0 2006.176.08:02:20.86#ibcon#enter sib2, iclass 11, count 0 2006.176.08:02:20.86#ibcon#flushed, iclass 11, count 0 2006.176.08:02:20.86#ibcon#about to write, iclass 11, count 0 2006.176.08:02:20.86#ibcon#wrote, iclass 11, count 0 2006.176.08:02:20.86#ibcon#about to read 3, iclass 11, count 0 2006.176.08:02:20.89#ibcon#read 3, iclass 11, count 0 2006.176.08:02:20.89#ibcon#about to read 4, iclass 11, count 0 2006.176.08:02:20.89#ibcon#read 4, iclass 11, count 0 2006.176.08:02:20.89#ibcon#about to read 5, iclass 11, count 0 2006.176.08:02:20.89#ibcon#read 5, iclass 11, count 0 2006.176.08:02:20.89#ibcon#about to read 6, iclass 11, count 0 2006.176.08:02:20.89#ibcon#read 6, iclass 11, count 0 2006.176.08:02:20.89#ibcon#end of sib2, iclass 11, count 0 2006.176.08:02:20.89#ibcon#*after write, iclass 11, count 0 2006.176.08:02:20.89#ibcon#*before return 0, iclass 11, count 0 2006.176.08:02:20.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:02:20.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:02:20.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:02:20.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:02:20.89$vc4f8/vblo=2,640.99 2006.176.08:02:20.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.08:02:20.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.08:02:20.89#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:20.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:20.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:20.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:20.89#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:02:20.89#ibcon#first serial, iclass 13, count 0 2006.176.08:02:20.89#ibcon#enter sib2, iclass 13, count 0 2006.176.08:02:20.89#ibcon#flushed, iclass 13, count 0 2006.176.08:02:20.89#ibcon#about to write, iclass 13, count 0 2006.176.08:02:20.89#ibcon#wrote, iclass 13, count 0 2006.176.08:02:20.89#ibcon#about to read 3, iclass 13, count 0 2006.176.08:02:20.91#ibcon#read 3, iclass 13, count 0 2006.176.08:02:20.91#ibcon#about to read 4, iclass 13, count 0 2006.176.08:02:20.91#ibcon#read 4, iclass 13, count 0 2006.176.08:02:20.91#ibcon#about to read 5, iclass 13, count 0 2006.176.08:02:20.91#ibcon#read 5, iclass 13, count 0 2006.176.08:02:20.91#ibcon#about to read 6, iclass 13, count 0 2006.176.08:02:20.91#ibcon#read 6, iclass 13, count 0 2006.176.08:02:20.91#ibcon#end of sib2, iclass 13, count 0 2006.176.08:02:20.91#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:02:20.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:02:20.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:02:20.91#ibcon#*before write, iclass 13, count 0 2006.176.08:02:20.91#ibcon#enter sib2, iclass 13, count 0 2006.176.08:02:20.91#ibcon#flushed, iclass 13, count 0 2006.176.08:02:20.91#ibcon#about to write, iclass 13, count 0 2006.176.08:02:20.91#ibcon#wrote, iclass 13, count 0 2006.176.08:02:20.91#ibcon#about to read 3, iclass 13, count 0 2006.176.08:02:20.95#ibcon#read 3, iclass 13, count 0 2006.176.08:02:20.95#ibcon#about to read 4, iclass 13, count 0 2006.176.08:02:20.95#ibcon#read 4, iclass 13, count 0 2006.176.08:02:20.95#ibcon#about to read 5, iclass 13, count 0 2006.176.08:02:20.95#ibcon#read 5, iclass 13, count 0 2006.176.08:02:20.95#ibcon#about to read 6, iclass 13, count 0 2006.176.08:02:20.95#ibcon#read 6, iclass 13, count 0 2006.176.08:02:20.95#ibcon#end of sib2, iclass 13, count 0 2006.176.08:02:20.95#ibcon#*after write, iclass 13, count 0 2006.176.08:02:20.95#ibcon#*before return 0, iclass 13, count 0 2006.176.08:02:20.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:20.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:02:20.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:02:20.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:02:20.95$vc4f8/vb=2,4 2006.176.08:02:20.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.176.08:02:20.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.176.08:02:20.95#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:20.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:21.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:21.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:21.01#ibcon#enter wrdev, iclass 15, count 2 2006.176.08:02:21.01#ibcon#first serial, iclass 15, count 2 2006.176.08:02:21.01#ibcon#enter sib2, iclass 15, count 2 2006.176.08:02:21.01#ibcon#flushed, iclass 15, count 2 2006.176.08:02:21.01#ibcon#about to write, iclass 15, count 2 2006.176.08:02:21.01#ibcon#wrote, iclass 15, count 2 2006.176.08:02:21.01#ibcon#about to read 3, iclass 15, count 2 2006.176.08:02:21.03#ibcon#read 3, iclass 15, count 2 2006.176.08:02:21.03#ibcon#about to read 4, iclass 15, count 2 2006.176.08:02:21.03#ibcon#read 4, iclass 15, count 2 2006.176.08:02:21.03#ibcon#about to read 5, iclass 15, count 2 2006.176.08:02:21.03#ibcon#read 5, iclass 15, count 2 2006.176.08:02:21.03#ibcon#about to read 6, iclass 15, count 2 2006.176.08:02:21.03#ibcon#read 6, iclass 15, count 2 2006.176.08:02:21.03#ibcon#end of sib2, iclass 15, count 2 2006.176.08:02:21.03#ibcon#*mode == 0, iclass 15, count 2 2006.176.08:02:21.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.176.08:02:21.03#ibcon#[27=AT02-04\r\n] 2006.176.08:02:21.03#ibcon#*before write, iclass 15, count 2 2006.176.08:02:21.03#ibcon#enter sib2, iclass 15, count 2 2006.176.08:02:21.03#ibcon#flushed, iclass 15, count 2 2006.176.08:02:21.03#ibcon#about to write, iclass 15, count 2 2006.176.08:02:21.03#ibcon#wrote, iclass 15, count 2 2006.176.08:02:21.03#ibcon#about to read 3, iclass 15, count 2 2006.176.08:02:21.06#ibcon#read 3, iclass 15, count 2 2006.176.08:02:21.06#ibcon#about to read 4, iclass 15, count 2 2006.176.08:02:21.06#ibcon#read 4, iclass 15, count 2 2006.176.08:02:21.06#ibcon#about to read 5, iclass 15, count 2 2006.176.08:02:21.06#ibcon#read 5, iclass 15, count 2 2006.176.08:02:21.06#ibcon#about to read 6, iclass 15, count 2 2006.176.08:02:21.06#ibcon#read 6, iclass 15, count 2 2006.176.08:02:21.06#ibcon#end of sib2, iclass 15, count 2 2006.176.08:02:21.06#ibcon#*after write, iclass 15, count 2 2006.176.08:02:21.06#ibcon#*before return 0, iclass 15, count 2 2006.176.08:02:21.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:21.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:02:21.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.176.08:02:21.06#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:21.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:21.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:21.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:21.18#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:02:21.18#ibcon#first serial, iclass 15, count 0 2006.176.08:02:21.18#ibcon#enter sib2, iclass 15, count 0 2006.176.08:02:21.18#ibcon#flushed, iclass 15, count 0 2006.176.08:02:21.18#ibcon#about to write, iclass 15, count 0 2006.176.08:02:21.18#ibcon#wrote, iclass 15, count 0 2006.176.08:02:21.18#ibcon#about to read 3, iclass 15, count 0 2006.176.08:02:21.20#ibcon#read 3, iclass 15, count 0 2006.176.08:02:21.20#ibcon#about to read 4, iclass 15, count 0 2006.176.08:02:21.20#ibcon#read 4, iclass 15, count 0 2006.176.08:02:21.20#ibcon#about to read 5, iclass 15, count 0 2006.176.08:02:21.20#ibcon#read 5, iclass 15, count 0 2006.176.08:02:21.20#ibcon#about to read 6, iclass 15, count 0 2006.176.08:02:21.20#ibcon#read 6, iclass 15, count 0 2006.176.08:02:21.20#ibcon#end of sib2, iclass 15, count 0 2006.176.08:02:21.20#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:02:21.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:02:21.20#ibcon#[27=USB\r\n] 2006.176.08:02:21.20#ibcon#*before write, iclass 15, count 0 2006.176.08:02:21.20#ibcon#enter sib2, iclass 15, count 0 2006.176.08:02:21.20#ibcon#flushed, iclass 15, count 0 2006.176.08:02:21.20#ibcon#about to write, iclass 15, count 0 2006.176.08:02:21.20#ibcon#wrote, iclass 15, count 0 2006.176.08:02:21.20#ibcon#about to read 3, iclass 15, count 0 2006.176.08:02:21.23#ibcon#read 3, iclass 15, count 0 2006.176.08:02:21.23#ibcon#about to read 4, iclass 15, count 0 2006.176.08:02:21.23#ibcon#read 4, iclass 15, count 0 2006.176.08:02:21.23#ibcon#about to read 5, iclass 15, count 0 2006.176.08:02:21.23#ibcon#read 5, iclass 15, count 0 2006.176.08:02:21.23#ibcon#about to read 6, iclass 15, count 0 2006.176.08:02:21.23#ibcon#read 6, iclass 15, count 0 2006.176.08:02:21.23#ibcon#end of sib2, iclass 15, count 0 2006.176.08:02:21.23#ibcon#*after write, iclass 15, count 0 2006.176.08:02:21.23#ibcon#*before return 0, iclass 15, count 0 2006.176.08:02:21.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:21.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:02:21.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:02:21.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:02:21.23$vc4f8/vblo=3,656.99 2006.176.08:02:21.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.08:02:21.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.08:02:21.23#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:21.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:21.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:21.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:21.23#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:02:21.23#ibcon#first serial, iclass 17, count 0 2006.176.08:02:21.23#ibcon#enter sib2, iclass 17, count 0 2006.176.08:02:21.23#ibcon#flushed, iclass 17, count 0 2006.176.08:02:21.23#ibcon#about to write, iclass 17, count 0 2006.176.08:02:21.23#ibcon#wrote, iclass 17, count 0 2006.176.08:02:21.23#ibcon#about to read 3, iclass 17, count 0 2006.176.08:02:21.25#ibcon#read 3, iclass 17, count 0 2006.176.08:02:21.25#ibcon#about to read 4, iclass 17, count 0 2006.176.08:02:21.25#ibcon#read 4, iclass 17, count 0 2006.176.08:02:21.25#ibcon#about to read 5, iclass 17, count 0 2006.176.08:02:21.25#ibcon#read 5, iclass 17, count 0 2006.176.08:02:21.25#ibcon#about to read 6, iclass 17, count 0 2006.176.08:02:21.25#ibcon#read 6, iclass 17, count 0 2006.176.08:02:21.25#ibcon#end of sib2, iclass 17, count 0 2006.176.08:02:21.25#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:02:21.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:02:21.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:02:21.25#ibcon#*before write, iclass 17, count 0 2006.176.08:02:21.25#ibcon#enter sib2, iclass 17, count 0 2006.176.08:02:21.25#ibcon#flushed, iclass 17, count 0 2006.176.08:02:21.25#ibcon#about to write, iclass 17, count 0 2006.176.08:02:21.25#ibcon#wrote, iclass 17, count 0 2006.176.08:02:21.25#ibcon#about to read 3, iclass 17, count 0 2006.176.08:02:21.29#ibcon#read 3, iclass 17, count 0 2006.176.08:02:21.29#ibcon#about to read 4, iclass 17, count 0 2006.176.08:02:21.29#ibcon#read 4, iclass 17, count 0 2006.176.08:02:21.29#ibcon#about to read 5, iclass 17, count 0 2006.176.08:02:21.29#ibcon#read 5, iclass 17, count 0 2006.176.08:02:21.29#ibcon#about to read 6, iclass 17, count 0 2006.176.08:02:21.29#ibcon#read 6, iclass 17, count 0 2006.176.08:02:21.29#ibcon#end of sib2, iclass 17, count 0 2006.176.08:02:21.29#ibcon#*after write, iclass 17, count 0 2006.176.08:02:21.29#ibcon#*before return 0, iclass 17, count 0 2006.176.08:02:21.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:21.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:02:21.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:02:21.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:02:21.29$vc4f8/vb=3,4 2006.176.08:02:21.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.176.08:02:21.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.176.08:02:21.29#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:21.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:21.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:21.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:21.35#ibcon#enter wrdev, iclass 19, count 2 2006.176.08:02:21.35#ibcon#first serial, iclass 19, count 2 2006.176.08:02:21.35#ibcon#enter sib2, iclass 19, count 2 2006.176.08:02:21.35#ibcon#flushed, iclass 19, count 2 2006.176.08:02:21.35#ibcon#about to write, iclass 19, count 2 2006.176.08:02:21.35#ibcon#wrote, iclass 19, count 2 2006.176.08:02:21.35#ibcon#about to read 3, iclass 19, count 2 2006.176.08:02:21.37#ibcon#read 3, iclass 19, count 2 2006.176.08:02:21.37#ibcon#about to read 4, iclass 19, count 2 2006.176.08:02:21.37#ibcon#read 4, iclass 19, count 2 2006.176.08:02:21.37#ibcon#about to read 5, iclass 19, count 2 2006.176.08:02:21.37#ibcon#read 5, iclass 19, count 2 2006.176.08:02:21.37#ibcon#about to read 6, iclass 19, count 2 2006.176.08:02:21.37#ibcon#read 6, iclass 19, count 2 2006.176.08:02:21.37#ibcon#end of sib2, iclass 19, count 2 2006.176.08:02:21.37#ibcon#*mode == 0, iclass 19, count 2 2006.176.08:02:21.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.176.08:02:21.37#ibcon#[27=AT03-04\r\n] 2006.176.08:02:21.37#ibcon#*before write, iclass 19, count 2 2006.176.08:02:21.37#ibcon#enter sib2, iclass 19, count 2 2006.176.08:02:21.37#ibcon#flushed, iclass 19, count 2 2006.176.08:02:21.37#ibcon#about to write, iclass 19, count 2 2006.176.08:02:21.37#ibcon#wrote, iclass 19, count 2 2006.176.08:02:21.37#ibcon#about to read 3, iclass 19, count 2 2006.176.08:02:21.40#ibcon#read 3, iclass 19, count 2 2006.176.08:02:21.40#ibcon#about to read 4, iclass 19, count 2 2006.176.08:02:21.40#ibcon#read 4, iclass 19, count 2 2006.176.08:02:21.40#ibcon#about to read 5, iclass 19, count 2 2006.176.08:02:21.40#ibcon#read 5, iclass 19, count 2 2006.176.08:02:21.40#ibcon#about to read 6, iclass 19, count 2 2006.176.08:02:21.40#ibcon#read 6, iclass 19, count 2 2006.176.08:02:21.40#ibcon#end of sib2, iclass 19, count 2 2006.176.08:02:21.40#ibcon#*after write, iclass 19, count 2 2006.176.08:02:21.40#ibcon#*before return 0, iclass 19, count 2 2006.176.08:02:21.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:21.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:02:21.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.176.08:02:21.40#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:21.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:21.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:21.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:21.52#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:02:21.52#ibcon#first serial, iclass 19, count 0 2006.176.08:02:21.52#ibcon#enter sib2, iclass 19, count 0 2006.176.08:02:21.52#ibcon#flushed, iclass 19, count 0 2006.176.08:02:21.52#ibcon#about to write, iclass 19, count 0 2006.176.08:02:21.52#ibcon#wrote, iclass 19, count 0 2006.176.08:02:21.52#ibcon#about to read 3, iclass 19, count 0 2006.176.08:02:21.54#ibcon#read 3, iclass 19, count 0 2006.176.08:02:21.54#ibcon#about to read 4, iclass 19, count 0 2006.176.08:02:21.54#ibcon#read 4, iclass 19, count 0 2006.176.08:02:21.54#ibcon#about to read 5, iclass 19, count 0 2006.176.08:02:21.54#ibcon#read 5, iclass 19, count 0 2006.176.08:02:21.54#ibcon#about to read 6, iclass 19, count 0 2006.176.08:02:21.54#ibcon#read 6, iclass 19, count 0 2006.176.08:02:21.54#ibcon#end of sib2, iclass 19, count 0 2006.176.08:02:21.54#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:02:21.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:02:21.54#ibcon#[27=USB\r\n] 2006.176.08:02:21.54#ibcon#*before write, iclass 19, count 0 2006.176.08:02:21.54#ibcon#enter sib2, iclass 19, count 0 2006.176.08:02:21.54#ibcon#flushed, iclass 19, count 0 2006.176.08:02:21.54#ibcon#about to write, iclass 19, count 0 2006.176.08:02:21.54#ibcon#wrote, iclass 19, count 0 2006.176.08:02:21.54#ibcon#about to read 3, iclass 19, count 0 2006.176.08:02:21.57#ibcon#read 3, iclass 19, count 0 2006.176.08:02:21.57#ibcon#about to read 4, iclass 19, count 0 2006.176.08:02:21.57#ibcon#read 4, iclass 19, count 0 2006.176.08:02:21.57#ibcon#about to read 5, iclass 19, count 0 2006.176.08:02:21.57#ibcon#read 5, iclass 19, count 0 2006.176.08:02:21.57#ibcon#about to read 6, iclass 19, count 0 2006.176.08:02:21.57#ibcon#read 6, iclass 19, count 0 2006.176.08:02:21.57#ibcon#end of sib2, iclass 19, count 0 2006.176.08:02:21.57#ibcon#*after write, iclass 19, count 0 2006.176.08:02:21.57#ibcon#*before return 0, iclass 19, count 0 2006.176.08:02:21.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:21.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:02:21.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:02:21.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:02:21.57$vc4f8/vblo=4,712.99 2006.176.08:02:21.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.08:02:21.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.08:02:21.57#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:21.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:21.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:21.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:21.57#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:02:21.57#ibcon#first serial, iclass 21, count 0 2006.176.08:02:21.57#ibcon#enter sib2, iclass 21, count 0 2006.176.08:02:21.57#ibcon#flushed, iclass 21, count 0 2006.176.08:02:21.57#ibcon#about to write, iclass 21, count 0 2006.176.08:02:21.57#ibcon#wrote, iclass 21, count 0 2006.176.08:02:21.57#ibcon#about to read 3, iclass 21, count 0 2006.176.08:02:21.59#ibcon#read 3, iclass 21, count 0 2006.176.08:02:21.59#ibcon#about to read 4, iclass 21, count 0 2006.176.08:02:21.59#ibcon#read 4, iclass 21, count 0 2006.176.08:02:21.59#ibcon#about to read 5, iclass 21, count 0 2006.176.08:02:21.59#ibcon#read 5, iclass 21, count 0 2006.176.08:02:21.59#ibcon#about to read 6, iclass 21, count 0 2006.176.08:02:21.59#ibcon#read 6, iclass 21, count 0 2006.176.08:02:21.59#ibcon#end of sib2, iclass 21, count 0 2006.176.08:02:21.59#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:02:21.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:02:21.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:02:21.59#ibcon#*before write, iclass 21, count 0 2006.176.08:02:21.59#ibcon#enter sib2, iclass 21, count 0 2006.176.08:02:21.59#ibcon#flushed, iclass 21, count 0 2006.176.08:02:21.59#ibcon#about to write, iclass 21, count 0 2006.176.08:02:21.59#ibcon#wrote, iclass 21, count 0 2006.176.08:02:21.59#ibcon#about to read 3, iclass 21, count 0 2006.176.08:02:21.63#ibcon#read 3, iclass 21, count 0 2006.176.08:02:21.63#ibcon#about to read 4, iclass 21, count 0 2006.176.08:02:21.63#ibcon#read 4, iclass 21, count 0 2006.176.08:02:21.63#ibcon#about to read 5, iclass 21, count 0 2006.176.08:02:21.63#ibcon#read 5, iclass 21, count 0 2006.176.08:02:21.63#ibcon#about to read 6, iclass 21, count 0 2006.176.08:02:21.63#ibcon#read 6, iclass 21, count 0 2006.176.08:02:21.63#ibcon#end of sib2, iclass 21, count 0 2006.176.08:02:21.63#ibcon#*after write, iclass 21, count 0 2006.176.08:02:21.63#ibcon#*before return 0, iclass 21, count 0 2006.176.08:02:21.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:21.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:02:21.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:02:21.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:02:21.63$vc4f8/vb=4,4 2006.176.08:02:21.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.08:02:21.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.08:02:21.63#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:21.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:21.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:21.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:21.69#ibcon#enter wrdev, iclass 23, count 2 2006.176.08:02:21.69#ibcon#first serial, iclass 23, count 2 2006.176.08:02:21.69#ibcon#enter sib2, iclass 23, count 2 2006.176.08:02:21.69#ibcon#flushed, iclass 23, count 2 2006.176.08:02:21.69#ibcon#about to write, iclass 23, count 2 2006.176.08:02:21.69#ibcon#wrote, iclass 23, count 2 2006.176.08:02:21.69#ibcon#about to read 3, iclass 23, count 2 2006.176.08:02:21.71#ibcon#read 3, iclass 23, count 2 2006.176.08:02:21.71#ibcon#about to read 4, iclass 23, count 2 2006.176.08:02:21.71#ibcon#read 4, iclass 23, count 2 2006.176.08:02:21.71#ibcon#about to read 5, iclass 23, count 2 2006.176.08:02:21.71#ibcon#read 5, iclass 23, count 2 2006.176.08:02:21.71#ibcon#about to read 6, iclass 23, count 2 2006.176.08:02:21.71#ibcon#read 6, iclass 23, count 2 2006.176.08:02:21.71#ibcon#end of sib2, iclass 23, count 2 2006.176.08:02:21.71#ibcon#*mode == 0, iclass 23, count 2 2006.176.08:02:21.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.08:02:21.71#ibcon#[27=AT04-04\r\n] 2006.176.08:02:21.71#ibcon#*before write, iclass 23, count 2 2006.176.08:02:21.71#ibcon#enter sib2, iclass 23, count 2 2006.176.08:02:21.71#ibcon#flushed, iclass 23, count 2 2006.176.08:02:21.71#ibcon#about to write, iclass 23, count 2 2006.176.08:02:21.71#ibcon#wrote, iclass 23, count 2 2006.176.08:02:21.71#ibcon#about to read 3, iclass 23, count 2 2006.176.08:02:21.74#ibcon#read 3, iclass 23, count 2 2006.176.08:02:21.74#ibcon#about to read 4, iclass 23, count 2 2006.176.08:02:21.74#ibcon#read 4, iclass 23, count 2 2006.176.08:02:21.74#ibcon#about to read 5, iclass 23, count 2 2006.176.08:02:21.74#ibcon#read 5, iclass 23, count 2 2006.176.08:02:21.74#ibcon#about to read 6, iclass 23, count 2 2006.176.08:02:21.74#ibcon#read 6, iclass 23, count 2 2006.176.08:02:21.74#ibcon#end of sib2, iclass 23, count 2 2006.176.08:02:21.74#ibcon#*after write, iclass 23, count 2 2006.176.08:02:21.74#ibcon#*before return 0, iclass 23, count 2 2006.176.08:02:21.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:21.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:02:21.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.08:02:21.74#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:21.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:21.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:21.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:21.86#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:02:21.86#ibcon#first serial, iclass 23, count 0 2006.176.08:02:21.86#ibcon#enter sib2, iclass 23, count 0 2006.176.08:02:21.86#ibcon#flushed, iclass 23, count 0 2006.176.08:02:21.86#ibcon#about to write, iclass 23, count 0 2006.176.08:02:21.86#ibcon#wrote, iclass 23, count 0 2006.176.08:02:21.86#ibcon#about to read 3, iclass 23, count 0 2006.176.08:02:21.88#ibcon#read 3, iclass 23, count 0 2006.176.08:02:21.88#ibcon#about to read 4, iclass 23, count 0 2006.176.08:02:21.88#ibcon#read 4, iclass 23, count 0 2006.176.08:02:21.88#ibcon#about to read 5, iclass 23, count 0 2006.176.08:02:21.88#ibcon#read 5, iclass 23, count 0 2006.176.08:02:21.88#ibcon#about to read 6, iclass 23, count 0 2006.176.08:02:21.88#ibcon#read 6, iclass 23, count 0 2006.176.08:02:21.88#ibcon#end of sib2, iclass 23, count 0 2006.176.08:02:21.88#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:02:21.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:02:21.88#ibcon#[27=USB\r\n] 2006.176.08:02:21.88#ibcon#*before write, iclass 23, count 0 2006.176.08:02:21.88#ibcon#enter sib2, iclass 23, count 0 2006.176.08:02:21.88#ibcon#flushed, iclass 23, count 0 2006.176.08:02:21.88#ibcon#about to write, iclass 23, count 0 2006.176.08:02:21.88#ibcon#wrote, iclass 23, count 0 2006.176.08:02:21.88#ibcon#about to read 3, iclass 23, count 0 2006.176.08:02:21.91#ibcon#read 3, iclass 23, count 0 2006.176.08:02:21.91#ibcon#about to read 4, iclass 23, count 0 2006.176.08:02:21.91#ibcon#read 4, iclass 23, count 0 2006.176.08:02:21.91#ibcon#about to read 5, iclass 23, count 0 2006.176.08:02:21.91#ibcon#read 5, iclass 23, count 0 2006.176.08:02:21.91#ibcon#about to read 6, iclass 23, count 0 2006.176.08:02:21.91#ibcon#read 6, iclass 23, count 0 2006.176.08:02:21.91#ibcon#end of sib2, iclass 23, count 0 2006.176.08:02:21.91#ibcon#*after write, iclass 23, count 0 2006.176.08:02:21.91#ibcon#*before return 0, iclass 23, count 0 2006.176.08:02:21.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:21.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:02:21.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:02:21.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:02:21.91$vc4f8/vblo=5,744.99 2006.176.08:02:21.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.08:02:21.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.08:02:21.91#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:21.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:21.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:21.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:21.91#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:02:21.91#ibcon#first serial, iclass 25, count 0 2006.176.08:02:21.91#ibcon#enter sib2, iclass 25, count 0 2006.176.08:02:21.91#ibcon#flushed, iclass 25, count 0 2006.176.08:02:21.91#ibcon#about to write, iclass 25, count 0 2006.176.08:02:21.91#ibcon#wrote, iclass 25, count 0 2006.176.08:02:21.91#ibcon#about to read 3, iclass 25, count 0 2006.176.08:02:21.93#ibcon#read 3, iclass 25, count 0 2006.176.08:02:21.93#ibcon#about to read 4, iclass 25, count 0 2006.176.08:02:21.93#ibcon#read 4, iclass 25, count 0 2006.176.08:02:21.93#ibcon#about to read 5, iclass 25, count 0 2006.176.08:02:21.93#ibcon#read 5, iclass 25, count 0 2006.176.08:02:21.93#ibcon#about to read 6, iclass 25, count 0 2006.176.08:02:21.93#ibcon#read 6, iclass 25, count 0 2006.176.08:02:21.93#ibcon#end of sib2, iclass 25, count 0 2006.176.08:02:21.93#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:02:21.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:02:21.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:02:21.93#ibcon#*before write, iclass 25, count 0 2006.176.08:02:21.93#ibcon#enter sib2, iclass 25, count 0 2006.176.08:02:21.93#ibcon#flushed, iclass 25, count 0 2006.176.08:02:21.93#ibcon#about to write, iclass 25, count 0 2006.176.08:02:21.93#ibcon#wrote, iclass 25, count 0 2006.176.08:02:21.93#ibcon#about to read 3, iclass 25, count 0 2006.176.08:02:21.97#ibcon#read 3, iclass 25, count 0 2006.176.08:02:21.97#ibcon#about to read 4, iclass 25, count 0 2006.176.08:02:21.97#ibcon#read 4, iclass 25, count 0 2006.176.08:02:21.97#ibcon#about to read 5, iclass 25, count 0 2006.176.08:02:21.97#ibcon#read 5, iclass 25, count 0 2006.176.08:02:21.97#ibcon#about to read 6, iclass 25, count 0 2006.176.08:02:21.97#ibcon#read 6, iclass 25, count 0 2006.176.08:02:21.97#ibcon#end of sib2, iclass 25, count 0 2006.176.08:02:21.97#ibcon#*after write, iclass 25, count 0 2006.176.08:02:21.97#ibcon#*before return 0, iclass 25, count 0 2006.176.08:02:21.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:21.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:02:21.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:02:21.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:02:21.97$vc4f8/vb=5,4 2006.176.08:02:21.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.08:02:21.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.08:02:21.97#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:21.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:22.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:22.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:22.03#ibcon#enter wrdev, iclass 27, count 2 2006.176.08:02:22.03#ibcon#first serial, iclass 27, count 2 2006.176.08:02:22.03#ibcon#enter sib2, iclass 27, count 2 2006.176.08:02:22.03#ibcon#flushed, iclass 27, count 2 2006.176.08:02:22.03#ibcon#about to write, iclass 27, count 2 2006.176.08:02:22.03#ibcon#wrote, iclass 27, count 2 2006.176.08:02:22.03#ibcon#about to read 3, iclass 27, count 2 2006.176.08:02:22.05#ibcon#read 3, iclass 27, count 2 2006.176.08:02:22.05#ibcon#about to read 4, iclass 27, count 2 2006.176.08:02:22.05#ibcon#read 4, iclass 27, count 2 2006.176.08:02:22.05#ibcon#about to read 5, iclass 27, count 2 2006.176.08:02:22.05#ibcon#read 5, iclass 27, count 2 2006.176.08:02:22.05#ibcon#about to read 6, iclass 27, count 2 2006.176.08:02:22.05#ibcon#read 6, iclass 27, count 2 2006.176.08:02:22.05#ibcon#end of sib2, iclass 27, count 2 2006.176.08:02:22.05#ibcon#*mode == 0, iclass 27, count 2 2006.176.08:02:22.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.08:02:22.05#ibcon#[27=AT05-04\r\n] 2006.176.08:02:22.05#ibcon#*before write, iclass 27, count 2 2006.176.08:02:22.05#ibcon#enter sib2, iclass 27, count 2 2006.176.08:02:22.05#ibcon#flushed, iclass 27, count 2 2006.176.08:02:22.05#ibcon#about to write, iclass 27, count 2 2006.176.08:02:22.05#ibcon#wrote, iclass 27, count 2 2006.176.08:02:22.05#ibcon#about to read 3, iclass 27, count 2 2006.176.08:02:22.08#ibcon#read 3, iclass 27, count 2 2006.176.08:02:22.08#ibcon#about to read 4, iclass 27, count 2 2006.176.08:02:22.08#ibcon#read 4, iclass 27, count 2 2006.176.08:02:22.08#ibcon#about to read 5, iclass 27, count 2 2006.176.08:02:22.08#ibcon#read 5, iclass 27, count 2 2006.176.08:02:22.08#ibcon#about to read 6, iclass 27, count 2 2006.176.08:02:22.08#ibcon#read 6, iclass 27, count 2 2006.176.08:02:22.08#ibcon#end of sib2, iclass 27, count 2 2006.176.08:02:22.08#ibcon#*after write, iclass 27, count 2 2006.176.08:02:22.08#ibcon#*before return 0, iclass 27, count 2 2006.176.08:02:22.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:22.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:02:22.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.08:02:22.08#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:22.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:22.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:22.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:22.20#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:02:22.20#ibcon#first serial, iclass 27, count 0 2006.176.08:02:22.20#ibcon#enter sib2, iclass 27, count 0 2006.176.08:02:22.20#ibcon#flushed, iclass 27, count 0 2006.176.08:02:22.20#ibcon#about to write, iclass 27, count 0 2006.176.08:02:22.20#ibcon#wrote, iclass 27, count 0 2006.176.08:02:22.20#ibcon#about to read 3, iclass 27, count 0 2006.176.08:02:22.22#ibcon#read 3, iclass 27, count 0 2006.176.08:02:22.22#ibcon#about to read 4, iclass 27, count 0 2006.176.08:02:22.22#ibcon#read 4, iclass 27, count 0 2006.176.08:02:22.22#ibcon#about to read 5, iclass 27, count 0 2006.176.08:02:22.22#ibcon#read 5, iclass 27, count 0 2006.176.08:02:22.22#ibcon#about to read 6, iclass 27, count 0 2006.176.08:02:22.22#ibcon#read 6, iclass 27, count 0 2006.176.08:02:22.22#ibcon#end of sib2, iclass 27, count 0 2006.176.08:02:22.22#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:02:22.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:02:22.22#ibcon#[27=USB\r\n] 2006.176.08:02:22.22#ibcon#*before write, iclass 27, count 0 2006.176.08:02:22.22#ibcon#enter sib2, iclass 27, count 0 2006.176.08:02:22.22#ibcon#flushed, iclass 27, count 0 2006.176.08:02:22.22#ibcon#about to write, iclass 27, count 0 2006.176.08:02:22.22#ibcon#wrote, iclass 27, count 0 2006.176.08:02:22.22#ibcon#about to read 3, iclass 27, count 0 2006.176.08:02:22.25#ibcon#read 3, iclass 27, count 0 2006.176.08:02:22.25#ibcon#about to read 4, iclass 27, count 0 2006.176.08:02:22.25#ibcon#read 4, iclass 27, count 0 2006.176.08:02:22.25#ibcon#about to read 5, iclass 27, count 0 2006.176.08:02:22.25#ibcon#read 5, iclass 27, count 0 2006.176.08:02:22.25#ibcon#about to read 6, iclass 27, count 0 2006.176.08:02:22.25#ibcon#read 6, iclass 27, count 0 2006.176.08:02:22.25#ibcon#end of sib2, iclass 27, count 0 2006.176.08:02:22.25#ibcon#*after write, iclass 27, count 0 2006.176.08:02:22.25#ibcon#*before return 0, iclass 27, count 0 2006.176.08:02:22.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:22.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:02:22.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:02:22.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:02:22.25$vc4f8/vblo=6,752.99 2006.176.08:02:22.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.08:02:22.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.08:02:22.25#ibcon#ireg 17 cls_cnt 0 2006.176.08:02:22.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:22.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:22.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:22.25#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:02:22.25#ibcon#first serial, iclass 29, count 0 2006.176.08:02:22.25#ibcon#enter sib2, iclass 29, count 0 2006.176.08:02:22.25#ibcon#flushed, iclass 29, count 0 2006.176.08:02:22.25#ibcon#about to write, iclass 29, count 0 2006.176.08:02:22.25#ibcon#wrote, iclass 29, count 0 2006.176.08:02:22.25#ibcon#about to read 3, iclass 29, count 0 2006.176.08:02:22.27#ibcon#read 3, iclass 29, count 0 2006.176.08:02:22.27#ibcon#about to read 4, iclass 29, count 0 2006.176.08:02:22.27#ibcon#read 4, iclass 29, count 0 2006.176.08:02:22.27#ibcon#about to read 5, iclass 29, count 0 2006.176.08:02:22.27#ibcon#read 5, iclass 29, count 0 2006.176.08:02:22.27#ibcon#about to read 6, iclass 29, count 0 2006.176.08:02:22.27#ibcon#read 6, iclass 29, count 0 2006.176.08:02:22.27#ibcon#end of sib2, iclass 29, count 0 2006.176.08:02:22.27#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:02:22.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:02:22.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:02:22.27#ibcon#*before write, iclass 29, count 0 2006.176.08:02:22.27#ibcon#enter sib2, iclass 29, count 0 2006.176.08:02:22.27#ibcon#flushed, iclass 29, count 0 2006.176.08:02:22.27#ibcon#about to write, iclass 29, count 0 2006.176.08:02:22.27#ibcon#wrote, iclass 29, count 0 2006.176.08:02:22.27#ibcon#about to read 3, iclass 29, count 0 2006.176.08:02:22.31#ibcon#read 3, iclass 29, count 0 2006.176.08:02:22.31#ibcon#about to read 4, iclass 29, count 0 2006.176.08:02:22.31#ibcon#read 4, iclass 29, count 0 2006.176.08:02:22.31#ibcon#about to read 5, iclass 29, count 0 2006.176.08:02:22.31#ibcon#read 5, iclass 29, count 0 2006.176.08:02:22.31#ibcon#about to read 6, iclass 29, count 0 2006.176.08:02:22.31#ibcon#read 6, iclass 29, count 0 2006.176.08:02:22.31#ibcon#end of sib2, iclass 29, count 0 2006.176.08:02:22.31#ibcon#*after write, iclass 29, count 0 2006.176.08:02:22.31#ibcon#*before return 0, iclass 29, count 0 2006.176.08:02:22.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:22.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:02:22.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:02:22.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:02:22.31$vc4f8/vb=6,4 2006.176.08:02:22.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.08:02:22.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.08:02:22.31#ibcon#ireg 11 cls_cnt 2 2006.176.08:02:22.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:22.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:22.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:22.37#ibcon#enter wrdev, iclass 31, count 2 2006.176.08:02:22.37#ibcon#first serial, iclass 31, count 2 2006.176.08:02:22.37#ibcon#enter sib2, iclass 31, count 2 2006.176.08:02:22.37#ibcon#flushed, iclass 31, count 2 2006.176.08:02:22.37#ibcon#about to write, iclass 31, count 2 2006.176.08:02:22.37#ibcon#wrote, iclass 31, count 2 2006.176.08:02:22.37#ibcon#about to read 3, iclass 31, count 2 2006.176.08:02:22.39#ibcon#read 3, iclass 31, count 2 2006.176.08:02:22.39#ibcon#about to read 4, iclass 31, count 2 2006.176.08:02:22.39#ibcon#read 4, iclass 31, count 2 2006.176.08:02:22.39#ibcon#about to read 5, iclass 31, count 2 2006.176.08:02:22.39#ibcon#read 5, iclass 31, count 2 2006.176.08:02:22.39#ibcon#about to read 6, iclass 31, count 2 2006.176.08:02:22.39#ibcon#read 6, iclass 31, count 2 2006.176.08:02:22.39#ibcon#end of sib2, iclass 31, count 2 2006.176.08:02:22.39#ibcon#*mode == 0, iclass 31, count 2 2006.176.08:02:22.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.08:02:22.39#ibcon#[27=AT06-04\r\n] 2006.176.08:02:22.39#ibcon#*before write, iclass 31, count 2 2006.176.08:02:22.39#ibcon#enter sib2, iclass 31, count 2 2006.176.08:02:22.39#ibcon#flushed, iclass 31, count 2 2006.176.08:02:22.39#ibcon#about to write, iclass 31, count 2 2006.176.08:02:22.39#ibcon#wrote, iclass 31, count 2 2006.176.08:02:22.39#ibcon#about to read 3, iclass 31, count 2 2006.176.08:02:22.42#ibcon#read 3, iclass 31, count 2 2006.176.08:02:22.42#ibcon#about to read 4, iclass 31, count 2 2006.176.08:02:22.42#ibcon#read 4, iclass 31, count 2 2006.176.08:02:22.42#ibcon#about to read 5, iclass 31, count 2 2006.176.08:02:22.42#ibcon#read 5, iclass 31, count 2 2006.176.08:02:22.42#ibcon#about to read 6, iclass 31, count 2 2006.176.08:02:22.42#ibcon#read 6, iclass 31, count 2 2006.176.08:02:22.42#ibcon#end of sib2, iclass 31, count 2 2006.176.08:02:22.42#ibcon#*after write, iclass 31, count 2 2006.176.08:02:22.42#ibcon#*before return 0, iclass 31, count 2 2006.176.08:02:22.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:22.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:02:22.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.08:02:22.42#ibcon#ireg 7 cls_cnt 0 2006.176.08:02:22.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:22.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:22.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:22.54#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:02:22.54#ibcon#first serial, iclass 31, count 0 2006.176.08:02:22.54#ibcon#enter sib2, iclass 31, count 0 2006.176.08:02:22.54#ibcon#flushed, iclass 31, count 0 2006.176.08:02:22.54#ibcon#about to write, iclass 31, count 0 2006.176.08:02:22.54#ibcon#wrote, iclass 31, count 0 2006.176.08:02:22.54#ibcon#about to read 3, iclass 31, count 0 2006.176.08:02:22.56#ibcon#read 3, iclass 31, count 0 2006.176.08:02:22.56#ibcon#about to read 4, iclass 31, count 0 2006.176.08:02:22.56#ibcon#read 4, iclass 31, count 0 2006.176.08:02:22.56#ibcon#about to read 5, iclass 31, count 0 2006.176.08:02:22.56#ibcon#read 5, iclass 31, count 0 2006.176.08:02:22.56#ibcon#about to read 6, iclass 31, count 0 2006.176.08:02:22.56#ibcon#read 6, iclass 31, count 0 2006.176.08:02:22.56#ibcon#end of sib2, iclass 31, count 0 2006.176.08:02:22.56#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:02:22.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:02:22.56#ibcon#[27=USB\r\n] 2006.176.08:02:22.56#ibcon#*before write, iclass 31, count 0 2006.176.08:02:22.56#ibcon#enter sib2, iclass 31, count 0 2006.176.08:02:22.56#ibcon#flushed, iclass 31, count 0 2006.176.08:02:22.56#ibcon#about to write, iclass 31, count 0 2006.176.08:02:22.56#ibcon#wrote, iclass 31, count 0 2006.176.08:02:22.56#ibcon#about to read 3, iclass 31, count 0 2006.176.08:02:22.59#ibcon#read 3, iclass 31, count 0 2006.176.08:02:22.59#ibcon#about to read 4, iclass 31, count 0 2006.176.08:02:22.59#ibcon#read 4, iclass 31, count 0 2006.176.08:02:22.59#ibcon#about to read 5, iclass 31, count 0 2006.176.08:02:22.59#ibcon#read 5, iclass 31, count 0 2006.176.08:02:22.59#ibcon#about to read 6, iclass 31, count 0 2006.176.08:02:22.59#ibcon#read 6, iclass 31, count 0 2006.176.08:02:22.59#ibcon#end of sib2, iclass 31, count 0 2006.176.08:02:22.59#ibcon#*after write, iclass 31, count 0 2006.176.08:02:22.59#ibcon#*before return 0, iclass 31, count 0 2006.176.08:02:22.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:22.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:02:22.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:02:22.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:02:22.59$vc4f8/vabw=wide 2006.176.08:02:22.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.08:02:22.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.08:02:22.59#ibcon#ireg 8 cls_cnt 0 2006.176.08:02:22.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:22.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:22.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:22.59#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:02:22.59#ibcon#first serial, iclass 33, count 0 2006.176.08:02:22.59#ibcon#enter sib2, iclass 33, count 0 2006.176.08:02:22.59#ibcon#flushed, iclass 33, count 0 2006.176.08:02:22.59#ibcon#about to write, iclass 33, count 0 2006.176.08:02:22.59#ibcon#wrote, iclass 33, count 0 2006.176.08:02:22.59#ibcon#about to read 3, iclass 33, count 0 2006.176.08:02:22.61#ibcon#read 3, iclass 33, count 0 2006.176.08:02:22.61#ibcon#about to read 4, iclass 33, count 0 2006.176.08:02:22.61#ibcon#read 4, iclass 33, count 0 2006.176.08:02:22.61#ibcon#about to read 5, iclass 33, count 0 2006.176.08:02:22.61#ibcon#read 5, iclass 33, count 0 2006.176.08:02:22.61#ibcon#about to read 6, iclass 33, count 0 2006.176.08:02:22.61#ibcon#read 6, iclass 33, count 0 2006.176.08:02:22.61#ibcon#end of sib2, iclass 33, count 0 2006.176.08:02:22.61#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:02:22.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:02:22.61#ibcon#[25=BW32\r\n] 2006.176.08:02:22.61#ibcon#*before write, iclass 33, count 0 2006.176.08:02:22.61#ibcon#enter sib2, iclass 33, count 0 2006.176.08:02:22.61#ibcon#flushed, iclass 33, count 0 2006.176.08:02:22.61#ibcon#about to write, iclass 33, count 0 2006.176.08:02:22.61#ibcon#wrote, iclass 33, count 0 2006.176.08:02:22.61#ibcon#about to read 3, iclass 33, count 0 2006.176.08:02:22.64#ibcon#read 3, iclass 33, count 0 2006.176.08:02:22.64#ibcon#about to read 4, iclass 33, count 0 2006.176.08:02:22.64#ibcon#read 4, iclass 33, count 0 2006.176.08:02:22.64#ibcon#about to read 5, iclass 33, count 0 2006.176.08:02:22.64#ibcon#read 5, iclass 33, count 0 2006.176.08:02:22.64#ibcon#about to read 6, iclass 33, count 0 2006.176.08:02:22.64#ibcon#read 6, iclass 33, count 0 2006.176.08:02:22.64#ibcon#end of sib2, iclass 33, count 0 2006.176.08:02:22.64#ibcon#*after write, iclass 33, count 0 2006.176.08:02:22.64#ibcon#*before return 0, iclass 33, count 0 2006.176.08:02:22.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:22.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:02:22.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:02:22.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:02:22.64$vc4f8/vbbw=wide 2006.176.08:02:22.64#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.08:02:22.64#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.08:02:22.64#ibcon#ireg 8 cls_cnt 0 2006.176.08:02:22.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:02:22.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:02:22.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:02:22.71#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:02:22.71#ibcon#first serial, iclass 35, count 0 2006.176.08:02:22.71#ibcon#enter sib2, iclass 35, count 0 2006.176.08:02:22.71#ibcon#flushed, iclass 35, count 0 2006.176.08:02:22.71#ibcon#about to write, iclass 35, count 0 2006.176.08:02:22.71#ibcon#wrote, iclass 35, count 0 2006.176.08:02:22.71#ibcon#about to read 3, iclass 35, count 0 2006.176.08:02:22.73#ibcon#read 3, iclass 35, count 0 2006.176.08:02:22.73#ibcon#about to read 4, iclass 35, count 0 2006.176.08:02:22.73#ibcon#read 4, iclass 35, count 0 2006.176.08:02:22.73#ibcon#about to read 5, iclass 35, count 0 2006.176.08:02:22.73#ibcon#read 5, iclass 35, count 0 2006.176.08:02:22.73#ibcon#about to read 6, iclass 35, count 0 2006.176.08:02:22.73#ibcon#read 6, iclass 35, count 0 2006.176.08:02:22.73#ibcon#end of sib2, iclass 35, count 0 2006.176.08:02:22.73#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:02:22.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:02:22.73#ibcon#[27=BW32\r\n] 2006.176.08:02:22.73#ibcon#*before write, iclass 35, count 0 2006.176.08:02:22.73#ibcon#enter sib2, iclass 35, count 0 2006.176.08:02:22.73#ibcon#flushed, iclass 35, count 0 2006.176.08:02:22.73#ibcon#about to write, iclass 35, count 0 2006.176.08:02:22.73#ibcon#wrote, iclass 35, count 0 2006.176.08:02:22.73#ibcon#about to read 3, iclass 35, count 0 2006.176.08:02:22.76#ibcon#read 3, iclass 35, count 0 2006.176.08:02:22.76#ibcon#about to read 4, iclass 35, count 0 2006.176.08:02:22.76#ibcon#read 4, iclass 35, count 0 2006.176.08:02:22.76#ibcon#about to read 5, iclass 35, count 0 2006.176.08:02:22.76#ibcon#read 5, iclass 35, count 0 2006.176.08:02:22.76#ibcon#about to read 6, iclass 35, count 0 2006.176.08:02:22.76#ibcon#read 6, iclass 35, count 0 2006.176.08:02:22.76#ibcon#end of sib2, iclass 35, count 0 2006.176.08:02:22.76#ibcon#*after write, iclass 35, count 0 2006.176.08:02:22.76#ibcon#*before return 0, iclass 35, count 0 2006.176.08:02:22.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:02:22.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:02:22.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:02:22.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:02:22.76$4f8m12a/ifd4f 2006.176.08:02:22.76$ifd4f/lo= 2006.176.08:02:22.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:02:22.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:02:22.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:02:22.76$ifd4f/patch= 2006.176.08:02:22.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:02:22.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:02:22.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:02:22.76$4f8m12a/"form=m,16.000,1:2 2006.176.08:02:22.76$4f8m12a/"tpicd 2006.176.08:02:22.76$4f8m12a/echo=off 2006.176.08:02:22.76$4f8m12a/xlog=off 2006.176.08:02:22.76:!2006.176.08:02:50 2006.176.08:02:27.14#trakl#Source acquired 2006.176.08:02:28.14#flagr#flagr/antenna,acquired 2006.176.08:02:50.01:preob 2006.176.08:02:51.14/onsource/TRACKING 2006.176.08:02:51.14:!2006.176.08:03:00 2006.176.08:03:00.00:data_valid=on 2006.176.08:03:00.00:midob 2006.176.08:03:00.14/onsource/TRACKING 2006.176.08:03:00.14/wx/23.85,1008.5,91 2006.176.08:03:00.28/cable/+6.4945E-03 2006.176.08:03:01.37/va/01,08,usb,yes,29,31 2006.176.08:03:01.37/va/02,07,usb,yes,29,31 2006.176.08:03:01.37/va/03,06,usb,yes,31,31 2006.176.08:03:01.37/va/04,07,usb,yes,30,32 2006.176.08:03:01.37/va/05,07,usb,yes,31,33 2006.176.08:03:01.37/va/06,06,usb,yes,30,30 2006.176.08:03:01.37/va/07,06,usb,yes,31,31 2006.176.08:03:01.37/va/08,06,usb,yes,33,32 2006.176.08:03:01.60/valo/01,532.99,yes,locked 2006.176.08:03:01.60/valo/02,572.99,yes,locked 2006.176.08:03:01.60/valo/03,672.99,yes,locked 2006.176.08:03:01.60/valo/04,832.99,yes,locked 2006.176.08:03:01.60/valo/05,652.99,yes,locked 2006.176.08:03:01.60/valo/06,772.99,yes,locked 2006.176.08:03:01.60/valo/07,832.99,yes,locked 2006.176.08:03:01.60/valo/08,852.99,yes,locked 2006.176.08:03:02.69/vb/01,04,usb,yes,29,28 2006.176.08:03:02.69/vb/02,04,usb,yes,31,32 2006.176.08:03:02.69/vb/03,04,usb,yes,27,31 2006.176.08:03:02.69/vb/04,04,usb,yes,28,28 2006.176.08:03:02.69/vb/05,04,usb,yes,27,30 2006.176.08:03:02.69/vb/06,04,usb,yes,28,30 2006.176.08:03:02.69/vb/07,04,usb,yes,30,29 2006.176.08:03:02.69/vb/08,04,usb,yes,27,30 2006.176.08:03:02.92/vblo/01,632.99,yes,locked 2006.176.08:03:02.92/vblo/02,640.99,yes,locked 2006.176.08:03:02.92/vblo/03,656.99,yes,locked 2006.176.08:03:02.92/vblo/04,712.99,yes,locked 2006.176.08:03:02.92/vblo/05,744.99,yes,locked 2006.176.08:03:02.92/vblo/06,752.99,yes,locked 2006.176.08:03:02.92/vblo/07,734.99,yes,locked 2006.176.08:03:02.92/vblo/08,744.99,yes,locked 2006.176.08:03:03.07/vabw/8 2006.176.08:03:03.22/vbbw/8 2006.176.08:03:03.31/xfe/off,on,14.2 2006.176.08:03:03.71/ifatt/23,28,28,28 2006.176.08:03:04.07/fmout-gps/S +3.72E-07 2006.176.08:03:04.11:!2006.176.08:04:00 2006.176.08:04:00.00:data_valid=off 2006.176.08:04:00.01:postob 2006.176.08:04:00.12/cable/+6.4952E-03 2006.176.08:04:00.13/wx/23.85,1008.6,92 2006.176.08:04:01.07/fmout-gps/S +3.71E-07 2006.176.08:04:01.08:scan_name=176-0805,k06176,60 2006.176.08:04:01.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.176.08:04:02.14#flagr#flagr/antenna,new-source 2006.176.08:04:02.15:checkk5 2006.176.08:04:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:04:02.91/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:04:03.29/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:04:03.70/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:04:04.07/chk_obsdata//k5ts1/T1760803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:04:04.45/chk_obsdata//k5ts2/T1760803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:04:04.81/chk_obsdata//k5ts3/T1760803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:04:05.18/chk_obsdata//k5ts4/T1760803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:04:05.89/k5log//k5ts1_log_newline 2006.176.08:04:06.57/k5log//k5ts2_log_newline 2006.176.08:04:07.27/k5log//k5ts3_log_newline 2006.176.08:04:07.95/k5log//k5ts4_log_newline 2006.176.08:04:07.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:04:07.98:4f8m12a=2 2006.176.08:04:07.98$4f8m12a/echo=on 2006.176.08:04:07.98$4f8m12a/pcalon 2006.176.08:04:07.98$pcalon/"no phase cal control is implemented here 2006.176.08:04:07.98$4f8m12a/"tpicd=stop 2006.176.08:04:07.98$4f8m12a/vc4f8 2006.176.08:04:07.98$vc4f8/valo=1,532.99 2006.176.08:04:07.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.08:04:07.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.08:04:07.98#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:07.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:07.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:07.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:07.98#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:04:07.98#ibcon#first serial, iclass 10, count 0 2006.176.08:04:07.98#ibcon#enter sib2, iclass 10, count 0 2006.176.08:04:07.98#ibcon#flushed, iclass 10, count 0 2006.176.08:04:07.98#ibcon#about to write, iclass 10, count 0 2006.176.08:04:07.98#ibcon#wrote, iclass 10, count 0 2006.176.08:04:07.98#ibcon#about to read 3, iclass 10, count 0 2006.176.08:04:07.99#ibcon#read 3, iclass 10, count 0 2006.176.08:04:07.99#ibcon#about to read 4, iclass 10, count 0 2006.176.08:04:07.99#ibcon#read 4, iclass 10, count 0 2006.176.08:04:07.99#ibcon#about to read 5, iclass 10, count 0 2006.176.08:04:07.99#ibcon#read 5, iclass 10, count 0 2006.176.08:04:07.99#ibcon#about to read 6, iclass 10, count 0 2006.176.08:04:07.99#ibcon#read 6, iclass 10, count 0 2006.176.08:04:07.99#ibcon#end of sib2, iclass 10, count 0 2006.176.08:04:07.99#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:04:07.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:04:07.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:04:07.99#ibcon#*before write, iclass 10, count 0 2006.176.08:04:07.99#ibcon#enter sib2, iclass 10, count 0 2006.176.08:04:07.99#ibcon#flushed, iclass 10, count 0 2006.176.08:04:07.99#ibcon#about to write, iclass 10, count 0 2006.176.08:04:07.99#ibcon#wrote, iclass 10, count 0 2006.176.08:04:07.99#ibcon#about to read 3, iclass 10, count 0 2006.176.08:04:08.04#ibcon#read 3, iclass 10, count 0 2006.176.08:04:08.04#ibcon#about to read 4, iclass 10, count 0 2006.176.08:04:08.04#ibcon#read 4, iclass 10, count 0 2006.176.08:04:08.04#ibcon#about to read 5, iclass 10, count 0 2006.176.08:04:08.04#ibcon#read 5, iclass 10, count 0 2006.176.08:04:08.04#ibcon#about to read 6, iclass 10, count 0 2006.176.08:04:08.04#ibcon#read 6, iclass 10, count 0 2006.176.08:04:08.04#ibcon#end of sib2, iclass 10, count 0 2006.176.08:04:08.04#ibcon#*after write, iclass 10, count 0 2006.176.08:04:08.04#ibcon#*before return 0, iclass 10, count 0 2006.176.08:04:08.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:08.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:08.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:04:08.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:04:08.04$vc4f8/va=1,8 2006.176.08:04:08.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.08:04:08.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.08:04:08.04#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:08.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:08.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:08.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:08.04#ibcon#enter wrdev, iclass 12, count 2 2006.176.08:04:08.04#ibcon#first serial, iclass 12, count 2 2006.176.08:04:08.04#ibcon#enter sib2, iclass 12, count 2 2006.176.08:04:08.04#ibcon#flushed, iclass 12, count 2 2006.176.08:04:08.04#ibcon#about to write, iclass 12, count 2 2006.176.08:04:08.04#ibcon#wrote, iclass 12, count 2 2006.176.08:04:08.04#ibcon#about to read 3, iclass 12, count 2 2006.176.08:04:08.06#ibcon#read 3, iclass 12, count 2 2006.176.08:04:08.06#ibcon#about to read 4, iclass 12, count 2 2006.176.08:04:08.06#ibcon#read 4, iclass 12, count 2 2006.176.08:04:08.06#ibcon#about to read 5, iclass 12, count 2 2006.176.08:04:08.06#ibcon#read 5, iclass 12, count 2 2006.176.08:04:08.06#ibcon#about to read 6, iclass 12, count 2 2006.176.08:04:08.06#ibcon#read 6, iclass 12, count 2 2006.176.08:04:08.06#ibcon#end of sib2, iclass 12, count 2 2006.176.08:04:08.06#ibcon#*mode == 0, iclass 12, count 2 2006.176.08:04:08.06#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.08:04:08.06#ibcon#[25=AT01-08\r\n] 2006.176.08:04:08.06#ibcon#*before write, iclass 12, count 2 2006.176.08:04:08.06#ibcon#enter sib2, iclass 12, count 2 2006.176.08:04:08.06#ibcon#flushed, iclass 12, count 2 2006.176.08:04:08.06#ibcon#about to write, iclass 12, count 2 2006.176.08:04:08.06#ibcon#wrote, iclass 12, count 2 2006.176.08:04:08.06#ibcon#about to read 3, iclass 12, count 2 2006.176.08:04:08.10#ibcon#read 3, iclass 12, count 2 2006.176.08:04:08.10#ibcon#about to read 4, iclass 12, count 2 2006.176.08:04:08.10#ibcon#read 4, iclass 12, count 2 2006.176.08:04:08.10#ibcon#about to read 5, iclass 12, count 2 2006.176.08:04:08.10#ibcon#read 5, iclass 12, count 2 2006.176.08:04:08.10#ibcon#about to read 6, iclass 12, count 2 2006.176.08:04:08.10#ibcon#read 6, iclass 12, count 2 2006.176.08:04:08.10#ibcon#end of sib2, iclass 12, count 2 2006.176.08:04:08.10#ibcon#*after write, iclass 12, count 2 2006.176.08:04:08.10#ibcon#*before return 0, iclass 12, count 2 2006.176.08:04:08.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:08.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:08.10#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.08:04:08.10#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:08.10#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:08.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:08.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:08.21#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:04:08.21#ibcon#first serial, iclass 12, count 0 2006.176.08:04:08.21#ibcon#enter sib2, iclass 12, count 0 2006.176.08:04:08.21#ibcon#flushed, iclass 12, count 0 2006.176.08:04:08.21#ibcon#about to write, iclass 12, count 0 2006.176.08:04:08.21#ibcon#wrote, iclass 12, count 0 2006.176.08:04:08.21#ibcon#about to read 3, iclass 12, count 0 2006.176.08:04:08.23#ibcon#read 3, iclass 12, count 0 2006.176.08:04:08.23#ibcon#about to read 4, iclass 12, count 0 2006.176.08:04:08.23#ibcon#read 4, iclass 12, count 0 2006.176.08:04:08.23#ibcon#about to read 5, iclass 12, count 0 2006.176.08:04:08.23#ibcon#read 5, iclass 12, count 0 2006.176.08:04:08.23#ibcon#about to read 6, iclass 12, count 0 2006.176.08:04:08.23#ibcon#read 6, iclass 12, count 0 2006.176.08:04:08.23#ibcon#end of sib2, iclass 12, count 0 2006.176.08:04:08.23#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:04:08.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:04:08.23#ibcon#[25=USB\r\n] 2006.176.08:04:08.23#ibcon#*before write, iclass 12, count 0 2006.176.08:04:08.23#ibcon#enter sib2, iclass 12, count 0 2006.176.08:04:08.23#ibcon#flushed, iclass 12, count 0 2006.176.08:04:08.23#ibcon#about to write, iclass 12, count 0 2006.176.08:04:08.23#ibcon#wrote, iclass 12, count 0 2006.176.08:04:08.23#ibcon#about to read 3, iclass 12, count 0 2006.176.08:04:08.26#ibcon#read 3, iclass 12, count 0 2006.176.08:04:08.26#ibcon#about to read 4, iclass 12, count 0 2006.176.08:04:08.26#ibcon#read 4, iclass 12, count 0 2006.176.08:04:08.26#ibcon#about to read 5, iclass 12, count 0 2006.176.08:04:08.26#ibcon#read 5, iclass 12, count 0 2006.176.08:04:08.26#ibcon#about to read 6, iclass 12, count 0 2006.176.08:04:08.26#ibcon#read 6, iclass 12, count 0 2006.176.08:04:08.26#ibcon#end of sib2, iclass 12, count 0 2006.176.08:04:08.26#ibcon#*after write, iclass 12, count 0 2006.176.08:04:08.26#ibcon#*before return 0, iclass 12, count 0 2006.176.08:04:08.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:08.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:08.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:04:08.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:04:08.26$vc4f8/valo=2,572.99 2006.176.08:04:08.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.08:04:08.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.08:04:08.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:08.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:08.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:08.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:08.26#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:04:08.26#ibcon#first serial, iclass 14, count 0 2006.176.08:04:08.26#ibcon#enter sib2, iclass 14, count 0 2006.176.08:04:08.26#ibcon#flushed, iclass 14, count 0 2006.176.08:04:08.26#ibcon#about to write, iclass 14, count 0 2006.176.08:04:08.26#ibcon#wrote, iclass 14, count 0 2006.176.08:04:08.26#ibcon#about to read 3, iclass 14, count 0 2006.176.08:04:08.28#ibcon#read 3, iclass 14, count 0 2006.176.08:04:08.28#ibcon#about to read 4, iclass 14, count 0 2006.176.08:04:08.28#ibcon#read 4, iclass 14, count 0 2006.176.08:04:08.28#ibcon#about to read 5, iclass 14, count 0 2006.176.08:04:08.28#ibcon#read 5, iclass 14, count 0 2006.176.08:04:08.28#ibcon#about to read 6, iclass 14, count 0 2006.176.08:04:08.28#ibcon#read 6, iclass 14, count 0 2006.176.08:04:08.28#ibcon#end of sib2, iclass 14, count 0 2006.176.08:04:08.28#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:04:08.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:04:08.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:04:08.28#ibcon#*before write, iclass 14, count 0 2006.176.08:04:08.28#ibcon#enter sib2, iclass 14, count 0 2006.176.08:04:08.28#ibcon#flushed, iclass 14, count 0 2006.176.08:04:08.28#ibcon#about to write, iclass 14, count 0 2006.176.08:04:08.28#ibcon#wrote, iclass 14, count 0 2006.176.08:04:08.28#ibcon#about to read 3, iclass 14, count 0 2006.176.08:04:08.32#ibcon#read 3, iclass 14, count 0 2006.176.08:04:08.32#ibcon#about to read 4, iclass 14, count 0 2006.176.08:04:08.32#ibcon#read 4, iclass 14, count 0 2006.176.08:04:08.32#ibcon#about to read 5, iclass 14, count 0 2006.176.08:04:08.32#ibcon#read 5, iclass 14, count 0 2006.176.08:04:08.32#ibcon#about to read 6, iclass 14, count 0 2006.176.08:04:08.32#ibcon#read 6, iclass 14, count 0 2006.176.08:04:08.32#ibcon#end of sib2, iclass 14, count 0 2006.176.08:04:08.32#ibcon#*after write, iclass 14, count 0 2006.176.08:04:08.32#ibcon#*before return 0, iclass 14, count 0 2006.176.08:04:08.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:08.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:08.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:04:08.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:04:08.32$vc4f8/va=2,7 2006.176.08:04:08.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.08:04:08.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.08:04:08.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:08.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:08.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:08.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:08.39#ibcon#enter wrdev, iclass 16, count 2 2006.176.08:04:08.39#ibcon#first serial, iclass 16, count 2 2006.176.08:04:08.39#ibcon#enter sib2, iclass 16, count 2 2006.176.08:04:08.39#ibcon#flushed, iclass 16, count 2 2006.176.08:04:08.39#ibcon#about to write, iclass 16, count 2 2006.176.08:04:08.39#ibcon#wrote, iclass 16, count 2 2006.176.08:04:08.39#ibcon#about to read 3, iclass 16, count 2 2006.176.08:04:08.40#ibcon#read 3, iclass 16, count 2 2006.176.08:04:08.40#ibcon#about to read 4, iclass 16, count 2 2006.176.08:04:08.40#ibcon#read 4, iclass 16, count 2 2006.176.08:04:08.40#ibcon#about to read 5, iclass 16, count 2 2006.176.08:04:08.40#ibcon#read 5, iclass 16, count 2 2006.176.08:04:08.40#ibcon#about to read 6, iclass 16, count 2 2006.176.08:04:08.40#ibcon#read 6, iclass 16, count 2 2006.176.08:04:08.40#ibcon#end of sib2, iclass 16, count 2 2006.176.08:04:08.40#ibcon#*mode == 0, iclass 16, count 2 2006.176.08:04:08.40#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.08:04:08.40#ibcon#[25=AT02-07\r\n] 2006.176.08:04:08.40#ibcon#*before write, iclass 16, count 2 2006.176.08:04:08.40#ibcon#enter sib2, iclass 16, count 2 2006.176.08:04:08.40#ibcon#flushed, iclass 16, count 2 2006.176.08:04:08.40#ibcon#about to write, iclass 16, count 2 2006.176.08:04:08.40#ibcon#wrote, iclass 16, count 2 2006.176.08:04:08.40#ibcon#about to read 3, iclass 16, count 2 2006.176.08:04:08.43#ibcon#read 3, iclass 16, count 2 2006.176.08:04:08.43#ibcon#about to read 4, iclass 16, count 2 2006.176.08:04:08.43#ibcon#read 4, iclass 16, count 2 2006.176.08:04:08.43#ibcon#about to read 5, iclass 16, count 2 2006.176.08:04:08.43#ibcon#read 5, iclass 16, count 2 2006.176.08:04:08.43#ibcon#about to read 6, iclass 16, count 2 2006.176.08:04:08.43#ibcon#read 6, iclass 16, count 2 2006.176.08:04:08.43#ibcon#end of sib2, iclass 16, count 2 2006.176.08:04:08.43#ibcon#*after write, iclass 16, count 2 2006.176.08:04:08.43#ibcon#*before return 0, iclass 16, count 2 2006.176.08:04:08.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:08.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:08.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.08:04:08.43#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:08.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:08.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:08.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:08.55#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:04:08.55#ibcon#first serial, iclass 16, count 0 2006.176.08:04:08.55#ibcon#enter sib2, iclass 16, count 0 2006.176.08:04:08.55#ibcon#flushed, iclass 16, count 0 2006.176.08:04:08.55#ibcon#about to write, iclass 16, count 0 2006.176.08:04:08.55#ibcon#wrote, iclass 16, count 0 2006.176.08:04:08.55#ibcon#about to read 3, iclass 16, count 0 2006.176.08:04:08.57#ibcon#read 3, iclass 16, count 0 2006.176.08:04:08.57#ibcon#about to read 4, iclass 16, count 0 2006.176.08:04:08.57#ibcon#read 4, iclass 16, count 0 2006.176.08:04:08.57#ibcon#about to read 5, iclass 16, count 0 2006.176.08:04:08.57#ibcon#read 5, iclass 16, count 0 2006.176.08:04:08.57#ibcon#about to read 6, iclass 16, count 0 2006.176.08:04:08.57#ibcon#read 6, iclass 16, count 0 2006.176.08:04:08.57#ibcon#end of sib2, iclass 16, count 0 2006.176.08:04:08.57#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:04:08.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:04:08.57#ibcon#[25=USB\r\n] 2006.176.08:04:08.57#ibcon#*before write, iclass 16, count 0 2006.176.08:04:08.57#ibcon#enter sib2, iclass 16, count 0 2006.176.08:04:08.57#ibcon#flushed, iclass 16, count 0 2006.176.08:04:08.57#ibcon#about to write, iclass 16, count 0 2006.176.08:04:08.57#ibcon#wrote, iclass 16, count 0 2006.176.08:04:08.57#ibcon#about to read 3, iclass 16, count 0 2006.176.08:04:08.60#ibcon#read 3, iclass 16, count 0 2006.176.08:04:08.60#ibcon#about to read 4, iclass 16, count 0 2006.176.08:04:08.60#ibcon#read 4, iclass 16, count 0 2006.176.08:04:08.60#ibcon#about to read 5, iclass 16, count 0 2006.176.08:04:08.60#ibcon#read 5, iclass 16, count 0 2006.176.08:04:08.60#ibcon#about to read 6, iclass 16, count 0 2006.176.08:04:08.60#ibcon#read 6, iclass 16, count 0 2006.176.08:04:08.60#ibcon#end of sib2, iclass 16, count 0 2006.176.08:04:08.60#ibcon#*after write, iclass 16, count 0 2006.176.08:04:08.60#ibcon#*before return 0, iclass 16, count 0 2006.176.08:04:08.60#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:08.60#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:08.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:04:08.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:04:08.60$vc4f8/valo=3,672.99 2006.176.08:04:08.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.08:04:08.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.08:04:08.60#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:08.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:08.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:08.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:08.60#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:04:08.60#ibcon#first serial, iclass 18, count 0 2006.176.08:04:08.60#ibcon#enter sib2, iclass 18, count 0 2006.176.08:04:08.60#ibcon#flushed, iclass 18, count 0 2006.176.08:04:08.60#ibcon#about to write, iclass 18, count 0 2006.176.08:04:08.60#ibcon#wrote, iclass 18, count 0 2006.176.08:04:08.60#ibcon#about to read 3, iclass 18, count 0 2006.176.08:04:08.62#ibcon#read 3, iclass 18, count 0 2006.176.08:04:08.62#ibcon#about to read 4, iclass 18, count 0 2006.176.08:04:08.62#ibcon#read 4, iclass 18, count 0 2006.176.08:04:08.62#ibcon#about to read 5, iclass 18, count 0 2006.176.08:04:08.62#ibcon#read 5, iclass 18, count 0 2006.176.08:04:08.62#ibcon#about to read 6, iclass 18, count 0 2006.176.08:04:08.62#ibcon#read 6, iclass 18, count 0 2006.176.08:04:08.62#ibcon#end of sib2, iclass 18, count 0 2006.176.08:04:08.62#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:04:08.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:04:08.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:04:08.62#ibcon#*before write, iclass 18, count 0 2006.176.08:04:08.62#ibcon#enter sib2, iclass 18, count 0 2006.176.08:04:08.62#ibcon#flushed, iclass 18, count 0 2006.176.08:04:08.62#ibcon#about to write, iclass 18, count 0 2006.176.08:04:08.62#ibcon#wrote, iclass 18, count 0 2006.176.08:04:08.62#ibcon#about to read 3, iclass 18, count 0 2006.176.08:04:08.66#ibcon#read 3, iclass 18, count 0 2006.176.08:04:08.66#ibcon#about to read 4, iclass 18, count 0 2006.176.08:04:08.66#ibcon#read 4, iclass 18, count 0 2006.176.08:04:08.66#ibcon#about to read 5, iclass 18, count 0 2006.176.08:04:08.66#ibcon#read 5, iclass 18, count 0 2006.176.08:04:08.66#ibcon#about to read 6, iclass 18, count 0 2006.176.08:04:08.66#ibcon#read 6, iclass 18, count 0 2006.176.08:04:08.66#ibcon#end of sib2, iclass 18, count 0 2006.176.08:04:08.66#ibcon#*after write, iclass 18, count 0 2006.176.08:04:08.66#ibcon#*before return 0, iclass 18, count 0 2006.176.08:04:08.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:08.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:08.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:04:08.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:04:08.66$vc4f8/va=3,6 2006.176.08:04:08.66#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.08:04:08.66#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.08:04:08.66#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:08.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:08.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:08.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:08.72#ibcon#enter wrdev, iclass 20, count 2 2006.176.08:04:08.72#ibcon#first serial, iclass 20, count 2 2006.176.08:04:08.72#ibcon#enter sib2, iclass 20, count 2 2006.176.08:04:08.72#ibcon#flushed, iclass 20, count 2 2006.176.08:04:08.72#ibcon#about to write, iclass 20, count 2 2006.176.08:04:08.72#ibcon#wrote, iclass 20, count 2 2006.176.08:04:08.72#ibcon#about to read 3, iclass 20, count 2 2006.176.08:04:08.75#ibcon#read 3, iclass 20, count 2 2006.176.08:04:08.75#ibcon#about to read 4, iclass 20, count 2 2006.176.08:04:08.75#ibcon#read 4, iclass 20, count 2 2006.176.08:04:08.75#ibcon#about to read 5, iclass 20, count 2 2006.176.08:04:08.75#ibcon#read 5, iclass 20, count 2 2006.176.08:04:08.75#ibcon#about to read 6, iclass 20, count 2 2006.176.08:04:08.75#ibcon#read 6, iclass 20, count 2 2006.176.08:04:08.75#ibcon#end of sib2, iclass 20, count 2 2006.176.08:04:08.75#ibcon#*mode == 0, iclass 20, count 2 2006.176.08:04:08.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.08:04:08.75#ibcon#[25=AT03-06\r\n] 2006.176.08:04:08.75#ibcon#*before write, iclass 20, count 2 2006.176.08:04:08.75#ibcon#enter sib2, iclass 20, count 2 2006.176.08:04:08.75#ibcon#flushed, iclass 20, count 2 2006.176.08:04:08.75#ibcon#about to write, iclass 20, count 2 2006.176.08:04:08.75#ibcon#wrote, iclass 20, count 2 2006.176.08:04:08.75#ibcon#about to read 3, iclass 20, count 2 2006.176.08:04:08.77#ibcon#read 3, iclass 20, count 2 2006.176.08:04:08.77#ibcon#about to read 4, iclass 20, count 2 2006.176.08:04:08.77#ibcon#read 4, iclass 20, count 2 2006.176.08:04:08.77#ibcon#about to read 5, iclass 20, count 2 2006.176.08:04:08.77#ibcon#read 5, iclass 20, count 2 2006.176.08:04:08.77#ibcon#about to read 6, iclass 20, count 2 2006.176.08:04:08.77#ibcon#read 6, iclass 20, count 2 2006.176.08:04:08.77#ibcon#end of sib2, iclass 20, count 2 2006.176.08:04:08.77#ibcon#*after write, iclass 20, count 2 2006.176.08:04:08.77#ibcon#*before return 0, iclass 20, count 2 2006.176.08:04:08.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:08.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:08.77#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.08:04:08.77#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:08.77#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:08.89#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:08.89#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:08.89#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:04:08.89#ibcon#first serial, iclass 20, count 0 2006.176.08:04:08.89#ibcon#enter sib2, iclass 20, count 0 2006.176.08:04:08.89#ibcon#flushed, iclass 20, count 0 2006.176.08:04:08.89#ibcon#about to write, iclass 20, count 0 2006.176.08:04:08.89#ibcon#wrote, iclass 20, count 0 2006.176.08:04:08.89#ibcon#about to read 3, iclass 20, count 0 2006.176.08:04:08.91#ibcon#read 3, iclass 20, count 0 2006.176.08:04:08.91#ibcon#about to read 4, iclass 20, count 0 2006.176.08:04:08.91#ibcon#read 4, iclass 20, count 0 2006.176.08:04:08.91#ibcon#about to read 5, iclass 20, count 0 2006.176.08:04:08.91#ibcon#read 5, iclass 20, count 0 2006.176.08:04:08.91#ibcon#about to read 6, iclass 20, count 0 2006.176.08:04:08.91#ibcon#read 6, iclass 20, count 0 2006.176.08:04:08.91#ibcon#end of sib2, iclass 20, count 0 2006.176.08:04:08.91#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:04:08.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:04:08.91#ibcon#[25=USB\r\n] 2006.176.08:04:08.91#ibcon#*before write, iclass 20, count 0 2006.176.08:04:08.91#ibcon#enter sib2, iclass 20, count 0 2006.176.08:04:08.91#ibcon#flushed, iclass 20, count 0 2006.176.08:04:08.91#ibcon#about to write, iclass 20, count 0 2006.176.08:04:08.91#ibcon#wrote, iclass 20, count 0 2006.176.08:04:08.91#ibcon#about to read 3, iclass 20, count 0 2006.176.08:04:08.94#ibcon#read 3, iclass 20, count 0 2006.176.08:04:08.94#ibcon#about to read 4, iclass 20, count 0 2006.176.08:04:08.94#ibcon#read 4, iclass 20, count 0 2006.176.08:04:08.94#ibcon#about to read 5, iclass 20, count 0 2006.176.08:04:08.94#ibcon#read 5, iclass 20, count 0 2006.176.08:04:08.94#ibcon#about to read 6, iclass 20, count 0 2006.176.08:04:08.94#ibcon#read 6, iclass 20, count 0 2006.176.08:04:08.94#ibcon#end of sib2, iclass 20, count 0 2006.176.08:04:08.94#ibcon#*after write, iclass 20, count 0 2006.176.08:04:08.94#ibcon#*before return 0, iclass 20, count 0 2006.176.08:04:08.94#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:08.94#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:08.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:04:08.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:04:08.94$vc4f8/valo=4,832.99 2006.176.08:04:08.94#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.08:04:08.94#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.08:04:08.94#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:08.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:08.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:08.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:08.94#ibcon#enter wrdev, iclass 22, count 0 2006.176.08:04:08.94#ibcon#first serial, iclass 22, count 0 2006.176.08:04:08.94#ibcon#enter sib2, iclass 22, count 0 2006.176.08:04:08.94#ibcon#flushed, iclass 22, count 0 2006.176.08:04:08.94#ibcon#about to write, iclass 22, count 0 2006.176.08:04:08.94#ibcon#wrote, iclass 22, count 0 2006.176.08:04:08.94#ibcon#about to read 3, iclass 22, count 0 2006.176.08:04:08.96#ibcon#read 3, iclass 22, count 0 2006.176.08:04:08.96#ibcon#about to read 4, iclass 22, count 0 2006.176.08:04:08.96#ibcon#read 4, iclass 22, count 0 2006.176.08:04:08.96#ibcon#about to read 5, iclass 22, count 0 2006.176.08:04:08.96#ibcon#read 5, iclass 22, count 0 2006.176.08:04:08.96#ibcon#about to read 6, iclass 22, count 0 2006.176.08:04:08.96#ibcon#read 6, iclass 22, count 0 2006.176.08:04:08.96#ibcon#end of sib2, iclass 22, count 0 2006.176.08:04:08.96#ibcon#*mode == 0, iclass 22, count 0 2006.176.08:04:08.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.08:04:08.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:04:08.96#ibcon#*before write, iclass 22, count 0 2006.176.08:04:08.96#ibcon#enter sib2, iclass 22, count 0 2006.176.08:04:08.96#ibcon#flushed, iclass 22, count 0 2006.176.08:04:08.96#ibcon#about to write, iclass 22, count 0 2006.176.08:04:08.96#ibcon#wrote, iclass 22, count 0 2006.176.08:04:08.96#ibcon#about to read 3, iclass 22, count 0 2006.176.08:04:09.00#ibcon#read 3, iclass 22, count 0 2006.176.08:04:09.00#ibcon#about to read 4, iclass 22, count 0 2006.176.08:04:09.00#ibcon#read 4, iclass 22, count 0 2006.176.08:04:09.00#ibcon#about to read 5, iclass 22, count 0 2006.176.08:04:09.00#ibcon#read 5, iclass 22, count 0 2006.176.08:04:09.00#ibcon#about to read 6, iclass 22, count 0 2006.176.08:04:09.00#ibcon#read 6, iclass 22, count 0 2006.176.08:04:09.00#ibcon#end of sib2, iclass 22, count 0 2006.176.08:04:09.00#ibcon#*after write, iclass 22, count 0 2006.176.08:04:09.00#ibcon#*before return 0, iclass 22, count 0 2006.176.08:04:09.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:09.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:09.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.08:04:09.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.08:04:09.00$vc4f8/va=4,7 2006.176.08:04:09.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.08:04:09.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.08:04:09.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:09.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:09.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:09.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:09.06#ibcon#enter wrdev, iclass 24, count 2 2006.176.08:04:09.06#ibcon#first serial, iclass 24, count 2 2006.176.08:04:09.06#ibcon#enter sib2, iclass 24, count 2 2006.176.08:04:09.06#ibcon#flushed, iclass 24, count 2 2006.176.08:04:09.06#ibcon#about to write, iclass 24, count 2 2006.176.08:04:09.06#ibcon#wrote, iclass 24, count 2 2006.176.08:04:09.06#ibcon#about to read 3, iclass 24, count 2 2006.176.08:04:09.08#ibcon#read 3, iclass 24, count 2 2006.176.08:04:09.08#ibcon#about to read 4, iclass 24, count 2 2006.176.08:04:09.08#ibcon#read 4, iclass 24, count 2 2006.176.08:04:09.08#ibcon#about to read 5, iclass 24, count 2 2006.176.08:04:09.08#ibcon#read 5, iclass 24, count 2 2006.176.08:04:09.08#ibcon#about to read 6, iclass 24, count 2 2006.176.08:04:09.08#ibcon#read 6, iclass 24, count 2 2006.176.08:04:09.08#ibcon#end of sib2, iclass 24, count 2 2006.176.08:04:09.08#ibcon#*mode == 0, iclass 24, count 2 2006.176.08:04:09.08#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.08:04:09.08#ibcon#[25=AT04-07\r\n] 2006.176.08:04:09.08#ibcon#*before write, iclass 24, count 2 2006.176.08:04:09.08#ibcon#enter sib2, iclass 24, count 2 2006.176.08:04:09.08#ibcon#flushed, iclass 24, count 2 2006.176.08:04:09.08#ibcon#about to write, iclass 24, count 2 2006.176.08:04:09.08#ibcon#wrote, iclass 24, count 2 2006.176.08:04:09.08#ibcon#about to read 3, iclass 24, count 2 2006.176.08:04:09.11#ibcon#read 3, iclass 24, count 2 2006.176.08:04:09.11#ibcon#about to read 4, iclass 24, count 2 2006.176.08:04:09.11#ibcon#read 4, iclass 24, count 2 2006.176.08:04:09.11#ibcon#about to read 5, iclass 24, count 2 2006.176.08:04:09.11#ibcon#read 5, iclass 24, count 2 2006.176.08:04:09.11#ibcon#about to read 6, iclass 24, count 2 2006.176.08:04:09.11#ibcon#read 6, iclass 24, count 2 2006.176.08:04:09.11#ibcon#end of sib2, iclass 24, count 2 2006.176.08:04:09.11#ibcon#*after write, iclass 24, count 2 2006.176.08:04:09.11#ibcon#*before return 0, iclass 24, count 2 2006.176.08:04:09.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:09.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:09.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.08:04:09.11#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:09.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:09.23#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:09.23#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:09.23#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:04:09.23#ibcon#first serial, iclass 24, count 0 2006.176.08:04:09.23#ibcon#enter sib2, iclass 24, count 0 2006.176.08:04:09.23#ibcon#flushed, iclass 24, count 0 2006.176.08:04:09.23#ibcon#about to write, iclass 24, count 0 2006.176.08:04:09.23#ibcon#wrote, iclass 24, count 0 2006.176.08:04:09.23#ibcon#about to read 3, iclass 24, count 0 2006.176.08:04:09.25#ibcon#read 3, iclass 24, count 0 2006.176.08:04:09.25#ibcon#about to read 4, iclass 24, count 0 2006.176.08:04:09.25#ibcon#read 4, iclass 24, count 0 2006.176.08:04:09.25#ibcon#about to read 5, iclass 24, count 0 2006.176.08:04:09.25#ibcon#read 5, iclass 24, count 0 2006.176.08:04:09.25#ibcon#about to read 6, iclass 24, count 0 2006.176.08:04:09.25#ibcon#read 6, iclass 24, count 0 2006.176.08:04:09.25#ibcon#end of sib2, iclass 24, count 0 2006.176.08:04:09.25#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:04:09.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:04:09.25#ibcon#[25=USB\r\n] 2006.176.08:04:09.25#ibcon#*before write, iclass 24, count 0 2006.176.08:04:09.25#ibcon#enter sib2, iclass 24, count 0 2006.176.08:04:09.25#ibcon#flushed, iclass 24, count 0 2006.176.08:04:09.25#ibcon#about to write, iclass 24, count 0 2006.176.08:04:09.25#ibcon#wrote, iclass 24, count 0 2006.176.08:04:09.25#ibcon#about to read 3, iclass 24, count 0 2006.176.08:04:09.28#ibcon#read 3, iclass 24, count 0 2006.176.08:04:09.28#ibcon#about to read 4, iclass 24, count 0 2006.176.08:04:09.28#ibcon#read 4, iclass 24, count 0 2006.176.08:04:09.28#ibcon#about to read 5, iclass 24, count 0 2006.176.08:04:09.28#ibcon#read 5, iclass 24, count 0 2006.176.08:04:09.28#ibcon#about to read 6, iclass 24, count 0 2006.176.08:04:09.28#ibcon#read 6, iclass 24, count 0 2006.176.08:04:09.28#ibcon#end of sib2, iclass 24, count 0 2006.176.08:04:09.28#ibcon#*after write, iclass 24, count 0 2006.176.08:04:09.28#ibcon#*before return 0, iclass 24, count 0 2006.176.08:04:09.28#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:09.28#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:09.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:04:09.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:04:09.28$vc4f8/valo=5,652.99 2006.176.08:04:09.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.08:04:09.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.08:04:09.28#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:09.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:09.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:09.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:09.28#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:04:09.28#ibcon#first serial, iclass 26, count 0 2006.176.08:04:09.28#ibcon#enter sib2, iclass 26, count 0 2006.176.08:04:09.28#ibcon#flushed, iclass 26, count 0 2006.176.08:04:09.28#ibcon#about to write, iclass 26, count 0 2006.176.08:04:09.28#ibcon#wrote, iclass 26, count 0 2006.176.08:04:09.28#ibcon#about to read 3, iclass 26, count 0 2006.176.08:04:09.30#ibcon#read 3, iclass 26, count 0 2006.176.08:04:09.30#ibcon#about to read 4, iclass 26, count 0 2006.176.08:04:09.30#ibcon#read 4, iclass 26, count 0 2006.176.08:04:09.30#ibcon#about to read 5, iclass 26, count 0 2006.176.08:04:09.30#ibcon#read 5, iclass 26, count 0 2006.176.08:04:09.30#ibcon#about to read 6, iclass 26, count 0 2006.176.08:04:09.30#ibcon#read 6, iclass 26, count 0 2006.176.08:04:09.30#ibcon#end of sib2, iclass 26, count 0 2006.176.08:04:09.30#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:04:09.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:04:09.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:04:09.30#ibcon#*before write, iclass 26, count 0 2006.176.08:04:09.30#ibcon#enter sib2, iclass 26, count 0 2006.176.08:04:09.30#ibcon#flushed, iclass 26, count 0 2006.176.08:04:09.30#ibcon#about to write, iclass 26, count 0 2006.176.08:04:09.30#ibcon#wrote, iclass 26, count 0 2006.176.08:04:09.30#ibcon#about to read 3, iclass 26, count 0 2006.176.08:04:09.34#ibcon#read 3, iclass 26, count 0 2006.176.08:04:09.34#ibcon#about to read 4, iclass 26, count 0 2006.176.08:04:09.34#ibcon#read 4, iclass 26, count 0 2006.176.08:04:09.34#ibcon#about to read 5, iclass 26, count 0 2006.176.08:04:09.34#ibcon#read 5, iclass 26, count 0 2006.176.08:04:09.34#ibcon#about to read 6, iclass 26, count 0 2006.176.08:04:09.34#ibcon#read 6, iclass 26, count 0 2006.176.08:04:09.34#ibcon#end of sib2, iclass 26, count 0 2006.176.08:04:09.34#ibcon#*after write, iclass 26, count 0 2006.176.08:04:09.34#ibcon#*before return 0, iclass 26, count 0 2006.176.08:04:09.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:09.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:09.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:04:09.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:04:09.34$vc4f8/va=5,7 2006.176.08:04:09.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.08:04:09.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.08:04:09.34#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:09.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:09.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:09.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:09.40#ibcon#enter wrdev, iclass 28, count 2 2006.176.08:04:09.40#ibcon#first serial, iclass 28, count 2 2006.176.08:04:09.40#ibcon#enter sib2, iclass 28, count 2 2006.176.08:04:09.40#ibcon#flushed, iclass 28, count 2 2006.176.08:04:09.40#ibcon#about to write, iclass 28, count 2 2006.176.08:04:09.40#ibcon#wrote, iclass 28, count 2 2006.176.08:04:09.40#ibcon#about to read 3, iclass 28, count 2 2006.176.08:04:09.42#ibcon#read 3, iclass 28, count 2 2006.176.08:04:09.42#ibcon#about to read 4, iclass 28, count 2 2006.176.08:04:09.42#ibcon#read 4, iclass 28, count 2 2006.176.08:04:09.42#ibcon#about to read 5, iclass 28, count 2 2006.176.08:04:09.42#ibcon#read 5, iclass 28, count 2 2006.176.08:04:09.42#ibcon#about to read 6, iclass 28, count 2 2006.176.08:04:09.42#ibcon#read 6, iclass 28, count 2 2006.176.08:04:09.42#ibcon#end of sib2, iclass 28, count 2 2006.176.08:04:09.42#ibcon#*mode == 0, iclass 28, count 2 2006.176.08:04:09.42#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.08:04:09.42#ibcon#[25=AT05-07\r\n] 2006.176.08:04:09.42#ibcon#*before write, iclass 28, count 2 2006.176.08:04:09.42#ibcon#enter sib2, iclass 28, count 2 2006.176.08:04:09.42#ibcon#flushed, iclass 28, count 2 2006.176.08:04:09.42#ibcon#about to write, iclass 28, count 2 2006.176.08:04:09.42#ibcon#wrote, iclass 28, count 2 2006.176.08:04:09.42#ibcon#about to read 3, iclass 28, count 2 2006.176.08:04:09.45#ibcon#read 3, iclass 28, count 2 2006.176.08:04:09.45#ibcon#about to read 4, iclass 28, count 2 2006.176.08:04:09.45#ibcon#read 4, iclass 28, count 2 2006.176.08:04:09.45#ibcon#about to read 5, iclass 28, count 2 2006.176.08:04:09.45#ibcon#read 5, iclass 28, count 2 2006.176.08:04:09.45#ibcon#about to read 6, iclass 28, count 2 2006.176.08:04:09.45#ibcon#read 6, iclass 28, count 2 2006.176.08:04:09.45#ibcon#end of sib2, iclass 28, count 2 2006.176.08:04:09.45#ibcon#*after write, iclass 28, count 2 2006.176.08:04:09.45#ibcon#*before return 0, iclass 28, count 2 2006.176.08:04:09.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:09.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:09.45#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.08:04:09.45#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:09.45#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:09.57#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:09.57#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:09.57#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:04:09.57#ibcon#first serial, iclass 28, count 0 2006.176.08:04:09.57#ibcon#enter sib2, iclass 28, count 0 2006.176.08:04:09.57#ibcon#flushed, iclass 28, count 0 2006.176.08:04:09.57#ibcon#about to write, iclass 28, count 0 2006.176.08:04:09.57#ibcon#wrote, iclass 28, count 0 2006.176.08:04:09.57#ibcon#about to read 3, iclass 28, count 0 2006.176.08:04:09.59#ibcon#read 3, iclass 28, count 0 2006.176.08:04:09.59#ibcon#about to read 4, iclass 28, count 0 2006.176.08:04:09.59#ibcon#read 4, iclass 28, count 0 2006.176.08:04:09.59#ibcon#about to read 5, iclass 28, count 0 2006.176.08:04:09.59#ibcon#read 5, iclass 28, count 0 2006.176.08:04:09.59#ibcon#about to read 6, iclass 28, count 0 2006.176.08:04:09.59#ibcon#read 6, iclass 28, count 0 2006.176.08:04:09.59#ibcon#end of sib2, iclass 28, count 0 2006.176.08:04:09.59#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:04:09.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:04:09.59#ibcon#[25=USB\r\n] 2006.176.08:04:09.59#ibcon#*before write, iclass 28, count 0 2006.176.08:04:09.59#ibcon#enter sib2, iclass 28, count 0 2006.176.08:04:09.59#ibcon#flushed, iclass 28, count 0 2006.176.08:04:09.59#ibcon#about to write, iclass 28, count 0 2006.176.08:04:09.59#ibcon#wrote, iclass 28, count 0 2006.176.08:04:09.59#ibcon#about to read 3, iclass 28, count 0 2006.176.08:04:09.62#ibcon#read 3, iclass 28, count 0 2006.176.08:04:09.62#ibcon#about to read 4, iclass 28, count 0 2006.176.08:04:09.62#ibcon#read 4, iclass 28, count 0 2006.176.08:04:09.62#ibcon#about to read 5, iclass 28, count 0 2006.176.08:04:09.62#ibcon#read 5, iclass 28, count 0 2006.176.08:04:09.62#ibcon#about to read 6, iclass 28, count 0 2006.176.08:04:09.62#ibcon#read 6, iclass 28, count 0 2006.176.08:04:09.62#ibcon#end of sib2, iclass 28, count 0 2006.176.08:04:09.62#ibcon#*after write, iclass 28, count 0 2006.176.08:04:09.62#ibcon#*before return 0, iclass 28, count 0 2006.176.08:04:09.62#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:09.62#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:09.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:04:09.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:04:09.62$vc4f8/valo=6,772.99 2006.176.08:04:09.62#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.08:04:09.62#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.08:04:09.62#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:09.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:09.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:09.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:09.62#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:04:09.62#ibcon#first serial, iclass 30, count 0 2006.176.08:04:09.62#ibcon#enter sib2, iclass 30, count 0 2006.176.08:04:09.62#ibcon#flushed, iclass 30, count 0 2006.176.08:04:09.62#ibcon#about to write, iclass 30, count 0 2006.176.08:04:09.62#ibcon#wrote, iclass 30, count 0 2006.176.08:04:09.62#ibcon#about to read 3, iclass 30, count 0 2006.176.08:04:09.64#ibcon#read 3, iclass 30, count 0 2006.176.08:04:09.64#ibcon#about to read 4, iclass 30, count 0 2006.176.08:04:09.64#ibcon#read 4, iclass 30, count 0 2006.176.08:04:09.64#ibcon#about to read 5, iclass 30, count 0 2006.176.08:04:09.64#ibcon#read 5, iclass 30, count 0 2006.176.08:04:09.64#ibcon#about to read 6, iclass 30, count 0 2006.176.08:04:09.64#ibcon#read 6, iclass 30, count 0 2006.176.08:04:09.64#ibcon#end of sib2, iclass 30, count 0 2006.176.08:04:09.64#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:04:09.64#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:04:09.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:04:09.64#ibcon#*before write, iclass 30, count 0 2006.176.08:04:09.64#ibcon#enter sib2, iclass 30, count 0 2006.176.08:04:09.64#ibcon#flushed, iclass 30, count 0 2006.176.08:04:09.64#ibcon#about to write, iclass 30, count 0 2006.176.08:04:09.64#ibcon#wrote, iclass 30, count 0 2006.176.08:04:09.64#ibcon#about to read 3, iclass 30, count 0 2006.176.08:04:09.68#ibcon#read 3, iclass 30, count 0 2006.176.08:04:09.68#ibcon#about to read 4, iclass 30, count 0 2006.176.08:04:09.68#ibcon#read 4, iclass 30, count 0 2006.176.08:04:09.68#ibcon#about to read 5, iclass 30, count 0 2006.176.08:04:09.68#ibcon#read 5, iclass 30, count 0 2006.176.08:04:09.68#ibcon#about to read 6, iclass 30, count 0 2006.176.08:04:09.68#ibcon#read 6, iclass 30, count 0 2006.176.08:04:09.68#ibcon#end of sib2, iclass 30, count 0 2006.176.08:04:09.68#ibcon#*after write, iclass 30, count 0 2006.176.08:04:09.68#ibcon#*before return 0, iclass 30, count 0 2006.176.08:04:09.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:09.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:09.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:04:09.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:04:09.68$vc4f8/va=6,6 2006.176.08:04:09.68#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.176.08:04:09.68#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.176.08:04:09.68#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:09.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:04:09.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:04:09.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:04:09.74#ibcon#enter wrdev, iclass 32, count 2 2006.176.08:04:09.74#ibcon#first serial, iclass 32, count 2 2006.176.08:04:09.74#ibcon#enter sib2, iclass 32, count 2 2006.176.08:04:09.74#ibcon#flushed, iclass 32, count 2 2006.176.08:04:09.74#ibcon#about to write, iclass 32, count 2 2006.176.08:04:09.74#ibcon#wrote, iclass 32, count 2 2006.176.08:04:09.74#ibcon#about to read 3, iclass 32, count 2 2006.176.08:04:09.77#ibcon#read 3, iclass 32, count 2 2006.176.08:04:09.77#ibcon#about to read 4, iclass 32, count 2 2006.176.08:04:09.77#ibcon#read 4, iclass 32, count 2 2006.176.08:04:09.77#ibcon#about to read 5, iclass 32, count 2 2006.176.08:04:09.77#ibcon#read 5, iclass 32, count 2 2006.176.08:04:09.77#ibcon#about to read 6, iclass 32, count 2 2006.176.08:04:09.77#ibcon#read 6, iclass 32, count 2 2006.176.08:04:09.77#ibcon#end of sib2, iclass 32, count 2 2006.176.08:04:09.77#ibcon#*mode == 0, iclass 32, count 2 2006.176.08:04:09.77#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.176.08:04:09.77#ibcon#[25=AT06-06\r\n] 2006.176.08:04:09.77#ibcon#*before write, iclass 32, count 2 2006.176.08:04:09.77#ibcon#enter sib2, iclass 32, count 2 2006.176.08:04:09.77#ibcon#flushed, iclass 32, count 2 2006.176.08:04:09.77#ibcon#about to write, iclass 32, count 2 2006.176.08:04:09.77#ibcon#wrote, iclass 32, count 2 2006.176.08:04:09.77#ibcon#about to read 3, iclass 32, count 2 2006.176.08:04:09.79#ibcon#read 3, iclass 32, count 2 2006.176.08:04:09.79#ibcon#about to read 4, iclass 32, count 2 2006.176.08:04:09.79#ibcon#read 4, iclass 32, count 2 2006.176.08:04:09.79#ibcon#about to read 5, iclass 32, count 2 2006.176.08:04:09.79#ibcon#read 5, iclass 32, count 2 2006.176.08:04:09.79#ibcon#about to read 6, iclass 32, count 2 2006.176.08:04:09.79#ibcon#read 6, iclass 32, count 2 2006.176.08:04:09.79#ibcon#end of sib2, iclass 32, count 2 2006.176.08:04:09.79#ibcon#*after write, iclass 32, count 2 2006.176.08:04:09.79#ibcon#*before return 0, iclass 32, count 2 2006.176.08:04:09.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:04:09.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:04:09.79#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.176.08:04:09.79#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:09.79#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:04:09.91#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:04:09.91#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:04:09.91#ibcon#enter wrdev, iclass 32, count 0 2006.176.08:04:09.91#ibcon#first serial, iclass 32, count 0 2006.176.08:04:09.91#ibcon#enter sib2, iclass 32, count 0 2006.176.08:04:09.91#ibcon#flushed, iclass 32, count 0 2006.176.08:04:09.91#ibcon#about to write, iclass 32, count 0 2006.176.08:04:09.91#ibcon#wrote, iclass 32, count 0 2006.176.08:04:09.91#ibcon#about to read 3, iclass 32, count 0 2006.176.08:04:09.93#ibcon#read 3, iclass 32, count 0 2006.176.08:04:09.93#ibcon#about to read 4, iclass 32, count 0 2006.176.08:04:09.93#ibcon#read 4, iclass 32, count 0 2006.176.08:04:09.93#ibcon#about to read 5, iclass 32, count 0 2006.176.08:04:09.93#ibcon#read 5, iclass 32, count 0 2006.176.08:04:09.93#ibcon#about to read 6, iclass 32, count 0 2006.176.08:04:09.93#ibcon#read 6, iclass 32, count 0 2006.176.08:04:09.93#ibcon#end of sib2, iclass 32, count 0 2006.176.08:04:09.93#ibcon#*mode == 0, iclass 32, count 0 2006.176.08:04:09.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.08:04:09.93#ibcon#[25=USB\r\n] 2006.176.08:04:09.93#ibcon#*before write, iclass 32, count 0 2006.176.08:04:09.93#ibcon#enter sib2, iclass 32, count 0 2006.176.08:04:09.93#ibcon#flushed, iclass 32, count 0 2006.176.08:04:09.93#ibcon#about to write, iclass 32, count 0 2006.176.08:04:09.93#ibcon#wrote, iclass 32, count 0 2006.176.08:04:09.93#ibcon#about to read 3, iclass 32, count 0 2006.176.08:04:09.96#ibcon#read 3, iclass 32, count 0 2006.176.08:04:09.96#ibcon#about to read 4, iclass 32, count 0 2006.176.08:04:09.96#ibcon#read 4, iclass 32, count 0 2006.176.08:04:09.96#ibcon#about to read 5, iclass 32, count 0 2006.176.08:04:09.96#ibcon#read 5, iclass 32, count 0 2006.176.08:04:09.96#ibcon#about to read 6, iclass 32, count 0 2006.176.08:04:09.96#ibcon#read 6, iclass 32, count 0 2006.176.08:04:09.96#ibcon#end of sib2, iclass 32, count 0 2006.176.08:04:09.96#ibcon#*after write, iclass 32, count 0 2006.176.08:04:09.96#ibcon#*before return 0, iclass 32, count 0 2006.176.08:04:09.96#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:04:09.96#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:04:09.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.08:04:09.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.08:04:09.96$vc4f8/valo=7,832.99 2006.176.08:04:09.96#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.08:04:09.96#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.08:04:09.96#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:09.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:04:09.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:04:09.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:04:09.96#ibcon#enter wrdev, iclass 34, count 0 2006.176.08:04:09.96#ibcon#first serial, iclass 34, count 0 2006.176.08:04:09.96#ibcon#enter sib2, iclass 34, count 0 2006.176.08:04:09.96#ibcon#flushed, iclass 34, count 0 2006.176.08:04:09.96#ibcon#about to write, iclass 34, count 0 2006.176.08:04:09.96#ibcon#wrote, iclass 34, count 0 2006.176.08:04:09.96#ibcon#about to read 3, iclass 34, count 0 2006.176.08:04:09.98#ibcon#read 3, iclass 34, count 0 2006.176.08:04:09.98#ibcon#about to read 4, iclass 34, count 0 2006.176.08:04:09.98#ibcon#read 4, iclass 34, count 0 2006.176.08:04:09.98#ibcon#about to read 5, iclass 34, count 0 2006.176.08:04:09.98#ibcon#read 5, iclass 34, count 0 2006.176.08:04:09.98#ibcon#about to read 6, iclass 34, count 0 2006.176.08:04:09.98#ibcon#read 6, iclass 34, count 0 2006.176.08:04:09.98#ibcon#end of sib2, iclass 34, count 0 2006.176.08:04:09.98#ibcon#*mode == 0, iclass 34, count 0 2006.176.08:04:09.98#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.08:04:09.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:04:09.98#ibcon#*before write, iclass 34, count 0 2006.176.08:04:09.98#ibcon#enter sib2, iclass 34, count 0 2006.176.08:04:09.98#ibcon#flushed, iclass 34, count 0 2006.176.08:04:09.98#ibcon#about to write, iclass 34, count 0 2006.176.08:04:09.98#ibcon#wrote, iclass 34, count 0 2006.176.08:04:09.98#ibcon#about to read 3, iclass 34, count 0 2006.176.08:04:10.02#ibcon#read 3, iclass 34, count 0 2006.176.08:04:10.02#ibcon#about to read 4, iclass 34, count 0 2006.176.08:04:10.02#ibcon#read 4, iclass 34, count 0 2006.176.08:04:10.02#ibcon#about to read 5, iclass 34, count 0 2006.176.08:04:10.02#ibcon#read 5, iclass 34, count 0 2006.176.08:04:10.02#ibcon#about to read 6, iclass 34, count 0 2006.176.08:04:10.02#ibcon#read 6, iclass 34, count 0 2006.176.08:04:10.02#ibcon#end of sib2, iclass 34, count 0 2006.176.08:04:10.02#ibcon#*after write, iclass 34, count 0 2006.176.08:04:10.02#ibcon#*before return 0, iclass 34, count 0 2006.176.08:04:10.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:04:10.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:04:10.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.08:04:10.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.08:04:10.02$vc4f8/va=7,6 2006.176.08:04:10.02#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.176.08:04:10.02#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.176.08:04:10.02#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:10.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:04:10.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:04:10.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:04:10.08#ibcon#enter wrdev, iclass 36, count 2 2006.176.08:04:10.08#ibcon#first serial, iclass 36, count 2 2006.176.08:04:10.08#ibcon#enter sib2, iclass 36, count 2 2006.176.08:04:10.08#ibcon#flushed, iclass 36, count 2 2006.176.08:04:10.08#ibcon#about to write, iclass 36, count 2 2006.176.08:04:10.08#ibcon#wrote, iclass 36, count 2 2006.176.08:04:10.08#ibcon#about to read 3, iclass 36, count 2 2006.176.08:04:10.10#ibcon#read 3, iclass 36, count 2 2006.176.08:04:10.10#ibcon#about to read 4, iclass 36, count 2 2006.176.08:04:10.10#ibcon#read 4, iclass 36, count 2 2006.176.08:04:10.10#ibcon#about to read 5, iclass 36, count 2 2006.176.08:04:10.10#ibcon#read 5, iclass 36, count 2 2006.176.08:04:10.10#ibcon#about to read 6, iclass 36, count 2 2006.176.08:04:10.10#ibcon#read 6, iclass 36, count 2 2006.176.08:04:10.10#ibcon#end of sib2, iclass 36, count 2 2006.176.08:04:10.10#ibcon#*mode == 0, iclass 36, count 2 2006.176.08:04:10.10#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.176.08:04:10.10#ibcon#[25=AT07-06\r\n] 2006.176.08:04:10.10#ibcon#*before write, iclass 36, count 2 2006.176.08:04:10.10#ibcon#enter sib2, iclass 36, count 2 2006.176.08:04:10.10#ibcon#flushed, iclass 36, count 2 2006.176.08:04:10.10#ibcon#about to write, iclass 36, count 2 2006.176.08:04:10.10#ibcon#wrote, iclass 36, count 2 2006.176.08:04:10.10#ibcon#about to read 3, iclass 36, count 2 2006.176.08:04:10.13#ibcon#read 3, iclass 36, count 2 2006.176.08:04:10.13#ibcon#about to read 4, iclass 36, count 2 2006.176.08:04:10.13#ibcon#read 4, iclass 36, count 2 2006.176.08:04:10.13#ibcon#about to read 5, iclass 36, count 2 2006.176.08:04:10.13#ibcon#read 5, iclass 36, count 2 2006.176.08:04:10.13#ibcon#about to read 6, iclass 36, count 2 2006.176.08:04:10.13#ibcon#read 6, iclass 36, count 2 2006.176.08:04:10.13#ibcon#end of sib2, iclass 36, count 2 2006.176.08:04:10.13#ibcon#*after write, iclass 36, count 2 2006.176.08:04:10.13#ibcon#*before return 0, iclass 36, count 2 2006.176.08:04:10.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:04:10.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:04:10.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.176.08:04:10.13#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:10.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:04:10.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:04:10.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:04:10.25#ibcon#enter wrdev, iclass 36, count 0 2006.176.08:04:10.25#ibcon#first serial, iclass 36, count 0 2006.176.08:04:10.25#ibcon#enter sib2, iclass 36, count 0 2006.176.08:04:10.25#ibcon#flushed, iclass 36, count 0 2006.176.08:04:10.25#ibcon#about to write, iclass 36, count 0 2006.176.08:04:10.25#ibcon#wrote, iclass 36, count 0 2006.176.08:04:10.25#ibcon#about to read 3, iclass 36, count 0 2006.176.08:04:10.27#ibcon#read 3, iclass 36, count 0 2006.176.08:04:10.27#ibcon#about to read 4, iclass 36, count 0 2006.176.08:04:10.27#ibcon#read 4, iclass 36, count 0 2006.176.08:04:10.27#ibcon#about to read 5, iclass 36, count 0 2006.176.08:04:10.27#ibcon#read 5, iclass 36, count 0 2006.176.08:04:10.27#ibcon#about to read 6, iclass 36, count 0 2006.176.08:04:10.27#ibcon#read 6, iclass 36, count 0 2006.176.08:04:10.27#ibcon#end of sib2, iclass 36, count 0 2006.176.08:04:10.27#ibcon#*mode == 0, iclass 36, count 0 2006.176.08:04:10.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.08:04:10.27#ibcon#[25=USB\r\n] 2006.176.08:04:10.27#ibcon#*before write, iclass 36, count 0 2006.176.08:04:10.27#ibcon#enter sib2, iclass 36, count 0 2006.176.08:04:10.27#ibcon#flushed, iclass 36, count 0 2006.176.08:04:10.27#ibcon#about to write, iclass 36, count 0 2006.176.08:04:10.27#ibcon#wrote, iclass 36, count 0 2006.176.08:04:10.27#ibcon#about to read 3, iclass 36, count 0 2006.176.08:04:10.30#ibcon#read 3, iclass 36, count 0 2006.176.08:04:10.30#ibcon#about to read 4, iclass 36, count 0 2006.176.08:04:10.30#ibcon#read 4, iclass 36, count 0 2006.176.08:04:10.30#ibcon#about to read 5, iclass 36, count 0 2006.176.08:04:10.30#ibcon#read 5, iclass 36, count 0 2006.176.08:04:10.30#ibcon#about to read 6, iclass 36, count 0 2006.176.08:04:10.30#ibcon#read 6, iclass 36, count 0 2006.176.08:04:10.30#ibcon#end of sib2, iclass 36, count 0 2006.176.08:04:10.30#ibcon#*after write, iclass 36, count 0 2006.176.08:04:10.30#ibcon#*before return 0, iclass 36, count 0 2006.176.08:04:10.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:04:10.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:04:10.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.08:04:10.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.08:04:10.30$vc4f8/valo=8,852.99 2006.176.08:04:10.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.08:04:10.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.08:04:10.30#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:10.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:04:10.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:04:10.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:04:10.30#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:04:10.30#ibcon#first serial, iclass 38, count 0 2006.176.08:04:10.30#ibcon#enter sib2, iclass 38, count 0 2006.176.08:04:10.30#ibcon#flushed, iclass 38, count 0 2006.176.08:04:10.30#ibcon#about to write, iclass 38, count 0 2006.176.08:04:10.30#ibcon#wrote, iclass 38, count 0 2006.176.08:04:10.30#ibcon#about to read 3, iclass 38, count 0 2006.176.08:04:10.32#ibcon#read 3, iclass 38, count 0 2006.176.08:04:10.32#ibcon#about to read 4, iclass 38, count 0 2006.176.08:04:10.32#ibcon#read 4, iclass 38, count 0 2006.176.08:04:10.32#ibcon#about to read 5, iclass 38, count 0 2006.176.08:04:10.32#ibcon#read 5, iclass 38, count 0 2006.176.08:04:10.32#ibcon#about to read 6, iclass 38, count 0 2006.176.08:04:10.32#ibcon#read 6, iclass 38, count 0 2006.176.08:04:10.32#ibcon#end of sib2, iclass 38, count 0 2006.176.08:04:10.32#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:04:10.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:04:10.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:04:10.32#ibcon#*before write, iclass 38, count 0 2006.176.08:04:10.32#ibcon#enter sib2, iclass 38, count 0 2006.176.08:04:10.32#ibcon#flushed, iclass 38, count 0 2006.176.08:04:10.32#ibcon#about to write, iclass 38, count 0 2006.176.08:04:10.32#ibcon#wrote, iclass 38, count 0 2006.176.08:04:10.32#ibcon#about to read 3, iclass 38, count 0 2006.176.08:04:10.36#ibcon#read 3, iclass 38, count 0 2006.176.08:04:10.36#ibcon#about to read 4, iclass 38, count 0 2006.176.08:04:10.36#ibcon#read 4, iclass 38, count 0 2006.176.08:04:10.36#ibcon#about to read 5, iclass 38, count 0 2006.176.08:04:10.36#ibcon#read 5, iclass 38, count 0 2006.176.08:04:10.36#ibcon#about to read 6, iclass 38, count 0 2006.176.08:04:10.36#ibcon#read 6, iclass 38, count 0 2006.176.08:04:10.36#ibcon#end of sib2, iclass 38, count 0 2006.176.08:04:10.36#ibcon#*after write, iclass 38, count 0 2006.176.08:04:10.36#ibcon#*before return 0, iclass 38, count 0 2006.176.08:04:10.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:04:10.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:04:10.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:04:10.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:04:10.36$vc4f8/va=8,6 2006.176.08:04:10.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.08:04:10.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.08:04:10.36#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:10.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:04:10.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:04:10.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:04:10.42#ibcon#enter wrdev, iclass 40, count 2 2006.176.08:04:10.42#ibcon#first serial, iclass 40, count 2 2006.176.08:04:10.42#ibcon#enter sib2, iclass 40, count 2 2006.176.08:04:10.42#ibcon#flushed, iclass 40, count 2 2006.176.08:04:10.42#ibcon#about to write, iclass 40, count 2 2006.176.08:04:10.42#ibcon#wrote, iclass 40, count 2 2006.176.08:04:10.42#ibcon#about to read 3, iclass 40, count 2 2006.176.08:04:10.44#ibcon#read 3, iclass 40, count 2 2006.176.08:04:10.44#ibcon#about to read 4, iclass 40, count 2 2006.176.08:04:10.44#ibcon#read 4, iclass 40, count 2 2006.176.08:04:10.44#ibcon#about to read 5, iclass 40, count 2 2006.176.08:04:10.44#ibcon#read 5, iclass 40, count 2 2006.176.08:04:10.44#ibcon#about to read 6, iclass 40, count 2 2006.176.08:04:10.44#ibcon#read 6, iclass 40, count 2 2006.176.08:04:10.44#ibcon#end of sib2, iclass 40, count 2 2006.176.08:04:10.44#ibcon#*mode == 0, iclass 40, count 2 2006.176.08:04:10.44#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.08:04:10.44#ibcon#[25=AT08-06\r\n] 2006.176.08:04:10.44#ibcon#*before write, iclass 40, count 2 2006.176.08:04:10.44#ibcon#enter sib2, iclass 40, count 2 2006.176.08:04:10.44#ibcon#flushed, iclass 40, count 2 2006.176.08:04:10.44#ibcon#about to write, iclass 40, count 2 2006.176.08:04:10.44#ibcon#wrote, iclass 40, count 2 2006.176.08:04:10.44#ibcon#about to read 3, iclass 40, count 2 2006.176.08:04:10.47#ibcon#read 3, iclass 40, count 2 2006.176.08:04:10.47#ibcon#about to read 4, iclass 40, count 2 2006.176.08:04:10.47#ibcon#read 4, iclass 40, count 2 2006.176.08:04:10.47#ibcon#about to read 5, iclass 40, count 2 2006.176.08:04:10.47#ibcon#read 5, iclass 40, count 2 2006.176.08:04:10.47#ibcon#about to read 6, iclass 40, count 2 2006.176.08:04:10.47#ibcon#read 6, iclass 40, count 2 2006.176.08:04:10.47#ibcon#end of sib2, iclass 40, count 2 2006.176.08:04:10.47#ibcon#*after write, iclass 40, count 2 2006.176.08:04:10.47#ibcon#*before return 0, iclass 40, count 2 2006.176.08:04:10.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:04:10.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:04:10.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.08:04:10.47#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:10.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:04:10.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:04:10.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:04:10.59#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:04:10.59#ibcon#first serial, iclass 40, count 0 2006.176.08:04:10.59#ibcon#enter sib2, iclass 40, count 0 2006.176.08:04:10.59#ibcon#flushed, iclass 40, count 0 2006.176.08:04:10.59#ibcon#about to write, iclass 40, count 0 2006.176.08:04:10.59#ibcon#wrote, iclass 40, count 0 2006.176.08:04:10.59#ibcon#about to read 3, iclass 40, count 0 2006.176.08:04:10.61#ibcon#read 3, iclass 40, count 0 2006.176.08:04:10.61#ibcon#about to read 4, iclass 40, count 0 2006.176.08:04:10.61#ibcon#read 4, iclass 40, count 0 2006.176.08:04:10.61#ibcon#about to read 5, iclass 40, count 0 2006.176.08:04:10.61#ibcon#read 5, iclass 40, count 0 2006.176.08:04:10.61#ibcon#about to read 6, iclass 40, count 0 2006.176.08:04:10.61#ibcon#read 6, iclass 40, count 0 2006.176.08:04:10.61#ibcon#end of sib2, iclass 40, count 0 2006.176.08:04:10.61#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:04:10.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:04:10.61#ibcon#[25=USB\r\n] 2006.176.08:04:10.61#ibcon#*before write, iclass 40, count 0 2006.176.08:04:10.61#ibcon#enter sib2, iclass 40, count 0 2006.176.08:04:10.61#ibcon#flushed, iclass 40, count 0 2006.176.08:04:10.61#ibcon#about to write, iclass 40, count 0 2006.176.08:04:10.61#ibcon#wrote, iclass 40, count 0 2006.176.08:04:10.61#ibcon#about to read 3, iclass 40, count 0 2006.176.08:04:10.64#ibcon#read 3, iclass 40, count 0 2006.176.08:04:10.64#ibcon#about to read 4, iclass 40, count 0 2006.176.08:04:10.64#ibcon#read 4, iclass 40, count 0 2006.176.08:04:10.64#ibcon#about to read 5, iclass 40, count 0 2006.176.08:04:10.64#ibcon#read 5, iclass 40, count 0 2006.176.08:04:10.64#ibcon#about to read 6, iclass 40, count 0 2006.176.08:04:10.64#ibcon#read 6, iclass 40, count 0 2006.176.08:04:10.64#ibcon#end of sib2, iclass 40, count 0 2006.176.08:04:10.64#ibcon#*after write, iclass 40, count 0 2006.176.08:04:10.64#ibcon#*before return 0, iclass 40, count 0 2006.176.08:04:10.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:04:10.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:04:10.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:04:10.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:04:10.64$vc4f8/vblo=1,632.99 2006.176.08:04:10.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.08:04:10.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.08:04:10.64#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:10.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:04:10.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:04:10.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:04:10.64#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:04:10.64#ibcon#first serial, iclass 4, count 0 2006.176.08:04:10.64#ibcon#enter sib2, iclass 4, count 0 2006.176.08:04:10.64#ibcon#flushed, iclass 4, count 0 2006.176.08:04:10.64#ibcon#about to write, iclass 4, count 0 2006.176.08:04:10.64#ibcon#wrote, iclass 4, count 0 2006.176.08:04:10.64#ibcon#about to read 3, iclass 4, count 0 2006.176.08:04:10.66#ibcon#read 3, iclass 4, count 0 2006.176.08:04:10.66#ibcon#about to read 4, iclass 4, count 0 2006.176.08:04:10.66#ibcon#read 4, iclass 4, count 0 2006.176.08:04:10.66#ibcon#about to read 5, iclass 4, count 0 2006.176.08:04:10.66#ibcon#read 5, iclass 4, count 0 2006.176.08:04:10.66#ibcon#about to read 6, iclass 4, count 0 2006.176.08:04:10.66#ibcon#read 6, iclass 4, count 0 2006.176.08:04:10.66#ibcon#end of sib2, iclass 4, count 0 2006.176.08:04:10.66#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:04:10.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:04:10.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:04:10.66#ibcon#*before write, iclass 4, count 0 2006.176.08:04:10.66#ibcon#enter sib2, iclass 4, count 0 2006.176.08:04:10.66#ibcon#flushed, iclass 4, count 0 2006.176.08:04:10.66#ibcon#about to write, iclass 4, count 0 2006.176.08:04:10.66#ibcon#wrote, iclass 4, count 0 2006.176.08:04:10.66#ibcon#about to read 3, iclass 4, count 0 2006.176.08:04:10.70#ibcon#read 3, iclass 4, count 0 2006.176.08:04:10.70#ibcon#about to read 4, iclass 4, count 0 2006.176.08:04:10.70#ibcon#read 4, iclass 4, count 0 2006.176.08:04:10.70#ibcon#about to read 5, iclass 4, count 0 2006.176.08:04:10.70#ibcon#read 5, iclass 4, count 0 2006.176.08:04:10.70#ibcon#about to read 6, iclass 4, count 0 2006.176.08:04:10.70#ibcon#read 6, iclass 4, count 0 2006.176.08:04:10.70#ibcon#end of sib2, iclass 4, count 0 2006.176.08:04:10.70#ibcon#*after write, iclass 4, count 0 2006.176.08:04:10.70#ibcon#*before return 0, iclass 4, count 0 2006.176.08:04:10.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:04:10.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:04:10.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:04:10.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:04:10.70$vc4f8/vb=1,4 2006.176.08:04:10.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.08:04:10.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.08:04:10.70#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:10.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:04:10.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:04:10.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:04:10.70#ibcon#enter wrdev, iclass 6, count 2 2006.176.08:04:10.70#ibcon#first serial, iclass 6, count 2 2006.176.08:04:10.70#ibcon#enter sib2, iclass 6, count 2 2006.176.08:04:10.70#ibcon#flushed, iclass 6, count 2 2006.176.08:04:10.70#ibcon#about to write, iclass 6, count 2 2006.176.08:04:10.70#ibcon#wrote, iclass 6, count 2 2006.176.08:04:10.70#ibcon#about to read 3, iclass 6, count 2 2006.176.08:04:10.72#ibcon#read 3, iclass 6, count 2 2006.176.08:04:10.72#ibcon#about to read 4, iclass 6, count 2 2006.176.08:04:10.72#ibcon#read 4, iclass 6, count 2 2006.176.08:04:10.72#ibcon#about to read 5, iclass 6, count 2 2006.176.08:04:10.72#ibcon#read 5, iclass 6, count 2 2006.176.08:04:10.72#ibcon#about to read 6, iclass 6, count 2 2006.176.08:04:10.72#ibcon#read 6, iclass 6, count 2 2006.176.08:04:10.72#ibcon#end of sib2, iclass 6, count 2 2006.176.08:04:10.72#ibcon#*mode == 0, iclass 6, count 2 2006.176.08:04:10.72#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.08:04:10.72#ibcon#[27=AT01-04\r\n] 2006.176.08:04:10.72#ibcon#*before write, iclass 6, count 2 2006.176.08:04:10.72#ibcon#enter sib2, iclass 6, count 2 2006.176.08:04:10.72#ibcon#flushed, iclass 6, count 2 2006.176.08:04:10.72#ibcon#about to write, iclass 6, count 2 2006.176.08:04:10.72#ibcon#wrote, iclass 6, count 2 2006.176.08:04:10.72#ibcon#about to read 3, iclass 6, count 2 2006.176.08:04:10.75#ibcon#read 3, iclass 6, count 2 2006.176.08:04:10.75#ibcon#about to read 4, iclass 6, count 2 2006.176.08:04:10.75#ibcon#read 4, iclass 6, count 2 2006.176.08:04:10.75#ibcon#about to read 5, iclass 6, count 2 2006.176.08:04:10.75#ibcon#read 5, iclass 6, count 2 2006.176.08:04:10.75#ibcon#about to read 6, iclass 6, count 2 2006.176.08:04:10.75#ibcon#read 6, iclass 6, count 2 2006.176.08:04:10.75#ibcon#end of sib2, iclass 6, count 2 2006.176.08:04:10.75#ibcon#*after write, iclass 6, count 2 2006.176.08:04:10.75#ibcon#*before return 0, iclass 6, count 2 2006.176.08:04:10.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:04:10.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:04:10.75#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.08:04:10.75#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:10.75#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:04:10.87#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:04:10.87#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:04:10.87#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:04:10.87#ibcon#first serial, iclass 6, count 0 2006.176.08:04:10.87#ibcon#enter sib2, iclass 6, count 0 2006.176.08:04:10.87#ibcon#flushed, iclass 6, count 0 2006.176.08:04:10.87#ibcon#about to write, iclass 6, count 0 2006.176.08:04:10.87#ibcon#wrote, iclass 6, count 0 2006.176.08:04:10.87#ibcon#about to read 3, iclass 6, count 0 2006.176.08:04:10.89#ibcon#read 3, iclass 6, count 0 2006.176.08:04:10.89#ibcon#about to read 4, iclass 6, count 0 2006.176.08:04:10.89#ibcon#read 4, iclass 6, count 0 2006.176.08:04:10.89#ibcon#about to read 5, iclass 6, count 0 2006.176.08:04:10.89#ibcon#read 5, iclass 6, count 0 2006.176.08:04:10.89#ibcon#about to read 6, iclass 6, count 0 2006.176.08:04:10.89#ibcon#read 6, iclass 6, count 0 2006.176.08:04:10.89#ibcon#end of sib2, iclass 6, count 0 2006.176.08:04:10.89#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:04:10.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:04:10.89#ibcon#[27=USB\r\n] 2006.176.08:04:10.89#ibcon#*before write, iclass 6, count 0 2006.176.08:04:10.89#ibcon#enter sib2, iclass 6, count 0 2006.176.08:04:10.89#ibcon#flushed, iclass 6, count 0 2006.176.08:04:10.89#ibcon#about to write, iclass 6, count 0 2006.176.08:04:10.89#ibcon#wrote, iclass 6, count 0 2006.176.08:04:10.89#ibcon#about to read 3, iclass 6, count 0 2006.176.08:04:10.92#ibcon#read 3, iclass 6, count 0 2006.176.08:04:10.92#ibcon#about to read 4, iclass 6, count 0 2006.176.08:04:10.92#ibcon#read 4, iclass 6, count 0 2006.176.08:04:10.92#ibcon#about to read 5, iclass 6, count 0 2006.176.08:04:10.92#ibcon#read 5, iclass 6, count 0 2006.176.08:04:10.92#ibcon#about to read 6, iclass 6, count 0 2006.176.08:04:10.92#ibcon#read 6, iclass 6, count 0 2006.176.08:04:10.92#ibcon#end of sib2, iclass 6, count 0 2006.176.08:04:10.92#ibcon#*after write, iclass 6, count 0 2006.176.08:04:10.92#ibcon#*before return 0, iclass 6, count 0 2006.176.08:04:10.92#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:04:10.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:04:10.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:04:10.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:04:10.92$vc4f8/vblo=2,640.99 2006.176.08:04:10.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.08:04:10.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.08:04:10.92#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:10.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:10.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:10.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:10.92#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:04:10.92#ibcon#first serial, iclass 10, count 0 2006.176.08:04:10.92#ibcon#enter sib2, iclass 10, count 0 2006.176.08:04:10.92#ibcon#flushed, iclass 10, count 0 2006.176.08:04:10.92#ibcon#about to write, iclass 10, count 0 2006.176.08:04:10.92#ibcon#wrote, iclass 10, count 0 2006.176.08:04:10.92#ibcon#about to read 3, iclass 10, count 0 2006.176.08:04:10.94#ibcon#read 3, iclass 10, count 0 2006.176.08:04:10.94#ibcon#about to read 4, iclass 10, count 0 2006.176.08:04:10.94#ibcon#read 4, iclass 10, count 0 2006.176.08:04:10.94#ibcon#about to read 5, iclass 10, count 0 2006.176.08:04:10.94#ibcon#read 5, iclass 10, count 0 2006.176.08:04:10.94#ibcon#about to read 6, iclass 10, count 0 2006.176.08:04:10.94#ibcon#read 6, iclass 10, count 0 2006.176.08:04:10.94#ibcon#end of sib2, iclass 10, count 0 2006.176.08:04:10.94#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:04:10.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:04:10.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:04:10.94#ibcon#*before write, iclass 10, count 0 2006.176.08:04:10.94#ibcon#enter sib2, iclass 10, count 0 2006.176.08:04:10.94#ibcon#flushed, iclass 10, count 0 2006.176.08:04:10.94#ibcon#about to write, iclass 10, count 0 2006.176.08:04:10.94#ibcon#wrote, iclass 10, count 0 2006.176.08:04:10.94#ibcon#about to read 3, iclass 10, count 0 2006.176.08:04:10.98#ibcon#read 3, iclass 10, count 0 2006.176.08:04:10.98#ibcon#about to read 4, iclass 10, count 0 2006.176.08:04:10.98#ibcon#read 4, iclass 10, count 0 2006.176.08:04:10.98#ibcon#about to read 5, iclass 10, count 0 2006.176.08:04:10.98#ibcon#read 5, iclass 10, count 0 2006.176.08:04:10.98#ibcon#about to read 6, iclass 10, count 0 2006.176.08:04:10.98#ibcon#read 6, iclass 10, count 0 2006.176.08:04:10.98#ibcon#end of sib2, iclass 10, count 0 2006.176.08:04:10.98#ibcon#*after write, iclass 10, count 0 2006.176.08:04:10.98#ibcon#*before return 0, iclass 10, count 0 2006.176.08:04:10.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:10.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:04:10.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:04:10.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:04:10.98$vc4f8/vb=2,4 2006.176.08:04:10.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.08:04:10.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.08:04:10.98#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:10.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:11.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:11.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:11.04#ibcon#enter wrdev, iclass 12, count 2 2006.176.08:04:11.04#ibcon#first serial, iclass 12, count 2 2006.176.08:04:11.04#ibcon#enter sib2, iclass 12, count 2 2006.176.08:04:11.04#ibcon#flushed, iclass 12, count 2 2006.176.08:04:11.04#ibcon#about to write, iclass 12, count 2 2006.176.08:04:11.04#ibcon#wrote, iclass 12, count 2 2006.176.08:04:11.04#ibcon#about to read 3, iclass 12, count 2 2006.176.08:04:11.06#ibcon#read 3, iclass 12, count 2 2006.176.08:04:11.06#ibcon#about to read 4, iclass 12, count 2 2006.176.08:04:11.06#ibcon#read 4, iclass 12, count 2 2006.176.08:04:11.06#ibcon#about to read 5, iclass 12, count 2 2006.176.08:04:11.06#ibcon#read 5, iclass 12, count 2 2006.176.08:04:11.06#ibcon#about to read 6, iclass 12, count 2 2006.176.08:04:11.06#ibcon#read 6, iclass 12, count 2 2006.176.08:04:11.06#ibcon#end of sib2, iclass 12, count 2 2006.176.08:04:11.06#ibcon#*mode == 0, iclass 12, count 2 2006.176.08:04:11.06#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.08:04:11.06#ibcon#[27=AT02-04\r\n] 2006.176.08:04:11.06#ibcon#*before write, iclass 12, count 2 2006.176.08:04:11.06#ibcon#enter sib2, iclass 12, count 2 2006.176.08:04:11.06#ibcon#flushed, iclass 12, count 2 2006.176.08:04:11.06#ibcon#about to write, iclass 12, count 2 2006.176.08:04:11.06#ibcon#wrote, iclass 12, count 2 2006.176.08:04:11.06#ibcon#about to read 3, iclass 12, count 2 2006.176.08:04:11.09#ibcon#read 3, iclass 12, count 2 2006.176.08:04:11.09#ibcon#about to read 4, iclass 12, count 2 2006.176.08:04:11.09#ibcon#read 4, iclass 12, count 2 2006.176.08:04:11.09#ibcon#about to read 5, iclass 12, count 2 2006.176.08:04:11.09#ibcon#read 5, iclass 12, count 2 2006.176.08:04:11.09#ibcon#about to read 6, iclass 12, count 2 2006.176.08:04:11.09#ibcon#read 6, iclass 12, count 2 2006.176.08:04:11.09#ibcon#end of sib2, iclass 12, count 2 2006.176.08:04:11.09#ibcon#*after write, iclass 12, count 2 2006.176.08:04:11.09#ibcon#*before return 0, iclass 12, count 2 2006.176.08:04:11.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:11.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:04:11.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.08:04:11.09#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:11.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:11.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:11.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:11.21#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:04:11.21#ibcon#first serial, iclass 12, count 0 2006.176.08:04:11.21#ibcon#enter sib2, iclass 12, count 0 2006.176.08:04:11.21#ibcon#flushed, iclass 12, count 0 2006.176.08:04:11.21#ibcon#about to write, iclass 12, count 0 2006.176.08:04:11.21#ibcon#wrote, iclass 12, count 0 2006.176.08:04:11.21#ibcon#about to read 3, iclass 12, count 0 2006.176.08:04:11.23#ibcon#read 3, iclass 12, count 0 2006.176.08:04:11.23#ibcon#about to read 4, iclass 12, count 0 2006.176.08:04:11.23#ibcon#read 4, iclass 12, count 0 2006.176.08:04:11.23#ibcon#about to read 5, iclass 12, count 0 2006.176.08:04:11.23#ibcon#read 5, iclass 12, count 0 2006.176.08:04:11.23#ibcon#about to read 6, iclass 12, count 0 2006.176.08:04:11.23#ibcon#read 6, iclass 12, count 0 2006.176.08:04:11.23#ibcon#end of sib2, iclass 12, count 0 2006.176.08:04:11.23#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:04:11.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:04:11.23#ibcon#[27=USB\r\n] 2006.176.08:04:11.23#ibcon#*before write, iclass 12, count 0 2006.176.08:04:11.23#ibcon#enter sib2, iclass 12, count 0 2006.176.08:04:11.23#ibcon#flushed, iclass 12, count 0 2006.176.08:04:11.23#ibcon#about to write, iclass 12, count 0 2006.176.08:04:11.23#ibcon#wrote, iclass 12, count 0 2006.176.08:04:11.23#ibcon#about to read 3, iclass 12, count 0 2006.176.08:04:11.26#ibcon#read 3, iclass 12, count 0 2006.176.08:04:11.26#ibcon#about to read 4, iclass 12, count 0 2006.176.08:04:11.26#ibcon#read 4, iclass 12, count 0 2006.176.08:04:11.26#ibcon#about to read 5, iclass 12, count 0 2006.176.08:04:11.26#ibcon#read 5, iclass 12, count 0 2006.176.08:04:11.26#ibcon#about to read 6, iclass 12, count 0 2006.176.08:04:11.26#ibcon#read 6, iclass 12, count 0 2006.176.08:04:11.26#ibcon#end of sib2, iclass 12, count 0 2006.176.08:04:11.26#ibcon#*after write, iclass 12, count 0 2006.176.08:04:11.26#ibcon#*before return 0, iclass 12, count 0 2006.176.08:04:11.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:11.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:04:11.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:04:11.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:04:11.26$vc4f8/vblo=3,656.99 2006.176.08:04:11.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.08:04:11.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.08:04:11.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:11.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:11.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:11.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:11.26#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:04:11.26#ibcon#first serial, iclass 14, count 0 2006.176.08:04:11.26#ibcon#enter sib2, iclass 14, count 0 2006.176.08:04:11.26#ibcon#flushed, iclass 14, count 0 2006.176.08:04:11.26#ibcon#about to write, iclass 14, count 0 2006.176.08:04:11.26#ibcon#wrote, iclass 14, count 0 2006.176.08:04:11.26#ibcon#about to read 3, iclass 14, count 0 2006.176.08:04:11.28#ibcon#read 3, iclass 14, count 0 2006.176.08:04:11.28#ibcon#about to read 4, iclass 14, count 0 2006.176.08:04:11.28#ibcon#read 4, iclass 14, count 0 2006.176.08:04:11.28#ibcon#about to read 5, iclass 14, count 0 2006.176.08:04:11.28#ibcon#read 5, iclass 14, count 0 2006.176.08:04:11.28#ibcon#about to read 6, iclass 14, count 0 2006.176.08:04:11.28#ibcon#read 6, iclass 14, count 0 2006.176.08:04:11.28#ibcon#end of sib2, iclass 14, count 0 2006.176.08:04:11.28#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:04:11.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:04:11.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:04:11.28#ibcon#*before write, iclass 14, count 0 2006.176.08:04:11.28#ibcon#enter sib2, iclass 14, count 0 2006.176.08:04:11.28#ibcon#flushed, iclass 14, count 0 2006.176.08:04:11.28#ibcon#about to write, iclass 14, count 0 2006.176.08:04:11.28#ibcon#wrote, iclass 14, count 0 2006.176.08:04:11.28#ibcon#about to read 3, iclass 14, count 0 2006.176.08:04:11.32#ibcon#read 3, iclass 14, count 0 2006.176.08:04:11.32#ibcon#about to read 4, iclass 14, count 0 2006.176.08:04:11.32#ibcon#read 4, iclass 14, count 0 2006.176.08:04:11.32#ibcon#about to read 5, iclass 14, count 0 2006.176.08:04:11.32#ibcon#read 5, iclass 14, count 0 2006.176.08:04:11.32#ibcon#about to read 6, iclass 14, count 0 2006.176.08:04:11.32#ibcon#read 6, iclass 14, count 0 2006.176.08:04:11.32#ibcon#end of sib2, iclass 14, count 0 2006.176.08:04:11.32#ibcon#*after write, iclass 14, count 0 2006.176.08:04:11.32#ibcon#*before return 0, iclass 14, count 0 2006.176.08:04:11.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:11.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:04:11.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:04:11.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:04:11.32$vc4f8/vb=3,4 2006.176.08:04:11.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.08:04:11.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.08:04:11.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:11.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:11.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:11.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:11.38#ibcon#enter wrdev, iclass 16, count 2 2006.176.08:04:11.38#ibcon#first serial, iclass 16, count 2 2006.176.08:04:11.38#ibcon#enter sib2, iclass 16, count 2 2006.176.08:04:11.38#ibcon#flushed, iclass 16, count 2 2006.176.08:04:11.38#ibcon#about to write, iclass 16, count 2 2006.176.08:04:11.38#ibcon#wrote, iclass 16, count 2 2006.176.08:04:11.38#ibcon#about to read 3, iclass 16, count 2 2006.176.08:04:11.40#ibcon#read 3, iclass 16, count 2 2006.176.08:04:11.40#ibcon#about to read 4, iclass 16, count 2 2006.176.08:04:11.40#ibcon#read 4, iclass 16, count 2 2006.176.08:04:11.40#ibcon#about to read 5, iclass 16, count 2 2006.176.08:04:11.40#ibcon#read 5, iclass 16, count 2 2006.176.08:04:11.40#ibcon#about to read 6, iclass 16, count 2 2006.176.08:04:11.40#ibcon#read 6, iclass 16, count 2 2006.176.08:04:11.40#ibcon#end of sib2, iclass 16, count 2 2006.176.08:04:11.40#ibcon#*mode == 0, iclass 16, count 2 2006.176.08:04:11.40#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.08:04:11.40#ibcon#[27=AT03-04\r\n] 2006.176.08:04:11.40#ibcon#*before write, iclass 16, count 2 2006.176.08:04:11.40#ibcon#enter sib2, iclass 16, count 2 2006.176.08:04:11.40#ibcon#flushed, iclass 16, count 2 2006.176.08:04:11.40#ibcon#about to write, iclass 16, count 2 2006.176.08:04:11.40#ibcon#wrote, iclass 16, count 2 2006.176.08:04:11.40#ibcon#about to read 3, iclass 16, count 2 2006.176.08:04:11.44#ibcon#read 3, iclass 16, count 2 2006.176.08:04:11.44#ibcon#about to read 4, iclass 16, count 2 2006.176.08:04:11.44#ibcon#read 4, iclass 16, count 2 2006.176.08:04:11.44#ibcon#about to read 5, iclass 16, count 2 2006.176.08:04:11.44#ibcon#read 5, iclass 16, count 2 2006.176.08:04:11.44#ibcon#about to read 6, iclass 16, count 2 2006.176.08:04:11.44#ibcon#read 6, iclass 16, count 2 2006.176.08:04:11.44#ibcon#end of sib2, iclass 16, count 2 2006.176.08:04:11.44#ibcon#*after write, iclass 16, count 2 2006.176.08:04:11.44#ibcon#*before return 0, iclass 16, count 2 2006.176.08:04:11.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:11.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:04:11.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.08:04:11.44#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:11.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:11.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:11.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:11.55#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:04:11.55#ibcon#first serial, iclass 16, count 0 2006.176.08:04:11.55#ibcon#enter sib2, iclass 16, count 0 2006.176.08:04:11.55#ibcon#flushed, iclass 16, count 0 2006.176.08:04:11.55#ibcon#about to write, iclass 16, count 0 2006.176.08:04:11.55#ibcon#wrote, iclass 16, count 0 2006.176.08:04:11.55#ibcon#about to read 3, iclass 16, count 0 2006.176.08:04:11.57#ibcon#read 3, iclass 16, count 0 2006.176.08:04:11.57#ibcon#about to read 4, iclass 16, count 0 2006.176.08:04:11.57#ibcon#read 4, iclass 16, count 0 2006.176.08:04:11.57#ibcon#about to read 5, iclass 16, count 0 2006.176.08:04:11.57#ibcon#read 5, iclass 16, count 0 2006.176.08:04:11.57#ibcon#about to read 6, iclass 16, count 0 2006.176.08:04:11.57#ibcon#read 6, iclass 16, count 0 2006.176.08:04:11.57#ibcon#end of sib2, iclass 16, count 0 2006.176.08:04:11.57#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:04:11.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:04:11.57#ibcon#[27=USB\r\n] 2006.176.08:04:11.57#ibcon#*before write, iclass 16, count 0 2006.176.08:04:11.57#ibcon#enter sib2, iclass 16, count 0 2006.176.08:04:11.57#ibcon#flushed, iclass 16, count 0 2006.176.08:04:11.57#ibcon#about to write, iclass 16, count 0 2006.176.08:04:11.57#ibcon#wrote, iclass 16, count 0 2006.176.08:04:11.57#ibcon#about to read 3, iclass 16, count 0 2006.176.08:04:11.60#ibcon#read 3, iclass 16, count 0 2006.176.08:04:11.60#ibcon#about to read 4, iclass 16, count 0 2006.176.08:04:11.60#ibcon#read 4, iclass 16, count 0 2006.176.08:04:11.60#ibcon#about to read 5, iclass 16, count 0 2006.176.08:04:11.60#ibcon#read 5, iclass 16, count 0 2006.176.08:04:11.60#ibcon#about to read 6, iclass 16, count 0 2006.176.08:04:11.60#ibcon#read 6, iclass 16, count 0 2006.176.08:04:11.60#ibcon#end of sib2, iclass 16, count 0 2006.176.08:04:11.60#ibcon#*after write, iclass 16, count 0 2006.176.08:04:11.60#ibcon#*before return 0, iclass 16, count 0 2006.176.08:04:11.60#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:11.60#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:04:11.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:04:11.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:04:11.60$vc4f8/vblo=4,712.99 2006.176.08:04:11.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.08:04:11.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.08:04:11.60#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:11.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:11.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:11.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:11.60#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:04:11.60#ibcon#first serial, iclass 18, count 0 2006.176.08:04:11.60#ibcon#enter sib2, iclass 18, count 0 2006.176.08:04:11.60#ibcon#flushed, iclass 18, count 0 2006.176.08:04:11.60#ibcon#about to write, iclass 18, count 0 2006.176.08:04:11.60#ibcon#wrote, iclass 18, count 0 2006.176.08:04:11.60#ibcon#about to read 3, iclass 18, count 0 2006.176.08:04:11.62#ibcon#read 3, iclass 18, count 0 2006.176.08:04:11.62#ibcon#about to read 4, iclass 18, count 0 2006.176.08:04:11.62#ibcon#read 4, iclass 18, count 0 2006.176.08:04:11.62#ibcon#about to read 5, iclass 18, count 0 2006.176.08:04:11.62#ibcon#read 5, iclass 18, count 0 2006.176.08:04:11.62#ibcon#about to read 6, iclass 18, count 0 2006.176.08:04:11.62#ibcon#read 6, iclass 18, count 0 2006.176.08:04:11.62#ibcon#end of sib2, iclass 18, count 0 2006.176.08:04:11.62#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:04:11.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:04:11.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:04:11.62#ibcon#*before write, iclass 18, count 0 2006.176.08:04:11.62#ibcon#enter sib2, iclass 18, count 0 2006.176.08:04:11.62#ibcon#flushed, iclass 18, count 0 2006.176.08:04:11.62#ibcon#about to write, iclass 18, count 0 2006.176.08:04:11.62#ibcon#wrote, iclass 18, count 0 2006.176.08:04:11.62#ibcon#about to read 3, iclass 18, count 0 2006.176.08:04:11.66#ibcon#read 3, iclass 18, count 0 2006.176.08:04:11.66#ibcon#about to read 4, iclass 18, count 0 2006.176.08:04:11.66#ibcon#read 4, iclass 18, count 0 2006.176.08:04:11.66#ibcon#about to read 5, iclass 18, count 0 2006.176.08:04:11.66#ibcon#read 5, iclass 18, count 0 2006.176.08:04:11.66#ibcon#about to read 6, iclass 18, count 0 2006.176.08:04:11.66#ibcon#read 6, iclass 18, count 0 2006.176.08:04:11.66#ibcon#end of sib2, iclass 18, count 0 2006.176.08:04:11.66#ibcon#*after write, iclass 18, count 0 2006.176.08:04:11.66#ibcon#*before return 0, iclass 18, count 0 2006.176.08:04:11.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:11.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:04:11.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:04:11.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:04:11.66$vc4f8/vb=4,4 2006.176.08:04:11.66#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.08:04:11.66#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.08:04:11.66#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:11.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:11.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:11.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:11.72#ibcon#enter wrdev, iclass 20, count 2 2006.176.08:04:11.72#ibcon#first serial, iclass 20, count 2 2006.176.08:04:11.72#ibcon#enter sib2, iclass 20, count 2 2006.176.08:04:11.72#ibcon#flushed, iclass 20, count 2 2006.176.08:04:11.72#ibcon#about to write, iclass 20, count 2 2006.176.08:04:11.72#ibcon#wrote, iclass 20, count 2 2006.176.08:04:11.72#ibcon#about to read 3, iclass 20, count 2 2006.176.08:04:11.74#ibcon#read 3, iclass 20, count 2 2006.176.08:04:11.74#ibcon#about to read 4, iclass 20, count 2 2006.176.08:04:11.74#ibcon#read 4, iclass 20, count 2 2006.176.08:04:11.74#ibcon#about to read 5, iclass 20, count 2 2006.176.08:04:11.74#ibcon#read 5, iclass 20, count 2 2006.176.08:04:11.74#ibcon#about to read 6, iclass 20, count 2 2006.176.08:04:11.74#ibcon#read 6, iclass 20, count 2 2006.176.08:04:11.74#ibcon#end of sib2, iclass 20, count 2 2006.176.08:04:11.74#ibcon#*mode == 0, iclass 20, count 2 2006.176.08:04:11.74#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.08:04:11.74#ibcon#[27=AT04-04\r\n] 2006.176.08:04:11.74#ibcon#*before write, iclass 20, count 2 2006.176.08:04:11.74#ibcon#enter sib2, iclass 20, count 2 2006.176.08:04:11.74#ibcon#flushed, iclass 20, count 2 2006.176.08:04:11.74#ibcon#about to write, iclass 20, count 2 2006.176.08:04:11.74#ibcon#wrote, iclass 20, count 2 2006.176.08:04:11.74#ibcon#about to read 3, iclass 20, count 2 2006.176.08:04:11.77#ibcon#read 3, iclass 20, count 2 2006.176.08:04:11.77#ibcon#about to read 4, iclass 20, count 2 2006.176.08:04:11.77#ibcon#read 4, iclass 20, count 2 2006.176.08:04:11.77#ibcon#about to read 5, iclass 20, count 2 2006.176.08:04:11.77#ibcon#read 5, iclass 20, count 2 2006.176.08:04:11.77#ibcon#about to read 6, iclass 20, count 2 2006.176.08:04:11.77#ibcon#read 6, iclass 20, count 2 2006.176.08:04:11.77#ibcon#end of sib2, iclass 20, count 2 2006.176.08:04:11.77#ibcon#*after write, iclass 20, count 2 2006.176.08:04:11.77#ibcon#*before return 0, iclass 20, count 2 2006.176.08:04:11.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:11.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:04:11.77#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.08:04:11.77#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:11.77#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:11.89#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:11.89#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:11.89#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:04:11.89#ibcon#first serial, iclass 20, count 0 2006.176.08:04:11.89#ibcon#enter sib2, iclass 20, count 0 2006.176.08:04:11.89#ibcon#flushed, iclass 20, count 0 2006.176.08:04:11.89#ibcon#about to write, iclass 20, count 0 2006.176.08:04:11.89#ibcon#wrote, iclass 20, count 0 2006.176.08:04:11.89#ibcon#about to read 3, iclass 20, count 0 2006.176.08:04:11.91#ibcon#read 3, iclass 20, count 0 2006.176.08:04:11.91#ibcon#about to read 4, iclass 20, count 0 2006.176.08:04:11.91#ibcon#read 4, iclass 20, count 0 2006.176.08:04:11.91#ibcon#about to read 5, iclass 20, count 0 2006.176.08:04:11.91#ibcon#read 5, iclass 20, count 0 2006.176.08:04:11.91#ibcon#about to read 6, iclass 20, count 0 2006.176.08:04:11.91#ibcon#read 6, iclass 20, count 0 2006.176.08:04:11.91#ibcon#end of sib2, iclass 20, count 0 2006.176.08:04:11.91#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:04:11.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:04:11.91#ibcon#[27=USB\r\n] 2006.176.08:04:11.91#ibcon#*before write, iclass 20, count 0 2006.176.08:04:11.91#ibcon#enter sib2, iclass 20, count 0 2006.176.08:04:11.91#ibcon#flushed, iclass 20, count 0 2006.176.08:04:11.91#ibcon#about to write, iclass 20, count 0 2006.176.08:04:11.91#ibcon#wrote, iclass 20, count 0 2006.176.08:04:11.91#ibcon#about to read 3, iclass 20, count 0 2006.176.08:04:11.94#ibcon#read 3, iclass 20, count 0 2006.176.08:04:11.94#ibcon#about to read 4, iclass 20, count 0 2006.176.08:04:11.94#ibcon#read 4, iclass 20, count 0 2006.176.08:04:11.94#ibcon#about to read 5, iclass 20, count 0 2006.176.08:04:11.94#ibcon#read 5, iclass 20, count 0 2006.176.08:04:11.94#ibcon#about to read 6, iclass 20, count 0 2006.176.08:04:11.94#ibcon#read 6, iclass 20, count 0 2006.176.08:04:11.94#ibcon#end of sib2, iclass 20, count 0 2006.176.08:04:11.94#ibcon#*after write, iclass 20, count 0 2006.176.08:04:11.94#ibcon#*before return 0, iclass 20, count 0 2006.176.08:04:11.94#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:11.94#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:04:11.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:04:11.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:04:11.94$vc4f8/vblo=5,744.99 2006.176.08:04:11.94#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.08:04:11.94#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.08:04:11.94#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:11.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:11.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:11.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:11.94#ibcon#enter wrdev, iclass 22, count 0 2006.176.08:04:11.94#ibcon#first serial, iclass 22, count 0 2006.176.08:04:11.94#ibcon#enter sib2, iclass 22, count 0 2006.176.08:04:11.94#ibcon#flushed, iclass 22, count 0 2006.176.08:04:11.94#ibcon#about to write, iclass 22, count 0 2006.176.08:04:11.94#ibcon#wrote, iclass 22, count 0 2006.176.08:04:11.94#ibcon#about to read 3, iclass 22, count 0 2006.176.08:04:11.96#ibcon#read 3, iclass 22, count 0 2006.176.08:04:11.96#ibcon#about to read 4, iclass 22, count 0 2006.176.08:04:11.96#ibcon#read 4, iclass 22, count 0 2006.176.08:04:11.96#ibcon#about to read 5, iclass 22, count 0 2006.176.08:04:11.96#ibcon#read 5, iclass 22, count 0 2006.176.08:04:11.96#ibcon#about to read 6, iclass 22, count 0 2006.176.08:04:11.96#ibcon#read 6, iclass 22, count 0 2006.176.08:04:11.96#ibcon#end of sib2, iclass 22, count 0 2006.176.08:04:11.96#ibcon#*mode == 0, iclass 22, count 0 2006.176.08:04:11.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.08:04:11.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:04:11.96#ibcon#*before write, iclass 22, count 0 2006.176.08:04:11.96#ibcon#enter sib2, iclass 22, count 0 2006.176.08:04:11.96#ibcon#flushed, iclass 22, count 0 2006.176.08:04:11.96#ibcon#about to write, iclass 22, count 0 2006.176.08:04:11.96#ibcon#wrote, iclass 22, count 0 2006.176.08:04:11.96#ibcon#about to read 3, iclass 22, count 0 2006.176.08:04:12.00#ibcon#read 3, iclass 22, count 0 2006.176.08:04:12.00#ibcon#about to read 4, iclass 22, count 0 2006.176.08:04:12.00#ibcon#read 4, iclass 22, count 0 2006.176.08:04:12.00#ibcon#about to read 5, iclass 22, count 0 2006.176.08:04:12.00#ibcon#read 5, iclass 22, count 0 2006.176.08:04:12.00#ibcon#about to read 6, iclass 22, count 0 2006.176.08:04:12.00#ibcon#read 6, iclass 22, count 0 2006.176.08:04:12.00#ibcon#end of sib2, iclass 22, count 0 2006.176.08:04:12.00#ibcon#*after write, iclass 22, count 0 2006.176.08:04:12.00#ibcon#*before return 0, iclass 22, count 0 2006.176.08:04:12.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:12.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:04:12.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.08:04:12.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.08:04:12.00$vc4f8/vb=5,4 2006.176.08:04:12.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.08:04:12.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.08:04:12.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:12.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:12.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:12.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:12.06#ibcon#enter wrdev, iclass 24, count 2 2006.176.08:04:12.06#ibcon#first serial, iclass 24, count 2 2006.176.08:04:12.06#ibcon#enter sib2, iclass 24, count 2 2006.176.08:04:12.06#ibcon#flushed, iclass 24, count 2 2006.176.08:04:12.06#ibcon#about to write, iclass 24, count 2 2006.176.08:04:12.06#ibcon#wrote, iclass 24, count 2 2006.176.08:04:12.06#ibcon#about to read 3, iclass 24, count 2 2006.176.08:04:12.08#ibcon#read 3, iclass 24, count 2 2006.176.08:04:12.08#ibcon#about to read 4, iclass 24, count 2 2006.176.08:04:12.08#ibcon#read 4, iclass 24, count 2 2006.176.08:04:12.08#ibcon#about to read 5, iclass 24, count 2 2006.176.08:04:12.08#ibcon#read 5, iclass 24, count 2 2006.176.08:04:12.08#ibcon#about to read 6, iclass 24, count 2 2006.176.08:04:12.08#ibcon#read 6, iclass 24, count 2 2006.176.08:04:12.08#ibcon#end of sib2, iclass 24, count 2 2006.176.08:04:12.08#ibcon#*mode == 0, iclass 24, count 2 2006.176.08:04:12.08#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.08:04:12.08#ibcon#[27=AT05-04\r\n] 2006.176.08:04:12.08#ibcon#*before write, iclass 24, count 2 2006.176.08:04:12.08#ibcon#enter sib2, iclass 24, count 2 2006.176.08:04:12.08#ibcon#flushed, iclass 24, count 2 2006.176.08:04:12.08#ibcon#about to write, iclass 24, count 2 2006.176.08:04:12.08#ibcon#wrote, iclass 24, count 2 2006.176.08:04:12.08#ibcon#about to read 3, iclass 24, count 2 2006.176.08:04:12.11#ibcon#read 3, iclass 24, count 2 2006.176.08:04:12.11#ibcon#about to read 4, iclass 24, count 2 2006.176.08:04:12.11#ibcon#read 4, iclass 24, count 2 2006.176.08:04:12.11#ibcon#about to read 5, iclass 24, count 2 2006.176.08:04:12.11#ibcon#read 5, iclass 24, count 2 2006.176.08:04:12.11#ibcon#about to read 6, iclass 24, count 2 2006.176.08:04:12.11#ibcon#read 6, iclass 24, count 2 2006.176.08:04:12.11#ibcon#end of sib2, iclass 24, count 2 2006.176.08:04:12.11#ibcon#*after write, iclass 24, count 2 2006.176.08:04:12.11#ibcon#*before return 0, iclass 24, count 2 2006.176.08:04:12.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:12.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:04:12.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.08:04:12.11#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:12.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:12.23#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:12.23#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:12.23#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:04:12.23#ibcon#first serial, iclass 24, count 0 2006.176.08:04:12.23#ibcon#enter sib2, iclass 24, count 0 2006.176.08:04:12.23#ibcon#flushed, iclass 24, count 0 2006.176.08:04:12.23#ibcon#about to write, iclass 24, count 0 2006.176.08:04:12.23#ibcon#wrote, iclass 24, count 0 2006.176.08:04:12.23#ibcon#about to read 3, iclass 24, count 0 2006.176.08:04:12.25#ibcon#read 3, iclass 24, count 0 2006.176.08:04:12.25#ibcon#about to read 4, iclass 24, count 0 2006.176.08:04:12.25#ibcon#read 4, iclass 24, count 0 2006.176.08:04:12.25#ibcon#about to read 5, iclass 24, count 0 2006.176.08:04:12.25#ibcon#read 5, iclass 24, count 0 2006.176.08:04:12.25#ibcon#about to read 6, iclass 24, count 0 2006.176.08:04:12.25#ibcon#read 6, iclass 24, count 0 2006.176.08:04:12.25#ibcon#end of sib2, iclass 24, count 0 2006.176.08:04:12.25#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:04:12.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:04:12.25#ibcon#[27=USB\r\n] 2006.176.08:04:12.25#ibcon#*before write, iclass 24, count 0 2006.176.08:04:12.25#ibcon#enter sib2, iclass 24, count 0 2006.176.08:04:12.25#ibcon#flushed, iclass 24, count 0 2006.176.08:04:12.25#ibcon#about to write, iclass 24, count 0 2006.176.08:04:12.25#ibcon#wrote, iclass 24, count 0 2006.176.08:04:12.25#ibcon#about to read 3, iclass 24, count 0 2006.176.08:04:12.28#ibcon#read 3, iclass 24, count 0 2006.176.08:04:12.28#ibcon#about to read 4, iclass 24, count 0 2006.176.08:04:12.28#ibcon#read 4, iclass 24, count 0 2006.176.08:04:12.28#ibcon#about to read 5, iclass 24, count 0 2006.176.08:04:12.28#ibcon#read 5, iclass 24, count 0 2006.176.08:04:12.28#ibcon#about to read 6, iclass 24, count 0 2006.176.08:04:12.28#ibcon#read 6, iclass 24, count 0 2006.176.08:04:12.28#ibcon#end of sib2, iclass 24, count 0 2006.176.08:04:12.28#ibcon#*after write, iclass 24, count 0 2006.176.08:04:12.28#ibcon#*before return 0, iclass 24, count 0 2006.176.08:04:12.28#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:12.28#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:04:12.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:04:12.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:04:12.28$vc4f8/vblo=6,752.99 2006.176.08:04:12.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.08:04:12.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.08:04:12.28#ibcon#ireg 17 cls_cnt 0 2006.176.08:04:12.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:12.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:12.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:12.28#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:04:12.28#ibcon#first serial, iclass 26, count 0 2006.176.08:04:12.28#ibcon#enter sib2, iclass 26, count 0 2006.176.08:04:12.28#ibcon#flushed, iclass 26, count 0 2006.176.08:04:12.28#ibcon#about to write, iclass 26, count 0 2006.176.08:04:12.28#ibcon#wrote, iclass 26, count 0 2006.176.08:04:12.28#ibcon#about to read 3, iclass 26, count 0 2006.176.08:04:12.30#ibcon#read 3, iclass 26, count 0 2006.176.08:04:12.30#ibcon#about to read 4, iclass 26, count 0 2006.176.08:04:12.30#ibcon#read 4, iclass 26, count 0 2006.176.08:04:12.30#ibcon#about to read 5, iclass 26, count 0 2006.176.08:04:12.30#ibcon#read 5, iclass 26, count 0 2006.176.08:04:12.30#ibcon#about to read 6, iclass 26, count 0 2006.176.08:04:12.30#ibcon#read 6, iclass 26, count 0 2006.176.08:04:12.30#ibcon#end of sib2, iclass 26, count 0 2006.176.08:04:12.30#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:04:12.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:04:12.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:04:12.30#ibcon#*before write, iclass 26, count 0 2006.176.08:04:12.30#ibcon#enter sib2, iclass 26, count 0 2006.176.08:04:12.30#ibcon#flushed, iclass 26, count 0 2006.176.08:04:12.30#ibcon#about to write, iclass 26, count 0 2006.176.08:04:12.30#ibcon#wrote, iclass 26, count 0 2006.176.08:04:12.30#ibcon#about to read 3, iclass 26, count 0 2006.176.08:04:12.34#ibcon#read 3, iclass 26, count 0 2006.176.08:04:12.34#ibcon#about to read 4, iclass 26, count 0 2006.176.08:04:12.34#ibcon#read 4, iclass 26, count 0 2006.176.08:04:12.34#ibcon#about to read 5, iclass 26, count 0 2006.176.08:04:12.34#ibcon#read 5, iclass 26, count 0 2006.176.08:04:12.34#ibcon#about to read 6, iclass 26, count 0 2006.176.08:04:12.34#ibcon#read 6, iclass 26, count 0 2006.176.08:04:12.34#ibcon#end of sib2, iclass 26, count 0 2006.176.08:04:12.34#ibcon#*after write, iclass 26, count 0 2006.176.08:04:12.34#ibcon#*before return 0, iclass 26, count 0 2006.176.08:04:12.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:12.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:04:12.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:04:12.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:04:12.34$vc4f8/vb=6,4 2006.176.08:04:12.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.08:04:12.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.08:04:12.34#ibcon#ireg 11 cls_cnt 2 2006.176.08:04:12.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:12.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:12.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:12.40#ibcon#enter wrdev, iclass 28, count 2 2006.176.08:04:12.40#ibcon#first serial, iclass 28, count 2 2006.176.08:04:12.40#ibcon#enter sib2, iclass 28, count 2 2006.176.08:04:12.40#ibcon#flushed, iclass 28, count 2 2006.176.08:04:12.40#ibcon#about to write, iclass 28, count 2 2006.176.08:04:12.40#ibcon#wrote, iclass 28, count 2 2006.176.08:04:12.40#ibcon#about to read 3, iclass 28, count 2 2006.176.08:04:12.43#ibcon#read 3, iclass 28, count 2 2006.176.08:04:12.43#ibcon#about to read 4, iclass 28, count 2 2006.176.08:04:12.43#ibcon#read 4, iclass 28, count 2 2006.176.08:04:12.43#ibcon#about to read 5, iclass 28, count 2 2006.176.08:04:12.43#ibcon#read 5, iclass 28, count 2 2006.176.08:04:12.43#ibcon#about to read 6, iclass 28, count 2 2006.176.08:04:12.43#ibcon#read 6, iclass 28, count 2 2006.176.08:04:12.43#ibcon#end of sib2, iclass 28, count 2 2006.176.08:04:12.43#ibcon#*mode == 0, iclass 28, count 2 2006.176.08:04:12.43#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.08:04:12.43#ibcon#[27=AT06-04\r\n] 2006.176.08:04:12.43#ibcon#*before write, iclass 28, count 2 2006.176.08:04:12.43#ibcon#enter sib2, iclass 28, count 2 2006.176.08:04:12.43#ibcon#flushed, iclass 28, count 2 2006.176.08:04:12.43#ibcon#about to write, iclass 28, count 2 2006.176.08:04:12.43#ibcon#wrote, iclass 28, count 2 2006.176.08:04:12.43#ibcon#about to read 3, iclass 28, count 2 2006.176.08:04:12.45#ibcon#read 3, iclass 28, count 2 2006.176.08:04:12.45#ibcon#about to read 4, iclass 28, count 2 2006.176.08:04:12.45#ibcon#read 4, iclass 28, count 2 2006.176.08:04:12.45#ibcon#about to read 5, iclass 28, count 2 2006.176.08:04:12.45#ibcon#read 5, iclass 28, count 2 2006.176.08:04:12.45#ibcon#about to read 6, iclass 28, count 2 2006.176.08:04:12.45#ibcon#read 6, iclass 28, count 2 2006.176.08:04:12.45#ibcon#end of sib2, iclass 28, count 2 2006.176.08:04:12.45#ibcon#*after write, iclass 28, count 2 2006.176.08:04:12.45#ibcon#*before return 0, iclass 28, count 2 2006.176.08:04:12.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:12.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:04:12.45#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.08:04:12.45#ibcon#ireg 7 cls_cnt 0 2006.176.08:04:12.45#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:12.57#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:12.57#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:12.57#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:04:12.57#ibcon#first serial, iclass 28, count 0 2006.176.08:04:12.57#ibcon#enter sib2, iclass 28, count 0 2006.176.08:04:12.57#ibcon#flushed, iclass 28, count 0 2006.176.08:04:12.57#ibcon#about to write, iclass 28, count 0 2006.176.08:04:12.57#ibcon#wrote, iclass 28, count 0 2006.176.08:04:12.57#ibcon#about to read 3, iclass 28, count 0 2006.176.08:04:12.59#ibcon#read 3, iclass 28, count 0 2006.176.08:04:12.59#ibcon#about to read 4, iclass 28, count 0 2006.176.08:04:12.59#ibcon#read 4, iclass 28, count 0 2006.176.08:04:12.59#ibcon#about to read 5, iclass 28, count 0 2006.176.08:04:12.59#ibcon#read 5, iclass 28, count 0 2006.176.08:04:12.59#ibcon#about to read 6, iclass 28, count 0 2006.176.08:04:12.59#ibcon#read 6, iclass 28, count 0 2006.176.08:04:12.59#ibcon#end of sib2, iclass 28, count 0 2006.176.08:04:12.59#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:04:12.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:04:12.59#ibcon#[27=USB\r\n] 2006.176.08:04:12.59#ibcon#*before write, iclass 28, count 0 2006.176.08:04:12.59#ibcon#enter sib2, iclass 28, count 0 2006.176.08:04:12.59#ibcon#flushed, iclass 28, count 0 2006.176.08:04:12.59#ibcon#about to write, iclass 28, count 0 2006.176.08:04:12.59#ibcon#wrote, iclass 28, count 0 2006.176.08:04:12.59#ibcon#about to read 3, iclass 28, count 0 2006.176.08:04:12.62#ibcon#read 3, iclass 28, count 0 2006.176.08:04:12.62#ibcon#about to read 4, iclass 28, count 0 2006.176.08:04:12.62#ibcon#read 4, iclass 28, count 0 2006.176.08:04:12.62#ibcon#about to read 5, iclass 28, count 0 2006.176.08:04:12.62#ibcon#read 5, iclass 28, count 0 2006.176.08:04:12.62#ibcon#about to read 6, iclass 28, count 0 2006.176.08:04:12.62#ibcon#read 6, iclass 28, count 0 2006.176.08:04:12.62#ibcon#end of sib2, iclass 28, count 0 2006.176.08:04:12.62#ibcon#*after write, iclass 28, count 0 2006.176.08:04:12.62#ibcon#*before return 0, iclass 28, count 0 2006.176.08:04:12.62#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:12.62#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:04:12.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:04:12.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:04:12.62$vc4f8/vabw=wide 2006.176.08:04:12.62#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.08:04:12.62#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.08:04:12.62#ibcon#ireg 8 cls_cnt 0 2006.176.08:04:12.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:12.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:12.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:12.62#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:04:12.62#ibcon#first serial, iclass 30, count 0 2006.176.08:04:12.62#ibcon#enter sib2, iclass 30, count 0 2006.176.08:04:12.62#ibcon#flushed, iclass 30, count 0 2006.176.08:04:12.62#ibcon#about to write, iclass 30, count 0 2006.176.08:04:12.62#ibcon#wrote, iclass 30, count 0 2006.176.08:04:12.62#ibcon#about to read 3, iclass 30, count 0 2006.176.08:04:12.64#ibcon#read 3, iclass 30, count 0 2006.176.08:04:12.64#ibcon#about to read 4, iclass 30, count 0 2006.176.08:04:12.64#ibcon#read 4, iclass 30, count 0 2006.176.08:04:12.64#ibcon#about to read 5, iclass 30, count 0 2006.176.08:04:12.64#ibcon#read 5, iclass 30, count 0 2006.176.08:04:12.64#ibcon#about to read 6, iclass 30, count 0 2006.176.08:04:12.64#ibcon#read 6, iclass 30, count 0 2006.176.08:04:12.64#ibcon#end of sib2, iclass 30, count 0 2006.176.08:04:12.64#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:04:12.64#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:04:12.64#ibcon#[25=BW32\r\n] 2006.176.08:04:12.64#ibcon#*before write, iclass 30, count 0 2006.176.08:04:12.64#ibcon#enter sib2, iclass 30, count 0 2006.176.08:04:12.64#ibcon#flushed, iclass 30, count 0 2006.176.08:04:12.64#ibcon#about to write, iclass 30, count 0 2006.176.08:04:12.64#ibcon#wrote, iclass 30, count 0 2006.176.08:04:12.64#ibcon#about to read 3, iclass 30, count 0 2006.176.08:04:12.67#ibcon#read 3, iclass 30, count 0 2006.176.08:04:12.67#ibcon#about to read 4, iclass 30, count 0 2006.176.08:04:12.67#ibcon#read 4, iclass 30, count 0 2006.176.08:04:12.67#ibcon#about to read 5, iclass 30, count 0 2006.176.08:04:12.67#ibcon#read 5, iclass 30, count 0 2006.176.08:04:12.67#ibcon#about to read 6, iclass 30, count 0 2006.176.08:04:12.67#ibcon#read 6, iclass 30, count 0 2006.176.08:04:12.67#ibcon#end of sib2, iclass 30, count 0 2006.176.08:04:12.67#ibcon#*after write, iclass 30, count 0 2006.176.08:04:12.67#ibcon#*before return 0, iclass 30, count 0 2006.176.08:04:12.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:12.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:04:12.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:04:12.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:04:12.67$vc4f8/vbbw=wide 2006.176.08:04:12.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.08:04:12.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.08:04:12.67#ibcon#ireg 8 cls_cnt 0 2006.176.08:04:12.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:04:12.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:04:12.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:04:12.74#ibcon#enter wrdev, iclass 32, count 0 2006.176.08:04:12.74#ibcon#first serial, iclass 32, count 0 2006.176.08:04:12.74#ibcon#enter sib2, iclass 32, count 0 2006.176.08:04:12.74#ibcon#flushed, iclass 32, count 0 2006.176.08:04:12.74#ibcon#about to write, iclass 32, count 0 2006.176.08:04:12.74#ibcon#wrote, iclass 32, count 0 2006.176.08:04:12.74#ibcon#about to read 3, iclass 32, count 0 2006.176.08:04:12.76#ibcon#read 3, iclass 32, count 0 2006.176.08:04:12.76#ibcon#about to read 4, iclass 32, count 0 2006.176.08:04:12.76#ibcon#read 4, iclass 32, count 0 2006.176.08:04:12.76#ibcon#about to read 5, iclass 32, count 0 2006.176.08:04:12.76#ibcon#read 5, iclass 32, count 0 2006.176.08:04:12.76#ibcon#about to read 6, iclass 32, count 0 2006.176.08:04:12.76#ibcon#read 6, iclass 32, count 0 2006.176.08:04:12.76#ibcon#end of sib2, iclass 32, count 0 2006.176.08:04:12.76#ibcon#*mode == 0, iclass 32, count 0 2006.176.08:04:12.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.08:04:12.76#ibcon#[27=BW32\r\n] 2006.176.08:04:12.76#ibcon#*before write, iclass 32, count 0 2006.176.08:04:12.76#ibcon#enter sib2, iclass 32, count 0 2006.176.08:04:12.76#ibcon#flushed, iclass 32, count 0 2006.176.08:04:12.76#ibcon#about to write, iclass 32, count 0 2006.176.08:04:12.76#ibcon#wrote, iclass 32, count 0 2006.176.08:04:12.76#ibcon#about to read 3, iclass 32, count 0 2006.176.08:04:12.79#ibcon#read 3, iclass 32, count 0 2006.176.08:04:12.79#ibcon#about to read 4, iclass 32, count 0 2006.176.08:04:12.79#ibcon#read 4, iclass 32, count 0 2006.176.08:04:12.79#ibcon#about to read 5, iclass 32, count 0 2006.176.08:04:12.79#ibcon#read 5, iclass 32, count 0 2006.176.08:04:12.79#ibcon#about to read 6, iclass 32, count 0 2006.176.08:04:12.79#ibcon#read 6, iclass 32, count 0 2006.176.08:04:12.79#ibcon#end of sib2, iclass 32, count 0 2006.176.08:04:12.79#ibcon#*after write, iclass 32, count 0 2006.176.08:04:12.79#ibcon#*before return 0, iclass 32, count 0 2006.176.08:04:12.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:04:12.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:04:12.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.08:04:12.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.08:04:12.79$4f8m12a/ifd4f 2006.176.08:04:12.79$ifd4f/lo= 2006.176.08:04:12.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:04:12.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:04:12.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:04:12.79$ifd4f/patch= 2006.176.08:04:12.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:04:12.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:04:12.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:04:12.79$4f8m12a/"form=m,16.000,1:2 2006.176.08:04:12.79$4f8m12a/"tpicd 2006.176.08:04:12.79$4f8m12a/echo=off 2006.176.08:04:12.79$4f8m12a/xlog=off 2006.176.08:04:12.79:!2006.176.08:04:50 2006.176.08:04:31.14#trakl#Source acquired 2006.176.08:04:33.14#flagr#flagr/antenna,acquired 2006.176.08:04:50.00:preob 2006.176.08:04:50.14/onsource/TRACKING 2006.176.08:04:50.14:!2006.176.08:05:00 2006.176.08:05:00.00:data_valid=on 2006.176.08:05:00.00:midob 2006.176.08:05:00.14/onsource/TRACKING 2006.176.08:05:00.14/wx/23.85,1008.6,92 2006.176.08:05:00.29/cable/+6.4938E-03 2006.176.08:05:01.38/va/01,08,usb,yes,28,30 2006.176.08:05:01.38/va/02,07,usb,yes,28,30 2006.176.08:05:01.38/va/03,06,usb,yes,30,30 2006.176.08:05:01.38/va/04,07,usb,yes,29,31 2006.176.08:05:01.38/va/05,07,usb,yes,31,32 2006.176.08:05:01.38/va/06,06,usb,yes,30,30 2006.176.08:05:01.38/va/07,06,usb,yes,30,30 2006.176.08:05:01.38/va/08,06,usb,yes,32,32 2006.176.08:05:01.61/valo/01,532.99,yes,locked 2006.176.08:05:01.61/valo/02,572.99,yes,locked 2006.176.08:05:01.61/valo/03,672.99,yes,locked 2006.176.08:05:01.61/valo/04,832.99,yes,locked 2006.176.08:05:01.61/valo/05,652.99,yes,locked 2006.176.08:05:01.61/valo/06,772.99,yes,locked 2006.176.08:05:01.61/valo/07,832.99,yes,locked 2006.176.08:05:01.61/valo/08,852.99,yes,locked 2006.176.08:05:02.70/vb/01,04,usb,yes,29,27 2006.176.08:05:02.70/vb/02,04,usb,yes,30,32 2006.176.08:05:02.70/vb/03,04,usb,yes,27,30 2006.176.08:05:02.70/vb/04,04,usb,yes,28,28 2006.176.08:05:02.70/vb/05,04,usb,yes,26,30 2006.176.08:05:02.70/vb/06,04,usb,yes,27,30 2006.176.08:05:02.70/vb/07,04,usb,yes,29,29 2006.176.08:05:02.70/vb/08,04,usb,yes,27,30 2006.176.08:05:02.94/vblo/01,632.99,yes,locked 2006.176.08:05:02.94/vblo/02,640.99,yes,locked 2006.176.08:05:02.94/vblo/03,656.99,yes,locked 2006.176.08:05:02.94/vblo/04,712.99,yes,locked 2006.176.08:05:02.94/vblo/05,744.99,yes,locked 2006.176.08:05:02.94/vblo/06,752.99,yes,locked 2006.176.08:05:02.94/vblo/07,734.99,yes,locked 2006.176.08:05:02.94/vblo/08,744.99,yes,locked 2006.176.08:05:03.09/vabw/8 2006.176.08:05:03.24/vbbw/8 2006.176.08:05:03.33/xfe/off,on,15.2 2006.176.08:05:03.71/ifatt/23,28,28,28 2006.176.08:05:04.07/fmout-gps/S +3.71E-07 2006.176.08:05:04.15:!2006.176.08:06:00 2006.176.08:06:00.00:data_valid=off 2006.176.08:06:00.01:postob 2006.176.08:06:00.08/cable/+6.4930E-03 2006.176.08:06:00.09/wx/23.86,1008.6,92 2006.176.08:06:01.07/fmout-gps/S +3.71E-07 2006.176.08:06:01.08:scan_name=176-0806,k06176,60 2006.176.08:06:01.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.176.08:06:01.13#flagr#flagr/antenna,new-source 2006.176.08:06:02.13:checkk5 2006.176.08:06:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:06:02.93/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:06:03.31/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:06:03.82/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:06:04.20/chk_obsdata//k5ts1/T1760805??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:06:04.57/chk_obsdata//k5ts2/T1760805??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:06:04.94/chk_obsdata//k5ts3/T1760805??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:06:05.32/chk_obsdata//k5ts4/T1760805??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:06:06.00/k5log//k5ts1_log_newline 2006.176.08:06:06.69/k5log//k5ts2_log_newline 2006.176.08:06:07.38/k5log//k5ts3_log_newline 2006.176.08:06:08.07/k5log//k5ts4_log_newline 2006.176.08:06:08.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:06:08.10:4f8m12a=2 2006.176.08:06:08.10$4f8m12a/echo=on 2006.176.08:06:08.10$4f8m12a/pcalon 2006.176.08:06:08.10$pcalon/"no phase cal control is implemented here 2006.176.08:06:08.10$4f8m12a/"tpicd=stop 2006.176.08:06:08.10$4f8m12a/vc4f8 2006.176.08:06:08.10$vc4f8/valo=1,532.99 2006.176.08:06:08.10#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.08:06:08.10#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.08:06:08.10#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:08.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:08.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:08.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:08.10#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:06:08.10#ibcon#first serial, iclass 5, count 0 2006.176.08:06:08.10#ibcon#enter sib2, iclass 5, count 0 2006.176.08:06:08.10#ibcon#flushed, iclass 5, count 0 2006.176.08:06:08.10#ibcon#about to write, iclass 5, count 0 2006.176.08:06:08.10#ibcon#wrote, iclass 5, count 0 2006.176.08:06:08.10#ibcon#about to read 3, iclass 5, count 0 2006.176.08:06:08.14#ibcon#read 3, iclass 5, count 0 2006.176.08:06:08.14#ibcon#about to read 4, iclass 5, count 0 2006.176.08:06:08.14#ibcon#read 4, iclass 5, count 0 2006.176.08:06:08.14#ibcon#about to read 5, iclass 5, count 0 2006.176.08:06:08.14#ibcon#read 5, iclass 5, count 0 2006.176.08:06:08.14#ibcon#about to read 6, iclass 5, count 0 2006.176.08:06:08.14#ibcon#read 6, iclass 5, count 0 2006.176.08:06:08.14#ibcon#end of sib2, iclass 5, count 0 2006.176.08:06:08.14#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:06:08.14#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:06:08.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:06:08.14#ibcon#*before write, iclass 5, count 0 2006.176.08:06:08.14#ibcon#enter sib2, iclass 5, count 0 2006.176.08:06:08.14#ibcon#flushed, iclass 5, count 0 2006.176.08:06:08.14#ibcon#about to write, iclass 5, count 0 2006.176.08:06:08.14#ibcon#wrote, iclass 5, count 0 2006.176.08:06:08.14#ibcon#about to read 3, iclass 5, count 0 2006.176.08:06:08.19#ibcon#read 3, iclass 5, count 0 2006.176.08:06:08.19#ibcon#about to read 4, iclass 5, count 0 2006.176.08:06:08.19#ibcon#read 4, iclass 5, count 0 2006.176.08:06:08.19#ibcon#about to read 5, iclass 5, count 0 2006.176.08:06:08.19#ibcon#read 5, iclass 5, count 0 2006.176.08:06:08.19#ibcon#about to read 6, iclass 5, count 0 2006.176.08:06:08.19#ibcon#read 6, iclass 5, count 0 2006.176.08:06:08.19#ibcon#end of sib2, iclass 5, count 0 2006.176.08:06:08.19#ibcon#*after write, iclass 5, count 0 2006.176.08:06:08.19#ibcon#*before return 0, iclass 5, count 0 2006.176.08:06:08.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:08.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:08.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:06:08.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:06:08.19$vc4f8/va=1,8 2006.176.08:06:08.19#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.08:06:08.19#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.08:06:08.19#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:08.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:08.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:08.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:08.19#ibcon#enter wrdev, iclass 7, count 2 2006.176.08:06:08.19#ibcon#first serial, iclass 7, count 2 2006.176.08:06:08.19#ibcon#enter sib2, iclass 7, count 2 2006.176.08:06:08.19#ibcon#flushed, iclass 7, count 2 2006.176.08:06:08.19#ibcon#about to write, iclass 7, count 2 2006.176.08:06:08.19#ibcon#wrote, iclass 7, count 2 2006.176.08:06:08.19#ibcon#about to read 3, iclass 7, count 2 2006.176.08:06:08.21#ibcon#read 3, iclass 7, count 2 2006.176.08:06:08.21#ibcon#about to read 4, iclass 7, count 2 2006.176.08:06:08.21#ibcon#read 4, iclass 7, count 2 2006.176.08:06:08.21#ibcon#about to read 5, iclass 7, count 2 2006.176.08:06:08.21#ibcon#read 5, iclass 7, count 2 2006.176.08:06:08.21#ibcon#about to read 6, iclass 7, count 2 2006.176.08:06:08.21#ibcon#read 6, iclass 7, count 2 2006.176.08:06:08.21#ibcon#end of sib2, iclass 7, count 2 2006.176.08:06:08.21#ibcon#*mode == 0, iclass 7, count 2 2006.176.08:06:08.21#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.08:06:08.21#ibcon#[25=AT01-08\r\n] 2006.176.08:06:08.21#ibcon#*before write, iclass 7, count 2 2006.176.08:06:08.21#ibcon#enter sib2, iclass 7, count 2 2006.176.08:06:08.21#ibcon#flushed, iclass 7, count 2 2006.176.08:06:08.21#ibcon#about to write, iclass 7, count 2 2006.176.08:06:08.21#ibcon#wrote, iclass 7, count 2 2006.176.08:06:08.21#ibcon#about to read 3, iclass 7, count 2 2006.176.08:06:08.24#ibcon#read 3, iclass 7, count 2 2006.176.08:06:08.24#ibcon#about to read 4, iclass 7, count 2 2006.176.08:06:08.24#ibcon#read 4, iclass 7, count 2 2006.176.08:06:08.24#ibcon#about to read 5, iclass 7, count 2 2006.176.08:06:08.24#ibcon#read 5, iclass 7, count 2 2006.176.08:06:08.24#ibcon#about to read 6, iclass 7, count 2 2006.176.08:06:08.24#ibcon#read 6, iclass 7, count 2 2006.176.08:06:08.24#ibcon#end of sib2, iclass 7, count 2 2006.176.08:06:08.24#ibcon#*after write, iclass 7, count 2 2006.176.08:06:08.24#ibcon#*before return 0, iclass 7, count 2 2006.176.08:06:08.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:08.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:08.24#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.08:06:08.24#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:08.24#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:08.36#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:08.36#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:08.36#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:06:08.36#ibcon#first serial, iclass 7, count 0 2006.176.08:06:08.36#ibcon#enter sib2, iclass 7, count 0 2006.176.08:06:08.36#ibcon#flushed, iclass 7, count 0 2006.176.08:06:08.36#ibcon#about to write, iclass 7, count 0 2006.176.08:06:08.36#ibcon#wrote, iclass 7, count 0 2006.176.08:06:08.36#ibcon#about to read 3, iclass 7, count 0 2006.176.08:06:08.38#ibcon#read 3, iclass 7, count 0 2006.176.08:06:08.38#ibcon#about to read 4, iclass 7, count 0 2006.176.08:06:08.38#ibcon#read 4, iclass 7, count 0 2006.176.08:06:08.38#ibcon#about to read 5, iclass 7, count 0 2006.176.08:06:08.38#ibcon#read 5, iclass 7, count 0 2006.176.08:06:08.38#ibcon#about to read 6, iclass 7, count 0 2006.176.08:06:08.38#ibcon#read 6, iclass 7, count 0 2006.176.08:06:08.38#ibcon#end of sib2, iclass 7, count 0 2006.176.08:06:08.38#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:06:08.38#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:06:08.38#ibcon#[25=USB\r\n] 2006.176.08:06:08.38#ibcon#*before write, iclass 7, count 0 2006.176.08:06:08.38#ibcon#enter sib2, iclass 7, count 0 2006.176.08:06:08.38#ibcon#flushed, iclass 7, count 0 2006.176.08:06:08.38#ibcon#about to write, iclass 7, count 0 2006.176.08:06:08.38#ibcon#wrote, iclass 7, count 0 2006.176.08:06:08.38#ibcon#about to read 3, iclass 7, count 0 2006.176.08:06:08.42#ibcon#read 3, iclass 7, count 0 2006.176.08:06:08.42#ibcon#about to read 4, iclass 7, count 0 2006.176.08:06:08.42#ibcon#read 4, iclass 7, count 0 2006.176.08:06:08.42#ibcon#about to read 5, iclass 7, count 0 2006.176.08:06:08.42#ibcon#read 5, iclass 7, count 0 2006.176.08:06:08.42#ibcon#about to read 6, iclass 7, count 0 2006.176.08:06:08.42#ibcon#read 6, iclass 7, count 0 2006.176.08:06:08.42#ibcon#end of sib2, iclass 7, count 0 2006.176.08:06:08.42#ibcon#*after write, iclass 7, count 0 2006.176.08:06:08.42#ibcon#*before return 0, iclass 7, count 0 2006.176.08:06:08.42#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:08.42#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:08.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:06:08.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:06:08.42$vc4f8/valo=2,572.99 2006.176.08:06:08.42#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.08:06:08.42#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.08:06:08.42#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:08.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:08.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:08.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:08.42#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:06:08.42#ibcon#first serial, iclass 11, count 0 2006.176.08:06:08.42#ibcon#enter sib2, iclass 11, count 0 2006.176.08:06:08.42#ibcon#flushed, iclass 11, count 0 2006.176.08:06:08.42#ibcon#about to write, iclass 11, count 0 2006.176.08:06:08.42#ibcon#wrote, iclass 11, count 0 2006.176.08:06:08.42#ibcon#about to read 3, iclass 11, count 0 2006.176.08:06:08.43#ibcon#read 3, iclass 11, count 0 2006.176.08:06:08.43#ibcon#about to read 4, iclass 11, count 0 2006.176.08:06:08.43#ibcon#read 4, iclass 11, count 0 2006.176.08:06:08.43#ibcon#about to read 5, iclass 11, count 0 2006.176.08:06:08.43#ibcon#read 5, iclass 11, count 0 2006.176.08:06:08.43#ibcon#about to read 6, iclass 11, count 0 2006.176.08:06:08.43#ibcon#read 6, iclass 11, count 0 2006.176.08:06:08.43#ibcon#end of sib2, iclass 11, count 0 2006.176.08:06:08.43#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:06:08.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:06:08.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:06:08.43#ibcon#*before write, iclass 11, count 0 2006.176.08:06:08.43#ibcon#enter sib2, iclass 11, count 0 2006.176.08:06:08.43#ibcon#flushed, iclass 11, count 0 2006.176.08:06:08.43#ibcon#about to write, iclass 11, count 0 2006.176.08:06:08.43#ibcon#wrote, iclass 11, count 0 2006.176.08:06:08.43#ibcon#about to read 3, iclass 11, count 0 2006.176.08:06:08.47#ibcon#read 3, iclass 11, count 0 2006.176.08:06:08.47#ibcon#about to read 4, iclass 11, count 0 2006.176.08:06:08.47#ibcon#read 4, iclass 11, count 0 2006.176.08:06:08.47#ibcon#about to read 5, iclass 11, count 0 2006.176.08:06:08.47#ibcon#read 5, iclass 11, count 0 2006.176.08:06:08.47#ibcon#about to read 6, iclass 11, count 0 2006.176.08:06:08.47#ibcon#read 6, iclass 11, count 0 2006.176.08:06:08.47#ibcon#end of sib2, iclass 11, count 0 2006.176.08:06:08.47#ibcon#*after write, iclass 11, count 0 2006.176.08:06:08.47#ibcon#*before return 0, iclass 11, count 0 2006.176.08:06:08.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:08.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:08.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:06:08.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:06:08.47$vc4f8/va=2,7 2006.176.08:06:08.47#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.08:06:08.47#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.08:06:08.47#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:08.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:08.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:08.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:08.54#ibcon#enter wrdev, iclass 13, count 2 2006.176.08:06:08.54#ibcon#first serial, iclass 13, count 2 2006.176.08:06:08.54#ibcon#enter sib2, iclass 13, count 2 2006.176.08:06:08.54#ibcon#flushed, iclass 13, count 2 2006.176.08:06:08.54#ibcon#about to write, iclass 13, count 2 2006.176.08:06:08.54#ibcon#wrote, iclass 13, count 2 2006.176.08:06:08.54#ibcon#about to read 3, iclass 13, count 2 2006.176.08:06:08.56#ibcon#read 3, iclass 13, count 2 2006.176.08:06:08.56#ibcon#about to read 4, iclass 13, count 2 2006.176.08:06:08.56#ibcon#read 4, iclass 13, count 2 2006.176.08:06:08.56#ibcon#about to read 5, iclass 13, count 2 2006.176.08:06:08.56#ibcon#read 5, iclass 13, count 2 2006.176.08:06:08.56#ibcon#about to read 6, iclass 13, count 2 2006.176.08:06:08.56#ibcon#read 6, iclass 13, count 2 2006.176.08:06:08.56#ibcon#end of sib2, iclass 13, count 2 2006.176.08:06:08.56#ibcon#*mode == 0, iclass 13, count 2 2006.176.08:06:08.56#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.08:06:08.56#ibcon#[25=AT02-07\r\n] 2006.176.08:06:08.56#ibcon#*before write, iclass 13, count 2 2006.176.08:06:08.56#ibcon#enter sib2, iclass 13, count 2 2006.176.08:06:08.56#ibcon#flushed, iclass 13, count 2 2006.176.08:06:08.56#ibcon#about to write, iclass 13, count 2 2006.176.08:06:08.56#ibcon#wrote, iclass 13, count 2 2006.176.08:06:08.56#ibcon#about to read 3, iclass 13, count 2 2006.176.08:06:08.59#ibcon#read 3, iclass 13, count 2 2006.176.08:06:08.59#ibcon#about to read 4, iclass 13, count 2 2006.176.08:06:08.59#ibcon#read 4, iclass 13, count 2 2006.176.08:06:08.59#ibcon#about to read 5, iclass 13, count 2 2006.176.08:06:08.59#ibcon#read 5, iclass 13, count 2 2006.176.08:06:08.59#ibcon#about to read 6, iclass 13, count 2 2006.176.08:06:08.59#ibcon#read 6, iclass 13, count 2 2006.176.08:06:08.59#ibcon#end of sib2, iclass 13, count 2 2006.176.08:06:08.59#ibcon#*after write, iclass 13, count 2 2006.176.08:06:08.59#ibcon#*before return 0, iclass 13, count 2 2006.176.08:06:08.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:08.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:08.59#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.08:06:08.59#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:08.59#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:08.71#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:08.71#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:08.71#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:06:08.71#ibcon#first serial, iclass 13, count 0 2006.176.08:06:08.71#ibcon#enter sib2, iclass 13, count 0 2006.176.08:06:08.71#ibcon#flushed, iclass 13, count 0 2006.176.08:06:08.71#ibcon#about to write, iclass 13, count 0 2006.176.08:06:08.71#ibcon#wrote, iclass 13, count 0 2006.176.08:06:08.71#ibcon#about to read 3, iclass 13, count 0 2006.176.08:06:08.74#ibcon#read 3, iclass 13, count 0 2006.176.08:06:08.74#ibcon#about to read 4, iclass 13, count 0 2006.176.08:06:08.74#ibcon#read 4, iclass 13, count 0 2006.176.08:06:08.74#ibcon#about to read 5, iclass 13, count 0 2006.176.08:06:08.74#ibcon#read 5, iclass 13, count 0 2006.176.08:06:08.74#ibcon#about to read 6, iclass 13, count 0 2006.176.08:06:08.74#ibcon#read 6, iclass 13, count 0 2006.176.08:06:08.74#ibcon#end of sib2, iclass 13, count 0 2006.176.08:06:08.74#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:06:08.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:06:08.74#ibcon#[25=USB\r\n] 2006.176.08:06:08.74#ibcon#*before write, iclass 13, count 0 2006.176.08:06:08.74#ibcon#enter sib2, iclass 13, count 0 2006.176.08:06:08.74#ibcon#flushed, iclass 13, count 0 2006.176.08:06:08.74#ibcon#about to write, iclass 13, count 0 2006.176.08:06:08.74#ibcon#wrote, iclass 13, count 0 2006.176.08:06:08.74#ibcon#about to read 3, iclass 13, count 0 2006.176.08:06:08.76#ibcon#read 3, iclass 13, count 0 2006.176.08:06:08.76#ibcon#about to read 4, iclass 13, count 0 2006.176.08:06:08.76#ibcon#read 4, iclass 13, count 0 2006.176.08:06:08.76#ibcon#about to read 5, iclass 13, count 0 2006.176.08:06:08.76#ibcon#read 5, iclass 13, count 0 2006.176.08:06:08.76#ibcon#about to read 6, iclass 13, count 0 2006.176.08:06:08.76#ibcon#read 6, iclass 13, count 0 2006.176.08:06:08.76#ibcon#end of sib2, iclass 13, count 0 2006.176.08:06:08.76#ibcon#*after write, iclass 13, count 0 2006.176.08:06:08.76#ibcon#*before return 0, iclass 13, count 0 2006.176.08:06:08.76#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:08.76#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:08.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:06:08.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:06:08.76$vc4f8/valo=3,672.99 2006.176.08:06:08.76#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.08:06:08.76#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.08:06:08.76#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:08.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:06:08.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:06:08.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:06:08.76#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:06:08.76#ibcon#first serial, iclass 16, count 0 2006.176.08:06:08.76#ibcon#enter sib2, iclass 16, count 0 2006.176.08:06:08.76#ibcon#flushed, iclass 16, count 0 2006.176.08:06:08.76#ibcon#about to write, iclass 16, count 0 2006.176.08:06:08.76#ibcon#wrote, iclass 16, count 0 2006.176.08:06:08.76#ibcon#about to read 3, iclass 16, count 0 2006.176.08:06:08.79#ibcon#read 3, iclass 16, count 0 2006.176.08:06:08.79#ibcon#about to read 4, iclass 16, count 0 2006.176.08:06:08.79#ibcon#read 4, iclass 16, count 0 2006.176.08:06:08.79#ibcon#about to read 5, iclass 16, count 0 2006.176.08:06:08.79#ibcon#read 5, iclass 16, count 0 2006.176.08:06:08.79#ibcon#about to read 6, iclass 16, count 0 2006.176.08:06:08.79#ibcon#read 6, iclass 16, count 0 2006.176.08:06:08.79#ibcon#end of sib2, iclass 16, count 0 2006.176.08:06:08.79#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:06:08.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:06:08.79#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:06:08.79#ibcon#*before write, iclass 16, count 0 2006.176.08:06:08.79#ibcon#enter sib2, iclass 16, count 0 2006.176.08:06:08.79#ibcon#flushed, iclass 16, count 0 2006.176.08:06:08.79#ibcon#about to write, iclass 16, count 0 2006.176.08:06:08.79#ibcon#wrote, iclass 16, count 0 2006.176.08:06:08.79#ibcon#about to read 3, iclass 16, count 0 2006.176.08:06:08.79#abcon#<5=/05 2.9 4.5 23.86 921008.6\r\n> 2006.176.08:06:08.81#abcon#{5=INTERFACE CLEAR} 2006.176.08:06:08.83#ibcon#read 3, iclass 16, count 0 2006.176.08:06:08.83#ibcon#about to read 4, iclass 16, count 0 2006.176.08:06:08.83#ibcon#read 4, iclass 16, count 0 2006.176.08:06:08.83#ibcon#about to read 5, iclass 16, count 0 2006.176.08:06:08.83#ibcon#read 5, iclass 16, count 0 2006.176.08:06:08.83#ibcon#about to read 6, iclass 16, count 0 2006.176.08:06:08.83#ibcon#read 6, iclass 16, count 0 2006.176.08:06:08.83#ibcon#end of sib2, iclass 16, count 0 2006.176.08:06:08.83#ibcon#*after write, iclass 16, count 0 2006.176.08:06:08.83#ibcon#*before return 0, iclass 16, count 0 2006.176.08:06:08.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:06:08.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:06:08.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:06:08.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:06:08.83$vc4f8/va=3,6 2006.176.08:06:08.83#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.08:06:08.83#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.08:06:08.83#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:08.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:06:08.87#abcon#[5=S1D000X0/0*\r\n] 2006.176.08:06:08.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:06:08.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:06:08.88#ibcon#enter wrdev, iclass 20, count 2 2006.176.08:06:08.88#ibcon#first serial, iclass 20, count 2 2006.176.08:06:08.88#ibcon#enter sib2, iclass 20, count 2 2006.176.08:06:08.88#ibcon#flushed, iclass 20, count 2 2006.176.08:06:08.88#ibcon#about to write, iclass 20, count 2 2006.176.08:06:08.88#ibcon#wrote, iclass 20, count 2 2006.176.08:06:08.88#ibcon#about to read 3, iclass 20, count 2 2006.176.08:06:08.90#ibcon#read 3, iclass 20, count 2 2006.176.08:06:08.90#ibcon#about to read 4, iclass 20, count 2 2006.176.08:06:08.90#ibcon#read 4, iclass 20, count 2 2006.176.08:06:08.90#ibcon#about to read 5, iclass 20, count 2 2006.176.08:06:08.90#ibcon#read 5, iclass 20, count 2 2006.176.08:06:08.90#ibcon#about to read 6, iclass 20, count 2 2006.176.08:06:08.90#ibcon#read 6, iclass 20, count 2 2006.176.08:06:08.90#ibcon#end of sib2, iclass 20, count 2 2006.176.08:06:08.90#ibcon#*mode == 0, iclass 20, count 2 2006.176.08:06:08.90#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.08:06:08.90#ibcon#[25=AT03-06\r\n] 2006.176.08:06:08.90#ibcon#*before write, iclass 20, count 2 2006.176.08:06:08.90#ibcon#enter sib2, iclass 20, count 2 2006.176.08:06:08.90#ibcon#flushed, iclass 20, count 2 2006.176.08:06:08.90#ibcon#about to write, iclass 20, count 2 2006.176.08:06:08.90#ibcon#wrote, iclass 20, count 2 2006.176.08:06:08.90#ibcon#about to read 3, iclass 20, count 2 2006.176.08:06:08.93#ibcon#read 3, iclass 20, count 2 2006.176.08:06:08.93#ibcon#about to read 4, iclass 20, count 2 2006.176.08:06:08.93#ibcon#read 4, iclass 20, count 2 2006.176.08:06:08.93#ibcon#about to read 5, iclass 20, count 2 2006.176.08:06:08.93#ibcon#read 5, iclass 20, count 2 2006.176.08:06:08.93#ibcon#about to read 6, iclass 20, count 2 2006.176.08:06:08.93#ibcon#read 6, iclass 20, count 2 2006.176.08:06:08.93#ibcon#end of sib2, iclass 20, count 2 2006.176.08:06:08.93#ibcon#*after write, iclass 20, count 2 2006.176.08:06:08.93#ibcon#*before return 0, iclass 20, count 2 2006.176.08:06:08.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:06:08.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:06:08.93#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.08:06:08.93#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:08.93#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:06:09.05#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:06:09.05#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:06:09.05#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:06:09.05#ibcon#first serial, iclass 20, count 0 2006.176.08:06:09.05#ibcon#enter sib2, iclass 20, count 0 2006.176.08:06:09.05#ibcon#flushed, iclass 20, count 0 2006.176.08:06:09.05#ibcon#about to write, iclass 20, count 0 2006.176.08:06:09.05#ibcon#wrote, iclass 20, count 0 2006.176.08:06:09.05#ibcon#about to read 3, iclass 20, count 0 2006.176.08:06:09.07#ibcon#read 3, iclass 20, count 0 2006.176.08:06:09.07#ibcon#about to read 4, iclass 20, count 0 2006.176.08:06:09.07#ibcon#read 4, iclass 20, count 0 2006.176.08:06:09.07#ibcon#about to read 5, iclass 20, count 0 2006.176.08:06:09.07#ibcon#read 5, iclass 20, count 0 2006.176.08:06:09.07#ibcon#about to read 6, iclass 20, count 0 2006.176.08:06:09.07#ibcon#read 6, iclass 20, count 0 2006.176.08:06:09.07#ibcon#end of sib2, iclass 20, count 0 2006.176.08:06:09.07#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:06:09.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:06:09.07#ibcon#[25=USB\r\n] 2006.176.08:06:09.07#ibcon#*before write, iclass 20, count 0 2006.176.08:06:09.07#ibcon#enter sib2, iclass 20, count 0 2006.176.08:06:09.07#ibcon#flushed, iclass 20, count 0 2006.176.08:06:09.07#ibcon#about to write, iclass 20, count 0 2006.176.08:06:09.07#ibcon#wrote, iclass 20, count 0 2006.176.08:06:09.07#ibcon#about to read 3, iclass 20, count 0 2006.176.08:06:09.10#ibcon#read 3, iclass 20, count 0 2006.176.08:06:09.10#ibcon#about to read 4, iclass 20, count 0 2006.176.08:06:09.10#ibcon#read 4, iclass 20, count 0 2006.176.08:06:09.10#ibcon#about to read 5, iclass 20, count 0 2006.176.08:06:09.10#ibcon#read 5, iclass 20, count 0 2006.176.08:06:09.10#ibcon#about to read 6, iclass 20, count 0 2006.176.08:06:09.10#ibcon#read 6, iclass 20, count 0 2006.176.08:06:09.10#ibcon#end of sib2, iclass 20, count 0 2006.176.08:06:09.10#ibcon#*after write, iclass 20, count 0 2006.176.08:06:09.10#ibcon#*before return 0, iclass 20, count 0 2006.176.08:06:09.10#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:06:09.10#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:06:09.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:06:09.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:06:09.10$vc4f8/valo=4,832.99 2006.176.08:06:09.10#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.08:06:09.10#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.08:06:09.10#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:09.10#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:09.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:09.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:09.10#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:06:09.10#ibcon#first serial, iclass 23, count 0 2006.176.08:06:09.10#ibcon#enter sib2, iclass 23, count 0 2006.176.08:06:09.10#ibcon#flushed, iclass 23, count 0 2006.176.08:06:09.10#ibcon#about to write, iclass 23, count 0 2006.176.08:06:09.10#ibcon#wrote, iclass 23, count 0 2006.176.08:06:09.10#ibcon#about to read 3, iclass 23, count 0 2006.176.08:06:09.12#ibcon#read 3, iclass 23, count 0 2006.176.08:06:09.12#ibcon#about to read 4, iclass 23, count 0 2006.176.08:06:09.12#ibcon#read 4, iclass 23, count 0 2006.176.08:06:09.12#ibcon#about to read 5, iclass 23, count 0 2006.176.08:06:09.12#ibcon#read 5, iclass 23, count 0 2006.176.08:06:09.12#ibcon#about to read 6, iclass 23, count 0 2006.176.08:06:09.12#ibcon#read 6, iclass 23, count 0 2006.176.08:06:09.12#ibcon#end of sib2, iclass 23, count 0 2006.176.08:06:09.12#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:06:09.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:06:09.12#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:06:09.12#ibcon#*before write, iclass 23, count 0 2006.176.08:06:09.12#ibcon#enter sib2, iclass 23, count 0 2006.176.08:06:09.12#ibcon#flushed, iclass 23, count 0 2006.176.08:06:09.12#ibcon#about to write, iclass 23, count 0 2006.176.08:06:09.12#ibcon#wrote, iclass 23, count 0 2006.176.08:06:09.12#ibcon#about to read 3, iclass 23, count 0 2006.176.08:06:09.16#ibcon#read 3, iclass 23, count 0 2006.176.08:06:09.16#ibcon#about to read 4, iclass 23, count 0 2006.176.08:06:09.16#ibcon#read 4, iclass 23, count 0 2006.176.08:06:09.16#ibcon#about to read 5, iclass 23, count 0 2006.176.08:06:09.16#ibcon#read 5, iclass 23, count 0 2006.176.08:06:09.16#ibcon#about to read 6, iclass 23, count 0 2006.176.08:06:09.16#ibcon#read 6, iclass 23, count 0 2006.176.08:06:09.16#ibcon#end of sib2, iclass 23, count 0 2006.176.08:06:09.16#ibcon#*after write, iclass 23, count 0 2006.176.08:06:09.16#ibcon#*before return 0, iclass 23, count 0 2006.176.08:06:09.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:09.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:09.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:06:09.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:06:09.16$vc4f8/va=4,7 2006.176.08:06:09.16#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.176.08:06:09.16#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.176.08:06:09.16#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:09.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:09.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:09.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:09.22#ibcon#enter wrdev, iclass 25, count 2 2006.176.08:06:09.22#ibcon#first serial, iclass 25, count 2 2006.176.08:06:09.22#ibcon#enter sib2, iclass 25, count 2 2006.176.08:06:09.22#ibcon#flushed, iclass 25, count 2 2006.176.08:06:09.22#ibcon#about to write, iclass 25, count 2 2006.176.08:06:09.22#ibcon#wrote, iclass 25, count 2 2006.176.08:06:09.22#ibcon#about to read 3, iclass 25, count 2 2006.176.08:06:09.24#ibcon#read 3, iclass 25, count 2 2006.176.08:06:09.24#ibcon#about to read 4, iclass 25, count 2 2006.176.08:06:09.24#ibcon#read 4, iclass 25, count 2 2006.176.08:06:09.24#ibcon#about to read 5, iclass 25, count 2 2006.176.08:06:09.24#ibcon#read 5, iclass 25, count 2 2006.176.08:06:09.24#ibcon#about to read 6, iclass 25, count 2 2006.176.08:06:09.24#ibcon#read 6, iclass 25, count 2 2006.176.08:06:09.24#ibcon#end of sib2, iclass 25, count 2 2006.176.08:06:09.24#ibcon#*mode == 0, iclass 25, count 2 2006.176.08:06:09.24#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.176.08:06:09.24#ibcon#[25=AT04-07\r\n] 2006.176.08:06:09.24#ibcon#*before write, iclass 25, count 2 2006.176.08:06:09.24#ibcon#enter sib2, iclass 25, count 2 2006.176.08:06:09.24#ibcon#flushed, iclass 25, count 2 2006.176.08:06:09.24#ibcon#about to write, iclass 25, count 2 2006.176.08:06:09.24#ibcon#wrote, iclass 25, count 2 2006.176.08:06:09.24#ibcon#about to read 3, iclass 25, count 2 2006.176.08:06:09.27#ibcon#read 3, iclass 25, count 2 2006.176.08:06:09.27#ibcon#about to read 4, iclass 25, count 2 2006.176.08:06:09.27#ibcon#read 4, iclass 25, count 2 2006.176.08:06:09.27#ibcon#about to read 5, iclass 25, count 2 2006.176.08:06:09.27#ibcon#read 5, iclass 25, count 2 2006.176.08:06:09.27#ibcon#about to read 6, iclass 25, count 2 2006.176.08:06:09.27#ibcon#read 6, iclass 25, count 2 2006.176.08:06:09.27#ibcon#end of sib2, iclass 25, count 2 2006.176.08:06:09.27#ibcon#*after write, iclass 25, count 2 2006.176.08:06:09.27#ibcon#*before return 0, iclass 25, count 2 2006.176.08:06:09.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:09.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:09.27#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.176.08:06:09.27#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:09.27#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:09.39#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:09.39#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:09.39#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:06:09.39#ibcon#first serial, iclass 25, count 0 2006.176.08:06:09.39#ibcon#enter sib2, iclass 25, count 0 2006.176.08:06:09.39#ibcon#flushed, iclass 25, count 0 2006.176.08:06:09.39#ibcon#about to write, iclass 25, count 0 2006.176.08:06:09.39#ibcon#wrote, iclass 25, count 0 2006.176.08:06:09.39#ibcon#about to read 3, iclass 25, count 0 2006.176.08:06:09.41#ibcon#read 3, iclass 25, count 0 2006.176.08:06:09.41#ibcon#about to read 4, iclass 25, count 0 2006.176.08:06:09.41#ibcon#read 4, iclass 25, count 0 2006.176.08:06:09.41#ibcon#about to read 5, iclass 25, count 0 2006.176.08:06:09.41#ibcon#read 5, iclass 25, count 0 2006.176.08:06:09.41#ibcon#about to read 6, iclass 25, count 0 2006.176.08:06:09.41#ibcon#read 6, iclass 25, count 0 2006.176.08:06:09.41#ibcon#end of sib2, iclass 25, count 0 2006.176.08:06:09.41#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:06:09.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:06:09.41#ibcon#[25=USB\r\n] 2006.176.08:06:09.41#ibcon#*before write, iclass 25, count 0 2006.176.08:06:09.41#ibcon#enter sib2, iclass 25, count 0 2006.176.08:06:09.41#ibcon#flushed, iclass 25, count 0 2006.176.08:06:09.41#ibcon#about to write, iclass 25, count 0 2006.176.08:06:09.41#ibcon#wrote, iclass 25, count 0 2006.176.08:06:09.41#ibcon#about to read 3, iclass 25, count 0 2006.176.08:06:09.44#ibcon#read 3, iclass 25, count 0 2006.176.08:06:09.44#ibcon#about to read 4, iclass 25, count 0 2006.176.08:06:09.44#ibcon#read 4, iclass 25, count 0 2006.176.08:06:09.44#ibcon#about to read 5, iclass 25, count 0 2006.176.08:06:09.44#ibcon#read 5, iclass 25, count 0 2006.176.08:06:09.44#ibcon#about to read 6, iclass 25, count 0 2006.176.08:06:09.44#ibcon#read 6, iclass 25, count 0 2006.176.08:06:09.44#ibcon#end of sib2, iclass 25, count 0 2006.176.08:06:09.44#ibcon#*after write, iclass 25, count 0 2006.176.08:06:09.44#ibcon#*before return 0, iclass 25, count 0 2006.176.08:06:09.44#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:09.44#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:09.44#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:06:09.44#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:06:09.44$vc4f8/valo=5,652.99 2006.176.08:06:09.44#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.08:06:09.44#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.08:06:09.44#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:09.44#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:09.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:09.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:09.44#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:06:09.44#ibcon#first serial, iclass 27, count 0 2006.176.08:06:09.44#ibcon#enter sib2, iclass 27, count 0 2006.176.08:06:09.44#ibcon#flushed, iclass 27, count 0 2006.176.08:06:09.44#ibcon#about to write, iclass 27, count 0 2006.176.08:06:09.44#ibcon#wrote, iclass 27, count 0 2006.176.08:06:09.44#ibcon#about to read 3, iclass 27, count 0 2006.176.08:06:09.46#ibcon#read 3, iclass 27, count 0 2006.176.08:06:09.46#ibcon#about to read 4, iclass 27, count 0 2006.176.08:06:09.46#ibcon#read 4, iclass 27, count 0 2006.176.08:06:09.46#ibcon#about to read 5, iclass 27, count 0 2006.176.08:06:09.46#ibcon#read 5, iclass 27, count 0 2006.176.08:06:09.46#ibcon#about to read 6, iclass 27, count 0 2006.176.08:06:09.46#ibcon#read 6, iclass 27, count 0 2006.176.08:06:09.46#ibcon#end of sib2, iclass 27, count 0 2006.176.08:06:09.46#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:06:09.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:06:09.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:06:09.46#ibcon#*before write, iclass 27, count 0 2006.176.08:06:09.46#ibcon#enter sib2, iclass 27, count 0 2006.176.08:06:09.46#ibcon#flushed, iclass 27, count 0 2006.176.08:06:09.46#ibcon#about to write, iclass 27, count 0 2006.176.08:06:09.46#ibcon#wrote, iclass 27, count 0 2006.176.08:06:09.46#ibcon#about to read 3, iclass 27, count 0 2006.176.08:06:09.50#ibcon#read 3, iclass 27, count 0 2006.176.08:06:09.50#ibcon#about to read 4, iclass 27, count 0 2006.176.08:06:09.50#ibcon#read 4, iclass 27, count 0 2006.176.08:06:09.50#ibcon#about to read 5, iclass 27, count 0 2006.176.08:06:09.50#ibcon#read 5, iclass 27, count 0 2006.176.08:06:09.50#ibcon#about to read 6, iclass 27, count 0 2006.176.08:06:09.50#ibcon#read 6, iclass 27, count 0 2006.176.08:06:09.50#ibcon#end of sib2, iclass 27, count 0 2006.176.08:06:09.50#ibcon#*after write, iclass 27, count 0 2006.176.08:06:09.50#ibcon#*before return 0, iclass 27, count 0 2006.176.08:06:09.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:09.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:09.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:06:09.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:06:09.50$vc4f8/va=5,7 2006.176.08:06:09.50#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.08:06:09.50#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.08:06:09.50#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:09.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:09.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:09.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:09.56#ibcon#enter wrdev, iclass 29, count 2 2006.176.08:06:09.56#ibcon#first serial, iclass 29, count 2 2006.176.08:06:09.56#ibcon#enter sib2, iclass 29, count 2 2006.176.08:06:09.56#ibcon#flushed, iclass 29, count 2 2006.176.08:06:09.56#ibcon#about to write, iclass 29, count 2 2006.176.08:06:09.56#ibcon#wrote, iclass 29, count 2 2006.176.08:06:09.56#ibcon#about to read 3, iclass 29, count 2 2006.176.08:06:09.58#ibcon#read 3, iclass 29, count 2 2006.176.08:06:09.58#ibcon#about to read 4, iclass 29, count 2 2006.176.08:06:09.58#ibcon#read 4, iclass 29, count 2 2006.176.08:06:09.58#ibcon#about to read 5, iclass 29, count 2 2006.176.08:06:09.58#ibcon#read 5, iclass 29, count 2 2006.176.08:06:09.58#ibcon#about to read 6, iclass 29, count 2 2006.176.08:06:09.58#ibcon#read 6, iclass 29, count 2 2006.176.08:06:09.58#ibcon#end of sib2, iclass 29, count 2 2006.176.08:06:09.58#ibcon#*mode == 0, iclass 29, count 2 2006.176.08:06:09.58#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.08:06:09.58#ibcon#[25=AT05-07\r\n] 2006.176.08:06:09.58#ibcon#*before write, iclass 29, count 2 2006.176.08:06:09.58#ibcon#enter sib2, iclass 29, count 2 2006.176.08:06:09.58#ibcon#flushed, iclass 29, count 2 2006.176.08:06:09.58#ibcon#about to write, iclass 29, count 2 2006.176.08:06:09.58#ibcon#wrote, iclass 29, count 2 2006.176.08:06:09.58#ibcon#about to read 3, iclass 29, count 2 2006.176.08:06:09.61#ibcon#read 3, iclass 29, count 2 2006.176.08:06:09.61#ibcon#about to read 4, iclass 29, count 2 2006.176.08:06:09.61#ibcon#read 4, iclass 29, count 2 2006.176.08:06:09.61#ibcon#about to read 5, iclass 29, count 2 2006.176.08:06:09.61#ibcon#read 5, iclass 29, count 2 2006.176.08:06:09.61#ibcon#about to read 6, iclass 29, count 2 2006.176.08:06:09.61#ibcon#read 6, iclass 29, count 2 2006.176.08:06:09.61#ibcon#end of sib2, iclass 29, count 2 2006.176.08:06:09.61#ibcon#*after write, iclass 29, count 2 2006.176.08:06:09.61#ibcon#*before return 0, iclass 29, count 2 2006.176.08:06:09.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:09.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:09.61#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.08:06:09.61#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:09.61#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:09.73#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:09.73#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:09.73#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:06:09.73#ibcon#first serial, iclass 29, count 0 2006.176.08:06:09.73#ibcon#enter sib2, iclass 29, count 0 2006.176.08:06:09.73#ibcon#flushed, iclass 29, count 0 2006.176.08:06:09.73#ibcon#about to write, iclass 29, count 0 2006.176.08:06:09.73#ibcon#wrote, iclass 29, count 0 2006.176.08:06:09.73#ibcon#about to read 3, iclass 29, count 0 2006.176.08:06:09.75#ibcon#read 3, iclass 29, count 0 2006.176.08:06:09.75#ibcon#about to read 4, iclass 29, count 0 2006.176.08:06:09.75#ibcon#read 4, iclass 29, count 0 2006.176.08:06:09.75#ibcon#about to read 5, iclass 29, count 0 2006.176.08:06:09.75#ibcon#read 5, iclass 29, count 0 2006.176.08:06:09.75#ibcon#about to read 6, iclass 29, count 0 2006.176.08:06:09.75#ibcon#read 6, iclass 29, count 0 2006.176.08:06:09.75#ibcon#end of sib2, iclass 29, count 0 2006.176.08:06:09.75#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:06:09.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:06:09.75#ibcon#[25=USB\r\n] 2006.176.08:06:09.75#ibcon#*before write, iclass 29, count 0 2006.176.08:06:09.75#ibcon#enter sib2, iclass 29, count 0 2006.176.08:06:09.75#ibcon#flushed, iclass 29, count 0 2006.176.08:06:09.75#ibcon#about to write, iclass 29, count 0 2006.176.08:06:09.75#ibcon#wrote, iclass 29, count 0 2006.176.08:06:09.75#ibcon#about to read 3, iclass 29, count 0 2006.176.08:06:09.78#ibcon#read 3, iclass 29, count 0 2006.176.08:06:09.78#ibcon#about to read 4, iclass 29, count 0 2006.176.08:06:09.78#ibcon#read 4, iclass 29, count 0 2006.176.08:06:09.78#ibcon#about to read 5, iclass 29, count 0 2006.176.08:06:09.78#ibcon#read 5, iclass 29, count 0 2006.176.08:06:09.78#ibcon#about to read 6, iclass 29, count 0 2006.176.08:06:09.78#ibcon#read 6, iclass 29, count 0 2006.176.08:06:09.78#ibcon#end of sib2, iclass 29, count 0 2006.176.08:06:09.78#ibcon#*after write, iclass 29, count 0 2006.176.08:06:09.78#ibcon#*before return 0, iclass 29, count 0 2006.176.08:06:09.78#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:09.78#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:09.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:06:09.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:06:09.78$vc4f8/valo=6,772.99 2006.176.08:06:09.78#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.08:06:09.78#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.08:06:09.78#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:09.78#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:09.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:09.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:09.78#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:06:09.78#ibcon#first serial, iclass 31, count 0 2006.176.08:06:09.78#ibcon#enter sib2, iclass 31, count 0 2006.176.08:06:09.78#ibcon#flushed, iclass 31, count 0 2006.176.08:06:09.78#ibcon#about to write, iclass 31, count 0 2006.176.08:06:09.78#ibcon#wrote, iclass 31, count 0 2006.176.08:06:09.78#ibcon#about to read 3, iclass 31, count 0 2006.176.08:06:09.80#ibcon#read 3, iclass 31, count 0 2006.176.08:06:09.80#ibcon#about to read 4, iclass 31, count 0 2006.176.08:06:09.80#ibcon#read 4, iclass 31, count 0 2006.176.08:06:09.80#ibcon#about to read 5, iclass 31, count 0 2006.176.08:06:09.80#ibcon#read 5, iclass 31, count 0 2006.176.08:06:09.80#ibcon#about to read 6, iclass 31, count 0 2006.176.08:06:09.80#ibcon#read 6, iclass 31, count 0 2006.176.08:06:09.80#ibcon#end of sib2, iclass 31, count 0 2006.176.08:06:09.80#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:06:09.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:06:09.80#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:06:09.80#ibcon#*before write, iclass 31, count 0 2006.176.08:06:09.80#ibcon#enter sib2, iclass 31, count 0 2006.176.08:06:09.80#ibcon#flushed, iclass 31, count 0 2006.176.08:06:09.80#ibcon#about to write, iclass 31, count 0 2006.176.08:06:09.80#ibcon#wrote, iclass 31, count 0 2006.176.08:06:09.80#ibcon#about to read 3, iclass 31, count 0 2006.176.08:06:09.84#ibcon#read 3, iclass 31, count 0 2006.176.08:06:09.84#ibcon#about to read 4, iclass 31, count 0 2006.176.08:06:09.84#ibcon#read 4, iclass 31, count 0 2006.176.08:06:09.84#ibcon#about to read 5, iclass 31, count 0 2006.176.08:06:09.84#ibcon#read 5, iclass 31, count 0 2006.176.08:06:09.84#ibcon#about to read 6, iclass 31, count 0 2006.176.08:06:09.84#ibcon#read 6, iclass 31, count 0 2006.176.08:06:09.84#ibcon#end of sib2, iclass 31, count 0 2006.176.08:06:09.84#ibcon#*after write, iclass 31, count 0 2006.176.08:06:09.84#ibcon#*before return 0, iclass 31, count 0 2006.176.08:06:09.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:09.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:09.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:06:09.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:06:09.84$vc4f8/va=6,6 2006.176.08:06:09.84#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.176.08:06:09.84#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.176.08:06:09.84#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:09.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:06:09.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:06:09.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:06:09.90#ibcon#enter wrdev, iclass 33, count 2 2006.176.08:06:09.90#ibcon#first serial, iclass 33, count 2 2006.176.08:06:09.90#ibcon#enter sib2, iclass 33, count 2 2006.176.08:06:09.90#ibcon#flushed, iclass 33, count 2 2006.176.08:06:09.90#ibcon#about to write, iclass 33, count 2 2006.176.08:06:09.90#ibcon#wrote, iclass 33, count 2 2006.176.08:06:09.90#ibcon#about to read 3, iclass 33, count 2 2006.176.08:06:09.92#ibcon#read 3, iclass 33, count 2 2006.176.08:06:09.92#ibcon#about to read 4, iclass 33, count 2 2006.176.08:06:09.92#ibcon#read 4, iclass 33, count 2 2006.176.08:06:09.92#ibcon#about to read 5, iclass 33, count 2 2006.176.08:06:09.92#ibcon#read 5, iclass 33, count 2 2006.176.08:06:09.92#ibcon#about to read 6, iclass 33, count 2 2006.176.08:06:09.92#ibcon#read 6, iclass 33, count 2 2006.176.08:06:09.92#ibcon#end of sib2, iclass 33, count 2 2006.176.08:06:09.92#ibcon#*mode == 0, iclass 33, count 2 2006.176.08:06:09.92#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.176.08:06:09.92#ibcon#[25=AT06-06\r\n] 2006.176.08:06:09.92#ibcon#*before write, iclass 33, count 2 2006.176.08:06:09.92#ibcon#enter sib2, iclass 33, count 2 2006.176.08:06:09.92#ibcon#flushed, iclass 33, count 2 2006.176.08:06:09.92#ibcon#about to write, iclass 33, count 2 2006.176.08:06:09.92#ibcon#wrote, iclass 33, count 2 2006.176.08:06:09.92#ibcon#about to read 3, iclass 33, count 2 2006.176.08:06:09.95#ibcon#read 3, iclass 33, count 2 2006.176.08:06:09.95#ibcon#about to read 4, iclass 33, count 2 2006.176.08:06:09.95#ibcon#read 4, iclass 33, count 2 2006.176.08:06:09.95#ibcon#about to read 5, iclass 33, count 2 2006.176.08:06:09.95#ibcon#read 5, iclass 33, count 2 2006.176.08:06:09.95#ibcon#about to read 6, iclass 33, count 2 2006.176.08:06:09.95#ibcon#read 6, iclass 33, count 2 2006.176.08:06:09.95#ibcon#end of sib2, iclass 33, count 2 2006.176.08:06:09.95#ibcon#*after write, iclass 33, count 2 2006.176.08:06:09.95#ibcon#*before return 0, iclass 33, count 2 2006.176.08:06:09.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:06:09.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:06:09.95#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.176.08:06:09.95#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:09.95#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:06:10.07#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:06:10.07#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:06:10.07#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:06:10.07#ibcon#first serial, iclass 33, count 0 2006.176.08:06:10.07#ibcon#enter sib2, iclass 33, count 0 2006.176.08:06:10.07#ibcon#flushed, iclass 33, count 0 2006.176.08:06:10.07#ibcon#about to write, iclass 33, count 0 2006.176.08:06:10.07#ibcon#wrote, iclass 33, count 0 2006.176.08:06:10.07#ibcon#about to read 3, iclass 33, count 0 2006.176.08:06:10.09#ibcon#read 3, iclass 33, count 0 2006.176.08:06:10.09#ibcon#about to read 4, iclass 33, count 0 2006.176.08:06:10.09#ibcon#read 4, iclass 33, count 0 2006.176.08:06:10.09#ibcon#about to read 5, iclass 33, count 0 2006.176.08:06:10.09#ibcon#read 5, iclass 33, count 0 2006.176.08:06:10.09#ibcon#about to read 6, iclass 33, count 0 2006.176.08:06:10.09#ibcon#read 6, iclass 33, count 0 2006.176.08:06:10.09#ibcon#end of sib2, iclass 33, count 0 2006.176.08:06:10.09#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:06:10.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:06:10.09#ibcon#[25=USB\r\n] 2006.176.08:06:10.09#ibcon#*before write, iclass 33, count 0 2006.176.08:06:10.09#ibcon#enter sib2, iclass 33, count 0 2006.176.08:06:10.09#ibcon#flushed, iclass 33, count 0 2006.176.08:06:10.09#ibcon#about to write, iclass 33, count 0 2006.176.08:06:10.09#ibcon#wrote, iclass 33, count 0 2006.176.08:06:10.09#ibcon#about to read 3, iclass 33, count 0 2006.176.08:06:10.12#ibcon#read 3, iclass 33, count 0 2006.176.08:06:10.12#ibcon#about to read 4, iclass 33, count 0 2006.176.08:06:10.12#ibcon#read 4, iclass 33, count 0 2006.176.08:06:10.12#ibcon#about to read 5, iclass 33, count 0 2006.176.08:06:10.12#ibcon#read 5, iclass 33, count 0 2006.176.08:06:10.12#ibcon#about to read 6, iclass 33, count 0 2006.176.08:06:10.12#ibcon#read 6, iclass 33, count 0 2006.176.08:06:10.12#ibcon#end of sib2, iclass 33, count 0 2006.176.08:06:10.12#ibcon#*after write, iclass 33, count 0 2006.176.08:06:10.12#ibcon#*before return 0, iclass 33, count 0 2006.176.08:06:10.12#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:06:10.12#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:06:10.12#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:06:10.12#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:06:10.12$vc4f8/valo=7,832.99 2006.176.08:06:10.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.08:06:10.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.08:06:10.12#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:10.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:06:10.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:06:10.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:06:10.12#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:06:10.12#ibcon#first serial, iclass 35, count 0 2006.176.08:06:10.12#ibcon#enter sib2, iclass 35, count 0 2006.176.08:06:10.12#ibcon#flushed, iclass 35, count 0 2006.176.08:06:10.12#ibcon#about to write, iclass 35, count 0 2006.176.08:06:10.12#ibcon#wrote, iclass 35, count 0 2006.176.08:06:10.12#ibcon#about to read 3, iclass 35, count 0 2006.176.08:06:10.14#ibcon#read 3, iclass 35, count 0 2006.176.08:06:10.14#ibcon#about to read 4, iclass 35, count 0 2006.176.08:06:10.14#ibcon#read 4, iclass 35, count 0 2006.176.08:06:10.14#ibcon#about to read 5, iclass 35, count 0 2006.176.08:06:10.14#ibcon#read 5, iclass 35, count 0 2006.176.08:06:10.14#ibcon#about to read 6, iclass 35, count 0 2006.176.08:06:10.14#ibcon#read 6, iclass 35, count 0 2006.176.08:06:10.14#ibcon#end of sib2, iclass 35, count 0 2006.176.08:06:10.14#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:06:10.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:06:10.14#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:06:10.14#ibcon#*before write, iclass 35, count 0 2006.176.08:06:10.14#ibcon#enter sib2, iclass 35, count 0 2006.176.08:06:10.14#ibcon#flushed, iclass 35, count 0 2006.176.08:06:10.14#ibcon#about to write, iclass 35, count 0 2006.176.08:06:10.14#ibcon#wrote, iclass 35, count 0 2006.176.08:06:10.14#ibcon#about to read 3, iclass 35, count 0 2006.176.08:06:10.18#ibcon#read 3, iclass 35, count 0 2006.176.08:06:10.18#ibcon#about to read 4, iclass 35, count 0 2006.176.08:06:10.18#ibcon#read 4, iclass 35, count 0 2006.176.08:06:10.18#ibcon#about to read 5, iclass 35, count 0 2006.176.08:06:10.18#ibcon#read 5, iclass 35, count 0 2006.176.08:06:10.18#ibcon#about to read 6, iclass 35, count 0 2006.176.08:06:10.18#ibcon#read 6, iclass 35, count 0 2006.176.08:06:10.18#ibcon#end of sib2, iclass 35, count 0 2006.176.08:06:10.18#ibcon#*after write, iclass 35, count 0 2006.176.08:06:10.18#ibcon#*before return 0, iclass 35, count 0 2006.176.08:06:10.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:06:10.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:06:10.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:06:10.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:06:10.18$vc4f8/va=7,6 2006.176.08:06:10.18#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.176.08:06:10.18#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.176.08:06:10.18#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:10.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:06:10.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:06:10.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:06:10.24#ibcon#enter wrdev, iclass 37, count 2 2006.176.08:06:10.24#ibcon#first serial, iclass 37, count 2 2006.176.08:06:10.24#ibcon#enter sib2, iclass 37, count 2 2006.176.08:06:10.24#ibcon#flushed, iclass 37, count 2 2006.176.08:06:10.24#ibcon#about to write, iclass 37, count 2 2006.176.08:06:10.24#ibcon#wrote, iclass 37, count 2 2006.176.08:06:10.24#ibcon#about to read 3, iclass 37, count 2 2006.176.08:06:10.26#ibcon#read 3, iclass 37, count 2 2006.176.08:06:10.26#ibcon#about to read 4, iclass 37, count 2 2006.176.08:06:10.26#ibcon#read 4, iclass 37, count 2 2006.176.08:06:10.26#ibcon#about to read 5, iclass 37, count 2 2006.176.08:06:10.26#ibcon#read 5, iclass 37, count 2 2006.176.08:06:10.26#ibcon#about to read 6, iclass 37, count 2 2006.176.08:06:10.26#ibcon#read 6, iclass 37, count 2 2006.176.08:06:10.26#ibcon#end of sib2, iclass 37, count 2 2006.176.08:06:10.26#ibcon#*mode == 0, iclass 37, count 2 2006.176.08:06:10.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.176.08:06:10.26#ibcon#[25=AT07-06\r\n] 2006.176.08:06:10.26#ibcon#*before write, iclass 37, count 2 2006.176.08:06:10.26#ibcon#enter sib2, iclass 37, count 2 2006.176.08:06:10.26#ibcon#flushed, iclass 37, count 2 2006.176.08:06:10.26#ibcon#about to write, iclass 37, count 2 2006.176.08:06:10.26#ibcon#wrote, iclass 37, count 2 2006.176.08:06:10.26#ibcon#about to read 3, iclass 37, count 2 2006.176.08:06:10.29#ibcon#read 3, iclass 37, count 2 2006.176.08:06:10.29#ibcon#about to read 4, iclass 37, count 2 2006.176.08:06:10.29#ibcon#read 4, iclass 37, count 2 2006.176.08:06:10.29#ibcon#about to read 5, iclass 37, count 2 2006.176.08:06:10.29#ibcon#read 5, iclass 37, count 2 2006.176.08:06:10.29#ibcon#about to read 6, iclass 37, count 2 2006.176.08:06:10.29#ibcon#read 6, iclass 37, count 2 2006.176.08:06:10.29#ibcon#end of sib2, iclass 37, count 2 2006.176.08:06:10.29#ibcon#*after write, iclass 37, count 2 2006.176.08:06:10.29#ibcon#*before return 0, iclass 37, count 2 2006.176.08:06:10.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:06:10.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:06:10.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.176.08:06:10.29#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:10.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:06:10.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:06:10.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:06:10.41#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:06:10.41#ibcon#first serial, iclass 37, count 0 2006.176.08:06:10.41#ibcon#enter sib2, iclass 37, count 0 2006.176.08:06:10.41#ibcon#flushed, iclass 37, count 0 2006.176.08:06:10.41#ibcon#about to write, iclass 37, count 0 2006.176.08:06:10.41#ibcon#wrote, iclass 37, count 0 2006.176.08:06:10.41#ibcon#about to read 3, iclass 37, count 0 2006.176.08:06:10.43#ibcon#read 3, iclass 37, count 0 2006.176.08:06:10.43#ibcon#about to read 4, iclass 37, count 0 2006.176.08:06:10.43#ibcon#read 4, iclass 37, count 0 2006.176.08:06:10.43#ibcon#about to read 5, iclass 37, count 0 2006.176.08:06:10.43#ibcon#read 5, iclass 37, count 0 2006.176.08:06:10.43#ibcon#about to read 6, iclass 37, count 0 2006.176.08:06:10.43#ibcon#read 6, iclass 37, count 0 2006.176.08:06:10.43#ibcon#end of sib2, iclass 37, count 0 2006.176.08:06:10.43#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:06:10.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:06:10.43#ibcon#[25=USB\r\n] 2006.176.08:06:10.43#ibcon#*before write, iclass 37, count 0 2006.176.08:06:10.43#ibcon#enter sib2, iclass 37, count 0 2006.176.08:06:10.43#ibcon#flushed, iclass 37, count 0 2006.176.08:06:10.43#ibcon#about to write, iclass 37, count 0 2006.176.08:06:10.43#ibcon#wrote, iclass 37, count 0 2006.176.08:06:10.43#ibcon#about to read 3, iclass 37, count 0 2006.176.08:06:10.46#ibcon#read 3, iclass 37, count 0 2006.176.08:06:10.46#ibcon#about to read 4, iclass 37, count 0 2006.176.08:06:10.46#ibcon#read 4, iclass 37, count 0 2006.176.08:06:10.46#ibcon#about to read 5, iclass 37, count 0 2006.176.08:06:10.46#ibcon#read 5, iclass 37, count 0 2006.176.08:06:10.46#ibcon#about to read 6, iclass 37, count 0 2006.176.08:06:10.46#ibcon#read 6, iclass 37, count 0 2006.176.08:06:10.46#ibcon#end of sib2, iclass 37, count 0 2006.176.08:06:10.46#ibcon#*after write, iclass 37, count 0 2006.176.08:06:10.46#ibcon#*before return 0, iclass 37, count 0 2006.176.08:06:10.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:06:10.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:06:10.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:06:10.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:06:10.46$vc4f8/valo=8,852.99 2006.176.08:06:10.46#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.08:06:10.46#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.08:06:10.46#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:10.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:06:10.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:06:10.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:06:10.46#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:06:10.46#ibcon#first serial, iclass 39, count 0 2006.176.08:06:10.46#ibcon#enter sib2, iclass 39, count 0 2006.176.08:06:10.46#ibcon#flushed, iclass 39, count 0 2006.176.08:06:10.46#ibcon#about to write, iclass 39, count 0 2006.176.08:06:10.46#ibcon#wrote, iclass 39, count 0 2006.176.08:06:10.46#ibcon#about to read 3, iclass 39, count 0 2006.176.08:06:10.48#ibcon#read 3, iclass 39, count 0 2006.176.08:06:10.48#ibcon#about to read 4, iclass 39, count 0 2006.176.08:06:10.48#ibcon#read 4, iclass 39, count 0 2006.176.08:06:10.48#ibcon#about to read 5, iclass 39, count 0 2006.176.08:06:10.48#ibcon#read 5, iclass 39, count 0 2006.176.08:06:10.48#ibcon#about to read 6, iclass 39, count 0 2006.176.08:06:10.48#ibcon#read 6, iclass 39, count 0 2006.176.08:06:10.48#ibcon#end of sib2, iclass 39, count 0 2006.176.08:06:10.48#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:06:10.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:06:10.48#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:06:10.48#ibcon#*before write, iclass 39, count 0 2006.176.08:06:10.48#ibcon#enter sib2, iclass 39, count 0 2006.176.08:06:10.48#ibcon#flushed, iclass 39, count 0 2006.176.08:06:10.48#ibcon#about to write, iclass 39, count 0 2006.176.08:06:10.48#ibcon#wrote, iclass 39, count 0 2006.176.08:06:10.48#ibcon#about to read 3, iclass 39, count 0 2006.176.08:06:10.52#ibcon#read 3, iclass 39, count 0 2006.176.08:06:10.52#ibcon#about to read 4, iclass 39, count 0 2006.176.08:06:10.52#ibcon#read 4, iclass 39, count 0 2006.176.08:06:10.52#ibcon#about to read 5, iclass 39, count 0 2006.176.08:06:10.52#ibcon#read 5, iclass 39, count 0 2006.176.08:06:10.52#ibcon#about to read 6, iclass 39, count 0 2006.176.08:06:10.52#ibcon#read 6, iclass 39, count 0 2006.176.08:06:10.52#ibcon#end of sib2, iclass 39, count 0 2006.176.08:06:10.52#ibcon#*after write, iclass 39, count 0 2006.176.08:06:10.52#ibcon#*before return 0, iclass 39, count 0 2006.176.08:06:10.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:06:10.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:06:10.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:06:10.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:06:10.52$vc4f8/va=8,6 2006.176.08:06:10.52#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.08:06:10.52#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.08:06:10.52#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:10.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:06:10.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:06:10.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:06:10.58#ibcon#enter wrdev, iclass 3, count 2 2006.176.08:06:10.58#ibcon#first serial, iclass 3, count 2 2006.176.08:06:10.58#ibcon#enter sib2, iclass 3, count 2 2006.176.08:06:10.58#ibcon#flushed, iclass 3, count 2 2006.176.08:06:10.58#ibcon#about to write, iclass 3, count 2 2006.176.08:06:10.58#ibcon#wrote, iclass 3, count 2 2006.176.08:06:10.58#ibcon#about to read 3, iclass 3, count 2 2006.176.08:06:10.60#ibcon#read 3, iclass 3, count 2 2006.176.08:06:10.60#ibcon#about to read 4, iclass 3, count 2 2006.176.08:06:10.60#ibcon#read 4, iclass 3, count 2 2006.176.08:06:10.60#ibcon#about to read 5, iclass 3, count 2 2006.176.08:06:10.60#ibcon#read 5, iclass 3, count 2 2006.176.08:06:10.60#ibcon#about to read 6, iclass 3, count 2 2006.176.08:06:10.60#ibcon#read 6, iclass 3, count 2 2006.176.08:06:10.60#ibcon#end of sib2, iclass 3, count 2 2006.176.08:06:10.60#ibcon#*mode == 0, iclass 3, count 2 2006.176.08:06:10.60#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.08:06:10.60#ibcon#[25=AT08-06\r\n] 2006.176.08:06:10.60#ibcon#*before write, iclass 3, count 2 2006.176.08:06:10.60#ibcon#enter sib2, iclass 3, count 2 2006.176.08:06:10.60#ibcon#flushed, iclass 3, count 2 2006.176.08:06:10.60#ibcon#about to write, iclass 3, count 2 2006.176.08:06:10.60#ibcon#wrote, iclass 3, count 2 2006.176.08:06:10.60#ibcon#about to read 3, iclass 3, count 2 2006.176.08:06:10.63#ibcon#read 3, iclass 3, count 2 2006.176.08:06:10.63#ibcon#about to read 4, iclass 3, count 2 2006.176.08:06:10.63#ibcon#read 4, iclass 3, count 2 2006.176.08:06:10.63#ibcon#about to read 5, iclass 3, count 2 2006.176.08:06:10.63#ibcon#read 5, iclass 3, count 2 2006.176.08:06:10.63#ibcon#about to read 6, iclass 3, count 2 2006.176.08:06:10.63#ibcon#read 6, iclass 3, count 2 2006.176.08:06:10.63#ibcon#end of sib2, iclass 3, count 2 2006.176.08:06:10.63#ibcon#*after write, iclass 3, count 2 2006.176.08:06:10.63#ibcon#*before return 0, iclass 3, count 2 2006.176.08:06:10.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:06:10.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:06:10.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.08:06:10.63#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:10.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:06:10.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:06:10.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:06:10.75#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:06:10.75#ibcon#first serial, iclass 3, count 0 2006.176.08:06:10.75#ibcon#enter sib2, iclass 3, count 0 2006.176.08:06:10.75#ibcon#flushed, iclass 3, count 0 2006.176.08:06:10.75#ibcon#about to write, iclass 3, count 0 2006.176.08:06:10.75#ibcon#wrote, iclass 3, count 0 2006.176.08:06:10.75#ibcon#about to read 3, iclass 3, count 0 2006.176.08:06:10.77#ibcon#read 3, iclass 3, count 0 2006.176.08:06:10.77#ibcon#about to read 4, iclass 3, count 0 2006.176.08:06:10.77#ibcon#read 4, iclass 3, count 0 2006.176.08:06:10.77#ibcon#about to read 5, iclass 3, count 0 2006.176.08:06:10.77#ibcon#read 5, iclass 3, count 0 2006.176.08:06:10.77#ibcon#about to read 6, iclass 3, count 0 2006.176.08:06:10.77#ibcon#read 6, iclass 3, count 0 2006.176.08:06:10.77#ibcon#end of sib2, iclass 3, count 0 2006.176.08:06:10.77#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:06:10.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:06:10.77#ibcon#[25=USB\r\n] 2006.176.08:06:10.77#ibcon#*before write, iclass 3, count 0 2006.176.08:06:10.77#ibcon#enter sib2, iclass 3, count 0 2006.176.08:06:10.77#ibcon#flushed, iclass 3, count 0 2006.176.08:06:10.77#ibcon#about to write, iclass 3, count 0 2006.176.08:06:10.77#ibcon#wrote, iclass 3, count 0 2006.176.08:06:10.77#ibcon#about to read 3, iclass 3, count 0 2006.176.08:06:10.80#ibcon#read 3, iclass 3, count 0 2006.176.08:06:10.80#ibcon#about to read 4, iclass 3, count 0 2006.176.08:06:10.80#ibcon#read 4, iclass 3, count 0 2006.176.08:06:10.80#ibcon#about to read 5, iclass 3, count 0 2006.176.08:06:10.80#ibcon#read 5, iclass 3, count 0 2006.176.08:06:10.80#ibcon#about to read 6, iclass 3, count 0 2006.176.08:06:10.80#ibcon#read 6, iclass 3, count 0 2006.176.08:06:10.80#ibcon#end of sib2, iclass 3, count 0 2006.176.08:06:10.80#ibcon#*after write, iclass 3, count 0 2006.176.08:06:10.80#ibcon#*before return 0, iclass 3, count 0 2006.176.08:06:10.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:06:10.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:06:10.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:06:10.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:06:10.80$vc4f8/vblo=1,632.99 2006.176.08:06:10.80#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.08:06:10.80#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.08:06:10.80#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:10.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:10.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:10.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:10.80#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:06:10.80#ibcon#first serial, iclass 5, count 0 2006.176.08:06:10.80#ibcon#enter sib2, iclass 5, count 0 2006.176.08:06:10.80#ibcon#flushed, iclass 5, count 0 2006.176.08:06:10.80#ibcon#about to write, iclass 5, count 0 2006.176.08:06:10.80#ibcon#wrote, iclass 5, count 0 2006.176.08:06:10.80#ibcon#about to read 3, iclass 5, count 0 2006.176.08:06:10.82#ibcon#read 3, iclass 5, count 0 2006.176.08:06:10.82#ibcon#about to read 4, iclass 5, count 0 2006.176.08:06:10.82#ibcon#read 4, iclass 5, count 0 2006.176.08:06:10.82#ibcon#about to read 5, iclass 5, count 0 2006.176.08:06:10.82#ibcon#read 5, iclass 5, count 0 2006.176.08:06:10.82#ibcon#about to read 6, iclass 5, count 0 2006.176.08:06:10.82#ibcon#read 6, iclass 5, count 0 2006.176.08:06:10.82#ibcon#end of sib2, iclass 5, count 0 2006.176.08:06:10.82#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:06:10.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:06:10.82#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:06:10.82#ibcon#*before write, iclass 5, count 0 2006.176.08:06:10.82#ibcon#enter sib2, iclass 5, count 0 2006.176.08:06:10.82#ibcon#flushed, iclass 5, count 0 2006.176.08:06:10.82#ibcon#about to write, iclass 5, count 0 2006.176.08:06:10.82#ibcon#wrote, iclass 5, count 0 2006.176.08:06:10.82#ibcon#about to read 3, iclass 5, count 0 2006.176.08:06:10.86#ibcon#read 3, iclass 5, count 0 2006.176.08:06:10.86#ibcon#about to read 4, iclass 5, count 0 2006.176.08:06:10.86#ibcon#read 4, iclass 5, count 0 2006.176.08:06:10.86#ibcon#about to read 5, iclass 5, count 0 2006.176.08:06:10.86#ibcon#read 5, iclass 5, count 0 2006.176.08:06:10.86#ibcon#about to read 6, iclass 5, count 0 2006.176.08:06:10.86#ibcon#read 6, iclass 5, count 0 2006.176.08:06:10.86#ibcon#end of sib2, iclass 5, count 0 2006.176.08:06:10.86#ibcon#*after write, iclass 5, count 0 2006.176.08:06:10.86#ibcon#*before return 0, iclass 5, count 0 2006.176.08:06:10.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:10.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:06:10.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:06:10.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:06:10.86$vc4f8/vb=1,4 2006.176.08:06:10.86#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.08:06:10.86#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.08:06:10.86#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:10.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:10.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:10.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:10.86#ibcon#enter wrdev, iclass 7, count 2 2006.176.08:06:10.86#ibcon#first serial, iclass 7, count 2 2006.176.08:06:10.86#ibcon#enter sib2, iclass 7, count 2 2006.176.08:06:10.86#ibcon#flushed, iclass 7, count 2 2006.176.08:06:10.86#ibcon#about to write, iclass 7, count 2 2006.176.08:06:10.86#ibcon#wrote, iclass 7, count 2 2006.176.08:06:10.86#ibcon#about to read 3, iclass 7, count 2 2006.176.08:06:10.88#ibcon#read 3, iclass 7, count 2 2006.176.08:06:10.88#ibcon#about to read 4, iclass 7, count 2 2006.176.08:06:10.88#ibcon#read 4, iclass 7, count 2 2006.176.08:06:10.88#ibcon#about to read 5, iclass 7, count 2 2006.176.08:06:10.88#ibcon#read 5, iclass 7, count 2 2006.176.08:06:10.88#ibcon#about to read 6, iclass 7, count 2 2006.176.08:06:10.88#ibcon#read 6, iclass 7, count 2 2006.176.08:06:10.88#ibcon#end of sib2, iclass 7, count 2 2006.176.08:06:10.88#ibcon#*mode == 0, iclass 7, count 2 2006.176.08:06:10.88#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.08:06:10.88#ibcon#[27=AT01-04\r\n] 2006.176.08:06:10.88#ibcon#*before write, iclass 7, count 2 2006.176.08:06:10.88#ibcon#enter sib2, iclass 7, count 2 2006.176.08:06:10.88#ibcon#flushed, iclass 7, count 2 2006.176.08:06:10.88#ibcon#about to write, iclass 7, count 2 2006.176.08:06:10.88#ibcon#wrote, iclass 7, count 2 2006.176.08:06:10.88#ibcon#about to read 3, iclass 7, count 2 2006.176.08:06:10.91#ibcon#read 3, iclass 7, count 2 2006.176.08:06:10.91#ibcon#about to read 4, iclass 7, count 2 2006.176.08:06:10.91#ibcon#read 4, iclass 7, count 2 2006.176.08:06:10.91#ibcon#about to read 5, iclass 7, count 2 2006.176.08:06:10.91#ibcon#read 5, iclass 7, count 2 2006.176.08:06:10.91#ibcon#about to read 6, iclass 7, count 2 2006.176.08:06:10.91#ibcon#read 6, iclass 7, count 2 2006.176.08:06:10.91#ibcon#end of sib2, iclass 7, count 2 2006.176.08:06:10.91#ibcon#*after write, iclass 7, count 2 2006.176.08:06:10.91#ibcon#*before return 0, iclass 7, count 2 2006.176.08:06:10.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:10.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:06:10.91#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.08:06:10.91#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:10.91#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:11.03#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:11.03#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:11.03#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:06:11.03#ibcon#first serial, iclass 7, count 0 2006.176.08:06:11.03#ibcon#enter sib2, iclass 7, count 0 2006.176.08:06:11.03#ibcon#flushed, iclass 7, count 0 2006.176.08:06:11.03#ibcon#about to write, iclass 7, count 0 2006.176.08:06:11.03#ibcon#wrote, iclass 7, count 0 2006.176.08:06:11.03#ibcon#about to read 3, iclass 7, count 0 2006.176.08:06:11.05#ibcon#read 3, iclass 7, count 0 2006.176.08:06:11.05#ibcon#about to read 4, iclass 7, count 0 2006.176.08:06:11.05#ibcon#read 4, iclass 7, count 0 2006.176.08:06:11.05#ibcon#about to read 5, iclass 7, count 0 2006.176.08:06:11.05#ibcon#read 5, iclass 7, count 0 2006.176.08:06:11.05#ibcon#about to read 6, iclass 7, count 0 2006.176.08:06:11.05#ibcon#read 6, iclass 7, count 0 2006.176.08:06:11.05#ibcon#end of sib2, iclass 7, count 0 2006.176.08:06:11.05#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:06:11.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:06:11.05#ibcon#[27=USB\r\n] 2006.176.08:06:11.05#ibcon#*before write, iclass 7, count 0 2006.176.08:06:11.05#ibcon#enter sib2, iclass 7, count 0 2006.176.08:06:11.05#ibcon#flushed, iclass 7, count 0 2006.176.08:06:11.05#ibcon#about to write, iclass 7, count 0 2006.176.08:06:11.05#ibcon#wrote, iclass 7, count 0 2006.176.08:06:11.05#ibcon#about to read 3, iclass 7, count 0 2006.176.08:06:11.08#ibcon#read 3, iclass 7, count 0 2006.176.08:06:11.08#ibcon#about to read 4, iclass 7, count 0 2006.176.08:06:11.08#ibcon#read 4, iclass 7, count 0 2006.176.08:06:11.08#ibcon#about to read 5, iclass 7, count 0 2006.176.08:06:11.08#ibcon#read 5, iclass 7, count 0 2006.176.08:06:11.08#ibcon#about to read 6, iclass 7, count 0 2006.176.08:06:11.08#ibcon#read 6, iclass 7, count 0 2006.176.08:06:11.08#ibcon#end of sib2, iclass 7, count 0 2006.176.08:06:11.08#ibcon#*after write, iclass 7, count 0 2006.176.08:06:11.08#ibcon#*before return 0, iclass 7, count 0 2006.176.08:06:11.08#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:11.08#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:06:11.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:06:11.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:06:11.08$vc4f8/vblo=2,640.99 2006.176.08:06:11.08#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.08:06:11.08#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.08:06:11.08#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:11.08#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:11.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:11.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:11.08#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:06:11.08#ibcon#first serial, iclass 11, count 0 2006.176.08:06:11.08#ibcon#enter sib2, iclass 11, count 0 2006.176.08:06:11.08#ibcon#flushed, iclass 11, count 0 2006.176.08:06:11.08#ibcon#about to write, iclass 11, count 0 2006.176.08:06:11.08#ibcon#wrote, iclass 11, count 0 2006.176.08:06:11.08#ibcon#about to read 3, iclass 11, count 0 2006.176.08:06:11.10#ibcon#read 3, iclass 11, count 0 2006.176.08:06:11.10#ibcon#about to read 4, iclass 11, count 0 2006.176.08:06:11.10#ibcon#read 4, iclass 11, count 0 2006.176.08:06:11.10#ibcon#about to read 5, iclass 11, count 0 2006.176.08:06:11.10#ibcon#read 5, iclass 11, count 0 2006.176.08:06:11.10#ibcon#about to read 6, iclass 11, count 0 2006.176.08:06:11.10#ibcon#read 6, iclass 11, count 0 2006.176.08:06:11.10#ibcon#end of sib2, iclass 11, count 0 2006.176.08:06:11.10#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:06:11.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:06:11.10#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:06:11.10#ibcon#*before write, iclass 11, count 0 2006.176.08:06:11.10#ibcon#enter sib2, iclass 11, count 0 2006.176.08:06:11.10#ibcon#flushed, iclass 11, count 0 2006.176.08:06:11.10#ibcon#about to write, iclass 11, count 0 2006.176.08:06:11.10#ibcon#wrote, iclass 11, count 0 2006.176.08:06:11.10#ibcon#about to read 3, iclass 11, count 0 2006.176.08:06:11.14#ibcon#read 3, iclass 11, count 0 2006.176.08:06:11.14#ibcon#about to read 4, iclass 11, count 0 2006.176.08:06:11.14#ibcon#read 4, iclass 11, count 0 2006.176.08:06:11.14#ibcon#about to read 5, iclass 11, count 0 2006.176.08:06:11.14#ibcon#read 5, iclass 11, count 0 2006.176.08:06:11.14#ibcon#about to read 6, iclass 11, count 0 2006.176.08:06:11.14#ibcon#read 6, iclass 11, count 0 2006.176.08:06:11.14#ibcon#end of sib2, iclass 11, count 0 2006.176.08:06:11.14#ibcon#*after write, iclass 11, count 0 2006.176.08:06:11.14#ibcon#*before return 0, iclass 11, count 0 2006.176.08:06:11.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:11.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:06:11.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:06:11.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:06:11.14$vc4f8/vb=2,4 2006.176.08:06:11.14#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.08:06:11.14#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.08:06:11.14#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:11.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:11.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:11.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:11.20#ibcon#enter wrdev, iclass 13, count 2 2006.176.08:06:11.20#ibcon#first serial, iclass 13, count 2 2006.176.08:06:11.20#ibcon#enter sib2, iclass 13, count 2 2006.176.08:06:11.20#ibcon#flushed, iclass 13, count 2 2006.176.08:06:11.20#ibcon#about to write, iclass 13, count 2 2006.176.08:06:11.20#ibcon#wrote, iclass 13, count 2 2006.176.08:06:11.20#ibcon#about to read 3, iclass 13, count 2 2006.176.08:06:11.22#ibcon#read 3, iclass 13, count 2 2006.176.08:06:11.22#ibcon#about to read 4, iclass 13, count 2 2006.176.08:06:11.22#ibcon#read 4, iclass 13, count 2 2006.176.08:06:11.22#ibcon#about to read 5, iclass 13, count 2 2006.176.08:06:11.22#ibcon#read 5, iclass 13, count 2 2006.176.08:06:11.22#ibcon#about to read 6, iclass 13, count 2 2006.176.08:06:11.22#ibcon#read 6, iclass 13, count 2 2006.176.08:06:11.22#ibcon#end of sib2, iclass 13, count 2 2006.176.08:06:11.22#ibcon#*mode == 0, iclass 13, count 2 2006.176.08:06:11.22#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.08:06:11.22#ibcon#[27=AT02-04\r\n] 2006.176.08:06:11.22#ibcon#*before write, iclass 13, count 2 2006.176.08:06:11.22#ibcon#enter sib2, iclass 13, count 2 2006.176.08:06:11.22#ibcon#flushed, iclass 13, count 2 2006.176.08:06:11.22#ibcon#about to write, iclass 13, count 2 2006.176.08:06:11.22#ibcon#wrote, iclass 13, count 2 2006.176.08:06:11.22#ibcon#about to read 3, iclass 13, count 2 2006.176.08:06:11.25#ibcon#read 3, iclass 13, count 2 2006.176.08:06:11.25#ibcon#about to read 4, iclass 13, count 2 2006.176.08:06:11.25#ibcon#read 4, iclass 13, count 2 2006.176.08:06:11.25#ibcon#about to read 5, iclass 13, count 2 2006.176.08:06:11.25#ibcon#read 5, iclass 13, count 2 2006.176.08:06:11.25#ibcon#about to read 6, iclass 13, count 2 2006.176.08:06:11.25#ibcon#read 6, iclass 13, count 2 2006.176.08:06:11.25#ibcon#end of sib2, iclass 13, count 2 2006.176.08:06:11.25#ibcon#*after write, iclass 13, count 2 2006.176.08:06:11.25#ibcon#*before return 0, iclass 13, count 2 2006.176.08:06:11.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:11.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:06:11.25#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.08:06:11.25#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:11.25#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:11.37#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:11.37#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:11.37#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:06:11.37#ibcon#first serial, iclass 13, count 0 2006.176.08:06:11.37#ibcon#enter sib2, iclass 13, count 0 2006.176.08:06:11.37#ibcon#flushed, iclass 13, count 0 2006.176.08:06:11.37#ibcon#about to write, iclass 13, count 0 2006.176.08:06:11.37#ibcon#wrote, iclass 13, count 0 2006.176.08:06:11.37#ibcon#about to read 3, iclass 13, count 0 2006.176.08:06:11.39#ibcon#read 3, iclass 13, count 0 2006.176.08:06:11.39#ibcon#about to read 4, iclass 13, count 0 2006.176.08:06:11.39#ibcon#read 4, iclass 13, count 0 2006.176.08:06:11.39#ibcon#about to read 5, iclass 13, count 0 2006.176.08:06:11.39#ibcon#read 5, iclass 13, count 0 2006.176.08:06:11.39#ibcon#about to read 6, iclass 13, count 0 2006.176.08:06:11.39#ibcon#read 6, iclass 13, count 0 2006.176.08:06:11.39#ibcon#end of sib2, iclass 13, count 0 2006.176.08:06:11.39#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:06:11.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:06:11.39#ibcon#[27=USB\r\n] 2006.176.08:06:11.39#ibcon#*before write, iclass 13, count 0 2006.176.08:06:11.39#ibcon#enter sib2, iclass 13, count 0 2006.176.08:06:11.39#ibcon#flushed, iclass 13, count 0 2006.176.08:06:11.39#ibcon#about to write, iclass 13, count 0 2006.176.08:06:11.39#ibcon#wrote, iclass 13, count 0 2006.176.08:06:11.39#ibcon#about to read 3, iclass 13, count 0 2006.176.08:06:11.42#ibcon#read 3, iclass 13, count 0 2006.176.08:06:11.42#ibcon#about to read 4, iclass 13, count 0 2006.176.08:06:11.42#ibcon#read 4, iclass 13, count 0 2006.176.08:06:11.42#ibcon#about to read 5, iclass 13, count 0 2006.176.08:06:11.42#ibcon#read 5, iclass 13, count 0 2006.176.08:06:11.42#ibcon#about to read 6, iclass 13, count 0 2006.176.08:06:11.42#ibcon#read 6, iclass 13, count 0 2006.176.08:06:11.42#ibcon#end of sib2, iclass 13, count 0 2006.176.08:06:11.42#ibcon#*after write, iclass 13, count 0 2006.176.08:06:11.42#ibcon#*before return 0, iclass 13, count 0 2006.176.08:06:11.42#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:11.42#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:06:11.42#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:06:11.42#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:06:11.42$vc4f8/vblo=3,656.99 2006.176.08:06:11.42#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.08:06:11.42#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.08:06:11.42#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:11.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:06:11.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:06:11.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:06:11.42#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:06:11.42#ibcon#first serial, iclass 15, count 0 2006.176.08:06:11.42#ibcon#enter sib2, iclass 15, count 0 2006.176.08:06:11.42#ibcon#flushed, iclass 15, count 0 2006.176.08:06:11.42#ibcon#about to write, iclass 15, count 0 2006.176.08:06:11.42#ibcon#wrote, iclass 15, count 0 2006.176.08:06:11.42#ibcon#about to read 3, iclass 15, count 0 2006.176.08:06:11.44#ibcon#read 3, iclass 15, count 0 2006.176.08:06:11.44#ibcon#about to read 4, iclass 15, count 0 2006.176.08:06:11.44#ibcon#read 4, iclass 15, count 0 2006.176.08:06:11.44#ibcon#about to read 5, iclass 15, count 0 2006.176.08:06:11.44#ibcon#read 5, iclass 15, count 0 2006.176.08:06:11.44#ibcon#about to read 6, iclass 15, count 0 2006.176.08:06:11.44#ibcon#read 6, iclass 15, count 0 2006.176.08:06:11.44#ibcon#end of sib2, iclass 15, count 0 2006.176.08:06:11.44#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:06:11.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:06:11.44#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:06:11.44#ibcon#*before write, iclass 15, count 0 2006.176.08:06:11.44#ibcon#enter sib2, iclass 15, count 0 2006.176.08:06:11.44#ibcon#flushed, iclass 15, count 0 2006.176.08:06:11.44#ibcon#about to write, iclass 15, count 0 2006.176.08:06:11.44#ibcon#wrote, iclass 15, count 0 2006.176.08:06:11.44#ibcon#about to read 3, iclass 15, count 0 2006.176.08:06:11.48#ibcon#read 3, iclass 15, count 0 2006.176.08:06:11.48#ibcon#about to read 4, iclass 15, count 0 2006.176.08:06:11.48#ibcon#read 4, iclass 15, count 0 2006.176.08:06:11.48#ibcon#about to read 5, iclass 15, count 0 2006.176.08:06:11.48#ibcon#read 5, iclass 15, count 0 2006.176.08:06:11.48#ibcon#about to read 6, iclass 15, count 0 2006.176.08:06:11.48#ibcon#read 6, iclass 15, count 0 2006.176.08:06:11.48#ibcon#end of sib2, iclass 15, count 0 2006.176.08:06:11.48#ibcon#*after write, iclass 15, count 0 2006.176.08:06:11.48#ibcon#*before return 0, iclass 15, count 0 2006.176.08:06:11.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:06:11.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:06:11.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:06:11.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:06:11.48$vc4f8/vb=3,4 2006.176.08:06:11.48#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.176.08:06:11.48#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.176.08:06:11.48#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:11.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:06:11.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:06:11.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:06:11.54#ibcon#enter wrdev, iclass 17, count 2 2006.176.08:06:11.54#ibcon#first serial, iclass 17, count 2 2006.176.08:06:11.54#ibcon#enter sib2, iclass 17, count 2 2006.176.08:06:11.54#ibcon#flushed, iclass 17, count 2 2006.176.08:06:11.54#ibcon#about to write, iclass 17, count 2 2006.176.08:06:11.54#ibcon#wrote, iclass 17, count 2 2006.176.08:06:11.54#ibcon#about to read 3, iclass 17, count 2 2006.176.08:06:11.56#ibcon#read 3, iclass 17, count 2 2006.176.08:06:11.56#ibcon#about to read 4, iclass 17, count 2 2006.176.08:06:11.56#ibcon#read 4, iclass 17, count 2 2006.176.08:06:11.56#ibcon#about to read 5, iclass 17, count 2 2006.176.08:06:11.56#ibcon#read 5, iclass 17, count 2 2006.176.08:06:11.56#ibcon#about to read 6, iclass 17, count 2 2006.176.08:06:11.56#ibcon#read 6, iclass 17, count 2 2006.176.08:06:11.56#ibcon#end of sib2, iclass 17, count 2 2006.176.08:06:11.56#ibcon#*mode == 0, iclass 17, count 2 2006.176.08:06:11.56#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.176.08:06:11.56#ibcon#[27=AT03-04\r\n] 2006.176.08:06:11.56#ibcon#*before write, iclass 17, count 2 2006.176.08:06:11.56#ibcon#enter sib2, iclass 17, count 2 2006.176.08:06:11.56#ibcon#flushed, iclass 17, count 2 2006.176.08:06:11.56#ibcon#about to write, iclass 17, count 2 2006.176.08:06:11.56#ibcon#wrote, iclass 17, count 2 2006.176.08:06:11.56#ibcon#about to read 3, iclass 17, count 2 2006.176.08:06:11.59#ibcon#read 3, iclass 17, count 2 2006.176.08:06:11.59#ibcon#about to read 4, iclass 17, count 2 2006.176.08:06:11.59#ibcon#read 4, iclass 17, count 2 2006.176.08:06:11.59#ibcon#about to read 5, iclass 17, count 2 2006.176.08:06:11.59#ibcon#read 5, iclass 17, count 2 2006.176.08:06:11.59#ibcon#about to read 6, iclass 17, count 2 2006.176.08:06:11.59#ibcon#read 6, iclass 17, count 2 2006.176.08:06:11.59#ibcon#end of sib2, iclass 17, count 2 2006.176.08:06:11.59#ibcon#*after write, iclass 17, count 2 2006.176.08:06:11.59#ibcon#*before return 0, iclass 17, count 2 2006.176.08:06:11.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:06:11.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:06:11.59#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.176.08:06:11.59#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:11.59#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:06:11.71#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:06:11.71#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:06:11.71#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:06:11.71#ibcon#first serial, iclass 17, count 0 2006.176.08:06:11.71#ibcon#enter sib2, iclass 17, count 0 2006.176.08:06:11.71#ibcon#flushed, iclass 17, count 0 2006.176.08:06:11.71#ibcon#about to write, iclass 17, count 0 2006.176.08:06:11.71#ibcon#wrote, iclass 17, count 0 2006.176.08:06:11.71#ibcon#about to read 3, iclass 17, count 0 2006.176.08:06:11.73#ibcon#read 3, iclass 17, count 0 2006.176.08:06:11.73#ibcon#about to read 4, iclass 17, count 0 2006.176.08:06:11.73#ibcon#read 4, iclass 17, count 0 2006.176.08:06:11.73#ibcon#about to read 5, iclass 17, count 0 2006.176.08:06:11.73#ibcon#read 5, iclass 17, count 0 2006.176.08:06:11.73#ibcon#about to read 6, iclass 17, count 0 2006.176.08:06:11.73#ibcon#read 6, iclass 17, count 0 2006.176.08:06:11.73#ibcon#end of sib2, iclass 17, count 0 2006.176.08:06:11.73#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:06:11.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:06:11.73#ibcon#[27=USB\r\n] 2006.176.08:06:11.73#ibcon#*before write, iclass 17, count 0 2006.176.08:06:11.73#ibcon#enter sib2, iclass 17, count 0 2006.176.08:06:11.73#ibcon#flushed, iclass 17, count 0 2006.176.08:06:11.73#ibcon#about to write, iclass 17, count 0 2006.176.08:06:11.73#ibcon#wrote, iclass 17, count 0 2006.176.08:06:11.73#ibcon#about to read 3, iclass 17, count 0 2006.176.08:06:11.76#ibcon#read 3, iclass 17, count 0 2006.176.08:06:11.76#ibcon#about to read 4, iclass 17, count 0 2006.176.08:06:11.76#ibcon#read 4, iclass 17, count 0 2006.176.08:06:11.76#ibcon#about to read 5, iclass 17, count 0 2006.176.08:06:11.76#ibcon#read 5, iclass 17, count 0 2006.176.08:06:11.76#ibcon#about to read 6, iclass 17, count 0 2006.176.08:06:11.76#ibcon#read 6, iclass 17, count 0 2006.176.08:06:11.76#ibcon#end of sib2, iclass 17, count 0 2006.176.08:06:11.76#ibcon#*after write, iclass 17, count 0 2006.176.08:06:11.76#ibcon#*before return 0, iclass 17, count 0 2006.176.08:06:11.76#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:06:11.76#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:06:11.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:06:11.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:06:11.76$vc4f8/vblo=4,712.99 2006.176.08:06:11.76#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.176.08:06:11.76#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.176.08:06:11.76#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:11.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:06:11.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:06:11.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:06:11.76#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:06:11.76#ibcon#first serial, iclass 19, count 0 2006.176.08:06:11.76#ibcon#enter sib2, iclass 19, count 0 2006.176.08:06:11.76#ibcon#flushed, iclass 19, count 0 2006.176.08:06:11.76#ibcon#about to write, iclass 19, count 0 2006.176.08:06:11.76#ibcon#wrote, iclass 19, count 0 2006.176.08:06:11.76#ibcon#about to read 3, iclass 19, count 0 2006.176.08:06:11.78#ibcon#read 3, iclass 19, count 0 2006.176.08:06:11.78#ibcon#about to read 4, iclass 19, count 0 2006.176.08:06:11.78#ibcon#read 4, iclass 19, count 0 2006.176.08:06:11.78#ibcon#about to read 5, iclass 19, count 0 2006.176.08:06:11.78#ibcon#read 5, iclass 19, count 0 2006.176.08:06:11.78#ibcon#about to read 6, iclass 19, count 0 2006.176.08:06:11.78#ibcon#read 6, iclass 19, count 0 2006.176.08:06:11.78#ibcon#end of sib2, iclass 19, count 0 2006.176.08:06:11.78#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:06:11.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:06:11.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:06:11.78#ibcon#*before write, iclass 19, count 0 2006.176.08:06:11.78#ibcon#enter sib2, iclass 19, count 0 2006.176.08:06:11.78#ibcon#flushed, iclass 19, count 0 2006.176.08:06:11.78#ibcon#about to write, iclass 19, count 0 2006.176.08:06:11.78#ibcon#wrote, iclass 19, count 0 2006.176.08:06:11.78#ibcon#about to read 3, iclass 19, count 0 2006.176.08:06:11.82#ibcon#read 3, iclass 19, count 0 2006.176.08:06:11.82#ibcon#about to read 4, iclass 19, count 0 2006.176.08:06:11.82#ibcon#read 4, iclass 19, count 0 2006.176.08:06:11.82#ibcon#about to read 5, iclass 19, count 0 2006.176.08:06:11.82#ibcon#read 5, iclass 19, count 0 2006.176.08:06:11.82#ibcon#about to read 6, iclass 19, count 0 2006.176.08:06:11.82#ibcon#read 6, iclass 19, count 0 2006.176.08:06:11.82#ibcon#end of sib2, iclass 19, count 0 2006.176.08:06:11.82#ibcon#*after write, iclass 19, count 0 2006.176.08:06:11.82#ibcon#*before return 0, iclass 19, count 0 2006.176.08:06:11.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:06:11.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:06:11.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:06:11.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:06:11.82$vc4f8/vb=4,4 2006.176.08:06:11.82#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.176.08:06:11.82#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.176.08:06:11.82#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:11.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:06:11.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:06:11.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:06:11.88#ibcon#enter wrdev, iclass 21, count 2 2006.176.08:06:11.88#ibcon#first serial, iclass 21, count 2 2006.176.08:06:11.88#ibcon#enter sib2, iclass 21, count 2 2006.176.08:06:11.88#ibcon#flushed, iclass 21, count 2 2006.176.08:06:11.88#ibcon#about to write, iclass 21, count 2 2006.176.08:06:11.88#ibcon#wrote, iclass 21, count 2 2006.176.08:06:11.88#ibcon#about to read 3, iclass 21, count 2 2006.176.08:06:11.90#ibcon#read 3, iclass 21, count 2 2006.176.08:06:11.90#ibcon#about to read 4, iclass 21, count 2 2006.176.08:06:11.90#ibcon#read 4, iclass 21, count 2 2006.176.08:06:11.90#ibcon#about to read 5, iclass 21, count 2 2006.176.08:06:11.90#ibcon#read 5, iclass 21, count 2 2006.176.08:06:11.90#ibcon#about to read 6, iclass 21, count 2 2006.176.08:06:11.90#ibcon#read 6, iclass 21, count 2 2006.176.08:06:11.90#ibcon#end of sib2, iclass 21, count 2 2006.176.08:06:11.90#ibcon#*mode == 0, iclass 21, count 2 2006.176.08:06:11.90#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.176.08:06:11.90#ibcon#[27=AT04-04\r\n] 2006.176.08:06:11.90#ibcon#*before write, iclass 21, count 2 2006.176.08:06:11.90#ibcon#enter sib2, iclass 21, count 2 2006.176.08:06:11.90#ibcon#flushed, iclass 21, count 2 2006.176.08:06:11.90#ibcon#about to write, iclass 21, count 2 2006.176.08:06:11.90#ibcon#wrote, iclass 21, count 2 2006.176.08:06:11.90#ibcon#about to read 3, iclass 21, count 2 2006.176.08:06:11.93#ibcon#read 3, iclass 21, count 2 2006.176.08:06:11.93#ibcon#about to read 4, iclass 21, count 2 2006.176.08:06:11.93#ibcon#read 4, iclass 21, count 2 2006.176.08:06:11.93#ibcon#about to read 5, iclass 21, count 2 2006.176.08:06:11.93#ibcon#read 5, iclass 21, count 2 2006.176.08:06:11.93#ibcon#about to read 6, iclass 21, count 2 2006.176.08:06:11.93#ibcon#read 6, iclass 21, count 2 2006.176.08:06:11.93#ibcon#end of sib2, iclass 21, count 2 2006.176.08:06:11.93#ibcon#*after write, iclass 21, count 2 2006.176.08:06:11.93#ibcon#*before return 0, iclass 21, count 2 2006.176.08:06:11.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:06:11.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:06:11.93#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.176.08:06:11.93#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:11.93#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:06:12.05#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:06:12.05#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:06:12.05#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:06:12.05#ibcon#first serial, iclass 21, count 0 2006.176.08:06:12.05#ibcon#enter sib2, iclass 21, count 0 2006.176.08:06:12.05#ibcon#flushed, iclass 21, count 0 2006.176.08:06:12.05#ibcon#about to write, iclass 21, count 0 2006.176.08:06:12.05#ibcon#wrote, iclass 21, count 0 2006.176.08:06:12.05#ibcon#about to read 3, iclass 21, count 0 2006.176.08:06:12.07#ibcon#read 3, iclass 21, count 0 2006.176.08:06:12.07#ibcon#about to read 4, iclass 21, count 0 2006.176.08:06:12.07#ibcon#read 4, iclass 21, count 0 2006.176.08:06:12.07#ibcon#about to read 5, iclass 21, count 0 2006.176.08:06:12.07#ibcon#read 5, iclass 21, count 0 2006.176.08:06:12.07#ibcon#about to read 6, iclass 21, count 0 2006.176.08:06:12.07#ibcon#read 6, iclass 21, count 0 2006.176.08:06:12.07#ibcon#end of sib2, iclass 21, count 0 2006.176.08:06:12.07#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:06:12.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:06:12.07#ibcon#[27=USB\r\n] 2006.176.08:06:12.07#ibcon#*before write, iclass 21, count 0 2006.176.08:06:12.07#ibcon#enter sib2, iclass 21, count 0 2006.176.08:06:12.07#ibcon#flushed, iclass 21, count 0 2006.176.08:06:12.07#ibcon#about to write, iclass 21, count 0 2006.176.08:06:12.07#ibcon#wrote, iclass 21, count 0 2006.176.08:06:12.07#ibcon#about to read 3, iclass 21, count 0 2006.176.08:06:12.10#ibcon#read 3, iclass 21, count 0 2006.176.08:06:12.10#ibcon#about to read 4, iclass 21, count 0 2006.176.08:06:12.10#ibcon#read 4, iclass 21, count 0 2006.176.08:06:12.10#ibcon#about to read 5, iclass 21, count 0 2006.176.08:06:12.10#ibcon#read 5, iclass 21, count 0 2006.176.08:06:12.10#ibcon#about to read 6, iclass 21, count 0 2006.176.08:06:12.10#ibcon#read 6, iclass 21, count 0 2006.176.08:06:12.10#ibcon#end of sib2, iclass 21, count 0 2006.176.08:06:12.10#ibcon#*after write, iclass 21, count 0 2006.176.08:06:12.10#ibcon#*before return 0, iclass 21, count 0 2006.176.08:06:12.10#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:06:12.10#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:06:12.10#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:06:12.10#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:06:12.10$vc4f8/vblo=5,744.99 2006.176.08:06:12.10#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.08:06:12.10#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.08:06:12.10#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:12.10#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:12.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:12.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:12.10#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:06:12.10#ibcon#first serial, iclass 23, count 0 2006.176.08:06:12.10#ibcon#enter sib2, iclass 23, count 0 2006.176.08:06:12.10#ibcon#flushed, iclass 23, count 0 2006.176.08:06:12.10#ibcon#about to write, iclass 23, count 0 2006.176.08:06:12.10#ibcon#wrote, iclass 23, count 0 2006.176.08:06:12.10#ibcon#about to read 3, iclass 23, count 0 2006.176.08:06:12.12#ibcon#read 3, iclass 23, count 0 2006.176.08:06:12.12#ibcon#about to read 4, iclass 23, count 0 2006.176.08:06:12.12#ibcon#read 4, iclass 23, count 0 2006.176.08:06:12.12#ibcon#about to read 5, iclass 23, count 0 2006.176.08:06:12.12#ibcon#read 5, iclass 23, count 0 2006.176.08:06:12.12#ibcon#about to read 6, iclass 23, count 0 2006.176.08:06:12.12#ibcon#read 6, iclass 23, count 0 2006.176.08:06:12.12#ibcon#end of sib2, iclass 23, count 0 2006.176.08:06:12.12#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:06:12.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:06:12.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:06:12.12#ibcon#*before write, iclass 23, count 0 2006.176.08:06:12.12#ibcon#enter sib2, iclass 23, count 0 2006.176.08:06:12.12#ibcon#flushed, iclass 23, count 0 2006.176.08:06:12.12#ibcon#about to write, iclass 23, count 0 2006.176.08:06:12.12#ibcon#wrote, iclass 23, count 0 2006.176.08:06:12.12#ibcon#about to read 3, iclass 23, count 0 2006.176.08:06:12.16#ibcon#read 3, iclass 23, count 0 2006.176.08:06:12.16#ibcon#about to read 4, iclass 23, count 0 2006.176.08:06:12.16#ibcon#read 4, iclass 23, count 0 2006.176.08:06:12.16#ibcon#about to read 5, iclass 23, count 0 2006.176.08:06:12.16#ibcon#read 5, iclass 23, count 0 2006.176.08:06:12.16#ibcon#about to read 6, iclass 23, count 0 2006.176.08:06:12.16#ibcon#read 6, iclass 23, count 0 2006.176.08:06:12.16#ibcon#end of sib2, iclass 23, count 0 2006.176.08:06:12.16#ibcon#*after write, iclass 23, count 0 2006.176.08:06:12.16#ibcon#*before return 0, iclass 23, count 0 2006.176.08:06:12.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:12.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:06:12.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:06:12.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:06:12.16$vc4f8/vb=5,4 2006.176.08:06:12.16#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.176.08:06:12.16#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.176.08:06:12.16#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:12.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:12.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:12.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:12.22#ibcon#enter wrdev, iclass 25, count 2 2006.176.08:06:12.22#ibcon#first serial, iclass 25, count 2 2006.176.08:06:12.22#ibcon#enter sib2, iclass 25, count 2 2006.176.08:06:12.22#ibcon#flushed, iclass 25, count 2 2006.176.08:06:12.22#ibcon#about to write, iclass 25, count 2 2006.176.08:06:12.22#ibcon#wrote, iclass 25, count 2 2006.176.08:06:12.22#ibcon#about to read 3, iclass 25, count 2 2006.176.08:06:12.24#ibcon#read 3, iclass 25, count 2 2006.176.08:06:12.24#ibcon#about to read 4, iclass 25, count 2 2006.176.08:06:12.24#ibcon#read 4, iclass 25, count 2 2006.176.08:06:12.24#ibcon#about to read 5, iclass 25, count 2 2006.176.08:06:12.24#ibcon#read 5, iclass 25, count 2 2006.176.08:06:12.24#ibcon#about to read 6, iclass 25, count 2 2006.176.08:06:12.24#ibcon#read 6, iclass 25, count 2 2006.176.08:06:12.24#ibcon#end of sib2, iclass 25, count 2 2006.176.08:06:12.24#ibcon#*mode == 0, iclass 25, count 2 2006.176.08:06:12.24#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.176.08:06:12.24#ibcon#[27=AT05-04\r\n] 2006.176.08:06:12.24#ibcon#*before write, iclass 25, count 2 2006.176.08:06:12.24#ibcon#enter sib2, iclass 25, count 2 2006.176.08:06:12.24#ibcon#flushed, iclass 25, count 2 2006.176.08:06:12.24#ibcon#about to write, iclass 25, count 2 2006.176.08:06:12.24#ibcon#wrote, iclass 25, count 2 2006.176.08:06:12.24#ibcon#about to read 3, iclass 25, count 2 2006.176.08:06:12.27#ibcon#read 3, iclass 25, count 2 2006.176.08:06:12.27#ibcon#about to read 4, iclass 25, count 2 2006.176.08:06:12.27#ibcon#read 4, iclass 25, count 2 2006.176.08:06:12.27#ibcon#about to read 5, iclass 25, count 2 2006.176.08:06:12.27#ibcon#read 5, iclass 25, count 2 2006.176.08:06:12.27#ibcon#about to read 6, iclass 25, count 2 2006.176.08:06:12.27#ibcon#read 6, iclass 25, count 2 2006.176.08:06:12.27#ibcon#end of sib2, iclass 25, count 2 2006.176.08:06:12.27#ibcon#*after write, iclass 25, count 2 2006.176.08:06:12.27#ibcon#*before return 0, iclass 25, count 2 2006.176.08:06:12.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:12.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:06:12.27#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.176.08:06:12.27#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:12.27#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:12.39#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:12.39#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:12.39#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:06:12.39#ibcon#first serial, iclass 25, count 0 2006.176.08:06:12.39#ibcon#enter sib2, iclass 25, count 0 2006.176.08:06:12.39#ibcon#flushed, iclass 25, count 0 2006.176.08:06:12.39#ibcon#about to write, iclass 25, count 0 2006.176.08:06:12.39#ibcon#wrote, iclass 25, count 0 2006.176.08:06:12.39#ibcon#about to read 3, iclass 25, count 0 2006.176.08:06:12.41#ibcon#read 3, iclass 25, count 0 2006.176.08:06:12.41#ibcon#about to read 4, iclass 25, count 0 2006.176.08:06:12.41#ibcon#read 4, iclass 25, count 0 2006.176.08:06:12.41#ibcon#about to read 5, iclass 25, count 0 2006.176.08:06:12.41#ibcon#read 5, iclass 25, count 0 2006.176.08:06:12.41#ibcon#about to read 6, iclass 25, count 0 2006.176.08:06:12.41#ibcon#read 6, iclass 25, count 0 2006.176.08:06:12.41#ibcon#end of sib2, iclass 25, count 0 2006.176.08:06:12.41#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:06:12.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:06:12.41#ibcon#[27=USB\r\n] 2006.176.08:06:12.41#ibcon#*before write, iclass 25, count 0 2006.176.08:06:12.41#ibcon#enter sib2, iclass 25, count 0 2006.176.08:06:12.41#ibcon#flushed, iclass 25, count 0 2006.176.08:06:12.41#ibcon#about to write, iclass 25, count 0 2006.176.08:06:12.41#ibcon#wrote, iclass 25, count 0 2006.176.08:06:12.41#ibcon#about to read 3, iclass 25, count 0 2006.176.08:06:12.44#ibcon#read 3, iclass 25, count 0 2006.176.08:06:12.44#ibcon#about to read 4, iclass 25, count 0 2006.176.08:06:12.44#ibcon#read 4, iclass 25, count 0 2006.176.08:06:12.44#ibcon#about to read 5, iclass 25, count 0 2006.176.08:06:12.44#ibcon#read 5, iclass 25, count 0 2006.176.08:06:12.44#ibcon#about to read 6, iclass 25, count 0 2006.176.08:06:12.44#ibcon#read 6, iclass 25, count 0 2006.176.08:06:12.44#ibcon#end of sib2, iclass 25, count 0 2006.176.08:06:12.44#ibcon#*after write, iclass 25, count 0 2006.176.08:06:12.44#ibcon#*before return 0, iclass 25, count 0 2006.176.08:06:12.44#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:12.44#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:06:12.44#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:06:12.44#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:06:12.44$vc4f8/vblo=6,752.99 2006.176.08:06:12.44#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.08:06:12.44#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.08:06:12.44#ibcon#ireg 17 cls_cnt 0 2006.176.08:06:12.44#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:12.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:12.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:12.44#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:06:12.44#ibcon#first serial, iclass 27, count 0 2006.176.08:06:12.44#ibcon#enter sib2, iclass 27, count 0 2006.176.08:06:12.44#ibcon#flushed, iclass 27, count 0 2006.176.08:06:12.44#ibcon#about to write, iclass 27, count 0 2006.176.08:06:12.44#ibcon#wrote, iclass 27, count 0 2006.176.08:06:12.44#ibcon#about to read 3, iclass 27, count 0 2006.176.08:06:12.46#ibcon#read 3, iclass 27, count 0 2006.176.08:06:12.46#ibcon#about to read 4, iclass 27, count 0 2006.176.08:06:12.46#ibcon#read 4, iclass 27, count 0 2006.176.08:06:12.46#ibcon#about to read 5, iclass 27, count 0 2006.176.08:06:12.46#ibcon#read 5, iclass 27, count 0 2006.176.08:06:12.46#ibcon#about to read 6, iclass 27, count 0 2006.176.08:06:12.46#ibcon#read 6, iclass 27, count 0 2006.176.08:06:12.46#ibcon#end of sib2, iclass 27, count 0 2006.176.08:06:12.46#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:06:12.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:06:12.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:06:12.46#ibcon#*before write, iclass 27, count 0 2006.176.08:06:12.46#ibcon#enter sib2, iclass 27, count 0 2006.176.08:06:12.46#ibcon#flushed, iclass 27, count 0 2006.176.08:06:12.46#ibcon#about to write, iclass 27, count 0 2006.176.08:06:12.46#ibcon#wrote, iclass 27, count 0 2006.176.08:06:12.46#ibcon#about to read 3, iclass 27, count 0 2006.176.08:06:12.50#ibcon#read 3, iclass 27, count 0 2006.176.08:06:12.50#ibcon#about to read 4, iclass 27, count 0 2006.176.08:06:12.50#ibcon#read 4, iclass 27, count 0 2006.176.08:06:12.50#ibcon#about to read 5, iclass 27, count 0 2006.176.08:06:12.50#ibcon#read 5, iclass 27, count 0 2006.176.08:06:12.50#ibcon#about to read 6, iclass 27, count 0 2006.176.08:06:12.50#ibcon#read 6, iclass 27, count 0 2006.176.08:06:12.50#ibcon#end of sib2, iclass 27, count 0 2006.176.08:06:12.50#ibcon#*after write, iclass 27, count 0 2006.176.08:06:12.50#ibcon#*before return 0, iclass 27, count 0 2006.176.08:06:12.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:12.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:06:12.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:06:12.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:06:12.50$vc4f8/vb=6,4 2006.176.08:06:12.50#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.08:06:12.50#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.08:06:12.50#ibcon#ireg 11 cls_cnt 2 2006.176.08:06:12.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:12.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:12.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:12.56#ibcon#enter wrdev, iclass 29, count 2 2006.176.08:06:12.56#ibcon#first serial, iclass 29, count 2 2006.176.08:06:12.56#ibcon#enter sib2, iclass 29, count 2 2006.176.08:06:12.56#ibcon#flushed, iclass 29, count 2 2006.176.08:06:12.56#ibcon#about to write, iclass 29, count 2 2006.176.08:06:12.56#ibcon#wrote, iclass 29, count 2 2006.176.08:06:12.56#ibcon#about to read 3, iclass 29, count 2 2006.176.08:06:12.58#ibcon#read 3, iclass 29, count 2 2006.176.08:06:12.58#ibcon#about to read 4, iclass 29, count 2 2006.176.08:06:12.58#ibcon#read 4, iclass 29, count 2 2006.176.08:06:12.58#ibcon#about to read 5, iclass 29, count 2 2006.176.08:06:12.58#ibcon#read 5, iclass 29, count 2 2006.176.08:06:12.58#ibcon#about to read 6, iclass 29, count 2 2006.176.08:06:12.58#ibcon#read 6, iclass 29, count 2 2006.176.08:06:12.58#ibcon#end of sib2, iclass 29, count 2 2006.176.08:06:12.58#ibcon#*mode == 0, iclass 29, count 2 2006.176.08:06:12.58#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.08:06:12.58#ibcon#[27=AT06-04\r\n] 2006.176.08:06:12.58#ibcon#*before write, iclass 29, count 2 2006.176.08:06:12.58#ibcon#enter sib2, iclass 29, count 2 2006.176.08:06:12.58#ibcon#flushed, iclass 29, count 2 2006.176.08:06:12.58#ibcon#about to write, iclass 29, count 2 2006.176.08:06:12.58#ibcon#wrote, iclass 29, count 2 2006.176.08:06:12.58#ibcon#about to read 3, iclass 29, count 2 2006.176.08:06:12.61#ibcon#read 3, iclass 29, count 2 2006.176.08:06:12.61#ibcon#about to read 4, iclass 29, count 2 2006.176.08:06:12.61#ibcon#read 4, iclass 29, count 2 2006.176.08:06:12.61#ibcon#about to read 5, iclass 29, count 2 2006.176.08:06:12.61#ibcon#read 5, iclass 29, count 2 2006.176.08:06:12.61#ibcon#about to read 6, iclass 29, count 2 2006.176.08:06:12.61#ibcon#read 6, iclass 29, count 2 2006.176.08:06:12.61#ibcon#end of sib2, iclass 29, count 2 2006.176.08:06:12.61#ibcon#*after write, iclass 29, count 2 2006.176.08:06:12.61#ibcon#*before return 0, iclass 29, count 2 2006.176.08:06:12.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:12.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:06:12.61#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.08:06:12.61#ibcon#ireg 7 cls_cnt 0 2006.176.08:06:12.61#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:12.73#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:12.73#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:12.73#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:06:12.73#ibcon#first serial, iclass 29, count 0 2006.176.08:06:12.73#ibcon#enter sib2, iclass 29, count 0 2006.176.08:06:12.73#ibcon#flushed, iclass 29, count 0 2006.176.08:06:12.73#ibcon#about to write, iclass 29, count 0 2006.176.08:06:12.73#ibcon#wrote, iclass 29, count 0 2006.176.08:06:12.73#ibcon#about to read 3, iclass 29, count 0 2006.176.08:06:12.75#ibcon#read 3, iclass 29, count 0 2006.176.08:06:12.75#ibcon#about to read 4, iclass 29, count 0 2006.176.08:06:12.75#ibcon#read 4, iclass 29, count 0 2006.176.08:06:12.75#ibcon#about to read 5, iclass 29, count 0 2006.176.08:06:12.75#ibcon#read 5, iclass 29, count 0 2006.176.08:06:12.75#ibcon#about to read 6, iclass 29, count 0 2006.176.08:06:12.75#ibcon#read 6, iclass 29, count 0 2006.176.08:06:12.75#ibcon#end of sib2, iclass 29, count 0 2006.176.08:06:12.75#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:06:12.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:06:12.75#ibcon#[27=USB\r\n] 2006.176.08:06:12.75#ibcon#*before write, iclass 29, count 0 2006.176.08:06:12.75#ibcon#enter sib2, iclass 29, count 0 2006.176.08:06:12.75#ibcon#flushed, iclass 29, count 0 2006.176.08:06:12.75#ibcon#about to write, iclass 29, count 0 2006.176.08:06:12.75#ibcon#wrote, iclass 29, count 0 2006.176.08:06:12.75#ibcon#about to read 3, iclass 29, count 0 2006.176.08:06:12.78#ibcon#read 3, iclass 29, count 0 2006.176.08:06:12.78#ibcon#about to read 4, iclass 29, count 0 2006.176.08:06:12.78#ibcon#read 4, iclass 29, count 0 2006.176.08:06:12.78#ibcon#about to read 5, iclass 29, count 0 2006.176.08:06:12.78#ibcon#read 5, iclass 29, count 0 2006.176.08:06:12.78#ibcon#about to read 6, iclass 29, count 0 2006.176.08:06:12.78#ibcon#read 6, iclass 29, count 0 2006.176.08:06:12.78#ibcon#end of sib2, iclass 29, count 0 2006.176.08:06:12.78#ibcon#*after write, iclass 29, count 0 2006.176.08:06:12.78#ibcon#*before return 0, iclass 29, count 0 2006.176.08:06:12.78#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:12.78#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:06:12.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:06:12.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:06:12.78$vc4f8/vabw=wide 2006.176.08:06:12.78#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.08:06:12.78#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.08:06:12.78#ibcon#ireg 8 cls_cnt 0 2006.176.08:06:12.78#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:12.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:12.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:12.78#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:06:12.78#ibcon#first serial, iclass 31, count 0 2006.176.08:06:12.78#ibcon#enter sib2, iclass 31, count 0 2006.176.08:06:12.78#ibcon#flushed, iclass 31, count 0 2006.176.08:06:12.78#ibcon#about to write, iclass 31, count 0 2006.176.08:06:12.78#ibcon#wrote, iclass 31, count 0 2006.176.08:06:12.78#ibcon#about to read 3, iclass 31, count 0 2006.176.08:06:12.80#ibcon#read 3, iclass 31, count 0 2006.176.08:06:12.80#ibcon#about to read 4, iclass 31, count 0 2006.176.08:06:12.80#ibcon#read 4, iclass 31, count 0 2006.176.08:06:12.80#ibcon#about to read 5, iclass 31, count 0 2006.176.08:06:12.80#ibcon#read 5, iclass 31, count 0 2006.176.08:06:12.80#ibcon#about to read 6, iclass 31, count 0 2006.176.08:06:12.80#ibcon#read 6, iclass 31, count 0 2006.176.08:06:12.80#ibcon#end of sib2, iclass 31, count 0 2006.176.08:06:12.80#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:06:12.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:06:12.80#ibcon#[25=BW32\r\n] 2006.176.08:06:12.80#ibcon#*before write, iclass 31, count 0 2006.176.08:06:12.80#ibcon#enter sib2, iclass 31, count 0 2006.176.08:06:12.80#ibcon#flushed, iclass 31, count 0 2006.176.08:06:12.80#ibcon#about to write, iclass 31, count 0 2006.176.08:06:12.80#ibcon#wrote, iclass 31, count 0 2006.176.08:06:12.80#ibcon#about to read 3, iclass 31, count 0 2006.176.08:06:12.83#ibcon#read 3, iclass 31, count 0 2006.176.08:06:12.83#ibcon#about to read 4, iclass 31, count 0 2006.176.08:06:12.83#ibcon#read 4, iclass 31, count 0 2006.176.08:06:12.83#ibcon#about to read 5, iclass 31, count 0 2006.176.08:06:12.83#ibcon#read 5, iclass 31, count 0 2006.176.08:06:12.83#ibcon#about to read 6, iclass 31, count 0 2006.176.08:06:12.83#ibcon#read 6, iclass 31, count 0 2006.176.08:06:12.83#ibcon#end of sib2, iclass 31, count 0 2006.176.08:06:12.83#ibcon#*after write, iclass 31, count 0 2006.176.08:06:12.83#ibcon#*before return 0, iclass 31, count 0 2006.176.08:06:12.83#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:12.83#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:06:12.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:06:12.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:06:12.83$vc4f8/vbbw=wide 2006.176.08:06:12.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.08:06:12.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.08:06:12.83#ibcon#ireg 8 cls_cnt 0 2006.176.08:06:12.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:06:12.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:06:12.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:06:12.90#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:06:12.90#ibcon#first serial, iclass 33, count 0 2006.176.08:06:12.90#ibcon#enter sib2, iclass 33, count 0 2006.176.08:06:12.90#ibcon#flushed, iclass 33, count 0 2006.176.08:06:12.90#ibcon#about to write, iclass 33, count 0 2006.176.08:06:12.90#ibcon#wrote, iclass 33, count 0 2006.176.08:06:12.90#ibcon#about to read 3, iclass 33, count 0 2006.176.08:06:12.92#ibcon#read 3, iclass 33, count 0 2006.176.08:06:12.92#ibcon#about to read 4, iclass 33, count 0 2006.176.08:06:12.92#ibcon#read 4, iclass 33, count 0 2006.176.08:06:12.92#ibcon#about to read 5, iclass 33, count 0 2006.176.08:06:12.92#ibcon#read 5, iclass 33, count 0 2006.176.08:06:12.92#ibcon#about to read 6, iclass 33, count 0 2006.176.08:06:12.92#ibcon#read 6, iclass 33, count 0 2006.176.08:06:12.92#ibcon#end of sib2, iclass 33, count 0 2006.176.08:06:12.92#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:06:12.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:06:12.92#ibcon#[27=BW32\r\n] 2006.176.08:06:12.92#ibcon#*before write, iclass 33, count 0 2006.176.08:06:12.92#ibcon#enter sib2, iclass 33, count 0 2006.176.08:06:12.92#ibcon#flushed, iclass 33, count 0 2006.176.08:06:12.92#ibcon#about to write, iclass 33, count 0 2006.176.08:06:12.92#ibcon#wrote, iclass 33, count 0 2006.176.08:06:12.92#ibcon#about to read 3, iclass 33, count 0 2006.176.08:06:12.95#ibcon#read 3, iclass 33, count 0 2006.176.08:06:12.95#ibcon#about to read 4, iclass 33, count 0 2006.176.08:06:12.95#ibcon#read 4, iclass 33, count 0 2006.176.08:06:12.95#ibcon#about to read 5, iclass 33, count 0 2006.176.08:06:12.95#ibcon#read 5, iclass 33, count 0 2006.176.08:06:12.95#ibcon#about to read 6, iclass 33, count 0 2006.176.08:06:12.95#ibcon#read 6, iclass 33, count 0 2006.176.08:06:12.95#ibcon#end of sib2, iclass 33, count 0 2006.176.08:06:12.95#ibcon#*after write, iclass 33, count 0 2006.176.08:06:12.95#ibcon#*before return 0, iclass 33, count 0 2006.176.08:06:12.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:06:12.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:06:12.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:06:12.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:06:12.95$4f8m12a/ifd4f 2006.176.08:06:12.95$ifd4f/lo= 2006.176.08:06:12.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:06:12.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:06:12.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:06:12.95$ifd4f/patch= 2006.176.08:06:12.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:06:12.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:06:12.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:06:12.95$4f8m12a/"form=m,16.000,1:2 2006.176.08:06:12.95$4f8m12a/"tpicd 2006.176.08:06:12.95$4f8m12a/echo=off 2006.176.08:06:12.95$4f8m12a/xlog=off 2006.176.08:06:12.95:!2006.176.08:06:40 2006.176.08:06:22.13#trakl#Source acquired 2006.176.08:06:22.13#flagr#flagr/antenna,acquired 2006.176.08:06:40.00:preob 2006.176.08:06:41.13/onsource/TRACKING 2006.176.08:06:41.13:!2006.176.08:06:50 2006.176.08:06:50.00:data_valid=on 2006.176.08:06:50.00:midob 2006.176.08:06:50.13/onsource/TRACKING 2006.176.08:06:50.13/wx/23.86,1008.6,91 2006.176.08:06:50.32/cable/+6.4949E-03 2006.176.08:06:51.41/va/01,08,usb,yes,28,30 2006.176.08:06:51.41/va/02,07,usb,yes,28,30 2006.176.08:06:51.41/va/03,06,usb,yes,30,30 2006.176.08:06:51.41/va/04,07,usb,yes,29,31 2006.176.08:06:51.41/va/05,07,usb,yes,31,32 2006.176.08:06:51.41/va/06,06,usb,yes,30,29 2006.176.08:06:51.41/va/07,06,usb,yes,30,30 2006.176.08:06:51.41/va/08,06,usb,yes,32,32 2006.176.08:06:51.64/valo/01,532.99,yes,locked 2006.176.08:06:51.64/valo/02,572.99,yes,locked 2006.176.08:06:51.64/valo/03,672.99,yes,locked 2006.176.08:06:51.64/valo/04,832.99,yes,locked 2006.176.08:06:51.64/valo/05,652.99,yes,locked 2006.176.08:06:51.64/valo/06,772.99,yes,locked 2006.176.08:06:51.64/valo/07,832.99,yes,locked 2006.176.08:06:51.64/valo/08,852.99,yes,locked 2006.176.08:06:52.73/vb/01,04,usb,yes,29,27 2006.176.08:06:52.73/vb/02,04,usb,yes,31,32 2006.176.08:06:52.73/vb/03,04,usb,yes,27,31 2006.176.08:06:52.73/vb/04,04,usb,yes,28,28 2006.176.08:06:52.73/vb/05,04,usb,yes,26,30 2006.176.08:06:52.73/vb/06,04,usb,yes,27,30 2006.176.08:06:52.73/vb/07,04,usb,yes,29,29 2006.176.08:06:52.73/vb/08,04,usb,yes,27,30 2006.176.08:06:52.97/vblo/01,632.99,yes,locked 2006.176.08:06:52.97/vblo/02,640.99,yes,locked 2006.176.08:06:52.97/vblo/03,656.99,yes,locked 2006.176.08:06:52.97/vblo/04,712.99,yes,locked 2006.176.08:06:52.97/vblo/05,744.99,yes,locked 2006.176.08:06:52.97/vblo/06,752.99,yes,locked 2006.176.08:06:52.97/vblo/07,734.99,yes,locked 2006.176.08:06:52.97/vblo/08,744.99,yes,locked 2006.176.08:06:53.12/vabw/8 2006.176.08:06:53.27/vbbw/8 2006.176.08:06:53.36/xfe/off,on,15.2 2006.176.08:06:53.73/ifatt/23,28,28,28 2006.176.08:06:54.07/fmout-gps/S +3.71E-07 2006.176.08:06:54.11:!2006.176.08:07:50 2006.176.08:07:50.01:data_valid=off 2006.176.08:07:50.02:postob 2006.176.08:07:50.12/cable/+6.4944E-03 2006.176.08:07:50.13/wx/23.86,1008.6,91 2006.176.08:07:51.07/fmout-gps/S +3.71E-07 2006.176.08:07:51.07:scan_name=176-0808,k06176,60 2006.176.08:07:51.08:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.176.08:07:51.13#flagr#flagr/antenna,new-source 2006.176.08:07:52.14:checkk5 2006.176.08:07:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:07:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:07:53.55/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:07:54.08/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:07:54.45/chk_obsdata//k5ts1/T1760806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:07:54.81/chk_obsdata//k5ts2/T1760806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:07:55.18/chk_obsdata//k5ts3/T1760806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:07:55.55/chk_obsdata//k5ts4/T1760806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:07:56.24/k5log//k5ts1_log_newline 2006.176.08:07:56.93/k5log//k5ts2_log_newline 2006.176.08:07:57.62/k5log//k5ts3_log_newline 2006.176.08:07:58.31/k5log//k5ts4_log_newline 2006.176.08:07:58.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:07:58.34:4f8m12a=2 2006.176.08:07:58.34$4f8m12a/echo=on 2006.176.08:07:58.34$4f8m12a/pcalon 2006.176.08:07:58.34$pcalon/"no phase cal control is implemented here 2006.176.08:07:58.34$4f8m12a/"tpicd=stop 2006.176.08:07:58.34$4f8m12a/vc4f8 2006.176.08:07:58.34$vc4f8/valo=1,532.99 2006.176.08:07:58.34#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.08:07:58.34#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.08:07:58.34#ibcon#ireg 17 cls_cnt 0 2006.176.08:07:58.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:07:58.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:07:58.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:07:58.34#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:07:58.34#ibcon#first serial, iclass 40, count 0 2006.176.08:07:58.34#ibcon#enter sib2, iclass 40, count 0 2006.176.08:07:58.34#ibcon#flushed, iclass 40, count 0 2006.176.08:07:58.34#ibcon#about to write, iclass 40, count 0 2006.176.08:07:58.34#ibcon#wrote, iclass 40, count 0 2006.176.08:07:58.34#ibcon#about to read 3, iclass 40, count 0 2006.176.08:07:58.38#ibcon#read 3, iclass 40, count 0 2006.176.08:07:58.38#ibcon#about to read 4, iclass 40, count 0 2006.176.08:07:58.38#ibcon#read 4, iclass 40, count 0 2006.176.08:07:58.38#ibcon#about to read 5, iclass 40, count 0 2006.176.08:07:58.38#ibcon#read 5, iclass 40, count 0 2006.176.08:07:58.38#ibcon#about to read 6, iclass 40, count 0 2006.176.08:07:58.38#ibcon#read 6, iclass 40, count 0 2006.176.08:07:58.38#ibcon#end of sib2, iclass 40, count 0 2006.176.08:07:58.38#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:07:58.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:07:58.38#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:07:58.38#ibcon#*before write, iclass 40, count 0 2006.176.08:07:58.38#ibcon#enter sib2, iclass 40, count 0 2006.176.08:07:58.38#ibcon#flushed, iclass 40, count 0 2006.176.08:07:58.38#ibcon#about to write, iclass 40, count 0 2006.176.08:07:58.38#ibcon#wrote, iclass 40, count 0 2006.176.08:07:58.38#ibcon#about to read 3, iclass 40, count 0 2006.176.08:07:58.43#ibcon#read 3, iclass 40, count 0 2006.176.08:07:58.43#ibcon#about to read 4, iclass 40, count 0 2006.176.08:07:58.43#ibcon#read 4, iclass 40, count 0 2006.176.08:07:58.43#ibcon#about to read 5, iclass 40, count 0 2006.176.08:07:58.43#ibcon#read 5, iclass 40, count 0 2006.176.08:07:58.43#ibcon#about to read 6, iclass 40, count 0 2006.176.08:07:58.43#ibcon#read 6, iclass 40, count 0 2006.176.08:07:58.43#ibcon#end of sib2, iclass 40, count 0 2006.176.08:07:58.43#ibcon#*after write, iclass 40, count 0 2006.176.08:07:58.43#ibcon#*before return 0, iclass 40, count 0 2006.176.08:07:58.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:07:58.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:07:58.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:07:58.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:07:58.43$vc4f8/va=1,8 2006.176.08:07:58.43#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.08:07:58.43#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.08:07:58.43#ibcon#ireg 11 cls_cnt 2 2006.176.08:07:58.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:07:58.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:07:58.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:07:58.43#ibcon#enter wrdev, iclass 4, count 2 2006.176.08:07:58.43#ibcon#first serial, iclass 4, count 2 2006.176.08:07:58.43#ibcon#enter sib2, iclass 4, count 2 2006.176.08:07:58.43#ibcon#flushed, iclass 4, count 2 2006.176.08:07:58.43#ibcon#about to write, iclass 4, count 2 2006.176.08:07:58.43#ibcon#wrote, iclass 4, count 2 2006.176.08:07:58.43#ibcon#about to read 3, iclass 4, count 2 2006.176.08:07:58.45#ibcon#read 3, iclass 4, count 2 2006.176.08:07:58.45#ibcon#about to read 4, iclass 4, count 2 2006.176.08:07:58.45#ibcon#read 4, iclass 4, count 2 2006.176.08:07:58.45#ibcon#about to read 5, iclass 4, count 2 2006.176.08:07:58.45#ibcon#read 5, iclass 4, count 2 2006.176.08:07:58.45#ibcon#about to read 6, iclass 4, count 2 2006.176.08:07:58.45#ibcon#read 6, iclass 4, count 2 2006.176.08:07:58.45#ibcon#end of sib2, iclass 4, count 2 2006.176.08:07:58.45#ibcon#*mode == 0, iclass 4, count 2 2006.176.08:07:58.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.08:07:58.45#ibcon#[25=AT01-08\r\n] 2006.176.08:07:58.45#ibcon#*before write, iclass 4, count 2 2006.176.08:07:58.45#ibcon#enter sib2, iclass 4, count 2 2006.176.08:07:58.45#ibcon#flushed, iclass 4, count 2 2006.176.08:07:58.45#ibcon#about to write, iclass 4, count 2 2006.176.08:07:58.45#ibcon#wrote, iclass 4, count 2 2006.176.08:07:58.45#ibcon#about to read 3, iclass 4, count 2 2006.176.08:07:58.48#ibcon#read 3, iclass 4, count 2 2006.176.08:07:58.48#ibcon#about to read 4, iclass 4, count 2 2006.176.08:07:58.48#ibcon#read 4, iclass 4, count 2 2006.176.08:07:58.48#ibcon#about to read 5, iclass 4, count 2 2006.176.08:07:58.48#ibcon#read 5, iclass 4, count 2 2006.176.08:07:58.48#ibcon#about to read 6, iclass 4, count 2 2006.176.08:07:58.48#ibcon#read 6, iclass 4, count 2 2006.176.08:07:58.48#ibcon#end of sib2, iclass 4, count 2 2006.176.08:07:58.48#ibcon#*after write, iclass 4, count 2 2006.176.08:07:58.48#ibcon#*before return 0, iclass 4, count 2 2006.176.08:07:58.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:07:58.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:07:58.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.08:07:58.48#ibcon#ireg 7 cls_cnt 0 2006.176.08:07:58.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:07:58.60#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:07:58.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:07:58.60#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:07:58.60#ibcon#first serial, iclass 4, count 0 2006.176.08:07:58.60#ibcon#enter sib2, iclass 4, count 0 2006.176.08:07:58.60#ibcon#flushed, iclass 4, count 0 2006.176.08:07:58.60#ibcon#about to write, iclass 4, count 0 2006.176.08:07:58.60#ibcon#wrote, iclass 4, count 0 2006.176.08:07:58.60#ibcon#about to read 3, iclass 4, count 0 2006.176.08:07:58.62#ibcon#read 3, iclass 4, count 0 2006.176.08:07:58.62#ibcon#about to read 4, iclass 4, count 0 2006.176.08:07:58.62#ibcon#read 4, iclass 4, count 0 2006.176.08:07:58.62#ibcon#about to read 5, iclass 4, count 0 2006.176.08:07:58.62#ibcon#read 5, iclass 4, count 0 2006.176.08:07:58.62#ibcon#about to read 6, iclass 4, count 0 2006.176.08:07:58.62#ibcon#read 6, iclass 4, count 0 2006.176.08:07:58.62#ibcon#end of sib2, iclass 4, count 0 2006.176.08:07:58.62#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:07:58.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:07:58.62#ibcon#[25=USB\r\n] 2006.176.08:07:58.62#ibcon#*before write, iclass 4, count 0 2006.176.08:07:58.62#ibcon#enter sib2, iclass 4, count 0 2006.176.08:07:58.62#ibcon#flushed, iclass 4, count 0 2006.176.08:07:58.62#ibcon#about to write, iclass 4, count 0 2006.176.08:07:58.62#ibcon#wrote, iclass 4, count 0 2006.176.08:07:58.62#ibcon#about to read 3, iclass 4, count 0 2006.176.08:07:58.65#ibcon#read 3, iclass 4, count 0 2006.176.08:07:58.65#ibcon#about to read 4, iclass 4, count 0 2006.176.08:07:58.65#ibcon#read 4, iclass 4, count 0 2006.176.08:07:58.65#ibcon#about to read 5, iclass 4, count 0 2006.176.08:07:58.65#ibcon#read 5, iclass 4, count 0 2006.176.08:07:58.65#ibcon#about to read 6, iclass 4, count 0 2006.176.08:07:58.65#ibcon#read 6, iclass 4, count 0 2006.176.08:07:58.65#ibcon#end of sib2, iclass 4, count 0 2006.176.08:07:58.65#ibcon#*after write, iclass 4, count 0 2006.176.08:07:58.65#ibcon#*before return 0, iclass 4, count 0 2006.176.08:07:58.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:07:58.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:07:58.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:07:58.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:07:58.65$vc4f8/valo=2,572.99 2006.176.08:07:58.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.08:07:58.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.08:07:58.65#ibcon#ireg 17 cls_cnt 0 2006.176.08:07:58.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:07:58.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:07:58.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:07:58.65#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:07:58.65#ibcon#first serial, iclass 6, count 0 2006.176.08:07:58.65#ibcon#enter sib2, iclass 6, count 0 2006.176.08:07:58.65#ibcon#flushed, iclass 6, count 0 2006.176.08:07:58.65#ibcon#about to write, iclass 6, count 0 2006.176.08:07:58.65#ibcon#wrote, iclass 6, count 0 2006.176.08:07:58.65#ibcon#about to read 3, iclass 6, count 0 2006.176.08:07:58.67#ibcon#read 3, iclass 6, count 0 2006.176.08:07:58.67#ibcon#about to read 4, iclass 6, count 0 2006.176.08:07:58.67#ibcon#read 4, iclass 6, count 0 2006.176.08:07:58.67#ibcon#about to read 5, iclass 6, count 0 2006.176.08:07:58.67#ibcon#read 5, iclass 6, count 0 2006.176.08:07:58.67#ibcon#about to read 6, iclass 6, count 0 2006.176.08:07:58.67#ibcon#read 6, iclass 6, count 0 2006.176.08:07:58.67#ibcon#end of sib2, iclass 6, count 0 2006.176.08:07:58.67#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:07:58.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:07:58.67#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:07:58.67#ibcon#*before write, iclass 6, count 0 2006.176.08:07:58.67#ibcon#enter sib2, iclass 6, count 0 2006.176.08:07:58.67#ibcon#flushed, iclass 6, count 0 2006.176.08:07:58.67#ibcon#about to write, iclass 6, count 0 2006.176.08:07:58.67#ibcon#wrote, iclass 6, count 0 2006.176.08:07:58.67#ibcon#about to read 3, iclass 6, count 0 2006.176.08:07:58.71#ibcon#read 3, iclass 6, count 0 2006.176.08:07:58.71#ibcon#about to read 4, iclass 6, count 0 2006.176.08:07:58.71#ibcon#read 4, iclass 6, count 0 2006.176.08:07:58.71#ibcon#about to read 5, iclass 6, count 0 2006.176.08:07:58.71#ibcon#read 5, iclass 6, count 0 2006.176.08:07:58.71#ibcon#about to read 6, iclass 6, count 0 2006.176.08:07:58.71#ibcon#read 6, iclass 6, count 0 2006.176.08:07:58.71#ibcon#end of sib2, iclass 6, count 0 2006.176.08:07:58.71#ibcon#*after write, iclass 6, count 0 2006.176.08:07:58.71#ibcon#*before return 0, iclass 6, count 0 2006.176.08:07:58.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:07:58.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:07:58.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:07:58.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:07:58.71$vc4f8/va=2,7 2006.176.08:07:58.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.08:07:58.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.08:07:58.71#ibcon#ireg 11 cls_cnt 2 2006.176.08:07:58.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:07:58.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:07:58.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:07:58.77#ibcon#enter wrdev, iclass 10, count 2 2006.176.08:07:58.77#ibcon#first serial, iclass 10, count 2 2006.176.08:07:58.77#ibcon#enter sib2, iclass 10, count 2 2006.176.08:07:58.77#ibcon#flushed, iclass 10, count 2 2006.176.08:07:58.77#ibcon#about to write, iclass 10, count 2 2006.176.08:07:58.77#ibcon#wrote, iclass 10, count 2 2006.176.08:07:58.77#ibcon#about to read 3, iclass 10, count 2 2006.176.08:07:58.80#ibcon#read 3, iclass 10, count 2 2006.176.08:07:58.80#ibcon#about to read 4, iclass 10, count 2 2006.176.08:07:58.80#ibcon#read 4, iclass 10, count 2 2006.176.08:07:58.80#ibcon#about to read 5, iclass 10, count 2 2006.176.08:07:58.80#ibcon#read 5, iclass 10, count 2 2006.176.08:07:58.80#ibcon#about to read 6, iclass 10, count 2 2006.176.08:07:58.80#ibcon#read 6, iclass 10, count 2 2006.176.08:07:58.80#ibcon#end of sib2, iclass 10, count 2 2006.176.08:07:58.80#ibcon#*mode == 0, iclass 10, count 2 2006.176.08:07:58.80#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.08:07:58.80#ibcon#[25=AT02-07\r\n] 2006.176.08:07:58.80#ibcon#*before write, iclass 10, count 2 2006.176.08:07:58.80#ibcon#enter sib2, iclass 10, count 2 2006.176.08:07:58.80#ibcon#flushed, iclass 10, count 2 2006.176.08:07:58.80#ibcon#about to write, iclass 10, count 2 2006.176.08:07:58.80#ibcon#wrote, iclass 10, count 2 2006.176.08:07:58.80#ibcon#about to read 3, iclass 10, count 2 2006.176.08:07:58.82#ibcon#read 3, iclass 10, count 2 2006.176.08:07:58.82#ibcon#about to read 4, iclass 10, count 2 2006.176.08:07:58.82#ibcon#read 4, iclass 10, count 2 2006.176.08:07:58.82#ibcon#about to read 5, iclass 10, count 2 2006.176.08:07:58.82#ibcon#read 5, iclass 10, count 2 2006.176.08:07:58.82#ibcon#about to read 6, iclass 10, count 2 2006.176.08:07:58.82#ibcon#read 6, iclass 10, count 2 2006.176.08:07:58.82#ibcon#end of sib2, iclass 10, count 2 2006.176.08:07:58.82#ibcon#*after write, iclass 10, count 2 2006.176.08:07:58.82#ibcon#*before return 0, iclass 10, count 2 2006.176.08:07:58.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:07:58.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:07:58.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.08:07:58.82#ibcon#ireg 7 cls_cnt 0 2006.176.08:07:58.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:07:58.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:07:58.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:07:58.94#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:07:58.94#ibcon#first serial, iclass 10, count 0 2006.176.08:07:58.94#ibcon#enter sib2, iclass 10, count 0 2006.176.08:07:58.94#ibcon#flushed, iclass 10, count 0 2006.176.08:07:58.94#ibcon#about to write, iclass 10, count 0 2006.176.08:07:58.94#ibcon#wrote, iclass 10, count 0 2006.176.08:07:58.94#ibcon#about to read 3, iclass 10, count 0 2006.176.08:07:58.96#ibcon#read 3, iclass 10, count 0 2006.176.08:07:58.96#ibcon#about to read 4, iclass 10, count 0 2006.176.08:07:58.96#ibcon#read 4, iclass 10, count 0 2006.176.08:07:58.96#ibcon#about to read 5, iclass 10, count 0 2006.176.08:07:58.96#ibcon#read 5, iclass 10, count 0 2006.176.08:07:58.96#ibcon#about to read 6, iclass 10, count 0 2006.176.08:07:58.96#ibcon#read 6, iclass 10, count 0 2006.176.08:07:58.96#ibcon#end of sib2, iclass 10, count 0 2006.176.08:07:58.96#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:07:58.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:07:58.96#ibcon#[25=USB\r\n] 2006.176.08:07:58.96#ibcon#*before write, iclass 10, count 0 2006.176.08:07:58.96#ibcon#enter sib2, iclass 10, count 0 2006.176.08:07:58.96#ibcon#flushed, iclass 10, count 0 2006.176.08:07:58.96#ibcon#about to write, iclass 10, count 0 2006.176.08:07:58.96#ibcon#wrote, iclass 10, count 0 2006.176.08:07:58.96#ibcon#about to read 3, iclass 10, count 0 2006.176.08:07:58.99#ibcon#read 3, iclass 10, count 0 2006.176.08:07:58.99#ibcon#about to read 4, iclass 10, count 0 2006.176.08:07:58.99#ibcon#read 4, iclass 10, count 0 2006.176.08:07:58.99#ibcon#about to read 5, iclass 10, count 0 2006.176.08:07:58.99#ibcon#read 5, iclass 10, count 0 2006.176.08:07:58.99#ibcon#about to read 6, iclass 10, count 0 2006.176.08:07:58.99#ibcon#read 6, iclass 10, count 0 2006.176.08:07:58.99#ibcon#end of sib2, iclass 10, count 0 2006.176.08:07:58.99#ibcon#*after write, iclass 10, count 0 2006.176.08:07:58.99#ibcon#*before return 0, iclass 10, count 0 2006.176.08:07:58.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:07:58.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:07:58.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:07:58.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:07:58.99$vc4f8/valo=3,672.99 2006.176.08:07:58.99#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.08:07:58.99#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.08:07:58.99#ibcon#ireg 17 cls_cnt 0 2006.176.08:07:58.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:07:58.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:07:58.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:07:58.99#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:07:58.99#ibcon#first serial, iclass 12, count 0 2006.176.08:07:58.99#ibcon#enter sib2, iclass 12, count 0 2006.176.08:07:58.99#ibcon#flushed, iclass 12, count 0 2006.176.08:07:58.99#ibcon#about to write, iclass 12, count 0 2006.176.08:07:58.99#ibcon#wrote, iclass 12, count 0 2006.176.08:07:58.99#ibcon#about to read 3, iclass 12, count 0 2006.176.08:07:59.01#ibcon#read 3, iclass 12, count 0 2006.176.08:07:59.01#ibcon#about to read 4, iclass 12, count 0 2006.176.08:07:59.01#ibcon#read 4, iclass 12, count 0 2006.176.08:07:59.01#ibcon#about to read 5, iclass 12, count 0 2006.176.08:07:59.01#ibcon#read 5, iclass 12, count 0 2006.176.08:07:59.01#ibcon#about to read 6, iclass 12, count 0 2006.176.08:07:59.01#ibcon#read 6, iclass 12, count 0 2006.176.08:07:59.01#ibcon#end of sib2, iclass 12, count 0 2006.176.08:07:59.01#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:07:59.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:07:59.01#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:07:59.01#ibcon#*before write, iclass 12, count 0 2006.176.08:07:59.01#ibcon#enter sib2, iclass 12, count 0 2006.176.08:07:59.01#ibcon#flushed, iclass 12, count 0 2006.176.08:07:59.01#ibcon#about to write, iclass 12, count 0 2006.176.08:07:59.01#ibcon#wrote, iclass 12, count 0 2006.176.08:07:59.01#ibcon#about to read 3, iclass 12, count 0 2006.176.08:07:59.05#ibcon#read 3, iclass 12, count 0 2006.176.08:07:59.05#ibcon#about to read 4, iclass 12, count 0 2006.176.08:07:59.05#ibcon#read 4, iclass 12, count 0 2006.176.08:07:59.05#ibcon#about to read 5, iclass 12, count 0 2006.176.08:07:59.05#ibcon#read 5, iclass 12, count 0 2006.176.08:07:59.05#ibcon#about to read 6, iclass 12, count 0 2006.176.08:07:59.05#ibcon#read 6, iclass 12, count 0 2006.176.08:07:59.05#ibcon#end of sib2, iclass 12, count 0 2006.176.08:07:59.05#ibcon#*after write, iclass 12, count 0 2006.176.08:07:59.05#ibcon#*before return 0, iclass 12, count 0 2006.176.08:07:59.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:07:59.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:07:59.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:07:59.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:07:59.05$vc4f8/va=3,6 2006.176.08:07:59.05#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.08:07:59.05#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.08:07:59.05#ibcon#ireg 11 cls_cnt 2 2006.176.08:07:59.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:07:59.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:07:59.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:07:59.11#ibcon#enter wrdev, iclass 14, count 2 2006.176.08:07:59.11#ibcon#first serial, iclass 14, count 2 2006.176.08:07:59.11#ibcon#enter sib2, iclass 14, count 2 2006.176.08:07:59.11#ibcon#flushed, iclass 14, count 2 2006.176.08:07:59.11#ibcon#about to write, iclass 14, count 2 2006.176.08:07:59.11#ibcon#wrote, iclass 14, count 2 2006.176.08:07:59.11#ibcon#about to read 3, iclass 14, count 2 2006.176.08:07:59.14#ibcon#read 3, iclass 14, count 2 2006.176.08:07:59.14#ibcon#about to read 4, iclass 14, count 2 2006.176.08:07:59.14#ibcon#read 4, iclass 14, count 2 2006.176.08:07:59.14#ibcon#about to read 5, iclass 14, count 2 2006.176.08:07:59.14#ibcon#read 5, iclass 14, count 2 2006.176.08:07:59.14#ibcon#about to read 6, iclass 14, count 2 2006.176.08:07:59.14#ibcon#read 6, iclass 14, count 2 2006.176.08:07:59.14#ibcon#end of sib2, iclass 14, count 2 2006.176.08:07:59.14#ibcon#*mode == 0, iclass 14, count 2 2006.176.08:07:59.14#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.08:07:59.14#ibcon#[25=AT03-06\r\n] 2006.176.08:07:59.14#ibcon#*before write, iclass 14, count 2 2006.176.08:07:59.14#ibcon#enter sib2, iclass 14, count 2 2006.176.08:07:59.14#ibcon#flushed, iclass 14, count 2 2006.176.08:07:59.14#ibcon#about to write, iclass 14, count 2 2006.176.08:07:59.14#ibcon#wrote, iclass 14, count 2 2006.176.08:07:59.14#ibcon#about to read 3, iclass 14, count 2 2006.176.08:07:59.17#ibcon#read 3, iclass 14, count 2 2006.176.08:07:59.17#ibcon#about to read 4, iclass 14, count 2 2006.176.08:07:59.17#ibcon#read 4, iclass 14, count 2 2006.176.08:07:59.17#ibcon#about to read 5, iclass 14, count 2 2006.176.08:07:59.17#ibcon#read 5, iclass 14, count 2 2006.176.08:07:59.17#ibcon#about to read 6, iclass 14, count 2 2006.176.08:07:59.17#ibcon#read 6, iclass 14, count 2 2006.176.08:07:59.17#ibcon#end of sib2, iclass 14, count 2 2006.176.08:07:59.17#ibcon#*after write, iclass 14, count 2 2006.176.08:07:59.17#ibcon#*before return 0, iclass 14, count 2 2006.176.08:07:59.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:07:59.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:07:59.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.08:07:59.17#ibcon#ireg 7 cls_cnt 0 2006.176.08:07:59.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:07:59.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:07:59.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:07:59.29#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:07:59.29#ibcon#first serial, iclass 14, count 0 2006.176.08:07:59.29#ibcon#enter sib2, iclass 14, count 0 2006.176.08:07:59.29#ibcon#flushed, iclass 14, count 0 2006.176.08:07:59.29#ibcon#about to write, iclass 14, count 0 2006.176.08:07:59.29#ibcon#wrote, iclass 14, count 0 2006.176.08:07:59.29#ibcon#about to read 3, iclass 14, count 0 2006.176.08:07:59.31#ibcon#read 3, iclass 14, count 0 2006.176.08:07:59.31#ibcon#about to read 4, iclass 14, count 0 2006.176.08:07:59.31#ibcon#read 4, iclass 14, count 0 2006.176.08:07:59.31#ibcon#about to read 5, iclass 14, count 0 2006.176.08:07:59.31#ibcon#read 5, iclass 14, count 0 2006.176.08:07:59.31#ibcon#about to read 6, iclass 14, count 0 2006.176.08:07:59.31#ibcon#read 6, iclass 14, count 0 2006.176.08:07:59.31#ibcon#end of sib2, iclass 14, count 0 2006.176.08:07:59.31#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:07:59.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:07:59.31#ibcon#[25=USB\r\n] 2006.176.08:07:59.31#ibcon#*before write, iclass 14, count 0 2006.176.08:07:59.31#ibcon#enter sib2, iclass 14, count 0 2006.176.08:07:59.31#ibcon#flushed, iclass 14, count 0 2006.176.08:07:59.31#ibcon#about to write, iclass 14, count 0 2006.176.08:07:59.31#ibcon#wrote, iclass 14, count 0 2006.176.08:07:59.31#ibcon#about to read 3, iclass 14, count 0 2006.176.08:07:59.34#ibcon#read 3, iclass 14, count 0 2006.176.08:07:59.34#ibcon#about to read 4, iclass 14, count 0 2006.176.08:07:59.34#ibcon#read 4, iclass 14, count 0 2006.176.08:07:59.34#ibcon#about to read 5, iclass 14, count 0 2006.176.08:07:59.34#ibcon#read 5, iclass 14, count 0 2006.176.08:07:59.34#ibcon#about to read 6, iclass 14, count 0 2006.176.08:07:59.34#ibcon#read 6, iclass 14, count 0 2006.176.08:07:59.34#ibcon#end of sib2, iclass 14, count 0 2006.176.08:07:59.34#ibcon#*after write, iclass 14, count 0 2006.176.08:07:59.34#ibcon#*before return 0, iclass 14, count 0 2006.176.08:07:59.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:07:59.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:07:59.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:07:59.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:07:59.34$vc4f8/valo=4,832.99 2006.176.08:07:59.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.08:07:59.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.08:07:59.34#ibcon#ireg 17 cls_cnt 0 2006.176.08:07:59.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:07:59.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:07:59.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:07:59.34#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:07:59.34#ibcon#first serial, iclass 16, count 0 2006.176.08:07:59.34#ibcon#enter sib2, iclass 16, count 0 2006.176.08:07:59.34#ibcon#flushed, iclass 16, count 0 2006.176.08:07:59.34#ibcon#about to write, iclass 16, count 0 2006.176.08:07:59.34#ibcon#wrote, iclass 16, count 0 2006.176.08:07:59.34#ibcon#about to read 3, iclass 16, count 0 2006.176.08:07:59.36#ibcon#read 3, iclass 16, count 0 2006.176.08:07:59.36#ibcon#about to read 4, iclass 16, count 0 2006.176.08:07:59.36#ibcon#read 4, iclass 16, count 0 2006.176.08:07:59.36#ibcon#about to read 5, iclass 16, count 0 2006.176.08:07:59.36#ibcon#read 5, iclass 16, count 0 2006.176.08:07:59.36#ibcon#about to read 6, iclass 16, count 0 2006.176.08:07:59.36#ibcon#read 6, iclass 16, count 0 2006.176.08:07:59.36#ibcon#end of sib2, iclass 16, count 0 2006.176.08:07:59.36#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:07:59.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:07:59.36#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:07:59.36#ibcon#*before write, iclass 16, count 0 2006.176.08:07:59.36#ibcon#enter sib2, iclass 16, count 0 2006.176.08:07:59.36#ibcon#flushed, iclass 16, count 0 2006.176.08:07:59.36#ibcon#about to write, iclass 16, count 0 2006.176.08:07:59.36#ibcon#wrote, iclass 16, count 0 2006.176.08:07:59.36#ibcon#about to read 3, iclass 16, count 0 2006.176.08:07:59.40#ibcon#read 3, iclass 16, count 0 2006.176.08:07:59.40#ibcon#about to read 4, iclass 16, count 0 2006.176.08:07:59.40#ibcon#read 4, iclass 16, count 0 2006.176.08:07:59.40#ibcon#about to read 5, iclass 16, count 0 2006.176.08:07:59.40#ibcon#read 5, iclass 16, count 0 2006.176.08:07:59.40#ibcon#about to read 6, iclass 16, count 0 2006.176.08:07:59.40#ibcon#read 6, iclass 16, count 0 2006.176.08:07:59.40#ibcon#end of sib2, iclass 16, count 0 2006.176.08:07:59.40#ibcon#*after write, iclass 16, count 0 2006.176.08:07:59.40#ibcon#*before return 0, iclass 16, count 0 2006.176.08:07:59.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:07:59.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:07:59.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:07:59.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:07:59.40$vc4f8/va=4,7 2006.176.08:07:59.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.08:07:59.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.08:07:59.40#ibcon#ireg 11 cls_cnt 2 2006.176.08:07:59.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:07:59.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:07:59.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:07:59.46#ibcon#enter wrdev, iclass 18, count 2 2006.176.08:07:59.46#ibcon#first serial, iclass 18, count 2 2006.176.08:07:59.46#ibcon#enter sib2, iclass 18, count 2 2006.176.08:07:59.46#ibcon#flushed, iclass 18, count 2 2006.176.08:07:59.46#ibcon#about to write, iclass 18, count 2 2006.176.08:07:59.46#ibcon#wrote, iclass 18, count 2 2006.176.08:07:59.46#ibcon#about to read 3, iclass 18, count 2 2006.176.08:07:59.48#ibcon#read 3, iclass 18, count 2 2006.176.08:07:59.48#ibcon#about to read 4, iclass 18, count 2 2006.176.08:07:59.48#ibcon#read 4, iclass 18, count 2 2006.176.08:07:59.48#ibcon#about to read 5, iclass 18, count 2 2006.176.08:07:59.48#ibcon#read 5, iclass 18, count 2 2006.176.08:07:59.48#ibcon#about to read 6, iclass 18, count 2 2006.176.08:07:59.48#ibcon#read 6, iclass 18, count 2 2006.176.08:07:59.48#ibcon#end of sib2, iclass 18, count 2 2006.176.08:07:59.48#ibcon#*mode == 0, iclass 18, count 2 2006.176.08:07:59.48#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.08:07:59.48#ibcon#[25=AT04-07\r\n] 2006.176.08:07:59.48#ibcon#*before write, iclass 18, count 2 2006.176.08:07:59.48#ibcon#enter sib2, iclass 18, count 2 2006.176.08:07:59.48#ibcon#flushed, iclass 18, count 2 2006.176.08:07:59.48#ibcon#about to write, iclass 18, count 2 2006.176.08:07:59.48#ibcon#wrote, iclass 18, count 2 2006.176.08:07:59.48#ibcon#about to read 3, iclass 18, count 2 2006.176.08:07:59.51#ibcon#read 3, iclass 18, count 2 2006.176.08:07:59.51#ibcon#about to read 4, iclass 18, count 2 2006.176.08:07:59.51#ibcon#read 4, iclass 18, count 2 2006.176.08:07:59.51#ibcon#about to read 5, iclass 18, count 2 2006.176.08:07:59.51#ibcon#read 5, iclass 18, count 2 2006.176.08:07:59.51#ibcon#about to read 6, iclass 18, count 2 2006.176.08:07:59.51#ibcon#read 6, iclass 18, count 2 2006.176.08:07:59.51#ibcon#end of sib2, iclass 18, count 2 2006.176.08:07:59.51#ibcon#*after write, iclass 18, count 2 2006.176.08:07:59.51#ibcon#*before return 0, iclass 18, count 2 2006.176.08:07:59.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:07:59.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:07:59.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.08:07:59.51#ibcon#ireg 7 cls_cnt 0 2006.176.08:07:59.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:07:59.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:07:59.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:07:59.63#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:07:59.63#ibcon#first serial, iclass 18, count 0 2006.176.08:07:59.63#ibcon#enter sib2, iclass 18, count 0 2006.176.08:07:59.63#ibcon#flushed, iclass 18, count 0 2006.176.08:07:59.63#ibcon#about to write, iclass 18, count 0 2006.176.08:07:59.63#ibcon#wrote, iclass 18, count 0 2006.176.08:07:59.63#ibcon#about to read 3, iclass 18, count 0 2006.176.08:07:59.65#ibcon#read 3, iclass 18, count 0 2006.176.08:07:59.65#ibcon#about to read 4, iclass 18, count 0 2006.176.08:07:59.65#ibcon#read 4, iclass 18, count 0 2006.176.08:07:59.65#ibcon#about to read 5, iclass 18, count 0 2006.176.08:07:59.65#ibcon#read 5, iclass 18, count 0 2006.176.08:07:59.65#ibcon#about to read 6, iclass 18, count 0 2006.176.08:07:59.65#ibcon#read 6, iclass 18, count 0 2006.176.08:07:59.65#ibcon#end of sib2, iclass 18, count 0 2006.176.08:07:59.65#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:07:59.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:07:59.65#ibcon#[25=USB\r\n] 2006.176.08:07:59.65#ibcon#*before write, iclass 18, count 0 2006.176.08:07:59.65#ibcon#enter sib2, iclass 18, count 0 2006.176.08:07:59.65#ibcon#flushed, iclass 18, count 0 2006.176.08:07:59.65#ibcon#about to write, iclass 18, count 0 2006.176.08:07:59.65#ibcon#wrote, iclass 18, count 0 2006.176.08:07:59.65#ibcon#about to read 3, iclass 18, count 0 2006.176.08:07:59.68#ibcon#read 3, iclass 18, count 0 2006.176.08:07:59.68#ibcon#about to read 4, iclass 18, count 0 2006.176.08:07:59.68#ibcon#read 4, iclass 18, count 0 2006.176.08:07:59.68#ibcon#about to read 5, iclass 18, count 0 2006.176.08:07:59.68#ibcon#read 5, iclass 18, count 0 2006.176.08:07:59.68#ibcon#about to read 6, iclass 18, count 0 2006.176.08:07:59.68#ibcon#read 6, iclass 18, count 0 2006.176.08:07:59.68#ibcon#end of sib2, iclass 18, count 0 2006.176.08:07:59.68#ibcon#*after write, iclass 18, count 0 2006.176.08:07:59.68#ibcon#*before return 0, iclass 18, count 0 2006.176.08:07:59.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:07:59.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:07:59.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:07:59.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:07:59.68$vc4f8/valo=5,652.99 2006.176.08:07:59.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.08:07:59.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.08:07:59.68#ibcon#ireg 17 cls_cnt 0 2006.176.08:07:59.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:07:59.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:07:59.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:07:59.68#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:07:59.68#ibcon#first serial, iclass 20, count 0 2006.176.08:07:59.68#ibcon#enter sib2, iclass 20, count 0 2006.176.08:07:59.68#ibcon#flushed, iclass 20, count 0 2006.176.08:07:59.68#ibcon#about to write, iclass 20, count 0 2006.176.08:07:59.68#ibcon#wrote, iclass 20, count 0 2006.176.08:07:59.68#ibcon#about to read 3, iclass 20, count 0 2006.176.08:07:59.70#ibcon#read 3, iclass 20, count 0 2006.176.08:07:59.70#ibcon#about to read 4, iclass 20, count 0 2006.176.08:07:59.70#ibcon#read 4, iclass 20, count 0 2006.176.08:07:59.70#ibcon#about to read 5, iclass 20, count 0 2006.176.08:07:59.70#ibcon#read 5, iclass 20, count 0 2006.176.08:07:59.70#ibcon#about to read 6, iclass 20, count 0 2006.176.08:07:59.70#ibcon#read 6, iclass 20, count 0 2006.176.08:07:59.70#ibcon#end of sib2, iclass 20, count 0 2006.176.08:07:59.70#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:07:59.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:07:59.70#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:07:59.70#ibcon#*before write, iclass 20, count 0 2006.176.08:07:59.70#ibcon#enter sib2, iclass 20, count 0 2006.176.08:07:59.70#ibcon#flushed, iclass 20, count 0 2006.176.08:07:59.70#ibcon#about to write, iclass 20, count 0 2006.176.08:07:59.70#ibcon#wrote, iclass 20, count 0 2006.176.08:07:59.70#ibcon#about to read 3, iclass 20, count 0 2006.176.08:07:59.74#ibcon#read 3, iclass 20, count 0 2006.176.08:07:59.74#ibcon#about to read 4, iclass 20, count 0 2006.176.08:07:59.74#ibcon#read 4, iclass 20, count 0 2006.176.08:07:59.74#ibcon#about to read 5, iclass 20, count 0 2006.176.08:07:59.74#ibcon#read 5, iclass 20, count 0 2006.176.08:07:59.74#ibcon#about to read 6, iclass 20, count 0 2006.176.08:07:59.74#ibcon#read 6, iclass 20, count 0 2006.176.08:07:59.74#ibcon#end of sib2, iclass 20, count 0 2006.176.08:07:59.74#ibcon#*after write, iclass 20, count 0 2006.176.08:07:59.74#ibcon#*before return 0, iclass 20, count 0 2006.176.08:07:59.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:07:59.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:07:59.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:07:59.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:07:59.74$vc4f8/va=5,7 2006.176.08:07:59.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.08:07:59.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.08:07:59.74#ibcon#ireg 11 cls_cnt 2 2006.176.08:07:59.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:07:59.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:07:59.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:07:59.80#ibcon#enter wrdev, iclass 22, count 2 2006.176.08:07:59.80#ibcon#first serial, iclass 22, count 2 2006.176.08:07:59.80#ibcon#enter sib2, iclass 22, count 2 2006.176.08:07:59.80#ibcon#flushed, iclass 22, count 2 2006.176.08:07:59.80#ibcon#about to write, iclass 22, count 2 2006.176.08:07:59.80#ibcon#wrote, iclass 22, count 2 2006.176.08:07:59.80#ibcon#about to read 3, iclass 22, count 2 2006.176.08:07:59.82#ibcon#read 3, iclass 22, count 2 2006.176.08:07:59.82#ibcon#about to read 4, iclass 22, count 2 2006.176.08:07:59.82#ibcon#read 4, iclass 22, count 2 2006.176.08:07:59.82#ibcon#about to read 5, iclass 22, count 2 2006.176.08:07:59.82#ibcon#read 5, iclass 22, count 2 2006.176.08:07:59.82#ibcon#about to read 6, iclass 22, count 2 2006.176.08:07:59.82#ibcon#read 6, iclass 22, count 2 2006.176.08:07:59.82#ibcon#end of sib2, iclass 22, count 2 2006.176.08:07:59.82#ibcon#*mode == 0, iclass 22, count 2 2006.176.08:07:59.82#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.08:07:59.82#ibcon#[25=AT05-07\r\n] 2006.176.08:07:59.82#ibcon#*before write, iclass 22, count 2 2006.176.08:07:59.82#ibcon#enter sib2, iclass 22, count 2 2006.176.08:07:59.82#ibcon#flushed, iclass 22, count 2 2006.176.08:07:59.82#ibcon#about to write, iclass 22, count 2 2006.176.08:07:59.82#ibcon#wrote, iclass 22, count 2 2006.176.08:07:59.82#ibcon#about to read 3, iclass 22, count 2 2006.176.08:07:59.85#ibcon#read 3, iclass 22, count 2 2006.176.08:07:59.85#ibcon#about to read 4, iclass 22, count 2 2006.176.08:07:59.85#ibcon#read 4, iclass 22, count 2 2006.176.08:07:59.85#ibcon#about to read 5, iclass 22, count 2 2006.176.08:07:59.85#ibcon#read 5, iclass 22, count 2 2006.176.08:07:59.85#ibcon#about to read 6, iclass 22, count 2 2006.176.08:07:59.85#ibcon#read 6, iclass 22, count 2 2006.176.08:07:59.85#ibcon#end of sib2, iclass 22, count 2 2006.176.08:07:59.85#ibcon#*after write, iclass 22, count 2 2006.176.08:07:59.85#ibcon#*before return 0, iclass 22, count 2 2006.176.08:07:59.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:07:59.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:07:59.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.08:07:59.85#ibcon#ireg 7 cls_cnt 0 2006.176.08:07:59.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:07:59.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:07:59.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:07:59.97#ibcon#enter wrdev, iclass 22, count 0 2006.176.08:07:59.97#ibcon#first serial, iclass 22, count 0 2006.176.08:07:59.97#ibcon#enter sib2, iclass 22, count 0 2006.176.08:07:59.97#ibcon#flushed, iclass 22, count 0 2006.176.08:07:59.97#ibcon#about to write, iclass 22, count 0 2006.176.08:07:59.97#ibcon#wrote, iclass 22, count 0 2006.176.08:07:59.97#ibcon#about to read 3, iclass 22, count 0 2006.176.08:07:59.99#ibcon#read 3, iclass 22, count 0 2006.176.08:07:59.99#ibcon#about to read 4, iclass 22, count 0 2006.176.08:07:59.99#ibcon#read 4, iclass 22, count 0 2006.176.08:07:59.99#ibcon#about to read 5, iclass 22, count 0 2006.176.08:07:59.99#ibcon#read 5, iclass 22, count 0 2006.176.08:07:59.99#ibcon#about to read 6, iclass 22, count 0 2006.176.08:07:59.99#ibcon#read 6, iclass 22, count 0 2006.176.08:07:59.99#ibcon#end of sib2, iclass 22, count 0 2006.176.08:07:59.99#ibcon#*mode == 0, iclass 22, count 0 2006.176.08:07:59.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.08:07:59.99#ibcon#[25=USB\r\n] 2006.176.08:07:59.99#ibcon#*before write, iclass 22, count 0 2006.176.08:07:59.99#ibcon#enter sib2, iclass 22, count 0 2006.176.08:07:59.99#ibcon#flushed, iclass 22, count 0 2006.176.08:07:59.99#ibcon#about to write, iclass 22, count 0 2006.176.08:07:59.99#ibcon#wrote, iclass 22, count 0 2006.176.08:07:59.99#ibcon#about to read 3, iclass 22, count 0 2006.176.08:08:00.02#ibcon#read 3, iclass 22, count 0 2006.176.08:08:00.02#ibcon#about to read 4, iclass 22, count 0 2006.176.08:08:00.02#ibcon#read 4, iclass 22, count 0 2006.176.08:08:00.02#ibcon#about to read 5, iclass 22, count 0 2006.176.08:08:00.02#ibcon#read 5, iclass 22, count 0 2006.176.08:08:00.02#ibcon#about to read 6, iclass 22, count 0 2006.176.08:08:00.02#ibcon#read 6, iclass 22, count 0 2006.176.08:08:00.02#ibcon#end of sib2, iclass 22, count 0 2006.176.08:08:00.02#ibcon#*after write, iclass 22, count 0 2006.176.08:08:00.02#ibcon#*before return 0, iclass 22, count 0 2006.176.08:08:00.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:08:00.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:08:00.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.08:08:00.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.08:08:00.02$vc4f8/valo=6,772.99 2006.176.08:08:00.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.08:08:00.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.08:08:00.02#ibcon#ireg 17 cls_cnt 0 2006.176.08:08:00.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:00.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:00.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:00.02#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:08:00.02#ibcon#first serial, iclass 24, count 0 2006.176.08:08:00.02#ibcon#enter sib2, iclass 24, count 0 2006.176.08:08:00.02#ibcon#flushed, iclass 24, count 0 2006.176.08:08:00.02#ibcon#about to write, iclass 24, count 0 2006.176.08:08:00.02#ibcon#wrote, iclass 24, count 0 2006.176.08:08:00.02#ibcon#about to read 3, iclass 24, count 0 2006.176.08:08:00.04#ibcon#read 3, iclass 24, count 0 2006.176.08:08:00.04#ibcon#about to read 4, iclass 24, count 0 2006.176.08:08:00.04#ibcon#read 4, iclass 24, count 0 2006.176.08:08:00.04#ibcon#about to read 5, iclass 24, count 0 2006.176.08:08:00.04#ibcon#read 5, iclass 24, count 0 2006.176.08:08:00.04#ibcon#about to read 6, iclass 24, count 0 2006.176.08:08:00.04#ibcon#read 6, iclass 24, count 0 2006.176.08:08:00.04#ibcon#end of sib2, iclass 24, count 0 2006.176.08:08:00.04#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:08:00.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:08:00.04#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:08:00.04#ibcon#*before write, iclass 24, count 0 2006.176.08:08:00.04#ibcon#enter sib2, iclass 24, count 0 2006.176.08:08:00.04#ibcon#flushed, iclass 24, count 0 2006.176.08:08:00.04#ibcon#about to write, iclass 24, count 0 2006.176.08:08:00.04#ibcon#wrote, iclass 24, count 0 2006.176.08:08:00.04#ibcon#about to read 3, iclass 24, count 0 2006.176.08:08:00.08#ibcon#read 3, iclass 24, count 0 2006.176.08:08:00.08#ibcon#about to read 4, iclass 24, count 0 2006.176.08:08:00.08#ibcon#read 4, iclass 24, count 0 2006.176.08:08:00.08#ibcon#about to read 5, iclass 24, count 0 2006.176.08:08:00.08#ibcon#read 5, iclass 24, count 0 2006.176.08:08:00.08#ibcon#about to read 6, iclass 24, count 0 2006.176.08:08:00.08#ibcon#read 6, iclass 24, count 0 2006.176.08:08:00.08#ibcon#end of sib2, iclass 24, count 0 2006.176.08:08:00.08#ibcon#*after write, iclass 24, count 0 2006.176.08:08:00.08#ibcon#*before return 0, iclass 24, count 0 2006.176.08:08:00.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:00.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:00.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:08:00.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:08:00.08$vc4f8/va=6,6 2006.176.08:08:00.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.08:08:00.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.08:08:00.08#ibcon#ireg 11 cls_cnt 2 2006.176.08:08:00.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:00.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:00.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:00.14#ibcon#enter wrdev, iclass 26, count 2 2006.176.08:08:00.14#ibcon#first serial, iclass 26, count 2 2006.176.08:08:00.14#ibcon#enter sib2, iclass 26, count 2 2006.176.08:08:00.14#ibcon#flushed, iclass 26, count 2 2006.176.08:08:00.14#ibcon#about to write, iclass 26, count 2 2006.176.08:08:00.14#ibcon#wrote, iclass 26, count 2 2006.176.08:08:00.14#ibcon#about to read 3, iclass 26, count 2 2006.176.08:08:00.17#ibcon#read 3, iclass 26, count 2 2006.176.08:08:00.17#ibcon#about to read 4, iclass 26, count 2 2006.176.08:08:00.17#ibcon#read 4, iclass 26, count 2 2006.176.08:08:00.17#ibcon#about to read 5, iclass 26, count 2 2006.176.08:08:00.17#ibcon#read 5, iclass 26, count 2 2006.176.08:08:00.17#ibcon#about to read 6, iclass 26, count 2 2006.176.08:08:00.17#ibcon#read 6, iclass 26, count 2 2006.176.08:08:00.17#ibcon#end of sib2, iclass 26, count 2 2006.176.08:08:00.17#ibcon#*mode == 0, iclass 26, count 2 2006.176.08:08:00.17#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.08:08:00.17#ibcon#[25=AT06-06\r\n] 2006.176.08:08:00.17#ibcon#*before write, iclass 26, count 2 2006.176.08:08:00.17#ibcon#enter sib2, iclass 26, count 2 2006.176.08:08:00.17#ibcon#flushed, iclass 26, count 2 2006.176.08:08:00.17#ibcon#about to write, iclass 26, count 2 2006.176.08:08:00.17#ibcon#wrote, iclass 26, count 2 2006.176.08:08:00.17#ibcon#about to read 3, iclass 26, count 2 2006.176.08:08:00.20#ibcon#read 3, iclass 26, count 2 2006.176.08:08:00.20#ibcon#about to read 4, iclass 26, count 2 2006.176.08:08:00.20#ibcon#read 4, iclass 26, count 2 2006.176.08:08:00.20#ibcon#about to read 5, iclass 26, count 2 2006.176.08:08:00.20#ibcon#read 5, iclass 26, count 2 2006.176.08:08:00.20#ibcon#about to read 6, iclass 26, count 2 2006.176.08:08:00.20#ibcon#read 6, iclass 26, count 2 2006.176.08:08:00.20#ibcon#end of sib2, iclass 26, count 2 2006.176.08:08:00.20#ibcon#*after write, iclass 26, count 2 2006.176.08:08:00.20#ibcon#*before return 0, iclass 26, count 2 2006.176.08:08:00.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:00.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:00.20#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.08:08:00.20#ibcon#ireg 7 cls_cnt 0 2006.176.08:08:00.20#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:00.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:00.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:00.32#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:08:00.32#ibcon#first serial, iclass 26, count 0 2006.176.08:08:00.32#ibcon#enter sib2, iclass 26, count 0 2006.176.08:08:00.32#ibcon#flushed, iclass 26, count 0 2006.176.08:08:00.32#ibcon#about to write, iclass 26, count 0 2006.176.08:08:00.32#ibcon#wrote, iclass 26, count 0 2006.176.08:08:00.32#ibcon#about to read 3, iclass 26, count 0 2006.176.08:08:00.34#ibcon#read 3, iclass 26, count 0 2006.176.08:08:00.34#ibcon#about to read 4, iclass 26, count 0 2006.176.08:08:00.34#ibcon#read 4, iclass 26, count 0 2006.176.08:08:00.34#ibcon#about to read 5, iclass 26, count 0 2006.176.08:08:00.34#ibcon#read 5, iclass 26, count 0 2006.176.08:08:00.34#ibcon#about to read 6, iclass 26, count 0 2006.176.08:08:00.34#ibcon#read 6, iclass 26, count 0 2006.176.08:08:00.34#ibcon#end of sib2, iclass 26, count 0 2006.176.08:08:00.34#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:08:00.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:08:00.34#ibcon#[25=USB\r\n] 2006.176.08:08:00.34#ibcon#*before write, iclass 26, count 0 2006.176.08:08:00.34#ibcon#enter sib2, iclass 26, count 0 2006.176.08:08:00.34#ibcon#flushed, iclass 26, count 0 2006.176.08:08:00.34#ibcon#about to write, iclass 26, count 0 2006.176.08:08:00.34#ibcon#wrote, iclass 26, count 0 2006.176.08:08:00.34#ibcon#about to read 3, iclass 26, count 0 2006.176.08:08:00.37#ibcon#read 3, iclass 26, count 0 2006.176.08:08:00.37#ibcon#about to read 4, iclass 26, count 0 2006.176.08:08:00.37#ibcon#read 4, iclass 26, count 0 2006.176.08:08:00.37#ibcon#about to read 5, iclass 26, count 0 2006.176.08:08:00.37#ibcon#read 5, iclass 26, count 0 2006.176.08:08:00.37#ibcon#about to read 6, iclass 26, count 0 2006.176.08:08:00.37#ibcon#read 6, iclass 26, count 0 2006.176.08:08:00.37#ibcon#end of sib2, iclass 26, count 0 2006.176.08:08:00.37#ibcon#*after write, iclass 26, count 0 2006.176.08:08:00.37#ibcon#*before return 0, iclass 26, count 0 2006.176.08:08:00.37#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:00.37#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:00.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:08:00.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:08:00.37$vc4f8/valo=7,832.99 2006.176.08:08:00.37#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.08:08:00.37#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.08:08:00.37#ibcon#ireg 17 cls_cnt 0 2006.176.08:08:00.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:00.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:00.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:00.37#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:08:00.37#ibcon#first serial, iclass 28, count 0 2006.176.08:08:00.37#ibcon#enter sib2, iclass 28, count 0 2006.176.08:08:00.37#ibcon#flushed, iclass 28, count 0 2006.176.08:08:00.37#ibcon#about to write, iclass 28, count 0 2006.176.08:08:00.37#ibcon#wrote, iclass 28, count 0 2006.176.08:08:00.37#ibcon#about to read 3, iclass 28, count 0 2006.176.08:08:00.39#ibcon#read 3, iclass 28, count 0 2006.176.08:08:00.39#ibcon#about to read 4, iclass 28, count 0 2006.176.08:08:00.39#ibcon#read 4, iclass 28, count 0 2006.176.08:08:00.39#ibcon#about to read 5, iclass 28, count 0 2006.176.08:08:00.39#ibcon#read 5, iclass 28, count 0 2006.176.08:08:00.39#ibcon#about to read 6, iclass 28, count 0 2006.176.08:08:00.39#ibcon#read 6, iclass 28, count 0 2006.176.08:08:00.39#ibcon#end of sib2, iclass 28, count 0 2006.176.08:08:00.39#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:08:00.39#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:08:00.39#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:08:00.39#ibcon#*before write, iclass 28, count 0 2006.176.08:08:00.39#ibcon#enter sib2, iclass 28, count 0 2006.176.08:08:00.39#ibcon#flushed, iclass 28, count 0 2006.176.08:08:00.39#ibcon#about to write, iclass 28, count 0 2006.176.08:08:00.39#ibcon#wrote, iclass 28, count 0 2006.176.08:08:00.39#ibcon#about to read 3, iclass 28, count 0 2006.176.08:08:00.43#ibcon#read 3, iclass 28, count 0 2006.176.08:08:00.43#ibcon#about to read 4, iclass 28, count 0 2006.176.08:08:00.43#ibcon#read 4, iclass 28, count 0 2006.176.08:08:00.43#ibcon#about to read 5, iclass 28, count 0 2006.176.08:08:00.43#ibcon#read 5, iclass 28, count 0 2006.176.08:08:00.43#ibcon#about to read 6, iclass 28, count 0 2006.176.08:08:00.43#ibcon#read 6, iclass 28, count 0 2006.176.08:08:00.43#ibcon#end of sib2, iclass 28, count 0 2006.176.08:08:00.43#ibcon#*after write, iclass 28, count 0 2006.176.08:08:00.43#ibcon#*before return 0, iclass 28, count 0 2006.176.08:08:00.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:00.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:00.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:08:00.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:08:00.43$vc4f8/va=7,6 2006.176.08:08:00.43#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.08:08:00.43#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.08:08:00.43#ibcon#ireg 11 cls_cnt 2 2006.176.08:08:00.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:08:00.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:08:00.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:08:00.49#ibcon#enter wrdev, iclass 30, count 2 2006.176.08:08:00.49#ibcon#first serial, iclass 30, count 2 2006.176.08:08:00.49#ibcon#enter sib2, iclass 30, count 2 2006.176.08:08:00.49#ibcon#flushed, iclass 30, count 2 2006.176.08:08:00.49#ibcon#about to write, iclass 30, count 2 2006.176.08:08:00.49#ibcon#wrote, iclass 30, count 2 2006.176.08:08:00.49#ibcon#about to read 3, iclass 30, count 2 2006.176.08:08:00.51#ibcon#read 3, iclass 30, count 2 2006.176.08:08:00.51#ibcon#about to read 4, iclass 30, count 2 2006.176.08:08:00.51#ibcon#read 4, iclass 30, count 2 2006.176.08:08:00.51#ibcon#about to read 5, iclass 30, count 2 2006.176.08:08:00.51#ibcon#read 5, iclass 30, count 2 2006.176.08:08:00.51#ibcon#about to read 6, iclass 30, count 2 2006.176.08:08:00.51#ibcon#read 6, iclass 30, count 2 2006.176.08:08:00.51#ibcon#end of sib2, iclass 30, count 2 2006.176.08:08:00.51#ibcon#*mode == 0, iclass 30, count 2 2006.176.08:08:00.51#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.08:08:00.51#ibcon#[25=AT07-06\r\n] 2006.176.08:08:00.51#ibcon#*before write, iclass 30, count 2 2006.176.08:08:00.51#ibcon#enter sib2, iclass 30, count 2 2006.176.08:08:00.51#ibcon#flushed, iclass 30, count 2 2006.176.08:08:00.51#ibcon#about to write, iclass 30, count 2 2006.176.08:08:00.51#ibcon#wrote, iclass 30, count 2 2006.176.08:08:00.51#ibcon#about to read 3, iclass 30, count 2 2006.176.08:08:00.54#ibcon#read 3, iclass 30, count 2 2006.176.08:08:00.54#ibcon#about to read 4, iclass 30, count 2 2006.176.08:08:00.54#ibcon#read 4, iclass 30, count 2 2006.176.08:08:00.54#ibcon#about to read 5, iclass 30, count 2 2006.176.08:08:00.54#ibcon#read 5, iclass 30, count 2 2006.176.08:08:00.54#ibcon#about to read 6, iclass 30, count 2 2006.176.08:08:00.54#ibcon#read 6, iclass 30, count 2 2006.176.08:08:00.54#ibcon#end of sib2, iclass 30, count 2 2006.176.08:08:00.54#ibcon#*after write, iclass 30, count 2 2006.176.08:08:00.54#ibcon#*before return 0, iclass 30, count 2 2006.176.08:08:00.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:08:00.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:08:00.54#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.08:08:00.54#ibcon#ireg 7 cls_cnt 0 2006.176.08:08:00.54#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:08:00.66#abcon#<5=/05 3.0 4.7 23.86 911008.6\r\n> 2006.176.08:08:00.66#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:08:00.66#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:08:00.66#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:08:00.66#ibcon#first serial, iclass 30, count 0 2006.176.08:08:00.66#ibcon#enter sib2, iclass 30, count 0 2006.176.08:08:00.66#ibcon#flushed, iclass 30, count 0 2006.176.08:08:00.66#ibcon#about to write, iclass 30, count 0 2006.176.08:08:00.66#ibcon#wrote, iclass 30, count 0 2006.176.08:08:00.66#ibcon#about to read 3, iclass 30, count 0 2006.176.08:08:00.68#ibcon#read 3, iclass 30, count 0 2006.176.08:08:00.68#ibcon#about to read 4, iclass 30, count 0 2006.176.08:08:00.68#ibcon#read 4, iclass 30, count 0 2006.176.08:08:00.68#ibcon#about to read 5, iclass 30, count 0 2006.176.08:08:00.68#ibcon#read 5, iclass 30, count 0 2006.176.08:08:00.68#ibcon#about to read 6, iclass 30, count 0 2006.176.08:08:00.68#ibcon#read 6, iclass 30, count 0 2006.176.08:08:00.68#ibcon#end of sib2, iclass 30, count 0 2006.176.08:08:00.68#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:08:00.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:08:00.68#ibcon#[25=USB\r\n] 2006.176.08:08:00.68#ibcon#*before write, iclass 30, count 0 2006.176.08:08:00.68#ibcon#enter sib2, iclass 30, count 0 2006.176.08:08:00.68#ibcon#flushed, iclass 30, count 0 2006.176.08:08:00.68#ibcon#about to write, iclass 30, count 0 2006.176.08:08:00.68#ibcon#wrote, iclass 30, count 0 2006.176.08:08:00.68#ibcon#about to read 3, iclass 30, count 0 2006.176.08:08:00.68#abcon#{5=INTERFACE CLEAR} 2006.176.08:08:00.71#ibcon#read 3, iclass 30, count 0 2006.176.08:08:00.71#ibcon#about to read 4, iclass 30, count 0 2006.176.08:08:00.71#ibcon#read 4, iclass 30, count 0 2006.176.08:08:00.71#ibcon#about to read 5, iclass 30, count 0 2006.176.08:08:00.71#ibcon#read 5, iclass 30, count 0 2006.176.08:08:00.71#ibcon#about to read 6, iclass 30, count 0 2006.176.08:08:00.71#ibcon#read 6, iclass 30, count 0 2006.176.08:08:00.71#ibcon#end of sib2, iclass 30, count 0 2006.176.08:08:00.71#ibcon#*after write, iclass 30, count 0 2006.176.08:08:00.71#ibcon#*before return 0, iclass 30, count 0 2006.176.08:08:00.71#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:08:00.71#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:08:00.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:08:00.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:08:00.71$vc4f8/valo=8,852.99 2006.176.08:08:00.71#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.08:08:00.71#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.08:08:00.71#ibcon#ireg 17 cls_cnt 0 2006.176.08:08:00.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:08:00.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:08:00.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:08:00.71#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:08:00.71#ibcon#first serial, iclass 35, count 0 2006.176.08:08:00.71#ibcon#enter sib2, iclass 35, count 0 2006.176.08:08:00.71#ibcon#flushed, iclass 35, count 0 2006.176.08:08:00.71#ibcon#about to write, iclass 35, count 0 2006.176.08:08:00.71#ibcon#wrote, iclass 35, count 0 2006.176.08:08:00.71#ibcon#about to read 3, iclass 35, count 0 2006.176.08:08:00.73#ibcon#read 3, iclass 35, count 0 2006.176.08:08:00.73#ibcon#about to read 4, iclass 35, count 0 2006.176.08:08:00.73#ibcon#read 4, iclass 35, count 0 2006.176.08:08:00.73#ibcon#about to read 5, iclass 35, count 0 2006.176.08:08:00.73#ibcon#read 5, iclass 35, count 0 2006.176.08:08:00.73#ibcon#about to read 6, iclass 35, count 0 2006.176.08:08:00.73#ibcon#read 6, iclass 35, count 0 2006.176.08:08:00.73#ibcon#end of sib2, iclass 35, count 0 2006.176.08:08:00.73#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:08:00.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:08:00.73#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:08:00.73#ibcon#*before write, iclass 35, count 0 2006.176.08:08:00.73#ibcon#enter sib2, iclass 35, count 0 2006.176.08:08:00.73#ibcon#flushed, iclass 35, count 0 2006.176.08:08:00.73#ibcon#about to write, iclass 35, count 0 2006.176.08:08:00.73#ibcon#wrote, iclass 35, count 0 2006.176.08:08:00.73#ibcon#about to read 3, iclass 35, count 0 2006.176.08:08:00.74#abcon#[5=S1D000X0/0*\r\n] 2006.176.08:08:00.77#ibcon#read 3, iclass 35, count 0 2006.176.08:08:00.77#ibcon#about to read 4, iclass 35, count 0 2006.176.08:08:00.77#ibcon#read 4, iclass 35, count 0 2006.176.08:08:00.77#ibcon#about to read 5, iclass 35, count 0 2006.176.08:08:00.77#ibcon#read 5, iclass 35, count 0 2006.176.08:08:00.77#ibcon#about to read 6, iclass 35, count 0 2006.176.08:08:00.77#ibcon#read 6, iclass 35, count 0 2006.176.08:08:00.77#ibcon#end of sib2, iclass 35, count 0 2006.176.08:08:00.77#ibcon#*after write, iclass 35, count 0 2006.176.08:08:00.77#ibcon#*before return 0, iclass 35, count 0 2006.176.08:08:00.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:08:00.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:08:00.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:08:00.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:08:00.77$vc4f8/va=8,6 2006.176.08:08:00.77#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.08:08:00.77#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.08:08:00.77#ibcon#ireg 11 cls_cnt 2 2006.176.08:08:00.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:08:00.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:08:00.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:08:00.83#ibcon#enter wrdev, iclass 38, count 2 2006.176.08:08:00.83#ibcon#first serial, iclass 38, count 2 2006.176.08:08:00.83#ibcon#enter sib2, iclass 38, count 2 2006.176.08:08:00.83#ibcon#flushed, iclass 38, count 2 2006.176.08:08:00.83#ibcon#about to write, iclass 38, count 2 2006.176.08:08:00.83#ibcon#wrote, iclass 38, count 2 2006.176.08:08:00.83#ibcon#about to read 3, iclass 38, count 2 2006.176.08:08:00.85#ibcon#read 3, iclass 38, count 2 2006.176.08:08:00.85#ibcon#about to read 4, iclass 38, count 2 2006.176.08:08:00.85#ibcon#read 4, iclass 38, count 2 2006.176.08:08:00.85#ibcon#about to read 5, iclass 38, count 2 2006.176.08:08:00.85#ibcon#read 5, iclass 38, count 2 2006.176.08:08:00.85#ibcon#about to read 6, iclass 38, count 2 2006.176.08:08:00.85#ibcon#read 6, iclass 38, count 2 2006.176.08:08:00.85#ibcon#end of sib2, iclass 38, count 2 2006.176.08:08:00.85#ibcon#*mode == 0, iclass 38, count 2 2006.176.08:08:00.85#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.08:08:00.85#ibcon#[25=AT08-06\r\n] 2006.176.08:08:00.85#ibcon#*before write, iclass 38, count 2 2006.176.08:08:00.85#ibcon#enter sib2, iclass 38, count 2 2006.176.08:08:00.85#ibcon#flushed, iclass 38, count 2 2006.176.08:08:00.85#ibcon#about to write, iclass 38, count 2 2006.176.08:08:00.85#ibcon#wrote, iclass 38, count 2 2006.176.08:08:00.85#ibcon#about to read 3, iclass 38, count 2 2006.176.08:08:00.88#ibcon#read 3, iclass 38, count 2 2006.176.08:08:00.88#ibcon#about to read 4, iclass 38, count 2 2006.176.08:08:00.88#ibcon#read 4, iclass 38, count 2 2006.176.08:08:00.88#ibcon#about to read 5, iclass 38, count 2 2006.176.08:08:00.88#ibcon#read 5, iclass 38, count 2 2006.176.08:08:00.88#ibcon#about to read 6, iclass 38, count 2 2006.176.08:08:00.88#ibcon#read 6, iclass 38, count 2 2006.176.08:08:00.88#ibcon#end of sib2, iclass 38, count 2 2006.176.08:08:00.88#ibcon#*after write, iclass 38, count 2 2006.176.08:08:00.88#ibcon#*before return 0, iclass 38, count 2 2006.176.08:08:00.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:08:00.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:08:00.88#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.08:08:00.88#ibcon#ireg 7 cls_cnt 0 2006.176.08:08:00.88#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:08:01.00#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:08:01.00#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:08:01.00#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:08:01.00#ibcon#first serial, iclass 38, count 0 2006.176.08:08:01.00#ibcon#enter sib2, iclass 38, count 0 2006.176.08:08:01.00#ibcon#flushed, iclass 38, count 0 2006.176.08:08:01.00#ibcon#about to write, iclass 38, count 0 2006.176.08:08:01.00#ibcon#wrote, iclass 38, count 0 2006.176.08:08:01.00#ibcon#about to read 3, iclass 38, count 0 2006.176.08:08:01.02#ibcon#read 3, iclass 38, count 0 2006.176.08:08:01.02#ibcon#about to read 4, iclass 38, count 0 2006.176.08:08:01.02#ibcon#read 4, iclass 38, count 0 2006.176.08:08:01.02#ibcon#about to read 5, iclass 38, count 0 2006.176.08:08:01.02#ibcon#read 5, iclass 38, count 0 2006.176.08:08:01.02#ibcon#about to read 6, iclass 38, count 0 2006.176.08:08:01.02#ibcon#read 6, iclass 38, count 0 2006.176.08:08:01.02#ibcon#end of sib2, iclass 38, count 0 2006.176.08:08:01.02#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:08:01.02#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:08:01.02#ibcon#[25=USB\r\n] 2006.176.08:08:01.02#ibcon#*before write, iclass 38, count 0 2006.176.08:08:01.02#ibcon#enter sib2, iclass 38, count 0 2006.176.08:08:01.02#ibcon#flushed, iclass 38, count 0 2006.176.08:08:01.02#ibcon#about to write, iclass 38, count 0 2006.176.08:08:01.02#ibcon#wrote, iclass 38, count 0 2006.176.08:08:01.02#ibcon#about to read 3, iclass 38, count 0 2006.176.08:08:01.05#ibcon#read 3, iclass 38, count 0 2006.176.08:08:01.05#ibcon#about to read 4, iclass 38, count 0 2006.176.08:08:01.05#ibcon#read 4, iclass 38, count 0 2006.176.08:08:01.05#ibcon#about to read 5, iclass 38, count 0 2006.176.08:08:01.05#ibcon#read 5, iclass 38, count 0 2006.176.08:08:01.05#ibcon#about to read 6, iclass 38, count 0 2006.176.08:08:01.05#ibcon#read 6, iclass 38, count 0 2006.176.08:08:01.05#ibcon#end of sib2, iclass 38, count 0 2006.176.08:08:01.05#ibcon#*after write, iclass 38, count 0 2006.176.08:08:01.05#ibcon#*before return 0, iclass 38, count 0 2006.176.08:08:01.05#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:08:01.05#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:08:01.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:08:01.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:08:01.05$vc4f8/vblo=1,632.99 2006.176.08:08:01.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.08:08:01.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.08:08:01.05#ibcon#ireg 17 cls_cnt 0 2006.176.08:08:01.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:08:01.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:08:01.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:08:01.05#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:08:01.05#ibcon#first serial, iclass 40, count 0 2006.176.08:08:01.05#ibcon#enter sib2, iclass 40, count 0 2006.176.08:08:01.05#ibcon#flushed, iclass 40, count 0 2006.176.08:08:01.05#ibcon#about to write, iclass 40, count 0 2006.176.08:08:01.05#ibcon#wrote, iclass 40, count 0 2006.176.08:08:01.05#ibcon#about to read 3, iclass 40, count 0 2006.176.08:08:01.07#ibcon#read 3, iclass 40, count 0 2006.176.08:08:01.07#ibcon#about to read 4, iclass 40, count 0 2006.176.08:08:01.07#ibcon#read 4, iclass 40, count 0 2006.176.08:08:01.07#ibcon#about to read 5, iclass 40, count 0 2006.176.08:08:01.07#ibcon#read 5, iclass 40, count 0 2006.176.08:08:01.07#ibcon#about to read 6, iclass 40, count 0 2006.176.08:08:01.07#ibcon#read 6, iclass 40, count 0 2006.176.08:08:01.07#ibcon#end of sib2, iclass 40, count 0 2006.176.08:08:01.07#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:08:01.07#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:08:01.07#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:08:01.07#ibcon#*before write, iclass 40, count 0 2006.176.08:08:01.07#ibcon#enter sib2, iclass 40, count 0 2006.176.08:08:01.07#ibcon#flushed, iclass 40, count 0 2006.176.08:08:01.07#ibcon#about to write, iclass 40, count 0 2006.176.08:08:01.07#ibcon#wrote, iclass 40, count 0 2006.176.08:08:01.07#ibcon#about to read 3, iclass 40, count 0 2006.176.08:08:01.11#ibcon#read 3, iclass 40, count 0 2006.176.08:08:01.11#ibcon#about to read 4, iclass 40, count 0 2006.176.08:08:01.11#ibcon#read 4, iclass 40, count 0 2006.176.08:08:01.11#ibcon#about to read 5, iclass 40, count 0 2006.176.08:08:01.11#ibcon#read 5, iclass 40, count 0 2006.176.08:08:01.11#ibcon#about to read 6, iclass 40, count 0 2006.176.08:08:01.11#ibcon#read 6, iclass 40, count 0 2006.176.08:08:01.11#ibcon#end of sib2, iclass 40, count 0 2006.176.08:08:01.11#ibcon#*after write, iclass 40, count 0 2006.176.08:08:01.11#ibcon#*before return 0, iclass 40, count 0 2006.176.08:08:01.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:08:01.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:08:01.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:08:01.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:08:01.11$vc4f8/vb=1,4 2006.176.08:08:01.11#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.08:08:01.11#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.08:08:01.11#ibcon#ireg 11 cls_cnt 2 2006.176.08:08:01.11#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:08:01.11#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:08:01.11#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:08:01.11#ibcon#enter wrdev, iclass 4, count 2 2006.176.08:08:01.11#ibcon#first serial, iclass 4, count 2 2006.176.08:08:01.11#ibcon#enter sib2, iclass 4, count 2 2006.176.08:08:01.11#ibcon#flushed, iclass 4, count 2 2006.176.08:08:01.11#ibcon#about to write, iclass 4, count 2 2006.176.08:08:01.11#ibcon#wrote, iclass 4, count 2 2006.176.08:08:01.11#ibcon#about to read 3, iclass 4, count 2 2006.176.08:08:01.13#ibcon#read 3, iclass 4, count 2 2006.176.08:08:01.13#ibcon#about to read 4, iclass 4, count 2 2006.176.08:08:01.13#ibcon#read 4, iclass 4, count 2 2006.176.08:08:01.13#ibcon#about to read 5, iclass 4, count 2 2006.176.08:08:01.13#ibcon#read 5, iclass 4, count 2 2006.176.08:08:01.13#ibcon#about to read 6, iclass 4, count 2 2006.176.08:08:01.13#ibcon#read 6, iclass 4, count 2 2006.176.08:08:01.13#ibcon#end of sib2, iclass 4, count 2 2006.176.08:08:01.13#ibcon#*mode == 0, iclass 4, count 2 2006.176.08:08:01.13#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.08:08:01.13#ibcon#[27=AT01-04\r\n] 2006.176.08:08:01.13#ibcon#*before write, iclass 4, count 2 2006.176.08:08:01.13#ibcon#enter sib2, iclass 4, count 2 2006.176.08:08:01.13#ibcon#flushed, iclass 4, count 2 2006.176.08:08:01.13#ibcon#about to write, iclass 4, count 2 2006.176.08:08:01.13#ibcon#wrote, iclass 4, count 2 2006.176.08:08:01.13#ibcon#about to read 3, iclass 4, count 2 2006.176.08:08:01.16#ibcon#read 3, iclass 4, count 2 2006.176.08:08:01.16#ibcon#about to read 4, iclass 4, count 2 2006.176.08:08:01.16#ibcon#read 4, iclass 4, count 2 2006.176.08:08:01.16#ibcon#about to read 5, iclass 4, count 2 2006.176.08:08:01.16#ibcon#read 5, iclass 4, count 2 2006.176.08:08:01.16#ibcon#about to read 6, iclass 4, count 2 2006.176.08:08:01.16#ibcon#read 6, iclass 4, count 2 2006.176.08:08:01.16#ibcon#end of sib2, iclass 4, count 2 2006.176.08:08:01.16#ibcon#*after write, iclass 4, count 2 2006.176.08:08:01.16#ibcon#*before return 0, iclass 4, count 2 2006.176.08:08:01.16#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:08:01.16#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:08:01.16#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.08:08:01.16#ibcon#ireg 7 cls_cnt 0 2006.176.08:08:01.16#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:08:01.28#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:08:01.28#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:08:01.28#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:08:01.28#ibcon#first serial, iclass 4, count 0 2006.176.08:08:01.28#ibcon#enter sib2, iclass 4, count 0 2006.176.08:08:01.28#ibcon#flushed, iclass 4, count 0 2006.176.08:08:01.28#ibcon#about to write, iclass 4, count 0 2006.176.08:08:01.28#ibcon#wrote, iclass 4, count 0 2006.176.08:08:01.28#ibcon#about to read 3, iclass 4, count 0 2006.176.08:08:01.30#ibcon#read 3, iclass 4, count 0 2006.176.08:08:01.30#ibcon#about to read 4, iclass 4, count 0 2006.176.08:08:01.30#ibcon#read 4, iclass 4, count 0 2006.176.08:08:01.30#ibcon#about to read 5, iclass 4, count 0 2006.176.08:08:01.30#ibcon#read 5, iclass 4, count 0 2006.176.08:08:01.30#ibcon#about to read 6, iclass 4, count 0 2006.176.08:08:01.30#ibcon#read 6, iclass 4, count 0 2006.176.08:08:01.30#ibcon#end of sib2, iclass 4, count 0 2006.176.08:08:01.30#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:08:01.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:08:01.30#ibcon#[27=USB\r\n] 2006.176.08:08:01.30#ibcon#*before write, iclass 4, count 0 2006.176.08:08:01.30#ibcon#enter sib2, iclass 4, count 0 2006.176.08:08:01.30#ibcon#flushed, iclass 4, count 0 2006.176.08:08:01.30#ibcon#about to write, iclass 4, count 0 2006.176.08:08:01.30#ibcon#wrote, iclass 4, count 0 2006.176.08:08:01.30#ibcon#about to read 3, iclass 4, count 0 2006.176.08:08:01.33#ibcon#read 3, iclass 4, count 0 2006.176.08:08:01.33#ibcon#about to read 4, iclass 4, count 0 2006.176.08:08:01.33#ibcon#read 4, iclass 4, count 0 2006.176.08:08:01.33#ibcon#about to read 5, iclass 4, count 0 2006.176.08:08:01.33#ibcon#read 5, iclass 4, count 0 2006.176.08:08:01.33#ibcon#about to read 6, iclass 4, count 0 2006.176.08:08:01.33#ibcon#read 6, iclass 4, count 0 2006.176.08:08:01.33#ibcon#end of sib2, iclass 4, count 0 2006.176.08:08:01.33#ibcon#*after write, iclass 4, count 0 2006.176.08:08:01.33#ibcon#*before return 0, iclass 4, count 0 2006.176.08:08:01.33#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:08:01.33#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:08:01.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:08:01.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:08:01.33$vc4f8/vblo=2,640.99 2006.176.08:08:01.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.08:08:01.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.08:08:01.33#ibcon#ireg 17 cls_cnt 0 2006.176.08:08:01.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:08:01.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:08:01.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:08:01.33#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:08:01.33#ibcon#first serial, iclass 6, count 0 2006.176.08:08:01.33#ibcon#enter sib2, iclass 6, count 0 2006.176.08:08:01.33#ibcon#flushed, iclass 6, count 0 2006.176.08:08:01.33#ibcon#about to write, iclass 6, count 0 2006.176.08:08:01.33#ibcon#wrote, iclass 6, count 0 2006.176.08:08:01.33#ibcon#about to read 3, iclass 6, count 0 2006.176.08:08:01.35#ibcon#read 3, iclass 6, count 0 2006.176.08:08:01.35#ibcon#about to read 4, iclass 6, count 0 2006.176.08:08:01.35#ibcon#read 4, iclass 6, count 0 2006.176.08:08:01.35#ibcon#about to read 5, iclass 6, count 0 2006.176.08:08:01.35#ibcon#read 5, iclass 6, count 0 2006.176.08:08:01.35#ibcon#about to read 6, iclass 6, count 0 2006.176.08:08:01.35#ibcon#read 6, iclass 6, count 0 2006.176.08:08:01.35#ibcon#end of sib2, iclass 6, count 0 2006.176.08:08:01.35#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:08:01.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:08:01.35#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:08:01.35#ibcon#*before write, iclass 6, count 0 2006.176.08:08:01.35#ibcon#enter sib2, iclass 6, count 0 2006.176.08:08:01.35#ibcon#flushed, iclass 6, count 0 2006.176.08:08:01.35#ibcon#about to write, iclass 6, count 0 2006.176.08:08:01.35#ibcon#wrote, iclass 6, count 0 2006.176.08:08:01.35#ibcon#about to read 3, iclass 6, count 0 2006.176.08:08:01.40#ibcon#read 3, iclass 6, count 0 2006.176.08:08:01.40#ibcon#about to read 4, iclass 6, count 0 2006.176.08:08:01.40#ibcon#read 4, iclass 6, count 0 2006.176.08:08:01.40#ibcon#about to read 5, iclass 6, count 0 2006.176.08:08:01.40#ibcon#read 5, iclass 6, count 0 2006.176.08:08:01.40#ibcon#about to read 6, iclass 6, count 0 2006.176.08:08:01.40#ibcon#read 6, iclass 6, count 0 2006.176.08:08:01.40#ibcon#end of sib2, iclass 6, count 0 2006.176.08:08:01.40#ibcon#*after write, iclass 6, count 0 2006.176.08:08:01.40#ibcon#*before return 0, iclass 6, count 0 2006.176.08:08:01.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:08:01.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:08:01.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:08:01.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:08:01.40$vc4f8/vb=2,4 2006.176.08:08:01.40#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.08:08:01.40#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.08:08:01.40#ibcon#ireg 11 cls_cnt 2 2006.176.08:08:01.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:08:01.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:08:01.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:08:01.44#ibcon#enter wrdev, iclass 10, count 2 2006.176.08:08:01.44#ibcon#first serial, iclass 10, count 2 2006.176.08:08:01.44#ibcon#enter sib2, iclass 10, count 2 2006.176.08:08:01.44#ibcon#flushed, iclass 10, count 2 2006.176.08:08:01.44#ibcon#about to write, iclass 10, count 2 2006.176.08:08:01.44#ibcon#wrote, iclass 10, count 2 2006.176.08:08:01.44#ibcon#about to read 3, iclass 10, count 2 2006.176.08:08:01.46#ibcon#read 3, iclass 10, count 2 2006.176.08:08:01.46#ibcon#about to read 4, iclass 10, count 2 2006.176.08:08:01.46#ibcon#read 4, iclass 10, count 2 2006.176.08:08:01.46#ibcon#about to read 5, iclass 10, count 2 2006.176.08:08:01.46#ibcon#read 5, iclass 10, count 2 2006.176.08:08:01.46#ibcon#about to read 6, iclass 10, count 2 2006.176.08:08:01.46#ibcon#read 6, iclass 10, count 2 2006.176.08:08:01.46#ibcon#end of sib2, iclass 10, count 2 2006.176.08:08:01.46#ibcon#*mode == 0, iclass 10, count 2 2006.176.08:08:01.46#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.08:08:01.46#ibcon#[27=AT02-04\r\n] 2006.176.08:08:01.46#ibcon#*before write, iclass 10, count 2 2006.176.08:08:01.46#ibcon#enter sib2, iclass 10, count 2 2006.176.08:08:01.46#ibcon#flushed, iclass 10, count 2 2006.176.08:08:01.46#ibcon#about to write, iclass 10, count 2 2006.176.08:08:01.46#ibcon#wrote, iclass 10, count 2 2006.176.08:08:01.46#ibcon#about to read 3, iclass 10, count 2 2006.176.08:08:01.49#ibcon#read 3, iclass 10, count 2 2006.176.08:08:01.49#ibcon#about to read 4, iclass 10, count 2 2006.176.08:08:01.49#ibcon#read 4, iclass 10, count 2 2006.176.08:08:01.49#ibcon#about to read 5, iclass 10, count 2 2006.176.08:08:01.49#ibcon#read 5, iclass 10, count 2 2006.176.08:08:01.49#ibcon#about to read 6, iclass 10, count 2 2006.176.08:08:01.49#ibcon#read 6, iclass 10, count 2 2006.176.08:08:01.49#ibcon#end of sib2, iclass 10, count 2 2006.176.08:08:01.49#ibcon#*after write, iclass 10, count 2 2006.176.08:08:01.49#ibcon#*before return 0, iclass 10, count 2 2006.176.08:08:01.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:08:01.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:08:01.49#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.08:08:01.49#ibcon#ireg 7 cls_cnt 0 2006.176.08:08:01.49#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:08:01.61#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:08:01.61#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:08:01.61#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:08:01.61#ibcon#first serial, iclass 10, count 0 2006.176.08:08:01.61#ibcon#enter sib2, iclass 10, count 0 2006.176.08:08:01.61#ibcon#flushed, iclass 10, count 0 2006.176.08:08:01.61#ibcon#about to write, iclass 10, count 0 2006.176.08:08:01.61#ibcon#wrote, iclass 10, count 0 2006.176.08:08:01.61#ibcon#about to read 3, iclass 10, count 0 2006.176.08:08:01.63#ibcon#read 3, iclass 10, count 0 2006.176.08:08:01.63#ibcon#about to read 4, iclass 10, count 0 2006.176.08:08:01.63#ibcon#read 4, iclass 10, count 0 2006.176.08:08:01.63#ibcon#about to read 5, iclass 10, count 0 2006.176.08:08:01.63#ibcon#read 5, iclass 10, count 0 2006.176.08:08:01.63#ibcon#about to read 6, iclass 10, count 0 2006.176.08:08:01.63#ibcon#read 6, iclass 10, count 0 2006.176.08:08:01.63#ibcon#end of sib2, iclass 10, count 0 2006.176.08:08:01.63#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:08:01.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:08:01.63#ibcon#[27=USB\r\n] 2006.176.08:08:01.63#ibcon#*before write, iclass 10, count 0 2006.176.08:08:01.63#ibcon#enter sib2, iclass 10, count 0 2006.176.08:08:01.63#ibcon#flushed, iclass 10, count 0 2006.176.08:08:01.63#ibcon#about to write, iclass 10, count 0 2006.176.08:08:01.63#ibcon#wrote, iclass 10, count 0 2006.176.08:08:01.63#ibcon#about to read 3, iclass 10, count 0 2006.176.08:08:01.66#ibcon#read 3, iclass 10, count 0 2006.176.08:08:01.66#ibcon#about to read 4, iclass 10, count 0 2006.176.08:08:01.66#ibcon#read 4, iclass 10, count 0 2006.176.08:08:01.66#ibcon#about to read 5, iclass 10, count 0 2006.176.08:08:01.66#ibcon#read 5, iclass 10, count 0 2006.176.08:08:01.66#ibcon#about to read 6, iclass 10, count 0 2006.176.08:08:01.66#ibcon#read 6, iclass 10, count 0 2006.176.08:08:01.66#ibcon#end of sib2, iclass 10, count 0 2006.176.08:08:01.66#ibcon#*after write, iclass 10, count 0 2006.176.08:08:01.66#ibcon#*before return 0, iclass 10, count 0 2006.176.08:08:01.66#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:08:01.66#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:08:01.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:08:01.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:08:01.66$vc4f8/vblo=3,656.99 2006.176.08:08:01.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.08:08:01.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.08:08:01.66#ibcon#ireg 17 cls_cnt 0 2006.176.08:08:01.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:08:01.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:08:01.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:08:01.66#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:08:01.66#ibcon#first serial, iclass 12, count 0 2006.176.08:08:01.66#ibcon#enter sib2, iclass 12, count 0 2006.176.08:08:01.66#ibcon#flushed, iclass 12, count 0 2006.176.08:08:01.66#ibcon#about to write, iclass 12, count 0 2006.176.08:08:01.66#ibcon#wrote, iclass 12, count 0 2006.176.08:08:01.66#ibcon#about to read 3, iclass 12, count 0 2006.176.08:08:01.68#ibcon#read 3, iclass 12, count 0 2006.176.08:08:01.68#ibcon#about to read 4, iclass 12, count 0 2006.176.08:08:01.68#ibcon#read 4, iclass 12, count 0 2006.176.08:08:01.68#ibcon#about to read 5, iclass 12, count 0 2006.176.08:08:01.68#ibcon#read 5, iclass 12, count 0 2006.176.08:08:01.68#ibcon#about to read 6, iclass 12, count 0 2006.176.08:08:01.68#ibcon#read 6, iclass 12, count 0 2006.176.08:08:01.68#ibcon#end of sib2, iclass 12, count 0 2006.176.08:08:01.68#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:08:01.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:08:01.68#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:08:01.68#ibcon#*before write, iclass 12, count 0 2006.176.08:08:01.68#ibcon#enter sib2, iclass 12, count 0 2006.176.08:08:01.68#ibcon#flushed, iclass 12, count 0 2006.176.08:08:01.68#ibcon#about to write, iclass 12, count 0 2006.176.08:08:01.68#ibcon#wrote, iclass 12, count 0 2006.176.08:08:01.68#ibcon#about to read 3, iclass 12, count 0 2006.176.08:08:01.72#ibcon#read 3, iclass 12, count 0 2006.176.08:08:01.72#ibcon#about to read 4, iclass 12, count 0 2006.176.08:08:01.72#ibcon#read 4, iclass 12, count 0 2006.176.08:08:01.72#ibcon#about to read 5, iclass 12, count 0 2006.176.08:08:01.72#ibcon#read 5, iclass 12, count 0 2006.176.08:08:01.72#ibcon#about to read 6, iclass 12, count 0 2006.176.08:08:01.72#ibcon#read 6, iclass 12, count 0 2006.176.08:08:01.72#ibcon#end of sib2, iclass 12, count 0 2006.176.08:08:01.72#ibcon#*after write, iclass 12, count 0 2006.176.08:08:01.72#ibcon#*before return 0, iclass 12, count 0 2006.176.08:08:01.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:08:01.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:08:01.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:08:01.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:08:01.72$vc4f8/vb=3,4 2006.176.08:08:01.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.08:08:01.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.08:08:01.72#ibcon#ireg 11 cls_cnt 2 2006.176.08:08:01.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:08:01.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:08:01.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:08:01.78#ibcon#enter wrdev, iclass 14, count 2 2006.176.08:08:01.78#ibcon#first serial, iclass 14, count 2 2006.176.08:08:01.78#ibcon#enter sib2, iclass 14, count 2 2006.176.08:08:01.78#ibcon#flushed, iclass 14, count 2 2006.176.08:08:01.78#ibcon#about to write, iclass 14, count 2 2006.176.08:08:01.78#ibcon#wrote, iclass 14, count 2 2006.176.08:08:01.78#ibcon#about to read 3, iclass 14, count 2 2006.176.08:08:01.80#ibcon#read 3, iclass 14, count 2 2006.176.08:08:01.80#ibcon#about to read 4, iclass 14, count 2 2006.176.08:08:01.80#ibcon#read 4, iclass 14, count 2 2006.176.08:08:01.80#ibcon#about to read 5, iclass 14, count 2 2006.176.08:08:01.80#ibcon#read 5, iclass 14, count 2 2006.176.08:08:01.80#ibcon#about to read 6, iclass 14, count 2 2006.176.08:08:01.80#ibcon#read 6, iclass 14, count 2 2006.176.08:08:01.80#ibcon#end of sib2, iclass 14, count 2 2006.176.08:08:01.80#ibcon#*mode == 0, iclass 14, count 2 2006.176.08:08:01.80#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.08:08:01.80#ibcon#[27=AT03-04\r\n] 2006.176.08:08:01.80#ibcon#*before write, iclass 14, count 2 2006.176.08:08:01.80#ibcon#enter sib2, iclass 14, count 2 2006.176.08:08:01.80#ibcon#flushed, iclass 14, count 2 2006.176.08:08:01.80#ibcon#about to write, iclass 14, count 2 2006.176.08:08:01.80#ibcon#wrote, iclass 14, count 2 2006.176.08:08:01.80#ibcon#about to read 3, iclass 14, count 2 2006.176.08:08:01.83#ibcon#read 3, iclass 14, count 2 2006.176.08:08:01.83#ibcon#about to read 4, iclass 14, count 2 2006.176.08:08:01.83#ibcon#read 4, iclass 14, count 2 2006.176.08:08:01.83#ibcon#about to read 5, iclass 14, count 2 2006.176.08:08:01.83#ibcon#read 5, iclass 14, count 2 2006.176.08:08:01.83#ibcon#about to read 6, iclass 14, count 2 2006.176.08:08:01.83#ibcon#read 6, iclass 14, count 2 2006.176.08:08:01.83#ibcon#end of sib2, iclass 14, count 2 2006.176.08:08:01.83#ibcon#*after write, iclass 14, count 2 2006.176.08:08:01.83#ibcon#*before return 0, iclass 14, count 2 2006.176.08:08:01.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:08:01.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:08:01.83#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.08:08:01.83#ibcon#ireg 7 cls_cnt 0 2006.176.08:08:01.83#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:08:01.95#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:08:01.95#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:08:01.95#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:08:01.95#ibcon#first serial, iclass 14, count 0 2006.176.08:08:01.95#ibcon#enter sib2, iclass 14, count 0 2006.176.08:08:01.95#ibcon#flushed, iclass 14, count 0 2006.176.08:08:01.95#ibcon#about to write, iclass 14, count 0 2006.176.08:08:01.95#ibcon#wrote, iclass 14, count 0 2006.176.08:08:01.95#ibcon#about to read 3, iclass 14, count 0 2006.176.08:08:01.97#ibcon#read 3, iclass 14, count 0 2006.176.08:08:01.97#ibcon#about to read 4, iclass 14, count 0 2006.176.08:08:01.97#ibcon#read 4, iclass 14, count 0 2006.176.08:08:01.97#ibcon#about to read 5, iclass 14, count 0 2006.176.08:08:01.97#ibcon#read 5, iclass 14, count 0 2006.176.08:08:01.97#ibcon#about to read 6, iclass 14, count 0 2006.176.08:08:01.97#ibcon#read 6, iclass 14, count 0 2006.176.08:08:01.97#ibcon#end of sib2, iclass 14, count 0 2006.176.08:08:01.97#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:08:01.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:08:01.97#ibcon#[27=USB\r\n] 2006.176.08:08:01.97#ibcon#*before write, iclass 14, count 0 2006.176.08:08:01.97#ibcon#enter sib2, iclass 14, count 0 2006.176.08:08:01.97#ibcon#flushed, iclass 14, count 0 2006.176.08:08:01.97#ibcon#about to write, iclass 14, count 0 2006.176.08:08:01.97#ibcon#wrote, iclass 14, count 0 2006.176.08:08:01.97#ibcon#about to read 3, iclass 14, count 0 2006.176.08:08:02.00#ibcon#read 3, iclass 14, count 0 2006.176.08:08:02.00#ibcon#about to read 4, iclass 14, count 0 2006.176.08:08:02.00#ibcon#read 4, iclass 14, count 0 2006.176.08:08:02.00#ibcon#about to read 5, iclass 14, count 0 2006.176.08:08:02.00#ibcon#read 5, iclass 14, count 0 2006.176.08:08:02.00#ibcon#about to read 6, iclass 14, count 0 2006.176.08:08:02.00#ibcon#read 6, iclass 14, count 0 2006.176.08:08:02.00#ibcon#end of sib2, iclass 14, count 0 2006.176.08:08:02.00#ibcon#*after write, iclass 14, count 0 2006.176.08:08:02.00#ibcon#*before return 0, iclass 14, count 0 2006.176.08:08:02.00#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:08:02.00#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:08:02.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:08:02.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:08:02.00$vc4f8/vblo=4,712.99 2006.176.08:08:02.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.08:08:02.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.08:08:02.00#ibcon#ireg 17 cls_cnt 0 2006.176.08:08:02.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:08:02.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:08:02.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:08:02.00#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:08:02.00#ibcon#first serial, iclass 16, count 0 2006.176.08:08:02.00#ibcon#enter sib2, iclass 16, count 0 2006.176.08:08:02.00#ibcon#flushed, iclass 16, count 0 2006.176.08:08:02.00#ibcon#about to write, iclass 16, count 0 2006.176.08:08:02.00#ibcon#wrote, iclass 16, count 0 2006.176.08:08:02.00#ibcon#about to read 3, iclass 16, count 0 2006.176.08:08:02.02#ibcon#read 3, iclass 16, count 0 2006.176.08:08:02.02#ibcon#about to read 4, iclass 16, count 0 2006.176.08:08:02.02#ibcon#read 4, iclass 16, count 0 2006.176.08:08:02.02#ibcon#about to read 5, iclass 16, count 0 2006.176.08:08:02.02#ibcon#read 5, iclass 16, count 0 2006.176.08:08:02.02#ibcon#about to read 6, iclass 16, count 0 2006.176.08:08:02.02#ibcon#read 6, iclass 16, count 0 2006.176.08:08:02.02#ibcon#end of sib2, iclass 16, count 0 2006.176.08:08:02.02#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:08:02.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:08:02.02#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:08:02.02#ibcon#*before write, iclass 16, count 0 2006.176.08:08:02.02#ibcon#enter sib2, iclass 16, count 0 2006.176.08:08:02.02#ibcon#flushed, iclass 16, count 0 2006.176.08:08:02.02#ibcon#about to write, iclass 16, count 0 2006.176.08:08:02.02#ibcon#wrote, iclass 16, count 0 2006.176.08:08:02.02#ibcon#about to read 3, iclass 16, count 0 2006.176.08:08:02.06#ibcon#read 3, iclass 16, count 0 2006.176.08:08:02.06#ibcon#about to read 4, iclass 16, count 0 2006.176.08:08:02.06#ibcon#read 4, iclass 16, count 0 2006.176.08:08:02.06#ibcon#about to read 5, iclass 16, count 0 2006.176.08:08:02.06#ibcon#read 5, iclass 16, count 0 2006.176.08:08:02.06#ibcon#about to read 6, iclass 16, count 0 2006.176.08:08:02.06#ibcon#read 6, iclass 16, count 0 2006.176.08:08:02.06#ibcon#end of sib2, iclass 16, count 0 2006.176.08:08:02.06#ibcon#*after write, iclass 16, count 0 2006.176.08:08:02.06#ibcon#*before return 0, iclass 16, count 0 2006.176.08:08:02.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:08:02.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:08:02.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:08:02.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:08:02.06$vc4f8/vb=4,4 2006.176.08:08:02.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.08:08:02.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.08:08:02.06#ibcon#ireg 11 cls_cnt 2 2006.176.08:08:02.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:08:02.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:08:02.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:08:02.12#ibcon#enter wrdev, iclass 18, count 2 2006.176.08:08:02.12#ibcon#first serial, iclass 18, count 2 2006.176.08:08:02.12#ibcon#enter sib2, iclass 18, count 2 2006.176.08:08:02.12#ibcon#flushed, iclass 18, count 2 2006.176.08:08:02.12#ibcon#about to write, iclass 18, count 2 2006.176.08:08:02.12#ibcon#wrote, iclass 18, count 2 2006.176.08:08:02.12#ibcon#about to read 3, iclass 18, count 2 2006.176.08:08:02.14#ibcon#read 3, iclass 18, count 2 2006.176.08:08:02.14#ibcon#about to read 4, iclass 18, count 2 2006.176.08:08:02.14#ibcon#read 4, iclass 18, count 2 2006.176.08:08:02.14#ibcon#about to read 5, iclass 18, count 2 2006.176.08:08:02.14#ibcon#read 5, iclass 18, count 2 2006.176.08:08:02.14#ibcon#about to read 6, iclass 18, count 2 2006.176.08:08:02.14#ibcon#read 6, iclass 18, count 2 2006.176.08:08:02.14#ibcon#end of sib2, iclass 18, count 2 2006.176.08:08:02.14#ibcon#*mode == 0, iclass 18, count 2 2006.176.08:08:02.14#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.08:08:02.14#ibcon#[27=AT04-04\r\n] 2006.176.08:08:02.14#ibcon#*before write, iclass 18, count 2 2006.176.08:08:02.14#ibcon#enter sib2, iclass 18, count 2 2006.176.08:08:02.14#ibcon#flushed, iclass 18, count 2 2006.176.08:08:02.14#ibcon#about to write, iclass 18, count 2 2006.176.08:08:02.14#ibcon#wrote, iclass 18, count 2 2006.176.08:08:02.14#ibcon#about to read 3, iclass 18, count 2 2006.176.08:08:02.17#ibcon#read 3, iclass 18, count 2 2006.176.08:08:02.17#ibcon#about to read 4, iclass 18, count 2 2006.176.08:08:02.17#ibcon#read 4, iclass 18, count 2 2006.176.08:08:02.17#ibcon#about to read 5, iclass 18, count 2 2006.176.08:08:02.17#ibcon#read 5, iclass 18, count 2 2006.176.08:08:02.17#ibcon#about to read 6, iclass 18, count 2 2006.176.08:08:02.17#ibcon#read 6, iclass 18, count 2 2006.176.08:08:02.17#ibcon#end of sib2, iclass 18, count 2 2006.176.08:08:02.17#ibcon#*after write, iclass 18, count 2 2006.176.08:08:02.17#ibcon#*before return 0, iclass 18, count 2 2006.176.08:08:02.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:08:02.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:08:02.17#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.08:08:02.17#ibcon#ireg 7 cls_cnt 0 2006.176.08:08:02.17#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:08:02.29#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:08:02.29#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:08:02.29#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:08:02.29#ibcon#first serial, iclass 18, count 0 2006.176.08:08:02.29#ibcon#enter sib2, iclass 18, count 0 2006.176.08:08:02.29#ibcon#flushed, iclass 18, count 0 2006.176.08:08:02.29#ibcon#about to write, iclass 18, count 0 2006.176.08:08:02.29#ibcon#wrote, iclass 18, count 0 2006.176.08:08:02.29#ibcon#about to read 3, iclass 18, count 0 2006.176.08:08:02.31#ibcon#read 3, iclass 18, count 0 2006.176.08:08:02.31#ibcon#about to read 4, iclass 18, count 0 2006.176.08:08:02.31#ibcon#read 4, iclass 18, count 0 2006.176.08:08:02.31#ibcon#about to read 5, iclass 18, count 0 2006.176.08:08:02.31#ibcon#read 5, iclass 18, count 0 2006.176.08:08:02.31#ibcon#about to read 6, iclass 18, count 0 2006.176.08:08:02.31#ibcon#read 6, iclass 18, count 0 2006.176.08:08:02.31#ibcon#end of sib2, iclass 18, count 0 2006.176.08:08:02.31#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:08:02.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:08:02.31#ibcon#[27=USB\r\n] 2006.176.08:08:02.31#ibcon#*before write, iclass 18, count 0 2006.176.08:08:02.31#ibcon#enter sib2, iclass 18, count 0 2006.176.08:08:02.31#ibcon#flushed, iclass 18, count 0 2006.176.08:08:02.31#ibcon#about to write, iclass 18, count 0 2006.176.08:08:02.31#ibcon#wrote, iclass 18, count 0 2006.176.08:08:02.31#ibcon#about to read 3, iclass 18, count 0 2006.176.08:08:02.34#ibcon#read 3, iclass 18, count 0 2006.176.08:08:02.34#ibcon#about to read 4, iclass 18, count 0 2006.176.08:08:02.34#ibcon#read 4, iclass 18, count 0 2006.176.08:08:02.34#ibcon#about to read 5, iclass 18, count 0 2006.176.08:08:02.34#ibcon#read 5, iclass 18, count 0 2006.176.08:08:02.34#ibcon#about to read 6, iclass 18, count 0 2006.176.08:08:02.34#ibcon#read 6, iclass 18, count 0 2006.176.08:08:02.34#ibcon#end of sib2, iclass 18, count 0 2006.176.08:08:02.34#ibcon#*after write, iclass 18, count 0 2006.176.08:08:02.34#ibcon#*before return 0, iclass 18, count 0 2006.176.08:08:02.34#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:08:02.34#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:08:02.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:08:02.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:08:02.34$vc4f8/vblo=5,744.99 2006.176.08:08:02.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.08:08:02.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.08:08:02.34#ibcon#ireg 17 cls_cnt 0 2006.176.08:08:02.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:08:02.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:08:02.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:08:02.34#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:08:02.34#ibcon#first serial, iclass 20, count 0 2006.176.08:08:02.34#ibcon#enter sib2, iclass 20, count 0 2006.176.08:08:02.34#ibcon#flushed, iclass 20, count 0 2006.176.08:08:02.34#ibcon#about to write, iclass 20, count 0 2006.176.08:08:02.34#ibcon#wrote, iclass 20, count 0 2006.176.08:08:02.34#ibcon#about to read 3, iclass 20, count 0 2006.176.08:08:02.36#ibcon#read 3, iclass 20, count 0 2006.176.08:08:02.36#ibcon#about to read 4, iclass 20, count 0 2006.176.08:08:02.36#ibcon#read 4, iclass 20, count 0 2006.176.08:08:02.36#ibcon#about to read 5, iclass 20, count 0 2006.176.08:08:02.36#ibcon#read 5, iclass 20, count 0 2006.176.08:08:02.36#ibcon#about to read 6, iclass 20, count 0 2006.176.08:08:02.36#ibcon#read 6, iclass 20, count 0 2006.176.08:08:02.36#ibcon#end of sib2, iclass 20, count 0 2006.176.08:08:02.36#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:08:02.36#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:08:02.36#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:08:02.36#ibcon#*before write, iclass 20, count 0 2006.176.08:08:02.36#ibcon#enter sib2, iclass 20, count 0 2006.176.08:08:02.36#ibcon#flushed, iclass 20, count 0 2006.176.08:08:02.36#ibcon#about to write, iclass 20, count 0 2006.176.08:08:02.36#ibcon#wrote, iclass 20, count 0 2006.176.08:08:02.36#ibcon#about to read 3, iclass 20, count 0 2006.176.08:08:02.40#ibcon#read 3, iclass 20, count 0 2006.176.08:08:02.40#ibcon#about to read 4, iclass 20, count 0 2006.176.08:08:02.40#ibcon#read 4, iclass 20, count 0 2006.176.08:08:02.40#ibcon#about to read 5, iclass 20, count 0 2006.176.08:08:02.40#ibcon#read 5, iclass 20, count 0 2006.176.08:08:02.40#ibcon#about to read 6, iclass 20, count 0 2006.176.08:08:02.40#ibcon#read 6, iclass 20, count 0 2006.176.08:08:02.40#ibcon#end of sib2, iclass 20, count 0 2006.176.08:08:02.40#ibcon#*after write, iclass 20, count 0 2006.176.08:08:02.40#ibcon#*before return 0, iclass 20, count 0 2006.176.08:08:02.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:08:02.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:08:02.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:08:02.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:08:02.40$vc4f8/vb=5,4 2006.176.08:08:02.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.08:08:02.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.08:08:02.40#ibcon#ireg 11 cls_cnt 2 2006.176.08:08:02.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:08:02.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:08:02.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:08:02.46#ibcon#enter wrdev, iclass 22, count 2 2006.176.08:08:02.46#ibcon#first serial, iclass 22, count 2 2006.176.08:08:02.46#ibcon#enter sib2, iclass 22, count 2 2006.176.08:08:02.46#ibcon#flushed, iclass 22, count 2 2006.176.08:08:02.46#ibcon#about to write, iclass 22, count 2 2006.176.08:08:02.46#ibcon#wrote, iclass 22, count 2 2006.176.08:08:02.46#ibcon#about to read 3, iclass 22, count 2 2006.176.08:08:02.48#ibcon#read 3, iclass 22, count 2 2006.176.08:08:02.48#ibcon#about to read 4, iclass 22, count 2 2006.176.08:08:02.48#ibcon#read 4, iclass 22, count 2 2006.176.08:08:02.48#ibcon#about to read 5, iclass 22, count 2 2006.176.08:08:02.48#ibcon#read 5, iclass 22, count 2 2006.176.08:08:02.48#ibcon#about to read 6, iclass 22, count 2 2006.176.08:08:02.48#ibcon#read 6, iclass 22, count 2 2006.176.08:08:02.48#ibcon#end of sib2, iclass 22, count 2 2006.176.08:08:02.48#ibcon#*mode == 0, iclass 22, count 2 2006.176.08:08:02.48#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.08:08:02.48#ibcon#[27=AT05-04\r\n] 2006.176.08:08:02.48#ibcon#*before write, iclass 22, count 2 2006.176.08:08:02.48#ibcon#enter sib2, iclass 22, count 2 2006.176.08:08:02.48#ibcon#flushed, iclass 22, count 2 2006.176.08:08:02.48#ibcon#about to write, iclass 22, count 2 2006.176.08:08:02.48#ibcon#wrote, iclass 22, count 2 2006.176.08:08:02.48#ibcon#about to read 3, iclass 22, count 2 2006.176.08:08:02.51#ibcon#read 3, iclass 22, count 2 2006.176.08:08:02.51#ibcon#about to read 4, iclass 22, count 2 2006.176.08:08:02.51#ibcon#read 4, iclass 22, count 2 2006.176.08:08:02.51#ibcon#about to read 5, iclass 22, count 2 2006.176.08:08:02.51#ibcon#read 5, iclass 22, count 2 2006.176.08:08:02.51#ibcon#about to read 6, iclass 22, count 2 2006.176.08:08:02.51#ibcon#read 6, iclass 22, count 2 2006.176.08:08:02.51#ibcon#end of sib2, iclass 22, count 2 2006.176.08:08:02.51#ibcon#*after write, iclass 22, count 2 2006.176.08:08:02.51#ibcon#*before return 0, iclass 22, count 2 2006.176.08:08:02.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:08:02.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:08:02.51#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.08:08:02.51#ibcon#ireg 7 cls_cnt 0 2006.176.08:08:02.51#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:08:02.63#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:08:02.63#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:08:02.63#ibcon#enter wrdev, iclass 22, count 0 2006.176.08:08:02.63#ibcon#first serial, iclass 22, count 0 2006.176.08:08:02.63#ibcon#enter sib2, iclass 22, count 0 2006.176.08:08:02.63#ibcon#flushed, iclass 22, count 0 2006.176.08:08:02.63#ibcon#about to write, iclass 22, count 0 2006.176.08:08:02.63#ibcon#wrote, iclass 22, count 0 2006.176.08:08:02.63#ibcon#about to read 3, iclass 22, count 0 2006.176.08:08:02.65#ibcon#read 3, iclass 22, count 0 2006.176.08:08:02.65#ibcon#about to read 4, iclass 22, count 0 2006.176.08:08:02.65#ibcon#read 4, iclass 22, count 0 2006.176.08:08:02.65#ibcon#about to read 5, iclass 22, count 0 2006.176.08:08:02.65#ibcon#read 5, iclass 22, count 0 2006.176.08:08:02.65#ibcon#about to read 6, iclass 22, count 0 2006.176.08:08:02.65#ibcon#read 6, iclass 22, count 0 2006.176.08:08:02.65#ibcon#end of sib2, iclass 22, count 0 2006.176.08:08:02.65#ibcon#*mode == 0, iclass 22, count 0 2006.176.08:08:02.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.08:08:02.65#ibcon#[27=USB\r\n] 2006.176.08:08:02.65#ibcon#*before write, iclass 22, count 0 2006.176.08:08:02.65#ibcon#enter sib2, iclass 22, count 0 2006.176.08:08:02.65#ibcon#flushed, iclass 22, count 0 2006.176.08:08:02.65#ibcon#about to write, iclass 22, count 0 2006.176.08:08:02.65#ibcon#wrote, iclass 22, count 0 2006.176.08:08:02.65#ibcon#about to read 3, iclass 22, count 0 2006.176.08:08:02.68#ibcon#read 3, iclass 22, count 0 2006.176.08:08:02.68#ibcon#about to read 4, iclass 22, count 0 2006.176.08:08:02.68#ibcon#read 4, iclass 22, count 0 2006.176.08:08:02.68#ibcon#about to read 5, iclass 22, count 0 2006.176.08:08:02.68#ibcon#read 5, iclass 22, count 0 2006.176.08:08:02.68#ibcon#about to read 6, iclass 22, count 0 2006.176.08:08:02.68#ibcon#read 6, iclass 22, count 0 2006.176.08:08:02.68#ibcon#end of sib2, iclass 22, count 0 2006.176.08:08:02.68#ibcon#*after write, iclass 22, count 0 2006.176.08:08:02.68#ibcon#*before return 0, iclass 22, count 0 2006.176.08:08:02.68#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:08:02.68#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:08:02.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.08:08:02.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.08:08:02.68$vc4f8/vblo=6,752.99 2006.176.08:08:02.68#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.08:08:02.68#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.08:08:02.68#ibcon#ireg 17 cls_cnt 0 2006.176.08:08:02.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:02.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:02.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:02.68#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:08:02.68#ibcon#first serial, iclass 24, count 0 2006.176.08:08:02.68#ibcon#enter sib2, iclass 24, count 0 2006.176.08:08:02.68#ibcon#flushed, iclass 24, count 0 2006.176.08:08:02.68#ibcon#about to write, iclass 24, count 0 2006.176.08:08:02.68#ibcon#wrote, iclass 24, count 0 2006.176.08:08:02.68#ibcon#about to read 3, iclass 24, count 0 2006.176.08:08:02.70#ibcon#read 3, iclass 24, count 0 2006.176.08:08:02.70#ibcon#about to read 4, iclass 24, count 0 2006.176.08:08:02.70#ibcon#read 4, iclass 24, count 0 2006.176.08:08:02.70#ibcon#about to read 5, iclass 24, count 0 2006.176.08:08:02.70#ibcon#read 5, iclass 24, count 0 2006.176.08:08:02.70#ibcon#about to read 6, iclass 24, count 0 2006.176.08:08:02.70#ibcon#read 6, iclass 24, count 0 2006.176.08:08:02.70#ibcon#end of sib2, iclass 24, count 0 2006.176.08:08:02.70#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:08:02.70#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:08:02.70#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:08:02.70#ibcon#*before write, iclass 24, count 0 2006.176.08:08:02.70#ibcon#enter sib2, iclass 24, count 0 2006.176.08:08:02.70#ibcon#flushed, iclass 24, count 0 2006.176.08:08:02.70#ibcon#about to write, iclass 24, count 0 2006.176.08:08:02.70#ibcon#wrote, iclass 24, count 0 2006.176.08:08:02.70#ibcon#about to read 3, iclass 24, count 0 2006.176.08:08:02.74#ibcon#read 3, iclass 24, count 0 2006.176.08:08:02.74#ibcon#about to read 4, iclass 24, count 0 2006.176.08:08:02.74#ibcon#read 4, iclass 24, count 0 2006.176.08:08:02.74#ibcon#about to read 5, iclass 24, count 0 2006.176.08:08:02.74#ibcon#read 5, iclass 24, count 0 2006.176.08:08:02.74#ibcon#about to read 6, iclass 24, count 0 2006.176.08:08:02.74#ibcon#read 6, iclass 24, count 0 2006.176.08:08:02.74#ibcon#end of sib2, iclass 24, count 0 2006.176.08:08:02.74#ibcon#*after write, iclass 24, count 0 2006.176.08:08:02.74#ibcon#*before return 0, iclass 24, count 0 2006.176.08:08:02.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:02.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:08:02.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:08:02.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:08:02.74$vc4f8/vb=6,4 2006.176.08:08:02.74#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.08:08:02.74#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.08:08:02.74#ibcon#ireg 11 cls_cnt 2 2006.176.08:08:02.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:02.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:02.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:02.80#ibcon#enter wrdev, iclass 26, count 2 2006.176.08:08:02.80#ibcon#first serial, iclass 26, count 2 2006.176.08:08:02.80#ibcon#enter sib2, iclass 26, count 2 2006.176.08:08:02.80#ibcon#flushed, iclass 26, count 2 2006.176.08:08:02.80#ibcon#about to write, iclass 26, count 2 2006.176.08:08:02.80#ibcon#wrote, iclass 26, count 2 2006.176.08:08:02.80#ibcon#about to read 3, iclass 26, count 2 2006.176.08:08:02.82#ibcon#read 3, iclass 26, count 2 2006.176.08:08:02.82#ibcon#about to read 4, iclass 26, count 2 2006.176.08:08:02.82#ibcon#read 4, iclass 26, count 2 2006.176.08:08:02.82#ibcon#about to read 5, iclass 26, count 2 2006.176.08:08:02.82#ibcon#read 5, iclass 26, count 2 2006.176.08:08:02.82#ibcon#about to read 6, iclass 26, count 2 2006.176.08:08:02.82#ibcon#read 6, iclass 26, count 2 2006.176.08:08:02.82#ibcon#end of sib2, iclass 26, count 2 2006.176.08:08:02.82#ibcon#*mode == 0, iclass 26, count 2 2006.176.08:08:02.82#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.08:08:02.82#ibcon#[27=AT06-04\r\n] 2006.176.08:08:02.82#ibcon#*before write, iclass 26, count 2 2006.176.08:08:02.82#ibcon#enter sib2, iclass 26, count 2 2006.176.08:08:02.82#ibcon#flushed, iclass 26, count 2 2006.176.08:08:02.82#ibcon#about to write, iclass 26, count 2 2006.176.08:08:02.82#ibcon#wrote, iclass 26, count 2 2006.176.08:08:02.82#ibcon#about to read 3, iclass 26, count 2 2006.176.08:08:02.85#ibcon#read 3, iclass 26, count 2 2006.176.08:08:02.85#ibcon#about to read 4, iclass 26, count 2 2006.176.08:08:02.85#ibcon#read 4, iclass 26, count 2 2006.176.08:08:02.85#ibcon#about to read 5, iclass 26, count 2 2006.176.08:08:02.85#ibcon#read 5, iclass 26, count 2 2006.176.08:08:02.85#ibcon#about to read 6, iclass 26, count 2 2006.176.08:08:02.85#ibcon#read 6, iclass 26, count 2 2006.176.08:08:02.85#ibcon#end of sib2, iclass 26, count 2 2006.176.08:08:02.85#ibcon#*after write, iclass 26, count 2 2006.176.08:08:02.85#ibcon#*before return 0, iclass 26, count 2 2006.176.08:08:02.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:02.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:08:02.85#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.08:08:02.85#ibcon#ireg 7 cls_cnt 0 2006.176.08:08:02.85#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:02.97#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:02.97#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:02.97#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:08:02.97#ibcon#first serial, iclass 26, count 0 2006.176.08:08:02.97#ibcon#enter sib2, iclass 26, count 0 2006.176.08:08:02.97#ibcon#flushed, iclass 26, count 0 2006.176.08:08:02.97#ibcon#about to write, iclass 26, count 0 2006.176.08:08:02.97#ibcon#wrote, iclass 26, count 0 2006.176.08:08:02.97#ibcon#about to read 3, iclass 26, count 0 2006.176.08:08:02.99#ibcon#read 3, iclass 26, count 0 2006.176.08:08:02.99#ibcon#about to read 4, iclass 26, count 0 2006.176.08:08:02.99#ibcon#read 4, iclass 26, count 0 2006.176.08:08:02.99#ibcon#about to read 5, iclass 26, count 0 2006.176.08:08:02.99#ibcon#read 5, iclass 26, count 0 2006.176.08:08:02.99#ibcon#about to read 6, iclass 26, count 0 2006.176.08:08:02.99#ibcon#read 6, iclass 26, count 0 2006.176.08:08:02.99#ibcon#end of sib2, iclass 26, count 0 2006.176.08:08:02.99#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:08:02.99#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:08:02.99#ibcon#[27=USB\r\n] 2006.176.08:08:02.99#ibcon#*before write, iclass 26, count 0 2006.176.08:08:02.99#ibcon#enter sib2, iclass 26, count 0 2006.176.08:08:02.99#ibcon#flushed, iclass 26, count 0 2006.176.08:08:02.99#ibcon#about to write, iclass 26, count 0 2006.176.08:08:02.99#ibcon#wrote, iclass 26, count 0 2006.176.08:08:02.99#ibcon#about to read 3, iclass 26, count 0 2006.176.08:08:03.02#ibcon#read 3, iclass 26, count 0 2006.176.08:08:03.02#ibcon#about to read 4, iclass 26, count 0 2006.176.08:08:03.02#ibcon#read 4, iclass 26, count 0 2006.176.08:08:03.02#ibcon#about to read 5, iclass 26, count 0 2006.176.08:08:03.02#ibcon#read 5, iclass 26, count 0 2006.176.08:08:03.02#ibcon#about to read 6, iclass 26, count 0 2006.176.08:08:03.02#ibcon#read 6, iclass 26, count 0 2006.176.08:08:03.02#ibcon#end of sib2, iclass 26, count 0 2006.176.08:08:03.02#ibcon#*after write, iclass 26, count 0 2006.176.08:08:03.02#ibcon#*before return 0, iclass 26, count 0 2006.176.08:08:03.02#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:03.02#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:08:03.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:08:03.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:08:03.02$vc4f8/vabw=wide 2006.176.08:08:03.02#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.08:08:03.02#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.08:08:03.02#ibcon#ireg 8 cls_cnt 0 2006.176.08:08:03.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:03.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:03.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:03.02#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:08:03.02#ibcon#first serial, iclass 28, count 0 2006.176.08:08:03.02#ibcon#enter sib2, iclass 28, count 0 2006.176.08:08:03.02#ibcon#flushed, iclass 28, count 0 2006.176.08:08:03.02#ibcon#about to write, iclass 28, count 0 2006.176.08:08:03.02#ibcon#wrote, iclass 28, count 0 2006.176.08:08:03.02#ibcon#about to read 3, iclass 28, count 0 2006.176.08:08:03.04#ibcon#read 3, iclass 28, count 0 2006.176.08:08:03.04#ibcon#about to read 4, iclass 28, count 0 2006.176.08:08:03.04#ibcon#read 4, iclass 28, count 0 2006.176.08:08:03.04#ibcon#about to read 5, iclass 28, count 0 2006.176.08:08:03.04#ibcon#read 5, iclass 28, count 0 2006.176.08:08:03.04#ibcon#about to read 6, iclass 28, count 0 2006.176.08:08:03.04#ibcon#read 6, iclass 28, count 0 2006.176.08:08:03.04#ibcon#end of sib2, iclass 28, count 0 2006.176.08:08:03.04#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:08:03.04#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:08:03.04#ibcon#[25=BW32\r\n] 2006.176.08:08:03.04#ibcon#*before write, iclass 28, count 0 2006.176.08:08:03.04#ibcon#enter sib2, iclass 28, count 0 2006.176.08:08:03.04#ibcon#flushed, iclass 28, count 0 2006.176.08:08:03.04#ibcon#about to write, iclass 28, count 0 2006.176.08:08:03.04#ibcon#wrote, iclass 28, count 0 2006.176.08:08:03.04#ibcon#about to read 3, iclass 28, count 0 2006.176.08:08:03.07#ibcon#read 3, iclass 28, count 0 2006.176.08:08:03.07#ibcon#about to read 4, iclass 28, count 0 2006.176.08:08:03.07#ibcon#read 4, iclass 28, count 0 2006.176.08:08:03.07#ibcon#about to read 5, iclass 28, count 0 2006.176.08:08:03.07#ibcon#read 5, iclass 28, count 0 2006.176.08:08:03.07#ibcon#about to read 6, iclass 28, count 0 2006.176.08:08:03.07#ibcon#read 6, iclass 28, count 0 2006.176.08:08:03.07#ibcon#end of sib2, iclass 28, count 0 2006.176.08:08:03.07#ibcon#*after write, iclass 28, count 0 2006.176.08:08:03.07#ibcon#*before return 0, iclass 28, count 0 2006.176.08:08:03.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:03.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:08:03.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:08:03.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:08:03.07$vc4f8/vbbw=wide 2006.176.08:08:03.07#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.08:08:03.07#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.08:08:03.07#ibcon#ireg 8 cls_cnt 0 2006.176.08:08:03.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:08:03.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:08:03.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:08:03.14#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:08:03.14#ibcon#first serial, iclass 30, count 0 2006.176.08:08:03.14#ibcon#enter sib2, iclass 30, count 0 2006.176.08:08:03.14#ibcon#flushed, iclass 30, count 0 2006.176.08:08:03.14#ibcon#about to write, iclass 30, count 0 2006.176.08:08:03.14#ibcon#wrote, iclass 30, count 0 2006.176.08:08:03.14#ibcon#about to read 3, iclass 30, count 0 2006.176.08:08:03.16#ibcon#read 3, iclass 30, count 0 2006.176.08:08:03.16#ibcon#about to read 4, iclass 30, count 0 2006.176.08:08:03.16#ibcon#read 4, iclass 30, count 0 2006.176.08:08:03.16#ibcon#about to read 5, iclass 30, count 0 2006.176.08:08:03.16#ibcon#read 5, iclass 30, count 0 2006.176.08:08:03.16#ibcon#about to read 6, iclass 30, count 0 2006.176.08:08:03.16#ibcon#read 6, iclass 30, count 0 2006.176.08:08:03.16#ibcon#end of sib2, iclass 30, count 0 2006.176.08:08:03.16#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:08:03.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:08:03.16#ibcon#[27=BW32\r\n] 2006.176.08:08:03.16#ibcon#*before write, iclass 30, count 0 2006.176.08:08:03.16#ibcon#enter sib2, iclass 30, count 0 2006.176.08:08:03.16#ibcon#flushed, iclass 30, count 0 2006.176.08:08:03.16#ibcon#about to write, iclass 30, count 0 2006.176.08:08:03.16#ibcon#wrote, iclass 30, count 0 2006.176.08:08:03.16#ibcon#about to read 3, iclass 30, count 0 2006.176.08:08:03.19#ibcon#read 3, iclass 30, count 0 2006.176.08:08:03.19#ibcon#about to read 4, iclass 30, count 0 2006.176.08:08:03.19#ibcon#read 4, iclass 30, count 0 2006.176.08:08:03.19#ibcon#about to read 5, iclass 30, count 0 2006.176.08:08:03.19#ibcon#read 5, iclass 30, count 0 2006.176.08:08:03.19#ibcon#about to read 6, iclass 30, count 0 2006.176.08:08:03.19#ibcon#read 6, iclass 30, count 0 2006.176.08:08:03.19#ibcon#end of sib2, iclass 30, count 0 2006.176.08:08:03.19#ibcon#*after write, iclass 30, count 0 2006.176.08:08:03.19#ibcon#*before return 0, iclass 30, count 0 2006.176.08:08:03.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:08:03.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:08:03.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:08:03.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:08:03.19$4f8m12a/ifd4f 2006.176.08:08:03.19$ifd4f/lo= 2006.176.08:08:03.19$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:08:03.19$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:08:03.19$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:08:03.19$ifd4f/patch= 2006.176.08:08:03.19$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:08:03.19$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:08:03.19$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:08:03.19$4f8m12a/"form=m,16.000,1:2 2006.176.08:08:03.19$4f8m12a/"tpicd 2006.176.08:08:03.19$4f8m12a/echo=off 2006.176.08:08:03.19$4f8m12a/xlog=off 2006.176.08:08:03.19:!2006.176.08:08:30 2006.176.08:08:16.14#trakl#Source acquired 2006.176.08:08:18.14#flagr#flagr/antenna,acquired 2006.176.08:08:30.00:preob 2006.176.08:08:31.14/onsource/TRACKING 2006.176.08:08:31.14:!2006.176.08:08:40 2006.176.08:08:40.00:data_valid=on 2006.176.08:08:40.00:midob 2006.176.08:08:40.14/onsource/TRACKING 2006.176.08:08:40.14/wx/23.85,1008.6,92 2006.176.08:08:40.26/cable/+6.4937E-03 2006.176.08:08:41.35/va/01,08,usb,yes,29,30 2006.176.08:08:41.35/va/02,07,usb,yes,29,30 2006.176.08:08:41.35/va/03,06,usb,yes,30,30 2006.176.08:08:41.35/va/04,07,usb,yes,29,32 2006.176.08:08:41.35/va/05,07,usb,yes,31,33 2006.176.08:08:41.35/va/06,06,usb,yes,30,30 2006.176.08:08:41.35/va/07,06,usb,yes,31,30 2006.176.08:08:41.35/va/08,06,usb,yes,33,32 2006.176.08:08:41.58/valo/01,532.99,yes,locked 2006.176.08:08:41.58/valo/02,572.99,yes,locked 2006.176.08:08:41.58/valo/03,672.99,yes,locked 2006.176.08:08:41.58/valo/04,832.99,yes,locked 2006.176.08:08:41.58/valo/05,652.99,yes,locked 2006.176.08:08:41.58/valo/06,772.99,yes,locked 2006.176.08:08:41.58/valo/07,832.99,yes,locked 2006.176.08:08:41.58/valo/08,852.99,yes,locked 2006.176.08:08:42.67/vb/01,04,usb,yes,29,27 2006.176.08:08:42.67/vb/02,04,usb,yes,30,32 2006.176.08:08:42.67/vb/03,04,usb,yes,27,31 2006.176.08:08:42.67/vb/04,04,usb,yes,28,28 2006.176.08:08:42.67/vb/05,04,usb,yes,26,30 2006.176.08:08:42.67/vb/06,04,usb,yes,27,30 2006.176.08:08:42.67/vb/07,04,usb,yes,29,29 2006.176.08:08:42.67/vb/08,04,usb,yes,27,30 2006.176.08:08:42.91/vblo/01,632.99,yes,locked 2006.176.08:08:42.91/vblo/02,640.99,yes,locked 2006.176.08:08:42.91/vblo/03,656.99,yes,locked 2006.176.08:08:42.91/vblo/04,712.99,yes,locked 2006.176.08:08:42.91/vblo/05,744.99,yes,locked 2006.176.08:08:42.91/vblo/06,752.99,yes,locked 2006.176.08:08:42.91/vblo/07,734.99,yes,locked 2006.176.08:08:42.91/vblo/08,744.99,yes,locked 2006.176.08:08:43.06/vabw/8 2006.176.08:08:43.21/vbbw/8 2006.176.08:08:43.32/xfe/off,on,16.0 2006.176.08:08:43.70/ifatt/23,28,28,28 2006.176.08:08:44.07/fmout-gps/S +3.71E-07 2006.176.08:08:44.15:!2006.176.08:09:40 2006.176.08:09:40.00:data_valid=off 2006.176.08:09:40.00:postob 2006.176.08:09:40.13/cable/+6.4945E-03 2006.176.08:09:40.13/wx/23.85,1008.6,92 2006.176.08:09:41.07/fmout-gps/S +3.70E-07 2006.176.08:09:41.07:scan_name=176-0810,k06176,60 2006.176.08:09:41.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.176.08:09:41.14#flagr#flagr/antenna,new-source 2006.176.08:09:42.14:checkk5 2006.176.08:09:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:09:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:09:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:09:43.83/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:09:44.19/chk_obsdata//k5ts1/T1760808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:09:44.57/chk_obsdata//k5ts2/T1760808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:09:44.93/chk_obsdata//k5ts3/T1760808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:09:45.32/chk_obsdata//k5ts4/T1760808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:09:46.00/k5log//k5ts1_log_newline 2006.176.08:09:46.69/k5log//k5ts2_log_newline 2006.176.08:09:47.38/k5log//k5ts3_log_newline 2006.176.08:09:48.07/k5log//k5ts4_log_newline 2006.176.08:09:48.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:09:48.10:4f8m12a=2 2006.176.08:09:48.10$4f8m12a/echo=on 2006.176.08:09:48.10$4f8m12a/pcalon 2006.176.08:09:48.10$pcalon/"no phase cal control is implemented here 2006.176.08:09:48.10$4f8m12a/"tpicd=stop 2006.176.08:09:48.10$4f8m12a/vc4f8 2006.176.08:09:48.10$vc4f8/valo=1,532.99 2006.176.08:09:48.10#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.176.08:09:48.10#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.176.08:09:48.10#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:48.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:48.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:48.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:48.10#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:09:48.10#ibcon#first serial, iclass 37, count 0 2006.176.08:09:48.10#ibcon#enter sib2, iclass 37, count 0 2006.176.08:09:48.10#ibcon#flushed, iclass 37, count 0 2006.176.08:09:48.10#ibcon#about to write, iclass 37, count 0 2006.176.08:09:48.10#ibcon#wrote, iclass 37, count 0 2006.176.08:09:48.10#ibcon#about to read 3, iclass 37, count 0 2006.176.08:09:48.14#ibcon#read 3, iclass 37, count 0 2006.176.08:09:48.14#ibcon#about to read 4, iclass 37, count 0 2006.176.08:09:48.14#ibcon#read 4, iclass 37, count 0 2006.176.08:09:48.14#ibcon#about to read 5, iclass 37, count 0 2006.176.08:09:48.14#ibcon#read 5, iclass 37, count 0 2006.176.08:09:48.14#ibcon#about to read 6, iclass 37, count 0 2006.176.08:09:48.14#ibcon#read 6, iclass 37, count 0 2006.176.08:09:48.14#ibcon#end of sib2, iclass 37, count 0 2006.176.08:09:48.14#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:09:48.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:09:48.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:09:48.14#ibcon#*before write, iclass 37, count 0 2006.176.08:09:48.14#ibcon#enter sib2, iclass 37, count 0 2006.176.08:09:48.15#ibcon#flushed, iclass 37, count 0 2006.176.08:09:48.15#ibcon#about to write, iclass 37, count 0 2006.176.08:09:48.15#ibcon#wrote, iclass 37, count 0 2006.176.08:09:48.15#ibcon#about to read 3, iclass 37, count 0 2006.176.08:09:48.19#ibcon#read 3, iclass 37, count 0 2006.176.08:09:48.19#ibcon#about to read 4, iclass 37, count 0 2006.176.08:09:48.19#ibcon#read 4, iclass 37, count 0 2006.176.08:09:48.19#ibcon#about to read 5, iclass 37, count 0 2006.176.08:09:48.19#ibcon#read 5, iclass 37, count 0 2006.176.08:09:48.19#ibcon#about to read 6, iclass 37, count 0 2006.176.08:09:48.19#ibcon#read 6, iclass 37, count 0 2006.176.08:09:48.19#ibcon#end of sib2, iclass 37, count 0 2006.176.08:09:48.19#ibcon#*after write, iclass 37, count 0 2006.176.08:09:48.19#ibcon#*before return 0, iclass 37, count 0 2006.176.08:09:48.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:48.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:48.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:09:48.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:09:48.19$vc4f8/va=1,8 2006.176.08:09:48.19#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.176.08:09:48.19#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.176.08:09:48.19#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:48.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:48.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:48.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:48.19#ibcon#enter wrdev, iclass 39, count 2 2006.176.08:09:48.19#ibcon#first serial, iclass 39, count 2 2006.176.08:09:48.19#ibcon#enter sib2, iclass 39, count 2 2006.176.08:09:48.19#ibcon#flushed, iclass 39, count 2 2006.176.08:09:48.19#ibcon#about to write, iclass 39, count 2 2006.176.08:09:48.19#ibcon#wrote, iclass 39, count 2 2006.176.08:09:48.19#ibcon#about to read 3, iclass 39, count 2 2006.176.08:09:48.21#ibcon#read 3, iclass 39, count 2 2006.176.08:09:48.21#ibcon#about to read 4, iclass 39, count 2 2006.176.08:09:48.21#ibcon#read 4, iclass 39, count 2 2006.176.08:09:48.21#ibcon#about to read 5, iclass 39, count 2 2006.176.08:09:48.21#ibcon#read 5, iclass 39, count 2 2006.176.08:09:48.21#ibcon#about to read 6, iclass 39, count 2 2006.176.08:09:48.21#ibcon#read 6, iclass 39, count 2 2006.176.08:09:48.21#ibcon#end of sib2, iclass 39, count 2 2006.176.08:09:48.21#ibcon#*mode == 0, iclass 39, count 2 2006.176.08:09:48.21#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.176.08:09:48.21#ibcon#[25=AT01-08\r\n] 2006.176.08:09:48.21#ibcon#*before write, iclass 39, count 2 2006.176.08:09:48.21#ibcon#enter sib2, iclass 39, count 2 2006.176.08:09:48.21#ibcon#flushed, iclass 39, count 2 2006.176.08:09:48.21#ibcon#about to write, iclass 39, count 2 2006.176.08:09:48.21#ibcon#wrote, iclass 39, count 2 2006.176.08:09:48.21#ibcon#about to read 3, iclass 39, count 2 2006.176.08:09:48.24#ibcon#read 3, iclass 39, count 2 2006.176.08:09:48.24#ibcon#about to read 4, iclass 39, count 2 2006.176.08:09:48.24#ibcon#read 4, iclass 39, count 2 2006.176.08:09:48.24#ibcon#about to read 5, iclass 39, count 2 2006.176.08:09:48.24#ibcon#read 5, iclass 39, count 2 2006.176.08:09:48.24#ibcon#about to read 6, iclass 39, count 2 2006.176.08:09:48.24#ibcon#read 6, iclass 39, count 2 2006.176.08:09:48.24#ibcon#end of sib2, iclass 39, count 2 2006.176.08:09:48.24#ibcon#*after write, iclass 39, count 2 2006.176.08:09:48.24#ibcon#*before return 0, iclass 39, count 2 2006.176.08:09:48.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:48.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:48.24#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.176.08:09:48.24#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:48.24#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:48.36#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:48.36#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:48.36#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:09:48.36#ibcon#first serial, iclass 39, count 0 2006.176.08:09:48.36#ibcon#enter sib2, iclass 39, count 0 2006.176.08:09:48.36#ibcon#flushed, iclass 39, count 0 2006.176.08:09:48.36#ibcon#about to write, iclass 39, count 0 2006.176.08:09:48.36#ibcon#wrote, iclass 39, count 0 2006.176.08:09:48.36#ibcon#about to read 3, iclass 39, count 0 2006.176.08:09:48.38#ibcon#read 3, iclass 39, count 0 2006.176.08:09:48.38#ibcon#about to read 4, iclass 39, count 0 2006.176.08:09:48.38#ibcon#read 4, iclass 39, count 0 2006.176.08:09:48.38#ibcon#about to read 5, iclass 39, count 0 2006.176.08:09:48.38#ibcon#read 5, iclass 39, count 0 2006.176.08:09:48.38#ibcon#about to read 6, iclass 39, count 0 2006.176.08:09:48.38#ibcon#read 6, iclass 39, count 0 2006.176.08:09:48.38#ibcon#end of sib2, iclass 39, count 0 2006.176.08:09:48.38#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:09:48.38#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:09:48.38#ibcon#[25=USB\r\n] 2006.176.08:09:48.38#ibcon#*before write, iclass 39, count 0 2006.176.08:09:48.38#ibcon#enter sib2, iclass 39, count 0 2006.176.08:09:48.38#ibcon#flushed, iclass 39, count 0 2006.176.08:09:48.38#ibcon#about to write, iclass 39, count 0 2006.176.08:09:48.38#ibcon#wrote, iclass 39, count 0 2006.176.08:09:48.38#ibcon#about to read 3, iclass 39, count 0 2006.176.08:09:48.42#ibcon#read 3, iclass 39, count 0 2006.176.08:09:48.42#ibcon#about to read 4, iclass 39, count 0 2006.176.08:09:48.42#ibcon#read 4, iclass 39, count 0 2006.176.08:09:48.42#ibcon#about to read 5, iclass 39, count 0 2006.176.08:09:48.42#ibcon#read 5, iclass 39, count 0 2006.176.08:09:48.42#ibcon#about to read 6, iclass 39, count 0 2006.176.08:09:48.42#ibcon#read 6, iclass 39, count 0 2006.176.08:09:48.42#ibcon#end of sib2, iclass 39, count 0 2006.176.08:09:48.42#ibcon#*after write, iclass 39, count 0 2006.176.08:09:48.42#ibcon#*before return 0, iclass 39, count 0 2006.176.08:09:48.42#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:48.42#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:48.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:09:48.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:09:48.42$vc4f8/valo=2,572.99 2006.176.08:09:48.42#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.08:09:48.42#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.08:09:48.42#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:48.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:48.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:48.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:48.42#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:09:48.42#ibcon#first serial, iclass 3, count 0 2006.176.08:09:48.42#ibcon#enter sib2, iclass 3, count 0 2006.176.08:09:48.42#ibcon#flushed, iclass 3, count 0 2006.176.08:09:48.42#ibcon#about to write, iclass 3, count 0 2006.176.08:09:48.42#ibcon#wrote, iclass 3, count 0 2006.176.08:09:48.42#ibcon#about to read 3, iclass 3, count 0 2006.176.08:09:48.43#ibcon#read 3, iclass 3, count 0 2006.176.08:09:48.43#ibcon#about to read 4, iclass 3, count 0 2006.176.08:09:48.43#ibcon#read 4, iclass 3, count 0 2006.176.08:09:48.43#ibcon#about to read 5, iclass 3, count 0 2006.176.08:09:48.43#ibcon#read 5, iclass 3, count 0 2006.176.08:09:48.43#ibcon#about to read 6, iclass 3, count 0 2006.176.08:09:48.43#ibcon#read 6, iclass 3, count 0 2006.176.08:09:48.43#ibcon#end of sib2, iclass 3, count 0 2006.176.08:09:48.43#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:09:48.43#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:09:48.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:09:48.43#ibcon#*before write, iclass 3, count 0 2006.176.08:09:48.43#ibcon#enter sib2, iclass 3, count 0 2006.176.08:09:48.43#ibcon#flushed, iclass 3, count 0 2006.176.08:09:48.43#ibcon#about to write, iclass 3, count 0 2006.176.08:09:48.43#ibcon#wrote, iclass 3, count 0 2006.176.08:09:48.43#ibcon#about to read 3, iclass 3, count 0 2006.176.08:09:48.47#ibcon#read 3, iclass 3, count 0 2006.176.08:09:48.47#ibcon#about to read 4, iclass 3, count 0 2006.176.08:09:48.47#ibcon#read 4, iclass 3, count 0 2006.176.08:09:48.47#ibcon#about to read 5, iclass 3, count 0 2006.176.08:09:48.47#ibcon#read 5, iclass 3, count 0 2006.176.08:09:48.47#ibcon#about to read 6, iclass 3, count 0 2006.176.08:09:48.47#ibcon#read 6, iclass 3, count 0 2006.176.08:09:48.47#ibcon#end of sib2, iclass 3, count 0 2006.176.08:09:48.47#ibcon#*after write, iclass 3, count 0 2006.176.08:09:48.47#ibcon#*before return 0, iclass 3, count 0 2006.176.08:09:48.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:48.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:48.47#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:09:48.47#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:09:48.47$vc4f8/va=2,7 2006.176.08:09:48.47#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.176.08:09:48.47#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.176.08:09:48.47#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:48.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:48.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:48.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:48.54#ibcon#enter wrdev, iclass 5, count 2 2006.176.08:09:48.54#ibcon#first serial, iclass 5, count 2 2006.176.08:09:48.54#ibcon#enter sib2, iclass 5, count 2 2006.176.08:09:48.54#ibcon#flushed, iclass 5, count 2 2006.176.08:09:48.54#ibcon#about to write, iclass 5, count 2 2006.176.08:09:48.54#ibcon#wrote, iclass 5, count 2 2006.176.08:09:48.54#ibcon#about to read 3, iclass 5, count 2 2006.176.08:09:48.56#ibcon#read 3, iclass 5, count 2 2006.176.08:09:48.56#ibcon#about to read 4, iclass 5, count 2 2006.176.08:09:48.56#ibcon#read 4, iclass 5, count 2 2006.176.08:09:48.56#ibcon#about to read 5, iclass 5, count 2 2006.176.08:09:48.56#ibcon#read 5, iclass 5, count 2 2006.176.08:09:48.56#ibcon#about to read 6, iclass 5, count 2 2006.176.08:09:48.56#ibcon#read 6, iclass 5, count 2 2006.176.08:09:48.56#ibcon#end of sib2, iclass 5, count 2 2006.176.08:09:48.56#ibcon#*mode == 0, iclass 5, count 2 2006.176.08:09:48.56#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.176.08:09:48.56#ibcon#[25=AT02-07\r\n] 2006.176.08:09:48.56#ibcon#*before write, iclass 5, count 2 2006.176.08:09:48.56#ibcon#enter sib2, iclass 5, count 2 2006.176.08:09:48.56#ibcon#flushed, iclass 5, count 2 2006.176.08:09:48.56#ibcon#about to write, iclass 5, count 2 2006.176.08:09:48.56#ibcon#wrote, iclass 5, count 2 2006.176.08:09:48.56#ibcon#about to read 3, iclass 5, count 2 2006.176.08:09:48.59#ibcon#read 3, iclass 5, count 2 2006.176.08:09:48.59#ibcon#about to read 4, iclass 5, count 2 2006.176.08:09:48.59#ibcon#read 4, iclass 5, count 2 2006.176.08:09:48.59#ibcon#about to read 5, iclass 5, count 2 2006.176.08:09:48.59#ibcon#read 5, iclass 5, count 2 2006.176.08:09:48.59#ibcon#about to read 6, iclass 5, count 2 2006.176.08:09:48.59#ibcon#read 6, iclass 5, count 2 2006.176.08:09:48.59#ibcon#end of sib2, iclass 5, count 2 2006.176.08:09:48.59#ibcon#*after write, iclass 5, count 2 2006.176.08:09:48.59#ibcon#*before return 0, iclass 5, count 2 2006.176.08:09:48.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:48.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:48.59#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.176.08:09:48.59#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:48.59#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:48.71#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:48.71#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:48.71#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:09:48.71#ibcon#first serial, iclass 5, count 0 2006.176.08:09:48.71#ibcon#enter sib2, iclass 5, count 0 2006.176.08:09:48.71#ibcon#flushed, iclass 5, count 0 2006.176.08:09:48.71#ibcon#about to write, iclass 5, count 0 2006.176.08:09:48.71#ibcon#wrote, iclass 5, count 0 2006.176.08:09:48.71#ibcon#about to read 3, iclass 5, count 0 2006.176.08:09:48.73#ibcon#read 3, iclass 5, count 0 2006.176.08:09:48.73#ibcon#about to read 4, iclass 5, count 0 2006.176.08:09:48.74#ibcon#read 4, iclass 5, count 0 2006.176.08:09:48.74#ibcon#about to read 5, iclass 5, count 0 2006.176.08:09:48.74#ibcon#read 5, iclass 5, count 0 2006.176.08:09:48.74#ibcon#about to read 6, iclass 5, count 0 2006.176.08:09:48.74#ibcon#read 6, iclass 5, count 0 2006.176.08:09:48.74#ibcon#end of sib2, iclass 5, count 0 2006.176.08:09:48.74#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:09:48.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:09:48.74#ibcon#[25=USB\r\n] 2006.176.08:09:48.74#ibcon#*before write, iclass 5, count 0 2006.176.08:09:48.74#ibcon#enter sib2, iclass 5, count 0 2006.176.08:09:48.74#ibcon#flushed, iclass 5, count 0 2006.176.08:09:48.74#ibcon#about to write, iclass 5, count 0 2006.176.08:09:48.74#ibcon#wrote, iclass 5, count 0 2006.176.08:09:48.74#ibcon#about to read 3, iclass 5, count 0 2006.176.08:09:48.76#ibcon#read 3, iclass 5, count 0 2006.176.08:09:48.76#ibcon#about to read 4, iclass 5, count 0 2006.176.08:09:48.76#ibcon#read 4, iclass 5, count 0 2006.176.08:09:48.76#ibcon#about to read 5, iclass 5, count 0 2006.176.08:09:48.76#ibcon#read 5, iclass 5, count 0 2006.176.08:09:48.76#ibcon#about to read 6, iclass 5, count 0 2006.176.08:09:48.76#ibcon#read 6, iclass 5, count 0 2006.176.08:09:48.76#ibcon#end of sib2, iclass 5, count 0 2006.176.08:09:48.76#ibcon#*after write, iclass 5, count 0 2006.176.08:09:48.76#ibcon#*before return 0, iclass 5, count 0 2006.176.08:09:48.76#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:48.76#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:48.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:09:48.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:09:48.76$vc4f8/valo=3,672.99 2006.176.08:09:48.76#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.08:09:48.76#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.08:09:48.76#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:48.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:48.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:48.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:48.76#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:09:48.76#ibcon#first serial, iclass 7, count 0 2006.176.08:09:48.76#ibcon#enter sib2, iclass 7, count 0 2006.176.08:09:48.76#ibcon#flushed, iclass 7, count 0 2006.176.08:09:48.76#ibcon#about to write, iclass 7, count 0 2006.176.08:09:48.76#ibcon#wrote, iclass 7, count 0 2006.176.08:09:48.76#ibcon#about to read 3, iclass 7, count 0 2006.176.08:09:48.78#ibcon#read 3, iclass 7, count 0 2006.176.08:09:48.78#ibcon#about to read 4, iclass 7, count 0 2006.176.08:09:48.78#ibcon#read 4, iclass 7, count 0 2006.176.08:09:48.78#ibcon#about to read 5, iclass 7, count 0 2006.176.08:09:48.78#ibcon#read 5, iclass 7, count 0 2006.176.08:09:48.78#ibcon#about to read 6, iclass 7, count 0 2006.176.08:09:48.78#ibcon#read 6, iclass 7, count 0 2006.176.08:09:48.78#ibcon#end of sib2, iclass 7, count 0 2006.176.08:09:48.78#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:09:48.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:09:48.78#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:09:48.78#ibcon#*before write, iclass 7, count 0 2006.176.08:09:48.78#ibcon#enter sib2, iclass 7, count 0 2006.176.08:09:48.78#ibcon#flushed, iclass 7, count 0 2006.176.08:09:48.78#ibcon#about to write, iclass 7, count 0 2006.176.08:09:48.78#ibcon#wrote, iclass 7, count 0 2006.176.08:09:48.78#ibcon#about to read 3, iclass 7, count 0 2006.176.08:09:48.82#ibcon#read 3, iclass 7, count 0 2006.176.08:09:48.82#ibcon#about to read 4, iclass 7, count 0 2006.176.08:09:48.82#ibcon#read 4, iclass 7, count 0 2006.176.08:09:48.82#ibcon#about to read 5, iclass 7, count 0 2006.176.08:09:48.82#ibcon#read 5, iclass 7, count 0 2006.176.08:09:48.82#ibcon#about to read 6, iclass 7, count 0 2006.176.08:09:48.82#ibcon#read 6, iclass 7, count 0 2006.176.08:09:48.82#ibcon#end of sib2, iclass 7, count 0 2006.176.08:09:48.82#ibcon#*after write, iclass 7, count 0 2006.176.08:09:48.82#ibcon#*before return 0, iclass 7, count 0 2006.176.08:09:48.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:48.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:48.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:09:48.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:09:48.82$vc4f8/va=3,6 2006.176.08:09:48.82#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.176.08:09:48.82#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.176.08:09:48.82#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:48.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:48.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:48.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:48.88#ibcon#enter wrdev, iclass 11, count 2 2006.176.08:09:48.88#ibcon#first serial, iclass 11, count 2 2006.176.08:09:48.88#ibcon#enter sib2, iclass 11, count 2 2006.176.08:09:48.88#ibcon#flushed, iclass 11, count 2 2006.176.08:09:48.88#ibcon#about to write, iclass 11, count 2 2006.176.08:09:48.88#ibcon#wrote, iclass 11, count 2 2006.176.08:09:48.88#ibcon#about to read 3, iclass 11, count 2 2006.176.08:09:48.90#ibcon#read 3, iclass 11, count 2 2006.176.08:09:48.90#ibcon#about to read 4, iclass 11, count 2 2006.176.08:09:48.90#ibcon#read 4, iclass 11, count 2 2006.176.08:09:48.90#ibcon#about to read 5, iclass 11, count 2 2006.176.08:09:48.90#ibcon#read 5, iclass 11, count 2 2006.176.08:09:48.90#ibcon#about to read 6, iclass 11, count 2 2006.176.08:09:48.90#ibcon#read 6, iclass 11, count 2 2006.176.08:09:48.90#ibcon#end of sib2, iclass 11, count 2 2006.176.08:09:48.90#ibcon#*mode == 0, iclass 11, count 2 2006.176.08:09:48.90#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.176.08:09:48.90#ibcon#[25=AT03-06\r\n] 2006.176.08:09:48.90#ibcon#*before write, iclass 11, count 2 2006.176.08:09:48.90#ibcon#enter sib2, iclass 11, count 2 2006.176.08:09:48.90#ibcon#flushed, iclass 11, count 2 2006.176.08:09:48.90#ibcon#about to write, iclass 11, count 2 2006.176.08:09:48.90#ibcon#wrote, iclass 11, count 2 2006.176.08:09:48.90#ibcon#about to read 3, iclass 11, count 2 2006.176.08:09:48.93#ibcon#read 3, iclass 11, count 2 2006.176.08:09:48.93#ibcon#about to read 4, iclass 11, count 2 2006.176.08:09:48.93#ibcon#read 4, iclass 11, count 2 2006.176.08:09:48.93#ibcon#about to read 5, iclass 11, count 2 2006.176.08:09:48.93#ibcon#read 5, iclass 11, count 2 2006.176.08:09:48.93#ibcon#about to read 6, iclass 11, count 2 2006.176.08:09:48.93#ibcon#read 6, iclass 11, count 2 2006.176.08:09:48.93#ibcon#end of sib2, iclass 11, count 2 2006.176.08:09:48.93#ibcon#*after write, iclass 11, count 2 2006.176.08:09:48.93#ibcon#*before return 0, iclass 11, count 2 2006.176.08:09:48.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:48.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:48.93#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.176.08:09:48.93#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:48.93#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:49.05#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:49.05#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:49.05#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:09:49.05#ibcon#first serial, iclass 11, count 0 2006.176.08:09:49.05#ibcon#enter sib2, iclass 11, count 0 2006.176.08:09:49.05#ibcon#flushed, iclass 11, count 0 2006.176.08:09:49.05#ibcon#about to write, iclass 11, count 0 2006.176.08:09:49.05#ibcon#wrote, iclass 11, count 0 2006.176.08:09:49.05#ibcon#about to read 3, iclass 11, count 0 2006.176.08:09:49.07#ibcon#read 3, iclass 11, count 0 2006.176.08:09:49.07#ibcon#about to read 4, iclass 11, count 0 2006.176.08:09:49.07#ibcon#read 4, iclass 11, count 0 2006.176.08:09:49.07#ibcon#about to read 5, iclass 11, count 0 2006.176.08:09:49.07#ibcon#read 5, iclass 11, count 0 2006.176.08:09:49.07#ibcon#about to read 6, iclass 11, count 0 2006.176.08:09:49.07#ibcon#read 6, iclass 11, count 0 2006.176.08:09:49.07#ibcon#end of sib2, iclass 11, count 0 2006.176.08:09:49.07#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:09:49.07#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:09:49.07#ibcon#[25=USB\r\n] 2006.176.08:09:49.07#ibcon#*before write, iclass 11, count 0 2006.176.08:09:49.07#ibcon#enter sib2, iclass 11, count 0 2006.176.08:09:49.07#ibcon#flushed, iclass 11, count 0 2006.176.08:09:49.07#ibcon#about to write, iclass 11, count 0 2006.176.08:09:49.07#ibcon#wrote, iclass 11, count 0 2006.176.08:09:49.07#ibcon#about to read 3, iclass 11, count 0 2006.176.08:09:49.10#ibcon#read 3, iclass 11, count 0 2006.176.08:09:49.10#ibcon#about to read 4, iclass 11, count 0 2006.176.08:09:49.10#ibcon#read 4, iclass 11, count 0 2006.176.08:09:49.10#ibcon#about to read 5, iclass 11, count 0 2006.176.08:09:49.10#ibcon#read 5, iclass 11, count 0 2006.176.08:09:49.10#ibcon#about to read 6, iclass 11, count 0 2006.176.08:09:49.10#ibcon#read 6, iclass 11, count 0 2006.176.08:09:49.10#ibcon#end of sib2, iclass 11, count 0 2006.176.08:09:49.10#ibcon#*after write, iclass 11, count 0 2006.176.08:09:49.10#ibcon#*before return 0, iclass 11, count 0 2006.176.08:09:49.10#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:49.10#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:49.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:09:49.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:09:49.10$vc4f8/valo=4,832.99 2006.176.08:09:49.10#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.08:09:49.10#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.08:09:49.10#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:49.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:49.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:49.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:49.10#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:09:49.10#ibcon#first serial, iclass 13, count 0 2006.176.08:09:49.10#ibcon#enter sib2, iclass 13, count 0 2006.176.08:09:49.10#ibcon#flushed, iclass 13, count 0 2006.176.08:09:49.10#ibcon#about to write, iclass 13, count 0 2006.176.08:09:49.10#ibcon#wrote, iclass 13, count 0 2006.176.08:09:49.10#ibcon#about to read 3, iclass 13, count 0 2006.176.08:09:49.12#ibcon#read 3, iclass 13, count 0 2006.176.08:09:49.12#ibcon#about to read 4, iclass 13, count 0 2006.176.08:09:49.12#ibcon#read 4, iclass 13, count 0 2006.176.08:09:49.12#ibcon#about to read 5, iclass 13, count 0 2006.176.08:09:49.12#ibcon#read 5, iclass 13, count 0 2006.176.08:09:49.12#ibcon#about to read 6, iclass 13, count 0 2006.176.08:09:49.12#ibcon#read 6, iclass 13, count 0 2006.176.08:09:49.12#ibcon#end of sib2, iclass 13, count 0 2006.176.08:09:49.12#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:09:49.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:09:49.12#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:09:49.12#ibcon#*before write, iclass 13, count 0 2006.176.08:09:49.12#ibcon#enter sib2, iclass 13, count 0 2006.176.08:09:49.12#ibcon#flushed, iclass 13, count 0 2006.176.08:09:49.12#ibcon#about to write, iclass 13, count 0 2006.176.08:09:49.12#ibcon#wrote, iclass 13, count 0 2006.176.08:09:49.12#ibcon#about to read 3, iclass 13, count 0 2006.176.08:09:49.16#ibcon#read 3, iclass 13, count 0 2006.176.08:09:49.16#ibcon#about to read 4, iclass 13, count 0 2006.176.08:09:49.16#ibcon#read 4, iclass 13, count 0 2006.176.08:09:49.16#ibcon#about to read 5, iclass 13, count 0 2006.176.08:09:49.16#ibcon#read 5, iclass 13, count 0 2006.176.08:09:49.16#ibcon#about to read 6, iclass 13, count 0 2006.176.08:09:49.16#ibcon#read 6, iclass 13, count 0 2006.176.08:09:49.16#ibcon#end of sib2, iclass 13, count 0 2006.176.08:09:49.16#ibcon#*after write, iclass 13, count 0 2006.176.08:09:49.16#ibcon#*before return 0, iclass 13, count 0 2006.176.08:09:49.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:49.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:49.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:09:49.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:09:49.16$vc4f8/va=4,7 2006.176.08:09:49.16#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.176.08:09:49.16#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.176.08:09:49.16#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:49.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:49.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:49.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:49.22#ibcon#enter wrdev, iclass 15, count 2 2006.176.08:09:49.22#ibcon#first serial, iclass 15, count 2 2006.176.08:09:49.22#ibcon#enter sib2, iclass 15, count 2 2006.176.08:09:49.22#ibcon#flushed, iclass 15, count 2 2006.176.08:09:49.22#ibcon#about to write, iclass 15, count 2 2006.176.08:09:49.22#ibcon#wrote, iclass 15, count 2 2006.176.08:09:49.22#ibcon#about to read 3, iclass 15, count 2 2006.176.08:09:49.24#ibcon#read 3, iclass 15, count 2 2006.176.08:09:49.24#ibcon#about to read 4, iclass 15, count 2 2006.176.08:09:49.24#ibcon#read 4, iclass 15, count 2 2006.176.08:09:49.24#ibcon#about to read 5, iclass 15, count 2 2006.176.08:09:49.24#ibcon#read 5, iclass 15, count 2 2006.176.08:09:49.24#ibcon#about to read 6, iclass 15, count 2 2006.176.08:09:49.24#ibcon#read 6, iclass 15, count 2 2006.176.08:09:49.24#ibcon#end of sib2, iclass 15, count 2 2006.176.08:09:49.24#ibcon#*mode == 0, iclass 15, count 2 2006.176.08:09:49.24#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.176.08:09:49.24#ibcon#[25=AT04-07\r\n] 2006.176.08:09:49.24#ibcon#*before write, iclass 15, count 2 2006.176.08:09:49.24#ibcon#enter sib2, iclass 15, count 2 2006.176.08:09:49.24#ibcon#flushed, iclass 15, count 2 2006.176.08:09:49.24#ibcon#about to write, iclass 15, count 2 2006.176.08:09:49.24#ibcon#wrote, iclass 15, count 2 2006.176.08:09:49.24#ibcon#about to read 3, iclass 15, count 2 2006.176.08:09:49.27#ibcon#read 3, iclass 15, count 2 2006.176.08:09:49.27#ibcon#about to read 4, iclass 15, count 2 2006.176.08:09:49.27#ibcon#read 4, iclass 15, count 2 2006.176.08:09:49.27#ibcon#about to read 5, iclass 15, count 2 2006.176.08:09:49.27#ibcon#read 5, iclass 15, count 2 2006.176.08:09:49.27#ibcon#about to read 6, iclass 15, count 2 2006.176.08:09:49.27#ibcon#read 6, iclass 15, count 2 2006.176.08:09:49.27#ibcon#end of sib2, iclass 15, count 2 2006.176.08:09:49.27#ibcon#*after write, iclass 15, count 2 2006.176.08:09:49.27#ibcon#*before return 0, iclass 15, count 2 2006.176.08:09:49.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:49.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:49.27#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.176.08:09:49.27#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:49.27#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:49.39#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:49.39#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:49.39#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:09:49.39#ibcon#first serial, iclass 15, count 0 2006.176.08:09:49.39#ibcon#enter sib2, iclass 15, count 0 2006.176.08:09:49.39#ibcon#flushed, iclass 15, count 0 2006.176.08:09:49.39#ibcon#about to write, iclass 15, count 0 2006.176.08:09:49.39#ibcon#wrote, iclass 15, count 0 2006.176.08:09:49.39#ibcon#about to read 3, iclass 15, count 0 2006.176.08:09:49.41#ibcon#read 3, iclass 15, count 0 2006.176.08:09:49.41#ibcon#about to read 4, iclass 15, count 0 2006.176.08:09:49.41#ibcon#read 4, iclass 15, count 0 2006.176.08:09:49.41#ibcon#about to read 5, iclass 15, count 0 2006.176.08:09:49.41#ibcon#read 5, iclass 15, count 0 2006.176.08:09:49.41#ibcon#about to read 6, iclass 15, count 0 2006.176.08:09:49.41#ibcon#read 6, iclass 15, count 0 2006.176.08:09:49.41#ibcon#end of sib2, iclass 15, count 0 2006.176.08:09:49.41#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:09:49.41#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:09:49.41#ibcon#[25=USB\r\n] 2006.176.08:09:49.41#ibcon#*before write, iclass 15, count 0 2006.176.08:09:49.41#ibcon#enter sib2, iclass 15, count 0 2006.176.08:09:49.41#ibcon#flushed, iclass 15, count 0 2006.176.08:09:49.41#ibcon#about to write, iclass 15, count 0 2006.176.08:09:49.41#ibcon#wrote, iclass 15, count 0 2006.176.08:09:49.41#ibcon#about to read 3, iclass 15, count 0 2006.176.08:09:49.44#ibcon#read 3, iclass 15, count 0 2006.176.08:09:49.44#ibcon#about to read 4, iclass 15, count 0 2006.176.08:09:49.44#ibcon#read 4, iclass 15, count 0 2006.176.08:09:49.44#ibcon#about to read 5, iclass 15, count 0 2006.176.08:09:49.44#ibcon#read 5, iclass 15, count 0 2006.176.08:09:49.44#ibcon#about to read 6, iclass 15, count 0 2006.176.08:09:49.44#ibcon#read 6, iclass 15, count 0 2006.176.08:09:49.44#ibcon#end of sib2, iclass 15, count 0 2006.176.08:09:49.44#ibcon#*after write, iclass 15, count 0 2006.176.08:09:49.44#ibcon#*before return 0, iclass 15, count 0 2006.176.08:09:49.44#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:49.44#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:49.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:09:49.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:09:49.44$vc4f8/valo=5,652.99 2006.176.08:09:49.44#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.08:09:49.44#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.08:09:49.44#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:49.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:49.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:49.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:49.44#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:09:49.44#ibcon#first serial, iclass 17, count 0 2006.176.08:09:49.44#ibcon#enter sib2, iclass 17, count 0 2006.176.08:09:49.44#ibcon#flushed, iclass 17, count 0 2006.176.08:09:49.44#ibcon#about to write, iclass 17, count 0 2006.176.08:09:49.44#ibcon#wrote, iclass 17, count 0 2006.176.08:09:49.44#ibcon#about to read 3, iclass 17, count 0 2006.176.08:09:49.46#ibcon#read 3, iclass 17, count 0 2006.176.08:09:49.46#ibcon#about to read 4, iclass 17, count 0 2006.176.08:09:49.46#ibcon#read 4, iclass 17, count 0 2006.176.08:09:49.46#ibcon#about to read 5, iclass 17, count 0 2006.176.08:09:49.46#ibcon#read 5, iclass 17, count 0 2006.176.08:09:49.46#ibcon#about to read 6, iclass 17, count 0 2006.176.08:09:49.46#ibcon#read 6, iclass 17, count 0 2006.176.08:09:49.46#ibcon#end of sib2, iclass 17, count 0 2006.176.08:09:49.46#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:09:49.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:09:49.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:09:49.46#ibcon#*before write, iclass 17, count 0 2006.176.08:09:49.46#ibcon#enter sib2, iclass 17, count 0 2006.176.08:09:49.46#ibcon#flushed, iclass 17, count 0 2006.176.08:09:49.46#ibcon#about to write, iclass 17, count 0 2006.176.08:09:49.46#ibcon#wrote, iclass 17, count 0 2006.176.08:09:49.46#ibcon#about to read 3, iclass 17, count 0 2006.176.08:09:49.50#ibcon#read 3, iclass 17, count 0 2006.176.08:09:49.50#ibcon#about to read 4, iclass 17, count 0 2006.176.08:09:49.50#ibcon#read 4, iclass 17, count 0 2006.176.08:09:49.50#ibcon#about to read 5, iclass 17, count 0 2006.176.08:09:49.50#ibcon#read 5, iclass 17, count 0 2006.176.08:09:49.50#ibcon#about to read 6, iclass 17, count 0 2006.176.08:09:49.50#ibcon#read 6, iclass 17, count 0 2006.176.08:09:49.50#ibcon#end of sib2, iclass 17, count 0 2006.176.08:09:49.50#ibcon#*after write, iclass 17, count 0 2006.176.08:09:49.50#ibcon#*before return 0, iclass 17, count 0 2006.176.08:09:49.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:49.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:49.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:09:49.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:09:49.50$vc4f8/va=5,7 2006.176.08:09:49.50#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.176.08:09:49.50#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.176.08:09:49.50#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:49.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:09:49.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:09:49.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:09:49.56#ibcon#enter wrdev, iclass 19, count 2 2006.176.08:09:49.56#ibcon#first serial, iclass 19, count 2 2006.176.08:09:49.56#ibcon#enter sib2, iclass 19, count 2 2006.176.08:09:49.56#ibcon#flushed, iclass 19, count 2 2006.176.08:09:49.56#ibcon#about to write, iclass 19, count 2 2006.176.08:09:49.56#ibcon#wrote, iclass 19, count 2 2006.176.08:09:49.56#ibcon#about to read 3, iclass 19, count 2 2006.176.08:09:49.58#ibcon#read 3, iclass 19, count 2 2006.176.08:09:49.58#ibcon#about to read 4, iclass 19, count 2 2006.176.08:09:49.58#ibcon#read 4, iclass 19, count 2 2006.176.08:09:49.58#ibcon#about to read 5, iclass 19, count 2 2006.176.08:09:49.58#ibcon#read 5, iclass 19, count 2 2006.176.08:09:49.58#ibcon#about to read 6, iclass 19, count 2 2006.176.08:09:49.58#ibcon#read 6, iclass 19, count 2 2006.176.08:09:49.58#ibcon#end of sib2, iclass 19, count 2 2006.176.08:09:49.58#ibcon#*mode == 0, iclass 19, count 2 2006.176.08:09:49.58#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.176.08:09:49.58#ibcon#[25=AT05-07\r\n] 2006.176.08:09:49.58#ibcon#*before write, iclass 19, count 2 2006.176.08:09:49.58#ibcon#enter sib2, iclass 19, count 2 2006.176.08:09:49.58#ibcon#flushed, iclass 19, count 2 2006.176.08:09:49.58#ibcon#about to write, iclass 19, count 2 2006.176.08:09:49.58#ibcon#wrote, iclass 19, count 2 2006.176.08:09:49.58#ibcon#about to read 3, iclass 19, count 2 2006.176.08:09:49.61#ibcon#read 3, iclass 19, count 2 2006.176.08:09:49.61#ibcon#about to read 4, iclass 19, count 2 2006.176.08:09:49.61#ibcon#read 4, iclass 19, count 2 2006.176.08:09:49.61#ibcon#about to read 5, iclass 19, count 2 2006.176.08:09:49.61#ibcon#read 5, iclass 19, count 2 2006.176.08:09:49.61#ibcon#about to read 6, iclass 19, count 2 2006.176.08:09:49.61#ibcon#read 6, iclass 19, count 2 2006.176.08:09:49.61#ibcon#end of sib2, iclass 19, count 2 2006.176.08:09:49.61#ibcon#*after write, iclass 19, count 2 2006.176.08:09:49.61#ibcon#*before return 0, iclass 19, count 2 2006.176.08:09:49.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:09:49.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:09:49.61#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.176.08:09:49.61#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:49.61#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:09:49.73#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:09:49.73#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:09:49.73#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:09:49.73#ibcon#first serial, iclass 19, count 0 2006.176.08:09:49.73#ibcon#enter sib2, iclass 19, count 0 2006.176.08:09:49.73#ibcon#flushed, iclass 19, count 0 2006.176.08:09:49.73#ibcon#about to write, iclass 19, count 0 2006.176.08:09:49.73#ibcon#wrote, iclass 19, count 0 2006.176.08:09:49.73#ibcon#about to read 3, iclass 19, count 0 2006.176.08:09:49.75#ibcon#read 3, iclass 19, count 0 2006.176.08:09:49.75#ibcon#about to read 4, iclass 19, count 0 2006.176.08:09:49.75#ibcon#read 4, iclass 19, count 0 2006.176.08:09:49.75#ibcon#about to read 5, iclass 19, count 0 2006.176.08:09:49.75#ibcon#read 5, iclass 19, count 0 2006.176.08:09:49.75#ibcon#about to read 6, iclass 19, count 0 2006.176.08:09:49.75#ibcon#read 6, iclass 19, count 0 2006.176.08:09:49.75#ibcon#end of sib2, iclass 19, count 0 2006.176.08:09:49.75#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:09:49.75#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:09:49.75#ibcon#[25=USB\r\n] 2006.176.08:09:49.75#ibcon#*before write, iclass 19, count 0 2006.176.08:09:49.75#ibcon#enter sib2, iclass 19, count 0 2006.176.08:09:49.75#ibcon#flushed, iclass 19, count 0 2006.176.08:09:49.75#ibcon#about to write, iclass 19, count 0 2006.176.08:09:49.75#ibcon#wrote, iclass 19, count 0 2006.176.08:09:49.75#ibcon#about to read 3, iclass 19, count 0 2006.176.08:09:49.78#ibcon#read 3, iclass 19, count 0 2006.176.08:09:49.78#ibcon#about to read 4, iclass 19, count 0 2006.176.08:09:49.78#ibcon#read 4, iclass 19, count 0 2006.176.08:09:49.78#ibcon#about to read 5, iclass 19, count 0 2006.176.08:09:49.78#ibcon#read 5, iclass 19, count 0 2006.176.08:09:49.78#ibcon#about to read 6, iclass 19, count 0 2006.176.08:09:49.78#ibcon#read 6, iclass 19, count 0 2006.176.08:09:49.78#ibcon#end of sib2, iclass 19, count 0 2006.176.08:09:49.78#ibcon#*after write, iclass 19, count 0 2006.176.08:09:49.78#ibcon#*before return 0, iclass 19, count 0 2006.176.08:09:49.78#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:09:49.78#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:09:49.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:09:49.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:09:49.78$vc4f8/valo=6,772.99 2006.176.08:09:49.78#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.08:09:49.78#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.08:09:49.78#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:49.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:09:49.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:09:49.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:09:49.78#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:09:49.78#ibcon#first serial, iclass 21, count 0 2006.176.08:09:49.78#ibcon#enter sib2, iclass 21, count 0 2006.176.08:09:49.78#ibcon#flushed, iclass 21, count 0 2006.176.08:09:49.78#ibcon#about to write, iclass 21, count 0 2006.176.08:09:49.78#ibcon#wrote, iclass 21, count 0 2006.176.08:09:49.78#ibcon#about to read 3, iclass 21, count 0 2006.176.08:09:49.80#ibcon#read 3, iclass 21, count 0 2006.176.08:09:49.80#ibcon#about to read 4, iclass 21, count 0 2006.176.08:09:49.80#ibcon#read 4, iclass 21, count 0 2006.176.08:09:49.80#ibcon#about to read 5, iclass 21, count 0 2006.176.08:09:49.80#ibcon#read 5, iclass 21, count 0 2006.176.08:09:49.80#ibcon#about to read 6, iclass 21, count 0 2006.176.08:09:49.80#ibcon#read 6, iclass 21, count 0 2006.176.08:09:49.80#ibcon#end of sib2, iclass 21, count 0 2006.176.08:09:49.80#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:09:49.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:09:49.80#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:09:49.80#ibcon#*before write, iclass 21, count 0 2006.176.08:09:49.80#ibcon#enter sib2, iclass 21, count 0 2006.176.08:09:49.80#ibcon#flushed, iclass 21, count 0 2006.176.08:09:49.80#ibcon#about to write, iclass 21, count 0 2006.176.08:09:49.80#ibcon#wrote, iclass 21, count 0 2006.176.08:09:49.80#ibcon#about to read 3, iclass 21, count 0 2006.176.08:09:49.84#ibcon#read 3, iclass 21, count 0 2006.176.08:09:49.84#ibcon#about to read 4, iclass 21, count 0 2006.176.08:09:49.84#ibcon#read 4, iclass 21, count 0 2006.176.08:09:49.84#ibcon#about to read 5, iclass 21, count 0 2006.176.08:09:49.84#ibcon#read 5, iclass 21, count 0 2006.176.08:09:49.84#ibcon#about to read 6, iclass 21, count 0 2006.176.08:09:49.84#ibcon#read 6, iclass 21, count 0 2006.176.08:09:49.84#ibcon#end of sib2, iclass 21, count 0 2006.176.08:09:49.84#ibcon#*after write, iclass 21, count 0 2006.176.08:09:49.84#ibcon#*before return 0, iclass 21, count 0 2006.176.08:09:49.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:09:49.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:09:49.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:09:49.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:09:49.84$vc4f8/va=6,6 2006.176.08:09:49.84#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.08:09:49.84#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.08:09:49.84#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:49.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:09:49.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:09:49.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:09:49.90#ibcon#enter wrdev, iclass 23, count 2 2006.176.08:09:49.90#ibcon#first serial, iclass 23, count 2 2006.176.08:09:49.90#ibcon#enter sib2, iclass 23, count 2 2006.176.08:09:49.90#ibcon#flushed, iclass 23, count 2 2006.176.08:09:49.90#ibcon#about to write, iclass 23, count 2 2006.176.08:09:49.90#ibcon#wrote, iclass 23, count 2 2006.176.08:09:49.90#ibcon#about to read 3, iclass 23, count 2 2006.176.08:09:49.92#ibcon#read 3, iclass 23, count 2 2006.176.08:09:49.92#ibcon#about to read 4, iclass 23, count 2 2006.176.08:09:49.92#ibcon#read 4, iclass 23, count 2 2006.176.08:09:49.92#ibcon#about to read 5, iclass 23, count 2 2006.176.08:09:49.92#ibcon#read 5, iclass 23, count 2 2006.176.08:09:49.92#ibcon#about to read 6, iclass 23, count 2 2006.176.08:09:49.92#ibcon#read 6, iclass 23, count 2 2006.176.08:09:49.92#ibcon#end of sib2, iclass 23, count 2 2006.176.08:09:49.92#ibcon#*mode == 0, iclass 23, count 2 2006.176.08:09:49.92#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.08:09:49.92#ibcon#[25=AT06-06\r\n] 2006.176.08:09:49.92#ibcon#*before write, iclass 23, count 2 2006.176.08:09:49.92#ibcon#enter sib2, iclass 23, count 2 2006.176.08:09:49.92#ibcon#flushed, iclass 23, count 2 2006.176.08:09:49.92#ibcon#about to write, iclass 23, count 2 2006.176.08:09:49.92#ibcon#wrote, iclass 23, count 2 2006.176.08:09:49.92#ibcon#about to read 3, iclass 23, count 2 2006.176.08:09:49.95#ibcon#read 3, iclass 23, count 2 2006.176.08:09:49.95#ibcon#about to read 4, iclass 23, count 2 2006.176.08:09:49.95#ibcon#read 4, iclass 23, count 2 2006.176.08:09:49.95#ibcon#about to read 5, iclass 23, count 2 2006.176.08:09:49.95#ibcon#read 5, iclass 23, count 2 2006.176.08:09:49.95#ibcon#about to read 6, iclass 23, count 2 2006.176.08:09:49.95#ibcon#read 6, iclass 23, count 2 2006.176.08:09:49.95#ibcon#end of sib2, iclass 23, count 2 2006.176.08:09:49.95#ibcon#*after write, iclass 23, count 2 2006.176.08:09:49.95#ibcon#*before return 0, iclass 23, count 2 2006.176.08:09:49.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:09:49.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:09:49.95#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.08:09:49.95#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:49.95#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:09:50.07#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:09:50.07#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:09:50.07#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:09:50.07#ibcon#first serial, iclass 23, count 0 2006.176.08:09:50.07#ibcon#enter sib2, iclass 23, count 0 2006.176.08:09:50.07#ibcon#flushed, iclass 23, count 0 2006.176.08:09:50.07#ibcon#about to write, iclass 23, count 0 2006.176.08:09:50.07#ibcon#wrote, iclass 23, count 0 2006.176.08:09:50.07#ibcon#about to read 3, iclass 23, count 0 2006.176.08:09:50.09#ibcon#read 3, iclass 23, count 0 2006.176.08:09:50.09#ibcon#about to read 4, iclass 23, count 0 2006.176.08:09:50.09#ibcon#read 4, iclass 23, count 0 2006.176.08:09:50.09#ibcon#about to read 5, iclass 23, count 0 2006.176.08:09:50.09#ibcon#read 5, iclass 23, count 0 2006.176.08:09:50.09#ibcon#about to read 6, iclass 23, count 0 2006.176.08:09:50.09#ibcon#read 6, iclass 23, count 0 2006.176.08:09:50.09#ibcon#end of sib2, iclass 23, count 0 2006.176.08:09:50.09#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:09:50.09#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:09:50.09#ibcon#[25=USB\r\n] 2006.176.08:09:50.09#ibcon#*before write, iclass 23, count 0 2006.176.08:09:50.09#ibcon#enter sib2, iclass 23, count 0 2006.176.08:09:50.09#ibcon#flushed, iclass 23, count 0 2006.176.08:09:50.09#ibcon#about to write, iclass 23, count 0 2006.176.08:09:50.09#ibcon#wrote, iclass 23, count 0 2006.176.08:09:50.09#ibcon#about to read 3, iclass 23, count 0 2006.176.08:09:50.12#ibcon#read 3, iclass 23, count 0 2006.176.08:09:50.12#ibcon#about to read 4, iclass 23, count 0 2006.176.08:09:50.12#ibcon#read 4, iclass 23, count 0 2006.176.08:09:50.12#ibcon#about to read 5, iclass 23, count 0 2006.176.08:09:50.12#ibcon#read 5, iclass 23, count 0 2006.176.08:09:50.12#ibcon#about to read 6, iclass 23, count 0 2006.176.08:09:50.12#ibcon#read 6, iclass 23, count 0 2006.176.08:09:50.12#ibcon#end of sib2, iclass 23, count 0 2006.176.08:09:50.12#ibcon#*after write, iclass 23, count 0 2006.176.08:09:50.12#ibcon#*before return 0, iclass 23, count 0 2006.176.08:09:50.12#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:09:50.12#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:09:50.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:09:50.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:09:50.12$vc4f8/valo=7,832.99 2006.176.08:09:50.12#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.08:09:50.12#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.08:09:50.12#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:50.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:50.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:50.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:50.12#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:09:50.12#ibcon#first serial, iclass 25, count 0 2006.176.08:09:50.12#ibcon#enter sib2, iclass 25, count 0 2006.176.08:09:50.12#ibcon#flushed, iclass 25, count 0 2006.176.08:09:50.12#ibcon#about to write, iclass 25, count 0 2006.176.08:09:50.12#ibcon#wrote, iclass 25, count 0 2006.176.08:09:50.12#ibcon#about to read 3, iclass 25, count 0 2006.176.08:09:50.14#ibcon#read 3, iclass 25, count 0 2006.176.08:09:50.14#ibcon#about to read 4, iclass 25, count 0 2006.176.08:09:50.14#ibcon#read 4, iclass 25, count 0 2006.176.08:09:50.14#ibcon#about to read 5, iclass 25, count 0 2006.176.08:09:50.14#ibcon#read 5, iclass 25, count 0 2006.176.08:09:50.14#ibcon#about to read 6, iclass 25, count 0 2006.176.08:09:50.14#ibcon#read 6, iclass 25, count 0 2006.176.08:09:50.14#ibcon#end of sib2, iclass 25, count 0 2006.176.08:09:50.14#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:09:50.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:09:50.14#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:09:50.14#ibcon#*before write, iclass 25, count 0 2006.176.08:09:50.14#ibcon#enter sib2, iclass 25, count 0 2006.176.08:09:50.14#ibcon#flushed, iclass 25, count 0 2006.176.08:09:50.14#ibcon#about to write, iclass 25, count 0 2006.176.08:09:50.14#ibcon#wrote, iclass 25, count 0 2006.176.08:09:50.14#ibcon#about to read 3, iclass 25, count 0 2006.176.08:09:50.18#ibcon#read 3, iclass 25, count 0 2006.176.08:09:50.18#ibcon#about to read 4, iclass 25, count 0 2006.176.08:09:50.18#ibcon#read 4, iclass 25, count 0 2006.176.08:09:50.18#ibcon#about to read 5, iclass 25, count 0 2006.176.08:09:50.18#ibcon#read 5, iclass 25, count 0 2006.176.08:09:50.18#ibcon#about to read 6, iclass 25, count 0 2006.176.08:09:50.18#ibcon#read 6, iclass 25, count 0 2006.176.08:09:50.18#ibcon#end of sib2, iclass 25, count 0 2006.176.08:09:50.18#ibcon#*after write, iclass 25, count 0 2006.176.08:09:50.18#ibcon#*before return 0, iclass 25, count 0 2006.176.08:09:50.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:50.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:50.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:09:50.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:09:50.18$vc4f8/va=7,6 2006.176.08:09:50.18#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.08:09:50.18#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.08:09:50.18#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:50.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:09:50.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:09:50.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:09:50.24#ibcon#enter wrdev, iclass 27, count 2 2006.176.08:09:50.24#ibcon#first serial, iclass 27, count 2 2006.176.08:09:50.24#ibcon#enter sib2, iclass 27, count 2 2006.176.08:09:50.24#ibcon#flushed, iclass 27, count 2 2006.176.08:09:50.24#ibcon#about to write, iclass 27, count 2 2006.176.08:09:50.24#ibcon#wrote, iclass 27, count 2 2006.176.08:09:50.24#ibcon#about to read 3, iclass 27, count 2 2006.176.08:09:50.26#ibcon#read 3, iclass 27, count 2 2006.176.08:09:50.26#ibcon#about to read 4, iclass 27, count 2 2006.176.08:09:50.26#ibcon#read 4, iclass 27, count 2 2006.176.08:09:50.26#ibcon#about to read 5, iclass 27, count 2 2006.176.08:09:50.26#ibcon#read 5, iclass 27, count 2 2006.176.08:09:50.26#ibcon#about to read 6, iclass 27, count 2 2006.176.08:09:50.26#ibcon#read 6, iclass 27, count 2 2006.176.08:09:50.26#ibcon#end of sib2, iclass 27, count 2 2006.176.08:09:50.26#ibcon#*mode == 0, iclass 27, count 2 2006.176.08:09:50.26#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.08:09:50.26#ibcon#[25=AT07-06\r\n] 2006.176.08:09:50.26#ibcon#*before write, iclass 27, count 2 2006.176.08:09:50.26#ibcon#enter sib2, iclass 27, count 2 2006.176.08:09:50.26#ibcon#flushed, iclass 27, count 2 2006.176.08:09:50.26#ibcon#about to write, iclass 27, count 2 2006.176.08:09:50.26#ibcon#wrote, iclass 27, count 2 2006.176.08:09:50.26#ibcon#about to read 3, iclass 27, count 2 2006.176.08:09:50.29#ibcon#read 3, iclass 27, count 2 2006.176.08:09:50.29#ibcon#about to read 4, iclass 27, count 2 2006.176.08:09:50.29#ibcon#read 4, iclass 27, count 2 2006.176.08:09:50.29#ibcon#about to read 5, iclass 27, count 2 2006.176.08:09:50.29#ibcon#read 5, iclass 27, count 2 2006.176.08:09:50.29#ibcon#about to read 6, iclass 27, count 2 2006.176.08:09:50.29#ibcon#read 6, iclass 27, count 2 2006.176.08:09:50.29#ibcon#end of sib2, iclass 27, count 2 2006.176.08:09:50.29#ibcon#*after write, iclass 27, count 2 2006.176.08:09:50.29#ibcon#*before return 0, iclass 27, count 2 2006.176.08:09:50.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:09:50.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:09:50.29#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.08:09:50.29#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:50.29#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:09:50.41#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:09:50.41#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:09:50.41#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:09:50.41#ibcon#first serial, iclass 27, count 0 2006.176.08:09:50.41#ibcon#enter sib2, iclass 27, count 0 2006.176.08:09:50.41#ibcon#flushed, iclass 27, count 0 2006.176.08:09:50.41#ibcon#about to write, iclass 27, count 0 2006.176.08:09:50.41#ibcon#wrote, iclass 27, count 0 2006.176.08:09:50.41#ibcon#about to read 3, iclass 27, count 0 2006.176.08:09:50.43#ibcon#read 3, iclass 27, count 0 2006.176.08:09:50.43#ibcon#about to read 4, iclass 27, count 0 2006.176.08:09:50.43#ibcon#read 4, iclass 27, count 0 2006.176.08:09:50.43#ibcon#about to read 5, iclass 27, count 0 2006.176.08:09:50.43#ibcon#read 5, iclass 27, count 0 2006.176.08:09:50.43#ibcon#about to read 6, iclass 27, count 0 2006.176.08:09:50.43#ibcon#read 6, iclass 27, count 0 2006.176.08:09:50.43#ibcon#end of sib2, iclass 27, count 0 2006.176.08:09:50.43#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:09:50.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:09:50.43#ibcon#[25=USB\r\n] 2006.176.08:09:50.43#ibcon#*before write, iclass 27, count 0 2006.176.08:09:50.43#ibcon#enter sib2, iclass 27, count 0 2006.176.08:09:50.43#ibcon#flushed, iclass 27, count 0 2006.176.08:09:50.43#ibcon#about to write, iclass 27, count 0 2006.176.08:09:50.43#ibcon#wrote, iclass 27, count 0 2006.176.08:09:50.43#ibcon#about to read 3, iclass 27, count 0 2006.176.08:09:50.46#ibcon#read 3, iclass 27, count 0 2006.176.08:09:50.46#ibcon#about to read 4, iclass 27, count 0 2006.176.08:09:50.46#ibcon#read 4, iclass 27, count 0 2006.176.08:09:50.46#ibcon#about to read 5, iclass 27, count 0 2006.176.08:09:50.46#ibcon#read 5, iclass 27, count 0 2006.176.08:09:50.46#ibcon#about to read 6, iclass 27, count 0 2006.176.08:09:50.46#ibcon#read 6, iclass 27, count 0 2006.176.08:09:50.46#ibcon#end of sib2, iclass 27, count 0 2006.176.08:09:50.46#ibcon#*after write, iclass 27, count 0 2006.176.08:09:50.46#ibcon#*before return 0, iclass 27, count 0 2006.176.08:09:50.46#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:09:50.46#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:09:50.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:09:50.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:09:50.46$vc4f8/valo=8,852.99 2006.176.08:09:50.46#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.08:09:50.46#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.08:09:50.46#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:50.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:09:50.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:09:50.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:09:50.46#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:09:50.46#ibcon#first serial, iclass 29, count 0 2006.176.08:09:50.46#ibcon#enter sib2, iclass 29, count 0 2006.176.08:09:50.46#ibcon#flushed, iclass 29, count 0 2006.176.08:09:50.46#ibcon#about to write, iclass 29, count 0 2006.176.08:09:50.46#ibcon#wrote, iclass 29, count 0 2006.176.08:09:50.46#ibcon#about to read 3, iclass 29, count 0 2006.176.08:09:50.48#ibcon#read 3, iclass 29, count 0 2006.176.08:09:50.48#ibcon#about to read 4, iclass 29, count 0 2006.176.08:09:50.48#ibcon#read 4, iclass 29, count 0 2006.176.08:09:50.48#ibcon#about to read 5, iclass 29, count 0 2006.176.08:09:50.48#ibcon#read 5, iclass 29, count 0 2006.176.08:09:50.48#ibcon#about to read 6, iclass 29, count 0 2006.176.08:09:50.48#ibcon#read 6, iclass 29, count 0 2006.176.08:09:50.48#ibcon#end of sib2, iclass 29, count 0 2006.176.08:09:50.48#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:09:50.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:09:50.48#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:09:50.48#ibcon#*before write, iclass 29, count 0 2006.176.08:09:50.48#ibcon#enter sib2, iclass 29, count 0 2006.176.08:09:50.48#ibcon#flushed, iclass 29, count 0 2006.176.08:09:50.48#ibcon#about to write, iclass 29, count 0 2006.176.08:09:50.48#ibcon#wrote, iclass 29, count 0 2006.176.08:09:50.48#ibcon#about to read 3, iclass 29, count 0 2006.176.08:09:50.52#ibcon#read 3, iclass 29, count 0 2006.176.08:09:50.52#ibcon#about to read 4, iclass 29, count 0 2006.176.08:09:50.52#ibcon#read 4, iclass 29, count 0 2006.176.08:09:50.52#ibcon#about to read 5, iclass 29, count 0 2006.176.08:09:50.52#ibcon#read 5, iclass 29, count 0 2006.176.08:09:50.52#ibcon#about to read 6, iclass 29, count 0 2006.176.08:09:50.52#ibcon#read 6, iclass 29, count 0 2006.176.08:09:50.52#ibcon#end of sib2, iclass 29, count 0 2006.176.08:09:50.52#ibcon#*after write, iclass 29, count 0 2006.176.08:09:50.52#ibcon#*before return 0, iclass 29, count 0 2006.176.08:09:50.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:09:50.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:09:50.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:09:50.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:09:50.52$vc4f8/va=8,6 2006.176.08:09:50.52#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.08:09:50.52#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.08:09:50.52#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:50.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:09:50.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:09:50.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:09:50.58#ibcon#enter wrdev, iclass 31, count 2 2006.176.08:09:50.58#ibcon#first serial, iclass 31, count 2 2006.176.08:09:50.58#ibcon#enter sib2, iclass 31, count 2 2006.176.08:09:50.58#ibcon#flushed, iclass 31, count 2 2006.176.08:09:50.58#ibcon#about to write, iclass 31, count 2 2006.176.08:09:50.58#ibcon#wrote, iclass 31, count 2 2006.176.08:09:50.58#ibcon#about to read 3, iclass 31, count 2 2006.176.08:09:50.60#ibcon#read 3, iclass 31, count 2 2006.176.08:09:50.60#ibcon#about to read 4, iclass 31, count 2 2006.176.08:09:50.60#ibcon#read 4, iclass 31, count 2 2006.176.08:09:50.60#ibcon#about to read 5, iclass 31, count 2 2006.176.08:09:50.60#ibcon#read 5, iclass 31, count 2 2006.176.08:09:50.60#ibcon#about to read 6, iclass 31, count 2 2006.176.08:09:50.60#ibcon#read 6, iclass 31, count 2 2006.176.08:09:50.60#ibcon#end of sib2, iclass 31, count 2 2006.176.08:09:50.60#ibcon#*mode == 0, iclass 31, count 2 2006.176.08:09:50.60#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.08:09:50.60#ibcon#[25=AT08-06\r\n] 2006.176.08:09:50.60#ibcon#*before write, iclass 31, count 2 2006.176.08:09:50.60#ibcon#enter sib2, iclass 31, count 2 2006.176.08:09:50.60#ibcon#flushed, iclass 31, count 2 2006.176.08:09:50.60#ibcon#about to write, iclass 31, count 2 2006.176.08:09:50.60#ibcon#wrote, iclass 31, count 2 2006.176.08:09:50.60#ibcon#about to read 3, iclass 31, count 2 2006.176.08:09:50.63#ibcon#read 3, iclass 31, count 2 2006.176.08:09:50.63#ibcon#about to read 4, iclass 31, count 2 2006.176.08:09:50.63#ibcon#read 4, iclass 31, count 2 2006.176.08:09:50.63#ibcon#about to read 5, iclass 31, count 2 2006.176.08:09:50.63#ibcon#read 5, iclass 31, count 2 2006.176.08:09:50.63#ibcon#about to read 6, iclass 31, count 2 2006.176.08:09:50.63#ibcon#read 6, iclass 31, count 2 2006.176.08:09:50.63#ibcon#end of sib2, iclass 31, count 2 2006.176.08:09:50.63#ibcon#*after write, iclass 31, count 2 2006.176.08:09:50.63#ibcon#*before return 0, iclass 31, count 2 2006.176.08:09:50.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:09:50.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:09:50.63#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.08:09:50.63#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:50.63#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:09:50.75#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:09:50.75#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:09:50.75#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:09:50.75#ibcon#first serial, iclass 31, count 0 2006.176.08:09:50.75#ibcon#enter sib2, iclass 31, count 0 2006.176.08:09:50.75#ibcon#flushed, iclass 31, count 0 2006.176.08:09:50.75#ibcon#about to write, iclass 31, count 0 2006.176.08:09:50.75#ibcon#wrote, iclass 31, count 0 2006.176.08:09:50.75#ibcon#about to read 3, iclass 31, count 0 2006.176.08:09:50.77#ibcon#read 3, iclass 31, count 0 2006.176.08:09:50.77#ibcon#about to read 4, iclass 31, count 0 2006.176.08:09:50.77#ibcon#read 4, iclass 31, count 0 2006.176.08:09:50.77#ibcon#about to read 5, iclass 31, count 0 2006.176.08:09:50.77#ibcon#read 5, iclass 31, count 0 2006.176.08:09:50.77#ibcon#about to read 6, iclass 31, count 0 2006.176.08:09:50.77#ibcon#read 6, iclass 31, count 0 2006.176.08:09:50.77#ibcon#end of sib2, iclass 31, count 0 2006.176.08:09:50.77#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:09:50.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:09:50.77#ibcon#[25=USB\r\n] 2006.176.08:09:50.77#ibcon#*before write, iclass 31, count 0 2006.176.08:09:50.77#ibcon#enter sib2, iclass 31, count 0 2006.176.08:09:50.77#ibcon#flushed, iclass 31, count 0 2006.176.08:09:50.77#ibcon#about to write, iclass 31, count 0 2006.176.08:09:50.77#ibcon#wrote, iclass 31, count 0 2006.176.08:09:50.77#ibcon#about to read 3, iclass 31, count 0 2006.176.08:09:50.80#ibcon#read 3, iclass 31, count 0 2006.176.08:09:50.80#ibcon#about to read 4, iclass 31, count 0 2006.176.08:09:50.80#ibcon#read 4, iclass 31, count 0 2006.176.08:09:50.80#ibcon#about to read 5, iclass 31, count 0 2006.176.08:09:50.80#ibcon#read 5, iclass 31, count 0 2006.176.08:09:50.80#ibcon#about to read 6, iclass 31, count 0 2006.176.08:09:50.80#ibcon#read 6, iclass 31, count 0 2006.176.08:09:50.80#ibcon#end of sib2, iclass 31, count 0 2006.176.08:09:50.80#ibcon#*after write, iclass 31, count 0 2006.176.08:09:50.80#ibcon#*before return 0, iclass 31, count 0 2006.176.08:09:50.80#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:09:50.80#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:09:50.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:09:50.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:09:50.80$vc4f8/vblo=1,632.99 2006.176.08:09:50.80#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.08:09:50.80#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.08:09:50.80#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:50.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:09:50.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:09:50.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:09:50.80#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:09:50.80#ibcon#first serial, iclass 33, count 0 2006.176.08:09:50.80#ibcon#enter sib2, iclass 33, count 0 2006.176.08:09:50.80#ibcon#flushed, iclass 33, count 0 2006.176.08:09:50.80#ibcon#about to write, iclass 33, count 0 2006.176.08:09:50.80#ibcon#wrote, iclass 33, count 0 2006.176.08:09:50.80#ibcon#about to read 3, iclass 33, count 0 2006.176.08:09:50.82#ibcon#read 3, iclass 33, count 0 2006.176.08:09:50.82#ibcon#about to read 4, iclass 33, count 0 2006.176.08:09:50.82#ibcon#read 4, iclass 33, count 0 2006.176.08:09:50.82#ibcon#about to read 5, iclass 33, count 0 2006.176.08:09:50.82#ibcon#read 5, iclass 33, count 0 2006.176.08:09:50.82#ibcon#about to read 6, iclass 33, count 0 2006.176.08:09:50.82#ibcon#read 6, iclass 33, count 0 2006.176.08:09:50.82#ibcon#end of sib2, iclass 33, count 0 2006.176.08:09:50.82#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:09:50.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:09:50.82#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:09:50.82#ibcon#*before write, iclass 33, count 0 2006.176.08:09:50.82#ibcon#enter sib2, iclass 33, count 0 2006.176.08:09:50.82#ibcon#flushed, iclass 33, count 0 2006.176.08:09:50.82#ibcon#about to write, iclass 33, count 0 2006.176.08:09:50.82#ibcon#wrote, iclass 33, count 0 2006.176.08:09:50.82#ibcon#about to read 3, iclass 33, count 0 2006.176.08:09:50.86#ibcon#read 3, iclass 33, count 0 2006.176.08:09:50.86#ibcon#about to read 4, iclass 33, count 0 2006.176.08:09:50.86#ibcon#read 4, iclass 33, count 0 2006.176.08:09:50.86#ibcon#about to read 5, iclass 33, count 0 2006.176.08:09:50.86#ibcon#read 5, iclass 33, count 0 2006.176.08:09:50.86#ibcon#about to read 6, iclass 33, count 0 2006.176.08:09:50.86#ibcon#read 6, iclass 33, count 0 2006.176.08:09:50.86#ibcon#end of sib2, iclass 33, count 0 2006.176.08:09:50.86#ibcon#*after write, iclass 33, count 0 2006.176.08:09:50.86#ibcon#*before return 0, iclass 33, count 0 2006.176.08:09:50.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:09:50.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:09:50.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:09:50.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:09:50.86$vc4f8/vb=1,4 2006.176.08:09:50.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.176.08:09:50.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.176.08:09:50.86#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:50.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:09:50.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:09:50.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:09:50.86#ibcon#enter wrdev, iclass 35, count 2 2006.176.08:09:50.86#ibcon#first serial, iclass 35, count 2 2006.176.08:09:50.86#ibcon#enter sib2, iclass 35, count 2 2006.176.08:09:50.86#ibcon#flushed, iclass 35, count 2 2006.176.08:09:50.86#ibcon#about to write, iclass 35, count 2 2006.176.08:09:50.86#ibcon#wrote, iclass 35, count 2 2006.176.08:09:50.86#ibcon#about to read 3, iclass 35, count 2 2006.176.08:09:50.88#ibcon#read 3, iclass 35, count 2 2006.176.08:09:50.88#ibcon#about to read 4, iclass 35, count 2 2006.176.08:09:50.88#ibcon#read 4, iclass 35, count 2 2006.176.08:09:50.88#ibcon#about to read 5, iclass 35, count 2 2006.176.08:09:50.88#ibcon#read 5, iclass 35, count 2 2006.176.08:09:50.88#ibcon#about to read 6, iclass 35, count 2 2006.176.08:09:50.88#ibcon#read 6, iclass 35, count 2 2006.176.08:09:50.88#ibcon#end of sib2, iclass 35, count 2 2006.176.08:09:50.88#ibcon#*mode == 0, iclass 35, count 2 2006.176.08:09:50.88#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.176.08:09:50.88#ibcon#[27=AT01-04\r\n] 2006.176.08:09:50.88#ibcon#*before write, iclass 35, count 2 2006.176.08:09:50.88#ibcon#enter sib2, iclass 35, count 2 2006.176.08:09:50.88#ibcon#flushed, iclass 35, count 2 2006.176.08:09:50.88#ibcon#about to write, iclass 35, count 2 2006.176.08:09:50.88#ibcon#wrote, iclass 35, count 2 2006.176.08:09:50.88#ibcon#about to read 3, iclass 35, count 2 2006.176.08:09:50.91#ibcon#read 3, iclass 35, count 2 2006.176.08:09:50.91#ibcon#about to read 4, iclass 35, count 2 2006.176.08:09:50.91#ibcon#read 4, iclass 35, count 2 2006.176.08:09:50.91#ibcon#about to read 5, iclass 35, count 2 2006.176.08:09:50.91#ibcon#read 5, iclass 35, count 2 2006.176.08:09:50.91#ibcon#about to read 6, iclass 35, count 2 2006.176.08:09:50.91#ibcon#read 6, iclass 35, count 2 2006.176.08:09:50.91#ibcon#end of sib2, iclass 35, count 2 2006.176.08:09:50.91#ibcon#*after write, iclass 35, count 2 2006.176.08:09:50.91#ibcon#*before return 0, iclass 35, count 2 2006.176.08:09:50.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:09:50.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:09:50.91#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.176.08:09:50.91#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:50.91#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:09:51.03#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:09:51.03#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:09:51.03#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:09:51.03#ibcon#first serial, iclass 35, count 0 2006.176.08:09:51.03#ibcon#enter sib2, iclass 35, count 0 2006.176.08:09:51.03#ibcon#flushed, iclass 35, count 0 2006.176.08:09:51.03#ibcon#about to write, iclass 35, count 0 2006.176.08:09:51.03#ibcon#wrote, iclass 35, count 0 2006.176.08:09:51.03#ibcon#about to read 3, iclass 35, count 0 2006.176.08:09:51.05#ibcon#read 3, iclass 35, count 0 2006.176.08:09:51.05#ibcon#about to read 4, iclass 35, count 0 2006.176.08:09:51.05#ibcon#read 4, iclass 35, count 0 2006.176.08:09:51.05#ibcon#about to read 5, iclass 35, count 0 2006.176.08:09:51.05#ibcon#read 5, iclass 35, count 0 2006.176.08:09:51.05#ibcon#about to read 6, iclass 35, count 0 2006.176.08:09:51.05#ibcon#read 6, iclass 35, count 0 2006.176.08:09:51.05#ibcon#end of sib2, iclass 35, count 0 2006.176.08:09:51.05#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:09:51.05#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:09:51.05#ibcon#[27=USB\r\n] 2006.176.08:09:51.05#ibcon#*before write, iclass 35, count 0 2006.176.08:09:51.05#ibcon#enter sib2, iclass 35, count 0 2006.176.08:09:51.05#ibcon#flushed, iclass 35, count 0 2006.176.08:09:51.05#ibcon#about to write, iclass 35, count 0 2006.176.08:09:51.05#ibcon#wrote, iclass 35, count 0 2006.176.08:09:51.05#ibcon#about to read 3, iclass 35, count 0 2006.176.08:09:51.08#ibcon#read 3, iclass 35, count 0 2006.176.08:09:51.08#ibcon#about to read 4, iclass 35, count 0 2006.176.08:09:51.08#ibcon#read 4, iclass 35, count 0 2006.176.08:09:51.08#ibcon#about to read 5, iclass 35, count 0 2006.176.08:09:51.08#ibcon#read 5, iclass 35, count 0 2006.176.08:09:51.08#ibcon#about to read 6, iclass 35, count 0 2006.176.08:09:51.08#ibcon#read 6, iclass 35, count 0 2006.176.08:09:51.08#ibcon#end of sib2, iclass 35, count 0 2006.176.08:09:51.08#ibcon#*after write, iclass 35, count 0 2006.176.08:09:51.08#ibcon#*before return 0, iclass 35, count 0 2006.176.08:09:51.08#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:09:51.08#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:09:51.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:09:51.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:09:51.08$vc4f8/vblo=2,640.99 2006.176.08:09:51.08#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.176.08:09:51.08#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.176.08:09:51.08#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:51.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:51.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:51.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:51.08#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:09:51.08#ibcon#first serial, iclass 37, count 0 2006.176.08:09:51.08#ibcon#enter sib2, iclass 37, count 0 2006.176.08:09:51.08#ibcon#flushed, iclass 37, count 0 2006.176.08:09:51.08#ibcon#about to write, iclass 37, count 0 2006.176.08:09:51.08#ibcon#wrote, iclass 37, count 0 2006.176.08:09:51.08#ibcon#about to read 3, iclass 37, count 0 2006.176.08:09:51.10#ibcon#read 3, iclass 37, count 0 2006.176.08:09:51.10#ibcon#about to read 4, iclass 37, count 0 2006.176.08:09:51.10#ibcon#read 4, iclass 37, count 0 2006.176.08:09:51.10#ibcon#about to read 5, iclass 37, count 0 2006.176.08:09:51.10#ibcon#read 5, iclass 37, count 0 2006.176.08:09:51.10#ibcon#about to read 6, iclass 37, count 0 2006.176.08:09:51.10#ibcon#read 6, iclass 37, count 0 2006.176.08:09:51.10#ibcon#end of sib2, iclass 37, count 0 2006.176.08:09:51.10#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:09:51.10#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:09:51.10#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:09:51.10#ibcon#*before write, iclass 37, count 0 2006.176.08:09:51.10#ibcon#enter sib2, iclass 37, count 0 2006.176.08:09:51.10#ibcon#flushed, iclass 37, count 0 2006.176.08:09:51.10#ibcon#about to write, iclass 37, count 0 2006.176.08:09:51.10#ibcon#wrote, iclass 37, count 0 2006.176.08:09:51.10#ibcon#about to read 3, iclass 37, count 0 2006.176.08:09:51.14#ibcon#read 3, iclass 37, count 0 2006.176.08:09:51.14#ibcon#about to read 4, iclass 37, count 0 2006.176.08:09:51.14#ibcon#read 4, iclass 37, count 0 2006.176.08:09:51.14#ibcon#about to read 5, iclass 37, count 0 2006.176.08:09:51.14#ibcon#read 5, iclass 37, count 0 2006.176.08:09:51.14#ibcon#about to read 6, iclass 37, count 0 2006.176.08:09:51.14#ibcon#read 6, iclass 37, count 0 2006.176.08:09:51.14#ibcon#end of sib2, iclass 37, count 0 2006.176.08:09:51.14#ibcon#*after write, iclass 37, count 0 2006.176.08:09:51.14#ibcon#*before return 0, iclass 37, count 0 2006.176.08:09:51.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:51.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:09:51.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:09:51.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:09:51.14$vc4f8/vb=2,4 2006.176.08:09:51.14#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.176.08:09:51.14#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.176.08:09:51.14#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:51.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:51.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:51.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:51.20#ibcon#enter wrdev, iclass 39, count 2 2006.176.08:09:51.20#ibcon#first serial, iclass 39, count 2 2006.176.08:09:51.20#ibcon#enter sib2, iclass 39, count 2 2006.176.08:09:51.20#ibcon#flushed, iclass 39, count 2 2006.176.08:09:51.20#ibcon#about to write, iclass 39, count 2 2006.176.08:09:51.20#ibcon#wrote, iclass 39, count 2 2006.176.08:09:51.20#ibcon#about to read 3, iclass 39, count 2 2006.176.08:09:51.22#ibcon#read 3, iclass 39, count 2 2006.176.08:09:51.22#ibcon#about to read 4, iclass 39, count 2 2006.176.08:09:51.22#ibcon#read 4, iclass 39, count 2 2006.176.08:09:51.22#ibcon#about to read 5, iclass 39, count 2 2006.176.08:09:51.22#ibcon#read 5, iclass 39, count 2 2006.176.08:09:51.22#ibcon#about to read 6, iclass 39, count 2 2006.176.08:09:51.22#ibcon#read 6, iclass 39, count 2 2006.176.08:09:51.22#ibcon#end of sib2, iclass 39, count 2 2006.176.08:09:51.22#ibcon#*mode == 0, iclass 39, count 2 2006.176.08:09:51.22#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.176.08:09:51.22#ibcon#[27=AT02-04\r\n] 2006.176.08:09:51.22#ibcon#*before write, iclass 39, count 2 2006.176.08:09:51.22#ibcon#enter sib2, iclass 39, count 2 2006.176.08:09:51.22#ibcon#flushed, iclass 39, count 2 2006.176.08:09:51.22#ibcon#about to write, iclass 39, count 2 2006.176.08:09:51.22#ibcon#wrote, iclass 39, count 2 2006.176.08:09:51.22#ibcon#about to read 3, iclass 39, count 2 2006.176.08:09:51.25#ibcon#read 3, iclass 39, count 2 2006.176.08:09:51.25#ibcon#about to read 4, iclass 39, count 2 2006.176.08:09:51.25#ibcon#read 4, iclass 39, count 2 2006.176.08:09:51.25#ibcon#about to read 5, iclass 39, count 2 2006.176.08:09:51.25#ibcon#read 5, iclass 39, count 2 2006.176.08:09:51.25#ibcon#about to read 6, iclass 39, count 2 2006.176.08:09:51.25#ibcon#read 6, iclass 39, count 2 2006.176.08:09:51.25#ibcon#end of sib2, iclass 39, count 2 2006.176.08:09:51.25#ibcon#*after write, iclass 39, count 2 2006.176.08:09:51.25#ibcon#*before return 0, iclass 39, count 2 2006.176.08:09:51.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:51.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:09:51.25#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.176.08:09:51.25#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:51.25#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:51.37#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:51.37#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:51.37#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:09:51.37#ibcon#first serial, iclass 39, count 0 2006.176.08:09:51.37#ibcon#enter sib2, iclass 39, count 0 2006.176.08:09:51.37#ibcon#flushed, iclass 39, count 0 2006.176.08:09:51.37#ibcon#about to write, iclass 39, count 0 2006.176.08:09:51.37#ibcon#wrote, iclass 39, count 0 2006.176.08:09:51.37#ibcon#about to read 3, iclass 39, count 0 2006.176.08:09:51.39#ibcon#read 3, iclass 39, count 0 2006.176.08:09:51.39#ibcon#about to read 4, iclass 39, count 0 2006.176.08:09:51.39#ibcon#read 4, iclass 39, count 0 2006.176.08:09:51.39#ibcon#about to read 5, iclass 39, count 0 2006.176.08:09:51.39#ibcon#read 5, iclass 39, count 0 2006.176.08:09:51.39#ibcon#about to read 6, iclass 39, count 0 2006.176.08:09:51.39#ibcon#read 6, iclass 39, count 0 2006.176.08:09:51.39#ibcon#end of sib2, iclass 39, count 0 2006.176.08:09:51.39#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:09:51.39#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:09:51.39#ibcon#[27=USB\r\n] 2006.176.08:09:51.39#ibcon#*before write, iclass 39, count 0 2006.176.08:09:51.39#ibcon#enter sib2, iclass 39, count 0 2006.176.08:09:51.39#ibcon#flushed, iclass 39, count 0 2006.176.08:09:51.39#ibcon#about to write, iclass 39, count 0 2006.176.08:09:51.39#ibcon#wrote, iclass 39, count 0 2006.176.08:09:51.39#ibcon#about to read 3, iclass 39, count 0 2006.176.08:09:51.42#ibcon#read 3, iclass 39, count 0 2006.176.08:09:51.42#ibcon#about to read 4, iclass 39, count 0 2006.176.08:09:51.42#ibcon#read 4, iclass 39, count 0 2006.176.08:09:51.42#ibcon#about to read 5, iclass 39, count 0 2006.176.08:09:51.42#ibcon#read 5, iclass 39, count 0 2006.176.08:09:51.42#ibcon#about to read 6, iclass 39, count 0 2006.176.08:09:51.42#ibcon#read 6, iclass 39, count 0 2006.176.08:09:51.42#ibcon#end of sib2, iclass 39, count 0 2006.176.08:09:51.42#ibcon#*after write, iclass 39, count 0 2006.176.08:09:51.42#ibcon#*before return 0, iclass 39, count 0 2006.176.08:09:51.42#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:51.42#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:09:51.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:09:51.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:09:51.42$vc4f8/vblo=3,656.99 2006.176.08:09:51.42#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.08:09:51.42#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.08:09:51.42#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:51.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:51.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:51.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:51.42#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:09:51.42#ibcon#first serial, iclass 3, count 0 2006.176.08:09:51.42#ibcon#enter sib2, iclass 3, count 0 2006.176.08:09:51.42#ibcon#flushed, iclass 3, count 0 2006.176.08:09:51.42#ibcon#about to write, iclass 3, count 0 2006.176.08:09:51.42#ibcon#wrote, iclass 3, count 0 2006.176.08:09:51.42#ibcon#about to read 3, iclass 3, count 0 2006.176.08:09:51.44#ibcon#read 3, iclass 3, count 0 2006.176.08:09:51.44#ibcon#about to read 4, iclass 3, count 0 2006.176.08:09:51.44#ibcon#read 4, iclass 3, count 0 2006.176.08:09:51.44#ibcon#about to read 5, iclass 3, count 0 2006.176.08:09:51.44#ibcon#read 5, iclass 3, count 0 2006.176.08:09:51.44#ibcon#about to read 6, iclass 3, count 0 2006.176.08:09:51.44#ibcon#read 6, iclass 3, count 0 2006.176.08:09:51.44#ibcon#end of sib2, iclass 3, count 0 2006.176.08:09:51.44#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:09:51.44#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:09:51.44#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:09:51.44#ibcon#*before write, iclass 3, count 0 2006.176.08:09:51.44#ibcon#enter sib2, iclass 3, count 0 2006.176.08:09:51.44#ibcon#flushed, iclass 3, count 0 2006.176.08:09:51.44#ibcon#about to write, iclass 3, count 0 2006.176.08:09:51.44#ibcon#wrote, iclass 3, count 0 2006.176.08:09:51.44#ibcon#about to read 3, iclass 3, count 0 2006.176.08:09:51.48#ibcon#read 3, iclass 3, count 0 2006.176.08:09:51.48#ibcon#about to read 4, iclass 3, count 0 2006.176.08:09:51.48#ibcon#read 4, iclass 3, count 0 2006.176.08:09:51.48#ibcon#about to read 5, iclass 3, count 0 2006.176.08:09:51.48#ibcon#read 5, iclass 3, count 0 2006.176.08:09:51.48#ibcon#about to read 6, iclass 3, count 0 2006.176.08:09:51.48#ibcon#read 6, iclass 3, count 0 2006.176.08:09:51.48#ibcon#end of sib2, iclass 3, count 0 2006.176.08:09:51.48#ibcon#*after write, iclass 3, count 0 2006.176.08:09:51.48#ibcon#*before return 0, iclass 3, count 0 2006.176.08:09:51.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:51.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:09:51.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:09:51.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:09:51.48$vc4f8/vb=3,4 2006.176.08:09:51.48#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.176.08:09:51.48#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.176.08:09:51.48#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:51.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:51.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:51.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:51.54#ibcon#enter wrdev, iclass 5, count 2 2006.176.08:09:51.54#ibcon#first serial, iclass 5, count 2 2006.176.08:09:51.54#ibcon#enter sib2, iclass 5, count 2 2006.176.08:09:51.54#ibcon#flushed, iclass 5, count 2 2006.176.08:09:51.54#ibcon#about to write, iclass 5, count 2 2006.176.08:09:51.54#ibcon#wrote, iclass 5, count 2 2006.176.08:09:51.54#ibcon#about to read 3, iclass 5, count 2 2006.176.08:09:51.56#ibcon#read 3, iclass 5, count 2 2006.176.08:09:51.56#ibcon#about to read 4, iclass 5, count 2 2006.176.08:09:51.56#ibcon#read 4, iclass 5, count 2 2006.176.08:09:51.56#ibcon#about to read 5, iclass 5, count 2 2006.176.08:09:51.56#ibcon#read 5, iclass 5, count 2 2006.176.08:09:51.56#ibcon#about to read 6, iclass 5, count 2 2006.176.08:09:51.56#ibcon#read 6, iclass 5, count 2 2006.176.08:09:51.56#ibcon#end of sib2, iclass 5, count 2 2006.176.08:09:51.56#ibcon#*mode == 0, iclass 5, count 2 2006.176.08:09:51.56#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.176.08:09:51.56#ibcon#[27=AT03-04\r\n] 2006.176.08:09:51.56#ibcon#*before write, iclass 5, count 2 2006.176.08:09:51.56#ibcon#enter sib2, iclass 5, count 2 2006.176.08:09:51.56#ibcon#flushed, iclass 5, count 2 2006.176.08:09:51.56#ibcon#about to write, iclass 5, count 2 2006.176.08:09:51.56#ibcon#wrote, iclass 5, count 2 2006.176.08:09:51.56#ibcon#about to read 3, iclass 5, count 2 2006.176.08:09:51.59#ibcon#read 3, iclass 5, count 2 2006.176.08:09:51.59#ibcon#about to read 4, iclass 5, count 2 2006.176.08:09:51.59#ibcon#read 4, iclass 5, count 2 2006.176.08:09:51.59#ibcon#about to read 5, iclass 5, count 2 2006.176.08:09:51.59#ibcon#read 5, iclass 5, count 2 2006.176.08:09:51.59#ibcon#about to read 6, iclass 5, count 2 2006.176.08:09:51.59#ibcon#read 6, iclass 5, count 2 2006.176.08:09:51.59#ibcon#end of sib2, iclass 5, count 2 2006.176.08:09:51.59#ibcon#*after write, iclass 5, count 2 2006.176.08:09:51.59#ibcon#*before return 0, iclass 5, count 2 2006.176.08:09:51.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:51.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:09:51.59#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.176.08:09:51.59#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:51.59#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:51.71#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:51.71#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:51.71#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:09:51.71#ibcon#first serial, iclass 5, count 0 2006.176.08:09:51.71#ibcon#enter sib2, iclass 5, count 0 2006.176.08:09:51.71#ibcon#flushed, iclass 5, count 0 2006.176.08:09:51.71#ibcon#about to write, iclass 5, count 0 2006.176.08:09:51.71#ibcon#wrote, iclass 5, count 0 2006.176.08:09:51.71#ibcon#about to read 3, iclass 5, count 0 2006.176.08:09:51.73#ibcon#read 3, iclass 5, count 0 2006.176.08:09:51.73#ibcon#about to read 4, iclass 5, count 0 2006.176.08:09:51.73#ibcon#read 4, iclass 5, count 0 2006.176.08:09:51.73#ibcon#about to read 5, iclass 5, count 0 2006.176.08:09:51.73#ibcon#read 5, iclass 5, count 0 2006.176.08:09:51.73#ibcon#about to read 6, iclass 5, count 0 2006.176.08:09:51.73#ibcon#read 6, iclass 5, count 0 2006.176.08:09:51.73#ibcon#end of sib2, iclass 5, count 0 2006.176.08:09:51.73#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:09:51.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:09:51.73#ibcon#[27=USB\r\n] 2006.176.08:09:51.73#ibcon#*before write, iclass 5, count 0 2006.176.08:09:51.73#ibcon#enter sib2, iclass 5, count 0 2006.176.08:09:51.73#ibcon#flushed, iclass 5, count 0 2006.176.08:09:51.73#ibcon#about to write, iclass 5, count 0 2006.176.08:09:51.73#ibcon#wrote, iclass 5, count 0 2006.176.08:09:51.73#ibcon#about to read 3, iclass 5, count 0 2006.176.08:09:51.76#ibcon#read 3, iclass 5, count 0 2006.176.08:09:51.76#ibcon#about to read 4, iclass 5, count 0 2006.176.08:09:51.76#ibcon#read 4, iclass 5, count 0 2006.176.08:09:51.76#ibcon#about to read 5, iclass 5, count 0 2006.176.08:09:51.76#ibcon#read 5, iclass 5, count 0 2006.176.08:09:51.76#ibcon#about to read 6, iclass 5, count 0 2006.176.08:09:51.76#ibcon#read 6, iclass 5, count 0 2006.176.08:09:51.76#ibcon#end of sib2, iclass 5, count 0 2006.176.08:09:51.76#ibcon#*after write, iclass 5, count 0 2006.176.08:09:51.76#ibcon#*before return 0, iclass 5, count 0 2006.176.08:09:51.76#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:51.76#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:09:51.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:09:51.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:09:51.76$vc4f8/vblo=4,712.99 2006.176.08:09:51.76#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.08:09:51.76#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.08:09:51.76#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:51.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:51.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:51.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:51.76#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:09:51.76#ibcon#first serial, iclass 7, count 0 2006.176.08:09:51.76#ibcon#enter sib2, iclass 7, count 0 2006.176.08:09:51.76#ibcon#flushed, iclass 7, count 0 2006.176.08:09:51.76#ibcon#about to write, iclass 7, count 0 2006.176.08:09:51.76#ibcon#wrote, iclass 7, count 0 2006.176.08:09:51.76#ibcon#about to read 3, iclass 7, count 0 2006.176.08:09:51.78#ibcon#read 3, iclass 7, count 0 2006.176.08:09:51.78#ibcon#about to read 4, iclass 7, count 0 2006.176.08:09:51.78#ibcon#read 4, iclass 7, count 0 2006.176.08:09:51.78#ibcon#about to read 5, iclass 7, count 0 2006.176.08:09:51.78#ibcon#read 5, iclass 7, count 0 2006.176.08:09:51.78#ibcon#about to read 6, iclass 7, count 0 2006.176.08:09:51.78#ibcon#read 6, iclass 7, count 0 2006.176.08:09:51.78#ibcon#end of sib2, iclass 7, count 0 2006.176.08:09:51.78#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:09:51.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:09:51.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:09:51.78#ibcon#*before write, iclass 7, count 0 2006.176.08:09:51.78#ibcon#enter sib2, iclass 7, count 0 2006.176.08:09:51.78#ibcon#flushed, iclass 7, count 0 2006.176.08:09:51.78#ibcon#about to write, iclass 7, count 0 2006.176.08:09:51.78#ibcon#wrote, iclass 7, count 0 2006.176.08:09:51.78#ibcon#about to read 3, iclass 7, count 0 2006.176.08:09:51.82#ibcon#read 3, iclass 7, count 0 2006.176.08:09:51.82#ibcon#about to read 4, iclass 7, count 0 2006.176.08:09:51.82#ibcon#read 4, iclass 7, count 0 2006.176.08:09:51.82#ibcon#about to read 5, iclass 7, count 0 2006.176.08:09:51.82#ibcon#read 5, iclass 7, count 0 2006.176.08:09:51.82#ibcon#about to read 6, iclass 7, count 0 2006.176.08:09:51.82#ibcon#read 6, iclass 7, count 0 2006.176.08:09:51.82#ibcon#end of sib2, iclass 7, count 0 2006.176.08:09:51.82#ibcon#*after write, iclass 7, count 0 2006.176.08:09:51.82#ibcon#*before return 0, iclass 7, count 0 2006.176.08:09:51.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:51.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:09:51.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:09:51.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:09:51.82$vc4f8/vb=4,4 2006.176.08:09:51.82#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.176.08:09:51.82#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.176.08:09:51.82#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:51.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:51.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:51.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:51.88#ibcon#enter wrdev, iclass 11, count 2 2006.176.08:09:51.88#ibcon#first serial, iclass 11, count 2 2006.176.08:09:51.88#ibcon#enter sib2, iclass 11, count 2 2006.176.08:09:51.88#ibcon#flushed, iclass 11, count 2 2006.176.08:09:51.88#ibcon#about to write, iclass 11, count 2 2006.176.08:09:51.88#ibcon#wrote, iclass 11, count 2 2006.176.08:09:51.88#ibcon#about to read 3, iclass 11, count 2 2006.176.08:09:51.90#ibcon#read 3, iclass 11, count 2 2006.176.08:09:51.90#ibcon#about to read 4, iclass 11, count 2 2006.176.08:09:51.90#ibcon#read 4, iclass 11, count 2 2006.176.08:09:51.90#ibcon#about to read 5, iclass 11, count 2 2006.176.08:09:51.90#ibcon#read 5, iclass 11, count 2 2006.176.08:09:51.90#ibcon#about to read 6, iclass 11, count 2 2006.176.08:09:51.90#ibcon#read 6, iclass 11, count 2 2006.176.08:09:51.90#ibcon#end of sib2, iclass 11, count 2 2006.176.08:09:51.90#ibcon#*mode == 0, iclass 11, count 2 2006.176.08:09:51.90#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.176.08:09:51.90#ibcon#[27=AT04-04\r\n] 2006.176.08:09:51.90#ibcon#*before write, iclass 11, count 2 2006.176.08:09:51.90#ibcon#enter sib2, iclass 11, count 2 2006.176.08:09:51.90#ibcon#flushed, iclass 11, count 2 2006.176.08:09:51.90#ibcon#about to write, iclass 11, count 2 2006.176.08:09:51.90#ibcon#wrote, iclass 11, count 2 2006.176.08:09:51.90#ibcon#about to read 3, iclass 11, count 2 2006.176.08:09:51.93#ibcon#read 3, iclass 11, count 2 2006.176.08:09:51.93#ibcon#about to read 4, iclass 11, count 2 2006.176.08:09:51.93#ibcon#read 4, iclass 11, count 2 2006.176.08:09:51.93#ibcon#about to read 5, iclass 11, count 2 2006.176.08:09:51.93#ibcon#read 5, iclass 11, count 2 2006.176.08:09:51.93#ibcon#about to read 6, iclass 11, count 2 2006.176.08:09:51.93#ibcon#read 6, iclass 11, count 2 2006.176.08:09:51.93#ibcon#end of sib2, iclass 11, count 2 2006.176.08:09:51.93#ibcon#*after write, iclass 11, count 2 2006.176.08:09:51.93#ibcon#*before return 0, iclass 11, count 2 2006.176.08:09:51.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:51.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:09:51.93#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.176.08:09:51.93#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:51.93#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:52.05#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:52.05#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:52.05#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:09:52.05#ibcon#first serial, iclass 11, count 0 2006.176.08:09:52.05#ibcon#enter sib2, iclass 11, count 0 2006.176.08:09:52.05#ibcon#flushed, iclass 11, count 0 2006.176.08:09:52.05#ibcon#about to write, iclass 11, count 0 2006.176.08:09:52.05#ibcon#wrote, iclass 11, count 0 2006.176.08:09:52.05#ibcon#about to read 3, iclass 11, count 0 2006.176.08:09:52.07#ibcon#read 3, iclass 11, count 0 2006.176.08:09:52.07#ibcon#about to read 4, iclass 11, count 0 2006.176.08:09:52.07#ibcon#read 4, iclass 11, count 0 2006.176.08:09:52.07#ibcon#about to read 5, iclass 11, count 0 2006.176.08:09:52.07#ibcon#read 5, iclass 11, count 0 2006.176.08:09:52.07#ibcon#about to read 6, iclass 11, count 0 2006.176.08:09:52.07#ibcon#read 6, iclass 11, count 0 2006.176.08:09:52.07#ibcon#end of sib2, iclass 11, count 0 2006.176.08:09:52.07#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:09:52.07#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:09:52.07#ibcon#[27=USB\r\n] 2006.176.08:09:52.07#ibcon#*before write, iclass 11, count 0 2006.176.08:09:52.07#ibcon#enter sib2, iclass 11, count 0 2006.176.08:09:52.07#ibcon#flushed, iclass 11, count 0 2006.176.08:09:52.07#ibcon#about to write, iclass 11, count 0 2006.176.08:09:52.07#ibcon#wrote, iclass 11, count 0 2006.176.08:09:52.07#ibcon#about to read 3, iclass 11, count 0 2006.176.08:09:52.10#ibcon#read 3, iclass 11, count 0 2006.176.08:09:52.10#ibcon#about to read 4, iclass 11, count 0 2006.176.08:09:52.10#ibcon#read 4, iclass 11, count 0 2006.176.08:09:52.10#ibcon#about to read 5, iclass 11, count 0 2006.176.08:09:52.10#ibcon#read 5, iclass 11, count 0 2006.176.08:09:52.10#ibcon#about to read 6, iclass 11, count 0 2006.176.08:09:52.10#ibcon#read 6, iclass 11, count 0 2006.176.08:09:52.10#ibcon#end of sib2, iclass 11, count 0 2006.176.08:09:52.10#ibcon#*after write, iclass 11, count 0 2006.176.08:09:52.10#ibcon#*before return 0, iclass 11, count 0 2006.176.08:09:52.10#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:52.10#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:09:52.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:09:52.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:09:52.10$vc4f8/vblo=5,744.99 2006.176.08:09:52.10#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.08:09:52.10#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.08:09:52.10#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:52.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:52.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:52.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:52.10#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:09:52.10#ibcon#first serial, iclass 13, count 0 2006.176.08:09:52.10#ibcon#enter sib2, iclass 13, count 0 2006.176.08:09:52.10#ibcon#flushed, iclass 13, count 0 2006.176.08:09:52.10#ibcon#about to write, iclass 13, count 0 2006.176.08:09:52.10#ibcon#wrote, iclass 13, count 0 2006.176.08:09:52.10#ibcon#about to read 3, iclass 13, count 0 2006.176.08:09:52.12#ibcon#read 3, iclass 13, count 0 2006.176.08:09:52.12#ibcon#about to read 4, iclass 13, count 0 2006.176.08:09:52.12#ibcon#read 4, iclass 13, count 0 2006.176.08:09:52.12#ibcon#about to read 5, iclass 13, count 0 2006.176.08:09:52.12#ibcon#read 5, iclass 13, count 0 2006.176.08:09:52.12#ibcon#about to read 6, iclass 13, count 0 2006.176.08:09:52.12#ibcon#read 6, iclass 13, count 0 2006.176.08:09:52.12#ibcon#end of sib2, iclass 13, count 0 2006.176.08:09:52.12#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:09:52.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:09:52.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:09:52.12#ibcon#*before write, iclass 13, count 0 2006.176.08:09:52.12#ibcon#enter sib2, iclass 13, count 0 2006.176.08:09:52.12#ibcon#flushed, iclass 13, count 0 2006.176.08:09:52.12#ibcon#about to write, iclass 13, count 0 2006.176.08:09:52.12#ibcon#wrote, iclass 13, count 0 2006.176.08:09:52.12#ibcon#about to read 3, iclass 13, count 0 2006.176.08:09:52.16#ibcon#read 3, iclass 13, count 0 2006.176.08:09:52.16#ibcon#about to read 4, iclass 13, count 0 2006.176.08:09:52.16#ibcon#read 4, iclass 13, count 0 2006.176.08:09:52.16#ibcon#about to read 5, iclass 13, count 0 2006.176.08:09:52.16#ibcon#read 5, iclass 13, count 0 2006.176.08:09:52.16#ibcon#about to read 6, iclass 13, count 0 2006.176.08:09:52.16#ibcon#read 6, iclass 13, count 0 2006.176.08:09:52.16#ibcon#end of sib2, iclass 13, count 0 2006.176.08:09:52.16#ibcon#*after write, iclass 13, count 0 2006.176.08:09:52.16#ibcon#*before return 0, iclass 13, count 0 2006.176.08:09:52.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:52.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:09:52.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:09:52.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:09:52.16$vc4f8/vb=5,4 2006.176.08:09:52.16#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.176.08:09:52.16#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.176.08:09:52.16#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:52.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:52.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:52.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:52.22#ibcon#enter wrdev, iclass 15, count 2 2006.176.08:09:52.22#ibcon#first serial, iclass 15, count 2 2006.176.08:09:52.22#ibcon#enter sib2, iclass 15, count 2 2006.176.08:09:52.22#ibcon#flushed, iclass 15, count 2 2006.176.08:09:52.22#ibcon#about to write, iclass 15, count 2 2006.176.08:09:52.22#ibcon#wrote, iclass 15, count 2 2006.176.08:09:52.22#ibcon#about to read 3, iclass 15, count 2 2006.176.08:09:52.24#ibcon#read 3, iclass 15, count 2 2006.176.08:09:52.24#ibcon#about to read 4, iclass 15, count 2 2006.176.08:09:52.24#ibcon#read 4, iclass 15, count 2 2006.176.08:09:52.24#ibcon#about to read 5, iclass 15, count 2 2006.176.08:09:52.24#ibcon#read 5, iclass 15, count 2 2006.176.08:09:52.24#ibcon#about to read 6, iclass 15, count 2 2006.176.08:09:52.24#ibcon#read 6, iclass 15, count 2 2006.176.08:09:52.24#ibcon#end of sib2, iclass 15, count 2 2006.176.08:09:52.24#ibcon#*mode == 0, iclass 15, count 2 2006.176.08:09:52.24#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.176.08:09:52.24#ibcon#[27=AT05-04\r\n] 2006.176.08:09:52.24#ibcon#*before write, iclass 15, count 2 2006.176.08:09:52.24#ibcon#enter sib2, iclass 15, count 2 2006.176.08:09:52.24#ibcon#flushed, iclass 15, count 2 2006.176.08:09:52.24#ibcon#about to write, iclass 15, count 2 2006.176.08:09:52.24#ibcon#wrote, iclass 15, count 2 2006.176.08:09:52.24#ibcon#about to read 3, iclass 15, count 2 2006.176.08:09:52.27#ibcon#read 3, iclass 15, count 2 2006.176.08:09:52.27#ibcon#about to read 4, iclass 15, count 2 2006.176.08:09:52.27#ibcon#read 4, iclass 15, count 2 2006.176.08:09:52.27#ibcon#about to read 5, iclass 15, count 2 2006.176.08:09:52.27#ibcon#read 5, iclass 15, count 2 2006.176.08:09:52.27#ibcon#about to read 6, iclass 15, count 2 2006.176.08:09:52.27#ibcon#read 6, iclass 15, count 2 2006.176.08:09:52.27#ibcon#end of sib2, iclass 15, count 2 2006.176.08:09:52.27#ibcon#*after write, iclass 15, count 2 2006.176.08:09:52.27#ibcon#*before return 0, iclass 15, count 2 2006.176.08:09:52.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:52.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:09:52.27#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.176.08:09:52.27#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:52.27#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:52.39#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:52.39#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:52.39#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:09:52.39#ibcon#first serial, iclass 15, count 0 2006.176.08:09:52.39#ibcon#enter sib2, iclass 15, count 0 2006.176.08:09:52.39#ibcon#flushed, iclass 15, count 0 2006.176.08:09:52.39#ibcon#about to write, iclass 15, count 0 2006.176.08:09:52.39#ibcon#wrote, iclass 15, count 0 2006.176.08:09:52.39#ibcon#about to read 3, iclass 15, count 0 2006.176.08:09:52.41#ibcon#read 3, iclass 15, count 0 2006.176.08:09:52.41#ibcon#about to read 4, iclass 15, count 0 2006.176.08:09:52.41#ibcon#read 4, iclass 15, count 0 2006.176.08:09:52.41#ibcon#about to read 5, iclass 15, count 0 2006.176.08:09:52.41#ibcon#read 5, iclass 15, count 0 2006.176.08:09:52.41#ibcon#about to read 6, iclass 15, count 0 2006.176.08:09:52.41#ibcon#read 6, iclass 15, count 0 2006.176.08:09:52.41#ibcon#end of sib2, iclass 15, count 0 2006.176.08:09:52.41#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:09:52.41#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:09:52.41#ibcon#[27=USB\r\n] 2006.176.08:09:52.41#ibcon#*before write, iclass 15, count 0 2006.176.08:09:52.41#ibcon#enter sib2, iclass 15, count 0 2006.176.08:09:52.41#ibcon#flushed, iclass 15, count 0 2006.176.08:09:52.41#ibcon#about to write, iclass 15, count 0 2006.176.08:09:52.41#ibcon#wrote, iclass 15, count 0 2006.176.08:09:52.41#ibcon#about to read 3, iclass 15, count 0 2006.176.08:09:52.44#ibcon#read 3, iclass 15, count 0 2006.176.08:09:52.44#ibcon#about to read 4, iclass 15, count 0 2006.176.08:09:52.44#ibcon#read 4, iclass 15, count 0 2006.176.08:09:52.44#ibcon#about to read 5, iclass 15, count 0 2006.176.08:09:52.44#ibcon#read 5, iclass 15, count 0 2006.176.08:09:52.44#ibcon#about to read 6, iclass 15, count 0 2006.176.08:09:52.44#ibcon#read 6, iclass 15, count 0 2006.176.08:09:52.44#ibcon#end of sib2, iclass 15, count 0 2006.176.08:09:52.44#ibcon#*after write, iclass 15, count 0 2006.176.08:09:52.44#ibcon#*before return 0, iclass 15, count 0 2006.176.08:09:52.44#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:52.44#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:09:52.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:09:52.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:09:52.44$vc4f8/vblo=6,752.99 2006.176.08:09:52.44#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.08:09:52.44#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.08:09:52.44#ibcon#ireg 17 cls_cnt 0 2006.176.08:09:52.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:52.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:52.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:52.44#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:09:52.44#ibcon#first serial, iclass 17, count 0 2006.176.08:09:52.44#ibcon#enter sib2, iclass 17, count 0 2006.176.08:09:52.44#ibcon#flushed, iclass 17, count 0 2006.176.08:09:52.44#ibcon#about to write, iclass 17, count 0 2006.176.08:09:52.44#ibcon#wrote, iclass 17, count 0 2006.176.08:09:52.44#ibcon#about to read 3, iclass 17, count 0 2006.176.08:09:52.46#ibcon#read 3, iclass 17, count 0 2006.176.08:09:52.46#ibcon#about to read 4, iclass 17, count 0 2006.176.08:09:52.46#ibcon#read 4, iclass 17, count 0 2006.176.08:09:52.46#ibcon#about to read 5, iclass 17, count 0 2006.176.08:09:52.46#ibcon#read 5, iclass 17, count 0 2006.176.08:09:52.46#ibcon#about to read 6, iclass 17, count 0 2006.176.08:09:52.46#ibcon#read 6, iclass 17, count 0 2006.176.08:09:52.46#ibcon#end of sib2, iclass 17, count 0 2006.176.08:09:52.46#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:09:52.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:09:52.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:09:52.46#ibcon#*before write, iclass 17, count 0 2006.176.08:09:52.46#ibcon#enter sib2, iclass 17, count 0 2006.176.08:09:52.46#ibcon#flushed, iclass 17, count 0 2006.176.08:09:52.46#ibcon#about to write, iclass 17, count 0 2006.176.08:09:52.46#ibcon#wrote, iclass 17, count 0 2006.176.08:09:52.46#ibcon#about to read 3, iclass 17, count 0 2006.176.08:09:52.50#ibcon#read 3, iclass 17, count 0 2006.176.08:09:52.50#ibcon#about to read 4, iclass 17, count 0 2006.176.08:09:52.50#ibcon#read 4, iclass 17, count 0 2006.176.08:09:52.50#ibcon#about to read 5, iclass 17, count 0 2006.176.08:09:52.50#ibcon#read 5, iclass 17, count 0 2006.176.08:09:52.50#ibcon#about to read 6, iclass 17, count 0 2006.176.08:09:52.50#ibcon#read 6, iclass 17, count 0 2006.176.08:09:52.50#ibcon#end of sib2, iclass 17, count 0 2006.176.08:09:52.50#ibcon#*after write, iclass 17, count 0 2006.176.08:09:52.50#ibcon#*before return 0, iclass 17, count 0 2006.176.08:09:52.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:52.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:09:52.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:09:52.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:09:52.50$vc4f8/vb=6,4 2006.176.08:09:52.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.08:09:52.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.08:09:52.50#ibcon#ireg 11 cls_cnt 2 2006.176.08:09:52.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:09:52.53#abcon#<5=/05 3.1 4.9 23.85 921008.6\r\n> 2006.176.08:09:52.55#abcon#{5=INTERFACE CLEAR} 2006.176.08:09:52.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:09:52.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:09:52.56#ibcon#enter wrdev, iclass 20, count 2 2006.176.08:09:52.56#ibcon#first serial, iclass 20, count 2 2006.176.08:09:52.56#ibcon#enter sib2, iclass 20, count 2 2006.176.08:09:52.56#ibcon#flushed, iclass 20, count 2 2006.176.08:09:52.56#ibcon#about to write, iclass 20, count 2 2006.176.08:09:52.56#ibcon#wrote, iclass 20, count 2 2006.176.08:09:52.56#ibcon#about to read 3, iclass 20, count 2 2006.176.08:09:52.58#ibcon#read 3, iclass 20, count 2 2006.176.08:09:52.58#ibcon#about to read 4, iclass 20, count 2 2006.176.08:09:52.58#ibcon#read 4, iclass 20, count 2 2006.176.08:09:52.58#ibcon#about to read 5, iclass 20, count 2 2006.176.08:09:52.58#ibcon#read 5, iclass 20, count 2 2006.176.08:09:52.58#ibcon#about to read 6, iclass 20, count 2 2006.176.08:09:52.58#ibcon#read 6, iclass 20, count 2 2006.176.08:09:52.58#ibcon#end of sib2, iclass 20, count 2 2006.176.08:09:52.58#ibcon#*mode == 0, iclass 20, count 2 2006.176.08:09:52.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.08:09:52.58#ibcon#[27=AT06-04\r\n] 2006.176.08:09:52.58#ibcon#*before write, iclass 20, count 2 2006.176.08:09:52.58#ibcon#enter sib2, iclass 20, count 2 2006.176.08:09:52.58#ibcon#flushed, iclass 20, count 2 2006.176.08:09:52.58#ibcon#about to write, iclass 20, count 2 2006.176.08:09:52.58#ibcon#wrote, iclass 20, count 2 2006.176.08:09:52.58#ibcon#about to read 3, iclass 20, count 2 2006.176.08:09:52.61#abcon#[5=S1D000X0/0*\r\n] 2006.176.08:09:52.61#ibcon#read 3, iclass 20, count 2 2006.176.08:09:52.61#ibcon#about to read 4, iclass 20, count 2 2006.176.08:09:52.61#ibcon#read 4, iclass 20, count 2 2006.176.08:09:52.61#ibcon#about to read 5, iclass 20, count 2 2006.176.08:09:52.61#ibcon#read 5, iclass 20, count 2 2006.176.08:09:52.61#ibcon#about to read 6, iclass 20, count 2 2006.176.08:09:52.61#ibcon#read 6, iclass 20, count 2 2006.176.08:09:52.61#ibcon#end of sib2, iclass 20, count 2 2006.176.08:09:52.61#ibcon#*after write, iclass 20, count 2 2006.176.08:09:52.61#ibcon#*before return 0, iclass 20, count 2 2006.176.08:09:52.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:09:52.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:09:52.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.08:09:52.61#ibcon#ireg 7 cls_cnt 0 2006.176.08:09:52.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:09:52.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:09:52.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:09:52.73#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:09:52.73#ibcon#first serial, iclass 20, count 0 2006.176.08:09:52.73#ibcon#enter sib2, iclass 20, count 0 2006.176.08:09:52.73#ibcon#flushed, iclass 20, count 0 2006.176.08:09:52.73#ibcon#about to write, iclass 20, count 0 2006.176.08:09:52.73#ibcon#wrote, iclass 20, count 0 2006.176.08:09:52.73#ibcon#about to read 3, iclass 20, count 0 2006.176.08:09:52.75#ibcon#read 3, iclass 20, count 0 2006.176.08:09:52.75#ibcon#about to read 4, iclass 20, count 0 2006.176.08:09:52.75#ibcon#read 4, iclass 20, count 0 2006.176.08:09:52.75#ibcon#about to read 5, iclass 20, count 0 2006.176.08:09:52.75#ibcon#read 5, iclass 20, count 0 2006.176.08:09:52.75#ibcon#about to read 6, iclass 20, count 0 2006.176.08:09:52.75#ibcon#read 6, iclass 20, count 0 2006.176.08:09:52.75#ibcon#end of sib2, iclass 20, count 0 2006.176.08:09:52.75#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:09:52.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:09:52.75#ibcon#[27=USB\r\n] 2006.176.08:09:52.75#ibcon#*before write, iclass 20, count 0 2006.176.08:09:52.75#ibcon#enter sib2, iclass 20, count 0 2006.176.08:09:52.75#ibcon#flushed, iclass 20, count 0 2006.176.08:09:52.75#ibcon#about to write, iclass 20, count 0 2006.176.08:09:52.75#ibcon#wrote, iclass 20, count 0 2006.176.08:09:52.75#ibcon#about to read 3, iclass 20, count 0 2006.176.08:09:52.78#ibcon#read 3, iclass 20, count 0 2006.176.08:09:52.78#ibcon#about to read 4, iclass 20, count 0 2006.176.08:09:52.78#ibcon#read 4, iclass 20, count 0 2006.176.08:09:52.78#ibcon#about to read 5, iclass 20, count 0 2006.176.08:09:52.78#ibcon#read 5, iclass 20, count 0 2006.176.08:09:52.78#ibcon#about to read 6, iclass 20, count 0 2006.176.08:09:52.78#ibcon#read 6, iclass 20, count 0 2006.176.08:09:52.78#ibcon#end of sib2, iclass 20, count 0 2006.176.08:09:52.78#ibcon#*after write, iclass 20, count 0 2006.176.08:09:52.78#ibcon#*before return 0, iclass 20, count 0 2006.176.08:09:52.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:09:52.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:09:52.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:09:52.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:09:52.78$vc4f8/vabw=wide 2006.176.08:09:52.78#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.08:09:52.78#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.08:09:52.78#ibcon#ireg 8 cls_cnt 0 2006.176.08:09:52.78#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:52.78#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:52.78#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:52.78#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:09:52.78#ibcon#first serial, iclass 25, count 0 2006.176.08:09:52.78#ibcon#enter sib2, iclass 25, count 0 2006.176.08:09:52.78#ibcon#flushed, iclass 25, count 0 2006.176.08:09:52.78#ibcon#about to write, iclass 25, count 0 2006.176.08:09:52.78#ibcon#wrote, iclass 25, count 0 2006.176.08:09:52.78#ibcon#about to read 3, iclass 25, count 0 2006.176.08:09:52.80#ibcon#read 3, iclass 25, count 0 2006.176.08:09:52.80#ibcon#about to read 4, iclass 25, count 0 2006.176.08:09:52.80#ibcon#read 4, iclass 25, count 0 2006.176.08:09:52.80#ibcon#about to read 5, iclass 25, count 0 2006.176.08:09:52.80#ibcon#read 5, iclass 25, count 0 2006.176.08:09:52.80#ibcon#about to read 6, iclass 25, count 0 2006.176.08:09:52.80#ibcon#read 6, iclass 25, count 0 2006.176.08:09:52.80#ibcon#end of sib2, iclass 25, count 0 2006.176.08:09:52.80#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:09:52.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:09:52.80#ibcon#[25=BW32\r\n] 2006.176.08:09:52.80#ibcon#*before write, iclass 25, count 0 2006.176.08:09:52.80#ibcon#enter sib2, iclass 25, count 0 2006.176.08:09:52.80#ibcon#flushed, iclass 25, count 0 2006.176.08:09:52.80#ibcon#about to write, iclass 25, count 0 2006.176.08:09:52.80#ibcon#wrote, iclass 25, count 0 2006.176.08:09:52.80#ibcon#about to read 3, iclass 25, count 0 2006.176.08:09:52.83#ibcon#read 3, iclass 25, count 0 2006.176.08:09:52.83#ibcon#about to read 4, iclass 25, count 0 2006.176.08:09:52.83#ibcon#read 4, iclass 25, count 0 2006.176.08:09:52.83#ibcon#about to read 5, iclass 25, count 0 2006.176.08:09:52.83#ibcon#read 5, iclass 25, count 0 2006.176.08:09:52.83#ibcon#about to read 6, iclass 25, count 0 2006.176.08:09:52.83#ibcon#read 6, iclass 25, count 0 2006.176.08:09:52.83#ibcon#end of sib2, iclass 25, count 0 2006.176.08:09:52.83#ibcon#*after write, iclass 25, count 0 2006.176.08:09:52.83#ibcon#*before return 0, iclass 25, count 0 2006.176.08:09:52.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:52.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:09:52.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:09:52.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:09:52.83$vc4f8/vbbw=wide 2006.176.08:09:52.83#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.08:09:52.83#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.08:09:52.83#ibcon#ireg 8 cls_cnt 0 2006.176.08:09:52.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:09:52.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:09:52.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:09:52.90#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:09:52.90#ibcon#first serial, iclass 27, count 0 2006.176.08:09:52.90#ibcon#enter sib2, iclass 27, count 0 2006.176.08:09:52.90#ibcon#flushed, iclass 27, count 0 2006.176.08:09:52.90#ibcon#about to write, iclass 27, count 0 2006.176.08:09:52.90#ibcon#wrote, iclass 27, count 0 2006.176.08:09:52.90#ibcon#about to read 3, iclass 27, count 0 2006.176.08:09:52.93#ibcon#read 3, iclass 27, count 0 2006.176.08:09:52.93#ibcon#about to read 4, iclass 27, count 0 2006.176.08:09:52.93#ibcon#read 4, iclass 27, count 0 2006.176.08:09:52.93#ibcon#about to read 5, iclass 27, count 0 2006.176.08:09:52.93#ibcon#read 5, iclass 27, count 0 2006.176.08:09:52.93#ibcon#about to read 6, iclass 27, count 0 2006.176.08:09:52.93#ibcon#read 6, iclass 27, count 0 2006.176.08:09:52.93#ibcon#end of sib2, iclass 27, count 0 2006.176.08:09:52.93#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:09:52.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:09:52.93#ibcon#[27=BW32\r\n] 2006.176.08:09:52.93#ibcon#*before write, iclass 27, count 0 2006.176.08:09:52.93#ibcon#enter sib2, iclass 27, count 0 2006.176.08:09:52.93#ibcon#flushed, iclass 27, count 0 2006.176.08:09:52.93#ibcon#about to write, iclass 27, count 0 2006.176.08:09:52.93#ibcon#wrote, iclass 27, count 0 2006.176.08:09:52.93#ibcon#about to read 3, iclass 27, count 0 2006.176.08:09:52.95#ibcon#read 3, iclass 27, count 0 2006.176.08:09:52.95#ibcon#about to read 4, iclass 27, count 0 2006.176.08:09:52.95#ibcon#read 4, iclass 27, count 0 2006.176.08:09:52.95#ibcon#about to read 5, iclass 27, count 0 2006.176.08:09:52.95#ibcon#read 5, iclass 27, count 0 2006.176.08:09:52.95#ibcon#about to read 6, iclass 27, count 0 2006.176.08:09:52.95#ibcon#read 6, iclass 27, count 0 2006.176.08:09:52.95#ibcon#end of sib2, iclass 27, count 0 2006.176.08:09:52.95#ibcon#*after write, iclass 27, count 0 2006.176.08:09:52.95#ibcon#*before return 0, iclass 27, count 0 2006.176.08:09:52.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:09:52.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:09:52.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:09:52.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:09:52.95$4f8m12a/ifd4f 2006.176.08:09:52.95$ifd4f/lo= 2006.176.08:09:52.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:09:52.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:09:52.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:09:52.95$ifd4f/patch= 2006.176.08:09:52.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:09:52.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:09:52.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:09:52.95$4f8m12a/"form=m,16.000,1:2 2006.176.08:09:52.95$4f8m12a/"tpicd 2006.176.08:09:52.95$4f8m12a/echo=off 2006.176.08:09:52.95$4f8m12a/xlog=off 2006.176.08:09:52.95:!2006.176.08:10:20 2006.176.08:09:58.14#trakl#Source acquired 2006.176.08:09:59.14#flagr#flagr/antenna,acquired 2006.176.08:10:20.00:preob 2006.176.08:10:21.14/onsource/TRACKING 2006.176.08:10:21.14:!2006.176.08:10:30 2006.176.08:10:30.00:data_valid=on 2006.176.08:10:30.00:midob 2006.176.08:10:30.14/onsource/TRACKING 2006.176.08:10:30.14/wx/23.84,1008.6,92 2006.176.08:10:30.28/cable/+6.4934E-03 2006.176.08:10:31.37/va/01,08,usb,yes,29,31 2006.176.08:10:31.37/va/02,07,usb,yes,29,31 2006.176.08:10:31.37/va/03,06,usb,yes,31,31 2006.176.08:10:31.37/va/04,07,usb,yes,30,32 2006.176.08:10:31.37/va/05,07,usb,yes,32,33 2006.176.08:10:31.37/va/06,06,usb,yes,31,30 2006.176.08:10:31.37/va/07,06,usb,yes,31,31 2006.176.08:10:31.37/va/08,06,usb,yes,33,33 2006.176.08:10:31.60/valo/01,532.99,yes,locked 2006.176.08:10:31.60/valo/02,572.99,yes,locked 2006.176.08:10:31.60/valo/03,672.99,yes,locked 2006.176.08:10:31.60/valo/04,832.99,yes,locked 2006.176.08:10:31.60/valo/05,652.99,yes,locked 2006.176.08:10:31.60/valo/06,772.99,yes,locked 2006.176.08:10:31.60/valo/07,832.99,yes,locked 2006.176.08:10:31.60/valo/08,852.99,yes,locked 2006.176.08:10:32.69/vb/01,04,usb,yes,29,28 2006.176.08:10:32.69/vb/02,04,usb,yes,31,32 2006.176.08:10:32.69/vb/03,04,usb,yes,27,31 2006.176.08:10:32.69/vb/04,04,usb,yes,28,28 2006.176.08:10:32.69/vb/05,04,usb,yes,27,31 2006.176.08:10:32.69/vb/06,04,usb,yes,28,30 2006.176.08:10:32.69/vb/07,04,usb,yes,30,30 2006.176.08:10:32.69/vb/08,04,usb,yes,27,31 2006.176.08:10:32.92/vblo/01,632.99,yes,locked 2006.176.08:10:32.92/vblo/02,640.99,yes,locked 2006.176.08:10:32.92/vblo/03,656.99,yes,locked 2006.176.08:10:32.92/vblo/04,712.99,yes,locked 2006.176.08:10:32.92/vblo/05,744.99,yes,locked 2006.176.08:10:32.92/vblo/06,752.99,yes,locked 2006.176.08:10:32.92/vblo/07,734.99,yes,locked 2006.176.08:10:32.92/vblo/08,744.99,yes,locked 2006.176.08:10:33.07/vabw/8 2006.176.08:10:33.22/vbbw/8 2006.176.08:10:33.32/xfe/off,on,15.2 2006.176.08:10:33.82/ifatt/23,28,28,28 2006.176.08:10:34.07/fmout-gps/S +3.70E-07 2006.176.08:10:34.11:!2006.176.08:11:30 2006.176.08:11:30.01:data_valid=off 2006.176.08:11:30.01:postob 2006.176.08:11:30.21/cable/+6.4931E-03 2006.176.08:11:30.21/wx/23.84,1008.6,92 2006.176.08:11:31.07/fmout-gps/S +3.71E-07 2006.176.08:11:31.07:scan_name=176-0812,k06176,60 2006.176.08:11:31.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.176.08:11:31.14#flagr#flagr/antenna,new-source 2006.176.08:11:32.14:checkk5 2006.176.08:11:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:11:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:11:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:11:33.60/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:11:33.97/chk_obsdata//k5ts1/T1760810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:11:34.35/chk_obsdata//k5ts2/T1760810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:11:34.71/chk_obsdata//k5ts3/T1760810??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:11:35.09/chk_obsdata//k5ts4/T1760810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:11:35.78/k5log//k5ts1_log_newline 2006.176.08:11:36.46/k5log//k5ts2_log_newline 2006.176.08:11:37.16/k5log//k5ts3_log_newline 2006.176.08:11:37.84/k5log//k5ts4_log_newline 2006.176.08:11:37.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:11:37.87:4f8m12a=2 2006.176.08:11:37.87$4f8m12a/echo=on 2006.176.08:11:37.87$4f8m12a/pcalon 2006.176.08:11:37.87$pcalon/"no phase cal control is implemented here 2006.176.08:11:37.87$4f8m12a/"tpicd=stop 2006.176.08:11:37.87$4f8m12a/vc4f8 2006.176.08:11:37.87$vc4f8/valo=1,532.99 2006.176.08:11:37.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.08:11:37.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.08:11:37.87#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:37.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:37.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:37.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:37.87#ibcon#enter wrdev, iclass 34, count 0 2006.176.08:11:37.87#ibcon#first serial, iclass 34, count 0 2006.176.08:11:37.87#ibcon#enter sib2, iclass 34, count 0 2006.176.08:11:37.87#ibcon#flushed, iclass 34, count 0 2006.176.08:11:37.87#ibcon#about to write, iclass 34, count 0 2006.176.08:11:37.87#ibcon#wrote, iclass 34, count 0 2006.176.08:11:37.87#ibcon#about to read 3, iclass 34, count 0 2006.176.08:11:37.91#ibcon#read 3, iclass 34, count 0 2006.176.08:11:37.91#ibcon#about to read 4, iclass 34, count 0 2006.176.08:11:37.91#ibcon#read 4, iclass 34, count 0 2006.176.08:11:37.91#ibcon#about to read 5, iclass 34, count 0 2006.176.08:11:37.91#ibcon#read 5, iclass 34, count 0 2006.176.08:11:37.91#ibcon#about to read 6, iclass 34, count 0 2006.176.08:11:37.91#ibcon#read 6, iclass 34, count 0 2006.176.08:11:37.91#ibcon#end of sib2, iclass 34, count 0 2006.176.08:11:37.91#ibcon#*mode == 0, iclass 34, count 0 2006.176.08:11:37.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.08:11:37.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:11:37.91#ibcon#*before write, iclass 34, count 0 2006.176.08:11:37.91#ibcon#enter sib2, iclass 34, count 0 2006.176.08:11:37.91#ibcon#flushed, iclass 34, count 0 2006.176.08:11:37.91#ibcon#about to write, iclass 34, count 0 2006.176.08:11:37.91#ibcon#wrote, iclass 34, count 0 2006.176.08:11:37.91#ibcon#about to read 3, iclass 34, count 0 2006.176.08:11:37.96#ibcon#read 3, iclass 34, count 0 2006.176.08:11:37.96#ibcon#about to read 4, iclass 34, count 0 2006.176.08:11:37.96#ibcon#read 4, iclass 34, count 0 2006.176.08:11:37.96#ibcon#about to read 5, iclass 34, count 0 2006.176.08:11:37.96#ibcon#read 5, iclass 34, count 0 2006.176.08:11:37.96#ibcon#about to read 6, iclass 34, count 0 2006.176.08:11:37.96#ibcon#read 6, iclass 34, count 0 2006.176.08:11:37.96#ibcon#end of sib2, iclass 34, count 0 2006.176.08:11:37.96#ibcon#*after write, iclass 34, count 0 2006.176.08:11:37.96#ibcon#*before return 0, iclass 34, count 0 2006.176.08:11:37.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:37.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:37.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.08:11:37.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.08:11:37.96$vc4f8/va=1,8 2006.176.08:11:37.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.176.08:11:37.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.176.08:11:37.96#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:37.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:37.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:37.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:37.96#ibcon#enter wrdev, iclass 36, count 2 2006.176.08:11:37.96#ibcon#first serial, iclass 36, count 2 2006.176.08:11:37.96#ibcon#enter sib2, iclass 36, count 2 2006.176.08:11:37.96#ibcon#flushed, iclass 36, count 2 2006.176.08:11:37.96#ibcon#about to write, iclass 36, count 2 2006.176.08:11:37.96#ibcon#wrote, iclass 36, count 2 2006.176.08:11:37.96#ibcon#about to read 3, iclass 36, count 2 2006.176.08:11:37.98#ibcon#read 3, iclass 36, count 2 2006.176.08:11:37.98#ibcon#about to read 4, iclass 36, count 2 2006.176.08:11:37.98#ibcon#read 4, iclass 36, count 2 2006.176.08:11:37.98#ibcon#about to read 5, iclass 36, count 2 2006.176.08:11:37.98#ibcon#read 5, iclass 36, count 2 2006.176.08:11:37.98#ibcon#about to read 6, iclass 36, count 2 2006.176.08:11:37.98#ibcon#read 6, iclass 36, count 2 2006.176.08:11:37.98#ibcon#end of sib2, iclass 36, count 2 2006.176.08:11:37.98#ibcon#*mode == 0, iclass 36, count 2 2006.176.08:11:37.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.176.08:11:37.98#ibcon#[25=AT01-08\r\n] 2006.176.08:11:37.98#ibcon#*before write, iclass 36, count 2 2006.176.08:11:37.98#ibcon#enter sib2, iclass 36, count 2 2006.176.08:11:37.98#ibcon#flushed, iclass 36, count 2 2006.176.08:11:37.98#ibcon#about to write, iclass 36, count 2 2006.176.08:11:37.98#ibcon#wrote, iclass 36, count 2 2006.176.08:11:37.98#ibcon#about to read 3, iclass 36, count 2 2006.176.08:11:38.01#ibcon#read 3, iclass 36, count 2 2006.176.08:11:38.01#ibcon#about to read 4, iclass 36, count 2 2006.176.08:11:38.01#ibcon#read 4, iclass 36, count 2 2006.176.08:11:38.01#ibcon#about to read 5, iclass 36, count 2 2006.176.08:11:38.01#ibcon#read 5, iclass 36, count 2 2006.176.08:11:38.01#ibcon#about to read 6, iclass 36, count 2 2006.176.08:11:38.01#ibcon#read 6, iclass 36, count 2 2006.176.08:11:38.01#ibcon#end of sib2, iclass 36, count 2 2006.176.08:11:38.01#ibcon#*after write, iclass 36, count 2 2006.176.08:11:38.01#ibcon#*before return 0, iclass 36, count 2 2006.176.08:11:38.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:38.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:38.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.176.08:11:38.01#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:38.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:38.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:38.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:38.13#ibcon#enter wrdev, iclass 36, count 0 2006.176.08:11:38.13#ibcon#first serial, iclass 36, count 0 2006.176.08:11:38.13#ibcon#enter sib2, iclass 36, count 0 2006.176.08:11:38.13#ibcon#flushed, iclass 36, count 0 2006.176.08:11:38.13#ibcon#about to write, iclass 36, count 0 2006.176.08:11:38.13#ibcon#wrote, iclass 36, count 0 2006.176.08:11:38.13#ibcon#about to read 3, iclass 36, count 0 2006.176.08:11:38.15#ibcon#read 3, iclass 36, count 0 2006.176.08:11:38.15#ibcon#about to read 4, iclass 36, count 0 2006.176.08:11:38.15#ibcon#read 4, iclass 36, count 0 2006.176.08:11:38.15#ibcon#about to read 5, iclass 36, count 0 2006.176.08:11:38.15#ibcon#read 5, iclass 36, count 0 2006.176.08:11:38.15#ibcon#about to read 6, iclass 36, count 0 2006.176.08:11:38.15#ibcon#read 6, iclass 36, count 0 2006.176.08:11:38.15#ibcon#end of sib2, iclass 36, count 0 2006.176.08:11:38.15#ibcon#*mode == 0, iclass 36, count 0 2006.176.08:11:38.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.08:11:38.15#ibcon#[25=USB\r\n] 2006.176.08:11:38.15#ibcon#*before write, iclass 36, count 0 2006.176.08:11:38.15#ibcon#enter sib2, iclass 36, count 0 2006.176.08:11:38.15#ibcon#flushed, iclass 36, count 0 2006.176.08:11:38.15#ibcon#about to write, iclass 36, count 0 2006.176.08:11:38.15#ibcon#wrote, iclass 36, count 0 2006.176.08:11:38.15#ibcon#about to read 3, iclass 36, count 0 2006.176.08:11:38.18#ibcon#read 3, iclass 36, count 0 2006.176.08:11:38.18#ibcon#about to read 4, iclass 36, count 0 2006.176.08:11:38.18#ibcon#read 4, iclass 36, count 0 2006.176.08:11:38.18#ibcon#about to read 5, iclass 36, count 0 2006.176.08:11:38.18#ibcon#read 5, iclass 36, count 0 2006.176.08:11:38.18#ibcon#about to read 6, iclass 36, count 0 2006.176.08:11:38.18#ibcon#read 6, iclass 36, count 0 2006.176.08:11:38.18#ibcon#end of sib2, iclass 36, count 0 2006.176.08:11:38.18#ibcon#*after write, iclass 36, count 0 2006.176.08:11:38.18#ibcon#*before return 0, iclass 36, count 0 2006.176.08:11:38.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:38.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:38.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.08:11:38.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.08:11:38.18$vc4f8/valo=2,572.99 2006.176.08:11:38.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.08:11:38.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.08:11:38.18#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:38.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:38.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:38.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:38.18#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:11:38.18#ibcon#first serial, iclass 38, count 0 2006.176.08:11:38.18#ibcon#enter sib2, iclass 38, count 0 2006.176.08:11:38.18#ibcon#flushed, iclass 38, count 0 2006.176.08:11:38.18#ibcon#about to write, iclass 38, count 0 2006.176.08:11:38.18#ibcon#wrote, iclass 38, count 0 2006.176.08:11:38.18#ibcon#about to read 3, iclass 38, count 0 2006.176.08:11:38.20#ibcon#read 3, iclass 38, count 0 2006.176.08:11:38.20#ibcon#about to read 4, iclass 38, count 0 2006.176.08:11:38.20#ibcon#read 4, iclass 38, count 0 2006.176.08:11:38.20#ibcon#about to read 5, iclass 38, count 0 2006.176.08:11:38.20#ibcon#read 5, iclass 38, count 0 2006.176.08:11:38.20#ibcon#about to read 6, iclass 38, count 0 2006.176.08:11:38.20#ibcon#read 6, iclass 38, count 0 2006.176.08:11:38.20#ibcon#end of sib2, iclass 38, count 0 2006.176.08:11:38.20#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:11:38.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:11:38.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:11:38.20#ibcon#*before write, iclass 38, count 0 2006.176.08:11:38.20#ibcon#enter sib2, iclass 38, count 0 2006.176.08:11:38.20#ibcon#flushed, iclass 38, count 0 2006.176.08:11:38.20#ibcon#about to write, iclass 38, count 0 2006.176.08:11:38.20#ibcon#wrote, iclass 38, count 0 2006.176.08:11:38.20#ibcon#about to read 3, iclass 38, count 0 2006.176.08:11:38.24#ibcon#read 3, iclass 38, count 0 2006.176.08:11:38.24#ibcon#about to read 4, iclass 38, count 0 2006.176.08:11:38.24#ibcon#read 4, iclass 38, count 0 2006.176.08:11:38.24#ibcon#about to read 5, iclass 38, count 0 2006.176.08:11:38.24#ibcon#read 5, iclass 38, count 0 2006.176.08:11:38.24#ibcon#about to read 6, iclass 38, count 0 2006.176.08:11:38.24#ibcon#read 6, iclass 38, count 0 2006.176.08:11:38.24#ibcon#end of sib2, iclass 38, count 0 2006.176.08:11:38.24#ibcon#*after write, iclass 38, count 0 2006.176.08:11:38.24#ibcon#*before return 0, iclass 38, count 0 2006.176.08:11:38.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:38.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:38.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:11:38.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:11:38.24$vc4f8/va=2,7 2006.176.08:11:38.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.08:11:38.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.08:11:38.24#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:38.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:38.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:38.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:38.30#ibcon#enter wrdev, iclass 40, count 2 2006.176.08:11:38.30#ibcon#first serial, iclass 40, count 2 2006.176.08:11:38.30#ibcon#enter sib2, iclass 40, count 2 2006.176.08:11:38.30#ibcon#flushed, iclass 40, count 2 2006.176.08:11:38.30#ibcon#about to write, iclass 40, count 2 2006.176.08:11:38.30#ibcon#wrote, iclass 40, count 2 2006.176.08:11:38.30#ibcon#about to read 3, iclass 40, count 2 2006.176.08:11:38.32#ibcon#read 3, iclass 40, count 2 2006.176.08:11:38.32#ibcon#about to read 4, iclass 40, count 2 2006.176.08:11:38.32#ibcon#read 4, iclass 40, count 2 2006.176.08:11:38.32#ibcon#about to read 5, iclass 40, count 2 2006.176.08:11:38.32#ibcon#read 5, iclass 40, count 2 2006.176.08:11:38.32#ibcon#about to read 6, iclass 40, count 2 2006.176.08:11:38.32#ibcon#read 6, iclass 40, count 2 2006.176.08:11:38.32#ibcon#end of sib2, iclass 40, count 2 2006.176.08:11:38.32#ibcon#*mode == 0, iclass 40, count 2 2006.176.08:11:38.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.08:11:38.32#ibcon#[25=AT02-07\r\n] 2006.176.08:11:38.32#ibcon#*before write, iclass 40, count 2 2006.176.08:11:38.32#ibcon#enter sib2, iclass 40, count 2 2006.176.08:11:38.32#ibcon#flushed, iclass 40, count 2 2006.176.08:11:38.32#ibcon#about to write, iclass 40, count 2 2006.176.08:11:38.32#ibcon#wrote, iclass 40, count 2 2006.176.08:11:38.32#ibcon#about to read 3, iclass 40, count 2 2006.176.08:11:38.35#ibcon#read 3, iclass 40, count 2 2006.176.08:11:38.35#ibcon#about to read 4, iclass 40, count 2 2006.176.08:11:38.35#ibcon#read 4, iclass 40, count 2 2006.176.08:11:38.35#ibcon#about to read 5, iclass 40, count 2 2006.176.08:11:38.35#ibcon#read 5, iclass 40, count 2 2006.176.08:11:38.35#ibcon#about to read 6, iclass 40, count 2 2006.176.08:11:38.35#ibcon#read 6, iclass 40, count 2 2006.176.08:11:38.35#ibcon#end of sib2, iclass 40, count 2 2006.176.08:11:38.35#ibcon#*after write, iclass 40, count 2 2006.176.08:11:38.35#ibcon#*before return 0, iclass 40, count 2 2006.176.08:11:38.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:38.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:38.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.08:11:38.35#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:38.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:38.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:38.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:38.47#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:11:38.47#ibcon#first serial, iclass 40, count 0 2006.176.08:11:38.47#ibcon#enter sib2, iclass 40, count 0 2006.176.08:11:38.47#ibcon#flushed, iclass 40, count 0 2006.176.08:11:38.47#ibcon#about to write, iclass 40, count 0 2006.176.08:11:38.47#ibcon#wrote, iclass 40, count 0 2006.176.08:11:38.47#ibcon#about to read 3, iclass 40, count 0 2006.176.08:11:38.49#ibcon#read 3, iclass 40, count 0 2006.176.08:11:38.49#ibcon#about to read 4, iclass 40, count 0 2006.176.08:11:38.49#ibcon#read 4, iclass 40, count 0 2006.176.08:11:38.49#ibcon#about to read 5, iclass 40, count 0 2006.176.08:11:38.49#ibcon#read 5, iclass 40, count 0 2006.176.08:11:38.49#ibcon#about to read 6, iclass 40, count 0 2006.176.08:11:38.49#ibcon#read 6, iclass 40, count 0 2006.176.08:11:38.49#ibcon#end of sib2, iclass 40, count 0 2006.176.08:11:38.49#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:11:38.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:11:38.49#ibcon#[25=USB\r\n] 2006.176.08:11:38.49#ibcon#*before write, iclass 40, count 0 2006.176.08:11:38.49#ibcon#enter sib2, iclass 40, count 0 2006.176.08:11:38.49#ibcon#flushed, iclass 40, count 0 2006.176.08:11:38.49#ibcon#about to write, iclass 40, count 0 2006.176.08:11:38.49#ibcon#wrote, iclass 40, count 0 2006.176.08:11:38.49#ibcon#about to read 3, iclass 40, count 0 2006.176.08:11:38.52#ibcon#read 3, iclass 40, count 0 2006.176.08:11:38.52#ibcon#about to read 4, iclass 40, count 0 2006.176.08:11:38.52#ibcon#read 4, iclass 40, count 0 2006.176.08:11:38.52#ibcon#about to read 5, iclass 40, count 0 2006.176.08:11:38.52#ibcon#read 5, iclass 40, count 0 2006.176.08:11:38.52#ibcon#about to read 6, iclass 40, count 0 2006.176.08:11:38.52#ibcon#read 6, iclass 40, count 0 2006.176.08:11:38.52#ibcon#end of sib2, iclass 40, count 0 2006.176.08:11:38.52#ibcon#*after write, iclass 40, count 0 2006.176.08:11:38.52#ibcon#*before return 0, iclass 40, count 0 2006.176.08:11:38.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:38.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:38.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:11:38.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:11:38.52$vc4f8/valo=3,672.99 2006.176.08:11:38.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.08:11:38.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.08:11:38.52#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:38.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:38.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:38.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:38.52#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:11:38.52#ibcon#first serial, iclass 4, count 0 2006.176.08:11:38.52#ibcon#enter sib2, iclass 4, count 0 2006.176.08:11:38.52#ibcon#flushed, iclass 4, count 0 2006.176.08:11:38.52#ibcon#about to write, iclass 4, count 0 2006.176.08:11:38.52#ibcon#wrote, iclass 4, count 0 2006.176.08:11:38.52#ibcon#about to read 3, iclass 4, count 0 2006.176.08:11:38.54#ibcon#read 3, iclass 4, count 0 2006.176.08:11:38.54#ibcon#about to read 4, iclass 4, count 0 2006.176.08:11:38.54#ibcon#read 4, iclass 4, count 0 2006.176.08:11:38.54#ibcon#about to read 5, iclass 4, count 0 2006.176.08:11:38.54#ibcon#read 5, iclass 4, count 0 2006.176.08:11:38.54#ibcon#about to read 6, iclass 4, count 0 2006.176.08:11:38.54#ibcon#read 6, iclass 4, count 0 2006.176.08:11:38.54#ibcon#end of sib2, iclass 4, count 0 2006.176.08:11:38.54#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:11:38.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:11:38.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:11:38.54#ibcon#*before write, iclass 4, count 0 2006.176.08:11:38.54#ibcon#enter sib2, iclass 4, count 0 2006.176.08:11:38.54#ibcon#flushed, iclass 4, count 0 2006.176.08:11:38.54#ibcon#about to write, iclass 4, count 0 2006.176.08:11:38.54#ibcon#wrote, iclass 4, count 0 2006.176.08:11:38.54#ibcon#about to read 3, iclass 4, count 0 2006.176.08:11:38.58#ibcon#read 3, iclass 4, count 0 2006.176.08:11:38.58#ibcon#about to read 4, iclass 4, count 0 2006.176.08:11:38.58#ibcon#read 4, iclass 4, count 0 2006.176.08:11:38.58#ibcon#about to read 5, iclass 4, count 0 2006.176.08:11:38.58#ibcon#read 5, iclass 4, count 0 2006.176.08:11:38.58#ibcon#about to read 6, iclass 4, count 0 2006.176.08:11:38.58#ibcon#read 6, iclass 4, count 0 2006.176.08:11:38.58#ibcon#end of sib2, iclass 4, count 0 2006.176.08:11:38.58#ibcon#*after write, iclass 4, count 0 2006.176.08:11:38.58#ibcon#*before return 0, iclass 4, count 0 2006.176.08:11:38.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:38.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:38.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:11:38.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:11:38.58$vc4f8/va=3,6 2006.176.08:11:38.58#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.08:11:38.58#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.08:11:38.58#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:38.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:38.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:38.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:38.64#ibcon#enter wrdev, iclass 6, count 2 2006.176.08:11:38.64#ibcon#first serial, iclass 6, count 2 2006.176.08:11:38.64#ibcon#enter sib2, iclass 6, count 2 2006.176.08:11:38.64#ibcon#flushed, iclass 6, count 2 2006.176.08:11:38.64#ibcon#about to write, iclass 6, count 2 2006.176.08:11:38.64#ibcon#wrote, iclass 6, count 2 2006.176.08:11:38.64#ibcon#about to read 3, iclass 6, count 2 2006.176.08:11:38.66#ibcon#read 3, iclass 6, count 2 2006.176.08:11:38.66#ibcon#about to read 4, iclass 6, count 2 2006.176.08:11:38.66#ibcon#read 4, iclass 6, count 2 2006.176.08:11:38.66#ibcon#about to read 5, iclass 6, count 2 2006.176.08:11:38.66#ibcon#read 5, iclass 6, count 2 2006.176.08:11:38.66#ibcon#about to read 6, iclass 6, count 2 2006.176.08:11:38.66#ibcon#read 6, iclass 6, count 2 2006.176.08:11:38.66#ibcon#end of sib2, iclass 6, count 2 2006.176.08:11:38.66#ibcon#*mode == 0, iclass 6, count 2 2006.176.08:11:38.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.08:11:38.66#ibcon#[25=AT03-06\r\n] 2006.176.08:11:38.66#ibcon#*before write, iclass 6, count 2 2006.176.08:11:38.66#ibcon#enter sib2, iclass 6, count 2 2006.176.08:11:38.66#ibcon#flushed, iclass 6, count 2 2006.176.08:11:38.66#ibcon#about to write, iclass 6, count 2 2006.176.08:11:38.66#ibcon#wrote, iclass 6, count 2 2006.176.08:11:38.66#ibcon#about to read 3, iclass 6, count 2 2006.176.08:11:38.69#ibcon#read 3, iclass 6, count 2 2006.176.08:11:38.69#ibcon#about to read 4, iclass 6, count 2 2006.176.08:11:38.69#ibcon#read 4, iclass 6, count 2 2006.176.08:11:38.69#ibcon#about to read 5, iclass 6, count 2 2006.176.08:11:38.69#ibcon#read 5, iclass 6, count 2 2006.176.08:11:38.69#ibcon#about to read 6, iclass 6, count 2 2006.176.08:11:38.69#ibcon#read 6, iclass 6, count 2 2006.176.08:11:38.69#ibcon#end of sib2, iclass 6, count 2 2006.176.08:11:38.69#ibcon#*after write, iclass 6, count 2 2006.176.08:11:38.69#ibcon#*before return 0, iclass 6, count 2 2006.176.08:11:38.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:38.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:38.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.08:11:38.69#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:38.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:38.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:38.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:38.81#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:11:38.81#ibcon#first serial, iclass 6, count 0 2006.176.08:11:38.81#ibcon#enter sib2, iclass 6, count 0 2006.176.08:11:38.81#ibcon#flushed, iclass 6, count 0 2006.176.08:11:38.81#ibcon#about to write, iclass 6, count 0 2006.176.08:11:38.81#ibcon#wrote, iclass 6, count 0 2006.176.08:11:38.81#ibcon#about to read 3, iclass 6, count 0 2006.176.08:11:38.83#ibcon#read 3, iclass 6, count 0 2006.176.08:11:38.83#ibcon#about to read 4, iclass 6, count 0 2006.176.08:11:38.83#ibcon#read 4, iclass 6, count 0 2006.176.08:11:38.83#ibcon#about to read 5, iclass 6, count 0 2006.176.08:11:38.83#ibcon#read 5, iclass 6, count 0 2006.176.08:11:38.83#ibcon#about to read 6, iclass 6, count 0 2006.176.08:11:38.83#ibcon#read 6, iclass 6, count 0 2006.176.08:11:38.83#ibcon#end of sib2, iclass 6, count 0 2006.176.08:11:38.83#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:11:38.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:11:38.83#ibcon#[25=USB\r\n] 2006.176.08:11:38.83#ibcon#*before write, iclass 6, count 0 2006.176.08:11:38.83#ibcon#enter sib2, iclass 6, count 0 2006.176.08:11:38.83#ibcon#flushed, iclass 6, count 0 2006.176.08:11:38.83#ibcon#about to write, iclass 6, count 0 2006.176.08:11:38.83#ibcon#wrote, iclass 6, count 0 2006.176.08:11:38.83#ibcon#about to read 3, iclass 6, count 0 2006.176.08:11:38.86#ibcon#read 3, iclass 6, count 0 2006.176.08:11:38.86#ibcon#about to read 4, iclass 6, count 0 2006.176.08:11:38.86#ibcon#read 4, iclass 6, count 0 2006.176.08:11:38.86#ibcon#about to read 5, iclass 6, count 0 2006.176.08:11:38.86#ibcon#read 5, iclass 6, count 0 2006.176.08:11:38.86#ibcon#about to read 6, iclass 6, count 0 2006.176.08:11:38.86#ibcon#read 6, iclass 6, count 0 2006.176.08:11:38.86#ibcon#end of sib2, iclass 6, count 0 2006.176.08:11:38.86#ibcon#*after write, iclass 6, count 0 2006.176.08:11:38.86#ibcon#*before return 0, iclass 6, count 0 2006.176.08:11:38.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:38.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:38.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:11:38.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:11:38.86$vc4f8/valo=4,832.99 2006.176.08:11:38.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.08:11:38.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.08:11:38.86#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:38.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:38.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:38.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:38.86#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:11:38.86#ibcon#first serial, iclass 10, count 0 2006.176.08:11:38.86#ibcon#enter sib2, iclass 10, count 0 2006.176.08:11:38.86#ibcon#flushed, iclass 10, count 0 2006.176.08:11:38.86#ibcon#about to write, iclass 10, count 0 2006.176.08:11:38.86#ibcon#wrote, iclass 10, count 0 2006.176.08:11:38.86#ibcon#about to read 3, iclass 10, count 0 2006.176.08:11:38.88#ibcon#read 3, iclass 10, count 0 2006.176.08:11:38.88#ibcon#about to read 4, iclass 10, count 0 2006.176.08:11:38.88#ibcon#read 4, iclass 10, count 0 2006.176.08:11:38.88#ibcon#about to read 5, iclass 10, count 0 2006.176.08:11:38.88#ibcon#read 5, iclass 10, count 0 2006.176.08:11:38.88#ibcon#about to read 6, iclass 10, count 0 2006.176.08:11:38.88#ibcon#read 6, iclass 10, count 0 2006.176.08:11:38.88#ibcon#end of sib2, iclass 10, count 0 2006.176.08:11:38.88#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:11:38.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:11:38.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:11:38.88#ibcon#*before write, iclass 10, count 0 2006.176.08:11:38.88#ibcon#enter sib2, iclass 10, count 0 2006.176.08:11:38.88#ibcon#flushed, iclass 10, count 0 2006.176.08:11:38.88#ibcon#about to write, iclass 10, count 0 2006.176.08:11:38.88#ibcon#wrote, iclass 10, count 0 2006.176.08:11:38.88#ibcon#about to read 3, iclass 10, count 0 2006.176.08:11:38.92#ibcon#read 3, iclass 10, count 0 2006.176.08:11:38.92#ibcon#about to read 4, iclass 10, count 0 2006.176.08:11:38.92#ibcon#read 4, iclass 10, count 0 2006.176.08:11:38.92#ibcon#about to read 5, iclass 10, count 0 2006.176.08:11:38.92#ibcon#read 5, iclass 10, count 0 2006.176.08:11:38.92#ibcon#about to read 6, iclass 10, count 0 2006.176.08:11:38.92#ibcon#read 6, iclass 10, count 0 2006.176.08:11:38.92#ibcon#end of sib2, iclass 10, count 0 2006.176.08:11:38.92#ibcon#*after write, iclass 10, count 0 2006.176.08:11:38.92#ibcon#*before return 0, iclass 10, count 0 2006.176.08:11:38.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:38.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:38.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:11:38.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:11:38.92$vc4f8/va=4,7 2006.176.08:11:38.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.08:11:38.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.08:11:38.92#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:38.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:38.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:38.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:38.98#ibcon#enter wrdev, iclass 12, count 2 2006.176.08:11:38.98#ibcon#first serial, iclass 12, count 2 2006.176.08:11:38.98#ibcon#enter sib2, iclass 12, count 2 2006.176.08:11:38.98#ibcon#flushed, iclass 12, count 2 2006.176.08:11:38.98#ibcon#about to write, iclass 12, count 2 2006.176.08:11:38.98#ibcon#wrote, iclass 12, count 2 2006.176.08:11:38.98#ibcon#about to read 3, iclass 12, count 2 2006.176.08:11:39.00#ibcon#read 3, iclass 12, count 2 2006.176.08:11:39.00#ibcon#about to read 4, iclass 12, count 2 2006.176.08:11:39.00#ibcon#read 4, iclass 12, count 2 2006.176.08:11:39.00#ibcon#about to read 5, iclass 12, count 2 2006.176.08:11:39.00#ibcon#read 5, iclass 12, count 2 2006.176.08:11:39.00#ibcon#about to read 6, iclass 12, count 2 2006.176.08:11:39.00#ibcon#read 6, iclass 12, count 2 2006.176.08:11:39.00#ibcon#end of sib2, iclass 12, count 2 2006.176.08:11:39.00#ibcon#*mode == 0, iclass 12, count 2 2006.176.08:11:39.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.08:11:39.00#ibcon#[25=AT04-07\r\n] 2006.176.08:11:39.00#ibcon#*before write, iclass 12, count 2 2006.176.08:11:39.00#ibcon#enter sib2, iclass 12, count 2 2006.176.08:11:39.00#ibcon#flushed, iclass 12, count 2 2006.176.08:11:39.00#ibcon#about to write, iclass 12, count 2 2006.176.08:11:39.00#ibcon#wrote, iclass 12, count 2 2006.176.08:11:39.00#ibcon#about to read 3, iclass 12, count 2 2006.176.08:11:39.03#ibcon#read 3, iclass 12, count 2 2006.176.08:11:39.03#ibcon#about to read 4, iclass 12, count 2 2006.176.08:11:39.03#ibcon#read 4, iclass 12, count 2 2006.176.08:11:39.03#ibcon#about to read 5, iclass 12, count 2 2006.176.08:11:39.03#ibcon#read 5, iclass 12, count 2 2006.176.08:11:39.03#ibcon#about to read 6, iclass 12, count 2 2006.176.08:11:39.03#ibcon#read 6, iclass 12, count 2 2006.176.08:11:39.03#ibcon#end of sib2, iclass 12, count 2 2006.176.08:11:39.03#ibcon#*after write, iclass 12, count 2 2006.176.08:11:39.03#ibcon#*before return 0, iclass 12, count 2 2006.176.08:11:39.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:39.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:39.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.08:11:39.03#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:39.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:39.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:39.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:39.15#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:11:39.15#ibcon#first serial, iclass 12, count 0 2006.176.08:11:39.15#ibcon#enter sib2, iclass 12, count 0 2006.176.08:11:39.15#ibcon#flushed, iclass 12, count 0 2006.176.08:11:39.15#ibcon#about to write, iclass 12, count 0 2006.176.08:11:39.15#ibcon#wrote, iclass 12, count 0 2006.176.08:11:39.15#ibcon#about to read 3, iclass 12, count 0 2006.176.08:11:39.17#ibcon#read 3, iclass 12, count 0 2006.176.08:11:39.17#ibcon#about to read 4, iclass 12, count 0 2006.176.08:11:39.17#ibcon#read 4, iclass 12, count 0 2006.176.08:11:39.17#ibcon#about to read 5, iclass 12, count 0 2006.176.08:11:39.17#ibcon#read 5, iclass 12, count 0 2006.176.08:11:39.17#ibcon#about to read 6, iclass 12, count 0 2006.176.08:11:39.17#ibcon#read 6, iclass 12, count 0 2006.176.08:11:39.17#ibcon#end of sib2, iclass 12, count 0 2006.176.08:11:39.17#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:11:39.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:11:39.17#ibcon#[25=USB\r\n] 2006.176.08:11:39.17#ibcon#*before write, iclass 12, count 0 2006.176.08:11:39.17#ibcon#enter sib2, iclass 12, count 0 2006.176.08:11:39.17#ibcon#flushed, iclass 12, count 0 2006.176.08:11:39.17#ibcon#about to write, iclass 12, count 0 2006.176.08:11:39.17#ibcon#wrote, iclass 12, count 0 2006.176.08:11:39.17#ibcon#about to read 3, iclass 12, count 0 2006.176.08:11:39.20#ibcon#read 3, iclass 12, count 0 2006.176.08:11:39.20#ibcon#about to read 4, iclass 12, count 0 2006.176.08:11:39.20#ibcon#read 4, iclass 12, count 0 2006.176.08:11:39.20#ibcon#about to read 5, iclass 12, count 0 2006.176.08:11:39.20#ibcon#read 5, iclass 12, count 0 2006.176.08:11:39.20#ibcon#about to read 6, iclass 12, count 0 2006.176.08:11:39.20#ibcon#read 6, iclass 12, count 0 2006.176.08:11:39.20#ibcon#end of sib2, iclass 12, count 0 2006.176.08:11:39.20#ibcon#*after write, iclass 12, count 0 2006.176.08:11:39.20#ibcon#*before return 0, iclass 12, count 0 2006.176.08:11:39.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:39.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:39.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:11:39.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:11:39.20$vc4f8/valo=5,652.99 2006.176.08:11:39.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.08:11:39.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.08:11:39.20#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:39.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:39.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:39.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:39.20#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:11:39.20#ibcon#first serial, iclass 14, count 0 2006.176.08:11:39.20#ibcon#enter sib2, iclass 14, count 0 2006.176.08:11:39.20#ibcon#flushed, iclass 14, count 0 2006.176.08:11:39.20#ibcon#about to write, iclass 14, count 0 2006.176.08:11:39.20#ibcon#wrote, iclass 14, count 0 2006.176.08:11:39.20#ibcon#about to read 3, iclass 14, count 0 2006.176.08:11:39.22#ibcon#read 3, iclass 14, count 0 2006.176.08:11:39.22#ibcon#about to read 4, iclass 14, count 0 2006.176.08:11:39.22#ibcon#read 4, iclass 14, count 0 2006.176.08:11:39.22#ibcon#about to read 5, iclass 14, count 0 2006.176.08:11:39.22#ibcon#read 5, iclass 14, count 0 2006.176.08:11:39.22#ibcon#about to read 6, iclass 14, count 0 2006.176.08:11:39.22#ibcon#read 6, iclass 14, count 0 2006.176.08:11:39.22#ibcon#end of sib2, iclass 14, count 0 2006.176.08:11:39.22#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:11:39.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:11:39.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:11:39.22#ibcon#*before write, iclass 14, count 0 2006.176.08:11:39.22#ibcon#enter sib2, iclass 14, count 0 2006.176.08:11:39.22#ibcon#flushed, iclass 14, count 0 2006.176.08:11:39.22#ibcon#about to write, iclass 14, count 0 2006.176.08:11:39.22#ibcon#wrote, iclass 14, count 0 2006.176.08:11:39.22#ibcon#about to read 3, iclass 14, count 0 2006.176.08:11:39.26#ibcon#read 3, iclass 14, count 0 2006.176.08:11:39.26#ibcon#about to read 4, iclass 14, count 0 2006.176.08:11:39.26#ibcon#read 4, iclass 14, count 0 2006.176.08:11:39.26#ibcon#about to read 5, iclass 14, count 0 2006.176.08:11:39.26#ibcon#read 5, iclass 14, count 0 2006.176.08:11:39.26#ibcon#about to read 6, iclass 14, count 0 2006.176.08:11:39.26#ibcon#read 6, iclass 14, count 0 2006.176.08:11:39.26#ibcon#end of sib2, iclass 14, count 0 2006.176.08:11:39.26#ibcon#*after write, iclass 14, count 0 2006.176.08:11:39.26#ibcon#*before return 0, iclass 14, count 0 2006.176.08:11:39.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:39.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:39.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:11:39.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:11:39.26$vc4f8/va=5,7 2006.176.08:11:39.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.08:11:39.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.08:11:39.26#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:39.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:39.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:39.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:39.32#ibcon#enter wrdev, iclass 16, count 2 2006.176.08:11:39.32#ibcon#first serial, iclass 16, count 2 2006.176.08:11:39.32#ibcon#enter sib2, iclass 16, count 2 2006.176.08:11:39.32#ibcon#flushed, iclass 16, count 2 2006.176.08:11:39.32#ibcon#about to write, iclass 16, count 2 2006.176.08:11:39.32#ibcon#wrote, iclass 16, count 2 2006.176.08:11:39.32#ibcon#about to read 3, iclass 16, count 2 2006.176.08:11:39.34#ibcon#read 3, iclass 16, count 2 2006.176.08:11:39.34#ibcon#about to read 4, iclass 16, count 2 2006.176.08:11:39.34#ibcon#read 4, iclass 16, count 2 2006.176.08:11:39.34#ibcon#about to read 5, iclass 16, count 2 2006.176.08:11:39.34#ibcon#read 5, iclass 16, count 2 2006.176.08:11:39.34#ibcon#about to read 6, iclass 16, count 2 2006.176.08:11:39.34#ibcon#read 6, iclass 16, count 2 2006.176.08:11:39.34#ibcon#end of sib2, iclass 16, count 2 2006.176.08:11:39.34#ibcon#*mode == 0, iclass 16, count 2 2006.176.08:11:39.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.08:11:39.34#ibcon#[25=AT05-07\r\n] 2006.176.08:11:39.34#ibcon#*before write, iclass 16, count 2 2006.176.08:11:39.34#ibcon#enter sib2, iclass 16, count 2 2006.176.08:11:39.34#ibcon#flushed, iclass 16, count 2 2006.176.08:11:39.34#ibcon#about to write, iclass 16, count 2 2006.176.08:11:39.34#ibcon#wrote, iclass 16, count 2 2006.176.08:11:39.34#ibcon#about to read 3, iclass 16, count 2 2006.176.08:11:39.37#ibcon#read 3, iclass 16, count 2 2006.176.08:11:39.37#ibcon#about to read 4, iclass 16, count 2 2006.176.08:11:39.37#ibcon#read 4, iclass 16, count 2 2006.176.08:11:39.37#ibcon#about to read 5, iclass 16, count 2 2006.176.08:11:39.37#ibcon#read 5, iclass 16, count 2 2006.176.08:11:39.37#ibcon#about to read 6, iclass 16, count 2 2006.176.08:11:39.37#ibcon#read 6, iclass 16, count 2 2006.176.08:11:39.37#ibcon#end of sib2, iclass 16, count 2 2006.176.08:11:39.37#ibcon#*after write, iclass 16, count 2 2006.176.08:11:39.37#ibcon#*before return 0, iclass 16, count 2 2006.176.08:11:39.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:39.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:39.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.08:11:39.37#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:39.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:39.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:39.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:39.49#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:11:39.49#ibcon#first serial, iclass 16, count 0 2006.176.08:11:39.49#ibcon#enter sib2, iclass 16, count 0 2006.176.08:11:39.49#ibcon#flushed, iclass 16, count 0 2006.176.08:11:39.49#ibcon#about to write, iclass 16, count 0 2006.176.08:11:39.49#ibcon#wrote, iclass 16, count 0 2006.176.08:11:39.49#ibcon#about to read 3, iclass 16, count 0 2006.176.08:11:39.51#ibcon#read 3, iclass 16, count 0 2006.176.08:11:39.51#ibcon#about to read 4, iclass 16, count 0 2006.176.08:11:39.51#ibcon#read 4, iclass 16, count 0 2006.176.08:11:39.51#ibcon#about to read 5, iclass 16, count 0 2006.176.08:11:39.51#ibcon#read 5, iclass 16, count 0 2006.176.08:11:39.51#ibcon#about to read 6, iclass 16, count 0 2006.176.08:11:39.51#ibcon#read 6, iclass 16, count 0 2006.176.08:11:39.51#ibcon#end of sib2, iclass 16, count 0 2006.176.08:11:39.51#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:11:39.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:11:39.51#ibcon#[25=USB\r\n] 2006.176.08:11:39.51#ibcon#*before write, iclass 16, count 0 2006.176.08:11:39.51#ibcon#enter sib2, iclass 16, count 0 2006.176.08:11:39.51#ibcon#flushed, iclass 16, count 0 2006.176.08:11:39.51#ibcon#about to write, iclass 16, count 0 2006.176.08:11:39.51#ibcon#wrote, iclass 16, count 0 2006.176.08:11:39.51#ibcon#about to read 3, iclass 16, count 0 2006.176.08:11:39.54#ibcon#read 3, iclass 16, count 0 2006.176.08:11:39.54#ibcon#about to read 4, iclass 16, count 0 2006.176.08:11:39.54#ibcon#read 4, iclass 16, count 0 2006.176.08:11:39.54#ibcon#about to read 5, iclass 16, count 0 2006.176.08:11:39.54#ibcon#read 5, iclass 16, count 0 2006.176.08:11:39.54#ibcon#about to read 6, iclass 16, count 0 2006.176.08:11:39.54#ibcon#read 6, iclass 16, count 0 2006.176.08:11:39.54#ibcon#end of sib2, iclass 16, count 0 2006.176.08:11:39.54#ibcon#*after write, iclass 16, count 0 2006.176.08:11:39.54#ibcon#*before return 0, iclass 16, count 0 2006.176.08:11:39.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:39.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:39.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:11:39.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:11:39.54$vc4f8/valo=6,772.99 2006.176.08:11:39.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.08:11:39.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.08:11:39.54#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:39.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:39.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:39.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:39.54#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:11:39.54#ibcon#first serial, iclass 18, count 0 2006.176.08:11:39.54#ibcon#enter sib2, iclass 18, count 0 2006.176.08:11:39.54#ibcon#flushed, iclass 18, count 0 2006.176.08:11:39.54#ibcon#about to write, iclass 18, count 0 2006.176.08:11:39.54#ibcon#wrote, iclass 18, count 0 2006.176.08:11:39.54#ibcon#about to read 3, iclass 18, count 0 2006.176.08:11:39.56#ibcon#read 3, iclass 18, count 0 2006.176.08:11:39.56#ibcon#about to read 4, iclass 18, count 0 2006.176.08:11:39.56#ibcon#read 4, iclass 18, count 0 2006.176.08:11:39.56#ibcon#about to read 5, iclass 18, count 0 2006.176.08:11:39.56#ibcon#read 5, iclass 18, count 0 2006.176.08:11:39.56#ibcon#about to read 6, iclass 18, count 0 2006.176.08:11:39.56#ibcon#read 6, iclass 18, count 0 2006.176.08:11:39.56#ibcon#end of sib2, iclass 18, count 0 2006.176.08:11:39.56#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:11:39.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:11:39.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:11:39.56#ibcon#*before write, iclass 18, count 0 2006.176.08:11:39.56#ibcon#enter sib2, iclass 18, count 0 2006.176.08:11:39.56#ibcon#flushed, iclass 18, count 0 2006.176.08:11:39.56#ibcon#about to write, iclass 18, count 0 2006.176.08:11:39.56#ibcon#wrote, iclass 18, count 0 2006.176.08:11:39.56#ibcon#about to read 3, iclass 18, count 0 2006.176.08:11:39.60#ibcon#read 3, iclass 18, count 0 2006.176.08:11:39.60#ibcon#about to read 4, iclass 18, count 0 2006.176.08:11:39.60#ibcon#read 4, iclass 18, count 0 2006.176.08:11:39.60#ibcon#about to read 5, iclass 18, count 0 2006.176.08:11:39.60#ibcon#read 5, iclass 18, count 0 2006.176.08:11:39.60#ibcon#about to read 6, iclass 18, count 0 2006.176.08:11:39.60#ibcon#read 6, iclass 18, count 0 2006.176.08:11:39.60#ibcon#end of sib2, iclass 18, count 0 2006.176.08:11:39.60#ibcon#*after write, iclass 18, count 0 2006.176.08:11:39.60#ibcon#*before return 0, iclass 18, count 0 2006.176.08:11:39.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:39.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:39.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:11:39.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:11:39.60$vc4f8/va=6,6 2006.176.08:11:39.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.08:11:39.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.08:11:39.60#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:39.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:11:39.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:11:39.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:11:39.66#ibcon#enter wrdev, iclass 20, count 2 2006.176.08:11:39.66#ibcon#first serial, iclass 20, count 2 2006.176.08:11:39.66#ibcon#enter sib2, iclass 20, count 2 2006.176.08:11:39.66#ibcon#flushed, iclass 20, count 2 2006.176.08:11:39.66#ibcon#about to write, iclass 20, count 2 2006.176.08:11:39.66#ibcon#wrote, iclass 20, count 2 2006.176.08:11:39.66#ibcon#about to read 3, iclass 20, count 2 2006.176.08:11:39.68#ibcon#read 3, iclass 20, count 2 2006.176.08:11:39.68#ibcon#about to read 4, iclass 20, count 2 2006.176.08:11:39.68#ibcon#read 4, iclass 20, count 2 2006.176.08:11:39.68#ibcon#about to read 5, iclass 20, count 2 2006.176.08:11:39.68#ibcon#read 5, iclass 20, count 2 2006.176.08:11:39.68#ibcon#about to read 6, iclass 20, count 2 2006.176.08:11:39.68#ibcon#read 6, iclass 20, count 2 2006.176.08:11:39.68#ibcon#end of sib2, iclass 20, count 2 2006.176.08:11:39.68#ibcon#*mode == 0, iclass 20, count 2 2006.176.08:11:39.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.08:11:39.68#ibcon#[25=AT06-06\r\n] 2006.176.08:11:39.68#ibcon#*before write, iclass 20, count 2 2006.176.08:11:39.68#ibcon#enter sib2, iclass 20, count 2 2006.176.08:11:39.68#ibcon#flushed, iclass 20, count 2 2006.176.08:11:39.68#ibcon#about to write, iclass 20, count 2 2006.176.08:11:39.68#ibcon#wrote, iclass 20, count 2 2006.176.08:11:39.68#ibcon#about to read 3, iclass 20, count 2 2006.176.08:11:39.71#ibcon#read 3, iclass 20, count 2 2006.176.08:11:39.71#ibcon#about to read 4, iclass 20, count 2 2006.176.08:11:39.71#ibcon#read 4, iclass 20, count 2 2006.176.08:11:39.71#ibcon#about to read 5, iclass 20, count 2 2006.176.08:11:39.71#ibcon#read 5, iclass 20, count 2 2006.176.08:11:39.71#ibcon#about to read 6, iclass 20, count 2 2006.176.08:11:39.71#ibcon#read 6, iclass 20, count 2 2006.176.08:11:39.71#ibcon#end of sib2, iclass 20, count 2 2006.176.08:11:39.71#ibcon#*after write, iclass 20, count 2 2006.176.08:11:39.71#ibcon#*before return 0, iclass 20, count 2 2006.176.08:11:39.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:11:39.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:11:39.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.08:11:39.71#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:39.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:11:39.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:11:39.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:11:39.83#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:11:39.83#ibcon#first serial, iclass 20, count 0 2006.176.08:11:39.83#ibcon#enter sib2, iclass 20, count 0 2006.176.08:11:39.83#ibcon#flushed, iclass 20, count 0 2006.176.08:11:39.83#ibcon#about to write, iclass 20, count 0 2006.176.08:11:39.83#ibcon#wrote, iclass 20, count 0 2006.176.08:11:39.83#ibcon#about to read 3, iclass 20, count 0 2006.176.08:11:39.85#ibcon#read 3, iclass 20, count 0 2006.176.08:11:39.85#ibcon#about to read 4, iclass 20, count 0 2006.176.08:11:39.85#ibcon#read 4, iclass 20, count 0 2006.176.08:11:39.85#ibcon#about to read 5, iclass 20, count 0 2006.176.08:11:39.85#ibcon#read 5, iclass 20, count 0 2006.176.08:11:39.85#ibcon#about to read 6, iclass 20, count 0 2006.176.08:11:39.85#ibcon#read 6, iclass 20, count 0 2006.176.08:11:39.85#ibcon#end of sib2, iclass 20, count 0 2006.176.08:11:39.85#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:11:39.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:11:39.85#ibcon#[25=USB\r\n] 2006.176.08:11:39.85#ibcon#*before write, iclass 20, count 0 2006.176.08:11:39.85#ibcon#enter sib2, iclass 20, count 0 2006.176.08:11:39.85#ibcon#flushed, iclass 20, count 0 2006.176.08:11:39.85#ibcon#about to write, iclass 20, count 0 2006.176.08:11:39.85#ibcon#wrote, iclass 20, count 0 2006.176.08:11:39.85#ibcon#about to read 3, iclass 20, count 0 2006.176.08:11:39.88#ibcon#read 3, iclass 20, count 0 2006.176.08:11:39.88#ibcon#about to read 4, iclass 20, count 0 2006.176.08:11:39.88#ibcon#read 4, iclass 20, count 0 2006.176.08:11:39.88#ibcon#about to read 5, iclass 20, count 0 2006.176.08:11:39.88#ibcon#read 5, iclass 20, count 0 2006.176.08:11:39.88#ibcon#about to read 6, iclass 20, count 0 2006.176.08:11:39.88#ibcon#read 6, iclass 20, count 0 2006.176.08:11:39.88#ibcon#end of sib2, iclass 20, count 0 2006.176.08:11:39.88#ibcon#*after write, iclass 20, count 0 2006.176.08:11:39.88#ibcon#*before return 0, iclass 20, count 0 2006.176.08:11:39.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:11:39.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:11:39.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:11:39.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:11:39.88$vc4f8/valo=7,832.99 2006.176.08:11:39.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.08:11:39.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.08:11:39.88#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:39.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:11:39.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:11:39.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:11:39.88#ibcon#enter wrdev, iclass 22, count 0 2006.176.08:11:39.88#ibcon#first serial, iclass 22, count 0 2006.176.08:11:39.88#ibcon#enter sib2, iclass 22, count 0 2006.176.08:11:39.88#ibcon#flushed, iclass 22, count 0 2006.176.08:11:39.88#ibcon#about to write, iclass 22, count 0 2006.176.08:11:39.88#ibcon#wrote, iclass 22, count 0 2006.176.08:11:39.88#ibcon#about to read 3, iclass 22, count 0 2006.176.08:11:39.90#ibcon#read 3, iclass 22, count 0 2006.176.08:11:39.90#ibcon#about to read 4, iclass 22, count 0 2006.176.08:11:39.90#ibcon#read 4, iclass 22, count 0 2006.176.08:11:39.90#ibcon#about to read 5, iclass 22, count 0 2006.176.08:11:39.90#ibcon#read 5, iclass 22, count 0 2006.176.08:11:39.90#ibcon#about to read 6, iclass 22, count 0 2006.176.08:11:39.90#ibcon#read 6, iclass 22, count 0 2006.176.08:11:39.90#ibcon#end of sib2, iclass 22, count 0 2006.176.08:11:39.90#ibcon#*mode == 0, iclass 22, count 0 2006.176.08:11:39.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.08:11:39.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:11:39.90#ibcon#*before write, iclass 22, count 0 2006.176.08:11:39.90#ibcon#enter sib2, iclass 22, count 0 2006.176.08:11:39.90#ibcon#flushed, iclass 22, count 0 2006.176.08:11:39.90#ibcon#about to write, iclass 22, count 0 2006.176.08:11:39.90#ibcon#wrote, iclass 22, count 0 2006.176.08:11:39.90#ibcon#about to read 3, iclass 22, count 0 2006.176.08:11:39.94#ibcon#read 3, iclass 22, count 0 2006.176.08:11:39.94#ibcon#about to read 4, iclass 22, count 0 2006.176.08:11:39.94#ibcon#read 4, iclass 22, count 0 2006.176.08:11:39.94#ibcon#about to read 5, iclass 22, count 0 2006.176.08:11:39.94#ibcon#read 5, iclass 22, count 0 2006.176.08:11:39.94#ibcon#about to read 6, iclass 22, count 0 2006.176.08:11:39.94#ibcon#read 6, iclass 22, count 0 2006.176.08:11:39.94#ibcon#end of sib2, iclass 22, count 0 2006.176.08:11:39.94#ibcon#*after write, iclass 22, count 0 2006.176.08:11:39.94#ibcon#*before return 0, iclass 22, count 0 2006.176.08:11:39.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:11:39.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:11:39.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.08:11:39.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.08:11:39.94$vc4f8/va=7,6 2006.176.08:11:39.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.08:11:39.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.08:11:39.94#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:39.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:11:40.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:11:40.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:11:40.00#ibcon#enter wrdev, iclass 24, count 2 2006.176.08:11:40.00#ibcon#first serial, iclass 24, count 2 2006.176.08:11:40.00#ibcon#enter sib2, iclass 24, count 2 2006.176.08:11:40.00#ibcon#flushed, iclass 24, count 2 2006.176.08:11:40.00#ibcon#about to write, iclass 24, count 2 2006.176.08:11:40.00#ibcon#wrote, iclass 24, count 2 2006.176.08:11:40.00#ibcon#about to read 3, iclass 24, count 2 2006.176.08:11:40.02#ibcon#read 3, iclass 24, count 2 2006.176.08:11:40.02#ibcon#about to read 4, iclass 24, count 2 2006.176.08:11:40.02#ibcon#read 4, iclass 24, count 2 2006.176.08:11:40.02#ibcon#about to read 5, iclass 24, count 2 2006.176.08:11:40.02#ibcon#read 5, iclass 24, count 2 2006.176.08:11:40.02#ibcon#about to read 6, iclass 24, count 2 2006.176.08:11:40.02#ibcon#read 6, iclass 24, count 2 2006.176.08:11:40.02#ibcon#end of sib2, iclass 24, count 2 2006.176.08:11:40.02#ibcon#*mode == 0, iclass 24, count 2 2006.176.08:11:40.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.08:11:40.02#ibcon#[25=AT07-06\r\n] 2006.176.08:11:40.02#ibcon#*before write, iclass 24, count 2 2006.176.08:11:40.02#ibcon#enter sib2, iclass 24, count 2 2006.176.08:11:40.02#ibcon#flushed, iclass 24, count 2 2006.176.08:11:40.02#ibcon#about to write, iclass 24, count 2 2006.176.08:11:40.02#ibcon#wrote, iclass 24, count 2 2006.176.08:11:40.02#ibcon#about to read 3, iclass 24, count 2 2006.176.08:11:40.05#ibcon#read 3, iclass 24, count 2 2006.176.08:11:40.05#ibcon#about to read 4, iclass 24, count 2 2006.176.08:11:40.05#ibcon#read 4, iclass 24, count 2 2006.176.08:11:40.05#ibcon#about to read 5, iclass 24, count 2 2006.176.08:11:40.05#ibcon#read 5, iclass 24, count 2 2006.176.08:11:40.05#ibcon#about to read 6, iclass 24, count 2 2006.176.08:11:40.05#ibcon#read 6, iclass 24, count 2 2006.176.08:11:40.05#ibcon#end of sib2, iclass 24, count 2 2006.176.08:11:40.05#ibcon#*after write, iclass 24, count 2 2006.176.08:11:40.05#ibcon#*before return 0, iclass 24, count 2 2006.176.08:11:40.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:11:40.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:11:40.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.08:11:40.05#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:40.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:11:40.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:11:40.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:11:40.17#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:11:40.17#ibcon#first serial, iclass 24, count 0 2006.176.08:11:40.17#ibcon#enter sib2, iclass 24, count 0 2006.176.08:11:40.17#ibcon#flushed, iclass 24, count 0 2006.176.08:11:40.17#ibcon#about to write, iclass 24, count 0 2006.176.08:11:40.17#ibcon#wrote, iclass 24, count 0 2006.176.08:11:40.17#ibcon#about to read 3, iclass 24, count 0 2006.176.08:11:40.19#ibcon#read 3, iclass 24, count 0 2006.176.08:11:40.19#ibcon#about to read 4, iclass 24, count 0 2006.176.08:11:40.19#ibcon#read 4, iclass 24, count 0 2006.176.08:11:40.19#ibcon#about to read 5, iclass 24, count 0 2006.176.08:11:40.19#ibcon#read 5, iclass 24, count 0 2006.176.08:11:40.19#ibcon#about to read 6, iclass 24, count 0 2006.176.08:11:40.19#ibcon#read 6, iclass 24, count 0 2006.176.08:11:40.19#ibcon#end of sib2, iclass 24, count 0 2006.176.08:11:40.19#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:11:40.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:11:40.19#ibcon#[25=USB\r\n] 2006.176.08:11:40.19#ibcon#*before write, iclass 24, count 0 2006.176.08:11:40.19#ibcon#enter sib2, iclass 24, count 0 2006.176.08:11:40.19#ibcon#flushed, iclass 24, count 0 2006.176.08:11:40.19#ibcon#about to write, iclass 24, count 0 2006.176.08:11:40.19#ibcon#wrote, iclass 24, count 0 2006.176.08:11:40.19#ibcon#about to read 3, iclass 24, count 0 2006.176.08:11:40.22#ibcon#read 3, iclass 24, count 0 2006.176.08:11:40.22#ibcon#about to read 4, iclass 24, count 0 2006.176.08:11:40.22#ibcon#read 4, iclass 24, count 0 2006.176.08:11:40.22#ibcon#about to read 5, iclass 24, count 0 2006.176.08:11:40.22#ibcon#read 5, iclass 24, count 0 2006.176.08:11:40.22#ibcon#about to read 6, iclass 24, count 0 2006.176.08:11:40.22#ibcon#read 6, iclass 24, count 0 2006.176.08:11:40.22#ibcon#end of sib2, iclass 24, count 0 2006.176.08:11:40.22#ibcon#*after write, iclass 24, count 0 2006.176.08:11:40.22#ibcon#*before return 0, iclass 24, count 0 2006.176.08:11:40.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:11:40.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:11:40.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:11:40.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:11:40.22$vc4f8/valo=8,852.99 2006.176.08:11:40.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.08:11:40.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.08:11:40.22#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:40.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:11:40.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:11:40.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:11:40.22#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:11:40.22#ibcon#first serial, iclass 26, count 0 2006.176.08:11:40.22#ibcon#enter sib2, iclass 26, count 0 2006.176.08:11:40.22#ibcon#flushed, iclass 26, count 0 2006.176.08:11:40.22#ibcon#about to write, iclass 26, count 0 2006.176.08:11:40.22#ibcon#wrote, iclass 26, count 0 2006.176.08:11:40.22#ibcon#about to read 3, iclass 26, count 0 2006.176.08:11:40.24#ibcon#read 3, iclass 26, count 0 2006.176.08:11:40.24#ibcon#about to read 4, iclass 26, count 0 2006.176.08:11:40.24#ibcon#read 4, iclass 26, count 0 2006.176.08:11:40.24#ibcon#about to read 5, iclass 26, count 0 2006.176.08:11:40.24#ibcon#read 5, iclass 26, count 0 2006.176.08:11:40.24#ibcon#about to read 6, iclass 26, count 0 2006.176.08:11:40.24#ibcon#read 6, iclass 26, count 0 2006.176.08:11:40.24#ibcon#end of sib2, iclass 26, count 0 2006.176.08:11:40.24#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:11:40.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:11:40.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:11:40.24#ibcon#*before write, iclass 26, count 0 2006.176.08:11:40.24#ibcon#enter sib2, iclass 26, count 0 2006.176.08:11:40.24#ibcon#flushed, iclass 26, count 0 2006.176.08:11:40.24#ibcon#about to write, iclass 26, count 0 2006.176.08:11:40.24#ibcon#wrote, iclass 26, count 0 2006.176.08:11:40.24#ibcon#about to read 3, iclass 26, count 0 2006.176.08:11:40.28#ibcon#read 3, iclass 26, count 0 2006.176.08:11:40.28#ibcon#about to read 4, iclass 26, count 0 2006.176.08:11:40.28#ibcon#read 4, iclass 26, count 0 2006.176.08:11:40.28#ibcon#about to read 5, iclass 26, count 0 2006.176.08:11:40.28#ibcon#read 5, iclass 26, count 0 2006.176.08:11:40.28#ibcon#about to read 6, iclass 26, count 0 2006.176.08:11:40.28#ibcon#read 6, iclass 26, count 0 2006.176.08:11:40.28#ibcon#end of sib2, iclass 26, count 0 2006.176.08:11:40.28#ibcon#*after write, iclass 26, count 0 2006.176.08:11:40.28#ibcon#*before return 0, iclass 26, count 0 2006.176.08:11:40.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:11:40.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:11:40.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:11:40.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:11:40.28$vc4f8/va=8,6 2006.176.08:11:40.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.08:11:40.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.08:11:40.28#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:40.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:11:40.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:11:40.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:11:40.34#ibcon#enter wrdev, iclass 28, count 2 2006.176.08:11:40.34#ibcon#first serial, iclass 28, count 2 2006.176.08:11:40.34#ibcon#enter sib2, iclass 28, count 2 2006.176.08:11:40.34#ibcon#flushed, iclass 28, count 2 2006.176.08:11:40.34#ibcon#about to write, iclass 28, count 2 2006.176.08:11:40.34#ibcon#wrote, iclass 28, count 2 2006.176.08:11:40.34#ibcon#about to read 3, iclass 28, count 2 2006.176.08:11:40.36#ibcon#read 3, iclass 28, count 2 2006.176.08:11:40.36#ibcon#about to read 4, iclass 28, count 2 2006.176.08:11:40.36#ibcon#read 4, iclass 28, count 2 2006.176.08:11:40.36#ibcon#about to read 5, iclass 28, count 2 2006.176.08:11:40.36#ibcon#read 5, iclass 28, count 2 2006.176.08:11:40.36#ibcon#about to read 6, iclass 28, count 2 2006.176.08:11:40.36#ibcon#read 6, iclass 28, count 2 2006.176.08:11:40.36#ibcon#end of sib2, iclass 28, count 2 2006.176.08:11:40.36#ibcon#*mode == 0, iclass 28, count 2 2006.176.08:11:40.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.08:11:40.36#ibcon#[25=AT08-06\r\n] 2006.176.08:11:40.36#ibcon#*before write, iclass 28, count 2 2006.176.08:11:40.36#ibcon#enter sib2, iclass 28, count 2 2006.176.08:11:40.36#ibcon#flushed, iclass 28, count 2 2006.176.08:11:40.36#ibcon#about to write, iclass 28, count 2 2006.176.08:11:40.36#ibcon#wrote, iclass 28, count 2 2006.176.08:11:40.36#ibcon#about to read 3, iclass 28, count 2 2006.176.08:11:40.39#ibcon#read 3, iclass 28, count 2 2006.176.08:11:40.39#ibcon#about to read 4, iclass 28, count 2 2006.176.08:11:40.39#ibcon#read 4, iclass 28, count 2 2006.176.08:11:40.39#ibcon#about to read 5, iclass 28, count 2 2006.176.08:11:40.39#ibcon#read 5, iclass 28, count 2 2006.176.08:11:40.39#ibcon#about to read 6, iclass 28, count 2 2006.176.08:11:40.39#ibcon#read 6, iclass 28, count 2 2006.176.08:11:40.39#ibcon#end of sib2, iclass 28, count 2 2006.176.08:11:40.39#ibcon#*after write, iclass 28, count 2 2006.176.08:11:40.39#ibcon#*before return 0, iclass 28, count 2 2006.176.08:11:40.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:11:40.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:11:40.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.08:11:40.39#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:40.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:11:40.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:11:40.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:11:40.51#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:11:40.51#ibcon#first serial, iclass 28, count 0 2006.176.08:11:40.51#ibcon#enter sib2, iclass 28, count 0 2006.176.08:11:40.51#ibcon#flushed, iclass 28, count 0 2006.176.08:11:40.51#ibcon#about to write, iclass 28, count 0 2006.176.08:11:40.51#ibcon#wrote, iclass 28, count 0 2006.176.08:11:40.51#ibcon#about to read 3, iclass 28, count 0 2006.176.08:11:40.53#ibcon#read 3, iclass 28, count 0 2006.176.08:11:40.53#ibcon#about to read 4, iclass 28, count 0 2006.176.08:11:40.53#ibcon#read 4, iclass 28, count 0 2006.176.08:11:40.53#ibcon#about to read 5, iclass 28, count 0 2006.176.08:11:40.53#ibcon#read 5, iclass 28, count 0 2006.176.08:11:40.53#ibcon#about to read 6, iclass 28, count 0 2006.176.08:11:40.53#ibcon#read 6, iclass 28, count 0 2006.176.08:11:40.53#ibcon#end of sib2, iclass 28, count 0 2006.176.08:11:40.53#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:11:40.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:11:40.53#ibcon#[25=USB\r\n] 2006.176.08:11:40.53#ibcon#*before write, iclass 28, count 0 2006.176.08:11:40.53#ibcon#enter sib2, iclass 28, count 0 2006.176.08:11:40.53#ibcon#flushed, iclass 28, count 0 2006.176.08:11:40.53#ibcon#about to write, iclass 28, count 0 2006.176.08:11:40.53#ibcon#wrote, iclass 28, count 0 2006.176.08:11:40.53#ibcon#about to read 3, iclass 28, count 0 2006.176.08:11:40.56#ibcon#read 3, iclass 28, count 0 2006.176.08:11:40.56#ibcon#about to read 4, iclass 28, count 0 2006.176.08:11:40.56#ibcon#read 4, iclass 28, count 0 2006.176.08:11:40.56#ibcon#about to read 5, iclass 28, count 0 2006.176.08:11:40.56#ibcon#read 5, iclass 28, count 0 2006.176.08:11:40.56#ibcon#about to read 6, iclass 28, count 0 2006.176.08:11:40.56#ibcon#read 6, iclass 28, count 0 2006.176.08:11:40.56#ibcon#end of sib2, iclass 28, count 0 2006.176.08:11:40.56#ibcon#*after write, iclass 28, count 0 2006.176.08:11:40.56#ibcon#*before return 0, iclass 28, count 0 2006.176.08:11:40.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:11:40.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:11:40.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:11:40.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:11:40.56$vc4f8/vblo=1,632.99 2006.176.08:11:40.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.08:11:40.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.08:11:40.56#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:40.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:11:40.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:11:40.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:11:40.56#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:11:40.56#ibcon#first serial, iclass 30, count 0 2006.176.08:11:40.56#ibcon#enter sib2, iclass 30, count 0 2006.176.08:11:40.56#ibcon#flushed, iclass 30, count 0 2006.176.08:11:40.56#ibcon#about to write, iclass 30, count 0 2006.176.08:11:40.56#ibcon#wrote, iclass 30, count 0 2006.176.08:11:40.56#ibcon#about to read 3, iclass 30, count 0 2006.176.08:11:40.58#ibcon#read 3, iclass 30, count 0 2006.176.08:11:40.58#ibcon#about to read 4, iclass 30, count 0 2006.176.08:11:40.58#ibcon#read 4, iclass 30, count 0 2006.176.08:11:40.58#ibcon#about to read 5, iclass 30, count 0 2006.176.08:11:40.58#ibcon#read 5, iclass 30, count 0 2006.176.08:11:40.58#ibcon#about to read 6, iclass 30, count 0 2006.176.08:11:40.58#ibcon#read 6, iclass 30, count 0 2006.176.08:11:40.58#ibcon#end of sib2, iclass 30, count 0 2006.176.08:11:40.58#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:11:40.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:11:40.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:11:40.58#ibcon#*before write, iclass 30, count 0 2006.176.08:11:40.58#ibcon#enter sib2, iclass 30, count 0 2006.176.08:11:40.58#ibcon#flushed, iclass 30, count 0 2006.176.08:11:40.58#ibcon#about to write, iclass 30, count 0 2006.176.08:11:40.58#ibcon#wrote, iclass 30, count 0 2006.176.08:11:40.58#ibcon#about to read 3, iclass 30, count 0 2006.176.08:11:40.62#ibcon#read 3, iclass 30, count 0 2006.176.08:11:40.62#ibcon#about to read 4, iclass 30, count 0 2006.176.08:11:40.62#ibcon#read 4, iclass 30, count 0 2006.176.08:11:40.62#ibcon#about to read 5, iclass 30, count 0 2006.176.08:11:40.62#ibcon#read 5, iclass 30, count 0 2006.176.08:11:40.62#ibcon#about to read 6, iclass 30, count 0 2006.176.08:11:40.62#ibcon#read 6, iclass 30, count 0 2006.176.08:11:40.62#ibcon#end of sib2, iclass 30, count 0 2006.176.08:11:40.62#ibcon#*after write, iclass 30, count 0 2006.176.08:11:40.62#ibcon#*before return 0, iclass 30, count 0 2006.176.08:11:40.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:11:40.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:11:40.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:11:40.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:11:40.62$vc4f8/vb=1,4 2006.176.08:11:40.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.176.08:11:40.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.176.08:11:40.62#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:40.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:11:40.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:11:40.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:11:40.62#ibcon#enter wrdev, iclass 32, count 2 2006.176.08:11:40.62#ibcon#first serial, iclass 32, count 2 2006.176.08:11:40.62#ibcon#enter sib2, iclass 32, count 2 2006.176.08:11:40.62#ibcon#flushed, iclass 32, count 2 2006.176.08:11:40.62#ibcon#about to write, iclass 32, count 2 2006.176.08:11:40.62#ibcon#wrote, iclass 32, count 2 2006.176.08:11:40.62#ibcon#about to read 3, iclass 32, count 2 2006.176.08:11:40.64#ibcon#read 3, iclass 32, count 2 2006.176.08:11:40.64#ibcon#about to read 4, iclass 32, count 2 2006.176.08:11:40.64#ibcon#read 4, iclass 32, count 2 2006.176.08:11:40.64#ibcon#about to read 5, iclass 32, count 2 2006.176.08:11:40.64#ibcon#read 5, iclass 32, count 2 2006.176.08:11:40.64#ibcon#about to read 6, iclass 32, count 2 2006.176.08:11:40.64#ibcon#read 6, iclass 32, count 2 2006.176.08:11:40.64#ibcon#end of sib2, iclass 32, count 2 2006.176.08:11:40.64#ibcon#*mode == 0, iclass 32, count 2 2006.176.08:11:40.64#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.176.08:11:40.64#ibcon#[27=AT01-04\r\n] 2006.176.08:11:40.64#ibcon#*before write, iclass 32, count 2 2006.176.08:11:40.64#ibcon#enter sib2, iclass 32, count 2 2006.176.08:11:40.64#ibcon#flushed, iclass 32, count 2 2006.176.08:11:40.64#ibcon#about to write, iclass 32, count 2 2006.176.08:11:40.64#ibcon#wrote, iclass 32, count 2 2006.176.08:11:40.64#ibcon#about to read 3, iclass 32, count 2 2006.176.08:11:40.67#ibcon#read 3, iclass 32, count 2 2006.176.08:11:40.67#ibcon#about to read 4, iclass 32, count 2 2006.176.08:11:40.67#ibcon#read 4, iclass 32, count 2 2006.176.08:11:40.67#ibcon#about to read 5, iclass 32, count 2 2006.176.08:11:40.67#ibcon#read 5, iclass 32, count 2 2006.176.08:11:40.67#ibcon#about to read 6, iclass 32, count 2 2006.176.08:11:40.67#ibcon#read 6, iclass 32, count 2 2006.176.08:11:40.67#ibcon#end of sib2, iclass 32, count 2 2006.176.08:11:40.67#ibcon#*after write, iclass 32, count 2 2006.176.08:11:40.67#ibcon#*before return 0, iclass 32, count 2 2006.176.08:11:40.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:11:40.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:11:40.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.176.08:11:40.67#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:40.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:11:40.79#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:11:40.79#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:11:40.79#ibcon#enter wrdev, iclass 32, count 0 2006.176.08:11:40.79#ibcon#first serial, iclass 32, count 0 2006.176.08:11:40.79#ibcon#enter sib2, iclass 32, count 0 2006.176.08:11:40.79#ibcon#flushed, iclass 32, count 0 2006.176.08:11:40.79#ibcon#about to write, iclass 32, count 0 2006.176.08:11:40.79#ibcon#wrote, iclass 32, count 0 2006.176.08:11:40.79#ibcon#about to read 3, iclass 32, count 0 2006.176.08:11:40.81#ibcon#read 3, iclass 32, count 0 2006.176.08:11:40.81#ibcon#about to read 4, iclass 32, count 0 2006.176.08:11:40.81#ibcon#read 4, iclass 32, count 0 2006.176.08:11:40.81#ibcon#about to read 5, iclass 32, count 0 2006.176.08:11:40.81#ibcon#read 5, iclass 32, count 0 2006.176.08:11:40.81#ibcon#about to read 6, iclass 32, count 0 2006.176.08:11:40.81#ibcon#read 6, iclass 32, count 0 2006.176.08:11:40.81#ibcon#end of sib2, iclass 32, count 0 2006.176.08:11:40.81#ibcon#*mode == 0, iclass 32, count 0 2006.176.08:11:40.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.08:11:40.81#ibcon#[27=USB\r\n] 2006.176.08:11:40.81#ibcon#*before write, iclass 32, count 0 2006.176.08:11:40.81#ibcon#enter sib2, iclass 32, count 0 2006.176.08:11:40.81#ibcon#flushed, iclass 32, count 0 2006.176.08:11:40.81#ibcon#about to write, iclass 32, count 0 2006.176.08:11:40.81#ibcon#wrote, iclass 32, count 0 2006.176.08:11:40.81#ibcon#about to read 3, iclass 32, count 0 2006.176.08:11:40.84#ibcon#read 3, iclass 32, count 0 2006.176.08:11:40.84#ibcon#about to read 4, iclass 32, count 0 2006.176.08:11:40.84#ibcon#read 4, iclass 32, count 0 2006.176.08:11:40.84#ibcon#about to read 5, iclass 32, count 0 2006.176.08:11:40.84#ibcon#read 5, iclass 32, count 0 2006.176.08:11:40.84#ibcon#about to read 6, iclass 32, count 0 2006.176.08:11:40.84#ibcon#read 6, iclass 32, count 0 2006.176.08:11:40.84#ibcon#end of sib2, iclass 32, count 0 2006.176.08:11:40.84#ibcon#*after write, iclass 32, count 0 2006.176.08:11:40.84#ibcon#*before return 0, iclass 32, count 0 2006.176.08:11:40.84#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:11:40.84#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:11:40.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.08:11:40.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.08:11:40.84$vc4f8/vblo=2,640.99 2006.176.08:11:40.84#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.08:11:40.84#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.08:11:40.84#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:40.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:40.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:40.84#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:40.84#ibcon#enter wrdev, iclass 34, count 0 2006.176.08:11:40.84#ibcon#first serial, iclass 34, count 0 2006.176.08:11:40.84#ibcon#enter sib2, iclass 34, count 0 2006.176.08:11:40.84#ibcon#flushed, iclass 34, count 0 2006.176.08:11:40.84#ibcon#about to write, iclass 34, count 0 2006.176.08:11:40.84#ibcon#wrote, iclass 34, count 0 2006.176.08:11:40.84#ibcon#about to read 3, iclass 34, count 0 2006.176.08:11:40.86#ibcon#read 3, iclass 34, count 0 2006.176.08:11:40.86#ibcon#about to read 4, iclass 34, count 0 2006.176.08:11:40.86#ibcon#read 4, iclass 34, count 0 2006.176.08:11:40.86#ibcon#about to read 5, iclass 34, count 0 2006.176.08:11:40.86#ibcon#read 5, iclass 34, count 0 2006.176.08:11:40.86#ibcon#about to read 6, iclass 34, count 0 2006.176.08:11:40.86#ibcon#read 6, iclass 34, count 0 2006.176.08:11:40.86#ibcon#end of sib2, iclass 34, count 0 2006.176.08:11:40.86#ibcon#*mode == 0, iclass 34, count 0 2006.176.08:11:40.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.08:11:40.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:11:40.86#ibcon#*before write, iclass 34, count 0 2006.176.08:11:40.86#ibcon#enter sib2, iclass 34, count 0 2006.176.08:11:40.86#ibcon#flushed, iclass 34, count 0 2006.176.08:11:40.86#ibcon#about to write, iclass 34, count 0 2006.176.08:11:40.86#ibcon#wrote, iclass 34, count 0 2006.176.08:11:40.86#ibcon#about to read 3, iclass 34, count 0 2006.176.08:11:40.90#ibcon#read 3, iclass 34, count 0 2006.176.08:11:40.90#ibcon#about to read 4, iclass 34, count 0 2006.176.08:11:40.90#ibcon#read 4, iclass 34, count 0 2006.176.08:11:40.90#ibcon#about to read 5, iclass 34, count 0 2006.176.08:11:40.90#ibcon#read 5, iclass 34, count 0 2006.176.08:11:40.90#ibcon#about to read 6, iclass 34, count 0 2006.176.08:11:40.90#ibcon#read 6, iclass 34, count 0 2006.176.08:11:40.90#ibcon#end of sib2, iclass 34, count 0 2006.176.08:11:40.90#ibcon#*after write, iclass 34, count 0 2006.176.08:11:40.90#ibcon#*before return 0, iclass 34, count 0 2006.176.08:11:40.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:40.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:11:40.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.08:11:40.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.08:11:40.90$vc4f8/vb=2,4 2006.176.08:11:40.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.176.08:11:40.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.176.08:11:40.90#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:40.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:40.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:40.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:40.96#ibcon#enter wrdev, iclass 36, count 2 2006.176.08:11:40.96#ibcon#first serial, iclass 36, count 2 2006.176.08:11:40.96#ibcon#enter sib2, iclass 36, count 2 2006.176.08:11:40.96#ibcon#flushed, iclass 36, count 2 2006.176.08:11:40.96#ibcon#about to write, iclass 36, count 2 2006.176.08:11:40.96#ibcon#wrote, iclass 36, count 2 2006.176.08:11:40.96#ibcon#about to read 3, iclass 36, count 2 2006.176.08:11:40.98#ibcon#read 3, iclass 36, count 2 2006.176.08:11:40.98#ibcon#about to read 4, iclass 36, count 2 2006.176.08:11:40.98#ibcon#read 4, iclass 36, count 2 2006.176.08:11:40.98#ibcon#about to read 5, iclass 36, count 2 2006.176.08:11:40.98#ibcon#read 5, iclass 36, count 2 2006.176.08:11:40.98#ibcon#about to read 6, iclass 36, count 2 2006.176.08:11:40.98#ibcon#read 6, iclass 36, count 2 2006.176.08:11:40.98#ibcon#end of sib2, iclass 36, count 2 2006.176.08:11:40.98#ibcon#*mode == 0, iclass 36, count 2 2006.176.08:11:40.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.176.08:11:40.98#ibcon#[27=AT02-04\r\n] 2006.176.08:11:40.98#ibcon#*before write, iclass 36, count 2 2006.176.08:11:40.98#ibcon#enter sib2, iclass 36, count 2 2006.176.08:11:40.98#ibcon#flushed, iclass 36, count 2 2006.176.08:11:40.98#ibcon#about to write, iclass 36, count 2 2006.176.08:11:40.98#ibcon#wrote, iclass 36, count 2 2006.176.08:11:40.98#ibcon#about to read 3, iclass 36, count 2 2006.176.08:11:41.01#ibcon#read 3, iclass 36, count 2 2006.176.08:11:41.01#ibcon#about to read 4, iclass 36, count 2 2006.176.08:11:41.01#ibcon#read 4, iclass 36, count 2 2006.176.08:11:41.01#ibcon#about to read 5, iclass 36, count 2 2006.176.08:11:41.01#ibcon#read 5, iclass 36, count 2 2006.176.08:11:41.01#ibcon#about to read 6, iclass 36, count 2 2006.176.08:11:41.01#ibcon#read 6, iclass 36, count 2 2006.176.08:11:41.01#ibcon#end of sib2, iclass 36, count 2 2006.176.08:11:41.01#ibcon#*after write, iclass 36, count 2 2006.176.08:11:41.01#ibcon#*before return 0, iclass 36, count 2 2006.176.08:11:41.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:41.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:11:41.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.176.08:11:41.01#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:41.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:41.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:41.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:41.13#ibcon#enter wrdev, iclass 36, count 0 2006.176.08:11:41.13#ibcon#first serial, iclass 36, count 0 2006.176.08:11:41.13#ibcon#enter sib2, iclass 36, count 0 2006.176.08:11:41.13#ibcon#flushed, iclass 36, count 0 2006.176.08:11:41.13#ibcon#about to write, iclass 36, count 0 2006.176.08:11:41.13#ibcon#wrote, iclass 36, count 0 2006.176.08:11:41.13#ibcon#about to read 3, iclass 36, count 0 2006.176.08:11:41.15#ibcon#read 3, iclass 36, count 0 2006.176.08:11:41.15#ibcon#about to read 4, iclass 36, count 0 2006.176.08:11:41.15#ibcon#read 4, iclass 36, count 0 2006.176.08:11:41.15#ibcon#about to read 5, iclass 36, count 0 2006.176.08:11:41.15#ibcon#read 5, iclass 36, count 0 2006.176.08:11:41.15#ibcon#about to read 6, iclass 36, count 0 2006.176.08:11:41.15#ibcon#read 6, iclass 36, count 0 2006.176.08:11:41.15#ibcon#end of sib2, iclass 36, count 0 2006.176.08:11:41.15#ibcon#*mode == 0, iclass 36, count 0 2006.176.08:11:41.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.08:11:41.15#ibcon#[27=USB\r\n] 2006.176.08:11:41.15#ibcon#*before write, iclass 36, count 0 2006.176.08:11:41.15#ibcon#enter sib2, iclass 36, count 0 2006.176.08:11:41.15#ibcon#flushed, iclass 36, count 0 2006.176.08:11:41.15#ibcon#about to write, iclass 36, count 0 2006.176.08:11:41.15#ibcon#wrote, iclass 36, count 0 2006.176.08:11:41.15#ibcon#about to read 3, iclass 36, count 0 2006.176.08:11:41.18#ibcon#read 3, iclass 36, count 0 2006.176.08:11:41.18#ibcon#about to read 4, iclass 36, count 0 2006.176.08:11:41.18#ibcon#read 4, iclass 36, count 0 2006.176.08:11:41.18#ibcon#about to read 5, iclass 36, count 0 2006.176.08:11:41.18#ibcon#read 5, iclass 36, count 0 2006.176.08:11:41.18#ibcon#about to read 6, iclass 36, count 0 2006.176.08:11:41.18#ibcon#read 6, iclass 36, count 0 2006.176.08:11:41.18#ibcon#end of sib2, iclass 36, count 0 2006.176.08:11:41.18#ibcon#*after write, iclass 36, count 0 2006.176.08:11:41.18#ibcon#*before return 0, iclass 36, count 0 2006.176.08:11:41.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:41.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:11:41.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.08:11:41.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.08:11:41.18$vc4f8/vblo=3,656.99 2006.176.08:11:41.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.08:11:41.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.08:11:41.18#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:41.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:41.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:41.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:41.18#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:11:41.18#ibcon#first serial, iclass 38, count 0 2006.176.08:11:41.18#ibcon#enter sib2, iclass 38, count 0 2006.176.08:11:41.18#ibcon#flushed, iclass 38, count 0 2006.176.08:11:41.18#ibcon#about to write, iclass 38, count 0 2006.176.08:11:41.18#ibcon#wrote, iclass 38, count 0 2006.176.08:11:41.18#ibcon#about to read 3, iclass 38, count 0 2006.176.08:11:41.20#ibcon#read 3, iclass 38, count 0 2006.176.08:11:41.20#ibcon#about to read 4, iclass 38, count 0 2006.176.08:11:41.20#ibcon#read 4, iclass 38, count 0 2006.176.08:11:41.20#ibcon#about to read 5, iclass 38, count 0 2006.176.08:11:41.20#ibcon#read 5, iclass 38, count 0 2006.176.08:11:41.20#ibcon#about to read 6, iclass 38, count 0 2006.176.08:11:41.20#ibcon#read 6, iclass 38, count 0 2006.176.08:11:41.20#ibcon#end of sib2, iclass 38, count 0 2006.176.08:11:41.20#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:11:41.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:11:41.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:11:41.20#ibcon#*before write, iclass 38, count 0 2006.176.08:11:41.20#ibcon#enter sib2, iclass 38, count 0 2006.176.08:11:41.20#ibcon#flushed, iclass 38, count 0 2006.176.08:11:41.20#ibcon#about to write, iclass 38, count 0 2006.176.08:11:41.20#ibcon#wrote, iclass 38, count 0 2006.176.08:11:41.20#ibcon#about to read 3, iclass 38, count 0 2006.176.08:11:41.24#ibcon#read 3, iclass 38, count 0 2006.176.08:11:41.24#ibcon#about to read 4, iclass 38, count 0 2006.176.08:11:41.24#ibcon#read 4, iclass 38, count 0 2006.176.08:11:41.24#ibcon#about to read 5, iclass 38, count 0 2006.176.08:11:41.24#ibcon#read 5, iclass 38, count 0 2006.176.08:11:41.24#ibcon#about to read 6, iclass 38, count 0 2006.176.08:11:41.24#ibcon#read 6, iclass 38, count 0 2006.176.08:11:41.24#ibcon#end of sib2, iclass 38, count 0 2006.176.08:11:41.24#ibcon#*after write, iclass 38, count 0 2006.176.08:11:41.24#ibcon#*before return 0, iclass 38, count 0 2006.176.08:11:41.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:41.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:11:41.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:11:41.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:11:41.24$vc4f8/vb=3,4 2006.176.08:11:41.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.08:11:41.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.08:11:41.24#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:41.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:41.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:41.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:41.30#ibcon#enter wrdev, iclass 40, count 2 2006.176.08:11:41.30#ibcon#first serial, iclass 40, count 2 2006.176.08:11:41.30#ibcon#enter sib2, iclass 40, count 2 2006.176.08:11:41.30#ibcon#flushed, iclass 40, count 2 2006.176.08:11:41.30#ibcon#about to write, iclass 40, count 2 2006.176.08:11:41.30#ibcon#wrote, iclass 40, count 2 2006.176.08:11:41.30#ibcon#about to read 3, iclass 40, count 2 2006.176.08:11:41.32#ibcon#read 3, iclass 40, count 2 2006.176.08:11:41.32#ibcon#about to read 4, iclass 40, count 2 2006.176.08:11:41.32#ibcon#read 4, iclass 40, count 2 2006.176.08:11:41.32#ibcon#about to read 5, iclass 40, count 2 2006.176.08:11:41.32#ibcon#read 5, iclass 40, count 2 2006.176.08:11:41.32#ibcon#about to read 6, iclass 40, count 2 2006.176.08:11:41.32#ibcon#read 6, iclass 40, count 2 2006.176.08:11:41.32#ibcon#end of sib2, iclass 40, count 2 2006.176.08:11:41.32#ibcon#*mode == 0, iclass 40, count 2 2006.176.08:11:41.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.08:11:41.32#ibcon#[27=AT03-04\r\n] 2006.176.08:11:41.32#ibcon#*before write, iclass 40, count 2 2006.176.08:11:41.32#ibcon#enter sib2, iclass 40, count 2 2006.176.08:11:41.32#ibcon#flushed, iclass 40, count 2 2006.176.08:11:41.32#ibcon#about to write, iclass 40, count 2 2006.176.08:11:41.32#ibcon#wrote, iclass 40, count 2 2006.176.08:11:41.32#ibcon#about to read 3, iclass 40, count 2 2006.176.08:11:41.35#ibcon#read 3, iclass 40, count 2 2006.176.08:11:41.35#ibcon#about to read 4, iclass 40, count 2 2006.176.08:11:41.35#ibcon#read 4, iclass 40, count 2 2006.176.08:11:41.35#ibcon#about to read 5, iclass 40, count 2 2006.176.08:11:41.35#ibcon#read 5, iclass 40, count 2 2006.176.08:11:41.35#ibcon#about to read 6, iclass 40, count 2 2006.176.08:11:41.35#ibcon#read 6, iclass 40, count 2 2006.176.08:11:41.35#ibcon#end of sib2, iclass 40, count 2 2006.176.08:11:41.35#ibcon#*after write, iclass 40, count 2 2006.176.08:11:41.35#ibcon#*before return 0, iclass 40, count 2 2006.176.08:11:41.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:41.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:11:41.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.08:11:41.35#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:41.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:41.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:41.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:41.47#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:11:41.47#ibcon#first serial, iclass 40, count 0 2006.176.08:11:41.47#ibcon#enter sib2, iclass 40, count 0 2006.176.08:11:41.47#ibcon#flushed, iclass 40, count 0 2006.176.08:11:41.47#ibcon#about to write, iclass 40, count 0 2006.176.08:11:41.47#ibcon#wrote, iclass 40, count 0 2006.176.08:11:41.47#ibcon#about to read 3, iclass 40, count 0 2006.176.08:11:41.49#ibcon#read 3, iclass 40, count 0 2006.176.08:11:41.49#ibcon#about to read 4, iclass 40, count 0 2006.176.08:11:41.49#ibcon#read 4, iclass 40, count 0 2006.176.08:11:41.49#ibcon#about to read 5, iclass 40, count 0 2006.176.08:11:41.49#ibcon#read 5, iclass 40, count 0 2006.176.08:11:41.49#ibcon#about to read 6, iclass 40, count 0 2006.176.08:11:41.49#ibcon#read 6, iclass 40, count 0 2006.176.08:11:41.49#ibcon#end of sib2, iclass 40, count 0 2006.176.08:11:41.49#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:11:41.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:11:41.49#ibcon#[27=USB\r\n] 2006.176.08:11:41.49#ibcon#*before write, iclass 40, count 0 2006.176.08:11:41.49#ibcon#enter sib2, iclass 40, count 0 2006.176.08:11:41.49#ibcon#flushed, iclass 40, count 0 2006.176.08:11:41.49#ibcon#about to write, iclass 40, count 0 2006.176.08:11:41.49#ibcon#wrote, iclass 40, count 0 2006.176.08:11:41.49#ibcon#about to read 3, iclass 40, count 0 2006.176.08:11:41.52#ibcon#read 3, iclass 40, count 0 2006.176.08:11:41.52#ibcon#about to read 4, iclass 40, count 0 2006.176.08:11:41.52#ibcon#read 4, iclass 40, count 0 2006.176.08:11:41.52#ibcon#about to read 5, iclass 40, count 0 2006.176.08:11:41.52#ibcon#read 5, iclass 40, count 0 2006.176.08:11:41.52#ibcon#about to read 6, iclass 40, count 0 2006.176.08:11:41.52#ibcon#read 6, iclass 40, count 0 2006.176.08:11:41.52#ibcon#end of sib2, iclass 40, count 0 2006.176.08:11:41.52#ibcon#*after write, iclass 40, count 0 2006.176.08:11:41.52#ibcon#*before return 0, iclass 40, count 0 2006.176.08:11:41.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:41.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:11:41.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:11:41.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:11:41.52$vc4f8/vblo=4,712.99 2006.176.08:11:41.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.08:11:41.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.08:11:41.52#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:41.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:41.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:41.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:41.52#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:11:41.52#ibcon#first serial, iclass 4, count 0 2006.176.08:11:41.52#ibcon#enter sib2, iclass 4, count 0 2006.176.08:11:41.52#ibcon#flushed, iclass 4, count 0 2006.176.08:11:41.52#ibcon#about to write, iclass 4, count 0 2006.176.08:11:41.52#ibcon#wrote, iclass 4, count 0 2006.176.08:11:41.52#ibcon#about to read 3, iclass 4, count 0 2006.176.08:11:41.54#ibcon#read 3, iclass 4, count 0 2006.176.08:11:41.54#ibcon#about to read 4, iclass 4, count 0 2006.176.08:11:41.54#ibcon#read 4, iclass 4, count 0 2006.176.08:11:41.54#ibcon#about to read 5, iclass 4, count 0 2006.176.08:11:41.54#ibcon#read 5, iclass 4, count 0 2006.176.08:11:41.54#ibcon#about to read 6, iclass 4, count 0 2006.176.08:11:41.54#ibcon#read 6, iclass 4, count 0 2006.176.08:11:41.54#ibcon#end of sib2, iclass 4, count 0 2006.176.08:11:41.54#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:11:41.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:11:41.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:11:41.54#ibcon#*before write, iclass 4, count 0 2006.176.08:11:41.54#ibcon#enter sib2, iclass 4, count 0 2006.176.08:11:41.54#ibcon#flushed, iclass 4, count 0 2006.176.08:11:41.54#ibcon#about to write, iclass 4, count 0 2006.176.08:11:41.54#ibcon#wrote, iclass 4, count 0 2006.176.08:11:41.54#ibcon#about to read 3, iclass 4, count 0 2006.176.08:11:41.58#ibcon#read 3, iclass 4, count 0 2006.176.08:11:41.58#ibcon#about to read 4, iclass 4, count 0 2006.176.08:11:41.58#ibcon#read 4, iclass 4, count 0 2006.176.08:11:41.58#ibcon#about to read 5, iclass 4, count 0 2006.176.08:11:41.58#ibcon#read 5, iclass 4, count 0 2006.176.08:11:41.58#ibcon#about to read 6, iclass 4, count 0 2006.176.08:11:41.58#ibcon#read 6, iclass 4, count 0 2006.176.08:11:41.58#ibcon#end of sib2, iclass 4, count 0 2006.176.08:11:41.58#ibcon#*after write, iclass 4, count 0 2006.176.08:11:41.58#ibcon#*before return 0, iclass 4, count 0 2006.176.08:11:41.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:41.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:11:41.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:11:41.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:11:41.58$vc4f8/vb=4,4 2006.176.08:11:41.58#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.08:11:41.58#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.08:11:41.58#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:41.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:41.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:41.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:41.64#ibcon#enter wrdev, iclass 6, count 2 2006.176.08:11:41.64#ibcon#first serial, iclass 6, count 2 2006.176.08:11:41.64#ibcon#enter sib2, iclass 6, count 2 2006.176.08:11:41.64#ibcon#flushed, iclass 6, count 2 2006.176.08:11:41.64#ibcon#about to write, iclass 6, count 2 2006.176.08:11:41.64#ibcon#wrote, iclass 6, count 2 2006.176.08:11:41.64#ibcon#about to read 3, iclass 6, count 2 2006.176.08:11:41.66#ibcon#read 3, iclass 6, count 2 2006.176.08:11:41.66#ibcon#about to read 4, iclass 6, count 2 2006.176.08:11:41.66#ibcon#read 4, iclass 6, count 2 2006.176.08:11:41.66#ibcon#about to read 5, iclass 6, count 2 2006.176.08:11:41.66#ibcon#read 5, iclass 6, count 2 2006.176.08:11:41.66#ibcon#about to read 6, iclass 6, count 2 2006.176.08:11:41.66#ibcon#read 6, iclass 6, count 2 2006.176.08:11:41.66#ibcon#end of sib2, iclass 6, count 2 2006.176.08:11:41.66#ibcon#*mode == 0, iclass 6, count 2 2006.176.08:11:41.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.08:11:41.66#ibcon#[27=AT04-04\r\n] 2006.176.08:11:41.66#ibcon#*before write, iclass 6, count 2 2006.176.08:11:41.66#ibcon#enter sib2, iclass 6, count 2 2006.176.08:11:41.66#ibcon#flushed, iclass 6, count 2 2006.176.08:11:41.66#ibcon#about to write, iclass 6, count 2 2006.176.08:11:41.66#ibcon#wrote, iclass 6, count 2 2006.176.08:11:41.66#ibcon#about to read 3, iclass 6, count 2 2006.176.08:11:41.69#ibcon#read 3, iclass 6, count 2 2006.176.08:11:41.69#ibcon#about to read 4, iclass 6, count 2 2006.176.08:11:41.69#ibcon#read 4, iclass 6, count 2 2006.176.08:11:41.69#ibcon#about to read 5, iclass 6, count 2 2006.176.08:11:41.69#ibcon#read 5, iclass 6, count 2 2006.176.08:11:41.69#ibcon#about to read 6, iclass 6, count 2 2006.176.08:11:41.69#ibcon#read 6, iclass 6, count 2 2006.176.08:11:41.69#ibcon#end of sib2, iclass 6, count 2 2006.176.08:11:41.69#ibcon#*after write, iclass 6, count 2 2006.176.08:11:41.69#ibcon#*before return 0, iclass 6, count 2 2006.176.08:11:41.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:41.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:11:41.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.08:11:41.69#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:41.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:41.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:41.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:41.81#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:11:41.81#ibcon#first serial, iclass 6, count 0 2006.176.08:11:41.81#ibcon#enter sib2, iclass 6, count 0 2006.176.08:11:41.81#ibcon#flushed, iclass 6, count 0 2006.176.08:11:41.81#ibcon#about to write, iclass 6, count 0 2006.176.08:11:41.81#ibcon#wrote, iclass 6, count 0 2006.176.08:11:41.81#ibcon#about to read 3, iclass 6, count 0 2006.176.08:11:41.83#ibcon#read 3, iclass 6, count 0 2006.176.08:11:41.83#ibcon#about to read 4, iclass 6, count 0 2006.176.08:11:41.83#ibcon#read 4, iclass 6, count 0 2006.176.08:11:41.83#ibcon#about to read 5, iclass 6, count 0 2006.176.08:11:41.83#ibcon#read 5, iclass 6, count 0 2006.176.08:11:41.83#ibcon#about to read 6, iclass 6, count 0 2006.176.08:11:41.83#ibcon#read 6, iclass 6, count 0 2006.176.08:11:41.83#ibcon#end of sib2, iclass 6, count 0 2006.176.08:11:41.83#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:11:41.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:11:41.83#ibcon#[27=USB\r\n] 2006.176.08:11:41.83#ibcon#*before write, iclass 6, count 0 2006.176.08:11:41.83#ibcon#enter sib2, iclass 6, count 0 2006.176.08:11:41.83#ibcon#flushed, iclass 6, count 0 2006.176.08:11:41.83#ibcon#about to write, iclass 6, count 0 2006.176.08:11:41.83#ibcon#wrote, iclass 6, count 0 2006.176.08:11:41.83#ibcon#about to read 3, iclass 6, count 0 2006.176.08:11:41.86#ibcon#read 3, iclass 6, count 0 2006.176.08:11:41.86#ibcon#about to read 4, iclass 6, count 0 2006.176.08:11:41.86#ibcon#read 4, iclass 6, count 0 2006.176.08:11:41.86#ibcon#about to read 5, iclass 6, count 0 2006.176.08:11:41.86#ibcon#read 5, iclass 6, count 0 2006.176.08:11:41.86#ibcon#about to read 6, iclass 6, count 0 2006.176.08:11:41.86#ibcon#read 6, iclass 6, count 0 2006.176.08:11:41.86#ibcon#end of sib2, iclass 6, count 0 2006.176.08:11:41.86#ibcon#*after write, iclass 6, count 0 2006.176.08:11:41.86#ibcon#*before return 0, iclass 6, count 0 2006.176.08:11:41.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:41.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:11:41.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:11:41.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:11:41.86$vc4f8/vblo=5,744.99 2006.176.08:11:41.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.08:11:41.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.08:11:41.86#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:41.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:41.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:41.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:41.86#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:11:41.86#ibcon#first serial, iclass 10, count 0 2006.176.08:11:41.86#ibcon#enter sib2, iclass 10, count 0 2006.176.08:11:41.86#ibcon#flushed, iclass 10, count 0 2006.176.08:11:41.86#ibcon#about to write, iclass 10, count 0 2006.176.08:11:41.86#ibcon#wrote, iclass 10, count 0 2006.176.08:11:41.86#ibcon#about to read 3, iclass 10, count 0 2006.176.08:11:41.88#ibcon#read 3, iclass 10, count 0 2006.176.08:11:41.88#ibcon#about to read 4, iclass 10, count 0 2006.176.08:11:41.88#ibcon#read 4, iclass 10, count 0 2006.176.08:11:41.88#ibcon#about to read 5, iclass 10, count 0 2006.176.08:11:41.88#ibcon#read 5, iclass 10, count 0 2006.176.08:11:41.88#ibcon#about to read 6, iclass 10, count 0 2006.176.08:11:41.88#ibcon#read 6, iclass 10, count 0 2006.176.08:11:41.88#ibcon#end of sib2, iclass 10, count 0 2006.176.08:11:41.88#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:11:41.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:11:41.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:11:41.88#ibcon#*before write, iclass 10, count 0 2006.176.08:11:41.88#ibcon#enter sib2, iclass 10, count 0 2006.176.08:11:41.88#ibcon#flushed, iclass 10, count 0 2006.176.08:11:41.88#ibcon#about to write, iclass 10, count 0 2006.176.08:11:41.88#ibcon#wrote, iclass 10, count 0 2006.176.08:11:41.88#ibcon#about to read 3, iclass 10, count 0 2006.176.08:11:41.92#ibcon#read 3, iclass 10, count 0 2006.176.08:11:41.92#ibcon#about to read 4, iclass 10, count 0 2006.176.08:11:41.92#ibcon#read 4, iclass 10, count 0 2006.176.08:11:41.92#ibcon#about to read 5, iclass 10, count 0 2006.176.08:11:41.92#ibcon#read 5, iclass 10, count 0 2006.176.08:11:41.92#ibcon#about to read 6, iclass 10, count 0 2006.176.08:11:41.92#ibcon#read 6, iclass 10, count 0 2006.176.08:11:41.92#ibcon#end of sib2, iclass 10, count 0 2006.176.08:11:41.92#ibcon#*after write, iclass 10, count 0 2006.176.08:11:41.92#ibcon#*before return 0, iclass 10, count 0 2006.176.08:11:41.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:41.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:11:41.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:11:41.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:11:41.92$vc4f8/vb=5,4 2006.176.08:11:41.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.08:11:41.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.08:11:41.92#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:41.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:41.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:41.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:41.98#ibcon#enter wrdev, iclass 12, count 2 2006.176.08:11:41.98#ibcon#first serial, iclass 12, count 2 2006.176.08:11:41.98#ibcon#enter sib2, iclass 12, count 2 2006.176.08:11:41.98#ibcon#flushed, iclass 12, count 2 2006.176.08:11:41.98#ibcon#about to write, iclass 12, count 2 2006.176.08:11:41.98#ibcon#wrote, iclass 12, count 2 2006.176.08:11:41.98#ibcon#about to read 3, iclass 12, count 2 2006.176.08:11:42.00#ibcon#read 3, iclass 12, count 2 2006.176.08:11:42.00#ibcon#about to read 4, iclass 12, count 2 2006.176.08:11:42.00#ibcon#read 4, iclass 12, count 2 2006.176.08:11:42.00#ibcon#about to read 5, iclass 12, count 2 2006.176.08:11:42.00#ibcon#read 5, iclass 12, count 2 2006.176.08:11:42.00#ibcon#about to read 6, iclass 12, count 2 2006.176.08:11:42.00#ibcon#read 6, iclass 12, count 2 2006.176.08:11:42.00#ibcon#end of sib2, iclass 12, count 2 2006.176.08:11:42.00#ibcon#*mode == 0, iclass 12, count 2 2006.176.08:11:42.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.08:11:42.00#ibcon#[27=AT05-04\r\n] 2006.176.08:11:42.00#ibcon#*before write, iclass 12, count 2 2006.176.08:11:42.00#ibcon#enter sib2, iclass 12, count 2 2006.176.08:11:42.00#ibcon#flushed, iclass 12, count 2 2006.176.08:11:42.00#ibcon#about to write, iclass 12, count 2 2006.176.08:11:42.00#ibcon#wrote, iclass 12, count 2 2006.176.08:11:42.00#ibcon#about to read 3, iclass 12, count 2 2006.176.08:11:42.03#ibcon#read 3, iclass 12, count 2 2006.176.08:11:42.03#ibcon#about to read 4, iclass 12, count 2 2006.176.08:11:42.03#ibcon#read 4, iclass 12, count 2 2006.176.08:11:42.03#ibcon#about to read 5, iclass 12, count 2 2006.176.08:11:42.03#ibcon#read 5, iclass 12, count 2 2006.176.08:11:42.03#ibcon#about to read 6, iclass 12, count 2 2006.176.08:11:42.03#ibcon#read 6, iclass 12, count 2 2006.176.08:11:42.03#ibcon#end of sib2, iclass 12, count 2 2006.176.08:11:42.03#ibcon#*after write, iclass 12, count 2 2006.176.08:11:42.03#ibcon#*before return 0, iclass 12, count 2 2006.176.08:11:42.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:42.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:11:42.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.08:11:42.03#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:42.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:42.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:42.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:42.15#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:11:42.15#ibcon#first serial, iclass 12, count 0 2006.176.08:11:42.15#ibcon#enter sib2, iclass 12, count 0 2006.176.08:11:42.15#ibcon#flushed, iclass 12, count 0 2006.176.08:11:42.15#ibcon#about to write, iclass 12, count 0 2006.176.08:11:42.15#ibcon#wrote, iclass 12, count 0 2006.176.08:11:42.15#ibcon#about to read 3, iclass 12, count 0 2006.176.08:11:42.17#ibcon#read 3, iclass 12, count 0 2006.176.08:11:42.17#ibcon#about to read 4, iclass 12, count 0 2006.176.08:11:42.17#ibcon#read 4, iclass 12, count 0 2006.176.08:11:42.17#ibcon#about to read 5, iclass 12, count 0 2006.176.08:11:42.17#ibcon#read 5, iclass 12, count 0 2006.176.08:11:42.17#ibcon#about to read 6, iclass 12, count 0 2006.176.08:11:42.17#ibcon#read 6, iclass 12, count 0 2006.176.08:11:42.17#ibcon#end of sib2, iclass 12, count 0 2006.176.08:11:42.17#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:11:42.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:11:42.17#ibcon#[27=USB\r\n] 2006.176.08:11:42.17#ibcon#*before write, iclass 12, count 0 2006.176.08:11:42.17#ibcon#enter sib2, iclass 12, count 0 2006.176.08:11:42.17#ibcon#flushed, iclass 12, count 0 2006.176.08:11:42.17#ibcon#about to write, iclass 12, count 0 2006.176.08:11:42.17#ibcon#wrote, iclass 12, count 0 2006.176.08:11:42.17#ibcon#about to read 3, iclass 12, count 0 2006.176.08:11:42.20#ibcon#read 3, iclass 12, count 0 2006.176.08:11:42.20#ibcon#about to read 4, iclass 12, count 0 2006.176.08:11:42.20#ibcon#read 4, iclass 12, count 0 2006.176.08:11:42.20#ibcon#about to read 5, iclass 12, count 0 2006.176.08:11:42.20#ibcon#read 5, iclass 12, count 0 2006.176.08:11:42.20#ibcon#about to read 6, iclass 12, count 0 2006.176.08:11:42.20#ibcon#read 6, iclass 12, count 0 2006.176.08:11:42.20#ibcon#end of sib2, iclass 12, count 0 2006.176.08:11:42.20#ibcon#*after write, iclass 12, count 0 2006.176.08:11:42.20#ibcon#*before return 0, iclass 12, count 0 2006.176.08:11:42.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:42.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:11:42.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:11:42.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:11:42.20$vc4f8/vblo=6,752.99 2006.176.08:11:42.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.08:11:42.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.08:11:42.20#ibcon#ireg 17 cls_cnt 0 2006.176.08:11:42.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:42.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:42.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:42.20#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:11:42.20#ibcon#first serial, iclass 14, count 0 2006.176.08:11:42.20#ibcon#enter sib2, iclass 14, count 0 2006.176.08:11:42.20#ibcon#flushed, iclass 14, count 0 2006.176.08:11:42.20#ibcon#about to write, iclass 14, count 0 2006.176.08:11:42.20#ibcon#wrote, iclass 14, count 0 2006.176.08:11:42.20#ibcon#about to read 3, iclass 14, count 0 2006.176.08:11:42.22#ibcon#read 3, iclass 14, count 0 2006.176.08:11:42.22#ibcon#about to read 4, iclass 14, count 0 2006.176.08:11:42.22#ibcon#read 4, iclass 14, count 0 2006.176.08:11:42.22#ibcon#about to read 5, iclass 14, count 0 2006.176.08:11:42.22#ibcon#read 5, iclass 14, count 0 2006.176.08:11:42.22#ibcon#about to read 6, iclass 14, count 0 2006.176.08:11:42.22#ibcon#read 6, iclass 14, count 0 2006.176.08:11:42.22#ibcon#end of sib2, iclass 14, count 0 2006.176.08:11:42.22#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:11:42.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:11:42.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:11:42.22#ibcon#*before write, iclass 14, count 0 2006.176.08:11:42.22#ibcon#enter sib2, iclass 14, count 0 2006.176.08:11:42.22#ibcon#flushed, iclass 14, count 0 2006.176.08:11:42.22#ibcon#about to write, iclass 14, count 0 2006.176.08:11:42.22#ibcon#wrote, iclass 14, count 0 2006.176.08:11:42.22#ibcon#about to read 3, iclass 14, count 0 2006.176.08:11:42.26#ibcon#read 3, iclass 14, count 0 2006.176.08:11:42.26#ibcon#about to read 4, iclass 14, count 0 2006.176.08:11:42.26#ibcon#read 4, iclass 14, count 0 2006.176.08:11:42.26#ibcon#about to read 5, iclass 14, count 0 2006.176.08:11:42.26#ibcon#read 5, iclass 14, count 0 2006.176.08:11:42.26#ibcon#about to read 6, iclass 14, count 0 2006.176.08:11:42.26#ibcon#read 6, iclass 14, count 0 2006.176.08:11:42.26#ibcon#end of sib2, iclass 14, count 0 2006.176.08:11:42.26#ibcon#*after write, iclass 14, count 0 2006.176.08:11:42.26#ibcon#*before return 0, iclass 14, count 0 2006.176.08:11:42.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:42.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:11:42.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:11:42.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:11:42.26$vc4f8/vb=6,4 2006.176.08:11:42.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.08:11:42.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.08:11:42.26#ibcon#ireg 11 cls_cnt 2 2006.176.08:11:42.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:42.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:42.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:42.32#ibcon#enter wrdev, iclass 16, count 2 2006.176.08:11:42.32#ibcon#first serial, iclass 16, count 2 2006.176.08:11:42.32#ibcon#enter sib2, iclass 16, count 2 2006.176.08:11:42.32#ibcon#flushed, iclass 16, count 2 2006.176.08:11:42.32#ibcon#about to write, iclass 16, count 2 2006.176.08:11:42.32#ibcon#wrote, iclass 16, count 2 2006.176.08:11:42.32#ibcon#about to read 3, iclass 16, count 2 2006.176.08:11:42.34#ibcon#read 3, iclass 16, count 2 2006.176.08:11:42.34#ibcon#about to read 4, iclass 16, count 2 2006.176.08:11:42.34#ibcon#read 4, iclass 16, count 2 2006.176.08:11:42.34#ibcon#about to read 5, iclass 16, count 2 2006.176.08:11:42.34#ibcon#read 5, iclass 16, count 2 2006.176.08:11:42.34#ibcon#about to read 6, iclass 16, count 2 2006.176.08:11:42.34#ibcon#read 6, iclass 16, count 2 2006.176.08:11:42.34#ibcon#end of sib2, iclass 16, count 2 2006.176.08:11:42.34#ibcon#*mode == 0, iclass 16, count 2 2006.176.08:11:42.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.08:11:42.34#ibcon#[27=AT06-04\r\n] 2006.176.08:11:42.34#ibcon#*before write, iclass 16, count 2 2006.176.08:11:42.34#ibcon#enter sib2, iclass 16, count 2 2006.176.08:11:42.34#ibcon#flushed, iclass 16, count 2 2006.176.08:11:42.34#ibcon#about to write, iclass 16, count 2 2006.176.08:11:42.34#ibcon#wrote, iclass 16, count 2 2006.176.08:11:42.34#ibcon#about to read 3, iclass 16, count 2 2006.176.08:11:42.37#ibcon#read 3, iclass 16, count 2 2006.176.08:11:42.37#ibcon#about to read 4, iclass 16, count 2 2006.176.08:11:42.37#ibcon#read 4, iclass 16, count 2 2006.176.08:11:42.37#ibcon#about to read 5, iclass 16, count 2 2006.176.08:11:42.37#ibcon#read 5, iclass 16, count 2 2006.176.08:11:42.37#ibcon#about to read 6, iclass 16, count 2 2006.176.08:11:42.37#ibcon#read 6, iclass 16, count 2 2006.176.08:11:42.37#ibcon#end of sib2, iclass 16, count 2 2006.176.08:11:42.37#ibcon#*after write, iclass 16, count 2 2006.176.08:11:42.37#ibcon#*before return 0, iclass 16, count 2 2006.176.08:11:42.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:42.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:11:42.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.08:11:42.37#ibcon#ireg 7 cls_cnt 0 2006.176.08:11:42.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:42.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:42.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:42.49#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:11:42.49#ibcon#first serial, iclass 16, count 0 2006.176.08:11:42.49#ibcon#enter sib2, iclass 16, count 0 2006.176.08:11:42.49#ibcon#flushed, iclass 16, count 0 2006.176.08:11:42.49#ibcon#about to write, iclass 16, count 0 2006.176.08:11:42.49#ibcon#wrote, iclass 16, count 0 2006.176.08:11:42.49#ibcon#about to read 3, iclass 16, count 0 2006.176.08:11:42.51#ibcon#read 3, iclass 16, count 0 2006.176.08:11:42.51#ibcon#about to read 4, iclass 16, count 0 2006.176.08:11:42.51#ibcon#read 4, iclass 16, count 0 2006.176.08:11:42.51#ibcon#about to read 5, iclass 16, count 0 2006.176.08:11:42.51#ibcon#read 5, iclass 16, count 0 2006.176.08:11:42.51#ibcon#about to read 6, iclass 16, count 0 2006.176.08:11:42.51#ibcon#read 6, iclass 16, count 0 2006.176.08:11:42.51#ibcon#end of sib2, iclass 16, count 0 2006.176.08:11:42.51#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:11:42.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:11:42.51#ibcon#[27=USB\r\n] 2006.176.08:11:42.51#ibcon#*before write, iclass 16, count 0 2006.176.08:11:42.51#ibcon#enter sib2, iclass 16, count 0 2006.176.08:11:42.51#ibcon#flushed, iclass 16, count 0 2006.176.08:11:42.51#ibcon#about to write, iclass 16, count 0 2006.176.08:11:42.51#ibcon#wrote, iclass 16, count 0 2006.176.08:11:42.51#ibcon#about to read 3, iclass 16, count 0 2006.176.08:11:42.54#ibcon#read 3, iclass 16, count 0 2006.176.08:11:42.54#ibcon#about to read 4, iclass 16, count 0 2006.176.08:11:42.54#ibcon#read 4, iclass 16, count 0 2006.176.08:11:42.54#ibcon#about to read 5, iclass 16, count 0 2006.176.08:11:42.54#ibcon#read 5, iclass 16, count 0 2006.176.08:11:42.54#ibcon#about to read 6, iclass 16, count 0 2006.176.08:11:42.54#ibcon#read 6, iclass 16, count 0 2006.176.08:11:42.54#ibcon#end of sib2, iclass 16, count 0 2006.176.08:11:42.54#ibcon#*after write, iclass 16, count 0 2006.176.08:11:42.54#ibcon#*before return 0, iclass 16, count 0 2006.176.08:11:42.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:42.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:11:42.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:11:42.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:11:42.54$vc4f8/vabw=wide 2006.176.08:11:42.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.08:11:42.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.08:11:42.54#ibcon#ireg 8 cls_cnt 0 2006.176.08:11:42.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:42.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:42.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:42.54#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:11:42.54#ibcon#first serial, iclass 18, count 0 2006.176.08:11:42.54#ibcon#enter sib2, iclass 18, count 0 2006.176.08:11:42.54#ibcon#flushed, iclass 18, count 0 2006.176.08:11:42.54#ibcon#about to write, iclass 18, count 0 2006.176.08:11:42.54#ibcon#wrote, iclass 18, count 0 2006.176.08:11:42.54#ibcon#about to read 3, iclass 18, count 0 2006.176.08:11:42.56#ibcon#read 3, iclass 18, count 0 2006.176.08:11:42.56#ibcon#about to read 4, iclass 18, count 0 2006.176.08:11:42.56#ibcon#read 4, iclass 18, count 0 2006.176.08:11:42.56#ibcon#about to read 5, iclass 18, count 0 2006.176.08:11:42.56#ibcon#read 5, iclass 18, count 0 2006.176.08:11:42.56#ibcon#about to read 6, iclass 18, count 0 2006.176.08:11:42.56#ibcon#read 6, iclass 18, count 0 2006.176.08:11:42.56#ibcon#end of sib2, iclass 18, count 0 2006.176.08:11:42.56#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:11:42.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:11:42.56#ibcon#[25=BW32\r\n] 2006.176.08:11:42.56#ibcon#*before write, iclass 18, count 0 2006.176.08:11:42.56#ibcon#enter sib2, iclass 18, count 0 2006.176.08:11:42.56#ibcon#flushed, iclass 18, count 0 2006.176.08:11:42.56#ibcon#about to write, iclass 18, count 0 2006.176.08:11:42.56#ibcon#wrote, iclass 18, count 0 2006.176.08:11:42.56#ibcon#about to read 3, iclass 18, count 0 2006.176.08:11:42.59#ibcon#read 3, iclass 18, count 0 2006.176.08:11:42.59#ibcon#about to read 4, iclass 18, count 0 2006.176.08:11:42.59#ibcon#read 4, iclass 18, count 0 2006.176.08:11:42.59#ibcon#about to read 5, iclass 18, count 0 2006.176.08:11:42.59#ibcon#read 5, iclass 18, count 0 2006.176.08:11:42.59#ibcon#about to read 6, iclass 18, count 0 2006.176.08:11:42.59#ibcon#read 6, iclass 18, count 0 2006.176.08:11:42.59#ibcon#end of sib2, iclass 18, count 0 2006.176.08:11:42.59#ibcon#*after write, iclass 18, count 0 2006.176.08:11:42.59#ibcon#*before return 0, iclass 18, count 0 2006.176.08:11:42.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:42.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:11:42.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:11:42.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:11:42.59$vc4f8/vbbw=wide 2006.176.08:11:42.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.08:11:42.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.08:11:42.59#ibcon#ireg 8 cls_cnt 0 2006.176.08:11:42.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:11:42.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:11:42.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:11:42.66#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:11:42.66#ibcon#first serial, iclass 20, count 0 2006.176.08:11:42.66#ibcon#enter sib2, iclass 20, count 0 2006.176.08:11:42.66#ibcon#flushed, iclass 20, count 0 2006.176.08:11:42.66#ibcon#about to write, iclass 20, count 0 2006.176.08:11:42.66#ibcon#wrote, iclass 20, count 0 2006.176.08:11:42.66#ibcon#about to read 3, iclass 20, count 0 2006.176.08:11:42.68#ibcon#read 3, iclass 20, count 0 2006.176.08:11:42.68#ibcon#about to read 4, iclass 20, count 0 2006.176.08:11:42.68#ibcon#read 4, iclass 20, count 0 2006.176.08:11:42.68#ibcon#about to read 5, iclass 20, count 0 2006.176.08:11:42.68#ibcon#read 5, iclass 20, count 0 2006.176.08:11:42.68#ibcon#about to read 6, iclass 20, count 0 2006.176.08:11:42.68#ibcon#read 6, iclass 20, count 0 2006.176.08:11:42.68#ibcon#end of sib2, iclass 20, count 0 2006.176.08:11:42.68#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:11:42.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:11:42.68#ibcon#[27=BW32\r\n] 2006.176.08:11:42.68#ibcon#*before write, iclass 20, count 0 2006.176.08:11:42.68#ibcon#enter sib2, iclass 20, count 0 2006.176.08:11:42.68#ibcon#flushed, iclass 20, count 0 2006.176.08:11:42.68#ibcon#about to write, iclass 20, count 0 2006.176.08:11:42.68#ibcon#wrote, iclass 20, count 0 2006.176.08:11:42.68#ibcon#about to read 3, iclass 20, count 0 2006.176.08:11:42.71#ibcon#read 3, iclass 20, count 0 2006.176.08:11:42.71#ibcon#about to read 4, iclass 20, count 0 2006.176.08:11:42.71#ibcon#read 4, iclass 20, count 0 2006.176.08:11:42.71#ibcon#about to read 5, iclass 20, count 0 2006.176.08:11:42.71#ibcon#read 5, iclass 20, count 0 2006.176.08:11:42.71#ibcon#about to read 6, iclass 20, count 0 2006.176.08:11:42.71#ibcon#read 6, iclass 20, count 0 2006.176.08:11:42.71#ibcon#end of sib2, iclass 20, count 0 2006.176.08:11:42.71#ibcon#*after write, iclass 20, count 0 2006.176.08:11:42.71#ibcon#*before return 0, iclass 20, count 0 2006.176.08:11:42.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:11:42.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:11:42.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:11:42.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:11:42.71$4f8m12a/ifd4f 2006.176.08:11:42.71$ifd4f/lo= 2006.176.08:11:42.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:11:42.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:11:42.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:11:42.71$ifd4f/patch= 2006.176.08:11:42.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:11:42.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:11:42.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:11:42.71$4f8m12a/"form=m,16.000,1:2 2006.176.08:11:42.71$4f8m12a/"tpicd 2006.176.08:11:42.71$4f8m12a/echo=off 2006.176.08:11:42.71$4f8m12a/xlog=off 2006.176.08:11:42.71:!2006.176.08:12:10 2006.176.08:11:55.14#trakl#Source acquired 2006.176.08:11:55.14#flagr#flagr/antenna,acquired 2006.176.08:12:10.00:preob 2006.176.08:12:11.14/onsource/TRACKING 2006.176.08:12:11.14:!2006.176.08:12:20 2006.176.08:12:20.00:data_valid=on 2006.176.08:12:20.00:midob 2006.176.08:12:20.14/onsource/TRACKING 2006.176.08:12:20.14/wx/23.84,1008.6,92 2006.176.08:12:20.24/cable/+6.4945E-03 2006.176.08:12:21.33/va/01,08,usb,yes,29,31 2006.176.08:12:21.33/va/02,07,usb,yes,29,31 2006.176.08:12:21.33/va/03,06,usb,yes,31,31 2006.176.08:12:21.33/va/04,07,usb,yes,30,32 2006.176.08:12:21.33/va/05,07,usb,yes,32,33 2006.176.08:12:21.33/va/06,06,usb,yes,31,30 2006.176.08:12:21.33/va/07,06,usb,yes,31,31 2006.176.08:12:21.33/va/08,06,usb,yes,33,33 2006.176.08:12:21.56/valo/01,532.99,yes,locked 2006.176.08:12:21.56/valo/02,572.99,yes,locked 2006.176.08:12:21.56/valo/03,672.99,yes,locked 2006.176.08:12:21.56/valo/04,832.99,yes,locked 2006.176.08:12:21.56/valo/05,652.99,yes,locked 2006.176.08:12:21.56/valo/06,772.99,yes,locked 2006.176.08:12:21.56/valo/07,832.99,yes,locked 2006.176.08:12:21.56/valo/08,852.99,yes,locked 2006.176.08:12:22.65/vb/01,04,usb,yes,29,27 2006.176.08:12:22.65/vb/02,04,usb,yes,30,32 2006.176.08:12:22.65/vb/03,04,usb,yes,27,30 2006.176.08:12:22.65/vb/04,04,usb,yes,28,28 2006.176.08:12:22.65/vb/05,04,usb,yes,26,30 2006.176.08:12:22.65/vb/06,04,usb,yes,27,30 2006.176.08:12:22.65/vb/07,04,usb,yes,29,29 2006.176.08:12:22.65/vb/08,04,usb,yes,27,30 2006.176.08:12:22.88/vblo/01,632.99,yes,locked 2006.176.08:12:22.88/vblo/02,640.99,yes,locked 2006.176.08:12:22.88/vblo/03,656.99,yes,locked 2006.176.08:12:22.88/vblo/04,712.99,yes,locked 2006.176.08:12:22.88/vblo/05,744.99,yes,locked 2006.176.08:12:22.88/vblo/06,752.99,yes,locked 2006.176.08:12:22.88/vblo/07,734.99,yes,locked 2006.176.08:12:22.88/vblo/08,744.99,yes,locked 2006.176.08:12:23.03/vabw/8 2006.176.08:12:23.18/vbbw/8 2006.176.08:12:23.27/xfe/off,on,15.2 2006.176.08:12:23.65/ifatt/23,28,28,28 2006.176.08:12:24.07/fmout-gps/S +3.71E-07 2006.176.08:12:24.15:!2006.176.08:13:20 2006.176.08:13:20.00:data_valid=off 2006.176.08:13:20.00:postob 2006.176.08:13:20.08/cable/+6.4943E-03 2006.176.08:13:20.08/wx/23.83,1008.6,92 2006.176.08:13:21.07/fmout-gps/S +3.71E-07 2006.176.08:13:21.07:scan_name=176-0814,k06176,60 2006.176.08:13:21.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.176.08:13:21.14#flagr#flagr/antenna,new-source 2006.176.08:13:22.14:checkk5 2006.176.08:13:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:13:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:13:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:13:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:13:24.02/chk_obsdata//k5ts1/T1760812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:13:24.39/chk_obsdata//k5ts2/T1760812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:13:24.75/chk_obsdata//k5ts3/T1760812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:13:25.13/chk_obsdata//k5ts4/T1760812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:13:25.82/k5log//k5ts1_log_newline 2006.176.08:13:26.51/k5log//k5ts2_log_newline 2006.176.08:13:27.20/k5log//k5ts3_log_newline 2006.176.08:13:27.88/k5log//k5ts4_log_newline 2006.176.08:13:27.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:13:27.91:4f8m12a=2 2006.176.08:13:27.91$4f8m12a/echo=on 2006.176.08:13:27.91$4f8m12a/pcalon 2006.176.08:13:27.91$pcalon/"no phase cal control is implemented here 2006.176.08:13:27.91$4f8m12a/"tpicd=stop 2006.176.08:13:27.91$4f8m12a/vc4f8 2006.176.08:13:27.91$vc4f8/valo=1,532.99 2006.176.08:13:27.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.08:13:27.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.08:13:27.91#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:27.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:27.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:27.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:27.91#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:13:27.91#ibcon#first serial, iclass 31, count 0 2006.176.08:13:27.91#ibcon#enter sib2, iclass 31, count 0 2006.176.08:13:27.91#ibcon#flushed, iclass 31, count 0 2006.176.08:13:27.91#ibcon#about to write, iclass 31, count 0 2006.176.08:13:27.91#ibcon#wrote, iclass 31, count 0 2006.176.08:13:27.91#ibcon#about to read 3, iclass 31, count 0 2006.176.08:13:27.95#ibcon#read 3, iclass 31, count 0 2006.176.08:13:27.95#ibcon#about to read 4, iclass 31, count 0 2006.176.08:13:27.95#ibcon#read 4, iclass 31, count 0 2006.176.08:13:27.95#ibcon#about to read 5, iclass 31, count 0 2006.176.08:13:27.95#ibcon#read 5, iclass 31, count 0 2006.176.08:13:27.95#ibcon#about to read 6, iclass 31, count 0 2006.176.08:13:27.95#ibcon#read 6, iclass 31, count 0 2006.176.08:13:27.95#ibcon#end of sib2, iclass 31, count 0 2006.176.08:13:27.95#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:13:27.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:13:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:13:27.95#ibcon#*before write, iclass 31, count 0 2006.176.08:13:27.95#ibcon#enter sib2, iclass 31, count 0 2006.176.08:13:27.95#ibcon#flushed, iclass 31, count 0 2006.176.08:13:27.95#ibcon#about to write, iclass 31, count 0 2006.176.08:13:27.95#ibcon#wrote, iclass 31, count 0 2006.176.08:13:27.95#ibcon#about to read 3, iclass 31, count 0 2006.176.08:13:28.00#ibcon#read 3, iclass 31, count 0 2006.176.08:13:28.00#ibcon#about to read 4, iclass 31, count 0 2006.176.08:13:28.00#ibcon#read 4, iclass 31, count 0 2006.176.08:13:28.00#ibcon#about to read 5, iclass 31, count 0 2006.176.08:13:28.00#ibcon#read 5, iclass 31, count 0 2006.176.08:13:28.00#ibcon#about to read 6, iclass 31, count 0 2006.176.08:13:28.00#ibcon#read 6, iclass 31, count 0 2006.176.08:13:28.00#ibcon#end of sib2, iclass 31, count 0 2006.176.08:13:28.00#ibcon#*after write, iclass 31, count 0 2006.176.08:13:28.00#ibcon#*before return 0, iclass 31, count 0 2006.176.08:13:28.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:28.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:28.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:13:28.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:13:28.00$vc4f8/va=1,8 2006.176.08:13:28.00#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.176.08:13:28.00#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.176.08:13:28.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:28.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:28.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:28.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:28.00#ibcon#enter wrdev, iclass 33, count 2 2006.176.08:13:28.00#ibcon#first serial, iclass 33, count 2 2006.176.08:13:28.00#ibcon#enter sib2, iclass 33, count 2 2006.176.08:13:28.00#ibcon#flushed, iclass 33, count 2 2006.176.08:13:28.00#ibcon#about to write, iclass 33, count 2 2006.176.08:13:28.00#ibcon#wrote, iclass 33, count 2 2006.176.08:13:28.00#ibcon#about to read 3, iclass 33, count 2 2006.176.08:13:28.02#ibcon#read 3, iclass 33, count 2 2006.176.08:13:28.02#ibcon#about to read 4, iclass 33, count 2 2006.176.08:13:28.02#ibcon#read 4, iclass 33, count 2 2006.176.08:13:28.02#ibcon#about to read 5, iclass 33, count 2 2006.176.08:13:28.02#ibcon#read 5, iclass 33, count 2 2006.176.08:13:28.02#ibcon#about to read 6, iclass 33, count 2 2006.176.08:13:28.02#ibcon#read 6, iclass 33, count 2 2006.176.08:13:28.02#ibcon#end of sib2, iclass 33, count 2 2006.176.08:13:28.02#ibcon#*mode == 0, iclass 33, count 2 2006.176.08:13:28.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.176.08:13:28.02#ibcon#[25=AT01-08\r\n] 2006.176.08:13:28.02#ibcon#*before write, iclass 33, count 2 2006.176.08:13:28.02#ibcon#enter sib2, iclass 33, count 2 2006.176.08:13:28.02#ibcon#flushed, iclass 33, count 2 2006.176.08:13:28.02#ibcon#about to write, iclass 33, count 2 2006.176.08:13:28.02#ibcon#wrote, iclass 33, count 2 2006.176.08:13:28.02#ibcon#about to read 3, iclass 33, count 2 2006.176.08:13:28.05#ibcon#read 3, iclass 33, count 2 2006.176.08:13:28.05#ibcon#about to read 4, iclass 33, count 2 2006.176.08:13:28.05#ibcon#read 4, iclass 33, count 2 2006.176.08:13:28.05#ibcon#about to read 5, iclass 33, count 2 2006.176.08:13:28.05#ibcon#read 5, iclass 33, count 2 2006.176.08:13:28.05#ibcon#about to read 6, iclass 33, count 2 2006.176.08:13:28.05#ibcon#read 6, iclass 33, count 2 2006.176.08:13:28.05#ibcon#end of sib2, iclass 33, count 2 2006.176.08:13:28.05#ibcon#*after write, iclass 33, count 2 2006.176.08:13:28.05#ibcon#*before return 0, iclass 33, count 2 2006.176.08:13:28.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:28.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:28.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.176.08:13:28.05#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:28.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:28.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:28.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:28.17#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:13:28.17#ibcon#first serial, iclass 33, count 0 2006.176.08:13:28.17#ibcon#enter sib2, iclass 33, count 0 2006.176.08:13:28.17#ibcon#flushed, iclass 33, count 0 2006.176.08:13:28.17#ibcon#about to write, iclass 33, count 0 2006.176.08:13:28.17#ibcon#wrote, iclass 33, count 0 2006.176.08:13:28.17#ibcon#about to read 3, iclass 33, count 0 2006.176.08:13:28.19#ibcon#read 3, iclass 33, count 0 2006.176.08:13:28.19#ibcon#about to read 4, iclass 33, count 0 2006.176.08:13:28.19#ibcon#read 4, iclass 33, count 0 2006.176.08:13:28.19#ibcon#about to read 5, iclass 33, count 0 2006.176.08:13:28.19#ibcon#read 5, iclass 33, count 0 2006.176.08:13:28.19#ibcon#about to read 6, iclass 33, count 0 2006.176.08:13:28.19#ibcon#read 6, iclass 33, count 0 2006.176.08:13:28.19#ibcon#end of sib2, iclass 33, count 0 2006.176.08:13:28.19#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:13:28.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:13:28.19#ibcon#[25=USB\r\n] 2006.176.08:13:28.19#ibcon#*before write, iclass 33, count 0 2006.176.08:13:28.19#ibcon#enter sib2, iclass 33, count 0 2006.176.08:13:28.19#ibcon#flushed, iclass 33, count 0 2006.176.08:13:28.19#ibcon#about to write, iclass 33, count 0 2006.176.08:13:28.19#ibcon#wrote, iclass 33, count 0 2006.176.08:13:28.19#ibcon#about to read 3, iclass 33, count 0 2006.176.08:13:28.23#ibcon#read 3, iclass 33, count 0 2006.176.08:13:28.23#ibcon#about to read 4, iclass 33, count 0 2006.176.08:13:28.23#ibcon#read 4, iclass 33, count 0 2006.176.08:13:28.23#ibcon#about to read 5, iclass 33, count 0 2006.176.08:13:28.23#ibcon#read 5, iclass 33, count 0 2006.176.08:13:28.23#ibcon#about to read 6, iclass 33, count 0 2006.176.08:13:28.23#ibcon#read 6, iclass 33, count 0 2006.176.08:13:28.23#ibcon#end of sib2, iclass 33, count 0 2006.176.08:13:28.23#ibcon#*after write, iclass 33, count 0 2006.176.08:13:28.23#ibcon#*before return 0, iclass 33, count 0 2006.176.08:13:28.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:28.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:28.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:13:28.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:13:28.23$vc4f8/valo=2,572.99 2006.176.08:13:28.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.08:13:28.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.08:13:28.23#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:28.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:28.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:28.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:28.23#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:13:28.23#ibcon#first serial, iclass 35, count 0 2006.176.08:13:28.23#ibcon#enter sib2, iclass 35, count 0 2006.176.08:13:28.23#ibcon#flushed, iclass 35, count 0 2006.176.08:13:28.23#ibcon#about to write, iclass 35, count 0 2006.176.08:13:28.23#ibcon#wrote, iclass 35, count 0 2006.176.08:13:28.23#ibcon#about to read 3, iclass 35, count 0 2006.176.08:13:28.24#ibcon#read 3, iclass 35, count 0 2006.176.08:13:28.24#ibcon#about to read 4, iclass 35, count 0 2006.176.08:13:28.24#ibcon#read 4, iclass 35, count 0 2006.176.08:13:28.24#ibcon#about to read 5, iclass 35, count 0 2006.176.08:13:28.24#ibcon#read 5, iclass 35, count 0 2006.176.08:13:28.24#ibcon#about to read 6, iclass 35, count 0 2006.176.08:13:28.24#ibcon#read 6, iclass 35, count 0 2006.176.08:13:28.24#ibcon#end of sib2, iclass 35, count 0 2006.176.08:13:28.24#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:13:28.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:13:28.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:13:28.24#ibcon#*before write, iclass 35, count 0 2006.176.08:13:28.24#ibcon#enter sib2, iclass 35, count 0 2006.176.08:13:28.24#ibcon#flushed, iclass 35, count 0 2006.176.08:13:28.24#ibcon#about to write, iclass 35, count 0 2006.176.08:13:28.24#ibcon#wrote, iclass 35, count 0 2006.176.08:13:28.24#ibcon#about to read 3, iclass 35, count 0 2006.176.08:13:28.28#ibcon#read 3, iclass 35, count 0 2006.176.08:13:28.28#ibcon#about to read 4, iclass 35, count 0 2006.176.08:13:28.28#ibcon#read 4, iclass 35, count 0 2006.176.08:13:28.28#ibcon#about to read 5, iclass 35, count 0 2006.176.08:13:28.28#ibcon#read 5, iclass 35, count 0 2006.176.08:13:28.28#ibcon#about to read 6, iclass 35, count 0 2006.176.08:13:28.28#ibcon#read 6, iclass 35, count 0 2006.176.08:13:28.28#ibcon#end of sib2, iclass 35, count 0 2006.176.08:13:28.28#ibcon#*after write, iclass 35, count 0 2006.176.08:13:28.28#ibcon#*before return 0, iclass 35, count 0 2006.176.08:13:28.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:28.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:28.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:13:28.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:13:28.28$vc4f8/va=2,7 2006.176.08:13:28.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.176.08:13:28.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.176.08:13:28.28#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:28.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:28.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:28.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:28.35#ibcon#enter wrdev, iclass 37, count 2 2006.176.08:13:28.35#ibcon#first serial, iclass 37, count 2 2006.176.08:13:28.35#ibcon#enter sib2, iclass 37, count 2 2006.176.08:13:28.35#ibcon#flushed, iclass 37, count 2 2006.176.08:13:28.35#ibcon#about to write, iclass 37, count 2 2006.176.08:13:28.35#ibcon#wrote, iclass 37, count 2 2006.176.08:13:28.35#ibcon#about to read 3, iclass 37, count 2 2006.176.08:13:28.37#ibcon#read 3, iclass 37, count 2 2006.176.08:13:28.37#ibcon#about to read 4, iclass 37, count 2 2006.176.08:13:28.37#ibcon#read 4, iclass 37, count 2 2006.176.08:13:28.37#ibcon#about to read 5, iclass 37, count 2 2006.176.08:13:28.37#ibcon#read 5, iclass 37, count 2 2006.176.08:13:28.37#ibcon#about to read 6, iclass 37, count 2 2006.176.08:13:28.37#ibcon#read 6, iclass 37, count 2 2006.176.08:13:28.37#ibcon#end of sib2, iclass 37, count 2 2006.176.08:13:28.37#ibcon#*mode == 0, iclass 37, count 2 2006.176.08:13:28.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.176.08:13:28.37#ibcon#[25=AT02-07\r\n] 2006.176.08:13:28.37#ibcon#*before write, iclass 37, count 2 2006.176.08:13:28.37#ibcon#enter sib2, iclass 37, count 2 2006.176.08:13:28.37#ibcon#flushed, iclass 37, count 2 2006.176.08:13:28.37#ibcon#about to write, iclass 37, count 2 2006.176.08:13:28.37#ibcon#wrote, iclass 37, count 2 2006.176.08:13:28.37#ibcon#about to read 3, iclass 37, count 2 2006.176.08:13:28.40#ibcon#read 3, iclass 37, count 2 2006.176.08:13:28.40#ibcon#about to read 4, iclass 37, count 2 2006.176.08:13:28.40#ibcon#read 4, iclass 37, count 2 2006.176.08:13:28.40#ibcon#about to read 5, iclass 37, count 2 2006.176.08:13:28.40#ibcon#read 5, iclass 37, count 2 2006.176.08:13:28.40#ibcon#about to read 6, iclass 37, count 2 2006.176.08:13:28.40#ibcon#read 6, iclass 37, count 2 2006.176.08:13:28.40#ibcon#end of sib2, iclass 37, count 2 2006.176.08:13:28.40#ibcon#*after write, iclass 37, count 2 2006.176.08:13:28.40#ibcon#*before return 0, iclass 37, count 2 2006.176.08:13:28.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:28.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:28.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.176.08:13:28.40#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:28.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:28.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:28.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:28.52#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:13:28.52#ibcon#first serial, iclass 37, count 0 2006.176.08:13:28.52#ibcon#enter sib2, iclass 37, count 0 2006.176.08:13:28.52#ibcon#flushed, iclass 37, count 0 2006.176.08:13:28.52#ibcon#about to write, iclass 37, count 0 2006.176.08:13:28.52#ibcon#wrote, iclass 37, count 0 2006.176.08:13:28.52#ibcon#about to read 3, iclass 37, count 0 2006.176.08:13:28.54#ibcon#read 3, iclass 37, count 0 2006.176.08:13:28.54#ibcon#about to read 4, iclass 37, count 0 2006.176.08:13:28.54#ibcon#read 4, iclass 37, count 0 2006.176.08:13:28.54#ibcon#about to read 5, iclass 37, count 0 2006.176.08:13:28.54#ibcon#read 5, iclass 37, count 0 2006.176.08:13:28.54#ibcon#about to read 6, iclass 37, count 0 2006.176.08:13:28.54#ibcon#read 6, iclass 37, count 0 2006.176.08:13:28.54#ibcon#end of sib2, iclass 37, count 0 2006.176.08:13:28.54#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:13:28.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:13:28.54#ibcon#[25=USB\r\n] 2006.176.08:13:28.54#ibcon#*before write, iclass 37, count 0 2006.176.08:13:28.54#ibcon#enter sib2, iclass 37, count 0 2006.176.08:13:28.54#ibcon#flushed, iclass 37, count 0 2006.176.08:13:28.54#ibcon#about to write, iclass 37, count 0 2006.176.08:13:28.54#ibcon#wrote, iclass 37, count 0 2006.176.08:13:28.54#ibcon#about to read 3, iclass 37, count 0 2006.176.08:13:28.57#ibcon#read 3, iclass 37, count 0 2006.176.08:13:28.57#ibcon#about to read 4, iclass 37, count 0 2006.176.08:13:28.57#ibcon#read 4, iclass 37, count 0 2006.176.08:13:28.57#ibcon#about to read 5, iclass 37, count 0 2006.176.08:13:28.57#ibcon#read 5, iclass 37, count 0 2006.176.08:13:28.57#ibcon#about to read 6, iclass 37, count 0 2006.176.08:13:28.57#ibcon#read 6, iclass 37, count 0 2006.176.08:13:28.57#ibcon#end of sib2, iclass 37, count 0 2006.176.08:13:28.57#ibcon#*after write, iclass 37, count 0 2006.176.08:13:28.57#ibcon#*before return 0, iclass 37, count 0 2006.176.08:13:28.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:28.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:28.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:13:28.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:13:28.57$vc4f8/valo=3,672.99 2006.176.08:13:28.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.08:13:28.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.08:13:28.57#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:28.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:28.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:28.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:28.57#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:13:28.57#ibcon#first serial, iclass 39, count 0 2006.176.08:13:28.57#ibcon#enter sib2, iclass 39, count 0 2006.176.08:13:28.57#ibcon#flushed, iclass 39, count 0 2006.176.08:13:28.57#ibcon#about to write, iclass 39, count 0 2006.176.08:13:28.57#ibcon#wrote, iclass 39, count 0 2006.176.08:13:28.57#ibcon#about to read 3, iclass 39, count 0 2006.176.08:13:28.59#ibcon#read 3, iclass 39, count 0 2006.176.08:13:28.59#ibcon#about to read 4, iclass 39, count 0 2006.176.08:13:28.59#ibcon#read 4, iclass 39, count 0 2006.176.08:13:28.59#ibcon#about to read 5, iclass 39, count 0 2006.176.08:13:28.59#ibcon#read 5, iclass 39, count 0 2006.176.08:13:28.59#ibcon#about to read 6, iclass 39, count 0 2006.176.08:13:28.59#ibcon#read 6, iclass 39, count 0 2006.176.08:13:28.59#ibcon#end of sib2, iclass 39, count 0 2006.176.08:13:28.59#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:13:28.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:13:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:13:28.59#ibcon#*before write, iclass 39, count 0 2006.176.08:13:28.59#ibcon#enter sib2, iclass 39, count 0 2006.176.08:13:28.59#ibcon#flushed, iclass 39, count 0 2006.176.08:13:28.59#ibcon#about to write, iclass 39, count 0 2006.176.08:13:28.59#ibcon#wrote, iclass 39, count 0 2006.176.08:13:28.59#ibcon#about to read 3, iclass 39, count 0 2006.176.08:13:28.63#ibcon#read 3, iclass 39, count 0 2006.176.08:13:28.63#ibcon#about to read 4, iclass 39, count 0 2006.176.08:13:28.63#ibcon#read 4, iclass 39, count 0 2006.176.08:13:28.63#ibcon#about to read 5, iclass 39, count 0 2006.176.08:13:28.63#ibcon#read 5, iclass 39, count 0 2006.176.08:13:28.63#ibcon#about to read 6, iclass 39, count 0 2006.176.08:13:28.63#ibcon#read 6, iclass 39, count 0 2006.176.08:13:28.63#ibcon#end of sib2, iclass 39, count 0 2006.176.08:13:28.63#ibcon#*after write, iclass 39, count 0 2006.176.08:13:28.63#ibcon#*before return 0, iclass 39, count 0 2006.176.08:13:28.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:28.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:28.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:13:28.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:13:28.63$vc4f8/va=3,6 2006.176.08:13:28.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.08:13:28.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.08:13:28.63#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:28.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:28.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:28.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:28.69#ibcon#enter wrdev, iclass 3, count 2 2006.176.08:13:28.69#ibcon#first serial, iclass 3, count 2 2006.176.08:13:28.69#ibcon#enter sib2, iclass 3, count 2 2006.176.08:13:28.69#ibcon#flushed, iclass 3, count 2 2006.176.08:13:28.69#ibcon#about to write, iclass 3, count 2 2006.176.08:13:28.69#ibcon#wrote, iclass 3, count 2 2006.176.08:13:28.69#ibcon#about to read 3, iclass 3, count 2 2006.176.08:13:28.71#ibcon#read 3, iclass 3, count 2 2006.176.08:13:28.71#ibcon#about to read 4, iclass 3, count 2 2006.176.08:13:28.71#ibcon#read 4, iclass 3, count 2 2006.176.08:13:28.71#ibcon#about to read 5, iclass 3, count 2 2006.176.08:13:28.71#ibcon#read 5, iclass 3, count 2 2006.176.08:13:28.71#ibcon#about to read 6, iclass 3, count 2 2006.176.08:13:28.71#ibcon#read 6, iclass 3, count 2 2006.176.08:13:28.71#ibcon#end of sib2, iclass 3, count 2 2006.176.08:13:28.71#ibcon#*mode == 0, iclass 3, count 2 2006.176.08:13:28.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.08:13:28.71#ibcon#[25=AT03-06\r\n] 2006.176.08:13:28.71#ibcon#*before write, iclass 3, count 2 2006.176.08:13:28.71#ibcon#enter sib2, iclass 3, count 2 2006.176.08:13:28.71#ibcon#flushed, iclass 3, count 2 2006.176.08:13:28.71#ibcon#about to write, iclass 3, count 2 2006.176.08:13:28.71#ibcon#wrote, iclass 3, count 2 2006.176.08:13:28.71#ibcon#about to read 3, iclass 3, count 2 2006.176.08:13:28.74#ibcon#read 3, iclass 3, count 2 2006.176.08:13:28.74#ibcon#about to read 4, iclass 3, count 2 2006.176.08:13:28.74#ibcon#read 4, iclass 3, count 2 2006.176.08:13:28.74#ibcon#about to read 5, iclass 3, count 2 2006.176.08:13:28.74#ibcon#read 5, iclass 3, count 2 2006.176.08:13:28.74#ibcon#about to read 6, iclass 3, count 2 2006.176.08:13:28.74#ibcon#read 6, iclass 3, count 2 2006.176.08:13:28.74#ibcon#end of sib2, iclass 3, count 2 2006.176.08:13:28.74#ibcon#*after write, iclass 3, count 2 2006.176.08:13:28.74#ibcon#*before return 0, iclass 3, count 2 2006.176.08:13:28.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:28.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:28.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.08:13:28.74#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:28.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:28.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:28.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:28.86#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:13:28.86#ibcon#first serial, iclass 3, count 0 2006.176.08:13:28.86#ibcon#enter sib2, iclass 3, count 0 2006.176.08:13:28.86#ibcon#flushed, iclass 3, count 0 2006.176.08:13:28.86#ibcon#about to write, iclass 3, count 0 2006.176.08:13:28.86#ibcon#wrote, iclass 3, count 0 2006.176.08:13:28.86#ibcon#about to read 3, iclass 3, count 0 2006.176.08:13:28.88#ibcon#read 3, iclass 3, count 0 2006.176.08:13:28.88#ibcon#about to read 4, iclass 3, count 0 2006.176.08:13:28.88#ibcon#read 4, iclass 3, count 0 2006.176.08:13:28.88#ibcon#about to read 5, iclass 3, count 0 2006.176.08:13:28.88#ibcon#read 5, iclass 3, count 0 2006.176.08:13:28.88#ibcon#about to read 6, iclass 3, count 0 2006.176.08:13:28.88#ibcon#read 6, iclass 3, count 0 2006.176.08:13:28.88#ibcon#end of sib2, iclass 3, count 0 2006.176.08:13:28.88#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:13:28.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:13:28.88#ibcon#[25=USB\r\n] 2006.176.08:13:28.88#ibcon#*before write, iclass 3, count 0 2006.176.08:13:28.88#ibcon#enter sib2, iclass 3, count 0 2006.176.08:13:28.88#ibcon#flushed, iclass 3, count 0 2006.176.08:13:28.88#ibcon#about to write, iclass 3, count 0 2006.176.08:13:28.88#ibcon#wrote, iclass 3, count 0 2006.176.08:13:28.88#ibcon#about to read 3, iclass 3, count 0 2006.176.08:13:28.91#ibcon#read 3, iclass 3, count 0 2006.176.08:13:28.91#ibcon#about to read 4, iclass 3, count 0 2006.176.08:13:28.91#ibcon#read 4, iclass 3, count 0 2006.176.08:13:28.91#ibcon#about to read 5, iclass 3, count 0 2006.176.08:13:28.91#ibcon#read 5, iclass 3, count 0 2006.176.08:13:28.91#ibcon#about to read 6, iclass 3, count 0 2006.176.08:13:28.91#ibcon#read 6, iclass 3, count 0 2006.176.08:13:28.91#ibcon#end of sib2, iclass 3, count 0 2006.176.08:13:28.91#ibcon#*after write, iclass 3, count 0 2006.176.08:13:28.91#ibcon#*before return 0, iclass 3, count 0 2006.176.08:13:28.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:28.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:28.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:13:28.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:13:28.91$vc4f8/valo=4,832.99 2006.176.08:13:28.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.08:13:28.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.08:13:28.91#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:28.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:28.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:28.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:28.91#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:13:28.91#ibcon#first serial, iclass 5, count 0 2006.176.08:13:28.91#ibcon#enter sib2, iclass 5, count 0 2006.176.08:13:28.91#ibcon#flushed, iclass 5, count 0 2006.176.08:13:28.91#ibcon#about to write, iclass 5, count 0 2006.176.08:13:28.91#ibcon#wrote, iclass 5, count 0 2006.176.08:13:28.91#ibcon#about to read 3, iclass 5, count 0 2006.176.08:13:28.93#ibcon#read 3, iclass 5, count 0 2006.176.08:13:28.93#ibcon#about to read 4, iclass 5, count 0 2006.176.08:13:28.93#ibcon#read 4, iclass 5, count 0 2006.176.08:13:28.93#ibcon#about to read 5, iclass 5, count 0 2006.176.08:13:28.93#ibcon#read 5, iclass 5, count 0 2006.176.08:13:28.93#ibcon#about to read 6, iclass 5, count 0 2006.176.08:13:28.93#ibcon#read 6, iclass 5, count 0 2006.176.08:13:28.93#ibcon#end of sib2, iclass 5, count 0 2006.176.08:13:28.93#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:13:28.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:13:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:13:28.93#ibcon#*before write, iclass 5, count 0 2006.176.08:13:28.93#ibcon#enter sib2, iclass 5, count 0 2006.176.08:13:28.93#ibcon#flushed, iclass 5, count 0 2006.176.08:13:28.93#ibcon#about to write, iclass 5, count 0 2006.176.08:13:28.93#ibcon#wrote, iclass 5, count 0 2006.176.08:13:28.93#ibcon#about to read 3, iclass 5, count 0 2006.176.08:13:28.97#ibcon#read 3, iclass 5, count 0 2006.176.08:13:28.97#ibcon#about to read 4, iclass 5, count 0 2006.176.08:13:28.97#ibcon#read 4, iclass 5, count 0 2006.176.08:13:28.97#ibcon#about to read 5, iclass 5, count 0 2006.176.08:13:28.97#ibcon#read 5, iclass 5, count 0 2006.176.08:13:28.97#ibcon#about to read 6, iclass 5, count 0 2006.176.08:13:28.97#ibcon#read 6, iclass 5, count 0 2006.176.08:13:28.97#ibcon#end of sib2, iclass 5, count 0 2006.176.08:13:28.97#ibcon#*after write, iclass 5, count 0 2006.176.08:13:28.97#ibcon#*before return 0, iclass 5, count 0 2006.176.08:13:28.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:28.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:28.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:13:28.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:13:28.97$vc4f8/va=4,7 2006.176.08:13:28.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.08:13:28.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.08:13:28.97#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:28.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:29.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:29.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:29.03#ibcon#enter wrdev, iclass 7, count 2 2006.176.08:13:29.03#ibcon#first serial, iclass 7, count 2 2006.176.08:13:29.03#ibcon#enter sib2, iclass 7, count 2 2006.176.08:13:29.03#ibcon#flushed, iclass 7, count 2 2006.176.08:13:29.03#ibcon#about to write, iclass 7, count 2 2006.176.08:13:29.03#ibcon#wrote, iclass 7, count 2 2006.176.08:13:29.03#ibcon#about to read 3, iclass 7, count 2 2006.176.08:13:29.05#ibcon#read 3, iclass 7, count 2 2006.176.08:13:29.05#ibcon#about to read 4, iclass 7, count 2 2006.176.08:13:29.05#ibcon#read 4, iclass 7, count 2 2006.176.08:13:29.05#ibcon#about to read 5, iclass 7, count 2 2006.176.08:13:29.05#ibcon#read 5, iclass 7, count 2 2006.176.08:13:29.05#ibcon#about to read 6, iclass 7, count 2 2006.176.08:13:29.05#ibcon#read 6, iclass 7, count 2 2006.176.08:13:29.05#ibcon#end of sib2, iclass 7, count 2 2006.176.08:13:29.05#ibcon#*mode == 0, iclass 7, count 2 2006.176.08:13:29.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.08:13:29.05#ibcon#[25=AT04-07\r\n] 2006.176.08:13:29.05#ibcon#*before write, iclass 7, count 2 2006.176.08:13:29.05#ibcon#enter sib2, iclass 7, count 2 2006.176.08:13:29.05#ibcon#flushed, iclass 7, count 2 2006.176.08:13:29.05#ibcon#about to write, iclass 7, count 2 2006.176.08:13:29.05#ibcon#wrote, iclass 7, count 2 2006.176.08:13:29.05#ibcon#about to read 3, iclass 7, count 2 2006.176.08:13:29.08#ibcon#read 3, iclass 7, count 2 2006.176.08:13:29.08#ibcon#about to read 4, iclass 7, count 2 2006.176.08:13:29.08#ibcon#read 4, iclass 7, count 2 2006.176.08:13:29.08#ibcon#about to read 5, iclass 7, count 2 2006.176.08:13:29.08#ibcon#read 5, iclass 7, count 2 2006.176.08:13:29.08#ibcon#about to read 6, iclass 7, count 2 2006.176.08:13:29.08#ibcon#read 6, iclass 7, count 2 2006.176.08:13:29.08#ibcon#end of sib2, iclass 7, count 2 2006.176.08:13:29.08#ibcon#*after write, iclass 7, count 2 2006.176.08:13:29.08#ibcon#*before return 0, iclass 7, count 2 2006.176.08:13:29.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:29.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:29.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.08:13:29.08#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:29.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:29.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:29.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:29.20#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:13:29.20#ibcon#first serial, iclass 7, count 0 2006.176.08:13:29.20#ibcon#enter sib2, iclass 7, count 0 2006.176.08:13:29.20#ibcon#flushed, iclass 7, count 0 2006.176.08:13:29.20#ibcon#about to write, iclass 7, count 0 2006.176.08:13:29.20#ibcon#wrote, iclass 7, count 0 2006.176.08:13:29.20#ibcon#about to read 3, iclass 7, count 0 2006.176.08:13:29.22#ibcon#read 3, iclass 7, count 0 2006.176.08:13:29.22#ibcon#about to read 4, iclass 7, count 0 2006.176.08:13:29.22#ibcon#read 4, iclass 7, count 0 2006.176.08:13:29.22#ibcon#about to read 5, iclass 7, count 0 2006.176.08:13:29.22#ibcon#read 5, iclass 7, count 0 2006.176.08:13:29.22#ibcon#about to read 6, iclass 7, count 0 2006.176.08:13:29.22#ibcon#read 6, iclass 7, count 0 2006.176.08:13:29.22#ibcon#end of sib2, iclass 7, count 0 2006.176.08:13:29.22#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:13:29.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:13:29.22#ibcon#[25=USB\r\n] 2006.176.08:13:29.22#ibcon#*before write, iclass 7, count 0 2006.176.08:13:29.22#ibcon#enter sib2, iclass 7, count 0 2006.176.08:13:29.22#ibcon#flushed, iclass 7, count 0 2006.176.08:13:29.22#ibcon#about to write, iclass 7, count 0 2006.176.08:13:29.22#ibcon#wrote, iclass 7, count 0 2006.176.08:13:29.22#ibcon#about to read 3, iclass 7, count 0 2006.176.08:13:29.25#ibcon#read 3, iclass 7, count 0 2006.176.08:13:29.25#ibcon#about to read 4, iclass 7, count 0 2006.176.08:13:29.25#ibcon#read 4, iclass 7, count 0 2006.176.08:13:29.25#ibcon#about to read 5, iclass 7, count 0 2006.176.08:13:29.25#ibcon#read 5, iclass 7, count 0 2006.176.08:13:29.25#ibcon#about to read 6, iclass 7, count 0 2006.176.08:13:29.25#ibcon#read 6, iclass 7, count 0 2006.176.08:13:29.25#ibcon#end of sib2, iclass 7, count 0 2006.176.08:13:29.25#ibcon#*after write, iclass 7, count 0 2006.176.08:13:29.25#ibcon#*before return 0, iclass 7, count 0 2006.176.08:13:29.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:29.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:29.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:13:29.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:13:29.25$vc4f8/valo=5,652.99 2006.176.08:13:29.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.08:13:29.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.08:13:29.25#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:29.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:29.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:29.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:29.25#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:13:29.25#ibcon#first serial, iclass 11, count 0 2006.176.08:13:29.25#ibcon#enter sib2, iclass 11, count 0 2006.176.08:13:29.25#ibcon#flushed, iclass 11, count 0 2006.176.08:13:29.25#ibcon#about to write, iclass 11, count 0 2006.176.08:13:29.25#ibcon#wrote, iclass 11, count 0 2006.176.08:13:29.25#ibcon#about to read 3, iclass 11, count 0 2006.176.08:13:29.27#ibcon#read 3, iclass 11, count 0 2006.176.08:13:29.27#ibcon#about to read 4, iclass 11, count 0 2006.176.08:13:29.27#ibcon#read 4, iclass 11, count 0 2006.176.08:13:29.27#ibcon#about to read 5, iclass 11, count 0 2006.176.08:13:29.27#ibcon#read 5, iclass 11, count 0 2006.176.08:13:29.27#ibcon#about to read 6, iclass 11, count 0 2006.176.08:13:29.27#ibcon#read 6, iclass 11, count 0 2006.176.08:13:29.27#ibcon#end of sib2, iclass 11, count 0 2006.176.08:13:29.27#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:13:29.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:13:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:13:29.27#ibcon#*before write, iclass 11, count 0 2006.176.08:13:29.27#ibcon#enter sib2, iclass 11, count 0 2006.176.08:13:29.27#ibcon#flushed, iclass 11, count 0 2006.176.08:13:29.27#ibcon#about to write, iclass 11, count 0 2006.176.08:13:29.27#ibcon#wrote, iclass 11, count 0 2006.176.08:13:29.27#ibcon#about to read 3, iclass 11, count 0 2006.176.08:13:29.31#ibcon#read 3, iclass 11, count 0 2006.176.08:13:29.31#ibcon#about to read 4, iclass 11, count 0 2006.176.08:13:29.31#ibcon#read 4, iclass 11, count 0 2006.176.08:13:29.31#ibcon#about to read 5, iclass 11, count 0 2006.176.08:13:29.31#ibcon#read 5, iclass 11, count 0 2006.176.08:13:29.31#ibcon#about to read 6, iclass 11, count 0 2006.176.08:13:29.31#ibcon#read 6, iclass 11, count 0 2006.176.08:13:29.31#ibcon#end of sib2, iclass 11, count 0 2006.176.08:13:29.31#ibcon#*after write, iclass 11, count 0 2006.176.08:13:29.31#ibcon#*before return 0, iclass 11, count 0 2006.176.08:13:29.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:29.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:29.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:13:29.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:13:29.31$vc4f8/va=5,7 2006.176.08:13:29.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.08:13:29.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.08:13:29.31#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:29.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:29.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:29.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:29.37#ibcon#enter wrdev, iclass 13, count 2 2006.176.08:13:29.37#ibcon#first serial, iclass 13, count 2 2006.176.08:13:29.37#ibcon#enter sib2, iclass 13, count 2 2006.176.08:13:29.37#ibcon#flushed, iclass 13, count 2 2006.176.08:13:29.37#ibcon#about to write, iclass 13, count 2 2006.176.08:13:29.37#ibcon#wrote, iclass 13, count 2 2006.176.08:13:29.37#ibcon#about to read 3, iclass 13, count 2 2006.176.08:13:29.39#ibcon#read 3, iclass 13, count 2 2006.176.08:13:29.39#ibcon#about to read 4, iclass 13, count 2 2006.176.08:13:29.39#ibcon#read 4, iclass 13, count 2 2006.176.08:13:29.39#ibcon#about to read 5, iclass 13, count 2 2006.176.08:13:29.39#ibcon#read 5, iclass 13, count 2 2006.176.08:13:29.39#ibcon#about to read 6, iclass 13, count 2 2006.176.08:13:29.39#ibcon#read 6, iclass 13, count 2 2006.176.08:13:29.39#ibcon#end of sib2, iclass 13, count 2 2006.176.08:13:29.39#ibcon#*mode == 0, iclass 13, count 2 2006.176.08:13:29.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.08:13:29.39#ibcon#[25=AT05-07\r\n] 2006.176.08:13:29.39#ibcon#*before write, iclass 13, count 2 2006.176.08:13:29.39#ibcon#enter sib2, iclass 13, count 2 2006.176.08:13:29.39#ibcon#flushed, iclass 13, count 2 2006.176.08:13:29.39#ibcon#about to write, iclass 13, count 2 2006.176.08:13:29.39#ibcon#wrote, iclass 13, count 2 2006.176.08:13:29.39#ibcon#about to read 3, iclass 13, count 2 2006.176.08:13:29.42#ibcon#read 3, iclass 13, count 2 2006.176.08:13:29.42#ibcon#about to read 4, iclass 13, count 2 2006.176.08:13:29.42#ibcon#read 4, iclass 13, count 2 2006.176.08:13:29.42#ibcon#about to read 5, iclass 13, count 2 2006.176.08:13:29.42#ibcon#read 5, iclass 13, count 2 2006.176.08:13:29.42#ibcon#about to read 6, iclass 13, count 2 2006.176.08:13:29.42#ibcon#read 6, iclass 13, count 2 2006.176.08:13:29.42#ibcon#end of sib2, iclass 13, count 2 2006.176.08:13:29.42#ibcon#*after write, iclass 13, count 2 2006.176.08:13:29.42#ibcon#*before return 0, iclass 13, count 2 2006.176.08:13:29.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:29.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:29.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.08:13:29.42#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:29.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:29.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:29.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:29.54#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:13:29.54#ibcon#first serial, iclass 13, count 0 2006.176.08:13:29.54#ibcon#enter sib2, iclass 13, count 0 2006.176.08:13:29.54#ibcon#flushed, iclass 13, count 0 2006.176.08:13:29.54#ibcon#about to write, iclass 13, count 0 2006.176.08:13:29.54#ibcon#wrote, iclass 13, count 0 2006.176.08:13:29.54#ibcon#about to read 3, iclass 13, count 0 2006.176.08:13:29.56#ibcon#read 3, iclass 13, count 0 2006.176.08:13:29.56#ibcon#about to read 4, iclass 13, count 0 2006.176.08:13:29.56#ibcon#read 4, iclass 13, count 0 2006.176.08:13:29.56#ibcon#about to read 5, iclass 13, count 0 2006.176.08:13:29.56#ibcon#read 5, iclass 13, count 0 2006.176.08:13:29.56#ibcon#about to read 6, iclass 13, count 0 2006.176.08:13:29.56#ibcon#read 6, iclass 13, count 0 2006.176.08:13:29.56#ibcon#end of sib2, iclass 13, count 0 2006.176.08:13:29.56#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:13:29.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:13:29.56#ibcon#[25=USB\r\n] 2006.176.08:13:29.56#ibcon#*before write, iclass 13, count 0 2006.176.08:13:29.56#ibcon#enter sib2, iclass 13, count 0 2006.176.08:13:29.56#ibcon#flushed, iclass 13, count 0 2006.176.08:13:29.56#ibcon#about to write, iclass 13, count 0 2006.176.08:13:29.56#ibcon#wrote, iclass 13, count 0 2006.176.08:13:29.56#ibcon#about to read 3, iclass 13, count 0 2006.176.08:13:29.59#ibcon#read 3, iclass 13, count 0 2006.176.08:13:29.59#ibcon#about to read 4, iclass 13, count 0 2006.176.08:13:29.59#ibcon#read 4, iclass 13, count 0 2006.176.08:13:29.59#ibcon#about to read 5, iclass 13, count 0 2006.176.08:13:29.59#ibcon#read 5, iclass 13, count 0 2006.176.08:13:29.59#ibcon#about to read 6, iclass 13, count 0 2006.176.08:13:29.59#ibcon#read 6, iclass 13, count 0 2006.176.08:13:29.59#ibcon#end of sib2, iclass 13, count 0 2006.176.08:13:29.59#ibcon#*after write, iclass 13, count 0 2006.176.08:13:29.59#ibcon#*before return 0, iclass 13, count 0 2006.176.08:13:29.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:29.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:29.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:13:29.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:13:29.59$vc4f8/valo=6,772.99 2006.176.08:13:29.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.08:13:29.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.08:13:29.59#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:29.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:29.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:29.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:29.59#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:13:29.59#ibcon#first serial, iclass 15, count 0 2006.176.08:13:29.59#ibcon#enter sib2, iclass 15, count 0 2006.176.08:13:29.59#ibcon#flushed, iclass 15, count 0 2006.176.08:13:29.59#ibcon#about to write, iclass 15, count 0 2006.176.08:13:29.59#ibcon#wrote, iclass 15, count 0 2006.176.08:13:29.59#ibcon#about to read 3, iclass 15, count 0 2006.176.08:13:29.61#ibcon#read 3, iclass 15, count 0 2006.176.08:13:29.61#ibcon#about to read 4, iclass 15, count 0 2006.176.08:13:29.61#ibcon#read 4, iclass 15, count 0 2006.176.08:13:29.61#ibcon#about to read 5, iclass 15, count 0 2006.176.08:13:29.61#ibcon#read 5, iclass 15, count 0 2006.176.08:13:29.61#ibcon#about to read 6, iclass 15, count 0 2006.176.08:13:29.61#ibcon#read 6, iclass 15, count 0 2006.176.08:13:29.61#ibcon#end of sib2, iclass 15, count 0 2006.176.08:13:29.61#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:13:29.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:13:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:13:29.61#ibcon#*before write, iclass 15, count 0 2006.176.08:13:29.61#ibcon#enter sib2, iclass 15, count 0 2006.176.08:13:29.61#ibcon#flushed, iclass 15, count 0 2006.176.08:13:29.61#ibcon#about to write, iclass 15, count 0 2006.176.08:13:29.61#ibcon#wrote, iclass 15, count 0 2006.176.08:13:29.61#ibcon#about to read 3, iclass 15, count 0 2006.176.08:13:29.65#ibcon#read 3, iclass 15, count 0 2006.176.08:13:29.65#ibcon#about to read 4, iclass 15, count 0 2006.176.08:13:29.65#ibcon#read 4, iclass 15, count 0 2006.176.08:13:29.65#ibcon#about to read 5, iclass 15, count 0 2006.176.08:13:29.65#ibcon#read 5, iclass 15, count 0 2006.176.08:13:29.65#ibcon#about to read 6, iclass 15, count 0 2006.176.08:13:29.65#ibcon#read 6, iclass 15, count 0 2006.176.08:13:29.65#ibcon#end of sib2, iclass 15, count 0 2006.176.08:13:29.65#ibcon#*after write, iclass 15, count 0 2006.176.08:13:29.65#ibcon#*before return 0, iclass 15, count 0 2006.176.08:13:29.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:29.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:29.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:13:29.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:13:29.65$vc4f8/va=6,6 2006.176.08:13:29.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.176.08:13:29.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.176.08:13:29.65#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:29.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:13:29.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:13:29.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:13:29.71#ibcon#enter wrdev, iclass 17, count 2 2006.176.08:13:29.71#ibcon#first serial, iclass 17, count 2 2006.176.08:13:29.71#ibcon#enter sib2, iclass 17, count 2 2006.176.08:13:29.71#ibcon#flushed, iclass 17, count 2 2006.176.08:13:29.71#ibcon#about to write, iclass 17, count 2 2006.176.08:13:29.71#ibcon#wrote, iclass 17, count 2 2006.176.08:13:29.71#ibcon#about to read 3, iclass 17, count 2 2006.176.08:13:29.73#ibcon#read 3, iclass 17, count 2 2006.176.08:13:29.73#ibcon#about to read 4, iclass 17, count 2 2006.176.08:13:29.73#ibcon#read 4, iclass 17, count 2 2006.176.08:13:29.73#ibcon#about to read 5, iclass 17, count 2 2006.176.08:13:29.73#ibcon#read 5, iclass 17, count 2 2006.176.08:13:29.73#ibcon#about to read 6, iclass 17, count 2 2006.176.08:13:29.73#ibcon#read 6, iclass 17, count 2 2006.176.08:13:29.73#ibcon#end of sib2, iclass 17, count 2 2006.176.08:13:29.73#ibcon#*mode == 0, iclass 17, count 2 2006.176.08:13:29.73#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.176.08:13:29.73#ibcon#[25=AT06-06\r\n] 2006.176.08:13:29.73#ibcon#*before write, iclass 17, count 2 2006.176.08:13:29.73#ibcon#enter sib2, iclass 17, count 2 2006.176.08:13:29.73#ibcon#flushed, iclass 17, count 2 2006.176.08:13:29.73#ibcon#about to write, iclass 17, count 2 2006.176.08:13:29.73#ibcon#wrote, iclass 17, count 2 2006.176.08:13:29.73#ibcon#about to read 3, iclass 17, count 2 2006.176.08:13:29.76#ibcon#read 3, iclass 17, count 2 2006.176.08:13:29.76#ibcon#about to read 4, iclass 17, count 2 2006.176.08:13:29.76#ibcon#read 4, iclass 17, count 2 2006.176.08:13:29.76#ibcon#about to read 5, iclass 17, count 2 2006.176.08:13:29.76#ibcon#read 5, iclass 17, count 2 2006.176.08:13:29.76#ibcon#about to read 6, iclass 17, count 2 2006.176.08:13:29.76#ibcon#read 6, iclass 17, count 2 2006.176.08:13:29.76#ibcon#end of sib2, iclass 17, count 2 2006.176.08:13:29.76#ibcon#*after write, iclass 17, count 2 2006.176.08:13:29.76#ibcon#*before return 0, iclass 17, count 2 2006.176.08:13:29.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:13:29.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:13:29.76#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.176.08:13:29.76#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:29.76#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:13:29.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:13:29.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:13:29.88#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:13:29.88#ibcon#first serial, iclass 17, count 0 2006.176.08:13:29.88#ibcon#enter sib2, iclass 17, count 0 2006.176.08:13:29.88#ibcon#flushed, iclass 17, count 0 2006.176.08:13:29.88#ibcon#about to write, iclass 17, count 0 2006.176.08:13:29.88#ibcon#wrote, iclass 17, count 0 2006.176.08:13:29.88#ibcon#about to read 3, iclass 17, count 0 2006.176.08:13:29.90#ibcon#read 3, iclass 17, count 0 2006.176.08:13:29.90#ibcon#about to read 4, iclass 17, count 0 2006.176.08:13:29.90#ibcon#read 4, iclass 17, count 0 2006.176.08:13:29.90#ibcon#about to read 5, iclass 17, count 0 2006.176.08:13:29.90#ibcon#read 5, iclass 17, count 0 2006.176.08:13:29.90#ibcon#about to read 6, iclass 17, count 0 2006.176.08:13:29.90#ibcon#read 6, iclass 17, count 0 2006.176.08:13:29.90#ibcon#end of sib2, iclass 17, count 0 2006.176.08:13:29.90#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:13:29.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:13:29.90#ibcon#[25=USB\r\n] 2006.176.08:13:29.90#ibcon#*before write, iclass 17, count 0 2006.176.08:13:29.90#ibcon#enter sib2, iclass 17, count 0 2006.176.08:13:29.90#ibcon#flushed, iclass 17, count 0 2006.176.08:13:29.90#ibcon#about to write, iclass 17, count 0 2006.176.08:13:29.90#ibcon#wrote, iclass 17, count 0 2006.176.08:13:29.90#ibcon#about to read 3, iclass 17, count 0 2006.176.08:13:29.93#ibcon#read 3, iclass 17, count 0 2006.176.08:13:29.93#ibcon#about to read 4, iclass 17, count 0 2006.176.08:13:29.93#ibcon#read 4, iclass 17, count 0 2006.176.08:13:29.93#ibcon#about to read 5, iclass 17, count 0 2006.176.08:13:29.93#ibcon#read 5, iclass 17, count 0 2006.176.08:13:29.93#ibcon#about to read 6, iclass 17, count 0 2006.176.08:13:29.93#ibcon#read 6, iclass 17, count 0 2006.176.08:13:29.93#ibcon#end of sib2, iclass 17, count 0 2006.176.08:13:29.93#ibcon#*after write, iclass 17, count 0 2006.176.08:13:29.93#ibcon#*before return 0, iclass 17, count 0 2006.176.08:13:29.93#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:13:29.93#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:13:29.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:13:29.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:13:29.93$vc4f8/valo=7,832.99 2006.176.08:13:29.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.176.08:13:29.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.176.08:13:29.93#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:29.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:13:29.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:13:29.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:13:29.93#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:13:29.93#ibcon#first serial, iclass 19, count 0 2006.176.08:13:29.93#ibcon#enter sib2, iclass 19, count 0 2006.176.08:13:29.93#ibcon#flushed, iclass 19, count 0 2006.176.08:13:29.93#ibcon#about to write, iclass 19, count 0 2006.176.08:13:29.93#ibcon#wrote, iclass 19, count 0 2006.176.08:13:29.93#ibcon#about to read 3, iclass 19, count 0 2006.176.08:13:29.95#ibcon#read 3, iclass 19, count 0 2006.176.08:13:29.95#ibcon#about to read 4, iclass 19, count 0 2006.176.08:13:29.95#ibcon#read 4, iclass 19, count 0 2006.176.08:13:29.95#ibcon#about to read 5, iclass 19, count 0 2006.176.08:13:29.95#ibcon#read 5, iclass 19, count 0 2006.176.08:13:29.95#ibcon#about to read 6, iclass 19, count 0 2006.176.08:13:29.95#ibcon#read 6, iclass 19, count 0 2006.176.08:13:29.95#ibcon#end of sib2, iclass 19, count 0 2006.176.08:13:29.95#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:13:29.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:13:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:13:29.95#ibcon#*before write, iclass 19, count 0 2006.176.08:13:29.95#ibcon#enter sib2, iclass 19, count 0 2006.176.08:13:29.95#ibcon#flushed, iclass 19, count 0 2006.176.08:13:29.95#ibcon#about to write, iclass 19, count 0 2006.176.08:13:29.95#ibcon#wrote, iclass 19, count 0 2006.176.08:13:29.95#ibcon#about to read 3, iclass 19, count 0 2006.176.08:13:29.99#ibcon#read 3, iclass 19, count 0 2006.176.08:13:29.99#ibcon#about to read 4, iclass 19, count 0 2006.176.08:13:29.99#ibcon#read 4, iclass 19, count 0 2006.176.08:13:29.99#ibcon#about to read 5, iclass 19, count 0 2006.176.08:13:29.99#ibcon#read 5, iclass 19, count 0 2006.176.08:13:29.99#ibcon#about to read 6, iclass 19, count 0 2006.176.08:13:29.99#ibcon#read 6, iclass 19, count 0 2006.176.08:13:29.99#ibcon#end of sib2, iclass 19, count 0 2006.176.08:13:29.99#ibcon#*after write, iclass 19, count 0 2006.176.08:13:29.99#ibcon#*before return 0, iclass 19, count 0 2006.176.08:13:29.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:13:29.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:13:29.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:13:29.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:13:29.99$vc4f8/va=7,6 2006.176.08:13:29.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.176.08:13:29.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.176.08:13:29.99#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:29.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:13:30.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:13:30.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:13:30.05#ibcon#enter wrdev, iclass 21, count 2 2006.176.08:13:30.05#ibcon#first serial, iclass 21, count 2 2006.176.08:13:30.05#ibcon#enter sib2, iclass 21, count 2 2006.176.08:13:30.05#ibcon#flushed, iclass 21, count 2 2006.176.08:13:30.05#ibcon#about to write, iclass 21, count 2 2006.176.08:13:30.05#ibcon#wrote, iclass 21, count 2 2006.176.08:13:30.05#ibcon#about to read 3, iclass 21, count 2 2006.176.08:13:30.07#ibcon#read 3, iclass 21, count 2 2006.176.08:13:30.07#ibcon#about to read 4, iclass 21, count 2 2006.176.08:13:30.07#ibcon#read 4, iclass 21, count 2 2006.176.08:13:30.07#ibcon#about to read 5, iclass 21, count 2 2006.176.08:13:30.07#ibcon#read 5, iclass 21, count 2 2006.176.08:13:30.07#ibcon#about to read 6, iclass 21, count 2 2006.176.08:13:30.07#ibcon#read 6, iclass 21, count 2 2006.176.08:13:30.07#ibcon#end of sib2, iclass 21, count 2 2006.176.08:13:30.07#ibcon#*mode == 0, iclass 21, count 2 2006.176.08:13:30.07#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.176.08:13:30.07#ibcon#[25=AT07-06\r\n] 2006.176.08:13:30.07#ibcon#*before write, iclass 21, count 2 2006.176.08:13:30.07#ibcon#enter sib2, iclass 21, count 2 2006.176.08:13:30.07#ibcon#flushed, iclass 21, count 2 2006.176.08:13:30.07#ibcon#about to write, iclass 21, count 2 2006.176.08:13:30.07#ibcon#wrote, iclass 21, count 2 2006.176.08:13:30.07#ibcon#about to read 3, iclass 21, count 2 2006.176.08:13:30.10#ibcon#read 3, iclass 21, count 2 2006.176.08:13:30.10#ibcon#about to read 4, iclass 21, count 2 2006.176.08:13:30.10#ibcon#read 4, iclass 21, count 2 2006.176.08:13:30.10#ibcon#about to read 5, iclass 21, count 2 2006.176.08:13:30.10#ibcon#read 5, iclass 21, count 2 2006.176.08:13:30.10#ibcon#about to read 6, iclass 21, count 2 2006.176.08:13:30.10#ibcon#read 6, iclass 21, count 2 2006.176.08:13:30.10#ibcon#end of sib2, iclass 21, count 2 2006.176.08:13:30.10#ibcon#*after write, iclass 21, count 2 2006.176.08:13:30.10#ibcon#*before return 0, iclass 21, count 2 2006.176.08:13:30.10#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:13:30.10#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:13:30.10#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.176.08:13:30.10#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:30.10#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:13:30.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:13:30.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:13:30.22#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:13:30.22#ibcon#first serial, iclass 21, count 0 2006.176.08:13:30.22#ibcon#enter sib2, iclass 21, count 0 2006.176.08:13:30.22#ibcon#flushed, iclass 21, count 0 2006.176.08:13:30.22#ibcon#about to write, iclass 21, count 0 2006.176.08:13:30.22#ibcon#wrote, iclass 21, count 0 2006.176.08:13:30.22#ibcon#about to read 3, iclass 21, count 0 2006.176.08:13:30.24#ibcon#read 3, iclass 21, count 0 2006.176.08:13:30.24#ibcon#about to read 4, iclass 21, count 0 2006.176.08:13:30.24#ibcon#read 4, iclass 21, count 0 2006.176.08:13:30.24#ibcon#about to read 5, iclass 21, count 0 2006.176.08:13:30.24#ibcon#read 5, iclass 21, count 0 2006.176.08:13:30.24#ibcon#about to read 6, iclass 21, count 0 2006.176.08:13:30.24#ibcon#read 6, iclass 21, count 0 2006.176.08:13:30.24#ibcon#end of sib2, iclass 21, count 0 2006.176.08:13:30.24#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:13:30.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:13:30.24#ibcon#[25=USB\r\n] 2006.176.08:13:30.24#ibcon#*before write, iclass 21, count 0 2006.176.08:13:30.24#ibcon#enter sib2, iclass 21, count 0 2006.176.08:13:30.24#ibcon#flushed, iclass 21, count 0 2006.176.08:13:30.24#ibcon#about to write, iclass 21, count 0 2006.176.08:13:30.24#ibcon#wrote, iclass 21, count 0 2006.176.08:13:30.24#ibcon#about to read 3, iclass 21, count 0 2006.176.08:13:30.27#ibcon#read 3, iclass 21, count 0 2006.176.08:13:30.27#ibcon#about to read 4, iclass 21, count 0 2006.176.08:13:30.27#ibcon#read 4, iclass 21, count 0 2006.176.08:13:30.27#ibcon#about to read 5, iclass 21, count 0 2006.176.08:13:30.27#ibcon#read 5, iclass 21, count 0 2006.176.08:13:30.27#ibcon#about to read 6, iclass 21, count 0 2006.176.08:13:30.27#ibcon#read 6, iclass 21, count 0 2006.176.08:13:30.27#ibcon#end of sib2, iclass 21, count 0 2006.176.08:13:30.27#ibcon#*after write, iclass 21, count 0 2006.176.08:13:30.27#ibcon#*before return 0, iclass 21, count 0 2006.176.08:13:30.27#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:13:30.27#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:13:30.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:13:30.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:13:30.27$vc4f8/valo=8,852.99 2006.176.08:13:30.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.08:13:30.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.08:13:30.27#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:30.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:13:30.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:13:30.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:13:30.27#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:13:30.27#ibcon#first serial, iclass 23, count 0 2006.176.08:13:30.27#ibcon#enter sib2, iclass 23, count 0 2006.176.08:13:30.27#ibcon#flushed, iclass 23, count 0 2006.176.08:13:30.27#ibcon#about to write, iclass 23, count 0 2006.176.08:13:30.27#ibcon#wrote, iclass 23, count 0 2006.176.08:13:30.27#ibcon#about to read 3, iclass 23, count 0 2006.176.08:13:30.29#ibcon#read 3, iclass 23, count 0 2006.176.08:13:30.29#ibcon#about to read 4, iclass 23, count 0 2006.176.08:13:30.29#ibcon#read 4, iclass 23, count 0 2006.176.08:13:30.29#ibcon#about to read 5, iclass 23, count 0 2006.176.08:13:30.29#ibcon#read 5, iclass 23, count 0 2006.176.08:13:30.29#ibcon#about to read 6, iclass 23, count 0 2006.176.08:13:30.29#ibcon#read 6, iclass 23, count 0 2006.176.08:13:30.29#ibcon#end of sib2, iclass 23, count 0 2006.176.08:13:30.29#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:13:30.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:13:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:13:30.29#ibcon#*before write, iclass 23, count 0 2006.176.08:13:30.29#ibcon#enter sib2, iclass 23, count 0 2006.176.08:13:30.29#ibcon#flushed, iclass 23, count 0 2006.176.08:13:30.29#ibcon#about to write, iclass 23, count 0 2006.176.08:13:30.29#ibcon#wrote, iclass 23, count 0 2006.176.08:13:30.29#ibcon#about to read 3, iclass 23, count 0 2006.176.08:13:30.33#ibcon#read 3, iclass 23, count 0 2006.176.08:13:30.33#ibcon#about to read 4, iclass 23, count 0 2006.176.08:13:30.33#ibcon#read 4, iclass 23, count 0 2006.176.08:13:30.33#ibcon#about to read 5, iclass 23, count 0 2006.176.08:13:30.33#ibcon#read 5, iclass 23, count 0 2006.176.08:13:30.33#ibcon#about to read 6, iclass 23, count 0 2006.176.08:13:30.33#ibcon#read 6, iclass 23, count 0 2006.176.08:13:30.33#ibcon#end of sib2, iclass 23, count 0 2006.176.08:13:30.33#ibcon#*after write, iclass 23, count 0 2006.176.08:13:30.33#ibcon#*before return 0, iclass 23, count 0 2006.176.08:13:30.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:13:30.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:13:30.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:13:30.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:13:30.33$vc4f8/va=8,6 2006.176.08:13:30.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.176.08:13:30.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.176.08:13:30.33#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:30.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:13:30.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:13:30.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:13:30.39#ibcon#enter wrdev, iclass 25, count 2 2006.176.08:13:30.39#ibcon#first serial, iclass 25, count 2 2006.176.08:13:30.39#ibcon#enter sib2, iclass 25, count 2 2006.176.08:13:30.39#ibcon#flushed, iclass 25, count 2 2006.176.08:13:30.39#ibcon#about to write, iclass 25, count 2 2006.176.08:13:30.39#ibcon#wrote, iclass 25, count 2 2006.176.08:13:30.39#ibcon#about to read 3, iclass 25, count 2 2006.176.08:13:30.41#ibcon#read 3, iclass 25, count 2 2006.176.08:13:30.41#ibcon#about to read 4, iclass 25, count 2 2006.176.08:13:30.41#ibcon#read 4, iclass 25, count 2 2006.176.08:13:30.41#ibcon#about to read 5, iclass 25, count 2 2006.176.08:13:30.41#ibcon#read 5, iclass 25, count 2 2006.176.08:13:30.41#ibcon#about to read 6, iclass 25, count 2 2006.176.08:13:30.41#ibcon#read 6, iclass 25, count 2 2006.176.08:13:30.41#ibcon#end of sib2, iclass 25, count 2 2006.176.08:13:30.41#ibcon#*mode == 0, iclass 25, count 2 2006.176.08:13:30.41#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.176.08:13:30.41#ibcon#[25=AT08-06\r\n] 2006.176.08:13:30.41#ibcon#*before write, iclass 25, count 2 2006.176.08:13:30.41#ibcon#enter sib2, iclass 25, count 2 2006.176.08:13:30.41#ibcon#flushed, iclass 25, count 2 2006.176.08:13:30.41#ibcon#about to write, iclass 25, count 2 2006.176.08:13:30.41#ibcon#wrote, iclass 25, count 2 2006.176.08:13:30.41#ibcon#about to read 3, iclass 25, count 2 2006.176.08:13:30.44#ibcon#read 3, iclass 25, count 2 2006.176.08:13:30.44#ibcon#about to read 4, iclass 25, count 2 2006.176.08:13:30.44#ibcon#read 4, iclass 25, count 2 2006.176.08:13:30.44#ibcon#about to read 5, iclass 25, count 2 2006.176.08:13:30.44#ibcon#read 5, iclass 25, count 2 2006.176.08:13:30.44#ibcon#about to read 6, iclass 25, count 2 2006.176.08:13:30.44#ibcon#read 6, iclass 25, count 2 2006.176.08:13:30.44#ibcon#end of sib2, iclass 25, count 2 2006.176.08:13:30.44#ibcon#*after write, iclass 25, count 2 2006.176.08:13:30.44#ibcon#*before return 0, iclass 25, count 2 2006.176.08:13:30.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:13:30.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:13:30.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.176.08:13:30.44#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:30.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:13:30.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:13:30.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:13:30.56#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:13:30.56#ibcon#first serial, iclass 25, count 0 2006.176.08:13:30.56#ibcon#enter sib2, iclass 25, count 0 2006.176.08:13:30.56#ibcon#flushed, iclass 25, count 0 2006.176.08:13:30.56#ibcon#about to write, iclass 25, count 0 2006.176.08:13:30.56#ibcon#wrote, iclass 25, count 0 2006.176.08:13:30.56#ibcon#about to read 3, iclass 25, count 0 2006.176.08:13:30.58#ibcon#read 3, iclass 25, count 0 2006.176.08:13:30.58#ibcon#about to read 4, iclass 25, count 0 2006.176.08:13:30.58#ibcon#read 4, iclass 25, count 0 2006.176.08:13:30.58#ibcon#about to read 5, iclass 25, count 0 2006.176.08:13:30.58#ibcon#read 5, iclass 25, count 0 2006.176.08:13:30.58#ibcon#about to read 6, iclass 25, count 0 2006.176.08:13:30.58#ibcon#read 6, iclass 25, count 0 2006.176.08:13:30.58#ibcon#end of sib2, iclass 25, count 0 2006.176.08:13:30.58#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:13:30.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:13:30.58#ibcon#[25=USB\r\n] 2006.176.08:13:30.58#ibcon#*before write, iclass 25, count 0 2006.176.08:13:30.58#ibcon#enter sib2, iclass 25, count 0 2006.176.08:13:30.58#ibcon#flushed, iclass 25, count 0 2006.176.08:13:30.58#ibcon#about to write, iclass 25, count 0 2006.176.08:13:30.58#ibcon#wrote, iclass 25, count 0 2006.176.08:13:30.58#ibcon#about to read 3, iclass 25, count 0 2006.176.08:13:30.61#ibcon#read 3, iclass 25, count 0 2006.176.08:13:30.61#ibcon#about to read 4, iclass 25, count 0 2006.176.08:13:30.61#ibcon#read 4, iclass 25, count 0 2006.176.08:13:30.61#ibcon#about to read 5, iclass 25, count 0 2006.176.08:13:30.61#ibcon#read 5, iclass 25, count 0 2006.176.08:13:30.61#ibcon#about to read 6, iclass 25, count 0 2006.176.08:13:30.61#ibcon#read 6, iclass 25, count 0 2006.176.08:13:30.61#ibcon#end of sib2, iclass 25, count 0 2006.176.08:13:30.61#ibcon#*after write, iclass 25, count 0 2006.176.08:13:30.61#ibcon#*before return 0, iclass 25, count 0 2006.176.08:13:30.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:13:30.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:13:30.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:13:30.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:13:30.61$vc4f8/vblo=1,632.99 2006.176.08:13:30.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.08:13:30.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.08:13:30.61#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:30.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:13:30.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:13:30.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:13:30.61#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:13:30.61#ibcon#first serial, iclass 27, count 0 2006.176.08:13:30.61#ibcon#enter sib2, iclass 27, count 0 2006.176.08:13:30.61#ibcon#flushed, iclass 27, count 0 2006.176.08:13:30.61#ibcon#about to write, iclass 27, count 0 2006.176.08:13:30.61#ibcon#wrote, iclass 27, count 0 2006.176.08:13:30.61#ibcon#about to read 3, iclass 27, count 0 2006.176.08:13:30.63#ibcon#read 3, iclass 27, count 0 2006.176.08:13:30.63#ibcon#about to read 4, iclass 27, count 0 2006.176.08:13:30.63#ibcon#read 4, iclass 27, count 0 2006.176.08:13:30.63#ibcon#about to read 5, iclass 27, count 0 2006.176.08:13:30.63#ibcon#read 5, iclass 27, count 0 2006.176.08:13:30.63#ibcon#about to read 6, iclass 27, count 0 2006.176.08:13:30.63#ibcon#read 6, iclass 27, count 0 2006.176.08:13:30.63#ibcon#end of sib2, iclass 27, count 0 2006.176.08:13:30.63#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:13:30.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:13:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:13:30.63#ibcon#*before write, iclass 27, count 0 2006.176.08:13:30.63#ibcon#enter sib2, iclass 27, count 0 2006.176.08:13:30.63#ibcon#flushed, iclass 27, count 0 2006.176.08:13:30.63#ibcon#about to write, iclass 27, count 0 2006.176.08:13:30.63#ibcon#wrote, iclass 27, count 0 2006.176.08:13:30.63#ibcon#about to read 3, iclass 27, count 0 2006.176.08:13:30.67#ibcon#read 3, iclass 27, count 0 2006.176.08:13:30.67#ibcon#about to read 4, iclass 27, count 0 2006.176.08:13:30.67#ibcon#read 4, iclass 27, count 0 2006.176.08:13:30.67#ibcon#about to read 5, iclass 27, count 0 2006.176.08:13:30.67#ibcon#read 5, iclass 27, count 0 2006.176.08:13:30.67#ibcon#about to read 6, iclass 27, count 0 2006.176.08:13:30.67#ibcon#read 6, iclass 27, count 0 2006.176.08:13:30.67#ibcon#end of sib2, iclass 27, count 0 2006.176.08:13:30.67#ibcon#*after write, iclass 27, count 0 2006.176.08:13:30.67#ibcon#*before return 0, iclass 27, count 0 2006.176.08:13:30.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:13:30.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:13:30.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:13:30.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:13:30.67$vc4f8/vb=1,4 2006.176.08:13:30.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.08:13:30.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.08:13:30.67#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:30.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:13:30.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:13:30.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:13:30.67#ibcon#enter wrdev, iclass 29, count 2 2006.176.08:13:30.67#ibcon#first serial, iclass 29, count 2 2006.176.08:13:30.67#ibcon#enter sib2, iclass 29, count 2 2006.176.08:13:30.67#ibcon#flushed, iclass 29, count 2 2006.176.08:13:30.67#ibcon#about to write, iclass 29, count 2 2006.176.08:13:30.67#ibcon#wrote, iclass 29, count 2 2006.176.08:13:30.67#ibcon#about to read 3, iclass 29, count 2 2006.176.08:13:30.69#ibcon#read 3, iclass 29, count 2 2006.176.08:13:30.69#ibcon#about to read 4, iclass 29, count 2 2006.176.08:13:30.69#ibcon#read 4, iclass 29, count 2 2006.176.08:13:30.69#ibcon#about to read 5, iclass 29, count 2 2006.176.08:13:30.69#ibcon#read 5, iclass 29, count 2 2006.176.08:13:30.69#ibcon#about to read 6, iclass 29, count 2 2006.176.08:13:30.69#ibcon#read 6, iclass 29, count 2 2006.176.08:13:30.69#ibcon#end of sib2, iclass 29, count 2 2006.176.08:13:30.69#ibcon#*mode == 0, iclass 29, count 2 2006.176.08:13:30.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.08:13:30.69#ibcon#[27=AT01-04\r\n] 2006.176.08:13:30.69#ibcon#*before write, iclass 29, count 2 2006.176.08:13:30.69#ibcon#enter sib2, iclass 29, count 2 2006.176.08:13:30.69#ibcon#flushed, iclass 29, count 2 2006.176.08:13:30.69#ibcon#about to write, iclass 29, count 2 2006.176.08:13:30.69#ibcon#wrote, iclass 29, count 2 2006.176.08:13:30.69#ibcon#about to read 3, iclass 29, count 2 2006.176.08:13:30.72#ibcon#read 3, iclass 29, count 2 2006.176.08:13:30.72#ibcon#about to read 4, iclass 29, count 2 2006.176.08:13:30.72#ibcon#read 4, iclass 29, count 2 2006.176.08:13:30.72#ibcon#about to read 5, iclass 29, count 2 2006.176.08:13:30.72#ibcon#read 5, iclass 29, count 2 2006.176.08:13:30.72#ibcon#about to read 6, iclass 29, count 2 2006.176.08:13:30.72#ibcon#read 6, iclass 29, count 2 2006.176.08:13:30.72#ibcon#end of sib2, iclass 29, count 2 2006.176.08:13:30.72#ibcon#*after write, iclass 29, count 2 2006.176.08:13:30.72#ibcon#*before return 0, iclass 29, count 2 2006.176.08:13:30.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:13:30.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:13:30.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.08:13:30.72#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:30.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:13:30.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:13:30.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:13:30.84#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:13:30.84#ibcon#first serial, iclass 29, count 0 2006.176.08:13:30.84#ibcon#enter sib2, iclass 29, count 0 2006.176.08:13:30.84#ibcon#flushed, iclass 29, count 0 2006.176.08:13:30.84#ibcon#about to write, iclass 29, count 0 2006.176.08:13:30.84#ibcon#wrote, iclass 29, count 0 2006.176.08:13:30.84#ibcon#about to read 3, iclass 29, count 0 2006.176.08:13:30.86#ibcon#read 3, iclass 29, count 0 2006.176.08:13:30.86#ibcon#about to read 4, iclass 29, count 0 2006.176.08:13:30.86#ibcon#read 4, iclass 29, count 0 2006.176.08:13:30.86#ibcon#about to read 5, iclass 29, count 0 2006.176.08:13:30.86#ibcon#read 5, iclass 29, count 0 2006.176.08:13:30.86#ibcon#about to read 6, iclass 29, count 0 2006.176.08:13:30.86#ibcon#read 6, iclass 29, count 0 2006.176.08:13:30.86#ibcon#end of sib2, iclass 29, count 0 2006.176.08:13:30.86#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:13:30.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:13:30.86#ibcon#[27=USB\r\n] 2006.176.08:13:30.86#ibcon#*before write, iclass 29, count 0 2006.176.08:13:30.86#ibcon#enter sib2, iclass 29, count 0 2006.176.08:13:30.86#ibcon#flushed, iclass 29, count 0 2006.176.08:13:30.86#ibcon#about to write, iclass 29, count 0 2006.176.08:13:30.86#ibcon#wrote, iclass 29, count 0 2006.176.08:13:30.86#ibcon#about to read 3, iclass 29, count 0 2006.176.08:13:30.89#ibcon#read 3, iclass 29, count 0 2006.176.08:13:30.89#ibcon#about to read 4, iclass 29, count 0 2006.176.08:13:30.89#ibcon#read 4, iclass 29, count 0 2006.176.08:13:30.89#ibcon#about to read 5, iclass 29, count 0 2006.176.08:13:30.89#ibcon#read 5, iclass 29, count 0 2006.176.08:13:30.89#ibcon#about to read 6, iclass 29, count 0 2006.176.08:13:30.89#ibcon#read 6, iclass 29, count 0 2006.176.08:13:30.89#ibcon#end of sib2, iclass 29, count 0 2006.176.08:13:30.89#ibcon#*after write, iclass 29, count 0 2006.176.08:13:30.89#ibcon#*before return 0, iclass 29, count 0 2006.176.08:13:30.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:13:30.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:13:30.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:13:30.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:13:30.89$vc4f8/vblo=2,640.99 2006.176.08:13:30.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.08:13:30.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.08:13:30.89#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:30.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:30.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:30.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:30.89#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:13:30.89#ibcon#first serial, iclass 31, count 0 2006.176.08:13:30.89#ibcon#enter sib2, iclass 31, count 0 2006.176.08:13:30.89#ibcon#flushed, iclass 31, count 0 2006.176.08:13:30.89#ibcon#about to write, iclass 31, count 0 2006.176.08:13:30.89#ibcon#wrote, iclass 31, count 0 2006.176.08:13:30.89#ibcon#about to read 3, iclass 31, count 0 2006.176.08:13:30.91#ibcon#read 3, iclass 31, count 0 2006.176.08:13:30.91#ibcon#about to read 4, iclass 31, count 0 2006.176.08:13:30.91#ibcon#read 4, iclass 31, count 0 2006.176.08:13:30.91#ibcon#about to read 5, iclass 31, count 0 2006.176.08:13:30.91#ibcon#read 5, iclass 31, count 0 2006.176.08:13:30.91#ibcon#about to read 6, iclass 31, count 0 2006.176.08:13:30.91#ibcon#read 6, iclass 31, count 0 2006.176.08:13:30.91#ibcon#end of sib2, iclass 31, count 0 2006.176.08:13:30.91#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:13:30.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:13:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:13:30.91#ibcon#*before write, iclass 31, count 0 2006.176.08:13:30.91#ibcon#enter sib2, iclass 31, count 0 2006.176.08:13:30.91#ibcon#flushed, iclass 31, count 0 2006.176.08:13:30.91#ibcon#about to write, iclass 31, count 0 2006.176.08:13:30.91#ibcon#wrote, iclass 31, count 0 2006.176.08:13:30.91#ibcon#about to read 3, iclass 31, count 0 2006.176.08:13:30.95#ibcon#read 3, iclass 31, count 0 2006.176.08:13:30.95#ibcon#about to read 4, iclass 31, count 0 2006.176.08:13:30.95#ibcon#read 4, iclass 31, count 0 2006.176.08:13:30.95#ibcon#about to read 5, iclass 31, count 0 2006.176.08:13:30.95#ibcon#read 5, iclass 31, count 0 2006.176.08:13:30.95#ibcon#about to read 6, iclass 31, count 0 2006.176.08:13:30.95#ibcon#read 6, iclass 31, count 0 2006.176.08:13:30.95#ibcon#end of sib2, iclass 31, count 0 2006.176.08:13:30.95#ibcon#*after write, iclass 31, count 0 2006.176.08:13:30.95#ibcon#*before return 0, iclass 31, count 0 2006.176.08:13:30.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:30.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:13:30.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:13:30.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:13:30.95$vc4f8/vb=2,4 2006.176.08:13:30.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.176.08:13:30.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.176.08:13:30.95#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:30.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:31.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:31.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:31.01#ibcon#enter wrdev, iclass 33, count 2 2006.176.08:13:31.01#ibcon#first serial, iclass 33, count 2 2006.176.08:13:31.01#ibcon#enter sib2, iclass 33, count 2 2006.176.08:13:31.01#ibcon#flushed, iclass 33, count 2 2006.176.08:13:31.01#ibcon#about to write, iclass 33, count 2 2006.176.08:13:31.01#ibcon#wrote, iclass 33, count 2 2006.176.08:13:31.01#ibcon#about to read 3, iclass 33, count 2 2006.176.08:13:31.03#ibcon#read 3, iclass 33, count 2 2006.176.08:13:31.03#ibcon#about to read 4, iclass 33, count 2 2006.176.08:13:31.03#ibcon#read 4, iclass 33, count 2 2006.176.08:13:31.03#ibcon#about to read 5, iclass 33, count 2 2006.176.08:13:31.03#ibcon#read 5, iclass 33, count 2 2006.176.08:13:31.03#ibcon#about to read 6, iclass 33, count 2 2006.176.08:13:31.03#ibcon#read 6, iclass 33, count 2 2006.176.08:13:31.03#ibcon#end of sib2, iclass 33, count 2 2006.176.08:13:31.03#ibcon#*mode == 0, iclass 33, count 2 2006.176.08:13:31.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.176.08:13:31.03#ibcon#[27=AT02-04\r\n] 2006.176.08:13:31.03#ibcon#*before write, iclass 33, count 2 2006.176.08:13:31.03#ibcon#enter sib2, iclass 33, count 2 2006.176.08:13:31.03#ibcon#flushed, iclass 33, count 2 2006.176.08:13:31.03#ibcon#about to write, iclass 33, count 2 2006.176.08:13:31.03#ibcon#wrote, iclass 33, count 2 2006.176.08:13:31.03#ibcon#about to read 3, iclass 33, count 2 2006.176.08:13:31.06#ibcon#read 3, iclass 33, count 2 2006.176.08:13:31.06#ibcon#about to read 4, iclass 33, count 2 2006.176.08:13:31.06#ibcon#read 4, iclass 33, count 2 2006.176.08:13:31.06#ibcon#about to read 5, iclass 33, count 2 2006.176.08:13:31.06#ibcon#read 5, iclass 33, count 2 2006.176.08:13:31.06#ibcon#about to read 6, iclass 33, count 2 2006.176.08:13:31.06#ibcon#read 6, iclass 33, count 2 2006.176.08:13:31.06#ibcon#end of sib2, iclass 33, count 2 2006.176.08:13:31.06#ibcon#*after write, iclass 33, count 2 2006.176.08:13:31.06#ibcon#*before return 0, iclass 33, count 2 2006.176.08:13:31.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:31.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:13:31.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.176.08:13:31.06#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:31.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:31.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:31.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:31.18#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:13:31.18#ibcon#first serial, iclass 33, count 0 2006.176.08:13:31.18#ibcon#enter sib2, iclass 33, count 0 2006.176.08:13:31.18#ibcon#flushed, iclass 33, count 0 2006.176.08:13:31.18#ibcon#about to write, iclass 33, count 0 2006.176.08:13:31.18#ibcon#wrote, iclass 33, count 0 2006.176.08:13:31.18#ibcon#about to read 3, iclass 33, count 0 2006.176.08:13:31.20#ibcon#read 3, iclass 33, count 0 2006.176.08:13:31.20#ibcon#about to read 4, iclass 33, count 0 2006.176.08:13:31.20#ibcon#read 4, iclass 33, count 0 2006.176.08:13:31.20#ibcon#about to read 5, iclass 33, count 0 2006.176.08:13:31.20#ibcon#read 5, iclass 33, count 0 2006.176.08:13:31.20#ibcon#about to read 6, iclass 33, count 0 2006.176.08:13:31.20#ibcon#read 6, iclass 33, count 0 2006.176.08:13:31.20#ibcon#end of sib2, iclass 33, count 0 2006.176.08:13:31.20#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:13:31.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:13:31.20#ibcon#[27=USB\r\n] 2006.176.08:13:31.20#ibcon#*before write, iclass 33, count 0 2006.176.08:13:31.20#ibcon#enter sib2, iclass 33, count 0 2006.176.08:13:31.20#ibcon#flushed, iclass 33, count 0 2006.176.08:13:31.20#ibcon#about to write, iclass 33, count 0 2006.176.08:13:31.20#ibcon#wrote, iclass 33, count 0 2006.176.08:13:31.20#ibcon#about to read 3, iclass 33, count 0 2006.176.08:13:31.23#ibcon#read 3, iclass 33, count 0 2006.176.08:13:31.23#ibcon#about to read 4, iclass 33, count 0 2006.176.08:13:31.23#ibcon#read 4, iclass 33, count 0 2006.176.08:13:31.23#ibcon#about to read 5, iclass 33, count 0 2006.176.08:13:31.23#ibcon#read 5, iclass 33, count 0 2006.176.08:13:31.23#ibcon#about to read 6, iclass 33, count 0 2006.176.08:13:31.23#ibcon#read 6, iclass 33, count 0 2006.176.08:13:31.23#ibcon#end of sib2, iclass 33, count 0 2006.176.08:13:31.23#ibcon#*after write, iclass 33, count 0 2006.176.08:13:31.23#ibcon#*before return 0, iclass 33, count 0 2006.176.08:13:31.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:31.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:13:31.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:13:31.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:13:31.23$vc4f8/vblo=3,656.99 2006.176.08:13:31.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.08:13:31.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.08:13:31.23#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:31.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:31.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:31.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:31.23#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:13:31.23#ibcon#first serial, iclass 35, count 0 2006.176.08:13:31.23#ibcon#enter sib2, iclass 35, count 0 2006.176.08:13:31.23#ibcon#flushed, iclass 35, count 0 2006.176.08:13:31.23#ibcon#about to write, iclass 35, count 0 2006.176.08:13:31.23#ibcon#wrote, iclass 35, count 0 2006.176.08:13:31.23#ibcon#about to read 3, iclass 35, count 0 2006.176.08:13:31.25#ibcon#read 3, iclass 35, count 0 2006.176.08:13:31.25#ibcon#about to read 4, iclass 35, count 0 2006.176.08:13:31.25#ibcon#read 4, iclass 35, count 0 2006.176.08:13:31.25#ibcon#about to read 5, iclass 35, count 0 2006.176.08:13:31.25#ibcon#read 5, iclass 35, count 0 2006.176.08:13:31.25#ibcon#about to read 6, iclass 35, count 0 2006.176.08:13:31.25#ibcon#read 6, iclass 35, count 0 2006.176.08:13:31.25#ibcon#end of sib2, iclass 35, count 0 2006.176.08:13:31.25#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:13:31.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:13:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:13:31.25#ibcon#*before write, iclass 35, count 0 2006.176.08:13:31.25#ibcon#enter sib2, iclass 35, count 0 2006.176.08:13:31.25#ibcon#flushed, iclass 35, count 0 2006.176.08:13:31.25#ibcon#about to write, iclass 35, count 0 2006.176.08:13:31.25#ibcon#wrote, iclass 35, count 0 2006.176.08:13:31.25#ibcon#about to read 3, iclass 35, count 0 2006.176.08:13:31.29#ibcon#read 3, iclass 35, count 0 2006.176.08:13:31.29#ibcon#about to read 4, iclass 35, count 0 2006.176.08:13:31.29#ibcon#read 4, iclass 35, count 0 2006.176.08:13:31.29#ibcon#about to read 5, iclass 35, count 0 2006.176.08:13:31.29#ibcon#read 5, iclass 35, count 0 2006.176.08:13:31.29#ibcon#about to read 6, iclass 35, count 0 2006.176.08:13:31.29#ibcon#read 6, iclass 35, count 0 2006.176.08:13:31.29#ibcon#end of sib2, iclass 35, count 0 2006.176.08:13:31.29#ibcon#*after write, iclass 35, count 0 2006.176.08:13:31.29#ibcon#*before return 0, iclass 35, count 0 2006.176.08:13:31.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:31.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:13:31.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:13:31.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:13:31.29$vc4f8/vb=3,4 2006.176.08:13:31.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.176.08:13:31.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.176.08:13:31.29#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:31.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:31.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:31.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:31.35#ibcon#enter wrdev, iclass 37, count 2 2006.176.08:13:31.35#ibcon#first serial, iclass 37, count 2 2006.176.08:13:31.35#ibcon#enter sib2, iclass 37, count 2 2006.176.08:13:31.35#ibcon#flushed, iclass 37, count 2 2006.176.08:13:31.35#ibcon#about to write, iclass 37, count 2 2006.176.08:13:31.35#ibcon#wrote, iclass 37, count 2 2006.176.08:13:31.35#ibcon#about to read 3, iclass 37, count 2 2006.176.08:13:31.37#ibcon#read 3, iclass 37, count 2 2006.176.08:13:31.37#ibcon#about to read 4, iclass 37, count 2 2006.176.08:13:31.37#ibcon#read 4, iclass 37, count 2 2006.176.08:13:31.37#ibcon#about to read 5, iclass 37, count 2 2006.176.08:13:31.37#ibcon#read 5, iclass 37, count 2 2006.176.08:13:31.37#ibcon#about to read 6, iclass 37, count 2 2006.176.08:13:31.37#ibcon#read 6, iclass 37, count 2 2006.176.08:13:31.37#ibcon#end of sib2, iclass 37, count 2 2006.176.08:13:31.37#ibcon#*mode == 0, iclass 37, count 2 2006.176.08:13:31.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.176.08:13:31.37#ibcon#[27=AT03-04\r\n] 2006.176.08:13:31.37#ibcon#*before write, iclass 37, count 2 2006.176.08:13:31.37#ibcon#enter sib2, iclass 37, count 2 2006.176.08:13:31.37#ibcon#flushed, iclass 37, count 2 2006.176.08:13:31.37#ibcon#about to write, iclass 37, count 2 2006.176.08:13:31.37#ibcon#wrote, iclass 37, count 2 2006.176.08:13:31.37#ibcon#about to read 3, iclass 37, count 2 2006.176.08:13:31.40#ibcon#read 3, iclass 37, count 2 2006.176.08:13:31.40#ibcon#about to read 4, iclass 37, count 2 2006.176.08:13:31.40#ibcon#read 4, iclass 37, count 2 2006.176.08:13:31.40#ibcon#about to read 5, iclass 37, count 2 2006.176.08:13:31.40#ibcon#read 5, iclass 37, count 2 2006.176.08:13:31.40#ibcon#about to read 6, iclass 37, count 2 2006.176.08:13:31.40#ibcon#read 6, iclass 37, count 2 2006.176.08:13:31.40#ibcon#end of sib2, iclass 37, count 2 2006.176.08:13:31.40#ibcon#*after write, iclass 37, count 2 2006.176.08:13:31.40#ibcon#*before return 0, iclass 37, count 2 2006.176.08:13:31.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:31.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:13:31.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.176.08:13:31.40#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:31.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:31.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:31.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:31.52#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:13:31.52#ibcon#first serial, iclass 37, count 0 2006.176.08:13:31.52#ibcon#enter sib2, iclass 37, count 0 2006.176.08:13:31.52#ibcon#flushed, iclass 37, count 0 2006.176.08:13:31.52#ibcon#about to write, iclass 37, count 0 2006.176.08:13:31.52#ibcon#wrote, iclass 37, count 0 2006.176.08:13:31.52#ibcon#about to read 3, iclass 37, count 0 2006.176.08:13:31.54#ibcon#read 3, iclass 37, count 0 2006.176.08:13:31.54#ibcon#about to read 4, iclass 37, count 0 2006.176.08:13:31.54#ibcon#read 4, iclass 37, count 0 2006.176.08:13:31.54#ibcon#about to read 5, iclass 37, count 0 2006.176.08:13:31.54#ibcon#read 5, iclass 37, count 0 2006.176.08:13:31.54#ibcon#about to read 6, iclass 37, count 0 2006.176.08:13:31.54#ibcon#read 6, iclass 37, count 0 2006.176.08:13:31.54#ibcon#end of sib2, iclass 37, count 0 2006.176.08:13:31.54#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:13:31.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:13:31.54#ibcon#[27=USB\r\n] 2006.176.08:13:31.54#ibcon#*before write, iclass 37, count 0 2006.176.08:13:31.54#ibcon#enter sib2, iclass 37, count 0 2006.176.08:13:31.54#ibcon#flushed, iclass 37, count 0 2006.176.08:13:31.54#ibcon#about to write, iclass 37, count 0 2006.176.08:13:31.54#ibcon#wrote, iclass 37, count 0 2006.176.08:13:31.54#ibcon#about to read 3, iclass 37, count 0 2006.176.08:13:31.57#ibcon#read 3, iclass 37, count 0 2006.176.08:13:31.57#ibcon#about to read 4, iclass 37, count 0 2006.176.08:13:31.57#ibcon#read 4, iclass 37, count 0 2006.176.08:13:31.57#ibcon#about to read 5, iclass 37, count 0 2006.176.08:13:31.57#ibcon#read 5, iclass 37, count 0 2006.176.08:13:31.57#ibcon#about to read 6, iclass 37, count 0 2006.176.08:13:31.57#ibcon#read 6, iclass 37, count 0 2006.176.08:13:31.57#ibcon#end of sib2, iclass 37, count 0 2006.176.08:13:31.57#ibcon#*after write, iclass 37, count 0 2006.176.08:13:31.57#ibcon#*before return 0, iclass 37, count 0 2006.176.08:13:31.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:31.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:13:31.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:13:31.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:13:31.57$vc4f8/vblo=4,712.99 2006.176.08:13:31.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.08:13:31.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.08:13:31.57#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:31.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:31.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:31.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:31.57#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:13:31.57#ibcon#first serial, iclass 39, count 0 2006.176.08:13:31.57#ibcon#enter sib2, iclass 39, count 0 2006.176.08:13:31.57#ibcon#flushed, iclass 39, count 0 2006.176.08:13:31.57#ibcon#about to write, iclass 39, count 0 2006.176.08:13:31.57#ibcon#wrote, iclass 39, count 0 2006.176.08:13:31.57#ibcon#about to read 3, iclass 39, count 0 2006.176.08:13:31.59#ibcon#read 3, iclass 39, count 0 2006.176.08:13:31.59#ibcon#about to read 4, iclass 39, count 0 2006.176.08:13:31.59#ibcon#read 4, iclass 39, count 0 2006.176.08:13:31.59#ibcon#about to read 5, iclass 39, count 0 2006.176.08:13:31.59#ibcon#read 5, iclass 39, count 0 2006.176.08:13:31.59#ibcon#about to read 6, iclass 39, count 0 2006.176.08:13:31.59#ibcon#read 6, iclass 39, count 0 2006.176.08:13:31.59#ibcon#end of sib2, iclass 39, count 0 2006.176.08:13:31.59#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:13:31.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:13:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:13:31.59#ibcon#*before write, iclass 39, count 0 2006.176.08:13:31.59#ibcon#enter sib2, iclass 39, count 0 2006.176.08:13:31.59#ibcon#flushed, iclass 39, count 0 2006.176.08:13:31.59#ibcon#about to write, iclass 39, count 0 2006.176.08:13:31.59#ibcon#wrote, iclass 39, count 0 2006.176.08:13:31.59#ibcon#about to read 3, iclass 39, count 0 2006.176.08:13:31.63#ibcon#read 3, iclass 39, count 0 2006.176.08:13:31.63#ibcon#about to read 4, iclass 39, count 0 2006.176.08:13:31.63#ibcon#read 4, iclass 39, count 0 2006.176.08:13:31.63#ibcon#about to read 5, iclass 39, count 0 2006.176.08:13:31.63#ibcon#read 5, iclass 39, count 0 2006.176.08:13:31.63#ibcon#about to read 6, iclass 39, count 0 2006.176.08:13:31.63#ibcon#read 6, iclass 39, count 0 2006.176.08:13:31.63#ibcon#end of sib2, iclass 39, count 0 2006.176.08:13:31.63#ibcon#*after write, iclass 39, count 0 2006.176.08:13:31.63#ibcon#*before return 0, iclass 39, count 0 2006.176.08:13:31.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:31.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:13:31.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:13:31.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:13:31.63$vc4f8/vb=4,4 2006.176.08:13:31.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.08:13:31.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.08:13:31.63#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:31.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:31.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:31.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:31.69#ibcon#enter wrdev, iclass 3, count 2 2006.176.08:13:31.69#ibcon#first serial, iclass 3, count 2 2006.176.08:13:31.69#ibcon#enter sib2, iclass 3, count 2 2006.176.08:13:31.69#ibcon#flushed, iclass 3, count 2 2006.176.08:13:31.69#ibcon#about to write, iclass 3, count 2 2006.176.08:13:31.69#ibcon#wrote, iclass 3, count 2 2006.176.08:13:31.69#ibcon#about to read 3, iclass 3, count 2 2006.176.08:13:31.71#ibcon#read 3, iclass 3, count 2 2006.176.08:13:31.71#ibcon#about to read 4, iclass 3, count 2 2006.176.08:13:31.71#ibcon#read 4, iclass 3, count 2 2006.176.08:13:31.71#ibcon#about to read 5, iclass 3, count 2 2006.176.08:13:31.71#ibcon#read 5, iclass 3, count 2 2006.176.08:13:31.71#ibcon#about to read 6, iclass 3, count 2 2006.176.08:13:31.71#ibcon#read 6, iclass 3, count 2 2006.176.08:13:31.71#ibcon#end of sib2, iclass 3, count 2 2006.176.08:13:31.71#ibcon#*mode == 0, iclass 3, count 2 2006.176.08:13:31.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.08:13:31.71#ibcon#[27=AT04-04\r\n] 2006.176.08:13:31.71#ibcon#*before write, iclass 3, count 2 2006.176.08:13:31.71#ibcon#enter sib2, iclass 3, count 2 2006.176.08:13:31.71#ibcon#flushed, iclass 3, count 2 2006.176.08:13:31.71#ibcon#about to write, iclass 3, count 2 2006.176.08:13:31.71#ibcon#wrote, iclass 3, count 2 2006.176.08:13:31.71#ibcon#about to read 3, iclass 3, count 2 2006.176.08:13:31.74#ibcon#read 3, iclass 3, count 2 2006.176.08:13:31.74#ibcon#about to read 4, iclass 3, count 2 2006.176.08:13:31.74#ibcon#read 4, iclass 3, count 2 2006.176.08:13:31.74#ibcon#about to read 5, iclass 3, count 2 2006.176.08:13:31.74#ibcon#read 5, iclass 3, count 2 2006.176.08:13:31.74#ibcon#about to read 6, iclass 3, count 2 2006.176.08:13:31.74#ibcon#read 6, iclass 3, count 2 2006.176.08:13:31.74#ibcon#end of sib2, iclass 3, count 2 2006.176.08:13:31.74#ibcon#*after write, iclass 3, count 2 2006.176.08:13:31.74#ibcon#*before return 0, iclass 3, count 2 2006.176.08:13:31.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:31.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:13:31.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.08:13:31.74#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:31.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:31.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:31.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:31.86#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:13:31.86#ibcon#first serial, iclass 3, count 0 2006.176.08:13:31.86#ibcon#enter sib2, iclass 3, count 0 2006.176.08:13:31.86#ibcon#flushed, iclass 3, count 0 2006.176.08:13:31.86#ibcon#about to write, iclass 3, count 0 2006.176.08:13:31.86#ibcon#wrote, iclass 3, count 0 2006.176.08:13:31.86#ibcon#about to read 3, iclass 3, count 0 2006.176.08:13:31.88#ibcon#read 3, iclass 3, count 0 2006.176.08:13:31.88#ibcon#about to read 4, iclass 3, count 0 2006.176.08:13:31.88#ibcon#read 4, iclass 3, count 0 2006.176.08:13:31.88#ibcon#about to read 5, iclass 3, count 0 2006.176.08:13:31.88#ibcon#read 5, iclass 3, count 0 2006.176.08:13:31.88#ibcon#about to read 6, iclass 3, count 0 2006.176.08:13:31.88#ibcon#read 6, iclass 3, count 0 2006.176.08:13:31.88#ibcon#end of sib2, iclass 3, count 0 2006.176.08:13:31.88#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:13:31.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:13:31.88#ibcon#[27=USB\r\n] 2006.176.08:13:31.88#ibcon#*before write, iclass 3, count 0 2006.176.08:13:31.88#ibcon#enter sib2, iclass 3, count 0 2006.176.08:13:31.88#ibcon#flushed, iclass 3, count 0 2006.176.08:13:31.88#ibcon#about to write, iclass 3, count 0 2006.176.08:13:31.88#ibcon#wrote, iclass 3, count 0 2006.176.08:13:31.88#ibcon#about to read 3, iclass 3, count 0 2006.176.08:13:31.92#ibcon#read 3, iclass 3, count 0 2006.176.08:13:31.92#ibcon#about to read 4, iclass 3, count 0 2006.176.08:13:31.92#ibcon#read 4, iclass 3, count 0 2006.176.08:13:31.92#ibcon#about to read 5, iclass 3, count 0 2006.176.08:13:31.92#ibcon#read 5, iclass 3, count 0 2006.176.08:13:31.92#ibcon#about to read 6, iclass 3, count 0 2006.176.08:13:31.92#ibcon#read 6, iclass 3, count 0 2006.176.08:13:31.92#ibcon#end of sib2, iclass 3, count 0 2006.176.08:13:31.92#ibcon#*after write, iclass 3, count 0 2006.176.08:13:31.92#ibcon#*before return 0, iclass 3, count 0 2006.176.08:13:31.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:31.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:13:31.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:13:31.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:13:31.92$vc4f8/vblo=5,744.99 2006.176.08:13:31.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.08:13:31.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.08:13:31.92#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:31.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:31.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:31.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:31.92#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:13:31.92#ibcon#first serial, iclass 5, count 0 2006.176.08:13:31.92#ibcon#enter sib2, iclass 5, count 0 2006.176.08:13:31.92#ibcon#flushed, iclass 5, count 0 2006.176.08:13:31.92#ibcon#about to write, iclass 5, count 0 2006.176.08:13:31.92#ibcon#wrote, iclass 5, count 0 2006.176.08:13:31.92#ibcon#about to read 3, iclass 5, count 0 2006.176.08:13:31.93#ibcon#read 3, iclass 5, count 0 2006.176.08:13:31.93#ibcon#about to read 4, iclass 5, count 0 2006.176.08:13:31.93#ibcon#read 4, iclass 5, count 0 2006.176.08:13:31.93#ibcon#about to read 5, iclass 5, count 0 2006.176.08:13:31.93#ibcon#read 5, iclass 5, count 0 2006.176.08:13:31.93#ibcon#about to read 6, iclass 5, count 0 2006.176.08:13:31.93#ibcon#read 6, iclass 5, count 0 2006.176.08:13:31.93#ibcon#end of sib2, iclass 5, count 0 2006.176.08:13:31.93#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:13:31.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:13:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:13:31.93#ibcon#*before write, iclass 5, count 0 2006.176.08:13:31.93#ibcon#enter sib2, iclass 5, count 0 2006.176.08:13:31.93#ibcon#flushed, iclass 5, count 0 2006.176.08:13:31.93#ibcon#about to write, iclass 5, count 0 2006.176.08:13:31.93#ibcon#wrote, iclass 5, count 0 2006.176.08:13:31.93#ibcon#about to read 3, iclass 5, count 0 2006.176.08:13:31.97#ibcon#read 3, iclass 5, count 0 2006.176.08:13:31.97#ibcon#about to read 4, iclass 5, count 0 2006.176.08:13:31.97#ibcon#read 4, iclass 5, count 0 2006.176.08:13:31.97#ibcon#about to read 5, iclass 5, count 0 2006.176.08:13:31.97#ibcon#read 5, iclass 5, count 0 2006.176.08:13:31.97#ibcon#about to read 6, iclass 5, count 0 2006.176.08:13:31.97#ibcon#read 6, iclass 5, count 0 2006.176.08:13:31.97#ibcon#end of sib2, iclass 5, count 0 2006.176.08:13:31.97#ibcon#*after write, iclass 5, count 0 2006.176.08:13:31.97#ibcon#*before return 0, iclass 5, count 0 2006.176.08:13:31.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:31.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:13:31.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:13:31.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:13:31.97$vc4f8/vb=5,4 2006.176.08:13:31.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.08:13:31.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.08:13:31.97#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:31.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:32.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:32.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:32.04#ibcon#enter wrdev, iclass 7, count 2 2006.176.08:13:32.04#ibcon#first serial, iclass 7, count 2 2006.176.08:13:32.04#ibcon#enter sib2, iclass 7, count 2 2006.176.08:13:32.04#ibcon#flushed, iclass 7, count 2 2006.176.08:13:32.04#ibcon#about to write, iclass 7, count 2 2006.176.08:13:32.04#ibcon#wrote, iclass 7, count 2 2006.176.08:13:32.04#ibcon#about to read 3, iclass 7, count 2 2006.176.08:13:32.06#ibcon#read 3, iclass 7, count 2 2006.176.08:13:32.06#ibcon#about to read 4, iclass 7, count 2 2006.176.08:13:32.06#ibcon#read 4, iclass 7, count 2 2006.176.08:13:32.06#ibcon#about to read 5, iclass 7, count 2 2006.176.08:13:32.06#ibcon#read 5, iclass 7, count 2 2006.176.08:13:32.06#ibcon#about to read 6, iclass 7, count 2 2006.176.08:13:32.06#ibcon#read 6, iclass 7, count 2 2006.176.08:13:32.06#ibcon#end of sib2, iclass 7, count 2 2006.176.08:13:32.06#ibcon#*mode == 0, iclass 7, count 2 2006.176.08:13:32.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.08:13:32.06#ibcon#[27=AT05-04\r\n] 2006.176.08:13:32.06#ibcon#*before write, iclass 7, count 2 2006.176.08:13:32.06#ibcon#enter sib2, iclass 7, count 2 2006.176.08:13:32.06#ibcon#flushed, iclass 7, count 2 2006.176.08:13:32.06#ibcon#about to write, iclass 7, count 2 2006.176.08:13:32.06#ibcon#wrote, iclass 7, count 2 2006.176.08:13:32.06#ibcon#about to read 3, iclass 7, count 2 2006.176.08:13:32.09#ibcon#read 3, iclass 7, count 2 2006.176.08:13:32.09#ibcon#about to read 4, iclass 7, count 2 2006.176.08:13:32.09#ibcon#read 4, iclass 7, count 2 2006.176.08:13:32.09#ibcon#about to read 5, iclass 7, count 2 2006.176.08:13:32.09#ibcon#read 5, iclass 7, count 2 2006.176.08:13:32.09#ibcon#about to read 6, iclass 7, count 2 2006.176.08:13:32.09#ibcon#read 6, iclass 7, count 2 2006.176.08:13:32.09#ibcon#end of sib2, iclass 7, count 2 2006.176.08:13:32.09#ibcon#*after write, iclass 7, count 2 2006.176.08:13:32.09#ibcon#*before return 0, iclass 7, count 2 2006.176.08:13:32.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:32.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:13:32.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.08:13:32.09#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:32.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:32.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:32.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:32.21#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:13:32.21#ibcon#first serial, iclass 7, count 0 2006.176.08:13:32.21#ibcon#enter sib2, iclass 7, count 0 2006.176.08:13:32.21#ibcon#flushed, iclass 7, count 0 2006.176.08:13:32.21#ibcon#about to write, iclass 7, count 0 2006.176.08:13:32.21#ibcon#wrote, iclass 7, count 0 2006.176.08:13:32.21#ibcon#about to read 3, iclass 7, count 0 2006.176.08:13:32.23#ibcon#read 3, iclass 7, count 0 2006.176.08:13:32.23#ibcon#about to read 4, iclass 7, count 0 2006.176.08:13:32.23#ibcon#read 4, iclass 7, count 0 2006.176.08:13:32.23#ibcon#about to read 5, iclass 7, count 0 2006.176.08:13:32.23#ibcon#read 5, iclass 7, count 0 2006.176.08:13:32.23#ibcon#about to read 6, iclass 7, count 0 2006.176.08:13:32.23#ibcon#read 6, iclass 7, count 0 2006.176.08:13:32.23#ibcon#end of sib2, iclass 7, count 0 2006.176.08:13:32.23#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:13:32.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:13:32.23#ibcon#[27=USB\r\n] 2006.176.08:13:32.23#ibcon#*before write, iclass 7, count 0 2006.176.08:13:32.23#ibcon#enter sib2, iclass 7, count 0 2006.176.08:13:32.23#ibcon#flushed, iclass 7, count 0 2006.176.08:13:32.23#ibcon#about to write, iclass 7, count 0 2006.176.08:13:32.23#ibcon#wrote, iclass 7, count 0 2006.176.08:13:32.23#ibcon#about to read 3, iclass 7, count 0 2006.176.08:13:32.26#ibcon#read 3, iclass 7, count 0 2006.176.08:13:32.26#ibcon#about to read 4, iclass 7, count 0 2006.176.08:13:32.26#ibcon#read 4, iclass 7, count 0 2006.176.08:13:32.26#ibcon#about to read 5, iclass 7, count 0 2006.176.08:13:32.26#ibcon#read 5, iclass 7, count 0 2006.176.08:13:32.26#ibcon#about to read 6, iclass 7, count 0 2006.176.08:13:32.26#ibcon#read 6, iclass 7, count 0 2006.176.08:13:32.26#ibcon#end of sib2, iclass 7, count 0 2006.176.08:13:32.26#ibcon#*after write, iclass 7, count 0 2006.176.08:13:32.26#ibcon#*before return 0, iclass 7, count 0 2006.176.08:13:32.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:32.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:13:32.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:13:32.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:13:32.26$vc4f8/vblo=6,752.99 2006.176.08:13:32.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.08:13:32.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.08:13:32.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:13:32.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:32.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:32.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:32.26#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:13:32.26#ibcon#first serial, iclass 11, count 0 2006.176.08:13:32.26#ibcon#enter sib2, iclass 11, count 0 2006.176.08:13:32.26#ibcon#flushed, iclass 11, count 0 2006.176.08:13:32.26#ibcon#about to write, iclass 11, count 0 2006.176.08:13:32.26#ibcon#wrote, iclass 11, count 0 2006.176.08:13:32.26#ibcon#about to read 3, iclass 11, count 0 2006.176.08:13:32.28#ibcon#read 3, iclass 11, count 0 2006.176.08:13:32.28#ibcon#about to read 4, iclass 11, count 0 2006.176.08:13:32.28#ibcon#read 4, iclass 11, count 0 2006.176.08:13:32.28#ibcon#about to read 5, iclass 11, count 0 2006.176.08:13:32.28#ibcon#read 5, iclass 11, count 0 2006.176.08:13:32.28#ibcon#about to read 6, iclass 11, count 0 2006.176.08:13:32.28#ibcon#read 6, iclass 11, count 0 2006.176.08:13:32.28#ibcon#end of sib2, iclass 11, count 0 2006.176.08:13:32.28#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:13:32.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:13:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:13:32.28#ibcon#*before write, iclass 11, count 0 2006.176.08:13:32.28#ibcon#enter sib2, iclass 11, count 0 2006.176.08:13:32.28#ibcon#flushed, iclass 11, count 0 2006.176.08:13:32.28#ibcon#about to write, iclass 11, count 0 2006.176.08:13:32.28#ibcon#wrote, iclass 11, count 0 2006.176.08:13:32.28#ibcon#about to read 3, iclass 11, count 0 2006.176.08:13:32.32#ibcon#read 3, iclass 11, count 0 2006.176.08:13:32.32#ibcon#about to read 4, iclass 11, count 0 2006.176.08:13:32.32#ibcon#read 4, iclass 11, count 0 2006.176.08:13:32.32#ibcon#about to read 5, iclass 11, count 0 2006.176.08:13:32.32#ibcon#read 5, iclass 11, count 0 2006.176.08:13:32.32#ibcon#about to read 6, iclass 11, count 0 2006.176.08:13:32.32#ibcon#read 6, iclass 11, count 0 2006.176.08:13:32.32#ibcon#end of sib2, iclass 11, count 0 2006.176.08:13:32.32#ibcon#*after write, iclass 11, count 0 2006.176.08:13:32.32#ibcon#*before return 0, iclass 11, count 0 2006.176.08:13:32.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:32.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:13:32.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:13:32.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:13:32.32$vc4f8/vb=6,4 2006.176.08:13:32.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.08:13:32.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.08:13:32.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:13:32.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:32.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:32.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:32.38#ibcon#enter wrdev, iclass 13, count 2 2006.176.08:13:32.38#ibcon#first serial, iclass 13, count 2 2006.176.08:13:32.38#ibcon#enter sib2, iclass 13, count 2 2006.176.08:13:32.38#ibcon#flushed, iclass 13, count 2 2006.176.08:13:32.38#ibcon#about to write, iclass 13, count 2 2006.176.08:13:32.38#ibcon#wrote, iclass 13, count 2 2006.176.08:13:32.38#ibcon#about to read 3, iclass 13, count 2 2006.176.08:13:32.40#ibcon#read 3, iclass 13, count 2 2006.176.08:13:32.40#ibcon#about to read 4, iclass 13, count 2 2006.176.08:13:32.40#ibcon#read 4, iclass 13, count 2 2006.176.08:13:32.40#ibcon#about to read 5, iclass 13, count 2 2006.176.08:13:32.40#ibcon#read 5, iclass 13, count 2 2006.176.08:13:32.40#ibcon#about to read 6, iclass 13, count 2 2006.176.08:13:32.40#ibcon#read 6, iclass 13, count 2 2006.176.08:13:32.40#ibcon#end of sib2, iclass 13, count 2 2006.176.08:13:32.40#ibcon#*mode == 0, iclass 13, count 2 2006.176.08:13:32.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.08:13:32.40#ibcon#[27=AT06-04\r\n] 2006.176.08:13:32.40#ibcon#*before write, iclass 13, count 2 2006.176.08:13:32.40#ibcon#enter sib2, iclass 13, count 2 2006.176.08:13:32.40#ibcon#flushed, iclass 13, count 2 2006.176.08:13:32.40#ibcon#about to write, iclass 13, count 2 2006.176.08:13:32.40#ibcon#wrote, iclass 13, count 2 2006.176.08:13:32.40#ibcon#about to read 3, iclass 13, count 2 2006.176.08:13:32.43#ibcon#read 3, iclass 13, count 2 2006.176.08:13:32.43#ibcon#about to read 4, iclass 13, count 2 2006.176.08:13:32.43#ibcon#read 4, iclass 13, count 2 2006.176.08:13:32.43#ibcon#about to read 5, iclass 13, count 2 2006.176.08:13:32.43#ibcon#read 5, iclass 13, count 2 2006.176.08:13:32.43#ibcon#about to read 6, iclass 13, count 2 2006.176.08:13:32.43#ibcon#read 6, iclass 13, count 2 2006.176.08:13:32.43#ibcon#end of sib2, iclass 13, count 2 2006.176.08:13:32.43#ibcon#*after write, iclass 13, count 2 2006.176.08:13:32.43#ibcon#*before return 0, iclass 13, count 2 2006.176.08:13:32.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:32.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:13:32.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.08:13:32.43#ibcon#ireg 7 cls_cnt 0 2006.176.08:13:32.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:32.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:32.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:32.55#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:13:32.55#ibcon#first serial, iclass 13, count 0 2006.176.08:13:32.55#ibcon#enter sib2, iclass 13, count 0 2006.176.08:13:32.55#ibcon#flushed, iclass 13, count 0 2006.176.08:13:32.55#ibcon#about to write, iclass 13, count 0 2006.176.08:13:32.55#ibcon#wrote, iclass 13, count 0 2006.176.08:13:32.55#ibcon#about to read 3, iclass 13, count 0 2006.176.08:13:32.57#ibcon#read 3, iclass 13, count 0 2006.176.08:13:32.57#ibcon#about to read 4, iclass 13, count 0 2006.176.08:13:32.57#ibcon#read 4, iclass 13, count 0 2006.176.08:13:32.57#ibcon#about to read 5, iclass 13, count 0 2006.176.08:13:32.57#ibcon#read 5, iclass 13, count 0 2006.176.08:13:32.57#ibcon#about to read 6, iclass 13, count 0 2006.176.08:13:32.57#ibcon#read 6, iclass 13, count 0 2006.176.08:13:32.57#ibcon#end of sib2, iclass 13, count 0 2006.176.08:13:32.57#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:13:32.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:13:32.57#ibcon#[27=USB\r\n] 2006.176.08:13:32.57#ibcon#*before write, iclass 13, count 0 2006.176.08:13:32.57#ibcon#enter sib2, iclass 13, count 0 2006.176.08:13:32.57#ibcon#flushed, iclass 13, count 0 2006.176.08:13:32.57#ibcon#about to write, iclass 13, count 0 2006.176.08:13:32.57#ibcon#wrote, iclass 13, count 0 2006.176.08:13:32.57#ibcon#about to read 3, iclass 13, count 0 2006.176.08:13:32.61#ibcon#read 3, iclass 13, count 0 2006.176.08:13:32.61#ibcon#about to read 4, iclass 13, count 0 2006.176.08:13:32.61#ibcon#read 4, iclass 13, count 0 2006.176.08:13:32.61#ibcon#about to read 5, iclass 13, count 0 2006.176.08:13:32.61#ibcon#read 5, iclass 13, count 0 2006.176.08:13:32.61#ibcon#about to read 6, iclass 13, count 0 2006.176.08:13:32.61#ibcon#read 6, iclass 13, count 0 2006.176.08:13:32.61#ibcon#end of sib2, iclass 13, count 0 2006.176.08:13:32.61#ibcon#*after write, iclass 13, count 0 2006.176.08:13:32.61#ibcon#*before return 0, iclass 13, count 0 2006.176.08:13:32.61#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:32.61#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:13:32.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:13:32.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:13:32.61$vc4f8/vabw=wide 2006.176.08:13:32.61#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.08:13:32.61#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.08:13:32.61#ibcon#ireg 8 cls_cnt 0 2006.176.08:13:32.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:32.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:32.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:32.61#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:13:32.61#ibcon#first serial, iclass 15, count 0 2006.176.08:13:32.61#ibcon#enter sib2, iclass 15, count 0 2006.176.08:13:32.61#ibcon#flushed, iclass 15, count 0 2006.176.08:13:32.61#ibcon#about to write, iclass 15, count 0 2006.176.08:13:32.61#ibcon#wrote, iclass 15, count 0 2006.176.08:13:32.61#ibcon#about to read 3, iclass 15, count 0 2006.176.08:13:32.62#ibcon#read 3, iclass 15, count 0 2006.176.08:13:32.62#ibcon#about to read 4, iclass 15, count 0 2006.176.08:13:32.62#ibcon#read 4, iclass 15, count 0 2006.176.08:13:32.62#ibcon#about to read 5, iclass 15, count 0 2006.176.08:13:32.62#ibcon#read 5, iclass 15, count 0 2006.176.08:13:32.62#ibcon#about to read 6, iclass 15, count 0 2006.176.08:13:32.62#ibcon#read 6, iclass 15, count 0 2006.176.08:13:32.62#ibcon#end of sib2, iclass 15, count 0 2006.176.08:13:32.62#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:13:32.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:13:32.62#ibcon#[25=BW32\r\n] 2006.176.08:13:32.62#ibcon#*before write, iclass 15, count 0 2006.176.08:13:32.62#ibcon#enter sib2, iclass 15, count 0 2006.176.08:13:32.62#ibcon#flushed, iclass 15, count 0 2006.176.08:13:32.62#ibcon#about to write, iclass 15, count 0 2006.176.08:13:32.62#ibcon#wrote, iclass 15, count 0 2006.176.08:13:32.62#ibcon#about to read 3, iclass 15, count 0 2006.176.08:13:32.65#ibcon#read 3, iclass 15, count 0 2006.176.08:13:32.65#ibcon#about to read 4, iclass 15, count 0 2006.176.08:13:32.65#ibcon#read 4, iclass 15, count 0 2006.176.08:13:32.65#ibcon#about to read 5, iclass 15, count 0 2006.176.08:13:32.65#ibcon#read 5, iclass 15, count 0 2006.176.08:13:32.65#ibcon#about to read 6, iclass 15, count 0 2006.176.08:13:32.65#ibcon#read 6, iclass 15, count 0 2006.176.08:13:32.65#ibcon#end of sib2, iclass 15, count 0 2006.176.08:13:32.65#ibcon#*after write, iclass 15, count 0 2006.176.08:13:32.65#ibcon#*before return 0, iclass 15, count 0 2006.176.08:13:32.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:32.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:13:32.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:13:32.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:13:32.65$vc4f8/vbbw=wide 2006.176.08:13:32.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.08:13:32.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.08:13:32.65#ibcon#ireg 8 cls_cnt 0 2006.176.08:13:32.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:13:32.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:13:32.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:13:32.73#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:13:32.73#ibcon#first serial, iclass 17, count 0 2006.176.08:13:32.73#ibcon#enter sib2, iclass 17, count 0 2006.176.08:13:32.73#ibcon#flushed, iclass 17, count 0 2006.176.08:13:32.73#ibcon#about to write, iclass 17, count 0 2006.176.08:13:32.73#ibcon#wrote, iclass 17, count 0 2006.176.08:13:32.73#ibcon#about to read 3, iclass 17, count 0 2006.176.08:13:32.75#ibcon#read 3, iclass 17, count 0 2006.176.08:13:32.75#ibcon#about to read 4, iclass 17, count 0 2006.176.08:13:32.75#ibcon#read 4, iclass 17, count 0 2006.176.08:13:32.75#ibcon#about to read 5, iclass 17, count 0 2006.176.08:13:32.75#ibcon#read 5, iclass 17, count 0 2006.176.08:13:32.75#ibcon#about to read 6, iclass 17, count 0 2006.176.08:13:32.75#ibcon#read 6, iclass 17, count 0 2006.176.08:13:32.75#ibcon#end of sib2, iclass 17, count 0 2006.176.08:13:32.75#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:13:32.75#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:13:32.75#ibcon#[27=BW32\r\n] 2006.176.08:13:32.75#ibcon#*before write, iclass 17, count 0 2006.176.08:13:32.75#ibcon#enter sib2, iclass 17, count 0 2006.176.08:13:32.75#ibcon#flushed, iclass 17, count 0 2006.176.08:13:32.75#ibcon#about to write, iclass 17, count 0 2006.176.08:13:32.75#ibcon#wrote, iclass 17, count 0 2006.176.08:13:32.75#ibcon#about to read 3, iclass 17, count 0 2006.176.08:13:32.78#ibcon#read 3, iclass 17, count 0 2006.176.08:13:32.78#ibcon#about to read 4, iclass 17, count 0 2006.176.08:13:32.78#ibcon#read 4, iclass 17, count 0 2006.176.08:13:32.78#ibcon#about to read 5, iclass 17, count 0 2006.176.08:13:32.78#ibcon#read 5, iclass 17, count 0 2006.176.08:13:32.78#ibcon#about to read 6, iclass 17, count 0 2006.176.08:13:32.78#ibcon#read 6, iclass 17, count 0 2006.176.08:13:32.78#ibcon#end of sib2, iclass 17, count 0 2006.176.08:13:32.78#ibcon#*after write, iclass 17, count 0 2006.176.08:13:32.78#ibcon#*before return 0, iclass 17, count 0 2006.176.08:13:32.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:13:32.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:13:32.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:13:32.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:13:32.78$4f8m12a/ifd4f 2006.176.08:13:32.78$ifd4f/lo= 2006.176.08:13:32.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:13:32.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:13:32.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:13:32.78$ifd4f/patch= 2006.176.08:13:32.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:13:32.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:13:32.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:13:32.78$4f8m12a/"form=m,16.000,1:2 2006.176.08:13:32.78$4f8m12a/"tpicd 2006.176.08:13:32.78$4f8m12a/echo=off 2006.176.08:13:32.78$4f8m12a/xlog=off 2006.176.08:13:32.78:!2006.176.08:14:00 2006.176.08:13:41.14#trakl#Source acquired 2006.176.08:13:42.14#flagr#flagr/antenna,acquired 2006.176.08:14:00.00:preob 2006.176.08:14:01.14/onsource/TRACKING 2006.176.08:14:01.14:!2006.176.08:14:10 2006.176.08:14:10.00:data_valid=on 2006.176.08:14:10.00:midob 2006.176.08:14:10.13/onsource/TRACKING 2006.176.08:14:10.13/wx/23.82,1008.6,92 2006.176.08:14:10.34/cable/+6.4938E-03 2006.176.08:14:11.43/va/01,08,usb,yes,29,31 2006.176.08:14:11.43/va/02,07,usb,yes,30,31 2006.176.08:14:11.43/va/03,06,usb,yes,31,32 2006.176.08:14:11.43/va/04,07,usb,yes,30,33 2006.176.08:14:11.43/va/05,07,usb,yes,32,34 2006.176.08:14:11.43/va/06,06,usb,yes,31,31 2006.176.08:14:11.43/va/07,06,usb,yes,32,32 2006.176.08:14:11.43/va/08,06,usb,yes,34,34 2006.176.08:14:11.66/valo/01,532.99,yes,locked 2006.176.08:14:11.66/valo/02,572.99,yes,locked 2006.176.08:14:11.66/valo/03,672.99,yes,locked 2006.176.08:14:11.66/valo/04,832.99,yes,locked 2006.176.08:14:11.66/valo/05,652.99,yes,locked 2006.176.08:14:11.66/valo/06,772.99,yes,locked 2006.176.08:14:11.66/valo/07,832.99,yes,locked 2006.176.08:14:11.66/valo/08,852.99,yes,locked 2006.176.08:14:12.75/vb/01,04,usb,yes,30,28 2006.176.08:14:12.75/vb/02,04,usb,yes,31,33 2006.176.08:14:12.75/vb/03,04,usb,yes,28,31 2006.176.08:14:12.75/vb/04,04,usb,yes,29,29 2006.176.08:14:12.75/vb/05,04,usb,yes,27,31 2006.176.08:14:12.75/vb/06,04,usb,yes,28,31 2006.176.08:14:12.75/vb/07,04,usb,yes,30,30 2006.176.08:14:12.75/vb/08,04,usb,yes,28,31 2006.176.08:14:12.98/vblo/01,632.99,yes,locked 2006.176.08:14:12.98/vblo/02,640.99,yes,locked 2006.176.08:14:12.98/vblo/03,656.99,yes,locked 2006.176.08:14:12.98/vblo/04,712.99,yes,locked 2006.176.08:14:12.98/vblo/05,744.99,yes,locked 2006.176.08:14:12.98/vblo/06,752.99,yes,locked 2006.176.08:14:12.98/vblo/07,734.99,yes,locked 2006.176.08:14:12.98/vblo/08,744.99,yes,locked 2006.176.08:14:13.13/vabw/8 2006.176.08:14:13.28/vbbw/8 2006.176.08:14:13.37/xfe/off,on,14.7 2006.176.08:14:13.76/ifatt/23,28,28,28 2006.176.08:14:14.07/fmout-gps/S +3.70E-07 2006.176.08:14:14.11:!2006.176.08:15:10 2006.176.08:15:10.00:data_valid=off 2006.176.08:15:10.00:postob 2006.176.08:15:10.18/cable/+6.4928E-03 2006.176.08:15:10.18/wx/23.82,1008.6,92 2006.176.08:15:11.07/fmout-gps/S +3.70E-07 2006.176.08:15:11.07:scan_name=176-0816,k06176,60 2006.176.08:15:11.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.176.08:15:12.13#flagr#flagr/antenna,new-source 2006.176.08:15:12.13:checkk5 2006.176.08:15:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:15:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:15:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:15:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:15:14.00/chk_obsdata//k5ts1/T1760814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:15:14.37/chk_obsdata//k5ts2/T1760814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:15:14.74/chk_obsdata//k5ts3/T1760814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:15:15.11/chk_obsdata//k5ts4/T1760814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:15:15.81/k5log//k5ts1_log_newline 2006.176.08:15:16.50/k5log//k5ts2_log_newline 2006.176.08:15:17.19/k5log//k5ts3_log_newline 2006.176.08:15:17.88/k5log//k5ts4_log_newline 2006.176.08:15:17.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:15:17.91:4f8m12a=2 2006.176.08:15:17.91$4f8m12a/echo=on 2006.176.08:15:17.91$4f8m12a/pcalon 2006.176.08:15:17.91$pcalon/"no phase cal control is implemented here 2006.176.08:15:17.91$4f8m12a/"tpicd=stop 2006.176.08:15:17.91$4f8m12a/vc4f8 2006.176.08:15:17.91$vc4f8/valo=1,532.99 2006.176.08:15:17.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.08:15:17.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.08:15:17.91#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:17.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:17.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:17.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:17.91#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:15:17.91#ibcon#first serial, iclass 24, count 0 2006.176.08:15:17.91#ibcon#enter sib2, iclass 24, count 0 2006.176.08:15:17.91#ibcon#flushed, iclass 24, count 0 2006.176.08:15:17.91#ibcon#about to write, iclass 24, count 0 2006.176.08:15:17.91#ibcon#wrote, iclass 24, count 0 2006.176.08:15:17.91#ibcon#about to read 3, iclass 24, count 0 2006.176.08:15:17.95#ibcon#read 3, iclass 24, count 0 2006.176.08:15:17.95#ibcon#about to read 4, iclass 24, count 0 2006.176.08:15:17.95#ibcon#read 4, iclass 24, count 0 2006.176.08:15:17.95#ibcon#about to read 5, iclass 24, count 0 2006.176.08:15:17.95#ibcon#read 5, iclass 24, count 0 2006.176.08:15:17.95#ibcon#about to read 6, iclass 24, count 0 2006.176.08:15:17.95#ibcon#read 6, iclass 24, count 0 2006.176.08:15:17.95#ibcon#end of sib2, iclass 24, count 0 2006.176.08:15:17.95#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:15:17.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:15:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:15:17.95#ibcon#*before write, iclass 24, count 0 2006.176.08:15:17.95#ibcon#enter sib2, iclass 24, count 0 2006.176.08:15:17.95#ibcon#flushed, iclass 24, count 0 2006.176.08:15:17.95#ibcon#about to write, iclass 24, count 0 2006.176.08:15:17.95#ibcon#wrote, iclass 24, count 0 2006.176.08:15:17.95#ibcon#about to read 3, iclass 24, count 0 2006.176.08:15:18.00#ibcon#read 3, iclass 24, count 0 2006.176.08:15:18.00#ibcon#about to read 4, iclass 24, count 0 2006.176.08:15:18.00#ibcon#read 4, iclass 24, count 0 2006.176.08:15:18.00#ibcon#about to read 5, iclass 24, count 0 2006.176.08:15:18.00#ibcon#read 5, iclass 24, count 0 2006.176.08:15:18.00#ibcon#about to read 6, iclass 24, count 0 2006.176.08:15:18.00#ibcon#read 6, iclass 24, count 0 2006.176.08:15:18.00#ibcon#end of sib2, iclass 24, count 0 2006.176.08:15:18.00#ibcon#*after write, iclass 24, count 0 2006.176.08:15:18.00#ibcon#*before return 0, iclass 24, count 0 2006.176.08:15:18.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:18.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:18.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:15:18.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:15:18.00$vc4f8/va=1,8 2006.176.08:15:18.00#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.08:15:18.00#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.08:15:18.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:18.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:18.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:18.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:18.00#ibcon#enter wrdev, iclass 26, count 2 2006.176.08:15:18.00#ibcon#first serial, iclass 26, count 2 2006.176.08:15:18.00#ibcon#enter sib2, iclass 26, count 2 2006.176.08:15:18.00#ibcon#flushed, iclass 26, count 2 2006.176.08:15:18.00#ibcon#about to write, iclass 26, count 2 2006.176.08:15:18.00#ibcon#wrote, iclass 26, count 2 2006.176.08:15:18.00#ibcon#about to read 3, iclass 26, count 2 2006.176.08:15:18.02#ibcon#read 3, iclass 26, count 2 2006.176.08:15:18.02#ibcon#about to read 4, iclass 26, count 2 2006.176.08:15:18.02#ibcon#read 4, iclass 26, count 2 2006.176.08:15:18.02#ibcon#about to read 5, iclass 26, count 2 2006.176.08:15:18.02#ibcon#read 5, iclass 26, count 2 2006.176.08:15:18.02#ibcon#about to read 6, iclass 26, count 2 2006.176.08:15:18.02#ibcon#read 6, iclass 26, count 2 2006.176.08:15:18.02#ibcon#end of sib2, iclass 26, count 2 2006.176.08:15:18.02#ibcon#*mode == 0, iclass 26, count 2 2006.176.08:15:18.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.08:15:18.02#ibcon#[25=AT01-08\r\n] 2006.176.08:15:18.02#ibcon#*before write, iclass 26, count 2 2006.176.08:15:18.02#ibcon#enter sib2, iclass 26, count 2 2006.176.08:15:18.02#ibcon#flushed, iclass 26, count 2 2006.176.08:15:18.02#ibcon#about to write, iclass 26, count 2 2006.176.08:15:18.02#ibcon#wrote, iclass 26, count 2 2006.176.08:15:18.02#ibcon#about to read 3, iclass 26, count 2 2006.176.08:15:18.05#ibcon#read 3, iclass 26, count 2 2006.176.08:15:18.05#ibcon#about to read 4, iclass 26, count 2 2006.176.08:15:18.05#ibcon#read 4, iclass 26, count 2 2006.176.08:15:18.05#ibcon#about to read 5, iclass 26, count 2 2006.176.08:15:18.05#ibcon#read 5, iclass 26, count 2 2006.176.08:15:18.05#ibcon#about to read 6, iclass 26, count 2 2006.176.08:15:18.05#ibcon#read 6, iclass 26, count 2 2006.176.08:15:18.05#ibcon#end of sib2, iclass 26, count 2 2006.176.08:15:18.05#ibcon#*after write, iclass 26, count 2 2006.176.08:15:18.05#ibcon#*before return 0, iclass 26, count 2 2006.176.08:15:18.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:18.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:18.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.08:15:18.05#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:18.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:18.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:18.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:18.17#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:15:18.17#ibcon#first serial, iclass 26, count 0 2006.176.08:15:18.17#ibcon#enter sib2, iclass 26, count 0 2006.176.08:15:18.17#ibcon#flushed, iclass 26, count 0 2006.176.08:15:18.17#ibcon#about to write, iclass 26, count 0 2006.176.08:15:18.17#ibcon#wrote, iclass 26, count 0 2006.176.08:15:18.17#ibcon#about to read 3, iclass 26, count 0 2006.176.08:15:18.19#ibcon#read 3, iclass 26, count 0 2006.176.08:15:18.19#ibcon#about to read 4, iclass 26, count 0 2006.176.08:15:18.19#ibcon#read 4, iclass 26, count 0 2006.176.08:15:18.19#ibcon#about to read 5, iclass 26, count 0 2006.176.08:15:18.19#ibcon#read 5, iclass 26, count 0 2006.176.08:15:18.19#ibcon#about to read 6, iclass 26, count 0 2006.176.08:15:18.19#ibcon#read 6, iclass 26, count 0 2006.176.08:15:18.19#ibcon#end of sib2, iclass 26, count 0 2006.176.08:15:18.19#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:15:18.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:15:18.19#ibcon#[25=USB\r\n] 2006.176.08:15:18.19#ibcon#*before write, iclass 26, count 0 2006.176.08:15:18.19#ibcon#enter sib2, iclass 26, count 0 2006.176.08:15:18.19#ibcon#flushed, iclass 26, count 0 2006.176.08:15:18.19#ibcon#about to write, iclass 26, count 0 2006.176.08:15:18.19#ibcon#wrote, iclass 26, count 0 2006.176.08:15:18.19#ibcon#about to read 3, iclass 26, count 0 2006.176.08:15:18.22#ibcon#read 3, iclass 26, count 0 2006.176.08:15:18.22#ibcon#about to read 4, iclass 26, count 0 2006.176.08:15:18.22#ibcon#read 4, iclass 26, count 0 2006.176.08:15:18.22#ibcon#about to read 5, iclass 26, count 0 2006.176.08:15:18.22#ibcon#read 5, iclass 26, count 0 2006.176.08:15:18.22#ibcon#about to read 6, iclass 26, count 0 2006.176.08:15:18.22#ibcon#read 6, iclass 26, count 0 2006.176.08:15:18.22#ibcon#end of sib2, iclass 26, count 0 2006.176.08:15:18.22#ibcon#*after write, iclass 26, count 0 2006.176.08:15:18.22#ibcon#*before return 0, iclass 26, count 0 2006.176.08:15:18.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:18.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:18.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:15:18.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:15:18.22$vc4f8/valo=2,572.99 2006.176.08:15:18.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.08:15:18.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.08:15:18.22#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:18.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:18.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:18.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:18.22#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:15:18.22#ibcon#first serial, iclass 28, count 0 2006.176.08:15:18.22#ibcon#enter sib2, iclass 28, count 0 2006.176.08:15:18.22#ibcon#flushed, iclass 28, count 0 2006.176.08:15:18.22#ibcon#about to write, iclass 28, count 0 2006.176.08:15:18.22#ibcon#wrote, iclass 28, count 0 2006.176.08:15:18.22#ibcon#about to read 3, iclass 28, count 0 2006.176.08:15:18.24#ibcon#read 3, iclass 28, count 0 2006.176.08:15:18.24#ibcon#about to read 4, iclass 28, count 0 2006.176.08:15:18.24#ibcon#read 4, iclass 28, count 0 2006.176.08:15:18.24#ibcon#about to read 5, iclass 28, count 0 2006.176.08:15:18.24#ibcon#read 5, iclass 28, count 0 2006.176.08:15:18.24#ibcon#about to read 6, iclass 28, count 0 2006.176.08:15:18.24#ibcon#read 6, iclass 28, count 0 2006.176.08:15:18.24#ibcon#end of sib2, iclass 28, count 0 2006.176.08:15:18.24#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:15:18.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:15:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:15:18.24#ibcon#*before write, iclass 28, count 0 2006.176.08:15:18.24#ibcon#enter sib2, iclass 28, count 0 2006.176.08:15:18.24#ibcon#flushed, iclass 28, count 0 2006.176.08:15:18.24#ibcon#about to write, iclass 28, count 0 2006.176.08:15:18.24#ibcon#wrote, iclass 28, count 0 2006.176.08:15:18.24#ibcon#about to read 3, iclass 28, count 0 2006.176.08:15:18.28#ibcon#read 3, iclass 28, count 0 2006.176.08:15:18.28#ibcon#about to read 4, iclass 28, count 0 2006.176.08:15:18.28#ibcon#read 4, iclass 28, count 0 2006.176.08:15:18.28#ibcon#about to read 5, iclass 28, count 0 2006.176.08:15:18.28#ibcon#read 5, iclass 28, count 0 2006.176.08:15:18.28#ibcon#about to read 6, iclass 28, count 0 2006.176.08:15:18.28#ibcon#read 6, iclass 28, count 0 2006.176.08:15:18.28#ibcon#end of sib2, iclass 28, count 0 2006.176.08:15:18.28#ibcon#*after write, iclass 28, count 0 2006.176.08:15:18.28#ibcon#*before return 0, iclass 28, count 0 2006.176.08:15:18.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:18.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:18.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:15:18.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:15:18.28$vc4f8/va=2,7 2006.176.08:15:18.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.08:15:18.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.08:15:18.28#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:18.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:15:18.29#abcon#<5=/06 3.4 6.3 23.82 921008.6\r\n> 2006.176.08:15:18.31#abcon#{5=INTERFACE CLEAR} 2006.176.08:15:18.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:15:18.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:15:18.34#ibcon#enter wrdev, iclass 31, count 2 2006.176.08:15:18.34#ibcon#first serial, iclass 31, count 2 2006.176.08:15:18.34#ibcon#enter sib2, iclass 31, count 2 2006.176.08:15:18.34#ibcon#flushed, iclass 31, count 2 2006.176.08:15:18.34#ibcon#about to write, iclass 31, count 2 2006.176.08:15:18.34#ibcon#wrote, iclass 31, count 2 2006.176.08:15:18.34#ibcon#about to read 3, iclass 31, count 2 2006.176.08:15:18.36#ibcon#read 3, iclass 31, count 2 2006.176.08:15:18.36#ibcon#about to read 4, iclass 31, count 2 2006.176.08:15:18.36#ibcon#read 4, iclass 31, count 2 2006.176.08:15:18.36#ibcon#about to read 5, iclass 31, count 2 2006.176.08:15:18.36#ibcon#read 5, iclass 31, count 2 2006.176.08:15:18.36#ibcon#about to read 6, iclass 31, count 2 2006.176.08:15:18.36#ibcon#read 6, iclass 31, count 2 2006.176.08:15:18.36#ibcon#end of sib2, iclass 31, count 2 2006.176.08:15:18.36#ibcon#*mode == 0, iclass 31, count 2 2006.176.08:15:18.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.08:15:18.36#ibcon#[25=AT02-07\r\n] 2006.176.08:15:18.36#ibcon#*before write, iclass 31, count 2 2006.176.08:15:18.36#ibcon#enter sib2, iclass 31, count 2 2006.176.08:15:18.36#ibcon#flushed, iclass 31, count 2 2006.176.08:15:18.36#ibcon#about to write, iclass 31, count 2 2006.176.08:15:18.36#ibcon#wrote, iclass 31, count 2 2006.176.08:15:18.36#ibcon#about to read 3, iclass 31, count 2 2006.176.08:15:18.37#abcon#[5=S1D000X0/0*\r\n] 2006.176.08:15:18.39#ibcon#read 3, iclass 31, count 2 2006.176.08:15:18.39#ibcon#about to read 4, iclass 31, count 2 2006.176.08:15:18.39#ibcon#read 4, iclass 31, count 2 2006.176.08:15:18.39#ibcon#about to read 5, iclass 31, count 2 2006.176.08:15:18.39#ibcon#read 5, iclass 31, count 2 2006.176.08:15:18.39#ibcon#about to read 6, iclass 31, count 2 2006.176.08:15:18.39#ibcon#read 6, iclass 31, count 2 2006.176.08:15:18.39#ibcon#end of sib2, iclass 31, count 2 2006.176.08:15:18.39#ibcon#*after write, iclass 31, count 2 2006.176.08:15:18.39#ibcon#*before return 0, iclass 31, count 2 2006.176.08:15:18.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:15:18.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:15:18.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.08:15:18.39#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:18.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:15:18.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:15:18.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:15:18.51#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:15:18.51#ibcon#first serial, iclass 31, count 0 2006.176.08:15:18.51#ibcon#enter sib2, iclass 31, count 0 2006.176.08:15:18.51#ibcon#flushed, iclass 31, count 0 2006.176.08:15:18.51#ibcon#about to write, iclass 31, count 0 2006.176.08:15:18.51#ibcon#wrote, iclass 31, count 0 2006.176.08:15:18.51#ibcon#about to read 3, iclass 31, count 0 2006.176.08:15:18.53#ibcon#read 3, iclass 31, count 0 2006.176.08:15:18.53#ibcon#about to read 4, iclass 31, count 0 2006.176.08:15:18.53#ibcon#read 4, iclass 31, count 0 2006.176.08:15:18.53#ibcon#about to read 5, iclass 31, count 0 2006.176.08:15:18.53#ibcon#read 5, iclass 31, count 0 2006.176.08:15:18.53#ibcon#about to read 6, iclass 31, count 0 2006.176.08:15:18.53#ibcon#read 6, iclass 31, count 0 2006.176.08:15:18.53#ibcon#end of sib2, iclass 31, count 0 2006.176.08:15:18.53#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:15:18.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:15:18.53#ibcon#[25=USB\r\n] 2006.176.08:15:18.53#ibcon#*before write, iclass 31, count 0 2006.176.08:15:18.53#ibcon#enter sib2, iclass 31, count 0 2006.176.08:15:18.53#ibcon#flushed, iclass 31, count 0 2006.176.08:15:18.53#ibcon#about to write, iclass 31, count 0 2006.176.08:15:18.53#ibcon#wrote, iclass 31, count 0 2006.176.08:15:18.53#ibcon#about to read 3, iclass 31, count 0 2006.176.08:15:18.56#ibcon#read 3, iclass 31, count 0 2006.176.08:15:18.56#ibcon#about to read 4, iclass 31, count 0 2006.176.08:15:18.56#ibcon#read 4, iclass 31, count 0 2006.176.08:15:18.56#ibcon#about to read 5, iclass 31, count 0 2006.176.08:15:18.56#ibcon#read 5, iclass 31, count 0 2006.176.08:15:18.56#ibcon#about to read 6, iclass 31, count 0 2006.176.08:15:18.56#ibcon#read 6, iclass 31, count 0 2006.176.08:15:18.56#ibcon#end of sib2, iclass 31, count 0 2006.176.08:15:18.56#ibcon#*after write, iclass 31, count 0 2006.176.08:15:18.56#ibcon#*before return 0, iclass 31, count 0 2006.176.08:15:18.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:15:18.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:15:18.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:15:18.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:15:18.56$vc4f8/valo=3,672.99 2006.176.08:15:18.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.08:15:18.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.08:15:18.56#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:18.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:18.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:18.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:18.56#ibcon#enter wrdev, iclass 36, count 0 2006.176.08:15:18.56#ibcon#first serial, iclass 36, count 0 2006.176.08:15:18.56#ibcon#enter sib2, iclass 36, count 0 2006.176.08:15:18.56#ibcon#flushed, iclass 36, count 0 2006.176.08:15:18.56#ibcon#about to write, iclass 36, count 0 2006.176.08:15:18.56#ibcon#wrote, iclass 36, count 0 2006.176.08:15:18.56#ibcon#about to read 3, iclass 36, count 0 2006.176.08:15:18.58#ibcon#read 3, iclass 36, count 0 2006.176.08:15:18.58#ibcon#about to read 4, iclass 36, count 0 2006.176.08:15:18.58#ibcon#read 4, iclass 36, count 0 2006.176.08:15:18.58#ibcon#about to read 5, iclass 36, count 0 2006.176.08:15:18.58#ibcon#read 5, iclass 36, count 0 2006.176.08:15:18.58#ibcon#about to read 6, iclass 36, count 0 2006.176.08:15:18.58#ibcon#read 6, iclass 36, count 0 2006.176.08:15:18.58#ibcon#end of sib2, iclass 36, count 0 2006.176.08:15:18.58#ibcon#*mode == 0, iclass 36, count 0 2006.176.08:15:18.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.08:15:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:15:18.58#ibcon#*before write, iclass 36, count 0 2006.176.08:15:18.58#ibcon#enter sib2, iclass 36, count 0 2006.176.08:15:18.58#ibcon#flushed, iclass 36, count 0 2006.176.08:15:18.58#ibcon#about to write, iclass 36, count 0 2006.176.08:15:18.58#ibcon#wrote, iclass 36, count 0 2006.176.08:15:18.58#ibcon#about to read 3, iclass 36, count 0 2006.176.08:15:18.62#ibcon#read 3, iclass 36, count 0 2006.176.08:15:18.62#ibcon#about to read 4, iclass 36, count 0 2006.176.08:15:18.62#ibcon#read 4, iclass 36, count 0 2006.176.08:15:18.62#ibcon#about to read 5, iclass 36, count 0 2006.176.08:15:18.62#ibcon#read 5, iclass 36, count 0 2006.176.08:15:18.62#ibcon#about to read 6, iclass 36, count 0 2006.176.08:15:18.62#ibcon#read 6, iclass 36, count 0 2006.176.08:15:18.62#ibcon#end of sib2, iclass 36, count 0 2006.176.08:15:18.62#ibcon#*after write, iclass 36, count 0 2006.176.08:15:18.62#ibcon#*before return 0, iclass 36, count 0 2006.176.08:15:18.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:18.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:18.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.08:15:18.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.08:15:18.62$vc4f8/va=3,6 2006.176.08:15:18.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.08:15:18.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.08:15:18.62#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:18.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:18.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:18.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:18.68#ibcon#enter wrdev, iclass 38, count 2 2006.176.08:15:18.68#ibcon#first serial, iclass 38, count 2 2006.176.08:15:18.68#ibcon#enter sib2, iclass 38, count 2 2006.176.08:15:18.68#ibcon#flushed, iclass 38, count 2 2006.176.08:15:18.68#ibcon#about to write, iclass 38, count 2 2006.176.08:15:18.68#ibcon#wrote, iclass 38, count 2 2006.176.08:15:18.68#ibcon#about to read 3, iclass 38, count 2 2006.176.08:15:18.70#ibcon#read 3, iclass 38, count 2 2006.176.08:15:18.70#ibcon#about to read 4, iclass 38, count 2 2006.176.08:15:18.70#ibcon#read 4, iclass 38, count 2 2006.176.08:15:18.70#ibcon#about to read 5, iclass 38, count 2 2006.176.08:15:18.70#ibcon#read 5, iclass 38, count 2 2006.176.08:15:18.70#ibcon#about to read 6, iclass 38, count 2 2006.176.08:15:18.70#ibcon#read 6, iclass 38, count 2 2006.176.08:15:18.70#ibcon#end of sib2, iclass 38, count 2 2006.176.08:15:18.70#ibcon#*mode == 0, iclass 38, count 2 2006.176.08:15:18.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.08:15:18.70#ibcon#[25=AT03-06\r\n] 2006.176.08:15:18.70#ibcon#*before write, iclass 38, count 2 2006.176.08:15:18.70#ibcon#enter sib2, iclass 38, count 2 2006.176.08:15:18.70#ibcon#flushed, iclass 38, count 2 2006.176.08:15:18.70#ibcon#about to write, iclass 38, count 2 2006.176.08:15:18.70#ibcon#wrote, iclass 38, count 2 2006.176.08:15:18.70#ibcon#about to read 3, iclass 38, count 2 2006.176.08:15:18.73#ibcon#read 3, iclass 38, count 2 2006.176.08:15:18.73#ibcon#about to read 4, iclass 38, count 2 2006.176.08:15:18.73#ibcon#read 4, iclass 38, count 2 2006.176.08:15:18.73#ibcon#about to read 5, iclass 38, count 2 2006.176.08:15:18.73#ibcon#read 5, iclass 38, count 2 2006.176.08:15:18.73#ibcon#about to read 6, iclass 38, count 2 2006.176.08:15:18.73#ibcon#read 6, iclass 38, count 2 2006.176.08:15:18.73#ibcon#end of sib2, iclass 38, count 2 2006.176.08:15:18.73#ibcon#*after write, iclass 38, count 2 2006.176.08:15:18.73#ibcon#*before return 0, iclass 38, count 2 2006.176.08:15:18.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:18.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:18.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.08:15:18.73#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:18.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:18.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:18.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:18.85#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:15:18.85#ibcon#first serial, iclass 38, count 0 2006.176.08:15:18.85#ibcon#enter sib2, iclass 38, count 0 2006.176.08:15:18.85#ibcon#flushed, iclass 38, count 0 2006.176.08:15:18.85#ibcon#about to write, iclass 38, count 0 2006.176.08:15:18.85#ibcon#wrote, iclass 38, count 0 2006.176.08:15:18.85#ibcon#about to read 3, iclass 38, count 0 2006.176.08:15:18.87#ibcon#read 3, iclass 38, count 0 2006.176.08:15:18.87#ibcon#about to read 4, iclass 38, count 0 2006.176.08:15:18.87#ibcon#read 4, iclass 38, count 0 2006.176.08:15:18.87#ibcon#about to read 5, iclass 38, count 0 2006.176.08:15:18.87#ibcon#read 5, iclass 38, count 0 2006.176.08:15:18.87#ibcon#about to read 6, iclass 38, count 0 2006.176.08:15:18.87#ibcon#read 6, iclass 38, count 0 2006.176.08:15:18.87#ibcon#end of sib2, iclass 38, count 0 2006.176.08:15:18.87#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:15:18.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:15:18.87#ibcon#[25=USB\r\n] 2006.176.08:15:18.87#ibcon#*before write, iclass 38, count 0 2006.176.08:15:18.87#ibcon#enter sib2, iclass 38, count 0 2006.176.08:15:18.87#ibcon#flushed, iclass 38, count 0 2006.176.08:15:18.87#ibcon#about to write, iclass 38, count 0 2006.176.08:15:18.87#ibcon#wrote, iclass 38, count 0 2006.176.08:15:18.87#ibcon#about to read 3, iclass 38, count 0 2006.176.08:15:18.90#ibcon#read 3, iclass 38, count 0 2006.176.08:15:18.90#ibcon#about to read 4, iclass 38, count 0 2006.176.08:15:18.90#ibcon#read 4, iclass 38, count 0 2006.176.08:15:18.90#ibcon#about to read 5, iclass 38, count 0 2006.176.08:15:18.90#ibcon#read 5, iclass 38, count 0 2006.176.08:15:18.90#ibcon#about to read 6, iclass 38, count 0 2006.176.08:15:18.90#ibcon#read 6, iclass 38, count 0 2006.176.08:15:18.90#ibcon#end of sib2, iclass 38, count 0 2006.176.08:15:18.90#ibcon#*after write, iclass 38, count 0 2006.176.08:15:18.90#ibcon#*before return 0, iclass 38, count 0 2006.176.08:15:18.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:18.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:18.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:15:18.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:15:18.90$vc4f8/valo=4,832.99 2006.176.08:15:18.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.08:15:18.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.08:15:18.90#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:18.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:18.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:18.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:18.90#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:15:18.90#ibcon#first serial, iclass 40, count 0 2006.176.08:15:18.90#ibcon#enter sib2, iclass 40, count 0 2006.176.08:15:18.90#ibcon#flushed, iclass 40, count 0 2006.176.08:15:18.90#ibcon#about to write, iclass 40, count 0 2006.176.08:15:18.90#ibcon#wrote, iclass 40, count 0 2006.176.08:15:18.90#ibcon#about to read 3, iclass 40, count 0 2006.176.08:15:18.92#ibcon#read 3, iclass 40, count 0 2006.176.08:15:18.92#ibcon#about to read 4, iclass 40, count 0 2006.176.08:15:18.92#ibcon#read 4, iclass 40, count 0 2006.176.08:15:18.92#ibcon#about to read 5, iclass 40, count 0 2006.176.08:15:18.92#ibcon#read 5, iclass 40, count 0 2006.176.08:15:18.92#ibcon#about to read 6, iclass 40, count 0 2006.176.08:15:18.92#ibcon#read 6, iclass 40, count 0 2006.176.08:15:18.92#ibcon#end of sib2, iclass 40, count 0 2006.176.08:15:18.92#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:15:18.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:15:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:15:18.92#ibcon#*before write, iclass 40, count 0 2006.176.08:15:18.92#ibcon#enter sib2, iclass 40, count 0 2006.176.08:15:18.92#ibcon#flushed, iclass 40, count 0 2006.176.08:15:18.92#ibcon#about to write, iclass 40, count 0 2006.176.08:15:18.92#ibcon#wrote, iclass 40, count 0 2006.176.08:15:18.92#ibcon#about to read 3, iclass 40, count 0 2006.176.08:15:18.96#ibcon#read 3, iclass 40, count 0 2006.176.08:15:18.96#ibcon#about to read 4, iclass 40, count 0 2006.176.08:15:18.96#ibcon#read 4, iclass 40, count 0 2006.176.08:15:18.96#ibcon#about to read 5, iclass 40, count 0 2006.176.08:15:18.96#ibcon#read 5, iclass 40, count 0 2006.176.08:15:18.96#ibcon#about to read 6, iclass 40, count 0 2006.176.08:15:18.96#ibcon#read 6, iclass 40, count 0 2006.176.08:15:18.96#ibcon#end of sib2, iclass 40, count 0 2006.176.08:15:18.96#ibcon#*after write, iclass 40, count 0 2006.176.08:15:18.96#ibcon#*before return 0, iclass 40, count 0 2006.176.08:15:18.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:18.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:18.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:15:18.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:15:18.96$vc4f8/va=4,7 2006.176.08:15:18.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.08:15:18.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.08:15:18.96#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:18.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:19.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:19.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:19.02#ibcon#enter wrdev, iclass 4, count 2 2006.176.08:15:19.02#ibcon#first serial, iclass 4, count 2 2006.176.08:15:19.02#ibcon#enter sib2, iclass 4, count 2 2006.176.08:15:19.02#ibcon#flushed, iclass 4, count 2 2006.176.08:15:19.02#ibcon#about to write, iclass 4, count 2 2006.176.08:15:19.02#ibcon#wrote, iclass 4, count 2 2006.176.08:15:19.02#ibcon#about to read 3, iclass 4, count 2 2006.176.08:15:19.04#ibcon#read 3, iclass 4, count 2 2006.176.08:15:19.04#ibcon#about to read 4, iclass 4, count 2 2006.176.08:15:19.04#ibcon#read 4, iclass 4, count 2 2006.176.08:15:19.04#ibcon#about to read 5, iclass 4, count 2 2006.176.08:15:19.04#ibcon#read 5, iclass 4, count 2 2006.176.08:15:19.04#ibcon#about to read 6, iclass 4, count 2 2006.176.08:15:19.04#ibcon#read 6, iclass 4, count 2 2006.176.08:15:19.04#ibcon#end of sib2, iclass 4, count 2 2006.176.08:15:19.04#ibcon#*mode == 0, iclass 4, count 2 2006.176.08:15:19.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.08:15:19.04#ibcon#[25=AT04-07\r\n] 2006.176.08:15:19.04#ibcon#*before write, iclass 4, count 2 2006.176.08:15:19.04#ibcon#enter sib2, iclass 4, count 2 2006.176.08:15:19.04#ibcon#flushed, iclass 4, count 2 2006.176.08:15:19.04#ibcon#about to write, iclass 4, count 2 2006.176.08:15:19.04#ibcon#wrote, iclass 4, count 2 2006.176.08:15:19.04#ibcon#about to read 3, iclass 4, count 2 2006.176.08:15:19.07#ibcon#read 3, iclass 4, count 2 2006.176.08:15:19.07#ibcon#about to read 4, iclass 4, count 2 2006.176.08:15:19.07#ibcon#read 4, iclass 4, count 2 2006.176.08:15:19.07#ibcon#about to read 5, iclass 4, count 2 2006.176.08:15:19.07#ibcon#read 5, iclass 4, count 2 2006.176.08:15:19.07#ibcon#about to read 6, iclass 4, count 2 2006.176.08:15:19.07#ibcon#read 6, iclass 4, count 2 2006.176.08:15:19.07#ibcon#end of sib2, iclass 4, count 2 2006.176.08:15:19.07#ibcon#*after write, iclass 4, count 2 2006.176.08:15:19.07#ibcon#*before return 0, iclass 4, count 2 2006.176.08:15:19.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:19.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:19.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.08:15:19.07#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:19.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:19.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:19.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:19.19#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:15:19.19#ibcon#first serial, iclass 4, count 0 2006.176.08:15:19.19#ibcon#enter sib2, iclass 4, count 0 2006.176.08:15:19.19#ibcon#flushed, iclass 4, count 0 2006.176.08:15:19.19#ibcon#about to write, iclass 4, count 0 2006.176.08:15:19.19#ibcon#wrote, iclass 4, count 0 2006.176.08:15:19.19#ibcon#about to read 3, iclass 4, count 0 2006.176.08:15:19.21#ibcon#read 3, iclass 4, count 0 2006.176.08:15:19.21#ibcon#about to read 4, iclass 4, count 0 2006.176.08:15:19.21#ibcon#read 4, iclass 4, count 0 2006.176.08:15:19.21#ibcon#about to read 5, iclass 4, count 0 2006.176.08:15:19.21#ibcon#read 5, iclass 4, count 0 2006.176.08:15:19.21#ibcon#about to read 6, iclass 4, count 0 2006.176.08:15:19.21#ibcon#read 6, iclass 4, count 0 2006.176.08:15:19.21#ibcon#end of sib2, iclass 4, count 0 2006.176.08:15:19.21#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:15:19.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:15:19.21#ibcon#[25=USB\r\n] 2006.176.08:15:19.21#ibcon#*before write, iclass 4, count 0 2006.176.08:15:19.21#ibcon#enter sib2, iclass 4, count 0 2006.176.08:15:19.21#ibcon#flushed, iclass 4, count 0 2006.176.08:15:19.21#ibcon#about to write, iclass 4, count 0 2006.176.08:15:19.21#ibcon#wrote, iclass 4, count 0 2006.176.08:15:19.21#ibcon#about to read 3, iclass 4, count 0 2006.176.08:15:19.24#ibcon#read 3, iclass 4, count 0 2006.176.08:15:19.24#ibcon#about to read 4, iclass 4, count 0 2006.176.08:15:19.24#ibcon#read 4, iclass 4, count 0 2006.176.08:15:19.24#ibcon#about to read 5, iclass 4, count 0 2006.176.08:15:19.24#ibcon#read 5, iclass 4, count 0 2006.176.08:15:19.24#ibcon#about to read 6, iclass 4, count 0 2006.176.08:15:19.24#ibcon#read 6, iclass 4, count 0 2006.176.08:15:19.24#ibcon#end of sib2, iclass 4, count 0 2006.176.08:15:19.24#ibcon#*after write, iclass 4, count 0 2006.176.08:15:19.24#ibcon#*before return 0, iclass 4, count 0 2006.176.08:15:19.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:19.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:19.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:15:19.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:15:19.24$vc4f8/valo=5,652.99 2006.176.08:15:19.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.08:15:19.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.08:15:19.24#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:19.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:19.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:19.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:19.24#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:15:19.24#ibcon#first serial, iclass 6, count 0 2006.176.08:15:19.24#ibcon#enter sib2, iclass 6, count 0 2006.176.08:15:19.24#ibcon#flushed, iclass 6, count 0 2006.176.08:15:19.24#ibcon#about to write, iclass 6, count 0 2006.176.08:15:19.24#ibcon#wrote, iclass 6, count 0 2006.176.08:15:19.24#ibcon#about to read 3, iclass 6, count 0 2006.176.08:15:19.26#ibcon#read 3, iclass 6, count 0 2006.176.08:15:19.26#ibcon#about to read 4, iclass 6, count 0 2006.176.08:15:19.26#ibcon#read 4, iclass 6, count 0 2006.176.08:15:19.26#ibcon#about to read 5, iclass 6, count 0 2006.176.08:15:19.26#ibcon#read 5, iclass 6, count 0 2006.176.08:15:19.26#ibcon#about to read 6, iclass 6, count 0 2006.176.08:15:19.26#ibcon#read 6, iclass 6, count 0 2006.176.08:15:19.26#ibcon#end of sib2, iclass 6, count 0 2006.176.08:15:19.26#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:15:19.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:15:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:15:19.26#ibcon#*before write, iclass 6, count 0 2006.176.08:15:19.26#ibcon#enter sib2, iclass 6, count 0 2006.176.08:15:19.26#ibcon#flushed, iclass 6, count 0 2006.176.08:15:19.26#ibcon#about to write, iclass 6, count 0 2006.176.08:15:19.26#ibcon#wrote, iclass 6, count 0 2006.176.08:15:19.26#ibcon#about to read 3, iclass 6, count 0 2006.176.08:15:19.30#ibcon#read 3, iclass 6, count 0 2006.176.08:15:19.30#ibcon#about to read 4, iclass 6, count 0 2006.176.08:15:19.30#ibcon#read 4, iclass 6, count 0 2006.176.08:15:19.30#ibcon#about to read 5, iclass 6, count 0 2006.176.08:15:19.30#ibcon#read 5, iclass 6, count 0 2006.176.08:15:19.30#ibcon#about to read 6, iclass 6, count 0 2006.176.08:15:19.30#ibcon#read 6, iclass 6, count 0 2006.176.08:15:19.30#ibcon#end of sib2, iclass 6, count 0 2006.176.08:15:19.30#ibcon#*after write, iclass 6, count 0 2006.176.08:15:19.30#ibcon#*before return 0, iclass 6, count 0 2006.176.08:15:19.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:19.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:19.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:15:19.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:15:19.30$vc4f8/va=5,7 2006.176.08:15:19.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.08:15:19.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.08:15:19.30#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:19.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:19.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:19.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:19.36#ibcon#enter wrdev, iclass 10, count 2 2006.176.08:15:19.36#ibcon#first serial, iclass 10, count 2 2006.176.08:15:19.36#ibcon#enter sib2, iclass 10, count 2 2006.176.08:15:19.36#ibcon#flushed, iclass 10, count 2 2006.176.08:15:19.36#ibcon#about to write, iclass 10, count 2 2006.176.08:15:19.36#ibcon#wrote, iclass 10, count 2 2006.176.08:15:19.36#ibcon#about to read 3, iclass 10, count 2 2006.176.08:15:19.38#ibcon#read 3, iclass 10, count 2 2006.176.08:15:19.38#ibcon#about to read 4, iclass 10, count 2 2006.176.08:15:19.38#ibcon#read 4, iclass 10, count 2 2006.176.08:15:19.38#ibcon#about to read 5, iclass 10, count 2 2006.176.08:15:19.38#ibcon#read 5, iclass 10, count 2 2006.176.08:15:19.38#ibcon#about to read 6, iclass 10, count 2 2006.176.08:15:19.38#ibcon#read 6, iclass 10, count 2 2006.176.08:15:19.38#ibcon#end of sib2, iclass 10, count 2 2006.176.08:15:19.38#ibcon#*mode == 0, iclass 10, count 2 2006.176.08:15:19.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.08:15:19.38#ibcon#[25=AT05-07\r\n] 2006.176.08:15:19.38#ibcon#*before write, iclass 10, count 2 2006.176.08:15:19.38#ibcon#enter sib2, iclass 10, count 2 2006.176.08:15:19.38#ibcon#flushed, iclass 10, count 2 2006.176.08:15:19.38#ibcon#about to write, iclass 10, count 2 2006.176.08:15:19.38#ibcon#wrote, iclass 10, count 2 2006.176.08:15:19.38#ibcon#about to read 3, iclass 10, count 2 2006.176.08:15:19.41#ibcon#read 3, iclass 10, count 2 2006.176.08:15:19.41#ibcon#about to read 4, iclass 10, count 2 2006.176.08:15:19.41#ibcon#read 4, iclass 10, count 2 2006.176.08:15:19.41#ibcon#about to read 5, iclass 10, count 2 2006.176.08:15:19.41#ibcon#read 5, iclass 10, count 2 2006.176.08:15:19.41#ibcon#about to read 6, iclass 10, count 2 2006.176.08:15:19.41#ibcon#read 6, iclass 10, count 2 2006.176.08:15:19.41#ibcon#end of sib2, iclass 10, count 2 2006.176.08:15:19.41#ibcon#*after write, iclass 10, count 2 2006.176.08:15:19.41#ibcon#*before return 0, iclass 10, count 2 2006.176.08:15:19.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:19.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:19.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.08:15:19.41#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:19.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:19.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:19.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:19.53#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:15:19.53#ibcon#first serial, iclass 10, count 0 2006.176.08:15:19.53#ibcon#enter sib2, iclass 10, count 0 2006.176.08:15:19.53#ibcon#flushed, iclass 10, count 0 2006.176.08:15:19.53#ibcon#about to write, iclass 10, count 0 2006.176.08:15:19.53#ibcon#wrote, iclass 10, count 0 2006.176.08:15:19.53#ibcon#about to read 3, iclass 10, count 0 2006.176.08:15:19.55#ibcon#read 3, iclass 10, count 0 2006.176.08:15:19.55#ibcon#about to read 4, iclass 10, count 0 2006.176.08:15:19.55#ibcon#read 4, iclass 10, count 0 2006.176.08:15:19.55#ibcon#about to read 5, iclass 10, count 0 2006.176.08:15:19.55#ibcon#read 5, iclass 10, count 0 2006.176.08:15:19.55#ibcon#about to read 6, iclass 10, count 0 2006.176.08:15:19.55#ibcon#read 6, iclass 10, count 0 2006.176.08:15:19.55#ibcon#end of sib2, iclass 10, count 0 2006.176.08:15:19.55#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:15:19.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:15:19.55#ibcon#[25=USB\r\n] 2006.176.08:15:19.55#ibcon#*before write, iclass 10, count 0 2006.176.08:15:19.55#ibcon#enter sib2, iclass 10, count 0 2006.176.08:15:19.55#ibcon#flushed, iclass 10, count 0 2006.176.08:15:19.55#ibcon#about to write, iclass 10, count 0 2006.176.08:15:19.55#ibcon#wrote, iclass 10, count 0 2006.176.08:15:19.55#ibcon#about to read 3, iclass 10, count 0 2006.176.08:15:19.58#ibcon#read 3, iclass 10, count 0 2006.176.08:15:19.58#ibcon#about to read 4, iclass 10, count 0 2006.176.08:15:19.58#ibcon#read 4, iclass 10, count 0 2006.176.08:15:19.58#ibcon#about to read 5, iclass 10, count 0 2006.176.08:15:19.58#ibcon#read 5, iclass 10, count 0 2006.176.08:15:19.58#ibcon#about to read 6, iclass 10, count 0 2006.176.08:15:19.58#ibcon#read 6, iclass 10, count 0 2006.176.08:15:19.58#ibcon#end of sib2, iclass 10, count 0 2006.176.08:15:19.58#ibcon#*after write, iclass 10, count 0 2006.176.08:15:19.58#ibcon#*before return 0, iclass 10, count 0 2006.176.08:15:19.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:19.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:19.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:15:19.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:15:19.58$vc4f8/valo=6,772.99 2006.176.08:15:19.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.08:15:19.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.08:15:19.58#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:19.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:19.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:19.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:19.58#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:15:19.58#ibcon#first serial, iclass 12, count 0 2006.176.08:15:19.58#ibcon#enter sib2, iclass 12, count 0 2006.176.08:15:19.58#ibcon#flushed, iclass 12, count 0 2006.176.08:15:19.58#ibcon#about to write, iclass 12, count 0 2006.176.08:15:19.58#ibcon#wrote, iclass 12, count 0 2006.176.08:15:19.58#ibcon#about to read 3, iclass 12, count 0 2006.176.08:15:19.60#ibcon#read 3, iclass 12, count 0 2006.176.08:15:19.60#ibcon#about to read 4, iclass 12, count 0 2006.176.08:15:19.60#ibcon#read 4, iclass 12, count 0 2006.176.08:15:19.60#ibcon#about to read 5, iclass 12, count 0 2006.176.08:15:19.60#ibcon#read 5, iclass 12, count 0 2006.176.08:15:19.60#ibcon#about to read 6, iclass 12, count 0 2006.176.08:15:19.60#ibcon#read 6, iclass 12, count 0 2006.176.08:15:19.60#ibcon#end of sib2, iclass 12, count 0 2006.176.08:15:19.60#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:15:19.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:15:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:15:19.60#ibcon#*before write, iclass 12, count 0 2006.176.08:15:19.60#ibcon#enter sib2, iclass 12, count 0 2006.176.08:15:19.60#ibcon#flushed, iclass 12, count 0 2006.176.08:15:19.60#ibcon#about to write, iclass 12, count 0 2006.176.08:15:19.60#ibcon#wrote, iclass 12, count 0 2006.176.08:15:19.60#ibcon#about to read 3, iclass 12, count 0 2006.176.08:15:19.64#ibcon#read 3, iclass 12, count 0 2006.176.08:15:19.64#ibcon#about to read 4, iclass 12, count 0 2006.176.08:15:19.64#ibcon#read 4, iclass 12, count 0 2006.176.08:15:19.64#ibcon#about to read 5, iclass 12, count 0 2006.176.08:15:19.64#ibcon#read 5, iclass 12, count 0 2006.176.08:15:19.64#ibcon#about to read 6, iclass 12, count 0 2006.176.08:15:19.64#ibcon#read 6, iclass 12, count 0 2006.176.08:15:19.64#ibcon#end of sib2, iclass 12, count 0 2006.176.08:15:19.64#ibcon#*after write, iclass 12, count 0 2006.176.08:15:19.64#ibcon#*before return 0, iclass 12, count 0 2006.176.08:15:19.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:19.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:19.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:15:19.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:15:19.64$vc4f8/va=6,6 2006.176.08:15:19.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.08:15:19.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.08:15:19.64#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:19.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:15:19.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:15:19.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:15:19.70#ibcon#enter wrdev, iclass 14, count 2 2006.176.08:15:19.70#ibcon#first serial, iclass 14, count 2 2006.176.08:15:19.70#ibcon#enter sib2, iclass 14, count 2 2006.176.08:15:19.70#ibcon#flushed, iclass 14, count 2 2006.176.08:15:19.70#ibcon#about to write, iclass 14, count 2 2006.176.08:15:19.70#ibcon#wrote, iclass 14, count 2 2006.176.08:15:19.70#ibcon#about to read 3, iclass 14, count 2 2006.176.08:15:19.72#ibcon#read 3, iclass 14, count 2 2006.176.08:15:19.72#ibcon#about to read 4, iclass 14, count 2 2006.176.08:15:19.72#ibcon#read 4, iclass 14, count 2 2006.176.08:15:19.72#ibcon#about to read 5, iclass 14, count 2 2006.176.08:15:19.72#ibcon#read 5, iclass 14, count 2 2006.176.08:15:19.72#ibcon#about to read 6, iclass 14, count 2 2006.176.08:15:19.72#ibcon#read 6, iclass 14, count 2 2006.176.08:15:19.72#ibcon#end of sib2, iclass 14, count 2 2006.176.08:15:19.72#ibcon#*mode == 0, iclass 14, count 2 2006.176.08:15:19.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.08:15:19.72#ibcon#[25=AT06-06\r\n] 2006.176.08:15:19.72#ibcon#*before write, iclass 14, count 2 2006.176.08:15:19.72#ibcon#enter sib2, iclass 14, count 2 2006.176.08:15:19.72#ibcon#flushed, iclass 14, count 2 2006.176.08:15:19.72#ibcon#about to write, iclass 14, count 2 2006.176.08:15:19.72#ibcon#wrote, iclass 14, count 2 2006.176.08:15:19.72#ibcon#about to read 3, iclass 14, count 2 2006.176.08:15:19.75#ibcon#read 3, iclass 14, count 2 2006.176.08:15:19.75#ibcon#about to read 4, iclass 14, count 2 2006.176.08:15:19.75#ibcon#read 4, iclass 14, count 2 2006.176.08:15:19.75#ibcon#about to read 5, iclass 14, count 2 2006.176.08:15:19.75#ibcon#read 5, iclass 14, count 2 2006.176.08:15:19.75#ibcon#about to read 6, iclass 14, count 2 2006.176.08:15:19.75#ibcon#read 6, iclass 14, count 2 2006.176.08:15:19.75#ibcon#end of sib2, iclass 14, count 2 2006.176.08:15:19.75#ibcon#*after write, iclass 14, count 2 2006.176.08:15:19.75#ibcon#*before return 0, iclass 14, count 2 2006.176.08:15:19.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:15:19.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:15:19.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.08:15:19.75#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:19.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:15:19.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:15:19.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:15:19.87#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:15:19.87#ibcon#first serial, iclass 14, count 0 2006.176.08:15:19.87#ibcon#enter sib2, iclass 14, count 0 2006.176.08:15:19.87#ibcon#flushed, iclass 14, count 0 2006.176.08:15:19.87#ibcon#about to write, iclass 14, count 0 2006.176.08:15:19.87#ibcon#wrote, iclass 14, count 0 2006.176.08:15:19.87#ibcon#about to read 3, iclass 14, count 0 2006.176.08:15:19.89#ibcon#read 3, iclass 14, count 0 2006.176.08:15:19.89#ibcon#about to read 4, iclass 14, count 0 2006.176.08:15:19.89#ibcon#read 4, iclass 14, count 0 2006.176.08:15:19.89#ibcon#about to read 5, iclass 14, count 0 2006.176.08:15:19.89#ibcon#read 5, iclass 14, count 0 2006.176.08:15:19.89#ibcon#about to read 6, iclass 14, count 0 2006.176.08:15:19.89#ibcon#read 6, iclass 14, count 0 2006.176.08:15:19.89#ibcon#end of sib2, iclass 14, count 0 2006.176.08:15:19.89#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:15:19.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:15:19.89#ibcon#[25=USB\r\n] 2006.176.08:15:19.89#ibcon#*before write, iclass 14, count 0 2006.176.08:15:19.89#ibcon#enter sib2, iclass 14, count 0 2006.176.08:15:19.89#ibcon#flushed, iclass 14, count 0 2006.176.08:15:19.89#ibcon#about to write, iclass 14, count 0 2006.176.08:15:19.89#ibcon#wrote, iclass 14, count 0 2006.176.08:15:19.89#ibcon#about to read 3, iclass 14, count 0 2006.176.08:15:19.92#ibcon#read 3, iclass 14, count 0 2006.176.08:15:19.92#ibcon#about to read 4, iclass 14, count 0 2006.176.08:15:19.92#ibcon#read 4, iclass 14, count 0 2006.176.08:15:19.92#ibcon#about to read 5, iclass 14, count 0 2006.176.08:15:19.92#ibcon#read 5, iclass 14, count 0 2006.176.08:15:19.92#ibcon#about to read 6, iclass 14, count 0 2006.176.08:15:19.92#ibcon#read 6, iclass 14, count 0 2006.176.08:15:19.92#ibcon#end of sib2, iclass 14, count 0 2006.176.08:15:19.92#ibcon#*after write, iclass 14, count 0 2006.176.08:15:19.92#ibcon#*before return 0, iclass 14, count 0 2006.176.08:15:19.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:15:19.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:15:19.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:15:19.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:15:19.92$vc4f8/valo=7,832.99 2006.176.08:15:19.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.08:15:19.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.08:15:19.92#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:19.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:15:19.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:15:19.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:15:19.92#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:15:19.92#ibcon#first serial, iclass 16, count 0 2006.176.08:15:19.92#ibcon#enter sib2, iclass 16, count 0 2006.176.08:15:19.92#ibcon#flushed, iclass 16, count 0 2006.176.08:15:19.92#ibcon#about to write, iclass 16, count 0 2006.176.08:15:19.92#ibcon#wrote, iclass 16, count 0 2006.176.08:15:19.92#ibcon#about to read 3, iclass 16, count 0 2006.176.08:15:19.94#ibcon#read 3, iclass 16, count 0 2006.176.08:15:19.94#ibcon#about to read 4, iclass 16, count 0 2006.176.08:15:19.94#ibcon#read 4, iclass 16, count 0 2006.176.08:15:19.94#ibcon#about to read 5, iclass 16, count 0 2006.176.08:15:19.94#ibcon#read 5, iclass 16, count 0 2006.176.08:15:19.94#ibcon#about to read 6, iclass 16, count 0 2006.176.08:15:19.94#ibcon#read 6, iclass 16, count 0 2006.176.08:15:19.94#ibcon#end of sib2, iclass 16, count 0 2006.176.08:15:19.94#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:15:19.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:15:19.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:15:19.94#ibcon#*before write, iclass 16, count 0 2006.176.08:15:19.94#ibcon#enter sib2, iclass 16, count 0 2006.176.08:15:19.94#ibcon#flushed, iclass 16, count 0 2006.176.08:15:19.94#ibcon#about to write, iclass 16, count 0 2006.176.08:15:19.94#ibcon#wrote, iclass 16, count 0 2006.176.08:15:19.94#ibcon#about to read 3, iclass 16, count 0 2006.176.08:15:19.98#ibcon#read 3, iclass 16, count 0 2006.176.08:15:19.98#ibcon#about to read 4, iclass 16, count 0 2006.176.08:15:19.98#ibcon#read 4, iclass 16, count 0 2006.176.08:15:19.98#ibcon#about to read 5, iclass 16, count 0 2006.176.08:15:19.98#ibcon#read 5, iclass 16, count 0 2006.176.08:15:19.98#ibcon#about to read 6, iclass 16, count 0 2006.176.08:15:19.98#ibcon#read 6, iclass 16, count 0 2006.176.08:15:19.98#ibcon#end of sib2, iclass 16, count 0 2006.176.08:15:19.98#ibcon#*after write, iclass 16, count 0 2006.176.08:15:19.98#ibcon#*before return 0, iclass 16, count 0 2006.176.08:15:19.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:15:19.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:15:19.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:15:19.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:15:19.98$vc4f8/va=7,6 2006.176.08:15:19.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.08:15:19.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.08:15:19.98#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:19.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:15:20.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:15:20.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:15:20.04#ibcon#enter wrdev, iclass 18, count 2 2006.176.08:15:20.04#ibcon#first serial, iclass 18, count 2 2006.176.08:15:20.04#ibcon#enter sib2, iclass 18, count 2 2006.176.08:15:20.04#ibcon#flushed, iclass 18, count 2 2006.176.08:15:20.04#ibcon#about to write, iclass 18, count 2 2006.176.08:15:20.04#ibcon#wrote, iclass 18, count 2 2006.176.08:15:20.04#ibcon#about to read 3, iclass 18, count 2 2006.176.08:15:20.06#ibcon#read 3, iclass 18, count 2 2006.176.08:15:20.06#ibcon#about to read 4, iclass 18, count 2 2006.176.08:15:20.06#ibcon#read 4, iclass 18, count 2 2006.176.08:15:20.06#ibcon#about to read 5, iclass 18, count 2 2006.176.08:15:20.06#ibcon#read 5, iclass 18, count 2 2006.176.08:15:20.06#ibcon#about to read 6, iclass 18, count 2 2006.176.08:15:20.06#ibcon#read 6, iclass 18, count 2 2006.176.08:15:20.06#ibcon#end of sib2, iclass 18, count 2 2006.176.08:15:20.06#ibcon#*mode == 0, iclass 18, count 2 2006.176.08:15:20.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.08:15:20.06#ibcon#[25=AT07-06\r\n] 2006.176.08:15:20.06#ibcon#*before write, iclass 18, count 2 2006.176.08:15:20.06#ibcon#enter sib2, iclass 18, count 2 2006.176.08:15:20.06#ibcon#flushed, iclass 18, count 2 2006.176.08:15:20.06#ibcon#about to write, iclass 18, count 2 2006.176.08:15:20.06#ibcon#wrote, iclass 18, count 2 2006.176.08:15:20.06#ibcon#about to read 3, iclass 18, count 2 2006.176.08:15:20.09#ibcon#read 3, iclass 18, count 2 2006.176.08:15:20.09#ibcon#about to read 4, iclass 18, count 2 2006.176.08:15:20.09#ibcon#read 4, iclass 18, count 2 2006.176.08:15:20.09#ibcon#about to read 5, iclass 18, count 2 2006.176.08:15:20.09#ibcon#read 5, iclass 18, count 2 2006.176.08:15:20.09#ibcon#about to read 6, iclass 18, count 2 2006.176.08:15:20.09#ibcon#read 6, iclass 18, count 2 2006.176.08:15:20.09#ibcon#end of sib2, iclass 18, count 2 2006.176.08:15:20.09#ibcon#*after write, iclass 18, count 2 2006.176.08:15:20.09#ibcon#*before return 0, iclass 18, count 2 2006.176.08:15:20.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:15:20.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:15:20.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.08:15:20.09#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:20.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:15:20.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:15:20.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:15:20.21#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:15:20.21#ibcon#first serial, iclass 18, count 0 2006.176.08:15:20.21#ibcon#enter sib2, iclass 18, count 0 2006.176.08:15:20.21#ibcon#flushed, iclass 18, count 0 2006.176.08:15:20.21#ibcon#about to write, iclass 18, count 0 2006.176.08:15:20.21#ibcon#wrote, iclass 18, count 0 2006.176.08:15:20.21#ibcon#about to read 3, iclass 18, count 0 2006.176.08:15:20.23#ibcon#read 3, iclass 18, count 0 2006.176.08:15:20.23#ibcon#about to read 4, iclass 18, count 0 2006.176.08:15:20.23#ibcon#read 4, iclass 18, count 0 2006.176.08:15:20.23#ibcon#about to read 5, iclass 18, count 0 2006.176.08:15:20.23#ibcon#read 5, iclass 18, count 0 2006.176.08:15:20.23#ibcon#about to read 6, iclass 18, count 0 2006.176.08:15:20.23#ibcon#read 6, iclass 18, count 0 2006.176.08:15:20.23#ibcon#end of sib2, iclass 18, count 0 2006.176.08:15:20.23#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:15:20.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:15:20.23#ibcon#[25=USB\r\n] 2006.176.08:15:20.23#ibcon#*before write, iclass 18, count 0 2006.176.08:15:20.23#ibcon#enter sib2, iclass 18, count 0 2006.176.08:15:20.23#ibcon#flushed, iclass 18, count 0 2006.176.08:15:20.23#ibcon#about to write, iclass 18, count 0 2006.176.08:15:20.23#ibcon#wrote, iclass 18, count 0 2006.176.08:15:20.23#ibcon#about to read 3, iclass 18, count 0 2006.176.08:15:20.26#ibcon#read 3, iclass 18, count 0 2006.176.08:15:20.26#ibcon#about to read 4, iclass 18, count 0 2006.176.08:15:20.26#ibcon#read 4, iclass 18, count 0 2006.176.08:15:20.26#ibcon#about to read 5, iclass 18, count 0 2006.176.08:15:20.26#ibcon#read 5, iclass 18, count 0 2006.176.08:15:20.26#ibcon#about to read 6, iclass 18, count 0 2006.176.08:15:20.26#ibcon#read 6, iclass 18, count 0 2006.176.08:15:20.26#ibcon#end of sib2, iclass 18, count 0 2006.176.08:15:20.26#ibcon#*after write, iclass 18, count 0 2006.176.08:15:20.26#ibcon#*before return 0, iclass 18, count 0 2006.176.08:15:20.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:15:20.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:15:20.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:15:20.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:15:20.26$vc4f8/valo=8,852.99 2006.176.08:15:20.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.08:15:20.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.08:15:20.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:20.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:15:20.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:15:20.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:15:20.26#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:15:20.26#ibcon#first serial, iclass 20, count 0 2006.176.08:15:20.26#ibcon#enter sib2, iclass 20, count 0 2006.176.08:15:20.26#ibcon#flushed, iclass 20, count 0 2006.176.08:15:20.26#ibcon#about to write, iclass 20, count 0 2006.176.08:15:20.26#ibcon#wrote, iclass 20, count 0 2006.176.08:15:20.26#ibcon#about to read 3, iclass 20, count 0 2006.176.08:15:20.28#ibcon#read 3, iclass 20, count 0 2006.176.08:15:20.28#ibcon#about to read 4, iclass 20, count 0 2006.176.08:15:20.28#ibcon#read 4, iclass 20, count 0 2006.176.08:15:20.28#ibcon#about to read 5, iclass 20, count 0 2006.176.08:15:20.28#ibcon#read 5, iclass 20, count 0 2006.176.08:15:20.28#ibcon#about to read 6, iclass 20, count 0 2006.176.08:15:20.28#ibcon#read 6, iclass 20, count 0 2006.176.08:15:20.28#ibcon#end of sib2, iclass 20, count 0 2006.176.08:15:20.28#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:15:20.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:15:20.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:15:20.28#ibcon#*before write, iclass 20, count 0 2006.176.08:15:20.28#ibcon#enter sib2, iclass 20, count 0 2006.176.08:15:20.28#ibcon#flushed, iclass 20, count 0 2006.176.08:15:20.28#ibcon#about to write, iclass 20, count 0 2006.176.08:15:20.28#ibcon#wrote, iclass 20, count 0 2006.176.08:15:20.28#ibcon#about to read 3, iclass 20, count 0 2006.176.08:15:20.32#ibcon#read 3, iclass 20, count 0 2006.176.08:15:20.32#ibcon#about to read 4, iclass 20, count 0 2006.176.08:15:20.32#ibcon#read 4, iclass 20, count 0 2006.176.08:15:20.32#ibcon#about to read 5, iclass 20, count 0 2006.176.08:15:20.32#ibcon#read 5, iclass 20, count 0 2006.176.08:15:20.32#ibcon#about to read 6, iclass 20, count 0 2006.176.08:15:20.32#ibcon#read 6, iclass 20, count 0 2006.176.08:15:20.32#ibcon#end of sib2, iclass 20, count 0 2006.176.08:15:20.32#ibcon#*after write, iclass 20, count 0 2006.176.08:15:20.32#ibcon#*before return 0, iclass 20, count 0 2006.176.08:15:20.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:15:20.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:15:20.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:15:20.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:15:20.32$vc4f8/va=8,6 2006.176.08:15:20.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.08:15:20.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.08:15:20.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:20.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:15:20.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:15:20.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:15:20.38#ibcon#enter wrdev, iclass 22, count 2 2006.176.08:15:20.38#ibcon#first serial, iclass 22, count 2 2006.176.08:15:20.38#ibcon#enter sib2, iclass 22, count 2 2006.176.08:15:20.38#ibcon#flushed, iclass 22, count 2 2006.176.08:15:20.38#ibcon#about to write, iclass 22, count 2 2006.176.08:15:20.38#ibcon#wrote, iclass 22, count 2 2006.176.08:15:20.38#ibcon#about to read 3, iclass 22, count 2 2006.176.08:15:20.40#ibcon#read 3, iclass 22, count 2 2006.176.08:15:20.40#ibcon#about to read 4, iclass 22, count 2 2006.176.08:15:20.40#ibcon#read 4, iclass 22, count 2 2006.176.08:15:20.40#ibcon#about to read 5, iclass 22, count 2 2006.176.08:15:20.40#ibcon#read 5, iclass 22, count 2 2006.176.08:15:20.40#ibcon#about to read 6, iclass 22, count 2 2006.176.08:15:20.40#ibcon#read 6, iclass 22, count 2 2006.176.08:15:20.40#ibcon#end of sib2, iclass 22, count 2 2006.176.08:15:20.40#ibcon#*mode == 0, iclass 22, count 2 2006.176.08:15:20.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.08:15:20.40#ibcon#[25=AT08-06\r\n] 2006.176.08:15:20.40#ibcon#*before write, iclass 22, count 2 2006.176.08:15:20.40#ibcon#enter sib2, iclass 22, count 2 2006.176.08:15:20.40#ibcon#flushed, iclass 22, count 2 2006.176.08:15:20.40#ibcon#about to write, iclass 22, count 2 2006.176.08:15:20.40#ibcon#wrote, iclass 22, count 2 2006.176.08:15:20.40#ibcon#about to read 3, iclass 22, count 2 2006.176.08:15:20.43#ibcon#read 3, iclass 22, count 2 2006.176.08:15:20.43#ibcon#about to read 4, iclass 22, count 2 2006.176.08:15:20.43#ibcon#read 4, iclass 22, count 2 2006.176.08:15:20.43#ibcon#about to read 5, iclass 22, count 2 2006.176.08:15:20.43#ibcon#read 5, iclass 22, count 2 2006.176.08:15:20.43#ibcon#about to read 6, iclass 22, count 2 2006.176.08:15:20.43#ibcon#read 6, iclass 22, count 2 2006.176.08:15:20.43#ibcon#end of sib2, iclass 22, count 2 2006.176.08:15:20.43#ibcon#*after write, iclass 22, count 2 2006.176.08:15:20.43#ibcon#*before return 0, iclass 22, count 2 2006.176.08:15:20.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:15:20.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:15:20.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.08:15:20.43#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:20.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:15:20.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:15:20.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:15:20.55#ibcon#enter wrdev, iclass 22, count 0 2006.176.08:15:20.55#ibcon#first serial, iclass 22, count 0 2006.176.08:15:20.55#ibcon#enter sib2, iclass 22, count 0 2006.176.08:15:20.55#ibcon#flushed, iclass 22, count 0 2006.176.08:15:20.55#ibcon#about to write, iclass 22, count 0 2006.176.08:15:20.55#ibcon#wrote, iclass 22, count 0 2006.176.08:15:20.55#ibcon#about to read 3, iclass 22, count 0 2006.176.08:15:20.57#ibcon#read 3, iclass 22, count 0 2006.176.08:15:20.57#ibcon#about to read 4, iclass 22, count 0 2006.176.08:15:20.57#ibcon#read 4, iclass 22, count 0 2006.176.08:15:20.57#ibcon#about to read 5, iclass 22, count 0 2006.176.08:15:20.57#ibcon#read 5, iclass 22, count 0 2006.176.08:15:20.57#ibcon#about to read 6, iclass 22, count 0 2006.176.08:15:20.57#ibcon#read 6, iclass 22, count 0 2006.176.08:15:20.57#ibcon#end of sib2, iclass 22, count 0 2006.176.08:15:20.57#ibcon#*mode == 0, iclass 22, count 0 2006.176.08:15:20.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.08:15:20.57#ibcon#[25=USB\r\n] 2006.176.08:15:20.57#ibcon#*before write, iclass 22, count 0 2006.176.08:15:20.57#ibcon#enter sib2, iclass 22, count 0 2006.176.08:15:20.57#ibcon#flushed, iclass 22, count 0 2006.176.08:15:20.57#ibcon#about to write, iclass 22, count 0 2006.176.08:15:20.57#ibcon#wrote, iclass 22, count 0 2006.176.08:15:20.57#ibcon#about to read 3, iclass 22, count 0 2006.176.08:15:20.60#ibcon#read 3, iclass 22, count 0 2006.176.08:15:20.60#ibcon#about to read 4, iclass 22, count 0 2006.176.08:15:20.60#ibcon#read 4, iclass 22, count 0 2006.176.08:15:20.60#ibcon#about to read 5, iclass 22, count 0 2006.176.08:15:20.60#ibcon#read 5, iclass 22, count 0 2006.176.08:15:20.60#ibcon#about to read 6, iclass 22, count 0 2006.176.08:15:20.60#ibcon#read 6, iclass 22, count 0 2006.176.08:15:20.60#ibcon#end of sib2, iclass 22, count 0 2006.176.08:15:20.60#ibcon#*after write, iclass 22, count 0 2006.176.08:15:20.60#ibcon#*before return 0, iclass 22, count 0 2006.176.08:15:20.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:15:20.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:15:20.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.08:15:20.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.08:15:20.60$vc4f8/vblo=1,632.99 2006.176.08:15:20.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.08:15:20.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.08:15:20.60#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:20.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:20.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:20.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:20.60#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:15:20.60#ibcon#first serial, iclass 24, count 0 2006.176.08:15:20.60#ibcon#enter sib2, iclass 24, count 0 2006.176.08:15:20.60#ibcon#flushed, iclass 24, count 0 2006.176.08:15:20.60#ibcon#about to write, iclass 24, count 0 2006.176.08:15:20.60#ibcon#wrote, iclass 24, count 0 2006.176.08:15:20.60#ibcon#about to read 3, iclass 24, count 0 2006.176.08:15:20.62#ibcon#read 3, iclass 24, count 0 2006.176.08:15:20.62#ibcon#about to read 4, iclass 24, count 0 2006.176.08:15:20.62#ibcon#read 4, iclass 24, count 0 2006.176.08:15:20.62#ibcon#about to read 5, iclass 24, count 0 2006.176.08:15:20.62#ibcon#read 5, iclass 24, count 0 2006.176.08:15:20.62#ibcon#about to read 6, iclass 24, count 0 2006.176.08:15:20.62#ibcon#read 6, iclass 24, count 0 2006.176.08:15:20.62#ibcon#end of sib2, iclass 24, count 0 2006.176.08:15:20.62#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:15:20.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:15:20.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:15:20.62#ibcon#*before write, iclass 24, count 0 2006.176.08:15:20.62#ibcon#enter sib2, iclass 24, count 0 2006.176.08:15:20.62#ibcon#flushed, iclass 24, count 0 2006.176.08:15:20.62#ibcon#about to write, iclass 24, count 0 2006.176.08:15:20.62#ibcon#wrote, iclass 24, count 0 2006.176.08:15:20.62#ibcon#about to read 3, iclass 24, count 0 2006.176.08:15:20.66#ibcon#read 3, iclass 24, count 0 2006.176.08:15:20.66#ibcon#about to read 4, iclass 24, count 0 2006.176.08:15:20.66#ibcon#read 4, iclass 24, count 0 2006.176.08:15:20.66#ibcon#about to read 5, iclass 24, count 0 2006.176.08:15:20.66#ibcon#read 5, iclass 24, count 0 2006.176.08:15:20.66#ibcon#about to read 6, iclass 24, count 0 2006.176.08:15:20.66#ibcon#read 6, iclass 24, count 0 2006.176.08:15:20.66#ibcon#end of sib2, iclass 24, count 0 2006.176.08:15:20.66#ibcon#*after write, iclass 24, count 0 2006.176.08:15:20.66#ibcon#*before return 0, iclass 24, count 0 2006.176.08:15:20.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:20.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:15:20.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:15:20.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:15:20.66$vc4f8/vb=1,4 2006.176.08:15:20.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.08:15:20.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.08:15:20.66#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:20.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:20.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:20.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:20.66#ibcon#enter wrdev, iclass 26, count 2 2006.176.08:15:20.66#ibcon#first serial, iclass 26, count 2 2006.176.08:15:20.66#ibcon#enter sib2, iclass 26, count 2 2006.176.08:15:20.66#ibcon#flushed, iclass 26, count 2 2006.176.08:15:20.66#ibcon#about to write, iclass 26, count 2 2006.176.08:15:20.66#ibcon#wrote, iclass 26, count 2 2006.176.08:15:20.66#ibcon#about to read 3, iclass 26, count 2 2006.176.08:15:20.68#ibcon#read 3, iclass 26, count 2 2006.176.08:15:20.68#ibcon#about to read 4, iclass 26, count 2 2006.176.08:15:20.68#ibcon#read 4, iclass 26, count 2 2006.176.08:15:20.68#ibcon#about to read 5, iclass 26, count 2 2006.176.08:15:20.68#ibcon#read 5, iclass 26, count 2 2006.176.08:15:20.68#ibcon#about to read 6, iclass 26, count 2 2006.176.08:15:20.68#ibcon#read 6, iclass 26, count 2 2006.176.08:15:20.68#ibcon#end of sib2, iclass 26, count 2 2006.176.08:15:20.68#ibcon#*mode == 0, iclass 26, count 2 2006.176.08:15:20.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.08:15:20.68#ibcon#[27=AT01-04\r\n] 2006.176.08:15:20.68#ibcon#*before write, iclass 26, count 2 2006.176.08:15:20.68#ibcon#enter sib2, iclass 26, count 2 2006.176.08:15:20.68#ibcon#flushed, iclass 26, count 2 2006.176.08:15:20.68#ibcon#about to write, iclass 26, count 2 2006.176.08:15:20.68#ibcon#wrote, iclass 26, count 2 2006.176.08:15:20.68#ibcon#about to read 3, iclass 26, count 2 2006.176.08:15:20.71#ibcon#read 3, iclass 26, count 2 2006.176.08:15:20.71#ibcon#about to read 4, iclass 26, count 2 2006.176.08:15:20.71#ibcon#read 4, iclass 26, count 2 2006.176.08:15:20.71#ibcon#about to read 5, iclass 26, count 2 2006.176.08:15:20.71#ibcon#read 5, iclass 26, count 2 2006.176.08:15:20.71#ibcon#about to read 6, iclass 26, count 2 2006.176.08:15:20.71#ibcon#read 6, iclass 26, count 2 2006.176.08:15:20.71#ibcon#end of sib2, iclass 26, count 2 2006.176.08:15:20.71#ibcon#*after write, iclass 26, count 2 2006.176.08:15:20.71#ibcon#*before return 0, iclass 26, count 2 2006.176.08:15:20.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:20.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:15:20.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.08:15:20.71#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:20.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:20.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:20.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:20.83#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:15:20.83#ibcon#first serial, iclass 26, count 0 2006.176.08:15:20.83#ibcon#enter sib2, iclass 26, count 0 2006.176.08:15:20.83#ibcon#flushed, iclass 26, count 0 2006.176.08:15:20.83#ibcon#about to write, iclass 26, count 0 2006.176.08:15:20.83#ibcon#wrote, iclass 26, count 0 2006.176.08:15:20.83#ibcon#about to read 3, iclass 26, count 0 2006.176.08:15:20.85#ibcon#read 3, iclass 26, count 0 2006.176.08:15:20.85#ibcon#about to read 4, iclass 26, count 0 2006.176.08:15:20.85#ibcon#read 4, iclass 26, count 0 2006.176.08:15:20.85#ibcon#about to read 5, iclass 26, count 0 2006.176.08:15:20.85#ibcon#read 5, iclass 26, count 0 2006.176.08:15:20.85#ibcon#about to read 6, iclass 26, count 0 2006.176.08:15:20.85#ibcon#read 6, iclass 26, count 0 2006.176.08:15:20.85#ibcon#end of sib2, iclass 26, count 0 2006.176.08:15:20.85#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:15:20.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:15:20.85#ibcon#[27=USB\r\n] 2006.176.08:15:20.85#ibcon#*before write, iclass 26, count 0 2006.176.08:15:20.85#ibcon#enter sib2, iclass 26, count 0 2006.176.08:15:20.85#ibcon#flushed, iclass 26, count 0 2006.176.08:15:20.85#ibcon#about to write, iclass 26, count 0 2006.176.08:15:20.85#ibcon#wrote, iclass 26, count 0 2006.176.08:15:20.85#ibcon#about to read 3, iclass 26, count 0 2006.176.08:15:20.88#ibcon#read 3, iclass 26, count 0 2006.176.08:15:20.88#ibcon#about to read 4, iclass 26, count 0 2006.176.08:15:20.88#ibcon#read 4, iclass 26, count 0 2006.176.08:15:20.88#ibcon#about to read 5, iclass 26, count 0 2006.176.08:15:20.88#ibcon#read 5, iclass 26, count 0 2006.176.08:15:20.88#ibcon#about to read 6, iclass 26, count 0 2006.176.08:15:20.88#ibcon#read 6, iclass 26, count 0 2006.176.08:15:20.88#ibcon#end of sib2, iclass 26, count 0 2006.176.08:15:20.88#ibcon#*after write, iclass 26, count 0 2006.176.08:15:20.88#ibcon#*before return 0, iclass 26, count 0 2006.176.08:15:20.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:20.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:15:20.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:15:20.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:15:20.88$vc4f8/vblo=2,640.99 2006.176.08:15:20.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.08:15:20.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.08:15:20.88#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:20.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:20.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:20.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:20.88#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:15:20.88#ibcon#first serial, iclass 28, count 0 2006.176.08:15:20.88#ibcon#enter sib2, iclass 28, count 0 2006.176.08:15:20.88#ibcon#flushed, iclass 28, count 0 2006.176.08:15:20.88#ibcon#about to write, iclass 28, count 0 2006.176.08:15:20.88#ibcon#wrote, iclass 28, count 0 2006.176.08:15:20.88#ibcon#about to read 3, iclass 28, count 0 2006.176.08:15:20.90#ibcon#read 3, iclass 28, count 0 2006.176.08:15:20.90#ibcon#about to read 4, iclass 28, count 0 2006.176.08:15:20.90#ibcon#read 4, iclass 28, count 0 2006.176.08:15:20.90#ibcon#about to read 5, iclass 28, count 0 2006.176.08:15:20.90#ibcon#read 5, iclass 28, count 0 2006.176.08:15:20.90#ibcon#about to read 6, iclass 28, count 0 2006.176.08:15:20.90#ibcon#read 6, iclass 28, count 0 2006.176.08:15:20.90#ibcon#end of sib2, iclass 28, count 0 2006.176.08:15:20.90#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:15:20.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:15:20.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:15:20.90#ibcon#*before write, iclass 28, count 0 2006.176.08:15:20.90#ibcon#enter sib2, iclass 28, count 0 2006.176.08:15:20.90#ibcon#flushed, iclass 28, count 0 2006.176.08:15:20.90#ibcon#about to write, iclass 28, count 0 2006.176.08:15:20.90#ibcon#wrote, iclass 28, count 0 2006.176.08:15:20.90#ibcon#about to read 3, iclass 28, count 0 2006.176.08:15:20.94#ibcon#read 3, iclass 28, count 0 2006.176.08:15:20.94#ibcon#about to read 4, iclass 28, count 0 2006.176.08:15:20.94#ibcon#read 4, iclass 28, count 0 2006.176.08:15:20.94#ibcon#about to read 5, iclass 28, count 0 2006.176.08:15:20.94#ibcon#read 5, iclass 28, count 0 2006.176.08:15:20.94#ibcon#about to read 6, iclass 28, count 0 2006.176.08:15:20.94#ibcon#read 6, iclass 28, count 0 2006.176.08:15:20.94#ibcon#end of sib2, iclass 28, count 0 2006.176.08:15:20.94#ibcon#*after write, iclass 28, count 0 2006.176.08:15:20.94#ibcon#*before return 0, iclass 28, count 0 2006.176.08:15:20.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:20.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:15:20.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:15:20.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:15:20.94$vc4f8/vb=2,4 2006.176.08:15:20.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.08:15:20.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.08:15:20.94#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:20.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:15:21.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:15:21.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:15:21.00#ibcon#enter wrdev, iclass 30, count 2 2006.176.08:15:21.00#ibcon#first serial, iclass 30, count 2 2006.176.08:15:21.00#ibcon#enter sib2, iclass 30, count 2 2006.176.08:15:21.00#ibcon#flushed, iclass 30, count 2 2006.176.08:15:21.00#ibcon#about to write, iclass 30, count 2 2006.176.08:15:21.00#ibcon#wrote, iclass 30, count 2 2006.176.08:15:21.00#ibcon#about to read 3, iclass 30, count 2 2006.176.08:15:21.02#ibcon#read 3, iclass 30, count 2 2006.176.08:15:21.02#ibcon#about to read 4, iclass 30, count 2 2006.176.08:15:21.02#ibcon#read 4, iclass 30, count 2 2006.176.08:15:21.02#ibcon#about to read 5, iclass 30, count 2 2006.176.08:15:21.02#ibcon#read 5, iclass 30, count 2 2006.176.08:15:21.02#ibcon#about to read 6, iclass 30, count 2 2006.176.08:15:21.02#ibcon#read 6, iclass 30, count 2 2006.176.08:15:21.02#ibcon#end of sib2, iclass 30, count 2 2006.176.08:15:21.02#ibcon#*mode == 0, iclass 30, count 2 2006.176.08:15:21.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.08:15:21.02#ibcon#[27=AT02-04\r\n] 2006.176.08:15:21.02#ibcon#*before write, iclass 30, count 2 2006.176.08:15:21.02#ibcon#enter sib2, iclass 30, count 2 2006.176.08:15:21.02#ibcon#flushed, iclass 30, count 2 2006.176.08:15:21.02#ibcon#about to write, iclass 30, count 2 2006.176.08:15:21.02#ibcon#wrote, iclass 30, count 2 2006.176.08:15:21.02#ibcon#about to read 3, iclass 30, count 2 2006.176.08:15:21.05#ibcon#read 3, iclass 30, count 2 2006.176.08:15:21.05#ibcon#about to read 4, iclass 30, count 2 2006.176.08:15:21.05#ibcon#read 4, iclass 30, count 2 2006.176.08:15:21.05#ibcon#about to read 5, iclass 30, count 2 2006.176.08:15:21.05#ibcon#read 5, iclass 30, count 2 2006.176.08:15:21.05#ibcon#about to read 6, iclass 30, count 2 2006.176.08:15:21.05#ibcon#read 6, iclass 30, count 2 2006.176.08:15:21.05#ibcon#end of sib2, iclass 30, count 2 2006.176.08:15:21.05#ibcon#*after write, iclass 30, count 2 2006.176.08:15:21.05#ibcon#*before return 0, iclass 30, count 2 2006.176.08:15:21.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:15:21.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:15:21.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.08:15:21.05#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:21.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:15:21.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:15:21.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:15:21.17#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:15:21.17#ibcon#first serial, iclass 30, count 0 2006.176.08:15:21.17#ibcon#enter sib2, iclass 30, count 0 2006.176.08:15:21.17#ibcon#flushed, iclass 30, count 0 2006.176.08:15:21.17#ibcon#about to write, iclass 30, count 0 2006.176.08:15:21.17#ibcon#wrote, iclass 30, count 0 2006.176.08:15:21.17#ibcon#about to read 3, iclass 30, count 0 2006.176.08:15:21.19#ibcon#read 3, iclass 30, count 0 2006.176.08:15:21.19#ibcon#about to read 4, iclass 30, count 0 2006.176.08:15:21.19#ibcon#read 4, iclass 30, count 0 2006.176.08:15:21.19#ibcon#about to read 5, iclass 30, count 0 2006.176.08:15:21.19#ibcon#read 5, iclass 30, count 0 2006.176.08:15:21.19#ibcon#about to read 6, iclass 30, count 0 2006.176.08:15:21.19#ibcon#read 6, iclass 30, count 0 2006.176.08:15:21.19#ibcon#end of sib2, iclass 30, count 0 2006.176.08:15:21.19#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:15:21.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:15:21.19#ibcon#[27=USB\r\n] 2006.176.08:15:21.19#ibcon#*before write, iclass 30, count 0 2006.176.08:15:21.19#ibcon#enter sib2, iclass 30, count 0 2006.176.08:15:21.19#ibcon#flushed, iclass 30, count 0 2006.176.08:15:21.19#ibcon#about to write, iclass 30, count 0 2006.176.08:15:21.19#ibcon#wrote, iclass 30, count 0 2006.176.08:15:21.19#ibcon#about to read 3, iclass 30, count 0 2006.176.08:15:21.22#ibcon#read 3, iclass 30, count 0 2006.176.08:15:21.22#ibcon#about to read 4, iclass 30, count 0 2006.176.08:15:21.22#ibcon#read 4, iclass 30, count 0 2006.176.08:15:21.22#ibcon#about to read 5, iclass 30, count 0 2006.176.08:15:21.22#ibcon#read 5, iclass 30, count 0 2006.176.08:15:21.22#ibcon#about to read 6, iclass 30, count 0 2006.176.08:15:21.22#ibcon#read 6, iclass 30, count 0 2006.176.08:15:21.22#ibcon#end of sib2, iclass 30, count 0 2006.176.08:15:21.22#ibcon#*after write, iclass 30, count 0 2006.176.08:15:21.22#ibcon#*before return 0, iclass 30, count 0 2006.176.08:15:21.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:15:21.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:15:21.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:15:21.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:15:21.22$vc4f8/vblo=3,656.99 2006.176.08:15:21.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.08:15:21.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.08:15:21.22#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:21.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:15:21.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:15:21.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:15:21.22#ibcon#enter wrdev, iclass 32, count 0 2006.176.08:15:21.22#ibcon#first serial, iclass 32, count 0 2006.176.08:15:21.22#ibcon#enter sib2, iclass 32, count 0 2006.176.08:15:21.22#ibcon#flushed, iclass 32, count 0 2006.176.08:15:21.22#ibcon#about to write, iclass 32, count 0 2006.176.08:15:21.22#ibcon#wrote, iclass 32, count 0 2006.176.08:15:21.22#ibcon#about to read 3, iclass 32, count 0 2006.176.08:15:21.24#ibcon#read 3, iclass 32, count 0 2006.176.08:15:21.24#ibcon#about to read 4, iclass 32, count 0 2006.176.08:15:21.24#ibcon#read 4, iclass 32, count 0 2006.176.08:15:21.24#ibcon#about to read 5, iclass 32, count 0 2006.176.08:15:21.24#ibcon#read 5, iclass 32, count 0 2006.176.08:15:21.24#ibcon#about to read 6, iclass 32, count 0 2006.176.08:15:21.24#ibcon#read 6, iclass 32, count 0 2006.176.08:15:21.24#ibcon#end of sib2, iclass 32, count 0 2006.176.08:15:21.24#ibcon#*mode == 0, iclass 32, count 0 2006.176.08:15:21.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.08:15:21.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:15:21.24#ibcon#*before write, iclass 32, count 0 2006.176.08:15:21.24#ibcon#enter sib2, iclass 32, count 0 2006.176.08:15:21.24#ibcon#flushed, iclass 32, count 0 2006.176.08:15:21.24#ibcon#about to write, iclass 32, count 0 2006.176.08:15:21.24#ibcon#wrote, iclass 32, count 0 2006.176.08:15:21.24#ibcon#about to read 3, iclass 32, count 0 2006.176.08:15:21.28#ibcon#read 3, iclass 32, count 0 2006.176.08:15:21.28#ibcon#about to read 4, iclass 32, count 0 2006.176.08:15:21.28#ibcon#read 4, iclass 32, count 0 2006.176.08:15:21.28#ibcon#about to read 5, iclass 32, count 0 2006.176.08:15:21.28#ibcon#read 5, iclass 32, count 0 2006.176.08:15:21.28#ibcon#about to read 6, iclass 32, count 0 2006.176.08:15:21.28#ibcon#read 6, iclass 32, count 0 2006.176.08:15:21.28#ibcon#end of sib2, iclass 32, count 0 2006.176.08:15:21.28#ibcon#*after write, iclass 32, count 0 2006.176.08:15:21.28#ibcon#*before return 0, iclass 32, count 0 2006.176.08:15:21.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:15:21.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:15:21.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.08:15:21.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.08:15:21.28$vc4f8/vb=3,4 2006.176.08:15:21.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.08:15:21.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.08:15:21.28#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:21.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:15:21.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:15:21.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:15:21.34#ibcon#enter wrdev, iclass 34, count 2 2006.176.08:15:21.34#ibcon#first serial, iclass 34, count 2 2006.176.08:15:21.34#ibcon#enter sib2, iclass 34, count 2 2006.176.08:15:21.34#ibcon#flushed, iclass 34, count 2 2006.176.08:15:21.34#ibcon#about to write, iclass 34, count 2 2006.176.08:15:21.34#ibcon#wrote, iclass 34, count 2 2006.176.08:15:21.34#ibcon#about to read 3, iclass 34, count 2 2006.176.08:15:21.36#ibcon#read 3, iclass 34, count 2 2006.176.08:15:21.36#ibcon#about to read 4, iclass 34, count 2 2006.176.08:15:21.36#ibcon#read 4, iclass 34, count 2 2006.176.08:15:21.36#ibcon#about to read 5, iclass 34, count 2 2006.176.08:15:21.36#ibcon#read 5, iclass 34, count 2 2006.176.08:15:21.36#ibcon#about to read 6, iclass 34, count 2 2006.176.08:15:21.36#ibcon#read 6, iclass 34, count 2 2006.176.08:15:21.36#ibcon#end of sib2, iclass 34, count 2 2006.176.08:15:21.36#ibcon#*mode == 0, iclass 34, count 2 2006.176.08:15:21.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.08:15:21.36#ibcon#[27=AT03-04\r\n] 2006.176.08:15:21.36#ibcon#*before write, iclass 34, count 2 2006.176.08:15:21.36#ibcon#enter sib2, iclass 34, count 2 2006.176.08:15:21.36#ibcon#flushed, iclass 34, count 2 2006.176.08:15:21.36#ibcon#about to write, iclass 34, count 2 2006.176.08:15:21.36#ibcon#wrote, iclass 34, count 2 2006.176.08:15:21.36#ibcon#about to read 3, iclass 34, count 2 2006.176.08:15:21.39#ibcon#read 3, iclass 34, count 2 2006.176.08:15:21.39#ibcon#about to read 4, iclass 34, count 2 2006.176.08:15:21.39#ibcon#read 4, iclass 34, count 2 2006.176.08:15:21.39#ibcon#about to read 5, iclass 34, count 2 2006.176.08:15:21.39#ibcon#read 5, iclass 34, count 2 2006.176.08:15:21.39#ibcon#about to read 6, iclass 34, count 2 2006.176.08:15:21.39#ibcon#read 6, iclass 34, count 2 2006.176.08:15:21.39#ibcon#end of sib2, iclass 34, count 2 2006.176.08:15:21.39#ibcon#*after write, iclass 34, count 2 2006.176.08:15:21.39#ibcon#*before return 0, iclass 34, count 2 2006.176.08:15:21.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:15:21.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:15:21.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.08:15:21.39#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:21.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:15:21.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:15:21.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:15:21.51#ibcon#enter wrdev, iclass 34, count 0 2006.176.08:15:21.51#ibcon#first serial, iclass 34, count 0 2006.176.08:15:21.51#ibcon#enter sib2, iclass 34, count 0 2006.176.08:15:21.51#ibcon#flushed, iclass 34, count 0 2006.176.08:15:21.51#ibcon#about to write, iclass 34, count 0 2006.176.08:15:21.51#ibcon#wrote, iclass 34, count 0 2006.176.08:15:21.51#ibcon#about to read 3, iclass 34, count 0 2006.176.08:15:21.53#ibcon#read 3, iclass 34, count 0 2006.176.08:15:21.53#ibcon#about to read 4, iclass 34, count 0 2006.176.08:15:21.53#ibcon#read 4, iclass 34, count 0 2006.176.08:15:21.53#ibcon#about to read 5, iclass 34, count 0 2006.176.08:15:21.53#ibcon#read 5, iclass 34, count 0 2006.176.08:15:21.53#ibcon#about to read 6, iclass 34, count 0 2006.176.08:15:21.53#ibcon#read 6, iclass 34, count 0 2006.176.08:15:21.53#ibcon#end of sib2, iclass 34, count 0 2006.176.08:15:21.53#ibcon#*mode == 0, iclass 34, count 0 2006.176.08:15:21.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.08:15:21.53#ibcon#[27=USB\r\n] 2006.176.08:15:21.53#ibcon#*before write, iclass 34, count 0 2006.176.08:15:21.53#ibcon#enter sib2, iclass 34, count 0 2006.176.08:15:21.53#ibcon#flushed, iclass 34, count 0 2006.176.08:15:21.53#ibcon#about to write, iclass 34, count 0 2006.176.08:15:21.53#ibcon#wrote, iclass 34, count 0 2006.176.08:15:21.53#ibcon#about to read 3, iclass 34, count 0 2006.176.08:15:21.56#ibcon#read 3, iclass 34, count 0 2006.176.08:15:21.56#ibcon#about to read 4, iclass 34, count 0 2006.176.08:15:21.56#ibcon#read 4, iclass 34, count 0 2006.176.08:15:21.56#ibcon#about to read 5, iclass 34, count 0 2006.176.08:15:21.56#ibcon#read 5, iclass 34, count 0 2006.176.08:15:21.56#ibcon#about to read 6, iclass 34, count 0 2006.176.08:15:21.56#ibcon#read 6, iclass 34, count 0 2006.176.08:15:21.56#ibcon#end of sib2, iclass 34, count 0 2006.176.08:15:21.56#ibcon#*after write, iclass 34, count 0 2006.176.08:15:21.56#ibcon#*before return 0, iclass 34, count 0 2006.176.08:15:21.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:15:21.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:15:21.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.08:15:21.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.08:15:21.56$vc4f8/vblo=4,712.99 2006.176.08:15:21.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.08:15:21.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.08:15:21.56#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:21.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:21.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:21.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:21.56#ibcon#enter wrdev, iclass 36, count 0 2006.176.08:15:21.56#ibcon#first serial, iclass 36, count 0 2006.176.08:15:21.56#ibcon#enter sib2, iclass 36, count 0 2006.176.08:15:21.56#ibcon#flushed, iclass 36, count 0 2006.176.08:15:21.56#ibcon#about to write, iclass 36, count 0 2006.176.08:15:21.56#ibcon#wrote, iclass 36, count 0 2006.176.08:15:21.56#ibcon#about to read 3, iclass 36, count 0 2006.176.08:15:21.58#ibcon#read 3, iclass 36, count 0 2006.176.08:15:21.58#ibcon#about to read 4, iclass 36, count 0 2006.176.08:15:21.58#ibcon#read 4, iclass 36, count 0 2006.176.08:15:21.58#ibcon#about to read 5, iclass 36, count 0 2006.176.08:15:21.58#ibcon#read 5, iclass 36, count 0 2006.176.08:15:21.58#ibcon#about to read 6, iclass 36, count 0 2006.176.08:15:21.58#ibcon#read 6, iclass 36, count 0 2006.176.08:15:21.58#ibcon#end of sib2, iclass 36, count 0 2006.176.08:15:21.58#ibcon#*mode == 0, iclass 36, count 0 2006.176.08:15:21.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.08:15:21.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:15:21.58#ibcon#*before write, iclass 36, count 0 2006.176.08:15:21.58#ibcon#enter sib2, iclass 36, count 0 2006.176.08:15:21.58#ibcon#flushed, iclass 36, count 0 2006.176.08:15:21.58#ibcon#about to write, iclass 36, count 0 2006.176.08:15:21.58#ibcon#wrote, iclass 36, count 0 2006.176.08:15:21.58#ibcon#about to read 3, iclass 36, count 0 2006.176.08:15:21.62#ibcon#read 3, iclass 36, count 0 2006.176.08:15:21.62#ibcon#about to read 4, iclass 36, count 0 2006.176.08:15:21.62#ibcon#read 4, iclass 36, count 0 2006.176.08:15:21.62#ibcon#about to read 5, iclass 36, count 0 2006.176.08:15:21.62#ibcon#read 5, iclass 36, count 0 2006.176.08:15:21.62#ibcon#about to read 6, iclass 36, count 0 2006.176.08:15:21.62#ibcon#read 6, iclass 36, count 0 2006.176.08:15:21.62#ibcon#end of sib2, iclass 36, count 0 2006.176.08:15:21.62#ibcon#*after write, iclass 36, count 0 2006.176.08:15:21.62#ibcon#*before return 0, iclass 36, count 0 2006.176.08:15:21.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:21.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:15:21.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.08:15:21.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.08:15:21.62$vc4f8/vb=4,4 2006.176.08:15:21.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.08:15:21.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.08:15:21.62#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:21.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:21.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:21.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:21.68#ibcon#enter wrdev, iclass 38, count 2 2006.176.08:15:21.68#ibcon#first serial, iclass 38, count 2 2006.176.08:15:21.68#ibcon#enter sib2, iclass 38, count 2 2006.176.08:15:21.68#ibcon#flushed, iclass 38, count 2 2006.176.08:15:21.68#ibcon#about to write, iclass 38, count 2 2006.176.08:15:21.68#ibcon#wrote, iclass 38, count 2 2006.176.08:15:21.68#ibcon#about to read 3, iclass 38, count 2 2006.176.08:15:21.70#ibcon#read 3, iclass 38, count 2 2006.176.08:15:21.70#ibcon#about to read 4, iclass 38, count 2 2006.176.08:15:21.70#ibcon#read 4, iclass 38, count 2 2006.176.08:15:21.70#ibcon#about to read 5, iclass 38, count 2 2006.176.08:15:21.70#ibcon#read 5, iclass 38, count 2 2006.176.08:15:21.70#ibcon#about to read 6, iclass 38, count 2 2006.176.08:15:21.70#ibcon#read 6, iclass 38, count 2 2006.176.08:15:21.70#ibcon#end of sib2, iclass 38, count 2 2006.176.08:15:21.70#ibcon#*mode == 0, iclass 38, count 2 2006.176.08:15:21.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.08:15:21.70#ibcon#[27=AT04-04\r\n] 2006.176.08:15:21.70#ibcon#*before write, iclass 38, count 2 2006.176.08:15:21.70#ibcon#enter sib2, iclass 38, count 2 2006.176.08:15:21.70#ibcon#flushed, iclass 38, count 2 2006.176.08:15:21.70#ibcon#about to write, iclass 38, count 2 2006.176.08:15:21.70#ibcon#wrote, iclass 38, count 2 2006.176.08:15:21.70#ibcon#about to read 3, iclass 38, count 2 2006.176.08:15:21.73#ibcon#read 3, iclass 38, count 2 2006.176.08:15:21.73#ibcon#about to read 4, iclass 38, count 2 2006.176.08:15:21.73#ibcon#read 4, iclass 38, count 2 2006.176.08:15:21.73#ibcon#about to read 5, iclass 38, count 2 2006.176.08:15:21.73#ibcon#read 5, iclass 38, count 2 2006.176.08:15:21.73#ibcon#about to read 6, iclass 38, count 2 2006.176.08:15:21.73#ibcon#read 6, iclass 38, count 2 2006.176.08:15:21.73#ibcon#end of sib2, iclass 38, count 2 2006.176.08:15:21.73#ibcon#*after write, iclass 38, count 2 2006.176.08:15:21.73#ibcon#*before return 0, iclass 38, count 2 2006.176.08:15:21.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:21.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:15:21.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.08:15:21.73#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:21.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:21.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:21.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:21.85#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:15:21.85#ibcon#first serial, iclass 38, count 0 2006.176.08:15:21.85#ibcon#enter sib2, iclass 38, count 0 2006.176.08:15:21.85#ibcon#flushed, iclass 38, count 0 2006.176.08:15:21.85#ibcon#about to write, iclass 38, count 0 2006.176.08:15:21.85#ibcon#wrote, iclass 38, count 0 2006.176.08:15:21.85#ibcon#about to read 3, iclass 38, count 0 2006.176.08:15:21.87#ibcon#read 3, iclass 38, count 0 2006.176.08:15:21.87#ibcon#about to read 4, iclass 38, count 0 2006.176.08:15:21.87#ibcon#read 4, iclass 38, count 0 2006.176.08:15:21.87#ibcon#about to read 5, iclass 38, count 0 2006.176.08:15:21.87#ibcon#read 5, iclass 38, count 0 2006.176.08:15:21.87#ibcon#about to read 6, iclass 38, count 0 2006.176.08:15:21.87#ibcon#read 6, iclass 38, count 0 2006.176.08:15:21.87#ibcon#end of sib2, iclass 38, count 0 2006.176.08:15:21.87#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:15:21.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:15:21.87#ibcon#[27=USB\r\n] 2006.176.08:15:21.87#ibcon#*before write, iclass 38, count 0 2006.176.08:15:21.87#ibcon#enter sib2, iclass 38, count 0 2006.176.08:15:21.87#ibcon#flushed, iclass 38, count 0 2006.176.08:15:21.87#ibcon#about to write, iclass 38, count 0 2006.176.08:15:21.87#ibcon#wrote, iclass 38, count 0 2006.176.08:15:21.87#ibcon#about to read 3, iclass 38, count 0 2006.176.08:15:21.90#ibcon#read 3, iclass 38, count 0 2006.176.08:15:21.90#ibcon#about to read 4, iclass 38, count 0 2006.176.08:15:21.90#ibcon#read 4, iclass 38, count 0 2006.176.08:15:21.90#ibcon#about to read 5, iclass 38, count 0 2006.176.08:15:21.90#ibcon#read 5, iclass 38, count 0 2006.176.08:15:21.90#ibcon#about to read 6, iclass 38, count 0 2006.176.08:15:21.90#ibcon#read 6, iclass 38, count 0 2006.176.08:15:21.90#ibcon#end of sib2, iclass 38, count 0 2006.176.08:15:21.90#ibcon#*after write, iclass 38, count 0 2006.176.08:15:21.90#ibcon#*before return 0, iclass 38, count 0 2006.176.08:15:21.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:21.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:15:21.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:15:21.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:15:21.90$vc4f8/vblo=5,744.99 2006.176.08:15:21.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.08:15:21.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.08:15:21.90#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:21.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:21.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:21.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:21.90#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:15:21.90#ibcon#first serial, iclass 40, count 0 2006.176.08:15:21.90#ibcon#enter sib2, iclass 40, count 0 2006.176.08:15:21.90#ibcon#flushed, iclass 40, count 0 2006.176.08:15:21.90#ibcon#about to write, iclass 40, count 0 2006.176.08:15:21.90#ibcon#wrote, iclass 40, count 0 2006.176.08:15:21.90#ibcon#about to read 3, iclass 40, count 0 2006.176.08:15:21.92#ibcon#read 3, iclass 40, count 0 2006.176.08:15:21.92#ibcon#about to read 4, iclass 40, count 0 2006.176.08:15:21.92#ibcon#read 4, iclass 40, count 0 2006.176.08:15:21.92#ibcon#about to read 5, iclass 40, count 0 2006.176.08:15:21.92#ibcon#read 5, iclass 40, count 0 2006.176.08:15:21.92#ibcon#about to read 6, iclass 40, count 0 2006.176.08:15:21.92#ibcon#read 6, iclass 40, count 0 2006.176.08:15:21.92#ibcon#end of sib2, iclass 40, count 0 2006.176.08:15:21.92#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:15:21.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:15:21.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:15:21.92#ibcon#*before write, iclass 40, count 0 2006.176.08:15:21.92#ibcon#enter sib2, iclass 40, count 0 2006.176.08:15:21.92#ibcon#flushed, iclass 40, count 0 2006.176.08:15:21.92#ibcon#about to write, iclass 40, count 0 2006.176.08:15:21.92#ibcon#wrote, iclass 40, count 0 2006.176.08:15:21.92#ibcon#about to read 3, iclass 40, count 0 2006.176.08:15:21.96#ibcon#read 3, iclass 40, count 0 2006.176.08:15:21.96#ibcon#about to read 4, iclass 40, count 0 2006.176.08:15:21.96#ibcon#read 4, iclass 40, count 0 2006.176.08:15:21.96#ibcon#about to read 5, iclass 40, count 0 2006.176.08:15:21.96#ibcon#read 5, iclass 40, count 0 2006.176.08:15:21.96#ibcon#about to read 6, iclass 40, count 0 2006.176.08:15:21.96#ibcon#read 6, iclass 40, count 0 2006.176.08:15:21.96#ibcon#end of sib2, iclass 40, count 0 2006.176.08:15:21.96#ibcon#*after write, iclass 40, count 0 2006.176.08:15:21.96#ibcon#*before return 0, iclass 40, count 0 2006.176.08:15:21.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:21.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:15:21.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:15:21.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:15:21.96$vc4f8/vb=5,4 2006.176.08:15:21.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.08:15:21.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.08:15:21.96#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:21.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:22.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:22.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:22.02#ibcon#enter wrdev, iclass 4, count 2 2006.176.08:15:22.02#ibcon#first serial, iclass 4, count 2 2006.176.08:15:22.02#ibcon#enter sib2, iclass 4, count 2 2006.176.08:15:22.02#ibcon#flushed, iclass 4, count 2 2006.176.08:15:22.02#ibcon#about to write, iclass 4, count 2 2006.176.08:15:22.02#ibcon#wrote, iclass 4, count 2 2006.176.08:15:22.02#ibcon#about to read 3, iclass 4, count 2 2006.176.08:15:22.04#ibcon#read 3, iclass 4, count 2 2006.176.08:15:22.04#ibcon#about to read 4, iclass 4, count 2 2006.176.08:15:22.04#ibcon#read 4, iclass 4, count 2 2006.176.08:15:22.04#ibcon#about to read 5, iclass 4, count 2 2006.176.08:15:22.04#ibcon#read 5, iclass 4, count 2 2006.176.08:15:22.04#ibcon#about to read 6, iclass 4, count 2 2006.176.08:15:22.04#ibcon#read 6, iclass 4, count 2 2006.176.08:15:22.04#ibcon#end of sib2, iclass 4, count 2 2006.176.08:15:22.04#ibcon#*mode == 0, iclass 4, count 2 2006.176.08:15:22.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.08:15:22.04#ibcon#[27=AT05-04\r\n] 2006.176.08:15:22.04#ibcon#*before write, iclass 4, count 2 2006.176.08:15:22.04#ibcon#enter sib2, iclass 4, count 2 2006.176.08:15:22.04#ibcon#flushed, iclass 4, count 2 2006.176.08:15:22.04#ibcon#about to write, iclass 4, count 2 2006.176.08:15:22.04#ibcon#wrote, iclass 4, count 2 2006.176.08:15:22.04#ibcon#about to read 3, iclass 4, count 2 2006.176.08:15:22.07#ibcon#read 3, iclass 4, count 2 2006.176.08:15:22.07#ibcon#about to read 4, iclass 4, count 2 2006.176.08:15:22.07#ibcon#read 4, iclass 4, count 2 2006.176.08:15:22.07#ibcon#about to read 5, iclass 4, count 2 2006.176.08:15:22.07#ibcon#read 5, iclass 4, count 2 2006.176.08:15:22.07#ibcon#about to read 6, iclass 4, count 2 2006.176.08:15:22.07#ibcon#read 6, iclass 4, count 2 2006.176.08:15:22.07#ibcon#end of sib2, iclass 4, count 2 2006.176.08:15:22.07#ibcon#*after write, iclass 4, count 2 2006.176.08:15:22.07#ibcon#*before return 0, iclass 4, count 2 2006.176.08:15:22.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:22.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:15:22.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.08:15:22.07#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:22.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:22.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:22.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:22.19#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:15:22.19#ibcon#first serial, iclass 4, count 0 2006.176.08:15:22.19#ibcon#enter sib2, iclass 4, count 0 2006.176.08:15:22.19#ibcon#flushed, iclass 4, count 0 2006.176.08:15:22.19#ibcon#about to write, iclass 4, count 0 2006.176.08:15:22.19#ibcon#wrote, iclass 4, count 0 2006.176.08:15:22.19#ibcon#about to read 3, iclass 4, count 0 2006.176.08:15:22.21#ibcon#read 3, iclass 4, count 0 2006.176.08:15:22.21#ibcon#about to read 4, iclass 4, count 0 2006.176.08:15:22.21#ibcon#read 4, iclass 4, count 0 2006.176.08:15:22.21#ibcon#about to read 5, iclass 4, count 0 2006.176.08:15:22.21#ibcon#read 5, iclass 4, count 0 2006.176.08:15:22.21#ibcon#about to read 6, iclass 4, count 0 2006.176.08:15:22.21#ibcon#read 6, iclass 4, count 0 2006.176.08:15:22.21#ibcon#end of sib2, iclass 4, count 0 2006.176.08:15:22.21#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:15:22.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:15:22.21#ibcon#[27=USB\r\n] 2006.176.08:15:22.21#ibcon#*before write, iclass 4, count 0 2006.176.08:15:22.21#ibcon#enter sib2, iclass 4, count 0 2006.176.08:15:22.21#ibcon#flushed, iclass 4, count 0 2006.176.08:15:22.21#ibcon#about to write, iclass 4, count 0 2006.176.08:15:22.21#ibcon#wrote, iclass 4, count 0 2006.176.08:15:22.21#ibcon#about to read 3, iclass 4, count 0 2006.176.08:15:22.24#ibcon#read 3, iclass 4, count 0 2006.176.08:15:22.24#ibcon#about to read 4, iclass 4, count 0 2006.176.08:15:22.24#ibcon#read 4, iclass 4, count 0 2006.176.08:15:22.24#ibcon#about to read 5, iclass 4, count 0 2006.176.08:15:22.24#ibcon#read 5, iclass 4, count 0 2006.176.08:15:22.24#ibcon#about to read 6, iclass 4, count 0 2006.176.08:15:22.24#ibcon#read 6, iclass 4, count 0 2006.176.08:15:22.24#ibcon#end of sib2, iclass 4, count 0 2006.176.08:15:22.24#ibcon#*after write, iclass 4, count 0 2006.176.08:15:22.24#ibcon#*before return 0, iclass 4, count 0 2006.176.08:15:22.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:22.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:15:22.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:15:22.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:15:22.24$vc4f8/vblo=6,752.99 2006.176.08:15:22.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.08:15:22.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.08:15:22.24#ibcon#ireg 17 cls_cnt 0 2006.176.08:15:22.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:22.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:22.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:22.24#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:15:22.24#ibcon#first serial, iclass 6, count 0 2006.176.08:15:22.24#ibcon#enter sib2, iclass 6, count 0 2006.176.08:15:22.24#ibcon#flushed, iclass 6, count 0 2006.176.08:15:22.24#ibcon#about to write, iclass 6, count 0 2006.176.08:15:22.24#ibcon#wrote, iclass 6, count 0 2006.176.08:15:22.24#ibcon#about to read 3, iclass 6, count 0 2006.176.08:15:22.26#ibcon#read 3, iclass 6, count 0 2006.176.08:15:22.26#ibcon#about to read 4, iclass 6, count 0 2006.176.08:15:22.26#ibcon#read 4, iclass 6, count 0 2006.176.08:15:22.26#ibcon#about to read 5, iclass 6, count 0 2006.176.08:15:22.26#ibcon#read 5, iclass 6, count 0 2006.176.08:15:22.26#ibcon#about to read 6, iclass 6, count 0 2006.176.08:15:22.26#ibcon#read 6, iclass 6, count 0 2006.176.08:15:22.26#ibcon#end of sib2, iclass 6, count 0 2006.176.08:15:22.26#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:15:22.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:15:22.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:15:22.26#ibcon#*before write, iclass 6, count 0 2006.176.08:15:22.26#ibcon#enter sib2, iclass 6, count 0 2006.176.08:15:22.26#ibcon#flushed, iclass 6, count 0 2006.176.08:15:22.26#ibcon#about to write, iclass 6, count 0 2006.176.08:15:22.26#ibcon#wrote, iclass 6, count 0 2006.176.08:15:22.26#ibcon#about to read 3, iclass 6, count 0 2006.176.08:15:22.30#ibcon#read 3, iclass 6, count 0 2006.176.08:15:22.30#ibcon#about to read 4, iclass 6, count 0 2006.176.08:15:22.30#ibcon#read 4, iclass 6, count 0 2006.176.08:15:22.30#ibcon#about to read 5, iclass 6, count 0 2006.176.08:15:22.30#ibcon#read 5, iclass 6, count 0 2006.176.08:15:22.30#ibcon#about to read 6, iclass 6, count 0 2006.176.08:15:22.30#ibcon#read 6, iclass 6, count 0 2006.176.08:15:22.30#ibcon#end of sib2, iclass 6, count 0 2006.176.08:15:22.30#ibcon#*after write, iclass 6, count 0 2006.176.08:15:22.30#ibcon#*before return 0, iclass 6, count 0 2006.176.08:15:22.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:22.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:15:22.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:15:22.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:15:22.30$vc4f8/vb=6,4 2006.176.08:15:22.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.08:15:22.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.08:15:22.30#ibcon#ireg 11 cls_cnt 2 2006.176.08:15:22.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:22.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:22.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:22.36#ibcon#enter wrdev, iclass 10, count 2 2006.176.08:15:22.36#ibcon#first serial, iclass 10, count 2 2006.176.08:15:22.36#ibcon#enter sib2, iclass 10, count 2 2006.176.08:15:22.36#ibcon#flushed, iclass 10, count 2 2006.176.08:15:22.36#ibcon#about to write, iclass 10, count 2 2006.176.08:15:22.36#ibcon#wrote, iclass 10, count 2 2006.176.08:15:22.36#ibcon#about to read 3, iclass 10, count 2 2006.176.08:15:22.38#ibcon#read 3, iclass 10, count 2 2006.176.08:15:22.38#ibcon#about to read 4, iclass 10, count 2 2006.176.08:15:22.38#ibcon#read 4, iclass 10, count 2 2006.176.08:15:22.38#ibcon#about to read 5, iclass 10, count 2 2006.176.08:15:22.38#ibcon#read 5, iclass 10, count 2 2006.176.08:15:22.38#ibcon#about to read 6, iclass 10, count 2 2006.176.08:15:22.38#ibcon#read 6, iclass 10, count 2 2006.176.08:15:22.38#ibcon#end of sib2, iclass 10, count 2 2006.176.08:15:22.38#ibcon#*mode == 0, iclass 10, count 2 2006.176.08:15:22.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.08:15:22.38#ibcon#[27=AT06-04\r\n] 2006.176.08:15:22.38#ibcon#*before write, iclass 10, count 2 2006.176.08:15:22.38#ibcon#enter sib2, iclass 10, count 2 2006.176.08:15:22.38#ibcon#flushed, iclass 10, count 2 2006.176.08:15:22.38#ibcon#about to write, iclass 10, count 2 2006.176.08:15:22.38#ibcon#wrote, iclass 10, count 2 2006.176.08:15:22.38#ibcon#about to read 3, iclass 10, count 2 2006.176.08:15:22.41#ibcon#read 3, iclass 10, count 2 2006.176.08:15:22.41#ibcon#about to read 4, iclass 10, count 2 2006.176.08:15:22.41#ibcon#read 4, iclass 10, count 2 2006.176.08:15:22.41#ibcon#about to read 5, iclass 10, count 2 2006.176.08:15:22.41#ibcon#read 5, iclass 10, count 2 2006.176.08:15:22.41#ibcon#about to read 6, iclass 10, count 2 2006.176.08:15:22.41#ibcon#read 6, iclass 10, count 2 2006.176.08:15:22.41#ibcon#end of sib2, iclass 10, count 2 2006.176.08:15:22.41#ibcon#*after write, iclass 10, count 2 2006.176.08:15:22.41#ibcon#*before return 0, iclass 10, count 2 2006.176.08:15:22.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:22.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:15:22.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.08:15:22.41#ibcon#ireg 7 cls_cnt 0 2006.176.08:15:22.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:22.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:22.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:22.53#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:15:22.53#ibcon#first serial, iclass 10, count 0 2006.176.08:15:22.53#ibcon#enter sib2, iclass 10, count 0 2006.176.08:15:22.53#ibcon#flushed, iclass 10, count 0 2006.176.08:15:22.53#ibcon#about to write, iclass 10, count 0 2006.176.08:15:22.53#ibcon#wrote, iclass 10, count 0 2006.176.08:15:22.53#ibcon#about to read 3, iclass 10, count 0 2006.176.08:15:22.55#ibcon#read 3, iclass 10, count 0 2006.176.08:15:22.55#ibcon#about to read 4, iclass 10, count 0 2006.176.08:15:22.55#ibcon#read 4, iclass 10, count 0 2006.176.08:15:22.55#ibcon#about to read 5, iclass 10, count 0 2006.176.08:15:22.55#ibcon#read 5, iclass 10, count 0 2006.176.08:15:22.55#ibcon#about to read 6, iclass 10, count 0 2006.176.08:15:22.55#ibcon#read 6, iclass 10, count 0 2006.176.08:15:22.55#ibcon#end of sib2, iclass 10, count 0 2006.176.08:15:22.55#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:15:22.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:15:22.55#ibcon#[27=USB\r\n] 2006.176.08:15:22.55#ibcon#*before write, iclass 10, count 0 2006.176.08:15:22.55#ibcon#enter sib2, iclass 10, count 0 2006.176.08:15:22.55#ibcon#flushed, iclass 10, count 0 2006.176.08:15:22.55#ibcon#about to write, iclass 10, count 0 2006.176.08:15:22.55#ibcon#wrote, iclass 10, count 0 2006.176.08:15:22.55#ibcon#about to read 3, iclass 10, count 0 2006.176.08:15:22.58#ibcon#read 3, iclass 10, count 0 2006.176.08:15:22.58#ibcon#about to read 4, iclass 10, count 0 2006.176.08:15:22.58#ibcon#read 4, iclass 10, count 0 2006.176.08:15:22.58#ibcon#about to read 5, iclass 10, count 0 2006.176.08:15:22.58#ibcon#read 5, iclass 10, count 0 2006.176.08:15:22.58#ibcon#about to read 6, iclass 10, count 0 2006.176.08:15:22.58#ibcon#read 6, iclass 10, count 0 2006.176.08:15:22.58#ibcon#end of sib2, iclass 10, count 0 2006.176.08:15:22.58#ibcon#*after write, iclass 10, count 0 2006.176.08:15:22.58#ibcon#*before return 0, iclass 10, count 0 2006.176.08:15:22.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:22.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:15:22.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:15:22.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:15:22.58$vc4f8/vabw=wide 2006.176.08:15:22.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.08:15:22.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.08:15:22.58#ibcon#ireg 8 cls_cnt 0 2006.176.08:15:22.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:22.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:22.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:22.58#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:15:22.58#ibcon#first serial, iclass 12, count 0 2006.176.08:15:22.58#ibcon#enter sib2, iclass 12, count 0 2006.176.08:15:22.58#ibcon#flushed, iclass 12, count 0 2006.176.08:15:22.58#ibcon#about to write, iclass 12, count 0 2006.176.08:15:22.58#ibcon#wrote, iclass 12, count 0 2006.176.08:15:22.58#ibcon#about to read 3, iclass 12, count 0 2006.176.08:15:22.60#ibcon#read 3, iclass 12, count 0 2006.176.08:15:22.60#ibcon#about to read 4, iclass 12, count 0 2006.176.08:15:22.60#ibcon#read 4, iclass 12, count 0 2006.176.08:15:22.60#ibcon#about to read 5, iclass 12, count 0 2006.176.08:15:22.60#ibcon#read 5, iclass 12, count 0 2006.176.08:15:22.60#ibcon#about to read 6, iclass 12, count 0 2006.176.08:15:22.60#ibcon#read 6, iclass 12, count 0 2006.176.08:15:22.60#ibcon#end of sib2, iclass 12, count 0 2006.176.08:15:22.60#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:15:22.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:15:22.60#ibcon#[25=BW32\r\n] 2006.176.08:15:22.60#ibcon#*before write, iclass 12, count 0 2006.176.08:15:22.60#ibcon#enter sib2, iclass 12, count 0 2006.176.08:15:22.60#ibcon#flushed, iclass 12, count 0 2006.176.08:15:22.60#ibcon#about to write, iclass 12, count 0 2006.176.08:15:22.60#ibcon#wrote, iclass 12, count 0 2006.176.08:15:22.60#ibcon#about to read 3, iclass 12, count 0 2006.176.08:15:22.63#ibcon#read 3, iclass 12, count 0 2006.176.08:15:22.63#ibcon#about to read 4, iclass 12, count 0 2006.176.08:15:22.63#ibcon#read 4, iclass 12, count 0 2006.176.08:15:22.63#ibcon#about to read 5, iclass 12, count 0 2006.176.08:15:22.63#ibcon#read 5, iclass 12, count 0 2006.176.08:15:22.63#ibcon#about to read 6, iclass 12, count 0 2006.176.08:15:22.63#ibcon#read 6, iclass 12, count 0 2006.176.08:15:22.63#ibcon#end of sib2, iclass 12, count 0 2006.176.08:15:22.63#ibcon#*after write, iclass 12, count 0 2006.176.08:15:22.63#ibcon#*before return 0, iclass 12, count 0 2006.176.08:15:22.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:22.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:15:22.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:15:22.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:15:22.63$vc4f8/vbbw=wide 2006.176.08:15:22.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.08:15:22.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.08:15:22.63#ibcon#ireg 8 cls_cnt 0 2006.176.08:15:22.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:15:22.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:15:22.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:15:22.70#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:15:22.70#ibcon#first serial, iclass 14, count 0 2006.176.08:15:22.70#ibcon#enter sib2, iclass 14, count 0 2006.176.08:15:22.70#ibcon#flushed, iclass 14, count 0 2006.176.08:15:22.70#ibcon#about to write, iclass 14, count 0 2006.176.08:15:22.70#ibcon#wrote, iclass 14, count 0 2006.176.08:15:22.70#ibcon#about to read 3, iclass 14, count 0 2006.176.08:15:22.72#ibcon#read 3, iclass 14, count 0 2006.176.08:15:22.72#ibcon#about to read 4, iclass 14, count 0 2006.176.08:15:22.72#ibcon#read 4, iclass 14, count 0 2006.176.08:15:22.72#ibcon#about to read 5, iclass 14, count 0 2006.176.08:15:22.72#ibcon#read 5, iclass 14, count 0 2006.176.08:15:22.72#ibcon#about to read 6, iclass 14, count 0 2006.176.08:15:22.72#ibcon#read 6, iclass 14, count 0 2006.176.08:15:22.72#ibcon#end of sib2, iclass 14, count 0 2006.176.08:15:22.72#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:15:22.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:15:22.72#ibcon#[27=BW32\r\n] 2006.176.08:15:22.72#ibcon#*before write, iclass 14, count 0 2006.176.08:15:22.72#ibcon#enter sib2, iclass 14, count 0 2006.176.08:15:22.72#ibcon#flushed, iclass 14, count 0 2006.176.08:15:22.72#ibcon#about to write, iclass 14, count 0 2006.176.08:15:22.72#ibcon#wrote, iclass 14, count 0 2006.176.08:15:22.72#ibcon#about to read 3, iclass 14, count 0 2006.176.08:15:22.75#ibcon#read 3, iclass 14, count 0 2006.176.08:15:22.75#ibcon#about to read 4, iclass 14, count 0 2006.176.08:15:22.75#ibcon#read 4, iclass 14, count 0 2006.176.08:15:22.75#ibcon#about to read 5, iclass 14, count 0 2006.176.08:15:22.75#ibcon#read 5, iclass 14, count 0 2006.176.08:15:22.75#ibcon#about to read 6, iclass 14, count 0 2006.176.08:15:22.75#ibcon#read 6, iclass 14, count 0 2006.176.08:15:22.75#ibcon#end of sib2, iclass 14, count 0 2006.176.08:15:22.75#ibcon#*after write, iclass 14, count 0 2006.176.08:15:22.75#ibcon#*before return 0, iclass 14, count 0 2006.176.08:15:22.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:15:22.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:15:22.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:15:22.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:15:22.75$4f8m12a/ifd4f 2006.176.08:15:22.75$ifd4f/lo= 2006.176.08:15:22.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:15:22.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:15:22.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:15:22.75$ifd4f/patch= 2006.176.08:15:22.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:15:22.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:15:22.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:15:22.75$4f8m12a/"form=m,16.000,1:2 2006.176.08:15:22.75$4f8m12a/"tpicd 2006.176.08:15:22.75$4f8m12a/echo=off 2006.176.08:15:22.75$4f8m12a/xlog=off 2006.176.08:15:22.75:!2006.176.08:15:50 2006.176.08:15:32.13#trakl#Source acquired 2006.176.08:15:34.13#flagr#flagr/antenna,acquired 2006.176.08:15:50.00:preob 2006.176.08:15:50.13/onsource/TRACKING 2006.176.08:15:50.13:!2006.176.08:16:00 2006.176.08:16:00.00:data_valid=on 2006.176.08:16:00.00:midob 2006.176.08:16:01.13/onsource/TRACKING 2006.176.08:16:01.13/wx/23.81,1008.6,92 2006.176.08:16:01.21/cable/+6.4939E-03 2006.176.08:16:02.30/va/01,08,usb,yes,28,30 2006.176.08:16:02.30/va/02,07,usb,yes,28,30 2006.176.08:16:02.30/va/03,06,usb,yes,30,30 2006.176.08:16:02.30/va/04,07,usb,yes,29,31 2006.176.08:16:02.30/va/05,07,usb,yes,31,33 2006.176.08:16:02.30/va/06,06,usb,yes,30,30 2006.176.08:16:02.30/va/07,06,usb,yes,30,30 2006.176.08:16:02.30/va/08,06,usb,yes,32,32 2006.176.08:16:02.53/valo/01,532.99,yes,locked 2006.176.08:16:02.53/valo/02,572.99,yes,locked 2006.176.08:16:02.53/valo/03,672.99,yes,locked 2006.176.08:16:02.53/valo/04,832.99,yes,locked 2006.176.08:16:02.53/valo/05,652.99,yes,locked 2006.176.08:16:02.53/valo/06,772.99,yes,locked 2006.176.08:16:02.53/valo/07,832.99,yes,locked 2006.176.08:16:02.53/valo/08,852.99,yes,locked 2006.176.08:16:03.62/vb/01,04,usb,yes,28,27 2006.176.08:16:03.62/vb/02,04,usb,yes,30,32 2006.176.08:16:03.62/vb/03,04,usb,yes,27,30 2006.176.08:16:03.62/vb/04,04,usb,yes,27,28 2006.176.08:16:03.62/vb/05,04,usb,yes,26,30 2006.176.08:16:03.62/vb/06,04,usb,yes,27,30 2006.176.08:16:03.62/vb/07,04,usb,yes,29,29 2006.176.08:16:03.62/vb/08,04,usb,yes,27,30 2006.176.08:16:03.86/vblo/01,632.99,yes,locked 2006.176.08:16:03.86/vblo/02,640.99,yes,locked 2006.176.08:16:03.86/vblo/03,656.99,yes,locked 2006.176.08:16:03.86/vblo/04,712.99,yes,locked 2006.176.08:16:03.86/vblo/05,744.99,yes,locked 2006.176.08:16:03.86/vblo/06,752.99,yes,locked 2006.176.08:16:03.86/vblo/07,734.99,yes,locked 2006.176.08:16:03.86/vblo/08,744.99,yes,locked 2006.176.08:16:04.01/vabw/8 2006.176.08:16:04.16/vbbw/8 2006.176.08:16:04.25/xfe/off,on,14.2 2006.176.08:16:04.63/ifatt/23,28,28,28 2006.176.08:16:05.07/fmout-gps/S +3.70E-07 2006.176.08:16:05.15:!2006.176.08:17:00 2006.176.08:17:00.00:data_valid=off 2006.176.08:17:00.00:postob 2006.176.08:17:00.22/cable/+6.4916E-03 2006.176.08:17:00.22/wx/23.80,1008.6,93 2006.176.08:17:01.07/fmout-gps/S +3.69E-07 2006.176.08:17:01.07:scan_name=176-0817,k06176,60 2006.176.08:17:01.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.176.08:17:01.14#flagr#flagr/antenna,new-source 2006.176.08:17:02.14:checkk5 2006.176.08:17:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:17:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:17:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:17:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:17:04.02/chk_obsdata//k5ts1/T1760816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:17:04.39/chk_obsdata//k5ts2/T1760816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:17:04.77/chk_obsdata//k5ts3/T1760816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:17:05.15/chk_obsdata//k5ts4/T1760816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:17:05.83/k5log//k5ts1_log_newline 2006.176.08:17:06.53/k5log//k5ts2_log_newline 2006.176.08:17:07.23/k5log//k5ts3_log_newline 2006.176.08:17:07.93/k5log//k5ts4_log_newline 2006.176.08:17:07.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:17:07.95:4f8m12a=2 2006.176.08:17:07.95$4f8m12a/echo=on 2006.176.08:17:07.95$4f8m12a/pcalon 2006.176.08:17:07.95$pcalon/"no phase cal control is implemented here 2006.176.08:17:07.95$4f8m12a/"tpicd=stop 2006.176.08:17:07.95$4f8m12a/vc4f8 2006.176.08:17:07.95$vc4f8/valo=1,532.99 2006.176.08:17:07.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.08:17:07.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.08:17:07.96#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:07.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:07.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:07.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:07.96#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:17:07.96#ibcon#first serial, iclass 21, count 0 2006.176.08:17:07.96#ibcon#enter sib2, iclass 21, count 0 2006.176.08:17:07.96#ibcon#flushed, iclass 21, count 0 2006.176.08:17:07.96#ibcon#about to write, iclass 21, count 0 2006.176.08:17:07.96#ibcon#wrote, iclass 21, count 0 2006.176.08:17:07.96#ibcon#about to read 3, iclass 21, count 0 2006.176.08:17:08.00#ibcon#read 3, iclass 21, count 0 2006.176.08:17:08.00#ibcon#about to read 4, iclass 21, count 0 2006.176.08:17:08.00#ibcon#read 4, iclass 21, count 0 2006.176.08:17:08.00#ibcon#about to read 5, iclass 21, count 0 2006.176.08:17:08.00#ibcon#read 5, iclass 21, count 0 2006.176.08:17:08.00#ibcon#about to read 6, iclass 21, count 0 2006.176.08:17:08.00#ibcon#read 6, iclass 21, count 0 2006.176.08:17:08.00#ibcon#end of sib2, iclass 21, count 0 2006.176.08:17:08.00#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:17:08.00#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:17:08.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:17:08.00#ibcon#*before write, iclass 21, count 0 2006.176.08:17:08.00#ibcon#enter sib2, iclass 21, count 0 2006.176.08:17:08.00#ibcon#flushed, iclass 21, count 0 2006.176.08:17:08.00#ibcon#about to write, iclass 21, count 0 2006.176.08:17:08.00#ibcon#wrote, iclass 21, count 0 2006.176.08:17:08.00#ibcon#about to read 3, iclass 21, count 0 2006.176.08:17:08.05#ibcon#read 3, iclass 21, count 0 2006.176.08:17:08.05#ibcon#about to read 4, iclass 21, count 0 2006.176.08:17:08.05#ibcon#read 4, iclass 21, count 0 2006.176.08:17:08.05#ibcon#about to read 5, iclass 21, count 0 2006.176.08:17:08.05#ibcon#read 5, iclass 21, count 0 2006.176.08:17:08.05#ibcon#about to read 6, iclass 21, count 0 2006.176.08:17:08.05#ibcon#read 6, iclass 21, count 0 2006.176.08:17:08.05#ibcon#end of sib2, iclass 21, count 0 2006.176.08:17:08.05#ibcon#*after write, iclass 21, count 0 2006.176.08:17:08.05#ibcon#*before return 0, iclass 21, count 0 2006.176.08:17:08.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:08.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:08.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:17:08.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:17:08.05$vc4f8/va=1,8 2006.176.08:17:08.05#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.08:17:08.05#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.08:17:08.05#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:08.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:08.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:08.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:08.05#ibcon#enter wrdev, iclass 23, count 2 2006.176.08:17:08.05#ibcon#first serial, iclass 23, count 2 2006.176.08:17:08.05#ibcon#enter sib2, iclass 23, count 2 2006.176.08:17:08.05#ibcon#flushed, iclass 23, count 2 2006.176.08:17:08.05#ibcon#about to write, iclass 23, count 2 2006.176.08:17:08.05#ibcon#wrote, iclass 23, count 2 2006.176.08:17:08.05#ibcon#about to read 3, iclass 23, count 2 2006.176.08:17:08.07#ibcon#read 3, iclass 23, count 2 2006.176.08:17:08.07#ibcon#about to read 4, iclass 23, count 2 2006.176.08:17:08.07#ibcon#read 4, iclass 23, count 2 2006.176.08:17:08.07#ibcon#about to read 5, iclass 23, count 2 2006.176.08:17:08.07#ibcon#read 5, iclass 23, count 2 2006.176.08:17:08.07#ibcon#about to read 6, iclass 23, count 2 2006.176.08:17:08.07#ibcon#read 6, iclass 23, count 2 2006.176.08:17:08.07#ibcon#end of sib2, iclass 23, count 2 2006.176.08:17:08.07#ibcon#*mode == 0, iclass 23, count 2 2006.176.08:17:08.07#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.08:17:08.07#ibcon#[25=AT01-08\r\n] 2006.176.08:17:08.07#ibcon#*before write, iclass 23, count 2 2006.176.08:17:08.07#ibcon#enter sib2, iclass 23, count 2 2006.176.08:17:08.07#ibcon#flushed, iclass 23, count 2 2006.176.08:17:08.07#ibcon#about to write, iclass 23, count 2 2006.176.08:17:08.07#ibcon#wrote, iclass 23, count 2 2006.176.08:17:08.07#ibcon#about to read 3, iclass 23, count 2 2006.176.08:17:08.10#ibcon#read 3, iclass 23, count 2 2006.176.08:17:08.10#ibcon#about to read 4, iclass 23, count 2 2006.176.08:17:08.10#ibcon#read 4, iclass 23, count 2 2006.176.08:17:08.10#ibcon#about to read 5, iclass 23, count 2 2006.176.08:17:08.10#ibcon#read 5, iclass 23, count 2 2006.176.08:17:08.10#ibcon#about to read 6, iclass 23, count 2 2006.176.08:17:08.10#ibcon#read 6, iclass 23, count 2 2006.176.08:17:08.10#ibcon#end of sib2, iclass 23, count 2 2006.176.08:17:08.10#ibcon#*after write, iclass 23, count 2 2006.176.08:17:08.10#ibcon#*before return 0, iclass 23, count 2 2006.176.08:17:08.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:08.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:08.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.08:17:08.10#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:08.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:08.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:08.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:08.22#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:17:08.22#ibcon#first serial, iclass 23, count 0 2006.176.08:17:08.22#ibcon#enter sib2, iclass 23, count 0 2006.176.08:17:08.22#ibcon#flushed, iclass 23, count 0 2006.176.08:17:08.22#ibcon#about to write, iclass 23, count 0 2006.176.08:17:08.22#ibcon#wrote, iclass 23, count 0 2006.176.08:17:08.22#ibcon#about to read 3, iclass 23, count 0 2006.176.08:17:08.24#ibcon#read 3, iclass 23, count 0 2006.176.08:17:08.24#ibcon#about to read 4, iclass 23, count 0 2006.176.08:17:08.24#ibcon#read 4, iclass 23, count 0 2006.176.08:17:08.24#ibcon#about to read 5, iclass 23, count 0 2006.176.08:17:08.24#ibcon#read 5, iclass 23, count 0 2006.176.08:17:08.24#ibcon#about to read 6, iclass 23, count 0 2006.176.08:17:08.24#ibcon#read 6, iclass 23, count 0 2006.176.08:17:08.24#ibcon#end of sib2, iclass 23, count 0 2006.176.08:17:08.24#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:17:08.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:17:08.24#ibcon#[25=USB\r\n] 2006.176.08:17:08.24#ibcon#*before write, iclass 23, count 0 2006.176.08:17:08.24#ibcon#enter sib2, iclass 23, count 0 2006.176.08:17:08.24#ibcon#flushed, iclass 23, count 0 2006.176.08:17:08.24#ibcon#about to write, iclass 23, count 0 2006.176.08:17:08.24#ibcon#wrote, iclass 23, count 0 2006.176.08:17:08.24#ibcon#about to read 3, iclass 23, count 0 2006.176.08:17:08.27#ibcon#read 3, iclass 23, count 0 2006.176.08:17:08.27#ibcon#about to read 4, iclass 23, count 0 2006.176.08:17:08.27#ibcon#read 4, iclass 23, count 0 2006.176.08:17:08.27#ibcon#about to read 5, iclass 23, count 0 2006.176.08:17:08.27#ibcon#read 5, iclass 23, count 0 2006.176.08:17:08.27#ibcon#about to read 6, iclass 23, count 0 2006.176.08:17:08.27#ibcon#read 6, iclass 23, count 0 2006.176.08:17:08.27#ibcon#end of sib2, iclass 23, count 0 2006.176.08:17:08.27#ibcon#*after write, iclass 23, count 0 2006.176.08:17:08.27#ibcon#*before return 0, iclass 23, count 0 2006.176.08:17:08.27#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:08.27#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:08.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:17:08.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:17:08.27$vc4f8/valo=2,572.99 2006.176.08:17:08.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.08:17:08.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.08:17:08.27#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:08.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:08.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:08.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:08.27#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:17:08.27#ibcon#first serial, iclass 25, count 0 2006.176.08:17:08.27#ibcon#enter sib2, iclass 25, count 0 2006.176.08:17:08.27#ibcon#flushed, iclass 25, count 0 2006.176.08:17:08.27#ibcon#about to write, iclass 25, count 0 2006.176.08:17:08.27#ibcon#wrote, iclass 25, count 0 2006.176.08:17:08.27#ibcon#about to read 3, iclass 25, count 0 2006.176.08:17:08.29#ibcon#read 3, iclass 25, count 0 2006.176.08:17:08.29#ibcon#about to read 4, iclass 25, count 0 2006.176.08:17:08.29#ibcon#read 4, iclass 25, count 0 2006.176.08:17:08.29#ibcon#about to read 5, iclass 25, count 0 2006.176.08:17:08.29#ibcon#read 5, iclass 25, count 0 2006.176.08:17:08.29#ibcon#about to read 6, iclass 25, count 0 2006.176.08:17:08.29#ibcon#read 6, iclass 25, count 0 2006.176.08:17:08.29#ibcon#end of sib2, iclass 25, count 0 2006.176.08:17:08.29#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:17:08.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:17:08.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:17:08.29#ibcon#*before write, iclass 25, count 0 2006.176.08:17:08.29#ibcon#enter sib2, iclass 25, count 0 2006.176.08:17:08.29#ibcon#flushed, iclass 25, count 0 2006.176.08:17:08.29#ibcon#about to write, iclass 25, count 0 2006.176.08:17:08.29#ibcon#wrote, iclass 25, count 0 2006.176.08:17:08.29#ibcon#about to read 3, iclass 25, count 0 2006.176.08:17:08.33#ibcon#read 3, iclass 25, count 0 2006.176.08:17:08.33#ibcon#about to read 4, iclass 25, count 0 2006.176.08:17:08.33#ibcon#read 4, iclass 25, count 0 2006.176.08:17:08.33#ibcon#about to read 5, iclass 25, count 0 2006.176.08:17:08.33#ibcon#read 5, iclass 25, count 0 2006.176.08:17:08.33#ibcon#about to read 6, iclass 25, count 0 2006.176.08:17:08.33#ibcon#read 6, iclass 25, count 0 2006.176.08:17:08.33#ibcon#end of sib2, iclass 25, count 0 2006.176.08:17:08.33#ibcon#*after write, iclass 25, count 0 2006.176.08:17:08.33#ibcon#*before return 0, iclass 25, count 0 2006.176.08:17:08.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:08.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:08.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:17:08.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:17:08.33$vc4f8/va=2,7 2006.176.08:17:08.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.08:17:08.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.08:17:08.33#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:08.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:08.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:08.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:08.39#ibcon#enter wrdev, iclass 27, count 2 2006.176.08:17:08.39#ibcon#first serial, iclass 27, count 2 2006.176.08:17:08.39#ibcon#enter sib2, iclass 27, count 2 2006.176.08:17:08.39#ibcon#flushed, iclass 27, count 2 2006.176.08:17:08.39#ibcon#about to write, iclass 27, count 2 2006.176.08:17:08.39#ibcon#wrote, iclass 27, count 2 2006.176.08:17:08.39#ibcon#about to read 3, iclass 27, count 2 2006.176.08:17:08.41#ibcon#read 3, iclass 27, count 2 2006.176.08:17:08.41#ibcon#about to read 4, iclass 27, count 2 2006.176.08:17:08.41#ibcon#read 4, iclass 27, count 2 2006.176.08:17:08.41#ibcon#about to read 5, iclass 27, count 2 2006.176.08:17:08.41#ibcon#read 5, iclass 27, count 2 2006.176.08:17:08.41#ibcon#about to read 6, iclass 27, count 2 2006.176.08:17:08.41#ibcon#read 6, iclass 27, count 2 2006.176.08:17:08.41#ibcon#end of sib2, iclass 27, count 2 2006.176.08:17:08.41#ibcon#*mode == 0, iclass 27, count 2 2006.176.08:17:08.41#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.08:17:08.41#ibcon#[25=AT02-07\r\n] 2006.176.08:17:08.41#ibcon#*before write, iclass 27, count 2 2006.176.08:17:08.41#ibcon#enter sib2, iclass 27, count 2 2006.176.08:17:08.41#ibcon#flushed, iclass 27, count 2 2006.176.08:17:08.41#ibcon#about to write, iclass 27, count 2 2006.176.08:17:08.41#ibcon#wrote, iclass 27, count 2 2006.176.08:17:08.41#ibcon#about to read 3, iclass 27, count 2 2006.176.08:17:08.44#ibcon#read 3, iclass 27, count 2 2006.176.08:17:08.44#ibcon#about to read 4, iclass 27, count 2 2006.176.08:17:08.44#ibcon#read 4, iclass 27, count 2 2006.176.08:17:08.44#ibcon#about to read 5, iclass 27, count 2 2006.176.08:17:08.44#ibcon#read 5, iclass 27, count 2 2006.176.08:17:08.44#ibcon#about to read 6, iclass 27, count 2 2006.176.08:17:08.44#ibcon#read 6, iclass 27, count 2 2006.176.08:17:08.44#ibcon#end of sib2, iclass 27, count 2 2006.176.08:17:08.44#ibcon#*after write, iclass 27, count 2 2006.176.08:17:08.44#ibcon#*before return 0, iclass 27, count 2 2006.176.08:17:08.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:08.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:08.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.08:17:08.44#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:08.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:08.56#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:08.56#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:08.56#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:17:08.56#ibcon#first serial, iclass 27, count 0 2006.176.08:17:08.56#ibcon#enter sib2, iclass 27, count 0 2006.176.08:17:08.56#ibcon#flushed, iclass 27, count 0 2006.176.08:17:08.56#ibcon#about to write, iclass 27, count 0 2006.176.08:17:08.56#ibcon#wrote, iclass 27, count 0 2006.176.08:17:08.56#ibcon#about to read 3, iclass 27, count 0 2006.176.08:17:08.58#ibcon#read 3, iclass 27, count 0 2006.176.08:17:08.58#ibcon#about to read 4, iclass 27, count 0 2006.176.08:17:08.58#ibcon#read 4, iclass 27, count 0 2006.176.08:17:08.58#ibcon#about to read 5, iclass 27, count 0 2006.176.08:17:08.58#ibcon#read 5, iclass 27, count 0 2006.176.08:17:08.58#ibcon#about to read 6, iclass 27, count 0 2006.176.08:17:08.58#ibcon#read 6, iclass 27, count 0 2006.176.08:17:08.58#ibcon#end of sib2, iclass 27, count 0 2006.176.08:17:08.58#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:17:08.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:17:08.58#ibcon#[25=USB\r\n] 2006.176.08:17:08.58#ibcon#*before write, iclass 27, count 0 2006.176.08:17:08.58#ibcon#enter sib2, iclass 27, count 0 2006.176.08:17:08.58#ibcon#flushed, iclass 27, count 0 2006.176.08:17:08.58#ibcon#about to write, iclass 27, count 0 2006.176.08:17:08.58#ibcon#wrote, iclass 27, count 0 2006.176.08:17:08.58#ibcon#about to read 3, iclass 27, count 0 2006.176.08:17:08.61#ibcon#read 3, iclass 27, count 0 2006.176.08:17:08.61#ibcon#about to read 4, iclass 27, count 0 2006.176.08:17:08.61#ibcon#read 4, iclass 27, count 0 2006.176.08:17:08.61#ibcon#about to read 5, iclass 27, count 0 2006.176.08:17:08.61#ibcon#read 5, iclass 27, count 0 2006.176.08:17:08.61#ibcon#about to read 6, iclass 27, count 0 2006.176.08:17:08.61#ibcon#read 6, iclass 27, count 0 2006.176.08:17:08.61#ibcon#end of sib2, iclass 27, count 0 2006.176.08:17:08.61#ibcon#*after write, iclass 27, count 0 2006.176.08:17:08.61#ibcon#*before return 0, iclass 27, count 0 2006.176.08:17:08.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:08.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:08.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:17:08.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:17:08.61$vc4f8/valo=3,672.99 2006.176.08:17:08.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.08:17:08.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.08:17:08.62#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:08.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:08.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:08.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:08.62#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:17:08.62#ibcon#first serial, iclass 29, count 0 2006.176.08:17:08.62#ibcon#enter sib2, iclass 29, count 0 2006.176.08:17:08.62#ibcon#flushed, iclass 29, count 0 2006.176.08:17:08.62#ibcon#about to write, iclass 29, count 0 2006.176.08:17:08.62#ibcon#wrote, iclass 29, count 0 2006.176.08:17:08.62#ibcon#about to read 3, iclass 29, count 0 2006.176.08:17:08.63#ibcon#read 3, iclass 29, count 0 2006.176.08:17:08.63#ibcon#about to read 4, iclass 29, count 0 2006.176.08:17:08.63#ibcon#read 4, iclass 29, count 0 2006.176.08:17:08.63#ibcon#about to read 5, iclass 29, count 0 2006.176.08:17:08.63#ibcon#read 5, iclass 29, count 0 2006.176.08:17:08.63#ibcon#about to read 6, iclass 29, count 0 2006.176.08:17:08.63#ibcon#read 6, iclass 29, count 0 2006.176.08:17:08.63#ibcon#end of sib2, iclass 29, count 0 2006.176.08:17:08.63#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:17:08.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:17:08.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:17:08.63#ibcon#*before write, iclass 29, count 0 2006.176.08:17:08.63#ibcon#enter sib2, iclass 29, count 0 2006.176.08:17:08.63#ibcon#flushed, iclass 29, count 0 2006.176.08:17:08.63#ibcon#about to write, iclass 29, count 0 2006.176.08:17:08.63#ibcon#wrote, iclass 29, count 0 2006.176.08:17:08.63#ibcon#about to read 3, iclass 29, count 0 2006.176.08:17:08.67#ibcon#read 3, iclass 29, count 0 2006.176.08:17:08.67#ibcon#about to read 4, iclass 29, count 0 2006.176.08:17:08.67#ibcon#read 4, iclass 29, count 0 2006.176.08:17:08.67#ibcon#about to read 5, iclass 29, count 0 2006.176.08:17:08.67#ibcon#read 5, iclass 29, count 0 2006.176.08:17:08.67#ibcon#about to read 6, iclass 29, count 0 2006.176.08:17:08.67#ibcon#read 6, iclass 29, count 0 2006.176.08:17:08.67#ibcon#end of sib2, iclass 29, count 0 2006.176.08:17:08.67#ibcon#*after write, iclass 29, count 0 2006.176.08:17:08.67#ibcon#*before return 0, iclass 29, count 0 2006.176.08:17:08.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:08.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:08.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:17:08.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:17:08.67$vc4f8/va=3,6 2006.176.08:17:08.67#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.08:17:08.67#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.08:17:08.67#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:08.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:08.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:08.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:08.73#ibcon#enter wrdev, iclass 31, count 2 2006.176.08:17:08.73#ibcon#first serial, iclass 31, count 2 2006.176.08:17:08.73#ibcon#enter sib2, iclass 31, count 2 2006.176.08:17:08.73#ibcon#flushed, iclass 31, count 2 2006.176.08:17:08.73#ibcon#about to write, iclass 31, count 2 2006.176.08:17:08.73#ibcon#wrote, iclass 31, count 2 2006.176.08:17:08.73#ibcon#about to read 3, iclass 31, count 2 2006.176.08:17:08.75#ibcon#read 3, iclass 31, count 2 2006.176.08:17:08.75#ibcon#about to read 4, iclass 31, count 2 2006.176.08:17:08.75#ibcon#read 4, iclass 31, count 2 2006.176.08:17:08.75#ibcon#about to read 5, iclass 31, count 2 2006.176.08:17:08.75#ibcon#read 5, iclass 31, count 2 2006.176.08:17:08.75#ibcon#about to read 6, iclass 31, count 2 2006.176.08:17:08.75#ibcon#read 6, iclass 31, count 2 2006.176.08:17:08.75#ibcon#end of sib2, iclass 31, count 2 2006.176.08:17:08.75#ibcon#*mode == 0, iclass 31, count 2 2006.176.08:17:08.75#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.08:17:08.75#ibcon#[25=AT03-06\r\n] 2006.176.08:17:08.75#ibcon#*before write, iclass 31, count 2 2006.176.08:17:08.75#ibcon#enter sib2, iclass 31, count 2 2006.176.08:17:08.75#ibcon#flushed, iclass 31, count 2 2006.176.08:17:08.75#ibcon#about to write, iclass 31, count 2 2006.176.08:17:08.75#ibcon#wrote, iclass 31, count 2 2006.176.08:17:08.75#ibcon#about to read 3, iclass 31, count 2 2006.176.08:17:08.79#ibcon#read 3, iclass 31, count 2 2006.176.08:17:08.79#ibcon#about to read 4, iclass 31, count 2 2006.176.08:17:08.79#ibcon#read 4, iclass 31, count 2 2006.176.08:17:08.79#ibcon#about to read 5, iclass 31, count 2 2006.176.08:17:08.79#ibcon#read 5, iclass 31, count 2 2006.176.08:17:08.79#ibcon#about to read 6, iclass 31, count 2 2006.176.08:17:08.79#ibcon#read 6, iclass 31, count 2 2006.176.08:17:08.79#ibcon#end of sib2, iclass 31, count 2 2006.176.08:17:08.79#ibcon#*after write, iclass 31, count 2 2006.176.08:17:08.79#ibcon#*before return 0, iclass 31, count 2 2006.176.08:17:08.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:08.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:08.79#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.08:17:08.79#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:08.79#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:08.91#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:08.91#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:08.91#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:17:08.91#ibcon#first serial, iclass 31, count 0 2006.176.08:17:08.91#ibcon#enter sib2, iclass 31, count 0 2006.176.08:17:08.91#ibcon#flushed, iclass 31, count 0 2006.176.08:17:08.91#ibcon#about to write, iclass 31, count 0 2006.176.08:17:08.91#ibcon#wrote, iclass 31, count 0 2006.176.08:17:08.91#ibcon#about to read 3, iclass 31, count 0 2006.176.08:17:08.93#ibcon#read 3, iclass 31, count 0 2006.176.08:17:08.93#ibcon#about to read 4, iclass 31, count 0 2006.176.08:17:08.93#ibcon#read 4, iclass 31, count 0 2006.176.08:17:08.93#ibcon#about to read 5, iclass 31, count 0 2006.176.08:17:08.93#ibcon#read 5, iclass 31, count 0 2006.176.08:17:08.93#ibcon#about to read 6, iclass 31, count 0 2006.176.08:17:08.93#ibcon#read 6, iclass 31, count 0 2006.176.08:17:08.93#ibcon#end of sib2, iclass 31, count 0 2006.176.08:17:08.93#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:17:08.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:17:08.93#ibcon#[25=USB\r\n] 2006.176.08:17:08.93#ibcon#*before write, iclass 31, count 0 2006.176.08:17:08.93#ibcon#enter sib2, iclass 31, count 0 2006.176.08:17:08.93#ibcon#flushed, iclass 31, count 0 2006.176.08:17:08.93#ibcon#about to write, iclass 31, count 0 2006.176.08:17:08.93#ibcon#wrote, iclass 31, count 0 2006.176.08:17:08.93#ibcon#about to read 3, iclass 31, count 0 2006.176.08:17:08.96#ibcon#read 3, iclass 31, count 0 2006.176.08:17:08.96#ibcon#about to read 4, iclass 31, count 0 2006.176.08:17:08.96#ibcon#read 4, iclass 31, count 0 2006.176.08:17:08.96#ibcon#about to read 5, iclass 31, count 0 2006.176.08:17:08.96#ibcon#read 5, iclass 31, count 0 2006.176.08:17:08.96#ibcon#about to read 6, iclass 31, count 0 2006.176.08:17:08.96#ibcon#read 6, iclass 31, count 0 2006.176.08:17:08.96#ibcon#end of sib2, iclass 31, count 0 2006.176.08:17:08.96#ibcon#*after write, iclass 31, count 0 2006.176.08:17:08.96#ibcon#*before return 0, iclass 31, count 0 2006.176.08:17:08.96#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:08.96#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:08.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:17:08.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:17:08.96$vc4f8/valo=4,832.99 2006.176.08:17:08.96#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.08:17:08.96#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.08:17:08.96#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:08.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:08.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:08.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:08.96#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:17:08.96#ibcon#first serial, iclass 33, count 0 2006.176.08:17:08.96#ibcon#enter sib2, iclass 33, count 0 2006.176.08:17:08.96#ibcon#flushed, iclass 33, count 0 2006.176.08:17:08.96#ibcon#about to write, iclass 33, count 0 2006.176.08:17:08.96#ibcon#wrote, iclass 33, count 0 2006.176.08:17:08.96#ibcon#about to read 3, iclass 33, count 0 2006.176.08:17:08.98#ibcon#read 3, iclass 33, count 0 2006.176.08:17:08.98#ibcon#about to read 4, iclass 33, count 0 2006.176.08:17:08.98#ibcon#read 4, iclass 33, count 0 2006.176.08:17:08.98#ibcon#about to read 5, iclass 33, count 0 2006.176.08:17:08.98#ibcon#read 5, iclass 33, count 0 2006.176.08:17:08.98#ibcon#about to read 6, iclass 33, count 0 2006.176.08:17:08.98#ibcon#read 6, iclass 33, count 0 2006.176.08:17:08.98#ibcon#end of sib2, iclass 33, count 0 2006.176.08:17:08.98#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:17:08.98#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:17:08.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:17:08.98#ibcon#*before write, iclass 33, count 0 2006.176.08:17:08.98#ibcon#enter sib2, iclass 33, count 0 2006.176.08:17:08.98#ibcon#flushed, iclass 33, count 0 2006.176.08:17:08.98#ibcon#about to write, iclass 33, count 0 2006.176.08:17:08.98#ibcon#wrote, iclass 33, count 0 2006.176.08:17:08.98#ibcon#about to read 3, iclass 33, count 0 2006.176.08:17:09.02#ibcon#read 3, iclass 33, count 0 2006.176.08:17:09.02#ibcon#about to read 4, iclass 33, count 0 2006.176.08:17:09.02#ibcon#read 4, iclass 33, count 0 2006.176.08:17:09.02#ibcon#about to read 5, iclass 33, count 0 2006.176.08:17:09.02#ibcon#read 5, iclass 33, count 0 2006.176.08:17:09.02#ibcon#about to read 6, iclass 33, count 0 2006.176.08:17:09.02#ibcon#read 6, iclass 33, count 0 2006.176.08:17:09.02#ibcon#end of sib2, iclass 33, count 0 2006.176.08:17:09.02#ibcon#*after write, iclass 33, count 0 2006.176.08:17:09.02#ibcon#*before return 0, iclass 33, count 0 2006.176.08:17:09.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:09.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:09.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:17:09.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:17:09.02$vc4f8/va=4,7 2006.176.08:17:09.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.176.08:17:09.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.176.08:17:09.02#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:09.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:09.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:09.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:09.08#ibcon#enter wrdev, iclass 35, count 2 2006.176.08:17:09.08#ibcon#first serial, iclass 35, count 2 2006.176.08:17:09.08#ibcon#enter sib2, iclass 35, count 2 2006.176.08:17:09.08#ibcon#flushed, iclass 35, count 2 2006.176.08:17:09.08#ibcon#about to write, iclass 35, count 2 2006.176.08:17:09.08#ibcon#wrote, iclass 35, count 2 2006.176.08:17:09.08#ibcon#about to read 3, iclass 35, count 2 2006.176.08:17:09.10#ibcon#read 3, iclass 35, count 2 2006.176.08:17:09.10#ibcon#about to read 4, iclass 35, count 2 2006.176.08:17:09.10#ibcon#read 4, iclass 35, count 2 2006.176.08:17:09.10#ibcon#about to read 5, iclass 35, count 2 2006.176.08:17:09.10#ibcon#read 5, iclass 35, count 2 2006.176.08:17:09.10#ibcon#about to read 6, iclass 35, count 2 2006.176.08:17:09.10#ibcon#read 6, iclass 35, count 2 2006.176.08:17:09.10#ibcon#end of sib2, iclass 35, count 2 2006.176.08:17:09.10#ibcon#*mode == 0, iclass 35, count 2 2006.176.08:17:09.10#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.176.08:17:09.10#ibcon#[25=AT04-07\r\n] 2006.176.08:17:09.10#ibcon#*before write, iclass 35, count 2 2006.176.08:17:09.10#ibcon#enter sib2, iclass 35, count 2 2006.176.08:17:09.10#ibcon#flushed, iclass 35, count 2 2006.176.08:17:09.10#ibcon#about to write, iclass 35, count 2 2006.176.08:17:09.10#ibcon#wrote, iclass 35, count 2 2006.176.08:17:09.10#ibcon#about to read 3, iclass 35, count 2 2006.176.08:17:09.13#ibcon#read 3, iclass 35, count 2 2006.176.08:17:09.13#ibcon#about to read 4, iclass 35, count 2 2006.176.08:17:09.13#ibcon#read 4, iclass 35, count 2 2006.176.08:17:09.13#ibcon#about to read 5, iclass 35, count 2 2006.176.08:17:09.13#ibcon#read 5, iclass 35, count 2 2006.176.08:17:09.13#ibcon#about to read 6, iclass 35, count 2 2006.176.08:17:09.13#ibcon#read 6, iclass 35, count 2 2006.176.08:17:09.13#ibcon#end of sib2, iclass 35, count 2 2006.176.08:17:09.13#ibcon#*after write, iclass 35, count 2 2006.176.08:17:09.13#ibcon#*before return 0, iclass 35, count 2 2006.176.08:17:09.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:09.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:09.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.176.08:17:09.13#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:09.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:09.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:09.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:09.25#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:17:09.25#ibcon#first serial, iclass 35, count 0 2006.176.08:17:09.25#ibcon#enter sib2, iclass 35, count 0 2006.176.08:17:09.25#ibcon#flushed, iclass 35, count 0 2006.176.08:17:09.25#ibcon#about to write, iclass 35, count 0 2006.176.08:17:09.25#ibcon#wrote, iclass 35, count 0 2006.176.08:17:09.25#ibcon#about to read 3, iclass 35, count 0 2006.176.08:17:09.27#ibcon#read 3, iclass 35, count 0 2006.176.08:17:09.27#ibcon#about to read 4, iclass 35, count 0 2006.176.08:17:09.27#ibcon#read 4, iclass 35, count 0 2006.176.08:17:09.27#ibcon#about to read 5, iclass 35, count 0 2006.176.08:17:09.27#ibcon#read 5, iclass 35, count 0 2006.176.08:17:09.27#ibcon#about to read 6, iclass 35, count 0 2006.176.08:17:09.27#ibcon#read 6, iclass 35, count 0 2006.176.08:17:09.27#ibcon#end of sib2, iclass 35, count 0 2006.176.08:17:09.27#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:17:09.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:17:09.27#ibcon#[25=USB\r\n] 2006.176.08:17:09.27#ibcon#*before write, iclass 35, count 0 2006.176.08:17:09.27#ibcon#enter sib2, iclass 35, count 0 2006.176.08:17:09.27#ibcon#flushed, iclass 35, count 0 2006.176.08:17:09.27#ibcon#about to write, iclass 35, count 0 2006.176.08:17:09.27#ibcon#wrote, iclass 35, count 0 2006.176.08:17:09.27#ibcon#about to read 3, iclass 35, count 0 2006.176.08:17:09.30#ibcon#read 3, iclass 35, count 0 2006.176.08:17:09.30#ibcon#about to read 4, iclass 35, count 0 2006.176.08:17:09.30#ibcon#read 4, iclass 35, count 0 2006.176.08:17:09.30#ibcon#about to read 5, iclass 35, count 0 2006.176.08:17:09.30#ibcon#read 5, iclass 35, count 0 2006.176.08:17:09.30#ibcon#about to read 6, iclass 35, count 0 2006.176.08:17:09.30#ibcon#read 6, iclass 35, count 0 2006.176.08:17:09.30#ibcon#end of sib2, iclass 35, count 0 2006.176.08:17:09.30#ibcon#*after write, iclass 35, count 0 2006.176.08:17:09.30#ibcon#*before return 0, iclass 35, count 0 2006.176.08:17:09.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:09.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:09.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:17:09.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:17:09.30$vc4f8/valo=5,652.99 2006.176.08:17:09.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.176.08:17:09.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.176.08:17:09.30#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:09.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:09.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:09.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:09.30#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:17:09.30#ibcon#first serial, iclass 37, count 0 2006.176.08:17:09.30#ibcon#enter sib2, iclass 37, count 0 2006.176.08:17:09.30#ibcon#flushed, iclass 37, count 0 2006.176.08:17:09.30#ibcon#about to write, iclass 37, count 0 2006.176.08:17:09.30#ibcon#wrote, iclass 37, count 0 2006.176.08:17:09.30#ibcon#about to read 3, iclass 37, count 0 2006.176.08:17:09.32#ibcon#read 3, iclass 37, count 0 2006.176.08:17:09.32#ibcon#about to read 4, iclass 37, count 0 2006.176.08:17:09.32#ibcon#read 4, iclass 37, count 0 2006.176.08:17:09.32#ibcon#about to read 5, iclass 37, count 0 2006.176.08:17:09.32#ibcon#read 5, iclass 37, count 0 2006.176.08:17:09.32#ibcon#about to read 6, iclass 37, count 0 2006.176.08:17:09.32#ibcon#read 6, iclass 37, count 0 2006.176.08:17:09.32#ibcon#end of sib2, iclass 37, count 0 2006.176.08:17:09.32#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:17:09.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:17:09.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:17:09.32#ibcon#*before write, iclass 37, count 0 2006.176.08:17:09.32#ibcon#enter sib2, iclass 37, count 0 2006.176.08:17:09.32#ibcon#flushed, iclass 37, count 0 2006.176.08:17:09.32#ibcon#about to write, iclass 37, count 0 2006.176.08:17:09.32#ibcon#wrote, iclass 37, count 0 2006.176.08:17:09.32#ibcon#about to read 3, iclass 37, count 0 2006.176.08:17:09.36#ibcon#read 3, iclass 37, count 0 2006.176.08:17:09.36#ibcon#about to read 4, iclass 37, count 0 2006.176.08:17:09.36#ibcon#read 4, iclass 37, count 0 2006.176.08:17:09.36#ibcon#about to read 5, iclass 37, count 0 2006.176.08:17:09.36#ibcon#read 5, iclass 37, count 0 2006.176.08:17:09.36#ibcon#about to read 6, iclass 37, count 0 2006.176.08:17:09.36#ibcon#read 6, iclass 37, count 0 2006.176.08:17:09.36#ibcon#end of sib2, iclass 37, count 0 2006.176.08:17:09.36#ibcon#*after write, iclass 37, count 0 2006.176.08:17:09.36#ibcon#*before return 0, iclass 37, count 0 2006.176.08:17:09.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:09.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:09.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:17:09.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:17:09.36$vc4f8/va=5,7 2006.176.08:17:09.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.176.08:17:09.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.176.08:17:09.36#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:09.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:09.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:09.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:09.42#ibcon#enter wrdev, iclass 39, count 2 2006.176.08:17:09.42#ibcon#first serial, iclass 39, count 2 2006.176.08:17:09.42#ibcon#enter sib2, iclass 39, count 2 2006.176.08:17:09.42#ibcon#flushed, iclass 39, count 2 2006.176.08:17:09.42#ibcon#about to write, iclass 39, count 2 2006.176.08:17:09.42#ibcon#wrote, iclass 39, count 2 2006.176.08:17:09.42#ibcon#about to read 3, iclass 39, count 2 2006.176.08:17:09.44#ibcon#read 3, iclass 39, count 2 2006.176.08:17:09.44#ibcon#about to read 4, iclass 39, count 2 2006.176.08:17:09.44#ibcon#read 4, iclass 39, count 2 2006.176.08:17:09.44#ibcon#about to read 5, iclass 39, count 2 2006.176.08:17:09.44#ibcon#read 5, iclass 39, count 2 2006.176.08:17:09.44#ibcon#about to read 6, iclass 39, count 2 2006.176.08:17:09.44#ibcon#read 6, iclass 39, count 2 2006.176.08:17:09.44#ibcon#end of sib2, iclass 39, count 2 2006.176.08:17:09.44#ibcon#*mode == 0, iclass 39, count 2 2006.176.08:17:09.44#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.176.08:17:09.44#ibcon#[25=AT05-07\r\n] 2006.176.08:17:09.44#ibcon#*before write, iclass 39, count 2 2006.176.08:17:09.44#ibcon#enter sib2, iclass 39, count 2 2006.176.08:17:09.44#ibcon#flushed, iclass 39, count 2 2006.176.08:17:09.44#ibcon#about to write, iclass 39, count 2 2006.176.08:17:09.44#ibcon#wrote, iclass 39, count 2 2006.176.08:17:09.44#ibcon#about to read 3, iclass 39, count 2 2006.176.08:17:09.47#ibcon#read 3, iclass 39, count 2 2006.176.08:17:09.47#ibcon#about to read 4, iclass 39, count 2 2006.176.08:17:09.47#ibcon#read 4, iclass 39, count 2 2006.176.08:17:09.47#ibcon#about to read 5, iclass 39, count 2 2006.176.08:17:09.47#ibcon#read 5, iclass 39, count 2 2006.176.08:17:09.47#ibcon#about to read 6, iclass 39, count 2 2006.176.08:17:09.47#ibcon#read 6, iclass 39, count 2 2006.176.08:17:09.47#ibcon#end of sib2, iclass 39, count 2 2006.176.08:17:09.47#ibcon#*after write, iclass 39, count 2 2006.176.08:17:09.47#ibcon#*before return 0, iclass 39, count 2 2006.176.08:17:09.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:09.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:09.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.176.08:17:09.47#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:09.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:09.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:09.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:09.59#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:17:09.59#ibcon#first serial, iclass 39, count 0 2006.176.08:17:09.59#ibcon#enter sib2, iclass 39, count 0 2006.176.08:17:09.59#ibcon#flushed, iclass 39, count 0 2006.176.08:17:09.59#ibcon#about to write, iclass 39, count 0 2006.176.08:17:09.59#ibcon#wrote, iclass 39, count 0 2006.176.08:17:09.59#ibcon#about to read 3, iclass 39, count 0 2006.176.08:17:09.61#ibcon#read 3, iclass 39, count 0 2006.176.08:17:09.61#ibcon#about to read 4, iclass 39, count 0 2006.176.08:17:09.61#ibcon#read 4, iclass 39, count 0 2006.176.08:17:09.61#ibcon#about to read 5, iclass 39, count 0 2006.176.08:17:09.61#ibcon#read 5, iclass 39, count 0 2006.176.08:17:09.61#ibcon#about to read 6, iclass 39, count 0 2006.176.08:17:09.61#ibcon#read 6, iclass 39, count 0 2006.176.08:17:09.61#ibcon#end of sib2, iclass 39, count 0 2006.176.08:17:09.61#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:17:09.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:17:09.61#ibcon#[25=USB\r\n] 2006.176.08:17:09.61#ibcon#*before write, iclass 39, count 0 2006.176.08:17:09.61#ibcon#enter sib2, iclass 39, count 0 2006.176.08:17:09.61#ibcon#flushed, iclass 39, count 0 2006.176.08:17:09.61#ibcon#about to write, iclass 39, count 0 2006.176.08:17:09.61#ibcon#wrote, iclass 39, count 0 2006.176.08:17:09.61#ibcon#about to read 3, iclass 39, count 0 2006.176.08:17:09.64#ibcon#read 3, iclass 39, count 0 2006.176.08:17:09.64#ibcon#about to read 4, iclass 39, count 0 2006.176.08:17:09.64#ibcon#read 4, iclass 39, count 0 2006.176.08:17:09.64#ibcon#about to read 5, iclass 39, count 0 2006.176.08:17:09.64#ibcon#read 5, iclass 39, count 0 2006.176.08:17:09.64#ibcon#about to read 6, iclass 39, count 0 2006.176.08:17:09.64#ibcon#read 6, iclass 39, count 0 2006.176.08:17:09.64#ibcon#end of sib2, iclass 39, count 0 2006.176.08:17:09.64#ibcon#*after write, iclass 39, count 0 2006.176.08:17:09.64#ibcon#*before return 0, iclass 39, count 0 2006.176.08:17:09.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:09.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:09.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:17:09.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:17:09.64$vc4f8/valo=6,772.99 2006.176.08:17:09.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.08:17:09.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.08:17:09.64#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:09.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:09.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:09.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:09.64#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:17:09.64#ibcon#first serial, iclass 3, count 0 2006.176.08:17:09.64#ibcon#enter sib2, iclass 3, count 0 2006.176.08:17:09.64#ibcon#flushed, iclass 3, count 0 2006.176.08:17:09.64#ibcon#about to write, iclass 3, count 0 2006.176.08:17:09.64#ibcon#wrote, iclass 3, count 0 2006.176.08:17:09.64#ibcon#about to read 3, iclass 3, count 0 2006.176.08:17:09.66#ibcon#read 3, iclass 3, count 0 2006.176.08:17:09.66#ibcon#about to read 4, iclass 3, count 0 2006.176.08:17:09.66#ibcon#read 4, iclass 3, count 0 2006.176.08:17:09.66#ibcon#about to read 5, iclass 3, count 0 2006.176.08:17:09.66#ibcon#read 5, iclass 3, count 0 2006.176.08:17:09.66#ibcon#about to read 6, iclass 3, count 0 2006.176.08:17:09.66#ibcon#read 6, iclass 3, count 0 2006.176.08:17:09.66#ibcon#end of sib2, iclass 3, count 0 2006.176.08:17:09.66#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:17:09.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:17:09.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:17:09.66#ibcon#*before write, iclass 3, count 0 2006.176.08:17:09.66#ibcon#enter sib2, iclass 3, count 0 2006.176.08:17:09.66#ibcon#flushed, iclass 3, count 0 2006.176.08:17:09.66#ibcon#about to write, iclass 3, count 0 2006.176.08:17:09.66#ibcon#wrote, iclass 3, count 0 2006.176.08:17:09.66#ibcon#about to read 3, iclass 3, count 0 2006.176.08:17:09.70#ibcon#read 3, iclass 3, count 0 2006.176.08:17:09.70#ibcon#about to read 4, iclass 3, count 0 2006.176.08:17:09.70#ibcon#read 4, iclass 3, count 0 2006.176.08:17:09.70#ibcon#about to read 5, iclass 3, count 0 2006.176.08:17:09.70#ibcon#read 5, iclass 3, count 0 2006.176.08:17:09.70#ibcon#about to read 6, iclass 3, count 0 2006.176.08:17:09.70#ibcon#read 6, iclass 3, count 0 2006.176.08:17:09.70#ibcon#end of sib2, iclass 3, count 0 2006.176.08:17:09.70#ibcon#*after write, iclass 3, count 0 2006.176.08:17:09.70#ibcon#*before return 0, iclass 3, count 0 2006.176.08:17:09.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:09.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:09.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:17:09.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:17:09.70$vc4f8/va=6,6 2006.176.08:17:09.70#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.176.08:17:09.70#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.176.08:17:09.70#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:09.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:09.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:09.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:09.76#ibcon#enter wrdev, iclass 5, count 2 2006.176.08:17:09.76#ibcon#first serial, iclass 5, count 2 2006.176.08:17:09.76#ibcon#enter sib2, iclass 5, count 2 2006.176.08:17:09.76#ibcon#flushed, iclass 5, count 2 2006.176.08:17:09.76#ibcon#about to write, iclass 5, count 2 2006.176.08:17:09.76#ibcon#wrote, iclass 5, count 2 2006.176.08:17:09.76#ibcon#about to read 3, iclass 5, count 2 2006.176.08:17:09.78#ibcon#read 3, iclass 5, count 2 2006.176.08:17:09.78#ibcon#about to read 4, iclass 5, count 2 2006.176.08:17:09.78#ibcon#read 4, iclass 5, count 2 2006.176.08:17:09.78#ibcon#about to read 5, iclass 5, count 2 2006.176.08:17:09.78#ibcon#read 5, iclass 5, count 2 2006.176.08:17:09.78#ibcon#about to read 6, iclass 5, count 2 2006.176.08:17:09.78#ibcon#read 6, iclass 5, count 2 2006.176.08:17:09.78#ibcon#end of sib2, iclass 5, count 2 2006.176.08:17:09.78#ibcon#*mode == 0, iclass 5, count 2 2006.176.08:17:09.78#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.176.08:17:09.78#ibcon#[25=AT06-06\r\n] 2006.176.08:17:09.78#ibcon#*before write, iclass 5, count 2 2006.176.08:17:09.78#ibcon#enter sib2, iclass 5, count 2 2006.176.08:17:09.78#ibcon#flushed, iclass 5, count 2 2006.176.08:17:09.78#ibcon#about to write, iclass 5, count 2 2006.176.08:17:09.78#ibcon#wrote, iclass 5, count 2 2006.176.08:17:09.78#ibcon#about to read 3, iclass 5, count 2 2006.176.08:17:09.81#ibcon#read 3, iclass 5, count 2 2006.176.08:17:09.81#ibcon#about to read 4, iclass 5, count 2 2006.176.08:17:09.81#ibcon#read 4, iclass 5, count 2 2006.176.08:17:09.81#ibcon#about to read 5, iclass 5, count 2 2006.176.08:17:09.81#ibcon#read 5, iclass 5, count 2 2006.176.08:17:09.81#ibcon#about to read 6, iclass 5, count 2 2006.176.08:17:09.81#ibcon#read 6, iclass 5, count 2 2006.176.08:17:09.81#ibcon#end of sib2, iclass 5, count 2 2006.176.08:17:09.81#ibcon#*after write, iclass 5, count 2 2006.176.08:17:09.81#ibcon#*before return 0, iclass 5, count 2 2006.176.08:17:09.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:09.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:09.81#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.176.08:17:09.81#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:09.81#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:09.93#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:09.93#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:09.93#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:17:09.93#ibcon#first serial, iclass 5, count 0 2006.176.08:17:09.93#ibcon#enter sib2, iclass 5, count 0 2006.176.08:17:09.93#ibcon#flushed, iclass 5, count 0 2006.176.08:17:09.93#ibcon#about to write, iclass 5, count 0 2006.176.08:17:09.93#ibcon#wrote, iclass 5, count 0 2006.176.08:17:09.93#ibcon#about to read 3, iclass 5, count 0 2006.176.08:17:09.95#ibcon#read 3, iclass 5, count 0 2006.176.08:17:09.95#ibcon#about to read 4, iclass 5, count 0 2006.176.08:17:09.95#ibcon#read 4, iclass 5, count 0 2006.176.08:17:09.95#ibcon#about to read 5, iclass 5, count 0 2006.176.08:17:09.95#ibcon#read 5, iclass 5, count 0 2006.176.08:17:09.95#ibcon#about to read 6, iclass 5, count 0 2006.176.08:17:09.95#ibcon#read 6, iclass 5, count 0 2006.176.08:17:09.95#ibcon#end of sib2, iclass 5, count 0 2006.176.08:17:09.95#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:17:09.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:17:09.95#ibcon#[25=USB\r\n] 2006.176.08:17:09.95#ibcon#*before write, iclass 5, count 0 2006.176.08:17:09.95#ibcon#enter sib2, iclass 5, count 0 2006.176.08:17:09.95#ibcon#flushed, iclass 5, count 0 2006.176.08:17:09.95#ibcon#about to write, iclass 5, count 0 2006.176.08:17:09.95#ibcon#wrote, iclass 5, count 0 2006.176.08:17:09.95#ibcon#about to read 3, iclass 5, count 0 2006.176.08:17:09.98#ibcon#read 3, iclass 5, count 0 2006.176.08:17:09.98#ibcon#about to read 4, iclass 5, count 0 2006.176.08:17:09.98#ibcon#read 4, iclass 5, count 0 2006.176.08:17:09.98#ibcon#about to read 5, iclass 5, count 0 2006.176.08:17:09.98#ibcon#read 5, iclass 5, count 0 2006.176.08:17:09.98#ibcon#about to read 6, iclass 5, count 0 2006.176.08:17:09.98#ibcon#read 6, iclass 5, count 0 2006.176.08:17:09.98#ibcon#end of sib2, iclass 5, count 0 2006.176.08:17:09.98#ibcon#*after write, iclass 5, count 0 2006.176.08:17:09.98#ibcon#*before return 0, iclass 5, count 0 2006.176.08:17:09.98#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:09.98#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:09.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:17:09.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:17:09.98$vc4f8/valo=7,832.99 2006.176.08:17:09.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.08:17:09.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.08:17:09.98#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:09.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:09.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:09.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:09.98#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:17:09.98#ibcon#first serial, iclass 7, count 0 2006.176.08:17:09.98#ibcon#enter sib2, iclass 7, count 0 2006.176.08:17:09.98#ibcon#flushed, iclass 7, count 0 2006.176.08:17:09.98#ibcon#about to write, iclass 7, count 0 2006.176.08:17:09.98#ibcon#wrote, iclass 7, count 0 2006.176.08:17:09.98#ibcon#about to read 3, iclass 7, count 0 2006.176.08:17:10.00#ibcon#read 3, iclass 7, count 0 2006.176.08:17:10.00#ibcon#about to read 4, iclass 7, count 0 2006.176.08:17:10.00#ibcon#read 4, iclass 7, count 0 2006.176.08:17:10.00#ibcon#about to read 5, iclass 7, count 0 2006.176.08:17:10.00#ibcon#read 5, iclass 7, count 0 2006.176.08:17:10.00#ibcon#about to read 6, iclass 7, count 0 2006.176.08:17:10.00#ibcon#read 6, iclass 7, count 0 2006.176.08:17:10.00#ibcon#end of sib2, iclass 7, count 0 2006.176.08:17:10.00#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:17:10.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:17:10.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:17:10.00#ibcon#*before write, iclass 7, count 0 2006.176.08:17:10.00#ibcon#enter sib2, iclass 7, count 0 2006.176.08:17:10.00#ibcon#flushed, iclass 7, count 0 2006.176.08:17:10.00#ibcon#about to write, iclass 7, count 0 2006.176.08:17:10.00#ibcon#wrote, iclass 7, count 0 2006.176.08:17:10.00#ibcon#about to read 3, iclass 7, count 0 2006.176.08:17:10.04#ibcon#read 3, iclass 7, count 0 2006.176.08:17:10.04#ibcon#about to read 4, iclass 7, count 0 2006.176.08:17:10.04#ibcon#read 4, iclass 7, count 0 2006.176.08:17:10.04#ibcon#about to read 5, iclass 7, count 0 2006.176.08:17:10.04#ibcon#read 5, iclass 7, count 0 2006.176.08:17:10.04#ibcon#about to read 6, iclass 7, count 0 2006.176.08:17:10.04#ibcon#read 6, iclass 7, count 0 2006.176.08:17:10.04#ibcon#end of sib2, iclass 7, count 0 2006.176.08:17:10.04#ibcon#*after write, iclass 7, count 0 2006.176.08:17:10.04#ibcon#*before return 0, iclass 7, count 0 2006.176.08:17:10.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:10.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:10.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:17:10.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:17:10.04$vc4f8/va=7,6 2006.176.08:17:10.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.176.08:17:10.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.176.08:17:10.04#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:10.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:17:10.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:17:10.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:17:10.10#ibcon#enter wrdev, iclass 11, count 2 2006.176.08:17:10.10#ibcon#first serial, iclass 11, count 2 2006.176.08:17:10.10#ibcon#enter sib2, iclass 11, count 2 2006.176.08:17:10.10#ibcon#flushed, iclass 11, count 2 2006.176.08:17:10.10#ibcon#about to write, iclass 11, count 2 2006.176.08:17:10.10#ibcon#wrote, iclass 11, count 2 2006.176.08:17:10.10#ibcon#about to read 3, iclass 11, count 2 2006.176.08:17:10.12#ibcon#read 3, iclass 11, count 2 2006.176.08:17:10.12#ibcon#about to read 4, iclass 11, count 2 2006.176.08:17:10.12#ibcon#read 4, iclass 11, count 2 2006.176.08:17:10.12#ibcon#about to read 5, iclass 11, count 2 2006.176.08:17:10.12#ibcon#read 5, iclass 11, count 2 2006.176.08:17:10.12#ibcon#about to read 6, iclass 11, count 2 2006.176.08:17:10.12#ibcon#read 6, iclass 11, count 2 2006.176.08:17:10.12#ibcon#end of sib2, iclass 11, count 2 2006.176.08:17:10.12#ibcon#*mode == 0, iclass 11, count 2 2006.176.08:17:10.12#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.176.08:17:10.12#ibcon#[25=AT07-06\r\n] 2006.176.08:17:10.12#ibcon#*before write, iclass 11, count 2 2006.176.08:17:10.12#ibcon#enter sib2, iclass 11, count 2 2006.176.08:17:10.12#ibcon#flushed, iclass 11, count 2 2006.176.08:17:10.12#ibcon#about to write, iclass 11, count 2 2006.176.08:17:10.12#ibcon#wrote, iclass 11, count 2 2006.176.08:17:10.12#ibcon#about to read 3, iclass 11, count 2 2006.176.08:17:10.15#ibcon#read 3, iclass 11, count 2 2006.176.08:17:10.15#ibcon#about to read 4, iclass 11, count 2 2006.176.08:17:10.15#ibcon#read 4, iclass 11, count 2 2006.176.08:17:10.15#ibcon#about to read 5, iclass 11, count 2 2006.176.08:17:10.15#ibcon#read 5, iclass 11, count 2 2006.176.08:17:10.15#ibcon#about to read 6, iclass 11, count 2 2006.176.08:17:10.15#ibcon#read 6, iclass 11, count 2 2006.176.08:17:10.15#ibcon#end of sib2, iclass 11, count 2 2006.176.08:17:10.15#ibcon#*after write, iclass 11, count 2 2006.176.08:17:10.15#ibcon#*before return 0, iclass 11, count 2 2006.176.08:17:10.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:17:10.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:17:10.15#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.176.08:17:10.15#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:10.15#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:17:10.16#abcon#<5=/06 3.4 6.3 23.80 931008.6\r\n> 2006.176.08:17:10.18#abcon#{5=INTERFACE CLEAR} 2006.176.08:17:10.24#abcon#[5=S1D000X0/0*\r\n] 2006.176.08:17:10.27#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:17:10.27#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:17:10.27#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:17:10.27#ibcon#first serial, iclass 11, count 0 2006.176.08:17:10.27#ibcon#enter sib2, iclass 11, count 0 2006.176.08:17:10.27#ibcon#flushed, iclass 11, count 0 2006.176.08:17:10.27#ibcon#about to write, iclass 11, count 0 2006.176.08:17:10.27#ibcon#wrote, iclass 11, count 0 2006.176.08:17:10.27#ibcon#about to read 3, iclass 11, count 0 2006.176.08:17:10.29#ibcon#read 3, iclass 11, count 0 2006.176.08:17:10.29#ibcon#about to read 4, iclass 11, count 0 2006.176.08:17:10.29#ibcon#read 4, iclass 11, count 0 2006.176.08:17:10.29#ibcon#about to read 5, iclass 11, count 0 2006.176.08:17:10.29#ibcon#read 5, iclass 11, count 0 2006.176.08:17:10.29#ibcon#about to read 6, iclass 11, count 0 2006.176.08:17:10.29#ibcon#read 6, iclass 11, count 0 2006.176.08:17:10.29#ibcon#end of sib2, iclass 11, count 0 2006.176.08:17:10.29#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:17:10.29#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:17:10.29#ibcon#[25=USB\r\n] 2006.176.08:17:10.29#ibcon#*before write, iclass 11, count 0 2006.176.08:17:10.29#ibcon#enter sib2, iclass 11, count 0 2006.176.08:17:10.29#ibcon#flushed, iclass 11, count 0 2006.176.08:17:10.29#ibcon#about to write, iclass 11, count 0 2006.176.08:17:10.29#ibcon#wrote, iclass 11, count 0 2006.176.08:17:10.29#ibcon#about to read 3, iclass 11, count 0 2006.176.08:17:10.32#ibcon#read 3, iclass 11, count 0 2006.176.08:17:10.32#ibcon#about to read 4, iclass 11, count 0 2006.176.08:17:10.32#ibcon#read 4, iclass 11, count 0 2006.176.08:17:10.32#ibcon#about to read 5, iclass 11, count 0 2006.176.08:17:10.32#ibcon#read 5, iclass 11, count 0 2006.176.08:17:10.32#ibcon#about to read 6, iclass 11, count 0 2006.176.08:17:10.32#ibcon#read 6, iclass 11, count 0 2006.176.08:17:10.32#ibcon#end of sib2, iclass 11, count 0 2006.176.08:17:10.32#ibcon#*after write, iclass 11, count 0 2006.176.08:17:10.32#ibcon#*before return 0, iclass 11, count 0 2006.176.08:17:10.32#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:17:10.32#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:17:10.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:17:10.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:17:10.32$vc4f8/valo=8,852.99 2006.176.08:17:10.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.08:17:10.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.08:17:10.32#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:10.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:17:10.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:17:10.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:17:10.32#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:17:10.32#ibcon#first serial, iclass 17, count 0 2006.176.08:17:10.32#ibcon#enter sib2, iclass 17, count 0 2006.176.08:17:10.32#ibcon#flushed, iclass 17, count 0 2006.176.08:17:10.32#ibcon#about to write, iclass 17, count 0 2006.176.08:17:10.32#ibcon#wrote, iclass 17, count 0 2006.176.08:17:10.32#ibcon#about to read 3, iclass 17, count 0 2006.176.08:17:10.34#ibcon#read 3, iclass 17, count 0 2006.176.08:17:10.34#ibcon#about to read 4, iclass 17, count 0 2006.176.08:17:10.34#ibcon#read 4, iclass 17, count 0 2006.176.08:17:10.34#ibcon#about to read 5, iclass 17, count 0 2006.176.08:17:10.34#ibcon#read 5, iclass 17, count 0 2006.176.08:17:10.34#ibcon#about to read 6, iclass 17, count 0 2006.176.08:17:10.34#ibcon#read 6, iclass 17, count 0 2006.176.08:17:10.34#ibcon#end of sib2, iclass 17, count 0 2006.176.08:17:10.34#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:17:10.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:17:10.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:17:10.34#ibcon#*before write, iclass 17, count 0 2006.176.08:17:10.34#ibcon#enter sib2, iclass 17, count 0 2006.176.08:17:10.34#ibcon#flushed, iclass 17, count 0 2006.176.08:17:10.34#ibcon#about to write, iclass 17, count 0 2006.176.08:17:10.34#ibcon#wrote, iclass 17, count 0 2006.176.08:17:10.34#ibcon#about to read 3, iclass 17, count 0 2006.176.08:17:10.38#ibcon#read 3, iclass 17, count 0 2006.176.08:17:10.38#ibcon#about to read 4, iclass 17, count 0 2006.176.08:17:10.38#ibcon#read 4, iclass 17, count 0 2006.176.08:17:10.38#ibcon#about to read 5, iclass 17, count 0 2006.176.08:17:10.38#ibcon#read 5, iclass 17, count 0 2006.176.08:17:10.38#ibcon#about to read 6, iclass 17, count 0 2006.176.08:17:10.38#ibcon#read 6, iclass 17, count 0 2006.176.08:17:10.38#ibcon#end of sib2, iclass 17, count 0 2006.176.08:17:10.38#ibcon#*after write, iclass 17, count 0 2006.176.08:17:10.38#ibcon#*before return 0, iclass 17, count 0 2006.176.08:17:10.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:17:10.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:17:10.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:17:10.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:17:10.38$vc4f8/va=8,6 2006.176.08:17:10.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.176.08:17:10.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.176.08:17:10.38#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:10.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:17:10.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:17:10.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:17:10.44#ibcon#enter wrdev, iclass 19, count 2 2006.176.08:17:10.44#ibcon#first serial, iclass 19, count 2 2006.176.08:17:10.44#ibcon#enter sib2, iclass 19, count 2 2006.176.08:17:10.44#ibcon#flushed, iclass 19, count 2 2006.176.08:17:10.44#ibcon#about to write, iclass 19, count 2 2006.176.08:17:10.44#ibcon#wrote, iclass 19, count 2 2006.176.08:17:10.44#ibcon#about to read 3, iclass 19, count 2 2006.176.08:17:10.46#ibcon#read 3, iclass 19, count 2 2006.176.08:17:10.46#ibcon#about to read 4, iclass 19, count 2 2006.176.08:17:10.46#ibcon#read 4, iclass 19, count 2 2006.176.08:17:10.46#ibcon#about to read 5, iclass 19, count 2 2006.176.08:17:10.46#ibcon#read 5, iclass 19, count 2 2006.176.08:17:10.46#ibcon#about to read 6, iclass 19, count 2 2006.176.08:17:10.46#ibcon#read 6, iclass 19, count 2 2006.176.08:17:10.46#ibcon#end of sib2, iclass 19, count 2 2006.176.08:17:10.46#ibcon#*mode == 0, iclass 19, count 2 2006.176.08:17:10.46#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.176.08:17:10.46#ibcon#[25=AT08-06\r\n] 2006.176.08:17:10.46#ibcon#*before write, iclass 19, count 2 2006.176.08:17:10.46#ibcon#enter sib2, iclass 19, count 2 2006.176.08:17:10.46#ibcon#flushed, iclass 19, count 2 2006.176.08:17:10.46#ibcon#about to write, iclass 19, count 2 2006.176.08:17:10.46#ibcon#wrote, iclass 19, count 2 2006.176.08:17:10.46#ibcon#about to read 3, iclass 19, count 2 2006.176.08:17:10.49#ibcon#read 3, iclass 19, count 2 2006.176.08:17:10.49#ibcon#about to read 4, iclass 19, count 2 2006.176.08:17:10.49#ibcon#read 4, iclass 19, count 2 2006.176.08:17:10.49#ibcon#about to read 5, iclass 19, count 2 2006.176.08:17:10.49#ibcon#read 5, iclass 19, count 2 2006.176.08:17:10.49#ibcon#about to read 6, iclass 19, count 2 2006.176.08:17:10.49#ibcon#read 6, iclass 19, count 2 2006.176.08:17:10.49#ibcon#end of sib2, iclass 19, count 2 2006.176.08:17:10.49#ibcon#*after write, iclass 19, count 2 2006.176.08:17:10.49#ibcon#*before return 0, iclass 19, count 2 2006.176.08:17:10.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:17:10.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:17:10.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.176.08:17:10.49#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:10.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:17:10.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:17:10.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:17:10.61#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:17:10.61#ibcon#first serial, iclass 19, count 0 2006.176.08:17:10.61#ibcon#enter sib2, iclass 19, count 0 2006.176.08:17:10.61#ibcon#flushed, iclass 19, count 0 2006.176.08:17:10.61#ibcon#about to write, iclass 19, count 0 2006.176.08:17:10.61#ibcon#wrote, iclass 19, count 0 2006.176.08:17:10.61#ibcon#about to read 3, iclass 19, count 0 2006.176.08:17:10.63#ibcon#read 3, iclass 19, count 0 2006.176.08:17:10.63#ibcon#about to read 4, iclass 19, count 0 2006.176.08:17:10.63#ibcon#read 4, iclass 19, count 0 2006.176.08:17:10.63#ibcon#about to read 5, iclass 19, count 0 2006.176.08:17:10.63#ibcon#read 5, iclass 19, count 0 2006.176.08:17:10.63#ibcon#about to read 6, iclass 19, count 0 2006.176.08:17:10.63#ibcon#read 6, iclass 19, count 0 2006.176.08:17:10.63#ibcon#end of sib2, iclass 19, count 0 2006.176.08:17:10.63#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:17:10.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:17:10.63#ibcon#[25=USB\r\n] 2006.176.08:17:10.63#ibcon#*before write, iclass 19, count 0 2006.176.08:17:10.63#ibcon#enter sib2, iclass 19, count 0 2006.176.08:17:10.63#ibcon#flushed, iclass 19, count 0 2006.176.08:17:10.63#ibcon#about to write, iclass 19, count 0 2006.176.08:17:10.63#ibcon#wrote, iclass 19, count 0 2006.176.08:17:10.63#ibcon#about to read 3, iclass 19, count 0 2006.176.08:17:10.66#ibcon#read 3, iclass 19, count 0 2006.176.08:17:10.66#ibcon#about to read 4, iclass 19, count 0 2006.176.08:17:10.66#ibcon#read 4, iclass 19, count 0 2006.176.08:17:10.66#ibcon#about to read 5, iclass 19, count 0 2006.176.08:17:10.66#ibcon#read 5, iclass 19, count 0 2006.176.08:17:10.66#ibcon#about to read 6, iclass 19, count 0 2006.176.08:17:10.66#ibcon#read 6, iclass 19, count 0 2006.176.08:17:10.66#ibcon#end of sib2, iclass 19, count 0 2006.176.08:17:10.66#ibcon#*after write, iclass 19, count 0 2006.176.08:17:10.66#ibcon#*before return 0, iclass 19, count 0 2006.176.08:17:10.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:17:10.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:17:10.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:17:10.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:17:10.66$vc4f8/vblo=1,632.99 2006.176.08:17:10.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.08:17:10.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.08:17:10.66#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:10.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:10.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:10.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:10.66#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:17:10.66#ibcon#first serial, iclass 21, count 0 2006.176.08:17:10.66#ibcon#enter sib2, iclass 21, count 0 2006.176.08:17:10.66#ibcon#flushed, iclass 21, count 0 2006.176.08:17:10.66#ibcon#about to write, iclass 21, count 0 2006.176.08:17:10.66#ibcon#wrote, iclass 21, count 0 2006.176.08:17:10.66#ibcon#about to read 3, iclass 21, count 0 2006.176.08:17:10.68#ibcon#read 3, iclass 21, count 0 2006.176.08:17:10.68#ibcon#about to read 4, iclass 21, count 0 2006.176.08:17:10.68#ibcon#read 4, iclass 21, count 0 2006.176.08:17:10.68#ibcon#about to read 5, iclass 21, count 0 2006.176.08:17:10.68#ibcon#read 5, iclass 21, count 0 2006.176.08:17:10.68#ibcon#about to read 6, iclass 21, count 0 2006.176.08:17:10.68#ibcon#read 6, iclass 21, count 0 2006.176.08:17:10.68#ibcon#end of sib2, iclass 21, count 0 2006.176.08:17:10.68#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:17:10.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:17:10.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:17:10.68#ibcon#*before write, iclass 21, count 0 2006.176.08:17:10.68#ibcon#enter sib2, iclass 21, count 0 2006.176.08:17:10.68#ibcon#flushed, iclass 21, count 0 2006.176.08:17:10.68#ibcon#about to write, iclass 21, count 0 2006.176.08:17:10.68#ibcon#wrote, iclass 21, count 0 2006.176.08:17:10.68#ibcon#about to read 3, iclass 21, count 0 2006.176.08:17:10.72#ibcon#read 3, iclass 21, count 0 2006.176.08:17:10.72#ibcon#about to read 4, iclass 21, count 0 2006.176.08:17:10.72#ibcon#read 4, iclass 21, count 0 2006.176.08:17:10.72#ibcon#about to read 5, iclass 21, count 0 2006.176.08:17:10.72#ibcon#read 5, iclass 21, count 0 2006.176.08:17:10.72#ibcon#about to read 6, iclass 21, count 0 2006.176.08:17:10.72#ibcon#read 6, iclass 21, count 0 2006.176.08:17:10.72#ibcon#end of sib2, iclass 21, count 0 2006.176.08:17:10.72#ibcon#*after write, iclass 21, count 0 2006.176.08:17:10.72#ibcon#*before return 0, iclass 21, count 0 2006.176.08:17:10.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:10.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:17:10.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:17:10.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:17:10.72$vc4f8/vb=1,4 2006.176.08:17:10.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.08:17:10.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.08:17:10.72#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:10.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:10.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:10.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:10.72#ibcon#enter wrdev, iclass 23, count 2 2006.176.08:17:10.72#ibcon#first serial, iclass 23, count 2 2006.176.08:17:10.72#ibcon#enter sib2, iclass 23, count 2 2006.176.08:17:10.72#ibcon#flushed, iclass 23, count 2 2006.176.08:17:10.72#ibcon#about to write, iclass 23, count 2 2006.176.08:17:10.72#ibcon#wrote, iclass 23, count 2 2006.176.08:17:10.72#ibcon#about to read 3, iclass 23, count 2 2006.176.08:17:10.74#ibcon#read 3, iclass 23, count 2 2006.176.08:17:10.74#ibcon#about to read 4, iclass 23, count 2 2006.176.08:17:10.74#ibcon#read 4, iclass 23, count 2 2006.176.08:17:10.74#ibcon#about to read 5, iclass 23, count 2 2006.176.08:17:10.74#ibcon#read 5, iclass 23, count 2 2006.176.08:17:10.74#ibcon#about to read 6, iclass 23, count 2 2006.176.08:17:10.74#ibcon#read 6, iclass 23, count 2 2006.176.08:17:10.74#ibcon#end of sib2, iclass 23, count 2 2006.176.08:17:10.74#ibcon#*mode == 0, iclass 23, count 2 2006.176.08:17:10.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.08:17:10.74#ibcon#[27=AT01-04\r\n] 2006.176.08:17:10.74#ibcon#*before write, iclass 23, count 2 2006.176.08:17:10.74#ibcon#enter sib2, iclass 23, count 2 2006.176.08:17:10.74#ibcon#flushed, iclass 23, count 2 2006.176.08:17:10.74#ibcon#about to write, iclass 23, count 2 2006.176.08:17:10.74#ibcon#wrote, iclass 23, count 2 2006.176.08:17:10.74#ibcon#about to read 3, iclass 23, count 2 2006.176.08:17:10.77#ibcon#read 3, iclass 23, count 2 2006.176.08:17:10.77#ibcon#about to read 4, iclass 23, count 2 2006.176.08:17:10.77#ibcon#read 4, iclass 23, count 2 2006.176.08:17:10.77#ibcon#about to read 5, iclass 23, count 2 2006.176.08:17:10.77#ibcon#read 5, iclass 23, count 2 2006.176.08:17:10.77#ibcon#about to read 6, iclass 23, count 2 2006.176.08:17:10.77#ibcon#read 6, iclass 23, count 2 2006.176.08:17:10.77#ibcon#end of sib2, iclass 23, count 2 2006.176.08:17:10.77#ibcon#*after write, iclass 23, count 2 2006.176.08:17:10.77#ibcon#*before return 0, iclass 23, count 2 2006.176.08:17:10.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:10.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:17:10.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.08:17:10.77#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:10.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:10.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:10.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:10.89#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:17:10.89#ibcon#first serial, iclass 23, count 0 2006.176.08:17:10.89#ibcon#enter sib2, iclass 23, count 0 2006.176.08:17:10.89#ibcon#flushed, iclass 23, count 0 2006.176.08:17:10.89#ibcon#about to write, iclass 23, count 0 2006.176.08:17:10.89#ibcon#wrote, iclass 23, count 0 2006.176.08:17:10.89#ibcon#about to read 3, iclass 23, count 0 2006.176.08:17:10.91#ibcon#read 3, iclass 23, count 0 2006.176.08:17:10.91#ibcon#about to read 4, iclass 23, count 0 2006.176.08:17:10.91#ibcon#read 4, iclass 23, count 0 2006.176.08:17:10.91#ibcon#about to read 5, iclass 23, count 0 2006.176.08:17:10.91#ibcon#read 5, iclass 23, count 0 2006.176.08:17:10.91#ibcon#about to read 6, iclass 23, count 0 2006.176.08:17:10.91#ibcon#read 6, iclass 23, count 0 2006.176.08:17:10.91#ibcon#end of sib2, iclass 23, count 0 2006.176.08:17:10.91#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:17:10.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:17:10.91#ibcon#[27=USB\r\n] 2006.176.08:17:10.91#ibcon#*before write, iclass 23, count 0 2006.176.08:17:10.91#ibcon#enter sib2, iclass 23, count 0 2006.176.08:17:10.91#ibcon#flushed, iclass 23, count 0 2006.176.08:17:10.91#ibcon#about to write, iclass 23, count 0 2006.176.08:17:10.91#ibcon#wrote, iclass 23, count 0 2006.176.08:17:10.91#ibcon#about to read 3, iclass 23, count 0 2006.176.08:17:10.94#ibcon#read 3, iclass 23, count 0 2006.176.08:17:10.94#ibcon#about to read 4, iclass 23, count 0 2006.176.08:17:10.94#ibcon#read 4, iclass 23, count 0 2006.176.08:17:10.94#ibcon#about to read 5, iclass 23, count 0 2006.176.08:17:10.94#ibcon#read 5, iclass 23, count 0 2006.176.08:17:10.94#ibcon#about to read 6, iclass 23, count 0 2006.176.08:17:10.94#ibcon#read 6, iclass 23, count 0 2006.176.08:17:10.94#ibcon#end of sib2, iclass 23, count 0 2006.176.08:17:10.94#ibcon#*after write, iclass 23, count 0 2006.176.08:17:10.94#ibcon#*before return 0, iclass 23, count 0 2006.176.08:17:10.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:10.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:17:10.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:17:10.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:17:10.94$vc4f8/vblo=2,640.99 2006.176.08:17:10.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.08:17:10.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.08:17:10.94#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:10.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:10.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:10.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:10.94#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:17:10.94#ibcon#first serial, iclass 25, count 0 2006.176.08:17:10.94#ibcon#enter sib2, iclass 25, count 0 2006.176.08:17:10.94#ibcon#flushed, iclass 25, count 0 2006.176.08:17:10.94#ibcon#about to write, iclass 25, count 0 2006.176.08:17:10.94#ibcon#wrote, iclass 25, count 0 2006.176.08:17:10.94#ibcon#about to read 3, iclass 25, count 0 2006.176.08:17:10.96#ibcon#read 3, iclass 25, count 0 2006.176.08:17:10.96#ibcon#about to read 4, iclass 25, count 0 2006.176.08:17:10.96#ibcon#read 4, iclass 25, count 0 2006.176.08:17:10.96#ibcon#about to read 5, iclass 25, count 0 2006.176.08:17:10.96#ibcon#read 5, iclass 25, count 0 2006.176.08:17:10.96#ibcon#about to read 6, iclass 25, count 0 2006.176.08:17:10.96#ibcon#read 6, iclass 25, count 0 2006.176.08:17:10.96#ibcon#end of sib2, iclass 25, count 0 2006.176.08:17:10.96#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:17:10.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:17:10.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:17:10.96#ibcon#*before write, iclass 25, count 0 2006.176.08:17:10.96#ibcon#enter sib2, iclass 25, count 0 2006.176.08:17:10.96#ibcon#flushed, iclass 25, count 0 2006.176.08:17:10.96#ibcon#about to write, iclass 25, count 0 2006.176.08:17:10.96#ibcon#wrote, iclass 25, count 0 2006.176.08:17:10.96#ibcon#about to read 3, iclass 25, count 0 2006.176.08:17:11.00#ibcon#read 3, iclass 25, count 0 2006.176.08:17:11.00#ibcon#about to read 4, iclass 25, count 0 2006.176.08:17:11.00#ibcon#read 4, iclass 25, count 0 2006.176.08:17:11.00#ibcon#about to read 5, iclass 25, count 0 2006.176.08:17:11.00#ibcon#read 5, iclass 25, count 0 2006.176.08:17:11.00#ibcon#about to read 6, iclass 25, count 0 2006.176.08:17:11.00#ibcon#read 6, iclass 25, count 0 2006.176.08:17:11.00#ibcon#end of sib2, iclass 25, count 0 2006.176.08:17:11.00#ibcon#*after write, iclass 25, count 0 2006.176.08:17:11.00#ibcon#*before return 0, iclass 25, count 0 2006.176.08:17:11.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:11.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:17:11.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:17:11.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:17:11.00$vc4f8/vb=2,4 2006.176.08:17:11.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.08:17:11.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.08:17:11.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:11.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:11.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:11.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:11.06#ibcon#enter wrdev, iclass 27, count 2 2006.176.08:17:11.06#ibcon#first serial, iclass 27, count 2 2006.176.08:17:11.06#ibcon#enter sib2, iclass 27, count 2 2006.176.08:17:11.06#ibcon#flushed, iclass 27, count 2 2006.176.08:17:11.06#ibcon#about to write, iclass 27, count 2 2006.176.08:17:11.06#ibcon#wrote, iclass 27, count 2 2006.176.08:17:11.06#ibcon#about to read 3, iclass 27, count 2 2006.176.08:17:11.08#ibcon#read 3, iclass 27, count 2 2006.176.08:17:11.08#ibcon#about to read 4, iclass 27, count 2 2006.176.08:17:11.08#ibcon#read 4, iclass 27, count 2 2006.176.08:17:11.08#ibcon#about to read 5, iclass 27, count 2 2006.176.08:17:11.08#ibcon#read 5, iclass 27, count 2 2006.176.08:17:11.08#ibcon#about to read 6, iclass 27, count 2 2006.176.08:17:11.08#ibcon#read 6, iclass 27, count 2 2006.176.08:17:11.08#ibcon#end of sib2, iclass 27, count 2 2006.176.08:17:11.08#ibcon#*mode == 0, iclass 27, count 2 2006.176.08:17:11.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.08:17:11.08#ibcon#[27=AT02-04\r\n] 2006.176.08:17:11.08#ibcon#*before write, iclass 27, count 2 2006.176.08:17:11.08#ibcon#enter sib2, iclass 27, count 2 2006.176.08:17:11.08#ibcon#flushed, iclass 27, count 2 2006.176.08:17:11.08#ibcon#about to write, iclass 27, count 2 2006.176.08:17:11.08#ibcon#wrote, iclass 27, count 2 2006.176.08:17:11.08#ibcon#about to read 3, iclass 27, count 2 2006.176.08:17:11.11#ibcon#read 3, iclass 27, count 2 2006.176.08:17:11.11#ibcon#about to read 4, iclass 27, count 2 2006.176.08:17:11.11#ibcon#read 4, iclass 27, count 2 2006.176.08:17:11.11#ibcon#about to read 5, iclass 27, count 2 2006.176.08:17:11.11#ibcon#read 5, iclass 27, count 2 2006.176.08:17:11.11#ibcon#about to read 6, iclass 27, count 2 2006.176.08:17:11.11#ibcon#read 6, iclass 27, count 2 2006.176.08:17:11.11#ibcon#end of sib2, iclass 27, count 2 2006.176.08:17:11.11#ibcon#*after write, iclass 27, count 2 2006.176.08:17:11.11#ibcon#*before return 0, iclass 27, count 2 2006.176.08:17:11.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:11.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:17:11.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.08:17:11.11#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:11.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:11.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:11.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:11.23#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:17:11.23#ibcon#first serial, iclass 27, count 0 2006.176.08:17:11.23#ibcon#enter sib2, iclass 27, count 0 2006.176.08:17:11.23#ibcon#flushed, iclass 27, count 0 2006.176.08:17:11.23#ibcon#about to write, iclass 27, count 0 2006.176.08:17:11.23#ibcon#wrote, iclass 27, count 0 2006.176.08:17:11.23#ibcon#about to read 3, iclass 27, count 0 2006.176.08:17:11.25#ibcon#read 3, iclass 27, count 0 2006.176.08:17:11.25#ibcon#about to read 4, iclass 27, count 0 2006.176.08:17:11.25#ibcon#read 4, iclass 27, count 0 2006.176.08:17:11.25#ibcon#about to read 5, iclass 27, count 0 2006.176.08:17:11.25#ibcon#read 5, iclass 27, count 0 2006.176.08:17:11.25#ibcon#about to read 6, iclass 27, count 0 2006.176.08:17:11.25#ibcon#read 6, iclass 27, count 0 2006.176.08:17:11.25#ibcon#end of sib2, iclass 27, count 0 2006.176.08:17:11.25#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:17:11.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:17:11.25#ibcon#[27=USB\r\n] 2006.176.08:17:11.25#ibcon#*before write, iclass 27, count 0 2006.176.08:17:11.25#ibcon#enter sib2, iclass 27, count 0 2006.176.08:17:11.25#ibcon#flushed, iclass 27, count 0 2006.176.08:17:11.25#ibcon#about to write, iclass 27, count 0 2006.176.08:17:11.25#ibcon#wrote, iclass 27, count 0 2006.176.08:17:11.25#ibcon#about to read 3, iclass 27, count 0 2006.176.08:17:11.28#ibcon#read 3, iclass 27, count 0 2006.176.08:17:11.28#ibcon#about to read 4, iclass 27, count 0 2006.176.08:17:11.28#ibcon#read 4, iclass 27, count 0 2006.176.08:17:11.28#ibcon#about to read 5, iclass 27, count 0 2006.176.08:17:11.28#ibcon#read 5, iclass 27, count 0 2006.176.08:17:11.28#ibcon#about to read 6, iclass 27, count 0 2006.176.08:17:11.28#ibcon#read 6, iclass 27, count 0 2006.176.08:17:11.28#ibcon#end of sib2, iclass 27, count 0 2006.176.08:17:11.28#ibcon#*after write, iclass 27, count 0 2006.176.08:17:11.28#ibcon#*before return 0, iclass 27, count 0 2006.176.08:17:11.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:11.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:17:11.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:17:11.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:17:11.28$vc4f8/vblo=3,656.99 2006.176.08:17:11.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.08:17:11.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.08:17:11.28#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:11.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:11.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:11.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:11.28#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:17:11.28#ibcon#first serial, iclass 29, count 0 2006.176.08:17:11.28#ibcon#enter sib2, iclass 29, count 0 2006.176.08:17:11.28#ibcon#flushed, iclass 29, count 0 2006.176.08:17:11.28#ibcon#about to write, iclass 29, count 0 2006.176.08:17:11.28#ibcon#wrote, iclass 29, count 0 2006.176.08:17:11.28#ibcon#about to read 3, iclass 29, count 0 2006.176.08:17:11.30#ibcon#read 3, iclass 29, count 0 2006.176.08:17:11.30#ibcon#about to read 4, iclass 29, count 0 2006.176.08:17:11.30#ibcon#read 4, iclass 29, count 0 2006.176.08:17:11.30#ibcon#about to read 5, iclass 29, count 0 2006.176.08:17:11.30#ibcon#read 5, iclass 29, count 0 2006.176.08:17:11.30#ibcon#about to read 6, iclass 29, count 0 2006.176.08:17:11.30#ibcon#read 6, iclass 29, count 0 2006.176.08:17:11.30#ibcon#end of sib2, iclass 29, count 0 2006.176.08:17:11.30#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:17:11.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:17:11.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:17:11.30#ibcon#*before write, iclass 29, count 0 2006.176.08:17:11.30#ibcon#enter sib2, iclass 29, count 0 2006.176.08:17:11.30#ibcon#flushed, iclass 29, count 0 2006.176.08:17:11.30#ibcon#about to write, iclass 29, count 0 2006.176.08:17:11.30#ibcon#wrote, iclass 29, count 0 2006.176.08:17:11.30#ibcon#about to read 3, iclass 29, count 0 2006.176.08:17:11.34#ibcon#read 3, iclass 29, count 0 2006.176.08:17:11.34#ibcon#about to read 4, iclass 29, count 0 2006.176.08:17:11.34#ibcon#read 4, iclass 29, count 0 2006.176.08:17:11.34#ibcon#about to read 5, iclass 29, count 0 2006.176.08:17:11.34#ibcon#read 5, iclass 29, count 0 2006.176.08:17:11.34#ibcon#about to read 6, iclass 29, count 0 2006.176.08:17:11.34#ibcon#read 6, iclass 29, count 0 2006.176.08:17:11.34#ibcon#end of sib2, iclass 29, count 0 2006.176.08:17:11.34#ibcon#*after write, iclass 29, count 0 2006.176.08:17:11.34#ibcon#*before return 0, iclass 29, count 0 2006.176.08:17:11.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:11.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:17:11.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:17:11.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:17:11.34$vc4f8/vb=3,4 2006.176.08:17:11.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.08:17:11.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.08:17:11.34#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:11.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:11.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:11.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:11.40#ibcon#enter wrdev, iclass 31, count 2 2006.176.08:17:11.40#ibcon#first serial, iclass 31, count 2 2006.176.08:17:11.40#ibcon#enter sib2, iclass 31, count 2 2006.176.08:17:11.40#ibcon#flushed, iclass 31, count 2 2006.176.08:17:11.40#ibcon#about to write, iclass 31, count 2 2006.176.08:17:11.40#ibcon#wrote, iclass 31, count 2 2006.176.08:17:11.40#ibcon#about to read 3, iclass 31, count 2 2006.176.08:17:11.42#ibcon#read 3, iclass 31, count 2 2006.176.08:17:11.42#ibcon#about to read 4, iclass 31, count 2 2006.176.08:17:11.42#ibcon#read 4, iclass 31, count 2 2006.176.08:17:11.42#ibcon#about to read 5, iclass 31, count 2 2006.176.08:17:11.42#ibcon#read 5, iclass 31, count 2 2006.176.08:17:11.42#ibcon#about to read 6, iclass 31, count 2 2006.176.08:17:11.42#ibcon#read 6, iclass 31, count 2 2006.176.08:17:11.42#ibcon#end of sib2, iclass 31, count 2 2006.176.08:17:11.42#ibcon#*mode == 0, iclass 31, count 2 2006.176.08:17:11.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.08:17:11.42#ibcon#[27=AT03-04\r\n] 2006.176.08:17:11.42#ibcon#*before write, iclass 31, count 2 2006.176.08:17:11.42#ibcon#enter sib2, iclass 31, count 2 2006.176.08:17:11.42#ibcon#flushed, iclass 31, count 2 2006.176.08:17:11.42#ibcon#about to write, iclass 31, count 2 2006.176.08:17:11.42#ibcon#wrote, iclass 31, count 2 2006.176.08:17:11.42#ibcon#about to read 3, iclass 31, count 2 2006.176.08:17:11.45#ibcon#read 3, iclass 31, count 2 2006.176.08:17:11.45#ibcon#about to read 4, iclass 31, count 2 2006.176.08:17:11.45#ibcon#read 4, iclass 31, count 2 2006.176.08:17:11.45#ibcon#about to read 5, iclass 31, count 2 2006.176.08:17:11.45#ibcon#read 5, iclass 31, count 2 2006.176.08:17:11.45#ibcon#about to read 6, iclass 31, count 2 2006.176.08:17:11.45#ibcon#read 6, iclass 31, count 2 2006.176.08:17:11.45#ibcon#end of sib2, iclass 31, count 2 2006.176.08:17:11.45#ibcon#*after write, iclass 31, count 2 2006.176.08:17:11.45#ibcon#*before return 0, iclass 31, count 2 2006.176.08:17:11.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:11.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:17:11.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.08:17:11.45#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:11.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:11.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:11.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:11.57#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:17:11.57#ibcon#first serial, iclass 31, count 0 2006.176.08:17:11.57#ibcon#enter sib2, iclass 31, count 0 2006.176.08:17:11.57#ibcon#flushed, iclass 31, count 0 2006.176.08:17:11.57#ibcon#about to write, iclass 31, count 0 2006.176.08:17:11.57#ibcon#wrote, iclass 31, count 0 2006.176.08:17:11.57#ibcon#about to read 3, iclass 31, count 0 2006.176.08:17:11.59#ibcon#read 3, iclass 31, count 0 2006.176.08:17:11.59#ibcon#about to read 4, iclass 31, count 0 2006.176.08:17:11.59#ibcon#read 4, iclass 31, count 0 2006.176.08:17:11.59#ibcon#about to read 5, iclass 31, count 0 2006.176.08:17:11.59#ibcon#read 5, iclass 31, count 0 2006.176.08:17:11.59#ibcon#about to read 6, iclass 31, count 0 2006.176.08:17:11.59#ibcon#read 6, iclass 31, count 0 2006.176.08:17:11.59#ibcon#end of sib2, iclass 31, count 0 2006.176.08:17:11.59#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:17:11.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:17:11.59#ibcon#[27=USB\r\n] 2006.176.08:17:11.59#ibcon#*before write, iclass 31, count 0 2006.176.08:17:11.59#ibcon#enter sib2, iclass 31, count 0 2006.176.08:17:11.59#ibcon#flushed, iclass 31, count 0 2006.176.08:17:11.59#ibcon#about to write, iclass 31, count 0 2006.176.08:17:11.59#ibcon#wrote, iclass 31, count 0 2006.176.08:17:11.59#ibcon#about to read 3, iclass 31, count 0 2006.176.08:17:11.62#ibcon#read 3, iclass 31, count 0 2006.176.08:17:11.62#ibcon#about to read 4, iclass 31, count 0 2006.176.08:17:11.62#ibcon#read 4, iclass 31, count 0 2006.176.08:17:11.62#ibcon#about to read 5, iclass 31, count 0 2006.176.08:17:11.62#ibcon#read 5, iclass 31, count 0 2006.176.08:17:11.62#ibcon#about to read 6, iclass 31, count 0 2006.176.08:17:11.62#ibcon#read 6, iclass 31, count 0 2006.176.08:17:11.62#ibcon#end of sib2, iclass 31, count 0 2006.176.08:17:11.62#ibcon#*after write, iclass 31, count 0 2006.176.08:17:11.62#ibcon#*before return 0, iclass 31, count 0 2006.176.08:17:11.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:11.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:17:11.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:17:11.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:17:11.62$vc4f8/vblo=4,712.99 2006.176.08:17:11.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.08:17:11.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.08:17:11.62#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:11.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:11.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:11.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:11.62#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:17:11.62#ibcon#first serial, iclass 33, count 0 2006.176.08:17:11.62#ibcon#enter sib2, iclass 33, count 0 2006.176.08:17:11.62#ibcon#flushed, iclass 33, count 0 2006.176.08:17:11.62#ibcon#about to write, iclass 33, count 0 2006.176.08:17:11.62#ibcon#wrote, iclass 33, count 0 2006.176.08:17:11.62#ibcon#about to read 3, iclass 33, count 0 2006.176.08:17:11.64#ibcon#read 3, iclass 33, count 0 2006.176.08:17:11.64#ibcon#about to read 4, iclass 33, count 0 2006.176.08:17:11.64#ibcon#read 4, iclass 33, count 0 2006.176.08:17:11.64#ibcon#about to read 5, iclass 33, count 0 2006.176.08:17:11.64#ibcon#read 5, iclass 33, count 0 2006.176.08:17:11.64#ibcon#about to read 6, iclass 33, count 0 2006.176.08:17:11.64#ibcon#read 6, iclass 33, count 0 2006.176.08:17:11.64#ibcon#end of sib2, iclass 33, count 0 2006.176.08:17:11.64#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:17:11.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:17:11.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:17:11.64#ibcon#*before write, iclass 33, count 0 2006.176.08:17:11.64#ibcon#enter sib2, iclass 33, count 0 2006.176.08:17:11.64#ibcon#flushed, iclass 33, count 0 2006.176.08:17:11.64#ibcon#about to write, iclass 33, count 0 2006.176.08:17:11.64#ibcon#wrote, iclass 33, count 0 2006.176.08:17:11.64#ibcon#about to read 3, iclass 33, count 0 2006.176.08:17:11.68#ibcon#read 3, iclass 33, count 0 2006.176.08:17:11.68#ibcon#about to read 4, iclass 33, count 0 2006.176.08:17:11.68#ibcon#read 4, iclass 33, count 0 2006.176.08:17:11.68#ibcon#about to read 5, iclass 33, count 0 2006.176.08:17:11.68#ibcon#read 5, iclass 33, count 0 2006.176.08:17:11.68#ibcon#about to read 6, iclass 33, count 0 2006.176.08:17:11.68#ibcon#read 6, iclass 33, count 0 2006.176.08:17:11.68#ibcon#end of sib2, iclass 33, count 0 2006.176.08:17:11.68#ibcon#*after write, iclass 33, count 0 2006.176.08:17:11.68#ibcon#*before return 0, iclass 33, count 0 2006.176.08:17:11.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:11.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:17:11.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:17:11.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:17:11.68$vc4f8/vb=4,4 2006.176.08:17:11.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.176.08:17:11.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.176.08:17:11.68#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:11.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:11.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:11.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:11.74#ibcon#enter wrdev, iclass 35, count 2 2006.176.08:17:11.74#ibcon#first serial, iclass 35, count 2 2006.176.08:17:11.74#ibcon#enter sib2, iclass 35, count 2 2006.176.08:17:11.74#ibcon#flushed, iclass 35, count 2 2006.176.08:17:11.74#ibcon#about to write, iclass 35, count 2 2006.176.08:17:11.74#ibcon#wrote, iclass 35, count 2 2006.176.08:17:11.74#ibcon#about to read 3, iclass 35, count 2 2006.176.08:17:11.76#ibcon#read 3, iclass 35, count 2 2006.176.08:17:11.76#ibcon#about to read 4, iclass 35, count 2 2006.176.08:17:11.76#ibcon#read 4, iclass 35, count 2 2006.176.08:17:11.76#ibcon#about to read 5, iclass 35, count 2 2006.176.08:17:11.76#ibcon#read 5, iclass 35, count 2 2006.176.08:17:11.76#ibcon#about to read 6, iclass 35, count 2 2006.176.08:17:11.76#ibcon#read 6, iclass 35, count 2 2006.176.08:17:11.76#ibcon#end of sib2, iclass 35, count 2 2006.176.08:17:11.76#ibcon#*mode == 0, iclass 35, count 2 2006.176.08:17:11.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.176.08:17:11.76#ibcon#[27=AT04-04\r\n] 2006.176.08:17:11.76#ibcon#*before write, iclass 35, count 2 2006.176.08:17:11.76#ibcon#enter sib2, iclass 35, count 2 2006.176.08:17:11.76#ibcon#flushed, iclass 35, count 2 2006.176.08:17:11.76#ibcon#about to write, iclass 35, count 2 2006.176.08:17:11.76#ibcon#wrote, iclass 35, count 2 2006.176.08:17:11.76#ibcon#about to read 3, iclass 35, count 2 2006.176.08:17:11.79#ibcon#read 3, iclass 35, count 2 2006.176.08:17:11.79#ibcon#about to read 4, iclass 35, count 2 2006.176.08:17:11.79#ibcon#read 4, iclass 35, count 2 2006.176.08:17:11.79#ibcon#about to read 5, iclass 35, count 2 2006.176.08:17:11.79#ibcon#read 5, iclass 35, count 2 2006.176.08:17:11.79#ibcon#about to read 6, iclass 35, count 2 2006.176.08:17:11.79#ibcon#read 6, iclass 35, count 2 2006.176.08:17:11.79#ibcon#end of sib2, iclass 35, count 2 2006.176.08:17:11.79#ibcon#*after write, iclass 35, count 2 2006.176.08:17:11.79#ibcon#*before return 0, iclass 35, count 2 2006.176.08:17:11.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:11.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:17:11.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.176.08:17:11.79#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:11.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:11.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:11.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:11.91#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:17:11.91#ibcon#first serial, iclass 35, count 0 2006.176.08:17:11.91#ibcon#enter sib2, iclass 35, count 0 2006.176.08:17:11.91#ibcon#flushed, iclass 35, count 0 2006.176.08:17:11.91#ibcon#about to write, iclass 35, count 0 2006.176.08:17:11.91#ibcon#wrote, iclass 35, count 0 2006.176.08:17:11.91#ibcon#about to read 3, iclass 35, count 0 2006.176.08:17:11.93#ibcon#read 3, iclass 35, count 0 2006.176.08:17:11.93#ibcon#about to read 4, iclass 35, count 0 2006.176.08:17:11.93#ibcon#read 4, iclass 35, count 0 2006.176.08:17:11.93#ibcon#about to read 5, iclass 35, count 0 2006.176.08:17:11.93#ibcon#read 5, iclass 35, count 0 2006.176.08:17:11.93#ibcon#about to read 6, iclass 35, count 0 2006.176.08:17:11.93#ibcon#read 6, iclass 35, count 0 2006.176.08:17:11.93#ibcon#end of sib2, iclass 35, count 0 2006.176.08:17:11.93#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:17:11.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:17:11.93#ibcon#[27=USB\r\n] 2006.176.08:17:11.93#ibcon#*before write, iclass 35, count 0 2006.176.08:17:11.93#ibcon#enter sib2, iclass 35, count 0 2006.176.08:17:11.93#ibcon#flushed, iclass 35, count 0 2006.176.08:17:11.93#ibcon#about to write, iclass 35, count 0 2006.176.08:17:11.93#ibcon#wrote, iclass 35, count 0 2006.176.08:17:11.93#ibcon#about to read 3, iclass 35, count 0 2006.176.08:17:11.96#ibcon#read 3, iclass 35, count 0 2006.176.08:17:11.96#ibcon#about to read 4, iclass 35, count 0 2006.176.08:17:11.96#ibcon#read 4, iclass 35, count 0 2006.176.08:17:11.96#ibcon#about to read 5, iclass 35, count 0 2006.176.08:17:11.96#ibcon#read 5, iclass 35, count 0 2006.176.08:17:11.96#ibcon#about to read 6, iclass 35, count 0 2006.176.08:17:11.96#ibcon#read 6, iclass 35, count 0 2006.176.08:17:11.96#ibcon#end of sib2, iclass 35, count 0 2006.176.08:17:11.96#ibcon#*after write, iclass 35, count 0 2006.176.08:17:11.96#ibcon#*before return 0, iclass 35, count 0 2006.176.08:17:11.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:11.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:17:11.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:17:11.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:17:11.96$vc4f8/vblo=5,744.99 2006.176.08:17:11.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.176.08:17:11.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.176.08:17:11.96#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:11.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:11.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:11.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:11.96#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:17:11.96#ibcon#first serial, iclass 37, count 0 2006.176.08:17:11.96#ibcon#enter sib2, iclass 37, count 0 2006.176.08:17:11.96#ibcon#flushed, iclass 37, count 0 2006.176.08:17:11.96#ibcon#about to write, iclass 37, count 0 2006.176.08:17:11.96#ibcon#wrote, iclass 37, count 0 2006.176.08:17:11.96#ibcon#about to read 3, iclass 37, count 0 2006.176.08:17:11.98#ibcon#read 3, iclass 37, count 0 2006.176.08:17:11.98#ibcon#about to read 4, iclass 37, count 0 2006.176.08:17:11.98#ibcon#read 4, iclass 37, count 0 2006.176.08:17:11.98#ibcon#about to read 5, iclass 37, count 0 2006.176.08:17:11.98#ibcon#read 5, iclass 37, count 0 2006.176.08:17:11.98#ibcon#about to read 6, iclass 37, count 0 2006.176.08:17:11.98#ibcon#read 6, iclass 37, count 0 2006.176.08:17:11.98#ibcon#end of sib2, iclass 37, count 0 2006.176.08:17:11.98#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:17:11.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:17:11.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:17:11.98#ibcon#*before write, iclass 37, count 0 2006.176.08:17:11.98#ibcon#enter sib2, iclass 37, count 0 2006.176.08:17:11.98#ibcon#flushed, iclass 37, count 0 2006.176.08:17:11.98#ibcon#about to write, iclass 37, count 0 2006.176.08:17:11.98#ibcon#wrote, iclass 37, count 0 2006.176.08:17:11.98#ibcon#about to read 3, iclass 37, count 0 2006.176.08:17:12.02#ibcon#read 3, iclass 37, count 0 2006.176.08:17:12.02#ibcon#about to read 4, iclass 37, count 0 2006.176.08:17:12.02#ibcon#read 4, iclass 37, count 0 2006.176.08:17:12.02#ibcon#about to read 5, iclass 37, count 0 2006.176.08:17:12.02#ibcon#read 5, iclass 37, count 0 2006.176.08:17:12.02#ibcon#about to read 6, iclass 37, count 0 2006.176.08:17:12.02#ibcon#read 6, iclass 37, count 0 2006.176.08:17:12.02#ibcon#end of sib2, iclass 37, count 0 2006.176.08:17:12.02#ibcon#*after write, iclass 37, count 0 2006.176.08:17:12.02#ibcon#*before return 0, iclass 37, count 0 2006.176.08:17:12.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:12.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:17:12.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:17:12.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:17:12.02$vc4f8/vb=5,4 2006.176.08:17:12.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.176.08:17:12.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.176.08:17:12.02#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:12.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:12.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:12.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:12.08#ibcon#enter wrdev, iclass 39, count 2 2006.176.08:17:12.08#ibcon#first serial, iclass 39, count 2 2006.176.08:17:12.08#ibcon#enter sib2, iclass 39, count 2 2006.176.08:17:12.08#ibcon#flushed, iclass 39, count 2 2006.176.08:17:12.08#ibcon#about to write, iclass 39, count 2 2006.176.08:17:12.08#ibcon#wrote, iclass 39, count 2 2006.176.08:17:12.08#ibcon#about to read 3, iclass 39, count 2 2006.176.08:17:12.10#ibcon#read 3, iclass 39, count 2 2006.176.08:17:12.10#ibcon#about to read 4, iclass 39, count 2 2006.176.08:17:12.10#ibcon#read 4, iclass 39, count 2 2006.176.08:17:12.10#ibcon#about to read 5, iclass 39, count 2 2006.176.08:17:12.10#ibcon#read 5, iclass 39, count 2 2006.176.08:17:12.10#ibcon#about to read 6, iclass 39, count 2 2006.176.08:17:12.10#ibcon#read 6, iclass 39, count 2 2006.176.08:17:12.10#ibcon#end of sib2, iclass 39, count 2 2006.176.08:17:12.10#ibcon#*mode == 0, iclass 39, count 2 2006.176.08:17:12.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.176.08:17:12.10#ibcon#[27=AT05-04\r\n] 2006.176.08:17:12.10#ibcon#*before write, iclass 39, count 2 2006.176.08:17:12.10#ibcon#enter sib2, iclass 39, count 2 2006.176.08:17:12.10#ibcon#flushed, iclass 39, count 2 2006.176.08:17:12.10#ibcon#about to write, iclass 39, count 2 2006.176.08:17:12.10#ibcon#wrote, iclass 39, count 2 2006.176.08:17:12.10#ibcon#about to read 3, iclass 39, count 2 2006.176.08:17:12.13#ibcon#read 3, iclass 39, count 2 2006.176.08:17:12.13#ibcon#about to read 4, iclass 39, count 2 2006.176.08:17:12.13#ibcon#read 4, iclass 39, count 2 2006.176.08:17:12.13#ibcon#about to read 5, iclass 39, count 2 2006.176.08:17:12.13#ibcon#read 5, iclass 39, count 2 2006.176.08:17:12.13#ibcon#about to read 6, iclass 39, count 2 2006.176.08:17:12.13#ibcon#read 6, iclass 39, count 2 2006.176.08:17:12.13#ibcon#end of sib2, iclass 39, count 2 2006.176.08:17:12.13#ibcon#*after write, iclass 39, count 2 2006.176.08:17:12.13#ibcon#*before return 0, iclass 39, count 2 2006.176.08:17:12.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:12.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:17:12.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.176.08:17:12.13#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:12.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:12.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:12.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:12.25#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:17:12.25#ibcon#first serial, iclass 39, count 0 2006.176.08:17:12.25#ibcon#enter sib2, iclass 39, count 0 2006.176.08:17:12.25#ibcon#flushed, iclass 39, count 0 2006.176.08:17:12.25#ibcon#about to write, iclass 39, count 0 2006.176.08:17:12.25#ibcon#wrote, iclass 39, count 0 2006.176.08:17:12.25#ibcon#about to read 3, iclass 39, count 0 2006.176.08:17:12.27#ibcon#read 3, iclass 39, count 0 2006.176.08:17:12.27#ibcon#about to read 4, iclass 39, count 0 2006.176.08:17:12.27#ibcon#read 4, iclass 39, count 0 2006.176.08:17:12.27#ibcon#about to read 5, iclass 39, count 0 2006.176.08:17:12.27#ibcon#read 5, iclass 39, count 0 2006.176.08:17:12.27#ibcon#about to read 6, iclass 39, count 0 2006.176.08:17:12.27#ibcon#read 6, iclass 39, count 0 2006.176.08:17:12.27#ibcon#end of sib2, iclass 39, count 0 2006.176.08:17:12.27#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:17:12.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:17:12.27#ibcon#[27=USB\r\n] 2006.176.08:17:12.27#ibcon#*before write, iclass 39, count 0 2006.176.08:17:12.27#ibcon#enter sib2, iclass 39, count 0 2006.176.08:17:12.27#ibcon#flushed, iclass 39, count 0 2006.176.08:17:12.27#ibcon#about to write, iclass 39, count 0 2006.176.08:17:12.27#ibcon#wrote, iclass 39, count 0 2006.176.08:17:12.27#ibcon#about to read 3, iclass 39, count 0 2006.176.08:17:12.30#ibcon#read 3, iclass 39, count 0 2006.176.08:17:12.30#ibcon#about to read 4, iclass 39, count 0 2006.176.08:17:12.30#ibcon#read 4, iclass 39, count 0 2006.176.08:17:12.30#ibcon#about to read 5, iclass 39, count 0 2006.176.08:17:12.30#ibcon#read 5, iclass 39, count 0 2006.176.08:17:12.30#ibcon#about to read 6, iclass 39, count 0 2006.176.08:17:12.30#ibcon#read 6, iclass 39, count 0 2006.176.08:17:12.30#ibcon#end of sib2, iclass 39, count 0 2006.176.08:17:12.30#ibcon#*after write, iclass 39, count 0 2006.176.08:17:12.30#ibcon#*before return 0, iclass 39, count 0 2006.176.08:17:12.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:12.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:17:12.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:17:12.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:17:12.30$vc4f8/vblo=6,752.99 2006.176.08:17:12.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.08:17:12.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.08:17:12.30#ibcon#ireg 17 cls_cnt 0 2006.176.08:17:12.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:12.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:12.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:12.30#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:17:12.30#ibcon#first serial, iclass 3, count 0 2006.176.08:17:12.30#ibcon#enter sib2, iclass 3, count 0 2006.176.08:17:12.30#ibcon#flushed, iclass 3, count 0 2006.176.08:17:12.30#ibcon#about to write, iclass 3, count 0 2006.176.08:17:12.30#ibcon#wrote, iclass 3, count 0 2006.176.08:17:12.30#ibcon#about to read 3, iclass 3, count 0 2006.176.08:17:12.32#ibcon#read 3, iclass 3, count 0 2006.176.08:17:12.32#ibcon#about to read 4, iclass 3, count 0 2006.176.08:17:12.32#ibcon#read 4, iclass 3, count 0 2006.176.08:17:12.32#ibcon#about to read 5, iclass 3, count 0 2006.176.08:17:12.32#ibcon#read 5, iclass 3, count 0 2006.176.08:17:12.32#ibcon#about to read 6, iclass 3, count 0 2006.176.08:17:12.32#ibcon#read 6, iclass 3, count 0 2006.176.08:17:12.32#ibcon#end of sib2, iclass 3, count 0 2006.176.08:17:12.32#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:17:12.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:17:12.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:17:12.32#ibcon#*before write, iclass 3, count 0 2006.176.08:17:12.32#ibcon#enter sib2, iclass 3, count 0 2006.176.08:17:12.32#ibcon#flushed, iclass 3, count 0 2006.176.08:17:12.32#ibcon#about to write, iclass 3, count 0 2006.176.08:17:12.32#ibcon#wrote, iclass 3, count 0 2006.176.08:17:12.32#ibcon#about to read 3, iclass 3, count 0 2006.176.08:17:12.36#ibcon#read 3, iclass 3, count 0 2006.176.08:17:12.36#ibcon#about to read 4, iclass 3, count 0 2006.176.08:17:12.36#ibcon#read 4, iclass 3, count 0 2006.176.08:17:12.36#ibcon#about to read 5, iclass 3, count 0 2006.176.08:17:12.36#ibcon#read 5, iclass 3, count 0 2006.176.08:17:12.36#ibcon#about to read 6, iclass 3, count 0 2006.176.08:17:12.36#ibcon#read 6, iclass 3, count 0 2006.176.08:17:12.36#ibcon#end of sib2, iclass 3, count 0 2006.176.08:17:12.36#ibcon#*after write, iclass 3, count 0 2006.176.08:17:12.36#ibcon#*before return 0, iclass 3, count 0 2006.176.08:17:12.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:12.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:17:12.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:17:12.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:17:12.36$vc4f8/vb=6,4 2006.176.08:17:12.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.176.08:17:12.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.176.08:17:12.36#ibcon#ireg 11 cls_cnt 2 2006.176.08:17:12.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:12.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:12.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:12.42#ibcon#enter wrdev, iclass 5, count 2 2006.176.08:17:12.42#ibcon#first serial, iclass 5, count 2 2006.176.08:17:12.42#ibcon#enter sib2, iclass 5, count 2 2006.176.08:17:12.42#ibcon#flushed, iclass 5, count 2 2006.176.08:17:12.42#ibcon#about to write, iclass 5, count 2 2006.176.08:17:12.42#ibcon#wrote, iclass 5, count 2 2006.176.08:17:12.42#ibcon#about to read 3, iclass 5, count 2 2006.176.08:17:12.44#ibcon#read 3, iclass 5, count 2 2006.176.08:17:12.44#ibcon#about to read 4, iclass 5, count 2 2006.176.08:17:12.44#ibcon#read 4, iclass 5, count 2 2006.176.08:17:12.44#ibcon#about to read 5, iclass 5, count 2 2006.176.08:17:12.44#ibcon#read 5, iclass 5, count 2 2006.176.08:17:12.44#ibcon#about to read 6, iclass 5, count 2 2006.176.08:17:12.44#ibcon#read 6, iclass 5, count 2 2006.176.08:17:12.44#ibcon#end of sib2, iclass 5, count 2 2006.176.08:17:12.44#ibcon#*mode == 0, iclass 5, count 2 2006.176.08:17:12.44#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.176.08:17:12.44#ibcon#[27=AT06-04\r\n] 2006.176.08:17:12.44#ibcon#*before write, iclass 5, count 2 2006.176.08:17:12.44#ibcon#enter sib2, iclass 5, count 2 2006.176.08:17:12.44#ibcon#flushed, iclass 5, count 2 2006.176.08:17:12.44#ibcon#about to write, iclass 5, count 2 2006.176.08:17:12.44#ibcon#wrote, iclass 5, count 2 2006.176.08:17:12.44#ibcon#about to read 3, iclass 5, count 2 2006.176.08:17:12.47#ibcon#read 3, iclass 5, count 2 2006.176.08:17:12.47#ibcon#about to read 4, iclass 5, count 2 2006.176.08:17:12.47#ibcon#read 4, iclass 5, count 2 2006.176.08:17:12.47#ibcon#about to read 5, iclass 5, count 2 2006.176.08:17:12.47#ibcon#read 5, iclass 5, count 2 2006.176.08:17:12.47#ibcon#about to read 6, iclass 5, count 2 2006.176.08:17:12.47#ibcon#read 6, iclass 5, count 2 2006.176.08:17:12.47#ibcon#end of sib2, iclass 5, count 2 2006.176.08:17:12.47#ibcon#*after write, iclass 5, count 2 2006.176.08:17:12.47#ibcon#*before return 0, iclass 5, count 2 2006.176.08:17:12.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:12.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:17:12.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.176.08:17:12.47#ibcon#ireg 7 cls_cnt 0 2006.176.08:17:12.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:12.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:12.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:12.59#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:17:12.59#ibcon#first serial, iclass 5, count 0 2006.176.08:17:12.59#ibcon#enter sib2, iclass 5, count 0 2006.176.08:17:12.59#ibcon#flushed, iclass 5, count 0 2006.176.08:17:12.59#ibcon#about to write, iclass 5, count 0 2006.176.08:17:12.59#ibcon#wrote, iclass 5, count 0 2006.176.08:17:12.59#ibcon#about to read 3, iclass 5, count 0 2006.176.08:17:12.61#ibcon#read 3, iclass 5, count 0 2006.176.08:17:12.61#ibcon#about to read 4, iclass 5, count 0 2006.176.08:17:12.61#ibcon#read 4, iclass 5, count 0 2006.176.08:17:12.61#ibcon#about to read 5, iclass 5, count 0 2006.176.08:17:12.61#ibcon#read 5, iclass 5, count 0 2006.176.08:17:12.61#ibcon#about to read 6, iclass 5, count 0 2006.176.08:17:12.61#ibcon#read 6, iclass 5, count 0 2006.176.08:17:12.61#ibcon#end of sib2, iclass 5, count 0 2006.176.08:17:12.61#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:17:12.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:17:12.61#ibcon#[27=USB\r\n] 2006.176.08:17:12.61#ibcon#*before write, iclass 5, count 0 2006.176.08:17:12.61#ibcon#enter sib2, iclass 5, count 0 2006.176.08:17:12.61#ibcon#flushed, iclass 5, count 0 2006.176.08:17:12.61#ibcon#about to write, iclass 5, count 0 2006.176.08:17:12.61#ibcon#wrote, iclass 5, count 0 2006.176.08:17:12.61#ibcon#about to read 3, iclass 5, count 0 2006.176.08:17:12.64#ibcon#read 3, iclass 5, count 0 2006.176.08:17:12.64#ibcon#about to read 4, iclass 5, count 0 2006.176.08:17:12.64#ibcon#read 4, iclass 5, count 0 2006.176.08:17:12.64#ibcon#about to read 5, iclass 5, count 0 2006.176.08:17:12.64#ibcon#read 5, iclass 5, count 0 2006.176.08:17:12.64#ibcon#about to read 6, iclass 5, count 0 2006.176.08:17:12.64#ibcon#read 6, iclass 5, count 0 2006.176.08:17:12.64#ibcon#end of sib2, iclass 5, count 0 2006.176.08:17:12.64#ibcon#*after write, iclass 5, count 0 2006.176.08:17:12.64#ibcon#*before return 0, iclass 5, count 0 2006.176.08:17:12.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:12.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:17:12.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:17:12.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:17:12.64$vc4f8/vabw=wide 2006.176.08:17:12.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.08:17:12.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.08:17:12.64#ibcon#ireg 8 cls_cnt 0 2006.176.08:17:12.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:12.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:12.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:12.64#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:17:12.64#ibcon#first serial, iclass 7, count 0 2006.176.08:17:12.64#ibcon#enter sib2, iclass 7, count 0 2006.176.08:17:12.64#ibcon#flushed, iclass 7, count 0 2006.176.08:17:12.64#ibcon#about to write, iclass 7, count 0 2006.176.08:17:12.64#ibcon#wrote, iclass 7, count 0 2006.176.08:17:12.64#ibcon#about to read 3, iclass 7, count 0 2006.176.08:17:12.66#ibcon#read 3, iclass 7, count 0 2006.176.08:17:12.66#ibcon#about to read 4, iclass 7, count 0 2006.176.08:17:12.66#ibcon#read 4, iclass 7, count 0 2006.176.08:17:12.66#ibcon#about to read 5, iclass 7, count 0 2006.176.08:17:12.66#ibcon#read 5, iclass 7, count 0 2006.176.08:17:12.66#ibcon#about to read 6, iclass 7, count 0 2006.176.08:17:12.66#ibcon#read 6, iclass 7, count 0 2006.176.08:17:12.66#ibcon#end of sib2, iclass 7, count 0 2006.176.08:17:12.66#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:17:12.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:17:12.66#ibcon#[25=BW32\r\n] 2006.176.08:17:12.66#ibcon#*before write, iclass 7, count 0 2006.176.08:17:12.66#ibcon#enter sib2, iclass 7, count 0 2006.176.08:17:12.66#ibcon#flushed, iclass 7, count 0 2006.176.08:17:12.66#ibcon#about to write, iclass 7, count 0 2006.176.08:17:12.66#ibcon#wrote, iclass 7, count 0 2006.176.08:17:12.66#ibcon#about to read 3, iclass 7, count 0 2006.176.08:17:12.69#ibcon#read 3, iclass 7, count 0 2006.176.08:17:12.69#ibcon#about to read 4, iclass 7, count 0 2006.176.08:17:12.69#ibcon#read 4, iclass 7, count 0 2006.176.08:17:12.69#ibcon#about to read 5, iclass 7, count 0 2006.176.08:17:12.69#ibcon#read 5, iclass 7, count 0 2006.176.08:17:12.69#ibcon#about to read 6, iclass 7, count 0 2006.176.08:17:12.69#ibcon#read 6, iclass 7, count 0 2006.176.08:17:12.69#ibcon#end of sib2, iclass 7, count 0 2006.176.08:17:12.69#ibcon#*after write, iclass 7, count 0 2006.176.08:17:12.69#ibcon#*before return 0, iclass 7, count 0 2006.176.08:17:12.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:12.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:17:12.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:17:12.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:17:12.69$vc4f8/vbbw=wide 2006.176.08:17:12.69#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.08:17:12.69#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.08:17:12.69#ibcon#ireg 8 cls_cnt 0 2006.176.08:17:12.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:17:12.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:17:12.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:17:12.76#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:17:12.76#ibcon#first serial, iclass 11, count 0 2006.176.08:17:12.76#ibcon#enter sib2, iclass 11, count 0 2006.176.08:17:12.76#ibcon#flushed, iclass 11, count 0 2006.176.08:17:12.76#ibcon#about to write, iclass 11, count 0 2006.176.08:17:12.76#ibcon#wrote, iclass 11, count 0 2006.176.08:17:12.76#ibcon#about to read 3, iclass 11, count 0 2006.176.08:17:12.78#ibcon#read 3, iclass 11, count 0 2006.176.08:17:12.78#ibcon#about to read 4, iclass 11, count 0 2006.176.08:17:12.78#ibcon#read 4, iclass 11, count 0 2006.176.08:17:12.78#ibcon#about to read 5, iclass 11, count 0 2006.176.08:17:12.78#ibcon#read 5, iclass 11, count 0 2006.176.08:17:12.78#ibcon#about to read 6, iclass 11, count 0 2006.176.08:17:12.78#ibcon#read 6, iclass 11, count 0 2006.176.08:17:12.78#ibcon#end of sib2, iclass 11, count 0 2006.176.08:17:12.78#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:17:12.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:17:12.78#ibcon#[27=BW32\r\n] 2006.176.08:17:12.78#ibcon#*before write, iclass 11, count 0 2006.176.08:17:12.78#ibcon#enter sib2, iclass 11, count 0 2006.176.08:17:12.78#ibcon#flushed, iclass 11, count 0 2006.176.08:17:12.78#ibcon#about to write, iclass 11, count 0 2006.176.08:17:12.78#ibcon#wrote, iclass 11, count 0 2006.176.08:17:12.78#ibcon#about to read 3, iclass 11, count 0 2006.176.08:17:12.81#ibcon#read 3, iclass 11, count 0 2006.176.08:17:12.81#ibcon#about to read 4, iclass 11, count 0 2006.176.08:17:12.81#ibcon#read 4, iclass 11, count 0 2006.176.08:17:12.81#ibcon#about to read 5, iclass 11, count 0 2006.176.08:17:12.81#ibcon#read 5, iclass 11, count 0 2006.176.08:17:12.81#ibcon#about to read 6, iclass 11, count 0 2006.176.08:17:12.81#ibcon#read 6, iclass 11, count 0 2006.176.08:17:12.81#ibcon#end of sib2, iclass 11, count 0 2006.176.08:17:12.81#ibcon#*after write, iclass 11, count 0 2006.176.08:17:12.81#ibcon#*before return 0, iclass 11, count 0 2006.176.08:17:12.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:17:12.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:17:12.81#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:17:12.81#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:17:12.81$4f8m12a/ifd4f 2006.176.08:17:12.81$ifd4f/lo= 2006.176.08:17:12.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:17:12.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:17:12.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:17:12.81$ifd4f/patch= 2006.176.08:17:12.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:17:12.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:17:12.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:17:12.81$4f8m12a/"form=m,16.000,1:2 2006.176.08:17:12.81$4f8m12a/"tpicd 2006.176.08:17:12.81$4f8m12a/echo=off 2006.176.08:17:12.81$4f8m12a/xlog=off 2006.176.08:17:12.81:!2006.176.08:17:40 2006.176.08:17:22.14#trakl#Source acquired 2006.176.08:17:22.14#flagr#flagr/antenna,acquired 2006.176.08:17:40.00:preob 2006.176.08:17:41.14/onsource/TRACKING 2006.176.08:17:41.14:!2006.176.08:17:50 2006.176.08:17:50.00:data_valid=on 2006.176.08:17:50.00:midob 2006.176.08:17:50.14/onsource/TRACKING 2006.176.08:17:50.14/wx/23.80,1008.6,93 2006.176.08:17:50.36/cable/+6.4924E-03 2006.176.08:17:51.45/va/01,08,usb,yes,29,31 2006.176.08:17:51.45/va/02,07,usb,yes,29,31 2006.176.08:17:51.45/va/03,06,usb,yes,31,31 2006.176.08:17:51.45/va/04,07,usb,yes,30,32 2006.176.08:17:51.45/va/05,07,usb,yes,32,34 2006.176.08:17:51.45/va/06,06,usb,yes,31,31 2006.176.08:17:51.45/va/07,06,usb,yes,31,31 2006.176.08:17:51.45/va/08,06,usb,yes,34,33 2006.176.08:17:51.68/valo/01,532.99,yes,locked 2006.176.08:17:51.68/valo/02,572.99,yes,locked 2006.176.08:17:51.68/valo/03,672.99,yes,locked 2006.176.08:17:51.68/valo/04,832.99,yes,locked 2006.176.08:17:51.68/valo/05,652.99,yes,locked 2006.176.08:17:51.68/valo/06,772.99,yes,locked 2006.176.08:17:51.68/valo/07,832.99,yes,locked 2006.176.08:17:51.68/valo/08,852.99,yes,locked 2006.176.08:17:52.77/vb/01,04,usb,yes,29,28 2006.176.08:17:52.77/vb/02,04,usb,yes,31,32 2006.176.08:17:52.77/vb/03,04,usb,yes,27,31 2006.176.08:17:52.77/vb/04,04,usb,yes,28,28 2006.176.08:17:52.77/vb/05,04,usb,yes,27,31 2006.176.08:17:52.77/vb/06,04,usb,yes,28,31 2006.176.08:17:52.77/vb/07,04,usb,yes,30,30 2006.176.08:17:52.77/vb/08,04,usb,yes,28,31 2006.176.08:17:53.00/vblo/01,632.99,yes,locked 2006.176.08:17:53.00/vblo/02,640.99,yes,locked 2006.176.08:17:53.00/vblo/03,656.99,yes,locked 2006.176.08:17:53.00/vblo/04,712.99,yes,locked 2006.176.08:17:53.00/vblo/05,744.99,yes,locked 2006.176.08:17:53.00/vblo/06,752.99,yes,locked 2006.176.08:17:53.00/vblo/07,734.99,yes,locked 2006.176.08:17:53.00/vblo/08,744.99,yes,locked 2006.176.08:17:53.15/vabw/8 2006.176.08:17:53.30/vbbw/8 2006.176.08:17:53.48/xfe/off,on,14.5 2006.176.08:17:53.86/ifatt/23,28,28,28 2006.176.08:17:54.08/fmout-gps/S +3.69E-07 2006.176.08:17:54.12:!2006.176.08:18:50 2006.176.08:18:50.00:data_valid=off 2006.176.08:18:50.00:postob 2006.176.08:18:50.09/cable/+6.4936E-03 2006.176.08:18:50.09/wx/23.80,1008.6,93 2006.176.08:18:51.07/fmout-gps/S +3.69E-07 2006.176.08:18:51.07:scan_name=176-0820,k06176,70 2006.176.08:18:51.08:source=1053+815,105811.54,811432.7,2000.0,neutral 2006.176.08:18:51.14#flagr#flagr/antenna,new-source 2006.176.08:18:52.14:checkk5 2006.176.08:18:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:18:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:18:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:18:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:18:54.02/chk_obsdata//k5ts1/T1760817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:18:54.39/chk_obsdata//k5ts2/T1760817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:18:54.76/chk_obsdata//k5ts3/T1760817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:18:55.13/chk_obsdata//k5ts4/T1760817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:18:55.81/k5log//k5ts1_log_newline 2006.176.08:18:56.50/k5log//k5ts2_log_newline 2006.176.08:18:57.20/k5log//k5ts3_log_newline 2006.176.08:18:57.90/k5log//k5ts4_log_newline 2006.176.08:18:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:18:57.92:4f8m12a=3 2006.176.08:18:57.92$4f8m12a/echo=on 2006.176.08:18:57.92$4f8m12a/pcalon 2006.176.08:18:57.92$pcalon/"no phase cal control is implemented here 2006.176.08:18:57.92$4f8m12a/"tpicd=stop 2006.176.08:18:57.93$4f8m12a/vc4f8 2006.176.08:18:57.93$vc4f8/valo=1,532.99 2006.176.08:18:57.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.08:18:57.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.08:18:57.93#ibcon#ireg 17 cls_cnt 0 2006.176.08:18:57.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:18:57.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:18:57.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:18:57.93#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:18:57.93#ibcon#first serial, iclass 18, count 0 2006.176.08:18:57.93#ibcon#enter sib2, iclass 18, count 0 2006.176.08:18:57.93#ibcon#flushed, iclass 18, count 0 2006.176.08:18:57.93#ibcon#about to write, iclass 18, count 0 2006.176.08:18:57.93#ibcon#wrote, iclass 18, count 0 2006.176.08:18:57.93#ibcon#about to read 3, iclass 18, count 0 2006.176.08:18:57.97#ibcon#read 3, iclass 18, count 0 2006.176.08:18:57.97#ibcon#about to read 4, iclass 18, count 0 2006.176.08:18:57.97#ibcon#read 4, iclass 18, count 0 2006.176.08:18:57.97#ibcon#about to read 5, iclass 18, count 0 2006.176.08:18:57.97#ibcon#read 5, iclass 18, count 0 2006.176.08:18:57.97#ibcon#about to read 6, iclass 18, count 0 2006.176.08:18:57.97#ibcon#read 6, iclass 18, count 0 2006.176.08:18:57.97#ibcon#end of sib2, iclass 18, count 0 2006.176.08:18:57.97#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:18:57.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:18:57.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:18:57.97#ibcon#*before write, iclass 18, count 0 2006.176.08:18:57.97#ibcon#enter sib2, iclass 18, count 0 2006.176.08:18:57.97#ibcon#flushed, iclass 18, count 0 2006.176.08:18:57.97#ibcon#about to write, iclass 18, count 0 2006.176.08:18:57.97#ibcon#wrote, iclass 18, count 0 2006.176.08:18:57.97#ibcon#about to read 3, iclass 18, count 0 2006.176.08:18:58.02#ibcon#read 3, iclass 18, count 0 2006.176.08:18:58.02#ibcon#about to read 4, iclass 18, count 0 2006.176.08:18:58.02#ibcon#read 4, iclass 18, count 0 2006.176.08:18:58.02#ibcon#about to read 5, iclass 18, count 0 2006.176.08:18:58.02#ibcon#read 5, iclass 18, count 0 2006.176.08:18:58.02#ibcon#about to read 6, iclass 18, count 0 2006.176.08:18:58.02#ibcon#read 6, iclass 18, count 0 2006.176.08:18:58.02#ibcon#end of sib2, iclass 18, count 0 2006.176.08:18:58.02#ibcon#*after write, iclass 18, count 0 2006.176.08:18:58.02#ibcon#*before return 0, iclass 18, count 0 2006.176.08:18:58.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:18:58.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:18:58.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:18:58.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:18:58.02$vc4f8/va=1,8 2006.176.08:18:58.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.08:18:58.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.08:18:58.02#ibcon#ireg 11 cls_cnt 2 2006.176.08:18:58.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:18:58.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:18:58.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:18:58.02#ibcon#enter wrdev, iclass 20, count 2 2006.176.08:18:58.02#ibcon#first serial, iclass 20, count 2 2006.176.08:18:58.02#ibcon#enter sib2, iclass 20, count 2 2006.176.08:18:58.02#ibcon#flushed, iclass 20, count 2 2006.176.08:18:58.02#ibcon#about to write, iclass 20, count 2 2006.176.08:18:58.02#ibcon#wrote, iclass 20, count 2 2006.176.08:18:58.02#ibcon#about to read 3, iclass 20, count 2 2006.176.08:18:58.04#ibcon#read 3, iclass 20, count 2 2006.176.08:18:58.04#ibcon#about to read 4, iclass 20, count 2 2006.176.08:18:58.04#ibcon#read 4, iclass 20, count 2 2006.176.08:18:58.04#ibcon#about to read 5, iclass 20, count 2 2006.176.08:18:58.04#ibcon#read 5, iclass 20, count 2 2006.176.08:18:58.04#ibcon#about to read 6, iclass 20, count 2 2006.176.08:18:58.04#ibcon#read 6, iclass 20, count 2 2006.176.08:18:58.04#ibcon#end of sib2, iclass 20, count 2 2006.176.08:18:58.04#ibcon#*mode == 0, iclass 20, count 2 2006.176.08:18:58.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.08:18:58.04#ibcon#[25=AT01-08\r\n] 2006.176.08:18:58.04#ibcon#*before write, iclass 20, count 2 2006.176.08:18:58.04#ibcon#enter sib2, iclass 20, count 2 2006.176.08:18:58.04#ibcon#flushed, iclass 20, count 2 2006.176.08:18:58.04#ibcon#about to write, iclass 20, count 2 2006.176.08:18:58.04#ibcon#wrote, iclass 20, count 2 2006.176.08:18:58.04#ibcon#about to read 3, iclass 20, count 2 2006.176.08:18:58.07#ibcon#read 3, iclass 20, count 2 2006.176.08:18:58.07#ibcon#about to read 4, iclass 20, count 2 2006.176.08:18:58.07#ibcon#read 4, iclass 20, count 2 2006.176.08:18:58.07#ibcon#about to read 5, iclass 20, count 2 2006.176.08:18:58.07#ibcon#read 5, iclass 20, count 2 2006.176.08:18:58.07#ibcon#about to read 6, iclass 20, count 2 2006.176.08:18:58.07#ibcon#read 6, iclass 20, count 2 2006.176.08:18:58.07#ibcon#end of sib2, iclass 20, count 2 2006.176.08:18:58.07#ibcon#*after write, iclass 20, count 2 2006.176.08:18:58.07#ibcon#*before return 0, iclass 20, count 2 2006.176.08:18:58.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:18:58.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:18:58.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.08:18:58.07#ibcon#ireg 7 cls_cnt 0 2006.176.08:18:58.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:18:58.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:18:58.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:18:58.19#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:18:58.19#ibcon#first serial, iclass 20, count 0 2006.176.08:18:58.19#ibcon#enter sib2, iclass 20, count 0 2006.176.08:18:58.19#ibcon#flushed, iclass 20, count 0 2006.176.08:18:58.19#ibcon#about to write, iclass 20, count 0 2006.176.08:18:58.19#ibcon#wrote, iclass 20, count 0 2006.176.08:18:58.19#ibcon#about to read 3, iclass 20, count 0 2006.176.08:18:58.21#ibcon#read 3, iclass 20, count 0 2006.176.08:18:58.21#ibcon#about to read 4, iclass 20, count 0 2006.176.08:18:58.21#ibcon#read 4, iclass 20, count 0 2006.176.08:18:58.21#ibcon#about to read 5, iclass 20, count 0 2006.176.08:18:58.21#ibcon#read 5, iclass 20, count 0 2006.176.08:18:58.21#ibcon#about to read 6, iclass 20, count 0 2006.176.08:18:58.21#ibcon#read 6, iclass 20, count 0 2006.176.08:18:58.21#ibcon#end of sib2, iclass 20, count 0 2006.176.08:18:58.21#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:18:58.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:18:58.21#ibcon#[25=USB\r\n] 2006.176.08:18:58.21#ibcon#*before write, iclass 20, count 0 2006.176.08:18:58.21#ibcon#enter sib2, iclass 20, count 0 2006.176.08:18:58.21#ibcon#flushed, iclass 20, count 0 2006.176.08:18:58.21#ibcon#about to write, iclass 20, count 0 2006.176.08:18:58.21#ibcon#wrote, iclass 20, count 0 2006.176.08:18:58.21#ibcon#about to read 3, iclass 20, count 0 2006.176.08:18:58.24#ibcon#read 3, iclass 20, count 0 2006.176.08:18:58.24#ibcon#about to read 4, iclass 20, count 0 2006.176.08:18:58.24#ibcon#read 4, iclass 20, count 0 2006.176.08:18:58.24#ibcon#about to read 5, iclass 20, count 0 2006.176.08:18:58.24#ibcon#read 5, iclass 20, count 0 2006.176.08:18:58.24#ibcon#about to read 6, iclass 20, count 0 2006.176.08:18:58.24#ibcon#read 6, iclass 20, count 0 2006.176.08:18:58.24#ibcon#end of sib2, iclass 20, count 0 2006.176.08:18:58.24#ibcon#*after write, iclass 20, count 0 2006.176.08:18:58.24#ibcon#*before return 0, iclass 20, count 0 2006.176.08:18:58.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:18:58.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:18:58.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:18:58.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:18:58.24$vc4f8/valo=2,572.99 2006.176.08:18:58.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.08:18:58.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.08:18:58.24#ibcon#ireg 17 cls_cnt 0 2006.176.08:18:58.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:18:58.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:18:58.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:18:58.24#ibcon#enter wrdev, iclass 22, count 0 2006.176.08:18:58.24#ibcon#first serial, iclass 22, count 0 2006.176.08:18:58.24#ibcon#enter sib2, iclass 22, count 0 2006.176.08:18:58.24#ibcon#flushed, iclass 22, count 0 2006.176.08:18:58.24#ibcon#about to write, iclass 22, count 0 2006.176.08:18:58.24#ibcon#wrote, iclass 22, count 0 2006.176.08:18:58.24#ibcon#about to read 3, iclass 22, count 0 2006.176.08:18:58.26#ibcon#read 3, iclass 22, count 0 2006.176.08:18:58.26#ibcon#about to read 4, iclass 22, count 0 2006.176.08:18:58.26#ibcon#read 4, iclass 22, count 0 2006.176.08:18:58.26#ibcon#about to read 5, iclass 22, count 0 2006.176.08:18:58.26#ibcon#read 5, iclass 22, count 0 2006.176.08:18:58.26#ibcon#about to read 6, iclass 22, count 0 2006.176.08:18:58.26#ibcon#read 6, iclass 22, count 0 2006.176.08:18:58.26#ibcon#end of sib2, iclass 22, count 0 2006.176.08:18:58.26#ibcon#*mode == 0, iclass 22, count 0 2006.176.08:18:58.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.08:18:58.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:18:58.26#ibcon#*before write, iclass 22, count 0 2006.176.08:18:58.26#ibcon#enter sib2, iclass 22, count 0 2006.176.08:18:58.26#ibcon#flushed, iclass 22, count 0 2006.176.08:18:58.26#ibcon#about to write, iclass 22, count 0 2006.176.08:18:58.26#ibcon#wrote, iclass 22, count 0 2006.176.08:18:58.26#ibcon#about to read 3, iclass 22, count 0 2006.176.08:18:58.30#ibcon#read 3, iclass 22, count 0 2006.176.08:18:58.30#ibcon#about to read 4, iclass 22, count 0 2006.176.08:18:58.30#ibcon#read 4, iclass 22, count 0 2006.176.08:18:58.30#ibcon#about to read 5, iclass 22, count 0 2006.176.08:18:58.30#ibcon#read 5, iclass 22, count 0 2006.176.08:18:58.30#ibcon#about to read 6, iclass 22, count 0 2006.176.08:18:58.30#ibcon#read 6, iclass 22, count 0 2006.176.08:18:58.30#ibcon#end of sib2, iclass 22, count 0 2006.176.08:18:58.30#ibcon#*after write, iclass 22, count 0 2006.176.08:18:58.30#ibcon#*before return 0, iclass 22, count 0 2006.176.08:18:58.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:18:58.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:18:58.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.08:18:58.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.08:18:58.30$vc4f8/va=2,7 2006.176.08:18:58.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.08:18:58.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.08:18:58.30#ibcon#ireg 11 cls_cnt 2 2006.176.08:18:58.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:18:58.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:18:58.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:18:58.36#ibcon#enter wrdev, iclass 24, count 2 2006.176.08:18:58.36#ibcon#first serial, iclass 24, count 2 2006.176.08:18:58.36#ibcon#enter sib2, iclass 24, count 2 2006.176.08:18:58.36#ibcon#flushed, iclass 24, count 2 2006.176.08:18:58.36#ibcon#about to write, iclass 24, count 2 2006.176.08:18:58.36#ibcon#wrote, iclass 24, count 2 2006.176.08:18:58.36#ibcon#about to read 3, iclass 24, count 2 2006.176.08:18:58.38#ibcon#read 3, iclass 24, count 2 2006.176.08:18:58.38#ibcon#about to read 4, iclass 24, count 2 2006.176.08:18:58.38#ibcon#read 4, iclass 24, count 2 2006.176.08:18:58.38#ibcon#about to read 5, iclass 24, count 2 2006.176.08:18:58.38#ibcon#read 5, iclass 24, count 2 2006.176.08:18:58.38#ibcon#about to read 6, iclass 24, count 2 2006.176.08:18:58.38#ibcon#read 6, iclass 24, count 2 2006.176.08:18:58.38#ibcon#end of sib2, iclass 24, count 2 2006.176.08:18:58.38#ibcon#*mode == 0, iclass 24, count 2 2006.176.08:18:58.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.08:18:58.38#ibcon#[25=AT02-07\r\n] 2006.176.08:18:58.38#ibcon#*before write, iclass 24, count 2 2006.176.08:18:58.38#ibcon#enter sib2, iclass 24, count 2 2006.176.08:18:58.38#ibcon#flushed, iclass 24, count 2 2006.176.08:18:58.38#ibcon#about to write, iclass 24, count 2 2006.176.08:18:58.38#ibcon#wrote, iclass 24, count 2 2006.176.08:18:58.38#ibcon#about to read 3, iclass 24, count 2 2006.176.08:18:58.41#ibcon#read 3, iclass 24, count 2 2006.176.08:18:58.41#ibcon#about to read 4, iclass 24, count 2 2006.176.08:18:58.41#ibcon#read 4, iclass 24, count 2 2006.176.08:18:58.41#ibcon#about to read 5, iclass 24, count 2 2006.176.08:18:58.41#ibcon#read 5, iclass 24, count 2 2006.176.08:18:58.41#ibcon#about to read 6, iclass 24, count 2 2006.176.08:18:58.41#ibcon#read 6, iclass 24, count 2 2006.176.08:18:58.41#ibcon#end of sib2, iclass 24, count 2 2006.176.08:18:58.41#ibcon#*after write, iclass 24, count 2 2006.176.08:18:58.41#ibcon#*before return 0, iclass 24, count 2 2006.176.08:18:58.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:18:58.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:18:58.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.08:18:58.41#ibcon#ireg 7 cls_cnt 0 2006.176.08:18:58.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:18:58.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:18:58.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:18:58.53#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:18:58.53#ibcon#first serial, iclass 24, count 0 2006.176.08:18:58.53#ibcon#enter sib2, iclass 24, count 0 2006.176.08:18:58.53#ibcon#flushed, iclass 24, count 0 2006.176.08:18:58.53#ibcon#about to write, iclass 24, count 0 2006.176.08:18:58.53#ibcon#wrote, iclass 24, count 0 2006.176.08:18:58.53#ibcon#about to read 3, iclass 24, count 0 2006.176.08:18:58.55#ibcon#read 3, iclass 24, count 0 2006.176.08:18:58.55#ibcon#about to read 4, iclass 24, count 0 2006.176.08:18:58.55#ibcon#read 4, iclass 24, count 0 2006.176.08:18:58.55#ibcon#about to read 5, iclass 24, count 0 2006.176.08:18:58.55#ibcon#read 5, iclass 24, count 0 2006.176.08:18:58.55#ibcon#about to read 6, iclass 24, count 0 2006.176.08:18:58.55#ibcon#read 6, iclass 24, count 0 2006.176.08:18:58.55#ibcon#end of sib2, iclass 24, count 0 2006.176.08:18:58.55#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:18:58.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:18:58.55#ibcon#[25=USB\r\n] 2006.176.08:18:58.55#ibcon#*before write, iclass 24, count 0 2006.176.08:18:58.55#ibcon#enter sib2, iclass 24, count 0 2006.176.08:18:58.55#ibcon#flushed, iclass 24, count 0 2006.176.08:18:58.55#ibcon#about to write, iclass 24, count 0 2006.176.08:18:58.55#ibcon#wrote, iclass 24, count 0 2006.176.08:18:58.55#ibcon#about to read 3, iclass 24, count 0 2006.176.08:18:58.58#ibcon#read 3, iclass 24, count 0 2006.176.08:18:58.58#ibcon#about to read 4, iclass 24, count 0 2006.176.08:18:58.58#ibcon#read 4, iclass 24, count 0 2006.176.08:18:58.58#ibcon#about to read 5, iclass 24, count 0 2006.176.08:18:58.58#ibcon#read 5, iclass 24, count 0 2006.176.08:18:58.58#ibcon#about to read 6, iclass 24, count 0 2006.176.08:18:58.58#ibcon#read 6, iclass 24, count 0 2006.176.08:18:58.58#ibcon#end of sib2, iclass 24, count 0 2006.176.08:18:58.58#ibcon#*after write, iclass 24, count 0 2006.176.08:18:58.58#ibcon#*before return 0, iclass 24, count 0 2006.176.08:18:58.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:18:58.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:18:58.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:18:58.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:18:58.58$vc4f8/valo=3,672.99 2006.176.08:18:58.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.08:18:58.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.08:18:58.58#ibcon#ireg 17 cls_cnt 0 2006.176.08:18:58.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:18:58.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:18:58.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:18:58.58#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:18:58.58#ibcon#first serial, iclass 26, count 0 2006.176.08:18:58.58#ibcon#enter sib2, iclass 26, count 0 2006.176.08:18:58.58#ibcon#flushed, iclass 26, count 0 2006.176.08:18:58.58#ibcon#about to write, iclass 26, count 0 2006.176.08:18:58.58#ibcon#wrote, iclass 26, count 0 2006.176.08:18:58.58#ibcon#about to read 3, iclass 26, count 0 2006.176.08:18:58.60#ibcon#read 3, iclass 26, count 0 2006.176.08:18:58.60#ibcon#about to read 4, iclass 26, count 0 2006.176.08:18:58.60#ibcon#read 4, iclass 26, count 0 2006.176.08:18:58.60#ibcon#about to read 5, iclass 26, count 0 2006.176.08:18:58.60#ibcon#read 5, iclass 26, count 0 2006.176.08:18:58.60#ibcon#about to read 6, iclass 26, count 0 2006.176.08:18:58.60#ibcon#read 6, iclass 26, count 0 2006.176.08:18:58.60#ibcon#end of sib2, iclass 26, count 0 2006.176.08:18:58.60#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:18:58.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:18:58.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:18:58.60#ibcon#*before write, iclass 26, count 0 2006.176.08:18:58.60#ibcon#enter sib2, iclass 26, count 0 2006.176.08:18:58.60#ibcon#flushed, iclass 26, count 0 2006.176.08:18:58.60#ibcon#about to write, iclass 26, count 0 2006.176.08:18:58.60#ibcon#wrote, iclass 26, count 0 2006.176.08:18:58.60#ibcon#about to read 3, iclass 26, count 0 2006.176.08:18:58.64#ibcon#read 3, iclass 26, count 0 2006.176.08:18:58.64#ibcon#about to read 4, iclass 26, count 0 2006.176.08:18:58.64#ibcon#read 4, iclass 26, count 0 2006.176.08:18:58.64#ibcon#about to read 5, iclass 26, count 0 2006.176.08:18:58.64#ibcon#read 5, iclass 26, count 0 2006.176.08:18:58.64#ibcon#about to read 6, iclass 26, count 0 2006.176.08:18:58.64#ibcon#read 6, iclass 26, count 0 2006.176.08:18:58.64#ibcon#end of sib2, iclass 26, count 0 2006.176.08:18:58.64#ibcon#*after write, iclass 26, count 0 2006.176.08:18:58.64#ibcon#*before return 0, iclass 26, count 0 2006.176.08:18:58.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:18:58.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:18:58.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:18:58.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:18:58.64$vc4f8/va=3,6 2006.176.08:18:58.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.08:18:58.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.08:18:58.64#ibcon#ireg 11 cls_cnt 2 2006.176.08:18:58.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:18:58.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:18:58.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:18:58.70#ibcon#enter wrdev, iclass 28, count 2 2006.176.08:18:58.70#ibcon#first serial, iclass 28, count 2 2006.176.08:18:58.70#ibcon#enter sib2, iclass 28, count 2 2006.176.08:18:58.70#ibcon#flushed, iclass 28, count 2 2006.176.08:18:58.70#ibcon#about to write, iclass 28, count 2 2006.176.08:18:58.70#ibcon#wrote, iclass 28, count 2 2006.176.08:18:58.70#ibcon#about to read 3, iclass 28, count 2 2006.176.08:18:58.72#ibcon#read 3, iclass 28, count 2 2006.176.08:18:58.72#ibcon#about to read 4, iclass 28, count 2 2006.176.08:18:58.72#ibcon#read 4, iclass 28, count 2 2006.176.08:18:58.72#ibcon#about to read 5, iclass 28, count 2 2006.176.08:18:58.72#ibcon#read 5, iclass 28, count 2 2006.176.08:18:58.72#ibcon#about to read 6, iclass 28, count 2 2006.176.08:18:58.72#ibcon#read 6, iclass 28, count 2 2006.176.08:18:58.72#ibcon#end of sib2, iclass 28, count 2 2006.176.08:18:58.72#ibcon#*mode == 0, iclass 28, count 2 2006.176.08:18:58.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.08:18:58.72#ibcon#[25=AT03-06\r\n] 2006.176.08:18:58.72#ibcon#*before write, iclass 28, count 2 2006.176.08:18:58.72#ibcon#enter sib2, iclass 28, count 2 2006.176.08:18:58.72#ibcon#flushed, iclass 28, count 2 2006.176.08:18:58.72#ibcon#about to write, iclass 28, count 2 2006.176.08:18:58.72#ibcon#wrote, iclass 28, count 2 2006.176.08:18:58.72#ibcon#about to read 3, iclass 28, count 2 2006.176.08:18:58.75#ibcon#read 3, iclass 28, count 2 2006.176.08:18:58.75#ibcon#about to read 4, iclass 28, count 2 2006.176.08:18:58.75#ibcon#read 4, iclass 28, count 2 2006.176.08:18:58.75#ibcon#about to read 5, iclass 28, count 2 2006.176.08:18:58.75#ibcon#read 5, iclass 28, count 2 2006.176.08:18:58.75#ibcon#about to read 6, iclass 28, count 2 2006.176.08:18:58.75#ibcon#read 6, iclass 28, count 2 2006.176.08:18:58.75#ibcon#end of sib2, iclass 28, count 2 2006.176.08:18:58.75#ibcon#*after write, iclass 28, count 2 2006.176.08:18:58.75#ibcon#*before return 0, iclass 28, count 2 2006.176.08:18:58.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:18:58.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:18:58.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.08:18:58.75#ibcon#ireg 7 cls_cnt 0 2006.176.08:18:58.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:18:58.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:18:58.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:18:58.87#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:18:58.87#ibcon#first serial, iclass 28, count 0 2006.176.08:18:58.87#ibcon#enter sib2, iclass 28, count 0 2006.176.08:18:58.87#ibcon#flushed, iclass 28, count 0 2006.176.08:18:58.87#ibcon#about to write, iclass 28, count 0 2006.176.08:18:58.87#ibcon#wrote, iclass 28, count 0 2006.176.08:18:58.87#ibcon#about to read 3, iclass 28, count 0 2006.176.08:18:58.89#ibcon#read 3, iclass 28, count 0 2006.176.08:18:58.89#ibcon#about to read 4, iclass 28, count 0 2006.176.08:18:58.89#ibcon#read 4, iclass 28, count 0 2006.176.08:18:58.89#ibcon#about to read 5, iclass 28, count 0 2006.176.08:18:58.89#ibcon#read 5, iclass 28, count 0 2006.176.08:18:58.89#ibcon#about to read 6, iclass 28, count 0 2006.176.08:18:58.89#ibcon#read 6, iclass 28, count 0 2006.176.08:18:58.89#ibcon#end of sib2, iclass 28, count 0 2006.176.08:18:58.89#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:18:58.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:18:58.89#ibcon#[25=USB\r\n] 2006.176.08:18:58.89#ibcon#*before write, iclass 28, count 0 2006.176.08:18:58.89#ibcon#enter sib2, iclass 28, count 0 2006.176.08:18:58.89#ibcon#flushed, iclass 28, count 0 2006.176.08:18:58.89#ibcon#about to write, iclass 28, count 0 2006.176.08:18:58.89#ibcon#wrote, iclass 28, count 0 2006.176.08:18:58.89#ibcon#about to read 3, iclass 28, count 0 2006.176.08:18:58.92#ibcon#read 3, iclass 28, count 0 2006.176.08:18:58.92#ibcon#about to read 4, iclass 28, count 0 2006.176.08:18:58.92#ibcon#read 4, iclass 28, count 0 2006.176.08:18:58.92#ibcon#about to read 5, iclass 28, count 0 2006.176.08:18:58.92#ibcon#read 5, iclass 28, count 0 2006.176.08:18:58.92#ibcon#about to read 6, iclass 28, count 0 2006.176.08:18:58.92#ibcon#read 6, iclass 28, count 0 2006.176.08:18:58.92#ibcon#end of sib2, iclass 28, count 0 2006.176.08:18:58.92#ibcon#*after write, iclass 28, count 0 2006.176.08:18:58.92#ibcon#*before return 0, iclass 28, count 0 2006.176.08:18:58.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:18:58.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:18:58.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:18:58.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:18:58.92$vc4f8/valo=4,832.99 2006.176.08:18:58.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.08:18:58.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.08:18:58.92#ibcon#ireg 17 cls_cnt 0 2006.176.08:18:58.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:18:58.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:18:58.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:18:58.92#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:18:58.92#ibcon#first serial, iclass 30, count 0 2006.176.08:18:58.92#ibcon#enter sib2, iclass 30, count 0 2006.176.08:18:58.92#ibcon#flushed, iclass 30, count 0 2006.176.08:18:58.92#ibcon#about to write, iclass 30, count 0 2006.176.08:18:58.92#ibcon#wrote, iclass 30, count 0 2006.176.08:18:58.92#ibcon#about to read 3, iclass 30, count 0 2006.176.08:18:58.94#ibcon#read 3, iclass 30, count 0 2006.176.08:18:58.94#ibcon#about to read 4, iclass 30, count 0 2006.176.08:18:58.94#ibcon#read 4, iclass 30, count 0 2006.176.08:18:58.94#ibcon#about to read 5, iclass 30, count 0 2006.176.08:18:58.94#ibcon#read 5, iclass 30, count 0 2006.176.08:18:58.94#ibcon#about to read 6, iclass 30, count 0 2006.176.08:18:58.94#ibcon#read 6, iclass 30, count 0 2006.176.08:18:58.94#ibcon#end of sib2, iclass 30, count 0 2006.176.08:18:58.94#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:18:58.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:18:58.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:18:58.94#ibcon#*before write, iclass 30, count 0 2006.176.08:18:58.94#ibcon#enter sib2, iclass 30, count 0 2006.176.08:18:58.94#ibcon#flushed, iclass 30, count 0 2006.176.08:18:58.94#ibcon#about to write, iclass 30, count 0 2006.176.08:18:58.94#ibcon#wrote, iclass 30, count 0 2006.176.08:18:58.94#ibcon#about to read 3, iclass 30, count 0 2006.176.08:18:58.98#ibcon#read 3, iclass 30, count 0 2006.176.08:18:58.98#ibcon#about to read 4, iclass 30, count 0 2006.176.08:18:58.98#ibcon#read 4, iclass 30, count 0 2006.176.08:18:58.98#ibcon#about to read 5, iclass 30, count 0 2006.176.08:18:58.98#ibcon#read 5, iclass 30, count 0 2006.176.08:18:58.98#ibcon#about to read 6, iclass 30, count 0 2006.176.08:18:58.98#ibcon#read 6, iclass 30, count 0 2006.176.08:18:58.98#ibcon#end of sib2, iclass 30, count 0 2006.176.08:18:58.98#ibcon#*after write, iclass 30, count 0 2006.176.08:18:58.98#ibcon#*before return 0, iclass 30, count 0 2006.176.08:18:58.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:18:58.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:18:58.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:18:58.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:18:58.98$vc4f8/va=4,7 2006.176.08:18:58.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.176.08:18:58.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.176.08:18:58.98#ibcon#ireg 11 cls_cnt 2 2006.176.08:18:58.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:18:59.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:18:59.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:18:59.04#ibcon#enter wrdev, iclass 32, count 2 2006.176.08:18:59.04#ibcon#first serial, iclass 32, count 2 2006.176.08:18:59.04#ibcon#enter sib2, iclass 32, count 2 2006.176.08:18:59.04#ibcon#flushed, iclass 32, count 2 2006.176.08:18:59.04#ibcon#about to write, iclass 32, count 2 2006.176.08:18:59.04#ibcon#wrote, iclass 32, count 2 2006.176.08:18:59.04#ibcon#about to read 3, iclass 32, count 2 2006.176.08:18:59.06#ibcon#read 3, iclass 32, count 2 2006.176.08:18:59.06#ibcon#about to read 4, iclass 32, count 2 2006.176.08:18:59.06#ibcon#read 4, iclass 32, count 2 2006.176.08:18:59.06#ibcon#about to read 5, iclass 32, count 2 2006.176.08:18:59.06#ibcon#read 5, iclass 32, count 2 2006.176.08:18:59.06#ibcon#about to read 6, iclass 32, count 2 2006.176.08:18:59.06#ibcon#read 6, iclass 32, count 2 2006.176.08:18:59.06#ibcon#end of sib2, iclass 32, count 2 2006.176.08:18:59.06#ibcon#*mode == 0, iclass 32, count 2 2006.176.08:18:59.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.176.08:18:59.06#ibcon#[25=AT04-07\r\n] 2006.176.08:18:59.06#ibcon#*before write, iclass 32, count 2 2006.176.08:18:59.06#ibcon#enter sib2, iclass 32, count 2 2006.176.08:18:59.06#ibcon#flushed, iclass 32, count 2 2006.176.08:18:59.06#ibcon#about to write, iclass 32, count 2 2006.176.08:18:59.06#ibcon#wrote, iclass 32, count 2 2006.176.08:18:59.06#ibcon#about to read 3, iclass 32, count 2 2006.176.08:18:59.09#ibcon#read 3, iclass 32, count 2 2006.176.08:18:59.09#ibcon#about to read 4, iclass 32, count 2 2006.176.08:18:59.09#ibcon#read 4, iclass 32, count 2 2006.176.08:18:59.09#ibcon#about to read 5, iclass 32, count 2 2006.176.08:18:59.09#ibcon#read 5, iclass 32, count 2 2006.176.08:18:59.09#ibcon#about to read 6, iclass 32, count 2 2006.176.08:18:59.09#ibcon#read 6, iclass 32, count 2 2006.176.08:18:59.09#ibcon#end of sib2, iclass 32, count 2 2006.176.08:18:59.09#ibcon#*after write, iclass 32, count 2 2006.176.08:18:59.09#ibcon#*before return 0, iclass 32, count 2 2006.176.08:18:59.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:18:59.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:18:59.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.176.08:18:59.09#ibcon#ireg 7 cls_cnt 0 2006.176.08:18:59.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:18:59.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:18:59.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:18:59.21#ibcon#enter wrdev, iclass 32, count 0 2006.176.08:18:59.21#ibcon#first serial, iclass 32, count 0 2006.176.08:18:59.21#ibcon#enter sib2, iclass 32, count 0 2006.176.08:18:59.21#ibcon#flushed, iclass 32, count 0 2006.176.08:18:59.21#ibcon#about to write, iclass 32, count 0 2006.176.08:18:59.21#ibcon#wrote, iclass 32, count 0 2006.176.08:18:59.21#ibcon#about to read 3, iclass 32, count 0 2006.176.08:18:59.23#ibcon#read 3, iclass 32, count 0 2006.176.08:18:59.23#ibcon#about to read 4, iclass 32, count 0 2006.176.08:18:59.23#ibcon#read 4, iclass 32, count 0 2006.176.08:18:59.23#ibcon#about to read 5, iclass 32, count 0 2006.176.08:18:59.23#ibcon#read 5, iclass 32, count 0 2006.176.08:18:59.23#ibcon#about to read 6, iclass 32, count 0 2006.176.08:18:59.23#ibcon#read 6, iclass 32, count 0 2006.176.08:18:59.23#ibcon#end of sib2, iclass 32, count 0 2006.176.08:18:59.23#ibcon#*mode == 0, iclass 32, count 0 2006.176.08:18:59.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.08:18:59.23#ibcon#[25=USB\r\n] 2006.176.08:18:59.23#ibcon#*before write, iclass 32, count 0 2006.176.08:18:59.23#ibcon#enter sib2, iclass 32, count 0 2006.176.08:18:59.23#ibcon#flushed, iclass 32, count 0 2006.176.08:18:59.23#ibcon#about to write, iclass 32, count 0 2006.176.08:18:59.23#ibcon#wrote, iclass 32, count 0 2006.176.08:18:59.23#ibcon#about to read 3, iclass 32, count 0 2006.176.08:18:59.26#ibcon#read 3, iclass 32, count 0 2006.176.08:18:59.26#ibcon#about to read 4, iclass 32, count 0 2006.176.08:18:59.26#ibcon#read 4, iclass 32, count 0 2006.176.08:18:59.26#ibcon#about to read 5, iclass 32, count 0 2006.176.08:18:59.26#ibcon#read 5, iclass 32, count 0 2006.176.08:18:59.26#ibcon#about to read 6, iclass 32, count 0 2006.176.08:18:59.26#ibcon#read 6, iclass 32, count 0 2006.176.08:18:59.26#ibcon#end of sib2, iclass 32, count 0 2006.176.08:18:59.26#ibcon#*after write, iclass 32, count 0 2006.176.08:18:59.26#ibcon#*before return 0, iclass 32, count 0 2006.176.08:18:59.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:18:59.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:18:59.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.08:18:59.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.08:18:59.26$vc4f8/valo=5,652.99 2006.176.08:18:59.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.08:18:59.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.08:18:59.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:18:59.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:18:59.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:18:59.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:18:59.26#ibcon#enter wrdev, iclass 34, count 0 2006.176.08:18:59.26#ibcon#first serial, iclass 34, count 0 2006.176.08:18:59.26#ibcon#enter sib2, iclass 34, count 0 2006.176.08:18:59.26#ibcon#flushed, iclass 34, count 0 2006.176.08:18:59.26#ibcon#about to write, iclass 34, count 0 2006.176.08:18:59.26#ibcon#wrote, iclass 34, count 0 2006.176.08:18:59.26#ibcon#about to read 3, iclass 34, count 0 2006.176.08:18:59.28#ibcon#read 3, iclass 34, count 0 2006.176.08:18:59.28#ibcon#about to read 4, iclass 34, count 0 2006.176.08:18:59.28#ibcon#read 4, iclass 34, count 0 2006.176.08:18:59.28#ibcon#about to read 5, iclass 34, count 0 2006.176.08:18:59.28#ibcon#read 5, iclass 34, count 0 2006.176.08:18:59.28#ibcon#about to read 6, iclass 34, count 0 2006.176.08:18:59.28#ibcon#read 6, iclass 34, count 0 2006.176.08:18:59.28#ibcon#end of sib2, iclass 34, count 0 2006.176.08:18:59.28#ibcon#*mode == 0, iclass 34, count 0 2006.176.08:18:59.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.08:18:59.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:18:59.28#ibcon#*before write, iclass 34, count 0 2006.176.08:18:59.28#ibcon#enter sib2, iclass 34, count 0 2006.176.08:18:59.28#ibcon#flushed, iclass 34, count 0 2006.176.08:18:59.28#ibcon#about to write, iclass 34, count 0 2006.176.08:18:59.28#ibcon#wrote, iclass 34, count 0 2006.176.08:18:59.28#ibcon#about to read 3, iclass 34, count 0 2006.176.08:18:59.32#ibcon#read 3, iclass 34, count 0 2006.176.08:18:59.32#ibcon#about to read 4, iclass 34, count 0 2006.176.08:18:59.32#ibcon#read 4, iclass 34, count 0 2006.176.08:18:59.32#ibcon#about to read 5, iclass 34, count 0 2006.176.08:18:59.32#ibcon#read 5, iclass 34, count 0 2006.176.08:18:59.32#ibcon#about to read 6, iclass 34, count 0 2006.176.08:18:59.32#ibcon#read 6, iclass 34, count 0 2006.176.08:18:59.32#ibcon#end of sib2, iclass 34, count 0 2006.176.08:18:59.32#ibcon#*after write, iclass 34, count 0 2006.176.08:18:59.32#ibcon#*before return 0, iclass 34, count 0 2006.176.08:18:59.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:18:59.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:18:59.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.08:18:59.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.08:18:59.32$vc4f8/va=5,7 2006.176.08:18:59.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.176.08:18:59.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.176.08:18:59.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:18:59.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:18:59.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:18:59.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:18:59.38#ibcon#enter wrdev, iclass 36, count 2 2006.176.08:18:59.38#ibcon#first serial, iclass 36, count 2 2006.176.08:18:59.38#ibcon#enter sib2, iclass 36, count 2 2006.176.08:18:59.38#ibcon#flushed, iclass 36, count 2 2006.176.08:18:59.38#ibcon#about to write, iclass 36, count 2 2006.176.08:18:59.38#ibcon#wrote, iclass 36, count 2 2006.176.08:18:59.38#ibcon#about to read 3, iclass 36, count 2 2006.176.08:18:59.40#ibcon#read 3, iclass 36, count 2 2006.176.08:18:59.40#ibcon#about to read 4, iclass 36, count 2 2006.176.08:18:59.40#ibcon#read 4, iclass 36, count 2 2006.176.08:18:59.40#ibcon#about to read 5, iclass 36, count 2 2006.176.08:18:59.40#ibcon#read 5, iclass 36, count 2 2006.176.08:18:59.40#ibcon#about to read 6, iclass 36, count 2 2006.176.08:18:59.40#ibcon#read 6, iclass 36, count 2 2006.176.08:18:59.40#ibcon#end of sib2, iclass 36, count 2 2006.176.08:18:59.40#ibcon#*mode == 0, iclass 36, count 2 2006.176.08:18:59.40#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.176.08:18:59.40#ibcon#[25=AT05-07\r\n] 2006.176.08:18:59.40#ibcon#*before write, iclass 36, count 2 2006.176.08:18:59.40#ibcon#enter sib2, iclass 36, count 2 2006.176.08:18:59.40#ibcon#flushed, iclass 36, count 2 2006.176.08:18:59.40#ibcon#about to write, iclass 36, count 2 2006.176.08:18:59.40#ibcon#wrote, iclass 36, count 2 2006.176.08:18:59.40#ibcon#about to read 3, iclass 36, count 2 2006.176.08:18:59.43#ibcon#read 3, iclass 36, count 2 2006.176.08:18:59.43#ibcon#about to read 4, iclass 36, count 2 2006.176.08:18:59.43#ibcon#read 4, iclass 36, count 2 2006.176.08:18:59.43#ibcon#about to read 5, iclass 36, count 2 2006.176.08:18:59.43#ibcon#read 5, iclass 36, count 2 2006.176.08:18:59.43#ibcon#about to read 6, iclass 36, count 2 2006.176.08:18:59.43#ibcon#read 6, iclass 36, count 2 2006.176.08:18:59.43#ibcon#end of sib2, iclass 36, count 2 2006.176.08:18:59.43#ibcon#*after write, iclass 36, count 2 2006.176.08:18:59.43#ibcon#*before return 0, iclass 36, count 2 2006.176.08:18:59.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:18:59.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.176.08:18:59.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.176.08:18:59.43#ibcon#ireg 7 cls_cnt 0 2006.176.08:18:59.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:18:59.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:18:59.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:18:59.55#ibcon#enter wrdev, iclass 36, count 0 2006.176.08:18:59.55#ibcon#first serial, iclass 36, count 0 2006.176.08:18:59.55#ibcon#enter sib2, iclass 36, count 0 2006.176.08:18:59.55#ibcon#flushed, iclass 36, count 0 2006.176.08:18:59.55#ibcon#about to write, iclass 36, count 0 2006.176.08:18:59.55#ibcon#wrote, iclass 36, count 0 2006.176.08:18:59.55#ibcon#about to read 3, iclass 36, count 0 2006.176.08:18:59.57#ibcon#read 3, iclass 36, count 0 2006.176.08:18:59.57#ibcon#about to read 4, iclass 36, count 0 2006.176.08:18:59.57#ibcon#read 4, iclass 36, count 0 2006.176.08:18:59.57#ibcon#about to read 5, iclass 36, count 0 2006.176.08:18:59.57#ibcon#read 5, iclass 36, count 0 2006.176.08:18:59.57#ibcon#about to read 6, iclass 36, count 0 2006.176.08:18:59.57#ibcon#read 6, iclass 36, count 0 2006.176.08:18:59.57#ibcon#end of sib2, iclass 36, count 0 2006.176.08:18:59.57#ibcon#*mode == 0, iclass 36, count 0 2006.176.08:18:59.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.08:18:59.57#ibcon#[25=USB\r\n] 2006.176.08:18:59.57#ibcon#*before write, iclass 36, count 0 2006.176.08:18:59.57#ibcon#enter sib2, iclass 36, count 0 2006.176.08:18:59.57#ibcon#flushed, iclass 36, count 0 2006.176.08:18:59.57#ibcon#about to write, iclass 36, count 0 2006.176.08:18:59.57#ibcon#wrote, iclass 36, count 0 2006.176.08:18:59.57#ibcon#about to read 3, iclass 36, count 0 2006.176.08:18:59.60#ibcon#read 3, iclass 36, count 0 2006.176.08:18:59.60#ibcon#about to read 4, iclass 36, count 0 2006.176.08:18:59.60#ibcon#read 4, iclass 36, count 0 2006.176.08:18:59.60#ibcon#about to read 5, iclass 36, count 0 2006.176.08:18:59.60#ibcon#read 5, iclass 36, count 0 2006.176.08:18:59.60#ibcon#about to read 6, iclass 36, count 0 2006.176.08:18:59.60#ibcon#read 6, iclass 36, count 0 2006.176.08:18:59.60#ibcon#end of sib2, iclass 36, count 0 2006.176.08:18:59.60#ibcon#*after write, iclass 36, count 0 2006.176.08:18:59.60#ibcon#*before return 0, iclass 36, count 0 2006.176.08:18:59.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:18:59.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.176.08:18:59.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.08:18:59.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.08:18:59.60$vc4f8/valo=6,772.99 2006.176.08:18:59.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.08:18:59.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.08:18:59.60#ibcon#ireg 17 cls_cnt 0 2006.176.08:18:59.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:18:59.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:18:59.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:18:59.60#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:18:59.60#ibcon#first serial, iclass 38, count 0 2006.176.08:18:59.60#ibcon#enter sib2, iclass 38, count 0 2006.176.08:18:59.60#ibcon#flushed, iclass 38, count 0 2006.176.08:18:59.60#ibcon#about to write, iclass 38, count 0 2006.176.08:18:59.60#ibcon#wrote, iclass 38, count 0 2006.176.08:18:59.60#ibcon#about to read 3, iclass 38, count 0 2006.176.08:18:59.62#ibcon#read 3, iclass 38, count 0 2006.176.08:18:59.62#ibcon#about to read 4, iclass 38, count 0 2006.176.08:18:59.62#ibcon#read 4, iclass 38, count 0 2006.176.08:18:59.62#ibcon#about to read 5, iclass 38, count 0 2006.176.08:18:59.62#ibcon#read 5, iclass 38, count 0 2006.176.08:18:59.62#ibcon#about to read 6, iclass 38, count 0 2006.176.08:18:59.62#ibcon#read 6, iclass 38, count 0 2006.176.08:18:59.62#ibcon#end of sib2, iclass 38, count 0 2006.176.08:18:59.62#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:18:59.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:18:59.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:18:59.62#ibcon#*before write, iclass 38, count 0 2006.176.08:18:59.62#ibcon#enter sib2, iclass 38, count 0 2006.176.08:18:59.62#ibcon#flushed, iclass 38, count 0 2006.176.08:18:59.62#ibcon#about to write, iclass 38, count 0 2006.176.08:18:59.62#ibcon#wrote, iclass 38, count 0 2006.176.08:18:59.62#ibcon#about to read 3, iclass 38, count 0 2006.176.08:18:59.66#ibcon#read 3, iclass 38, count 0 2006.176.08:18:59.66#ibcon#about to read 4, iclass 38, count 0 2006.176.08:18:59.66#ibcon#read 4, iclass 38, count 0 2006.176.08:18:59.66#ibcon#about to read 5, iclass 38, count 0 2006.176.08:18:59.66#ibcon#read 5, iclass 38, count 0 2006.176.08:18:59.66#ibcon#about to read 6, iclass 38, count 0 2006.176.08:18:59.66#ibcon#read 6, iclass 38, count 0 2006.176.08:18:59.66#ibcon#end of sib2, iclass 38, count 0 2006.176.08:18:59.66#ibcon#*after write, iclass 38, count 0 2006.176.08:18:59.66#ibcon#*before return 0, iclass 38, count 0 2006.176.08:18:59.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:18:59.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:18:59.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:18:59.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:18:59.66$vc4f8/va=6,6 2006.176.08:18:59.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.08:18:59.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.08:18:59.66#ibcon#ireg 11 cls_cnt 2 2006.176.08:18:59.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:18:59.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:18:59.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:18:59.72#ibcon#enter wrdev, iclass 40, count 2 2006.176.08:18:59.72#ibcon#first serial, iclass 40, count 2 2006.176.08:18:59.72#ibcon#enter sib2, iclass 40, count 2 2006.176.08:18:59.72#ibcon#flushed, iclass 40, count 2 2006.176.08:18:59.72#ibcon#about to write, iclass 40, count 2 2006.176.08:18:59.72#ibcon#wrote, iclass 40, count 2 2006.176.08:18:59.72#ibcon#about to read 3, iclass 40, count 2 2006.176.08:18:59.74#ibcon#read 3, iclass 40, count 2 2006.176.08:18:59.74#ibcon#about to read 4, iclass 40, count 2 2006.176.08:18:59.74#ibcon#read 4, iclass 40, count 2 2006.176.08:18:59.74#ibcon#about to read 5, iclass 40, count 2 2006.176.08:18:59.74#ibcon#read 5, iclass 40, count 2 2006.176.08:18:59.74#ibcon#about to read 6, iclass 40, count 2 2006.176.08:18:59.74#ibcon#read 6, iclass 40, count 2 2006.176.08:18:59.74#ibcon#end of sib2, iclass 40, count 2 2006.176.08:18:59.74#ibcon#*mode == 0, iclass 40, count 2 2006.176.08:18:59.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.08:18:59.74#ibcon#[25=AT06-06\r\n] 2006.176.08:18:59.74#ibcon#*before write, iclass 40, count 2 2006.176.08:18:59.74#ibcon#enter sib2, iclass 40, count 2 2006.176.08:18:59.74#ibcon#flushed, iclass 40, count 2 2006.176.08:18:59.74#ibcon#about to write, iclass 40, count 2 2006.176.08:18:59.74#ibcon#wrote, iclass 40, count 2 2006.176.08:18:59.74#ibcon#about to read 3, iclass 40, count 2 2006.176.08:18:59.77#ibcon#read 3, iclass 40, count 2 2006.176.08:18:59.77#ibcon#about to read 4, iclass 40, count 2 2006.176.08:18:59.77#ibcon#read 4, iclass 40, count 2 2006.176.08:18:59.77#ibcon#about to read 5, iclass 40, count 2 2006.176.08:18:59.77#ibcon#read 5, iclass 40, count 2 2006.176.08:18:59.77#ibcon#about to read 6, iclass 40, count 2 2006.176.08:18:59.77#ibcon#read 6, iclass 40, count 2 2006.176.08:18:59.77#ibcon#end of sib2, iclass 40, count 2 2006.176.08:18:59.77#ibcon#*after write, iclass 40, count 2 2006.176.08:18:59.77#ibcon#*before return 0, iclass 40, count 2 2006.176.08:18:59.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:18:59.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:18:59.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.08:18:59.77#ibcon#ireg 7 cls_cnt 0 2006.176.08:18:59.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:18:59.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:18:59.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:18:59.89#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:18:59.89#ibcon#first serial, iclass 40, count 0 2006.176.08:18:59.89#ibcon#enter sib2, iclass 40, count 0 2006.176.08:18:59.89#ibcon#flushed, iclass 40, count 0 2006.176.08:18:59.89#ibcon#about to write, iclass 40, count 0 2006.176.08:18:59.89#ibcon#wrote, iclass 40, count 0 2006.176.08:18:59.89#ibcon#about to read 3, iclass 40, count 0 2006.176.08:18:59.91#ibcon#read 3, iclass 40, count 0 2006.176.08:18:59.91#ibcon#about to read 4, iclass 40, count 0 2006.176.08:18:59.91#ibcon#read 4, iclass 40, count 0 2006.176.08:18:59.91#ibcon#about to read 5, iclass 40, count 0 2006.176.08:18:59.91#ibcon#read 5, iclass 40, count 0 2006.176.08:18:59.91#ibcon#about to read 6, iclass 40, count 0 2006.176.08:18:59.91#ibcon#read 6, iclass 40, count 0 2006.176.08:18:59.91#ibcon#end of sib2, iclass 40, count 0 2006.176.08:18:59.91#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:18:59.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:18:59.91#ibcon#[25=USB\r\n] 2006.176.08:18:59.91#ibcon#*before write, iclass 40, count 0 2006.176.08:18:59.91#ibcon#enter sib2, iclass 40, count 0 2006.176.08:18:59.91#ibcon#flushed, iclass 40, count 0 2006.176.08:18:59.91#ibcon#about to write, iclass 40, count 0 2006.176.08:18:59.91#ibcon#wrote, iclass 40, count 0 2006.176.08:18:59.91#ibcon#about to read 3, iclass 40, count 0 2006.176.08:18:59.94#ibcon#read 3, iclass 40, count 0 2006.176.08:18:59.94#ibcon#about to read 4, iclass 40, count 0 2006.176.08:18:59.94#ibcon#read 4, iclass 40, count 0 2006.176.08:18:59.94#ibcon#about to read 5, iclass 40, count 0 2006.176.08:18:59.94#ibcon#read 5, iclass 40, count 0 2006.176.08:18:59.94#ibcon#about to read 6, iclass 40, count 0 2006.176.08:18:59.94#ibcon#read 6, iclass 40, count 0 2006.176.08:18:59.94#ibcon#end of sib2, iclass 40, count 0 2006.176.08:18:59.94#ibcon#*after write, iclass 40, count 0 2006.176.08:18:59.94#ibcon#*before return 0, iclass 40, count 0 2006.176.08:18:59.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:18:59.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:18:59.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:18:59.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:18:59.94$vc4f8/valo=7,832.99 2006.176.08:18:59.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.08:18:59.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.08:18:59.94#ibcon#ireg 17 cls_cnt 0 2006.176.08:18:59.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:18:59.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:18:59.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:18:59.94#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:18:59.94#ibcon#first serial, iclass 4, count 0 2006.176.08:18:59.94#ibcon#enter sib2, iclass 4, count 0 2006.176.08:18:59.94#ibcon#flushed, iclass 4, count 0 2006.176.08:18:59.94#ibcon#about to write, iclass 4, count 0 2006.176.08:18:59.94#ibcon#wrote, iclass 4, count 0 2006.176.08:18:59.94#ibcon#about to read 3, iclass 4, count 0 2006.176.08:18:59.96#ibcon#read 3, iclass 4, count 0 2006.176.08:18:59.96#ibcon#about to read 4, iclass 4, count 0 2006.176.08:18:59.96#ibcon#read 4, iclass 4, count 0 2006.176.08:18:59.96#ibcon#about to read 5, iclass 4, count 0 2006.176.08:18:59.96#ibcon#read 5, iclass 4, count 0 2006.176.08:18:59.96#ibcon#about to read 6, iclass 4, count 0 2006.176.08:18:59.96#ibcon#read 6, iclass 4, count 0 2006.176.08:18:59.96#ibcon#end of sib2, iclass 4, count 0 2006.176.08:18:59.96#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:18:59.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:18:59.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:18:59.96#ibcon#*before write, iclass 4, count 0 2006.176.08:18:59.96#ibcon#enter sib2, iclass 4, count 0 2006.176.08:18:59.96#ibcon#flushed, iclass 4, count 0 2006.176.08:18:59.96#ibcon#about to write, iclass 4, count 0 2006.176.08:18:59.96#ibcon#wrote, iclass 4, count 0 2006.176.08:18:59.96#ibcon#about to read 3, iclass 4, count 0 2006.176.08:19:00.00#ibcon#read 3, iclass 4, count 0 2006.176.08:19:00.00#ibcon#about to read 4, iclass 4, count 0 2006.176.08:19:00.00#ibcon#read 4, iclass 4, count 0 2006.176.08:19:00.00#ibcon#about to read 5, iclass 4, count 0 2006.176.08:19:00.00#ibcon#read 5, iclass 4, count 0 2006.176.08:19:00.00#ibcon#about to read 6, iclass 4, count 0 2006.176.08:19:00.00#ibcon#read 6, iclass 4, count 0 2006.176.08:19:00.00#ibcon#end of sib2, iclass 4, count 0 2006.176.08:19:00.00#ibcon#*after write, iclass 4, count 0 2006.176.08:19:00.00#ibcon#*before return 0, iclass 4, count 0 2006.176.08:19:00.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:19:00.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:19:00.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:19:00.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:19:00.00$vc4f8/va=7,6 2006.176.08:19:00.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.176.08:19:00.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.176.08:19:00.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:19:00.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:19:00.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:19:00.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:19:00.06#ibcon#enter wrdev, iclass 6, count 2 2006.176.08:19:00.06#ibcon#first serial, iclass 6, count 2 2006.176.08:19:00.06#ibcon#enter sib2, iclass 6, count 2 2006.176.08:19:00.06#ibcon#flushed, iclass 6, count 2 2006.176.08:19:00.06#ibcon#about to write, iclass 6, count 2 2006.176.08:19:00.06#ibcon#wrote, iclass 6, count 2 2006.176.08:19:00.06#ibcon#about to read 3, iclass 6, count 2 2006.176.08:19:00.08#ibcon#read 3, iclass 6, count 2 2006.176.08:19:00.08#ibcon#about to read 4, iclass 6, count 2 2006.176.08:19:00.08#ibcon#read 4, iclass 6, count 2 2006.176.08:19:00.08#ibcon#about to read 5, iclass 6, count 2 2006.176.08:19:00.08#ibcon#read 5, iclass 6, count 2 2006.176.08:19:00.08#ibcon#about to read 6, iclass 6, count 2 2006.176.08:19:00.08#ibcon#read 6, iclass 6, count 2 2006.176.08:19:00.08#ibcon#end of sib2, iclass 6, count 2 2006.176.08:19:00.08#ibcon#*mode == 0, iclass 6, count 2 2006.176.08:19:00.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.176.08:19:00.08#ibcon#[25=AT07-06\r\n] 2006.176.08:19:00.08#ibcon#*before write, iclass 6, count 2 2006.176.08:19:00.08#ibcon#enter sib2, iclass 6, count 2 2006.176.08:19:00.08#ibcon#flushed, iclass 6, count 2 2006.176.08:19:00.08#ibcon#about to write, iclass 6, count 2 2006.176.08:19:00.08#ibcon#wrote, iclass 6, count 2 2006.176.08:19:00.08#ibcon#about to read 3, iclass 6, count 2 2006.176.08:19:00.11#ibcon#read 3, iclass 6, count 2 2006.176.08:19:00.11#ibcon#about to read 4, iclass 6, count 2 2006.176.08:19:00.11#ibcon#read 4, iclass 6, count 2 2006.176.08:19:00.11#ibcon#about to read 5, iclass 6, count 2 2006.176.08:19:00.11#ibcon#read 5, iclass 6, count 2 2006.176.08:19:00.11#ibcon#about to read 6, iclass 6, count 2 2006.176.08:19:00.11#ibcon#read 6, iclass 6, count 2 2006.176.08:19:00.11#ibcon#end of sib2, iclass 6, count 2 2006.176.08:19:00.11#ibcon#*after write, iclass 6, count 2 2006.176.08:19:00.11#ibcon#*before return 0, iclass 6, count 2 2006.176.08:19:00.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:19:00.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.176.08:19:00.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.176.08:19:00.11#ibcon#ireg 7 cls_cnt 0 2006.176.08:19:00.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:19:00.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:19:00.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:19:00.23#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:19:00.23#ibcon#first serial, iclass 6, count 0 2006.176.08:19:00.23#ibcon#enter sib2, iclass 6, count 0 2006.176.08:19:00.23#ibcon#flushed, iclass 6, count 0 2006.176.08:19:00.23#ibcon#about to write, iclass 6, count 0 2006.176.08:19:00.23#ibcon#wrote, iclass 6, count 0 2006.176.08:19:00.23#ibcon#about to read 3, iclass 6, count 0 2006.176.08:19:00.25#ibcon#read 3, iclass 6, count 0 2006.176.08:19:00.25#ibcon#about to read 4, iclass 6, count 0 2006.176.08:19:00.25#ibcon#read 4, iclass 6, count 0 2006.176.08:19:00.25#ibcon#about to read 5, iclass 6, count 0 2006.176.08:19:00.25#ibcon#read 5, iclass 6, count 0 2006.176.08:19:00.25#ibcon#about to read 6, iclass 6, count 0 2006.176.08:19:00.25#ibcon#read 6, iclass 6, count 0 2006.176.08:19:00.25#ibcon#end of sib2, iclass 6, count 0 2006.176.08:19:00.25#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:19:00.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:19:00.25#ibcon#[25=USB\r\n] 2006.176.08:19:00.25#ibcon#*before write, iclass 6, count 0 2006.176.08:19:00.25#ibcon#enter sib2, iclass 6, count 0 2006.176.08:19:00.25#ibcon#flushed, iclass 6, count 0 2006.176.08:19:00.25#ibcon#about to write, iclass 6, count 0 2006.176.08:19:00.25#ibcon#wrote, iclass 6, count 0 2006.176.08:19:00.25#ibcon#about to read 3, iclass 6, count 0 2006.176.08:19:00.28#ibcon#read 3, iclass 6, count 0 2006.176.08:19:00.28#ibcon#about to read 4, iclass 6, count 0 2006.176.08:19:00.28#ibcon#read 4, iclass 6, count 0 2006.176.08:19:00.28#ibcon#about to read 5, iclass 6, count 0 2006.176.08:19:00.28#ibcon#read 5, iclass 6, count 0 2006.176.08:19:00.28#ibcon#about to read 6, iclass 6, count 0 2006.176.08:19:00.28#ibcon#read 6, iclass 6, count 0 2006.176.08:19:00.28#ibcon#end of sib2, iclass 6, count 0 2006.176.08:19:00.28#ibcon#*after write, iclass 6, count 0 2006.176.08:19:00.28#ibcon#*before return 0, iclass 6, count 0 2006.176.08:19:00.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:19:00.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.176.08:19:00.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:19:00.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:19:00.28$vc4f8/valo=8,852.99 2006.176.08:19:00.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.176.08:19:00.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.176.08:19:00.28#ibcon#ireg 17 cls_cnt 0 2006.176.08:19:00.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:19:00.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:19:00.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:19:00.28#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:19:00.28#ibcon#first serial, iclass 10, count 0 2006.176.08:19:00.28#ibcon#enter sib2, iclass 10, count 0 2006.176.08:19:00.28#ibcon#flushed, iclass 10, count 0 2006.176.08:19:00.28#ibcon#about to write, iclass 10, count 0 2006.176.08:19:00.28#ibcon#wrote, iclass 10, count 0 2006.176.08:19:00.28#ibcon#about to read 3, iclass 10, count 0 2006.176.08:19:00.30#ibcon#read 3, iclass 10, count 0 2006.176.08:19:00.30#ibcon#about to read 4, iclass 10, count 0 2006.176.08:19:00.30#ibcon#read 4, iclass 10, count 0 2006.176.08:19:00.30#ibcon#about to read 5, iclass 10, count 0 2006.176.08:19:00.30#ibcon#read 5, iclass 10, count 0 2006.176.08:19:00.30#ibcon#about to read 6, iclass 10, count 0 2006.176.08:19:00.30#ibcon#read 6, iclass 10, count 0 2006.176.08:19:00.30#ibcon#end of sib2, iclass 10, count 0 2006.176.08:19:00.30#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:19:00.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:19:00.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:19:00.30#ibcon#*before write, iclass 10, count 0 2006.176.08:19:00.30#ibcon#enter sib2, iclass 10, count 0 2006.176.08:19:00.30#ibcon#flushed, iclass 10, count 0 2006.176.08:19:00.30#ibcon#about to write, iclass 10, count 0 2006.176.08:19:00.30#ibcon#wrote, iclass 10, count 0 2006.176.08:19:00.30#ibcon#about to read 3, iclass 10, count 0 2006.176.08:19:00.34#ibcon#read 3, iclass 10, count 0 2006.176.08:19:00.34#ibcon#about to read 4, iclass 10, count 0 2006.176.08:19:00.34#ibcon#read 4, iclass 10, count 0 2006.176.08:19:00.34#ibcon#about to read 5, iclass 10, count 0 2006.176.08:19:00.34#ibcon#read 5, iclass 10, count 0 2006.176.08:19:00.34#ibcon#about to read 6, iclass 10, count 0 2006.176.08:19:00.34#ibcon#read 6, iclass 10, count 0 2006.176.08:19:00.34#ibcon#end of sib2, iclass 10, count 0 2006.176.08:19:00.34#ibcon#*after write, iclass 10, count 0 2006.176.08:19:00.34#ibcon#*before return 0, iclass 10, count 0 2006.176.08:19:00.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:19:00.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.176.08:19:00.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:19:00.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:19:00.34$vc4f8/va=8,6 2006.176.08:19:00.34#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.176.08:19:00.34#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.176.08:19:00.34#ibcon#ireg 11 cls_cnt 2 2006.176.08:19:00.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:19:00.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:19:00.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:19:00.40#ibcon#enter wrdev, iclass 12, count 2 2006.176.08:19:00.40#ibcon#first serial, iclass 12, count 2 2006.176.08:19:00.40#ibcon#enter sib2, iclass 12, count 2 2006.176.08:19:00.40#ibcon#flushed, iclass 12, count 2 2006.176.08:19:00.40#ibcon#about to write, iclass 12, count 2 2006.176.08:19:00.40#ibcon#wrote, iclass 12, count 2 2006.176.08:19:00.40#ibcon#about to read 3, iclass 12, count 2 2006.176.08:19:00.42#ibcon#read 3, iclass 12, count 2 2006.176.08:19:00.42#ibcon#about to read 4, iclass 12, count 2 2006.176.08:19:00.42#ibcon#read 4, iclass 12, count 2 2006.176.08:19:00.42#ibcon#about to read 5, iclass 12, count 2 2006.176.08:19:00.42#ibcon#read 5, iclass 12, count 2 2006.176.08:19:00.42#ibcon#about to read 6, iclass 12, count 2 2006.176.08:19:00.42#ibcon#read 6, iclass 12, count 2 2006.176.08:19:00.42#ibcon#end of sib2, iclass 12, count 2 2006.176.08:19:00.42#ibcon#*mode == 0, iclass 12, count 2 2006.176.08:19:00.42#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.176.08:19:00.42#ibcon#[25=AT08-06\r\n] 2006.176.08:19:00.42#ibcon#*before write, iclass 12, count 2 2006.176.08:19:00.42#ibcon#enter sib2, iclass 12, count 2 2006.176.08:19:00.42#ibcon#flushed, iclass 12, count 2 2006.176.08:19:00.42#ibcon#about to write, iclass 12, count 2 2006.176.08:19:00.42#ibcon#wrote, iclass 12, count 2 2006.176.08:19:00.42#ibcon#about to read 3, iclass 12, count 2 2006.176.08:19:00.45#ibcon#read 3, iclass 12, count 2 2006.176.08:19:00.45#ibcon#about to read 4, iclass 12, count 2 2006.176.08:19:00.45#ibcon#read 4, iclass 12, count 2 2006.176.08:19:00.45#ibcon#about to read 5, iclass 12, count 2 2006.176.08:19:00.45#ibcon#read 5, iclass 12, count 2 2006.176.08:19:00.45#ibcon#about to read 6, iclass 12, count 2 2006.176.08:19:00.45#ibcon#read 6, iclass 12, count 2 2006.176.08:19:00.45#ibcon#end of sib2, iclass 12, count 2 2006.176.08:19:00.45#ibcon#*after write, iclass 12, count 2 2006.176.08:19:00.45#ibcon#*before return 0, iclass 12, count 2 2006.176.08:19:00.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:19:00.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.176.08:19:00.45#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.176.08:19:00.45#ibcon#ireg 7 cls_cnt 0 2006.176.08:19:00.45#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:19:00.57#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:19:00.57#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:19:00.57#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:19:00.57#ibcon#first serial, iclass 12, count 0 2006.176.08:19:00.57#ibcon#enter sib2, iclass 12, count 0 2006.176.08:19:00.57#ibcon#flushed, iclass 12, count 0 2006.176.08:19:00.57#ibcon#about to write, iclass 12, count 0 2006.176.08:19:00.57#ibcon#wrote, iclass 12, count 0 2006.176.08:19:00.57#ibcon#about to read 3, iclass 12, count 0 2006.176.08:19:00.59#ibcon#read 3, iclass 12, count 0 2006.176.08:19:00.59#ibcon#about to read 4, iclass 12, count 0 2006.176.08:19:00.59#ibcon#read 4, iclass 12, count 0 2006.176.08:19:00.59#ibcon#about to read 5, iclass 12, count 0 2006.176.08:19:00.59#ibcon#read 5, iclass 12, count 0 2006.176.08:19:00.59#ibcon#about to read 6, iclass 12, count 0 2006.176.08:19:00.59#ibcon#read 6, iclass 12, count 0 2006.176.08:19:00.59#ibcon#end of sib2, iclass 12, count 0 2006.176.08:19:00.59#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:19:00.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:19:00.59#ibcon#[25=USB\r\n] 2006.176.08:19:00.59#ibcon#*before write, iclass 12, count 0 2006.176.08:19:00.59#ibcon#enter sib2, iclass 12, count 0 2006.176.08:19:00.59#ibcon#flushed, iclass 12, count 0 2006.176.08:19:00.59#ibcon#about to write, iclass 12, count 0 2006.176.08:19:00.59#ibcon#wrote, iclass 12, count 0 2006.176.08:19:00.59#ibcon#about to read 3, iclass 12, count 0 2006.176.08:19:00.62#ibcon#read 3, iclass 12, count 0 2006.176.08:19:00.62#ibcon#about to read 4, iclass 12, count 0 2006.176.08:19:00.62#ibcon#read 4, iclass 12, count 0 2006.176.08:19:00.62#ibcon#about to read 5, iclass 12, count 0 2006.176.08:19:00.62#ibcon#read 5, iclass 12, count 0 2006.176.08:19:00.62#ibcon#about to read 6, iclass 12, count 0 2006.176.08:19:00.62#ibcon#read 6, iclass 12, count 0 2006.176.08:19:00.62#ibcon#end of sib2, iclass 12, count 0 2006.176.08:19:00.62#ibcon#*after write, iclass 12, count 0 2006.176.08:19:00.62#ibcon#*before return 0, iclass 12, count 0 2006.176.08:19:00.62#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:19:00.62#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.176.08:19:00.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:19:00.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:19:00.62$vc4f8/vblo=1,632.99 2006.176.08:19:00.62#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.176.08:19:00.62#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.176.08:19:00.62#ibcon#ireg 17 cls_cnt 0 2006.176.08:19:00.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:19:00.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:19:00.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:19:00.62#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:19:00.62#ibcon#first serial, iclass 14, count 0 2006.176.08:19:00.62#ibcon#enter sib2, iclass 14, count 0 2006.176.08:19:00.62#ibcon#flushed, iclass 14, count 0 2006.176.08:19:00.62#ibcon#about to write, iclass 14, count 0 2006.176.08:19:00.62#ibcon#wrote, iclass 14, count 0 2006.176.08:19:00.62#ibcon#about to read 3, iclass 14, count 0 2006.176.08:19:00.64#ibcon#read 3, iclass 14, count 0 2006.176.08:19:00.64#ibcon#about to read 4, iclass 14, count 0 2006.176.08:19:00.64#ibcon#read 4, iclass 14, count 0 2006.176.08:19:00.64#ibcon#about to read 5, iclass 14, count 0 2006.176.08:19:00.64#ibcon#read 5, iclass 14, count 0 2006.176.08:19:00.64#ibcon#about to read 6, iclass 14, count 0 2006.176.08:19:00.64#ibcon#read 6, iclass 14, count 0 2006.176.08:19:00.64#ibcon#end of sib2, iclass 14, count 0 2006.176.08:19:00.64#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:19:00.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:19:00.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:19:00.64#ibcon#*before write, iclass 14, count 0 2006.176.08:19:00.64#ibcon#enter sib2, iclass 14, count 0 2006.176.08:19:00.64#ibcon#flushed, iclass 14, count 0 2006.176.08:19:00.64#ibcon#about to write, iclass 14, count 0 2006.176.08:19:00.64#ibcon#wrote, iclass 14, count 0 2006.176.08:19:00.64#ibcon#about to read 3, iclass 14, count 0 2006.176.08:19:00.68#ibcon#read 3, iclass 14, count 0 2006.176.08:19:00.68#ibcon#about to read 4, iclass 14, count 0 2006.176.08:19:00.68#ibcon#read 4, iclass 14, count 0 2006.176.08:19:00.68#ibcon#about to read 5, iclass 14, count 0 2006.176.08:19:00.68#ibcon#read 5, iclass 14, count 0 2006.176.08:19:00.68#ibcon#about to read 6, iclass 14, count 0 2006.176.08:19:00.68#ibcon#read 6, iclass 14, count 0 2006.176.08:19:00.68#ibcon#end of sib2, iclass 14, count 0 2006.176.08:19:00.68#ibcon#*after write, iclass 14, count 0 2006.176.08:19:00.68#ibcon#*before return 0, iclass 14, count 0 2006.176.08:19:00.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:19:00.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.176.08:19:00.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:19:00.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:19:00.68$vc4f8/vb=1,4 2006.176.08:19:00.68#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.176.08:19:00.68#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.176.08:19:00.68#ibcon#ireg 11 cls_cnt 2 2006.176.08:19:00.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:19:00.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:19:00.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:19:00.68#ibcon#enter wrdev, iclass 16, count 2 2006.176.08:19:00.68#ibcon#first serial, iclass 16, count 2 2006.176.08:19:00.68#ibcon#enter sib2, iclass 16, count 2 2006.176.08:19:00.68#ibcon#flushed, iclass 16, count 2 2006.176.08:19:00.68#ibcon#about to write, iclass 16, count 2 2006.176.08:19:00.68#ibcon#wrote, iclass 16, count 2 2006.176.08:19:00.68#ibcon#about to read 3, iclass 16, count 2 2006.176.08:19:00.70#ibcon#read 3, iclass 16, count 2 2006.176.08:19:00.70#ibcon#about to read 4, iclass 16, count 2 2006.176.08:19:00.70#ibcon#read 4, iclass 16, count 2 2006.176.08:19:00.70#ibcon#about to read 5, iclass 16, count 2 2006.176.08:19:00.70#ibcon#read 5, iclass 16, count 2 2006.176.08:19:00.70#ibcon#about to read 6, iclass 16, count 2 2006.176.08:19:00.70#ibcon#read 6, iclass 16, count 2 2006.176.08:19:00.70#ibcon#end of sib2, iclass 16, count 2 2006.176.08:19:00.70#ibcon#*mode == 0, iclass 16, count 2 2006.176.08:19:00.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.176.08:19:00.70#ibcon#[27=AT01-04\r\n] 2006.176.08:19:00.70#ibcon#*before write, iclass 16, count 2 2006.176.08:19:00.70#ibcon#enter sib2, iclass 16, count 2 2006.176.08:19:00.70#ibcon#flushed, iclass 16, count 2 2006.176.08:19:00.70#ibcon#about to write, iclass 16, count 2 2006.176.08:19:00.70#ibcon#wrote, iclass 16, count 2 2006.176.08:19:00.70#ibcon#about to read 3, iclass 16, count 2 2006.176.08:19:00.73#ibcon#read 3, iclass 16, count 2 2006.176.08:19:00.73#ibcon#about to read 4, iclass 16, count 2 2006.176.08:19:00.73#ibcon#read 4, iclass 16, count 2 2006.176.08:19:00.73#ibcon#about to read 5, iclass 16, count 2 2006.176.08:19:00.73#ibcon#read 5, iclass 16, count 2 2006.176.08:19:00.73#ibcon#about to read 6, iclass 16, count 2 2006.176.08:19:00.73#ibcon#read 6, iclass 16, count 2 2006.176.08:19:00.73#ibcon#end of sib2, iclass 16, count 2 2006.176.08:19:00.73#ibcon#*after write, iclass 16, count 2 2006.176.08:19:00.73#ibcon#*before return 0, iclass 16, count 2 2006.176.08:19:00.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:19:00.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.176.08:19:00.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.176.08:19:00.73#ibcon#ireg 7 cls_cnt 0 2006.176.08:19:00.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:19:00.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:19:00.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:19:00.85#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:19:00.85#ibcon#first serial, iclass 16, count 0 2006.176.08:19:00.85#ibcon#enter sib2, iclass 16, count 0 2006.176.08:19:00.85#ibcon#flushed, iclass 16, count 0 2006.176.08:19:00.85#ibcon#about to write, iclass 16, count 0 2006.176.08:19:00.85#ibcon#wrote, iclass 16, count 0 2006.176.08:19:00.85#ibcon#about to read 3, iclass 16, count 0 2006.176.08:19:00.87#ibcon#read 3, iclass 16, count 0 2006.176.08:19:00.87#ibcon#about to read 4, iclass 16, count 0 2006.176.08:19:00.87#ibcon#read 4, iclass 16, count 0 2006.176.08:19:00.87#ibcon#about to read 5, iclass 16, count 0 2006.176.08:19:00.87#ibcon#read 5, iclass 16, count 0 2006.176.08:19:00.87#ibcon#about to read 6, iclass 16, count 0 2006.176.08:19:00.87#ibcon#read 6, iclass 16, count 0 2006.176.08:19:00.87#ibcon#end of sib2, iclass 16, count 0 2006.176.08:19:00.87#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:19:00.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:19:00.87#ibcon#[27=USB\r\n] 2006.176.08:19:00.87#ibcon#*before write, iclass 16, count 0 2006.176.08:19:00.87#ibcon#enter sib2, iclass 16, count 0 2006.176.08:19:00.87#ibcon#flushed, iclass 16, count 0 2006.176.08:19:00.87#ibcon#about to write, iclass 16, count 0 2006.176.08:19:00.87#ibcon#wrote, iclass 16, count 0 2006.176.08:19:00.87#ibcon#about to read 3, iclass 16, count 0 2006.176.08:19:00.90#ibcon#read 3, iclass 16, count 0 2006.176.08:19:00.90#ibcon#about to read 4, iclass 16, count 0 2006.176.08:19:00.90#ibcon#read 4, iclass 16, count 0 2006.176.08:19:00.90#ibcon#about to read 5, iclass 16, count 0 2006.176.08:19:00.90#ibcon#read 5, iclass 16, count 0 2006.176.08:19:00.90#ibcon#about to read 6, iclass 16, count 0 2006.176.08:19:00.90#ibcon#read 6, iclass 16, count 0 2006.176.08:19:00.90#ibcon#end of sib2, iclass 16, count 0 2006.176.08:19:00.90#ibcon#*after write, iclass 16, count 0 2006.176.08:19:00.90#ibcon#*before return 0, iclass 16, count 0 2006.176.08:19:00.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:19:00.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.176.08:19:00.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:19:00.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:19:00.90$vc4f8/vblo=2,640.99 2006.176.08:19:00.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.176.08:19:00.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.176.08:19:00.90#ibcon#ireg 17 cls_cnt 0 2006.176.08:19:00.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:19:00.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:19:00.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:19:00.90#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:19:00.90#ibcon#first serial, iclass 18, count 0 2006.176.08:19:00.90#ibcon#enter sib2, iclass 18, count 0 2006.176.08:19:00.90#ibcon#flushed, iclass 18, count 0 2006.176.08:19:00.90#ibcon#about to write, iclass 18, count 0 2006.176.08:19:00.90#ibcon#wrote, iclass 18, count 0 2006.176.08:19:00.90#ibcon#about to read 3, iclass 18, count 0 2006.176.08:19:00.92#ibcon#read 3, iclass 18, count 0 2006.176.08:19:00.92#ibcon#about to read 4, iclass 18, count 0 2006.176.08:19:00.92#ibcon#read 4, iclass 18, count 0 2006.176.08:19:00.92#ibcon#about to read 5, iclass 18, count 0 2006.176.08:19:00.92#ibcon#read 5, iclass 18, count 0 2006.176.08:19:00.92#ibcon#about to read 6, iclass 18, count 0 2006.176.08:19:00.92#ibcon#read 6, iclass 18, count 0 2006.176.08:19:00.92#ibcon#end of sib2, iclass 18, count 0 2006.176.08:19:00.92#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:19:00.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:19:00.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:19:00.92#ibcon#*before write, iclass 18, count 0 2006.176.08:19:00.92#ibcon#enter sib2, iclass 18, count 0 2006.176.08:19:00.92#ibcon#flushed, iclass 18, count 0 2006.176.08:19:00.92#ibcon#about to write, iclass 18, count 0 2006.176.08:19:00.92#ibcon#wrote, iclass 18, count 0 2006.176.08:19:00.92#ibcon#about to read 3, iclass 18, count 0 2006.176.08:19:00.96#ibcon#read 3, iclass 18, count 0 2006.176.08:19:00.96#ibcon#about to read 4, iclass 18, count 0 2006.176.08:19:00.96#ibcon#read 4, iclass 18, count 0 2006.176.08:19:00.96#ibcon#about to read 5, iclass 18, count 0 2006.176.08:19:00.96#ibcon#read 5, iclass 18, count 0 2006.176.08:19:00.96#ibcon#about to read 6, iclass 18, count 0 2006.176.08:19:00.96#ibcon#read 6, iclass 18, count 0 2006.176.08:19:00.96#ibcon#end of sib2, iclass 18, count 0 2006.176.08:19:00.96#ibcon#*after write, iclass 18, count 0 2006.176.08:19:00.96#ibcon#*before return 0, iclass 18, count 0 2006.176.08:19:00.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:19:00.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.176.08:19:00.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:19:00.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:19:00.96$vc4f8/vb=2,4 2006.176.08:19:00.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.176.08:19:00.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.176.08:19:00.96#ibcon#ireg 11 cls_cnt 2 2006.176.08:19:00.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:19:01.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:19:01.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:19:01.02#ibcon#enter wrdev, iclass 20, count 2 2006.176.08:19:01.02#ibcon#first serial, iclass 20, count 2 2006.176.08:19:01.02#ibcon#enter sib2, iclass 20, count 2 2006.176.08:19:01.02#ibcon#flushed, iclass 20, count 2 2006.176.08:19:01.02#ibcon#about to write, iclass 20, count 2 2006.176.08:19:01.02#ibcon#wrote, iclass 20, count 2 2006.176.08:19:01.02#ibcon#about to read 3, iclass 20, count 2 2006.176.08:19:01.04#ibcon#read 3, iclass 20, count 2 2006.176.08:19:01.04#ibcon#about to read 4, iclass 20, count 2 2006.176.08:19:01.04#ibcon#read 4, iclass 20, count 2 2006.176.08:19:01.04#ibcon#about to read 5, iclass 20, count 2 2006.176.08:19:01.04#ibcon#read 5, iclass 20, count 2 2006.176.08:19:01.04#ibcon#about to read 6, iclass 20, count 2 2006.176.08:19:01.04#ibcon#read 6, iclass 20, count 2 2006.176.08:19:01.04#ibcon#end of sib2, iclass 20, count 2 2006.176.08:19:01.04#ibcon#*mode == 0, iclass 20, count 2 2006.176.08:19:01.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.176.08:19:01.04#ibcon#[27=AT02-04\r\n] 2006.176.08:19:01.04#ibcon#*before write, iclass 20, count 2 2006.176.08:19:01.04#ibcon#enter sib2, iclass 20, count 2 2006.176.08:19:01.04#ibcon#flushed, iclass 20, count 2 2006.176.08:19:01.04#ibcon#about to write, iclass 20, count 2 2006.176.08:19:01.04#ibcon#wrote, iclass 20, count 2 2006.176.08:19:01.04#ibcon#about to read 3, iclass 20, count 2 2006.176.08:19:01.07#ibcon#read 3, iclass 20, count 2 2006.176.08:19:01.07#ibcon#about to read 4, iclass 20, count 2 2006.176.08:19:01.07#ibcon#read 4, iclass 20, count 2 2006.176.08:19:01.07#ibcon#about to read 5, iclass 20, count 2 2006.176.08:19:01.07#ibcon#read 5, iclass 20, count 2 2006.176.08:19:01.07#ibcon#about to read 6, iclass 20, count 2 2006.176.08:19:01.07#ibcon#read 6, iclass 20, count 2 2006.176.08:19:01.07#ibcon#end of sib2, iclass 20, count 2 2006.176.08:19:01.07#ibcon#*after write, iclass 20, count 2 2006.176.08:19:01.07#ibcon#*before return 0, iclass 20, count 2 2006.176.08:19:01.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:19:01.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.176.08:19:01.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.176.08:19:01.07#ibcon#ireg 7 cls_cnt 0 2006.176.08:19:01.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:19:01.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:19:01.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:19:01.19#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:19:01.19#ibcon#first serial, iclass 20, count 0 2006.176.08:19:01.19#ibcon#enter sib2, iclass 20, count 0 2006.176.08:19:01.19#ibcon#flushed, iclass 20, count 0 2006.176.08:19:01.19#ibcon#about to write, iclass 20, count 0 2006.176.08:19:01.19#ibcon#wrote, iclass 20, count 0 2006.176.08:19:01.19#ibcon#about to read 3, iclass 20, count 0 2006.176.08:19:01.21#ibcon#read 3, iclass 20, count 0 2006.176.08:19:01.21#ibcon#about to read 4, iclass 20, count 0 2006.176.08:19:01.21#ibcon#read 4, iclass 20, count 0 2006.176.08:19:01.21#ibcon#about to read 5, iclass 20, count 0 2006.176.08:19:01.21#ibcon#read 5, iclass 20, count 0 2006.176.08:19:01.21#ibcon#about to read 6, iclass 20, count 0 2006.176.08:19:01.21#ibcon#read 6, iclass 20, count 0 2006.176.08:19:01.21#ibcon#end of sib2, iclass 20, count 0 2006.176.08:19:01.21#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:19:01.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:19:01.21#ibcon#[27=USB\r\n] 2006.176.08:19:01.21#ibcon#*before write, iclass 20, count 0 2006.176.08:19:01.21#ibcon#enter sib2, iclass 20, count 0 2006.176.08:19:01.21#ibcon#flushed, iclass 20, count 0 2006.176.08:19:01.21#ibcon#about to write, iclass 20, count 0 2006.176.08:19:01.21#ibcon#wrote, iclass 20, count 0 2006.176.08:19:01.21#ibcon#about to read 3, iclass 20, count 0 2006.176.08:19:01.24#ibcon#read 3, iclass 20, count 0 2006.176.08:19:01.24#ibcon#about to read 4, iclass 20, count 0 2006.176.08:19:01.24#ibcon#read 4, iclass 20, count 0 2006.176.08:19:01.24#ibcon#about to read 5, iclass 20, count 0 2006.176.08:19:01.24#ibcon#read 5, iclass 20, count 0 2006.176.08:19:01.24#ibcon#about to read 6, iclass 20, count 0 2006.176.08:19:01.24#ibcon#read 6, iclass 20, count 0 2006.176.08:19:01.24#ibcon#end of sib2, iclass 20, count 0 2006.176.08:19:01.24#ibcon#*after write, iclass 20, count 0 2006.176.08:19:01.24#ibcon#*before return 0, iclass 20, count 0 2006.176.08:19:01.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:19:01.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.176.08:19:01.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:19:01.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:19:01.24$vc4f8/vblo=3,656.99 2006.176.08:19:01.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.176.08:19:01.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.176.08:19:01.24#ibcon#ireg 17 cls_cnt 0 2006.176.08:19:01.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:19:01.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:19:01.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:19:01.24#ibcon#enter wrdev, iclass 22, count 0 2006.176.08:19:01.24#ibcon#first serial, iclass 22, count 0 2006.176.08:19:01.24#ibcon#enter sib2, iclass 22, count 0 2006.176.08:19:01.24#ibcon#flushed, iclass 22, count 0 2006.176.08:19:01.24#ibcon#about to write, iclass 22, count 0 2006.176.08:19:01.24#ibcon#wrote, iclass 22, count 0 2006.176.08:19:01.24#ibcon#about to read 3, iclass 22, count 0 2006.176.08:19:01.26#ibcon#read 3, iclass 22, count 0 2006.176.08:19:01.26#ibcon#about to read 4, iclass 22, count 0 2006.176.08:19:01.26#ibcon#read 4, iclass 22, count 0 2006.176.08:19:01.26#ibcon#about to read 5, iclass 22, count 0 2006.176.08:19:01.26#ibcon#read 5, iclass 22, count 0 2006.176.08:19:01.26#ibcon#about to read 6, iclass 22, count 0 2006.176.08:19:01.26#ibcon#read 6, iclass 22, count 0 2006.176.08:19:01.26#ibcon#end of sib2, iclass 22, count 0 2006.176.08:19:01.26#ibcon#*mode == 0, iclass 22, count 0 2006.176.08:19:01.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.08:19:01.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:19:01.26#ibcon#*before write, iclass 22, count 0 2006.176.08:19:01.26#ibcon#enter sib2, iclass 22, count 0 2006.176.08:19:01.26#ibcon#flushed, iclass 22, count 0 2006.176.08:19:01.26#ibcon#about to write, iclass 22, count 0 2006.176.08:19:01.26#ibcon#wrote, iclass 22, count 0 2006.176.08:19:01.26#ibcon#about to read 3, iclass 22, count 0 2006.176.08:19:01.30#ibcon#read 3, iclass 22, count 0 2006.176.08:19:01.30#ibcon#about to read 4, iclass 22, count 0 2006.176.08:19:01.30#ibcon#read 4, iclass 22, count 0 2006.176.08:19:01.30#ibcon#about to read 5, iclass 22, count 0 2006.176.08:19:01.30#ibcon#read 5, iclass 22, count 0 2006.176.08:19:01.30#ibcon#about to read 6, iclass 22, count 0 2006.176.08:19:01.30#ibcon#read 6, iclass 22, count 0 2006.176.08:19:01.30#ibcon#end of sib2, iclass 22, count 0 2006.176.08:19:01.30#ibcon#*after write, iclass 22, count 0 2006.176.08:19:01.30#ibcon#*before return 0, iclass 22, count 0 2006.176.08:19:01.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:19:01.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.176.08:19:01.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.08:19:01.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.08:19:01.30$vc4f8/vb=3,4 2006.176.08:19:01.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.176.08:19:01.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.176.08:19:01.30#ibcon#ireg 11 cls_cnt 2 2006.176.08:19:01.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:19:01.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:19:01.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:19:01.36#ibcon#enter wrdev, iclass 24, count 2 2006.176.08:19:01.36#ibcon#first serial, iclass 24, count 2 2006.176.08:19:01.36#ibcon#enter sib2, iclass 24, count 2 2006.176.08:19:01.36#ibcon#flushed, iclass 24, count 2 2006.176.08:19:01.36#ibcon#about to write, iclass 24, count 2 2006.176.08:19:01.36#ibcon#wrote, iclass 24, count 2 2006.176.08:19:01.36#ibcon#about to read 3, iclass 24, count 2 2006.176.08:19:01.38#ibcon#read 3, iclass 24, count 2 2006.176.08:19:01.38#ibcon#about to read 4, iclass 24, count 2 2006.176.08:19:01.38#ibcon#read 4, iclass 24, count 2 2006.176.08:19:01.38#ibcon#about to read 5, iclass 24, count 2 2006.176.08:19:01.38#ibcon#read 5, iclass 24, count 2 2006.176.08:19:01.38#ibcon#about to read 6, iclass 24, count 2 2006.176.08:19:01.38#ibcon#read 6, iclass 24, count 2 2006.176.08:19:01.38#ibcon#end of sib2, iclass 24, count 2 2006.176.08:19:01.38#ibcon#*mode == 0, iclass 24, count 2 2006.176.08:19:01.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.176.08:19:01.38#ibcon#[27=AT03-04\r\n] 2006.176.08:19:01.38#ibcon#*before write, iclass 24, count 2 2006.176.08:19:01.38#ibcon#enter sib2, iclass 24, count 2 2006.176.08:19:01.38#ibcon#flushed, iclass 24, count 2 2006.176.08:19:01.38#ibcon#about to write, iclass 24, count 2 2006.176.08:19:01.38#ibcon#wrote, iclass 24, count 2 2006.176.08:19:01.38#ibcon#about to read 3, iclass 24, count 2 2006.176.08:19:01.41#ibcon#read 3, iclass 24, count 2 2006.176.08:19:01.41#ibcon#about to read 4, iclass 24, count 2 2006.176.08:19:01.41#ibcon#read 4, iclass 24, count 2 2006.176.08:19:01.41#ibcon#about to read 5, iclass 24, count 2 2006.176.08:19:01.41#ibcon#read 5, iclass 24, count 2 2006.176.08:19:01.41#ibcon#about to read 6, iclass 24, count 2 2006.176.08:19:01.41#ibcon#read 6, iclass 24, count 2 2006.176.08:19:01.41#ibcon#end of sib2, iclass 24, count 2 2006.176.08:19:01.41#ibcon#*after write, iclass 24, count 2 2006.176.08:19:01.41#ibcon#*before return 0, iclass 24, count 2 2006.176.08:19:01.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:19:01.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.176.08:19:01.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.176.08:19:01.41#ibcon#ireg 7 cls_cnt 0 2006.176.08:19:01.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:19:01.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:19:01.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:19:01.53#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:19:01.53#ibcon#first serial, iclass 24, count 0 2006.176.08:19:01.53#ibcon#enter sib2, iclass 24, count 0 2006.176.08:19:01.53#ibcon#flushed, iclass 24, count 0 2006.176.08:19:01.53#ibcon#about to write, iclass 24, count 0 2006.176.08:19:01.53#ibcon#wrote, iclass 24, count 0 2006.176.08:19:01.53#ibcon#about to read 3, iclass 24, count 0 2006.176.08:19:01.55#ibcon#read 3, iclass 24, count 0 2006.176.08:19:01.55#ibcon#about to read 4, iclass 24, count 0 2006.176.08:19:01.55#ibcon#read 4, iclass 24, count 0 2006.176.08:19:01.55#ibcon#about to read 5, iclass 24, count 0 2006.176.08:19:01.55#ibcon#read 5, iclass 24, count 0 2006.176.08:19:01.55#ibcon#about to read 6, iclass 24, count 0 2006.176.08:19:01.55#ibcon#read 6, iclass 24, count 0 2006.176.08:19:01.55#ibcon#end of sib2, iclass 24, count 0 2006.176.08:19:01.55#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:19:01.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:19:01.55#ibcon#[27=USB\r\n] 2006.176.08:19:01.55#ibcon#*before write, iclass 24, count 0 2006.176.08:19:01.55#ibcon#enter sib2, iclass 24, count 0 2006.176.08:19:01.55#ibcon#flushed, iclass 24, count 0 2006.176.08:19:01.55#ibcon#about to write, iclass 24, count 0 2006.176.08:19:01.55#ibcon#wrote, iclass 24, count 0 2006.176.08:19:01.55#ibcon#about to read 3, iclass 24, count 0 2006.176.08:19:01.58#ibcon#read 3, iclass 24, count 0 2006.176.08:19:01.58#ibcon#about to read 4, iclass 24, count 0 2006.176.08:19:01.58#ibcon#read 4, iclass 24, count 0 2006.176.08:19:01.58#ibcon#about to read 5, iclass 24, count 0 2006.176.08:19:01.58#ibcon#read 5, iclass 24, count 0 2006.176.08:19:01.58#ibcon#about to read 6, iclass 24, count 0 2006.176.08:19:01.58#ibcon#read 6, iclass 24, count 0 2006.176.08:19:01.58#ibcon#end of sib2, iclass 24, count 0 2006.176.08:19:01.58#ibcon#*after write, iclass 24, count 0 2006.176.08:19:01.58#ibcon#*before return 0, iclass 24, count 0 2006.176.08:19:01.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:19:01.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.176.08:19:01.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:19:01.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:19:01.58$vc4f8/vblo=4,712.99 2006.176.08:19:01.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.176.08:19:01.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.176.08:19:01.58#ibcon#ireg 17 cls_cnt 0 2006.176.08:19:01.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:19:01.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:19:01.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:19:01.58#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:19:01.58#ibcon#first serial, iclass 26, count 0 2006.176.08:19:01.58#ibcon#enter sib2, iclass 26, count 0 2006.176.08:19:01.58#ibcon#flushed, iclass 26, count 0 2006.176.08:19:01.58#ibcon#about to write, iclass 26, count 0 2006.176.08:19:01.58#ibcon#wrote, iclass 26, count 0 2006.176.08:19:01.58#ibcon#about to read 3, iclass 26, count 0 2006.176.08:19:01.60#ibcon#read 3, iclass 26, count 0 2006.176.08:19:01.60#ibcon#about to read 4, iclass 26, count 0 2006.176.08:19:01.60#ibcon#read 4, iclass 26, count 0 2006.176.08:19:01.60#ibcon#about to read 5, iclass 26, count 0 2006.176.08:19:01.60#ibcon#read 5, iclass 26, count 0 2006.176.08:19:01.60#ibcon#about to read 6, iclass 26, count 0 2006.176.08:19:01.60#ibcon#read 6, iclass 26, count 0 2006.176.08:19:01.60#ibcon#end of sib2, iclass 26, count 0 2006.176.08:19:01.60#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:19:01.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:19:01.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:19:01.60#ibcon#*before write, iclass 26, count 0 2006.176.08:19:01.60#ibcon#enter sib2, iclass 26, count 0 2006.176.08:19:01.60#ibcon#flushed, iclass 26, count 0 2006.176.08:19:01.60#ibcon#about to write, iclass 26, count 0 2006.176.08:19:01.60#ibcon#wrote, iclass 26, count 0 2006.176.08:19:01.60#ibcon#about to read 3, iclass 26, count 0 2006.176.08:19:01.64#ibcon#read 3, iclass 26, count 0 2006.176.08:19:01.64#ibcon#about to read 4, iclass 26, count 0 2006.176.08:19:01.64#ibcon#read 4, iclass 26, count 0 2006.176.08:19:01.64#ibcon#about to read 5, iclass 26, count 0 2006.176.08:19:01.64#ibcon#read 5, iclass 26, count 0 2006.176.08:19:01.64#ibcon#about to read 6, iclass 26, count 0 2006.176.08:19:01.64#ibcon#read 6, iclass 26, count 0 2006.176.08:19:01.64#ibcon#end of sib2, iclass 26, count 0 2006.176.08:19:01.64#ibcon#*after write, iclass 26, count 0 2006.176.08:19:01.64#ibcon#*before return 0, iclass 26, count 0 2006.176.08:19:01.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:19:01.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.176.08:19:01.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:19:01.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:19:01.64$vc4f8/vb=4,4 2006.176.08:19:01.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.176.08:19:01.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.176.08:19:01.64#ibcon#ireg 11 cls_cnt 2 2006.176.08:19:01.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:19:01.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:19:01.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:19:01.70#ibcon#enter wrdev, iclass 28, count 2 2006.176.08:19:01.70#ibcon#first serial, iclass 28, count 2 2006.176.08:19:01.70#ibcon#enter sib2, iclass 28, count 2 2006.176.08:19:01.70#ibcon#flushed, iclass 28, count 2 2006.176.08:19:01.70#ibcon#about to write, iclass 28, count 2 2006.176.08:19:01.70#ibcon#wrote, iclass 28, count 2 2006.176.08:19:01.70#ibcon#about to read 3, iclass 28, count 2 2006.176.08:19:01.72#ibcon#read 3, iclass 28, count 2 2006.176.08:19:01.72#ibcon#about to read 4, iclass 28, count 2 2006.176.08:19:01.72#ibcon#read 4, iclass 28, count 2 2006.176.08:19:01.72#ibcon#about to read 5, iclass 28, count 2 2006.176.08:19:01.72#ibcon#read 5, iclass 28, count 2 2006.176.08:19:01.72#ibcon#about to read 6, iclass 28, count 2 2006.176.08:19:01.72#ibcon#read 6, iclass 28, count 2 2006.176.08:19:01.72#ibcon#end of sib2, iclass 28, count 2 2006.176.08:19:01.72#ibcon#*mode == 0, iclass 28, count 2 2006.176.08:19:01.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.176.08:19:01.72#ibcon#[27=AT04-04\r\n] 2006.176.08:19:01.72#ibcon#*before write, iclass 28, count 2 2006.176.08:19:01.72#ibcon#enter sib2, iclass 28, count 2 2006.176.08:19:01.72#ibcon#flushed, iclass 28, count 2 2006.176.08:19:01.72#ibcon#about to write, iclass 28, count 2 2006.176.08:19:01.72#ibcon#wrote, iclass 28, count 2 2006.176.08:19:01.72#ibcon#about to read 3, iclass 28, count 2 2006.176.08:19:01.75#ibcon#read 3, iclass 28, count 2 2006.176.08:19:01.75#ibcon#about to read 4, iclass 28, count 2 2006.176.08:19:01.75#ibcon#read 4, iclass 28, count 2 2006.176.08:19:01.75#ibcon#about to read 5, iclass 28, count 2 2006.176.08:19:01.75#ibcon#read 5, iclass 28, count 2 2006.176.08:19:01.75#ibcon#about to read 6, iclass 28, count 2 2006.176.08:19:01.75#ibcon#read 6, iclass 28, count 2 2006.176.08:19:01.75#ibcon#end of sib2, iclass 28, count 2 2006.176.08:19:01.75#ibcon#*after write, iclass 28, count 2 2006.176.08:19:01.75#ibcon#*before return 0, iclass 28, count 2 2006.176.08:19:01.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:19:01.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.176.08:19:01.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.176.08:19:01.75#ibcon#ireg 7 cls_cnt 0 2006.176.08:19:01.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:19:01.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:19:01.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:19:01.87#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:19:01.87#ibcon#first serial, iclass 28, count 0 2006.176.08:19:01.87#ibcon#enter sib2, iclass 28, count 0 2006.176.08:19:01.87#ibcon#flushed, iclass 28, count 0 2006.176.08:19:01.87#ibcon#about to write, iclass 28, count 0 2006.176.08:19:01.87#ibcon#wrote, iclass 28, count 0 2006.176.08:19:01.87#ibcon#about to read 3, iclass 28, count 0 2006.176.08:19:01.89#ibcon#read 3, iclass 28, count 0 2006.176.08:19:01.89#ibcon#about to read 4, iclass 28, count 0 2006.176.08:19:01.89#ibcon#read 4, iclass 28, count 0 2006.176.08:19:01.89#ibcon#about to read 5, iclass 28, count 0 2006.176.08:19:01.89#ibcon#read 5, iclass 28, count 0 2006.176.08:19:01.89#ibcon#about to read 6, iclass 28, count 0 2006.176.08:19:01.89#ibcon#read 6, iclass 28, count 0 2006.176.08:19:01.89#ibcon#end of sib2, iclass 28, count 0 2006.176.08:19:01.89#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:19:01.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:19:01.89#ibcon#[27=USB\r\n] 2006.176.08:19:01.89#ibcon#*before write, iclass 28, count 0 2006.176.08:19:01.89#ibcon#enter sib2, iclass 28, count 0 2006.176.08:19:01.89#ibcon#flushed, iclass 28, count 0 2006.176.08:19:01.89#ibcon#about to write, iclass 28, count 0 2006.176.08:19:01.89#ibcon#wrote, iclass 28, count 0 2006.176.08:19:01.89#ibcon#about to read 3, iclass 28, count 0 2006.176.08:19:01.92#ibcon#read 3, iclass 28, count 0 2006.176.08:19:01.92#ibcon#about to read 4, iclass 28, count 0 2006.176.08:19:01.92#ibcon#read 4, iclass 28, count 0 2006.176.08:19:01.92#ibcon#about to read 5, iclass 28, count 0 2006.176.08:19:01.92#ibcon#read 5, iclass 28, count 0 2006.176.08:19:01.92#ibcon#about to read 6, iclass 28, count 0 2006.176.08:19:01.92#ibcon#read 6, iclass 28, count 0 2006.176.08:19:01.92#ibcon#end of sib2, iclass 28, count 0 2006.176.08:19:01.92#ibcon#*after write, iclass 28, count 0 2006.176.08:19:01.92#ibcon#*before return 0, iclass 28, count 0 2006.176.08:19:01.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:19:01.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.176.08:19:01.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:19:01.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:19:01.92$vc4f8/vblo=5,744.99 2006.176.08:19:01.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.176.08:19:01.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.176.08:19:01.92#ibcon#ireg 17 cls_cnt 0 2006.176.08:19:01.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:19:01.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:19:01.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:19:01.92#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:19:01.92#ibcon#first serial, iclass 30, count 0 2006.176.08:19:01.92#ibcon#enter sib2, iclass 30, count 0 2006.176.08:19:01.92#ibcon#flushed, iclass 30, count 0 2006.176.08:19:01.92#ibcon#about to write, iclass 30, count 0 2006.176.08:19:01.92#ibcon#wrote, iclass 30, count 0 2006.176.08:19:01.92#ibcon#about to read 3, iclass 30, count 0 2006.176.08:19:01.94#ibcon#read 3, iclass 30, count 0 2006.176.08:19:01.94#ibcon#about to read 4, iclass 30, count 0 2006.176.08:19:01.94#ibcon#read 4, iclass 30, count 0 2006.176.08:19:01.94#ibcon#about to read 5, iclass 30, count 0 2006.176.08:19:01.94#ibcon#read 5, iclass 30, count 0 2006.176.08:19:01.94#ibcon#about to read 6, iclass 30, count 0 2006.176.08:19:01.94#ibcon#read 6, iclass 30, count 0 2006.176.08:19:01.94#ibcon#end of sib2, iclass 30, count 0 2006.176.08:19:01.94#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:19:01.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:19:01.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:19:01.94#ibcon#*before write, iclass 30, count 0 2006.176.08:19:01.94#ibcon#enter sib2, iclass 30, count 0 2006.176.08:19:01.94#ibcon#flushed, iclass 30, count 0 2006.176.08:19:01.94#ibcon#about to write, iclass 30, count 0 2006.176.08:19:01.94#ibcon#wrote, iclass 30, count 0 2006.176.08:19:01.94#ibcon#about to read 3, iclass 30, count 0 2006.176.08:19:01.98#ibcon#read 3, iclass 30, count 0 2006.176.08:19:01.98#ibcon#about to read 4, iclass 30, count 0 2006.176.08:19:01.98#ibcon#read 4, iclass 30, count 0 2006.176.08:19:01.98#ibcon#about to read 5, iclass 30, count 0 2006.176.08:19:01.98#ibcon#read 5, iclass 30, count 0 2006.176.08:19:01.98#ibcon#about to read 6, iclass 30, count 0 2006.176.08:19:01.98#ibcon#read 6, iclass 30, count 0 2006.176.08:19:01.98#ibcon#end of sib2, iclass 30, count 0 2006.176.08:19:01.98#ibcon#*after write, iclass 30, count 0 2006.176.08:19:01.98#ibcon#*before return 0, iclass 30, count 0 2006.176.08:19:01.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:19:01.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.176.08:19:01.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:19:01.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:19:01.98$vc4f8/vb=5,4 2006.176.08:19:01.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.176.08:19:01.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.176.08:19:01.98#ibcon#ireg 11 cls_cnt 2 2006.176.08:19:01.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:19:02.03#abcon#<5=/06 3.3 6.3 23.80 931008.6\r\n> 2006.176.08:19:02.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:19:02.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:19:02.04#ibcon#enter wrdev, iclass 32, count 2 2006.176.08:19:02.04#ibcon#first serial, iclass 32, count 2 2006.176.08:19:02.04#ibcon#enter sib2, iclass 32, count 2 2006.176.08:19:02.04#ibcon#flushed, iclass 32, count 2 2006.176.08:19:02.04#ibcon#about to write, iclass 32, count 2 2006.176.08:19:02.04#ibcon#wrote, iclass 32, count 2 2006.176.08:19:02.04#ibcon#about to read 3, iclass 32, count 2 2006.176.08:19:02.05#abcon#{5=INTERFACE CLEAR} 2006.176.08:19:02.06#ibcon#read 3, iclass 32, count 2 2006.176.08:19:02.06#ibcon#about to read 4, iclass 32, count 2 2006.176.08:19:02.06#ibcon#read 4, iclass 32, count 2 2006.176.08:19:02.06#ibcon#about to read 5, iclass 32, count 2 2006.176.08:19:02.06#ibcon#read 5, iclass 32, count 2 2006.176.08:19:02.06#ibcon#about to read 6, iclass 32, count 2 2006.176.08:19:02.06#ibcon#read 6, iclass 32, count 2 2006.176.08:19:02.06#ibcon#end of sib2, iclass 32, count 2 2006.176.08:19:02.06#ibcon#*mode == 0, iclass 32, count 2 2006.176.08:19:02.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.176.08:19:02.06#ibcon#[27=AT05-04\r\n] 2006.176.08:19:02.06#ibcon#*before write, iclass 32, count 2 2006.176.08:19:02.06#ibcon#enter sib2, iclass 32, count 2 2006.176.08:19:02.06#ibcon#flushed, iclass 32, count 2 2006.176.08:19:02.06#ibcon#about to write, iclass 32, count 2 2006.176.08:19:02.06#ibcon#wrote, iclass 32, count 2 2006.176.08:19:02.06#ibcon#about to read 3, iclass 32, count 2 2006.176.08:19:02.09#ibcon#read 3, iclass 32, count 2 2006.176.08:19:02.09#ibcon#about to read 4, iclass 32, count 2 2006.176.08:19:02.09#ibcon#read 4, iclass 32, count 2 2006.176.08:19:02.09#ibcon#about to read 5, iclass 32, count 2 2006.176.08:19:02.09#ibcon#read 5, iclass 32, count 2 2006.176.08:19:02.09#ibcon#about to read 6, iclass 32, count 2 2006.176.08:19:02.09#ibcon#read 6, iclass 32, count 2 2006.176.08:19:02.09#ibcon#end of sib2, iclass 32, count 2 2006.176.08:19:02.09#ibcon#*after write, iclass 32, count 2 2006.176.08:19:02.09#ibcon#*before return 0, iclass 32, count 2 2006.176.08:19:02.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:19:02.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.176.08:19:02.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.176.08:19:02.09#ibcon#ireg 7 cls_cnt 0 2006.176.08:19:02.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:19:02.11#abcon#[5=S1D000X0/0*\r\n] 2006.176.08:19:02.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:19:02.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:19:02.21#ibcon#enter wrdev, iclass 32, count 0 2006.176.08:19:02.21#ibcon#first serial, iclass 32, count 0 2006.176.08:19:02.21#ibcon#enter sib2, iclass 32, count 0 2006.176.08:19:02.21#ibcon#flushed, iclass 32, count 0 2006.176.08:19:02.21#ibcon#about to write, iclass 32, count 0 2006.176.08:19:02.21#ibcon#wrote, iclass 32, count 0 2006.176.08:19:02.21#ibcon#about to read 3, iclass 32, count 0 2006.176.08:19:02.23#ibcon#read 3, iclass 32, count 0 2006.176.08:19:02.23#ibcon#about to read 4, iclass 32, count 0 2006.176.08:19:02.23#ibcon#read 4, iclass 32, count 0 2006.176.08:19:02.23#ibcon#about to read 5, iclass 32, count 0 2006.176.08:19:02.23#ibcon#read 5, iclass 32, count 0 2006.176.08:19:02.23#ibcon#about to read 6, iclass 32, count 0 2006.176.08:19:02.23#ibcon#read 6, iclass 32, count 0 2006.176.08:19:02.23#ibcon#end of sib2, iclass 32, count 0 2006.176.08:19:02.23#ibcon#*mode == 0, iclass 32, count 0 2006.176.08:19:02.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.08:19:02.23#ibcon#[27=USB\r\n] 2006.176.08:19:02.23#ibcon#*before write, iclass 32, count 0 2006.176.08:19:02.23#ibcon#enter sib2, iclass 32, count 0 2006.176.08:19:02.23#ibcon#flushed, iclass 32, count 0 2006.176.08:19:02.23#ibcon#about to write, iclass 32, count 0 2006.176.08:19:02.23#ibcon#wrote, iclass 32, count 0 2006.176.08:19:02.23#ibcon#about to read 3, iclass 32, count 0 2006.176.08:19:02.26#ibcon#read 3, iclass 32, count 0 2006.176.08:19:02.26#ibcon#about to read 4, iclass 32, count 0 2006.176.08:19:02.26#ibcon#read 4, iclass 32, count 0 2006.176.08:19:02.26#ibcon#about to read 5, iclass 32, count 0 2006.176.08:19:02.26#ibcon#read 5, iclass 32, count 0 2006.176.08:19:02.26#ibcon#about to read 6, iclass 32, count 0 2006.176.08:19:02.26#ibcon#read 6, iclass 32, count 0 2006.176.08:19:02.26#ibcon#end of sib2, iclass 32, count 0 2006.176.08:19:02.26#ibcon#*after write, iclass 32, count 0 2006.176.08:19:02.26#ibcon#*before return 0, iclass 32, count 0 2006.176.08:19:02.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:19:02.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.176.08:19:02.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.08:19:02.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.08:19:02.26$vc4f8/vblo=6,752.99 2006.176.08:19:02.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.176.08:19:02.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.176.08:19:02.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:19:02.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:19:02.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:19:02.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:19:02.26#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:19:02.26#ibcon#first serial, iclass 38, count 0 2006.176.08:19:02.26#ibcon#enter sib2, iclass 38, count 0 2006.176.08:19:02.26#ibcon#flushed, iclass 38, count 0 2006.176.08:19:02.26#ibcon#about to write, iclass 38, count 0 2006.176.08:19:02.26#ibcon#wrote, iclass 38, count 0 2006.176.08:19:02.26#ibcon#about to read 3, iclass 38, count 0 2006.176.08:19:02.28#ibcon#read 3, iclass 38, count 0 2006.176.08:19:02.28#ibcon#about to read 4, iclass 38, count 0 2006.176.08:19:02.28#ibcon#read 4, iclass 38, count 0 2006.176.08:19:02.28#ibcon#about to read 5, iclass 38, count 0 2006.176.08:19:02.28#ibcon#read 5, iclass 38, count 0 2006.176.08:19:02.28#ibcon#about to read 6, iclass 38, count 0 2006.176.08:19:02.28#ibcon#read 6, iclass 38, count 0 2006.176.08:19:02.28#ibcon#end of sib2, iclass 38, count 0 2006.176.08:19:02.28#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:19:02.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:19:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:19:02.28#ibcon#*before write, iclass 38, count 0 2006.176.08:19:02.28#ibcon#enter sib2, iclass 38, count 0 2006.176.08:19:02.28#ibcon#flushed, iclass 38, count 0 2006.176.08:19:02.28#ibcon#about to write, iclass 38, count 0 2006.176.08:19:02.28#ibcon#wrote, iclass 38, count 0 2006.176.08:19:02.28#ibcon#about to read 3, iclass 38, count 0 2006.176.08:19:02.32#ibcon#read 3, iclass 38, count 0 2006.176.08:19:02.32#ibcon#about to read 4, iclass 38, count 0 2006.176.08:19:02.32#ibcon#read 4, iclass 38, count 0 2006.176.08:19:02.32#ibcon#about to read 5, iclass 38, count 0 2006.176.08:19:02.32#ibcon#read 5, iclass 38, count 0 2006.176.08:19:02.32#ibcon#about to read 6, iclass 38, count 0 2006.176.08:19:02.32#ibcon#read 6, iclass 38, count 0 2006.176.08:19:02.32#ibcon#end of sib2, iclass 38, count 0 2006.176.08:19:02.32#ibcon#*after write, iclass 38, count 0 2006.176.08:19:02.32#ibcon#*before return 0, iclass 38, count 0 2006.176.08:19:02.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:19:02.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.176.08:19:02.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:19:02.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:19:02.32$vc4f8/vb=6,4 2006.176.08:19:02.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.176.08:19:02.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.176.08:19:02.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:19:02.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:19:02.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:19:02.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:19:02.38#ibcon#enter wrdev, iclass 40, count 2 2006.176.08:19:02.38#ibcon#first serial, iclass 40, count 2 2006.176.08:19:02.38#ibcon#enter sib2, iclass 40, count 2 2006.176.08:19:02.38#ibcon#flushed, iclass 40, count 2 2006.176.08:19:02.38#ibcon#about to write, iclass 40, count 2 2006.176.08:19:02.38#ibcon#wrote, iclass 40, count 2 2006.176.08:19:02.38#ibcon#about to read 3, iclass 40, count 2 2006.176.08:19:02.40#ibcon#read 3, iclass 40, count 2 2006.176.08:19:02.40#ibcon#about to read 4, iclass 40, count 2 2006.176.08:19:02.40#ibcon#read 4, iclass 40, count 2 2006.176.08:19:02.40#ibcon#about to read 5, iclass 40, count 2 2006.176.08:19:02.40#ibcon#read 5, iclass 40, count 2 2006.176.08:19:02.40#ibcon#about to read 6, iclass 40, count 2 2006.176.08:19:02.40#ibcon#read 6, iclass 40, count 2 2006.176.08:19:02.40#ibcon#end of sib2, iclass 40, count 2 2006.176.08:19:02.40#ibcon#*mode == 0, iclass 40, count 2 2006.176.08:19:02.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.176.08:19:02.40#ibcon#[27=AT06-04\r\n] 2006.176.08:19:02.40#ibcon#*before write, iclass 40, count 2 2006.176.08:19:02.40#ibcon#enter sib2, iclass 40, count 2 2006.176.08:19:02.40#ibcon#flushed, iclass 40, count 2 2006.176.08:19:02.40#ibcon#about to write, iclass 40, count 2 2006.176.08:19:02.40#ibcon#wrote, iclass 40, count 2 2006.176.08:19:02.40#ibcon#about to read 3, iclass 40, count 2 2006.176.08:19:02.43#ibcon#read 3, iclass 40, count 2 2006.176.08:19:02.43#ibcon#about to read 4, iclass 40, count 2 2006.176.08:19:02.43#ibcon#read 4, iclass 40, count 2 2006.176.08:19:02.43#ibcon#about to read 5, iclass 40, count 2 2006.176.08:19:02.43#ibcon#read 5, iclass 40, count 2 2006.176.08:19:02.43#ibcon#about to read 6, iclass 40, count 2 2006.176.08:19:02.43#ibcon#read 6, iclass 40, count 2 2006.176.08:19:02.43#ibcon#end of sib2, iclass 40, count 2 2006.176.08:19:02.43#ibcon#*after write, iclass 40, count 2 2006.176.08:19:02.43#ibcon#*before return 0, iclass 40, count 2 2006.176.08:19:02.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:19:02.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.176.08:19:02.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.176.08:19:02.43#ibcon#ireg 7 cls_cnt 0 2006.176.08:19:02.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:19:02.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:19:02.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:19:02.55#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:19:02.55#ibcon#first serial, iclass 40, count 0 2006.176.08:19:02.55#ibcon#enter sib2, iclass 40, count 0 2006.176.08:19:02.55#ibcon#flushed, iclass 40, count 0 2006.176.08:19:02.55#ibcon#about to write, iclass 40, count 0 2006.176.08:19:02.55#ibcon#wrote, iclass 40, count 0 2006.176.08:19:02.55#ibcon#about to read 3, iclass 40, count 0 2006.176.08:19:02.57#ibcon#read 3, iclass 40, count 0 2006.176.08:19:02.57#ibcon#about to read 4, iclass 40, count 0 2006.176.08:19:02.57#ibcon#read 4, iclass 40, count 0 2006.176.08:19:02.57#ibcon#about to read 5, iclass 40, count 0 2006.176.08:19:02.57#ibcon#read 5, iclass 40, count 0 2006.176.08:19:02.57#ibcon#about to read 6, iclass 40, count 0 2006.176.08:19:02.57#ibcon#read 6, iclass 40, count 0 2006.176.08:19:02.57#ibcon#end of sib2, iclass 40, count 0 2006.176.08:19:02.57#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:19:02.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:19:02.57#ibcon#[27=USB\r\n] 2006.176.08:19:02.57#ibcon#*before write, iclass 40, count 0 2006.176.08:19:02.57#ibcon#enter sib2, iclass 40, count 0 2006.176.08:19:02.57#ibcon#flushed, iclass 40, count 0 2006.176.08:19:02.57#ibcon#about to write, iclass 40, count 0 2006.176.08:19:02.57#ibcon#wrote, iclass 40, count 0 2006.176.08:19:02.57#ibcon#about to read 3, iclass 40, count 0 2006.176.08:19:02.60#ibcon#read 3, iclass 40, count 0 2006.176.08:19:02.60#ibcon#about to read 4, iclass 40, count 0 2006.176.08:19:02.60#ibcon#read 4, iclass 40, count 0 2006.176.08:19:02.60#ibcon#about to read 5, iclass 40, count 0 2006.176.08:19:02.60#ibcon#read 5, iclass 40, count 0 2006.176.08:19:02.60#ibcon#about to read 6, iclass 40, count 0 2006.176.08:19:02.60#ibcon#read 6, iclass 40, count 0 2006.176.08:19:02.60#ibcon#end of sib2, iclass 40, count 0 2006.176.08:19:02.60#ibcon#*after write, iclass 40, count 0 2006.176.08:19:02.60#ibcon#*before return 0, iclass 40, count 0 2006.176.08:19:02.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:19:02.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.176.08:19:02.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:19:02.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:19:02.60$vc4f8/vabw=wide 2006.176.08:19:02.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.176.08:19:02.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.176.08:19:02.60#ibcon#ireg 8 cls_cnt 0 2006.176.08:19:02.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:19:02.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:19:02.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:19:02.60#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:19:02.60#ibcon#first serial, iclass 4, count 0 2006.176.08:19:02.60#ibcon#enter sib2, iclass 4, count 0 2006.176.08:19:02.60#ibcon#flushed, iclass 4, count 0 2006.176.08:19:02.60#ibcon#about to write, iclass 4, count 0 2006.176.08:19:02.60#ibcon#wrote, iclass 4, count 0 2006.176.08:19:02.60#ibcon#about to read 3, iclass 4, count 0 2006.176.08:19:02.62#ibcon#read 3, iclass 4, count 0 2006.176.08:19:02.62#ibcon#about to read 4, iclass 4, count 0 2006.176.08:19:02.62#ibcon#read 4, iclass 4, count 0 2006.176.08:19:02.62#ibcon#about to read 5, iclass 4, count 0 2006.176.08:19:02.62#ibcon#read 5, iclass 4, count 0 2006.176.08:19:02.62#ibcon#about to read 6, iclass 4, count 0 2006.176.08:19:02.62#ibcon#read 6, iclass 4, count 0 2006.176.08:19:02.62#ibcon#end of sib2, iclass 4, count 0 2006.176.08:19:02.62#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:19:02.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:19:02.62#ibcon#[25=BW32\r\n] 2006.176.08:19:02.62#ibcon#*before write, iclass 4, count 0 2006.176.08:19:02.62#ibcon#enter sib2, iclass 4, count 0 2006.176.08:19:02.62#ibcon#flushed, iclass 4, count 0 2006.176.08:19:02.62#ibcon#about to write, iclass 4, count 0 2006.176.08:19:02.62#ibcon#wrote, iclass 4, count 0 2006.176.08:19:02.62#ibcon#about to read 3, iclass 4, count 0 2006.176.08:19:02.65#ibcon#read 3, iclass 4, count 0 2006.176.08:19:02.65#ibcon#about to read 4, iclass 4, count 0 2006.176.08:19:02.65#ibcon#read 4, iclass 4, count 0 2006.176.08:19:02.65#ibcon#about to read 5, iclass 4, count 0 2006.176.08:19:02.65#ibcon#read 5, iclass 4, count 0 2006.176.08:19:02.65#ibcon#about to read 6, iclass 4, count 0 2006.176.08:19:02.65#ibcon#read 6, iclass 4, count 0 2006.176.08:19:02.65#ibcon#end of sib2, iclass 4, count 0 2006.176.08:19:02.65#ibcon#*after write, iclass 4, count 0 2006.176.08:19:02.65#ibcon#*before return 0, iclass 4, count 0 2006.176.08:19:02.65#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:19:02.65#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.176.08:19:02.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:19:02.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:19:02.65$vc4f8/vbbw=wide 2006.176.08:19:02.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.08:19:02.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.08:19:02.65#ibcon#ireg 8 cls_cnt 0 2006.176.08:19:02.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:19:02.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:19:02.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:19:02.72#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:19:02.72#ibcon#first serial, iclass 6, count 0 2006.176.08:19:02.72#ibcon#enter sib2, iclass 6, count 0 2006.176.08:19:02.72#ibcon#flushed, iclass 6, count 0 2006.176.08:19:02.72#ibcon#about to write, iclass 6, count 0 2006.176.08:19:02.72#ibcon#wrote, iclass 6, count 0 2006.176.08:19:02.72#ibcon#about to read 3, iclass 6, count 0 2006.176.08:19:02.74#ibcon#read 3, iclass 6, count 0 2006.176.08:19:02.74#ibcon#about to read 4, iclass 6, count 0 2006.176.08:19:02.74#ibcon#read 4, iclass 6, count 0 2006.176.08:19:02.74#ibcon#about to read 5, iclass 6, count 0 2006.176.08:19:02.74#ibcon#read 5, iclass 6, count 0 2006.176.08:19:02.74#ibcon#about to read 6, iclass 6, count 0 2006.176.08:19:02.74#ibcon#read 6, iclass 6, count 0 2006.176.08:19:02.74#ibcon#end of sib2, iclass 6, count 0 2006.176.08:19:02.74#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:19:02.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:19:02.74#ibcon#[27=BW32\r\n] 2006.176.08:19:02.74#ibcon#*before write, iclass 6, count 0 2006.176.08:19:02.74#ibcon#enter sib2, iclass 6, count 0 2006.176.08:19:02.74#ibcon#flushed, iclass 6, count 0 2006.176.08:19:02.74#ibcon#about to write, iclass 6, count 0 2006.176.08:19:02.74#ibcon#wrote, iclass 6, count 0 2006.176.08:19:02.74#ibcon#about to read 3, iclass 6, count 0 2006.176.08:19:02.77#ibcon#read 3, iclass 6, count 0 2006.176.08:19:02.77#ibcon#about to read 4, iclass 6, count 0 2006.176.08:19:02.77#ibcon#read 4, iclass 6, count 0 2006.176.08:19:02.77#ibcon#about to read 5, iclass 6, count 0 2006.176.08:19:02.77#ibcon#read 5, iclass 6, count 0 2006.176.08:19:02.77#ibcon#about to read 6, iclass 6, count 0 2006.176.08:19:02.77#ibcon#read 6, iclass 6, count 0 2006.176.08:19:02.77#ibcon#end of sib2, iclass 6, count 0 2006.176.08:19:02.77#ibcon#*after write, iclass 6, count 0 2006.176.08:19:02.77#ibcon#*before return 0, iclass 6, count 0 2006.176.08:19:02.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:19:02.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:19:02.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:19:02.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:19:02.77$4f8m12a/ifd4f 2006.176.08:19:02.77$ifd4f/lo= 2006.176.08:19:02.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:19:02.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:19:02.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:19:02.77$ifd4f/patch= 2006.176.08:19:02.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:19:02.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:19:02.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:19:02.77$4f8m12a/"form=m,16.000,1:2 2006.176.08:19:02.77$4f8m12a/"tpicd 2006.176.08:19:02.77$4f8m12a/echo=off 2006.176.08:19:02.77$4f8m12a/xlog=off 2006.176.08:19:02.77:!2006.176.08:20:40 2006.176.08:19:10.14#trakl#Source acquired 2006.176.08:19:12.14#flagr#flagr/antenna,acquired 2006.176.08:20:40.00:preob 2006.176.08:20:40.14/onsource/TRACKING 2006.176.08:20:40.14:!2006.176.08:20:50 2006.176.08:20:50.00:data_valid=on 2006.176.08:20:50.00:midob 2006.176.08:20:51.14/onsource/TRACKING 2006.176.08:20:51.14/wx/23.79,1008.5,93 2006.176.08:20:51.24/cable/+6.4930E-03 2006.176.08:20:52.33/va/01,08,usb,yes,29,30 2006.176.08:20:52.33/va/02,07,usb,yes,29,30 2006.176.08:20:52.33/va/03,06,usb,yes,30,30 2006.176.08:20:52.33/va/04,07,usb,yes,29,32 2006.176.08:20:52.33/va/05,07,usb,yes,31,33 2006.176.08:20:52.33/va/06,06,usb,yes,30,30 2006.176.08:20:52.33/va/07,06,usb,yes,30,30 2006.176.08:20:52.33/va/08,06,usb,yes,33,32 2006.176.08:20:52.56/valo/01,532.99,yes,locked 2006.176.08:20:52.56/valo/02,572.99,yes,locked 2006.176.08:20:52.56/valo/03,672.99,yes,locked 2006.176.08:20:52.56/valo/04,832.99,yes,locked 2006.176.08:20:52.56/valo/05,652.99,yes,locked 2006.176.08:20:52.56/valo/06,772.99,yes,locked 2006.176.08:20:52.56/valo/07,832.99,yes,locked 2006.176.08:20:52.56/valo/08,852.99,yes,locked 2006.176.08:20:53.65/vb/01,04,usb,yes,29,27 2006.176.08:20:53.65/vb/02,04,usb,yes,31,32 2006.176.08:20:53.65/vb/03,04,usb,yes,27,31 2006.176.08:20:53.65/vb/04,04,usb,yes,28,28 2006.176.08:20:53.65/vb/05,04,usb,yes,26,30 2006.176.08:20:53.65/vb/06,04,usb,yes,27,30 2006.176.08:20:53.65/vb/07,04,usb,yes,29,29 2006.176.08:20:53.65/vb/08,04,usb,yes,27,30 2006.176.08:20:53.89/vblo/01,632.99,yes,locked 2006.176.08:20:53.89/vblo/02,640.99,yes,locked 2006.176.08:20:53.89/vblo/03,656.99,yes,locked 2006.176.08:20:53.89/vblo/04,712.99,yes,locked 2006.176.08:20:53.89/vblo/05,744.99,yes,locked 2006.176.08:20:53.89/vblo/06,752.99,yes,locked 2006.176.08:20:53.89/vblo/07,734.99,yes,locked 2006.176.08:20:53.89/vblo/08,744.99,yes,locked 2006.176.08:20:54.04/vabw/8 2006.176.08:20:54.19/vbbw/8 2006.176.08:20:54.28/xfe/off,on,15.0 2006.176.08:20:54.66/ifatt/23,28,28,28 2006.176.08:20:55.07/fmout-gps/S +3.70E-07 2006.176.08:20:55.14:!2006.176.08:22:00 2006.176.08:22:00.00:data_valid=off 2006.176.08:22:00.00:postob 2006.176.08:22:00.18/cable/+6.4938E-03 2006.176.08:22:00.18/wx/23.78,1008.5,93 2006.176.08:22:01.08/fmout-gps/S +3.69E-07 2006.176.08:22:01.08:scan_name=176-0824,k06176,60 2006.176.08:22:01.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.176.08:22:02.14#flagr#flagr/antenna,new-source 2006.176.08:22:02.14:checkk5 2006.176.08:22:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:22:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:22:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:22:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:22:04.02/chk_obsdata//k5ts1/T1760820??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.176.08:22:04.39/chk_obsdata//k5ts2/T1760820??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.176.08:22:04.76/chk_obsdata//k5ts3/T1760820??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.176.08:22:05.13/chk_obsdata//k5ts4/T1760820??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.176.08:22:05.82/k5log//k5ts1_log_newline 2006.176.08:22:06.51/k5log//k5ts2_log_newline 2006.176.08:22:07.19/k5log//k5ts3_log_newline 2006.176.08:22:07.88/k5log//k5ts4_log_newline 2006.176.08:22:07.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:22:07.91:4f8m12a=3 2006.176.08:22:07.91$4f8m12a/echo=on 2006.176.08:22:07.91$4f8m12a/pcalon 2006.176.08:22:07.91$pcalon/"no phase cal control is implemented here 2006.176.08:22:07.91$4f8m12a/"tpicd=stop 2006.176.08:22:07.91$4f8m12a/vc4f8 2006.176.08:22:07.91$vc4f8/valo=1,532.99 2006.176.08:22:07.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.08:22:07.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.08:22:07.91#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:07.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:07.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:07.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:07.91#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:22:07.91#ibcon#first serial, iclass 11, count 0 2006.176.08:22:07.91#ibcon#enter sib2, iclass 11, count 0 2006.176.08:22:07.91#ibcon#flushed, iclass 11, count 0 2006.176.08:22:07.91#ibcon#about to write, iclass 11, count 0 2006.176.08:22:07.91#ibcon#wrote, iclass 11, count 0 2006.176.08:22:07.91#ibcon#about to read 3, iclass 11, count 0 2006.176.08:22:07.95#ibcon#read 3, iclass 11, count 0 2006.176.08:22:07.95#ibcon#about to read 4, iclass 11, count 0 2006.176.08:22:07.95#ibcon#read 4, iclass 11, count 0 2006.176.08:22:07.95#ibcon#about to read 5, iclass 11, count 0 2006.176.08:22:07.95#ibcon#read 5, iclass 11, count 0 2006.176.08:22:07.95#ibcon#about to read 6, iclass 11, count 0 2006.176.08:22:07.95#ibcon#read 6, iclass 11, count 0 2006.176.08:22:07.95#ibcon#end of sib2, iclass 11, count 0 2006.176.08:22:07.95#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:22:07.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:22:07.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:22:07.96#ibcon#*before write, iclass 11, count 0 2006.176.08:22:07.96#ibcon#enter sib2, iclass 11, count 0 2006.176.08:22:07.96#ibcon#flushed, iclass 11, count 0 2006.176.08:22:07.96#ibcon#about to write, iclass 11, count 0 2006.176.08:22:07.96#ibcon#wrote, iclass 11, count 0 2006.176.08:22:07.96#ibcon#about to read 3, iclass 11, count 0 2006.176.08:22:08.00#ibcon#read 3, iclass 11, count 0 2006.176.08:22:08.00#ibcon#about to read 4, iclass 11, count 0 2006.176.08:22:08.00#ibcon#read 4, iclass 11, count 0 2006.176.08:22:08.00#ibcon#about to read 5, iclass 11, count 0 2006.176.08:22:08.00#ibcon#read 5, iclass 11, count 0 2006.176.08:22:08.00#ibcon#about to read 6, iclass 11, count 0 2006.176.08:22:08.00#ibcon#read 6, iclass 11, count 0 2006.176.08:22:08.00#ibcon#end of sib2, iclass 11, count 0 2006.176.08:22:08.00#ibcon#*after write, iclass 11, count 0 2006.176.08:22:08.00#ibcon#*before return 0, iclass 11, count 0 2006.176.08:22:08.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:08.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:08.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:22:08.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:22:08.00$vc4f8/va=1,8 2006.176.08:22:08.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.08:22:08.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.08:22:08.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:08.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:08.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:08.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:08.00#ibcon#enter wrdev, iclass 13, count 2 2006.176.08:22:08.00#ibcon#first serial, iclass 13, count 2 2006.176.08:22:08.00#ibcon#enter sib2, iclass 13, count 2 2006.176.08:22:08.00#ibcon#flushed, iclass 13, count 2 2006.176.08:22:08.00#ibcon#about to write, iclass 13, count 2 2006.176.08:22:08.00#ibcon#wrote, iclass 13, count 2 2006.176.08:22:08.00#ibcon#about to read 3, iclass 13, count 2 2006.176.08:22:08.02#ibcon#read 3, iclass 13, count 2 2006.176.08:22:08.02#ibcon#about to read 4, iclass 13, count 2 2006.176.08:22:08.02#ibcon#read 4, iclass 13, count 2 2006.176.08:22:08.02#ibcon#about to read 5, iclass 13, count 2 2006.176.08:22:08.02#ibcon#read 5, iclass 13, count 2 2006.176.08:22:08.02#ibcon#about to read 6, iclass 13, count 2 2006.176.08:22:08.02#ibcon#read 6, iclass 13, count 2 2006.176.08:22:08.02#ibcon#end of sib2, iclass 13, count 2 2006.176.08:22:08.02#ibcon#*mode == 0, iclass 13, count 2 2006.176.08:22:08.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.08:22:08.02#ibcon#[25=AT01-08\r\n] 2006.176.08:22:08.02#ibcon#*before write, iclass 13, count 2 2006.176.08:22:08.02#ibcon#enter sib2, iclass 13, count 2 2006.176.08:22:08.02#ibcon#flushed, iclass 13, count 2 2006.176.08:22:08.02#ibcon#about to write, iclass 13, count 2 2006.176.08:22:08.02#ibcon#wrote, iclass 13, count 2 2006.176.08:22:08.02#ibcon#about to read 3, iclass 13, count 2 2006.176.08:22:08.05#ibcon#read 3, iclass 13, count 2 2006.176.08:22:08.05#ibcon#about to read 4, iclass 13, count 2 2006.176.08:22:08.05#ibcon#read 4, iclass 13, count 2 2006.176.08:22:08.05#ibcon#about to read 5, iclass 13, count 2 2006.176.08:22:08.05#ibcon#read 5, iclass 13, count 2 2006.176.08:22:08.05#ibcon#about to read 6, iclass 13, count 2 2006.176.08:22:08.05#ibcon#read 6, iclass 13, count 2 2006.176.08:22:08.05#ibcon#end of sib2, iclass 13, count 2 2006.176.08:22:08.05#ibcon#*after write, iclass 13, count 2 2006.176.08:22:08.05#ibcon#*before return 0, iclass 13, count 2 2006.176.08:22:08.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:08.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:08.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.08:22:08.05#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:08.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:08.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:08.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:08.17#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:22:08.17#ibcon#first serial, iclass 13, count 0 2006.176.08:22:08.17#ibcon#enter sib2, iclass 13, count 0 2006.176.08:22:08.17#ibcon#flushed, iclass 13, count 0 2006.176.08:22:08.17#ibcon#about to write, iclass 13, count 0 2006.176.08:22:08.17#ibcon#wrote, iclass 13, count 0 2006.176.08:22:08.17#ibcon#about to read 3, iclass 13, count 0 2006.176.08:22:08.19#ibcon#read 3, iclass 13, count 0 2006.176.08:22:08.19#ibcon#about to read 4, iclass 13, count 0 2006.176.08:22:08.19#ibcon#read 4, iclass 13, count 0 2006.176.08:22:08.19#ibcon#about to read 5, iclass 13, count 0 2006.176.08:22:08.19#ibcon#read 5, iclass 13, count 0 2006.176.08:22:08.19#ibcon#about to read 6, iclass 13, count 0 2006.176.08:22:08.19#ibcon#read 6, iclass 13, count 0 2006.176.08:22:08.19#ibcon#end of sib2, iclass 13, count 0 2006.176.08:22:08.19#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:22:08.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:22:08.19#ibcon#[25=USB\r\n] 2006.176.08:22:08.19#ibcon#*before write, iclass 13, count 0 2006.176.08:22:08.19#ibcon#enter sib2, iclass 13, count 0 2006.176.08:22:08.19#ibcon#flushed, iclass 13, count 0 2006.176.08:22:08.19#ibcon#about to write, iclass 13, count 0 2006.176.08:22:08.19#ibcon#wrote, iclass 13, count 0 2006.176.08:22:08.19#ibcon#about to read 3, iclass 13, count 0 2006.176.08:22:08.22#ibcon#read 3, iclass 13, count 0 2006.176.08:22:08.22#ibcon#about to read 4, iclass 13, count 0 2006.176.08:22:08.22#ibcon#read 4, iclass 13, count 0 2006.176.08:22:08.22#ibcon#about to read 5, iclass 13, count 0 2006.176.08:22:08.22#ibcon#read 5, iclass 13, count 0 2006.176.08:22:08.22#ibcon#about to read 6, iclass 13, count 0 2006.176.08:22:08.22#ibcon#read 6, iclass 13, count 0 2006.176.08:22:08.22#ibcon#end of sib2, iclass 13, count 0 2006.176.08:22:08.22#ibcon#*after write, iclass 13, count 0 2006.176.08:22:08.22#ibcon#*before return 0, iclass 13, count 0 2006.176.08:22:08.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:08.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:08.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:22:08.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:22:08.22$vc4f8/valo=2,572.99 2006.176.08:22:08.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.08:22:08.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.08:22:08.22#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:08.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:08.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:08.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:08.22#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:22:08.22#ibcon#first serial, iclass 15, count 0 2006.176.08:22:08.22#ibcon#enter sib2, iclass 15, count 0 2006.176.08:22:08.22#ibcon#flushed, iclass 15, count 0 2006.176.08:22:08.22#ibcon#about to write, iclass 15, count 0 2006.176.08:22:08.22#ibcon#wrote, iclass 15, count 0 2006.176.08:22:08.22#ibcon#about to read 3, iclass 15, count 0 2006.176.08:22:08.24#ibcon#read 3, iclass 15, count 0 2006.176.08:22:08.24#ibcon#about to read 4, iclass 15, count 0 2006.176.08:22:08.24#ibcon#read 4, iclass 15, count 0 2006.176.08:22:08.24#ibcon#about to read 5, iclass 15, count 0 2006.176.08:22:08.24#ibcon#read 5, iclass 15, count 0 2006.176.08:22:08.24#ibcon#about to read 6, iclass 15, count 0 2006.176.08:22:08.24#ibcon#read 6, iclass 15, count 0 2006.176.08:22:08.24#ibcon#end of sib2, iclass 15, count 0 2006.176.08:22:08.24#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:22:08.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:22:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:22:08.24#ibcon#*before write, iclass 15, count 0 2006.176.08:22:08.24#ibcon#enter sib2, iclass 15, count 0 2006.176.08:22:08.24#ibcon#flushed, iclass 15, count 0 2006.176.08:22:08.24#ibcon#about to write, iclass 15, count 0 2006.176.08:22:08.24#ibcon#wrote, iclass 15, count 0 2006.176.08:22:08.24#ibcon#about to read 3, iclass 15, count 0 2006.176.08:22:08.28#ibcon#read 3, iclass 15, count 0 2006.176.08:22:08.28#ibcon#about to read 4, iclass 15, count 0 2006.176.08:22:08.28#ibcon#read 4, iclass 15, count 0 2006.176.08:22:08.28#ibcon#about to read 5, iclass 15, count 0 2006.176.08:22:08.28#ibcon#read 5, iclass 15, count 0 2006.176.08:22:08.28#ibcon#about to read 6, iclass 15, count 0 2006.176.08:22:08.28#ibcon#read 6, iclass 15, count 0 2006.176.08:22:08.28#ibcon#end of sib2, iclass 15, count 0 2006.176.08:22:08.28#ibcon#*after write, iclass 15, count 0 2006.176.08:22:08.28#ibcon#*before return 0, iclass 15, count 0 2006.176.08:22:08.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:08.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:08.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:22:08.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:22:08.28$vc4f8/va=2,7 2006.176.08:22:08.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.176.08:22:08.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.176.08:22:08.28#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:08.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:08.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:08.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:08.34#ibcon#enter wrdev, iclass 17, count 2 2006.176.08:22:08.34#ibcon#first serial, iclass 17, count 2 2006.176.08:22:08.34#ibcon#enter sib2, iclass 17, count 2 2006.176.08:22:08.34#ibcon#flushed, iclass 17, count 2 2006.176.08:22:08.34#ibcon#about to write, iclass 17, count 2 2006.176.08:22:08.34#ibcon#wrote, iclass 17, count 2 2006.176.08:22:08.34#ibcon#about to read 3, iclass 17, count 2 2006.176.08:22:08.36#ibcon#read 3, iclass 17, count 2 2006.176.08:22:08.36#ibcon#about to read 4, iclass 17, count 2 2006.176.08:22:08.36#ibcon#read 4, iclass 17, count 2 2006.176.08:22:08.36#ibcon#about to read 5, iclass 17, count 2 2006.176.08:22:08.36#ibcon#read 5, iclass 17, count 2 2006.176.08:22:08.36#ibcon#about to read 6, iclass 17, count 2 2006.176.08:22:08.36#ibcon#read 6, iclass 17, count 2 2006.176.08:22:08.36#ibcon#end of sib2, iclass 17, count 2 2006.176.08:22:08.36#ibcon#*mode == 0, iclass 17, count 2 2006.176.08:22:08.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.176.08:22:08.36#ibcon#[25=AT02-07\r\n] 2006.176.08:22:08.36#ibcon#*before write, iclass 17, count 2 2006.176.08:22:08.36#ibcon#enter sib2, iclass 17, count 2 2006.176.08:22:08.36#ibcon#flushed, iclass 17, count 2 2006.176.08:22:08.36#ibcon#about to write, iclass 17, count 2 2006.176.08:22:08.36#ibcon#wrote, iclass 17, count 2 2006.176.08:22:08.36#ibcon#about to read 3, iclass 17, count 2 2006.176.08:22:08.39#ibcon#read 3, iclass 17, count 2 2006.176.08:22:08.39#ibcon#about to read 4, iclass 17, count 2 2006.176.08:22:08.39#ibcon#read 4, iclass 17, count 2 2006.176.08:22:08.39#ibcon#about to read 5, iclass 17, count 2 2006.176.08:22:08.39#ibcon#read 5, iclass 17, count 2 2006.176.08:22:08.39#ibcon#about to read 6, iclass 17, count 2 2006.176.08:22:08.39#ibcon#read 6, iclass 17, count 2 2006.176.08:22:08.39#ibcon#end of sib2, iclass 17, count 2 2006.176.08:22:08.39#ibcon#*after write, iclass 17, count 2 2006.176.08:22:08.39#ibcon#*before return 0, iclass 17, count 2 2006.176.08:22:08.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:08.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:08.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.176.08:22:08.39#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:08.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:08.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:08.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:08.51#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:22:08.51#ibcon#first serial, iclass 17, count 0 2006.176.08:22:08.51#ibcon#enter sib2, iclass 17, count 0 2006.176.08:22:08.51#ibcon#flushed, iclass 17, count 0 2006.176.08:22:08.51#ibcon#about to write, iclass 17, count 0 2006.176.08:22:08.51#ibcon#wrote, iclass 17, count 0 2006.176.08:22:08.51#ibcon#about to read 3, iclass 17, count 0 2006.176.08:22:08.53#ibcon#read 3, iclass 17, count 0 2006.176.08:22:08.53#ibcon#about to read 4, iclass 17, count 0 2006.176.08:22:08.53#ibcon#read 4, iclass 17, count 0 2006.176.08:22:08.53#ibcon#about to read 5, iclass 17, count 0 2006.176.08:22:08.53#ibcon#read 5, iclass 17, count 0 2006.176.08:22:08.53#ibcon#about to read 6, iclass 17, count 0 2006.176.08:22:08.53#ibcon#read 6, iclass 17, count 0 2006.176.08:22:08.53#ibcon#end of sib2, iclass 17, count 0 2006.176.08:22:08.53#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:22:08.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:22:08.53#ibcon#[25=USB\r\n] 2006.176.08:22:08.53#ibcon#*before write, iclass 17, count 0 2006.176.08:22:08.53#ibcon#enter sib2, iclass 17, count 0 2006.176.08:22:08.53#ibcon#flushed, iclass 17, count 0 2006.176.08:22:08.53#ibcon#about to write, iclass 17, count 0 2006.176.08:22:08.53#ibcon#wrote, iclass 17, count 0 2006.176.08:22:08.53#ibcon#about to read 3, iclass 17, count 0 2006.176.08:22:08.56#ibcon#read 3, iclass 17, count 0 2006.176.08:22:08.56#ibcon#about to read 4, iclass 17, count 0 2006.176.08:22:08.56#ibcon#read 4, iclass 17, count 0 2006.176.08:22:08.56#ibcon#about to read 5, iclass 17, count 0 2006.176.08:22:08.56#ibcon#read 5, iclass 17, count 0 2006.176.08:22:08.56#ibcon#about to read 6, iclass 17, count 0 2006.176.08:22:08.56#ibcon#read 6, iclass 17, count 0 2006.176.08:22:08.56#ibcon#end of sib2, iclass 17, count 0 2006.176.08:22:08.56#ibcon#*after write, iclass 17, count 0 2006.176.08:22:08.56#ibcon#*before return 0, iclass 17, count 0 2006.176.08:22:08.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:08.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:08.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:22:08.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:22:08.56$vc4f8/valo=3,672.99 2006.176.08:22:08.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.176.08:22:08.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.176.08:22:08.56#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:08.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:08.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:08.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:08.56#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:22:08.56#ibcon#first serial, iclass 19, count 0 2006.176.08:22:08.56#ibcon#enter sib2, iclass 19, count 0 2006.176.08:22:08.56#ibcon#flushed, iclass 19, count 0 2006.176.08:22:08.56#ibcon#about to write, iclass 19, count 0 2006.176.08:22:08.56#ibcon#wrote, iclass 19, count 0 2006.176.08:22:08.56#ibcon#about to read 3, iclass 19, count 0 2006.176.08:22:08.58#ibcon#read 3, iclass 19, count 0 2006.176.08:22:08.58#ibcon#about to read 4, iclass 19, count 0 2006.176.08:22:08.58#ibcon#read 4, iclass 19, count 0 2006.176.08:22:08.58#ibcon#about to read 5, iclass 19, count 0 2006.176.08:22:08.58#ibcon#read 5, iclass 19, count 0 2006.176.08:22:08.58#ibcon#about to read 6, iclass 19, count 0 2006.176.08:22:08.58#ibcon#read 6, iclass 19, count 0 2006.176.08:22:08.58#ibcon#end of sib2, iclass 19, count 0 2006.176.08:22:08.58#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:22:08.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:22:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:22:08.58#ibcon#*before write, iclass 19, count 0 2006.176.08:22:08.58#ibcon#enter sib2, iclass 19, count 0 2006.176.08:22:08.58#ibcon#flushed, iclass 19, count 0 2006.176.08:22:08.58#ibcon#about to write, iclass 19, count 0 2006.176.08:22:08.58#ibcon#wrote, iclass 19, count 0 2006.176.08:22:08.58#ibcon#about to read 3, iclass 19, count 0 2006.176.08:22:08.62#ibcon#read 3, iclass 19, count 0 2006.176.08:22:08.62#ibcon#about to read 4, iclass 19, count 0 2006.176.08:22:08.62#ibcon#read 4, iclass 19, count 0 2006.176.08:22:08.62#ibcon#about to read 5, iclass 19, count 0 2006.176.08:22:08.62#ibcon#read 5, iclass 19, count 0 2006.176.08:22:08.62#ibcon#about to read 6, iclass 19, count 0 2006.176.08:22:08.62#ibcon#read 6, iclass 19, count 0 2006.176.08:22:08.62#ibcon#end of sib2, iclass 19, count 0 2006.176.08:22:08.62#ibcon#*after write, iclass 19, count 0 2006.176.08:22:08.62#ibcon#*before return 0, iclass 19, count 0 2006.176.08:22:08.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:08.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:08.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:22:08.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:22:08.62$vc4f8/va=3,6 2006.176.08:22:08.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.176.08:22:08.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.176.08:22:08.62#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:08.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:08.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:08.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:08.68#ibcon#enter wrdev, iclass 21, count 2 2006.176.08:22:08.68#ibcon#first serial, iclass 21, count 2 2006.176.08:22:08.68#ibcon#enter sib2, iclass 21, count 2 2006.176.08:22:08.68#ibcon#flushed, iclass 21, count 2 2006.176.08:22:08.68#ibcon#about to write, iclass 21, count 2 2006.176.08:22:08.68#ibcon#wrote, iclass 21, count 2 2006.176.08:22:08.68#ibcon#about to read 3, iclass 21, count 2 2006.176.08:22:08.70#ibcon#read 3, iclass 21, count 2 2006.176.08:22:08.70#ibcon#about to read 4, iclass 21, count 2 2006.176.08:22:08.70#ibcon#read 4, iclass 21, count 2 2006.176.08:22:08.70#ibcon#about to read 5, iclass 21, count 2 2006.176.08:22:08.70#ibcon#read 5, iclass 21, count 2 2006.176.08:22:08.70#ibcon#about to read 6, iclass 21, count 2 2006.176.08:22:08.70#ibcon#read 6, iclass 21, count 2 2006.176.08:22:08.70#ibcon#end of sib2, iclass 21, count 2 2006.176.08:22:08.70#ibcon#*mode == 0, iclass 21, count 2 2006.176.08:22:08.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.176.08:22:08.70#ibcon#[25=AT03-06\r\n] 2006.176.08:22:08.70#ibcon#*before write, iclass 21, count 2 2006.176.08:22:08.70#ibcon#enter sib2, iclass 21, count 2 2006.176.08:22:08.70#ibcon#flushed, iclass 21, count 2 2006.176.08:22:08.70#ibcon#about to write, iclass 21, count 2 2006.176.08:22:08.70#ibcon#wrote, iclass 21, count 2 2006.176.08:22:08.70#ibcon#about to read 3, iclass 21, count 2 2006.176.08:22:08.73#ibcon#read 3, iclass 21, count 2 2006.176.08:22:08.73#ibcon#about to read 4, iclass 21, count 2 2006.176.08:22:08.73#ibcon#read 4, iclass 21, count 2 2006.176.08:22:08.73#ibcon#about to read 5, iclass 21, count 2 2006.176.08:22:08.73#ibcon#read 5, iclass 21, count 2 2006.176.08:22:08.73#ibcon#about to read 6, iclass 21, count 2 2006.176.08:22:08.73#ibcon#read 6, iclass 21, count 2 2006.176.08:22:08.73#ibcon#end of sib2, iclass 21, count 2 2006.176.08:22:08.73#ibcon#*after write, iclass 21, count 2 2006.176.08:22:08.73#ibcon#*before return 0, iclass 21, count 2 2006.176.08:22:08.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:08.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:08.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.176.08:22:08.73#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:08.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:08.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:08.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:08.85#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:22:08.85#ibcon#first serial, iclass 21, count 0 2006.176.08:22:08.85#ibcon#enter sib2, iclass 21, count 0 2006.176.08:22:08.85#ibcon#flushed, iclass 21, count 0 2006.176.08:22:08.85#ibcon#about to write, iclass 21, count 0 2006.176.08:22:08.85#ibcon#wrote, iclass 21, count 0 2006.176.08:22:08.85#ibcon#about to read 3, iclass 21, count 0 2006.176.08:22:08.87#ibcon#read 3, iclass 21, count 0 2006.176.08:22:08.87#ibcon#about to read 4, iclass 21, count 0 2006.176.08:22:08.87#ibcon#read 4, iclass 21, count 0 2006.176.08:22:08.87#ibcon#about to read 5, iclass 21, count 0 2006.176.08:22:08.87#ibcon#read 5, iclass 21, count 0 2006.176.08:22:08.87#ibcon#about to read 6, iclass 21, count 0 2006.176.08:22:08.87#ibcon#read 6, iclass 21, count 0 2006.176.08:22:08.87#ibcon#end of sib2, iclass 21, count 0 2006.176.08:22:08.87#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:22:08.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:22:08.87#ibcon#[25=USB\r\n] 2006.176.08:22:08.87#ibcon#*before write, iclass 21, count 0 2006.176.08:22:08.87#ibcon#enter sib2, iclass 21, count 0 2006.176.08:22:08.87#ibcon#flushed, iclass 21, count 0 2006.176.08:22:08.87#ibcon#about to write, iclass 21, count 0 2006.176.08:22:08.87#ibcon#wrote, iclass 21, count 0 2006.176.08:22:08.87#ibcon#about to read 3, iclass 21, count 0 2006.176.08:22:08.90#ibcon#read 3, iclass 21, count 0 2006.176.08:22:08.90#ibcon#about to read 4, iclass 21, count 0 2006.176.08:22:08.90#ibcon#read 4, iclass 21, count 0 2006.176.08:22:08.90#ibcon#about to read 5, iclass 21, count 0 2006.176.08:22:08.90#ibcon#read 5, iclass 21, count 0 2006.176.08:22:08.90#ibcon#about to read 6, iclass 21, count 0 2006.176.08:22:08.90#ibcon#read 6, iclass 21, count 0 2006.176.08:22:08.90#ibcon#end of sib2, iclass 21, count 0 2006.176.08:22:08.90#ibcon#*after write, iclass 21, count 0 2006.176.08:22:08.90#ibcon#*before return 0, iclass 21, count 0 2006.176.08:22:08.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:08.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:08.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:22:08.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:22:08.90$vc4f8/valo=4,832.99 2006.176.08:22:08.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.08:22:08.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.08:22:08.90#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:08.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:08.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:08.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:08.90#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:22:08.90#ibcon#first serial, iclass 23, count 0 2006.176.08:22:08.90#ibcon#enter sib2, iclass 23, count 0 2006.176.08:22:08.90#ibcon#flushed, iclass 23, count 0 2006.176.08:22:08.90#ibcon#about to write, iclass 23, count 0 2006.176.08:22:08.90#ibcon#wrote, iclass 23, count 0 2006.176.08:22:08.90#ibcon#about to read 3, iclass 23, count 0 2006.176.08:22:08.92#ibcon#read 3, iclass 23, count 0 2006.176.08:22:08.92#ibcon#about to read 4, iclass 23, count 0 2006.176.08:22:08.92#ibcon#read 4, iclass 23, count 0 2006.176.08:22:08.92#ibcon#about to read 5, iclass 23, count 0 2006.176.08:22:08.92#ibcon#read 5, iclass 23, count 0 2006.176.08:22:08.92#ibcon#about to read 6, iclass 23, count 0 2006.176.08:22:08.92#ibcon#read 6, iclass 23, count 0 2006.176.08:22:08.92#ibcon#end of sib2, iclass 23, count 0 2006.176.08:22:08.92#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:22:08.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:22:08.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:22:08.92#ibcon#*before write, iclass 23, count 0 2006.176.08:22:08.92#ibcon#enter sib2, iclass 23, count 0 2006.176.08:22:08.92#ibcon#flushed, iclass 23, count 0 2006.176.08:22:08.92#ibcon#about to write, iclass 23, count 0 2006.176.08:22:08.92#ibcon#wrote, iclass 23, count 0 2006.176.08:22:08.92#ibcon#about to read 3, iclass 23, count 0 2006.176.08:22:08.96#ibcon#read 3, iclass 23, count 0 2006.176.08:22:08.96#ibcon#about to read 4, iclass 23, count 0 2006.176.08:22:08.96#ibcon#read 4, iclass 23, count 0 2006.176.08:22:08.96#ibcon#about to read 5, iclass 23, count 0 2006.176.08:22:08.96#ibcon#read 5, iclass 23, count 0 2006.176.08:22:08.96#ibcon#about to read 6, iclass 23, count 0 2006.176.08:22:08.96#ibcon#read 6, iclass 23, count 0 2006.176.08:22:08.96#ibcon#end of sib2, iclass 23, count 0 2006.176.08:22:08.96#ibcon#*after write, iclass 23, count 0 2006.176.08:22:08.96#ibcon#*before return 0, iclass 23, count 0 2006.176.08:22:08.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:08.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:08.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:22:08.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:22:08.96$vc4f8/va=4,7 2006.176.08:22:08.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.176.08:22:08.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.176.08:22:08.96#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:08.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:09.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:09.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:09.02#ibcon#enter wrdev, iclass 25, count 2 2006.176.08:22:09.02#ibcon#first serial, iclass 25, count 2 2006.176.08:22:09.02#ibcon#enter sib2, iclass 25, count 2 2006.176.08:22:09.02#ibcon#flushed, iclass 25, count 2 2006.176.08:22:09.02#ibcon#about to write, iclass 25, count 2 2006.176.08:22:09.02#ibcon#wrote, iclass 25, count 2 2006.176.08:22:09.02#ibcon#about to read 3, iclass 25, count 2 2006.176.08:22:09.04#ibcon#read 3, iclass 25, count 2 2006.176.08:22:09.04#ibcon#about to read 4, iclass 25, count 2 2006.176.08:22:09.04#ibcon#read 4, iclass 25, count 2 2006.176.08:22:09.04#ibcon#about to read 5, iclass 25, count 2 2006.176.08:22:09.04#ibcon#read 5, iclass 25, count 2 2006.176.08:22:09.04#ibcon#about to read 6, iclass 25, count 2 2006.176.08:22:09.04#ibcon#read 6, iclass 25, count 2 2006.176.08:22:09.04#ibcon#end of sib2, iclass 25, count 2 2006.176.08:22:09.04#ibcon#*mode == 0, iclass 25, count 2 2006.176.08:22:09.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.176.08:22:09.04#ibcon#[25=AT04-07\r\n] 2006.176.08:22:09.04#ibcon#*before write, iclass 25, count 2 2006.176.08:22:09.04#ibcon#enter sib2, iclass 25, count 2 2006.176.08:22:09.04#ibcon#flushed, iclass 25, count 2 2006.176.08:22:09.04#ibcon#about to write, iclass 25, count 2 2006.176.08:22:09.04#ibcon#wrote, iclass 25, count 2 2006.176.08:22:09.04#ibcon#about to read 3, iclass 25, count 2 2006.176.08:22:09.07#ibcon#read 3, iclass 25, count 2 2006.176.08:22:09.07#ibcon#about to read 4, iclass 25, count 2 2006.176.08:22:09.07#ibcon#read 4, iclass 25, count 2 2006.176.08:22:09.07#ibcon#about to read 5, iclass 25, count 2 2006.176.08:22:09.07#ibcon#read 5, iclass 25, count 2 2006.176.08:22:09.07#ibcon#about to read 6, iclass 25, count 2 2006.176.08:22:09.07#ibcon#read 6, iclass 25, count 2 2006.176.08:22:09.07#ibcon#end of sib2, iclass 25, count 2 2006.176.08:22:09.07#ibcon#*after write, iclass 25, count 2 2006.176.08:22:09.07#ibcon#*before return 0, iclass 25, count 2 2006.176.08:22:09.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:09.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:09.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.176.08:22:09.07#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:09.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:09.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:09.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:09.19#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:22:09.19#ibcon#first serial, iclass 25, count 0 2006.176.08:22:09.19#ibcon#enter sib2, iclass 25, count 0 2006.176.08:22:09.19#ibcon#flushed, iclass 25, count 0 2006.176.08:22:09.19#ibcon#about to write, iclass 25, count 0 2006.176.08:22:09.19#ibcon#wrote, iclass 25, count 0 2006.176.08:22:09.19#ibcon#about to read 3, iclass 25, count 0 2006.176.08:22:09.21#ibcon#read 3, iclass 25, count 0 2006.176.08:22:09.21#ibcon#about to read 4, iclass 25, count 0 2006.176.08:22:09.21#ibcon#read 4, iclass 25, count 0 2006.176.08:22:09.21#ibcon#about to read 5, iclass 25, count 0 2006.176.08:22:09.21#ibcon#read 5, iclass 25, count 0 2006.176.08:22:09.21#ibcon#about to read 6, iclass 25, count 0 2006.176.08:22:09.21#ibcon#read 6, iclass 25, count 0 2006.176.08:22:09.21#ibcon#end of sib2, iclass 25, count 0 2006.176.08:22:09.21#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:22:09.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:22:09.21#ibcon#[25=USB\r\n] 2006.176.08:22:09.21#ibcon#*before write, iclass 25, count 0 2006.176.08:22:09.21#ibcon#enter sib2, iclass 25, count 0 2006.176.08:22:09.21#ibcon#flushed, iclass 25, count 0 2006.176.08:22:09.21#ibcon#about to write, iclass 25, count 0 2006.176.08:22:09.21#ibcon#wrote, iclass 25, count 0 2006.176.08:22:09.21#ibcon#about to read 3, iclass 25, count 0 2006.176.08:22:09.24#ibcon#read 3, iclass 25, count 0 2006.176.08:22:09.24#ibcon#about to read 4, iclass 25, count 0 2006.176.08:22:09.24#ibcon#read 4, iclass 25, count 0 2006.176.08:22:09.24#ibcon#about to read 5, iclass 25, count 0 2006.176.08:22:09.24#ibcon#read 5, iclass 25, count 0 2006.176.08:22:09.24#ibcon#about to read 6, iclass 25, count 0 2006.176.08:22:09.24#ibcon#read 6, iclass 25, count 0 2006.176.08:22:09.24#ibcon#end of sib2, iclass 25, count 0 2006.176.08:22:09.24#ibcon#*after write, iclass 25, count 0 2006.176.08:22:09.24#ibcon#*before return 0, iclass 25, count 0 2006.176.08:22:09.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:09.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:09.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:22:09.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:22:09.24$vc4f8/valo=5,652.99 2006.176.08:22:09.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.08:22:09.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.08:22:09.24#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:09.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:09.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:09.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:09.24#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:22:09.24#ibcon#first serial, iclass 27, count 0 2006.176.08:22:09.24#ibcon#enter sib2, iclass 27, count 0 2006.176.08:22:09.24#ibcon#flushed, iclass 27, count 0 2006.176.08:22:09.24#ibcon#about to write, iclass 27, count 0 2006.176.08:22:09.24#ibcon#wrote, iclass 27, count 0 2006.176.08:22:09.24#ibcon#about to read 3, iclass 27, count 0 2006.176.08:22:09.26#ibcon#read 3, iclass 27, count 0 2006.176.08:22:09.26#ibcon#about to read 4, iclass 27, count 0 2006.176.08:22:09.26#ibcon#read 4, iclass 27, count 0 2006.176.08:22:09.26#ibcon#about to read 5, iclass 27, count 0 2006.176.08:22:09.26#ibcon#read 5, iclass 27, count 0 2006.176.08:22:09.26#ibcon#about to read 6, iclass 27, count 0 2006.176.08:22:09.26#ibcon#read 6, iclass 27, count 0 2006.176.08:22:09.26#ibcon#end of sib2, iclass 27, count 0 2006.176.08:22:09.26#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:22:09.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:22:09.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:22:09.26#ibcon#*before write, iclass 27, count 0 2006.176.08:22:09.26#ibcon#enter sib2, iclass 27, count 0 2006.176.08:22:09.26#ibcon#flushed, iclass 27, count 0 2006.176.08:22:09.26#ibcon#about to write, iclass 27, count 0 2006.176.08:22:09.26#ibcon#wrote, iclass 27, count 0 2006.176.08:22:09.26#ibcon#about to read 3, iclass 27, count 0 2006.176.08:22:09.30#ibcon#read 3, iclass 27, count 0 2006.176.08:22:09.30#ibcon#about to read 4, iclass 27, count 0 2006.176.08:22:09.30#ibcon#read 4, iclass 27, count 0 2006.176.08:22:09.30#ibcon#about to read 5, iclass 27, count 0 2006.176.08:22:09.30#ibcon#read 5, iclass 27, count 0 2006.176.08:22:09.30#ibcon#about to read 6, iclass 27, count 0 2006.176.08:22:09.30#ibcon#read 6, iclass 27, count 0 2006.176.08:22:09.30#ibcon#end of sib2, iclass 27, count 0 2006.176.08:22:09.30#ibcon#*after write, iclass 27, count 0 2006.176.08:22:09.30#ibcon#*before return 0, iclass 27, count 0 2006.176.08:22:09.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:09.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:09.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:22:09.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:22:09.30$vc4f8/va=5,7 2006.176.08:22:09.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.08:22:09.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.08:22:09.30#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:09.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:09.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:09.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:09.36#ibcon#enter wrdev, iclass 29, count 2 2006.176.08:22:09.36#ibcon#first serial, iclass 29, count 2 2006.176.08:22:09.36#ibcon#enter sib2, iclass 29, count 2 2006.176.08:22:09.36#ibcon#flushed, iclass 29, count 2 2006.176.08:22:09.36#ibcon#about to write, iclass 29, count 2 2006.176.08:22:09.36#ibcon#wrote, iclass 29, count 2 2006.176.08:22:09.36#ibcon#about to read 3, iclass 29, count 2 2006.176.08:22:09.38#ibcon#read 3, iclass 29, count 2 2006.176.08:22:09.38#ibcon#about to read 4, iclass 29, count 2 2006.176.08:22:09.38#ibcon#read 4, iclass 29, count 2 2006.176.08:22:09.38#ibcon#about to read 5, iclass 29, count 2 2006.176.08:22:09.38#ibcon#read 5, iclass 29, count 2 2006.176.08:22:09.38#ibcon#about to read 6, iclass 29, count 2 2006.176.08:22:09.38#ibcon#read 6, iclass 29, count 2 2006.176.08:22:09.38#ibcon#end of sib2, iclass 29, count 2 2006.176.08:22:09.38#ibcon#*mode == 0, iclass 29, count 2 2006.176.08:22:09.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.08:22:09.38#ibcon#[25=AT05-07\r\n] 2006.176.08:22:09.38#ibcon#*before write, iclass 29, count 2 2006.176.08:22:09.38#ibcon#enter sib2, iclass 29, count 2 2006.176.08:22:09.38#ibcon#flushed, iclass 29, count 2 2006.176.08:22:09.38#ibcon#about to write, iclass 29, count 2 2006.176.08:22:09.38#ibcon#wrote, iclass 29, count 2 2006.176.08:22:09.38#ibcon#about to read 3, iclass 29, count 2 2006.176.08:22:09.41#ibcon#read 3, iclass 29, count 2 2006.176.08:22:09.41#ibcon#about to read 4, iclass 29, count 2 2006.176.08:22:09.41#ibcon#read 4, iclass 29, count 2 2006.176.08:22:09.41#ibcon#about to read 5, iclass 29, count 2 2006.176.08:22:09.41#ibcon#read 5, iclass 29, count 2 2006.176.08:22:09.41#ibcon#about to read 6, iclass 29, count 2 2006.176.08:22:09.41#ibcon#read 6, iclass 29, count 2 2006.176.08:22:09.41#ibcon#end of sib2, iclass 29, count 2 2006.176.08:22:09.41#ibcon#*after write, iclass 29, count 2 2006.176.08:22:09.41#ibcon#*before return 0, iclass 29, count 2 2006.176.08:22:09.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:09.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:09.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.08:22:09.41#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:09.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:09.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:09.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:09.53#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:22:09.53#ibcon#first serial, iclass 29, count 0 2006.176.08:22:09.53#ibcon#enter sib2, iclass 29, count 0 2006.176.08:22:09.53#ibcon#flushed, iclass 29, count 0 2006.176.08:22:09.53#ibcon#about to write, iclass 29, count 0 2006.176.08:22:09.53#ibcon#wrote, iclass 29, count 0 2006.176.08:22:09.53#ibcon#about to read 3, iclass 29, count 0 2006.176.08:22:09.55#ibcon#read 3, iclass 29, count 0 2006.176.08:22:09.55#ibcon#about to read 4, iclass 29, count 0 2006.176.08:22:09.55#ibcon#read 4, iclass 29, count 0 2006.176.08:22:09.55#ibcon#about to read 5, iclass 29, count 0 2006.176.08:22:09.55#ibcon#read 5, iclass 29, count 0 2006.176.08:22:09.55#ibcon#about to read 6, iclass 29, count 0 2006.176.08:22:09.55#ibcon#read 6, iclass 29, count 0 2006.176.08:22:09.55#ibcon#end of sib2, iclass 29, count 0 2006.176.08:22:09.55#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:22:09.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:22:09.55#ibcon#[25=USB\r\n] 2006.176.08:22:09.55#ibcon#*before write, iclass 29, count 0 2006.176.08:22:09.55#ibcon#enter sib2, iclass 29, count 0 2006.176.08:22:09.55#ibcon#flushed, iclass 29, count 0 2006.176.08:22:09.55#ibcon#about to write, iclass 29, count 0 2006.176.08:22:09.55#ibcon#wrote, iclass 29, count 0 2006.176.08:22:09.55#ibcon#about to read 3, iclass 29, count 0 2006.176.08:22:09.58#ibcon#read 3, iclass 29, count 0 2006.176.08:22:09.58#ibcon#about to read 4, iclass 29, count 0 2006.176.08:22:09.58#ibcon#read 4, iclass 29, count 0 2006.176.08:22:09.58#ibcon#about to read 5, iclass 29, count 0 2006.176.08:22:09.58#ibcon#read 5, iclass 29, count 0 2006.176.08:22:09.58#ibcon#about to read 6, iclass 29, count 0 2006.176.08:22:09.58#ibcon#read 6, iclass 29, count 0 2006.176.08:22:09.58#ibcon#end of sib2, iclass 29, count 0 2006.176.08:22:09.58#ibcon#*after write, iclass 29, count 0 2006.176.08:22:09.58#ibcon#*before return 0, iclass 29, count 0 2006.176.08:22:09.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:09.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:09.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:22:09.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:22:09.58$vc4f8/valo=6,772.99 2006.176.08:22:09.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.08:22:09.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.08:22:09.58#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:09.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:09.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:09.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:09.58#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:22:09.58#ibcon#first serial, iclass 31, count 0 2006.176.08:22:09.58#ibcon#enter sib2, iclass 31, count 0 2006.176.08:22:09.58#ibcon#flushed, iclass 31, count 0 2006.176.08:22:09.58#ibcon#about to write, iclass 31, count 0 2006.176.08:22:09.58#ibcon#wrote, iclass 31, count 0 2006.176.08:22:09.58#ibcon#about to read 3, iclass 31, count 0 2006.176.08:22:09.60#ibcon#read 3, iclass 31, count 0 2006.176.08:22:09.60#ibcon#about to read 4, iclass 31, count 0 2006.176.08:22:09.60#ibcon#read 4, iclass 31, count 0 2006.176.08:22:09.60#ibcon#about to read 5, iclass 31, count 0 2006.176.08:22:09.60#ibcon#read 5, iclass 31, count 0 2006.176.08:22:09.60#ibcon#about to read 6, iclass 31, count 0 2006.176.08:22:09.60#ibcon#read 6, iclass 31, count 0 2006.176.08:22:09.60#ibcon#end of sib2, iclass 31, count 0 2006.176.08:22:09.60#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:22:09.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:22:09.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:22:09.60#ibcon#*before write, iclass 31, count 0 2006.176.08:22:09.60#ibcon#enter sib2, iclass 31, count 0 2006.176.08:22:09.60#ibcon#flushed, iclass 31, count 0 2006.176.08:22:09.60#ibcon#about to write, iclass 31, count 0 2006.176.08:22:09.60#ibcon#wrote, iclass 31, count 0 2006.176.08:22:09.60#ibcon#about to read 3, iclass 31, count 0 2006.176.08:22:09.64#ibcon#read 3, iclass 31, count 0 2006.176.08:22:09.64#ibcon#about to read 4, iclass 31, count 0 2006.176.08:22:09.64#ibcon#read 4, iclass 31, count 0 2006.176.08:22:09.64#ibcon#about to read 5, iclass 31, count 0 2006.176.08:22:09.64#ibcon#read 5, iclass 31, count 0 2006.176.08:22:09.64#ibcon#about to read 6, iclass 31, count 0 2006.176.08:22:09.64#ibcon#read 6, iclass 31, count 0 2006.176.08:22:09.64#ibcon#end of sib2, iclass 31, count 0 2006.176.08:22:09.64#ibcon#*after write, iclass 31, count 0 2006.176.08:22:09.64#ibcon#*before return 0, iclass 31, count 0 2006.176.08:22:09.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:09.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:09.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:22:09.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:22:09.64$vc4f8/va=6,6 2006.176.08:22:09.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.176.08:22:09.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.176.08:22:09.64#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:09.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:22:09.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:22:09.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:22:09.70#ibcon#enter wrdev, iclass 33, count 2 2006.176.08:22:09.70#ibcon#first serial, iclass 33, count 2 2006.176.08:22:09.70#ibcon#enter sib2, iclass 33, count 2 2006.176.08:22:09.70#ibcon#flushed, iclass 33, count 2 2006.176.08:22:09.70#ibcon#about to write, iclass 33, count 2 2006.176.08:22:09.70#ibcon#wrote, iclass 33, count 2 2006.176.08:22:09.70#ibcon#about to read 3, iclass 33, count 2 2006.176.08:22:09.72#ibcon#read 3, iclass 33, count 2 2006.176.08:22:09.72#ibcon#about to read 4, iclass 33, count 2 2006.176.08:22:09.72#ibcon#read 4, iclass 33, count 2 2006.176.08:22:09.72#ibcon#about to read 5, iclass 33, count 2 2006.176.08:22:09.72#ibcon#read 5, iclass 33, count 2 2006.176.08:22:09.72#ibcon#about to read 6, iclass 33, count 2 2006.176.08:22:09.72#ibcon#read 6, iclass 33, count 2 2006.176.08:22:09.72#ibcon#end of sib2, iclass 33, count 2 2006.176.08:22:09.72#ibcon#*mode == 0, iclass 33, count 2 2006.176.08:22:09.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.176.08:22:09.72#ibcon#[25=AT06-06\r\n] 2006.176.08:22:09.72#ibcon#*before write, iclass 33, count 2 2006.176.08:22:09.72#ibcon#enter sib2, iclass 33, count 2 2006.176.08:22:09.72#ibcon#flushed, iclass 33, count 2 2006.176.08:22:09.72#ibcon#about to write, iclass 33, count 2 2006.176.08:22:09.72#ibcon#wrote, iclass 33, count 2 2006.176.08:22:09.72#ibcon#about to read 3, iclass 33, count 2 2006.176.08:22:09.75#ibcon#read 3, iclass 33, count 2 2006.176.08:22:09.75#ibcon#about to read 4, iclass 33, count 2 2006.176.08:22:09.75#ibcon#read 4, iclass 33, count 2 2006.176.08:22:09.75#ibcon#about to read 5, iclass 33, count 2 2006.176.08:22:09.75#ibcon#read 5, iclass 33, count 2 2006.176.08:22:09.75#ibcon#about to read 6, iclass 33, count 2 2006.176.08:22:09.75#ibcon#read 6, iclass 33, count 2 2006.176.08:22:09.75#ibcon#end of sib2, iclass 33, count 2 2006.176.08:22:09.75#ibcon#*after write, iclass 33, count 2 2006.176.08:22:09.75#ibcon#*before return 0, iclass 33, count 2 2006.176.08:22:09.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:22:09.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.176.08:22:09.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.176.08:22:09.75#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:09.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:22:09.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:22:09.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:22:09.87#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:22:09.87#ibcon#first serial, iclass 33, count 0 2006.176.08:22:09.87#ibcon#enter sib2, iclass 33, count 0 2006.176.08:22:09.87#ibcon#flushed, iclass 33, count 0 2006.176.08:22:09.87#ibcon#about to write, iclass 33, count 0 2006.176.08:22:09.87#ibcon#wrote, iclass 33, count 0 2006.176.08:22:09.87#ibcon#about to read 3, iclass 33, count 0 2006.176.08:22:09.89#ibcon#read 3, iclass 33, count 0 2006.176.08:22:09.89#ibcon#about to read 4, iclass 33, count 0 2006.176.08:22:09.89#ibcon#read 4, iclass 33, count 0 2006.176.08:22:09.89#ibcon#about to read 5, iclass 33, count 0 2006.176.08:22:09.89#ibcon#read 5, iclass 33, count 0 2006.176.08:22:09.89#ibcon#about to read 6, iclass 33, count 0 2006.176.08:22:09.89#ibcon#read 6, iclass 33, count 0 2006.176.08:22:09.89#ibcon#end of sib2, iclass 33, count 0 2006.176.08:22:09.89#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:22:09.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:22:09.89#ibcon#[25=USB\r\n] 2006.176.08:22:09.89#ibcon#*before write, iclass 33, count 0 2006.176.08:22:09.89#ibcon#enter sib2, iclass 33, count 0 2006.176.08:22:09.89#ibcon#flushed, iclass 33, count 0 2006.176.08:22:09.89#ibcon#about to write, iclass 33, count 0 2006.176.08:22:09.89#ibcon#wrote, iclass 33, count 0 2006.176.08:22:09.89#ibcon#about to read 3, iclass 33, count 0 2006.176.08:22:09.92#ibcon#read 3, iclass 33, count 0 2006.176.08:22:09.92#ibcon#about to read 4, iclass 33, count 0 2006.176.08:22:09.92#ibcon#read 4, iclass 33, count 0 2006.176.08:22:09.92#ibcon#about to read 5, iclass 33, count 0 2006.176.08:22:09.92#ibcon#read 5, iclass 33, count 0 2006.176.08:22:09.92#ibcon#about to read 6, iclass 33, count 0 2006.176.08:22:09.92#ibcon#read 6, iclass 33, count 0 2006.176.08:22:09.92#ibcon#end of sib2, iclass 33, count 0 2006.176.08:22:09.92#ibcon#*after write, iclass 33, count 0 2006.176.08:22:09.92#ibcon#*before return 0, iclass 33, count 0 2006.176.08:22:09.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:22:09.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.176.08:22:09.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:22:09.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:22:09.92$vc4f8/valo=7,832.99 2006.176.08:22:09.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.176.08:22:09.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.176.08:22:09.92#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:09.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:22:09.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:22:09.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:22:09.92#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:22:09.92#ibcon#first serial, iclass 35, count 0 2006.176.08:22:09.92#ibcon#enter sib2, iclass 35, count 0 2006.176.08:22:09.92#ibcon#flushed, iclass 35, count 0 2006.176.08:22:09.92#ibcon#about to write, iclass 35, count 0 2006.176.08:22:09.92#ibcon#wrote, iclass 35, count 0 2006.176.08:22:09.92#ibcon#about to read 3, iclass 35, count 0 2006.176.08:22:09.94#ibcon#read 3, iclass 35, count 0 2006.176.08:22:09.94#ibcon#about to read 4, iclass 35, count 0 2006.176.08:22:09.94#ibcon#read 4, iclass 35, count 0 2006.176.08:22:09.94#ibcon#about to read 5, iclass 35, count 0 2006.176.08:22:09.94#ibcon#read 5, iclass 35, count 0 2006.176.08:22:09.94#ibcon#about to read 6, iclass 35, count 0 2006.176.08:22:09.94#ibcon#read 6, iclass 35, count 0 2006.176.08:22:09.94#ibcon#end of sib2, iclass 35, count 0 2006.176.08:22:09.94#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:22:09.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:22:09.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:22:09.94#ibcon#*before write, iclass 35, count 0 2006.176.08:22:09.94#ibcon#enter sib2, iclass 35, count 0 2006.176.08:22:09.94#ibcon#flushed, iclass 35, count 0 2006.176.08:22:09.94#ibcon#about to write, iclass 35, count 0 2006.176.08:22:09.94#ibcon#wrote, iclass 35, count 0 2006.176.08:22:09.94#ibcon#about to read 3, iclass 35, count 0 2006.176.08:22:09.98#ibcon#read 3, iclass 35, count 0 2006.176.08:22:09.98#ibcon#about to read 4, iclass 35, count 0 2006.176.08:22:09.98#ibcon#read 4, iclass 35, count 0 2006.176.08:22:09.98#ibcon#about to read 5, iclass 35, count 0 2006.176.08:22:09.98#ibcon#read 5, iclass 35, count 0 2006.176.08:22:09.98#ibcon#about to read 6, iclass 35, count 0 2006.176.08:22:09.98#ibcon#read 6, iclass 35, count 0 2006.176.08:22:09.98#ibcon#end of sib2, iclass 35, count 0 2006.176.08:22:09.98#ibcon#*after write, iclass 35, count 0 2006.176.08:22:09.98#ibcon#*before return 0, iclass 35, count 0 2006.176.08:22:09.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:22:09.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.176.08:22:09.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:22:09.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:22:09.98$vc4f8/va=7,6 2006.176.08:22:09.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.176.08:22:09.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.176.08:22:09.98#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:09.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:22:10.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:22:10.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:22:10.04#ibcon#enter wrdev, iclass 37, count 2 2006.176.08:22:10.04#ibcon#first serial, iclass 37, count 2 2006.176.08:22:10.04#ibcon#enter sib2, iclass 37, count 2 2006.176.08:22:10.04#ibcon#flushed, iclass 37, count 2 2006.176.08:22:10.04#ibcon#about to write, iclass 37, count 2 2006.176.08:22:10.04#ibcon#wrote, iclass 37, count 2 2006.176.08:22:10.04#ibcon#about to read 3, iclass 37, count 2 2006.176.08:22:10.06#ibcon#read 3, iclass 37, count 2 2006.176.08:22:10.06#ibcon#about to read 4, iclass 37, count 2 2006.176.08:22:10.06#ibcon#read 4, iclass 37, count 2 2006.176.08:22:10.06#ibcon#about to read 5, iclass 37, count 2 2006.176.08:22:10.06#ibcon#read 5, iclass 37, count 2 2006.176.08:22:10.06#ibcon#about to read 6, iclass 37, count 2 2006.176.08:22:10.06#ibcon#read 6, iclass 37, count 2 2006.176.08:22:10.06#ibcon#end of sib2, iclass 37, count 2 2006.176.08:22:10.06#ibcon#*mode == 0, iclass 37, count 2 2006.176.08:22:10.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.176.08:22:10.06#ibcon#[25=AT07-06\r\n] 2006.176.08:22:10.06#ibcon#*before write, iclass 37, count 2 2006.176.08:22:10.06#ibcon#enter sib2, iclass 37, count 2 2006.176.08:22:10.06#ibcon#flushed, iclass 37, count 2 2006.176.08:22:10.06#ibcon#about to write, iclass 37, count 2 2006.176.08:22:10.06#ibcon#wrote, iclass 37, count 2 2006.176.08:22:10.06#ibcon#about to read 3, iclass 37, count 2 2006.176.08:22:10.09#ibcon#read 3, iclass 37, count 2 2006.176.08:22:10.09#ibcon#about to read 4, iclass 37, count 2 2006.176.08:22:10.09#ibcon#read 4, iclass 37, count 2 2006.176.08:22:10.09#ibcon#about to read 5, iclass 37, count 2 2006.176.08:22:10.09#ibcon#read 5, iclass 37, count 2 2006.176.08:22:10.09#ibcon#about to read 6, iclass 37, count 2 2006.176.08:22:10.09#ibcon#read 6, iclass 37, count 2 2006.176.08:22:10.09#ibcon#end of sib2, iclass 37, count 2 2006.176.08:22:10.09#ibcon#*after write, iclass 37, count 2 2006.176.08:22:10.09#ibcon#*before return 0, iclass 37, count 2 2006.176.08:22:10.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:22:10.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.176.08:22:10.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.176.08:22:10.09#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:10.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:22:10.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:22:10.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:22:10.21#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:22:10.21#ibcon#first serial, iclass 37, count 0 2006.176.08:22:10.21#ibcon#enter sib2, iclass 37, count 0 2006.176.08:22:10.21#ibcon#flushed, iclass 37, count 0 2006.176.08:22:10.21#ibcon#about to write, iclass 37, count 0 2006.176.08:22:10.21#ibcon#wrote, iclass 37, count 0 2006.176.08:22:10.21#ibcon#about to read 3, iclass 37, count 0 2006.176.08:22:10.23#ibcon#read 3, iclass 37, count 0 2006.176.08:22:10.23#ibcon#about to read 4, iclass 37, count 0 2006.176.08:22:10.23#ibcon#read 4, iclass 37, count 0 2006.176.08:22:10.23#ibcon#about to read 5, iclass 37, count 0 2006.176.08:22:10.23#ibcon#read 5, iclass 37, count 0 2006.176.08:22:10.23#ibcon#about to read 6, iclass 37, count 0 2006.176.08:22:10.23#ibcon#read 6, iclass 37, count 0 2006.176.08:22:10.23#ibcon#end of sib2, iclass 37, count 0 2006.176.08:22:10.23#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:22:10.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:22:10.23#ibcon#[25=USB\r\n] 2006.176.08:22:10.23#ibcon#*before write, iclass 37, count 0 2006.176.08:22:10.23#ibcon#enter sib2, iclass 37, count 0 2006.176.08:22:10.23#ibcon#flushed, iclass 37, count 0 2006.176.08:22:10.23#ibcon#about to write, iclass 37, count 0 2006.176.08:22:10.23#ibcon#wrote, iclass 37, count 0 2006.176.08:22:10.23#ibcon#about to read 3, iclass 37, count 0 2006.176.08:22:10.26#ibcon#read 3, iclass 37, count 0 2006.176.08:22:10.26#ibcon#about to read 4, iclass 37, count 0 2006.176.08:22:10.26#ibcon#read 4, iclass 37, count 0 2006.176.08:22:10.26#ibcon#about to read 5, iclass 37, count 0 2006.176.08:22:10.26#ibcon#read 5, iclass 37, count 0 2006.176.08:22:10.26#ibcon#about to read 6, iclass 37, count 0 2006.176.08:22:10.26#ibcon#read 6, iclass 37, count 0 2006.176.08:22:10.26#ibcon#end of sib2, iclass 37, count 0 2006.176.08:22:10.26#ibcon#*after write, iclass 37, count 0 2006.176.08:22:10.26#ibcon#*before return 0, iclass 37, count 0 2006.176.08:22:10.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:22:10.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.176.08:22:10.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:22:10.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:22:10.26$vc4f8/valo=8,852.99 2006.176.08:22:10.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.176.08:22:10.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.176.08:22:10.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:10.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:22:10.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:22:10.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:22:10.26#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:22:10.26#ibcon#first serial, iclass 39, count 0 2006.176.08:22:10.26#ibcon#enter sib2, iclass 39, count 0 2006.176.08:22:10.26#ibcon#flushed, iclass 39, count 0 2006.176.08:22:10.26#ibcon#about to write, iclass 39, count 0 2006.176.08:22:10.26#ibcon#wrote, iclass 39, count 0 2006.176.08:22:10.26#ibcon#about to read 3, iclass 39, count 0 2006.176.08:22:10.28#ibcon#read 3, iclass 39, count 0 2006.176.08:22:10.28#ibcon#about to read 4, iclass 39, count 0 2006.176.08:22:10.28#ibcon#read 4, iclass 39, count 0 2006.176.08:22:10.28#ibcon#about to read 5, iclass 39, count 0 2006.176.08:22:10.28#ibcon#read 5, iclass 39, count 0 2006.176.08:22:10.28#ibcon#about to read 6, iclass 39, count 0 2006.176.08:22:10.28#ibcon#read 6, iclass 39, count 0 2006.176.08:22:10.28#ibcon#end of sib2, iclass 39, count 0 2006.176.08:22:10.28#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:22:10.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:22:10.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:22:10.28#ibcon#*before write, iclass 39, count 0 2006.176.08:22:10.28#ibcon#enter sib2, iclass 39, count 0 2006.176.08:22:10.28#ibcon#flushed, iclass 39, count 0 2006.176.08:22:10.28#ibcon#about to write, iclass 39, count 0 2006.176.08:22:10.28#ibcon#wrote, iclass 39, count 0 2006.176.08:22:10.28#ibcon#about to read 3, iclass 39, count 0 2006.176.08:22:10.32#ibcon#read 3, iclass 39, count 0 2006.176.08:22:10.32#ibcon#about to read 4, iclass 39, count 0 2006.176.08:22:10.32#ibcon#read 4, iclass 39, count 0 2006.176.08:22:10.32#ibcon#about to read 5, iclass 39, count 0 2006.176.08:22:10.32#ibcon#read 5, iclass 39, count 0 2006.176.08:22:10.32#ibcon#about to read 6, iclass 39, count 0 2006.176.08:22:10.32#ibcon#read 6, iclass 39, count 0 2006.176.08:22:10.32#ibcon#end of sib2, iclass 39, count 0 2006.176.08:22:10.32#ibcon#*after write, iclass 39, count 0 2006.176.08:22:10.32#ibcon#*before return 0, iclass 39, count 0 2006.176.08:22:10.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:22:10.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.176.08:22:10.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:22:10.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:22:10.32$vc4f8/va=8,6 2006.176.08:22:10.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.176.08:22:10.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.176.08:22:10.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:10.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:22:10.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:22:10.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:22:10.38#ibcon#enter wrdev, iclass 3, count 2 2006.176.08:22:10.38#ibcon#first serial, iclass 3, count 2 2006.176.08:22:10.38#ibcon#enter sib2, iclass 3, count 2 2006.176.08:22:10.38#ibcon#flushed, iclass 3, count 2 2006.176.08:22:10.38#ibcon#about to write, iclass 3, count 2 2006.176.08:22:10.38#ibcon#wrote, iclass 3, count 2 2006.176.08:22:10.38#ibcon#about to read 3, iclass 3, count 2 2006.176.08:22:10.40#ibcon#read 3, iclass 3, count 2 2006.176.08:22:10.40#ibcon#about to read 4, iclass 3, count 2 2006.176.08:22:10.40#ibcon#read 4, iclass 3, count 2 2006.176.08:22:10.40#ibcon#about to read 5, iclass 3, count 2 2006.176.08:22:10.40#ibcon#read 5, iclass 3, count 2 2006.176.08:22:10.40#ibcon#about to read 6, iclass 3, count 2 2006.176.08:22:10.40#ibcon#read 6, iclass 3, count 2 2006.176.08:22:10.40#ibcon#end of sib2, iclass 3, count 2 2006.176.08:22:10.40#ibcon#*mode == 0, iclass 3, count 2 2006.176.08:22:10.40#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.176.08:22:10.40#ibcon#[25=AT08-06\r\n] 2006.176.08:22:10.40#ibcon#*before write, iclass 3, count 2 2006.176.08:22:10.40#ibcon#enter sib2, iclass 3, count 2 2006.176.08:22:10.40#ibcon#flushed, iclass 3, count 2 2006.176.08:22:10.40#ibcon#about to write, iclass 3, count 2 2006.176.08:22:10.40#ibcon#wrote, iclass 3, count 2 2006.176.08:22:10.40#ibcon#about to read 3, iclass 3, count 2 2006.176.08:22:10.43#ibcon#read 3, iclass 3, count 2 2006.176.08:22:10.43#ibcon#about to read 4, iclass 3, count 2 2006.176.08:22:10.43#ibcon#read 4, iclass 3, count 2 2006.176.08:22:10.43#ibcon#about to read 5, iclass 3, count 2 2006.176.08:22:10.43#ibcon#read 5, iclass 3, count 2 2006.176.08:22:10.43#ibcon#about to read 6, iclass 3, count 2 2006.176.08:22:10.43#ibcon#read 6, iclass 3, count 2 2006.176.08:22:10.43#ibcon#end of sib2, iclass 3, count 2 2006.176.08:22:10.43#ibcon#*after write, iclass 3, count 2 2006.176.08:22:10.43#ibcon#*before return 0, iclass 3, count 2 2006.176.08:22:10.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:22:10.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.176.08:22:10.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.176.08:22:10.43#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:10.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:22:10.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:22:10.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:22:10.55#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:22:10.55#ibcon#first serial, iclass 3, count 0 2006.176.08:22:10.55#ibcon#enter sib2, iclass 3, count 0 2006.176.08:22:10.55#ibcon#flushed, iclass 3, count 0 2006.176.08:22:10.55#ibcon#about to write, iclass 3, count 0 2006.176.08:22:10.55#ibcon#wrote, iclass 3, count 0 2006.176.08:22:10.55#ibcon#about to read 3, iclass 3, count 0 2006.176.08:22:10.57#ibcon#read 3, iclass 3, count 0 2006.176.08:22:10.57#ibcon#about to read 4, iclass 3, count 0 2006.176.08:22:10.57#ibcon#read 4, iclass 3, count 0 2006.176.08:22:10.57#ibcon#about to read 5, iclass 3, count 0 2006.176.08:22:10.57#ibcon#read 5, iclass 3, count 0 2006.176.08:22:10.57#ibcon#about to read 6, iclass 3, count 0 2006.176.08:22:10.57#ibcon#read 6, iclass 3, count 0 2006.176.08:22:10.57#ibcon#end of sib2, iclass 3, count 0 2006.176.08:22:10.57#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:22:10.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:22:10.57#ibcon#[25=USB\r\n] 2006.176.08:22:10.57#ibcon#*before write, iclass 3, count 0 2006.176.08:22:10.57#ibcon#enter sib2, iclass 3, count 0 2006.176.08:22:10.57#ibcon#flushed, iclass 3, count 0 2006.176.08:22:10.57#ibcon#about to write, iclass 3, count 0 2006.176.08:22:10.57#ibcon#wrote, iclass 3, count 0 2006.176.08:22:10.57#ibcon#about to read 3, iclass 3, count 0 2006.176.08:22:10.60#ibcon#read 3, iclass 3, count 0 2006.176.08:22:10.60#ibcon#about to read 4, iclass 3, count 0 2006.176.08:22:10.60#ibcon#read 4, iclass 3, count 0 2006.176.08:22:10.60#ibcon#about to read 5, iclass 3, count 0 2006.176.08:22:10.60#ibcon#read 5, iclass 3, count 0 2006.176.08:22:10.60#ibcon#about to read 6, iclass 3, count 0 2006.176.08:22:10.60#ibcon#read 6, iclass 3, count 0 2006.176.08:22:10.60#ibcon#end of sib2, iclass 3, count 0 2006.176.08:22:10.60#ibcon#*after write, iclass 3, count 0 2006.176.08:22:10.60#ibcon#*before return 0, iclass 3, count 0 2006.176.08:22:10.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:22:10.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.176.08:22:10.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:22:10.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:22:10.60$vc4f8/vblo=1,632.99 2006.176.08:22:10.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.176.08:22:10.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.176.08:22:10.60#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:10.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:22:10.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:22:10.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:22:10.60#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:22:10.60#ibcon#first serial, iclass 5, count 0 2006.176.08:22:10.60#ibcon#enter sib2, iclass 5, count 0 2006.176.08:22:10.60#ibcon#flushed, iclass 5, count 0 2006.176.08:22:10.60#ibcon#about to write, iclass 5, count 0 2006.176.08:22:10.60#ibcon#wrote, iclass 5, count 0 2006.176.08:22:10.60#ibcon#about to read 3, iclass 5, count 0 2006.176.08:22:10.62#ibcon#read 3, iclass 5, count 0 2006.176.08:22:10.62#ibcon#about to read 4, iclass 5, count 0 2006.176.08:22:10.62#ibcon#read 4, iclass 5, count 0 2006.176.08:22:10.62#ibcon#about to read 5, iclass 5, count 0 2006.176.08:22:10.62#ibcon#read 5, iclass 5, count 0 2006.176.08:22:10.62#ibcon#about to read 6, iclass 5, count 0 2006.176.08:22:10.62#ibcon#read 6, iclass 5, count 0 2006.176.08:22:10.62#ibcon#end of sib2, iclass 5, count 0 2006.176.08:22:10.62#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:22:10.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:22:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:22:10.62#ibcon#*before write, iclass 5, count 0 2006.176.08:22:10.62#ibcon#enter sib2, iclass 5, count 0 2006.176.08:22:10.62#ibcon#flushed, iclass 5, count 0 2006.176.08:22:10.62#ibcon#about to write, iclass 5, count 0 2006.176.08:22:10.62#ibcon#wrote, iclass 5, count 0 2006.176.08:22:10.62#ibcon#about to read 3, iclass 5, count 0 2006.176.08:22:10.66#ibcon#read 3, iclass 5, count 0 2006.176.08:22:10.66#ibcon#about to read 4, iclass 5, count 0 2006.176.08:22:10.66#ibcon#read 4, iclass 5, count 0 2006.176.08:22:10.66#ibcon#about to read 5, iclass 5, count 0 2006.176.08:22:10.66#ibcon#read 5, iclass 5, count 0 2006.176.08:22:10.66#ibcon#about to read 6, iclass 5, count 0 2006.176.08:22:10.66#ibcon#read 6, iclass 5, count 0 2006.176.08:22:10.66#ibcon#end of sib2, iclass 5, count 0 2006.176.08:22:10.66#ibcon#*after write, iclass 5, count 0 2006.176.08:22:10.66#ibcon#*before return 0, iclass 5, count 0 2006.176.08:22:10.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:22:10.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.176.08:22:10.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:22:10.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:22:10.66$vc4f8/vb=1,4 2006.176.08:22:10.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.176.08:22:10.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.176.08:22:10.66#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:10.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:22:10.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:22:10.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:22:10.66#ibcon#enter wrdev, iclass 7, count 2 2006.176.08:22:10.66#ibcon#first serial, iclass 7, count 2 2006.176.08:22:10.66#ibcon#enter sib2, iclass 7, count 2 2006.176.08:22:10.66#ibcon#flushed, iclass 7, count 2 2006.176.08:22:10.66#ibcon#about to write, iclass 7, count 2 2006.176.08:22:10.66#ibcon#wrote, iclass 7, count 2 2006.176.08:22:10.66#ibcon#about to read 3, iclass 7, count 2 2006.176.08:22:10.68#ibcon#read 3, iclass 7, count 2 2006.176.08:22:10.68#ibcon#about to read 4, iclass 7, count 2 2006.176.08:22:10.68#ibcon#read 4, iclass 7, count 2 2006.176.08:22:10.68#ibcon#about to read 5, iclass 7, count 2 2006.176.08:22:10.68#ibcon#read 5, iclass 7, count 2 2006.176.08:22:10.68#ibcon#about to read 6, iclass 7, count 2 2006.176.08:22:10.68#ibcon#read 6, iclass 7, count 2 2006.176.08:22:10.68#ibcon#end of sib2, iclass 7, count 2 2006.176.08:22:10.68#ibcon#*mode == 0, iclass 7, count 2 2006.176.08:22:10.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.176.08:22:10.68#ibcon#[27=AT01-04\r\n] 2006.176.08:22:10.68#ibcon#*before write, iclass 7, count 2 2006.176.08:22:10.68#ibcon#enter sib2, iclass 7, count 2 2006.176.08:22:10.68#ibcon#flushed, iclass 7, count 2 2006.176.08:22:10.68#ibcon#about to write, iclass 7, count 2 2006.176.08:22:10.68#ibcon#wrote, iclass 7, count 2 2006.176.08:22:10.68#ibcon#about to read 3, iclass 7, count 2 2006.176.08:22:10.71#ibcon#read 3, iclass 7, count 2 2006.176.08:22:10.71#ibcon#about to read 4, iclass 7, count 2 2006.176.08:22:10.71#ibcon#read 4, iclass 7, count 2 2006.176.08:22:10.71#ibcon#about to read 5, iclass 7, count 2 2006.176.08:22:10.71#ibcon#read 5, iclass 7, count 2 2006.176.08:22:10.71#ibcon#about to read 6, iclass 7, count 2 2006.176.08:22:10.71#ibcon#read 6, iclass 7, count 2 2006.176.08:22:10.71#ibcon#end of sib2, iclass 7, count 2 2006.176.08:22:10.71#ibcon#*after write, iclass 7, count 2 2006.176.08:22:10.71#ibcon#*before return 0, iclass 7, count 2 2006.176.08:22:10.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:22:10.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.176.08:22:10.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.176.08:22:10.71#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:10.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:22:10.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:22:10.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:22:10.83#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:22:10.83#ibcon#first serial, iclass 7, count 0 2006.176.08:22:10.83#ibcon#enter sib2, iclass 7, count 0 2006.176.08:22:10.83#ibcon#flushed, iclass 7, count 0 2006.176.08:22:10.83#ibcon#about to write, iclass 7, count 0 2006.176.08:22:10.83#ibcon#wrote, iclass 7, count 0 2006.176.08:22:10.83#ibcon#about to read 3, iclass 7, count 0 2006.176.08:22:10.85#ibcon#read 3, iclass 7, count 0 2006.176.08:22:10.85#ibcon#about to read 4, iclass 7, count 0 2006.176.08:22:10.85#ibcon#read 4, iclass 7, count 0 2006.176.08:22:10.85#ibcon#about to read 5, iclass 7, count 0 2006.176.08:22:10.85#ibcon#read 5, iclass 7, count 0 2006.176.08:22:10.85#ibcon#about to read 6, iclass 7, count 0 2006.176.08:22:10.85#ibcon#read 6, iclass 7, count 0 2006.176.08:22:10.85#ibcon#end of sib2, iclass 7, count 0 2006.176.08:22:10.85#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:22:10.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:22:10.85#ibcon#[27=USB\r\n] 2006.176.08:22:10.85#ibcon#*before write, iclass 7, count 0 2006.176.08:22:10.85#ibcon#enter sib2, iclass 7, count 0 2006.176.08:22:10.85#ibcon#flushed, iclass 7, count 0 2006.176.08:22:10.85#ibcon#about to write, iclass 7, count 0 2006.176.08:22:10.85#ibcon#wrote, iclass 7, count 0 2006.176.08:22:10.85#ibcon#about to read 3, iclass 7, count 0 2006.176.08:22:10.88#ibcon#read 3, iclass 7, count 0 2006.176.08:22:10.88#ibcon#about to read 4, iclass 7, count 0 2006.176.08:22:10.88#ibcon#read 4, iclass 7, count 0 2006.176.08:22:10.88#ibcon#about to read 5, iclass 7, count 0 2006.176.08:22:10.88#ibcon#read 5, iclass 7, count 0 2006.176.08:22:10.88#ibcon#about to read 6, iclass 7, count 0 2006.176.08:22:10.88#ibcon#read 6, iclass 7, count 0 2006.176.08:22:10.88#ibcon#end of sib2, iclass 7, count 0 2006.176.08:22:10.88#ibcon#*after write, iclass 7, count 0 2006.176.08:22:10.88#ibcon#*before return 0, iclass 7, count 0 2006.176.08:22:10.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:22:10.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.176.08:22:10.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:22:10.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:22:10.88$vc4f8/vblo=2,640.99 2006.176.08:22:10.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.176.08:22:10.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.176.08:22:10.88#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:10.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:10.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:10.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:10.88#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:22:10.88#ibcon#first serial, iclass 11, count 0 2006.176.08:22:10.88#ibcon#enter sib2, iclass 11, count 0 2006.176.08:22:10.88#ibcon#flushed, iclass 11, count 0 2006.176.08:22:10.88#ibcon#about to write, iclass 11, count 0 2006.176.08:22:10.88#ibcon#wrote, iclass 11, count 0 2006.176.08:22:10.88#ibcon#about to read 3, iclass 11, count 0 2006.176.08:22:10.90#ibcon#read 3, iclass 11, count 0 2006.176.08:22:10.90#ibcon#about to read 4, iclass 11, count 0 2006.176.08:22:10.90#ibcon#read 4, iclass 11, count 0 2006.176.08:22:10.90#ibcon#about to read 5, iclass 11, count 0 2006.176.08:22:10.90#ibcon#read 5, iclass 11, count 0 2006.176.08:22:10.90#ibcon#about to read 6, iclass 11, count 0 2006.176.08:22:10.90#ibcon#read 6, iclass 11, count 0 2006.176.08:22:10.90#ibcon#end of sib2, iclass 11, count 0 2006.176.08:22:10.90#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:22:10.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:22:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:22:10.90#ibcon#*before write, iclass 11, count 0 2006.176.08:22:10.90#ibcon#enter sib2, iclass 11, count 0 2006.176.08:22:10.90#ibcon#flushed, iclass 11, count 0 2006.176.08:22:10.90#ibcon#about to write, iclass 11, count 0 2006.176.08:22:10.90#ibcon#wrote, iclass 11, count 0 2006.176.08:22:10.90#ibcon#about to read 3, iclass 11, count 0 2006.176.08:22:10.94#ibcon#read 3, iclass 11, count 0 2006.176.08:22:10.94#ibcon#about to read 4, iclass 11, count 0 2006.176.08:22:10.94#ibcon#read 4, iclass 11, count 0 2006.176.08:22:10.94#ibcon#about to read 5, iclass 11, count 0 2006.176.08:22:10.94#ibcon#read 5, iclass 11, count 0 2006.176.08:22:10.94#ibcon#about to read 6, iclass 11, count 0 2006.176.08:22:10.94#ibcon#read 6, iclass 11, count 0 2006.176.08:22:10.94#ibcon#end of sib2, iclass 11, count 0 2006.176.08:22:10.94#ibcon#*after write, iclass 11, count 0 2006.176.08:22:10.94#ibcon#*before return 0, iclass 11, count 0 2006.176.08:22:10.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:10.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.176.08:22:10.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:22:10.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:22:10.94$vc4f8/vb=2,4 2006.176.08:22:10.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.176.08:22:10.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.176.08:22:10.94#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:10.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:11.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:11.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:11.00#ibcon#enter wrdev, iclass 13, count 2 2006.176.08:22:11.00#ibcon#first serial, iclass 13, count 2 2006.176.08:22:11.00#ibcon#enter sib2, iclass 13, count 2 2006.176.08:22:11.00#ibcon#flushed, iclass 13, count 2 2006.176.08:22:11.00#ibcon#about to write, iclass 13, count 2 2006.176.08:22:11.00#ibcon#wrote, iclass 13, count 2 2006.176.08:22:11.00#ibcon#about to read 3, iclass 13, count 2 2006.176.08:22:11.02#ibcon#read 3, iclass 13, count 2 2006.176.08:22:11.02#ibcon#about to read 4, iclass 13, count 2 2006.176.08:22:11.02#ibcon#read 4, iclass 13, count 2 2006.176.08:22:11.02#ibcon#about to read 5, iclass 13, count 2 2006.176.08:22:11.02#ibcon#read 5, iclass 13, count 2 2006.176.08:22:11.02#ibcon#about to read 6, iclass 13, count 2 2006.176.08:22:11.02#ibcon#read 6, iclass 13, count 2 2006.176.08:22:11.02#ibcon#end of sib2, iclass 13, count 2 2006.176.08:22:11.02#ibcon#*mode == 0, iclass 13, count 2 2006.176.08:22:11.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.176.08:22:11.02#ibcon#[27=AT02-04\r\n] 2006.176.08:22:11.02#ibcon#*before write, iclass 13, count 2 2006.176.08:22:11.02#ibcon#enter sib2, iclass 13, count 2 2006.176.08:22:11.02#ibcon#flushed, iclass 13, count 2 2006.176.08:22:11.02#ibcon#about to write, iclass 13, count 2 2006.176.08:22:11.02#ibcon#wrote, iclass 13, count 2 2006.176.08:22:11.02#ibcon#about to read 3, iclass 13, count 2 2006.176.08:22:11.05#ibcon#read 3, iclass 13, count 2 2006.176.08:22:11.05#ibcon#about to read 4, iclass 13, count 2 2006.176.08:22:11.05#ibcon#read 4, iclass 13, count 2 2006.176.08:22:11.05#ibcon#about to read 5, iclass 13, count 2 2006.176.08:22:11.05#ibcon#read 5, iclass 13, count 2 2006.176.08:22:11.05#ibcon#about to read 6, iclass 13, count 2 2006.176.08:22:11.05#ibcon#read 6, iclass 13, count 2 2006.176.08:22:11.05#ibcon#end of sib2, iclass 13, count 2 2006.176.08:22:11.05#ibcon#*after write, iclass 13, count 2 2006.176.08:22:11.05#ibcon#*before return 0, iclass 13, count 2 2006.176.08:22:11.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:11.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.176.08:22:11.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.176.08:22:11.05#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:11.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:11.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:11.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:11.17#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:22:11.17#ibcon#first serial, iclass 13, count 0 2006.176.08:22:11.17#ibcon#enter sib2, iclass 13, count 0 2006.176.08:22:11.17#ibcon#flushed, iclass 13, count 0 2006.176.08:22:11.17#ibcon#about to write, iclass 13, count 0 2006.176.08:22:11.17#ibcon#wrote, iclass 13, count 0 2006.176.08:22:11.17#ibcon#about to read 3, iclass 13, count 0 2006.176.08:22:11.19#ibcon#read 3, iclass 13, count 0 2006.176.08:22:11.19#ibcon#about to read 4, iclass 13, count 0 2006.176.08:22:11.19#ibcon#read 4, iclass 13, count 0 2006.176.08:22:11.19#ibcon#about to read 5, iclass 13, count 0 2006.176.08:22:11.19#ibcon#read 5, iclass 13, count 0 2006.176.08:22:11.19#ibcon#about to read 6, iclass 13, count 0 2006.176.08:22:11.19#ibcon#read 6, iclass 13, count 0 2006.176.08:22:11.19#ibcon#end of sib2, iclass 13, count 0 2006.176.08:22:11.19#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:22:11.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:22:11.19#ibcon#[27=USB\r\n] 2006.176.08:22:11.19#ibcon#*before write, iclass 13, count 0 2006.176.08:22:11.19#ibcon#enter sib2, iclass 13, count 0 2006.176.08:22:11.19#ibcon#flushed, iclass 13, count 0 2006.176.08:22:11.19#ibcon#about to write, iclass 13, count 0 2006.176.08:22:11.19#ibcon#wrote, iclass 13, count 0 2006.176.08:22:11.19#ibcon#about to read 3, iclass 13, count 0 2006.176.08:22:11.22#ibcon#read 3, iclass 13, count 0 2006.176.08:22:11.22#ibcon#about to read 4, iclass 13, count 0 2006.176.08:22:11.22#ibcon#read 4, iclass 13, count 0 2006.176.08:22:11.22#ibcon#about to read 5, iclass 13, count 0 2006.176.08:22:11.22#ibcon#read 5, iclass 13, count 0 2006.176.08:22:11.22#ibcon#about to read 6, iclass 13, count 0 2006.176.08:22:11.22#ibcon#read 6, iclass 13, count 0 2006.176.08:22:11.22#ibcon#end of sib2, iclass 13, count 0 2006.176.08:22:11.22#ibcon#*after write, iclass 13, count 0 2006.176.08:22:11.22#ibcon#*before return 0, iclass 13, count 0 2006.176.08:22:11.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:11.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.176.08:22:11.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:22:11.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:22:11.22$vc4f8/vblo=3,656.99 2006.176.08:22:11.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.176.08:22:11.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.176.08:22:11.22#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:11.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:11.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:11.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:11.22#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:22:11.22#ibcon#first serial, iclass 15, count 0 2006.176.08:22:11.22#ibcon#enter sib2, iclass 15, count 0 2006.176.08:22:11.22#ibcon#flushed, iclass 15, count 0 2006.176.08:22:11.22#ibcon#about to write, iclass 15, count 0 2006.176.08:22:11.22#ibcon#wrote, iclass 15, count 0 2006.176.08:22:11.22#ibcon#about to read 3, iclass 15, count 0 2006.176.08:22:11.24#ibcon#read 3, iclass 15, count 0 2006.176.08:22:11.24#ibcon#about to read 4, iclass 15, count 0 2006.176.08:22:11.24#ibcon#read 4, iclass 15, count 0 2006.176.08:22:11.24#ibcon#about to read 5, iclass 15, count 0 2006.176.08:22:11.24#ibcon#read 5, iclass 15, count 0 2006.176.08:22:11.24#ibcon#about to read 6, iclass 15, count 0 2006.176.08:22:11.24#ibcon#read 6, iclass 15, count 0 2006.176.08:22:11.24#ibcon#end of sib2, iclass 15, count 0 2006.176.08:22:11.24#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:22:11.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:22:11.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:22:11.24#ibcon#*before write, iclass 15, count 0 2006.176.08:22:11.24#ibcon#enter sib2, iclass 15, count 0 2006.176.08:22:11.24#ibcon#flushed, iclass 15, count 0 2006.176.08:22:11.24#ibcon#about to write, iclass 15, count 0 2006.176.08:22:11.24#ibcon#wrote, iclass 15, count 0 2006.176.08:22:11.24#ibcon#about to read 3, iclass 15, count 0 2006.176.08:22:11.28#ibcon#read 3, iclass 15, count 0 2006.176.08:22:11.28#ibcon#about to read 4, iclass 15, count 0 2006.176.08:22:11.28#ibcon#read 4, iclass 15, count 0 2006.176.08:22:11.28#ibcon#about to read 5, iclass 15, count 0 2006.176.08:22:11.28#ibcon#read 5, iclass 15, count 0 2006.176.08:22:11.28#ibcon#about to read 6, iclass 15, count 0 2006.176.08:22:11.28#ibcon#read 6, iclass 15, count 0 2006.176.08:22:11.28#ibcon#end of sib2, iclass 15, count 0 2006.176.08:22:11.28#ibcon#*after write, iclass 15, count 0 2006.176.08:22:11.28#ibcon#*before return 0, iclass 15, count 0 2006.176.08:22:11.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:11.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.176.08:22:11.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:22:11.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:22:11.28$vc4f8/vb=3,4 2006.176.08:22:11.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.176.08:22:11.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.176.08:22:11.28#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:11.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:11.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:11.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:11.34#ibcon#enter wrdev, iclass 17, count 2 2006.176.08:22:11.34#ibcon#first serial, iclass 17, count 2 2006.176.08:22:11.34#ibcon#enter sib2, iclass 17, count 2 2006.176.08:22:11.34#ibcon#flushed, iclass 17, count 2 2006.176.08:22:11.34#ibcon#about to write, iclass 17, count 2 2006.176.08:22:11.34#ibcon#wrote, iclass 17, count 2 2006.176.08:22:11.34#ibcon#about to read 3, iclass 17, count 2 2006.176.08:22:11.36#ibcon#read 3, iclass 17, count 2 2006.176.08:22:11.36#ibcon#about to read 4, iclass 17, count 2 2006.176.08:22:11.36#ibcon#read 4, iclass 17, count 2 2006.176.08:22:11.36#ibcon#about to read 5, iclass 17, count 2 2006.176.08:22:11.36#ibcon#read 5, iclass 17, count 2 2006.176.08:22:11.36#ibcon#about to read 6, iclass 17, count 2 2006.176.08:22:11.36#ibcon#read 6, iclass 17, count 2 2006.176.08:22:11.36#ibcon#end of sib2, iclass 17, count 2 2006.176.08:22:11.36#ibcon#*mode == 0, iclass 17, count 2 2006.176.08:22:11.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.176.08:22:11.36#ibcon#[27=AT03-04\r\n] 2006.176.08:22:11.36#ibcon#*before write, iclass 17, count 2 2006.176.08:22:11.36#ibcon#enter sib2, iclass 17, count 2 2006.176.08:22:11.36#ibcon#flushed, iclass 17, count 2 2006.176.08:22:11.36#ibcon#about to write, iclass 17, count 2 2006.176.08:22:11.36#ibcon#wrote, iclass 17, count 2 2006.176.08:22:11.36#ibcon#about to read 3, iclass 17, count 2 2006.176.08:22:11.39#ibcon#read 3, iclass 17, count 2 2006.176.08:22:11.39#ibcon#about to read 4, iclass 17, count 2 2006.176.08:22:11.39#ibcon#read 4, iclass 17, count 2 2006.176.08:22:11.39#ibcon#about to read 5, iclass 17, count 2 2006.176.08:22:11.39#ibcon#read 5, iclass 17, count 2 2006.176.08:22:11.39#ibcon#about to read 6, iclass 17, count 2 2006.176.08:22:11.39#ibcon#read 6, iclass 17, count 2 2006.176.08:22:11.39#ibcon#end of sib2, iclass 17, count 2 2006.176.08:22:11.39#ibcon#*after write, iclass 17, count 2 2006.176.08:22:11.39#ibcon#*before return 0, iclass 17, count 2 2006.176.08:22:11.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:11.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.176.08:22:11.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.176.08:22:11.39#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:11.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:11.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:11.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:11.51#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:22:11.51#ibcon#first serial, iclass 17, count 0 2006.176.08:22:11.51#ibcon#enter sib2, iclass 17, count 0 2006.176.08:22:11.51#ibcon#flushed, iclass 17, count 0 2006.176.08:22:11.51#ibcon#about to write, iclass 17, count 0 2006.176.08:22:11.51#ibcon#wrote, iclass 17, count 0 2006.176.08:22:11.51#ibcon#about to read 3, iclass 17, count 0 2006.176.08:22:11.53#ibcon#read 3, iclass 17, count 0 2006.176.08:22:11.53#ibcon#about to read 4, iclass 17, count 0 2006.176.08:22:11.53#ibcon#read 4, iclass 17, count 0 2006.176.08:22:11.53#ibcon#about to read 5, iclass 17, count 0 2006.176.08:22:11.53#ibcon#read 5, iclass 17, count 0 2006.176.08:22:11.53#ibcon#about to read 6, iclass 17, count 0 2006.176.08:22:11.53#ibcon#read 6, iclass 17, count 0 2006.176.08:22:11.53#ibcon#end of sib2, iclass 17, count 0 2006.176.08:22:11.53#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:22:11.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:22:11.53#ibcon#[27=USB\r\n] 2006.176.08:22:11.53#ibcon#*before write, iclass 17, count 0 2006.176.08:22:11.53#ibcon#enter sib2, iclass 17, count 0 2006.176.08:22:11.53#ibcon#flushed, iclass 17, count 0 2006.176.08:22:11.53#ibcon#about to write, iclass 17, count 0 2006.176.08:22:11.53#ibcon#wrote, iclass 17, count 0 2006.176.08:22:11.53#ibcon#about to read 3, iclass 17, count 0 2006.176.08:22:11.56#ibcon#read 3, iclass 17, count 0 2006.176.08:22:11.56#ibcon#about to read 4, iclass 17, count 0 2006.176.08:22:11.56#ibcon#read 4, iclass 17, count 0 2006.176.08:22:11.56#ibcon#about to read 5, iclass 17, count 0 2006.176.08:22:11.56#ibcon#read 5, iclass 17, count 0 2006.176.08:22:11.56#ibcon#about to read 6, iclass 17, count 0 2006.176.08:22:11.56#ibcon#read 6, iclass 17, count 0 2006.176.08:22:11.56#ibcon#end of sib2, iclass 17, count 0 2006.176.08:22:11.56#ibcon#*after write, iclass 17, count 0 2006.176.08:22:11.56#ibcon#*before return 0, iclass 17, count 0 2006.176.08:22:11.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:11.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.176.08:22:11.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:22:11.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:22:11.56$vc4f8/vblo=4,712.99 2006.176.08:22:11.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.176.08:22:11.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.176.08:22:11.56#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:11.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:11.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:11.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:11.56#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:22:11.56#ibcon#first serial, iclass 19, count 0 2006.176.08:22:11.56#ibcon#enter sib2, iclass 19, count 0 2006.176.08:22:11.56#ibcon#flushed, iclass 19, count 0 2006.176.08:22:11.56#ibcon#about to write, iclass 19, count 0 2006.176.08:22:11.56#ibcon#wrote, iclass 19, count 0 2006.176.08:22:11.56#ibcon#about to read 3, iclass 19, count 0 2006.176.08:22:11.58#ibcon#read 3, iclass 19, count 0 2006.176.08:22:11.58#ibcon#about to read 4, iclass 19, count 0 2006.176.08:22:11.58#ibcon#read 4, iclass 19, count 0 2006.176.08:22:11.58#ibcon#about to read 5, iclass 19, count 0 2006.176.08:22:11.58#ibcon#read 5, iclass 19, count 0 2006.176.08:22:11.58#ibcon#about to read 6, iclass 19, count 0 2006.176.08:22:11.58#ibcon#read 6, iclass 19, count 0 2006.176.08:22:11.58#ibcon#end of sib2, iclass 19, count 0 2006.176.08:22:11.58#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:22:11.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:22:11.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:22:11.58#ibcon#*before write, iclass 19, count 0 2006.176.08:22:11.58#ibcon#enter sib2, iclass 19, count 0 2006.176.08:22:11.58#ibcon#flushed, iclass 19, count 0 2006.176.08:22:11.58#ibcon#about to write, iclass 19, count 0 2006.176.08:22:11.58#ibcon#wrote, iclass 19, count 0 2006.176.08:22:11.58#ibcon#about to read 3, iclass 19, count 0 2006.176.08:22:11.62#ibcon#read 3, iclass 19, count 0 2006.176.08:22:11.62#ibcon#about to read 4, iclass 19, count 0 2006.176.08:22:11.62#ibcon#read 4, iclass 19, count 0 2006.176.08:22:11.62#ibcon#about to read 5, iclass 19, count 0 2006.176.08:22:11.62#ibcon#read 5, iclass 19, count 0 2006.176.08:22:11.62#ibcon#about to read 6, iclass 19, count 0 2006.176.08:22:11.62#ibcon#read 6, iclass 19, count 0 2006.176.08:22:11.62#ibcon#end of sib2, iclass 19, count 0 2006.176.08:22:11.62#ibcon#*after write, iclass 19, count 0 2006.176.08:22:11.62#ibcon#*before return 0, iclass 19, count 0 2006.176.08:22:11.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:11.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.176.08:22:11.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:22:11.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:22:11.62$vc4f8/vb=4,4 2006.176.08:22:11.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.176.08:22:11.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.176.08:22:11.62#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:11.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:11.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:11.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:11.68#ibcon#enter wrdev, iclass 21, count 2 2006.176.08:22:11.68#ibcon#first serial, iclass 21, count 2 2006.176.08:22:11.68#ibcon#enter sib2, iclass 21, count 2 2006.176.08:22:11.68#ibcon#flushed, iclass 21, count 2 2006.176.08:22:11.68#ibcon#about to write, iclass 21, count 2 2006.176.08:22:11.68#ibcon#wrote, iclass 21, count 2 2006.176.08:22:11.68#ibcon#about to read 3, iclass 21, count 2 2006.176.08:22:11.70#ibcon#read 3, iclass 21, count 2 2006.176.08:22:11.70#ibcon#about to read 4, iclass 21, count 2 2006.176.08:22:11.70#ibcon#read 4, iclass 21, count 2 2006.176.08:22:11.70#ibcon#about to read 5, iclass 21, count 2 2006.176.08:22:11.70#ibcon#read 5, iclass 21, count 2 2006.176.08:22:11.70#ibcon#about to read 6, iclass 21, count 2 2006.176.08:22:11.70#ibcon#read 6, iclass 21, count 2 2006.176.08:22:11.70#ibcon#end of sib2, iclass 21, count 2 2006.176.08:22:11.70#ibcon#*mode == 0, iclass 21, count 2 2006.176.08:22:11.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.176.08:22:11.70#ibcon#[27=AT04-04\r\n] 2006.176.08:22:11.70#ibcon#*before write, iclass 21, count 2 2006.176.08:22:11.70#ibcon#enter sib2, iclass 21, count 2 2006.176.08:22:11.70#ibcon#flushed, iclass 21, count 2 2006.176.08:22:11.70#ibcon#about to write, iclass 21, count 2 2006.176.08:22:11.70#ibcon#wrote, iclass 21, count 2 2006.176.08:22:11.70#ibcon#about to read 3, iclass 21, count 2 2006.176.08:22:11.73#ibcon#read 3, iclass 21, count 2 2006.176.08:22:11.73#ibcon#about to read 4, iclass 21, count 2 2006.176.08:22:11.73#ibcon#read 4, iclass 21, count 2 2006.176.08:22:11.73#ibcon#about to read 5, iclass 21, count 2 2006.176.08:22:11.73#ibcon#read 5, iclass 21, count 2 2006.176.08:22:11.73#ibcon#about to read 6, iclass 21, count 2 2006.176.08:22:11.73#ibcon#read 6, iclass 21, count 2 2006.176.08:22:11.73#ibcon#end of sib2, iclass 21, count 2 2006.176.08:22:11.73#ibcon#*after write, iclass 21, count 2 2006.176.08:22:11.73#ibcon#*before return 0, iclass 21, count 2 2006.176.08:22:11.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:11.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.176.08:22:11.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.176.08:22:11.73#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:11.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:11.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:11.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:11.85#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:22:11.85#ibcon#first serial, iclass 21, count 0 2006.176.08:22:11.85#ibcon#enter sib2, iclass 21, count 0 2006.176.08:22:11.85#ibcon#flushed, iclass 21, count 0 2006.176.08:22:11.85#ibcon#about to write, iclass 21, count 0 2006.176.08:22:11.85#ibcon#wrote, iclass 21, count 0 2006.176.08:22:11.85#ibcon#about to read 3, iclass 21, count 0 2006.176.08:22:11.87#ibcon#read 3, iclass 21, count 0 2006.176.08:22:11.87#ibcon#about to read 4, iclass 21, count 0 2006.176.08:22:11.87#ibcon#read 4, iclass 21, count 0 2006.176.08:22:11.87#ibcon#about to read 5, iclass 21, count 0 2006.176.08:22:11.87#ibcon#read 5, iclass 21, count 0 2006.176.08:22:11.87#ibcon#about to read 6, iclass 21, count 0 2006.176.08:22:11.87#ibcon#read 6, iclass 21, count 0 2006.176.08:22:11.87#ibcon#end of sib2, iclass 21, count 0 2006.176.08:22:11.87#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:22:11.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:22:11.87#ibcon#[27=USB\r\n] 2006.176.08:22:11.87#ibcon#*before write, iclass 21, count 0 2006.176.08:22:11.87#ibcon#enter sib2, iclass 21, count 0 2006.176.08:22:11.87#ibcon#flushed, iclass 21, count 0 2006.176.08:22:11.87#ibcon#about to write, iclass 21, count 0 2006.176.08:22:11.87#ibcon#wrote, iclass 21, count 0 2006.176.08:22:11.87#ibcon#about to read 3, iclass 21, count 0 2006.176.08:22:11.90#ibcon#read 3, iclass 21, count 0 2006.176.08:22:11.90#ibcon#about to read 4, iclass 21, count 0 2006.176.08:22:11.90#ibcon#read 4, iclass 21, count 0 2006.176.08:22:11.90#ibcon#about to read 5, iclass 21, count 0 2006.176.08:22:11.90#ibcon#read 5, iclass 21, count 0 2006.176.08:22:11.90#ibcon#about to read 6, iclass 21, count 0 2006.176.08:22:11.90#ibcon#read 6, iclass 21, count 0 2006.176.08:22:11.90#ibcon#end of sib2, iclass 21, count 0 2006.176.08:22:11.90#ibcon#*after write, iclass 21, count 0 2006.176.08:22:11.90#ibcon#*before return 0, iclass 21, count 0 2006.176.08:22:11.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:11.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.176.08:22:11.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:22:11.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:22:11.90$vc4f8/vblo=5,744.99 2006.176.08:22:11.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.176.08:22:11.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.176.08:22:11.90#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:11.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:11.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:11.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:11.90#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:22:11.90#ibcon#first serial, iclass 23, count 0 2006.176.08:22:11.90#ibcon#enter sib2, iclass 23, count 0 2006.176.08:22:11.90#ibcon#flushed, iclass 23, count 0 2006.176.08:22:11.90#ibcon#about to write, iclass 23, count 0 2006.176.08:22:11.90#ibcon#wrote, iclass 23, count 0 2006.176.08:22:11.90#ibcon#about to read 3, iclass 23, count 0 2006.176.08:22:11.92#ibcon#read 3, iclass 23, count 0 2006.176.08:22:11.92#ibcon#about to read 4, iclass 23, count 0 2006.176.08:22:11.92#ibcon#read 4, iclass 23, count 0 2006.176.08:22:11.92#ibcon#about to read 5, iclass 23, count 0 2006.176.08:22:11.92#ibcon#read 5, iclass 23, count 0 2006.176.08:22:11.92#ibcon#about to read 6, iclass 23, count 0 2006.176.08:22:11.92#ibcon#read 6, iclass 23, count 0 2006.176.08:22:11.92#ibcon#end of sib2, iclass 23, count 0 2006.176.08:22:11.92#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:22:11.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:22:11.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:22:11.92#ibcon#*before write, iclass 23, count 0 2006.176.08:22:11.92#ibcon#enter sib2, iclass 23, count 0 2006.176.08:22:11.92#ibcon#flushed, iclass 23, count 0 2006.176.08:22:11.92#ibcon#about to write, iclass 23, count 0 2006.176.08:22:11.92#ibcon#wrote, iclass 23, count 0 2006.176.08:22:11.92#ibcon#about to read 3, iclass 23, count 0 2006.176.08:22:11.96#ibcon#read 3, iclass 23, count 0 2006.176.08:22:11.96#ibcon#about to read 4, iclass 23, count 0 2006.176.08:22:11.96#ibcon#read 4, iclass 23, count 0 2006.176.08:22:11.96#ibcon#about to read 5, iclass 23, count 0 2006.176.08:22:11.96#ibcon#read 5, iclass 23, count 0 2006.176.08:22:11.96#ibcon#about to read 6, iclass 23, count 0 2006.176.08:22:11.96#ibcon#read 6, iclass 23, count 0 2006.176.08:22:11.96#ibcon#end of sib2, iclass 23, count 0 2006.176.08:22:11.96#ibcon#*after write, iclass 23, count 0 2006.176.08:22:11.96#ibcon#*before return 0, iclass 23, count 0 2006.176.08:22:11.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:11.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.176.08:22:11.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:22:11.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:22:11.96$vc4f8/vb=5,4 2006.176.08:22:11.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.176.08:22:11.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.176.08:22:11.96#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:11.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:12.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:12.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:12.02#ibcon#enter wrdev, iclass 25, count 2 2006.176.08:22:12.02#ibcon#first serial, iclass 25, count 2 2006.176.08:22:12.02#ibcon#enter sib2, iclass 25, count 2 2006.176.08:22:12.02#ibcon#flushed, iclass 25, count 2 2006.176.08:22:12.02#ibcon#about to write, iclass 25, count 2 2006.176.08:22:12.02#ibcon#wrote, iclass 25, count 2 2006.176.08:22:12.02#ibcon#about to read 3, iclass 25, count 2 2006.176.08:22:12.04#ibcon#read 3, iclass 25, count 2 2006.176.08:22:12.04#ibcon#about to read 4, iclass 25, count 2 2006.176.08:22:12.04#ibcon#read 4, iclass 25, count 2 2006.176.08:22:12.04#ibcon#about to read 5, iclass 25, count 2 2006.176.08:22:12.04#ibcon#read 5, iclass 25, count 2 2006.176.08:22:12.04#ibcon#about to read 6, iclass 25, count 2 2006.176.08:22:12.04#ibcon#read 6, iclass 25, count 2 2006.176.08:22:12.04#ibcon#end of sib2, iclass 25, count 2 2006.176.08:22:12.04#ibcon#*mode == 0, iclass 25, count 2 2006.176.08:22:12.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.176.08:22:12.04#ibcon#[27=AT05-04\r\n] 2006.176.08:22:12.04#ibcon#*before write, iclass 25, count 2 2006.176.08:22:12.04#ibcon#enter sib2, iclass 25, count 2 2006.176.08:22:12.04#ibcon#flushed, iclass 25, count 2 2006.176.08:22:12.04#ibcon#about to write, iclass 25, count 2 2006.176.08:22:12.04#ibcon#wrote, iclass 25, count 2 2006.176.08:22:12.04#ibcon#about to read 3, iclass 25, count 2 2006.176.08:22:12.07#ibcon#read 3, iclass 25, count 2 2006.176.08:22:12.07#ibcon#about to read 4, iclass 25, count 2 2006.176.08:22:12.07#ibcon#read 4, iclass 25, count 2 2006.176.08:22:12.07#ibcon#about to read 5, iclass 25, count 2 2006.176.08:22:12.07#ibcon#read 5, iclass 25, count 2 2006.176.08:22:12.07#ibcon#about to read 6, iclass 25, count 2 2006.176.08:22:12.07#ibcon#read 6, iclass 25, count 2 2006.176.08:22:12.07#ibcon#end of sib2, iclass 25, count 2 2006.176.08:22:12.07#ibcon#*after write, iclass 25, count 2 2006.176.08:22:12.07#ibcon#*before return 0, iclass 25, count 2 2006.176.08:22:12.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:12.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:22:12.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.176.08:22:12.07#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:12.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:12.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:12.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:12.19#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:22:12.19#ibcon#first serial, iclass 25, count 0 2006.176.08:22:12.19#ibcon#enter sib2, iclass 25, count 0 2006.176.08:22:12.19#ibcon#flushed, iclass 25, count 0 2006.176.08:22:12.19#ibcon#about to write, iclass 25, count 0 2006.176.08:22:12.19#ibcon#wrote, iclass 25, count 0 2006.176.08:22:12.19#ibcon#about to read 3, iclass 25, count 0 2006.176.08:22:12.21#ibcon#read 3, iclass 25, count 0 2006.176.08:22:12.21#ibcon#about to read 4, iclass 25, count 0 2006.176.08:22:12.21#ibcon#read 4, iclass 25, count 0 2006.176.08:22:12.21#ibcon#about to read 5, iclass 25, count 0 2006.176.08:22:12.21#ibcon#read 5, iclass 25, count 0 2006.176.08:22:12.21#ibcon#about to read 6, iclass 25, count 0 2006.176.08:22:12.21#ibcon#read 6, iclass 25, count 0 2006.176.08:22:12.21#ibcon#end of sib2, iclass 25, count 0 2006.176.08:22:12.21#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:22:12.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:22:12.21#ibcon#[27=USB\r\n] 2006.176.08:22:12.21#ibcon#*before write, iclass 25, count 0 2006.176.08:22:12.21#ibcon#enter sib2, iclass 25, count 0 2006.176.08:22:12.21#ibcon#flushed, iclass 25, count 0 2006.176.08:22:12.21#ibcon#about to write, iclass 25, count 0 2006.176.08:22:12.21#ibcon#wrote, iclass 25, count 0 2006.176.08:22:12.21#ibcon#about to read 3, iclass 25, count 0 2006.176.08:22:12.24#ibcon#read 3, iclass 25, count 0 2006.176.08:22:12.24#ibcon#about to read 4, iclass 25, count 0 2006.176.08:22:12.24#ibcon#read 4, iclass 25, count 0 2006.176.08:22:12.24#ibcon#about to read 5, iclass 25, count 0 2006.176.08:22:12.24#ibcon#read 5, iclass 25, count 0 2006.176.08:22:12.24#ibcon#about to read 6, iclass 25, count 0 2006.176.08:22:12.24#ibcon#read 6, iclass 25, count 0 2006.176.08:22:12.24#ibcon#end of sib2, iclass 25, count 0 2006.176.08:22:12.24#ibcon#*after write, iclass 25, count 0 2006.176.08:22:12.24#ibcon#*before return 0, iclass 25, count 0 2006.176.08:22:12.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:12.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:22:12.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:22:12.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:22:12.24$vc4f8/vblo=6,752.99 2006.176.08:22:12.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.176.08:22:12.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.176.08:22:12.24#ibcon#ireg 17 cls_cnt 0 2006.176.08:22:12.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:12.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:12.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:12.24#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:22:12.24#ibcon#first serial, iclass 27, count 0 2006.176.08:22:12.24#ibcon#enter sib2, iclass 27, count 0 2006.176.08:22:12.24#ibcon#flushed, iclass 27, count 0 2006.176.08:22:12.24#ibcon#about to write, iclass 27, count 0 2006.176.08:22:12.24#ibcon#wrote, iclass 27, count 0 2006.176.08:22:12.24#ibcon#about to read 3, iclass 27, count 0 2006.176.08:22:12.26#ibcon#read 3, iclass 27, count 0 2006.176.08:22:12.26#ibcon#about to read 4, iclass 27, count 0 2006.176.08:22:12.26#ibcon#read 4, iclass 27, count 0 2006.176.08:22:12.26#ibcon#about to read 5, iclass 27, count 0 2006.176.08:22:12.26#ibcon#read 5, iclass 27, count 0 2006.176.08:22:12.26#ibcon#about to read 6, iclass 27, count 0 2006.176.08:22:12.26#ibcon#read 6, iclass 27, count 0 2006.176.08:22:12.26#ibcon#end of sib2, iclass 27, count 0 2006.176.08:22:12.26#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:22:12.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:22:12.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:22:12.26#ibcon#*before write, iclass 27, count 0 2006.176.08:22:12.26#ibcon#enter sib2, iclass 27, count 0 2006.176.08:22:12.26#ibcon#flushed, iclass 27, count 0 2006.176.08:22:12.26#ibcon#about to write, iclass 27, count 0 2006.176.08:22:12.26#ibcon#wrote, iclass 27, count 0 2006.176.08:22:12.26#ibcon#about to read 3, iclass 27, count 0 2006.176.08:22:12.30#ibcon#read 3, iclass 27, count 0 2006.176.08:22:12.30#ibcon#about to read 4, iclass 27, count 0 2006.176.08:22:12.30#ibcon#read 4, iclass 27, count 0 2006.176.08:22:12.30#ibcon#about to read 5, iclass 27, count 0 2006.176.08:22:12.30#ibcon#read 5, iclass 27, count 0 2006.176.08:22:12.30#ibcon#about to read 6, iclass 27, count 0 2006.176.08:22:12.30#ibcon#read 6, iclass 27, count 0 2006.176.08:22:12.30#ibcon#end of sib2, iclass 27, count 0 2006.176.08:22:12.30#ibcon#*after write, iclass 27, count 0 2006.176.08:22:12.30#ibcon#*before return 0, iclass 27, count 0 2006.176.08:22:12.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:12.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.176.08:22:12.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:22:12.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:22:12.30$vc4f8/vb=6,4 2006.176.08:22:12.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.176.08:22:12.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.176.08:22:12.30#ibcon#ireg 11 cls_cnt 2 2006.176.08:22:12.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:12.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:12.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:12.36#ibcon#enter wrdev, iclass 29, count 2 2006.176.08:22:12.36#ibcon#first serial, iclass 29, count 2 2006.176.08:22:12.36#ibcon#enter sib2, iclass 29, count 2 2006.176.08:22:12.36#ibcon#flushed, iclass 29, count 2 2006.176.08:22:12.36#ibcon#about to write, iclass 29, count 2 2006.176.08:22:12.36#ibcon#wrote, iclass 29, count 2 2006.176.08:22:12.36#ibcon#about to read 3, iclass 29, count 2 2006.176.08:22:12.38#ibcon#read 3, iclass 29, count 2 2006.176.08:22:12.38#ibcon#about to read 4, iclass 29, count 2 2006.176.08:22:12.38#ibcon#read 4, iclass 29, count 2 2006.176.08:22:12.38#ibcon#about to read 5, iclass 29, count 2 2006.176.08:22:12.38#ibcon#read 5, iclass 29, count 2 2006.176.08:22:12.38#ibcon#about to read 6, iclass 29, count 2 2006.176.08:22:12.38#ibcon#read 6, iclass 29, count 2 2006.176.08:22:12.38#ibcon#end of sib2, iclass 29, count 2 2006.176.08:22:12.38#ibcon#*mode == 0, iclass 29, count 2 2006.176.08:22:12.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.176.08:22:12.38#ibcon#[27=AT06-04\r\n] 2006.176.08:22:12.38#ibcon#*before write, iclass 29, count 2 2006.176.08:22:12.38#ibcon#enter sib2, iclass 29, count 2 2006.176.08:22:12.38#ibcon#flushed, iclass 29, count 2 2006.176.08:22:12.38#ibcon#about to write, iclass 29, count 2 2006.176.08:22:12.38#ibcon#wrote, iclass 29, count 2 2006.176.08:22:12.38#ibcon#about to read 3, iclass 29, count 2 2006.176.08:22:12.41#ibcon#read 3, iclass 29, count 2 2006.176.08:22:12.41#ibcon#about to read 4, iclass 29, count 2 2006.176.08:22:12.41#ibcon#read 4, iclass 29, count 2 2006.176.08:22:12.41#ibcon#about to read 5, iclass 29, count 2 2006.176.08:22:12.41#ibcon#read 5, iclass 29, count 2 2006.176.08:22:12.41#ibcon#about to read 6, iclass 29, count 2 2006.176.08:22:12.41#ibcon#read 6, iclass 29, count 2 2006.176.08:22:12.41#ibcon#end of sib2, iclass 29, count 2 2006.176.08:22:12.41#ibcon#*after write, iclass 29, count 2 2006.176.08:22:12.41#ibcon#*before return 0, iclass 29, count 2 2006.176.08:22:12.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:12.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.176.08:22:12.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.176.08:22:12.41#ibcon#ireg 7 cls_cnt 0 2006.176.08:22:12.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:12.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:12.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:12.53#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:22:12.53#ibcon#first serial, iclass 29, count 0 2006.176.08:22:12.53#ibcon#enter sib2, iclass 29, count 0 2006.176.08:22:12.53#ibcon#flushed, iclass 29, count 0 2006.176.08:22:12.53#ibcon#about to write, iclass 29, count 0 2006.176.08:22:12.53#ibcon#wrote, iclass 29, count 0 2006.176.08:22:12.53#ibcon#about to read 3, iclass 29, count 0 2006.176.08:22:12.55#ibcon#read 3, iclass 29, count 0 2006.176.08:22:12.55#ibcon#about to read 4, iclass 29, count 0 2006.176.08:22:12.55#ibcon#read 4, iclass 29, count 0 2006.176.08:22:12.55#ibcon#about to read 5, iclass 29, count 0 2006.176.08:22:12.55#ibcon#read 5, iclass 29, count 0 2006.176.08:22:12.55#ibcon#about to read 6, iclass 29, count 0 2006.176.08:22:12.55#ibcon#read 6, iclass 29, count 0 2006.176.08:22:12.55#ibcon#end of sib2, iclass 29, count 0 2006.176.08:22:12.55#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:22:12.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:22:12.55#ibcon#[27=USB\r\n] 2006.176.08:22:12.55#ibcon#*before write, iclass 29, count 0 2006.176.08:22:12.55#ibcon#enter sib2, iclass 29, count 0 2006.176.08:22:12.55#ibcon#flushed, iclass 29, count 0 2006.176.08:22:12.55#ibcon#about to write, iclass 29, count 0 2006.176.08:22:12.55#ibcon#wrote, iclass 29, count 0 2006.176.08:22:12.55#ibcon#about to read 3, iclass 29, count 0 2006.176.08:22:12.58#ibcon#read 3, iclass 29, count 0 2006.176.08:22:12.58#ibcon#about to read 4, iclass 29, count 0 2006.176.08:22:12.58#ibcon#read 4, iclass 29, count 0 2006.176.08:22:12.58#ibcon#about to read 5, iclass 29, count 0 2006.176.08:22:12.58#ibcon#read 5, iclass 29, count 0 2006.176.08:22:12.58#ibcon#about to read 6, iclass 29, count 0 2006.176.08:22:12.58#ibcon#read 6, iclass 29, count 0 2006.176.08:22:12.58#ibcon#end of sib2, iclass 29, count 0 2006.176.08:22:12.58#ibcon#*after write, iclass 29, count 0 2006.176.08:22:12.58#ibcon#*before return 0, iclass 29, count 0 2006.176.08:22:12.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:12.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.176.08:22:12.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:22:12.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:22:12.58$vc4f8/vabw=wide 2006.176.08:22:12.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.08:22:12.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.08:22:12.58#ibcon#ireg 8 cls_cnt 0 2006.176.08:22:12.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:12.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:12.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:12.58#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:22:12.58#ibcon#first serial, iclass 31, count 0 2006.176.08:22:12.58#ibcon#enter sib2, iclass 31, count 0 2006.176.08:22:12.58#ibcon#flushed, iclass 31, count 0 2006.176.08:22:12.58#ibcon#about to write, iclass 31, count 0 2006.176.08:22:12.58#ibcon#wrote, iclass 31, count 0 2006.176.08:22:12.58#ibcon#about to read 3, iclass 31, count 0 2006.176.08:22:12.60#ibcon#read 3, iclass 31, count 0 2006.176.08:22:12.60#ibcon#about to read 4, iclass 31, count 0 2006.176.08:22:12.60#ibcon#read 4, iclass 31, count 0 2006.176.08:22:12.60#ibcon#about to read 5, iclass 31, count 0 2006.176.08:22:12.60#ibcon#read 5, iclass 31, count 0 2006.176.08:22:12.60#ibcon#about to read 6, iclass 31, count 0 2006.176.08:22:12.60#ibcon#read 6, iclass 31, count 0 2006.176.08:22:12.60#ibcon#end of sib2, iclass 31, count 0 2006.176.08:22:12.60#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:22:12.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:22:12.60#ibcon#[25=BW32\r\n] 2006.176.08:22:12.60#ibcon#*before write, iclass 31, count 0 2006.176.08:22:12.60#ibcon#enter sib2, iclass 31, count 0 2006.176.08:22:12.60#ibcon#flushed, iclass 31, count 0 2006.176.08:22:12.60#ibcon#about to write, iclass 31, count 0 2006.176.08:22:12.60#ibcon#wrote, iclass 31, count 0 2006.176.08:22:12.60#ibcon#about to read 3, iclass 31, count 0 2006.176.08:22:12.63#ibcon#read 3, iclass 31, count 0 2006.176.08:22:12.63#ibcon#about to read 4, iclass 31, count 0 2006.176.08:22:12.63#ibcon#read 4, iclass 31, count 0 2006.176.08:22:12.63#ibcon#about to read 5, iclass 31, count 0 2006.176.08:22:12.63#ibcon#read 5, iclass 31, count 0 2006.176.08:22:12.63#ibcon#about to read 6, iclass 31, count 0 2006.176.08:22:12.63#ibcon#read 6, iclass 31, count 0 2006.176.08:22:12.63#ibcon#end of sib2, iclass 31, count 0 2006.176.08:22:12.63#ibcon#*after write, iclass 31, count 0 2006.176.08:22:12.63#ibcon#*before return 0, iclass 31, count 0 2006.176.08:22:12.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:12.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:22:12.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:22:12.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:22:12.63$vc4f8/vbbw=wide 2006.176.08:22:12.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.08:22:12.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.08:22:12.63#ibcon#ireg 8 cls_cnt 0 2006.176.08:22:12.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:22:12.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:22:12.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:22:12.70#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:22:12.70#ibcon#first serial, iclass 33, count 0 2006.176.08:22:12.70#ibcon#enter sib2, iclass 33, count 0 2006.176.08:22:12.70#ibcon#flushed, iclass 33, count 0 2006.176.08:22:12.70#ibcon#about to write, iclass 33, count 0 2006.176.08:22:12.70#ibcon#wrote, iclass 33, count 0 2006.176.08:22:12.70#ibcon#about to read 3, iclass 33, count 0 2006.176.08:22:12.72#ibcon#read 3, iclass 33, count 0 2006.176.08:22:12.72#ibcon#about to read 4, iclass 33, count 0 2006.176.08:22:12.72#ibcon#read 4, iclass 33, count 0 2006.176.08:22:12.72#ibcon#about to read 5, iclass 33, count 0 2006.176.08:22:12.72#ibcon#read 5, iclass 33, count 0 2006.176.08:22:12.72#ibcon#about to read 6, iclass 33, count 0 2006.176.08:22:12.72#ibcon#read 6, iclass 33, count 0 2006.176.08:22:12.72#ibcon#end of sib2, iclass 33, count 0 2006.176.08:22:12.72#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:22:12.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:22:12.72#ibcon#[27=BW32\r\n] 2006.176.08:22:12.72#ibcon#*before write, iclass 33, count 0 2006.176.08:22:12.72#ibcon#enter sib2, iclass 33, count 0 2006.176.08:22:12.72#ibcon#flushed, iclass 33, count 0 2006.176.08:22:12.72#ibcon#about to write, iclass 33, count 0 2006.176.08:22:12.72#ibcon#wrote, iclass 33, count 0 2006.176.08:22:12.72#ibcon#about to read 3, iclass 33, count 0 2006.176.08:22:12.75#ibcon#read 3, iclass 33, count 0 2006.176.08:22:12.75#ibcon#about to read 4, iclass 33, count 0 2006.176.08:22:12.75#ibcon#read 4, iclass 33, count 0 2006.176.08:22:12.75#ibcon#about to read 5, iclass 33, count 0 2006.176.08:22:12.75#ibcon#read 5, iclass 33, count 0 2006.176.08:22:12.75#ibcon#about to read 6, iclass 33, count 0 2006.176.08:22:12.75#ibcon#read 6, iclass 33, count 0 2006.176.08:22:12.75#ibcon#end of sib2, iclass 33, count 0 2006.176.08:22:12.75#ibcon#*after write, iclass 33, count 0 2006.176.08:22:12.75#ibcon#*before return 0, iclass 33, count 0 2006.176.08:22:12.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:22:12.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:22:12.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:22:12.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:22:12.75$4f8m12a/ifd4f 2006.176.08:22:12.75$ifd4f/lo= 2006.176.08:22:12.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:22:12.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:22:12.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:22:12.75$ifd4f/patch= 2006.176.08:22:12.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:22:12.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:22:12.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:22:12.75$4f8m12a/"form=m,16.000,1:2 2006.176.08:22:12.75$4f8m12a/"tpicd 2006.176.08:22:12.75$4f8m12a/echo=off 2006.176.08:22:12.75$4f8m12a/xlog=off 2006.176.08:22:12.75:!2006.176.08:24:20 2006.176.08:22:41.13#trakl#Source acquired 2006.176.08:22:42.13#flagr#flagr/antenna,acquired 2006.176.08:24:20.00:preob 2006.176.08:24:20.13/onsource/TRACKING 2006.176.08:24:20.13:!2006.176.08:24:30 2006.176.08:24:30.00:data_valid=on 2006.176.08:24:30.00:midob 2006.176.08:24:30.13/onsource/TRACKING 2006.176.08:24:30.13/wx/23.75,1008.5,92 2006.176.08:24:30.32/cable/+6.4943E-03 2006.176.08:24:31.41/va/01,08,usb,yes,29,31 2006.176.08:24:31.41/va/02,07,usb,yes,30,31 2006.176.08:24:31.41/va/03,06,usb,yes,31,31 2006.176.08:24:31.41/va/04,07,usb,yes,30,33 2006.176.08:24:31.41/va/05,07,usb,yes,32,34 2006.176.08:24:31.41/va/06,06,usb,yes,31,31 2006.176.08:24:31.41/va/07,06,usb,yes,31,31 2006.176.08:24:31.41/va/08,06,usb,yes,34,33 2006.176.08:24:31.64/valo/01,532.99,yes,locked 2006.176.08:24:31.64/valo/02,572.99,yes,locked 2006.176.08:24:31.64/valo/03,672.99,yes,locked 2006.176.08:24:31.64/valo/04,832.99,yes,locked 2006.176.08:24:31.64/valo/05,652.99,yes,locked 2006.176.08:24:31.64/valo/06,772.99,yes,locked 2006.176.08:24:31.64/valo/07,832.99,yes,locked 2006.176.08:24:31.64/valo/08,852.99,yes,locked 2006.176.08:24:32.73/vb/01,04,usb,yes,29,28 2006.176.08:24:32.73/vb/02,04,usb,yes,31,32 2006.176.08:24:32.73/vb/03,04,usb,yes,27,31 2006.176.08:24:32.73/vb/04,04,usb,yes,28,28 2006.176.08:24:32.73/vb/05,04,usb,yes,27,31 2006.176.08:24:32.73/vb/06,04,usb,yes,28,30 2006.176.08:24:32.73/vb/07,04,usb,yes,30,30 2006.176.08:24:32.73/vb/08,04,usb,yes,27,31 2006.176.08:24:32.97/vblo/01,632.99,yes,locked 2006.176.08:24:32.97/vblo/02,640.99,yes,locked 2006.176.08:24:32.97/vblo/03,656.99,yes,locked 2006.176.08:24:32.97/vblo/04,712.99,yes,locked 2006.176.08:24:32.97/vblo/05,744.99,yes,locked 2006.176.08:24:32.97/vblo/06,752.99,yes,locked 2006.176.08:24:32.97/vblo/07,734.99,yes,locked 2006.176.08:24:32.97/vblo/08,744.99,yes,locked 2006.176.08:24:33.12/vabw/8 2006.176.08:24:33.27/vbbw/8 2006.176.08:24:33.36/xfe/off,on,15.2 2006.176.08:24:33.74/ifatt/23,28,28,28 2006.176.08:24:34.08/fmout-gps/S +3.70E-07 2006.176.08:24:34.15:!2006.176.08:25:30 2006.176.08:25:30.00:data_valid=off 2006.176.08:25:30.00:postob 2006.176.08:25:30.09/cable/+6.4938E-03 2006.176.08:25:30.09/wx/23.74,1008.5,92 2006.176.08:25:31.08/fmout-gps/S +3.69E-07 2006.176.08:25:31.08:scan_name=176-0826,k06176,60 2006.176.08:25:31.08:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.176.08:25:31.14#flagr#flagr/antenna,new-source 2006.176.08:25:32.14:checkk5 2006.176.08:25:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:25:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:25:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:25:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:25:34.03/chk_obsdata//k5ts1/T1760824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:25:34.40/chk_obsdata//k5ts2/T1760824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:25:34.77/chk_obsdata//k5ts3/T1760824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:25:35.15/chk_obsdata//k5ts4/T1760824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.176.08:25:35.85/k5log//k5ts1_log_newline 2006.176.08:25:36.54/k5log//k5ts2_log_newline 2006.176.08:25:37.23/k5log//k5ts3_log_newline 2006.176.08:25:37.91/k5log//k5ts4_log_newline 2006.176.08:25:37.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:25:37.94:4f8m12a=3 2006.176.08:25:37.94$4f8m12a/echo=on 2006.176.08:25:37.94$4f8m12a/pcalon 2006.176.08:25:37.94$pcalon/"no phase cal control is implemented here 2006.176.08:25:37.94$4f8m12a/"tpicd=stop 2006.176.08:25:37.94$4f8m12a/vc4f8 2006.176.08:25:37.94$vc4f8/valo=1,532.99 2006.176.08:25:37.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.08:25:37.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.08:25:37.94#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:37.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:37.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:37.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:37.94#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:25:37.94#ibcon#first serial, iclass 6, count 0 2006.176.08:25:37.94#ibcon#enter sib2, iclass 6, count 0 2006.176.08:25:37.94#ibcon#flushed, iclass 6, count 0 2006.176.08:25:37.94#ibcon#about to write, iclass 6, count 0 2006.176.08:25:37.94#ibcon#wrote, iclass 6, count 0 2006.176.08:25:37.94#ibcon#about to read 3, iclass 6, count 0 2006.176.08:25:37.96#ibcon#read 3, iclass 6, count 0 2006.176.08:25:37.96#ibcon#about to read 4, iclass 6, count 0 2006.176.08:25:37.96#ibcon#read 4, iclass 6, count 0 2006.176.08:25:37.96#ibcon#about to read 5, iclass 6, count 0 2006.176.08:25:37.96#ibcon#read 5, iclass 6, count 0 2006.176.08:25:37.96#ibcon#about to read 6, iclass 6, count 0 2006.176.08:25:37.96#ibcon#read 6, iclass 6, count 0 2006.176.08:25:37.96#ibcon#end of sib2, iclass 6, count 0 2006.176.08:25:37.96#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:25:37.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:25:37.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:25:37.96#ibcon#*before write, iclass 6, count 0 2006.176.08:25:37.96#ibcon#enter sib2, iclass 6, count 0 2006.176.08:25:37.96#ibcon#flushed, iclass 6, count 0 2006.176.08:25:37.96#ibcon#about to write, iclass 6, count 0 2006.176.08:25:37.96#ibcon#wrote, iclass 6, count 0 2006.176.08:25:37.96#ibcon#about to read 3, iclass 6, count 0 2006.176.08:25:38.01#ibcon#read 3, iclass 6, count 0 2006.176.08:25:38.01#ibcon#about to read 4, iclass 6, count 0 2006.176.08:25:38.01#ibcon#read 4, iclass 6, count 0 2006.176.08:25:38.01#ibcon#about to read 5, iclass 6, count 0 2006.176.08:25:38.01#ibcon#read 5, iclass 6, count 0 2006.176.08:25:38.01#ibcon#about to read 6, iclass 6, count 0 2006.176.08:25:38.01#ibcon#read 6, iclass 6, count 0 2006.176.08:25:38.01#ibcon#end of sib2, iclass 6, count 0 2006.176.08:25:38.01#ibcon#*after write, iclass 6, count 0 2006.176.08:25:38.01#ibcon#*before return 0, iclass 6, count 0 2006.176.08:25:38.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:38.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:38.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:25:38.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:25:38.01$vc4f8/va=1,8 2006.176.08:25:38.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.08:25:38.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.08:25:38.01#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:38.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:38.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:38.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:38.01#ibcon#enter wrdev, iclass 10, count 2 2006.176.08:25:38.01#ibcon#first serial, iclass 10, count 2 2006.176.08:25:38.01#ibcon#enter sib2, iclass 10, count 2 2006.176.08:25:38.01#ibcon#flushed, iclass 10, count 2 2006.176.08:25:38.01#ibcon#about to write, iclass 10, count 2 2006.176.08:25:38.01#ibcon#wrote, iclass 10, count 2 2006.176.08:25:38.01#ibcon#about to read 3, iclass 10, count 2 2006.176.08:25:38.03#ibcon#read 3, iclass 10, count 2 2006.176.08:25:38.03#ibcon#about to read 4, iclass 10, count 2 2006.176.08:25:38.03#ibcon#read 4, iclass 10, count 2 2006.176.08:25:38.03#ibcon#about to read 5, iclass 10, count 2 2006.176.08:25:38.03#ibcon#read 5, iclass 10, count 2 2006.176.08:25:38.03#ibcon#about to read 6, iclass 10, count 2 2006.176.08:25:38.03#ibcon#read 6, iclass 10, count 2 2006.176.08:25:38.03#ibcon#end of sib2, iclass 10, count 2 2006.176.08:25:38.03#ibcon#*mode == 0, iclass 10, count 2 2006.176.08:25:38.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.08:25:38.03#ibcon#[25=AT01-08\r\n] 2006.176.08:25:38.03#ibcon#*before write, iclass 10, count 2 2006.176.08:25:38.03#ibcon#enter sib2, iclass 10, count 2 2006.176.08:25:38.03#ibcon#flushed, iclass 10, count 2 2006.176.08:25:38.03#ibcon#about to write, iclass 10, count 2 2006.176.08:25:38.03#ibcon#wrote, iclass 10, count 2 2006.176.08:25:38.03#ibcon#about to read 3, iclass 10, count 2 2006.176.08:25:38.06#ibcon#read 3, iclass 10, count 2 2006.176.08:25:38.06#ibcon#about to read 4, iclass 10, count 2 2006.176.08:25:38.06#ibcon#read 4, iclass 10, count 2 2006.176.08:25:38.06#ibcon#about to read 5, iclass 10, count 2 2006.176.08:25:38.06#ibcon#read 5, iclass 10, count 2 2006.176.08:25:38.06#ibcon#about to read 6, iclass 10, count 2 2006.176.08:25:38.06#ibcon#read 6, iclass 10, count 2 2006.176.08:25:38.06#ibcon#end of sib2, iclass 10, count 2 2006.176.08:25:38.06#ibcon#*after write, iclass 10, count 2 2006.176.08:25:38.06#ibcon#*before return 0, iclass 10, count 2 2006.176.08:25:38.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:38.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:38.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.08:25:38.06#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:38.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:38.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:38.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:38.18#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:25:38.18#ibcon#first serial, iclass 10, count 0 2006.176.08:25:38.18#ibcon#enter sib2, iclass 10, count 0 2006.176.08:25:38.18#ibcon#flushed, iclass 10, count 0 2006.176.08:25:38.18#ibcon#about to write, iclass 10, count 0 2006.176.08:25:38.18#ibcon#wrote, iclass 10, count 0 2006.176.08:25:38.18#ibcon#about to read 3, iclass 10, count 0 2006.176.08:25:38.20#ibcon#read 3, iclass 10, count 0 2006.176.08:25:38.20#ibcon#about to read 4, iclass 10, count 0 2006.176.08:25:38.20#ibcon#read 4, iclass 10, count 0 2006.176.08:25:38.20#ibcon#about to read 5, iclass 10, count 0 2006.176.08:25:38.20#ibcon#read 5, iclass 10, count 0 2006.176.08:25:38.20#ibcon#about to read 6, iclass 10, count 0 2006.176.08:25:38.20#ibcon#read 6, iclass 10, count 0 2006.176.08:25:38.20#ibcon#end of sib2, iclass 10, count 0 2006.176.08:25:38.20#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:25:38.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:25:38.20#ibcon#[25=USB\r\n] 2006.176.08:25:38.20#ibcon#*before write, iclass 10, count 0 2006.176.08:25:38.20#ibcon#enter sib2, iclass 10, count 0 2006.176.08:25:38.20#ibcon#flushed, iclass 10, count 0 2006.176.08:25:38.20#ibcon#about to write, iclass 10, count 0 2006.176.08:25:38.20#ibcon#wrote, iclass 10, count 0 2006.176.08:25:38.20#ibcon#about to read 3, iclass 10, count 0 2006.176.08:25:38.23#ibcon#read 3, iclass 10, count 0 2006.176.08:25:38.23#ibcon#about to read 4, iclass 10, count 0 2006.176.08:25:38.23#ibcon#read 4, iclass 10, count 0 2006.176.08:25:38.23#ibcon#about to read 5, iclass 10, count 0 2006.176.08:25:38.23#ibcon#read 5, iclass 10, count 0 2006.176.08:25:38.23#ibcon#about to read 6, iclass 10, count 0 2006.176.08:25:38.23#ibcon#read 6, iclass 10, count 0 2006.176.08:25:38.23#ibcon#end of sib2, iclass 10, count 0 2006.176.08:25:38.23#ibcon#*after write, iclass 10, count 0 2006.176.08:25:38.23#ibcon#*before return 0, iclass 10, count 0 2006.176.08:25:38.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:38.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:38.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:25:38.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:25:38.23$vc4f8/valo=2,572.99 2006.176.08:25:38.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.08:25:38.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.08:25:38.23#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:38.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:38.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:38.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:38.23#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:25:38.23#ibcon#first serial, iclass 12, count 0 2006.176.08:25:38.23#ibcon#enter sib2, iclass 12, count 0 2006.176.08:25:38.23#ibcon#flushed, iclass 12, count 0 2006.176.08:25:38.23#ibcon#about to write, iclass 12, count 0 2006.176.08:25:38.23#ibcon#wrote, iclass 12, count 0 2006.176.08:25:38.23#ibcon#about to read 3, iclass 12, count 0 2006.176.08:25:38.25#ibcon#read 3, iclass 12, count 0 2006.176.08:25:38.25#ibcon#about to read 4, iclass 12, count 0 2006.176.08:25:38.25#ibcon#read 4, iclass 12, count 0 2006.176.08:25:38.25#ibcon#about to read 5, iclass 12, count 0 2006.176.08:25:38.25#ibcon#read 5, iclass 12, count 0 2006.176.08:25:38.25#ibcon#about to read 6, iclass 12, count 0 2006.176.08:25:38.25#ibcon#read 6, iclass 12, count 0 2006.176.08:25:38.25#ibcon#end of sib2, iclass 12, count 0 2006.176.08:25:38.25#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:25:38.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:25:38.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:25:38.25#ibcon#*before write, iclass 12, count 0 2006.176.08:25:38.25#ibcon#enter sib2, iclass 12, count 0 2006.176.08:25:38.25#ibcon#flushed, iclass 12, count 0 2006.176.08:25:38.25#ibcon#about to write, iclass 12, count 0 2006.176.08:25:38.25#ibcon#wrote, iclass 12, count 0 2006.176.08:25:38.25#ibcon#about to read 3, iclass 12, count 0 2006.176.08:25:38.29#ibcon#read 3, iclass 12, count 0 2006.176.08:25:38.29#ibcon#about to read 4, iclass 12, count 0 2006.176.08:25:38.29#ibcon#read 4, iclass 12, count 0 2006.176.08:25:38.29#ibcon#about to read 5, iclass 12, count 0 2006.176.08:25:38.29#ibcon#read 5, iclass 12, count 0 2006.176.08:25:38.29#ibcon#about to read 6, iclass 12, count 0 2006.176.08:25:38.29#ibcon#read 6, iclass 12, count 0 2006.176.08:25:38.29#ibcon#end of sib2, iclass 12, count 0 2006.176.08:25:38.29#ibcon#*after write, iclass 12, count 0 2006.176.08:25:38.29#ibcon#*before return 0, iclass 12, count 0 2006.176.08:25:38.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:38.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:38.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:25:38.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:25:38.29$vc4f8/va=2,7 2006.176.08:25:38.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.08:25:38.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.08:25:38.29#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:38.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:38.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:38.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:38.35#ibcon#enter wrdev, iclass 14, count 2 2006.176.08:25:38.35#ibcon#first serial, iclass 14, count 2 2006.176.08:25:38.35#ibcon#enter sib2, iclass 14, count 2 2006.176.08:25:38.35#ibcon#flushed, iclass 14, count 2 2006.176.08:25:38.35#ibcon#about to write, iclass 14, count 2 2006.176.08:25:38.35#ibcon#wrote, iclass 14, count 2 2006.176.08:25:38.35#ibcon#about to read 3, iclass 14, count 2 2006.176.08:25:38.37#ibcon#read 3, iclass 14, count 2 2006.176.08:25:38.37#ibcon#about to read 4, iclass 14, count 2 2006.176.08:25:38.37#ibcon#read 4, iclass 14, count 2 2006.176.08:25:38.37#ibcon#about to read 5, iclass 14, count 2 2006.176.08:25:38.37#ibcon#read 5, iclass 14, count 2 2006.176.08:25:38.37#ibcon#about to read 6, iclass 14, count 2 2006.176.08:25:38.37#ibcon#read 6, iclass 14, count 2 2006.176.08:25:38.37#ibcon#end of sib2, iclass 14, count 2 2006.176.08:25:38.37#ibcon#*mode == 0, iclass 14, count 2 2006.176.08:25:38.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.08:25:38.37#ibcon#[25=AT02-07\r\n] 2006.176.08:25:38.37#ibcon#*before write, iclass 14, count 2 2006.176.08:25:38.37#ibcon#enter sib2, iclass 14, count 2 2006.176.08:25:38.37#ibcon#flushed, iclass 14, count 2 2006.176.08:25:38.37#ibcon#about to write, iclass 14, count 2 2006.176.08:25:38.37#ibcon#wrote, iclass 14, count 2 2006.176.08:25:38.37#ibcon#about to read 3, iclass 14, count 2 2006.176.08:25:38.40#ibcon#read 3, iclass 14, count 2 2006.176.08:25:38.40#ibcon#about to read 4, iclass 14, count 2 2006.176.08:25:38.40#ibcon#read 4, iclass 14, count 2 2006.176.08:25:38.40#ibcon#about to read 5, iclass 14, count 2 2006.176.08:25:38.40#ibcon#read 5, iclass 14, count 2 2006.176.08:25:38.40#ibcon#about to read 6, iclass 14, count 2 2006.176.08:25:38.40#ibcon#read 6, iclass 14, count 2 2006.176.08:25:38.40#ibcon#end of sib2, iclass 14, count 2 2006.176.08:25:38.40#ibcon#*after write, iclass 14, count 2 2006.176.08:25:38.40#ibcon#*before return 0, iclass 14, count 2 2006.176.08:25:38.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:38.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:38.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.08:25:38.40#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:38.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:38.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:38.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:38.52#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:25:38.52#ibcon#first serial, iclass 14, count 0 2006.176.08:25:38.52#ibcon#enter sib2, iclass 14, count 0 2006.176.08:25:38.52#ibcon#flushed, iclass 14, count 0 2006.176.08:25:38.52#ibcon#about to write, iclass 14, count 0 2006.176.08:25:38.52#ibcon#wrote, iclass 14, count 0 2006.176.08:25:38.52#ibcon#about to read 3, iclass 14, count 0 2006.176.08:25:38.54#ibcon#read 3, iclass 14, count 0 2006.176.08:25:38.54#ibcon#about to read 4, iclass 14, count 0 2006.176.08:25:38.54#ibcon#read 4, iclass 14, count 0 2006.176.08:25:38.54#ibcon#about to read 5, iclass 14, count 0 2006.176.08:25:38.54#ibcon#read 5, iclass 14, count 0 2006.176.08:25:38.54#ibcon#about to read 6, iclass 14, count 0 2006.176.08:25:38.54#ibcon#read 6, iclass 14, count 0 2006.176.08:25:38.54#ibcon#end of sib2, iclass 14, count 0 2006.176.08:25:38.54#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:25:38.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:25:38.54#ibcon#[25=USB\r\n] 2006.176.08:25:38.54#ibcon#*before write, iclass 14, count 0 2006.176.08:25:38.54#ibcon#enter sib2, iclass 14, count 0 2006.176.08:25:38.54#ibcon#flushed, iclass 14, count 0 2006.176.08:25:38.54#ibcon#about to write, iclass 14, count 0 2006.176.08:25:38.54#ibcon#wrote, iclass 14, count 0 2006.176.08:25:38.54#ibcon#about to read 3, iclass 14, count 0 2006.176.08:25:38.57#ibcon#read 3, iclass 14, count 0 2006.176.08:25:38.57#ibcon#about to read 4, iclass 14, count 0 2006.176.08:25:38.57#ibcon#read 4, iclass 14, count 0 2006.176.08:25:38.57#ibcon#about to read 5, iclass 14, count 0 2006.176.08:25:38.57#ibcon#read 5, iclass 14, count 0 2006.176.08:25:38.57#ibcon#about to read 6, iclass 14, count 0 2006.176.08:25:38.57#ibcon#read 6, iclass 14, count 0 2006.176.08:25:38.57#ibcon#end of sib2, iclass 14, count 0 2006.176.08:25:38.57#ibcon#*after write, iclass 14, count 0 2006.176.08:25:38.57#ibcon#*before return 0, iclass 14, count 0 2006.176.08:25:38.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:38.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:38.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:25:38.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:25:38.57$vc4f8/valo=3,672.99 2006.176.08:25:38.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.08:25:38.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.08:25:38.57#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:38.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:38.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:38.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:38.57#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:25:38.57#ibcon#first serial, iclass 16, count 0 2006.176.08:25:38.57#ibcon#enter sib2, iclass 16, count 0 2006.176.08:25:38.57#ibcon#flushed, iclass 16, count 0 2006.176.08:25:38.57#ibcon#about to write, iclass 16, count 0 2006.176.08:25:38.57#ibcon#wrote, iclass 16, count 0 2006.176.08:25:38.57#ibcon#about to read 3, iclass 16, count 0 2006.176.08:25:38.59#ibcon#read 3, iclass 16, count 0 2006.176.08:25:38.59#ibcon#about to read 4, iclass 16, count 0 2006.176.08:25:38.59#ibcon#read 4, iclass 16, count 0 2006.176.08:25:38.59#ibcon#about to read 5, iclass 16, count 0 2006.176.08:25:38.59#ibcon#read 5, iclass 16, count 0 2006.176.08:25:38.59#ibcon#about to read 6, iclass 16, count 0 2006.176.08:25:38.59#ibcon#read 6, iclass 16, count 0 2006.176.08:25:38.59#ibcon#end of sib2, iclass 16, count 0 2006.176.08:25:38.59#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:25:38.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:25:38.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:25:38.59#ibcon#*before write, iclass 16, count 0 2006.176.08:25:38.59#ibcon#enter sib2, iclass 16, count 0 2006.176.08:25:38.59#ibcon#flushed, iclass 16, count 0 2006.176.08:25:38.59#ibcon#about to write, iclass 16, count 0 2006.176.08:25:38.59#ibcon#wrote, iclass 16, count 0 2006.176.08:25:38.59#ibcon#about to read 3, iclass 16, count 0 2006.176.08:25:38.63#ibcon#read 3, iclass 16, count 0 2006.176.08:25:38.63#ibcon#about to read 4, iclass 16, count 0 2006.176.08:25:38.63#ibcon#read 4, iclass 16, count 0 2006.176.08:25:38.63#ibcon#about to read 5, iclass 16, count 0 2006.176.08:25:38.63#ibcon#read 5, iclass 16, count 0 2006.176.08:25:38.63#ibcon#about to read 6, iclass 16, count 0 2006.176.08:25:38.63#ibcon#read 6, iclass 16, count 0 2006.176.08:25:38.63#ibcon#end of sib2, iclass 16, count 0 2006.176.08:25:38.63#ibcon#*after write, iclass 16, count 0 2006.176.08:25:38.63#ibcon#*before return 0, iclass 16, count 0 2006.176.08:25:38.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:38.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:38.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:25:38.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:25:38.63$vc4f8/va=3,6 2006.176.08:25:38.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.08:25:38.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.08:25:38.63#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:38.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:38.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:38.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:38.69#ibcon#enter wrdev, iclass 18, count 2 2006.176.08:25:38.69#ibcon#first serial, iclass 18, count 2 2006.176.08:25:38.69#ibcon#enter sib2, iclass 18, count 2 2006.176.08:25:38.69#ibcon#flushed, iclass 18, count 2 2006.176.08:25:38.69#ibcon#about to write, iclass 18, count 2 2006.176.08:25:38.69#ibcon#wrote, iclass 18, count 2 2006.176.08:25:38.69#ibcon#about to read 3, iclass 18, count 2 2006.176.08:25:38.71#ibcon#read 3, iclass 18, count 2 2006.176.08:25:38.71#ibcon#about to read 4, iclass 18, count 2 2006.176.08:25:38.71#ibcon#read 4, iclass 18, count 2 2006.176.08:25:38.71#ibcon#about to read 5, iclass 18, count 2 2006.176.08:25:38.71#ibcon#read 5, iclass 18, count 2 2006.176.08:25:38.71#ibcon#about to read 6, iclass 18, count 2 2006.176.08:25:38.71#ibcon#read 6, iclass 18, count 2 2006.176.08:25:38.71#ibcon#end of sib2, iclass 18, count 2 2006.176.08:25:38.71#ibcon#*mode == 0, iclass 18, count 2 2006.176.08:25:38.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.08:25:38.71#ibcon#[25=AT03-06\r\n] 2006.176.08:25:38.71#ibcon#*before write, iclass 18, count 2 2006.176.08:25:38.71#ibcon#enter sib2, iclass 18, count 2 2006.176.08:25:38.71#ibcon#flushed, iclass 18, count 2 2006.176.08:25:38.71#ibcon#about to write, iclass 18, count 2 2006.176.08:25:38.71#ibcon#wrote, iclass 18, count 2 2006.176.08:25:38.71#ibcon#about to read 3, iclass 18, count 2 2006.176.08:25:38.74#ibcon#read 3, iclass 18, count 2 2006.176.08:25:38.74#ibcon#about to read 4, iclass 18, count 2 2006.176.08:25:38.74#ibcon#read 4, iclass 18, count 2 2006.176.08:25:38.74#ibcon#about to read 5, iclass 18, count 2 2006.176.08:25:38.74#ibcon#read 5, iclass 18, count 2 2006.176.08:25:38.74#ibcon#about to read 6, iclass 18, count 2 2006.176.08:25:38.74#ibcon#read 6, iclass 18, count 2 2006.176.08:25:38.74#ibcon#end of sib2, iclass 18, count 2 2006.176.08:25:38.74#ibcon#*after write, iclass 18, count 2 2006.176.08:25:38.74#ibcon#*before return 0, iclass 18, count 2 2006.176.08:25:38.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:38.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:38.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.08:25:38.74#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:38.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:38.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:38.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:38.86#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:25:38.86#ibcon#first serial, iclass 18, count 0 2006.176.08:25:38.86#ibcon#enter sib2, iclass 18, count 0 2006.176.08:25:38.86#ibcon#flushed, iclass 18, count 0 2006.176.08:25:38.86#ibcon#about to write, iclass 18, count 0 2006.176.08:25:38.86#ibcon#wrote, iclass 18, count 0 2006.176.08:25:38.86#ibcon#about to read 3, iclass 18, count 0 2006.176.08:25:38.89#ibcon#read 3, iclass 18, count 0 2006.176.08:25:38.89#ibcon#about to read 4, iclass 18, count 0 2006.176.08:25:38.89#ibcon#read 4, iclass 18, count 0 2006.176.08:25:38.89#ibcon#about to read 5, iclass 18, count 0 2006.176.08:25:38.89#ibcon#read 5, iclass 18, count 0 2006.176.08:25:38.89#ibcon#about to read 6, iclass 18, count 0 2006.176.08:25:38.89#ibcon#read 6, iclass 18, count 0 2006.176.08:25:38.89#ibcon#end of sib2, iclass 18, count 0 2006.176.08:25:38.89#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:25:38.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:25:38.89#ibcon#[25=USB\r\n] 2006.176.08:25:38.89#ibcon#*before write, iclass 18, count 0 2006.176.08:25:38.89#ibcon#enter sib2, iclass 18, count 0 2006.176.08:25:38.89#ibcon#flushed, iclass 18, count 0 2006.176.08:25:38.89#ibcon#about to write, iclass 18, count 0 2006.176.08:25:38.89#ibcon#wrote, iclass 18, count 0 2006.176.08:25:38.89#ibcon#about to read 3, iclass 18, count 0 2006.176.08:25:38.92#ibcon#read 3, iclass 18, count 0 2006.176.08:25:38.92#ibcon#about to read 4, iclass 18, count 0 2006.176.08:25:38.92#ibcon#read 4, iclass 18, count 0 2006.176.08:25:38.92#ibcon#about to read 5, iclass 18, count 0 2006.176.08:25:38.92#ibcon#read 5, iclass 18, count 0 2006.176.08:25:38.92#ibcon#about to read 6, iclass 18, count 0 2006.176.08:25:38.92#ibcon#read 6, iclass 18, count 0 2006.176.08:25:38.92#ibcon#end of sib2, iclass 18, count 0 2006.176.08:25:38.92#ibcon#*after write, iclass 18, count 0 2006.176.08:25:38.92#ibcon#*before return 0, iclass 18, count 0 2006.176.08:25:38.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:38.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:38.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:25:38.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:25:38.92$vc4f8/valo=4,832.99 2006.176.08:25:38.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.08:25:38.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.08:25:38.92#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:38.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:25:38.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:25:38.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:25:38.92#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:25:38.92#ibcon#first serial, iclass 21, count 0 2006.176.08:25:38.92#ibcon#enter sib2, iclass 21, count 0 2006.176.08:25:38.92#ibcon#flushed, iclass 21, count 0 2006.176.08:25:38.92#ibcon#about to write, iclass 21, count 0 2006.176.08:25:38.92#ibcon#wrote, iclass 21, count 0 2006.176.08:25:38.92#ibcon#about to read 3, iclass 21, count 0 2006.176.08:25:38.94#ibcon#read 3, iclass 21, count 0 2006.176.08:25:38.94#ibcon#about to read 4, iclass 21, count 0 2006.176.08:25:38.94#ibcon#read 4, iclass 21, count 0 2006.176.08:25:38.94#ibcon#about to read 5, iclass 21, count 0 2006.176.08:25:38.94#ibcon#read 5, iclass 21, count 0 2006.176.08:25:38.94#ibcon#about to read 6, iclass 21, count 0 2006.176.08:25:38.94#ibcon#read 6, iclass 21, count 0 2006.176.08:25:38.94#ibcon#end of sib2, iclass 21, count 0 2006.176.08:25:38.94#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:25:38.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:25:38.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:25:38.94#ibcon#*before write, iclass 21, count 0 2006.176.08:25:38.94#ibcon#enter sib2, iclass 21, count 0 2006.176.08:25:38.94#ibcon#flushed, iclass 21, count 0 2006.176.08:25:38.94#ibcon#about to write, iclass 21, count 0 2006.176.08:25:38.94#ibcon#wrote, iclass 21, count 0 2006.176.08:25:38.94#ibcon#about to read 3, iclass 21, count 0 2006.176.08:25:38.96#abcon#<5=/05 3.0 5.2 23.73 921008.5\r\n> 2006.176.08:25:38.98#abcon#{5=INTERFACE CLEAR} 2006.176.08:25:38.98#ibcon#read 3, iclass 21, count 0 2006.176.08:25:38.98#ibcon#about to read 4, iclass 21, count 0 2006.176.08:25:38.98#ibcon#read 4, iclass 21, count 0 2006.176.08:25:38.98#ibcon#about to read 5, iclass 21, count 0 2006.176.08:25:38.98#ibcon#read 5, iclass 21, count 0 2006.176.08:25:38.98#ibcon#about to read 6, iclass 21, count 0 2006.176.08:25:38.98#ibcon#read 6, iclass 21, count 0 2006.176.08:25:38.98#ibcon#end of sib2, iclass 21, count 0 2006.176.08:25:38.98#ibcon#*after write, iclass 21, count 0 2006.176.08:25:38.98#ibcon#*before return 0, iclass 21, count 0 2006.176.08:25:38.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:25:38.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:25:38.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:25:38.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:25:38.98$vc4f8/va=4,7 2006.176.08:25:38.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.176.08:25:38.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.176.08:25:38.98#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:38.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:25:39.04#abcon#[5=S1D000X0/0*\r\n] 2006.176.08:25:39.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:25:39.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:25:39.04#ibcon#enter wrdev, iclass 25, count 2 2006.176.08:25:39.04#ibcon#first serial, iclass 25, count 2 2006.176.08:25:39.04#ibcon#enter sib2, iclass 25, count 2 2006.176.08:25:39.04#ibcon#flushed, iclass 25, count 2 2006.176.08:25:39.04#ibcon#about to write, iclass 25, count 2 2006.176.08:25:39.04#ibcon#wrote, iclass 25, count 2 2006.176.08:25:39.04#ibcon#about to read 3, iclass 25, count 2 2006.176.08:25:39.06#ibcon#read 3, iclass 25, count 2 2006.176.08:25:39.06#ibcon#about to read 4, iclass 25, count 2 2006.176.08:25:39.06#ibcon#read 4, iclass 25, count 2 2006.176.08:25:39.06#ibcon#about to read 5, iclass 25, count 2 2006.176.08:25:39.06#ibcon#read 5, iclass 25, count 2 2006.176.08:25:39.06#ibcon#about to read 6, iclass 25, count 2 2006.176.08:25:39.06#ibcon#read 6, iclass 25, count 2 2006.176.08:25:39.06#ibcon#end of sib2, iclass 25, count 2 2006.176.08:25:39.06#ibcon#*mode == 0, iclass 25, count 2 2006.176.08:25:39.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.176.08:25:39.06#ibcon#[25=AT04-07\r\n] 2006.176.08:25:39.06#ibcon#*before write, iclass 25, count 2 2006.176.08:25:39.06#ibcon#enter sib2, iclass 25, count 2 2006.176.08:25:39.06#ibcon#flushed, iclass 25, count 2 2006.176.08:25:39.06#ibcon#about to write, iclass 25, count 2 2006.176.08:25:39.06#ibcon#wrote, iclass 25, count 2 2006.176.08:25:39.06#ibcon#about to read 3, iclass 25, count 2 2006.176.08:25:39.09#ibcon#read 3, iclass 25, count 2 2006.176.08:25:39.09#ibcon#about to read 4, iclass 25, count 2 2006.176.08:25:39.09#ibcon#read 4, iclass 25, count 2 2006.176.08:25:39.09#ibcon#about to read 5, iclass 25, count 2 2006.176.08:25:39.09#ibcon#read 5, iclass 25, count 2 2006.176.08:25:39.09#ibcon#about to read 6, iclass 25, count 2 2006.176.08:25:39.09#ibcon#read 6, iclass 25, count 2 2006.176.08:25:39.09#ibcon#end of sib2, iclass 25, count 2 2006.176.08:25:39.09#ibcon#*after write, iclass 25, count 2 2006.176.08:25:39.09#ibcon#*before return 0, iclass 25, count 2 2006.176.08:25:39.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:25:39.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.176.08:25:39.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.176.08:25:39.09#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:39.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:25:39.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:25:39.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:25:39.21#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:25:39.21#ibcon#first serial, iclass 25, count 0 2006.176.08:25:39.21#ibcon#enter sib2, iclass 25, count 0 2006.176.08:25:39.21#ibcon#flushed, iclass 25, count 0 2006.176.08:25:39.21#ibcon#about to write, iclass 25, count 0 2006.176.08:25:39.21#ibcon#wrote, iclass 25, count 0 2006.176.08:25:39.21#ibcon#about to read 3, iclass 25, count 0 2006.176.08:25:39.23#ibcon#read 3, iclass 25, count 0 2006.176.08:25:39.23#ibcon#about to read 4, iclass 25, count 0 2006.176.08:25:39.23#ibcon#read 4, iclass 25, count 0 2006.176.08:25:39.23#ibcon#about to read 5, iclass 25, count 0 2006.176.08:25:39.23#ibcon#read 5, iclass 25, count 0 2006.176.08:25:39.23#ibcon#about to read 6, iclass 25, count 0 2006.176.08:25:39.23#ibcon#read 6, iclass 25, count 0 2006.176.08:25:39.23#ibcon#end of sib2, iclass 25, count 0 2006.176.08:25:39.23#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:25:39.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:25:39.23#ibcon#[25=USB\r\n] 2006.176.08:25:39.23#ibcon#*before write, iclass 25, count 0 2006.176.08:25:39.23#ibcon#enter sib2, iclass 25, count 0 2006.176.08:25:39.23#ibcon#flushed, iclass 25, count 0 2006.176.08:25:39.23#ibcon#about to write, iclass 25, count 0 2006.176.08:25:39.23#ibcon#wrote, iclass 25, count 0 2006.176.08:25:39.23#ibcon#about to read 3, iclass 25, count 0 2006.176.08:25:39.26#ibcon#read 3, iclass 25, count 0 2006.176.08:25:39.26#ibcon#about to read 4, iclass 25, count 0 2006.176.08:25:39.26#ibcon#read 4, iclass 25, count 0 2006.176.08:25:39.26#ibcon#about to read 5, iclass 25, count 0 2006.176.08:25:39.26#ibcon#read 5, iclass 25, count 0 2006.176.08:25:39.26#ibcon#about to read 6, iclass 25, count 0 2006.176.08:25:39.26#ibcon#read 6, iclass 25, count 0 2006.176.08:25:39.26#ibcon#end of sib2, iclass 25, count 0 2006.176.08:25:39.26#ibcon#*after write, iclass 25, count 0 2006.176.08:25:39.26#ibcon#*before return 0, iclass 25, count 0 2006.176.08:25:39.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:25:39.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.176.08:25:39.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:25:39.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:25:39.26$vc4f8/valo=5,652.99 2006.176.08:25:39.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.08:25:39.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.08:25:39.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:39.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:39.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:39.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:39.26#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:25:39.26#ibcon#first serial, iclass 28, count 0 2006.176.08:25:39.26#ibcon#enter sib2, iclass 28, count 0 2006.176.08:25:39.26#ibcon#flushed, iclass 28, count 0 2006.176.08:25:39.26#ibcon#about to write, iclass 28, count 0 2006.176.08:25:39.26#ibcon#wrote, iclass 28, count 0 2006.176.08:25:39.26#ibcon#about to read 3, iclass 28, count 0 2006.176.08:25:39.28#ibcon#read 3, iclass 28, count 0 2006.176.08:25:39.28#ibcon#about to read 4, iclass 28, count 0 2006.176.08:25:39.28#ibcon#read 4, iclass 28, count 0 2006.176.08:25:39.28#ibcon#about to read 5, iclass 28, count 0 2006.176.08:25:39.28#ibcon#read 5, iclass 28, count 0 2006.176.08:25:39.28#ibcon#about to read 6, iclass 28, count 0 2006.176.08:25:39.28#ibcon#read 6, iclass 28, count 0 2006.176.08:25:39.28#ibcon#end of sib2, iclass 28, count 0 2006.176.08:25:39.28#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:25:39.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:25:39.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:25:39.28#ibcon#*before write, iclass 28, count 0 2006.176.08:25:39.28#ibcon#enter sib2, iclass 28, count 0 2006.176.08:25:39.28#ibcon#flushed, iclass 28, count 0 2006.176.08:25:39.28#ibcon#about to write, iclass 28, count 0 2006.176.08:25:39.28#ibcon#wrote, iclass 28, count 0 2006.176.08:25:39.28#ibcon#about to read 3, iclass 28, count 0 2006.176.08:25:39.32#ibcon#read 3, iclass 28, count 0 2006.176.08:25:39.32#ibcon#about to read 4, iclass 28, count 0 2006.176.08:25:39.32#ibcon#read 4, iclass 28, count 0 2006.176.08:25:39.32#ibcon#about to read 5, iclass 28, count 0 2006.176.08:25:39.32#ibcon#read 5, iclass 28, count 0 2006.176.08:25:39.32#ibcon#about to read 6, iclass 28, count 0 2006.176.08:25:39.32#ibcon#read 6, iclass 28, count 0 2006.176.08:25:39.32#ibcon#end of sib2, iclass 28, count 0 2006.176.08:25:39.32#ibcon#*after write, iclass 28, count 0 2006.176.08:25:39.32#ibcon#*before return 0, iclass 28, count 0 2006.176.08:25:39.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:39.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:39.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:25:39.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:25:39.32$vc4f8/va=5,7 2006.176.08:25:39.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.08:25:39.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.08:25:39.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:39.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:39.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:39.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:39.38#ibcon#enter wrdev, iclass 30, count 2 2006.176.08:25:39.38#ibcon#first serial, iclass 30, count 2 2006.176.08:25:39.38#ibcon#enter sib2, iclass 30, count 2 2006.176.08:25:39.38#ibcon#flushed, iclass 30, count 2 2006.176.08:25:39.38#ibcon#about to write, iclass 30, count 2 2006.176.08:25:39.38#ibcon#wrote, iclass 30, count 2 2006.176.08:25:39.38#ibcon#about to read 3, iclass 30, count 2 2006.176.08:25:39.40#ibcon#read 3, iclass 30, count 2 2006.176.08:25:39.40#ibcon#about to read 4, iclass 30, count 2 2006.176.08:25:39.40#ibcon#read 4, iclass 30, count 2 2006.176.08:25:39.40#ibcon#about to read 5, iclass 30, count 2 2006.176.08:25:39.40#ibcon#read 5, iclass 30, count 2 2006.176.08:25:39.40#ibcon#about to read 6, iclass 30, count 2 2006.176.08:25:39.40#ibcon#read 6, iclass 30, count 2 2006.176.08:25:39.40#ibcon#end of sib2, iclass 30, count 2 2006.176.08:25:39.40#ibcon#*mode == 0, iclass 30, count 2 2006.176.08:25:39.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.08:25:39.40#ibcon#[25=AT05-07\r\n] 2006.176.08:25:39.40#ibcon#*before write, iclass 30, count 2 2006.176.08:25:39.40#ibcon#enter sib2, iclass 30, count 2 2006.176.08:25:39.40#ibcon#flushed, iclass 30, count 2 2006.176.08:25:39.40#ibcon#about to write, iclass 30, count 2 2006.176.08:25:39.40#ibcon#wrote, iclass 30, count 2 2006.176.08:25:39.40#ibcon#about to read 3, iclass 30, count 2 2006.176.08:25:39.43#ibcon#read 3, iclass 30, count 2 2006.176.08:25:39.43#ibcon#about to read 4, iclass 30, count 2 2006.176.08:25:39.43#ibcon#read 4, iclass 30, count 2 2006.176.08:25:39.43#ibcon#about to read 5, iclass 30, count 2 2006.176.08:25:39.43#ibcon#read 5, iclass 30, count 2 2006.176.08:25:39.43#ibcon#about to read 6, iclass 30, count 2 2006.176.08:25:39.43#ibcon#read 6, iclass 30, count 2 2006.176.08:25:39.43#ibcon#end of sib2, iclass 30, count 2 2006.176.08:25:39.43#ibcon#*after write, iclass 30, count 2 2006.176.08:25:39.43#ibcon#*before return 0, iclass 30, count 2 2006.176.08:25:39.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:39.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:39.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.08:25:39.43#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:39.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:39.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:39.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:39.55#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:25:39.55#ibcon#first serial, iclass 30, count 0 2006.176.08:25:39.55#ibcon#enter sib2, iclass 30, count 0 2006.176.08:25:39.55#ibcon#flushed, iclass 30, count 0 2006.176.08:25:39.55#ibcon#about to write, iclass 30, count 0 2006.176.08:25:39.55#ibcon#wrote, iclass 30, count 0 2006.176.08:25:39.55#ibcon#about to read 3, iclass 30, count 0 2006.176.08:25:39.57#ibcon#read 3, iclass 30, count 0 2006.176.08:25:39.57#ibcon#about to read 4, iclass 30, count 0 2006.176.08:25:39.57#ibcon#read 4, iclass 30, count 0 2006.176.08:25:39.57#ibcon#about to read 5, iclass 30, count 0 2006.176.08:25:39.57#ibcon#read 5, iclass 30, count 0 2006.176.08:25:39.57#ibcon#about to read 6, iclass 30, count 0 2006.176.08:25:39.57#ibcon#read 6, iclass 30, count 0 2006.176.08:25:39.57#ibcon#end of sib2, iclass 30, count 0 2006.176.08:25:39.57#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:25:39.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:25:39.57#ibcon#[25=USB\r\n] 2006.176.08:25:39.57#ibcon#*before write, iclass 30, count 0 2006.176.08:25:39.57#ibcon#enter sib2, iclass 30, count 0 2006.176.08:25:39.57#ibcon#flushed, iclass 30, count 0 2006.176.08:25:39.57#ibcon#about to write, iclass 30, count 0 2006.176.08:25:39.57#ibcon#wrote, iclass 30, count 0 2006.176.08:25:39.57#ibcon#about to read 3, iclass 30, count 0 2006.176.08:25:39.60#ibcon#read 3, iclass 30, count 0 2006.176.08:25:39.60#ibcon#about to read 4, iclass 30, count 0 2006.176.08:25:39.60#ibcon#read 4, iclass 30, count 0 2006.176.08:25:39.60#ibcon#about to read 5, iclass 30, count 0 2006.176.08:25:39.60#ibcon#read 5, iclass 30, count 0 2006.176.08:25:39.60#ibcon#about to read 6, iclass 30, count 0 2006.176.08:25:39.60#ibcon#read 6, iclass 30, count 0 2006.176.08:25:39.60#ibcon#end of sib2, iclass 30, count 0 2006.176.08:25:39.60#ibcon#*after write, iclass 30, count 0 2006.176.08:25:39.60#ibcon#*before return 0, iclass 30, count 0 2006.176.08:25:39.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:39.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:39.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:25:39.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:25:39.60$vc4f8/valo=6,772.99 2006.176.08:25:39.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.08:25:39.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.08:25:39.60#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:39.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:39.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:39.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:39.60#ibcon#enter wrdev, iclass 32, count 0 2006.176.08:25:39.60#ibcon#first serial, iclass 32, count 0 2006.176.08:25:39.60#ibcon#enter sib2, iclass 32, count 0 2006.176.08:25:39.60#ibcon#flushed, iclass 32, count 0 2006.176.08:25:39.60#ibcon#about to write, iclass 32, count 0 2006.176.08:25:39.60#ibcon#wrote, iclass 32, count 0 2006.176.08:25:39.60#ibcon#about to read 3, iclass 32, count 0 2006.176.08:25:39.62#ibcon#read 3, iclass 32, count 0 2006.176.08:25:39.62#ibcon#about to read 4, iclass 32, count 0 2006.176.08:25:39.62#ibcon#read 4, iclass 32, count 0 2006.176.08:25:39.62#ibcon#about to read 5, iclass 32, count 0 2006.176.08:25:39.62#ibcon#read 5, iclass 32, count 0 2006.176.08:25:39.62#ibcon#about to read 6, iclass 32, count 0 2006.176.08:25:39.62#ibcon#read 6, iclass 32, count 0 2006.176.08:25:39.62#ibcon#end of sib2, iclass 32, count 0 2006.176.08:25:39.62#ibcon#*mode == 0, iclass 32, count 0 2006.176.08:25:39.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.08:25:39.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:25:39.62#ibcon#*before write, iclass 32, count 0 2006.176.08:25:39.62#ibcon#enter sib2, iclass 32, count 0 2006.176.08:25:39.62#ibcon#flushed, iclass 32, count 0 2006.176.08:25:39.62#ibcon#about to write, iclass 32, count 0 2006.176.08:25:39.62#ibcon#wrote, iclass 32, count 0 2006.176.08:25:39.62#ibcon#about to read 3, iclass 32, count 0 2006.176.08:25:39.66#ibcon#read 3, iclass 32, count 0 2006.176.08:25:39.66#ibcon#about to read 4, iclass 32, count 0 2006.176.08:25:39.66#ibcon#read 4, iclass 32, count 0 2006.176.08:25:39.66#ibcon#about to read 5, iclass 32, count 0 2006.176.08:25:39.66#ibcon#read 5, iclass 32, count 0 2006.176.08:25:39.66#ibcon#about to read 6, iclass 32, count 0 2006.176.08:25:39.66#ibcon#read 6, iclass 32, count 0 2006.176.08:25:39.66#ibcon#end of sib2, iclass 32, count 0 2006.176.08:25:39.66#ibcon#*after write, iclass 32, count 0 2006.176.08:25:39.66#ibcon#*before return 0, iclass 32, count 0 2006.176.08:25:39.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:39.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:39.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.08:25:39.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.08:25:39.66$vc4f8/va=6,6 2006.176.08:25:39.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.176.08:25:39.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.176.08:25:39.66#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:39.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:25:39.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:25:39.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:25:39.72#ibcon#enter wrdev, iclass 34, count 2 2006.176.08:25:39.72#ibcon#first serial, iclass 34, count 2 2006.176.08:25:39.72#ibcon#enter sib2, iclass 34, count 2 2006.176.08:25:39.72#ibcon#flushed, iclass 34, count 2 2006.176.08:25:39.72#ibcon#about to write, iclass 34, count 2 2006.176.08:25:39.72#ibcon#wrote, iclass 34, count 2 2006.176.08:25:39.72#ibcon#about to read 3, iclass 34, count 2 2006.176.08:25:39.74#ibcon#read 3, iclass 34, count 2 2006.176.08:25:39.74#ibcon#about to read 4, iclass 34, count 2 2006.176.08:25:39.74#ibcon#read 4, iclass 34, count 2 2006.176.08:25:39.74#ibcon#about to read 5, iclass 34, count 2 2006.176.08:25:39.74#ibcon#read 5, iclass 34, count 2 2006.176.08:25:39.74#ibcon#about to read 6, iclass 34, count 2 2006.176.08:25:39.74#ibcon#read 6, iclass 34, count 2 2006.176.08:25:39.74#ibcon#end of sib2, iclass 34, count 2 2006.176.08:25:39.74#ibcon#*mode == 0, iclass 34, count 2 2006.176.08:25:39.74#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.176.08:25:39.74#ibcon#[25=AT06-06\r\n] 2006.176.08:25:39.74#ibcon#*before write, iclass 34, count 2 2006.176.08:25:39.74#ibcon#enter sib2, iclass 34, count 2 2006.176.08:25:39.74#ibcon#flushed, iclass 34, count 2 2006.176.08:25:39.74#ibcon#about to write, iclass 34, count 2 2006.176.08:25:39.74#ibcon#wrote, iclass 34, count 2 2006.176.08:25:39.74#ibcon#about to read 3, iclass 34, count 2 2006.176.08:25:39.77#ibcon#read 3, iclass 34, count 2 2006.176.08:25:39.77#ibcon#about to read 4, iclass 34, count 2 2006.176.08:25:39.77#ibcon#read 4, iclass 34, count 2 2006.176.08:25:39.77#ibcon#about to read 5, iclass 34, count 2 2006.176.08:25:39.77#ibcon#read 5, iclass 34, count 2 2006.176.08:25:39.77#ibcon#about to read 6, iclass 34, count 2 2006.176.08:25:39.77#ibcon#read 6, iclass 34, count 2 2006.176.08:25:39.77#ibcon#end of sib2, iclass 34, count 2 2006.176.08:25:39.77#ibcon#*after write, iclass 34, count 2 2006.176.08:25:39.77#ibcon#*before return 0, iclass 34, count 2 2006.176.08:25:39.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:25:39.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.176.08:25:39.77#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.176.08:25:39.77#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:39.77#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:25:39.89#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:25:39.89#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:25:39.89#ibcon#enter wrdev, iclass 34, count 0 2006.176.08:25:39.89#ibcon#first serial, iclass 34, count 0 2006.176.08:25:39.89#ibcon#enter sib2, iclass 34, count 0 2006.176.08:25:39.89#ibcon#flushed, iclass 34, count 0 2006.176.08:25:39.89#ibcon#about to write, iclass 34, count 0 2006.176.08:25:39.89#ibcon#wrote, iclass 34, count 0 2006.176.08:25:39.89#ibcon#about to read 3, iclass 34, count 0 2006.176.08:25:39.91#ibcon#read 3, iclass 34, count 0 2006.176.08:25:39.91#ibcon#about to read 4, iclass 34, count 0 2006.176.08:25:39.91#ibcon#read 4, iclass 34, count 0 2006.176.08:25:39.91#ibcon#about to read 5, iclass 34, count 0 2006.176.08:25:39.91#ibcon#read 5, iclass 34, count 0 2006.176.08:25:39.91#ibcon#about to read 6, iclass 34, count 0 2006.176.08:25:39.91#ibcon#read 6, iclass 34, count 0 2006.176.08:25:39.91#ibcon#end of sib2, iclass 34, count 0 2006.176.08:25:39.91#ibcon#*mode == 0, iclass 34, count 0 2006.176.08:25:39.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.08:25:39.91#ibcon#[25=USB\r\n] 2006.176.08:25:39.91#ibcon#*before write, iclass 34, count 0 2006.176.08:25:39.91#ibcon#enter sib2, iclass 34, count 0 2006.176.08:25:39.91#ibcon#flushed, iclass 34, count 0 2006.176.08:25:39.91#ibcon#about to write, iclass 34, count 0 2006.176.08:25:39.91#ibcon#wrote, iclass 34, count 0 2006.176.08:25:39.91#ibcon#about to read 3, iclass 34, count 0 2006.176.08:25:39.94#ibcon#read 3, iclass 34, count 0 2006.176.08:25:39.94#ibcon#about to read 4, iclass 34, count 0 2006.176.08:25:39.94#ibcon#read 4, iclass 34, count 0 2006.176.08:25:39.94#ibcon#about to read 5, iclass 34, count 0 2006.176.08:25:39.94#ibcon#read 5, iclass 34, count 0 2006.176.08:25:39.94#ibcon#about to read 6, iclass 34, count 0 2006.176.08:25:39.94#ibcon#read 6, iclass 34, count 0 2006.176.08:25:39.94#ibcon#end of sib2, iclass 34, count 0 2006.176.08:25:39.94#ibcon#*after write, iclass 34, count 0 2006.176.08:25:39.94#ibcon#*before return 0, iclass 34, count 0 2006.176.08:25:39.94#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:25:39.94#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.176.08:25:39.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.08:25:39.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.08:25:39.94$vc4f8/valo=7,832.99 2006.176.08:25:39.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.176.08:25:39.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.176.08:25:39.94#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:39.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:25:39.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:25:39.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:25:39.94#ibcon#enter wrdev, iclass 36, count 0 2006.176.08:25:39.94#ibcon#first serial, iclass 36, count 0 2006.176.08:25:39.94#ibcon#enter sib2, iclass 36, count 0 2006.176.08:25:39.94#ibcon#flushed, iclass 36, count 0 2006.176.08:25:39.94#ibcon#about to write, iclass 36, count 0 2006.176.08:25:39.94#ibcon#wrote, iclass 36, count 0 2006.176.08:25:39.94#ibcon#about to read 3, iclass 36, count 0 2006.176.08:25:39.96#ibcon#read 3, iclass 36, count 0 2006.176.08:25:39.96#ibcon#about to read 4, iclass 36, count 0 2006.176.08:25:39.96#ibcon#read 4, iclass 36, count 0 2006.176.08:25:39.96#ibcon#about to read 5, iclass 36, count 0 2006.176.08:25:39.96#ibcon#read 5, iclass 36, count 0 2006.176.08:25:39.96#ibcon#about to read 6, iclass 36, count 0 2006.176.08:25:39.96#ibcon#read 6, iclass 36, count 0 2006.176.08:25:39.96#ibcon#end of sib2, iclass 36, count 0 2006.176.08:25:39.96#ibcon#*mode == 0, iclass 36, count 0 2006.176.08:25:39.96#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.176.08:25:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:25:39.96#ibcon#*before write, iclass 36, count 0 2006.176.08:25:39.96#ibcon#enter sib2, iclass 36, count 0 2006.176.08:25:39.96#ibcon#flushed, iclass 36, count 0 2006.176.08:25:39.96#ibcon#about to write, iclass 36, count 0 2006.176.08:25:39.96#ibcon#wrote, iclass 36, count 0 2006.176.08:25:39.96#ibcon#about to read 3, iclass 36, count 0 2006.176.08:25:40.00#ibcon#read 3, iclass 36, count 0 2006.176.08:25:40.00#ibcon#about to read 4, iclass 36, count 0 2006.176.08:25:40.00#ibcon#read 4, iclass 36, count 0 2006.176.08:25:40.00#ibcon#about to read 5, iclass 36, count 0 2006.176.08:25:40.00#ibcon#read 5, iclass 36, count 0 2006.176.08:25:40.00#ibcon#about to read 6, iclass 36, count 0 2006.176.08:25:40.00#ibcon#read 6, iclass 36, count 0 2006.176.08:25:40.00#ibcon#end of sib2, iclass 36, count 0 2006.176.08:25:40.00#ibcon#*after write, iclass 36, count 0 2006.176.08:25:40.00#ibcon#*before return 0, iclass 36, count 0 2006.176.08:25:40.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:25:40.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.176.08:25:40.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.176.08:25:40.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.176.08:25:40.00$vc4f8/va=7,6 2006.176.08:25:40.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.176.08:25:40.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.176.08:25:40.00#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:40.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:25:40.06#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:25:40.06#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:25:40.06#ibcon#enter wrdev, iclass 38, count 2 2006.176.08:25:40.06#ibcon#first serial, iclass 38, count 2 2006.176.08:25:40.06#ibcon#enter sib2, iclass 38, count 2 2006.176.08:25:40.06#ibcon#flushed, iclass 38, count 2 2006.176.08:25:40.06#ibcon#about to write, iclass 38, count 2 2006.176.08:25:40.06#ibcon#wrote, iclass 38, count 2 2006.176.08:25:40.06#ibcon#about to read 3, iclass 38, count 2 2006.176.08:25:40.08#ibcon#read 3, iclass 38, count 2 2006.176.08:25:40.08#ibcon#about to read 4, iclass 38, count 2 2006.176.08:25:40.08#ibcon#read 4, iclass 38, count 2 2006.176.08:25:40.08#ibcon#about to read 5, iclass 38, count 2 2006.176.08:25:40.08#ibcon#read 5, iclass 38, count 2 2006.176.08:25:40.08#ibcon#about to read 6, iclass 38, count 2 2006.176.08:25:40.08#ibcon#read 6, iclass 38, count 2 2006.176.08:25:40.08#ibcon#end of sib2, iclass 38, count 2 2006.176.08:25:40.08#ibcon#*mode == 0, iclass 38, count 2 2006.176.08:25:40.08#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.176.08:25:40.08#ibcon#[25=AT07-06\r\n] 2006.176.08:25:40.08#ibcon#*before write, iclass 38, count 2 2006.176.08:25:40.08#ibcon#enter sib2, iclass 38, count 2 2006.176.08:25:40.08#ibcon#flushed, iclass 38, count 2 2006.176.08:25:40.08#ibcon#about to write, iclass 38, count 2 2006.176.08:25:40.08#ibcon#wrote, iclass 38, count 2 2006.176.08:25:40.08#ibcon#about to read 3, iclass 38, count 2 2006.176.08:25:40.11#ibcon#read 3, iclass 38, count 2 2006.176.08:25:40.11#ibcon#about to read 4, iclass 38, count 2 2006.176.08:25:40.11#ibcon#read 4, iclass 38, count 2 2006.176.08:25:40.11#ibcon#about to read 5, iclass 38, count 2 2006.176.08:25:40.11#ibcon#read 5, iclass 38, count 2 2006.176.08:25:40.11#ibcon#about to read 6, iclass 38, count 2 2006.176.08:25:40.11#ibcon#read 6, iclass 38, count 2 2006.176.08:25:40.11#ibcon#end of sib2, iclass 38, count 2 2006.176.08:25:40.11#ibcon#*after write, iclass 38, count 2 2006.176.08:25:40.11#ibcon#*before return 0, iclass 38, count 2 2006.176.08:25:40.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:25:40.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.176.08:25:40.11#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.176.08:25:40.11#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:40.11#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:25:40.23#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:25:40.23#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:25:40.23#ibcon#enter wrdev, iclass 38, count 0 2006.176.08:25:40.23#ibcon#first serial, iclass 38, count 0 2006.176.08:25:40.23#ibcon#enter sib2, iclass 38, count 0 2006.176.08:25:40.23#ibcon#flushed, iclass 38, count 0 2006.176.08:25:40.23#ibcon#about to write, iclass 38, count 0 2006.176.08:25:40.23#ibcon#wrote, iclass 38, count 0 2006.176.08:25:40.23#ibcon#about to read 3, iclass 38, count 0 2006.176.08:25:40.25#ibcon#read 3, iclass 38, count 0 2006.176.08:25:40.25#ibcon#about to read 4, iclass 38, count 0 2006.176.08:25:40.25#ibcon#read 4, iclass 38, count 0 2006.176.08:25:40.25#ibcon#about to read 5, iclass 38, count 0 2006.176.08:25:40.25#ibcon#read 5, iclass 38, count 0 2006.176.08:25:40.25#ibcon#about to read 6, iclass 38, count 0 2006.176.08:25:40.25#ibcon#read 6, iclass 38, count 0 2006.176.08:25:40.25#ibcon#end of sib2, iclass 38, count 0 2006.176.08:25:40.25#ibcon#*mode == 0, iclass 38, count 0 2006.176.08:25:40.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.176.08:25:40.25#ibcon#[25=USB\r\n] 2006.176.08:25:40.25#ibcon#*before write, iclass 38, count 0 2006.176.08:25:40.25#ibcon#enter sib2, iclass 38, count 0 2006.176.08:25:40.25#ibcon#flushed, iclass 38, count 0 2006.176.08:25:40.25#ibcon#about to write, iclass 38, count 0 2006.176.08:25:40.25#ibcon#wrote, iclass 38, count 0 2006.176.08:25:40.25#ibcon#about to read 3, iclass 38, count 0 2006.176.08:25:40.28#ibcon#read 3, iclass 38, count 0 2006.176.08:25:40.28#ibcon#about to read 4, iclass 38, count 0 2006.176.08:25:40.28#ibcon#read 4, iclass 38, count 0 2006.176.08:25:40.28#ibcon#about to read 5, iclass 38, count 0 2006.176.08:25:40.28#ibcon#read 5, iclass 38, count 0 2006.176.08:25:40.28#ibcon#about to read 6, iclass 38, count 0 2006.176.08:25:40.28#ibcon#read 6, iclass 38, count 0 2006.176.08:25:40.28#ibcon#end of sib2, iclass 38, count 0 2006.176.08:25:40.28#ibcon#*after write, iclass 38, count 0 2006.176.08:25:40.28#ibcon#*before return 0, iclass 38, count 0 2006.176.08:25:40.28#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:25:40.28#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.176.08:25:40.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.176.08:25:40.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.176.08:25:40.28$vc4f8/valo=8,852.99 2006.176.08:25:40.28#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.176.08:25:40.28#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.176.08:25:40.28#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:40.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:25:40.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:25:40.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:25:40.28#ibcon#enter wrdev, iclass 40, count 0 2006.176.08:25:40.28#ibcon#first serial, iclass 40, count 0 2006.176.08:25:40.28#ibcon#enter sib2, iclass 40, count 0 2006.176.08:25:40.28#ibcon#flushed, iclass 40, count 0 2006.176.08:25:40.28#ibcon#about to write, iclass 40, count 0 2006.176.08:25:40.28#ibcon#wrote, iclass 40, count 0 2006.176.08:25:40.28#ibcon#about to read 3, iclass 40, count 0 2006.176.08:25:40.30#ibcon#read 3, iclass 40, count 0 2006.176.08:25:40.30#ibcon#about to read 4, iclass 40, count 0 2006.176.08:25:40.30#ibcon#read 4, iclass 40, count 0 2006.176.08:25:40.30#ibcon#about to read 5, iclass 40, count 0 2006.176.08:25:40.30#ibcon#read 5, iclass 40, count 0 2006.176.08:25:40.30#ibcon#about to read 6, iclass 40, count 0 2006.176.08:25:40.30#ibcon#read 6, iclass 40, count 0 2006.176.08:25:40.30#ibcon#end of sib2, iclass 40, count 0 2006.176.08:25:40.30#ibcon#*mode == 0, iclass 40, count 0 2006.176.08:25:40.30#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.176.08:25:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:25:40.30#ibcon#*before write, iclass 40, count 0 2006.176.08:25:40.30#ibcon#enter sib2, iclass 40, count 0 2006.176.08:25:40.30#ibcon#flushed, iclass 40, count 0 2006.176.08:25:40.30#ibcon#about to write, iclass 40, count 0 2006.176.08:25:40.30#ibcon#wrote, iclass 40, count 0 2006.176.08:25:40.30#ibcon#about to read 3, iclass 40, count 0 2006.176.08:25:40.34#ibcon#read 3, iclass 40, count 0 2006.176.08:25:40.34#ibcon#about to read 4, iclass 40, count 0 2006.176.08:25:40.34#ibcon#read 4, iclass 40, count 0 2006.176.08:25:40.34#ibcon#about to read 5, iclass 40, count 0 2006.176.08:25:40.34#ibcon#read 5, iclass 40, count 0 2006.176.08:25:40.34#ibcon#about to read 6, iclass 40, count 0 2006.176.08:25:40.34#ibcon#read 6, iclass 40, count 0 2006.176.08:25:40.34#ibcon#end of sib2, iclass 40, count 0 2006.176.08:25:40.34#ibcon#*after write, iclass 40, count 0 2006.176.08:25:40.34#ibcon#*before return 0, iclass 40, count 0 2006.176.08:25:40.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:25:40.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.176.08:25:40.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.176.08:25:40.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.176.08:25:40.34$vc4f8/va=8,6 2006.176.08:25:40.34#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.176.08:25:40.34#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.176.08:25:40.34#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:40.34#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:25:40.40#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:25:40.40#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:25:40.40#ibcon#enter wrdev, iclass 4, count 2 2006.176.08:25:40.40#ibcon#first serial, iclass 4, count 2 2006.176.08:25:40.40#ibcon#enter sib2, iclass 4, count 2 2006.176.08:25:40.40#ibcon#flushed, iclass 4, count 2 2006.176.08:25:40.40#ibcon#about to write, iclass 4, count 2 2006.176.08:25:40.40#ibcon#wrote, iclass 4, count 2 2006.176.08:25:40.40#ibcon#about to read 3, iclass 4, count 2 2006.176.08:25:40.42#ibcon#read 3, iclass 4, count 2 2006.176.08:25:40.42#ibcon#about to read 4, iclass 4, count 2 2006.176.08:25:40.42#ibcon#read 4, iclass 4, count 2 2006.176.08:25:40.42#ibcon#about to read 5, iclass 4, count 2 2006.176.08:25:40.42#ibcon#read 5, iclass 4, count 2 2006.176.08:25:40.42#ibcon#about to read 6, iclass 4, count 2 2006.176.08:25:40.42#ibcon#read 6, iclass 4, count 2 2006.176.08:25:40.42#ibcon#end of sib2, iclass 4, count 2 2006.176.08:25:40.42#ibcon#*mode == 0, iclass 4, count 2 2006.176.08:25:40.42#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.176.08:25:40.42#ibcon#[25=AT08-06\r\n] 2006.176.08:25:40.42#ibcon#*before write, iclass 4, count 2 2006.176.08:25:40.42#ibcon#enter sib2, iclass 4, count 2 2006.176.08:25:40.42#ibcon#flushed, iclass 4, count 2 2006.176.08:25:40.42#ibcon#about to write, iclass 4, count 2 2006.176.08:25:40.42#ibcon#wrote, iclass 4, count 2 2006.176.08:25:40.42#ibcon#about to read 3, iclass 4, count 2 2006.176.08:25:40.45#ibcon#read 3, iclass 4, count 2 2006.176.08:25:40.45#ibcon#about to read 4, iclass 4, count 2 2006.176.08:25:40.45#ibcon#read 4, iclass 4, count 2 2006.176.08:25:40.45#ibcon#about to read 5, iclass 4, count 2 2006.176.08:25:40.45#ibcon#read 5, iclass 4, count 2 2006.176.08:25:40.45#ibcon#about to read 6, iclass 4, count 2 2006.176.08:25:40.45#ibcon#read 6, iclass 4, count 2 2006.176.08:25:40.45#ibcon#end of sib2, iclass 4, count 2 2006.176.08:25:40.45#ibcon#*after write, iclass 4, count 2 2006.176.08:25:40.45#ibcon#*before return 0, iclass 4, count 2 2006.176.08:25:40.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:25:40.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.176.08:25:40.45#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.176.08:25:40.45#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:40.45#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:25:40.57#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:25:40.57#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:25:40.57#ibcon#enter wrdev, iclass 4, count 0 2006.176.08:25:40.57#ibcon#first serial, iclass 4, count 0 2006.176.08:25:40.57#ibcon#enter sib2, iclass 4, count 0 2006.176.08:25:40.57#ibcon#flushed, iclass 4, count 0 2006.176.08:25:40.57#ibcon#about to write, iclass 4, count 0 2006.176.08:25:40.57#ibcon#wrote, iclass 4, count 0 2006.176.08:25:40.57#ibcon#about to read 3, iclass 4, count 0 2006.176.08:25:40.59#ibcon#read 3, iclass 4, count 0 2006.176.08:25:40.59#ibcon#about to read 4, iclass 4, count 0 2006.176.08:25:40.59#ibcon#read 4, iclass 4, count 0 2006.176.08:25:40.59#ibcon#about to read 5, iclass 4, count 0 2006.176.08:25:40.59#ibcon#read 5, iclass 4, count 0 2006.176.08:25:40.59#ibcon#about to read 6, iclass 4, count 0 2006.176.08:25:40.59#ibcon#read 6, iclass 4, count 0 2006.176.08:25:40.59#ibcon#end of sib2, iclass 4, count 0 2006.176.08:25:40.59#ibcon#*mode == 0, iclass 4, count 0 2006.176.08:25:40.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.176.08:25:40.59#ibcon#[25=USB\r\n] 2006.176.08:25:40.59#ibcon#*before write, iclass 4, count 0 2006.176.08:25:40.59#ibcon#enter sib2, iclass 4, count 0 2006.176.08:25:40.59#ibcon#flushed, iclass 4, count 0 2006.176.08:25:40.59#ibcon#about to write, iclass 4, count 0 2006.176.08:25:40.59#ibcon#wrote, iclass 4, count 0 2006.176.08:25:40.59#ibcon#about to read 3, iclass 4, count 0 2006.176.08:25:40.62#ibcon#read 3, iclass 4, count 0 2006.176.08:25:40.62#ibcon#about to read 4, iclass 4, count 0 2006.176.08:25:40.62#ibcon#read 4, iclass 4, count 0 2006.176.08:25:40.62#ibcon#about to read 5, iclass 4, count 0 2006.176.08:25:40.62#ibcon#read 5, iclass 4, count 0 2006.176.08:25:40.62#ibcon#about to read 6, iclass 4, count 0 2006.176.08:25:40.62#ibcon#read 6, iclass 4, count 0 2006.176.08:25:40.62#ibcon#end of sib2, iclass 4, count 0 2006.176.08:25:40.62#ibcon#*after write, iclass 4, count 0 2006.176.08:25:40.62#ibcon#*before return 0, iclass 4, count 0 2006.176.08:25:40.62#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:25:40.62#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.176.08:25:40.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.176.08:25:40.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.176.08:25:40.62$vc4f8/vblo=1,632.99 2006.176.08:25:40.62#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.08:25:40.62#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.08:25:40.62#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:40.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:40.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:40.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:40.62#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:25:40.62#ibcon#first serial, iclass 6, count 0 2006.176.08:25:40.62#ibcon#enter sib2, iclass 6, count 0 2006.176.08:25:40.62#ibcon#flushed, iclass 6, count 0 2006.176.08:25:40.62#ibcon#about to write, iclass 6, count 0 2006.176.08:25:40.62#ibcon#wrote, iclass 6, count 0 2006.176.08:25:40.62#ibcon#about to read 3, iclass 6, count 0 2006.176.08:25:40.64#ibcon#read 3, iclass 6, count 0 2006.176.08:25:40.64#ibcon#about to read 4, iclass 6, count 0 2006.176.08:25:40.64#ibcon#read 4, iclass 6, count 0 2006.176.08:25:40.64#ibcon#about to read 5, iclass 6, count 0 2006.176.08:25:40.64#ibcon#read 5, iclass 6, count 0 2006.176.08:25:40.64#ibcon#about to read 6, iclass 6, count 0 2006.176.08:25:40.64#ibcon#read 6, iclass 6, count 0 2006.176.08:25:40.64#ibcon#end of sib2, iclass 6, count 0 2006.176.08:25:40.64#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:25:40.64#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:25:40.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:25:40.64#ibcon#*before write, iclass 6, count 0 2006.176.08:25:40.64#ibcon#enter sib2, iclass 6, count 0 2006.176.08:25:40.64#ibcon#flushed, iclass 6, count 0 2006.176.08:25:40.64#ibcon#about to write, iclass 6, count 0 2006.176.08:25:40.64#ibcon#wrote, iclass 6, count 0 2006.176.08:25:40.64#ibcon#about to read 3, iclass 6, count 0 2006.176.08:25:40.68#ibcon#read 3, iclass 6, count 0 2006.176.08:25:40.68#ibcon#about to read 4, iclass 6, count 0 2006.176.08:25:40.68#ibcon#read 4, iclass 6, count 0 2006.176.08:25:40.68#ibcon#about to read 5, iclass 6, count 0 2006.176.08:25:40.68#ibcon#read 5, iclass 6, count 0 2006.176.08:25:40.68#ibcon#about to read 6, iclass 6, count 0 2006.176.08:25:40.68#ibcon#read 6, iclass 6, count 0 2006.176.08:25:40.68#ibcon#end of sib2, iclass 6, count 0 2006.176.08:25:40.68#ibcon#*after write, iclass 6, count 0 2006.176.08:25:40.68#ibcon#*before return 0, iclass 6, count 0 2006.176.08:25:40.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:40.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:25:40.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:25:40.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:25:40.68$vc4f8/vb=1,4 2006.176.08:25:40.68#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.176.08:25:40.68#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.176.08:25:40.68#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:40.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:40.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:40.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:40.68#ibcon#enter wrdev, iclass 10, count 2 2006.176.08:25:40.68#ibcon#first serial, iclass 10, count 2 2006.176.08:25:40.68#ibcon#enter sib2, iclass 10, count 2 2006.176.08:25:40.68#ibcon#flushed, iclass 10, count 2 2006.176.08:25:40.68#ibcon#about to write, iclass 10, count 2 2006.176.08:25:40.68#ibcon#wrote, iclass 10, count 2 2006.176.08:25:40.68#ibcon#about to read 3, iclass 10, count 2 2006.176.08:25:40.70#ibcon#read 3, iclass 10, count 2 2006.176.08:25:40.70#ibcon#about to read 4, iclass 10, count 2 2006.176.08:25:40.70#ibcon#read 4, iclass 10, count 2 2006.176.08:25:40.70#ibcon#about to read 5, iclass 10, count 2 2006.176.08:25:40.70#ibcon#read 5, iclass 10, count 2 2006.176.08:25:40.70#ibcon#about to read 6, iclass 10, count 2 2006.176.08:25:40.70#ibcon#read 6, iclass 10, count 2 2006.176.08:25:40.70#ibcon#end of sib2, iclass 10, count 2 2006.176.08:25:40.70#ibcon#*mode == 0, iclass 10, count 2 2006.176.08:25:40.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.176.08:25:40.70#ibcon#[27=AT01-04\r\n] 2006.176.08:25:40.70#ibcon#*before write, iclass 10, count 2 2006.176.08:25:40.70#ibcon#enter sib2, iclass 10, count 2 2006.176.08:25:40.70#ibcon#flushed, iclass 10, count 2 2006.176.08:25:40.70#ibcon#about to write, iclass 10, count 2 2006.176.08:25:40.70#ibcon#wrote, iclass 10, count 2 2006.176.08:25:40.70#ibcon#about to read 3, iclass 10, count 2 2006.176.08:25:40.73#ibcon#read 3, iclass 10, count 2 2006.176.08:25:40.73#ibcon#about to read 4, iclass 10, count 2 2006.176.08:25:40.73#ibcon#read 4, iclass 10, count 2 2006.176.08:25:40.73#ibcon#about to read 5, iclass 10, count 2 2006.176.08:25:40.73#ibcon#read 5, iclass 10, count 2 2006.176.08:25:40.73#ibcon#about to read 6, iclass 10, count 2 2006.176.08:25:40.73#ibcon#read 6, iclass 10, count 2 2006.176.08:25:40.73#ibcon#end of sib2, iclass 10, count 2 2006.176.08:25:40.73#ibcon#*after write, iclass 10, count 2 2006.176.08:25:40.73#ibcon#*before return 0, iclass 10, count 2 2006.176.08:25:40.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:40.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.176.08:25:40.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.176.08:25:40.73#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:40.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:40.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:40.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:40.85#ibcon#enter wrdev, iclass 10, count 0 2006.176.08:25:40.85#ibcon#first serial, iclass 10, count 0 2006.176.08:25:40.85#ibcon#enter sib2, iclass 10, count 0 2006.176.08:25:40.85#ibcon#flushed, iclass 10, count 0 2006.176.08:25:40.85#ibcon#about to write, iclass 10, count 0 2006.176.08:25:40.85#ibcon#wrote, iclass 10, count 0 2006.176.08:25:40.85#ibcon#about to read 3, iclass 10, count 0 2006.176.08:25:40.87#ibcon#read 3, iclass 10, count 0 2006.176.08:25:40.87#ibcon#about to read 4, iclass 10, count 0 2006.176.08:25:40.87#ibcon#read 4, iclass 10, count 0 2006.176.08:25:40.87#ibcon#about to read 5, iclass 10, count 0 2006.176.08:25:40.87#ibcon#read 5, iclass 10, count 0 2006.176.08:25:40.87#ibcon#about to read 6, iclass 10, count 0 2006.176.08:25:40.87#ibcon#read 6, iclass 10, count 0 2006.176.08:25:40.87#ibcon#end of sib2, iclass 10, count 0 2006.176.08:25:40.87#ibcon#*mode == 0, iclass 10, count 0 2006.176.08:25:40.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.176.08:25:40.87#ibcon#[27=USB\r\n] 2006.176.08:25:40.87#ibcon#*before write, iclass 10, count 0 2006.176.08:25:40.87#ibcon#enter sib2, iclass 10, count 0 2006.176.08:25:40.87#ibcon#flushed, iclass 10, count 0 2006.176.08:25:40.87#ibcon#about to write, iclass 10, count 0 2006.176.08:25:40.87#ibcon#wrote, iclass 10, count 0 2006.176.08:25:40.87#ibcon#about to read 3, iclass 10, count 0 2006.176.08:25:40.90#ibcon#read 3, iclass 10, count 0 2006.176.08:25:40.90#ibcon#about to read 4, iclass 10, count 0 2006.176.08:25:40.90#ibcon#read 4, iclass 10, count 0 2006.176.08:25:40.90#ibcon#about to read 5, iclass 10, count 0 2006.176.08:25:40.90#ibcon#read 5, iclass 10, count 0 2006.176.08:25:40.90#ibcon#about to read 6, iclass 10, count 0 2006.176.08:25:40.90#ibcon#read 6, iclass 10, count 0 2006.176.08:25:40.90#ibcon#end of sib2, iclass 10, count 0 2006.176.08:25:40.90#ibcon#*after write, iclass 10, count 0 2006.176.08:25:40.90#ibcon#*before return 0, iclass 10, count 0 2006.176.08:25:40.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:40.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.176.08:25:40.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.176.08:25:40.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.176.08:25:40.90$vc4f8/vblo=2,640.99 2006.176.08:25:40.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.176.08:25:40.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.176.08:25:40.90#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:40.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:40.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:40.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:40.90#ibcon#enter wrdev, iclass 12, count 0 2006.176.08:25:40.90#ibcon#first serial, iclass 12, count 0 2006.176.08:25:40.90#ibcon#enter sib2, iclass 12, count 0 2006.176.08:25:40.90#ibcon#flushed, iclass 12, count 0 2006.176.08:25:40.90#ibcon#about to write, iclass 12, count 0 2006.176.08:25:40.90#ibcon#wrote, iclass 12, count 0 2006.176.08:25:40.90#ibcon#about to read 3, iclass 12, count 0 2006.176.08:25:40.92#ibcon#read 3, iclass 12, count 0 2006.176.08:25:40.92#ibcon#about to read 4, iclass 12, count 0 2006.176.08:25:40.92#ibcon#read 4, iclass 12, count 0 2006.176.08:25:40.92#ibcon#about to read 5, iclass 12, count 0 2006.176.08:25:40.92#ibcon#read 5, iclass 12, count 0 2006.176.08:25:40.92#ibcon#about to read 6, iclass 12, count 0 2006.176.08:25:40.92#ibcon#read 6, iclass 12, count 0 2006.176.08:25:40.92#ibcon#end of sib2, iclass 12, count 0 2006.176.08:25:40.92#ibcon#*mode == 0, iclass 12, count 0 2006.176.08:25:40.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.176.08:25:40.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:25:40.92#ibcon#*before write, iclass 12, count 0 2006.176.08:25:40.92#ibcon#enter sib2, iclass 12, count 0 2006.176.08:25:40.92#ibcon#flushed, iclass 12, count 0 2006.176.08:25:40.92#ibcon#about to write, iclass 12, count 0 2006.176.08:25:40.92#ibcon#wrote, iclass 12, count 0 2006.176.08:25:40.92#ibcon#about to read 3, iclass 12, count 0 2006.176.08:25:40.96#ibcon#read 3, iclass 12, count 0 2006.176.08:25:40.96#ibcon#about to read 4, iclass 12, count 0 2006.176.08:25:40.96#ibcon#read 4, iclass 12, count 0 2006.176.08:25:40.96#ibcon#about to read 5, iclass 12, count 0 2006.176.08:25:40.96#ibcon#read 5, iclass 12, count 0 2006.176.08:25:40.96#ibcon#about to read 6, iclass 12, count 0 2006.176.08:25:40.96#ibcon#read 6, iclass 12, count 0 2006.176.08:25:40.96#ibcon#end of sib2, iclass 12, count 0 2006.176.08:25:40.96#ibcon#*after write, iclass 12, count 0 2006.176.08:25:40.96#ibcon#*before return 0, iclass 12, count 0 2006.176.08:25:40.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:40.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.176.08:25:40.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.176.08:25:40.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.176.08:25:40.96$vc4f8/vb=2,4 2006.176.08:25:40.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.176.08:25:40.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.176.08:25:40.96#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:40.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:41.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:41.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:41.02#ibcon#enter wrdev, iclass 14, count 2 2006.176.08:25:41.02#ibcon#first serial, iclass 14, count 2 2006.176.08:25:41.02#ibcon#enter sib2, iclass 14, count 2 2006.176.08:25:41.02#ibcon#flushed, iclass 14, count 2 2006.176.08:25:41.02#ibcon#about to write, iclass 14, count 2 2006.176.08:25:41.02#ibcon#wrote, iclass 14, count 2 2006.176.08:25:41.02#ibcon#about to read 3, iclass 14, count 2 2006.176.08:25:41.04#ibcon#read 3, iclass 14, count 2 2006.176.08:25:41.04#ibcon#about to read 4, iclass 14, count 2 2006.176.08:25:41.04#ibcon#read 4, iclass 14, count 2 2006.176.08:25:41.04#ibcon#about to read 5, iclass 14, count 2 2006.176.08:25:41.04#ibcon#read 5, iclass 14, count 2 2006.176.08:25:41.04#ibcon#about to read 6, iclass 14, count 2 2006.176.08:25:41.04#ibcon#read 6, iclass 14, count 2 2006.176.08:25:41.04#ibcon#end of sib2, iclass 14, count 2 2006.176.08:25:41.04#ibcon#*mode == 0, iclass 14, count 2 2006.176.08:25:41.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.176.08:25:41.04#ibcon#[27=AT02-04\r\n] 2006.176.08:25:41.04#ibcon#*before write, iclass 14, count 2 2006.176.08:25:41.04#ibcon#enter sib2, iclass 14, count 2 2006.176.08:25:41.04#ibcon#flushed, iclass 14, count 2 2006.176.08:25:41.04#ibcon#about to write, iclass 14, count 2 2006.176.08:25:41.04#ibcon#wrote, iclass 14, count 2 2006.176.08:25:41.04#ibcon#about to read 3, iclass 14, count 2 2006.176.08:25:41.07#ibcon#read 3, iclass 14, count 2 2006.176.08:25:41.07#ibcon#about to read 4, iclass 14, count 2 2006.176.08:25:41.07#ibcon#read 4, iclass 14, count 2 2006.176.08:25:41.07#ibcon#about to read 5, iclass 14, count 2 2006.176.08:25:41.07#ibcon#read 5, iclass 14, count 2 2006.176.08:25:41.07#ibcon#about to read 6, iclass 14, count 2 2006.176.08:25:41.07#ibcon#read 6, iclass 14, count 2 2006.176.08:25:41.07#ibcon#end of sib2, iclass 14, count 2 2006.176.08:25:41.07#ibcon#*after write, iclass 14, count 2 2006.176.08:25:41.07#ibcon#*before return 0, iclass 14, count 2 2006.176.08:25:41.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:41.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.176.08:25:41.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.176.08:25:41.07#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:41.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:41.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:41.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:41.19#ibcon#enter wrdev, iclass 14, count 0 2006.176.08:25:41.19#ibcon#first serial, iclass 14, count 0 2006.176.08:25:41.19#ibcon#enter sib2, iclass 14, count 0 2006.176.08:25:41.19#ibcon#flushed, iclass 14, count 0 2006.176.08:25:41.19#ibcon#about to write, iclass 14, count 0 2006.176.08:25:41.19#ibcon#wrote, iclass 14, count 0 2006.176.08:25:41.19#ibcon#about to read 3, iclass 14, count 0 2006.176.08:25:41.21#ibcon#read 3, iclass 14, count 0 2006.176.08:25:41.21#ibcon#about to read 4, iclass 14, count 0 2006.176.08:25:41.21#ibcon#read 4, iclass 14, count 0 2006.176.08:25:41.21#ibcon#about to read 5, iclass 14, count 0 2006.176.08:25:41.21#ibcon#read 5, iclass 14, count 0 2006.176.08:25:41.21#ibcon#about to read 6, iclass 14, count 0 2006.176.08:25:41.21#ibcon#read 6, iclass 14, count 0 2006.176.08:25:41.21#ibcon#end of sib2, iclass 14, count 0 2006.176.08:25:41.21#ibcon#*mode == 0, iclass 14, count 0 2006.176.08:25:41.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.176.08:25:41.21#ibcon#[27=USB\r\n] 2006.176.08:25:41.21#ibcon#*before write, iclass 14, count 0 2006.176.08:25:41.21#ibcon#enter sib2, iclass 14, count 0 2006.176.08:25:41.21#ibcon#flushed, iclass 14, count 0 2006.176.08:25:41.21#ibcon#about to write, iclass 14, count 0 2006.176.08:25:41.21#ibcon#wrote, iclass 14, count 0 2006.176.08:25:41.21#ibcon#about to read 3, iclass 14, count 0 2006.176.08:25:41.24#ibcon#read 3, iclass 14, count 0 2006.176.08:25:41.24#ibcon#about to read 4, iclass 14, count 0 2006.176.08:25:41.24#ibcon#read 4, iclass 14, count 0 2006.176.08:25:41.24#ibcon#about to read 5, iclass 14, count 0 2006.176.08:25:41.24#ibcon#read 5, iclass 14, count 0 2006.176.08:25:41.24#ibcon#about to read 6, iclass 14, count 0 2006.176.08:25:41.24#ibcon#read 6, iclass 14, count 0 2006.176.08:25:41.24#ibcon#end of sib2, iclass 14, count 0 2006.176.08:25:41.24#ibcon#*after write, iclass 14, count 0 2006.176.08:25:41.24#ibcon#*before return 0, iclass 14, count 0 2006.176.08:25:41.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:41.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.176.08:25:41.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.176.08:25:41.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.176.08:25:41.24$vc4f8/vblo=3,656.99 2006.176.08:25:41.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.176.08:25:41.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.176.08:25:41.24#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:41.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:41.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:41.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:41.24#ibcon#enter wrdev, iclass 16, count 0 2006.176.08:25:41.24#ibcon#first serial, iclass 16, count 0 2006.176.08:25:41.24#ibcon#enter sib2, iclass 16, count 0 2006.176.08:25:41.24#ibcon#flushed, iclass 16, count 0 2006.176.08:25:41.24#ibcon#about to write, iclass 16, count 0 2006.176.08:25:41.24#ibcon#wrote, iclass 16, count 0 2006.176.08:25:41.24#ibcon#about to read 3, iclass 16, count 0 2006.176.08:25:41.26#ibcon#read 3, iclass 16, count 0 2006.176.08:25:41.26#ibcon#about to read 4, iclass 16, count 0 2006.176.08:25:41.26#ibcon#read 4, iclass 16, count 0 2006.176.08:25:41.26#ibcon#about to read 5, iclass 16, count 0 2006.176.08:25:41.26#ibcon#read 5, iclass 16, count 0 2006.176.08:25:41.26#ibcon#about to read 6, iclass 16, count 0 2006.176.08:25:41.26#ibcon#read 6, iclass 16, count 0 2006.176.08:25:41.26#ibcon#end of sib2, iclass 16, count 0 2006.176.08:25:41.26#ibcon#*mode == 0, iclass 16, count 0 2006.176.08:25:41.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.176.08:25:41.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:25:41.26#ibcon#*before write, iclass 16, count 0 2006.176.08:25:41.26#ibcon#enter sib2, iclass 16, count 0 2006.176.08:25:41.26#ibcon#flushed, iclass 16, count 0 2006.176.08:25:41.26#ibcon#about to write, iclass 16, count 0 2006.176.08:25:41.26#ibcon#wrote, iclass 16, count 0 2006.176.08:25:41.26#ibcon#about to read 3, iclass 16, count 0 2006.176.08:25:41.30#ibcon#read 3, iclass 16, count 0 2006.176.08:25:41.30#ibcon#about to read 4, iclass 16, count 0 2006.176.08:25:41.30#ibcon#read 4, iclass 16, count 0 2006.176.08:25:41.30#ibcon#about to read 5, iclass 16, count 0 2006.176.08:25:41.30#ibcon#read 5, iclass 16, count 0 2006.176.08:25:41.30#ibcon#about to read 6, iclass 16, count 0 2006.176.08:25:41.30#ibcon#read 6, iclass 16, count 0 2006.176.08:25:41.30#ibcon#end of sib2, iclass 16, count 0 2006.176.08:25:41.30#ibcon#*after write, iclass 16, count 0 2006.176.08:25:41.30#ibcon#*before return 0, iclass 16, count 0 2006.176.08:25:41.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:41.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.176.08:25:41.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.176.08:25:41.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.176.08:25:41.30$vc4f8/vb=3,4 2006.176.08:25:41.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.176.08:25:41.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.176.08:25:41.30#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:41.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:41.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:41.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:41.36#ibcon#enter wrdev, iclass 18, count 2 2006.176.08:25:41.36#ibcon#first serial, iclass 18, count 2 2006.176.08:25:41.36#ibcon#enter sib2, iclass 18, count 2 2006.176.08:25:41.36#ibcon#flushed, iclass 18, count 2 2006.176.08:25:41.36#ibcon#about to write, iclass 18, count 2 2006.176.08:25:41.36#ibcon#wrote, iclass 18, count 2 2006.176.08:25:41.36#ibcon#about to read 3, iclass 18, count 2 2006.176.08:25:41.38#ibcon#read 3, iclass 18, count 2 2006.176.08:25:41.38#ibcon#about to read 4, iclass 18, count 2 2006.176.08:25:41.38#ibcon#read 4, iclass 18, count 2 2006.176.08:25:41.38#ibcon#about to read 5, iclass 18, count 2 2006.176.08:25:41.38#ibcon#read 5, iclass 18, count 2 2006.176.08:25:41.38#ibcon#about to read 6, iclass 18, count 2 2006.176.08:25:41.38#ibcon#read 6, iclass 18, count 2 2006.176.08:25:41.38#ibcon#end of sib2, iclass 18, count 2 2006.176.08:25:41.38#ibcon#*mode == 0, iclass 18, count 2 2006.176.08:25:41.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.176.08:25:41.38#ibcon#[27=AT03-04\r\n] 2006.176.08:25:41.38#ibcon#*before write, iclass 18, count 2 2006.176.08:25:41.38#ibcon#enter sib2, iclass 18, count 2 2006.176.08:25:41.38#ibcon#flushed, iclass 18, count 2 2006.176.08:25:41.38#ibcon#about to write, iclass 18, count 2 2006.176.08:25:41.38#ibcon#wrote, iclass 18, count 2 2006.176.08:25:41.38#ibcon#about to read 3, iclass 18, count 2 2006.176.08:25:41.41#ibcon#read 3, iclass 18, count 2 2006.176.08:25:41.41#ibcon#about to read 4, iclass 18, count 2 2006.176.08:25:41.41#ibcon#read 4, iclass 18, count 2 2006.176.08:25:41.41#ibcon#about to read 5, iclass 18, count 2 2006.176.08:25:41.41#ibcon#read 5, iclass 18, count 2 2006.176.08:25:41.41#ibcon#about to read 6, iclass 18, count 2 2006.176.08:25:41.41#ibcon#read 6, iclass 18, count 2 2006.176.08:25:41.41#ibcon#end of sib2, iclass 18, count 2 2006.176.08:25:41.41#ibcon#*after write, iclass 18, count 2 2006.176.08:25:41.41#ibcon#*before return 0, iclass 18, count 2 2006.176.08:25:41.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:41.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.176.08:25:41.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.176.08:25:41.41#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:41.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:41.53#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:41.53#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:41.53#ibcon#enter wrdev, iclass 18, count 0 2006.176.08:25:41.53#ibcon#first serial, iclass 18, count 0 2006.176.08:25:41.53#ibcon#enter sib2, iclass 18, count 0 2006.176.08:25:41.53#ibcon#flushed, iclass 18, count 0 2006.176.08:25:41.53#ibcon#about to write, iclass 18, count 0 2006.176.08:25:41.53#ibcon#wrote, iclass 18, count 0 2006.176.08:25:41.53#ibcon#about to read 3, iclass 18, count 0 2006.176.08:25:41.55#ibcon#read 3, iclass 18, count 0 2006.176.08:25:41.55#ibcon#about to read 4, iclass 18, count 0 2006.176.08:25:41.55#ibcon#read 4, iclass 18, count 0 2006.176.08:25:41.55#ibcon#about to read 5, iclass 18, count 0 2006.176.08:25:41.55#ibcon#read 5, iclass 18, count 0 2006.176.08:25:41.55#ibcon#about to read 6, iclass 18, count 0 2006.176.08:25:41.55#ibcon#read 6, iclass 18, count 0 2006.176.08:25:41.55#ibcon#end of sib2, iclass 18, count 0 2006.176.08:25:41.55#ibcon#*mode == 0, iclass 18, count 0 2006.176.08:25:41.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.176.08:25:41.55#ibcon#[27=USB\r\n] 2006.176.08:25:41.55#ibcon#*before write, iclass 18, count 0 2006.176.08:25:41.55#ibcon#enter sib2, iclass 18, count 0 2006.176.08:25:41.55#ibcon#flushed, iclass 18, count 0 2006.176.08:25:41.55#ibcon#about to write, iclass 18, count 0 2006.176.08:25:41.55#ibcon#wrote, iclass 18, count 0 2006.176.08:25:41.55#ibcon#about to read 3, iclass 18, count 0 2006.176.08:25:41.58#ibcon#read 3, iclass 18, count 0 2006.176.08:25:41.58#ibcon#about to read 4, iclass 18, count 0 2006.176.08:25:41.58#ibcon#read 4, iclass 18, count 0 2006.176.08:25:41.58#ibcon#about to read 5, iclass 18, count 0 2006.176.08:25:41.58#ibcon#read 5, iclass 18, count 0 2006.176.08:25:41.58#ibcon#about to read 6, iclass 18, count 0 2006.176.08:25:41.58#ibcon#read 6, iclass 18, count 0 2006.176.08:25:41.58#ibcon#end of sib2, iclass 18, count 0 2006.176.08:25:41.58#ibcon#*after write, iclass 18, count 0 2006.176.08:25:41.58#ibcon#*before return 0, iclass 18, count 0 2006.176.08:25:41.58#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:41.58#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.176.08:25:41.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.176.08:25:41.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.176.08:25:41.58$vc4f8/vblo=4,712.99 2006.176.08:25:41.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.176.08:25:41.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.176.08:25:41.58#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:41.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:25:41.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:25:41.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:25:41.58#ibcon#enter wrdev, iclass 20, count 0 2006.176.08:25:41.58#ibcon#first serial, iclass 20, count 0 2006.176.08:25:41.58#ibcon#enter sib2, iclass 20, count 0 2006.176.08:25:41.58#ibcon#flushed, iclass 20, count 0 2006.176.08:25:41.58#ibcon#about to write, iclass 20, count 0 2006.176.08:25:41.58#ibcon#wrote, iclass 20, count 0 2006.176.08:25:41.58#ibcon#about to read 3, iclass 20, count 0 2006.176.08:25:41.60#ibcon#read 3, iclass 20, count 0 2006.176.08:25:41.60#ibcon#about to read 4, iclass 20, count 0 2006.176.08:25:41.60#ibcon#read 4, iclass 20, count 0 2006.176.08:25:41.60#ibcon#about to read 5, iclass 20, count 0 2006.176.08:25:41.60#ibcon#read 5, iclass 20, count 0 2006.176.08:25:41.60#ibcon#about to read 6, iclass 20, count 0 2006.176.08:25:41.60#ibcon#read 6, iclass 20, count 0 2006.176.08:25:41.60#ibcon#end of sib2, iclass 20, count 0 2006.176.08:25:41.60#ibcon#*mode == 0, iclass 20, count 0 2006.176.08:25:41.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.176.08:25:41.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:25:41.60#ibcon#*before write, iclass 20, count 0 2006.176.08:25:41.60#ibcon#enter sib2, iclass 20, count 0 2006.176.08:25:41.60#ibcon#flushed, iclass 20, count 0 2006.176.08:25:41.60#ibcon#about to write, iclass 20, count 0 2006.176.08:25:41.60#ibcon#wrote, iclass 20, count 0 2006.176.08:25:41.60#ibcon#about to read 3, iclass 20, count 0 2006.176.08:25:41.64#ibcon#read 3, iclass 20, count 0 2006.176.08:25:41.64#ibcon#about to read 4, iclass 20, count 0 2006.176.08:25:41.64#ibcon#read 4, iclass 20, count 0 2006.176.08:25:41.64#ibcon#about to read 5, iclass 20, count 0 2006.176.08:25:41.64#ibcon#read 5, iclass 20, count 0 2006.176.08:25:41.64#ibcon#about to read 6, iclass 20, count 0 2006.176.08:25:41.64#ibcon#read 6, iclass 20, count 0 2006.176.08:25:41.64#ibcon#end of sib2, iclass 20, count 0 2006.176.08:25:41.64#ibcon#*after write, iclass 20, count 0 2006.176.08:25:41.64#ibcon#*before return 0, iclass 20, count 0 2006.176.08:25:41.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:25:41.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.176.08:25:41.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.176.08:25:41.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.176.08:25:41.64$vc4f8/vb=4,4 2006.176.08:25:41.64#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.176.08:25:41.64#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.176.08:25:41.64#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:41.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:25:41.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:25:41.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:25:41.70#ibcon#enter wrdev, iclass 22, count 2 2006.176.08:25:41.70#ibcon#first serial, iclass 22, count 2 2006.176.08:25:41.70#ibcon#enter sib2, iclass 22, count 2 2006.176.08:25:41.70#ibcon#flushed, iclass 22, count 2 2006.176.08:25:41.70#ibcon#about to write, iclass 22, count 2 2006.176.08:25:41.70#ibcon#wrote, iclass 22, count 2 2006.176.08:25:41.70#ibcon#about to read 3, iclass 22, count 2 2006.176.08:25:41.72#ibcon#read 3, iclass 22, count 2 2006.176.08:25:41.72#ibcon#about to read 4, iclass 22, count 2 2006.176.08:25:41.72#ibcon#read 4, iclass 22, count 2 2006.176.08:25:41.72#ibcon#about to read 5, iclass 22, count 2 2006.176.08:25:41.72#ibcon#read 5, iclass 22, count 2 2006.176.08:25:41.72#ibcon#about to read 6, iclass 22, count 2 2006.176.08:25:41.72#ibcon#read 6, iclass 22, count 2 2006.176.08:25:41.72#ibcon#end of sib2, iclass 22, count 2 2006.176.08:25:41.72#ibcon#*mode == 0, iclass 22, count 2 2006.176.08:25:41.72#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.176.08:25:41.72#ibcon#[27=AT04-04\r\n] 2006.176.08:25:41.72#ibcon#*before write, iclass 22, count 2 2006.176.08:25:41.72#ibcon#enter sib2, iclass 22, count 2 2006.176.08:25:41.72#ibcon#flushed, iclass 22, count 2 2006.176.08:25:41.72#ibcon#about to write, iclass 22, count 2 2006.176.08:25:41.72#ibcon#wrote, iclass 22, count 2 2006.176.08:25:41.72#ibcon#about to read 3, iclass 22, count 2 2006.176.08:25:41.75#ibcon#read 3, iclass 22, count 2 2006.176.08:25:41.75#ibcon#about to read 4, iclass 22, count 2 2006.176.08:25:41.75#ibcon#read 4, iclass 22, count 2 2006.176.08:25:41.75#ibcon#about to read 5, iclass 22, count 2 2006.176.08:25:41.75#ibcon#read 5, iclass 22, count 2 2006.176.08:25:41.75#ibcon#about to read 6, iclass 22, count 2 2006.176.08:25:41.75#ibcon#read 6, iclass 22, count 2 2006.176.08:25:41.75#ibcon#end of sib2, iclass 22, count 2 2006.176.08:25:41.75#ibcon#*after write, iclass 22, count 2 2006.176.08:25:41.75#ibcon#*before return 0, iclass 22, count 2 2006.176.08:25:41.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:25:41.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.176.08:25:41.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.176.08:25:41.75#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:41.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:25:41.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:25:41.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:25:41.87#ibcon#enter wrdev, iclass 22, count 0 2006.176.08:25:41.87#ibcon#first serial, iclass 22, count 0 2006.176.08:25:41.87#ibcon#enter sib2, iclass 22, count 0 2006.176.08:25:41.87#ibcon#flushed, iclass 22, count 0 2006.176.08:25:41.87#ibcon#about to write, iclass 22, count 0 2006.176.08:25:41.87#ibcon#wrote, iclass 22, count 0 2006.176.08:25:41.87#ibcon#about to read 3, iclass 22, count 0 2006.176.08:25:41.89#ibcon#read 3, iclass 22, count 0 2006.176.08:25:41.89#ibcon#about to read 4, iclass 22, count 0 2006.176.08:25:41.89#ibcon#read 4, iclass 22, count 0 2006.176.08:25:41.89#ibcon#about to read 5, iclass 22, count 0 2006.176.08:25:41.89#ibcon#read 5, iclass 22, count 0 2006.176.08:25:41.89#ibcon#about to read 6, iclass 22, count 0 2006.176.08:25:41.89#ibcon#read 6, iclass 22, count 0 2006.176.08:25:41.89#ibcon#end of sib2, iclass 22, count 0 2006.176.08:25:41.89#ibcon#*mode == 0, iclass 22, count 0 2006.176.08:25:41.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.176.08:25:41.89#ibcon#[27=USB\r\n] 2006.176.08:25:41.89#ibcon#*before write, iclass 22, count 0 2006.176.08:25:41.89#ibcon#enter sib2, iclass 22, count 0 2006.176.08:25:41.89#ibcon#flushed, iclass 22, count 0 2006.176.08:25:41.89#ibcon#about to write, iclass 22, count 0 2006.176.08:25:41.89#ibcon#wrote, iclass 22, count 0 2006.176.08:25:41.89#ibcon#about to read 3, iclass 22, count 0 2006.176.08:25:41.92#ibcon#read 3, iclass 22, count 0 2006.176.08:25:41.92#ibcon#about to read 4, iclass 22, count 0 2006.176.08:25:41.92#ibcon#read 4, iclass 22, count 0 2006.176.08:25:41.92#ibcon#about to read 5, iclass 22, count 0 2006.176.08:25:41.92#ibcon#read 5, iclass 22, count 0 2006.176.08:25:41.92#ibcon#about to read 6, iclass 22, count 0 2006.176.08:25:41.92#ibcon#read 6, iclass 22, count 0 2006.176.08:25:41.92#ibcon#end of sib2, iclass 22, count 0 2006.176.08:25:41.92#ibcon#*after write, iclass 22, count 0 2006.176.08:25:41.92#ibcon#*before return 0, iclass 22, count 0 2006.176.08:25:41.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:25:41.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.176.08:25:41.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.176.08:25:41.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.176.08:25:41.92$vc4f8/vblo=5,744.99 2006.176.08:25:41.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.176.08:25:41.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.176.08:25:41.92#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:41.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:25:41.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:25:41.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:25:41.92#ibcon#enter wrdev, iclass 24, count 0 2006.176.08:25:41.92#ibcon#first serial, iclass 24, count 0 2006.176.08:25:41.92#ibcon#enter sib2, iclass 24, count 0 2006.176.08:25:41.92#ibcon#flushed, iclass 24, count 0 2006.176.08:25:41.92#ibcon#about to write, iclass 24, count 0 2006.176.08:25:41.92#ibcon#wrote, iclass 24, count 0 2006.176.08:25:41.92#ibcon#about to read 3, iclass 24, count 0 2006.176.08:25:41.94#ibcon#read 3, iclass 24, count 0 2006.176.08:25:41.94#ibcon#about to read 4, iclass 24, count 0 2006.176.08:25:41.94#ibcon#read 4, iclass 24, count 0 2006.176.08:25:41.94#ibcon#about to read 5, iclass 24, count 0 2006.176.08:25:41.94#ibcon#read 5, iclass 24, count 0 2006.176.08:25:41.94#ibcon#about to read 6, iclass 24, count 0 2006.176.08:25:41.94#ibcon#read 6, iclass 24, count 0 2006.176.08:25:41.94#ibcon#end of sib2, iclass 24, count 0 2006.176.08:25:41.94#ibcon#*mode == 0, iclass 24, count 0 2006.176.08:25:41.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.176.08:25:41.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:25:41.94#ibcon#*before write, iclass 24, count 0 2006.176.08:25:41.94#ibcon#enter sib2, iclass 24, count 0 2006.176.08:25:41.94#ibcon#flushed, iclass 24, count 0 2006.176.08:25:41.94#ibcon#about to write, iclass 24, count 0 2006.176.08:25:41.94#ibcon#wrote, iclass 24, count 0 2006.176.08:25:41.94#ibcon#about to read 3, iclass 24, count 0 2006.176.08:25:41.98#ibcon#read 3, iclass 24, count 0 2006.176.08:25:41.98#ibcon#about to read 4, iclass 24, count 0 2006.176.08:25:41.98#ibcon#read 4, iclass 24, count 0 2006.176.08:25:41.98#ibcon#about to read 5, iclass 24, count 0 2006.176.08:25:41.98#ibcon#read 5, iclass 24, count 0 2006.176.08:25:41.98#ibcon#about to read 6, iclass 24, count 0 2006.176.08:25:41.98#ibcon#read 6, iclass 24, count 0 2006.176.08:25:41.98#ibcon#end of sib2, iclass 24, count 0 2006.176.08:25:41.98#ibcon#*after write, iclass 24, count 0 2006.176.08:25:41.98#ibcon#*before return 0, iclass 24, count 0 2006.176.08:25:41.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:25:41.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.176.08:25:41.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.176.08:25:41.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.176.08:25:41.98$vc4f8/vb=5,4 2006.176.08:25:41.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.176.08:25:41.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.176.08:25:41.98#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:41.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:25:42.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:25:42.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:25:42.04#ibcon#enter wrdev, iclass 26, count 2 2006.176.08:25:42.04#ibcon#first serial, iclass 26, count 2 2006.176.08:25:42.04#ibcon#enter sib2, iclass 26, count 2 2006.176.08:25:42.04#ibcon#flushed, iclass 26, count 2 2006.176.08:25:42.04#ibcon#about to write, iclass 26, count 2 2006.176.08:25:42.04#ibcon#wrote, iclass 26, count 2 2006.176.08:25:42.04#ibcon#about to read 3, iclass 26, count 2 2006.176.08:25:42.06#ibcon#read 3, iclass 26, count 2 2006.176.08:25:42.06#ibcon#about to read 4, iclass 26, count 2 2006.176.08:25:42.06#ibcon#read 4, iclass 26, count 2 2006.176.08:25:42.06#ibcon#about to read 5, iclass 26, count 2 2006.176.08:25:42.06#ibcon#read 5, iclass 26, count 2 2006.176.08:25:42.06#ibcon#about to read 6, iclass 26, count 2 2006.176.08:25:42.06#ibcon#read 6, iclass 26, count 2 2006.176.08:25:42.06#ibcon#end of sib2, iclass 26, count 2 2006.176.08:25:42.06#ibcon#*mode == 0, iclass 26, count 2 2006.176.08:25:42.06#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.176.08:25:42.06#ibcon#[27=AT05-04\r\n] 2006.176.08:25:42.06#ibcon#*before write, iclass 26, count 2 2006.176.08:25:42.06#ibcon#enter sib2, iclass 26, count 2 2006.176.08:25:42.06#ibcon#flushed, iclass 26, count 2 2006.176.08:25:42.06#ibcon#about to write, iclass 26, count 2 2006.176.08:25:42.06#ibcon#wrote, iclass 26, count 2 2006.176.08:25:42.06#ibcon#about to read 3, iclass 26, count 2 2006.176.08:25:42.09#ibcon#read 3, iclass 26, count 2 2006.176.08:25:42.09#ibcon#about to read 4, iclass 26, count 2 2006.176.08:25:42.09#ibcon#read 4, iclass 26, count 2 2006.176.08:25:42.09#ibcon#about to read 5, iclass 26, count 2 2006.176.08:25:42.09#ibcon#read 5, iclass 26, count 2 2006.176.08:25:42.09#ibcon#about to read 6, iclass 26, count 2 2006.176.08:25:42.09#ibcon#read 6, iclass 26, count 2 2006.176.08:25:42.09#ibcon#end of sib2, iclass 26, count 2 2006.176.08:25:42.09#ibcon#*after write, iclass 26, count 2 2006.176.08:25:42.09#ibcon#*before return 0, iclass 26, count 2 2006.176.08:25:42.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:25:42.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.176.08:25:42.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.176.08:25:42.09#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:42.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:25:42.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:25:42.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:25:42.21#ibcon#enter wrdev, iclass 26, count 0 2006.176.08:25:42.21#ibcon#first serial, iclass 26, count 0 2006.176.08:25:42.21#ibcon#enter sib2, iclass 26, count 0 2006.176.08:25:42.21#ibcon#flushed, iclass 26, count 0 2006.176.08:25:42.21#ibcon#about to write, iclass 26, count 0 2006.176.08:25:42.21#ibcon#wrote, iclass 26, count 0 2006.176.08:25:42.21#ibcon#about to read 3, iclass 26, count 0 2006.176.08:25:42.23#ibcon#read 3, iclass 26, count 0 2006.176.08:25:42.23#ibcon#about to read 4, iclass 26, count 0 2006.176.08:25:42.23#ibcon#read 4, iclass 26, count 0 2006.176.08:25:42.23#ibcon#about to read 5, iclass 26, count 0 2006.176.08:25:42.23#ibcon#read 5, iclass 26, count 0 2006.176.08:25:42.23#ibcon#about to read 6, iclass 26, count 0 2006.176.08:25:42.23#ibcon#read 6, iclass 26, count 0 2006.176.08:25:42.23#ibcon#end of sib2, iclass 26, count 0 2006.176.08:25:42.23#ibcon#*mode == 0, iclass 26, count 0 2006.176.08:25:42.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.176.08:25:42.23#ibcon#[27=USB\r\n] 2006.176.08:25:42.23#ibcon#*before write, iclass 26, count 0 2006.176.08:25:42.23#ibcon#enter sib2, iclass 26, count 0 2006.176.08:25:42.23#ibcon#flushed, iclass 26, count 0 2006.176.08:25:42.23#ibcon#about to write, iclass 26, count 0 2006.176.08:25:42.23#ibcon#wrote, iclass 26, count 0 2006.176.08:25:42.23#ibcon#about to read 3, iclass 26, count 0 2006.176.08:25:42.26#ibcon#read 3, iclass 26, count 0 2006.176.08:25:42.26#ibcon#about to read 4, iclass 26, count 0 2006.176.08:25:42.26#ibcon#read 4, iclass 26, count 0 2006.176.08:25:42.26#ibcon#about to read 5, iclass 26, count 0 2006.176.08:25:42.26#ibcon#read 5, iclass 26, count 0 2006.176.08:25:42.26#ibcon#about to read 6, iclass 26, count 0 2006.176.08:25:42.26#ibcon#read 6, iclass 26, count 0 2006.176.08:25:42.26#ibcon#end of sib2, iclass 26, count 0 2006.176.08:25:42.26#ibcon#*after write, iclass 26, count 0 2006.176.08:25:42.26#ibcon#*before return 0, iclass 26, count 0 2006.176.08:25:42.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:25:42.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.176.08:25:42.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.176.08:25:42.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.176.08:25:42.26$vc4f8/vblo=6,752.99 2006.176.08:25:42.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.176.08:25:42.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.176.08:25:42.26#ibcon#ireg 17 cls_cnt 0 2006.176.08:25:42.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:42.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:42.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:42.26#ibcon#enter wrdev, iclass 28, count 0 2006.176.08:25:42.26#ibcon#first serial, iclass 28, count 0 2006.176.08:25:42.26#ibcon#enter sib2, iclass 28, count 0 2006.176.08:25:42.26#ibcon#flushed, iclass 28, count 0 2006.176.08:25:42.26#ibcon#about to write, iclass 28, count 0 2006.176.08:25:42.26#ibcon#wrote, iclass 28, count 0 2006.176.08:25:42.26#ibcon#about to read 3, iclass 28, count 0 2006.176.08:25:42.28#ibcon#read 3, iclass 28, count 0 2006.176.08:25:42.28#ibcon#about to read 4, iclass 28, count 0 2006.176.08:25:42.28#ibcon#read 4, iclass 28, count 0 2006.176.08:25:42.28#ibcon#about to read 5, iclass 28, count 0 2006.176.08:25:42.28#ibcon#read 5, iclass 28, count 0 2006.176.08:25:42.28#ibcon#about to read 6, iclass 28, count 0 2006.176.08:25:42.28#ibcon#read 6, iclass 28, count 0 2006.176.08:25:42.28#ibcon#end of sib2, iclass 28, count 0 2006.176.08:25:42.28#ibcon#*mode == 0, iclass 28, count 0 2006.176.08:25:42.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.176.08:25:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:25:42.28#ibcon#*before write, iclass 28, count 0 2006.176.08:25:42.28#ibcon#enter sib2, iclass 28, count 0 2006.176.08:25:42.28#ibcon#flushed, iclass 28, count 0 2006.176.08:25:42.28#ibcon#about to write, iclass 28, count 0 2006.176.08:25:42.28#ibcon#wrote, iclass 28, count 0 2006.176.08:25:42.28#ibcon#about to read 3, iclass 28, count 0 2006.176.08:25:42.32#ibcon#read 3, iclass 28, count 0 2006.176.08:25:42.32#ibcon#about to read 4, iclass 28, count 0 2006.176.08:25:42.32#ibcon#read 4, iclass 28, count 0 2006.176.08:25:42.32#ibcon#about to read 5, iclass 28, count 0 2006.176.08:25:42.32#ibcon#read 5, iclass 28, count 0 2006.176.08:25:42.32#ibcon#about to read 6, iclass 28, count 0 2006.176.08:25:42.32#ibcon#read 6, iclass 28, count 0 2006.176.08:25:42.32#ibcon#end of sib2, iclass 28, count 0 2006.176.08:25:42.32#ibcon#*after write, iclass 28, count 0 2006.176.08:25:42.32#ibcon#*before return 0, iclass 28, count 0 2006.176.08:25:42.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:42.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.176.08:25:42.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.176.08:25:42.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.176.08:25:42.32$vc4f8/vb=6,4 2006.176.08:25:42.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.176.08:25:42.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.176.08:25:42.32#ibcon#ireg 11 cls_cnt 2 2006.176.08:25:42.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:42.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:42.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:42.38#ibcon#enter wrdev, iclass 30, count 2 2006.176.08:25:42.38#ibcon#first serial, iclass 30, count 2 2006.176.08:25:42.38#ibcon#enter sib2, iclass 30, count 2 2006.176.08:25:42.38#ibcon#flushed, iclass 30, count 2 2006.176.08:25:42.38#ibcon#about to write, iclass 30, count 2 2006.176.08:25:42.38#ibcon#wrote, iclass 30, count 2 2006.176.08:25:42.38#ibcon#about to read 3, iclass 30, count 2 2006.176.08:25:42.40#ibcon#read 3, iclass 30, count 2 2006.176.08:25:42.40#ibcon#about to read 4, iclass 30, count 2 2006.176.08:25:42.40#ibcon#read 4, iclass 30, count 2 2006.176.08:25:42.40#ibcon#about to read 5, iclass 30, count 2 2006.176.08:25:42.40#ibcon#read 5, iclass 30, count 2 2006.176.08:25:42.40#ibcon#about to read 6, iclass 30, count 2 2006.176.08:25:42.40#ibcon#read 6, iclass 30, count 2 2006.176.08:25:42.40#ibcon#end of sib2, iclass 30, count 2 2006.176.08:25:42.40#ibcon#*mode == 0, iclass 30, count 2 2006.176.08:25:42.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.176.08:25:42.40#ibcon#[27=AT06-04\r\n] 2006.176.08:25:42.40#ibcon#*before write, iclass 30, count 2 2006.176.08:25:42.40#ibcon#enter sib2, iclass 30, count 2 2006.176.08:25:42.40#ibcon#flushed, iclass 30, count 2 2006.176.08:25:42.40#ibcon#about to write, iclass 30, count 2 2006.176.08:25:42.40#ibcon#wrote, iclass 30, count 2 2006.176.08:25:42.40#ibcon#about to read 3, iclass 30, count 2 2006.176.08:25:42.43#ibcon#read 3, iclass 30, count 2 2006.176.08:25:42.43#ibcon#about to read 4, iclass 30, count 2 2006.176.08:25:42.43#ibcon#read 4, iclass 30, count 2 2006.176.08:25:42.43#ibcon#about to read 5, iclass 30, count 2 2006.176.08:25:42.43#ibcon#read 5, iclass 30, count 2 2006.176.08:25:42.43#ibcon#about to read 6, iclass 30, count 2 2006.176.08:25:42.43#ibcon#read 6, iclass 30, count 2 2006.176.08:25:42.43#ibcon#end of sib2, iclass 30, count 2 2006.176.08:25:42.43#ibcon#*after write, iclass 30, count 2 2006.176.08:25:42.43#ibcon#*before return 0, iclass 30, count 2 2006.176.08:25:42.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:42.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.176.08:25:42.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.176.08:25:42.43#ibcon#ireg 7 cls_cnt 0 2006.176.08:25:42.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:42.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:42.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:42.55#ibcon#enter wrdev, iclass 30, count 0 2006.176.08:25:42.55#ibcon#first serial, iclass 30, count 0 2006.176.08:25:42.55#ibcon#enter sib2, iclass 30, count 0 2006.176.08:25:42.55#ibcon#flushed, iclass 30, count 0 2006.176.08:25:42.55#ibcon#about to write, iclass 30, count 0 2006.176.08:25:42.55#ibcon#wrote, iclass 30, count 0 2006.176.08:25:42.55#ibcon#about to read 3, iclass 30, count 0 2006.176.08:25:42.57#ibcon#read 3, iclass 30, count 0 2006.176.08:25:42.57#ibcon#about to read 4, iclass 30, count 0 2006.176.08:25:42.57#ibcon#read 4, iclass 30, count 0 2006.176.08:25:42.57#ibcon#about to read 5, iclass 30, count 0 2006.176.08:25:42.57#ibcon#read 5, iclass 30, count 0 2006.176.08:25:42.57#ibcon#about to read 6, iclass 30, count 0 2006.176.08:25:42.57#ibcon#read 6, iclass 30, count 0 2006.176.08:25:42.57#ibcon#end of sib2, iclass 30, count 0 2006.176.08:25:42.57#ibcon#*mode == 0, iclass 30, count 0 2006.176.08:25:42.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.176.08:25:42.57#ibcon#[27=USB\r\n] 2006.176.08:25:42.57#ibcon#*before write, iclass 30, count 0 2006.176.08:25:42.57#ibcon#enter sib2, iclass 30, count 0 2006.176.08:25:42.57#ibcon#flushed, iclass 30, count 0 2006.176.08:25:42.57#ibcon#about to write, iclass 30, count 0 2006.176.08:25:42.57#ibcon#wrote, iclass 30, count 0 2006.176.08:25:42.57#ibcon#about to read 3, iclass 30, count 0 2006.176.08:25:42.60#ibcon#read 3, iclass 30, count 0 2006.176.08:25:42.60#ibcon#about to read 4, iclass 30, count 0 2006.176.08:25:42.60#ibcon#read 4, iclass 30, count 0 2006.176.08:25:42.60#ibcon#about to read 5, iclass 30, count 0 2006.176.08:25:42.60#ibcon#read 5, iclass 30, count 0 2006.176.08:25:42.60#ibcon#about to read 6, iclass 30, count 0 2006.176.08:25:42.60#ibcon#read 6, iclass 30, count 0 2006.176.08:25:42.60#ibcon#end of sib2, iclass 30, count 0 2006.176.08:25:42.60#ibcon#*after write, iclass 30, count 0 2006.176.08:25:42.60#ibcon#*before return 0, iclass 30, count 0 2006.176.08:25:42.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:42.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.176.08:25:42.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.176.08:25:42.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.176.08:25:42.60$vc4f8/vabw=wide 2006.176.08:25:42.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.176.08:25:42.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.176.08:25:42.60#ibcon#ireg 8 cls_cnt 0 2006.176.08:25:42.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:42.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:42.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:42.60#ibcon#enter wrdev, iclass 32, count 0 2006.176.08:25:42.60#ibcon#first serial, iclass 32, count 0 2006.176.08:25:42.60#ibcon#enter sib2, iclass 32, count 0 2006.176.08:25:42.60#ibcon#flushed, iclass 32, count 0 2006.176.08:25:42.60#ibcon#about to write, iclass 32, count 0 2006.176.08:25:42.60#ibcon#wrote, iclass 32, count 0 2006.176.08:25:42.60#ibcon#about to read 3, iclass 32, count 0 2006.176.08:25:42.62#ibcon#read 3, iclass 32, count 0 2006.176.08:25:42.62#ibcon#about to read 4, iclass 32, count 0 2006.176.08:25:42.62#ibcon#read 4, iclass 32, count 0 2006.176.08:25:42.62#ibcon#about to read 5, iclass 32, count 0 2006.176.08:25:42.62#ibcon#read 5, iclass 32, count 0 2006.176.08:25:42.62#ibcon#about to read 6, iclass 32, count 0 2006.176.08:25:42.62#ibcon#read 6, iclass 32, count 0 2006.176.08:25:42.62#ibcon#end of sib2, iclass 32, count 0 2006.176.08:25:42.62#ibcon#*mode == 0, iclass 32, count 0 2006.176.08:25:42.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.176.08:25:42.62#ibcon#[25=BW32\r\n] 2006.176.08:25:42.62#ibcon#*before write, iclass 32, count 0 2006.176.08:25:42.62#ibcon#enter sib2, iclass 32, count 0 2006.176.08:25:42.62#ibcon#flushed, iclass 32, count 0 2006.176.08:25:42.62#ibcon#about to write, iclass 32, count 0 2006.176.08:25:42.62#ibcon#wrote, iclass 32, count 0 2006.176.08:25:42.62#ibcon#about to read 3, iclass 32, count 0 2006.176.08:25:42.65#ibcon#read 3, iclass 32, count 0 2006.176.08:25:42.65#ibcon#about to read 4, iclass 32, count 0 2006.176.08:25:42.65#ibcon#read 4, iclass 32, count 0 2006.176.08:25:42.65#ibcon#about to read 5, iclass 32, count 0 2006.176.08:25:42.65#ibcon#read 5, iclass 32, count 0 2006.176.08:25:42.65#ibcon#about to read 6, iclass 32, count 0 2006.176.08:25:42.65#ibcon#read 6, iclass 32, count 0 2006.176.08:25:42.65#ibcon#end of sib2, iclass 32, count 0 2006.176.08:25:42.65#ibcon#*after write, iclass 32, count 0 2006.176.08:25:42.65#ibcon#*before return 0, iclass 32, count 0 2006.176.08:25:42.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:42.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.176.08:25:42.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.176.08:25:42.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.176.08:25:42.65$vc4f8/vbbw=wide 2006.176.08:25:42.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.176.08:25:42.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.176.08:25:42.65#ibcon#ireg 8 cls_cnt 0 2006.176.08:25:42.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:25:42.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:25:42.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:25:42.72#ibcon#enter wrdev, iclass 34, count 0 2006.176.08:25:42.72#ibcon#first serial, iclass 34, count 0 2006.176.08:25:42.72#ibcon#enter sib2, iclass 34, count 0 2006.176.08:25:42.72#ibcon#flushed, iclass 34, count 0 2006.176.08:25:42.72#ibcon#about to write, iclass 34, count 0 2006.176.08:25:42.72#ibcon#wrote, iclass 34, count 0 2006.176.08:25:42.72#ibcon#about to read 3, iclass 34, count 0 2006.176.08:25:42.74#ibcon#read 3, iclass 34, count 0 2006.176.08:25:42.74#ibcon#about to read 4, iclass 34, count 0 2006.176.08:25:42.74#ibcon#read 4, iclass 34, count 0 2006.176.08:25:42.74#ibcon#about to read 5, iclass 34, count 0 2006.176.08:25:42.74#ibcon#read 5, iclass 34, count 0 2006.176.08:25:42.74#ibcon#about to read 6, iclass 34, count 0 2006.176.08:25:42.74#ibcon#read 6, iclass 34, count 0 2006.176.08:25:42.74#ibcon#end of sib2, iclass 34, count 0 2006.176.08:25:42.74#ibcon#*mode == 0, iclass 34, count 0 2006.176.08:25:42.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.176.08:25:42.74#ibcon#[27=BW32\r\n] 2006.176.08:25:42.74#ibcon#*before write, iclass 34, count 0 2006.176.08:25:42.74#ibcon#enter sib2, iclass 34, count 0 2006.176.08:25:42.74#ibcon#flushed, iclass 34, count 0 2006.176.08:25:42.74#ibcon#about to write, iclass 34, count 0 2006.176.08:25:42.74#ibcon#wrote, iclass 34, count 0 2006.176.08:25:42.74#ibcon#about to read 3, iclass 34, count 0 2006.176.08:25:42.77#ibcon#read 3, iclass 34, count 0 2006.176.08:25:42.77#ibcon#about to read 4, iclass 34, count 0 2006.176.08:25:42.77#ibcon#read 4, iclass 34, count 0 2006.176.08:25:42.77#ibcon#about to read 5, iclass 34, count 0 2006.176.08:25:42.77#ibcon#read 5, iclass 34, count 0 2006.176.08:25:42.77#ibcon#about to read 6, iclass 34, count 0 2006.176.08:25:42.77#ibcon#read 6, iclass 34, count 0 2006.176.08:25:42.77#ibcon#end of sib2, iclass 34, count 0 2006.176.08:25:42.77#ibcon#*after write, iclass 34, count 0 2006.176.08:25:42.77#ibcon#*before return 0, iclass 34, count 0 2006.176.08:25:42.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:25:42.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.176.08:25:42.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.176.08:25:42.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.176.08:25:42.77$4f8m12a/ifd4f 2006.176.08:25:42.77$ifd4f/lo= 2006.176.08:25:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:25:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:25:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:25:42.77$ifd4f/patch= 2006.176.08:25:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:25:42.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:25:42.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:25:42.77$4f8m12a/"form=m,16.000,1:2 2006.176.08:25:42.77$4f8m12a/"tpicd 2006.176.08:25:42.77$4f8m12a/echo=off 2006.176.08:25:42.77$4f8m12a/xlog=off 2006.176.08:25:42.77:!2006.176.08:26:10 2006.176.08:25:50.14#trakl#Source acquired 2006.176.08:25:52.14#flagr#flagr/antenna,acquired 2006.176.08:26:10.00:preob 2006.176.08:26:11.14/onsource/TRACKING 2006.176.08:26:11.14:!2006.176.08:26:20 2006.176.08:26:20.00:data_valid=on 2006.176.08:26:20.00:midob 2006.176.08:26:20.14/onsource/TRACKING 2006.176.08:26:20.14/wx/23.72,1008.5,93 2006.176.08:26:20.29/cable/+6.4935E-03 2006.176.08:26:21.38/va/01,08,usb,yes,34,36 2006.176.08:26:21.38/va/02,07,usb,yes,34,36 2006.176.08:26:21.38/va/03,06,usb,yes,36,36 2006.176.08:26:21.38/va/04,07,usb,yes,35,38 2006.176.08:26:21.38/va/05,07,usb,yes,37,39 2006.176.08:26:21.38/va/06,06,usb,yes,36,36 2006.176.08:26:21.38/va/07,06,usb,yes,37,36 2006.176.08:26:21.38/va/08,06,usb,yes,39,39 2006.176.08:26:21.61/valo/01,532.99,yes,locked 2006.176.08:26:21.61/valo/02,572.99,yes,locked 2006.176.08:26:21.61/valo/03,672.99,yes,locked 2006.176.08:26:21.61/valo/04,832.99,yes,locked 2006.176.08:26:21.61/valo/05,652.99,yes,locked 2006.176.08:26:21.61/valo/06,772.99,yes,locked 2006.176.08:26:21.61/valo/07,832.99,yes,locked 2006.176.08:26:21.61/valo/08,852.99,yes,locked 2006.176.08:26:22.70/vb/01,04,usb,yes,32,30 2006.176.08:26:22.70/vb/02,04,usb,yes,34,35 2006.176.08:26:22.70/vb/03,04,usb,yes,30,34 2006.176.08:26:22.70/vb/04,04,usb,yes,31,31 2006.176.08:26:22.70/vb/05,04,usb,yes,29,33 2006.176.08:26:22.70/vb/06,04,usb,yes,30,33 2006.176.08:26:22.70/vb/07,04,usb,yes,33,32 2006.176.08:26:22.70/vb/08,04,usb,yes,30,33 2006.176.08:26:22.94/vblo/01,632.99,yes,locked 2006.176.08:26:22.94/vblo/02,640.99,yes,locked 2006.176.08:26:22.94/vblo/03,656.99,yes,locked 2006.176.08:26:22.94/vblo/04,712.99,yes,locked 2006.176.08:26:22.94/vblo/05,744.99,yes,locked 2006.176.08:26:22.94/vblo/06,752.99,yes,locked 2006.176.08:26:22.94/vblo/07,734.99,yes,locked 2006.176.08:26:22.94/vblo/08,744.99,yes,locked 2006.176.08:26:23.09/vabw/8 2006.176.08:26:23.24/vbbw/8 2006.176.08:26:23.48/xfe/off,on,15.5 2006.176.08:26:23.85/ifatt/23,28,28,28 2006.176.08:26:24.07/fmout-gps/S +3.68E-07 2006.176.08:26:24.14:!2006.176.08:27:20 2006.176.08:27:20.00:data_valid=off 2006.176.08:27:20.00:postob 2006.176.08:27:20.08/cable/+6.4947E-03 2006.176.08:27:20.08/wx/23.71,1008.5,93 2006.176.08:27:21.08/fmout-gps/S +3.67E-07 2006.176.08:27:21.08:scan_name=176-0828,k06176,60 2006.176.08:27:21.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.176.08:27:21.14#flagr#flagr/antenna,new-source 2006.176.08:27:22.14:checkk5 2006.176.08:27:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.176.08:27:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.176.08:27:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.176.08:27:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.176.08:27:24.01/chk_obsdata//k5ts1/T1760826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:27:24.38/chk_obsdata//k5ts2/T1760826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:27:24.76/chk_obsdata//k5ts3/T1760826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:27:25.13/chk_obsdata//k5ts4/T1760826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:27:25.82/k5log//k5ts1_log_newline 2006.176.08:27:26.51/k5log//k5ts2_log_newline 2006.176.08:27:27.20/k5log//k5ts3_log_newline 2006.176.08:27:27.89/k5log//k5ts4_log_newline 2006.176.08:27:27.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:27:27.91:4f8m12a=3 2006.176.08:27:27.91$4f8m12a/echo=on 2006.176.08:27:27.91$4f8m12a/pcalon 2006.176.08:27:27.91$pcalon/"no phase cal control is implemented here 2006.176.08:27:27.91$4f8m12a/"tpicd=stop 2006.176.08:27:27.91$4f8m12a/vc4f8 2006.176.08:27:27.91$vc4f8/valo=1,532.99 2006.176.08:27:27.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.176.08:27:27.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.176.08:27:27.91#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:27.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:27:27.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:27:27.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:27:27.91#ibcon#enter wrdev, iclass 3, count 0 2006.176.08:27:27.91#ibcon#first serial, iclass 3, count 0 2006.176.08:27:27.91#ibcon#enter sib2, iclass 3, count 0 2006.176.08:27:27.91#ibcon#flushed, iclass 3, count 0 2006.176.08:27:27.91#ibcon#about to write, iclass 3, count 0 2006.176.08:27:27.91#ibcon#wrote, iclass 3, count 0 2006.176.08:27:27.91#ibcon#about to read 3, iclass 3, count 0 2006.176.08:27:27.96#ibcon#read 3, iclass 3, count 0 2006.176.08:27:27.96#ibcon#about to read 4, iclass 3, count 0 2006.176.08:27:27.96#ibcon#read 4, iclass 3, count 0 2006.176.08:27:27.96#ibcon#about to read 5, iclass 3, count 0 2006.176.08:27:27.96#ibcon#read 5, iclass 3, count 0 2006.176.08:27:27.96#ibcon#about to read 6, iclass 3, count 0 2006.176.08:27:27.96#ibcon#read 6, iclass 3, count 0 2006.176.08:27:27.96#ibcon#end of sib2, iclass 3, count 0 2006.176.08:27:27.96#ibcon#*mode == 0, iclass 3, count 0 2006.176.08:27:27.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.176.08:27:27.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.176.08:27:27.96#ibcon#*before write, iclass 3, count 0 2006.176.08:27:27.96#ibcon#enter sib2, iclass 3, count 0 2006.176.08:27:27.96#ibcon#flushed, iclass 3, count 0 2006.176.08:27:27.96#ibcon#about to write, iclass 3, count 0 2006.176.08:27:27.96#ibcon#wrote, iclass 3, count 0 2006.176.08:27:27.96#ibcon#about to read 3, iclass 3, count 0 2006.176.08:27:28.01#ibcon#read 3, iclass 3, count 0 2006.176.08:27:28.01#ibcon#about to read 4, iclass 3, count 0 2006.176.08:27:28.01#ibcon#read 4, iclass 3, count 0 2006.176.08:27:28.01#ibcon#about to read 5, iclass 3, count 0 2006.176.08:27:28.01#ibcon#read 5, iclass 3, count 0 2006.176.08:27:28.01#ibcon#about to read 6, iclass 3, count 0 2006.176.08:27:28.01#ibcon#read 6, iclass 3, count 0 2006.176.08:27:28.01#ibcon#end of sib2, iclass 3, count 0 2006.176.08:27:28.01#ibcon#*after write, iclass 3, count 0 2006.176.08:27:28.01#ibcon#*before return 0, iclass 3, count 0 2006.176.08:27:28.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:27:28.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.176.08:27:28.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.176.08:27:28.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.176.08:27:28.01$vc4f8/va=1,8 2006.176.08:27:28.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.176.08:27:28.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.176.08:27:28.01#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:28.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:27:28.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:27:28.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:27:28.01#ibcon#enter wrdev, iclass 5, count 2 2006.176.08:27:28.01#ibcon#first serial, iclass 5, count 2 2006.176.08:27:28.01#ibcon#enter sib2, iclass 5, count 2 2006.176.08:27:28.01#ibcon#flushed, iclass 5, count 2 2006.176.08:27:28.01#ibcon#about to write, iclass 5, count 2 2006.176.08:27:28.01#ibcon#wrote, iclass 5, count 2 2006.176.08:27:28.01#ibcon#about to read 3, iclass 5, count 2 2006.176.08:27:28.03#ibcon#read 3, iclass 5, count 2 2006.176.08:27:28.03#ibcon#about to read 4, iclass 5, count 2 2006.176.08:27:28.03#ibcon#read 4, iclass 5, count 2 2006.176.08:27:28.03#ibcon#about to read 5, iclass 5, count 2 2006.176.08:27:28.03#ibcon#read 5, iclass 5, count 2 2006.176.08:27:28.03#ibcon#about to read 6, iclass 5, count 2 2006.176.08:27:28.03#ibcon#read 6, iclass 5, count 2 2006.176.08:27:28.03#ibcon#end of sib2, iclass 5, count 2 2006.176.08:27:28.03#ibcon#*mode == 0, iclass 5, count 2 2006.176.08:27:28.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.176.08:27:28.03#ibcon#[25=AT01-08\r\n] 2006.176.08:27:28.03#ibcon#*before write, iclass 5, count 2 2006.176.08:27:28.03#ibcon#enter sib2, iclass 5, count 2 2006.176.08:27:28.03#ibcon#flushed, iclass 5, count 2 2006.176.08:27:28.03#ibcon#about to write, iclass 5, count 2 2006.176.08:27:28.03#ibcon#wrote, iclass 5, count 2 2006.176.08:27:28.03#ibcon#about to read 3, iclass 5, count 2 2006.176.08:27:28.06#ibcon#read 3, iclass 5, count 2 2006.176.08:27:28.06#ibcon#about to read 4, iclass 5, count 2 2006.176.08:27:28.06#ibcon#read 4, iclass 5, count 2 2006.176.08:27:28.06#ibcon#about to read 5, iclass 5, count 2 2006.176.08:27:28.06#ibcon#read 5, iclass 5, count 2 2006.176.08:27:28.06#ibcon#about to read 6, iclass 5, count 2 2006.176.08:27:28.06#ibcon#read 6, iclass 5, count 2 2006.176.08:27:28.06#ibcon#end of sib2, iclass 5, count 2 2006.176.08:27:28.06#ibcon#*after write, iclass 5, count 2 2006.176.08:27:28.06#ibcon#*before return 0, iclass 5, count 2 2006.176.08:27:28.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:27:28.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.176.08:27:28.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.176.08:27:28.06#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:28.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:27:28.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:27:28.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:27:28.18#ibcon#enter wrdev, iclass 5, count 0 2006.176.08:27:28.18#ibcon#first serial, iclass 5, count 0 2006.176.08:27:28.18#ibcon#enter sib2, iclass 5, count 0 2006.176.08:27:28.18#ibcon#flushed, iclass 5, count 0 2006.176.08:27:28.18#ibcon#about to write, iclass 5, count 0 2006.176.08:27:28.18#ibcon#wrote, iclass 5, count 0 2006.176.08:27:28.18#ibcon#about to read 3, iclass 5, count 0 2006.176.08:27:28.20#ibcon#read 3, iclass 5, count 0 2006.176.08:27:28.20#ibcon#about to read 4, iclass 5, count 0 2006.176.08:27:28.20#ibcon#read 4, iclass 5, count 0 2006.176.08:27:28.20#ibcon#about to read 5, iclass 5, count 0 2006.176.08:27:28.20#ibcon#read 5, iclass 5, count 0 2006.176.08:27:28.20#ibcon#about to read 6, iclass 5, count 0 2006.176.08:27:28.20#ibcon#read 6, iclass 5, count 0 2006.176.08:27:28.20#ibcon#end of sib2, iclass 5, count 0 2006.176.08:27:28.20#ibcon#*mode == 0, iclass 5, count 0 2006.176.08:27:28.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.176.08:27:28.20#ibcon#[25=USB\r\n] 2006.176.08:27:28.20#ibcon#*before write, iclass 5, count 0 2006.176.08:27:28.20#ibcon#enter sib2, iclass 5, count 0 2006.176.08:27:28.20#ibcon#flushed, iclass 5, count 0 2006.176.08:27:28.20#ibcon#about to write, iclass 5, count 0 2006.176.08:27:28.20#ibcon#wrote, iclass 5, count 0 2006.176.08:27:28.20#ibcon#about to read 3, iclass 5, count 0 2006.176.08:27:28.23#ibcon#read 3, iclass 5, count 0 2006.176.08:27:28.23#ibcon#about to read 4, iclass 5, count 0 2006.176.08:27:28.23#ibcon#read 4, iclass 5, count 0 2006.176.08:27:28.23#ibcon#about to read 5, iclass 5, count 0 2006.176.08:27:28.23#ibcon#read 5, iclass 5, count 0 2006.176.08:27:28.23#ibcon#about to read 6, iclass 5, count 0 2006.176.08:27:28.23#ibcon#read 6, iclass 5, count 0 2006.176.08:27:28.23#ibcon#end of sib2, iclass 5, count 0 2006.176.08:27:28.23#ibcon#*after write, iclass 5, count 0 2006.176.08:27:28.23#ibcon#*before return 0, iclass 5, count 0 2006.176.08:27:28.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:27:28.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.176.08:27:28.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.176.08:27:28.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.176.08:27:28.23$vc4f8/valo=2,572.99 2006.176.08:27:28.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.176.08:27:28.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.176.08:27:28.23#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:28.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:27:28.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:27:28.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:27:28.23#ibcon#enter wrdev, iclass 7, count 0 2006.176.08:27:28.23#ibcon#first serial, iclass 7, count 0 2006.176.08:27:28.23#ibcon#enter sib2, iclass 7, count 0 2006.176.08:27:28.23#ibcon#flushed, iclass 7, count 0 2006.176.08:27:28.23#ibcon#about to write, iclass 7, count 0 2006.176.08:27:28.23#ibcon#wrote, iclass 7, count 0 2006.176.08:27:28.23#ibcon#about to read 3, iclass 7, count 0 2006.176.08:27:28.25#ibcon#read 3, iclass 7, count 0 2006.176.08:27:28.25#ibcon#about to read 4, iclass 7, count 0 2006.176.08:27:28.25#ibcon#read 4, iclass 7, count 0 2006.176.08:27:28.25#ibcon#about to read 5, iclass 7, count 0 2006.176.08:27:28.25#ibcon#read 5, iclass 7, count 0 2006.176.08:27:28.25#ibcon#about to read 6, iclass 7, count 0 2006.176.08:27:28.25#ibcon#read 6, iclass 7, count 0 2006.176.08:27:28.25#ibcon#end of sib2, iclass 7, count 0 2006.176.08:27:28.25#ibcon#*mode == 0, iclass 7, count 0 2006.176.08:27:28.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.176.08:27:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.176.08:27:28.25#ibcon#*before write, iclass 7, count 0 2006.176.08:27:28.25#ibcon#enter sib2, iclass 7, count 0 2006.176.08:27:28.25#ibcon#flushed, iclass 7, count 0 2006.176.08:27:28.25#ibcon#about to write, iclass 7, count 0 2006.176.08:27:28.25#ibcon#wrote, iclass 7, count 0 2006.176.08:27:28.25#ibcon#about to read 3, iclass 7, count 0 2006.176.08:27:28.29#ibcon#read 3, iclass 7, count 0 2006.176.08:27:28.29#ibcon#about to read 4, iclass 7, count 0 2006.176.08:27:28.29#ibcon#read 4, iclass 7, count 0 2006.176.08:27:28.29#ibcon#about to read 5, iclass 7, count 0 2006.176.08:27:28.29#ibcon#read 5, iclass 7, count 0 2006.176.08:27:28.29#ibcon#about to read 6, iclass 7, count 0 2006.176.08:27:28.29#ibcon#read 6, iclass 7, count 0 2006.176.08:27:28.29#ibcon#end of sib2, iclass 7, count 0 2006.176.08:27:28.29#ibcon#*after write, iclass 7, count 0 2006.176.08:27:28.29#ibcon#*before return 0, iclass 7, count 0 2006.176.08:27:28.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:27:28.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.176.08:27:28.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.176.08:27:28.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.176.08:27:28.29$vc4f8/va=2,7 2006.176.08:27:28.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.176.08:27:28.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.176.08:27:28.29#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:28.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:28.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:28.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:28.35#ibcon#enter wrdev, iclass 11, count 2 2006.176.08:27:28.35#ibcon#first serial, iclass 11, count 2 2006.176.08:27:28.35#ibcon#enter sib2, iclass 11, count 2 2006.176.08:27:28.35#ibcon#flushed, iclass 11, count 2 2006.176.08:27:28.35#ibcon#about to write, iclass 11, count 2 2006.176.08:27:28.35#ibcon#wrote, iclass 11, count 2 2006.176.08:27:28.35#ibcon#about to read 3, iclass 11, count 2 2006.176.08:27:28.37#ibcon#read 3, iclass 11, count 2 2006.176.08:27:28.37#ibcon#about to read 4, iclass 11, count 2 2006.176.08:27:28.37#ibcon#read 4, iclass 11, count 2 2006.176.08:27:28.37#ibcon#about to read 5, iclass 11, count 2 2006.176.08:27:28.37#ibcon#read 5, iclass 11, count 2 2006.176.08:27:28.37#ibcon#about to read 6, iclass 11, count 2 2006.176.08:27:28.37#ibcon#read 6, iclass 11, count 2 2006.176.08:27:28.37#ibcon#end of sib2, iclass 11, count 2 2006.176.08:27:28.37#ibcon#*mode == 0, iclass 11, count 2 2006.176.08:27:28.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.176.08:27:28.37#ibcon#[25=AT02-07\r\n] 2006.176.08:27:28.37#ibcon#*before write, iclass 11, count 2 2006.176.08:27:28.37#ibcon#enter sib2, iclass 11, count 2 2006.176.08:27:28.37#ibcon#flushed, iclass 11, count 2 2006.176.08:27:28.37#ibcon#about to write, iclass 11, count 2 2006.176.08:27:28.37#ibcon#wrote, iclass 11, count 2 2006.176.08:27:28.37#ibcon#about to read 3, iclass 11, count 2 2006.176.08:27:28.40#ibcon#read 3, iclass 11, count 2 2006.176.08:27:28.40#ibcon#about to read 4, iclass 11, count 2 2006.176.08:27:28.40#ibcon#read 4, iclass 11, count 2 2006.176.08:27:28.40#ibcon#about to read 5, iclass 11, count 2 2006.176.08:27:28.40#ibcon#read 5, iclass 11, count 2 2006.176.08:27:28.40#ibcon#about to read 6, iclass 11, count 2 2006.176.08:27:28.40#ibcon#read 6, iclass 11, count 2 2006.176.08:27:28.40#ibcon#end of sib2, iclass 11, count 2 2006.176.08:27:28.40#ibcon#*after write, iclass 11, count 2 2006.176.08:27:28.40#ibcon#*before return 0, iclass 11, count 2 2006.176.08:27:28.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:28.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:28.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.176.08:27:28.40#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:28.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:28.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:28.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:28.52#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:27:28.52#ibcon#first serial, iclass 11, count 0 2006.176.08:27:28.52#ibcon#enter sib2, iclass 11, count 0 2006.176.08:27:28.52#ibcon#flushed, iclass 11, count 0 2006.176.08:27:28.52#ibcon#about to write, iclass 11, count 0 2006.176.08:27:28.52#ibcon#wrote, iclass 11, count 0 2006.176.08:27:28.52#ibcon#about to read 3, iclass 11, count 0 2006.176.08:27:28.54#ibcon#read 3, iclass 11, count 0 2006.176.08:27:28.54#ibcon#about to read 4, iclass 11, count 0 2006.176.08:27:28.54#ibcon#read 4, iclass 11, count 0 2006.176.08:27:28.54#ibcon#about to read 5, iclass 11, count 0 2006.176.08:27:28.54#ibcon#read 5, iclass 11, count 0 2006.176.08:27:28.54#ibcon#about to read 6, iclass 11, count 0 2006.176.08:27:28.54#ibcon#read 6, iclass 11, count 0 2006.176.08:27:28.54#ibcon#end of sib2, iclass 11, count 0 2006.176.08:27:28.54#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:27:28.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:27:28.54#ibcon#[25=USB\r\n] 2006.176.08:27:28.54#ibcon#*before write, iclass 11, count 0 2006.176.08:27:28.54#ibcon#enter sib2, iclass 11, count 0 2006.176.08:27:28.54#ibcon#flushed, iclass 11, count 0 2006.176.08:27:28.54#ibcon#about to write, iclass 11, count 0 2006.176.08:27:28.54#ibcon#wrote, iclass 11, count 0 2006.176.08:27:28.54#ibcon#about to read 3, iclass 11, count 0 2006.176.08:27:28.57#ibcon#read 3, iclass 11, count 0 2006.176.08:27:28.57#ibcon#about to read 4, iclass 11, count 0 2006.176.08:27:28.57#ibcon#read 4, iclass 11, count 0 2006.176.08:27:28.57#ibcon#about to read 5, iclass 11, count 0 2006.176.08:27:28.57#ibcon#read 5, iclass 11, count 0 2006.176.08:27:28.57#ibcon#about to read 6, iclass 11, count 0 2006.176.08:27:28.57#ibcon#read 6, iclass 11, count 0 2006.176.08:27:28.57#ibcon#end of sib2, iclass 11, count 0 2006.176.08:27:28.57#ibcon#*after write, iclass 11, count 0 2006.176.08:27:28.57#ibcon#*before return 0, iclass 11, count 0 2006.176.08:27:28.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:28.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:28.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:27:28.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:27:28.57$vc4f8/valo=3,672.99 2006.176.08:27:28.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.08:27:28.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.08:27:28.57#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:28.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:28.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:28.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:28.57#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:27:28.57#ibcon#first serial, iclass 13, count 0 2006.176.08:27:28.57#ibcon#enter sib2, iclass 13, count 0 2006.176.08:27:28.57#ibcon#flushed, iclass 13, count 0 2006.176.08:27:28.57#ibcon#about to write, iclass 13, count 0 2006.176.08:27:28.57#ibcon#wrote, iclass 13, count 0 2006.176.08:27:28.57#ibcon#about to read 3, iclass 13, count 0 2006.176.08:27:28.59#ibcon#read 3, iclass 13, count 0 2006.176.08:27:28.59#ibcon#about to read 4, iclass 13, count 0 2006.176.08:27:28.59#ibcon#read 4, iclass 13, count 0 2006.176.08:27:28.59#ibcon#about to read 5, iclass 13, count 0 2006.176.08:27:28.59#ibcon#read 5, iclass 13, count 0 2006.176.08:27:28.59#ibcon#about to read 6, iclass 13, count 0 2006.176.08:27:28.59#ibcon#read 6, iclass 13, count 0 2006.176.08:27:28.59#ibcon#end of sib2, iclass 13, count 0 2006.176.08:27:28.59#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:27:28.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:27:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.176.08:27:28.59#ibcon#*before write, iclass 13, count 0 2006.176.08:27:28.59#ibcon#enter sib2, iclass 13, count 0 2006.176.08:27:28.59#ibcon#flushed, iclass 13, count 0 2006.176.08:27:28.59#ibcon#about to write, iclass 13, count 0 2006.176.08:27:28.59#ibcon#wrote, iclass 13, count 0 2006.176.08:27:28.59#ibcon#about to read 3, iclass 13, count 0 2006.176.08:27:28.63#ibcon#read 3, iclass 13, count 0 2006.176.08:27:28.63#ibcon#about to read 4, iclass 13, count 0 2006.176.08:27:28.63#ibcon#read 4, iclass 13, count 0 2006.176.08:27:28.63#ibcon#about to read 5, iclass 13, count 0 2006.176.08:27:28.63#ibcon#read 5, iclass 13, count 0 2006.176.08:27:28.63#ibcon#about to read 6, iclass 13, count 0 2006.176.08:27:28.63#ibcon#read 6, iclass 13, count 0 2006.176.08:27:28.63#ibcon#end of sib2, iclass 13, count 0 2006.176.08:27:28.63#ibcon#*after write, iclass 13, count 0 2006.176.08:27:28.63#ibcon#*before return 0, iclass 13, count 0 2006.176.08:27:28.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:28.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:28.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:27:28.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:27:28.63$vc4f8/va=3,6 2006.176.08:27:28.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.176.08:27:28.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.176.08:27:28.63#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:28.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:28.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:28.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:28.69#ibcon#enter wrdev, iclass 15, count 2 2006.176.08:27:28.69#ibcon#first serial, iclass 15, count 2 2006.176.08:27:28.69#ibcon#enter sib2, iclass 15, count 2 2006.176.08:27:28.69#ibcon#flushed, iclass 15, count 2 2006.176.08:27:28.69#ibcon#about to write, iclass 15, count 2 2006.176.08:27:28.69#ibcon#wrote, iclass 15, count 2 2006.176.08:27:28.69#ibcon#about to read 3, iclass 15, count 2 2006.176.08:27:28.71#ibcon#read 3, iclass 15, count 2 2006.176.08:27:28.71#ibcon#about to read 4, iclass 15, count 2 2006.176.08:27:28.71#ibcon#read 4, iclass 15, count 2 2006.176.08:27:28.71#ibcon#about to read 5, iclass 15, count 2 2006.176.08:27:28.71#ibcon#read 5, iclass 15, count 2 2006.176.08:27:28.71#ibcon#about to read 6, iclass 15, count 2 2006.176.08:27:28.71#ibcon#read 6, iclass 15, count 2 2006.176.08:27:28.71#ibcon#end of sib2, iclass 15, count 2 2006.176.08:27:28.71#ibcon#*mode == 0, iclass 15, count 2 2006.176.08:27:28.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.176.08:27:28.71#ibcon#[25=AT03-06\r\n] 2006.176.08:27:28.71#ibcon#*before write, iclass 15, count 2 2006.176.08:27:28.71#ibcon#enter sib2, iclass 15, count 2 2006.176.08:27:28.71#ibcon#flushed, iclass 15, count 2 2006.176.08:27:28.71#ibcon#about to write, iclass 15, count 2 2006.176.08:27:28.71#ibcon#wrote, iclass 15, count 2 2006.176.08:27:28.71#ibcon#about to read 3, iclass 15, count 2 2006.176.08:27:28.74#ibcon#read 3, iclass 15, count 2 2006.176.08:27:28.74#ibcon#about to read 4, iclass 15, count 2 2006.176.08:27:28.74#ibcon#read 4, iclass 15, count 2 2006.176.08:27:28.74#ibcon#about to read 5, iclass 15, count 2 2006.176.08:27:28.74#ibcon#read 5, iclass 15, count 2 2006.176.08:27:28.74#ibcon#about to read 6, iclass 15, count 2 2006.176.08:27:28.74#ibcon#read 6, iclass 15, count 2 2006.176.08:27:28.74#ibcon#end of sib2, iclass 15, count 2 2006.176.08:27:28.74#ibcon#*after write, iclass 15, count 2 2006.176.08:27:28.74#ibcon#*before return 0, iclass 15, count 2 2006.176.08:27:28.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:28.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:28.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.176.08:27:28.74#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:28.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:28.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:28.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:28.86#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:27:28.86#ibcon#first serial, iclass 15, count 0 2006.176.08:27:28.86#ibcon#enter sib2, iclass 15, count 0 2006.176.08:27:28.86#ibcon#flushed, iclass 15, count 0 2006.176.08:27:28.86#ibcon#about to write, iclass 15, count 0 2006.176.08:27:28.86#ibcon#wrote, iclass 15, count 0 2006.176.08:27:28.86#ibcon#about to read 3, iclass 15, count 0 2006.176.08:27:28.88#ibcon#read 3, iclass 15, count 0 2006.176.08:27:28.88#ibcon#about to read 4, iclass 15, count 0 2006.176.08:27:28.88#ibcon#read 4, iclass 15, count 0 2006.176.08:27:28.88#ibcon#about to read 5, iclass 15, count 0 2006.176.08:27:28.88#ibcon#read 5, iclass 15, count 0 2006.176.08:27:28.88#ibcon#about to read 6, iclass 15, count 0 2006.176.08:27:28.88#ibcon#read 6, iclass 15, count 0 2006.176.08:27:28.88#ibcon#end of sib2, iclass 15, count 0 2006.176.08:27:28.88#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:27:28.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:27:28.88#ibcon#[25=USB\r\n] 2006.176.08:27:28.88#ibcon#*before write, iclass 15, count 0 2006.176.08:27:28.88#ibcon#enter sib2, iclass 15, count 0 2006.176.08:27:28.88#ibcon#flushed, iclass 15, count 0 2006.176.08:27:28.88#ibcon#about to write, iclass 15, count 0 2006.176.08:27:28.88#ibcon#wrote, iclass 15, count 0 2006.176.08:27:28.88#ibcon#about to read 3, iclass 15, count 0 2006.176.08:27:28.91#ibcon#read 3, iclass 15, count 0 2006.176.08:27:28.91#ibcon#about to read 4, iclass 15, count 0 2006.176.08:27:28.91#ibcon#read 4, iclass 15, count 0 2006.176.08:27:28.91#ibcon#about to read 5, iclass 15, count 0 2006.176.08:27:28.91#ibcon#read 5, iclass 15, count 0 2006.176.08:27:28.91#ibcon#about to read 6, iclass 15, count 0 2006.176.08:27:28.91#ibcon#read 6, iclass 15, count 0 2006.176.08:27:28.91#ibcon#end of sib2, iclass 15, count 0 2006.176.08:27:28.91#ibcon#*after write, iclass 15, count 0 2006.176.08:27:28.91#ibcon#*before return 0, iclass 15, count 0 2006.176.08:27:28.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:28.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:28.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:27:28.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:27:28.91$vc4f8/valo=4,832.99 2006.176.08:27:28.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.08:27:28.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.08:27:28.91#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:28.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:28.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:28.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:28.91#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:27:28.91#ibcon#first serial, iclass 17, count 0 2006.176.08:27:28.91#ibcon#enter sib2, iclass 17, count 0 2006.176.08:27:28.91#ibcon#flushed, iclass 17, count 0 2006.176.08:27:28.91#ibcon#about to write, iclass 17, count 0 2006.176.08:27:28.91#ibcon#wrote, iclass 17, count 0 2006.176.08:27:28.91#ibcon#about to read 3, iclass 17, count 0 2006.176.08:27:28.93#ibcon#read 3, iclass 17, count 0 2006.176.08:27:28.93#ibcon#about to read 4, iclass 17, count 0 2006.176.08:27:28.93#ibcon#read 4, iclass 17, count 0 2006.176.08:27:28.93#ibcon#about to read 5, iclass 17, count 0 2006.176.08:27:28.93#ibcon#read 5, iclass 17, count 0 2006.176.08:27:28.93#ibcon#about to read 6, iclass 17, count 0 2006.176.08:27:28.93#ibcon#read 6, iclass 17, count 0 2006.176.08:27:28.93#ibcon#end of sib2, iclass 17, count 0 2006.176.08:27:28.93#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:27:28.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:27:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.176.08:27:28.93#ibcon#*before write, iclass 17, count 0 2006.176.08:27:28.93#ibcon#enter sib2, iclass 17, count 0 2006.176.08:27:28.93#ibcon#flushed, iclass 17, count 0 2006.176.08:27:28.93#ibcon#about to write, iclass 17, count 0 2006.176.08:27:28.93#ibcon#wrote, iclass 17, count 0 2006.176.08:27:28.93#ibcon#about to read 3, iclass 17, count 0 2006.176.08:27:28.97#ibcon#read 3, iclass 17, count 0 2006.176.08:27:28.97#ibcon#about to read 4, iclass 17, count 0 2006.176.08:27:28.97#ibcon#read 4, iclass 17, count 0 2006.176.08:27:28.97#ibcon#about to read 5, iclass 17, count 0 2006.176.08:27:28.97#ibcon#read 5, iclass 17, count 0 2006.176.08:27:28.97#ibcon#about to read 6, iclass 17, count 0 2006.176.08:27:28.97#ibcon#read 6, iclass 17, count 0 2006.176.08:27:28.97#ibcon#end of sib2, iclass 17, count 0 2006.176.08:27:28.97#ibcon#*after write, iclass 17, count 0 2006.176.08:27:28.97#ibcon#*before return 0, iclass 17, count 0 2006.176.08:27:28.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:28.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:28.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:27:28.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:27:28.97$vc4f8/va=4,7 2006.176.08:27:28.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.176.08:27:28.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.176.08:27:28.97#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:28.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:29.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:29.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:29.03#ibcon#enter wrdev, iclass 19, count 2 2006.176.08:27:29.03#ibcon#first serial, iclass 19, count 2 2006.176.08:27:29.03#ibcon#enter sib2, iclass 19, count 2 2006.176.08:27:29.03#ibcon#flushed, iclass 19, count 2 2006.176.08:27:29.03#ibcon#about to write, iclass 19, count 2 2006.176.08:27:29.03#ibcon#wrote, iclass 19, count 2 2006.176.08:27:29.03#ibcon#about to read 3, iclass 19, count 2 2006.176.08:27:29.05#ibcon#read 3, iclass 19, count 2 2006.176.08:27:29.05#ibcon#about to read 4, iclass 19, count 2 2006.176.08:27:29.05#ibcon#read 4, iclass 19, count 2 2006.176.08:27:29.05#ibcon#about to read 5, iclass 19, count 2 2006.176.08:27:29.05#ibcon#read 5, iclass 19, count 2 2006.176.08:27:29.05#ibcon#about to read 6, iclass 19, count 2 2006.176.08:27:29.05#ibcon#read 6, iclass 19, count 2 2006.176.08:27:29.05#ibcon#end of sib2, iclass 19, count 2 2006.176.08:27:29.05#ibcon#*mode == 0, iclass 19, count 2 2006.176.08:27:29.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.176.08:27:29.05#ibcon#[25=AT04-07\r\n] 2006.176.08:27:29.05#ibcon#*before write, iclass 19, count 2 2006.176.08:27:29.05#ibcon#enter sib2, iclass 19, count 2 2006.176.08:27:29.05#ibcon#flushed, iclass 19, count 2 2006.176.08:27:29.05#ibcon#about to write, iclass 19, count 2 2006.176.08:27:29.05#ibcon#wrote, iclass 19, count 2 2006.176.08:27:29.05#ibcon#about to read 3, iclass 19, count 2 2006.176.08:27:29.08#ibcon#read 3, iclass 19, count 2 2006.176.08:27:29.08#ibcon#about to read 4, iclass 19, count 2 2006.176.08:27:29.08#ibcon#read 4, iclass 19, count 2 2006.176.08:27:29.08#ibcon#about to read 5, iclass 19, count 2 2006.176.08:27:29.08#ibcon#read 5, iclass 19, count 2 2006.176.08:27:29.08#ibcon#about to read 6, iclass 19, count 2 2006.176.08:27:29.08#ibcon#read 6, iclass 19, count 2 2006.176.08:27:29.08#ibcon#end of sib2, iclass 19, count 2 2006.176.08:27:29.08#ibcon#*after write, iclass 19, count 2 2006.176.08:27:29.08#ibcon#*before return 0, iclass 19, count 2 2006.176.08:27:29.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:29.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:29.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.176.08:27:29.08#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:29.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:29.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:29.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:29.20#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:27:29.20#ibcon#first serial, iclass 19, count 0 2006.176.08:27:29.20#ibcon#enter sib2, iclass 19, count 0 2006.176.08:27:29.20#ibcon#flushed, iclass 19, count 0 2006.176.08:27:29.20#ibcon#about to write, iclass 19, count 0 2006.176.08:27:29.20#ibcon#wrote, iclass 19, count 0 2006.176.08:27:29.20#ibcon#about to read 3, iclass 19, count 0 2006.176.08:27:29.22#ibcon#read 3, iclass 19, count 0 2006.176.08:27:29.22#ibcon#about to read 4, iclass 19, count 0 2006.176.08:27:29.22#ibcon#read 4, iclass 19, count 0 2006.176.08:27:29.22#ibcon#about to read 5, iclass 19, count 0 2006.176.08:27:29.22#ibcon#read 5, iclass 19, count 0 2006.176.08:27:29.22#ibcon#about to read 6, iclass 19, count 0 2006.176.08:27:29.22#ibcon#read 6, iclass 19, count 0 2006.176.08:27:29.22#ibcon#end of sib2, iclass 19, count 0 2006.176.08:27:29.22#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:27:29.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:27:29.22#ibcon#[25=USB\r\n] 2006.176.08:27:29.22#ibcon#*before write, iclass 19, count 0 2006.176.08:27:29.22#ibcon#enter sib2, iclass 19, count 0 2006.176.08:27:29.22#ibcon#flushed, iclass 19, count 0 2006.176.08:27:29.22#ibcon#about to write, iclass 19, count 0 2006.176.08:27:29.22#ibcon#wrote, iclass 19, count 0 2006.176.08:27:29.22#ibcon#about to read 3, iclass 19, count 0 2006.176.08:27:29.25#ibcon#read 3, iclass 19, count 0 2006.176.08:27:29.25#ibcon#about to read 4, iclass 19, count 0 2006.176.08:27:29.25#ibcon#read 4, iclass 19, count 0 2006.176.08:27:29.25#ibcon#about to read 5, iclass 19, count 0 2006.176.08:27:29.25#ibcon#read 5, iclass 19, count 0 2006.176.08:27:29.25#ibcon#about to read 6, iclass 19, count 0 2006.176.08:27:29.25#ibcon#read 6, iclass 19, count 0 2006.176.08:27:29.25#ibcon#end of sib2, iclass 19, count 0 2006.176.08:27:29.25#ibcon#*after write, iclass 19, count 0 2006.176.08:27:29.25#ibcon#*before return 0, iclass 19, count 0 2006.176.08:27:29.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:29.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:29.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:27:29.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:27:29.25$vc4f8/valo=5,652.99 2006.176.08:27:29.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.08:27:29.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.08:27:29.25#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:29.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:29.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:29.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:29.25#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:27:29.25#ibcon#first serial, iclass 21, count 0 2006.176.08:27:29.25#ibcon#enter sib2, iclass 21, count 0 2006.176.08:27:29.25#ibcon#flushed, iclass 21, count 0 2006.176.08:27:29.25#ibcon#about to write, iclass 21, count 0 2006.176.08:27:29.25#ibcon#wrote, iclass 21, count 0 2006.176.08:27:29.25#ibcon#about to read 3, iclass 21, count 0 2006.176.08:27:29.27#ibcon#read 3, iclass 21, count 0 2006.176.08:27:29.27#ibcon#about to read 4, iclass 21, count 0 2006.176.08:27:29.27#ibcon#read 4, iclass 21, count 0 2006.176.08:27:29.27#ibcon#about to read 5, iclass 21, count 0 2006.176.08:27:29.27#ibcon#read 5, iclass 21, count 0 2006.176.08:27:29.27#ibcon#about to read 6, iclass 21, count 0 2006.176.08:27:29.27#ibcon#read 6, iclass 21, count 0 2006.176.08:27:29.27#ibcon#end of sib2, iclass 21, count 0 2006.176.08:27:29.27#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:27:29.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:27:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.176.08:27:29.27#ibcon#*before write, iclass 21, count 0 2006.176.08:27:29.27#ibcon#enter sib2, iclass 21, count 0 2006.176.08:27:29.27#ibcon#flushed, iclass 21, count 0 2006.176.08:27:29.27#ibcon#about to write, iclass 21, count 0 2006.176.08:27:29.27#ibcon#wrote, iclass 21, count 0 2006.176.08:27:29.27#ibcon#about to read 3, iclass 21, count 0 2006.176.08:27:29.31#ibcon#read 3, iclass 21, count 0 2006.176.08:27:29.31#ibcon#about to read 4, iclass 21, count 0 2006.176.08:27:29.31#ibcon#read 4, iclass 21, count 0 2006.176.08:27:29.31#ibcon#about to read 5, iclass 21, count 0 2006.176.08:27:29.31#ibcon#read 5, iclass 21, count 0 2006.176.08:27:29.31#ibcon#about to read 6, iclass 21, count 0 2006.176.08:27:29.31#ibcon#read 6, iclass 21, count 0 2006.176.08:27:29.31#ibcon#end of sib2, iclass 21, count 0 2006.176.08:27:29.31#ibcon#*after write, iclass 21, count 0 2006.176.08:27:29.31#ibcon#*before return 0, iclass 21, count 0 2006.176.08:27:29.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:29.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:29.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:27:29.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:27:29.31$vc4f8/va=5,7 2006.176.08:27:29.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.08:27:29.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.08:27:29.31#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:29.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:29.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:29.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:29.37#ibcon#enter wrdev, iclass 23, count 2 2006.176.08:27:29.37#ibcon#first serial, iclass 23, count 2 2006.176.08:27:29.37#ibcon#enter sib2, iclass 23, count 2 2006.176.08:27:29.37#ibcon#flushed, iclass 23, count 2 2006.176.08:27:29.37#ibcon#about to write, iclass 23, count 2 2006.176.08:27:29.37#ibcon#wrote, iclass 23, count 2 2006.176.08:27:29.37#ibcon#about to read 3, iclass 23, count 2 2006.176.08:27:29.39#ibcon#read 3, iclass 23, count 2 2006.176.08:27:29.39#ibcon#about to read 4, iclass 23, count 2 2006.176.08:27:29.39#ibcon#read 4, iclass 23, count 2 2006.176.08:27:29.39#ibcon#about to read 5, iclass 23, count 2 2006.176.08:27:29.39#ibcon#read 5, iclass 23, count 2 2006.176.08:27:29.39#ibcon#about to read 6, iclass 23, count 2 2006.176.08:27:29.39#ibcon#read 6, iclass 23, count 2 2006.176.08:27:29.39#ibcon#end of sib2, iclass 23, count 2 2006.176.08:27:29.39#ibcon#*mode == 0, iclass 23, count 2 2006.176.08:27:29.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.08:27:29.39#ibcon#[25=AT05-07\r\n] 2006.176.08:27:29.39#ibcon#*before write, iclass 23, count 2 2006.176.08:27:29.39#ibcon#enter sib2, iclass 23, count 2 2006.176.08:27:29.39#ibcon#flushed, iclass 23, count 2 2006.176.08:27:29.39#ibcon#about to write, iclass 23, count 2 2006.176.08:27:29.39#ibcon#wrote, iclass 23, count 2 2006.176.08:27:29.39#ibcon#about to read 3, iclass 23, count 2 2006.176.08:27:29.42#ibcon#read 3, iclass 23, count 2 2006.176.08:27:29.42#ibcon#about to read 4, iclass 23, count 2 2006.176.08:27:29.42#ibcon#read 4, iclass 23, count 2 2006.176.08:27:29.42#ibcon#about to read 5, iclass 23, count 2 2006.176.08:27:29.42#ibcon#read 5, iclass 23, count 2 2006.176.08:27:29.42#ibcon#about to read 6, iclass 23, count 2 2006.176.08:27:29.42#ibcon#read 6, iclass 23, count 2 2006.176.08:27:29.42#ibcon#end of sib2, iclass 23, count 2 2006.176.08:27:29.42#ibcon#*after write, iclass 23, count 2 2006.176.08:27:29.42#ibcon#*before return 0, iclass 23, count 2 2006.176.08:27:29.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:29.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:29.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.08:27:29.42#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:29.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:29.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:29.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:29.54#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:27:29.54#ibcon#first serial, iclass 23, count 0 2006.176.08:27:29.54#ibcon#enter sib2, iclass 23, count 0 2006.176.08:27:29.54#ibcon#flushed, iclass 23, count 0 2006.176.08:27:29.54#ibcon#about to write, iclass 23, count 0 2006.176.08:27:29.54#ibcon#wrote, iclass 23, count 0 2006.176.08:27:29.54#ibcon#about to read 3, iclass 23, count 0 2006.176.08:27:29.56#ibcon#read 3, iclass 23, count 0 2006.176.08:27:29.56#ibcon#about to read 4, iclass 23, count 0 2006.176.08:27:29.56#ibcon#read 4, iclass 23, count 0 2006.176.08:27:29.56#ibcon#about to read 5, iclass 23, count 0 2006.176.08:27:29.56#ibcon#read 5, iclass 23, count 0 2006.176.08:27:29.56#ibcon#about to read 6, iclass 23, count 0 2006.176.08:27:29.56#ibcon#read 6, iclass 23, count 0 2006.176.08:27:29.56#ibcon#end of sib2, iclass 23, count 0 2006.176.08:27:29.56#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:27:29.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:27:29.56#ibcon#[25=USB\r\n] 2006.176.08:27:29.56#ibcon#*before write, iclass 23, count 0 2006.176.08:27:29.56#ibcon#enter sib2, iclass 23, count 0 2006.176.08:27:29.56#ibcon#flushed, iclass 23, count 0 2006.176.08:27:29.56#ibcon#about to write, iclass 23, count 0 2006.176.08:27:29.56#ibcon#wrote, iclass 23, count 0 2006.176.08:27:29.56#ibcon#about to read 3, iclass 23, count 0 2006.176.08:27:29.59#ibcon#read 3, iclass 23, count 0 2006.176.08:27:29.59#ibcon#about to read 4, iclass 23, count 0 2006.176.08:27:29.59#ibcon#read 4, iclass 23, count 0 2006.176.08:27:29.59#ibcon#about to read 5, iclass 23, count 0 2006.176.08:27:29.59#ibcon#read 5, iclass 23, count 0 2006.176.08:27:29.59#ibcon#about to read 6, iclass 23, count 0 2006.176.08:27:29.59#ibcon#read 6, iclass 23, count 0 2006.176.08:27:29.59#ibcon#end of sib2, iclass 23, count 0 2006.176.08:27:29.59#ibcon#*after write, iclass 23, count 0 2006.176.08:27:29.59#ibcon#*before return 0, iclass 23, count 0 2006.176.08:27:29.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:29.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:29.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:27:29.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:27:29.59$vc4f8/valo=6,772.99 2006.176.08:27:29.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.08:27:29.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.08:27:29.59#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:29.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:29.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:29.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:29.59#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:27:29.59#ibcon#first serial, iclass 25, count 0 2006.176.08:27:29.59#ibcon#enter sib2, iclass 25, count 0 2006.176.08:27:29.59#ibcon#flushed, iclass 25, count 0 2006.176.08:27:29.59#ibcon#about to write, iclass 25, count 0 2006.176.08:27:29.59#ibcon#wrote, iclass 25, count 0 2006.176.08:27:29.59#ibcon#about to read 3, iclass 25, count 0 2006.176.08:27:29.61#ibcon#read 3, iclass 25, count 0 2006.176.08:27:29.61#ibcon#about to read 4, iclass 25, count 0 2006.176.08:27:29.61#ibcon#read 4, iclass 25, count 0 2006.176.08:27:29.61#ibcon#about to read 5, iclass 25, count 0 2006.176.08:27:29.61#ibcon#read 5, iclass 25, count 0 2006.176.08:27:29.61#ibcon#about to read 6, iclass 25, count 0 2006.176.08:27:29.61#ibcon#read 6, iclass 25, count 0 2006.176.08:27:29.61#ibcon#end of sib2, iclass 25, count 0 2006.176.08:27:29.61#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:27:29.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:27:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.176.08:27:29.61#ibcon#*before write, iclass 25, count 0 2006.176.08:27:29.61#ibcon#enter sib2, iclass 25, count 0 2006.176.08:27:29.61#ibcon#flushed, iclass 25, count 0 2006.176.08:27:29.61#ibcon#about to write, iclass 25, count 0 2006.176.08:27:29.61#ibcon#wrote, iclass 25, count 0 2006.176.08:27:29.61#ibcon#about to read 3, iclass 25, count 0 2006.176.08:27:29.65#ibcon#read 3, iclass 25, count 0 2006.176.08:27:29.65#ibcon#about to read 4, iclass 25, count 0 2006.176.08:27:29.65#ibcon#read 4, iclass 25, count 0 2006.176.08:27:29.65#ibcon#about to read 5, iclass 25, count 0 2006.176.08:27:29.65#ibcon#read 5, iclass 25, count 0 2006.176.08:27:29.65#ibcon#about to read 6, iclass 25, count 0 2006.176.08:27:29.65#ibcon#read 6, iclass 25, count 0 2006.176.08:27:29.65#ibcon#end of sib2, iclass 25, count 0 2006.176.08:27:29.65#ibcon#*after write, iclass 25, count 0 2006.176.08:27:29.65#ibcon#*before return 0, iclass 25, count 0 2006.176.08:27:29.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:29.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:29.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:27:29.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:27:29.65$vc4f8/va=6,6 2006.176.08:27:29.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.08:27:29.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.08:27:29.65#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:29.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:29.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:29.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:29.71#ibcon#enter wrdev, iclass 27, count 2 2006.176.08:27:29.71#ibcon#first serial, iclass 27, count 2 2006.176.08:27:29.71#ibcon#enter sib2, iclass 27, count 2 2006.176.08:27:29.71#ibcon#flushed, iclass 27, count 2 2006.176.08:27:29.71#ibcon#about to write, iclass 27, count 2 2006.176.08:27:29.71#ibcon#wrote, iclass 27, count 2 2006.176.08:27:29.71#ibcon#about to read 3, iclass 27, count 2 2006.176.08:27:29.73#ibcon#read 3, iclass 27, count 2 2006.176.08:27:29.73#ibcon#about to read 4, iclass 27, count 2 2006.176.08:27:29.73#ibcon#read 4, iclass 27, count 2 2006.176.08:27:29.73#ibcon#about to read 5, iclass 27, count 2 2006.176.08:27:29.73#ibcon#read 5, iclass 27, count 2 2006.176.08:27:29.73#ibcon#about to read 6, iclass 27, count 2 2006.176.08:27:29.73#ibcon#read 6, iclass 27, count 2 2006.176.08:27:29.73#ibcon#end of sib2, iclass 27, count 2 2006.176.08:27:29.73#ibcon#*mode == 0, iclass 27, count 2 2006.176.08:27:29.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.08:27:29.73#ibcon#[25=AT06-06\r\n] 2006.176.08:27:29.73#ibcon#*before write, iclass 27, count 2 2006.176.08:27:29.73#ibcon#enter sib2, iclass 27, count 2 2006.176.08:27:29.73#ibcon#flushed, iclass 27, count 2 2006.176.08:27:29.73#ibcon#about to write, iclass 27, count 2 2006.176.08:27:29.73#ibcon#wrote, iclass 27, count 2 2006.176.08:27:29.73#ibcon#about to read 3, iclass 27, count 2 2006.176.08:27:29.76#ibcon#read 3, iclass 27, count 2 2006.176.08:27:29.76#ibcon#about to read 4, iclass 27, count 2 2006.176.08:27:29.76#ibcon#read 4, iclass 27, count 2 2006.176.08:27:29.76#ibcon#about to read 5, iclass 27, count 2 2006.176.08:27:29.76#ibcon#read 5, iclass 27, count 2 2006.176.08:27:29.76#ibcon#about to read 6, iclass 27, count 2 2006.176.08:27:29.76#ibcon#read 6, iclass 27, count 2 2006.176.08:27:29.76#ibcon#end of sib2, iclass 27, count 2 2006.176.08:27:29.76#ibcon#*after write, iclass 27, count 2 2006.176.08:27:29.76#ibcon#*before return 0, iclass 27, count 2 2006.176.08:27:29.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:29.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:29.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.08:27:29.76#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:29.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:29.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:29.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:29.88#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:27:29.88#ibcon#first serial, iclass 27, count 0 2006.176.08:27:29.88#ibcon#enter sib2, iclass 27, count 0 2006.176.08:27:29.88#ibcon#flushed, iclass 27, count 0 2006.176.08:27:29.88#ibcon#about to write, iclass 27, count 0 2006.176.08:27:29.88#ibcon#wrote, iclass 27, count 0 2006.176.08:27:29.88#ibcon#about to read 3, iclass 27, count 0 2006.176.08:27:29.90#ibcon#read 3, iclass 27, count 0 2006.176.08:27:29.90#ibcon#about to read 4, iclass 27, count 0 2006.176.08:27:29.90#ibcon#read 4, iclass 27, count 0 2006.176.08:27:29.90#ibcon#about to read 5, iclass 27, count 0 2006.176.08:27:29.90#ibcon#read 5, iclass 27, count 0 2006.176.08:27:29.90#ibcon#about to read 6, iclass 27, count 0 2006.176.08:27:29.90#ibcon#read 6, iclass 27, count 0 2006.176.08:27:29.90#ibcon#end of sib2, iclass 27, count 0 2006.176.08:27:29.90#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:27:29.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:27:29.90#ibcon#[25=USB\r\n] 2006.176.08:27:29.90#ibcon#*before write, iclass 27, count 0 2006.176.08:27:29.90#ibcon#enter sib2, iclass 27, count 0 2006.176.08:27:29.90#ibcon#flushed, iclass 27, count 0 2006.176.08:27:29.90#ibcon#about to write, iclass 27, count 0 2006.176.08:27:29.90#ibcon#wrote, iclass 27, count 0 2006.176.08:27:29.90#ibcon#about to read 3, iclass 27, count 0 2006.176.08:27:29.93#ibcon#read 3, iclass 27, count 0 2006.176.08:27:29.93#ibcon#about to read 4, iclass 27, count 0 2006.176.08:27:29.93#ibcon#read 4, iclass 27, count 0 2006.176.08:27:29.93#ibcon#about to read 5, iclass 27, count 0 2006.176.08:27:29.93#ibcon#read 5, iclass 27, count 0 2006.176.08:27:29.93#ibcon#about to read 6, iclass 27, count 0 2006.176.08:27:29.93#ibcon#read 6, iclass 27, count 0 2006.176.08:27:29.93#ibcon#end of sib2, iclass 27, count 0 2006.176.08:27:29.93#ibcon#*after write, iclass 27, count 0 2006.176.08:27:29.93#ibcon#*before return 0, iclass 27, count 0 2006.176.08:27:29.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:29.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:29.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:27:29.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:27:29.93$vc4f8/valo=7,832.99 2006.176.08:27:29.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.08:27:29.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.08:27:29.93#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:29.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:29.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:29.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:29.93#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:27:29.93#ibcon#first serial, iclass 29, count 0 2006.176.08:27:29.93#ibcon#enter sib2, iclass 29, count 0 2006.176.08:27:29.93#ibcon#flushed, iclass 29, count 0 2006.176.08:27:29.93#ibcon#about to write, iclass 29, count 0 2006.176.08:27:29.93#ibcon#wrote, iclass 29, count 0 2006.176.08:27:29.93#ibcon#about to read 3, iclass 29, count 0 2006.176.08:27:29.95#ibcon#read 3, iclass 29, count 0 2006.176.08:27:29.95#ibcon#about to read 4, iclass 29, count 0 2006.176.08:27:29.95#ibcon#read 4, iclass 29, count 0 2006.176.08:27:29.95#ibcon#about to read 5, iclass 29, count 0 2006.176.08:27:29.95#ibcon#read 5, iclass 29, count 0 2006.176.08:27:29.95#ibcon#about to read 6, iclass 29, count 0 2006.176.08:27:29.95#ibcon#read 6, iclass 29, count 0 2006.176.08:27:29.95#ibcon#end of sib2, iclass 29, count 0 2006.176.08:27:29.95#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:27:29.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:27:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.176.08:27:29.95#ibcon#*before write, iclass 29, count 0 2006.176.08:27:29.95#ibcon#enter sib2, iclass 29, count 0 2006.176.08:27:29.95#ibcon#flushed, iclass 29, count 0 2006.176.08:27:29.95#ibcon#about to write, iclass 29, count 0 2006.176.08:27:29.95#ibcon#wrote, iclass 29, count 0 2006.176.08:27:29.95#ibcon#about to read 3, iclass 29, count 0 2006.176.08:27:29.99#ibcon#read 3, iclass 29, count 0 2006.176.08:27:29.99#ibcon#about to read 4, iclass 29, count 0 2006.176.08:27:29.99#ibcon#read 4, iclass 29, count 0 2006.176.08:27:29.99#ibcon#about to read 5, iclass 29, count 0 2006.176.08:27:29.99#ibcon#read 5, iclass 29, count 0 2006.176.08:27:29.99#ibcon#about to read 6, iclass 29, count 0 2006.176.08:27:29.99#ibcon#read 6, iclass 29, count 0 2006.176.08:27:29.99#ibcon#end of sib2, iclass 29, count 0 2006.176.08:27:29.99#ibcon#*after write, iclass 29, count 0 2006.176.08:27:29.99#ibcon#*before return 0, iclass 29, count 0 2006.176.08:27:29.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:29.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:29.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:27:29.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:27:29.99$vc4f8/va=7,6 2006.176.08:27:29.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.176.08:27:29.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.176.08:27:29.99#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:29.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:27:30.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:27:30.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:27:30.05#ibcon#enter wrdev, iclass 31, count 2 2006.176.08:27:30.05#ibcon#first serial, iclass 31, count 2 2006.176.08:27:30.05#ibcon#enter sib2, iclass 31, count 2 2006.176.08:27:30.05#ibcon#flushed, iclass 31, count 2 2006.176.08:27:30.05#ibcon#about to write, iclass 31, count 2 2006.176.08:27:30.05#ibcon#wrote, iclass 31, count 2 2006.176.08:27:30.05#ibcon#about to read 3, iclass 31, count 2 2006.176.08:27:30.07#ibcon#read 3, iclass 31, count 2 2006.176.08:27:30.07#ibcon#about to read 4, iclass 31, count 2 2006.176.08:27:30.07#ibcon#read 4, iclass 31, count 2 2006.176.08:27:30.07#ibcon#about to read 5, iclass 31, count 2 2006.176.08:27:30.07#ibcon#read 5, iclass 31, count 2 2006.176.08:27:30.07#ibcon#about to read 6, iclass 31, count 2 2006.176.08:27:30.07#ibcon#read 6, iclass 31, count 2 2006.176.08:27:30.07#ibcon#end of sib2, iclass 31, count 2 2006.176.08:27:30.07#ibcon#*mode == 0, iclass 31, count 2 2006.176.08:27:30.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.176.08:27:30.07#ibcon#[25=AT07-06\r\n] 2006.176.08:27:30.07#ibcon#*before write, iclass 31, count 2 2006.176.08:27:30.07#ibcon#enter sib2, iclass 31, count 2 2006.176.08:27:30.07#ibcon#flushed, iclass 31, count 2 2006.176.08:27:30.07#ibcon#about to write, iclass 31, count 2 2006.176.08:27:30.07#ibcon#wrote, iclass 31, count 2 2006.176.08:27:30.07#ibcon#about to read 3, iclass 31, count 2 2006.176.08:27:30.10#ibcon#read 3, iclass 31, count 2 2006.176.08:27:30.10#ibcon#about to read 4, iclass 31, count 2 2006.176.08:27:30.10#ibcon#read 4, iclass 31, count 2 2006.176.08:27:30.10#ibcon#about to read 5, iclass 31, count 2 2006.176.08:27:30.10#ibcon#read 5, iclass 31, count 2 2006.176.08:27:30.10#ibcon#about to read 6, iclass 31, count 2 2006.176.08:27:30.10#ibcon#read 6, iclass 31, count 2 2006.176.08:27:30.10#ibcon#end of sib2, iclass 31, count 2 2006.176.08:27:30.10#ibcon#*after write, iclass 31, count 2 2006.176.08:27:30.10#ibcon#*before return 0, iclass 31, count 2 2006.176.08:27:30.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:27:30.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.176.08:27:30.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.176.08:27:30.10#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:30.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:27:30.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:27:30.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:27:30.22#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:27:30.22#ibcon#first serial, iclass 31, count 0 2006.176.08:27:30.22#ibcon#enter sib2, iclass 31, count 0 2006.176.08:27:30.22#ibcon#flushed, iclass 31, count 0 2006.176.08:27:30.22#ibcon#about to write, iclass 31, count 0 2006.176.08:27:30.22#ibcon#wrote, iclass 31, count 0 2006.176.08:27:30.22#ibcon#about to read 3, iclass 31, count 0 2006.176.08:27:30.24#ibcon#read 3, iclass 31, count 0 2006.176.08:27:30.24#ibcon#about to read 4, iclass 31, count 0 2006.176.08:27:30.24#ibcon#read 4, iclass 31, count 0 2006.176.08:27:30.24#ibcon#about to read 5, iclass 31, count 0 2006.176.08:27:30.24#ibcon#read 5, iclass 31, count 0 2006.176.08:27:30.24#ibcon#about to read 6, iclass 31, count 0 2006.176.08:27:30.24#ibcon#read 6, iclass 31, count 0 2006.176.08:27:30.24#ibcon#end of sib2, iclass 31, count 0 2006.176.08:27:30.24#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:27:30.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:27:30.24#ibcon#[25=USB\r\n] 2006.176.08:27:30.24#ibcon#*before write, iclass 31, count 0 2006.176.08:27:30.24#ibcon#enter sib2, iclass 31, count 0 2006.176.08:27:30.24#ibcon#flushed, iclass 31, count 0 2006.176.08:27:30.24#ibcon#about to write, iclass 31, count 0 2006.176.08:27:30.24#ibcon#wrote, iclass 31, count 0 2006.176.08:27:30.24#ibcon#about to read 3, iclass 31, count 0 2006.176.08:27:30.27#ibcon#read 3, iclass 31, count 0 2006.176.08:27:30.27#ibcon#about to read 4, iclass 31, count 0 2006.176.08:27:30.27#ibcon#read 4, iclass 31, count 0 2006.176.08:27:30.27#ibcon#about to read 5, iclass 31, count 0 2006.176.08:27:30.27#ibcon#read 5, iclass 31, count 0 2006.176.08:27:30.27#ibcon#about to read 6, iclass 31, count 0 2006.176.08:27:30.27#ibcon#read 6, iclass 31, count 0 2006.176.08:27:30.27#ibcon#end of sib2, iclass 31, count 0 2006.176.08:27:30.27#ibcon#*after write, iclass 31, count 0 2006.176.08:27:30.27#ibcon#*before return 0, iclass 31, count 0 2006.176.08:27:30.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:27:30.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.176.08:27:30.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:27:30.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:27:30.27$vc4f8/valo=8,852.99 2006.176.08:27:30.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.176.08:27:30.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.176.08:27:30.27#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:30.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:27:30.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:27:30.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:27:30.27#ibcon#enter wrdev, iclass 33, count 0 2006.176.08:27:30.27#ibcon#first serial, iclass 33, count 0 2006.176.08:27:30.27#ibcon#enter sib2, iclass 33, count 0 2006.176.08:27:30.27#ibcon#flushed, iclass 33, count 0 2006.176.08:27:30.27#ibcon#about to write, iclass 33, count 0 2006.176.08:27:30.27#ibcon#wrote, iclass 33, count 0 2006.176.08:27:30.27#ibcon#about to read 3, iclass 33, count 0 2006.176.08:27:30.29#ibcon#read 3, iclass 33, count 0 2006.176.08:27:30.29#ibcon#about to read 4, iclass 33, count 0 2006.176.08:27:30.29#ibcon#read 4, iclass 33, count 0 2006.176.08:27:30.29#ibcon#about to read 5, iclass 33, count 0 2006.176.08:27:30.29#ibcon#read 5, iclass 33, count 0 2006.176.08:27:30.29#ibcon#about to read 6, iclass 33, count 0 2006.176.08:27:30.29#ibcon#read 6, iclass 33, count 0 2006.176.08:27:30.29#ibcon#end of sib2, iclass 33, count 0 2006.176.08:27:30.29#ibcon#*mode == 0, iclass 33, count 0 2006.176.08:27:30.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.176.08:27:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.176.08:27:30.29#ibcon#*before write, iclass 33, count 0 2006.176.08:27:30.29#ibcon#enter sib2, iclass 33, count 0 2006.176.08:27:30.29#ibcon#flushed, iclass 33, count 0 2006.176.08:27:30.29#ibcon#about to write, iclass 33, count 0 2006.176.08:27:30.29#ibcon#wrote, iclass 33, count 0 2006.176.08:27:30.29#ibcon#about to read 3, iclass 33, count 0 2006.176.08:27:30.33#ibcon#read 3, iclass 33, count 0 2006.176.08:27:30.33#ibcon#about to read 4, iclass 33, count 0 2006.176.08:27:30.33#ibcon#read 4, iclass 33, count 0 2006.176.08:27:30.33#ibcon#about to read 5, iclass 33, count 0 2006.176.08:27:30.33#ibcon#read 5, iclass 33, count 0 2006.176.08:27:30.33#ibcon#about to read 6, iclass 33, count 0 2006.176.08:27:30.33#ibcon#read 6, iclass 33, count 0 2006.176.08:27:30.33#ibcon#end of sib2, iclass 33, count 0 2006.176.08:27:30.33#ibcon#*after write, iclass 33, count 0 2006.176.08:27:30.33#ibcon#*before return 0, iclass 33, count 0 2006.176.08:27:30.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:27:30.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.176.08:27:30.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.176.08:27:30.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.176.08:27:30.33$vc4f8/va=8,6 2006.176.08:27:30.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.176.08:27:30.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.176.08:27:30.33#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:30.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:27:30.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:27:30.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:27:30.39#ibcon#enter wrdev, iclass 35, count 2 2006.176.08:27:30.39#ibcon#first serial, iclass 35, count 2 2006.176.08:27:30.39#ibcon#enter sib2, iclass 35, count 2 2006.176.08:27:30.39#ibcon#flushed, iclass 35, count 2 2006.176.08:27:30.39#ibcon#about to write, iclass 35, count 2 2006.176.08:27:30.39#ibcon#wrote, iclass 35, count 2 2006.176.08:27:30.39#ibcon#about to read 3, iclass 35, count 2 2006.176.08:27:30.41#ibcon#read 3, iclass 35, count 2 2006.176.08:27:30.41#ibcon#about to read 4, iclass 35, count 2 2006.176.08:27:30.41#ibcon#read 4, iclass 35, count 2 2006.176.08:27:30.41#ibcon#about to read 5, iclass 35, count 2 2006.176.08:27:30.41#ibcon#read 5, iclass 35, count 2 2006.176.08:27:30.41#ibcon#about to read 6, iclass 35, count 2 2006.176.08:27:30.41#ibcon#read 6, iclass 35, count 2 2006.176.08:27:30.41#ibcon#end of sib2, iclass 35, count 2 2006.176.08:27:30.41#ibcon#*mode == 0, iclass 35, count 2 2006.176.08:27:30.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.176.08:27:30.41#ibcon#[25=AT08-06\r\n] 2006.176.08:27:30.41#ibcon#*before write, iclass 35, count 2 2006.176.08:27:30.41#ibcon#enter sib2, iclass 35, count 2 2006.176.08:27:30.41#ibcon#flushed, iclass 35, count 2 2006.176.08:27:30.41#ibcon#about to write, iclass 35, count 2 2006.176.08:27:30.41#ibcon#wrote, iclass 35, count 2 2006.176.08:27:30.41#ibcon#about to read 3, iclass 35, count 2 2006.176.08:27:30.44#ibcon#read 3, iclass 35, count 2 2006.176.08:27:30.44#ibcon#about to read 4, iclass 35, count 2 2006.176.08:27:30.44#ibcon#read 4, iclass 35, count 2 2006.176.08:27:30.44#ibcon#about to read 5, iclass 35, count 2 2006.176.08:27:30.44#ibcon#read 5, iclass 35, count 2 2006.176.08:27:30.44#ibcon#about to read 6, iclass 35, count 2 2006.176.08:27:30.44#ibcon#read 6, iclass 35, count 2 2006.176.08:27:30.44#ibcon#end of sib2, iclass 35, count 2 2006.176.08:27:30.44#ibcon#*after write, iclass 35, count 2 2006.176.08:27:30.44#ibcon#*before return 0, iclass 35, count 2 2006.176.08:27:30.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:27:30.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.176.08:27:30.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.176.08:27:30.44#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:30.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:27:30.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:27:30.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:27:30.56#ibcon#enter wrdev, iclass 35, count 0 2006.176.08:27:30.56#ibcon#first serial, iclass 35, count 0 2006.176.08:27:30.56#ibcon#enter sib2, iclass 35, count 0 2006.176.08:27:30.56#ibcon#flushed, iclass 35, count 0 2006.176.08:27:30.56#ibcon#about to write, iclass 35, count 0 2006.176.08:27:30.56#ibcon#wrote, iclass 35, count 0 2006.176.08:27:30.56#ibcon#about to read 3, iclass 35, count 0 2006.176.08:27:30.58#ibcon#read 3, iclass 35, count 0 2006.176.08:27:30.58#ibcon#about to read 4, iclass 35, count 0 2006.176.08:27:30.58#ibcon#read 4, iclass 35, count 0 2006.176.08:27:30.58#ibcon#about to read 5, iclass 35, count 0 2006.176.08:27:30.58#ibcon#read 5, iclass 35, count 0 2006.176.08:27:30.58#ibcon#about to read 6, iclass 35, count 0 2006.176.08:27:30.58#ibcon#read 6, iclass 35, count 0 2006.176.08:27:30.58#ibcon#end of sib2, iclass 35, count 0 2006.176.08:27:30.58#ibcon#*mode == 0, iclass 35, count 0 2006.176.08:27:30.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.176.08:27:30.58#ibcon#[25=USB\r\n] 2006.176.08:27:30.58#ibcon#*before write, iclass 35, count 0 2006.176.08:27:30.58#ibcon#enter sib2, iclass 35, count 0 2006.176.08:27:30.58#ibcon#flushed, iclass 35, count 0 2006.176.08:27:30.58#ibcon#about to write, iclass 35, count 0 2006.176.08:27:30.58#ibcon#wrote, iclass 35, count 0 2006.176.08:27:30.58#ibcon#about to read 3, iclass 35, count 0 2006.176.08:27:30.61#ibcon#read 3, iclass 35, count 0 2006.176.08:27:30.61#ibcon#about to read 4, iclass 35, count 0 2006.176.08:27:30.61#ibcon#read 4, iclass 35, count 0 2006.176.08:27:30.61#ibcon#about to read 5, iclass 35, count 0 2006.176.08:27:30.61#ibcon#read 5, iclass 35, count 0 2006.176.08:27:30.61#ibcon#about to read 6, iclass 35, count 0 2006.176.08:27:30.61#ibcon#read 6, iclass 35, count 0 2006.176.08:27:30.61#ibcon#end of sib2, iclass 35, count 0 2006.176.08:27:30.61#ibcon#*after write, iclass 35, count 0 2006.176.08:27:30.61#ibcon#*before return 0, iclass 35, count 0 2006.176.08:27:30.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:27:30.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.176.08:27:30.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.176.08:27:30.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.176.08:27:30.61$vc4f8/vblo=1,632.99 2006.176.08:27:30.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.176.08:27:30.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.176.08:27:30.61#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:30.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:27:30.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:27:30.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:27:30.61#ibcon#enter wrdev, iclass 37, count 0 2006.176.08:27:30.61#ibcon#first serial, iclass 37, count 0 2006.176.08:27:30.61#ibcon#enter sib2, iclass 37, count 0 2006.176.08:27:30.61#ibcon#flushed, iclass 37, count 0 2006.176.08:27:30.61#ibcon#about to write, iclass 37, count 0 2006.176.08:27:30.61#ibcon#wrote, iclass 37, count 0 2006.176.08:27:30.61#ibcon#about to read 3, iclass 37, count 0 2006.176.08:27:30.63#ibcon#read 3, iclass 37, count 0 2006.176.08:27:30.63#ibcon#about to read 4, iclass 37, count 0 2006.176.08:27:30.63#ibcon#read 4, iclass 37, count 0 2006.176.08:27:30.63#ibcon#about to read 5, iclass 37, count 0 2006.176.08:27:30.63#ibcon#read 5, iclass 37, count 0 2006.176.08:27:30.63#ibcon#about to read 6, iclass 37, count 0 2006.176.08:27:30.63#ibcon#read 6, iclass 37, count 0 2006.176.08:27:30.63#ibcon#end of sib2, iclass 37, count 0 2006.176.08:27:30.63#ibcon#*mode == 0, iclass 37, count 0 2006.176.08:27:30.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.176.08:27:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.176.08:27:30.63#ibcon#*before write, iclass 37, count 0 2006.176.08:27:30.63#ibcon#enter sib2, iclass 37, count 0 2006.176.08:27:30.63#ibcon#flushed, iclass 37, count 0 2006.176.08:27:30.63#ibcon#about to write, iclass 37, count 0 2006.176.08:27:30.63#ibcon#wrote, iclass 37, count 0 2006.176.08:27:30.63#ibcon#about to read 3, iclass 37, count 0 2006.176.08:27:30.67#ibcon#read 3, iclass 37, count 0 2006.176.08:27:30.67#ibcon#about to read 4, iclass 37, count 0 2006.176.08:27:30.67#ibcon#read 4, iclass 37, count 0 2006.176.08:27:30.67#ibcon#about to read 5, iclass 37, count 0 2006.176.08:27:30.67#ibcon#read 5, iclass 37, count 0 2006.176.08:27:30.67#ibcon#about to read 6, iclass 37, count 0 2006.176.08:27:30.67#ibcon#read 6, iclass 37, count 0 2006.176.08:27:30.67#ibcon#end of sib2, iclass 37, count 0 2006.176.08:27:30.67#ibcon#*after write, iclass 37, count 0 2006.176.08:27:30.67#ibcon#*before return 0, iclass 37, count 0 2006.176.08:27:30.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:27:30.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.176.08:27:30.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.176.08:27:30.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.176.08:27:30.67$vc4f8/vb=1,4 2006.176.08:27:30.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.176.08:27:30.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.176.08:27:30.67#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:30.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:27:30.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:27:30.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:27:30.67#ibcon#enter wrdev, iclass 39, count 2 2006.176.08:27:30.67#ibcon#first serial, iclass 39, count 2 2006.176.08:27:30.67#ibcon#enter sib2, iclass 39, count 2 2006.176.08:27:30.67#ibcon#flushed, iclass 39, count 2 2006.176.08:27:30.67#ibcon#about to write, iclass 39, count 2 2006.176.08:27:30.67#ibcon#wrote, iclass 39, count 2 2006.176.08:27:30.67#ibcon#about to read 3, iclass 39, count 2 2006.176.08:27:30.69#ibcon#read 3, iclass 39, count 2 2006.176.08:27:30.69#ibcon#about to read 4, iclass 39, count 2 2006.176.08:27:30.69#ibcon#read 4, iclass 39, count 2 2006.176.08:27:30.69#ibcon#about to read 5, iclass 39, count 2 2006.176.08:27:30.69#ibcon#read 5, iclass 39, count 2 2006.176.08:27:30.69#ibcon#about to read 6, iclass 39, count 2 2006.176.08:27:30.69#ibcon#read 6, iclass 39, count 2 2006.176.08:27:30.69#ibcon#end of sib2, iclass 39, count 2 2006.176.08:27:30.69#ibcon#*mode == 0, iclass 39, count 2 2006.176.08:27:30.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.176.08:27:30.69#ibcon#[27=AT01-04\r\n] 2006.176.08:27:30.69#ibcon#*before write, iclass 39, count 2 2006.176.08:27:30.69#ibcon#enter sib2, iclass 39, count 2 2006.176.08:27:30.69#ibcon#flushed, iclass 39, count 2 2006.176.08:27:30.69#ibcon#about to write, iclass 39, count 2 2006.176.08:27:30.69#ibcon#wrote, iclass 39, count 2 2006.176.08:27:30.69#ibcon#about to read 3, iclass 39, count 2 2006.176.08:27:30.72#ibcon#read 3, iclass 39, count 2 2006.176.08:27:30.72#ibcon#about to read 4, iclass 39, count 2 2006.176.08:27:30.72#ibcon#read 4, iclass 39, count 2 2006.176.08:27:30.72#ibcon#about to read 5, iclass 39, count 2 2006.176.08:27:30.72#ibcon#read 5, iclass 39, count 2 2006.176.08:27:30.72#ibcon#about to read 6, iclass 39, count 2 2006.176.08:27:30.72#ibcon#read 6, iclass 39, count 2 2006.176.08:27:30.72#ibcon#end of sib2, iclass 39, count 2 2006.176.08:27:30.72#ibcon#*after write, iclass 39, count 2 2006.176.08:27:30.72#ibcon#*before return 0, iclass 39, count 2 2006.176.08:27:30.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:27:30.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.176.08:27:30.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.176.08:27:30.72#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:30.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:27:30.83#abcon#<5=/05 3.1 5.2 23.71 931008.5\r\n> 2006.176.08:27:30.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:27:30.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:27:30.84#ibcon#enter wrdev, iclass 39, count 0 2006.176.08:27:30.84#ibcon#first serial, iclass 39, count 0 2006.176.08:27:30.84#ibcon#enter sib2, iclass 39, count 0 2006.176.08:27:30.84#ibcon#flushed, iclass 39, count 0 2006.176.08:27:30.84#ibcon#about to write, iclass 39, count 0 2006.176.08:27:30.84#ibcon#wrote, iclass 39, count 0 2006.176.08:27:30.84#ibcon#about to read 3, iclass 39, count 0 2006.176.08:27:30.85#abcon#{5=INTERFACE CLEAR} 2006.176.08:27:30.86#ibcon#read 3, iclass 39, count 0 2006.176.08:27:30.86#ibcon#about to read 4, iclass 39, count 0 2006.176.08:27:30.86#ibcon#read 4, iclass 39, count 0 2006.176.08:27:30.86#ibcon#about to read 5, iclass 39, count 0 2006.176.08:27:30.86#ibcon#read 5, iclass 39, count 0 2006.176.08:27:30.86#ibcon#about to read 6, iclass 39, count 0 2006.176.08:27:30.86#ibcon#read 6, iclass 39, count 0 2006.176.08:27:30.86#ibcon#end of sib2, iclass 39, count 0 2006.176.08:27:30.86#ibcon#*mode == 0, iclass 39, count 0 2006.176.08:27:30.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.176.08:27:30.86#ibcon#[27=USB\r\n] 2006.176.08:27:30.86#ibcon#*before write, iclass 39, count 0 2006.176.08:27:30.86#ibcon#enter sib2, iclass 39, count 0 2006.176.08:27:30.86#ibcon#flushed, iclass 39, count 0 2006.176.08:27:30.86#ibcon#about to write, iclass 39, count 0 2006.176.08:27:30.86#ibcon#wrote, iclass 39, count 0 2006.176.08:27:30.86#ibcon#about to read 3, iclass 39, count 0 2006.176.08:27:30.89#ibcon#read 3, iclass 39, count 0 2006.176.08:27:30.89#ibcon#about to read 4, iclass 39, count 0 2006.176.08:27:30.89#ibcon#read 4, iclass 39, count 0 2006.176.08:27:30.89#ibcon#about to read 5, iclass 39, count 0 2006.176.08:27:30.89#ibcon#read 5, iclass 39, count 0 2006.176.08:27:30.89#ibcon#about to read 6, iclass 39, count 0 2006.176.08:27:30.89#ibcon#read 6, iclass 39, count 0 2006.176.08:27:30.89#ibcon#end of sib2, iclass 39, count 0 2006.176.08:27:30.89#ibcon#*after write, iclass 39, count 0 2006.176.08:27:30.89#ibcon#*before return 0, iclass 39, count 0 2006.176.08:27:30.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:27:30.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.176.08:27:30.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.176.08:27:30.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.176.08:27:30.89$vc4f8/vblo=2,640.99 2006.176.08:27:30.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.176.08:27:30.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.176.08:27:30.89#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:30.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:27:30.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:27:30.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:27:30.89#ibcon#enter wrdev, iclass 6, count 0 2006.176.08:27:30.89#ibcon#first serial, iclass 6, count 0 2006.176.08:27:30.89#ibcon#enter sib2, iclass 6, count 0 2006.176.08:27:30.89#ibcon#flushed, iclass 6, count 0 2006.176.08:27:30.89#ibcon#about to write, iclass 6, count 0 2006.176.08:27:30.89#ibcon#wrote, iclass 6, count 0 2006.176.08:27:30.89#ibcon#about to read 3, iclass 6, count 0 2006.176.08:27:30.91#ibcon#read 3, iclass 6, count 0 2006.176.08:27:30.91#ibcon#about to read 4, iclass 6, count 0 2006.176.08:27:30.91#ibcon#read 4, iclass 6, count 0 2006.176.08:27:30.91#ibcon#about to read 5, iclass 6, count 0 2006.176.08:27:30.91#ibcon#read 5, iclass 6, count 0 2006.176.08:27:30.91#ibcon#about to read 6, iclass 6, count 0 2006.176.08:27:30.91#ibcon#read 6, iclass 6, count 0 2006.176.08:27:30.91#ibcon#end of sib2, iclass 6, count 0 2006.176.08:27:30.91#ibcon#*mode == 0, iclass 6, count 0 2006.176.08:27:30.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.176.08:27:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.176.08:27:30.91#ibcon#*before write, iclass 6, count 0 2006.176.08:27:30.91#ibcon#enter sib2, iclass 6, count 0 2006.176.08:27:30.91#ibcon#flushed, iclass 6, count 0 2006.176.08:27:30.91#ibcon#about to write, iclass 6, count 0 2006.176.08:27:30.91#ibcon#wrote, iclass 6, count 0 2006.176.08:27:30.91#ibcon#about to read 3, iclass 6, count 0 2006.176.08:27:30.91#abcon#[5=S1D000X0/0*\r\n] 2006.176.08:27:30.95#ibcon#read 3, iclass 6, count 0 2006.176.08:27:30.95#ibcon#about to read 4, iclass 6, count 0 2006.176.08:27:30.95#ibcon#read 4, iclass 6, count 0 2006.176.08:27:30.95#ibcon#about to read 5, iclass 6, count 0 2006.176.08:27:30.95#ibcon#read 5, iclass 6, count 0 2006.176.08:27:30.95#ibcon#about to read 6, iclass 6, count 0 2006.176.08:27:30.95#ibcon#read 6, iclass 6, count 0 2006.176.08:27:30.95#ibcon#end of sib2, iclass 6, count 0 2006.176.08:27:30.95#ibcon#*after write, iclass 6, count 0 2006.176.08:27:30.95#ibcon#*before return 0, iclass 6, count 0 2006.176.08:27:30.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:27:30.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.176.08:27:30.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.176.08:27:30.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.176.08:27:30.95$vc4f8/vb=2,4 2006.176.08:27:30.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.176.08:27:30.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.176.08:27:30.95#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:30.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:31.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:31.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:31.01#ibcon#enter wrdev, iclass 11, count 2 2006.176.08:27:31.01#ibcon#first serial, iclass 11, count 2 2006.176.08:27:31.01#ibcon#enter sib2, iclass 11, count 2 2006.176.08:27:31.01#ibcon#flushed, iclass 11, count 2 2006.176.08:27:31.01#ibcon#about to write, iclass 11, count 2 2006.176.08:27:31.01#ibcon#wrote, iclass 11, count 2 2006.176.08:27:31.01#ibcon#about to read 3, iclass 11, count 2 2006.176.08:27:31.03#ibcon#read 3, iclass 11, count 2 2006.176.08:27:31.03#ibcon#about to read 4, iclass 11, count 2 2006.176.08:27:31.03#ibcon#read 4, iclass 11, count 2 2006.176.08:27:31.03#ibcon#about to read 5, iclass 11, count 2 2006.176.08:27:31.03#ibcon#read 5, iclass 11, count 2 2006.176.08:27:31.03#ibcon#about to read 6, iclass 11, count 2 2006.176.08:27:31.03#ibcon#read 6, iclass 11, count 2 2006.176.08:27:31.03#ibcon#end of sib2, iclass 11, count 2 2006.176.08:27:31.03#ibcon#*mode == 0, iclass 11, count 2 2006.176.08:27:31.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.176.08:27:31.03#ibcon#[27=AT02-04\r\n] 2006.176.08:27:31.03#ibcon#*before write, iclass 11, count 2 2006.176.08:27:31.03#ibcon#enter sib2, iclass 11, count 2 2006.176.08:27:31.03#ibcon#flushed, iclass 11, count 2 2006.176.08:27:31.03#ibcon#about to write, iclass 11, count 2 2006.176.08:27:31.03#ibcon#wrote, iclass 11, count 2 2006.176.08:27:31.03#ibcon#about to read 3, iclass 11, count 2 2006.176.08:27:31.06#ibcon#read 3, iclass 11, count 2 2006.176.08:27:31.06#ibcon#about to read 4, iclass 11, count 2 2006.176.08:27:31.06#ibcon#read 4, iclass 11, count 2 2006.176.08:27:31.06#ibcon#about to read 5, iclass 11, count 2 2006.176.08:27:31.06#ibcon#read 5, iclass 11, count 2 2006.176.08:27:31.06#ibcon#about to read 6, iclass 11, count 2 2006.176.08:27:31.06#ibcon#read 6, iclass 11, count 2 2006.176.08:27:31.06#ibcon#end of sib2, iclass 11, count 2 2006.176.08:27:31.06#ibcon#*after write, iclass 11, count 2 2006.176.08:27:31.06#ibcon#*before return 0, iclass 11, count 2 2006.176.08:27:31.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:31.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.176.08:27:31.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.176.08:27:31.06#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:31.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:31.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:31.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:31.18#ibcon#enter wrdev, iclass 11, count 0 2006.176.08:27:31.18#ibcon#first serial, iclass 11, count 0 2006.176.08:27:31.18#ibcon#enter sib2, iclass 11, count 0 2006.176.08:27:31.18#ibcon#flushed, iclass 11, count 0 2006.176.08:27:31.18#ibcon#about to write, iclass 11, count 0 2006.176.08:27:31.18#ibcon#wrote, iclass 11, count 0 2006.176.08:27:31.18#ibcon#about to read 3, iclass 11, count 0 2006.176.08:27:31.20#ibcon#read 3, iclass 11, count 0 2006.176.08:27:31.20#ibcon#about to read 4, iclass 11, count 0 2006.176.08:27:31.20#ibcon#read 4, iclass 11, count 0 2006.176.08:27:31.20#ibcon#about to read 5, iclass 11, count 0 2006.176.08:27:31.20#ibcon#read 5, iclass 11, count 0 2006.176.08:27:31.20#ibcon#about to read 6, iclass 11, count 0 2006.176.08:27:31.20#ibcon#read 6, iclass 11, count 0 2006.176.08:27:31.20#ibcon#end of sib2, iclass 11, count 0 2006.176.08:27:31.20#ibcon#*mode == 0, iclass 11, count 0 2006.176.08:27:31.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.176.08:27:31.20#ibcon#[27=USB\r\n] 2006.176.08:27:31.20#ibcon#*before write, iclass 11, count 0 2006.176.08:27:31.20#ibcon#enter sib2, iclass 11, count 0 2006.176.08:27:31.20#ibcon#flushed, iclass 11, count 0 2006.176.08:27:31.20#ibcon#about to write, iclass 11, count 0 2006.176.08:27:31.20#ibcon#wrote, iclass 11, count 0 2006.176.08:27:31.20#ibcon#about to read 3, iclass 11, count 0 2006.176.08:27:31.23#ibcon#read 3, iclass 11, count 0 2006.176.08:27:31.23#ibcon#about to read 4, iclass 11, count 0 2006.176.08:27:31.23#ibcon#read 4, iclass 11, count 0 2006.176.08:27:31.23#ibcon#about to read 5, iclass 11, count 0 2006.176.08:27:31.23#ibcon#read 5, iclass 11, count 0 2006.176.08:27:31.23#ibcon#about to read 6, iclass 11, count 0 2006.176.08:27:31.23#ibcon#read 6, iclass 11, count 0 2006.176.08:27:31.23#ibcon#end of sib2, iclass 11, count 0 2006.176.08:27:31.23#ibcon#*after write, iclass 11, count 0 2006.176.08:27:31.23#ibcon#*before return 0, iclass 11, count 0 2006.176.08:27:31.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:31.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.176.08:27:31.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.176.08:27:31.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.176.08:27:31.23$vc4f8/vblo=3,656.99 2006.176.08:27:31.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.176.08:27:31.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.176.08:27:31.23#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:31.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:31.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:31.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:31.23#ibcon#enter wrdev, iclass 13, count 0 2006.176.08:27:31.23#ibcon#first serial, iclass 13, count 0 2006.176.08:27:31.23#ibcon#enter sib2, iclass 13, count 0 2006.176.08:27:31.23#ibcon#flushed, iclass 13, count 0 2006.176.08:27:31.23#ibcon#about to write, iclass 13, count 0 2006.176.08:27:31.23#ibcon#wrote, iclass 13, count 0 2006.176.08:27:31.23#ibcon#about to read 3, iclass 13, count 0 2006.176.08:27:31.25#ibcon#read 3, iclass 13, count 0 2006.176.08:27:31.25#ibcon#about to read 4, iclass 13, count 0 2006.176.08:27:31.25#ibcon#read 4, iclass 13, count 0 2006.176.08:27:31.25#ibcon#about to read 5, iclass 13, count 0 2006.176.08:27:31.25#ibcon#read 5, iclass 13, count 0 2006.176.08:27:31.25#ibcon#about to read 6, iclass 13, count 0 2006.176.08:27:31.25#ibcon#read 6, iclass 13, count 0 2006.176.08:27:31.25#ibcon#end of sib2, iclass 13, count 0 2006.176.08:27:31.25#ibcon#*mode == 0, iclass 13, count 0 2006.176.08:27:31.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.176.08:27:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.176.08:27:31.25#ibcon#*before write, iclass 13, count 0 2006.176.08:27:31.25#ibcon#enter sib2, iclass 13, count 0 2006.176.08:27:31.25#ibcon#flushed, iclass 13, count 0 2006.176.08:27:31.25#ibcon#about to write, iclass 13, count 0 2006.176.08:27:31.25#ibcon#wrote, iclass 13, count 0 2006.176.08:27:31.25#ibcon#about to read 3, iclass 13, count 0 2006.176.08:27:31.29#ibcon#read 3, iclass 13, count 0 2006.176.08:27:31.29#ibcon#about to read 4, iclass 13, count 0 2006.176.08:27:31.29#ibcon#read 4, iclass 13, count 0 2006.176.08:27:31.29#ibcon#about to read 5, iclass 13, count 0 2006.176.08:27:31.29#ibcon#read 5, iclass 13, count 0 2006.176.08:27:31.29#ibcon#about to read 6, iclass 13, count 0 2006.176.08:27:31.29#ibcon#read 6, iclass 13, count 0 2006.176.08:27:31.29#ibcon#end of sib2, iclass 13, count 0 2006.176.08:27:31.29#ibcon#*after write, iclass 13, count 0 2006.176.08:27:31.29#ibcon#*before return 0, iclass 13, count 0 2006.176.08:27:31.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:31.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.176.08:27:31.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.176.08:27:31.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.176.08:27:31.29$vc4f8/vb=3,4 2006.176.08:27:31.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.176.08:27:31.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.176.08:27:31.29#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:31.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:31.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:31.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:31.35#ibcon#enter wrdev, iclass 15, count 2 2006.176.08:27:31.35#ibcon#first serial, iclass 15, count 2 2006.176.08:27:31.35#ibcon#enter sib2, iclass 15, count 2 2006.176.08:27:31.35#ibcon#flushed, iclass 15, count 2 2006.176.08:27:31.35#ibcon#about to write, iclass 15, count 2 2006.176.08:27:31.35#ibcon#wrote, iclass 15, count 2 2006.176.08:27:31.35#ibcon#about to read 3, iclass 15, count 2 2006.176.08:27:31.37#ibcon#read 3, iclass 15, count 2 2006.176.08:27:31.37#ibcon#about to read 4, iclass 15, count 2 2006.176.08:27:31.37#ibcon#read 4, iclass 15, count 2 2006.176.08:27:31.37#ibcon#about to read 5, iclass 15, count 2 2006.176.08:27:31.37#ibcon#read 5, iclass 15, count 2 2006.176.08:27:31.37#ibcon#about to read 6, iclass 15, count 2 2006.176.08:27:31.37#ibcon#read 6, iclass 15, count 2 2006.176.08:27:31.37#ibcon#end of sib2, iclass 15, count 2 2006.176.08:27:31.37#ibcon#*mode == 0, iclass 15, count 2 2006.176.08:27:31.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.176.08:27:31.37#ibcon#[27=AT03-04\r\n] 2006.176.08:27:31.37#ibcon#*before write, iclass 15, count 2 2006.176.08:27:31.37#ibcon#enter sib2, iclass 15, count 2 2006.176.08:27:31.37#ibcon#flushed, iclass 15, count 2 2006.176.08:27:31.37#ibcon#about to write, iclass 15, count 2 2006.176.08:27:31.37#ibcon#wrote, iclass 15, count 2 2006.176.08:27:31.37#ibcon#about to read 3, iclass 15, count 2 2006.176.08:27:31.40#ibcon#read 3, iclass 15, count 2 2006.176.08:27:31.40#ibcon#about to read 4, iclass 15, count 2 2006.176.08:27:31.40#ibcon#read 4, iclass 15, count 2 2006.176.08:27:31.40#ibcon#about to read 5, iclass 15, count 2 2006.176.08:27:31.40#ibcon#read 5, iclass 15, count 2 2006.176.08:27:31.40#ibcon#about to read 6, iclass 15, count 2 2006.176.08:27:31.40#ibcon#read 6, iclass 15, count 2 2006.176.08:27:31.40#ibcon#end of sib2, iclass 15, count 2 2006.176.08:27:31.40#ibcon#*after write, iclass 15, count 2 2006.176.08:27:31.40#ibcon#*before return 0, iclass 15, count 2 2006.176.08:27:31.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:31.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.176.08:27:31.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.176.08:27:31.40#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:31.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:31.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:31.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:31.52#ibcon#enter wrdev, iclass 15, count 0 2006.176.08:27:31.52#ibcon#first serial, iclass 15, count 0 2006.176.08:27:31.52#ibcon#enter sib2, iclass 15, count 0 2006.176.08:27:31.52#ibcon#flushed, iclass 15, count 0 2006.176.08:27:31.52#ibcon#about to write, iclass 15, count 0 2006.176.08:27:31.52#ibcon#wrote, iclass 15, count 0 2006.176.08:27:31.52#ibcon#about to read 3, iclass 15, count 0 2006.176.08:27:31.54#ibcon#read 3, iclass 15, count 0 2006.176.08:27:31.54#ibcon#about to read 4, iclass 15, count 0 2006.176.08:27:31.54#ibcon#read 4, iclass 15, count 0 2006.176.08:27:31.54#ibcon#about to read 5, iclass 15, count 0 2006.176.08:27:31.54#ibcon#read 5, iclass 15, count 0 2006.176.08:27:31.54#ibcon#about to read 6, iclass 15, count 0 2006.176.08:27:31.54#ibcon#read 6, iclass 15, count 0 2006.176.08:27:31.54#ibcon#end of sib2, iclass 15, count 0 2006.176.08:27:31.54#ibcon#*mode == 0, iclass 15, count 0 2006.176.08:27:31.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.176.08:27:31.54#ibcon#[27=USB\r\n] 2006.176.08:27:31.54#ibcon#*before write, iclass 15, count 0 2006.176.08:27:31.54#ibcon#enter sib2, iclass 15, count 0 2006.176.08:27:31.54#ibcon#flushed, iclass 15, count 0 2006.176.08:27:31.54#ibcon#about to write, iclass 15, count 0 2006.176.08:27:31.54#ibcon#wrote, iclass 15, count 0 2006.176.08:27:31.54#ibcon#about to read 3, iclass 15, count 0 2006.176.08:27:31.57#ibcon#read 3, iclass 15, count 0 2006.176.08:27:31.57#ibcon#about to read 4, iclass 15, count 0 2006.176.08:27:31.57#ibcon#read 4, iclass 15, count 0 2006.176.08:27:31.57#ibcon#about to read 5, iclass 15, count 0 2006.176.08:27:31.57#ibcon#read 5, iclass 15, count 0 2006.176.08:27:31.57#ibcon#about to read 6, iclass 15, count 0 2006.176.08:27:31.57#ibcon#read 6, iclass 15, count 0 2006.176.08:27:31.57#ibcon#end of sib2, iclass 15, count 0 2006.176.08:27:31.57#ibcon#*after write, iclass 15, count 0 2006.176.08:27:31.57#ibcon#*before return 0, iclass 15, count 0 2006.176.08:27:31.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:31.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.176.08:27:31.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.176.08:27:31.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.176.08:27:31.57$vc4f8/vblo=4,712.99 2006.176.08:27:31.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.176.08:27:31.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.176.08:27:31.57#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:31.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:31.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:31.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:31.57#ibcon#enter wrdev, iclass 17, count 0 2006.176.08:27:31.57#ibcon#first serial, iclass 17, count 0 2006.176.08:27:31.57#ibcon#enter sib2, iclass 17, count 0 2006.176.08:27:31.57#ibcon#flushed, iclass 17, count 0 2006.176.08:27:31.57#ibcon#about to write, iclass 17, count 0 2006.176.08:27:31.57#ibcon#wrote, iclass 17, count 0 2006.176.08:27:31.57#ibcon#about to read 3, iclass 17, count 0 2006.176.08:27:31.59#ibcon#read 3, iclass 17, count 0 2006.176.08:27:31.59#ibcon#about to read 4, iclass 17, count 0 2006.176.08:27:31.59#ibcon#read 4, iclass 17, count 0 2006.176.08:27:31.59#ibcon#about to read 5, iclass 17, count 0 2006.176.08:27:31.59#ibcon#read 5, iclass 17, count 0 2006.176.08:27:31.59#ibcon#about to read 6, iclass 17, count 0 2006.176.08:27:31.59#ibcon#read 6, iclass 17, count 0 2006.176.08:27:31.59#ibcon#end of sib2, iclass 17, count 0 2006.176.08:27:31.59#ibcon#*mode == 0, iclass 17, count 0 2006.176.08:27:31.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.176.08:27:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.176.08:27:31.59#ibcon#*before write, iclass 17, count 0 2006.176.08:27:31.59#ibcon#enter sib2, iclass 17, count 0 2006.176.08:27:31.59#ibcon#flushed, iclass 17, count 0 2006.176.08:27:31.59#ibcon#about to write, iclass 17, count 0 2006.176.08:27:31.59#ibcon#wrote, iclass 17, count 0 2006.176.08:27:31.59#ibcon#about to read 3, iclass 17, count 0 2006.176.08:27:31.63#ibcon#read 3, iclass 17, count 0 2006.176.08:27:31.63#ibcon#about to read 4, iclass 17, count 0 2006.176.08:27:31.63#ibcon#read 4, iclass 17, count 0 2006.176.08:27:31.63#ibcon#about to read 5, iclass 17, count 0 2006.176.08:27:31.63#ibcon#read 5, iclass 17, count 0 2006.176.08:27:31.63#ibcon#about to read 6, iclass 17, count 0 2006.176.08:27:31.63#ibcon#read 6, iclass 17, count 0 2006.176.08:27:31.63#ibcon#end of sib2, iclass 17, count 0 2006.176.08:27:31.63#ibcon#*after write, iclass 17, count 0 2006.176.08:27:31.63#ibcon#*before return 0, iclass 17, count 0 2006.176.08:27:31.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:31.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.176.08:27:31.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.176.08:27:31.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.176.08:27:31.63$vc4f8/vb=4,4 2006.176.08:27:31.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.176.08:27:31.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.176.08:27:31.63#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:31.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:31.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:31.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:31.69#ibcon#enter wrdev, iclass 19, count 2 2006.176.08:27:31.69#ibcon#first serial, iclass 19, count 2 2006.176.08:27:31.69#ibcon#enter sib2, iclass 19, count 2 2006.176.08:27:31.69#ibcon#flushed, iclass 19, count 2 2006.176.08:27:31.69#ibcon#about to write, iclass 19, count 2 2006.176.08:27:31.69#ibcon#wrote, iclass 19, count 2 2006.176.08:27:31.69#ibcon#about to read 3, iclass 19, count 2 2006.176.08:27:31.71#ibcon#read 3, iclass 19, count 2 2006.176.08:27:31.71#ibcon#about to read 4, iclass 19, count 2 2006.176.08:27:31.71#ibcon#read 4, iclass 19, count 2 2006.176.08:27:31.71#ibcon#about to read 5, iclass 19, count 2 2006.176.08:27:31.71#ibcon#read 5, iclass 19, count 2 2006.176.08:27:31.71#ibcon#about to read 6, iclass 19, count 2 2006.176.08:27:31.71#ibcon#read 6, iclass 19, count 2 2006.176.08:27:31.71#ibcon#end of sib2, iclass 19, count 2 2006.176.08:27:31.71#ibcon#*mode == 0, iclass 19, count 2 2006.176.08:27:31.71#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.176.08:27:31.71#ibcon#[27=AT04-04\r\n] 2006.176.08:27:31.71#ibcon#*before write, iclass 19, count 2 2006.176.08:27:31.71#ibcon#enter sib2, iclass 19, count 2 2006.176.08:27:31.71#ibcon#flushed, iclass 19, count 2 2006.176.08:27:31.71#ibcon#about to write, iclass 19, count 2 2006.176.08:27:31.71#ibcon#wrote, iclass 19, count 2 2006.176.08:27:31.71#ibcon#about to read 3, iclass 19, count 2 2006.176.08:27:31.74#ibcon#read 3, iclass 19, count 2 2006.176.08:27:31.74#ibcon#about to read 4, iclass 19, count 2 2006.176.08:27:31.74#ibcon#read 4, iclass 19, count 2 2006.176.08:27:31.74#ibcon#about to read 5, iclass 19, count 2 2006.176.08:27:31.74#ibcon#read 5, iclass 19, count 2 2006.176.08:27:31.74#ibcon#about to read 6, iclass 19, count 2 2006.176.08:27:31.74#ibcon#read 6, iclass 19, count 2 2006.176.08:27:31.74#ibcon#end of sib2, iclass 19, count 2 2006.176.08:27:31.74#ibcon#*after write, iclass 19, count 2 2006.176.08:27:31.74#ibcon#*before return 0, iclass 19, count 2 2006.176.08:27:31.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:31.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.176.08:27:31.74#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.176.08:27:31.74#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:31.74#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:31.86#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:31.86#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:31.86#ibcon#enter wrdev, iclass 19, count 0 2006.176.08:27:31.86#ibcon#first serial, iclass 19, count 0 2006.176.08:27:31.86#ibcon#enter sib2, iclass 19, count 0 2006.176.08:27:31.86#ibcon#flushed, iclass 19, count 0 2006.176.08:27:31.86#ibcon#about to write, iclass 19, count 0 2006.176.08:27:31.86#ibcon#wrote, iclass 19, count 0 2006.176.08:27:31.86#ibcon#about to read 3, iclass 19, count 0 2006.176.08:27:31.88#ibcon#read 3, iclass 19, count 0 2006.176.08:27:31.88#ibcon#about to read 4, iclass 19, count 0 2006.176.08:27:31.88#ibcon#read 4, iclass 19, count 0 2006.176.08:27:31.88#ibcon#about to read 5, iclass 19, count 0 2006.176.08:27:31.88#ibcon#read 5, iclass 19, count 0 2006.176.08:27:31.88#ibcon#about to read 6, iclass 19, count 0 2006.176.08:27:31.88#ibcon#read 6, iclass 19, count 0 2006.176.08:27:31.88#ibcon#end of sib2, iclass 19, count 0 2006.176.08:27:31.88#ibcon#*mode == 0, iclass 19, count 0 2006.176.08:27:31.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.176.08:27:31.88#ibcon#[27=USB\r\n] 2006.176.08:27:31.88#ibcon#*before write, iclass 19, count 0 2006.176.08:27:31.88#ibcon#enter sib2, iclass 19, count 0 2006.176.08:27:31.88#ibcon#flushed, iclass 19, count 0 2006.176.08:27:31.88#ibcon#about to write, iclass 19, count 0 2006.176.08:27:31.88#ibcon#wrote, iclass 19, count 0 2006.176.08:27:31.88#ibcon#about to read 3, iclass 19, count 0 2006.176.08:27:31.91#ibcon#read 3, iclass 19, count 0 2006.176.08:27:31.91#ibcon#about to read 4, iclass 19, count 0 2006.176.08:27:31.91#ibcon#read 4, iclass 19, count 0 2006.176.08:27:31.91#ibcon#about to read 5, iclass 19, count 0 2006.176.08:27:31.91#ibcon#read 5, iclass 19, count 0 2006.176.08:27:31.91#ibcon#about to read 6, iclass 19, count 0 2006.176.08:27:31.91#ibcon#read 6, iclass 19, count 0 2006.176.08:27:31.91#ibcon#end of sib2, iclass 19, count 0 2006.176.08:27:31.91#ibcon#*after write, iclass 19, count 0 2006.176.08:27:31.91#ibcon#*before return 0, iclass 19, count 0 2006.176.08:27:31.91#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:31.91#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.176.08:27:31.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.176.08:27:31.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.176.08:27:31.91$vc4f8/vblo=5,744.99 2006.176.08:27:31.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.176.08:27:31.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.176.08:27:31.91#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:31.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:31.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:31.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:31.91#ibcon#enter wrdev, iclass 21, count 0 2006.176.08:27:31.91#ibcon#first serial, iclass 21, count 0 2006.176.08:27:31.91#ibcon#enter sib2, iclass 21, count 0 2006.176.08:27:31.91#ibcon#flushed, iclass 21, count 0 2006.176.08:27:31.91#ibcon#about to write, iclass 21, count 0 2006.176.08:27:31.91#ibcon#wrote, iclass 21, count 0 2006.176.08:27:31.91#ibcon#about to read 3, iclass 21, count 0 2006.176.08:27:31.93#ibcon#read 3, iclass 21, count 0 2006.176.08:27:31.93#ibcon#about to read 4, iclass 21, count 0 2006.176.08:27:31.93#ibcon#read 4, iclass 21, count 0 2006.176.08:27:31.93#ibcon#about to read 5, iclass 21, count 0 2006.176.08:27:31.93#ibcon#read 5, iclass 21, count 0 2006.176.08:27:31.93#ibcon#about to read 6, iclass 21, count 0 2006.176.08:27:31.93#ibcon#read 6, iclass 21, count 0 2006.176.08:27:31.93#ibcon#end of sib2, iclass 21, count 0 2006.176.08:27:31.93#ibcon#*mode == 0, iclass 21, count 0 2006.176.08:27:31.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.176.08:27:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.176.08:27:31.93#ibcon#*before write, iclass 21, count 0 2006.176.08:27:31.93#ibcon#enter sib2, iclass 21, count 0 2006.176.08:27:31.93#ibcon#flushed, iclass 21, count 0 2006.176.08:27:31.93#ibcon#about to write, iclass 21, count 0 2006.176.08:27:31.93#ibcon#wrote, iclass 21, count 0 2006.176.08:27:31.93#ibcon#about to read 3, iclass 21, count 0 2006.176.08:27:31.97#ibcon#read 3, iclass 21, count 0 2006.176.08:27:31.97#ibcon#about to read 4, iclass 21, count 0 2006.176.08:27:31.97#ibcon#read 4, iclass 21, count 0 2006.176.08:27:31.97#ibcon#about to read 5, iclass 21, count 0 2006.176.08:27:31.97#ibcon#read 5, iclass 21, count 0 2006.176.08:27:31.97#ibcon#about to read 6, iclass 21, count 0 2006.176.08:27:31.97#ibcon#read 6, iclass 21, count 0 2006.176.08:27:31.97#ibcon#end of sib2, iclass 21, count 0 2006.176.08:27:31.97#ibcon#*after write, iclass 21, count 0 2006.176.08:27:31.97#ibcon#*before return 0, iclass 21, count 0 2006.176.08:27:31.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:31.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.176.08:27:31.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.176.08:27:31.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.176.08:27:31.97$vc4f8/vb=5,4 2006.176.08:27:31.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.176.08:27:31.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.176.08:27:31.97#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:31.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:32.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:32.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:32.03#ibcon#enter wrdev, iclass 23, count 2 2006.176.08:27:32.03#ibcon#first serial, iclass 23, count 2 2006.176.08:27:32.03#ibcon#enter sib2, iclass 23, count 2 2006.176.08:27:32.03#ibcon#flushed, iclass 23, count 2 2006.176.08:27:32.03#ibcon#about to write, iclass 23, count 2 2006.176.08:27:32.03#ibcon#wrote, iclass 23, count 2 2006.176.08:27:32.03#ibcon#about to read 3, iclass 23, count 2 2006.176.08:27:32.05#ibcon#read 3, iclass 23, count 2 2006.176.08:27:32.05#ibcon#about to read 4, iclass 23, count 2 2006.176.08:27:32.05#ibcon#read 4, iclass 23, count 2 2006.176.08:27:32.05#ibcon#about to read 5, iclass 23, count 2 2006.176.08:27:32.05#ibcon#read 5, iclass 23, count 2 2006.176.08:27:32.05#ibcon#about to read 6, iclass 23, count 2 2006.176.08:27:32.05#ibcon#read 6, iclass 23, count 2 2006.176.08:27:32.05#ibcon#end of sib2, iclass 23, count 2 2006.176.08:27:32.05#ibcon#*mode == 0, iclass 23, count 2 2006.176.08:27:32.05#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.176.08:27:32.05#ibcon#[27=AT05-04\r\n] 2006.176.08:27:32.05#ibcon#*before write, iclass 23, count 2 2006.176.08:27:32.05#ibcon#enter sib2, iclass 23, count 2 2006.176.08:27:32.05#ibcon#flushed, iclass 23, count 2 2006.176.08:27:32.05#ibcon#about to write, iclass 23, count 2 2006.176.08:27:32.05#ibcon#wrote, iclass 23, count 2 2006.176.08:27:32.05#ibcon#about to read 3, iclass 23, count 2 2006.176.08:27:32.08#ibcon#read 3, iclass 23, count 2 2006.176.08:27:32.08#ibcon#about to read 4, iclass 23, count 2 2006.176.08:27:32.08#ibcon#read 4, iclass 23, count 2 2006.176.08:27:32.08#ibcon#about to read 5, iclass 23, count 2 2006.176.08:27:32.08#ibcon#read 5, iclass 23, count 2 2006.176.08:27:32.08#ibcon#about to read 6, iclass 23, count 2 2006.176.08:27:32.08#ibcon#read 6, iclass 23, count 2 2006.176.08:27:32.08#ibcon#end of sib2, iclass 23, count 2 2006.176.08:27:32.08#ibcon#*after write, iclass 23, count 2 2006.176.08:27:32.08#ibcon#*before return 0, iclass 23, count 2 2006.176.08:27:32.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:32.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.176.08:27:32.08#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.176.08:27:32.08#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:32.08#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:32.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:32.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:32.20#ibcon#enter wrdev, iclass 23, count 0 2006.176.08:27:32.20#ibcon#first serial, iclass 23, count 0 2006.176.08:27:32.20#ibcon#enter sib2, iclass 23, count 0 2006.176.08:27:32.20#ibcon#flushed, iclass 23, count 0 2006.176.08:27:32.20#ibcon#about to write, iclass 23, count 0 2006.176.08:27:32.20#ibcon#wrote, iclass 23, count 0 2006.176.08:27:32.20#ibcon#about to read 3, iclass 23, count 0 2006.176.08:27:32.24#ibcon#read 3, iclass 23, count 0 2006.176.08:27:32.24#ibcon#about to read 4, iclass 23, count 0 2006.176.08:27:32.24#ibcon#read 4, iclass 23, count 0 2006.176.08:27:32.24#ibcon#about to read 5, iclass 23, count 0 2006.176.08:27:32.24#ibcon#read 5, iclass 23, count 0 2006.176.08:27:32.24#ibcon#about to read 6, iclass 23, count 0 2006.176.08:27:32.24#ibcon#read 6, iclass 23, count 0 2006.176.08:27:32.24#ibcon#end of sib2, iclass 23, count 0 2006.176.08:27:32.24#ibcon#*mode == 0, iclass 23, count 0 2006.176.08:27:32.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.176.08:27:32.24#ibcon#[27=USB\r\n] 2006.176.08:27:32.24#ibcon#*before write, iclass 23, count 0 2006.176.08:27:32.24#ibcon#enter sib2, iclass 23, count 0 2006.176.08:27:32.24#ibcon#flushed, iclass 23, count 0 2006.176.08:27:32.24#ibcon#about to write, iclass 23, count 0 2006.176.08:27:32.24#ibcon#wrote, iclass 23, count 0 2006.176.08:27:32.24#ibcon#about to read 3, iclass 23, count 0 2006.176.08:27:32.27#ibcon#read 3, iclass 23, count 0 2006.176.08:27:32.27#ibcon#about to read 4, iclass 23, count 0 2006.176.08:27:32.27#ibcon#read 4, iclass 23, count 0 2006.176.08:27:32.27#ibcon#about to read 5, iclass 23, count 0 2006.176.08:27:32.27#ibcon#read 5, iclass 23, count 0 2006.176.08:27:32.27#ibcon#about to read 6, iclass 23, count 0 2006.176.08:27:32.27#ibcon#read 6, iclass 23, count 0 2006.176.08:27:32.27#ibcon#end of sib2, iclass 23, count 0 2006.176.08:27:32.27#ibcon#*after write, iclass 23, count 0 2006.176.08:27:32.27#ibcon#*before return 0, iclass 23, count 0 2006.176.08:27:32.27#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:32.27#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.176.08:27:32.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.176.08:27:32.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.176.08:27:32.27$vc4f8/vblo=6,752.99 2006.176.08:27:32.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.176.08:27:32.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.176.08:27:32.27#ibcon#ireg 17 cls_cnt 0 2006.176.08:27:32.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:32.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:32.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:32.27#ibcon#enter wrdev, iclass 25, count 0 2006.176.08:27:32.27#ibcon#first serial, iclass 25, count 0 2006.176.08:27:32.27#ibcon#enter sib2, iclass 25, count 0 2006.176.08:27:32.27#ibcon#flushed, iclass 25, count 0 2006.176.08:27:32.27#ibcon#about to write, iclass 25, count 0 2006.176.08:27:32.27#ibcon#wrote, iclass 25, count 0 2006.176.08:27:32.27#ibcon#about to read 3, iclass 25, count 0 2006.176.08:27:32.29#ibcon#read 3, iclass 25, count 0 2006.176.08:27:32.29#ibcon#about to read 4, iclass 25, count 0 2006.176.08:27:32.29#ibcon#read 4, iclass 25, count 0 2006.176.08:27:32.29#ibcon#about to read 5, iclass 25, count 0 2006.176.08:27:32.29#ibcon#read 5, iclass 25, count 0 2006.176.08:27:32.29#ibcon#about to read 6, iclass 25, count 0 2006.176.08:27:32.29#ibcon#read 6, iclass 25, count 0 2006.176.08:27:32.29#ibcon#end of sib2, iclass 25, count 0 2006.176.08:27:32.29#ibcon#*mode == 0, iclass 25, count 0 2006.176.08:27:32.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.176.08:27:32.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.176.08:27:32.29#ibcon#*before write, iclass 25, count 0 2006.176.08:27:32.29#ibcon#enter sib2, iclass 25, count 0 2006.176.08:27:32.29#ibcon#flushed, iclass 25, count 0 2006.176.08:27:32.29#ibcon#about to write, iclass 25, count 0 2006.176.08:27:32.29#ibcon#wrote, iclass 25, count 0 2006.176.08:27:32.29#ibcon#about to read 3, iclass 25, count 0 2006.176.08:27:32.33#ibcon#read 3, iclass 25, count 0 2006.176.08:27:32.33#ibcon#about to read 4, iclass 25, count 0 2006.176.08:27:32.33#ibcon#read 4, iclass 25, count 0 2006.176.08:27:32.33#ibcon#about to read 5, iclass 25, count 0 2006.176.08:27:32.33#ibcon#read 5, iclass 25, count 0 2006.176.08:27:32.33#ibcon#about to read 6, iclass 25, count 0 2006.176.08:27:32.33#ibcon#read 6, iclass 25, count 0 2006.176.08:27:32.33#ibcon#end of sib2, iclass 25, count 0 2006.176.08:27:32.33#ibcon#*after write, iclass 25, count 0 2006.176.08:27:32.33#ibcon#*before return 0, iclass 25, count 0 2006.176.08:27:32.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:32.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.176.08:27:32.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.176.08:27:32.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.176.08:27:32.33$vc4f8/vb=6,4 2006.176.08:27:32.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.176.08:27:32.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.176.08:27:32.33#ibcon#ireg 11 cls_cnt 2 2006.176.08:27:32.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:32.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:32.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:32.39#ibcon#enter wrdev, iclass 27, count 2 2006.176.08:27:32.39#ibcon#first serial, iclass 27, count 2 2006.176.08:27:32.39#ibcon#enter sib2, iclass 27, count 2 2006.176.08:27:32.39#ibcon#flushed, iclass 27, count 2 2006.176.08:27:32.39#ibcon#about to write, iclass 27, count 2 2006.176.08:27:32.39#ibcon#wrote, iclass 27, count 2 2006.176.08:27:32.39#ibcon#about to read 3, iclass 27, count 2 2006.176.08:27:32.41#ibcon#read 3, iclass 27, count 2 2006.176.08:27:32.41#ibcon#about to read 4, iclass 27, count 2 2006.176.08:27:32.41#ibcon#read 4, iclass 27, count 2 2006.176.08:27:32.41#ibcon#about to read 5, iclass 27, count 2 2006.176.08:27:32.41#ibcon#read 5, iclass 27, count 2 2006.176.08:27:32.41#ibcon#about to read 6, iclass 27, count 2 2006.176.08:27:32.41#ibcon#read 6, iclass 27, count 2 2006.176.08:27:32.41#ibcon#end of sib2, iclass 27, count 2 2006.176.08:27:32.41#ibcon#*mode == 0, iclass 27, count 2 2006.176.08:27:32.41#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.176.08:27:32.41#ibcon#[27=AT06-04\r\n] 2006.176.08:27:32.41#ibcon#*before write, iclass 27, count 2 2006.176.08:27:32.41#ibcon#enter sib2, iclass 27, count 2 2006.176.08:27:32.41#ibcon#flushed, iclass 27, count 2 2006.176.08:27:32.41#ibcon#about to write, iclass 27, count 2 2006.176.08:27:32.41#ibcon#wrote, iclass 27, count 2 2006.176.08:27:32.41#ibcon#about to read 3, iclass 27, count 2 2006.176.08:27:32.44#ibcon#read 3, iclass 27, count 2 2006.176.08:27:32.44#ibcon#about to read 4, iclass 27, count 2 2006.176.08:27:32.44#ibcon#read 4, iclass 27, count 2 2006.176.08:27:32.44#ibcon#about to read 5, iclass 27, count 2 2006.176.08:27:32.44#ibcon#read 5, iclass 27, count 2 2006.176.08:27:32.44#ibcon#about to read 6, iclass 27, count 2 2006.176.08:27:32.44#ibcon#read 6, iclass 27, count 2 2006.176.08:27:32.44#ibcon#end of sib2, iclass 27, count 2 2006.176.08:27:32.44#ibcon#*after write, iclass 27, count 2 2006.176.08:27:32.44#ibcon#*before return 0, iclass 27, count 2 2006.176.08:27:32.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:32.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.176.08:27:32.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.176.08:27:32.44#ibcon#ireg 7 cls_cnt 0 2006.176.08:27:32.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:32.56#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:32.56#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:32.56#ibcon#enter wrdev, iclass 27, count 0 2006.176.08:27:32.56#ibcon#first serial, iclass 27, count 0 2006.176.08:27:32.56#ibcon#enter sib2, iclass 27, count 0 2006.176.08:27:32.56#ibcon#flushed, iclass 27, count 0 2006.176.08:27:32.56#ibcon#about to write, iclass 27, count 0 2006.176.08:27:32.56#ibcon#wrote, iclass 27, count 0 2006.176.08:27:32.56#ibcon#about to read 3, iclass 27, count 0 2006.176.08:27:32.58#ibcon#read 3, iclass 27, count 0 2006.176.08:27:32.58#ibcon#about to read 4, iclass 27, count 0 2006.176.08:27:32.58#ibcon#read 4, iclass 27, count 0 2006.176.08:27:32.58#ibcon#about to read 5, iclass 27, count 0 2006.176.08:27:32.58#ibcon#read 5, iclass 27, count 0 2006.176.08:27:32.58#ibcon#about to read 6, iclass 27, count 0 2006.176.08:27:32.58#ibcon#read 6, iclass 27, count 0 2006.176.08:27:32.58#ibcon#end of sib2, iclass 27, count 0 2006.176.08:27:32.58#ibcon#*mode == 0, iclass 27, count 0 2006.176.08:27:32.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.176.08:27:32.58#ibcon#[27=USB\r\n] 2006.176.08:27:32.58#ibcon#*before write, iclass 27, count 0 2006.176.08:27:32.58#ibcon#enter sib2, iclass 27, count 0 2006.176.08:27:32.58#ibcon#flushed, iclass 27, count 0 2006.176.08:27:32.58#ibcon#about to write, iclass 27, count 0 2006.176.08:27:32.58#ibcon#wrote, iclass 27, count 0 2006.176.08:27:32.58#ibcon#about to read 3, iclass 27, count 0 2006.176.08:27:32.61#ibcon#read 3, iclass 27, count 0 2006.176.08:27:32.61#ibcon#about to read 4, iclass 27, count 0 2006.176.08:27:32.61#ibcon#read 4, iclass 27, count 0 2006.176.08:27:32.61#ibcon#about to read 5, iclass 27, count 0 2006.176.08:27:32.61#ibcon#read 5, iclass 27, count 0 2006.176.08:27:32.61#ibcon#about to read 6, iclass 27, count 0 2006.176.08:27:32.61#ibcon#read 6, iclass 27, count 0 2006.176.08:27:32.61#ibcon#end of sib2, iclass 27, count 0 2006.176.08:27:32.61#ibcon#*after write, iclass 27, count 0 2006.176.08:27:32.61#ibcon#*before return 0, iclass 27, count 0 2006.176.08:27:32.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:32.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.176.08:27:32.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.176.08:27:32.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.176.08:27:32.61$vc4f8/vabw=wide 2006.176.08:27:32.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.176.08:27:32.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.176.08:27:32.61#ibcon#ireg 8 cls_cnt 0 2006.176.08:27:32.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:32.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:32.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:32.61#ibcon#enter wrdev, iclass 29, count 0 2006.176.08:27:32.61#ibcon#first serial, iclass 29, count 0 2006.176.08:27:32.61#ibcon#enter sib2, iclass 29, count 0 2006.176.08:27:32.61#ibcon#flushed, iclass 29, count 0 2006.176.08:27:32.61#ibcon#about to write, iclass 29, count 0 2006.176.08:27:32.61#ibcon#wrote, iclass 29, count 0 2006.176.08:27:32.61#ibcon#about to read 3, iclass 29, count 0 2006.176.08:27:32.63#ibcon#read 3, iclass 29, count 0 2006.176.08:27:32.63#ibcon#about to read 4, iclass 29, count 0 2006.176.08:27:32.63#ibcon#read 4, iclass 29, count 0 2006.176.08:27:32.63#ibcon#about to read 5, iclass 29, count 0 2006.176.08:27:32.63#ibcon#read 5, iclass 29, count 0 2006.176.08:27:32.63#ibcon#about to read 6, iclass 29, count 0 2006.176.08:27:32.63#ibcon#read 6, iclass 29, count 0 2006.176.08:27:32.63#ibcon#end of sib2, iclass 29, count 0 2006.176.08:27:32.63#ibcon#*mode == 0, iclass 29, count 0 2006.176.08:27:32.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.176.08:27:32.63#ibcon#[25=BW32\r\n] 2006.176.08:27:32.63#ibcon#*before write, iclass 29, count 0 2006.176.08:27:32.63#ibcon#enter sib2, iclass 29, count 0 2006.176.08:27:32.63#ibcon#flushed, iclass 29, count 0 2006.176.08:27:32.63#ibcon#about to write, iclass 29, count 0 2006.176.08:27:32.63#ibcon#wrote, iclass 29, count 0 2006.176.08:27:32.63#ibcon#about to read 3, iclass 29, count 0 2006.176.08:27:32.66#ibcon#read 3, iclass 29, count 0 2006.176.08:27:32.66#ibcon#about to read 4, iclass 29, count 0 2006.176.08:27:32.66#ibcon#read 4, iclass 29, count 0 2006.176.08:27:32.66#ibcon#about to read 5, iclass 29, count 0 2006.176.08:27:32.66#ibcon#read 5, iclass 29, count 0 2006.176.08:27:32.66#ibcon#about to read 6, iclass 29, count 0 2006.176.08:27:32.66#ibcon#read 6, iclass 29, count 0 2006.176.08:27:32.66#ibcon#end of sib2, iclass 29, count 0 2006.176.08:27:32.66#ibcon#*after write, iclass 29, count 0 2006.176.08:27:32.66#ibcon#*before return 0, iclass 29, count 0 2006.176.08:27:32.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:32.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.176.08:27:32.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.176.08:27:32.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.176.08:27:32.66$vc4f8/vbbw=wide 2006.176.08:27:32.66#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.176.08:27:32.66#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.176.08:27:32.66#ibcon#ireg 8 cls_cnt 0 2006.176.08:27:32.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:27:32.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:27:32.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:27:32.73#ibcon#enter wrdev, iclass 31, count 0 2006.176.08:27:32.73#ibcon#first serial, iclass 31, count 0 2006.176.08:27:32.73#ibcon#enter sib2, iclass 31, count 0 2006.176.08:27:32.73#ibcon#flushed, iclass 31, count 0 2006.176.08:27:32.73#ibcon#about to write, iclass 31, count 0 2006.176.08:27:32.73#ibcon#wrote, iclass 31, count 0 2006.176.08:27:32.73#ibcon#about to read 3, iclass 31, count 0 2006.176.08:27:32.75#ibcon#read 3, iclass 31, count 0 2006.176.08:27:32.75#ibcon#about to read 4, iclass 31, count 0 2006.176.08:27:32.75#ibcon#read 4, iclass 31, count 0 2006.176.08:27:32.75#ibcon#about to read 5, iclass 31, count 0 2006.176.08:27:32.75#ibcon#read 5, iclass 31, count 0 2006.176.08:27:32.75#ibcon#about to read 6, iclass 31, count 0 2006.176.08:27:32.75#ibcon#read 6, iclass 31, count 0 2006.176.08:27:32.75#ibcon#end of sib2, iclass 31, count 0 2006.176.08:27:32.75#ibcon#*mode == 0, iclass 31, count 0 2006.176.08:27:32.75#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.176.08:27:32.75#ibcon#[27=BW32\r\n] 2006.176.08:27:32.75#ibcon#*before write, iclass 31, count 0 2006.176.08:27:32.75#ibcon#enter sib2, iclass 31, count 0 2006.176.08:27:32.75#ibcon#flushed, iclass 31, count 0 2006.176.08:27:32.75#ibcon#about to write, iclass 31, count 0 2006.176.08:27:32.75#ibcon#wrote, iclass 31, count 0 2006.176.08:27:32.75#ibcon#about to read 3, iclass 31, count 0 2006.176.08:27:32.78#ibcon#read 3, iclass 31, count 0 2006.176.08:27:32.78#ibcon#about to read 4, iclass 31, count 0 2006.176.08:27:32.78#ibcon#read 4, iclass 31, count 0 2006.176.08:27:32.78#ibcon#about to read 5, iclass 31, count 0 2006.176.08:27:32.78#ibcon#read 5, iclass 31, count 0 2006.176.08:27:32.78#ibcon#about to read 6, iclass 31, count 0 2006.176.08:27:32.78#ibcon#read 6, iclass 31, count 0 2006.176.08:27:32.78#ibcon#end of sib2, iclass 31, count 0 2006.176.08:27:32.78#ibcon#*after write, iclass 31, count 0 2006.176.08:27:32.78#ibcon#*before return 0, iclass 31, count 0 2006.176.08:27:32.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:27:32.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.176.08:27:32.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.176.08:27:32.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.176.08:27:32.78$4f8m12a/ifd4f 2006.176.08:27:32.78$ifd4f/lo= 2006.176.08:27:32.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.176.08:27:32.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.176.08:27:32.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.176.08:27:32.78$ifd4f/patch= 2006.176.08:27:32.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.176.08:27:32.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.176.08:27:32.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.176.08:27:32.78$4f8m12a/"form=m,16.000,1:2 2006.176.08:27:32.78$4f8m12a/"tpicd 2006.176.08:27:32.78$4f8m12a/echo=off 2006.176.08:27:32.78$4f8m12a/xlog=off 2006.176.08:27:32.78:!2006.176.08:28:00 2006.176.08:27:39.14#trakl#Source acquired 2006.176.08:27:39.14#flagr#flagr/antenna,acquired 2006.176.08:28:00.00:preob 2006.176.08:28:01.14/onsource/TRACKING 2006.176.08:28:01.14:!2006.176.08:28:10 2006.176.08:28:10.00:data_valid=on 2006.176.08:28:10.00:midob 2006.176.08:28:10.14/onsource/TRACKING 2006.176.08:28:10.14/wx/23.70,1008.5,93 2006.176.08:28:10.30/cable/+6.4956E-03 2006.176.08:28:11.39/va/01,08,usb,yes,29,31 2006.176.08:28:11.39/va/02,07,usb,yes,30,31 2006.176.08:28:11.39/va/03,06,usb,yes,31,31 2006.176.08:28:11.39/va/04,07,usb,yes,30,33 2006.176.08:28:11.39/va/05,07,usb,yes,32,34 2006.176.08:28:11.39/va/06,06,usb,yes,31,31 2006.176.08:28:11.39/va/07,06,usb,yes,31,31 2006.176.08:28:11.39/va/08,06,usb,yes,34,33 2006.176.08:28:11.62/valo/01,532.99,yes,locked 2006.176.08:28:11.62/valo/02,572.99,yes,locked 2006.176.08:28:11.62/valo/03,672.99,yes,locked 2006.176.08:28:11.62/valo/04,832.99,yes,locked 2006.176.08:28:11.62/valo/05,652.99,yes,locked 2006.176.08:28:11.62/valo/06,772.99,yes,locked 2006.176.08:28:11.62/valo/07,832.99,yes,locked 2006.176.08:28:11.62/valo/08,852.99,yes,locked 2006.176.08:28:12.71/vb/01,04,usb,yes,29,28 2006.176.08:28:12.71/vb/02,04,usb,yes,31,32 2006.176.08:28:12.71/vb/03,04,usb,yes,27,31 2006.176.08:28:12.71/vb/04,04,usb,yes,28,28 2006.176.08:28:12.71/vb/05,04,usb,yes,27,31 2006.176.08:28:12.71/vb/06,04,usb,yes,28,30 2006.176.08:28:12.71/vb/07,04,usb,yes,30,30 2006.176.08:28:12.71/vb/08,04,usb,yes,27,31 2006.176.08:28:12.95/vblo/01,632.99,yes,locked 2006.176.08:28:12.95/vblo/02,640.99,yes,locked 2006.176.08:28:12.95/vblo/03,656.99,yes,locked 2006.176.08:28:12.95/vblo/04,712.99,yes,locked 2006.176.08:28:12.95/vblo/05,744.99,yes,locked 2006.176.08:28:12.95/vblo/06,752.99,yes,locked 2006.176.08:28:12.95/vblo/07,734.99,yes,locked 2006.176.08:28:12.95/vblo/08,744.99,yes,locked 2006.176.08:28:13.10/vabw/8 2006.176.08:28:13.25/vbbw/8 2006.176.08:28:13.36/xfe/off,on,15.5 2006.176.08:28:13.74/ifatt/23,28,28,28 2006.176.08:28:14.08/fmout-gps/S +3.68E-07 2006.176.08:28:14.15:!2006.176.08:29:10 2006.176.08:29:10.00:data_valid=off 2006.176.08:29:10.00:postob 2006.176.08:29:10.21/cable/+6.4955E-03 2006.176.08:29:10.21/wx/23.70,1008.5,93 2006.176.08:29:11.08/fmout-gps/S +3.68E-07 2006.176.08:29:11.08:checkk5last 2006.176.08:29:11.08&checkk5last/chk_obsdata=1 2006.176.08:29:11.09&checkk5last/chk_obsdata=2 2006.176.08:29:11.09&checkk5last/chk_obsdata=3 2006.176.08:29:11.09&checkk5last/chk_obsdata=4 2006.176.08:29:11.10&checkk5last/k5log=1 2006.176.08:29:11.10&checkk5last/k5log=2 2006.176.08:29:11.10&checkk5last/k5log=3 2006.176.08:29:11.11&checkk5last/k5log=4 2006.176.08:29:11.11&checkk5last/obsinfo 2006.176.08:29:11.49/chk_obsdata//k5ts1/T1760828??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:29:11.85/chk_obsdata//k5ts2/T1760828??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:29:12.23/chk_obsdata//k5ts3/T1760828??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:29:12.62/chk_obsdata//k5ts4/T1760828??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.176.08:29:13.30/k5log//k5ts1_log_newline 2006.176.08:29:13.98/k5log//k5ts2_log_newline 2006.176.08:29:14.66/k5log//k5ts3_log_newline 2006.176.08:29:15.36/k5log//k5ts4_log_newline 2006.176.08:29:15.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.176.08:29:15.38:sched_end 2006.176.08:29:15.38&sched_end/stopcheck 2006.176.08:29:15.38&stopcheck/sy=killall check_fsrun.pl 2006.176.08:29:15.38&stopcheck/" sy=killall chmem.sh 2006.176.08:29:15.47:source=idle 2006.176.08:29:16.14#flagr#flagr/antenna,new-source 2006.176.08:29:16.14:stow 2006.176.08:29:16.14&stow/source=idle 2006.176.08:29:16.15&stow/"this is stow command. 2006.176.08:29:16.15&stow/antenna=m3 2006.176.08:29:20.01:!+10m 2006.176.08:39:20.02:standby 2006.176.08:39:20.03&standby/"this is standby command. 2006.176.08:39:20.03&standby/antenna=m0 2006.176.08:39:21.01:sy=cp /usr2/log/k06176ts.log /usr2/log_backup/ 2006.176.08:39:21.10:*end of schedule