2006.175.06:24:34.66;Log Opened: Mark IV Field System Version 9.7.7 2006.175.06:24:34.66;location,TSUKUB32,-140.09,36.10,61.0 2006.175.06:24:34.66;horizon1,0.,5.,360. 2006.175.06:24:34.66;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.175.06:24:34.66;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.175.06:24:34.66;drivev11,330,270,no 2006.175.06:24:34.66;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.175.06:24:34.66;drivev13,15.000,268,10.000,10.000,10.000 2006.175.06:24:34.66;drivev21,330,270,no 2006.175.06:24:34.66;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.175.06:24:34.66;drivev23,15.000,268,10.000,10.000,10.000 2006.175.06:24:34.66;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.175.06:24:34.66;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.175.06:24:34.66;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.175.06:24:34.66;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.175.06:24:34.66;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.175.06:24:34.66;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.175.06:24:34.66;time,-0.364,101.533,rate 2006.175.06:24:34.66;flagr,200 2006.175.06:24:34.66:" K06175 2006 TSUKUB32 T Ts 2006.175.06:24:34.66:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.175.06:24:34.66:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.175.06:24:34.66:" 108 TSUKUB32 14 17400 2006.175.06:24:34.66:" drudg version 050216 compiled under FS 9.7.07 2006.175.06:24:34.66:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.175.06:24:34.66:exper_initi 2006.175.06:24:34.66&exper_initi/proc_library 2006.175.06:24:34.66&exper_initi/sched_initi 2006.175.06:24:34.66:!2006.175.06:29:50 2006.175.06:24:34.66&proc_library/" k06175 tsukub32 ts 2006.175.06:24:34.66&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.175.06:24:34.66&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.175.06:24:34.66&sched_initi/startcheck 2006.175.06:24:34.66&startcheck/sy=check_fsrun.pl & 2006.175.06:24:34.66&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.175.06:24:46.56;cable 2006.175.06:24:46.68/cable/+6.4771E-03 2006.175.06:25:28.57;cablelong 2006.175.06:25:28.65/cablelong/+7.0314E-03 2006.175.06:25:30.62;cablediff 2006.175.06:25:30.62/cablediff/554.3e-6,+ 2006.175.06:26:15.76;cable 2006.175.06:26:15.84/cable/+6.4801E-03 2006.175.06:26:32.96;wx 2006.175.06:26:32.96/wx/26.97,1007.2,69 2006.175.06:26:38.35;"Sky is fine. 2006.175.06:26:43.53;xfe 2006.175.06:26:43.63/xfe/off,on,14.7 2006.175.06:26:46.66;clockoff 2006.175.06:26:46.66&clockoff/"gps-fmout=1p 2006.175.06:26:46.66&clockoff/fmout-gps=1p 2006.175.06:26:47.07/fmout-gps/S +3.85E-07 2006.175.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.175.06:29:50.02:!2006.175.07:19:50 2006.175.07:19:50.00:unstow 2006.175.07:19:50.00&unstow/antenna=e 2006.175.07:19:50.00&unstow/!+10s 2006.175.07:19:50.00&unstow/antenna=m2 2006.175.07:20:02.02:scan_name=175-0730,k06175,60 2006.175.07:20:02.02:source=3c371,180650.68,694928.1,2000.0,ccw 2006.175.07:20:03.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.175.07:20:03.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.175.07:20:03.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.175.07:20:03.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.175.07:20:03.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.175.07:20:03.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.175.07:20:04.15:ready_k5 2006.175.07:20:04.15&ready_k5/obsinfo=st 2006.175.07:20:04.15&ready_k5/autoobs=1 2006.175.07:20:04.15&ready_k5/autoobs=2 2006.175.07:20:04.15&ready_k5/autoobs=3 2006.175.07:20:04.15&ready_k5/autoobs=4 2006.175.07:20:04.15&ready_k5/obsinfo 2006.175.07:20:04.15#flagr#flagr/antenna,new-source 2006.175.07:20:04.15/obsinfo=st/error_log.tmp was not found (or not removed). 2006.175.07:20:07.34/autoobs//k5ts1/ autoobs started! 2006.175.07:20:10.47/autoobs//k5ts2/ autoobs started! 2006.175.07:20:13.59/autoobs//k5ts3/ autoobs started! 2006.175.07:20:16.70/autoobs//k5ts4/ autoobs started! 2006.175.07:20:16.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:20:16.73:4f8m12a=1 2006.175.07:20:16.73&4f8m12a/xlog=on 2006.175.07:20:16.73&4f8m12a/echo=on 2006.175.07:20:16.73&4f8m12a/pcalon 2006.175.07:20:16.73&4f8m12a/"tpicd=stop 2006.175.07:20:16.73&4f8m12a/vc4f8 2006.175.07:20:16.73&4f8m12a/ifd4f 2006.175.07:20:16.73&4f8m12a/"form=m,16.000,1:2 2006.175.07:20:16.73&4f8m12a/"tpicd 2006.175.07:20:16.73&4f8m12a/echo=off 2006.175.07:20:16.73&4f8m12a/xlog=off 2006.175.07:20:16.73$4f8m12a/echo=on 2006.175.07:20:16.73$4f8m12a/pcalon 2006.175.07:20:16.73&pcalon/"no phase cal control is implemented here 2006.175.07:20:16.73$pcalon/"no phase cal control is implemented here 2006.175.07:20:16.73$4f8m12a/"tpicd=stop 2006.175.07:20:16.73$4f8m12a/vc4f8 2006.175.07:20:16.73&vc4f8/valo=1,532.99 2006.175.07:20:16.73&vc4f8/va=1,8 2006.175.07:20:16.73&vc4f8/valo=2,572.99 2006.175.07:20:16.73&vc4f8/va=2,7 2006.175.07:20:16.73&vc4f8/valo=3,672.99 2006.175.07:20:16.73&vc4f8/va=3,6 2006.175.07:20:16.73&vc4f8/valo=4,832.99 2006.175.07:20:16.73&vc4f8/va=4,7 2006.175.07:20:16.73&vc4f8/valo=5,652.99 2006.175.07:20:16.73&vc4f8/va=5,7 2006.175.07:20:16.73&vc4f8/valo=6,772.99 2006.175.07:20:16.73&vc4f8/va=6,6 2006.175.07:20:16.73&vc4f8/valo=7,832.99 2006.175.07:20:16.73&vc4f8/va=7,6 2006.175.07:20:16.73&vc4f8/valo=8,852.99 2006.175.07:20:16.73&vc4f8/va=8,6 2006.175.07:20:16.73&vc4f8/vblo=1,632.99 2006.175.07:20:16.73&vc4f8/vb=1,4 2006.175.07:20:16.73&vc4f8/vblo=2,640.99 2006.175.07:20:16.73&vc4f8/vb=2,4 2006.175.07:20:16.73&vc4f8/vblo=3,656.99 2006.175.07:20:16.73&vc4f8/vb=3,4 2006.175.07:20:16.73&vc4f8/vblo=4,712.99 2006.175.07:20:16.73&vc4f8/vb=4,4 2006.175.07:20:16.73&vc4f8/vblo=5,744.99 2006.175.07:20:16.73&vc4f8/vb=5,4 2006.175.07:20:16.73&vc4f8/vblo=6,752.99 2006.175.07:20:16.73&vc4f8/vb=6,4 2006.175.07:20:16.73&vc4f8/vabw=wide 2006.175.07:20:16.73&vc4f8/vbbw=wide 2006.175.07:20:16.73$vc4f8/valo=1,532.99 2006.175.07:20:16.74#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.07:20:16.74#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.07:20:16.74#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:16.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:16.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:16.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:16.74#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:20:16.74#ibcon#first serial, iclass 26, count 0 2006.175.07:20:16.74#ibcon#enter sib2, iclass 26, count 0 2006.175.07:20:16.74#ibcon#flushed, iclass 26, count 0 2006.175.07:20:16.74#ibcon#about to write, iclass 26, count 0 2006.175.07:20:16.74#ibcon#wrote, iclass 26, count 0 2006.175.07:20:16.74#ibcon#about to read 3, iclass 26, count 0 2006.175.07:20:16.77#ibcon#read 3, iclass 26, count 0 2006.175.07:20:16.77#ibcon#about to read 4, iclass 26, count 0 2006.175.07:20:16.77#ibcon#read 4, iclass 26, count 0 2006.175.07:20:16.77#ibcon#about to read 5, iclass 26, count 0 2006.175.07:20:16.77#ibcon#read 5, iclass 26, count 0 2006.175.07:20:16.77#ibcon#about to read 6, iclass 26, count 0 2006.175.07:20:16.77#ibcon#read 6, iclass 26, count 0 2006.175.07:20:16.77#ibcon#end of sib2, iclass 26, count 0 2006.175.07:20:16.77#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:20:16.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:20:16.77#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:20:16.77#ibcon#*before write, iclass 26, count 0 2006.175.07:20:16.77#ibcon#enter sib2, iclass 26, count 0 2006.175.07:20:16.77#ibcon#flushed, iclass 26, count 0 2006.175.07:20:16.77#ibcon#about to write, iclass 26, count 0 2006.175.07:20:16.77#ibcon#wrote, iclass 26, count 0 2006.175.07:20:16.77#ibcon#about to read 3, iclass 26, count 0 2006.175.07:20:16.83#ibcon#read 3, iclass 26, count 0 2006.175.07:20:16.83#ibcon#about to read 4, iclass 26, count 0 2006.175.07:20:16.83#ibcon#read 4, iclass 26, count 0 2006.175.07:20:16.83#ibcon#about to read 5, iclass 26, count 0 2006.175.07:20:16.83#ibcon#read 5, iclass 26, count 0 2006.175.07:20:16.83#ibcon#about to read 6, iclass 26, count 0 2006.175.07:20:16.83#ibcon#read 6, iclass 26, count 0 2006.175.07:20:16.83#ibcon#end of sib2, iclass 26, count 0 2006.175.07:20:16.83#ibcon#*after write, iclass 26, count 0 2006.175.07:20:16.83#ibcon#*before return 0, iclass 26, count 0 2006.175.07:20:16.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:16.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:16.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:20:16.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:20:16.84$vc4f8/va=1,8 2006.175.07:20:16.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.07:20:16.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.07:20:16.84#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:16.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:16.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:16.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:16.84#ibcon#enter wrdev, iclass 28, count 2 2006.175.07:20:16.84#ibcon#first serial, iclass 28, count 2 2006.175.07:20:16.84#ibcon#enter sib2, iclass 28, count 2 2006.175.07:20:16.84#ibcon#flushed, iclass 28, count 2 2006.175.07:20:16.84#ibcon#about to write, iclass 28, count 2 2006.175.07:20:16.84#ibcon#wrote, iclass 28, count 2 2006.175.07:20:16.84#ibcon#about to read 3, iclass 28, count 2 2006.175.07:20:16.85#ibcon#read 3, iclass 28, count 2 2006.175.07:20:16.85#ibcon#about to read 4, iclass 28, count 2 2006.175.07:20:16.85#ibcon#read 4, iclass 28, count 2 2006.175.07:20:16.85#ibcon#about to read 5, iclass 28, count 2 2006.175.07:20:16.85#ibcon#read 5, iclass 28, count 2 2006.175.07:20:16.85#ibcon#about to read 6, iclass 28, count 2 2006.175.07:20:16.85#ibcon#read 6, iclass 28, count 2 2006.175.07:20:16.85#ibcon#end of sib2, iclass 28, count 2 2006.175.07:20:16.85#ibcon#*mode == 0, iclass 28, count 2 2006.175.07:20:16.85#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.07:20:16.85#ibcon#[25=AT01-08\r\n] 2006.175.07:20:16.85#ibcon#*before write, iclass 28, count 2 2006.175.07:20:16.85#ibcon#enter sib2, iclass 28, count 2 2006.175.07:20:16.85#ibcon#flushed, iclass 28, count 2 2006.175.07:20:16.85#ibcon#about to write, iclass 28, count 2 2006.175.07:20:16.85#ibcon#wrote, iclass 28, count 2 2006.175.07:20:16.85#ibcon#about to read 3, iclass 28, count 2 2006.175.07:20:16.89#ibcon#read 3, iclass 28, count 2 2006.175.07:20:16.89#ibcon#about to read 4, iclass 28, count 2 2006.175.07:20:16.89#ibcon#read 4, iclass 28, count 2 2006.175.07:20:16.89#ibcon#about to read 5, iclass 28, count 2 2006.175.07:20:16.89#ibcon#read 5, iclass 28, count 2 2006.175.07:20:16.89#ibcon#about to read 6, iclass 28, count 2 2006.175.07:20:16.89#ibcon#read 6, iclass 28, count 2 2006.175.07:20:16.89#ibcon#end of sib2, iclass 28, count 2 2006.175.07:20:16.89#ibcon#*after write, iclass 28, count 2 2006.175.07:20:16.89#ibcon#*before return 0, iclass 28, count 2 2006.175.07:20:16.89#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:16.89#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:16.89#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.07:20:16.89#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:16.89#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:17.01#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:17.01#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:17.01#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:20:17.01#ibcon#first serial, iclass 28, count 0 2006.175.07:20:17.01#ibcon#enter sib2, iclass 28, count 0 2006.175.07:20:17.01#ibcon#flushed, iclass 28, count 0 2006.175.07:20:17.01#ibcon#about to write, iclass 28, count 0 2006.175.07:20:17.01#ibcon#wrote, iclass 28, count 0 2006.175.07:20:17.01#ibcon#about to read 3, iclass 28, count 0 2006.175.07:20:17.03#ibcon#read 3, iclass 28, count 0 2006.175.07:20:17.03#ibcon#about to read 4, iclass 28, count 0 2006.175.07:20:17.03#ibcon#read 4, iclass 28, count 0 2006.175.07:20:17.03#ibcon#about to read 5, iclass 28, count 0 2006.175.07:20:17.03#ibcon#read 5, iclass 28, count 0 2006.175.07:20:17.03#ibcon#about to read 6, iclass 28, count 0 2006.175.07:20:17.03#ibcon#read 6, iclass 28, count 0 2006.175.07:20:17.03#ibcon#end of sib2, iclass 28, count 0 2006.175.07:20:17.03#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:20:17.03#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:20:17.03#ibcon#[25=USB\r\n] 2006.175.07:20:17.03#ibcon#*before write, iclass 28, count 0 2006.175.07:20:17.03#ibcon#enter sib2, iclass 28, count 0 2006.175.07:20:17.03#ibcon#flushed, iclass 28, count 0 2006.175.07:20:17.03#ibcon#about to write, iclass 28, count 0 2006.175.07:20:17.03#ibcon#wrote, iclass 28, count 0 2006.175.07:20:17.03#ibcon#about to read 3, iclass 28, count 0 2006.175.07:20:17.06#ibcon#read 3, iclass 28, count 0 2006.175.07:20:17.06#ibcon#about to read 4, iclass 28, count 0 2006.175.07:20:17.06#ibcon#read 4, iclass 28, count 0 2006.175.07:20:17.06#ibcon#about to read 5, iclass 28, count 0 2006.175.07:20:17.06#ibcon#read 5, iclass 28, count 0 2006.175.07:20:17.06#ibcon#about to read 6, iclass 28, count 0 2006.175.07:20:17.06#ibcon#read 6, iclass 28, count 0 2006.175.07:20:17.06#ibcon#end of sib2, iclass 28, count 0 2006.175.07:20:17.06#ibcon#*after write, iclass 28, count 0 2006.175.07:20:17.06#ibcon#*before return 0, iclass 28, count 0 2006.175.07:20:17.06#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:17.06#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:17.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:20:17.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:20:17.07$vc4f8/valo=2,572.99 2006.175.07:20:17.07#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.07:20:17.07#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.07:20:17.07#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:17.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:17.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:17.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:17.07#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:20:17.07#ibcon#first serial, iclass 30, count 0 2006.175.07:20:17.07#ibcon#enter sib2, iclass 30, count 0 2006.175.07:20:17.07#ibcon#flushed, iclass 30, count 0 2006.175.07:20:17.07#ibcon#about to write, iclass 30, count 0 2006.175.07:20:17.07#ibcon#wrote, iclass 30, count 0 2006.175.07:20:17.07#ibcon#about to read 3, iclass 30, count 0 2006.175.07:20:17.09#ibcon#read 3, iclass 30, count 0 2006.175.07:20:17.09#ibcon#about to read 4, iclass 30, count 0 2006.175.07:20:17.09#ibcon#read 4, iclass 30, count 0 2006.175.07:20:17.09#ibcon#about to read 5, iclass 30, count 0 2006.175.07:20:17.09#ibcon#read 5, iclass 30, count 0 2006.175.07:20:17.09#ibcon#about to read 6, iclass 30, count 0 2006.175.07:20:17.09#ibcon#read 6, iclass 30, count 0 2006.175.07:20:17.09#ibcon#end of sib2, iclass 30, count 0 2006.175.07:20:17.09#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:20:17.09#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:20:17.09#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:20:17.09#ibcon#*before write, iclass 30, count 0 2006.175.07:20:17.09#ibcon#enter sib2, iclass 30, count 0 2006.175.07:20:17.09#ibcon#flushed, iclass 30, count 0 2006.175.07:20:17.09#ibcon#about to write, iclass 30, count 0 2006.175.07:20:17.09#ibcon#wrote, iclass 30, count 0 2006.175.07:20:17.09#ibcon#about to read 3, iclass 30, count 0 2006.175.07:20:17.13#ibcon#read 3, iclass 30, count 0 2006.175.07:20:17.13#ibcon#about to read 4, iclass 30, count 0 2006.175.07:20:17.13#ibcon#read 4, iclass 30, count 0 2006.175.07:20:17.13#ibcon#about to read 5, iclass 30, count 0 2006.175.07:20:17.13#ibcon#read 5, iclass 30, count 0 2006.175.07:20:17.13#ibcon#about to read 6, iclass 30, count 0 2006.175.07:20:17.13#ibcon#read 6, iclass 30, count 0 2006.175.07:20:17.13#ibcon#end of sib2, iclass 30, count 0 2006.175.07:20:17.13#ibcon#*after write, iclass 30, count 0 2006.175.07:20:17.13#ibcon#*before return 0, iclass 30, count 0 2006.175.07:20:17.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:17.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:17.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:20:17.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:20:17.14$vc4f8/va=2,7 2006.175.07:20:17.14#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.07:20:17.14#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.07:20:17.14#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:17.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:17.17#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:17.17#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:17.17#ibcon#enter wrdev, iclass 32, count 2 2006.175.07:20:17.17#ibcon#first serial, iclass 32, count 2 2006.175.07:20:17.17#ibcon#enter sib2, iclass 32, count 2 2006.175.07:20:17.17#ibcon#flushed, iclass 32, count 2 2006.175.07:20:17.17#ibcon#about to write, iclass 32, count 2 2006.175.07:20:17.17#ibcon#wrote, iclass 32, count 2 2006.175.07:20:17.17#ibcon#about to read 3, iclass 32, count 2 2006.175.07:20:17.19#ibcon#read 3, iclass 32, count 2 2006.175.07:20:17.19#ibcon#about to read 4, iclass 32, count 2 2006.175.07:20:17.19#ibcon#read 4, iclass 32, count 2 2006.175.07:20:17.19#ibcon#about to read 5, iclass 32, count 2 2006.175.07:20:17.19#ibcon#read 5, iclass 32, count 2 2006.175.07:20:17.19#ibcon#about to read 6, iclass 32, count 2 2006.175.07:20:17.19#ibcon#read 6, iclass 32, count 2 2006.175.07:20:17.19#ibcon#end of sib2, iclass 32, count 2 2006.175.07:20:17.19#ibcon#*mode == 0, iclass 32, count 2 2006.175.07:20:17.19#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.07:20:17.19#ibcon#[25=AT02-07\r\n] 2006.175.07:20:17.19#ibcon#*before write, iclass 32, count 2 2006.175.07:20:17.19#ibcon#enter sib2, iclass 32, count 2 2006.175.07:20:17.19#ibcon#flushed, iclass 32, count 2 2006.175.07:20:17.19#ibcon#about to write, iclass 32, count 2 2006.175.07:20:17.19#ibcon#wrote, iclass 32, count 2 2006.175.07:20:17.19#ibcon#about to read 3, iclass 32, count 2 2006.175.07:20:17.22#ibcon#read 3, iclass 32, count 2 2006.175.07:20:17.22#ibcon#about to read 4, iclass 32, count 2 2006.175.07:20:17.22#ibcon#read 4, iclass 32, count 2 2006.175.07:20:17.22#ibcon#about to read 5, iclass 32, count 2 2006.175.07:20:17.22#ibcon#read 5, iclass 32, count 2 2006.175.07:20:17.22#ibcon#about to read 6, iclass 32, count 2 2006.175.07:20:17.22#ibcon#read 6, iclass 32, count 2 2006.175.07:20:17.22#ibcon#end of sib2, iclass 32, count 2 2006.175.07:20:17.22#ibcon#*after write, iclass 32, count 2 2006.175.07:20:17.22#ibcon#*before return 0, iclass 32, count 2 2006.175.07:20:17.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:17.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:17.22#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.07:20:17.22#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:17.22#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:17.34#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:17.34#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:17.34#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:20:17.34#ibcon#first serial, iclass 32, count 0 2006.175.07:20:17.34#ibcon#enter sib2, iclass 32, count 0 2006.175.07:20:17.34#ibcon#flushed, iclass 32, count 0 2006.175.07:20:17.34#ibcon#about to write, iclass 32, count 0 2006.175.07:20:17.34#ibcon#wrote, iclass 32, count 0 2006.175.07:20:17.34#ibcon#about to read 3, iclass 32, count 0 2006.175.07:20:17.36#ibcon#read 3, iclass 32, count 0 2006.175.07:20:17.36#ibcon#about to read 4, iclass 32, count 0 2006.175.07:20:17.36#ibcon#read 4, iclass 32, count 0 2006.175.07:20:17.36#ibcon#about to read 5, iclass 32, count 0 2006.175.07:20:17.36#ibcon#read 5, iclass 32, count 0 2006.175.07:20:17.36#ibcon#about to read 6, iclass 32, count 0 2006.175.07:20:17.36#ibcon#read 6, iclass 32, count 0 2006.175.07:20:17.36#ibcon#end of sib2, iclass 32, count 0 2006.175.07:20:17.36#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:20:17.36#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:20:17.36#ibcon#[25=USB\r\n] 2006.175.07:20:17.36#ibcon#*before write, iclass 32, count 0 2006.175.07:20:17.36#ibcon#enter sib2, iclass 32, count 0 2006.175.07:20:17.36#ibcon#flushed, iclass 32, count 0 2006.175.07:20:17.36#ibcon#about to write, iclass 32, count 0 2006.175.07:20:17.36#ibcon#wrote, iclass 32, count 0 2006.175.07:20:17.36#ibcon#about to read 3, iclass 32, count 0 2006.175.07:20:17.39#ibcon#read 3, iclass 32, count 0 2006.175.07:20:17.39#ibcon#about to read 4, iclass 32, count 0 2006.175.07:20:17.39#ibcon#read 4, iclass 32, count 0 2006.175.07:20:17.39#ibcon#about to read 5, iclass 32, count 0 2006.175.07:20:17.39#ibcon#read 5, iclass 32, count 0 2006.175.07:20:17.39#ibcon#about to read 6, iclass 32, count 0 2006.175.07:20:17.39#ibcon#read 6, iclass 32, count 0 2006.175.07:20:17.39#ibcon#end of sib2, iclass 32, count 0 2006.175.07:20:17.39#ibcon#*after write, iclass 32, count 0 2006.175.07:20:17.39#ibcon#*before return 0, iclass 32, count 0 2006.175.07:20:17.39#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:17.39#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:17.39#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:20:17.39#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:20:17.40$vc4f8/valo=3,672.99 2006.175.07:20:17.40#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.07:20:17.40#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.07:20:17.40#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:17.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:17.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:17.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:17.40#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:20:17.40#ibcon#first serial, iclass 34, count 0 2006.175.07:20:17.40#ibcon#enter sib2, iclass 34, count 0 2006.175.07:20:17.40#ibcon#flushed, iclass 34, count 0 2006.175.07:20:17.40#ibcon#about to write, iclass 34, count 0 2006.175.07:20:17.40#ibcon#wrote, iclass 34, count 0 2006.175.07:20:17.40#ibcon#about to read 3, iclass 34, count 0 2006.175.07:20:17.41#ibcon#read 3, iclass 34, count 0 2006.175.07:20:17.41#ibcon#about to read 4, iclass 34, count 0 2006.175.07:20:17.41#ibcon#read 4, iclass 34, count 0 2006.175.07:20:17.41#ibcon#about to read 5, iclass 34, count 0 2006.175.07:20:17.41#ibcon#read 5, iclass 34, count 0 2006.175.07:20:17.41#ibcon#about to read 6, iclass 34, count 0 2006.175.07:20:17.41#ibcon#read 6, iclass 34, count 0 2006.175.07:20:17.41#ibcon#end of sib2, iclass 34, count 0 2006.175.07:20:17.41#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:20:17.41#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:20:17.41#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:20:17.41#ibcon#*before write, iclass 34, count 0 2006.175.07:20:17.41#ibcon#enter sib2, iclass 34, count 0 2006.175.07:20:17.41#ibcon#flushed, iclass 34, count 0 2006.175.07:20:17.41#ibcon#about to write, iclass 34, count 0 2006.175.07:20:17.41#ibcon#wrote, iclass 34, count 0 2006.175.07:20:17.41#ibcon#about to read 3, iclass 34, count 0 2006.175.07:20:17.45#ibcon#read 3, iclass 34, count 0 2006.175.07:20:17.45#ibcon#about to read 4, iclass 34, count 0 2006.175.07:20:17.45#ibcon#read 4, iclass 34, count 0 2006.175.07:20:17.45#ibcon#about to read 5, iclass 34, count 0 2006.175.07:20:17.45#ibcon#read 5, iclass 34, count 0 2006.175.07:20:17.45#ibcon#about to read 6, iclass 34, count 0 2006.175.07:20:17.45#ibcon#read 6, iclass 34, count 0 2006.175.07:20:17.45#ibcon#end of sib2, iclass 34, count 0 2006.175.07:20:17.45#ibcon#*after write, iclass 34, count 0 2006.175.07:20:17.45#ibcon#*before return 0, iclass 34, count 0 2006.175.07:20:17.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:17.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:17.45#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:20:17.45#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:20:17.46$vc4f8/va=3,6 2006.175.07:20:17.46#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.07:20:17.46#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.07:20:17.46#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:17.46#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:17.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:17.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:17.51#ibcon#enter wrdev, iclass 36, count 2 2006.175.07:20:17.51#ibcon#first serial, iclass 36, count 2 2006.175.07:20:17.51#ibcon#enter sib2, iclass 36, count 2 2006.175.07:20:17.51#ibcon#flushed, iclass 36, count 2 2006.175.07:20:17.51#ibcon#about to write, iclass 36, count 2 2006.175.07:20:17.51#ibcon#wrote, iclass 36, count 2 2006.175.07:20:17.51#ibcon#about to read 3, iclass 36, count 2 2006.175.07:20:17.52#ibcon#read 3, iclass 36, count 2 2006.175.07:20:17.52#ibcon#about to read 4, iclass 36, count 2 2006.175.07:20:17.52#ibcon#read 4, iclass 36, count 2 2006.175.07:20:17.52#ibcon#about to read 5, iclass 36, count 2 2006.175.07:20:17.52#ibcon#read 5, iclass 36, count 2 2006.175.07:20:17.52#ibcon#about to read 6, iclass 36, count 2 2006.175.07:20:17.52#ibcon#read 6, iclass 36, count 2 2006.175.07:20:17.52#ibcon#end of sib2, iclass 36, count 2 2006.175.07:20:17.52#ibcon#*mode == 0, iclass 36, count 2 2006.175.07:20:17.52#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.07:20:17.52#ibcon#[25=AT03-06\r\n] 2006.175.07:20:17.52#ibcon#*before write, iclass 36, count 2 2006.175.07:20:17.52#ibcon#enter sib2, iclass 36, count 2 2006.175.07:20:17.52#ibcon#flushed, iclass 36, count 2 2006.175.07:20:17.52#ibcon#about to write, iclass 36, count 2 2006.175.07:20:17.52#ibcon#wrote, iclass 36, count 2 2006.175.07:20:17.52#ibcon#about to read 3, iclass 36, count 2 2006.175.07:20:17.55#ibcon#read 3, iclass 36, count 2 2006.175.07:20:17.55#ibcon#about to read 4, iclass 36, count 2 2006.175.07:20:17.55#ibcon#read 4, iclass 36, count 2 2006.175.07:20:17.55#ibcon#about to read 5, iclass 36, count 2 2006.175.07:20:17.55#ibcon#read 5, iclass 36, count 2 2006.175.07:20:17.55#ibcon#about to read 6, iclass 36, count 2 2006.175.07:20:17.55#ibcon#read 6, iclass 36, count 2 2006.175.07:20:17.55#ibcon#end of sib2, iclass 36, count 2 2006.175.07:20:17.55#ibcon#*after write, iclass 36, count 2 2006.175.07:20:17.55#ibcon#*before return 0, iclass 36, count 2 2006.175.07:20:17.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:17.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:17.55#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.07:20:17.55#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:17.55#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:17.67#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:17.67#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:17.67#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:20:17.67#ibcon#first serial, iclass 36, count 0 2006.175.07:20:17.67#ibcon#enter sib2, iclass 36, count 0 2006.175.07:20:17.67#ibcon#flushed, iclass 36, count 0 2006.175.07:20:17.67#ibcon#about to write, iclass 36, count 0 2006.175.07:20:17.67#ibcon#wrote, iclass 36, count 0 2006.175.07:20:17.67#ibcon#about to read 3, iclass 36, count 0 2006.175.07:20:17.69#ibcon#read 3, iclass 36, count 0 2006.175.07:20:17.69#ibcon#about to read 4, iclass 36, count 0 2006.175.07:20:17.69#ibcon#read 4, iclass 36, count 0 2006.175.07:20:17.69#ibcon#about to read 5, iclass 36, count 0 2006.175.07:20:17.69#ibcon#read 5, iclass 36, count 0 2006.175.07:20:17.69#ibcon#about to read 6, iclass 36, count 0 2006.175.07:20:17.69#ibcon#read 6, iclass 36, count 0 2006.175.07:20:17.69#ibcon#end of sib2, iclass 36, count 0 2006.175.07:20:17.69#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:20:17.69#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:20:17.69#ibcon#[25=USB\r\n] 2006.175.07:20:17.69#ibcon#*before write, iclass 36, count 0 2006.175.07:20:17.69#ibcon#enter sib2, iclass 36, count 0 2006.175.07:20:17.69#ibcon#flushed, iclass 36, count 0 2006.175.07:20:17.69#ibcon#about to write, iclass 36, count 0 2006.175.07:20:17.69#ibcon#wrote, iclass 36, count 0 2006.175.07:20:17.69#ibcon#about to read 3, iclass 36, count 0 2006.175.07:20:17.72#ibcon#read 3, iclass 36, count 0 2006.175.07:20:17.72#ibcon#about to read 4, iclass 36, count 0 2006.175.07:20:17.72#ibcon#read 4, iclass 36, count 0 2006.175.07:20:17.72#ibcon#about to read 5, iclass 36, count 0 2006.175.07:20:17.72#ibcon#read 5, iclass 36, count 0 2006.175.07:20:17.72#ibcon#about to read 6, iclass 36, count 0 2006.175.07:20:17.72#ibcon#read 6, iclass 36, count 0 2006.175.07:20:17.72#ibcon#end of sib2, iclass 36, count 0 2006.175.07:20:17.72#ibcon#*after write, iclass 36, count 0 2006.175.07:20:17.72#ibcon#*before return 0, iclass 36, count 0 2006.175.07:20:17.72#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:17.72#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:17.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:20:17.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:20:17.73$vc4f8/valo=4,832.99 2006.175.07:20:17.73#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:20:17.73#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:20:17.73#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:17.73#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:17.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:17.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:17.73#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:20:17.73#ibcon#first serial, iclass 38, count 0 2006.175.07:20:17.73#ibcon#enter sib2, iclass 38, count 0 2006.175.07:20:17.73#ibcon#flushed, iclass 38, count 0 2006.175.07:20:17.73#ibcon#about to write, iclass 38, count 0 2006.175.07:20:17.73#ibcon#wrote, iclass 38, count 0 2006.175.07:20:17.73#ibcon#about to read 3, iclass 38, count 0 2006.175.07:20:17.74#ibcon#read 3, iclass 38, count 0 2006.175.07:20:17.74#ibcon#about to read 4, iclass 38, count 0 2006.175.07:20:17.74#ibcon#read 4, iclass 38, count 0 2006.175.07:20:17.74#ibcon#about to read 5, iclass 38, count 0 2006.175.07:20:17.74#ibcon#read 5, iclass 38, count 0 2006.175.07:20:17.74#ibcon#about to read 6, iclass 38, count 0 2006.175.07:20:17.74#ibcon#read 6, iclass 38, count 0 2006.175.07:20:17.74#ibcon#end of sib2, iclass 38, count 0 2006.175.07:20:17.74#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:20:17.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:20:17.74#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:20:17.74#ibcon#*before write, iclass 38, count 0 2006.175.07:20:17.74#ibcon#enter sib2, iclass 38, count 0 2006.175.07:20:17.74#ibcon#flushed, iclass 38, count 0 2006.175.07:20:17.74#ibcon#about to write, iclass 38, count 0 2006.175.07:20:17.74#ibcon#wrote, iclass 38, count 0 2006.175.07:20:17.74#ibcon#about to read 3, iclass 38, count 0 2006.175.07:20:17.78#ibcon#read 3, iclass 38, count 0 2006.175.07:20:17.78#ibcon#about to read 4, iclass 38, count 0 2006.175.07:20:17.78#ibcon#read 4, iclass 38, count 0 2006.175.07:20:17.78#ibcon#about to read 5, iclass 38, count 0 2006.175.07:20:17.78#ibcon#read 5, iclass 38, count 0 2006.175.07:20:17.78#ibcon#about to read 6, iclass 38, count 0 2006.175.07:20:17.78#ibcon#read 6, iclass 38, count 0 2006.175.07:20:17.78#ibcon#end of sib2, iclass 38, count 0 2006.175.07:20:17.78#ibcon#*after write, iclass 38, count 0 2006.175.07:20:17.78#ibcon#*before return 0, iclass 38, count 0 2006.175.07:20:17.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:17.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:17.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:20:17.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:20:17.79$vc4f8/va=4,7 2006.175.07:20:17.79#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.07:20:17.79#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.07:20:17.79#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:17.79#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:17.84#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:17.84#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:17.84#ibcon#enter wrdev, iclass 40, count 2 2006.175.07:20:17.84#ibcon#first serial, iclass 40, count 2 2006.175.07:20:17.84#ibcon#enter sib2, iclass 40, count 2 2006.175.07:20:17.84#ibcon#flushed, iclass 40, count 2 2006.175.07:20:17.84#ibcon#about to write, iclass 40, count 2 2006.175.07:20:17.84#ibcon#wrote, iclass 40, count 2 2006.175.07:20:17.84#ibcon#about to read 3, iclass 40, count 2 2006.175.07:20:17.85#ibcon#read 3, iclass 40, count 2 2006.175.07:20:17.85#ibcon#about to read 4, iclass 40, count 2 2006.175.07:20:17.85#ibcon#read 4, iclass 40, count 2 2006.175.07:20:17.85#ibcon#about to read 5, iclass 40, count 2 2006.175.07:20:17.85#ibcon#read 5, iclass 40, count 2 2006.175.07:20:17.85#ibcon#about to read 6, iclass 40, count 2 2006.175.07:20:17.85#ibcon#read 6, iclass 40, count 2 2006.175.07:20:17.85#ibcon#end of sib2, iclass 40, count 2 2006.175.07:20:17.85#ibcon#*mode == 0, iclass 40, count 2 2006.175.07:20:17.85#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.07:20:17.85#ibcon#[25=AT04-07\r\n] 2006.175.07:20:17.85#ibcon#*before write, iclass 40, count 2 2006.175.07:20:17.85#ibcon#enter sib2, iclass 40, count 2 2006.175.07:20:17.85#ibcon#flushed, iclass 40, count 2 2006.175.07:20:17.85#ibcon#about to write, iclass 40, count 2 2006.175.07:20:17.85#ibcon#wrote, iclass 40, count 2 2006.175.07:20:17.85#ibcon#about to read 3, iclass 40, count 2 2006.175.07:20:17.88#ibcon#read 3, iclass 40, count 2 2006.175.07:20:17.88#ibcon#about to read 4, iclass 40, count 2 2006.175.07:20:17.88#ibcon#read 4, iclass 40, count 2 2006.175.07:20:17.88#ibcon#about to read 5, iclass 40, count 2 2006.175.07:20:17.88#ibcon#read 5, iclass 40, count 2 2006.175.07:20:17.88#ibcon#about to read 6, iclass 40, count 2 2006.175.07:20:17.88#ibcon#read 6, iclass 40, count 2 2006.175.07:20:17.88#ibcon#end of sib2, iclass 40, count 2 2006.175.07:20:17.88#ibcon#*after write, iclass 40, count 2 2006.175.07:20:17.88#ibcon#*before return 0, iclass 40, count 2 2006.175.07:20:17.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:17.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:17.88#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.07:20:17.88#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:17.88#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:18.00#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:18.00#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:18.00#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:20:18.00#ibcon#first serial, iclass 40, count 0 2006.175.07:20:18.00#ibcon#enter sib2, iclass 40, count 0 2006.175.07:20:18.00#ibcon#flushed, iclass 40, count 0 2006.175.07:20:18.00#ibcon#about to write, iclass 40, count 0 2006.175.07:20:18.00#ibcon#wrote, iclass 40, count 0 2006.175.07:20:18.00#ibcon#about to read 3, iclass 40, count 0 2006.175.07:20:18.02#ibcon#read 3, iclass 40, count 0 2006.175.07:20:18.02#ibcon#about to read 4, iclass 40, count 0 2006.175.07:20:18.02#ibcon#read 4, iclass 40, count 0 2006.175.07:20:18.02#ibcon#about to read 5, iclass 40, count 0 2006.175.07:20:18.02#ibcon#read 5, iclass 40, count 0 2006.175.07:20:18.02#ibcon#about to read 6, iclass 40, count 0 2006.175.07:20:18.02#ibcon#read 6, iclass 40, count 0 2006.175.07:20:18.02#ibcon#end of sib2, iclass 40, count 0 2006.175.07:20:18.02#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:20:18.02#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:20:18.02#ibcon#[25=USB\r\n] 2006.175.07:20:18.02#ibcon#*before write, iclass 40, count 0 2006.175.07:20:18.02#ibcon#enter sib2, iclass 40, count 0 2006.175.07:20:18.02#ibcon#flushed, iclass 40, count 0 2006.175.07:20:18.02#ibcon#about to write, iclass 40, count 0 2006.175.07:20:18.02#ibcon#wrote, iclass 40, count 0 2006.175.07:20:18.02#ibcon#about to read 3, iclass 40, count 0 2006.175.07:20:18.05#ibcon#read 3, iclass 40, count 0 2006.175.07:20:18.05#ibcon#about to read 4, iclass 40, count 0 2006.175.07:20:18.05#ibcon#read 4, iclass 40, count 0 2006.175.07:20:18.05#ibcon#about to read 5, iclass 40, count 0 2006.175.07:20:18.05#ibcon#read 5, iclass 40, count 0 2006.175.07:20:18.05#ibcon#about to read 6, iclass 40, count 0 2006.175.07:20:18.05#ibcon#read 6, iclass 40, count 0 2006.175.07:20:18.05#ibcon#end of sib2, iclass 40, count 0 2006.175.07:20:18.05#ibcon#*after write, iclass 40, count 0 2006.175.07:20:18.05#ibcon#*before return 0, iclass 40, count 0 2006.175.07:20:18.05#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:18.05#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:18.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:20:18.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:20:18.05$vc4f8/valo=5,652.99 2006.175.07:20:18.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:20:18.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:20:18.05#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:18.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:18.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:18.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:18.05#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:20:18.06#ibcon#first serial, iclass 4, count 0 2006.175.07:20:18.06#ibcon#enter sib2, iclass 4, count 0 2006.175.07:20:18.06#ibcon#flushed, iclass 4, count 0 2006.175.07:20:18.06#ibcon#about to write, iclass 4, count 0 2006.175.07:20:18.06#ibcon#wrote, iclass 4, count 0 2006.175.07:20:18.06#ibcon#about to read 3, iclass 4, count 0 2006.175.07:20:18.07#ibcon#read 3, iclass 4, count 0 2006.175.07:20:18.07#ibcon#about to read 4, iclass 4, count 0 2006.175.07:20:18.07#ibcon#read 4, iclass 4, count 0 2006.175.07:20:18.07#ibcon#about to read 5, iclass 4, count 0 2006.175.07:20:18.07#ibcon#read 5, iclass 4, count 0 2006.175.07:20:18.07#ibcon#about to read 6, iclass 4, count 0 2006.175.07:20:18.07#ibcon#read 6, iclass 4, count 0 2006.175.07:20:18.07#ibcon#end of sib2, iclass 4, count 0 2006.175.07:20:18.07#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:20:18.07#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:20:18.07#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:20:18.07#ibcon#*before write, iclass 4, count 0 2006.175.07:20:18.07#ibcon#enter sib2, iclass 4, count 0 2006.175.07:20:18.07#ibcon#flushed, iclass 4, count 0 2006.175.07:20:18.07#ibcon#about to write, iclass 4, count 0 2006.175.07:20:18.07#ibcon#wrote, iclass 4, count 0 2006.175.07:20:18.07#ibcon#about to read 3, iclass 4, count 0 2006.175.07:20:18.11#ibcon#read 3, iclass 4, count 0 2006.175.07:20:18.11#ibcon#about to read 4, iclass 4, count 0 2006.175.07:20:18.11#ibcon#read 4, iclass 4, count 0 2006.175.07:20:18.11#ibcon#about to read 5, iclass 4, count 0 2006.175.07:20:18.11#ibcon#read 5, iclass 4, count 0 2006.175.07:20:18.11#ibcon#about to read 6, iclass 4, count 0 2006.175.07:20:18.11#ibcon#read 6, iclass 4, count 0 2006.175.07:20:18.11#ibcon#end of sib2, iclass 4, count 0 2006.175.07:20:18.11#ibcon#*after write, iclass 4, count 0 2006.175.07:20:18.11#ibcon#*before return 0, iclass 4, count 0 2006.175.07:20:18.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:18.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:18.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:20:18.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:20:18.11$vc4f8/va=5,7 2006.175.07:20:18.11#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.07:20:18.11#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.07:20:18.11#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:18.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:18.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:18.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:18.17#ibcon#enter wrdev, iclass 6, count 2 2006.175.07:20:18.17#ibcon#first serial, iclass 6, count 2 2006.175.07:20:18.17#ibcon#enter sib2, iclass 6, count 2 2006.175.07:20:18.17#ibcon#flushed, iclass 6, count 2 2006.175.07:20:18.17#ibcon#about to write, iclass 6, count 2 2006.175.07:20:18.17#ibcon#wrote, iclass 6, count 2 2006.175.07:20:18.17#ibcon#about to read 3, iclass 6, count 2 2006.175.07:20:18.19#ibcon#read 3, iclass 6, count 2 2006.175.07:20:18.19#ibcon#about to read 4, iclass 6, count 2 2006.175.07:20:18.19#ibcon#read 4, iclass 6, count 2 2006.175.07:20:18.19#ibcon#about to read 5, iclass 6, count 2 2006.175.07:20:18.19#ibcon#read 5, iclass 6, count 2 2006.175.07:20:18.19#ibcon#about to read 6, iclass 6, count 2 2006.175.07:20:18.19#ibcon#read 6, iclass 6, count 2 2006.175.07:20:18.19#ibcon#end of sib2, iclass 6, count 2 2006.175.07:20:18.19#ibcon#*mode == 0, iclass 6, count 2 2006.175.07:20:18.19#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.07:20:18.19#ibcon#[25=AT05-07\r\n] 2006.175.07:20:18.19#ibcon#*before write, iclass 6, count 2 2006.175.07:20:18.19#ibcon#enter sib2, iclass 6, count 2 2006.175.07:20:18.19#ibcon#flushed, iclass 6, count 2 2006.175.07:20:18.19#ibcon#about to write, iclass 6, count 2 2006.175.07:20:18.19#ibcon#wrote, iclass 6, count 2 2006.175.07:20:18.19#ibcon#about to read 3, iclass 6, count 2 2006.175.07:20:18.22#ibcon#read 3, iclass 6, count 2 2006.175.07:20:18.22#ibcon#about to read 4, iclass 6, count 2 2006.175.07:20:18.22#ibcon#read 4, iclass 6, count 2 2006.175.07:20:18.22#ibcon#about to read 5, iclass 6, count 2 2006.175.07:20:18.22#ibcon#read 5, iclass 6, count 2 2006.175.07:20:18.22#ibcon#about to read 6, iclass 6, count 2 2006.175.07:20:18.22#ibcon#read 6, iclass 6, count 2 2006.175.07:20:18.22#ibcon#end of sib2, iclass 6, count 2 2006.175.07:20:18.22#ibcon#*after write, iclass 6, count 2 2006.175.07:20:18.22#ibcon#*before return 0, iclass 6, count 2 2006.175.07:20:18.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:18.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:18.22#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.07:20:18.22#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:18.22#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:18.34#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:18.34#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:18.34#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:20:18.34#ibcon#first serial, iclass 6, count 0 2006.175.07:20:18.34#ibcon#enter sib2, iclass 6, count 0 2006.175.07:20:18.34#ibcon#flushed, iclass 6, count 0 2006.175.07:20:18.34#ibcon#about to write, iclass 6, count 0 2006.175.07:20:18.34#ibcon#wrote, iclass 6, count 0 2006.175.07:20:18.34#ibcon#about to read 3, iclass 6, count 0 2006.175.07:20:18.36#ibcon#read 3, iclass 6, count 0 2006.175.07:20:18.36#ibcon#about to read 4, iclass 6, count 0 2006.175.07:20:18.36#ibcon#read 4, iclass 6, count 0 2006.175.07:20:18.36#ibcon#about to read 5, iclass 6, count 0 2006.175.07:20:18.36#ibcon#read 5, iclass 6, count 0 2006.175.07:20:18.36#ibcon#about to read 6, iclass 6, count 0 2006.175.07:20:18.36#ibcon#read 6, iclass 6, count 0 2006.175.07:20:18.36#ibcon#end of sib2, iclass 6, count 0 2006.175.07:20:18.36#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:20:18.36#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:20:18.36#ibcon#[25=USB\r\n] 2006.175.07:20:18.36#ibcon#*before write, iclass 6, count 0 2006.175.07:20:18.36#ibcon#enter sib2, iclass 6, count 0 2006.175.07:20:18.36#ibcon#flushed, iclass 6, count 0 2006.175.07:20:18.36#ibcon#about to write, iclass 6, count 0 2006.175.07:20:18.36#ibcon#wrote, iclass 6, count 0 2006.175.07:20:18.36#ibcon#about to read 3, iclass 6, count 0 2006.175.07:20:18.39#ibcon#read 3, iclass 6, count 0 2006.175.07:20:18.39#ibcon#about to read 4, iclass 6, count 0 2006.175.07:20:18.39#ibcon#read 4, iclass 6, count 0 2006.175.07:20:18.39#ibcon#about to read 5, iclass 6, count 0 2006.175.07:20:18.39#ibcon#read 5, iclass 6, count 0 2006.175.07:20:18.39#ibcon#about to read 6, iclass 6, count 0 2006.175.07:20:18.39#ibcon#read 6, iclass 6, count 0 2006.175.07:20:18.39#ibcon#end of sib2, iclass 6, count 0 2006.175.07:20:18.39#ibcon#*after write, iclass 6, count 0 2006.175.07:20:18.39#ibcon#*before return 0, iclass 6, count 0 2006.175.07:20:18.39#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:18.39#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:18.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:20:18.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:20:18.39$vc4f8/valo=6,772.99 2006.175.07:20:18.39#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.07:20:18.39#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.07:20:18.39#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:18.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:18.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:18.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:18.39#ibcon#enter wrdev, iclass 10, count 0 2006.175.07:20:18.39#ibcon#first serial, iclass 10, count 0 2006.175.07:20:18.39#ibcon#enter sib2, iclass 10, count 0 2006.175.07:20:18.39#ibcon#flushed, iclass 10, count 0 2006.175.07:20:18.40#ibcon#about to write, iclass 10, count 0 2006.175.07:20:18.40#ibcon#wrote, iclass 10, count 0 2006.175.07:20:18.40#ibcon#about to read 3, iclass 10, count 0 2006.175.07:20:18.41#ibcon#read 3, iclass 10, count 0 2006.175.07:20:18.41#ibcon#about to read 4, iclass 10, count 0 2006.175.07:20:18.41#ibcon#read 4, iclass 10, count 0 2006.175.07:20:18.41#ibcon#about to read 5, iclass 10, count 0 2006.175.07:20:18.41#ibcon#read 5, iclass 10, count 0 2006.175.07:20:18.41#ibcon#about to read 6, iclass 10, count 0 2006.175.07:20:18.41#ibcon#read 6, iclass 10, count 0 2006.175.07:20:18.41#ibcon#end of sib2, iclass 10, count 0 2006.175.07:20:18.41#ibcon#*mode == 0, iclass 10, count 0 2006.175.07:20:18.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.07:20:18.41#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:20:18.41#ibcon#*before write, iclass 10, count 0 2006.175.07:20:18.41#ibcon#enter sib2, iclass 10, count 0 2006.175.07:20:18.41#ibcon#flushed, iclass 10, count 0 2006.175.07:20:18.41#ibcon#about to write, iclass 10, count 0 2006.175.07:20:18.41#ibcon#wrote, iclass 10, count 0 2006.175.07:20:18.41#ibcon#about to read 3, iclass 10, count 0 2006.175.07:20:18.45#ibcon#read 3, iclass 10, count 0 2006.175.07:20:18.45#ibcon#about to read 4, iclass 10, count 0 2006.175.07:20:18.45#ibcon#read 4, iclass 10, count 0 2006.175.07:20:18.45#ibcon#about to read 5, iclass 10, count 0 2006.175.07:20:18.45#ibcon#read 5, iclass 10, count 0 2006.175.07:20:18.45#ibcon#about to read 6, iclass 10, count 0 2006.175.07:20:18.45#ibcon#read 6, iclass 10, count 0 2006.175.07:20:18.45#ibcon#end of sib2, iclass 10, count 0 2006.175.07:20:18.45#ibcon#*after write, iclass 10, count 0 2006.175.07:20:18.45#ibcon#*before return 0, iclass 10, count 0 2006.175.07:20:18.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:18.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:18.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.07:20:18.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.07:20:18.45$vc4f8/va=6,6 2006.175.07:20:18.45#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.07:20:18.45#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.07:20:18.45#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:18.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:18.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:18.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:18.51#ibcon#enter wrdev, iclass 12, count 2 2006.175.07:20:18.51#ibcon#first serial, iclass 12, count 2 2006.175.07:20:18.51#ibcon#enter sib2, iclass 12, count 2 2006.175.07:20:18.51#ibcon#flushed, iclass 12, count 2 2006.175.07:20:18.51#ibcon#about to write, iclass 12, count 2 2006.175.07:20:18.51#ibcon#wrote, iclass 12, count 2 2006.175.07:20:18.51#ibcon#about to read 3, iclass 12, count 2 2006.175.07:20:18.53#ibcon#read 3, iclass 12, count 2 2006.175.07:20:18.53#ibcon#about to read 4, iclass 12, count 2 2006.175.07:20:18.53#ibcon#read 4, iclass 12, count 2 2006.175.07:20:18.53#ibcon#about to read 5, iclass 12, count 2 2006.175.07:20:18.53#ibcon#read 5, iclass 12, count 2 2006.175.07:20:18.53#ibcon#about to read 6, iclass 12, count 2 2006.175.07:20:18.53#ibcon#read 6, iclass 12, count 2 2006.175.07:20:18.53#ibcon#end of sib2, iclass 12, count 2 2006.175.07:20:18.53#ibcon#*mode == 0, iclass 12, count 2 2006.175.07:20:18.53#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.07:20:18.53#ibcon#[25=AT06-06\r\n] 2006.175.07:20:18.53#ibcon#*before write, iclass 12, count 2 2006.175.07:20:18.53#ibcon#enter sib2, iclass 12, count 2 2006.175.07:20:18.53#ibcon#flushed, iclass 12, count 2 2006.175.07:20:18.53#ibcon#about to write, iclass 12, count 2 2006.175.07:20:18.53#ibcon#wrote, iclass 12, count 2 2006.175.07:20:18.53#ibcon#about to read 3, iclass 12, count 2 2006.175.07:20:18.56#ibcon#read 3, iclass 12, count 2 2006.175.07:20:18.56#ibcon#about to read 4, iclass 12, count 2 2006.175.07:20:18.56#ibcon#read 4, iclass 12, count 2 2006.175.07:20:18.56#ibcon#about to read 5, iclass 12, count 2 2006.175.07:20:18.56#ibcon#read 5, iclass 12, count 2 2006.175.07:20:18.56#ibcon#about to read 6, iclass 12, count 2 2006.175.07:20:18.56#ibcon#read 6, iclass 12, count 2 2006.175.07:20:18.56#ibcon#end of sib2, iclass 12, count 2 2006.175.07:20:18.56#ibcon#*after write, iclass 12, count 2 2006.175.07:20:18.56#ibcon#*before return 0, iclass 12, count 2 2006.175.07:20:18.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:18.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:18.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.07:20:18.56#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:18.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:18.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:18.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:18.68#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:20:18.68#ibcon#first serial, iclass 12, count 0 2006.175.07:20:18.68#ibcon#enter sib2, iclass 12, count 0 2006.175.07:20:18.68#ibcon#flushed, iclass 12, count 0 2006.175.07:20:18.68#ibcon#about to write, iclass 12, count 0 2006.175.07:20:18.68#ibcon#wrote, iclass 12, count 0 2006.175.07:20:18.68#ibcon#about to read 3, iclass 12, count 0 2006.175.07:20:18.70#ibcon#read 3, iclass 12, count 0 2006.175.07:20:18.70#ibcon#about to read 4, iclass 12, count 0 2006.175.07:20:18.70#ibcon#read 4, iclass 12, count 0 2006.175.07:20:18.70#ibcon#about to read 5, iclass 12, count 0 2006.175.07:20:18.70#ibcon#read 5, iclass 12, count 0 2006.175.07:20:18.70#ibcon#about to read 6, iclass 12, count 0 2006.175.07:20:18.70#ibcon#read 6, iclass 12, count 0 2006.175.07:20:18.70#ibcon#end of sib2, iclass 12, count 0 2006.175.07:20:18.70#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:20:18.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:20:18.70#ibcon#[25=USB\r\n] 2006.175.07:20:18.70#ibcon#*before write, iclass 12, count 0 2006.175.07:20:18.70#ibcon#enter sib2, iclass 12, count 0 2006.175.07:20:18.70#ibcon#flushed, iclass 12, count 0 2006.175.07:20:18.70#ibcon#about to write, iclass 12, count 0 2006.175.07:20:18.70#ibcon#wrote, iclass 12, count 0 2006.175.07:20:18.70#ibcon#about to read 3, iclass 12, count 0 2006.175.07:20:18.73#ibcon#read 3, iclass 12, count 0 2006.175.07:20:18.73#ibcon#about to read 4, iclass 12, count 0 2006.175.07:20:18.73#ibcon#read 4, iclass 12, count 0 2006.175.07:20:18.73#ibcon#about to read 5, iclass 12, count 0 2006.175.07:20:18.73#ibcon#read 5, iclass 12, count 0 2006.175.07:20:18.73#ibcon#about to read 6, iclass 12, count 0 2006.175.07:20:18.73#ibcon#read 6, iclass 12, count 0 2006.175.07:20:18.73#ibcon#end of sib2, iclass 12, count 0 2006.175.07:20:18.73#ibcon#*after write, iclass 12, count 0 2006.175.07:20:18.73#ibcon#*before return 0, iclass 12, count 0 2006.175.07:20:18.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:18.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:18.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:20:18.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:20:18.73$vc4f8/valo=7,832.99 2006.175.07:20:18.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.07:20:18.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.07:20:18.73#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:18.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:18.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:18.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:18.73#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:20:18.73#ibcon#first serial, iclass 14, count 0 2006.175.07:20:18.73#ibcon#enter sib2, iclass 14, count 0 2006.175.07:20:18.73#ibcon#flushed, iclass 14, count 0 2006.175.07:20:18.73#ibcon#about to write, iclass 14, count 0 2006.175.07:20:18.74#ibcon#wrote, iclass 14, count 0 2006.175.07:20:18.74#ibcon#about to read 3, iclass 14, count 0 2006.175.07:20:18.75#ibcon#read 3, iclass 14, count 0 2006.175.07:20:18.75#ibcon#about to read 4, iclass 14, count 0 2006.175.07:20:18.75#ibcon#read 4, iclass 14, count 0 2006.175.07:20:18.75#ibcon#about to read 5, iclass 14, count 0 2006.175.07:20:18.75#ibcon#read 5, iclass 14, count 0 2006.175.07:20:18.75#ibcon#about to read 6, iclass 14, count 0 2006.175.07:20:18.75#ibcon#read 6, iclass 14, count 0 2006.175.07:20:18.75#ibcon#end of sib2, iclass 14, count 0 2006.175.07:20:18.75#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:20:18.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:20:18.75#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:20:18.75#ibcon#*before write, iclass 14, count 0 2006.175.07:20:18.75#ibcon#enter sib2, iclass 14, count 0 2006.175.07:20:18.75#ibcon#flushed, iclass 14, count 0 2006.175.07:20:18.75#ibcon#about to write, iclass 14, count 0 2006.175.07:20:18.75#ibcon#wrote, iclass 14, count 0 2006.175.07:20:18.75#ibcon#about to read 3, iclass 14, count 0 2006.175.07:20:18.79#ibcon#read 3, iclass 14, count 0 2006.175.07:20:18.79#ibcon#about to read 4, iclass 14, count 0 2006.175.07:20:18.79#ibcon#read 4, iclass 14, count 0 2006.175.07:20:18.79#ibcon#about to read 5, iclass 14, count 0 2006.175.07:20:18.79#ibcon#read 5, iclass 14, count 0 2006.175.07:20:18.79#ibcon#about to read 6, iclass 14, count 0 2006.175.07:20:18.79#ibcon#read 6, iclass 14, count 0 2006.175.07:20:18.79#ibcon#end of sib2, iclass 14, count 0 2006.175.07:20:18.79#ibcon#*after write, iclass 14, count 0 2006.175.07:20:18.79#ibcon#*before return 0, iclass 14, count 0 2006.175.07:20:18.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:18.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:18.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:20:18.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:20:18.79$vc4f8/va=7,6 2006.175.07:20:18.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.07:20:18.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.07:20:18.79#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:18.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:20:18.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:20:18.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:20:18.85#ibcon#enter wrdev, iclass 16, count 2 2006.175.07:20:18.85#ibcon#first serial, iclass 16, count 2 2006.175.07:20:18.85#ibcon#enter sib2, iclass 16, count 2 2006.175.07:20:18.85#ibcon#flushed, iclass 16, count 2 2006.175.07:20:18.85#ibcon#about to write, iclass 16, count 2 2006.175.07:20:18.85#ibcon#wrote, iclass 16, count 2 2006.175.07:20:18.85#ibcon#about to read 3, iclass 16, count 2 2006.175.07:20:18.87#ibcon#read 3, iclass 16, count 2 2006.175.07:20:18.87#ibcon#about to read 4, iclass 16, count 2 2006.175.07:20:18.87#ibcon#read 4, iclass 16, count 2 2006.175.07:20:18.87#ibcon#about to read 5, iclass 16, count 2 2006.175.07:20:18.87#ibcon#read 5, iclass 16, count 2 2006.175.07:20:18.87#ibcon#about to read 6, iclass 16, count 2 2006.175.07:20:18.87#ibcon#read 6, iclass 16, count 2 2006.175.07:20:18.87#ibcon#end of sib2, iclass 16, count 2 2006.175.07:20:18.87#ibcon#*mode == 0, iclass 16, count 2 2006.175.07:20:18.87#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.07:20:18.87#ibcon#[25=AT07-06\r\n] 2006.175.07:20:18.87#ibcon#*before write, iclass 16, count 2 2006.175.07:20:18.87#ibcon#enter sib2, iclass 16, count 2 2006.175.07:20:18.87#ibcon#flushed, iclass 16, count 2 2006.175.07:20:18.87#ibcon#about to write, iclass 16, count 2 2006.175.07:20:18.87#ibcon#wrote, iclass 16, count 2 2006.175.07:20:18.87#ibcon#about to read 3, iclass 16, count 2 2006.175.07:20:18.90#ibcon#read 3, iclass 16, count 2 2006.175.07:20:18.90#ibcon#about to read 4, iclass 16, count 2 2006.175.07:20:18.90#ibcon#read 4, iclass 16, count 2 2006.175.07:20:18.90#ibcon#about to read 5, iclass 16, count 2 2006.175.07:20:18.90#ibcon#read 5, iclass 16, count 2 2006.175.07:20:18.90#ibcon#about to read 6, iclass 16, count 2 2006.175.07:20:18.90#ibcon#read 6, iclass 16, count 2 2006.175.07:20:18.90#ibcon#end of sib2, iclass 16, count 2 2006.175.07:20:18.90#ibcon#*after write, iclass 16, count 2 2006.175.07:20:18.90#ibcon#*before return 0, iclass 16, count 2 2006.175.07:20:18.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:20:18.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:20:18.90#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.07:20:18.90#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:18.90#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:20:19.03#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:20:19.03#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:20:19.03#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:20:19.03#ibcon#first serial, iclass 16, count 0 2006.175.07:20:19.03#ibcon#enter sib2, iclass 16, count 0 2006.175.07:20:19.03#ibcon#flushed, iclass 16, count 0 2006.175.07:20:19.03#ibcon#about to write, iclass 16, count 0 2006.175.07:20:19.03#ibcon#wrote, iclass 16, count 0 2006.175.07:20:19.03#ibcon#about to read 3, iclass 16, count 0 2006.175.07:20:19.05#abcon#<5=/05 4.5 7.5 26.17 701007.3\r\n> 2006.175.07:20:19.05#ibcon#read 3, iclass 16, count 0 2006.175.07:20:19.05#ibcon#about to read 4, iclass 16, count 0 2006.175.07:20:19.05#ibcon#read 4, iclass 16, count 0 2006.175.07:20:19.05#ibcon#about to read 5, iclass 16, count 0 2006.175.07:20:19.05#ibcon#read 5, iclass 16, count 0 2006.175.07:20:19.05#ibcon#about to read 6, iclass 16, count 0 2006.175.07:20:19.05#ibcon#read 6, iclass 16, count 0 2006.175.07:20:19.05#ibcon#end of sib2, iclass 16, count 0 2006.175.07:20:19.05#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:20:19.05#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:20:19.05#ibcon#[25=USB\r\n] 2006.175.07:20:19.05#ibcon#*before write, iclass 16, count 0 2006.175.07:20:19.05#ibcon#enter sib2, iclass 16, count 0 2006.175.07:20:19.05#ibcon#flushed, iclass 16, count 0 2006.175.07:20:19.05#ibcon#about to write, iclass 16, count 0 2006.175.07:20:19.05#ibcon#wrote, iclass 16, count 0 2006.175.07:20:19.05#ibcon#about to read 3, iclass 16, count 0 2006.175.07:20:19.06#abcon#{5=INTERFACE CLEAR} 2006.175.07:20:19.07#ibcon#read 3, iclass 16, count 0 2006.175.07:20:19.07#ibcon#about to read 4, iclass 16, count 0 2006.175.07:20:19.07#ibcon#read 4, iclass 16, count 0 2006.175.07:20:19.07#ibcon#about to read 5, iclass 16, count 0 2006.175.07:20:19.07#ibcon#read 5, iclass 16, count 0 2006.175.07:20:19.07#ibcon#about to read 6, iclass 16, count 0 2006.175.07:20:19.07#ibcon#read 6, iclass 16, count 0 2006.175.07:20:19.07#ibcon#end of sib2, iclass 16, count 0 2006.175.07:20:19.07#ibcon#*after write, iclass 16, count 0 2006.175.07:20:19.07#ibcon#*before return 0, iclass 16, count 0 2006.175.07:20:19.07#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:20:19.07#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:20:19.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:20:19.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:20:19.07$vc4f8/valo=8,852.99 2006.175.07:20:19.07#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.07:20:19.07#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.07:20:19.07#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:19.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:20:19.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:20:19.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:20:19.07#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:20:19.07#ibcon#first serial, iclass 21, count 0 2006.175.07:20:19.07#ibcon#enter sib2, iclass 21, count 0 2006.175.07:20:19.07#ibcon#flushed, iclass 21, count 0 2006.175.07:20:19.07#ibcon#about to write, iclass 21, count 0 2006.175.07:20:19.08#ibcon#wrote, iclass 21, count 0 2006.175.07:20:19.08#ibcon#about to read 3, iclass 21, count 0 2006.175.07:20:19.09#ibcon#read 3, iclass 21, count 0 2006.175.07:20:19.09#ibcon#about to read 4, iclass 21, count 0 2006.175.07:20:19.09#ibcon#read 4, iclass 21, count 0 2006.175.07:20:19.09#ibcon#about to read 5, iclass 21, count 0 2006.175.07:20:19.09#ibcon#read 5, iclass 21, count 0 2006.175.07:20:19.09#ibcon#about to read 6, iclass 21, count 0 2006.175.07:20:19.09#ibcon#read 6, iclass 21, count 0 2006.175.07:20:19.10#ibcon#end of sib2, iclass 21, count 0 2006.175.07:20:19.10#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:20:19.10#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:20:19.10#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:20:19.10#ibcon#*before write, iclass 21, count 0 2006.175.07:20:19.10#ibcon#enter sib2, iclass 21, count 0 2006.175.07:20:19.10#ibcon#flushed, iclass 21, count 0 2006.175.07:20:19.10#ibcon#about to write, iclass 21, count 0 2006.175.07:20:19.10#ibcon#wrote, iclass 21, count 0 2006.175.07:20:19.10#ibcon#about to read 3, iclass 21, count 0 2006.175.07:20:19.12#abcon#[5=S1D000X0/0*\r\n] 2006.175.07:20:19.13#ibcon#read 3, iclass 21, count 0 2006.175.07:20:19.13#ibcon#about to read 4, iclass 21, count 0 2006.175.07:20:19.13#ibcon#read 4, iclass 21, count 0 2006.175.07:20:19.13#ibcon#about to read 5, iclass 21, count 0 2006.175.07:20:19.13#ibcon#read 5, iclass 21, count 0 2006.175.07:20:19.13#ibcon#about to read 6, iclass 21, count 0 2006.175.07:20:19.13#ibcon#read 6, iclass 21, count 0 2006.175.07:20:19.13#ibcon#end of sib2, iclass 21, count 0 2006.175.07:20:19.13#ibcon#*after write, iclass 21, count 0 2006.175.07:20:19.13#ibcon#*before return 0, iclass 21, count 0 2006.175.07:20:19.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:20:19.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:20:19.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:20:19.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:20:19.13$vc4f8/va=8,6 2006.175.07:20:19.13#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.07:20:19.13#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.07:20:19.13#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:19.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:20:19.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:20:19.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:20:19.19#ibcon#enter wrdev, iclass 24, count 2 2006.175.07:20:19.19#ibcon#first serial, iclass 24, count 2 2006.175.07:20:19.19#ibcon#enter sib2, iclass 24, count 2 2006.175.07:20:19.19#ibcon#flushed, iclass 24, count 2 2006.175.07:20:19.19#ibcon#about to write, iclass 24, count 2 2006.175.07:20:19.19#ibcon#wrote, iclass 24, count 2 2006.175.07:20:19.19#ibcon#about to read 3, iclass 24, count 2 2006.175.07:20:19.21#ibcon#read 3, iclass 24, count 2 2006.175.07:20:19.21#ibcon#about to read 4, iclass 24, count 2 2006.175.07:20:19.21#ibcon#read 4, iclass 24, count 2 2006.175.07:20:19.21#ibcon#about to read 5, iclass 24, count 2 2006.175.07:20:19.21#ibcon#read 5, iclass 24, count 2 2006.175.07:20:19.21#ibcon#about to read 6, iclass 24, count 2 2006.175.07:20:19.21#ibcon#read 6, iclass 24, count 2 2006.175.07:20:19.21#ibcon#end of sib2, iclass 24, count 2 2006.175.07:20:19.21#ibcon#*mode == 0, iclass 24, count 2 2006.175.07:20:19.21#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.07:20:19.21#ibcon#[25=AT08-06\r\n] 2006.175.07:20:19.21#ibcon#*before write, iclass 24, count 2 2006.175.07:20:19.21#ibcon#enter sib2, iclass 24, count 2 2006.175.07:20:19.21#ibcon#flushed, iclass 24, count 2 2006.175.07:20:19.21#ibcon#about to write, iclass 24, count 2 2006.175.07:20:19.21#ibcon#wrote, iclass 24, count 2 2006.175.07:20:19.21#ibcon#about to read 3, iclass 24, count 2 2006.175.07:20:19.24#ibcon#read 3, iclass 24, count 2 2006.175.07:20:19.24#ibcon#about to read 4, iclass 24, count 2 2006.175.07:20:19.24#ibcon#read 4, iclass 24, count 2 2006.175.07:20:19.24#ibcon#about to read 5, iclass 24, count 2 2006.175.07:20:19.24#ibcon#read 5, iclass 24, count 2 2006.175.07:20:19.24#ibcon#about to read 6, iclass 24, count 2 2006.175.07:20:19.24#ibcon#read 6, iclass 24, count 2 2006.175.07:20:19.24#ibcon#end of sib2, iclass 24, count 2 2006.175.07:20:19.24#ibcon#*after write, iclass 24, count 2 2006.175.07:20:19.24#ibcon#*before return 0, iclass 24, count 2 2006.175.07:20:19.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:20:19.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:20:19.24#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.07:20:19.24#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:19.24#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:20:19.36#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:20:19.36#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:20:19.36#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:20:19.36#ibcon#first serial, iclass 24, count 0 2006.175.07:20:19.36#ibcon#enter sib2, iclass 24, count 0 2006.175.07:20:19.36#ibcon#flushed, iclass 24, count 0 2006.175.07:20:19.36#ibcon#about to write, iclass 24, count 0 2006.175.07:20:19.36#ibcon#wrote, iclass 24, count 0 2006.175.07:20:19.36#ibcon#about to read 3, iclass 24, count 0 2006.175.07:20:19.38#ibcon#read 3, iclass 24, count 0 2006.175.07:20:19.38#ibcon#about to read 4, iclass 24, count 0 2006.175.07:20:19.38#ibcon#read 4, iclass 24, count 0 2006.175.07:20:19.38#ibcon#about to read 5, iclass 24, count 0 2006.175.07:20:19.38#ibcon#read 5, iclass 24, count 0 2006.175.07:20:19.38#ibcon#about to read 6, iclass 24, count 0 2006.175.07:20:19.38#ibcon#read 6, iclass 24, count 0 2006.175.07:20:19.38#ibcon#end of sib2, iclass 24, count 0 2006.175.07:20:19.38#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:20:19.38#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:20:19.38#ibcon#[25=USB\r\n] 2006.175.07:20:19.38#ibcon#*before write, iclass 24, count 0 2006.175.07:20:19.38#ibcon#enter sib2, iclass 24, count 0 2006.175.07:20:19.38#ibcon#flushed, iclass 24, count 0 2006.175.07:20:19.38#ibcon#about to write, iclass 24, count 0 2006.175.07:20:19.38#ibcon#wrote, iclass 24, count 0 2006.175.07:20:19.38#ibcon#about to read 3, iclass 24, count 0 2006.175.07:20:19.41#ibcon#read 3, iclass 24, count 0 2006.175.07:20:19.41#ibcon#about to read 4, iclass 24, count 0 2006.175.07:20:19.41#ibcon#read 4, iclass 24, count 0 2006.175.07:20:19.41#ibcon#about to read 5, iclass 24, count 0 2006.175.07:20:19.41#ibcon#read 5, iclass 24, count 0 2006.175.07:20:19.41#ibcon#about to read 6, iclass 24, count 0 2006.175.07:20:19.41#ibcon#read 6, iclass 24, count 0 2006.175.07:20:19.41#ibcon#end of sib2, iclass 24, count 0 2006.175.07:20:19.41#ibcon#*after write, iclass 24, count 0 2006.175.07:20:19.41#ibcon#*before return 0, iclass 24, count 0 2006.175.07:20:19.41#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:20:19.41#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:20:19.41#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:20:19.41#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:20:19.41$vc4f8/vblo=1,632.99 2006.175.07:20:19.41#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.07:20:19.41#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.07:20:19.41#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:19.41#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:19.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:19.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:19.41#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:20:19.41#ibcon#first serial, iclass 26, count 0 2006.175.07:20:19.41#ibcon#enter sib2, iclass 26, count 0 2006.175.07:20:19.41#ibcon#flushed, iclass 26, count 0 2006.175.07:20:19.41#ibcon#about to write, iclass 26, count 0 2006.175.07:20:19.42#ibcon#wrote, iclass 26, count 0 2006.175.07:20:19.42#ibcon#about to read 3, iclass 26, count 0 2006.175.07:20:19.43#ibcon#read 3, iclass 26, count 0 2006.175.07:20:19.43#ibcon#about to read 4, iclass 26, count 0 2006.175.07:20:19.43#ibcon#read 4, iclass 26, count 0 2006.175.07:20:19.43#ibcon#about to read 5, iclass 26, count 0 2006.175.07:20:19.43#ibcon#read 5, iclass 26, count 0 2006.175.07:20:19.43#ibcon#about to read 6, iclass 26, count 0 2006.175.07:20:19.43#ibcon#read 6, iclass 26, count 0 2006.175.07:20:19.43#ibcon#end of sib2, iclass 26, count 0 2006.175.07:20:19.43#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:20:19.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:20:19.43#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:20:19.43#ibcon#*before write, iclass 26, count 0 2006.175.07:20:19.43#ibcon#enter sib2, iclass 26, count 0 2006.175.07:20:19.43#ibcon#flushed, iclass 26, count 0 2006.175.07:20:19.43#ibcon#about to write, iclass 26, count 0 2006.175.07:20:19.43#ibcon#wrote, iclass 26, count 0 2006.175.07:20:19.43#ibcon#about to read 3, iclass 26, count 0 2006.175.07:20:19.49#ibcon#read 3, iclass 26, count 0 2006.175.07:20:19.49#ibcon#about to read 4, iclass 26, count 0 2006.175.07:20:19.49#ibcon#read 4, iclass 26, count 0 2006.175.07:20:19.49#ibcon#about to read 5, iclass 26, count 0 2006.175.07:20:19.49#ibcon#read 5, iclass 26, count 0 2006.175.07:20:19.49#ibcon#about to read 6, iclass 26, count 0 2006.175.07:20:19.49#ibcon#read 6, iclass 26, count 0 2006.175.07:20:19.49#ibcon#end of sib2, iclass 26, count 0 2006.175.07:20:19.49#ibcon#*after write, iclass 26, count 0 2006.175.07:20:19.49#ibcon#*before return 0, iclass 26, count 0 2006.175.07:20:19.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:19.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:20:19.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:20:19.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:20:19.49$vc4f8/vb=1,4 2006.175.07:20:19.49#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.07:20:19.49#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.07:20:19.49#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:19.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:19.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:19.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:19.49#ibcon#enter wrdev, iclass 28, count 2 2006.175.07:20:19.49#ibcon#first serial, iclass 28, count 2 2006.175.07:20:19.49#ibcon#enter sib2, iclass 28, count 2 2006.175.07:20:19.49#ibcon#flushed, iclass 28, count 2 2006.175.07:20:19.49#ibcon#about to write, iclass 28, count 2 2006.175.07:20:19.49#ibcon#wrote, iclass 28, count 2 2006.175.07:20:19.50#ibcon#about to read 3, iclass 28, count 2 2006.175.07:20:19.51#ibcon#read 3, iclass 28, count 2 2006.175.07:20:19.51#ibcon#about to read 4, iclass 28, count 2 2006.175.07:20:19.51#ibcon#read 4, iclass 28, count 2 2006.175.07:20:19.51#ibcon#about to read 5, iclass 28, count 2 2006.175.07:20:19.51#ibcon#read 5, iclass 28, count 2 2006.175.07:20:19.51#ibcon#about to read 6, iclass 28, count 2 2006.175.07:20:19.51#ibcon#read 6, iclass 28, count 2 2006.175.07:20:19.51#ibcon#end of sib2, iclass 28, count 2 2006.175.07:20:19.51#ibcon#*mode == 0, iclass 28, count 2 2006.175.07:20:19.51#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.07:20:19.51#ibcon#[27=AT01-04\r\n] 2006.175.07:20:19.51#ibcon#*before write, iclass 28, count 2 2006.175.07:20:19.51#ibcon#enter sib2, iclass 28, count 2 2006.175.07:20:19.51#ibcon#flushed, iclass 28, count 2 2006.175.07:20:19.51#ibcon#about to write, iclass 28, count 2 2006.175.07:20:19.51#ibcon#wrote, iclass 28, count 2 2006.175.07:20:19.51#ibcon#about to read 3, iclass 28, count 2 2006.175.07:20:19.55#ibcon#read 3, iclass 28, count 2 2006.175.07:20:19.55#ibcon#about to read 4, iclass 28, count 2 2006.175.07:20:19.55#ibcon#read 4, iclass 28, count 2 2006.175.07:20:19.55#ibcon#about to read 5, iclass 28, count 2 2006.175.07:20:19.55#ibcon#read 5, iclass 28, count 2 2006.175.07:20:19.55#ibcon#about to read 6, iclass 28, count 2 2006.175.07:20:19.55#ibcon#read 6, iclass 28, count 2 2006.175.07:20:19.55#ibcon#end of sib2, iclass 28, count 2 2006.175.07:20:19.55#ibcon#*after write, iclass 28, count 2 2006.175.07:20:19.55#ibcon#*before return 0, iclass 28, count 2 2006.175.07:20:19.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:19.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:20:19.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.07:20:19.55#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:19.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:19.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:19.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:19.67#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:20:19.67#ibcon#first serial, iclass 28, count 0 2006.175.07:20:19.67#ibcon#enter sib2, iclass 28, count 0 2006.175.07:20:19.67#ibcon#flushed, iclass 28, count 0 2006.175.07:20:19.67#ibcon#about to write, iclass 28, count 0 2006.175.07:20:19.67#ibcon#wrote, iclass 28, count 0 2006.175.07:20:19.67#ibcon#about to read 3, iclass 28, count 0 2006.175.07:20:19.69#ibcon#read 3, iclass 28, count 0 2006.175.07:20:19.69#ibcon#about to read 4, iclass 28, count 0 2006.175.07:20:19.69#ibcon#read 4, iclass 28, count 0 2006.175.07:20:19.69#ibcon#about to read 5, iclass 28, count 0 2006.175.07:20:19.69#ibcon#read 5, iclass 28, count 0 2006.175.07:20:19.69#ibcon#about to read 6, iclass 28, count 0 2006.175.07:20:19.69#ibcon#read 6, iclass 28, count 0 2006.175.07:20:19.69#ibcon#end of sib2, iclass 28, count 0 2006.175.07:20:19.69#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:20:19.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:20:19.69#ibcon#[27=USB\r\n] 2006.175.07:20:19.69#ibcon#*before write, iclass 28, count 0 2006.175.07:20:19.69#ibcon#enter sib2, iclass 28, count 0 2006.175.07:20:19.69#ibcon#flushed, iclass 28, count 0 2006.175.07:20:19.69#ibcon#about to write, iclass 28, count 0 2006.175.07:20:19.69#ibcon#wrote, iclass 28, count 0 2006.175.07:20:19.69#ibcon#about to read 3, iclass 28, count 0 2006.175.07:20:19.72#ibcon#read 3, iclass 28, count 0 2006.175.07:20:19.72#ibcon#about to read 4, iclass 28, count 0 2006.175.07:20:19.72#ibcon#read 4, iclass 28, count 0 2006.175.07:20:19.72#ibcon#about to read 5, iclass 28, count 0 2006.175.07:20:19.72#ibcon#read 5, iclass 28, count 0 2006.175.07:20:19.72#ibcon#about to read 6, iclass 28, count 0 2006.175.07:20:19.72#ibcon#read 6, iclass 28, count 0 2006.175.07:20:19.72#ibcon#end of sib2, iclass 28, count 0 2006.175.07:20:19.72#ibcon#*after write, iclass 28, count 0 2006.175.07:20:19.72#ibcon#*before return 0, iclass 28, count 0 2006.175.07:20:19.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:19.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:20:19.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:20:19.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:20:19.72$vc4f8/vblo=2,640.99 2006.175.07:20:19.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.07:20:19.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.07:20:19.72#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:19.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:19.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:19.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:19.72#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:20:19.72#ibcon#first serial, iclass 30, count 0 2006.175.07:20:19.72#ibcon#enter sib2, iclass 30, count 0 2006.175.07:20:19.72#ibcon#flushed, iclass 30, count 0 2006.175.07:20:19.72#ibcon#about to write, iclass 30, count 0 2006.175.07:20:19.72#ibcon#wrote, iclass 30, count 0 2006.175.07:20:19.73#ibcon#about to read 3, iclass 30, count 0 2006.175.07:20:19.74#ibcon#read 3, iclass 30, count 0 2006.175.07:20:19.74#ibcon#about to read 4, iclass 30, count 0 2006.175.07:20:19.74#ibcon#read 4, iclass 30, count 0 2006.175.07:20:19.74#ibcon#about to read 5, iclass 30, count 0 2006.175.07:20:19.74#ibcon#read 5, iclass 30, count 0 2006.175.07:20:19.74#ibcon#about to read 6, iclass 30, count 0 2006.175.07:20:19.74#ibcon#read 6, iclass 30, count 0 2006.175.07:20:19.74#ibcon#end of sib2, iclass 30, count 0 2006.175.07:20:19.74#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:20:19.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:20:19.74#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:20:19.74#ibcon#*before write, iclass 30, count 0 2006.175.07:20:19.74#ibcon#enter sib2, iclass 30, count 0 2006.175.07:20:19.74#ibcon#flushed, iclass 30, count 0 2006.175.07:20:19.74#ibcon#about to write, iclass 30, count 0 2006.175.07:20:19.74#ibcon#wrote, iclass 30, count 0 2006.175.07:20:19.74#ibcon#about to read 3, iclass 30, count 0 2006.175.07:20:19.78#ibcon#read 3, iclass 30, count 0 2006.175.07:20:19.78#ibcon#about to read 4, iclass 30, count 0 2006.175.07:20:19.78#ibcon#read 4, iclass 30, count 0 2006.175.07:20:19.78#ibcon#about to read 5, iclass 30, count 0 2006.175.07:20:19.78#ibcon#read 5, iclass 30, count 0 2006.175.07:20:19.78#ibcon#about to read 6, iclass 30, count 0 2006.175.07:20:19.78#ibcon#read 6, iclass 30, count 0 2006.175.07:20:19.78#ibcon#end of sib2, iclass 30, count 0 2006.175.07:20:19.78#ibcon#*after write, iclass 30, count 0 2006.175.07:20:19.78#ibcon#*before return 0, iclass 30, count 0 2006.175.07:20:19.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:19.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:20:19.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:20:19.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:20:19.78$vc4f8/vb=2,4 2006.175.07:20:19.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.07:20:19.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.07:20:19.78#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:19.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:19.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:19.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:19.85#ibcon#enter wrdev, iclass 32, count 2 2006.175.07:20:19.85#ibcon#first serial, iclass 32, count 2 2006.175.07:20:19.85#ibcon#enter sib2, iclass 32, count 2 2006.175.07:20:19.85#ibcon#flushed, iclass 32, count 2 2006.175.07:20:19.85#ibcon#about to write, iclass 32, count 2 2006.175.07:20:19.85#ibcon#wrote, iclass 32, count 2 2006.175.07:20:19.85#ibcon#about to read 3, iclass 32, count 2 2006.175.07:20:19.87#ibcon#read 3, iclass 32, count 2 2006.175.07:20:19.87#ibcon#about to read 4, iclass 32, count 2 2006.175.07:20:19.87#ibcon#read 4, iclass 32, count 2 2006.175.07:20:19.87#ibcon#about to read 5, iclass 32, count 2 2006.175.07:20:19.87#ibcon#read 5, iclass 32, count 2 2006.175.07:20:19.87#ibcon#about to read 6, iclass 32, count 2 2006.175.07:20:19.87#ibcon#read 6, iclass 32, count 2 2006.175.07:20:19.87#ibcon#end of sib2, iclass 32, count 2 2006.175.07:20:19.87#ibcon#*mode == 0, iclass 32, count 2 2006.175.07:20:19.87#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.07:20:19.87#ibcon#[27=AT02-04\r\n] 2006.175.07:20:19.87#ibcon#*before write, iclass 32, count 2 2006.175.07:20:19.87#ibcon#enter sib2, iclass 32, count 2 2006.175.07:20:19.87#ibcon#flushed, iclass 32, count 2 2006.175.07:20:19.87#ibcon#about to write, iclass 32, count 2 2006.175.07:20:19.87#ibcon#wrote, iclass 32, count 2 2006.175.07:20:19.87#ibcon#about to read 3, iclass 32, count 2 2006.175.07:20:19.89#ibcon#read 3, iclass 32, count 2 2006.175.07:20:19.89#ibcon#about to read 4, iclass 32, count 2 2006.175.07:20:19.89#ibcon#read 4, iclass 32, count 2 2006.175.07:20:19.89#ibcon#about to read 5, iclass 32, count 2 2006.175.07:20:19.89#ibcon#read 5, iclass 32, count 2 2006.175.07:20:19.89#ibcon#about to read 6, iclass 32, count 2 2006.175.07:20:19.89#ibcon#read 6, iclass 32, count 2 2006.175.07:20:19.89#ibcon#end of sib2, iclass 32, count 2 2006.175.07:20:19.89#ibcon#*after write, iclass 32, count 2 2006.175.07:20:19.89#ibcon#*before return 0, iclass 32, count 2 2006.175.07:20:19.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:19.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:20:19.89#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.07:20:19.89#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:19.89#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:20.01#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:20.01#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:20.01#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:20:20.01#ibcon#first serial, iclass 32, count 0 2006.175.07:20:20.01#ibcon#enter sib2, iclass 32, count 0 2006.175.07:20:20.01#ibcon#flushed, iclass 32, count 0 2006.175.07:20:20.01#ibcon#about to write, iclass 32, count 0 2006.175.07:20:20.01#ibcon#wrote, iclass 32, count 0 2006.175.07:20:20.01#ibcon#about to read 3, iclass 32, count 0 2006.175.07:20:20.03#ibcon#read 3, iclass 32, count 0 2006.175.07:20:20.03#ibcon#about to read 4, iclass 32, count 0 2006.175.07:20:20.03#ibcon#read 4, iclass 32, count 0 2006.175.07:20:20.03#ibcon#about to read 5, iclass 32, count 0 2006.175.07:20:20.03#ibcon#read 5, iclass 32, count 0 2006.175.07:20:20.03#ibcon#about to read 6, iclass 32, count 0 2006.175.07:20:20.03#ibcon#read 6, iclass 32, count 0 2006.175.07:20:20.03#ibcon#end of sib2, iclass 32, count 0 2006.175.07:20:20.03#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:20:20.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:20:20.03#ibcon#[27=USB\r\n] 2006.175.07:20:20.03#ibcon#*before write, iclass 32, count 0 2006.175.07:20:20.03#ibcon#enter sib2, iclass 32, count 0 2006.175.07:20:20.03#ibcon#flushed, iclass 32, count 0 2006.175.07:20:20.03#ibcon#about to write, iclass 32, count 0 2006.175.07:20:20.03#ibcon#wrote, iclass 32, count 0 2006.175.07:20:20.03#ibcon#about to read 3, iclass 32, count 0 2006.175.07:20:20.06#ibcon#read 3, iclass 32, count 0 2006.175.07:20:20.06#ibcon#about to read 4, iclass 32, count 0 2006.175.07:20:20.06#ibcon#read 4, iclass 32, count 0 2006.175.07:20:20.06#ibcon#about to read 5, iclass 32, count 0 2006.175.07:20:20.06#ibcon#read 5, iclass 32, count 0 2006.175.07:20:20.06#ibcon#about to read 6, iclass 32, count 0 2006.175.07:20:20.06#ibcon#read 6, iclass 32, count 0 2006.175.07:20:20.06#ibcon#end of sib2, iclass 32, count 0 2006.175.07:20:20.06#ibcon#*after write, iclass 32, count 0 2006.175.07:20:20.06#ibcon#*before return 0, iclass 32, count 0 2006.175.07:20:20.06#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:20.06#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:20:20.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:20:20.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:20:20.06$vc4f8/vblo=3,656.99 2006.175.07:20:20.06#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.07:20:20.06#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.07:20:20.06#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:20.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:20.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:20.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:20.06#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:20:20.06#ibcon#first serial, iclass 34, count 0 2006.175.07:20:20.06#ibcon#enter sib2, iclass 34, count 0 2006.175.07:20:20.06#ibcon#flushed, iclass 34, count 0 2006.175.07:20:20.06#ibcon#about to write, iclass 34, count 0 2006.175.07:20:20.07#ibcon#wrote, iclass 34, count 0 2006.175.07:20:20.07#ibcon#about to read 3, iclass 34, count 0 2006.175.07:20:20.08#ibcon#read 3, iclass 34, count 0 2006.175.07:20:20.08#ibcon#about to read 4, iclass 34, count 0 2006.175.07:20:20.08#ibcon#read 4, iclass 34, count 0 2006.175.07:20:20.08#ibcon#about to read 5, iclass 34, count 0 2006.175.07:20:20.08#ibcon#read 5, iclass 34, count 0 2006.175.07:20:20.08#ibcon#about to read 6, iclass 34, count 0 2006.175.07:20:20.08#ibcon#read 6, iclass 34, count 0 2006.175.07:20:20.08#ibcon#end of sib2, iclass 34, count 0 2006.175.07:20:20.08#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:20:20.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:20:20.08#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:20:20.08#ibcon#*before write, iclass 34, count 0 2006.175.07:20:20.08#ibcon#enter sib2, iclass 34, count 0 2006.175.07:20:20.08#ibcon#flushed, iclass 34, count 0 2006.175.07:20:20.08#ibcon#about to write, iclass 34, count 0 2006.175.07:20:20.08#ibcon#wrote, iclass 34, count 0 2006.175.07:20:20.08#ibcon#about to read 3, iclass 34, count 0 2006.175.07:20:20.12#ibcon#read 3, iclass 34, count 0 2006.175.07:20:20.12#ibcon#about to read 4, iclass 34, count 0 2006.175.07:20:20.12#ibcon#read 4, iclass 34, count 0 2006.175.07:20:20.12#ibcon#about to read 5, iclass 34, count 0 2006.175.07:20:20.12#ibcon#read 5, iclass 34, count 0 2006.175.07:20:20.12#ibcon#about to read 6, iclass 34, count 0 2006.175.07:20:20.12#ibcon#read 6, iclass 34, count 0 2006.175.07:20:20.12#ibcon#end of sib2, iclass 34, count 0 2006.175.07:20:20.12#ibcon#*after write, iclass 34, count 0 2006.175.07:20:20.12#ibcon#*before return 0, iclass 34, count 0 2006.175.07:20:20.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:20.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:20:20.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:20:20.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:20:20.12$vc4f8/vb=3,4 2006.175.07:20:20.12#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.07:20:20.12#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.07:20:20.12#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:20.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:20.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:20.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:20.18#ibcon#enter wrdev, iclass 36, count 2 2006.175.07:20:20.18#ibcon#first serial, iclass 36, count 2 2006.175.07:20:20.18#ibcon#enter sib2, iclass 36, count 2 2006.175.07:20:20.18#ibcon#flushed, iclass 36, count 2 2006.175.07:20:20.18#ibcon#about to write, iclass 36, count 2 2006.175.07:20:20.18#ibcon#wrote, iclass 36, count 2 2006.175.07:20:20.18#ibcon#about to read 3, iclass 36, count 2 2006.175.07:20:20.20#ibcon#read 3, iclass 36, count 2 2006.175.07:20:20.20#ibcon#about to read 4, iclass 36, count 2 2006.175.07:20:20.20#ibcon#read 4, iclass 36, count 2 2006.175.07:20:20.20#ibcon#about to read 5, iclass 36, count 2 2006.175.07:20:20.20#ibcon#read 5, iclass 36, count 2 2006.175.07:20:20.20#ibcon#about to read 6, iclass 36, count 2 2006.175.07:20:20.20#ibcon#read 6, iclass 36, count 2 2006.175.07:20:20.20#ibcon#end of sib2, iclass 36, count 2 2006.175.07:20:20.20#ibcon#*mode == 0, iclass 36, count 2 2006.175.07:20:20.20#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.07:20:20.20#ibcon#[27=AT03-04\r\n] 2006.175.07:20:20.20#ibcon#*before write, iclass 36, count 2 2006.175.07:20:20.20#ibcon#enter sib2, iclass 36, count 2 2006.175.07:20:20.20#ibcon#flushed, iclass 36, count 2 2006.175.07:20:20.20#ibcon#about to write, iclass 36, count 2 2006.175.07:20:20.20#ibcon#wrote, iclass 36, count 2 2006.175.07:20:20.20#ibcon#about to read 3, iclass 36, count 2 2006.175.07:20:20.23#ibcon#read 3, iclass 36, count 2 2006.175.07:20:20.23#ibcon#about to read 4, iclass 36, count 2 2006.175.07:20:20.23#ibcon#read 4, iclass 36, count 2 2006.175.07:20:20.23#ibcon#about to read 5, iclass 36, count 2 2006.175.07:20:20.23#ibcon#read 5, iclass 36, count 2 2006.175.07:20:20.23#ibcon#about to read 6, iclass 36, count 2 2006.175.07:20:20.23#ibcon#read 6, iclass 36, count 2 2006.175.07:20:20.23#ibcon#end of sib2, iclass 36, count 2 2006.175.07:20:20.23#ibcon#*after write, iclass 36, count 2 2006.175.07:20:20.23#ibcon#*before return 0, iclass 36, count 2 2006.175.07:20:20.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:20.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:20:20.23#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.07:20:20.23#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:20.23#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:20.35#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:20.35#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:20.35#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:20:20.35#ibcon#first serial, iclass 36, count 0 2006.175.07:20:20.35#ibcon#enter sib2, iclass 36, count 0 2006.175.07:20:20.35#ibcon#flushed, iclass 36, count 0 2006.175.07:20:20.35#ibcon#about to write, iclass 36, count 0 2006.175.07:20:20.35#ibcon#wrote, iclass 36, count 0 2006.175.07:20:20.35#ibcon#about to read 3, iclass 36, count 0 2006.175.07:20:20.37#ibcon#read 3, iclass 36, count 0 2006.175.07:20:20.37#ibcon#about to read 4, iclass 36, count 0 2006.175.07:20:20.37#ibcon#read 4, iclass 36, count 0 2006.175.07:20:20.37#ibcon#about to read 5, iclass 36, count 0 2006.175.07:20:20.37#ibcon#read 5, iclass 36, count 0 2006.175.07:20:20.37#ibcon#about to read 6, iclass 36, count 0 2006.175.07:20:20.37#ibcon#read 6, iclass 36, count 0 2006.175.07:20:20.37#ibcon#end of sib2, iclass 36, count 0 2006.175.07:20:20.37#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:20:20.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:20:20.37#ibcon#[27=USB\r\n] 2006.175.07:20:20.37#ibcon#*before write, iclass 36, count 0 2006.175.07:20:20.37#ibcon#enter sib2, iclass 36, count 0 2006.175.07:20:20.37#ibcon#flushed, iclass 36, count 0 2006.175.07:20:20.37#ibcon#about to write, iclass 36, count 0 2006.175.07:20:20.37#ibcon#wrote, iclass 36, count 0 2006.175.07:20:20.37#ibcon#about to read 3, iclass 36, count 0 2006.175.07:20:20.40#ibcon#read 3, iclass 36, count 0 2006.175.07:20:20.40#ibcon#about to read 4, iclass 36, count 0 2006.175.07:20:20.40#ibcon#read 4, iclass 36, count 0 2006.175.07:20:20.40#ibcon#about to read 5, iclass 36, count 0 2006.175.07:20:20.40#ibcon#read 5, iclass 36, count 0 2006.175.07:20:20.40#ibcon#about to read 6, iclass 36, count 0 2006.175.07:20:20.40#ibcon#read 6, iclass 36, count 0 2006.175.07:20:20.40#ibcon#end of sib2, iclass 36, count 0 2006.175.07:20:20.40#ibcon#*after write, iclass 36, count 0 2006.175.07:20:20.40#ibcon#*before return 0, iclass 36, count 0 2006.175.07:20:20.40#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:20.40#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:20:20.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:20:20.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:20:20.40$vc4f8/vblo=4,712.99 2006.175.07:20:20.40#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:20:20.40#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:20:20.40#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:20.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:20.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:20.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:20.40#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:20:20.40#ibcon#first serial, iclass 38, count 0 2006.175.07:20:20.40#ibcon#enter sib2, iclass 38, count 0 2006.175.07:20:20.40#ibcon#flushed, iclass 38, count 0 2006.175.07:20:20.40#ibcon#about to write, iclass 38, count 0 2006.175.07:20:20.41#ibcon#wrote, iclass 38, count 0 2006.175.07:20:20.41#ibcon#about to read 3, iclass 38, count 0 2006.175.07:20:20.42#ibcon#read 3, iclass 38, count 0 2006.175.07:20:20.42#ibcon#about to read 4, iclass 38, count 0 2006.175.07:20:20.42#ibcon#read 4, iclass 38, count 0 2006.175.07:20:20.42#ibcon#about to read 5, iclass 38, count 0 2006.175.07:20:20.42#ibcon#read 5, iclass 38, count 0 2006.175.07:20:20.42#ibcon#about to read 6, iclass 38, count 0 2006.175.07:20:20.42#ibcon#read 6, iclass 38, count 0 2006.175.07:20:20.42#ibcon#end of sib2, iclass 38, count 0 2006.175.07:20:20.42#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:20:20.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:20:20.42#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:20:20.42#ibcon#*before write, iclass 38, count 0 2006.175.07:20:20.42#ibcon#enter sib2, iclass 38, count 0 2006.175.07:20:20.42#ibcon#flushed, iclass 38, count 0 2006.175.07:20:20.42#ibcon#about to write, iclass 38, count 0 2006.175.07:20:20.42#ibcon#wrote, iclass 38, count 0 2006.175.07:20:20.42#ibcon#about to read 3, iclass 38, count 0 2006.175.07:20:20.46#ibcon#read 3, iclass 38, count 0 2006.175.07:20:20.46#ibcon#about to read 4, iclass 38, count 0 2006.175.07:20:20.46#ibcon#read 4, iclass 38, count 0 2006.175.07:20:20.46#ibcon#about to read 5, iclass 38, count 0 2006.175.07:20:20.46#ibcon#read 5, iclass 38, count 0 2006.175.07:20:20.46#ibcon#about to read 6, iclass 38, count 0 2006.175.07:20:20.46#ibcon#read 6, iclass 38, count 0 2006.175.07:20:20.46#ibcon#end of sib2, iclass 38, count 0 2006.175.07:20:20.46#ibcon#*after write, iclass 38, count 0 2006.175.07:20:20.46#ibcon#*before return 0, iclass 38, count 0 2006.175.07:20:20.46#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:20.46#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:20:20.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:20:20.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:20:20.46$vc4f8/vb=4,4 2006.175.07:20:20.46#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.07:20:20.46#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.07:20:20.46#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:20.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:20.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:20.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:20.52#ibcon#enter wrdev, iclass 40, count 2 2006.175.07:20:20.52#ibcon#first serial, iclass 40, count 2 2006.175.07:20:20.52#ibcon#enter sib2, iclass 40, count 2 2006.175.07:20:20.52#ibcon#flushed, iclass 40, count 2 2006.175.07:20:20.52#ibcon#about to write, iclass 40, count 2 2006.175.07:20:20.52#ibcon#wrote, iclass 40, count 2 2006.175.07:20:20.52#ibcon#about to read 3, iclass 40, count 2 2006.175.07:20:20.54#ibcon#read 3, iclass 40, count 2 2006.175.07:20:20.54#ibcon#about to read 4, iclass 40, count 2 2006.175.07:20:20.54#ibcon#read 4, iclass 40, count 2 2006.175.07:20:20.54#ibcon#about to read 5, iclass 40, count 2 2006.175.07:20:20.54#ibcon#read 5, iclass 40, count 2 2006.175.07:20:20.54#ibcon#about to read 6, iclass 40, count 2 2006.175.07:20:20.54#ibcon#read 6, iclass 40, count 2 2006.175.07:20:20.54#ibcon#end of sib2, iclass 40, count 2 2006.175.07:20:20.54#ibcon#*mode == 0, iclass 40, count 2 2006.175.07:20:20.54#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.07:20:20.54#ibcon#[27=AT04-04\r\n] 2006.175.07:20:20.54#ibcon#*before write, iclass 40, count 2 2006.175.07:20:20.54#ibcon#enter sib2, iclass 40, count 2 2006.175.07:20:20.54#ibcon#flushed, iclass 40, count 2 2006.175.07:20:20.54#ibcon#about to write, iclass 40, count 2 2006.175.07:20:20.54#ibcon#wrote, iclass 40, count 2 2006.175.07:20:20.54#ibcon#about to read 3, iclass 40, count 2 2006.175.07:20:20.57#ibcon#read 3, iclass 40, count 2 2006.175.07:20:20.57#ibcon#about to read 4, iclass 40, count 2 2006.175.07:20:20.57#ibcon#read 4, iclass 40, count 2 2006.175.07:20:20.57#ibcon#about to read 5, iclass 40, count 2 2006.175.07:20:20.57#ibcon#read 5, iclass 40, count 2 2006.175.07:20:20.57#ibcon#about to read 6, iclass 40, count 2 2006.175.07:20:20.57#ibcon#read 6, iclass 40, count 2 2006.175.07:20:20.57#ibcon#end of sib2, iclass 40, count 2 2006.175.07:20:20.57#ibcon#*after write, iclass 40, count 2 2006.175.07:20:20.57#ibcon#*before return 0, iclass 40, count 2 2006.175.07:20:20.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:20.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:20:20.57#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.07:20:20.57#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:20.57#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:20.69#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:20.69#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:20.69#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:20:20.69#ibcon#first serial, iclass 40, count 0 2006.175.07:20:20.69#ibcon#enter sib2, iclass 40, count 0 2006.175.07:20:20.69#ibcon#flushed, iclass 40, count 0 2006.175.07:20:20.69#ibcon#about to write, iclass 40, count 0 2006.175.07:20:20.69#ibcon#wrote, iclass 40, count 0 2006.175.07:20:20.69#ibcon#about to read 3, iclass 40, count 0 2006.175.07:20:20.71#ibcon#read 3, iclass 40, count 0 2006.175.07:20:20.71#ibcon#about to read 4, iclass 40, count 0 2006.175.07:20:20.71#ibcon#read 4, iclass 40, count 0 2006.175.07:20:20.71#ibcon#about to read 5, iclass 40, count 0 2006.175.07:20:20.71#ibcon#read 5, iclass 40, count 0 2006.175.07:20:20.71#ibcon#about to read 6, iclass 40, count 0 2006.175.07:20:20.71#ibcon#read 6, iclass 40, count 0 2006.175.07:20:20.71#ibcon#end of sib2, iclass 40, count 0 2006.175.07:20:20.71#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:20:20.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:20:20.71#ibcon#[27=USB\r\n] 2006.175.07:20:20.71#ibcon#*before write, iclass 40, count 0 2006.175.07:20:20.71#ibcon#enter sib2, iclass 40, count 0 2006.175.07:20:20.71#ibcon#flushed, iclass 40, count 0 2006.175.07:20:20.71#ibcon#about to write, iclass 40, count 0 2006.175.07:20:20.71#ibcon#wrote, iclass 40, count 0 2006.175.07:20:20.71#ibcon#about to read 3, iclass 40, count 0 2006.175.07:20:20.74#ibcon#read 3, iclass 40, count 0 2006.175.07:20:20.74#ibcon#about to read 4, iclass 40, count 0 2006.175.07:20:20.74#ibcon#read 4, iclass 40, count 0 2006.175.07:20:20.74#ibcon#about to read 5, iclass 40, count 0 2006.175.07:20:20.74#ibcon#read 5, iclass 40, count 0 2006.175.07:20:20.74#ibcon#about to read 6, iclass 40, count 0 2006.175.07:20:20.74#ibcon#read 6, iclass 40, count 0 2006.175.07:20:20.74#ibcon#end of sib2, iclass 40, count 0 2006.175.07:20:20.74#ibcon#*after write, iclass 40, count 0 2006.175.07:20:20.74#ibcon#*before return 0, iclass 40, count 0 2006.175.07:20:20.74#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:20.74#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:20:20.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:20:20.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:20:20.74$vc4f8/vblo=5,744.99 2006.175.07:20:20.74#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:20:20.74#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:20:20.74#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:20.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:20.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:20.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:20.74#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:20:20.74#ibcon#first serial, iclass 4, count 0 2006.175.07:20:20.74#ibcon#enter sib2, iclass 4, count 0 2006.175.07:20:20.74#ibcon#flushed, iclass 4, count 0 2006.175.07:20:20.74#ibcon#about to write, iclass 4, count 0 2006.175.07:20:20.75#ibcon#wrote, iclass 4, count 0 2006.175.07:20:20.75#ibcon#about to read 3, iclass 4, count 0 2006.175.07:20:20.76#ibcon#read 3, iclass 4, count 0 2006.175.07:20:20.76#ibcon#about to read 4, iclass 4, count 0 2006.175.07:20:20.76#ibcon#read 4, iclass 4, count 0 2006.175.07:20:20.76#ibcon#about to read 5, iclass 4, count 0 2006.175.07:20:20.76#ibcon#read 5, iclass 4, count 0 2006.175.07:20:20.76#ibcon#about to read 6, iclass 4, count 0 2006.175.07:20:20.76#ibcon#read 6, iclass 4, count 0 2006.175.07:20:20.76#ibcon#end of sib2, iclass 4, count 0 2006.175.07:20:20.76#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:20:20.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:20:20.76#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:20:20.76#ibcon#*before write, iclass 4, count 0 2006.175.07:20:20.76#ibcon#enter sib2, iclass 4, count 0 2006.175.07:20:20.76#ibcon#flushed, iclass 4, count 0 2006.175.07:20:20.76#ibcon#about to write, iclass 4, count 0 2006.175.07:20:20.76#ibcon#wrote, iclass 4, count 0 2006.175.07:20:20.76#ibcon#about to read 3, iclass 4, count 0 2006.175.07:20:20.80#ibcon#read 3, iclass 4, count 0 2006.175.07:20:20.80#ibcon#about to read 4, iclass 4, count 0 2006.175.07:20:20.80#ibcon#read 4, iclass 4, count 0 2006.175.07:20:20.80#ibcon#about to read 5, iclass 4, count 0 2006.175.07:20:20.80#ibcon#read 5, iclass 4, count 0 2006.175.07:20:20.80#ibcon#about to read 6, iclass 4, count 0 2006.175.07:20:20.80#ibcon#read 6, iclass 4, count 0 2006.175.07:20:20.80#ibcon#end of sib2, iclass 4, count 0 2006.175.07:20:20.80#ibcon#*after write, iclass 4, count 0 2006.175.07:20:20.80#ibcon#*before return 0, iclass 4, count 0 2006.175.07:20:20.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:20.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:20:20.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:20:20.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:20:20.80$vc4f8/vb=5,4 2006.175.07:20:20.80#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.07:20:20.80#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.07:20:20.80#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:20.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:20.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:20.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:20.86#ibcon#enter wrdev, iclass 6, count 2 2006.175.07:20:20.86#ibcon#first serial, iclass 6, count 2 2006.175.07:20:20.86#ibcon#enter sib2, iclass 6, count 2 2006.175.07:20:20.86#ibcon#flushed, iclass 6, count 2 2006.175.07:20:20.86#ibcon#about to write, iclass 6, count 2 2006.175.07:20:20.86#ibcon#wrote, iclass 6, count 2 2006.175.07:20:20.86#ibcon#about to read 3, iclass 6, count 2 2006.175.07:20:20.88#ibcon#read 3, iclass 6, count 2 2006.175.07:20:20.88#ibcon#about to read 4, iclass 6, count 2 2006.175.07:20:20.88#ibcon#read 4, iclass 6, count 2 2006.175.07:20:20.88#ibcon#about to read 5, iclass 6, count 2 2006.175.07:20:20.88#ibcon#read 5, iclass 6, count 2 2006.175.07:20:20.88#ibcon#about to read 6, iclass 6, count 2 2006.175.07:20:20.88#ibcon#read 6, iclass 6, count 2 2006.175.07:20:20.88#ibcon#end of sib2, iclass 6, count 2 2006.175.07:20:20.88#ibcon#*mode == 0, iclass 6, count 2 2006.175.07:20:20.88#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.07:20:20.88#ibcon#[27=AT05-04\r\n] 2006.175.07:20:20.88#ibcon#*before write, iclass 6, count 2 2006.175.07:20:20.88#ibcon#enter sib2, iclass 6, count 2 2006.175.07:20:20.88#ibcon#flushed, iclass 6, count 2 2006.175.07:20:20.88#ibcon#about to write, iclass 6, count 2 2006.175.07:20:20.88#ibcon#wrote, iclass 6, count 2 2006.175.07:20:20.88#ibcon#about to read 3, iclass 6, count 2 2006.175.07:20:20.91#ibcon#read 3, iclass 6, count 2 2006.175.07:20:20.91#ibcon#about to read 4, iclass 6, count 2 2006.175.07:20:20.91#ibcon#read 4, iclass 6, count 2 2006.175.07:20:20.91#ibcon#about to read 5, iclass 6, count 2 2006.175.07:20:20.91#ibcon#read 5, iclass 6, count 2 2006.175.07:20:20.91#ibcon#about to read 6, iclass 6, count 2 2006.175.07:20:20.91#ibcon#read 6, iclass 6, count 2 2006.175.07:20:20.91#ibcon#end of sib2, iclass 6, count 2 2006.175.07:20:20.91#ibcon#*after write, iclass 6, count 2 2006.175.07:20:20.91#ibcon#*before return 0, iclass 6, count 2 2006.175.07:20:20.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:20.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:20:20.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.07:20:20.91#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:20.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:21.03#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:21.03#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:21.03#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:20:21.03#ibcon#first serial, iclass 6, count 0 2006.175.07:20:21.03#ibcon#enter sib2, iclass 6, count 0 2006.175.07:20:21.03#ibcon#flushed, iclass 6, count 0 2006.175.07:20:21.03#ibcon#about to write, iclass 6, count 0 2006.175.07:20:21.03#ibcon#wrote, iclass 6, count 0 2006.175.07:20:21.03#ibcon#about to read 3, iclass 6, count 0 2006.175.07:20:21.05#ibcon#read 3, iclass 6, count 0 2006.175.07:20:21.05#ibcon#about to read 4, iclass 6, count 0 2006.175.07:20:21.05#ibcon#read 4, iclass 6, count 0 2006.175.07:20:21.05#ibcon#about to read 5, iclass 6, count 0 2006.175.07:20:21.05#ibcon#read 5, iclass 6, count 0 2006.175.07:20:21.05#ibcon#about to read 6, iclass 6, count 0 2006.175.07:20:21.05#ibcon#read 6, iclass 6, count 0 2006.175.07:20:21.05#ibcon#end of sib2, iclass 6, count 0 2006.175.07:20:21.05#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:20:21.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:20:21.05#ibcon#[27=USB\r\n] 2006.175.07:20:21.05#ibcon#*before write, iclass 6, count 0 2006.175.07:20:21.05#ibcon#enter sib2, iclass 6, count 0 2006.175.07:20:21.05#ibcon#flushed, iclass 6, count 0 2006.175.07:20:21.05#ibcon#about to write, iclass 6, count 0 2006.175.07:20:21.05#ibcon#wrote, iclass 6, count 0 2006.175.07:20:21.05#ibcon#about to read 3, iclass 6, count 0 2006.175.07:20:21.08#ibcon#read 3, iclass 6, count 0 2006.175.07:20:21.08#ibcon#about to read 4, iclass 6, count 0 2006.175.07:20:21.08#ibcon#read 4, iclass 6, count 0 2006.175.07:20:21.08#ibcon#about to read 5, iclass 6, count 0 2006.175.07:20:21.08#ibcon#read 5, iclass 6, count 0 2006.175.07:20:21.08#ibcon#about to read 6, iclass 6, count 0 2006.175.07:20:21.08#ibcon#read 6, iclass 6, count 0 2006.175.07:20:21.08#ibcon#end of sib2, iclass 6, count 0 2006.175.07:20:21.08#ibcon#*after write, iclass 6, count 0 2006.175.07:20:21.08#ibcon#*before return 0, iclass 6, count 0 2006.175.07:20:21.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:21.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:20:21.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:20:21.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:20:21.08$vc4f8/vblo=6,752.99 2006.175.07:20:21.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.07:20:21.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.07:20:21.08#ibcon#ireg 17 cls_cnt 0 2006.175.07:20:21.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:21.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:21.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:21.08#ibcon#enter wrdev, iclass 10, count 0 2006.175.07:20:21.08#ibcon#first serial, iclass 10, count 0 2006.175.07:20:21.08#ibcon#enter sib2, iclass 10, count 0 2006.175.07:20:21.08#ibcon#flushed, iclass 10, count 0 2006.175.07:20:21.08#ibcon#about to write, iclass 10, count 0 2006.175.07:20:21.09#ibcon#wrote, iclass 10, count 0 2006.175.07:20:21.09#ibcon#about to read 3, iclass 10, count 0 2006.175.07:20:21.10#ibcon#read 3, iclass 10, count 0 2006.175.07:20:21.10#ibcon#about to read 4, iclass 10, count 0 2006.175.07:20:21.10#ibcon#read 4, iclass 10, count 0 2006.175.07:20:21.10#ibcon#about to read 5, iclass 10, count 0 2006.175.07:20:21.10#ibcon#read 5, iclass 10, count 0 2006.175.07:20:21.10#ibcon#about to read 6, iclass 10, count 0 2006.175.07:20:21.10#ibcon#read 6, iclass 10, count 0 2006.175.07:20:21.10#ibcon#end of sib2, iclass 10, count 0 2006.175.07:20:21.10#ibcon#*mode == 0, iclass 10, count 0 2006.175.07:20:21.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.07:20:21.10#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:20:21.10#ibcon#*before write, iclass 10, count 0 2006.175.07:20:21.10#ibcon#enter sib2, iclass 10, count 0 2006.175.07:20:21.10#ibcon#flushed, iclass 10, count 0 2006.175.07:20:21.10#ibcon#about to write, iclass 10, count 0 2006.175.07:20:21.10#ibcon#wrote, iclass 10, count 0 2006.175.07:20:21.10#ibcon#about to read 3, iclass 10, count 0 2006.175.07:20:21.14#ibcon#read 3, iclass 10, count 0 2006.175.07:20:21.14#ibcon#about to read 4, iclass 10, count 0 2006.175.07:20:21.14#ibcon#read 4, iclass 10, count 0 2006.175.07:20:21.14#ibcon#about to read 5, iclass 10, count 0 2006.175.07:20:21.14#ibcon#read 5, iclass 10, count 0 2006.175.07:20:21.14#ibcon#about to read 6, iclass 10, count 0 2006.175.07:20:21.14#ibcon#read 6, iclass 10, count 0 2006.175.07:20:21.14#ibcon#end of sib2, iclass 10, count 0 2006.175.07:20:21.14#ibcon#*after write, iclass 10, count 0 2006.175.07:20:21.14#ibcon#*before return 0, iclass 10, count 0 2006.175.07:20:21.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:21.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:20:21.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.07:20:21.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.07:20:21.14$vc4f8/vb=6,4 2006.175.07:20:21.14#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.07:20:21.14#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.07:20:21.14#ibcon#ireg 11 cls_cnt 2 2006.175.07:20:21.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:21.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:21.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:21.20#ibcon#enter wrdev, iclass 12, count 2 2006.175.07:20:21.20#ibcon#first serial, iclass 12, count 2 2006.175.07:20:21.20#ibcon#enter sib2, iclass 12, count 2 2006.175.07:20:21.20#ibcon#flushed, iclass 12, count 2 2006.175.07:20:21.20#ibcon#about to write, iclass 12, count 2 2006.175.07:20:21.20#ibcon#wrote, iclass 12, count 2 2006.175.07:20:21.20#ibcon#about to read 3, iclass 12, count 2 2006.175.07:20:21.22#ibcon#read 3, iclass 12, count 2 2006.175.07:20:21.22#ibcon#about to read 4, iclass 12, count 2 2006.175.07:20:21.22#ibcon#read 4, iclass 12, count 2 2006.175.07:20:21.22#ibcon#about to read 5, iclass 12, count 2 2006.175.07:20:21.22#ibcon#read 5, iclass 12, count 2 2006.175.07:20:21.22#ibcon#about to read 6, iclass 12, count 2 2006.175.07:20:21.22#ibcon#read 6, iclass 12, count 2 2006.175.07:20:21.22#ibcon#end of sib2, iclass 12, count 2 2006.175.07:20:21.22#ibcon#*mode == 0, iclass 12, count 2 2006.175.07:20:21.22#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.07:20:21.22#ibcon#[27=AT06-04\r\n] 2006.175.07:20:21.22#ibcon#*before write, iclass 12, count 2 2006.175.07:20:21.22#ibcon#enter sib2, iclass 12, count 2 2006.175.07:20:21.22#ibcon#flushed, iclass 12, count 2 2006.175.07:20:21.22#ibcon#about to write, iclass 12, count 2 2006.175.07:20:21.22#ibcon#wrote, iclass 12, count 2 2006.175.07:20:21.22#ibcon#about to read 3, iclass 12, count 2 2006.175.07:20:21.25#ibcon#read 3, iclass 12, count 2 2006.175.07:20:21.25#ibcon#about to read 4, iclass 12, count 2 2006.175.07:20:21.25#ibcon#read 4, iclass 12, count 2 2006.175.07:20:21.25#ibcon#about to read 5, iclass 12, count 2 2006.175.07:20:21.25#ibcon#read 5, iclass 12, count 2 2006.175.07:20:21.25#ibcon#about to read 6, iclass 12, count 2 2006.175.07:20:21.25#ibcon#read 6, iclass 12, count 2 2006.175.07:20:21.25#ibcon#end of sib2, iclass 12, count 2 2006.175.07:20:21.25#ibcon#*after write, iclass 12, count 2 2006.175.07:20:21.25#ibcon#*before return 0, iclass 12, count 2 2006.175.07:20:21.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:21.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:20:21.25#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.07:20:21.25#ibcon#ireg 7 cls_cnt 0 2006.175.07:20:21.25#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:21.37#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:21.37#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:21.37#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:20:21.37#ibcon#first serial, iclass 12, count 0 2006.175.07:20:21.37#ibcon#enter sib2, iclass 12, count 0 2006.175.07:20:21.37#ibcon#flushed, iclass 12, count 0 2006.175.07:20:21.37#ibcon#about to write, iclass 12, count 0 2006.175.07:20:21.37#ibcon#wrote, iclass 12, count 0 2006.175.07:20:21.37#ibcon#about to read 3, iclass 12, count 0 2006.175.07:20:21.39#ibcon#read 3, iclass 12, count 0 2006.175.07:20:21.39#ibcon#about to read 4, iclass 12, count 0 2006.175.07:20:21.39#ibcon#read 4, iclass 12, count 0 2006.175.07:20:21.39#ibcon#about to read 5, iclass 12, count 0 2006.175.07:20:21.39#ibcon#read 5, iclass 12, count 0 2006.175.07:20:21.39#ibcon#about to read 6, iclass 12, count 0 2006.175.07:20:21.39#ibcon#read 6, iclass 12, count 0 2006.175.07:20:21.39#ibcon#end of sib2, iclass 12, count 0 2006.175.07:20:21.39#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:20:21.39#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:20:21.39#ibcon#[27=USB\r\n] 2006.175.07:20:21.39#ibcon#*before write, iclass 12, count 0 2006.175.07:20:21.39#ibcon#enter sib2, iclass 12, count 0 2006.175.07:20:21.39#ibcon#flushed, iclass 12, count 0 2006.175.07:20:21.39#ibcon#about to write, iclass 12, count 0 2006.175.07:20:21.39#ibcon#wrote, iclass 12, count 0 2006.175.07:20:21.39#ibcon#about to read 3, iclass 12, count 0 2006.175.07:20:21.42#ibcon#read 3, iclass 12, count 0 2006.175.07:20:21.42#ibcon#about to read 4, iclass 12, count 0 2006.175.07:20:21.42#ibcon#read 4, iclass 12, count 0 2006.175.07:20:21.42#ibcon#about to read 5, iclass 12, count 0 2006.175.07:20:21.42#ibcon#read 5, iclass 12, count 0 2006.175.07:20:21.42#ibcon#about to read 6, iclass 12, count 0 2006.175.07:20:21.42#ibcon#read 6, iclass 12, count 0 2006.175.07:20:21.42#ibcon#end of sib2, iclass 12, count 0 2006.175.07:20:21.42#ibcon#*after write, iclass 12, count 0 2006.175.07:20:21.42#ibcon#*before return 0, iclass 12, count 0 2006.175.07:20:21.42#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:21.42#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:20:21.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:20:21.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:20:21.42$vc4f8/vabw=wide 2006.175.07:20:21.42#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.07:20:21.42#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.07:20:21.42#ibcon#ireg 8 cls_cnt 0 2006.175.07:20:21.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:21.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:21.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:21.42#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:20:21.42#ibcon#first serial, iclass 14, count 0 2006.175.07:20:21.42#ibcon#enter sib2, iclass 14, count 0 2006.175.07:20:21.42#ibcon#flushed, iclass 14, count 0 2006.175.07:20:21.42#ibcon#about to write, iclass 14, count 0 2006.175.07:20:21.42#ibcon#wrote, iclass 14, count 0 2006.175.07:20:21.42#ibcon#about to read 3, iclass 14, count 0 2006.175.07:20:21.44#ibcon#read 3, iclass 14, count 0 2006.175.07:20:21.44#ibcon#about to read 4, iclass 14, count 0 2006.175.07:20:21.44#ibcon#read 4, iclass 14, count 0 2006.175.07:20:21.44#ibcon#about to read 5, iclass 14, count 0 2006.175.07:20:21.44#ibcon#read 5, iclass 14, count 0 2006.175.07:20:21.44#ibcon#about to read 6, iclass 14, count 0 2006.175.07:20:21.44#ibcon#read 6, iclass 14, count 0 2006.175.07:20:21.44#ibcon#end of sib2, iclass 14, count 0 2006.175.07:20:21.44#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:20:21.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:20:21.44#ibcon#[25=BW32\r\n] 2006.175.07:20:21.44#ibcon#*before write, iclass 14, count 0 2006.175.07:20:21.44#ibcon#enter sib2, iclass 14, count 0 2006.175.07:20:21.44#ibcon#flushed, iclass 14, count 0 2006.175.07:20:21.44#ibcon#about to write, iclass 14, count 0 2006.175.07:20:21.44#ibcon#wrote, iclass 14, count 0 2006.175.07:20:21.44#ibcon#about to read 3, iclass 14, count 0 2006.175.07:20:21.47#ibcon#read 3, iclass 14, count 0 2006.175.07:20:21.47#ibcon#about to read 4, iclass 14, count 0 2006.175.07:20:21.47#ibcon#read 4, iclass 14, count 0 2006.175.07:20:21.47#ibcon#about to read 5, iclass 14, count 0 2006.175.07:20:21.47#ibcon#read 5, iclass 14, count 0 2006.175.07:20:21.47#ibcon#about to read 6, iclass 14, count 0 2006.175.07:20:21.47#ibcon#read 6, iclass 14, count 0 2006.175.07:20:21.47#ibcon#end of sib2, iclass 14, count 0 2006.175.07:20:21.47#ibcon#*after write, iclass 14, count 0 2006.175.07:20:21.47#ibcon#*before return 0, iclass 14, count 0 2006.175.07:20:21.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:21.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:20:21.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:20:21.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:20:21.47$vc4f8/vbbw=wide 2006.175.07:20:21.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.07:20:21.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.07:20:21.47#ibcon#ireg 8 cls_cnt 0 2006.175.07:20:21.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:20:21.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:20:21.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:20:21.55#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:20:21.55#ibcon#first serial, iclass 16, count 0 2006.175.07:20:21.55#ibcon#enter sib2, iclass 16, count 0 2006.175.07:20:21.55#ibcon#flushed, iclass 16, count 0 2006.175.07:20:21.55#ibcon#about to write, iclass 16, count 0 2006.175.07:20:21.55#ibcon#wrote, iclass 16, count 0 2006.175.07:20:21.55#ibcon#about to read 3, iclass 16, count 0 2006.175.07:20:21.56#ibcon#read 3, iclass 16, count 0 2006.175.07:20:21.56#ibcon#about to read 4, iclass 16, count 0 2006.175.07:20:21.56#ibcon#read 4, iclass 16, count 0 2006.175.07:20:21.56#ibcon#about to read 5, iclass 16, count 0 2006.175.07:20:21.56#ibcon#read 5, iclass 16, count 0 2006.175.07:20:21.56#ibcon#about to read 6, iclass 16, count 0 2006.175.07:20:21.56#ibcon#read 6, iclass 16, count 0 2006.175.07:20:21.56#ibcon#end of sib2, iclass 16, count 0 2006.175.07:20:21.56#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:20:21.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:20:21.56#ibcon#[27=BW32\r\n] 2006.175.07:20:21.56#ibcon#*before write, iclass 16, count 0 2006.175.07:20:21.56#ibcon#enter sib2, iclass 16, count 0 2006.175.07:20:21.56#ibcon#flushed, iclass 16, count 0 2006.175.07:20:21.56#ibcon#about to write, iclass 16, count 0 2006.175.07:20:21.56#ibcon#wrote, iclass 16, count 0 2006.175.07:20:21.56#ibcon#about to read 3, iclass 16, count 0 2006.175.07:20:21.59#ibcon#read 3, iclass 16, count 0 2006.175.07:20:21.59#ibcon#about to read 4, iclass 16, count 0 2006.175.07:20:21.59#ibcon#read 4, iclass 16, count 0 2006.175.07:20:21.59#ibcon#about to read 5, iclass 16, count 0 2006.175.07:20:21.59#ibcon#read 5, iclass 16, count 0 2006.175.07:20:21.59#ibcon#about to read 6, iclass 16, count 0 2006.175.07:20:21.59#ibcon#read 6, iclass 16, count 0 2006.175.07:20:21.59#ibcon#end of sib2, iclass 16, count 0 2006.175.07:20:21.59#ibcon#*after write, iclass 16, count 0 2006.175.07:20:21.59#ibcon#*before return 0, iclass 16, count 0 2006.175.07:20:21.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:20:21.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:20:21.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:20:21.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:20:21.59$4f8m12a/ifd4f 2006.175.07:20:21.59&ifd4f/lo= 2006.175.07:20:21.59&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:20:21.59&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:20:21.59&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:20:21.59&ifd4f/patch= 2006.175.07:20:21.59&ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:20:21.59&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:20:21.59&ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:20:21.60$ifd4f/lo= 2006.175.07:20:21.60$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:20:21.60$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:20:21.60$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:20:21.60$ifd4f/patch= 2006.175.07:20:21.60$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:20:21.60$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:20:21.60$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:20:21.60$4f8m12a/"form=m,16.000,1:2 2006.175.07:20:21.60$4f8m12a/"tpicd 2006.175.07:20:21.60$4f8m12a/echo=off 2006.175.07:20:21.60$4f8m12a/xlog=off 2006.175.07:20:21.60:!2006.175.07:29:50 2006.175.07:20:38.14#trakl#Source acquired 2006.175.07:20:38.14#flagr#flagr/antenna,acquired 2006.175.07:23:14.14#trakl#Off source 2006.175.07:23:14.14?ERROR st -7 Antenna off-source! 2006.175.07:23:14.14#trakl#az 21.665 el 27.669 azerr*cos(el) -0.0027 elerr 0.0204 2006.175.07:23:14.14#flagr#flagr/antenna,off-source 2006.175.07:23:20.14#trakl#Source re-acquired 2006.175.07:23:20.14#flagr#flagr/antenna,re-acquired 2006.175.07:29:50.00:preob 2006.175.07:29:50.00&preob/onsource 2006.175.07:29:51.14/onsource/TRACKING 2006.175.07:29:51.14:!2006.175.07:30:00 2006.175.07:30:00.00:data_valid=on 2006.175.07:30:00.00:midob 2006.175.07:30:00.00&midob/onsource 2006.175.07:30:00.00&midob/wx 2006.175.07:30:00.00&midob/cable 2006.175.07:30:00.00&midob/va 2006.175.07:30:00.00&midob/valo 2006.175.07:30:00.00&midob/vb 2006.175.07:30:00.00&midob/vblo 2006.175.07:30:00.00&midob/vabw 2006.175.07:30:00.00&midob/vbbw 2006.175.07:30:00.00&midob/"form 2006.175.07:30:00.00&midob/xfe 2006.175.07:30:00.00&midob/ifatt 2006.175.07:30:00.00&midob/clockoff 2006.175.07:30:00.00&midob/sy=logmail 2006.175.07:30:00.00&midob/"sy=run setcl adapt & 2006.175.07:30:00.14/onsource/TRACKING 2006.175.07:30:00.14/wx/26.07,1007.4,70 2006.175.07:30:00.29/cable/+6.4777E-03 2006.175.07:30:01.38/va/01,08,usb,yes,29,31 2006.175.07:30:01.38/va/02,07,usb,yes,30,31 2006.175.07:30:01.38/va/03,06,usb,yes,31,31 2006.175.07:30:01.38/va/04,07,usb,yes,30,33 2006.175.07:30:01.38/va/05,07,usb,yes,30,32 2006.175.07:30:01.38/va/06,06,usb,yes,30,29 2006.175.07:30:01.38/va/07,06,usb,yes,30,30 2006.175.07:30:01.38/va/08,06,usb,yes,32,32 2006.175.07:30:01.61/valo/01,532.99,yes,locked 2006.175.07:30:01.61/valo/02,572.99,yes,locked 2006.175.07:30:01.61/valo/03,672.99,yes,locked 2006.175.07:30:01.61/valo/04,832.99,yes,locked 2006.175.07:30:01.61/valo/05,652.99,yes,locked 2006.175.07:30:01.61/valo/06,772.99,yes,locked 2006.175.07:30:01.61/valo/07,832.99,yes,locked 2006.175.07:30:01.61/valo/08,852.99,yes,locked 2006.175.07:30:02.70/vb/01,04,usb,yes,29,28 2006.175.07:30:02.70/vb/02,04,usb,yes,31,32 2006.175.07:30:02.70/vb/03,04,usb,yes,28,31 2006.175.07:30:02.70/vb/04,04,usb,yes,28,29 2006.175.07:30:02.70/vb/05,04,usb,yes,27,31 2006.175.07:30:02.70/vb/06,04,usb,yes,28,31 2006.175.07:30:02.70/vb/07,04,usb,yes,30,30 2006.175.07:30:02.70/vb/08,04,usb,yes,28,31 2006.175.07:30:02.94/vblo/01,632.99,yes,locked 2006.175.07:30:02.94/vblo/02,640.99,yes,locked 2006.175.07:30:02.94/vblo/03,656.99,yes,locked 2006.175.07:30:02.94/vblo/04,712.99,yes,locked 2006.175.07:30:02.94/vblo/05,744.99,yes,locked 2006.175.07:30:02.94/vblo/06,752.99,yes,locked 2006.175.07:30:02.94/vblo/07,734.99,yes,locked 2006.175.07:30:02.94/vblo/08,744.99,yes,locked 2006.175.07:30:03.09/vabw/8 2006.175.07:30:03.24/vbbw/8 2006.175.07:30:03.33/xfe/off,on,15.2 2006.175.07:30:03.73/ifatt/23,28,28,28 2006.175.07:30:04.07/fmout-gps/S +3.79E-07 2006.175.07:30:04.16:!2006.175.07:31:00 2006.175.07:31:00.01:data_valid=off 2006.175.07:31:00.02:postob 2006.175.07:31:00.02&postob/cable 2006.175.07:31:00.02&postob/wx 2006.175.07:31:00.03&postob/clockoff 2006.175.07:31:00.20/cable/+6.4753E-03 2006.175.07:31:00.21/wx/26.06,1007.4,70 2006.175.07:31:00.26/fmout-gps/S +3.78E-07 2006.175.07:31:00.27:scan_name=175-0733,k06175,60 2006.175.07:31:00.27:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.175.07:31:01.14#flagr#flagr/antenna,new-source 2006.175.07:31:01.15:checkk5 2006.175.07:31:01.15&checkk5/chk_autoobs=1 2006.175.07:31:01.15&checkk5/chk_autoobs=2 2006.175.07:31:01.16&checkk5/chk_autoobs=3 2006.175.07:31:01.16&checkk5/chk_autoobs=4 2006.175.07:31:01.16&checkk5/chk_obsdata=1 2006.175.07:31:01.17&checkk5/chk_obsdata=2 2006.175.07:31:01.17&checkk5/chk_obsdata=3 2006.175.07:31:01.17&checkk5/chk_obsdata=4 2006.175.07:31:01.17&checkk5/k5log=1 2006.175.07:31:01.17&checkk5/k5log=2 2006.175.07:31:01.17&checkk5/k5log=3 2006.175.07:31:01.17&checkk5/k5log=4 2006.175.07:31:01.17&checkk5/obsinfo 2006.175.07:31:01.59/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:31:02.03/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:31:02.74/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:31:03.49/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:31:03.91/chk_obsdata//k5ts1/T1750730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:31:04.31/chk_obsdata//k5ts2/T1750730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:31:04.70/chk_obsdata//k5ts3/T1750730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:31:05.09/chk_obsdata//k5ts4/T1750730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:31:05.80/k5log//k5ts1_log_newline 2006.175.07:31:06.51/k5log//k5ts2_log_newline 2006.175.07:31:07.19/k5log//k5ts3_log_newline 2006.175.07:31:07.93/k5log//k5ts4_log_newline 2006.175.07:31:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:31:07.96:4f8m12a=1 2006.175.07:31:07.96$4f8m12a/echo=on 2006.175.07:31:07.96$4f8m12a/pcalon 2006.175.07:31:07.96$pcalon/"no phase cal control is implemented here 2006.175.07:31:07.96$4f8m12a/"tpicd=stop 2006.175.07:31:07.96$4f8m12a/vc4f8 2006.175.07:31:07.96$vc4f8/valo=1,532.99 2006.175.07:31:07.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.07:31:07.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.07:31:07.96#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:07.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:07.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:07.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:07.96#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:31:07.96#ibcon#first serial, iclass 21, count 0 2006.175.07:31:07.96#ibcon#enter sib2, iclass 21, count 0 2006.175.07:31:07.96#ibcon#flushed, iclass 21, count 0 2006.175.07:31:07.96#ibcon#about to write, iclass 21, count 0 2006.175.07:31:07.96#ibcon#wrote, iclass 21, count 0 2006.175.07:31:07.96#ibcon#about to read 3, iclass 21, count 0 2006.175.07:31:08.00#ibcon#read 3, iclass 21, count 0 2006.175.07:31:08.00#ibcon#about to read 4, iclass 21, count 0 2006.175.07:31:08.00#ibcon#read 4, iclass 21, count 0 2006.175.07:31:08.00#ibcon#about to read 5, iclass 21, count 0 2006.175.07:31:08.00#ibcon#read 5, iclass 21, count 0 2006.175.07:31:08.00#ibcon#about to read 6, iclass 21, count 0 2006.175.07:31:08.00#ibcon#read 6, iclass 21, count 0 2006.175.07:31:08.00#ibcon#end of sib2, iclass 21, count 0 2006.175.07:31:08.00#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:31:08.00#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:31:08.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:31:08.00#ibcon#*before write, iclass 21, count 0 2006.175.07:31:08.00#ibcon#enter sib2, iclass 21, count 0 2006.175.07:31:08.00#ibcon#flushed, iclass 21, count 0 2006.175.07:31:08.00#ibcon#about to write, iclass 21, count 0 2006.175.07:31:08.00#ibcon#wrote, iclass 21, count 0 2006.175.07:31:08.00#ibcon#about to read 3, iclass 21, count 0 2006.175.07:31:08.04#ibcon#read 3, iclass 21, count 0 2006.175.07:31:08.04#ibcon#about to read 4, iclass 21, count 0 2006.175.07:31:08.04#ibcon#read 4, iclass 21, count 0 2006.175.07:31:08.04#ibcon#about to read 5, iclass 21, count 0 2006.175.07:31:08.04#ibcon#read 5, iclass 21, count 0 2006.175.07:31:08.04#ibcon#about to read 6, iclass 21, count 0 2006.175.07:31:08.04#ibcon#read 6, iclass 21, count 0 2006.175.07:31:08.04#ibcon#end of sib2, iclass 21, count 0 2006.175.07:31:08.04#ibcon#*after write, iclass 21, count 0 2006.175.07:31:08.04#ibcon#*before return 0, iclass 21, count 0 2006.175.07:31:08.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:08.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:08.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:31:08.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:31:08.04$vc4f8/va=1,8 2006.175.07:31:08.04#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.07:31:08.04#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.07:31:08.04#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:08.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:08.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:08.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:08.04#ibcon#enter wrdev, iclass 23, count 2 2006.175.07:31:08.04#ibcon#first serial, iclass 23, count 2 2006.175.07:31:08.04#ibcon#enter sib2, iclass 23, count 2 2006.175.07:31:08.04#ibcon#flushed, iclass 23, count 2 2006.175.07:31:08.04#ibcon#about to write, iclass 23, count 2 2006.175.07:31:08.04#ibcon#wrote, iclass 23, count 2 2006.175.07:31:08.04#ibcon#about to read 3, iclass 23, count 2 2006.175.07:31:08.06#ibcon#read 3, iclass 23, count 2 2006.175.07:31:08.06#ibcon#about to read 4, iclass 23, count 2 2006.175.07:31:08.06#ibcon#read 4, iclass 23, count 2 2006.175.07:31:08.06#ibcon#about to read 5, iclass 23, count 2 2006.175.07:31:08.06#ibcon#read 5, iclass 23, count 2 2006.175.07:31:08.06#ibcon#about to read 6, iclass 23, count 2 2006.175.07:31:08.06#ibcon#read 6, iclass 23, count 2 2006.175.07:31:08.06#ibcon#end of sib2, iclass 23, count 2 2006.175.07:31:08.06#ibcon#*mode == 0, iclass 23, count 2 2006.175.07:31:08.06#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.07:31:08.06#ibcon#[25=AT01-08\r\n] 2006.175.07:31:08.06#ibcon#*before write, iclass 23, count 2 2006.175.07:31:08.06#ibcon#enter sib2, iclass 23, count 2 2006.175.07:31:08.06#ibcon#flushed, iclass 23, count 2 2006.175.07:31:08.06#ibcon#about to write, iclass 23, count 2 2006.175.07:31:08.06#ibcon#wrote, iclass 23, count 2 2006.175.07:31:08.06#ibcon#about to read 3, iclass 23, count 2 2006.175.07:31:08.09#ibcon#read 3, iclass 23, count 2 2006.175.07:31:08.09#ibcon#about to read 4, iclass 23, count 2 2006.175.07:31:08.09#ibcon#read 4, iclass 23, count 2 2006.175.07:31:08.09#ibcon#about to read 5, iclass 23, count 2 2006.175.07:31:08.09#ibcon#read 5, iclass 23, count 2 2006.175.07:31:08.09#ibcon#about to read 6, iclass 23, count 2 2006.175.07:31:08.09#ibcon#read 6, iclass 23, count 2 2006.175.07:31:08.09#ibcon#end of sib2, iclass 23, count 2 2006.175.07:31:08.09#ibcon#*after write, iclass 23, count 2 2006.175.07:31:08.09#ibcon#*before return 0, iclass 23, count 2 2006.175.07:31:08.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:08.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:08.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.07:31:08.09#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:08.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:08.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:08.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:08.21#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:31:08.21#ibcon#first serial, iclass 23, count 0 2006.175.07:31:08.21#ibcon#enter sib2, iclass 23, count 0 2006.175.07:31:08.21#ibcon#flushed, iclass 23, count 0 2006.175.07:31:08.21#ibcon#about to write, iclass 23, count 0 2006.175.07:31:08.21#ibcon#wrote, iclass 23, count 0 2006.175.07:31:08.21#ibcon#about to read 3, iclass 23, count 0 2006.175.07:31:08.23#ibcon#read 3, iclass 23, count 0 2006.175.07:31:08.23#ibcon#about to read 4, iclass 23, count 0 2006.175.07:31:08.23#ibcon#read 4, iclass 23, count 0 2006.175.07:31:08.23#ibcon#about to read 5, iclass 23, count 0 2006.175.07:31:08.23#ibcon#read 5, iclass 23, count 0 2006.175.07:31:08.23#ibcon#about to read 6, iclass 23, count 0 2006.175.07:31:08.23#ibcon#read 6, iclass 23, count 0 2006.175.07:31:08.23#ibcon#end of sib2, iclass 23, count 0 2006.175.07:31:08.23#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:31:08.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:31:08.23#ibcon#[25=USB\r\n] 2006.175.07:31:08.23#ibcon#*before write, iclass 23, count 0 2006.175.07:31:08.23#ibcon#enter sib2, iclass 23, count 0 2006.175.07:31:08.23#ibcon#flushed, iclass 23, count 0 2006.175.07:31:08.23#ibcon#about to write, iclass 23, count 0 2006.175.07:31:08.23#ibcon#wrote, iclass 23, count 0 2006.175.07:31:08.23#ibcon#about to read 3, iclass 23, count 0 2006.175.07:31:08.26#ibcon#read 3, iclass 23, count 0 2006.175.07:31:08.26#ibcon#about to read 4, iclass 23, count 0 2006.175.07:31:08.26#ibcon#read 4, iclass 23, count 0 2006.175.07:31:08.26#ibcon#about to read 5, iclass 23, count 0 2006.175.07:31:08.26#ibcon#read 5, iclass 23, count 0 2006.175.07:31:08.26#ibcon#about to read 6, iclass 23, count 0 2006.175.07:31:08.26#ibcon#read 6, iclass 23, count 0 2006.175.07:31:08.26#ibcon#end of sib2, iclass 23, count 0 2006.175.07:31:08.26#ibcon#*after write, iclass 23, count 0 2006.175.07:31:08.26#ibcon#*before return 0, iclass 23, count 0 2006.175.07:31:08.26#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:08.26#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:08.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:31:08.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:31:08.26$vc4f8/valo=2,572.99 2006.175.07:31:08.26#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.07:31:08.26#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.07:31:08.26#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:08.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:08.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:08.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:08.26#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:31:08.26#ibcon#first serial, iclass 25, count 0 2006.175.07:31:08.26#ibcon#enter sib2, iclass 25, count 0 2006.175.07:31:08.26#ibcon#flushed, iclass 25, count 0 2006.175.07:31:08.26#ibcon#about to write, iclass 25, count 0 2006.175.07:31:08.26#ibcon#wrote, iclass 25, count 0 2006.175.07:31:08.26#ibcon#about to read 3, iclass 25, count 0 2006.175.07:31:08.28#ibcon#read 3, iclass 25, count 0 2006.175.07:31:08.28#ibcon#about to read 4, iclass 25, count 0 2006.175.07:31:08.28#ibcon#read 4, iclass 25, count 0 2006.175.07:31:08.28#ibcon#about to read 5, iclass 25, count 0 2006.175.07:31:08.28#ibcon#read 5, iclass 25, count 0 2006.175.07:31:08.28#ibcon#about to read 6, iclass 25, count 0 2006.175.07:31:08.28#ibcon#read 6, iclass 25, count 0 2006.175.07:31:08.28#ibcon#end of sib2, iclass 25, count 0 2006.175.07:31:08.28#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:31:08.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:31:08.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:31:08.28#ibcon#*before write, iclass 25, count 0 2006.175.07:31:08.28#ibcon#enter sib2, iclass 25, count 0 2006.175.07:31:08.28#ibcon#flushed, iclass 25, count 0 2006.175.07:31:08.28#ibcon#about to write, iclass 25, count 0 2006.175.07:31:08.28#ibcon#wrote, iclass 25, count 0 2006.175.07:31:08.28#ibcon#about to read 3, iclass 25, count 0 2006.175.07:31:08.32#ibcon#read 3, iclass 25, count 0 2006.175.07:31:08.32#ibcon#about to read 4, iclass 25, count 0 2006.175.07:31:08.32#ibcon#read 4, iclass 25, count 0 2006.175.07:31:08.32#ibcon#about to read 5, iclass 25, count 0 2006.175.07:31:08.32#ibcon#read 5, iclass 25, count 0 2006.175.07:31:08.32#ibcon#about to read 6, iclass 25, count 0 2006.175.07:31:08.32#ibcon#read 6, iclass 25, count 0 2006.175.07:31:08.32#ibcon#end of sib2, iclass 25, count 0 2006.175.07:31:08.32#ibcon#*after write, iclass 25, count 0 2006.175.07:31:08.32#ibcon#*before return 0, iclass 25, count 0 2006.175.07:31:08.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:08.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:08.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:31:08.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:31:08.32$vc4f8/va=2,7 2006.175.07:31:08.32#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.07:31:08.32#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.07:31:08.32#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:08.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:08.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:08.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:08.38#ibcon#enter wrdev, iclass 27, count 2 2006.175.07:31:08.38#ibcon#first serial, iclass 27, count 2 2006.175.07:31:08.38#ibcon#enter sib2, iclass 27, count 2 2006.175.07:31:08.38#ibcon#flushed, iclass 27, count 2 2006.175.07:31:08.38#ibcon#about to write, iclass 27, count 2 2006.175.07:31:08.38#ibcon#wrote, iclass 27, count 2 2006.175.07:31:08.38#ibcon#about to read 3, iclass 27, count 2 2006.175.07:31:08.40#ibcon#read 3, iclass 27, count 2 2006.175.07:31:08.40#ibcon#about to read 4, iclass 27, count 2 2006.175.07:31:08.40#ibcon#read 4, iclass 27, count 2 2006.175.07:31:08.40#ibcon#about to read 5, iclass 27, count 2 2006.175.07:31:08.40#ibcon#read 5, iclass 27, count 2 2006.175.07:31:08.40#ibcon#about to read 6, iclass 27, count 2 2006.175.07:31:08.40#ibcon#read 6, iclass 27, count 2 2006.175.07:31:08.40#ibcon#end of sib2, iclass 27, count 2 2006.175.07:31:08.40#ibcon#*mode == 0, iclass 27, count 2 2006.175.07:31:08.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.07:31:08.40#ibcon#[25=AT02-07\r\n] 2006.175.07:31:08.40#ibcon#*before write, iclass 27, count 2 2006.175.07:31:08.40#ibcon#enter sib2, iclass 27, count 2 2006.175.07:31:08.40#ibcon#flushed, iclass 27, count 2 2006.175.07:31:08.40#ibcon#about to write, iclass 27, count 2 2006.175.07:31:08.40#ibcon#wrote, iclass 27, count 2 2006.175.07:31:08.40#ibcon#about to read 3, iclass 27, count 2 2006.175.07:31:08.43#ibcon#read 3, iclass 27, count 2 2006.175.07:31:08.43#ibcon#about to read 4, iclass 27, count 2 2006.175.07:31:08.43#ibcon#read 4, iclass 27, count 2 2006.175.07:31:08.43#ibcon#about to read 5, iclass 27, count 2 2006.175.07:31:08.43#ibcon#read 5, iclass 27, count 2 2006.175.07:31:08.43#ibcon#about to read 6, iclass 27, count 2 2006.175.07:31:08.43#ibcon#read 6, iclass 27, count 2 2006.175.07:31:08.43#ibcon#end of sib2, iclass 27, count 2 2006.175.07:31:08.43#ibcon#*after write, iclass 27, count 2 2006.175.07:31:08.43#ibcon#*before return 0, iclass 27, count 2 2006.175.07:31:08.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:08.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:08.43#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.07:31:08.43#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:08.43#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:08.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:08.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:08.55#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:31:08.55#ibcon#first serial, iclass 27, count 0 2006.175.07:31:08.55#ibcon#enter sib2, iclass 27, count 0 2006.175.07:31:08.55#ibcon#flushed, iclass 27, count 0 2006.175.07:31:08.55#ibcon#about to write, iclass 27, count 0 2006.175.07:31:08.55#ibcon#wrote, iclass 27, count 0 2006.175.07:31:08.55#ibcon#about to read 3, iclass 27, count 0 2006.175.07:31:08.57#ibcon#read 3, iclass 27, count 0 2006.175.07:31:08.57#ibcon#about to read 4, iclass 27, count 0 2006.175.07:31:08.57#ibcon#read 4, iclass 27, count 0 2006.175.07:31:08.57#ibcon#about to read 5, iclass 27, count 0 2006.175.07:31:08.57#ibcon#read 5, iclass 27, count 0 2006.175.07:31:08.57#ibcon#about to read 6, iclass 27, count 0 2006.175.07:31:08.57#ibcon#read 6, iclass 27, count 0 2006.175.07:31:08.57#ibcon#end of sib2, iclass 27, count 0 2006.175.07:31:08.57#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:31:08.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:31:08.57#ibcon#[25=USB\r\n] 2006.175.07:31:08.57#ibcon#*before write, iclass 27, count 0 2006.175.07:31:08.57#ibcon#enter sib2, iclass 27, count 0 2006.175.07:31:08.57#ibcon#flushed, iclass 27, count 0 2006.175.07:31:08.57#ibcon#about to write, iclass 27, count 0 2006.175.07:31:08.57#ibcon#wrote, iclass 27, count 0 2006.175.07:31:08.57#ibcon#about to read 3, iclass 27, count 0 2006.175.07:31:08.60#ibcon#read 3, iclass 27, count 0 2006.175.07:31:08.60#ibcon#about to read 4, iclass 27, count 0 2006.175.07:31:08.60#ibcon#read 4, iclass 27, count 0 2006.175.07:31:08.60#ibcon#about to read 5, iclass 27, count 0 2006.175.07:31:08.60#ibcon#read 5, iclass 27, count 0 2006.175.07:31:08.60#ibcon#about to read 6, iclass 27, count 0 2006.175.07:31:08.60#ibcon#read 6, iclass 27, count 0 2006.175.07:31:08.60#ibcon#end of sib2, iclass 27, count 0 2006.175.07:31:08.60#ibcon#*after write, iclass 27, count 0 2006.175.07:31:08.60#ibcon#*before return 0, iclass 27, count 0 2006.175.07:31:08.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:08.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:08.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:31:08.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:31:08.60$vc4f8/valo=3,672.99 2006.175.07:31:08.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.07:31:08.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.07:31:08.60#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:08.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:08.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:08.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:08.60#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:31:08.60#ibcon#first serial, iclass 29, count 0 2006.175.07:31:08.60#ibcon#enter sib2, iclass 29, count 0 2006.175.07:31:08.60#ibcon#flushed, iclass 29, count 0 2006.175.07:31:08.60#ibcon#about to write, iclass 29, count 0 2006.175.07:31:08.60#ibcon#wrote, iclass 29, count 0 2006.175.07:31:08.60#ibcon#about to read 3, iclass 29, count 0 2006.175.07:31:08.62#ibcon#read 3, iclass 29, count 0 2006.175.07:31:08.62#ibcon#about to read 4, iclass 29, count 0 2006.175.07:31:08.62#ibcon#read 4, iclass 29, count 0 2006.175.07:31:08.62#ibcon#about to read 5, iclass 29, count 0 2006.175.07:31:08.62#ibcon#read 5, iclass 29, count 0 2006.175.07:31:08.62#ibcon#about to read 6, iclass 29, count 0 2006.175.07:31:08.62#ibcon#read 6, iclass 29, count 0 2006.175.07:31:08.62#ibcon#end of sib2, iclass 29, count 0 2006.175.07:31:08.62#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:31:08.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:31:08.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:31:08.62#ibcon#*before write, iclass 29, count 0 2006.175.07:31:08.62#ibcon#enter sib2, iclass 29, count 0 2006.175.07:31:08.62#ibcon#flushed, iclass 29, count 0 2006.175.07:31:08.62#ibcon#about to write, iclass 29, count 0 2006.175.07:31:08.62#ibcon#wrote, iclass 29, count 0 2006.175.07:31:08.62#ibcon#about to read 3, iclass 29, count 0 2006.175.07:31:08.66#ibcon#read 3, iclass 29, count 0 2006.175.07:31:08.66#ibcon#about to read 4, iclass 29, count 0 2006.175.07:31:08.66#ibcon#read 4, iclass 29, count 0 2006.175.07:31:08.66#ibcon#about to read 5, iclass 29, count 0 2006.175.07:31:08.66#ibcon#read 5, iclass 29, count 0 2006.175.07:31:08.66#ibcon#about to read 6, iclass 29, count 0 2006.175.07:31:08.66#ibcon#read 6, iclass 29, count 0 2006.175.07:31:08.66#ibcon#end of sib2, iclass 29, count 0 2006.175.07:31:08.66#ibcon#*after write, iclass 29, count 0 2006.175.07:31:08.66#ibcon#*before return 0, iclass 29, count 0 2006.175.07:31:08.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:08.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:08.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:31:08.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:31:08.66$vc4f8/va=3,6 2006.175.07:31:08.66#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.07:31:08.66#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.07:31:08.66#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:08.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:08.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:08.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:08.72#ibcon#enter wrdev, iclass 31, count 2 2006.175.07:31:08.72#ibcon#first serial, iclass 31, count 2 2006.175.07:31:08.72#ibcon#enter sib2, iclass 31, count 2 2006.175.07:31:08.72#ibcon#flushed, iclass 31, count 2 2006.175.07:31:08.72#ibcon#about to write, iclass 31, count 2 2006.175.07:31:08.72#ibcon#wrote, iclass 31, count 2 2006.175.07:31:08.72#ibcon#about to read 3, iclass 31, count 2 2006.175.07:31:08.74#ibcon#read 3, iclass 31, count 2 2006.175.07:31:08.74#ibcon#about to read 4, iclass 31, count 2 2006.175.07:31:08.74#ibcon#read 4, iclass 31, count 2 2006.175.07:31:08.74#ibcon#about to read 5, iclass 31, count 2 2006.175.07:31:08.74#ibcon#read 5, iclass 31, count 2 2006.175.07:31:08.74#ibcon#about to read 6, iclass 31, count 2 2006.175.07:31:08.74#ibcon#read 6, iclass 31, count 2 2006.175.07:31:08.74#ibcon#end of sib2, iclass 31, count 2 2006.175.07:31:08.74#ibcon#*mode == 0, iclass 31, count 2 2006.175.07:31:08.74#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.07:31:08.74#ibcon#[25=AT03-06\r\n] 2006.175.07:31:08.74#ibcon#*before write, iclass 31, count 2 2006.175.07:31:08.74#ibcon#enter sib2, iclass 31, count 2 2006.175.07:31:08.74#ibcon#flushed, iclass 31, count 2 2006.175.07:31:08.74#ibcon#about to write, iclass 31, count 2 2006.175.07:31:08.74#ibcon#wrote, iclass 31, count 2 2006.175.07:31:08.74#ibcon#about to read 3, iclass 31, count 2 2006.175.07:31:08.77#ibcon#read 3, iclass 31, count 2 2006.175.07:31:08.77#ibcon#about to read 4, iclass 31, count 2 2006.175.07:31:08.77#ibcon#read 4, iclass 31, count 2 2006.175.07:31:08.77#ibcon#about to read 5, iclass 31, count 2 2006.175.07:31:08.77#ibcon#read 5, iclass 31, count 2 2006.175.07:31:08.77#ibcon#about to read 6, iclass 31, count 2 2006.175.07:31:08.77#ibcon#read 6, iclass 31, count 2 2006.175.07:31:08.77#ibcon#end of sib2, iclass 31, count 2 2006.175.07:31:08.77#ibcon#*after write, iclass 31, count 2 2006.175.07:31:08.77#ibcon#*before return 0, iclass 31, count 2 2006.175.07:31:08.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:08.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:08.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.07:31:08.77#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:08.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:08.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:08.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:08.89#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:31:08.89#ibcon#first serial, iclass 31, count 0 2006.175.07:31:08.89#ibcon#enter sib2, iclass 31, count 0 2006.175.07:31:08.89#ibcon#flushed, iclass 31, count 0 2006.175.07:31:08.89#ibcon#about to write, iclass 31, count 0 2006.175.07:31:08.89#ibcon#wrote, iclass 31, count 0 2006.175.07:31:08.89#ibcon#about to read 3, iclass 31, count 0 2006.175.07:31:08.91#ibcon#read 3, iclass 31, count 0 2006.175.07:31:08.91#ibcon#about to read 4, iclass 31, count 0 2006.175.07:31:08.91#ibcon#read 4, iclass 31, count 0 2006.175.07:31:08.91#ibcon#about to read 5, iclass 31, count 0 2006.175.07:31:08.91#ibcon#read 5, iclass 31, count 0 2006.175.07:31:08.91#ibcon#about to read 6, iclass 31, count 0 2006.175.07:31:08.91#ibcon#read 6, iclass 31, count 0 2006.175.07:31:08.91#ibcon#end of sib2, iclass 31, count 0 2006.175.07:31:08.91#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:31:08.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:31:08.91#ibcon#[25=USB\r\n] 2006.175.07:31:08.91#ibcon#*before write, iclass 31, count 0 2006.175.07:31:08.91#ibcon#enter sib2, iclass 31, count 0 2006.175.07:31:08.91#ibcon#flushed, iclass 31, count 0 2006.175.07:31:08.91#ibcon#about to write, iclass 31, count 0 2006.175.07:31:08.91#ibcon#wrote, iclass 31, count 0 2006.175.07:31:08.91#ibcon#about to read 3, iclass 31, count 0 2006.175.07:31:08.94#ibcon#read 3, iclass 31, count 0 2006.175.07:31:08.94#ibcon#about to read 4, iclass 31, count 0 2006.175.07:31:08.94#ibcon#read 4, iclass 31, count 0 2006.175.07:31:08.94#ibcon#about to read 5, iclass 31, count 0 2006.175.07:31:08.94#ibcon#read 5, iclass 31, count 0 2006.175.07:31:08.94#ibcon#about to read 6, iclass 31, count 0 2006.175.07:31:08.94#ibcon#read 6, iclass 31, count 0 2006.175.07:31:08.94#ibcon#end of sib2, iclass 31, count 0 2006.175.07:31:08.94#ibcon#*after write, iclass 31, count 0 2006.175.07:31:08.94#ibcon#*before return 0, iclass 31, count 0 2006.175.07:31:08.94#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:08.94#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:08.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:31:08.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:31:08.94$vc4f8/valo=4,832.99 2006.175.07:31:08.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.07:31:08.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.07:31:08.94#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:08.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:08.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:08.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:08.94#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:31:08.94#ibcon#first serial, iclass 33, count 0 2006.175.07:31:08.94#ibcon#enter sib2, iclass 33, count 0 2006.175.07:31:08.94#ibcon#flushed, iclass 33, count 0 2006.175.07:31:08.94#ibcon#about to write, iclass 33, count 0 2006.175.07:31:08.94#ibcon#wrote, iclass 33, count 0 2006.175.07:31:08.94#ibcon#about to read 3, iclass 33, count 0 2006.175.07:31:08.96#ibcon#read 3, iclass 33, count 0 2006.175.07:31:08.96#ibcon#about to read 4, iclass 33, count 0 2006.175.07:31:08.96#ibcon#read 4, iclass 33, count 0 2006.175.07:31:08.96#ibcon#about to read 5, iclass 33, count 0 2006.175.07:31:08.96#ibcon#read 5, iclass 33, count 0 2006.175.07:31:08.96#ibcon#about to read 6, iclass 33, count 0 2006.175.07:31:08.96#ibcon#read 6, iclass 33, count 0 2006.175.07:31:08.96#ibcon#end of sib2, iclass 33, count 0 2006.175.07:31:08.96#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:31:08.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:31:08.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:31:08.96#ibcon#*before write, iclass 33, count 0 2006.175.07:31:08.96#ibcon#enter sib2, iclass 33, count 0 2006.175.07:31:08.96#ibcon#flushed, iclass 33, count 0 2006.175.07:31:08.96#ibcon#about to write, iclass 33, count 0 2006.175.07:31:08.96#ibcon#wrote, iclass 33, count 0 2006.175.07:31:08.96#ibcon#about to read 3, iclass 33, count 0 2006.175.07:31:09.00#ibcon#read 3, iclass 33, count 0 2006.175.07:31:09.00#ibcon#about to read 4, iclass 33, count 0 2006.175.07:31:09.00#ibcon#read 4, iclass 33, count 0 2006.175.07:31:09.00#ibcon#about to read 5, iclass 33, count 0 2006.175.07:31:09.00#ibcon#read 5, iclass 33, count 0 2006.175.07:31:09.00#ibcon#about to read 6, iclass 33, count 0 2006.175.07:31:09.00#ibcon#read 6, iclass 33, count 0 2006.175.07:31:09.00#ibcon#end of sib2, iclass 33, count 0 2006.175.07:31:09.00#ibcon#*after write, iclass 33, count 0 2006.175.07:31:09.00#ibcon#*before return 0, iclass 33, count 0 2006.175.07:31:09.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:09.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:09.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:31:09.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:31:09.00$vc4f8/va=4,7 2006.175.07:31:09.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.175.07:31:09.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.175.07:31:09.00#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:09.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:09.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:09.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:09.06#ibcon#enter wrdev, iclass 35, count 2 2006.175.07:31:09.06#ibcon#first serial, iclass 35, count 2 2006.175.07:31:09.06#ibcon#enter sib2, iclass 35, count 2 2006.175.07:31:09.06#ibcon#flushed, iclass 35, count 2 2006.175.07:31:09.06#ibcon#about to write, iclass 35, count 2 2006.175.07:31:09.06#ibcon#wrote, iclass 35, count 2 2006.175.07:31:09.06#ibcon#about to read 3, iclass 35, count 2 2006.175.07:31:09.08#ibcon#read 3, iclass 35, count 2 2006.175.07:31:09.08#ibcon#about to read 4, iclass 35, count 2 2006.175.07:31:09.08#ibcon#read 4, iclass 35, count 2 2006.175.07:31:09.08#ibcon#about to read 5, iclass 35, count 2 2006.175.07:31:09.08#ibcon#read 5, iclass 35, count 2 2006.175.07:31:09.08#ibcon#about to read 6, iclass 35, count 2 2006.175.07:31:09.08#ibcon#read 6, iclass 35, count 2 2006.175.07:31:09.08#ibcon#end of sib2, iclass 35, count 2 2006.175.07:31:09.08#ibcon#*mode == 0, iclass 35, count 2 2006.175.07:31:09.08#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.175.07:31:09.08#ibcon#[25=AT04-07\r\n] 2006.175.07:31:09.08#ibcon#*before write, iclass 35, count 2 2006.175.07:31:09.08#ibcon#enter sib2, iclass 35, count 2 2006.175.07:31:09.08#ibcon#flushed, iclass 35, count 2 2006.175.07:31:09.08#ibcon#about to write, iclass 35, count 2 2006.175.07:31:09.08#ibcon#wrote, iclass 35, count 2 2006.175.07:31:09.08#ibcon#about to read 3, iclass 35, count 2 2006.175.07:31:09.11#ibcon#read 3, iclass 35, count 2 2006.175.07:31:09.11#ibcon#about to read 4, iclass 35, count 2 2006.175.07:31:09.11#ibcon#read 4, iclass 35, count 2 2006.175.07:31:09.11#ibcon#about to read 5, iclass 35, count 2 2006.175.07:31:09.11#ibcon#read 5, iclass 35, count 2 2006.175.07:31:09.11#ibcon#about to read 6, iclass 35, count 2 2006.175.07:31:09.11#ibcon#read 6, iclass 35, count 2 2006.175.07:31:09.11#ibcon#end of sib2, iclass 35, count 2 2006.175.07:31:09.11#ibcon#*after write, iclass 35, count 2 2006.175.07:31:09.11#ibcon#*before return 0, iclass 35, count 2 2006.175.07:31:09.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:09.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:09.11#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.175.07:31:09.11#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:09.11#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:09.23#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:09.23#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:09.23#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:31:09.23#ibcon#first serial, iclass 35, count 0 2006.175.07:31:09.23#ibcon#enter sib2, iclass 35, count 0 2006.175.07:31:09.23#ibcon#flushed, iclass 35, count 0 2006.175.07:31:09.23#ibcon#about to write, iclass 35, count 0 2006.175.07:31:09.23#ibcon#wrote, iclass 35, count 0 2006.175.07:31:09.23#ibcon#about to read 3, iclass 35, count 0 2006.175.07:31:09.25#ibcon#read 3, iclass 35, count 0 2006.175.07:31:09.25#ibcon#about to read 4, iclass 35, count 0 2006.175.07:31:09.25#ibcon#read 4, iclass 35, count 0 2006.175.07:31:09.25#ibcon#about to read 5, iclass 35, count 0 2006.175.07:31:09.25#ibcon#read 5, iclass 35, count 0 2006.175.07:31:09.25#ibcon#about to read 6, iclass 35, count 0 2006.175.07:31:09.25#ibcon#read 6, iclass 35, count 0 2006.175.07:31:09.25#ibcon#end of sib2, iclass 35, count 0 2006.175.07:31:09.25#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:31:09.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:31:09.25#ibcon#[25=USB\r\n] 2006.175.07:31:09.25#ibcon#*before write, iclass 35, count 0 2006.175.07:31:09.25#ibcon#enter sib2, iclass 35, count 0 2006.175.07:31:09.25#ibcon#flushed, iclass 35, count 0 2006.175.07:31:09.25#ibcon#about to write, iclass 35, count 0 2006.175.07:31:09.25#ibcon#wrote, iclass 35, count 0 2006.175.07:31:09.25#ibcon#about to read 3, iclass 35, count 0 2006.175.07:31:09.28#ibcon#read 3, iclass 35, count 0 2006.175.07:31:09.28#ibcon#about to read 4, iclass 35, count 0 2006.175.07:31:09.28#ibcon#read 4, iclass 35, count 0 2006.175.07:31:09.28#ibcon#about to read 5, iclass 35, count 0 2006.175.07:31:09.28#ibcon#read 5, iclass 35, count 0 2006.175.07:31:09.28#ibcon#about to read 6, iclass 35, count 0 2006.175.07:31:09.28#ibcon#read 6, iclass 35, count 0 2006.175.07:31:09.28#ibcon#end of sib2, iclass 35, count 0 2006.175.07:31:09.28#ibcon#*after write, iclass 35, count 0 2006.175.07:31:09.28#ibcon#*before return 0, iclass 35, count 0 2006.175.07:31:09.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:09.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:09.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:31:09.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:31:09.28$vc4f8/valo=5,652.99 2006.175.07:31:09.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.07:31:09.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.07:31:09.28#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:09.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:09.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:09.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:09.28#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:31:09.28#ibcon#first serial, iclass 37, count 0 2006.175.07:31:09.28#ibcon#enter sib2, iclass 37, count 0 2006.175.07:31:09.28#ibcon#flushed, iclass 37, count 0 2006.175.07:31:09.28#ibcon#about to write, iclass 37, count 0 2006.175.07:31:09.28#ibcon#wrote, iclass 37, count 0 2006.175.07:31:09.28#ibcon#about to read 3, iclass 37, count 0 2006.175.07:31:09.30#ibcon#read 3, iclass 37, count 0 2006.175.07:31:09.30#ibcon#about to read 4, iclass 37, count 0 2006.175.07:31:09.30#ibcon#read 4, iclass 37, count 0 2006.175.07:31:09.30#ibcon#about to read 5, iclass 37, count 0 2006.175.07:31:09.30#ibcon#read 5, iclass 37, count 0 2006.175.07:31:09.30#ibcon#about to read 6, iclass 37, count 0 2006.175.07:31:09.30#ibcon#read 6, iclass 37, count 0 2006.175.07:31:09.30#ibcon#end of sib2, iclass 37, count 0 2006.175.07:31:09.30#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:31:09.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:31:09.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:31:09.30#ibcon#*before write, iclass 37, count 0 2006.175.07:31:09.30#ibcon#enter sib2, iclass 37, count 0 2006.175.07:31:09.30#ibcon#flushed, iclass 37, count 0 2006.175.07:31:09.30#ibcon#about to write, iclass 37, count 0 2006.175.07:31:09.30#ibcon#wrote, iclass 37, count 0 2006.175.07:31:09.30#ibcon#about to read 3, iclass 37, count 0 2006.175.07:31:09.34#ibcon#read 3, iclass 37, count 0 2006.175.07:31:09.34#ibcon#about to read 4, iclass 37, count 0 2006.175.07:31:09.34#ibcon#read 4, iclass 37, count 0 2006.175.07:31:09.34#ibcon#about to read 5, iclass 37, count 0 2006.175.07:31:09.34#ibcon#read 5, iclass 37, count 0 2006.175.07:31:09.34#ibcon#about to read 6, iclass 37, count 0 2006.175.07:31:09.34#ibcon#read 6, iclass 37, count 0 2006.175.07:31:09.34#ibcon#end of sib2, iclass 37, count 0 2006.175.07:31:09.34#ibcon#*after write, iclass 37, count 0 2006.175.07:31:09.34#ibcon#*before return 0, iclass 37, count 0 2006.175.07:31:09.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:09.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:09.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:31:09.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:31:09.34$vc4f8/va=5,7 2006.175.07:31:09.34#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.175.07:31:09.34#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.175.07:31:09.34#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:09.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:09.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:09.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:09.40#ibcon#enter wrdev, iclass 39, count 2 2006.175.07:31:09.40#ibcon#first serial, iclass 39, count 2 2006.175.07:31:09.40#ibcon#enter sib2, iclass 39, count 2 2006.175.07:31:09.40#ibcon#flushed, iclass 39, count 2 2006.175.07:31:09.40#ibcon#about to write, iclass 39, count 2 2006.175.07:31:09.40#ibcon#wrote, iclass 39, count 2 2006.175.07:31:09.40#ibcon#about to read 3, iclass 39, count 2 2006.175.07:31:09.42#ibcon#read 3, iclass 39, count 2 2006.175.07:31:09.42#ibcon#about to read 4, iclass 39, count 2 2006.175.07:31:09.42#ibcon#read 4, iclass 39, count 2 2006.175.07:31:09.42#ibcon#about to read 5, iclass 39, count 2 2006.175.07:31:09.42#ibcon#read 5, iclass 39, count 2 2006.175.07:31:09.42#ibcon#about to read 6, iclass 39, count 2 2006.175.07:31:09.42#ibcon#read 6, iclass 39, count 2 2006.175.07:31:09.42#ibcon#end of sib2, iclass 39, count 2 2006.175.07:31:09.42#ibcon#*mode == 0, iclass 39, count 2 2006.175.07:31:09.42#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.175.07:31:09.42#ibcon#[25=AT05-07\r\n] 2006.175.07:31:09.42#ibcon#*before write, iclass 39, count 2 2006.175.07:31:09.42#ibcon#enter sib2, iclass 39, count 2 2006.175.07:31:09.42#ibcon#flushed, iclass 39, count 2 2006.175.07:31:09.42#ibcon#about to write, iclass 39, count 2 2006.175.07:31:09.42#ibcon#wrote, iclass 39, count 2 2006.175.07:31:09.42#ibcon#about to read 3, iclass 39, count 2 2006.175.07:31:09.45#ibcon#read 3, iclass 39, count 2 2006.175.07:31:09.45#ibcon#about to read 4, iclass 39, count 2 2006.175.07:31:09.45#ibcon#read 4, iclass 39, count 2 2006.175.07:31:09.45#ibcon#about to read 5, iclass 39, count 2 2006.175.07:31:09.45#ibcon#read 5, iclass 39, count 2 2006.175.07:31:09.45#ibcon#about to read 6, iclass 39, count 2 2006.175.07:31:09.45#ibcon#read 6, iclass 39, count 2 2006.175.07:31:09.45#ibcon#end of sib2, iclass 39, count 2 2006.175.07:31:09.45#ibcon#*after write, iclass 39, count 2 2006.175.07:31:09.45#ibcon#*before return 0, iclass 39, count 2 2006.175.07:31:09.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:09.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:09.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.175.07:31:09.45#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:09.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:09.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:09.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:09.57#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:31:09.57#ibcon#first serial, iclass 39, count 0 2006.175.07:31:09.57#ibcon#enter sib2, iclass 39, count 0 2006.175.07:31:09.57#ibcon#flushed, iclass 39, count 0 2006.175.07:31:09.57#ibcon#about to write, iclass 39, count 0 2006.175.07:31:09.57#ibcon#wrote, iclass 39, count 0 2006.175.07:31:09.57#ibcon#about to read 3, iclass 39, count 0 2006.175.07:31:09.59#ibcon#read 3, iclass 39, count 0 2006.175.07:31:09.59#ibcon#about to read 4, iclass 39, count 0 2006.175.07:31:09.59#ibcon#read 4, iclass 39, count 0 2006.175.07:31:09.59#ibcon#about to read 5, iclass 39, count 0 2006.175.07:31:09.59#ibcon#read 5, iclass 39, count 0 2006.175.07:31:09.59#ibcon#about to read 6, iclass 39, count 0 2006.175.07:31:09.59#ibcon#read 6, iclass 39, count 0 2006.175.07:31:09.59#ibcon#end of sib2, iclass 39, count 0 2006.175.07:31:09.59#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:31:09.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:31:09.59#ibcon#[25=USB\r\n] 2006.175.07:31:09.59#ibcon#*before write, iclass 39, count 0 2006.175.07:31:09.59#ibcon#enter sib2, iclass 39, count 0 2006.175.07:31:09.59#ibcon#flushed, iclass 39, count 0 2006.175.07:31:09.59#ibcon#about to write, iclass 39, count 0 2006.175.07:31:09.59#ibcon#wrote, iclass 39, count 0 2006.175.07:31:09.59#ibcon#about to read 3, iclass 39, count 0 2006.175.07:31:09.62#ibcon#read 3, iclass 39, count 0 2006.175.07:31:09.62#ibcon#about to read 4, iclass 39, count 0 2006.175.07:31:09.62#ibcon#read 4, iclass 39, count 0 2006.175.07:31:09.62#ibcon#about to read 5, iclass 39, count 0 2006.175.07:31:09.62#ibcon#read 5, iclass 39, count 0 2006.175.07:31:09.62#ibcon#about to read 6, iclass 39, count 0 2006.175.07:31:09.62#ibcon#read 6, iclass 39, count 0 2006.175.07:31:09.62#ibcon#end of sib2, iclass 39, count 0 2006.175.07:31:09.62#ibcon#*after write, iclass 39, count 0 2006.175.07:31:09.62#ibcon#*before return 0, iclass 39, count 0 2006.175.07:31:09.62#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:09.62#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:09.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:31:09.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:31:09.62$vc4f8/valo=6,772.99 2006.175.07:31:09.62#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.07:31:09.62#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.07:31:09.62#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:09.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:09.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:09.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:09.62#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:31:09.62#ibcon#first serial, iclass 3, count 0 2006.175.07:31:09.62#ibcon#enter sib2, iclass 3, count 0 2006.175.07:31:09.62#ibcon#flushed, iclass 3, count 0 2006.175.07:31:09.62#ibcon#about to write, iclass 3, count 0 2006.175.07:31:09.62#ibcon#wrote, iclass 3, count 0 2006.175.07:31:09.62#ibcon#about to read 3, iclass 3, count 0 2006.175.07:31:09.64#ibcon#read 3, iclass 3, count 0 2006.175.07:31:09.64#ibcon#about to read 4, iclass 3, count 0 2006.175.07:31:09.64#ibcon#read 4, iclass 3, count 0 2006.175.07:31:09.64#ibcon#about to read 5, iclass 3, count 0 2006.175.07:31:09.64#ibcon#read 5, iclass 3, count 0 2006.175.07:31:09.64#ibcon#about to read 6, iclass 3, count 0 2006.175.07:31:09.64#ibcon#read 6, iclass 3, count 0 2006.175.07:31:09.64#ibcon#end of sib2, iclass 3, count 0 2006.175.07:31:09.64#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:31:09.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:31:09.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:31:09.64#ibcon#*before write, iclass 3, count 0 2006.175.07:31:09.64#ibcon#enter sib2, iclass 3, count 0 2006.175.07:31:09.64#ibcon#flushed, iclass 3, count 0 2006.175.07:31:09.64#ibcon#about to write, iclass 3, count 0 2006.175.07:31:09.64#ibcon#wrote, iclass 3, count 0 2006.175.07:31:09.64#ibcon#about to read 3, iclass 3, count 0 2006.175.07:31:09.68#ibcon#read 3, iclass 3, count 0 2006.175.07:31:09.68#ibcon#about to read 4, iclass 3, count 0 2006.175.07:31:09.68#ibcon#read 4, iclass 3, count 0 2006.175.07:31:09.68#ibcon#about to read 5, iclass 3, count 0 2006.175.07:31:09.68#ibcon#read 5, iclass 3, count 0 2006.175.07:31:09.68#ibcon#about to read 6, iclass 3, count 0 2006.175.07:31:09.68#ibcon#read 6, iclass 3, count 0 2006.175.07:31:09.68#ibcon#end of sib2, iclass 3, count 0 2006.175.07:31:09.68#ibcon#*after write, iclass 3, count 0 2006.175.07:31:09.68#ibcon#*before return 0, iclass 3, count 0 2006.175.07:31:09.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:09.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:09.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:31:09.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:31:09.68$vc4f8/va=6,6 2006.175.07:31:09.68#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.175.07:31:09.68#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.175.07:31:09.68#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:09.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:09.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:09.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:09.74#ibcon#enter wrdev, iclass 5, count 2 2006.175.07:31:09.74#ibcon#first serial, iclass 5, count 2 2006.175.07:31:09.74#ibcon#enter sib2, iclass 5, count 2 2006.175.07:31:09.74#ibcon#flushed, iclass 5, count 2 2006.175.07:31:09.74#ibcon#about to write, iclass 5, count 2 2006.175.07:31:09.74#ibcon#wrote, iclass 5, count 2 2006.175.07:31:09.74#ibcon#about to read 3, iclass 5, count 2 2006.175.07:31:09.76#ibcon#read 3, iclass 5, count 2 2006.175.07:31:09.76#ibcon#about to read 4, iclass 5, count 2 2006.175.07:31:09.76#ibcon#read 4, iclass 5, count 2 2006.175.07:31:09.76#ibcon#about to read 5, iclass 5, count 2 2006.175.07:31:09.76#ibcon#read 5, iclass 5, count 2 2006.175.07:31:09.76#ibcon#about to read 6, iclass 5, count 2 2006.175.07:31:09.76#ibcon#read 6, iclass 5, count 2 2006.175.07:31:09.76#ibcon#end of sib2, iclass 5, count 2 2006.175.07:31:09.76#ibcon#*mode == 0, iclass 5, count 2 2006.175.07:31:09.76#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.175.07:31:09.76#ibcon#[25=AT06-06\r\n] 2006.175.07:31:09.76#ibcon#*before write, iclass 5, count 2 2006.175.07:31:09.76#ibcon#enter sib2, iclass 5, count 2 2006.175.07:31:09.76#ibcon#flushed, iclass 5, count 2 2006.175.07:31:09.76#ibcon#about to write, iclass 5, count 2 2006.175.07:31:09.76#ibcon#wrote, iclass 5, count 2 2006.175.07:31:09.76#ibcon#about to read 3, iclass 5, count 2 2006.175.07:31:09.79#ibcon#read 3, iclass 5, count 2 2006.175.07:31:09.79#ibcon#about to read 4, iclass 5, count 2 2006.175.07:31:09.79#ibcon#read 4, iclass 5, count 2 2006.175.07:31:09.79#ibcon#about to read 5, iclass 5, count 2 2006.175.07:31:09.79#ibcon#read 5, iclass 5, count 2 2006.175.07:31:09.79#ibcon#about to read 6, iclass 5, count 2 2006.175.07:31:09.79#ibcon#read 6, iclass 5, count 2 2006.175.07:31:09.79#ibcon#end of sib2, iclass 5, count 2 2006.175.07:31:09.79#ibcon#*after write, iclass 5, count 2 2006.175.07:31:09.79#ibcon#*before return 0, iclass 5, count 2 2006.175.07:31:09.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:09.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:09.79#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.175.07:31:09.79#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:09.79#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:09.91#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:09.91#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:09.91#ibcon#enter wrdev, iclass 5, count 0 2006.175.07:31:09.91#ibcon#first serial, iclass 5, count 0 2006.175.07:31:09.91#ibcon#enter sib2, iclass 5, count 0 2006.175.07:31:09.91#ibcon#flushed, iclass 5, count 0 2006.175.07:31:09.91#ibcon#about to write, iclass 5, count 0 2006.175.07:31:09.91#ibcon#wrote, iclass 5, count 0 2006.175.07:31:09.91#ibcon#about to read 3, iclass 5, count 0 2006.175.07:31:09.93#ibcon#read 3, iclass 5, count 0 2006.175.07:31:09.93#ibcon#about to read 4, iclass 5, count 0 2006.175.07:31:09.93#ibcon#read 4, iclass 5, count 0 2006.175.07:31:09.93#ibcon#about to read 5, iclass 5, count 0 2006.175.07:31:09.93#ibcon#read 5, iclass 5, count 0 2006.175.07:31:09.93#ibcon#about to read 6, iclass 5, count 0 2006.175.07:31:09.93#ibcon#read 6, iclass 5, count 0 2006.175.07:31:09.93#ibcon#end of sib2, iclass 5, count 0 2006.175.07:31:09.93#ibcon#*mode == 0, iclass 5, count 0 2006.175.07:31:09.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.07:31:09.93#ibcon#[25=USB\r\n] 2006.175.07:31:09.93#ibcon#*before write, iclass 5, count 0 2006.175.07:31:09.93#ibcon#enter sib2, iclass 5, count 0 2006.175.07:31:09.93#ibcon#flushed, iclass 5, count 0 2006.175.07:31:09.93#ibcon#about to write, iclass 5, count 0 2006.175.07:31:09.93#ibcon#wrote, iclass 5, count 0 2006.175.07:31:09.93#ibcon#about to read 3, iclass 5, count 0 2006.175.07:31:09.96#ibcon#read 3, iclass 5, count 0 2006.175.07:31:09.96#ibcon#about to read 4, iclass 5, count 0 2006.175.07:31:09.96#ibcon#read 4, iclass 5, count 0 2006.175.07:31:09.96#ibcon#about to read 5, iclass 5, count 0 2006.175.07:31:09.96#ibcon#read 5, iclass 5, count 0 2006.175.07:31:09.96#ibcon#about to read 6, iclass 5, count 0 2006.175.07:31:09.96#ibcon#read 6, iclass 5, count 0 2006.175.07:31:09.96#ibcon#end of sib2, iclass 5, count 0 2006.175.07:31:09.96#ibcon#*after write, iclass 5, count 0 2006.175.07:31:09.96#ibcon#*before return 0, iclass 5, count 0 2006.175.07:31:09.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:09.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:09.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.07:31:09.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.07:31:09.96$vc4f8/valo=7,832.99 2006.175.07:31:09.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.07:31:09.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.07:31:09.96#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:09.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:09.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:09.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:09.96#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:31:09.96#ibcon#first serial, iclass 7, count 0 2006.175.07:31:09.96#ibcon#enter sib2, iclass 7, count 0 2006.175.07:31:09.96#ibcon#flushed, iclass 7, count 0 2006.175.07:31:09.96#ibcon#about to write, iclass 7, count 0 2006.175.07:31:09.96#ibcon#wrote, iclass 7, count 0 2006.175.07:31:09.96#ibcon#about to read 3, iclass 7, count 0 2006.175.07:31:09.98#ibcon#read 3, iclass 7, count 0 2006.175.07:31:09.98#ibcon#about to read 4, iclass 7, count 0 2006.175.07:31:09.98#ibcon#read 4, iclass 7, count 0 2006.175.07:31:09.98#ibcon#about to read 5, iclass 7, count 0 2006.175.07:31:09.98#ibcon#read 5, iclass 7, count 0 2006.175.07:31:09.98#ibcon#about to read 6, iclass 7, count 0 2006.175.07:31:09.98#ibcon#read 6, iclass 7, count 0 2006.175.07:31:09.98#ibcon#end of sib2, iclass 7, count 0 2006.175.07:31:09.98#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:31:09.98#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:31:09.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:31:09.98#ibcon#*before write, iclass 7, count 0 2006.175.07:31:09.98#ibcon#enter sib2, iclass 7, count 0 2006.175.07:31:09.98#ibcon#flushed, iclass 7, count 0 2006.175.07:31:09.98#ibcon#about to write, iclass 7, count 0 2006.175.07:31:09.98#ibcon#wrote, iclass 7, count 0 2006.175.07:31:09.98#ibcon#about to read 3, iclass 7, count 0 2006.175.07:31:10.02#ibcon#read 3, iclass 7, count 0 2006.175.07:31:10.02#ibcon#about to read 4, iclass 7, count 0 2006.175.07:31:10.02#ibcon#read 4, iclass 7, count 0 2006.175.07:31:10.02#ibcon#about to read 5, iclass 7, count 0 2006.175.07:31:10.02#ibcon#read 5, iclass 7, count 0 2006.175.07:31:10.02#ibcon#about to read 6, iclass 7, count 0 2006.175.07:31:10.02#ibcon#read 6, iclass 7, count 0 2006.175.07:31:10.02#ibcon#end of sib2, iclass 7, count 0 2006.175.07:31:10.02#ibcon#*after write, iclass 7, count 0 2006.175.07:31:10.02#ibcon#*before return 0, iclass 7, count 0 2006.175.07:31:10.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:10.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:10.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:31:10.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:31:10.02$vc4f8/va=7,6 2006.175.07:31:10.02#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.07:31:10.02#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.07:31:10.02#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:10.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:31:10.06#abcon#<5=/04 4.3 7.4 26.06 691007.4\r\n> 2006.175.07:31:10.08#abcon#{5=INTERFACE CLEAR} 2006.175.07:31:10.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:31:10.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:31:10.08#ibcon#enter wrdev, iclass 12, count 2 2006.175.07:31:10.08#ibcon#first serial, iclass 12, count 2 2006.175.07:31:10.08#ibcon#enter sib2, iclass 12, count 2 2006.175.07:31:10.08#ibcon#flushed, iclass 12, count 2 2006.175.07:31:10.08#ibcon#about to write, iclass 12, count 2 2006.175.07:31:10.08#ibcon#wrote, iclass 12, count 2 2006.175.07:31:10.08#ibcon#about to read 3, iclass 12, count 2 2006.175.07:31:10.10#ibcon#read 3, iclass 12, count 2 2006.175.07:31:10.10#ibcon#about to read 4, iclass 12, count 2 2006.175.07:31:10.10#ibcon#read 4, iclass 12, count 2 2006.175.07:31:10.10#ibcon#about to read 5, iclass 12, count 2 2006.175.07:31:10.10#ibcon#read 5, iclass 12, count 2 2006.175.07:31:10.10#ibcon#about to read 6, iclass 12, count 2 2006.175.07:31:10.10#ibcon#read 6, iclass 12, count 2 2006.175.07:31:10.10#ibcon#end of sib2, iclass 12, count 2 2006.175.07:31:10.10#ibcon#*mode == 0, iclass 12, count 2 2006.175.07:31:10.10#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.07:31:10.10#ibcon#[25=AT07-06\r\n] 2006.175.07:31:10.10#ibcon#*before write, iclass 12, count 2 2006.175.07:31:10.10#ibcon#enter sib2, iclass 12, count 2 2006.175.07:31:10.10#ibcon#flushed, iclass 12, count 2 2006.175.07:31:10.10#ibcon#about to write, iclass 12, count 2 2006.175.07:31:10.10#ibcon#wrote, iclass 12, count 2 2006.175.07:31:10.10#ibcon#about to read 3, iclass 12, count 2 2006.175.07:31:10.13#ibcon#read 3, iclass 12, count 2 2006.175.07:31:10.13#ibcon#about to read 4, iclass 12, count 2 2006.175.07:31:10.13#ibcon#read 4, iclass 12, count 2 2006.175.07:31:10.13#ibcon#about to read 5, iclass 12, count 2 2006.175.07:31:10.13#ibcon#read 5, iclass 12, count 2 2006.175.07:31:10.13#ibcon#about to read 6, iclass 12, count 2 2006.175.07:31:10.13#ibcon#read 6, iclass 12, count 2 2006.175.07:31:10.13#ibcon#end of sib2, iclass 12, count 2 2006.175.07:31:10.13#ibcon#*after write, iclass 12, count 2 2006.175.07:31:10.13#ibcon#*before return 0, iclass 12, count 2 2006.175.07:31:10.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:31:10.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:31:10.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.07:31:10.13#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:10.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:31:10.14#abcon#[5=S1D000X0/0*\r\n] 2006.175.07:31:10.26#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:31:10.26#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:31:10.26#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:31:10.26#ibcon#first serial, iclass 12, count 0 2006.175.07:31:10.26#ibcon#enter sib2, iclass 12, count 0 2006.175.07:31:10.26#ibcon#flushed, iclass 12, count 0 2006.175.07:31:10.26#ibcon#about to write, iclass 12, count 0 2006.175.07:31:10.26#ibcon#wrote, iclass 12, count 0 2006.175.07:31:10.26#ibcon#about to read 3, iclass 12, count 0 2006.175.07:31:10.27#ibcon#read 3, iclass 12, count 0 2006.175.07:31:10.27#ibcon#about to read 4, iclass 12, count 0 2006.175.07:31:10.27#ibcon#read 4, iclass 12, count 0 2006.175.07:31:10.27#ibcon#about to read 5, iclass 12, count 0 2006.175.07:31:10.27#ibcon#read 5, iclass 12, count 0 2006.175.07:31:10.27#ibcon#about to read 6, iclass 12, count 0 2006.175.07:31:10.27#ibcon#read 6, iclass 12, count 0 2006.175.07:31:10.27#ibcon#end of sib2, iclass 12, count 0 2006.175.07:31:10.27#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:31:10.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:31:10.27#ibcon#[25=USB\r\n] 2006.175.07:31:10.27#ibcon#*before write, iclass 12, count 0 2006.175.07:31:10.27#ibcon#enter sib2, iclass 12, count 0 2006.175.07:31:10.27#ibcon#flushed, iclass 12, count 0 2006.175.07:31:10.27#ibcon#about to write, iclass 12, count 0 2006.175.07:31:10.27#ibcon#wrote, iclass 12, count 0 2006.175.07:31:10.27#ibcon#about to read 3, iclass 12, count 0 2006.175.07:31:10.31#ibcon#read 3, iclass 12, count 0 2006.175.07:31:10.31#ibcon#about to read 4, iclass 12, count 0 2006.175.07:31:10.31#ibcon#read 4, iclass 12, count 0 2006.175.07:31:10.31#ibcon#about to read 5, iclass 12, count 0 2006.175.07:31:10.31#ibcon#read 5, iclass 12, count 0 2006.175.07:31:10.31#ibcon#about to read 6, iclass 12, count 0 2006.175.07:31:10.31#ibcon#read 6, iclass 12, count 0 2006.175.07:31:10.31#ibcon#end of sib2, iclass 12, count 0 2006.175.07:31:10.31#ibcon#*after write, iclass 12, count 0 2006.175.07:31:10.31#ibcon#*before return 0, iclass 12, count 0 2006.175.07:31:10.31#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:31:10.31#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:31:10.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:31:10.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:31:10.31$vc4f8/valo=8,852.99 2006.175.07:31:10.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.07:31:10.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.07:31:10.31#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:10.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:31:10.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:31:10.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:31:10.31#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:31:10.31#ibcon#first serial, iclass 17, count 0 2006.175.07:31:10.31#ibcon#enter sib2, iclass 17, count 0 2006.175.07:31:10.31#ibcon#flushed, iclass 17, count 0 2006.175.07:31:10.31#ibcon#about to write, iclass 17, count 0 2006.175.07:31:10.31#ibcon#wrote, iclass 17, count 0 2006.175.07:31:10.31#ibcon#about to read 3, iclass 17, count 0 2006.175.07:31:10.33#ibcon#read 3, iclass 17, count 0 2006.175.07:31:10.33#ibcon#about to read 4, iclass 17, count 0 2006.175.07:31:10.33#ibcon#read 4, iclass 17, count 0 2006.175.07:31:10.33#ibcon#about to read 5, iclass 17, count 0 2006.175.07:31:10.33#ibcon#read 5, iclass 17, count 0 2006.175.07:31:10.33#ibcon#about to read 6, iclass 17, count 0 2006.175.07:31:10.33#ibcon#read 6, iclass 17, count 0 2006.175.07:31:10.33#ibcon#end of sib2, iclass 17, count 0 2006.175.07:31:10.33#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:31:10.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:31:10.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:31:10.33#ibcon#*before write, iclass 17, count 0 2006.175.07:31:10.33#ibcon#enter sib2, iclass 17, count 0 2006.175.07:31:10.33#ibcon#flushed, iclass 17, count 0 2006.175.07:31:10.33#ibcon#about to write, iclass 17, count 0 2006.175.07:31:10.33#ibcon#wrote, iclass 17, count 0 2006.175.07:31:10.33#ibcon#about to read 3, iclass 17, count 0 2006.175.07:31:10.37#ibcon#read 3, iclass 17, count 0 2006.175.07:31:10.37#ibcon#about to read 4, iclass 17, count 0 2006.175.07:31:10.37#ibcon#read 4, iclass 17, count 0 2006.175.07:31:10.37#ibcon#about to read 5, iclass 17, count 0 2006.175.07:31:10.37#ibcon#read 5, iclass 17, count 0 2006.175.07:31:10.37#ibcon#about to read 6, iclass 17, count 0 2006.175.07:31:10.37#ibcon#read 6, iclass 17, count 0 2006.175.07:31:10.37#ibcon#end of sib2, iclass 17, count 0 2006.175.07:31:10.37#ibcon#*after write, iclass 17, count 0 2006.175.07:31:10.37#ibcon#*before return 0, iclass 17, count 0 2006.175.07:31:10.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:31:10.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:31:10.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:31:10.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:31:10.37$vc4f8/va=8,6 2006.175.07:31:10.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.175.07:31:10.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.175.07:31:10.37#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:10.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:31:10.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:31:10.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:31:10.43#ibcon#enter wrdev, iclass 19, count 2 2006.175.07:31:10.43#ibcon#first serial, iclass 19, count 2 2006.175.07:31:10.43#ibcon#enter sib2, iclass 19, count 2 2006.175.07:31:10.43#ibcon#flushed, iclass 19, count 2 2006.175.07:31:10.43#ibcon#about to write, iclass 19, count 2 2006.175.07:31:10.43#ibcon#wrote, iclass 19, count 2 2006.175.07:31:10.43#ibcon#about to read 3, iclass 19, count 2 2006.175.07:31:10.45#ibcon#read 3, iclass 19, count 2 2006.175.07:31:10.45#ibcon#about to read 4, iclass 19, count 2 2006.175.07:31:10.45#ibcon#read 4, iclass 19, count 2 2006.175.07:31:10.45#ibcon#about to read 5, iclass 19, count 2 2006.175.07:31:10.45#ibcon#read 5, iclass 19, count 2 2006.175.07:31:10.45#ibcon#about to read 6, iclass 19, count 2 2006.175.07:31:10.45#ibcon#read 6, iclass 19, count 2 2006.175.07:31:10.45#ibcon#end of sib2, iclass 19, count 2 2006.175.07:31:10.45#ibcon#*mode == 0, iclass 19, count 2 2006.175.07:31:10.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.175.07:31:10.45#ibcon#[25=AT08-06\r\n] 2006.175.07:31:10.45#ibcon#*before write, iclass 19, count 2 2006.175.07:31:10.45#ibcon#enter sib2, iclass 19, count 2 2006.175.07:31:10.45#ibcon#flushed, iclass 19, count 2 2006.175.07:31:10.45#ibcon#about to write, iclass 19, count 2 2006.175.07:31:10.45#ibcon#wrote, iclass 19, count 2 2006.175.07:31:10.45#ibcon#about to read 3, iclass 19, count 2 2006.175.07:31:10.48#ibcon#read 3, iclass 19, count 2 2006.175.07:31:10.48#ibcon#about to read 4, iclass 19, count 2 2006.175.07:31:10.48#ibcon#read 4, iclass 19, count 2 2006.175.07:31:10.48#ibcon#about to read 5, iclass 19, count 2 2006.175.07:31:10.48#ibcon#read 5, iclass 19, count 2 2006.175.07:31:10.48#ibcon#about to read 6, iclass 19, count 2 2006.175.07:31:10.48#ibcon#read 6, iclass 19, count 2 2006.175.07:31:10.48#ibcon#end of sib2, iclass 19, count 2 2006.175.07:31:10.48#ibcon#*after write, iclass 19, count 2 2006.175.07:31:10.48#ibcon#*before return 0, iclass 19, count 2 2006.175.07:31:10.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:31:10.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:31:10.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.175.07:31:10.48#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:10.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:31:10.60#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:31:10.60#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:31:10.60#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:31:10.60#ibcon#first serial, iclass 19, count 0 2006.175.07:31:10.60#ibcon#enter sib2, iclass 19, count 0 2006.175.07:31:10.60#ibcon#flushed, iclass 19, count 0 2006.175.07:31:10.60#ibcon#about to write, iclass 19, count 0 2006.175.07:31:10.60#ibcon#wrote, iclass 19, count 0 2006.175.07:31:10.60#ibcon#about to read 3, iclass 19, count 0 2006.175.07:31:10.62#ibcon#read 3, iclass 19, count 0 2006.175.07:31:10.62#ibcon#about to read 4, iclass 19, count 0 2006.175.07:31:10.62#ibcon#read 4, iclass 19, count 0 2006.175.07:31:10.62#ibcon#about to read 5, iclass 19, count 0 2006.175.07:31:10.62#ibcon#read 5, iclass 19, count 0 2006.175.07:31:10.62#ibcon#about to read 6, iclass 19, count 0 2006.175.07:31:10.62#ibcon#read 6, iclass 19, count 0 2006.175.07:31:10.62#ibcon#end of sib2, iclass 19, count 0 2006.175.07:31:10.62#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:31:10.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:31:10.62#ibcon#[25=USB\r\n] 2006.175.07:31:10.62#ibcon#*before write, iclass 19, count 0 2006.175.07:31:10.62#ibcon#enter sib2, iclass 19, count 0 2006.175.07:31:10.62#ibcon#flushed, iclass 19, count 0 2006.175.07:31:10.62#ibcon#about to write, iclass 19, count 0 2006.175.07:31:10.62#ibcon#wrote, iclass 19, count 0 2006.175.07:31:10.62#ibcon#about to read 3, iclass 19, count 0 2006.175.07:31:10.65#ibcon#read 3, iclass 19, count 0 2006.175.07:31:10.65#ibcon#about to read 4, iclass 19, count 0 2006.175.07:31:10.65#ibcon#read 4, iclass 19, count 0 2006.175.07:31:10.65#ibcon#about to read 5, iclass 19, count 0 2006.175.07:31:10.65#ibcon#read 5, iclass 19, count 0 2006.175.07:31:10.65#ibcon#about to read 6, iclass 19, count 0 2006.175.07:31:10.65#ibcon#read 6, iclass 19, count 0 2006.175.07:31:10.65#ibcon#end of sib2, iclass 19, count 0 2006.175.07:31:10.65#ibcon#*after write, iclass 19, count 0 2006.175.07:31:10.65#ibcon#*before return 0, iclass 19, count 0 2006.175.07:31:10.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:31:10.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:31:10.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:31:10.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:31:10.65$vc4f8/vblo=1,632.99 2006.175.07:31:10.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.07:31:10.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.07:31:10.65#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:10.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:10.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:10.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:10.65#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:31:10.65#ibcon#first serial, iclass 21, count 0 2006.175.07:31:10.65#ibcon#enter sib2, iclass 21, count 0 2006.175.07:31:10.65#ibcon#flushed, iclass 21, count 0 2006.175.07:31:10.65#ibcon#about to write, iclass 21, count 0 2006.175.07:31:10.65#ibcon#wrote, iclass 21, count 0 2006.175.07:31:10.65#ibcon#about to read 3, iclass 21, count 0 2006.175.07:31:10.67#ibcon#read 3, iclass 21, count 0 2006.175.07:31:10.67#ibcon#about to read 4, iclass 21, count 0 2006.175.07:31:10.67#ibcon#read 4, iclass 21, count 0 2006.175.07:31:10.67#ibcon#about to read 5, iclass 21, count 0 2006.175.07:31:10.67#ibcon#read 5, iclass 21, count 0 2006.175.07:31:10.67#ibcon#about to read 6, iclass 21, count 0 2006.175.07:31:10.67#ibcon#read 6, iclass 21, count 0 2006.175.07:31:10.67#ibcon#end of sib2, iclass 21, count 0 2006.175.07:31:10.67#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:31:10.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:31:10.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:31:10.67#ibcon#*before write, iclass 21, count 0 2006.175.07:31:10.67#ibcon#enter sib2, iclass 21, count 0 2006.175.07:31:10.67#ibcon#flushed, iclass 21, count 0 2006.175.07:31:10.67#ibcon#about to write, iclass 21, count 0 2006.175.07:31:10.67#ibcon#wrote, iclass 21, count 0 2006.175.07:31:10.67#ibcon#about to read 3, iclass 21, count 0 2006.175.07:31:10.72#ibcon#read 3, iclass 21, count 0 2006.175.07:31:10.72#ibcon#about to read 4, iclass 21, count 0 2006.175.07:31:10.72#ibcon#read 4, iclass 21, count 0 2006.175.07:31:10.72#ibcon#about to read 5, iclass 21, count 0 2006.175.07:31:10.72#ibcon#read 5, iclass 21, count 0 2006.175.07:31:10.72#ibcon#about to read 6, iclass 21, count 0 2006.175.07:31:10.72#ibcon#read 6, iclass 21, count 0 2006.175.07:31:10.72#ibcon#end of sib2, iclass 21, count 0 2006.175.07:31:10.72#ibcon#*after write, iclass 21, count 0 2006.175.07:31:10.72#ibcon#*before return 0, iclass 21, count 0 2006.175.07:31:10.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:10.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:31:10.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:31:10.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:31:10.72$vc4f8/vb=1,4 2006.175.07:31:10.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.07:31:10.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.07:31:10.72#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:10.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:10.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:10.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:10.72#ibcon#enter wrdev, iclass 23, count 2 2006.175.07:31:10.72#ibcon#first serial, iclass 23, count 2 2006.175.07:31:10.72#ibcon#enter sib2, iclass 23, count 2 2006.175.07:31:10.72#ibcon#flushed, iclass 23, count 2 2006.175.07:31:10.72#ibcon#about to write, iclass 23, count 2 2006.175.07:31:10.72#ibcon#wrote, iclass 23, count 2 2006.175.07:31:10.72#ibcon#about to read 3, iclass 23, count 2 2006.175.07:31:10.73#ibcon#read 3, iclass 23, count 2 2006.175.07:31:10.73#ibcon#about to read 4, iclass 23, count 2 2006.175.07:31:10.73#ibcon#read 4, iclass 23, count 2 2006.175.07:31:10.73#ibcon#about to read 5, iclass 23, count 2 2006.175.07:31:10.73#ibcon#read 5, iclass 23, count 2 2006.175.07:31:10.73#ibcon#about to read 6, iclass 23, count 2 2006.175.07:31:10.73#ibcon#read 6, iclass 23, count 2 2006.175.07:31:10.73#ibcon#end of sib2, iclass 23, count 2 2006.175.07:31:10.73#ibcon#*mode == 0, iclass 23, count 2 2006.175.07:31:10.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.07:31:10.73#ibcon#[27=AT01-04\r\n] 2006.175.07:31:10.73#ibcon#*before write, iclass 23, count 2 2006.175.07:31:10.73#ibcon#enter sib2, iclass 23, count 2 2006.175.07:31:10.73#ibcon#flushed, iclass 23, count 2 2006.175.07:31:10.73#ibcon#about to write, iclass 23, count 2 2006.175.07:31:10.73#ibcon#wrote, iclass 23, count 2 2006.175.07:31:10.73#ibcon#about to read 3, iclass 23, count 2 2006.175.07:31:10.76#ibcon#read 3, iclass 23, count 2 2006.175.07:31:10.76#ibcon#about to read 4, iclass 23, count 2 2006.175.07:31:10.76#ibcon#read 4, iclass 23, count 2 2006.175.07:31:10.76#ibcon#about to read 5, iclass 23, count 2 2006.175.07:31:10.76#ibcon#read 5, iclass 23, count 2 2006.175.07:31:10.76#ibcon#about to read 6, iclass 23, count 2 2006.175.07:31:10.76#ibcon#read 6, iclass 23, count 2 2006.175.07:31:10.76#ibcon#end of sib2, iclass 23, count 2 2006.175.07:31:10.76#ibcon#*after write, iclass 23, count 2 2006.175.07:31:10.76#ibcon#*before return 0, iclass 23, count 2 2006.175.07:31:10.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:10.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:31:10.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.07:31:10.76#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:10.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:10.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:10.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:10.88#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:31:10.88#ibcon#first serial, iclass 23, count 0 2006.175.07:31:10.88#ibcon#enter sib2, iclass 23, count 0 2006.175.07:31:10.88#ibcon#flushed, iclass 23, count 0 2006.175.07:31:10.88#ibcon#about to write, iclass 23, count 0 2006.175.07:31:10.88#ibcon#wrote, iclass 23, count 0 2006.175.07:31:10.88#ibcon#about to read 3, iclass 23, count 0 2006.175.07:31:10.90#ibcon#read 3, iclass 23, count 0 2006.175.07:31:10.90#ibcon#about to read 4, iclass 23, count 0 2006.175.07:31:10.90#ibcon#read 4, iclass 23, count 0 2006.175.07:31:10.90#ibcon#about to read 5, iclass 23, count 0 2006.175.07:31:10.90#ibcon#read 5, iclass 23, count 0 2006.175.07:31:10.90#ibcon#about to read 6, iclass 23, count 0 2006.175.07:31:10.90#ibcon#read 6, iclass 23, count 0 2006.175.07:31:10.90#ibcon#end of sib2, iclass 23, count 0 2006.175.07:31:10.90#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:31:10.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:31:10.90#ibcon#[27=USB\r\n] 2006.175.07:31:10.90#ibcon#*before write, iclass 23, count 0 2006.175.07:31:10.90#ibcon#enter sib2, iclass 23, count 0 2006.175.07:31:10.90#ibcon#flushed, iclass 23, count 0 2006.175.07:31:10.90#ibcon#about to write, iclass 23, count 0 2006.175.07:31:10.90#ibcon#wrote, iclass 23, count 0 2006.175.07:31:10.90#ibcon#about to read 3, iclass 23, count 0 2006.175.07:31:10.93#ibcon#read 3, iclass 23, count 0 2006.175.07:31:10.93#ibcon#about to read 4, iclass 23, count 0 2006.175.07:31:10.93#ibcon#read 4, iclass 23, count 0 2006.175.07:31:10.93#ibcon#about to read 5, iclass 23, count 0 2006.175.07:31:10.93#ibcon#read 5, iclass 23, count 0 2006.175.07:31:10.93#ibcon#about to read 6, iclass 23, count 0 2006.175.07:31:10.93#ibcon#read 6, iclass 23, count 0 2006.175.07:31:10.93#ibcon#end of sib2, iclass 23, count 0 2006.175.07:31:10.93#ibcon#*after write, iclass 23, count 0 2006.175.07:31:10.93#ibcon#*before return 0, iclass 23, count 0 2006.175.07:31:10.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:10.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:31:10.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:31:10.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:31:10.93$vc4f8/vblo=2,640.99 2006.175.07:31:10.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.07:31:10.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.07:31:10.93#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:10.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:10.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:10.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:10.93#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:31:10.93#ibcon#first serial, iclass 25, count 0 2006.175.07:31:10.93#ibcon#enter sib2, iclass 25, count 0 2006.175.07:31:10.93#ibcon#flushed, iclass 25, count 0 2006.175.07:31:10.93#ibcon#about to write, iclass 25, count 0 2006.175.07:31:10.93#ibcon#wrote, iclass 25, count 0 2006.175.07:31:10.93#ibcon#about to read 3, iclass 25, count 0 2006.175.07:31:10.95#ibcon#read 3, iclass 25, count 0 2006.175.07:31:10.95#ibcon#about to read 4, iclass 25, count 0 2006.175.07:31:10.95#ibcon#read 4, iclass 25, count 0 2006.175.07:31:10.95#ibcon#about to read 5, iclass 25, count 0 2006.175.07:31:10.95#ibcon#read 5, iclass 25, count 0 2006.175.07:31:10.95#ibcon#about to read 6, iclass 25, count 0 2006.175.07:31:10.95#ibcon#read 6, iclass 25, count 0 2006.175.07:31:10.95#ibcon#end of sib2, iclass 25, count 0 2006.175.07:31:10.95#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:31:10.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:31:10.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:31:10.95#ibcon#*before write, iclass 25, count 0 2006.175.07:31:10.95#ibcon#enter sib2, iclass 25, count 0 2006.175.07:31:10.95#ibcon#flushed, iclass 25, count 0 2006.175.07:31:10.95#ibcon#about to write, iclass 25, count 0 2006.175.07:31:10.95#ibcon#wrote, iclass 25, count 0 2006.175.07:31:10.95#ibcon#about to read 3, iclass 25, count 0 2006.175.07:31:10.99#ibcon#read 3, iclass 25, count 0 2006.175.07:31:10.99#ibcon#about to read 4, iclass 25, count 0 2006.175.07:31:10.99#ibcon#read 4, iclass 25, count 0 2006.175.07:31:10.99#ibcon#about to read 5, iclass 25, count 0 2006.175.07:31:10.99#ibcon#read 5, iclass 25, count 0 2006.175.07:31:10.99#ibcon#about to read 6, iclass 25, count 0 2006.175.07:31:10.99#ibcon#read 6, iclass 25, count 0 2006.175.07:31:10.99#ibcon#end of sib2, iclass 25, count 0 2006.175.07:31:10.99#ibcon#*after write, iclass 25, count 0 2006.175.07:31:10.99#ibcon#*before return 0, iclass 25, count 0 2006.175.07:31:10.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:10.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:31:10.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:31:10.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:31:10.99$vc4f8/vb=2,4 2006.175.07:31:10.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.07:31:10.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.07:31:10.99#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:10.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:11.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:11.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:11.05#ibcon#enter wrdev, iclass 27, count 2 2006.175.07:31:11.05#ibcon#first serial, iclass 27, count 2 2006.175.07:31:11.05#ibcon#enter sib2, iclass 27, count 2 2006.175.07:31:11.05#ibcon#flushed, iclass 27, count 2 2006.175.07:31:11.05#ibcon#about to write, iclass 27, count 2 2006.175.07:31:11.05#ibcon#wrote, iclass 27, count 2 2006.175.07:31:11.05#ibcon#about to read 3, iclass 27, count 2 2006.175.07:31:11.07#ibcon#read 3, iclass 27, count 2 2006.175.07:31:11.07#ibcon#about to read 4, iclass 27, count 2 2006.175.07:31:11.07#ibcon#read 4, iclass 27, count 2 2006.175.07:31:11.07#ibcon#about to read 5, iclass 27, count 2 2006.175.07:31:11.07#ibcon#read 5, iclass 27, count 2 2006.175.07:31:11.07#ibcon#about to read 6, iclass 27, count 2 2006.175.07:31:11.07#ibcon#read 6, iclass 27, count 2 2006.175.07:31:11.07#ibcon#end of sib2, iclass 27, count 2 2006.175.07:31:11.07#ibcon#*mode == 0, iclass 27, count 2 2006.175.07:31:11.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.07:31:11.07#ibcon#[27=AT02-04\r\n] 2006.175.07:31:11.07#ibcon#*before write, iclass 27, count 2 2006.175.07:31:11.07#ibcon#enter sib2, iclass 27, count 2 2006.175.07:31:11.07#ibcon#flushed, iclass 27, count 2 2006.175.07:31:11.07#ibcon#about to write, iclass 27, count 2 2006.175.07:31:11.07#ibcon#wrote, iclass 27, count 2 2006.175.07:31:11.07#ibcon#about to read 3, iclass 27, count 2 2006.175.07:31:11.10#ibcon#read 3, iclass 27, count 2 2006.175.07:31:11.10#ibcon#about to read 4, iclass 27, count 2 2006.175.07:31:11.10#ibcon#read 4, iclass 27, count 2 2006.175.07:31:11.10#ibcon#about to read 5, iclass 27, count 2 2006.175.07:31:11.10#ibcon#read 5, iclass 27, count 2 2006.175.07:31:11.10#ibcon#about to read 6, iclass 27, count 2 2006.175.07:31:11.10#ibcon#read 6, iclass 27, count 2 2006.175.07:31:11.10#ibcon#end of sib2, iclass 27, count 2 2006.175.07:31:11.10#ibcon#*after write, iclass 27, count 2 2006.175.07:31:11.10#ibcon#*before return 0, iclass 27, count 2 2006.175.07:31:11.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:11.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:31:11.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.07:31:11.10#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:11.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:11.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:11.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:11.22#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:31:11.22#ibcon#first serial, iclass 27, count 0 2006.175.07:31:11.22#ibcon#enter sib2, iclass 27, count 0 2006.175.07:31:11.22#ibcon#flushed, iclass 27, count 0 2006.175.07:31:11.22#ibcon#about to write, iclass 27, count 0 2006.175.07:31:11.22#ibcon#wrote, iclass 27, count 0 2006.175.07:31:11.22#ibcon#about to read 3, iclass 27, count 0 2006.175.07:31:11.24#ibcon#read 3, iclass 27, count 0 2006.175.07:31:11.24#ibcon#about to read 4, iclass 27, count 0 2006.175.07:31:11.24#ibcon#read 4, iclass 27, count 0 2006.175.07:31:11.24#ibcon#about to read 5, iclass 27, count 0 2006.175.07:31:11.24#ibcon#read 5, iclass 27, count 0 2006.175.07:31:11.24#ibcon#about to read 6, iclass 27, count 0 2006.175.07:31:11.25#ibcon#read 6, iclass 27, count 0 2006.175.07:31:11.25#ibcon#end of sib2, iclass 27, count 0 2006.175.07:31:11.25#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:31:11.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:31:11.25#ibcon#[27=USB\r\n] 2006.175.07:31:11.25#ibcon#*before write, iclass 27, count 0 2006.175.07:31:11.25#ibcon#enter sib2, iclass 27, count 0 2006.175.07:31:11.25#ibcon#flushed, iclass 27, count 0 2006.175.07:31:11.25#ibcon#about to write, iclass 27, count 0 2006.175.07:31:11.25#ibcon#wrote, iclass 27, count 0 2006.175.07:31:11.25#ibcon#about to read 3, iclass 27, count 0 2006.175.07:31:11.27#ibcon#read 3, iclass 27, count 0 2006.175.07:31:11.27#ibcon#about to read 4, iclass 27, count 0 2006.175.07:31:11.27#ibcon#read 4, iclass 27, count 0 2006.175.07:31:11.27#ibcon#about to read 5, iclass 27, count 0 2006.175.07:31:11.27#ibcon#read 5, iclass 27, count 0 2006.175.07:31:11.27#ibcon#about to read 6, iclass 27, count 0 2006.175.07:31:11.27#ibcon#read 6, iclass 27, count 0 2006.175.07:31:11.27#ibcon#end of sib2, iclass 27, count 0 2006.175.07:31:11.27#ibcon#*after write, iclass 27, count 0 2006.175.07:31:11.27#ibcon#*before return 0, iclass 27, count 0 2006.175.07:31:11.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:11.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:31:11.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:31:11.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:31:11.27$vc4f8/vblo=3,656.99 2006.175.07:31:11.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.07:31:11.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.07:31:11.27#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:11.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:11.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:11.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:11.27#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:31:11.27#ibcon#first serial, iclass 29, count 0 2006.175.07:31:11.27#ibcon#enter sib2, iclass 29, count 0 2006.175.07:31:11.27#ibcon#flushed, iclass 29, count 0 2006.175.07:31:11.27#ibcon#about to write, iclass 29, count 0 2006.175.07:31:11.27#ibcon#wrote, iclass 29, count 0 2006.175.07:31:11.27#ibcon#about to read 3, iclass 29, count 0 2006.175.07:31:11.29#ibcon#read 3, iclass 29, count 0 2006.175.07:31:11.29#ibcon#about to read 4, iclass 29, count 0 2006.175.07:31:11.29#ibcon#read 4, iclass 29, count 0 2006.175.07:31:11.29#ibcon#about to read 5, iclass 29, count 0 2006.175.07:31:11.29#ibcon#read 5, iclass 29, count 0 2006.175.07:31:11.29#ibcon#about to read 6, iclass 29, count 0 2006.175.07:31:11.29#ibcon#read 6, iclass 29, count 0 2006.175.07:31:11.29#ibcon#end of sib2, iclass 29, count 0 2006.175.07:31:11.29#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:31:11.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:31:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:31:11.29#ibcon#*before write, iclass 29, count 0 2006.175.07:31:11.29#ibcon#enter sib2, iclass 29, count 0 2006.175.07:31:11.29#ibcon#flushed, iclass 29, count 0 2006.175.07:31:11.29#ibcon#about to write, iclass 29, count 0 2006.175.07:31:11.29#ibcon#wrote, iclass 29, count 0 2006.175.07:31:11.29#ibcon#about to read 3, iclass 29, count 0 2006.175.07:31:11.33#ibcon#read 3, iclass 29, count 0 2006.175.07:31:11.33#ibcon#about to read 4, iclass 29, count 0 2006.175.07:31:11.33#ibcon#read 4, iclass 29, count 0 2006.175.07:31:11.33#ibcon#about to read 5, iclass 29, count 0 2006.175.07:31:11.33#ibcon#read 5, iclass 29, count 0 2006.175.07:31:11.33#ibcon#about to read 6, iclass 29, count 0 2006.175.07:31:11.33#ibcon#read 6, iclass 29, count 0 2006.175.07:31:11.33#ibcon#end of sib2, iclass 29, count 0 2006.175.07:31:11.33#ibcon#*after write, iclass 29, count 0 2006.175.07:31:11.33#ibcon#*before return 0, iclass 29, count 0 2006.175.07:31:11.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:11.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:31:11.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:31:11.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:31:11.33$vc4f8/vb=3,4 2006.175.07:31:11.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.07:31:11.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.07:31:11.33#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:11.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:11.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:11.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:11.39#ibcon#enter wrdev, iclass 31, count 2 2006.175.07:31:11.39#ibcon#first serial, iclass 31, count 2 2006.175.07:31:11.39#ibcon#enter sib2, iclass 31, count 2 2006.175.07:31:11.39#ibcon#flushed, iclass 31, count 2 2006.175.07:31:11.39#ibcon#about to write, iclass 31, count 2 2006.175.07:31:11.39#ibcon#wrote, iclass 31, count 2 2006.175.07:31:11.39#ibcon#about to read 3, iclass 31, count 2 2006.175.07:31:11.41#ibcon#read 3, iclass 31, count 2 2006.175.07:31:11.41#ibcon#about to read 4, iclass 31, count 2 2006.175.07:31:11.41#ibcon#read 4, iclass 31, count 2 2006.175.07:31:11.41#ibcon#about to read 5, iclass 31, count 2 2006.175.07:31:11.41#ibcon#read 5, iclass 31, count 2 2006.175.07:31:11.41#ibcon#about to read 6, iclass 31, count 2 2006.175.07:31:11.41#ibcon#read 6, iclass 31, count 2 2006.175.07:31:11.41#ibcon#end of sib2, iclass 31, count 2 2006.175.07:31:11.41#ibcon#*mode == 0, iclass 31, count 2 2006.175.07:31:11.41#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.07:31:11.41#ibcon#[27=AT03-04\r\n] 2006.175.07:31:11.41#ibcon#*before write, iclass 31, count 2 2006.175.07:31:11.41#ibcon#enter sib2, iclass 31, count 2 2006.175.07:31:11.41#ibcon#flushed, iclass 31, count 2 2006.175.07:31:11.41#ibcon#about to write, iclass 31, count 2 2006.175.07:31:11.41#ibcon#wrote, iclass 31, count 2 2006.175.07:31:11.41#ibcon#about to read 3, iclass 31, count 2 2006.175.07:31:11.44#ibcon#read 3, iclass 31, count 2 2006.175.07:31:11.44#ibcon#about to read 4, iclass 31, count 2 2006.175.07:31:11.44#ibcon#read 4, iclass 31, count 2 2006.175.07:31:11.44#ibcon#about to read 5, iclass 31, count 2 2006.175.07:31:11.44#ibcon#read 5, iclass 31, count 2 2006.175.07:31:11.44#ibcon#about to read 6, iclass 31, count 2 2006.175.07:31:11.44#ibcon#read 6, iclass 31, count 2 2006.175.07:31:11.44#ibcon#end of sib2, iclass 31, count 2 2006.175.07:31:11.44#ibcon#*after write, iclass 31, count 2 2006.175.07:31:11.44#ibcon#*before return 0, iclass 31, count 2 2006.175.07:31:11.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:11.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:31:11.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.07:31:11.44#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:11.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:11.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:11.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:11.56#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:31:11.56#ibcon#first serial, iclass 31, count 0 2006.175.07:31:11.56#ibcon#enter sib2, iclass 31, count 0 2006.175.07:31:11.56#ibcon#flushed, iclass 31, count 0 2006.175.07:31:11.56#ibcon#about to write, iclass 31, count 0 2006.175.07:31:11.56#ibcon#wrote, iclass 31, count 0 2006.175.07:31:11.56#ibcon#about to read 3, iclass 31, count 0 2006.175.07:31:11.58#ibcon#read 3, iclass 31, count 0 2006.175.07:31:11.58#ibcon#about to read 4, iclass 31, count 0 2006.175.07:31:11.58#ibcon#read 4, iclass 31, count 0 2006.175.07:31:11.58#ibcon#about to read 5, iclass 31, count 0 2006.175.07:31:11.58#ibcon#read 5, iclass 31, count 0 2006.175.07:31:11.58#ibcon#about to read 6, iclass 31, count 0 2006.175.07:31:11.58#ibcon#read 6, iclass 31, count 0 2006.175.07:31:11.58#ibcon#end of sib2, iclass 31, count 0 2006.175.07:31:11.58#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:31:11.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:31:11.58#ibcon#[27=USB\r\n] 2006.175.07:31:11.58#ibcon#*before write, iclass 31, count 0 2006.175.07:31:11.58#ibcon#enter sib2, iclass 31, count 0 2006.175.07:31:11.58#ibcon#flushed, iclass 31, count 0 2006.175.07:31:11.58#ibcon#about to write, iclass 31, count 0 2006.175.07:31:11.58#ibcon#wrote, iclass 31, count 0 2006.175.07:31:11.58#ibcon#about to read 3, iclass 31, count 0 2006.175.07:31:11.61#ibcon#read 3, iclass 31, count 0 2006.175.07:31:11.61#ibcon#about to read 4, iclass 31, count 0 2006.175.07:31:11.61#ibcon#read 4, iclass 31, count 0 2006.175.07:31:11.61#ibcon#about to read 5, iclass 31, count 0 2006.175.07:31:11.61#ibcon#read 5, iclass 31, count 0 2006.175.07:31:11.61#ibcon#about to read 6, iclass 31, count 0 2006.175.07:31:11.61#ibcon#read 6, iclass 31, count 0 2006.175.07:31:11.61#ibcon#end of sib2, iclass 31, count 0 2006.175.07:31:11.61#ibcon#*after write, iclass 31, count 0 2006.175.07:31:11.61#ibcon#*before return 0, iclass 31, count 0 2006.175.07:31:11.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:11.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:31:11.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:31:11.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:31:11.61$vc4f8/vblo=4,712.99 2006.175.07:31:11.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.07:31:11.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.07:31:11.61#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:11.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:11.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:11.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:11.61#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:31:11.61#ibcon#first serial, iclass 33, count 0 2006.175.07:31:11.61#ibcon#enter sib2, iclass 33, count 0 2006.175.07:31:11.61#ibcon#flushed, iclass 33, count 0 2006.175.07:31:11.61#ibcon#about to write, iclass 33, count 0 2006.175.07:31:11.61#ibcon#wrote, iclass 33, count 0 2006.175.07:31:11.61#ibcon#about to read 3, iclass 33, count 0 2006.175.07:31:11.63#ibcon#read 3, iclass 33, count 0 2006.175.07:31:11.63#ibcon#about to read 4, iclass 33, count 0 2006.175.07:31:11.63#ibcon#read 4, iclass 33, count 0 2006.175.07:31:11.63#ibcon#about to read 5, iclass 33, count 0 2006.175.07:31:11.63#ibcon#read 5, iclass 33, count 0 2006.175.07:31:11.63#ibcon#about to read 6, iclass 33, count 0 2006.175.07:31:11.63#ibcon#read 6, iclass 33, count 0 2006.175.07:31:11.63#ibcon#end of sib2, iclass 33, count 0 2006.175.07:31:11.63#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:31:11.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:31:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:31:11.63#ibcon#*before write, iclass 33, count 0 2006.175.07:31:11.63#ibcon#enter sib2, iclass 33, count 0 2006.175.07:31:11.63#ibcon#flushed, iclass 33, count 0 2006.175.07:31:11.63#ibcon#about to write, iclass 33, count 0 2006.175.07:31:11.63#ibcon#wrote, iclass 33, count 0 2006.175.07:31:11.63#ibcon#about to read 3, iclass 33, count 0 2006.175.07:31:11.67#ibcon#read 3, iclass 33, count 0 2006.175.07:31:11.67#ibcon#about to read 4, iclass 33, count 0 2006.175.07:31:11.67#ibcon#read 4, iclass 33, count 0 2006.175.07:31:11.67#ibcon#about to read 5, iclass 33, count 0 2006.175.07:31:11.67#ibcon#read 5, iclass 33, count 0 2006.175.07:31:11.67#ibcon#about to read 6, iclass 33, count 0 2006.175.07:31:11.67#ibcon#read 6, iclass 33, count 0 2006.175.07:31:11.67#ibcon#end of sib2, iclass 33, count 0 2006.175.07:31:11.67#ibcon#*after write, iclass 33, count 0 2006.175.07:31:11.67#ibcon#*before return 0, iclass 33, count 0 2006.175.07:31:11.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:11.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:31:11.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:31:11.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:31:11.67$vc4f8/vb=4,4 2006.175.07:31:11.67#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.175.07:31:11.67#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.175.07:31:11.67#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:11.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:11.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:11.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:11.73#ibcon#enter wrdev, iclass 35, count 2 2006.175.07:31:11.73#ibcon#first serial, iclass 35, count 2 2006.175.07:31:11.73#ibcon#enter sib2, iclass 35, count 2 2006.175.07:31:11.73#ibcon#flushed, iclass 35, count 2 2006.175.07:31:11.73#ibcon#about to write, iclass 35, count 2 2006.175.07:31:11.73#ibcon#wrote, iclass 35, count 2 2006.175.07:31:11.73#ibcon#about to read 3, iclass 35, count 2 2006.175.07:31:11.75#ibcon#read 3, iclass 35, count 2 2006.175.07:31:11.75#ibcon#about to read 4, iclass 35, count 2 2006.175.07:31:11.75#ibcon#read 4, iclass 35, count 2 2006.175.07:31:11.75#ibcon#about to read 5, iclass 35, count 2 2006.175.07:31:11.75#ibcon#read 5, iclass 35, count 2 2006.175.07:31:11.75#ibcon#about to read 6, iclass 35, count 2 2006.175.07:31:11.75#ibcon#read 6, iclass 35, count 2 2006.175.07:31:11.75#ibcon#end of sib2, iclass 35, count 2 2006.175.07:31:11.75#ibcon#*mode == 0, iclass 35, count 2 2006.175.07:31:11.75#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.175.07:31:11.75#ibcon#[27=AT04-04\r\n] 2006.175.07:31:11.75#ibcon#*before write, iclass 35, count 2 2006.175.07:31:11.75#ibcon#enter sib2, iclass 35, count 2 2006.175.07:31:11.75#ibcon#flushed, iclass 35, count 2 2006.175.07:31:11.75#ibcon#about to write, iclass 35, count 2 2006.175.07:31:11.75#ibcon#wrote, iclass 35, count 2 2006.175.07:31:11.75#ibcon#about to read 3, iclass 35, count 2 2006.175.07:31:11.78#ibcon#read 3, iclass 35, count 2 2006.175.07:31:11.78#ibcon#about to read 4, iclass 35, count 2 2006.175.07:31:11.78#ibcon#read 4, iclass 35, count 2 2006.175.07:31:11.78#ibcon#about to read 5, iclass 35, count 2 2006.175.07:31:11.78#ibcon#read 5, iclass 35, count 2 2006.175.07:31:11.78#ibcon#about to read 6, iclass 35, count 2 2006.175.07:31:11.78#ibcon#read 6, iclass 35, count 2 2006.175.07:31:11.78#ibcon#end of sib2, iclass 35, count 2 2006.175.07:31:11.78#ibcon#*after write, iclass 35, count 2 2006.175.07:31:11.78#ibcon#*before return 0, iclass 35, count 2 2006.175.07:31:11.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:11.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:31:11.78#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.175.07:31:11.78#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:11.78#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:11.90#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:11.90#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:11.90#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:31:11.90#ibcon#first serial, iclass 35, count 0 2006.175.07:31:11.90#ibcon#enter sib2, iclass 35, count 0 2006.175.07:31:11.90#ibcon#flushed, iclass 35, count 0 2006.175.07:31:11.90#ibcon#about to write, iclass 35, count 0 2006.175.07:31:11.90#ibcon#wrote, iclass 35, count 0 2006.175.07:31:11.90#ibcon#about to read 3, iclass 35, count 0 2006.175.07:31:11.92#ibcon#read 3, iclass 35, count 0 2006.175.07:31:11.92#ibcon#about to read 4, iclass 35, count 0 2006.175.07:31:11.92#ibcon#read 4, iclass 35, count 0 2006.175.07:31:11.92#ibcon#about to read 5, iclass 35, count 0 2006.175.07:31:11.92#ibcon#read 5, iclass 35, count 0 2006.175.07:31:11.92#ibcon#about to read 6, iclass 35, count 0 2006.175.07:31:11.92#ibcon#read 6, iclass 35, count 0 2006.175.07:31:11.92#ibcon#end of sib2, iclass 35, count 0 2006.175.07:31:11.92#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:31:11.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:31:11.92#ibcon#[27=USB\r\n] 2006.175.07:31:11.92#ibcon#*before write, iclass 35, count 0 2006.175.07:31:11.92#ibcon#enter sib2, iclass 35, count 0 2006.175.07:31:11.92#ibcon#flushed, iclass 35, count 0 2006.175.07:31:11.92#ibcon#about to write, iclass 35, count 0 2006.175.07:31:11.92#ibcon#wrote, iclass 35, count 0 2006.175.07:31:11.92#ibcon#about to read 3, iclass 35, count 0 2006.175.07:31:11.95#ibcon#read 3, iclass 35, count 0 2006.175.07:31:11.95#ibcon#about to read 4, iclass 35, count 0 2006.175.07:31:11.95#ibcon#read 4, iclass 35, count 0 2006.175.07:31:11.95#ibcon#about to read 5, iclass 35, count 0 2006.175.07:31:11.95#ibcon#read 5, iclass 35, count 0 2006.175.07:31:11.95#ibcon#about to read 6, iclass 35, count 0 2006.175.07:31:11.95#ibcon#read 6, iclass 35, count 0 2006.175.07:31:11.95#ibcon#end of sib2, iclass 35, count 0 2006.175.07:31:11.95#ibcon#*after write, iclass 35, count 0 2006.175.07:31:11.95#ibcon#*before return 0, iclass 35, count 0 2006.175.07:31:11.95#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:11.95#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:31:11.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:31:11.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:31:11.95$vc4f8/vblo=5,744.99 2006.175.07:31:11.95#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.07:31:11.95#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.07:31:11.95#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:11.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:11.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:11.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:11.95#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:31:11.95#ibcon#first serial, iclass 37, count 0 2006.175.07:31:11.95#ibcon#enter sib2, iclass 37, count 0 2006.175.07:31:11.95#ibcon#flushed, iclass 37, count 0 2006.175.07:31:11.95#ibcon#about to write, iclass 37, count 0 2006.175.07:31:11.95#ibcon#wrote, iclass 37, count 0 2006.175.07:31:11.95#ibcon#about to read 3, iclass 37, count 0 2006.175.07:31:11.97#ibcon#read 3, iclass 37, count 0 2006.175.07:31:11.97#ibcon#about to read 4, iclass 37, count 0 2006.175.07:31:11.97#ibcon#read 4, iclass 37, count 0 2006.175.07:31:11.97#ibcon#about to read 5, iclass 37, count 0 2006.175.07:31:11.97#ibcon#read 5, iclass 37, count 0 2006.175.07:31:11.97#ibcon#about to read 6, iclass 37, count 0 2006.175.07:31:11.97#ibcon#read 6, iclass 37, count 0 2006.175.07:31:11.97#ibcon#end of sib2, iclass 37, count 0 2006.175.07:31:11.97#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:31:11.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:31:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:31:11.97#ibcon#*before write, iclass 37, count 0 2006.175.07:31:11.97#ibcon#enter sib2, iclass 37, count 0 2006.175.07:31:11.97#ibcon#flushed, iclass 37, count 0 2006.175.07:31:11.97#ibcon#about to write, iclass 37, count 0 2006.175.07:31:11.97#ibcon#wrote, iclass 37, count 0 2006.175.07:31:11.97#ibcon#about to read 3, iclass 37, count 0 2006.175.07:31:12.01#ibcon#read 3, iclass 37, count 0 2006.175.07:31:12.01#ibcon#about to read 4, iclass 37, count 0 2006.175.07:31:12.01#ibcon#read 4, iclass 37, count 0 2006.175.07:31:12.01#ibcon#about to read 5, iclass 37, count 0 2006.175.07:31:12.01#ibcon#read 5, iclass 37, count 0 2006.175.07:31:12.01#ibcon#about to read 6, iclass 37, count 0 2006.175.07:31:12.01#ibcon#read 6, iclass 37, count 0 2006.175.07:31:12.01#ibcon#end of sib2, iclass 37, count 0 2006.175.07:31:12.01#ibcon#*after write, iclass 37, count 0 2006.175.07:31:12.01#ibcon#*before return 0, iclass 37, count 0 2006.175.07:31:12.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:12.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:31:12.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:31:12.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:31:12.01$vc4f8/vb=5,4 2006.175.07:31:12.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.175.07:31:12.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.175.07:31:12.01#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:12.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:12.07#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:12.07#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:12.07#ibcon#enter wrdev, iclass 39, count 2 2006.175.07:31:12.07#ibcon#first serial, iclass 39, count 2 2006.175.07:31:12.07#ibcon#enter sib2, iclass 39, count 2 2006.175.07:31:12.07#ibcon#flushed, iclass 39, count 2 2006.175.07:31:12.07#ibcon#about to write, iclass 39, count 2 2006.175.07:31:12.07#ibcon#wrote, iclass 39, count 2 2006.175.07:31:12.07#ibcon#about to read 3, iclass 39, count 2 2006.175.07:31:12.09#ibcon#read 3, iclass 39, count 2 2006.175.07:31:12.09#ibcon#about to read 4, iclass 39, count 2 2006.175.07:31:12.09#ibcon#read 4, iclass 39, count 2 2006.175.07:31:12.09#ibcon#about to read 5, iclass 39, count 2 2006.175.07:31:12.09#ibcon#read 5, iclass 39, count 2 2006.175.07:31:12.09#ibcon#about to read 6, iclass 39, count 2 2006.175.07:31:12.09#ibcon#read 6, iclass 39, count 2 2006.175.07:31:12.09#ibcon#end of sib2, iclass 39, count 2 2006.175.07:31:12.09#ibcon#*mode == 0, iclass 39, count 2 2006.175.07:31:12.09#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.175.07:31:12.09#ibcon#[27=AT05-04\r\n] 2006.175.07:31:12.09#ibcon#*before write, iclass 39, count 2 2006.175.07:31:12.09#ibcon#enter sib2, iclass 39, count 2 2006.175.07:31:12.09#ibcon#flushed, iclass 39, count 2 2006.175.07:31:12.09#ibcon#about to write, iclass 39, count 2 2006.175.07:31:12.09#ibcon#wrote, iclass 39, count 2 2006.175.07:31:12.09#ibcon#about to read 3, iclass 39, count 2 2006.175.07:31:12.12#ibcon#read 3, iclass 39, count 2 2006.175.07:31:12.12#ibcon#about to read 4, iclass 39, count 2 2006.175.07:31:12.12#ibcon#read 4, iclass 39, count 2 2006.175.07:31:12.12#ibcon#about to read 5, iclass 39, count 2 2006.175.07:31:12.12#ibcon#read 5, iclass 39, count 2 2006.175.07:31:12.12#ibcon#about to read 6, iclass 39, count 2 2006.175.07:31:12.12#ibcon#read 6, iclass 39, count 2 2006.175.07:31:12.12#ibcon#end of sib2, iclass 39, count 2 2006.175.07:31:12.12#ibcon#*after write, iclass 39, count 2 2006.175.07:31:12.12#ibcon#*before return 0, iclass 39, count 2 2006.175.07:31:12.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:12.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:31:12.12#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.175.07:31:12.12#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:12.12#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:12.24#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:12.24#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:12.24#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:31:12.24#ibcon#first serial, iclass 39, count 0 2006.175.07:31:12.24#ibcon#enter sib2, iclass 39, count 0 2006.175.07:31:12.24#ibcon#flushed, iclass 39, count 0 2006.175.07:31:12.24#ibcon#about to write, iclass 39, count 0 2006.175.07:31:12.24#ibcon#wrote, iclass 39, count 0 2006.175.07:31:12.24#ibcon#about to read 3, iclass 39, count 0 2006.175.07:31:12.26#ibcon#read 3, iclass 39, count 0 2006.175.07:31:12.26#ibcon#about to read 4, iclass 39, count 0 2006.175.07:31:12.26#ibcon#read 4, iclass 39, count 0 2006.175.07:31:12.26#ibcon#about to read 5, iclass 39, count 0 2006.175.07:31:12.26#ibcon#read 5, iclass 39, count 0 2006.175.07:31:12.26#ibcon#about to read 6, iclass 39, count 0 2006.175.07:31:12.26#ibcon#read 6, iclass 39, count 0 2006.175.07:31:12.26#ibcon#end of sib2, iclass 39, count 0 2006.175.07:31:12.26#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:31:12.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:31:12.26#ibcon#[27=USB\r\n] 2006.175.07:31:12.26#ibcon#*before write, iclass 39, count 0 2006.175.07:31:12.26#ibcon#enter sib2, iclass 39, count 0 2006.175.07:31:12.26#ibcon#flushed, iclass 39, count 0 2006.175.07:31:12.26#ibcon#about to write, iclass 39, count 0 2006.175.07:31:12.26#ibcon#wrote, iclass 39, count 0 2006.175.07:31:12.26#ibcon#about to read 3, iclass 39, count 0 2006.175.07:31:12.29#ibcon#read 3, iclass 39, count 0 2006.175.07:31:12.29#ibcon#about to read 4, iclass 39, count 0 2006.175.07:31:12.29#ibcon#read 4, iclass 39, count 0 2006.175.07:31:12.29#ibcon#about to read 5, iclass 39, count 0 2006.175.07:31:12.29#ibcon#read 5, iclass 39, count 0 2006.175.07:31:12.29#ibcon#about to read 6, iclass 39, count 0 2006.175.07:31:12.29#ibcon#read 6, iclass 39, count 0 2006.175.07:31:12.29#ibcon#end of sib2, iclass 39, count 0 2006.175.07:31:12.29#ibcon#*after write, iclass 39, count 0 2006.175.07:31:12.29#ibcon#*before return 0, iclass 39, count 0 2006.175.07:31:12.29#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:12.29#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:31:12.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:31:12.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:31:12.29$vc4f8/vblo=6,752.99 2006.175.07:31:12.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.07:31:12.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.07:31:12.30#ibcon#ireg 17 cls_cnt 0 2006.175.07:31:12.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:12.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:12.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:12.30#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:31:12.30#ibcon#first serial, iclass 3, count 0 2006.175.07:31:12.30#ibcon#enter sib2, iclass 3, count 0 2006.175.07:31:12.30#ibcon#flushed, iclass 3, count 0 2006.175.07:31:12.30#ibcon#about to write, iclass 3, count 0 2006.175.07:31:12.30#ibcon#wrote, iclass 3, count 0 2006.175.07:31:12.30#ibcon#about to read 3, iclass 3, count 0 2006.175.07:31:12.32#ibcon#read 3, iclass 3, count 0 2006.175.07:31:12.32#ibcon#about to read 4, iclass 3, count 0 2006.175.07:31:12.32#ibcon#read 4, iclass 3, count 0 2006.175.07:31:12.32#ibcon#about to read 5, iclass 3, count 0 2006.175.07:31:12.32#ibcon#read 5, iclass 3, count 0 2006.175.07:31:12.32#ibcon#about to read 6, iclass 3, count 0 2006.175.07:31:12.32#ibcon#read 6, iclass 3, count 0 2006.175.07:31:12.32#ibcon#end of sib2, iclass 3, count 0 2006.175.07:31:12.32#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:31:12.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:31:12.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:31:12.32#ibcon#*before write, iclass 3, count 0 2006.175.07:31:12.32#ibcon#enter sib2, iclass 3, count 0 2006.175.07:31:12.32#ibcon#flushed, iclass 3, count 0 2006.175.07:31:12.32#ibcon#about to write, iclass 3, count 0 2006.175.07:31:12.32#ibcon#wrote, iclass 3, count 0 2006.175.07:31:12.32#ibcon#about to read 3, iclass 3, count 0 2006.175.07:31:12.35#ibcon#read 3, iclass 3, count 0 2006.175.07:31:12.35#ibcon#about to read 4, iclass 3, count 0 2006.175.07:31:12.35#ibcon#read 4, iclass 3, count 0 2006.175.07:31:12.35#ibcon#about to read 5, iclass 3, count 0 2006.175.07:31:12.35#ibcon#read 5, iclass 3, count 0 2006.175.07:31:12.35#ibcon#about to read 6, iclass 3, count 0 2006.175.07:31:12.35#ibcon#read 6, iclass 3, count 0 2006.175.07:31:12.35#ibcon#end of sib2, iclass 3, count 0 2006.175.07:31:12.35#ibcon#*after write, iclass 3, count 0 2006.175.07:31:12.35#ibcon#*before return 0, iclass 3, count 0 2006.175.07:31:12.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:12.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:31:12.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:31:12.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:31:12.35$vc4f8/vb=6,4 2006.175.07:31:12.35#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.175.07:31:12.35#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.175.07:31:12.35#ibcon#ireg 11 cls_cnt 2 2006.175.07:31:12.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:12.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:12.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:12.41#ibcon#enter wrdev, iclass 5, count 2 2006.175.07:31:12.41#ibcon#first serial, iclass 5, count 2 2006.175.07:31:12.41#ibcon#enter sib2, iclass 5, count 2 2006.175.07:31:12.41#ibcon#flushed, iclass 5, count 2 2006.175.07:31:12.41#ibcon#about to write, iclass 5, count 2 2006.175.07:31:12.41#ibcon#wrote, iclass 5, count 2 2006.175.07:31:12.41#ibcon#about to read 3, iclass 5, count 2 2006.175.07:31:12.43#ibcon#read 3, iclass 5, count 2 2006.175.07:31:12.43#ibcon#about to read 4, iclass 5, count 2 2006.175.07:31:12.43#ibcon#read 4, iclass 5, count 2 2006.175.07:31:12.43#ibcon#about to read 5, iclass 5, count 2 2006.175.07:31:12.43#ibcon#read 5, iclass 5, count 2 2006.175.07:31:12.43#ibcon#about to read 6, iclass 5, count 2 2006.175.07:31:12.43#ibcon#read 6, iclass 5, count 2 2006.175.07:31:12.43#ibcon#end of sib2, iclass 5, count 2 2006.175.07:31:12.43#ibcon#*mode == 0, iclass 5, count 2 2006.175.07:31:12.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.175.07:31:12.43#ibcon#[27=AT06-04\r\n] 2006.175.07:31:12.43#ibcon#*before write, iclass 5, count 2 2006.175.07:31:12.43#ibcon#enter sib2, iclass 5, count 2 2006.175.07:31:12.43#ibcon#flushed, iclass 5, count 2 2006.175.07:31:12.43#ibcon#about to write, iclass 5, count 2 2006.175.07:31:12.43#ibcon#wrote, iclass 5, count 2 2006.175.07:31:12.43#ibcon#about to read 3, iclass 5, count 2 2006.175.07:31:12.46#ibcon#read 3, iclass 5, count 2 2006.175.07:31:12.46#ibcon#about to read 4, iclass 5, count 2 2006.175.07:31:12.46#ibcon#read 4, iclass 5, count 2 2006.175.07:31:12.46#ibcon#about to read 5, iclass 5, count 2 2006.175.07:31:12.46#ibcon#read 5, iclass 5, count 2 2006.175.07:31:12.46#ibcon#about to read 6, iclass 5, count 2 2006.175.07:31:12.46#ibcon#read 6, iclass 5, count 2 2006.175.07:31:12.46#ibcon#end of sib2, iclass 5, count 2 2006.175.07:31:12.46#ibcon#*after write, iclass 5, count 2 2006.175.07:31:12.46#ibcon#*before return 0, iclass 5, count 2 2006.175.07:31:12.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:12.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:31:12.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.175.07:31:12.46#ibcon#ireg 7 cls_cnt 0 2006.175.07:31:12.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:12.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:12.58#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:12.58#ibcon#enter wrdev, iclass 5, count 0 2006.175.07:31:12.58#ibcon#first serial, iclass 5, count 0 2006.175.07:31:12.58#ibcon#enter sib2, iclass 5, count 0 2006.175.07:31:12.58#ibcon#flushed, iclass 5, count 0 2006.175.07:31:12.58#ibcon#about to write, iclass 5, count 0 2006.175.07:31:12.58#ibcon#wrote, iclass 5, count 0 2006.175.07:31:12.58#ibcon#about to read 3, iclass 5, count 0 2006.175.07:31:12.60#ibcon#read 3, iclass 5, count 0 2006.175.07:31:12.60#ibcon#about to read 4, iclass 5, count 0 2006.175.07:31:12.60#ibcon#read 4, iclass 5, count 0 2006.175.07:31:12.60#ibcon#about to read 5, iclass 5, count 0 2006.175.07:31:12.60#ibcon#read 5, iclass 5, count 0 2006.175.07:31:12.60#ibcon#about to read 6, iclass 5, count 0 2006.175.07:31:12.60#ibcon#read 6, iclass 5, count 0 2006.175.07:31:12.60#ibcon#end of sib2, iclass 5, count 0 2006.175.07:31:12.60#ibcon#*mode == 0, iclass 5, count 0 2006.175.07:31:12.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.07:31:12.60#ibcon#[27=USB\r\n] 2006.175.07:31:12.60#ibcon#*before write, iclass 5, count 0 2006.175.07:31:12.60#ibcon#enter sib2, iclass 5, count 0 2006.175.07:31:12.60#ibcon#flushed, iclass 5, count 0 2006.175.07:31:12.60#ibcon#about to write, iclass 5, count 0 2006.175.07:31:12.60#ibcon#wrote, iclass 5, count 0 2006.175.07:31:12.60#ibcon#about to read 3, iclass 5, count 0 2006.175.07:31:12.63#ibcon#read 3, iclass 5, count 0 2006.175.07:31:12.63#ibcon#about to read 4, iclass 5, count 0 2006.175.07:31:12.63#ibcon#read 4, iclass 5, count 0 2006.175.07:31:12.63#ibcon#about to read 5, iclass 5, count 0 2006.175.07:31:12.63#ibcon#read 5, iclass 5, count 0 2006.175.07:31:12.63#ibcon#about to read 6, iclass 5, count 0 2006.175.07:31:12.63#ibcon#read 6, iclass 5, count 0 2006.175.07:31:12.63#ibcon#end of sib2, iclass 5, count 0 2006.175.07:31:12.63#ibcon#*after write, iclass 5, count 0 2006.175.07:31:12.63#ibcon#*before return 0, iclass 5, count 0 2006.175.07:31:12.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:12.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:31:12.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.07:31:12.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.07:31:12.63$vc4f8/vabw=wide 2006.175.07:31:12.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.07:31:12.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.07:31:12.63#ibcon#ireg 8 cls_cnt 0 2006.175.07:31:12.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:12.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:12.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:12.63#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:31:12.63#ibcon#first serial, iclass 7, count 0 2006.175.07:31:12.63#ibcon#enter sib2, iclass 7, count 0 2006.175.07:31:12.63#ibcon#flushed, iclass 7, count 0 2006.175.07:31:12.63#ibcon#about to write, iclass 7, count 0 2006.175.07:31:12.63#ibcon#wrote, iclass 7, count 0 2006.175.07:31:12.63#ibcon#about to read 3, iclass 7, count 0 2006.175.07:31:12.65#ibcon#read 3, iclass 7, count 0 2006.175.07:31:12.65#ibcon#about to read 4, iclass 7, count 0 2006.175.07:31:12.65#ibcon#read 4, iclass 7, count 0 2006.175.07:31:12.65#ibcon#about to read 5, iclass 7, count 0 2006.175.07:31:12.65#ibcon#read 5, iclass 7, count 0 2006.175.07:31:12.65#ibcon#about to read 6, iclass 7, count 0 2006.175.07:31:12.65#ibcon#read 6, iclass 7, count 0 2006.175.07:31:12.65#ibcon#end of sib2, iclass 7, count 0 2006.175.07:31:12.65#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:31:12.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:31:12.65#ibcon#[25=BW32\r\n] 2006.175.07:31:12.65#ibcon#*before write, iclass 7, count 0 2006.175.07:31:12.65#ibcon#enter sib2, iclass 7, count 0 2006.175.07:31:12.65#ibcon#flushed, iclass 7, count 0 2006.175.07:31:12.65#ibcon#about to write, iclass 7, count 0 2006.175.07:31:12.65#ibcon#wrote, iclass 7, count 0 2006.175.07:31:12.65#ibcon#about to read 3, iclass 7, count 0 2006.175.07:31:12.68#ibcon#read 3, iclass 7, count 0 2006.175.07:31:12.68#ibcon#about to read 4, iclass 7, count 0 2006.175.07:31:12.68#ibcon#read 4, iclass 7, count 0 2006.175.07:31:12.68#ibcon#about to read 5, iclass 7, count 0 2006.175.07:31:12.68#ibcon#read 5, iclass 7, count 0 2006.175.07:31:12.68#ibcon#about to read 6, iclass 7, count 0 2006.175.07:31:12.68#ibcon#read 6, iclass 7, count 0 2006.175.07:31:12.68#ibcon#end of sib2, iclass 7, count 0 2006.175.07:31:12.68#ibcon#*after write, iclass 7, count 0 2006.175.07:31:12.68#ibcon#*before return 0, iclass 7, count 0 2006.175.07:31:12.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:12.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:31:12.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:31:12.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:31:12.68$vc4f8/vbbw=wide 2006.175.07:31:12.68#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.07:31:12.68#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.07:31:12.68#ibcon#ireg 8 cls_cnt 0 2006.175.07:31:12.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:31:12.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:31:12.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:31:12.75#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:31:12.75#ibcon#first serial, iclass 11, count 0 2006.175.07:31:12.75#ibcon#enter sib2, iclass 11, count 0 2006.175.07:31:12.75#ibcon#flushed, iclass 11, count 0 2006.175.07:31:12.75#ibcon#about to write, iclass 11, count 0 2006.175.07:31:12.75#ibcon#wrote, iclass 11, count 0 2006.175.07:31:12.75#ibcon#about to read 3, iclass 11, count 0 2006.175.07:31:12.77#ibcon#read 3, iclass 11, count 0 2006.175.07:31:12.77#ibcon#about to read 4, iclass 11, count 0 2006.175.07:31:12.77#ibcon#read 4, iclass 11, count 0 2006.175.07:31:12.77#ibcon#about to read 5, iclass 11, count 0 2006.175.07:31:12.77#ibcon#read 5, iclass 11, count 0 2006.175.07:31:12.77#ibcon#about to read 6, iclass 11, count 0 2006.175.07:31:12.77#ibcon#read 6, iclass 11, count 0 2006.175.07:31:12.77#ibcon#end of sib2, iclass 11, count 0 2006.175.07:31:12.77#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:31:12.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:31:12.77#ibcon#[27=BW32\r\n] 2006.175.07:31:12.77#ibcon#*before write, iclass 11, count 0 2006.175.07:31:12.77#ibcon#enter sib2, iclass 11, count 0 2006.175.07:31:12.77#ibcon#flushed, iclass 11, count 0 2006.175.07:31:12.77#ibcon#about to write, iclass 11, count 0 2006.175.07:31:12.77#ibcon#wrote, iclass 11, count 0 2006.175.07:31:12.77#ibcon#about to read 3, iclass 11, count 0 2006.175.07:31:12.80#ibcon#read 3, iclass 11, count 0 2006.175.07:31:12.80#ibcon#about to read 4, iclass 11, count 0 2006.175.07:31:12.80#ibcon#read 4, iclass 11, count 0 2006.175.07:31:12.80#ibcon#about to read 5, iclass 11, count 0 2006.175.07:31:12.80#ibcon#read 5, iclass 11, count 0 2006.175.07:31:12.80#ibcon#about to read 6, iclass 11, count 0 2006.175.07:31:12.80#ibcon#read 6, iclass 11, count 0 2006.175.07:31:12.80#ibcon#end of sib2, iclass 11, count 0 2006.175.07:31:12.80#ibcon#*after write, iclass 11, count 0 2006.175.07:31:12.80#ibcon#*before return 0, iclass 11, count 0 2006.175.07:31:12.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:31:12.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:31:12.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:31:12.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:31:12.80$4f8m12a/ifd4f 2006.175.07:31:12.80$ifd4f/lo= 2006.175.07:31:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:31:12.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:31:12.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:31:12.80$ifd4f/patch= 2006.175.07:31:12.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:31:12.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:31:12.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:31:12.80$4f8m12a/"form=m,16.000,1:2 2006.175.07:31:12.80$4f8m12a/"tpicd 2006.175.07:31:12.80$4f8m12a/echo=off 2006.175.07:31:12.80$4f8m12a/xlog=off 2006.175.07:31:12.80:!2006.175.07:33:20 2006.175.07:31:51.14#trakl#Source acquired 2006.175.07:31:51.14#flagr#flagr/antenna,acquired 2006.175.07:33:20.00:preob 2006.175.07:33:20.14/onsource/TRACKING 2006.175.07:33:20.14:!2006.175.07:33:30 2006.175.07:33:30.00:data_valid=on 2006.175.07:33:30.00:midob 2006.175.07:33:30.13/onsource/TRACKING 2006.175.07:33:30.13/wx/26.03,1007.5,69 2006.175.07:33:30.37/cable/+6.4796E-03 2006.175.07:33:31.46/va/01,08,usb,yes,29,30 2006.175.07:33:31.46/va/02,07,usb,yes,29,30 2006.175.07:33:31.46/va/03,06,usb,yes,30,31 2006.175.07:33:31.46/va/04,07,usb,yes,29,32 2006.175.07:33:31.46/va/05,07,usb,yes,29,31 2006.175.07:33:31.46/va/06,06,usb,yes,29,28 2006.175.07:33:31.46/va/07,06,usb,yes,29,29 2006.175.07:33:31.46/va/08,06,usb,yes,31,30 2006.175.07:33:31.69/valo/01,532.99,yes,locked 2006.175.07:33:31.69/valo/02,572.99,yes,locked 2006.175.07:33:31.69/valo/03,672.99,yes,locked 2006.175.07:33:31.69/valo/04,832.99,yes,locked 2006.175.07:33:31.69/valo/05,652.99,yes,locked 2006.175.07:33:31.69/valo/06,772.99,yes,locked 2006.175.07:33:31.69/valo/07,832.99,yes,locked 2006.175.07:33:31.69/valo/08,852.99,yes,locked 2006.175.07:33:32.78/vb/01,04,usb,yes,29,28 2006.175.07:33:32.78/vb/02,04,usb,yes,31,32 2006.175.07:33:32.78/vb/03,04,usb,yes,27,31 2006.175.07:33:32.78/vb/04,04,usb,yes,28,28 2006.175.07:33:32.78/vb/05,04,usb,yes,27,30 2006.175.07:33:32.78/vb/06,04,usb,yes,28,30 2006.175.07:33:32.78/vb/07,04,usb,yes,30,29 2006.175.07:33:32.78/vb/08,04,usb,yes,27,30 2006.175.07:33:33.01/vblo/01,632.99,yes,locked 2006.175.07:33:33.01/vblo/02,640.99,yes,locked 2006.175.07:33:33.01/vblo/03,656.99,yes,locked 2006.175.07:33:33.01/vblo/04,712.99,yes,locked 2006.175.07:33:33.01/vblo/05,744.99,yes,locked 2006.175.07:33:33.01/vblo/06,752.99,yes,locked 2006.175.07:33:33.01/vblo/07,734.99,yes,locked 2006.175.07:33:33.01/vblo/08,744.99,yes,locked 2006.175.07:33:33.16/vabw/8 2006.175.07:33:33.31/vbbw/8 2006.175.07:33:33.40/xfe/off,on,15.0 2006.175.07:33:33.78/ifatt/23,28,28,28 2006.175.07:33:34.07/fmout-gps/S +3.78E-07 2006.175.07:33:34.11:!2006.175.07:34:30 2006.175.07:34:30.00:data_valid=off 2006.175.07:34:30.00:postob 2006.175.07:34:30.21/cable/+6.4782E-03 2006.175.07:34:30.21/wx/26.02,1007.5,69 2006.175.07:34:31.07/fmout-gps/S +3.77E-07 2006.175.07:34:31.07:scan_name=175-0735,k06175,60 2006.175.07:34:31.07:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.175.07:34:31.13#flagr#flagr/antenna,new-source 2006.175.07:34:32.13:checkk5 2006.175.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:34:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:34:33.30/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:34:33.67/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:34:34.07/chk_obsdata//k5ts1/T1750733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:34:34.44/chk_obsdata//k5ts2/T1750733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:34:34.80/chk_obsdata//k5ts3/T1750733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:34:35.19/chk_obsdata//k5ts4/T1750733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:34:35.88/k5log//k5ts1_log_newline 2006.175.07:34:36.70/k5log//k5ts2_log_newline 2006.175.07:34:37.41/k5log//k5ts3_log_newline 2006.175.07:34:38.10/k5log//k5ts4_log_newline 2006.175.07:34:38.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:34:38.12:4f8m12a=1 2006.175.07:34:38.12$4f8m12a/echo=on 2006.175.07:34:38.12$4f8m12a/pcalon 2006.175.07:34:38.12$pcalon/"no phase cal control is implemented here 2006.175.07:34:38.12$4f8m12a/"tpicd=stop 2006.175.07:34:38.12$4f8m12a/vc4f8 2006.175.07:34:38.12$vc4f8/valo=1,532.99 2006.175.07:34:38.12#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.07:34:38.12#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.07:34:38.12#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:38.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:38.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:38.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:38.13#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:34:38.13#ibcon#first serial, iclass 22, count 0 2006.175.07:34:38.13#ibcon#enter sib2, iclass 22, count 0 2006.175.07:34:38.13#ibcon#flushed, iclass 22, count 0 2006.175.07:34:38.13#ibcon#about to write, iclass 22, count 0 2006.175.07:34:38.13#ibcon#wrote, iclass 22, count 0 2006.175.07:34:38.13#ibcon#about to read 3, iclass 22, count 0 2006.175.07:34:38.14#ibcon#read 3, iclass 22, count 0 2006.175.07:34:38.14#ibcon#about to read 4, iclass 22, count 0 2006.175.07:34:38.14#ibcon#read 4, iclass 22, count 0 2006.175.07:34:38.14#ibcon#about to read 5, iclass 22, count 0 2006.175.07:34:38.14#ibcon#read 5, iclass 22, count 0 2006.175.07:34:38.14#ibcon#about to read 6, iclass 22, count 0 2006.175.07:34:38.14#ibcon#read 6, iclass 22, count 0 2006.175.07:34:38.14#ibcon#end of sib2, iclass 22, count 0 2006.175.07:34:38.14#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:34:38.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:34:38.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:34:38.14#ibcon#*before write, iclass 22, count 0 2006.175.07:34:38.14#ibcon#enter sib2, iclass 22, count 0 2006.175.07:34:38.14#ibcon#flushed, iclass 22, count 0 2006.175.07:34:38.14#ibcon#about to write, iclass 22, count 0 2006.175.07:34:38.14#ibcon#wrote, iclass 22, count 0 2006.175.07:34:38.14#ibcon#about to read 3, iclass 22, count 0 2006.175.07:34:38.19#ibcon#read 3, iclass 22, count 0 2006.175.07:34:38.19#ibcon#about to read 4, iclass 22, count 0 2006.175.07:34:38.19#ibcon#read 4, iclass 22, count 0 2006.175.07:34:38.19#ibcon#about to read 5, iclass 22, count 0 2006.175.07:34:38.19#ibcon#read 5, iclass 22, count 0 2006.175.07:34:38.19#ibcon#about to read 6, iclass 22, count 0 2006.175.07:34:38.19#ibcon#read 6, iclass 22, count 0 2006.175.07:34:38.19#ibcon#end of sib2, iclass 22, count 0 2006.175.07:34:38.19#ibcon#*after write, iclass 22, count 0 2006.175.07:34:38.19#ibcon#*before return 0, iclass 22, count 0 2006.175.07:34:38.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:38.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:38.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:34:38.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:34:38.19$vc4f8/va=1,8 2006.175.07:34:38.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.07:34:38.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.07:34:38.19#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:38.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:38.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:38.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:38.19#ibcon#enter wrdev, iclass 24, count 2 2006.175.07:34:38.19#ibcon#first serial, iclass 24, count 2 2006.175.07:34:38.19#ibcon#enter sib2, iclass 24, count 2 2006.175.07:34:38.19#ibcon#flushed, iclass 24, count 2 2006.175.07:34:38.19#ibcon#about to write, iclass 24, count 2 2006.175.07:34:38.19#ibcon#wrote, iclass 24, count 2 2006.175.07:34:38.19#ibcon#about to read 3, iclass 24, count 2 2006.175.07:34:38.21#ibcon#read 3, iclass 24, count 2 2006.175.07:34:38.21#ibcon#about to read 4, iclass 24, count 2 2006.175.07:34:38.21#ibcon#read 4, iclass 24, count 2 2006.175.07:34:38.21#ibcon#about to read 5, iclass 24, count 2 2006.175.07:34:38.21#ibcon#read 5, iclass 24, count 2 2006.175.07:34:38.21#ibcon#about to read 6, iclass 24, count 2 2006.175.07:34:38.21#ibcon#read 6, iclass 24, count 2 2006.175.07:34:38.21#ibcon#end of sib2, iclass 24, count 2 2006.175.07:34:38.21#ibcon#*mode == 0, iclass 24, count 2 2006.175.07:34:38.21#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.07:34:38.21#ibcon#[25=AT01-08\r\n] 2006.175.07:34:38.21#ibcon#*before write, iclass 24, count 2 2006.175.07:34:38.21#ibcon#enter sib2, iclass 24, count 2 2006.175.07:34:38.21#ibcon#flushed, iclass 24, count 2 2006.175.07:34:38.21#ibcon#about to write, iclass 24, count 2 2006.175.07:34:38.21#ibcon#wrote, iclass 24, count 2 2006.175.07:34:38.21#ibcon#about to read 3, iclass 24, count 2 2006.175.07:34:38.24#ibcon#read 3, iclass 24, count 2 2006.175.07:34:38.24#ibcon#about to read 4, iclass 24, count 2 2006.175.07:34:38.24#ibcon#read 4, iclass 24, count 2 2006.175.07:34:38.24#ibcon#about to read 5, iclass 24, count 2 2006.175.07:34:38.24#ibcon#read 5, iclass 24, count 2 2006.175.07:34:38.24#ibcon#about to read 6, iclass 24, count 2 2006.175.07:34:38.24#ibcon#read 6, iclass 24, count 2 2006.175.07:34:38.24#ibcon#end of sib2, iclass 24, count 2 2006.175.07:34:38.24#ibcon#*after write, iclass 24, count 2 2006.175.07:34:38.24#ibcon#*before return 0, iclass 24, count 2 2006.175.07:34:38.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:38.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:38.24#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.07:34:38.24#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:38.24#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:38.36#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:38.36#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:38.36#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:34:38.36#ibcon#first serial, iclass 24, count 0 2006.175.07:34:38.36#ibcon#enter sib2, iclass 24, count 0 2006.175.07:34:38.36#ibcon#flushed, iclass 24, count 0 2006.175.07:34:38.36#ibcon#about to write, iclass 24, count 0 2006.175.07:34:38.36#ibcon#wrote, iclass 24, count 0 2006.175.07:34:38.36#ibcon#about to read 3, iclass 24, count 0 2006.175.07:34:38.38#ibcon#read 3, iclass 24, count 0 2006.175.07:34:38.38#ibcon#about to read 4, iclass 24, count 0 2006.175.07:34:38.38#ibcon#read 4, iclass 24, count 0 2006.175.07:34:38.38#ibcon#about to read 5, iclass 24, count 0 2006.175.07:34:38.38#ibcon#read 5, iclass 24, count 0 2006.175.07:34:38.38#ibcon#about to read 6, iclass 24, count 0 2006.175.07:34:38.38#ibcon#read 6, iclass 24, count 0 2006.175.07:34:38.38#ibcon#end of sib2, iclass 24, count 0 2006.175.07:34:38.38#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:34:38.38#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:34:38.38#ibcon#[25=USB\r\n] 2006.175.07:34:38.38#ibcon#*before write, iclass 24, count 0 2006.175.07:34:38.38#ibcon#enter sib2, iclass 24, count 0 2006.175.07:34:38.38#ibcon#flushed, iclass 24, count 0 2006.175.07:34:38.38#ibcon#about to write, iclass 24, count 0 2006.175.07:34:38.38#ibcon#wrote, iclass 24, count 0 2006.175.07:34:38.38#ibcon#about to read 3, iclass 24, count 0 2006.175.07:34:38.41#ibcon#read 3, iclass 24, count 0 2006.175.07:34:38.41#ibcon#about to read 4, iclass 24, count 0 2006.175.07:34:38.41#ibcon#read 4, iclass 24, count 0 2006.175.07:34:38.41#ibcon#about to read 5, iclass 24, count 0 2006.175.07:34:38.41#ibcon#read 5, iclass 24, count 0 2006.175.07:34:38.41#ibcon#about to read 6, iclass 24, count 0 2006.175.07:34:38.41#ibcon#read 6, iclass 24, count 0 2006.175.07:34:38.41#ibcon#end of sib2, iclass 24, count 0 2006.175.07:34:38.41#ibcon#*after write, iclass 24, count 0 2006.175.07:34:38.41#ibcon#*before return 0, iclass 24, count 0 2006.175.07:34:38.41#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:38.41#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:38.41#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:34:38.41#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:34:38.41$vc4f8/valo=2,572.99 2006.175.07:34:38.41#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.07:34:38.41#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.07:34:38.41#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:38.41#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:38.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:38.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:38.41#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:34:38.41#ibcon#first serial, iclass 26, count 0 2006.175.07:34:38.41#ibcon#enter sib2, iclass 26, count 0 2006.175.07:34:38.41#ibcon#flushed, iclass 26, count 0 2006.175.07:34:38.41#ibcon#about to write, iclass 26, count 0 2006.175.07:34:38.41#ibcon#wrote, iclass 26, count 0 2006.175.07:34:38.41#ibcon#about to read 3, iclass 26, count 0 2006.175.07:34:38.43#ibcon#read 3, iclass 26, count 0 2006.175.07:34:38.43#ibcon#about to read 4, iclass 26, count 0 2006.175.07:34:38.43#ibcon#read 4, iclass 26, count 0 2006.175.07:34:38.43#ibcon#about to read 5, iclass 26, count 0 2006.175.07:34:38.43#ibcon#read 5, iclass 26, count 0 2006.175.07:34:38.43#ibcon#about to read 6, iclass 26, count 0 2006.175.07:34:38.43#ibcon#read 6, iclass 26, count 0 2006.175.07:34:38.43#ibcon#end of sib2, iclass 26, count 0 2006.175.07:34:38.43#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:34:38.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:34:38.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:34:38.43#ibcon#*before write, iclass 26, count 0 2006.175.07:34:38.43#ibcon#enter sib2, iclass 26, count 0 2006.175.07:34:38.43#ibcon#flushed, iclass 26, count 0 2006.175.07:34:38.43#ibcon#about to write, iclass 26, count 0 2006.175.07:34:38.43#ibcon#wrote, iclass 26, count 0 2006.175.07:34:38.43#ibcon#about to read 3, iclass 26, count 0 2006.175.07:34:38.47#ibcon#read 3, iclass 26, count 0 2006.175.07:34:38.47#ibcon#about to read 4, iclass 26, count 0 2006.175.07:34:38.47#ibcon#read 4, iclass 26, count 0 2006.175.07:34:38.47#ibcon#about to read 5, iclass 26, count 0 2006.175.07:34:38.47#ibcon#read 5, iclass 26, count 0 2006.175.07:34:38.47#ibcon#about to read 6, iclass 26, count 0 2006.175.07:34:38.47#ibcon#read 6, iclass 26, count 0 2006.175.07:34:38.47#ibcon#end of sib2, iclass 26, count 0 2006.175.07:34:38.47#ibcon#*after write, iclass 26, count 0 2006.175.07:34:38.47#ibcon#*before return 0, iclass 26, count 0 2006.175.07:34:38.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:38.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:38.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:34:38.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:34:38.47$vc4f8/va=2,7 2006.175.07:34:38.47#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.07:34:38.47#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.07:34:38.47#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:38.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:38.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:38.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:38.53#ibcon#enter wrdev, iclass 28, count 2 2006.175.07:34:38.53#ibcon#first serial, iclass 28, count 2 2006.175.07:34:38.53#ibcon#enter sib2, iclass 28, count 2 2006.175.07:34:38.53#ibcon#flushed, iclass 28, count 2 2006.175.07:34:38.53#ibcon#about to write, iclass 28, count 2 2006.175.07:34:38.53#ibcon#wrote, iclass 28, count 2 2006.175.07:34:38.53#ibcon#about to read 3, iclass 28, count 2 2006.175.07:34:38.55#ibcon#read 3, iclass 28, count 2 2006.175.07:34:38.55#ibcon#about to read 4, iclass 28, count 2 2006.175.07:34:38.55#ibcon#read 4, iclass 28, count 2 2006.175.07:34:38.55#ibcon#about to read 5, iclass 28, count 2 2006.175.07:34:38.55#ibcon#read 5, iclass 28, count 2 2006.175.07:34:38.55#ibcon#about to read 6, iclass 28, count 2 2006.175.07:34:38.55#ibcon#read 6, iclass 28, count 2 2006.175.07:34:38.55#ibcon#end of sib2, iclass 28, count 2 2006.175.07:34:38.55#ibcon#*mode == 0, iclass 28, count 2 2006.175.07:34:38.55#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.07:34:38.55#ibcon#[25=AT02-07\r\n] 2006.175.07:34:38.55#ibcon#*before write, iclass 28, count 2 2006.175.07:34:38.55#ibcon#enter sib2, iclass 28, count 2 2006.175.07:34:38.55#ibcon#flushed, iclass 28, count 2 2006.175.07:34:38.55#ibcon#about to write, iclass 28, count 2 2006.175.07:34:38.55#ibcon#wrote, iclass 28, count 2 2006.175.07:34:38.55#ibcon#about to read 3, iclass 28, count 2 2006.175.07:34:38.58#ibcon#read 3, iclass 28, count 2 2006.175.07:34:38.58#ibcon#about to read 4, iclass 28, count 2 2006.175.07:34:38.58#ibcon#read 4, iclass 28, count 2 2006.175.07:34:38.58#ibcon#about to read 5, iclass 28, count 2 2006.175.07:34:38.58#ibcon#read 5, iclass 28, count 2 2006.175.07:34:38.58#ibcon#about to read 6, iclass 28, count 2 2006.175.07:34:38.58#ibcon#read 6, iclass 28, count 2 2006.175.07:34:38.58#ibcon#end of sib2, iclass 28, count 2 2006.175.07:34:38.58#ibcon#*after write, iclass 28, count 2 2006.175.07:34:38.58#ibcon#*before return 0, iclass 28, count 2 2006.175.07:34:38.58#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:38.58#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:38.58#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.07:34:38.58#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:38.58#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:38.70#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:38.70#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:38.70#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:34:38.70#ibcon#first serial, iclass 28, count 0 2006.175.07:34:38.70#ibcon#enter sib2, iclass 28, count 0 2006.175.07:34:38.70#ibcon#flushed, iclass 28, count 0 2006.175.07:34:38.70#ibcon#about to write, iclass 28, count 0 2006.175.07:34:38.70#ibcon#wrote, iclass 28, count 0 2006.175.07:34:38.70#ibcon#about to read 3, iclass 28, count 0 2006.175.07:34:38.72#ibcon#read 3, iclass 28, count 0 2006.175.07:34:38.72#ibcon#about to read 4, iclass 28, count 0 2006.175.07:34:38.72#ibcon#read 4, iclass 28, count 0 2006.175.07:34:38.72#ibcon#about to read 5, iclass 28, count 0 2006.175.07:34:38.72#ibcon#read 5, iclass 28, count 0 2006.175.07:34:38.72#ibcon#about to read 6, iclass 28, count 0 2006.175.07:34:38.72#ibcon#read 6, iclass 28, count 0 2006.175.07:34:38.72#ibcon#end of sib2, iclass 28, count 0 2006.175.07:34:38.72#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:34:38.72#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:34:38.72#ibcon#[25=USB\r\n] 2006.175.07:34:38.72#ibcon#*before write, iclass 28, count 0 2006.175.07:34:38.72#ibcon#enter sib2, iclass 28, count 0 2006.175.07:34:38.72#ibcon#flushed, iclass 28, count 0 2006.175.07:34:38.72#ibcon#about to write, iclass 28, count 0 2006.175.07:34:38.72#ibcon#wrote, iclass 28, count 0 2006.175.07:34:38.72#ibcon#about to read 3, iclass 28, count 0 2006.175.07:34:38.75#ibcon#read 3, iclass 28, count 0 2006.175.07:34:38.75#ibcon#about to read 4, iclass 28, count 0 2006.175.07:34:38.75#ibcon#read 4, iclass 28, count 0 2006.175.07:34:38.75#ibcon#about to read 5, iclass 28, count 0 2006.175.07:34:38.75#ibcon#read 5, iclass 28, count 0 2006.175.07:34:38.75#ibcon#about to read 6, iclass 28, count 0 2006.175.07:34:38.75#ibcon#read 6, iclass 28, count 0 2006.175.07:34:38.75#ibcon#end of sib2, iclass 28, count 0 2006.175.07:34:38.75#ibcon#*after write, iclass 28, count 0 2006.175.07:34:38.75#ibcon#*before return 0, iclass 28, count 0 2006.175.07:34:38.75#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:38.75#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:38.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:34:38.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:34:38.75$vc4f8/valo=3,672.99 2006.175.07:34:38.75#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.07:34:38.75#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.07:34:38.75#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:38.75#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:38.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:38.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:38.75#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:34:38.75#ibcon#first serial, iclass 30, count 0 2006.175.07:34:38.75#ibcon#enter sib2, iclass 30, count 0 2006.175.07:34:38.75#ibcon#flushed, iclass 30, count 0 2006.175.07:34:38.75#ibcon#about to write, iclass 30, count 0 2006.175.07:34:38.75#ibcon#wrote, iclass 30, count 0 2006.175.07:34:38.75#ibcon#about to read 3, iclass 30, count 0 2006.175.07:34:38.77#ibcon#read 3, iclass 30, count 0 2006.175.07:34:38.77#ibcon#about to read 4, iclass 30, count 0 2006.175.07:34:38.77#ibcon#read 4, iclass 30, count 0 2006.175.07:34:38.77#ibcon#about to read 5, iclass 30, count 0 2006.175.07:34:38.77#ibcon#read 5, iclass 30, count 0 2006.175.07:34:38.77#ibcon#about to read 6, iclass 30, count 0 2006.175.07:34:38.77#ibcon#read 6, iclass 30, count 0 2006.175.07:34:38.77#ibcon#end of sib2, iclass 30, count 0 2006.175.07:34:38.77#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:34:38.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:34:38.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:34:38.77#ibcon#*before write, iclass 30, count 0 2006.175.07:34:38.77#ibcon#enter sib2, iclass 30, count 0 2006.175.07:34:38.77#ibcon#flushed, iclass 30, count 0 2006.175.07:34:38.77#ibcon#about to write, iclass 30, count 0 2006.175.07:34:38.77#ibcon#wrote, iclass 30, count 0 2006.175.07:34:38.77#ibcon#about to read 3, iclass 30, count 0 2006.175.07:34:38.81#ibcon#read 3, iclass 30, count 0 2006.175.07:34:38.81#ibcon#about to read 4, iclass 30, count 0 2006.175.07:34:38.81#ibcon#read 4, iclass 30, count 0 2006.175.07:34:38.81#ibcon#about to read 5, iclass 30, count 0 2006.175.07:34:38.81#ibcon#read 5, iclass 30, count 0 2006.175.07:34:38.81#ibcon#about to read 6, iclass 30, count 0 2006.175.07:34:38.81#ibcon#read 6, iclass 30, count 0 2006.175.07:34:38.81#ibcon#end of sib2, iclass 30, count 0 2006.175.07:34:38.81#ibcon#*after write, iclass 30, count 0 2006.175.07:34:38.81#ibcon#*before return 0, iclass 30, count 0 2006.175.07:34:38.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:38.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:38.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:34:38.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:34:38.81$vc4f8/va=3,6 2006.175.07:34:38.81#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.07:34:38.81#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.07:34:38.81#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:38.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:38.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:38.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:38.87#ibcon#enter wrdev, iclass 32, count 2 2006.175.07:34:38.87#ibcon#first serial, iclass 32, count 2 2006.175.07:34:38.87#ibcon#enter sib2, iclass 32, count 2 2006.175.07:34:38.87#ibcon#flushed, iclass 32, count 2 2006.175.07:34:38.87#ibcon#about to write, iclass 32, count 2 2006.175.07:34:38.87#ibcon#wrote, iclass 32, count 2 2006.175.07:34:38.87#ibcon#about to read 3, iclass 32, count 2 2006.175.07:34:38.89#ibcon#read 3, iclass 32, count 2 2006.175.07:34:38.89#ibcon#about to read 4, iclass 32, count 2 2006.175.07:34:38.89#ibcon#read 4, iclass 32, count 2 2006.175.07:34:38.89#ibcon#about to read 5, iclass 32, count 2 2006.175.07:34:38.89#ibcon#read 5, iclass 32, count 2 2006.175.07:34:38.89#ibcon#about to read 6, iclass 32, count 2 2006.175.07:34:38.89#ibcon#read 6, iclass 32, count 2 2006.175.07:34:38.89#ibcon#end of sib2, iclass 32, count 2 2006.175.07:34:38.89#ibcon#*mode == 0, iclass 32, count 2 2006.175.07:34:38.89#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.07:34:38.89#ibcon#[25=AT03-06\r\n] 2006.175.07:34:38.89#ibcon#*before write, iclass 32, count 2 2006.175.07:34:38.89#ibcon#enter sib2, iclass 32, count 2 2006.175.07:34:38.89#ibcon#flushed, iclass 32, count 2 2006.175.07:34:38.89#ibcon#about to write, iclass 32, count 2 2006.175.07:34:38.89#ibcon#wrote, iclass 32, count 2 2006.175.07:34:38.89#ibcon#about to read 3, iclass 32, count 2 2006.175.07:34:38.92#ibcon#read 3, iclass 32, count 2 2006.175.07:34:38.92#ibcon#about to read 4, iclass 32, count 2 2006.175.07:34:38.92#ibcon#read 4, iclass 32, count 2 2006.175.07:34:38.92#ibcon#about to read 5, iclass 32, count 2 2006.175.07:34:38.92#ibcon#read 5, iclass 32, count 2 2006.175.07:34:38.92#ibcon#about to read 6, iclass 32, count 2 2006.175.07:34:38.92#ibcon#read 6, iclass 32, count 2 2006.175.07:34:38.92#ibcon#end of sib2, iclass 32, count 2 2006.175.07:34:38.92#ibcon#*after write, iclass 32, count 2 2006.175.07:34:38.92#ibcon#*before return 0, iclass 32, count 2 2006.175.07:34:38.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:38.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:38.92#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.07:34:38.92#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:38.92#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:39.04#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:39.04#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:39.04#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:34:39.04#ibcon#first serial, iclass 32, count 0 2006.175.07:34:39.04#ibcon#enter sib2, iclass 32, count 0 2006.175.07:34:39.04#ibcon#flushed, iclass 32, count 0 2006.175.07:34:39.04#ibcon#about to write, iclass 32, count 0 2006.175.07:34:39.04#ibcon#wrote, iclass 32, count 0 2006.175.07:34:39.04#ibcon#about to read 3, iclass 32, count 0 2006.175.07:34:39.06#ibcon#read 3, iclass 32, count 0 2006.175.07:34:39.06#ibcon#about to read 4, iclass 32, count 0 2006.175.07:34:39.06#ibcon#read 4, iclass 32, count 0 2006.175.07:34:39.06#ibcon#about to read 5, iclass 32, count 0 2006.175.07:34:39.06#ibcon#read 5, iclass 32, count 0 2006.175.07:34:39.06#ibcon#about to read 6, iclass 32, count 0 2006.175.07:34:39.06#ibcon#read 6, iclass 32, count 0 2006.175.07:34:39.06#ibcon#end of sib2, iclass 32, count 0 2006.175.07:34:39.06#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:34:39.06#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:34:39.06#ibcon#[25=USB\r\n] 2006.175.07:34:39.06#ibcon#*before write, iclass 32, count 0 2006.175.07:34:39.06#ibcon#enter sib2, iclass 32, count 0 2006.175.07:34:39.06#ibcon#flushed, iclass 32, count 0 2006.175.07:34:39.06#ibcon#about to write, iclass 32, count 0 2006.175.07:34:39.06#ibcon#wrote, iclass 32, count 0 2006.175.07:34:39.06#ibcon#about to read 3, iclass 32, count 0 2006.175.07:34:39.09#ibcon#read 3, iclass 32, count 0 2006.175.07:34:39.09#ibcon#about to read 4, iclass 32, count 0 2006.175.07:34:39.09#ibcon#read 4, iclass 32, count 0 2006.175.07:34:39.09#ibcon#about to read 5, iclass 32, count 0 2006.175.07:34:39.09#ibcon#read 5, iclass 32, count 0 2006.175.07:34:39.09#ibcon#about to read 6, iclass 32, count 0 2006.175.07:34:39.09#ibcon#read 6, iclass 32, count 0 2006.175.07:34:39.09#ibcon#end of sib2, iclass 32, count 0 2006.175.07:34:39.09#ibcon#*after write, iclass 32, count 0 2006.175.07:34:39.09#ibcon#*before return 0, iclass 32, count 0 2006.175.07:34:39.09#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:39.09#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:39.09#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:34:39.09#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:34:39.09$vc4f8/valo=4,832.99 2006.175.07:34:39.09#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.07:34:39.09#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.07:34:39.09#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:39.09#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:39.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:39.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:39.09#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:34:39.09#ibcon#first serial, iclass 34, count 0 2006.175.07:34:39.09#ibcon#enter sib2, iclass 34, count 0 2006.175.07:34:39.09#ibcon#flushed, iclass 34, count 0 2006.175.07:34:39.09#ibcon#about to write, iclass 34, count 0 2006.175.07:34:39.09#ibcon#wrote, iclass 34, count 0 2006.175.07:34:39.09#ibcon#about to read 3, iclass 34, count 0 2006.175.07:34:39.11#ibcon#read 3, iclass 34, count 0 2006.175.07:34:39.11#ibcon#about to read 4, iclass 34, count 0 2006.175.07:34:39.11#ibcon#read 4, iclass 34, count 0 2006.175.07:34:39.11#ibcon#about to read 5, iclass 34, count 0 2006.175.07:34:39.11#ibcon#read 5, iclass 34, count 0 2006.175.07:34:39.11#ibcon#about to read 6, iclass 34, count 0 2006.175.07:34:39.11#ibcon#read 6, iclass 34, count 0 2006.175.07:34:39.11#ibcon#end of sib2, iclass 34, count 0 2006.175.07:34:39.11#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:34:39.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:34:39.11#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:34:39.11#ibcon#*before write, iclass 34, count 0 2006.175.07:34:39.11#ibcon#enter sib2, iclass 34, count 0 2006.175.07:34:39.11#ibcon#flushed, iclass 34, count 0 2006.175.07:34:39.11#ibcon#about to write, iclass 34, count 0 2006.175.07:34:39.11#ibcon#wrote, iclass 34, count 0 2006.175.07:34:39.11#ibcon#about to read 3, iclass 34, count 0 2006.175.07:34:39.15#ibcon#read 3, iclass 34, count 0 2006.175.07:34:39.15#ibcon#about to read 4, iclass 34, count 0 2006.175.07:34:39.15#ibcon#read 4, iclass 34, count 0 2006.175.07:34:39.15#ibcon#about to read 5, iclass 34, count 0 2006.175.07:34:39.15#ibcon#read 5, iclass 34, count 0 2006.175.07:34:39.15#ibcon#about to read 6, iclass 34, count 0 2006.175.07:34:39.15#ibcon#read 6, iclass 34, count 0 2006.175.07:34:39.15#ibcon#end of sib2, iclass 34, count 0 2006.175.07:34:39.15#ibcon#*after write, iclass 34, count 0 2006.175.07:34:39.15#ibcon#*before return 0, iclass 34, count 0 2006.175.07:34:39.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:39.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:39.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:34:39.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:34:39.15$vc4f8/va=4,7 2006.175.07:34:39.15#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.07:34:39.15#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.07:34:39.15#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:39.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:39.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:39.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:39.21#ibcon#enter wrdev, iclass 36, count 2 2006.175.07:34:39.21#ibcon#first serial, iclass 36, count 2 2006.175.07:34:39.21#ibcon#enter sib2, iclass 36, count 2 2006.175.07:34:39.21#ibcon#flushed, iclass 36, count 2 2006.175.07:34:39.21#ibcon#about to write, iclass 36, count 2 2006.175.07:34:39.21#ibcon#wrote, iclass 36, count 2 2006.175.07:34:39.21#ibcon#about to read 3, iclass 36, count 2 2006.175.07:34:39.23#ibcon#read 3, iclass 36, count 2 2006.175.07:34:39.23#ibcon#about to read 4, iclass 36, count 2 2006.175.07:34:39.23#ibcon#read 4, iclass 36, count 2 2006.175.07:34:39.23#ibcon#about to read 5, iclass 36, count 2 2006.175.07:34:39.23#ibcon#read 5, iclass 36, count 2 2006.175.07:34:39.23#ibcon#about to read 6, iclass 36, count 2 2006.175.07:34:39.23#ibcon#read 6, iclass 36, count 2 2006.175.07:34:39.23#ibcon#end of sib2, iclass 36, count 2 2006.175.07:34:39.23#ibcon#*mode == 0, iclass 36, count 2 2006.175.07:34:39.23#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.07:34:39.23#ibcon#[25=AT04-07\r\n] 2006.175.07:34:39.23#ibcon#*before write, iclass 36, count 2 2006.175.07:34:39.23#ibcon#enter sib2, iclass 36, count 2 2006.175.07:34:39.23#ibcon#flushed, iclass 36, count 2 2006.175.07:34:39.23#ibcon#about to write, iclass 36, count 2 2006.175.07:34:39.23#ibcon#wrote, iclass 36, count 2 2006.175.07:34:39.23#ibcon#about to read 3, iclass 36, count 2 2006.175.07:34:39.26#ibcon#read 3, iclass 36, count 2 2006.175.07:34:39.26#ibcon#about to read 4, iclass 36, count 2 2006.175.07:34:39.26#ibcon#read 4, iclass 36, count 2 2006.175.07:34:39.26#ibcon#about to read 5, iclass 36, count 2 2006.175.07:34:39.26#ibcon#read 5, iclass 36, count 2 2006.175.07:34:39.26#ibcon#about to read 6, iclass 36, count 2 2006.175.07:34:39.26#ibcon#read 6, iclass 36, count 2 2006.175.07:34:39.26#ibcon#end of sib2, iclass 36, count 2 2006.175.07:34:39.26#ibcon#*after write, iclass 36, count 2 2006.175.07:34:39.26#ibcon#*before return 0, iclass 36, count 2 2006.175.07:34:39.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:39.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:39.26#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.07:34:39.26#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:39.26#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:39.38#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:39.38#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:39.38#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:34:39.38#ibcon#first serial, iclass 36, count 0 2006.175.07:34:39.38#ibcon#enter sib2, iclass 36, count 0 2006.175.07:34:39.38#ibcon#flushed, iclass 36, count 0 2006.175.07:34:39.38#ibcon#about to write, iclass 36, count 0 2006.175.07:34:39.38#ibcon#wrote, iclass 36, count 0 2006.175.07:34:39.38#ibcon#about to read 3, iclass 36, count 0 2006.175.07:34:39.40#ibcon#read 3, iclass 36, count 0 2006.175.07:34:39.40#ibcon#about to read 4, iclass 36, count 0 2006.175.07:34:39.40#ibcon#read 4, iclass 36, count 0 2006.175.07:34:39.40#ibcon#about to read 5, iclass 36, count 0 2006.175.07:34:39.40#ibcon#read 5, iclass 36, count 0 2006.175.07:34:39.40#ibcon#about to read 6, iclass 36, count 0 2006.175.07:34:39.40#ibcon#read 6, iclass 36, count 0 2006.175.07:34:39.40#ibcon#end of sib2, iclass 36, count 0 2006.175.07:34:39.40#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:34:39.40#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:34:39.40#ibcon#[25=USB\r\n] 2006.175.07:34:39.40#ibcon#*before write, iclass 36, count 0 2006.175.07:34:39.40#ibcon#enter sib2, iclass 36, count 0 2006.175.07:34:39.40#ibcon#flushed, iclass 36, count 0 2006.175.07:34:39.40#ibcon#about to write, iclass 36, count 0 2006.175.07:34:39.40#ibcon#wrote, iclass 36, count 0 2006.175.07:34:39.40#ibcon#about to read 3, iclass 36, count 0 2006.175.07:34:39.43#ibcon#read 3, iclass 36, count 0 2006.175.07:34:39.43#ibcon#about to read 4, iclass 36, count 0 2006.175.07:34:39.43#ibcon#read 4, iclass 36, count 0 2006.175.07:34:39.43#ibcon#about to read 5, iclass 36, count 0 2006.175.07:34:39.43#ibcon#read 5, iclass 36, count 0 2006.175.07:34:39.43#ibcon#about to read 6, iclass 36, count 0 2006.175.07:34:39.43#ibcon#read 6, iclass 36, count 0 2006.175.07:34:39.43#ibcon#end of sib2, iclass 36, count 0 2006.175.07:34:39.43#ibcon#*after write, iclass 36, count 0 2006.175.07:34:39.43#ibcon#*before return 0, iclass 36, count 0 2006.175.07:34:39.43#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:39.43#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:39.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:34:39.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:34:39.43$vc4f8/valo=5,652.99 2006.175.07:34:39.43#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:34:39.43#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:34:39.43#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:39.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:39.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:39.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:39.43#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:34:39.43#ibcon#first serial, iclass 38, count 0 2006.175.07:34:39.43#ibcon#enter sib2, iclass 38, count 0 2006.175.07:34:39.43#ibcon#flushed, iclass 38, count 0 2006.175.07:34:39.43#ibcon#about to write, iclass 38, count 0 2006.175.07:34:39.43#ibcon#wrote, iclass 38, count 0 2006.175.07:34:39.43#ibcon#about to read 3, iclass 38, count 0 2006.175.07:34:39.45#ibcon#read 3, iclass 38, count 0 2006.175.07:34:39.45#ibcon#about to read 4, iclass 38, count 0 2006.175.07:34:39.45#ibcon#read 4, iclass 38, count 0 2006.175.07:34:39.45#ibcon#about to read 5, iclass 38, count 0 2006.175.07:34:39.45#ibcon#read 5, iclass 38, count 0 2006.175.07:34:39.45#ibcon#about to read 6, iclass 38, count 0 2006.175.07:34:39.45#ibcon#read 6, iclass 38, count 0 2006.175.07:34:39.45#ibcon#end of sib2, iclass 38, count 0 2006.175.07:34:39.45#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:34:39.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:34:39.45#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:34:39.45#ibcon#*before write, iclass 38, count 0 2006.175.07:34:39.45#ibcon#enter sib2, iclass 38, count 0 2006.175.07:34:39.45#ibcon#flushed, iclass 38, count 0 2006.175.07:34:39.45#ibcon#about to write, iclass 38, count 0 2006.175.07:34:39.45#ibcon#wrote, iclass 38, count 0 2006.175.07:34:39.45#ibcon#about to read 3, iclass 38, count 0 2006.175.07:34:39.49#ibcon#read 3, iclass 38, count 0 2006.175.07:34:39.49#ibcon#about to read 4, iclass 38, count 0 2006.175.07:34:39.49#ibcon#read 4, iclass 38, count 0 2006.175.07:34:39.49#ibcon#about to read 5, iclass 38, count 0 2006.175.07:34:39.49#ibcon#read 5, iclass 38, count 0 2006.175.07:34:39.49#ibcon#about to read 6, iclass 38, count 0 2006.175.07:34:39.49#ibcon#read 6, iclass 38, count 0 2006.175.07:34:39.49#ibcon#end of sib2, iclass 38, count 0 2006.175.07:34:39.49#ibcon#*after write, iclass 38, count 0 2006.175.07:34:39.49#ibcon#*before return 0, iclass 38, count 0 2006.175.07:34:39.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:39.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:39.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:34:39.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:34:39.49$vc4f8/va=5,7 2006.175.07:34:39.49#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.07:34:39.49#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.07:34:39.49#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:39.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:39.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:39.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:39.55#ibcon#enter wrdev, iclass 40, count 2 2006.175.07:34:39.55#ibcon#first serial, iclass 40, count 2 2006.175.07:34:39.55#ibcon#enter sib2, iclass 40, count 2 2006.175.07:34:39.55#ibcon#flushed, iclass 40, count 2 2006.175.07:34:39.55#ibcon#about to write, iclass 40, count 2 2006.175.07:34:39.55#ibcon#wrote, iclass 40, count 2 2006.175.07:34:39.55#ibcon#about to read 3, iclass 40, count 2 2006.175.07:34:39.57#ibcon#read 3, iclass 40, count 2 2006.175.07:34:39.57#ibcon#about to read 4, iclass 40, count 2 2006.175.07:34:39.57#ibcon#read 4, iclass 40, count 2 2006.175.07:34:39.57#ibcon#about to read 5, iclass 40, count 2 2006.175.07:34:39.57#ibcon#read 5, iclass 40, count 2 2006.175.07:34:39.57#ibcon#about to read 6, iclass 40, count 2 2006.175.07:34:39.57#ibcon#read 6, iclass 40, count 2 2006.175.07:34:39.57#ibcon#end of sib2, iclass 40, count 2 2006.175.07:34:39.57#ibcon#*mode == 0, iclass 40, count 2 2006.175.07:34:39.57#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.07:34:39.57#ibcon#[25=AT05-07\r\n] 2006.175.07:34:39.57#ibcon#*before write, iclass 40, count 2 2006.175.07:34:39.57#ibcon#enter sib2, iclass 40, count 2 2006.175.07:34:39.57#ibcon#flushed, iclass 40, count 2 2006.175.07:34:39.57#ibcon#about to write, iclass 40, count 2 2006.175.07:34:39.57#ibcon#wrote, iclass 40, count 2 2006.175.07:34:39.57#ibcon#about to read 3, iclass 40, count 2 2006.175.07:34:39.60#ibcon#read 3, iclass 40, count 2 2006.175.07:34:39.60#ibcon#about to read 4, iclass 40, count 2 2006.175.07:34:39.60#ibcon#read 4, iclass 40, count 2 2006.175.07:34:39.60#ibcon#about to read 5, iclass 40, count 2 2006.175.07:34:39.60#ibcon#read 5, iclass 40, count 2 2006.175.07:34:39.60#ibcon#about to read 6, iclass 40, count 2 2006.175.07:34:39.60#ibcon#read 6, iclass 40, count 2 2006.175.07:34:39.60#ibcon#end of sib2, iclass 40, count 2 2006.175.07:34:39.60#ibcon#*after write, iclass 40, count 2 2006.175.07:34:39.60#ibcon#*before return 0, iclass 40, count 2 2006.175.07:34:39.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:39.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:39.60#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.07:34:39.60#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:39.60#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:39.72#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:39.72#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:39.72#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:34:39.72#ibcon#first serial, iclass 40, count 0 2006.175.07:34:39.72#ibcon#enter sib2, iclass 40, count 0 2006.175.07:34:39.72#ibcon#flushed, iclass 40, count 0 2006.175.07:34:39.72#ibcon#about to write, iclass 40, count 0 2006.175.07:34:39.72#ibcon#wrote, iclass 40, count 0 2006.175.07:34:39.72#ibcon#about to read 3, iclass 40, count 0 2006.175.07:34:39.74#ibcon#read 3, iclass 40, count 0 2006.175.07:34:39.74#ibcon#about to read 4, iclass 40, count 0 2006.175.07:34:39.74#ibcon#read 4, iclass 40, count 0 2006.175.07:34:39.74#ibcon#about to read 5, iclass 40, count 0 2006.175.07:34:39.74#ibcon#read 5, iclass 40, count 0 2006.175.07:34:39.74#ibcon#about to read 6, iclass 40, count 0 2006.175.07:34:39.74#ibcon#read 6, iclass 40, count 0 2006.175.07:34:39.74#ibcon#end of sib2, iclass 40, count 0 2006.175.07:34:39.74#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:34:39.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:34:39.74#ibcon#[25=USB\r\n] 2006.175.07:34:39.74#ibcon#*before write, iclass 40, count 0 2006.175.07:34:39.74#ibcon#enter sib2, iclass 40, count 0 2006.175.07:34:39.74#ibcon#flushed, iclass 40, count 0 2006.175.07:34:39.74#ibcon#about to write, iclass 40, count 0 2006.175.07:34:39.74#ibcon#wrote, iclass 40, count 0 2006.175.07:34:39.74#ibcon#about to read 3, iclass 40, count 0 2006.175.07:34:39.77#ibcon#read 3, iclass 40, count 0 2006.175.07:34:39.77#ibcon#about to read 4, iclass 40, count 0 2006.175.07:34:39.77#ibcon#read 4, iclass 40, count 0 2006.175.07:34:39.77#ibcon#about to read 5, iclass 40, count 0 2006.175.07:34:39.77#ibcon#read 5, iclass 40, count 0 2006.175.07:34:39.77#ibcon#about to read 6, iclass 40, count 0 2006.175.07:34:39.77#ibcon#read 6, iclass 40, count 0 2006.175.07:34:39.77#ibcon#end of sib2, iclass 40, count 0 2006.175.07:34:39.77#ibcon#*after write, iclass 40, count 0 2006.175.07:34:39.77#ibcon#*before return 0, iclass 40, count 0 2006.175.07:34:39.77#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:39.77#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:39.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:34:39.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:34:39.77$vc4f8/valo=6,772.99 2006.175.07:34:39.77#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:34:39.77#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:34:39.77#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:39.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:39.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:39.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:39.77#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:34:39.77#ibcon#first serial, iclass 4, count 0 2006.175.07:34:39.77#ibcon#enter sib2, iclass 4, count 0 2006.175.07:34:39.77#ibcon#flushed, iclass 4, count 0 2006.175.07:34:39.77#ibcon#about to write, iclass 4, count 0 2006.175.07:34:39.77#ibcon#wrote, iclass 4, count 0 2006.175.07:34:39.77#ibcon#about to read 3, iclass 4, count 0 2006.175.07:34:39.79#ibcon#read 3, iclass 4, count 0 2006.175.07:34:39.79#ibcon#about to read 4, iclass 4, count 0 2006.175.07:34:39.79#ibcon#read 4, iclass 4, count 0 2006.175.07:34:39.79#ibcon#about to read 5, iclass 4, count 0 2006.175.07:34:39.79#ibcon#read 5, iclass 4, count 0 2006.175.07:34:39.79#ibcon#about to read 6, iclass 4, count 0 2006.175.07:34:39.79#ibcon#read 6, iclass 4, count 0 2006.175.07:34:39.79#ibcon#end of sib2, iclass 4, count 0 2006.175.07:34:39.79#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:34:39.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:34:39.79#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:34:39.79#ibcon#*before write, iclass 4, count 0 2006.175.07:34:39.79#ibcon#enter sib2, iclass 4, count 0 2006.175.07:34:39.79#ibcon#flushed, iclass 4, count 0 2006.175.07:34:39.79#ibcon#about to write, iclass 4, count 0 2006.175.07:34:39.79#ibcon#wrote, iclass 4, count 0 2006.175.07:34:39.79#ibcon#about to read 3, iclass 4, count 0 2006.175.07:34:39.83#ibcon#read 3, iclass 4, count 0 2006.175.07:34:39.83#ibcon#about to read 4, iclass 4, count 0 2006.175.07:34:39.83#ibcon#read 4, iclass 4, count 0 2006.175.07:34:39.83#ibcon#about to read 5, iclass 4, count 0 2006.175.07:34:39.83#ibcon#read 5, iclass 4, count 0 2006.175.07:34:39.83#ibcon#about to read 6, iclass 4, count 0 2006.175.07:34:39.83#ibcon#read 6, iclass 4, count 0 2006.175.07:34:39.83#ibcon#end of sib2, iclass 4, count 0 2006.175.07:34:39.83#ibcon#*after write, iclass 4, count 0 2006.175.07:34:39.83#ibcon#*before return 0, iclass 4, count 0 2006.175.07:34:39.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:39.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:39.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:34:39.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:34:39.83$vc4f8/va=6,6 2006.175.07:34:39.83#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.07:34:39.83#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.07:34:39.83#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:39.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:34:39.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:34:39.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:34:39.89#ibcon#enter wrdev, iclass 6, count 2 2006.175.07:34:39.89#ibcon#first serial, iclass 6, count 2 2006.175.07:34:39.89#ibcon#enter sib2, iclass 6, count 2 2006.175.07:34:39.89#ibcon#flushed, iclass 6, count 2 2006.175.07:34:39.89#ibcon#about to write, iclass 6, count 2 2006.175.07:34:39.89#ibcon#wrote, iclass 6, count 2 2006.175.07:34:39.89#ibcon#about to read 3, iclass 6, count 2 2006.175.07:34:39.91#ibcon#read 3, iclass 6, count 2 2006.175.07:34:39.91#ibcon#about to read 4, iclass 6, count 2 2006.175.07:34:39.91#ibcon#read 4, iclass 6, count 2 2006.175.07:34:39.91#ibcon#about to read 5, iclass 6, count 2 2006.175.07:34:39.91#ibcon#read 5, iclass 6, count 2 2006.175.07:34:39.91#ibcon#about to read 6, iclass 6, count 2 2006.175.07:34:39.91#ibcon#read 6, iclass 6, count 2 2006.175.07:34:39.91#ibcon#end of sib2, iclass 6, count 2 2006.175.07:34:39.91#ibcon#*mode == 0, iclass 6, count 2 2006.175.07:34:39.91#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.07:34:39.91#ibcon#[25=AT06-06\r\n] 2006.175.07:34:39.91#ibcon#*before write, iclass 6, count 2 2006.175.07:34:39.91#ibcon#enter sib2, iclass 6, count 2 2006.175.07:34:39.91#ibcon#flushed, iclass 6, count 2 2006.175.07:34:39.91#ibcon#about to write, iclass 6, count 2 2006.175.07:34:39.91#ibcon#wrote, iclass 6, count 2 2006.175.07:34:39.91#ibcon#about to read 3, iclass 6, count 2 2006.175.07:34:39.94#ibcon#read 3, iclass 6, count 2 2006.175.07:34:39.94#ibcon#about to read 4, iclass 6, count 2 2006.175.07:34:39.94#ibcon#read 4, iclass 6, count 2 2006.175.07:34:39.94#ibcon#about to read 5, iclass 6, count 2 2006.175.07:34:39.94#ibcon#read 5, iclass 6, count 2 2006.175.07:34:39.94#ibcon#about to read 6, iclass 6, count 2 2006.175.07:34:39.94#ibcon#read 6, iclass 6, count 2 2006.175.07:34:39.94#ibcon#end of sib2, iclass 6, count 2 2006.175.07:34:39.94#ibcon#*after write, iclass 6, count 2 2006.175.07:34:39.94#ibcon#*before return 0, iclass 6, count 2 2006.175.07:34:39.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:34:39.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:34:39.94#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.07:34:39.94#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:39.94#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:34:40.06#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:34:40.06#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:34:40.06#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:34:40.06#ibcon#first serial, iclass 6, count 0 2006.175.07:34:40.06#ibcon#enter sib2, iclass 6, count 0 2006.175.07:34:40.06#ibcon#flushed, iclass 6, count 0 2006.175.07:34:40.06#ibcon#about to write, iclass 6, count 0 2006.175.07:34:40.06#ibcon#wrote, iclass 6, count 0 2006.175.07:34:40.06#ibcon#about to read 3, iclass 6, count 0 2006.175.07:34:40.08#ibcon#read 3, iclass 6, count 0 2006.175.07:34:40.08#ibcon#about to read 4, iclass 6, count 0 2006.175.07:34:40.08#ibcon#read 4, iclass 6, count 0 2006.175.07:34:40.08#ibcon#about to read 5, iclass 6, count 0 2006.175.07:34:40.08#ibcon#read 5, iclass 6, count 0 2006.175.07:34:40.08#ibcon#about to read 6, iclass 6, count 0 2006.175.07:34:40.08#ibcon#read 6, iclass 6, count 0 2006.175.07:34:40.08#ibcon#end of sib2, iclass 6, count 0 2006.175.07:34:40.08#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:34:40.08#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:34:40.08#ibcon#[25=USB\r\n] 2006.175.07:34:40.08#ibcon#*before write, iclass 6, count 0 2006.175.07:34:40.08#ibcon#enter sib2, iclass 6, count 0 2006.175.07:34:40.08#ibcon#flushed, iclass 6, count 0 2006.175.07:34:40.08#ibcon#about to write, iclass 6, count 0 2006.175.07:34:40.08#ibcon#wrote, iclass 6, count 0 2006.175.07:34:40.08#ibcon#about to read 3, iclass 6, count 0 2006.175.07:34:40.11#ibcon#read 3, iclass 6, count 0 2006.175.07:34:40.11#ibcon#about to read 4, iclass 6, count 0 2006.175.07:34:40.11#ibcon#read 4, iclass 6, count 0 2006.175.07:34:40.11#ibcon#about to read 5, iclass 6, count 0 2006.175.07:34:40.11#ibcon#read 5, iclass 6, count 0 2006.175.07:34:40.11#ibcon#about to read 6, iclass 6, count 0 2006.175.07:34:40.11#ibcon#read 6, iclass 6, count 0 2006.175.07:34:40.11#ibcon#end of sib2, iclass 6, count 0 2006.175.07:34:40.11#ibcon#*after write, iclass 6, count 0 2006.175.07:34:40.11#ibcon#*before return 0, iclass 6, count 0 2006.175.07:34:40.11#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:34:40.11#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:34:40.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:34:40.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:34:40.11$vc4f8/valo=7,832.99 2006.175.07:34:40.11#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.07:34:40.11#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.07:34:40.11#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:40.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:34:40.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:34:40.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:34:40.11#ibcon#enter wrdev, iclass 10, count 0 2006.175.07:34:40.11#ibcon#first serial, iclass 10, count 0 2006.175.07:34:40.11#ibcon#enter sib2, iclass 10, count 0 2006.175.07:34:40.11#ibcon#flushed, iclass 10, count 0 2006.175.07:34:40.11#ibcon#about to write, iclass 10, count 0 2006.175.07:34:40.11#ibcon#wrote, iclass 10, count 0 2006.175.07:34:40.11#ibcon#about to read 3, iclass 10, count 0 2006.175.07:34:40.13#ibcon#read 3, iclass 10, count 0 2006.175.07:34:40.13#ibcon#about to read 4, iclass 10, count 0 2006.175.07:34:40.13#ibcon#read 4, iclass 10, count 0 2006.175.07:34:40.13#ibcon#about to read 5, iclass 10, count 0 2006.175.07:34:40.13#ibcon#read 5, iclass 10, count 0 2006.175.07:34:40.13#ibcon#about to read 6, iclass 10, count 0 2006.175.07:34:40.13#ibcon#read 6, iclass 10, count 0 2006.175.07:34:40.13#ibcon#end of sib2, iclass 10, count 0 2006.175.07:34:40.13#ibcon#*mode == 0, iclass 10, count 0 2006.175.07:34:40.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.07:34:40.13#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:34:40.13#ibcon#*before write, iclass 10, count 0 2006.175.07:34:40.13#ibcon#enter sib2, iclass 10, count 0 2006.175.07:34:40.13#ibcon#flushed, iclass 10, count 0 2006.175.07:34:40.13#ibcon#about to write, iclass 10, count 0 2006.175.07:34:40.13#ibcon#wrote, iclass 10, count 0 2006.175.07:34:40.13#ibcon#about to read 3, iclass 10, count 0 2006.175.07:34:40.17#ibcon#read 3, iclass 10, count 0 2006.175.07:34:40.17#ibcon#about to read 4, iclass 10, count 0 2006.175.07:34:40.17#ibcon#read 4, iclass 10, count 0 2006.175.07:34:40.17#ibcon#about to read 5, iclass 10, count 0 2006.175.07:34:40.17#ibcon#read 5, iclass 10, count 0 2006.175.07:34:40.17#ibcon#about to read 6, iclass 10, count 0 2006.175.07:34:40.17#ibcon#read 6, iclass 10, count 0 2006.175.07:34:40.17#ibcon#end of sib2, iclass 10, count 0 2006.175.07:34:40.17#ibcon#*after write, iclass 10, count 0 2006.175.07:34:40.17#ibcon#*before return 0, iclass 10, count 0 2006.175.07:34:40.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:34:40.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:34:40.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.07:34:40.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.07:34:40.17$vc4f8/va=7,6 2006.175.07:34:40.17#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.07:34:40.17#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.07:34:40.17#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:40.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:34:40.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:34:40.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:34:40.23#ibcon#enter wrdev, iclass 12, count 2 2006.175.07:34:40.23#ibcon#first serial, iclass 12, count 2 2006.175.07:34:40.23#ibcon#enter sib2, iclass 12, count 2 2006.175.07:34:40.23#ibcon#flushed, iclass 12, count 2 2006.175.07:34:40.23#ibcon#about to write, iclass 12, count 2 2006.175.07:34:40.23#ibcon#wrote, iclass 12, count 2 2006.175.07:34:40.23#ibcon#about to read 3, iclass 12, count 2 2006.175.07:34:40.25#ibcon#read 3, iclass 12, count 2 2006.175.07:34:40.25#ibcon#about to read 4, iclass 12, count 2 2006.175.07:34:40.25#ibcon#read 4, iclass 12, count 2 2006.175.07:34:40.25#ibcon#about to read 5, iclass 12, count 2 2006.175.07:34:40.25#ibcon#read 5, iclass 12, count 2 2006.175.07:34:40.25#ibcon#about to read 6, iclass 12, count 2 2006.175.07:34:40.25#ibcon#read 6, iclass 12, count 2 2006.175.07:34:40.25#ibcon#end of sib2, iclass 12, count 2 2006.175.07:34:40.25#ibcon#*mode == 0, iclass 12, count 2 2006.175.07:34:40.25#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.07:34:40.25#ibcon#[25=AT07-06\r\n] 2006.175.07:34:40.25#ibcon#*before write, iclass 12, count 2 2006.175.07:34:40.25#ibcon#enter sib2, iclass 12, count 2 2006.175.07:34:40.25#ibcon#flushed, iclass 12, count 2 2006.175.07:34:40.25#ibcon#about to write, iclass 12, count 2 2006.175.07:34:40.25#ibcon#wrote, iclass 12, count 2 2006.175.07:34:40.25#ibcon#about to read 3, iclass 12, count 2 2006.175.07:34:40.28#ibcon#read 3, iclass 12, count 2 2006.175.07:34:40.28#ibcon#about to read 4, iclass 12, count 2 2006.175.07:34:40.28#ibcon#read 4, iclass 12, count 2 2006.175.07:34:40.28#ibcon#about to read 5, iclass 12, count 2 2006.175.07:34:40.28#ibcon#read 5, iclass 12, count 2 2006.175.07:34:40.28#ibcon#about to read 6, iclass 12, count 2 2006.175.07:34:40.28#ibcon#read 6, iclass 12, count 2 2006.175.07:34:40.28#ibcon#end of sib2, iclass 12, count 2 2006.175.07:34:40.28#ibcon#*after write, iclass 12, count 2 2006.175.07:34:40.28#ibcon#*before return 0, iclass 12, count 2 2006.175.07:34:40.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:34:40.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:34:40.28#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.07:34:40.28#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:40.28#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:34:40.41#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:34:40.41#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:34:40.41#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:34:40.41#ibcon#first serial, iclass 12, count 0 2006.175.07:34:40.41#ibcon#enter sib2, iclass 12, count 0 2006.175.07:34:40.41#ibcon#flushed, iclass 12, count 0 2006.175.07:34:40.41#ibcon#about to write, iclass 12, count 0 2006.175.07:34:40.41#ibcon#wrote, iclass 12, count 0 2006.175.07:34:40.41#ibcon#about to read 3, iclass 12, count 0 2006.175.07:34:40.43#ibcon#read 3, iclass 12, count 0 2006.175.07:34:40.43#ibcon#about to read 4, iclass 12, count 0 2006.175.07:34:40.43#ibcon#read 4, iclass 12, count 0 2006.175.07:34:40.43#ibcon#about to read 5, iclass 12, count 0 2006.175.07:34:40.43#ibcon#read 5, iclass 12, count 0 2006.175.07:34:40.43#ibcon#about to read 6, iclass 12, count 0 2006.175.07:34:40.43#ibcon#read 6, iclass 12, count 0 2006.175.07:34:40.43#ibcon#end of sib2, iclass 12, count 0 2006.175.07:34:40.43#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:34:40.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:34:40.43#ibcon#[25=USB\r\n] 2006.175.07:34:40.43#ibcon#*before write, iclass 12, count 0 2006.175.07:34:40.43#ibcon#enter sib2, iclass 12, count 0 2006.175.07:34:40.43#ibcon#flushed, iclass 12, count 0 2006.175.07:34:40.43#ibcon#about to write, iclass 12, count 0 2006.175.07:34:40.43#ibcon#wrote, iclass 12, count 0 2006.175.07:34:40.43#ibcon#about to read 3, iclass 12, count 0 2006.175.07:34:40.46#ibcon#read 3, iclass 12, count 0 2006.175.07:34:40.46#ibcon#about to read 4, iclass 12, count 0 2006.175.07:34:40.46#ibcon#read 4, iclass 12, count 0 2006.175.07:34:40.46#ibcon#about to read 5, iclass 12, count 0 2006.175.07:34:40.46#ibcon#read 5, iclass 12, count 0 2006.175.07:34:40.46#ibcon#about to read 6, iclass 12, count 0 2006.175.07:34:40.46#ibcon#read 6, iclass 12, count 0 2006.175.07:34:40.46#ibcon#end of sib2, iclass 12, count 0 2006.175.07:34:40.46#ibcon#*after write, iclass 12, count 0 2006.175.07:34:40.46#ibcon#*before return 0, iclass 12, count 0 2006.175.07:34:40.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:34:40.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:34:40.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:34:40.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:34:40.46$vc4f8/valo=8,852.99 2006.175.07:34:40.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.07:34:40.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.07:34:40.46#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:40.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:34:40.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:34:40.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:34:40.46#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:34:40.46#ibcon#first serial, iclass 14, count 0 2006.175.07:34:40.46#ibcon#enter sib2, iclass 14, count 0 2006.175.07:34:40.46#ibcon#flushed, iclass 14, count 0 2006.175.07:34:40.46#ibcon#about to write, iclass 14, count 0 2006.175.07:34:40.46#ibcon#wrote, iclass 14, count 0 2006.175.07:34:40.46#ibcon#about to read 3, iclass 14, count 0 2006.175.07:34:40.48#ibcon#read 3, iclass 14, count 0 2006.175.07:34:40.48#ibcon#about to read 4, iclass 14, count 0 2006.175.07:34:40.48#ibcon#read 4, iclass 14, count 0 2006.175.07:34:40.48#ibcon#about to read 5, iclass 14, count 0 2006.175.07:34:40.48#ibcon#read 5, iclass 14, count 0 2006.175.07:34:40.48#ibcon#about to read 6, iclass 14, count 0 2006.175.07:34:40.48#ibcon#read 6, iclass 14, count 0 2006.175.07:34:40.48#ibcon#end of sib2, iclass 14, count 0 2006.175.07:34:40.48#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:34:40.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:34:40.48#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:34:40.48#ibcon#*before write, iclass 14, count 0 2006.175.07:34:40.48#ibcon#enter sib2, iclass 14, count 0 2006.175.07:34:40.48#ibcon#flushed, iclass 14, count 0 2006.175.07:34:40.48#ibcon#about to write, iclass 14, count 0 2006.175.07:34:40.48#ibcon#wrote, iclass 14, count 0 2006.175.07:34:40.48#ibcon#about to read 3, iclass 14, count 0 2006.175.07:34:40.52#ibcon#read 3, iclass 14, count 0 2006.175.07:34:40.52#ibcon#about to read 4, iclass 14, count 0 2006.175.07:34:40.52#ibcon#read 4, iclass 14, count 0 2006.175.07:34:40.52#ibcon#about to read 5, iclass 14, count 0 2006.175.07:34:40.52#ibcon#read 5, iclass 14, count 0 2006.175.07:34:40.52#ibcon#about to read 6, iclass 14, count 0 2006.175.07:34:40.52#ibcon#read 6, iclass 14, count 0 2006.175.07:34:40.52#ibcon#end of sib2, iclass 14, count 0 2006.175.07:34:40.52#ibcon#*after write, iclass 14, count 0 2006.175.07:34:40.52#ibcon#*before return 0, iclass 14, count 0 2006.175.07:34:40.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:34:40.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:34:40.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:34:40.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:34:40.52$vc4f8/va=8,6 2006.175.07:34:40.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.07:34:40.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.07:34:40.52#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:40.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:34:40.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:34:40.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:34:40.58#ibcon#enter wrdev, iclass 16, count 2 2006.175.07:34:40.58#ibcon#first serial, iclass 16, count 2 2006.175.07:34:40.58#ibcon#enter sib2, iclass 16, count 2 2006.175.07:34:40.58#ibcon#flushed, iclass 16, count 2 2006.175.07:34:40.58#ibcon#about to write, iclass 16, count 2 2006.175.07:34:40.58#ibcon#wrote, iclass 16, count 2 2006.175.07:34:40.58#ibcon#about to read 3, iclass 16, count 2 2006.175.07:34:40.60#ibcon#read 3, iclass 16, count 2 2006.175.07:34:40.60#ibcon#about to read 4, iclass 16, count 2 2006.175.07:34:40.60#ibcon#read 4, iclass 16, count 2 2006.175.07:34:40.60#ibcon#about to read 5, iclass 16, count 2 2006.175.07:34:40.60#ibcon#read 5, iclass 16, count 2 2006.175.07:34:40.60#ibcon#about to read 6, iclass 16, count 2 2006.175.07:34:40.60#ibcon#read 6, iclass 16, count 2 2006.175.07:34:40.60#ibcon#end of sib2, iclass 16, count 2 2006.175.07:34:40.60#ibcon#*mode == 0, iclass 16, count 2 2006.175.07:34:40.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.07:34:40.60#ibcon#[25=AT08-06\r\n] 2006.175.07:34:40.60#ibcon#*before write, iclass 16, count 2 2006.175.07:34:40.60#ibcon#enter sib2, iclass 16, count 2 2006.175.07:34:40.60#ibcon#flushed, iclass 16, count 2 2006.175.07:34:40.60#ibcon#about to write, iclass 16, count 2 2006.175.07:34:40.60#ibcon#wrote, iclass 16, count 2 2006.175.07:34:40.60#ibcon#about to read 3, iclass 16, count 2 2006.175.07:34:40.63#ibcon#read 3, iclass 16, count 2 2006.175.07:34:40.63#ibcon#about to read 4, iclass 16, count 2 2006.175.07:34:40.63#ibcon#read 4, iclass 16, count 2 2006.175.07:34:40.63#ibcon#about to read 5, iclass 16, count 2 2006.175.07:34:40.63#ibcon#read 5, iclass 16, count 2 2006.175.07:34:40.63#ibcon#about to read 6, iclass 16, count 2 2006.175.07:34:40.63#ibcon#read 6, iclass 16, count 2 2006.175.07:34:40.63#ibcon#end of sib2, iclass 16, count 2 2006.175.07:34:40.63#ibcon#*after write, iclass 16, count 2 2006.175.07:34:40.63#ibcon#*before return 0, iclass 16, count 2 2006.175.07:34:40.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:34:40.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:34:40.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.07:34:40.63#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:40.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:34:40.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:34:40.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:34:40.75#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:34:40.75#ibcon#first serial, iclass 16, count 0 2006.175.07:34:40.75#ibcon#enter sib2, iclass 16, count 0 2006.175.07:34:40.75#ibcon#flushed, iclass 16, count 0 2006.175.07:34:40.75#ibcon#about to write, iclass 16, count 0 2006.175.07:34:40.75#ibcon#wrote, iclass 16, count 0 2006.175.07:34:40.75#ibcon#about to read 3, iclass 16, count 0 2006.175.07:34:40.77#ibcon#read 3, iclass 16, count 0 2006.175.07:34:40.77#ibcon#about to read 4, iclass 16, count 0 2006.175.07:34:40.77#ibcon#read 4, iclass 16, count 0 2006.175.07:34:40.77#ibcon#about to read 5, iclass 16, count 0 2006.175.07:34:40.77#ibcon#read 5, iclass 16, count 0 2006.175.07:34:40.77#ibcon#about to read 6, iclass 16, count 0 2006.175.07:34:40.77#ibcon#read 6, iclass 16, count 0 2006.175.07:34:40.77#ibcon#end of sib2, iclass 16, count 0 2006.175.07:34:40.77#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:34:40.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:34:40.77#ibcon#[25=USB\r\n] 2006.175.07:34:40.77#ibcon#*before write, iclass 16, count 0 2006.175.07:34:40.77#ibcon#enter sib2, iclass 16, count 0 2006.175.07:34:40.77#ibcon#flushed, iclass 16, count 0 2006.175.07:34:40.77#ibcon#about to write, iclass 16, count 0 2006.175.07:34:40.77#ibcon#wrote, iclass 16, count 0 2006.175.07:34:40.77#ibcon#about to read 3, iclass 16, count 0 2006.175.07:34:40.80#ibcon#read 3, iclass 16, count 0 2006.175.07:34:40.80#ibcon#about to read 4, iclass 16, count 0 2006.175.07:34:40.80#ibcon#read 4, iclass 16, count 0 2006.175.07:34:40.80#ibcon#about to read 5, iclass 16, count 0 2006.175.07:34:40.80#ibcon#read 5, iclass 16, count 0 2006.175.07:34:40.80#ibcon#about to read 6, iclass 16, count 0 2006.175.07:34:40.80#ibcon#read 6, iclass 16, count 0 2006.175.07:34:40.80#ibcon#end of sib2, iclass 16, count 0 2006.175.07:34:40.80#ibcon#*after write, iclass 16, count 0 2006.175.07:34:40.80#ibcon#*before return 0, iclass 16, count 0 2006.175.07:34:40.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:34:40.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:34:40.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:34:40.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:34:40.80$vc4f8/vblo=1,632.99 2006.175.07:34:40.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.07:34:40.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.07:34:40.80#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:40.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:34:40.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:34:40.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:34:40.80#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:34:40.80#ibcon#first serial, iclass 18, count 0 2006.175.07:34:40.80#ibcon#enter sib2, iclass 18, count 0 2006.175.07:34:40.80#ibcon#flushed, iclass 18, count 0 2006.175.07:34:40.80#ibcon#about to write, iclass 18, count 0 2006.175.07:34:40.80#ibcon#wrote, iclass 18, count 0 2006.175.07:34:40.80#ibcon#about to read 3, iclass 18, count 0 2006.175.07:34:40.82#ibcon#read 3, iclass 18, count 0 2006.175.07:34:40.82#ibcon#about to read 4, iclass 18, count 0 2006.175.07:34:40.82#ibcon#read 4, iclass 18, count 0 2006.175.07:34:40.82#ibcon#about to read 5, iclass 18, count 0 2006.175.07:34:40.82#ibcon#read 5, iclass 18, count 0 2006.175.07:34:40.82#ibcon#about to read 6, iclass 18, count 0 2006.175.07:34:40.82#ibcon#read 6, iclass 18, count 0 2006.175.07:34:40.82#ibcon#end of sib2, iclass 18, count 0 2006.175.07:34:40.82#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:34:40.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:34:40.82#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:34:40.82#ibcon#*before write, iclass 18, count 0 2006.175.07:34:40.82#ibcon#enter sib2, iclass 18, count 0 2006.175.07:34:40.82#ibcon#flushed, iclass 18, count 0 2006.175.07:34:40.82#ibcon#about to write, iclass 18, count 0 2006.175.07:34:40.82#ibcon#wrote, iclass 18, count 0 2006.175.07:34:40.82#ibcon#about to read 3, iclass 18, count 0 2006.175.07:34:40.86#ibcon#read 3, iclass 18, count 0 2006.175.07:34:40.86#ibcon#about to read 4, iclass 18, count 0 2006.175.07:34:40.86#ibcon#read 4, iclass 18, count 0 2006.175.07:34:40.86#ibcon#about to read 5, iclass 18, count 0 2006.175.07:34:40.86#ibcon#read 5, iclass 18, count 0 2006.175.07:34:40.86#ibcon#about to read 6, iclass 18, count 0 2006.175.07:34:40.86#ibcon#read 6, iclass 18, count 0 2006.175.07:34:40.86#ibcon#end of sib2, iclass 18, count 0 2006.175.07:34:40.86#ibcon#*after write, iclass 18, count 0 2006.175.07:34:40.86#ibcon#*before return 0, iclass 18, count 0 2006.175.07:34:40.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:34:40.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:34:40.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:34:40.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:34:40.86$vc4f8/vb=1,4 2006.175.07:34:40.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.175.07:34:40.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.175.07:34:40.86#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:40.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:34:40.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:34:40.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:34:40.86#ibcon#enter wrdev, iclass 20, count 2 2006.175.07:34:40.86#ibcon#first serial, iclass 20, count 2 2006.175.07:34:40.86#ibcon#enter sib2, iclass 20, count 2 2006.175.07:34:40.86#ibcon#flushed, iclass 20, count 2 2006.175.07:34:40.86#ibcon#about to write, iclass 20, count 2 2006.175.07:34:40.86#ibcon#wrote, iclass 20, count 2 2006.175.07:34:40.86#ibcon#about to read 3, iclass 20, count 2 2006.175.07:34:40.88#ibcon#read 3, iclass 20, count 2 2006.175.07:34:40.88#ibcon#about to read 4, iclass 20, count 2 2006.175.07:34:40.88#ibcon#read 4, iclass 20, count 2 2006.175.07:34:40.88#ibcon#about to read 5, iclass 20, count 2 2006.175.07:34:40.88#ibcon#read 5, iclass 20, count 2 2006.175.07:34:40.88#ibcon#about to read 6, iclass 20, count 2 2006.175.07:34:40.88#ibcon#read 6, iclass 20, count 2 2006.175.07:34:40.88#ibcon#end of sib2, iclass 20, count 2 2006.175.07:34:40.88#ibcon#*mode == 0, iclass 20, count 2 2006.175.07:34:40.88#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.175.07:34:40.88#ibcon#[27=AT01-04\r\n] 2006.175.07:34:40.88#ibcon#*before write, iclass 20, count 2 2006.175.07:34:40.88#ibcon#enter sib2, iclass 20, count 2 2006.175.07:34:40.88#ibcon#flushed, iclass 20, count 2 2006.175.07:34:40.88#ibcon#about to write, iclass 20, count 2 2006.175.07:34:40.88#ibcon#wrote, iclass 20, count 2 2006.175.07:34:40.88#ibcon#about to read 3, iclass 20, count 2 2006.175.07:34:40.91#ibcon#read 3, iclass 20, count 2 2006.175.07:34:40.91#ibcon#about to read 4, iclass 20, count 2 2006.175.07:34:40.91#ibcon#read 4, iclass 20, count 2 2006.175.07:34:40.91#ibcon#about to read 5, iclass 20, count 2 2006.175.07:34:40.91#ibcon#read 5, iclass 20, count 2 2006.175.07:34:40.91#ibcon#about to read 6, iclass 20, count 2 2006.175.07:34:40.91#ibcon#read 6, iclass 20, count 2 2006.175.07:34:40.91#ibcon#end of sib2, iclass 20, count 2 2006.175.07:34:40.91#ibcon#*after write, iclass 20, count 2 2006.175.07:34:40.91#ibcon#*before return 0, iclass 20, count 2 2006.175.07:34:40.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:34:40.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:34:40.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.175.07:34:40.91#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:40.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:34:41.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:34:41.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:34:41.03#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:34:41.03#ibcon#first serial, iclass 20, count 0 2006.175.07:34:41.03#ibcon#enter sib2, iclass 20, count 0 2006.175.07:34:41.03#ibcon#flushed, iclass 20, count 0 2006.175.07:34:41.03#ibcon#about to write, iclass 20, count 0 2006.175.07:34:41.03#ibcon#wrote, iclass 20, count 0 2006.175.07:34:41.03#ibcon#about to read 3, iclass 20, count 0 2006.175.07:34:41.05#ibcon#read 3, iclass 20, count 0 2006.175.07:34:41.05#ibcon#about to read 4, iclass 20, count 0 2006.175.07:34:41.05#ibcon#read 4, iclass 20, count 0 2006.175.07:34:41.05#ibcon#about to read 5, iclass 20, count 0 2006.175.07:34:41.05#ibcon#read 5, iclass 20, count 0 2006.175.07:34:41.05#ibcon#about to read 6, iclass 20, count 0 2006.175.07:34:41.05#ibcon#read 6, iclass 20, count 0 2006.175.07:34:41.05#ibcon#end of sib2, iclass 20, count 0 2006.175.07:34:41.05#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:34:41.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:34:41.05#ibcon#[27=USB\r\n] 2006.175.07:34:41.05#ibcon#*before write, iclass 20, count 0 2006.175.07:34:41.05#ibcon#enter sib2, iclass 20, count 0 2006.175.07:34:41.05#ibcon#flushed, iclass 20, count 0 2006.175.07:34:41.05#ibcon#about to write, iclass 20, count 0 2006.175.07:34:41.05#ibcon#wrote, iclass 20, count 0 2006.175.07:34:41.05#ibcon#about to read 3, iclass 20, count 0 2006.175.07:34:41.08#ibcon#read 3, iclass 20, count 0 2006.175.07:34:41.08#ibcon#about to read 4, iclass 20, count 0 2006.175.07:34:41.08#ibcon#read 4, iclass 20, count 0 2006.175.07:34:41.08#ibcon#about to read 5, iclass 20, count 0 2006.175.07:34:41.08#ibcon#read 5, iclass 20, count 0 2006.175.07:34:41.08#ibcon#about to read 6, iclass 20, count 0 2006.175.07:34:41.08#ibcon#read 6, iclass 20, count 0 2006.175.07:34:41.08#ibcon#end of sib2, iclass 20, count 0 2006.175.07:34:41.08#ibcon#*after write, iclass 20, count 0 2006.175.07:34:41.08#ibcon#*before return 0, iclass 20, count 0 2006.175.07:34:41.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:34:41.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:34:41.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:34:41.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:34:41.08$vc4f8/vblo=2,640.99 2006.175.07:34:41.08#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.07:34:41.08#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.07:34:41.08#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:41.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:41.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:41.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:41.08#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:34:41.08#ibcon#first serial, iclass 22, count 0 2006.175.07:34:41.08#ibcon#enter sib2, iclass 22, count 0 2006.175.07:34:41.08#ibcon#flushed, iclass 22, count 0 2006.175.07:34:41.08#ibcon#about to write, iclass 22, count 0 2006.175.07:34:41.08#ibcon#wrote, iclass 22, count 0 2006.175.07:34:41.08#ibcon#about to read 3, iclass 22, count 0 2006.175.07:34:41.10#ibcon#read 3, iclass 22, count 0 2006.175.07:34:41.10#ibcon#about to read 4, iclass 22, count 0 2006.175.07:34:41.10#ibcon#read 4, iclass 22, count 0 2006.175.07:34:41.10#ibcon#about to read 5, iclass 22, count 0 2006.175.07:34:41.10#ibcon#read 5, iclass 22, count 0 2006.175.07:34:41.10#ibcon#about to read 6, iclass 22, count 0 2006.175.07:34:41.10#ibcon#read 6, iclass 22, count 0 2006.175.07:34:41.10#ibcon#end of sib2, iclass 22, count 0 2006.175.07:34:41.10#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:34:41.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:34:41.10#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:34:41.10#ibcon#*before write, iclass 22, count 0 2006.175.07:34:41.10#ibcon#enter sib2, iclass 22, count 0 2006.175.07:34:41.10#ibcon#flushed, iclass 22, count 0 2006.175.07:34:41.10#ibcon#about to write, iclass 22, count 0 2006.175.07:34:41.10#ibcon#wrote, iclass 22, count 0 2006.175.07:34:41.10#ibcon#about to read 3, iclass 22, count 0 2006.175.07:34:41.14#ibcon#read 3, iclass 22, count 0 2006.175.07:34:41.14#ibcon#about to read 4, iclass 22, count 0 2006.175.07:34:41.14#ibcon#read 4, iclass 22, count 0 2006.175.07:34:41.14#ibcon#about to read 5, iclass 22, count 0 2006.175.07:34:41.14#ibcon#read 5, iclass 22, count 0 2006.175.07:34:41.14#ibcon#about to read 6, iclass 22, count 0 2006.175.07:34:41.14#ibcon#read 6, iclass 22, count 0 2006.175.07:34:41.14#ibcon#end of sib2, iclass 22, count 0 2006.175.07:34:41.14#ibcon#*after write, iclass 22, count 0 2006.175.07:34:41.14#ibcon#*before return 0, iclass 22, count 0 2006.175.07:34:41.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:41.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:34:41.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:34:41.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:34:41.14$vc4f8/vb=2,4 2006.175.07:34:41.14#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.07:34:41.14#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.07:34:41.14#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:41.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:41.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:41.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:41.20#ibcon#enter wrdev, iclass 24, count 2 2006.175.07:34:41.20#ibcon#first serial, iclass 24, count 2 2006.175.07:34:41.20#ibcon#enter sib2, iclass 24, count 2 2006.175.07:34:41.20#ibcon#flushed, iclass 24, count 2 2006.175.07:34:41.20#ibcon#about to write, iclass 24, count 2 2006.175.07:34:41.20#ibcon#wrote, iclass 24, count 2 2006.175.07:34:41.20#ibcon#about to read 3, iclass 24, count 2 2006.175.07:34:41.22#ibcon#read 3, iclass 24, count 2 2006.175.07:34:41.22#ibcon#about to read 4, iclass 24, count 2 2006.175.07:34:41.22#ibcon#read 4, iclass 24, count 2 2006.175.07:34:41.22#ibcon#about to read 5, iclass 24, count 2 2006.175.07:34:41.22#ibcon#read 5, iclass 24, count 2 2006.175.07:34:41.22#ibcon#about to read 6, iclass 24, count 2 2006.175.07:34:41.22#ibcon#read 6, iclass 24, count 2 2006.175.07:34:41.22#ibcon#end of sib2, iclass 24, count 2 2006.175.07:34:41.22#ibcon#*mode == 0, iclass 24, count 2 2006.175.07:34:41.22#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.07:34:41.22#ibcon#[27=AT02-04\r\n] 2006.175.07:34:41.22#ibcon#*before write, iclass 24, count 2 2006.175.07:34:41.22#ibcon#enter sib2, iclass 24, count 2 2006.175.07:34:41.22#ibcon#flushed, iclass 24, count 2 2006.175.07:34:41.22#ibcon#about to write, iclass 24, count 2 2006.175.07:34:41.22#ibcon#wrote, iclass 24, count 2 2006.175.07:34:41.22#ibcon#about to read 3, iclass 24, count 2 2006.175.07:34:41.25#ibcon#read 3, iclass 24, count 2 2006.175.07:34:41.25#ibcon#about to read 4, iclass 24, count 2 2006.175.07:34:41.25#ibcon#read 4, iclass 24, count 2 2006.175.07:34:41.25#ibcon#about to read 5, iclass 24, count 2 2006.175.07:34:41.25#ibcon#read 5, iclass 24, count 2 2006.175.07:34:41.25#ibcon#about to read 6, iclass 24, count 2 2006.175.07:34:41.25#ibcon#read 6, iclass 24, count 2 2006.175.07:34:41.25#ibcon#end of sib2, iclass 24, count 2 2006.175.07:34:41.25#ibcon#*after write, iclass 24, count 2 2006.175.07:34:41.25#ibcon#*before return 0, iclass 24, count 2 2006.175.07:34:41.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:41.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:34:41.25#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.07:34:41.25#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:41.25#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:41.37#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:41.37#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:41.37#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:34:41.37#ibcon#first serial, iclass 24, count 0 2006.175.07:34:41.37#ibcon#enter sib2, iclass 24, count 0 2006.175.07:34:41.37#ibcon#flushed, iclass 24, count 0 2006.175.07:34:41.37#ibcon#about to write, iclass 24, count 0 2006.175.07:34:41.37#ibcon#wrote, iclass 24, count 0 2006.175.07:34:41.37#ibcon#about to read 3, iclass 24, count 0 2006.175.07:34:41.39#ibcon#read 3, iclass 24, count 0 2006.175.07:34:41.39#ibcon#about to read 4, iclass 24, count 0 2006.175.07:34:41.39#ibcon#read 4, iclass 24, count 0 2006.175.07:34:41.39#ibcon#about to read 5, iclass 24, count 0 2006.175.07:34:41.39#ibcon#read 5, iclass 24, count 0 2006.175.07:34:41.39#ibcon#about to read 6, iclass 24, count 0 2006.175.07:34:41.39#ibcon#read 6, iclass 24, count 0 2006.175.07:34:41.39#ibcon#end of sib2, iclass 24, count 0 2006.175.07:34:41.39#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:34:41.39#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:34:41.39#ibcon#[27=USB\r\n] 2006.175.07:34:41.39#ibcon#*before write, iclass 24, count 0 2006.175.07:34:41.39#ibcon#enter sib2, iclass 24, count 0 2006.175.07:34:41.39#ibcon#flushed, iclass 24, count 0 2006.175.07:34:41.39#ibcon#about to write, iclass 24, count 0 2006.175.07:34:41.39#ibcon#wrote, iclass 24, count 0 2006.175.07:34:41.39#ibcon#about to read 3, iclass 24, count 0 2006.175.07:34:41.42#ibcon#read 3, iclass 24, count 0 2006.175.07:34:41.42#ibcon#about to read 4, iclass 24, count 0 2006.175.07:34:41.42#ibcon#read 4, iclass 24, count 0 2006.175.07:34:41.42#ibcon#about to read 5, iclass 24, count 0 2006.175.07:34:41.42#ibcon#read 5, iclass 24, count 0 2006.175.07:34:41.42#ibcon#about to read 6, iclass 24, count 0 2006.175.07:34:41.42#ibcon#read 6, iclass 24, count 0 2006.175.07:34:41.42#ibcon#end of sib2, iclass 24, count 0 2006.175.07:34:41.42#ibcon#*after write, iclass 24, count 0 2006.175.07:34:41.42#ibcon#*before return 0, iclass 24, count 0 2006.175.07:34:41.42#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:41.42#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:34:41.42#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:34:41.42#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:34:41.42$vc4f8/vblo=3,656.99 2006.175.07:34:41.42#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.07:34:41.42#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.07:34:41.42#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:41.42#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:41.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:41.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:41.42#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:34:41.42#ibcon#first serial, iclass 26, count 0 2006.175.07:34:41.42#ibcon#enter sib2, iclass 26, count 0 2006.175.07:34:41.42#ibcon#flushed, iclass 26, count 0 2006.175.07:34:41.42#ibcon#about to write, iclass 26, count 0 2006.175.07:34:41.42#ibcon#wrote, iclass 26, count 0 2006.175.07:34:41.42#ibcon#about to read 3, iclass 26, count 0 2006.175.07:34:41.44#ibcon#read 3, iclass 26, count 0 2006.175.07:34:41.44#ibcon#about to read 4, iclass 26, count 0 2006.175.07:34:41.44#ibcon#read 4, iclass 26, count 0 2006.175.07:34:41.44#ibcon#about to read 5, iclass 26, count 0 2006.175.07:34:41.44#ibcon#read 5, iclass 26, count 0 2006.175.07:34:41.44#ibcon#about to read 6, iclass 26, count 0 2006.175.07:34:41.44#ibcon#read 6, iclass 26, count 0 2006.175.07:34:41.44#ibcon#end of sib2, iclass 26, count 0 2006.175.07:34:41.44#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:34:41.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:34:41.44#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:34:41.44#ibcon#*before write, iclass 26, count 0 2006.175.07:34:41.44#ibcon#enter sib2, iclass 26, count 0 2006.175.07:34:41.44#ibcon#flushed, iclass 26, count 0 2006.175.07:34:41.44#ibcon#about to write, iclass 26, count 0 2006.175.07:34:41.44#ibcon#wrote, iclass 26, count 0 2006.175.07:34:41.44#ibcon#about to read 3, iclass 26, count 0 2006.175.07:34:41.48#ibcon#read 3, iclass 26, count 0 2006.175.07:34:41.48#ibcon#about to read 4, iclass 26, count 0 2006.175.07:34:41.48#ibcon#read 4, iclass 26, count 0 2006.175.07:34:41.48#ibcon#about to read 5, iclass 26, count 0 2006.175.07:34:41.48#ibcon#read 5, iclass 26, count 0 2006.175.07:34:41.48#ibcon#about to read 6, iclass 26, count 0 2006.175.07:34:41.48#ibcon#read 6, iclass 26, count 0 2006.175.07:34:41.48#ibcon#end of sib2, iclass 26, count 0 2006.175.07:34:41.48#ibcon#*after write, iclass 26, count 0 2006.175.07:34:41.48#ibcon#*before return 0, iclass 26, count 0 2006.175.07:34:41.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:41.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:34:41.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:34:41.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:34:41.48$vc4f8/vb=3,4 2006.175.07:34:41.48#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.07:34:41.48#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.07:34:41.48#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:41.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:41.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:41.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:41.54#ibcon#enter wrdev, iclass 28, count 2 2006.175.07:34:41.54#ibcon#first serial, iclass 28, count 2 2006.175.07:34:41.54#ibcon#enter sib2, iclass 28, count 2 2006.175.07:34:41.54#ibcon#flushed, iclass 28, count 2 2006.175.07:34:41.54#ibcon#about to write, iclass 28, count 2 2006.175.07:34:41.54#ibcon#wrote, iclass 28, count 2 2006.175.07:34:41.54#ibcon#about to read 3, iclass 28, count 2 2006.175.07:34:41.56#ibcon#read 3, iclass 28, count 2 2006.175.07:34:41.56#ibcon#about to read 4, iclass 28, count 2 2006.175.07:34:41.56#ibcon#read 4, iclass 28, count 2 2006.175.07:34:41.56#ibcon#about to read 5, iclass 28, count 2 2006.175.07:34:41.56#ibcon#read 5, iclass 28, count 2 2006.175.07:34:41.56#ibcon#about to read 6, iclass 28, count 2 2006.175.07:34:41.56#ibcon#read 6, iclass 28, count 2 2006.175.07:34:41.56#ibcon#end of sib2, iclass 28, count 2 2006.175.07:34:41.56#ibcon#*mode == 0, iclass 28, count 2 2006.175.07:34:41.56#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.07:34:41.56#ibcon#[27=AT03-04\r\n] 2006.175.07:34:41.56#ibcon#*before write, iclass 28, count 2 2006.175.07:34:41.56#ibcon#enter sib2, iclass 28, count 2 2006.175.07:34:41.56#ibcon#flushed, iclass 28, count 2 2006.175.07:34:41.56#ibcon#about to write, iclass 28, count 2 2006.175.07:34:41.56#ibcon#wrote, iclass 28, count 2 2006.175.07:34:41.56#ibcon#about to read 3, iclass 28, count 2 2006.175.07:34:41.59#ibcon#read 3, iclass 28, count 2 2006.175.07:34:41.59#ibcon#about to read 4, iclass 28, count 2 2006.175.07:34:41.59#ibcon#read 4, iclass 28, count 2 2006.175.07:34:41.59#ibcon#about to read 5, iclass 28, count 2 2006.175.07:34:41.59#ibcon#read 5, iclass 28, count 2 2006.175.07:34:41.59#ibcon#about to read 6, iclass 28, count 2 2006.175.07:34:41.59#ibcon#read 6, iclass 28, count 2 2006.175.07:34:41.59#ibcon#end of sib2, iclass 28, count 2 2006.175.07:34:41.59#ibcon#*after write, iclass 28, count 2 2006.175.07:34:41.59#ibcon#*before return 0, iclass 28, count 2 2006.175.07:34:41.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:41.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:34:41.59#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.07:34:41.59#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:41.59#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:41.71#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:41.71#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:41.71#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:34:41.71#ibcon#first serial, iclass 28, count 0 2006.175.07:34:41.71#ibcon#enter sib2, iclass 28, count 0 2006.175.07:34:41.71#ibcon#flushed, iclass 28, count 0 2006.175.07:34:41.71#ibcon#about to write, iclass 28, count 0 2006.175.07:34:41.71#ibcon#wrote, iclass 28, count 0 2006.175.07:34:41.71#ibcon#about to read 3, iclass 28, count 0 2006.175.07:34:41.73#ibcon#read 3, iclass 28, count 0 2006.175.07:34:41.73#ibcon#about to read 4, iclass 28, count 0 2006.175.07:34:41.73#ibcon#read 4, iclass 28, count 0 2006.175.07:34:41.73#ibcon#about to read 5, iclass 28, count 0 2006.175.07:34:41.73#ibcon#read 5, iclass 28, count 0 2006.175.07:34:41.73#ibcon#about to read 6, iclass 28, count 0 2006.175.07:34:41.73#ibcon#read 6, iclass 28, count 0 2006.175.07:34:41.73#ibcon#end of sib2, iclass 28, count 0 2006.175.07:34:41.73#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:34:41.73#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:34:41.73#ibcon#[27=USB\r\n] 2006.175.07:34:41.73#ibcon#*before write, iclass 28, count 0 2006.175.07:34:41.73#ibcon#enter sib2, iclass 28, count 0 2006.175.07:34:41.73#ibcon#flushed, iclass 28, count 0 2006.175.07:34:41.73#ibcon#about to write, iclass 28, count 0 2006.175.07:34:41.73#ibcon#wrote, iclass 28, count 0 2006.175.07:34:41.73#ibcon#about to read 3, iclass 28, count 0 2006.175.07:34:41.76#ibcon#read 3, iclass 28, count 0 2006.175.07:34:41.76#ibcon#about to read 4, iclass 28, count 0 2006.175.07:34:41.76#ibcon#read 4, iclass 28, count 0 2006.175.07:34:41.76#ibcon#about to read 5, iclass 28, count 0 2006.175.07:34:41.76#ibcon#read 5, iclass 28, count 0 2006.175.07:34:41.76#ibcon#about to read 6, iclass 28, count 0 2006.175.07:34:41.76#ibcon#read 6, iclass 28, count 0 2006.175.07:34:41.76#ibcon#end of sib2, iclass 28, count 0 2006.175.07:34:41.76#ibcon#*after write, iclass 28, count 0 2006.175.07:34:41.76#ibcon#*before return 0, iclass 28, count 0 2006.175.07:34:41.76#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:41.76#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:34:41.76#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:34:41.76#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:34:41.76$vc4f8/vblo=4,712.99 2006.175.07:34:41.76#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.07:34:41.76#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.07:34:41.76#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:41.76#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:41.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:41.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:41.76#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:34:41.76#ibcon#first serial, iclass 30, count 0 2006.175.07:34:41.76#ibcon#enter sib2, iclass 30, count 0 2006.175.07:34:41.76#ibcon#flushed, iclass 30, count 0 2006.175.07:34:41.76#ibcon#about to write, iclass 30, count 0 2006.175.07:34:41.76#ibcon#wrote, iclass 30, count 0 2006.175.07:34:41.76#ibcon#about to read 3, iclass 30, count 0 2006.175.07:34:41.78#ibcon#read 3, iclass 30, count 0 2006.175.07:34:41.78#ibcon#about to read 4, iclass 30, count 0 2006.175.07:34:41.78#ibcon#read 4, iclass 30, count 0 2006.175.07:34:41.78#ibcon#about to read 5, iclass 30, count 0 2006.175.07:34:41.78#ibcon#read 5, iclass 30, count 0 2006.175.07:34:41.78#ibcon#about to read 6, iclass 30, count 0 2006.175.07:34:41.78#ibcon#read 6, iclass 30, count 0 2006.175.07:34:41.78#ibcon#end of sib2, iclass 30, count 0 2006.175.07:34:41.78#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:34:41.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:34:41.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:34:41.78#ibcon#*before write, iclass 30, count 0 2006.175.07:34:41.78#ibcon#enter sib2, iclass 30, count 0 2006.175.07:34:41.78#ibcon#flushed, iclass 30, count 0 2006.175.07:34:41.78#ibcon#about to write, iclass 30, count 0 2006.175.07:34:41.78#ibcon#wrote, iclass 30, count 0 2006.175.07:34:41.78#ibcon#about to read 3, iclass 30, count 0 2006.175.07:34:41.82#ibcon#read 3, iclass 30, count 0 2006.175.07:34:41.82#ibcon#about to read 4, iclass 30, count 0 2006.175.07:34:41.82#ibcon#read 4, iclass 30, count 0 2006.175.07:34:41.82#ibcon#about to read 5, iclass 30, count 0 2006.175.07:34:41.82#ibcon#read 5, iclass 30, count 0 2006.175.07:34:41.82#ibcon#about to read 6, iclass 30, count 0 2006.175.07:34:41.82#ibcon#read 6, iclass 30, count 0 2006.175.07:34:41.82#ibcon#end of sib2, iclass 30, count 0 2006.175.07:34:41.82#ibcon#*after write, iclass 30, count 0 2006.175.07:34:41.82#ibcon#*before return 0, iclass 30, count 0 2006.175.07:34:41.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:41.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:34:41.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:34:41.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:34:41.82$vc4f8/vb=4,4 2006.175.07:34:41.82#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.07:34:41.82#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.07:34:41.82#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:41.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:41.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:41.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:41.88#ibcon#enter wrdev, iclass 32, count 2 2006.175.07:34:41.88#ibcon#first serial, iclass 32, count 2 2006.175.07:34:41.88#ibcon#enter sib2, iclass 32, count 2 2006.175.07:34:41.88#ibcon#flushed, iclass 32, count 2 2006.175.07:34:41.88#ibcon#about to write, iclass 32, count 2 2006.175.07:34:41.88#ibcon#wrote, iclass 32, count 2 2006.175.07:34:41.88#ibcon#about to read 3, iclass 32, count 2 2006.175.07:34:41.90#ibcon#read 3, iclass 32, count 2 2006.175.07:34:41.90#ibcon#about to read 4, iclass 32, count 2 2006.175.07:34:41.90#ibcon#read 4, iclass 32, count 2 2006.175.07:34:41.90#ibcon#about to read 5, iclass 32, count 2 2006.175.07:34:41.90#ibcon#read 5, iclass 32, count 2 2006.175.07:34:41.90#ibcon#about to read 6, iclass 32, count 2 2006.175.07:34:41.90#ibcon#read 6, iclass 32, count 2 2006.175.07:34:41.90#ibcon#end of sib2, iclass 32, count 2 2006.175.07:34:41.90#ibcon#*mode == 0, iclass 32, count 2 2006.175.07:34:41.90#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.07:34:41.90#ibcon#[27=AT04-04\r\n] 2006.175.07:34:41.90#ibcon#*before write, iclass 32, count 2 2006.175.07:34:41.90#ibcon#enter sib2, iclass 32, count 2 2006.175.07:34:41.90#ibcon#flushed, iclass 32, count 2 2006.175.07:34:41.90#ibcon#about to write, iclass 32, count 2 2006.175.07:34:41.90#ibcon#wrote, iclass 32, count 2 2006.175.07:34:41.90#ibcon#about to read 3, iclass 32, count 2 2006.175.07:34:41.93#ibcon#read 3, iclass 32, count 2 2006.175.07:34:41.93#ibcon#about to read 4, iclass 32, count 2 2006.175.07:34:41.93#ibcon#read 4, iclass 32, count 2 2006.175.07:34:41.93#ibcon#about to read 5, iclass 32, count 2 2006.175.07:34:41.93#ibcon#read 5, iclass 32, count 2 2006.175.07:34:41.93#ibcon#about to read 6, iclass 32, count 2 2006.175.07:34:41.93#ibcon#read 6, iclass 32, count 2 2006.175.07:34:41.93#ibcon#end of sib2, iclass 32, count 2 2006.175.07:34:41.93#ibcon#*after write, iclass 32, count 2 2006.175.07:34:41.93#ibcon#*before return 0, iclass 32, count 2 2006.175.07:34:41.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:41.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:34:41.93#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.07:34:41.93#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:41.93#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:42.05#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:42.05#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:42.05#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:34:42.05#ibcon#first serial, iclass 32, count 0 2006.175.07:34:42.05#ibcon#enter sib2, iclass 32, count 0 2006.175.07:34:42.05#ibcon#flushed, iclass 32, count 0 2006.175.07:34:42.05#ibcon#about to write, iclass 32, count 0 2006.175.07:34:42.05#ibcon#wrote, iclass 32, count 0 2006.175.07:34:42.05#ibcon#about to read 3, iclass 32, count 0 2006.175.07:34:42.07#ibcon#read 3, iclass 32, count 0 2006.175.07:34:42.07#ibcon#about to read 4, iclass 32, count 0 2006.175.07:34:42.07#ibcon#read 4, iclass 32, count 0 2006.175.07:34:42.07#ibcon#about to read 5, iclass 32, count 0 2006.175.07:34:42.07#ibcon#read 5, iclass 32, count 0 2006.175.07:34:42.07#ibcon#about to read 6, iclass 32, count 0 2006.175.07:34:42.07#ibcon#read 6, iclass 32, count 0 2006.175.07:34:42.07#ibcon#end of sib2, iclass 32, count 0 2006.175.07:34:42.07#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:34:42.07#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:34:42.07#ibcon#[27=USB\r\n] 2006.175.07:34:42.07#ibcon#*before write, iclass 32, count 0 2006.175.07:34:42.07#ibcon#enter sib2, iclass 32, count 0 2006.175.07:34:42.07#ibcon#flushed, iclass 32, count 0 2006.175.07:34:42.07#ibcon#about to write, iclass 32, count 0 2006.175.07:34:42.07#ibcon#wrote, iclass 32, count 0 2006.175.07:34:42.07#ibcon#about to read 3, iclass 32, count 0 2006.175.07:34:42.10#ibcon#read 3, iclass 32, count 0 2006.175.07:34:42.10#ibcon#about to read 4, iclass 32, count 0 2006.175.07:34:42.10#ibcon#read 4, iclass 32, count 0 2006.175.07:34:42.10#ibcon#about to read 5, iclass 32, count 0 2006.175.07:34:42.10#ibcon#read 5, iclass 32, count 0 2006.175.07:34:42.10#ibcon#about to read 6, iclass 32, count 0 2006.175.07:34:42.10#ibcon#read 6, iclass 32, count 0 2006.175.07:34:42.10#ibcon#end of sib2, iclass 32, count 0 2006.175.07:34:42.10#ibcon#*after write, iclass 32, count 0 2006.175.07:34:42.10#ibcon#*before return 0, iclass 32, count 0 2006.175.07:34:42.10#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:42.10#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:34:42.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:34:42.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:34:42.10$vc4f8/vblo=5,744.99 2006.175.07:34:42.10#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.07:34:42.10#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.07:34:42.10#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:42.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:42.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:42.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:42.10#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:34:42.10#ibcon#first serial, iclass 34, count 0 2006.175.07:34:42.10#ibcon#enter sib2, iclass 34, count 0 2006.175.07:34:42.10#ibcon#flushed, iclass 34, count 0 2006.175.07:34:42.10#ibcon#about to write, iclass 34, count 0 2006.175.07:34:42.10#ibcon#wrote, iclass 34, count 0 2006.175.07:34:42.10#ibcon#about to read 3, iclass 34, count 0 2006.175.07:34:42.12#ibcon#read 3, iclass 34, count 0 2006.175.07:34:42.12#ibcon#about to read 4, iclass 34, count 0 2006.175.07:34:42.12#ibcon#read 4, iclass 34, count 0 2006.175.07:34:42.12#ibcon#about to read 5, iclass 34, count 0 2006.175.07:34:42.12#ibcon#read 5, iclass 34, count 0 2006.175.07:34:42.12#ibcon#about to read 6, iclass 34, count 0 2006.175.07:34:42.12#ibcon#read 6, iclass 34, count 0 2006.175.07:34:42.12#ibcon#end of sib2, iclass 34, count 0 2006.175.07:34:42.12#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:34:42.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:34:42.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:34:42.12#ibcon#*before write, iclass 34, count 0 2006.175.07:34:42.12#ibcon#enter sib2, iclass 34, count 0 2006.175.07:34:42.12#ibcon#flushed, iclass 34, count 0 2006.175.07:34:42.12#ibcon#about to write, iclass 34, count 0 2006.175.07:34:42.12#ibcon#wrote, iclass 34, count 0 2006.175.07:34:42.12#ibcon#about to read 3, iclass 34, count 0 2006.175.07:34:42.16#ibcon#read 3, iclass 34, count 0 2006.175.07:34:42.16#ibcon#about to read 4, iclass 34, count 0 2006.175.07:34:42.16#ibcon#read 4, iclass 34, count 0 2006.175.07:34:42.16#ibcon#about to read 5, iclass 34, count 0 2006.175.07:34:42.16#ibcon#read 5, iclass 34, count 0 2006.175.07:34:42.16#ibcon#about to read 6, iclass 34, count 0 2006.175.07:34:42.16#ibcon#read 6, iclass 34, count 0 2006.175.07:34:42.16#ibcon#end of sib2, iclass 34, count 0 2006.175.07:34:42.16#ibcon#*after write, iclass 34, count 0 2006.175.07:34:42.16#ibcon#*before return 0, iclass 34, count 0 2006.175.07:34:42.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:42.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:34:42.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:34:42.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:34:42.16$vc4f8/vb=5,4 2006.175.07:34:42.16#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.07:34:42.16#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.07:34:42.16#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:42.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:42.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:42.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:42.22#ibcon#enter wrdev, iclass 36, count 2 2006.175.07:34:42.22#ibcon#first serial, iclass 36, count 2 2006.175.07:34:42.22#ibcon#enter sib2, iclass 36, count 2 2006.175.07:34:42.22#ibcon#flushed, iclass 36, count 2 2006.175.07:34:42.22#ibcon#about to write, iclass 36, count 2 2006.175.07:34:42.22#ibcon#wrote, iclass 36, count 2 2006.175.07:34:42.22#ibcon#about to read 3, iclass 36, count 2 2006.175.07:34:42.24#ibcon#read 3, iclass 36, count 2 2006.175.07:34:42.24#ibcon#about to read 4, iclass 36, count 2 2006.175.07:34:42.24#ibcon#read 4, iclass 36, count 2 2006.175.07:34:42.24#ibcon#about to read 5, iclass 36, count 2 2006.175.07:34:42.24#ibcon#read 5, iclass 36, count 2 2006.175.07:34:42.24#ibcon#about to read 6, iclass 36, count 2 2006.175.07:34:42.24#ibcon#read 6, iclass 36, count 2 2006.175.07:34:42.24#ibcon#end of sib2, iclass 36, count 2 2006.175.07:34:42.24#ibcon#*mode == 0, iclass 36, count 2 2006.175.07:34:42.24#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.07:34:42.24#ibcon#[27=AT05-04\r\n] 2006.175.07:34:42.24#ibcon#*before write, iclass 36, count 2 2006.175.07:34:42.24#ibcon#enter sib2, iclass 36, count 2 2006.175.07:34:42.24#ibcon#flushed, iclass 36, count 2 2006.175.07:34:42.24#ibcon#about to write, iclass 36, count 2 2006.175.07:34:42.24#ibcon#wrote, iclass 36, count 2 2006.175.07:34:42.24#ibcon#about to read 3, iclass 36, count 2 2006.175.07:34:42.27#ibcon#read 3, iclass 36, count 2 2006.175.07:34:42.27#ibcon#about to read 4, iclass 36, count 2 2006.175.07:34:42.27#ibcon#read 4, iclass 36, count 2 2006.175.07:34:42.27#ibcon#about to read 5, iclass 36, count 2 2006.175.07:34:42.27#ibcon#read 5, iclass 36, count 2 2006.175.07:34:42.27#ibcon#about to read 6, iclass 36, count 2 2006.175.07:34:42.27#ibcon#read 6, iclass 36, count 2 2006.175.07:34:42.27#ibcon#end of sib2, iclass 36, count 2 2006.175.07:34:42.27#ibcon#*after write, iclass 36, count 2 2006.175.07:34:42.27#ibcon#*before return 0, iclass 36, count 2 2006.175.07:34:42.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:42.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:34:42.27#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.07:34:42.27#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:42.27#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:42.39#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:42.39#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:42.39#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:34:42.39#ibcon#first serial, iclass 36, count 0 2006.175.07:34:42.39#ibcon#enter sib2, iclass 36, count 0 2006.175.07:34:42.39#ibcon#flushed, iclass 36, count 0 2006.175.07:34:42.39#ibcon#about to write, iclass 36, count 0 2006.175.07:34:42.39#ibcon#wrote, iclass 36, count 0 2006.175.07:34:42.39#ibcon#about to read 3, iclass 36, count 0 2006.175.07:34:42.41#ibcon#read 3, iclass 36, count 0 2006.175.07:34:42.41#ibcon#about to read 4, iclass 36, count 0 2006.175.07:34:42.41#ibcon#read 4, iclass 36, count 0 2006.175.07:34:42.41#ibcon#about to read 5, iclass 36, count 0 2006.175.07:34:42.41#ibcon#read 5, iclass 36, count 0 2006.175.07:34:42.41#ibcon#about to read 6, iclass 36, count 0 2006.175.07:34:42.41#ibcon#read 6, iclass 36, count 0 2006.175.07:34:42.41#ibcon#end of sib2, iclass 36, count 0 2006.175.07:34:42.41#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:34:42.41#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:34:42.41#ibcon#[27=USB\r\n] 2006.175.07:34:42.41#ibcon#*before write, iclass 36, count 0 2006.175.07:34:42.41#ibcon#enter sib2, iclass 36, count 0 2006.175.07:34:42.41#ibcon#flushed, iclass 36, count 0 2006.175.07:34:42.41#ibcon#about to write, iclass 36, count 0 2006.175.07:34:42.41#ibcon#wrote, iclass 36, count 0 2006.175.07:34:42.41#ibcon#about to read 3, iclass 36, count 0 2006.175.07:34:42.44#ibcon#read 3, iclass 36, count 0 2006.175.07:34:42.44#ibcon#about to read 4, iclass 36, count 0 2006.175.07:34:42.44#ibcon#read 4, iclass 36, count 0 2006.175.07:34:42.44#ibcon#about to read 5, iclass 36, count 0 2006.175.07:34:42.44#ibcon#read 5, iclass 36, count 0 2006.175.07:34:42.44#ibcon#about to read 6, iclass 36, count 0 2006.175.07:34:42.44#ibcon#read 6, iclass 36, count 0 2006.175.07:34:42.44#ibcon#end of sib2, iclass 36, count 0 2006.175.07:34:42.44#ibcon#*after write, iclass 36, count 0 2006.175.07:34:42.44#ibcon#*before return 0, iclass 36, count 0 2006.175.07:34:42.44#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:42.44#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:34:42.44#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:34:42.44#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:34:42.44$vc4f8/vblo=6,752.99 2006.175.07:34:42.44#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:34:42.44#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:34:42.44#ibcon#ireg 17 cls_cnt 0 2006.175.07:34:42.44#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:42.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:42.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:42.44#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:34:42.44#ibcon#first serial, iclass 38, count 0 2006.175.07:34:42.44#ibcon#enter sib2, iclass 38, count 0 2006.175.07:34:42.44#ibcon#flushed, iclass 38, count 0 2006.175.07:34:42.44#ibcon#about to write, iclass 38, count 0 2006.175.07:34:42.44#ibcon#wrote, iclass 38, count 0 2006.175.07:34:42.44#ibcon#about to read 3, iclass 38, count 0 2006.175.07:34:42.46#ibcon#read 3, iclass 38, count 0 2006.175.07:34:42.46#ibcon#about to read 4, iclass 38, count 0 2006.175.07:34:42.46#ibcon#read 4, iclass 38, count 0 2006.175.07:34:42.46#ibcon#about to read 5, iclass 38, count 0 2006.175.07:34:42.46#ibcon#read 5, iclass 38, count 0 2006.175.07:34:42.46#ibcon#about to read 6, iclass 38, count 0 2006.175.07:34:42.46#ibcon#read 6, iclass 38, count 0 2006.175.07:34:42.46#ibcon#end of sib2, iclass 38, count 0 2006.175.07:34:42.46#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:34:42.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:34:42.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:34:42.46#ibcon#*before write, iclass 38, count 0 2006.175.07:34:42.46#ibcon#enter sib2, iclass 38, count 0 2006.175.07:34:42.46#ibcon#flushed, iclass 38, count 0 2006.175.07:34:42.46#ibcon#about to write, iclass 38, count 0 2006.175.07:34:42.46#ibcon#wrote, iclass 38, count 0 2006.175.07:34:42.46#ibcon#about to read 3, iclass 38, count 0 2006.175.07:34:42.50#ibcon#read 3, iclass 38, count 0 2006.175.07:34:42.50#ibcon#about to read 4, iclass 38, count 0 2006.175.07:34:42.50#ibcon#read 4, iclass 38, count 0 2006.175.07:34:42.50#ibcon#about to read 5, iclass 38, count 0 2006.175.07:34:42.50#ibcon#read 5, iclass 38, count 0 2006.175.07:34:42.50#ibcon#about to read 6, iclass 38, count 0 2006.175.07:34:42.50#ibcon#read 6, iclass 38, count 0 2006.175.07:34:42.50#ibcon#end of sib2, iclass 38, count 0 2006.175.07:34:42.50#ibcon#*after write, iclass 38, count 0 2006.175.07:34:42.50#ibcon#*before return 0, iclass 38, count 0 2006.175.07:34:42.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:42.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:34:42.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:34:42.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:34:42.50$vc4f8/vb=6,4 2006.175.07:34:42.50#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.07:34:42.50#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.07:34:42.50#ibcon#ireg 11 cls_cnt 2 2006.175.07:34:42.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:42.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:42.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:42.56#ibcon#enter wrdev, iclass 40, count 2 2006.175.07:34:42.56#ibcon#first serial, iclass 40, count 2 2006.175.07:34:42.56#ibcon#enter sib2, iclass 40, count 2 2006.175.07:34:42.56#ibcon#flushed, iclass 40, count 2 2006.175.07:34:42.56#ibcon#about to write, iclass 40, count 2 2006.175.07:34:42.56#ibcon#wrote, iclass 40, count 2 2006.175.07:34:42.56#ibcon#about to read 3, iclass 40, count 2 2006.175.07:34:42.58#ibcon#read 3, iclass 40, count 2 2006.175.07:34:42.58#ibcon#about to read 4, iclass 40, count 2 2006.175.07:34:42.58#ibcon#read 4, iclass 40, count 2 2006.175.07:34:42.58#ibcon#about to read 5, iclass 40, count 2 2006.175.07:34:42.58#ibcon#read 5, iclass 40, count 2 2006.175.07:34:42.58#ibcon#about to read 6, iclass 40, count 2 2006.175.07:34:42.58#ibcon#read 6, iclass 40, count 2 2006.175.07:34:42.58#ibcon#end of sib2, iclass 40, count 2 2006.175.07:34:42.58#ibcon#*mode == 0, iclass 40, count 2 2006.175.07:34:42.58#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.07:34:42.58#ibcon#[27=AT06-04\r\n] 2006.175.07:34:42.58#ibcon#*before write, iclass 40, count 2 2006.175.07:34:42.58#ibcon#enter sib2, iclass 40, count 2 2006.175.07:34:42.58#ibcon#flushed, iclass 40, count 2 2006.175.07:34:42.58#ibcon#about to write, iclass 40, count 2 2006.175.07:34:42.58#ibcon#wrote, iclass 40, count 2 2006.175.07:34:42.58#ibcon#about to read 3, iclass 40, count 2 2006.175.07:34:42.61#ibcon#read 3, iclass 40, count 2 2006.175.07:34:42.61#ibcon#about to read 4, iclass 40, count 2 2006.175.07:34:42.61#ibcon#read 4, iclass 40, count 2 2006.175.07:34:42.61#ibcon#about to read 5, iclass 40, count 2 2006.175.07:34:42.61#ibcon#read 5, iclass 40, count 2 2006.175.07:34:42.61#ibcon#about to read 6, iclass 40, count 2 2006.175.07:34:42.61#ibcon#read 6, iclass 40, count 2 2006.175.07:34:42.61#ibcon#end of sib2, iclass 40, count 2 2006.175.07:34:42.61#ibcon#*after write, iclass 40, count 2 2006.175.07:34:42.61#ibcon#*before return 0, iclass 40, count 2 2006.175.07:34:42.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:42.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:34:42.61#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.07:34:42.61#ibcon#ireg 7 cls_cnt 0 2006.175.07:34:42.61#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:42.73#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:42.73#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:42.73#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:34:42.73#ibcon#first serial, iclass 40, count 0 2006.175.07:34:42.73#ibcon#enter sib2, iclass 40, count 0 2006.175.07:34:42.73#ibcon#flushed, iclass 40, count 0 2006.175.07:34:42.73#ibcon#about to write, iclass 40, count 0 2006.175.07:34:42.73#ibcon#wrote, iclass 40, count 0 2006.175.07:34:42.73#ibcon#about to read 3, iclass 40, count 0 2006.175.07:34:42.75#ibcon#read 3, iclass 40, count 0 2006.175.07:34:42.75#ibcon#about to read 4, iclass 40, count 0 2006.175.07:34:42.75#ibcon#read 4, iclass 40, count 0 2006.175.07:34:42.75#ibcon#about to read 5, iclass 40, count 0 2006.175.07:34:42.75#ibcon#read 5, iclass 40, count 0 2006.175.07:34:42.75#ibcon#about to read 6, iclass 40, count 0 2006.175.07:34:42.75#ibcon#read 6, iclass 40, count 0 2006.175.07:34:42.75#ibcon#end of sib2, iclass 40, count 0 2006.175.07:34:42.75#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:34:42.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:34:42.75#ibcon#[27=USB\r\n] 2006.175.07:34:42.75#ibcon#*before write, iclass 40, count 0 2006.175.07:34:42.75#ibcon#enter sib2, iclass 40, count 0 2006.175.07:34:42.75#ibcon#flushed, iclass 40, count 0 2006.175.07:34:42.75#ibcon#about to write, iclass 40, count 0 2006.175.07:34:42.75#ibcon#wrote, iclass 40, count 0 2006.175.07:34:42.75#ibcon#about to read 3, iclass 40, count 0 2006.175.07:34:42.78#ibcon#read 3, iclass 40, count 0 2006.175.07:34:42.78#ibcon#about to read 4, iclass 40, count 0 2006.175.07:34:42.78#ibcon#read 4, iclass 40, count 0 2006.175.07:34:42.78#ibcon#about to read 5, iclass 40, count 0 2006.175.07:34:42.78#ibcon#read 5, iclass 40, count 0 2006.175.07:34:42.78#ibcon#about to read 6, iclass 40, count 0 2006.175.07:34:42.78#ibcon#read 6, iclass 40, count 0 2006.175.07:34:42.78#ibcon#end of sib2, iclass 40, count 0 2006.175.07:34:42.78#ibcon#*after write, iclass 40, count 0 2006.175.07:34:42.78#ibcon#*before return 0, iclass 40, count 0 2006.175.07:34:42.78#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:42.78#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:34:42.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:34:42.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:34:42.78$vc4f8/vabw=wide 2006.175.07:34:42.78#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:34:42.78#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:34:42.78#ibcon#ireg 8 cls_cnt 0 2006.175.07:34:42.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:42.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:42.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:42.78#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:34:42.78#ibcon#first serial, iclass 4, count 0 2006.175.07:34:42.78#ibcon#enter sib2, iclass 4, count 0 2006.175.07:34:42.78#ibcon#flushed, iclass 4, count 0 2006.175.07:34:42.78#ibcon#about to write, iclass 4, count 0 2006.175.07:34:42.78#ibcon#wrote, iclass 4, count 0 2006.175.07:34:42.78#ibcon#about to read 3, iclass 4, count 0 2006.175.07:34:42.80#ibcon#read 3, iclass 4, count 0 2006.175.07:34:42.80#ibcon#about to read 4, iclass 4, count 0 2006.175.07:34:42.80#ibcon#read 4, iclass 4, count 0 2006.175.07:34:42.80#ibcon#about to read 5, iclass 4, count 0 2006.175.07:34:42.80#ibcon#read 5, iclass 4, count 0 2006.175.07:34:42.80#ibcon#about to read 6, iclass 4, count 0 2006.175.07:34:42.80#ibcon#read 6, iclass 4, count 0 2006.175.07:34:42.80#ibcon#end of sib2, iclass 4, count 0 2006.175.07:34:42.80#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:34:42.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:34:42.80#ibcon#[25=BW32\r\n] 2006.175.07:34:42.80#ibcon#*before write, iclass 4, count 0 2006.175.07:34:42.80#ibcon#enter sib2, iclass 4, count 0 2006.175.07:34:42.80#ibcon#flushed, iclass 4, count 0 2006.175.07:34:42.80#ibcon#about to write, iclass 4, count 0 2006.175.07:34:42.80#ibcon#wrote, iclass 4, count 0 2006.175.07:34:42.80#ibcon#about to read 3, iclass 4, count 0 2006.175.07:34:42.83#ibcon#read 3, iclass 4, count 0 2006.175.07:34:42.83#ibcon#about to read 4, iclass 4, count 0 2006.175.07:34:42.83#ibcon#read 4, iclass 4, count 0 2006.175.07:34:42.83#ibcon#about to read 5, iclass 4, count 0 2006.175.07:34:42.83#ibcon#read 5, iclass 4, count 0 2006.175.07:34:42.83#ibcon#about to read 6, iclass 4, count 0 2006.175.07:34:42.83#ibcon#read 6, iclass 4, count 0 2006.175.07:34:42.83#ibcon#end of sib2, iclass 4, count 0 2006.175.07:34:42.83#ibcon#*after write, iclass 4, count 0 2006.175.07:34:42.83#ibcon#*before return 0, iclass 4, count 0 2006.175.07:34:42.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:42.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:34:42.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:34:42.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:34:42.83$vc4f8/vbbw=wide 2006.175.07:34:42.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.175.07:34:42.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.175.07:34:42.83#ibcon#ireg 8 cls_cnt 0 2006.175.07:34:42.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:34:42.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:34:42.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:34:42.90#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:34:42.90#ibcon#first serial, iclass 6, count 0 2006.175.07:34:42.90#ibcon#enter sib2, iclass 6, count 0 2006.175.07:34:42.90#ibcon#flushed, iclass 6, count 0 2006.175.07:34:42.90#ibcon#about to write, iclass 6, count 0 2006.175.07:34:42.90#ibcon#wrote, iclass 6, count 0 2006.175.07:34:42.90#ibcon#about to read 3, iclass 6, count 0 2006.175.07:34:42.92#ibcon#read 3, iclass 6, count 0 2006.175.07:34:42.92#ibcon#about to read 4, iclass 6, count 0 2006.175.07:34:42.92#ibcon#read 4, iclass 6, count 0 2006.175.07:34:42.92#ibcon#about to read 5, iclass 6, count 0 2006.175.07:34:42.92#ibcon#read 5, iclass 6, count 0 2006.175.07:34:42.92#ibcon#about to read 6, iclass 6, count 0 2006.175.07:34:42.92#ibcon#read 6, iclass 6, count 0 2006.175.07:34:42.92#ibcon#end of sib2, iclass 6, count 0 2006.175.07:34:42.92#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:34:42.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:34:42.92#ibcon#[27=BW32\r\n] 2006.175.07:34:42.92#ibcon#*before write, iclass 6, count 0 2006.175.07:34:42.92#ibcon#enter sib2, iclass 6, count 0 2006.175.07:34:42.92#ibcon#flushed, iclass 6, count 0 2006.175.07:34:42.92#ibcon#about to write, iclass 6, count 0 2006.175.07:34:42.92#ibcon#wrote, iclass 6, count 0 2006.175.07:34:42.92#ibcon#about to read 3, iclass 6, count 0 2006.175.07:34:42.95#ibcon#read 3, iclass 6, count 0 2006.175.07:34:42.95#ibcon#about to read 4, iclass 6, count 0 2006.175.07:34:42.95#ibcon#read 4, iclass 6, count 0 2006.175.07:34:42.95#ibcon#about to read 5, iclass 6, count 0 2006.175.07:34:42.95#ibcon#read 5, iclass 6, count 0 2006.175.07:34:42.95#ibcon#about to read 6, iclass 6, count 0 2006.175.07:34:42.95#ibcon#read 6, iclass 6, count 0 2006.175.07:34:42.95#ibcon#end of sib2, iclass 6, count 0 2006.175.07:34:42.95#ibcon#*after write, iclass 6, count 0 2006.175.07:34:42.95#ibcon#*before return 0, iclass 6, count 0 2006.175.07:34:42.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:34:42.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:34:42.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:34:42.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:34:42.95$4f8m12a/ifd4f 2006.175.07:34:42.95$ifd4f/lo= 2006.175.07:34:42.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:34:42.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:34:42.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:34:42.95$ifd4f/patch= 2006.175.07:34:42.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:34:42.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:34:42.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:34:42.95$4f8m12a/"form=m,16.000,1:2 2006.175.07:34:42.95$4f8m12a/"tpicd 2006.175.07:34:42.95$4f8m12a/echo=off 2006.175.07:34:42.95$4f8m12a/xlog=off 2006.175.07:34:42.95:!2006.175.07:35:10 2006.175.07:34:54.13#trakl#Source acquired 2006.175.07:34:55.13#flagr#flagr/antenna,acquired 2006.175.07:35:10.00:preob 2006.175.07:35:11.13/onsource/TRACKING 2006.175.07:35:11.13:!2006.175.07:35:20 2006.175.07:35:20.00:data_valid=on 2006.175.07:35:20.00:midob 2006.175.07:35:20.13/onsource/TRACKING 2006.175.07:35:20.13/wx/26.00,1007.5,71 2006.175.07:35:20.29/cable/+6.4788E-03 2006.175.07:35:21.38/va/01,08,usb,yes,29,30 2006.175.07:35:21.38/va/02,07,usb,yes,29,30 2006.175.07:35:21.38/va/03,06,usb,yes,30,30 2006.175.07:35:21.38/va/04,07,usb,yes,29,32 2006.175.07:35:21.38/va/05,07,usb,yes,30,31 2006.175.07:35:21.38/va/06,06,usb,yes,29,29 2006.175.07:35:21.38/va/07,06,usb,yes,29,29 2006.175.07:35:21.38/va/08,06,usb,yes,31,31 2006.175.07:35:21.61/valo/01,532.99,yes,locked 2006.175.07:35:21.61/valo/02,572.99,yes,locked 2006.175.07:35:21.61/valo/03,672.99,yes,locked 2006.175.07:35:21.61/valo/04,832.99,yes,locked 2006.175.07:35:21.61/valo/05,652.99,yes,locked 2006.175.07:35:21.61/valo/06,772.99,yes,locked 2006.175.07:35:21.61/valo/07,832.99,yes,locked 2006.175.07:35:21.61/valo/08,852.99,yes,locked 2006.175.07:35:22.70/vb/01,04,usb,yes,29,28 2006.175.07:35:22.70/vb/02,04,usb,yes,31,32 2006.175.07:35:22.70/vb/03,04,usb,yes,27,31 2006.175.07:35:22.70/vb/04,04,usb,yes,28,28 2006.175.07:35:22.70/vb/05,04,usb,yes,26,30 2006.175.07:35:22.70/vb/06,04,usb,yes,27,30 2006.175.07:35:22.70/vb/07,04,usb,yes,29,29 2006.175.07:35:22.70/vb/08,04,usb,yes,27,30 2006.175.07:35:22.93/vblo/01,632.99,yes,locked 2006.175.07:35:22.93/vblo/02,640.99,yes,locked 2006.175.07:35:22.93/vblo/03,656.99,yes,locked 2006.175.07:35:22.93/vblo/04,712.99,yes,locked 2006.175.07:35:22.93/vblo/05,744.99,yes,locked 2006.175.07:35:22.93/vblo/06,752.99,yes,locked 2006.175.07:35:22.93/vblo/07,734.99,yes,locked 2006.175.07:35:22.93/vblo/08,744.99,yes,locked 2006.175.07:35:23.08/vabw/8 2006.175.07:35:23.23/vbbw/8 2006.175.07:35:23.32/xfe/off,on,15.0 2006.175.07:35:23.70/ifatt/23,28,28,28 2006.175.07:35:24.07/fmout-gps/S +3.77E-07 2006.175.07:35:24.15:!2006.175.07:36:20 2006.175.07:36:20.00:data_valid=off 2006.175.07:36:20.00:postob 2006.175.07:36:20.18/cable/+6.4765E-03 2006.175.07:36:20.18/wx/25.99,1007.5,71 2006.175.07:36:21.07/fmout-gps/S +3.76E-07 2006.175.07:36:21.07:scan_name=175-0737,k06175,60 2006.175.07:36:21.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.175.07:36:21.14#flagr#flagr/antenna,new-source 2006.175.07:36:22.14:checkk5 2006.175.07:36:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:36:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:36:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:36:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:36:24.04/chk_obsdata//k5ts1/T1750735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:36:24.39/chk_obsdata//k5ts2/T1750735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:36:24.75/chk_obsdata//k5ts3/T1750735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:36:25.13/chk_obsdata//k5ts4/T1750735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:36:25.85/k5log//k5ts1_log_newline 2006.175.07:36:26.57/k5log//k5ts2_log_newline 2006.175.07:36:27.28/k5log//k5ts3_log_newline 2006.175.07:36:27.98/k5log//k5ts4_log_newline 2006.175.07:36:28.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:36:28.00:4f8m12a=1 2006.175.07:36:28.00$4f8m12a/echo=on 2006.175.07:36:28.00$4f8m12a/pcalon 2006.175.07:36:28.00$pcalon/"no phase cal control is implemented here 2006.175.07:36:28.00$4f8m12a/"tpicd=stop 2006.175.07:36:28.00$4f8m12a/vc4f8 2006.175.07:36:28.00$vc4f8/valo=1,532.99 2006.175.07:36:28.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.07:36:28.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.07:36:28.00#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:28.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:28.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:28.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:28.00#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:36:28.00#ibcon#first serial, iclass 19, count 0 2006.175.07:36:28.00#ibcon#enter sib2, iclass 19, count 0 2006.175.07:36:28.00#ibcon#flushed, iclass 19, count 0 2006.175.07:36:28.00#ibcon#about to write, iclass 19, count 0 2006.175.07:36:28.00#ibcon#wrote, iclass 19, count 0 2006.175.07:36:28.00#ibcon#about to read 3, iclass 19, count 0 2006.175.07:36:28.05#ibcon#read 3, iclass 19, count 0 2006.175.07:36:28.05#ibcon#about to read 4, iclass 19, count 0 2006.175.07:36:28.05#ibcon#read 4, iclass 19, count 0 2006.175.07:36:28.05#ibcon#about to read 5, iclass 19, count 0 2006.175.07:36:28.05#ibcon#read 5, iclass 19, count 0 2006.175.07:36:28.05#ibcon#about to read 6, iclass 19, count 0 2006.175.07:36:28.05#ibcon#read 6, iclass 19, count 0 2006.175.07:36:28.05#ibcon#end of sib2, iclass 19, count 0 2006.175.07:36:28.05#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:36:28.05#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:36:28.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:36:28.05#ibcon#*before write, iclass 19, count 0 2006.175.07:36:28.05#ibcon#enter sib2, iclass 19, count 0 2006.175.07:36:28.05#ibcon#flushed, iclass 19, count 0 2006.175.07:36:28.05#ibcon#about to write, iclass 19, count 0 2006.175.07:36:28.05#ibcon#wrote, iclass 19, count 0 2006.175.07:36:28.05#ibcon#about to read 3, iclass 19, count 0 2006.175.07:36:28.10#ibcon#read 3, iclass 19, count 0 2006.175.07:36:28.10#ibcon#about to read 4, iclass 19, count 0 2006.175.07:36:28.10#ibcon#read 4, iclass 19, count 0 2006.175.07:36:28.10#ibcon#about to read 5, iclass 19, count 0 2006.175.07:36:28.10#ibcon#read 5, iclass 19, count 0 2006.175.07:36:28.10#ibcon#about to read 6, iclass 19, count 0 2006.175.07:36:28.10#ibcon#read 6, iclass 19, count 0 2006.175.07:36:28.10#ibcon#end of sib2, iclass 19, count 0 2006.175.07:36:28.10#ibcon#*after write, iclass 19, count 0 2006.175.07:36:28.10#ibcon#*before return 0, iclass 19, count 0 2006.175.07:36:28.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:28.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:28.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:36:28.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:36:28.10$vc4f8/va=1,8 2006.175.07:36:28.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.07:36:28.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.07:36:28.10#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:28.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:28.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:28.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:28.10#ibcon#enter wrdev, iclass 21, count 2 2006.175.07:36:28.10#ibcon#first serial, iclass 21, count 2 2006.175.07:36:28.10#ibcon#enter sib2, iclass 21, count 2 2006.175.07:36:28.10#ibcon#flushed, iclass 21, count 2 2006.175.07:36:28.10#ibcon#about to write, iclass 21, count 2 2006.175.07:36:28.10#ibcon#wrote, iclass 21, count 2 2006.175.07:36:28.10#ibcon#about to read 3, iclass 21, count 2 2006.175.07:36:28.12#ibcon#read 3, iclass 21, count 2 2006.175.07:36:28.12#ibcon#about to read 4, iclass 21, count 2 2006.175.07:36:28.12#ibcon#read 4, iclass 21, count 2 2006.175.07:36:28.12#ibcon#about to read 5, iclass 21, count 2 2006.175.07:36:28.12#ibcon#read 5, iclass 21, count 2 2006.175.07:36:28.12#ibcon#about to read 6, iclass 21, count 2 2006.175.07:36:28.12#ibcon#read 6, iclass 21, count 2 2006.175.07:36:28.12#ibcon#end of sib2, iclass 21, count 2 2006.175.07:36:28.12#ibcon#*mode == 0, iclass 21, count 2 2006.175.07:36:28.12#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.07:36:28.12#ibcon#[25=AT01-08\r\n] 2006.175.07:36:28.12#ibcon#*before write, iclass 21, count 2 2006.175.07:36:28.12#ibcon#enter sib2, iclass 21, count 2 2006.175.07:36:28.12#ibcon#flushed, iclass 21, count 2 2006.175.07:36:28.12#ibcon#about to write, iclass 21, count 2 2006.175.07:36:28.12#ibcon#wrote, iclass 21, count 2 2006.175.07:36:28.12#ibcon#about to read 3, iclass 21, count 2 2006.175.07:36:28.15#ibcon#read 3, iclass 21, count 2 2006.175.07:36:28.15#ibcon#about to read 4, iclass 21, count 2 2006.175.07:36:28.15#ibcon#read 4, iclass 21, count 2 2006.175.07:36:28.15#ibcon#about to read 5, iclass 21, count 2 2006.175.07:36:28.15#ibcon#read 5, iclass 21, count 2 2006.175.07:36:28.15#ibcon#about to read 6, iclass 21, count 2 2006.175.07:36:28.15#ibcon#read 6, iclass 21, count 2 2006.175.07:36:28.15#ibcon#end of sib2, iclass 21, count 2 2006.175.07:36:28.15#ibcon#*after write, iclass 21, count 2 2006.175.07:36:28.15#ibcon#*before return 0, iclass 21, count 2 2006.175.07:36:28.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:28.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:28.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.07:36:28.15#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:28.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:28.27#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:28.27#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:28.27#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:36:28.27#ibcon#first serial, iclass 21, count 0 2006.175.07:36:28.27#ibcon#enter sib2, iclass 21, count 0 2006.175.07:36:28.27#ibcon#flushed, iclass 21, count 0 2006.175.07:36:28.27#ibcon#about to write, iclass 21, count 0 2006.175.07:36:28.27#ibcon#wrote, iclass 21, count 0 2006.175.07:36:28.27#ibcon#about to read 3, iclass 21, count 0 2006.175.07:36:28.29#ibcon#read 3, iclass 21, count 0 2006.175.07:36:28.29#ibcon#about to read 4, iclass 21, count 0 2006.175.07:36:28.29#ibcon#read 4, iclass 21, count 0 2006.175.07:36:28.29#ibcon#about to read 5, iclass 21, count 0 2006.175.07:36:28.29#ibcon#read 5, iclass 21, count 0 2006.175.07:36:28.29#ibcon#about to read 6, iclass 21, count 0 2006.175.07:36:28.29#ibcon#read 6, iclass 21, count 0 2006.175.07:36:28.29#ibcon#end of sib2, iclass 21, count 0 2006.175.07:36:28.29#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:36:28.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:36:28.29#ibcon#[25=USB\r\n] 2006.175.07:36:28.29#ibcon#*before write, iclass 21, count 0 2006.175.07:36:28.29#ibcon#enter sib2, iclass 21, count 0 2006.175.07:36:28.29#ibcon#flushed, iclass 21, count 0 2006.175.07:36:28.29#ibcon#about to write, iclass 21, count 0 2006.175.07:36:28.29#ibcon#wrote, iclass 21, count 0 2006.175.07:36:28.29#ibcon#about to read 3, iclass 21, count 0 2006.175.07:36:28.32#ibcon#read 3, iclass 21, count 0 2006.175.07:36:28.32#ibcon#about to read 4, iclass 21, count 0 2006.175.07:36:28.32#ibcon#read 4, iclass 21, count 0 2006.175.07:36:28.32#ibcon#about to read 5, iclass 21, count 0 2006.175.07:36:28.32#ibcon#read 5, iclass 21, count 0 2006.175.07:36:28.32#ibcon#about to read 6, iclass 21, count 0 2006.175.07:36:28.32#ibcon#read 6, iclass 21, count 0 2006.175.07:36:28.32#ibcon#end of sib2, iclass 21, count 0 2006.175.07:36:28.32#ibcon#*after write, iclass 21, count 0 2006.175.07:36:28.32#ibcon#*before return 0, iclass 21, count 0 2006.175.07:36:28.32#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:28.32#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:28.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:36:28.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:36:28.32$vc4f8/valo=2,572.99 2006.175.07:36:28.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.07:36:28.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.07:36:28.32#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:28.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:28.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:28.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:28.32#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:36:28.32#ibcon#first serial, iclass 23, count 0 2006.175.07:36:28.32#ibcon#enter sib2, iclass 23, count 0 2006.175.07:36:28.32#ibcon#flushed, iclass 23, count 0 2006.175.07:36:28.32#ibcon#about to write, iclass 23, count 0 2006.175.07:36:28.32#ibcon#wrote, iclass 23, count 0 2006.175.07:36:28.32#ibcon#about to read 3, iclass 23, count 0 2006.175.07:36:28.34#ibcon#read 3, iclass 23, count 0 2006.175.07:36:28.34#ibcon#about to read 4, iclass 23, count 0 2006.175.07:36:28.34#ibcon#read 4, iclass 23, count 0 2006.175.07:36:28.34#ibcon#about to read 5, iclass 23, count 0 2006.175.07:36:28.34#ibcon#read 5, iclass 23, count 0 2006.175.07:36:28.34#ibcon#about to read 6, iclass 23, count 0 2006.175.07:36:28.34#ibcon#read 6, iclass 23, count 0 2006.175.07:36:28.34#ibcon#end of sib2, iclass 23, count 0 2006.175.07:36:28.34#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:36:28.34#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:36:28.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:36:28.34#ibcon#*before write, iclass 23, count 0 2006.175.07:36:28.34#ibcon#enter sib2, iclass 23, count 0 2006.175.07:36:28.34#ibcon#flushed, iclass 23, count 0 2006.175.07:36:28.34#ibcon#about to write, iclass 23, count 0 2006.175.07:36:28.34#ibcon#wrote, iclass 23, count 0 2006.175.07:36:28.34#ibcon#about to read 3, iclass 23, count 0 2006.175.07:36:28.38#ibcon#read 3, iclass 23, count 0 2006.175.07:36:28.38#ibcon#about to read 4, iclass 23, count 0 2006.175.07:36:28.38#ibcon#read 4, iclass 23, count 0 2006.175.07:36:28.38#ibcon#about to read 5, iclass 23, count 0 2006.175.07:36:28.38#ibcon#read 5, iclass 23, count 0 2006.175.07:36:28.38#ibcon#about to read 6, iclass 23, count 0 2006.175.07:36:28.38#ibcon#read 6, iclass 23, count 0 2006.175.07:36:28.38#ibcon#end of sib2, iclass 23, count 0 2006.175.07:36:28.38#ibcon#*after write, iclass 23, count 0 2006.175.07:36:28.38#ibcon#*before return 0, iclass 23, count 0 2006.175.07:36:28.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:28.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:28.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:36:28.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:36:28.38$vc4f8/va=2,7 2006.175.07:36:28.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.07:36:28.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.07:36:28.38#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:28.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:28.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:28.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:28.44#ibcon#enter wrdev, iclass 25, count 2 2006.175.07:36:28.44#ibcon#first serial, iclass 25, count 2 2006.175.07:36:28.44#ibcon#enter sib2, iclass 25, count 2 2006.175.07:36:28.44#ibcon#flushed, iclass 25, count 2 2006.175.07:36:28.44#ibcon#about to write, iclass 25, count 2 2006.175.07:36:28.44#ibcon#wrote, iclass 25, count 2 2006.175.07:36:28.44#ibcon#about to read 3, iclass 25, count 2 2006.175.07:36:28.46#ibcon#read 3, iclass 25, count 2 2006.175.07:36:28.46#ibcon#about to read 4, iclass 25, count 2 2006.175.07:36:28.46#ibcon#read 4, iclass 25, count 2 2006.175.07:36:28.46#ibcon#about to read 5, iclass 25, count 2 2006.175.07:36:28.46#ibcon#read 5, iclass 25, count 2 2006.175.07:36:28.46#ibcon#about to read 6, iclass 25, count 2 2006.175.07:36:28.46#ibcon#read 6, iclass 25, count 2 2006.175.07:36:28.46#ibcon#end of sib2, iclass 25, count 2 2006.175.07:36:28.46#ibcon#*mode == 0, iclass 25, count 2 2006.175.07:36:28.46#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.07:36:28.46#ibcon#[25=AT02-07\r\n] 2006.175.07:36:28.46#ibcon#*before write, iclass 25, count 2 2006.175.07:36:28.46#ibcon#enter sib2, iclass 25, count 2 2006.175.07:36:28.46#ibcon#flushed, iclass 25, count 2 2006.175.07:36:28.46#ibcon#about to write, iclass 25, count 2 2006.175.07:36:28.46#ibcon#wrote, iclass 25, count 2 2006.175.07:36:28.46#ibcon#about to read 3, iclass 25, count 2 2006.175.07:36:28.49#ibcon#read 3, iclass 25, count 2 2006.175.07:36:28.49#ibcon#about to read 4, iclass 25, count 2 2006.175.07:36:28.49#ibcon#read 4, iclass 25, count 2 2006.175.07:36:28.49#ibcon#about to read 5, iclass 25, count 2 2006.175.07:36:28.49#ibcon#read 5, iclass 25, count 2 2006.175.07:36:28.49#ibcon#about to read 6, iclass 25, count 2 2006.175.07:36:28.49#ibcon#read 6, iclass 25, count 2 2006.175.07:36:28.49#ibcon#end of sib2, iclass 25, count 2 2006.175.07:36:28.49#ibcon#*after write, iclass 25, count 2 2006.175.07:36:28.49#ibcon#*before return 0, iclass 25, count 2 2006.175.07:36:28.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:28.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:28.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.07:36:28.49#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:28.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:28.61#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:28.61#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:28.61#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:36:28.61#ibcon#first serial, iclass 25, count 0 2006.175.07:36:28.61#ibcon#enter sib2, iclass 25, count 0 2006.175.07:36:28.61#ibcon#flushed, iclass 25, count 0 2006.175.07:36:28.61#ibcon#about to write, iclass 25, count 0 2006.175.07:36:28.61#ibcon#wrote, iclass 25, count 0 2006.175.07:36:28.61#ibcon#about to read 3, iclass 25, count 0 2006.175.07:36:28.63#ibcon#read 3, iclass 25, count 0 2006.175.07:36:28.63#ibcon#about to read 4, iclass 25, count 0 2006.175.07:36:28.63#ibcon#read 4, iclass 25, count 0 2006.175.07:36:28.63#ibcon#about to read 5, iclass 25, count 0 2006.175.07:36:28.63#ibcon#read 5, iclass 25, count 0 2006.175.07:36:28.63#ibcon#about to read 6, iclass 25, count 0 2006.175.07:36:28.63#ibcon#read 6, iclass 25, count 0 2006.175.07:36:28.63#ibcon#end of sib2, iclass 25, count 0 2006.175.07:36:28.63#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:36:28.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:36:28.63#ibcon#[25=USB\r\n] 2006.175.07:36:28.63#ibcon#*before write, iclass 25, count 0 2006.175.07:36:28.63#ibcon#enter sib2, iclass 25, count 0 2006.175.07:36:28.63#ibcon#flushed, iclass 25, count 0 2006.175.07:36:28.63#ibcon#about to write, iclass 25, count 0 2006.175.07:36:28.63#ibcon#wrote, iclass 25, count 0 2006.175.07:36:28.63#ibcon#about to read 3, iclass 25, count 0 2006.175.07:36:28.66#ibcon#read 3, iclass 25, count 0 2006.175.07:36:28.66#ibcon#about to read 4, iclass 25, count 0 2006.175.07:36:28.66#ibcon#read 4, iclass 25, count 0 2006.175.07:36:28.66#ibcon#about to read 5, iclass 25, count 0 2006.175.07:36:28.66#ibcon#read 5, iclass 25, count 0 2006.175.07:36:28.66#ibcon#about to read 6, iclass 25, count 0 2006.175.07:36:28.66#ibcon#read 6, iclass 25, count 0 2006.175.07:36:28.66#ibcon#end of sib2, iclass 25, count 0 2006.175.07:36:28.66#ibcon#*after write, iclass 25, count 0 2006.175.07:36:28.66#ibcon#*before return 0, iclass 25, count 0 2006.175.07:36:28.66#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:28.66#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:28.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:36:28.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:36:28.66$vc4f8/valo=3,672.99 2006.175.07:36:28.66#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.07:36:28.66#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.07:36:28.66#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:28.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:28.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:28.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:28.66#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:36:28.66#ibcon#first serial, iclass 27, count 0 2006.175.07:36:28.66#ibcon#enter sib2, iclass 27, count 0 2006.175.07:36:28.66#ibcon#flushed, iclass 27, count 0 2006.175.07:36:28.66#ibcon#about to write, iclass 27, count 0 2006.175.07:36:28.66#ibcon#wrote, iclass 27, count 0 2006.175.07:36:28.66#ibcon#about to read 3, iclass 27, count 0 2006.175.07:36:28.68#ibcon#read 3, iclass 27, count 0 2006.175.07:36:28.68#ibcon#about to read 4, iclass 27, count 0 2006.175.07:36:28.68#ibcon#read 4, iclass 27, count 0 2006.175.07:36:28.68#ibcon#about to read 5, iclass 27, count 0 2006.175.07:36:28.68#ibcon#read 5, iclass 27, count 0 2006.175.07:36:28.68#ibcon#about to read 6, iclass 27, count 0 2006.175.07:36:28.68#ibcon#read 6, iclass 27, count 0 2006.175.07:36:28.68#ibcon#end of sib2, iclass 27, count 0 2006.175.07:36:28.68#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:36:28.68#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:36:28.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:36:28.68#ibcon#*before write, iclass 27, count 0 2006.175.07:36:28.68#ibcon#enter sib2, iclass 27, count 0 2006.175.07:36:28.68#ibcon#flushed, iclass 27, count 0 2006.175.07:36:28.68#ibcon#about to write, iclass 27, count 0 2006.175.07:36:28.68#ibcon#wrote, iclass 27, count 0 2006.175.07:36:28.68#ibcon#about to read 3, iclass 27, count 0 2006.175.07:36:28.72#ibcon#read 3, iclass 27, count 0 2006.175.07:36:28.72#ibcon#about to read 4, iclass 27, count 0 2006.175.07:36:28.72#ibcon#read 4, iclass 27, count 0 2006.175.07:36:28.72#ibcon#about to read 5, iclass 27, count 0 2006.175.07:36:28.72#ibcon#read 5, iclass 27, count 0 2006.175.07:36:28.72#ibcon#about to read 6, iclass 27, count 0 2006.175.07:36:28.72#ibcon#read 6, iclass 27, count 0 2006.175.07:36:28.72#ibcon#end of sib2, iclass 27, count 0 2006.175.07:36:28.72#ibcon#*after write, iclass 27, count 0 2006.175.07:36:28.72#ibcon#*before return 0, iclass 27, count 0 2006.175.07:36:28.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:28.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:28.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:36:28.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:36:28.72$vc4f8/va=3,6 2006.175.07:36:28.72#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.175.07:36:28.72#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.175.07:36:28.72#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:28.72#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:28.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:28.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:28.78#ibcon#enter wrdev, iclass 29, count 2 2006.175.07:36:28.78#ibcon#first serial, iclass 29, count 2 2006.175.07:36:28.78#ibcon#enter sib2, iclass 29, count 2 2006.175.07:36:28.78#ibcon#flushed, iclass 29, count 2 2006.175.07:36:28.78#ibcon#about to write, iclass 29, count 2 2006.175.07:36:28.78#ibcon#wrote, iclass 29, count 2 2006.175.07:36:28.78#ibcon#about to read 3, iclass 29, count 2 2006.175.07:36:28.80#ibcon#read 3, iclass 29, count 2 2006.175.07:36:28.80#ibcon#about to read 4, iclass 29, count 2 2006.175.07:36:28.80#ibcon#read 4, iclass 29, count 2 2006.175.07:36:28.80#ibcon#about to read 5, iclass 29, count 2 2006.175.07:36:28.80#ibcon#read 5, iclass 29, count 2 2006.175.07:36:28.80#ibcon#about to read 6, iclass 29, count 2 2006.175.07:36:28.80#ibcon#read 6, iclass 29, count 2 2006.175.07:36:28.80#ibcon#end of sib2, iclass 29, count 2 2006.175.07:36:28.80#ibcon#*mode == 0, iclass 29, count 2 2006.175.07:36:28.80#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.175.07:36:28.80#ibcon#[25=AT03-06\r\n] 2006.175.07:36:28.80#ibcon#*before write, iclass 29, count 2 2006.175.07:36:28.80#ibcon#enter sib2, iclass 29, count 2 2006.175.07:36:28.80#ibcon#flushed, iclass 29, count 2 2006.175.07:36:28.80#ibcon#about to write, iclass 29, count 2 2006.175.07:36:28.80#ibcon#wrote, iclass 29, count 2 2006.175.07:36:28.80#ibcon#about to read 3, iclass 29, count 2 2006.175.07:36:28.83#ibcon#read 3, iclass 29, count 2 2006.175.07:36:28.83#ibcon#about to read 4, iclass 29, count 2 2006.175.07:36:28.83#ibcon#read 4, iclass 29, count 2 2006.175.07:36:28.83#ibcon#about to read 5, iclass 29, count 2 2006.175.07:36:28.83#ibcon#read 5, iclass 29, count 2 2006.175.07:36:28.83#ibcon#about to read 6, iclass 29, count 2 2006.175.07:36:28.83#ibcon#read 6, iclass 29, count 2 2006.175.07:36:28.83#ibcon#end of sib2, iclass 29, count 2 2006.175.07:36:28.83#ibcon#*after write, iclass 29, count 2 2006.175.07:36:28.83#ibcon#*before return 0, iclass 29, count 2 2006.175.07:36:28.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:28.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:28.83#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.175.07:36:28.83#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:28.83#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:28.95#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:28.95#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:28.95#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:36:28.95#ibcon#first serial, iclass 29, count 0 2006.175.07:36:28.95#ibcon#enter sib2, iclass 29, count 0 2006.175.07:36:28.95#ibcon#flushed, iclass 29, count 0 2006.175.07:36:28.95#ibcon#about to write, iclass 29, count 0 2006.175.07:36:28.95#ibcon#wrote, iclass 29, count 0 2006.175.07:36:28.95#ibcon#about to read 3, iclass 29, count 0 2006.175.07:36:28.97#ibcon#read 3, iclass 29, count 0 2006.175.07:36:28.97#ibcon#about to read 4, iclass 29, count 0 2006.175.07:36:28.97#ibcon#read 4, iclass 29, count 0 2006.175.07:36:28.97#ibcon#about to read 5, iclass 29, count 0 2006.175.07:36:28.97#ibcon#read 5, iclass 29, count 0 2006.175.07:36:28.97#ibcon#about to read 6, iclass 29, count 0 2006.175.07:36:28.97#ibcon#read 6, iclass 29, count 0 2006.175.07:36:28.97#ibcon#end of sib2, iclass 29, count 0 2006.175.07:36:28.97#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:36:28.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:36:28.97#ibcon#[25=USB\r\n] 2006.175.07:36:28.97#ibcon#*before write, iclass 29, count 0 2006.175.07:36:28.97#ibcon#enter sib2, iclass 29, count 0 2006.175.07:36:28.97#ibcon#flushed, iclass 29, count 0 2006.175.07:36:28.97#ibcon#about to write, iclass 29, count 0 2006.175.07:36:28.97#ibcon#wrote, iclass 29, count 0 2006.175.07:36:28.97#ibcon#about to read 3, iclass 29, count 0 2006.175.07:36:29.00#ibcon#read 3, iclass 29, count 0 2006.175.07:36:29.00#ibcon#about to read 4, iclass 29, count 0 2006.175.07:36:29.00#ibcon#read 4, iclass 29, count 0 2006.175.07:36:29.00#ibcon#about to read 5, iclass 29, count 0 2006.175.07:36:29.00#ibcon#read 5, iclass 29, count 0 2006.175.07:36:29.00#ibcon#about to read 6, iclass 29, count 0 2006.175.07:36:29.00#ibcon#read 6, iclass 29, count 0 2006.175.07:36:29.00#ibcon#end of sib2, iclass 29, count 0 2006.175.07:36:29.00#ibcon#*after write, iclass 29, count 0 2006.175.07:36:29.00#ibcon#*before return 0, iclass 29, count 0 2006.175.07:36:29.00#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:29.00#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:29.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:36:29.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:36:29.00$vc4f8/valo=4,832.99 2006.175.07:36:29.00#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.07:36:29.00#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.07:36:29.00#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:29.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:29.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:29.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:29.00#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:36:29.00#ibcon#first serial, iclass 31, count 0 2006.175.07:36:29.00#ibcon#enter sib2, iclass 31, count 0 2006.175.07:36:29.00#ibcon#flushed, iclass 31, count 0 2006.175.07:36:29.00#ibcon#about to write, iclass 31, count 0 2006.175.07:36:29.00#ibcon#wrote, iclass 31, count 0 2006.175.07:36:29.00#ibcon#about to read 3, iclass 31, count 0 2006.175.07:36:29.02#ibcon#read 3, iclass 31, count 0 2006.175.07:36:29.02#ibcon#about to read 4, iclass 31, count 0 2006.175.07:36:29.02#ibcon#read 4, iclass 31, count 0 2006.175.07:36:29.02#ibcon#about to read 5, iclass 31, count 0 2006.175.07:36:29.02#ibcon#read 5, iclass 31, count 0 2006.175.07:36:29.02#ibcon#about to read 6, iclass 31, count 0 2006.175.07:36:29.02#ibcon#read 6, iclass 31, count 0 2006.175.07:36:29.02#ibcon#end of sib2, iclass 31, count 0 2006.175.07:36:29.02#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:36:29.02#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:36:29.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:36:29.02#ibcon#*before write, iclass 31, count 0 2006.175.07:36:29.02#ibcon#enter sib2, iclass 31, count 0 2006.175.07:36:29.02#ibcon#flushed, iclass 31, count 0 2006.175.07:36:29.02#ibcon#about to write, iclass 31, count 0 2006.175.07:36:29.02#ibcon#wrote, iclass 31, count 0 2006.175.07:36:29.02#ibcon#about to read 3, iclass 31, count 0 2006.175.07:36:29.06#ibcon#read 3, iclass 31, count 0 2006.175.07:36:29.06#ibcon#about to read 4, iclass 31, count 0 2006.175.07:36:29.06#ibcon#read 4, iclass 31, count 0 2006.175.07:36:29.06#ibcon#about to read 5, iclass 31, count 0 2006.175.07:36:29.06#ibcon#read 5, iclass 31, count 0 2006.175.07:36:29.06#ibcon#about to read 6, iclass 31, count 0 2006.175.07:36:29.06#ibcon#read 6, iclass 31, count 0 2006.175.07:36:29.06#ibcon#end of sib2, iclass 31, count 0 2006.175.07:36:29.06#ibcon#*after write, iclass 31, count 0 2006.175.07:36:29.06#ibcon#*before return 0, iclass 31, count 0 2006.175.07:36:29.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:29.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:29.06#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:36:29.06#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:36:29.06$vc4f8/va=4,7 2006.175.07:36:29.06#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.07:36:29.06#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.07:36:29.06#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:29.06#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:29.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:29.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:29.12#ibcon#enter wrdev, iclass 33, count 2 2006.175.07:36:29.12#ibcon#first serial, iclass 33, count 2 2006.175.07:36:29.12#ibcon#enter sib2, iclass 33, count 2 2006.175.07:36:29.12#ibcon#flushed, iclass 33, count 2 2006.175.07:36:29.12#ibcon#about to write, iclass 33, count 2 2006.175.07:36:29.12#ibcon#wrote, iclass 33, count 2 2006.175.07:36:29.12#ibcon#about to read 3, iclass 33, count 2 2006.175.07:36:29.14#ibcon#read 3, iclass 33, count 2 2006.175.07:36:29.14#ibcon#about to read 4, iclass 33, count 2 2006.175.07:36:29.14#ibcon#read 4, iclass 33, count 2 2006.175.07:36:29.14#ibcon#about to read 5, iclass 33, count 2 2006.175.07:36:29.14#ibcon#read 5, iclass 33, count 2 2006.175.07:36:29.14#ibcon#about to read 6, iclass 33, count 2 2006.175.07:36:29.14#ibcon#read 6, iclass 33, count 2 2006.175.07:36:29.14#ibcon#end of sib2, iclass 33, count 2 2006.175.07:36:29.14#ibcon#*mode == 0, iclass 33, count 2 2006.175.07:36:29.14#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.07:36:29.14#ibcon#[25=AT04-07\r\n] 2006.175.07:36:29.14#ibcon#*before write, iclass 33, count 2 2006.175.07:36:29.14#ibcon#enter sib2, iclass 33, count 2 2006.175.07:36:29.14#ibcon#flushed, iclass 33, count 2 2006.175.07:36:29.14#ibcon#about to write, iclass 33, count 2 2006.175.07:36:29.14#ibcon#wrote, iclass 33, count 2 2006.175.07:36:29.14#ibcon#about to read 3, iclass 33, count 2 2006.175.07:36:29.17#ibcon#read 3, iclass 33, count 2 2006.175.07:36:29.17#ibcon#about to read 4, iclass 33, count 2 2006.175.07:36:29.17#ibcon#read 4, iclass 33, count 2 2006.175.07:36:29.17#ibcon#about to read 5, iclass 33, count 2 2006.175.07:36:29.17#ibcon#read 5, iclass 33, count 2 2006.175.07:36:29.17#ibcon#about to read 6, iclass 33, count 2 2006.175.07:36:29.17#ibcon#read 6, iclass 33, count 2 2006.175.07:36:29.17#ibcon#end of sib2, iclass 33, count 2 2006.175.07:36:29.17#ibcon#*after write, iclass 33, count 2 2006.175.07:36:29.17#ibcon#*before return 0, iclass 33, count 2 2006.175.07:36:29.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:29.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:29.17#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.07:36:29.17#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:29.17#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:29.29#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:29.29#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:29.29#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:36:29.29#ibcon#first serial, iclass 33, count 0 2006.175.07:36:29.29#ibcon#enter sib2, iclass 33, count 0 2006.175.07:36:29.29#ibcon#flushed, iclass 33, count 0 2006.175.07:36:29.29#ibcon#about to write, iclass 33, count 0 2006.175.07:36:29.29#ibcon#wrote, iclass 33, count 0 2006.175.07:36:29.29#ibcon#about to read 3, iclass 33, count 0 2006.175.07:36:29.31#ibcon#read 3, iclass 33, count 0 2006.175.07:36:29.31#ibcon#about to read 4, iclass 33, count 0 2006.175.07:36:29.31#ibcon#read 4, iclass 33, count 0 2006.175.07:36:29.31#ibcon#about to read 5, iclass 33, count 0 2006.175.07:36:29.31#ibcon#read 5, iclass 33, count 0 2006.175.07:36:29.31#ibcon#about to read 6, iclass 33, count 0 2006.175.07:36:29.31#ibcon#read 6, iclass 33, count 0 2006.175.07:36:29.31#ibcon#end of sib2, iclass 33, count 0 2006.175.07:36:29.31#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:36:29.31#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:36:29.31#ibcon#[25=USB\r\n] 2006.175.07:36:29.31#ibcon#*before write, iclass 33, count 0 2006.175.07:36:29.31#ibcon#enter sib2, iclass 33, count 0 2006.175.07:36:29.31#ibcon#flushed, iclass 33, count 0 2006.175.07:36:29.31#ibcon#about to write, iclass 33, count 0 2006.175.07:36:29.31#ibcon#wrote, iclass 33, count 0 2006.175.07:36:29.31#ibcon#about to read 3, iclass 33, count 0 2006.175.07:36:29.34#ibcon#read 3, iclass 33, count 0 2006.175.07:36:29.34#ibcon#about to read 4, iclass 33, count 0 2006.175.07:36:29.34#ibcon#read 4, iclass 33, count 0 2006.175.07:36:29.34#ibcon#about to read 5, iclass 33, count 0 2006.175.07:36:29.34#ibcon#read 5, iclass 33, count 0 2006.175.07:36:29.34#ibcon#about to read 6, iclass 33, count 0 2006.175.07:36:29.34#ibcon#read 6, iclass 33, count 0 2006.175.07:36:29.34#ibcon#end of sib2, iclass 33, count 0 2006.175.07:36:29.34#ibcon#*after write, iclass 33, count 0 2006.175.07:36:29.34#ibcon#*before return 0, iclass 33, count 0 2006.175.07:36:29.34#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:29.34#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:29.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:36:29.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:36:29.34$vc4f8/valo=5,652.99 2006.175.07:36:29.34#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.07:36:29.34#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.07:36:29.34#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:29.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:29.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:29.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:29.34#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:36:29.34#ibcon#first serial, iclass 35, count 0 2006.175.07:36:29.34#ibcon#enter sib2, iclass 35, count 0 2006.175.07:36:29.34#ibcon#flushed, iclass 35, count 0 2006.175.07:36:29.34#ibcon#about to write, iclass 35, count 0 2006.175.07:36:29.34#ibcon#wrote, iclass 35, count 0 2006.175.07:36:29.34#ibcon#about to read 3, iclass 35, count 0 2006.175.07:36:29.36#ibcon#read 3, iclass 35, count 0 2006.175.07:36:29.36#ibcon#about to read 4, iclass 35, count 0 2006.175.07:36:29.36#ibcon#read 4, iclass 35, count 0 2006.175.07:36:29.36#ibcon#about to read 5, iclass 35, count 0 2006.175.07:36:29.36#ibcon#read 5, iclass 35, count 0 2006.175.07:36:29.36#ibcon#about to read 6, iclass 35, count 0 2006.175.07:36:29.36#ibcon#read 6, iclass 35, count 0 2006.175.07:36:29.36#ibcon#end of sib2, iclass 35, count 0 2006.175.07:36:29.36#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:36:29.36#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:36:29.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:36:29.36#ibcon#*before write, iclass 35, count 0 2006.175.07:36:29.36#ibcon#enter sib2, iclass 35, count 0 2006.175.07:36:29.36#ibcon#flushed, iclass 35, count 0 2006.175.07:36:29.36#ibcon#about to write, iclass 35, count 0 2006.175.07:36:29.36#ibcon#wrote, iclass 35, count 0 2006.175.07:36:29.36#ibcon#about to read 3, iclass 35, count 0 2006.175.07:36:29.40#ibcon#read 3, iclass 35, count 0 2006.175.07:36:29.40#ibcon#about to read 4, iclass 35, count 0 2006.175.07:36:29.40#ibcon#read 4, iclass 35, count 0 2006.175.07:36:29.40#ibcon#about to read 5, iclass 35, count 0 2006.175.07:36:29.40#ibcon#read 5, iclass 35, count 0 2006.175.07:36:29.40#ibcon#about to read 6, iclass 35, count 0 2006.175.07:36:29.40#ibcon#read 6, iclass 35, count 0 2006.175.07:36:29.40#ibcon#end of sib2, iclass 35, count 0 2006.175.07:36:29.40#ibcon#*after write, iclass 35, count 0 2006.175.07:36:29.40#ibcon#*before return 0, iclass 35, count 0 2006.175.07:36:29.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:29.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:29.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:36:29.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:36:29.40$vc4f8/va=5,7 2006.175.07:36:29.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.07:36:29.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.07:36:29.40#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:29.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:29.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:29.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:29.46#ibcon#enter wrdev, iclass 37, count 2 2006.175.07:36:29.46#ibcon#first serial, iclass 37, count 2 2006.175.07:36:29.46#ibcon#enter sib2, iclass 37, count 2 2006.175.07:36:29.46#ibcon#flushed, iclass 37, count 2 2006.175.07:36:29.46#ibcon#about to write, iclass 37, count 2 2006.175.07:36:29.46#ibcon#wrote, iclass 37, count 2 2006.175.07:36:29.46#ibcon#about to read 3, iclass 37, count 2 2006.175.07:36:29.48#ibcon#read 3, iclass 37, count 2 2006.175.07:36:29.48#ibcon#about to read 4, iclass 37, count 2 2006.175.07:36:29.48#ibcon#read 4, iclass 37, count 2 2006.175.07:36:29.48#ibcon#about to read 5, iclass 37, count 2 2006.175.07:36:29.48#ibcon#read 5, iclass 37, count 2 2006.175.07:36:29.48#ibcon#about to read 6, iclass 37, count 2 2006.175.07:36:29.48#ibcon#read 6, iclass 37, count 2 2006.175.07:36:29.48#ibcon#end of sib2, iclass 37, count 2 2006.175.07:36:29.48#ibcon#*mode == 0, iclass 37, count 2 2006.175.07:36:29.48#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.07:36:29.48#ibcon#[25=AT05-07\r\n] 2006.175.07:36:29.48#ibcon#*before write, iclass 37, count 2 2006.175.07:36:29.48#ibcon#enter sib2, iclass 37, count 2 2006.175.07:36:29.48#ibcon#flushed, iclass 37, count 2 2006.175.07:36:29.48#ibcon#about to write, iclass 37, count 2 2006.175.07:36:29.48#ibcon#wrote, iclass 37, count 2 2006.175.07:36:29.48#ibcon#about to read 3, iclass 37, count 2 2006.175.07:36:29.51#ibcon#read 3, iclass 37, count 2 2006.175.07:36:29.51#ibcon#about to read 4, iclass 37, count 2 2006.175.07:36:29.51#ibcon#read 4, iclass 37, count 2 2006.175.07:36:29.51#ibcon#about to read 5, iclass 37, count 2 2006.175.07:36:29.51#ibcon#read 5, iclass 37, count 2 2006.175.07:36:29.51#ibcon#about to read 6, iclass 37, count 2 2006.175.07:36:29.51#ibcon#read 6, iclass 37, count 2 2006.175.07:36:29.51#ibcon#end of sib2, iclass 37, count 2 2006.175.07:36:29.51#ibcon#*after write, iclass 37, count 2 2006.175.07:36:29.51#ibcon#*before return 0, iclass 37, count 2 2006.175.07:36:29.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:29.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:29.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.07:36:29.51#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:29.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:29.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:29.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:29.63#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:36:29.63#ibcon#first serial, iclass 37, count 0 2006.175.07:36:29.63#ibcon#enter sib2, iclass 37, count 0 2006.175.07:36:29.63#ibcon#flushed, iclass 37, count 0 2006.175.07:36:29.63#ibcon#about to write, iclass 37, count 0 2006.175.07:36:29.63#ibcon#wrote, iclass 37, count 0 2006.175.07:36:29.63#ibcon#about to read 3, iclass 37, count 0 2006.175.07:36:29.65#ibcon#read 3, iclass 37, count 0 2006.175.07:36:29.65#ibcon#about to read 4, iclass 37, count 0 2006.175.07:36:29.65#ibcon#read 4, iclass 37, count 0 2006.175.07:36:29.65#ibcon#about to read 5, iclass 37, count 0 2006.175.07:36:29.65#ibcon#read 5, iclass 37, count 0 2006.175.07:36:29.65#ibcon#about to read 6, iclass 37, count 0 2006.175.07:36:29.65#ibcon#read 6, iclass 37, count 0 2006.175.07:36:29.65#ibcon#end of sib2, iclass 37, count 0 2006.175.07:36:29.65#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:36:29.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:36:29.65#ibcon#[25=USB\r\n] 2006.175.07:36:29.65#ibcon#*before write, iclass 37, count 0 2006.175.07:36:29.65#ibcon#enter sib2, iclass 37, count 0 2006.175.07:36:29.65#ibcon#flushed, iclass 37, count 0 2006.175.07:36:29.65#ibcon#about to write, iclass 37, count 0 2006.175.07:36:29.65#ibcon#wrote, iclass 37, count 0 2006.175.07:36:29.65#ibcon#about to read 3, iclass 37, count 0 2006.175.07:36:29.68#ibcon#read 3, iclass 37, count 0 2006.175.07:36:29.68#ibcon#about to read 4, iclass 37, count 0 2006.175.07:36:29.68#ibcon#read 4, iclass 37, count 0 2006.175.07:36:29.68#ibcon#about to read 5, iclass 37, count 0 2006.175.07:36:29.68#ibcon#read 5, iclass 37, count 0 2006.175.07:36:29.68#ibcon#about to read 6, iclass 37, count 0 2006.175.07:36:29.68#ibcon#read 6, iclass 37, count 0 2006.175.07:36:29.68#ibcon#end of sib2, iclass 37, count 0 2006.175.07:36:29.68#ibcon#*after write, iclass 37, count 0 2006.175.07:36:29.68#ibcon#*before return 0, iclass 37, count 0 2006.175.07:36:29.68#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:29.68#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:29.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:36:29.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:36:29.68$vc4f8/valo=6,772.99 2006.175.07:36:29.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.07:36:29.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.07:36:29.68#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:29.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:29.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:29.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:29.68#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:36:29.68#ibcon#first serial, iclass 39, count 0 2006.175.07:36:29.68#ibcon#enter sib2, iclass 39, count 0 2006.175.07:36:29.68#ibcon#flushed, iclass 39, count 0 2006.175.07:36:29.68#ibcon#about to write, iclass 39, count 0 2006.175.07:36:29.68#ibcon#wrote, iclass 39, count 0 2006.175.07:36:29.68#ibcon#about to read 3, iclass 39, count 0 2006.175.07:36:29.70#ibcon#read 3, iclass 39, count 0 2006.175.07:36:29.70#ibcon#about to read 4, iclass 39, count 0 2006.175.07:36:29.70#ibcon#read 4, iclass 39, count 0 2006.175.07:36:29.70#ibcon#about to read 5, iclass 39, count 0 2006.175.07:36:29.70#ibcon#read 5, iclass 39, count 0 2006.175.07:36:29.70#ibcon#about to read 6, iclass 39, count 0 2006.175.07:36:29.70#ibcon#read 6, iclass 39, count 0 2006.175.07:36:29.70#ibcon#end of sib2, iclass 39, count 0 2006.175.07:36:29.70#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:36:29.70#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:36:29.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:36:29.70#ibcon#*before write, iclass 39, count 0 2006.175.07:36:29.70#ibcon#enter sib2, iclass 39, count 0 2006.175.07:36:29.70#ibcon#flushed, iclass 39, count 0 2006.175.07:36:29.70#ibcon#about to write, iclass 39, count 0 2006.175.07:36:29.70#ibcon#wrote, iclass 39, count 0 2006.175.07:36:29.70#ibcon#about to read 3, iclass 39, count 0 2006.175.07:36:29.74#ibcon#read 3, iclass 39, count 0 2006.175.07:36:29.74#ibcon#about to read 4, iclass 39, count 0 2006.175.07:36:29.74#ibcon#read 4, iclass 39, count 0 2006.175.07:36:29.74#ibcon#about to read 5, iclass 39, count 0 2006.175.07:36:29.74#ibcon#read 5, iclass 39, count 0 2006.175.07:36:29.74#ibcon#about to read 6, iclass 39, count 0 2006.175.07:36:29.74#ibcon#read 6, iclass 39, count 0 2006.175.07:36:29.74#ibcon#end of sib2, iclass 39, count 0 2006.175.07:36:29.74#ibcon#*after write, iclass 39, count 0 2006.175.07:36:29.74#ibcon#*before return 0, iclass 39, count 0 2006.175.07:36:29.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:29.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:29.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:36:29.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:36:29.74$vc4f8/va=6,6 2006.175.07:36:29.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.07:36:29.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.07:36:29.74#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:29.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:36:29.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:36:29.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:36:29.80#ibcon#enter wrdev, iclass 3, count 2 2006.175.07:36:29.80#ibcon#first serial, iclass 3, count 2 2006.175.07:36:29.80#ibcon#enter sib2, iclass 3, count 2 2006.175.07:36:29.80#ibcon#flushed, iclass 3, count 2 2006.175.07:36:29.80#ibcon#about to write, iclass 3, count 2 2006.175.07:36:29.80#ibcon#wrote, iclass 3, count 2 2006.175.07:36:29.80#ibcon#about to read 3, iclass 3, count 2 2006.175.07:36:29.82#ibcon#read 3, iclass 3, count 2 2006.175.07:36:29.82#ibcon#about to read 4, iclass 3, count 2 2006.175.07:36:29.82#ibcon#read 4, iclass 3, count 2 2006.175.07:36:29.82#ibcon#about to read 5, iclass 3, count 2 2006.175.07:36:29.82#ibcon#read 5, iclass 3, count 2 2006.175.07:36:29.82#ibcon#about to read 6, iclass 3, count 2 2006.175.07:36:29.82#ibcon#read 6, iclass 3, count 2 2006.175.07:36:29.82#ibcon#end of sib2, iclass 3, count 2 2006.175.07:36:29.82#ibcon#*mode == 0, iclass 3, count 2 2006.175.07:36:29.82#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.07:36:29.82#ibcon#[25=AT06-06\r\n] 2006.175.07:36:29.82#ibcon#*before write, iclass 3, count 2 2006.175.07:36:29.82#ibcon#enter sib2, iclass 3, count 2 2006.175.07:36:29.82#ibcon#flushed, iclass 3, count 2 2006.175.07:36:29.82#ibcon#about to write, iclass 3, count 2 2006.175.07:36:29.82#ibcon#wrote, iclass 3, count 2 2006.175.07:36:29.82#ibcon#about to read 3, iclass 3, count 2 2006.175.07:36:29.85#ibcon#read 3, iclass 3, count 2 2006.175.07:36:29.85#ibcon#about to read 4, iclass 3, count 2 2006.175.07:36:29.85#ibcon#read 4, iclass 3, count 2 2006.175.07:36:29.85#ibcon#about to read 5, iclass 3, count 2 2006.175.07:36:29.85#ibcon#read 5, iclass 3, count 2 2006.175.07:36:29.85#ibcon#about to read 6, iclass 3, count 2 2006.175.07:36:29.85#ibcon#read 6, iclass 3, count 2 2006.175.07:36:29.85#ibcon#end of sib2, iclass 3, count 2 2006.175.07:36:29.85#ibcon#*after write, iclass 3, count 2 2006.175.07:36:29.85#ibcon#*before return 0, iclass 3, count 2 2006.175.07:36:29.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:36:29.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:36:29.85#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.07:36:29.85#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:29.85#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:36:29.97#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:36:29.97#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:36:29.97#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:36:29.97#ibcon#first serial, iclass 3, count 0 2006.175.07:36:29.97#ibcon#enter sib2, iclass 3, count 0 2006.175.07:36:29.97#ibcon#flushed, iclass 3, count 0 2006.175.07:36:29.97#ibcon#about to write, iclass 3, count 0 2006.175.07:36:29.97#ibcon#wrote, iclass 3, count 0 2006.175.07:36:29.97#ibcon#about to read 3, iclass 3, count 0 2006.175.07:36:29.99#ibcon#read 3, iclass 3, count 0 2006.175.07:36:29.99#ibcon#about to read 4, iclass 3, count 0 2006.175.07:36:29.99#ibcon#read 4, iclass 3, count 0 2006.175.07:36:29.99#ibcon#about to read 5, iclass 3, count 0 2006.175.07:36:29.99#ibcon#read 5, iclass 3, count 0 2006.175.07:36:29.99#ibcon#about to read 6, iclass 3, count 0 2006.175.07:36:29.99#ibcon#read 6, iclass 3, count 0 2006.175.07:36:29.99#ibcon#end of sib2, iclass 3, count 0 2006.175.07:36:29.99#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:36:29.99#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:36:29.99#ibcon#[25=USB\r\n] 2006.175.07:36:29.99#ibcon#*before write, iclass 3, count 0 2006.175.07:36:29.99#ibcon#enter sib2, iclass 3, count 0 2006.175.07:36:29.99#ibcon#flushed, iclass 3, count 0 2006.175.07:36:29.99#ibcon#about to write, iclass 3, count 0 2006.175.07:36:29.99#ibcon#wrote, iclass 3, count 0 2006.175.07:36:29.99#ibcon#about to read 3, iclass 3, count 0 2006.175.07:36:30.02#ibcon#read 3, iclass 3, count 0 2006.175.07:36:30.02#ibcon#about to read 4, iclass 3, count 0 2006.175.07:36:30.02#ibcon#read 4, iclass 3, count 0 2006.175.07:36:30.02#ibcon#about to read 5, iclass 3, count 0 2006.175.07:36:30.02#ibcon#read 5, iclass 3, count 0 2006.175.07:36:30.02#ibcon#about to read 6, iclass 3, count 0 2006.175.07:36:30.02#ibcon#read 6, iclass 3, count 0 2006.175.07:36:30.02#ibcon#end of sib2, iclass 3, count 0 2006.175.07:36:30.02#ibcon#*after write, iclass 3, count 0 2006.175.07:36:30.02#ibcon#*before return 0, iclass 3, count 0 2006.175.07:36:30.02#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:36:30.02#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:36:30.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:36:30.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:36:30.02$vc4f8/valo=7,832.99 2006.175.07:36:30.02#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.07:36:30.02#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.07:36:30.02#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:30.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:36:30.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:36:30.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:36:30.02#ibcon#enter wrdev, iclass 5, count 0 2006.175.07:36:30.02#ibcon#first serial, iclass 5, count 0 2006.175.07:36:30.02#ibcon#enter sib2, iclass 5, count 0 2006.175.07:36:30.02#ibcon#flushed, iclass 5, count 0 2006.175.07:36:30.02#ibcon#about to write, iclass 5, count 0 2006.175.07:36:30.02#ibcon#wrote, iclass 5, count 0 2006.175.07:36:30.02#ibcon#about to read 3, iclass 5, count 0 2006.175.07:36:30.04#ibcon#read 3, iclass 5, count 0 2006.175.07:36:30.04#ibcon#about to read 4, iclass 5, count 0 2006.175.07:36:30.04#ibcon#read 4, iclass 5, count 0 2006.175.07:36:30.04#ibcon#about to read 5, iclass 5, count 0 2006.175.07:36:30.04#ibcon#read 5, iclass 5, count 0 2006.175.07:36:30.04#ibcon#about to read 6, iclass 5, count 0 2006.175.07:36:30.04#ibcon#read 6, iclass 5, count 0 2006.175.07:36:30.04#ibcon#end of sib2, iclass 5, count 0 2006.175.07:36:30.04#ibcon#*mode == 0, iclass 5, count 0 2006.175.07:36:30.04#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.07:36:30.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:36:30.04#ibcon#*before write, iclass 5, count 0 2006.175.07:36:30.04#ibcon#enter sib2, iclass 5, count 0 2006.175.07:36:30.04#ibcon#flushed, iclass 5, count 0 2006.175.07:36:30.04#ibcon#about to write, iclass 5, count 0 2006.175.07:36:30.04#ibcon#wrote, iclass 5, count 0 2006.175.07:36:30.04#ibcon#about to read 3, iclass 5, count 0 2006.175.07:36:30.08#ibcon#read 3, iclass 5, count 0 2006.175.07:36:30.08#ibcon#about to read 4, iclass 5, count 0 2006.175.07:36:30.08#ibcon#read 4, iclass 5, count 0 2006.175.07:36:30.08#ibcon#about to read 5, iclass 5, count 0 2006.175.07:36:30.08#ibcon#read 5, iclass 5, count 0 2006.175.07:36:30.08#ibcon#about to read 6, iclass 5, count 0 2006.175.07:36:30.08#ibcon#read 6, iclass 5, count 0 2006.175.07:36:30.08#ibcon#end of sib2, iclass 5, count 0 2006.175.07:36:30.08#ibcon#*after write, iclass 5, count 0 2006.175.07:36:30.08#ibcon#*before return 0, iclass 5, count 0 2006.175.07:36:30.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:36:30.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:36:30.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.07:36:30.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.07:36:30.08$vc4f8/va=7,6 2006.175.07:36:30.08#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.07:36:30.08#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.07:36:30.08#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:30.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:36:30.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:36:30.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:36:30.14#ibcon#enter wrdev, iclass 7, count 2 2006.175.07:36:30.14#ibcon#first serial, iclass 7, count 2 2006.175.07:36:30.14#ibcon#enter sib2, iclass 7, count 2 2006.175.07:36:30.14#ibcon#flushed, iclass 7, count 2 2006.175.07:36:30.14#ibcon#about to write, iclass 7, count 2 2006.175.07:36:30.14#ibcon#wrote, iclass 7, count 2 2006.175.07:36:30.14#ibcon#about to read 3, iclass 7, count 2 2006.175.07:36:30.16#ibcon#read 3, iclass 7, count 2 2006.175.07:36:30.16#ibcon#about to read 4, iclass 7, count 2 2006.175.07:36:30.16#ibcon#read 4, iclass 7, count 2 2006.175.07:36:30.16#ibcon#about to read 5, iclass 7, count 2 2006.175.07:36:30.16#ibcon#read 5, iclass 7, count 2 2006.175.07:36:30.16#ibcon#about to read 6, iclass 7, count 2 2006.175.07:36:30.16#ibcon#read 6, iclass 7, count 2 2006.175.07:36:30.16#ibcon#end of sib2, iclass 7, count 2 2006.175.07:36:30.16#ibcon#*mode == 0, iclass 7, count 2 2006.175.07:36:30.16#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.07:36:30.16#ibcon#[25=AT07-06\r\n] 2006.175.07:36:30.16#ibcon#*before write, iclass 7, count 2 2006.175.07:36:30.16#ibcon#enter sib2, iclass 7, count 2 2006.175.07:36:30.16#ibcon#flushed, iclass 7, count 2 2006.175.07:36:30.16#ibcon#about to write, iclass 7, count 2 2006.175.07:36:30.16#ibcon#wrote, iclass 7, count 2 2006.175.07:36:30.16#ibcon#about to read 3, iclass 7, count 2 2006.175.07:36:30.19#ibcon#read 3, iclass 7, count 2 2006.175.07:36:30.19#ibcon#about to read 4, iclass 7, count 2 2006.175.07:36:30.19#ibcon#read 4, iclass 7, count 2 2006.175.07:36:30.19#ibcon#about to read 5, iclass 7, count 2 2006.175.07:36:30.19#ibcon#read 5, iclass 7, count 2 2006.175.07:36:30.19#ibcon#about to read 6, iclass 7, count 2 2006.175.07:36:30.19#ibcon#read 6, iclass 7, count 2 2006.175.07:36:30.19#ibcon#end of sib2, iclass 7, count 2 2006.175.07:36:30.19#ibcon#*after write, iclass 7, count 2 2006.175.07:36:30.19#ibcon#*before return 0, iclass 7, count 2 2006.175.07:36:30.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:36:30.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:36:30.19#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.07:36:30.19#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:30.19#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:36:30.31#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:36:30.31#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:36:30.31#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:36:30.31#ibcon#first serial, iclass 7, count 0 2006.175.07:36:30.31#ibcon#enter sib2, iclass 7, count 0 2006.175.07:36:30.31#ibcon#flushed, iclass 7, count 0 2006.175.07:36:30.31#ibcon#about to write, iclass 7, count 0 2006.175.07:36:30.31#ibcon#wrote, iclass 7, count 0 2006.175.07:36:30.31#ibcon#about to read 3, iclass 7, count 0 2006.175.07:36:30.33#ibcon#read 3, iclass 7, count 0 2006.175.07:36:30.33#ibcon#about to read 4, iclass 7, count 0 2006.175.07:36:30.33#ibcon#read 4, iclass 7, count 0 2006.175.07:36:30.33#ibcon#about to read 5, iclass 7, count 0 2006.175.07:36:30.33#ibcon#read 5, iclass 7, count 0 2006.175.07:36:30.33#ibcon#about to read 6, iclass 7, count 0 2006.175.07:36:30.33#ibcon#read 6, iclass 7, count 0 2006.175.07:36:30.33#ibcon#end of sib2, iclass 7, count 0 2006.175.07:36:30.33#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:36:30.33#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:36:30.33#ibcon#[25=USB\r\n] 2006.175.07:36:30.33#ibcon#*before write, iclass 7, count 0 2006.175.07:36:30.33#ibcon#enter sib2, iclass 7, count 0 2006.175.07:36:30.33#ibcon#flushed, iclass 7, count 0 2006.175.07:36:30.33#ibcon#about to write, iclass 7, count 0 2006.175.07:36:30.33#ibcon#wrote, iclass 7, count 0 2006.175.07:36:30.33#ibcon#about to read 3, iclass 7, count 0 2006.175.07:36:30.36#ibcon#read 3, iclass 7, count 0 2006.175.07:36:30.36#ibcon#about to read 4, iclass 7, count 0 2006.175.07:36:30.36#ibcon#read 4, iclass 7, count 0 2006.175.07:36:30.36#ibcon#about to read 5, iclass 7, count 0 2006.175.07:36:30.36#ibcon#read 5, iclass 7, count 0 2006.175.07:36:30.36#ibcon#about to read 6, iclass 7, count 0 2006.175.07:36:30.36#ibcon#read 6, iclass 7, count 0 2006.175.07:36:30.36#ibcon#end of sib2, iclass 7, count 0 2006.175.07:36:30.36#ibcon#*after write, iclass 7, count 0 2006.175.07:36:30.36#ibcon#*before return 0, iclass 7, count 0 2006.175.07:36:30.36#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:36:30.36#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:36:30.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:36:30.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:36:30.36$vc4f8/valo=8,852.99 2006.175.07:36:30.36#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.07:36:30.36#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.07:36:30.36#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:30.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:36:30.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:36:30.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:36:30.36#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:36:30.36#ibcon#first serial, iclass 11, count 0 2006.175.07:36:30.36#ibcon#enter sib2, iclass 11, count 0 2006.175.07:36:30.36#ibcon#flushed, iclass 11, count 0 2006.175.07:36:30.36#ibcon#about to write, iclass 11, count 0 2006.175.07:36:30.36#ibcon#wrote, iclass 11, count 0 2006.175.07:36:30.36#ibcon#about to read 3, iclass 11, count 0 2006.175.07:36:30.38#ibcon#read 3, iclass 11, count 0 2006.175.07:36:30.38#ibcon#about to read 4, iclass 11, count 0 2006.175.07:36:30.38#ibcon#read 4, iclass 11, count 0 2006.175.07:36:30.38#ibcon#about to read 5, iclass 11, count 0 2006.175.07:36:30.38#ibcon#read 5, iclass 11, count 0 2006.175.07:36:30.38#ibcon#about to read 6, iclass 11, count 0 2006.175.07:36:30.38#ibcon#read 6, iclass 11, count 0 2006.175.07:36:30.38#ibcon#end of sib2, iclass 11, count 0 2006.175.07:36:30.38#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:36:30.38#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:36:30.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:36:30.38#ibcon#*before write, iclass 11, count 0 2006.175.07:36:30.38#ibcon#enter sib2, iclass 11, count 0 2006.175.07:36:30.38#ibcon#flushed, iclass 11, count 0 2006.175.07:36:30.38#ibcon#about to write, iclass 11, count 0 2006.175.07:36:30.38#ibcon#wrote, iclass 11, count 0 2006.175.07:36:30.38#ibcon#about to read 3, iclass 11, count 0 2006.175.07:36:30.42#ibcon#read 3, iclass 11, count 0 2006.175.07:36:30.42#ibcon#about to read 4, iclass 11, count 0 2006.175.07:36:30.42#ibcon#read 4, iclass 11, count 0 2006.175.07:36:30.42#ibcon#about to read 5, iclass 11, count 0 2006.175.07:36:30.42#ibcon#read 5, iclass 11, count 0 2006.175.07:36:30.42#ibcon#about to read 6, iclass 11, count 0 2006.175.07:36:30.42#ibcon#read 6, iclass 11, count 0 2006.175.07:36:30.42#ibcon#end of sib2, iclass 11, count 0 2006.175.07:36:30.42#ibcon#*after write, iclass 11, count 0 2006.175.07:36:30.42#ibcon#*before return 0, iclass 11, count 0 2006.175.07:36:30.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:36:30.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:36:30.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:36:30.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:36:30.42$vc4f8/va=8,6 2006.175.07:36:30.42#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.07:36:30.42#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.07:36:30.42#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:30.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:36:30.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:36:30.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:36:30.48#ibcon#enter wrdev, iclass 13, count 2 2006.175.07:36:30.48#ibcon#first serial, iclass 13, count 2 2006.175.07:36:30.48#ibcon#enter sib2, iclass 13, count 2 2006.175.07:36:30.48#ibcon#flushed, iclass 13, count 2 2006.175.07:36:30.48#ibcon#about to write, iclass 13, count 2 2006.175.07:36:30.48#ibcon#wrote, iclass 13, count 2 2006.175.07:36:30.48#ibcon#about to read 3, iclass 13, count 2 2006.175.07:36:30.50#ibcon#read 3, iclass 13, count 2 2006.175.07:36:30.50#ibcon#about to read 4, iclass 13, count 2 2006.175.07:36:30.50#ibcon#read 4, iclass 13, count 2 2006.175.07:36:30.50#ibcon#about to read 5, iclass 13, count 2 2006.175.07:36:30.50#ibcon#read 5, iclass 13, count 2 2006.175.07:36:30.50#ibcon#about to read 6, iclass 13, count 2 2006.175.07:36:30.50#ibcon#read 6, iclass 13, count 2 2006.175.07:36:30.50#ibcon#end of sib2, iclass 13, count 2 2006.175.07:36:30.50#ibcon#*mode == 0, iclass 13, count 2 2006.175.07:36:30.50#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.07:36:30.50#ibcon#[25=AT08-06\r\n] 2006.175.07:36:30.50#ibcon#*before write, iclass 13, count 2 2006.175.07:36:30.50#ibcon#enter sib2, iclass 13, count 2 2006.175.07:36:30.50#ibcon#flushed, iclass 13, count 2 2006.175.07:36:30.50#ibcon#about to write, iclass 13, count 2 2006.175.07:36:30.50#ibcon#wrote, iclass 13, count 2 2006.175.07:36:30.50#ibcon#about to read 3, iclass 13, count 2 2006.175.07:36:30.53#ibcon#read 3, iclass 13, count 2 2006.175.07:36:30.53#ibcon#about to read 4, iclass 13, count 2 2006.175.07:36:30.53#ibcon#read 4, iclass 13, count 2 2006.175.07:36:30.53#ibcon#about to read 5, iclass 13, count 2 2006.175.07:36:30.53#ibcon#read 5, iclass 13, count 2 2006.175.07:36:30.53#ibcon#about to read 6, iclass 13, count 2 2006.175.07:36:30.53#ibcon#read 6, iclass 13, count 2 2006.175.07:36:30.53#ibcon#end of sib2, iclass 13, count 2 2006.175.07:36:30.53#ibcon#*after write, iclass 13, count 2 2006.175.07:36:30.53#ibcon#*before return 0, iclass 13, count 2 2006.175.07:36:30.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:36:30.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:36:30.53#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.07:36:30.53#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:30.53#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:36:30.65#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:36:30.65#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:36:30.65#ibcon#enter wrdev, iclass 13, count 0 2006.175.07:36:30.65#ibcon#first serial, iclass 13, count 0 2006.175.07:36:30.65#ibcon#enter sib2, iclass 13, count 0 2006.175.07:36:30.65#ibcon#flushed, iclass 13, count 0 2006.175.07:36:30.65#ibcon#about to write, iclass 13, count 0 2006.175.07:36:30.65#ibcon#wrote, iclass 13, count 0 2006.175.07:36:30.65#ibcon#about to read 3, iclass 13, count 0 2006.175.07:36:30.67#ibcon#read 3, iclass 13, count 0 2006.175.07:36:30.67#ibcon#about to read 4, iclass 13, count 0 2006.175.07:36:30.67#ibcon#read 4, iclass 13, count 0 2006.175.07:36:30.67#ibcon#about to read 5, iclass 13, count 0 2006.175.07:36:30.67#ibcon#read 5, iclass 13, count 0 2006.175.07:36:30.67#ibcon#about to read 6, iclass 13, count 0 2006.175.07:36:30.67#ibcon#read 6, iclass 13, count 0 2006.175.07:36:30.67#ibcon#end of sib2, iclass 13, count 0 2006.175.07:36:30.67#ibcon#*mode == 0, iclass 13, count 0 2006.175.07:36:30.67#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.07:36:30.67#ibcon#[25=USB\r\n] 2006.175.07:36:30.67#ibcon#*before write, iclass 13, count 0 2006.175.07:36:30.67#ibcon#enter sib2, iclass 13, count 0 2006.175.07:36:30.67#ibcon#flushed, iclass 13, count 0 2006.175.07:36:30.67#ibcon#about to write, iclass 13, count 0 2006.175.07:36:30.67#ibcon#wrote, iclass 13, count 0 2006.175.07:36:30.67#ibcon#about to read 3, iclass 13, count 0 2006.175.07:36:30.70#ibcon#read 3, iclass 13, count 0 2006.175.07:36:30.70#ibcon#about to read 4, iclass 13, count 0 2006.175.07:36:30.70#ibcon#read 4, iclass 13, count 0 2006.175.07:36:30.70#ibcon#about to read 5, iclass 13, count 0 2006.175.07:36:30.70#ibcon#read 5, iclass 13, count 0 2006.175.07:36:30.70#ibcon#about to read 6, iclass 13, count 0 2006.175.07:36:30.70#ibcon#read 6, iclass 13, count 0 2006.175.07:36:30.70#ibcon#end of sib2, iclass 13, count 0 2006.175.07:36:30.70#ibcon#*after write, iclass 13, count 0 2006.175.07:36:30.70#ibcon#*before return 0, iclass 13, count 0 2006.175.07:36:30.70#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:36:30.70#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:36:30.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.07:36:30.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.07:36:30.70$vc4f8/vblo=1,632.99 2006.175.07:36:30.70#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.07:36:30.70#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.07:36:30.70#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:30.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:36:30.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:36:30.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:36:30.70#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:36:30.70#ibcon#first serial, iclass 15, count 0 2006.175.07:36:30.70#ibcon#enter sib2, iclass 15, count 0 2006.175.07:36:30.70#ibcon#flushed, iclass 15, count 0 2006.175.07:36:30.70#ibcon#about to write, iclass 15, count 0 2006.175.07:36:30.70#ibcon#wrote, iclass 15, count 0 2006.175.07:36:30.70#ibcon#about to read 3, iclass 15, count 0 2006.175.07:36:30.72#ibcon#read 3, iclass 15, count 0 2006.175.07:36:30.72#ibcon#about to read 4, iclass 15, count 0 2006.175.07:36:30.72#ibcon#read 4, iclass 15, count 0 2006.175.07:36:30.72#ibcon#about to read 5, iclass 15, count 0 2006.175.07:36:30.72#ibcon#read 5, iclass 15, count 0 2006.175.07:36:30.72#ibcon#about to read 6, iclass 15, count 0 2006.175.07:36:30.72#ibcon#read 6, iclass 15, count 0 2006.175.07:36:30.72#ibcon#end of sib2, iclass 15, count 0 2006.175.07:36:30.72#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:36:30.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:36:30.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:36:30.72#ibcon#*before write, iclass 15, count 0 2006.175.07:36:30.72#ibcon#enter sib2, iclass 15, count 0 2006.175.07:36:30.72#ibcon#flushed, iclass 15, count 0 2006.175.07:36:30.72#ibcon#about to write, iclass 15, count 0 2006.175.07:36:30.72#ibcon#wrote, iclass 15, count 0 2006.175.07:36:30.72#ibcon#about to read 3, iclass 15, count 0 2006.175.07:36:30.76#ibcon#read 3, iclass 15, count 0 2006.175.07:36:30.76#ibcon#about to read 4, iclass 15, count 0 2006.175.07:36:30.76#ibcon#read 4, iclass 15, count 0 2006.175.07:36:30.76#ibcon#about to read 5, iclass 15, count 0 2006.175.07:36:30.76#ibcon#read 5, iclass 15, count 0 2006.175.07:36:30.76#ibcon#about to read 6, iclass 15, count 0 2006.175.07:36:30.76#ibcon#read 6, iclass 15, count 0 2006.175.07:36:30.76#ibcon#end of sib2, iclass 15, count 0 2006.175.07:36:30.76#ibcon#*after write, iclass 15, count 0 2006.175.07:36:30.76#ibcon#*before return 0, iclass 15, count 0 2006.175.07:36:30.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:36:30.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:36:30.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:36:30.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:36:30.76$vc4f8/vb=1,4 2006.175.07:36:30.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.07:36:30.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.07:36:30.76#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:30.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:36:30.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:36:30.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:36:30.76#ibcon#enter wrdev, iclass 17, count 2 2006.175.07:36:30.76#ibcon#first serial, iclass 17, count 2 2006.175.07:36:30.76#ibcon#enter sib2, iclass 17, count 2 2006.175.07:36:30.76#ibcon#flushed, iclass 17, count 2 2006.175.07:36:30.76#ibcon#about to write, iclass 17, count 2 2006.175.07:36:30.76#ibcon#wrote, iclass 17, count 2 2006.175.07:36:30.76#ibcon#about to read 3, iclass 17, count 2 2006.175.07:36:30.78#ibcon#read 3, iclass 17, count 2 2006.175.07:36:30.78#ibcon#about to read 4, iclass 17, count 2 2006.175.07:36:30.78#ibcon#read 4, iclass 17, count 2 2006.175.07:36:30.78#ibcon#about to read 5, iclass 17, count 2 2006.175.07:36:30.78#ibcon#read 5, iclass 17, count 2 2006.175.07:36:30.78#ibcon#about to read 6, iclass 17, count 2 2006.175.07:36:30.78#ibcon#read 6, iclass 17, count 2 2006.175.07:36:30.78#ibcon#end of sib2, iclass 17, count 2 2006.175.07:36:30.78#ibcon#*mode == 0, iclass 17, count 2 2006.175.07:36:30.78#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.07:36:30.78#ibcon#[27=AT01-04\r\n] 2006.175.07:36:30.78#ibcon#*before write, iclass 17, count 2 2006.175.07:36:30.78#ibcon#enter sib2, iclass 17, count 2 2006.175.07:36:30.78#ibcon#flushed, iclass 17, count 2 2006.175.07:36:30.78#ibcon#about to write, iclass 17, count 2 2006.175.07:36:30.78#ibcon#wrote, iclass 17, count 2 2006.175.07:36:30.78#ibcon#about to read 3, iclass 17, count 2 2006.175.07:36:30.81#ibcon#read 3, iclass 17, count 2 2006.175.07:36:30.81#ibcon#about to read 4, iclass 17, count 2 2006.175.07:36:30.81#ibcon#read 4, iclass 17, count 2 2006.175.07:36:30.81#ibcon#about to read 5, iclass 17, count 2 2006.175.07:36:30.81#ibcon#read 5, iclass 17, count 2 2006.175.07:36:30.81#ibcon#about to read 6, iclass 17, count 2 2006.175.07:36:30.81#ibcon#read 6, iclass 17, count 2 2006.175.07:36:30.81#ibcon#end of sib2, iclass 17, count 2 2006.175.07:36:30.81#ibcon#*after write, iclass 17, count 2 2006.175.07:36:30.81#ibcon#*before return 0, iclass 17, count 2 2006.175.07:36:30.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:36:30.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:36:30.81#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.07:36:30.81#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:30.81#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:36:30.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:36:30.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:36:30.93#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:36:30.93#ibcon#first serial, iclass 17, count 0 2006.175.07:36:30.93#ibcon#enter sib2, iclass 17, count 0 2006.175.07:36:30.93#ibcon#flushed, iclass 17, count 0 2006.175.07:36:30.93#ibcon#about to write, iclass 17, count 0 2006.175.07:36:30.93#ibcon#wrote, iclass 17, count 0 2006.175.07:36:30.93#ibcon#about to read 3, iclass 17, count 0 2006.175.07:36:30.95#ibcon#read 3, iclass 17, count 0 2006.175.07:36:30.95#ibcon#about to read 4, iclass 17, count 0 2006.175.07:36:30.95#ibcon#read 4, iclass 17, count 0 2006.175.07:36:30.95#ibcon#about to read 5, iclass 17, count 0 2006.175.07:36:30.95#ibcon#read 5, iclass 17, count 0 2006.175.07:36:30.95#ibcon#about to read 6, iclass 17, count 0 2006.175.07:36:30.95#ibcon#read 6, iclass 17, count 0 2006.175.07:36:30.95#ibcon#end of sib2, iclass 17, count 0 2006.175.07:36:30.95#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:36:30.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:36:30.95#ibcon#[27=USB\r\n] 2006.175.07:36:30.95#ibcon#*before write, iclass 17, count 0 2006.175.07:36:30.95#ibcon#enter sib2, iclass 17, count 0 2006.175.07:36:30.95#ibcon#flushed, iclass 17, count 0 2006.175.07:36:30.95#ibcon#about to write, iclass 17, count 0 2006.175.07:36:30.95#ibcon#wrote, iclass 17, count 0 2006.175.07:36:30.95#ibcon#about to read 3, iclass 17, count 0 2006.175.07:36:30.98#ibcon#read 3, iclass 17, count 0 2006.175.07:36:30.98#ibcon#about to read 4, iclass 17, count 0 2006.175.07:36:30.98#ibcon#read 4, iclass 17, count 0 2006.175.07:36:30.98#ibcon#about to read 5, iclass 17, count 0 2006.175.07:36:30.98#ibcon#read 5, iclass 17, count 0 2006.175.07:36:30.98#ibcon#about to read 6, iclass 17, count 0 2006.175.07:36:30.98#ibcon#read 6, iclass 17, count 0 2006.175.07:36:30.98#ibcon#end of sib2, iclass 17, count 0 2006.175.07:36:30.98#ibcon#*after write, iclass 17, count 0 2006.175.07:36:30.98#ibcon#*before return 0, iclass 17, count 0 2006.175.07:36:30.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:36:30.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:36:30.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:36:30.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:36:30.98$vc4f8/vblo=2,640.99 2006.175.07:36:30.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.07:36:30.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.07:36:30.98#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:30.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:30.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:30.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:30.98#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:36:30.98#ibcon#first serial, iclass 19, count 0 2006.175.07:36:30.98#ibcon#enter sib2, iclass 19, count 0 2006.175.07:36:30.98#ibcon#flushed, iclass 19, count 0 2006.175.07:36:30.98#ibcon#about to write, iclass 19, count 0 2006.175.07:36:30.98#ibcon#wrote, iclass 19, count 0 2006.175.07:36:30.98#ibcon#about to read 3, iclass 19, count 0 2006.175.07:36:31.00#ibcon#read 3, iclass 19, count 0 2006.175.07:36:31.00#ibcon#about to read 4, iclass 19, count 0 2006.175.07:36:31.00#ibcon#read 4, iclass 19, count 0 2006.175.07:36:31.00#ibcon#about to read 5, iclass 19, count 0 2006.175.07:36:31.00#ibcon#read 5, iclass 19, count 0 2006.175.07:36:31.00#ibcon#about to read 6, iclass 19, count 0 2006.175.07:36:31.00#ibcon#read 6, iclass 19, count 0 2006.175.07:36:31.00#ibcon#end of sib2, iclass 19, count 0 2006.175.07:36:31.00#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:36:31.00#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:36:31.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:36:31.00#ibcon#*before write, iclass 19, count 0 2006.175.07:36:31.00#ibcon#enter sib2, iclass 19, count 0 2006.175.07:36:31.00#ibcon#flushed, iclass 19, count 0 2006.175.07:36:31.00#ibcon#about to write, iclass 19, count 0 2006.175.07:36:31.00#ibcon#wrote, iclass 19, count 0 2006.175.07:36:31.00#ibcon#about to read 3, iclass 19, count 0 2006.175.07:36:31.04#ibcon#read 3, iclass 19, count 0 2006.175.07:36:31.04#ibcon#about to read 4, iclass 19, count 0 2006.175.07:36:31.04#ibcon#read 4, iclass 19, count 0 2006.175.07:36:31.04#ibcon#about to read 5, iclass 19, count 0 2006.175.07:36:31.04#ibcon#read 5, iclass 19, count 0 2006.175.07:36:31.04#ibcon#about to read 6, iclass 19, count 0 2006.175.07:36:31.04#ibcon#read 6, iclass 19, count 0 2006.175.07:36:31.04#ibcon#end of sib2, iclass 19, count 0 2006.175.07:36:31.04#ibcon#*after write, iclass 19, count 0 2006.175.07:36:31.04#ibcon#*before return 0, iclass 19, count 0 2006.175.07:36:31.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:31.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:36:31.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:36:31.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:36:31.04$vc4f8/vb=2,4 2006.175.07:36:31.04#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.07:36:31.04#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.07:36:31.04#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:31.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:31.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:31.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:31.10#ibcon#enter wrdev, iclass 21, count 2 2006.175.07:36:31.10#ibcon#first serial, iclass 21, count 2 2006.175.07:36:31.10#ibcon#enter sib2, iclass 21, count 2 2006.175.07:36:31.10#ibcon#flushed, iclass 21, count 2 2006.175.07:36:31.10#ibcon#about to write, iclass 21, count 2 2006.175.07:36:31.10#ibcon#wrote, iclass 21, count 2 2006.175.07:36:31.10#ibcon#about to read 3, iclass 21, count 2 2006.175.07:36:31.12#ibcon#read 3, iclass 21, count 2 2006.175.07:36:31.12#ibcon#about to read 4, iclass 21, count 2 2006.175.07:36:31.12#ibcon#read 4, iclass 21, count 2 2006.175.07:36:31.12#ibcon#about to read 5, iclass 21, count 2 2006.175.07:36:31.12#ibcon#read 5, iclass 21, count 2 2006.175.07:36:31.12#ibcon#about to read 6, iclass 21, count 2 2006.175.07:36:31.12#ibcon#read 6, iclass 21, count 2 2006.175.07:36:31.12#ibcon#end of sib2, iclass 21, count 2 2006.175.07:36:31.12#ibcon#*mode == 0, iclass 21, count 2 2006.175.07:36:31.12#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.07:36:31.12#ibcon#[27=AT02-04\r\n] 2006.175.07:36:31.12#ibcon#*before write, iclass 21, count 2 2006.175.07:36:31.12#ibcon#enter sib2, iclass 21, count 2 2006.175.07:36:31.12#ibcon#flushed, iclass 21, count 2 2006.175.07:36:31.12#ibcon#about to write, iclass 21, count 2 2006.175.07:36:31.12#ibcon#wrote, iclass 21, count 2 2006.175.07:36:31.12#ibcon#about to read 3, iclass 21, count 2 2006.175.07:36:31.15#ibcon#read 3, iclass 21, count 2 2006.175.07:36:31.15#ibcon#about to read 4, iclass 21, count 2 2006.175.07:36:31.15#ibcon#read 4, iclass 21, count 2 2006.175.07:36:31.15#ibcon#about to read 5, iclass 21, count 2 2006.175.07:36:31.15#ibcon#read 5, iclass 21, count 2 2006.175.07:36:31.15#ibcon#about to read 6, iclass 21, count 2 2006.175.07:36:31.15#ibcon#read 6, iclass 21, count 2 2006.175.07:36:31.15#ibcon#end of sib2, iclass 21, count 2 2006.175.07:36:31.15#ibcon#*after write, iclass 21, count 2 2006.175.07:36:31.15#ibcon#*before return 0, iclass 21, count 2 2006.175.07:36:31.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:31.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:36:31.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.07:36:31.15#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:31.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:31.27#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:31.27#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:31.27#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:36:31.27#ibcon#first serial, iclass 21, count 0 2006.175.07:36:31.27#ibcon#enter sib2, iclass 21, count 0 2006.175.07:36:31.27#ibcon#flushed, iclass 21, count 0 2006.175.07:36:31.27#ibcon#about to write, iclass 21, count 0 2006.175.07:36:31.27#ibcon#wrote, iclass 21, count 0 2006.175.07:36:31.27#ibcon#about to read 3, iclass 21, count 0 2006.175.07:36:31.29#ibcon#read 3, iclass 21, count 0 2006.175.07:36:31.29#ibcon#about to read 4, iclass 21, count 0 2006.175.07:36:31.29#ibcon#read 4, iclass 21, count 0 2006.175.07:36:31.29#ibcon#about to read 5, iclass 21, count 0 2006.175.07:36:31.29#ibcon#read 5, iclass 21, count 0 2006.175.07:36:31.29#ibcon#about to read 6, iclass 21, count 0 2006.175.07:36:31.29#ibcon#read 6, iclass 21, count 0 2006.175.07:36:31.29#ibcon#end of sib2, iclass 21, count 0 2006.175.07:36:31.29#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:36:31.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:36:31.29#ibcon#[27=USB\r\n] 2006.175.07:36:31.29#ibcon#*before write, iclass 21, count 0 2006.175.07:36:31.29#ibcon#enter sib2, iclass 21, count 0 2006.175.07:36:31.29#ibcon#flushed, iclass 21, count 0 2006.175.07:36:31.29#ibcon#about to write, iclass 21, count 0 2006.175.07:36:31.29#ibcon#wrote, iclass 21, count 0 2006.175.07:36:31.29#ibcon#about to read 3, iclass 21, count 0 2006.175.07:36:31.32#ibcon#read 3, iclass 21, count 0 2006.175.07:36:31.32#ibcon#about to read 4, iclass 21, count 0 2006.175.07:36:31.32#ibcon#read 4, iclass 21, count 0 2006.175.07:36:31.32#ibcon#about to read 5, iclass 21, count 0 2006.175.07:36:31.32#ibcon#read 5, iclass 21, count 0 2006.175.07:36:31.32#ibcon#about to read 6, iclass 21, count 0 2006.175.07:36:31.32#ibcon#read 6, iclass 21, count 0 2006.175.07:36:31.32#ibcon#end of sib2, iclass 21, count 0 2006.175.07:36:31.32#ibcon#*after write, iclass 21, count 0 2006.175.07:36:31.32#ibcon#*before return 0, iclass 21, count 0 2006.175.07:36:31.32#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:31.32#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:36:31.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:36:31.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:36:31.32$vc4f8/vblo=3,656.99 2006.175.07:36:31.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.07:36:31.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.07:36:31.32#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:31.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:31.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:31.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:31.32#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:36:31.32#ibcon#first serial, iclass 23, count 0 2006.175.07:36:31.32#ibcon#enter sib2, iclass 23, count 0 2006.175.07:36:31.32#ibcon#flushed, iclass 23, count 0 2006.175.07:36:31.32#ibcon#about to write, iclass 23, count 0 2006.175.07:36:31.32#ibcon#wrote, iclass 23, count 0 2006.175.07:36:31.32#ibcon#about to read 3, iclass 23, count 0 2006.175.07:36:31.34#ibcon#read 3, iclass 23, count 0 2006.175.07:36:31.34#ibcon#about to read 4, iclass 23, count 0 2006.175.07:36:31.34#ibcon#read 4, iclass 23, count 0 2006.175.07:36:31.34#ibcon#about to read 5, iclass 23, count 0 2006.175.07:36:31.34#ibcon#read 5, iclass 23, count 0 2006.175.07:36:31.34#ibcon#about to read 6, iclass 23, count 0 2006.175.07:36:31.34#ibcon#read 6, iclass 23, count 0 2006.175.07:36:31.34#ibcon#end of sib2, iclass 23, count 0 2006.175.07:36:31.34#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:36:31.34#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:36:31.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:36:31.34#ibcon#*before write, iclass 23, count 0 2006.175.07:36:31.34#ibcon#enter sib2, iclass 23, count 0 2006.175.07:36:31.34#ibcon#flushed, iclass 23, count 0 2006.175.07:36:31.34#ibcon#about to write, iclass 23, count 0 2006.175.07:36:31.34#ibcon#wrote, iclass 23, count 0 2006.175.07:36:31.34#ibcon#about to read 3, iclass 23, count 0 2006.175.07:36:31.38#ibcon#read 3, iclass 23, count 0 2006.175.07:36:31.38#ibcon#about to read 4, iclass 23, count 0 2006.175.07:36:31.38#ibcon#read 4, iclass 23, count 0 2006.175.07:36:31.38#ibcon#about to read 5, iclass 23, count 0 2006.175.07:36:31.38#ibcon#read 5, iclass 23, count 0 2006.175.07:36:31.38#ibcon#about to read 6, iclass 23, count 0 2006.175.07:36:31.38#ibcon#read 6, iclass 23, count 0 2006.175.07:36:31.38#ibcon#end of sib2, iclass 23, count 0 2006.175.07:36:31.38#ibcon#*after write, iclass 23, count 0 2006.175.07:36:31.38#ibcon#*before return 0, iclass 23, count 0 2006.175.07:36:31.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:31.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:36:31.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:36:31.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:36:31.38$vc4f8/vb=3,4 2006.175.07:36:31.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.07:36:31.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.07:36:31.38#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:31.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:31.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:31.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:31.44#ibcon#enter wrdev, iclass 25, count 2 2006.175.07:36:31.44#ibcon#first serial, iclass 25, count 2 2006.175.07:36:31.44#ibcon#enter sib2, iclass 25, count 2 2006.175.07:36:31.44#ibcon#flushed, iclass 25, count 2 2006.175.07:36:31.44#ibcon#about to write, iclass 25, count 2 2006.175.07:36:31.44#ibcon#wrote, iclass 25, count 2 2006.175.07:36:31.44#ibcon#about to read 3, iclass 25, count 2 2006.175.07:36:31.46#ibcon#read 3, iclass 25, count 2 2006.175.07:36:31.46#ibcon#about to read 4, iclass 25, count 2 2006.175.07:36:31.46#ibcon#read 4, iclass 25, count 2 2006.175.07:36:31.46#ibcon#about to read 5, iclass 25, count 2 2006.175.07:36:31.46#ibcon#read 5, iclass 25, count 2 2006.175.07:36:31.46#ibcon#about to read 6, iclass 25, count 2 2006.175.07:36:31.46#ibcon#read 6, iclass 25, count 2 2006.175.07:36:31.46#ibcon#end of sib2, iclass 25, count 2 2006.175.07:36:31.46#ibcon#*mode == 0, iclass 25, count 2 2006.175.07:36:31.46#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.07:36:31.46#ibcon#[27=AT03-04\r\n] 2006.175.07:36:31.46#ibcon#*before write, iclass 25, count 2 2006.175.07:36:31.46#ibcon#enter sib2, iclass 25, count 2 2006.175.07:36:31.46#ibcon#flushed, iclass 25, count 2 2006.175.07:36:31.46#ibcon#about to write, iclass 25, count 2 2006.175.07:36:31.46#ibcon#wrote, iclass 25, count 2 2006.175.07:36:31.46#ibcon#about to read 3, iclass 25, count 2 2006.175.07:36:31.49#ibcon#read 3, iclass 25, count 2 2006.175.07:36:31.49#ibcon#about to read 4, iclass 25, count 2 2006.175.07:36:31.49#ibcon#read 4, iclass 25, count 2 2006.175.07:36:31.49#ibcon#about to read 5, iclass 25, count 2 2006.175.07:36:31.49#ibcon#read 5, iclass 25, count 2 2006.175.07:36:31.49#ibcon#about to read 6, iclass 25, count 2 2006.175.07:36:31.49#ibcon#read 6, iclass 25, count 2 2006.175.07:36:31.49#ibcon#end of sib2, iclass 25, count 2 2006.175.07:36:31.49#ibcon#*after write, iclass 25, count 2 2006.175.07:36:31.49#ibcon#*before return 0, iclass 25, count 2 2006.175.07:36:31.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:31.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:36:31.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.07:36:31.49#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:31.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:31.61#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:31.61#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:31.61#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:36:31.61#ibcon#first serial, iclass 25, count 0 2006.175.07:36:31.61#ibcon#enter sib2, iclass 25, count 0 2006.175.07:36:31.61#ibcon#flushed, iclass 25, count 0 2006.175.07:36:31.61#ibcon#about to write, iclass 25, count 0 2006.175.07:36:31.61#ibcon#wrote, iclass 25, count 0 2006.175.07:36:31.61#ibcon#about to read 3, iclass 25, count 0 2006.175.07:36:31.63#ibcon#read 3, iclass 25, count 0 2006.175.07:36:31.63#ibcon#about to read 4, iclass 25, count 0 2006.175.07:36:31.63#ibcon#read 4, iclass 25, count 0 2006.175.07:36:31.63#ibcon#about to read 5, iclass 25, count 0 2006.175.07:36:31.63#ibcon#read 5, iclass 25, count 0 2006.175.07:36:31.63#ibcon#about to read 6, iclass 25, count 0 2006.175.07:36:31.63#ibcon#read 6, iclass 25, count 0 2006.175.07:36:31.63#ibcon#end of sib2, iclass 25, count 0 2006.175.07:36:31.63#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:36:31.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:36:31.63#ibcon#[27=USB\r\n] 2006.175.07:36:31.63#ibcon#*before write, iclass 25, count 0 2006.175.07:36:31.63#ibcon#enter sib2, iclass 25, count 0 2006.175.07:36:31.63#ibcon#flushed, iclass 25, count 0 2006.175.07:36:31.63#ibcon#about to write, iclass 25, count 0 2006.175.07:36:31.63#ibcon#wrote, iclass 25, count 0 2006.175.07:36:31.63#ibcon#about to read 3, iclass 25, count 0 2006.175.07:36:31.66#ibcon#read 3, iclass 25, count 0 2006.175.07:36:31.66#ibcon#about to read 4, iclass 25, count 0 2006.175.07:36:31.66#ibcon#read 4, iclass 25, count 0 2006.175.07:36:31.66#ibcon#about to read 5, iclass 25, count 0 2006.175.07:36:31.66#ibcon#read 5, iclass 25, count 0 2006.175.07:36:31.66#ibcon#about to read 6, iclass 25, count 0 2006.175.07:36:31.66#ibcon#read 6, iclass 25, count 0 2006.175.07:36:31.66#ibcon#end of sib2, iclass 25, count 0 2006.175.07:36:31.66#ibcon#*after write, iclass 25, count 0 2006.175.07:36:31.66#ibcon#*before return 0, iclass 25, count 0 2006.175.07:36:31.66#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:31.66#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:36:31.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:36:31.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:36:31.66$vc4f8/vblo=4,712.99 2006.175.07:36:31.66#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.07:36:31.66#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.07:36:31.66#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:31.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:31.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:31.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:31.66#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:36:31.66#ibcon#first serial, iclass 27, count 0 2006.175.07:36:31.66#ibcon#enter sib2, iclass 27, count 0 2006.175.07:36:31.66#ibcon#flushed, iclass 27, count 0 2006.175.07:36:31.66#ibcon#about to write, iclass 27, count 0 2006.175.07:36:31.66#ibcon#wrote, iclass 27, count 0 2006.175.07:36:31.66#ibcon#about to read 3, iclass 27, count 0 2006.175.07:36:31.68#ibcon#read 3, iclass 27, count 0 2006.175.07:36:31.68#ibcon#about to read 4, iclass 27, count 0 2006.175.07:36:31.68#ibcon#read 4, iclass 27, count 0 2006.175.07:36:31.68#ibcon#about to read 5, iclass 27, count 0 2006.175.07:36:31.68#ibcon#read 5, iclass 27, count 0 2006.175.07:36:31.68#ibcon#about to read 6, iclass 27, count 0 2006.175.07:36:31.68#ibcon#read 6, iclass 27, count 0 2006.175.07:36:31.68#ibcon#end of sib2, iclass 27, count 0 2006.175.07:36:31.68#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:36:31.68#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:36:31.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:36:31.68#ibcon#*before write, iclass 27, count 0 2006.175.07:36:31.68#ibcon#enter sib2, iclass 27, count 0 2006.175.07:36:31.68#ibcon#flushed, iclass 27, count 0 2006.175.07:36:31.68#ibcon#about to write, iclass 27, count 0 2006.175.07:36:31.68#ibcon#wrote, iclass 27, count 0 2006.175.07:36:31.68#ibcon#about to read 3, iclass 27, count 0 2006.175.07:36:31.72#ibcon#read 3, iclass 27, count 0 2006.175.07:36:31.72#ibcon#about to read 4, iclass 27, count 0 2006.175.07:36:31.72#ibcon#read 4, iclass 27, count 0 2006.175.07:36:31.72#ibcon#about to read 5, iclass 27, count 0 2006.175.07:36:31.72#ibcon#read 5, iclass 27, count 0 2006.175.07:36:31.72#ibcon#about to read 6, iclass 27, count 0 2006.175.07:36:31.72#ibcon#read 6, iclass 27, count 0 2006.175.07:36:31.72#ibcon#end of sib2, iclass 27, count 0 2006.175.07:36:31.72#ibcon#*after write, iclass 27, count 0 2006.175.07:36:31.72#ibcon#*before return 0, iclass 27, count 0 2006.175.07:36:31.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:31.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:36:31.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:36:31.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:36:31.72$vc4f8/vb=4,4 2006.175.07:36:31.72#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.175.07:36:31.72#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.175.07:36:31.72#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:31.72#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:31.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:31.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:31.78#ibcon#enter wrdev, iclass 29, count 2 2006.175.07:36:31.78#ibcon#first serial, iclass 29, count 2 2006.175.07:36:31.78#ibcon#enter sib2, iclass 29, count 2 2006.175.07:36:31.78#ibcon#flushed, iclass 29, count 2 2006.175.07:36:31.78#ibcon#about to write, iclass 29, count 2 2006.175.07:36:31.78#ibcon#wrote, iclass 29, count 2 2006.175.07:36:31.78#ibcon#about to read 3, iclass 29, count 2 2006.175.07:36:31.80#ibcon#read 3, iclass 29, count 2 2006.175.07:36:31.80#ibcon#about to read 4, iclass 29, count 2 2006.175.07:36:31.80#ibcon#read 4, iclass 29, count 2 2006.175.07:36:31.80#ibcon#about to read 5, iclass 29, count 2 2006.175.07:36:31.80#ibcon#read 5, iclass 29, count 2 2006.175.07:36:31.80#ibcon#about to read 6, iclass 29, count 2 2006.175.07:36:31.80#ibcon#read 6, iclass 29, count 2 2006.175.07:36:31.80#ibcon#end of sib2, iclass 29, count 2 2006.175.07:36:31.80#ibcon#*mode == 0, iclass 29, count 2 2006.175.07:36:31.80#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.175.07:36:31.80#ibcon#[27=AT04-04\r\n] 2006.175.07:36:31.80#ibcon#*before write, iclass 29, count 2 2006.175.07:36:31.80#ibcon#enter sib2, iclass 29, count 2 2006.175.07:36:31.80#ibcon#flushed, iclass 29, count 2 2006.175.07:36:31.80#ibcon#about to write, iclass 29, count 2 2006.175.07:36:31.80#ibcon#wrote, iclass 29, count 2 2006.175.07:36:31.80#ibcon#about to read 3, iclass 29, count 2 2006.175.07:36:31.83#ibcon#read 3, iclass 29, count 2 2006.175.07:36:31.83#ibcon#about to read 4, iclass 29, count 2 2006.175.07:36:31.83#ibcon#read 4, iclass 29, count 2 2006.175.07:36:31.83#ibcon#about to read 5, iclass 29, count 2 2006.175.07:36:31.83#ibcon#read 5, iclass 29, count 2 2006.175.07:36:31.83#ibcon#about to read 6, iclass 29, count 2 2006.175.07:36:31.83#ibcon#read 6, iclass 29, count 2 2006.175.07:36:31.83#ibcon#end of sib2, iclass 29, count 2 2006.175.07:36:31.83#ibcon#*after write, iclass 29, count 2 2006.175.07:36:31.83#ibcon#*before return 0, iclass 29, count 2 2006.175.07:36:31.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:31.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:36:31.83#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.175.07:36:31.83#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:31.83#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:31.95#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:31.95#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:31.95#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:36:31.95#ibcon#first serial, iclass 29, count 0 2006.175.07:36:31.95#ibcon#enter sib2, iclass 29, count 0 2006.175.07:36:31.95#ibcon#flushed, iclass 29, count 0 2006.175.07:36:31.95#ibcon#about to write, iclass 29, count 0 2006.175.07:36:31.95#ibcon#wrote, iclass 29, count 0 2006.175.07:36:31.95#ibcon#about to read 3, iclass 29, count 0 2006.175.07:36:31.97#ibcon#read 3, iclass 29, count 0 2006.175.07:36:31.97#ibcon#about to read 4, iclass 29, count 0 2006.175.07:36:31.97#ibcon#read 4, iclass 29, count 0 2006.175.07:36:31.97#ibcon#about to read 5, iclass 29, count 0 2006.175.07:36:31.97#ibcon#read 5, iclass 29, count 0 2006.175.07:36:31.97#ibcon#about to read 6, iclass 29, count 0 2006.175.07:36:31.97#ibcon#read 6, iclass 29, count 0 2006.175.07:36:31.97#ibcon#end of sib2, iclass 29, count 0 2006.175.07:36:31.97#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:36:31.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:36:31.97#ibcon#[27=USB\r\n] 2006.175.07:36:31.97#ibcon#*before write, iclass 29, count 0 2006.175.07:36:31.97#ibcon#enter sib2, iclass 29, count 0 2006.175.07:36:31.97#ibcon#flushed, iclass 29, count 0 2006.175.07:36:31.97#ibcon#about to write, iclass 29, count 0 2006.175.07:36:31.97#ibcon#wrote, iclass 29, count 0 2006.175.07:36:31.97#ibcon#about to read 3, iclass 29, count 0 2006.175.07:36:32.00#ibcon#read 3, iclass 29, count 0 2006.175.07:36:32.00#ibcon#about to read 4, iclass 29, count 0 2006.175.07:36:32.00#ibcon#read 4, iclass 29, count 0 2006.175.07:36:32.00#ibcon#about to read 5, iclass 29, count 0 2006.175.07:36:32.00#ibcon#read 5, iclass 29, count 0 2006.175.07:36:32.00#ibcon#about to read 6, iclass 29, count 0 2006.175.07:36:32.00#ibcon#read 6, iclass 29, count 0 2006.175.07:36:32.00#ibcon#end of sib2, iclass 29, count 0 2006.175.07:36:32.00#ibcon#*after write, iclass 29, count 0 2006.175.07:36:32.00#ibcon#*before return 0, iclass 29, count 0 2006.175.07:36:32.00#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:32.00#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:36:32.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:36:32.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:36:32.00$vc4f8/vblo=5,744.99 2006.175.07:36:32.00#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.07:36:32.00#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.07:36:32.00#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:32.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:32.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:32.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:32.00#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:36:32.00#ibcon#first serial, iclass 31, count 0 2006.175.07:36:32.00#ibcon#enter sib2, iclass 31, count 0 2006.175.07:36:32.00#ibcon#flushed, iclass 31, count 0 2006.175.07:36:32.00#ibcon#about to write, iclass 31, count 0 2006.175.07:36:32.00#ibcon#wrote, iclass 31, count 0 2006.175.07:36:32.00#ibcon#about to read 3, iclass 31, count 0 2006.175.07:36:32.02#ibcon#read 3, iclass 31, count 0 2006.175.07:36:32.02#ibcon#about to read 4, iclass 31, count 0 2006.175.07:36:32.02#ibcon#read 4, iclass 31, count 0 2006.175.07:36:32.02#ibcon#about to read 5, iclass 31, count 0 2006.175.07:36:32.02#ibcon#read 5, iclass 31, count 0 2006.175.07:36:32.02#ibcon#about to read 6, iclass 31, count 0 2006.175.07:36:32.02#ibcon#read 6, iclass 31, count 0 2006.175.07:36:32.02#ibcon#end of sib2, iclass 31, count 0 2006.175.07:36:32.02#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:36:32.02#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:36:32.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:36:32.02#ibcon#*before write, iclass 31, count 0 2006.175.07:36:32.02#ibcon#enter sib2, iclass 31, count 0 2006.175.07:36:32.02#ibcon#flushed, iclass 31, count 0 2006.175.07:36:32.02#ibcon#about to write, iclass 31, count 0 2006.175.07:36:32.02#ibcon#wrote, iclass 31, count 0 2006.175.07:36:32.02#ibcon#about to read 3, iclass 31, count 0 2006.175.07:36:32.06#ibcon#read 3, iclass 31, count 0 2006.175.07:36:32.06#ibcon#about to read 4, iclass 31, count 0 2006.175.07:36:32.06#ibcon#read 4, iclass 31, count 0 2006.175.07:36:32.06#ibcon#about to read 5, iclass 31, count 0 2006.175.07:36:32.06#ibcon#read 5, iclass 31, count 0 2006.175.07:36:32.06#ibcon#about to read 6, iclass 31, count 0 2006.175.07:36:32.06#ibcon#read 6, iclass 31, count 0 2006.175.07:36:32.06#ibcon#end of sib2, iclass 31, count 0 2006.175.07:36:32.06#ibcon#*after write, iclass 31, count 0 2006.175.07:36:32.06#ibcon#*before return 0, iclass 31, count 0 2006.175.07:36:32.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:32.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:36:32.06#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:36:32.06#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:36:32.06$vc4f8/vb=5,4 2006.175.07:36:32.06#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.07:36:32.06#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.07:36:32.06#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:32.06#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:32.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:32.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:32.12#ibcon#enter wrdev, iclass 33, count 2 2006.175.07:36:32.12#ibcon#first serial, iclass 33, count 2 2006.175.07:36:32.12#ibcon#enter sib2, iclass 33, count 2 2006.175.07:36:32.12#ibcon#flushed, iclass 33, count 2 2006.175.07:36:32.12#ibcon#about to write, iclass 33, count 2 2006.175.07:36:32.12#ibcon#wrote, iclass 33, count 2 2006.175.07:36:32.12#ibcon#about to read 3, iclass 33, count 2 2006.175.07:36:32.14#ibcon#read 3, iclass 33, count 2 2006.175.07:36:32.14#ibcon#about to read 4, iclass 33, count 2 2006.175.07:36:32.14#ibcon#read 4, iclass 33, count 2 2006.175.07:36:32.14#ibcon#about to read 5, iclass 33, count 2 2006.175.07:36:32.14#ibcon#read 5, iclass 33, count 2 2006.175.07:36:32.14#ibcon#about to read 6, iclass 33, count 2 2006.175.07:36:32.14#ibcon#read 6, iclass 33, count 2 2006.175.07:36:32.14#ibcon#end of sib2, iclass 33, count 2 2006.175.07:36:32.14#ibcon#*mode == 0, iclass 33, count 2 2006.175.07:36:32.14#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.07:36:32.14#ibcon#[27=AT05-04\r\n] 2006.175.07:36:32.14#ibcon#*before write, iclass 33, count 2 2006.175.07:36:32.14#ibcon#enter sib2, iclass 33, count 2 2006.175.07:36:32.14#ibcon#flushed, iclass 33, count 2 2006.175.07:36:32.14#ibcon#about to write, iclass 33, count 2 2006.175.07:36:32.14#ibcon#wrote, iclass 33, count 2 2006.175.07:36:32.14#ibcon#about to read 3, iclass 33, count 2 2006.175.07:36:32.17#ibcon#read 3, iclass 33, count 2 2006.175.07:36:32.17#ibcon#about to read 4, iclass 33, count 2 2006.175.07:36:32.17#ibcon#read 4, iclass 33, count 2 2006.175.07:36:32.17#ibcon#about to read 5, iclass 33, count 2 2006.175.07:36:32.17#ibcon#read 5, iclass 33, count 2 2006.175.07:36:32.17#ibcon#about to read 6, iclass 33, count 2 2006.175.07:36:32.17#ibcon#read 6, iclass 33, count 2 2006.175.07:36:32.17#ibcon#end of sib2, iclass 33, count 2 2006.175.07:36:32.17#ibcon#*after write, iclass 33, count 2 2006.175.07:36:32.17#ibcon#*before return 0, iclass 33, count 2 2006.175.07:36:32.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:32.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:36:32.17#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.07:36:32.17#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:32.17#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:32.29#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:32.29#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:32.29#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:36:32.29#ibcon#first serial, iclass 33, count 0 2006.175.07:36:32.29#ibcon#enter sib2, iclass 33, count 0 2006.175.07:36:32.29#ibcon#flushed, iclass 33, count 0 2006.175.07:36:32.29#ibcon#about to write, iclass 33, count 0 2006.175.07:36:32.29#ibcon#wrote, iclass 33, count 0 2006.175.07:36:32.29#ibcon#about to read 3, iclass 33, count 0 2006.175.07:36:32.31#ibcon#read 3, iclass 33, count 0 2006.175.07:36:32.31#ibcon#about to read 4, iclass 33, count 0 2006.175.07:36:32.31#ibcon#read 4, iclass 33, count 0 2006.175.07:36:32.31#ibcon#about to read 5, iclass 33, count 0 2006.175.07:36:32.31#ibcon#read 5, iclass 33, count 0 2006.175.07:36:32.31#ibcon#about to read 6, iclass 33, count 0 2006.175.07:36:32.31#ibcon#read 6, iclass 33, count 0 2006.175.07:36:32.31#ibcon#end of sib2, iclass 33, count 0 2006.175.07:36:32.31#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:36:32.31#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:36:32.31#ibcon#[27=USB\r\n] 2006.175.07:36:32.31#ibcon#*before write, iclass 33, count 0 2006.175.07:36:32.31#ibcon#enter sib2, iclass 33, count 0 2006.175.07:36:32.31#ibcon#flushed, iclass 33, count 0 2006.175.07:36:32.31#ibcon#about to write, iclass 33, count 0 2006.175.07:36:32.31#ibcon#wrote, iclass 33, count 0 2006.175.07:36:32.31#ibcon#about to read 3, iclass 33, count 0 2006.175.07:36:32.34#ibcon#read 3, iclass 33, count 0 2006.175.07:36:32.34#ibcon#about to read 4, iclass 33, count 0 2006.175.07:36:32.34#ibcon#read 4, iclass 33, count 0 2006.175.07:36:32.34#ibcon#about to read 5, iclass 33, count 0 2006.175.07:36:32.34#ibcon#read 5, iclass 33, count 0 2006.175.07:36:32.34#ibcon#about to read 6, iclass 33, count 0 2006.175.07:36:32.34#ibcon#read 6, iclass 33, count 0 2006.175.07:36:32.34#ibcon#end of sib2, iclass 33, count 0 2006.175.07:36:32.34#ibcon#*after write, iclass 33, count 0 2006.175.07:36:32.34#ibcon#*before return 0, iclass 33, count 0 2006.175.07:36:32.34#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:32.34#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:36:32.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:36:32.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:36:32.34$vc4f8/vblo=6,752.99 2006.175.07:36:32.34#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.07:36:32.34#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.07:36:32.34#ibcon#ireg 17 cls_cnt 0 2006.175.07:36:32.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:32.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:32.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:32.34#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:36:32.34#ibcon#first serial, iclass 35, count 0 2006.175.07:36:32.34#ibcon#enter sib2, iclass 35, count 0 2006.175.07:36:32.34#ibcon#flushed, iclass 35, count 0 2006.175.07:36:32.34#ibcon#about to write, iclass 35, count 0 2006.175.07:36:32.34#ibcon#wrote, iclass 35, count 0 2006.175.07:36:32.34#ibcon#about to read 3, iclass 35, count 0 2006.175.07:36:32.36#ibcon#read 3, iclass 35, count 0 2006.175.07:36:32.36#ibcon#about to read 4, iclass 35, count 0 2006.175.07:36:32.36#ibcon#read 4, iclass 35, count 0 2006.175.07:36:32.36#ibcon#about to read 5, iclass 35, count 0 2006.175.07:36:32.36#ibcon#read 5, iclass 35, count 0 2006.175.07:36:32.36#ibcon#about to read 6, iclass 35, count 0 2006.175.07:36:32.36#ibcon#read 6, iclass 35, count 0 2006.175.07:36:32.36#ibcon#end of sib2, iclass 35, count 0 2006.175.07:36:32.36#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:36:32.36#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:36:32.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:36:32.36#ibcon#*before write, iclass 35, count 0 2006.175.07:36:32.36#ibcon#enter sib2, iclass 35, count 0 2006.175.07:36:32.36#ibcon#flushed, iclass 35, count 0 2006.175.07:36:32.36#ibcon#about to write, iclass 35, count 0 2006.175.07:36:32.36#ibcon#wrote, iclass 35, count 0 2006.175.07:36:32.36#ibcon#about to read 3, iclass 35, count 0 2006.175.07:36:32.40#ibcon#read 3, iclass 35, count 0 2006.175.07:36:32.40#ibcon#about to read 4, iclass 35, count 0 2006.175.07:36:32.40#ibcon#read 4, iclass 35, count 0 2006.175.07:36:32.40#ibcon#about to read 5, iclass 35, count 0 2006.175.07:36:32.40#ibcon#read 5, iclass 35, count 0 2006.175.07:36:32.40#ibcon#about to read 6, iclass 35, count 0 2006.175.07:36:32.40#ibcon#read 6, iclass 35, count 0 2006.175.07:36:32.40#ibcon#end of sib2, iclass 35, count 0 2006.175.07:36:32.40#ibcon#*after write, iclass 35, count 0 2006.175.07:36:32.40#ibcon#*before return 0, iclass 35, count 0 2006.175.07:36:32.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:32.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:36:32.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:36:32.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:36:32.40$vc4f8/vb=6,4 2006.175.07:36:32.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.07:36:32.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.07:36:32.40#ibcon#ireg 11 cls_cnt 2 2006.175.07:36:32.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:32.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:32.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:32.46#ibcon#enter wrdev, iclass 37, count 2 2006.175.07:36:32.46#ibcon#first serial, iclass 37, count 2 2006.175.07:36:32.46#ibcon#enter sib2, iclass 37, count 2 2006.175.07:36:32.46#ibcon#flushed, iclass 37, count 2 2006.175.07:36:32.46#ibcon#about to write, iclass 37, count 2 2006.175.07:36:32.46#ibcon#wrote, iclass 37, count 2 2006.175.07:36:32.46#ibcon#about to read 3, iclass 37, count 2 2006.175.07:36:32.48#ibcon#read 3, iclass 37, count 2 2006.175.07:36:32.48#ibcon#about to read 4, iclass 37, count 2 2006.175.07:36:32.48#ibcon#read 4, iclass 37, count 2 2006.175.07:36:32.48#ibcon#about to read 5, iclass 37, count 2 2006.175.07:36:32.48#ibcon#read 5, iclass 37, count 2 2006.175.07:36:32.48#ibcon#about to read 6, iclass 37, count 2 2006.175.07:36:32.48#ibcon#read 6, iclass 37, count 2 2006.175.07:36:32.48#ibcon#end of sib2, iclass 37, count 2 2006.175.07:36:32.48#ibcon#*mode == 0, iclass 37, count 2 2006.175.07:36:32.48#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.07:36:32.48#ibcon#[27=AT06-04\r\n] 2006.175.07:36:32.48#ibcon#*before write, iclass 37, count 2 2006.175.07:36:32.48#ibcon#enter sib2, iclass 37, count 2 2006.175.07:36:32.48#ibcon#flushed, iclass 37, count 2 2006.175.07:36:32.48#ibcon#about to write, iclass 37, count 2 2006.175.07:36:32.48#ibcon#wrote, iclass 37, count 2 2006.175.07:36:32.48#ibcon#about to read 3, iclass 37, count 2 2006.175.07:36:32.51#ibcon#read 3, iclass 37, count 2 2006.175.07:36:32.51#ibcon#about to read 4, iclass 37, count 2 2006.175.07:36:32.51#ibcon#read 4, iclass 37, count 2 2006.175.07:36:32.51#ibcon#about to read 5, iclass 37, count 2 2006.175.07:36:32.51#ibcon#read 5, iclass 37, count 2 2006.175.07:36:32.51#ibcon#about to read 6, iclass 37, count 2 2006.175.07:36:32.51#ibcon#read 6, iclass 37, count 2 2006.175.07:36:32.51#ibcon#end of sib2, iclass 37, count 2 2006.175.07:36:32.51#ibcon#*after write, iclass 37, count 2 2006.175.07:36:32.51#ibcon#*before return 0, iclass 37, count 2 2006.175.07:36:32.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:32.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:36:32.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.07:36:32.51#ibcon#ireg 7 cls_cnt 0 2006.175.07:36:32.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:32.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:32.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:32.63#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:36:32.63#ibcon#first serial, iclass 37, count 0 2006.175.07:36:32.63#ibcon#enter sib2, iclass 37, count 0 2006.175.07:36:32.63#ibcon#flushed, iclass 37, count 0 2006.175.07:36:32.63#ibcon#about to write, iclass 37, count 0 2006.175.07:36:32.63#ibcon#wrote, iclass 37, count 0 2006.175.07:36:32.63#ibcon#about to read 3, iclass 37, count 0 2006.175.07:36:32.65#ibcon#read 3, iclass 37, count 0 2006.175.07:36:32.65#ibcon#about to read 4, iclass 37, count 0 2006.175.07:36:32.65#ibcon#read 4, iclass 37, count 0 2006.175.07:36:32.65#ibcon#about to read 5, iclass 37, count 0 2006.175.07:36:32.65#ibcon#read 5, iclass 37, count 0 2006.175.07:36:32.65#ibcon#about to read 6, iclass 37, count 0 2006.175.07:36:32.65#ibcon#read 6, iclass 37, count 0 2006.175.07:36:32.65#ibcon#end of sib2, iclass 37, count 0 2006.175.07:36:32.65#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:36:32.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:36:32.65#ibcon#[27=USB\r\n] 2006.175.07:36:32.65#ibcon#*before write, iclass 37, count 0 2006.175.07:36:32.65#ibcon#enter sib2, iclass 37, count 0 2006.175.07:36:32.65#ibcon#flushed, iclass 37, count 0 2006.175.07:36:32.65#ibcon#about to write, iclass 37, count 0 2006.175.07:36:32.65#ibcon#wrote, iclass 37, count 0 2006.175.07:36:32.65#ibcon#about to read 3, iclass 37, count 0 2006.175.07:36:32.68#ibcon#read 3, iclass 37, count 0 2006.175.07:36:32.68#ibcon#about to read 4, iclass 37, count 0 2006.175.07:36:32.68#ibcon#read 4, iclass 37, count 0 2006.175.07:36:32.68#ibcon#about to read 5, iclass 37, count 0 2006.175.07:36:32.68#ibcon#read 5, iclass 37, count 0 2006.175.07:36:32.68#ibcon#about to read 6, iclass 37, count 0 2006.175.07:36:32.68#ibcon#read 6, iclass 37, count 0 2006.175.07:36:32.68#ibcon#end of sib2, iclass 37, count 0 2006.175.07:36:32.68#ibcon#*after write, iclass 37, count 0 2006.175.07:36:32.68#ibcon#*before return 0, iclass 37, count 0 2006.175.07:36:32.68#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:32.68#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:36:32.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:36:32.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:36:32.68$vc4f8/vabw=wide 2006.175.07:36:32.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.07:36:32.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.07:36:32.68#ibcon#ireg 8 cls_cnt 0 2006.175.07:36:32.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:32.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:32.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:32.68#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:36:32.68#ibcon#first serial, iclass 39, count 0 2006.175.07:36:32.68#ibcon#enter sib2, iclass 39, count 0 2006.175.07:36:32.68#ibcon#flushed, iclass 39, count 0 2006.175.07:36:32.68#ibcon#about to write, iclass 39, count 0 2006.175.07:36:32.68#ibcon#wrote, iclass 39, count 0 2006.175.07:36:32.68#ibcon#about to read 3, iclass 39, count 0 2006.175.07:36:32.70#ibcon#read 3, iclass 39, count 0 2006.175.07:36:32.70#ibcon#about to read 4, iclass 39, count 0 2006.175.07:36:32.70#ibcon#read 4, iclass 39, count 0 2006.175.07:36:32.70#ibcon#about to read 5, iclass 39, count 0 2006.175.07:36:32.70#ibcon#read 5, iclass 39, count 0 2006.175.07:36:32.70#ibcon#about to read 6, iclass 39, count 0 2006.175.07:36:32.70#ibcon#read 6, iclass 39, count 0 2006.175.07:36:32.70#ibcon#end of sib2, iclass 39, count 0 2006.175.07:36:32.70#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:36:32.70#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:36:32.70#ibcon#[25=BW32\r\n] 2006.175.07:36:32.70#ibcon#*before write, iclass 39, count 0 2006.175.07:36:32.70#ibcon#enter sib2, iclass 39, count 0 2006.175.07:36:32.70#ibcon#flushed, iclass 39, count 0 2006.175.07:36:32.70#ibcon#about to write, iclass 39, count 0 2006.175.07:36:32.70#ibcon#wrote, iclass 39, count 0 2006.175.07:36:32.70#ibcon#about to read 3, iclass 39, count 0 2006.175.07:36:32.73#ibcon#read 3, iclass 39, count 0 2006.175.07:36:32.73#ibcon#about to read 4, iclass 39, count 0 2006.175.07:36:32.73#ibcon#read 4, iclass 39, count 0 2006.175.07:36:32.73#ibcon#about to read 5, iclass 39, count 0 2006.175.07:36:32.73#ibcon#read 5, iclass 39, count 0 2006.175.07:36:32.73#ibcon#about to read 6, iclass 39, count 0 2006.175.07:36:32.73#ibcon#read 6, iclass 39, count 0 2006.175.07:36:32.73#ibcon#end of sib2, iclass 39, count 0 2006.175.07:36:32.73#ibcon#*after write, iclass 39, count 0 2006.175.07:36:32.73#ibcon#*before return 0, iclass 39, count 0 2006.175.07:36:32.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:32.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:36:32.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:36:32.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:36:32.73$vc4f8/vbbw=wide 2006.175.07:36:32.73#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.07:36:32.73#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.07:36:32.73#ibcon#ireg 8 cls_cnt 0 2006.175.07:36:32.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:36:32.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:36:32.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:36:32.80#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:36:32.80#ibcon#first serial, iclass 3, count 0 2006.175.07:36:32.80#ibcon#enter sib2, iclass 3, count 0 2006.175.07:36:32.80#ibcon#flushed, iclass 3, count 0 2006.175.07:36:32.80#ibcon#about to write, iclass 3, count 0 2006.175.07:36:32.80#ibcon#wrote, iclass 3, count 0 2006.175.07:36:32.80#ibcon#about to read 3, iclass 3, count 0 2006.175.07:36:32.82#ibcon#read 3, iclass 3, count 0 2006.175.07:36:32.82#ibcon#about to read 4, iclass 3, count 0 2006.175.07:36:32.82#ibcon#read 4, iclass 3, count 0 2006.175.07:36:32.82#ibcon#about to read 5, iclass 3, count 0 2006.175.07:36:32.82#ibcon#read 5, iclass 3, count 0 2006.175.07:36:32.82#ibcon#about to read 6, iclass 3, count 0 2006.175.07:36:32.82#ibcon#read 6, iclass 3, count 0 2006.175.07:36:32.82#ibcon#end of sib2, iclass 3, count 0 2006.175.07:36:32.82#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:36:32.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:36:32.82#ibcon#[27=BW32\r\n] 2006.175.07:36:32.82#ibcon#*before write, iclass 3, count 0 2006.175.07:36:32.82#ibcon#enter sib2, iclass 3, count 0 2006.175.07:36:32.82#ibcon#flushed, iclass 3, count 0 2006.175.07:36:32.82#ibcon#about to write, iclass 3, count 0 2006.175.07:36:32.82#ibcon#wrote, iclass 3, count 0 2006.175.07:36:32.82#ibcon#about to read 3, iclass 3, count 0 2006.175.07:36:32.85#ibcon#read 3, iclass 3, count 0 2006.175.07:36:32.85#ibcon#about to read 4, iclass 3, count 0 2006.175.07:36:32.85#ibcon#read 4, iclass 3, count 0 2006.175.07:36:32.85#ibcon#about to read 5, iclass 3, count 0 2006.175.07:36:32.85#ibcon#read 5, iclass 3, count 0 2006.175.07:36:32.85#ibcon#about to read 6, iclass 3, count 0 2006.175.07:36:32.85#ibcon#read 6, iclass 3, count 0 2006.175.07:36:32.85#ibcon#end of sib2, iclass 3, count 0 2006.175.07:36:32.85#ibcon#*after write, iclass 3, count 0 2006.175.07:36:32.85#ibcon#*before return 0, iclass 3, count 0 2006.175.07:36:32.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:36:32.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:36:32.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:36:32.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:36:32.85$4f8m12a/ifd4f 2006.175.07:36:32.85$ifd4f/lo= 2006.175.07:36:32.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:36:32.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:36:32.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:36:32.85$ifd4f/patch= 2006.175.07:36:32.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:36:32.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:36:32.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:36:32.85$4f8m12a/"form=m,16.000,1:2 2006.175.07:36:32.85$4f8m12a/"tpicd 2006.175.07:36:32.85$4f8m12a/echo=off 2006.175.07:36:32.85$4f8m12a/xlog=off 2006.175.07:36:32.85:!2006.175.07:37:00 2006.175.07:36:47.14#trakl#Source acquired 2006.175.07:36:48.14#flagr#flagr/antenna,acquired 2006.175.07:37:00.00:preob 2006.175.07:37:01.14/onsource/TRACKING 2006.175.07:37:01.14:!2006.175.07:37:10 2006.175.07:37:10.00:data_valid=on 2006.175.07:37:10.00:midob 2006.175.07:37:10.14/onsource/TRACKING 2006.175.07:37:10.14/wx/25.99,1007.5,69 2006.175.07:37:10.37/cable/+6.4778E-03 2006.175.07:37:11.46/va/01,08,usb,yes,29,31 2006.175.07:37:11.46/va/02,07,usb,yes,30,31 2006.175.07:37:11.46/va/03,06,usb,yes,31,31 2006.175.07:37:11.46/va/04,07,usb,yes,30,33 2006.175.07:37:11.46/va/05,07,usb,yes,31,32 2006.175.07:37:11.46/va/06,06,usb,yes,30,29 2006.175.07:37:11.46/va/07,06,usb,yes,30,30 2006.175.07:37:11.46/va/08,06,usb,yes,32,32 2006.175.07:37:11.69/valo/01,532.99,yes,locked 2006.175.07:37:11.69/valo/02,572.99,yes,locked 2006.175.07:37:11.69/valo/03,672.99,yes,locked 2006.175.07:37:11.69/valo/04,832.99,yes,locked 2006.175.07:37:11.69/valo/05,652.99,yes,locked 2006.175.07:37:11.69/valo/06,772.99,yes,locked 2006.175.07:37:11.69/valo/07,832.99,yes,locked 2006.175.07:37:11.69/valo/08,852.99,yes,locked 2006.175.07:37:12.78/vb/01,04,usb,yes,30,28 2006.175.07:37:12.78/vb/02,04,usb,yes,31,33 2006.175.07:37:12.78/vb/03,04,usb,yes,28,31 2006.175.07:37:12.78/vb/04,04,usb,yes,29,29 2006.175.07:37:12.78/vb/05,04,usb,yes,27,31 2006.175.07:37:12.78/vb/06,04,usb,yes,28,31 2006.175.07:37:12.78/vb/07,04,usb,yes,30,30 2006.175.07:37:12.78/vb/08,04,usb,yes,28,31 2006.175.07:37:13.01/vblo/01,632.99,yes,locked 2006.175.07:37:13.01/vblo/02,640.99,yes,locked 2006.175.07:37:13.01/vblo/03,656.99,yes,locked 2006.175.07:37:13.01/vblo/04,712.99,yes,locked 2006.175.07:37:13.01/vblo/05,744.99,yes,locked 2006.175.07:37:13.01/vblo/06,752.99,yes,locked 2006.175.07:37:13.01/vblo/07,734.99,yes,locked 2006.175.07:37:13.01/vblo/08,744.99,yes,locked 2006.175.07:37:13.16/vabw/8 2006.175.07:37:13.31/vbbw/8 2006.175.07:37:13.40/xfe/off,on,15.2 2006.175.07:37:13.78/ifatt/23,28,28,28 2006.175.07:37:14.07/fmout-gps/S +3.76E-07 2006.175.07:37:14.15:!2006.175.07:38:10 2006.175.07:38:10.00:data_valid=off 2006.175.07:38:10.00:postob 2006.175.07:38:10.12/cable/+6.4775E-03 2006.175.07:38:10.12/wx/25.98,1007.5,70 2006.175.07:38:11.07/fmout-gps/S +3.78E-07 2006.175.07:38:11.07:scan_name=175-0739,k06175,60 2006.175.07:38:11.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.175.07:38:11.14#flagr#flagr/antenna,new-source 2006.175.07:38:12.14:checkk5 2006.175.07:38:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:38:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:38:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:38:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:38:14.03/chk_obsdata//k5ts1/T1750737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:38:14.40/chk_obsdata//k5ts2/T1750737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:38:14.77/chk_obsdata//k5ts3/T1750737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:38:15.15/chk_obsdata//k5ts4/T1750737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:38:15.84/k5log//k5ts1_log_newline 2006.175.07:38:16.53/k5log//k5ts2_log_newline 2006.175.07:38:20.22/k5log//k5ts3_log_newline 2006.175.07:38:20.93/k5log//k5ts4_log_newline 2006.175.07:38:20.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:38:20.95:4f8m12a=1 2006.175.07:38:20.95$4f8m12a/echo=on 2006.175.07:38:20.95$4f8m12a/pcalon 2006.175.07:38:20.95$pcalon/"no phase cal control is implemented here 2006.175.07:38:20.95$4f8m12a/"tpicd=stop 2006.175.07:38:20.95$4f8m12a/vc4f8 2006.175.07:38:20.95$vc4f8/valo=1,532.99 2006.175.07:38:20.95#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.07:38:20.95#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.07:38:20.95#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:20.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:20.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:20.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:20.95#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:38:20.95#ibcon#first serial, iclass 16, count 0 2006.175.07:38:20.95#ibcon#enter sib2, iclass 16, count 0 2006.175.07:38:20.95#ibcon#flushed, iclass 16, count 0 2006.175.07:38:20.95#ibcon#about to write, iclass 16, count 0 2006.175.07:38:20.95#ibcon#wrote, iclass 16, count 0 2006.175.07:38:20.95#ibcon#about to read 3, iclass 16, count 0 2006.175.07:38:20.97#ibcon#read 3, iclass 16, count 0 2006.175.07:38:20.97#ibcon#about to read 4, iclass 16, count 0 2006.175.07:38:20.97#ibcon#read 4, iclass 16, count 0 2006.175.07:38:20.97#ibcon#about to read 5, iclass 16, count 0 2006.175.07:38:20.97#ibcon#read 5, iclass 16, count 0 2006.175.07:38:20.97#ibcon#about to read 6, iclass 16, count 0 2006.175.07:38:20.97#ibcon#read 6, iclass 16, count 0 2006.175.07:38:20.97#ibcon#end of sib2, iclass 16, count 0 2006.175.07:38:20.97#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:38:20.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:38:20.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:38:20.97#ibcon#*before write, iclass 16, count 0 2006.175.07:38:20.97#ibcon#enter sib2, iclass 16, count 0 2006.175.07:38:20.97#ibcon#flushed, iclass 16, count 0 2006.175.07:38:20.97#ibcon#about to write, iclass 16, count 0 2006.175.07:38:20.97#ibcon#wrote, iclass 16, count 0 2006.175.07:38:20.97#ibcon#about to read 3, iclass 16, count 0 2006.175.07:38:21.02#ibcon#read 3, iclass 16, count 0 2006.175.07:38:21.02#ibcon#about to read 4, iclass 16, count 0 2006.175.07:38:21.02#ibcon#read 4, iclass 16, count 0 2006.175.07:38:21.02#ibcon#about to read 5, iclass 16, count 0 2006.175.07:38:21.02#ibcon#read 5, iclass 16, count 0 2006.175.07:38:21.02#ibcon#about to read 6, iclass 16, count 0 2006.175.07:38:21.02#ibcon#read 6, iclass 16, count 0 2006.175.07:38:21.02#ibcon#end of sib2, iclass 16, count 0 2006.175.07:38:21.02#ibcon#*after write, iclass 16, count 0 2006.175.07:38:21.02#ibcon#*before return 0, iclass 16, count 0 2006.175.07:38:21.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:21.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:21.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:38:21.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:38:21.02$vc4f8/va=1,8 2006.175.07:38:21.02#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.07:38:21.02#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.07:38:21.02#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:21.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:21.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:21.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:21.02#ibcon#enter wrdev, iclass 18, count 2 2006.175.07:38:21.02#ibcon#first serial, iclass 18, count 2 2006.175.07:38:21.02#ibcon#enter sib2, iclass 18, count 2 2006.175.07:38:21.02#ibcon#flushed, iclass 18, count 2 2006.175.07:38:21.02#ibcon#about to write, iclass 18, count 2 2006.175.07:38:21.02#ibcon#wrote, iclass 18, count 2 2006.175.07:38:21.02#ibcon#about to read 3, iclass 18, count 2 2006.175.07:38:21.04#ibcon#read 3, iclass 18, count 2 2006.175.07:38:21.04#ibcon#about to read 4, iclass 18, count 2 2006.175.07:38:21.04#ibcon#read 4, iclass 18, count 2 2006.175.07:38:21.04#ibcon#about to read 5, iclass 18, count 2 2006.175.07:38:21.04#ibcon#read 5, iclass 18, count 2 2006.175.07:38:21.04#ibcon#about to read 6, iclass 18, count 2 2006.175.07:38:21.04#ibcon#read 6, iclass 18, count 2 2006.175.07:38:21.04#ibcon#end of sib2, iclass 18, count 2 2006.175.07:38:21.04#ibcon#*mode == 0, iclass 18, count 2 2006.175.07:38:21.04#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.07:38:21.04#ibcon#[25=AT01-08\r\n] 2006.175.07:38:21.04#ibcon#*before write, iclass 18, count 2 2006.175.07:38:21.04#ibcon#enter sib2, iclass 18, count 2 2006.175.07:38:21.04#ibcon#flushed, iclass 18, count 2 2006.175.07:38:21.04#ibcon#about to write, iclass 18, count 2 2006.175.07:38:21.04#ibcon#wrote, iclass 18, count 2 2006.175.07:38:21.04#ibcon#about to read 3, iclass 18, count 2 2006.175.07:38:21.07#ibcon#read 3, iclass 18, count 2 2006.175.07:38:21.07#ibcon#about to read 4, iclass 18, count 2 2006.175.07:38:21.07#ibcon#read 4, iclass 18, count 2 2006.175.07:38:21.07#ibcon#about to read 5, iclass 18, count 2 2006.175.07:38:21.07#ibcon#read 5, iclass 18, count 2 2006.175.07:38:21.07#ibcon#about to read 6, iclass 18, count 2 2006.175.07:38:21.07#ibcon#read 6, iclass 18, count 2 2006.175.07:38:21.07#ibcon#end of sib2, iclass 18, count 2 2006.175.07:38:21.07#ibcon#*after write, iclass 18, count 2 2006.175.07:38:21.07#ibcon#*before return 0, iclass 18, count 2 2006.175.07:38:21.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:21.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:21.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.07:38:21.07#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:21.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:21.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:21.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:21.19#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:38:21.19#ibcon#first serial, iclass 18, count 0 2006.175.07:38:21.19#ibcon#enter sib2, iclass 18, count 0 2006.175.07:38:21.19#ibcon#flushed, iclass 18, count 0 2006.175.07:38:21.19#ibcon#about to write, iclass 18, count 0 2006.175.07:38:21.19#ibcon#wrote, iclass 18, count 0 2006.175.07:38:21.19#ibcon#about to read 3, iclass 18, count 0 2006.175.07:38:21.21#ibcon#read 3, iclass 18, count 0 2006.175.07:38:21.21#ibcon#about to read 4, iclass 18, count 0 2006.175.07:38:21.21#ibcon#read 4, iclass 18, count 0 2006.175.07:38:21.21#ibcon#about to read 5, iclass 18, count 0 2006.175.07:38:21.21#ibcon#read 5, iclass 18, count 0 2006.175.07:38:21.21#ibcon#about to read 6, iclass 18, count 0 2006.175.07:38:21.21#ibcon#read 6, iclass 18, count 0 2006.175.07:38:21.21#ibcon#end of sib2, iclass 18, count 0 2006.175.07:38:21.21#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:38:21.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:38:21.21#ibcon#[25=USB\r\n] 2006.175.07:38:21.21#ibcon#*before write, iclass 18, count 0 2006.175.07:38:21.21#ibcon#enter sib2, iclass 18, count 0 2006.175.07:38:21.21#ibcon#flushed, iclass 18, count 0 2006.175.07:38:21.21#ibcon#about to write, iclass 18, count 0 2006.175.07:38:21.21#ibcon#wrote, iclass 18, count 0 2006.175.07:38:21.21#ibcon#about to read 3, iclass 18, count 0 2006.175.07:38:21.24#ibcon#read 3, iclass 18, count 0 2006.175.07:38:21.24#ibcon#about to read 4, iclass 18, count 0 2006.175.07:38:21.24#ibcon#read 4, iclass 18, count 0 2006.175.07:38:21.24#ibcon#about to read 5, iclass 18, count 0 2006.175.07:38:21.24#ibcon#read 5, iclass 18, count 0 2006.175.07:38:21.24#ibcon#about to read 6, iclass 18, count 0 2006.175.07:38:21.24#ibcon#read 6, iclass 18, count 0 2006.175.07:38:21.24#ibcon#end of sib2, iclass 18, count 0 2006.175.07:38:21.24#ibcon#*after write, iclass 18, count 0 2006.175.07:38:21.24#ibcon#*before return 0, iclass 18, count 0 2006.175.07:38:21.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:21.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:21.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:38:21.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:38:21.24$vc4f8/valo=2,572.99 2006.175.07:38:21.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.07:38:21.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.07:38:21.24#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:21.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:21.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:21.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:21.24#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:38:21.24#ibcon#first serial, iclass 20, count 0 2006.175.07:38:21.24#ibcon#enter sib2, iclass 20, count 0 2006.175.07:38:21.24#ibcon#flushed, iclass 20, count 0 2006.175.07:38:21.24#ibcon#about to write, iclass 20, count 0 2006.175.07:38:21.24#ibcon#wrote, iclass 20, count 0 2006.175.07:38:21.24#ibcon#about to read 3, iclass 20, count 0 2006.175.07:38:21.26#ibcon#read 3, iclass 20, count 0 2006.175.07:38:21.26#ibcon#about to read 4, iclass 20, count 0 2006.175.07:38:21.26#ibcon#read 4, iclass 20, count 0 2006.175.07:38:21.26#ibcon#about to read 5, iclass 20, count 0 2006.175.07:38:21.26#ibcon#read 5, iclass 20, count 0 2006.175.07:38:21.26#ibcon#about to read 6, iclass 20, count 0 2006.175.07:38:21.26#ibcon#read 6, iclass 20, count 0 2006.175.07:38:21.26#ibcon#end of sib2, iclass 20, count 0 2006.175.07:38:21.26#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:38:21.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:38:21.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:38:21.26#ibcon#*before write, iclass 20, count 0 2006.175.07:38:21.26#ibcon#enter sib2, iclass 20, count 0 2006.175.07:38:21.26#ibcon#flushed, iclass 20, count 0 2006.175.07:38:21.26#ibcon#about to write, iclass 20, count 0 2006.175.07:38:21.26#ibcon#wrote, iclass 20, count 0 2006.175.07:38:21.26#ibcon#about to read 3, iclass 20, count 0 2006.175.07:38:21.30#ibcon#read 3, iclass 20, count 0 2006.175.07:38:21.30#ibcon#about to read 4, iclass 20, count 0 2006.175.07:38:21.30#ibcon#read 4, iclass 20, count 0 2006.175.07:38:21.30#ibcon#about to read 5, iclass 20, count 0 2006.175.07:38:21.30#ibcon#read 5, iclass 20, count 0 2006.175.07:38:21.30#ibcon#about to read 6, iclass 20, count 0 2006.175.07:38:21.30#ibcon#read 6, iclass 20, count 0 2006.175.07:38:21.30#ibcon#end of sib2, iclass 20, count 0 2006.175.07:38:21.30#ibcon#*after write, iclass 20, count 0 2006.175.07:38:21.30#ibcon#*before return 0, iclass 20, count 0 2006.175.07:38:21.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:21.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:21.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:38:21.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:38:21.30$vc4f8/va=2,7 2006.175.07:38:21.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.07:38:21.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.07:38:21.30#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:21.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:21.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:21.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:21.36#ibcon#enter wrdev, iclass 22, count 2 2006.175.07:38:21.36#ibcon#first serial, iclass 22, count 2 2006.175.07:38:21.36#ibcon#enter sib2, iclass 22, count 2 2006.175.07:38:21.36#ibcon#flushed, iclass 22, count 2 2006.175.07:38:21.36#ibcon#about to write, iclass 22, count 2 2006.175.07:38:21.36#ibcon#wrote, iclass 22, count 2 2006.175.07:38:21.36#ibcon#about to read 3, iclass 22, count 2 2006.175.07:38:21.38#ibcon#read 3, iclass 22, count 2 2006.175.07:38:21.38#ibcon#about to read 4, iclass 22, count 2 2006.175.07:38:21.38#ibcon#read 4, iclass 22, count 2 2006.175.07:38:21.38#ibcon#about to read 5, iclass 22, count 2 2006.175.07:38:21.38#ibcon#read 5, iclass 22, count 2 2006.175.07:38:21.38#ibcon#about to read 6, iclass 22, count 2 2006.175.07:38:21.38#ibcon#read 6, iclass 22, count 2 2006.175.07:38:21.38#ibcon#end of sib2, iclass 22, count 2 2006.175.07:38:21.38#ibcon#*mode == 0, iclass 22, count 2 2006.175.07:38:21.38#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.07:38:21.38#ibcon#[25=AT02-07\r\n] 2006.175.07:38:21.38#ibcon#*before write, iclass 22, count 2 2006.175.07:38:21.38#ibcon#enter sib2, iclass 22, count 2 2006.175.07:38:21.38#ibcon#flushed, iclass 22, count 2 2006.175.07:38:21.38#ibcon#about to write, iclass 22, count 2 2006.175.07:38:21.38#ibcon#wrote, iclass 22, count 2 2006.175.07:38:21.38#ibcon#about to read 3, iclass 22, count 2 2006.175.07:38:21.41#ibcon#read 3, iclass 22, count 2 2006.175.07:38:21.41#ibcon#about to read 4, iclass 22, count 2 2006.175.07:38:21.41#ibcon#read 4, iclass 22, count 2 2006.175.07:38:21.41#ibcon#about to read 5, iclass 22, count 2 2006.175.07:38:21.41#ibcon#read 5, iclass 22, count 2 2006.175.07:38:21.41#ibcon#about to read 6, iclass 22, count 2 2006.175.07:38:21.41#ibcon#read 6, iclass 22, count 2 2006.175.07:38:21.41#ibcon#end of sib2, iclass 22, count 2 2006.175.07:38:21.41#ibcon#*after write, iclass 22, count 2 2006.175.07:38:21.41#ibcon#*before return 0, iclass 22, count 2 2006.175.07:38:21.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:21.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:21.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.07:38:21.41#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:21.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:21.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:21.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:21.53#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:38:21.53#ibcon#first serial, iclass 22, count 0 2006.175.07:38:21.53#ibcon#enter sib2, iclass 22, count 0 2006.175.07:38:21.53#ibcon#flushed, iclass 22, count 0 2006.175.07:38:21.53#ibcon#about to write, iclass 22, count 0 2006.175.07:38:21.53#ibcon#wrote, iclass 22, count 0 2006.175.07:38:21.53#ibcon#about to read 3, iclass 22, count 0 2006.175.07:38:21.55#ibcon#read 3, iclass 22, count 0 2006.175.07:38:21.55#ibcon#about to read 4, iclass 22, count 0 2006.175.07:38:21.55#ibcon#read 4, iclass 22, count 0 2006.175.07:38:21.55#ibcon#about to read 5, iclass 22, count 0 2006.175.07:38:21.55#ibcon#read 5, iclass 22, count 0 2006.175.07:38:21.55#ibcon#about to read 6, iclass 22, count 0 2006.175.07:38:21.55#ibcon#read 6, iclass 22, count 0 2006.175.07:38:21.55#ibcon#end of sib2, iclass 22, count 0 2006.175.07:38:21.55#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:38:21.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:38:21.55#ibcon#[25=USB\r\n] 2006.175.07:38:21.55#ibcon#*before write, iclass 22, count 0 2006.175.07:38:21.55#ibcon#enter sib2, iclass 22, count 0 2006.175.07:38:21.55#ibcon#flushed, iclass 22, count 0 2006.175.07:38:21.55#ibcon#about to write, iclass 22, count 0 2006.175.07:38:21.55#ibcon#wrote, iclass 22, count 0 2006.175.07:38:21.55#ibcon#about to read 3, iclass 22, count 0 2006.175.07:38:21.58#ibcon#read 3, iclass 22, count 0 2006.175.07:38:21.58#ibcon#about to read 4, iclass 22, count 0 2006.175.07:38:21.58#ibcon#read 4, iclass 22, count 0 2006.175.07:38:21.58#ibcon#about to read 5, iclass 22, count 0 2006.175.07:38:21.58#ibcon#read 5, iclass 22, count 0 2006.175.07:38:21.58#ibcon#about to read 6, iclass 22, count 0 2006.175.07:38:21.58#ibcon#read 6, iclass 22, count 0 2006.175.07:38:21.58#ibcon#end of sib2, iclass 22, count 0 2006.175.07:38:21.58#ibcon#*after write, iclass 22, count 0 2006.175.07:38:21.58#ibcon#*before return 0, iclass 22, count 0 2006.175.07:38:21.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:21.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:21.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:38:21.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:38:21.58$vc4f8/valo=3,672.99 2006.175.07:38:21.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.07:38:21.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.07:38:21.58#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:21.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:21.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:21.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:21.58#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:38:21.58#ibcon#first serial, iclass 24, count 0 2006.175.07:38:21.58#ibcon#enter sib2, iclass 24, count 0 2006.175.07:38:21.58#ibcon#flushed, iclass 24, count 0 2006.175.07:38:21.58#ibcon#about to write, iclass 24, count 0 2006.175.07:38:21.58#ibcon#wrote, iclass 24, count 0 2006.175.07:38:21.58#ibcon#about to read 3, iclass 24, count 0 2006.175.07:38:21.60#ibcon#read 3, iclass 24, count 0 2006.175.07:38:21.60#ibcon#about to read 4, iclass 24, count 0 2006.175.07:38:21.60#ibcon#read 4, iclass 24, count 0 2006.175.07:38:21.60#ibcon#about to read 5, iclass 24, count 0 2006.175.07:38:21.60#ibcon#read 5, iclass 24, count 0 2006.175.07:38:21.60#ibcon#about to read 6, iclass 24, count 0 2006.175.07:38:21.60#ibcon#read 6, iclass 24, count 0 2006.175.07:38:21.60#ibcon#end of sib2, iclass 24, count 0 2006.175.07:38:21.60#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:38:21.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:38:21.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:38:21.60#ibcon#*before write, iclass 24, count 0 2006.175.07:38:21.60#ibcon#enter sib2, iclass 24, count 0 2006.175.07:38:21.60#ibcon#flushed, iclass 24, count 0 2006.175.07:38:21.60#ibcon#about to write, iclass 24, count 0 2006.175.07:38:21.60#ibcon#wrote, iclass 24, count 0 2006.175.07:38:21.60#ibcon#about to read 3, iclass 24, count 0 2006.175.07:38:21.64#ibcon#read 3, iclass 24, count 0 2006.175.07:38:21.64#ibcon#about to read 4, iclass 24, count 0 2006.175.07:38:21.64#ibcon#read 4, iclass 24, count 0 2006.175.07:38:21.64#ibcon#about to read 5, iclass 24, count 0 2006.175.07:38:21.64#ibcon#read 5, iclass 24, count 0 2006.175.07:38:21.64#ibcon#about to read 6, iclass 24, count 0 2006.175.07:38:21.64#ibcon#read 6, iclass 24, count 0 2006.175.07:38:21.64#ibcon#end of sib2, iclass 24, count 0 2006.175.07:38:21.64#ibcon#*after write, iclass 24, count 0 2006.175.07:38:21.64#ibcon#*before return 0, iclass 24, count 0 2006.175.07:38:21.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:21.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:21.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:38:21.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:38:21.64$vc4f8/va=3,6 2006.175.07:38:21.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.07:38:21.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.07:38:21.64#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:21.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:21.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:21.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:21.70#ibcon#enter wrdev, iclass 26, count 2 2006.175.07:38:21.70#ibcon#first serial, iclass 26, count 2 2006.175.07:38:21.70#ibcon#enter sib2, iclass 26, count 2 2006.175.07:38:21.70#ibcon#flushed, iclass 26, count 2 2006.175.07:38:21.70#ibcon#about to write, iclass 26, count 2 2006.175.07:38:21.70#ibcon#wrote, iclass 26, count 2 2006.175.07:38:21.70#ibcon#about to read 3, iclass 26, count 2 2006.175.07:38:21.72#ibcon#read 3, iclass 26, count 2 2006.175.07:38:21.72#ibcon#about to read 4, iclass 26, count 2 2006.175.07:38:21.72#ibcon#read 4, iclass 26, count 2 2006.175.07:38:21.72#ibcon#about to read 5, iclass 26, count 2 2006.175.07:38:21.72#ibcon#read 5, iclass 26, count 2 2006.175.07:38:21.72#ibcon#about to read 6, iclass 26, count 2 2006.175.07:38:21.72#ibcon#read 6, iclass 26, count 2 2006.175.07:38:21.72#ibcon#end of sib2, iclass 26, count 2 2006.175.07:38:21.72#ibcon#*mode == 0, iclass 26, count 2 2006.175.07:38:21.72#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.07:38:21.72#ibcon#[25=AT03-06\r\n] 2006.175.07:38:21.72#ibcon#*before write, iclass 26, count 2 2006.175.07:38:21.72#ibcon#enter sib2, iclass 26, count 2 2006.175.07:38:21.72#ibcon#flushed, iclass 26, count 2 2006.175.07:38:21.72#ibcon#about to write, iclass 26, count 2 2006.175.07:38:21.72#ibcon#wrote, iclass 26, count 2 2006.175.07:38:21.72#ibcon#about to read 3, iclass 26, count 2 2006.175.07:38:21.75#ibcon#read 3, iclass 26, count 2 2006.175.07:38:21.75#ibcon#about to read 4, iclass 26, count 2 2006.175.07:38:21.75#ibcon#read 4, iclass 26, count 2 2006.175.07:38:21.75#ibcon#about to read 5, iclass 26, count 2 2006.175.07:38:21.75#ibcon#read 5, iclass 26, count 2 2006.175.07:38:21.75#ibcon#about to read 6, iclass 26, count 2 2006.175.07:38:21.75#ibcon#read 6, iclass 26, count 2 2006.175.07:38:21.75#ibcon#end of sib2, iclass 26, count 2 2006.175.07:38:21.75#ibcon#*after write, iclass 26, count 2 2006.175.07:38:21.75#ibcon#*before return 0, iclass 26, count 2 2006.175.07:38:21.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:21.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:21.75#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.07:38:21.75#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:21.75#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:21.87#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:21.87#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:21.87#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:38:21.87#ibcon#first serial, iclass 26, count 0 2006.175.07:38:21.87#ibcon#enter sib2, iclass 26, count 0 2006.175.07:38:21.87#ibcon#flushed, iclass 26, count 0 2006.175.07:38:21.87#ibcon#about to write, iclass 26, count 0 2006.175.07:38:21.87#ibcon#wrote, iclass 26, count 0 2006.175.07:38:21.87#ibcon#about to read 3, iclass 26, count 0 2006.175.07:38:21.89#ibcon#read 3, iclass 26, count 0 2006.175.07:38:21.89#ibcon#about to read 4, iclass 26, count 0 2006.175.07:38:21.89#ibcon#read 4, iclass 26, count 0 2006.175.07:38:21.89#ibcon#about to read 5, iclass 26, count 0 2006.175.07:38:21.89#ibcon#read 5, iclass 26, count 0 2006.175.07:38:21.89#ibcon#about to read 6, iclass 26, count 0 2006.175.07:38:21.89#ibcon#read 6, iclass 26, count 0 2006.175.07:38:21.89#ibcon#end of sib2, iclass 26, count 0 2006.175.07:38:21.89#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:38:21.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:38:21.89#ibcon#[25=USB\r\n] 2006.175.07:38:21.89#ibcon#*before write, iclass 26, count 0 2006.175.07:38:21.89#ibcon#enter sib2, iclass 26, count 0 2006.175.07:38:21.89#ibcon#flushed, iclass 26, count 0 2006.175.07:38:21.89#ibcon#about to write, iclass 26, count 0 2006.175.07:38:21.89#ibcon#wrote, iclass 26, count 0 2006.175.07:38:21.89#ibcon#about to read 3, iclass 26, count 0 2006.175.07:38:21.92#ibcon#read 3, iclass 26, count 0 2006.175.07:38:21.92#ibcon#about to read 4, iclass 26, count 0 2006.175.07:38:21.92#ibcon#read 4, iclass 26, count 0 2006.175.07:38:21.92#ibcon#about to read 5, iclass 26, count 0 2006.175.07:38:21.92#ibcon#read 5, iclass 26, count 0 2006.175.07:38:21.92#ibcon#about to read 6, iclass 26, count 0 2006.175.07:38:21.92#ibcon#read 6, iclass 26, count 0 2006.175.07:38:21.92#ibcon#end of sib2, iclass 26, count 0 2006.175.07:38:21.92#ibcon#*after write, iclass 26, count 0 2006.175.07:38:21.92#ibcon#*before return 0, iclass 26, count 0 2006.175.07:38:21.92#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:21.92#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:21.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:38:21.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:38:21.92$vc4f8/valo=4,832.99 2006.175.07:38:21.92#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.07:38:21.92#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.07:38:21.92#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:21.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:21.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:21.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:21.92#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:38:21.92#ibcon#first serial, iclass 28, count 0 2006.175.07:38:21.92#ibcon#enter sib2, iclass 28, count 0 2006.175.07:38:21.92#ibcon#flushed, iclass 28, count 0 2006.175.07:38:21.92#ibcon#about to write, iclass 28, count 0 2006.175.07:38:21.92#ibcon#wrote, iclass 28, count 0 2006.175.07:38:21.92#ibcon#about to read 3, iclass 28, count 0 2006.175.07:38:21.94#ibcon#read 3, iclass 28, count 0 2006.175.07:38:21.94#ibcon#about to read 4, iclass 28, count 0 2006.175.07:38:21.94#ibcon#read 4, iclass 28, count 0 2006.175.07:38:21.94#ibcon#about to read 5, iclass 28, count 0 2006.175.07:38:21.94#ibcon#read 5, iclass 28, count 0 2006.175.07:38:21.94#ibcon#about to read 6, iclass 28, count 0 2006.175.07:38:21.94#ibcon#read 6, iclass 28, count 0 2006.175.07:38:21.94#ibcon#end of sib2, iclass 28, count 0 2006.175.07:38:21.94#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:38:21.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:38:21.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:38:21.94#ibcon#*before write, iclass 28, count 0 2006.175.07:38:21.94#ibcon#enter sib2, iclass 28, count 0 2006.175.07:38:21.94#ibcon#flushed, iclass 28, count 0 2006.175.07:38:21.94#ibcon#about to write, iclass 28, count 0 2006.175.07:38:21.94#ibcon#wrote, iclass 28, count 0 2006.175.07:38:21.94#ibcon#about to read 3, iclass 28, count 0 2006.175.07:38:21.98#ibcon#read 3, iclass 28, count 0 2006.175.07:38:21.98#ibcon#about to read 4, iclass 28, count 0 2006.175.07:38:21.98#ibcon#read 4, iclass 28, count 0 2006.175.07:38:21.98#ibcon#about to read 5, iclass 28, count 0 2006.175.07:38:21.98#ibcon#read 5, iclass 28, count 0 2006.175.07:38:21.98#ibcon#about to read 6, iclass 28, count 0 2006.175.07:38:21.98#ibcon#read 6, iclass 28, count 0 2006.175.07:38:21.98#ibcon#end of sib2, iclass 28, count 0 2006.175.07:38:21.98#ibcon#*after write, iclass 28, count 0 2006.175.07:38:21.98#ibcon#*before return 0, iclass 28, count 0 2006.175.07:38:21.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:21.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:21.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:38:21.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:38:21.98$vc4f8/va=4,7 2006.175.07:38:21.98#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.07:38:21.98#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.07:38:21.98#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:21.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:22.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:22.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:22.04#ibcon#enter wrdev, iclass 30, count 2 2006.175.07:38:22.04#ibcon#first serial, iclass 30, count 2 2006.175.07:38:22.04#ibcon#enter sib2, iclass 30, count 2 2006.175.07:38:22.04#ibcon#flushed, iclass 30, count 2 2006.175.07:38:22.04#ibcon#about to write, iclass 30, count 2 2006.175.07:38:22.04#ibcon#wrote, iclass 30, count 2 2006.175.07:38:22.04#ibcon#about to read 3, iclass 30, count 2 2006.175.07:38:22.06#ibcon#read 3, iclass 30, count 2 2006.175.07:38:22.06#ibcon#about to read 4, iclass 30, count 2 2006.175.07:38:22.06#ibcon#read 4, iclass 30, count 2 2006.175.07:38:22.06#ibcon#about to read 5, iclass 30, count 2 2006.175.07:38:22.06#ibcon#read 5, iclass 30, count 2 2006.175.07:38:22.06#ibcon#about to read 6, iclass 30, count 2 2006.175.07:38:22.06#ibcon#read 6, iclass 30, count 2 2006.175.07:38:22.06#ibcon#end of sib2, iclass 30, count 2 2006.175.07:38:22.06#ibcon#*mode == 0, iclass 30, count 2 2006.175.07:38:22.06#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.07:38:22.06#ibcon#[25=AT04-07\r\n] 2006.175.07:38:22.06#ibcon#*before write, iclass 30, count 2 2006.175.07:38:22.06#ibcon#enter sib2, iclass 30, count 2 2006.175.07:38:22.06#ibcon#flushed, iclass 30, count 2 2006.175.07:38:22.06#ibcon#about to write, iclass 30, count 2 2006.175.07:38:22.06#ibcon#wrote, iclass 30, count 2 2006.175.07:38:22.06#ibcon#about to read 3, iclass 30, count 2 2006.175.07:38:22.09#ibcon#read 3, iclass 30, count 2 2006.175.07:38:22.09#ibcon#about to read 4, iclass 30, count 2 2006.175.07:38:22.09#ibcon#read 4, iclass 30, count 2 2006.175.07:38:22.09#ibcon#about to read 5, iclass 30, count 2 2006.175.07:38:22.09#ibcon#read 5, iclass 30, count 2 2006.175.07:38:22.09#ibcon#about to read 6, iclass 30, count 2 2006.175.07:38:22.09#ibcon#read 6, iclass 30, count 2 2006.175.07:38:22.09#ibcon#end of sib2, iclass 30, count 2 2006.175.07:38:22.09#ibcon#*after write, iclass 30, count 2 2006.175.07:38:22.09#ibcon#*before return 0, iclass 30, count 2 2006.175.07:38:22.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:22.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:22.09#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.07:38:22.09#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:22.09#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:22.21#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:22.21#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:22.21#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:38:22.21#ibcon#first serial, iclass 30, count 0 2006.175.07:38:22.21#ibcon#enter sib2, iclass 30, count 0 2006.175.07:38:22.21#ibcon#flushed, iclass 30, count 0 2006.175.07:38:22.21#ibcon#about to write, iclass 30, count 0 2006.175.07:38:22.21#ibcon#wrote, iclass 30, count 0 2006.175.07:38:22.21#ibcon#about to read 3, iclass 30, count 0 2006.175.07:38:22.23#ibcon#read 3, iclass 30, count 0 2006.175.07:38:22.23#ibcon#about to read 4, iclass 30, count 0 2006.175.07:38:22.23#ibcon#read 4, iclass 30, count 0 2006.175.07:38:22.23#ibcon#about to read 5, iclass 30, count 0 2006.175.07:38:22.23#ibcon#read 5, iclass 30, count 0 2006.175.07:38:22.23#ibcon#about to read 6, iclass 30, count 0 2006.175.07:38:22.23#ibcon#read 6, iclass 30, count 0 2006.175.07:38:22.23#ibcon#end of sib2, iclass 30, count 0 2006.175.07:38:22.23#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:38:22.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:38:22.23#ibcon#[25=USB\r\n] 2006.175.07:38:22.23#ibcon#*before write, iclass 30, count 0 2006.175.07:38:22.23#ibcon#enter sib2, iclass 30, count 0 2006.175.07:38:22.23#ibcon#flushed, iclass 30, count 0 2006.175.07:38:22.23#ibcon#about to write, iclass 30, count 0 2006.175.07:38:22.23#ibcon#wrote, iclass 30, count 0 2006.175.07:38:22.23#ibcon#about to read 3, iclass 30, count 0 2006.175.07:38:22.26#ibcon#read 3, iclass 30, count 0 2006.175.07:38:22.26#ibcon#about to read 4, iclass 30, count 0 2006.175.07:38:22.26#ibcon#read 4, iclass 30, count 0 2006.175.07:38:22.26#ibcon#about to read 5, iclass 30, count 0 2006.175.07:38:22.26#ibcon#read 5, iclass 30, count 0 2006.175.07:38:22.26#ibcon#about to read 6, iclass 30, count 0 2006.175.07:38:22.26#ibcon#read 6, iclass 30, count 0 2006.175.07:38:22.26#ibcon#end of sib2, iclass 30, count 0 2006.175.07:38:22.26#ibcon#*after write, iclass 30, count 0 2006.175.07:38:22.26#ibcon#*before return 0, iclass 30, count 0 2006.175.07:38:22.26#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:22.26#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:22.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:38:22.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:38:22.26$vc4f8/valo=5,652.99 2006.175.07:38:22.26#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.07:38:22.26#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.07:38:22.26#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:22.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:22.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:22.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:22.26#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:38:22.26#ibcon#first serial, iclass 32, count 0 2006.175.07:38:22.26#ibcon#enter sib2, iclass 32, count 0 2006.175.07:38:22.26#ibcon#flushed, iclass 32, count 0 2006.175.07:38:22.26#ibcon#about to write, iclass 32, count 0 2006.175.07:38:22.26#ibcon#wrote, iclass 32, count 0 2006.175.07:38:22.26#ibcon#about to read 3, iclass 32, count 0 2006.175.07:38:22.28#ibcon#read 3, iclass 32, count 0 2006.175.07:38:22.28#ibcon#about to read 4, iclass 32, count 0 2006.175.07:38:22.28#ibcon#read 4, iclass 32, count 0 2006.175.07:38:22.28#ibcon#about to read 5, iclass 32, count 0 2006.175.07:38:22.28#ibcon#read 5, iclass 32, count 0 2006.175.07:38:22.28#ibcon#about to read 6, iclass 32, count 0 2006.175.07:38:22.28#ibcon#read 6, iclass 32, count 0 2006.175.07:38:22.28#ibcon#end of sib2, iclass 32, count 0 2006.175.07:38:22.28#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:38:22.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:38:22.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:38:22.28#ibcon#*before write, iclass 32, count 0 2006.175.07:38:22.28#ibcon#enter sib2, iclass 32, count 0 2006.175.07:38:22.28#ibcon#flushed, iclass 32, count 0 2006.175.07:38:22.28#ibcon#about to write, iclass 32, count 0 2006.175.07:38:22.28#ibcon#wrote, iclass 32, count 0 2006.175.07:38:22.28#ibcon#about to read 3, iclass 32, count 0 2006.175.07:38:22.32#ibcon#read 3, iclass 32, count 0 2006.175.07:38:22.32#ibcon#about to read 4, iclass 32, count 0 2006.175.07:38:22.32#ibcon#read 4, iclass 32, count 0 2006.175.07:38:22.32#ibcon#about to read 5, iclass 32, count 0 2006.175.07:38:22.32#ibcon#read 5, iclass 32, count 0 2006.175.07:38:22.32#ibcon#about to read 6, iclass 32, count 0 2006.175.07:38:22.32#ibcon#read 6, iclass 32, count 0 2006.175.07:38:22.32#ibcon#end of sib2, iclass 32, count 0 2006.175.07:38:22.32#ibcon#*after write, iclass 32, count 0 2006.175.07:38:22.32#ibcon#*before return 0, iclass 32, count 0 2006.175.07:38:22.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:22.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:22.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:38:22.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:38:22.32$vc4f8/va=5,7 2006.175.07:38:22.32#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.175.07:38:22.32#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.175.07:38:22.32#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:22.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:22.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:22.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:22.38#ibcon#enter wrdev, iclass 34, count 2 2006.175.07:38:22.38#ibcon#first serial, iclass 34, count 2 2006.175.07:38:22.38#ibcon#enter sib2, iclass 34, count 2 2006.175.07:38:22.38#ibcon#flushed, iclass 34, count 2 2006.175.07:38:22.38#ibcon#about to write, iclass 34, count 2 2006.175.07:38:22.38#ibcon#wrote, iclass 34, count 2 2006.175.07:38:22.38#ibcon#about to read 3, iclass 34, count 2 2006.175.07:38:22.40#ibcon#read 3, iclass 34, count 2 2006.175.07:38:22.40#ibcon#about to read 4, iclass 34, count 2 2006.175.07:38:22.40#ibcon#read 4, iclass 34, count 2 2006.175.07:38:22.40#ibcon#about to read 5, iclass 34, count 2 2006.175.07:38:22.40#ibcon#read 5, iclass 34, count 2 2006.175.07:38:22.40#ibcon#about to read 6, iclass 34, count 2 2006.175.07:38:22.40#ibcon#read 6, iclass 34, count 2 2006.175.07:38:22.40#ibcon#end of sib2, iclass 34, count 2 2006.175.07:38:22.40#ibcon#*mode == 0, iclass 34, count 2 2006.175.07:38:22.40#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.175.07:38:22.40#ibcon#[25=AT05-07\r\n] 2006.175.07:38:22.40#ibcon#*before write, iclass 34, count 2 2006.175.07:38:22.40#ibcon#enter sib2, iclass 34, count 2 2006.175.07:38:22.40#ibcon#flushed, iclass 34, count 2 2006.175.07:38:22.40#ibcon#about to write, iclass 34, count 2 2006.175.07:38:22.40#ibcon#wrote, iclass 34, count 2 2006.175.07:38:22.40#ibcon#about to read 3, iclass 34, count 2 2006.175.07:38:22.43#ibcon#read 3, iclass 34, count 2 2006.175.07:38:22.43#ibcon#about to read 4, iclass 34, count 2 2006.175.07:38:22.43#ibcon#read 4, iclass 34, count 2 2006.175.07:38:22.43#ibcon#about to read 5, iclass 34, count 2 2006.175.07:38:22.43#ibcon#read 5, iclass 34, count 2 2006.175.07:38:22.43#ibcon#about to read 6, iclass 34, count 2 2006.175.07:38:22.43#ibcon#read 6, iclass 34, count 2 2006.175.07:38:22.43#ibcon#end of sib2, iclass 34, count 2 2006.175.07:38:22.43#ibcon#*after write, iclass 34, count 2 2006.175.07:38:22.43#ibcon#*before return 0, iclass 34, count 2 2006.175.07:38:22.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:22.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:22.43#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.175.07:38:22.43#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:22.43#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:22.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:22.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:22.55#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:38:22.55#ibcon#first serial, iclass 34, count 0 2006.175.07:38:22.55#ibcon#enter sib2, iclass 34, count 0 2006.175.07:38:22.55#ibcon#flushed, iclass 34, count 0 2006.175.07:38:22.55#ibcon#about to write, iclass 34, count 0 2006.175.07:38:22.55#ibcon#wrote, iclass 34, count 0 2006.175.07:38:22.55#ibcon#about to read 3, iclass 34, count 0 2006.175.07:38:22.57#ibcon#read 3, iclass 34, count 0 2006.175.07:38:22.57#ibcon#about to read 4, iclass 34, count 0 2006.175.07:38:22.57#ibcon#read 4, iclass 34, count 0 2006.175.07:38:22.57#ibcon#about to read 5, iclass 34, count 0 2006.175.07:38:22.57#ibcon#read 5, iclass 34, count 0 2006.175.07:38:22.57#ibcon#about to read 6, iclass 34, count 0 2006.175.07:38:22.57#ibcon#read 6, iclass 34, count 0 2006.175.07:38:22.57#ibcon#end of sib2, iclass 34, count 0 2006.175.07:38:22.57#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:38:22.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:38:22.57#ibcon#[25=USB\r\n] 2006.175.07:38:22.57#ibcon#*before write, iclass 34, count 0 2006.175.07:38:22.57#ibcon#enter sib2, iclass 34, count 0 2006.175.07:38:22.57#ibcon#flushed, iclass 34, count 0 2006.175.07:38:22.57#ibcon#about to write, iclass 34, count 0 2006.175.07:38:22.57#ibcon#wrote, iclass 34, count 0 2006.175.07:38:22.57#ibcon#about to read 3, iclass 34, count 0 2006.175.07:38:22.60#ibcon#read 3, iclass 34, count 0 2006.175.07:38:22.60#ibcon#about to read 4, iclass 34, count 0 2006.175.07:38:22.60#ibcon#read 4, iclass 34, count 0 2006.175.07:38:22.60#ibcon#about to read 5, iclass 34, count 0 2006.175.07:38:22.60#ibcon#read 5, iclass 34, count 0 2006.175.07:38:22.60#ibcon#about to read 6, iclass 34, count 0 2006.175.07:38:22.60#ibcon#read 6, iclass 34, count 0 2006.175.07:38:22.60#ibcon#end of sib2, iclass 34, count 0 2006.175.07:38:22.60#ibcon#*after write, iclass 34, count 0 2006.175.07:38:22.60#ibcon#*before return 0, iclass 34, count 0 2006.175.07:38:22.60#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:22.60#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:22.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:38:22.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:38:22.60$vc4f8/valo=6,772.99 2006.175.07:38:22.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.07:38:22.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.07:38:22.60#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:22.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:22.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:22.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:22.60#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:38:22.60#ibcon#first serial, iclass 36, count 0 2006.175.07:38:22.60#ibcon#enter sib2, iclass 36, count 0 2006.175.07:38:22.60#ibcon#flushed, iclass 36, count 0 2006.175.07:38:22.60#ibcon#about to write, iclass 36, count 0 2006.175.07:38:22.60#ibcon#wrote, iclass 36, count 0 2006.175.07:38:22.60#ibcon#about to read 3, iclass 36, count 0 2006.175.07:38:22.62#ibcon#read 3, iclass 36, count 0 2006.175.07:38:22.62#ibcon#about to read 4, iclass 36, count 0 2006.175.07:38:22.62#ibcon#read 4, iclass 36, count 0 2006.175.07:38:22.62#ibcon#about to read 5, iclass 36, count 0 2006.175.07:38:22.62#ibcon#read 5, iclass 36, count 0 2006.175.07:38:22.62#ibcon#about to read 6, iclass 36, count 0 2006.175.07:38:22.62#ibcon#read 6, iclass 36, count 0 2006.175.07:38:22.62#ibcon#end of sib2, iclass 36, count 0 2006.175.07:38:22.62#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:38:22.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:38:22.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:38:22.62#ibcon#*before write, iclass 36, count 0 2006.175.07:38:22.62#ibcon#enter sib2, iclass 36, count 0 2006.175.07:38:22.62#ibcon#flushed, iclass 36, count 0 2006.175.07:38:22.62#ibcon#about to write, iclass 36, count 0 2006.175.07:38:22.62#ibcon#wrote, iclass 36, count 0 2006.175.07:38:22.62#ibcon#about to read 3, iclass 36, count 0 2006.175.07:38:22.66#ibcon#read 3, iclass 36, count 0 2006.175.07:38:22.66#ibcon#about to read 4, iclass 36, count 0 2006.175.07:38:22.66#ibcon#read 4, iclass 36, count 0 2006.175.07:38:22.66#ibcon#about to read 5, iclass 36, count 0 2006.175.07:38:22.66#ibcon#read 5, iclass 36, count 0 2006.175.07:38:22.66#ibcon#about to read 6, iclass 36, count 0 2006.175.07:38:22.66#ibcon#read 6, iclass 36, count 0 2006.175.07:38:22.66#ibcon#end of sib2, iclass 36, count 0 2006.175.07:38:22.66#ibcon#*after write, iclass 36, count 0 2006.175.07:38:22.66#ibcon#*before return 0, iclass 36, count 0 2006.175.07:38:22.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:22.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:22.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:38:22.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:38:22.66$vc4f8/va=6,6 2006.175.07:38:22.66#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.175.07:38:22.66#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.175.07:38:22.66#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:22.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:38:22.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:38:22.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:38:22.72#ibcon#enter wrdev, iclass 38, count 2 2006.175.07:38:22.72#ibcon#first serial, iclass 38, count 2 2006.175.07:38:22.72#ibcon#enter sib2, iclass 38, count 2 2006.175.07:38:22.72#ibcon#flushed, iclass 38, count 2 2006.175.07:38:22.72#ibcon#about to write, iclass 38, count 2 2006.175.07:38:22.72#ibcon#wrote, iclass 38, count 2 2006.175.07:38:22.72#ibcon#about to read 3, iclass 38, count 2 2006.175.07:38:22.74#ibcon#read 3, iclass 38, count 2 2006.175.07:38:22.74#ibcon#about to read 4, iclass 38, count 2 2006.175.07:38:22.74#ibcon#read 4, iclass 38, count 2 2006.175.07:38:22.74#ibcon#about to read 5, iclass 38, count 2 2006.175.07:38:22.74#ibcon#read 5, iclass 38, count 2 2006.175.07:38:22.74#ibcon#about to read 6, iclass 38, count 2 2006.175.07:38:22.74#ibcon#read 6, iclass 38, count 2 2006.175.07:38:22.74#ibcon#end of sib2, iclass 38, count 2 2006.175.07:38:22.74#ibcon#*mode == 0, iclass 38, count 2 2006.175.07:38:22.74#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.175.07:38:22.74#ibcon#[25=AT06-06\r\n] 2006.175.07:38:22.74#ibcon#*before write, iclass 38, count 2 2006.175.07:38:22.74#ibcon#enter sib2, iclass 38, count 2 2006.175.07:38:22.74#ibcon#flushed, iclass 38, count 2 2006.175.07:38:22.74#ibcon#about to write, iclass 38, count 2 2006.175.07:38:22.74#ibcon#wrote, iclass 38, count 2 2006.175.07:38:22.74#ibcon#about to read 3, iclass 38, count 2 2006.175.07:38:22.77#ibcon#read 3, iclass 38, count 2 2006.175.07:38:22.77#ibcon#about to read 4, iclass 38, count 2 2006.175.07:38:22.77#ibcon#read 4, iclass 38, count 2 2006.175.07:38:22.77#ibcon#about to read 5, iclass 38, count 2 2006.175.07:38:22.77#ibcon#read 5, iclass 38, count 2 2006.175.07:38:22.77#ibcon#about to read 6, iclass 38, count 2 2006.175.07:38:22.77#ibcon#read 6, iclass 38, count 2 2006.175.07:38:22.77#ibcon#end of sib2, iclass 38, count 2 2006.175.07:38:22.77#ibcon#*after write, iclass 38, count 2 2006.175.07:38:22.77#ibcon#*before return 0, iclass 38, count 2 2006.175.07:38:22.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:38:22.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:38:22.77#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.175.07:38:22.77#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:22.77#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:38:22.89#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:38:22.89#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:38:22.89#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:38:22.89#ibcon#first serial, iclass 38, count 0 2006.175.07:38:22.89#ibcon#enter sib2, iclass 38, count 0 2006.175.07:38:22.89#ibcon#flushed, iclass 38, count 0 2006.175.07:38:22.89#ibcon#about to write, iclass 38, count 0 2006.175.07:38:22.89#ibcon#wrote, iclass 38, count 0 2006.175.07:38:22.89#ibcon#about to read 3, iclass 38, count 0 2006.175.07:38:22.91#ibcon#read 3, iclass 38, count 0 2006.175.07:38:22.91#ibcon#about to read 4, iclass 38, count 0 2006.175.07:38:22.91#ibcon#read 4, iclass 38, count 0 2006.175.07:38:22.91#ibcon#about to read 5, iclass 38, count 0 2006.175.07:38:22.91#ibcon#read 5, iclass 38, count 0 2006.175.07:38:22.91#ibcon#about to read 6, iclass 38, count 0 2006.175.07:38:22.91#ibcon#read 6, iclass 38, count 0 2006.175.07:38:22.91#ibcon#end of sib2, iclass 38, count 0 2006.175.07:38:22.91#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:38:22.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:38:22.91#ibcon#[25=USB\r\n] 2006.175.07:38:22.91#ibcon#*before write, iclass 38, count 0 2006.175.07:38:22.91#ibcon#enter sib2, iclass 38, count 0 2006.175.07:38:22.91#ibcon#flushed, iclass 38, count 0 2006.175.07:38:22.91#ibcon#about to write, iclass 38, count 0 2006.175.07:38:22.91#ibcon#wrote, iclass 38, count 0 2006.175.07:38:22.91#ibcon#about to read 3, iclass 38, count 0 2006.175.07:38:22.94#ibcon#read 3, iclass 38, count 0 2006.175.07:38:22.94#ibcon#about to read 4, iclass 38, count 0 2006.175.07:38:22.94#ibcon#read 4, iclass 38, count 0 2006.175.07:38:22.94#ibcon#about to read 5, iclass 38, count 0 2006.175.07:38:22.94#ibcon#read 5, iclass 38, count 0 2006.175.07:38:22.94#ibcon#about to read 6, iclass 38, count 0 2006.175.07:38:22.94#ibcon#read 6, iclass 38, count 0 2006.175.07:38:22.94#ibcon#end of sib2, iclass 38, count 0 2006.175.07:38:22.94#ibcon#*after write, iclass 38, count 0 2006.175.07:38:22.94#ibcon#*before return 0, iclass 38, count 0 2006.175.07:38:22.94#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:38:22.94#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:38:22.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:38:22.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:38:22.94$vc4f8/valo=7,832.99 2006.175.07:38:22.94#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.07:38:22.94#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.07:38:22.94#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:22.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:38:22.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:38:22.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:38:22.94#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:38:22.94#ibcon#first serial, iclass 40, count 0 2006.175.07:38:22.94#ibcon#enter sib2, iclass 40, count 0 2006.175.07:38:22.94#ibcon#flushed, iclass 40, count 0 2006.175.07:38:22.94#ibcon#about to write, iclass 40, count 0 2006.175.07:38:22.94#ibcon#wrote, iclass 40, count 0 2006.175.07:38:22.94#ibcon#about to read 3, iclass 40, count 0 2006.175.07:38:22.96#ibcon#read 3, iclass 40, count 0 2006.175.07:38:22.96#ibcon#about to read 4, iclass 40, count 0 2006.175.07:38:22.96#ibcon#read 4, iclass 40, count 0 2006.175.07:38:22.96#ibcon#about to read 5, iclass 40, count 0 2006.175.07:38:22.96#ibcon#read 5, iclass 40, count 0 2006.175.07:38:22.96#ibcon#about to read 6, iclass 40, count 0 2006.175.07:38:22.96#ibcon#read 6, iclass 40, count 0 2006.175.07:38:22.96#ibcon#end of sib2, iclass 40, count 0 2006.175.07:38:22.96#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:38:22.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:38:22.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:38:22.96#ibcon#*before write, iclass 40, count 0 2006.175.07:38:22.96#ibcon#enter sib2, iclass 40, count 0 2006.175.07:38:22.96#ibcon#flushed, iclass 40, count 0 2006.175.07:38:22.96#ibcon#about to write, iclass 40, count 0 2006.175.07:38:22.96#ibcon#wrote, iclass 40, count 0 2006.175.07:38:22.96#ibcon#about to read 3, iclass 40, count 0 2006.175.07:38:23.00#ibcon#read 3, iclass 40, count 0 2006.175.07:38:23.00#ibcon#about to read 4, iclass 40, count 0 2006.175.07:38:23.00#ibcon#read 4, iclass 40, count 0 2006.175.07:38:23.00#ibcon#about to read 5, iclass 40, count 0 2006.175.07:38:23.00#ibcon#read 5, iclass 40, count 0 2006.175.07:38:23.00#ibcon#about to read 6, iclass 40, count 0 2006.175.07:38:23.00#ibcon#read 6, iclass 40, count 0 2006.175.07:38:23.00#ibcon#end of sib2, iclass 40, count 0 2006.175.07:38:23.00#ibcon#*after write, iclass 40, count 0 2006.175.07:38:23.00#ibcon#*before return 0, iclass 40, count 0 2006.175.07:38:23.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:38:23.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:38:23.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:38:23.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:38:23.00$vc4f8/va=7,6 2006.175.07:38:23.00#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.175.07:38:23.00#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.175.07:38:23.00#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:23.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:38:23.06#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:38:23.06#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:38:23.06#ibcon#enter wrdev, iclass 4, count 2 2006.175.07:38:23.06#ibcon#first serial, iclass 4, count 2 2006.175.07:38:23.06#ibcon#enter sib2, iclass 4, count 2 2006.175.07:38:23.06#ibcon#flushed, iclass 4, count 2 2006.175.07:38:23.06#ibcon#about to write, iclass 4, count 2 2006.175.07:38:23.06#ibcon#wrote, iclass 4, count 2 2006.175.07:38:23.06#ibcon#about to read 3, iclass 4, count 2 2006.175.07:38:23.08#ibcon#read 3, iclass 4, count 2 2006.175.07:38:23.08#ibcon#about to read 4, iclass 4, count 2 2006.175.07:38:23.08#ibcon#read 4, iclass 4, count 2 2006.175.07:38:23.08#ibcon#about to read 5, iclass 4, count 2 2006.175.07:38:23.08#ibcon#read 5, iclass 4, count 2 2006.175.07:38:23.08#ibcon#about to read 6, iclass 4, count 2 2006.175.07:38:23.08#ibcon#read 6, iclass 4, count 2 2006.175.07:38:23.08#ibcon#end of sib2, iclass 4, count 2 2006.175.07:38:23.08#ibcon#*mode == 0, iclass 4, count 2 2006.175.07:38:23.08#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.175.07:38:23.08#ibcon#[25=AT07-06\r\n] 2006.175.07:38:23.08#ibcon#*before write, iclass 4, count 2 2006.175.07:38:23.08#ibcon#enter sib2, iclass 4, count 2 2006.175.07:38:23.08#ibcon#flushed, iclass 4, count 2 2006.175.07:38:23.08#ibcon#about to write, iclass 4, count 2 2006.175.07:38:23.08#ibcon#wrote, iclass 4, count 2 2006.175.07:38:23.08#ibcon#about to read 3, iclass 4, count 2 2006.175.07:38:23.11#ibcon#read 3, iclass 4, count 2 2006.175.07:38:23.11#ibcon#about to read 4, iclass 4, count 2 2006.175.07:38:23.11#ibcon#read 4, iclass 4, count 2 2006.175.07:38:23.11#ibcon#about to read 5, iclass 4, count 2 2006.175.07:38:23.11#ibcon#read 5, iclass 4, count 2 2006.175.07:38:23.11#ibcon#about to read 6, iclass 4, count 2 2006.175.07:38:23.11#ibcon#read 6, iclass 4, count 2 2006.175.07:38:23.11#ibcon#end of sib2, iclass 4, count 2 2006.175.07:38:23.11#ibcon#*after write, iclass 4, count 2 2006.175.07:38:23.11#ibcon#*before return 0, iclass 4, count 2 2006.175.07:38:23.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:38:23.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:38:23.11#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.175.07:38:23.11#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:23.11#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:38:23.23#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:38:23.23#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:38:23.23#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:38:23.23#ibcon#first serial, iclass 4, count 0 2006.175.07:38:23.23#ibcon#enter sib2, iclass 4, count 0 2006.175.07:38:23.23#ibcon#flushed, iclass 4, count 0 2006.175.07:38:23.23#ibcon#about to write, iclass 4, count 0 2006.175.07:38:23.23#ibcon#wrote, iclass 4, count 0 2006.175.07:38:23.23#ibcon#about to read 3, iclass 4, count 0 2006.175.07:38:23.25#ibcon#read 3, iclass 4, count 0 2006.175.07:38:23.25#ibcon#about to read 4, iclass 4, count 0 2006.175.07:38:23.25#ibcon#read 4, iclass 4, count 0 2006.175.07:38:23.25#ibcon#about to read 5, iclass 4, count 0 2006.175.07:38:23.25#ibcon#read 5, iclass 4, count 0 2006.175.07:38:23.25#ibcon#about to read 6, iclass 4, count 0 2006.175.07:38:23.25#ibcon#read 6, iclass 4, count 0 2006.175.07:38:23.25#ibcon#end of sib2, iclass 4, count 0 2006.175.07:38:23.25#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:38:23.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:38:23.25#ibcon#[25=USB\r\n] 2006.175.07:38:23.25#ibcon#*before write, iclass 4, count 0 2006.175.07:38:23.25#ibcon#enter sib2, iclass 4, count 0 2006.175.07:38:23.25#ibcon#flushed, iclass 4, count 0 2006.175.07:38:23.25#ibcon#about to write, iclass 4, count 0 2006.175.07:38:23.25#ibcon#wrote, iclass 4, count 0 2006.175.07:38:23.25#ibcon#about to read 3, iclass 4, count 0 2006.175.07:38:23.28#ibcon#read 3, iclass 4, count 0 2006.175.07:38:23.28#ibcon#about to read 4, iclass 4, count 0 2006.175.07:38:23.28#ibcon#read 4, iclass 4, count 0 2006.175.07:38:23.28#ibcon#about to read 5, iclass 4, count 0 2006.175.07:38:23.28#ibcon#read 5, iclass 4, count 0 2006.175.07:38:23.28#ibcon#about to read 6, iclass 4, count 0 2006.175.07:38:23.28#ibcon#read 6, iclass 4, count 0 2006.175.07:38:23.28#ibcon#end of sib2, iclass 4, count 0 2006.175.07:38:23.28#ibcon#*after write, iclass 4, count 0 2006.175.07:38:23.28#ibcon#*before return 0, iclass 4, count 0 2006.175.07:38:23.28#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:38:23.28#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:38:23.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:38:23.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:38:23.28$vc4f8/valo=8,852.99 2006.175.07:38:23.28#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.175.07:38:23.28#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.175.07:38:23.28#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:23.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:38:23.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:38:23.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:38:23.28#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:38:23.28#ibcon#first serial, iclass 6, count 0 2006.175.07:38:23.28#ibcon#enter sib2, iclass 6, count 0 2006.175.07:38:23.28#ibcon#flushed, iclass 6, count 0 2006.175.07:38:23.28#ibcon#about to write, iclass 6, count 0 2006.175.07:38:23.28#ibcon#wrote, iclass 6, count 0 2006.175.07:38:23.28#ibcon#about to read 3, iclass 6, count 0 2006.175.07:38:23.30#ibcon#read 3, iclass 6, count 0 2006.175.07:38:23.30#ibcon#about to read 4, iclass 6, count 0 2006.175.07:38:23.30#ibcon#read 4, iclass 6, count 0 2006.175.07:38:23.30#ibcon#about to read 5, iclass 6, count 0 2006.175.07:38:23.30#ibcon#read 5, iclass 6, count 0 2006.175.07:38:23.30#ibcon#about to read 6, iclass 6, count 0 2006.175.07:38:23.30#ibcon#read 6, iclass 6, count 0 2006.175.07:38:23.30#ibcon#end of sib2, iclass 6, count 0 2006.175.07:38:23.30#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:38:23.30#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:38:23.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:38:23.30#ibcon#*before write, iclass 6, count 0 2006.175.07:38:23.30#ibcon#enter sib2, iclass 6, count 0 2006.175.07:38:23.30#ibcon#flushed, iclass 6, count 0 2006.175.07:38:23.30#ibcon#about to write, iclass 6, count 0 2006.175.07:38:23.30#ibcon#wrote, iclass 6, count 0 2006.175.07:38:23.30#ibcon#about to read 3, iclass 6, count 0 2006.175.07:38:23.34#ibcon#read 3, iclass 6, count 0 2006.175.07:38:23.34#ibcon#about to read 4, iclass 6, count 0 2006.175.07:38:23.34#ibcon#read 4, iclass 6, count 0 2006.175.07:38:23.34#ibcon#about to read 5, iclass 6, count 0 2006.175.07:38:23.34#ibcon#read 5, iclass 6, count 0 2006.175.07:38:23.34#ibcon#about to read 6, iclass 6, count 0 2006.175.07:38:23.34#ibcon#read 6, iclass 6, count 0 2006.175.07:38:23.34#ibcon#end of sib2, iclass 6, count 0 2006.175.07:38:23.34#ibcon#*after write, iclass 6, count 0 2006.175.07:38:23.34#ibcon#*before return 0, iclass 6, count 0 2006.175.07:38:23.34#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:38:23.34#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:38:23.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:38:23.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:38:23.34$vc4f8/va=8,6 2006.175.07:38:23.34#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.175.07:38:23.34#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.175.07:38:23.34#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:23.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.07:38:23.40#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.07:38:23.40#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.07:38:23.40#ibcon#enter wrdev, iclass 10, count 2 2006.175.07:38:23.40#ibcon#first serial, iclass 10, count 2 2006.175.07:38:23.40#ibcon#enter sib2, iclass 10, count 2 2006.175.07:38:23.40#ibcon#flushed, iclass 10, count 2 2006.175.07:38:23.40#ibcon#about to write, iclass 10, count 2 2006.175.07:38:23.40#ibcon#wrote, iclass 10, count 2 2006.175.07:38:23.40#ibcon#about to read 3, iclass 10, count 2 2006.175.07:38:23.42#ibcon#read 3, iclass 10, count 2 2006.175.07:38:23.42#ibcon#about to read 4, iclass 10, count 2 2006.175.07:38:23.42#ibcon#read 4, iclass 10, count 2 2006.175.07:38:23.42#ibcon#about to read 5, iclass 10, count 2 2006.175.07:38:23.42#ibcon#read 5, iclass 10, count 2 2006.175.07:38:23.42#ibcon#about to read 6, iclass 10, count 2 2006.175.07:38:23.42#ibcon#read 6, iclass 10, count 2 2006.175.07:38:23.42#ibcon#end of sib2, iclass 10, count 2 2006.175.07:38:23.42#ibcon#*mode == 0, iclass 10, count 2 2006.175.07:38:23.42#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.175.07:38:23.42#ibcon#[25=AT08-06\r\n] 2006.175.07:38:23.42#ibcon#*before write, iclass 10, count 2 2006.175.07:38:23.42#ibcon#enter sib2, iclass 10, count 2 2006.175.07:38:23.42#ibcon#flushed, iclass 10, count 2 2006.175.07:38:23.42#ibcon#about to write, iclass 10, count 2 2006.175.07:38:23.42#ibcon#wrote, iclass 10, count 2 2006.175.07:38:23.42#ibcon#about to read 3, iclass 10, count 2 2006.175.07:38:23.45#ibcon#read 3, iclass 10, count 2 2006.175.07:38:23.45#ibcon#about to read 4, iclass 10, count 2 2006.175.07:38:23.45#ibcon#read 4, iclass 10, count 2 2006.175.07:38:23.45#ibcon#about to read 5, iclass 10, count 2 2006.175.07:38:23.45#ibcon#read 5, iclass 10, count 2 2006.175.07:38:23.45#ibcon#about to read 6, iclass 10, count 2 2006.175.07:38:23.45#ibcon#read 6, iclass 10, count 2 2006.175.07:38:23.45#ibcon#end of sib2, iclass 10, count 2 2006.175.07:38:23.45#ibcon#*after write, iclass 10, count 2 2006.175.07:38:23.45#ibcon#*before return 0, iclass 10, count 2 2006.175.07:38:23.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.07:38:23.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.175.07:38:23.45#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.175.07:38:23.45#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:23.45#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.07:38:23.57#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.07:38:23.57#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.07:38:23.57#ibcon#enter wrdev, iclass 10, count 0 2006.175.07:38:23.57#ibcon#first serial, iclass 10, count 0 2006.175.07:38:23.57#ibcon#enter sib2, iclass 10, count 0 2006.175.07:38:23.57#ibcon#flushed, iclass 10, count 0 2006.175.07:38:23.57#ibcon#about to write, iclass 10, count 0 2006.175.07:38:23.57#ibcon#wrote, iclass 10, count 0 2006.175.07:38:23.57#ibcon#about to read 3, iclass 10, count 0 2006.175.07:38:23.59#ibcon#read 3, iclass 10, count 0 2006.175.07:38:23.59#ibcon#about to read 4, iclass 10, count 0 2006.175.07:38:23.59#ibcon#read 4, iclass 10, count 0 2006.175.07:38:23.59#ibcon#about to read 5, iclass 10, count 0 2006.175.07:38:23.59#ibcon#read 5, iclass 10, count 0 2006.175.07:38:23.59#ibcon#about to read 6, iclass 10, count 0 2006.175.07:38:23.59#ibcon#read 6, iclass 10, count 0 2006.175.07:38:23.59#ibcon#end of sib2, iclass 10, count 0 2006.175.07:38:23.59#ibcon#*mode == 0, iclass 10, count 0 2006.175.07:38:23.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.07:38:23.59#ibcon#[25=USB\r\n] 2006.175.07:38:23.59#ibcon#*before write, iclass 10, count 0 2006.175.07:38:23.59#ibcon#enter sib2, iclass 10, count 0 2006.175.07:38:23.59#ibcon#flushed, iclass 10, count 0 2006.175.07:38:23.59#ibcon#about to write, iclass 10, count 0 2006.175.07:38:23.59#ibcon#wrote, iclass 10, count 0 2006.175.07:38:23.59#ibcon#about to read 3, iclass 10, count 0 2006.175.07:38:23.62#ibcon#read 3, iclass 10, count 0 2006.175.07:38:23.62#ibcon#about to read 4, iclass 10, count 0 2006.175.07:38:23.62#ibcon#read 4, iclass 10, count 0 2006.175.07:38:23.62#ibcon#about to read 5, iclass 10, count 0 2006.175.07:38:23.62#ibcon#read 5, iclass 10, count 0 2006.175.07:38:23.62#ibcon#about to read 6, iclass 10, count 0 2006.175.07:38:23.62#ibcon#read 6, iclass 10, count 0 2006.175.07:38:23.62#ibcon#end of sib2, iclass 10, count 0 2006.175.07:38:23.62#ibcon#*after write, iclass 10, count 0 2006.175.07:38:23.62#ibcon#*before return 0, iclass 10, count 0 2006.175.07:38:23.62#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.07:38:23.62#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.175.07:38:23.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.07:38:23.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.07:38:23.62$vc4f8/vblo=1,632.99 2006.175.07:38:23.62#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.07:38:23.62#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.07:38:23.62#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:23.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:38:23.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:38:23.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:38:23.62#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:38:23.62#ibcon#first serial, iclass 12, count 0 2006.175.07:38:23.62#ibcon#enter sib2, iclass 12, count 0 2006.175.07:38:23.62#ibcon#flushed, iclass 12, count 0 2006.175.07:38:23.62#ibcon#about to write, iclass 12, count 0 2006.175.07:38:23.62#ibcon#wrote, iclass 12, count 0 2006.175.07:38:23.62#ibcon#about to read 3, iclass 12, count 0 2006.175.07:38:23.64#ibcon#read 3, iclass 12, count 0 2006.175.07:38:23.64#ibcon#about to read 4, iclass 12, count 0 2006.175.07:38:23.64#ibcon#read 4, iclass 12, count 0 2006.175.07:38:23.64#ibcon#about to read 5, iclass 12, count 0 2006.175.07:38:23.64#ibcon#read 5, iclass 12, count 0 2006.175.07:38:23.64#ibcon#about to read 6, iclass 12, count 0 2006.175.07:38:23.64#ibcon#read 6, iclass 12, count 0 2006.175.07:38:23.64#ibcon#end of sib2, iclass 12, count 0 2006.175.07:38:23.64#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:38:23.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:38:23.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:38:23.64#ibcon#*before write, iclass 12, count 0 2006.175.07:38:23.64#ibcon#enter sib2, iclass 12, count 0 2006.175.07:38:23.64#ibcon#flushed, iclass 12, count 0 2006.175.07:38:23.64#ibcon#about to write, iclass 12, count 0 2006.175.07:38:23.64#ibcon#wrote, iclass 12, count 0 2006.175.07:38:23.64#ibcon#about to read 3, iclass 12, count 0 2006.175.07:38:23.68#ibcon#read 3, iclass 12, count 0 2006.175.07:38:23.68#ibcon#about to read 4, iclass 12, count 0 2006.175.07:38:23.68#ibcon#read 4, iclass 12, count 0 2006.175.07:38:23.68#ibcon#about to read 5, iclass 12, count 0 2006.175.07:38:23.68#ibcon#read 5, iclass 12, count 0 2006.175.07:38:23.68#ibcon#about to read 6, iclass 12, count 0 2006.175.07:38:23.68#ibcon#read 6, iclass 12, count 0 2006.175.07:38:23.68#ibcon#end of sib2, iclass 12, count 0 2006.175.07:38:23.68#ibcon#*after write, iclass 12, count 0 2006.175.07:38:23.68#ibcon#*before return 0, iclass 12, count 0 2006.175.07:38:23.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:38:23.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:38:23.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:38:23.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:38:23.68$vc4f8/vb=1,4 2006.175.07:38:23.68#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.07:38:23.68#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.07:38:23.68#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:23.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:38:23.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:38:23.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:38:23.68#ibcon#enter wrdev, iclass 14, count 2 2006.175.07:38:23.68#ibcon#first serial, iclass 14, count 2 2006.175.07:38:23.68#ibcon#enter sib2, iclass 14, count 2 2006.175.07:38:23.68#ibcon#flushed, iclass 14, count 2 2006.175.07:38:23.68#ibcon#about to write, iclass 14, count 2 2006.175.07:38:23.68#ibcon#wrote, iclass 14, count 2 2006.175.07:38:23.68#ibcon#about to read 3, iclass 14, count 2 2006.175.07:38:23.70#ibcon#read 3, iclass 14, count 2 2006.175.07:38:23.70#ibcon#about to read 4, iclass 14, count 2 2006.175.07:38:23.70#ibcon#read 4, iclass 14, count 2 2006.175.07:38:23.70#ibcon#about to read 5, iclass 14, count 2 2006.175.07:38:23.70#ibcon#read 5, iclass 14, count 2 2006.175.07:38:23.70#ibcon#about to read 6, iclass 14, count 2 2006.175.07:38:23.70#ibcon#read 6, iclass 14, count 2 2006.175.07:38:23.70#ibcon#end of sib2, iclass 14, count 2 2006.175.07:38:23.70#ibcon#*mode == 0, iclass 14, count 2 2006.175.07:38:23.70#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.07:38:23.70#ibcon#[27=AT01-04\r\n] 2006.175.07:38:23.70#ibcon#*before write, iclass 14, count 2 2006.175.07:38:23.70#ibcon#enter sib2, iclass 14, count 2 2006.175.07:38:23.70#ibcon#flushed, iclass 14, count 2 2006.175.07:38:23.70#ibcon#about to write, iclass 14, count 2 2006.175.07:38:23.70#ibcon#wrote, iclass 14, count 2 2006.175.07:38:23.70#ibcon#about to read 3, iclass 14, count 2 2006.175.07:38:23.73#ibcon#read 3, iclass 14, count 2 2006.175.07:38:23.73#ibcon#about to read 4, iclass 14, count 2 2006.175.07:38:23.73#ibcon#read 4, iclass 14, count 2 2006.175.07:38:23.73#ibcon#about to read 5, iclass 14, count 2 2006.175.07:38:23.73#ibcon#read 5, iclass 14, count 2 2006.175.07:38:23.73#ibcon#about to read 6, iclass 14, count 2 2006.175.07:38:23.73#ibcon#read 6, iclass 14, count 2 2006.175.07:38:23.73#ibcon#end of sib2, iclass 14, count 2 2006.175.07:38:23.73#ibcon#*after write, iclass 14, count 2 2006.175.07:38:23.73#ibcon#*before return 0, iclass 14, count 2 2006.175.07:38:23.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:38:23.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:38:23.73#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.07:38:23.73#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:23.73#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:38:23.85#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:38:23.85#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:38:23.85#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:38:23.85#ibcon#first serial, iclass 14, count 0 2006.175.07:38:23.85#ibcon#enter sib2, iclass 14, count 0 2006.175.07:38:23.85#ibcon#flushed, iclass 14, count 0 2006.175.07:38:23.85#ibcon#about to write, iclass 14, count 0 2006.175.07:38:23.85#ibcon#wrote, iclass 14, count 0 2006.175.07:38:23.85#ibcon#about to read 3, iclass 14, count 0 2006.175.07:38:23.87#ibcon#read 3, iclass 14, count 0 2006.175.07:38:23.87#ibcon#about to read 4, iclass 14, count 0 2006.175.07:38:23.87#ibcon#read 4, iclass 14, count 0 2006.175.07:38:23.87#ibcon#about to read 5, iclass 14, count 0 2006.175.07:38:23.87#ibcon#read 5, iclass 14, count 0 2006.175.07:38:23.87#ibcon#about to read 6, iclass 14, count 0 2006.175.07:38:23.87#ibcon#read 6, iclass 14, count 0 2006.175.07:38:23.87#ibcon#end of sib2, iclass 14, count 0 2006.175.07:38:23.87#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:38:23.87#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:38:23.87#ibcon#[27=USB\r\n] 2006.175.07:38:23.87#ibcon#*before write, iclass 14, count 0 2006.175.07:38:23.87#ibcon#enter sib2, iclass 14, count 0 2006.175.07:38:23.87#ibcon#flushed, iclass 14, count 0 2006.175.07:38:23.87#ibcon#about to write, iclass 14, count 0 2006.175.07:38:23.87#ibcon#wrote, iclass 14, count 0 2006.175.07:38:23.87#ibcon#about to read 3, iclass 14, count 0 2006.175.07:38:23.90#ibcon#read 3, iclass 14, count 0 2006.175.07:38:23.90#ibcon#about to read 4, iclass 14, count 0 2006.175.07:38:23.90#ibcon#read 4, iclass 14, count 0 2006.175.07:38:23.90#ibcon#about to read 5, iclass 14, count 0 2006.175.07:38:23.90#ibcon#read 5, iclass 14, count 0 2006.175.07:38:23.90#ibcon#about to read 6, iclass 14, count 0 2006.175.07:38:23.90#ibcon#read 6, iclass 14, count 0 2006.175.07:38:23.90#ibcon#end of sib2, iclass 14, count 0 2006.175.07:38:23.90#ibcon#*after write, iclass 14, count 0 2006.175.07:38:23.90#ibcon#*before return 0, iclass 14, count 0 2006.175.07:38:23.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:38:23.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:38:23.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:38:23.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:38:23.90$vc4f8/vblo=2,640.99 2006.175.07:38:23.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.07:38:23.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.07:38:23.90#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:23.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:23.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:23.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:23.90#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:38:23.90#ibcon#first serial, iclass 16, count 0 2006.175.07:38:23.90#ibcon#enter sib2, iclass 16, count 0 2006.175.07:38:23.90#ibcon#flushed, iclass 16, count 0 2006.175.07:38:23.90#ibcon#about to write, iclass 16, count 0 2006.175.07:38:23.90#ibcon#wrote, iclass 16, count 0 2006.175.07:38:23.90#ibcon#about to read 3, iclass 16, count 0 2006.175.07:38:23.92#ibcon#read 3, iclass 16, count 0 2006.175.07:38:23.92#ibcon#about to read 4, iclass 16, count 0 2006.175.07:38:23.92#ibcon#read 4, iclass 16, count 0 2006.175.07:38:23.92#ibcon#about to read 5, iclass 16, count 0 2006.175.07:38:23.92#ibcon#read 5, iclass 16, count 0 2006.175.07:38:23.92#ibcon#about to read 6, iclass 16, count 0 2006.175.07:38:23.92#ibcon#read 6, iclass 16, count 0 2006.175.07:38:23.92#ibcon#end of sib2, iclass 16, count 0 2006.175.07:38:23.92#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:38:23.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:38:23.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:38:23.92#ibcon#*before write, iclass 16, count 0 2006.175.07:38:23.92#ibcon#enter sib2, iclass 16, count 0 2006.175.07:38:23.92#ibcon#flushed, iclass 16, count 0 2006.175.07:38:23.92#ibcon#about to write, iclass 16, count 0 2006.175.07:38:23.92#ibcon#wrote, iclass 16, count 0 2006.175.07:38:23.92#ibcon#about to read 3, iclass 16, count 0 2006.175.07:38:23.96#ibcon#read 3, iclass 16, count 0 2006.175.07:38:23.96#ibcon#about to read 4, iclass 16, count 0 2006.175.07:38:23.96#ibcon#read 4, iclass 16, count 0 2006.175.07:38:23.96#ibcon#about to read 5, iclass 16, count 0 2006.175.07:38:23.96#ibcon#read 5, iclass 16, count 0 2006.175.07:38:23.96#ibcon#about to read 6, iclass 16, count 0 2006.175.07:38:23.96#ibcon#read 6, iclass 16, count 0 2006.175.07:38:23.96#ibcon#end of sib2, iclass 16, count 0 2006.175.07:38:23.96#ibcon#*after write, iclass 16, count 0 2006.175.07:38:23.96#ibcon#*before return 0, iclass 16, count 0 2006.175.07:38:23.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:23.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:38:23.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:38:23.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:38:23.96$vc4f8/vb=2,4 2006.175.07:38:23.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.07:38:23.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.07:38:23.96#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:23.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:24.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:24.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:24.02#ibcon#enter wrdev, iclass 18, count 2 2006.175.07:38:24.02#ibcon#first serial, iclass 18, count 2 2006.175.07:38:24.02#ibcon#enter sib2, iclass 18, count 2 2006.175.07:38:24.02#ibcon#flushed, iclass 18, count 2 2006.175.07:38:24.02#ibcon#about to write, iclass 18, count 2 2006.175.07:38:24.02#ibcon#wrote, iclass 18, count 2 2006.175.07:38:24.02#ibcon#about to read 3, iclass 18, count 2 2006.175.07:38:24.04#ibcon#read 3, iclass 18, count 2 2006.175.07:38:24.04#ibcon#about to read 4, iclass 18, count 2 2006.175.07:38:24.04#ibcon#read 4, iclass 18, count 2 2006.175.07:38:24.04#ibcon#about to read 5, iclass 18, count 2 2006.175.07:38:24.04#ibcon#read 5, iclass 18, count 2 2006.175.07:38:24.04#ibcon#about to read 6, iclass 18, count 2 2006.175.07:38:24.04#ibcon#read 6, iclass 18, count 2 2006.175.07:38:24.04#ibcon#end of sib2, iclass 18, count 2 2006.175.07:38:24.04#ibcon#*mode == 0, iclass 18, count 2 2006.175.07:38:24.04#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.07:38:24.04#ibcon#[27=AT02-04\r\n] 2006.175.07:38:24.04#ibcon#*before write, iclass 18, count 2 2006.175.07:38:24.04#ibcon#enter sib2, iclass 18, count 2 2006.175.07:38:24.04#ibcon#flushed, iclass 18, count 2 2006.175.07:38:24.04#ibcon#about to write, iclass 18, count 2 2006.175.07:38:24.04#ibcon#wrote, iclass 18, count 2 2006.175.07:38:24.04#ibcon#about to read 3, iclass 18, count 2 2006.175.07:38:24.07#ibcon#read 3, iclass 18, count 2 2006.175.07:38:24.07#ibcon#about to read 4, iclass 18, count 2 2006.175.07:38:24.07#ibcon#read 4, iclass 18, count 2 2006.175.07:38:24.07#ibcon#about to read 5, iclass 18, count 2 2006.175.07:38:24.07#ibcon#read 5, iclass 18, count 2 2006.175.07:38:24.07#ibcon#about to read 6, iclass 18, count 2 2006.175.07:38:24.07#ibcon#read 6, iclass 18, count 2 2006.175.07:38:24.07#ibcon#end of sib2, iclass 18, count 2 2006.175.07:38:24.07#ibcon#*after write, iclass 18, count 2 2006.175.07:38:24.07#ibcon#*before return 0, iclass 18, count 2 2006.175.07:38:24.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:24.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:38:24.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.07:38:24.07#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:24.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:24.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:24.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:24.19#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:38:24.19#ibcon#first serial, iclass 18, count 0 2006.175.07:38:24.19#ibcon#enter sib2, iclass 18, count 0 2006.175.07:38:24.19#ibcon#flushed, iclass 18, count 0 2006.175.07:38:24.19#ibcon#about to write, iclass 18, count 0 2006.175.07:38:24.19#ibcon#wrote, iclass 18, count 0 2006.175.07:38:24.19#ibcon#about to read 3, iclass 18, count 0 2006.175.07:38:24.21#ibcon#read 3, iclass 18, count 0 2006.175.07:38:24.21#ibcon#about to read 4, iclass 18, count 0 2006.175.07:38:24.21#ibcon#read 4, iclass 18, count 0 2006.175.07:38:24.21#ibcon#about to read 5, iclass 18, count 0 2006.175.07:38:24.21#ibcon#read 5, iclass 18, count 0 2006.175.07:38:24.21#ibcon#about to read 6, iclass 18, count 0 2006.175.07:38:24.21#ibcon#read 6, iclass 18, count 0 2006.175.07:38:24.21#ibcon#end of sib2, iclass 18, count 0 2006.175.07:38:24.21#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:38:24.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:38:24.21#ibcon#[27=USB\r\n] 2006.175.07:38:24.21#ibcon#*before write, iclass 18, count 0 2006.175.07:38:24.21#ibcon#enter sib2, iclass 18, count 0 2006.175.07:38:24.21#ibcon#flushed, iclass 18, count 0 2006.175.07:38:24.21#ibcon#about to write, iclass 18, count 0 2006.175.07:38:24.21#ibcon#wrote, iclass 18, count 0 2006.175.07:38:24.21#ibcon#about to read 3, iclass 18, count 0 2006.175.07:38:24.24#ibcon#read 3, iclass 18, count 0 2006.175.07:38:24.24#ibcon#about to read 4, iclass 18, count 0 2006.175.07:38:24.24#ibcon#read 4, iclass 18, count 0 2006.175.07:38:24.24#ibcon#about to read 5, iclass 18, count 0 2006.175.07:38:24.24#ibcon#read 5, iclass 18, count 0 2006.175.07:38:24.24#ibcon#about to read 6, iclass 18, count 0 2006.175.07:38:24.24#ibcon#read 6, iclass 18, count 0 2006.175.07:38:24.24#ibcon#end of sib2, iclass 18, count 0 2006.175.07:38:24.24#ibcon#*after write, iclass 18, count 0 2006.175.07:38:24.24#ibcon#*before return 0, iclass 18, count 0 2006.175.07:38:24.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:24.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:38:24.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:38:24.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:38:24.24$vc4f8/vblo=3,656.99 2006.175.07:38:24.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.07:38:24.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.07:38:24.24#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:24.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:24.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:24.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:24.24#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:38:24.24#ibcon#first serial, iclass 20, count 0 2006.175.07:38:24.24#ibcon#enter sib2, iclass 20, count 0 2006.175.07:38:24.24#ibcon#flushed, iclass 20, count 0 2006.175.07:38:24.24#ibcon#about to write, iclass 20, count 0 2006.175.07:38:24.24#ibcon#wrote, iclass 20, count 0 2006.175.07:38:24.24#ibcon#about to read 3, iclass 20, count 0 2006.175.07:38:24.26#ibcon#read 3, iclass 20, count 0 2006.175.07:38:24.26#ibcon#about to read 4, iclass 20, count 0 2006.175.07:38:24.26#ibcon#read 4, iclass 20, count 0 2006.175.07:38:24.26#ibcon#about to read 5, iclass 20, count 0 2006.175.07:38:24.26#ibcon#read 5, iclass 20, count 0 2006.175.07:38:24.26#ibcon#about to read 6, iclass 20, count 0 2006.175.07:38:24.26#ibcon#read 6, iclass 20, count 0 2006.175.07:38:24.26#ibcon#end of sib2, iclass 20, count 0 2006.175.07:38:24.26#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:38:24.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:38:24.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:38:24.26#ibcon#*before write, iclass 20, count 0 2006.175.07:38:24.26#ibcon#enter sib2, iclass 20, count 0 2006.175.07:38:24.26#ibcon#flushed, iclass 20, count 0 2006.175.07:38:24.26#ibcon#about to write, iclass 20, count 0 2006.175.07:38:24.26#ibcon#wrote, iclass 20, count 0 2006.175.07:38:24.26#ibcon#about to read 3, iclass 20, count 0 2006.175.07:38:24.30#ibcon#read 3, iclass 20, count 0 2006.175.07:38:24.30#ibcon#about to read 4, iclass 20, count 0 2006.175.07:38:24.30#ibcon#read 4, iclass 20, count 0 2006.175.07:38:24.30#ibcon#about to read 5, iclass 20, count 0 2006.175.07:38:24.30#ibcon#read 5, iclass 20, count 0 2006.175.07:38:24.30#ibcon#about to read 6, iclass 20, count 0 2006.175.07:38:24.30#ibcon#read 6, iclass 20, count 0 2006.175.07:38:24.30#ibcon#end of sib2, iclass 20, count 0 2006.175.07:38:24.30#ibcon#*after write, iclass 20, count 0 2006.175.07:38:24.30#ibcon#*before return 0, iclass 20, count 0 2006.175.07:38:24.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:24.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:38:24.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:38:24.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:38:24.30$vc4f8/vb=3,4 2006.175.07:38:24.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.07:38:24.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.07:38:24.30#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:24.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:24.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:24.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:24.36#ibcon#enter wrdev, iclass 22, count 2 2006.175.07:38:24.36#ibcon#first serial, iclass 22, count 2 2006.175.07:38:24.36#ibcon#enter sib2, iclass 22, count 2 2006.175.07:38:24.36#ibcon#flushed, iclass 22, count 2 2006.175.07:38:24.36#ibcon#about to write, iclass 22, count 2 2006.175.07:38:24.36#ibcon#wrote, iclass 22, count 2 2006.175.07:38:24.36#ibcon#about to read 3, iclass 22, count 2 2006.175.07:38:24.38#ibcon#read 3, iclass 22, count 2 2006.175.07:38:24.38#ibcon#about to read 4, iclass 22, count 2 2006.175.07:38:24.38#ibcon#read 4, iclass 22, count 2 2006.175.07:38:24.38#ibcon#about to read 5, iclass 22, count 2 2006.175.07:38:24.38#ibcon#read 5, iclass 22, count 2 2006.175.07:38:24.38#ibcon#about to read 6, iclass 22, count 2 2006.175.07:38:24.38#ibcon#read 6, iclass 22, count 2 2006.175.07:38:24.38#ibcon#end of sib2, iclass 22, count 2 2006.175.07:38:24.38#ibcon#*mode == 0, iclass 22, count 2 2006.175.07:38:24.38#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.07:38:24.38#ibcon#[27=AT03-04\r\n] 2006.175.07:38:24.38#ibcon#*before write, iclass 22, count 2 2006.175.07:38:24.38#ibcon#enter sib2, iclass 22, count 2 2006.175.07:38:24.38#ibcon#flushed, iclass 22, count 2 2006.175.07:38:24.38#ibcon#about to write, iclass 22, count 2 2006.175.07:38:24.38#ibcon#wrote, iclass 22, count 2 2006.175.07:38:24.38#ibcon#about to read 3, iclass 22, count 2 2006.175.07:38:24.41#ibcon#read 3, iclass 22, count 2 2006.175.07:38:24.41#ibcon#about to read 4, iclass 22, count 2 2006.175.07:38:24.41#ibcon#read 4, iclass 22, count 2 2006.175.07:38:24.41#ibcon#about to read 5, iclass 22, count 2 2006.175.07:38:24.41#ibcon#read 5, iclass 22, count 2 2006.175.07:38:24.41#ibcon#about to read 6, iclass 22, count 2 2006.175.07:38:24.41#ibcon#read 6, iclass 22, count 2 2006.175.07:38:24.41#ibcon#end of sib2, iclass 22, count 2 2006.175.07:38:24.41#ibcon#*after write, iclass 22, count 2 2006.175.07:38:24.41#ibcon#*before return 0, iclass 22, count 2 2006.175.07:38:24.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:24.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:38:24.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.07:38:24.41#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:24.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:24.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:24.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:24.53#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:38:24.53#ibcon#first serial, iclass 22, count 0 2006.175.07:38:24.53#ibcon#enter sib2, iclass 22, count 0 2006.175.07:38:24.53#ibcon#flushed, iclass 22, count 0 2006.175.07:38:24.53#ibcon#about to write, iclass 22, count 0 2006.175.07:38:24.53#ibcon#wrote, iclass 22, count 0 2006.175.07:38:24.53#ibcon#about to read 3, iclass 22, count 0 2006.175.07:38:24.55#ibcon#read 3, iclass 22, count 0 2006.175.07:38:24.55#ibcon#about to read 4, iclass 22, count 0 2006.175.07:38:24.55#ibcon#read 4, iclass 22, count 0 2006.175.07:38:24.55#ibcon#about to read 5, iclass 22, count 0 2006.175.07:38:24.55#ibcon#read 5, iclass 22, count 0 2006.175.07:38:24.55#ibcon#about to read 6, iclass 22, count 0 2006.175.07:38:24.55#ibcon#read 6, iclass 22, count 0 2006.175.07:38:24.55#ibcon#end of sib2, iclass 22, count 0 2006.175.07:38:24.55#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:38:24.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:38:24.55#ibcon#[27=USB\r\n] 2006.175.07:38:24.55#ibcon#*before write, iclass 22, count 0 2006.175.07:38:24.55#ibcon#enter sib2, iclass 22, count 0 2006.175.07:38:24.55#ibcon#flushed, iclass 22, count 0 2006.175.07:38:24.55#ibcon#about to write, iclass 22, count 0 2006.175.07:38:24.55#ibcon#wrote, iclass 22, count 0 2006.175.07:38:24.55#ibcon#about to read 3, iclass 22, count 0 2006.175.07:38:24.58#ibcon#read 3, iclass 22, count 0 2006.175.07:38:24.58#ibcon#about to read 4, iclass 22, count 0 2006.175.07:38:24.58#ibcon#read 4, iclass 22, count 0 2006.175.07:38:24.58#ibcon#about to read 5, iclass 22, count 0 2006.175.07:38:24.58#ibcon#read 5, iclass 22, count 0 2006.175.07:38:24.58#ibcon#about to read 6, iclass 22, count 0 2006.175.07:38:24.58#ibcon#read 6, iclass 22, count 0 2006.175.07:38:24.58#ibcon#end of sib2, iclass 22, count 0 2006.175.07:38:24.58#ibcon#*after write, iclass 22, count 0 2006.175.07:38:24.58#ibcon#*before return 0, iclass 22, count 0 2006.175.07:38:24.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:24.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:38:24.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:38:24.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:38:24.58$vc4f8/vblo=4,712.99 2006.175.07:38:24.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.07:38:24.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.07:38:24.58#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:24.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:24.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:24.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:24.58#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:38:24.58#ibcon#first serial, iclass 24, count 0 2006.175.07:38:24.58#ibcon#enter sib2, iclass 24, count 0 2006.175.07:38:24.58#ibcon#flushed, iclass 24, count 0 2006.175.07:38:24.58#ibcon#about to write, iclass 24, count 0 2006.175.07:38:24.58#ibcon#wrote, iclass 24, count 0 2006.175.07:38:24.58#ibcon#about to read 3, iclass 24, count 0 2006.175.07:38:24.60#ibcon#read 3, iclass 24, count 0 2006.175.07:38:24.60#ibcon#about to read 4, iclass 24, count 0 2006.175.07:38:24.60#ibcon#read 4, iclass 24, count 0 2006.175.07:38:24.60#ibcon#about to read 5, iclass 24, count 0 2006.175.07:38:24.60#ibcon#read 5, iclass 24, count 0 2006.175.07:38:24.60#ibcon#about to read 6, iclass 24, count 0 2006.175.07:38:24.60#ibcon#read 6, iclass 24, count 0 2006.175.07:38:24.60#ibcon#end of sib2, iclass 24, count 0 2006.175.07:38:24.60#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:38:24.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:38:24.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:38:24.60#ibcon#*before write, iclass 24, count 0 2006.175.07:38:24.60#ibcon#enter sib2, iclass 24, count 0 2006.175.07:38:24.60#ibcon#flushed, iclass 24, count 0 2006.175.07:38:24.60#ibcon#about to write, iclass 24, count 0 2006.175.07:38:24.60#ibcon#wrote, iclass 24, count 0 2006.175.07:38:24.60#ibcon#about to read 3, iclass 24, count 0 2006.175.07:38:24.64#ibcon#read 3, iclass 24, count 0 2006.175.07:38:24.64#ibcon#about to read 4, iclass 24, count 0 2006.175.07:38:24.64#ibcon#read 4, iclass 24, count 0 2006.175.07:38:24.64#ibcon#about to read 5, iclass 24, count 0 2006.175.07:38:24.64#ibcon#read 5, iclass 24, count 0 2006.175.07:38:24.64#ibcon#about to read 6, iclass 24, count 0 2006.175.07:38:24.64#ibcon#read 6, iclass 24, count 0 2006.175.07:38:24.64#ibcon#end of sib2, iclass 24, count 0 2006.175.07:38:24.64#ibcon#*after write, iclass 24, count 0 2006.175.07:38:24.64#ibcon#*before return 0, iclass 24, count 0 2006.175.07:38:24.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:24.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:38:24.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:38:24.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:38:24.64$vc4f8/vb=4,4 2006.175.07:38:24.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.07:38:24.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.07:38:24.64#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:24.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:24.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:24.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:24.70#ibcon#enter wrdev, iclass 26, count 2 2006.175.07:38:24.70#ibcon#first serial, iclass 26, count 2 2006.175.07:38:24.70#ibcon#enter sib2, iclass 26, count 2 2006.175.07:38:24.70#ibcon#flushed, iclass 26, count 2 2006.175.07:38:24.70#ibcon#about to write, iclass 26, count 2 2006.175.07:38:24.70#ibcon#wrote, iclass 26, count 2 2006.175.07:38:24.70#ibcon#about to read 3, iclass 26, count 2 2006.175.07:38:24.72#ibcon#read 3, iclass 26, count 2 2006.175.07:38:24.72#ibcon#about to read 4, iclass 26, count 2 2006.175.07:38:24.72#ibcon#read 4, iclass 26, count 2 2006.175.07:38:24.72#ibcon#about to read 5, iclass 26, count 2 2006.175.07:38:24.72#ibcon#read 5, iclass 26, count 2 2006.175.07:38:24.72#ibcon#about to read 6, iclass 26, count 2 2006.175.07:38:24.72#ibcon#read 6, iclass 26, count 2 2006.175.07:38:24.72#ibcon#end of sib2, iclass 26, count 2 2006.175.07:38:24.72#ibcon#*mode == 0, iclass 26, count 2 2006.175.07:38:24.72#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.07:38:24.72#ibcon#[27=AT04-04\r\n] 2006.175.07:38:24.72#ibcon#*before write, iclass 26, count 2 2006.175.07:38:24.72#ibcon#enter sib2, iclass 26, count 2 2006.175.07:38:24.72#ibcon#flushed, iclass 26, count 2 2006.175.07:38:24.72#ibcon#about to write, iclass 26, count 2 2006.175.07:38:24.72#ibcon#wrote, iclass 26, count 2 2006.175.07:38:24.72#ibcon#about to read 3, iclass 26, count 2 2006.175.07:38:24.75#ibcon#read 3, iclass 26, count 2 2006.175.07:38:24.75#ibcon#about to read 4, iclass 26, count 2 2006.175.07:38:24.75#ibcon#read 4, iclass 26, count 2 2006.175.07:38:24.75#ibcon#about to read 5, iclass 26, count 2 2006.175.07:38:24.75#ibcon#read 5, iclass 26, count 2 2006.175.07:38:24.75#ibcon#about to read 6, iclass 26, count 2 2006.175.07:38:24.75#ibcon#read 6, iclass 26, count 2 2006.175.07:38:24.75#ibcon#end of sib2, iclass 26, count 2 2006.175.07:38:24.75#ibcon#*after write, iclass 26, count 2 2006.175.07:38:24.75#ibcon#*before return 0, iclass 26, count 2 2006.175.07:38:24.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:24.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:38:24.75#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.07:38:24.75#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:24.75#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:24.87#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:24.87#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:24.87#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:38:24.87#ibcon#first serial, iclass 26, count 0 2006.175.07:38:24.87#ibcon#enter sib2, iclass 26, count 0 2006.175.07:38:24.87#ibcon#flushed, iclass 26, count 0 2006.175.07:38:24.87#ibcon#about to write, iclass 26, count 0 2006.175.07:38:24.87#ibcon#wrote, iclass 26, count 0 2006.175.07:38:24.87#ibcon#about to read 3, iclass 26, count 0 2006.175.07:38:24.89#ibcon#read 3, iclass 26, count 0 2006.175.07:38:24.89#ibcon#about to read 4, iclass 26, count 0 2006.175.07:38:24.89#ibcon#read 4, iclass 26, count 0 2006.175.07:38:24.89#ibcon#about to read 5, iclass 26, count 0 2006.175.07:38:24.89#ibcon#read 5, iclass 26, count 0 2006.175.07:38:24.89#ibcon#about to read 6, iclass 26, count 0 2006.175.07:38:24.89#ibcon#read 6, iclass 26, count 0 2006.175.07:38:24.89#ibcon#end of sib2, iclass 26, count 0 2006.175.07:38:24.89#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:38:24.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:38:24.89#ibcon#[27=USB\r\n] 2006.175.07:38:24.89#ibcon#*before write, iclass 26, count 0 2006.175.07:38:24.89#ibcon#enter sib2, iclass 26, count 0 2006.175.07:38:24.89#ibcon#flushed, iclass 26, count 0 2006.175.07:38:24.89#ibcon#about to write, iclass 26, count 0 2006.175.07:38:24.89#ibcon#wrote, iclass 26, count 0 2006.175.07:38:24.89#ibcon#about to read 3, iclass 26, count 0 2006.175.07:38:24.92#ibcon#read 3, iclass 26, count 0 2006.175.07:38:24.92#ibcon#about to read 4, iclass 26, count 0 2006.175.07:38:24.92#ibcon#read 4, iclass 26, count 0 2006.175.07:38:24.92#ibcon#about to read 5, iclass 26, count 0 2006.175.07:38:24.92#ibcon#read 5, iclass 26, count 0 2006.175.07:38:24.92#ibcon#about to read 6, iclass 26, count 0 2006.175.07:38:24.92#ibcon#read 6, iclass 26, count 0 2006.175.07:38:24.92#ibcon#end of sib2, iclass 26, count 0 2006.175.07:38:24.92#ibcon#*after write, iclass 26, count 0 2006.175.07:38:24.92#ibcon#*before return 0, iclass 26, count 0 2006.175.07:38:24.92#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:24.92#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:38:24.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:38:24.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:38:24.92$vc4f8/vblo=5,744.99 2006.175.07:38:24.92#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.07:38:24.92#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.07:38:24.92#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:24.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:24.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:24.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:24.92#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:38:24.92#ibcon#first serial, iclass 28, count 0 2006.175.07:38:24.92#ibcon#enter sib2, iclass 28, count 0 2006.175.07:38:24.92#ibcon#flushed, iclass 28, count 0 2006.175.07:38:24.92#ibcon#about to write, iclass 28, count 0 2006.175.07:38:24.92#ibcon#wrote, iclass 28, count 0 2006.175.07:38:24.92#ibcon#about to read 3, iclass 28, count 0 2006.175.07:38:24.94#ibcon#read 3, iclass 28, count 0 2006.175.07:38:24.94#ibcon#about to read 4, iclass 28, count 0 2006.175.07:38:24.94#ibcon#read 4, iclass 28, count 0 2006.175.07:38:24.94#ibcon#about to read 5, iclass 28, count 0 2006.175.07:38:24.94#ibcon#read 5, iclass 28, count 0 2006.175.07:38:24.94#ibcon#about to read 6, iclass 28, count 0 2006.175.07:38:24.94#ibcon#read 6, iclass 28, count 0 2006.175.07:38:24.94#ibcon#end of sib2, iclass 28, count 0 2006.175.07:38:24.94#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:38:24.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:38:24.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:38:24.94#ibcon#*before write, iclass 28, count 0 2006.175.07:38:24.94#ibcon#enter sib2, iclass 28, count 0 2006.175.07:38:24.94#ibcon#flushed, iclass 28, count 0 2006.175.07:38:24.94#ibcon#about to write, iclass 28, count 0 2006.175.07:38:24.94#ibcon#wrote, iclass 28, count 0 2006.175.07:38:24.94#ibcon#about to read 3, iclass 28, count 0 2006.175.07:38:24.98#ibcon#read 3, iclass 28, count 0 2006.175.07:38:24.98#ibcon#about to read 4, iclass 28, count 0 2006.175.07:38:24.98#ibcon#read 4, iclass 28, count 0 2006.175.07:38:24.98#ibcon#about to read 5, iclass 28, count 0 2006.175.07:38:24.98#ibcon#read 5, iclass 28, count 0 2006.175.07:38:24.98#ibcon#about to read 6, iclass 28, count 0 2006.175.07:38:24.98#ibcon#read 6, iclass 28, count 0 2006.175.07:38:24.98#ibcon#end of sib2, iclass 28, count 0 2006.175.07:38:24.98#ibcon#*after write, iclass 28, count 0 2006.175.07:38:24.98#ibcon#*before return 0, iclass 28, count 0 2006.175.07:38:24.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:24.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:38:24.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:38:24.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:38:24.98$vc4f8/vb=5,4 2006.175.07:38:24.98#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.07:38:24.98#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.07:38:24.98#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:24.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:25.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:25.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:25.04#ibcon#enter wrdev, iclass 30, count 2 2006.175.07:38:25.04#ibcon#first serial, iclass 30, count 2 2006.175.07:38:25.04#ibcon#enter sib2, iclass 30, count 2 2006.175.07:38:25.04#ibcon#flushed, iclass 30, count 2 2006.175.07:38:25.04#ibcon#about to write, iclass 30, count 2 2006.175.07:38:25.04#ibcon#wrote, iclass 30, count 2 2006.175.07:38:25.04#ibcon#about to read 3, iclass 30, count 2 2006.175.07:38:25.06#ibcon#read 3, iclass 30, count 2 2006.175.07:38:25.06#ibcon#about to read 4, iclass 30, count 2 2006.175.07:38:25.06#ibcon#read 4, iclass 30, count 2 2006.175.07:38:25.06#ibcon#about to read 5, iclass 30, count 2 2006.175.07:38:25.06#ibcon#read 5, iclass 30, count 2 2006.175.07:38:25.06#ibcon#about to read 6, iclass 30, count 2 2006.175.07:38:25.06#ibcon#read 6, iclass 30, count 2 2006.175.07:38:25.06#ibcon#end of sib2, iclass 30, count 2 2006.175.07:38:25.06#ibcon#*mode == 0, iclass 30, count 2 2006.175.07:38:25.06#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.07:38:25.06#ibcon#[27=AT05-04\r\n] 2006.175.07:38:25.06#ibcon#*before write, iclass 30, count 2 2006.175.07:38:25.06#ibcon#enter sib2, iclass 30, count 2 2006.175.07:38:25.06#ibcon#flushed, iclass 30, count 2 2006.175.07:38:25.06#ibcon#about to write, iclass 30, count 2 2006.175.07:38:25.06#ibcon#wrote, iclass 30, count 2 2006.175.07:38:25.06#ibcon#about to read 3, iclass 30, count 2 2006.175.07:38:25.09#ibcon#read 3, iclass 30, count 2 2006.175.07:38:25.09#ibcon#about to read 4, iclass 30, count 2 2006.175.07:38:25.09#ibcon#read 4, iclass 30, count 2 2006.175.07:38:25.09#ibcon#about to read 5, iclass 30, count 2 2006.175.07:38:25.09#ibcon#read 5, iclass 30, count 2 2006.175.07:38:25.09#ibcon#about to read 6, iclass 30, count 2 2006.175.07:38:25.09#ibcon#read 6, iclass 30, count 2 2006.175.07:38:25.09#ibcon#end of sib2, iclass 30, count 2 2006.175.07:38:25.09#ibcon#*after write, iclass 30, count 2 2006.175.07:38:25.09#ibcon#*before return 0, iclass 30, count 2 2006.175.07:38:25.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:25.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:38:25.09#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.07:38:25.09#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:25.09#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:25.21#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:25.21#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:25.21#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:38:25.21#ibcon#first serial, iclass 30, count 0 2006.175.07:38:25.21#ibcon#enter sib2, iclass 30, count 0 2006.175.07:38:25.21#ibcon#flushed, iclass 30, count 0 2006.175.07:38:25.21#ibcon#about to write, iclass 30, count 0 2006.175.07:38:25.21#ibcon#wrote, iclass 30, count 0 2006.175.07:38:25.21#ibcon#about to read 3, iclass 30, count 0 2006.175.07:38:25.23#ibcon#read 3, iclass 30, count 0 2006.175.07:38:25.23#ibcon#about to read 4, iclass 30, count 0 2006.175.07:38:25.23#ibcon#read 4, iclass 30, count 0 2006.175.07:38:25.23#ibcon#about to read 5, iclass 30, count 0 2006.175.07:38:25.23#ibcon#read 5, iclass 30, count 0 2006.175.07:38:25.23#ibcon#about to read 6, iclass 30, count 0 2006.175.07:38:25.23#ibcon#read 6, iclass 30, count 0 2006.175.07:38:25.23#ibcon#end of sib2, iclass 30, count 0 2006.175.07:38:25.23#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:38:25.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:38:25.23#ibcon#[27=USB\r\n] 2006.175.07:38:25.23#ibcon#*before write, iclass 30, count 0 2006.175.07:38:25.23#ibcon#enter sib2, iclass 30, count 0 2006.175.07:38:25.23#ibcon#flushed, iclass 30, count 0 2006.175.07:38:25.23#ibcon#about to write, iclass 30, count 0 2006.175.07:38:25.23#ibcon#wrote, iclass 30, count 0 2006.175.07:38:25.23#ibcon#about to read 3, iclass 30, count 0 2006.175.07:38:25.26#ibcon#read 3, iclass 30, count 0 2006.175.07:38:25.26#ibcon#about to read 4, iclass 30, count 0 2006.175.07:38:25.26#ibcon#read 4, iclass 30, count 0 2006.175.07:38:25.26#ibcon#about to read 5, iclass 30, count 0 2006.175.07:38:25.26#ibcon#read 5, iclass 30, count 0 2006.175.07:38:25.26#ibcon#about to read 6, iclass 30, count 0 2006.175.07:38:25.26#ibcon#read 6, iclass 30, count 0 2006.175.07:38:25.26#ibcon#end of sib2, iclass 30, count 0 2006.175.07:38:25.26#ibcon#*after write, iclass 30, count 0 2006.175.07:38:25.26#ibcon#*before return 0, iclass 30, count 0 2006.175.07:38:25.26#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:25.26#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:38:25.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:38:25.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:38:25.26$vc4f8/vblo=6,752.99 2006.175.07:38:25.26#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.07:38:25.26#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.07:38:25.26#ibcon#ireg 17 cls_cnt 0 2006.175.07:38:25.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:25.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:25.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:25.26#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:38:25.26#ibcon#first serial, iclass 32, count 0 2006.175.07:38:25.26#ibcon#enter sib2, iclass 32, count 0 2006.175.07:38:25.26#ibcon#flushed, iclass 32, count 0 2006.175.07:38:25.26#ibcon#about to write, iclass 32, count 0 2006.175.07:38:25.26#ibcon#wrote, iclass 32, count 0 2006.175.07:38:25.26#ibcon#about to read 3, iclass 32, count 0 2006.175.07:38:25.28#ibcon#read 3, iclass 32, count 0 2006.175.07:38:25.28#ibcon#about to read 4, iclass 32, count 0 2006.175.07:38:25.28#ibcon#read 4, iclass 32, count 0 2006.175.07:38:25.28#ibcon#about to read 5, iclass 32, count 0 2006.175.07:38:25.28#ibcon#read 5, iclass 32, count 0 2006.175.07:38:25.28#ibcon#about to read 6, iclass 32, count 0 2006.175.07:38:25.28#ibcon#read 6, iclass 32, count 0 2006.175.07:38:25.28#ibcon#end of sib2, iclass 32, count 0 2006.175.07:38:25.28#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:38:25.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:38:25.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:38:25.28#ibcon#*before write, iclass 32, count 0 2006.175.07:38:25.28#ibcon#enter sib2, iclass 32, count 0 2006.175.07:38:25.28#ibcon#flushed, iclass 32, count 0 2006.175.07:38:25.28#ibcon#about to write, iclass 32, count 0 2006.175.07:38:25.28#ibcon#wrote, iclass 32, count 0 2006.175.07:38:25.28#ibcon#about to read 3, iclass 32, count 0 2006.175.07:38:25.32#ibcon#read 3, iclass 32, count 0 2006.175.07:38:25.32#ibcon#about to read 4, iclass 32, count 0 2006.175.07:38:25.32#ibcon#read 4, iclass 32, count 0 2006.175.07:38:25.32#ibcon#about to read 5, iclass 32, count 0 2006.175.07:38:25.32#ibcon#read 5, iclass 32, count 0 2006.175.07:38:25.32#ibcon#about to read 6, iclass 32, count 0 2006.175.07:38:25.32#ibcon#read 6, iclass 32, count 0 2006.175.07:38:25.32#ibcon#end of sib2, iclass 32, count 0 2006.175.07:38:25.32#ibcon#*after write, iclass 32, count 0 2006.175.07:38:25.32#ibcon#*before return 0, iclass 32, count 0 2006.175.07:38:25.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:25.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:38:25.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:38:25.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:38:25.32$vc4f8/vb=6,4 2006.175.07:38:25.32#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.175.07:38:25.32#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.175.07:38:25.32#ibcon#ireg 11 cls_cnt 2 2006.175.07:38:25.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:25.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:25.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:25.38#ibcon#enter wrdev, iclass 34, count 2 2006.175.07:38:25.38#ibcon#first serial, iclass 34, count 2 2006.175.07:38:25.38#ibcon#enter sib2, iclass 34, count 2 2006.175.07:38:25.38#ibcon#flushed, iclass 34, count 2 2006.175.07:38:25.38#ibcon#about to write, iclass 34, count 2 2006.175.07:38:25.38#ibcon#wrote, iclass 34, count 2 2006.175.07:38:25.38#ibcon#about to read 3, iclass 34, count 2 2006.175.07:38:25.40#ibcon#read 3, iclass 34, count 2 2006.175.07:38:25.40#ibcon#about to read 4, iclass 34, count 2 2006.175.07:38:25.40#ibcon#read 4, iclass 34, count 2 2006.175.07:38:25.40#ibcon#about to read 5, iclass 34, count 2 2006.175.07:38:25.40#ibcon#read 5, iclass 34, count 2 2006.175.07:38:25.40#ibcon#about to read 6, iclass 34, count 2 2006.175.07:38:25.40#ibcon#read 6, iclass 34, count 2 2006.175.07:38:25.40#ibcon#end of sib2, iclass 34, count 2 2006.175.07:38:25.40#ibcon#*mode == 0, iclass 34, count 2 2006.175.07:38:25.40#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.175.07:38:25.40#ibcon#[27=AT06-04\r\n] 2006.175.07:38:25.40#ibcon#*before write, iclass 34, count 2 2006.175.07:38:25.40#ibcon#enter sib2, iclass 34, count 2 2006.175.07:38:25.40#ibcon#flushed, iclass 34, count 2 2006.175.07:38:25.40#ibcon#about to write, iclass 34, count 2 2006.175.07:38:25.40#ibcon#wrote, iclass 34, count 2 2006.175.07:38:25.40#ibcon#about to read 3, iclass 34, count 2 2006.175.07:38:25.43#ibcon#read 3, iclass 34, count 2 2006.175.07:38:25.43#ibcon#about to read 4, iclass 34, count 2 2006.175.07:38:25.43#ibcon#read 4, iclass 34, count 2 2006.175.07:38:25.43#ibcon#about to read 5, iclass 34, count 2 2006.175.07:38:25.43#ibcon#read 5, iclass 34, count 2 2006.175.07:38:25.43#ibcon#about to read 6, iclass 34, count 2 2006.175.07:38:25.43#ibcon#read 6, iclass 34, count 2 2006.175.07:38:25.43#ibcon#end of sib2, iclass 34, count 2 2006.175.07:38:25.43#ibcon#*after write, iclass 34, count 2 2006.175.07:38:25.43#ibcon#*before return 0, iclass 34, count 2 2006.175.07:38:25.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:25.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:38:25.43#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.175.07:38:25.43#ibcon#ireg 7 cls_cnt 0 2006.175.07:38:25.43#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:25.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:25.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:25.55#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:38:25.55#ibcon#first serial, iclass 34, count 0 2006.175.07:38:25.55#ibcon#enter sib2, iclass 34, count 0 2006.175.07:38:25.55#ibcon#flushed, iclass 34, count 0 2006.175.07:38:25.55#ibcon#about to write, iclass 34, count 0 2006.175.07:38:25.55#ibcon#wrote, iclass 34, count 0 2006.175.07:38:25.55#ibcon#about to read 3, iclass 34, count 0 2006.175.07:38:25.57#ibcon#read 3, iclass 34, count 0 2006.175.07:38:25.57#ibcon#about to read 4, iclass 34, count 0 2006.175.07:38:25.57#ibcon#read 4, iclass 34, count 0 2006.175.07:38:25.57#ibcon#about to read 5, iclass 34, count 0 2006.175.07:38:25.57#ibcon#read 5, iclass 34, count 0 2006.175.07:38:25.57#ibcon#about to read 6, iclass 34, count 0 2006.175.07:38:25.57#ibcon#read 6, iclass 34, count 0 2006.175.07:38:25.57#ibcon#end of sib2, iclass 34, count 0 2006.175.07:38:25.57#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:38:25.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:38:25.57#ibcon#[27=USB\r\n] 2006.175.07:38:25.57#ibcon#*before write, iclass 34, count 0 2006.175.07:38:25.57#ibcon#enter sib2, iclass 34, count 0 2006.175.07:38:25.57#ibcon#flushed, iclass 34, count 0 2006.175.07:38:25.57#ibcon#about to write, iclass 34, count 0 2006.175.07:38:25.57#ibcon#wrote, iclass 34, count 0 2006.175.07:38:25.57#ibcon#about to read 3, iclass 34, count 0 2006.175.07:38:25.60#ibcon#read 3, iclass 34, count 0 2006.175.07:38:25.60#ibcon#about to read 4, iclass 34, count 0 2006.175.07:38:25.60#ibcon#read 4, iclass 34, count 0 2006.175.07:38:25.60#ibcon#about to read 5, iclass 34, count 0 2006.175.07:38:25.60#ibcon#read 5, iclass 34, count 0 2006.175.07:38:25.60#ibcon#about to read 6, iclass 34, count 0 2006.175.07:38:25.60#ibcon#read 6, iclass 34, count 0 2006.175.07:38:25.60#ibcon#end of sib2, iclass 34, count 0 2006.175.07:38:25.60#ibcon#*after write, iclass 34, count 0 2006.175.07:38:25.60#ibcon#*before return 0, iclass 34, count 0 2006.175.07:38:25.60#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:25.60#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:38:25.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:38:25.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:38:25.60$vc4f8/vabw=wide 2006.175.07:38:25.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.07:38:25.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.07:38:25.60#ibcon#ireg 8 cls_cnt 0 2006.175.07:38:25.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:25.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:25.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:25.60#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:38:25.60#ibcon#first serial, iclass 36, count 0 2006.175.07:38:25.60#ibcon#enter sib2, iclass 36, count 0 2006.175.07:38:25.60#ibcon#flushed, iclass 36, count 0 2006.175.07:38:25.60#ibcon#about to write, iclass 36, count 0 2006.175.07:38:25.60#ibcon#wrote, iclass 36, count 0 2006.175.07:38:25.60#ibcon#about to read 3, iclass 36, count 0 2006.175.07:38:25.62#ibcon#read 3, iclass 36, count 0 2006.175.07:38:25.62#ibcon#about to read 4, iclass 36, count 0 2006.175.07:38:25.62#ibcon#read 4, iclass 36, count 0 2006.175.07:38:25.62#ibcon#about to read 5, iclass 36, count 0 2006.175.07:38:25.62#ibcon#read 5, iclass 36, count 0 2006.175.07:38:25.62#ibcon#about to read 6, iclass 36, count 0 2006.175.07:38:25.62#ibcon#read 6, iclass 36, count 0 2006.175.07:38:25.62#ibcon#end of sib2, iclass 36, count 0 2006.175.07:38:25.62#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:38:25.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:38:25.62#ibcon#[25=BW32\r\n] 2006.175.07:38:25.62#ibcon#*before write, iclass 36, count 0 2006.175.07:38:25.62#ibcon#enter sib2, iclass 36, count 0 2006.175.07:38:25.62#ibcon#flushed, iclass 36, count 0 2006.175.07:38:25.62#ibcon#about to write, iclass 36, count 0 2006.175.07:38:25.62#ibcon#wrote, iclass 36, count 0 2006.175.07:38:25.62#ibcon#about to read 3, iclass 36, count 0 2006.175.07:38:25.65#ibcon#read 3, iclass 36, count 0 2006.175.07:38:25.65#ibcon#about to read 4, iclass 36, count 0 2006.175.07:38:25.65#ibcon#read 4, iclass 36, count 0 2006.175.07:38:25.65#ibcon#about to read 5, iclass 36, count 0 2006.175.07:38:25.65#ibcon#read 5, iclass 36, count 0 2006.175.07:38:25.65#ibcon#about to read 6, iclass 36, count 0 2006.175.07:38:25.65#ibcon#read 6, iclass 36, count 0 2006.175.07:38:25.65#ibcon#end of sib2, iclass 36, count 0 2006.175.07:38:25.65#ibcon#*after write, iclass 36, count 0 2006.175.07:38:25.65#ibcon#*before return 0, iclass 36, count 0 2006.175.07:38:25.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:25.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:38:25.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:38:25.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:38:25.65$vc4f8/vbbw=wide 2006.175.07:38:25.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:38:25.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:38:25.65#ibcon#ireg 8 cls_cnt 0 2006.175.07:38:25.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:38:25.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:38:25.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:38:25.72#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:38:25.72#ibcon#first serial, iclass 38, count 0 2006.175.07:38:25.72#ibcon#enter sib2, iclass 38, count 0 2006.175.07:38:25.72#ibcon#flushed, iclass 38, count 0 2006.175.07:38:25.72#ibcon#about to write, iclass 38, count 0 2006.175.07:38:25.72#ibcon#wrote, iclass 38, count 0 2006.175.07:38:25.72#ibcon#about to read 3, iclass 38, count 0 2006.175.07:38:25.74#ibcon#read 3, iclass 38, count 0 2006.175.07:38:25.74#ibcon#about to read 4, iclass 38, count 0 2006.175.07:38:25.74#ibcon#read 4, iclass 38, count 0 2006.175.07:38:25.74#ibcon#about to read 5, iclass 38, count 0 2006.175.07:38:25.74#ibcon#read 5, iclass 38, count 0 2006.175.07:38:25.74#ibcon#about to read 6, iclass 38, count 0 2006.175.07:38:25.74#ibcon#read 6, iclass 38, count 0 2006.175.07:38:25.74#ibcon#end of sib2, iclass 38, count 0 2006.175.07:38:25.74#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:38:25.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:38:25.74#ibcon#[27=BW32\r\n] 2006.175.07:38:25.74#ibcon#*before write, iclass 38, count 0 2006.175.07:38:25.74#ibcon#enter sib2, iclass 38, count 0 2006.175.07:38:25.74#ibcon#flushed, iclass 38, count 0 2006.175.07:38:25.74#ibcon#about to write, iclass 38, count 0 2006.175.07:38:25.74#ibcon#wrote, iclass 38, count 0 2006.175.07:38:25.74#ibcon#about to read 3, iclass 38, count 0 2006.175.07:38:25.77#ibcon#read 3, iclass 38, count 0 2006.175.07:38:25.77#ibcon#about to read 4, iclass 38, count 0 2006.175.07:38:25.77#ibcon#read 4, iclass 38, count 0 2006.175.07:38:25.77#ibcon#about to read 5, iclass 38, count 0 2006.175.07:38:25.77#ibcon#read 5, iclass 38, count 0 2006.175.07:38:25.77#ibcon#about to read 6, iclass 38, count 0 2006.175.07:38:25.77#ibcon#read 6, iclass 38, count 0 2006.175.07:38:25.77#ibcon#end of sib2, iclass 38, count 0 2006.175.07:38:25.77#ibcon#*after write, iclass 38, count 0 2006.175.07:38:25.77#ibcon#*before return 0, iclass 38, count 0 2006.175.07:38:25.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:38:25.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:38:25.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:38:25.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:38:25.77$4f8m12a/ifd4f 2006.175.07:38:25.77$ifd4f/lo= 2006.175.07:38:25.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:38:25.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:38:25.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:38:25.77$ifd4f/patch= 2006.175.07:38:25.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:38:25.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:38:25.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:38:25.77$4f8m12a/"form=m,16.000,1:2 2006.175.07:38:25.77$4f8m12a/"tpicd 2006.175.07:38:25.77$4f8m12a/echo=off 2006.175.07:38:25.77$4f8m12a/xlog=off 2006.175.07:38:25.77:!2006.175.07:38:50 2006.175.07:38:32.14#trakl#Source acquired 2006.175.07:38:32.14#flagr#flagr/antenna,acquired 2006.175.07:38:50.00:preob 2006.175.07:38:51.14/onsource/TRACKING 2006.175.07:38:51.14:!2006.175.07:39:00 2006.175.07:39:00.00:data_valid=on 2006.175.07:39:00.00:midob 2006.175.07:39:00.14/onsource/TRACKING 2006.175.07:39:00.14/wx/25.96,1007.5,70 2006.175.07:39:00.21/cable/+6.4796E-03 2006.175.07:39:01.30/va/01,08,usb,yes,29,30 2006.175.07:39:01.30/va/02,07,usb,yes,29,30 2006.175.07:39:01.30/va/03,06,usb,yes,30,31 2006.175.07:39:01.30/va/04,07,usb,yes,30,32 2006.175.07:39:01.30/va/05,07,usb,yes,30,32 2006.175.07:39:01.30/va/06,06,usb,yes,29,29 2006.175.07:39:01.30/va/07,06,usb,yes,29,29 2006.175.07:39:01.30/va/08,06,usb,yes,32,31 2006.175.07:39:01.53/valo/01,532.99,yes,locked 2006.175.07:39:01.53/valo/02,572.99,yes,locked 2006.175.07:39:01.53/valo/03,672.99,yes,locked 2006.175.07:39:01.53/valo/04,832.99,yes,locked 2006.175.07:39:01.53/valo/05,652.99,yes,locked 2006.175.07:39:01.53/valo/06,772.99,yes,locked 2006.175.07:39:01.53/valo/07,832.99,yes,locked 2006.175.07:39:01.53/valo/08,852.99,yes,locked 2006.175.07:39:02.62/vb/01,04,usb,yes,29,28 2006.175.07:39:02.62/vb/02,04,usb,yes,31,32 2006.175.07:39:02.62/vb/03,04,usb,yes,27,31 2006.175.07:39:02.62/vb/04,04,usb,yes,28,28 2006.175.07:39:02.62/vb/05,04,usb,yes,27,31 2006.175.07:39:02.62/vb/06,04,usb,yes,28,31 2006.175.07:39:02.62/vb/07,04,usb,yes,30,30 2006.175.07:39:02.62/vb/08,04,usb,yes,27,31 2006.175.07:39:02.85/vblo/01,632.99,yes,locked 2006.175.07:39:02.85/vblo/02,640.99,yes,locked 2006.175.07:39:02.85/vblo/03,656.99,yes,locked 2006.175.07:39:02.85/vblo/04,712.99,yes,locked 2006.175.07:39:02.85/vblo/05,744.99,yes,locked 2006.175.07:39:02.85/vblo/06,752.99,yes,locked 2006.175.07:39:02.85/vblo/07,734.99,yes,locked 2006.175.07:39:02.85/vblo/08,744.99,yes,locked 2006.175.07:39:03.00/vabw/8 2006.175.07:39:03.15/vbbw/8 2006.175.07:39:03.24/xfe/off,on,14.5 2006.175.07:39:03.61/ifatt/23,28,28,28 2006.175.07:39:04.07/fmout-gps/S +3.77E-07 2006.175.07:39:04.15:!2006.175.07:40:00 2006.175.07:40:00.00:data_valid=off 2006.175.07:40:00.00:postob 2006.175.07:40:00.16/cable/+6.4781E-03 2006.175.07:40:00.16/wx/25.95,1007.5,69 2006.175.07:40:01.07/fmout-gps/S +3.76E-07 2006.175.07:40:01.07:scan_name=175-0740,k06175,60 2006.175.07:40:01.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.175.07:40:01.14#flagr#flagr/antenna,new-source 2006.175.07:40:02.14:checkk5 2006.175.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:40:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:40:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:40:03.67/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:40:04.04/chk_obsdata//k5ts1/T1750739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:40:04.41/chk_obsdata//k5ts2/T1750739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:40:04.78/chk_obsdata//k5ts3/T1750739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:40:05.16/chk_obsdata//k5ts4/T1750739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:40:05.85/k5log//k5ts1_log_newline 2006.175.07:40:06.55/k5log//k5ts2_log_newline 2006.175.07:40:07.25/k5log//k5ts3_log_newline 2006.175.07:40:07.95/k5log//k5ts4_log_newline 2006.175.07:40:07.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:40:07.97:4f8m12a=1 2006.175.07:40:07.97$4f8m12a/echo=on 2006.175.07:40:07.97$4f8m12a/pcalon 2006.175.07:40:07.97$pcalon/"no phase cal control is implemented here 2006.175.07:40:07.97$4f8m12a/"tpicd=stop 2006.175.07:40:07.97$4f8m12a/vc4f8 2006.175.07:40:07.97$vc4f8/valo=1,532.99 2006.175.07:40:07.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.07:40:07.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.07:40:07.97#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:07.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:07.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:07.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:07.97#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:40:07.97#ibcon#first serial, iclass 7, count 0 2006.175.07:40:07.97#ibcon#enter sib2, iclass 7, count 0 2006.175.07:40:07.97#ibcon#flushed, iclass 7, count 0 2006.175.07:40:07.97#ibcon#about to write, iclass 7, count 0 2006.175.07:40:07.97#ibcon#wrote, iclass 7, count 0 2006.175.07:40:07.97#ibcon#about to read 3, iclass 7, count 0 2006.175.07:40:07.99#ibcon#read 3, iclass 7, count 0 2006.175.07:40:07.99#ibcon#about to read 4, iclass 7, count 0 2006.175.07:40:07.99#ibcon#read 4, iclass 7, count 0 2006.175.07:40:07.99#ibcon#about to read 5, iclass 7, count 0 2006.175.07:40:07.99#ibcon#read 5, iclass 7, count 0 2006.175.07:40:07.99#ibcon#about to read 6, iclass 7, count 0 2006.175.07:40:07.99#ibcon#read 6, iclass 7, count 0 2006.175.07:40:07.99#ibcon#end of sib2, iclass 7, count 0 2006.175.07:40:07.99#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:40:07.99#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:40:07.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:40:07.99#ibcon#*before write, iclass 7, count 0 2006.175.07:40:07.99#ibcon#enter sib2, iclass 7, count 0 2006.175.07:40:07.99#ibcon#flushed, iclass 7, count 0 2006.175.07:40:07.99#ibcon#about to write, iclass 7, count 0 2006.175.07:40:07.99#ibcon#wrote, iclass 7, count 0 2006.175.07:40:07.99#ibcon#about to read 3, iclass 7, count 0 2006.175.07:40:08.04#ibcon#read 3, iclass 7, count 0 2006.175.07:40:08.04#ibcon#about to read 4, iclass 7, count 0 2006.175.07:40:08.04#ibcon#read 4, iclass 7, count 0 2006.175.07:40:08.04#ibcon#about to read 5, iclass 7, count 0 2006.175.07:40:08.04#ibcon#read 5, iclass 7, count 0 2006.175.07:40:08.04#ibcon#about to read 6, iclass 7, count 0 2006.175.07:40:08.04#ibcon#read 6, iclass 7, count 0 2006.175.07:40:08.04#ibcon#end of sib2, iclass 7, count 0 2006.175.07:40:08.04#ibcon#*after write, iclass 7, count 0 2006.175.07:40:08.04#ibcon#*before return 0, iclass 7, count 0 2006.175.07:40:08.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:08.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:08.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:40:08.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:40:08.04$vc4f8/va=1,8 2006.175.07:40:08.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.175.07:40:08.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.175.07:40:08.04#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:08.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:08.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:08.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:08.04#ibcon#enter wrdev, iclass 11, count 2 2006.175.07:40:08.04#ibcon#first serial, iclass 11, count 2 2006.175.07:40:08.04#ibcon#enter sib2, iclass 11, count 2 2006.175.07:40:08.04#ibcon#flushed, iclass 11, count 2 2006.175.07:40:08.04#ibcon#about to write, iclass 11, count 2 2006.175.07:40:08.04#ibcon#wrote, iclass 11, count 2 2006.175.07:40:08.04#ibcon#about to read 3, iclass 11, count 2 2006.175.07:40:08.06#ibcon#read 3, iclass 11, count 2 2006.175.07:40:08.06#ibcon#about to read 4, iclass 11, count 2 2006.175.07:40:08.06#ibcon#read 4, iclass 11, count 2 2006.175.07:40:08.06#ibcon#about to read 5, iclass 11, count 2 2006.175.07:40:08.06#ibcon#read 5, iclass 11, count 2 2006.175.07:40:08.06#ibcon#about to read 6, iclass 11, count 2 2006.175.07:40:08.06#ibcon#read 6, iclass 11, count 2 2006.175.07:40:08.06#ibcon#end of sib2, iclass 11, count 2 2006.175.07:40:08.06#ibcon#*mode == 0, iclass 11, count 2 2006.175.07:40:08.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.175.07:40:08.06#ibcon#[25=AT01-08\r\n] 2006.175.07:40:08.06#ibcon#*before write, iclass 11, count 2 2006.175.07:40:08.06#ibcon#enter sib2, iclass 11, count 2 2006.175.07:40:08.06#ibcon#flushed, iclass 11, count 2 2006.175.07:40:08.06#ibcon#about to write, iclass 11, count 2 2006.175.07:40:08.06#ibcon#wrote, iclass 11, count 2 2006.175.07:40:08.06#ibcon#about to read 3, iclass 11, count 2 2006.175.07:40:08.09#ibcon#read 3, iclass 11, count 2 2006.175.07:40:08.09#ibcon#about to read 4, iclass 11, count 2 2006.175.07:40:08.09#ibcon#read 4, iclass 11, count 2 2006.175.07:40:08.09#ibcon#about to read 5, iclass 11, count 2 2006.175.07:40:08.09#ibcon#read 5, iclass 11, count 2 2006.175.07:40:08.09#ibcon#about to read 6, iclass 11, count 2 2006.175.07:40:08.09#ibcon#read 6, iclass 11, count 2 2006.175.07:40:08.09#ibcon#end of sib2, iclass 11, count 2 2006.175.07:40:08.09#ibcon#*after write, iclass 11, count 2 2006.175.07:40:08.09#ibcon#*before return 0, iclass 11, count 2 2006.175.07:40:08.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:08.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:08.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.175.07:40:08.09#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:08.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:08.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:08.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:08.21#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:40:08.21#ibcon#first serial, iclass 11, count 0 2006.175.07:40:08.21#ibcon#enter sib2, iclass 11, count 0 2006.175.07:40:08.21#ibcon#flushed, iclass 11, count 0 2006.175.07:40:08.21#ibcon#about to write, iclass 11, count 0 2006.175.07:40:08.21#ibcon#wrote, iclass 11, count 0 2006.175.07:40:08.21#ibcon#about to read 3, iclass 11, count 0 2006.175.07:40:08.23#ibcon#read 3, iclass 11, count 0 2006.175.07:40:08.23#ibcon#about to read 4, iclass 11, count 0 2006.175.07:40:08.23#ibcon#read 4, iclass 11, count 0 2006.175.07:40:08.23#ibcon#about to read 5, iclass 11, count 0 2006.175.07:40:08.23#ibcon#read 5, iclass 11, count 0 2006.175.07:40:08.23#ibcon#about to read 6, iclass 11, count 0 2006.175.07:40:08.23#ibcon#read 6, iclass 11, count 0 2006.175.07:40:08.23#ibcon#end of sib2, iclass 11, count 0 2006.175.07:40:08.23#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:40:08.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:40:08.23#ibcon#[25=USB\r\n] 2006.175.07:40:08.23#ibcon#*before write, iclass 11, count 0 2006.175.07:40:08.23#ibcon#enter sib2, iclass 11, count 0 2006.175.07:40:08.23#ibcon#flushed, iclass 11, count 0 2006.175.07:40:08.23#ibcon#about to write, iclass 11, count 0 2006.175.07:40:08.23#ibcon#wrote, iclass 11, count 0 2006.175.07:40:08.23#ibcon#about to read 3, iclass 11, count 0 2006.175.07:40:08.26#ibcon#read 3, iclass 11, count 0 2006.175.07:40:08.26#ibcon#about to read 4, iclass 11, count 0 2006.175.07:40:08.26#ibcon#read 4, iclass 11, count 0 2006.175.07:40:08.26#ibcon#about to read 5, iclass 11, count 0 2006.175.07:40:08.26#ibcon#read 5, iclass 11, count 0 2006.175.07:40:08.26#ibcon#about to read 6, iclass 11, count 0 2006.175.07:40:08.26#ibcon#read 6, iclass 11, count 0 2006.175.07:40:08.26#ibcon#end of sib2, iclass 11, count 0 2006.175.07:40:08.26#ibcon#*after write, iclass 11, count 0 2006.175.07:40:08.26#ibcon#*before return 0, iclass 11, count 0 2006.175.07:40:08.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:08.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:08.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:40:08.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:40:08.26$vc4f8/valo=2,572.99 2006.175.07:40:08.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.175.07:40:08.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.175.07:40:08.26#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:08.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:08.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:08.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:08.26#ibcon#enter wrdev, iclass 13, count 0 2006.175.07:40:08.26#ibcon#first serial, iclass 13, count 0 2006.175.07:40:08.26#ibcon#enter sib2, iclass 13, count 0 2006.175.07:40:08.26#ibcon#flushed, iclass 13, count 0 2006.175.07:40:08.26#ibcon#about to write, iclass 13, count 0 2006.175.07:40:08.26#ibcon#wrote, iclass 13, count 0 2006.175.07:40:08.26#ibcon#about to read 3, iclass 13, count 0 2006.175.07:40:08.28#ibcon#read 3, iclass 13, count 0 2006.175.07:40:08.28#ibcon#about to read 4, iclass 13, count 0 2006.175.07:40:08.28#ibcon#read 4, iclass 13, count 0 2006.175.07:40:08.28#ibcon#about to read 5, iclass 13, count 0 2006.175.07:40:08.28#ibcon#read 5, iclass 13, count 0 2006.175.07:40:08.28#ibcon#about to read 6, iclass 13, count 0 2006.175.07:40:08.28#ibcon#read 6, iclass 13, count 0 2006.175.07:40:08.28#ibcon#end of sib2, iclass 13, count 0 2006.175.07:40:08.28#ibcon#*mode == 0, iclass 13, count 0 2006.175.07:40:08.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.07:40:08.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:40:08.28#ibcon#*before write, iclass 13, count 0 2006.175.07:40:08.28#ibcon#enter sib2, iclass 13, count 0 2006.175.07:40:08.28#ibcon#flushed, iclass 13, count 0 2006.175.07:40:08.28#ibcon#about to write, iclass 13, count 0 2006.175.07:40:08.28#ibcon#wrote, iclass 13, count 0 2006.175.07:40:08.28#ibcon#about to read 3, iclass 13, count 0 2006.175.07:40:08.32#ibcon#read 3, iclass 13, count 0 2006.175.07:40:08.32#ibcon#about to read 4, iclass 13, count 0 2006.175.07:40:08.32#ibcon#read 4, iclass 13, count 0 2006.175.07:40:08.32#ibcon#about to read 5, iclass 13, count 0 2006.175.07:40:08.32#ibcon#read 5, iclass 13, count 0 2006.175.07:40:08.32#ibcon#about to read 6, iclass 13, count 0 2006.175.07:40:08.32#ibcon#read 6, iclass 13, count 0 2006.175.07:40:08.32#ibcon#end of sib2, iclass 13, count 0 2006.175.07:40:08.32#ibcon#*after write, iclass 13, count 0 2006.175.07:40:08.32#ibcon#*before return 0, iclass 13, count 0 2006.175.07:40:08.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:08.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:08.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.07:40:08.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.07:40:08.32$vc4f8/va=2,7 2006.175.07:40:08.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.175.07:40:08.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.175.07:40:08.32#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:08.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:08.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:08.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:08.38#ibcon#enter wrdev, iclass 15, count 2 2006.175.07:40:08.38#ibcon#first serial, iclass 15, count 2 2006.175.07:40:08.38#ibcon#enter sib2, iclass 15, count 2 2006.175.07:40:08.38#ibcon#flushed, iclass 15, count 2 2006.175.07:40:08.38#ibcon#about to write, iclass 15, count 2 2006.175.07:40:08.38#ibcon#wrote, iclass 15, count 2 2006.175.07:40:08.38#ibcon#about to read 3, iclass 15, count 2 2006.175.07:40:08.40#ibcon#read 3, iclass 15, count 2 2006.175.07:40:08.40#ibcon#about to read 4, iclass 15, count 2 2006.175.07:40:08.40#ibcon#read 4, iclass 15, count 2 2006.175.07:40:08.40#ibcon#about to read 5, iclass 15, count 2 2006.175.07:40:08.40#ibcon#read 5, iclass 15, count 2 2006.175.07:40:08.40#ibcon#about to read 6, iclass 15, count 2 2006.175.07:40:08.40#ibcon#read 6, iclass 15, count 2 2006.175.07:40:08.40#ibcon#end of sib2, iclass 15, count 2 2006.175.07:40:08.40#ibcon#*mode == 0, iclass 15, count 2 2006.175.07:40:08.40#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.175.07:40:08.40#ibcon#[25=AT02-07\r\n] 2006.175.07:40:08.40#ibcon#*before write, iclass 15, count 2 2006.175.07:40:08.40#ibcon#enter sib2, iclass 15, count 2 2006.175.07:40:08.40#ibcon#flushed, iclass 15, count 2 2006.175.07:40:08.40#ibcon#about to write, iclass 15, count 2 2006.175.07:40:08.40#ibcon#wrote, iclass 15, count 2 2006.175.07:40:08.40#ibcon#about to read 3, iclass 15, count 2 2006.175.07:40:08.43#ibcon#read 3, iclass 15, count 2 2006.175.07:40:08.43#ibcon#about to read 4, iclass 15, count 2 2006.175.07:40:08.43#ibcon#read 4, iclass 15, count 2 2006.175.07:40:08.43#ibcon#about to read 5, iclass 15, count 2 2006.175.07:40:08.43#ibcon#read 5, iclass 15, count 2 2006.175.07:40:08.43#ibcon#about to read 6, iclass 15, count 2 2006.175.07:40:08.43#ibcon#read 6, iclass 15, count 2 2006.175.07:40:08.43#ibcon#end of sib2, iclass 15, count 2 2006.175.07:40:08.43#ibcon#*after write, iclass 15, count 2 2006.175.07:40:08.43#ibcon#*before return 0, iclass 15, count 2 2006.175.07:40:08.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:08.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:08.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.175.07:40:08.43#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:08.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:08.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:08.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:08.55#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:40:08.55#ibcon#first serial, iclass 15, count 0 2006.175.07:40:08.55#ibcon#enter sib2, iclass 15, count 0 2006.175.07:40:08.55#ibcon#flushed, iclass 15, count 0 2006.175.07:40:08.55#ibcon#about to write, iclass 15, count 0 2006.175.07:40:08.55#ibcon#wrote, iclass 15, count 0 2006.175.07:40:08.55#ibcon#about to read 3, iclass 15, count 0 2006.175.07:40:08.57#ibcon#read 3, iclass 15, count 0 2006.175.07:40:08.57#ibcon#about to read 4, iclass 15, count 0 2006.175.07:40:08.57#ibcon#read 4, iclass 15, count 0 2006.175.07:40:08.57#ibcon#about to read 5, iclass 15, count 0 2006.175.07:40:08.57#ibcon#read 5, iclass 15, count 0 2006.175.07:40:08.57#ibcon#about to read 6, iclass 15, count 0 2006.175.07:40:08.57#ibcon#read 6, iclass 15, count 0 2006.175.07:40:08.57#ibcon#end of sib2, iclass 15, count 0 2006.175.07:40:08.57#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:40:08.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:40:08.57#ibcon#[25=USB\r\n] 2006.175.07:40:08.57#ibcon#*before write, iclass 15, count 0 2006.175.07:40:08.57#ibcon#enter sib2, iclass 15, count 0 2006.175.07:40:08.57#ibcon#flushed, iclass 15, count 0 2006.175.07:40:08.57#ibcon#about to write, iclass 15, count 0 2006.175.07:40:08.57#ibcon#wrote, iclass 15, count 0 2006.175.07:40:08.57#ibcon#about to read 3, iclass 15, count 0 2006.175.07:40:08.60#ibcon#read 3, iclass 15, count 0 2006.175.07:40:08.60#ibcon#about to read 4, iclass 15, count 0 2006.175.07:40:08.60#ibcon#read 4, iclass 15, count 0 2006.175.07:40:08.60#ibcon#about to read 5, iclass 15, count 0 2006.175.07:40:08.60#ibcon#read 5, iclass 15, count 0 2006.175.07:40:08.60#ibcon#about to read 6, iclass 15, count 0 2006.175.07:40:08.60#ibcon#read 6, iclass 15, count 0 2006.175.07:40:08.60#ibcon#end of sib2, iclass 15, count 0 2006.175.07:40:08.60#ibcon#*after write, iclass 15, count 0 2006.175.07:40:08.60#ibcon#*before return 0, iclass 15, count 0 2006.175.07:40:08.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:08.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:08.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:40:08.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:40:08.60$vc4f8/valo=3,672.99 2006.175.07:40:08.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.07:40:08.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.07:40:08.60#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:08.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:08.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:08.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:08.60#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:40:08.60#ibcon#first serial, iclass 17, count 0 2006.175.07:40:08.60#ibcon#enter sib2, iclass 17, count 0 2006.175.07:40:08.60#ibcon#flushed, iclass 17, count 0 2006.175.07:40:08.60#ibcon#about to write, iclass 17, count 0 2006.175.07:40:08.60#ibcon#wrote, iclass 17, count 0 2006.175.07:40:08.60#ibcon#about to read 3, iclass 17, count 0 2006.175.07:40:08.62#ibcon#read 3, iclass 17, count 0 2006.175.07:40:08.62#ibcon#about to read 4, iclass 17, count 0 2006.175.07:40:08.62#ibcon#read 4, iclass 17, count 0 2006.175.07:40:08.62#ibcon#about to read 5, iclass 17, count 0 2006.175.07:40:08.62#ibcon#read 5, iclass 17, count 0 2006.175.07:40:08.62#ibcon#about to read 6, iclass 17, count 0 2006.175.07:40:08.62#ibcon#read 6, iclass 17, count 0 2006.175.07:40:08.62#ibcon#end of sib2, iclass 17, count 0 2006.175.07:40:08.62#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:40:08.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:40:08.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:40:08.62#ibcon#*before write, iclass 17, count 0 2006.175.07:40:08.62#ibcon#enter sib2, iclass 17, count 0 2006.175.07:40:08.62#ibcon#flushed, iclass 17, count 0 2006.175.07:40:08.62#ibcon#about to write, iclass 17, count 0 2006.175.07:40:08.62#ibcon#wrote, iclass 17, count 0 2006.175.07:40:08.62#ibcon#about to read 3, iclass 17, count 0 2006.175.07:40:08.66#ibcon#read 3, iclass 17, count 0 2006.175.07:40:08.66#ibcon#about to read 4, iclass 17, count 0 2006.175.07:40:08.66#ibcon#read 4, iclass 17, count 0 2006.175.07:40:08.66#ibcon#about to read 5, iclass 17, count 0 2006.175.07:40:08.66#ibcon#read 5, iclass 17, count 0 2006.175.07:40:08.66#ibcon#about to read 6, iclass 17, count 0 2006.175.07:40:08.66#ibcon#read 6, iclass 17, count 0 2006.175.07:40:08.66#ibcon#end of sib2, iclass 17, count 0 2006.175.07:40:08.66#ibcon#*after write, iclass 17, count 0 2006.175.07:40:08.66#ibcon#*before return 0, iclass 17, count 0 2006.175.07:40:08.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:08.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:08.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:40:08.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:40:08.66$vc4f8/va=3,6 2006.175.07:40:08.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.175.07:40:08.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.175.07:40:08.66#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:08.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:08.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:08.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:08.72#ibcon#enter wrdev, iclass 19, count 2 2006.175.07:40:08.72#ibcon#first serial, iclass 19, count 2 2006.175.07:40:08.72#ibcon#enter sib2, iclass 19, count 2 2006.175.07:40:08.72#ibcon#flushed, iclass 19, count 2 2006.175.07:40:08.72#ibcon#about to write, iclass 19, count 2 2006.175.07:40:08.72#ibcon#wrote, iclass 19, count 2 2006.175.07:40:08.72#ibcon#about to read 3, iclass 19, count 2 2006.175.07:40:08.74#ibcon#read 3, iclass 19, count 2 2006.175.07:40:08.74#ibcon#about to read 4, iclass 19, count 2 2006.175.07:40:08.74#ibcon#read 4, iclass 19, count 2 2006.175.07:40:08.74#ibcon#about to read 5, iclass 19, count 2 2006.175.07:40:08.74#ibcon#read 5, iclass 19, count 2 2006.175.07:40:08.74#ibcon#about to read 6, iclass 19, count 2 2006.175.07:40:08.74#ibcon#read 6, iclass 19, count 2 2006.175.07:40:08.74#ibcon#end of sib2, iclass 19, count 2 2006.175.07:40:08.74#ibcon#*mode == 0, iclass 19, count 2 2006.175.07:40:08.74#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.175.07:40:08.74#ibcon#[25=AT03-06\r\n] 2006.175.07:40:08.74#ibcon#*before write, iclass 19, count 2 2006.175.07:40:08.74#ibcon#enter sib2, iclass 19, count 2 2006.175.07:40:08.74#ibcon#flushed, iclass 19, count 2 2006.175.07:40:08.74#ibcon#about to write, iclass 19, count 2 2006.175.07:40:08.74#ibcon#wrote, iclass 19, count 2 2006.175.07:40:08.74#ibcon#about to read 3, iclass 19, count 2 2006.175.07:40:08.77#ibcon#read 3, iclass 19, count 2 2006.175.07:40:08.77#ibcon#about to read 4, iclass 19, count 2 2006.175.07:40:08.77#ibcon#read 4, iclass 19, count 2 2006.175.07:40:08.77#ibcon#about to read 5, iclass 19, count 2 2006.175.07:40:08.77#ibcon#read 5, iclass 19, count 2 2006.175.07:40:08.77#ibcon#about to read 6, iclass 19, count 2 2006.175.07:40:08.77#ibcon#read 6, iclass 19, count 2 2006.175.07:40:08.77#ibcon#end of sib2, iclass 19, count 2 2006.175.07:40:08.77#ibcon#*after write, iclass 19, count 2 2006.175.07:40:08.77#ibcon#*before return 0, iclass 19, count 2 2006.175.07:40:08.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:08.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:08.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.175.07:40:08.77#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:08.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:08.89#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:08.89#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:08.89#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:40:08.89#ibcon#first serial, iclass 19, count 0 2006.175.07:40:08.89#ibcon#enter sib2, iclass 19, count 0 2006.175.07:40:08.89#ibcon#flushed, iclass 19, count 0 2006.175.07:40:08.89#ibcon#about to write, iclass 19, count 0 2006.175.07:40:08.89#ibcon#wrote, iclass 19, count 0 2006.175.07:40:08.89#ibcon#about to read 3, iclass 19, count 0 2006.175.07:40:08.91#ibcon#read 3, iclass 19, count 0 2006.175.07:40:08.91#ibcon#about to read 4, iclass 19, count 0 2006.175.07:40:08.91#ibcon#read 4, iclass 19, count 0 2006.175.07:40:08.91#ibcon#about to read 5, iclass 19, count 0 2006.175.07:40:08.91#ibcon#read 5, iclass 19, count 0 2006.175.07:40:08.91#ibcon#about to read 6, iclass 19, count 0 2006.175.07:40:08.91#ibcon#read 6, iclass 19, count 0 2006.175.07:40:08.91#ibcon#end of sib2, iclass 19, count 0 2006.175.07:40:08.91#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:40:08.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:40:08.91#ibcon#[25=USB\r\n] 2006.175.07:40:08.91#ibcon#*before write, iclass 19, count 0 2006.175.07:40:08.91#ibcon#enter sib2, iclass 19, count 0 2006.175.07:40:08.91#ibcon#flushed, iclass 19, count 0 2006.175.07:40:08.91#ibcon#about to write, iclass 19, count 0 2006.175.07:40:08.91#ibcon#wrote, iclass 19, count 0 2006.175.07:40:08.91#ibcon#about to read 3, iclass 19, count 0 2006.175.07:40:08.94#ibcon#read 3, iclass 19, count 0 2006.175.07:40:08.94#ibcon#about to read 4, iclass 19, count 0 2006.175.07:40:08.94#ibcon#read 4, iclass 19, count 0 2006.175.07:40:08.94#ibcon#about to read 5, iclass 19, count 0 2006.175.07:40:08.94#ibcon#read 5, iclass 19, count 0 2006.175.07:40:08.94#ibcon#about to read 6, iclass 19, count 0 2006.175.07:40:08.94#ibcon#read 6, iclass 19, count 0 2006.175.07:40:08.94#ibcon#end of sib2, iclass 19, count 0 2006.175.07:40:08.94#ibcon#*after write, iclass 19, count 0 2006.175.07:40:08.94#ibcon#*before return 0, iclass 19, count 0 2006.175.07:40:08.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:08.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:08.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:40:08.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:40:08.94$vc4f8/valo=4,832.99 2006.175.07:40:08.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.07:40:08.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.07:40:08.94#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:08.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:08.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:08.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:08.94#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:40:08.94#ibcon#first serial, iclass 21, count 0 2006.175.07:40:08.94#ibcon#enter sib2, iclass 21, count 0 2006.175.07:40:08.94#ibcon#flushed, iclass 21, count 0 2006.175.07:40:08.94#ibcon#about to write, iclass 21, count 0 2006.175.07:40:08.94#ibcon#wrote, iclass 21, count 0 2006.175.07:40:08.94#ibcon#about to read 3, iclass 21, count 0 2006.175.07:40:08.96#ibcon#read 3, iclass 21, count 0 2006.175.07:40:08.96#ibcon#about to read 4, iclass 21, count 0 2006.175.07:40:08.96#ibcon#read 4, iclass 21, count 0 2006.175.07:40:08.96#ibcon#about to read 5, iclass 21, count 0 2006.175.07:40:08.96#ibcon#read 5, iclass 21, count 0 2006.175.07:40:08.96#ibcon#about to read 6, iclass 21, count 0 2006.175.07:40:08.96#ibcon#read 6, iclass 21, count 0 2006.175.07:40:08.96#ibcon#end of sib2, iclass 21, count 0 2006.175.07:40:08.96#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:40:08.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:40:08.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:40:08.96#ibcon#*before write, iclass 21, count 0 2006.175.07:40:08.96#ibcon#enter sib2, iclass 21, count 0 2006.175.07:40:08.96#ibcon#flushed, iclass 21, count 0 2006.175.07:40:08.96#ibcon#about to write, iclass 21, count 0 2006.175.07:40:08.96#ibcon#wrote, iclass 21, count 0 2006.175.07:40:08.96#ibcon#about to read 3, iclass 21, count 0 2006.175.07:40:09.00#ibcon#read 3, iclass 21, count 0 2006.175.07:40:09.00#ibcon#about to read 4, iclass 21, count 0 2006.175.07:40:09.00#ibcon#read 4, iclass 21, count 0 2006.175.07:40:09.00#ibcon#about to read 5, iclass 21, count 0 2006.175.07:40:09.00#ibcon#read 5, iclass 21, count 0 2006.175.07:40:09.00#ibcon#about to read 6, iclass 21, count 0 2006.175.07:40:09.00#ibcon#read 6, iclass 21, count 0 2006.175.07:40:09.00#ibcon#end of sib2, iclass 21, count 0 2006.175.07:40:09.00#ibcon#*after write, iclass 21, count 0 2006.175.07:40:09.00#ibcon#*before return 0, iclass 21, count 0 2006.175.07:40:09.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:09.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:09.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:40:09.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:40:09.00$vc4f8/va=4,7 2006.175.07:40:09.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.07:40:09.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.07:40:09.00#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:09.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:09.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:09.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:09.06#ibcon#enter wrdev, iclass 23, count 2 2006.175.07:40:09.06#ibcon#first serial, iclass 23, count 2 2006.175.07:40:09.06#ibcon#enter sib2, iclass 23, count 2 2006.175.07:40:09.06#ibcon#flushed, iclass 23, count 2 2006.175.07:40:09.06#ibcon#about to write, iclass 23, count 2 2006.175.07:40:09.06#ibcon#wrote, iclass 23, count 2 2006.175.07:40:09.06#ibcon#about to read 3, iclass 23, count 2 2006.175.07:40:09.08#ibcon#read 3, iclass 23, count 2 2006.175.07:40:09.08#ibcon#about to read 4, iclass 23, count 2 2006.175.07:40:09.08#ibcon#read 4, iclass 23, count 2 2006.175.07:40:09.08#ibcon#about to read 5, iclass 23, count 2 2006.175.07:40:09.08#ibcon#read 5, iclass 23, count 2 2006.175.07:40:09.08#ibcon#about to read 6, iclass 23, count 2 2006.175.07:40:09.08#ibcon#read 6, iclass 23, count 2 2006.175.07:40:09.08#ibcon#end of sib2, iclass 23, count 2 2006.175.07:40:09.08#ibcon#*mode == 0, iclass 23, count 2 2006.175.07:40:09.08#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.07:40:09.08#ibcon#[25=AT04-07\r\n] 2006.175.07:40:09.08#ibcon#*before write, iclass 23, count 2 2006.175.07:40:09.08#ibcon#enter sib2, iclass 23, count 2 2006.175.07:40:09.08#ibcon#flushed, iclass 23, count 2 2006.175.07:40:09.08#ibcon#about to write, iclass 23, count 2 2006.175.07:40:09.08#ibcon#wrote, iclass 23, count 2 2006.175.07:40:09.08#ibcon#about to read 3, iclass 23, count 2 2006.175.07:40:09.11#ibcon#read 3, iclass 23, count 2 2006.175.07:40:09.11#ibcon#about to read 4, iclass 23, count 2 2006.175.07:40:09.11#ibcon#read 4, iclass 23, count 2 2006.175.07:40:09.11#ibcon#about to read 5, iclass 23, count 2 2006.175.07:40:09.11#ibcon#read 5, iclass 23, count 2 2006.175.07:40:09.11#ibcon#about to read 6, iclass 23, count 2 2006.175.07:40:09.11#ibcon#read 6, iclass 23, count 2 2006.175.07:40:09.11#ibcon#end of sib2, iclass 23, count 2 2006.175.07:40:09.11#ibcon#*after write, iclass 23, count 2 2006.175.07:40:09.11#ibcon#*before return 0, iclass 23, count 2 2006.175.07:40:09.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:09.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:09.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.07:40:09.11#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:09.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:09.21#abcon#<5=/05 4.9 7.3 25.95 681007.5\r\n> 2006.175.07:40:09.23#abcon#{5=INTERFACE CLEAR} 2006.175.07:40:09.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:09.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:09.23#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:40:09.23#ibcon#first serial, iclass 23, count 0 2006.175.07:40:09.23#ibcon#enter sib2, iclass 23, count 0 2006.175.07:40:09.23#ibcon#flushed, iclass 23, count 0 2006.175.07:40:09.23#ibcon#about to write, iclass 23, count 0 2006.175.07:40:09.23#ibcon#wrote, iclass 23, count 0 2006.175.07:40:09.23#ibcon#about to read 3, iclass 23, count 0 2006.175.07:40:09.25#ibcon#read 3, iclass 23, count 0 2006.175.07:40:09.25#ibcon#about to read 4, iclass 23, count 0 2006.175.07:40:09.25#ibcon#read 4, iclass 23, count 0 2006.175.07:40:09.25#ibcon#about to read 5, iclass 23, count 0 2006.175.07:40:09.25#ibcon#read 5, iclass 23, count 0 2006.175.07:40:09.25#ibcon#about to read 6, iclass 23, count 0 2006.175.07:40:09.25#ibcon#read 6, iclass 23, count 0 2006.175.07:40:09.25#ibcon#end of sib2, iclass 23, count 0 2006.175.07:40:09.25#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:40:09.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:40:09.25#ibcon#[25=USB\r\n] 2006.175.07:40:09.25#ibcon#*before write, iclass 23, count 0 2006.175.07:40:09.25#ibcon#enter sib2, iclass 23, count 0 2006.175.07:40:09.25#ibcon#flushed, iclass 23, count 0 2006.175.07:40:09.25#ibcon#about to write, iclass 23, count 0 2006.175.07:40:09.25#ibcon#wrote, iclass 23, count 0 2006.175.07:40:09.25#ibcon#about to read 3, iclass 23, count 0 2006.175.07:40:09.28#ibcon#read 3, iclass 23, count 0 2006.175.07:40:09.28#ibcon#about to read 4, iclass 23, count 0 2006.175.07:40:09.28#ibcon#read 4, iclass 23, count 0 2006.175.07:40:09.28#ibcon#about to read 5, iclass 23, count 0 2006.175.07:40:09.28#ibcon#read 5, iclass 23, count 0 2006.175.07:40:09.28#ibcon#about to read 6, iclass 23, count 0 2006.175.07:40:09.28#ibcon#read 6, iclass 23, count 0 2006.175.07:40:09.28#ibcon#end of sib2, iclass 23, count 0 2006.175.07:40:09.28#ibcon#*after write, iclass 23, count 0 2006.175.07:40:09.28#ibcon#*before return 0, iclass 23, count 0 2006.175.07:40:09.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:09.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:09.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:40:09.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:40:09.28$vc4f8/valo=5,652.99 2006.175.07:40:09.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.07:40:09.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.07:40:09.28#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:09.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:09.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:09.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:09.28#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:40:09.28#ibcon#first serial, iclass 29, count 0 2006.175.07:40:09.28#ibcon#enter sib2, iclass 29, count 0 2006.175.07:40:09.28#ibcon#flushed, iclass 29, count 0 2006.175.07:40:09.28#ibcon#about to write, iclass 29, count 0 2006.175.07:40:09.28#ibcon#wrote, iclass 29, count 0 2006.175.07:40:09.28#ibcon#about to read 3, iclass 29, count 0 2006.175.07:40:09.29#abcon#[5=S1D000X0/0*\r\n] 2006.175.07:40:09.30#ibcon#read 3, iclass 29, count 0 2006.175.07:40:09.30#ibcon#about to read 4, iclass 29, count 0 2006.175.07:40:09.30#ibcon#read 4, iclass 29, count 0 2006.175.07:40:09.30#ibcon#about to read 5, iclass 29, count 0 2006.175.07:40:09.30#ibcon#read 5, iclass 29, count 0 2006.175.07:40:09.30#ibcon#about to read 6, iclass 29, count 0 2006.175.07:40:09.30#ibcon#read 6, iclass 29, count 0 2006.175.07:40:09.30#ibcon#end of sib2, iclass 29, count 0 2006.175.07:40:09.30#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:40:09.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:40:09.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:40:09.30#ibcon#*before write, iclass 29, count 0 2006.175.07:40:09.30#ibcon#enter sib2, iclass 29, count 0 2006.175.07:40:09.30#ibcon#flushed, iclass 29, count 0 2006.175.07:40:09.30#ibcon#about to write, iclass 29, count 0 2006.175.07:40:09.30#ibcon#wrote, iclass 29, count 0 2006.175.07:40:09.30#ibcon#about to read 3, iclass 29, count 0 2006.175.07:40:09.34#ibcon#read 3, iclass 29, count 0 2006.175.07:40:09.34#ibcon#about to read 4, iclass 29, count 0 2006.175.07:40:09.34#ibcon#read 4, iclass 29, count 0 2006.175.07:40:09.34#ibcon#about to read 5, iclass 29, count 0 2006.175.07:40:09.34#ibcon#read 5, iclass 29, count 0 2006.175.07:40:09.34#ibcon#about to read 6, iclass 29, count 0 2006.175.07:40:09.34#ibcon#read 6, iclass 29, count 0 2006.175.07:40:09.34#ibcon#end of sib2, iclass 29, count 0 2006.175.07:40:09.34#ibcon#*after write, iclass 29, count 0 2006.175.07:40:09.34#ibcon#*before return 0, iclass 29, count 0 2006.175.07:40:09.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:09.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:09.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:40:09.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:40:09.34$vc4f8/va=5,7 2006.175.07:40:09.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.07:40:09.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.07:40:09.34#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:09.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:09.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:09.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:09.40#ibcon#enter wrdev, iclass 31, count 2 2006.175.07:40:09.40#ibcon#first serial, iclass 31, count 2 2006.175.07:40:09.40#ibcon#enter sib2, iclass 31, count 2 2006.175.07:40:09.40#ibcon#flushed, iclass 31, count 2 2006.175.07:40:09.40#ibcon#about to write, iclass 31, count 2 2006.175.07:40:09.40#ibcon#wrote, iclass 31, count 2 2006.175.07:40:09.40#ibcon#about to read 3, iclass 31, count 2 2006.175.07:40:09.42#ibcon#read 3, iclass 31, count 2 2006.175.07:40:09.42#ibcon#about to read 4, iclass 31, count 2 2006.175.07:40:09.42#ibcon#read 4, iclass 31, count 2 2006.175.07:40:09.42#ibcon#about to read 5, iclass 31, count 2 2006.175.07:40:09.42#ibcon#read 5, iclass 31, count 2 2006.175.07:40:09.42#ibcon#about to read 6, iclass 31, count 2 2006.175.07:40:09.42#ibcon#read 6, iclass 31, count 2 2006.175.07:40:09.42#ibcon#end of sib2, iclass 31, count 2 2006.175.07:40:09.42#ibcon#*mode == 0, iclass 31, count 2 2006.175.07:40:09.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.07:40:09.42#ibcon#[25=AT05-07\r\n] 2006.175.07:40:09.42#ibcon#*before write, iclass 31, count 2 2006.175.07:40:09.42#ibcon#enter sib2, iclass 31, count 2 2006.175.07:40:09.42#ibcon#flushed, iclass 31, count 2 2006.175.07:40:09.42#ibcon#about to write, iclass 31, count 2 2006.175.07:40:09.42#ibcon#wrote, iclass 31, count 2 2006.175.07:40:09.42#ibcon#about to read 3, iclass 31, count 2 2006.175.07:40:09.45#ibcon#read 3, iclass 31, count 2 2006.175.07:40:09.45#ibcon#about to read 4, iclass 31, count 2 2006.175.07:40:09.45#ibcon#read 4, iclass 31, count 2 2006.175.07:40:09.45#ibcon#about to read 5, iclass 31, count 2 2006.175.07:40:09.45#ibcon#read 5, iclass 31, count 2 2006.175.07:40:09.45#ibcon#about to read 6, iclass 31, count 2 2006.175.07:40:09.45#ibcon#read 6, iclass 31, count 2 2006.175.07:40:09.45#ibcon#end of sib2, iclass 31, count 2 2006.175.07:40:09.45#ibcon#*after write, iclass 31, count 2 2006.175.07:40:09.45#ibcon#*before return 0, iclass 31, count 2 2006.175.07:40:09.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:09.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:09.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.07:40:09.45#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:09.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:09.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:09.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:09.57#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:40:09.57#ibcon#first serial, iclass 31, count 0 2006.175.07:40:09.57#ibcon#enter sib2, iclass 31, count 0 2006.175.07:40:09.57#ibcon#flushed, iclass 31, count 0 2006.175.07:40:09.57#ibcon#about to write, iclass 31, count 0 2006.175.07:40:09.57#ibcon#wrote, iclass 31, count 0 2006.175.07:40:09.57#ibcon#about to read 3, iclass 31, count 0 2006.175.07:40:09.59#ibcon#read 3, iclass 31, count 0 2006.175.07:40:09.59#ibcon#about to read 4, iclass 31, count 0 2006.175.07:40:09.59#ibcon#read 4, iclass 31, count 0 2006.175.07:40:09.59#ibcon#about to read 5, iclass 31, count 0 2006.175.07:40:09.59#ibcon#read 5, iclass 31, count 0 2006.175.07:40:09.59#ibcon#about to read 6, iclass 31, count 0 2006.175.07:40:09.59#ibcon#read 6, iclass 31, count 0 2006.175.07:40:09.59#ibcon#end of sib2, iclass 31, count 0 2006.175.07:40:09.59#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:40:09.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:40:09.59#ibcon#[25=USB\r\n] 2006.175.07:40:09.59#ibcon#*before write, iclass 31, count 0 2006.175.07:40:09.59#ibcon#enter sib2, iclass 31, count 0 2006.175.07:40:09.59#ibcon#flushed, iclass 31, count 0 2006.175.07:40:09.59#ibcon#about to write, iclass 31, count 0 2006.175.07:40:09.59#ibcon#wrote, iclass 31, count 0 2006.175.07:40:09.59#ibcon#about to read 3, iclass 31, count 0 2006.175.07:40:09.62#ibcon#read 3, iclass 31, count 0 2006.175.07:40:09.62#ibcon#about to read 4, iclass 31, count 0 2006.175.07:40:09.62#ibcon#read 4, iclass 31, count 0 2006.175.07:40:09.62#ibcon#about to read 5, iclass 31, count 0 2006.175.07:40:09.62#ibcon#read 5, iclass 31, count 0 2006.175.07:40:09.62#ibcon#about to read 6, iclass 31, count 0 2006.175.07:40:09.62#ibcon#read 6, iclass 31, count 0 2006.175.07:40:09.62#ibcon#end of sib2, iclass 31, count 0 2006.175.07:40:09.62#ibcon#*after write, iclass 31, count 0 2006.175.07:40:09.62#ibcon#*before return 0, iclass 31, count 0 2006.175.07:40:09.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:09.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:09.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:40:09.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:40:09.62$vc4f8/valo=6,772.99 2006.175.07:40:09.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.07:40:09.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.07:40:09.62#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:09.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:09.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:09.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:09.62#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:40:09.62#ibcon#first serial, iclass 33, count 0 2006.175.07:40:09.62#ibcon#enter sib2, iclass 33, count 0 2006.175.07:40:09.62#ibcon#flushed, iclass 33, count 0 2006.175.07:40:09.62#ibcon#about to write, iclass 33, count 0 2006.175.07:40:09.62#ibcon#wrote, iclass 33, count 0 2006.175.07:40:09.62#ibcon#about to read 3, iclass 33, count 0 2006.175.07:40:09.64#ibcon#read 3, iclass 33, count 0 2006.175.07:40:09.64#ibcon#about to read 4, iclass 33, count 0 2006.175.07:40:09.64#ibcon#read 4, iclass 33, count 0 2006.175.07:40:09.64#ibcon#about to read 5, iclass 33, count 0 2006.175.07:40:09.64#ibcon#read 5, iclass 33, count 0 2006.175.07:40:09.64#ibcon#about to read 6, iclass 33, count 0 2006.175.07:40:09.64#ibcon#read 6, iclass 33, count 0 2006.175.07:40:09.64#ibcon#end of sib2, iclass 33, count 0 2006.175.07:40:09.64#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:40:09.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:40:09.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:40:09.64#ibcon#*before write, iclass 33, count 0 2006.175.07:40:09.64#ibcon#enter sib2, iclass 33, count 0 2006.175.07:40:09.64#ibcon#flushed, iclass 33, count 0 2006.175.07:40:09.64#ibcon#about to write, iclass 33, count 0 2006.175.07:40:09.64#ibcon#wrote, iclass 33, count 0 2006.175.07:40:09.64#ibcon#about to read 3, iclass 33, count 0 2006.175.07:40:09.68#ibcon#read 3, iclass 33, count 0 2006.175.07:40:09.68#ibcon#about to read 4, iclass 33, count 0 2006.175.07:40:09.68#ibcon#read 4, iclass 33, count 0 2006.175.07:40:09.68#ibcon#about to read 5, iclass 33, count 0 2006.175.07:40:09.68#ibcon#read 5, iclass 33, count 0 2006.175.07:40:09.68#ibcon#about to read 6, iclass 33, count 0 2006.175.07:40:09.68#ibcon#read 6, iclass 33, count 0 2006.175.07:40:09.68#ibcon#end of sib2, iclass 33, count 0 2006.175.07:40:09.68#ibcon#*after write, iclass 33, count 0 2006.175.07:40:09.68#ibcon#*before return 0, iclass 33, count 0 2006.175.07:40:09.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:09.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:09.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:40:09.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:40:09.68$vc4f8/va=6,6 2006.175.07:40:09.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.175.07:40:09.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.175.07:40:09.68#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:09.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:40:09.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:40:09.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:40:09.74#ibcon#enter wrdev, iclass 35, count 2 2006.175.07:40:09.74#ibcon#first serial, iclass 35, count 2 2006.175.07:40:09.74#ibcon#enter sib2, iclass 35, count 2 2006.175.07:40:09.74#ibcon#flushed, iclass 35, count 2 2006.175.07:40:09.74#ibcon#about to write, iclass 35, count 2 2006.175.07:40:09.74#ibcon#wrote, iclass 35, count 2 2006.175.07:40:09.74#ibcon#about to read 3, iclass 35, count 2 2006.175.07:40:09.76#ibcon#read 3, iclass 35, count 2 2006.175.07:40:09.76#ibcon#about to read 4, iclass 35, count 2 2006.175.07:40:09.76#ibcon#read 4, iclass 35, count 2 2006.175.07:40:09.76#ibcon#about to read 5, iclass 35, count 2 2006.175.07:40:09.76#ibcon#read 5, iclass 35, count 2 2006.175.07:40:09.76#ibcon#about to read 6, iclass 35, count 2 2006.175.07:40:09.76#ibcon#read 6, iclass 35, count 2 2006.175.07:40:09.76#ibcon#end of sib2, iclass 35, count 2 2006.175.07:40:09.76#ibcon#*mode == 0, iclass 35, count 2 2006.175.07:40:09.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.175.07:40:09.76#ibcon#[25=AT06-06\r\n] 2006.175.07:40:09.76#ibcon#*before write, iclass 35, count 2 2006.175.07:40:09.76#ibcon#enter sib2, iclass 35, count 2 2006.175.07:40:09.76#ibcon#flushed, iclass 35, count 2 2006.175.07:40:09.76#ibcon#about to write, iclass 35, count 2 2006.175.07:40:09.76#ibcon#wrote, iclass 35, count 2 2006.175.07:40:09.76#ibcon#about to read 3, iclass 35, count 2 2006.175.07:40:09.79#ibcon#read 3, iclass 35, count 2 2006.175.07:40:09.79#ibcon#about to read 4, iclass 35, count 2 2006.175.07:40:09.79#ibcon#read 4, iclass 35, count 2 2006.175.07:40:09.79#ibcon#about to read 5, iclass 35, count 2 2006.175.07:40:09.79#ibcon#read 5, iclass 35, count 2 2006.175.07:40:09.79#ibcon#about to read 6, iclass 35, count 2 2006.175.07:40:09.79#ibcon#read 6, iclass 35, count 2 2006.175.07:40:09.79#ibcon#end of sib2, iclass 35, count 2 2006.175.07:40:09.79#ibcon#*after write, iclass 35, count 2 2006.175.07:40:09.79#ibcon#*before return 0, iclass 35, count 2 2006.175.07:40:09.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:40:09.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:40:09.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.175.07:40:09.79#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:09.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:40:09.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:40:09.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:40:09.91#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:40:09.91#ibcon#first serial, iclass 35, count 0 2006.175.07:40:09.91#ibcon#enter sib2, iclass 35, count 0 2006.175.07:40:09.91#ibcon#flushed, iclass 35, count 0 2006.175.07:40:09.91#ibcon#about to write, iclass 35, count 0 2006.175.07:40:09.91#ibcon#wrote, iclass 35, count 0 2006.175.07:40:09.91#ibcon#about to read 3, iclass 35, count 0 2006.175.07:40:09.93#ibcon#read 3, iclass 35, count 0 2006.175.07:40:09.93#ibcon#about to read 4, iclass 35, count 0 2006.175.07:40:09.93#ibcon#read 4, iclass 35, count 0 2006.175.07:40:09.93#ibcon#about to read 5, iclass 35, count 0 2006.175.07:40:09.93#ibcon#read 5, iclass 35, count 0 2006.175.07:40:09.93#ibcon#about to read 6, iclass 35, count 0 2006.175.07:40:09.93#ibcon#read 6, iclass 35, count 0 2006.175.07:40:09.93#ibcon#end of sib2, iclass 35, count 0 2006.175.07:40:09.93#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:40:09.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:40:09.93#ibcon#[25=USB\r\n] 2006.175.07:40:09.93#ibcon#*before write, iclass 35, count 0 2006.175.07:40:09.93#ibcon#enter sib2, iclass 35, count 0 2006.175.07:40:09.93#ibcon#flushed, iclass 35, count 0 2006.175.07:40:09.93#ibcon#about to write, iclass 35, count 0 2006.175.07:40:09.93#ibcon#wrote, iclass 35, count 0 2006.175.07:40:09.93#ibcon#about to read 3, iclass 35, count 0 2006.175.07:40:09.96#ibcon#read 3, iclass 35, count 0 2006.175.07:40:09.96#ibcon#about to read 4, iclass 35, count 0 2006.175.07:40:09.96#ibcon#read 4, iclass 35, count 0 2006.175.07:40:09.96#ibcon#about to read 5, iclass 35, count 0 2006.175.07:40:09.96#ibcon#read 5, iclass 35, count 0 2006.175.07:40:09.96#ibcon#about to read 6, iclass 35, count 0 2006.175.07:40:09.96#ibcon#read 6, iclass 35, count 0 2006.175.07:40:09.96#ibcon#end of sib2, iclass 35, count 0 2006.175.07:40:09.96#ibcon#*after write, iclass 35, count 0 2006.175.07:40:09.96#ibcon#*before return 0, iclass 35, count 0 2006.175.07:40:09.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:40:09.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:40:09.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:40:09.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:40:09.96$vc4f8/valo=7,832.99 2006.175.07:40:09.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.07:40:09.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.07:40:09.96#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:09.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:40:09.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:40:09.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:40:09.96#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:40:09.96#ibcon#first serial, iclass 37, count 0 2006.175.07:40:09.96#ibcon#enter sib2, iclass 37, count 0 2006.175.07:40:09.96#ibcon#flushed, iclass 37, count 0 2006.175.07:40:09.96#ibcon#about to write, iclass 37, count 0 2006.175.07:40:09.96#ibcon#wrote, iclass 37, count 0 2006.175.07:40:09.96#ibcon#about to read 3, iclass 37, count 0 2006.175.07:40:09.98#ibcon#read 3, iclass 37, count 0 2006.175.07:40:09.98#ibcon#about to read 4, iclass 37, count 0 2006.175.07:40:09.98#ibcon#read 4, iclass 37, count 0 2006.175.07:40:09.98#ibcon#about to read 5, iclass 37, count 0 2006.175.07:40:09.98#ibcon#read 5, iclass 37, count 0 2006.175.07:40:09.98#ibcon#about to read 6, iclass 37, count 0 2006.175.07:40:09.98#ibcon#read 6, iclass 37, count 0 2006.175.07:40:09.98#ibcon#end of sib2, iclass 37, count 0 2006.175.07:40:09.98#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:40:09.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:40:09.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:40:09.98#ibcon#*before write, iclass 37, count 0 2006.175.07:40:09.98#ibcon#enter sib2, iclass 37, count 0 2006.175.07:40:09.98#ibcon#flushed, iclass 37, count 0 2006.175.07:40:09.98#ibcon#about to write, iclass 37, count 0 2006.175.07:40:09.98#ibcon#wrote, iclass 37, count 0 2006.175.07:40:09.98#ibcon#about to read 3, iclass 37, count 0 2006.175.07:40:10.02#ibcon#read 3, iclass 37, count 0 2006.175.07:40:10.02#ibcon#about to read 4, iclass 37, count 0 2006.175.07:40:10.02#ibcon#read 4, iclass 37, count 0 2006.175.07:40:10.02#ibcon#about to read 5, iclass 37, count 0 2006.175.07:40:10.02#ibcon#read 5, iclass 37, count 0 2006.175.07:40:10.02#ibcon#about to read 6, iclass 37, count 0 2006.175.07:40:10.02#ibcon#read 6, iclass 37, count 0 2006.175.07:40:10.02#ibcon#end of sib2, iclass 37, count 0 2006.175.07:40:10.02#ibcon#*after write, iclass 37, count 0 2006.175.07:40:10.02#ibcon#*before return 0, iclass 37, count 0 2006.175.07:40:10.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:40:10.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:40:10.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:40:10.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:40:10.02$vc4f8/va=7,6 2006.175.07:40:10.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.175.07:40:10.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.175.07:40:10.02#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:10.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:40:10.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:40:10.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:40:10.08#ibcon#enter wrdev, iclass 39, count 2 2006.175.07:40:10.08#ibcon#first serial, iclass 39, count 2 2006.175.07:40:10.08#ibcon#enter sib2, iclass 39, count 2 2006.175.07:40:10.08#ibcon#flushed, iclass 39, count 2 2006.175.07:40:10.08#ibcon#about to write, iclass 39, count 2 2006.175.07:40:10.08#ibcon#wrote, iclass 39, count 2 2006.175.07:40:10.08#ibcon#about to read 3, iclass 39, count 2 2006.175.07:40:10.10#ibcon#read 3, iclass 39, count 2 2006.175.07:40:10.10#ibcon#about to read 4, iclass 39, count 2 2006.175.07:40:10.10#ibcon#read 4, iclass 39, count 2 2006.175.07:40:10.10#ibcon#about to read 5, iclass 39, count 2 2006.175.07:40:10.10#ibcon#read 5, iclass 39, count 2 2006.175.07:40:10.10#ibcon#about to read 6, iclass 39, count 2 2006.175.07:40:10.10#ibcon#read 6, iclass 39, count 2 2006.175.07:40:10.10#ibcon#end of sib2, iclass 39, count 2 2006.175.07:40:10.10#ibcon#*mode == 0, iclass 39, count 2 2006.175.07:40:10.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.175.07:40:10.10#ibcon#[25=AT07-06\r\n] 2006.175.07:40:10.10#ibcon#*before write, iclass 39, count 2 2006.175.07:40:10.10#ibcon#enter sib2, iclass 39, count 2 2006.175.07:40:10.10#ibcon#flushed, iclass 39, count 2 2006.175.07:40:10.10#ibcon#about to write, iclass 39, count 2 2006.175.07:40:10.10#ibcon#wrote, iclass 39, count 2 2006.175.07:40:10.10#ibcon#about to read 3, iclass 39, count 2 2006.175.07:40:10.13#ibcon#read 3, iclass 39, count 2 2006.175.07:40:10.13#ibcon#about to read 4, iclass 39, count 2 2006.175.07:40:10.13#ibcon#read 4, iclass 39, count 2 2006.175.07:40:10.13#ibcon#about to read 5, iclass 39, count 2 2006.175.07:40:10.13#ibcon#read 5, iclass 39, count 2 2006.175.07:40:10.13#ibcon#about to read 6, iclass 39, count 2 2006.175.07:40:10.13#ibcon#read 6, iclass 39, count 2 2006.175.07:40:10.13#ibcon#end of sib2, iclass 39, count 2 2006.175.07:40:10.13#ibcon#*after write, iclass 39, count 2 2006.175.07:40:10.13#ibcon#*before return 0, iclass 39, count 2 2006.175.07:40:10.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:40:10.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:40:10.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.175.07:40:10.13#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:10.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:40:10.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:40:10.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:40:10.25#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:40:10.25#ibcon#first serial, iclass 39, count 0 2006.175.07:40:10.25#ibcon#enter sib2, iclass 39, count 0 2006.175.07:40:10.25#ibcon#flushed, iclass 39, count 0 2006.175.07:40:10.25#ibcon#about to write, iclass 39, count 0 2006.175.07:40:10.25#ibcon#wrote, iclass 39, count 0 2006.175.07:40:10.25#ibcon#about to read 3, iclass 39, count 0 2006.175.07:40:10.27#ibcon#read 3, iclass 39, count 0 2006.175.07:40:10.27#ibcon#about to read 4, iclass 39, count 0 2006.175.07:40:10.27#ibcon#read 4, iclass 39, count 0 2006.175.07:40:10.27#ibcon#about to read 5, iclass 39, count 0 2006.175.07:40:10.27#ibcon#read 5, iclass 39, count 0 2006.175.07:40:10.27#ibcon#about to read 6, iclass 39, count 0 2006.175.07:40:10.27#ibcon#read 6, iclass 39, count 0 2006.175.07:40:10.27#ibcon#end of sib2, iclass 39, count 0 2006.175.07:40:10.27#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:40:10.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:40:10.27#ibcon#[25=USB\r\n] 2006.175.07:40:10.27#ibcon#*before write, iclass 39, count 0 2006.175.07:40:10.27#ibcon#enter sib2, iclass 39, count 0 2006.175.07:40:10.27#ibcon#flushed, iclass 39, count 0 2006.175.07:40:10.27#ibcon#about to write, iclass 39, count 0 2006.175.07:40:10.27#ibcon#wrote, iclass 39, count 0 2006.175.07:40:10.27#ibcon#about to read 3, iclass 39, count 0 2006.175.07:40:10.30#ibcon#read 3, iclass 39, count 0 2006.175.07:40:10.30#ibcon#about to read 4, iclass 39, count 0 2006.175.07:40:10.30#ibcon#read 4, iclass 39, count 0 2006.175.07:40:10.30#ibcon#about to read 5, iclass 39, count 0 2006.175.07:40:10.30#ibcon#read 5, iclass 39, count 0 2006.175.07:40:10.30#ibcon#about to read 6, iclass 39, count 0 2006.175.07:40:10.30#ibcon#read 6, iclass 39, count 0 2006.175.07:40:10.30#ibcon#end of sib2, iclass 39, count 0 2006.175.07:40:10.30#ibcon#*after write, iclass 39, count 0 2006.175.07:40:10.30#ibcon#*before return 0, iclass 39, count 0 2006.175.07:40:10.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:40:10.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:40:10.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:40:10.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:40:10.30$vc4f8/valo=8,852.99 2006.175.07:40:10.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.07:40:10.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.07:40:10.30#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:10.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:40:10.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:40:10.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:40:10.30#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:40:10.30#ibcon#first serial, iclass 3, count 0 2006.175.07:40:10.30#ibcon#enter sib2, iclass 3, count 0 2006.175.07:40:10.30#ibcon#flushed, iclass 3, count 0 2006.175.07:40:10.30#ibcon#about to write, iclass 3, count 0 2006.175.07:40:10.30#ibcon#wrote, iclass 3, count 0 2006.175.07:40:10.30#ibcon#about to read 3, iclass 3, count 0 2006.175.07:40:10.32#ibcon#read 3, iclass 3, count 0 2006.175.07:40:10.32#ibcon#about to read 4, iclass 3, count 0 2006.175.07:40:10.32#ibcon#read 4, iclass 3, count 0 2006.175.07:40:10.32#ibcon#about to read 5, iclass 3, count 0 2006.175.07:40:10.32#ibcon#read 5, iclass 3, count 0 2006.175.07:40:10.32#ibcon#about to read 6, iclass 3, count 0 2006.175.07:40:10.32#ibcon#read 6, iclass 3, count 0 2006.175.07:40:10.32#ibcon#end of sib2, iclass 3, count 0 2006.175.07:40:10.32#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:40:10.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:40:10.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:40:10.32#ibcon#*before write, iclass 3, count 0 2006.175.07:40:10.32#ibcon#enter sib2, iclass 3, count 0 2006.175.07:40:10.32#ibcon#flushed, iclass 3, count 0 2006.175.07:40:10.32#ibcon#about to write, iclass 3, count 0 2006.175.07:40:10.32#ibcon#wrote, iclass 3, count 0 2006.175.07:40:10.32#ibcon#about to read 3, iclass 3, count 0 2006.175.07:40:10.36#ibcon#read 3, iclass 3, count 0 2006.175.07:40:10.36#ibcon#about to read 4, iclass 3, count 0 2006.175.07:40:10.36#ibcon#read 4, iclass 3, count 0 2006.175.07:40:10.36#ibcon#about to read 5, iclass 3, count 0 2006.175.07:40:10.36#ibcon#read 5, iclass 3, count 0 2006.175.07:40:10.36#ibcon#about to read 6, iclass 3, count 0 2006.175.07:40:10.36#ibcon#read 6, iclass 3, count 0 2006.175.07:40:10.36#ibcon#end of sib2, iclass 3, count 0 2006.175.07:40:10.36#ibcon#*after write, iclass 3, count 0 2006.175.07:40:10.36#ibcon#*before return 0, iclass 3, count 0 2006.175.07:40:10.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:40:10.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:40:10.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:40:10.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:40:10.36$vc4f8/va=8,6 2006.175.07:40:10.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.175.07:40:10.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.175.07:40:10.36#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:10.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:40:10.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:40:10.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:40:10.42#ibcon#enter wrdev, iclass 5, count 2 2006.175.07:40:10.42#ibcon#first serial, iclass 5, count 2 2006.175.07:40:10.42#ibcon#enter sib2, iclass 5, count 2 2006.175.07:40:10.42#ibcon#flushed, iclass 5, count 2 2006.175.07:40:10.42#ibcon#about to write, iclass 5, count 2 2006.175.07:40:10.42#ibcon#wrote, iclass 5, count 2 2006.175.07:40:10.42#ibcon#about to read 3, iclass 5, count 2 2006.175.07:40:10.44#ibcon#read 3, iclass 5, count 2 2006.175.07:40:10.44#ibcon#about to read 4, iclass 5, count 2 2006.175.07:40:10.44#ibcon#read 4, iclass 5, count 2 2006.175.07:40:10.44#ibcon#about to read 5, iclass 5, count 2 2006.175.07:40:10.44#ibcon#read 5, iclass 5, count 2 2006.175.07:40:10.44#ibcon#about to read 6, iclass 5, count 2 2006.175.07:40:10.44#ibcon#read 6, iclass 5, count 2 2006.175.07:40:10.44#ibcon#end of sib2, iclass 5, count 2 2006.175.07:40:10.44#ibcon#*mode == 0, iclass 5, count 2 2006.175.07:40:10.44#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.175.07:40:10.44#ibcon#[25=AT08-06\r\n] 2006.175.07:40:10.44#ibcon#*before write, iclass 5, count 2 2006.175.07:40:10.44#ibcon#enter sib2, iclass 5, count 2 2006.175.07:40:10.44#ibcon#flushed, iclass 5, count 2 2006.175.07:40:10.44#ibcon#about to write, iclass 5, count 2 2006.175.07:40:10.44#ibcon#wrote, iclass 5, count 2 2006.175.07:40:10.44#ibcon#about to read 3, iclass 5, count 2 2006.175.07:40:10.47#ibcon#read 3, iclass 5, count 2 2006.175.07:40:10.47#ibcon#about to read 4, iclass 5, count 2 2006.175.07:40:10.47#ibcon#read 4, iclass 5, count 2 2006.175.07:40:10.47#ibcon#about to read 5, iclass 5, count 2 2006.175.07:40:10.47#ibcon#read 5, iclass 5, count 2 2006.175.07:40:10.47#ibcon#about to read 6, iclass 5, count 2 2006.175.07:40:10.47#ibcon#read 6, iclass 5, count 2 2006.175.07:40:10.47#ibcon#end of sib2, iclass 5, count 2 2006.175.07:40:10.47#ibcon#*after write, iclass 5, count 2 2006.175.07:40:10.47#ibcon#*before return 0, iclass 5, count 2 2006.175.07:40:10.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:40:10.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:40:10.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.175.07:40:10.47#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:10.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:40:10.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:40:10.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:40:10.59#ibcon#enter wrdev, iclass 5, count 0 2006.175.07:40:10.59#ibcon#first serial, iclass 5, count 0 2006.175.07:40:10.59#ibcon#enter sib2, iclass 5, count 0 2006.175.07:40:10.59#ibcon#flushed, iclass 5, count 0 2006.175.07:40:10.59#ibcon#about to write, iclass 5, count 0 2006.175.07:40:10.59#ibcon#wrote, iclass 5, count 0 2006.175.07:40:10.59#ibcon#about to read 3, iclass 5, count 0 2006.175.07:40:10.61#ibcon#read 3, iclass 5, count 0 2006.175.07:40:10.61#ibcon#about to read 4, iclass 5, count 0 2006.175.07:40:10.61#ibcon#read 4, iclass 5, count 0 2006.175.07:40:10.61#ibcon#about to read 5, iclass 5, count 0 2006.175.07:40:10.61#ibcon#read 5, iclass 5, count 0 2006.175.07:40:10.61#ibcon#about to read 6, iclass 5, count 0 2006.175.07:40:10.61#ibcon#read 6, iclass 5, count 0 2006.175.07:40:10.61#ibcon#end of sib2, iclass 5, count 0 2006.175.07:40:10.61#ibcon#*mode == 0, iclass 5, count 0 2006.175.07:40:10.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.07:40:10.61#ibcon#[25=USB\r\n] 2006.175.07:40:10.61#ibcon#*before write, iclass 5, count 0 2006.175.07:40:10.61#ibcon#enter sib2, iclass 5, count 0 2006.175.07:40:10.61#ibcon#flushed, iclass 5, count 0 2006.175.07:40:10.61#ibcon#about to write, iclass 5, count 0 2006.175.07:40:10.61#ibcon#wrote, iclass 5, count 0 2006.175.07:40:10.61#ibcon#about to read 3, iclass 5, count 0 2006.175.07:40:10.64#ibcon#read 3, iclass 5, count 0 2006.175.07:40:10.64#ibcon#about to read 4, iclass 5, count 0 2006.175.07:40:10.64#ibcon#read 4, iclass 5, count 0 2006.175.07:40:10.64#ibcon#about to read 5, iclass 5, count 0 2006.175.07:40:10.64#ibcon#read 5, iclass 5, count 0 2006.175.07:40:10.64#ibcon#about to read 6, iclass 5, count 0 2006.175.07:40:10.64#ibcon#read 6, iclass 5, count 0 2006.175.07:40:10.64#ibcon#end of sib2, iclass 5, count 0 2006.175.07:40:10.64#ibcon#*after write, iclass 5, count 0 2006.175.07:40:10.64#ibcon#*before return 0, iclass 5, count 0 2006.175.07:40:10.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:40:10.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:40:10.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.07:40:10.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.07:40:10.64$vc4f8/vblo=1,632.99 2006.175.07:40:10.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.07:40:10.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.07:40:10.64#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:10.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:10.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:10.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:10.64#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:40:10.64#ibcon#first serial, iclass 7, count 0 2006.175.07:40:10.64#ibcon#enter sib2, iclass 7, count 0 2006.175.07:40:10.64#ibcon#flushed, iclass 7, count 0 2006.175.07:40:10.64#ibcon#about to write, iclass 7, count 0 2006.175.07:40:10.64#ibcon#wrote, iclass 7, count 0 2006.175.07:40:10.64#ibcon#about to read 3, iclass 7, count 0 2006.175.07:40:10.66#ibcon#read 3, iclass 7, count 0 2006.175.07:40:10.66#ibcon#about to read 4, iclass 7, count 0 2006.175.07:40:10.66#ibcon#read 4, iclass 7, count 0 2006.175.07:40:10.66#ibcon#about to read 5, iclass 7, count 0 2006.175.07:40:10.66#ibcon#read 5, iclass 7, count 0 2006.175.07:40:10.66#ibcon#about to read 6, iclass 7, count 0 2006.175.07:40:10.66#ibcon#read 6, iclass 7, count 0 2006.175.07:40:10.66#ibcon#end of sib2, iclass 7, count 0 2006.175.07:40:10.66#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:40:10.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:40:10.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:40:10.66#ibcon#*before write, iclass 7, count 0 2006.175.07:40:10.66#ibcon#enter sib2, iclass 7, count 0 2006.175.07:40:10.66#ibcon#flushed, iclass 7, count 0 2006.175.07:40:10.66#ibcon#about to write, iclass 7, count 0 2006.175.07:40:10.66#ibcon#wrote, iclass 7, count 0 2006.175.07:40:10.66#ibcon#about to read 3, iclass 7, count 0 2006.175.07:40:10.70#ibcon#read 3, iclass 7, count 0 2006.175.07:40:10.70#ibcon#about to read 4, iclass 7, count 0 2006.175.07:40:10.70#ibcon#read 4, iclass 7, count 0 2006.175.07:40:10.70#ibcon#about to read 5, iclass 7, count 0 2006.175.07:40:10.70#ibcon#read 5, iclass 7, count 0 2006.175.07:40:10.70#ibcon#about to read 6, iclass 7, count 0 2006.175.07:40:10.70#ibcon#read 6, iclass 7, count 0 2006.175.07:40:10.70#ibcon#end of sib2, iclass 7, count 0 2006.175.07:40:10.70#ibcon#*after write, iclass 7, count 0 2006.175.07:40:10.70#ibcon#*before return 0, iclass 7, count 0 2006.175.07:40:10.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:10.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:40:10.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:40:10.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:40:10.70$vc4f8/vb=1,4 2006.175.07:40:10.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.175.07:40:10.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.175.07:40:10.70#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:10.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:10.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:10.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:10.70#ibcon#enter wrdev, iclass 11, count 2 2006.175.07:40:10.70#ibcon#first serial, iclass 11, count 2 2006.175.07:40:10.70#ibcon#enter sib2, iclass 11, count 2 2006.175.07:40:10.70#ibcon#flushed, iclass 11, count 2 2006.175.07:40:10.70#ibcon#about to write, iclass 11, count 2 2006.175.07:40:10.70#ibcon#wrote, iclass 11, count 2 2006.175.07:40:10.70#ibcon#about to read 3, iclass 11, count 2 2006.175.07:40:10.72#ibcon#read 3, iclass 11, count 2 2006.175.07:40:10.72#ibcon#about to read 4, iclass 11, count 2 2006.175.07:40:10.72#ibcon#read 4, iclass 11, count 2 2006.175.07:40:10.72#ibcon#about to read 5, iclass 11, count 2 2006.175.07:40:10.72#ibcon#read 5, iclass 11, count 2 2006.175.07:40:10.72#ibcon#about to read 6, iclass 11, count 2 2006.175.07:40:10.72#ibcon#read 6, iclass 11, count 2 2006.175.07:40:10.72#ibcon#end of sib2, iclass 11, count 2 2006.175.07:40:10.72#ibcon#*mode == 0, iclass 11, count 2 2006.175.07:40:10.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.175.07:40:10.72#ibcon#[27=AT01-04\r\n] 2006.175.07:40:10.72#ibcon#*before write, iclass 11, count 2 2006.175.07:40:10.72#ibcon#enter sib2, iclass 11, count 2 2006.175.07:40:10.72#ibcon#flushed, iclass 11, count 2 2006.175.07:40:10.72#ibcon#about to write, iclass 11, count 2 2006.175.07:40:10.72#ibcon#wrote, iclass 11, count 2 2006.175.07:40:10.72#ibcon#about to read 3, iclass 11, count 2 2006.175.07:40:10.75#ibcon#read 3, iclass 11, count 2 2006.175.07:40:10.75#ibcon#about to read 4, iclass 11, count 2 2006.175.07:40:10.75#ibcon#read 4, iclass 11, count 2 2006.175.07:40:10.75#ibcon#about to read 5, iclass 11, count 2 2006.175.07:40:10.75#ibcon#read 5, iclass 11, count 2 2006.175.07:40:10.75#ibcon#about to read 6, iclass 11, count 2 2006.175.07:40:10.75#ibcon#read 6, iclass 11, count 2 2006.175.07:40:10.75#ibcon#end of sib2, iclass 11, count 2 2006.175.07:40:10.75#ibcon#*after write, iclass 11, count 2 2006.175.07:40:10.75#ibcon#*before return 0, iclass 11, count 2 2006.175.07:40:10.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:10.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:40:10.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.175.07:40:10.75#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:10.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:10.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:10.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:10.87#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:40:10.87#ibcon#first serial, iclass 11, count 0 2006.175.07:40:10.87#ibcon#enter sib2, iclass 11, count 0 2006.175.07:40:10.87#ibcon#flushed, iclass 11, count 0 2006.175.07:40:10.87#ibcon#about to write, iclass 11, count 0 2006.175.07:40:10.87#ibcon#wrote, iclass 11, count 0 2006.175.07:40:10.87#ibcon#about to read 3, iclass 11, count 0 2006.175.07:40:10.89#ibcon#read 3, iclass 11, count 0 2006.175.07:40:10.89#ibcon#about to read 4, iclass 11, count 0 2006.175.07:40:10.89#ibcon#read 4, iclass 11, count 0 2006.175.07:40:10.89#ibcon#about to read 5, iclass 11, count 0 2006.175.07:40:10.89#ibcon#read 5, iclass 11, count 0 2006.175.07:40:10.89#ibcon#about to read 6, iclass 11, count 0 2006.175.07:40:10.89#ibcon#read 6, iclass 11, count 0 2006.175.07:40:10.89#ibcon#end of sib2, iclass 11, count 0 2006.175.07:40:10.89#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:40:10.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:40:10.89#ibcon#[27=USB\r\n] 2006.175.07:40:10.89#ibcon#*before write, iclass 11, count 0 2006.175.07:40:10.89#ibcon#enter sib2, iclass 11, count 0 2006.175.07:40:10.89#ibcon#flushed, iclass 11, count 0 2006.175.07:40:10.89#ibcon#about to write, iclass 11, count 0 2006.175.07:40:10.89#ibcon#wrote, iclass 11, count 0 2006.175.07:40:10.89#ibcon#about to read 3, iclass 11, count 0 2006.175.07:40:10.92#ibcon#read 3, iclass 11, count 0 2006.175.07:40:10.92#ibcon#about to read 4, iclass 11, count 0 2006.175.07:40:10.92#ibcon#read 4, iclass 11, count 0 2006.175.07:40:10.92#ibcon#about to read 5, iclass 11, count 0 2006.175.07:40:10.92#ibcon#read 5, iclass 11, count 0 2006.175.07:40:10.92#ibcon#about to read 6, iclass 11, count 0 2006.175.07:40:10.92#ibcon#read 6, iclass 11, count 0 2006.175.07:40:10.92#ibcon#end of sib2, iclass 11, count 0 2006.175.07:40:10.92#ibcon#*after write, iclass 11, count 0 2006.175.07:40:10.92#ibcon#*before return 0, iclass 11, count 0 2006.175.07:40:10.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:10.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:40:10.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:40:10.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:40:10.92$vc4f8/vblo=2,640.99 2006.175.07:40:10.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.175.07:40:10.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.175.07:40:10.92#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:10.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:10.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:10.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:10.92#ibcon#enter wrdev, iclass 13, count 0 2006.175.07:40:10.92#ibcon#first serial, iclass 13, count 0 2006.175.07:40:10.92#ibcon#enter sib2, iclass 13, count 0 2006.175.07:40:10.92#ibcon#flushed, iclass 13, count 0 2006.175.07:40:10.92#ibcon#about to write, iclass 13, count 0 2006.175.07:40:10.92#ibcon#wrote, iclass 13, count 0 2006.175.07:40:10.92#ibcon#about to read 3, iclass 13, count 0 2006.175.07:40:10.94#ibcon#read 3, iclass 13, count 0 2006.175.07:40:10.94#ibcon#about to read 4, iclass 13, count 0 2006.175.07:40:10.94#ibcon#read 4, iclass 13, count 0 2006.175.07:40:10.94#ibcon#about to read 5, iclass 13, count 0 2006.175.07:40:10.94#ibcon#read 5, iclass 13, count 0 2006.175.07:40:10.94#ibcon#about to read 6, iclass 13, count 0 2006.175.07:40:10.94#ibcon#read 6, iclass 13, count 0 2006.175.07:40:10.94#ibcon#end of sib2, iclass 13, count 0 2006.175.07:40:10.94#ibcon#*mode == 0, iclass 13, count 0 2006.175.07:40:10.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.07:40:10.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:40:10.94#ibcon#*before write, iclass 13, count 0 2006.175.07:40:10.94#ibcon#enter sib2, iclass 13, count 0 2006.175.07:40:10.94#ibcon#flushed, iclass 13, count 0 2006.175.07:40:10.94#ibcon#about to write, iclass 13, count 0 2006.175.07:40:10.94#ibcon#wrote, iclass 13, count 0 2006.175.07:40:10.94#ibcon#about to read 3, iclass 13, count 0 2006.175.07:40:10.98#ibcon#read 3, iclass 13, count 0 2006.175.07:40:10.98#ibcon#about to read 4, iclass 13, count 0 2006.175.07:40:10.98#ibcon#read 4, iclass 13, count 0 2006.175.07:40:10.98#ibcon#about to read 5, iclass 13, count 0 2006.175.07:40:10.98#ibcon#read 5, iclass 13, count 0 2006.175.07:40:10.98#ibcon#about to read 6, iclass 13, count 0 2006.175.07:40:10.98#ibcon#read 6, iclass 13, count 0 2006.175.07:40:10.98#ibcon#end of sib2, iclass 13, count 0 2006.175.07:40:10.98#ibcon#*after write, iclass 13, count 0 2006.175.07:40:10.98#ibcon#*before return 0, iclass 13, count 0 2006.175.07:40:10.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:10.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:40:10.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.07:40:10.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.07:40:10.98$vc4f8/vb=2,4 2006.175.07:40:10.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.175.07:40:10.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.175.07:40:10.98#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:10.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:11.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:11.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:11.04#ibcon#enter wrdev, iclass 15, count 2 2006.175.07:40:11.04#ibcon#first serial, iclass 15, count 2 2006.175.07:40:11.04#ibcon#enter sib2, iclass 15, count 2 2006.175.07:40:11.04#ibcon#flushed, iclass 15, count 2 2006.175.07:40:11.04#ibcon#about to write, iclass 15, count 2 2006.175.07:40:11.04#ibcon#wrote, iclass 15, count 2 2006.175.07:40:11.04#ibcon#about to read 3, iclass 15, count 2 2006.175.07:40:11.06#ibcon#read 3, iclass 15, count 2 2006.175.07:40:11.06#ibcon#about to read 4, iclass 15, count 2 2006.175.07:40:11.06#ibcon#read 4, iclass 15, count 2 2006.175.07:40:11.06#ibcon#about to read 5, iclass 15, count 2 2006.175.07:40:11.06#ibcon#read 5, iclass 15, count 2 2006.175.07:40:11.06#ibcon#about to read 6, iclass 15, count 2 2006.175.07:40:11.06#ibcon#read 6, iclass 15, count 2 2006.175.07:40:11.06#ibcon#end of sib2, iclass 15, count 2 2006.175.07:40:11.06#ibcon#*mode == 0, iclass 15, count 2 2006.175.07:40:11.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.175.07:40:11.06#ibcon#[27=AT02-04\r\n] 2006.175.07:40:11.06#ibcon#*before write, iclass 15, count 2 2006.175.07:40:11.06#ibcon#enter sib2, iclass 15, count 2 2006.175.07:40:11.06#ibcon#flushed, iclass 15, count 2 2006.175.07:40:11.06#ibcon#about to write, iclass 15, count 2 2006.175.07:40:11.06#ibcon#wrote, iclass 15, count 2 2006.175.07:40:11.06#ibcon#about to read 3, iclass 15, count 2 2006.175.07:40:11.09#ibcon#read 3, iclass 15, count 2 2006.175.07:40:11.09#ibcon#about to read 4, iclass 15, count 2 2006.175.07:40:11.09#ibcon#read 4, iclass 15, count 2 2006.175.07:40:11.09#ibcon#about to read 5, iclass 15, count 2 2006.175.07:40:11.09#ibcon#read 5, iclass 15, count 2 2006.175.07:40:11.09#ibcon#about to read 6, iclass 15, count 2 2006.175.07:40:11.09#ibcon#read 6, iclass 15, count 2 2006.175.07:40:11.09#ibcon#end of sib2, iclass 15, count 2 2006.175.07:40:11.09#ibcon#*after write, iclass 15, count 2 2006.175.07:40:11.09#ibcon#*before return 0, iclass 15, count 2 2006.175.07:40:11.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:11.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:40:11.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.175.07:40:11.09#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:11.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:11.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:11.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:11.21#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:40:11.21#ibcon#first serial, iclass 15, count 0 2006.175.07:40:11.21#ibcon#enter sib2, iclass 15, count 0 2006.175.07:40:11.21#ibcon#flushed, iclass 15, count 0 2006.175.07:40:11.21#ibcon#about to write, iclass 15, count 0 2006.175.07:40:11.21#ibcon#wrote, iclass 15, count 0 2006.175.07:40:11.21#ibcon#about to read 3, iclass 15, count 0 2006.175.07:40:11.23#ibcon#read 3, iclass 15, count 0 2006.175.07:40:11.23#ibcon#about to read 4, iclass 15, count 0 2006.175.07:40:11.23#ibcon#read 4, iclass 15, count 0 2006.175.07:40:11.23#ibcon#about to read 5, iclass 15, count 0 2006.175.07:40:11.23#ibcon#read 5, iclass 15, count 0 2006.175.07:40:11.23#ibcon#about to read 6, iclass 15, count 0 2006.175.07:40:11.23#ibcon#read 6, iclass 15, count 0 2006.175.07:40:11.23#ibcon#end of sib2, iclass 15, count 0 2006.175.07:40:11.23#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:40:11.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:40:11.23#ibcon#[27=USB\r\n] 2006.175.07:40:11.23#ibcon#*before write, iclass 15, count 0 2006.175.07:40:11.23#ibcon#enter sib2, iclass 15, count 0 2006.175.07:40:11.23#ibcon#flushed, iclass 15, count 0 2006.175.07:40:11.23#ibcon#about to write, iclass 15, count 0 2006.175.07:40:11.23#ibcon#wrote, iclass 15, count 0 2006.175.07:40:11.23#ibcon#about to read 3, iclass 15, count 0 2006.175.07:40:11.26#ibcon#read 3, iclass 15, count 0 2006.175.07:40:11.26#ibcon#about to read 4, iclass 15, count 0 2006.175.07:40:11.26#ibcon#read 4, iclass 15, count 0 2006.175.07:40:11.26#ibcon#about to read 5, iclass 15, count 0 2006.175.07:40:11.26#ibcon#read 5, iclass 15, count 0 2006.175.07:40:11.26#ibcon#about to read 6, iclass 15, count 0 2006.175.07:40:11.26#ibcon#read 6, iclass 15, count 0 2006.175.07:40:11.26#ibcon#end of sib2, iclass 15, count 0 2006.175.07:40:11.26#ibcon#*after write, iclass 15, count 0 2006.175.07:40:11.26#ibcon#*before return 0, iclass 15, count 0 2006.175.07:40:11.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:11.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:40:11.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:40:11.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:40:11.26$vc4f8/vblo=3,656.99 2006.175.07:40:11.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.07:40:11.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.07:40:11.26#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:11.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:11.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:11.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:11.26#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:40:11.26#ibcon#first serial, iclass 17, count 0 2006.175.07:40:11.26#ibcon#enter sib2, iclass 17, count 0 2006.175.07:40:11.26#ibcon#flushed, iclass 17, count 0 2006.175.07:40:11.26#ibcon#about to write, iclass 17, count 0 2006.175.07:40:11.26#ibcon#wrote, iclass 17, count 0 2006.175.07:40:11.26#ibcon#about to read 3, iclass 17, count 0 2006.175.07:40:11.28#ibcon#read 3, iclass 17, count 0 2006.175.07:40:11.28#ibcon#about to read 4, iclass 17, count 0 2006.175.07:40:11.28#ibcon#read 4, iclass 17, count 0 2006.175.07:40:11.28#ibcon#about to read 5, iclass 17, count 0 2006.175.07:40:11.28#ibcon#read 5, iclass 17, count 0 2006.175.07:40:11.28#ibcon#about to read 6, iclass 17, count 0 2006.175.07:40:11.28#ibcon#read 6, iclass 17, count 0 2006.175.07:40:11.28#ibcon#end of sib2, iclass 17, count 0 2006.175.07:40:11.28#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:40:11.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:40:11.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:40:11.28#ibcon#*before write, iclass 17, count 0 2006.175.07:40:11.28#ibcon#enter sib2, iclass 17, count 0 2006.175.07:40:11.28#ibcon#flushed, iclass 17, count 0 2006.175.07:40:11.28#ibcon#about to write, iclass 17, count 0 2006.175.07:40:11.28#ibcon#wrote, iclass 17, count 0 2006.175.07:40:11.28#ibcon#about to read 3, iclass 17, count 0 2006.175.07:40:11.32#ibcon#read 3, iclass 17, count 0 2006.175.07:40:11.32#ibcon#about to read 4, iclass 17, count 0 2006.175.07:40:11.32#ibcon#read 4, iclass 17, count 0 2006.175.07:40:11.32#ibcon#about to read 5, iclass 17, count 0 2006.175.07:40:11.32#ibcon#read 5, iclass 17, count 0 2006.175.07:40:11.32#ibcon#about to read 6, iclass 17, count 0 2006.175.07:40:11.32#ibcon#read 6, iclass 17, count 0 2006.175.07:40:11.32#ibcon#end of sib2, iclass 17, count 0 2006.175.07:40:11.32#ibcon#*after write, iclass 17, count 0 2006.175.07:40:11.32#ibcon#*before return 0, iclass 17, count 0 2006.175.07:40:11.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:11.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:40:11.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:40:11.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:40:11.32$vc4f8/vb=3,4 2006.175.07:40:11.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.175.07:40:11.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.175.07:40:11.32#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:11.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:11.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:11.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:11.38#ibcon#enter wrdev, iclass 19, count 2 2006.175.07:40:11.38#ibcon#first serial, iclass 19, count 2 2006.175.07:40:11.38#ibcon#enter sib2, iclass 19, count 2 2006.175.07:40:11.38#ibcon#flushed, iclass 19, count 2 2006.175.07:40:11.38#ibcon#about to write, iclass 19, count 2 2006.175.07:40:11.38#ibcon#wrote, iclass 19, count 2 2006.175.07:40:11.38#ibcon#about to read 3, iclass 19, count 2 2006.175.07:40:11.40#ibcon#read 3, iclass 19, count 2 2006.175.07:40:11.40#ibcon#about to read 4, iclass 19, count 2 2006.175.07:40:11.40#ibcon#read 4, iclass 19, count 2 2006.175.07:40:11.40#ibcon#about to read 5, iclass 19, count 2 2006.175.07:40:11.40#ibcon#read 5, iclass 19, count 2 2006.175.07:40:11.40#ibcon#about to read 6, iclass 19, count 2 2006.175.07:40:11.40#ibcon#read 6, iclass 19, count 2 2006.175.07:40:11.40#ibcon#end of sib2, iclass 19, count 2 2006.175.07:40:11.40#ibcon#*mode == 0, iclass 19, count 2 2006.175.07:40:11.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.175.07:40:11.40#ibcon#[27=AT03-04\r\n] 2006.175.07:40:11.40#ibcon#*before write, iclass 19, count 2 2006.175.07:40:11.40#ibcon#enter sib2, iclass 19, count 2 2006.175.07:40:11.40#ibcon#flushed, iclass 19, count 2 2006.175.07:40:11.40#ibcon#about to write, iclass 19, count 2 2006.175.07:40:11.40#ibcon#wrote, iclass 19, count 2 2006.175.07:40:11.40#ibcon#about to read 3, iclass 19, count 2 2006.175.07:40:11.43#ibcon#read 3, iclass 19, count 2 2006.175.07:40:11.43#ibcon#about to read 4, iclass 19, count 2 2006.175.07:40:11.43#ibcon#read 4, iclass 19, count 2 2006.175.07:40:11.43#ibcon#about to read 5, iclass 19, count 2 2006.175.07:40:11.43#ibcon#read 5, iclass 19, count 2 2006.175.07:40:11.43#ibcon#about to read 6, iclass 19, count 2 2006.175.07:40:11.43#ibcon#read 6, iclass 19, count 2 2006.175.07:40:11.43#ibcon#end of sib2, iclass 19, count 2 2006.175.07:40:11.43#ibcon#*after write, iclass 19, count 2 2006.175.07:40:11.43#ibcon#*before return 0, iclass 19, count 2 2006.175.07:40:11.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:11.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:40:11.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.175.07:40:11.43#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:11.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:11.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:11.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:11.55#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:40:11.55#ibcon#first serial, iclass 19, count 0 2006.175.07:40:11.55#ibcon#enter sib2, iclass 19, count 0 2006.175.07:40:11.55#ibcon#flushed, iclass 19, count 0 2006.175.07:40:11.55#ibcon#about to write, iclass 19, count 0 2006.175.07:40:11.55#ibcon#wrote, iclass 19, count 0 2006.175.07:40:11.55#ibcon#about to read 3, iclass 19, count 0 2006.175.07:40:11.57#ibcon#read 3, iclass 19, count 0 2006.175.07:40:11.57#ibcon#about to read 4, iclass 19, count 0 2006.175.07:40:11.57#ibcon#read 4, iclass 19, count 0 2006.175.07:40:11.57#ibcon#about to read 5, iclass 19, count 0 2006.175.07:40:11.57#ibcon#read 5, iclass 19, count 0 2006.175.07:40:11.57#ibcon#about to read 6, iclass 19, count 0 2006.175.07:40:11.57#ibcon#read 6, iclass 19, count 0 2006.175.07:40:11.57#ibcon#end of sib2, iclass 19, count 0 2006.175.07:40:11.57#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:40:11.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:40:11.57#ibcon#[27=USB\r\n] 2006.175.07:40:11.57#ibcon#*before write, iclass 19, count 0 2006.175.07:40:11.57#ibcon#enter sib2, iclass 19, count 0 2006.175.07:40:11.57#ibcon#flushed, iclass 19, count 0 2006.175.07:40:11.57#ibcon#about to write, iclass 19, count 0 2006.175.07:40:11.57#ibcon#wrote, iclass 19, count 0 2006.175.07:40:11.57#ibcon#about to read 3, iclass 19, count 0 2006.175.07:40:11.60#ibcon#read 3, iclass 19, count 0 2006.175.07:40:11.60#ibcon#about to read 4, iclass 19, count 0 2006.175.07:40:11.60#ibcon#read 4, iclass 19, count 0 2006.175.07:40:11.60#ibcon#about to read 5, iclass 19, count 0 2006.175.07:40:11.60#ibcon#read 5, iclass 19, count 0 2006.175.07:40:11.60#ibcon#about to read 6, iclass 19, count 0 2006.175.07:40:11.60#ibcon#read 6, iclass 19, count 0 2006.175.07:40:11.60#ibcon#end of sib2, iclass 19, count 0 2006.175.07:40:11.60#ibcon#*after write, iclass 19, count 0 2006.175.07:40:11.60#ibcon#*before return 0, iclass 19, count 0 2006.175.07:40:11.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:11.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:40:11.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:40:11.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:40:11.60$vc4f8/vblo=4,712.99 2006.175.07:40:11.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.07:40:11.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.07:40:11.60#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:11.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:11.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:11.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:11.60#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:40:11.60#ibcon#first serial, iclass 21, count 0 2006.175.07:40:11.60#ibcon#enter sib2, iclass 21, count 0 2006.175.07:40:11.60#ibcon#flushed, iclass 21, count 0 2006.175.07:40:11.60#ibcon#about to write, iclass 21, count 0 2006.175.07:40:11.60#ibcon#wrote, iclass 21, count 0 2006.175.07:40:11.60#ibcon#about to read 3, iclass 21, count 0 2006.175.07:40:11.62#ibcon#read 3, iclass 21, count 0 2006.175.07:40:11.62#ibcon#about to read 4, iclass 21, count 0 2006.175.07:40:11.62#ibcon#read 4, iclass 21, count 0 2006.175.07:40:11.62#ibcon#about to read 5, iclass 21, count 0 2006.175.07:40:11.62#ibcon#read 5, iclass 21, count 0 2006.175.07:40:11.62#ibcon#about to read 6, iclass 21, count 0 2006.175.07:40:11.62#ibcon#read 6, iclass 21, count 0 2006.175.07:40:11.62#ibcon#end of sib2, iclass 21, count 0 2006.175.07:40:11.62#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:40:11.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:40:11.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:40:11.62#ibcon#*before write, iclass 21, count 0 2006.175.07:40:11.62#ibcon#enter sib2, iclass 21, count 0 2006.175.07:40:11.62#ibcon#flushed, iclass 21, count 0 2006.175.07:40:11.62#ibcon#about to write, iclass 21, count 0 2006.175.07:40:11.62#ibcon#wrote, iclass 21, count 0 2006.175.07:40:11.62#ibcon#about to read 3, iclass 21, count 0 2006.175.07:40:11.66#ibcon#read 3, iclass 21, count 0 2006.175.07:40:11.66#ibcon#about to read 4, iclass 21, count 0 2006.175.07:40:11.66#ibcon#read 4, iclass 21, count 0 2006.175.07:40:11.66#ibcon#about to read 5, iclass 21, count 0 2006.175.07:40:11.66#ibcon#read 5, iclass 21, count 0 2006.175.07:40:11.66#ibcon#about to read 6, iclass 21, count 0 2006.175.07:40:11.66#ibcon#read 6, iclass 21, count 0 2006.175.07:40:11.66#ibcon#end of sib2, iclass 21, count 0 2006.175.07:40:11.66#ibcon#*after write, iclass 21, count 0 2006.175.07:40:11.66#ibcon#*before return 0, iclass 21, count 0 2006.175.07:40:11.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:11.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:40:11.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:40:11.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:40:11.66$vc4f8/vb=4,4 2006.175.07:40:11.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.07:40:11.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.07:40:11.66#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:11.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:11.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:11.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:11.72#ibcon#enter wrdev, iclass 23, count 2 2006.175.07:40:11.72#ibcon#first serial, iclass 23, count 2 2006.175.07:40:11.72#ibcon#enter sib2, iclass 23, count 2 2006.175.07:40:11.72#ibcon#flushed, iclass 23, count 2 2006.175.07:40:11.72#ibcon#about to write, iclass 23, count 2 2006.175.07:40:11.72#ibcon#wrote, iclass 23, count 2 2006.175.07:40:11.72#ibcon#about to read 3, iclass 23, count 2 2006.175.07:40:11.74#ibcon#read 3, iclass 23, count 2 2006.175.07:40:11.74#ibcon#about to read 4, iclass 23, count 2 2006.175.07:40:11.74#ibcon#read 4, iclass 23, count 2 2006.175.07:40:11.74#ibcon#about to read 5, iclass 23, count 2 2006.175.07:40:11.74#ibcon#read 5, iclass 23, count 2 2006.175.07:40:11.74#ibcon#about to read 6, iclass 23, count 2 2006.175.07:40:11.74#ibcon#read 6, iclass 23, count 2 2006.175.07:40:11.74#ibcon#end of sib2, iclass 23, count 2 2006.175.07:40:11.74#ibcon#*mode == 0, iclass 23, count 2 2006.175.07:40:11.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.07:40:11.74#ibcon#[27=AT04-04\r\n] 2006.175.07:40:11.74#ibcon#*before write, iclass 23, count 2 2006.175.07:40:11.74#ibcon#enter sib2, iclass 23, count 2 2006.175.07:40:11.74#ibcon#flushed, iclass 23, count 2 2006.175.07:40:11.74#ibcon#about to write, iclass 23, count 2 2006.175.07:40:11.74#ibcon#wrote, iclass 23, count 2 2006.175.07:40:11.74#ibcon#about to read 3, iclass 23, count 2 2006.175.07:40:11.77#ibcon#read 3, iclass 23, count 2 2006.175.07:40:11.77#ibcon#about to read 4, iclass 23, count 2 2006.175.07:40:11.77#ibcon#read 4, iclass 23, count 2 2006.175.07:40:11.77#ibcon#about to read 5, iclass 23, count 2 2006.175.07:40:11.77#ibcon#read 5, iclass 23, count 2 2006.175.07:40:11.77#ibcon#about to read 6, iclass 23, count 2 2006.175.07:40:11.77#ibcon#read 6, iclass 23, count 2 2006.175.07:40:11.77#ibcon#end of sib2, iclass 23, count 2 2006.175.07:40:11.77#ibcon#*after write, iclass 23, count 2 2006.175.07:40:11.77#ibcon#*before return 0, iclass 23, count 2 2006.175.07:40:11.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:11.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:40:11.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.07:40:11.77#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:11.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:11.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:11.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:11.89#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:40:11.89#ibcon#first serial, iclass 23, count 0 2006.175.07:40:11.89#ibcon#enter sib2, iclass 23, count 0 2006.175.07:40:11.89#ibcon#flushed, iclass 23, count 0 2006.175.07:40:11.89#ibcon#about to write, iclass 23, count 0 2006.175.07:40:11.89#ibcon#wrote, iclass 23, count 0 2006.175.07:40:11.89#ibcon#about to read 3, iclass 23, count 0 2006.175.07:40:11.91#ibcon#read 3, iclass 23, count 0 2006.175.07:40:11.91#ibcon#about to read 4, iclass 23, count 0 2006.175.07:40:11.91#ibcon#read 4, iclass 23, count 0 2006.175.07:40:11.91#ibcon#about to read 5, iclass 23, count 0 2006.175.07:40:11.91#ibcon#read 5, iclass 23, count 0 2006.175.07:40:11.91#ibcon#about to read 6, iclass 23, count 0 2006.175.07:40:11.91#ibcon#read 6, iclass 23, count 0 2006.175.07:40:11.91#ibcon#end of sib2, iclass 23, count 0 2006.175.07:40:11.91#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:40:11.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:40:11.91#ibcon#[27=USB\r\n] 2006.175.07:40:11.91#ibcon#*before write, iclass 23, count 0 2006.175.07:40:11.91#ibcon#enter sib2, iclass 23, count 0 2006.175.07:40:11.91#ibcon#flushed, iclass 23, count 0 2006.175.07:40:11.91#ibcon#about to write, iclass 23, count 0 2006.175.07:40:11.91#ibcon#wrote, iclass 23, count 0 2006.175.07:40:11.91#ibcon#about to read 3, iclass 23, count 0 2006.175.07:40:11.94#ibcon#read 3, iclass 23, count 0 2006.175.07:40:11.94#ibcon#about to read 4, iclass 23, count 0 2006.175.07:40:11.94#ibcon#read 4, iclass 23, count 0 2006.175.07:40:11.94#ibcon#about to read 5, iclass 23, count 0 2006.175.07:40:11.94#ibcon#read 5, iclass 23, count 0 2006.175.07:40:11.94#ibcon#about to read 6, iclass 23, count 0 2006.175.07:40:11.94#ibcon#read 6, iclass 23, count 0 2006.175.07:40:11.94#ibcon#end of sib2, iclass 23, count 0 2006.175.07:40:11.94#ibcon#*after write, iclass 23, count 0 2006.175.07:40:11.94#ibcon#*before return 0, iclass 23, count 0 2006.175.07:40:11.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:11.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:40:11.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:40:11.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:40:11.94$vc4f8/vblo=5,744.99 2006.175.07:40:11.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.07:40:11.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.07:40:11.94#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:11.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:40:11.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:40:11.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:40:11.94#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:40:11.94#ibcon#first serial, iclass 25, count 0 2006.175.07:40:11.94#ibcon#enter sib2, iclass 25, count 0 2006.175.07:40:11.94#ibcon#flushed, iclass 25, count 0 2006.175.07:40:11.94#ibcon#about to write, iclass 25, count 0 2006.175.07:40:11.94#ibcon#wrote, iclass 25, count 0 2006.175.07:40:11.94#ibcon#about to read 3, iclass 25, count 0 2006.175.07:40:11.96#ibcon#read 3, iclass 25, count 0 2006.175.07:40:11.96#ibcon#about to read 4, iclass 25, count 0 2006.175.07:40:11.96#ibcon#read 4, iclass 25, count 0 2006.175.07:40:11.96#ibcon#about to read 5, iclass 25, count 0 2006.175.07:40:11.96#ibcon#read 5, iclass 25, count 0 2006.175.07:40:11.96#ibcon#about to read 6, iclass 25, count 0 2006.175.07:40:11.96#ibcon#read 6, iclass 25, count 0 2006.175.07:40:11.96#ibcon#end of sib2, iclass 25, count 0 2006.175.07:40:11.96#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:40:11.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:40:11.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:40:11.96#ibcon#*before write, iclass 25, count 0 2006.175.07:40:11.96#ibcon#enter sib2, iclass 25, count 0 2006.175.07:40:11.96#ibcon#flushed, iclass 25, count 0 2006.175.07:40:11.96#ibcon#about to write, iclass 25, count 0 2006.175.07:40:11.96#ibcon#wrote, iclass 25, count 0 2006.175.07:40:11.96#ibcon#about to read 3, iclass 25, count 0 2006.175.07:40:12.00#ibcon#read 3, iclass 25, count 0 2006.175.07:40:12.00#ibcon#about to read 4, iclass 25, count 0 2006.175.07:40:12.00#ibcon#read 4, iclass 25, count 0 2006.175.07:40:12.00#ibcon#about to read 5, iclass 25, count 0 2006.175.07:40:12.00#ibcon#read 5, iclass 25, count 0 2006.175.07:40:12.00#ibcon#about to read 6, iclass 25, count 0 2006.175.07:40:12.00#ibcon#read 6, iclass 25, count 0 2006.175.07:40:12.00#ibcon#end of sib2, iclass 25, count 0 2006.175.07:40:12.00#ibcon#*after write, iclass 25, count 0 2006.175.07:40:12.00#ibcon#*before return 0, iclass 25, count 0 2006.175.07:40:12.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:40:12.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:40:12.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:40:12.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:40:12.00$vc4f8/vb=5,4 2006.175.07:40:12.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.07:40:12.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.07:40:12.00#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:12.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:40:12.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:40:12.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:40:12.06#ibcon#enter wrdev, iclass 27, count 2 2006.175.07:40:12.06#ibcon#first serial, iclass 27, count 2 2006.175.07:40:12.06#ibcon#enter sib2, iclass 27, count 2 2006.175.07:40:12.06#ibcon#flushed, iclass 27, count 2 2006.175.07:40:12.06#ibcon#about to write, iclass 27, count 2 2006.175.07:40:12.06#ibcon#wrote, iclass 27, count 2 2006.175.07:40:12.06#ibcon#about to read 3, iclass 27, count 2 2006.175.07:40:12.08#ibcon#read 3, iclass 27, count 2 2006.175.07:40:12.08#ibcon#about to read 4, iclass 27, count 2 2006.175.07:40:12.08#ibcon#read 4, iclass 27, count 2 2006.175.07:40:12.08#ibcon#about to read 5, iclass 27, count 2 2006.175.07:40:12.08#ibcon#read 5, iclass 27, count 2 2006.175.07:40:12.08#ibcon#about to read 6, iclass 27, count 2 2006.175.07:40:12.08#ibcon#read 6, iclass 27, count 2 2006.175.07:40:12.08#ibcon#end of sib2, iclass 27, count 2 2006.175.07:40:12.08#ibcon#*mode == 0, iclass 27, count 2 2006.175.07:40:12.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.07:40:12.08#ibcon#[27=AT05-04\r\n] 2006.175.07:40:12.08#ibcon#*before write, iclass 27, count 2 2006.175.07:40:12.08#ibcon#enter sib2, iclass 27, count 2 2006.175.07:40:12.08#ibcon#flushed, iclass 27, count 2 2006.175.07:40:12.08#ibcon#about to write, iclass 27, count 2 2006.175.07:40:12.08#ibcon#wrote, iclass 27, count 2 2006.175.07:40:12.08#ibcon#about to read 3, iclass 27, count 2 2006.175.07:40:12.11#ibcon#read 3, iclass 27, count 2 2006.175.07:40:12.11#ibcon#about to read 4, iclass 27, count 2 2006.175.07:40:12.11#ibcon#read 4, iclass 27, count 2 2006.175.07:40:12.11#ibcon#about to read 5, iclass 27, count 2 2006.175.07:40:12.11#ibcon#read 5, iclass 27, count 2 2006.175.07:40:12.11#ibcon#about to read 6, iclass 27, count 2 2006.175.07:40:12.11#ibcon#read 6, iclass 27, count 2 2006.175.07:40:12.11#ibcon#end of sib2, iclass 27, count 2 2006.175.07:40:12.11#ibcon#*after write, iclass 27, count 2 2006.175.07:40:12.11#ibcon#*before return 0, iclass 27, count 2 2006.175.07:40:12.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:40:12.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:40:12.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.07:40:12.11#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:12.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:40:12.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:40:12.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:40:12.23#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:40:12.23#ibcon#first serial, iclass 27, count 0 2006.175.07:40:12.23#ibcon#enter sib2, iclass 27, count 0 2006.175.07:40:12.23#ibcon#flushed, iclass 27, count 0 2006.175.07:40:12.23#ibcon#about to write, iclass 27, count 0 2006.175.07:40:12.23#ibcon#wrote, iclass 27, count 0 2006.175.07:40:12.23#ibcon#about to read 3, iclass 27, count 0 2006.175.07:40:12.25#ibcon#read 3, iclass 27, count 0 2006.175.07:40:12.25#ibcon#about to read 4, iclass 27, count 0 2006.175.07:40:12.25#ibcon#read 4, iclass 27, count 0 2006.175.07:40:12.25#ibcon#about to read 5, iclass 27, count 0 2006.175.07:40:12.25#ibcon#read 5, iclass 27, count 0 2006.175.07:40:12.25#ibcon#about to read 6, iclass 27, count 0 2006.175.07:40:12.25#ibcon#read 6, iclass 27, count 0 2006.175.07:40:12.25#ibcon#end of sib2, iclass 27, count 0 2006.175.07:40:12.25#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:40:12.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:40:12.25#ibcon#[27=USB\r\n] 2006.175.07:40:12.25#ibcon#*before write, iclass 27, count 0 2006.175.07:40:12.25#ibcon#enter sib2, iclass 27, count 0 2006.175.07:40:12.25#ibcon#flushed, iclass 27, count 0 2006.175.07:40:12.25#ibcon#about to write, iclass 27, count 0 2006.175.07:40:12.25#ibcon#wrote, iclass 27, count 0 2006.175.07:40:12.25#ibcon#about to read 3, iclass 27, count 0 2006.175.07:40:12.28#ibcon#read 3, iclass 27, count 0 2006.175.07:40:12.28#ibcon#about to read 4, iclass 27, count 0 2006.175.07:40:12.28#ibcon#read 4, iclass 27, count 0 2006.175.07:40:12.28#ibcon#about to read 5, iclass 27, count 0 2006.175.07:40:12.28#ibcon#read 5, iclass 27, count 0 2006.175.07:40:12.28#ibcon#about to read 6, iclass 27, count 0 2006.175.07:40:12.28#ibcon#read 6, iclass 27, count 0 2006.175.07:40:12.28#ibcon#end of sib2, iclass 27, count 0 2006.175.07:40:12.28#ibcon#*after write, iclass 27, count 0 2006.175.07:40:12.28#ibcon#*before return 0, iclass 27, count 0 2006.175.07:40:12.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:40:12.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:40:12.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:40:12.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:40:12.28$vc4f8/vblo=6,752.99 2006.175.07:40:12.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.07:40:12.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.07:40:12.28#ibcon#ireg 17 cls_cnt 0 2006.175.07:40:12.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:12.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:12.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:12.28#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:40:12.28#ibcon#first serial, iclass 29, count 0 2006.175.07:40:12.28#ibcon#enter sib2, iclass 29, count 0 2006.175.07:40:12.28#ibcon#flushed, iclass 29, count 0 2006.175.07:40:12.28#ibcon#about to write, iclass 29, count 0 2006.175.07:40:12.28#ibcon#wrote, iclass 29, count 0 2006.175.07:40:12.28#ibcon#about to read 3, iclass 29, count 0 2006.175.07:40:12.30#ibcon#read 3, iclass 29, count 0 2006.175.07:40:12.30#ibcon#about to read 4, iclass 29, count 0 2006.175.07:40:12.30#ibcon#read 4, iclass 29, count 0 2006.175.07:40:12.30#ibcon#about to read 5, iclass 29, count 0 2006.175.07:40:12.30#ibcon#read 5, iclass 29, count 0 2006.175.07:40:12.30#ibcon#about to read 6, iclass 29, count 0 2006.175.07:40:12.30#ibcon#read 6, iclass 29, count 0 2006.175.07:40:12.30#ibcon#end of sib2, iclass 29, count 0 2006.175.07:40:12.30#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:40:12.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:40:12.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:40:12.30#ibcon#*before write, iclass 29, count 0 2006.175.07:40:12.30#ibcon#enter sib2, iclass 29, count 0 2006.175.07:40:12.30#ibcon#flushed, iclass 29, count 0 2006.175.07:40:12.30#ibcon#about to write, iclass 29, count 0 2006.175.07:40:12.30#ibcon#wrote, iclass 29, count 0 2006.175.07:40:12.30#ibcon#about to read 3, iclass 29, count 0 2006.175.07:40:12.34#ibcon#read 3, iclass 29, count 0 2006.175.07:40:12.34#ibcon#about to read 4, iclass 29, count 0 2006.175.07:40:12.34#ibcon#read 4, iclass 29, count 0 2006.175.07:40:12.34#ibcon#about to read 5, iclass 29, count 0 2006.175.07:40:12.34#ibcon#read 5, iclass 29, count 0 2006.175.07:40:12.34#ibcon#about to read 6, iclass 29, count 0 2006.175.07:40:12.34#ibcon#read 6, iclass 29, count 0 2006.175.07:40:12.34#ibcon#end of sib2, iclass 29, count 0 2006.175.07:40:12.34#ibcon#*after write, iclass 29, count 0 2006.175.07:40:12.34#ibcon#*before return 0, iclass 29, count 0 2006.175.07:40:12.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:12.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:40:12.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:40:12.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:40:12.34$vc4f8/vb=6,4 2006.175.07:40:12.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.07:40:12.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.07:40:12.34#ibcon#ireg 11 cls_cnt 2 2006.175.07:40:12.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:12.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:12.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:12.40#ibcon#enter wrdev, iclass 31, count 2 2006.175.07:40:12.40#ibcon#first serial, iclass 31, count 2 2006.175.07:40:12.40#ibcon#enter sib2, iclass 31, count 2 2006.175.07:40:12.40#ibcon#flushed, iclass 31, count 2 2006.175.07:40:12.40#ibcon#about to write, iclass 31, count 2 2006.175.07:40:12.40#ibcon#wrote, iclass 31, count 2 2006.175.07:40:12.40#ibcon#about to read 3, iclass 31, count 2 2006.175.07:40:12.42#ibcon#read 3, iclass 31, count 2 2006.175.07:40:12.42#ibcon#about to read 4, iclass 31, count 2 2006.175.07:40:12.42#ibcon#read 4, iclass 31, count 2 2006.175.07:40:12.42#ibcon#about to read 5, iclass 31, count 2 2006.175.07:40:12.42#ibcon#read 5, iclass 31, count 2 2006.175.07:40:12.42#ibcon#about to read 6, iclass 31, count 2 2006.175.07:40:12.42#ibcon#read 6, iclass 31, count 2 2006.175.07:40:12.42#ibcon#end of sib2, iclass 31, count 2 2006.175.07:40:12.42#ibcon#*mode == 0, iclass 31, count 2 2006.175.07:40:12.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.07:40:12.42#ibcon#[27=AT06-04\r\n] 2006.175.07:40:12.42#ibcon#*before write, iclass 31, count 2 2006.175.07:40:12.42#ibcon#enter sib2, iclass 31, count 2 2006.175.07:40:12.42#ibcon#flushed, iclass 31, count 2 2006.175.07:40:12.42#ibcon#about to write, iclass 31, count 2 2006.175.07:40:12.42#ibcon#wrote, iclass 31, count 2 2006.175.07:40:12.42#ibcon#about to read 3, iclass 31, count 2 2006.175.07:40:12.45#ibcon#read 3, iclass 31, count 2 2006.175.07:40:12.45#ibcon#about to read 4, iclass 31, count 2 2006.175.07:40:12.45#ibcon#read 4, iclass 31, count 2 2006.175.07:40:12.45#ibcon#about to read 5, iclass 31, count 2 2006.175.07:40:12.45#ibcon#read 5, iclass 31, count 2 2006.175.07:40:12.45#ibcon#about to read 6, iclass 31, count 2 2006.175.07:40:12.45#ibcon#read 6, iclass 31, count 2 2006.175.07:40:12.45#ibcon#end of sib2, iclass 31, count 2 2006.175.07:40:12.45#ibcon#*after write, iclass 31, count 2 2006.175.07:40:12.45#ibcon#*before return 0, iclass 31, count 2 2006.175.07:40:12.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:12.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:40:12.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.07:40:12.45#ibcon#ireg 7 cls_cnt 0 2006.175.07:40:12.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:12.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:12.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:12.57#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:40:12.57#ibcon#first serial, iclass 31, count 0 2006.175.07:40:12.57#ibcon#enter sib2, iclass 31, count 0 2006.175.07:40:12.57#ibcon#flushed, iclass 31, count 0 2006.175.07:40:12.57#ibcon#about to write, iclass 31, count 0 2006.175.07:40:12.57#ibcon#wrote, iclass 31, count 0 2006.175.07:40:12.57#ibcon#about to read 3, iclass 31, count 0 2006.175.07:40:12.59#ibcon#read 3, iclass 31, count 0 2006.175.07:40:12.59#ibcon#about to read 4, iclass 31, count 0 2006.175.07:40:12.59#ibcon#read 4, iclass 31, count 0 2006.175.07:40:12.59#ibcon#about to read 5, iclass 31, count 0 2006.175.07:40:12.59#ibcon#read 5, iclass 31, count 0 2006.175.07:40:12.59#ibcon#about to read 6, iclass 31, count 0 2006.175.07:40:12.59#ibcon#read 6, iclass 31, count 0 2006.175.07:40:12.59#ibcon#end of sib2, iclass 31, count 0 2006.175.07:40:12.59#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:40:12.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:40:12.59#ibcon#[27=USB\r\n] 2006.175.07:40:12.59#ibcon#*before write, iclass 31, count 0 2006.175.07:40:12.59#ibcon#enter sib2, iclass 31, count 0 2006.175.07:40:12.59#ibcon#flushed, iclass 31, count 0 2006.175.07:40:12.59#ibcon#about to write, iclass 31, count 0 2006.175.07:40:12.59#ibcon#wrote, iclass 31, count 0 2006.175.07:40:12.59#ibcon#about to read 3, iclass 31, count 0 2006.175.07:40:12.62#ibcon#read 3, iclass 31, count 0 2006.175.07:40:12.62#ibcon#about to read 4, iclass 31, count 0 2006.175.07:40:12.62#ibcon#read 4, iclass 31, count 0 2006.175.07:40:12.62#ibcon#about to read 5, iclass 31, count 0 2006.175.07:40:12.62#ibcon#read 5, iclass 31, count 0 2006.175.07:40:12.62#ibcon#about to read 6, iclass 31, count 0 2006.175.07:40:12.62#ibcon#read 6, iclass 31, count 0 2006.175.07:40:12.62#ibcon#end of sib2, iclass 31, count 0 2006.175.07:40:12.62#ibcon#*after write, iclass 31, count 0 2006.175.07:40:12.62#ibcon#*before return 0, iclass 31, count 0 2006.175.07:40:12.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:12.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:40:12.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:40:12.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:40:12.62$vc4f8/vabw=wide 2006.175.07:40:12.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.07:40:12.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.07:40:12.62#ibcon#ireg 8 cls_cnt 0 2006.175.07:40:12.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:12.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:12.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:12.62#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:40:12.62#ibcon#first serial, iclass 33, count 0 2006.175.07:40:12.62#ibcon#enter sib2, iclass 33, count 0 2006.175.07:40:12.62#ibcon#flushed, iclass 33, count 0 2006.175.07:40:12.62#ibcon#about to write, iclass 33, count 0 2006.175.07:40:12.62#ibcon#wrote, iclass 33, count 0 2006.175.07:40:12.62#ibcon#about to read 3, iclass 33, count 0 2006.175.07:40:12.64#ibcon#read 3, iclass 33, count 0 2006.175.07:40:12.64#ibcon#about to read 4, iclass 33, count 0 2006.175.07:40:12.64#ibcon#read 4, iclass 33, count 0 2006.175.07:40:12.64#ibcon#about to read 5, iclass 33, count 0 2006.175.07:40:12.64#ibcon#read 5, iclass 33, count 0 2006.175.07:40:12.64#ibcon#about to read 6, iclass 33, count 0 2006.175.07:40:12.64#ibcon#read 6, iclass 33, count 0 2006.175.07:40:12.64#ibcon#end of sib2, iclass 33, count 0 2006.175.07:40:12.64#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:40:12.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:40:12.64#ibcon#[25=BW32\r\n] 2006.175.07:40:12.64#ibcon#*before write, iclass 33, count 0 2006.175.07:40:12.64#ibcon#enter sib2, iclass 33, count 0 2006.175.07:40:12.64#ibcon#flushed, iclass 33, count 0 2006.175.07:40:12.64#ibcon#about to write, iclass 33, count 0 2006.175.07:40:12.64#ibcon#wrote, iclass 33, count 0 2006.175.07:40:12.64#ibcon#about to read 3, iclass 33, count 0 2006.175.07:40:12.67#ibcon#read 3, iclass 33, count 0 2006.175.07:40:12.67#ibcon#about to read 4, iclass 33, count 0 2006.175.07:40:12.67#ibcon#read 4, iclass 33, count 0 2006.175.07:40:12.67#ibcon#about to read 5, iclass 33, count 0 2006.175.07:40:12.67#ibcon#read 5, iclass 33, count 0 2006.175.07:40:12.67#ibcon#about to read 6, iclass 33, count 0 2006.175.07:40:12.67#ibcon#read 6, iclass 33, count 0 2006.175.07:40:12.67#ibcon#end of sib2, iclass 33, count 0 2006.175.07:40:12.67#ibcon#*after write, iclass 33, count 0 2006.175.07:40:12.67#ibcon#*before return 0, iclass 33, count 0 2006.175.07:40:12.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:12.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:40:12.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:40:12.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:40:12.67$vc4f8/vbbw=wide 2006.175.07:40:12.67#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.07:40:12.67#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.07:40:12.67#ibcon#ireg 8 cls_cnt 0 2006.175.07:40:12.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:40:12.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:40:12.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:40:12.74#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:40:12.74#ibcon#first serial, iclass 35, count 0 2006.175.07:40:12.74#ibcon#enter sib2, iclass 35, count 0 2006.175.07:40:12.74#ibcon#flushed, iclass 35, count 0 2006.175.07:40:12.74#ibcon#about to write, iclass 35, count 0 2006.175.07:40:12.74#ibcon#wrote, iclass 35, count 0 2006.175.07:40:12.74#ibcon#about to read 3, iclass 35, count 0 2006.175.07:40:12.76#ibcon#read 3, iclass 35, count 0 2006.175.07:40:12.76#ibcon#about to read 4, iclass 35, count 0 2006.175.07:40:12.76#ibcon#read 4, iclass 35, count 0 2006.175.07:40:12.76#ibcon#about to read 5, iclass 35, count 0 2006.175.07:40:12.76#ibcon#read 5, iclass 35, count 0 2006.175.07:40:12.76#ibcon#about to read 6, iclass 35, count 0 2006.175.07:40:12.76#ibcon#read 6, iclass 35, count 0 2006.175.07:40:12.76#ibcon#end of sib2, iclass 35, count 0 2006.175.07:40:12.76#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:40:12.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:40:12.76#ibcon#[27=BW32\r\n] 2006.175.07:40:12.76#ibcon#*before write, iclass 35, count 0 2006.175.07:40:12.76#ibcon#enter sib2, iclass 35, count 0 2006.175.07:40:12.76#ibcon#flushed, iclass 35, count 0 2006.175.07:40:12.76#ibcon#about to write, iclass 35, count 0 2006.175.07:40:12.76#ibcon#wrote, iclass 35, count 0 2006.175.07:40:12.76#ibcon#about to read 3, iclass 35, count 0 2006.175.07:40:12.79#ibcon#read 3, iclass 35, count 0 2006.175.07:40:12.79#ibcon#about to read 4, iclass 35, count 0 2006.175.07:40:12.79#ibcon#read 4, iclass 35, count 0 2006.175.07:40:12.79#ibcon#about to read 5, iclass 35, count 0 2006.175.07:40:12.79#ibcon#read 5, iclass 35, count 0 2006.175.07:40:12.79#ibcon#about to read 6, iclass 35, count 0 2006.175.07:40:12.79#ibcon#read 6, iclass 35, count 0 2006.175.07:40:12.79#ibcon#end of sib2, iclass 35, count 0 2006.175.07:40:12.79#ibcon#*after write, iclass 35, count 0 2006.175.07:40:12.79#ibcon#*before return 0, iclass 35, count 0 2006.175.07:40:12.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:40:12.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:40:12.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:40:12.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:40:12.79$4f8m12a/ifd4f 2006.175.07:40:12.79$ifd4f/lo= 2006.175.07:40:12.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:40:12.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:40:12.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:40:12.79$ifd4f/patch= 2006.175.07:40:12.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:40:12.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:40:12.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:40:12.79$4f8m12a/"form=m,16.000,1:2 2006.175.07:40:12.79$4f8m12a/"tpicd 2006.175.07:40:12.79$4f8m12a/echo=off 2006.175.07:40:12.79$4f8m12a/xlog=off 2006.175.07:40:12.79:!2006.175.07:40:40 2006.175.07:40:24.14#trakl#Source acquired 2006.175.07:40:25.14#flagr#flagr/antenna,acquired 2006.175.07:40:40.00:preob 2006.175.07:40:41.14/onsource/TRACKING 2006.175.07:40:41.14:!2006.175.07:40:50 2006.175.07:40:50.00:data_valid=on 2006.175.07:40:50.00:midob 2006.175.07:40:50.14/onsource/TRACKING 2006.175.07:40:50.14/wx/25.94,1007.4,70 2006.175.07:40:50.29/cable/+6.4785E-03 2006.175.07:40:51.38/va/01,08,usb,yes,28,30 2006.175.07:40:51.38/va/02,07,usb,yes,28,30 2006.175.07:40:51.38/va/03,06,usb,yes,30,30 2006.175.07:40:51.38/va/04,07,usb,yes,29,31 2006.175.07:40:51.38/va/05,07,usb,yes,29,31 2006.175.07:40:51.38/va/06,06,usb,yes,28,28 2006.175.07:40:51.38/va/07,06,usb,yes,29,29 2006.175.07:40:51.38/va/08,06,usb,yes,31,30 2006.175.07:40:51.61/valo/01,532.99,yes,locked 2006.175.07:40:51.61/valo/02,572.99,yes,locked 2006.175.07:40:51.61/valo/03,672.99,yes,locked 2006.175.07:40:51.61/valo/04,832.99,yes,locked 2006.175.07:40:51.61/valo/05,652.99,yes,locked 2006.175.07:40:51.61/valo/06,772.99,yes,locked 2006.175.07:40:51.61/valo/07,832.99,yes,locked 2006.175.07:40:51.61/valo/08,852.99,yes,locked 2006.175.07:40:52.70/vb/01,04,usb,yes,29,27 2006.175.07:40:52.70/vb/02,04,usb,yes,30,32 2006.175.07:40:52.70/vb/03,04,usb,yes,27,30 2006.175.07:40:52.70/vb/04,04,usb,yes,28,28 2006.175.07:40:52.70/vb/05,04,usb,yes,26,30 2006.175.07:40:52.70/vb/06,04,usb,yes,27,30 2006.175.07:40:52.70/vb/07,04,usb,yes,29,29 2006.175.07:40:52.70/vb/08,04,usb,yes,27,30 2006.175.07:40:52.93/vblo/01,632.99,yes,locked 2006.175.07:40:52.93/vblo/02,640.99,yes,locked 2006.175.07:40:52.93/vblo/03,656.99,yes,locked 2006.175.07:40:52.93/vblo/04,712.99,yes,locked 2006.175.07:40:52.93/vblo/05,744.99,yes,locked 2006.175.07:40:52.93/vblo/06,752.99,yes,locked 2006.175.07:40:52.93/vblo/07,734.99,yes,locked 2006.175.07:40:52.93/vblo/08,744.99,yes,locked 2006.175.07:40:53.08/vabw/8 2006.175.07:40:53.23/vbbw/8 2006.175.07:40:53.32/xfe/off,on,14.7 2006.175.07:40:53.69/ifatt/23,28,28,28 2006.175.07:40:54.07/fmout-gps/S +3.76E-07 2006.175.07:40:54.15:!2006.175.07:41:50 2006.175.07:41:50.00:data_valid=off 2006.175.07:41:50.00:postob 2006.175.07:41:50.05/cable/+6.4770E-03 2006.175.07:41:50.05/wx/25.93,1007.4,69 2006.175.07:41:51.07/fmout-gps/S +3.77E-07 2006.175.07:41:51.07:scan_name=175-0743,k06175,130 2006.175.07:41:51.08:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.175.07:41:51.13#flagr#flagr/antenna,new-source 2006.175.07:41:52.13:checkk5 2006.175.07:41:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:41:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:41:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:41:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:41:54.01/chk_obsdata//k5ts1/T1750740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:41:54.38/chk_obsdata//k5ts2/T1750740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:41:54.75/chk_obsdata//k5ts3/T1750740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:41:55.12/chk_obsdata//k5ts4/T1750740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:41:55.82/k5log//k5ts1_log_newline 2006.175.07:41:56.52/k5log//k5ts2_log_newline 2006.175.07:41:57.21/k5log//k5ts3_log_newline 2006.175.07:41:57.93/k5log//k5ts4_log_newline 2006.175.07:41:57.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:41:57.95:4f8m12a=1 2006.175.07:41:57.95$4f8m12a/echo=on 2006.175.07:41:57.95$4f8m12a/pcalon 2006.175.07:41:57.95$pcalon/"no phase cal control is implemented here 2006.175.07:41:57.95$4f8m12a/"tpicd=stop 2006.175.07:41:57.95$4f8m12a/vc4f8 2006.175.07:41:57.95$vc4f8/valo=1,532.99 2006.175.07:41:57.95#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:41:57.95#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:41:57.95#ibcon#ireg 17 cls_cnt 0 2006.175.07:41:57.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:41:57.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:41:57.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:41:57.95#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:41:57.95#ibcon#first serial, iclass 4, count 0 2006.175.07:41:57.95#ibcon#enter sib2, iclass 4, count 0 2006.175.07:41:57.95#ibcon#flushed, iclass 4, count 0 2006.175.07:41:57.95#ibcon#about to write, iclass 4, count 0 2006.175.07:41:57.95#ibcon#wrote, iclass 4, count 0 2006.175.07:41:57.95#ibcon#about to read 3, iclass 4, count 0 2006.175.07:41:57.97#ibcon#read 3, iclass 4, count 0 2006.175.07:41:57.97#ibcon#about to read 4, iclass 4, count 0 2006.175.07:41:57.97#ibcon#read 4, iclass 4, count 0 2006.175.07:41:57.97#ibcon#about to read 5, iclass 4, count 0 2006.175.07:41:57.97#ibcon#read 5, iclass 4, count 0 2006.175.07:41:57.97#ibcon#about to read 6, iclass 4, count 0 2006.175.07:41:57.97#ibcon#read 6, iclass 4, count 0 2006.175.07:41:57.97#ibcon#end of sib2, iclass 4, count 0 2006.175.07:41:57.97#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:41:57.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:41:57.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:41:57.97#ibcon#*before write, iclass 4, count 0 2006.175.07:41:57.97#ibcon#enter sib2, iclass 4, count 0 2006.175.07:41:57.97#ibcon#flushed, iclass 4, count 0 2006.175.07:41:57.97#ibcon#about to write, iclass 4, count 0 2006.175.07:41:57.97#ibcon#wrote, iclass 4, count 0 2006.175.07:41:57.97#ibcon#about to read 3, iclass 4, count 0 2006.175.07:41:58.02#ibcon#read 3, iclass 4, count 0 2006.175.07:41:58.02#ibcon#about to read 4, iclass 4, count 0 2006.175.07:41:58.02#ibcon#read 4, iclass 4, count 0 2006.175.07:41:58.02#ibcon#about to read 5, iclass 4, count 0 2006.175.07:41:58.02#ibcon#read 5, iclass 4, count 0 2006.175.07:41:58.02#ibcon#about to read 6, iclass 4, count 0 2006.175.07:41:58.02#ibcon#read 6, iclass 4, count 0 2006.175.07:41:58.02#ibcon#end of sib2, iclass 4, count 0 2006.175.07:41:58.02#ibcon#*after write, iclass 4, count 0 2006.175.07:41:58.02#ibcon#*before return 0, iclass 4, count 0 2006.175.07:41:58.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:41:58.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:41:58.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:41:58.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:41:58.02$vc4f8/va=1,8 2006.175.07:41:58.02#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.07:41:58.02#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.07:41:58.02#ibcon#ireg 11 cls_cnt 2 2006.175.07:41:58.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:41:58.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:41:58.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:41:58.02#ibcon#enter wrdev, iclass 6, count 2 2006.175.07:41:58.02#ibcon#first serial, iclass 6, count 2 2006.175.07:41:58.02#ibcon#enter sib2, iclass 6, count 2 2006.175.07:41:58.02#ibcon#flushed, iclass 6, count 2 2006.175.07:41:58.02#ibcon#about to write, iclass 6, count 2 2006.175.07:41:58.02#ibcon#wrote, iclass 6, count 2 2006.175.07:41:58.02#ibcon#about to read 3, iclass 6, count 2 2006.175.07:41:58.04#ibcon#read 3, iclass 6, count 2 2006.175.07:41:58.04#ibcon#about to read 4, iclass 6, count 2 2006.175.07:41:58.04#ibcon#read 4, iclass 6, count 2 2006.175.07:41:58.04#ibcon#about to read 5, iclass 6, count 2 2006.175.07:41:58.04#ibcon#read 5, iclass 6, count 2 2006.175.07:41:58.04#ibcon#about to read 6, iclass 6, count 2 2006.175.07:41:58.04#ibcon#read 6, iclass 6, count 2 2006.175.07:41:58.04#ibcon#end of sib2, iclass 6, count 2 2006.175.07:41:58.04#ibcon#*mode == 0, iclass 6, count 2 2006.175.07:41:58.04#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.07:41:58.04#ibcon#[25=AT01-08\r\n] 2006.175.07:41:58.04#ibcon#*before write, iclass 6, count 2 2006.175.07:41:58.04#ibcon#enter sib2, iclass 6, count 2 2006.175.07:41:58.04#ibcon#flushed, iclass 6, count 2 2006.175.07:41:58.04#ibcon#about to write, iclass 6, count 2 2006.175.07:41:58.04#ibcon#wrote, iclass 6, count 2 2006.175.07:41:58.04#ibcon#about to read 3, iclass 6, count 2 2006.175.07:41:58.07#ibcon#read 3, iclass 6, count 2 2006.175.07:41:58.07#ibcon#about to read 4, iclass 6, count 2 2006.175.07:41:58.07#ibcon#read 4, iclass 6, count 2 2006.175.07:41:58.07#ibcon#about to read 5, iclass 6, count 2 2006.175.07:41:58.07#ibcon#read 5, iclass 6, count 2 2006.175.07:41:58.07#ibcon#about to read 6, iclass 6, count 2 2006.175.07:41:58.07#ibcon#read 6, iclass 6, count 2 2006.175.07:41:58.07#ibcon#end of sib2, iclass 6, count 2 2006.175.07:41:58.07#ibcon#*after write, iclass 6, count 2 2006.175.07:41:58.07#ibcon#*before return 0, iclass 6, count 2 2006.175.07:41:58.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:41:58.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:41:58.07#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.07:41:58.07#ibcon#ireg 7 cls_cnt 0 2006.175.07:41:58.07#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:41:58.19#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:41:58.19#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:41:58.19#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:41:58.19#ibcon#first serial, iclass 6, count 0 2006.175.07:41:58.19#ibcon#enter sib2, iclass 6, count 0 2006.175.07:41:58.19#ibcon#flushed, iclass 6, count 0 2006.175.07:41:58.19#ibcon#about to write, iclass 6, count 0 2006.175.07:41:58.19#ibcon#wrote, iclass 6, count 0 2006.175.07:41:58.19#ibcon#about to read 3, iclass 6, count 0 2006.175.07:41:58.21#ibcon#read 3, iclass 6, count 0 2006.175.07:41:58.21#ibcon#about to read 4, iclass 6, count 0 2006.175.07:41:58.21#ibcon#read 4, iclass 6, count 0 2006.175.07:41:58.21#ibcon#about to read 5, iclass 6, count 0 2006.175.07:41:58.21#ibcon#read 5, iclass 6, count 0 2006.175.07:41:58.21#ibcon#about to read 6, iclass 6, count 0 2006.175.07:41:58.21#ibcon#read 6, iclass 6, count 0 2006.175.07:41:58.21#ibcon#end of sib2, iclass 6, count 0 2006.175.07:41:58.21#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:41:58.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:41:58.21#ibcon#[25=USB\r\n] 2006.175.07:41:58.21#ibcon#*before write, iclass 6, count 0 2006.175.07:41:58.21#ibcon#enter sib2, iclass 6, count 0 2006.175.07:41:58.21#ibcon#flushed, iclass 6, count 0 2006.175.07:41:58.21#ibcon#about to write, iclass 6, count 0 2006.175.07:41:58.21#ibcon#wrote, iclass 6, count 0 2006.175.07:41:58.21#ibcon#about to read 3, iclass 6, count 0 2006.175.07:41:58.24#ibcon#read 3, iclass 6, count 0 2006.175.07:41:58.24#ibcon#about to read 4, iclass 6, count 0 2006.175.07:41:58.24#ibcon#read 4, iclass 6, count 0 2006.175.07:41:58.24#ibcon#about to read 5, iclass 6, count 0 2006.175.07:41:58.24#ibcon#read 5, iclass 6, count 0 2006.175.07:41:58.24#ibcon#about to read 6, iclass 6, count 0 2006.175.07:41:58.24#ibcon#read 6, iclass 6, count 0 2006.175.07:41:58.24#ibcon#end of sib2, iclass 6, count 0 2006.175.07:41:58.24#ibcon#*after write, iclass 6, count 0 2006.175.07:41:58.24#ibcon#*before return 0, iclass 6, count 0 2006.175.07:41:58.24#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:41:58.24#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:41:58.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:41:58.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:41:58.24$vc4f8/valo=2,572.99 2006.175.07:41:58.24#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.07:41:58.24#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.07:41:58.24#ibcon#ireg 17 cls_cnt 0 2006.175.07:41:58.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:41:58.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:41:58.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:41:58.24#ibcon#enter wrdev, iclass 10, count 0 2006.175.07:41:58.24#ibcon#first serial, iclass 10, count 0 2006.175.07:41:58.24#ibcon#enter sib2, iclass 10, count 0 2006.175.07:41:58.24#ibcon#flushed, iclass 10, count 0 2006.175.07:41:58.24#ibcon#about to write, iclass 10, count 0 2006.175.07:41:58.24#ibcon#wrote, iclass 10, count 0 2006.175.07:41:58.24#ibcon#about to read 3, iclass 10, count 0 2006.175.07:41:58.26#ibcon#read 3, iclass 10, count 0 2006.175.07:41:58.26#ibcon#about to read 4, iclass 10, count 0 2006.175.07:41:58.26#ibcon#read 4, iclass 10, count 0 2006.175.07:41:58.26#ibcon#about to read 5, iclass 10, count 0 2006.175.07:41:58.26#ibcon#read 5, iclass 10, count 0 2006.175.07:41:58.26#ibcon#about to read 6, iclass 10, count 0 2006.175.07:41:58.26#ibcon#read 6, iclass 10, count 0 2006.175.07:41:58.26#ibcon#end of sib2, iclass 10, count 0 2006.175.07:41:58.26#ibcon#*mode == 0, iclass 10, count 0 2006.175.07:41:58.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.07:41:58.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:41:58.26#ibcon#*before write, iclass 10, count 0 2006.175.07:41:58.26#ibcon#enter sib2, iclass 10, count 0 2006.175.07:41:58.26#ibcon#flushed, iclass 10, count 0 2006.175.07:41:58.26#ibcon#about to write, iclass 10, count 0 2006.175.07:41:58.26#ibcon#wrote, iclass 10, count 0 2006.175.07:41:58.26#ibcon#about to read 3, iclass 10, count 0 2006.175.07:41:58.30#ibcon#read 3, iclass 10, count 0 2006.175.07:41:58.30#ibcon#about to read 4, iclass 10, count 0 2006.175.07:41:58.30#ibcon#read 4, iclass 10, count 0 2006.175.07:41:58.30#ibcon#about to read 5, iclass 10, count 0 2006.175.07:41:58.30#ibcon#read 5, iclass 10, count 0 2006.175.07:41:58.30#ibcon#about to read 6, iclass 10, count 0 2006.175.07:41:58.30#ibcon#read 6, iclass 10, count 0 2006.175.07:41:58.30#ibcon#end of sib2, iclass 10, count 0 2006.175.07:41:58.30#ibcon#*after write, iclass 10, count 0 2006.175.07:41:58.30#ibcon#*before return 0, iclass 10, count 0 2006.175.07:41:58.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:41:58.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:41:58.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.07:41:58.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.07:41:58.30$vc4f8/va=2,7 2006.175.07:41:58.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.07:41:58.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.07:41:58.30#ibcon#ireg 11 cls_cnt 2 2006.175.07:41:58.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:41:58.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:41:58.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:41:58.36#ibcon#enter wrdev, iclass 12, count 2 2006.175.07:41:58.36#ibcon#first serial, iclass 12, count 2 2006.175.07:41:58.36#ibcon#enter sib2, iclass 12, count 2 2006.175.07:41:58.36#ibcon#flushed, iclass 12, count 2 2006.175.07:41:58.36#ibcon#about to write, iclass 12, count 2 2006.175.07:41:58.36#ibcon#wrote, iclass 12, count 2 2006.175.07:41:58.36#ibcon#about to read 3, iclass 12, count 2 2006.175.07:41:58.38#ibcon#read 3, iclass 12, count 2 2006.175.07:41:58.38#ibcon#about to read 4, iclass 12, count 2 2006.175.07:41:58.38#ibcon#read 4, iclass 12, count 2 2006.175.07:41:58.38#ibcon#about to read 5, iclass 12, count 2 2006.175.07:41:58.38#ibcon#read 5, iclass 12, count 2 2006.175.07:41:58.38#ibcon#about to read 6, iclass 12, count 2 2006.175.07:41:58.38#ibcon#read 6, iclass 12, count 2 2006.175.07:41:58.38#ibcon#end of sib2, iclass 12, count 2 2006.175.07:41:58.38#ibcon#*mode == 0, iclass 12, count 2 2006.175.07:41:58.38#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.07:41:58.38#ibcon#[25=AT02-07\r\n] 2006.175.07:41:58.38#ibcon#*before write, iclass 12, count 2 2006.175.07:41:58.38#ibcon#enter sib2, iclass 12, count 2 2006.175.07:41:58.38#ibcon#flushed, iclass 12, count 2 2006.175.07:41:58.38#ibcon#about to write, iclass 12, count 2 2006.175.07:41:58.38#ibcon#wrote, iclass 12, count 2 2006.175.07:41:58.38#ibcon#about to read 3, iclass 12, count 2 2006.175.07:41:58.41#ibcon#read 3, iclass 12, count 2 2006.175.07:41:58.41#ibcon#about to read 4, iclass 12, count 2 2006.175.07:41:58.41#ibcon#read 4, iclass 12, count 2 2006.175.07:41:58.41#ibcon#about to read 5, iclass 12, count 2 2006.175.07:41:58.41#ibcon#read 5, iclass 12, count 2 2006.175.07:41:58.41#ibcon#about to read 6, iclass 12, count 2 2006.175.07:41:58.41#ibcon#read 6, iclass 12, count 2 2006.175.07:41:58.41#ibcon#end of sib2, iclass 12, count 2 2006.175.07:41:58.41#ibcon#*after write, iclass 12, count 2 2006.175.07:41:58.41#ibcon#*before return 0, iclass 12, count 2 2006.175.07:41:58.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:41:58.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:41:58.41#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.07:41:58.41#ibcon#ireg 7 cls_cnt 0 2006.175.07:41:58.41#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:41:58.53#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:41:58.53#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:41:58.53#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:41:58.53#ibcon#first serial, iclass 12, count 0 2006.175.07:41:58.53#ibcon#enter sib2, iclass 12, count 0 2006.175.07:41:58.53#ibcon#flushed, iclass 12, count 0 2006.175.07:41:58.53#ibcon#about to write, iclass 12, count 0 2006.175.07:41:58.53#ibcon#wrote, iclass 12, count 0 2006.175.07:41:58.53#ibcon#about to read 3, iclass 12, count 0 2006.175.07:41:58.55#ibcon#read 3, iclass 12, count 0 2006.175.07:41:58.55#ibcon#about to read 4, iclass 12, count 0 2006.175.07:41:58.55#ibcon#read 4, iclass 12, count 0 2006.175.07:41:58.55#ibcon#about to read 5, iclass 12, count 0 2006.175.07:41:58.55#ibcon#read 5, iclass 12, count 0 2006.175.07:41:58.55#ibcon#about to read 6, iclass 12, count 0 2006.175.07:41:58.55#ibcon#read 6, iclass 12, count 0 2006.175.07:41:58.55#ibcon#end of sib2, iclass 12, count 0 2006.175.07:41:58.55#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:41:58.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:41:58.55#ibcon#[25=USB\r\n] 2006.175.07:41:58.55#ibcon#*before write, iclass 12, count 0 2006.175.07:41:58.55#ibcon#enter sib2, iclass 12, count 0 2006.175.07:41:58.55#ibcon#flushed, iclass 12, count 0 2006.175.07:41:58.55#ibcon#about to write, iclass 12, count 0 2006.175.07:41:58.55#ibcon#wrote, iclass 12, count 0 2006.175.07:41:58.55#ibcon#about to read 3, iclass 12, count 0 2006.175.07:41:58.58#ibcon#read 3, iclass 12, count 0 2006.175.07:41:58.58#ibcon#about to read 4, iclass 12, count 0 2006.175.07:41:58.58#ibcon#read 4, iclass 12, count 0 2006.175.07:41:58.58#ibcon#about to read 5, iclass 12, count 0 2006.175.07:41:58.58#ibcon#read 5, iclass 12, count 0 2006.175.07:41:58.58#ibcon#about to read 6, iclass 12, count 0 2006.175.07:41:58.58#ibcon#read 6, iclass 12, count 0 2006.175.07:41:58.58#ibcon#end of sib2, iclass 12, count 0 2006.175.07:41:58.58#ibcon#*after write, iclass 12, count 0 2006.175.07:41:58.58#ibcon#*before return 0, iclass 12, count 0 2006.175.07:41:58.58#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:41:58.58#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:41:58.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:41:58.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:41:58.58$vc4f8/valo=3,672.99 2006.175.07:41:58.58#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.07:41:58.58#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.07:41:58.58#ibcon#ireg 17 cls_cnt 0 2006.175.07:41:58.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:41:58.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:41:58.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:41:58.58#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:41:58.58#ibcon#first serial, iclass 14, count 0 2006.175.07:41:58.58#ibcon#enter sib2, iclass 14, count 0 2006.175.07:41:58.58#ibcon#flushed, iclass 14, count 0 2006.175.07:41:58.58#ibcon#about to write, iclass 14, count 0 2006.175.07:41:58.58#ibcon#wrote, iclass 14, count 0 2006.175.07:41:58.58#ibcon#about to read 3, iclass 14, count 0 2006.175.07:41:58.60#ibcon#read 3, iclass 14, count 0 2006.175.07:41:58.60#ibcon#about to read 4, iclass 14, count 0 2006.175.07:41:58.60#ibcon#read 4, iclass 14, count 0 2006.175.07:41:58.60#ibcon#about to read 5, iclass 14, count 0 2006.175.07:41:58.60#ibcon#read 5, iclass 14, count 0 2006.175.07:41:58.60#ibcon#about to read 6, iclass 14, count 0 2006.175.07:41:58.60#ibcon#read 6, iclass 14, count 0 2006.175.07:41:58.60#ibcon#end of sib2, iclass 14, count 0 2006.175.07:41:58.60#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:41:58.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:41:58.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:41:58.60#ibcon#*before write, iclass 14, count 0 2006.175.07:41:58.60#ibcon#enter sib2, iclass 14, count 0 2006.175.07:41:58.60#ibcon#flushed, iclass 14, count 0 2006.175.07:41:58.60#ibcon#about to write, iclass 14, count 0 2006.175.07:41:58.60#ibcon#wrote, iclass 14, count 0 2006.175.07:41:58.60#ibcon#about to read 3, iclass 14, count 0 2006.175.07:41:58.64#ibcon#read 3, iclass 14, count 0 2006.175.07:41:58.64#ibcon#about to read 4, iclass 14, count 0 2006.175.07:41:58.64#ibcon#read 4, iclass 14, count 0 2006.175.07:41:58.64#ibcon#about to read 5, iclass 14, count 0 2006.175.07:41:58.64#ibcon#read 5, iclass 14, count 0 2006.175.07:41:58.64#ibcon#about to read 6, iclass 14, count 0 2006.175.07:41:58.64#ibcon#read 6, iclass 14, count 0 2006.175.07:41:58.64#ibcon#end of sib2, iclass 14, count 0 2006.175.07:41:58.64#ibcon#*after write, iclass 14, count 0 2006.175.07:41:58.64#ibcon#*before return 0, iclass 14, count 0 2006.175.07:41:58.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:41:58.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:41:58.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:41:58.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:41:58.64$vc4f8/va=3,6 2006.175.07:41:58.64#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.07:41:58.64#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.07:41:58.64#ibcon#ireg 11 cls_cnt 2 2006.175.07:41:58.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:41:58.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:41:58.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:41:58.70#ibcon#enter wrdev, iclass 16, count 2 2006.175.07:41:58.70#ibcon#first serial, iclass 16, count 2 2006.175.07:41:58.70#ibcon#enter sib2, iclass 16, count 2 2006.175.07:41:58.70#ibcon#flushed, iclass 16, count 2 2006.175.07:41:58.70#ibcon#about to write, iclass 16, count 2 2006.175.07:41:58.70#ibcon#wrote, iclass 16, count 2 2006.175.07:41:58.70#ibcon#about to read 3, iclass 16, count 2 2006.175.07:41:58.72#ibcon#read 3, iclass 16, count 2 2006.175.07:41:58.72#ibcon#about to read 4, iclass 16, count 2 2006.175.07:41:58.72#ibcon#read 4, iclass 16, count 2 2006.175.07:41:58.72#ibcon#about to read 5, iclass 16, count 2 2006.175.07:41:58.72#ibcon#read 5, iclass 16, count 2 2006.175.07:41:58.72#ibcon#about to read 6, iclass 16, count 2 2006.175.07:41:58.72#ibcon#read 6, iclass 16, count 2 2006.175.07:41:58.72#ibcon#end of sib2, iclass 16, count 2 2006.175.07:41:58.72#ibcon#*mode == 0, iclass 16, count 2 2006.175.07:41:58.72#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.07:41:58.72#ibcon#[25=AT03-06\r\n] 2006.175.07:41:58.72#ibcon#*before write, iclass 16, count 2 2006.175.07:41:58.72#ibcon#enter sib2, iclass 16, count 2 2006.175.07:41:58.72#ibcon#flushed, iclass 16, count 2 2006.175.07:41:58.72#ibcon#about to write, iclass 16, count 2 2006.175.07:41:58.72#ibcon#wrote, iclass 16, count 2 2006.175.07:41:58.72#ibcon#about to read 3, iclass 16, count 2 2006.175.07:41:58.75#ibcon#read 3, iclass 16, count 2 2006.175.07:41:58.75#ibcon#about to read 4, iclass 16, count 2 2006.175.07:41:58.75#ibcon#read 4, iclass 16, count 2 2006.175.07:41:58.75#ibcon#about to read 5, iclass 16, count 2 2006.175.07:41:58.75#ibcon#read 5, iclass 16, count 2 2006.175.07:41:58.75#ibcon#about to read 6, iclass 16, count 2 2006.175.07:41:58.75#ibcon#read 6, iclass 16, count 2 2006.175.07:41:58.75#ibcon#end of sib2, iclass 16, count 2 2006.175.07:41:58.75#ibcon#*after write, iclass 16, count 2 2006.175.07:41:58.75#ibcon#*before return 0, iclass 16, count 2 2006.175.07:41:58.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:41:58.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:41:58.75#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.07:41:58.75#ibcon#ireg 7 cls_cnt 0 2006.175.07:41:58.75#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:41:58.87#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:41:58.87#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:41:58.87#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:41:58.87#ibcon#first serial, iclass 16, count 0 2006.175.07:41:58.87#ibcon#enter sib2, iclass 16, count 0 2006.175.07:41:58.87#ibcon#flushed, iclass 16, count 0 2006.175.07:41:58.87#ibcon#about to write, iclass 16, count 0 2006.175.07:41:58.87#ibcon#wrote, iclass 16, count 0 2006.175.07:41:58.87#ibcon#about to read 3, iclass 16, count 0 2006.175.07:41:58.89#ibcon#read 3, iclass 16, count 0 2006.175.07:41:58.89#ibcon#about to read 4, iclass 16, count 0 2006.175.07:41:58.89#ibcon#read 4, iclass 16, count 0 2006.175.07:41:58.89#ibcon#about to read 5, iclass 16, count 0 2006.175.07:41:58.89#ibcon#read 5, iclass 16, count 0 2006.175.07:41:58.89#ibcon#about to read 6, iclass 16, count 0 2006.175.07:41:58.89#ibcon#read 6, iclass 16, count 0 2006.175.07:41:58.89#ibcon#end of sib2, iclass 16, count 0 2006.175.07:41:58.89#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:41:58.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:41:58.89#ibcon#[25=USB\r\n] 2006.175.07:41:58.89#ibcon#*before write, iclass 16, count 0 2006.175.07:41:58.89#ibcon#enter sib2, iclass 16, count 0 2006.175.07:41:58.89#ibcon#flushed, iclass 16, count 0 2006.175.07:41:58.89#ibcon#about to write, iclass 16, count 0 2006.175.07:41:58.89#ibcon#wrote, iclass 16, count 0 2006.175.07:41:58.89#ibcon#about to read 3, iclass 16, count 0 2006.175.07:41:58.92#ibcon#read 3, iclass 16, count 0 2006.175.07:41:58.92#ibcon#about to read 4, iclass 16, count 0 2006.175.07:41:58.92#ibcon#read 4, iclass 16, count 0 2006.175.07:41:58.92#ibcon#about to read 5, iclass 16, count 0 2006.175.07:41:58.92#ibcon#read 5, iclass 16, count 0 2006.175.07:41:58.92#ibcon#about to read 6, iclass 16, count 0 2006.175.07:41:58.92#ibcon#read 6, iclass 16, count 0 2006.175.07:41:58.92#ibcon#end of sib2, iclass 16, count 0 2006.175.07:41:58.92#ibcon#*after write, iclass 16, count 0 2006.175.07:41:58.92#ibcon#*before return 0, iclass 16, count 0 2006.175.07:41:58.92#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:41:58.92#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:41:58.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:41:58.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:41:58.92$vc4f8/valo=4,832.99 2006.175.07:41:58.92#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.07:41:58.92#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.07:41:58.92#ibcon#ireg 17 cls_cnt 0 2006.175.07:41:58.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:41:58.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:41:58.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:41:58.92#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:41:58.92#ibcon#first serial, iclass 18, count 0 2006.175.07:41:58.92#ibcon#enter sib2, iclass 18, count 0 2006.175.07:41:58.92#ibcon#flushed, iclass 18, count 0 2006.175.07:41:58.92#ibcon#about to write, iclass 18, count 0 2006.175.07:41:58.92#ibcon#wrote, iclass 18, count 0 2006.175.07:41:58.92#ibcon#about to read 3, iclass 18, count 0 2006.175.07:41:58.94#ibcon#read 3, iclass 18, count 0 2006.175.07:41:58.94#ibcon#about to read 4, iclass 18, count 0 2006.175.07:41:58.94#ibcon#read 4, iclass 18, count 0 2006.175.07:41:58.94#ibcon#about to read 5, iclass 18, count 0 2006.175.07:41:58.94#ibcon#read 5, iclass 18, count 0 2006.175.07:41:58.94#ibcon#about to read 6, iclass 18, count 0 2006.175.07:41:58.94#ibcon#read 6, iclass 18, count 0 2006.175.07:41:58.94#ibcon#end of sib2, iclass 18, count 0 2006.175.07:41:58.94#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:41:58.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:41:58.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:41:58.94#ibcon#*before write, iclass 18, count 0 2006.175.07:41:58.94#ibcon#enter sib2, iclass 18, count 0 2006.175.07:41:58.94#ibcon#flushed, iclass 18, count 0 2006.175.07:41:58.94#ibcon#about to write, iclass 18, count 0 2006.175.07:41:58.94#ibcon#wrote, iclass 18, count 0 2006.175.07:41:58.94#ibcon#about to read 3, iclass 18, count 0 2006.175.07:41:58.98#ibcon#read 3, iclass 18, count 0 2006.175.07:41:58.98#ibcon#about to read 4, iclass 18, count 0 2006.175.07:41:58.98#ibcon#read 4, iclass 18, count 0 2006.175.07:41:58.98#ibcon#about to read 5, iclass 18, count 0 2006.175.07:41:58.98#ibcon#read 5, iclass 18, count 0 2006.175.07:41:58.98#ibcon#about to read 6, iclass 18, count 0 2006.175.07:41:58.98#ibcon#read 6, iclass 18, count 0 2006.175.07:41:58.98#ibcon#end of sib2, iclass 18, count 0 2006.175.07:41:58.98#ibcon#*after write, iclass 18, count 0 2006.175.07:41:58.98#ibcon#*before return 0, iclass 18, count 0 2006.175.07:41:58.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:41:58.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:41:58.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:41:58.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:41:58.98$vc4f8/va=4,7 2006.175.07:41:58.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.175.07:41:58.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.175.07:41:58.98#ibcon#ireg 11 cls_cnt 2 2006.175.07:41:58.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:41:59.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:41:59.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:41:59.04#ibcon#enter wrdev, iclass 20, count 2 2006.175.07:41:59.04#ibcon#first serial, iclass 20, count 2 2006.175.07:41:59.04#ibcon#enter sib2, iclass 20, count 2 2006.175.07:41:59.04#ibcon#flushed, iclass 20, count 2 2006.175.07:41:59.04#ibcon#about to write, iclass 20, count 2 2006.175.07:41:59.04#ibcon#wrote, iclass 20, count 2 2006.175.07:41:59.04#ibcon#about to read 3, iclass 20, count 2 2006.175.07:41:59.06#ibcon#read 3, iclass 20, count 2 2006.175.07:41:59.06#ibcon#about to read 4, iclass 20, count 2 2006.175.07:41:59.06#ibcon#read 4, iclass 20, count 2 2006.175.07:41:59.06#ibcon#about to read 5, iclass 20, count 2 2006.175.07:41:59.06#ibcon#read 5, iclass 20, count 2 2006.175.07:41:59.06#ibcon#about to read 6, iclass 20, count 2 2006.175.07:41:59.06#ibcon#read 6, iclass 20, count 2 2006.175.07:41:59.06#ibcon#end of sib2, iclass 20, count 2 2006.175.07:41:59.06#ibcon#*mode == 0, iclass 20, count 2 2006.175.07:41:59.06#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.175.07:41:59.06#ibcon#[25=AT04-07\r\n] 2006.175.07:41:59.06#ibcon#*before write, iclass 20, count 2 2006.175.07:41:59.06#ibcon#enter sib2, iclass 20, count 2 2006.175.07:41:59.06#ibcon#flushed, iclass 20, count 2 2006.175.07:41:59.06#ibcon#about to write, iclass 20, count 2 2006.175.07:41:59.06#ibcon#wrote, iclass 20, count 2 2006.175.07:41:59.06#ibcon#about to read 3, iclass 20, count 2 2006.175.07:41:59.09#ibcon#read 3, iclass 20, count 2 2006.175.07:41:59.09#ibcon#about to read 4, iclass 20, count 2 2006.175.07:41:59.09#ibcon#read 4, iclass 20, count 2 2006.175.07:41:59.09#ibcon#about to read 5, iclass 20, count 2 2006.175.07:41:59.09#ibcon#read 5, iclass 20, count 2 2006.175.07:41:59.09#ibcon#about to read 6, iclass 20, count 2 2006.175.07:41:59.09#ibcon#read 6, iclass 20, count 2 2006.175.07:41:59.09#ibcon#end of sib2, iclass 20, count 2 2006.175.07:41:59.09#ibcon#*after write, iclass 20, count 2 2006.175.07:41:59.09#ibcon#*before return 0, iclass 20, count 2 2006.175.07:41:59.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:41:59.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:41:59.09#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.175.07:41:59.09#ibcon#ireg 7 cls_cnt 0 2006.175.07:41:59.09#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:41:59.21#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:41:59.21#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:41:59.21#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:41:59.21#ibcon#first serial, iclass 20, count 0 2006.175.07:41:59.21#ibcon#enter sib2, iclass 20, count 0 2006.175.07:41:59.21#ibcon#flushed, iclass 20, count 0 2006.175.07:41:59.21#ibcon#about to write, iclass 20, count 0 2006.175.07:41:59.21#ibcon#wrote, iclass 20, count 0 2006.175.07:41:59.21#ibcon#about to read 3, iclass 20, count 0 2006.175.07:41:59.23#ibcon#read 3, iclass 20, count 0 2006.175.07:41:59.23#ibcon#about to read 4, iclass 20, count 0 2006.175.07:41:59.23#ibcon#read 4, iclass 20, count 0 2006.175.07:41:59.23#ibcon#about to read 5, iclass 20, count 0 2006.175.07:41:59.23#ibcon#read 5, iclass 20, count 0 2006.175.07:41:59.23#ibcon#about to read 6, iclass 20, count 0 2006.175.07:41:59.23#ibcon#read 6, iclass 20, count 0 2006.175.07:41:59.23#ibcon#end of sib2, iclass 20, count 0 2006.175.07:41:59.23#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:41:59.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:41:59.23#ibcon#[25=USB\r\n] 2006.175.07:41:59.23#ibcon#*before write, iclass 20, count 0 2006.175.07:41:59.23#ibcon#enter sib2, iclass 20, count 0 2006.175.07:41:59.23#ibcon#flushed, iclass 20, count 0 2006.175.07:41:59.23#ibcon#about to write, iclass 20, count 0 2006.175.07:41:59.23#ibcon#wrote, iclass 20, count 0 2006.175.07:41:59.23#ibcon#about to read 3, iclass 20, count 0 2006.175.07:41:59.26#ibcon#read 3, iclass 20, count 0 2006.175.07:41:59.26#ibcon#about to read 4, iclass 20, count 0 2006.175.07:41:59.26#ibcon#read 4, iclass 20, count 0 2006.175.07:41:59.26#ibcon#about to read 5, iclass 20, count 0 2006.175.07:41:59.26#ibcon#read 5, iclass 20, count 0 2006.175.07:41:59.26#ibcon#about to read 6, iclass 20, count 0 2006.175.07:41:59.26#ibcon#read 6, iclass 20, count 0 2006.175.07:41:59.26#ibcon#end of sib2, iclass 20, count 0 2006.175.07:41:59.26#ibcon#*after write, iclass 20, count 0 2006.175.07:41:59.26#ibcon#*before return 0, iclass 20, count 0 2006.175.07:41:59.26#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:41:59.26#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:41:59.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:41:59.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:41:59.26$vc4f8/valo=5,652.99 2006.175.07:41:59.26#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.07:41:59.26#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.07:41:59.26#ibcon#ireg 17 cls_cnt 0 2006.175.07:41:59.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:41:59.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:41:59.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:41:59.26#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:41:59.26#ibcon#first serial, iclass 22, count 0 2006.175.07:41:59.26#ibcon#enter sib2, iclass 22, count 0 2006.175.07:41:59.26#ibcon#flushed, iclass 22, count 0 2006.175.07:41:59.26#ibcon#about to write, iclass 22, count 0 2006.175.07:41:59.26#ibcon#wrote, iclass 22, count 0 2006.175.07:41:59.26#ibcon#about to read 3, iclass 22, count 0 2006.175.07:41:59.28#ibcon#read 3, iclass 22, count 0 2006.175.07:41:59.28#ibcon#about to read 4, iclass 22, count 0 2006.175.07:41:59.28#ibcon#read 4, iclass 22, count 0 2006.175.07:41:59.28#ibcon#about to read 5, iclass 22, count 0 2006.175.07:41:59.28#ibcon#read 5, iclass 22, count 0 2006.175.07:41:59.28#ibcon#about to read 6, iclass 22, count 0 2006.175.07:41:59.28#ibcon#read 6, iclass 22, count 0 2006.175.07:41:59.28#ibcon#end of sib2, iclass 22, count 0 2006.175.07:41:59.28#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:41:59.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:41:59.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:41:59.28#ibcon#*before write, iclass 22, count 0 2006.175.07:41:59.28#ibcon#enter sib2, iclass 22, count 0 2006.175.07:41:59.28#ibcon#flushed, iclass 22, count 0 2006.175.07:41:59.28#ibcon#about to write, iclass 22, count 0 2006.175.07:41:59.28#ibcon#wrote, iclass 22, count 0 2006.175.07:41:59.28#ibcon#about to read 3, iclass 22, count 0 2006.175.07:41:59.32#ibcon#read 3, iclass 22, count 0 2006.175.07:41:59.32#ibcon#about to read 4, iclass 22, count 0 2006.175.07:41:59.32#ibcon#read 4, iclass 22, count 0 2006.175.07:41:59.32#ibcon#about to read 5, iclass 22, count 0 2006.175.07:41:59.32#ibcon#read 5, iclass 22, count 0 2006.175.07:41:59.32#ibcon#about to read 6, iclass 22, count 0 2006.175.07:41:59.32#ibcon#read 6, iclass 22, count 0 2006.175.07:41:59.32#ibcon#end of sib2, iclass 22, count 0 2006.175.07:41:59.32#ibcon#*after write, iclass 22, count 0 2006.175.07:41:59.32#ibcon#*before return 0, iclass 22, count 0 2006.175.07:41:59.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:41:59.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:41:59.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:41:59.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:41:59.32$vc4f8/va=5,7 2006.175.07:41:59.32#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.07:41:59.32#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.07:41:59.32#ibcon#ireg 11 cls_cnt 2 2006.175.07:41:59.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:41:59.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:41:59.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:41:59.38#ibcon#enter wrdev, iclass 24, count 2 2006.175.07:41:59.38#ibcon#first serial, iclass 24, count 2 2006.175.07:41:59.38#ibcon#enter sib2, iclass 24, count 2 2006.175.07:41:59.38#ibcon#flushed, iclass 24, count 2 2006.175.07:41:59.38#ibcon#about to write, iclass 24, count 2 2006.175.07:41:59.38#ibcon#wrote, iclass 24, count 2 2006.175.07:41:59.38#ibcon#about to read 3, iclass 24, count 2 2006.175.07:41:59.40#ibcon#read 3, iclass 24, count 2 2006.175.07:41:59.40#ibcon#about to read 4, iclass 24, count 2 2006.175.07:41:59.40#ibcon#read 4, iclass 24, count 2 2006.175.07:41:59.40#ibcon#about to read 5, iclass 24, count 2 2006.175.07:41:59.40#ibcon#read 5, iclass 24, count 2 2006.175.07:41:59.40#ibcon#about to read 6, iclass 24, count 2 2006.175.07:41:59.40#ibcon#read 6, iclass 24, count 2 2006.175.07:41:59.40#ibcon#end of sib2, iclass 24, count 2 2006.175.07:41:59.40#ibcon#*mode == 0, iclass 24, count 2 2006.175.07:41:59.40#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.07:41:59.40#ibcon#[25=AT05-07\r\n] 2006.175.07:41:59.40#ibcon#*before write, iclass 24, count 2 2006.175.07:41:59.40#ibcon#enter sib2, iclass 24, count 2 2006.175.07:41:59.40#ibcon#flushed, iclass 24, count 2 2006.175.07:41:59.40#ibcon#about to write, iclass 24, count 2 2006.175.07:41:59.40#ibcon#wrote, iclass 24, count 2 2006.175.07:41:59.40#ibcon#about to read 3, iclass 24, count 2 2006.175.07:41:59.43#ibcon#read 3, iclass 24, count 2 2006.175.07:41:59.43#ibcon#about to read 4, iclass 24, count 2 2006.175.07:41:59.43#ibcon#read 4, iclass 24, count 2 2006.175.07:41:59.43#ibcon#about to read 5, iclass 24, count 2 2006.175.07:41:59.43#ibcon#read 5, iclass 24, count 2 2006.175.07:41:59.43#ibcon#about to read 6, iclass 24, count 2 2006.175.07:41:59.43#ibcon#read 6, iclass 24, count 2 2006.175.07:41:59.43#ibcon#end of sib2, iclass 24, count 2 2006.175.07:41:59.43#ibcon#*after write, iclass 24, count 2 2006.175.07:41:59.43#ibcon#*before return 0, iclass 24, count 2 2006.175.07:41:59.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:41:59.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:41:59.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.07:41:59.43#ibcon#ireg 7 cls_cnt 0 2006.175.07:41:59.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:41:59.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:41:59.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:41:59.55#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:41:59.55#ibcon#first serial, iclass 24, count 0 2006.175.07:41:59.55#ibcon#enter sib2, iclass 24, count 0 2006.175.07:41:59.55#ibcon#flushed, iclass 24, count 0 2006.175.07:41:59.55#ibcon#about to write, iclass 24, count 0 2006.175.07:41:59.55#ibcon#wrote, iclass 24, count 0 2006.175.07:41:59.55#ibcon#about to read 3, iclass 24, count 0 2006.175.07:41:59.57#ibcon#read 3, iclass 24, count 0 2006.175.07:41:59.57#ibcon#about to read 4, iclass 24, count 0 2006.175.07:41:59.57#ibcon#read 4, iclass 24, count 0 2006.175.07:41:59.57#ibcon#about to read 5, iclass 24, count 0 2006.175.07:41:59.57#ibcon#read 5, iclass 24, count 0 2006.175.07:41:59.57#ibcon#about to read 6, iclass 24, count 0 2006.175.07:41:59.57#ibcon#read 6, iclass 24, count 0 2006.175.07:41:59.57#ibcon#end of sib2, iclass 24, count 0 2006.175.07:41:59.57#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:41:59.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:41:59.57#ibcon#[25=USB\r\n] 2006.175.07:41:59.57#ibcon#*before write, iclass 24, count 0 2006.175.07:41:59.57#ibcon#enter sib2, iclass 24, count 0 2006.175.07:41:59.57#ibcon#flushed, iclass 24, count 0 2006.175.07:41:59.57#ibcon#about to write, iclass 24, count 0 2006.175.07:41:59.57#ibcon#wrote, iclass 24, count 0 2006.175.07:41:59.57#ibcon#about to read 3, iclass 24, count 0 2006.175.07:41:59.60#ibcon#read 3, iclass 24, count 0 2006.175.07:41:59.60#ibcon#about to read 4, iclass 24, count 0 2006.175.07:41:59.60#ibcon#read 4, iclass 24, count 0 2006.175.07:41:59.60#ibcon#about to read 5, iclass 24, count 0 2006.175.07:41:59.60#ibcon#read 5, iclass 24, count 0 2006.175.07:41:59.60#ibcon#about to read 6, iclass 24, count 0 2006.175.07:41:59.60#ibcon#read 6, iclass 24, count 0 2006.175.07:41:59.60#ibcon#end of sib2, iclass 24, count 0 2006.175.07:41:59.60#ibcon#*after write, iclass 24, count 0 2006.175.07:41:59.60#ibcon#*before return 0, iclass 24, count 0 2006.175.07:41:59.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:41:59.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:41:59.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:41:59.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:41:59.60$vc4f8/valo=6,772.99 2006.175.07:41:59.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.07:41:59.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.07:41:59.60#ibcon#ireg 17 cls_cnt 0 2006.175.07:41:59.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:41:59.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:41:59.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:41:59.60#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:41:59.60#ibcon#first serial, iclass 26, count 0 2006.175.07:41:59.60#ibcon#enter sib2, iclass 26, count 0 2006.175.07:41:59.60#ibcon#flushed, iclass 26, count 0 2006.175.07:41:59.60#ibcon#about to write, iclass 26, count 0 2006.175.07:41:59.60#ibcon#wrote, iclass 26, count 0 2006.175.07:41:59.60#ibcon#about to read 3, iclass 26, count 0 2006.175.07:41:59.62#ibcon#read 3, iclass 26, count 0 2006.175.07:41:59.62#ibcon#about to read 4, iclass 26, count 0 2006.175.07:41:59.62#ibcon#read 4, iclass 26, count 0 2006.175.07:41:59.62#ibcon#about to read 5, iclass 26, count 0 2006.175.07:41:59.62#ibcon#read 5, iclass 26, count 0 2006.175.07:41:59.62#ibcon#about to read 6, iclass 26, count 0 2006.175.07:41:59.62#ibcon#read 6, iclass 26, count 0 2006.175.07:41:59.62#ibcon#end of sib2, iclass 26, count 0 2006.175.07:41:59.62#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:41:59.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:41:59.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:41:59.62#ibcon#*before write, iclass 26, count 0 2006.175.07:41:59.62#ibcon#enter sib2, iclass 26, count 0 2006.175.07:41:59.62#ibcon#flushed, iclass 26, count 0 2006.175.07:41:59.62#ibcon#about to write, iclass 26, count 0 2006.175.07:41:59.62#ibcon#wrote, iclass 26, count 0 2006.175.07:41:59.62#ibcon#about to read 3, iclass 26, count 0 2006.175.07:41:59.66#ibcon#read 3, iclass 26, count 0 2006.175.07:41:59.66#ibcon#about to read 4, iclass 26, count 0 2006.175.07:41:59.66#ibcon#read 4, iclass 26, count 0 2006.175.07:41:59.66#ibcon#about to read 5, iclass 26, count 0 2006.175.07:41:59.66#ibcon#read 5, iclass 26, count 0 2006.175.07:41:59.66#ibcon#about to read 6, iclass 26, count 0 2006.175.07:41:59.66#ibcon#read 6, iclass 26, count 0 2006.175.07:41:59.66#ibcon#end of sib2, iclass 26, count 0 2006.175.07:41:59.66#ibcon#*after write, iclass 26, count 0 2006.175.07:41:59.66#ibcon#*before return 0, iclass 26, count 0 2006.175.07:41:59.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:41:59.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:41:59.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:41:59.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:41:59.66$vc4f8/va=6,6 2006.175.07:41:59.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.07:41:59.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.07:41:59.66#ibcon#ireg 11 cls_cnt 2 2006.175.07:41:59.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:41:59.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:41:59.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:41:59.72#ibcon#enter wrdev, iclass 28, count 2 2006.175.07:41:59.72#ibcon#first serial, iclass 28, count 2 2006.175.07:41:59.72#ibcon#enter sib2, iclass 28, count 2 2006.175.07:41:59.72#ibcon#flushed, iclass 28, count 2 2006.175.07:41:59.72#ibcon#about to write, iclass 28, count 2 2006.175.07:41:59.72#ibcon#wrote, iclass 28, count 2 2006.175.07:41:59.72#ibcon#about to read 3, iclass 28, count 2 2006.175.07:41:59.74#ibcon#read 3, iclass 28, count 2 2006.175.07:41:59.74#ibcon#about to read 4, iclass 28, count 2 2006.175.07:41:59.74#ibcon#read 4, iclass 28, count 2 2006.175.07:41:59.74#ibcon#about to read 5, iclass 28, count 2 2006.175.07:41:59.74#ibcon#read 5, iclass 28, count 2 2006.175.07:41:59.74#ibcon#about to read 6, iclass 28, count 2 2006.175.07:41:59.74#ibcon#read 6, iclass 28, count 2 2006.175.07:41:59.74#ibcon#end of sib2, iclass 28, count 2 2006.175.07:41:59.74#ibcon#*mode == 0, iclass 28, count 2 2006.175.07:41:59.74#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.07:41:59.74#ibcon#[25=AT06-06\r\n] 2006.175.07:41:59.74#ibcon#*before write, iclass 28, count 2 2006.175.07:41:59.74#ibcon#enter sib2, iclass 28, count 2 2006.175.07:41:59.74#ibcon#flushed, iclass 28, count 2 2006.175.07:41:59.74#ibcon#about to write, iclass 28, count 2 2006.175.07:41:59.74#ibcon#wrote, iclass 28, count 2 2006.175.07:41:59.74#ibcon#about to read 3, iclass 28, count 2 2006.175.07:41:59.77#ibcon#read 3, iclass 28, count 2 2006.175.07:41:59.77#ibcon#about to read 4, iclass 28, count 2 2006.175.07:41:59.77#ibcon#read 4, iclass 28, count 2 2006.175.07:41:59.77#ibcon#about to read 5, iclass 28, count 2 2006.175.07:41:59.77#ibcon#read 5, iclass 28, count 2 2006.175.07:41:59.77#ibcon#about to read 6, iclass 28, count 2 2006.175.07:41:59.77#ibcon#read 6, iclass 28, count 2 2006.175.07:41:59.77#ibcon#end of sib2, iclass 28, count 2 2006.175.07:41:59.77#ibcon#*after write, iclass 28, count 2 2006.175.07:41:59.77#ibcon#*before return 0, iclass 28, count 2 2006.175.07:41:59.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:41:59.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:41:59.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.07:41:59.77#ibcon#ireg 7 cls_cnt 0 2006.175.07:41:59.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:41:59.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:41:59.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:41:59.89#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:41:59.89#ibcon#first serial, iclass 28, count 0 2006.175.07:41:59.89#ibcon#enter sib2, iclass 28, count 0 2006.175.07:41:59.89#ibcon#flushed, iclass 28, count 0 2006.175.07:41:59.89#ibcon#about to write, iclass 28, count 0 2006.175.07:41:59.89#ibcon#wrote, iclass 28, count 0 2006.175.07:41:59.89#ibcon#about to read 3, iclass 28, count 0 2006.175.07:41:59.91#ibcon#read 3, iclass 28, count 0 2006.175.07:41:59.91#ibcon#about to read 4, iclass 28, count 0 2006.175.07:41:59.91#ibcon#read 4, iclass 28, count 0 2006.175.07:41:59.91#ibcon#about to read 5, iclass 28, count 0 2006.175.07:41:59.91#ibcon#read 5, iclass 28, count 0 2006.175.07:41:59.91#ibcon#about to read 6, iclass 28, count 0 2006.175.07:41:59.91#ibcon#read 6, iclass 28, count 0 2006.175.07:41:59.91#ibcon#end of sib2, iclass 28, count 0 2006.175.07:41:59.91#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:41:59.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:41:59.91#ibcon#[25=USB\r\n] 2006.175.07:41:59.91#ibcon#*before write, iclass 28, count 0 2006.175.07:41:59.91#ibcon#enter sib2, iclass 28, count 0 2006.175.07:41:59.91#ibcon#flushed, iclass 28, count 0 2006.175.07:41:59.91#ibcon#about to write, iclass 28, count 0 2006.175.07:41:59.91#ibcon#wrote, iclass 28, count 0 2006.175.07:41:59.91#ibcon#about to read 3, iclass 28, count 0 2006.175.07:41:59.94#ibcon#read 3, iclass 28, count 0 2006.175.07:41:59.94#ibcon#about to read 4, iclass 28, count 0 2006.175.07:41:59.94#ibcon#read 4, iclass 28, count 0 2006.175.07:41:59.94#ibcon#about to read 5, iclass 28, count 0 2006.175.07:41:59.94#ibcon#read 5, iclass 28, count 0 2006.175.07:41:59.94#ibcon#about to read 6, iclass 28, count 0 2006.175.07:41:59.94#ibcon#read 6, iclass 28, count 0 2006.175.07:41:59.94#ibcon#end of sib2, iclass 28, count 0 2006.175.07:41:59.94#ibcon#*after write, iclass 28, count 0 2006.175.07:41:59.94#ibcon#*before return 0, iclass 28, count 0 2006.175.07:41:59.94#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:41:59.94#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:41:59.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:41:59.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:41:59.94$vc4f8/valo=7,832.99 2006.175.07:41:59.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.07:41:59.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.07:41:59.94#ibcon#ireg 17 cls_cnt 0 2006.175.07:41:59.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:41:59.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:41:59.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:41:59.94#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:41:59.94#ibcon#first serial, iclass 30, count 0 2006.175.07:41:59.94#ibcon#enter sib2, iclass 30, count 0 2006.175.07:41:59.94#ibcon#flushed, iclass 30, count 0 2006.175.07:41:59.94#ibcon#about to write, iclass 30, count 0 2006.175.07:41:59.94#ibcon#wrote, iclass 30, count 0 2006.175.07:41:59.94#ibcon#about to read 3, iclass 30, count 0 2006.175.07:41:59.96#ibcon#read 3, iclass 30, count 0 2006.175.07:41:59.96#ibcon#about to read 4, iclass 30, count 0 2006.175.07:41:59.96#ibcon#read 4, iclass 30, count 0 2006.175.07:41:59.96#ibcon#about to read 5, iclass 30, count 0 2006.175.07:41:59.96#ibcon#read 5, iclass 30, count 0 2006.175.07:41:59.96#ibcon#about to read 6, iclass 30, count 0 2006.175.07:41:59.96#ibcon#read 6, iclass 30, count 0 2006.175.07:41:59.96#ibcon#end of sib2, iclass 30, count 0 2006.175.07:41:59.96#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:41:59.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:41:59.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:41:59.96#ibcon#*before write, iclass 30, count 0 2006.175.07:41:59.96#ibcon#enter sib2, iclass 30, count 0 2006.175.07:41:59.96#ibcon#flushed, iclass 30, count 0 2006.175.07:41:59.96#ibcon#about to write, iclass 30, count 0 2006.175.07:41:59.96#ibcon#wrote, iclass 30, count 0 2006.175.07:41:59.96#ibcon#about to read 3, iclass 30, count 0 2006.175.07:42:00.00#ibcon#read 3, iclass 30, count 0 2006.175.07:42:00.00#ibcon#about to read 4, iclass 30, count 0 2006.175.07:42:00.00#ibcon#read 4, iclass 30, count 0 2006.175.07:42:00.00#ibcon#about to read 5, iclass 30, count 0 2006.175.07:42:00.00#ibcon#read 5, iclass 30, count 0 2006.175.07:42:00.00#ibcon#about to read 6, iclass 30, count 0 2006.175.07:42:00.00#ibcon#read 6, iclass 30, count 0 2006.175.07:42:00.00#ibcon#end of sib2, iclass 30, count 0 2006.175.07:42:00.00#ibcon#*after write, iclass 30, count 0 2006.175.07:42:00.00#ibcon#*before return 0, iclass 30, count 0 2006.175.07:42:00.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:42:00.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:42:00.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:42:00.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:42:00.00$vc4f8/va=7,6 2006.175.07:42:00.00#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.07:42:00.00#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.07:42:00.00#ibcon#ireg 11 cls_cnt 2 2006.175.07:42:00.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:42:00.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:42:00.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:42:00.06#ibcon#enter wrdev, iclass 32, count 2 2006.175.07:42:00.06#ibcon#first serial, iclass 32, count 2 2006.175.07:42:00.06#ibcon#enter sib2, iclass 32, count 2 2006.175.07:42:00.06#ibcon#flushed, iclass 32, count 2 2006.175.07:42:00.06#ibcon#about to write, iclass 32, count 2 2006.175.07:42:00.06#ibcon#wrote, iclass 32, count 2 2006.175.07:42:00.06#ibcon#about to read 3, iclass 32, count 2 2006.175.07:42:00.08#ibcon#read 3, iclass 32, count 2 2006.175.07:42:00.08#ibcon#about to read 4, iclass 32, count 2 2006.175.07:42:00.08#ibcon#read 4, iclass 32, count 2 2006.175.07:42:00.08#ibcon#about to read 5, iclass 32, count 2 2006.175.07:42:00.08#ibcon#read 5, iclass 32, count 2 2006.175.07:42:00.08#ibcon#about to read 6, iclass 32, count 2 2006.175.07:42:00.08#ibcon#read 6, iclass 32, count 2 2006.175.07:42:00.08#ibcon#end of sib2, iclass 32, count 2 2006.175.07:42:00.08#ibcon#*mode == 0, iclass 32, count 2 2006.175.07:42:00.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.07:42:00.08#ibcon#[25=AT07-06\r\n] 2006.175.07:42:00.08#ibcon#*before write, iclass 32, count 2 2006.175.07:42:00.08#ibcon#enter sib2, iclass 32, count 2 2006.175.07:42:00.08#ibcon#flushed, iclass 32, count 2 2006.175.07:42:00.08#ibcon#about to write, iclass 32, count 2 2006.175.07:42:00.08#ibcon#wrote, iclass 32, count 2 2006.175.07:42:00.08#ibcon#about to read 3, iclass 32, count 2 2006.175.07:42:00.11#ibcon#read 3, iclass 32, count 2 2006.175.07:42:00.11#ibcon#about to read 4, iclass 32, count 2 2006.175.07:42:00.11#ibcon#read 4, iclass 32, count 2 2006.175.07:42:00.11#ibcon#about to read 5, iclass 32, count 2 2006.175.07:42:00.11#ibcon#read 5, iclass 32, count 2 2006.175.07:42:00.11#ibcon#about to read 6, iclass 32, count 2 2006.175.07:42:00.11#ibcon#read 6, iclass 32, count 2 2006.175.07:42:00.11#ibcon#end of sib2, iclass 32, count 2 2006.175.07:42:00.11#ibcon#*after write, iclass 32, count 2 2006.175.07:42:00.11#ibcon#*before return 0, iclass 32, count 2 2006.175.07:42:00.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:42:00.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:42:00.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.07:42:00.11#ibcon#ireg 7 cls_cnt 0 2006.175.07:42:00.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:42:00.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:42:00.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:42:00.23#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:42:00.23#ibcon#first serial, iclass 32, count 0 2006.175.07:42:00.23#ibcon#enter sib2, iclass 32, count 0 2006.175.07:42:00.23#ibcon#flushed, iclass 32, count 0 2006.175.07:42:00.23#ibcon#about to write, iclass 32, count 0 2006.175.07:42:00.23#ibcon#wrote, iclass 32, count 0 2006.175.07:42:00.23#ibcon#about to read 3, iclass 32, count 0 2006.175.07:42:00.25#ibcon#read 3, iclass 32, count 0 2006.175.07:42:00.25#ibcon#about to read 4, iclass 32, count 0 2006.175.07:42:00.25#ibcon#read 4, iclass 32, count 0 2006.175.07:42:00.25#ibcon#about to read 5, iclass 32, count 0 2006.175.07:42:00.25#ibcon#read 5, iclass 32, count 0 2006.175.07:42:00.25#ibcon#about to read 6, iclass 32, count 0 2006.175.07:42:00.25#ibcon#read 6, iclass 32, count 0 2006.175.07:42:00.25#ibcon#end of sib2, iclass 32, count 0 2006.175.07:42:00.25#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:42:00.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:42:00.25#ibcon#[25=USB\r\n] 2006.175.07:42:00.25#ibcon#*before write, iclass 32, count 0 2006.175.07:42:00.25#ibcon#enter sib2, iclass 32, count 0 2006.175.07:42:00.25#ibcon#flushed, iclass 32, count 0 2006.175.07:42:00.25#ibcon#about to write, iclass 32, count 0 2006.175.07:42:00.25#ibcon#wrote, iclass 32, count 0 2006.175.07:42:00.25#ibcon#about to read 3, iclass 32, count 0 2006.175.07:42:00.28#ibcon#read 3, iclass 32, count 0 2006.175.07:42:00.28#ibcon#about to read 4, iclass 32, count 0 2006.175.07:42:00.28#ibcon#read 4, iclass 32, count 0 2006.175.07:42:00.28#ibcon#about to read 5, iclass 32, count 0 2006.175.07:42:00.28#ibcon#read 5, iclass 32, count 0 2006.175.07:42:00.28#ibcon#about to read 6, iclass 32, count 0 2006.175.07:42:00.28#ibcon#read 6, iclass 32, count 0 2006.175.07:42:00.28#ibcon#end of sib2, iclass 32, count 0 2006.175.07:42:00.28#ibcon#*after write, iclass 32, count 0 2006.175.07:42:00.28#ibcon#*before return 0, iclass 32, count 0 2006.175.07:42:00.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:42:00.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:42:00.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:42:00.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:42:00.28$vc4f8/valo=8,852.99 2006.175.07:42:00.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.07:42:00.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.07:42:00.28#ibcon#ireg 17 cls_cnt 0 2006.175.07:42:00.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:42:00.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:42:00.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:42:00.28#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:42:00.28#ibcon#first serial, iclass 34, count 0 2006.175.07:42:00.28#ibcon#enter sib2, iclass 34, count 0 2006.175.07:42:00.28#ibcon#flushed, iclass 34, count 0 2006.175.07:42:00.28#ibcon#about to write, iclass 34, count 0 2006.175.07:42:00.28#ibcon#wrote, iclass 34, count 0 2006.175.07:42:00.28#ibcon#about to read 3, iclass 34, count 0 2006.175.07:42:00.30#ibcon#read 3, iclass 34, count 0 2006.175.07:42:00.30#ibcon#about to read 4, iclass 34, count 0 2006.175.07:42:00.30#ibcon#read 4, iclass 34, count 0 2006.175.07:42:00.30#ibcon#about to read 5, iclass 34, count 0 2006.175.07:42:00.30#ibcon#read 5, iclass 34, count 0 2006.175.07:42:00.30#ibcon#about to read 6, iclass 34, count 0 2006.175.07:42:00.30#ibcon#read 6, iclass 34, count 0 2006.175.07:42:00.30#ibcon#end of sib2, iclass 34, count 0 2006.175.07:42:00.30#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:42:00.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:42:00.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:42:00.30#ibcon#*before write, iclass 34, count 0 2006.175.07:42:00.30#ibcon#enter sib2, iclass 34, count 0 2006.175.07:42:00.30#ibcon#flushed, iclass 34, count 0 2006.175.07:42:00.30#ibcon#about to write, iclass 34, count 0 2006.175.07:42:00.30#ibcon#wrote, iclass 34, count 0 2006.175.07:42:00.30#ibcon#about to read 3, iclass 34, count 0 2006.175.07:42:00.34#ibcon#read 3, iclass 34, count 0 2006.175.07:42:00.34#ibcon#about to read 4, iclass 34, count 0 2006.175.07:42:00.34#ibcon#read 4, iclass 34, count 0 2006.175.07:42:00.34#ibcon#about to read 5, iclass 34, count 0 2006.175.07:42:00.34#ibcon#read 5, iclass 34, count 0 2006.175.07:42:00.34#ibcon#about to read 6, iclass 34, count 0 2006.175.07:42:00.34#ibcon#read 6, iclass 34, count 0 2006.175.07:42:00.34#ibcon#end of sib2, iclass 34, count 0 2006.175.07:42:00.34#ibcon#*after write, iclass 34, count 0 2006.175.07:42:00.34#ibcon#*before return 0, iclass 34, count 0 2006.175.07:42:00.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:42:00.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:42:00.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:42:00.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:42:00.34$vc4f8/va=8,6 2006.175.07:42:00.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.07:42:00.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.07:42:00.34#ibcon#ireg 11 cls_cnt 2 2006.175.07:42:00.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:42:00.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:42:00.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:42:00.40#ibcon#enter wrdev, iclass 36, count 2 2006.175.07:42:00.40#ibcon#first serial, iclass 36, count 2 2006.175.07:42:00.40#ibcon#enter sib2, iclass 36, count 2 2006.175.07:42:00.40#ibcon#flushed, iclass 36, count 2 2006.175.07:42:00.40#ibcon#about to write, iclass 36, count 2 2006.175.07:42:00.40#ibcon#wrote, iclass 36, count 2 2006.175.07:42:00.40#ibcon#about to read 3, iclass 36, count 2 2006.175.07:42:00.42#ibcon#read 3, iclass 36, count 2 2006.175.07:42:00.42#ibcon#about to read 4, iclass 36, count 2 2006.175.07:42:00.42#ibcon#read 4, iclass 36, count 2 2006.175.07:42:00.42#ibcon#about to read 5, iclass 36, count 2 2006.175.07:42:00.42#ibcon#read 5, iclass 36, count 2 2006.175.07:42:00.42#ibcon#about to read 6, iclass 36, count 2 2006.175.07:42:00.42#ibcon#read 6, iclass 36, count 2 2006.175.07:42:00.42#ibcon#end of sib2, iclass 36, count 2 2006.175.07:42:00.42#ibcon#*mode == 0, iclass 36, count 2 2006.175.07:42:00.42#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.07:42:00.42#ibcon#[25=AT08-06\r\n] 2006.175.07:42:00.42#ibcon#*before write, iclass 36, count 2 2006.175.07:42:00.42#ibcon#enter sib2, iclass 36, count 2 2006.175.07:42:00.42#ibcon#flushed, iclass 36, count 2 2006.175.07:42:00.42#ibcon#about to write, iclass 36, count 2 2006.175.07:42:00.42#ibcon#wrote, iclass 36, count 2 2006.175.07:42:00.42#ibcon#about to read 3, iclass 36, count 2 2006.175.07:42:00.45#ibcon#read 3, iclass 36, count 2 2006.175.07:42:00.45#ibcon#about to read 4, iclass 36, count 2 2006.175.07:42:00.45#ibcon#read 4, iclass 36, count 2 2006.175.07:42:00.45#ibcon#about to read 5, iclass 36, count 2 2006.175.07:42:00.45#ibcon#read 5, iclass 36, count 2 2006.175.07:42:00.45#ibcon#about to read 6, iclass 36, count 2 2006.175.07:42:00.45#ibcon#read 6, iclass 36, count 2 2006.175.07:42:00.45#ibcon#end of sib2, iclass 36, count 2 2006.175.07:42:00.45#ibcon#*after write, iclass 36, count 2 2006.175.07:42:00.45#ibcon#*before return 0, iclass 36, count 2 2006.175.07:42:00.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:42:00.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:42:00.45#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.07:42:00.45#ibcon#ireg 7 cls_cnt 0 2006.175.07:42:00.45#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:42:00.57#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:42:00.57#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:42:00.57#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:42:00.57#ibcon#first serial, iclass 36, count 0 2006.175.07:42:00.57#ibcon#enter sib2, iclass 36, count 0 2006.175.07:42:00.57#ibcon#flushed, iclass 36, count 0 2006.175.07:42:00.57#ibcon#about to write, iclass 36, count 0 2006.175.07:42:00.57#ibcon#wrote, iclass 36, count 0 2006.175.07:42:00.57#ibcon#about to read 3, iclass 36, count 0 2006.175.07:42:00.59#ibcon#read 3, iclass 36, count 0 2006.175.07:42:00.59#ibcon#about to read 4, iclass 36, count 0 2006.175.07:42:00.59#ibcon#read 4, iclass 36, count 0 2006.175.07:42:00.59#ibcon#about to read 5, iclass 36, count 0 2006.175.07:42:00.59#ibcon#read 5, iclass 36, count 0 2006.175.07:42:00.59#ibcon#about to read 6, iclass 36, count 0 2006.175.07:42:00.59#ibcon#read 6, iclass 36, count 0 2006.175.07:42:00.59#ibcon#end of sib2, iclass 36, count 0 2006.175.07:42:00.59#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:42:00.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:42:00.59#ibcon#[25=USB\r\n] 2006.175.07:42:00.59#ibcon#*before write, iclass 36, count 0 2006.175.07:42:00.59#ibcon#enter sib2, iclass 36, count 0 2006.175.07:42:00.59#ibcon#flushed, iclass 36, count 0 2006.175.07:42:00.59#ibcon#about to write, iclass 36, count 0 2006.175.07:42:00.59#ibcon#wrote, iclass 36, count 0 2006.175.07:42:00.59#ibcon#about to read 3, iclass 36, count 0 2006.175.07:42:00.62#ibcon#read 3, iclass 36, count 0 2006.175.07:42:00.62#ibcon#about to read 4, iclass 36, count 0 2006.175.07:42:00.62#ibcon#read 4, iclass 36, count 0 2006.175.07:42:00.62#ibcon#about to read 5, iclass 36, count 0 2006.175.07:42:00.62#ibcon#read 5, iclass 36, count 0 2006.175.07:42:00.62#ibcon#about to read 6, iclass 36, count 0 2006.175.07:42:00.62#ibcon#read 6, iclass 36, count 0 2006.175.07:42:00.62#ibcon#end of sib2, iclass 36, count 0 2006.175.07:42:00.62#ibcon#*after write, iclass 36, count 0 2006.175.07:42:00.62#ibcon#*before return 0, iclass 36, count 0 2006.175.07:42:00.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:42:00.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:42:00.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:42:00.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:42:00.62$vc4f8/vblo=1,632.99 2006.175.07:42:00.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:42:00.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:42:00.62#ibcon#ireg 17 cls_cnt 0 2006.175.07:42:00.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:42:00.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:42:00.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:42:00.62#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:42:00.62#ibcon#first serial, iclass 38, count 0 2006.175.07:42:00.62#ibcon#enter sib2, iclass 38, count 0 2006.175.07:42:00.62#ibcon#flushed, iclass 38, count 0 2006.175.07:42:00.62#ibcon#about to write, iclass 38, count 0 2006.175.07:42:00.62#ibcon#wrote, iclass 38, count 0 2006.175.07:42:00.62#ibcon#about to read 3, iclass 38, count 0 2006.175.07:42:00.64#ibcon#read 3, iclass 38, count 0 2006.175.07:42:00.64#ibcon#about to read 4, iclass 38, count 0 2006.175.07:42:00.64#ibcon#read 4, iclass 38, count 0 2006.175.07:42:00.64#ibcon#about to read 5, iclass 38, count 0 2006.175.07:42:00.64#ibcon#read 5, iclass 38, count 0 2006.175.07:42:00.64#ibcon#about to read 6, iclass 38, count 0 2006.175.07:42:00.64#ibcon#read 6, iclass 38, count 0 2006.175.07:42:00.64#ibcon#end of sib2, iclass 38, count 0 2006.175.07:42:00.64#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:42:00.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:42:00.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:42:00.64#ibcon#*before write, iclass 38, count 0 2006.175.07:42:00.64#ibcon#enter sib2, iclass 38, count 0 2006.175.07:42:00.64#ibcon#flushed, iclass 38, count 0 2006.175.07:42:00.64#ibcon#about to write, iclass 38, count 0 2006.175.07:42:00.64#ibcon#wrote, iclass 38, count 0 2006.175.07:42:00.64#ibcon#about to read 3, iclass 38, count 0 2006.175.07:42:00.68#ibcon#read 3, iclass 38, count 0 2006.175.07:42:00.68#ibcon#about to read 4, iclass 38, count 0 2006.175.07:42:00.68#ibcon#read 4, iclass 38, count 0 2006.175.07:42:00.68#ibcon#about to read 5, iclass 38, count 0 2006.175.07:42:00.68#ibcon#read 5, iclass 38, count 0 2006.175.07:42:00.68#ibcon#about to read 6, iclass 38, count 0 2006.175.07:42:00.68#ibcon#read 6, iclass 38, count 0 2006.175.07:42:00.68#ibcon#end of sib2, iclass 38, count 0 2006.175.07:42:00.68#ibcon#*after write, iclass 38, count 0 2006.175.07:42:00.68#ibcon#*before return 0, iclass 38, count 0 2006.175.07:42:00.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:42:00.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:42:00.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:42:00.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:42:00.68$vc4f8/vb=1,4 2006.175.07:42:00.68#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.07:42:00.68#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.07:42:00.68#ibcon#ireg 11 cls_cnt 2 2006.175.07:42:00.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:42:00.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:42:00.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:42:00.68#ibcon#enter wrdev, iclass 40, count 2 2006.175.07:42:00.68#ibcon#first serial, iclass 40, count 2 2006.175.07:42:00.68#ibcon#enter sib2, iclass 40, count 2 2006.175.07:42:00.68#ibcon#flushed, iclass 40, count 2 2006.175.07:42:00.68#ibcon#about to write, iclass 40, count 2 2006.175.07:42:00.68#ibcon#wrote, iclass 40, count 2 2006.175.07:42:00.68#ibcon#about to read 3, iclass 40, count 2 2006.175.07:42:00.70#ibcon#read 3, iclass 40, count 2 2006.175.07:42:00.70#ibcon#about to read 4, iclass 40, count 2 2006.175.07:42:00.70#ibcon#read 4, iclass 40, count 2 2006.175.07:42:00.70#ibcon#about to read 5, iclass 40, count 2 2006.175.07:42:00.70#ibcon#read 5, iclass 40, count 2 2006.175.07:42:00.70#ibcon#about to read 6, iclass 40, count 2 2006.175.07:42:00.70#ibcon#read 6, iclass 40, count 2 2006.175.07:42:00.70#ibcon#end of sib2, iclass 40, count 2 2006.175.07:42:00.70#ibcon#*mode == 0, iclass 40, count 2 2006.175.07:42:00.70#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.07:42:00.70#ibcon#[27=AT01-04\r\n] 2006.175.07:42:00.70#ibcon#*before write, iclass 40, count 2 2006.175.07:42:00.70#ibcon#enter sib2, iclass 40, count 2 2006.175.07:42:00.70#ibcon#flushed, iclass 40, count 2 2006.175.07:42:00.70#ibcon#about to write, iclass 40, count 2 2006.175.07:42:00.70#ibcon#wrote, iclass 40, count 2 2006.175.07:42:00.70#ibcon#about to read 3, iclass 40, count 2 2006.175.07:42:00.73#ibcon#read 3, iclass 40, count 2 2006.175.07:42:00.73#ibcon#about to read 4, iclass 40, count 2 2006.175.07:42:00.73#ibcon#read 4, iclass 40, count 2 2006.175.07:42:00.73#ibcon#about to read 5, iclass 40, count 2 2006.175.07:42:00.73#ibcon#read 5, iclass 40, count 2 2006.175.07:42:00.73#ibcon#about to read 6, iclass 40, count 2 2006.175.07:42:00.73#ibcon#read 6, iclass 40, count 2 2006.175.07:42:00.73#ibcon#end of sib2, iclass 40, count 2 2006.175.07:42:00.73#ibcon#*after write, iclass 40, count 2 2006.175.07:42:00.73#ibcon#*before return 0, iclass 40, count 2 2006.175.07:42:00.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:42:00.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:42:00.73#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.07:42:00.73#ibcon#ireg 7 cls_cnt 0 2006.175.07:42:00.73#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:42:00.85#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:42:00.85#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:42:00.85#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:42:00.85#ibcon#first serial, iclass 40, count 0 2006.175.07:42:00.85#ibcon#enter sib2, iclass 40, count 0 2006.175.07:42:00.85#ibcon#flushed, iclass 40, count 0 2006.175.07:42:00.85#ibcon#about to write, iclass 40, count 0 2006.175.07:42:00.85#ibcon#wrote, iclass 40, count 0 2006.175.07:42:00.85#ibcon#about to read 3, iclass 40, count 0 2006.175.07:42:00.87#ibcon#read 3, iclass 40, count 0 2006.175.07:42:00.87#ibcon#about to read 4, iclass 40, count 0 2006.175.07:42:00.87#ibcon#read 4, iclass 40, count 0 2006.175.07:42:00.87#ibcon#about to read 5, iclass 40, count 0 2006.175.07:42:00.87#ibcon#read 5, iclass 40, count 0 2006.175.07:42:00.87#ibcon#about to read 6, iclass 40, count 0 2006.175.07:42:00.87#ibcon#read 6, iclass 40, count 0 2006.175.07:42:00.87#ibcon#end of sib2, iclass 40, count 0 2006.175.07:42:00.87#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:42:00.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:42:00.87#ibcon#[27=USB\r\n] 2006.175.07:42:00.87#ibcon#*before write, iclass 40, count 0 2006.175.07:42:00.87#ibcon#enter sib2, iclass 40, count 0 2006.175.07:42:00.87#ibcon#flushed, iclass 40, count 0 2006.175.07:42:00.87#ibcon#about to write, iclass 40, count 0 2006.175.07:42:00.87#ibcon#wrote, iclass 40, count 0 2006.175.07:42:00.87#ibcon#about to read 3, iclass 40, count 0 2006.175.07:42:00.90#ibcon#read 3, iclass 40, count 0 2006.175.07:42:00.90#ibcon#about to read 4, iclass 40, count 0 2006.175.07:42:00.90#ibcon#read 4, iclass 40, count 0 2006.175.07:42:00.90#ibcon#about to read 5, iclass 40, count 0 2006.175.07:42:00.90#ibcon#read 5, iclass 40, count 0 2006.175.07:42:00.90#ibcon#about to read 6, iclass 40, count 0 2006.175.07:42:00.90#ibcon#read 6, iclass 40, count 0 2006.175.07:42:00.90#ibcon#end of sib2, iclass 40, count 0 2006.175.07:42:00.90#ibcon#*after write, iclass 40, count 0 2006.175.07:42:00.90#ibcon#*before return 0, iclass 40, count 0 2006.175.07:42:00.90#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:42:00.90#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:42:00.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:42:00.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:42:00.90$vc4f8/vblo=2,640.99 2006.175.07:42:00.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:42:00.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:42:00.90#ibcon#ireg 17 cls_cnt 0 2006.175.07:42:00.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:42:00.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:42:00.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:42:00.90#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:42:00.90#ibcon#first serial, iclass 4, count 0 2006.175.07:42:00.90#ibcon#enter sib2, iclass 4, count 0 2006.175.07:42:00.90#ibcon#flushed, iclass 4, count 0 2006.175.07:42:00.90#ibcon#about to write, iclass 4, count 0 2006.175.07:42:00.90#ibcon#wrote, iclass 4, count 0 2006.175.07:42:00.90#ibcon#about to read 3, iclass 4, count 0 2006.175.07:42:00.92#ibcon#read 3, iclass 4, count 0 2006.175.07:42:00.92#ibcon#about to read 4, iclass 4, count 0 2006.175.07:42:00.92#ibcon#read 4, iclass 4, count 0 2006.175.07:42:00.92#ibcon#about to read 5, iclass 4, count 0 2006.175.07:42:00.92#ibcon#read 5, iclass 4, count 0 2006.175.07:42:00.92#ibcon#about to read 6, iclass 4, count 0 2006.175.07:42:00.92#ibcon#read 6, iclass 4, count 0 2006.175.07:42:00.92#ibcon#end of sib2, iclass 4, count 0 2006.175.07:42:00.92#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:42:00.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:42:00.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:42:00.92#ibcon#*before write, iclass 4, count 0 2006.175.07:42:00.92#ibcon#enter sib2, iclass 4, count 0 2006.175.07:42:00.92#ibcon#flushed, iclass 4, count 0 2006.175.07:42:00.92#ibcon#about to write, iclass 4, count 0 2006.175.07:42:00.92#ibcon#wrote, iclass 4, count 0 2006.175.07:42:00.92#ibcon#about to read 3, iclass 4, count 0 2006.175.07:42:00.96#ibcon#read 3, iclass 4, count 0 2006.175.07:42:00.96#ibcon#about to read 4, iclass 4, count 0 2006.175.07:42:00.96#ibcon#read 4, iclass 4, count 0 2006.175.07:42:00.96#ibcon#about to read 5, iclass 4, count 0 2006.175.07:42:00.96#ibcon#read 5, iclass 4, count 0 2006.175.07:42:00.96#ibcon#about to read 6, iclass 4, count 0 2006.175.07:42:00.96#ibcon#read 6, iclass 4, count 0 2006.175.07:42:00.96#ibcon#end of sib2, iclass 4, count 0 2006.175.07:42:00.96#ibcon#*after write, iclass 4, count 0 2006.175.07:42:00.96#ibcon#*before return 0, iclass 4, count 0 2006.175.07:42:00.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:42:00.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:42:00.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:42:00.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:42:00.96$vc4f8/vb=2,4 2006.175.07:42:00.96#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.07:42:00.96#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.07:42:00.96#ibcon#ireg 11 cls_cnt 2 2006.175.07:42:00.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:42:01.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:42:01.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:42:01.02#ibcon#enter wrdev, iclass 6, count 2 2006.175.07:42:01.02#ibcon#first serial, iclass 6, count 2 2006.175.07:42:01.02#ibcon#enter sib2, iclass 6, count 2 2006.175.07:42:01.02#ibcon#flushed, iclass 6, count 2 2006.175.07:42:01.02#ibcon#about to write, iclass 6, count 2 2006.175.07:42:01.02#ibcon#wrote, iclass 6, count 2 2006.175.07:42:01.02#ibcon#about to read 3, iclass 6, count 2 2006.175.07:42:01.04#ibcon#read 3, iclass 6, count 2 2006.175.07:42:01.04#ibcon#about to read 4, iclass 6, count 2 2006.175.07:42:01.04#ibcon#read 4, iclass 6, count 2 2006.175.07:42:01.04#ibcon#about to read 5, iclass 6, count 2 2006.175.07:42:01.04#ibcon#read 5, iclass 6, count 2 2006.175.07:42:01.04#ibcon#about to read 6, iclass 6, count 2 2006.175.07:42:01.04#ibcon#read 6, iclass 6, count 2 2006.175.07:42:01.04#ibcon#end of sib2, iclass 6, count 2 2006.175.07:42:01.04#ibcon#*mode == 0, iclass 6, count 2 2006.175.07:42:01.04#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.07:42:01.04#ibcon#[27=AT02-04\r\n] 2006.175.07:42:01.04#ibcon#*before write, iclass 6, count 2 2006.175.07:42:01.04#ibcon#enter sib2, iclass 6, count 2 2006.175.07:42:01.04#ibcon#flushed, iclass 6, count 2 2006.175.07:42:01.04#ibcon#about to write, iclass 6, count 2 2006.175.07:42:01.04#ibcon#wrote, iclass 6, count 2 2006.175.07:42:01.04#ibcon#about to read 3, iclass 6, count 2 2006.175.07:42:01.07#ibcon#read 3, iclass 6, count 2 2006.175.07:42:01.07#ibcon#about to read 4, iclass 6, count 2 2006.175.07:42:01.07#ibcon#read 4, iclass 6, count 2 2006.175.07:42:01.07#ibcon#about to read 5, iclass 6, count 2 2006.175.07:42:01.07#ibcon#read 5, iclass 6, count 2 2006.175.07:42:01.07#ibcon#about to read 6, iclass 6, count 2 2006.175.07:42:01.07#ibcon#read 6, iclass 6, count 2 2006.175.07:42:01.07#ibcon#end of sib2, iclass 6, count 2 2006.175.07:42:01.07#ibcon#*after write, iclass 6, count 2 2006.175.07:42:01.07#ibcon#*before return 0, iclass 6, count 2 2006.175.07:42:01.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:42:01.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:42:01.07#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.07:42:01.07#ibcon#ireg 7 cls_cnt 0 2006.175.07:42:01.07#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:42:01.08#abcon#<5=/05 4.7 7.3 25.92 701007.4\r\n> 2006.175.07:42:01.10#abcon#{5=INTERFACE CLEAR} 2006.175.07:42:01.16#abcon#[5=S1D000X0/0*\r\n] 2006.175.07:42:01.19#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:42:01.19#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:42:01.19#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:42:01.19#ibcon#first serial, iclass 6, count 0 2006.175.07:42:01.19#ibcon#enter sib2, iclass 6, count 0 2006.175.07:42:01.19#ibcon#flushed, iclass 6, count 0 2006.175.07:42:01.19#ibcon#about to write, iclass 6, count 0 2006.175.07:42:01.19#ibcon#wrote, iclass 6, count 0 2006.175.07:42:01.19#ibcon#about to read 3, iclass 6, count 0 2006.175.07:42:01.21#ibcon#read 3, iclass 6, count 0 2006.175.07:42:01.21#ibcon#about to read 4, iclass 6, count 0 2006.175.07:42:01.21#ibcon#read 4, iclass 6, count 0 2006.175.07:42:01.21#ibcon#about to read 5, iclass 6, count 0 2006.175.07:42:01.21#ibcon#read 5, iclass 6, count 0 2006.175.07:42:01.21#ibcon#about to read 6, iclass 6, count 0 2006.175.07:42:01.21#ibcon#read 6, iclass 6, count 0 2006.175.07:42:01.21#ibcon#end of sib2, iclass 6, count 0 2006.175.07:42:01.21#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:42:01.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:42:01.21#ibcon#[27=USB\r\n] 2006.175.07:42:01.21#ibcon#*before write, iclass 6, count 0 2006.175.07:42:01.21#ibcon#enter sib2, iclass 6, count 0 2006.175.07:42:01.21#ibcon#flushed, iclass 6, count 0 2006.175.07:42:01.21#ibcon#about to write, iclass 6, count 0 2006.175.07:42:01.21#ibcon#wrote, iclass 6, count 0 2006.175.07:42:01.21#ibcon#about to read 3, iclass 6, count 0 2006.175.07:42:01.24#ibcon#read 3, iclass 6, count 0 2006.175.07:42:01.24#ibcon#about to read 4, iclass 6, count 0 2006.175.07:42:01.24#ibcon#read 4, iclass 6, count 0 2006.175.07:42:01.24#ibcon#about to read 5, iclass 6, count 0 2006.175.07:42:01.24#ibcon#read 5, iclass 6, count 0 2006.175.07:42:01.24#ibcon#about to read 6, iclass 6, count 0 2006.175.07:42:01.24#ibcon#read 6, iclass 6, count 0 2006.175.07:42:01.24#ibcon#end of sib2, iclass 6, count 0 2006.175.07:42:01.24#ibcon#*after write, iclass 6, count 0 2006.175.07:42:01.24#ibcon#*before return 0, iclass 6, count 0 2006.175.07:42:01.24#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:42:01.24#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:42:01.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:42:01.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:42:01.24$vc4f8/vblo=3,656.99 2006.175.07:42:01.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.07:42:01.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.07:42:01.24#ibcon#ireg 17 cls_cnt 0 2006.175.07:42:01.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:42:01.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:42:01.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:42:01.24#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:42:01.24#ibcon#first serial, iclass 14, count 0 2006.175.07:42:01.24#ibcon#enter sib2, iclass 14, count 0 2006.175.07:42:01.24#ibcon#flushed, iclass 14, count 0 2006.175.07:42:01.24#ibcon#about to write, iclass 14, count 0 2006.175.07:42:01.24#ibcon#wrote, iclass 14, count 0 2006.175.07:42:01.24#ibcon#about to read 3, iclass 14, count 0 2006.175.07:42:01.26#ibcon#read 3, iclass 14, count 0 2006.175.07:42:01.26#ibcon#about to read 4, iclass 14, count 0 2006.175.07:42:01.26#ibcon#read 4, iclass 14, count 0 2006.175.07:42:01.26#ibcon#about to read 5, iclass 14, count 0 2006.175.07:42:01.26#ibcon#read 5, iclass 14, count 0 2006.175.07:42:01.26#ibcon#about to read 6, iclass 14, count 0 2006.175.07:42:01.26#ibcon#read 6, iclass 14, count 0 2006.175.07:42:01.26#ibcon#end of sib2, iclass 14, count 0 2006.175.07:42:01.26#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:42:01.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:42:01.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:42:01.26#ibcon#*before write, iclass 14, count 0 2006.175.07:42:01.26#ibcon#enter sib2, iclass 14, count 0 2006.175.07:42:01.26#ibcon#flushed, iclass 14, count 0 2006.175.07:42:01.26#ibcon#about to write, iclass 14, count 0 2006.175.07:42:01.26#ibcon#wrote, iclass 14, count 0 2006.175.07:42:01.26#ibcon#about to read 3, iclass 14, count 0 2006.175.07:42:01.30#ibcon#read 3, iclass 14, count 0 2006.175.07:42:01.30#ibcon#about to read 4, iclass 14, count 0 2006.175.07:42:01.30#ibcon#read 4, iclass 14, count 0 2006.175.07:42:01.30#ibcon#about to read 5, iclass 14, count 0 2006.175.07:42:01.30#ibcon#read 5, iclass 14, count 0 2006.175.07:42:01.30#ibcon#about to read 6, iclass 14, count 0 2006.175.07:42:01.30#ibcon#read 6, iclass 14, count 0 2006.175.07:42:01.30#ibcon#end of sib2, iclass 14, count 0 2006.175.07:42:01.30#ibcon#*after write, iclass 14, count 0 2006.175.07:42:01.30#ibcon#*before return 0, iclass 14, count 0 2006.175.07:42:01.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:42:01.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:42:01.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:42:01.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:42:01.30$vc4f8/vb=3,4 2006.175.07:42:01.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.07:42:01.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.07:42:01.30#ibcon#ireg 11 cls_cnt 2 2006.175.07:42:01.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:42:01.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:42:01.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:42:01.36#ibcon#enter wrdev, iclass 16, count 2 2006.175.07:42:01.36#ibcon#first serial, iclass 16, count 2 2006.175.07:42:01.36#ibcon#enter sib2, iclass 16, count 2 2006.175.07:42:01.36#ibcon#flushed, iclass 16, count 2 2006.175.07:42:01.36#ibcon#about to write, iclass 16, count 2 2006.175.07:42:01.36#ibcon#wrote, iclass 16, count 2 2006.175.07:42:01.36#ibcon#about to read 3, iclass 16, count 2 2006.175.07:42:01.38#ibcon#read 3, iclass 16, count 2 2006.175.07:42:01.38#ibcon#about to read 4, iclass 16, count 2 2006.175.07:42:01.38#ibcon#read 4, iclass 16, count 2 2006.175.07:42:01.38#ibcon#about to read 5, iclass 16, count 2 2006.175.07:42:01.38#ibcon#read 5, iclass 16, count 2 2006.175.07:42:01.38#ibcon#about to read 6, iclass 16, count 2 2006.175.07:42:01.38#ibcon#read 6, iclass 16, count 2 2006.175.07:42:01.38#ibcon#end of sib2, iclass 16, count 2 2006.175.07:42:01.38#ibcon#*mode == 0, iclass 16, count 2 2006.175.07:42:01.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.07:42:01.38#ibcon#[27=AT03-04\r\n] 2006.175.07:42:01.38#ibcon#*before write, iclass 16, count 2 2006.175.07:42:01.38#ibcon#enter sib2, iclass 16, count 2 2006.175.07:42:01.38#ibcon#flushed, iclass 16, count 2 2006.175.07:42:01.38#ibcon#about to write, iclass 16, count 2 2006.175.07:42:01.38#ibcon#wrote, iclass 16, count 2 2006.175.07:42:01.38#ibcon#about to read 3, iclass 16, count 2 2006.175.07:42:01.41#ibcon#read 3, iclass 16, count 2 2006.175.07:42:01.41#ibcon#about to read 4, iclass 16, count 2 2006.175.07:42:01.41#ibcon#read 4, iclass 16, count 2 2006.175.07:42:01.41#ibcon#about to read 5, iclass 16, count 2 2006.175.07:42:01.41#ibcon#read 5, iclass 16, count 2 2006.175.07:42:01.41#ibcon#about to read 6, iclass 16, count 2 2006.175.07:42:01.41#ibcon#read 6, iclass 16, count 2 2006.175.07:42:01.41#ibcon#end of sib2, iclass 16, count 2 2006.175.07:42:01.41#ibcon#*after write, iclass 16, count 2 2006.175.07:42:01.41#ibcon#*before return 0, iclass 16, count 2 2006.175.07:42:01.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:42:01.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:42:01.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.07:42:01.41#ibcon#ireg 7 cls_cnt 0 2006.175.07:42:01.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:42:01.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:42:01.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:42:01.53#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:42:01.53#ibcon#first serial, iclass 16, count 0 2006.175.07:42:01.53#ibcon#enter sib2, iclass 16, count 0 2006.175.07:42:01.53#ibcon#flushed, iclass 16, count 0 2006.175.07:42:01.53#ibcon#about to write, iclass 16, count 0 2006.175.07:42:01.53#ibcon#wrote, iclass 16, count 0 2006.175.07:42:01.53#ibcon#about to read 3, iclass 16, count 0 2006.175.07:42:01.55#ibcon#read 3, iclass 16, count 0 2006.175.07:42:01.55#ibcon#about to read 4, iclass 16, count 0 2006.175.07:42:01.55#ibcon#read 4, iclass 16, count 0 2006.175.07:42:01.55#ibcon#about to read 5, iclass 16, count 0 2006.175.07:42:01.55#ibcon#read 5, iclass 16, count 0 2006.175.07:42:01.55#ibcon#about to read 6, iclass 16, count 0 2006.175.07:42:01.55#ibcon#read 6, iclass 16, count 0 2006.175.07:42:01.55#ibcon#end of sib2, iclass 16, count 0 2006.175.07:42:01.55#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:42:01.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:42:01.55#ibcon#[27=USB\r\n] 2006.175.07:42:01.55#ibcon#*before write, iclass 16, count 0 2006.175.07:42:01.55#ibcon#enter sib2, iclass 16, count 0 2006.175.07:42:01.55#ibcon#flushed, iclass 16, count 0 2006.175.07:42:01.55#ibcon#about to write, iclass 16, count 0 2006.175.07:42:01.55#ibcon#wrote, iclass 16, count 0 2006.175.07:42:01.55#ibcon#about to read 3, iclass 16, count 0 2006.175.07:42:01.58#ibcon#read 3, iclass 16, count 0 2006.175.07:42:01.58#ibcon#about to read 4, iclass 16, count 0 2006.175.07:42:01.58#ibcon#read 4, iclass 16, count 0 2006.175.07:42:01.58#ibcon#about to read 5, iclass 16, count 0 2006.175.07:42:01.58#ibcon#read 5, iclass 16, count 0 2006.175.07:42:01.58#ibcon#about to read 6, iclass 16, count 0 2006.175.07:42:01.58#ibcon#read 6, iclass 16, count 0 2006.175.07:42:01.58#ibcon#end of sib2, iclass 16, count 0 2006.175.07:42:01.58#ibcon#*after write, iclass 16, count 0 2006.175.07:42:01.58#ibcon#*before return 0, iclass 16, count 0 2006.175.07:42:01.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:42:01.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:42:01.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:42:01.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:42:01.58$vc4f8/vblo=4,712.99 2006.175.07:42:01.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.07:42:01.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.07:42:01.58#ibcon#ireg 17 cls_cnt 0 2006.175.07:42:01.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:42:01.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:42:01.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:42:01.58#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:42:01.58#ibcon#first serial, iclass 18, count 0 2006.175.07:42:01.58#ibcon#enter sib2, iclass 18, count 0 2006.175.07:42:01.58#ibcon#flushed, iclass 18, count 0 2006.175.07:42:01.58#ibcon#about to write, iclass 18, count 0 2006.175.07:42:01.58#ibcon#wrote, iclass 18, count 0 2006.175.07:42:01.58#ibcon#about to read 3, iclass 18, count 0 2006.175.07:42:01.60#ibcon#read 3, iclass 18, count 0 2006.175.07:42:01.60#ibcon#about to read 4, iclass 18, count 0 2006.175.07:42:01.60#ibcon#read 4, iclass 18, count 0 2006.175.07:42:01.60#ibcon#about to read 5, iclass 18, count 0 2006.175.07:42:01.60#ibcon#read 5, iclass 18, count 0 2006.175.07:42:01.60#ibcon#about to read 6, iclass 18, count 0 2006.175.07:42:01.60#ibcon#read 6, iclass 18, count 0 2006.175.07:42:01.60#ibcon#end of sib2, iclass 18, count 0 2006.175.07:42:01.60#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:42:01.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:42:01.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:42:01.60#ibcon#*before write, iclass 18, count 0 2006.175.07:42:01.60#ibcon#enter sib2, iclass 18, count 0 2006.175.07:42:01.60#ibcon#flushed, iclass 18, count 0 2006.175.07:42:01.60#ibcon#about to write, iclass 18, count 0 2006.175.07:42:01.60#ibcon#wrote, iclass 18, count 0 2006.175.07:42:01.60#ibcon#about to read 3, iclass 18, count 0 2006.175.07:42:01.64#ibcon#read 3, iclass 18, count 0 2006.175.07:42:01.64#ibcon#about to read 4, iclass 18, count 0 2006.175.07:42:01.64#ibcon#read 4, iclass 18, count 0 2006.175.07:42:01.64#ibcon#about to read 5, iclass 18, count 0 2006.175.07:42:01.64#ibcon#read 5, iclass 18, count 0 2006.175.07:42:01.64#ibcon#about to read 6, iclass 18, count 0 2006.175.07:42:01.64#ibcon#read 6, iclass 18, count 0 2006.175.07:42:01.64#ibcon#end of sib2, iclass 18, count 0 2006.175.07:42:01.64#ibcon#*after write, iclass 18, count 0 2006.175.07:42:01.64#ibcon#*before return 0, iclass 18, count 0 2006.175.07:42:01.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:42:01.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:42:01.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:42:01.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:42:01.64$vc4f8/vb=4,4 2006.175.07:42:01.64#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.175.07:42:01.64#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.175.07:42:01.64#ibcon#ireg 11 cls_cnt 2 2006.175.07:42:01.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:42:01.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:42:01.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:42:01.70#ibcon#enter wrdev, iclass 20, count 2 2006.175.07:42:01.70#ibcon#first serial, iclass 20, count 2 2006.175.07:42:01.70#ibcon#enter sib2, iclass 20, count 2 2006.175.07:42:01.70#ibcon#flushed, iclass 20, count 2 2006.175.07:42:01.70#ibcon#about to write, iclass 20, count 2 2006.175.07:42:01.70#ibcon#wrote, iclass 20, count 2 2006.175.07:42:01.70#ibcon#about to read 3, iclass 20, count 2 2006.175.07:42:01.72#ibcon#read 3, iclass 20, count 2 2006.175.07:42:01.72#ibcon#about to read 4, iclass 20, count 2 2006.175.07:42:01.72#ibcon#read 4, iclass 20, count 2 2006.175.07:42:01.72#ibcon#about to read 5, iclass 20, count 2 2006.175.07:42:01.72#ibcon#read 5, iclass 20, count 2 2006.175.07:42:01.72#ibcon#about to read 6, iclass 20, count 2 2006.175.07:42:01.72#ibcon#read 6, iclass 20, count 2 2006.175.07:42:01.72#ibcon#end of sib2, iclass 20, count 2 2006.175.07:42:01.72#ibcon#*mode == 0, iclass 20, count 2 2006.175.07:42:01.72#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.175.07:42:01.72#ibcon#[27=AT04-04\r\n] 2006.175.07:42:01.72#ibcon#*before write, iclass 20, count 2 2006.175.07:42:01.72#ibcon#enter sib2, iclass 20, count 2 2006.175.07:42:01.72#ibcon#flushed, iclass 20, count 2 2006.175.07:42:01.72#ibcon#about to write, iclass 20, count 2 2006.175.07:42:01.72#ibcon#wrote, iclass 20, count 2 2006.175.07:42:01.72#ibcon#about to read 3, iclass 20, count 2 2006.175.07:42:01.75#ibcon#read 3, iclass 20, count 2 2006.175.07:42:01.75#ibcon#about to read 4, iclass 20, count 2 2006.175.07:42:01.75#ibcon#read 4, iclass 20, count 2 2006.175.07:42:01.75#ibcon#about to read 5, iclass 20, count 2 2006.175.07:42:01.75#ibcon#read 5, iclass 20, count 2 2006.175.07:42:01.75#ibcon#about to read 6, iclass 20, count 2 2006.175.07:42:01.75#ibcon#read 6, iclass 20, count 2 2006.175.07:42:01.75#ibcon#end of sib2, iclass 20, count 2 2006.175.07:42:01.75#ibcon#*after write, iclass 20, count 2 2006.175.07:42:01.75#ibcon#*before return 0, iclass 20, count 2 2006.175.07:42:01.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:42:01.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:42:01.75#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.175.07:42:01.75#ibcon#ireg 7 cls_cnt 0 2006.175.07:42:01.75#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:42:01.87#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:42:01.87#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:42:01.87#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:42:01.87#ibcon#first serial, iclass 20, count 0 2006.175.07:42:01.87#ibcon#enter sib2, iclass 20, count 0 2006.175.07:42:01.87#ibcon#flushed, iclass 20, count 0 2006.175.07:42:01.87#ibcon#about to write, iclass 20, count 0 2006.175.07:42:01.87#ibcon#wrote, iclass 20, count 0 2006.175.07:42:01.87#ibcon#about to read 3, iclass 20, count 0 2006.175.07:42:01.89#ibcon#read 3, iclass 20, count 0 2006.175.07:42:01.89#ibcon#about to read 4, iclass 20, count 0 2006.175.07:42:01.89#ibcon#read 4, iclass 20, count 0 2006.175.07:42:01.89#ibcon#about to read 5, iclass 20, count 0 2006.175.07:42:01.89#ibcon#read 5, iclass 20, count 0 2006.175.07:42:01.89#ibcon#about to read 6, iclass 20, count 0 2006.175.07:42:01.89#ibcon#read 6, iclass 20, count 0 2006.175.07:42:01.89#ibcon#end of sib2, iclass 20, count 0 2006.175.07:42:01.89#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:42:01.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:42:01.89#ibcon#[27=USB\r\n] 2006.175.07:42:01.89#ibcon#*before write, iclass 20, count 0 2006.175.07:42:01.89#ibcon#enter sib2, iclass 20, count 0 2006.175.07:42:01.89#ibcon#flushed, iclass 20, count 0 2006.175.07:42:01.89#ibcon#about to write, iclass 20, count 0 2006.175.07:42:01.89#ibcon#wrote, iclass 20, count 0 2006.175.07:42:01.89#ibcon#about to read 3, iclass 20, count 0 2006.175.07:42:01.92#ibcon#read 3, iclass 20, count 0 2006.175.07:42:01.92#ibcon#about to read 4, iclass 20, count 0 2006.175.07:42:01.92#ibcon#read 4, iclass 20, count 0 2006.175.07:42:01.92#ibcon#about to read 5, iclass 20, count 0 2006.175.07:42:01.92#ibcon#read 5, iclass 20, count 0 2006.175.07:42:01.92#ibcon#about to read 6, iclass 20, count 0 2006.175.07:42:01.92#ibcon#read 6, iclass 20, count 0 2006.175.07:42:01.92#ibcon#end of sib2, iclass 20, count 0 2006.175.07:42:01.92#ibcon#*after write, iclass 20, count 0 2006.175.07:42:01.92#ibcon#*before return 0, iclass 20, count 0 2006.175.07:42:01.92#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:42:01.92#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:42:01.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:42:01.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:42:01.92$vc4f8/vblo=5,744.99 2006.175.07:42:01.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.07:42:01.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.07:42:01.92#ibcon#ireg 17 cls_cnt 0 2006.175.07:42:01.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:42:01.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:42:01.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:42:01.92#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:42:01.92#ibcon#first serial, iclass 22, count 0 2006.175.07:42:01.92#ibcon#enter sib2, iclass 22, count 0 2006.175.07:42:01.92#ibcon#flushed, iclass 22, count 0 2006.175.07:42:01.92#ibcon#about to write, iclass 22, count 0 2006.175.07:42:01.92#ibcon#wrote, iclass 22, count 0 2006.175.07:42:01.92#ibcon#about to read 3, iclass 22, count 0 2006.175.07:42:01.94#ibcon#read 3, iclass 22, count 0 2006.175.07:42:01.94#ibcon#about to read 4, iclass 22, count 0 2006.175.07:42:01.94#ibcon#read 4, iclass 22, count 0 2006.175.07:42:01.94#ibcon#about to read 5, iclass 22, count 0 2006.175.07:42:01.94#ibcon#read 5, iclass 22, count 0 2006.175.07:42:01.94#ibcon#about to read 6, iclass 22, count 0 2006.175.07:42:01.94#ibcon#read 6, iclass 22, count 0 2006.175.07:42:01.94#ibcon#end of sib2, iclass 22, count 0 2006.175.07:42:01.94#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:42:01.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:42:01.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:42:01.94#ibcon#*before write, iclass 22, count 0 2006.175.07:42:01.94#ibcon#enter sib2, iclass 22, count 0 2006.175.07:42:01.94#ibcon#flushed, iclass 22, count 0 2006.175.07:42:01.94#ibcon#about to write, iclass 22, count 0 2006.175.07:42:01.94#ibcon#wrote, iclass 22, count 0 2006.175.07:42:01.94#ibcon#about to read 3, iclass 22, count 0 2006.175.07:42:01.98#ibcon#read 3, iclass 22, count 0 2006.175.07:42:01.98#ibcon#about to read 4, iclass 22, count 0 2006.175.07:42:01.98#ibcon#read 4, iclass 22, count 0 2006.175.07:42:01.98#ibcon#about to read 5, iclass 22, count 0 2006.175.07:42:01.98#ibcon#read 5, iclass 22, count 0 2006.175.07:42:01.98#ibcon#about to read 6, iclass 22, count 0 2006.175.07:42:01.98#ibcon#read 6, iclass 22, count 0 2006.175.07:42:01.98#ibcon#end of sib2, iclass 22, count 0 2006.175.07:42:01.98#ibcon#*after write, iclass 22, count 0 2006.175.07:42:01.98#ibcon#*before return 0, iclass 22, count 0 2006.175.07:42:01.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:42:01.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:42:01.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:42:01.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:42:01.98$vc4f8/vb=5,4 2006.175.07:42:01.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.07:42:01.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.07:42:01.98#ibcon#ireg 11 cls_cnt 2 2006.175.07:42:01.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:42:02.04#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:42:02.04#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:42:02.04#ibcon#enter wrdev, iclass 24, count 2 2006.175.07:42:02.04#ibcon#first serial, iclass 24, count 2 2006.175.07:42:02.04#ibcon#enter sib2, iclass 24, count 2 2006.175.07:42:02.04#ibcon#flushed, iclass 24, count 2 2006.175.07:42:02.04#ibcon#about to write, iclass 24, count 2 2006.175.07:42:02.04#ibcon#wrote, iclass 24, count 2 2006.175.07:42:02.04#ibcon#about to read 3, iclass 24, count 2 2006.175.07:42:02.06#ibcon#read 3, iclass 24, count 2 2006.175.07:42:02.06#ibcon#about to read 4, iclass 24, count 2 2006.175.07:42:02.06#ibcon#read 4, iclass 24, count 2 2006.175.07:42:02.06#ibcon#about to read 5, iclass 24, count 2 2006.175.07:42:02.06#ibcon#read 5, iclass 24, count 2 2006.175.07:42:02.06#ibcon#about to read 6, iclass 24, count 2 2006.175.07:42:02.06#ibcon#read 6, iclass 24, count 2 2006.175.07:42:02.06#ibcon#end of sib2, iclass 24, count 2 2006.175.07:42:02.06#ibcon#*mode == 0, iclass 24, count 2 2006.175.07:42:02.06#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.07:42:02.06#ibcon#[27=AT05-04\r\n] 2006.175.07:42:02.06#ibcon#*before write, iclass 24, count 2 2006.175.07:42:02.06#ibcon#enter sib2, iclass 24, count 2 2006.175.07:42:02.06#ibcon#flushed, iclass 24, count 2 2006.175.07:42:02.06#ibcon#about to write, iclass 24, count 2 2006.175.07:42:02.06#ibcon#wrote, iclass 24, count 2 2006.175.07:42:02.06#ibcon#about to read 3, iclass 24, count 2 2006.175.07:42:02.09#ibcon#read 3, iclass 24, count 2 2006.175.07:42:02.09#ibcon#about to read 4, iclass 24, count 2 2006.175.07:42:02.09#ibcon#read 4, iclass 24, count 2 2006.175.07:42:02.09#ibcon#about to read 5, iclass 24, count 2 2006.175.07:42:02.09#ibcon#read 5, iclass 24, count 2 2006.175.07:42:02.09#ibcon#about to read 6, iclass 24, count 2 2006.175.07:42:02.09#ibcon#read 6, iclass 24, count 2 2006.175.07:42:02.09#ibcon#end of sib2, iclass 24, count 2 2006.175.07:42:02.09#ibcon#*after write, iclass 24, count 2 2006.175.07:42:02.09#ibcon#*before return 0, iclass 24, count 2 2006.175.07:42:02.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:42:02.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:42:02.09#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.07:42:02.09#ibcon#ireg 7 cls_cnt 0 2006.175.07:42:02.09#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:42:02.21#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:42:02.21#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:42:02.21#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:42:02.21#ibcon#first serial, iclass 24, count 0 2006.175.07:42:02.21#ibcon#enter sib2, iclass 24, count 0 2006.175.07:42:02.21#ibcon#flushed, iclass 24, count 0 2006.175.07:42:02.21#ibcon#about to write, iclass 24, count 0 2006.175.07:42:02.21#ibcon#wrote, iclass 24, count 0 2006.175.07:42:02.21#ibcon#about to read 3, iclass 24, count 0 2006.175.07:42:02.23#ibcon#read 3, iclass 24, count 0 2006.175.07:42:02.23#ibcon#about to read 4, iclass 24, count 0 2006.175.07:42:02.23#ibcon#read 4, iclass 24, count 0 2006.175.07:42:02.23#ibcon#about to read 5, iclass 24, count 0 2006.175.07:42:02.23#ibcon#read 5, iclass 24, count 0 2006.175.07:42:02.23#ibcon#about to read 6, iclass 24, count 0 2006.175.07:42:02.23#ibcon#read 6, iclass 24, count 0 2006.175.07:42:02.23#ibcon#end of sib2, iclass 24, count 0 2006.175.07:42:02.23#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:42:02.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:42:02.23#ibcon#[27=USB\r\n] 2006.175.07:42:02.23#ibcon#*before write, iclass 24, count 0 2006.175.07:42:02.23#ibcon#enter sib2, iclass 24, count 0 2006.175.07:42:02.23#ibcon#flushed, iclass 24, count 0 2006.175.07:42:02.23#ibcon#about to write, iclass 24, count 0 2006.175.07:42:02.23#ibcon#wrote, iclass 24, count 0 2006.175.07:42:02.23#ibcon#about to read 3, iclass 24, count 0 2006.175.07:42:02.26#ibcon#read 3, iclass 24, count 0 2006.175.07:42:02.26#ibcon#about to read 4, iclass 24, count 0 2006.175.07:42:02.26#ibcon#read 4, iclass 24, count 0 2006.175.07:42:02.26#ibcon#about to read 5, iclass 24, count 0 2006.175.07:42:02.26#ibcon#read 5, iclass 24, count 0 2006.175.07:42:02.26#ibcon#about to read 6, iclass 24, count 0 2006.175.07:42:02.26#ibcon#read 6, iclass 24, count 0 2006.175.07:42:02.26#ibcon#end of sib2, iclass 24, count 0 2006.175.07:42:02.26#ibcon#*after write, iclass 24, count 0 2006.175.07:42:02.26#ibcon#*before return 0, iclass 24, count 0 2006.175.07:42:02.26#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:42:02.26#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:42:02.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:42:02.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:42:02.26$vc4f8/vblo=6,752.99 2006.175.07:42:02.26#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.07:42:02.26#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.07:42:02.26#ibcon#ireg 17 cls_cnt 0 2006.175.07:42:02.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:42:02.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:42:02.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:42:02.26#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:42:02.26#ibcon#first serial, iclass 26, count 0 2006.175.07:42:02.26#ibcon#enter sib2, iclass 26, count 0 2006.175.07:42:02.26#ibcon#flushed, iclass 26, count 0 2006.175.07:42:02.26#ibcon#about to write, iclass 26, count 0 2006.175.07:42:02.26#ibcon#wrote, iclass 26, count 0 2006.175.07:42:02.26#ibcon#about to read 3, iclass 26, count 0 2006.175.07:42:02.28#ibcon#read 3, iclass 26, count 0 2006.175.07:42:02.28#ibcon#about to read 4, iclass 26, count 0 2006.175.07:42:02.28#ibcon#read 4, iclass 26, count 0 2006.175.07:42:02.28#ibcon#about to read 5, iclass 26, count 0 2006.175.07:42:02.28#ibcon#read 5, iclass 26, count 0 2006.175.07:42:02.28#ibcon#about to read 6, iclass 26, count 0 2006.175.07:42:02.28#ibcon#read 6, iclass 26, count 0 2006.175.07:42:02.28#ibcon#end of sib2, iclass 26, count 0 2006.175.07:42:02.28#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:42:02.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:42:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:42:02.28#ibcon#*before write, iclass 26, count 0 2006.175.07:42:02.28#ibcon#enter sib2, iclass 26, count 0 2006.175.07:42:02.28#ibcon#flushed, iclass 26, count 0 2006.175.07:42:02.28#ibcon#about to write, iclass 26, count 0 2006.175.07:42:02.28#ibcon#wrote, iclass 26, count 0 2006.175.07:42:02.28#ibcon#about to read 3, iclass 26, count 0 2006.175.07:42:02.32#ibcon#read 3, iclass 26, count 0 2006.175.07:42:02.32#ibcon#about to read 4, iclass 26, count 0 2006.175.07:42:02.32#ibcon#read 4, iclass 26, count 0 2006.175.07:42:02.32#ibcon#about to read 5, iclass 26, count 0 2006.175.07:42:02.32#ibcon#read 5, iclass 26, count 0 2006.175.07:42:02.32#ibcon#about to read 6, iclass 26, count 0 2006.175.07:42:02.32#ibcon#read 6, iclass 26, count 0 2006.175.07:42:02.32#ibcon#end of sib2, iclass 26, count 0 2006.175.07:42:02.32#ibcon#*after write, iclass 26, count 0 2006.175.07:42:02.32#ibcon#*before return 0, iclass 26, count 0 2006.175.07:42:02.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:42:02.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:42:02.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:42:02.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:42:02.32$vc4f8/vb=6,4 2006.175.07:42:02.32#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.07:42:02.32#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.07:42:02.32#ibcon#ireg 11 cls_cnt 2 2006.175.07:42:02.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:42:02.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:42:02.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:42:02.38#ibcon#enter wrdev, iclass 28, count 2 2006.175.07:42:02.38#ibcon#first serial, iclass 28, count 2 2006.175.07:42:02.38#ibcon#enter sib2, iclass 28, count 2 2006.175.07:42:02.38#ibcon#flushed, iclass 28, count 2 2006.175.07:42:02.38#ibcon#about to write, iclass 28, count 2 2006.175.07:42:02.38#ibcon#wrote, iclass 28, count 2 2006.175.07:42:02.38#ibcon#about to read 3, iclass 28, count 2 2006.175.07:42:02.40#ibcon#read 3, iclass 28, count 2 2006.175.07:42:02.40#ibcon#about to read 4, iclass 28, count 2 2006.175.07:42:02.40#ibcon#read 4, iclass 28, count 2 2006.175.07:42:02.40#ibcon#about to read 5, iclass 28, count 2 2006.175.07:42:02.40#ibcon#read 5, iclass 28, count 2 2006.175.07:42:02.40#ibcon#about to read 6, iclass 28, count 2 2006.175.07:42:02.40#ibcon#read 6, iclass 28, count 2 2006.175.07:42:02.40#ibcon#end of sib2, iclass 28, count 2 2006.175.07:42:02.40#ibcon#*mode == 0, iclass 28, count 2 2006.175.07:42:02.40#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.07:42:02.40#ibcon#[27=AT06-04\r\n] 2006.175.07:42:02.40#ibcon#*before write, iclass 28, count 2 2006.175.07:42:02.40#ibcon#enter sib2, iclass 28, count 2 2006.175.07:42:02.40#ibcon#flushed, iclass 28, count 2 2006.175.07:42:02.40#ibcon#about to write, iclass 28, count 2 2006.175.07:42:02.40#ibcon#wrote, iclass 28, count 2 2006.175.07:42:02.40#ibcon#about to read 3, iclass 28, count 2 2006.175.07:42:02.43#ibcon#read 3, iclass 28, count 2 2006.175.07:42:02.43#ibcon#about to read 4, iclass 28, count 2 2006.175.07:42:02.43#ibcon#read 4, iclass 28, count 2 2006.175.07:42:02.43#ibcon#about to read 5, iclass 28, count 2 2006.175.07:42:02.43#ibcon#read 5, iclass 28, count 2 2006.175.07:42:02.43#ibcon#about to read 6, iclass 28, count 2 2006.175.07:42:02.43#ibcon#read 6, iclass 28, count 2 2006.175.07:42:02.43#ibcon#end of sib2, iclass 28, count 2 2006.175.07:42:02.43#ibcon#*after write, iclass 28, count 2 2006.175.07:42:02.43#ibcon#*before return 0, iclass 28, count 2 2006.175.07:42:02.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:42:02.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:42:02.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.07:42:02.43#ibcon#ireg 7 cls_cnt 0 2006.175.07:42:02.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:42:02.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:42:02.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:42:02.55#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:42:02.55#ibcon#first serial, iclass 28, count 0 2006.175.07:42:02.55#ibcon#enter sib2, iclass 28, count 0 2006.175.07:42:02.55#ibcon#flushed, iclass 28, count 0 2006.175.07:42:02.55#ibcon#about to write, iclass 28, count 0 2006.175.07:42:02.55#ibcon#wrote, iclass 28, count 0 2006.175.07:42:02.55#ibcon#about to read 3, iclass 28, count 0 2006.175.07:42:02.57#ibcon#read 3, iclass 28, count 0 2006.175.07:42:02.57#ibcon#about to read 4, iclass 28, count 0 2006.175.07:42:02.57#ibcon#read 4, iclass 28, count 0 2006.175.07:42:02.57#ibcon#about to read 5, iclass 28, count 0 2006.175.07:42:02.57#ibcon#read 5, iclass 28, count 0 2006.175.07:42:02.57#ibcon#about to read 6, iclass 28, count 0 2006.175.07:42:02.57#ibcon#read 6, iclass 28, count 0 2006.175.07:42:02.57#ibcon#end of sib2, iclass 28, count 0 2006.175.07:42:02.57#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:42:02.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:42:02.57#ibcon#[27=USB\r\n] 2006.175.07:42:02.57#ibcon#*before write, iclass 28, count 0 2006.175.07:42:02.57#ibcon#enter sib2, iclass 28, count 0 2006.175.07:42:02.57#ibcon#flushed, iclass 28, count 0 2006.175.07:42:02.57#ibcon#about to write, iclass 28, count 0 2006.175.07:42:02.57#ibcon#wrote, iclass 28, count 0 2006.175.07:42:02.57#ibcon#about to read 3, iclass 28, count 0 2006.175.07:42:02.60#ibcon#read 3, iclass 28, count 0 2006.175.07:42:02.60#ibcon#about to read 4, iclass 28, count 0 2006.175.07:42:02.60#ibcon#read 4, iclass 28, count 0 2006.175.07:42:02.60#ibcon#about to read 5, iclass 28, count 0 2006.175.07:42:02.60#ibcon#read 5, iclass 28, count 0 2006.175.07:42:02.60#ibcon#about to read 6, iclass 28, count 0 2006.175.07:42:02.60#ibcon#read 6, iclass 28, count 0 2006.175.07:42:02.60#ibcon#end of sib2, iclass 28, count 0 2006.175.07:42:02.60#ibcon#*after write, iclass 28, count 0 2006.175.07:42:02.60#ibcon#*before return 0, iclass 28, count 0 2006.175.07:42:02.60#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:42:02.60#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:42:02.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:42:02.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:42:02.60$vc4f8/vabw=wide 2006.175.07:42:02.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.07:42:02.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.07:42:02.60#ibcon#ireg 8 cls_cnt 0 2006.175.07:42:02.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:42:02.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:42:02.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:42:02.60#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:42:02.60#ibcon#first serial, iclass 30, count 0 2006.175.07:42:02.60#ibcon#enter sib2, iclass 30, count 0 2006.175.07:42:02.60#ibcon#flushed, iclass 30, count 0 2006.175.07:42:02.60#ibcon#about to write, iclass 30, count 0 2006.175.07:42:02.60#ibcon#wrote, iclass 30, count 0 2006.175.07:42:02.60#ibcon#about to read 3, iclass 30, count 0 2006.175.07:42:02.62#ibcon#read 3, iclass 30, count 0 2006.175.07:42:02.62#ibcon#about to read 4, iclass 30, count 0 2006.175.07:42:02.62#ibcon#read 4, iclass 30, count 0 2006.175.07:42:02.62#ibcon#about to read 5, iclass 30, count 0 2006.175.07:42:02.62#ibcon#read 5, iclass 30, count 0 2006.175.07:42:02.62#ibcon#about to read 6, iclass 30, count 0 2006.175.07:42:02.62#ibcon#read 6, iclass 30, count 0 2006.175.07:42:02.62#ibcon#end of sib2, iclass 30, count 0 2006.175.07:42:02.62#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:42:02.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:42:02.62#ibcon#[25=BW32\r\n] 2006.175.07:42:02.62#ibcon#*before write, iclass 30, count 0 2006.175.07:42:02.62#ibcon#enter sib2, iclass 30, count 0 2006.175.07:42:02.62#ibcon#flushed, iclass 30, count 0 2006.175.07:42:02.62#ibcon#about to write, iclass 30, count 0 2006.175.07:42:02.62#ibcon#wrote, iclass 30, count 0 2006.175.07:42:02.62#ibcon#about to read 3, iclass 30, count 0 2006.175.07:42:02.65#ibcon#read 3, iclass 30, count 0 2006.175.07:42:02.65#ibcon#about to read 4, iclass 30, count 0 2006.175.07:42:02.65#ibcon#read 4, iclass 30, count 0 2006.175.07:42:02.65#ibcon#about to read 5, iclass 30, count 0 2006.175.07:42:02.65#ibcon#read 5, iclass 30, count 0 2006.175.07:42:02.65#ibcon#about to read 6, iclass 30, count 0 2006.175.07:42:02.65#ibcon#read 6, iclass 30, count 0 2006.175.07:42:02.65#ibcon#end of sib2, iclass 30, count 0 2006.175.07:42:02.65#ibcon#*after write, iclass 30, count 0 2006.175.07:42:02.65#ibcon#*before return 0, iclass 30, count 0 2006.175.07:42:02.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:42:02.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:42:02.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:42:02.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:42:02.65$vc4f8/vbbw=wide 2006.175.07:42:02.65#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.07:42:02.65#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.07:42:02.65#ibcon#ireg 8 cls_cnt 0 2006.175.07:42:02.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:42:02.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:42:02.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:42:02.72#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:42:02.72#ibcon#first serial, iclass 32, count 0 2006.175.07:42:02.72#ibcon#enter sib2, iclass 32, count 0 2006.175.07:42:02.72#ibcon#flushed, iclass 32, count 0 2006.175.07:42:02.72#ibcon#about to write, iclass 32, count 0 2006.175.07:42:02.72#ibcon#wrote, iclass 32, count 0 2006.175.07:42:02.72#ibcon#about to read 3, iclass 32, count 0 2006.175.07:42:02.74#ibcon#read 3, iclass 32, count 0 2006.175.07:42:02.74#ibcon#about to read 4, iclass 32, count 0 2006.175.07:42:02.74#ibcon#read 4, iclass 32, count 0 2006.175.07:42:02.74#ibcon#about to read 5, iclass 32, count 0 2006.175.07:42:02.74#ibcon#read 5, iclass 32, count 0 2006.175.07:42:02.74#ibcon#about to read 6, iclass 32, count 0 2006.175.07:42:02.74#ibcon#read 6, iclass 32, count 0 2006.175.07:42:02.74#ibcon#end of sib2, iclass 32, count 0 2006.175.07:42:02.74#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:42:02.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:42:02.74#ibcon#[27=BW32\r\n] 2006.175.07:42:02.74#ibcon#*before write, iclass 32, count 0 2006.175.07:42:02.74#ibcon#enter sib2, iclass 32, count 0 2006.175.07:42:02.74#ibcon#flushed, iclass 32, count 0 2006.175.07:42:02.74#ibcon#about to write, iclass 32, count 0 2006.175.07:42:02.74#ibcon#wrote, iclass 32, count 0 2006.175.07:42:02.74#ibcon#about to read 3, iclass 32, count 0 2006.175.07:42:02.77#ibcon#read 3, iclass 32, count 0 2006.175.07:42:02.77#ibcon#about to read 4, iclass 32, count 0 2006.175.07:42:02.77#ibcon#read 4, iclass 32, count 0 2006.175.07:42:02.77#ibcon#about to read 5, iclass 32, count 0 2006.175.07:42:02.77#ibcon#read 5, iclass 32, count 0 2006.175.07:42:02.77#ibcon#about to read 6, iclass 32, count 0 2006.175.07:42:02.77#ibcon#read 6, iclass 32, count 0 2006.175.07:42:02.77#ibcon#end of sib2, iclass 32, count 0 2006.175.07:42:02.77#ibcon#*after write, iclass 32, count 0 2006.175.07:42:02.77#ibcon#*before return 0, iclass 32, count 0 2006.175.07:42:02.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:42:02.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:42:02.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:42:02.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:42:02.77$4f8m12a/ifd4f 2006.175.07:42:02.77$ifd4f/lo= 2006.175.07:42:02.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:42:02.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:42:02.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:42:02.77$ifd4f/patch= 2006.175.07:42:02.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:42:02.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:42:02.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:42:02.77$4f8m12a/"form=m,16.000,1:2 2006.175.07:42:02.77$4f8m12a/"tpicd 2006.175.07:42:02.77$4f8m12a/echo=off 2006.175.07:42:02.77$4f8m12a/xlog=off 2006.175.07:42:02.77:!2006.175.07:43:00 2006.175.07:42:37.13#trakl#Source acquired 2006.175.07:42:39.13#flagr#flagr/antenna,acquired 2006.175.07:43:00.00:preob 2006.175.07:43:01.13/onsource/TRACKING 2006.175.07:43:01.13:!2006.175.07:43:10 2006.175.07:43:10.00:data_valid=on 2006.175.07:43:10.00:midob 2006.175.07:43:10.13/onsource/TRACKING 2006.175.07:43:10.13/wx/25.92,1007.4,70 2006.175.07:43:10.37/cable/+6.4773E-03 2006.175.07:43:11.46/va/01,08,usb,yes,29,30 2006.175.07:43:11.46/va/02,07,usb,yes,29,30 2006.175.07:43:11.46/va/03,06,usb,yes,30,31 2006.175.07:43:11.46/va/04,07,usb,yes,30,32 2006.175.07:43:11.46/va/05,07,usb,yes,30,31 2006.175.07:43:11.46/va/06,06,usb,yes,29,29 2006.175.07:43:11.46/va/07,06,usb,yes,29,29 2006.175.07:43:11.46/va/08,06,usb,yes,31,31 2006.175.07:43:11.69/valo/01,532.99,yes,locked 2006.175.07:43:11.69/valo/02,572.99,yes,locked 2006.175.07:43:11.69/valo/03,672.99,yes,locked 2006.175.07:43:11.69/valo/04,832.99,yes,locked 2006.175.07:43:11.69/valo/05,652.99,yes,locked 2006.175.07:43:11.69/valo/06,772.99,yes,locked 2006.175.07:43:11.69/valo/07,832.99,yes,locked 2006.175.07:43:11.69/valo/08,852.99,yes,locked 2006.175.07:43:12.78/vb/01,04,usb,yes,29,28 2006.175.07:43:12.78/vb/02,04,usb,yes,31,32 2006.175.07:43:12.78/vb/03,04,usb,yes,27,31 2006.175.07:43:12.78/vb/04,04,usb,yes,28,28 2006.175.07:43:12.78/vb/05,04,usb,yes,27,31 2006.175.07:43:12.78/vb/06,04,usb,yes,28,30 2006.175.07:43:12.78/vb/07,04,usb,yes,30,30 2006.175.07:43:12.78/vb/08,04,usb,yes,27,31 2006.175.07:43:13.02/vblo/01,632.99,yes,locked 2006.175.07:43:13.02/vblo/02,640.99,yes,locked 2006.175.07:43:13.02/vblo/03,656.99,yes,locked 2006.175.07:43:13.02/vblo/04,712.99,yes,locked 2006.175.07:43:13.02/vblo/05,744.99,yes,locked 2006.175.07:43:13.02/vblo/06,752.99,yes,locked 2006.175.07:43:13.02/vblo/07,734.99,yes,locked 2006.175.07:43:13.02/vblo/08,744.99,yes,locked 2006.175.07:43:13.17/vabw/8 2006.175.07:43:13.32/vbbw/8 2006.175.07:43:13.41/xfe/off,on,15.2 2006.175.07:43:13.78/ifatt/23,28,28,28 2006.175.07:43:14.07/fmout-gps/S +3.76E-07 2006.175.07:43:14.11:!2006.175.07:45:20 2006.175.07:45:20.00:data_valid=off 2006.175.07:45:20.00:postob 2006.175.07:45:20.13/cable/+6.4782E-03 2006.175.07:45:20.13/wx/25.92,1007.4,69 2006.175.07:45:21.07/fmout-gps/S +3.76E-07 2006.175.07:45:21.07:scan_name=175-0746,k06175,60 2006.175.07:45:21.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.175.07:45:22.14#flagr#flagr/antenna,new-source 2006.175.07:45:22.14:checkk5 2006.175.07:45:22.54/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:45:22.92/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:45:23.30/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:45:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:45:24.05/chk_obsdata//k5ts1/T1750743??a.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.175.07:45:24.42/chk_obsdata//k5ts2/T1750743??b.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.175.07:45:24.79/chk_obsdata//k5ts3/T1750743??c.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.175.07:45:25.17/chk_obsdata//k5ts4/T1750743??d.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.175.07:45:25.87/k5log//k5ts1_log_newline 2006.175.07:45:26.56/k5log//k5ts2_log_newline 2006.175.07:45:27.26/k5log//k5ts3_log_newline 2006.175.07:45:27.95/k5log//k5ts4_log_newline 2006.175.07:45:27.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:45:27.97:4f8m12a=1 2006.175.07:45:27.97$4f8m12a/echo=on 2006.175.07:45:27.97$4f8m12a/pcalon 2006.175.07:45:27.97$pcalon/"no phase cal control is implemented here 2006.175.07:45:27.97$4f8m12a/"tpicd=stop 2006.175.07:45:27.97$4f8m12a/vc4f8 2006.175.07:45:27.97$vc4f8/valo=1,532.99 2006.175.07:45:27.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.07:45:27.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.07:45:27.98#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:27.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:27.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:27.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:27.98#ibcon#enter wrdev, iclass 5, count 0 2006.175.07:45:27.98#ibcon#first serial, iclass 5, count 0 2006.175.07:45:27.98#ibcon#enter sib2, iclass 5, count 0 2006.175.07:45:27.98#ibcon#flushed, iclass 5, count 0 2006.175.07:45:27.98#ibcon#about to write, iclass 5, count 0 2006.175.07:45:27.98#ibcon#wrote, iclass 5, count 0 2006.175.07:45:27.98#ibcon#about to read 3, iclass 5, count 0 2006.175.07:45:28.02#ibcon#read 3, iclass 5, count 0 2006.175.07:45:28.02#ibcon#about to read 4, iclass 5, count 0 2006.175.07:45:28.02#ibcon#read 4, iclass 5, count 0 2006.175.07:45:28.02#ibcon#about to read 5, iclass 5, count 0 2006.175.07:45:28.02#ibcon#read 5, iclass 5, count 0 2006.175.07:45:28.02#ibcon#about to read 6, iclass 5, count 0 2006.175.07:45:28.02#ibcon#read 6, iclass 5, count 0 2006.175.07:45:28.02#ibcon#end of sib2, iclass 5, count 0 2006.175.07:45:28.02#ibcon#*mode == 0, iclass 5, count 0 2006.175.07:45:28.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.07:45:28.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:45:28.02#ibcon#*before write, iclass 5, count 0 2006.175.07:45:28.02#ibcon#enter sib2, iclass 5, count 0 2006.175.07:45:28.02#ibcon#flushed, iclass 5, count 0 2006.175.07:45:28.02#ibcon#about to write, iclass 5, count 0 2006.175.07:45:28.02#ibcon#wrote, iclass 5, count 0 2006.175.07:45:28.02#ibcon#about to read 3, iclass 5, count 0 2006.175.07:45:28.07#ibcon#read 3, iclass 5, count 0 2006.175.07:45:28.07#ibcon#about to read 4, iclass 5, count 0 2006.175.07:45:28.07#ibcon#read 4, iclass 5, count 0 2006.175.07:45:28.07#ibcon#about to read 5, iclass 5, count 0 2006.175.07:45:28.07#ibcon#read 5, iclass 5, count 0 2006.175.07:45:28.07#ibcon#about to read 6, iclass 5, count 0 2006.175.07:45:28.07#ibcon#read 6, iclass 5, count 0 2006.175.07:45:28.07#ibcon#end of sib2, iclass 5, count 0 2006.175.07:45:28.07#ibcon#*after write, iclass 5, count 0 2006.175.07:45:28.07#ibcon#*before return 0, iclass 5, count 0 2006.175.07:45:28.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:28.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:28.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.07:45:28.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.07:45:28.07$vc4f8/va=1,8 2006.175.07:45:28.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.07:45:28.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.07:45:28.07#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:28.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:28.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:28.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:28.07#ibcon#enter wrdev, iclass 7, count 2 2006.175.07:45:28.07#ibcon#first serial, iclass 7, count 2 2006.175.07:45:28.07#ibcon#enter sib2, iclass 7, count 2 2006.175.07:45:28.07#ibcon#flushed, iclass 7, count 2 2006.175.07:45:28.07#ibcon#about to write, iclass 7, count 2 2006.175.07:45:28.07#ibcon#wrote, iclass 7, count 2 2006.175.07:45:28.07#ibcon#about to read 3, iclass 7, count 2 2006.175.07:45:28.09#ibcon#read 3, iclass 7, count 2 2006.175.07:45:28.09#ibcon#about to read 4, iclass 7, count 2 2006.175.07:45:28.09#ibcon#read 4, iclass 7, count 2 2006.175.07:45:28.09#ibcon#about to read 5, iclass 7, count 2 2006.175.07:45:28.09#ibcon#read 5, iclass 7, count 2 2006.175.07:45:28.09#ibcon#about to read 6, iclass 7, count 2 2006.175.07:45:28.09#ibcon#read 6, iclass 7, count 2 2006.175.07:45:28.09#ibcon#end of sib2, iclass 7, count 2 2006.175.07:45:28.09#ibcon#*mode == 0, iclass 7, count 2 2006.175.07:45:28.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.07:45:28.09#ibcon#[25=AT01-08\r\n] 2006.175.07:45:28.09#ibcon#*before write, iclass 7, count 2 2006.175.07:45:28.09#ibcon#enter sib2, iclass 7, count 2 2006.175.07:45:28.09#ibcon#flushed, iclass 7, count 2 2006.175.07:45:28.09#ibcon#about to write, iclass 7, count 2 2006.175.07:45:28.09#ibcon#wrote, iclass 7, count 2 2006.175.07:45:28.09#ibcon#about to read 3, iclass 7, count 2 2006.175.07:45:28.12#ibcon#read 3, iclass 7, count 2 2006.175.07:45:28.12#ibcon#about to read 4, iclass 7, count 2 2006.175.07:45:28.12#ibcon#read 4, iclass 7, count 2 2006.175.07:45:28.12#ibcon#about to read 5, iclass 7, count 2 2006.175.07:45:28.12#ibcon#read 5, iclass 7, count 2 2006.175.07:45:28.12#ibcon#about to read 6, iclass 7, count 2 2006.175.07:45:28.12#ibcon#read 6, iclass 7, count 2 2006.175.07:45:28.12#ibcon#end of sib2, iclass 7, count 2 2006.175.07:45:28.12#ibcon#*after write, iclass 7, count 2 2006.175.07:45:28.12#ibcon#*before return 0, iclass 7, count 2 2006.175.07:45:28.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:28.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:28.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.07:45:28.12#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:28.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:28.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:28.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:28.24#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:45:28.24#ibcon#first serial, iclass 7, count 0 2006.175.07:45:28.24#ibcon#enter sib2, iclass 7, count 0 2006.175.07:45:28.24#ibcon#flushed, iclass 7, count 0 2006.175.07:45:28.24#ibcon#about to write, iclass 7, count 0 2006.175.07:45:28.24#ibcon#wrote, iclass 7, count 0 2006.175.07:45:28.24#ibcon#about to read 3, iclass 7, count 0 2006.175.07:45:28.26#ibcon#read 3, iclass 7, count 0 2006.175.07:45:28.26#ibcon#about to read 4, iclass 7, count 0 2006.175.07:45:28.26#ibcon#read 4, iclass 7, count 0 2006.175.07:45:28.26#ibcon#about to read 5, iclass 7, count 0 2006.175.07:45:28.26#ibcon#read 5, iclass 7, count 0 2006.175.07:45:28.26#ibcon#about to read 6, iclass 7, count 0 2006.175.07:45:28.26#ibcon#read 6, iclass 7, count 0 2006.175.07:45:28.26#ibcon#end of sib2, iclass 7, count 0 2006.175.07:45:28.26#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:45:28.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:45:28.26#ibcon#[25=USB\r\n] 2006.175.07:45:28.26#ibcon#*before write, iclass 7, count 0 2006.175.07:45:28.26#ibcon#enter sib2, iclass 7, count 0 2006.175.07:45:28.26#ibcon#flushed, iclass 7, count 0 2006.175.07:45:28.26#ibcon#about to write, iclass 7, count 0 2006.175.07:45:28.26#ibcon#wrote, iclass 7, count 0 2006.175.07:45:28.26#ibcon#about to read 3, iclass 7, count 0 2006.175.07:45:28.29#ibcon#read 3, iclass 7, count 0 2006.175.07:45:28.29#ibcon#about to read 4, iclass 7, count 0 2006.175.07:45:28.29#ibcon#read 4, iclass 7, count 0 2006.175.07:45:28.29#ibcon#about to read 5, iclass 7, count 0 2006.175.07:45:28.29#ibcon#read 5, iclass 7, count 0 2006.175.07:45:28.29#ibcon#about to read 6, iclass 7, count 0 2006.175.07:45:28.29#ibcon#read 6, iclass 7, count 0 2006.175.07:45:28.29#ibcon#end of sib2, iclass 7, count 0 2006.175.07:45:28.29#ibcon#*after write, iclass 7, count 0 2006.175.07:45:28.29#ibcon#*before return 0, iclass 7, count 0 2006.175.07:45:28.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:28.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:28.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:45:28.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:45:28.29$vc4f8/valo=2,572.99 2006.175.07:45:28.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.07:45:28.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.07:45:28.29#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:28.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:28.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:28.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:28.29#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:45:28.29#ibcon#first serial, iclass 11, count 0 2006.175.07:45:28.29#ibcon#enter sib2, iclass 11, count 0 2006.175.07:45:28.29#ibcon#flushed, iclass 11, count 0 2006.175.07:45:28.29#ibcon#about to write, iclass 11, count 0 2006.175.07:45:28.29#ibcon#wrote, iclass 11, count 0 2006.175.07:45:28.29#ibcon#about to read 3, iclass 11, count 0 2006.175.07:45:28.31#ibcon#read 3, iclass 11, count 0 2006.175.07:45:28.31#ibcon#about to read 4, iclass 11, count 0 2006.175.07:45:28.31#ibcon#read 4, iclass 11, count 0 2006.175.07:45:28.31#ibcon#about to read 5, iclass 11, count 0 2006.175.07:45:28.31#ibcon#read 5, iclass 11, count 0 2006.175.07:45:28.31#ibcon#about to read 6, iclass 11, count 0 2006.175.07:45:28.31#ibcon#read 6, iclass 11, count 0 2006.175.07:45:28.31#ibcon#end of sib2, iclass 11, count 0 2006.175.07:45:28.31#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:45:28.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:45:28.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:45:28.31#ibcon#*before write, iclass 11, count 0 2006.175.07:45:28.31#ibcon#enter sib2, iclass 11, count 0 2006.175.07:45:28.31#ibcon#flushed, iclass 11, count 0 2006.175.07:45:28.31#ibcon#about to write, iclass 11, count 0 2006.175.07:45:28.31#ibcon#wrote, iclass 11, count 0 2006.175.07:45:28.31#ibcon#about to read 3, iclass 11, count 0 2006.175.07:45:28.35#ibcon#read 3, iclass 11, count 0 2006.175.07:45:28.35#ibcon#about to read 4, iclass 11, count 0 2006.175.07:45:28.35#ibcon#read 4, iclass 11, count 0 2006.175.07:45:28.35#ibcon#about to read 5, iclass 11, count 0 2006.175.07:45:28.35#ibcon#read 5, iclass 11, count 0 2006.175.07:45:28.35#ibcon#about to read 6, iclass 11, count 0 2006.175.07:45:28.35#ibcon#read 6, iclass 11, count 0 2006.175.07:45:28.35#ibcon#end of sib2, iclass 11, count 0 2006.175.07:45:28.35#ibcon#*after write, iclass 11, count 0 2006.175.07:45:28.35#ibcon#*before return 0, iclass 11, count 0 2006.175.07:45:28.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:28.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:28.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:45:28.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:45:28.35$vc4f8/va=2,7 2006.175.07:45:28.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.07:45:28.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.07:45:28.35#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:28.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:28.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:28.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:28.41#ibcon#enter wrdev, iclass 13, count 2 2006.175.07:45:28.41#ibcon#first serial, iclass 13, count 2 2006.175.07:45:28.41#ibcon#enter sib2, iclass 13, count 2 2006.175.07:45:28.41#ibcon#flushed, iclass 13, count 2 2006.175.07:45:28.41#ibcon#about to write, iclass 13, count 2 2006.175.07:45:28.41#ibcon#wrote, iclass 13, count 2 2006.175.07:45:28.41#ibcon#about to read 3, iclass 13, count 2 2006.175.07:45:28.43#ibcon#read 3, iclass 13, count 2 2006.175.07:45:28.43#ibcon#about to read 4, iclass 13, count 2 2006.175.07:45:28.43#ibcon#read 4, iclass 13, count 2 2006.175.07:45:28.43#ibcon#about to read 5, iclass 13, count 2 2006.175.07:45:28.43#ibcon#read 5, iclass 13, count 2 2006.175.07:45:28.43#ibcon#about to read 6, iclass 13, count 2 2006.175.07:45:28.43#ibcon#read 6, iclass 13, count 2 2006.175.07:45:28.43#ibcon#end of sib2, iclass 13, count 2 2006.175.07:45:28.43#ibcon#*mode == 0, iclass 13, count 2 2006.175.07:45:28.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.07:45:28.43#ibcon#[25=AT02-07\r\n] 2006.175.07:45:28.43#ibcon#*before write, iclass 13, count 2 2006.175.07:45:28.43#ibcon#enter sib2, iclass 13, count 2 2006.175.07:45:28.43#ibcon#flushed, iclass 13, count 2 2006.175.07:45:28.43#ibcon#about to write, iclass 13, count 2 2006.175.07:45:28.43#ibcon#wrote, iclass 13, count 2 2006.175.07:45:28.43#ibcon#about to read 3, iclass 13, count 2 2006.175.07:45:28.46#ibcon#read 3, iclass 13, count 2 2006.175.07:45:28.46#ibcon#about to read 4, iclass 13, count 2 2006.175.07:45:28.46#ibcon#read 4, iclass 13, count 2 2006.175.07:45:28.46#ibcon#about to read 5, iclass 13, count 2 2006.175.07:45:28.46#ibcon#read 5, iclass 13, count 2 2006.175.07:45:28.46#ibcon#about to read 6, iclass 13, count 2 2006.175.07:45:28.46#ibcon#read 6, iclass 13, count 2 2006.175.07:45:28.46#ibcon#end of sib2, iclass 13, count 2 2006.175.07:45:28.46#ibcon#*after write, iclass 13, count 2 2006.175.07:45:28.46#ibcon#*before return 0, iclass 13, count 2 2006.175.07:45:28.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:28.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:28.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.07:45:28.46#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:28.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:28.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:28.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:28.58#ibcon#enter wrdev, iclass 13, count 0 2006.175.07:45:28.58#ibcon#first serial, iclass 13, count 0 2006.175.07:45:28.58#ibcon#enter sib2, iclass 13, count 0 2006.175.07:45:28.58#ibcon#flushed, iclass 13, count 0 2006.175.07:45:28.58#ibcon#about to write, iclass 13, count 0 2006.175.07:45:28.58#ibcon#wrote, iclass 13, count 0 2006.175.07:45:28.58#ibcon#about to read 3, iclass 13, count 0 2006.175.07:45:28.60#ibcon#read 3, iclass 13, count 0 2006.175.07:45:28.60#ibcon#about to read 4, iclass 13, count 0 2006.175.07:45:28.60#ibcon#read 4, iclass 13, count 0 2006.175.07:45:28.60#ibcon#about to read 5, iclass 13, count 0 2006.175.07:45:28.60#ibcon#read 5, iclass 13, count 0 2006.175.07:45:28.60#ibcon#about to read 6, iclass 13, count 0 2006.175.07:45:28.60#ibcon#read 6, iclass 13, count 0 2006.175.07:45:28.60#ibcon#end of sib2, iclass 13, count 0 2006.175.07:45:28.60#ibcon#*mode == 0, iclass 13, count 0 2006.175.07:45:28.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.07:45:28.60#ibcon#[25=USB\r\n] 2006.175.07:45:28.60#ibcon#*before write, iclass 13, count 0 2006.175.07:45:28.60#ibcon#enter sib2, iclass 13, count 0 2006.175.07:45:28.60#ibcon#flushed, iclass 13, count 0 2006.175.07:45:28.60#ibcon#about to write, iclass 13, count 0 2006.175.07:45:28.60#ibcon#wrote, iclass 13, count 0 2006.175.07:45:28.60#ibcon#about to read 3, iclass 13, count 0 2006.175.07:45:28.63#ibcon#read 3, iclass 13, count 0 2006.175.07:45:28.63#ibcon#about to read 4, iclass 13, count 0 2006.175.07:45:28.63#ibcon#read 4, iclass 13, count 0 2006.175.07:45:28.63#ibcon#about to read 5, iclass 13, count 0 2006.175.07:45:28.63#ibcon#read 5, iclass 13, count 0 2006.175.07:45:28.63#ibcon#about to read 6, iclass 13, count 0 2006.175.07:45:28.63#ibcon#read 6, iclass 13, count 0 2006.175.07:45:28.63#ibcon#end of sib2, iclass 13, count 0 2006.175.07:45:28.63#ibcon#*after write, iclass 13, count 0 2006.175.07:45:28.63#ibcon#*before return 0, iclass 13, count 0 2006.175.07:45:28.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:28.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:28.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.07:45:28.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.07:45:28.63$vc4f8/valo=3,672.99 2006.175.07:45:28.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.07:45:28.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.07:45:28.63#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:28.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:28.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:28.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:28.63#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:45:28.63#ibcon#first serial, iclass 15, count 0 2006.175.07:45:28.63#ibcon#enter sib2, iclass 15, count 0 2006.175.07:45:28.63#ibcon#flushed, iclass 15, count 0 2006.175.07:45:28.63#ibcon#about to write, iclass 15, count 0 2006.175.07:45:28.63#ibcon#wrote, iclass 15, count 0 2006.175.07:45:28.63#ibcon#about to read 3, iclass 15, count 0 2006.175.07:45:28.65#ibcon#read 3, iclass 15, count 0 2006.175.07:45:28.65#ibcon#about to read 4, iclass 15, count 0 2006.175.07:45:28.65#ibcon#read 4, iclass 15, count 0 2006.175.07:45:28.65#ibcon#about to read 5, iclass 15, count 0 2006.175.07:45:28.65#ibcon#read 5, iclass 15, count 0 2006.175.07:45:28.65#ibcon#about to read 6, iclass 15, count 0 2006.175.07:45:28.65#ibcon#read 6, iclass 15, count 0 2006.175.07:45:28.65#ibcon#end of sib2, iclass 15, count 0 2006.175.07:45:28.65#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:45:28.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:45:28.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:45:28.65#ibcon#*before write, iclass 15, count 0 2006.175.07:45:28.65#ibcon#enter sib2, iclass 15, count 0 2006.175.07:45:28.65#ibcon#flushed, iclass 15, count 0 2006.175.07:45:28.65#ibcon#about to write, iclass 15, count 0 2006.175.07:45:28.65#ibcon#wrote, iclass 15, count 0 2006.175.07:45:28.65#ibcon#about to read 3, iclass 15, count 0 2006.175.07:45:28.69#ibcon#read 3, iclass 15, count 0 2006.175.07:45:28.69#ibcon#about to read 4, iclass 15, count 0 2006.175.07:45:28.69#ibcon#read 4, iclass 15, count 0 2006.175.07:45:28.69#ibcon#about to read 5, iclass 15, count 0 2006.175.07:45:28.69#ibcon#read 5, iclass 15, count 0 2006.175.07:45:28.69#ibcon#about to read 6, iclass 15, count 0 2006.175.07:45:28.69#ibcon#read 6, iclass 15, count 0 2006.175.07:45:28.69#ibcon#end of sib2, iclass 15, count 0 2006.175.07:45:28.69#ibcon#*after write, iclass 15, count 0 2006.175.07:45:28.69#ibcon#*before return 0, iclass 15, count 0 2006.175.07:45:28.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:28.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:28.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:45:28.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:45:28.69$vc4f8/va=3,6 2006.175.07:45:28.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.07:45:28.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.07:45:28.69#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:28.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:28.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:28.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:28.75#ibcon#enter wrdev, iclass 17, count 2 2006.175.07:45:28.75#ibcon#first serial, iclass 17, count 2 2006.175.07:45:28.75#ibcon#enter sib2, iclass 17, count 2 2006.175.07:45:28.75#ibcon#flushed, iclass 17, count 2 2006.175.07:45:28.75#ibcon#about to write, iclass 17, count 2 2006.175.07:45:28.75#ibcon#wrote, iclass 17, count 2 2006.175.07:45:28.75#ibcon#about to read 3, iclass 17, count 2 2006.175.07:45:28.77#ibcon#read 3, iclass 17, count 2 2006.175.07:45:28.77#ibcon#about to read 4, iclass 17, count 2 2006.175.07:45:28.77#ibcon#read 4, iclass 17, count 2 2006.175.07:45:28.77#ibcon#about to read 5, iclass 17, count 2 2006.175.07:45:28.77#ibcon#read 5, iclass 17, count 2 2006.175.07:45:28.77#ibcon#about to read 6, iclass 17, count 2 2006.175.07:45:28.77#ibcon#read 6, iclass 17, count 2 2006.175.07:45:28.77#ibcon#end of sib2, iclass 17, count 2 2006.175.07:45:28.77#ibcon#*mode == 0, iclass 17, count 2 2006.175.07:45:28.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.07:45:28.77#ibcon#[25=AT03-06\r\n] 2006.175.07:45:28.77#ibcon#*before write, iclass 17, count 2 2006.175.07:45:28.77#ibcon#enter sib2, iclass 17, count 2 2006.175.07:45:28.77#ibcon#flushed, iclass 17, count 2 2006.175.07:45:28.77#ibcon#about to write, iclass 17, count 2 2006.175.07:45:28.77#ibcon#wrote, iclass 17, count 2 2006.175.07:45:28.77#ibcon#about to read 3, iclass 17, count 2 2006.175.07:45:28.80#ibcon#read 3, iclass 17, count 2 2006.175.07:45:28.80#ibcon#about to read 4, iclass 17, count 2 2006.175.07:45:28.80#ibcon#read 4, iclass 17, count 2 2006.175.07:45:28.80#ibcon#about to read 5, iclass 17, count 2 2006.175.07:45:28.80#ibcon#read 5, iclass 17, count 2 2006.175.07:45:28.80#ibcon#about to read 6, iclass 17, count 2 2006.175.07:45:28.80#ibcon#read 6, iclass 17, count 2 2006.175.07:45:28.80#ibcon#end of sib2, iclass 17, count 2 2006.175.07:45:28.80#ibcon#*after write, iclass 17, count 2 2006.175.07:45:28.80#ibcon#*before return 0, iclass 17, count 2 2006.175.07:45:28.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:28.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:28.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.07:45:28.80#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:28.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:28.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:28.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:28.92#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:45:28.92#ibcon#first serial, iclass 17, count 0 2006.175.07:45:28.92#ibcon#enter sib2, iclass 17, count 0 2006.175.07:45:28.92#ibcon#flushed, iclass 17, count 0 2006.175.07:45:28.92#ibcon#about to write, iclass 17, count 0 2006.175.07:45:28.92#ibcon#wrote, iclass 17, count 0 2006.175.07:45:28.92#ibcon#about to read 3, iclass 17, count 0 2006.175.07:45:28.94#ibcon#read 3, iclass 17, count 0 2006.175.07:45:28.94#ibcon#about to read 4, iclass 17, count 0 2006.175.07:45:28.94#ibcon#read 4, iclass 17, count 0 2006.175.07:45:28.94#ibcon#about to read 5, iclass 17, count 0 2006.175.07:45:28.94#ibcon#read 5, iclass 17, count 0 2006.175.07:45:28.94#ibcon#about to read 6, iclass 17, count 0 2006.175.07:45:28.94#ibcon#read 6, iclass 17, count 0 2006.175.07:45:28.94#ibcon#end of sib2, iclass 17, count 0 2006.175.07:45:28.94#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:45:28.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:45:28.94#ibcon#[25=USB\r\n] 2006.175.07:45:28.94#ibcon#*before write, iclass 17, count 0 2006.175.07:45:28.94#ibcon#enter sib2, iclass 17, count 0 2006.175.07:45:28.94#ibcon#flushed, iclass 17, count 0 2006.175.07:45:28.94#ibcon#about to write, iclass 17, count 0 2006.175.07:45:28.94#ibcon#wrote, iclass 17, count 0 2006.175.07:45:28.94#ibcon#about to read 3, iclass 17, count 0 2006.175.07:45:28.97#ibcon#read 3, iclass 17, count 0 2006.175.07:45:28.97#ibcon#about to read 4, iclass 17, count 0 2006.175.07:45:28.97#ibcon#read 4, iclass 17, count 0 2006.175.07:45:28.97#ibcon#about to read 5, iclass 17, count 0 2006.175.07:45:28.97#ibcon#read 5, iclass 17, count 0 2006.175.07:45:28.97#ibcon#about to read 6, iclass 17, count 0 2006.175.07:45:28.97#ibcon#read 6, iclass 17, count 0 2006.175.07:45:28.97#ibcon#end of sib2, iclass 17, count 0 2006.175.07:45:28.97#ibcon#*after write, iclass 17, count 0 2006.175.07:45:28.97#ibcon#*before return 0, iclass 17, count 0 2006.175.07:45:28.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:28.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:28.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:45:28.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:45:28.97$vc4f8/valo=4,832.99 2006.175.07:45:28.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.07:45:28.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.07:45:28.97#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:28.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:28.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:28.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:28.97#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:45:28.97#ibcon#first serial, iclass 19, count 0 2006.175.07:45:28.97#ibcon#enter sib2, iclass 19, count 0 2006.175.07:45:28.97#ibcon#flushed, iclass 19, count 0 2006.175.07:45:28.97#ibcon#about to write, iclass 19, count 0 2006.175.07:45:28.97#ibcon#wrote, iclass 19, count 0 2006.175.07:45:28.97#ibcon#about to read 3, iclass 19, count 0 2006.175.07:45:28.99#ibcon#read 3, iclass 19, count 0 2006.175.07:45:28.99#ibcon#about to read 4, iclass 19, count 0 2006.175.07:45:28.99#ibcon#read 4, iclass 19, count 0 2006.175.07:45:28.99#ibcon#about to read 5, iclass 19, count 0 2006.175.07:45:28.99#ibcon#read 5, iclass 19, count 0 2006.175.07:45:28.99#ibcon#about to read 6, iclass 19, count 0 2006.175.07:45:28.99#ibcon#read 6, iclass 19, count 0 2006.175.07:45:28.99#ibcon#end of sib2, iclass 19, count 0 2006.175.07:45:28.99#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:45:28.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:45:28.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:45:28.99#ibcon#*before write, iclass 19, count 0 2006.175.07:45:28.99#ibcon#enter sib2, iclass 19, count 0 2006.175.07:45:28.99#ibcon#flushed, iclass 19, count 0 2006.175.07:45:28.99#ibcon#about to write, iclass 19, count 0 2006.175.07:45:28.99#ibcon#wrote, iclass 19, count 0 2006.175.07:45:28.99#ibcon#about to read 3, iclass 19, count 0 2006.175.07:45:29.03#ibcon#read 3, iclass 19, count 0 2006.175.07:45:29.03#ibcon#about to read 4, iclass 19, count 0 2006.175.07:45:29.03#ibcon#read 4, iclass 19, count 0 2006.175.07:45:29.03#ibcon#about to read 5, iclass 19, count 0 2006.175.07:45:29.03#ibcon#read 5, iclass 19, count 0 2006.175.07:45:29.03#ibcon#about to read 6, iclass 19, count 0 2006.175.07:45:29.03#ibcon#read 6, iclass 19, count 0 2006.175.07:45:29.03#ibcon#end of sib2, iclass 19, count 0 2006.175.07:45:29.03#ibcon#*after write, iclass 19, count 0 2006.175.07:45:29.03#ibcon#*before return 0, iclass 19, count 0 2006.175.07:45:29.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:29.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:29.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:45:29.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:45:29.03$vc4f8/va=4,7 2006.175.07:45:29.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.07:45:29.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.07:45:29.03#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:29.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:29.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:29.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:29.09#ibcon#enter wrdev, iclass 21, count 2 2006.175.07:45:29.09#ibcon#first serial, iclass 21, count 2 2006.175.07:45:29.09#ibcon#enter sib2, iclass 21, count 2 2006.175.07:45:29.09#ibcon#flushed, iclass 21, count 2 2006.175.07:45:29.09#ibcon#about to write, iclass 21, count 2 2006.175.07:45:29.09#ibcon#wrote, iclass 21, count 2 2006.175.07:45:29.09#ibcon#about to read 3, iclass 21, count 2 2006.175.07:45:29.11#ibcon#read 3, iclass 21, count 2 2006.175.07:45:29.11#ibcon#about to read 4, iclass 21, count 2 2006.175.07:45:29.11#ibcon#read 4, iclass 21, count 2 2006.175.07:45:29.11#ibcon#about to read 5, iclass 21, count 2 2006.175.07:45:29.11#ibcon#read 5, iclass 21, count 2 2006.175.07:45:29.11#ibcon#about to read 6, iclass 21, count 2 2006.175.07:45:29.11#ibcon#read 6, iclass 21, count 2 2006.175.07:45:29.11#ibcon#end of sib2, iclass 21, count 2 2006.175.07:45:29.11#ibcon#*mode == 0, iclass 21, count 2 2006.175.07:45:29.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.07:45:29.11#ibcon#[25=AT04-07\r\n] 2006.175.07:45:29.11#ibcon#*before write, iclass 21, count 2 2006.175.07:45:29.11#ibcon#enter sib2, iclass 21, count 2 2006.175.07:45:29.11#ibcon#flushed, iclass 21, count 2 2006.175.07:45:29.11#ibcon#about to write, iclass 21, count 2 2006.175.07:45:29.11#ibcon#wrote, iclass 21, count 2 2006.175.07:45:29.11#ibcon#about to read 3, iclass 21, count 2 2006.175.07:45:29.14#ibcon#read 3, iclass 21, count 2 2006.175.07:45:29.14#ibcon#about to read 4, iclass 21, count 2 2006.175.07:45:29.14#ibcon#read 4, iclass 21, count 2 2006.175.07:45:29.14#ibcon#about to read 5, iclass 21, count 2 2006.175.07:45:29.14#ibcon#read 5, iclass 21, count 2 2006.175.07:45:29.14#ibcon#about to read 6, iclass 21, count 2 2006.175.07:45:29.14#ibcon#read 6, iclass 21, count 2 2006.175.07:45:29.14#ibcon#end of sib2, iclass 21, count 2 2006.175.07:45:29.14#ibcon#*after write, iclass 21, count 2 2006.175.07:45:29.14#ibcon#*before return 0, iclass 21, count 2 2006.175.07:45:29.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:29.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:29.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.07:45:29.14#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:29.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:29.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:29.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:29.26#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:45:29.26#ibcon#first serial, iclass 21, count 0 2006.175.07:45:29.26#ibcon#enter sib2, iclass 21, count 0 2006.175.07:45:29.26#ibcon#flushed, iclass 21, count 0 2006.175.07:45:29.26#ibcon#about to write, iclass 21, count 0 2006.175.07:45:29.26#ibcon#wrote, iclass 21, count 0 2006.175.07:45:29.26#ibcon#about to read 3, iclass 21, count 0 2006.175.07:45:29.28#ibcon#read 3, iclass 21, count 0 2006.175.07:45:29.28#ibcon#about to read 4, iclass 21, count 0 2006.175.07:45:29.28#ibcon#read 4, iclass 21, count 0 2006.175.07:45:29.28#ibcon#about to read 5, iclass 21, count 0 2006.175.07:45:29.28#ibcon#read 5, iclass 21, count 0 2006.175.07:45:29.28#ibcon#about to read 6, iclass 21, count 0 2006.175.07:45:29.28#ibcon#read 6, iclass 21, count 0 2006.175.07:45:29.28#ibcon#end of sib2, iclass 21, count 0 2006.175.07:45:29.28#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:45:29.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:45:29.28#ibcon#[25=USB\r\n] 2006.175.07:45:29.28#ibcon#*before write, iclass 21, count 0 2006.175.07:45:29.28#ibcon#enter sib2, iclass 21, count 0 2006.175.07:45:29.28#ibcon#flushed, iclass 21, count 0 2006.175.07:45:29.28#ibcon#about to write, iclass 21, count 0 2006.175.07:45:29.28#ibcon#wrote, iclass 21, count 0 2006.175.07:45:29.28#ibcon#about to read 3, iclass 21, count 0 2006.175.07:45:29.31#ibcon#read 3, iclass 21, count 0 2006.175.07:45:29.31#ibcon#about to read 4, iclass 21, count 0 2006.175.07:45:29.31#ibcon#read 4, iclass 21, count 0 2006.175.07:45:29.31#ibcon#about to read 5, iclass 21, count 0 2006.175.07:45:29.31#ibcon#read 5, iclass 21, count 0 2006.175.07:45:29.31#ibcon#about to read 6, iclass 21, count 0 2006.175.07:45:29.31#ibcon#read 6, iclass 21, count 0 2006.175.07:45:29.31#ibcon#end of sib2, iclass 21, count 0 2006.175.07:45:29.31#ibcon#*after write, iclass 21, count 0 2006.175.07:45:29.31#ibcon#*before return 0, iclass 21, count 0 2006.175.07:45:29.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:29.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:29.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:45:29.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:45:29.31$vc4f8/valo=5,652.99 2006.175.07:45:29.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.07:45:29.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.07:45:29.31#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:29.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:29.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:29.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:29.31#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:45:29.31#ibcon#first serial, iclass 23, count 0 2006.175.07:45:29.31#ibcon#enter sib2, iclass 23, count 0 2006.175.07:45:29.31#ibcon#flushed, iclass 23, count 0 2006.175.07:45:29.31#ibcon#about to write, iclass 23, count 0 2006.175.07:45:29.31#ibcon#wrote, iclass 23, count 0 2006.175.07:45:29.31#ibcon#about to read 3, iclass 23, count 0 2006.175.07:45:29.33#ibcon#read 3, iclass 23, count 0 2006.175.07:45:29.33#ibcon#about to read 4, iclass 23, count 0 2006.175.07:45:29.33#ibcon#read 4, iclass 23, count 0 2006.175.07:45:29.33#ibcon#about to read 5, iclass 23, count 0 2006.175.07:45:29.33#ibcon#read 5, iclass 23, count 0 2006.175.07:45:29.33#ibcon#about to read 6, iclass 23, count 0 2006.175.07:45:29.33#ibcon#read 6, iclass 23, count 0 2006.175.07:45:29.33#ibcon#end of sib2, iclass 23, count 0 2006.175.07:45:29.33#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:45:29.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:45:29.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:45:29.33#ibcon#*before write, iclass 23, count 0 2006.175.07:45:29.33#ibcon#enter sib2, iclass 23, count 0 2006.175.07:45:29.33#ibcon#flushed, iclass 23, count 0 2006.175.07:45:29.33#ibcon#about to write, iclass 23, count 0 2006.175.07:45:29.33#ibcon#wrote, iclass 23, count 0 2006.175.07:45:29.33#ibcon#about to read 3, iclass 23, count 0 2006.175.07:45:29.37#ibcon#read 3, iclass 23, count 0 2006.175.07:45:29.37#ibcon#about to read 4, iclass 23, count 0 2006.175.07:45:29.37#ibcon#read 4, iclass 23, count 0 2006.175.07:45:29.37#ibcon#about to read 5, iclass 23, count 0 2006.175.07:45:29.37#ibcon#read 5, iclass 23, count 0 2006.175.07:45:29.37#ibcon#about to read 6, iclass 23, count 0 2006.175.07:45:29.37#ibcon#read 6, iclass 23, count 0 2006.175.07:45:29.37#ibcon#end of sib2, iclass 23, count 0 2006.175.07:45:29.37#ibcon#*after write, iclass 23, count 0 2006.175.07:45:29.37#ibcon#*before return 0, iclass 23, count 0 2006.175.07:45:29.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:29.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:29.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:45:29.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:45:29.37$vc4f8/va=5,7 2006.175.07:45:29.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.07:45:29.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.07:45:29.37#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:29.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:29.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:29.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:29.43#ibcon#enter wrdev, iclass 25, count 2 2006.175.07:45:29.43#ibcon#first serial, iclass 25, count 2 2006.175.07:45:29.43#ibcon#enter sib2, iclass 25, count 2 2006.175.07:45:29.43#ibcon#flushed, iclass 25, count 2 2006.175.07:45:29.43#ibcon#about to write, iclass 25, count 2 2006.175.07:45:29.43#ibcon#wrote, iclass 25, count 2 2006.175.07:45:29.43#ibcon#about to read 3, iclass 25, count 2 2006.175.07:45:29.45#ibcon#read 3, iclass 25, count 2 2006.175.07:45:29.45#ibcon#about to read 4, iclass 25, count 2 2006.175.07:45:29.45#ibcon#read 4, iclass 25, count 2 2006.175.07:45:29.45#ibcon#about to read 5, iclass 25, count 2 2006.175.07:45:29.45#ibcon#read 5, iclass 25, count 2 2006.175.07:45:29.45#ibcon#about to read 6, iclass 25, count 2 2006.175.07:45:29.45#ibcon#read 6, iclass 25, count 2 2006.175.07:45:29.45#ibcon#end of sib2, iclass 25, count 2 2006.175.07:45:29.45#ibcon#*mode == 0, iclass 25, count 2 2006.175.07:45:29.45#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.07:45:29.45#ibcon#[25=AT05-07\r\n] 2006.175.07:45:29.45#ibcon#*before write, iclass 25, count 2 2006.175.07:45:29.45#ibcon#enter sib2, iclass 25, count 2 2006.175.07:45:29.45#ibcon#flushed, iclass 25, count 2 2006.175.07:45:29.45#ibcon#about to write, iclass 25, count 2 2006.175.07:45:29.45#ibcon#wrote, iclass 25, count 2 2006.175.07:45:29.45#ibcon#about to read 3, iclass 25, count 2 2006.175.07:45:29.48#ibcon#read 3, iclass 25, count 2 2006.175.07:45:29.48#ibcon#about to read 4, iclass 25, count 2 2006.175.07:45:29.48#ibcon#read 4, iclass 25, count 2 2006.175.07:45:29.48#ibcon#about to read 5, iclass 25, count 2 2006.175.07:45:29.48#ibcon#read 5, iclass 25, count 2 2006.175.07:45:29.48#ibcon#about to read 6, iclass 25, count 2 2006.175.07:45:29.48#ibcon#read 6, iclass 25, count 2 2006.175.07:45:29.48#ibcon#end of sib2, iclass 25, count 2 2006.175.07:45:29.48#ibcon#*after write, iclass 25, count 2 2006.175.07:45:29.48#ibcon#*before return 0, iclass 25, count 2 2006.175.07:45:29.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:29.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:29.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.07:45:29.48#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:29.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:29.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:29.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:29.60#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:45:29.60#ibcon#first serial, iclass 25, count 0 2006.175.07:45:29.60#ibcon#enter sib2, iclass 25, count 0 2006.175.07:45:29.60#ibcon#flushed, iclass 25, count 0 2006.175.07:45:29.60#ibcon#about to write, iclass 25, count 0 2006.175.07:45:29.60#ibcon#wrote, iclass 25, count 0 2006.175.07:45:29.60#ibcon#about to read 3, iclass 25, count 0 2006.175.07:45:29.62#ibcon#read 3, iclass 25, count 0 2006.175.07:45:29.62#ibcon#about to read 4, iclass 25, count 0 2006.175.07:45:29.62#ibcon#read 4, iclass 25, count 0 2006.175.07:45:29.62#ibcon#about to read 5, iclass 25, count 0 2006.175.07:45:29.62#ibcon#read 5, iclass 25, count 0 2006.175.07:45:29.62#ibcon#about to read 6, iclass 25, count 0 2006.175.07:45:29.62#ibcon#read 6, iclass 25, count 0 2006.175.07:45:29.62#ibcon#end of sib2, iclass 25, count 0 2006.175.07:45:29.62#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:45:29.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:45:29.62#ibcon#[25=USB\r\n] 2006.175.07:45:29.62#ibcon#*before write, iclass 25, count 0 2006.175.07:45:29.62#ibcon#enter sib2, iclass 25, count 0 2006.175.07:45:29.62#ibcon#flushed, iclass 25, count 0 2006.175.07:45:29.62#ibcon#about to write, iclass 25, count 0 2006.175.07:45:29.62#ibcon#wrote, iclass 25, count 0 2006.175.07:45:29.62#ibcon#about to read 3, iclass 25, count 0 2006.175.07:45:29.65#ibcon#read 3, iclass 25, count 0 2006.175.07:45:29.65#ibcon#about to read 4, iclass 25, count 0 2006.175.07:45:29.65#ibcon#read 4, iclass 25, count 0 2006.175.07:45:29.65#ibcon#about to read 5, iclass 25, count 0 2006.175.07:45:29.65#ibcon#read 5, iclass 25, count 0 2006.175.07:45:29.65#ibcon#about to read 6, iclass 25, count 0 2006.175.07:45:29.65#ibcon#read 6, iclass 25, count 0 2006.175.07:45:29.65#ibcon#end of sib2, iclass 25, count 0 2006.175.07:45:29.65#ibcon#*after write, iclass 25, count 0 2006.175.07:45:29.65#ibcon#*before return 0, iclass 25, count 0 2006.175.07:45:29.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:29.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:29.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:45:29.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:45:29.65$vc4f8/valo=6,772.99 2006.175.07:45:29.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.07:45:29.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.07:45:29.65#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:29.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:29.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:29.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:29.65#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:45:29.65#ibcon#first serial, iclass 27, count 0 2006.175.07:45:29.65#ibcon#enter sib2, iclass 27, count 0 2006.175.07:45:29.65#ibcon#flushed, iclass 27, count 0 2006.175.07:45:29.65#ibcon#about to write, iclass 27, count 0 2006.175.07:45:29.65#ibcon#wrote, iclass 27, count 0 2006.175.07:45:29.65#ibcon#about to read 3, iclass 27, count 0 2006.175.07:45:29.67#ibcon#read 3, iclass 27, count 0 2006.175.07:45:29.67#ibcon#about to read 4, iclass 27, count 0 2006.175.07:45:29.67#ibcon#read 4, iclass 27, count 0 2006.175.07:45:29.67#ibcon#about to read 5, iclass 27, count 0 2006.175.07:45:29.67#ibcon#read 5, iclass 27, count 0 2006.175.07:45:29.67#ibcon#about to read 6, iclass 27, count 0 2006.175.07:45:29.67#ibcon#read 6, iclass 27, count 0 2006.175.07:45:29.67#ibcon#end of sib2, iclass 27, count 0 2006.175.07:45:29.67#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:45:29.67#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:45:29.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:45:29.67#ibcon#*before write, iclass 27, count 0 2006.175.07:45:29.67#ibcon#enter sib2, iclass 27, count 0 2006.175.07:45:29.67#ibcon#flushed, iclass 27, count 0 2006.175.07:45:29.67#ibcon#about to write, iclass 27, count 0 2006.175.07:45:29.67#ibcon#wrote, iclass 27, count 0 2006.175.07:45:29.67#ibcon#about to read 3, iclass 27, count 0 2006.175.07:45:29.71#ibcon#read 3, iclass 27, count 0 2006.175.07:45:29.71#ibcon#about to read 4, iclass 27, count 0 2006.175.07:45:29.71#ibcon#read 4, iclass 27, count 0 2006.175.07:45:29.71#ibcon#about to read 5, iclass 27, count 0 2006.175.07:45:29.71#ibcon#read 5, iclass 27, count 0 2006.175.07:45:29.71#ibcon#about to read 6, iclass 27, count 0 2006.175.07:45:29.71#ibcon#read 6, iclass 27, count 0 2006.175.07:45:29.71#ibcon#end of sib2, iclass 27, count 0 2006.175.07:45:29.71#ibcon#*after write, iclass 27, count 0 2006.175.07:45:29.71#ibcon#*before return 0, iclass 27, count 0 2006.175.07:45:29.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:29.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:29.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:45:29.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:45:29.71$vc4f8/va=6,6 2006.175.07:45:29.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.175.07:45:29.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.175.07:45:29.71#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:29.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:45:29.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:45:29.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:45:29.77#ibcon#enter wrdev, iclass 29, count 2 2006.175.07:45:29.77#ibcon#first serial, iclass 29, count 2 2006.175.07:45:29.77#ibcon#enter sib2, iclass 29, count 2 2006.175.07:45:29.77#ibcon#flushed, iclass 29, count 2 2006.175.07:45:29.77#ibcon#about to write, iclass 29, count 2 2006.175.07:45:29.77#ibcon#wrote, iclass 29, count 2 2006.175.07:45:29.77#ibcon#about to read 3, iclass 29, count 2 2006.175.07:45:29.79#ibcon#read 3, iclass 29, count 2 2006.175.07:45:29.79#ibcon#about to read 4, iclass 29, count 2 2006.175.07:45:29.79#ibcon#read 4, iclass 29, count 2 2006.175.07:45:29.79#ibcon#about to read 5, iclass 29, count 2 2006.175.07:45:29.79#ibcon#read 5, iclass 29, count 2 2006.175.07:45:29.79#ibcon#about to read 6, iclass 29, count 2 2006.175.07:45:29.79#ibcon#read 6, iclass 29, count 2 2006.175.07:45:29.79#ibcon#end of sib2, iclass 29, count 2 2006.175.07:45:29.79#ibcon#*mode == 0, iclass 29, count 2 2006.175.07:45:29.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.175.07:45:29.79#ibcon#[25=AT06-06\r\n] 2006.175.07:45:29.79#ibcon#*before write, iclass 29, count 2 2006.175.07:45:29.79#ibcon#enter sib2, iclass 29, count 2 2006.175.07:45:29.79#ibcon#flushed, iclass 29, count 2 2006.175.07:45:29.79#ibcon#about to write, iclass 29, count 2 2006.175.07:45:29.79#ibcon#wrote, iclass 29, count 2 2006.175.07:45:29.79#ibcon#about to read 3, iclass 29, count 2 2006.175.07:45:29.82#ibcon#read 3, iclass 29, count 2 2006.175.07:45:29.82#ibcon#about to read 4, iclass 29, count 2 2006.175.07:45:29.82#ibcon#read 4, iclass 29, count 2 2006.175.07:45:29.82#ibcon#about to read 5, iclass 29, count 2 2006.175.07:45:29.82#ibcon#read 5, iclass 29, count 2 2006.175.07:45:29.82#ibcon#about to read 6, iclass 29, count 2 2006.175.07:45:29.82#ibcon#read 6, iclass 29, count 2 2006.175.07:45:29.82#ibcon#end of sib2, iclass 29, count 2 2006.175.07:45:29.82#ibcon#*after write, iclass 29, count 2 2006.175.07:45:29.82#ibcon#*before return 0, iclass 29, count 2 2006.175.07:45:29.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:45:29.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:45:29.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.175.07:45:29.82#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:29.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:45:29.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:45:29.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:45:29.94#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:45:29.94#ibcon#first serial, iclass 29, count 0 2006.175.07:45:29.94#ibcon#enter sib2, iclass 29, count 0 2006.175.07:45:29.94#ibcon#flushed, iclass 29, count 0 2006.175.07:45:29.94#ibcon#about to write, iclass 29, count 0 2006.175.07:45:29.94#ibcon#wrote, iclass 29, count 0 2006.175.07:45:29.94#ibcon#about to read 3, iclass 29, count 0 2006.175.07:45:29.96#ibcon#read 3, iclass 29, count 0 2006.175.07:45:29.96#ibcon#about to read 4, iclass 29, count 0 2006.175.07:45:29.96#ibcon#read 4, iclass 29, count 0 2006.175.07:45:29.96#ibcon#about to read 5, iclass 29, count 0 2006.175.07:45:29.96#ibcon#read 5, iclass 29, count 0 2006.175.07:45:29.96#ibcon#about to read 6, iclass 29, count 0 2006.175.07:45:29.96#ibcon#read 6, iclass 29, count 0 2006.175.07:45:29.96#ibcon#end of sib2, iclass 29, count 0 2006.175.07:45:29.96#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:45:29.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:45:29.96#ibcon#[25=USB\r\n] 2006.175.07:45:29.96#ibcon#*before write, iclass 29, count 0 2006.175.07:45:29.96#ibcon#enter sib2, iclass 29, count 0 2006.175.07:45:29.96#ibcon#flushed, iclass 29, count 0 2006.175.07:45:29.96#ibcon#about to write, iclass 29, count 0 2006.175.07:45:29.96#ibcon#wrote, iclass 29, count 0 2006.175.07:45:29.96#ibcon#about to read 3, iclass 29, count 0 2006.175.07:45:29.99#ibcon#read 3, iclass 29, count 0 2006.175.07:45:29.99#ibcon#about to read 4, iclass 29, count 0 2006.175.07:45:29.99#ibcon#read 4, iclass 29, count 0 2006.175.07:45:29.99#ibcon#about to read 5, iclass 29, count 0 2006.175.07:45:29.99#ibcon#read 5, iclass 29, count 0 2006.175.07:45:29.99#ibcon#about to read 6, iclass 29, count 0 2006.175.07:45:29.99#ibcon#read 6, iclass 29, count 0 2006.175.07:45:29.99#ibcon#end of sib2, iclass 29, count 0 2006.175.07:45:29.99#ibcon#*after write, iclass 29, count 0 2006.175.07:45:29.99#ibcon#*before return 0, iclass 29, count 0 2006.175.07:45:29.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:45:29.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:45:29.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:45:29.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:45:29.99$vc4f8/valo=7,832.99 2006.175.07:45:29.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.07:45:29.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.07:45:29.99#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:29.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:45:29.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:45:29.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:45:29.99#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:45:29.99#ibcon#first serial, iclass 31, count 0 2006.175.07:45:29.99#ibcon#enter sib2, iclass 31, count 0 2006.175.07:45:29.99#ibcon#flushed, iclass 31, count 0 2006.175.07:45:29.99#ibcon#about to write, iclass 31, count 0 2006.175.07:45:29.99#ibcon#wrote, iclass 31, count 0 2006.175.07:45:29.99#ibcon#about to read 3, iclass 31, count 0 2006.175.07:45:30.01#ibcon#read 3, iclass 31, count 0 2006.175.07:45:30.01#ibcon#about to read 4, iclass 31, count 0 2006.175.07:45:30.01#ibcon#read 4, iclass 31, count 0 2006.175.07:45:30.01#ibcon#about to read 5, iclass 31, count 0 2006.175.07:45:30.01#ibcon#read 5, iclass 31, count 0 2006.175.07:45:30.01#ibcon#about to read 6, iclass 31, count 0 2006.175.07:45:30.01#ibcon#read 6, iclass 31, count 0 2006.175.07:45:30.01#ibcon#end of sib2, iclass 31, count 0 2006.175.07:45:30.01#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:45:30.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:45:30.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:45:30.01#ibcon#*before write, iclass 31, count 0 2006.175.07:45:30.01#ibcon#enter sib2, iclass 31, count 0 2006.175.07:45:30.01#ibcon#flushed, iclass 31, count 0 2006.175.07:45:30.01#ibcon#about to write, iclass 31, count 0 2006.175.07:45:30.01#ibcon#wrote, iclass 31, count 0 2006.175.07:45:30.01#ibcon#about to read 3, iclass 31, count 0 2006.175.07:45:30.05#ibcon#read 3, iclass 31, count 0 2006.175.07:45:30.05#ibcon#about to read 4, iclass 31, count 0 2006.175.07:45:30.05#ibcon#read 4, iclass 31, count 0 2006.175.07:45:30.05#ibcon#about to read 5, iclass 31, count 0 2006.175.07:45:30.05#ibcon#read 5, iclass 31, count 0 2006.175.07:45:30.05#ibcon#about to read 6, iclass 31, count 0 2006.175.07:45:30.05#ibcon#read 6, iclass 31, count 0 2006.175.07:45:30.05#ibcon#end of sib2, iclass 31, count 0 2006.175.07:45:30.05#ibcon#*after write, iclass 31, count 0 2006.175.07:45:30.05#ibcon#*before return 0, iclass 31, count 0 2006.175.07:45:30.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:45:30.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:45:30.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:45:30.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:45:30.05$vc4f8/va=7,6 2006.175.07:45:30.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.07:45:30.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.07:45:30.05#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:30.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:45:30.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:45:30.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:45:30.11#ibcon#enter wrdev, iclass 33, count 2 2006.175.07:45:30.11#ibcon#first serial, iclass 33, count 2 2006.175.07:45:30.11#ibcon#enter sib2, iclass 33, count 2 2006.175.07:45:30.11#ibcon#flushed, iclass 33, count 2 2006.175.07:45:30.11#ibcon#about to write, iclass 33, count 2 2006.175.07:45:30.11#ibcon#wrote, iclass 33, count 2 2006.175.07:45:30.11#ibcon#about to read 3, iclass 33, count 2 2006.175.07:45:30.13#ibcon#read 3, iclass 33, count 2 2006.175.07:45:30.13#ibcon#about to read 4, iclass 33, count 2 2006.175.07:45:30.13#ibcon#read 4, iclass 33, count 2 2006.175.07:45:30.13#ibcon#about to read 5, iclass 33, count 2 2006.175.07:45:30.13#ibcon#read 5, iclass 33, count 2 2006.175.07:45:30.13#ibcon#about to read 6, iclass 33, count 2 2006.175.07:45:30.13#ibcon#read 6, iclass 33, count 2 2006.175.07:45:30.13#ibcon#end of sib2, iclass 33, count 2 2006.175.07:45:30.13#ibcon#*mode == 0, iclass 33, count 2 2006.175.07:45:30.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.07:45:30.13#ibcon#[25=AT07-06\r\n] 2006.175.07:45:30.13#ibcon#*before write, iclass 33, count 2 2006.175.07:45:30.13#ibcon#enter sib2, iclass 33, count 2 2006.175.07:45:30.13#ibcon#flushed, iclass 33, count 2 2006.175.07:45:30.13#ibcon#about to write, iclass 33, count 2 2006.175.07:45:30.13#ibcon#wrote, iclass 33, count 2 2006.175.07:45:30.13#ibcon#about to read 3, iclass 33, count 2 2006.175.07:45:30.16#ibcon#read 3, iclass 33, count 2 2006.175.07:45:30.16#ibcon#about to read 4, iclass 33, count 2 2006.175.07:45:30.16#ibcon#read 4, iclass 33, count 2 2006.175.07:45:30.16#ibcon#about to read 5, iclass 33, count 2 2006.175.07:45:30.16#ibcon#read 5, iclass 33, count 2 2006.175.07:45:30.16#ibcon#about to read 6, iclass 33, count 2 2006.175.07:45:30.16#ibcon#read 6, iclass 33, count 2 2006.175.07:45:30.16#ibcon#end of sib2, iclass 33, count 2 2006.175.07:45:30.16#ibcon#*after write, iclass 33, count 2 2006.175.07:45:30.16#ibcon#*before return 0, iclass 33, count 2 2006.175.07:45:30.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:45:30.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:45:30.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.07:45:30.16#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:30.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:45:30.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:45:30.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:45:30.28#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:45:30.28#ibcon#first serial, iclass 33, count 0 2006.175.07:45:30.28#ibcon#enter sib2, iclass 33, count 0 2006.175.07:45:30.28#ibcon#flushed, iclass 33, count 0 2006.175.07:45:30.28#ibcon#about to write, iclass 33, count 0 2006.175.07:45:30.28#ibcon#wrote, iclass 33, count 0 2006.175.07:45:30.28#ibcon#about to read 3, iclass 33, count 0 2006.175.07:45:30.30#ibcon#read 3, iclass 33, count 0 2006.175.07:45:30.30#ibcon#about to read 4, iclass 33, count 0 2006.175.07:45:30.30#ibcon#read 4, iclass 33, count 0 2006.175.07:45:30.30#ibcon#about to read 5, iclass 33, count 0 2006.175.07:45:30.30#ibcon#read 5, iclass 33, count 0 2006.175.07:45:30.30#ibcon#about to read 6, iclass 33, count 0 2006.175.07:45:30.30#ibcon#read 6, iclass 33, count 0 2006.175.07:45:30.30#ibcon#end of sib2, iclass 33, count 0 2006.175.07:45:30.30#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:45:30.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:45:30.30#ibcon#[25=USB\r\n] 2006.175.07:45:30.30#ibcon#*before write, iclass 33, count 0 2006.175.07:45:30.30#ibcon#enter sib2, iclass 33, count 0 2006.175.07:45:30.30#ibcon#flushed, iclass 33, count 0 2006.175.07:45:30.30#ibcon#about to write, iclass 33, count 0 2006.175.07:45:30.30#ibcon#wrote, iclass 33, count 0 2006.175.07:45:30.30#ibcon#about to read 3, iclass 33, count 0 2006.175.07:45:30.33#ibcon#read 3, iclass 33, count 0 2006.175.07:45:30.33#ibcon#about to read 4, iclass 33, count 0 2006.175.07:45:30.33#ibcon#read 4, iclass 33, count 0 2006.175.07:45:30.33#ibcon#about to read 5, iclass 33, count 0 2006.175.07:45:30.33#ibcon#read 5, iclass 33, count 0 2006.175.07:45:30.33#ibcon#about to read 6, iclass 33, count 0 2006.175.07:45:30.33#ibcon#read 6, iclass 33, count 0 2006.175.07:45:30.33#ibcon#end of sib2, iclass 33, count 0 2006.175.07:45:30.33#ibcon#*after write, iclass 33, count 0 2006.175.07:45:30.33#ibcon#*before return 0, iclass 33, count 0 2006.175.07:45:30.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:45:30.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:45:30.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:45:30.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:45:30.33$vc4f8/valo=8,852.99 2006.175.07:45:30.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.07:45:30.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.07:45:30.33#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:30.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:45:30.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:45:30.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:45:30.33#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:45:30.33#ibcon#first serial, iclass 35, count 0 2006.175.07:45:30.33#ibcon#enter sib2, iclass 35, count 0 2006.175.07:45:30.33#ibcon#flushed, iclass 35, count 0 2006.175.07:45:30.33#ibcon#about to write, iclass 35, count 0 2006.175.07:45:30.33#ibcon#wrote, iclass 35, count 0 2006.175.07:45:30.33#ibcon#about to read 3, iclass 35, count 0 2006.175.07:45:30.35#ibcon#read 3, iclass 35, count 0 2006.175.07:45:30.35#ibcon#about to read 4, iclass 35, count 0 2006.175.07:45:30.35#ibcon#read 4, iclass 35, count 0 2006.175.07:45:30.35#ibcon#about to read 5, iclass 35, count 0 2006.175.07:45:30.35#ibcon#read 5, iclass 35, count 0 2006.175.07:45:30.35#ibcon#about to read 6, iclass 35, count 0 2006.175.07:45:30.35#ibcon#read 6, iclass 35, count 0 2006.175.07:45:30.35#ibcon#end of sib2, iclass 35, count 0 2006.175.07:45:30.35#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:45:30.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:45:30.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:45:30.35#ibcon#*before write, iclass 35, count 0 2006.175.07:45:30.35#ibcon#enter sib2, iclass 35, count 0 2006.175.07:45:30.35#ibcon#flushed, iclass 35, count 0 2006.175.07:45:30.35#ibcon#about to write, iclass 35, count 0 2006.175.07:45:30.35#ibcon#wrote, iclass 35, count 0 2006.175.07:45:30.35#ibcon#about to read 3, iclass 35, count 0 2006.175.07:45:30.39#ibcon#read 3, iclass 35, count 0 2006.175.07:45:30.39#ibcon#about to read 4, iclass 35, count 0 2006.175.07:45:30.39#ibcon#read 4, iclass 35, count 0 2006.175.07:45:30.39#ibcon#about to read 5, iclass 35, count 0 2006.175.07:45:30.39#ibcon#read 5, iclass 35, count 0 2006.175.07:45:30.39#ibcon#about to read 6, iclass 35, count 0 2006.175.07:45:30.39#ibcon#read 6, iclass 35, count 0 2006.175.07:45:30.39#ibcon#end of sib2, iclass 35, count 0 2006.175.07:45:30.39#ibcon#*after write, iclass 35, count 0 2006.175.07:45:30.39#ibcon#*before return 0, iclass 35, count 0 2006.175.07:45:30.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:45:30.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:45:30.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:45:30.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:45:30.39$vc4f8/va=8,6 2006.175.07:45:30.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.07:45:30.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.07:45:30.39#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:30.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:45:30.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:45:30.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:45:30.45#ibcon#enter wrdev, iclass 37, count 2 2006.175.07:45:30.45#ibcon#first serial, iclass 37, count 2 2006.175.07:45:30.45#ibcon#enter sib2, iclass 37, count 2 2006.175.07:45:30.45#ibcon#flushed, iclass 37, count 2 2006.175.07:45:30.45#ibcon#about to write, iclass 37, count 2 2006.175.07:45:30.45#ibcon#wrote, iclass 37, count 2 2006.175.07:45:30.45#ibcon#about to read 3, iclass 37, count 2 2006.175.07:45:30.47#ibcon#read 3, iclass 37, count 2 2006.175.07:45:30.47#ibcon#about to read 4, iclass 37, count 2 2006.175.07:45:30.47#ibcon#read 4, iclass 37, count 2 2006.175.07:45:30.47#ibcon#about to read 5, iclass 37, count 2 2006.175.07:45:30.47#ibcon#read 5, iclass 37, count 2 2006.175.07:45:30.47#ibcon#about to read 6, iclass 37, count 2 2006.175.07:45:30.47#ibcon#read 6, iclass 37, count 2 2006.175.07:45:30.47#ibcon#end of sib2, iclass 37, count 2 2006.175.07:45:30.47#ibcon#*mode == 0, iclass 37, count 2 2006.175.07:45:30.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.07:45:30.47#ibcon#[25=AT08-06\r\n] 2006.175.07:45:30.47#ibcon#*before write, iclass 37, count 2 2006.175.07:45:30.47#ibcon#enter sib2, iclass 37, count 2 2006.175.07:45:30.47#ibcon#flushed, iclass 37, count 2 2006.175.07:45:30.47#ibcon#about to write, iclass 37, count 2 2006.175.07:45:30.47#ibcon#wrote, iclass 37, count 2 2006.175.07:45:30.47#ibcon#about to read 3, iclass 37, count 2 2006.175.07:45:30.50#ibcon#read 3, iclass 37, count 2 2006.175.07:45:30.50#ibcon#about to read 4, iclass 37, count 2 2006.175.07:45:30.50#ibcon#read 4, iclass 37, count 2 2006.175.07:45:30.50#ibcon#about to read 5, iclass 37, count 2 2006.175.07:45:30.50#ibcon#read 5, iclass 37, count 2 2006.175.07:45:30.50#ibcon#about to read 6, iclass 37, count 2 2006.175.07:45:30.50#ibcon#read 6, iclass 37, count 2 2006.175.07:45:30.50#ibcon#end of sib2, iclass 37, count 2 2006.175.07:45:30.50#ibcon#*after write, iclass 37, count 2 2006.175.07:45:30.50#ibcon#*before return 0, iclass 37, count 2 2006.175.07:45:30.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:45:30.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:45:30.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.07:45:30.50#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:30.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:45:30.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:45:30.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:45:30.62#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:45:30.62#ibcon#first serial, iclass 37, count 0 2006.175.07:45:30.62#ibcon#enter sib2, iclass 37, count 0 2006.175.07:45:30.62#ibcon#flushed, iclass 37, count 0 2006.175.07:45:30.62#ibcon#about to write, iclass 37, count 0 2006.175.07:45:30.62#ibcon#wrote, iclass 37, count 0 2006.175.07:45:30.62#ibcon#about to read 3, iclass 37, count 0 2006.175.07:45:30.64#ibcon#read 3, iclass 37, count 0 2006.175.07:45:30.64#ibcon#about to read 4, iclass 37, count 0 2006.175.07:45:30.64#ibcon#read 4, iclass 37, count 0 2006.175.07:45:30.64#ibcon#about to read 5, iclass 37, count 0 2006.175.07:45:30.64#ibcon#read 5, iclass 37, count 0 2006.175.07:45:30.64#ibcon#about to read 6, iclass 37, count 0 2006.175.07:45:30.64#ibcon#read 6, iclass 37, count 0 2006.175.07:45:30.64#ibcon#end of sib2, iclass 37, count 0 2006.175.07:45:30.64#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:45:30.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:45:30.64#ibcon#[25=USB\r\n] 2006.175.07:45:30.64#ibcon#*before write, iclass 37, count 0 2006.175.07:45:30.64#ibcon#enter sib2, iclass 37, count 0 2006.175.07:45:30.64#ibcon#flushed, iclass 37, count 0 2006.175.07:45:30.64#ibcon#about to write, iclass 37, count 0 2006.175.07:45:30.64#ibcon#wrote, iclass 37, count 0 2006.175.07:45:30.64#ibcon#about to read 3, iclass 37, count 0 2006.175.07:45:30.67#ibcon#read 3, iclass 37, count 0 2006.175.07:45:30.67#ibcon#about to read 4, iclass 37, count 0 2006.175.07:45:30.67#ibcon#read 4, iclass 37, count 0 2006.175.07:45:30.67#ibcon#about to read 5, iclass 37, count 0 2006.175.07:45:30.67#ibcon#read 5, iclass 37, count 0 2006.175.07:45:30.67#ibcon#about to read 6, iclass 37, count 0 2006.175.07:45:30.67#ibcon#read 6, iclass 37, count 0 2006.175.07:45:30.67#ibcon#end of sib2, iclass 37, count 0 2006.175.07:45:30.67#ibcon#*after write, iclass 37, count 0 2006.175.07:45:30.67#ibcon#*before return 0, iclass 37, count 0 2006.175.07:45:30.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:45:30.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:45:30.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:45:30.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:45:30.67$vc4f8/vblo=1,632.99 2006.175.07:45:30.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.07:45:30.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.07:45:30.67#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:30.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:45:30.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:45:30.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:45:30.67#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:45:30.67#ibcon#first serial, iclass 39, count 0 2006.175.07:45:30.67#ibcon#enter sib2, iclass 39, count 0 2006.175.07:45:30.67#ibcon#flushed, iclass 39, count 0 2006.175.07:45:30.67#ibcon#about to write, iclass 39, count 0 2006.175.07:45:30.67#ibcon#wrote, iclass 39, count 0 2006.175.07:45:30.67#ibcon#about to read 3, iclass 39, count 0 2006.175.07:45:30.69#ibcon#read 3, iclass 39, count 0 2006.175.07:45:30.69#ibcon#about to read 4, iclass 39, count 0 2006.175.07:45:30.69#ibcon#read 4, iclass 39, count 0 2006.175.07:45:30.69#ibcon#about to read 5, iclass 39, count 0 2006.175.07:45:30.69#ibcon#read 5, iclass 39, count 0 2006.175.07:45:30.69#ibcon#about to read 6, iclass 39, count 0 2006.175.07:45:30.69#ibcon#read 6, iclass 39, count 0 2006.175.07:45:30.69#ibcon#end of sib2, iclass 39, count 0 2006.175.07:45:30.69#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:45:30.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:45:30.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:45:30.69#ibcon#*before write, iclass 39, count 0 2006.175.07:45:30.69#ibcon#enter sib2, iclass 39, count 0 2006.175.07:45:30.69#ibcon#flushed, iclass 39, count 0 2006.175.07:45:30.69#ibcon#about to write, iclass 39, count 0 2006.175.07:45:30.69#ibcon#wrote, iclass 39, count 0 2006.175.07:45:30.69#ibcon#about to read 3, iclass 39, count 0 2006.175.07:45:30.73#ibcon#read 3, iclass 39, count 0 2006.175.07:45:30.73#ibcon#about to read 4, iclass 39, count 0 2006.175.07:45:30.73#ibcon#read 4, iclass 39, count 0 2006.175.07:45:30.73#ibcon#about to read 5, iclass 39, count 0 2006.175.07:45:30.73#ibcon#read 5, iclass 39, count 0 2006.175.07:45:30.73#ibcon#about to read 6, iclass 39, count 0 2006.175.07:45:30.73#ibcon#read 6, iclass 39, count 0 2006.175.07:45:30.73#ibcon#end of sib2, iclass 39, count 0 2006.175.07:45:30.73#ibcon#*after write, iclass 39, count 0 2006.175.07:45:30.73#ibcon#*before return 0, iclass 39, count 0 2006.175.07:45:30.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:45:30.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:45:30.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:45:30.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:45:30.73$vc4f8/vb=1,4 2006.175.07:45:30.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.07:45:30.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.07:45:30.73#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:30.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:45:30.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:45:30.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:45:30.73#ibcon#enter wrdev, iclass 3, count 2 2006.175.07:45:30.73#ibcon#first serial, iclass 3, count 2 2006.175.07:45:30.73#ibcon#enter sib2, iclass 3, count 2 2006.175.07:45:30.73#ibcon#flushed, iclass 3, count 2 2006.175.07:45:30.73#ibcon#about to write, iclass 3, count 2 2006.175.07:45:30.73#ibcon#wrote, iclass 3, count 2 2006.175.07:45:30.73#ibcon#about to read 3, iclass 3, count 2 2006.175.07:45:30.75#ibcon#read 3, iclass 3, count 2 2006.175.07:45:30.75#ibcon#about to read 4, iclass 3, count 2 2006.175.07:45:30.75#ibcon#read 4, iclass 3, count 2 2006.175.07:45:30.75#ibcon#about to read 5, iclass 3, count 2 2006.175.07:45:30.75#ibcon#read 5, iclass 3, count 2 2006.175.07:45:30.75#ibcon#about to read 6, iclass 3, count 2 2006.175.07:45:30.75#ibcon#read 6, iclass 3, count 2 2006.175.07:45:30.75#ibcon#end of sib2, iclass 3, count 2 2006.175.07:45:30.75#ibcon#*mode == 0, iclass 3, count 2 2006.175.07:45:30.75#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.07:45:30.75#ibcon#[27=AT01-04\r\n] 2006.175.07:45:30.75#ibcon#*before write, iclass 3, count 2 2006.175.07:45:30.75#ibcon#enter sib2, iclass 3, count 2 2006.175.07:45:30.75#ibcon#flushed, iclass 3, count 2 2006.175.07:45:30.75#ibcon#about to write, iclass 3, count 2 2006.175.07:45:30.75#ibcon#wrote, iclass 3, count 2 2006.175.07:45:30.75#ibcon#about to read 3, iclass 3, count 2 2006.175.07:45:30.78#ibcon#read 3, iclass 3, count 2 2006.175.07:45:30.78#ibcon#about to read 4, iclass 3, count 2 2006.175.07:45:30.78#ibcon#read 4, iclass 3, count 2 2006.175.07:45:30.78#ibcon#about to read 5, iclass 3, count 2 2006.175.07:45:30.78#ibcon#read 5, iclass 3, count 2 2006.175.07:45:30.78#ibcon#about to read 6, iclass 3, count 2 2006.175.07:45:30.78#ibcon#read 6, iclass 3, count 2 2006.175.07:45:30.78#ibcon#end of sib2, iclass 3, count 2 2006.175.07:45:30.78#ibcon#*after write, iclass 3, count 2 2006.175.07:45:30.78#ibcon#*before return 0, iclass 3, count 2 2006.175.07:45:30.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:45:30.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:45:30.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.07:45:30.78#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:30.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:45:30.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:45:30.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:45:30.90#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:45:30.90#ibcon#first serial, iclass 3, count 0 2006.175.07:45:30.90#ibcon#enter sib2, iclass 3, count 0 2006.175.07:45:30.90#ibcon#flushed, iclass 3, count 0 2006.175.07:45:30.90#ibcon#about to write, iclass 3, count 0 2006.175.07:45:30.90#ibcon#wrote, iclass 3, count 0 2006.175.07:45:30.90#ibcon#about to read 3, iclass 3, count 0 2006.175.07:45:30.92#ibcon#read 3, iclass 3, count 0 2006.175.07:45:30.92#ibcon#about to read 4, iclass 3, count 0 2006.175.07:45:30.92#ibcon#read 4, iclass 3, count 0 2006.175.07:45:30.92#ibcon#about to read 5, iclass 3, count 0 2006.175.07:45:30.92#ibcon#read 5, iclass 3, count 0 2006.175.07:45:30.92#ibcon#about to read 6, iclass 3, count 0 2006.175.07:45:30.92#ibcon#read 6, iclass 3, count 0 2006.175.07:45:30.92#ibcon#end of sib2, iclass 3, count 0 2006.175.07:45:30.92#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:45:30.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:45:30.92#ibcon#[27=USB\r\n] 2006.175.07:45:30.92#ibcon#*before write, iclass 3, count 0 2006.175.07:45:30.92#ibcon#enter sib2, iclass 3, count 0 2006.175.07:45:30.92#ibcon#flushed, iclass 3, count 0 2006.175.07:45:30.92#ibcon#about to write, iclass 3, count 0 2006.175.07:45:30.92#ibcon#wrote, iclass 3, count 0 2006.175.07:45:30.92#ibcon#about to read 3, iclass 3, count 0 2006.175.07:45:30.95#ibcon#read 3, iclass 3, count 0 2006.175.07:45:30.95#ibcon#about to read 4, iclass 3, count 0 2006.175.07:45:30.95#ibcon#read 4, iclass 3, count 0 2006.175.07:45:30.95#ibcon#about to read 5, iclass 3, count 0 2006.175.07:45:30.95#ibcon#read 5, iclass 3, count 0 2006.175.07:45:30.95#ibcon#about to read 6, iclass 3, count 0 2006.175.07:45:30.95#ibcon#read 6, iclass 3, count 0 2006.175.07:45:30.95#ibcon#end of sib2, iclass 3, count 0 2006.175.07:45:30.95#ibcon#*after write, iclass 3, count 0 2006.175.07:45:30.95#ibcon#*before return 0, iclass 3, count 0 2006.175.07:45:30.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:45:30.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:45:30.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:45:30.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:45:30.95$vc4f8/vblo=2,640.99 2006.175.07:45:30.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.07:45:30.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.07:45:30.95#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:30.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:30.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:30.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:30.95#ibcon#enter wrdev, iclass 5, count 0 2006.175.07:45:30.95#ibcon#first serial, iclass 5, count 0 2006.175.07:45:30.95#ibcon#enter sib2, iclass 5, count 0 2006.175.07:45:30.95#ibcon#flushed, iclass 5, count 0 2006.175.07:45:30.95#ibcon#about to write, iclass 5, count 0 2006.175.07:45:30.95#ibcon#wrote, iclass 5, count 0 2006.175.07:45:30.95#ibcon#about to read 3, iclass 5, count 0 2006.175.07:45:30.97#ibcon#read 3, iclass 5, count 0 2006.175.07:45:30.97#ibcon#about to read 4, iclass 5, count 0 2006.175.07:45:30.97#ibcon#read 4, iclass 5, count 0 2006.175.07:45:30.97#ibcon#about to read 5, iclass 5, count 0 2006.175.07:45:30.97#ibcon#read 5, iclass 5, count 0 2006.175.07:45:30.97#ibcon#about to read 6, iclass 5, count 0 2006.175.07:45:30.97#ibcon#read 6, iclass 5, count 0 2006.175.07:45:30.97#ibcon#end of sib2, iclass 5, count 0 2006.175.07:45:30.97#ibcon#*mode == 0, iclass 5, count 0 2006.175.07:45:30.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.07:45:30.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:45:30.97#ibcon#*before write, iclass 5, count 0 2006.175.07:45:30.97#ibcon#enter sib2, iclass 5, count 0 2006.175.07:45:30.97#ibcon#flushed, iclass 5, count 0 2006.175.07:45:30.97#ibcon#about to write, iclass 5, count 0 2006.175.07:45:30.97#ibcon#wrote, iclass 5, count 0 2006.175.07:45:30.97#ibcon#about to read 3, iclass 5, count 0 2006.175.07:45:31.01#ibcon#read 3, iclass 5, count 0 2006.175.07:45:31.01#ibcon#about to read 4, iclass 5, count 0 2006.175.07:45:31.01#ibcon#read 4, iclass 5, count 0 2006.175.07:45:31.01#ibcon#about to read 5, iclass 5, count 0 2006.175.07:45:31.01#ibcon#read 5, iclass 5, count 0 2006.175.07:45:31.01#ibcon#about to read 6, iclass 5, count 0 2006.175.07:45:31.01#ibcon#read 6, iclass 5, count 0 2006.175.07:45:31.01#ibcon#end of sib2, iclass 5, count 0 2006.175.07:45:31.01#ibcon#*after write, iclass 5, count 0 2006.175.07:45:31.01#ibcon#*before return 0, iclass 5, count 0 2006.175.07:45:31.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:31.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:45:31.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.07:45:31.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.07:45:31.01$vc4f8/vb=2,4 2006.175.07:45:31.01#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.07:45:31.01#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.07:45:31.01#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:31.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:31.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:31.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:31.07#ibcon#enter wrdev, iclass 7, count 2 2006.175.07:45:31.07#ibcon#first serial, iclass 7, count 2 2006.175.07:45:31.07#ibcon#enter sib2, iclass 7, count 2 2006.175.07:45:31.07#ibcon#flushed, iclass 7, count 2 2006.175.07:45:31.07#ibcon#about to write, iclass 7, count 2 2006.175.07:45:31.07#ibcon#wrote, iclass 7, count 2 2006.175.07:45:31.07#ibcon#about to read 3, iclass 7, count 2 2006.175.07:45:31.09#ibcon#read 3, iclass 7, count 2 2006.175.07:45:31.09#ibcon#about to read 4, iclass 7, count 2 2006.175.07:45:31.09#ibcon#read 4, iclass 7, count 2 2006.175.07:45:31.09#ibcon#about to read 5, iclass 7, count 2 2006.175.07:45:31.09#ibcon#read 5, iclass 7, count 2 2006.175.07:45:31.09#ibcon#about to read 6, iclass 7, count 2 2006.175.07:45:31.09#ibcon#read 6, iclass 7, count 2 2006.175.07:45:31.09#ibcon#end of sib2, iclass 7, count 2 2006.175.07:45:31.09#ibcon#*mode == 0, iclass 7, count 2 2006.175.07:45:31.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.07:45:31.09#ibcon#[27=AT02-04\r\n] 2006.175.07:45:31.09#ibcon#*before write, iclass 7, count 2 2006.175.07:45:31.09#ibcon#enter sib2, iclass 7, count 2 2006.175.07:45:31.09#ibcon#flushed, iclass 7, count 2 2006.175.07:45:31.09#ibcon#about to write, iclass 7, count 2 2006.175.07:45:31.09#ibcon#wrote, iclass 7, count 2 2006.175.07:45:31.09#ibcon#about to read 3, iclass 7, count 2 2006.175.07:45:31.12#ibcon#read 3, iclass 7, count 2 2006.175.07:45:31.12#ibcon#about to read 4, iclass 7, count 2 2006.175.07:45:31.12#ibcon#read 4, iclass 7, count 2 2006.175.07:45:31.12#ibcon#about to read 5, iclass 7, count 2 2006.175.07:45:31.12#ibcon#read 5, iclass 7, count 2 2006.175.07:45:31.12#ibcon#about to read 6, iclass 7, count 2 2006.175.07:45:31.12#ibcon#read 6, iclass 7, count 2 2006.175.07:45:31.12#ibcon#end of sib2, iclass 7, count 2 2006.175.07:45:31.12#ibcon#*after write, iclass 7, count 2 2006.175.07:45:31.12#ibcon#*before return 0, iclass 7, count 2 2006.175.07:45:31.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:31.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:45:31.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.07:45:31.12#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:31.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:31.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:31.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:31.24#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:45:31.24#ibcon#first serial, iclass 7, count 0 2006.175.07:45:31.24#ibcon#enter sib2, iclass 7, count 0 2006.175.07:45:31.24#ibcon#flushed, iclass 7, count 0 2006.175.07:45:31.24#ibcon#about to write, iclass 7, count 0 2006.175.07:45:31.24#ibcon#wrote, iclass 7, count 0 2006.175.07:45:31.24#ibcon#about to read 3, iclass 7, count 0 2006.175.07:45:31.26#ibcon#read 3, iclass 7, count 0 2006.175.07:45:31.26#ibcon#about to read 4, iclass 7, count 0 2006.175.07:45:31.26#ibcon#read 4, iclass 7, count 0 2006.175.07:45:31.26#ibcon#about to read 5, iclass 7, count 0 2006.175.07:45:31.26#ibcon#read 5, iclass 7, count 0 2006.175.07:45:31.26#ibcon#about to read 6, iclass 7, count 0 2006.175.07:45:31.26#ibcon#read 6, iclass 7, count 0 2006.175.07:45:31.26#ibcon#end of sib2, iclass 7, count 0 2006.175.07:45:31.26#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:45:31.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:45:31.26#ibcon#[27=USB\r\n] 2006.175.07:45:31.26#ibcon#*before write, iclass 7, count 0 2006.175.07:45:31.26#ibcon#enter sib2, iclass 7, count 0 2006.175.07:45:31.26#ibcon#flushed, iclass 7, count 0 2006.175.07:45:31.26#ibcon#about to write, iclass 7, count 0 2006.175.07:45:31.26#ibcon#wrote, iclass 7, count 0 2006.175.07:45:31.26#ibcon#about to read 3, iclass 7, count 0 2006.175.07:45:31.29#ibcon#read 3, iclass 7, count 0 2006.175.07:45:31.29#ibcon#about to read 4, iclass 7, count 0 2006.175.07:45:31.29#ibcon#read 4, iclass 7, count 0 2006.175.07:45:31.29#ibcon#about to read 5, iclass 7, count 0 2006.175.07:45:31.29#ibcon#read 5, iclass 7, count 0 2006.175.07:45:31.29#ibcon#about to read 6, iclass 7, count 0 2006.175.07:45:31.29#ibcon#read 6, iclass 7, count 0 2006.175.07:45:31.29#ibcon#end of sib2, iclass 7, count 0 2006.175.07:45:31.29#ibcon#*after write, iclass 7, count 0 2006.175.07:45:31.29#ibcon#*before return 0, iclass 7, count 0 2006.175.07:45:31.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:31.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:45:31.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:45:31.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:45:31.29$vc4f8/vblo=3,656.99 2006.175.07:45:31.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.07:45:31.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.07:45:31.29#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:31.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:31.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:31.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:31.29#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:45:31.29#ibcon#first serial, iclass 11, count 0 2006.175.07:45:31.29#ibcon#enter sib2, iclass 11, count 0 2006.175.07:45:31.29#ibcon#flushed, iclass 11, count 0 2006.175.07:45:31.29#ibcon#about to write, iclass 11, count 0 2006.175.07:45:31.29#ibcon#wrote, iclass 11, count 0 2006.175.07:45:31.29#ibcon#about to read 3, iclass 11, count 0 2006.175.07:45:31.31#ibcon#read 3, iclass 11, count 0 2006.175.07:45:31.31#ibcon#about to read 4, iclass 11, count 0 2006.175.07:45:31.31#ibcon#read 4, iclass 11, count 0 2006.175.07:45:31.31#ibcon#about to read 5, iclass 11, count 0 2006.175.07:45:31.31#ibcon#read 5, iclass 11, count 0 2006.175.07:45:31.31#ibcon#about to read 6, iclass 11, count 0 2006.175.07:45:31.31#ibcon#read 6, iclass 11, count 0 2006.175.07:45:31.31#ibcon#end of sib2, iclass 11, count 0 2006.175.07:45:31.31#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:45:31.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:45:31.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:45:31.31#ibcon#*before write, iclass 11, count 0 2006.175.07:45:31.31#ibcon#enter sib2, iclass 11, count 0 2006.175.07:45:31.31#ibcon#flushed, iclass 11, count 0 2006.175.07:45:31.31#ibcon#about to write, iclass 11, count 0 2006.175.07:45:31.31#ibcon#wrote, iclass 11, count 0 2006.175.07:45:31.31#ibcon#about to read 3, iclass 11, count 0 2006.175.07:45:31.35#ibcon#read 3, iclass 11, count 0 2006.175.07:45:31.35#ibcon#about to read 4, iclass 11, count 0 2006.175.07:45:31.35#ibcon#read 4, iclass 11, count 0 2006.175.07:45:31.35#ibcon#about to read 5, iclass 11, count 0 2006.175.07:45:31.35#ibcon#read 5, iclass 11, count 0 2006.175.07:45:31.35#ibcon#about to read 6, iclass 11, count 0 2006.175.07:45:31.35#ibcon#read 6, iclass 11, count 0 2006.175.07:45:31.35#ibcon#end of sib2, iclass 11, count 0 2006.175.07:45:31.35#ibcon#*after write, iclass 11, count 0 2006.175.07:45:31.35#ibcon#*before return 0, iclass 11, count 0 2006.175.07:45:31.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:31.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:45:31.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:45:31.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:45:31.35$vc4f8/vb=3,4 2006.175.07:45:31.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.07:45:31.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.07:45:31.35#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:31.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:31.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:31.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:31.41#ibcon#enter wrdev, iclass 13, count 2 2006.175.07:45:31.41#ibcon#first serial, iclass 13, count 2 2006.175.07:45:31.41#ibcon#enter sib2, iclass 13, count 2 2006.175.07:45:31.41#ibcon#flushed, iclass 13, count 2 2006.175.07:45:31.41#ibcon#about to write, iclass 13, count 2 2006.175.07:45:31.41#ibcon#wrote, iclass 13, count 2 2006.175.07:45:31.41#ibcon#about to read 3, iclass 13, count 2 2006.175.07:45:31.43#ibcon#read 3, iclass 13, count 2 2006.175.07:45:31.43#ibcon#about to read 4, iclass 13, count 2 2006.175.07:45:31.43#ibcon#read 4, iclass 13, count 2 2006.175.07:45:31.43#ibcon#about to read 5, iclass 13, count 2 2006.175.07:45:31.43#ibcon#read 5, iclass 13, count 2 2006.175.07:45:31.43#ibcon#about to read 6, iclass 13, count 2 2006.175.07:45:31.43#ibcon#read 6, iclass 13, count 2 2006.175.07:45:31.43#ibcon#end of sib2, iclass 13, count 2 2006.175.07:45:31.43#ibcon#*mode == 0, iclass 13, count 2 2006.175.07:45:31.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.07:45:31.43#ibcon#[27=AT03-04\r\n] 2006.175.07:45:31.43#ibcon#*before write, iclass 13, count 2 2006.175.07:45:31.43#ibcon#enter sib2, iclass 13, count 2 2006.175.07:45:31.43#ibcon#flushed, iclass 13, count 2 2006.175.07:45:31.43#ibcon#about to write, iclass 13, count 2 2006.175.07:45:31.43#ibcon#wrote, iclass 13, count 2 2006.175.07:45:31.43#ibcon#about to read 3, iclass 13, count 2 2006.175.07:45:31.46#ibcon#read 3, iclass 13, count 2 2006.175.07:45:31.46#ibcon#about to read 4, iclass 13, count 2 2006.175.07:45:31.46#ibcon#read 4, iclass 13, count 2 2006.175.07:45:31.46#ibcon#about to read 5, iclass 13, count 2 2006.175.07:45:31.46#ibcon#read 5, iclass 13, count 2 2006.175.07:45:31.46#ibcon#about to read 6, iclass 13, count 2 2006.175.07:45:31.46#ibcon#read 6, iclass 13, count 2 2006.175.07:45:31.46#ibcon#end of sib2, iclass 13, count 2 2006.175.07:45:31.46#ibcon#*after write, iclass 13, count 2 2006.175.07:45:31.46#ibcon#*before return 0, iclass 13, count 2 2006.175.07:45:31.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:31.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:45:31.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.07:45:31.46#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:31.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:31.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:31.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:31.58#ibcon#enter wrdev, iclass 13, count 0 2006.175.07:45:31.58#ibcon#first serial, iclass 13, count 0 2006.175.07:45:31.58#ibcon#enter sib2, iclass 13, count 0 2006.175.07:45:31.58#ibcon#flushed, iclass 13, count 0 2006.175.07:45:31.58#ibcon#about to write, iclass 13, count 0 2006.175.07:45:31.58#ibcon#wrote, iclass 13, count 0 2006.175.07:45:31.58#ibcon#about to read 3, iclass 13, count 0 2006.175.07:45:31.60#ibcon#read 3, iclass 13, count 0 2006.175.07:45:31.60#ibcon#about to read 4, iclass 13, count 0 2006.175.07:45:31.60#ibcon#read 4, iclass 13, count 0 2006.175.07:45:31.60#ibcon#about to read 5, iclass 13, count 0 2006.175.07:45:31.60#ibcon#read 5, iclass 13, count 0 2006.175.07:45:31.60#ibcon#about to read 6, iclass 13, count 0 2006.175.07:45:31.60#ibcon#read 6, iclass 13, count 0 2006.175.07:45:31.60#ibcon#end of sib2, iclass 13, count 0 2006.175.07:45:31.60#ibcon#*mode == 0, iclass 13, count 0 2006.175.07:45:31.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.07:45:31.60#ibcon#[27=USB\r\n] 2006.175.07:45:31.60#ibcon#*before write, iclass 13, count 0 2006.175.07:45:31.60#ibcon#enter sib2, iclass 13, count 0 2006.175.07:45:31.60#ibcon#flushed, iclass 13, count 0 2006.175.07:45:31.60#ibcon#about to write, iclass 13, count 0 2006.175.07:45:31.60#ibcon#wrote, iclass 13, count 0 2006.175.07:45:31.60#ibcon#about to read 3, iclass 13, count 0 2006.175.07:45:31.63#ibcon#read 3, iclass 13, count 0 2006.175.07:45:31.63#ibcon#about to read 4, iclass 13, count 0 2006.175.07:45:31.63#ibcon#read 4, iclass 13, count 0 2006.175.07:45:31.63#ibcon#about to read 5, iclass 13, count 0 2006.175.07:45:31.63#ibcon#read 5, iclass 13, count 0 2006.175.07:45:31.63#ibcon#about to read 6, iclass 13, count 0 2006.175.07:45:31.63#ibcon#read 6, iclass 13, count 0 2006.175.07:45:31.63#ibcon#end of sib2, iclass 13, count 0 2006.175.07:45:31.63#ibcon#*after write, iclass 13, count 0 2006.175.07:45:31.63#ibcon#*before return 0, iclass 13, count 0 2006.175.07:45:31.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:31.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:45:31.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.07:45:31.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.07:45:31.63$vc4f8/vblo=4,712.99 2006.175.07:45:31.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.07:45:31.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.07:45:31.63#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:31.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:31.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:31.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:31.63#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:45:31.63#ibcon#first serial, iclass 15, count 0 2006.175.07:45:31.63#ibcon#enter sib2, iclass 15, count 0 2006.175.07:45:31.63#ibcon#flushed, iclass 15, count 0 2006.175.07:45:31.63#ibcon#about to write, iclass 15, count 0 2006.175.07:45:31.63#ibcon#wrote, iclass 15, count 0 2006.175.07:45:31.63#ibcon#about to read 3, iclass 15, count 0 2006.175.07:45:31.65#ibcon#read 3, iclass 15, count 0 2006.175.07:45:31.65#ibcon#about to read 4, iclass 15, count 0 2006.175.07:45:31.65#ibcon#read 4, iclass 15, count 0 2006.175.07:45:31.65#ibcon#about to read 5, iclass 15, count 0 2006.175.07:45:31.65#ibcon#read 5, iclass 15, count 0 2006.175.07:45:31.65#ibcon#about to read 6, iclass 15, count 0 2006.175.07:45:31.65#ibcon#read 6, iclass 15, count 0 2006.175.07:45:31.65#ibcon#end of sib2, iclass 15, count 0 2006.175.07:45:31.65#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:45:31.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:45:31.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:45:31.65#ibcon#*before write, iclass 15, count 0 2006.175.07:45:31.65#ibcon#enter sib2, iclass 15, count 0 2006.175.07:45:31.65#ibcon#flushed, iclass 15, count 0 2006.175.07:45:31.65#ibcon#about to write, iclass 15, count 0 2006.175.07:45:31.65#ibcon#wrote, iclass 15, count 0 2006.175.07:45:31.65#ibcon#about to read 3, iclass 15, count 0 2006.175.07:45:31.69#ibcon#read 3, iclass 15, count 0 2006.175.07:45:31.69#ibcon#about to read 4, iclass 15, count 0 2006.175.07:45:31.69#ibcon#read 4, iclass 15, count 0 2006.175.07:45:31.69#ibcon#about to read 5, iclass 15, count 0 2006.175.07:45:31.69#ibcon#read 5, iclass 15, count 0 2006.175.07:45:31.69#ibcon#about to read 6, iclass 15, count 0 2006.175.07:45:31.69#ibcon#read 6, iclass 15, count 0 2006.175.07:45:31.69#ibcon#end of sib2, iclass 15, count 0 2006.175.07:45:31.69#ibcon#*after write, iclass 15, count 0 2006.175.07:45:31.69#ibcon#*before return 0, iclass 15, count 0 2006.175.07:45:31.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:31.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:45:31.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:45:31.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:45:31.69$vc4f8/vb=4,4 2006.175.07:45:31.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.07:45:31.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.07:45:31.69#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:31.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:31.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:31.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:31.75#ibcon#enter wrdev, iclass 17, count 2 2006.175.07:45:31.75#ibcon#first serial, iclass 17, count 2 2006.175.07:45:31.75#ibcon#enter sib2, iclass 17, count 2 2006.175.07:45:31.75#ibcon#flushed, iclass 17, count 2 2006.175.07:45:31.75#ibcon#about to write, iclass 17, count 2 2006.175.07:45:31.75#ibcon#wrote, iclass 17, count 2 2006.175.07:45:31.75#ibcon#about to read 3, iclass 17, count 2 2006.175.07:45:31.77#ibcon#read 3, iclass 17, count 2 2006.175.07:45:31.77#ibcon#about to read 4, iclass 17, count 2 2006.175.07:45:31.77#ibcon#read 4, iclass 17, count 2 2006.175.07:45:31.77#ibcon#about to read 5, iclass 17, count 2 2006.175.07:45:31.77#ibcon#read 5, iclass 17, count 2 2006.175.07:45:31.77#ibcon#about to read 6, iclass 17, count 2 2006.175.07:45:31.77#ibcon#read 6, iclass 17, count 2 2006.175.07:45:31.77#ibcon#end of sib2, iclass 17, count 2 2006.175.07:45:31.77#ibcon#*mode == 0, iclass 17, count 2 2006.175.07:45:31.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.07:45:31.77#ibcon#[27=AT04-04\r\n] 2006.175.07:45:31.77#ibcon#*before write, iclass 17, count 2 2006.175.07:45:31.77#ibcon#enter sib2, iclass 17, count 2 2006.175.07:45:31.77#ibcon#flushed, iclass 17, count 2 2006.175.07:45:31.77#ibcon#about to write, iclass 17, count 2 2006.175.07:45:31.77#ibcon#wrote, iclass 17, count 2 2006.175.07:45:31.77#ibcon#about to read 3, iclass 17, count 2 2006.175.07:45:31.80#ibcon#read 3, iclass 17, count 2 2006.175.07:45:31.80#ibcon#about to read 4, iclass 17, count 2 2006.175.07:45:31.80#ibcon#read 4, iclass 17, count 2 2006.175.07:45:31.80#ibcon#about to read 5, iclass 17, count 2 2006.175.07:45:31.80#ibcon#read 5, iclass 17, count 2 2006.175.07:45:31.80#ibcon#about to read 6, iclass 17, count 2 2006.175.07:45:31.80#ibcon#read 6, iclass 17, count 2 2006.175.07:45:31.80#ibcon#end of sib2, iclass 17, count 2 2006.175.07:45:31.80#ibcon#*after write, iclass 17, count 2 2006.175.07:45:31.80#ibcon#*before return 0, iclass 17, count 2 2006.175.07:45:31.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:31.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:45:31.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.07:45:31.80#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:31.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:31.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:31.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:31.92#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:45:31.92#ibcon#first serial, iclass 17, count 0 2006.175.07:45:31.92#ibcon#enter sib2, iclass 17, count 0 2006.175.07:45:31.92#ibcon#flushed, iclass 17, count 0 2006.175.07:45:31.92#ibcon#about to write, iclass 17, count 0 2006.175.07:45:31.92#ibcon#wrote, iclass 17, count 0 2006.175.07:45:31.92#ibcon#about to read 3, iclass 17, count 0 2006.175.07:45:31.94#ibcon#read 3, iclass 17, count 0 2006.175.07:45:31.94#ibcon#about to read 4, iclass 17, count 0 2006.175.07:45:31.94#ibcon#read 4, iclass 17, count 0 2006.175.07:45:31.94#ibcon#about to read 5, iclass 17, count 0 2006.175.07:45:31.94#ibcon#read 5, iclass 17, count 0 2006.175.07:45:31.94#ibcon#about to read 6, iclass 17, count 0 2006.175.07:45:31.94#ibcon#read 6, iclass 17, count 0 2006.175.07:45:31.94#ibcon#end of sib2, iclass 17, count 0 2006.175.07:45:31.94#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:45:31.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:45:31.94#ibcon#[27=USB\r\n] 2006.175.07:45:31.94#ibcon#*before write, iclass 17, count 0 2006.175.07:45:31.94#ibcon#enter sib2, iclass 17, count 0 2006.175.07:45:31.94#ibcon#flushed, iclass 17, count 0 2006.175.07:45:31.94#ibcon#about to write, iclass 17, count 0 2006.175.07:45:31.94#ibcon#wrote, iclass 17, count 0 2006.175.07:45:31.94#ibcon#about to read 3, iclass 17, count 0 2006.175.07:45:31.97#ibcon#read 3, iclass 17, count 0 2006.175.07:45:31.97#ibcon#about to read 4, iclass 17, count 0 2006.175.07:45:31.97#ibcon#read 4, iclass 17, count 0 2006.175.07:45:31.97#ibcon#about to read 5, iclass 17, count 0 2006.175.07:45:31.97#ibcon#read 5, iclass 17, count 0 2006.175.07:45:31.97#ibcon#about to read 6, iclass 17, count 0 2006.175.07:45:31.97#ibcon#read 6, iclass 17, count 0 2006.175.07:45:31.97#ibcon#end of sib2, iclass 17, count 0 2006.175.07:45:31.97#ibcon#*after write, iclass 17, count 0 2006.175.07:45:31.97#ibcon#*before return 0, iclass 17, count 0 2006.175.07:45:31.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:31.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:45:31.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:45:31.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:45:31.97$vc4f8/vblo=5,744.99 2006.175.07:45:31.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.07:45:31.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.07:45:31.97#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:31.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:31.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:31.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:31.97#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:45:31.97#ibcon#first serial, iclass 19, count 0 2006.175.07:45:31.97#ibcon#enter sib2, iclass 19, count 0 2006.175.07:45:31.97#ibcon#flushed, iclass 19, count 0 2006.175.07:45:31.97#ibcon#about to write, iclass 19, count 0 2006.175.07:45:31.97#ibcon#wrote, iclass 19, count 0 2006.175.07:45:31.97#ibcon#about to read 3, iclass 19, count 0 2006.175.07:45:31.99#ibcon#read 3, iclass 19, count 0 2006.175.07:45:31.99#ibcon#about to read 4, iclass 19, count 0 2006.175.07:45:31.99#ibcon#read 4, iclass 19, count 0 2006.175.07:45:31.99#ibcon#about to read 5, iclass 19, count 0 2006.175.07:45:31.99#ibcon#read 5, iclass 19, count 0 2006.175.07:45:31.99#ibcon#about to read 6, iclass 19, count 0 2006.175.07:45:31.99#ibcon#read 6, iclass 19, count 0 2006.175.07:45:31.99#ibcon#end of sib2, iclass 19, count 0 2006.175.07:45:31.99#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:45:31.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:45:31.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:45:31.99#ibcon#*before write, iclass 19, count 0 2006.175.07:45:31.99#ibcon#enter sib2, iclass 19, count 0 2006.175.07:45:31.99#ibcon#flushed, iclass 19, count 0 2006.175.07:45:31.99#ibcon#about to write, iclass 19, count 0 2006.175.07:45:31.99#ibcon#wrote, iclass 19, count 0 2006.175.07:45:31.99#ibcon#about to read 3, iclass 19, count 0 2006.175.07:45:32.03#ibcon#read 3, iclass 19, count 0 2006.175.07:45:32.03#ibcon#about to read 4, iclass 19, count 0 2006.175.07:45:32.03#ibcon#read 4, iclass 19, count 0 2006.175.07:45:32.03#ibcon#about to read 5, iclass 19, count 0 2006.175.07:45:32.03#ibcon#read 5, iclass 19, count 0 2006.175.07:45:32.03#ibcon#about to read 6, iclass 19, count 0 2006.175.07:45:32.03#ibcon#read 6, iclass 19, count 0 2006.175.07:45:32.03#ibcon#end of sib2, iclass 19, count 0 2006.175.07:45:32.03#ibcon#*after write, iclass 19, count 0 2006.175.07:45:32.03#ibcon#*before return 0, iclass 19, count 0 2006.175.07:45:32.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:32.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:45:32.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:45:32.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:45:32.03$vc4f8/vb=5,4 2006.175.07:45:32.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.07:45:32.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.07:45:32.03#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:32.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:32.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:32.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:32.09#ibcon#enter wrdev, iclass 21, count 2 2006.175.07:45:32.09#ibcon#first serial, iclass 21, count 2 2006.175.07:45:32.09#ibcon#enter sib2, iclass 21, count 2 2006.175.07:45:32.09#ibcon#flushed, iclass 21, count 2 2006.175.07:45:32.09#ibcon#about to write, iclass 21, count 2 2006.175.07:45:32.09#ibcon#wrote, iclass 21, count 2 2006.175.07:45:32.09#ibcon#about to read 3, iclass 21, count 2 2006.175.07:45:32.11#ibcon#read 3, iclass 21, count 2 2006.175.07:45:32.11#ibcon#about to read 4, iclass 21, count 2 2006.175.07:45:32.11#ibcon#read 4, iclass 21, count 2 2006.175.07:45:32.11#ibcon#about to read 5, iclass 21, count 2 2006.175.07:45:32.11#ibcon#read 5, iclass 21, count 2 2006.175.07:45:32.11#ibcon#about to read 6, iclass 21, count 2 2006.175.07:45:32.11#ibcon#read 6, iclass 21, count 2 2006.175.07:45:32.11#ibcon#end of sib2, iclass 21, count 2 2006.175.07:45:32.11#ibcon#*mode == 0, iclass 21, count 2 2006.175.07:45:32.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.07:45:32.11#ibcon#[27=AT05-04\r\n] 2006.175.07:45:32.11#ibcon#*before write, iclass 21, count 2 2006.175.07:45:32.11#ibcon#enter sib2, iclass 21, count 2 2006.175.07:45:32.11#ibcon#flushed, iclass 21, count 2 2006.175.07:45:32.11#ibcon#about to write, iclass 21, count 2 2006.175.07:45:32.11#ibcon#wrote, iclass 21, count 2 2006.175.07:45:32.11#ibcon#about to read 3, iclass 21, count 2 2006.175.07:45:32.14#ibcon#read 3, iclass 21, count 2 2006.175.07:45:32.14#ibcon#about to read 4, iclass 21, count 2 2006.175.07:45:32.14#ibcon#read 4, iclass 21, count 2 2006.175.07:45:32.14#ibcon#about to read 5, iclass 21, count 2 2006.175.07:45:32.14#ibcon#read 5, iclass 21, count 2 2006.175.07:45:32.14#ibcon#about to read 6, iclass 21, count 2 2006.175.07:45:32.14#ibcon#read 6, iclass 21, count 2 2006.175.07:45:32.14#ibcon#end of sib2, iclass 21, count 2 2006.175.07:45:32.14#ibcon#*after write, iclass 21, count 2 2006.175.07:45:32.14#ibcon#*before return 0, iclass 21, count 2 2006.175.07:45:32.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:32.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:45:32.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.07:45:32.14#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:32.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:32.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:32.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:32.26#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:45:32.26#ibcon#first serial, iclass 21, count 0 2006.175.07:45:32.26#ibcon#enter sib2, iclass 21, count 0 2006.175.07:45:32.26#ibcon#flushed, iclass 21, count 0 2006.175.07:45:32.26#ibcon#about to write, iclass 21, count 0 2006.175.07:45:32.26#ibcon#wrote, iclass 21, count 0 2006.175.07:45:32.26#ibcon#about to read 3, iclass 21, count 0 2006.175.07:45:32.28#ibcon#read 3, iclass 21, count 0 2006.175.07:45:32.28#ibcon#about to read 4, iclass 21, count 0 2006.175.07:45:32.28#ibcon#read 4, iclass 21, count 0 2006.175.07:45:32.28#ibcon#about to read 5, iclass 21, count 0 2006.175.07:45:32.28#ibcon#read 5, iclass 21, count 0 2006.175.07:45:32.28#ibcon#about to read 6, iclass 21, count 0 2006.175.07:45:32.28#ibcon#read 6, iclass 21, count 0 2006.175.07:45:32.28#ibcon#end of sib2, iclass 21, count 0 2006.175.07:45:32.28#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:45:32.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:45:32.28#ibcon#[27=USB\r\n] 2006.175.07:45:32.28#ibcon#*before write, iclass 21, count 0 2006.175.07:45:32.28#ibcon#enter sib2, iclass 21, count 0 2006.175.07:45:32.28#ibcon#flushed, iclass 21, count 0 2006.175.07:45:32.28#ibcon#about to write, iclass 21, count 0 2006.175.07:45:32.28#ibcon#wrote, iclass 21, count 0 2006.175.07:45:32.28#ibcon#about to read 3, iclass 21, count 0 2006.175.07:45:32.31#ibcon#read 3, iclass 21, count 0 2006.175.07:45:32.31#ibcon#about to read 4, iclass 21, count 0 2006.175.07:45:32.31#ibcon#read 4, iclass 21, count 0 2006.175.07:45:32.31#ibcon#about to read 5, iclass 21, count 0 2006.175.07:45:32.31#ibcon#read 5, iclass 21, count 0 2006.175.07:45:32.31#ibcon#about to read 6, iclass 21, count 0 2006.175.07:45:32.31#ibcon#read 6, iclass 21, count 0 2006.175.07:45:32.31#ibcon#end of sib2, iclass 21, count 0 2006.175.07:45:32.31#ibcon#*after write, iclass 21, count 0 2006.175.07:45:32.31#ibcon#*before return 0, iclass 21, count 0 2006.175.07:45:32.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:32.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:45:32.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:45:32.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:45:32.31$vc4f8/vblo=6,752.99 2006.175.07:45:32.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.07:45:32.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.07:45:32.31#ibcon#ireg 17 cls_cnt 0 2006.175.07:45:32.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:32.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:32.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:32.31#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:45:32.31#ibcon#first serial, iclass 23, count 0 2006.175.07:45:32.31#ibcon#enter sib2, iclass 23, count 0 2006.175.07:45:32.31#ibcon#flushed, iclass 23, count 0 2006.175.07:45:32.31#ibcon#about to write, iclass 23, count 0 2006.175.07:45:32.31#ibcon#wrote, iclass 23, count 0 2006.175.07:45:32.31#ibcon#about to read 3, iclass 23, count 0 2006.175.07:45:32.33#ibcon#read 3, iclass 23, count 0 2006.175.07:45:32.33#ibcon#about to read 4, iclass 23, count 0 2006.175.07:45:32.33#ibcon#read 4, iclass 23, count 0 2006.175.07:45:32.33#ibcon#about to read 5, iclass 23, count 0 2006.175.07:45:32.33#ibcon#read 5, iclass 23, count 0 2006.175.07:45:32.33#ibcon#about to read 6, iclass 23, count 0 2006.175.07:45:32.33#ibcon#read 6, iclass 23, count 0 2006.175.07:45:32.33#ibcon#end of sib2, iclass 23, count 0 2006.175.07:45:32.33#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:45:32.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:45:32.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:45:32.33#ibcon#*before write, iclass 23, count 0 2006.175.07:45:32.33#ibcon#enter sib2, iclass 23, count 0 2006.175.07:45:32.33#ibcon#flushed, iclass 23, count 0 2006.175.07:45:32.33#ibcon#about to write, iclass 23, count 0 2006.175.07:45:32.33#ibcon#wrote, iclass 23, count 0 2006.175.07:45:32.33#ibcon#about to read 3, iclass 23, count 0 2006.175.07:45:32.37#ibcon#read 3, iclass 23, count 0 2006.175.07:45:32.37#ibcon#about to read 4, iclass 23, count 0 2006.175.07:45:32.37#ibcon#read 4, iclass 23, count 0 2006.175.07:45:32.37#ibcon#about to read 5, iclass 23, count 0 2006.175.07:45:32.37#ibcon#read 5, iclass 23, count 0 2006.175.07:45:32.37#ibcon#about to read 6, iclass 23, count 0 2006.175.07:45:32.37#ibcon#read 6, iclass 23, count 0 2006.175.07:45:32.37#ibcon#end of sib2, iclass 23, count 0 2006.175.07:45:32.37#ibcon#*after write, iclass 23, count 0 2006.175.07:45:32.37#ibcon#*before return 0, iclass 23, count 0 2006.175.07:45:32.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:32.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:45:32.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:45:32.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:45:32.37$vc4f8/vb=6,4 2006.175.07:45:32.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.07:45:32.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.07:45:32.37#ibcon#ireg 11 cls_cnt 2 2006.175.07:45:32.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:32.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:32.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:32.43#ibcon#enter wrdev, iclass 25, count 2 2006.175.07:45:32.43#ibcon#first serial, iclass 25, count 2 2006.175.07:45:32.43#ibcon#enter sib2, iclass 25, count 2 2006.175.07:45:32.43#ibcon#flushed, iclass 25, count 2 2006.175.07:45:32.43#ibcon#about to write, iclass 25, count 2 2006.175.07:45:32.43#ibcon#wrote, iclass 25, count 2 2006.175.07:45:32.43#ibcon#about to read 3, iclass 25, count 2 2006.175.07:45:32.45#ibcon#read 3, iclass 25, count 2 2006.175.07:45:32.45#ibcon#about to read 4, iclass 25, count 2 2006.175.07:45:32.45#ibcon#read 4, iclass 25, count 2 2006.175.07:45:32.45#ibcon#about to read 5, iclass 25, count 2 2006.175.07:45:32.45#ibcon#read 5, iclass 25, count 2 2006.175.07:45:32.45#ibcon#about to read 6, iclass 25, count 2 2006.175.07:45:32.45#ibcon#read 6, iclass 25, count 2 2006.175.07:45:32.45#ibcon#end of sib2, iclass 25, count 2 2006.175.07:45:32.45#ibcon#*mode == 0, iclass 25, count 2 2006.175.07:45:32.45#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.07:45:32.45#ibcon#[27=AT06-04\r\n] 2006.175.07:45:32.45#ibcon#*before write, iclass 25, count 2 2006.175.07:45:32.45#ibcon#enter sib2, iclass 25, count 2 2006.175.07:45:32.45#ibcon#flushed, iclass 25, count 2 2006.175.07:45:32.45#ibcon#about to write, iclass 25, count 2 2006.175.07:45:32.45#ibcon#wrote, iclass 25, count 2 2006.175.07:45:32.45#ibcon#about to read 3, iclass 25, count 2 2006.175.07:45:32.48#ibcon#read 3, iclass 25, count 2 2006.175.07:45:32.48#ibcon#about to read 4, iclass 25, count 2 2006.175.07:45:32.48#ibcon#read 4, iclass 25, count 2 2006.175.07:45:32.48#ibcon#about to read 5, iclass 25, count 2 2006.175.07:45:32.48#ibcon#read 5, iclass 25, count 2 2006.175.07:45:32.48#ibcon#about to read 6, iclass 25, count 2 2006.175.07:45:32.48#ibcon#read 6, iclass 25, count 2 2006.175.07:45:32.48#ibcon#end of sib2, iclass 25, count 2 2006.175.07:45:32.48#ibcon#*after write, iclass 25, count 2 2006.175.07:45:32.48#ibcon#*before return 0, iclass 25, count 2 2006.175.07:45:32.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:32.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:45:32.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.07:45:32.48#ibcon#ireg 7 cls_cnt 0 2006.175.07:45:32.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:32.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:32.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:32.60#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:45:32.60#ibcon#first serial, iclass 25, count 0 2006.175.07:45:32.60#ibcon#enter sib2, iclass 25, count 0 2006.175.07:45:32.60#ibcon#flushed, iclass 25, count 0 2006.175.07:45:32.60#ibcon#about to write, iclass 25, count 0 2006.175.07:45:32.60#ibcon#wrote, iclass 25, count 0 2006.175.07:45:32.60#ibcon#about to read 3, iclass 25, count 0 2006.175.07:45:32.62#ibcon#read 3, iclass 25, count 0 2006.175.07:45:32.62#ibcon#about to read 4, iclass 25, count 0 2006.175.07:45:32.62#ibcon#read 4, iclass 25, count 0 2006.175.07:45:32.62#ibcon#about to read 5, iclass 25, count 0 2006.175.07:45:32.62#ibcon#read 5, iclass 25, count 0 2006.175.07:45:32.62#ibcon#about to read 6, iclass 25, count 0 2006.175.07:45:32.62#ibcon#read 6, iclass 25, count 0 2006.175.07:45:32.62#ibcon#end of sib2, iclass 25, count 0 2006.175.07:45:32.62#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:45:32.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:45:32.62#ibcon#[27=USB\r\n] 2006.175.07:45:32.62#ibcon#*before write, iclass 25, count 0 2006.175.07:45:32.62#ibcon#enter sib2, iclass 25, count 0 2006.175.07:45:32.62#ibcon#flushed, iclass 25, count 0 2006.175.07:45:32.62#ibcon#about to write, iclass 25, count 0 2006.175.07:45:32.62#ibcon#wrote, iclass 25, count 0 2006.175.07:45:32.62#ibcon#about to read 3, iclass 25, count 0 2006.175.07:45:32.65#ibcon#read 3, iclass 25, count 0 2006.175.07:45:32.65#ibcon#about to read 4, iclass 25, count 0 2006.175.07:45:32.65#ibcon#read 4, iclass 25, count 0 2006.175.07:45:32.65#ibcon#about to read 5, iclass 25, count 0 2006.175.07:45:32.65#ibcon#read 5, iclass 25, count 0 2006.175.07:45:32.65#ibcon#about to read 6, iclass 25, count 0 2006.175.07:45:32.65#ibcon#read 6, iclass 25, count 0 2006.175.07:45:32.65#ibcon#end of sib2, iclass 25, count 0 2006.175.07:45:32.65#ibcon#*after write, iclass 25, count 0 2006.175.07:45:32.65#ibcon#*before return 0, iclass 25, count 0 2006.175.07:45:32.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:32.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:45:32.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:45:32.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:45:32.65$vc4f8/vabw=wide 2006.175.07:45:32.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.07:45:32.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.07:45:32.65#ibcon#ireg 8 cls_cnt 0 2006.175.07:45:32.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:32.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:32.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:32.65#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:45:32.65#ibcon#first serial, iclass 27, count 0 2006.175.07:45:32.65#ibcon#enter sib2, iclass 27, count 0 2006.175.07:45:32.65#ibcon#flushed, iclass 27, count 0 2006.175.07:45:32.65#ibcon#about to write, iclass 27, count 0 2006.175.07:45:32.65#ibcon#wrote, iclass 27, count 0 2006.175.07:45:32.65#ibcon#about to read 3, iclass 27, count 0 2006.175.07:45:32.67#ibcon#read 3, iclass 27, count 0 2006.175.07:45:32.67#ibcon#about to read 4, iclass 27, count 0 2006.175.07:45:32.67#ibcon#read 4, iclass 27, count 0 2006.175.07:45:32.67#ibcon#about to read 5, iclass 27, count 0 2006.175.07:45:32.67#ibcon#read 5, iclass 27, count 0 2006.175.07:45:32.67#ibcon#about to read 6, iclass 27, count 0 2006.175.07:45:32.67#ibcon#read 6, iclass 27, count 0 2006.175.07:45:32.67#ibcon#end of sib2, iclass 27, count 0 2006.175.07:45:32.67#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:45:32.67#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:45:32.67#ibcon#[25=BW32\r\n] 2006.175.07:45:32.67#ibcon#*before write, iclass 27, count 0 2006.175.07:45:32.67#ibcon#enter sib2, iclass 27, count 0 2006.175.07:45:32.67#ibcon#flushed, iclass 27, count 0 2006.175.07:45:32.67#ibcon#about to write, iclass 27, count 0 2006.175.07:45:32.67#ibcon#wrote, iclass 27, count 0 2006.175.07:45:32.67#ibcon#about to read 3, iclass 27, count 0 2006.175.07:45:32.70#ibcon#read 3, iclass 27, count 0 2006.175.07:45:32.70#ibcon#about to read 4, iclass 27, count 0 2006.175.07:45:32.70#ibcon#read 4, iclass 27, count 0 2006.175.07:45:32.70#ibcon#about to read 5, iclass 27, count 0 2006.175.07:45:32.70#ibcon#read 5, iclass 27, count 0 2006.175.07:45:32.70#ibcon#about to read 6, iclass 27, count 0 2006.175.07:45:32.70#ibcon#read 6, iclass 27, count 0 2006.175.07:45:32.70#ibcon#end of sib2, iclass 27, count 0 2006.175.07:45:32.70#ibcon#*after write, iclass 27, count 0 2006.175.07:45:32.70#ibcon#*before return 0, iclass 27, count 0 2006.175.07:45:32.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:32.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:45:32.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:45:32.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:45:32.70$vc4f8/vbbw=wide 2006.175.07:45:32.70#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.07:45:32.70#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.07:45:32.70#ibcon#ireg 8 cls_cnt 0 2006.175.07:45:32.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:45:32.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:45:32.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:45:32.77#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:45:32.77#ibcon#first serial, iclass 29, count 0 2006.175.07:45:32.77#ibcon#enter sib2, iclass 29, count 0 2006.175.07:45:32.77#ibcon#flushed, iclass 29, count 0 2006.175.07:45:32.77#ibcon#about to write, iclass 29, count 0 2006.175.07:45:32.77#ibcon#wrote, iclass 29, count 0 2006.175.07:45:32.77#ibcon#about to read 3, iclass 29, count 0 2006.175.07:45:32.79#ibcon#read 3, iclass 29, count 0 2006.175.07:45:32.79#ibcon#about to read 4, iclass 29, count 0 2006.175.07:45:32.79#ibcon#read 4, iclass 29, count 0 2006.175.07:45:32.79#ibcon#about to read 5, iclass 29, count 0 2006.175.07:45:32.79#ibcon#read 5, iclass 29, count 0 2006.175.07:45:32.79#ibcon#about to read 6, iclass 29, count 0 2006.175.07:45:32.79#ibcon#read 6, iclass 29, count 0 2006.175.07:45:32.79#ibcon#end of sib2, iclass 29, count 0 2006.175.07:45:32.79#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:45:32.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:45:32.79#ibcon#[27=BW32\r\n] 2006.175.07:45:32.79#ibcon#*before write, iclass 29, count 0 2006.175.07:45:32.79#ibcon#enter sib2, iclass 29, count 0 2006.175.07:45:32.79#ibcon#flushed, iclass 29, count 0 2006.175.07:45:32.79#ibcon#about to write, iclass 29, count 0 2006.175.07:45:32.79#ibcon#wrote, iclass 29, count 0 2006.175.07:45:32.79#ibcon#about to read 3, iclass 29, count 0 2006.175.07:45:32.82#ibcon#read 3, iclass 29, count 0 2006.175.07:45:32.82#ibcon#about to read 4, iclass 29, count 0 2006.175.07:45:32.82#ibcon#read 4, iclass 29, count 0 2006.175.07:45:32.82#ibcon#about to read 5, iclass 29, count 0 2006.175.07:45:32.82#ibcon#read 5, iclass 29, count 0 2006.175.07:45:32.82#ibcon#about to read 6, iclass 29, count 0 2006.175.07:45:32.82#ibcon#read 6, iclass 29, count 0 2006.175.07:45:32.82#ibcon#end of sib2, iclass 29, count 0 2006.175.07:45:32.82#ibcon#*after write, iclass 29, count 0 2006.175.07:45:32.82#ibcon#*before return 0, iclass 29, count 0 2006.175.07:45:32.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:45:32.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:45:32.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:45:32.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:45:32.82$4f8m12a/ifd4f 2006.175.07:45:32.82$ifd4f/lo= 2006.175.07:45:32.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:45:32.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:45:32.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:45:32.82$ifd4f/patch= 2006.175.07:45:32.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:45:32.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:45:32.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:45:32.82$4f8m12a/"form=m,16.000,1:2 2006.175.07:45:32.82$4f8m12a/"tpicd 2006.175.07:45:32.82$4f8m12a/echo=off 2006.175.07:45:32.82$4f8m12a/xlog=off 2006.175.07:45:32.82:!2006.175.07:46:40 2006.175.07:46:15.14#trakl#Source acquired 2006.175.07:46:17.14#flagr#flagr/antenna,acquired 2006.175.07:46:40.00:preob 2006.175.07:46:40.14/onsource/TRACKING 2006.175.07:46:40.14:!2006.175.07:46:50 2006.175.07:46:50.00:data_valid=on 2006.175.07:46:50.00:midob 2006.175.07:46:50.14/onsource/TRACKING 2006.175.07:46:50.14/wx/25.92,1007.4,68 2006.175.07:46:50.29/cable/+6.4777E-03 2006.175.07:46:51.38/va/01,08,usb,yes,30,31 2006.175.07:46:51.38/va/02,07,usb,yes,30,31 2006.175.07:46:51.38/va/03,06,usb,yes,31,32 2006.175.07:46:51.38/va/04,07,usb,yes,31,33 2006.175.07:46:51.38/va/05,07,usb,yes,31,33 2006.175.07:46:51.38/va/06,06,usb,yes,30,30 2006.175.07:46:51.38/va/07,06,usb,yes,31,31 2006.175.07:46:51.38/va/08,06,usb,yes,33,33 2006.175.07:46:51.61/valo/01,532.99,yes,locked 2006.175.07:46:51.61/valo/02,572.99,yes,locked 2006.175.07:46:51.61/valo/03,672.99,yes,locked 2006.175.07:46:51.61/valo/04,832.99,yes,locked 2006.175.07:46:51.61/valo/05,652.99,yes,locked 2006.175.07:46:51.61/valo/06,772.99,yes,locked 2006.175.07:46:51.61/valo/07,832.99,yes,locked 2006.175.07:46:51.61/valo/08,852.99,yes,locked 2006.175.07:46:52.14#trakl#Off source 2006.175.07:46:52.14?ERROR st -7 Antenna off-source! 2006.175.07:46:52.14#trakl#az 42.010 el 24.390 azerr*cos(el) 0.0199 elerr 0.0085 2006.175.07:46:52.14#flagr#flagr/antenna,off-source 2006.175.07:46:52.70/vb/01,04,usb,yes,30,28 2006.175.07:46:52.70/vb/02,04,usb,yes,31,33 2006.175.07:46:52.70/vb/03,04,usb,yes,28,32 2006.175.07:46:52.70/vb/04,04,usb,yes,29,29 2006.175.07:46:52.70/vb/05,04,usb,yes,27,31 2006.175.07:46:52.70/vb/06,04,usb,yes,28,31 2006.175.07:46:52.70/vb/07,04,usb,yes,30,30 2006.175.07:46:52.70/vb/08,04,usb,yes,28,31 2006.175.07:46:52.93/vblo/01,632.99,yes,locked 2006.175.07:46:52.93/vblo/02,640.99,yes,locked 2006.175.07:46:52.93/vblo/03,656.99,yes,locked 2006.175.07:46:52.93/vblo/04,712.99,yes,locked 2006.175.07:46:52.93/vblo/05,744.99,yes,locked 2006.175.07:46:52.93/vblo/06,752.99,yes,locked 2006.175.07:46:52.93/vblo/07,734.99,yes,locked 2006.175.07:46:52.93/vblo/08,744.99,yes,locked 2006.175.07:46:53.08/vabw/8 2006.175.07:46:53.23/vbbw/8 2006.175.07:46:53.32/xfe/off,on,14.7 2006.175.07:46:53.71/ifatt/23,28,28,28 2006.175.07:46:54.08/fmout-gps/S +3.76E-07 2006.175.07:46:54.12:!2006.175.07:47:50 2006.175.07:46:58.14#trakl#Source re-acquired 2006.175.07:46:58.14#flagr#flagr/antenna,re-acquired 2006.175.07:47:50.00:data_valid=off 2006.175.07:47:50.00:postob 2006.175.07:47:50.09/cable/+6.4763E-03 2006.175.07:47:50.09/wx/25.91,1007.4,69 2006.175.07:47:51.08/fmout-gps/S +3.76E-07 2006.175.07:47:51.08:scan_name=175-0748,k06175,60 2006.175.07:47:51.09:source=1300+580,130252.47,574837.6,2000.0,cw 2006.175.07:47:51.14#flagr#flagr/antenna,new-source 2006.175.07:47:52.14:checkk5 2006.175.07:47:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:47:52.93/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:47:53.32/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:47:53.69/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:47:54.07/chk_obsdata//k5ts1/T1750746??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:47:54.44/chk_obsdata//k5ts2/T1750746??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:47:54.81/chk_obsdata//k5ts3/T1750746??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:47:55.19/chk_obsdata//k5ts4/T1750746??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:47:55.89/k5log//k5ts1_log_newline 2006.175.07:47:56.59/k5log//k5ts2_log_newline 2006.175.07:47:57.30/k5log//k5ts3_log_newline 2006.175.07:47:58.01/k5log//k5ts4_log_newline 2006.175.07:47:58.03/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:47:58.03:4f8m12a=1 2006.175.07:47:58.03$4f8m12a/echo=on 2006.175.07:47:58.03$4f8m12a/pcalon 2006.175.07:47:58.03$pcalon/"no phase cal control is implemented here 2006.175.07:47:58.03$4f8m12a/"tpicd=stop 2006.175.07:47:58.03$4f8m12a/vc4f8 2006.175.07:47:58.03$vc4f8/valo=1,532.99 2006.175.07:47:58.03#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.07:47:58.03#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.07:47:58.03#ibcon#ireg 17 cls_cnt 0 2006.175.07:47:58.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:47:58.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:47:58.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:47:58.03#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:47:58.03#ibcon#first serial, iclass 22, count 0 2006.175.07:47:58.03#ibcon#enter sib2, iclass 22, count 0 2006.175.07:47:58.03#ibcon#flushed, iclass 22, count 0 2006.175.07:47:58.03#ibcon#about to write, iclass 22, count 0 2006.175.07:47:58.03#ibcon#wrote, iclass 22, count 0 2006.175.07:47:58.03#ibcon#about to read 3, iclass 22, count 0 2006.175.07:47:58.05#ibcon#read 3, iclass 22, count 0 2006.175.07:47:58.05#ibcon#about to read 4, iclass 22, count 0 2006.175.07:47:58.05#ibcon#read 4, iclass 22, count 0 2006.175.07:47:58.05#ibcon#about to read 5, iclass 22, count 0 2006.175.07:47:58.05#ibcon#read 5, iclass 22, count 0 2006.175.07:47:58.05#ibcon#about to read 6, iclass 22, count 0 2006.175.07:47:58.05#ibcon#read 6, iclass 22, count 0 2006.175.07:47:58.05#ibcon#end of sib2, iclass 22, count 0 2006.175.07:47:58.05#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:47:58.05#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:47:58.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:47:58.05#ibcon#*before write, iclass 22, count 0 2006.175.07:47:58.05#ibcon#enter sib2, iclass 22, count 0 2006.175.07:47:58.05#ibcon#flushed, iclass 22, count 0 2006.175.07:47:58.05#ibcon#about to write, iclass 22, count 0 2006.175.07:47:58.05#ibcon#wrote, iclass 22, count 0 2006.175.07:47:58.05#ibcon#about to read 3, iclass 22, count 0 2006.175.07:47:58.10#ibcon#read 3, iclass 22, count 0 2006.175.07:47:58.10#ibcon#about to read 4, iclass 22, count 0 2006.175.07:47:58.10#ibcon#read 4, iclass 22, count 0 2006.175.07:47:58.10#ibcon#about to read 5, iclass 22, count 0 2006.175.07:47:58.10#ibcon#read 5, iclass 22, count 0 2006.175.07:47:58.10#ibcon#about to read 6, iclass 22, count 0 2006.175.07:47:58.10#ibcon#read 6, iclass 22, count 0 2006.175.07:47:58.10#ibcon#end of sib2, iclass 22, count 0 2006.175.07:47:58.10#ibcon#*after write, iclass 22, count 0 2006.175.07:47:58.10#ibcon#*before return 0, iclass 22, count 0 2006.175.07:47:58.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:47:58.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:47:58.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:47:58.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:47:58.10$vc4f8/va=1,8 2006.175.07:47:58.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.07:47:58.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.07:47:58.10#ibcon#ireg 11 cls_cnt 2 2006.175.07:47:58.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:47:58.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:47:58.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:47:58.10#ibcon#enter wrdev, iclass 24, count 2 2006.175.07:47:58.10#ibcon#first serial, iclass 24, count 2 2006.175.07:47:58.10#ibcon#enter sib2, iclass 24, count 2 2006.175.07:47:58.10#ibcon#flushed, iclass 24, count 2 2006.175.07:47:58.10#ibcon#about to write, iclass 24, count 2 2006.175.07:47:58.10#ibcon#wrote, iclass 24, count 2 2006.175.07:47:58.10#ibcon#about to read 3, iclass 24, count 2 2006.175.07:47:58.12#ibcon#read 3, iclass 24, count 2 2006.175.07:47:58.12#ibcon#about to read 4, iclass 24, count 2 2006.175.07:47:58.12#ibcon#read 4, iclass 24, count 2 2006.175.07:47:58.12#ibcon#about to read 5, iclass 24, count 2 2006.175.07:47:58.12#ibcon#read 5, iclass 24, count 2 2006.175.07:47:58.12#ibcon#about to read 6, iclass 24, count 2 2006.175.07:47:58.12#ibcon#read 6, iclass 24, count 2 2006.175.07:47:58.12#ibcon#end of sib2, iclass 24, count 2 2006.175.07:47:58.12#ibcon#*mode == 0, iclass 24, count 2 2006.175.07:47:58.12#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.07:47:58.12#ibcon#[25=AT01-08\r\n] 2006.175.07:47:58.12#ibcon#*before write, iclass 24, count 2 2006.175.07:47:58.12#ibcon#enter sib2, iclass 24, count 2 2006.175.07:47:58.12#ibcon#flushed, iclass 24, count 2 2006.175.07:47:58.12#ibcon#about to write, iclass 24, count 2 2006.175.07:47:58.12#ibcon#wrote, iclass 24, count 2 2006.175.07:47:58.12#ibcon#about to read 3, iclass 24, count 2 2006.175.07:47:58.15#ibcon#read 3, iclass 24, count 2 2006.175.07:47:58.15#ibcon#about to read 4, iclass 24, count 2 2006.175.07:47:58.15#ibcon#read 4, iclass 24, count 2 2006.175.07:47:58.15#ibcon#about to read 5, iclass 24, count 2 2006.175.07:47:58.15#ibcon#read 5, iclass 24, count 2 2006.175.07:47:58.15#ibcon#about to read 6, iclass 24, count 2 2006.175.07:47:58.15#ibcon#read 6, iclass 24, count 2 2006.175.07:47:58.15#ibcon#end of sib2, iclass 24, count 2 2006.175.07:47:58.15#ibcon#*after write, iclass 24, count 2 2006.175.07:47:58.15#ibcon#*before return 0, iclass 24, count 2 2006.175.07:47:58.15#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:47:58.15#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:47:58.15#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.07:47:58.15#ibcon#ireg 7 cls_cnt 0 2006.175.07:47:58.15#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:47:58.27#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:47:58.27#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:47:58.27#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:47:58.27#ibcon#first serial, iclass 24, count 0 2006.175.07:47:58.27#ibcon#enter sib2, iclass 24, count 0 2006.175.07:47:58.27#ibcon#flushed, iclass 24, count 0 2006.175.07:47:58.27#ibcon#about to write, iclass 24, count 0 2006.175.07:47:58.27#ibcon#wrote, iclass 24, count 0 2006.175.07:47:58.27#ibcon#about to read 3, iclass 24, count 0 2006.175.07:47:58.29#ibcon#read 3, iclass 24, count 0 2006.175.07:47:58.29#ibcon#about to read 4, iclass 24, count 0 2006.175.07:47:58.29#ibcon#read 4, iclass 24, count 0 2006.175.07:47:58.29#ibcon#about to read 5, iclass 24, count 0 2006.175.07:47:58.29#ibcon#read 5, iclass 24, count 0 2006.175.07:47:58.29#ibcon#about to read 6, iclass 24, count 0 2006.175.07:47:58.29#ibcon#read 6, iclass 24, count 0 2006.175.07:47:58.29#ibcon#end of sib2, iclass 24, count 0 2006.175.07:47:58.29#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:47:58.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:47:58.29#ibcon#[25=USB\r\n] 2006.175.07:47:58.29#ibcon#*before write, iclass 24, count 0 2006.175.07:47:58.29#ibcon#enter sib2, iclass 24, count 0 2006.175.07:47:58.29#ibcon#flushed, iclass 24, count 0 2006.175.07:47:58.29#ibcon#about to write, iclass 24, count 0 2006.175.07:47:58.29#ibcon#wrote, iclass 24, count 0 2006.175.07:47:58.29#ibcon#about to read 3, iclass 24, count 0 2006.175.07:47:58.32#ibcon#read 3, iclass 24, count 0 2006.175.07:47:58.32#ibcon#about to read 4, iclass 24, count 0 2006.175.07:47:58.32#ibcon#read 4, iclass 24, count 0 2006.175.07:47:58.32#ibcon#about to read 5, iclass 24, count 0 2006.175.07:47:58.32#ibcon#read 5, iclass 24, count 0 2006.175.07:47:58.32#ibcon#about to read 6, iclass 24, count 0 2006.175.07:47:58.32#ibcon#read 6, iclass 24, count 0 2006.175.07:47:58.32#ibcon#end of sib2, iclass 24, count 0 2006.175.07:47:58.32#ibcon#*after write, iclass 24, count 0 2006.175.07:47:58.32#ibcon#*before return 0, iclass 24, count 0 2006.175.07:47:58.32#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:47:58.32#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:47:58.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:47:58.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:47:58.32$vc4f8/valo=2,572.99 2006.175.07:47:58.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.07:47:58.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.07:47:58.32#ibcon#ireg 17 cls_cnt 0 2006.175.07:47:58.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:47:58.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:47:58.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:47:58.32#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:47:58.32#ibcon#first serial, iclass 26, count 0 2006.175.07:47:58.32#ibcon#enter sib2, iclass 26, count 0 2006.175.07:47:58.32#ibcon#flushed, iclass 26, count 0 2006.175.07:47:58.32#ibcon#about to write, iclass 26, count 0 2006.175.07:47:58.32#ibcon#wrote, iclass 26, count 0 2006.175.07:47:58.32#ibcon#about to read 3, iclass 26, count 0 2006.175.07:47:58.34#ibcon#read 3, iclass 26, count 0 2006.175.07:47:58.34#ibcon#about to read 4, iclass 26, count 0 2006.175.07:47:58.34#ibcon#read 4, iclass 26, count 0 2006.175.07:47:58.34#ibcon#about to read 5, iclass 26, count 0 2006.175.07:47:58.34#ibcon#read 5, iclass 26, count 0 2006.175.07:47:58.34#ibcon#about to read 6, iclass 26, count 0 2006.175.07:47:58.34#ibcon#read 6, iclass 26, count 0 2006.175.07:47:58.34#ibcon#end of sib2, iclass 26, count 0 2006.175.07:47:58.34#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:47:58.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:47:58.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:47:58.34#ibcon#*before write, iclass 26, count 0 2006.175.07:47:58.34#ibcon#enter sib2, iclass 26, count 0 2006.175.07:47:58.34#ibcon#flushed, iclass 26, count 0 2006.175.07:47:58.34#ibcon#about to write, iclass 26, count 0 2006.175.07:47:58.34#ibcon#wrote, iclass 26, count 0 2006.175.07:47:58.34#ibcon#about to read 3, iclass 26, count 0 2006.175.07:47:58.38#ibcon#read 3, iclass 26, count 0 2006.175.07:47:58.38#ibcon#about to read 4, iclass 26, count 0 2006.175.07:47:58.38#ibcon#read 4, iclass 26, count 0 2006.175.07:47:58.38#ibcon#about to read 5, iclass 26, count 0 2006.175.07:47:58.38#ibcon#read 5, iclass 26, count 0 2006.175.07:47:58.38#ibcon#about to read 6, iclass 26, count 0 2006.175.07:47:58.38#ibcon#read 6, iclass 26, count 0 2006.175.07:47:58.38#ibcon#end of sib2, iclass 26, count 0 2006.175.07:47:58.38#ibcon#*after write, iclass 26, count 0 2006.175.07:47:58.38#ibcon#*before return 0, iclass 26, count 0 2006.175.07:47:58.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:47:58.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:47:58.38#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:47:58.38#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:47:58.38$vc4f8/va=2,7 2006.175.07:47:58.38#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.07:47:58.38#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.07:47:58.38#ibcon#ireg 11 cls_cnt 2 2006.175.07:47:58.38#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:47:58.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:47:58.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:47:58.44#ibcon#enter wrdev, iclass 28, count 2 2006.175.07:47:58.44#ibcon#first serial, iclass 28, count 2 2006.175.07:47:58.44#ibcon#enter sib2, iclass 28, count 2 2006.175.07:47:58.44#ibcon#flushed, iclass 28, count 2 2006.175.07:47:58.44#ibcon#about to write, iclass 28, count 2 2006.175.07:47:58.44#ibcon#wrote, iclass 28, count 2 2006.175.07:47:58.44#ibcon#about to read 3, iclass 28, count 2 2006.175.07:47:58.46#ibcon#read 3, iclass 28, count 2 2006.175.07:47:58.46#ibcon#about to read 4, iclass 28, count 2 2006.175.07:47:58.46#ibcon#read 4, iclass 28, count 2 2006.175.07:47:58.46#ibcon#about to read 5, iclass 28, count 2 2006.175.07:47:58.46#ibcon#read 5, iclass 28, count 2 2006.175.07:47:58.46#ibcon#about to read 6, iclass 28, count 2 2006.175.07:47:58.46#ibcon#read 6, iclass 28, count 2 2006.175.07:47:58.46#ibcon#end of sib2, iclass 28, count 2 2006.175.07:47:58.46#ibcon#*mode == 0, iclass 28, count 2 2006.175.07:47:58.46#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.07:47:58.46#ibcon#[25=AT02-07\r\n] 2006.175.07:47:58.46#ibcon#*before write, iclass 28, count 2 2006.175.07:47:58.46#ibcon#enter sib2, iclass 28, count 2 2006.175.07:47:58.46#ibcon#flushed, iclass 28, count 2 2006.175.07:47:58.46#ibcon#about to write, iclass 28, count 2 2006.175.07:47:58.46#ibcon#wrote, iclass 28, count 2 2006.175.07:47:58.46#ibcon#about to read 3, iclass 28, count 2 2006.175.07:47:58.49#ibcon#read 3, iclass 28, count 2 2006.175.07:47:58.49#ibcon#about to read 4, iclass 28, count 2 2006.175.07:47:58.49#ibcon#read 4, iclass 28, count 2 2006.175.07:47:58.49#ibcon#about to read 5, iclass 28, count 2 2006.175.07:47:58.49#ibcon#read 5, iclass 28, count 2 2006.175.07:47:58.49#ibcon#about to read 6, iclass 28, count 2 2006.175.07:47:58.49#ibcon#read 6, iclass 28, count 2 2006.175.07:47:58.49#ibcon#end of sib2, iclass 28, count 2 2006.175.07:47:58.49#ibcon#*after write, iclass 28, count 2 2006.175.07:47:58.49#ibcon#*before return 0, iclass 28, count 2 2006.175.07:47:58.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:47:58.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:47:58.49#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.07:47:58.49#ibcon#ireg 7 cls_cnt 0 2006.175.07:47:58.49#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:47:58.61#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:47:58.61#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:47:58.61#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:47:58.61#ibcon#first serial, iclass 28, count 0 2006.175.07:47:58.61#ibcon#enter sib2, iclass 28, count 0 2006.175.07:47:58.61#ibcon#flushed, iclass 28, count 0 2006.175.07:47:58.61#ibcon#about to write, iclass 28, count 0 2006.175.07:47:58.61#ibcon#wrote, iclass 28, count 0 2006.175.07:47:58.61#ibcon#about to read 3, iclass 28, count 0 2006.175.07:47:58.63#ibcon#read 3, iclass 28, count 0 2006.175.07:47:58.63#ibcon#about to read 4, iclass 28, count 0 2006.175.07:47:58.63#ibcon#read 4, iclass 28, count 0 2006.175.07:47:58.63#ibcon#about to read 5, iclass 28, count 0 2006.175.07:47:58.63#ibcon#read 5, iclass 28, count 0 2006.175.07:47:58.63#ibcon#about to read 6, iclass 28, count 0 2006.175.07:47:58.63#ibcon#read 6, iclass 28, count 0 2006.175.07:47:58.63#ibcon#end of sib2, iclass 28, count 0 2006.175.07:47:58.63#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:47:58.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:47:58.63#ibcon#[25=USB\r\n] 2006.175.07:47:58.63#ibcon#*before write, iclass 28, count 0 2006.175.07:47:58.63#ibcon#enter sib2, iclass 28, count 0 2006.175.07:47:58.63#ibcon#flushed, iclass 28, count 0 2006.175.07:47:58.63#ibcon#about to write, iclass 28, count 0 2006.175.07:47:58.63#ibcon#wrote, iclass 28, count 0 2006.175.07:47:58.63#ibcon#about to read 3, iclass 28, count 0 2006.175.07:47:58.66#ibcon#read 3, iclass 28, count 0 2006.175.07:47:58.66#ibcon#about to read 4, iclass 28, count 0 2006.175.07:47:58.66#ibcon#read 4, iclass 28, count 0 2006.175.07:47:58.66#ibcon#about to read 5, iclass 28, count 0 2006.175.07:47:58.66#ibcon#read 5, iclass 28, count 0 2006.175.07:47:58.66#ibcon#about to read 6, iclass 28, count 0 2006.175.07:47:58.66#ibcon#read 6, iclass 28, count 0 2006.175.07:47:58.66#ibcon#end of sib2, iclass 28, count 0 2006.175.07:47:58.66#ibcon#*after write, iclass 28, count 0 2006.175.07:47:58.66#ibcon#*before return 0, iclass 28, count 0 2006.175.07:47:58.66#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:47:58.66#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:47:58.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:47:58.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:47:58.66$vc4f8/valo=3,672.99 2006.175.07:47:58.66#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.07:47:58.66#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.07:47:58.66#ibcon#ireg 17 cls_cnt 0 2006.175.07:47:58.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:47:58.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:47:58.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:47:58.66#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:47:58.66#ibcon#first serial, iclass 30, count 0 2006.175.07:47:58.66#ibcon#enter sib2, iclass 30, count 0 2006.175.07:47:58.66#ibcon#flushed, iclass 30, count 0 2006.175.07:47:58.66#ibcon#about to write, iclass 30, count 0 2006.175.07:47:58.66#ibcon#wrote, iclass 30, count 0 2006.175.07:47:58.66#ibcon#about to read 3, iclass 30, count 0 2006.175.07:47:58.68#ibcon#read 3, iclass 30, count 0 2006.175.07:47:58.68#ibcon#about to read 4, iclass 30, count 0 2006.175.07:47:58.68#ibcon#read 4, iclass 30, count 0 2006.175.07:47:58.68#ibcon#about to read 5, iclass 30, count 0 2006.175.07:47:58.68#ibcon#read 5, iclass 30, count 0 2006.175.07:47:58.68#ibcon#about to read 6, iclass 30, count 0 2006.175.07:47:58.68#ibcon#read 6, iclass 30, count 0 2006.175.07:47:58.68#ibcon#end of sib2, iclass 30, count 0 2006.175.07:47:58.68#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:47:58.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:47:58.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:47:58.68#ibcon#*before write, iclass 30, count 0 2006.175.07:47:58.68#ibcon#enter sib2, iclass 30, count 0 2006.175.07:47:58.68#ibcon#flushed, iclass 30, count 0 2006.175.07:47:58.68#ibcon#about to write, iclass 30, count 0 2006.175.07:47:58.68#ibcon#wrote, iclass 30, count 0 2006.175.07:47:58.68#ibcon#about to read 3, iclass 30, count 0 2006.175.07:47:58.72#ibcon#read 3, iclass 30, count 0 2006.175.07:47:58.72#ibcon#about to read 4, iclass 30, count 0 2006.175.07:47:58.72#ibcon#read 4, iclass 30, count 0 2006.175.07:47:58.72#ibcon#about to read 5, iclass 30, count 0 2006.175.07:47:58.72#ibcon#read 5, iclass 30, count 0 2006.175.07:47:58.72#ibcon#about to read 6, iclass 30, count 0 2006.175.07:47:58.72#ibcon#read 6, iclass 30, count 0 2006.175.07:47:58.72#ibcon#end of sib2, iclass 30, count 0 2006.175.07:47:58.72#ibcon#*after write, iclass 30, count 0 2006.175.07:47:58.72#ibcon#*before return 0, iclass 30, count 0 2006.175.07:47:58.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:47:58.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:47:58.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:47:58.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:47:58.72$vc4f8/va=3,6 2006.175.07:47:58.72#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.07:47:58.72#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.07:47:58.72#ibcon#ireg 11 cls_cnt 2 2006.175.07:47:58.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:47:58.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:47:58.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:47:58.78#ibcon#enter wrdev, iclass 32, count 2 2006.175.07:47:58.78#ibcon#first serial, iclass 32, count 2 2006.175.07:47:58.78#ibcon#enter sib2, iclass 32, count 2 2006.175.07:47:58.78#ibcon#flushed, iclass 32, count 2 2006.175.07:47:58.78#ibcon#about to write, iclass 32, count 2 2006.175.07:47:58.78#ibcon#wrote, iclass 32, count 2 2006.175.07:47:58.78#ibcon#about to read 3, iclass 32, count 2 2006.175.07:47:58.80#ibcon#read 3, iclass 32, count 2 2006.175.07:47:58.80#ibcon#about to read 4, iclass 32, count 2 2006.175.07:47:58.80#ibcon#read 4, iclass 32, count 2 2006.175.07:47:58.80#ibcon#about to read 5, iclass 32, count 2 2006.175.07:47:58.80#ibcon#read 5, iclass 32, count 2 2006.175.07:47:58.80#ibcon#about to read 6, iclass 32, count 2 2006.175.07:47:58.80#ibcon#read 6, iclass 32, count 2 2006.175.07:47:58.80#ibcon#end of sib2, iclass 32, count 2 2006.175.07:47:58.80#ibcon#*mode == 0, iclass 32, count 2 2006.175.07:47:58.80#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.07:47:58.80#ibcon#[25=AT03-06\r\n] 2006.175.07:47:58.80#ibcon#*before write, iclass 32, count 2 2006.175.07:47:58.80#ibcon#enter sib2, iclass 32, count 2 2006.175.07:47:58.80#ibcon#flushed, iclass 32, count 2 2006.175.07:47:58.80#ibcon#about to write, iclass 32, count 2 2006.175.07:47:58.80#ibcon#wrote, iclass 32, count 2 2006.175.07:47:58.80#ibcon#about to read 3, iclass 32, count 2 2006.175.07:47:58.83#ibcon#read 3, iclass 32, count 2 2006.175.07:47:58.83#ibcon#about to read 4, iclass 32, count 2 2006.175.07:47:58.83#ibcon#read 4, iclass 32, count 2 2006.175.07:47:58.83#ibcon#about to read 5, iclass 32, count 2 2006.175.07:47:58.83#ibcon#read 5, iclass 32, count 2 2006.175.07:47:58.83#ibcon#about to read 6, iclass 32, count 2 2006.175.07:47:58.83#ibcon#read 6, iclass 32, count 2 2006.175.07:47:58.83#ibcon#end of sib2, iclass 32, count 2 2006.175.07:47:58.83#ibcon#*after write, iclass 32, count 2 2006.175.07:47:58.83#ibcon#*before return 0, iclass 32, count 2 2006.175.07:47:58.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:47:58.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:47:58.83#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.07:47:58.83#ibcon#ireg 7 cls_cnt 0 2006.175.07:47:58.83#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:47:58.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:47:58.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:47:58.95#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:47:58.95#ibcon#first serial, iclass 32, count 0 2006.175.07:47:58.95#ibcon#enter sib2, iclass 32, count 0 2006.175.07:47:58.95#ibcon#flushed, iclass 32, count 0 2006.175.07:47:58.95#ibcon#about to write, iclass 32, count 0 2006.175.07:47:58.95#ibcon#wrote, iclass 32, count 0 2006.175.07:47:58.95#ibcon#about to read 3, iclass 32, count 0 2006.175.07:47:58.97#ibcon#read 3, iclass 32, count 0 2006.175.07:47:58.97#ibcon#about to read 4, iclass 32, count 0 2006.175.07:47:58.97#ibcon#read 4, iclass 32, count 0 2006.175.07:47:58.97#ibcon#about to read 5, iclass 32, count 0 2006.175.07:47:58.97#ibcon#read 5, iclass 32, count 0 2006.175.07:47:58.97#ibcon#about to read 6, iclass 32, count 0 2006.175.07:47:58.97#ibcon#read 6, iclass 32, count 0 2006.175.07:47:58.97#ibcon#end of sib2, iclass 32, count 0 2006.175.07:47:58.97#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:47:58.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:47:58.97#ibcon#[25=USB\r\n] 2006.175.07:47:58.97#ibcon#*before write, iclass 32, count 0 2006.175.07:47:58.97#ibcon#enter sib2, iclass 32, count 0 2006.175.07:47:58.97#ibcon#flushed, iclass 32, count 0 2006.175.07:47:58.97#ibcon#about to write, iclass 32, count 0 2006.175.07:47:58.97#ibcon#wrote, iclass 32, count 0 2006.175.07:47:58.97#ibcon#about to read 3, iclass 32, count 0 2006.175.07:47:59.00#ibcon#read 3, iclass 32, count 0 2006.175.07:47:59.00#ibcon#about to read 4, iclass 32, count 0 2006.175.07:47:59.00#ibcon#read 4, iclass 32, count 0 2006.175.07:47:59.00#ibcon#about to read 5, iclass 32, count 0 2006.175.07:47:59.00#ibcon#read 5, iclass 32, count 0 2006.175.07:47:59.00#ibcon#about to read 6, iclass 32, count 0 2006.175.07:47:59.00#ibcon#read 6, iclass 32, count 0 2006.175.07:47:59.00#ibcon#end of sib2, iclass 32, count 0 2006.175.07:47:59.00#ibcon#*after write, iclass 32, count 0 2006.175.07:47:59.00#ibcon#*before return 0, iclass 32, count 0 2006.175.07:47:59.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:47:59.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:47:59.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:47:59.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:47:59.00$vc4f8/valo=4,832.99 2006.175.07:47:59.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.07:47:59.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.07:47:59.00#ibcon#ireg 17 cls_cnt 0 2006.175.07:47:59.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:47:59.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:47:59.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:47:59.00#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:47:59.00#ibcon#first serial, iclass 34, count 0 2006.175.07:47:59.00#ibcon#enter sib2, iclass 34, count 0 2006.175.07:47:59.00#ibcon#flushed, iclass 34, count 0 2006.175.07:47:59.00#ibcon#about to write, iclass 34, count 0 2006.175.07:47:59.00#ibcon#wrote, iclass 34, count 0 2006.175.07:47:59.00#ibcon#about to read 3, iclass 34, count 0 2006.175.07:47:59.02#ibcon#read 3, iclass 34, count 0 2006.175.07:47:59.02#ibcon#about to read 4, iclass 34, count 0 2006.175.07:47:59.02#ibcon#read 4, iclass 34, count 0 2006.175.07:47:59.02#ibcon#about to read 5, iclass 34, count 0 2006.175.07:47:59.02#ibcon#read 5, iclass 34, count 0 2006.175.07:47:59.02#ibcon#about to read 6, iclass 34, count 0 2006.175.07:47:59.02#ibcon#read 6, iclass 34, count 0 2006.175.07:47:59.02#ibcon#end of sib2, iclass 34, count 0 2006.175.07:47:59.02#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:47:59.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:47:59.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:47:59.02#ibcon#*before write, iclass 34, count 0 2006.175.07:47:59.02#ibcon#enter sib2, iclass 34, count 0 2006.175.07:47:59.02#ibcon#flushed, iclass 34, count 0 2006.175.07:47:59.02#ibcon#about to write, iclass 34, count 0 2006.175.07:47:59.02#ibcon#wrote, iclass 34, count 0 2006.175.07:47:59.02#ibcon#about to read 3, iclass 34, count 0 2006.175.07:47:59.06#ibcon#read 3, iclass 34, count 0 2006.175.07:47:59.06#ibcon#about to read 4, iclass 34, count 0 2006.175.07:47:59.06#ibcon#read 4, iclass 34, count 0 2006.175.07:47:59.06#ibcon#about to read 5, iclass 34, count 0 2006.175.07:47:59.06#ibcon#read 5, iclass 34, count 0 2006.175.07:47:59.06#ibcon#about to read 6, iclass 34, count 0 2006.175.07:47:59.06#ibcon#read 6, iclass 34, count 0 2006.175.07:47:59.06#ibcon#end of sib2, iclass 34, count 0 2006.175.07:47:59.06#ibcon#*after write, iclass 34, count 0 2006.175.07:47:59.06#ibcon#*before return 0, iclass 34, count 0 2006.175.07:47:59.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:47:59.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:47:59.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:47:59.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:47:59.06$vc4f8/va=4,7 2006.175.07:47:59.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.07:47:59.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.07:47:59.06#ibcon#ireg 11 cls_cnt 2 2006.175.07:47:59.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:47:59.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:47:59.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:47:59.12#ibcon#enter wrdev, iclass 36, count 2 2006.175.07:47:59.12#ibcon#first serial, iclass 36, count 2 2006.175.07:47:59.12#ibcon#enter sib2, iclass 36, count 2 2006.175.07:47:59.12#ibcon#flushed, iclass 36, count 2 2006.175.07:47:59.12#ibcon#about to write, iclass 36, count 2 2006.175.07:47:59.12#ibcon#wrote, iclass 36, count 2 2006.175.07:47:59.12#ibcon#about to read 3, iclass 36, count 2 2006.175.07:47:59.14#ibcon#read 3, iclass 36, count 2 2006.175.07:47:59.14#ibcon#about to read 4, iclass 36, count 2 2006.175.07:47:59.14#ibcon#read 4, iclass 36, count 2 2006.175.07:47:59.14#ibcon#about to read 5, iclass 36, count 2 2006.175.07:47:59.14#ibcon#read 5, iclass 36, count 2 2006.175.07:47:59.14#ibcon#about to read 6, iclass 36, count 2 2006.175.07:47:59.14#ibcon#read 6, iclass 36, count 2 2006.175.07:47:59.14#ibcon#end of sib2, iclass 36, count 2 2006.175.07:47:59.14#ibcon#*mode == 0, iclass 36, count 2 2006.175.07:47:59.14#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.07:47:59.14#ibcon#[25=AT04-07\r\n] 2006.175.07:47:59.14#ibcon#*before write, iclass 36, count 2 2006.175.07:47:59.14#ibcon#enter sib2, iclass 36, count 2 2006.175.07:47:59.14#ibcon#flushed, iclass 36, count 2 2006.175.07:47:59.14#ibcon#about to write, iclass 36, count 2 2006.175.07:47:59.14#ibcon#wrote, iclass 36, count 2 2006.175.07:47:59.14#ibcon#about to read 3, iclass 36, count 2 2006.175.07:47:59.17#ibcon#read 3, iclass 36, count 2 2006.175.07:47:59.17#ibcon#about to read 4, iclass 36, count 2 2006.175.07:47:59.17#ibcon#read 4, iclass 36, count 2 2006.175.07:47:59.17#ibcon#about to read 5, iclass 36, count 2 2006.175.07:47:59.17#ibcon#read 5, iclass 36, count 2 2006.175.07:47:59.17#ibcon#about to read 6, iclass 36, count 2 2006.175.07:47:59.17#ibcon#read 6, iclass 36, count 2 2006.175.07:47:59.17#ibcon#end of sib2, iclass 36, count 2 2006.175.07:47:59.17#ibcon#*after write, iclass 36, count 2 2006.175.07:47:59.17#ibcon#*before return 0, iclass 36, count 2 2006.175.07:47:59.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:47:59.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:47:59.17#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.07:47:59.17#ibcon#ireg 7 cls_cnt 0 2006.175.07:47:59.17#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:47:59.29#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:47:59.29#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:47:59.29#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:47:59.29#ibcon#first serial, iclass 36, count 0 2006.175.07:47:59.29#ibcon#enter sib2, iclass 36, count 0 2006.175.07:47:59.29#ibcon#flushed, iclass 36, count 0 2006.175.07:47:59.29#ibcon#about to write, iclass 36, count 0 2006.175.07:47:59.29#ibcon#wrote, iclass 36, count 0 2006.175.07:47:59.29#ibcon#about to read 3, iclass 36, count 0 2006.175.07:47:59.31#ibcon#read 3, iclass 36, count 0 2006.175.07:47:59.31#ibcon#about to read 4, iclass 36, count 0 2006.175.07:47:59.31#ibcon#read 4, iclass 36, count 0 2006.175.07:47:59.31#ibcon#about to read 5, iclass 36, count 0 2006.175.07:47:59.31#ibcon#read 5, iclass 36, count 0 2006.175.07:47:59.31#ibcon#about to read 6, iclass 36, count 0 2006.175.07:47:59.31#ibcon#read 6, iclass 36, count 0 2006.175.07:47:59.31#ibcon#end of sib2, iclass 36, count 0 2006.175.07:47:59.31#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:47:59.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:47:59.31#ibcon#[25=USB\r\n] 2006.175.07:47:59.31#ibcon#*before write, iclass 36, count 0 2006.175.07:47:59.31#ibcon#enter sib2, iclass 36, count 0 2006.175.07:47:59.31#ibcon#flushed, iclass 36, count 0 2006.175.07:47:59.31#ibcon#about to write, iclass 36, count 0 2006.175.07:47:59.31#ibcon#wrote, iclass 36, count 0 2006.175.07:47:59.31#ibcon#about to read 3, iclass 36, count 0 2006.175.07:47:59.34#ibcon#read 3, iclass 36, count 0 2006.175.07:47:59.34#ibcon#about to read 4, iclass 36, count 0 2006.175.07:47:59.34#ibcon#read 4, iclass 36, count 0 2006.175.07:47:59.34#ibcon#about to read 5, iclass 36, count 0 2006.175.07:47:59.34#ibcon#read 5, iclass 36, count 0 2006.175.07:47:59.34#ibcon#about to read 6, iclass 36, count 0 2006.175.07:47:59.34#ibcon#read 6, iclass 36, count 0 2006.175.07:47:59.34#ibcon#end of sib2, iclass 36, count 0 2006.175.07:47:59.34#ibcon#*after write, iclass 36, count 0 2006.175.07:47:59.34#ibcon#*before return 0, iclass 36, count 0 2006.175.07:47:59.34#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:47:59.34#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:47:59.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:47:59.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:47:59.34$vc4f8/valo=5,652.99 2006.175.07:47:59.34#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:47:59.34#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:47:59.34#ibcon#ireg 17 cls_cnt 0 2006.175.07:47:59.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:47:59.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:47:59.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:47:59.34#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:47:59.34#ibcon#first serial, iclass 38, count 0 2006.175.07:47:59.34#ibcon#enter sib2, iclass 38, count 0 2006.175.07:47:59.34#ibcon#flushed, iclass 38, count 0 2006.175.07:47:59.34#ibcon#about to write, iclass 38, count 0 2006.175.07:47:59.34#ibcon#wrote, iclass 38, count 0 2006.175.07:47:59.34#ibcon#about to read 3, iclass 38, count 0 2006.175.07:47:59.36#ibcon#read 3, iclass 38, count 0 2006.175.07:47:59.36#ibcon#about to read 4, iclass 38, count 0 2006.175.07:47:59.36#ibcon#read 4, iclass 38, count 0 2006.175.07:47:59.36#ibcon#about to read 5, iclass 38, count 0 2006.175.07:47:59.36#ibcon#read 5, iclass 38, count 0 2006.175.07:47:59.36#ibcon#about to read 6, iclass 38, count 0 2006.175.07:47:59.36#ibcon#read 6, iclass 38, count 0 2006.175.07:47:59.36#ibcon#end of sib2, iclass 38, count 0 2006.175.07:47:59.36#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:47:59.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:47:59.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:47:59.36#ibcon#*before write, iclass 38, count 0 2006.175.07:47:59.36#ibcon#enter sib2, iclass 38, count 0 2006.175.07:47:59.36#ibcon#flushed, iclass 38, count 0 2006.175.07:47:59.36#ibcon#about to write, iclass 38, count 0 2006.175.07:47:59.36#ibcon#wrote, iclass 38, count 0 2006.175.07:47:59.36#ibcon#about to read 3, iclass 38, count 0 2006.175.07:47:59.40#ibcon#read 3, iclass 38, count 0 2006.175.07:47:59.40#ibcon#about to read 4, iclass 38, count 0 2006.175.07:47:59.40#ibcon#read 4, iclass 38, count 0 2006.175.07:47:59.40#ibcon#about to read 5, iclass 38, count 0 2006.175.07:47:59.40#ibcon#read 5, iclass 38, count 0 2006.175.07:47:59.40#ibcon#about to read 6, iclass 38, count 0 2006.175.07:47:59.40#ibcon#read 6, iclass 38, count 0 2006.175.07:47:59.40#ibcon#end of sib2, iclass 38, count 0 2006.175.07:47:59.40#ibcon#*after write, iclass 38, count 0 2006.175.07:47:59.40#ibcon#*before return 0, iclass 38, count 0 2006.175.07:47:59.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:47:59.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:47:59.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:47:59.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:47:59.40$vc4f8/va=5,7 2006.175.07:47:59.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.07:47:59.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.07:47:59.40#ibcon#ireg 11 cls_cnt 2 2006.175.07:47:59.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:47:59.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:47:59.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:47:59.46#ibcon#enter wrdev, iclass 40, count 2 2006.175.07:47:59.46#ibcon#first serial, iclass 40, count 2 2006.175.07:47:59.46#ibcon#enter sib2, iclass 40, count 2 2006.175.07:47:59.46#ibcon#flushed, iclass 40, count 2 2006.175.07:47:59.46#ibcon#about to write, iclass 40, count 2 2006.175.07:47:59.46#ibcon#wrote, iclass 40, count 2 2006.175.07:47:59.46#ibcon#about to read 3, iclass 40, count 2 2006.175.07:47:59.48#ibcon#read 3, iclass 40, count 2 2006.175.07:47:59.48#ibcon#about to read 4, iclass 40, count 2 2006.175.07:47:59.48#ibcon#read 4, iclass 40, count 2 2006.175.07:47:59.48#ibcon#about to read 5, iclass 40, count 2 2006.175.07:47:59.48#ibcon#read 5, iclass 40, count 2 2006.175.07:47:59.48#ibcon#about to read 6, iclass 40, count 2 2006.175.07:47:59.48#ibcon#read 6, iclass 40, count 2 2006.175.07:47:59.48#ibcon#end of sib2, iclass 40, count 2 2006.175.07:47:59.48#ibcon#*mode == 0, iclass 40, count 2 2006.175.07:47:59.48#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.07:47:59.48#ibcon#[25=AT05-07\r\n] 2006.175.07:47:59.48#ibcon#*before write, iclass 40, count 2 2006.175.07:47:59.48#ibcon#enter sib2, iclass 40, count 2 2006.175.07:47:59.48#ibcon#flushed, iclass 40, count 2 2006.175.07:47:59.48#ibcon#about to write, iclass 40, count 2 2006.175.07:47:59.48#ibcon#wrote, iclass 40, count 2 2006.175.07:47:59.48#ibcon#about to read 3, iclass 40, count 2 2006.175.07:47:59.51#ibcon#read 3, iclass 40, count 2 2006.175.07:47:59.51#ibcon#about to read 4, iclass 40, count 2 2006.175.07:47:59.51#ibcon#read 4, iclass 40, count 2 2006.175.07:47:59.51#ibcon#about to read 5, iclass 40, count 2 2006.175.07:47:59.51#ibcon#read 5, iclass 40, count 2 2006.175.07:47:59.51#ibcon#about to read 6, iclass 40, count 2 2006.175.07:47:59.51#ibcon#read 6, iclass 40, count 2 2006.175.07:47:59.51#ibcon#end of sib2, iclass 40, count 2 2006.175.07:47:59.51#ibcon#*after write, iclass 40, count 2 2006.175.07:47:59.51#ibcon#*before return 0, iclass 40, count 2 2006.175.07:47:59.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:47:59.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:47:59.51#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.07:47:59.51#ibcon#ireg 7 cls_cnt 0 2006.175.07:47:59.51#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:47:59.63#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:47:59.63#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:47:59.63#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:47:59.63#ibcon#first serial, iclass 40, count 0 2006.175.07:47:59.63#ibcon#enter sib2, iclass 40, count 0 2006.175.07:47:59.63#ibcon#flushed, iclass 40, count 0 2006.175.07:47:59.63#ibcon#about to write, iclass 40, count 0 2006.175.07:47:59.63#ibcon#wrote, iclass 40, count 0 2006.175.07:47:59.63#ibcon#about to read 3, iclass 40, count 0 2006.175.07:47:59.65#ibcon#read 3, iclass 40, count 0 2006.175.07:47:59.65#ibcon#about to read 4, iclass 40, count 0 2006.175.07:47:59.65#ibcon#read 4, iclass 40, count 0 2006.175.07:47:59.65#ibcon#about to read 5, iclass 40, count 0 2006.175.07:47:59.65#ibcon#read 5, iclass 40, count 0 2006.175.07:47:59.65#ibcon#about to read 6, iclass 40, count 0 2006.175.07:47:59.65#ibcon#read 6, iclass 40, count 0 2006.175.07:47:59.65#ibcon#end of sib2, iclass 40, count 0 2006.175.07:47:59.65#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:47:59.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:47:59.65#ibcon#[25=USB\r\n] 2006.175.07:47:59.65#ibcon#*before write, iclass 40, count 0 2006.175.07:47:59.65#ibcon#enter sib2, iclass 40, count 0 2006.175.07:47:59.65#ibcon#flushed, iclass 40, count 0 2006.175.07:47:59.65#ibcon#about to write, iclass 40, count 0 2006.175.07:47:59.65#ibcon#wrote, iclass 40, count 0 2006.175.07:47:59.65#ibcon#about to read 3, iclass 40, count 0 2006.175.07:47:59.68#ibcon#read 3, iclass 40, count 0 2006.175.07:47:59.68#ibcon#about to read 4, iclass 40, count 0 2006.175.07:47:59.68#ibcon#read 4, iclass 40, count 0 2006.175.07:47:59.68#ibcon#about to read 5, iclass 40, count 0 2006.175.07:47:59.68#ibcon#read 5, iclass 40, count 0 2006.175.07:47:59.68#ibcon#about to read 6, iclass 40, count 0 2006.175.07:47:59.68#ibcon#read 6, iclass 40, count 0 2006.175.07:47:59.68#ibcon#end of sib2, iclass 40, count 0 2006.175.07:47:59.68#ibcon#*after write, iclass 40, count 0 2006.175.07:47:59.68#ibcon#*before return 0, iclass 40, count 0 2006.175.07:47:59.68#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:47:59.68#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:47:59.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:47:59.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:47:59.68$vc4f8/valo=6,772.99 2006.175.07:47:59.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:47:59.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:47:59.68#ibcon#ireg 17 cls_cnt 0 2006.175.07:47:59.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:47:59.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:47:59.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:47:59.68#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:47:59.68#ibcon#first serial, iclass 4, count 0 2006.175.07:47:59.68#ibcon#enter sib2, iclass 4, count 0 2006.175.07:47:59.68#ibcon#flushed, iclass 4, count 0 2006.175.07:47:59.68#ibcon#about to write, iclass 4, count 0 2006.175.07:47:59.68#ibcon#wrote, iclass 4, count 0 2006.175.07:47:59.68#ibcon#about to read 3, iclass 4, count 0 2006.175.07:47:59.70#ibcon#read 3, iclass 4, count 0 2006.175.07:47:59.70#ibcon#about to read 4, iclass 4, count 0 2006.175.07:47:59.70#ibcon#read 4, iclass 4, count 0 2006.175.07:47:59.70#ibcon#about to read 5, iclass 4, count 0 2006.175.07:47:59.70#ibcon#read 5, iclass 4, count 0 2006.175.07:47:59.70#ibcon#about to read 6, iclass 4, count 0 2006.175.07:47:59.70#ibcon#read 6, iclass 4, count 0 2006.175.07:47:59.70#ibcon#end of sib2, iclass 4, count 0 2006.175.07:47:59.70#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:47:59.70#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:47:59.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:47:59.70#ibcon#*before write, iclass 4, count 0 2006.175.07:47:59.70#ibcon#enter sib2, iclass 4, count 0 2006.175.07:47:59.70#ibcon#flushed, iclass 4, count 0 2006.175.07:47:59.70#ibcon#about to write, iclass 4, count 0 2006.175.07:47:59.70#ibcon#wrote, iclass 4, count 0 2006.175.07:47:59.70#ibcon#about to read 3, iclass 4, count 0 2006.175.07:47:59.74#ibcon#read 3, iclass 4, count 0 2006.175.07:47:59.74#ibcon#about to read 4, iclass 4, count 0 2006.175.07:47:59.74#ibcon#read 4, iclass 4, count 0 2006.175.07:47:59.74#ibcon#about to read 5, iclass 4, count 0 2006.175.07:47:59.74#ibcon#read 5, iclass 4, count 0 2006.175.07:47:59.74#ibcon#about to read 6, iclass 4, count 0 2006.175.07:47:59.74#ibcon#read 6, iclass 4, count 0 2006.175.07:47:59.74#ibcon#end of sib2, iclass 4, count 0 2006.175.07:47:59.74#ibcon#*after write, iclass 4, count 0 2006.175.07:47:59.74#ibcon#*before return 0, iclass 4, count 0 2006.175.07:47:59.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:47:59.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:47:59.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:47:59.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:47:59.74$vc4f8/va=6,6 2006.175.07:47:59.74#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.07:47:59.74#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.07:47:59.74#ibcon#ireg 11 cls_cnt 2 2006.175.07:47:59.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:47:59.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:47:59.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:47:59.80#ibcon#enter wrdev, iclass 6, count 2 2006.175.07:47:59.80#ibcon#first serial, iclass 6, count 2 2006.175.07:47:59.80#ibcon#enter sib2, iclass 6, count 2 2006.175.07:47:59.80#ibcon#flushed, iclass 6, count 2 2006.175.07:47:59.80#ibcon#about to write, iclass 6, count 2 2006.175.07:47:59.80#ibcon#wrote, iclass 6, count 2 2006.175.07:47:59.80#ibcon#about to read 3, iclass 6, count 2 2006.175.07:47:59.82#ibcon#read 3, iclass 6, count 2 2006.175.07:47:59.82#ibcon#about to read 4, iclass 6, count 2 2006.175.07:47:59.82#ibcon#read 4, iclass 6, count 2 2006.175.07:47:59.82#ibcon#about to read 5, iclass 6, count 2 2006.175.07:47:59.82#ibcon#read 5, iclass 6, count 2 2006.175.07:47:59.82#ibcon#about to read 6, iclass 6, count 2 2006.175.07:47:59.82#ibcon#read 6, iclass 6, count 2 2006.175.07:47:59.82#ibcon#end of sib2, iclass 6, count 2 2006.175.07:47:59.82#ibcon#*mode == 0, iclass 6, count 2 2006.175.07:47:59.82#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.07:47:59.82#ibcon#[25=AT06-06\r\n] 2006.175.07:47:59.82#ibcon#*before write, iclass 6, count 2 2006.175.07:47:59.82#ibcon#enter sib2, iclass 6, count 2 2006.175.07:47:59.82#ibcon#flushed, iclass 6, count 2 2006.175.07:47:59.82#ibcon#about to write, iclass 6, count 2 2006.175.07:47:59.82#ibcon#wrote, iclass 6, count 2 2006.175.07:47:59.82#ibcon#about to read 3, iclass 6, count 2 2006.175.07:47:59.85#ibcon#read 3, iclass 6, count 2 2006.175.07:47:59.85#ibcon#about to read 4, iclass 6, count 2 2006.175.07:47:59.85#ibcon#read 4, iclass 6, count 2 2006.175.07:47:59.85#ibcon#about to read 5, iclass 6, count 2 2006.175.07:47:59.85#ibcon#read 5, iclass 6, count 2 2006.175.07:47:59.85#ibcon#about to read 6, iclass 6, count 2 2006.175.07:47:59.85#ibcon#read 6, iclass 6, count 2 2006.175.07:47:59.85#ibcon#end of sib2, iclass 6, count 2 2006.175.07:47:59.85#ibcon#*after write, iclass 6, count 2 2006.175.07:47:59.85#ibcon#*before return 0, iclass 6, count 2 2006.175.07:47:59.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:47:59.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:47:59.85#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.07:47:59.85#ibcon#ireg 7 cls_cnt 0 2006.175.07:47:59.85#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:47:59.97#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:47:59.97#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:47:59.97#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:47:59.97#ibcon#first serial, iclass 6, count 0 2006.175.07:47:59.97#ibcon#enter sib2, iclass 6, count 0 2006.175.07:47:59.97#ibcon#flushed, iclass 6, count 0 2006.175.07:47:59.97#ibcon#about to write, iclass 6, count 0 2006.175.07:47:59.97#ibcon#wrote, iclass 6, count 0 2006.175.07:47:59.97#ibcon#about to read 3, iclass 6, count 0 2006.175.07:47:59.99#ibcon#read 3, iclass 6, count 0 2006.175.07:47:59.99#ibcon#about to read 4, iclass 6, count 0 2006.175.07:47:59.99#ibcon#read 4, iclass 6, count 0 2006.175.07:47:59.99#ibcon#about to read 5, iclass 6, count 0 2006.175.07:47:59.99#ibcon#read 5, iclass 6, count 0 2006.175.07:47:59.99#ibcon#about to read 6, iclass 6, count 0 2006.175.07:47:59.99#ibcon#read 6, iclass 6, count 0 2006.175.07:47:59.99#ibcon#end of sib2, iclass 6, count 0 2006.175.07:47:59.99#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:47:59.99#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:47:59.99#ibcon#[25=USB\r\n] 2006.175.07:47:59.99#ibcon#*before write, iclass 6, count 0 2006.175.07:47:59.99#ibcon#enter sib2, iclass 6, count 0 2006.175.07:47:59.99#ibcon#flushed, iclass 6, count 0 2006.175.07:47:59.99#ibcon#about to write, iclass 6, count 0 2006.175.07:47:59.99#ibcon#wrote, iclass 6, count 0 2006.175.07:47:59.99#ibcon#about to read 3, iclass 6, count 0 2006.175.07:48:00.02#ibcon#read 3, iclass 6, count 0 2006.175.07:48:00.02#ibcon#about to read 4, iclass 6, count 0 2006.175.07:48:00.02#ibcon#read 4, iclass 6, count 0 2006.175.07:48:00.02#ibcon#about to read 5, iclass 6, count 0 2006.175.07:48:00.02#ibcon#read 5, iclass 6, count 0 2006.175.07:48:00.02#ibcon#about to read 6, iclass 6, count 0 2006.175.07:48:00.02#ibcon#read 6, iclass 6, count 0 2006.175.07:48:00.02#ibcon#end of sib2, iclass 6, count 0 2006.175.07:48:00.02#ibcon#*after write, iclass 6, count 0 2006.175.07:48:00.02#ibcon#*before return 0, iclass 6, count 0 2006.175.07:48:00.02#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:48:00.02#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:48:00.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:48:00.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:48:00.02$vc4f8/valo=7,832.99 2006.175.07:48:00.02#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.07:48:00.02#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.07:48:00.02#ibcon#ireg 17 cls_cnt 0 2006.175.07:48:00.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:48:00.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:48:00.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:48:00.02#ibcon#enter wrdev, iclass 10, count 0 2006.175.07:48:00.02#ibcon#first serial, iclass 10, count 0 2006.175.07:48:00.02#ibcon#enter sib2, iclass 10, count 0 2006.175.07:48:00.02#ibcon#flushed, iclass 10, count 0 2006.175.07:48:00.02#ibcon#about to write, iclass 10, count 0 2006.175.07:48:00.02#ibcon#wrote, iclass 10, count 0 2006.175.07:48:00.02#ibcon#about to read 3, iclass 10, count 0 2006.175.07:48:00.04#ibcon#read 3, iclass 10, count 0 2006.175.07:48:00.04#ibcon#about to read 4, iclass 10, count 0 2006.175.07:48:00.04#ibcon#read 4, iclass 10, count 0 2006.175.07:48:00.04#ibcon#about to read 5, iclass 10, count 0 2006.175.07:48:00.04#ibcon#read 5, iclass 10, count 0 2006.175.07:48:00.04#ibcon#about to read 6, iclass 10, count 0 2006.175.07:48:00.04#ibcon#read 6, iclass 10, count 0 2006.175.07:48:00.04#ibcon#end of sib2, iclass 10, count 0 2006.175.07:48:00.04#ibcon#*mode == 0, iclass 10, count 0 2006.175.07:48:00.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.07:48:00.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:48:00.04#ibcon#*before write, iclass 10, count 0 2006.175.07:48:00.04#ibcon#enter sib2, iclass 10, count 0 2006.175.07:48:00.04#ibcon#flushed, iclass 10, count 0 2006.175.07:48:00.04#ibcon#about to write, iclass 10, count 0 2006.175.07:48:00.04#ibcon#wrote, iclass 10, count 0 2006.175.07:48:00.04#ibcon#about to read 3, iclass 10, count 0 2006.175.07:48:00.08#ibcon#read 3, iclass 10, count 0 2006.175.07:48:00.08#ibcon#about to read 4, iclass 10, count 0 2006.175.07:48:00.08#ibcon#read 4, iclass 10, count 0 2006.175.07:48:00.08#ibcon#about to read 5, iclass 10, count 0 2006.175.07:48:00.08#ibcon#read 5, iclass 10, count 0 2006.175.07:48:00.08#ibcon#about to read 6, iclass 10, count 0 2006.175.07:48:00.08#ibcon#read 6, iclass 10, count 0 2006.175.07:48:00.08#ibcon#end of sib2, iclass 10, count 0 2006.175.07:48:00.08#ibcon#*after write, iclass 10, count 0 2006.175.07:48:00.08#ibcon#*before return 0, iclass 10, count 0 2006.175.07:48:00.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:48:00.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:48:00.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.07:48:00.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.07:48:00.08$vc4f8/va=7,6 2006.175.07:48:00.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.07:48:00.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.07:48:00.08#ibcon#ireg 11 cls_cnt 2 2006.175.07:48:00.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:48:00.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:48:00.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:48:00.14#ibcon#enter wrdev, iclass 12, count 2 2006.175.07:48:00.14#ibcon#first serial, iclass 12, count 2 2006.175.07:48:00.14#ibcon#enter sib2, iclass 12, count 2 2006.175.07:48:00.14#ibcon#flushed, iclass 12, count 2 2006.175.07:48:00.14#ibcon#about to write, iclass 12, count 2 2006.175.07:48:00.14#ibcon#wrote, iclass 12, count 2 2006.175.07:48:00.14#ibcon#about to read 3, iclass 12, count 2 2006.175.07:48:00.16#ibcon#read 3, iclass 12, count 2 2006.175.07:48:00.16#ibcon#about to read 4, iclass 12, count 2 2006.175.07:48:00.16#ibcon#read 4, iclass 12, count 2 2006.175.07:48:00.16#ibcon#about to read 5, iclass 12, count 2 2006.175.07:48:00.16#ibcon#read 5, iclass 12, count 2 2006.175.07:48:00.16#ibcon#about to read 6, iclass 12, count 2 2006.175.07:48:00.16#ibcon#read 6, iclass 12, count 2 2006.175.07:48:00.16#ibcon#end of sib2, iclass 12, count 2 2006.175.07:48:00.16#ibcon#*mode == 0, iclass 12, count 2 2006.175.07:48:00.16#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.07:48:00.16#ibcon#[25=AT07-06\r\n] 2006.175.07:48:00.16#ibcon#*before write, iclass 12, count 2 2006.175.07:48:00.16#ibcon#enter sib2, iclass 12, count 2 2006.175.07:48:00.16#ibcon#flushed, iclass 12, count 2 2006.175.07:48:00.16#ibcon#about to write, iclass 12, count 2 2006.175.07:48:00.16#ibcon#wrote, iclass 12, count 2 2006.175.07:48:00.16#ibcon#about to read 3, iclass 12, count 2 2006.175.07:48:00.19#ibcon#read 3, iclass 12, count 2 2006.175.07:48:00.19#ibcon#about to read 4, iclass 12, count 2 2006.175.07:48:00.19#ibcon#read 4, iclass 12, count 2 2006.175.07:48:00.19#ibcon#about to read 5, iclass 12, count 2 2006.175.07:48:00.19#ibcon#read 5, iclass 12, count 2 2006.175.07:48:00.19#ibcon#about to read 6, iclass 12, count 2 2006.175.07:48:00.19#ibcon#read 6, iclass 12, count 2 2006.175.07:48:00.19#ibcon#end of sib2, iclass 12, count 2 2006.175.07:48:00.19#ibcon#*after write, iclass 12, count 2 2006.175.07:48:00.19#ibcon#*before return 0, iclass 12, count 2 2006.175.07:48:00.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:48:00.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:48:00.19#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.07:48:00.19#ibcon#ireg 7 cls_cnt 0 2006.175.07:48:00.19#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:48:00.31#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:48:00.31#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:48:00.31#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:48:00.31#ibcon#first serial, iclass 12, count 0 2006.175.07:48:00.31#ibcon#enter sib2, iclass 12, count 0 2006.175.07:48:00.31#ibcon#flushed, iclass 12, count 0 2006.175.07:48:00.31#ibcon#about to write, iclass 12, count 0 2006.175.07:48:00.31#ibcon#wrote, iclass 12, count 0 2006.175.07:48:00.31#ibcon#about to read 3, iclass 12, count 0 2006.175.07:48:00.33#ibcon#read 3, iclass 12, count 0 2006.175.07:48:00.33#ibcon#about to read 4, iclass 12, count 0 2006.175.07:48:00.33#ibcon#read 4, iclass 12, count 0 2006.175.07:48:00.33#ibcon#about to read 5, iclass 12, count 0 2006.175.07:48:00.33#ibcon#read 5, iclass 12, count 0 2006.175.07:48:00.33#ibcon#about to read 6, iclass 12, count 0 2006.175.07:48:00.33#ibcon#read 6, iclass 12, count 0 2006.175.07:48:00.33#ibcon#end of sib2, iclass 12, count 0 2006.175.07:48:00.33#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:48:00.33#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:48:00.33#ibcon#[25=USB\r\n] 2006.175.07:48:00.33#ibcon#*before write, iclass 12, count 0 2006.175.07:48:00.33#ibcon#enter sib2, iclass 12, count 0 2006.175.07:48:00.33#ibcon#flushed, iclass 12, count 0 2006.175.07:48:00.33#ibcon#about to write, iclass 12, count 0 2006.175.07:48:00.33#ibcon#wrote, iclass 12, count 0 2006.175.07:48:00.33#ibcon#about to read 3, iclass 12, count 0 2006.175.07:48:00.36#ibcon#read 3, iclass 12, count 0 2006.175.07:48:00.36#ibcon#about to read 4, iclass 12, count 0 2006.175.07:48:00.36#ibcon#read 4, iclass 12, count 0 2006.175.07:48:00.36#ibcon#about to read 5, iclass 12, count 0 2006.175.07:48:00.36#ibcon#read 5, iclass 12, count 0 2006.175.07:48:00.36#ibcon#about to read 6, iclass 12, count 0 2006.175.07:48:00.36#ibcon#read 6, iclass 12, count 0 2006.175.07:48:00.36#ibcon#end of sib2, iclass 12, count 0 2006.175.07:48:00.36#ibcon#*after write, iclass 12, count 0 2006.175.07:48:00.36#ibcon#*before return 0, iclass 12, count 0 2006.175.07:48:00.36#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:48:00.36#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:48:00.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:48:00.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:48:00.36$vc4f8/valo=8,852.99 2006.175.07:48:00.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.07:48:00.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.07:48:00.36#ibcon#ireg 17 cls_cnt 0 2006.175.07:48:00.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:48:00.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:48:00.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:48:00.36#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:48:00.36#ibcon#first serial, iclass 14, count 0 2006.175.07:48:00.36#ibcon#enter sib2, iclass 14, count 0 2006.175.07:48:00.36#ibcon#flushed, iclass 14, count 0 2006.175.07:48:00.36#ibcon#about to write, iclass 14, count 0 2006.175.07:48:00.36#ibcon#wrote, iclass 14, count 0 2006.175.07:48:00.36#ibcon#about to read 3, iclass 14, count 0 2006.175.07:48:00.38#ibcon#read 3, iclass 14, count 0 2006.175.07:48:00.38#ibcon#about to read 4, iclass 14, count 0 2006.175.07:48:00.38#ibcon#read 4, iclass 14, count 0 2006.175.07:48:00.38#ibcon#about to read 5, iclass 14, count 0 2006.175.07:48:00.38#ibcon#read 5, iclass 14, count 0 2006.175.07:48:00.38#ibcon#about to read 6, iclass 14, count 0 2006.175.07:48:00.38#ibcon#read 6, iclass 14, count 0 2006.175.07:48:00.38#ibcon#end of sib2, iclass 14, count 0 2006.175.07:48:00.38#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:48:00.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:48:00.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:48:00.38#ibcon#*before write, iclass 14, count 0 2006.175.07:48:00.38#ibcon#enter sib2, iclass 14, count 0 2006.175.07:48:00.38#ibcon#flushed, iclass 14, count 0 2006.175.07:48:00.38#ibcon#about to write, iclass 14, count 0 2006.175.07:48:00.38#ibcon#wrote, iclass 14, count 0 2006.175.07:48:00.38#ibcon#about to read 3, iclass 14, count 0 2006.175.07:48:00.42#ibcon#read 3, iclass 14, count 0 2006.175.07:48:00.42#ibcon#about to read 4, iclass 14, count 0 2006.175.07:48:00.42#ibcon#read 4, iclass 14, count 0 2006.175.07:48:00.42#ibcon#about to read 5, iclass 14, count 0 2006.175.07:48:00.42#ibcon#read 5, iclass 14, count 0 2006.175.07:48:00.42#ibcon#about to read 6, iclass 14, count 0 2006.175.07:48:00.42#ibcon#read 6, iclass 14, count 0 2006.175.07:48:00.42#ibcon#end of sib2, iclass 14, count 0 2006.175.07:48:00.42#ibcon#*after write, iclass 14, count 0 2006.175.07:48:00.42#ibcon#*before return 0, iclass 14, count 0 2006.175.07:48:00.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:48:00.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:48:00.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:48:00.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:48:00.42$vc4f8/va=8,6 2006.175.07:48:00.42#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.07:48:00.42#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.07:48:00.42#ibcon#ireg 11 cls_cnt 2 2006.175.07:48:00.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:48:00.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:48:00.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:48:00.48#ibcon#enter wrdev, iclass 16, count 2 2006.175.07:48:00.48#ibcon#first serial, iclass 16, count 2 2006.175.07:48:00.48#ibcon#enter sib2, iclass 16, count 2 2006.175.07:48:00.48#ibcon#flushed, iclass 16, count 2 2006.175.07:48:00.48#ibcon#about to write, iclass 16, count 2 2006.175.07:48:00.48#ibcon#wrote, iclass 16, count 2 2006.175.07:48:00.48#ibcon#about to read 3, iclass 16, count 2 2006.175.07:48:00.50#ibcon#read 3, iclass 16, count 2 2006.175.07:48:00.50#ibcon#about to read 4, iclass 16, count 2 2006.175.07:48:00.50#ibcon#read 4, iclass 16, count 2 2006.175.07:48:00.50#ibcon#about to read 5, iclass 16, count 2 2006.175.07:48:00.50#ibcon#read 5, iclass 16, count 2 2006.175.07:48:00.50#ibcon#about to read 6, iclass 16, count 2 2006.175.07:48:00.50#ibcon#read 6, iclass 16, count 2 2006.175.07:48:00.50#ibcon#end of sib2, iclass 16, count 2 2006.175.07:48:00.50#ibcon#*mode == 0, iclass 16, count 2 2006.175.07:48:00.50#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.07:48:00.50#ibcon#[25=AT08-06\r\n] 2006.175.07:48:00.50#ibcon#*before write, iclass 16, count 2 2006.175.07:48:00.50#ibcon#enter sib2, iclass 16, count 2 2006.175.07:48:00.50#ibcon#flushed, iclass 16, count 2 2006.175.07:48:00.50#ibcon#about to write, iclass 16, count 2 2006.175.07:48:00.50#ibcon#wrote, iclass 16, count 2 2006.175.07:48:00.50#ibcon#about to read 3, iclass 16, count 2 2006.175.07:48:00.53#ibcon#read 3, iclass 16, count 2 2006.175.07:48:00.53#ibcon#about to read 4, iclass 16, count 2 2006.175.07:48:00.53#ibcon#read 4, iclass 16, count 2 2006.175.07:48:00.53#ibcon#about to read 5, iclass 16, count 2 2006.175.07:48:00.53#ibcon#read 5, iclass 16, count 2 2006.175.07:48:00.53#ibcon#about to read 6, iclass 16, count 2 2006.175.07:48:00.53#ibcon#read 6, iclass 16, count 2 2006.175.07:48:00.53#ibcon#end of sib2, iclass 16, count 2 2006.175.07:48:00.53#ibcon#*after write, iclass 16, count 2 2006.175.07:48:00.53#ibcon#*before return 0, iclass 16, count 2 2006.175.07:48:00.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:48:00.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:48:00.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.07:48:00.53#ibcon#ireg 7 cls_cnt 0 2006.175.07:48:00.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:48:00.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:48:00.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:48:00.65#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:48:00.65#ibcon#first serial, iclass 16, count 0 2006.175.07:48:00.65#ibcon#enter sib2, iclass 16, count 0 2006.175.07:48:00.65#ibcon#flushed, iclass 16, count 0 2006.175.07:48:00.65#ibcon#about to write, iclass 16, count 0 2006.175.07:48:00.65#ibcon#wrote, iclass 16, count 0 2006.175.07:48:00.65#ibcon#about to read 3, iclass 16, count 0 2006.175.07:48:00.67#ibcon#read 3, iclass 16, count 0 2006.175.07:48:00.67#ibcon#about to read 4, iclass 16, count 0 2006.175.07:48:00.67#ibcon#read 4, iclass 16, count 0 2006.175.07:48:00.67#ibcon#about to read 5, iclass 16, count 0 2006.175.07:48:00.67#ibcon#read 5, iclass 16, count 0 2006.175.07:48:00.67#ibcon#about to read 6, iclass 16, count 0 2006.175.07:48:00.67#ibcon#read 6, iclass 16, count 0 2006.175.07:48:00.67#ibcon#end of sib2, iclass 16, count 0 2006.175.07:48:00.67#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:48:00.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:48:00.67#ibcon#[25=USB\r\n] 2006.175.07:48:00.67#ibcon#*before write, iclass 16, count 0 2006.175.07:48:00.67#ibcon#enter sib2, iclass 16, count 0 2006.175.07:48:00.67#ibcon#flushed, iclass 16, count 0 2006.175.07:48:00.67#ibcon#about to write, iclass 16, count 0 2006.175.07:48:00.67#ibcon#wrote, iclass 16, count 0 2006.175.07:48:00.67#ibcon#about to read 3, iclass 16, count 0 2006.175.07:48:00.70#ibcon#read 3, iclass 16, count 0 2006.175.07:48:00.70#ibcon#about to read 4, iclass 16, count 0 2006.175.07:48:00.70#ibcon#read 4, iclass 16, count 0 2006.175.07:48:00.70#ibcon#about to read 5, iclass 16, count 0 2006.175.07:48:00.70#ibcon#read 5, iclass 16, count 0 2006.175.07:48:00.70#ibcon#about to read 6, iclass 16, count 0 2006.175.07:48:00.70#ibcon#read 6, iclass 16, count 0 2006.175.07:48:00.70#ibcon#end of sib2, iclass 16, count 0 2006.175.07:48:00.70#ibcon#*after write, iclass 16, count 0 2006.175.07:48:00.70#ibcon#*before return 0, iclass 16, count 0 2006.175.07:48:00.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:48:00.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:48:00.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:48:00.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:48:00.70$vc4f8/vblo=1,632.99 2006.175.07:48:00.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.07:48:00.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.07:48:00.70#ibcon#ireg 17 cls_cnt 0 2006.175.07:48:00.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:48:00.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:48:00.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:48:00.70#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:48:00.70#ibcon#first serial, iclass 18, count 0 2006.175.07:48:00.70#ibcon#enter sib2, iclass 18, count 0 2006.175.07:48:00.70#ibcon#flushed, iclass 18, count 0 2006.175.07:48:00.70#ibcon#about to write, iclass 18, count 0 2006.175.07:48:00.70#ibcon#wrote, iclass 18, count 0 2006.175.07:48:00.70#ibcon#about to read 3, iclass 18, count 0 2006.175.07:48:00.72#ibcon#read 3, iclass 18, count 0 2006.175.07:48:00.72#ibcon#about to read 4, iclass 18, count 0 2006.175.07:48:00.72#ibcon#read 4, iclass 18, count 0 2006.175.07:48:00.72#ibcon#about to read 5, iclass 18, count 0 2006.175.07:48:00.72#ibcon#read 5, iclass 18, count 0 2006.175.07:48:00.72#ibcon#about to read 6, iclass 18, count 0 2006.175.07:48:00.72#ibcon#read 6, iclass 18, count 0 2006.175.07:48:00.72#ibcon#end of sib2, iclass 18, count 0 2006.175.07:48:00.72#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:48:00.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:48:00.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:48:00.72#ibcon#*before write, iclass 18, count 0 2006.175.07:48:00.72#ibcon#enter sib2, iclass 18, count 0 2006.175.07:48:00.72#ibcon#flushed, iclass 18, count 0 2006.175.07:48:00.72#ibcon#about to write, iclass 18, count 0 2006.175.07:48:00.72#ibcon#wrote, iclass 18, count 0 2006.175.07:48:00.72#ibcon#about to read 3, iclass 18, count 0 2006.175.07:48:00.76#ibcon#read 3, iclass 18, count 0 2006.175.07:48:00.76#ibcon#about to read 4, iclass 18, count 0 2006.175.07:48:00.76#ibcon#read 4, iclass 18, count 0 2006.175.07:48:00.76#ibcon#about to read 5, iclass 18, count 0 2006.175.07:48:00.76#ibcon#read 5, iclass 18, count 0 2006.175.07:48:00.76#ibcon#about to read 6, iclass 18, count 0 2006.175.07:48:00.76#ibcon#read 6, iclass 18, count 0 2006.175.07:48:00.76#ibcon#end of sib2, iclass 18, count 0 2006.175.07:48:00.76#ibcon#*after write, iclass 18, count 0 2006.175.07:48:00.76#ibcon#*before return 0, iclass 18, count 0 2006.175.07:48:00.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:48:00.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:48:00.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:48:00.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:48:00.76$vc4f8/vb=1,4 2006.175.07:48:00.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.175.07:48:00.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.175.07:48:00.76#ibcon#ireg 11 cls_cnt 2 2006.175.07:48:00.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:48:00.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:48:00.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:48:00.76#ibcon#enter wrdev, iclass 20, count 2 2006.175.07:48:00.76#ibcon#first serial, iclass 20, count 2 2006.175.07:48:00.76#ibcon#enter sib2, iclass 20, count 2 2006.175.07:48:00.76#ibcon#flushed, iclass 20, count 2 2006.175.07:48:00.76#ibcon#about to write, iclass 20, count 2 2006.175.07:48:00.76#ibcon#wrote, iclass 20, count 2 2006.175.07:48:00.76#ibcon#about to read 3, iclass 20, count 2 2006.175.07:48:00.78#ibcon#read 3, iclass 20, count 2 2006.175.07:48:00.78#ibcon#about to read 4, iclass 20, count 2 2006.175.07:48:00.78#ibcon#read 4, iclass 20, count 2 2006.175.07:48:00.78#ibcon#about to read 5, iclass 20, count 2 2006.175.07:48:00.78#ibcon#read 5, iclass 20, count 2 2006.175.07:48:00.78#ibcon#about to read 6, iclass 20, count 2 2006.175.07:48:00.78#ibcon#read 6, iclass 20, count 2 2006.175.07:48:00.78#ibcon#end of sib2, iclass 20, count 2 2006.175.07:48:00.78#ibcon#*mode == 0, iclass 20, count 2 2006.175.07:48:00.78#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.175.07:48:00.78#ibcon#[27=AT01-04\r\n] 2006.175.07:48:00.78#ibcon#*before write, iclass 20, count 2 2006.175.07:48:00.78#ibcon#enter sib2, iclass 20, count 2 2006.175.07:48:00.78#ibcon#flushed, iclass 20, count 2 2006.175.07:48:00.78#ibcon#about to write, iclass 20, count 2 2006.175.07:48:00.78#ibcon#wrote, iclass 20, count 2 2006.175.07:48:00.78#ibcon#about to read 3, iclass 20, count 2 2006.175.07:48:00.81#ibcon#read 3, iclass 20, count 2 2006.175.07:48:00.81#ibcon#about to read 4, iclass 20, count 2 2006.175.07:48:00.81#ibcon#read 4, iclass 20, count 2 2006.175.07:48:00.81#ibcon#about to read 5, iclass 20, count 2 2006.175.07:48:00.81#ibcon#read 5, iclass 20, count 2 2006.175.07:48:00.81#ibcon#about to read 6, iclass 20, count 2 2006.175.07:48:00.81#ibcon#read 6, iclass 20, count 2 2006.175.07:48:00.81#ibcon#end of sib2, iclass 20, count 2 2006.175.07:48:00.81#ibcon#*after write, iclass 20, count 2 2006.175.07:48:00.81#ibcon#*before return 0, iclass 20, count 2 2006.175.07:48:00.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:48:00.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:48:00.81#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.175.07:48:00.81#ibcon#ireg 7 cls_cnt 0 2006.175.07:48:00.81#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:48:00.93#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:48:00.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:48:00.93#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:48:00.93#ibcon#first serial, iclass 20, count 0 2006.175.07:48:00.93#ibcon#enter sib2, iclass 20, count 0 2006.175.07:48:00.93#ibcon#flushed, iclass 20, count 0 2006.175.07:48:00.93#ibcon#about to write, iclass 20, count 0 2006.175.07:48:00.93#ibcon#wrote, iclass 20, count 0 2006.175.07:48:00.93#ibcon#about to read 3, iclass 20, count 0 2006.175.07:48:00.95#ibcon#read 3, iclass 20, count 0 2006.175.07:48:00.95#ibcon#about to read 4, iclass 20, count 0 2006.175.07:48:00.95#ibcon#read 4, iclass 20, count 0 2006.175.07:48:00.95#ibcon#about to read 5, iclass 20, count 0 2006.175.07:48:00.95#ibcon#read 5, iclass 20, count 0 2006.175.07:48:00.95#ibcon#about to read 6, iclass 20, count 0 2006.175.07:48:00.95#ibcon#read 6, iclass 20, count 0 2006.175.07:48:00.95#ibcon#end of sib2, iclass 20, count 0 2006.175.07:48:00.95#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:48:00.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:48:00.95#ibcon#[27=USB\r\n] 2006.175.07:48:00.95#ibcon#*before write, iclass 20, count 0 2006.175.07:48:00.95#ibcon#enter sib2, iclass 20, count 0 2006.175.07:48:00.95#ibcon#flushed, iclass 20, count 0 2006.175.07:48:00.95#ibcon#about to write, iclass 20, count 0 2006.175.07:48:00.95#ibcon#wrote, iclass 20, count 0 2006.175.07:48:00.95#ibcon#about to read 3, iclass 20, count 0 2006.175.07:48:00.98#ibcon#read 3, iclass 20, count 0 2006.175.07:48:00.98#ibcon#about to read 4, iclass 20, count 0 2006.175.07:48:00.98#ibcon#read 4, iclass 20, count 0 2006.175.07:48:00.98#ibcon#about to read 5, iclass 20, count 0 2006.175.07:48:00.98#ibcon#read 5, iclass 20, count 0 2006.175.07:48:00.98#ibcon#about to read 6, iclass 20, count 0 2006.175.07:48:00.98#ibcon#read 6, iclass 20, count 0 2006.175.07:48:00.98#ibcon#end of sib2, iclass 20, count 0 2006.175.07:48:00.98#ibcon#*after write, iclass 20, count 0 2006.175.07:48:00.98#ibcon#*before return 0, iclass 20, count 0 2006.175.07:48:00.98#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:48:00.98#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:48:00.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:48:00.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:48:00.98$vc4f8/vblo=2,640.99 2006.175.07:48:00.98#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.07:48:00.98#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.07:48:00.98#ibcon#ireg 17 cls_cnt 0 2006.175.07:48:00.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:48:00.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:48:00.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:48:00.98#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:48:00.98#ibcon#first serial, iclass 22, count 0 2006.175.07:48:00.98#ibcon#enter sib2, iclass 22, count 0 2006.175.07:48:00.98#ibcon#flushed, iclass 22, count 0 2006.175.07:48:00.98#ibcon#about to write, iclass 22, count 0 2006.175.07:48:00.98#ibcon#wrote, iclass 22, count 0 2006.175.07:48:00.98#ibcon#about to read 3, iclass 22, count 0 2006.175.07:48:01.00#ibcon#read 3, iclass 22, count 0 2006.175.07:48:01.00#ibcon#about to read 4, iclass 22, count 0 2006.175.07:48:01.00#ibcon#read 4, iclass 22, count 0 2006.175.07:48:01.00#ibcon#about to read 5, iclass 22, count 0 2006.175.07:48:01.00#ibcon#read 5, iclass 22, count 0 2006.175.07:48:01.00#ibcon#about to read 6, iclass 22, count 0 2006.175.07:48:01.00#ibcon#read 6, iclass 22, count 0 2006.175.07:48:01.00#ibcon#end of sib2, iclass 22, count 0 2006.175.07:48:01.00#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:48:01.00#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:48:01.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:48:01.00#ibcon#*before write, iclass 22, count 0 2006.175.07:48:01.00#ibcon#enter sib2, iclass 22, count 0 2006.175.07:48:01.00#ibcon#flushed, iclass 22, count 0 2006.175.07:48:01.00#ibcon#about to write, iclass 22, count 0 2006.175.07:48:01.00#ibcon#wrote, iclass 22, count 0 2006.175.07:48:01.00#ibcon#about to read 3, iclass 22, count 0 2006.175.07:48:01.04#ibcon#read 3, iclass 22, count 0 2006.175.07:48:01.04#ibcon#about to read 4, iclass 22, count 0 2006.175.07:48:01.04#ibcon#read 4, iclass 22, count 0 2006.175.07:48:01.04#ibcon#about to read 5, iclass 22, count 0 2006.175.07:48:01.04#ibcon#read 5, iclass 22, count 0 2006.175.07:48:01.04#ibcon#about to read 6, iclass 22, count 0 2006.175.07:48:01.04#ibcon#read 6, iclass 22, count 0 2006.175.07:48:01.04#ibcon#end of sib2, iclass 22, count 0 2006.175.07:48:01.04#ibcon#*after write, iclass 22, count 0 2006.175.07:48:01.04#ibcon#*before return 0, iclass 22, count 0 2006.175.07:48:01.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:48:01.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:48:01.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:48:01.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:48:01.04$vc4f8/vb=2,4 2006.175.07:48:01.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.07:48:01.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.07:48:01.04#ibcon#ireg 11 cls_cnt 2 2006.175.07:48:01.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:48:01.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:48:01.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:48:01.10#ibcon#enter wrdev, iclass 24, count 2 2006.175.07:48:01.10#ibcon#first serial, iclass 24, count 2 2006.175.07:48:01.10#ibcon#enter sib2, iclass 24, count 2 2006.175.07:48:01.10#ibcon#flushed, iclass 24, count 2 2006.175.07:48:01.10#ibcon#about to write, iclass 24, count 2 2006.175.07:48:01.10#ibcon#wrote, iclass 24, count 2 2006.175.07:48:01.10#ibcon#about to read 3, iclass 24, count 2 2006.175.07:48:01.12#ibcon#read 3, iclass 24, count 2 2006.175.07:48:01.12#ibcon#about to read 4, iclass 24, count 2 2006.175.07:48:01.12#ibcon#read 4, iclass 24, count 2 2006.175.07:48:01.12#ibcon#about to read 5, iclass 24, count 2 2006.175.07:48:01.12#ibcon#read 5, iclass 24, count 2 2006.175.07:48:01.12#ibcon#about to read 6, iclass 24, count 2 2006.175.07:48:01.12#ibcon#read 6, iclass 24, count 2 2006.175.07:48:01.12#ibcon#end of sib2, iclass 24, count 2 2006.175.07:48:01.12#ibcon#*mode == 0, iclass 24, count 2 2006.175.07:48:01.12#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.07:48:01.12#ibcon#[27=AT02-04\r\n] 2006.175.07:48:01.12#ibcon#*before write, iclass 24, count 2 2006.175.07:48:01.12#ibcon#enter sib2, iclass 24, count 2 2006.175.07:48:01.12#ibcon#flushed, iclass 24, count 2 2006.175.07:48:01.12#ibcon#about to write, iclass 24, count 2 2006.175.07:48:01.12#ibcon#wrote, iclass 24, count 2 2006.175.07:48:01.12#ibcon#about to read 3, iclass 24, count 2 2006.175.07:48:01.15#ibcon#read 3, iclass 24, count 2 2006.175.07:48:01.15#ibcon#about to read 4, iclass 24, count 2 2006.175.07:48:01.15#ibcon#read 4, iclass 24, count 2 2006.175.07:48:01.15#ibcon#about to read 5, iclass 24, count 2 2006.175.07:48:01.15#ibcon#read 5, iclass 24, count 2 2006.175.07:48:01.15#ibcon#about to read 6, iclass 24, count 2 2006.175.07:48:01.15#ibcon#read 6, iclass 24, count 2 2006.175.07:48:01.15#ibcon#end of sib2, iclass 24, count 2 2006.175.07:48:01.15#ibcon#*after write, iclass 24, count 2 2006.175.07:48:01.15#ibcon#*before return 0, iclass 24, count 2 2006.175.07:48:01.15#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:48:01.15#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:48:01.15#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.07:48:01.15#ibcon#ireg 7 cls_cnt 0 2006.175.07:48:01.15#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:48:01.27#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:48:01.27#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:48:01.27#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:48:01.27#ibcon#first serial, iclass 24, count 0 2006.175.07:48:01.27#ibcon#enter sib2, iclass 24, count 0 2006.175.07:48:01.27#ibcon#flushed, iclass 24, count 0 2006.175.07:48:01.27#ibcon#about to write, iclass 24, count 0 2006.175.07:48:01.27#ibcon#wrote, iclass 24, count 0 2006.175.07:48:01.27#ibcon#about to read 3, iclass 24, count 0 2006.175.07:48:01.29#ibcon#read 3, iclass 24, count 0 2006.175.07:48:01.29#ibcon#about to read 4, iclass 24, count 0 2006.175.07:48:01.29#ibcon#read 4, iclass 24, count 0 2006.175.07:48:01.29#ibcon#about to read 5, iclass 24, count 0 2006.175.07:48:01.29#ibcon#read 5, iclass 24, count 0 2006.175.07:48:01.29#ibcon#about to read 6, iclass 24, count 0 2006.175.07:48:01.29#ibcon#read 6, iclass 24, count 0 2006.175.07:48:01.29#ibcon#end of sib2, iclass 24, count 0 2006.175.07:48:01.29#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:48:01.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:48:01.29#ibcon#[27=USB\r\n] 2006.175.07:48:01.29#ibcon#*before write, iclass 24, count 0 2006.175.07:48:01.29#ibcon#enter sib2, iclass 24, count 0 2006.175.07:48:01.29#ibcon#flushed, iclass 24, count 0 2006.175.07:48:01.29#ibcon#about to write, iclass 24, count 0 2006.175.07:48:01.29#ibcon#wrote, iclass 24, count 0 2006.175.07:48:01.29#ibcon#about to read 3, iclass 24, count 0 2006.175.07:48:01.32#ibcon#read 3, iclass 24, count 0 2006.175.07:48:01.32#ibcon#about to read 4, iclass 24, count 0 2006.175.07:48:01.32#ibcon#read 4, iclass 24, count 0 2006.175.07:48:01.32#ibcon#about to read 5, iclass 24, count 0 2006.175.07:48:01.32#ibcon#read 5, iclass 24, count 0 2006.175.07:48:01.32#ibcon#about to read 6, iclass 24, count 0 2006.175.07:48:01.32#ibcon#read 6, iclass 24, count 0 2006.175.07:48:01.32#ibcon#end of sib2, iclass 24, count 0 2006.175.07:48:01.32#ibcon#*after write, iclass 24, count 0 2006.175.07:48:01.32#ibcon#*before return 0, iclass 24, count 0 2006.175.07:48:01.32#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:48:01.32#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:48:01.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:48:01.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:48:01.32$vc4f8/vblo=3,656.99 2006.175.07:48:01.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.07:48:01.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.07:48:01.32#ibcon#ireg 17 cls_cnt 0 2006.175.07:48:01.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:48:01.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:48:01.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:48:01.32#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:48:01.32#ibcon#first serial, iclass 26, count 0 2006.175.07:48:01.32#ibcon#enter sib2, iclass 26, count 0 2006.175.07:48:01.32#ibcon#flushed, iclass 26, count 0 2006.175.07:48:01.32#ibcon#about to write, iclass 26, count 0 2006.175.07:48:01.32#ibcon#wrote, iclass 26, count 0 2006.175.07:48:01.32#ibcon#about to read 3, iclass 26, count 0 2006.175.07:48:01.34#ibcon#read 3, iclass 26, count 0 2006.175.07:48:01.34#ibcon#about to read 4, iclass 26, count 0 2006.175.07:48:01.34#ibcon#read 4, iclass 26, count 0 2006.175.07:48:01.34#ibcon#about to read 5, iclass 26, count 0 2006.175.07:48:01.34#ibcon#read 5, iclass 26, count 0 2006.175.07:48:01.34#ibcon#about to read 6, iclass 26, count 0 2006.175.07:48:01.34#ibcon#read 6, iclass 26, count 0 2006.175.07:48:01.34#ibcon#end of sib2, iclass 26, count 0 2006.175.07:48:01.34#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:48:01.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:48:01.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:48:01.34#ibcon#*before write, iclass 26, count 0 2006.175.07:48:01.34#ibcon#enter sib2, iclass 26, count 0 2006.175.07:48:01.34#ibcon#flushed, iclass 26, count 0 2006.175.07:48:01.34#ibcon#about to write, iclass 26, count 0 2006.175.07:48:01.34#ibcon#wrote, iclass 26, count 0 2006.175.07:48:01.34#ibcon#about to read 3, iclass 26, count 0 2006.175.07:48:01.38#ibcon#read 3, iclass 26, count 0 2006.175.07:48:01.38#ibcon#about to read 4, iclass 26, count 0 2006.175.07:48:01.38#ibcon#read 4, iclass 26, count 0 2006.175.07:48:01.38#ibcon#about to read 5, iclass 26, count 0 2006.175.07:48:01.38#ibcon#read 5, iclass 26, count 0 2006.175.07:48:01.38#ibcon#about to read 6, iclass 26, count 0 2006.175.07:48:01.38#ibcon#read 6, iclass 26, count 0 2006.175.07:48:01.38#ibcon#end of sib2, iclass 26, count 0 2006.175.07:48:01.38#ibcon#*after write, iclass 26, count 0 2006.175.07:48:01.38#ibcon#*before return 0, iclass 26, count 0 2006.175.07:48:01.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:48:01.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:48:01.38#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:48:01.38#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:48:01.38$vc4f8/vb=3,4 2006.175.07:48:01.38#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.07:48:01.38#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.07:48:01.38#ibcon#ireg 11 cls_cnt 2 2006.175.07:48:01.38#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:48:01.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:48:01.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:48:01.44#ibcon#enter wrdev, iclass 28, count 2 2006.175.07:48:01.44#ibcon#first serial, iclass 28, count 2 2006.175.07:48:01.44#ibcon#enter sib2, iclass 28, count 2 2006.175.07:48:01.44#ibcon#flushed, iclass 28, count 2 2006.175.07:48:01.44#ibcon#about to write, iclass 28, count 2 2006.175.07:48:01.44#ibcon#wrote, iclass 28, count 2 2006.175.07:48:01.44#ibcon#about to read 3, iclass 28, count 2 2006.175.07:48:01.46#ibcon#read 3, iclass 28, count 2 2006.175.07:48:01.46#ibcon#about to read 4, iclass 28, count 2 2006.175.07:48:01.46#ibcon#read 4, iclass 28, count 2 2006.175.07:48:01.46#ibcon#about to read 5, iclass 28, count 2 2006.175.07:48:01.46#ibcon#read 5, iclass 28, count 2 2006.175.07:48:01.46#ibcon#about to read 6, iclass 28, count 2 2006.175.07:48:01.46#ibcon#read 6, iclass 28, count 2 2006.175.07:48:01.46#ibcon#end of sib2, iclass 28, count 2 2006.175.07:48:01.46#ibcon#*mode == 0, iclass 28, count 2 2006.175.07:48:01.46#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.07:48:01.46#ibcon#[27=AT03-04\r\n] 2006.175.07:48:01.46#ibcon#*before write, iclass 28, count 2 2006.175.07:48:01.46#ibcon#enter sib2, iclass 28, count 2 2006.175.07:48:01.46#ibcon#flushed, iclass 28, count 2 2006.175.07:48:01.46#ibcon#about to write, iclass 28, count 2 2006.175.07:48:01.46#ibcon#wrote, iclass 28, count 2 2006.175.07:48:01.46#ibcon#about to read 3, iclass 28, count 2 2006.175.07:48:01.49#ibcon#read 3, iclass 28, count 2 2006.175.07:48:01.49#ibcon#about to read 4, iclass 28, count 2 2006.175.07:48:01.49#ibcon#read 4, iclass 28, count 2 2006.175.07:48:01.49#ibcon#about to read 5, iclass 28, count 2 2006.175.07:48:01.49#ibcon#read 5, iclass 28, count 2 2006.175.07:48:01.49#ibcon#about to read 6, iclass 28, count 2 2006.175.07:48:01.49#ibcon#read 6, iclass 28, count 2 2006.175.07:48:01.49#ibcon#end of sib2, iclass 28, count 2 2006.175.07:48:01.49#ibcon#*after write, iclass 28, count 2 2006.175.07:48:01.49#ibcon#*before return 0, iclass 28, count 2 2006.175.07:48:01.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:48:01.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:48:01.49#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.07:48:01.49#ibcon#ireg 7 cls_cnt 0 2006.175.07:48:01.49#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:48:01.61#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:48:01.61#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:48:01.61#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:48:01.61#ibcon#first serial, iclass 28, count 0 2006.175.07:48:01.61#ibcon#enter sib2, iclass 28, count 0 2006.175.07:48:01.61#ibcon#flushed, iclass 28, count 0 2006.175.07:48:01.61#ibcon#about to write, iclass 28, count 0 2006.175.07:48:01.61#ibcon#wrote, iclass 28, count 0 2006.175.07:48:01.61#ibcon#about to read 3, iclass 28, count 0 2006.175.07:48:01.63#ibcon#read 3, iclass 28, count 0 2006.175.07:48:01.63#ibcon#about to read 4, iclass 28, count 0 2006.175.07:48:01.63#ibcon#read 4, iclass 28, count 0 2006.175.07:48:01.63#ibcon#about to read 5, iclass 28, count 0 2006.175.07:48:01.63#ibcon#read 5, iclass 28, count 0 2006.175.07:48:01.63#ibcon#about to read 6, iclass 28, count 0 2006.175.07:48:01.63#ibcon#read 6, iclass 28, count 0 2006.175.07:48:01.63#ibcon#end of sib2, iclass 28, count 0 2006.175.07:48:01.63#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:48:01.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:48:01.63#ibcon#[27=USB\r\n] 2006.175.07:48:01.63#ibcon#*before write, iclass 28, count 0 2006.175.07:48:01.63#ibcon#enter sib2, iclass 28, count 0 2006.175.07:48:01.63#ibcon#flushed, iclass 28, count 0 2006.175.07:48:01.63#ibcon#about to write, iclass 28, count 0 2006.175.07:48:01.63#ibcon#wrote, iclass 28, count 0 2006.175.07:48:01.63#ibcon#about to read 3, iclass 28, count 0 2006.175.07:48:01.66#ibcon#read 3, iclass 28, count 0 2006.175.07:48:01.66#ibcon#about to read 4, iclass 28, count 0 2006.175.07:48:01.66#ibcon#read 4, iclass 28, count 0 2006.175.07:48:01.66#ibcon#about to read 5, iclass 28, count 0 2006.175.07:48:01.66#ibcon#read 5, iclass 28, count 0 2006.175.07:48:01.66#ibcon#about to read 6, iclass 28, count 0 2006.175.07:48:01.66#ibcon#read 6, iclass 28, count 0 2006.175.07:48:01.66#ibcon#end of sib2, iclass 28, count 0 2006.175.07:48:01.66#ibcon#*after write, iclass 28, count 0 2006.175.07:48:01.66#ibcon#*before return 0, iclass 28, count 0 2006.175.07:48:01.66#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:48:01.66#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:48:01.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:48:01.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:48:01.66$vc4f8/vblo=4,712.99 2006.175.07:48:01.66#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.07:48:01.66#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.07:48:01.66#ibcon#ireg 17 cls_cnt 0 2006.175.07:48:01.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:48:01.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:48:01.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:48:01.66#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:48:01.66#ibcon#first serial, iclass 30, count 0 2006.175.07:48:01.66#ibcon#enter sib2, iclass 30, count 0 2006.175.07:48:01.66#ibcon#flushed, iclass 30, count 0 2006.175.07:48:01.66#ibcon#about to write, iclass 30, count 0 2006.175.07:48:01.66#ibcon#wrote, iclass 30, count 0 2006.175.07:48:01.66#ibcon#about to read 3, iclass 30, count 0 2006.175.07:48:01.68#ibcon#read 3, iclass 30, count 0 2006.175.07:48:01.68#ibcon#about to read 4, iclass 30, count 0 2006.175.07:48:01.68#ibcon#read 4, iclass 30, count 0 2006.175.07:48:01.68#ibcon#about to read 5, iclass 30, count 0 2006.175.07:48:01.68#ibcon#read 5, iclass 30, count 0 2006.175.07:48:01.68#ibcon#about to read 6, iclass 30, count 0 2006.175.07:48:01.68#ibcon#read 6, iclass 30, count 0 2006.175.07:48:01.68#ibcon#end of sib2, iclass 30, count 0 2006.175.07:48:01.68#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:48:01.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:48:01.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:48:01.68#ibcon#*before write, iclass 30, count 0 2006.175.07:48:01.68#ibcon#enter sib2, iclass 30, count 0 2006.175.07:48:01.68#ibcon#flushed, iclass 30, count 0 2006.175.07:48:01.68#ibcon#about to write, iclass 30, count 0 2006.175.07:48:01.68#ibcon#wrote, iclass 30, count 0 2006.175.07:48:01.68#ibcon#about to read 3, iclass 30, count 0 2006.175.07:48:01.72#ibcon#read 3, iclass 30, count 0 2006.175.07:48:01.72#ibcon#about to read 4, iclass 30, count 0 2006.175.07:48:01.72#ibcon#read 4, iclass 30, count 0 2006.175.07:48:01.72#ibcon#about to read 5, iclass 30, count 0 2006.175.07:48:01.72#ibcon#read 5, iclass 30, count 0 2006.175.07:48:01.72#ibcon#about to read 6, iclass 30, count 0 2006.175.07:48:01.72#ibcon#read 6, iclass 30, count 0 2006.175.07:48:01.72#ibcon#end of sib2, iclass 30, count 0 2006.175.07:48:01.72#ibcon#*after write, iclass 30, count 0 2006.175.07:48:01.72#ibcon#*before return 0, iclass 30, count 0 2006.175.07:48:01.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:48:01.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:48:01.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:48:01.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:48:01.72$vc4f8/vb=4,4 2006.175.07:48:01.72#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.07:48:01.72#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.07:48:01.72#ibcon#ireg 11 cls_cnt 2 2006.175.07:48:01.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:48:01.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:48:01.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:48:01.78#ibcon#enter wrdev, iclass 32, count 2 2006.175.07:48:01.78#ibcon#first serial, iclass 32, count 2 2006.175.07:48:01.78#ibcon#enter sib2, iclass 32, count 2 2006.175.07:48:01.78#ibcon#flushed, iclass 32, count 2 2006.175.07:48:01.78#ibcon#about to write, iclass 32, count 2 2006.175.07:48:01.78#ibcon#wrote, iclass 32, count 2 2006.175.07:48:01.78#ibcon#about to read 3, iclass 32, count 2 2006.175.07:48:01.80#ibcon#read 3, iclass 32, count 2 2006.175.07:48:01.80#ibcon#about to read 4, iclass 32, count 2 2006.175.07:48:01.80#ibcon#read 4, iclass 32, count 2 2006.175.07:48:01.80#ibcon#about to read 5, iclass 32, count 2 2006.175.07:48:01.80#ibcon#read 5, iclass 32, count 2 2006.175.07:48:01.80#ibcon#about to read 6, iclass 32, count 2 2006.175.07:48:01.80#ibcon#read 6, iclass 32, count 2 2006.175.07:48:01.80#ibcon#end of sib2, iclass 32, count 2 2006.175.07:48:01.80#ibcon#*mode == 0, iclass 32, count 2 2006.175.07:48:01.80#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.07:48:01.80#ibcon#[27=AT04-04\r\n] 2006.175.07:48:01.80#ibcon#*before write, iclass 32, count 2 2006.175.07:48:01.80#ibcon#enter sib2, iclass 32, count 2 2006.175.07:48:01.80#ibcon#flushed, iclass 32, count 2 2006.175.07:48:01.80#ibcon#about to write, iclass 32, count 2 2006.175.07:48:01.80#ibcon#wrote, iclass 32, count 2 2006.175.07:48:01.80#ibcon#about to read 3, iclass 32, count 2 2006.175.07:48:01.83#ibcon#read 3, iclass 32, count 2 2006.175.07:48:01.83#ibcon#about to read 4, iclass 32, count 2 2006.175.07:48:01.83#ibcon#read 4, iclass 32, count 2 2006.175.07:48:01.83#ibcon#about to read 5, iclass 32, count 2 2006.175.07:48:01.83#ibcon#read 5, iclass 32, count 2 2006.175.07:48:01.83#ibcon#about to read 6, iclass 32, count 2 2006.175.07:48:01.83#ibcon#read 6, iclass 32, count 2 2006.175.07:48:01.83#ibcon#end of sib2, iclass 32, count 2 2006.175.07:48:01.83#ibcon#*after write, iclass 32, count 2 2006.175.07:48:01.83#ibcon#*before return 0, iclass 32, count 2 2006.175.07:48:01.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:48:01.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:48:01.83#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.07:48:01.83#ibcon#ireg 7 cls_cnt 0 2006.175.07:48:01.83#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:48:01.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:48:01.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:48:01.95#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:48:01.95#ibcon#first serial, iclass 32, count 0 2006.175.07:48:01.95#ibcon#enter sib2, iclass 32, count 0 2006.175.07:48:01.95#ibcon#flushed, iclass 32, count 0 2006.175.07:48:01.95#ibcon#about to write, iclass 32, count 0 2006.175.07:48:01.95#ibcon#wrote, iclass 32, count 0 2006.175.07:48:01.95#ibcon#about to read 3, iclass 32, count 0 2006.175.07:48:01.97#ibcon#read 3, iclass 32, count 0 2006.175.07:48:01.97#ibcon#about to read 4, iclass 32, count 0 2006.175.07:48:01.97#ibcon#read 4, iclass 32, count 0 2006.175.07:48:01.97#ibcon#about to read 5, iclass 32, count 0 2006.175.07:48:01.97#ibcon#read 5, iclass 32, count 0 2006.175.07:48:01.97#ibcon#about to read 6, iclass 32, count 0 2006.175.07:48:01.97#ibcon#read 6, iclass 32, count 0 2006.175.07:48:01.97#ibcon#end of sib2, iclass 32, count 0 2006.175.07:48:01.97#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:48:01.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:48:01.97#ibcon#[27=USB\r\n] 2006.175.07:48:01.97#ibcon#*before write, iclass 32, count 0 2006.175.07:48:01.97#ibcon#enter sib2, iclass 32, count 0 2006.175.07:48:01.97#ibcon#flushed, iclass 32, count 0 2006.175.07:48:01.97#ibcon#about to write, iclass 32, count 0 2006.175.07:48:01.97#ibcon#wrote, iclass 32, count 0 2006.175.07:48:01.97#ibcon#about to read 3, iclass 32, count 0 2006.175.07:48:02.00#ibcon#read 3, iclass 32, count 0 2006.175.07:48:02.00#ibcon#about to read 4, iclass 32, count 0 2006.175.07:48:02.00#ibcon#read 4, iclass 32, count 0 2006.175.07:48:02.00#ibcon#about to read 5, iclass 32, count 0 2006.175.07:48:02.00#ibcon#read 5, iclass 32, count 0 2006.175.07:48:02.00#ibcon#about to read 6, iclass 32, count 0 2006.175.07:48:02.00#ibcon#read 6, iclass 32, count 0 2006.175.07:48:02.00#ibcon#end of sib2, iclass 32, count 0 2006.175.07:48:02.00#ibcon#*after write, iclass 32, count 0 2006.175.07:48:02.00#ibcon#*before return 0, iclass 32, count 0 2006.175.07:48:02.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:48:02.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:48:02.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:48:02.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:48:02.00$vc4f8/vblo=5,744.99 2006.175.07:48:02.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.07:48:02.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.07:48:02.00#ibcon#ireg 17 cls_cnt 0 2006.175.07:48:02.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:48:02.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:48:02.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:48:02.00#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:48:02.00#ibcon#first serial, iclass 34, count 0 2006.175.07:48:02.00#ibcon#enter sib2, iclass 34, count 0 2006.175.07:48:02.00#ibcon#flushed, iclass 34, count 0 2006.175.07:48:02.00#ibcon#about to write, iclass 34, count 0 2006.175.07:48:02.00#ibcon#wrote, iclass 34, count 0 2006.175.07:48:02.00#ibcon#about to read 3, iclass 34, count 0 2006.175.07:48:02.02#ibcon#read 3, iclass 34, count 0 2006.175.07:48:02.02#ibcon#about to read 4, iclass 34, count 0 2006.175.07:48:02.02#ibcon#read 4, iclass 34, count 0 2006.175.07:48:02.02#ibcon#about to read 5, iclass 34, count 0 2006.175.07:48:02.02#ibcon#read 5, iclass 34, count 0 2006.175.07:48:02.02#ibcon#about to read 6, iclass 34, count 0 2006.175.07:48:02.02#ibcon#read 6, iclass 34, count 0 2006.175.07:48:02.02#ibcon#end of sib2, iclass 34, count 0 2006.175.07:48:02.02#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:48:02.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:48:02.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:48:02.02#ibcon#*before write, iclass 34, count 0 2006.175.07:48:02.02#ibcon#enter sib2, iclass 34, count 0 2006.175.07:48:02.02#ibcon#flushed, iclass 34, count 0 2006.175.07:48:02.02#ibcon#about to write, iclass 34, count 0 2006.175.07:48:02.02#ibcon#wrote, iclass 34, count 0 2006.175.07:48:02.02#ibcon#about to read 3, iclass 34, count 0 2006.175.07:48:02.06#ibcon#read 3, iclass 34, count 0 2006.175.07:48:02.06#ibcon#about to read 4, iclass 34, count 0 2006.175.07:48:02.06#ibcon#read 4, iclass 34, count 0 2006.175.07:48:02.06#ibcon#about to read 5, iclass 34, count 0 2006.175.07:48:02.06#ibcon#read 5, iclass 34, count 0 2006.175.07:48:02.06#ibcon#about to read 6, iclass 34, count 0 2006.175.07:48:02.06#ibcon#read 6, iclass 34, count 0 2006.175.07:48:02.06#ibcon#end of sib2, iclass 34, count 0 2006.175.07:48:02.06#ibcon#*after write, iclass 34, count 0 2006.175.07:48:02.06#ibcon#*before return 0, iclass 34, count 0 2006.175.07:48:02.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:48:02.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:48:02.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:48:02.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:48:02.06$vc4f8/vb=5,4 2006.175.07:48:02.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.07:48:02.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.07:48:02.06#ibcon#ireg 11 cls_cnt 2 2006.175.07:48:02.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:48:02.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:48:02.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:48:02.12#ibcon#enter wrdev, iclass 36, count 2 2006.175.07:48:02.12#ibcon#first serial, iclass 36, count 2 2006.175.07:48:02.12#ibcon#enter sib2, iclass 36, count 2 2006.175.07:48:02.12#ibcon#flushed, iclass 36, count 2 2006.175.07:48:02.12#ibcon#about to write, iclass 36, count 2 2006.175.07:48:02.12#ibcon#wrote, iclass 36, count 2 2006.175.07:48:02.12#ibcon#about to read 3, iclass 36, count 2 2006.175.07:48:02.14#ibcon#read 3, iclass 36, count 2 2006.175.07:48:02.14#ibcon#about to read 4, iclass 36, count 2 2006.175.07:48:02.14#ibcon#read 4, iclass 36, count 2 2006.175.07:48:02.14#ibcon#about to read 5, iclass 36, count 2 2006.175.07:48:02.14#ibcon#read 5, iclass 36, count 2 2006.175.07:48:02.14#ibcon#about to read 6, iclass 36, count 2 2006.175.07:48:02.14#ibcon#read 6, iclass 36, count 2 2006.175.07:48:02.14#ibcon#end of sib2, iclass 36, count 2 2006.175.07:48:02.14#ibcon#*mode == 0, iclass 36, count 2 2006.175.07:48:02.14#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.07:48:02.14#ibcon#[27=AT05-04\r\n] 2006.175.07:48:02.14#ibcon#*before write, iclass 36, count 2 2006.175.07:48:02.14#ibcon#enter sib2, iclass 36, count 2 2006.175.07:48:02.14#ibcon#flushed, iclass 36, count 2 2006.175.07:48:02.14#ibcon#about to write, iclass 36, count 2 2006.175.07:48:02.14#ibcon#wrote, iclass 36, count 2 2006.175.07:48:02.14#ibcon#about to read 3, iclass 36, count 2 2006.175.07:48:02.17#ibcon#read 3, iclass 36, count 2 2006.175.07:48:02.17#ibcon#about to read 4, iclass 36, count 2 2006.175.07:48:02.17#ibcon#read 4, iclass 36, count 2 2006.175.07:48:02.17#ibcon#about to read 5, iclass 36, count 2 2006.175.07:48:02.17#ibcon#read 5, iclass 36, count 2 2006.175.07:48:02.17#ibcon#about to read 6, iclass 36, count 2 2006.175.07:48:02.17#ibcon#read 6, iclass 36, count 2 2006.175.07:48:02.17#ibcon#end of sib2, iclass 36, count 2 2006.175.07:48:02.17#ibcon#*after write, iclass 36, count 2 2006.175.07:48:02.17#ibcon#*before return 0, iclass 36, count 2 2006.175.07:48:02.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:48:02.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:48:02.17#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.07:48:02.17#ibcon#ireg 7 cls_cnt 0 2006.175.07:48:02.17#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:48:02.29#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:48:02.29#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:48:02.29#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:48:02.29#ibcon#first serial, iclass 36, count 0 2006.175.07:48:02.29#ibcon#enter sib2, iclass 36, count 0 2006.175.07:48:02.29#ibcon#flushed, iclass 36, count 0 2006.175.07:48:02.29#ibcon#about to write, iclass 36, count 0 2006.175.07:48:02.29#ibcon#wrote, iclass 36, count 0 2006.175.07:48:02.29#ibcon#about to read 3, iclass 36, count 0 2006.175.07:48:02.31#ibcon#read 3, iclass 36, count 0 2006.175.07:48:02.31#ibcon#about to read 4, iclass 36, count 0 2006.175.07:48:02.31#ibcon#read 4, iclass 36, count 0 2006.175.07:48:02.31#ibcon#about to read 5, iclass 36, count 0 2006.175.07:48:02.31#ibcon#read 5, iclass 36, count 0 2006.175.07:48:02.31#ibcon#about to read 6, iclass 36, count 0 2006.175.07:48:02.31#ibcon#read 6, iclass 36, count 0 2006.175.07:48:02.31#ibcon#end of sib2, iclass 36, count 0 2006.175.07:48:02.31#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:48:02.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:48:02.31#ibcon#[27=USB\r\n] 2006.175.07:48:02.31#ibcon#*before write, iclass 36, count 0 2006.175.07:48:02.31#ibcon#enter sib2, iclass 36, count 0 2006.175.07:48:02.31#ibcon#flushed, iclass 36, count 0 2006.175.07:48:02.31#ibcon#about to write, iclass 36, count 0 2006.175.07:48:02.31#ibcon#wrote, iclass 36, count 0 2006.175.07:48:02.31#ibcon#about to read 3, iclass 36, count 0 2006.175.07:48:02.34#ibcon#read 3, iclass 36, count 0 2006.175.07:48:02.34#ibcon#about to read 4, iclass 36, count 0 2006.175.07:48:02.34#ibcon#read 4, iclass 36, count 0 2006.175.07:48:02.34#ibcon#about to read 5, iclass 36, count 0 2006.175.07:48:02.34#ibcon#read 5, iclass 36, count 0 2006.175.07:48:02.34#ibcon#about to read 6, iclass 36, count 0 2006.175.07:48:02.34#ibcon#read 6, iclass 36, count 0 2006.175.07:48:02.34#ibcon#end of sib2, iclass 36, count 0 2006.175.07:48:02.34#ibcon#*after write, iclass 36, count 0 2006.175.07:48:02.34#ibcon#*before return 0, iclass 36, count 0 2006.175.07:48:02.34#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:48:02.34#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:48:02.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:48:02.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:48:02.34$vc4f8/vblo=6,752.99 2006.175.07:48:02.34#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:48:02.34#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:48:02.34#ibcon#ireg 17 cls_cnt 0 2006.175.07:48:02.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:48:02.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:48:02.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:48:02.34#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:48:02.34#ibcon#first serial, iclass 38, count 0 2006.175.07:48:02.34#ibcon#enter sib2, iclass 38, count 0 2006.175.07:48:02.34#ibcon#flushed, iclass 38, count 0 2006.175.07:48:02.34#ibcon#about to write, iclass 38, count 0 2006.175.07:48:02.34#ibcon#wrote, iclass 38, count 0 2006.175.07:48:02.34#ibcon#about to read 3, iclass 38, count 0 2006.175.07:48:02.36#ibcon#read 3, iclass 38, count 0 2006.175.07:48:02.36#ibcon#about to read 4, iclass 38, count 0 2006.175.07:48:02.36#ibcon#read 4, iclass 38, count 0 2006.175.07:48:02.36#ibcon#about to read 5, iclass 38, count 0 2006.175.07:48:02.36#ibcon#read 5, iclass 38, count 0 2006.175.07:48:02.36#ibcon#about to read 6, iclass 38, count 0 2006.175.07:48:02.36#ibcon#read 6, iclass 38, count 0 2006.175.07:48:02.36#ibcon#end of sib2, iclass 38, count 0 2006.175.07:48:02.36#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:48:02.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:48:02.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:48:02.36#ibcon#*before write, iclass 38, count 0 2006.175.07:48:02.36#ibcon#enter sib2, iclass 38, count 0 2006.175.07:48:02.36#ibcon#flushed, iclass 38, count 0 2006.175.07:48:02.36#ibcon#about to write, iclass 38, count 0 2006.175.07:48:02.36#ibcon#wrote, iclass 38, count 0 2006.175.07:48:02.36#ibcon#about to read 3, iclass 38, count 0 2006.175.07:48:02.40#ibcon#read 3, iclass 38, count 0 2006.175.07:48:02.40#ibcon#about to read 4, iclass 38, count 0 2006.175.07:48:02.40#ibcon#read 4, iclass 38, count 0 2006.175.07:48:02.40#ibcon#about to read 5, iclass 38, count 0 2006.175.07:48:02.40#ibcon#read 5, iclass 38, count 0 2006.175.07:48:02.40#ibcon#about to read 6, iclass 38, count 0 2006.175.07:48:02.40#ibcon#read 6, iclass 38, count 0 2006.175.07:48:02.40#ibcon#end of sib2, iclass 38, count 0 2006.175.07:48:02.40#ibcon#*after write, iclass 38, count 0 2006.175.07:48:02.40#ibcon#*before return 0, iclass 38, count 0 2006.175.07:48:02.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:48:02.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:48:02.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:48:02.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:48:02.40$vc4f8/vb=6,4 2006.175.07:48:02.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.07:48:02.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.07:48:02.40#ibcon#ireg 11 cls_cnt 2 2006.175.07:48:02.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:48:02.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:48:02.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:48:02.46#ibcon#enter wrdev, iclass 40, count 2 2006.175.07:48:02.46#ibcon#first serial, iclass 40, count 2 2006.175.07:48:02.46#ibcon#enter sib2, iclass 40, count 2 2006.175.07:48:02.46#ibcon#flushed, iclass 40, count 2 2006.175.07:48:02.46#ibcon#about to write, iclass 40, count 2 2006.175.07:48:02.46#ibcon#wrote, iclass 40, count 2 2006.175.07:48:02.46#ibcon#about to read 3, iclass 40, count 2 2006.175.07:48:02.48#ibcon#read 3, iclass 40, count 2 2006.175.07:48:02.48#ibcon#about to read 4, iclass 40, count 2 2006.175.07:48:02.48#ibcon#read 4, iclass 40, count 2 2006.175.07:48:02.48#ibcon#about to read 5, iclass 40, count 2 2006.175.07:48:02.48#ibcon#read 5, iclass 40, count 2 2006.175.07:48:02.48#ibcon#about to read 6, iclass 40, count 2 2006.175.07:48:02.48#ibcon#read 6, iclass 40, count 2 2006.175.07:48:02.48#ibcon#end of sib2, iclass 40, count 2 2006.175.07:48:02.48#ibcon#*mode == 0, iclass 40, count 2 2006.175.07:48:02.48#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.07:48:02.48#ibcon#[27=AT06-04\r\n] 2006.175.07:48:02.48#ibcon#*before write, iclass 40, count 2 2006.175.07:48:02.48#ibcon#enter sib2, iclass 40, count 2 2006.175.07:48:02.48#ibcon#flushed, iclass 40, count 2 2006.175.07:48:02.48#ibcon#about to write, iclass 40, count 2 2006.175.07:48:02.48#ibcon#wrote, iclass 40, count 2 2006.175.07:48:02.48#ibcon#about to read 3, iclass 40, count 2 2006.175.07:48:02.51#ibcon#read 3, iclass 40, count 2 2006.175.07:48:02.51#ibcon#about to read 4, iclass 40, count 2 2006.175.07:48:02.51#ibcon#read 4, iclass 40, count 2 2006.175.07:48:02.51#ibcon#about to read 5, iclass 40, count 2 2006.175.07:48:02.51#ibcon#read 5, iclass 40, count 2 2006.175.07:48:02.51#ibcon#about to read 6, iclass 40, count 2 2006.175.07:48:02.51#ibcon#read 6, iclass 40, count 2 2006.175.07:48:02.51#ibcon#end of sib2, iclass 40, count 2 2006.175.07:48:02.51#ibcon#*after write, iclass 40, count 2 2006.175.07:48:02.51#ibcon#*before return 0, iclass 40, count 2 2006.175.07:48:02.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:48:02.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:48:02.51#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.07:48:02.51#ibcon#ireg 7 cls_cnt 0 2006.175.07:48:02.51#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:48:02.63#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:48:02.63#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:48:02.63#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:48:02.63#ibcon#first serial, iclass 40, count 0 2006.175.07:48:02.63#ibcon#enter sib2, iclass 40, count 0 2006.175.07:48:02.63#ibcon#flushed, iclass 40, count 0 2006.175.07:48:02.63#ibcon#about to write, iclass 40, count 0 2006.175.07:48:02.63#ibcon#wrote, iclass 40, count 0 2006.175.07:48:02.63#ibcon#about to read 3, iclass 40, count 0 2006.175.07:48:02.65#ibcon#read 3, iclass 40, count 0 2006.175.07:48:02.65#ibcon#about to read 4, iclass 40, count 0 2006.175.07:48:02.65#ibcon#read 4, iclass 40, count 0 2006.175.07:48:02.65#ibcon#about to read 5, iclass 40, count 0 2006.175.07:48:02.65#ibcon#read 5, iclass 40, count 0 2006.175.07:48:02.65#ibcon#about to read 6, iclass 40, count 0 2006.175.07:48:02.65#ibcon#read 6, iclass 40, count 0 2006.175.07:48:02.65#ibcon#end of sib2, iclass 40, count 0 2006.175.07:48:02.65#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:48:02.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:48:02.65#ibcon#[27=USB\r\n] 2006.175.07:48:02.65#ibcon#*before write, iclass 40, count 0 2006.175.07:48:02.65#ibcon#enter sib2, iclass 40, count 0 2006.175.07:48:02.65#ibcon#flushed, iclass 40, count 0 2006.175.07:48:02.65#ibcon#about to write, iclass 40, count 0 2006.175.07:48:02.65#ibcon#wrote, iclass 40, count 0 2006.175.07:48:02.65#ibcon#about to read 3, iclass 40, count 0 2006.175.07:48:02.68#ibcon#read 3, iclass 40, count 0 2006.175.07:48:02.68#ibcon#about to read 4, iclass 40, count 0 2006.175.07:48:02.68#ibcon#read 4, iclass 40, count 0 2006.175.07:48:02.68#ibcon#about to read 5, iclass 40, count 0 2006.175.07:48:02.68#ibcon#read 5, iclass 40, count 0 2006.175.07:48:02.68#ibcon#about to read 6, iclass 40, count 0 2006.175.07:48:02.68#ibcon#read 6, iclass 40, count 0 2006.175.07:48:02.68#ibcon#end of sib2, iclass 40, count 0 2006.175.07:48:02.68#ibcon#*after write, iclass 40, count 0 2006.175.07:48:02.68#ibcon#*before return 0, iclass 40, count 0 2006.175.07:48:02.68#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:48:02.68#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:48:02.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:48:02.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:48:02.68$vc4f8/vabw=wide 2006.175.07:48:02.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:48:02.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:48:02.68#ibcon#ireg 8 cls_cnt 0 2006.175.07:48:02.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:48:02.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:48:02.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:48:02.68#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:48:02.68#ibcon#first serial, iclass 4, count 0 2006.175.07:48:02.68#ibcon#enter sib2, iclass 4, count 0 2006.175.07:48:02.68#ibcon#flushed, iclass 4, count 0 2006.175.07:48:02.68#ibcon#about to write, iclass 4, count 0 2006.175.07:48:02.68#ibcon#wrote, iclass 4, count 0 2006.175.07:48:02.68#ibcon#about to read 3, iclass 4, count 0 2006.175.07:48:02.70#ibcon#read 3, iclass 4, count 0 2006.175.07:48:02.70#ibcon#about to read 4, iclass 4, count 0 2006.175.07:48:02.70#ibcon#read 4, iclass 4, count 0 2006.175.07:48:02.70#ibcon#about to read 5, iclass 4, count 0 2006.175.07:48:02.70#ibcon#read 5, iclass 4, count 0 2006.175.07:48:02.70#ibcon#about to read 6, iclass 4, count 0 2006.175.07:48:02.70#ibcon#read 6, iclass 4, count 0 2006.175.07:48:02.70#ibcon#end of sib2, iclass 4, count 0 2006.175.07:48:02.70#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:48:02.70#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:48:02.70#ibcon#[25=BW32\r\n] 2006.175.07:48:02.70#ibcon#*before write, iclass 4, count 0 2006.175.07:48:02.70#ibcon#enter sib2, iclass 4, count 0 2006.175.07:48:02.70#ibcon#flushed, iclass 4, count 0 2006.175.07:48:02.70#ibcon#about to write, iclass 4, count 0 2006.175.07:48:02.70#ibcon#wrote, iclass 4, count 0 2006.175.07:48:02.70#ibcon#about to read 3, iclass 4, count 0 2006.175.07:48:02.73#ibcon#read 3, iclass 4, count 0 2006.175.07:48:02.73#ibcon#about to read 4, iclass 4, count 0 2006.175.07:48:02.73#ibcon#read 4, iclass 4, count 0 2006.175.07:48:02.73#ibcon#about to read 5, iclass 4, count 0 2006.175.07:48:02.73#ibcon#read 5, iclass 4, count 0 2006.175.07:48:02.73#ibcon#about to read 6, iclass 4, count 0 2006.175.07:48:02.73#ibcon#read 6, iclass 4, count 0 2006.175.07:48:02.73#ibcon#end of sib2, iclass 4, count 0 2006.175.07:48:02.73#ibcon#*after write, iclass 4, count 0 2006.175.07:48:02.73#ibcon#*before return 0, iclass 4, count 0 2006.175.07:48:02.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:48:02.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:48:02.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:48:02.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:48:02.73$vc4f8/vbbw=wide 2006.175.07:48:02.73#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.175.07:48:02.73#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.175.07:48:02.73#ibcon#ireg 8 cls_cnt 0 2006.175.07:48:02.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:48:02.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:48:02.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:48:02.80#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:48:02.80#ibcon#first serial, iclass 6, count 0 2006.175.07:48:02.80#ibcon#enter sib2, iclass 6, count 0 2006.175.07:48:02.80#ibcon#flushed, iclass 6, count 0 2006.175.07:48:02.80#ibcon#about to write, iclass 6, count 0 2006.175.07:48:02.80#ibcon#wrote, iclass 6, count 0 2006.175.07:48:02.80#ibcon#about to read 3, iclass 6, count 0 2006.175.07:48:02.82#ibcon#read 3, iclass 6, count 0 2006.175.07:48:02.82#ibcon#about to read 4, iclass 6, count 0 2006.175.07:48:02.82#ibcon#read 4, iclass 6, count 0 2006.175.07:48:02.82#ibcon#about to read 5, iclass 6, count 0 2006.175.07:48:02.82#ibcon#read 5, iclass 6, count 0 2006.175.07:48:02.82#ibcon#about to read 6, iclass 6, count 0 2006.175.07:48:02.82#ibcon#read 6, iclass 6, count 0 2006.175.07:48:02.82#ibcon#end of sib2, iclass 6, count 0 2006.175.07:48:02.82#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:48:02.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:48:02.82#ibcon#[27=BW32\r\n] 2006.175.07:48:02.82#ibcon#*before write, iclass 6, count 0 2006.175.07:48:02.82#ibcon#enter sib2, iclass 6, count 0 2006.175.07:48:02.82#ibcon#flushed, iclass 6, count 0 2006.175.07:48:02.82#ibcon#about to write, iclass 6, count 0 2006.175.07:48:02.82#ibcon#wrote, iclass 6, count 0 2006.175.07:48:02.82#ibcon#about to read 3, iclass 6, count 0 2006.175.07:48:02.85#ibcon#read 3, iclass 6, count 0 2006.175.07:48:02.85#ibcon#about to read 4, iclass 6, count 0 2006.175.07:48:02.85#ibcon#read 4, iclass 6, count 0 2006.175.07:48:02.85#ibcon#about to read 5, iclass 6, count 0 2006.175.07:48:02.85#ibcon#read 5, iclass 6, count 0 2006.175.07:48:02.85#ibcon#about to read 6, iclass 6, count 0 2006.175.07:48:02.85#ibcon#read 6, iclass 6, count 0 2006.175.07:48:02.85#ibcon#end of sib2, iclass 6, count 0 2006.175.07:48:02.85#ibcon#*after write, iclass 6, count 0 2006.175.07:48:02.85#ibcon#*before return 0, iclass 6, count 0 2006.175.07:48:02.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:48:02.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.175.07:48:02.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:48:02.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:48:02.85$4f8m12a/ifd4f 2006.175.07:48:02.85$ifd4f/lo= 2006.175.07:48:02.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:48:02.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:48:02.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:48:02.85$ifd4f/patch= 2006.175.07:48:02.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:48:02.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:48:02.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:48:02.85$4f8m12a/"form=m,16.000,1:2 2006.175.07:48:02.85$4f8m12a/"tpicd 2006.175.07:48:02.85$4f8m12a/echo=off 2006.175.07:48:02.85$4f8m12a/xlog=off 2006.175.07:48:02.85:!2006.175.07:48:30 2006.175.07:48:17.14#trakl#Source acquired 2006.175.07:48:18.14#flagr#flagr/antenna,acquired 2006.175.07:48:30.00:preob 2006.175.07:48:31.14/onsource/TRACKING 2006.175.07:48:31.14:!2006.175.07:48:40 2006.175.07:48:40.00:data_valid=on 2006.175.07:48:40.00:midob 2006.175.07:48:40.14/onsource/TRACKING 2006.175.07:48:40.14/wx/25.91,1007.4,69 2006.175.07:48:40.24/cable/+6.4765E-03 2006.175.07:48:41.33/va/01,08,usb,yes,28,30 2006.175.07:48:41.33/va/02,07,usb,yes,28,29 2006.175.07:48:41.33/va/03,06,usb,yes,30,30 2006.175.07:48:41.33/va/04,07,usb,yes,29,31 2006.175.07:48:41.33/va/05,07,usb,yes,29,31 2006.175.07:48:41.33/va/06,06,usb,yes,28,28 2006.175.07:48:41.33/va/07,06,usb,yes,29,29 2006.175.07:48:41.33/va/08,06,usb,yes,31,30 2006.175.07:48:41.56/valo/01,532.99,yes,locked 2006.175.07:48:41.56/valo/02,572.99,yes,locked 2006.175.07:48:41.56/valo/03,672.99,yes,locked 2006.175.07:48:41.56/valo/04,832.99,yes,locked 2006.175.07:48:41.56/valo/05,652.99,yes,locked 2006.175.07:48:41.56/valo/06,772.99,yes,locked 2006.175.07:48:41.56/valo/07,832.99,yes,locked 2006.175.07:48:41.56/valo/08,852.99,yes,locked 2006.175.07:48:42.65/vb/01,04,usb,yes,28,27 2006.175.07:48:42.65/vb/02,04,usb,yes,30,32 2006.175.07:48:42.65/vb/03,04,usb,yes,27,30 2006.175.07:48:42.65/vb/04,04,usb,yes,27,28 2006.175.07:48:42.65/vb/05,04,usb,yes,26,30 2006.175.07:48:42.65/vb/06,04,usb,yes,27,30 2006.175.07:48:42.65/vb/07,04,usb,yes,29,29 2006.175.07:48:42.65/vb/08,04,usb,yes,27,30 2006.175.07:48:42.88/vblo/01,632.99,yes,locked 2006.175.07:48:42.88/vblo/02,640.99,yes,locked 2006.175.07:48:42.88/vblo/03,656.99,yes,locked 2006.175.07:48:42.88/vblo/04,712.99,yes,locked 2006.175.07:48:42.88/vblo/05,744.99,yes,locked 2006.175.07:48:42.88/vblo/06,752.99,yes,locked 2006.175.07:48:42.88/vblo/07,734.99,yes,locked 2006.175.07:48:42.88/vblo/08,744.99,yes,locked 2006.175.07:48:43.03/vabw/8 2006.175.07:48:43.18/vbbw/8 2006.175.07:48:43.27/xfe/off,on,15.0 2006.175.07:48:43.66/ifatt/23,28,28,28 2006.175.07:48:44.08/fmout-gps/S +3.76E-07 2006.175.07:48:44.16:!2006.175.07:49:40 2006.175.07:49:40.00:data_valid=off 2006.175.07:49:40.00:postob 2006.175.07:49:40.09/cable/+6.4753E-03 2006.175.07:49:40.09/wx/25.90,1007.3,69 2006.175.07:49:41.08/fmout-gps/S +3.76E-07 2006.175.07:49:41.08:scan_name=175-0750,k06175,60 2006.175.07:49:41.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.175.07:49:41.14#flagr#flagr/antenna,new-source 2006.175.07:49:42.14:checkk5 2006.175.07:49:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:49:42.95/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:49:43.34/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:49:43.72/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:49:44.09/chk_obsdata//k5ts1/T1750748??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:49:44.46/chk_obsdata//k5ts2/T1750748??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:49:44.83/chk_obsdata//k5ts3/T1750748??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:49:45.20/chk_obsdata//k5ts4/T1750748??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:49:45.89/k5log//k5ts1_log_newline 2006.175.07:49:46.59/k5log//k5ts2_log_newline 2006.175.07:49:47.29/k5log//k5ts3_log_newline 2006.175.07:49:47.98/k5log//k5ts4_log_newline 2006.175.07:49:48.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:49:48.01:4f8m12a=1 2006.175.07:49:48.01$4f8m12a/echo=on 2006.175.07:49:48.01$4f8m12a/pcalon 2006.175.07:49:48.01$pcalon/"no phase cal control is implemented here 2006.175.07:49:48.01$4f8m12a/"tpicd=stop 2006.175.07:49:48.01$4f8m12a/vc4f8 2006.175.07:49:48.01$vc4f8/valo=1,532.99 2006.175.07:49:48.01#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.07:49:48.01#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.07:49:48.01#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:48.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:48.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:48.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:48.01#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:49:48.01#ibcon#first serial, iclass 15, count 0 2006.175.07:49:48.01#ibcon#enter sib2, iclass 15, count 0 2006.175.07:49:48.01#ibcon#flushed, iclass 15, count 0 2006.175.07:49:48.01#ibcon#about to write, iclass 15, count 0 2006.175.07:49:48.01#ibcon#wrote, iclass 15, count 0 2006.175.07:49:48.01#ibcon#about to read 3, iclass 15, count 0 2006.175.07:49:48.05#ibcon#read 3, iclass 15, count 0 2006.175.07:49:48.05#ibcon#about to read 4, iclass 15, count 0 2006.175.07:49:48.05#ibcon#read 4, iclass 15, count 0 2006.175.07:49:48.05#ibcon#about to read 5, iclass 15, count 0 2006.175.07:49:48.05#ibcon#read 5, iclass 15, count 0 2006.175.07:49:48.05#ibcon#about to read 6, iclass 15, count 0 2006.175.07:49:48.05#ibcon#read 6, iclass 15, count 0 2006.175.07:49:48.05#ibcon#end of sib2, iclass 15, count 0 2006.175.07:49:48.05#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:49:48.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:49:48.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:49:48.05#ibcon#*before write, iclass 15, count 0 2006.175.07:49:48.05#ibcon#enter sib2, iclass 15, count 0 2006.175.07:49:48.05#ibcon#flushed, iclass 15, count 0 2006.175.07:49:48.05#ibcon#about to write, iclass 15, count 0 2006.175.07:49:48.05#ibcon#wrote, iclass 15, count 0 2006.175.07:49:48.05#ibcon#about to read 3, iclass 15, count 0 2006.175.07:49:48.10#ibcon#read 3, iclass 15, count 0 2006.175.07:49:48.10#ibcon#about to read 4, iclass 15, count 0 2006.175.07:49:48.10#ibcon#read 4, iclass 15, count 0 2006.175.07:49:48.10#ibcon#about to read 5, iclass 15, count 0 2006.175.07:49:48.10#ibcon#read 5, iclass 15, count 0 2006.175.07:49:48.10#ibcon#about to read 6, iclass 15, count 0 2006.175.07:49:48.10#ibcon#read 6, iclass 15, count 0 2006.175.07:49:48.10#ibcon#end of sib2, iclass 15, count 0 2006.175.07:49:48.10#ibcon#*after write, iclass 15, count 0 2006.175.07:49:48.10#ibcon#*before return 0, iclass 15, count 0 2006.175.07:49:48.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:48.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:48.10#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:49:48.10#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:49:48.10$vc4f8/va=1,8 2006.175.07:49:48.10#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.07:49:48.10#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.07:49:48.10#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:48.10#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:48.10#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:48.10#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:48.10#ibcon#enter wrdev, iclass 17, count 2 2006.175.07:49:48.10#ibcon#first serial, iclass 17, count 2 2006.175.07:49:48.10#ibcon#enter sib2, iclass 17, count 2 2006.175.07:49:48.10#ibcon#flushed, iclass 17, count 2 2006.175.07:49:48.10#ibcon#about to write, iclass 17, count 2 2006.175.07:49:48.10#ibcon#wrote, iclass 17, count 2 2006.175.07:49:48.10#ibcon#about to read 3, iclass 17, count 2 2006.175.07:49:48.12#ibcon#read 3, iclass 17, count 2 2006.175.07:49:48.12#ibcon#about to read 4, iclass 17, count 2 2006.175.07:49:48.12#ibcon#read 4, iclass 17, count 2 2006.175.07:49:48.12#ibcon#about to read 5, iclass 17, count 2 2006.175.07:49:48.12#ibcon#read 5, iclass 17, count 2 2006.175.07:49:48.12#ibcon#about to read 6, iclass 17, count 2 2006.175.07:49:48.12#ibcon#read 6, iclass 17, count 2 2006.175.07:49:48.12#ibcon#end of sib2, iclass 17, count 2 2006.175.07:49:48.12#ibcon#*mode == 0, iclass 17, count 2 2006.175.07:49:48.12#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.07:49:48.12#ibcon#[25=AT01-08\r\n] 2006.175.07:49:48.12#ibcon#*before write, iclass 17, count 2 2006.175.07:49:48.12#ibcon#enter sib2, iclass 17, count 2 2006.175.07:49:48.12#ibcon#flushed, iclass 17, count 2 2006.175.07:49:48.12#ibcon#about to write, iclass 17, count 2 2006.175.07:49:48.12#ibcon#wrote, iclass 17, count 2 2006.175.07:49:48.12#ibcon#about to read 3, iclass 17, count 2 2006.175.07:49:48.16#ibcon#read 3, iclass 17, count 2 2006.175.07:49:48.16#ibcon#about to read 4, iclass 17, count 2 2006.175.07:49:48.16#ibcon#read 4, iclass 17, count 2 2006.175.07:49:48.16#ibcon#about to read 5, iclass 17, count 2 2006.175.07:49:48.16#ibcon#read 5, iclass 17, count 2 2006.175.07:49:48.16#ibcon#about to read 6, iclass 17, count 2 2006.175.07:49:48.16#ibcon#read 6, iclass 17, count 2 2006.175.07:49:48.16#ibcon#end of sib2, iclass 17, count 2 2006.175.07:49:48.16#ibcon#*after write, iclass 17, count 2 2006.175.07:49:48.16#ibcon#*before return 0, iclass 17, count 2 2006.175.07:49:48.16#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:48.16#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:48.16#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.07:49:48.16#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:48.16#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:48.28#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:48.28#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:48.28#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:49:48.28#ibcon#first serial, iclass 17, count 0 2006.175.07:49:48.28#ibcon#enter sib2, iclass 17, count 0 2006.175.07:49:48.28#ibcon#flushed, iclass 17, count 0 2006.175.07:49:48.28#ibcon#about to write, iclass 17, count 0 2006.175.07:49:48.28#ibcon#wrote, iclass 17, count 0 2006.175.07:49:48.28#ibcon#about to read 3, iclass 17, count 0 2006.175.07:49:48.30#ibcon#read 3, iclass 17, count 0 2006.175.07:49:48.30#ibcon#about to read 4, iclass 17, count 0 2006.175.07:49:48.30#ibcon#read 4, iclass 17, count 0 2006.175.07:49:48.30#ibcon#about to read 5, iclass 17, count 0 2006.175.07:49:48.30#ibcon#read 5, iclass 17, count 0 2006.175.07:49:48.30#ibcon#about to read 6, iclass 17, count 0 2006.175.07:49:48.30#ibcon#read 6, iclass 17, count 0 2006.175.07:49:48.30#ibcon#end of sib2, iclass 17, count 0 2006.175.07:49:48.30#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:49:48.30#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:49:48.30#ibcon#[25=USB\r\n] 2006.175.07:49:48.30#ibcon#*before write, iclass 17, count 0 2006.175.07:49:48.30#ibcon#enter sib2, iclass 17, count 0 2006.175.07:49:48.30#ibcon#flushed, iclass 17, count 0 2006.175.07:49:48.30#ibcon#about to write, iclass 17, count 0 2006.175.07:49:48.30#ibcon#wrote, iclass 17, count 0 2006.175.07:49:48.30#ibcon#about to read 3, iclass 17, count 0 2006.175.07:49:48.33#ibcon#read 3, iclass 17, count 0 2006.175.07:49:48.33#ibcon#about to read 4, iclass 17, count 0 2006.175.07:49:48.33#ibcon#read 4, iclass 17, count 0 2006.175.07:49:48.33#ibcon#about to read 5, iclass 17, count 0 2006.175.07:49:48.33#ibcon#read 5, iclass 17, count 0 2006.175.07:49:48.33#ibcon#about to read 6, iclass 17, count 0 2006.175.07:49:48.33#ibcon#read 6, iclass 17, count 0 2006.175.07:49:48.33#ibcon#end of sib2, iclass 17, count 0 2006.175.07:49:48.33#ibcon#*after write, iclass 17, count 0 2006.175.07:49:48.33#ibcon#*before return 0, iclass 17, count 0 2006.175.07:49:48.33#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:48.33#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:48.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:49:48.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:49:48.33$vc4f8/valo=2,572.99 2006.175.07:49:48.33#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.07:49:48.33#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.07:49:48.33#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:48.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:48.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:48.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:48.33#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:49:48.33#ibcon#first serial, iclass 19, count 0 2006.175.07:49:48.33#ibcon#enter sib2, iclass 19, count 0 2006.175.07:49:48.33#ibcon#flushed, iclass 19, count 0 2006.175.07:49:48.33#ibcon#about to write, iclass 19, count 0 2006.175.07:49:48.33#ibcon#wrote, iclass 19, count 0 2006.175.07:49:48.33#ibcon#about to read 3, iclass 19, count 0 2006.175.07:49:48.35#ibcon#read 3, iclass 19, count 0 2006.175.07:49:48.35#ibcon#about to read 4, iclass 19, count 0 2006.175.07:49:48.35#ibcon#read 4, iclass 19, count 0 2006.175.07:49:48.35#ibcon#about to read 5, iclass 19, count 0 2006.175.07:49:48.35#ibcon#read 5, iclass 19, count 0 2006.175.07:49:48.35#ibcon#about to read 6, iclass 19, count 0 2006.175.07:49:48.35#ibcon#read 6, iclass 19, count 0 2006.175.07:49:48.35#ibcon#end of sib2, iclass 19, count 0 2006.175.07:49:48.35#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:49:48.35#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:49:48.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:49:48.35#ibcon#*before write, iclass 19, count 0 2006.175.07:49:48.35#ibcon#enter sib2, iclass 19, count 0 2006.175.07:49:48.35#ibcon#flushed, iclass 19, count 0 2006.175.07:49:48.35#ibcon#about to write, iclass 19, count 0 2006.175.07:49:48.35#ibcon#wrote, iclass 19, count 0 2006.175.07:49:48.35#ibcon#about to read 3, iclass 19, count 0 2006.175.07:49:48.39#ibcon#read 3, iclass 19, count 0 2006.175.07:49:48.39#ibcon#about to read 4, iclass 19, count 0 2006.175.07:49:48.39#ibcon#read 4, iclass 19, count 0 2006.175.07:49:48.39#ibcon#about to read 5, iclass 19, count 0 2006.175.07:49:48.39#ibcon#read 5, iclass 19, count 0 2006.175.07:49:48.39#ibcon#about to read 6, iclass 19, count 0 2006.175.07:49:48.39#ibcon#read 6, iclass 19, count 0 2006.175.07:49:48.39#ibcon#end of sib2, iclass 19, count 0 2006.175.07:49:48.39#ibcon#*after write, iclass 19, count 0 2006.175.07:49:48.39#ibcon#*before return 0, iclass 19, count 0 2006.175.07:49:48.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:48.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:48.39#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:49:48.39#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:49:48.39$vc4f8/va=2,7 2006.175.07:49:48.39#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.07:49:48.39#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.07:49:48.39#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:48.39#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:48.45#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:48.45#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:48.45#ibcon#enter wrdev, iclass 21, count 2 2006.175.07:49:48.45#ibcon#first serial, iclass 21, count 2 2006.175.07:49:48.45#ibcon#enter sib2, iclass 21, count 2 2006.175.07:49:48.45#ibcon#flushed, iclass 21, count 2 2006.175.07:49:48.45#ibcon#about to write, iclass 21, count 2 2006.175.07:49:48.45#ibcon#wrote, iclass 21, count 2 2006.175.07:49:48.45#ibcon#about to read 3, iclass 21, count 2 2006.175.07:49:48.47#ibcon#read 3, iclass 21, count 2 2006.175.07:49:48.47#ibcon#about to read 4, iclass 21, count 2 2006.175.07:49:48.47#ibcon#read 4, iclass 21, count 2 2006.175.07:49:48.47#ibcon#about to read 5, iclass 21, count 2 2006.175.07:49:48.47#ibcon#read 5, iclass 21, count 2 2006.175.07:49:48.47#ibcon#about to read 6, iclass 21, count 2 2006.175.07:49:48.47#ibcon#read 6, iclass 21, count 2 2006.175.07:49:48.47#ibcon#end of sib2, iclass 21, count 2 2006.175.07:49:48.47#ibcon#*mode == 0, iclass 21, count 2 2006.175.07:49:48.47#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.07:49:48.47#ibcon#[25=AT02-07\r\n] 2006.175.07:49:48.47#ibcon#*before write, iclass 21, count 2 2006.175.07:49:48.47#ibcon#enter sib2, iclass 21, count 2 2006.175.07:49:48.47#ibcon#flushed, iclass 21, count 2 2006.175.07:49:48.47#ibcon#about to write, iclass 21, count 2 2006.175.07:49:48.47#ibcon#wrote, iclass 21, count 2 2006.175.07:49:48.47#ibcon#about to read 3, iclass 21, count 2 2006.175.07:49:48.50#ibcon#read 3, iclass 21, count 2 2006.175.07:49:48.50#ibcon#about to read 4, iclass 21, count 2 2006.175.07:49:48.50#ibcon#read 4, iclass 21, count 2 2006.175.07:49:48.50#ibcon#about to read 5, iclass 21, count 2 2006.175.07:49:48.50#ibcon#read 5, iclass 21, count 2 2006.175.07:49:48.50#ibcon#about to read 6, iclass 21, count 2 2006.175.07:49:48.50#ibcon#read 6, iclass 21, count 2 2006.175.07:49:48.50#ibcon#end of sib2, iclass 21, count 2 2006.175.07:49:48.50#ibcon#*after write, iclass 21, count 2 2006.175.07:49:48.50#ibcon#*before return 0, iclass 21, count 2 2006.175.07:49:48.50#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:48.50#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:48.50#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.07:49:48.50#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:48.50#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:48.62#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:48.62#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:48.62#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:49:48.62#ibcon#first serial, iclass 21, count 0 2006.175.07:49:48.62#ibcon#enter sib2, iclass 21, count 0 2006.175.07:49:48.62#ibcon#flushed, iclass 21, count 0 2006.175.07:49:48.62#ibcon#about to write, iclass 21, count 0 2006.175.07:49:48.62#ibcon#wrote, iclass 21, count 0 2006.175.07:49:48.62#ibcon#about to read 3, iclass 21, count 0 2006.175.07:49:48.64#ibcon#read 3, iclass 21, count 0 2006.175.07:49:48.64#ibcon#about to read 4, iclass 21, count 0 2006.175.07:49:48.64#ibcon#read 4, iclass 21, count 0 2006.175.07:49:48.64#ibcon#about to read 5, iclass 21, count 0 2006.175.07:49:48.64#ibcon#read 5, iclass 21, count 0 2006.175.07:49:48.64#ibcon#about to read 6, iclass 21, count 0 2006.175.07:49:48.64#ibcon#read 6, iclass 21, count 0 2006.175.07:49:48.64#ibcon#end of sib2, iclass 21, count 0 2006.175.07:49:48.64#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:49:48.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:49:48.64#ibcon#[25=USB\r\n] 2006.175.07:49:48.64#ibcon#*before write, iclass 21, count 0 2006.175.07:49:48.64#ibcon#enter sib2, iclass 21, count 0 2006.175.07:49:48.64#ibcon#flushed, iclass 21, count 0 2006.175.07:49:48.64#ibcon#about to write, iclass 21, count 0 2006.175.07:49:48.64#ibcon#wrote, iclass 21, count 0 2006.175.07:49:48.64#ibcon#about to read 3, iclass 21, count 0 2006.175.07:49:48.67#ibcon#read 3, iclass 21, count 0 2006.175.07:49:48.67#ibcon#about to read 4, iclass 21, count 0 2006.175.07:49:48.67#ibcon#read 4, iclass 21, count 0 2006.175.07:49:48.67#ibcon#about to read 5, iclass 21, count 0 2006.175.07:49:48.67#ibcon#read 5, iclass 21, count 0 2006.175.07:49:48.67#ibcon#about to read 6, iclass 21, count 0 2006.175.07:49:48.67#ibcon#read 6, iclass 21, count 0 2006.175.07:49:48.67#ibcon#end of sib2, iclass 21, count 0 2006.175.07:49:48.67#ibcon#*after write, iclass 21, count 0 2006.175.07:49:48.67#ibcon#*before return 0, iclass 21, count 0 2006.175.07:49:48.67#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:48.67#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:48.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:49:48.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:49:48.67$vc4f8/valo=3,672.99 2006.175.07:49:48.67#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.07:49:48.67#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.07:49:48.67#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:48.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:48.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:48.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:48.67#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:49:48.67#ibcon#first serial, iclass 23, count 0 2006.175.07:49:48.67#ibcon#enter sib2, iclass 23, count 0 2006.175.07:49:48.67#ibcon#flushed, iclass 23, count 0 2006.175.07:49:48.67#ibcon#about to write, iclass 23, count 0 2006.175.07:49:48.67#ibcon#wrote, iclass 23, count 0 2006.175.07:49:48.67#ibcon#about to read 3, iclass 23, count 0 2006.175.07:49:48.69#ibcon#read 3, iclass 23, count 0 2006.175.07:49:48.69#ibcon#about to read 4, iclass 23, count 0 2006.175.07:49:48.69#ibcon#read 4, iclass 23, count 0 2006.175.07:49:48.69#ibcon#about to read 5, iclass 23, count 0 2006.175.07:49:48.69#ibcon#read 5, iclass 23, count 0 2006.175.07:49:48.69#ibcon#about to read 6, iclass 23, count 0 2006.175.07:49:48.69#ibcon#read 6, iclass 23, count 0 2006.175.07:49:48.69#ibcon#end of sib2, iclass 23, count 0 2006.175.07:49:48.69#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:49:48.69#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:49:48.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:49:48.69#ibcon#*before write, iclass 23, count 0 2006.175.07:49:48.69#ibcon#enter sib2, iclass 23, count 0 2006.175.07:49:48.69#ibcon#flushed, iclass 23, count 0 2006.175.07:49:48.69#ibcon#about to write, iclass 23, count 0 2006.175.07:49:48.69#ibcon#wrote, iclass 23, count 0 2006.175.07:49:48.69#ibcon#about to read 3, iclass 23, count 0 2006.175.07:49:48.73#ibcon#read 3, iclass 23, count 0 2006.175.07:49:48.73#ibcon#about to read 4, iclass 23, count 0 2006.175.07:49:48.73#ibcon#read 4, iclass 23, count 0 2006.175.07:49:48.73#ibcon#about to read 5, iclass 23, count 0 2006.175.07:49:48.73#ibcon#read 5, iclass 23, count 0 2006.175.07:49:48.73#ibcon#about to read 6, iclass 23, count 0 2006.175.07:49:48.73#ibcon#read 6, iclass 23, count 0 2006.175.07:49:48.73#ibcon#end of sib2, iclass 23, count 0 2006.175.07:49:48.73#ibcon#*after write, iclass 23, count 0 2006.175.07:49:48.73#ibcon#*before return 0, iclass 23, count 0 2006.175.07:49:48.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:48.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:48.73#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:49:48.73#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:49:48.73$vc4f8/va=3,6 2006.175.07:49:48.73#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.07:49:48.73#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.07:49:48.73#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:48.73#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:48.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:48.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:48.79#ibcon#enter wrdev, iclass 25, count 2 2006.175.07:49:48.79#ibcon#first serial, iclass 25, count 2 2006.175.07:49:48.79#ibcon#enter sib2, iclass 25, count 2 2006.175.07:49:48.79#ibcon#flushed, iclass 25, count 2 2006.175.07:49:48.79#ibcon#about to write, iclass 25, count 2 2006.175.07:49:48.79#ibcon#wrote, iclass 25, count 2 2006.175.07:49:48.79#ibcon#about to read 3, iclass 25, count 2 2006.175.07:49:48.81#ibcon#read 3, iclass 25, count 2 2006.175.07:49:48.81#ibcon#about to read 4, iclass 25, count 2 2006.175.07:49:48.81#ibcon#read 4, iclass 25, count 2 2006.175.07:49:48.81#ibcon#about to read 5, iclass 25, count 2 2006.175.07:49:48.81#ibcon#read 5, iclass 25, count 2 2006.175.07:49:48.81#ibcon#about to read 6, iclass 25, count 2 2006.175.07:49:48.81#ibcon#read 6, iclass 25, count 2 2006.175.07:49:48.81#ibcon#end of sib2, iclass 25, count 2 2006.175.07:49:48.81#ibcon#*mode == 0, iclass 25, count 2 2006.175.07:49:48.81#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.07:49:48.81#ibcon#[25=AT03-06\r\n] 2006.175.07:49:48.81#ibcon#*before write, iclass 25, count 2 2006.175.07:49:48.81#ibcon#enter sib2, iclass 25, count 2 2006.175.07:49:48.81#ibcon#flushed, iclass 25, count 2 2006.175.07:49:48.81#ibcon#about to write, iclass 25, count 2 2006.175.07:49:48.81#ibcon#wrote, iclass 25, count 2 2006.175.07:49:48.81#ibcon#about to read 3, iclass 25, count 2 2006.175.07:49:48.84#ibcon#read 3, iclass 25, count 2 2006.175.07:49:48.84#ibcon#about to read 4, iclass 25, count 2 2006.175.07:49:48.84#ibcon#read 4, iclass 25, count 2 2006.175.07:49:48.84#ibcon#about to read 5, iclass 25, count 2 2006.175.07:49:48.84#ibcon#read 5, iclass 25, count 2 2006.175.07:49:48.84#ibcon#about to read 6, iclass 25, count 2 2006.175.07:49:48.84#ibcon#read 6, iclass 25, count 2 2006.175.07:49:48.84#ibcon#end of sib2, iclass 25, count 2 2006.175.07:49:48.84#ibcon#*after write, iclass 25, count 2 2006.175.07:49:48.84#ibcon#*before return 0, iclass 25, count 2 2006.175.07:49:48.84#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:48.84#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:48.84#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.07:49:48.84#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:48.84#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:48.96#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:48.96#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:48.96#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:49:48.96#ibcon#first serial, iclass 25, count 0 2006.175.07:49:48.96#ibcon#enter sib2, iclass 25, count 0 2006.175.07:49:48.96#ibcon#flushed, iclass 25, count 0 2006.175.07:49:48.96#ibcon#about to write, iclass 25, count 0 2006.175.07:49:48.96#ibcon#wrote, iclass 25, count 0 2006.175.07:49:48.96#ibcon#about to read 3, iclass 25, count 0 2006.175.07:49:48.98#ibcon#read 3, iclass 25, count 0 2006.175.07:49:48.98#ibcon#about to read 4, iclass 25, count 0 2006.175.07:49:48.98#ibcon#read 4, iclass 25, count 0 2006.175.07:49:48.98#ibcon#about to read 5, iclass 25, count 0 2006.175.07:49:48.98#ibcon#read 5, iclass 25, count 0 2006.175.07:49:48.98#ibcon#about to read 6, iclass 25, count 0 2006.175.07:49:48.98#ibcon#read 6, iclass 25, count 0 2006.175.07:49:48.98#ibcon#end of sib2, iclass 25, count 0 2006.175.07:49:48.98#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:49:48.98#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:49:48.98#ibcon#[25=USB\r\n] 2006.175.07:49:48.98#ibcon#*before write, iclass 25, count 0 2006.175.07:49:48.98#ibcon#enter sib2, iclass 25, count 0 2006.175.07:49:48.98#ibcon#flushed, iclass 25, count 0 2006.175.07:49:48.98#ibcon#about to write, iclass 25, count 0 2006.175.07:49:48.98#ibcon#wrote, iclass 25, count 0 2006.175.07:49:48.98#ibcon#about to read 3, iclass 25, count 0 2006.175.07:49:49.01#ibcon#read 3, iclass 25, count 0 2006.175.07:49:49.01#ibcon#about to read 4, iclass 25, count 0 2006.175.07:49:49.01#ibcon#read 4, iclass 25, count 0 2006.175.07:49:49.01#ibcon#about to read 5, iclass 25, count 0 2006.175.07:49:49.01#ibcon#read 5, iclass 25, count 0 2006.175.07:49:49.01#ibcon#about to read 6, iclass 25, count 0 2006.175.07:49:49.01#ibcon#read 6, iclass 25, count 0 2006.175.07:49:49.01#ibcon#end of sib2, iclass 25, count 0 2006.175.07:49:49.01#ibcon#*after write, iclass 25, count 0 2006.175.07:49:49.01#ibcon#*before return 0, iclass 25, count 0 2006.175.07:49:49.01#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:49.01#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:49.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:49:49.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:49:49.01$vc4f8/valo=4,832.99 2006.175.07:49:49.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.07:49:49.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.07:49:49.01#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:49.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:49:49.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:49:49.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:49:49.01#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:49:49.01#ibcon#first serial, iclass 28, count 0 2006.175.07:49:49.01#ibcon#enter sib2, iclass 28, count 0 2006.175.07:49:49.01#ibcon#flushed, iclass 28, count 0 2006.175.07:49:49.01#ibcon#about to write, iclass 28, count 0 2006.175.07:49:49.01#ibcon#wrote, iclass 28, count 0 2006.175.07:49:49.01#ibcon#about to read 3, iclass 28, count 0 2006.175.07:49:49.03#ibcon#read 3, iclass 28, count 0 2006.175.07:49:49.03#ibcon#about to read 4, iclass 28, count 0 2006.175.07:49:49.03#ibcon#read 4, iclass 28, count 0 2006.175.07:49:49.03#ibcon#about to read 5, iclass 28, count 0 2006.175.07:49:49.03#ibcon#read 5, iclass 28, count 0 2006.175.07:49:49.03#ibcon#about to read 6, iclass 28, count 0 2006.175.07:49:49.03#ibcon#read 6, iclass 28, count 0 2006.175.07:49:49.03#ibcon#end of sib2, iclass 28, count 0 2006.175.07:49:49.03#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:49:49.03#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:49:49.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:49:49.03#ibcon#*before write, iclass 28, count 0 2006.175.07:49:49.03#ibcon#enter sib2, iclass 28, count 0 2006.175.07:49:49.03#ibcon#flushed, iclass 28, count 0 2006.175.07:49:49.03#ibcon#about to write, iclass 28, count 0 2006.175.07:49:49.03#ibcon#wrote, iclass 28, count 0 2006.175.07:49:49.03#ibcon#about to read 3, iclass 28, count 0 2006.175.07:49:49.04#abcon#<5=/05 4.2 7.3 25.89 691007.3\r\n> 2006.175.07:49:49.06#abcon#{5=INTERFACE CLEAR} 2006.175.07:49:49.07#ibcon#read 3, iclass 28, count 0 2006.175.07:49:49.07#ibcon#about to read 4, iclass 28, count 0 2006.175.07:49:49.07#ibcon#read 4, iclass 28, count 0 2006.175.07:49:49.07#ibcon#about to read 5, iclass 28, count 0 2006.175.07:49:49.07#ibcon#read 5, iclass 28, count 0 2006.175.07:49:49.07#ibcon#about to read 6, iclass 28, count 0 2006.175.07:49:49.07#ibcon#read 6, iclass 28, count 0 2006.175.07:49:49.07#ibcon#end of sib2, iclass 28, count 0 2006.175.07:49:49.07#ibcon#*after write, iclass 28, count 0 2006.175.07:49:49.07#ibcon#*before return 0, iclass 28, count 0 2006.175.07:49:49.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:49:49.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:49:49.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:49:49.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:49:49.07$vc4f8/va=4,7 2006.175.07:49:49.07#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.07:49:49.07#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.07:49:49.07#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:49.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:49:49.12#abcon#[5=S1D000X0/0*\r\n] 2006.175.07:49:49.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:49:49.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:49:49.13#ibcon#enter wrdev, iclass 32, count 2 2006.175.07:49:49.13#ibcon#first serial, iclass 32, count 2 2006.175.07:49:49.13#ibcon#enter sib2, iclass 32, count 2 2006.175.07:49:49.13#ibcon#flushed, iclass 32, count 2 2006.175.07:49:49.13#ibcon#about to write, iclass 32, count 2 2006.175.07:49:49.13#ibcon#wrote, iclass 32, count 2 2006.175.07:49:49.13#ibcon#about to read 3, iclass 32, count 2 2006.175.07:49:49.15#ibcon#read 3, iclass 32, count 2 2006.175.07:49:49.15#ibcon#about to read 4, iclass 32, count 2 2006.175.07:49:49.15#ibcon#read 4, iclass 32, count 2 2006.175.07:49:49.15#ibcon#about to read 5, iclass 32, count 2 2006.175.07:49:49.15#ibcon#read 5, iclass 32, count 2 2006.175.07:49:49.15#ibcon#about to read 6, iclass 32, count 2 2006.175.07:49:49.15#ibcon#read 6, iclass 32, count 2 2006.175.07:49:49.15#ibcon#end of sib2, iclass 32, count 2 2006.175.07:49:49.15#ibcon#*mode == 0, iclass 32, count 2 2006.175.07:49:49.15#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.07:49:49.15#ibcon#[25=AT04-07\r\n] 2006.175.07:49:49.15#ibcon#*before write, iclass 32, count 2 2006.175.07:49:49.15#ibcon#enter sib2, iclass 32, count 2 2006.175.07:49:49.15#ibcon#flushed, iclass 32, count 2 2006.175.07:49:49.15#ibcon#about to write, iclass 32, count 2 2006.175.07:49:49.15#ibcon#wrote, iclass 32, count 2 2006.175.07:49:49.15#ibcon#about to read 3, iclass 32, count 2 2006.175.07:49:49.18#ibcon#read 3, iclass 32, count 2 2006.175.07:49:49.18#ibcon#about to read 4, iclass 32, count 2 2006.175.07:49:49.18#ibcon#read 4, iclass 32, count 2 2006.175.07:49:49.18#ibcon#about to read 5, iclass 32, count 2 2006.175.07:49:49.18#ibcon#read 5, iclass 32, count 2 2006.175.07:49:49.18#ibcon#about to read 6, iclass 32, count 2 2006.175.07:49:49.18#ibcon#read 6, iclass 32, count 2 2006.175.07:49:49.18#ibcon#end of sib2, iclass 32, count 2 2006.175.07:49:49.18#ibcon#*after write, iclass 32, count 2 2006.175.07:49:49.18#ibcon#*before return 0, iclass 32, count 2 2006.175.07:49:49.18#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:49:49.18#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:49:49.18#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.07:49:49.18#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:49.18#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:49:49.30#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:49:49.30#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:49:49.30#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:49:49.30#ibcon#first serial, iclass 32, count 0 2006.175.07:49:49.30#ibcon#enter sib2, iclass 32, count 0 2006.175.07:49:49.30#ibcon#flushed, iclass 32, count 0 2006.175.07:49:49.30#ibcon#about to write, iclass 32, count 0 2006.175.07:49:49.30#ibcon#wrote, iclass 32, count 0 2006.175.07:49:49.30#ibcon#about to read 3, iclass 32, count 0 2006.175.07:49:49.32#ibcon#read 3, iclass 32, count 0 2006.175.07:49:49.32#ibcon#about to read 4, iclass 32, count 0 2006.175.07:49:49.32#ibcon#read 4, iclass 32, count 0 2006.175.07:49:49.32#ibcon#about to read 5, iclass 32, count 0 2006.175.07:49:49.32#ibcon#read 5, iclass 32, count 0 2006.175.07:49:49.32#ibcon#about to read 6, iclass 32, count 0 2006.175.07:49:49.32#ibcon#read 6, iclass 32, count 0 2006.175.07:49:49.32#ibcon#end of sib2, iclass 32, count 0 2006.175.07:49:49.32#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:49:49.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:49:49.32#ibcon#[25=USB\r\n] 2006.175.07:49:49.32#ibcon#*before write, iclass 32, count 0 2006.175.07:49:49.32#ibcon#enter sib2, iclass 32, count 0 2006.175.07:49:49.32#ibcon#flushed, iclass 32, count 0 2006.175.07:49:49.32#ibcon#about to write, iclass 32, count 0 2006.175.07:49:49.32#ibcon#wrote, iclass 32, count 0 2006.175.07:49:49.32#ibcon#about to read 3, iclass 32, count 0 2006.175.07:49:49.35#ibcon#read 3, iclass 32, count 0 2006.175.07:49:49.35#ibcon#about to read 4, iclass 32, count 0 2006.175.07:49:49.35#ibcon#read 4, iclass 32, count 0 2006.175.07:49:49.35#ibcon#about to read 5, iclass 32, count 0 2006.175.07:49:49.35#ibcon#read 5, iclass 32, count 0 2006.175.07:49:49.35#ibcon#about to read 6, iclass 32, count 0 2006.175.07:49:49.35#ibcon#read 6, iclass 32, count 0 2006.175.07:49:49.35#ibcon#end of sib2, iclass 32, count 0 2006.175.07:49:49.35#ibcon#*after write, iclass 32, count 0 2006.175.07:49:49.35#ibcon#*before return 0, iclass 32, count 0 2006.175.07:49:49.35#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:49:49.35#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:49:49.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:49:49.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:49:49.35$vc4f8/valo=5,652.99 2006.175.07:49:49.35#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.07:49:49.35#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.07:49:49.35#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:49.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:49.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:49.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:49.35#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:49:49.35#ibcon#first serial, iclass 35, count 0 2006.175.07:49:49.35#ibcon#enter sib2, iclass 35, count 0 2006.175.07:49:49.35#ibcon#flushed, iclass 35, count 0 2006.175.07:49:49.35#ibcon#about to write, iclass 35, count 0 2006.175.07:49:49.35#ibcon#wrote, iclass 35, count 0 2006.175.07:49:49.35#ibcon#about to read 3, iclass 35, count 0 2006.175.07:49:49.37#ibcon#read 3, iclass 35, count 0 2006.175.07:49:49.37#ibcon#about to read 4, iclass 35, count 0 2006.175.07:49:49.37#ibcon#read 4, iclass 35, count 0 2006.175.07:49:49.37#ibcon#about to read 5, iclass 35, count 0 2006.175.07:49:49.37#ibcon#read 5, iclass 35, count 0 2006.175.07:49:49.37#ibcon#about to read 6, iclass 35, count 0 2006.175.07:49:49.37#ibcon#read 6, iclass 35, count 0 2006.175.07:49:49.37#ibcon#end of sib2, iclass 35, count 0 2006.175.07:49:49.37#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:49:49.37#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:49:49.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:49:49.37#ibcon#*before write, iclass 35, count 0 2006.175.07:49:49.37#ibcon#enter sib2, iclass 35, count 0 2006.175.07:49:49.37#ibcon#flushed, iclass 35, count 0 2006.175.07:49:49.37#ibcon#about to write, iclass 35, count 0 2006.175.07:49:49.37#ibcon#wrote, iclass 35, count 0 2006.175.07:49:49.37#ibcon#about to read 3, iclass 35, count 0 2006.175.07:49:49.41#ibcon#read 3, iclass 35, count 0 2006.175.07:49:49.41#ibcon#about to read 4, iclass 35, count 0 2006.175.07:49:49.41#ibcon#read 4, iclass 35, count 0 2006.175.07:49:49.41#ibcon#about to read 5, iclass 35, count 0 2006.175.07:49:49.41#ibcon#read 5, iclass 35, count 0 2006.175.07:49:49.41#ibcon#about to read 6, iclass 35, count 0 2006.175.07:49:49.41#ibcon#read 6, iclass 35, count 0 2006.175.07:49:49.41#ibcon#end of sib2, iclass 35, count 0 2006.175.07:49:49.41#ibcon#*after write, iclass 35, count 0 2006.175.07:49:49.41#ibcon#*before return 0, iclass 35, count 0 2006.175.07:49:49.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:49.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:49.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:49:49.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:49:49.41$vc4f8/va=5,7 2006.175.07:49:49.41#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.07:49:49.41#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.07:49:49.41#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:49.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:49.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:49.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:49.47#ibcon#enter wrdev, iclass 37, count 2 2006.175.07:49:49.47#ibcon#first serial, iclass 37, count 2 2006.175.07:49:49.47#ibcon#enter sib2, iclass 37, count 2 2006.175.07:49:49.47#ibcon#flushed, iclass 37, count 2 2006.175.07:49:49.47#ibcon#about to write, iclass 37, count 2 2006.175.07:49:49.47#ibcon#wrote, iclass 37, count 2 2006.175.07:49:49.47#ibcon#about to read 3, iclass 37, count 2 2006.175.07:49:49.49#ibcon#read 3, iclass 37, count 2 2006.175.07:49:49.49#ibcon#about to read 4, iclass 37, count 2 2006.175.07:49:49.49#ibcon#read 4, iclass 37, count 2 2006.175.07:49:49.49#ibcon#about to read 5, iclass 37, count 2 2006.175.07:49:49.49#ibcon#read 5, iclass 37, count 2 2006.175.07:49:49.49#ibcon#about to read 6, iclass 37, count 2 2006.175.07:49:49.49#ibcon#read 6, iclass 37, count 2 2006.175.07:49:49.49#ibcon#end of sib2, iclass 37, count 2 2006.175.07:49:49.49#ibcon#*mode == 0, iclass 37, count 2 2006.175.07:49:49.49#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.07:49:49.49#ibcon#[25=AT05-07\r\n] 2006.175.07:49:49.49#ibcon#*before write, iclass 37, count 2 2006.175.07:49:49.49#ibcon#enter sib2, iclass 37, count 2 2006.175.07:49:49.49#ibcon#flushed, iclass 37, count 2 2006.175.07:49:49.49#ibcon#about to write, iclass 37, count 2 2006.175.07:49:49.49#ibcon#wrote, iclass 37, count 2 2006.175.07:49:49.49#ibcon#about to read 3, iclass 37, count 2 2006.175.07:49:49.52#ibcon#read 3, iclass 37, count 2 2006.175.07:49:49.52#ibcon#about to read 4, iclass 37, count 2 2006.175.07:49:49.52#ibcon#read 4, iclass 37, count 2 2006.175.07:49:49.52#ibcon#about to read 5, iclass 37, count 2 2006.175.07:49:49.52#ibcon#read 5, iclass 37, count 2 2006.175.07:49:49.52#ibcon#about to read 6, iclass 37, count 2 2006.175.07:49:49.52#ibcon#read 6, iclass 37, count 2 2006.175.07:49:49.52#ibcon#end of sib2, iclass 37, count 2 2006.175.07:49:49.52#ibcon#*after write, iclass 37, count 2 2006.175.07:49:49.52#ibcon#*before return 0, iclass 37, count 2 2006.175.07:49:49.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:49.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:49.52#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.07:49:49.52#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:49.52#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:49.64#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:49.64#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:49.64#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:49:49.64#ibcon#first serial, iclass 37, count 0 2006.175.07:49:49.64#ibcon#enter sib2, iclass 37, count 0 2006.175.07:49:49.64#ibcon#flushed, iclass 37, count 0 2006.175.07:49:49.64#ibcon#about to write, iclass 37, count 0 2006.175.07:49:49.64#ibcon#wrote, iclass 37, count 0 2006.175.07:49:49.64#ibcon#about to read 3, iclass 37, count 0 2006.175.07:49:49.66#ibcon#read 3, iclass 37, count 0 2006.175.07:49:49.66#ibcon#about to read 4, iclass 37, count 0 2006.175.07:49:49.66#ibcon#read 4, iclass 37, count 0 2006.175.07:49:49.66#ibcon#about to read 5, iclass 37, count 0 2006.175.07:49:49.66#ibcon#read 5, iclass 37, count 0 2006.175.07:49:49.66#ibcon#about to read 6, iclass 37, count 0 2006.175.07:49:49.66#ibcon#read 6, iclass 37, count 0 2006.175.07:49:49.66#ibcon#end of sib2, iclass 37, count 0 2006.175.07:49:49.66#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:49:49.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:49:49.66#ibcon#[25=USB\r\n] 2006.175.07:49:49.66#ibcon#*before write, iclass 37, count 0 2006.175.07:49:49.66#ibcon#enter sib2, iclass 37, count 0 2006.175.07:49:49.66#ibcon#flushed, iclass 37, count 0 2006.175.07:49:49.66#ibcon#about to write, iclass 37, count 0 2006.175.07:49:49.66#ibcon#wrote, iclass 37, count 0 2006.175.07:49:49.66#ibcon#about to read 3, iclass 37, count 0 2006.175.07:49:49.69#ibcon#read 3, iclass 37, count 0 2006.175.07:49:49.69#ibcon#about to read 4, iclass 37, count 0 2006.175.07:49:49.69#ibcon#read 4, iclass 37, count 0 2006.175.07:49:49.69#ibcon#about to read 5, iclass 37, count 0 2006.175.07:49:49.69#ibcon#read 5, iclass 37, count 0 2006.175.07:49:49.69#ibcon#about to read 6, iclass 37, count 0 2006.175.07:49:49.69#ibcon#read 6, iclass 37, count 0 2006.175.07:49:49.69#ibcon#end of sib2, iclass 37, count 0 2006.175.07:49:49.69#ibcon#*after write, iclass 37, count 0 2006.175.07:49:49.69#ibcon#*before return 0, iclass 37, count 0 2006.175.07:49:49.69#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:49.69#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:49.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:49:49.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:49:49.69$vc4f8/valo=6,772.99 2006.175.07:49:49.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.07:49:49.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.07:49:49.69#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:49.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:49.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:49.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:49.69#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:49:49.69#ibcon#first serial, iclass 39, count 0 2006.175.07:49:49.69#ibcon#enter sib2, iclass 39, count 0 2006.175.07:49:49.69#ibcon#flushed, iclass 39, count 0 2006.175.07:49:49.69#ibcon#about to write, iclass 39, count 0 2006.175.07:49:49.69#ibcon#wrote, iclass 39, count 0 2006.175.07:49:49.69#ibcon#about to read 3, iclass 39, count 0 2006.175.07:49:49.71#ibcon#read 3, iclass 39, count 0 2006.175.07:49:49.71#ibcon#about to read 4, iclass 39, count 0 2006.175.07:49:49.71#ibcon#read 4, iclass 39, count 0 2006.175.07:49:49.71#ibcon#about to read 5, iclass 39, count 0 2006.175.07:49:49.71#ibcon#read 5, iclass 39, count 0 2006.175.07:49:49.71#ibcon#about to read 6, iclass 39, count 0 2006.175.07:49:49.71#ibcon#read 6, iclass 39, count 0 2006.175.07:49:49.71#ibcon#end of sib2, iclass 39, count 0 2006.175.07:49:49.71#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:49:49.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:49:49.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:49:49.71#ibcon#*before write, iclass 39, count 0 2006.175.07:49:49.71#ibcon#enter sib2, iclass 39, count 0 2006.175.07:49:49.71#ibcon#flushed, iclass 39, count 0 2006.175.07:49:49.71#ibcon#about to write, iclass 39, count 0 2006.175.07:49:49.71#ibcon#wrote, iclass 39, count 0 2006.175.07:49:49.71#ibcon#about to read 3, iclass 39, count 0 2006.175.07:49:49.75#ibcon#read 3, iclass 39, count 0 2006.175.07:49:49.75#ibcon#about to read 4, iclass 39, count 0 2006.175.07:49:49.75#ibcon#read 4, iclass 39, count 0 2006.175.07:49:49.75#ibcon#about to read 5, iclass 39, count 0 2006.175.07:49:49.75#ibcon#read 5, iclass 39, count 0 2006.175.07:49:49.75#ibcon#about to read 6, iclass 39, count 0 2006.175.07:49:49.75#ibcon#read 6, iclass 39, count 0 2006.175.07:49:49.75#ibcon#end of sib2, iclass 39, count 0 2006.175.07:49:49.75#ibcon#*after write, iclass 39, count 0 2006.175.07:49:49.75#ibcon#*before return 0, iclass 39, count 0 2006.175.07:49:49.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:49.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:49.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:49:49.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:49:49.75$vc4f8/va=6,6 2006.175.07:49:49.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.07:49:49.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.07:49:49.75#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:49.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:49:49.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:49:49.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:49:49.81#ibcon#enter wrdev, iclass 3, count 2 2006.175.07:49:49.81#ibcon#first serial, iclass 3, count 2 2006.175.07:49:49.81#ibcon#enter sib2, iclass 3, count 2 2006.175.07:49:49.81#ibcon#flushed, iclass 3, count 2 2006.175.07:49:49.81#ibcon#about to write, iclass 3, count 2 2006.175.07:49:49.81#ibcon#wrote, iclass 3, count 2 2006.175.07:49:49.81#ibcon#about to read 3, iclass 3, count 2 2006.175.07:49:49.83#ibcon#read 3, iclass 3, count 2 2006.175.07:49:49.83#ibcon#about to read 4, iclass 3, count 2 2006.175.07:49:49.83#ibcon#read 4, iclass 3, count 2 2006.175.07:49:49.83#ibcon#about to read 5, iclass 3, count 2 2006.175.07:49:49.83#ibcon#read 5, iclass 3, count 2 2006.175.07:49:49.83#ibcon#about to read 6, iclass 3, count 2 2006.175.07:49:49.83#ibcon#read 6, iclass 3, count 2 2006.175.07:49:49.83#ibcon#end of sib2, iclass 3, count 2 2006.175.07:49:49.83#ibcon#*mode == 0, iclass 3, count 2 2006.175.07:49:49.83#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.07:49:49.83#ibcon#[25=AT06-06\r\n] 2006.175.07:49:49.83#ibcon#*before write, iclass 3, count 2 2006.175.07:49:49.83#ibcon#enter sib2, iclass 3, count 2 2006.175.07:49:49.83#ibcon#flushed, iclass 3, count 2 2006.175.07:49:49.83#ibcon#about to write, iclass 3, count 2 2006.175.07:49:49.83#ibcon#wrote, iclass 3, count 2 2006.175.07:49:49.83#ibcon#about to read 3, iclass 3, count 2 2006.175.07:49:49.86#ibcon#read 3, iclass 3, count 2 2006.175.07:49:49.86#ibcon#about to read 4, iclass 3, count 2 2006.175.07:49:49.86#ibcon#read 4, iclass 3, count 2 2006.175.07:49:49.86#ibcon#about to read 5, iclass 3, count 2 2006.175.07:49:49.86#ibcon#read 5, iclass 3, count 2 2006.175.07:49:49.86#ibcon#about to read 6, iclass 3, count 2 2006.175.07:49:49.86#ibcon#read 6, iclass 3, count 2 2006.175.07:49:49.86#ibcon#end of sib2, iclass 3, count 2 2006.175.07:49:49.86#ibcon#*after write, iclass 3, count 2 2006.175.07:49:49.86#ibcon#*before return 0, iclass 3, count 2 2006.175.07:49:49.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:49:49.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:49:49.86#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.07:49:49.86#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:49.86#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:49:49.98#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:49:49.98#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:49:49.98#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:49:49.98#ibcon#first serial, iclass 3, count 0 2006.175.07:49:49.98#ibcon#enter sib2, iclass 3, count 0 2006.175.07:49:49.98#ibcon#flushed, iclass 3, count 0 2006.175.07:49:49.98#ibcon#about to write, iclass 3, count 0 2006.175.07:49:49.98#ibcon#wrote, iclass 3, count 0 2006.175.07:49:49.98#ibcon#about to read 3, iclass 3, count 0 2006.175.07:49:50.00#ibcon#read 3, iclass 3, count 0 2006.175.07:49:50.00#ibcon#about to read 4, iclass 3, count 0 2006.175.07:49:50.00#ibcon#read 4, iclass 3, count 0 2006.175.07:49:50.00#ibcon#about to read 5, iclass 3, count 0 2006.175.07:49:50.00#ibcon#read 5, iclass 3, count 0 2006.175.07:49:50.00#ibcon#about to read 6, iclass 3, count 0 2006.175.07:49:50.00#ibcon#read 6, iclass 3, count 0 2006.175.07:49:50.00#ibcon#end of sib2, iclass 3, count 0 2006.175.07:49:50.00#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:49:50.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:49:50.00#ibcon#[25=USB\r\n] 2006.175.07:49:50.00#ibcon#*before write, iclass 3, count 0 2006.175.07:49:50.00#ibcon#enter sib2, iclass 3, count 0 2006.175.07:49:50.00#ibcon#flushed, iclass 3, count 0 2006.175.07:49:50.00#ibcon#about to write, iclass 3, count 0 2006.175.07:49:50.00#ibcon#wrote, iclass 3, count 0 2006.175.07:49:50.00#ibcon#about to read 3, iclass 3, count 0 2006.175.07:49:50.03#ibcon#read 3, iclass 3, count 0 2006.175.07:49:50.03#ibcon#about to read 4, iclass 3, count 0 2006.175.07:49:50.03#ibcon#read 4, iclass 3, count 0 2006.175.07:49:50.03#ibcon#about to read 5, iclass 3, count 0 2006.175.07:49:50.03#ibcon#read 5, iclass 3, count 0 2006.175.07:49:50.03#ibcon#about to read 6, iclass 3, count 0 2006.175.07:49:50.03#ibcon#read 6, iclass 3, count 0 2006.175.07:49:50.03#ibcon#end of sib2, iclass 3, count 0 2006.175.07:49:50.03#ibcon#*after write, iclass 3, count 0 2006.175.07:49:50.03#ibcon#*before return 0, iclass 3, count 0 2006.175.07:49:50.03#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:49:50.03#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:49:50.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:49:50.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:49:50.03$vc4f8/valo=7,832.99 2006.175.07:49:50.03#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.07:49:50.03#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.07:49:50.03#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:50.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:49:50.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:49:50.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:49:50.03#ibcon#enter wrdev, iclass 5, count 0 2006.175.07:49:50.03#ibcon#first serial, iclass 5, count 0 2006.175.07:49:50.03#ibcon#enter sib2, iclass 5, count 0 2006.175.07:49:50.03#ibcon#flushed, iclass 5, count 0 2006.175.07:49:50.03#ibcon#about to write, iclass 5, count 0 2006.175.07:49:50.03#ibcon#wrote, iclass 5, count 0 2006.175.07:49:50.03#ibcon#about to read 3, iclass 5, count 0 2006.175.07:49:50.05#ibcon#read 3, iclass 5, count 0 2006.175.07:49:50.05#ibcon#about to read 4, iclass 5, count 0 2006.175.07:49:50.05#ibcon#read 4, iclass 5, count 0 2006.175.07:49:50.05#ibcon#about to read 5, iclass 5, count 0 2006.175.07:49:50.05#ibcon#read 5, iclass 5, count 0 2006.175.07:49:50.05#ibcon#about to read 6, iclass 5, count 0 2006.175.07:49:50.05#ibcon#read 6, iclass 5, count 0 2006.175.07:49:50.05#ibcon#end of sib2, iclass 5, count 0 2006.175.07:49:50.05#ibcon#*mode == 0, iclass 5, count 0 2006.175.07:49:50.05#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.07:49:50.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:49:50.05#ibcon#*before write, iclass 5, count 0 2006.175.07:49:50.05#ibcon#enter sib2, iclass 5, count 0 2006.175.07:49:50.05#ibcon#flushed, iclass 5, count 0 2006.175.07:49:50.05#ibcon#about to write, iclass 5, count 0 2006.175.07:49:50.05#ibcon#wrote, iclass 5, count 0 2006.175.07:49:50.05#ibcon#about to read 3, iclass 5, count 0 2006.175.07:49:50.09#ibcon#read 3, iclass 5, count 0 2006.175.07:49:50.09#ibcon#about to read 4, iclass 5, count 0 2006.175.07:49:50.09#ibcon#read 4, iclass 5, count 0 2006.175.07:49:50.09#ibcon#about to read 5, iclass 5, count 0 2006.175.07:49:50.09#ibcon#read 5, iclass 5, count 0 2006.175.07:49:50.09#ibcon#about to read 6, iclass 5, count 0 2006.175.07:49:50.09#ibcon#read 6, iclass 5, count 0 2006.175.07:49:50.09#ibcon#end of sib2, iclass 5, count 0 2006.175.07:49:50.09#ibcon#*after write, iclass 5, count 0 2006.175.07:49:50.09#ibcon#*before return 0, iclass 5, count 0 2006.175.07:49:50.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:49:50.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:49:50.09#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.07:49:50.09#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.07:49:50.09$vc4f8/va=7,6 2006.175.07:49:50.09#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.07:49:50.09#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.07:49:50.09#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:50.09#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:49:50.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:49:50.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:49:50.15#ibcon#enter wrdev, iclass 7, count 2 2006.175.07:49:50.15#ibcon#first serial, iclass 7, count 2 2006.175.07:49:50.15#ibcon#enter sib2, iclass 7, count 2 2006.175.07:49:50.15#ibcon#flushed, iclass 7, count 2 2006.175.07:49:50.15#ibcon#about to write, iclass 7, count 2 2006.175.07:49:50.15#ibcon#wrote, iclass 7, count 2 2006.175.07:49:50.15#ibcon#about to read 3, iclass 7, count 2 2006.175.07:49:50.17#ibcon#read 3, iclass 7, count 2 2006.175.07:49:50.17#ibcon#about to read 4, iclass 7, count 2 2006.175.07:49:50.17#ibcon#read 4, iclass 7, count 2 2006.175.07:49:50.17#ibcon#about to read 5, iclass 7, count 2 2006.175.07:49:50.17#ibcon#read 5, iclass 7, count 2 2006.175.07:49:50.17#ibcon#about to read 6, iclass 7, count 2 2006.175.07:49:50.17#ibcon#read 6, iclass 7, count 2 2006.175.07:49:50.17#ibcon#end of sib2, iclass 7, count 2 2006.175.07:49:50.17#ibcon#*mode == 0, iclass 7, count 2 2006.175.07:49:50.17#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.07:49:50.17#ibcon#[25=AT07-06\r\n] 2006.175.07:49:50.17#ibcon#*before write, iclass 7, count 2 2006.175.07:49:50.17#ibcon#enter sib2, iclass 7, count 2 2006.175.07:49:50.17#ibcon#flushed, iclass 7, count 2 2006.175.07:49:50.17#ibcon#about to write, iclass 7, count 2 2006.175.07:49:50.17#ibcon#wrote, iclass 7, count 2 2006.175.07:49:50.17#ibcon#about to read 3, iclass 7, count 2 2006.175.07:49:50.20#ibcon#read 3, iclass 7, count 2 2006.175.07:49:50.20#ibcon#about to read 4, iclass 7, count 2 2006.175.07:49:50.20#ibcon#read 4, iclass 7, count 2 2006.175.07:49:50.20#ibcon#about to read 5, iclass 7, count 2 2006.175.07:49:50.20#ibcon#read 5, iclass 7, count 2 2006.175.07:49:50.20#ibcon#about to read 6, iclass 7, count 2 2006.175.07:49:50.20#ibcon#read 6, iclass 7, count 2 2006.175.07:49:50.20#ibcon#end of sib2, iclass 7, count 2 2006.175.07:49:50.20#ibcon#*after write, iclass 7, count 2 2006.175.07:49:50.20#ibcon#*before return 0, iclass 7, count 2 2006.175.07:49:50.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:49:50.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:49:50.20#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.07:49:50.20#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:50.20#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:49:50.32#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:49:50.32#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:49:50.32#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:49:50.32#ibcon#first serial, iclass 7, count 0 2006.175.07:49:50.32#ibcon#enter sib2, iclass 7, count 0 2006.175.07:49:50.32#ibcon#flushed, iclass 7, count 0 2006.175.07:49:50.32#ibcon#about to write, iclass 7, count 0 2006.175.07:49:50.32#ibcon#wrote, iclass 7, count 0 2006.175.07:49:50.32#ibcon#about to read 3, iclass 7, count 0 2006.175.07:49:50.34#ibcon#read 3, iclass 7, count 0 2006.175.07:49:50.34#ibcon#about to read 4, iclass 7, count 0 2006.175.07:49:50.34#ibcon#read 4, iclass 7, count 0 2006.175.07:49:50.34#ibcon#about to read 5, iclass 7, count 0 2006.175.07:49:50.34#ibcon#read 5, iclass 7, count 0 2006.175.07:49:50.34#ibcon#about to read 6, iclass 7, count 0 2006.175.07:49:50.34#ibcon#read 6, iclass 7, count 0 2006.175.07:49:50.34#ibcon#end of sib2, iclass 7, count 0 2006.175.07:49:50.34#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:49:50.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:49:50.34#ibcon#[25=USB\r\n] 2006.175.07:49:50.34#ibcon#*before write, iclass 7, count 0 2006.175.07:49:50.34#ibcon#enter sib2, iclass 7, count 0 2006.175.07:49:50.34#ibcon#flushed, iclass 7, count 0 2006.175.07:49:50.34#ibcon#about to write, iclass 7, count 0 2006.175.07:49:50.34#ibcon#wrote, iclass 7, count 0 2006.175.07:49:50.34#ibcon#about to read 3, iclass 7, count 0 2006.175.07:49:50.37#ibcon#read 3, iclass 7, count 0 2006.175.07:49:50.37#ibcon#about to read 4, iclass 7, count 0 2006.175.07:49:50.37#ibcon#read 4, iclass 7, count 0 2006.175.07:49:50.37#ibcon#about to read 5, iclass 7, count 0 2006.175.07:49:50.37#ibcon#read 5, iclass 7, count 0 2006.175.07:49:50.37#ibcon#about to read 6, iclass 7, count 0 2006.175.07:49:50.37#ibcon#read 6, iclass 7, count 0 2006.175.07:49:50.37#ibcon#end of sib2, iclass 7, count 0 2006.175.07:49:50.37#ibcon#*after write, iclass 7, count 0 2006.175.07:49:50.37#ibcon#*before return 0, iclass 7, count 0 2006.175.07:49:50.37#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:49:50.37#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:49:50.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:49:50.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:49:50.37$vc4f8/valo=8,852.99 2006.175.07:49:50.37#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.07:49:50.37#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.07:49:50.37#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:50.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:49:50.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:49:50.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:49:50.37#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:49:50.37#ibcon#first serial, iclass 11, count 0 2006.175.07:49:50.37#ibcon#enter sib2, iclass 11, count 0 2006.175.07:49:50.37#ibcon#flushed, iclass 11, count 0 2006.175.07:49:50.37#ibcon#about to write, iclass 11, count 0 2006.175.07:49:50.37#ibcon#wrote, iclass 11, count 0 2006.175.07:49:50.37#ibcon#about to read 3, iclass 11, count 0 2006.175.07:49:50.39#ibcon#read 3, iclass 11, count 0 2006.175.07:49:50.39#ibcon#about to read 4, iclass 11, count 0 2006.175.07:49:50.39#ibcon#read 4, iclass 11, count 0 2006.175.07:49:50.39#ibcon#about to read 5, iclass 11, count 0 2006.175.07:49:50.39#ibcon#read 5, iclass 11, count 0 2006.175.07:49:50.39#ibcon#about to read 6, iclass 11, count 0 2006.175.07:49:50.39#ibcon#read 6, iclass 11, count 0 2006.175.07:49:50.39#ibcon#end of sib2, iclass 11, count 0 2006.175.07:49:50.39#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:49:50.39#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:49:50.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:49:50.39#ibcon#*before write, iclass 11, count 0 2006.175.07:49:50.39#ibcon#enter sib2, iclass 11, count 0 2006.175.07:49:50.39#ibcon#flushed, iclass 11, count 0 2006.175.07:49:50.39#ibcon#about to write, iclass 11, count 0 2006.175.07:49:50.39#ibcon#wrote, iclass 11, count 0 2006.175.07:49:50.39#ibcon#about to read 3, iclass 11, count 0 2006.175.07:49:50.43#ibcon#read 3, iclass 11, count 0 2006.175.07:49:50.43#ibcon#about to read 4, iclass 11, count 0 2006.175.07:49:50.43#ibcon#read 4, iclass 11, count 0 2006.175.07:49:50.43#ibcon#about to read 5, iclass 11, count 0 2006.175.07:49:50.43#ibcon#read 5, iclass 11, count 0 2006.175.07:49:50.43#ibcon#about to read 6, iclass 11, count 0 2006.175.07:49:50.43#ibcon#read 6, iclass 11, count 0 2006.175.07:49:50.43#ibcon#end of sib2, iclass 11, count 0 2006.175.07:49:50.43#ibcon#*after write, iclass 11, count 0 2006.175.07:49:50.43#ibcon#*before return 0, iclass 11, count 0 2006.175.07:49:50.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:49:50.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:49:50.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:49:50.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:49:50.43$vc4f8/va=8,6 2006.175.07:49:50.43#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.07:49:50.43#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.07:49:50.43#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:50.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:49:50.49#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:49:50.49#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:49:50.49#ibcon#enter wrdev, iclass 13, count 2 2006.175.07:49:50.49#ibcon#first serial, iclass 13, count 2 2006.175.07:49:50.49#ibcon#enter sib2, iclass 13, count 2 2006.175.07:49:50.49#ibcon#flushed, iclass 13, count 2 2006.175.07:49:50.49#ibcon#about to write, iclass 13, count 2 2006.175.07:49:50.49#ibcon#wrote, iclass 13, count 2 2006.175.07:49:50.49#ibcon#about to read 3, iclass 13, count 2 2006.175.07:49:50.51#ibcon#read 3, iclass 13, count 2 2006.175.07:49:50.51#ibcon#about to read 4, iclass 13, count 2 2006.175.07:49:50.51#ibcon#read 4, iclass 13, count 2 2006.175.07:49:50.51#ibcon#about to read 5, iclass 13, count 2 2006.175.07:49:50.51#ibcon#read 5, iclass 13, count 2 2006.175.07:49:50.51#ibcon#about to read 6, iclass 13, count 2 2006.175.07:49:50.51#ibcon#read 6, iclass 13, count 2 2006.175.07:49:50.51#ibcon#end of sib2, iclass 13, count 2 2006.175.07:49:50.51#ibcon#*mode == 0, iclass 13, count 2 2006.175.07:49:50.51#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.07:49:50.51#ibcon#[25=AT08-06\r\n] 2006.175.07:49:50.51#ibcon#*before write, iclass 13, count 2 2006.175.07:49:50.51#ibcon#enter sib2, iclass 13, count 2 2006.175.07:49:50.51#ibcon#flushed, iclass 13, count 2 2006.175.07:49:50.51#ibcon#about to write, iclass 13, count 2 2006.175.07:49:50.51#ibcon#wrote, iclass 13, count 2 2006.175.07:49:50.51#ibcon#about to read 3, iclass 13, count 2 2006.175.07:49:50.54#ibcon#read 3, iclass 13, count 2 2006.175.07:49:50.54#ibcon#about to read 4, iclass 13, count 2 2006.175.07:49:50.54#ibcon#read 4, iclass 13, count 2 2006.175.07:49:50.54#ibcon#about to read 5, iclass 13, count 2 2006.175.07:49:50.54#ibcon#read 5, iclass 13, count 2 2006.175.07:49:50.54#ibcon#about to read 6, iclass 13, count 2 2006.175.07:49:50.54#ibcon#read 6, iclass 13, count 2 2006.175.07:49:50.54#ibcon#end of sib2, iclass 13, count 2 2006.175.07:49:50.54#ibcon#*after write, iclass 13, count 2 2006.175.07:49:50.54#ibcon#*before return 0, iclass 13, count 2 2006.175.07:49:50.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:49:50.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:49:50.54#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.07:49:50.54#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:50.54#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:49:50.66#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:49:50.66#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:49:50.66#ibcon#enter wrdev, iclass 13, count 0 2006.175.07:49:50.66#ibcon#first serial, iclass 13, count 0 2006.175.07:49:50.66#ibcon#enter sib2, iclass 13, count 0 2006.175.07:49:50.66#ibcon#flushed, iclass 13, count 0 2006.175.07:49:50.66#ibcon#about to write, iclass 13, count 0 2006.175.07:49:50.66#ibcon#wrote, iclass 13, count 0 2006.175.07:49:50.66#ibcon#about to read 3, iclass 13, count 0 2006.175.07:49:50.68#ibcon#read 3, iclass 13, count 0 2006.175.07:49:50.68#ibcon#about to read 4, iclass 13, count 0 2006.175.07:49:50.68#ibcon#read 4, iclass 13, count 0 2006.175.07:49:50.68#ibcon#about to read 5, iclass 13, count 0 2006.175.07:49:50.68#ibcon#read 5, iclass 13, count 0 2006.175.07:49:50.68#ibcon#about to read 6, iclass 13, count 0 2006.175.07:49:50.68#ibcon#read 6, iclass 13, count 0 2006.175.07:49:50.68#ibcon#end of sib2, iclass 13, count 0 2006.175.07:49:50.68#ibcon#*mode == 0, iclass 13, count 0 2006.175.07:49:50.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.07:49:50.68#ibcon#[25=USB\r\n] 2006.175.07:49:50.68#ibcon#*before write, iclass 13, count 0 2006.175.07:49:50.68#ibcon#enter sib2, iclass 13, count 0 2006.175.07:49:50.68#ibcon#flushed, iclass 13, count 0 2006.175.07:49:50.68#ibcon#about to write, iclass 13, count 0 2006.175.07:49:50.68#ibcon#wrote, iclass 13, count 0 2006.175.07:49:50.68#ibcon#about to read 3, iclass 13, count 0 2006.175.07:49:50.71#ibcon#read 3, iclass 13, count 0 2006.175.07:49:50.71#ibcon#about to read 4, iclass 13, count 0 2006.175.07:49:50.71#ibcon#read 4, iclass 13, count 0 2006.175.07:49:50.71#ibcon#about to read 5, iclass 13, count 0 2006.175.07:49:50.71#ibcon#read 5, iclass 13, count 0 2006.175.07:49:50.71#ibcon#about to read 6, iclass 13, count 0 2006.175.07:49:50.71#ibcon#read 6, iclass 13, count 0 2006.175.07:49:50.71#ibcon#end of sib2, iclass 13, count 0 2006.175.07:49:50.71#ibcon#*after write, iclass 13, count 0 2006.175.07:49:50.71#ibcon#*before return 0, iclass 13, count 0 2006.175.07:49:50.71#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:49:50.71#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:49:50.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.07:49:50.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.07:49:50.71$vc4f8/vblo=1,632.99 2006.175.07:49:50.71#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.07:49:50.71#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.07:49:50.71#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:50.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:50.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:50.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:50.71#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:49:50.71#ibcon#first serial, iclass 15, count 0 2006.175.07:49:50.71#ibcon#enter sib2, iclass 15, count 0 2006.175.07:49:50.71#ibcon#flushed, iclass 15, count 0 2006.175.07:49:50.71#ibcon#about to write, iclass 15, count 0 2006.175.07:49:50.71#ibcon#wrote, iclass 15, count 0 2006.175.07:49:50.71#ibcon#about to read 3, iclass 15, count 0 2006.175.07:49:50.73#ibcon#read 3, iclass 15, count 0 2006.175.07:49:50.73#ibcon#about to read 4, iclass 15, count 0 2006.175.07:49:50.73#ibcon#read 4, iclass 15, count 0 2006.175.07:49:50.73#ibcon#about to read 5, iclass 15, count 0 2006.175.07:49:50.73#ibcon#read 5, iclass 15, count 0 2006.175.07:49:50.73#ibcon#about to read 6, iclass 15, count 0 2006.175.07:49:50.73#ibcon#read 6, iclass 15, count 0 2006.175.07:49:50.73#ibcon#end of sib2, iclass 15, count 0 2006.175.07:49:50.73#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:49:50.73#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:49:50.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:49:50.73#ibcon#*before write, iclass 15, count 0 2006.175.07:49:50.73#ibcon#enter sib2, iclass 15, count 0 2006.175.07:49:50.73#ibcon#flushed, iclass 15, count 0 2006.175.07:49:50.73#ibcon#about to write, iclass 15, count 0 2006.175.07:49:50.73#ibcon#wrote, iclass 15, count 0 2006.175.07:49:50.73#ibcon#about to read 3, iclass 15, count 0 2006.175.07:49:50.77#ibcon#read 3, iclass 15, count 0 2006.175.07:49:50.77#ibcon#about to read 4, iclass 15, count 0 2006.175.07:49:50.77#ibcon#read 4, iclass 15, count 0 2006.175.07:49:50.77#ibcon#about to read 5, iclass 15, count 0 2006.175.07:49:50.77#ibcon#read 5, iclass 15, count 0 2006.175.07:49:50.77#ibcon#about to read 6, iclass 15, count 0 2006.175.07:49:50.77#ibcon#read 6, iclass 15, count 0 2006.175.07:49:50.77#ibcon#end of sib2, iclass 15, count 0 2006.175.07:49:50.77#ibcon#*after write, iclass 15, count 0 2006.175.07:49:50.77#ibcon#*before return 0, iclass 15, count 0 2006.175.07:49:50.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:50.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:49:50.77#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:49:50.77#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:49:50.77$vc4f8/vb=1,4 2006.175.07:49:50.77#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.07:49:50.77#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.07:49:50.77#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:50.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:50.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:50.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:50.77#ibcon#enter wrdev, iclass 17, count 2 2006.175.07:49:50.77#ibcon#first serial, iclass 17, count 2 2006.175.07:49:50.77#ibcon#enter sib2, iclass 17, count 2 2006.175.07:49:50.77#ibcon#flushed, iclass 17, count 2 2006.175.07:49:50.77#ibcon#about to write, iclass 17, count 2 2006.175.07:49:50.77#ibcon#wrote, iclass 17, count 2 2006.175.07:49:50.77#ibcon#about to read 3, iclass 17, count 2 2006.175.07:49:50.79#ibcon#read 3, iclass 17, count 2 2006.175.07:49:50.79#ibcon#about to read 4, iclass 17, count 2 2006.175.07:49:50.79#ibcon#read 4, iclass 17, count 2 2006.175.07:49:50.79#ibcon#about to read 5, iclass 17, count 2 2006.175.07:49:50.79#ibcon#read 5, iclass 17, count 2 2006.175.07:49:50.79#ibcon#about to read 6, iclass 17, count 2 2006.175.07:49:50.79#ibcon#read 6, iclass 17, count 2 2006.175.07:49:50.79#ibcon#end of sib2, iclass 17, count 2 2006.175.07:49:50.79#ibcon#*mode == 0, iclass 17, count 2 2006.175.07:49:50.79#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.07:49:50.79#ibcon#[27=AT01-04\r\n] 2006.175.07:49:50.79#ibcon#*before write, iclass 17, count 2 2006.175.07:49:50.79#ibcon#enter sib2, iclass 17, count 2 2006.175.07:49:50.79#ibcon#flushed, iclass 17, count 2 2006.175.07:49:50.79#ibcon#about to write, iclass 17, count 2 2006.175.07:49:50.79#ibcon#wrote, iclass 17, count 2 2006.175.07:49:50.79#ibcon#about to read 3, iclass 17, count 2 2006.175.07:49:50.82#ibcon#read 3, iclass 17, count 2 2006.175.07:49:50.82#ibcon#about to read 4, iclass 17, count 2 2006.175.07:49:50.82#ibcon#read 4, iclass 17, count 2 2006.175.07:49:50.82#ibcon#about to read 5, iclass 17, count 2 2006.175.07:49:50.82#ibcon#read 5, iclass 17, count 2 2006.175.07:49:50.82#ibcon#about to read 6, iclass 17, count 2 2006.175.07:49:50.82#ibcon#read 6, iclass 17, count 2 2006.175.07:49:50.82#ibcon#end of sib2, iclass 17, count 2 2006.175.07:49:50.82#ibcon#*after write, iclass 17, count 2 2006.175.07:49:50.82#ibcon#*before return 0, iclass 17, count 2 2006.175.07:49:50.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:50.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.07:49:50.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.07:49:50.82#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:50.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:50.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:50.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:50.94#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:49:50.94#ibcon#first serial, iclass 17, count 0 2006.175.07:49:50.94#ibcon#enter sib2, iclass 17, count 0 2006.175.07:49:50.94#ibcon#flushed, iclass 17, count 0 2006.175.07:49:50.94#ibcon#about to write, iclass 17, count 0 2006.175.07:49:50.94#ibcon#wrote, iclass 17, count 0 2006.175.07:49:50.94#ibcon#about to read 3, iclass 17, count 0 2006.175.07:49:50.96#ibcon#read 3, iclass 17, count 0 2006.175.07:49:50.96#ibcon#about to read 4, iclass 17, count 0 2006.175.07:49:50.96#ibcon#read 4, iclass 17, count 0 2006.175.07:49:50.96#ibcon#about to read 5, iclass 17, count 0 2006.175.07:49:50.96#ibcon#read 5, iclass 17, count 0 2006.175.07:49:50.96#ibcon#about to read 6, iclass 17, count 0 2006.175.07:49:50.96#ibcon#read 6, iclass 17, count 0 2006.175.07:49:50.96#ibcon#end of sib2, iclass 17, count 0 2006.175.07:49:50.96#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:49:50.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:49:50.96#ibcon#[27=USB\r\n] 2006.175.07:49:50.96#ibcon#*before write, iclass 17, count 0 2006.175.07:49:50.96#ibcon#enter sib2, iclass 17, count 0 2006.175.07:49:50.96#ibcon#flushed, iclass 17, count 0 2006.175.07:49:50.96#ibcon#about to write, iclass 17, count 0 2006.175.07:49:50.96#ibcon#wrote, iclass 17, count 0 2006.175.07:49:50.96#ibcon#about to read 3, iclass 17, count 0 2006.175.07:49:50.99#ibcon#read 3, iclass 17, count 0 2006.175.07:49:50.99#ibcon#about to read 4, iclass 17, count 0 2006.175.07:49:50.99#ibcon#read 4, iclass 17, count 0 2006.175.07:49:50.99#ibcon#about to read 5, iclass 17, count 0 2006.175.07:49:50.99#ibcon#read 5, iclass 17, count 0 2006.175.07:49:50.99#ibcon#about to read 6, iclass 17, count 0 2006.175.07:49:50.99#ibcon#read 6, iclass 17, count 0 2006.175.07:49:50.99#ibcon#end of sib2, iclass 17, count 0 2006.175.07:49:50.99#ibcon#*after write, iclass 17, count 0 2006.175.07:49:50.99#ibcon#*before return 0, iclass 17, count 0 2006.175.07:49:50.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:50.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.07:49:50.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:49:50.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:49:50.99$vc4f8/vblo=2,640.99 2006.175.07:49:50.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.07:49:50.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.07:49:50.99#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:50.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:50.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:50.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:50.99#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:49:50.99#ibcon#first serial, iclass 19, count 0 2006.175.07:49:50.99#ibcon#enter sib2, iclass 19, count 0 2006.175.07:49:50.99#ibcon#flushed, iclass 19, count 0 2006.175.07:49:50.99#ibcon#about to write, iclass 19, count 0 2006.175.07:49:50.99#ibcon#wrote, iclass 19, count 0 2006.175.07:49:50.99#ibcon#about to read 3, iclass 19, count 0 2006.175.07:49:51.01#ibcon#read 3, iclass 19, count 0 2006.175.07:49:51.01#ibcon#about to read 4, iclass 19, count 0 2006.175.07:49:51.01#ibcon#read 4, iclass 19, count 0 2006.175.07:49:51.01#ibcon#about to read 5, iclass 19, count 0 2006.175.07:49:51.01#ibcon#read 5, iclass 19, count 0 2006.175.07:49:51.01#ibcon#about to read 6, iclass 19, count 0 2006.175.07:49:51.01#ibcon#read 6, iclass 19, count 0 2006.175.07:49:51.01#ibcon#end of sib2, iclass 19, count 0 2006.175.07:49:51.01#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:49:51.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:49:51.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:49:51.01#ibcon#*before write, iclass 19, count 0 2006.175.07:49:51.01#ibcon#enter sib2, iclass 19, count 0 2006.175.07:49:51.01#ibcon#flushed, iclass 19, count 0 2006.175.07:49:51.01#ibcon#about to write, iclass 19, count 0 2006.175.07:49:51.01#ibcon#wrote, iclass 19, count 0 2006.175.07:49:51.01#ibcon#about to read 3, iclass 19, count 0 2006.175.07:49:51.05#ibcon#read 3, iclass 19, count 0 2006.175.07:49:51.05#ibcon#about to read 4, iclass 19, count 0 2006.175.07:49:51.05#ibcon#read 4, iclass 19, count 0 2006.175.07:49:51.05#ibcon#about to read 5, iclass 19, count 0 2006.175.07:49:51.05#ibcon#read 5, iclass 19, count 0 2006.175.07:49:51.05#ibcon#about to read 6, iclass 19, count 0 2006.175.07:49:51.05#ibcon#read 6, iclass 19, count 0 2006.175.07:49:51.05#ibcon#end of sib2, iclass 19, count 0 2006.175.07:49:51.05#ibcon#*after write, iclass 19, count 0 2006.175.07:49:51.05#ibcon#*before return 0, iclass 19, count 0 2006.175.07:49:51.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:51.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.07:49:51.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:49:51.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:49:51.05$vc4f8/vb=2,4 2006.175.07:49:51.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.07:49:51.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.07:49:51.05#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:51.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:51.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:51.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:51.11#ibcon#enter wrdev, iclass 21, count 2 2006.175.07:49:51.11#ibcon#first serial, iclass 21, count 2 2006.175.07:49:51.11#ibcon#enter sib2, iclass 21, count 2 2006.175.07:49:51.11#ibcon#flushed, iclass 21, count 2 2006.175.07:49:51.11#ibcon#about to write, iclass 21, count 2 2006.175.07:49:51.11#ibcon#wrote, iclass 21, count 2 2006.175.07:49:51.11#ibcon#about to read 3, iclass 21, count 2 2006.175.07:49:51.13#ibcon#read 3, iclass 21, count 2 2006.175.07:49:51.13#ibcon#about to read 4, iclass 21, count 2 2006.175.07:49:51.13#ibcon#read 4, iclass 21, count 2 2006.175.07:49:51.13#ibcon#about to read 5, iclass 21, count 2 2006.175.07:49:51.13#ibcon#read 5, iclass 21, count 2 2006.175.07:49:51.13#ibcon#about to read 6, iclass 21, count 2 2006.175.07:49:51.13#ibcon#read 6, iclass 21, count 2 2006.175.07:49:51.13#ibcon#end of sib2, iclass 21, count 2 2006.175.07:49:51.13#ibcon#*mode == 0, iclass 21, count 2 2006.175.07:49:51.13#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.07:49:51.13#ibcon#[27=AT02-04\r\n] 2006.175.07:49:51.13#ibcon#*before write, iclass 21, count 2 2006.175.07:49:51.13#ibcon#enter sib2, iclass 21, count 2 2006.175.07:49:51.13#ibcon#flushed, iclass 21, count 2 2006.175.07:49:51.13#ibcon#about to write, iclass 21, count 2 2006.175.07:49:51.13#ibcon#wrote, iclass 21, count 2 2006.175.07:49:51.13#ibcon#about to read 3, iclass 21, count 2 2006.175.07:49:51.16#ibcon#read 3, iclass 21, count 2 2006.175.07:49:51.16#ibcon#about to read 4, iclass 21, count 2 2006.175.07:49:51.16#ibcon#read 4, iclass 21, count 2 2006.175.07:49:51.16#ibcon#about to read 5, iclass 21, count 2 2006.175.07:49:51.16#ibcon#read 5, iclass 21, count 2 2006.175.07:49:51.16#ibcon#about to read 6, iclass 21, count 2 2006.175.07:49:51.16#ibcon#read 6, iclass 21, count 2 2006.175.07:49:51.16#ibcon#end of sib2, iclass 21, count 2 2006.175.07:49:51.16#ibcon#*after write, iclass 21, count 2 2006.175.07:49:51.16#ibcon#*before return 0, iclass 21, count 2 2006.175.07:49:51.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:51.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.07:49:51.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.07:49:51.16#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:51.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:51.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:51.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:51.28#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:49:51.28#ibcon#first serial, iclass 21, count 0 2006.175.07:49:51.28#ibcon#enter sib2, iclass 21, count 0 2006.175.07:49:51.28#ibcon#flushed, iclass 21, count 0 2006.175.07:49:51.28#ibcon#about to write, iclass 21, count 0 2006.175.07:49:51.28#ibcon#wrote, iclass 21, count 0 2006.175.07:49:51.28#ibcon#about to read 3, iclass 21, count 0 2006.175.07:49:51.30#ibcon#read 3, iclass 21, count 0 2006.175.07:49:51.30#ibcon#about to read 4, iclass 21, count 0 2006.175.07:49:51.30#ibcon#read 4, iclass 21, count 0 2006.175.07:49:51.30#ibcon#about to read 5, iclass 21, count 0 2006.175.07:49:51.30#ibcon#read 5, iclass 21, count 0 2006.175.07:49:51.30#ibcon#about to read 6, iclass 21, count 0 2006.175.07:49:51.30#ibcon#read 6, iclass 21, count 0 2006.175.07:49:51.30#ibcon#end of sib2, iclass 21, count 0 2006.175.07:49:51.30#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:49:51.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:49:51.30#ibcon#[27=USB\r\n] 2006.175.07:49:51.30#ibcon#*before write, iclass 21, count 0 2006.175.07:49:51.30#ibcon#enter sib2, iclass 21, count 0 2006.175.07:49:51.30#ibcon#flushed, iclass 21, count 0 2006.175.07:49:51.30#ibcon#about to write, iclass 21, count 0 2006.175.07:49:51.30#ibcon#wrote, iclass 21, count 0 2006.175.07:49:51.30#ibcon#about to read 3, iclass 21, count 0 2006.175.07:49:51.33#ibcon#read 3, iclass 21, count 0 2006.175.07:49:51.33#ibcon#about to read 4, iclass 21, count 0 2006.175.07:49:51.33#ibcon#read 4, iclass 21, count 0 2006.175.07:49:51.33#ibcon#about to read 5, iclass 21, count 0 2006.175.07:49:51.33#ibcon#read 5, iclass 21, count 0 2006.175.07:49:51.33#ibcon#about to read 6, iclass 21, count 0 2006.175.07:49:51.33#ibcon#read 6, iclass 21, count 0 2006.175.07:49:51.33#ibcon#end of sib2, iclass 21, count 0 2006.175.07:49:51.33#ibcon#*after write, iclass 21, count 0 2006.175.07:49:51.33#ibcon#*before return 0, iclass 21, count 0 2006.175.07:49:51.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:51.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.07:49:51.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:49:51.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:49:51.33$vc4f8/vblo=3,656.99 2006.175.07:49:51.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.07:49:51.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.07:49:51.33#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:51.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:51.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:51.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:51.33#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:49:51.33#ibcon#first serial, iclass 23, count 0 2006.175.07:49:51.33#ibcon#enter sib2, iclass 23, count 0 2006.175.07:49:51.33#ibcon#flushed, iclass 23, count 0 2006.175.07:49:51.33#ibcon#about to write, iclass 23, count 0 2006.175.07:49:51.33#ibcon#wrote, iclass 23, count 0 2006.175.07:49:51.33#ibcon#about to read 3, iclass 23, count 0 2006.175.07:49:51.35#ibcon#read 3, iclass 23, count 0 2006.175.07:49:51.35#ibcon#about to read 4, iclass 23, count 0 2006.175.07:49:51.35#ibcon#read 4, iclass 23, count 0 2006.175.07:49:51.35#ibcon#about to read 5, iclass 23, count 0 2006.175.07:49:51.35#ibcon#read 5, iclass 23, count 0 2006.175.07:49:51.35#ibcon#about to read 6, iclass 23, count 0 2006.175.07:49:51.35#ibcon#read 6, iclass 23, count 0 2006.175.07:49:51.35#ibcon#end of sib2, iclass 23, count 0 2006.175.07:49:51.35#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:49:51.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:49:51.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:49:51.35#ibcon#*before write, iclass 23, count 0 2006.175.07:49:51.35#ibcon#enter sib2, iclass 23, count 0 2006.175.07:49:51.35#ibcon#flushed, iclass 23, count 0 2006.175.07:49:51.35#ibcon#about to write, iclass 23, count 0 2006.175.07:49:51.35#ibcon#wrote, iclass 23, count 0 2006.175.07:49:51.35#ibcon#about to read 3, iclass 23, count 0 2006.175.07:49:51.39#ibcon#read 3, iclass 23, count 0 2006.175.07:49:51.39#ibcon#about to read 4, iclass 23, count 0 2006.175.07:49:51.39#ibcon#read 4, iclass 23, count 0 2006.175.07:49:51.39#ibcon#about to read 5, iclass 23, count 0 2006.175.07:49:51.39#ibcon#read 5, iclass 23, count 0 2006.175.07:49:51.39#ibcon#about to read 6, iclass 23, count 0 2006.175.07:49:51.39#ibcon#read 6, iclass 23, count 0 2006.175.07:49:51.39#ibcon#end of sib2, iclass 23, count 0 2006.175.07:49:51.39#ibcon#*after write, iclass 23, count 0 2006.175.07:49:51.39#ibcon#*before return 0, iclass 23, count 0 2006.175.07:49:51.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:51.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:49:51.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:49:51.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:49:51.39$vc4f8/vb=3,4 2006.175.07:49:51.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.07:49:51.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.07:49:51.39#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:51.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:51.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:51.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:51.45#ibcon#enter wrdev, iclass 25, count 2 2006.175.07:49:51.45#ibcon#first serial, iclass 25, count 2 2006.175.07:49:51.45#ibcon#enter sib2, iclass 25, count 2 2006.175.07:49:51.45#ibcon#flushed, iclass 25, count 2 2006.175.07:49:51.45#ibcon#about to write, iclass 25, count 2 2006.175.07:49:51.45#ibcon#wrote, iclass 25, count 2 2006.175.07:49:51.45#ibcon#about to read 3, iclass 25, count 2 2006.175.07:49:51.47#ibcon#read 3, iclass 25, count 2 2006.175.07:49:51.47#ibcon#about to read 4, iclass 25, count 2 2006.175.07:49:51.47#ibcon#read 4, iclass 25, count 2 2006.175.07:49:51.47#ibcon#about to read 5, iclass 25, count 2 2006.175.07:49:51.47#ibcon#read 5, iclass 25, count 2 2006.175.07:49:51.47#ibcon#about to read 6, iclass 25, count 2 2006.175.07:49:51.47#ibcon#read 6, iclass 25, count 2 2006.175.07:49:51.47#ibcon#end of sib2, iclass 25, count 2 2006.175.07:49:51.47#ibcon#*mode == 0, iclass 25, count 2 2006.175.07:49:51.47#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.07:49:51.47#ibcon#[27=AT03-04\r\n] 2006.175.07:49:51.47#ibcon#*before write, iclass 25, count 2 2006.175.07:49:51.47#ibcon#enter sib2, iclass 25, count 2 2006.175.07:49:51.47#ibcon#flushed, iclass 25, count 2 2006.175.07:49:51.47#ibcon#about to write, iclass 25, count 2 2006.175.07:49:51.47#ibcon#wrote, iclass 25, count 2 2006.175.07:49:51.47#ibcon#about to read 3, iclass 25, count 2 2006.175.07:49:51.50#ibcon#read 3, iclass 25, count 2 2006.175.07:49:51.50#ibcon#about to read 4, iclass 25, count 2 2006.175.07:49:51.50#ibcon#read 4, iclass 25, count 2 2006.175.07:49:51.50#ibcon#about to read 5, iclass 25, count 2 2006.175.07:49:51.50#ibcon#read 5, iclass 25, count 2 2006.175.07:49:51.50#ibcon#about to read 6, iclass 25, count 2 2006.175.07:49:51.50#ibcon#read 6, iclass 25, count 2 2006.175.07:49:51.50#ibcon#end of sib2, iclass 25, count 2 2006.175.07:49:51.50#ibcon#*after write, iclass 25, count 2 2006.175.07:49:51.50#ibcon#*before return 0, iclass 25, count 2 2006.175.07:49:51.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:51.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.07:49:51.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.07:49:51.50#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:51.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:51.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:51.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:51.62#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:49:51.62#ibcon#first serial, iclass 25, count 0 2006.175.07:49:51.62#ibcon#enter sib2, iclass 25, count 0 2006.175.07:49:51.62#ibcon#flushed, iclass 25, count 0 2006.175.07:49:51.62#ibcon#about to write, iclass 25, count 0 2006.175.07:49:51.62#ibcon#wrote, iclass 25, count 0 2006.175.07:49:51.62#ibcon#about to read 3, iclass 25, count 0 2006.175.07:49:51.64#ibcon#read 3, iclass 25, count 0 2006.175.07:49:51.64#ibcon#about to read 4, iclass 25, count 0 2006.175.07:49:51.64#ibcon#read 4, iclass 25, count 0 2006.175.07:49:51.64#ibcon#about to read 5, iclass 25, count 0 2006.175.07:49:51.64#ibcon#read 5, iclass 25, count 0 2006.175.07:49:51.64#ibcon#about to read 6, iclass 25, count 0 2006.175.07:49:51.64#ibcon#read 6, iclass 25, count 0 2006.175.07:49:51.64#ibcon#end of sib2, iclass 25, count 0 2006.175.07:49:51.64#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:49:51.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:49:51.64#ibcon#[27=USB\r\n] 2006.175.07:49:51.64#ibcon#*before write, iclass 25, count 0 2006.175.07:49:51.64#ibcon#enter sib2, iclass 25, count 0 2006.175.07:49:51.64#ibcon#flushed, iclass 25, count 0 2006.175.07:49:51.64#ibcon#about to write, iclass 25, count 0 2006.175.07:49:51.64#ibcon#wrote, iclass 25, count 0 2006.175.07:49:51.64#ibcon#about to read 3, iclass 25, count 0 2006.175.07:49:51.67#ibcon#read 3, iclass 25, count 0 2006.175.07:49:51.67#ibcon#about to read 4, iclass 25, count 0 2006.175.07:49:51.67#ibcon#read 4, iclass 25, count 0 2006.175.07:49:51.67#ibcon#about to read 5, iclass 25, count 0 2006.175.07:49:51.67#ibcon#read 5, iclass 25, count 0 2006.175.07:49:51.67#ibcon#about to read 6, iclass 25, count 0 2006.175.07:49:51.67#ibcon#read 6, iclass 25, count 0 2006.175.07:49:51.67#ibcon#end of sib2, iclass 25, count 0 2006.175.07:49:51.67#ibcon#*after write, iclass 25, count 0 2006.175.07:49:51.67#ibcon#*before return 0, iclass 25, count 0 2006.175.07:49:51.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:51.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.07:49:51.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:49:51.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:49:51.67$vc4f8/vblo=4,712.99 2006.175.07:49:51.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.07:49:51.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.07:49:51.67#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:51.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:49:51.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:49:51.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:49:51.67#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:49:51.67#ibcon#first serial, iclass 27, count 0 2006.175.07:49:51.67#ibcon#enter sib2, iclass 27, count 0 2006.175.07:49:51.67#ibcon#flushed, iclass 27, count 0 2006.175.07:49:51.67#ibcon#about to write, iclass 27, count 0 2006.175.07:49:51.67#ibcon#wrote, iclass 27, count 0 2006.175.07:49:51.67#ibcon#about to read 3, iclass 27, count 0 2006.175.07:49:51.69#ibcon#read 3, iclass 27, count 0 2006.175.07:49:51.69#ibcon#about to read 4, iclass 27, count 0 2006.175.07:49:51.69#ibcon#read 4, iclass 27, count 0 2006.175.07:49:51.69#ibcon#about to read 5, iclass 27, count 0 2006.175.07:49:51.69#ibcon#read 5, iclass 27, count 0 2006.175.07:49:51.69#ibcon#about to read 6, iclass 27, count 0 2006.175.07:49:51.69#ibcon#read 6, iclass 27, count 0 2006.175.07:49:51.69#ibcon#end of sib2, iclass 27, count 0 2006.175.07:49:51.69#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:49:51.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:49:51.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:49:51.69#ibcon#*before write, iclass 27, count 0 2006.175.07:49:51.69#ibcon#enter sib2, iclass 27, count 0 2006.175.07:49:51.69#ibcon#flushed, iclass 27, count 0 2006.175.07:49:51.69#ibcon#about to write, iclass 27, count 0 2006.175.07:49:51.69#ibcon#wrote, iclass 27, count 0 2006.175.07:49:51.69#ibcon#about to read 3, iclass 27, count 0 2006.175.07:49:51.73#ibcon#read 3, iclass 27, count 0 2006.175.07:49:51.73#ibcon#about to read 4, iclass 27, count 0 2006.175.07:49:51.73#ibcon#read 4, iclass 27, count 0 2006.175.07:49:51.73#ibcon#about to read 5, iclass 27, count 0 2006.175.07:49:51.73#ibcon#read 5, iclass 27, count 0 2006.175.07:49:51.73#ibcon#about to read 6, iclass 27, count 0 2006.175.07:49:51.73#ibcon#read 6, iclass 27, count 0 2006.175.07:49:51.73#ibcon#end of sib2, iclass 27, count 0 2006.175.07:49:51.73#ibcon#*after write, iclass 27, count 0 2006.175.07:49:51.73#ibcon#*before return 0, iclass 27, count 0 2006.175.07:49:51.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:49:51.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.07:49:51.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:49:51.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:49:51.73$vc4f8/vb=4,4 2006.175.07:49:51.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.175.07:49:51.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.175.07:49:51.73#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:51.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:49:51.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:49:51.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:49:51.79#ibcon#enter wrdev, iclass 29, count 2 2006.175.07:49:51.79#ibcon#first serial, iclass 29, count 2 2006.175.07:49:51.79#ibcon#enter sib2, iclass 29, count 2 2006.175.07:49:51.79#ibcon#flushed, iclass 29, count 2 2006.175.07:49:51.79#ibcon#about to write, iclass 29, count 2 2006.175.07:49:51.79#ibcon#wrote, iclass 29, count 2 2006.175.07:49:51.79#ibcon#about to read 3, iclass 29, count 2 2006.175.07:49:51.81#ibcon#read 3, iclass 29, count 2 2006.175.07:49:51.81#ibcon#about to read 4, iclass 29, count 2 2006.175.07:49:51.81#ibcon#read 4, iclass 29, count 2 2006.175.07:49:51.81#ibcon#about to read 5, iclass 29, count 2 2006.175.07:49:51.81#ibcon#read 5, iclass 29, count 2 2006.175.07:49:51.81#ibcon#about to read 6, iclass 29, count 2 2006.175.07:49:51.81#ibcon#read 6, iclass 29, count 2 2006.175.07:49:51.81#ibcon#end of sib2, iclass 29, count 2 2006.175.07:49:51.81#ibcon#*mode == 0, iclass 29, count 2 2006.175.07:49:51.81#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.175.07:49:51.81#ibcon#[27=AT04-04\r\n] 2006.175.07:49:51.81#ibcon#*before write, iclass 29, count 2 2006.175.07:49:51.81#ibcon#enter sib2, iclass 29, count 2 2006.175.07:49:51.81#ibcon#flushed, iclass 29, count 2 2006.175.07:49:51.81#ibcon#about to write, iclass 29, count 2 2006.175.07:49:51.81#ibcon#wrote, iclass 29, count 2 2006.175.07:49:51.81#ibcon#about to read 3, iclass 29, count 2 2006.175.07:49:51.84#ibcon#read 3, iclass 29, count 2 2006.175.07:49:51.84#ibcon#about to read 4, iclass 29, count 2 2006.175.07:49:51.84#ibcon#read 4, iclass 29, count 2 2006.175.07:49:51.84#ibcon#about to read 5, iclass 29, count 2 2006.175.07:49:51.84#ibcon#read 5, iclass 29, count 2 2006.175.07:49:51.84#ibcon#about to read 6, iclass 29, count 2 2006.175.07:49:51.84#ibcon#read 6, iclass 29, count 2 2006.175.07:49:51.84#ibcon#end of sib2, iclass 29, count 2 2006.175.07:49:51.84#ibcon#*after write, iclass 29, count 2 2006.175.07:49:51.84#ibcon#*before return 0, iclass 29, count 2 2006.175.07:49:51.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:49:51.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.175.07:49:51.84#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.175.07:49:51.84#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:51.84#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:49:51.96#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:49:51.96#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:49:51.96#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:49:51.96#ibcon#first serial, iclass 29, count 0 2006.175.07:49:51.96#ibcon#enter sib2, iclass 29, count 0 2006.175.07:49:51.96#ibcon#flushed, iclass 29, count 0 2006.175.07:49:51.96#ibcon#about to write, iclass 29, count 0 2006.175.07:49:51.96#ibcon#wrote, iclass 29, count 0 2006.175.07:49:51.96#ibcon#about to read 3, iclass 29, count 0 2006.175.07:49:51.98#ibcon#read 3, iclass 29, count 0 2006.175.07:49:51.98#ibcon#about to read 4, iclass 29, count 0 2006.175.07:49:51.98#ibcon#read 4, iclass 29, count 0 2006.175.07:49:51.98#ibcon#about to read 5, iclass 29, count 0 2006.175.07:49:51.98#ibcon#read 5, iclass 29, count 0 2006.175.07:49:51.98#ibcon#about to read 6, iclass 29, count 0 2006.175.07:49:51.98#ibcon#read 6, iclass 29, count 0 2006.175.07:49:51.98#ibcon#end of sib2, iclass 29, count 0 2006.175.07:49:51.98#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:49:51.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:49:51.98#ibcon#[27=USB\r\n] 2006.175.07:49:51.98#ibcon#*before write, iclass 29, count 0 2006.175.07:49:51.98#ibcon#enter sib2, iclass 29, count 0 2006.175.07:49:51.98#ibcon#flushed, iclass 29, count 0 2006.175.07:49:51.98#ibcon#about to write, iclass 29, count 0 2006.175.07:49:51.98#ibcon#wrote, iclass 29, count 0 2006.175.07:49:51.98#ibcon#about to read 3, iclass 29, count 0 2006.175.07:49:52.01#ibcon#read 3, iclass 29, count 0 2006.175.07:49:52.01#ibcon#about to read 4, iclass 29, count 0 2006.175.07:49:52.01#ibcon#read 4, iclass 29, count 0 2006.175.07:49:52.01#ibcon#about to read 5, iclass 29, count 0 2006.175.07:49:52.01#ibcon#read 5, iclass 29, count 0 2006.175.07:49:52.01#ibcon#about to read 6, iclass 29, count 0 2006.175.07:49:52.01#ibcon#read 6, iclass 29, count 0 2006.175.07:49:52.01#ibcon#end of sib2, iclass 29, count 0 2006.175.07:49:52.01#ibcon#*after write, iclass 29, count 0 2006.175.07:49:52.01#ibcon#*before return 0, iclass 29, count 0 2006.175.07:49:52.01#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:49:52.01#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.175.07:49:52.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:49:52.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:49:52.01$vc4f8/vblo=5,744.99 2006.175.07:49:52.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.07:49:52.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.07:49:52.01#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:52.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:49:52.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:49:52.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:49:52.01#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:49:52.01#ibcon#first serial, iclass 31, count 0 2006.175.07:49:52.01#ibcon#enter sib2, iclass 31, count 0 2006.175.07:49:52.01#ibcon#flushed, iclass 31, count 0 2006.175.07:49:52.01#ibcon#about to write, iclass 31, count 0 2006.175.07:49:52.01#ibcon#wrote, iclass 31, count 0 2006.175.07:49:52.01#ibcon#about to read 3, iclass 31, count 0 2006.175.07:49:52.03#ibcon#read 3, iclass 31, count 0 2006.175.07:49:52.03#ibcon#about to read 4, iclass 31, count 0 2006.175.07:49:52.03#ibcon#read 4, iclass 31, count 0 2006.175.07:49:52.03#ibcon#about to read 5, iclass 31, count 0 2006.175.07:49:52.03#ibcon#read 5, iclass 31, count 0 2006.175.07:49:52.03#ibcon#about to read 6, iclass 31, count 0 2006.175.07:49:52.03#ibcon#read 6, iclass 31, count 0 2006.175.07:49:52.03#ibcon#end of sib2, iclass 31, count 0 2006.175.07:49:52.03#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:49:52.03#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:49:52.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:49:52.03#ibcon#*before write, iclass 31, count 0 2006.175.07:49:52.03#ibcon#enter sib2, iclass 31, count 0 2006.175.07:49:52.03#ibcon#flushed, iclass 31, count 0 2006.175.07:49:52.03#ibcon#about to write, iclass 31, count 0 2006.175.07:49:52.03#ibcon#wrote, iclass 31, count 0 2006.175.07:49:52.03#ibcon#about to read 3, iclass 31, count 0 2006.175.07:49:52.07#ibcon#read 3, iclass 31, count 0 2006.175.07:49:52.07#ibcon#about to read 4, iclass 31, count 0 2006.175.07:49:52.07#ibcon#read 4, iclass 31, count 0 2006.175.07:49:52.07#ibcon#about to read 5, iclass 31, count 0 2006.175.07:49:52.07#ibcon#read 5, iclass 31, count 0 2006.175.07:49:52.07#ibcon#about to read 6, iclass 31, count 0 2006.175.07:49:52.07#ibcon#read 6, iclass 31, count 0 2006.175.07:49:52.07#ibcon#end of sib2, iclass 31, count 0 2006.175.07:49:52.07#ibcon#*after write, iclass 31, count 0 2006.175.07:49:52.07#ibcon#*before return 0, iclass 31, count 0 2006.175.07:49:52.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:49:52.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:49:52.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:49:52.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:49:52.07$vc4f8/vb=5,4 2006.175.07:49:52.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.07:49:52.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.07:49:52.07#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:52.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:49:52.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:49:52.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:49:52.13#ibcon#enter wrdev, iclass 33, count 2 2006.175.07:49:52.13#ibcon#first serial, iclass 33, count 2 2006.175.07:49:52.13#ibcon#enter sib2, iclass 33, count 2 2006.175.07:49:52.13#ibcon#flushed, iclass 33, count 2 2006.175.07:49:52.13#ibcon#about to write, iclass 33, count 2 2006.175.07:49:52.13#ibcon#wrote, iclass 33, count 2 2006.175.07:49:52.13#ibcon#about to read 3, iclass 33, count 2 2006.175.07:49:52.15#ibcon#read 3, iclass 33, count 2 2006.175.07:49:52.15#ibcon#about to read 4, iclass 33, count 2 2006.175.07:49:52.15#ibcon#read 4, iclass 33, count 2 2006.175.07:49:52.15#ibcon#about to read 5, iclass 33, count 2 2006.175.07:49:52.15#ibcon#read 5, iclass 33, count 2 2006.175.07:49:52.15#ibcon#about to read 6, iclass 33, count 2 2006.175.07:49:52.15#ibcon#read 6, iclass 33, count 2 2006.175.07:49:52.15#ibcon#end of sib2, iclass 33, count 2 2006.175.07:49:52.15#ibcon#*mode == 0, iclass 33, count 2 2006.175.07:49:52.15#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.07:49:52.15#ibcon#[27=AT05-04\r\n] 2006.175.07:49:52.15#ibcon#*before write, iclass 33, count 2 2006.175.07:49:52.15#ibcon#enter sib2, iclass 33, count 2 2006.175.07:49:52.15#ibcon#flushed, iclass 33, count 2 2006.175.07:49:52.15#ibcon#about to write, iclass 33, count 2 2006.175.07:49:52.15#ibcon#wrote, iclass 33, count 2 2006.175.07:49:52.15#ibcon#about to read 3, iclass 33, count 2 2006.175.07:49:52.18#ibcon#read 3, iclass 33, count 2 2006.175.07:49:52.18#ibcon#about to read 4, iclass 33, count 2 2006.175.07:49:52.18#ibcon#read 4, iclass 33, count 2 2006.175.07:49:52.18#ibcon#about to read 5, iclass 33, count 2 2006.175.07:49:52.18#ibcon#read 5, iclass 33, count 2 2006.175.07:49:52.18#ibcon#about to read 6, iclass 33, count 2 2006.175.07:49:52.18#ibcon#read 6, iclass 33, count 2 2006.175.07:49:52.18#ibcon#end of sib2, iclass 33, count 2 2006.175.07:49:52.18#ibcon#*after write, iclass 33, count 2 2006.175.07:49:52.18#ibcon#*before return 0, iclass 33, count 2 2006.175.07:49:52.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:49:52.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:49:52.18#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.07:49:52.18#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:52.18#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:49:52.30#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:49:52.30#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:49:52.30#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:49:52.30#ibcon#first serial, iclass 33, count 0 2006.175.07:49:52.30#ibcon#enter sib2, iclass 33, count 0 2006.175.07:49:52.30#ibcon#flushed, iclass 33, count 0 2006.175.07:49:52.30#ibcon#about to write, iclass 33, count 0 2006.175.07:49:52.30#ibcon#wrote, iclass 33, count 0 2006.175.07:49:52.30#ibcon#about to read 3, iclass 33, count 0 2006.175.07:49:52.32#ibcon#read 3, iclass 33, count 0 2006.175.07:49:52.32#ibcon#about to read 4, iclass 33, count 0 2006.175.07:49:52.32#ibcon#read 4, iclass 33, count 0 2006.175.07:49:52.32#ibcon#about to read 5, iclass 33, count 0 2006.175.07:49:52.32#ibcon#read 5, iclass 33, count 0 2006.175.07:49:52.32#ibcon#about to read 6, iclass 33, count 0 2006.175.07:49:52.32#ibcon#read 6, iclass 33, count 0 2006.175.07:49:52.32#ibcon#end of sib2, iclass 33, count 0 2006.175.07:49:52.32#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:49:52.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:49:52.32#ibcon#[27=USB\r\n] 2006.175.07:49:52.32#ibcon#*before write, iclass 33, count 0 2006.175.07:49:52.32#ibcon#enter sib2, iclass 33, count 0 2006.175.07:49:52.32#ibcon#flushed, iclass 33, count 0 2006.175.07:49:52.32#ibcon#about to write, iclass 33, count 0 2006.175.07:49:52.32#ibcon#wrote, iclass 33, count 0 2006.175.07:49:52.32#ibcon#about to read 3, iclass 33, count 0 2006.175.07:49:52.35#ibcon#read 3, iclass 33, count 0 2006.175.07:49:52.35#ibcon#about to read 4, iclass 33, count 0 2006.175.07:49:52.35#ibcon#read 4, iclass 33, count 0 2006.175.07:49:52.35#ibcon#about to read 5, iclass 33, count 0 2006.175.07:49:52.35#ibcon#read 5, iclass 33, count 0 2006.175.07:49:52.35#ibcon#about to read 6, iclass 33, count 0 2006.175.07:49:52.35#ibcon#read 6, iclass 33, count 0 2006.175.07:49:52.35#ibcon#end of sib2, iclass 33, count 0 2006.175.07:49:52.35#ibcon#*after write, iclass 33, count 0 2006.175.07:49:52.35#ibcon#*before return 0, iclass 33, count 0 2006.175.07:49:52.35#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:49:52.35#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:49:52.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:49:52.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:49:52.35$vc4f8/vblo=6,752.99 2006.175.07:49:52.35#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.07:49:52.35#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.07:49:52.35#ibcon#ireg 17 cls_cnt 0 2006.175.07:49:52.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:52.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:52.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:52.35#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:49:52.35#ibcon#first serial, iclass 35, count 0 2006.175.07:49:52.35#ibcon#enter sib2, iclass 35, count 0 2006.175.07:49:52.35#ibcon#flushed, iclass 35, count 0 2006.175.07:49:52.35#ibcon#about to write, iclass 35, count 0 2006.175.07:49:52.35#ibcon#wrote, iclass 35, count 0 2006.175.07:49:52.35#ibcon#about to read 3, iclass 35, count 0 2006.175.07:49:52.37#ibcon#read 3, iclass 35, count 0 2006.175.07:49:52.37#ibcon#about to read 4, iclass 35, count 0 2006.175.07:49:52.37#ibcon#read 4, iclass 35, count 0 2006.175.07:49:52.37#ibcon#about to read 5, iclass 35, count 0 2006.175.07:49:52.37#ibcon#read 5, iclass 35, count 0 2006.175.07:49:52.37#ibcon#about to read 6, iclass 35, count 0 2006.175.07:49:52.37#ibcon#read 6, iclass 35, count 0 2006.175.07:49:52.37#ibcon#end of sib2, iclass 35, count 0 2006.175.07:49:52.37#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:49:52.37#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:49:52.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:49:52.37#ibcon#*before write, iclass 35, count 0 2006.175.07:49:52.37#ibcon#enter sib2, iclass 35, count 0 2006.175.07:49:52.37#ibcon#flushed, iclass 35, count 0 2006.175.07:49:52.37#ibcon#about to write, iclass 35, count 0 2006.175.07:49:52.37#ibcon#wrote, iclass 35, count 0 2006.175.07:49:52.37#ibcon#about to read 3, iclass 35, count 0 2006.175.07:49:52.41#ibcon#read 3, iclass 35, count 0 2006.175.07:49:52.41#ibcon#about to read 4, iclass 35, count 0 2006.175.07:49:52.41#ibcon#read 4, iclass 35, count 0 2006.175.07:49:52.41#ibcon#about to read 5, iclass 35, count 0 2006.175.07:49:52.41#ibcon#read 5, iclass 35, count 0 2006.175.07:49:52.41#ibcon#about to read 6, iclass 35, count 0 2006.175.07:49:52.41#ibcon#read 6, iclass 35, count 0 2006.175.07:49:52.41#ibcon#end of sib2, iclass 35, count 0 2006.175.07:49:52.41#ibcon#*after write, iclass 35, count 0 2006.175.07:49:52.41#ibcon#*before return 0, iclass 35, count 0 2006.175.07:49:52.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:52.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:49:52.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:49:52.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:49:52.41$vc4f8/vb=6,4 2006.175.07:49:52.41#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.07:49:52.41#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.07:49:52.41#ibcon#ireg 11 cls_cnt 2 2006.175.07:49:52.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:52.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:52.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:52.47#ibcon#enter wrdev, iclass 37, count 2 2006.175.07:49:52.47#ibcon#first serial, iclass 37, count 2 2006.175.07:49:52.47#ibcon#enter sib2, iclass 37, count 2 2006.175.07:49:52.47#ibcon#flushed, iclass 37, count 2 2006.175.07:49:52.47#ibcon#about to write, iclass 37, count 2 2006.175.07:49:52.47#ibcon#wrote, iclass 37, count 2 2006.175.07:49:52.47#ibcon#about to read 3, iclass 37, count 2 2006.175.07:49:52.49#ibcon#read 3, iclass 37, count 2 2006.175.07:49:52.49#ibcon#about to read 4, iclass 37, count 2 2006.175.07:49:52.49#ibcon#read 4, iclass 37, count 2 2006.175.07:49:52.49#ibcon#about to read 5, iclass 37, count 2 2006.175.07:49:52.49#ibcon#read 5, iclass 37, count 2 2006.175.07:49:52.49#ibcon#about to read 6, iclass 37, count 2 2006.175.07:49:52.49#ibcon#read 6, iclass 37, count 2 2006.175.07:49:52.49#ibcon#end of sib2, iclass 37, count 2 2006.175.07:49:52.49#ibcon#*mode == 0, iclass 37, count 2 2006.175.07:49:52.49#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.07:49:52.49#ibcon#[27=AT06-04\r\n] 2006.175.07:49:52.49#ibcon#*before write, iclass 37, count 2 2006.175.07:49:52.49#ibcon#enter sib2, iclass 37, count 2 2006.175.07:49:52.49#ibcon#flushed, iclass 37, count 2 2006.175.07:49:52.49#ibcon#about to write, iclass 37, count 2 2006.175.07:49:52.49#ibcon#wrote, iclass 37, count 2 2006.175.07:49:52.49#ibcon#about to read 3, iclass 37, count 2 2006.175.07:49:52.52#ibcon#read 3, iclass 37, count 2 2006.175.07:49:52.52#ibcon#about to read 4, iclass 37, count 2 2006.175.07:49:52.52#ibcon#read 4, iclass 37, count 2 2006.175.07:49:52.52#ibcon#about to read 5, iclass 37, count 2 2006.175.07:49:52.52#ibcon#read 5, iclass 37, count 2 2006.175.07:49:52.52#ibcon#about to read 6, iclass 37, count 2 2006.175.07:49:52.52#ibcon#read 6, iclass 37, count 2 2006.175.07:49:52.52#ibcon#end of sib2, iclass 37, count 2 2006.175.07:49:52.52#ibcon#*after write, iclass 37, count 2 2006.175.07:49:52.52#ibcon#*before return 0, iclass 37, count 2 2006.175.07:49:52.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:52.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:49:52.52#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.07:49:52.52#ibcon#ireg 7 cls_cnt 0 2006.175.07:49:52.52#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:52.64#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:52.64#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:52.64#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:49:52.64#ibcon#first serial, iclass 37, count 0 2006.175.07:49:52.64#ibcon#enter sib2, iclass 37, count 0 2006.175.07:49:52.64#ibcon#flushed, iclass 37, count 0 2006.175.07:49:52.64#ibcon#about to write, iclass 37, count 0 2006.175.07:49:52.64#ibcon#wrote, iclass 37, count 0 2006.175.07:49:52.64#ibcon#about to read 3, iclass 37, count 0 2006.175.07:49:52.66#ibcon#read 3, iclass 37, count 0 2006.175.07:49:52.66#ibcon#about to read 4, iclass 37, count 0 2006.175.07:49:52.66#ibcon#read 4, iclass 37, count 0 2006.175.07:49:52.66#ibcon#about to read 5, iclass 37, count 0 2006.175.07:49:52.66#ibcon#read 5, iclass 37, count 0 2006.175.07:49:52.66#ibcon#about to read 6, iclass 37, count 0 2006.175.07:49:52.66#ibcon#read 6, iclass 37, count 0 2006.175.07:49:52.66#ibcon#end of sib2, iclass 37, count 0 2006.175.07:49:52.66#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:49:52.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:49:52.66#ibcon#[27=USB\r\n] 2006.175.07:49:52.66#ibcon#*before write, iclass 37, count 0 2006.175.07:49:52.66#ibcon#enter sib2, iclass 37, count 0 2006.175.07:49:52.66#ibcon#flushed, iclass 37, count 0 2006.175.07:49:52.66#ibcon#about to write, iclass 37, count 0 2006.175.07:49:52.66#ibcon#wrote, iclass 37, count 0 2006.175.07:49:52.66#ibcon#about to read 3, iclass 37, count 0 2006.175.07:49:52.69#ibcon#read 3, iclass 37, count 0 2006.175.07:49:52.69#ibcon#about to read 4, iclass 37, count 0 2006.175.07:49:52.69#ibcon#read 4, iclass 37, count 0 2006.175.07:49:52.69#ibcon#about to read 5, iclass 37, count 0 2006.175.07:49:52.69#ibcon#read 5, iclass 37, count 0 2006.175.07:49:52.69#ibcon#about to read 6, iclass 37, count 0 2006.175.07:49:52.69#ibcon#read 6, iclass 37, count 0 2006.175.07:49:52.69#ibcon#end of sib2, iclass 37, count 0 2006.175.07:49:52.69#ibcon#*after write, iclass 37, count 0 2006.175.07:49:52.69#ibcon#*before return 0, iclass 37, count 0 2006.175.07:49:52.69#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:52.69#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:49:52.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:49:52.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:49:52.69$vc4f8/vabw=wide 2006.175.07:49:52.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.07:49:52.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.07:49:52.69#ibcon#ireg 8 cls_cnt 0 2006.175.07:49:52.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:52.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:52.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:52.69#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:49:52.69#ibcon#first serial, iclass 39, count 0 2006.175.07:49:52.69#ibcon#enter sib2, iclass 39, count 0 2006.175.07:49:52.69#ibcon#flushed, iclass 39, count 0 2006.175.07:49:52.69#ibcon#about to write, iclass 39, count 0 2006.175.07:49:52.69#ibcon#wrote, iclass 39, count 0 2006.175.07:49:52.69#ibcon#about to read 3, iclass 39, count 0 2006.175.07:49:52.71#ibcon#read 3, iclass 39, count 0 2006.175.07:49:52.71#ibcon#about to read 4, iclass 39, count 0 2006.175.07:49:52.71#ibcon#read 4, iclass 39, count 0 2006.175.07:49:52.71#ibcon#about to read 5, iclass 39, count 0 2006.175.07:49:52.71#ibcon#read 5, iclass 39, count 0 2006.175.07:49:52.71#ibcon#about to read 6, iclass 39, count 0 2006.175.07:49:52.71#ibcon#read 6, iclass 39, count 0 2006.175.07:49:52.71#ibcon#end of sib2, iclass 39, count 0 2006.175.07:49:52.71#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:49:52.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:49:52.71#ibcon#[25=BW32\r\n] 2006.175.07:49:52.71#ibcon#*before write, iclass 39, count 0 2006.175.07:49:52.71#ibcon#enter sib2, iclass 39, count 0 2006.175.07:49:52.71#ibcon#flushed, iclass 39, count 0 2006.175.07:49:52.71#ibcon#about to write, iclass 39, count 0 2006.175.07:49:52.71#ibcon#wrote, iclass 39, count 0 2006.175.07:49:52.71#ibcon#about to read 3, iclass 39, count 0 2006.175.07:49:52.74#ibcon#read 3, iclass 39, count 0 2006.175.07:49:52.74#ibcon#about to read 4, iclass 39, count 0 2006.175.07:49:52.74#ibcon#read 4, iclass 39, count 0 2006.175.07:49:52.74#ibcon#about to read 5, iclass 39, count 0 2006.175.07:49:52.74#ibcon#read 5, iclass 39, count 0 2006.175.07:49:52.74#ibcon#about to read 6, iclass 39, count 0 2006.175.07:49:52.74#ibcon#read 6, iclass 39, count 0 2006.175.07:49:52.74#ibcon#end of sib2, iclass 39, count 0 2006.175.07:49:52.74#ibcon#*after write, iclass 39, count 0 2006.175.07:49:52.74#ibcon#*before return 0, iclass 39, count 0 2006.175.07:49:52.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:52.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:49:52.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:49:52.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:49:52.74$vc4f8/vbbw=wide 2006.175.07:49:52.74#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.07:49:52.74#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.07:49:52.74#ibcon#ireg 8 cls_cnt 0 2006.175.07:49:52.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:49:52.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:49:52.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:49:52.81#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:49:52.81#ibcon#first serial, iclass 3, count 0 2006.175.07:49:52.81#ibcon#enter sib2, iclass 3, count 0 2006.175.07:49:52.81#ibcon#flushed, iclass 3, count 0 2006.175.07:49:52.81#ibcon#about to write, iclass 3, count 0 2006.175.07:49:52.81#ibcon#wrote, iclass 3, count 0 2006.175.07:49:52.81#ibcon#about to read 3, iclass 3, count 0 2006.175.07:49:52.83#ibcon#read 3, iclass 3, count 0 2006.175.07:49:52.83#ibcon#about to read 4, iclass 3, count 0 2006.175.07:49:52.83#ibcon#read 4, iclass 3, count 0 2006.175.07:49:52.83#ibcon#about to read 5, iclass 3, count 0 2006.175.07:49:52.83#ibcon#read 5, iclass 3, count 0 2006.175.07:49:52.83#ibcon#about to read 6, iclass 3, count 0 2006.175.07:49:52.83#ibcon#read 6, iclass 3, count 0 2006.175.07:49:52.83#ibcon#end of sib2, iclass 3, count 0 2006.175.07:49:52.83#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:49:52.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:49:52.83#ibcon#[27=BW32\r\n] 2006.175.07:49:52.83#ibcon#*before write, iclass 3, count 0 2006.175.07:49:52.83#ibcon#enter sib2, iclass 3, count 0 2006.175.07:49:52.83#ibcon#flushed, iclass 3, count 0 2006.175.07:49:52.83#ibcon#about to write, iclass 3, count 0 2006.175.07:49:52.83#ibcon#wrote, iclass 3, count 0 2006.175.07:49:52.83#ibcon#about to read 3, iclass 3, count 0 2006.175.07:49:52.86#ibcon#read 3, iclass 3, count 0 2006.175.07:49:52.86#ibcon#about to read 4, iclass 3, count 0 2006.175.07:49:52.86#ibcon#read 4, iclass 3, count 0 2006.175.07:49:52.86#ibcon#about to read 5, iclass 3, count 0 2006.175.07:49:52.86#ibcon#read 5, iclass 3, count 0 2006.175.07:49:52.86#ibcon#about to read 6, iclass 3, count 0 2006.175.07:49:52.86#ibcon#read 6, iclass 3, count 0 2006.175.07:49:52.86#ibcon#end of sib2, iclass 3, count 0 2006.175.07:49:52.86#ibcon#*after write, iclass 3, count 0 2006.175.07:49:52.86#ibcon#*before return 0, iclass 3, count 0 2006.175.07:49:52.86#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:49:52.86#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:49:52.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:49:52.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:49:52.86$4f8m12a/ifd4f 2006.175.07:49:52.86$ifd4f/lo= 2006.175.07:49:52.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:49:52.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:49:52.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:49:52.86$ifd4f/patch= 2006.175.07:49:52.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:49:52.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:49:52.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:49:52.86$4f8m12a/"form=m,16.000,1:2 2006.175.07:49:52.86$4f8m12a/"tpicd 2006.175.07:49:52.86$4f8m12a/echo=off 2006.175.07:49:52.86$4f8m12a/xlog=off 2006.175.07:49:52.86:!2006.175.07:50:20 2006.175.07:50:04.13#trakl#Source acquired 2006.175.07:50:05.13#flagr#flagr/antenna,acquired 2006.175.07:50:20.00:preob 2006.175.07:50:21.13/onsource/TRACKING 2006.175.07:50:21.13:!2006.175.07:50:30 2006.175.07:50:30.00:data_valid=on 2006.175.07:50:30.00:midob 2006.175.07:50:30.13/onsource/TRACKING 2006.175.07:50:30.13/wx/25.89,1007.3,69 2006.175.07:50:30.28/cable/+6.4779E-03 2006.175.07:50:31.37/va/01,08,usb,yes,29,31 2006.175.07:50:31.37/va/02,07,usb,yes,29,30 2006.175.07:50:31.37/va/03,06,usb,yes,31,31 2006.175.07:50:31.37/va/04,07,usb,yes,30,32 2006.175.07:50:31.37/va/05,07,usb,yes,30,32 2006.175.07:50:31.37/va/06,06,usb,yes,29,29 2006.175.07:50:31.37/va/07,06,usb,yes,30,30 2006.175.07:50:31.37/va/08,06,usb,yes,32,31 2006.175.07:50:31.60/valo/01,532.99,yes,locked 2006.175.07:50:31.60/valo/02,572.99,yes,locked 2006.175.07:50:31.60/valo/03,672.99,yes,locked 2006.175.07:50:31.60/valo/04,832.99,yes,locked 2006.175.07:50:31.60/valo/05,652.99,yes,locked 2006.175.07:50:31.60/valo/06,772.99,yes,locked 2006.175.07:50:31.60/valo/07,832.99,yes,locked 2006.175.07:50:31.60/valo/08,852.99,yes,locked 2006.175.07:50:32.69/vb/01,04,usb,yes,29,28 2006.175.07:50:32.69/vb/02,04,usb,yes,31,32 2006.175.07:50:32.69/vb/03,04,usb,yes,27,31 2006.175.07:50:32.69/vb/04,04,usb,yes,28,28 2006.175.07:50:32.69/vb/05,04,usb,yes,27,31 2006.175.07:50:32.69/vb/06,04,usb,yes,28,31 2006.175.07:50:32.69/vb/07,04,usb,yes,30,30 2006.175.07:50:32.69/vb/08,04,usb,yes,27,31 2006.175.07:50:32.93/vblo/01,632.99,yes,locked 2006.175.07:50:32.93/vblo/02,640.99,yes,locked 2006.175.07:50:32.93/vblo/03,656.99,yes,locked 2006.175.07:50:32.93/vblo/04,712.99,yes,locked 2006.175.07:50:32.93/vblo/05,744.99,yes,locked 2006.175.07:50:32.93/vblo/06,752.99,yes,locked 2006.175.07:50:32.93/vblo/07,734.99,yes,locked 2006.175.07:50:32.93/vblo/08,744.99,yes,locked 2006.175.07:50:33.08/vabw/8 2006.175.07:50:33.23/vbbw/8 2006.175.07:50:33.44/xfe/off,on,15.2 2006.175.07:50:33.83/ifatt/23,28,28,28 2006.175.07:50:34.08/fmout-gps/S +3.75E-07 2006.175.07:50:34.12:!2006.175.07:51:30 2006.175.07:51:30.00:data_valid=off 2006.175.07:51:30.00:postob 2006.175.07:51:30.09/cable/+6.4766E-03 2006.175.07:51:30.09/wx/25.88,1007.3,68 2006.175.07:51:31.08/fmout-gps/S +3.75E-07 2006.175.07:51:31.08:scan_name=175-0752,k06175,60 2006.175.07:51:31.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.175.07:51:31.13#flagr#flagr/antenna,new-source 2006.175.07:51:32.13:checkk5 2006.175.07:51:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:51:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:51:33.55/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:51:33.93/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:51:34.30/chk_obsdata//k5ts1/T1750750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:51:34.67/chk_obsdata//k5ts2/T1750750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:51:35.05/chk_obsdata//k5ts3/T1750750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:51:35.42/chk_obsdata//k5ts4/T1750750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:51:36.11/k5log//k5ts1_log_newline 2006.175.07:51:36.80/k5log//k5ts2_log_newline 2006.175.07:51:37.49/k5log//k5ts3_log_newline 2006.175.07:51:38.19/k5log//k5ts4_log_newline 2006.175.07:51:38.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:51:38.21:4f8m12a=1 2006.175.07:51:38.22$4f8m12a/echo=on 2006.175.07:51:38.22$4f8m12a/pcalon 2006.175.07:51:38.22$pcalon/"no phase cal control is implemented here 2006.175.07:51:38.22$4f8m12a/"tpicd=stop 2006.175.07:51:38.22$4f8m12a/vc4f8 2006.175.07:51:38.22$vc4f8/valo=1,532.99 2006.175.07:51:38.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.07:51:38.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.07:51:38.22#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:38.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:51:38.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:51:38.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:51:38.22#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:51:38.22#ibcon#first serial, iclass 12, count 0 2006.175.07:51:38.22#ibcon#enter sib2, iclass 12, count 0 2006.175.07:51:38.22#ibcon#flushed, iclass 12, count 0 2006.175.07:51:38.22#ibcon#about to write, iclass 12, count 0 2006.175.07:51:38.22#ibcon#wrote, iclass 12, count 0 2006.175.07:51:38.22#ibcon#about to read 3, iclass 12, count 0 2006.175.07:51:38.26#ibcon#read 3, iclass 12, count 0 2006.175.07:51:38.26#ibcon#about to read 4, iclass 12, count 0 2006.175.07:51:38.26#ibcon#read 4, iclass 12, count 0 2006.175.07:51:38.26#ibcon#about to read 5, iclass 12, count 0 2006.175.07:51:38.26#ibcon#read 5, iclass 12, count 0 2006.175.07:51:38.26#ibcon#about to read 6, iclass 12, count 0 2006.175.07:51:38.26#ibcon#read 6, iclass 12, count 0 2006.175.07:51:38.26#ibcon#end of sib2, iclass 12, count 0 2006.175.07:51:38.26#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:51:38.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:51:38.26#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:51:38.26#ibcon#*before write, iclass 12, count 0 2006.175.07:51:38.26#ibcon#enter sib2, iclass 12, count 0 2006.175.07:51:38.26#ibcon#flushed, iclass 12, count 0 2006.175.07:51:38.26#ibcon#about to write, iclass 12, count 0 2006.175.07:51:38.26#ibcon#wrote, iclass 12, count 0 2006.175.07:51:38.26#ibcon#about to read 3, iclass 12, count 0 2006.175.07:51:38.31#ibcon#read 3, iclass 12, count 0 2006.175.07:51:38.31#ibcon#about to read 4, iclass 12, count 0 2006.175.07:51:38.31#ibcon#read 4, iclass 12, count 0 2006.175.07:51:38.31#ibcon#about to read 5, iclass 12, count 0 2006.175.07:51:38.31#ibcon#read 5, iclass 12, count 0 2006.175.07:51:38.31#ibcon#about to read 6, iclass 12, count 0 2006.175.07:51:38.31#ibcon#read 6, iclass 12, count 0 2006.175.07:51:38.31#ibcon#end of sib2, iclass 12, count 0 2006.175.07:51:38.31#ibcon#*after write, iclass 12, count 0 2006.175.07:51:38.31#ibcon#*before return 0, iclass 12, count 0 2006.175.07:51:38.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:51:38.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.07:51:38.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:51:38.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:51:38.31$vc4f8/va=1,8 2006.175.07:51:38.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.07:51:38.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.07:51:38.31#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:38.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:38.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:38.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:38.31#ibcon#enter wrdev, iclass 14, count 2 2006.175.07:51:38.31#ibcon#first serial, iclass 14, count 2 2006.175.07:51:38.31#ibcon#enter sib2, iclass 14, count 2 2006.175.07:51:38.31#ibcon#flushed, iclass 14, count 2 2006.175.07:51:38.31#ibcon#about to write, iclass 14, count 2 2006.175.07:51:38.31#ibcon#wrote, iclass 14, count 2 2006.175.07:51:38.31#ibcon#about to read 3, iclass 14, count 2 2006.175.07:51:38.33#ibcon#read 3, iclass 14, count 2 2006.175.07:51:38.33#ibcon#about to read 4, iclass 14, count 2 2006.175.07:51:38.33#ibcon#read 4, iclass 14, count 2 2006.175.07:51:38.33#ibcon#about to read 5, iclass 14, count 2 2006.175.07:51:38.33#ibcon#read 5, iclass 14, count 2 2006.175.07:51:38.33#ibcon#about to read 6, iclass 14, count 2 2006.175.07:51:38.33#ibcon#read 6, iclass 14, count 2 2006.175.07:51:38.33#ibcon#end of sib2, iclass 14, count 2 2006.175.07:51:38.33#ibcon#*mode == 0, iclass 14, count 2 2006.175.07:51:38.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.07:51:38.33#ibcon#[25=AT01-08\r\n] 2006.175.07:51:38.33#ibcon#*before write, iclass 14, count 2 2006.175.07:51:38.33#ibcon#enter sib2, iclass 14, count 2 2006.175.07:51:38.33#ibcon#flushed, iclass 14, count 2 2006.175.07:51:38.33#ibcon#about to write, iclass 14, count 2 2006.175.07:51:38.33#ibcon#wrote, iclass 14, count 2 2006.175.07:51:38.33#ibcon#about to read 3, iclass 14, count 2 2006.175.07:51:38.37#ibcon#read 3, iclass 14, count 2 2006.175.07:51:38.37#ibcon#about to read 4, iclass 14, count 2 2006.175.07:51:38.37#ibcon#read 4, iclass 14, count 2 2006.175.07:51:38.37#ibcon#about to read 5, iclass 14, count 2 2006.175.07:51:38.37#ibcon#read 5, iclass 14, count 2 2006.175.07:51:38.37#ibcon#about to read 6, iclass 14, count 2 2006.175.07:51:38.37#ibcon#read 6, iclass 14, count 2 2006.175.07:51:38.37#ibcon#end of sib2, iclass 14, count 2 2006.175.07:51:38.37#ibcon#*after write, iclass 14, count 2 2006.175.07:51:38.37#ibcon#*before return 0, iclass 14, count 2 2006.175.07:51:38.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:38.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:38.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.07:51:38.37#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:38.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:38.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:38.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:38.49#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:51:38.49#ibcon#first serial, iclass 14, count 0 2006.175.07:51:38.49#ibcon#enter sib2, iclass 14, count 0 2006.175.07:51:38.49#ibcon#flushed, iclass 14, count 0 2006.175.07:51:38.49#ibcon#about to write, iclass 14, count 0 2006.175.07:51:38.49#ibcon#wrote, iclass 14, count 0 2006.175.07:51:38.49#ibcon#about to read 3, iclass 14, count 0 2006.175.07:51:38.51#ibcon#read 3, iclass 14, count 0 2006.175.07:51:38.51#ibcon#about to read 4, iclass 14, count 0 2006.175.07:51:38.51#ibcon#read 4, iclass 14, count 0 2006.175.07:51:38.51#ibcon#about to read 5, iclass 14, count 0 2006.175.07:51:38.51#ibcon#read 5, iclass 14, count 0 2006.175.07:51:38.51#ibcon#about to read 6, iclass 14, count 0 2006.175.07:51:38.51#ibcon#read 6, iclass 14, count 0 2006.175.07:51:38.51#ibcon#end of sib2, iclass 14, count 0 2006.175.07:51:38.51#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:51:38.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:51:38.51#ibcon#[25=USB\r\n] 2006.175.07:51:38.51#ibcon#*before write, iclass 14, count 0 2006.175.07:51:38.51#ibcon#enter sib2, iclass 14, count 0 2006.175.07:51:38.51#ibcon#flushed, iclass 14, count 0 2006.175.07:51:38.51#ibcon#about to write, iclass 14, count 0 2006.175.07:51:38.51#ibcon#wrote, iclass 14, count 0 2006.175.07:51:38.51#ibcon#about to read 3, iclass 14, count 0 2006.175.07:51:38.54#ibcon#read 3, iclass 14, count 0 2006.175.07:51:38.54#ibcon#about to read 4, iclass 14, count 0 2006.175.07:51:38.54#ibcon#read 4, iclass 14, count 0 2006.175.07:51:38.54#ibcon#about to read 5, iclass 14, count 0 2006.175.07:51:38.54#ibcon#read 5, iclass 14, count 0 2006.175.07:51:38.54#ibcon#about to read 6, iclass 14, count 0 2006.175.07:51:38.54#ibcon#read 6, iclass 14, count 0 2006.175.07:51:38.54#ibcon#end of sib2, iclass 14, count 0 2006.175.07:51:38.54#ibcon#*after write, iclass 14, count 0 2006.175.07:51:38.54#ibcon#*before return 0, iclass 14, count 0 2006.175.07:51:38.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:38.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:38.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:51:38.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:51:38.54$vc4f8/valo=2,572.99 2006.175.07:51:38.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.07:51:38.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.07:51:38.54#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:38.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:38.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:38.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:38.54#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:51:38.54#ibcon#first serial, iclass 16, count 0 2006.175.07:51:38.54#ibcon#enter sib2, iclass 16, count 0 2006.175.07:51:38.54#ibcon#flushed, iclass 16, count 0 2006.175.07:51:38.54#ibcon#about to write, iclass 16, count 0 2006.175.07:51:38.54#ibcon#wrote, iclass 16, count 0 2006.175.07:51:38.54#ibcon#about to read 3, iclass 16, count 0 2006.175.07:51:38.56#ibcon#read 3, iclass 16, count 0 2006.175.07:51:38.56#ibcon#about to read 4, iclass 16, count 0 2006.175.07:51:38.56#ibcon#read 4, iclass 16, count 0 2006.175.07:51:38.56#ibcon#about to read 5, iclass 16, count 0 2006.175.07:51:38.56#ibcon#read 5, iclass 16, count 0 2006.175.07:51:38.56#ibcon#about to read 6, iclass 16, count 0 2006.175.07:51:38.56#ibcon#read 6, iclass 16, count 0 2006.175.07:51:38.56#ibcon#end of sib2, iclass 16, count 0 2006.175.07:51:38.56#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:51:38.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:51:38.56#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:51:38.56#ibcon#*before write, iclass 16, count 0 2006.175.07:51:38.56#ibcon#enter sib2, iclass 16, count 0 2006.175.07:51:38.56#ibcon#flushed, iclass 16, count 0 2006.175.07:51:38.56#ibcon#about to write, iclass 16, count 0 2006.175.07:51:38.56#ibcon#wrote, iclass 16, count 0 2006.175.07:51:38.56#ibcon#about to read 3, iclass 16, count 0 2006.175.07:51:38.60#ibcon#read 3, iclass 16, count 0 2006.175.07:51:38.60#ibcon#about to read 4, iclass 16, count 0 2006.175.07:51:38.60#ibcon#read 4, iclass 16, count 0 2006.175.07:51:38.60#ibcon#about to read 5, iclass 16, count 0 2006.175.07:51:38.60#ibcon#read 5, iclass 16, count 0 2006.175.07:51:38.60#ibcon#about to read 6, iclass 16, count 0 2006.175.07:51:38.60#ibcon#read 6, iclass 16, count 0 2006.175.07:51:38.60#ibcon#end of sib2, iclass 16, count 0 2006.175.07:51:38.60#ibcon#*after write, iclass 16, count 0 2006.175.07:51:38.60#ibcon#*before return 0, iclass 16, count 0 2006.175.07:51:38.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:38.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:38.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:51:38.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:51:38.60$vc4f8/va=2,7 2006.175.07:51:38.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.07:51:38.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.07:51:38.60#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:38.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:38.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:38.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:38.66#ibcon#enter wrdev, iclass 18, count 2 2006.175.07:51:38.66#ibcon#first serial, iclass 18, count 2 2006.175.07:51:38.66#ibcon#enter sib2, iclass 18, count 2 2006.175.07:51:38.66#ibcon#flushed, iclass 18, count 2 2006.175.07:51:38.66#ibcon#about to write, iclass 18, count 2 2006.175.07:51:38.66#ibcon#wrote, iclass 18, count 2 2006.175.07:51:38.66#ibcon#about to read 3, iclass 18, count 2 2006.175.07:51:38.68#ibcon#read 3, iclass 18, count 2 2006.175.07:51:38.68#ibcon#about to read 4, iclass 18, count 2 2006.175.07:51:38.68#ibcon#read 4, iclass 18, count 2 2006.175.07:51:38.68#ibcon#about to read 5, iclass 18, count 2 2006.175.07:51:38.68#ibcon#read 5, iclass 18, count 2 2006.175.07:51:38.68#ibcon#about to read 6, iclass 18, count 2 2006.175.07:51:38.68#ibcon#read 6, iclass 18, count 2 2006.175.07:51:38.68#ibcon#end of sib2, iclass 18, count 2 2006.175.07:51:38.68#ibcon#*mode == 0, iclass 18, count 2 2006.175.07:51:38.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.07:51:38.68#ibcon#[25=AT02-07\r\n] 2006.175.07:51:38.68#ibcon#*before write, iclass 18, count 2 2006.175.07:51:38.68#ibcon#enter sib2, iclass 18, count 2 2006.175.07:51:38.68#ibcon#flushed, iclass 18, count 2 2006.175.07:51:38.68#ibcon#about to write, iclass 18, count 2 2006.175.07:51:38.68#ibcon#wrote, iclass 18, count 2 2006.175.07:51:38.68#ibcon#about to read 3, iclass 18, count 2 2006.175.07:51:38.71#ibcon#read 3, iclass 18, count 2 2006.175.07:51:38.71#ibcon#about to read 4, iclass 18, count 2 2006.175.07:51:38.71#ibcon#read 4, iclass 18, count 2 2006.175.07:51:38.71#ibcon#about to read 5, iclass 18, count 2 2006.175.07:51:38.71#ibcon#read 5, iclass 18, count 2 2006.175.07:51:38.71#ibcon#about to read 6, iclass 18, count 2 2006.175.07:51:38.71#ibcon#read 6, iclass 18, count 2 2006.175.07:51:38.71#ibcon#end of sib2, iclass 18, count 2 2006.175.07:51:38.71#ibcon#*after write, iclass 18, count 2 2006.175.07:51:38.71#ibcon#*before return 0, iclass 18, count 2 2006.175.07:51:38.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:38.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:38.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.07:51:38.71#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:38.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:38.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:38.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:38.83#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:51:38.83#ibcon#first serial, iclass 18, count 0 2006.175.07:51:38.83#ibcon#enter sib2, iclass 18, count 0 2006.175.07:51:38.83#ibcon#flushed, iclass 18, count 0 2006.175.07:51:38.83#ibcon#about to write, iclass 18, count 0 2006.175.07:51:38.83#ibcon#wrote, iclass 18, count 0 2006.175.07:51:38.83#ibcon#about to read 3, iclass 18, count 0 2006.175.07:51:38.85#ibcon#read 3, iclass 18, count 0 2006.175.07:51:38.85#ibcon#about to read 4, iclass 18, count 0 2006.175.07:51:38.85#ibcon#read 4, iclass 18, count 0 2006.175.07:51:38.85#ibcon#about to read 5, iclass 18, count 0 2006.175.07:51:38.85#ibcon#read 5, iclass 18, count 0 2006.175.07:51:38.85#ibcon#about to read 6, iclass 18, count 0 2006.175.07:51:38.85#ibcon#read 6, iclass 18, count 0 2006.175.07:51:38.85#ibcon#end of sib2, iclass 18, count 0 2006.175.07:51:38.85#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:51:38.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:51:38.85#ibcon#[25=USB\r\n] 2006.175.07:51:38.85#ibcon#*before write, iclass 18, count 0 2006.175.07:51:38.85#ibcon#enter sib2, iclass 18, count 0 2006.175.07:51:38.85#ibcon#flushed, iclass 18, count 0 2006.175.07:51:38.85#ibcon#about to write, iclass 18, count 0 2006.175.07:51:38.85#ibcon#wrote, iclass 18, count 0 2006.175.07:51:38.85#ibcon#about to read 3, iclass 18, count 0 2006.175.07:51:38.88#ibcon#read 3, iclass 18, count 0 2006.175.07:51:38.88#ibcon#about to read 4, iclass 18, count 0 2006.175.07:51:38.88#ibcon#read 4, iclass 18, count 0 2006.175.07:51:38.88#ibcon#about to read 5, iclass 18, count 0 2006.175.07:51:38.88#ibcon#read 5, iclass 18, count 0 2006.175.07:51:38.88#ibcon#about to read 6, iclass 18, count 0 2006.175.07:51:38.88#ibcon#read 6, iclass 18, count 0 2006.175.07:51:38.88#ibcon#end of sib2, iclass 18, count 0 2006.175.07:51:38.88#ibcon#*after write, iclass 18, count 0 2006.175.07:51:38.88#ibcon#*before return 0, iclass 18, count 0 2006.175.07:51:38.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:38.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:38.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:51:38.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:51:38.88$vc4f8/valo=3,672.99 2006.175.07:51:38.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.07:51:38.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.07:51:38.88#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:38.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:38.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:38.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:38.88#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:51:38.88#ibcon#first serial, iclass 20, count 0 2006.175.07:51:38.88#ibcon#enter sib2, iclass 20, count 0 2006.175.07:51:38.88#ibcon#flushed, iclass 20, count 0 2006.175.07:51:38.88#ibcon#about to write, iclass 20, count 0 2006.175.07:51:38.88#ibcon#wrote, iclass 20, count 0 2006.175.07:51:38.88#ibcon#about to read 3, iclass 20, count 0 2006.175.07:51:38.90#ibcon#read 3, iclass 20, count 0 2006.175.07:51:38.90#ibcon#about to read 4, iclass 20, count 0 2006.175.07:51:38.90#ibcon#read 4, iclass 20, count 0 2006.175.07:51:38.90#ibcon#about to read 5, iclass 20, count 0 2006.175.07:51:38.90#ibcon#read 5, iclass 20, count 0 2006.175.07:51:38.90#ibcon#about to read 6, iclass 20, count 0 2006.175.07:51:38.90#ibcon#read 6, iclass 20, count 0 2006.175.07:51:38.90#ibcon#end of sib2, iclass 20, count 0 2006.175.07:51:38.90#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:51:38.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:51:38.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:51:38.90#ibcon#*before write, iclass 20, count 0 2006.175.07:51:38.90#ibcon#enter sib2, iclass 20, count 0 2006.175.07:51:38.90#ibcon#flushed, iclass 20, count 0 2006.175.07:51:38.90#ibcon#about to write, iclass 20, count 0 2006.175.07:51:38.90#ibcon#wrote, iclass 20, count 0 2006.175.07:51:38.90#ibcon#about to read 3, iclass 20, count 0 2006.175.07:51:38.94#ibcon#read 3, iclass 20, count 0 2006.175.07:51:38.94#ibcon#about to read 4, iclass 20, count 0 2006.175.07:51:38.94#ibcon#read 4, iclass 20, count 0 2006.175.07:51:38.94#ibcon#about to read 5, iclass 20, count 0 2006.175.07:51:38.94#ibcon#read 5, iclass 20, count 0 2006.175.07:51:38.94#ibcon#about to read 6, iclass 20, count 0 2006.175.07:51:38.94#ibcon#read 6, iclass 20, count 0 2006.175.07:51:38.94#ibcon#end of sib2, iclass 20, count 0 2006.175.07:51:38.94#ibcon#*after write, iclass 20, count 0 2006.175.07:51:38.94#ibcon#*before return 0, iclass 20, count 0 2006.175.07:51:38.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:38.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:38.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:51:38.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:51:38.94$vc4f8/va=3,6 2006.175.07:51:38.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.07:51:38.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.07:51:38.94#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:38.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:39.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:39.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:39.00#ibcon#enter wrdev, iclass 22, count 2 2006.175.07:51:39.00#ibcon#first serial, iclass 22, count 2 2006.175.07:51:39.00#ibcon#enter sib2, iclass 22, count 2 2006.175.07:51:39.00#ibcon#flushed, iclass 22, count 2 2006.175.07:51:39.00#ibcon#about to write, iclass 22, count 2 2006.175.07:51:39.00#ibcon#wrote, iclass 22, count 2 2006.175.07:51:39.00#ibcon#about to read 3, iclass 22, count 2 2006.175.07:51:39.02#ibcon#read 3, iclass 22, count 2 2006.175.07:51:39.02#ibcon#about to read 4, iclass 22, count 2 2006.175.07:51:39.02#ibcon#read 4, iclass 22, count 2 2006.175.07:51:39.02#ibcon#about to read 5, iclass 22, count 2 2006.175.07:51:39.02#ibcon#read 5, iclass 22, count 2 2006.175.07:51:39.02#ibcon#about to read 6, iclass 22, count 2 2006.175.07:51:39.02#ibcon#read 6, iclass 22, count 2 2006.175.07:51:39.02#ibcon#end of sib2, iclass 22, count 2 2006.175.07:51:39.02#ibcon#*mode == 0, iclass 22, count 2 2006.175.07:51:39.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.07:51:39.02#ibcon#[25=AT03-06\r\n] 2006.175.07:51:39.02#ibcon#*before write, iclass 22, count 2 2006.175.07:51:39.02#ibcon#enter sib2, iclass 22, count 2 2006.175.07:51:39.02#ibcon#flushed, iclass 22, count 2 2006.175.07:51:39.02#ibcon#about to write, iclass 22, count 2 2006.175.07:51:39.02#ibcon#wrote, iclass 22, count 2 2006.175.07:51:39.02#ibcon#about to read 3, iclass 22, count 2 2006.175.07:51:39.05#ibcon#read 3, iclass 22, count 2 2006.175.07:51:39.05#ibcon#about to read 4, iclass 22, count 2 2006.175.07:51:39.05#ibcon#read 4, iclass 22, count 2 2006.175.07:51:39.05#ibcon#about to read 5, iclass 22, count 2 2006.175.07:51:39.05#ibcon#read 5, iclass 22, count 2 2006.175.07:51:39.05#ibcon#about to read 6, iclass 22, count 2 2006.175.07:51:39.05#ibcon#read 6, iclass 22, count 2 2006.175.07:51:39.05#ibcon#end of sib2, iclass 22, count 2 2006.175.07:51:39.05#ibcon#*after write, iclass 22, count 2 2006.175.07:51:39.05#ibcon#*before return 0, iclass 22, count 2 2006.175.07:51:39.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:39.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:39.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.07:51:39.05#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:39.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:39.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:39.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:39.17#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:51:39.17#ibcon#first serial, iclass 22, count 0 2006.175.07:51:39.17#ibcon#enter sib2, iclass 22, count 0 2006.175.07:51:39.17#ibcon#flushed, iclass 22, count 0 2006.175.07:51:39.17#ibcon#about to write, iclass 22, count 0 2006.175.07:51:39.17#ibcon#wrote, iclass 22, count 0 2006.175.07:51:39.17#ibcon#about to read 3, iclass 22, count 0 2006.175.07:51:39.19#ibcon#read 3, iclass 22, count 0 2006.175.07:51:39.19#ibcon#about to read 4, iclass 22, count 0 2006.175.07:51:39.19#ibcon#read 4, iclass 22, count 0 2006.175.07:51:39.19#ibcon#about to read 5, iclass 22, count 0 2006.175.07:51:39.19#ibcon#read 5, iclass 22, count 0 2006.175.07:51:39.19#ibcon#about to read 6, iclass 22, count 0 2006.175.07:51:39.19#ibcon#read 6, iclass 22, count 0 2006.175.07:51:39.19#ibcon#end of sib2, iclass 22, count 0 2006.175.07:51:39.19#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:51:39.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:51:39.19#ibcon#[25=USB\r\n] 2006.175.07:51:39.19#ibcon#*before write, iclass 22, count 0 2006.175.07:51:39.19#ibcon#enter sib2, iclass 22, count 0 2006.175.07:51:39.19#ibcon#flushed, iclass 22, count 0 2006.175.07:51:39.19#ibcon#about to write, iclass 22, count 0 2006.175.07:51:39.19#ibcon#wrote, iclass 22, count 0 2006.175.07:51:39.19#ibcon#about to read 3, iclass 22, count 0 2006.175.07:51:39.22#ibcon#read 3, iclass 22, count 0 2006.175.07:51:39.22#ibcon#about to read 4, iclass 22, count 0 2006.175.07:51:39.22#ibcon#read 4, iclass 22, count 0 2006.175.07:51:39.22#ibcon#about to read 5, iclass 22, count 0 2006.175.07:51:39.22#ibcon#read 5, iclass 22, count 0 2006.175.07:51:39.22#ibcon#about to read 6, iclass 22, count 0 2006.175.07:51:39.22#ibcon#read 6, iclass 22, count 0 2006.175.07:51:39.22#ibcon#end of sib2, iclass 22, count 0 2006.175.07:51:39.22#ibcon#*after write, iclass 22, count 0 2006.175.07:51:39.22#ibcon#*before return 0, iclass 22, count 0 2006.175.07:51:39.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:39.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:39.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:51:39.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:51:39.22$vc4f8/valo=4,832.99 2006.175.07:51:39.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.07:51:39.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.07:51:39.22#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:39.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:39.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:39.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:39.22#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:51:39.22#ibcon#first serial, iclass 24, count 0 2006.175.07:51:39.22#ibcon#enter sib2, iclass 24, count 0 2006.175.07:51:39.22#ibcon#flushed, iclass 24, count 0 2006.175.07:51:39.22#ibcon#about to write, iclass 24, count 0 2006.175.07:51:39.22#ibcon#wrote, iclass 24, count 0 2006.175.07:51:39.22#ibcon#about to read 3, iclass 24, count 0 2006.175.07:51:39.24#ibcon#read 3, iclass 24, count 0 2006.175.07:51:39.24#ibcon#about to read 4, iclass 24, count 0 2006.175.07:51:39.24#ibcon#read 4, iclass 24, count 0 2006.175.07:51:39.24#ibcon#about to read 5, iclass 24, count 0 2006.175.07:51:39.24#ibcon#read 5, iclass 24, count 0 2006.175.07:51:39.24#ibcon#about to read 6, iclass 24, count 0 2006.175.07:51:39.24#ibcon#read 6, iclass 24, count 0 2006.175.07:51:39.24#ibcon#end of sib2, iclass 24, count 0 2006.175.07:51:39.24#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:51:39.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:51:39.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:51:39.24#ibcon#*before write, iclass 24, count 0 2006.175.07:51:39.24#ibcon#enter sib2, iclass 24, count 0 2006.175.07:51:39.24#ibcon#flushed, iclass 24, count 0 2006.175.07:51:39.24#ibcon#about to write, iclass 24, count 0 2006.175.07:51:39.24#ibcon#wrote, iclass 24, count 0 2006.175.07:51:39.24#ibcon#about to read 3, iclass 24, count 0 2006.175.07:51:39.28#ibcon#read 3, iclass 24, count 0 2006.175.07:51:39.28#ibcon#about to read 4, iclass 24, count 0 2006.175.07:51:39.28#ibcon#read 4, iclass 24, count 0 2006.175.07:51:39.28#ibcon#about to read 5, iclass 24, count 0 2006.175.07:51:39.28#ibcon#read 5, iclass 24, count 0 2006.175.07:51:39.28#ibcon#about to read 6, iclass 24, count 0 2006.175.07:51:39.28#ibcon#read 6, iclass 24, count 0 2006.175.07:51:39.28#ibcon#end of sib2, iclass 24, count 0 2006.175.07:51:39.28#ibcon#*after write, iclass 24, count 0 2006.175.07:51:39.28#ibcon#*before return 0, iclass 24, count 0 2006.175.07:51:39.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:39.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:39.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:51:39.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:51:39.28$vc4f8/va=4,7 2006.175.07:51:39.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.07:51:39.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.07:51:39.28#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:39.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:39.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:39.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:39.34#ibcon#enter wrdev, iclass 26, count 2 2006.175.07:51:39.34#ibcon#first serial, iclass 26, count 2 2006.175.07:51:39.34#ibcon#enter sib2, iclass 26, count 2 2006.175.07:51:39.34#ibcon#flushed, iclass 26, count 2 2006.175.07:51:39.34#ibcon#about to write, iclass 26, count 2 2006.175.07:51:39.34#ibcon#wrote, iclass 26, count 2 2006.175.07:51:39.34#ibcon#about to read 3, iclass 26, count 2 2006.175.07:51:39.36#ibcon#read 3, iclass 26, count 2 2006.175.07:51:39.36#ibcon#about to read 4, iclass 26, count 2 2006.175.07:51:39.36#ibcon#read 4, iclass 26, count 2 2006.175.07:51:39.36#ibcon#about to read 5, iclass 26, count 2 2006.175.07:51:39.36#ibcon#read 5, iclass 26, count 2 2006.175.07:51:39.36#ibcon#about to read 6, iclass 26, count 2 2006.175.07:51:39.36#ibcon#read 6, iclass 26, count 2 2006.175.07:51:39.36#ibcon#end of sib2, iclass 26, count 2 2006.175.07:51:39.36#ibcon#*mode == 0, iclass 26, count 2 2006.175.07:51:39.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.07:51:39.36#ibcon#[25=AT04-07\r\n] 2006.175.07:51:39.36#ibcon#*before write, iclass 26, count 2 2006.175.07:51:39.36#ibcon#enter sib2, iclass 26, count 2 2006.175.07:51:39.36#ibcon#flushed, iclass 26, count 2 2006.175.07:51:39.36#ibcon#about to write, iclass 26, count 2 2006.175.07:51:39.36#ibcon#wrote, iclass 26, count 2 2006.175.07:51:39.36#ibcon#about to read 3, iclass 26, count 2 2006.175.07:51:39.39#ibcon#read 3, iclass 26, count 2 2006.175.07:51:39.39#ibcon#about to read 4, iclass 26, count 2 2006.175.07:51:39.39#ibcon#read 4, iclass 26, count 2 2006.175.07:51:39.39#ibcon#about to read 5, iclass 26, count 2 2006.175.07:51:39.39#ibcon#read 5, iclass 26, count 2 2006.175.07:51:39.39#ibcon#about to read 6, iclass 26, count 2 2006.175.07:51:39.39#ibcon#read 6, iclass 26, count 2 2006.175.07:51:39.39#ibcon#end of sib2, iclass 26, count 2 2006.175.07:51:39.39#ibcon#*after write, iclass 26, count 2 2006.175.07:51:39.39#ibcon#*before return 0, iclass 26, count 2 2006.175.07:51:39.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:39.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:39.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.07:51:39.39#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:39.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:39.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:39.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:39.51#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:51:39.51#ibcon#first serial, iclass 26, count 0 2006.175.07:51:39.51#ibcon#enter sib2, iclass 26, count 0 2006.175.07:51:39.51#ibcon#flushed, iclass 26, count 0 2006.175.07:51:39.51#ibcon#about to write, iclass 26, count 0 2006.175.07:51:39.51#ibcon#wrote, iclass 26, count 0 2006.175.07:51:39.51#ibcon#about to read 3, iclass 26, count 0 2006.175.07:51:39.53#ibcon#read 3, iclass 26, count 0 2006.175.07:51:39.53#ibcon#about to read 4, iclass 26, count 0 2006.175.07:51:39.53#ibcon#read 4, iclass 26, count 0 2006.175.07:51:39.53#ibcon#about to read 5, iclass 26, count 0 2006.175.07:51:39.53#ibcon#read 5, iclass 26, count 0 2006.175.07:51:39.53#ibcon#about to read 6, iclass 26, count 0 2006.175.07:51:39.53#ibcon#read 6, iclass 26, count 0 2006.175.07:51:39.53#ibcon#end of sib2, iclass 26, count 0 2006.175.07:51:39.53#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:51:39.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:51:39.53#ibcon#[25=USB\r\n] 2006.175.07:51:39.53#ibcon#*before write, iclass 26, count 0 2006.175.07:51:39.53#ibcon#enter sib2, iclass 26, count 0 2006.175.07:51:39.53#ibcon#flushed, iclass 26, count 0 2006.175.07:51:39.53#ibcon#about to write, iclass 26, count 0 2006.175.07:51:39.53#ibcon#wrote, iclass 26, count 0 2006.175.07:51:39.53#ibcon#about to read 3, iclass 26, count 0 2006.175.07:51:39.56#ibcon#read 3, iclass 26, count 0 2006.175.07:51:39.56#ibcon#about to read 4, iclass 26, count 0 2006.175.07:51:39.56#ibcon#read 4, iclass 26, count 0 2006.175.07:51:39.56#ibcon#about to read 5, iclass 26, count 0 2006.175.07:51:39.56#ibcon#read 5, iclass 26, count 0 2006.175.07:51:39.56#ibcon#about to read 6, iclass 26, count 0 2006.175.07:51:39.56#ibcon#read 6, iclass 26, count 0 2006.175.07:51:39.56#ibcon#end of sib2, iclass 26, count 0 2006.175.07:51:39.56#ibcon#*after write, iclass 26, count 0 2006.175.07:51:39.56#ibcon#*before return 0, iclass 26, count 0 2006.175.07:51:39.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:39.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:39.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:51:39.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:51:39.56$vc4f8/valo=5,652.99 2006.175.07:51:39.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.07:51:39.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.07:51:39.56#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:39.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:39.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:39.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:39.56#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:51:39.56#ibcon#first serial, iclass 28, count 0 2006.175.07:51:39.56#ibcon#enter sib2, iclass 28, count 0 2006.175.07:51:39.56#ibcon#flushed, iclass 28, count 0 2006.175.07:51:39.56#ibcon#about to write, iclass 28, count 0 2006.175.07:51:39.56#ibcon#wrote, iclass 28, count 0 2006.175.07:51:39.56#ibcon#about to read 3, iclass 28, count 0 2006.175.07:51:39.58#ibcon#read 3, iclass 28, count 0 2006.175.07:51:39.58#ibcon#about to read 4, iclass 28, count 0 2006.175.07:51:39.58#ibcon#read 4, iclass 28, count 0 2006.175.07:51:39.58#ibcon#about to read 5, iclass 28, count 0 2006.175.07:51:39.58#ibcon#read 5, iclass 28, count 0 2006.175.07:51:39.58#ibcon#about to read 6, iclass 28, count 0 2006.175.07:51:39.58#ibcon#read 6, iclass 28, count 0 2006.175.07:51:39.58#ibcon#end of sib2, iclass 28, count 0 2006.175.07:51:39.58#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:51:39.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:51:39.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:51:39.58#ibcon#*before write, iclass 28, count 0 2006.175.07:51:39.58#ibcon#enter sib2, iclass 28, count 0 2006.175.07:51:39.58#ibcon#flushed, iclass 28, count 0 2006.175.07:51:39.58#ibcon#about to write, iclass 28, count 0 2006.175.07:51:39.58#ibcon#wrote, iclass 28, count 0 2006.175.07:51:39.58#ibcon#about to read 3, iclass 28, count 0 2006.175.07:51:39.62#ibcon#read 3, iclass 28, count 0 2006.175.07:51:39.62#ibcon#about to read 4, iclass 28, count 0 2006.175.07:51:39.62#ibcon#read 4, iclass 28, count 0 2006.175.07:51:39.62#ibcon#about to read 5, iclass 28, count 0 2006.175.07:51:39.62#ibcon#read 5, iclass 28, count 0 2006.175.07:51:39.62#ibcon#about to read 6, iclass 28, count 0 2006.175.07:51:39.62#ibcon#read 6, iclass 28, count 0 2006.175.07:51:39.62#ibcon#end of sib2, iclass 28, count 0 2006.175.07:51:39.62#ibcon#*after write, iclass 28, count 0 2006.175.07:51:39.62#ibcon#*before return 0, iclass 28, count 0 2006.175.07:51:39.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:39.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:39.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:51:39.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:51:39.62$vc4f8/va=5,7 2006.175.07:51:39.62#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.07:51:39.62#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.07:51:39.62#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:39.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:39.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:39.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:39.68#ibcon#enter wrdev, iclass 30, count 2 2006.175.07:51:39.68#ibcon#first serial, iclass 30, count 2 2006.175.07:51:39.68#ibcon#enter sib2, iclass 30, count 2 2006.175.07:51:39.68#ibcon#flushed, iclass 30, count 2 2006.175.07:51:39.68#ibcon#about to write, iclass 30, count 2 2006.175.07:51:39.68#ibcon#wrote, iclass 30, count 2 2006.175.07:51:39.68#ibcon#about to read 3, iclass 30, count 2 2006.175.07:51:39.70#ibcon#read 3, iclass 30, count 2 2006.175.07:51:39.70#ibcon#about to read 4, iclass 30, count 2 2006.175.07:51:39.70#ibcon#read 4, iclass 30, count 2 2006.175.07:51:39.70#ibcon#about to read 5, iclass 30, count 2 2006.175.07:51:39.70#ibcon#read 5, iclass 30, count 2 2006.175.07:51:39.70#ibcon#about to read 6, iclass 30, count 2 2006.175.07:51:39.70#ibcon#read 6, iclass 30, count 2 2006.175.07:51:39.70#ibcon#end of sib2, iclass 30, count 2 2006.175.07:51:39.70#ibcon#*mode == 0, iclass 30, count 2 2006.175.07:51:39.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.07:51:39.70#ibcon#[25=AT05-07\r\n] 2006.175.07:51:39.70#ibcon#*before write, iclass 30, count 2 2006.175.07:51:39.70#ibcon#enter sib2, iclass 30, count 2 2006.175.07:51:39.70#ibcon#flushed, iclass 30, count 2 2006.175.07:51:39.70#ibcon#about to write, iclass 30, count 2 2006.175.07:51:39.70#ibcon#wrote, iclass 30, count 2 2006.175.07:51:39.70#ibcon#about to read 3, iclass 30, count 2 2006.175.07:51:39.73#ibcon#read 3, iclass 30, count 2 2006.175.07:51:39.73#ibcon#about to read 4, iclass 30, count 2 2006.175.07:51:39.73#ibcon#read 4, iclass 30, count 2 2006.175.07:51:39.73#ibcon#about to read 5, iclass 30, count 2 2006.175.07:51:39.73#ibcon#read 5, iclass 30, count 2 2006.175.07:51:39.73#ibcon#about to read 6, iclass 30, count 2 2006.175.07:51:39.73#ibcon#read 6, iclass 30, count 2 2006.175.07:51:39.73#ibcon#end of sib2, iclass 30, count 2 2006.175.07:51:39.73#ibcon#*after write, iclass 30, count 2 2006.175.07:51:39.73#ibcon#*before return 0, iclass 30, count 2 2006.175.07:51:39.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:39.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:39.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.07:51:39.73#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:39.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:39.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:39.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:39.85#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:51:39.85#ibcon#first serial, iclass 30, count 0 2006.175.07:51:39.85#ibcon#enter sib2, iclass 30, count 0 2006.175.07:51:39.85#ibcon#flushed, iclass 30, count 0 2006.175.07:51:39.85#ibcon#about to write, iclass 30, count 0 2006.175.07:51:39.85#ibcon#wrote, iclass 30, count 0 2006.175.07:51:39.85#ibcon#about to read 3, iclass 30, count 0 2006.175.07:51:39.87#ibcon#read 3, iclass 30, count 0 2006.175.07:51:39.87#ibcon#about to read 4, iclass 30, count 0 2006.175.07:51:39.87#ibcon#read 4, iclass 30, count 0 2006.175.07:51:39.87#ibcon#about to read 5, iclass 30, count 0 2006.175.07:51:39.87#ibcon#read 5, iclass 30, count 0 2006.175.07:51:39.87#ibcon#about to read 6, iclass 30, count 0 2006.175.07:51:39.87#ibcon#read 6, iclass 30, count 0 2006.175.07:51:39.87#ibcon#end of sib2, iclass 30, count 0 2006.175.07:51:39.87#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:51:39.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:51:39.87#ibcon#[25=USB\r\n] 2006.175.07:51:39.87#ibcon#*before write, iclass 30, count 0 2006.175.07:51:39.87#ibcon#enter sib2, iclass 30, count 0 2006.175.07:51:39.87#ibcon#flushed, iclass 30, count 0 2006.175.07:51:39.87#ibcon#about to write, iclass 30, count 0 2006.175.07:51:39.87#ibcon#wrote, iclass 30, count 0 2006.175.07:51:39.87#ibcon#about to read 3, iclass 30, count 0 2006.175.07:51:39.90#ibcon#read 3, iclass 30, count 0 2006.175.07:51:39.90#ibcon#about to read 4, iclass 30, count 0 2006.175.07:51:39.90#ibcon#read 4, iclass 30, count 0 2006.175.07:51:39.90#ibcon#about to read 5, iclass 30, count 0 2006.175.07:51:39.90#ibcon#read 5, iclass 30, count 0 2006.175.07:51:39.90#ibcon#about to read 6, iclass 30, count 0 2006.175.07:51:39.90#ibcon#read 6, iclass 30, count 0 2006.175.07:51:39.90#ibcon#end of sib2, iclass 30, count 0 2006.175.07:51:39.90#ibcon#*after write, iclass 30, count 0 2006.175.07:51:39.90#ibcon#*before return 0, iclass 30, count 0 2006.175.07:51:39.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:39.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:39.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:51:39.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:51:39.90$vc4f8/valo=6,772.99 2006.175.07:51:39.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.07:51:39.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.07:51:39.90#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:39.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:39.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:39.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:39.90#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:51:39.90#ibcon#first serial, iclass 32, count 0 2006.175.07:51:39.90#ibcon#enter sib2, iclass 32, count 0 2006.175.07:51:39.90#ibcon#flushed, iclass 32, count 0 2006.175.07:51:39.90#ibcon#about to write, iclass 32, count 0 2006.175.07:51:39.90#ibcon#wrote, iclass 32, count 0 2006.175.07:51:39.90#ibcon#about to read 3, iclass 32, count 0 2006.175.07:51:39.92#ibcon#read 3, iclass 32, count 0 2006.175.07:51:39.92#ibcon#about to read 4, iclass 32, count 0 2006.175.07:51:39.92#ibcon#read 4, iclass 32, count 0 2006.175.07:51:39.92#ibcon#about to read 5, iclass 32, count 0 2006.175.07:51:39.92#ibcon#read 5, iclass 32, count 0 2006.175.07:51:39.92#ibcon#about to read 6, iclass 32, count 0 2006.175.07:51:39.92#ibcon#read 6, iclass 32, count 0 2006.175.07:51:39.92#ibcon#end of sib2, iclass 32, count 0 2006.175.07:51:39.92#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:51:39.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:51:39.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:51:39.92#ibcon#*before write, iclass 32, count 0 2006.175.07:51:39.92#ibcon#enter sib2, iclass 32, count 0 2006.175.07:51:39.92#ibcon#flushed, iclass 32, count 0 2006.175.07:51:39.92#ibcon#about to write, iclass 32, count 0 2006.175.07:51:39.92#ibcon#wrote, iclass 32, count 0 2006.175.07:51:39.92#ibcon#about to read 3, iclass 32, count 0 2006.175.07:51:39.96#ibcon#read 3, iclass 32, count 0 2006.175.07:51:39.96#ibcon#about to read 4, iclass 32, count 0 2006.175.07:51:39.96#ibcon#read 4, iclass 32, count 0 2006.175.07:51:39.96#ibcon#about to read 5, iclass 32, count 0 2006.175.07:51:39.96#ibcon#read 5, iclass 32, count 0 2006.175.07:51:39.96#ibcon#about to read 6, iclass 32, count 0 2006.175.07:51:39.96#ibcon#read 6, iclass 32, count 0 2006.175.07:51:39.96#ibcon#end of sib2, iclass 32, count 0 2006.175.07:51:39.96#ibcon#*after write, iclass 32, count 0 2006.175.07:51:39.96#ibcon#*before return 0, iclass 32, count 0 2006.175.07:51:39.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:39.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:39.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:51:39.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:51:39.96$vc4f8/va=6,6 2006.175.07:51:39.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.175.07:51:39.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.175.07:51:39.96#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:39.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:40.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:40.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:40.02#ibcon#enter wrdev, iclass 34, count 2 2006.175.07:51:40.02#ibcon#first serial, iclass 34, count 2 2006.175.07:51:40.02#ibcon#enter sib2, iclass 34, count 2 2006.175.07:51:40.02#ibcon#flushed, iclass 34, count 2 2006.175.07:51:40.02#ibcon#about to write, iclass 34, count 2 2006.175.07:51:40.02#ibcon#wrote, iclass 34, count 2 2006.175.07:51:40.02#ibcon#about to read 3, iclass 34, count 2 2006.175.07:51:40.04#ibcon#read 3, iclass 34, count 2 2006.175.07:51:40.04#ibcon#about to read 4, iclass 34, count 2 2006.175.07:51:40.04#ibcon#read 4, iclass 34, count 2 2006.175.07:51:40.04#ibcon#about to read 5, iclass 34, count 2 2006.175.07:51:40.04#ibcon#read 5, iclass 34, count 2 2006.175.07:51:40.04#ibcon#about to read 6, iclass 34, count 2 2006.175.07:51:40.04#ibcon#read 6, iclass 34, count 2 2006.175.07:51:40.04#ibcon#end of sib2, iclass 34, count 2 2006.175.07:51:40.04#ibcon#*mode == 0, iclass 34, count 2 2006.175.07:51:40.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.175.07:51:40.04#ibcon#[25=AT06-06\r\n] 2006.175.07:51:40.04#ibcon#*before write, iclass 34, count 2 2006.175.07:51:40.04#ibcon#enter sib2, iclass 34, count 2 2006.175.07:51:40.04#ibcon#flushed, iclass 34, count 2 2006.175.07:51:40.04#ibcon#about to write, iclass 34, count 2 2006.175.07:51:40.04#ibcon#wrote, iclass 34, count 2 2006.175.07:51:40.04#ibcon#about to read 3, iclass 34, count 2 2006.175.07:51:40.07#ibcon#read 3, iclass 34, count 2 2006.175.07:51:40.07#ibcon#about to read 4, iclass 34, count 2 2006.175.07:51:40.07#ibcon#read 4, iclass 34, count 2 2006.175.07:51:40.07#ibcon#about to read 5, iclass 34, count 2 2006.175.07:51:40.07#ibcon#read 5, iclass 34, count 2 2006.175.07:51:40.07#ibcon#about to read 6, iclass 34, count 2 2006.175.07:51:40.07#ibcon#read 6, iclass 34, count 2 2006.175.07:51:40.07#ibcon#end of sib2, iclass 34, count 2 2006.175.07:51:40.07#ibcon#*after write, iclass 34, count 2 2006.175.07:51:40.07#ibcon#*before return 0, iclass 34, count 2 2006.175.07:51:40.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:40.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:40.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.175.07:51:40.07#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:40.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:40.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:40.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:40.19#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:51:40.19#ibcon#first serial, iclass 34, count 0 2006.175.07:51:40.19#ibcon#enter sib2, iclass 34, count 0 2006.175.07:51:40.19#ibcon#flushed, iclass 34, count 0 2006.175.07:51:40.19#ibcon#about to write, iclass 34, count 0 2006.175.07:51:40.19#ibcon#wrote, iclass 34, count 0 2006.175.07:51:40.19#ibcon#about to read 3, iclass 34, count 0 2006.175.07:51:40.21#ibcon#read 3, iclass 34, count 0 2006.175.07:51:40.21#ibcon#about to read 4, iclass 34, count 0 2006.175.07:51:40.21#ibcon#read 4, iclass 34, count 0 2006.175.07:51:40.21#ibcon#about to read 5, iclass 34, count 0 2006.175.07:51:40.21#ibcon#read 5, iclass 34, count 0 2006.175.07:51:40.21#ibcon#about to read 6, iclass 34, count 0 2006.175.07:51:40.21#ibcon#read 6, iclass 34, count 0 2006.175.07:51:40.21#ibcon#end of sib2, iclass 34, count 0 2006.175.07:51:40.21#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:51:40.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:51:40.21#ibcon#[25=USB\r\n] 2006.175.07:51:40.21#ibcon#*before write, iclass 34, count 0 2006.175.07:51:40.21#ibcon#enter sib2, iclass 34, count 0 2006.175.07:51:40.21#ibcon#flushed, iclass 34, count 0 2006.175.07:51:40.21#ibcon#about to write, iclass 34, count 0 2006.175.07:51:40.21#ibcon#wrote, iclass 34, count 0 2006.175.07:51:40.21#ibcon#about to read 3, iclass 34, count 0 2006.175.07:51:40.24#ibcon#read 3, iclass 34, count 0 2006.175.07:51:40.24#ibcon#about to read 4, iclass 34, count 0 2006.175.07:51:40.24#ibcon#read 4, iclass 34, count 0 2006.175.07:51:40.24#ibcon#about to read 5, iclass 34, count 0 2006.175.07:51:40.24#ibcon#read 5, iclass 34, count 0 2006.175.07:51:40.24#ibcon#about to read 6, iclass 34, count 0 2006.175.07:51:40.24#ibcon#read 6, iclass 34, count 0 2006.175.07:51:40.24#ibcon#end of sib2, iclass 34, count 0 2006.175.07:51:40.24#ibcon#*after write, iclass 34, count 0 2006.175.07:51:40.24#ibcon#*before return 0, iclass 34, count 0 2006.175.07:51:40.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:40.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:40.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:51:40.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:51:40.24$vc4f8/valo=7,832.99 2006.175.07:51:40.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.07:51:40.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.07:51:40.24#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:40.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:40.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:40.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:40.24#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:51:40.24#ibcon#first serial, iclass 36, count 0 2006.175.07:51:40.24#ibcon#enter sib2, iclass 36, count 0 2006.175.07:51:40.24#ibcon#flushed, iclass 36, count 0 2006.175.07:51:40.24#ibcon#about to write, iclass 36, count 0 2006.175.07:51:40.24#ibcon#wrote, iclass 36, count 0 2006.175.07:51:40.24#ibcon#about to read 3, iclass 36, count 0 2006.175.07:51:40.26#ibcon#read 3, iclass 36, count 0 2006.175.07:51:40.26#ibcon#about to read 4, iclass 36, count 0 2006.175.07:51:40.26#ibcon#read 4, iclass 36, count 0 2006.175.07:51:40.26#ibcon#about to read 5, iclass 36, count 0 2006.175.07:51:40.26#ibcon#read 5, iclass 36, count 0 2006.175.07:51:40.26#ibcon#about to read 6, iclass 36, count 0 2006.175.07:51:40.26#ibcon#read 6, iclass 36, count 0 2006.175.07:51:40.26#ibcon#end of sib2, iclass 36, count 0 2006.175.07:51:40.26#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:51:40.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:51:40.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:51:40.26#ibcon#*before write, iclass 36, count 0 2006.175.07:51:40.26#ibcon#enter sib2, iclass 36, count 0 2006.175.07:51:40.26#ibcon#flushed, iclass 36, count 0 2006.175.07:51:40.26#ibcon#about to write, iclass 36, count 0 2006.175.07:51:40.26#ibcon#wrote, iclass 36, count 0 2006.175.07:51:40.26#ibcon#about to read 3, iclass 36, count 0 2006.175.07:51:40.30#ibcon#read 3, iclass 36, count 0 2006.175.07:51:40.30#ibcon#about to read 4, iclass 36, count 0 2006.175.07:51:40.30#ibcon#read 4, iclass 36, count 0 2006.175.07:51:40.30#ibcon#about to read 5, iclass 36, count 0 2006.175.07:51:40.30#ibcon#read 5, iclass 36, count 0 2006.175.07:51:40.30#ibcon#about to read 6, iclass 36, count 0 2006.175.07:51:40.30#ibcon#read 6, iclass 36, count 0 2006.175.07:51:40.30#ibcon#end of sib2, iclass 36, count 0 2006.175.07:51:40.30#ibcon#*after write, iclass 36, count 0 2006.175.07:51:40.30#ibcon#*before return 0, iclass 36, count 0 2006.175.07:51:40.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:40.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:40.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:51:40.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:51:40.30$vc4f8/va=7,6 2006.175.07:51:40.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.175.07:51:40.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.175.07:51:40.30#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:40.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:51:40.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:51:40.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:51:40.36#ibcon#enter wrdev, iclass 38, count 2 2006.175.07:51:40.36#ibcon#first serial, iclass 38, count 2 2006.175.07:51:40.36#ibcon#enter sib2, iclass 38, count 2 2006.175.07:51:40.36#ibcon#flushed, iclass 38, count 2 2006.175.07:51:40.36#ibcon#about to write, iclass 38, count 2 2006.175.07:51:40.36#ibcon#wrote, iclass 38, count 2 2006.175.07:51:40.36#ibcon#about to read 3, iclass 38, count 2 2006.175.07:51:40.38#ibcon#read 3, iclass 38, count 2 2006.175.07:51:40.38#ibcon#about to read 4, iclass 38, count 2 2006.175.07:51:40.38#ibcon#read 4, iclass 38, count 2 2006.175.07:51:40.38#ibcon#about to read 5, iclass 38, count 2 2006.175.07:51:40.38#ibcon#read 5, iclass 38, count 2 2006.175.07:51:40.38#ibcon#about to read 6, iclass 38, count 2 2006.175.07:51:40.38#ibcon#read 6, iclass 38, count 2 2006.175.07:51:40.38#ibcon#end of sib2, iclass 38, count 2 2006.175.07:51:40.38#ibcon#*mode == 0, iclass 38, count 2 2006.175.07:51:40.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.175.07:51:40.38#ibcon#[25=AT07-06\r\n] 2006.175.07:51:40.38#ibcon#*before write, iclass 38, count 2 2006.175.07:51:40.38#ibcon#enter sib2, iclass 38, count 2 2006.175.07:51:40.38#ibcon#flushed, iclass 38, count 2 2006.175.07:51:40.38#ibcon#about to write, iclass 38, count 2 2006.175.07:51:40.38#ibcon#wrote, iclass 38, count 2 2006.175.07:51:40.38#ibcon#about to read 3, iclass 38, count 2 2006.175.07:51:40.41#ibcon#read 3, iclass 38, count 2 2006.175.07:51:40.41#ibcon#about to read 4, iclass 38, count 2 2006.175.07:51:40.41#ibcon#read 4, iclass 38, count 2 2006.175.07:51:40.41#ibcon#about to read 5, iclass 38, count 2 2006.175.07:51:40.41#ibcon#read 5, iclass 38, count 2 2006.175.07:51:40.41#ibcon#about to read 6, iclass 38, count 2 2006.175.07:51:40.41#ibcon#read 6, iclass 38, count 2 2006.175.07:51:40.41#ibcon#end of sib2, iclass 38, count 2 2006.175.07:51:40.41#ibcon#*after write, iclass 38, count 2 2006.175.07:51:40.41#ibcon#*before return 0, iclass 38, count 2 2006.175.07:51:40.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:51:40.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.175.07:51:40.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.175.07:51:40.41#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:40.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:51:40.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:51:40.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:51:40.53#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:51:40.53#ibcon#first serial, iclass 38, count 0 2006.175.07:51:40.53#ibcon#enter sib2, iclass 38, count 0 2006.175.07:51:40.53#ibcon#flushed, iclass 38, count 0 2006.175.07:51:40.53#ibcon#about to write, iclass 38, count 0 2006.175.07:51:40.53#ibcon#wrote, iclass 38, count 0 2006.175.07:51:40.53#ibcon#about to read 3, iclass 38, count 0 2006.175.07:51:40.55#ibcon#read 3, iclass 38, count 0 2006.175.07:51:40.55#ibcon#about to read 4, iclass 38, count 0 2006.175.07:51:40.55#ibcon#read 4, iclass 38, count 0 2006.175.07:51:40.55#ibcon#about to read 5, iclass 38, count 0 2006.175.07:51:40.55#ibcon#read 5, iclass 38, count 0 2006.175.07:51:40.55#ibcon#about to read 6, iclass 38, count 0 2006.175.07:51:40.55#ibcon#read 6, iclass 38, count 0 2006.175.07:51:40.55#ibcon#end of sib2, iclass 38, count 0 2006.175.07:51:40.55#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:51:40.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:51:40.55#ibcon#[25=USB\r\n] 2006.175.07:51:40.55#ibcon#*before write, iclass 38, count 0 2006.175.07:51:40.55#ibcon#enter sib2, iclass 38, count 0 2006.175.07:51:40.55#ibcon#flushed, iclass 38, count 0 2006.175.07:51:40.55#ibcon#about to write, iclass 38, count 0 2006.175.07:51:40.55#ibcon#wrote, iclass 38, count 0 2006.175.07:51:40.55#ibcon#about to read 3, iclass 38, count 0 2006.175.07:51:40.58#ibcon#read 3, iclass 38, count 0 2006.175.07:51:40.58#ibcon#about to read 4, iclass 38, count 0 2006.175.07:51:40.58#ibcon#read 4, iclass 38, count 0 2006.175.07:51:40.58#ibcon#about to read 5, iclass 38, count 0 2006.175.07:51:40.58#ibcon#read 5, iclass 38, count 0 2006.175.07:51:40.58#ibcon#about to read 6, iclass 38, count 0 2006.175.07:51:40.58#ibcon#read 6, iclass 38, count 0 2006.175.07:51:40.58#ibcon#end of sib2, iclass 38, count 0 2006.175.07:51:40.58#ibcon#*after write, iclass 38, count 0 2006.175.07:51:40.58#ibcon#*before return 0, iclass 38, count 0 2006.175.07:51:40.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:51:40.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.175.07:51:40.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:51:40.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:51:40.58$vc4f8/valo=8,852.99 2006.175.07:51:40.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.07:51:40.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.07:51:40.58#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:40.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:51:40.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:51:40.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:51:40.58#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:51:40.58#ibcon#first serial, iclass 40, count 0 2006.175.07:51:40.58#ibcon#enter sib2, iclass 40, count 0 2006.175.07:51:40.58#ibcon#flushed, iclass 40, count 0 2006.175.07:51:40.58#ibcon#about to write, iclass 40, count 0 2006.175.07:51:40.58#ibcon#wrote, iclass 40, count 0 2006.175.07:51:40.58#ibcon#about to read 3, iclass 40, count 0 2006.175.07:51:40.60#ibcon#read 3, iclass 40, count 0 2006.175.07:51:40.60#ibcon#about to read 4, iclass 40, count 0 2006.175.07:51:40.60#ibcon#read 4, iclass 40, count 0 2006.175.07:51:40.60#ibcon#about to read 5, iclass 40, count 0 2006.175.07:51:40.60#ibcon#read 5, iclass 40, count 0 2006.175.07:51:40.60#ibcon#about to read 6, iclass 40, count 0 2006.175.07:51:40.60#ibcon#read 6, iclass 40, count 0 2006.175.07:51:40.60#ibcon#end of sib2, iclass 40, count 0 2006.175.07:51:40.60#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:51:40.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:51:40.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:51:40.60#ibcon#*before write, iclass 40, count 0 2006.175.07:51:40.60#ibcon#enter sib2, iclass 40, count 0 2006.175.07:51:40.60#ibcon#flushed, iclass 40, count 0 2006.175.07:51:40.60#ibcon#about to write, iclass 40, count 0 2006.175.07:51:40.60#ibcon#wrote, iclass 40, count 0 2006.175.07:51:40.60#ibcon#about to read 3, iclass 40, count 0 2006.175.07:51:40.64#ibcon#read 3, iclass 40, count 0 2006.175.07:51:40.64#ibcon#about to read 4, iclass 40, count 0 2006.175.07:51:40.64#ibcon#read 4, iclass 40, count 0 2006.175.07:51:40.64#ibcon#about to read 5, iclass 40, count 0 2006.175.07:51:40.64#ibcon#read 5, iclass 40, count 0 2006.175.07:51:40.64#ibcon#about to read 6, iclass 40, count 0 2006.175.07:51:40.64#ibcon#read 6, iclass 40, count 0 2006.175.07:51:40.64#ibcon#end of sib2, iclass 40, count 0 2006.175.07:51:40.64#ibcon#*after write, iclass 40, count 0 2006.175.07:51:40.64#ibcon#*before return 0, iclass 40, count 0 2006.175.07:51:40.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:51:40.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.07:51:40.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:51:40.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:51:40.64$vc4f8/va=8,6 2006.175.07:51:40.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.175.07:51:40.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.175.07:51:40.64#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:40.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:51:40.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:51:40.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:51:40.70#ibcon#enter wrdev, iclass 4, count 2 2006.175.07:51:40.70#ibcon#first serial, iclass 4, count 2 2006.175.07:51:40.70#ibcon#enter sib2, iclass 4, count 2 2006.175.07:51:40.70#ibcon#flushed, iclass 4, count 2 2006.175.07:51:40.70#ibcon#about to write, iclass 4, count 2 2006.175.07:51:40.70#ibcon#wrote, iclass 4, count 2 2006.175.07:51:40.70#ibcon#about to read 3, iclass 4, count 2 2006.175.07:51:40.72#ibcon#read 3, iclass 4, count 2 2006.175.07:51:40.72#ibcon#about to read 4, iclass 4, count 2 2006.175.07:51:40.72#ibcon#read 4, iclass 4, count 2 2006.175.07:51:40.72#ibcon#about to read 5, iclass 4, count 2 2006.175.07:51:40.72#ibcon#read 5, iclass 4, count 2 2006.175.07:51:40.72#ibcon#about to read 6, iclass 4, count 2 2006.175.07:51:40.72#ibcon#read 6, iclass 4, count 2 2006.175.07:51:40.72#ibcon#end of sib2, iclass 4, count 2 2006.175.07:51:40.72#ibcon#*mode == 0, iclass 4, count 2 2006.175.07:51:40.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.175.07:51:40.72#ibcon#[25=AT08-06\r\n] 2006.175.07:51:40.72#ibcon#*before write, iclass 4, count 2 2006.175.07:51:40.72#ibcon#enter sib2, iclass 4, count 2 2006.175.07:51:40.72#ibcon#flushed, iclass 4, count 2 2006.175.07:51:40.72#ibcon#about to write, iclass 4, count 2 2006.175.07:51:40.72#ibcon#wrote, iclass 4, count 2 2006.175.07:51:40.72#ibcon#about to read 3, iclass 4, count 2 2006.175.07:51:40.75#ibcon#read 3, iclass 4, count 2 2006.175.07:51:40.75#ibcon#about to read 4, iclass 4, count 2 2006.175.07:51:40.75#ibcon#read 4, iclass 4, count 2 2006.175.07:51:40.75#ibcon#about to read 5, iclass 4, count 2 2006.175.07:51:40.75#ibcon#read 5, iclass 4, count 2 2006.175.07:51:40.75#ibcon#about to read 6, iclass 4, count 2 2006.175.07:51:40.75#ibcon#read 6, iclass 4, count 2 2006.175.07:51:40.75#ibcon#end of sib2, iclass 4, count 2 2006.175.07:51:40.75#ibcon#*after write, iclass 4, count 2 2006.175.07:51:40.75#ibcon#*before return 0, iclass 4, count 2 2006.175.07:51:40.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:51:40.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.175.07:51:40.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.175.07:51:40.75#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:40.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:51:40.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:51:40.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:51:40.87#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:51:40.87#ibcon#first serial, iclass 4, count 0 2006.175.07:51:40.87#ibcon#enter sib2, iclass 4, count 0 2006.175.07:51:40.87#ibcon#flushed, iclass 4, count 0 2006.175.07:51:40.87#ibcon#about to write, iclass 4, count 0 2006.175.07:51:40.87#ibcon#wrote, iclass 4, count 0 2006.175.07:51:40.87#ibcon#about to read 3, iclass 4, count 0 2006.175.07:51:40.89#ibcon#read 3, iclass 4, count 0 2006.175.07:51:40.89#ibcon#about to read 4, iclass 4, count 0 2006.175.07:51:40.89#ibcon#read 4, iclass 4, count 0 2006.175.07:51:40.89#ibcon#about to read 5, iclass 4, count 0 2006.175.07:51:40.89#ibcon#read 5, iclass 4, count 0 2006.175.07:51:40.89#ibcon#about to read 6, iclass 4, count 0 2006.175.07:51:40.89#ibcon#read 6, iclass 4, count 0 2006.175.07:51:40.89#ibcon#end of sib2, iclass 4, count 0 2006.175.07:51:40.89#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:51:40.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:51:40.89#ibcon#[25=USB\r\n] 2006.175.07:51:40.89#ibcon#*before write, iclass 4, count 0 2006.175.07:51:40.89#ibcon#enter sib2, iclass 4, count 0 2006.175.07:51:40.89#ibcon#flushed, iclass 4, count 0 2006.175.07:51:40.89#ibcon#about to write, iclass 4, count 0 2006.175.07:51:40.89#ibcon#wrote, iclass 4, count 0 2006.175.07:51:40.89#ibcon#about to read 3, iclass 4, count 0 2006.175.07:51:40.91#abcon#<5=/04 4.2 7.5 25.87 681007.3\r\n> 2006.175.07:51:40.92#ibcon#read 3, iclass 4, count 0 2006.175.07:51:40.92#ibcon#about to read 4, iclass 4, count 0 2006.175.07:51:40.92#ibcon#read 4, iclass 4, count 0 2006.175.07:51:40.92#ibcon#about to read 5, iclass 4, count 0 2006.175.07:51:40.92#ibcon#read 5, iclass 4, count 0 2006.175.07:51:40.92#ibcon#about to read 6, iclass 4, count 0 2006.175.07:51:40.92#ibcon#read 6, iclass 4, count 0 2006.175.07:51:40.92#ibcon#end of sib2, iclass 4, count 0 2006.175.07:51:40.92#ibcon#*after write, iclass 4, count 0 2006.175.07:51:40.92#ibcon#*before return 0, iclass 4, count 0 2006.175.07:51:40.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:51:40.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.175.07:51:40.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:51:40.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:51:40.92$vc4f8/vblo=1,632.99 2006.175.07:51:40.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.07:51:40.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.07:51:40.92#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:40.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:51:40.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:51:40.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:51:40.92#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:51:40.92#ibcon#first serial, iclass 11, count 0 2006.175.07:51:40.92#ibcon#enter sib2, iclass 11, count 0 2006.175.07:51:40.92#ibcon#flushed, iclass 11, count 0 2006.175.07:51:40.92#ibcon#about to write, iclass 11, count 0 2006.175.07:51:40.92#ibcon#wrote, iclass 11, count 0 2006.175.07:51:40.92#ibcon#about to read 3, iclass 11, count 0 2006.175.07:51:40.93#abcon#{5=INTERFACE CLEAR} 2006.175.07:51:40.94#ibcon#read 3, iclass 11, count 0 2006.175.07:51:40.94#ibcon#about to read 4, iclass 11, count 0 2006.175.07:51:40.94#ibcon#read 4, iclass 11, count 0 2006.175.07:51:40.94#ibcon#about to read 5, iclass 11, count 0 2006.175.07:51:40.94#ibcon#read 5, iclass 11, count 0 2006.175.07:51:40.94#ibcon#about to read 6, iclass 11, count 0 2006.175.07:51:40.94#ibcon#read 6, iclass 11, count 0 2006.175.07:51:40.94#ibcon#end of sib2, iclass 11, count 0 2006.175.07:51:40.94#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:51:40.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:51:40.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:51:40.94#ibcon#*before write, iclass 11, count 0 2006.175.07:51:40.94#ibcon#enter sib2, iclass 11, count 0 2006.175.07:51:40.94#ibcon#flushed, iclass 11, count 0 2006.175.07:51:40.94#ibcon#about to write, iclass 11, count 0 2006.175.07:51:40.94#ibcon#wrote, iclass 11, count 0 2006.175.07:51:40.94#ibcon#about to read 3, iclass 11, count 0 2006.175.07:51:40.98#ibcon#read 3, iclass 11, count 0 2006.175.07:51:40.98#ibcon#about to read 4, iclass 11, count 0 2006.175.07:51:40.98#ibcon#read 4, iclass 11, count 0 2006.175.07:51:40.98#ibcon#about to read 5, iclass 11, count 0 2006.175.07:51:40.98#ibcon#read 5, iclass 11, count 0 2006.175.07:51:40.98#ibcon#about to read 6, iclass 11, count 0 2006.175.07:51:40.98#ibcon#read 6, iclass 11, count 0 2006.175.07:51:40.98#ibcon#end of sib2, iclass 11, count 0 2006.175.07:51:40.98#ibcon#*after write, iclass 11, count 0 2006.175.07:51:40.98#ibcon#*before return 0, iclass 11, count 0 2006.175.07:51:40.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:51:40.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:51:40.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:51:40.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:51:40.98$vc4f8/vb=1,4 2006.175.07:51:40.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.07:51:40.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.07:51:40.98#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:40.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:40.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:40.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:40.98#ibcon#enter wrdev, iclass 14, count 2 2006.175.07:51:40.98#ibcon#first serial, iclass 14, count 2 2006.175.07:51:40.98#ibcon#enter sib2, iclass 14, count 2 2006.175.07:51:40.98#ibcon#flushed, iclass 14, count 2 2006.175.07:51:40.98#ibcon#about to write, iclass 14, count 2 2006.175.07:51:40.98#ibcon#wrote, iclass 14, count 2 2006.175.07:51:40.98#ibcon#about to read 3, iclass 14, count 2 2006.175.07:51:40.99#abcon#[5=S1D000X0/0*\r\n] 2006.175.07:51:41.00#ibcon#read 3, iclass 14, count 2 2006.175.07:51:41.00#ibcon#about to read 4, iclass 14, count 2 2006.175.07:51:41.00#ibcon#read 4, iclass 14, count 2 2006.175.07:51:41.00#ibcon#about to read 5, iclass 14, count 2 2006.175.07:51:41.00#ibcon#read 5, iclass 14, count 2 2006.175.07:51:41.00#ibcon#about to read 6, iclass 14, count 2 2006.175.07:51:41.00#ibcon#read 6, iclass 14, count 2 2006.175.07:51:41.00#ibcon#end of sib2, iclass 14, count 2 2006.175.07:51:41.00#ibcon#*mode == 0, iclass 14, count 2 2006.175.07:51:41.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.07:51:41.00#ibcon#[27=AT01-04\r\n] 2006.175.07:51:41.00#ibcon#*before write, iclass 14, count 2 2006.175.07:51:41.00#ibcon#enter sib2, iclass 14, count 2 2006.175.07:51:41.00#ibcon#flushed, iclass 14, count 2 2006.175.07:51:41.00#ibcon#about to write, iclass 14, count 2 2006.175.07:51:41.00#ibcon#wrote, iclass 14, count 2 2006.175.07:51:41.00#ibcon#about to read 3, iclass 14, count 2 2006.175.07:51:41.03#ibcon#read 3, iclass 14, count 2 2006.175.07:51:41.03#ibcon#about to read 4, iclass 14, count 2 2006.175.07:51:41.03#ibcon#read 4, iclass 14, count 2 2006.175.07:51:41.03#ibcon#about to read 5, iclass 14, count 2 2006.175.07:51:41.03#ibcon#read 5, iclass 14, count 2 2006.175.07:51:41.03#ibcon#about to read 6, iclass 14, count 2 2006.175.07:51:41.03#ibcon#read 6, iclass 14, count 2 2006.175.07:51:41.03#ibcon#end of sib2, iclass 14, count 2 2006.175.07:51:41.03#ibcon#*after write, iclass 14, count 2 2006.175.07:51:41.03#ibcon#*before return 0, iclass 14, count 2 2006.175.07:51:41.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:41.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.07:51:41.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.07:51:41.03#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:41.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:41.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:41.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:41.15#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:51:41.15#ibcon#first serial, iclass 14, count 0 2006.175.07:51:41.15#ibcon#enter sib2, iclass 14, count 0 2006.175.07:51:41.15#ibcon#flushed, iclass 14, count 0 2006.175.07:51:41.15#ibcon#about to write, iclass 14, count 0 2006.175.07:51:41.15#ibcon#wrote, iclass 14, count 0 2006.175.07:51:41.15#ibcon#about to read 3, iclass 14, count 0 2006.175.07:51:41.17#ibcon#read 3, iclass 14, count 0 2006.175.07:51:41.17#ibcon#about to read 4, iclass 14, count 0 2006.175.07:51:41.17#ibcon#read 4, iclass 14, count 0 2006.175.07:51:41.17#ibcon#about to read 5, iclass 14, count 0 2006.175.07:51:41.17#ibcon#read 5, iclass 14, count 0 2006.175.07:51:41.17#ibcon#about to read 6, iclass 14, count 0 2006.175.07:51:41.17#ibcon#read 6, iclass 14, count 0 2006.175.07:51:41.17#ibcon#end of sib2, iclass 14, count 0 2006.175.07:51:41.17#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:51:41.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:51:41.17#ibcon#[27=USB\r\n] 2006.175.07:51:41.17#ibcon#*before write, iclass 14, count 0 2006.175.07:51:41.17#ibcon#enter sib2, iclass 14, count 0 2006.175.07:51:41.17#ibcon#flushed, iclass 14, count 0 2006.175.07:51:41.17#ibcon#about to write, iclass 14, count 0 2006.175.07:51:41.17#ibcon#wrote, iclass 14, count 0 2006.175.07:51:41.17#ibcon#about to read 3, iclass 14, count 0 2006.175.07:51:41.20#ibcon#read 3, iclass 14, count 0 2006.175.07:51:41.20#ibcon#about to read 4, iclass 14, count 0 2006.175.07:51:41.20#ibcon#read 4, iclass 14, count 0 2006.175.07:51:41.20#ibcon#about to read 5, iclass 14, count 0 2006.175.07:51:41.20#ibcon#read 5, iclass 14, count 0 2006.175.07:51:41.20#ibcon#about to read 6, iclass 14, count 0 2006.175.07:51:41.20#ibcon#read 6, iclass 14, count 0 2006.175.07:51:41.20#ibcon#end of sib2, iclass 14, count 0 2006.175.07:51:41.20#ibcon#*after write, iclass 14, count 0 2006.175.07:51:41.20#ibcon#*before return 0, iclass 14, count 0 2006.175.07:51:41.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:41.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.07:51:41.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:51:41.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:51:41.20$vc4f8/vblo=2,640.99 2006.175.07:51:41.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.07:51:41.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.07:51:41.20#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:41.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:41.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:41.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:41.20#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:51:41.20#ibcon#first serial, iclass 16, count 0 2006.175.07:51:41.20#ibcon#enter sib2, iclass 16, count 0 2006.175.07:51:41.20#ibcon#flushed, iclass 16, count 0 2006.175.07:51:41.20#ibcon#about to write, iclass 16, count 0 2006.175.07:51:41.20#ibcon#wrote, iclass 16, count 0 2006.175.07:51:41.20#ibcon#about to read 3, iclass 16, count 0 2006.175.07:51:41.22#ibcon#read 3, iclass 16, count 0 2006.175.07:51:41.22#ibcon#about to read 4, iclass 16, count 0 2006.175.07:51:41.22#ibcon#read 4, iclass 16, count 0 2006.175.07:51:41.22#ibcon#about to read 5, iclass 16, count 0 2006.175.07:51:41.22#ibcon#read 5, iclass 16, count 0 2006.175.07:51:41.22#ibcon#about to read 6, iclass 16, count 0 2006.175.07:51:41.22#ibcon#read 6, iclass 16, count 0 2006.175.07:51:41.22#ibcon#end of sib2, iclass 16, count 0 2006.175.07:51:41.22#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:51:41.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:51:41.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:51:41.22#ibcon#*before write, iclass 16, count 0 2006.175.07:51:41.22#ibcon#enter sib2, iclass 16, count 0 2006.175.07:51:41.22#ibcon#flushed, iclass 16, count 0 2006.175.07:51:41.22#ibcon#about to write, iclass 16, count 0 2006.175.07:51:41.22#ibcon#wrote, iclass 16, count 0 2006.175.07:51:41.22#ibcon#about to read 3, iclass 16, count 0 2006.175.07:51:41.26#ibcon#read 3, iclass 16, count 0 2006.175.07:51:41.26#ibcon#about to read 4, iclass 16, count 0 2006.175.07:51:41.26#ibcon#read 4, iclass 16, count 0 2006.175.07:51:41.26#ibcon#about to read 5, iclass 16, count 0 2006.175.07:51:41.26#ibcon#read 5, iclass 16, count 0 2006.175.07:51:41.26#ibcon#about to read 6, iclass 16, count 0 2006.175.07:51:41.26#ibcon#read 6, iclass 16, count 0 2006.175.07:51:41.26#ibcon#end of sib2, iclass 16, count 0 2006.175.07:51:41.26#ibcon#*after write, iclass 16, count 0 2006.175.07:51:41.26#ibcon#*before return 0, iclass 16, count 0 2006.175.07:51:41.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:41.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.07:51:41.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:51:41.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:51:41.26$vc4f8/vb=2,4 2006.175.07:51:41.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.07:51:41.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.07:51:41.26#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:41.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:41.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:41.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:41.32#ibcon#enter wrdev, iclass 18, count 2 2006.175.07:51:41.32#ibcon#first serial, iclass 18, count 2 2006.175.07:51:41.32#ibcon#enter sib2, iclass 18, count 2 2006.175.07:51:41.32#ibcon#flushed, iclass 18, count 2 2006.175.07:51:41.32#ibcon#about to write, iclass 18, count 2 2006.175.07:51:41.32#ibcon#wrote, iclass 18, count 2 2006.175.07:51:41.32#ibcon#about to read 3, iclass 18, count 2 2006.175.07:51:41.34#ibcon#read 3, iclass 18, count 2 2006.175.07:51:41.34#ibcon#about to read 4, iclass 18, count 2 2006.175.07:51:41.34#ibcon#read 4, iclass 18, count 2 2006.175.07:51:41.34#ibcon#about to read 5, iclass 18, count 2 2006.175.07:51:41.34#ibcon#read 5, iclass 18, count 2 2006.175.07:51:41.34#ibcon#about to read 6, iclass 18, count 2 2006.175.07:51:41.34#ibcon#read 6, iclass 18, count 2 2006.175.07:51:41.34#ibcon#end of sib2, iclass 18, count 2 2006.175.07:51:41.34#ibcon#*mode == 0, iclass 18, count 2 2006.175.07:51:41.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.07:51:41.34#ibcon#[27=AT02-04\r\n] 2006.175.07:51:41.34#ibcon#*before write, iclass 18, count 2 2006.175.07:51:41.34#ibcon#enter sib2, iclass 18, count 2 2006.175.07:51:41.34#ibcon#flushed, iclass 18, count 2 2006.175.07:51:41.34#ibcon#about to write, iclass 18, count 2 2006.175.07:51:41.34#ibcon#wrote, iclass 18, count 2 2006.175.07:51:41.34#ibcon#about to read 3, iclass 18, count 2 2006.175.07:51:41.37#ibcon#read 3, iclass 18, count 2 2006.175.07:51:41.37#ibcon#about to read 4, iclass 18, count 2 2006.175.07:51:41.37#ibcon#read 4, iclass 18, count 2 2006.175.07:51:41.37#ibcon#about to read 5, iclass 18, count 2 2006.175.07:51:41.37#ibcon#read 5, iclass 18, count 2 2006.175.07:51:41.37#ibcon#about to read 6, iclass 18, count 2 2006.175.07:51:41.37#ibcon#read 6, iclass 18, count 2 2006.175.07:51:41.37#ibcon#end of sib2, iclass 18, count 2 2006.175.07:51:41.37#ibcon#*after write, iclass 18, count 2 2006.175.07:51:41.37#ibcon#*before return 0, iclass 18, count 2 2006.175.07:51:41.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:41.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:51:41.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.07:51:41.37#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:41.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:41.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:41.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:41.49#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:51:41.49#ibcon#first serial, iclass 18, count 0 2006.175.07:51:41.49#ibcon#enter sib2, iclass 18, count 0 2006.175.07:51:41.49#ibcon#flushed, iclass 18, count 0 2006.175.07:51:41.49#ibcon#about to write, iclass 18, count 0 2006.175.07:51:41.49#ibcon#wrote, iclass 18, count 0 2006.175.07:51:41.49#ibcon#about to read 3, iclass 18, count 0 2006.175.07:51:41.51#ibcon#read 3, iclass 18, count 0 2006.175.07:51:41.51#ibcon#about to read 4, iclass 18, count 0 2006.175.07:51:41.51#ibcon#read 4, iclass 18, count 0 2006.175.07:51:41.51#ibcon#about to read 5, iclass 18, count 0 2006.175.07:51:41.51#ibcon#read 5, iclass 18, count 0 2006.175.07:51:41.51#ibcon#about to read 6, iclass 18, count 0 2006.175.07:51:41.51#ibcon#read 6, iclass 18, count 0 2006.175.07:51:41.51#ibcon#end of sib2, iclass 18, count 0 2006.175.07:51:41.51#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:51:41.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:51:41.51#ibcon#[27=USB\r\n] 2006.175.07:51:41.51#ibcon#*before write, iclass 18, count 0 2006.175.07:51:41.51#ibcon#enter sib2, iclass 18, count 0 2006.175.07:51:41.51#ibcon#flushed, iclass 18, count 0 2006.175.07:51:41.51#ibcon#about to write, iclass 18, count 0 2006.175.07:51:41.51#ibcon#wrote, iclass 18, count 0 2006.175.07:51:41.51#ibcon#about to read 3, iclass 18, count 0 2006.175.07:51:41.54#ibcon#read 3, iclass 18, count 0 2006.175.07:51:41.54#ibcon#about to read 4, iclass 18, count 0 2006.175.07:51:41.54#ibcon#read 4, iclass 18, count 0 2006.175.07:51:41.54#ibcon#about to read 5, iclass 18, count 0 2006.175.07:51:41.54#ibcon#read 5, iclass 18, count 0 2006.175.07:51:41.54#ibcon#about to read 6, iclass 18, count 0 2006.175.07:51:41.54#ibcon#read 6, iclass 18, count 0 2006.175.07:51:41.54#ibcon#end of sib2, iclass 18, count 0 2006.175.07:51:41.54#ibcon#*after write, iclass 18, count 0 2006.175.07:51:41.54#ibcon#*before return 0, iclass 18, count 0 2006.175.07:51:41.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:41.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:51:41.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:51:41.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:51:41.54$vc4f8/vblo=3,656.99 2006.175.07:51:41.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.07:51:41.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.07:51:41.54#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:41.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:41.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:41.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:41.54#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:51:41.54#ibcon#first serial, iclass 20, count 0 2006.175.07:51:41.54#ibcon#enter sib2, iclass 20, count 0 2006.175.07:51:41.54#ibcon#flushed, iclass 20, count 0 2006.175.07:51:41.54#ibcon#about to write, iclass 20, count 0 2006.175.07:51:41.54#ibcon#wrote, iclass 20, count 0 2006.175.07:51:41.54#ibcon#about to read 3, iclass 20, count 0 2006.175.07:51:41.56#ibcon#read 3, iclass 20, count 0 2006.175.07:51:41.56#ibcon#about to read 4, iclass 20, count 0 2006.175.07:51:41.56#ibcon#read 4, iclass 20, count 0 2006.175.07:51:41.56#ibcon#about to read 5, iclass 20, count 0 2006.175.07:51:41.56#ibcon#read 5, iclass 20, count 0 2006.175.07:51:41.56#ibcon#about to read 6, iclass 20, count 0 2006.175.07:51:41.56#ibcon#read 6, iclass 20, count 0 2006.175.07:51:41.56#ibcon#end of sib2, iclass 20, count 0 2006.175.07:51:41.56#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:51:41.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:51:41.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:51:41.56#ibcon#*before write, iclass 20, count 0 2006.175.07:51:41.56#ibcon#enter sib2, iclass 20, count 0 2006.175.07:51:41.56#ibcon#flushed, iclass 20, count 0 2006.175.07:51:41.56#ibcon#about to write, iclass 20, count 0 2006.175.07:51:41.56#ibcon#wrote, iclass 20, count 0 2006.175.07:51:41.56#ibcon#about to read 3, iclass 20, count 0 2006.175.07:51:41.60#ibcon#read 3, iclass 20, count 0 2006.175.07:51:41.60#ibcon#about to read 4, iclass 20, count 0 2006.175.07:51:41.60#ibcon#read 4, iclass 20, count 0 2006.175.07:51:41.60#ibcon#about to read 5, iclass 20, count 0 2006.175.07:51:41.60#ibcon#read 5, iclass 20, count 0 2006.175.07:51:41.60#ibcon#about to read 6, iclass 20, count 0 2006.175.07:51:41.60#ibcon#read 6, iclass 20, count 0 2006.175.07:51:41.60#ibcon#end of sib2, iclass 20, count 0 2006.175.07:51:41.60#ibcon#*after write, iclass 20, count 0 2006.175.07:51:41.60#ibcon#*before return 0, iclass 20, count 0 2006.175.07:51:41.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:41.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:51:41.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:51:41.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:51:41.60$vc4f8/vb=3,4 2006.175.07:51:41.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.07:51:41.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.07:51:41.60#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:41.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:41.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:41.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:41.66#ibcon#enter wrdev, iclass 22, count 2 2006.175.07:51:41.66#ibcon#first serial, iclass 22, count 2 2006.175.07:51:41.66#ibcon#enter sib2, iclass 22, count 2 2006.175.07:51:41.66#ibcon#flushed, iclass 22, count 2 2006.175.07:51:41.66#ibcon#about to write, iclass 22, count 2 2006.175.07:51:41.66#ibcon#wrote, iclass 22, count 2 2006.175.07:51:41.66#ibcon#about to read 3, iclass 22, count 2 2006.175.07:51:41.68#ibcon#read 3, iclass 22, count 2 2006.175.07:51:41.68#ibcon#about to read 4, iclass 22, count 2 2006.175.07:51:41.68#ibcon#read 4, iclass 22, count 2 2006.175.07:51:41.68#ibcon#about to read 5, iclass 22, count 2 2006.175.07:51:41.68#ibcon#read 5, iclass 22, count 2 2006.175.07:51:41.68#ibcon#about to read 6, iclass 22, count 2 2006.175.07:51:41.68#ibcon#read 6, iclass 22, count 2 2006.175.07:51:41.68#ibcon#end of sib2, iclass 22, count 2 2006.175.07:51:41.68#ibcon#*mode == 0, iclass 22, count 2 2006.175.07:51:41.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.07:51:41.68#ibcon#[27=AT03-04\r\n] 2006.175.07:51:41.68#ibcon#*before write, iclass 22, count 2 2006.175.07:51:41.68#ibcon#enter sib2, iclass 22, count 2 2006.175.07:51:41.68#ibcon#flushed, iclass 22, count 2 2006.175.07:51:41.68#ibcon#about to write, iclass 22, count 2 2006.175.07:51:41.68#ibcon#wrote, iclass 22, count 2 2006.175.07:51:41.68#ibcon#about to read 3, iclass 22, count 2 2006.175.07:51:41.71#ibcon#read 3, iclass 22, count 2 2006.175.07:51:41.71#ibcon#about to read 4, iclass 22, count 2 2006.175.07:51:41.71#ibcon#read 4, iclass 22, count 2 2006.175.07:51:41.71#ibcon#about to read 5, iclass 22, count 2 2006.175.07:51:41.71#ibcon#read 5, iclass 22, count 2 2006.175.07:51:41.71#ibcon#about to read 6, iclass 22, count 2 2006.175.07:51:41.71#ibcon#read 6, iclass 22, count 2 2006.175.07:51:41.71#ibcon#end of sib2, iclass 22, count 2 2006.175.07:51:41.71#ibcon#*after write, iclass 22, count 2 2006.175.07:51:41.71#ibcon#*before return 0, iclass 22, count 2 2006.175.07:51:41.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:41.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.07:51:41.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.07:51:41.71#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:41.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:41.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:41.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:41.83#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:51:41.83#ibcon#first serial, iclass 22, count 0 2006.175.07:51:41.83#ibcon#enter sib2, iclass 22, count 0 2006.175.07:51:41.83#ibcon#flushed, iclass 22, count 0 2006.175.07:51:41.83#ibcon#about to write, iclass 22, count 0 2006.175.07:51:41.83#ibcon#wrote, iclass 22, count 0 2006.175.07:51:41.83#ibcon#about to read 3, iclass 22, count 0 2006.175.07:51:41.85#ibcon#read 3, iclass 22, count 0 2006.175.07:51:41.85#ibcon#about to read 4, iclass 22, count 0 2006.175.07:51:41.85#ibcon#read 4, iclass 22, count 0 2006.175.07:51:41.85#ibcon#about to read 5, iclass 22, count 0 2006.175.07:51:41.85#ibcon#read 5, iclass 22, count 0 2006.175.07:51:41.85#ibcon#about to read 6, iclass 22, count 0 2006.175.07:51:41.85#ibcon#read 6, iclass 22, count 0 2006.175.07:51:41.85#ibcon#end of sib2, iclass 22, count 0 2006.175.07:51:41.85#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:51:41.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:51:41.85#ibcon#[27=USB\r\n] 2006.175.07:51:41.85#ibcon#*before write, iclass 22, count 0 2006.175.07:51:41.85#ibcon#enter sib2, iclass 22, count 0 2006.175.07:51:41.85#ibcon#flushed, iclass 22, count 0 2006.175.07:51:41.85#ibcon#about to write, iclass 22, count 0 2006.175.07:51:41.85#ibcon#wrote, iclass 22, count 0 2006.175.07:51:41.85#ibcon#about to read 3, iclass 22, count 0 2006.175.07:51:41.88#ibcon#read 3, iclass 22, count 0 2006.175.07:51:41.88#ibcon#about to read 4, iclass 22, count 0 2006.175.07:51:41.88#ibcon#read 4, iclass 22, count 0 2006.175.07:51:41.88#ibcon#about to read 5, iclass 22, count 0 2006.175.07:51:41.88#ibcon#read 5, iclass 22, count 0 2006.175.07:51:41.88#ibcon#about to read 6, iclass 22, count 0 2006.175.07:51:41.88#ibcon#read 6, iclass 22, count 0 2006.175.07:51:41.88#ibcon#end of sib2, iclass 22, count 0 2006.175.07:51:41.88#ibcon#*after write, iclass 22, count 0 2006.175.07:51:41.88#ibcon#*before return 0, iclass 22, count 0 2006.175.07:51:41.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:41.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.07:51:41.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:51:41.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:51:41.88$vc4f8/vblo=4,712.99 2006.175.07:51:41.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.07:51:41.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.07:51:41.88#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:41.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:41.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:41.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:41.88#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:51:41.88#ibcon#first serial, iclass 24, count 0 2006.175.07:51:41.88#ibcon#enter sib2, iclass 24, count 0 2006.175.07:51:41.88#ibcon#flushed, iclass 24, count 0 2006.175.07:51:41.88#ibcon#about to write, iclass 24, count 0 2006.175.07:51:41.88#ibcon#wrote, iclass 24, count 0 2006.175.07:51:41.88#ibcon#about to read 3, iclass 24, count 0 2006.175.07:51:41.90#ibcon#read 3, iclass 24, count 0 2006.175.07:51:41.90#ibcon#about to read 4, iclass 24, count 0 2006.175.07:51:41.90#ibcon#read 4, iclass 24, count 0 2006.175.07:51:41.90#ibcon#about to read 5, iclass 24, count 0 2006.175.07:51:41.90#ibcon#read 5, iclass 24, count 0 2006.175.07:51:41.90#ibcon#about to read 6, iclass 24, count 0 2006.175.07:51:41.90#ibcon#read 6, iclass 24, count 0 2006.175.07:51:41.90#ibcon#end of sib2, iclass 24, count 0 2006.175.07:51:41.90#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:51:41.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:51:41.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:51:41.90#ibcon#*before write, iclass 24, count 0 2006.175.07:51:41.90#ibcon#enter sib2, iclass 24, count 0 2006.175.07:51:41.90#ibcon#flushed, iclass 24, count 0 2006.175.07:51:41.90#ibcon#about to write, iclass 24, count 0 2006.175.07:51:41.90#ibcon#wrote, iclass 24, count 0 2006.175.07:51:41.90#ibcon#about to read 3, iclass 24, count 0 2006.175.07:51:41.94#ibcon#read 3, iclass 24, count 0 2006.175.07:51:41.94#ibcon#about to read 4, iclass 24, count 0 2006.175.07:51:41.94#ibcon#read 4, iclass 24, count 0 2006.175.07:51:41.94#ibcon#about to read 5, iclass 24, count 0 2006.175.07:51:41.94#ibcon#read 5, iclass 24, count 0 2006.175.07:51:41.94#ibcon#about to read 6, iclass 24, count 0 2006.175.07:51:41.94#ibcon#read 6, iclass 24, count 0 2006.175.07:51:41.94#ibcon#end of sib2, iclass 24, count 0 2006.175.07:51:41.94#ibcon#*after write, iclass 24, count 0 2006.175.07:51:41.94#ibcon#*before return 0, iclass 24, count 0 2006.175.07:51:41.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:41.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.07:51:41.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:51:41.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:51:41.94$vc4f8/vb=4,4 2006.175.07:51:41.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.07:51:41.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.07:51:41.94#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:41.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:42.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:42.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:42.00#ibcon#enter wrdev, iclass 26, count 2 2006.175.07:51:42.00#ibcon#first serial, iclass 26, count 2 2006.175.07:51:42.00#ibcon#enter sib2, iclass 26, count 2 2006.175.07:51:42.00#ibcon#flushed, iclass 26, count 2 2006.175.07:51:42.00#ibcon#about to write, iclass 26, count 2 2006.175.07:51:42.00#ibcon#wrote, iclass 26, count 2 2006.175.07:51:42.00#ibcon#about to read 3, iclass 26, count 2 2006.175.07:51:42.02#ibcon#read 3, iclass 26, count 2 2006.175.07:51:42.02#ibcon#about to read 4, iclass 26, count 2 2006.175.07:51:42.02#ibcon#read 4, iclass 26, count 2 2006.175.07:51:42.02#ibcon#about to read 5, iclass 26, count 2 2006.175.07:51:42.02#ibcon#read 5, iclass 26, count 2 2006.175.07:51:42.02#ibcon#about to read 6, iclass 26, count 2 2006.175.07:51:42.02#ibcon#read 6, iclass 26, count 2 2006.175.07:51:42.02#ibcon#end of sib2, iclass 26, count 2 2006.175.07:51:42.02#ibcon#*mode == 0, iclass 26, count 2 2006.175.07:51:42.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.07:51:42.02#ibcon#[27=AT04-04\r\n] 2006.175.07:51:42.02#ibcon#*before write, iclass 26, count 2 2006.175.07:51:42.02#ibcon#enter sib2, iclass 26, count 2 2006.175.07:51:42.02#ibcon#flushed, iclass 26, count 2 2006.175.07:51:42.02#ibcon#about to write, iclass 26, count 2 2006.175.07:51:42.02#ibcon#wrote, iclass 26, count 2 2006.175.07:51:42.02#ibcon#about to read 3, iclass 26, count 2 2006.175.07:51:42.05#ibcon#read 3, iclass 26, count 2 2006.175.07:51:42.05#ibcon#about to read 4, iclass 26, count 2 2006.175.07:51:42.05#ibcon#read 4, iclass 26, count 2 2006.175.07:51:42.05#ibcon#about to read 5, iclass 26, count 2 2006.175.07:51:42.05#ibcon#read 5, iclass 26, count 2 2006.175.07:51:42.05#ibcon#about to read 6, iclass 26, count 2 2006.175.07:51:42.05#ibcon#read 6, iclass 26, count 2 2006.175.07:51:42.05#ibcon#end of sib2, iclass 26, count 2 2006.175.07:51:42.05#ibcon#*after write, iclass 26, count 2 2006.175.07:51:42.05#ibcon#*before return 0, iclass 26, count 2 2006.175.07:51:42.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:42.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.07:51:42.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.07:51:42.05#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:42.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:42.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:42.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:42.17#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:51:42.17#ibcon#first serial, iclass 26, count 0 2006.175.07:51:42.17#ibcon#enter sib2, iclass 26, count 0 2006.175.07:51:42.17#ibcon#flushed, iclass 26, count 0 2006.175.07:51:42.17#ibcon#about to write, iclass 26, count 0 2006.175.07:51:42.17#ibcon#wrote, iclass 26, count 0 2006.175.07:51:42.17#ibcon#about to read 3, iclass 26, count 0 2006.175.07:51:42.19#ibcon#read 3, iclass 26, count 0 2006.175.07:51:42.19#ibcon#about to read 4, iclass 26, count 0 2006.175.07:51:42.19#ibcon#read 4, iclass 26, count 0 2006.175.07:51:42.19#ibcon#about to read 5, iclass 26, count 0 2006.175.07:51:42.19#ibcon#read 5, iclass 26, count 0 2006.175.07:51:42.19#ibcon#about to read 6, iclass 26, count 0 2006.175.07:51:42.19#ibcon#read 6, iclass 26, count 0 2006.175.07:51:42.19#ibcon#end of sib2, iclass 26, count 0 2006.175.07:51:42.19#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:51:42.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:51:42.19#ibcon#[27=USB\r\n] 2006.175.07:51:42.19#ibcon#*before write, iclass 26, count 0 2006.175.07:51:42.19#ibcon#enter sib2, iclass 26, count 0 2006.175.07:51:42.19#ibcon#flushed, iclass 26, count 0 2006.175.07:51:42.19#ibcon#about to write, iclass 26, count 0 2006.175.07:51:42.19#ibcon#wrote, iclass 26, count 0 2006.175.07:51:42.19#ibcon#about to read 3, iclass 26, count 0 2006.175.07:51:42.22#ibcon#read 3, iclass 26, count 0 2006.175.07:51:42.22#ibcon#about to read 4, iclass 26, count 0 2006.175.07:51:42.22#ibcon#read 4, iclass 26, count 0 2006.175.07:51:42.22#ibcon#about to read 5, iclass 26, count 0 2006.175.07:51:42.22#ibcon#read 5, iclass 26, count 0 2006.175.07:51:42.22#ibcon#about to read 6, iclass 26, count 0 2006.175.07:51:42.22#ibcon#read 6, iclass 26, count 0 2006.175.07:51:42.22#ibcon#end of sib2, iclass 26, count 0 2006.175.07:51:42.22#ibcon#*after write, iclass 26, count 0 2006.175.07:51:42.22#ibcon#*before return 0, iclass 26, count 0 2006.175.07:51:42.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:42.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.07:51:42.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:51:42.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:51:42.22$vc4f8/vblo=5,744.99 2006.175.07:51:42.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.07:51:42.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.07:51:42.22#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:42.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:42.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:42.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:42.22#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:51:42.22#ibcon#first serial, iclass 28, count 0 2006.175.07:51:42.22#ibcon#enter sib2, iclass 28, count 0 2006.175.07:51:42.22#ibcon#flushed, iclass 28, count 0 2006.175.07:51:42.22#ibcon#about to write, iclass 28, count 0 2006.175.07:51:42.22#ibcon#wrote, iclass 28, count 0 2006.175.07:51:42.22#ibcon#about to read 3, iclass 28, count 0 2006.175.07:51:42.24#ibcon#read 3, iclass 28, count 0 2006.175.07:51:42.24#ibcon#about to read 4, iclass 28, count 0 2006.175.07:51:42.24#ibcon#read 4, iclass 28, count 0 2006.175.07:51:42.24#ibcon#about to read 5, iclass 28, count 0 2006.175.07:51:42.24#ibcon#read 5, iclass 28, count 0 2006.175.07:51:42.24#ibcon#about to read 6, iclass 28, count 0 2006.175.07:51:42.24#ibcon#read 6, iclass 28, count 0 2006.175.07:51:42.24#ibcon#end of sib2, iclass 28, count 0 2006.175.07:51:42.24#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:51:42.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:51:42.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:51:42.24#ibcon#*before write, iclass 28, count 0 2006.175.07:51:42.24#ibcon#enter sib2, iclass 28, count 0 2006.175.07:51:42.24#ibcon#flushed, iclass 28, count 0 2006.175.07:51:42.24#ibcon#about to write, iclass 28, count 0 2006.175.07:51:42.24#ibcon#wrote, iclass 28, count 0 2006.175.07:51:42.24#ibcon#about to read 3, iclass 28, count 0 2006.175.07:51:42.28#ibcon#read 3, iclass 28, count 0 2006.175.07:51:42.28#ibcon#about to read 4, iclass 28, count 0 2006.175.07:51:42.28#ibcon#read 4, iclass 28, count 0 2006.175.07:51:42.28#ibcon#about to read 5, iclass 28, count 0 2006.175.07:51:42.28#ibcon#read 5, iclass 28, count 0 2006.175.07:51:42.28#ibcon#about to read 6, iclass 28, count 0 2006.175.07:51:42.28#ibcon#read 6, iclass 28, count 0 2006.175.07:51:42.28#ibcon#end of sib2, iclass 28, count 0 2006.175.07:51:42.28#ibcon#*after write, iclass 28, count 0 2006.175.07:51:42.28#ibcon#*before return 0, iclass 28, count 0 2006.175.07:51:42.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:42.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.07:51:42.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:51:42.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:51:42.28$vc4f8/vb=5,4 2006.175.07:51:42.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.07:51:42.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.07:51:42.28#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:42.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:42.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:42.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:42.34#ibcon#enter wrdev, iclass 30, count 2 2006.175.07:51:42.34#ibcon#first serial, iclass 30, count 2 2006.175.07:51:42.34#ibcon#enter sib2, iclass 30, count 2 2006.175.07:51:42.34#ibcon#flushed, iclass 30, count 2 2006.175.07:51:42.34#ibcon#about to write, iclass 30, count 2 2006.175.07:51:42.34#ibcon#wrote, iclass 30, count 2 2006.175.07:51:42.34#ibcon#about to read 3, iclass 30, count 2 2006.175.07:51:42.36#ibcon#read 3, iclass 30, count 2 2006.175.07:51:42.36#ibcon#about to read 4, iclass 30, count 2 2006.175.07:51:42.36#ibcon#read 4, iclass 30, count 2 2006.175.07:51:42.36#ibcon#about to read 5, iclass 30, count 2 2006.175.07:51:42.36#ibcon#read 5, iclass 30, count 2 2006.175.07:51:42.36#ibcon#about to read 6, iclass 30, count 2 2006.175.07:51:42.36#ibcon#read 6, iclass 30, count 2 2006.175.07:51:42.36#ibcon#end of sib2, iclass 30, count 2 2006.175.07:51:42.36#ibcon#*mode == 0, iclass 30, count 2 2006.175.07:51:42.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.07:51:42.36#ibcon#[27=AT05-04\r\n] 2006.175.07:51:42.36#ibcon#*before write, iclass 30, count 2 2006.175.07:51:42.36#ibcon#enter sib2, iclass 30, count 2 2006.175.07:51:42.36#ibcon#flushed, iclass 30, count 2 2006.175.07:51:42.36#ibcon#about to write, iclass 30, count 2 2006.175.07:51:42.36#ibcon#wrote, iclass 30, count 2 2006.175.07:51:42.36#ibcon#about to read 3, iclass 30, count 2 2006.175.07:51:42.39#ibcon#read 3, iclass 30, count 2 2006.175.07:51:42.39#ibcon#about to read 4, iclass 30, count 2 2006.175.07:51:42.39#ibcon#read 4, iclass 30, count 2 2006.175.07:51:42.39#ibcon#about to read 5, iclass 30, count 2 2006.175.07:51:42.39#ibcon#read 5, iclass 30, count 2 2006.175.07:51:42.39#ibcon#about to read 6, iclass 30, count 2 2006.175.07:51:42.39#ibcon#read 6, iclass 30, count 2 2006.175.07:51:42.39#ibcon#end of sib2, iclass 30, count 2 2006.175.07:51:42.39#ibcon#*after write, iclass 30, count 2 2006.175.07:51:42.39#ibcon#*before return 0, iclass 30, count 2 2006.175.07:51:42.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:42.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.07:51:42.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.07:51:42.39#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:42.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:42.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:42.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:42.51#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:51:42.51#ibcon#first serial, iclass 30, count 0 2006.175.07:51:42.51#ibcon#enter sib2, iclass 30, count 0 2006.175.07:51:42.51#ibcon#flushed, iclass 30, count 0 2006.175.07:51:42.51#ibcon#about to write, iclass 30, count 0 2006.175.07:51:42.51#ibcon#wrote, iclass 30, count 0 2006.175.07:51:42.51#ibcon#about to read 3, iclass 30, count 0 2006.175.07:51:42.53#ibcon#read 3, iclass 30, count 0 2006.175.07:51:42.53#ibcon#about to read 4, iclass 30, count 0 2006.175.07:51:42.53#ibcon#read 4, iclass 30, count 0 2006.175.07:51:42.53#ibcon#about to read 5, iclass 30, count 0 2006.175.07:51:42.53#ibcon#read 5, iclass 30, count 0 2006.175.07:51:42.53#ibcon#about to read 6, iclass 30, count 0 2006.175.07:51:42.53#ibcon#read 6, iclass 30, count 0 2006.175.07:51:42.53#ibcon#end of sib2, iclass 30, count 0 2006.175.07:51:42.53#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:51:42.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:51:42.53#ibcon#[27=USB\r\n] 2006.175.07:51:42.53#ibcon#*before write, iclass 30, count 0 2006.175.07:51:42.53#ibcon#enter sib2, iclass 30, count 0 2006.175.07:51:42.53#ibcon#flushed, iclass 30, count 0 2006.175.07:51:42.53#ibcon#about to write, iclass 30, count 0 2006.175.07:51:42.53#ibcon#wrote, iclass 30, count 0 2006.175.07:51:42.53#ibcon#about to read 3, iclass 30, count 0 2006.175.07:51:42.56#ibcon#read 3, iclass 30, count 0 2006.175.07:51:42.56#ibcon#about to read 4, iclass 30, count 0 2006.175.07:51:42.56#ibcon#read 4, iclass 30, count 0 2006.175.07:51:42.56#ibcon#about to read 5, iclass 30, count 0 2006.175.07:51:42.56#ibcon#read 5, iclass 30, count 0 2006.175.07:51:42.56#ibcon#about to read 6, iclass 30, count 0 2006.175.07:51:42.56#ibcon#read 6, iclass 30, count 0 2006.175.07:51:42.56#ibcon#end of sib2, iclass 30, count 0 2006.175.07:51:42.56#ibcon#*after write, iclass 30, count 0 2006.175.07:51:42.56#ibcon#*before return 0, iclass 30, count 0 2006.175.07:51:42.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:42.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.07:51:42.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:51:42.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:51:42.56$vc4f8/vblo=6,752.99 2006.175.07:51:42.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.07:51:42.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.07:51:42.56#ibcon#ireg 17 cls_cnt 0 2006.175.07:51:42.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:42.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:42.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:42.56#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:51:42.56#ibcon#first serial, iclass 32, count 0 2006.175.07:51:42.56#ibcon#enter sib2, iclass 32, count 0 2006.175.07:51:42.56#ibcon#flushed, iclass 32, count 0 2006.175.07:51:42.56#ibcon#about to write, iclass 32, count 0 2006.175.07:51:42.56#ibcon#wrote, iclass 32, count 0 2006.175.07:51:42.56#ibcon#about to read 3, iclass 32, count 0 2006.175.07:51:42.58#ibcon#read 3, iclass 32, count 0 2006.175.07:51:42.58#ibcon#about to read 4, iclass 32, count 0 2006.175.07:51:42.58#ibcon#read 4, iclass 32, count 0 2006.175.07:51:42.58#ibcon#about to read 5, iclass 32, count 0 2006.175.07:51:42.58#ibcon#read 5, iclass 32, count 0 2006.175.07:51:42.58#ibcon#about to read 6, iclass 32, count 0 2006.175.07:51:42.58#ibcon#read 6, iclass 32, count 0 2006.175.07:51:42.58#ibcon#end of sib2, iclass 32, count 0 2006.175.07:51:42.58#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:51:42.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:51:42.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:51:42.58#ibcon#*before write, iclass 32, count 0 2006.175.07:51:42.58#ibcon#enter sib2, iclass 32, count 0 2006.175.07:51:42.58#ibcon#flushed, iclass 32, count 0 2006.175.07:51:42.58#ibcon#about to write, iclass 32, count 0 2006.175.07:51:42.58#ibcon#wrote, iclass 32, count 0 2006.175.07:51:42.58#ibcon#about to read 3, iclass 32, count 0 2006.175.07:51:42.62#ibcon#read 3, iclass 32, count 0 2006.175.07:51:42.62#ibcon#about to read 4, iclass 32, count 0 2006.175.07:51:42.62#ibcon#read 4, iclass 32, count 0 2006.175.07:51:42.62#ibcon#about to read 5, iclass 32, count 0 2006.175.07:51:42.62#ibcon#read 5, iclass 32, count 0 2006.175.07:51:42.62#ibcon#about to read 6, iclass 32, count 0 2006.175.07:51:42.62#ibcon#read 6, iclass 32, count 0 2006.175.07:51:42.62#ibcon#end of sib2, iclass 32, count 0 2006.175.07:51:42.62#ibcon#*after write, iclass 32, count 0 2006.175.07:51:42.62#ibcon#*before return 0, iclass 32, count 0 2006.175.07:51:42.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:42.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.07:51:42.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:51:42.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:51:42.62$vc4f8/vb=6,4 2006.175.07:51:42.62#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.175.07:51:42.62#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.175.07:51:42.62#ibcon#ireg 11 cls_cnt 2 2006.175.07:51:42.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:42.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:42.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:42.68#ibcon#enter wrdev, iclass 34, count 2 2006.175.07:51:42.68#ibcon#first serial, iclass 34, count 2 2006.175.07:51:42.68#ibcon#enter sib2, iclass 34, count 2 2006.175.07:51:42.68#ibcon#flushed, iclass 34, count 2 2006.175.07:51:42.68#ibcon#about to write, iclass 34, count 2 2006.175.07:51:42.68#ibcon#wrote, iclass 34, count 2 2006.175.07:51:42.68#ibcon#about to read 3, iclass 34, count 2 2006.175.07:51:42.70#ibcon#read 3, iclass 34, count 2 2006.175.07:51:42.70#ibcon#about to read 4, iclass 34, count 2 2006.175.07:51:42.70#ibcon#read 4, iclass 34, count 2 2006.175.07:51:42.70#ibcon#about to read 5, iclass 34, count 2 2006.175.07:51:42.70#ibcon#read 5, iclass 34, count 2 2006.175.07:51:42.70#ibcon#about to read 6, iclass 34, count 2 2006.175.07:51:42.70#ibcon#read 6, iclass 34, count 2 2006.175.07:51:42.70#ibcon#end of sib2, iclass 34, count 2 2006.175.07:51:42.70#ibcon#*mode == 0, iclass 34, count 2 2006.175.07:51:42.70#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.175.07:51:42.70#ibcon#[27=AT06-04\r\n] 2006.175.07:51:42.70#ibcon#*before write, iclass 34, count 2 2006.175.07:51:42.70#ibcon#enter sib2, iclass 34, count 2 2006.175.07:51:42.70#ibcon#flushed, iclass 34, count 2 2006.175.07:51:42.70#ibcon#about to write, iclass 34, count 2 2006.175.07:51:42.70#ibcon#wrote, iclass 34, count 2 2006.175.07:51:42.70#ibcon#about to read 3, iclass 34, count 2 2006.175.07:51:42.73#ibcon#read 3, iclass 34, count 2 2006.175.07:51:42.73#ibcon#about to read 4, iclass 34, count 2 2006.175.07:51:42.73#ibcon#read 4, iclass 34, count 2 2006.175.07:51:42.73#ibcon#about to read 5, iclass 34, count 2 2006.175.07:51:42.73#ibcon#read 5, iclass 34, count 2 2006.175.07:51:42.73#ibcon#about to read 6, iclass 34, count 2 2006.175.07:51:42.73#ibcon#read 6, iclass 34, count 2 2006.175.07:51:42.73#ibcon#end of sib2, iclass 34, count 2 2006.175.07:51:42.73#ibcon#*after write, iclass 34, count 2 2006.175.07:51:42.73#ibcon#*before return 0, iclass 34, count 2 2006.175.07:51:42.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:42.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.175.07:51:42.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.175.07:51:42.73#ibcon#ireg 7 cls_cnt 0 2006.175.07:51:42.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:42.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:42.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:42.85#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:51:42.85#ibcon#first serial, iclass 34, count 0 2006.175.07:51:42.85#ibcon#enter sib2, iclass 34, count 0 2006.175.07:51:42.85#ibcon#flushed, iclass 34, count 0 2006.175.07:51:42.85#ibcon#about to write, iclass 34, count 0 2006.175.07:51:42.85#ibcon#wrote, iclass 34, count 0 2006.175.07:51:42.85#ibcon#about to read 3, iclass 34, count 0 2006.175.07:51:42.87#ibcon#read 3, iclass 34, count 0 2006.175.07:51:42.87#ibcon#about to read 4, iclass 34, count 0 2006.175.07:51:42.87#ibcon#read 4, iclass 34, count 0 2006.175.07:51:42.87#ibcon#about to read 5, iclass 34, count 0 2006.175.07:51:42.87#ibcon#read 5, iclass 34, count 0 2006.175.07:51:42.87#ibcon#about to read 6, iclass 34, count 0 2006.175.07:51:42.87#ibcon#read 6, iclass 34, count 0 2006.175.07:51:42.87#ibcon#end of sib2, iclass 34, count 0 2006.175.07:51:42.87#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:51:42.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:51:42.87#ibcon#[27=USB\r\n] 2006.175.07:51:42.87#ibcon#*before write, iclass 34, count 0 2006.175.07:51:42.87#ibcon#enter sib2, iclass 34, count 0 2006.175.07:51:42.87#ibcon#flushed, iclass 34, count 0 2006.175.07:51:42.87#ibcon#about to write, iclass 34, count 0 2006.175.07:51:42.87#ibcon#wrote, iclass 34, count 0 2006.175.07:51:42.87#ibcon#about to read 3, iclass 34, count 0 2006.175.07:51:42.90#ibcon#read 3, iclass 34, count 0 2006.175.07:51:42.90#ibcon#about to read 4, iclass 34, count 0 2006.175.07:51:42.90#ibcon#read 4, iclass 34, count 0 2006.175.07:51:42.90#ibcon#about to read 5, iclass 34, count 0 2006.175.07:51:42.90#ibcon#read 5, iclass 34, count 0 2006.175.07:51:42.90#ibcon#about to read 6, iclass 34, count 0 2006.175.07:51:42.90#ibcon#read 6, iclass 34, count 0 2006.175.07:51:42.90#ibcon#end of sib2, iclass 34, count 0 2006.175.07:51:42.90#ibcon#*after write, iclass 34, count 0 2006.175.07:51:42.90#ibcon#*before return 0, iclass 34, count 0 2006.175.07:51:42.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:42.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.175.07:51:42.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:51:42.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:51:42.90$vc4f8/vabw=wide 2006.175.07:51:42.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.07:51:42.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.07:51:42.90#ibcon#ireg 8 cls_cnt 0 2006.175.07:51:42.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:42.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:42.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:42.90#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:51:42.90#ibcon#first serial, iclass 36, count 0 2006.175.07:51:42.90#ibcon#enter sib2, iclass 36, count 0 2006.175.07:51:42.90#ibcon#flushed, iclass 36, count 0 2006.175.07:51:42.90#ibcon#about to write, iclass 36, count 0 2006.175.07:51:42.90#ibcon#wrote, iclass 36, count 0 2006.175.07:51:42.90#ibcon#about to read 3, iclass 36, count 0 2006.175.07:51:42.92#ibcon#read 3, iclass 36, count 0 2006.175.07:51:42.92#ibcon#about to read 4, iclass 36, count 0 2006.175.07:51:42.92#ibcon#read 4, iclass 36, count 0 2006.175.07:51:42.92#ibcon#about to read 5, iclass 36, count 0 2006.175.07:51:42.92#ibcon#read 5, iclass 36, count 0 2006.175.07:51:42.92#ibcon#about to read 6, iclass 36, count 0 2006.175.07:51:42.92#ibcon#read 6, iclass 36, count 0 2006.175.07:51:42.92#ibcon#end of sib2, iclass 36, count 0 2006.175.07:51:42.92#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:51:42.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:51:42.92#ibcon#[25=BW32\r\n] 2006.175.07:51:42.92#ibcon#*before write, iclass 36, count 0 2006.175.07:51:42.92#ibcon#enter sib2, iclass 36, count 0 2006.175.07:51:42.92#ibcon#flushed, iclass 36, count 0 2006.175.07:51:42.92#ibcon#about to write, iclass 36, count 0 2006.175.07:51:42.92#ibcon#wrote, iclass 36, count 0 2006.175.07:51:42.92#ibcon#about to read 3, iclass 36, count 0 2006.175.07:51:42.95#ibcon#read 3, iclass 36, count 0 2006.175.07:51:42.95#ibcon#about to read 4, iclass 36, count 0 2006.175.07:51:42.95#ibcon#read 4, iclass 36, count 0 2006.175.07:51:42.95#ibcon#about to read 5, iclass 36, count 0 2006.175.07:51:42.95#ibcon#read 5, iclass 36, count 0 2006.175.07:51:42.95#ibcon#about to read 6, iclass 36, count 0 2006.175.07:51:42.95#ibcon#read 6, iclass 36, count 0 2006.175.07:51:42.95#ibcon#end of sib2, iclass 36, count 0 2006.175.07:51:42.95#ibcon#*after write, iclass 36, count 0 2006.175.07:51:42.95#ibcon#*before return 0, iclass 36, count 0 2006.175.07:51:42.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:42.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.07:51:42.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:51:42.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:51:42.95$vc4f8/vbbw=wide 2006.175.07:51:42.95#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:51:42.95#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:51:42.95#ibcon#ireg 8 cls_cnt 0 2006.175.07:51:42.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:51:43.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:51:43.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:51:43.02#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:51:43.02#ibcon#first serial, iclass 38, count 0 2006.175.07:51:43.02#ibcon#enter sib2, iclass 38, count 0 2006.175.07:51:43.02#ibcon#flushed, iclass 38, count 0 2006.175.07:51:43.02#ibcon#about to write, iclass 38, count 0 2006.175.07:51:43.02#ibcon#wrote, iclass 38, count 0 2006.175.07:51:43.02#ibcon#about to read 3, iclass 38, count 0 2006.175.07:51:43.04#ibcon#read 3, iclass 38, count 0 2006.175.07:51:43.04#ibcon#about to read 4, iclass 38, count 0 2006.175.07:51:43.04#ibcon#read 4, iclass 38, count 0 2006.175.07:51:43.04#ibcon#about to read 5, iclass 38, count 0 2006.175.07:51:43.04#ibcon#read 5, iclass 38, count 0 2006.175.07:51:43.04#ibcon#about to read 6, iclass 38, count 0 2006.175.07:51:43.04#ibcon#read 6, iclass 38, count 0 2006.175.07:51:43.04#ibcon#end of sib2, iclass 38, count 0 2006.175.07:51:43.04#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:51:43.04#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:51:43.04#ibcon#[27=BW32\r\n] 2006.175.07:51:43.04#ibcon#*before write, iclass 38, count 0 2006.175.07:51:43.04#ibcon#enter sib2, iclass 38, count 0 2006.175.07:51:43.04#ibcon#flushed, iclass 38, count 0 2006.175.07:51:43.04#ibcon#about to write, iclass 38, count 0 2006.175.07:51:43.04#ibcon#wrote, iclass 38, count 0 2006.175.07:51:43.04#ibcon#about to read 3, iclass 38, count 0 2006.175.07:51:43.07#ibcon#read 3, iclass 38, count 0 2006.175.07:51:43.07#ibcon#about to read 4, iclass 38, count 0 2006.175.07:51:43.07#ibcon#read 4, iclass 38, count 0 2006.175.07:51:43.07#ibcon#about to read 5, iclass 38, count 0 2006.175.07:51:43.07#ibcon#read 5, iclass 38, count 0 2006.175.07:51:43.07#ibcon#about to read 6, iclass 38, count 0 2006.175.07:51:43.07#ibcon#read 6, iclass 38, count 0 2006.175.07:51:43.07#ibcon#end of sib2, iclass 38, count 0 2006.175.07:51:43.07#ibcon#*after write, iclass 38, count 0 2006.175.07:51:43.07#ibcon#*before return 0, iclass 38, count 0 2006.175.07:51:43.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:51:43.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:51:43.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:51:43.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:51:43.07$4f8m12a/ifd4f 2006.175.07:51:43.07$ifd4f/lo= 2006.175.07:51:43.07$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:51:43.07$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:51:43.07$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:51:43.07$ifd4f/patch= 2006.175.07:51:43.07$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:51:43.07$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:51:43.07$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:51:43.07$4f8m12a/"form=m,16.000,1:2 2006.175.07:51:43.07$4f8m12a/"tpicd 2006.175.07:51:43.07$4f8m12a/echo=off 2006.175.07:51:43.07$4f8m12a/xlog=off 2006.175.07:51:43.07:!2006.175.07:52:20 2006.175.07:52:04.13#trakl#Source acquired 2006.175.07:52:04.13#flagr#flagr/antenna,acquired 2006.175.07:52:20.00:preob 2006.175.07:52:20.14/onsource/TRACKING 2006.175.07:52:20.14:!2006.175.07:52:30 2006.175.07:52:30.00:data_valid=on 2006.175.07:52:30.00:midob 2006.175.07:52:31.14/onsource/TRACKING 2006.175.07:52:31.14/wx/25.86,1007.3,68 2006.175.07:52:31.37/cable/+6.4798E-03 2006.175.07:52:32.46/va/01,08,usb,yes,29,30 2006.175.07:52:32.46/va/02,07,usb,yes,29,30 2006.175.07:52:32.46/va/03,06,usb,yes,30,31 2006.175.07:52:32.46/va/04,07,usb,yes,30,32 2006.175.07:52:32.46/va/05,07,usb,yes,30,32 2006.175.07:52:32.46/va/06,06,usb,yes,29,29 2006.175.07:52:32.46/va/07,06,usb,yes,30,30 2006.175.07:52:32.46/va/08,06,usb,yes,32,31 2006.175.07:52:32.69/valo/01,532.99,yes,locked 2006.175.07:52:32.69/valo/02,572.99,yes,locked 2006.175.07:52:32.69/valo/03,672.99,yes,locked 2006.175.07:52:32.69/valo/04,832.99,yes,locked 2006.175.07:52:32.69/valo/05,652.99,yes,locked 2006.175.07:52:32.69/valo/06,772.99,yes,locked 2006.175.07:52:32.69/valo/07,832.99,yes,locked 2006.175.07:52:32.69/valo/08,852.99,yes,locked 2006.175.07:52:33.78/vb/01,04,usb,yes,29,28 2006.175.07:52:33.78/vb/02,04,usb,yes,31,32 2006.175.07:52:33.78/vb/03,04,usb,yes,27,31 2006.175.07:52:33.78/vb/04,04,usb,yes,28,28 2006.175.07:52:33.78/vb/05,04,usb,yes,27,31 2006.175.07:52:33.78/vb/06,04,usb,yes,28,30 2006.175.07:52:33.78/vb/07,04,usb,yes,30,29 2006.175.07:52:33.78/vb/08,04,usb,yes,27,30 2006.175.07:52:34.02/vblo/01,632.99,yes,locked 2006.175.07:52:34.02/vblo/02,640.99,yes,locked 2006.175.07:52:34.02/vblo/03,656.99,yes,locked 2006.175.07:52:34.02/vblo/04,712.99,yes,locked 2006.175.07:52:34.02/vblo/05,744.99,yes,locked 2006.175.07:52:34.02/vblo/06,752.99,yes,locked 2006.175.07:52:34.02/vblo/07,734.99,yes,locked 2006.175.07:52:34.02/vblo/08,744.99,yes,locked 2006.175.07:52:34.17/vabw/8 2006.175.07:52:34.32/vbbw/8 2006.175.07:52:34.41/xfe/off,on,15.0 2006.175.07:52:34.78/ifatt/23,28,28,28 2006.175.07:52:35.08/fmout-gps/S +3.75E-07 2006.175.07:52:35.16:!2006.175.07:53:30 2006.175.07:53:30.00:data_valid=off 2006.175.07:53:30.00:postob 2006.175.07:53:30.21/cable/+6.4781E-03 2006.175.07:53:30.21/wx/25.85,1007.4,68 2006.175.07:53:31.08/fmout-gps/S +3.75E-07 2006.175.07:53:31.08:scan_name=175-0755,k06175,60 2006.175.07:53:31.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.175.07:53:31.14#flagr#flagr/antenna,new-source 2006.175.07:53:32.14:checkk5 2006.175.07:53:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:53:33.01/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:53:33.38/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:53:33.75/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:53:34.13/chk_obsdata//k5ts1/T1750752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:53:34.51/chk_obsdata//k5ts2/T1750752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:53:34.88/chk_obsdata//k5ts3/T1750752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:53:35.25/chk_obsdata//k5ts4/T1750752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:53:35.95/k5log//k5ts1_log_newline 2006.175.07:53:36.64/k5log//k5ts2_log_newline 2006.175.07:53:37.34/k5log//k5ts3_log_newline 2006.175.07:53:38.03/k5log//k5ts4_log_newline 2006.175.07:53:38.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:53:38.09:4f8m12a=2 2006.175.07:53:38.09$4f8m12a/echo=on 2006.175.07:53:38.09$4f8m12a/pcalon 2006.175.07:53:38.09$pcalon/"no phase cal control is implemented here 2006.175.07:53:38.09$4f8m12a/"tpicd=stop 2006.175.07:53:38.09$4f8m12a/vc4f8 2006.175.07:53:38.09$vc4f8/valo=1,532.99 2006.175.07:53:38.10#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.175.07:53:38.10#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.175.07:53:38.10#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:38.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:38.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:38.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:38.10#ibcon#enter wrdev, iclass 13, count 0 2006.175.07:53:38.10#ibcon#first serial, iclass 13, count 0 2006.175.07:53:38.10#ibcon#enter sib2, iclass 13, count 0 2006.175.07:53:38.10#ibcon#flushed, iclass 13, count 0 2006.175.07:53:38.10#ibcon#about to write, iclass 13, count 0 2006.175.07:53:38.10#ibcon#wrote, iclass 13, count 0 2006.175.07:53:38.10#ibcon#about to read 3, iclass 13, count 0 2006.175.07:53:38.12#ibcon#read 3, iclass 13, count 0 2006.175.07:53:38.12#ibcon#about to read 4, iclass 13, count 0 2006.175.07:53:38.12#ibcon#read 4, iclass 13, count 0 2006.175.07:53:38.12#ibcon#about to read 5, iclass 13, count 0 2006.175.07:53:38.12#ibcon#read 5, iclass 13, count 0 2006.175.07:53:38.12#ibcon#about to read 6, iclass 13, count 0 2006.175.07:53:38.12#ibcon#read 6, iclass 13, count 0 2006.175.07:53:38.12#ibcon#end of sib2, iclass 13, count 0 2006.175.07:53:38.12#ibcon#*mode == 0, iclass 13, count 0 2006.175.07:53:38.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.07:53:38.12#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:53:38.12#ibcon#*before write, iclass 13, count 0 2006.175.07:53:38.12#ibcon#enter sib2, iclass 13, count 0 2006.175.07:53:38.12#ibcon#flushed, iclass 13, count 0 2006.175.07:53:38.12#ibcon#about to write, iclass 13, count 0 2006.175.07:53:38.12#ibcon#wrote, iclass 13, count 0 2006.175.07:53:38.12#ibcon#about to read 3, iclass 13, count 0 2006.175.07:53:38.17#ibcon#read 3, iclass 13, count 0 2006.175.07:53:38.17#ibcon#about to read 4, iclass 13, count 0 2006.175.07:53:38.17#ibcon#read 4, iclass 13, count 0 2006.175.07:53:38.17#ibcon#about to read 5, iclass 13, count 0 2006.175.07:53:38.17#ibcon#read 5, iclass 13, count 0 2006.175.07:53:38.17#ibcon#about to read 6, iclass 13, count 0 2006.175.07:53:38.17#ibcon#read 6, iclass 13, count 0 2006.175.07:53:38.17#ibcon#end of sib2, iclass 13, count 0 2006.175.07:53:38.17#ibcon#*after write, iclass 13, count 0 2006.175.07:53:38.17#ibcon#*before return 0, iclass 13, count 0 2006.175.07:53:38.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:38.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:38.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.07:53:38.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.07:53:38.17$vc4f8/va=1,8 2006.175.07:53:38.17#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.175.07:53:38.17#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.175.07:53:38.17#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:38.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:38.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:38.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:38.17#ibcon#enter wrdev, iclass 15, count 2 2006.175.07:53:38.17#ibcon#first serial, iclass 15, count 2 2006.175.07:53:38.17#ibcon#enter sib2, iclass 15, count 2 2006.175.07:53:38.17#ibcon#flushed, iclass 15, count 2 2006.175.07:53:38.17#ibcon#about to write, iclass 15, count 2 2006.175.07:53:38.17#ibcon#wrote, iclass 15, count 2 2006.175.07:53:38.17#ibcon#about to read 3, iclass 15, count 2 2006.175.07:53:38.19#ibcon#read 3, iclass 15, count 2 2006.175.07:53:38.19#ibcon#about to read 4, iclass 15, count 2 2006.175.07:53:38.19#ibcon#read 4, iclass 15, count 2 2006.175.07:53:38.19#ibcon#about to read 5, iclass 15, count 2 2006.175.07:53:38.19#ibcon#read 5, iclass 15, count 2 2006.175.07:53:38.19#ibcon#about to read 6, iclass 15, count 2 2006.175.07:53:38.19#ibcon#read 6, iclass 15, count 2 2006.175.07:53:38.19#ibcon#end of sib2, iclass 15, count 2 2006.175.07:53:38.19#ibcon#*mode == 0, iclass 15, count 2 2006.175.07:53:38.19#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.175.07:53:38.19#ibcon#[25=AT01-08\r\n] 2006.175.07:53:38.19#ibcon#*before write, iclass 15, count 2 2006.175.07:53:38.19#ibcon#enter sib2, iclass 15, count 2 2006.175.07:53:38.19#ibcon#flushed, iclass 15, count 2 2006.175.07:53:38.19#ibcon#about to write, iclass 15, count 2 2006.175.07:53:38.19#ibcon#wrote, iclass 15, count 2 2006.175.07:53:38.19#ibcon#about to read 3, iclass 15, count 2 2006.175.07:53:38.22#ibcon#read 3, iclass 15, count 2 2006.175.07:53:38.22#ibcon#about to read 4, iclass 15, count 2 2006.175.07:53:38.22#ibcon#read 4, iclass 15, count 2 2006.175.07:53:38.22#ibcon#about to read 5, iclass 15, count 2 2006.175.07:53:38.22#ibcon#read 5, iclass 15, count 2 2006.175.07:53:38.22#ibcon#about to read 6, iclass 15, count 2 2006.175.07:53:38.22#ibcon#read 6, iclass 15, count 2 2006.175.07:53:38.22#ibcon#end of sib2, iclass 15, count 2 2006.175.07:53:38.22#ibcon#*after write, iclass 15, count 2 2006.175.07:53:38.22#ibcon#*before return 0, iclass 15, count 2 2006.175.07:53:38.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:38.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:38.22#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.175.07:53:38.22#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:38.22#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:38.34#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:38.34#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:38.34#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:53:38.34#ibcon#first serial, iclass 15, count 0 2006.175.07:53:38.34#ibcon#enter sib2, iclass 15, count 0 2006.175.07:53:38.34#ibcon#flushed, iclass 15, count 0 2006.175.07:53:38.34#ibcon#about to write, iclass 15, count 0 2006.175.07:53:38.34#ibcon#wrote, iclass 15, count 0 2006.175.07:53:38.34#ibcon#about to read 3, iclass 15, count 0 2006.175.07:53:38.36#ibcon#read 3, iclass 15, count 0 2006.175.07:53:38.36#ibcon#about to read 4, iclass 15, count 0 2006.175.07:53:38.36#ibcon#read 4, iclass 15, count 0 2006.175.07:53:38.36#ibcon#about to read 5, iclass 15, count 0 2006.175.07:53:38.36#ibcon#read 5, iclass 15, count 0 2006.175.07:53:38.36#ibcon#about to read 6, iclass 15, count 0 2006.175.07:53:38.36#ibcon#read 6, iclass 15, count 0 2006.175.07:53:38.36#ibcon#end of sib2, iclass 15, count 0 2006.175.07:53:38.36#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:53:38.36#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:53:38.36#ibcon#[25=USB\r\n] 2006.175.07:53:38.36#ibcon#*before write, iclass 15, count 0 2006.175.07:53:38.36#ibcon#enter sib2, iclass 15, count 0 2006.175.07:53:38.36#ibcon#flushed, iclass 15, count 0 2006.175.07:53:38.36#ibcon#about to write, iclass 15, count 0 2006.175.07:53:38.36#ibcon#wrote, iclass 15, count 0 2006.175.07:53:38.36#ibcon#about to read 3, iclass 15, count 0 2006.175.07:53:38.39#ibcon#read 3, iclass 15, count 0 2006.175.07:53:38.39#ibcon#about to read 4, iclass 15, count 0 2006.175.07:53:38.39#ibcon#read 4, iclass 15, count 0 2006.175.07:53:38.39#ibcon#about to read 5, iclass 15, count 0 2006.175.07:53:38.39#ibcon#read 5, iclass 15, count 0 2006.175.07:53:38.39#ibcon#about to read 6, iclass 15, count 0 2006.175.07:53:38.39#ibcon#read 6, iclass 15, count 0 2006.175.07:53:38.39#ibcon#end of sib2, iclass 15, count 0 2006.175.07:53:38.39#ibcon#*after write, iclass 15, count 0 2006.175.07:53:38.39#ibcon#*before return 0, iclass 15, count 0 2006.175.07:53:38.39#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:38.39#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:38.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:53:38.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:53:38.39$vc4f8/valo=2,572.99 2006.175.07:53:38.39#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.07:53:38.39#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.07:53:38.39#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:38.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:38.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:38.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:38.39#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:53:38.39#ibcon#first serial, iclass 17, count 0 2006.175.07:53:38.39#ibcon#enter sib2, iclass 17, count 0 2006.175.07:53:38.39#ibcon#flushed, iclass 17, count 0 2006.175.07:53:38.39#ibcon#about to write, iclass 17, count 0 2006.175.07:53:38.39#ibcon#wrote, iclass 17, count 0 2006.175.07:53:38.39#ibcon#about to read 3, iclass 17, count 0 2006.175.07:53:38.41#ibcon#read 3, iclass 17, count 0 2006.175.07:53:38.41#ibcon#about to read 4, iclass 17, count 0 2006.175.07:53:38.41#ibcon#read 4, iclass 17, count 0 2006.175.07:53:38.41#ibcon#about to read 5, iclass 17, count 0 2006.175.07:53:38.41#ibcon#read 5, iclass 17, count 0 2006.175.07:53:38.41#ibcon#about to read 6, iclass 17, count 0 2006.175.07:53:38.41#ibcon#read 6, iclass 17, count 0 2006.175.07:53:38.41#ibcon#end of sib2, iclass 17, count 0 2006.175.07:53:38.41#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:53:38.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:53:38.41#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:53:38.41#ibcon#*before write, iclass 17, count 0 2006.175.07:53:38.41#ibcon#enter sib2, iclass 17, count 0 2006.175.07:53:38.41#ibcon#flushed, iclass 17, count 0 2006.175.07:53:38.41#ibcon#about to write, iclass 17, count 0 2006.175.07:53:38.41#ibcon#wrote, iclass 17, count 0 2006.175.07:53:38.41#ibcon#about to read 3, iclass 17, count 0 2006.175.07:53:38.45#ibcon#read 3, iclass 17, count 0 2006.175.07:53:38.45#ibcon#about to read 4, iclass 17, count 0 2006.175.07:53:38.45#ibcon#read 4, iclass 17, count 0 2006.175.07:53:38.45#ibcon#about to read 5, iclass 17, count 0 2006.175.07:53:38.45#ibcon#read 5, iclass 17, count 0 2006.175.07:53:38.45#ibcon#about to read 6, iclass 17, count 0 2006.175.07:53:38.45#ibcon#read 6, iclass 17, count 0 2006.175.07:53:38.45#ibcon#end of sib2, iclass 17, count 0 2006.175.07:53:38.45#ibcon#*after write, iclass 17, count 0 2006.175.07:53:38.45#ibcon#*before return 0, iclass 17, count 0 2006.175.07:53:38.45#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:38.45#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:38.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:53:38.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:53:38.45$vc4f8/va=2,7 2006.175.07:53:38.45#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.175.07:53:38.45#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.175.07:53:38.45#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:38.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:38.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:38.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:38.51#ibcon#enter wrdev, iclass 19, count 2 2006.175.07:53:38.51#ibcon#first serial, iclass 19, count 2 2006.175.07:53:38.51#ibcon#enter sib2, iclass 19, count 2 2006.175.07:53:38.51#ibcon#flushed, iclass 19, count 2 2006.175.07:53:38.51#ibcon#about to write, iclass 19, count 2 2006.175.07:53:38.51#ibcon#wrote, iclass 19, count 2 2006.175.07:53:38.51#ibcon#about to read 3, iclass 19, count 2 2006.175.07:53:38.53#ibcon#read 3, iclass 19, count 2 2006.175.07:53:38.53#ibcon#about to read 4, iclass 19, count 2 2006.175.07:53:38.53#ibcon#read 4, iclass 19, count 2 2006.175.07:53:38.53#ibcon#about to read 5, iclass 19, count 2 2006.175.07:53:38.53#ibcon#read 5, iclass 19, count 2 2006.175.07:53:38.53#ibcon#about to read 6, iclass 19, count 2 2006.175.07:53:38.53#ibcon#read 6, iclass 19, count 2 2006.175.07:53:38.53#ibcon#end of sib2, iclass 19, count 2 2006.175.07:53:38.53#ibcon#*mode == 0, iclass 19, count 2 2006.175.07:53:38.53#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.175.07:53:38.53#ibcon#[25=AT02-07\r\n] 2006.175.07:53:38.53#ibcon#*before write, iclass 19, count 2 2006.175.07:53:38.53#ibcon#enter sib2, iclass 19, count 2 2006.175.07:53:38.53#ibcon#flushed, iclass 19, count 2 2006.175.07:53:38.53#ibcon#about to write, iclass 19, count 2 2006.175.07:53:38.53#ibcon#wrote, iclass 19, count 2 2006.175.07:53:38.53#ibcon#about to read 3, iclass 19, count 2 2006.175.07:53:38.56#ibcon#read 3, iclass 19, count 2 2006.175.07:53:38.56#ibcon#about to read 4, iclass 19, count 2 2006.175.07:53:38.56#ibcon#read 4, iclass 19, count 2 2006.175.07:53:38.56#ibcon#about to read 5, iclass 19, count 2 2006.175.07:53:38.56#ibcon#read 5, iclass 19, count 2 2006.175.07:53:38.56#ibcon#about to read 6, iclass 19, count 2 2006.175.07:53:38.56#ibcon#read 6, iclass 19, count 2 2006.175.07:53:38.56#ibcon#end of sib2, iclass 19, count 2 2006.175.07:53:38.56#ibcon#*after write, iclass 19, count 2 2006.175.07:53:38.56#ibcon#*before return 0, iclass 19, count 2 2006.175.07:53:38.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:38.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:38.56#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.175.07:53:38.56#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:38.56#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:38.68#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:38.68#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:38.68#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:53:38.68#ibcon#first serial, iclass 19, count 0 2006.175.07:53:38.68#ibcon#enter sib2, iclass 19, count 0 2006.175.07:53:38.68#ibcon#flushed, iclass 19, count 0 2006.175.07:53:38.68#ibcon#about to write, iclass 19, count 0 2006.175.07:53:38.68#ibcon#wrote, iclass 19, count 0 2006.175.07:53:38.68#ibcon#about to read 3, iclass 19, count 0 2006.175.07:53:38.70#ibcon#read 3, iclass 19, count 0 2006.175.07:53:38.70#ibcon#about to read 4, iclass 19, count 0 2006.175.07:53:38.70#ibcon#read 4, iclass 19, count 0 2006.175.07:53:38.70#ibcon#about to read 5, iclass 19, count 0 2006.175.07:53:38.70#ibcon#read 5, iclass 19, count 0 2006.175.07:53:38.70#ibcon#about to read 6, iclass 19, count 0 2006.175.07:53:38.70#ibcon#read 6, iclass 19, count 0 2006.175.07:53:38.70#ibcon#end of sib2, iclass 19, count 0 2006.175.07:53:38.70#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:53:38.70#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:53:38.70#ibcon#[25=USB\r\n] 2006.175.07:53:38.70#ibcon#*before write, iclass 19, count 0 2006.175.07:53:38.70#ibcon#enter sib2, iclass 19, count 0 2006.175.07:53:38.70#ibcon#flushed, iclass 19, count 0 2006.175.07:53:38.70#ibcon#about to write, iclass 19, count 0 2006.175.07:53:38.70#ibcon#wrote, iclass 19, count 0 2006.175.07:53:38.70#ibcon#about to read 3, iclass 19, count 0 2006.175.07:53:38.73#ibcon#read 3, iclass 19, count 0 2006.175.07:53:38.73#ibcon#about to read 4, iclass 19, count 0 2006.175.07:53:38.73#ibcon#read 4, iclass 19, count 0 2006.175.07:53:38.73#ibcon#about to read 5, iclass 19, count 0 2006.175.07:53:38.73#ibcon#read 5, iclass 19, count 0 2006.175.07:53:38.73#ibcon#about to read 6, iclass 19, count 0 2006.175.07:53:38.73#ibcon#read 6, iclass 19, count 0 2006.175.07:53:38.73#ibcon#end of sib2, iclass 19, count 0 2006.175.07:53:38.73#ibcon#*after write, iclass 19, count 0 2006.175.07:53:38.73#ibcon#*before return 0, iclass 19, count 0 2006.175.07:53:38.73#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:38.73#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:38.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:53:38.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:53:38.73$vc4f8/valo=3,672.99 2006.175.07:53:38.73#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.07:53:38.73#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.07:53:38.73#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:38.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:38.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:38.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:38.73#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:53:38.73#ibcon#first serial, iclass 21, count 0 2006.175.07:53:38.73#ibcon#enter sib2, iclass 21, count 0 2006.175.07:53:38.73#ibcon#flushed, iclass 21, count 0 2006.175.07:53:38.73#ibcon#about to write, iclass 21, count 0 2006.175.07:53:38.73#ibcon#wrote, iclass 21, count 0 2006.175.07:53:38.73#ibcon#about to read 3, iclass 21, count 0 2006.175.07:53:38.75#ibcon#read 3, iclass 21, count 0 2006.175.07:53:38.75#ibcon#about to read 4, iclass 21, count 0 2006.175.07:53:38.75#ibcon#read 4, iclass 21, count 0 2006.175.07:53:38.75#ibcon#about to read 5, iclass 21, count 0 2006.175.07:53:38.75#ibcon#read 5, iclass 21, count 0 2006.175.07:53:38.75#ibcon#about to read 6, iclass 21, count 0 2006.175.07:53:38.75#ibcon#read 6, iclass 21, count 0 2006.175.07:53:38.75#ibcon#end of sib2, iclass 21, count 0 2006.175.07:53:38.75#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:53:38.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:53:38.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:53:38.75#ibcon#*before write, iclass 21, count 0 2006.175.07:53:38.75#ibcon#enter sib2, iclass 21, count 0 2006.175.07:53:38.75#ibcon#flushed, iclass 21, count 0 2006.175.07:53:38.75#ibcon#about to write, iclass 21, count 0 2006.175.07:53:38.75#ibcon#wrote, iclass 21, count 0 2006.175.07:53:38.75#ibcon#about to read 3, iclass 21, count 0 2006.175.07:53:38.79#ibcon#read 3, iclass 21, count 0 2006.175.07:53:38.79#ibcon#about to read 4, iclass 21, count 0 2006.175.07:53:38.79#ibcon#read 4, iclass 21, count 0 2006.175.07:53:38.79#ibcon#about to read 5, iclass 21, count 0 2006.175.07:53:38.79#ibcon#read 5, iclass 21, count 0 2006.175.07:53:38.79#ibcon#about to read 6, iclass 21, count 0 2006.175.07:53:38.79#ibcon#read 6, iclass 21, count 0 2006.175.07:53:38.79#ibcon#end of sib2, iclass 21, count 0 2006.175.07:53:38.79#ibcon#*after write, iclass 21, count 0 2006.175.07:53:38.79#ibcon#*before return 0, iclass 21, count 0 2006.175.07:53:38.79#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:38.79#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:38.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:53:38.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:53:38.79$vc4f8/va=3,6 2006.175.07:53:38.79#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.07:53:38.79#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.07:53:38.79#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:38.79#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:38.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:38.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:38.85#ibcon#enter wrdev, iclass 23, count 2 2006.175.07:53:38.85#ibcon#first serial, iclass 23, count 2 2006.175.07:53:38.85#ibcon#enter sib2, iclass 23, count 2 2006.175.07:53:38.85#ibcon#flushed, iclass 23, count 2 2006.175.07:53:38.85#ibcon#about to write, iclass 23, count 2 2006.175.07:53:38.85#ibcon#wrote, iclass 23, count 2 2006.175.07:53:38.85#ibcon#about to read 3, iclass 23, count 2 2006.175.07:53:38.87#ibcon#read 3, iclass 23, count 2 2006.175.07:53:38.87#ibcon#about to read 4, iclass 23, count 2 2006.175.07:53:38.87#ibcon#read 4, iclass 23, count 2 2006.175.07:53:38.87#ibcon#about to read 5, iclass 23, count 2 2006.175.07:53:38.87#ibcon#read 5, iclass 23, count 2 2006.175.07:53:38.87#ibcon#about to read 6, iclass 23, count 2 2006.175.07:53:38.87#ibcon#read 6, iclass 23, count 2 2006.175.07:53:38.87#ibcon#end of sib2, iclass 23, count 2 2006.175.07:53:38.87#ibcon#*mode == 0, iclass 23, count 2 2006.175.07:53:38.87#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.07:53:38.87#ibcon#[25=AT03-06\r\n] 2006.175.07:53:38.87#ibcon#*before write, iclass 23, count 2 2006.175.07:53:38.87#ibcon#enter sib2, iclass 23, count 2 2006.175.07:53:38.87#ibcon#flushed, iclass 23, count 2 2006.175.07:53:38.87#ibcon#about to write, iclass 23, count 2 2006.175.07:53:38.87#ibcon#wrote, iclass 23, count 2 2006.175.07:53:38.87#ibcon#about to read 3, iclass 23, count 2 2006.175.07:53:38.90#ibcon#read 3, iclass 23, count 2 2006.175.07:53:38.90#ibcon#about to read 4, iclass 23, count 2 2006.175.07:53:38.90#ibcon#read 4, iclass 23, count 2 2006.175.07:53:38.90#ibcon#about to read 5, iclass 23, count 2 2006.175.07:53:38.90#ibcon#read 5, iclass 23, count 2 2006.175.07:53:38.90#ibcon#about to read 6, iclass 23, count 2 2006.175.07:53:38.90#ibcon#read 6, iclass 23, count 2 2006.175.07:53:38.90#ibcon#end of sib2, iclass 23, count 2 2006.175.07:53:38.90#ibcon#*after write, iclass 23, count 2 2006.175.07:53:38.90#ibcon#*before return 0, iclass 23, count 2 2006.175.07:53:38.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:38.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:38.90#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.07:53:38.90#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:38.90#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:39.02#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:39.02#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:39.02#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:53:39.02#ibcon#first serial, iclass 23, count 0 2006.175.07:53:39.02#ibcon#enter sib2, iclass 23, count 0 2006.175.07:53:39.02#ibcon#flushed, iclass 23, count 0 2006.175.07:53:39.02#ibcon#about to write, iclass 23, count 0 2006.175.07:53:39.02#ibcon#wrote, iclass 23, count 0 2006.175.07:53:39.02#ibcon#about to read 3, iclass 23, count 0 2006.175.07:53:39.04#ibcon#read 3, iclass 23, count 0 2006.175.07:53:39.04#ibcon#about to read 4, iclass 23, count 0 2006.175.07:53:39.04#ibcon#read 4, iclass 23, count 0 2006.175.07:53:39.04#ibcon#about to read 5, iclass 23, count 0 2006.175.07:53:39.04#ibcon#read 5, iclass 23, count 0 2006.175.07:53:39.04#ibcon#about to read 6, iclass 23, count 0 2006.175.07:53:39.04#ibcon#read 6, iclass 23, count 0 2006.175.07:53:39.04#ibcon#end of sib2, iclass 23, count 0 2006.175.07:53:39.04#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:53:39.04#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:53:39.04#ibcon#[25=USB\r\n] 2006.175.07:53:39.04#ibcon#*before write, iclass 23, count 0 2006.175.07:53:39.04#ibcon#enter sib2, iclass 23, count 0 2006.175.07:53:39.04#ibcon#flushed, iclass 23, count 0 2006.175.07:53:39.04#ibcon#about to write, iclass 23, count 0 2006.175.07:53:39.04#ibcon#wrote, iclass 23, count 0 2006.175.07:53:39.04#ibcon#about to read 3, iclass 23, count 0 2006.175.07:53:39.07#ibcon#read 3, iclass 23, count 0 2006.175.07:53:39.07#ibcon#about to read 4, iclass 23, count 0 2006.175.07:53:39.07#ibcon#read 4, iclass 23, count 0 2006.175.07:53:39.07#ibcon#about to read 5, iclass 23, count 0 2006.175.07:53:39.07#ibcon#read 5, iclass 23, count 0 2006.175.07:53:39.07#ibcon#about to read 6, iclass 23, count 0 2006.175.07:53:39.07#ibcon#read 6, iclass 23, count 0 2006.175.07:53:39.07#ibcon#end of sib2, iclass 23, count 0 2006.175.07:53:39.07#ibcon#*after write, iclass 23, count 0 2006.175.07:53:39.07#ibcon#*before return 0, iclass 23, count 0 2006.175.07:53:39.07#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:39.07#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:39.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:53:39.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:53:39.07$vc4f8/valo=4,832.99 2006.175.07:53:39.07#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.07:53:39.07#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.07:53:39.07#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:39.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:39.07#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:39.07#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:39.07#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:53:39.07#ibcon#first serial, iclass 25, count 0 2006.175.07:53:39.07#ibcon#enter sib2, iclass 25, count 0 2006.175.07:53:39.07#ibcon#flushed, iclass 25, count 0 2006.175.07:53:39.07#ibcon#about to write, iclass 25, count 0 2006.175.07:53:39.07#ibcon#wrote, iclass 25, count 0 2006.175.07:53:39.07#ibcon#about to read 3, iclass 25, count 0 2006.175.07:53:39.09#ibcon#read 3, iclass 25, count 0 2006.175.07:53:39.09#ibcon#about to read 4, iclass 25, count 0 2006.175.07:53:39.09#ibcon#read 4, iclass 25, count 0 2006.175.07:53:39.09#ibcon#about to read 5, iclass 25, count 0 2006.175.07:53:39.09#ibcon#read 5, iclass 25, count 0 2006.175.07:53:39.09#ibcon#about to read 6, iclass 25, count 0 2006.175.07:53:39.09#ibcon#read 6, iclass 25, count 0 2006.175.07:53:39.09#ibcon#end of sib2, iclass 25, count 0 2006.175.07:53:39.09#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:53:39.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:53:39.09#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:53:39.09#ibcon#*before write, iclass 25, count 0 2006.175.07:53:39.09#ibcon#enter sib2, iclass 25, count 0 2006.175.07:53:39.09#ibcon#flushed, iclass 25, count 0 2006.175.07:53:39.09#ibcon#about to write, iclass 25, count 0 2006.175.07:53:39.09#ibcon#wrote, iclass 25, count 0 2006.175.07:53:39.09#ibcon#about to read 3, iclass 25, count 0 2006.175.07:53:39.13#ibcon#read 3, iclass 25, count 0 2006.175.07:53:39.13#ibcon#about to read 4, iclass 25, count 0 2006.175.07:53:39.13#ibcon#read 4, iclass 25, count 0 2006.175.07:53:39.13#ibcon#about to read 5, iclass 25, count 0 2006.175.07:53:39.13#ibcon#read 5, iclass 25, count 0 2006.175.07:53:39.13#ibcon#about to read 6, iclass 25, count 0 2006.175.07:53:39.13#ibcon#read 6, iclass 25, count 0 2006.175.07:53:39.13#ibcon#end of sib2, iclass 25, count 0 2006.175.07:53:39.13#ibcon#*after write, iclass 25, count 0 2006.175.07:53:39.13#ibcon#*before return 0, iclass 25, count 0 2006.175.07:53:39.13#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:39.13#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:39.13#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:53:39.13#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:53:39.13$vc4f8/va=4,7 2006.175.07:53:39.13#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.07:53:39.13#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.07:53:39.13#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:39.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:39.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:39.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:39.19#ibcon#enter wrdev, iclass 27, count 2 2006.175.07:53:39.19#ibcon#first serial, iclass 27, count 2 2006.175.07:53:39.19#ibcon#enter sib2, iclass 27, count 2 2006.175.07:53:39.19#ibcon#flushed, iclass 27, count 2 2006.175.07:53:39.19#ibcon#about to write, iclass 27, count 2 2006.175.07:53:39.19#ibcon#wrote, iclass 27, count 2 2006.175.07:53:39.19#ibcon#about to read 3, iclass 27, count 2 2006.175.07:53:39.21#ibcon#read 3, iclass 27, count 2 2006.175.07:53:39.21#ibcon#about to read 4, iclass 27, count 2 2006.175.07:53:39.21#ibcon#read 4, iclass 27, count 2 2006.175.07:53:39.21#ibcon#about to read 5, iclass 27, count 2 2006.175.07:53:39.21#ibcon#read 5, iclass 27, count 2 2006.175.07:53:39.21#ibcon#about to read 6, iclass 27, count 2 2006.175.07:53:39.21#ibcon#read 6, iclass 27, count 2 2006.175.07:53:39.21#ibcon#end of sib2, iclass 27, count 2 2006.175.07:53:39.21#ibcon#*mode == 0, iclass 27, count 2 2006.175.07:53:39.21#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.07:53:39.21#ibcon#[25=AT04-07\r\n] 2006.175.07:53:39.21#ibcon#*before write, iclass 27, count 2 2006.175.07:53:39.21#ibcon#enter sib2, iclass 27, count 2 2006.175.07:53:39.21#ibcon#flushed, iclass 27, count 2 2006.175.07:53:39.21#ibcon#about to write, iclass 27, count 2 2006.175.07:53:39.21#ibcon#wrote, iclass 27, count 2 2006.175.07:53:39.21#ibcon#about to read 3, iclass 27, count 2 2006.175.07:53:39.24#ibcon#read 3, iclass 27, count 2 2006.175.07:53:39.24#ibcon#about to read 4, iclass 27, count 2 2006.175.07:53:39.24#ibcon#read 4, iclass 27, count 2 2006.175.07:53:39.24#ibcon#about to read 5, iclass 27, count 2 2006.175.07:53:39.24#ibcon#read 5, iclass 27, count 2 2006.175.07:53:39.24#ibcon#about to read 6, iclass 27, count 2 2006.175.07:53:39.24#ibcon#read 6, iclass 27, count 2 2006.175.07:53:39.24#ibcon#end of sib2, iclass 27, count 2 2006.175.07:53:39.24#ibcon#*after write, iclass 27, count 2 2006.175.07:53:39.24#ibcon#*before return 0, iclass 27, count 2 2006.175.07:53:39.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:39.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:39.24#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.07:53:39.24#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:39.24#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:39.36#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:39.36#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:39.36#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:53:39.36#ibcon#first serial, iclass 27, count 0 2006.175.07:53:39.36#ibcon#enter sib2, iclass 27, count 0 2006.175.07:53:39.36#ibcon#flushed, iclass 27, count 0 2006.175.07:53:39.36#ibcon#about to write, iclass 27, count 0 2006.175.07:53:39.36#ibcon#wrote, iclass 27, count 0 2006.175.07:53:39.36#ibcon#about to read 3, iclass 27, count 0 2006.175.07:53:39.38#ibcon#read 3, iclass 27, count 0 2006.175.07:53:39.38#ibcon#about to read 4, iclass 27, count 0 2006.175.07:53:39.38#ibcon#read 4, iclass 27, count 0 2006.175.07:53:39.38#ibcon#about to read 5, iclass 27, count 0 2006.175.07:53:39.38#ibcon#read 5, iclass 27, count 0 2006.175.07:53:39.38#ibcon#about to read 6, iclass 27, count 0 2006.175.07:53:39.38#ibcon#read 6, iclass 27, count 0 2006.175.07:53:39.38#ibcon#end of sib2, iclass 27, count 0 2006.175.07:53:39.38#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:53:39.38#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:53:39.38#ibcon#[25=USB\r\n] 2006.175.07:53:39.38#ibcon#*before write, iclass 27, count 0 2006.175.07:53:39.38#ibcon#enter sib2, iclass 27, count 0 2006.175.07:53:39.38#ibcon#flushed, iclass 27, count 0 2006.175.07:53:39.38#ibcon#about to write, iclass 27, count 0 2006.175.07:53:39.38#ibcon#wrote, iclass 27, count 0 2006.175.07:53:39.38#ibcon#about to read 3, iclass 27, count 0 2006.175.07:53:39.41#ibcon#read 3, iclass 27, count 0 2006.175.07:53:39.41#ibcon#about to read 4, iclass 27, count 0 2006.175.07:53:39.41#ibcon#read 4, iclass 27, count 0 2006.175.07:53:39.41#ibcon#about to read 5, iclass 27, count 0 2006.175.07:53:39.41#ibcon#read 5, iclass 27, count 0 2006.175.07:53:39.41#ibcon#about to read 6, iclass 27, count 0 2006.175.07:53:39.41#ibcon#read 6, iclass 27, count 0 2006.175.07:53:39.41#ibcon#end of sib2, iclass 27, count 0 2006.175.07:53:39.41#ibcon#*after write, iclass 27, count 0 2006.175.07:53:39.41#ibcon#*before return 0, iclass 27, count 0 2006.175.07:53:39.41#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:39.41#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:39.41#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:53:39.41#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:53:39.41$vc4f8/valo=5,652.99 2006.175.07:53:39.41#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.07:53:39.41#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.07:53:39.41#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:39.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:39.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:39.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:39.41#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:53:39.41#ibcon#first serial, iclass 29, count 0 2006.175.07:53:39.41#ibcon#enter sib2, iclass 29, count 0 2006.175.07:53:39.41#ibcon#flushed, iclass 29, count 0 2006.175.07:53:39.41#ibcon#about to write, iclass 29, count 0 2006.175.07:53:39.41#ibcon#wrote, iclass 29, count 0 2006.175.07:53:39.41#ibcon#about to read 3, iclass 29, count 0 2006.175.07:53:39.43#ibcon#read 3, iclass 29, count 0 2006.175.07:53:39.43#ibcon#about to read 4, iclass 29, count 0 2006.175.07:53:39.43#ibcon#read 4, iclass 29, count 0 2006.175.07:53:39.43#ibcon#about to read 5, iclass 29, count 0 2006.175.07:53:39.43#ibcon#read 5, iclass 29, count 0 2006.175.07:53:39.43#ibcon#about to read 6, iclass 29, count 0 2006.175.07:53:39.43#ibcon#read 6, iclass 29, count 0 2006.175.07:53:39.43#ibcon#end of sib2, iclass 29, count 0 2006.175.07:53:39.43#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:53:39.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:53:39.43#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:53:39.43#ibcon#*before write, iclass 29, count 0 2006.175.07:53:39.43#ibcon#enter sib2, iclass 29, count 0 2006.175.07:53:39.43#ibcon#flushed, iclass 29, count 0 2006.175.07:53:39.43#ibcon#about to write, iclass 29, count 0 2006.175.07:53:39.43#ibcon#wrote, iclass 29, count 0 2006.175.07:53:39.43#ibcon#about to read 3, iclass 29, count 0 2006.175.07:53:39.47#ibcon#read 3, iclass 29, count 0 2006.175.07:53:39.47#ibcon#about to read 4, iclass 29, count 0 2006.175.07:53:39.47#ibcon#read 4, iclass 29, count 0 2006.175.07:53:39.47#ibcon#about to read 5, iclass 29, count 0 2006.175.07:53:39.47#ibcon#read 5, iclass 29, count 0 2006.175.07:53:39.47#ibcon#about to read 6, iclass 29, count 0 2006.175.07:53:39.47#ibcon#read 6, iclass 29, count 0 2006.175.07:53:39.47#ibcon#end of sib2, iclass 29, count 0 2006.175.07:53:39.47#ibcon#*after write, iclass 29, count 0 2006.175.07:53:39.47#ibcon#*before return 0, iclass 29, count 0 2006.175.07:53:39.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:39.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:39.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:53:39.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:53:39.47$vc4f8/va=5,7 2006.175.07:53:39.47#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.07:53:39.47#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.07:53:39.47#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:39.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:39.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:39.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:39.53#ibcon#enter wrdev, iclass 31, count 2 2006.175.07:53:39.53#ibcon#first serial, iclass 31, count 2 2006.175.07:53:39.53#ibcon#enter sib2, iclass 31, count 2 2006.175.07:53:39.53#ibcon#flushed, iclass 31, count 2 2006.175.07:53:39.53#ibcon#about to write, iclass 31, count 2 2006.175.07:53:39.53#ibcon#wrote, iclass 31, count 2 2006.175.07:53:39.53#ibcon#about to read 3, iclass 31, count 2 2006.175.07:53:39.55#ibcon#read 3, iclass 31, count 2 2006.175.07:53:39.55#ibcon#about to read 4, iclass 31, count 2 2006.175.07:53:39.55#ibcon#read 4, iclass 31, count 2 2006.175.07:53:39.55#ibcon#about to read 5, iclass 31, count 2 2006.175.07:53:39.55#ibcon#read 5, iclass 31, count 2 2006.175.07:53:39.55#ibcon#about to read 6, iclass 31, count 2 2006.175.07:53:39.55#ibcon#read 6, iclass 31, count 2 2006.175.07:53:39.55#ibcon#end of sib2, iclass 31, count 2 2006.175.07:53:39.55#ibcon#*mode == 0, iclass 31, count 2 2006.175.07:53:39.55#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.07:53:39.55#ibcon#[25=AT05-07\r\n] 2006.175.07:53:39.55#ibcon#*before write, iclass 31, count 2 2006.175.07:53:39.55#ibcon#enter sib2, iclass 31, count 2 2006.175.07:53:39.55#ibcon#flushed, iclass 31, count 2 2006.175.07:53:39.55#ibcon#about to write, iclass 31, count 2 2006.175.07:53:39.55#ibcon#wrote, iclass 31, count 2 2006.175.07:53:39.55#ibcon#about to read 3, iclass 31, count 2 2006.175.07:53:39.58#ibcon#read 3, iclass 31, count 2 2006.175.07:53:39.58#ibcon#about to read 4, iclass 31, count 2 2006.175.07:53:39.58#ibcon#read 4, iclass 31, count 2 2006.175.07:53:39.58#ibcon#about to read 5, iclass 31, count 2 2006.175.07:53:39.58#ibcon#read 5, iclass 31, count 2 2006.175.07:53:39.58#ibcon#about to read 6, iclass 31, count 2 2006.175.07:53:39.58#ibcon#read 6, iclass 31, count 2 2006.175.07:53:39.58#ibcon#end of sib2, iclass 31, count 2 2006.175.07:53:39.58#ibcon#*after write, iclass 31, count 2 2006.175.07:53:39.58#ibcon#*before return 0, iclass 31, count 2 2006.175.07:53:39.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:39.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:39.58#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.07:53:39.58#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:39.58#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:39.70#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:39.70#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:39.70#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:53:39.70#ibcon#first serial, iclass 31, count 0 2006.175.07:53:39.70#ibcon#enter sib2, iclass 31, count 0 2006.175.07:53:39.70#ibcon#flushed, iclass 31, count 0 2006.175.07:53:39.70#ibcon#about to write, iclass 31, count 0 2006.175.07:53:39.70#ibcon#wrote, iclass 31, count 0 2006.175.07:53:39.70#ibcon#about to read 3, iclass 31, count 0 2006.175.07:53:39.72#ibcon#read 3, iclass 31, count 0 2006.175.07:53:39.72#ibcon#about to read 4, iclass 31, count 0 2006.175.07:53:39.72#ibcon#read 4, iclass 31, count 0 2006.175.07:53:39.72#ibcon#about to read 5, iclass 31, count 0 2006.175.07:53:39.72#ibcon#read 5, iclass 31, count 0 2006.175.07:53:39.72#ibcon#about to read 6, iclass 31, count 0 2006.175.07:53:39.72#ibcon#read 6, iclass 31, count 0 2006.175.07:53:39.72#ibcon#end of sib2, iclass 31, count 0 2006.175.07:53:39.72#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:53:39.72#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:53:39.72#ibcon#[25=USB\r\n] 2006.175.07:53:39.72#ibcon#*before write, iclass 31, count 0 2006.175.07:53:39.72#ibcon#enter sib2, iclass 31, count 0 2006.175.07:53:39.72#ibcon#flushed, iclass 31, count 0 2006.175.07:53:39.72#ibcon#about to write, iclass 31, count 0 2006.175.07:53:39.72#ibcon#wrote, iclass 31, count 0 2006.175.07:53:39.72#ibcon#about to read 3, iclass 31, count 0 2006.175.07:53:39.75#ibcon#read 3, iclass 31, count 0 2006.175.07:53:39.75#ibcon#about to read 4, iclass 31, count 0 2006.175.07:53:39.75#ibcon#read 4, iclass 31, count 0 2006.175.07:53:39.75#ibcon#about to read 5, iclass 31, count 0 2006.175.07:53:39.75#ibcon#read 5, iclass 31, count 0 2006.175.07:53:39.75#ibcon#about to read 6, iclass 31, count 0 2006.175.07:53:39.75#ibcon#read 6, iclass 31, count 0 2006.175.07:53:39.75#ibcon#end of sib2, iclass 31, count 0 2006.175.07:53:39.75#ibcon#*after write, iclass 31, count 0 2006.175.07:53:39.75#ibcon#*before return 0, iclass 31, count 0 2006.175.07:53:39.75#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:39.75#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:39.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:53:39.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:53:39.75$vc4f8/valo=6,772.99 2006.175.07:53:39.75#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.07:53:39.75#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.07:53:39.75#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:39.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:39.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:39.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:39.75#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:53:39.75#ibcon#first serial, iclass 33, count 0 2006.175.07:53:39.75#ibcon#enter sib2, iclass 33, count 0 2006.175.07:53:39.75#ibcon#flushed, iclass 33, count 0 2006.175.07:53:39.75#ibcon#about to write, iclass 33, count 0 2006.175.07:53:39.75#ibcon#wrote, iclass 33, count 0 2006.175.07:53:39.75#ibcon#about to read 3, iclass 33, count 0 2006.175.07:53:39.77#ibcon#read 3, iclass 33, count 0 2006.175.07:53:39.77#ibcon#about to read 4, iclass 33, count 0 2006.175.07:53:39.77#ibcon#read 4, iclass 33, count 0 2006.175.07:53:39.77#ibcon#about to read 5, iclass 33, count 0 2006.175.07:53:39.77#ibcon#read 5, iclass 33, count 0 2006.175.07:53:39.77#ibcon#about to read 6, iclass 33, count 0 2006.175.07:53:39.77#ibcon#read 6, iclass 33, count 0 2006.175.07:53:39.77#ibcon#end of sib2, iclass 33, count 0 2006.175.07:53:39.77#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:53:39.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:53:39.77#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:53:39.77#ibcon#*before write, iclass 33, count 0 2006.175.07:53:39.77#ibcon#enter sib2, iclass 33, count 0 2006.175.07:53:39.77#ibcon#flushed, iclass 33, count 0 2006.175.07:53:39.77#ibcon#about to write, iclass 33, count 0 2006.175.07:53:39.77#ibcon#wrote, iclass 33, count 0 2006.175.07:53:39.77#ibcon#about to read 3, iclass 33, count 0 2006.175.07:53:39.81#ibcon#read 3, iclass 33, count 0 2006.175.07:53:39.81#ibcon#about to read 4, iclass 33, count 0 2006.175.07:53:39.81#ibcon#read 4, iclass 33, count 0 2006.175.07:53:39.81#ibcon#about to read 5, iclass 33, count 0 2006.175.07:53:39.81#ibcon#read 5, iclass 33, count 0 2006.175.07:53:39.81#ibcon#about to read 6, iclass 33, count 0 2006.175.07:53:39.81#ibcon#read 6, iclass 33, count 0 2006.175.07:53:39.81#ibcon#end of sib2, iclass 33, count 0 2006.175.07:53:39.81#ibcon#*after write, iclass 33, count 0 2006.175.07:53:39.81#ibcon#*before return 0, iclass 33, count 0 2006.175.07:53:39.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:39.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:39.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:53:39.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:53:39.81$vc4f8/va=6,6 2006.175.07:53:39.81#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.175.07:53:39.81#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.175.07:53:39.81#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:39.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:53:39.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:53:39.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:53:39.87#ibcon#enter wrdev, iclass 35, count 2 2006.175.07:53:39.87#ibcon#first serial, iclass 35, count 2 2006.175.07:53:39.87#ibcon#enter sib2, iclass 35, count 2 2006.175.07:53:39.87#ibcon#flushed, iclass 35, count 2 2006.175.07:53:39.87#ibcon#about to write, iclass 35, count 2 2006.175.07:53:39.87#ibcon#wrote, iclass 35, count 2 2006.175.07:53:39.87#ibcon#about to read 3, iclass 35, count 2 2006.175.07:53:39.89#ibcon#read 3, iclass 35, count 2 2006.175.07:53:39.89#ibcon#about to read 4, iclass 35, count 2 2006.175.07:53:39.89#ibcon#read 4, iclass 35, count 2 2006.175.07:53:39.89#ibcon#about to read 5, iclass 35, count 2 2006.175.07:53:39.89#ibcon#read 5, iclass 35, count 2 2006.175.07:53:39.89#ibcon#about to read 6, iclass 35, count 2 2006.175.07:53:39.89#ibcon#read 6, iclass 35, count 2 2006.175.07:53:39.89#ibcon#end of sib2, iclass 35, count 2 2006.175.07:53:39.89#ibcon#*mode == 0, iclass 35, count 2 2006.175.07:53:39.89#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.175.07:53:39.89#ibcon#[25=AT06-06\r\n] 2006.175.07:53:39.89#ibcon#*before write, iclass 35, count 2 2006.175.07:53:39.89#ibcon#enter sib2, iclass 35, count 2 2006.175.07:53:39.89#ibcon#flushed, iclass 35, count 2 2006.175.07:53:39.89#ibcon#about to write, iclass 35, count 2 2006.175.07:53:39.89#ibcon#wrote, iclass 35, count 2 2006.175.07:53:39.89#ibcon#about to read 3, iclass 35, count 2 2006.175.07:53:39.92#ibcon#read 3, iclass 35, count 2 2006.175.07:53:39.92#ibcon#about to read 4, iclass 35, count 2 2006.175.07:53:39.92#ibcon#read 4, iclass 35, count 2 2006.175.07:53:39.92#ibcon#about to read 5, iclass 35, count 2 2006.175.07:53:39.92#ibcon#read 5, iclass 35, count 2 2006.175.07:53:39.92#ibcon#about to read 6, iclass 35, count 2 2006.175.07:53:39.92#ibcon#read 6, iclass 35, count 2 2006.175.07:53:39.92#ibcon#end of sib2, iclass 35, count 2 2006.175.07:53:39.92#ibcon#*after write, iclass 35, count 2 2006.175.07:53:39.92#ibcon#*before return 0, iclass 35, count 2 2006.175.07:53:39.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:53:39.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.175.07:53:39.92#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.175.07:53:39.92#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:39.92#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:53:40.04#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:53:40.04#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:53:40.04#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:53:40.04#ibcon#first serial, iclass 35, count 0 2006.175.07:53:40.04#ibcon#enter sib2, iclass 35, count 0 2006.175.07:53:40.04#ibcon#flushed, iclass 35, count 0 2006.175.07:53:40.04#ibcon#about to write, iclass 35, count 0 2006.175.07:53:40.04#ibcon#wrote, iclass 35, count 0 2006.175.07:53:40.04#ibcon#about to read 3, iclass 35, count 0 2006.175.07:53:40.06#ibcon#read 3, iclass 35, count 0 2006.175.07:53:40.06#ibcon#about to read 4, iclass 35, count 0 2006.175.07:53:40.06#ibcon#read 4, iclass 35, count 0 2006.175.07:53:40.06#ibcon#about to read 5, iclass 35, count 0 2006.175.07:53:40.06#ibcon#read 5, iclass 35, count 0 2006.175.07:53:40.06#ibcon#about to read 6, iclass 35, count 0 2006.175.07:53:40.06#ibcon#read 6, iclass 35, count 0 2006.175.07:53:40.06#ibcon#end of sib2, iclass 35, count 0 2006.175.07:53:40.06#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:53:40.06#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:53:40.06#ibcon#[25=USB\r\n] 2006.175.07:53:40.06#ibcon#*before write, iclass 35, count 0 2006.175.07:53:40.06#ibcon#enter sib2, iclass 35, count 0 2006.175.07:53:40.06#ibcon#flushed, iclass 35, count 0 2006.175.07:53:40.06#ibcon#about to write, iclass 35, count 0 2006.175.07:53:40.06#ibcon#wrote, iclass 35, count 0 2006.175.07:53:40.06#ibcon#about to read 3, iclass 35, count 0 2006.175.07:53:40.09#ibcon#read 3, iclass 35, count 0 2006.175.07:53:40.09#ibcon#about to read 4, iclass 35, count 0 2006.175.07:53:40.09#ibcon#read 4, iclass 35, count 0 2006.175.07:53:40.09#ibcon#about to read 5, iclass 35, count 0 2006.175.07:53:40.09#ibcon#read 5, iclass 35, count 0 2006.175.07:53:40.09#ibcon#about to read 6, iclass 35, count 0 2006.175.07:53:40.09#ibcon#read 6, iclass 35, count 0 2006.175.07:53:40.09#ibcon#end of sib2, iclass 35, count 0 2006.175.07:53:40.09#ibcon#*after write, iclass 35, count 0 2006.175.07:53:40.09#ibcon#*before return 0, iclass 35, count 0 2006.175.07:53:40.09#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:53:40.09#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.175.07:53:40.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:53:40.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:53:40.09$vc4f8/valo=7,832.99 2006.175.07:53:40.09#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.07:53:40.09#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.07:53:40.09#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:40.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:53:40.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:53:40.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:53:40.09#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:53:40.09#ibcon#first serial, iclass 37, count 0 2006.175.07:53:40.09#ibcon#enter sib2, iclass 37, count 0 2006.175.07:53:40.09#ibcon#flushed, iclass 37, count 0 2006.175.07:53:40.09#ibcon#about to write, iclass 37, count 0 2006.175.07:53:40.09#ibcon#wrote, iclass 37, count 0 2006.175.07:53:40.09#ibcon#about to read 3, iclass 37, count 0 2006.175.07:53:40.11#ibcon#read 3, iclass 37, count 0 2006.175.07:53:40.11#ibcon#about to read 4, iclass 37, count 0 2006.175.07:53:40.11#ibcon#read 4, iclass 37, count 0 2006.175.07:53:40.11#ibcon#about to read 5, iclass 37, count 0 2006.175.07:53:40.11#ibcon#read 5, iclass 37, count 0 2006.175.07:53:40.11#ibcon#about to read 6, iclass 37, count 0 2006.175.07:53:40.11#ibcon#read 6, iclass 37, count 0 2006.175.07:53:40.11#ibcon#end of sib2, iclass 37, count 0 2006.175.07:53:40.11#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:53:40.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:53:40.11#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:53:40.11#ibcon#*before write, iclass 37, count 0 2006.175.07:53:40.11#ibcon#enter sib2, iclass 37, count 0 2006.175.07:53:40.11#ibcon#flushed, iclass 37, count 0 2006.175.07:53:40.11#ibcon#about to write, iclass 37, count 0 2006.175.07:53:40.11#ibcon#wrote, iclass 37, count 0 2006.175.07:53:40.11#ibcon#about to read 3, iclass 37, count 0 2006.175.07:53:40.15#ibcon#read 3, iclass 37, count 0 2006.175.07:53:40.15#ibcon#about to read 4, iclass 37, count 0 2006.175.07:53:40.15#ibcon#read 4, iclass 37, count 0 2006.175.07:53:40.15#ibcon#about to read 5, iclass 37, count 0 2006.175.07:53:40.15#ibcon#read 5, iclass 37, count 0 2006.175.07:53:40.15#ibcon#about to read 6, iclass 37, count 0 2006.175.07:53:40.15#ibcon#read 6, iclass 37, count 0 2006.175.07:53:40.15#ibcon#end of sib2, iclass 37, count 0 2006.175.07:53:40.15#ibcon#*after write, iclass 37, count 0 2006.175.07:53:40.15#ibcon#*before return 0, iclass 37, count 0 2006.175.07:53:40.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:53:40.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.07:53:40.15#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:53:40.15#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:53:40.15$vc4f8/va=7,6 2006.175.07:53:40.15#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.175.07:53:40.15#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.175.07:53:40.15#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:40.15#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:53:40.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:53:40.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:53:40.21#ibcon#enter wrdev, iclass 39, count 2 2006.175.07:53:40.21#ibcon#first serial, iclass 39, count 2 2006.175.07:53:40.21#ibcon#enter sib2, iclass 39, count 2 2006.175.07:53:40.21#ibcon#flushed, iclass 39, count 2 2006.175.07:53:40.21#ibcon#about to write, iclass 39, count 2 2006.175.07:53:40.21#ibcon#wrote, iclass 39, count 2 2006.175.07:53:40.21#ibcon#about to read 3, iclass 39, count 2 2006.175.07:53:40.23#ibcon#read 3, iclass 39, count 2 2006.175.07:53:40.23#ibcon#about to read 4, iclass 39, count 2 2006.175.07:53:40.23#ibcon#read 4, iclass 39, count 2 2006.175.07:53:40.23#ibcon#about to read 5, iclass 39, count 2 2006.175.07:53:40.23#ibcon#read 5, iclass 39, count 2 2006.175.07:53:40.23#ibcon#about to read 6, iclass 39, count 2 2006.175.07:53:40.23#ibcon#read 6, iclass 39, count 2 2006.175.07:53:40.23#ibcon#end of sib2, iclass 39, count 2 2006.175.07:53:40.23#ibcon#*mode == 0, iclass 39, count 2 2006.175.07:53:40.23#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.175.07:53:40.23#ibcon#[25=AT07-06\r\n] 2006.175.07:53:40.23#ibcon#*before write, iclass 39, count 2 2006.175.07:53:40.23#ibcon#enter sib2, iclass 39, count 2 2006.175.07:53:40.23#ibcon#flushed, iclass 39, count 2 2006.175.07:53:40.23#ibcon#about to write, iclass 39, count 2 2006.175.07:53:40.23#ibcon#wrote, iclass 39, count 2 2006.175.07:53:40.23#ibcon#about to read 3, iclass 39, count 2 2006.175.07:53:40.26#ibcon#read 3, iclass 39, count 2 2006.175.07:53:40.26#ibcon#about to read 4, iclass 39, count 2 2006.175.07:53:40.26#ibcon#read 4, iclass 39, count 2 2006.175.07:53:40.26#ibcon#about to read 5, iclass 39, count 2 2006.175.07:53:40.26#ibcon#read 5, iclass 39, count 2 2006.175.07:53:40.26#ibcon#about to read 6, iclass 39, count 2 2006.175.07:53:40.26#ibcon#read 6, iclass 39, count 2 2006.175.07:53:40.26#ibcon#end of sib2, iclass 39, count 2 2006.175.07:53:40.26#ibcon#*after write, iclass 39, count 2 2006.175.07:53:40.26#ibcon#*before return 0, iclass 39, count 2 2006.175.07:53:40.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:53:40.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.175.07:53:40.26#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.175.07:53:40.26#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:40.26#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:53:40.38#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:53:40.38#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:53:40.38#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:53:40.38#ibcon#first serial, iclass 39, count 0 2006.175.07:53:40.38#ibcon#enter sib2, iclass 39, count 0 2006.175.07:53:40.38#ibcon#flushed, iclass 39, count 0 2006.175.07:53:40.38#ibcon#about to write, iclass 39, count 0 2006.175.07:53:40.38#ibcon#wrote, iclass 39, count 0 2006.175.07:53:40.38#ibcon#about to read 3, iclass 39, count 0 2006.175.07:53:40.40#ibcon#read 3, iclass 39, count 0 2006.175.07:53:40.40#ibcon#about to read 4, iclass 39, count 0 2006.175.07:53:40.40#ibcon#read 4, iclass 39, count 0 2006.175.07:53:40.40#ibcon#about to read 5, iclass 39, count 0 2006.175.07:53:40.40#ibcon#read 5, iclass 39, count 0 2006.175.07:53:40.40#ibcon#about to read 6, iclass 39, count 0 2006.175.07:53:40.40#ibcon#read 6, iclass 39, count 0 2006.175.07:53:40.40#ibcon#end of sib2, iclass 39, count 0 2006.175.07:53:40.40#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:53:40.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:53:40.40#ibcon#[25=USB\r\n] 2006.175.07:53:40.40#ibcon#*before write, iclass 39, count 0 2006.175.07:53:40.40#ibcon#enter sib2, iclass 39, count 0 2006.175.07:53:40.40#ibcon#flushed, iclass 39, count 0 2006.175.07:53:40.40#ibcon#about to write, iclass 39, count 0 2006.175.07:53:40.40#ibcon#wrote, iclass 39, count 0 2006.175.07:53:40.40#ibcon#about to read 3, iclass 39, count 0 2006.175.07:53:40.43#ibcon#read 3, iclass 39, count 0 2006.175.07:53:40.43#ibcon#about to read 4, iclass 39, count 0 2006.175.07:53:40.43#ibcon#read 4, iclass 39, count 0 2006.175.07:53:40.43#ibcon#about to read 5, iclass 39, count 0 2006.175.07:53:40.43#ibcon#read 5, iclass 39, count 0 2006.175.07:53:40.43#ibcon#about to read 6, iclass 39, count 0 2006.175.07:53:40.43#ibcon#read 6, iclass 39, count 0 2006.175.07:53:40.43#ibcon#end of sib2, iclass 39, count 0 2006.175.07:53:40.43#ibcon#*after write, iclass 39, count 0 2006.175.07:53:40.43#ibcon#*before return 0, iclass 39, count 0 2006.175.07:53:40.43#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:53:40.43#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.175.07:53:40.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:53:40.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:53:40.43$vc4f8/valo=8,852.99 2006.175.07:53:40.43#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.07:53:40.43#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.07:53:40.43#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:40.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:53:40.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:53:40.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:53:40.43#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:53:40.43#ibcon#first serial, iclass 3, count 0 2006.175.07:53:40.43#ibcon#enter sib2, iclass 3, count 0 2006.175.07:53:40.43#ibcon#flushed, iclass 3, count 0 2006.175.07:53:40.43#ibcon#about to write, iclass 3, count 0 2006.175.07:53:40.43#ibcon#wrote, iclass 3, count 0 2006.175.07:53:40.43#ibcon#about to read 3, iclass 3, count 0 2006.175.07:53:40.45#ibcon#read 3, iclass 3, count 0 2006.175.07:53:40.45#ibcon#about to read 4, iclass 3, count 0 2006.175.07:53:40.45#ibcon#read 4, iclass 3, count 0 2006.175.07:53:40.45#ibcon#about to read 5, iclass 3, count 0 2006.175.07:53:40.45#ibcon#read 5, iclass 3, count 0 2006.175.07:53:40.45#ibcon#about to read 6, iclass 3, count 0 2006.175.07:53:40.45#ibcon#read 6, iclass 3, count 0 2006.175.07:53:40.45#ibcon#end of sib2, iclass 3, count 0 2006.175.07:53:40.45#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:53:40.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:53:40.45#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:53:40.45#ibcon#*before write, iclass 3, count 0 2006.175.07:53:40.45#ibcon#enter sib2, iclass 3, count 0 2006.175.07:53:40.45#ibcon#flushed, iclass 3, count 0 2006.175.07:53:40.45#ibcon#about to write, iclass 3, count 0 2006.175.07:53:40.45#ibcon#wrote, iclass 3, count 0 2006.175.07:53:40.45#ibcon#about to read 3, iclass 3, count 0 2006.175.07:53:40.49#ibcon#read 3, iclass 3, count 0 2006.175.07:53:40.49#ibcon#about to read 4, iclass 3, count 0 2006.175.07:53:40.49#ibcon#read 4, iclass 3, count 0 2006.175.07:53:40.49#ibcon#about to read 5, iclass 3, count 0 2006.175.07:53:40.49#ibcon#read 5, iclass 3, count 0 2006.175.07:53:40.49#ibcon#about to read 6, iclass 3, count 0 2006.175.07:53:40.49#ibcon#read 6, iclass 3, count 0 2006.175.07:53:40.49#ibcon#end of sib2, iclass 3, count 0 2006.175.07:53:40.49#ibcon#*after write, iclass 3, count 0 2006.175.07:53:40.49#ibcon#*before return 0, iclass 3, count 0 2006.175.07:53:40.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:53:40.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.07:53:40.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:53:40.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:53:40.49$vc4f8/va=8,6 2006.175.07:53:40.49#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.175.07:53:40.49#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.175.07:53:40.49#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:40.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:53:40.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:53:40.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:53:40.55#ibcon#enter wrdev, iclass 5, count 2 2006.175.07:53:40.55#ibcon#first serial, iclass 5, count 2 2006.175.07:53:40.55#ibcon#enter sib2, iclass 5, count 2 2006.175.07:53:40.55#ibcon#flushed, iclass 5, count 2 2006.175.07:53:40.55#ibcon#about to write, iclass 5, count 2 2006.175.07:53:40.55#ibcon#wrote, iclass 5, count 2 2006.175.07:53:40.55#ibcon#about to read 3, iclass 5, count 2 2006.175.07:53:40.57#ibcon#read 3, iclass 5, count 2 2006.175.07:53:40.57#ibcon#about to read 4, iclass 5, count 2 2006.175.07:53:40.57#ibcon#read 4, iclass 5, count 2 2006.175.07:53:40.57#ibcon#about to read 5, iclass 5, count 2 2006.175.07:53:40.57#ibcon#read 5, iclass 5, count 2 2006.175.07:53:40.57#ibcon#about to read 6, iclass 5, count 2 2006.175.07:53:40.57#ibcon#read 6, iclass 5, count 2 2006.175.07:53:40.57#ibcon#end of sib2, iclass 5, count 2 2006.175.07:53:40.57#ibcon#*mode == 0, iclass 5, count 2 2006.175.07:53:40.57#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.175.07:53:40.57#ibcon#[25=AT08-06\r\n] 2006.175.07:53:40.57#ibcon#*before write, iclass 5, count 2 2006.175.07:53:40.57#ibcon#enter sib2, iclass 5, count 2 2006.175.07:53:40.57#ibcon#flushed, iclass 5, count 2 2006.175.07:53:40.57#ibcon#about to write, iclass 5, count 2 2006.175.07:53:40.57#ibcon#wrote, iclass 5, count 2 2006.175.07:53:40.57#ibcon#about to read 3, iclass 5, count 2 2006.175.07:53:40.60#ibcon#read 3, iclass 5, count 2 2006.175.07:53:40.60#ibcon#about to read 4, iclass 5, count 2 2006.175.07:53:40.60#ibcon#read 4, iclass 5, count 2 2006.175.07:53:40.60#ibcon#about to read 5, iclass 5, count 2 2006.175.07:53:40.60#ibcon#read 5, iclass 5, count 2 2006.175.07:53:40.60#ibcon#about to read 6, iclass 5, count 2 2006.175.07:53:40.60#ibcon#read 6, iclass 5, count 2 2006.175.07:53:40.60#ibcon#end of sib2, iclass 5, count 2 2006.175.07:53:40.60#ibcon#*after write, iclass 5, count 2 2006.175.07:53:40.60#ibcon#*before return 0, iclass 5, count 2 2006.175.07:53:40.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:53:40.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.175.07:53:40.60#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.175.07:53:40.60#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:40.60#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:53:40.72#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:53:40.72#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:53:40.72#ibcon#enter wrdev, iclass 5, count 0 2006.175.07:53:40.72#ibcon#first serial, iclass 5, count 0 2006.175.07:53:40.72#ibcon#enter sib2, iclass 5, count 0 2006.175.07:53:40.72#ibcon#flushed, iclass 5, count 0 2006.175.07:53:40.72#ibcon#about to write, iclass 5, count 0 2006.175.07:53:40.72#ibcon#wrote, iclass 5, count 0 2006.175.07:53:40.72#ibcon#about to read 3, iclass 5, count 0 2006.175.07:53:40.74#ibcon#read 3, iclass 5, count 0 2006.175.07:53:40.74#ibcon#about to read 4, iclass 5, count 0 2006.175.07:53:40.74#ibcon#read 4, iclass 5, count 0 2006.175.07:53:40.74#ibcon#about to read 5, iclass 5, count 0 2006.175.07:53:40.74#ibcon#read 5, iclass 5, count 0 2006.175.07:53:40.74#ibcon#about to read 6, iclass 5, count 0 2006.175.07:53:40.74#ibcon#read 6, iclass 5, count 0 2006.175.07:53:40.74#ibcon#end of sib2, iclass 5, count 0 2006.175.07:53:40.74#ibcon#*mode == 0, iclass 5, count 0 2006.175.07:53:40.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.07:53:40.74#ibcon#[25=USB\r\n] 2006.175.07:53:40.74#ibcon#*before write, iclass 5, count 0 2006.175.07:53:40.74#ibcon#enter sib2, iclass 5, count 0 2006.175.07:53:40.74#ibcon#flushed, iclass 5, count 0 2006.175.07:53:40.74#ibcon#about to write, iclass 5, count 0 2006.175.07:53:40.74#ibcon#wrote, iclass 5, count 0 2006.175.07:53:40.74#ibcon#about to read 3, iclass 5, count 0 2006.175.07:53:40.77#ibcon#read 3, iclass 5, count 0 2006.175.07:53:40.77#ibcon#about to read 4, iclass 5, count 0 2006.175.07:53:40.77#ibcon#read 4, iclass 5, count 0 2006.175.07:53:40.77#ibcon#about to read 5, iclass 5, count 0 2006.175.07:53:40.77#ibcon#read 5, iclass 5, count 0 2006.175.07:53:40.77#ibcon#about to read 6, iclass 5, count 0 2006.175.07:53:40.77#ibcon#read 6, iclass 5, count 0 2006.175.07:53:40.77#ibcon#end of sib2, iclass 5, count 0 2006.175.07:53:40.77#ibcon#*after write, iclass 5, count 0 2006.175.07:53:40.77#ibcon#*before return 0, iclass 5, count 0 2006.175.07:53:40.77#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:53:40.77#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.175.07:53:40.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.07:53:40.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.07:53:40.77$vc4f8/vblo=1,632.99 2006.175.07:53:40.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.07:53:40.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.07:53:40.77#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:40.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:53:40.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:53:40.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:53:40.77#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:53:40.77#ibcon#first serial, iclass 7, count 0 2006.175.07:53:40.77#ibcon#enter sib2, iclass 7, count 0 2006.175.07:53:40.77#ibcon#flushed, iclass 7, count 0 2006.175.07:53:40.77#ibcon#about to write, iclass 7, count 0 2006.175.07:53:40.77#ibcon#wrote, iclass 7, count 0 2006.175.07:53:40.77#ibcon#about to read 3, iclass 7, count 0 2006.175.07:53:40.79#ibcon#read 3, iclass 7, count 0 2006.175.07:53:40.79#ibcon#about to read 4, iclass 7, count 0 2006.175.07:53:40.79#ibcon#read 4, iclass 7, count 0 2006.175.07:53:40.79#ibcon#about to read 5, iclass 7, count 0 2006.175.07:53:40.79#ibcon#read 5, iclass 7, count 0 2006.175.07:53:40.79#ibcon#about to read 6, iclass 7, count 0 2006.175.07:53:40.79#ibcon#read 6, iclass 7, count 0 2006.175.07:53:40.79#ibcon#end of sib2, iclass 7, count 0 2006.175.07:53:40.79#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:53:40.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:53:40.79#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:53:40.79#ibcon#*before write, iclass 7, count 0 2006.175.07:53:40.79#ibcon#enter sib2, iclass 7, count 0 2006.175.07:53:40.79#ibcon#flushed, iclass 7, count 0 2006.175.07:53:40.79#ibcon#about to write, iclass 7, count 0 2006.175.07:53:40.79#ibcon#wrote, iclass 7, count 0 2006.175.07:53:40.79#ibcon#about to read 3, iclass 7, count 0 2006.175.07:53:40.83#ibcon#read 3, iclass 7, count 0 2006.175.07:53:40.83#ibcon#about to read 4, iclass 7, count 0 2006.175.07:53:40.83#ibcon#read 4, iclass 7, count 0 2006.175.07:53:40.83#ibcon#about to read 5, iclass 7, count 0 2006.175.07:53:40.83#ibcon#read 5, iclass 7, count 0 2006.175.07:53:40.83#ibcon#about to read 6, iclass 7, count 0 2006.175.07:53:40.83#ibcon#read 6, iclass 7, count 0 2006.175.07:53:40.83#ibcon#end of sib2, iclass 7, count 0 2006.175.07:53:40.83#ibcon#*after write, iclass 7, count 0 2006.175.07:53:40.83#ibcon#*before return 0, iclass 7, count 0 2006.175.07:53:40.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:53:40.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.07:53:40.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:53:40.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:53:40.83$vc4f8/vb=1,4 2006.175.07:53:40.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.175.07:53:40.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.175.07:53:40.83#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:40.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:53:40.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:53:40.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:53:40.83#ibcon#enter wrdev, iclass 11, count 2 2006.175.07:53:40.83#ibcon#first serial, iclass 11, count 2 2006.175.07:53:40.83#ibcon#enter sib2, iclass 11, count 2 2006.175.07:53:40.83#ibcon#flushed, iclass 11, count 2 2006.175.07:53:40.83#ibcon#about to write, iclass 11, count 2 2006.175.07:53:40.83#ibcon#wrote, iclass 11, count 2 2006.175.07:53:40.83#ibcon#about to read 3, iclass 11, count 2 2006.175.07:53:40.85#ibcon#read 3, iclass 11, count 2 2006.175.07:53:40.85#ibcon#about to read 4, iclass 11, count 2 2006.175.07:53:40.85#ibcon#read 4, iclass 11, count 2 2006.175.07:53:40.85#ibcon#about to read 5, iclass 11, count 2 2006.175.07:53:40.85#ibcon#read 5, iclass 11, count 2 2006.175.07:53:40.85#ibcon#about to read 6, iclass 11, count 2 2006.175.07:53:40.85#ibcon#read 6, iclass 11, count 2 2006.175.07:53:40.85#ibcon#end of sib2, iclass 11, count 2 2006.175.07:53:40.85#ibcon#*mode == 0, iclass 11, count 2 2006.175.07:53:40.85#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.175.07:53:40.85#ibcon#[27=AT01-04\r\n] 2006.175.07:53:40.85#ibcon#*before write, iclass 11, count 2 2006.175.07:53:40.85#ibcon#enter sib2, iclass 11, count 2 2006.175.07:53:40.85#ibcon#flushed, iclass 11, count 2 2006.175.07:53:40.85#ibcon#about to write, iclass 11, count 2 2006.175.07:53:40.85#ibcon#wrote, iclass 11, count 2 2006.175.07:53:40.85#ibcon#about to read 3, iclass 11, count 2 2006.175.07:53:40.88#ibcon#read 3, iclass 11, count 2 2006.175.07:53:40.88#ibcon#about to read 4, iclass 11, count 2 2006.175.07:53:40.88#ibcon#read 4, iclass 11, count 2 2006.175.07:53:40.88#ibcon#about to read 5, iclass 11, count 2 2006.175.07:53:40.88#ibcon#read 5, iclass 11, count 2 2006.175.07:53:40.88#ibcon#about to read 6, iclass 11, count 2 2006.175.07:53:40.88#ibcon#read 6, iclass 11, count 2 2006.175.07:53:40.88#ibcon#end of sib2, iclass 11, count 2 2006.175.07:53:40.88#ibcon#*after write, iclass 11, count 2 2006.175.07:53:40.88#ibcon#*before return 0, iclass 11, count 2 2006.175.07:53:40.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:53:40.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.175.07:53:40.88#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.175.07:53:40.88#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:40.88#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:53:41.00#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:53:41.00#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:53:41.00#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:53:41.00#ibcon#first serial, iclass 11, count 0 2006.175.07:53:41.00#ibcon#enter sib2, iclass 11, count 0 2006.175.07:53:41.00#ibcon#flushed, iclass 11, count 0 2006.175.07:53:41.00#ibcon#about to write, iclass 11, count 0 2006.175.07:53:41.00#ibcon#wrote, iclass 11, count 0 2006.175.07:53:41.00#ibcon#about to read 3, iclass 11, count 0 2006.175.07:53:41.02#ibcon#read 3, iclass 11, count 0 2006.175.07:53:41.02#ibcon#about to read 4, iclass 11, count 0 2006.175.07:53:41.02#ibcon#read 4, iclass 11, count 0 2006.175.07:53:41.02#ibcon#about to read 5, iclass 11, count 0 2006.175.07:53:41.02#ibcon#read 5, iclass 11, count 0 2006.175.07:53:41.02#ibcon#about to read 6, iclass 11, count 0 2006.175.07:53:41.02#ibcon#read 6, iclass 11, count 0 2006.175.07:53:41.02#ibcon#end of sib2, iclass 11, count 0 2006.175.07:53:41.02#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:53:41.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:53:41.02#ibcon#[27=USB\r\n] 2006.175.07:53:41.02#ibcon#*before write, iclass 11, count 0 2006.175.07:53:41.02#ibcon#enter sib2, iclass 11, count 0 2006.175.07:53:41.02#ibcon#flushed, iclass 11, count 0 2006.175.07:53:41.02#ibcon#about to write, iclass 11, count 0 2006.175.07:53:41.02#ibcon#wrote, iclass 11, count 0 2006.175.07:53:41.02#ibcon#about to read 3, iclass 11, count 0 2006.175.07:53:41.05#ibcon#read 3, iclass 11, count 0 2006.175.07:53:41.05#ibcon#about to read 4, iclass 11, count 0 2006.175.07:53:41.05#ibcon#read 4, iclass 11, count 0 2006.175.07:53:41.05#ibcon#about to read 5, iclass 11, count 0 2006.175.07:53:41.05#ibcon#read 5, iclass 11, count 0 2006.175.07:53:41.05#ibcon#about to read 6, iclass 11, count 0 2006.175.07:53:41.05#ibcon#read 6, iclass 11, count 0 2006.175.07:53:41.05#ibcon#end of sib2, iclass 11, count 0 2006.175.07:53:41.05#ibcon#*after write, iclass 11, count 0 2006.175.07:53:41.05#ibcon#*before return 0, iclass 11, count 0 2006.175.07:53:41.05#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:53:41.05#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.175.07:53:41.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:53:41.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:53:41.05$vc4f8/vblo=2,640.99 2006.175.07:53:41.05#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.175.07:53:41.05#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.175.07:53:41.05#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:41.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:41.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:41.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:41.05#ibcon#enter wrdev, iclass 13, count 0 2006.175.07:53:41.05#ibcon#first serial, iclass 13, count 0 2006.175.07:53:41.05#ibcon#enter sib2, iclass 13, count 0 2006.175.07:53:41.05#ibcon#flushed, iclass 13, count 0 2006.175.07:53:41.05#ibcon#about to write, iclass 13, count 0 2006.175.07:53:41.05#ibcon#wrote, iclass 13, count 0 2006.175.07:53:41.05#ibcon#about to read 3, iclass 13, count 0 2006.175.07:53:41.07#ibcon#read 3, iclass 13, count 0 2006.175.07:53:41.07#ibcon#about to read 4, iclass 13, count 0 2006.175.07:53:41.07#ibcon#read 4, iclass 13, count 0 2006.175.07:53:41.07#ibcon#about to read 5, iclass 13, count 0 2006.175.07:53:41.07#ibcon#read 5, iclass 13, count 0 2006.175.07:53:41.07#ibcon#about to read 6, iclass 13, count 0 2006.175.07:53:41.07#ibcon#read 6, iclass 13, count 0 2006.175.07:53:41.07#ibcon#end of sib2, iclass 13, count 0 2006.175.07:53:41.07#ibcon#*mode == 0, iclass 13, count 0 2006.175.07:53:41.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.07:53:41.07#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:53:41.07#ibcon#*before write, iclass 13, count 0 2006.175.07:53:41.07#ibcon#enter sib2, iclass 13, count 0 2006.175.07:53:41.07#ibcon#flushed, iclass 13, count 0 2006.175.07:53:41.07#ibcon#about to write, iclass 13, count 0 2006.175.07:53:41.07#ibcon#wrote, iclass 13, count 0 2006.175.07:53:41.07#ibcon#about to read 3, iclass 13, count 0 2006.175.07:53:41.11#ibcon#read 3, iclass 13, count 0 2006.175.07:53:41.11#ibcon#about to read 4, iclass 13, count 0 2006.175.07:53:41.11#ibcon#read 4, iclass 13, count 0 2006.175.07:53:41.11#ibcon#about to read 5, iclass 13, count 0 2006.175.07:53:41.11#ibcon#read 5, iclass 13, count 0 2006.175.07:53:41.11#ibcon#about to read 6, iclass 13, count 0 2006.175.07:53:41.11#ibcon#read 6, iclass 13, count 0 2006.175.07:53:41.11#ibcon#end of sib2, iclass 13, count 0 2006.175.07:53:41.11#ibcon#*after write, iclass 13, count 0 2006.175.07:53:41.11#ibcon#*before return 0, iclass 13, count 0 2006.175.07:53:41.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:41.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.175.07:53:41.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.07:53:41.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.07:53:41.11$vc4f8/vb=2,4 2006.175.07:53:41.11#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.175.07:53:41.11#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.175.07:53:41.11#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:41.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:41.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:41.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:41.17#ibcon#enter wrdev, iclass 15, count 2 2006.175.07:53:41.17#ibcon#first serial, iclass 15, count 2 2006.175.07:53:41.17#ibcon#enter sib2, iclass 15, count 2 2006.175.07:53:41.17#ibcon#flushed, iclass 15, count 2 2006.175.07:53:41.17#ibcon#about to write, iclass 15, count 2 2006.175.07:53:41.17#ibcon#wrote, iclass 15, count 2 2006.175.07:53:41.17#ibcon#about to read 3, iclass 15, count 2 2006.175.07:53:41.19#ibcon#read 3, iclass 15, count 2 2006.175.07:53:41.19#ibcon#about to read 4, iclass 15, count 2 2006.175.07:53:41.19#ibcon#read 4, iclass 15, count 2 2006.175.07:53:41.19#ibcon#about to read 5, iclass 15, count 2 2006.175.07:53:41.19#ibcon#read 5, iclass 15, count 2 2006.175.07:53:41.19#ibcon#about to read 6, iclass 15, count 2 2006.175.07:53:41.19#ibcon#read 6, iclass 15, count 2 2006.175.07:53:41.19#ibcon#end of sib2, iclass 15, count 2 2006.175.07:53:41.19#ibcon#*mode == 0, iclass 15, count 2 2006.175.07:53:41.19#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.175.07:53:41.19#ibcon#[27=AT02-04\r\n] 2006.175.07:53:41.19#ibcon#*before write, iclass 15, count 2 2006.175.07:53:41.19#ibcon#enter sib2, iclass 15, count 2 2006.175.07:53:41.19#ibcon#flushed, iclass 15, count 2 2006.175.07:53:41.19#ibcon#about to write, iclass 15, count 2 2006.175.07:53:41.19#ibcon#wrote, iclass 15, count 2 2006.175.07:53:41.19#ibcon#about to read 3, iclass 15, count 2 2006.175.07:53:41.23#ibcon#read 3, iclass 15, count 2 2006.175.07:53:41.23#ibcon#about to read 4, iclass 15, count 2 2006.175.07:53:41.23#ibcon#read 4, iclass 15, count 2 2006.175.07:53:41.23#ibcon#about to read 5, iclass 15, count 2 2006.175.07:53:41.23#ibcon#read 5, iclass 15, count 2 2006.175.07:53:41.23#ibcon#about to read 6, iclass 15, count 2 2006.175.07:53:41.23#ibcon#read 6, iclass 15, count 2 2006.175.07:53:41.23#ibcon#end of sib2, iclass 15, count 2 2006.175.07:53:41.23#ibcon#*after write, iclass 15, count 2 2006.175.07:53:41.23#ibcon#*before return 0, iclass 15, count 2 2006.175.07:53:41.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:41.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.175.07:53:41.23#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.175.07:53:41.23#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:41.23#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:41.35#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:41.35#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:41.35#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:53:41.35#ibcon#first serial, iclass 15, count 0 2006.175.07:53:41.35#ibcon#enter sib2, iclass 15, count 0 2006.175.07:53:41.35#ibcon#flushed, iclass 15, count 0 2006.175.07:53:41.35#ibcon#about to write, iclass 15, count 0 2006.175.07:53:41.35#ibcon#wrote, iclass 15, count 0 2006.175.07:53:41.35#ibcon#about to read 3, iclass 15, count 0 2006.175.07:53:41.37#ibcon#read 3, iclass 15, count 0 2006.175.07:53:41.37#ibcon#about to read 4, iclass 15, count 0 2006.175.07:53:41.37#ibcon#read 4, iclass 15, count 0 2006.175.07:53:41.37#ibcon#about to read 5, iclass 15, count 0 2006.175.07:53:41.37#ibcon#read 5, iclass 15, count 0 2006.175.07:53:41.37#ibcon#about to read 6, iclass 15, count 0 2006.175.07:53:41.37#ibcon#read 6, iclass 15, count 0 2006.175.07:53:41.37#ibcon#end of sib2, iclass 15, count 0 2006.175.07:53:41.37#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:53:41.37#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:53:41.37#ibcon#[27=USB\r\n] 2006.175.07:53:41.37#ibcon#*before write, iclass 15, count 0 2006.175.07:53:41.37#ibcon#enter sib2, iclass 15, count 0 2006.175.07:53:41.37#ibcon#flushed, iclass 15, count 0 2006.175.07:53:41.37#ibcon#about to write, iclass 15, count 0 2006.175.07:53:41.37#ibcon#wrote, iclass 15, count 0 2006.175.07:53:41.37#ibcon#about to read 3, iclass 15, count 0 2006.175.07:53:41.40#ibcon#read 3, iclass 15, count 0 2006.175.07:53:41.40#ibcon#about to read 4, iclass 15, count 0 2006.175.07:53:41.40#ibcon#read 4, iclass 15, count 0 2006.175.07:53:41.40#ibcon#about to read 5, iclass 15, count 0 2006.175.07:53:41.40#ibcon#read 5, iclass 15, count 0 2006.175.07:53:41.40#ibcon#about to read 6, iclass 15, count 0 2006.175.07:53:41.40#ibcon#read 6, iclass 15, count 0 2006.175.07:53:41.40#ibcon#end of sib2, iclass 15, count 0 2006.175.07:53:41.40#ibcon#*after write, iclass 15, count 0 2006.175.07:53:41.40#ibcon#*before return 0, iclass 15, count 0 2006.175.07:53:41.40#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:41.40#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.175.07:53:41.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:53:41.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:53:41.40$vc4f8/vblo=3,656.99 2006.175.07:53:41.40#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.07:53:41.40#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.07:53:41.40#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:41.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:41.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:41.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:41.40#ibcon#enter wrdev, iclass 17, count 0 2006.175.07:53:41.40#ibcon#first serial, iclass 17, count 0 2006.175.07:53:41.40#ibcon#enter sib2, iclass 17, count 0 2006.175.07:53:41.40#ibcon#flushed, iclass 17, count 0 2006.175.07:53:41.40#ibcon#about to write, iclass 17, count 0 2006.175.07:53:41.40#ibcon#wrote, iclass 17, count 0 2006.175.07:53:41.40#ibcon#about to read 3, iclass 17, count 0 2006.175.07:53:41.42#ibcon#read 3, iclass 17, count 0 2006.175.07:53:41.42#ibcon#about to read 4, iclass 17, count 0 2006.175.07:53:41.42#ibcon#read 4, iclass 17, count 0 2006.175.07:53:41.42#ibcon#about to read 5, iclass 17, count 0 2006.175.07:53:41.42#ibcon#read 5, iclass 17, count 0 2006.175.07:53:41.42#ibcon#about to read 6, iclass 17, count 0 2006.175.07:53:41.42#ibcon#read 6, iclass 17, count 0 2006.175.07:53:41.42#ibcon#end of sib2, iclass 17, count 0 2006.175.07:53:41.42#ibcon#*mode == 0, iclass 17, count 0 2006.175.07:53:41.42#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.07:53:41.42#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:53:41.42#ibcon#*before write, iclass 17, count 0 2006.175.07:53:41.42#ibcon#enter sib2, iclass 17, count 0 2006.175.07:53:41.42#ibcon#flushed, iclass 17, count 0 2006.175.07:53:41.42#ibcon#about to write, iclass 17, count 0 2006.175.07:53:41.42#ibcon#wrote, iclass 17, count 0 2006.175.07:53:41.42#ibcon#about to read 3, iclass 17, count 0 2006.175.07:53:41.46#ibcon#read 3, iclass 17, count 0 2006.175.07:53:41.46#ibcon#about to read 4, iclass 17, count 0 2006.175.07:53:41.46#ibcon#read 4, iclass 17, count 0 2006.175.07:53:41.46#ibcon#about to read 5, iclass 17, count 0 2006.175.07:53:41.46#ibcon#read 5, iclass 17, count 0 2006.175.07:53:41.46#ibcon#about to read 6, iclass 17, count 0 2006.175.07:53:41.46#ibcon#read 6, iclass 17, count 0 2006.175.07:53:41.46#ibcon#end of sib2, iclass 17, count 0 2006.175.07:53:41.46#ibcon#*after write, iclass 17, count 0 2006.175.07:53:41.46#ibcon#*before return 0, iclass 17, count 0 2006.175.07:53:41.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:41.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.07:53:41.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.07:53:41.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.07:53:41.46$vc4f8/vb=3,4 2006.175.07:53:41.46#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.175.07:53:41.46#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.175.07:53:41.46#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:41.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:41.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:41.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:41.52#ibcon#enter wrdev, iclass 19, count 2 2006.175.07:53:41.52#ibcon#first serial, iclass 19, count 2 2006.175.07:53:41.52#ibcon#enter sib2, iclass 19, count 2 2006.175.07:53:41.52#ibcon#flushed, iclass 19, count 2 2006.175.07:53:41.52#ibcon#about to write, iclass 19, count 2 2006.175.07:53:41.52#ibcon#wrote, iclass 19, count 2 2006.175.07:53:41.52#ibcon#about to read 3, iclass 19, count 2 2006.175.07:53:41.54#ibcon#read 3, iclass 19, count 2 2006.175.07:53:41.54#ibcon#about to read 4, iclass 19, count 2 2006.175.07:53:41.54#ibcon#read 4, iclass 19, count 2 2006.175.07:53:41.54#ibcon#about to read 5, iclass 19, count 2 2006.175.07:53:41.54#ibcon#read 5, iclass 19, count 2 2006.175.07:53:41.54#ibcon#about to read 6, iclass 19, count 2 2006.175.07:53:41.54#ibcon#read 6, iclass 19, count 2 2006.175.07:53:41.54#ibcon#end of sib2, iclass 19, count 2 2006.175.07:53:41.54#ibcon#*mode == 0, iclass 19, count 2 2006.175.07:53:41.54#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.175.07:53:41.54#ibcon#[27=AT03-04\r\n] 2006.175.07:53:41.54#ibcon#*before write, iclass 19, count 2 2006.175.07:53:41.54#ibcon#enter sib2, iclass 19, count 2 2006.175.07:53:41.54#ibcon#flushed, iclass 19, count 2 2006.175.07:53:41.54#ibcon#about to write, iclass 19, count 2 2006.175.07:53:41.54#ibcon#wrote, iclass 19, count 2 2006.175.07:53:41.54#ibcon#about to read 3, iclass 19, count 2 2006.175.07:53:41.57#ibcon#read 3, iclass 19, count 2 2006.175.07:53:41.57#ibcon#about to read 4, iclass 19, count 2 2006.175.07:53:41.57#ibcon#read 4, iclass 19, count 2 2006.175.07:53:41.57#ibcon#about to read 5, iclass 19, count 2 2006.175.07:53:41.57#ibcon#read 5, iclass 19, count 2 2006.175.07:53:41.57#ibcon#about to read 6, iclass 19, count 2 2006.175.07:53:41.57#ibcon#read 6, iclass 19, count 2 2006.175.07:53:41.57#ibcon#end of sib2, iclass 19, count 2 2006.175.07:53:41.57#ibcon#*after write, iclass 19, count 2 2006.175.07:53:41.57#ibcon#*before return 0, iclass 19, count 2 2006.175.07:53:41.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:41.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.175.07:53:41.57#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.175.07:53:41.57#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:41.57#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:41.69#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:41.69#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:41.69#ibcon#enter wrdev, iclass 19, count 0 2006.175.07:53:41.69#ibcon#first serial, iclass 19, count 0 2006.175.07:53:41.69#ibcon#enter sib2, iclass 19, count 0 2006.175.07:53:41.69#ibcon#flushed, iclass 19, count 0 2006.175.07:53:41.69#ibcon#about to write, iclass 19, count 0 2006.175.07:53:41.69#ibcon#wrote, iclass 19, count 0 2006.175.07:53:41.69#ibcon#about to read 3, iclass 19, count 0 2006.175.07:53:41.71#ibcon#read 3, iclass 19, count 0 2006.175.07:53:41.71#ibcon#about to read 4, iclass 19, count 0 2006.175.07:53:41.71#ibcon#read 4, iclass 19, count 0 2006.175.07:53:41.71#ibcon#about to read 5, iclass 19, count 0 2006.175.07:53:41.71#ibcon#read 5, iclass 19, count 0 2006.175.07:53:41.71#ibcon#about to read 6, iclass 19, count 0 2006.175.07:53:41.71#ibcon#read 6, iclass 19, count 0 2006.175.07:53:41.71#ibcon#end of sib2, iclass 19, count 0 2006.175.07:53:41.71#ibcon#*mode == 0, iclass 19, count 0 2006.175.07:53:41.71#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.07:53:41.71#ibcon#[27=USB\r\n] 2006.175.07:53:41.71#ibcon#*before write, iclass 19, count 0 2006.175.07:53:41.71#ibcon#enter sib2, iclass 19, count 0 2006.175.07:53:41.71#ibcon#flushed, iclass 19, count 0 2006.175.07:53:41.71#ibcon#about to write, iclass 19, count 0 2006.175.07:53:41.71#ibcon#wrote, iclass 19, count 0 2006.175.07:53:41.71#ibcon#about to read 3, iclass 19, count 0 2006.175.07:53:41.74#ibcon#read 3, iclass 19, count 0 2006.175.07:53:41.74#ibcon#about to read 4, iclass 19, count 0 2006.175.07:53:41.74#ibcon#read 4, iclass 19, count 0 2006.175.07:53:41.74#ibcon#about to read 5, iclass 19, count 0 2006.175.07:53:41.74#ibcon#read 5, iclass 19, count 0 2006.175.07:53:41.74#ibcon#about to read 6, iclass 19, count 0 2006.175.07:53:41.74#ibcon#read 6, iclass 19, count 0 2006.175.07:53:41.74#ibcon#end of sib2, iclass 19, count 0 2006.175.07:53:41.74#ibcon#*after write, iclass 19, count 0 2006.175.07:53:41.74#ibcon#*before return 0, iclass 19, count 0 2006.175.07:53:41.74#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:41.74#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.175.07:53:41.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.07:53:41.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.07:53:41.74$vc4f8/vblo=4,712.99 2006.175.07:53:41.74#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.07:53:41.74#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.07:53:41.74#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:41.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:41.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:41.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:41.74#ibcon#enter wrdev, iclass 21, count 0 2006.175.07:53:41.74#ibcon#first serial, iclass 21, count 0 2006.175.07:53:41.74#ibcon#enter sib2, iclass 21, count 0 2006.175.07:53:41.74#ibcon#flushed, iclass 21, count 0 2006.175.07:53:41.74#ibcon#about to write, iclass 21, count 0 2006.175.07:53:41.74#ibcon#wrote, iclass 21, count 0 2006.175.07:53:41.74#ibcon#about to read 3, iclass 21, count 0 2006.175.07:53:41.76#ibcon#read 3, iclass 21, count 0 2006.175.07:53:41.76#ibcon#about to read 4, iclass 21, count 0 2006.175.07:53:41.76#ibcon#read 4, iclass 21, count 0 2006.175.07:53:41.76#ibcon#about to read 5, iclass 21, count 0 2006.175.07:53:41.76#ibcon#read 5, iclass 21, count 0 2006.175.07:53:41.76#ibcon#about to read 6, iclass 21, count 0 2006.175.07:53:41.76#ibcon#read 6, iclass 21, count 0 2006.175.07:53:41.76#ibcon#end of sib2, iclass 21, count 0 2006.175.07:53:41.76#ibcon#*mode == 0, iclass 21, count 0 2006.175.07:53:41.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.07:53:41.76#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:53:41.76#ibcon#*before write, iclass 21, count 0 2006.175.07:53:41.76#ibcon#enter sib2, iclass 21, count 0 2006.175.07:53:41.76#ibcon#flushed, iclass 21, count 0 2006.175.07:53:41.76#ibcon#about to write, iclass 21, count 0 2006.175.07:53:41.76#ibcon#wrote, iclass 21, count 0 2006.175.07:53:41.76#ibcon#about to read 3, iclass 21, count 0 2006.175.07:53:41.80#ibcon#read 3, iclass 21, count 0 2006.175.07:53:41.80#ibcon#about to read 4, iclass 21, count 0 2006.175.07:53:41.80#ibcon#read 4, iclass 21, count 0 2006.175.07:53:41.80#ibcon#about to read 5, iclass 21, count 0 2006.175.07:53:41.80#ibcon#read 5, iclass 21, count 0 2006.175.07:53:41.80#ibcon#about to read 6, iclass 21, count 0 2006.175.07:53:41.80#ibcon#read 6, iclass 21, count 0 2006.175.07:53:41.80#ibcon#end of sib2, iclass 21, count 0 2006.175.07:53:41.80#ibcon#*after write, iclass 21, count 0 2006.175.07:53:41.80#ibcon#*before return 0, iclass 21, count 0 2006.175.07:53:41.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:41.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.07:53:41.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.07:53:41.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.07:53:41.80$vc4f8/vb=4,4 2006.175.07:53:41.80#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.07:53:41.80#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.07:53:41.80#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:41.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:41.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:41.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:41.86#ibcon#enter wrdev, iclass 23, count 2 2006.175.07:53:41.86#ibcon#first serial, iclass 23, count 2 2006.175.07:53:41.86#ibcon#enter sib2, iclass 23, count 2 2006.175.07:53:41.86#ibcon#flushed, iclass 23, count 2 2006.175.07:53:41.86#ibcon#about to write, iclass 23, count 2 2006.175.07:53:41.86#ibcon#wrote, iclass 23, count 2 2006.175.07:53:41.86#ibcon#about to read 3, iclass 23, count 2 2006.175.07:53:41.88#ibcon#read 3, iclass 23, count 2 2006.175.07:53:41.88#ibcon#about to read 4, iclass 23, count 2 2006.175.07:53:41.88#ibcon#read 4, iclass 23, count 2 2006.175.07:53:41.88#ibcon#about to read 5, iclass 23, count 2 2006.175.07:53:41.88#ibcon#read 5, iclass 23, count 2 2006.175.07:53:41.88#ibcon#about to read 6, iclass 23, count 2 2006.175.07:53:41.88#ibcon#read 6, iclass 23, count 2 2006.175.07:53:41.88#ibcon#end of sib2, iclass 23, count 2 2006.175.07:53:41.88#ibcon#*mode == 0, iclass 23, count 2 2006.175.07:53:41.88#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.07:53:41.88#ibcon#[27=AT04-04\r\n] 2006.175.07:53:41.88#ibcon#*before write, iclass 23, count 2 2006.175.07:53:41.88#ibcon#enter sib2, iclass 23, count 2 2006.175.07:53:41.88#ibcon#flushed, iclass 23, count 2 2006.175.07:53:41.88#ibcon#about to write, iclass 23, count 2 2006.175.07:53:41.88#ibcon#wrote, iclass 23, count 2 2006.175.07:53:41.88#ibcon#about to read 3, iclass 23, count 2 2006.175.07:53:41.91#ibcon#read 3, iclass 23, count 2 2006.175.07:53:41.91#ibcon#about to read 4, iclass 23, count 2 2006.175.07:53:41.91#ibcon#read 4, iclass 23, count 2 2006.175.07:53:41.91#ibcon#about to read 5, iclass 23, count 2 2006.175.07:53:41.91#ibcon#read 5, iclass 23, count 2 2006.175.07:53:41.91#ibcon#about to read 6, iclass 23, count 2 2006.175.07:53:41.91#ibcon#read 6, iclass 23, count 2 2006.175.07:53:41.91#ibcon#end of sib2, iclass 23, count 2 2006.175.07:53:41.91#ibcon#*after write, iclass 23, count 2 2006.175.07:53:41.91#ibcon#*before return 0, iclass 23, count 2 2006.175.07:53:41.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:41.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.07:53:41.91#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.07:53:41.91#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:41.91#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:42.03#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:42.03#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:42.03#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:53:42.03#ibcon#first serial, iclass 23, count 0 2006.175.07:53:42.03#ibcon#enter sib2, iclass 23, count 0 2006.175.07:53:42.03#ibcon#flushed, iclass 23, count 0 2006.175.07:53:42.03#ibcon#about to write, iclass 23, count 0 2006.175.07:53:42.03#ibcon#wrote, iclass 23, count 0 2006.175.07:53:42.03#ibcon#about to read 3, iclass 23, count 0 2006.175.07:53:42.05#ibcon#read 3, iclass 23, count 0 2006.175.07:53:42.05#ibcon#about to read 4, iclass 23, count 0 2006.175.07:53:42.05#ibcon#read 4, iclass 23, count 0 2006.175.07:53:42.05#ibcon#about to read 5, iclass 23, count 0 2006.175.07:53:42.05#ibcon#read 5, iclass 23, count 0 2006.175.07:53:42.05#ibcon#about to read 6, iclass 23, count 0 2006.175.07:53:42.05#ibcon#read 6, iclass 23, count 0 2006.175.07:53:42.05#ibcon#end of sib2, iclass 23, count 0 2006.175.07:53:42.05#ibcon#*mode == 0, iclass 23, count 0 2006.175.07:53:42.05#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.07:53:42.05#ibcon#[27=USB\r\n] 2006.175.07:53:42.05#ibcon#*before write, iclass 23, count 0 2006.175.07:53:42.05#ibcon#enter sib2, iclass 23, count 0 2006.175.07:53:42.05#ibcon#flushed, iclass 23, count 0 2006.175.07:53:42.05#ibcon#about to write, iclass 23, count 0 2006.175.07:53:42.05#ibcon#wrote, iclass 23, count 0 2006.175.07:53:42.05#ibcon#about to read 3, iclass 23, count 0 2006.175.07:53:42.08#ibcon#read 3, iclass 23, count 0 2006.175.07:53:42.08#ibcon#about to read 4, iclass 23, count 0 2006.175.07:53:42.08#ibcon#read 4, iclass 23, count 0 2006.175.07:53:42.08#ibcon#about to read 5, iclass 23, count 0 2006.175.07:53:42.08#ibcon#read 5, iclass 23, count 0 2006.175.07:53:42.08#ibcon#about to read 6, iclass 23, count 0 2006.175.07:53:42.08#ibcon#read 6, iclass 23, count 0 2006.175.07:53:42.08#ibcon#end of sib2, iclass 23, count 0 2006.175.07:53:42.08#ibcon#*after write, iclass 23, count 0 2006.175.07:53:42.08#ibcon#*before return 0, iclass 23, count 0 2006.175.07:53:42.08#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:42.08#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.07:53:42.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.07:53:42.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.07:53:42.08$vc4f8/vblo=5,744.99 2006.175.07:53:42.08#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.07:53:42.08#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.07:53:42.08#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:42.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:42.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:42.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:42.08#ibcon#enter wrdev, iclass 25, count 0 2006.175.07:53:42.08#ibcon#first serial, iclass 25, count 0 2006.175.07:53:42.08#ibcon#enter sib2, iclass 25, count 0 2006.175.07:53:42.08#ibcon#flushed, iclass 25, count 0 2006.175.07:53:42.08#ibcon#about to write, iclass 25, count 0 2006.175.07:53:42.08#ibcon#wrote, iclass 25, count 0 2006.175.07:53:42.08#ibcon#about to read 3, iclass 25, count 0 2006.175.07:53:42.10#ibcon#read 3, iclass 25, count 0 2006.175.07:53:42.10#ibcon#about to read 4, iclass 25, count 0 2006.175.07:53:42.10#ibcon#read 4, iclass 25, count 0 2006.175.07:53:42.10#ibcon#about to read 5, iclass 25, count 0 2006.175.07:53:42.10#ibcon#read 5, iclass 25, count 0 2006.175.07:53:42.10#ibcon#about to read 6, iclass 25, count 0 2006.175.07:53:42.10#ibcon#read 6, iclass 25, count 0 2006.175.07:53:42.10#ibcon#end of sib2, iclass 25, count 0 2006.175.07:53:42.10#ibcon#*mode == 0, iclass 25, count 0 2006.175.07:53:42.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.07:53:42.10#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:53:42.10#ibcon#*before write, iclass 25, count 0 2006.175.07:53:42.10#ibcon#enter sib2, iclass 25, count 0 2006.175.07:53:42.10#ibcon#flushed, iclass 25, count 0 2006.175.07:53:42.10#ibcon#about to write, iclass 25, count 0 2006.175.07:53:42.10#ibcon#wrote, iclass 25, count 0 2006.175.07:53:42.10#ibcon#about to read 3, iclass 25, count 0 2006.175.07:53:42.14#ibcon#read 3, iclass 25, count 0 2006.175.07:53:42.14#ibcon#about to read 4, iclass 25, count 0 2006.175.07:53:42.14#ibcon#read 4, iclass 25, count 0 2006.175.07:53:42.14#ibcon#about to read 5, iclass 25, count 0 2006.175.07:53:42.14#ibcon#read 5, iclass 25, count 0 2006.175.07:53:42.14#ibcon#about to read 6, iclass 25, count 0 2006.175.07:53:42.14#ibcon#read 6, iclass 25, count 0 2006.175.07:53:42.14#ibcon#end of sib2, iclass 25, count 0 2006.175.07:53:42.14#ibcon#*after write, iclass 25, count 0 2006.175.07:53:42.14#ibcon#*before return 0, iclass 25, count 0 2006.175.07:53:42.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:42.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.07:53:42.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.07:53:42.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.07:53:42.14$vc4f8/vb=5,4 2006.175.07:53:42.14#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.07:53:42.14#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.07:53:42.14#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:42.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:42.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:42.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:42.20#ibcon#enter wrdev, iclass 27, count 2 2006.175.07:53:42.20#ibcon#first serial, iclass 27, count 2 2006.175.07:53:42.20#ibcon#enter sib2, iclass 27, count 2 2006.175.07:53:42.20#ibcon#flushed, iclass 27, count 2 2006.175.07:53:42.20#ibcon#about to write, iclass 27, count 2 2006.175.07:53:42.20#ibcon#wrote, iclass 27, count 2 2006.175.07:53:42.20#ibcon#about to read 3, iclass 27, count 2 2006.175.07:53:42.22#ibcon#read 3, iclass 27, count 2 2006.175.07:53:42.22#ibcon#about to read 4, iclass 27, count 2 2006.175.07:53:42.22#ibcon#read 4, iclass 27, count 2 2006.175.07:53:42.22#ibcon#about to read 5, iclass 27, count 2 2006.175.07:53:42.22#ibcon#read 5, iclass 27, count 2 2006.175.07:53:42.22#ibcon#about to read 6, iclass 27, count 2 2006.175.07:53:42.22#ibcon#read 6, iclass 27, count 2 2006.175.07:53:42.22#ibcon#end of sib2, iclass 27, count 2 2006.175.07:53:42.22#ibcon#*mode == 0, iclass 27, count 2 2006.175.07:53:42.22#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.07:53:42.22#ibcon#[27=AT05-04\r\n] 2006.175.07:53:42.22#ibcon#*before write, iclass 27, count 2 2006.175.07:53:42.22#ibcon#enter sib2, iclass 27, count 2 2006.175.07:53:42.22#ibcon#flushed, iclass 27, count 2 2006.175.07:53:42.22#ibcon#about to write, iclass 27, count 2 2006.175.07:53:42.22#ibcon#wrote, iclass 27, count 2 2006.175.07:53:42.22#ibcon#about to read 3, iclass 27, count 2 2006.175.07:53:42.25#ibcon#read 3, iclass 27, count 2 2006.175.07:53:42.25#ibcon#about to read 4, iclass 27, count 2 2006.175.07:53:42.25#ibcon#read 4, iclass 27, count 2 2006.175.07:53:42.25#ibcon#about to read 5, iclass 27, count 2 2006.175.07:53:42.25#ibcon#read 5, iclass 27, count 2 2006.175.07:53:42.25#ibcon#about to read 6, iclass 27, count 2 2006.175.07:53:42.25#ibcon#read 6, iclass 27, count 2 2006.175.07:53:42.25#ibcon#end of sib2, iclass 27, count 2 2006.175.07:53:42.25#ibcon#*after write, iclass 27, count 2 2006.175.07:53:42.25#ibcon#*before return 0, iclass 27, count 2 2006.175.07:53:42.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:42.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.07:53:42.25#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.07:53:42.25#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:42.25#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:42.37#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:42.37#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:42.37#ibcon#enter wrdev, iclass 27, count 0 2006.175.07:53:42.37#ibcon#first serial, iclass 27, count 0 2006.175.07:53:42.37#ibcon#enter sib2, iclass 27, count 0 2006.175.07:53:42.37#ibcon#flushed, iclass 27, count 0 2006.175.07:53:42.37#ibcon#about to write, iclass 27, count 0 2006.175.07:53:42.37#ibcon#wrote, iclass 27, count 0 2006.175.07:53:42.37#ibcon#about to read 3, iclass 27, count 0 2006.175.07:53:42.39#ibcon#read 3, iclass 27, count 0 2006.175.07:53:42.39#ibcon#about to read 4, iclass 27, count 0 2006.175.07:53:42.39#ibcon#read 4, iclass 27, count 0 2006.175.07:53:42.39#ibcon#about to read 5, iclass 27, count 0 2006.175.07:53:42.39#ibcon#read 5, iclass 27, count 0 2006.175.07:53:42.39#ibcon#about to read 6, iclass 27, count 0 2006.175.07:53:42.39#ibcon#read 6, iclass 27, count 0 2006.175.07:53:42.39#ibcon#end of sib2, iclass 27, count 0 2006.175.07:53:42.39#ibcon#*mode == 0, iclass 27, count 0 2006.175.07:53:42.39#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.07:53:42.39#ibcon#[27=USB\r\n] 2006.175.07:53:42.39#ibcon#*before write, iclass 27, count 0 2006.175.07:53:42.39#ibcon#enter sib2, iclass 27, count 0 2006.175.07:53:42.39#ibcon#flushed, iclass 27, count 0 2006.175.07:53:42.39#ibcon#about to write, iclass 27, count 0 2006.175.07:53:42.39#ibcon#wrote, iclass 27, count 0 2006.175.07:53:42.39#ibcon#about to read 3, iclass 27, count 0 2006.175.07:53:42.42#ibcon#read 3, iclass 27, count 0 2006.175.07:53:42.42#ibcon#about to read 4, iclass 27, count 0 2006.175.07:53:42.42#ibcon#read 4, iclass 27, count 0 2006.175.07:53:42.42#ibcon#about to read 5, iclass 27, count 0 2006.175.07:53:42.42#ibcon#read 5, iclass 27, count 0 2006.175.07:53:42.42#ibcon#about to read 6, iclass 27, count 0 2006.175.07:53:42.42#ibcon#read 6, iclass 27, count 0 2006.175.07:53:42.42#ibcon#end of sib2, iclass 27, count 0 2006.175.07:53:42.42#ibcon#*after write, iclass 27, count 0 2006.175.07:53:42.42#ibcon#*before return 0, iclass 27, count 0 2006.175.07:53:42.42#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:42.42#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.07:53:42.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.07:53:42.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.07:53:42.42$vc4f8/vblo=6,752.99 2006.175.07:53:42.42#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.07:53:42.42#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.07:53:42.42#ibcon#ireg 17 cls_cnt 0 2006.175.07:53:42.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:42.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:42.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:42.42#ibcon#enter wrdev, iclass 29, count 0 2006.175.07:53:42.42#ibcon#first serial, iclass 29, count 0 2006.175.07:53:42.42#ibcon#enter sib2, iclass 29, count 0 2006.175.07:53:42.42#ibcon#flushed, iclass 29, count 0 2006.175.07:53:42.42#ibcon#about to write, iclass 29, count 0 2006.175.07:53:42.42#ibcon#wrote, iclass 29, count 0 2006.175.07:53:42.42#ibcon#about to read 3, iclass 29, count 0 2006.175.07:53:42.44#ibcon#read 3, iclass 29, count 0 2006.175.07:53:42.44#ibcon#about to read 4, iclass 29, count 0 2006.175.07:53:42.44#ibcon#read 4, iclass 29, count 0 2006.175.07:53:42.44#ibcon#about to read 5, iclass 29, count 0 2006.175.07:53:42.44#ibcon#read 5, iclass 29, count 0 2006.175.07:53:42.44#ibcon#about to read 6, iclass 29, count 0 2006.175.07:53:42.44#ibcon#read 6, iclass 29, count 0 2006.175.07:53:42.44#ibcon#end of sib2, iclass 29, count 0 2006.175.07:53:42.44#ibcon#*mode == 0, iclass 29, count 0 2006.175.07:53:42.44#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.07:53:42.44#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:53:42.44#ibcon#*before write, iclass 29, count 0 2006.175.07:53:42.44#ibcon#enter sib2, iclass 29, count 0 2006.175.07:53:42.44#ibcon#flushed, iclass 29, count 0 2006.175.07:53:42.44#ibcon#about to write, iclass 29, count 0 2006.175.07:53:42.44#ibcon#wrote, iclass 29, count 0 2006.175.07:53:42.44#ibcon#about to read 3, iclass 29, count 0 2006.175.07:53:42.48#ibcon#read 3, iclass 29, count 0 2006.175.07:53:42.48#ibcon#about to read 4, iclass 29, count 0 2006.175.07:53:42.48#ibcon#read 4, iclass 29, count 0 2006.175.07:53:42.48#ibcon#about to read 5, iclass 29, count 0 2006.175.07:53:42.48#ibcon#read 5, iclass 29, count 0 2006.175.07:53:42.48#ibcon#about to read 6, iclass 29, count 0 2006.175.07:53:42.48#ibcon#read 6, iclass 29, count 0 2006.175.07:53:42.48#ibcon#end of sib2, iclass 29, count 0 2006.175.07:53:42.48#ibcon#*after write, iclass 29, count 0 2006.175.07:53:42.48#ibcon#*before return 0, iclass 29, count 0 2006.175.07:53:42.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:42.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.07:53:42.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.07:53:42.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.07:53:42.48$vc4f8/vb=6,4 2006.175.07:53:42.48#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.07:53:42.48#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.07:53:42.48#ibcon#ireg 11 cls_cnt 2 2006.175.07:53:42.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:42.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:42.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:42.54#ibcon#enter wrdev, iclass 31, count 2 2006.175.07:53:42.54#ibcon#first serial, iclass 31, count 2 2006.175.07:53:42.54#ibcon#enter sib2, iclass 31, count 2 2006.175.07:53:42.54#ibcon#flushed, iclass 31, count 2 2006.175.07:53:42.54#ibcon#about to write, iclass 31, count 2 2006.175.07:53:42.54#ibcon#wrote, iclass 31, count 2 2006.175.07:53:42.54#ibcon#about to read 3, iclass 31, count 2 2006.175.07:53:42.56#ibcon#read 3, iclass 31, count 2 2006.175.07:53:42.56#ibcon#about to read 4, iclass 31, count 2 2006.175.07:53:42.56#ibcon#read 4, iclass 31, count 2 2006.175.07:53:42.56#ibcon#about to read 5, iclass 31, count 2 2006.175.07:53:42.56#ibcon#read 5, iclass 31, count 2 2006.175.07:53:42.56#ibcon#about to read 6, iclass 31, count 2 2006.175.07:53:42.56#ibcon#read 6, iclass 31, count 2 2006.175.07:53:42.56#ibcon#end of sib2, iclass 31, count 2 2006.175.07:53:42.56#ibcon#*mode == 0, iclass 31, count 2 2006.175.07:53:42.56#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.07:53:42.56#ibcon#[27=AT06-04\r\n] 2006.175.07:53:42.56#ibcon#*before write, iclass 31, count 2 2006.175.07:53:42.56#ibcon#enter sib2, iclass 31, count 2 2006.175.07:53:42.56#ibcon#flushed, iclass 31, count 2 2006.175.07:53:42.56#ibcon#about to write, iclass 31, count 2 2006.175.07:53:42.56#ibcon#wrote, iclass 31, count 2 2006.175.07:53:42.56#ibcon#about to read 3, iclass 31, count 2 2006.175.07:53:42.59#ibcon#read 3, iclass 31, count 2 2006.175.07:53:42.59#ibcon#about to read 4, iclass 31, count 2 2006.175.07:53:42.59#ibcon#read 4, iclass 31, count 2 2006.175.07:53:42.59#ibcon#about to read 5, iclass 31, count 2 2006.175.07:53:42.59#ibcon#read 5, iclass 31, count 2 2006.175.07:53:42.59#ibcon#about to read 6, iclass 31, count 2 2006.175.07:53:42.59#ibcon#read 6, iclass 31, count 2 2006.175.07:53:42.59#ibcon#end of sib2, iclass 31, count 2 2006.175.07:53:42.59#ibcon#*after write, iclass 31, count 2 2006.175.07:53:42.59#ibcon#*before return 0, iclass 31, count 2 2006.175.07:53:42.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:42.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.07:53:42.59#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.07:53:42.59#ibcon#ireg 7 cls_cnt 0 2006.175.07:53:42.59#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:42.71#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:42.71#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:42.71#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:53:42.71#ibcon#first serial, iclass 31, count 0 2006.175.07:53:42.71#ibcon#enter sib2, iclass 31, count 0 2006.175.07:53:42.71#ibcon#flushed, iclass 31, count 0 2006.175.07:53:42.71#ibcon#about to write, iclass 31, count 0 2006.175.07:53:42.71#ibcon#wrote, iclass 31, count 0 2006.175.07:53:42.71#ibcon#about to read 3, iclass 31, count 0 2006.175.07:53:42.73#ibcon#read 3, iclass 31, count 0 2006.175.07:53:42.73#ibcon#about to read 4, iclass 31, count 0 2006.175.07:53:42.73#ibcon#read 4, iclass 31, count 0 2006.175.07:53:42.73#ibcon#about to read 5, iclass 31, count 0 2006.175.07:53:42.73#ibcon#read 5, iclass 31, count 0 2006.175.07:53:42.73#ibcon#about to read 6, iclass 31, count 0 2006.175.07:53:42.73#ibcon#read 6, iclass 31, count 0 2006.175.07:53:42.73#ibcon#end of sib2, iclass 31, count 0 2006.175.07:53:42.73#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:53:42.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:53:42.73#ibcon#[27=USB\r\n] 2006.175.07:53:42.73#ibcon#*before write, iclass 31, count 0 2006.175.07:53:42.73#ibcon#enter sib2, iclass 31, count 0 2006.175.07:53:42.73#ibcon#flushed, iclass 31, count 0 2006.175.07:53:42.73#ibcon#about to write, iclass 31, count 0 2006.175.07:53:42.73#ibcon#wrote, iclass 31, count 0 2006.175.07:53:42.73#ibcon#about to read 3, iclass 31, count 0 2006.175.07:53:42.76#ibcon#read 3, iclass 31, count 0 2006.175.07:53:42.76#ibcon#about to read 4, iclass 31, count 0 2006.175.07:53:42.76#ibcon#read 4, iclass 31, count 0 2006.175.07:53:42.76#ibcon#about to read 5, iclass 31, count 0 2006.175.07:53:42.76#ibcon#read 5, iclass 31, count 0 2006.175.07:53:42.76#ibcon#about to read 6, iclass 31, count 0 2006.175.07:53:42.76#ibcon#read 6, iclass 31, count 0 2006.175.07:53:42.76#ibcon#end of sib2, iclass 31, count 0 2006.175.07:53:42.76#ibcon#*after write, iclass 31, count 0 2006.175.07:53:42.76#ibcon#*before return 0, iclass 31, count 0 2006.175.07:53:42.76#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:42.76#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.07:53:42.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:53:42.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:53:42.76$vc4f8/vabw=wide 2006.175.07:53:42.76#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.07:53:42.76#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.07:53:42.76#ibcon#ireg 8 cls_cnt 0 2006.175.07:53:42.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:42.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:42.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:42.76#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:53:42.76#ibcon#first serial, iclass 33, count 0 2006.175.07:53:42.76#ibcon#enter sib2, iclass 33, count 0 2006.175.07:53:42.76#ibcon#flushed, iclass 33, count 0 2006.175.07:53:42.76#ibcon#about to write, iclass 33, count 0 2006.175.07:53:42.76#ibcon#wrote, iclass 33, count 0 2006.175.07:53:42.76#ibcon#about to read 3, iclass 33, count 0 2006.175.07:53:42.78#ibcon#read 3, iclass 33, count 0 2006.175.07:53:42.78#ibcon#about to read 4, iclass 33, count 0 2006.175.07:53:42.78#ibcon#read 4, iclass 33, count 0 2006.175.07:53:42.78#ibcon#about to read 5, iclass 33, count 0 2006.175.07:53:42.78#ibcon#read 5, iclass 33, count 0 2006.175.07:53:42.78#ibcon#about to read 6, iclass 33, count 0 2006.175.07:53:42.78#ibcon#read 6, iclass 33, count 0 2006.175.07:53:42.78#ibcon#end of sib2, iclass 33, count 0 2006.175.07:53:42.78#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:53:42.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:53:42.78#ibcon#[25=BW32\r\n] 2006.175.07:53:42.78#ibcon#*before write, iclass 33, count 0 2006.175.07:53:42.78#ibcon#enter sib2, iclass 33, count 0 2006.175.07:53:42.78#ibcon#flushed, iclass 33, count 0 2006.175.07:53:42.78#ibcon#about to write, iclass 33, count 0 2006.175.07:53:42.78#ibcon#wrote, iclass 33, count 0 2006.175.07:53:42.78#ibcon#about to read 3, iclass 33, count 0 2006.175.07:53:42.81#ibcon#read 3, iclass 33, count 0 2006.175.07:53:42.81#ibcon#about to read 4, iclass 33, count 0 2006.175.07:53:42.81#ibcon#read 4, iclass 33, count 0 2006.175.07:53:42.81#ibcon#about to read 5, iclass 33, count 0 2006.175.07:53:42.81#ibcon#read 5, iclass 33, count 0 2006.175.07:53:42.81#ibcon#about to read 6, iclass 33, count 0 2006.175.07:53:42.81#ibcon#read 6, iclass 33, count 0 2006.175.07:53:42.81#ibcon#end of sib2, iclass 33, count 0 2006.175.07:53:42.81#ibcon#*after write, iclass 33, count 0 2006.175.07:53:42.81#ibcon#*before return 0, iclass 33, count 0 2006.175.07:53:42.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:42.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.07:53:42.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:53:42.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:53:42.81$vc4f8/vbbw=wide 2006.175.07:53:42.81#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.07:53:42.81#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.07:53:42.81#ibcon#ireg 8 cls_cnt 0 2006.175.07:53:42.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:53:42.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:53:42.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:53:42.88#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:53:42.88#ibcon#first serial, iclass 35, count 0 2006.175.07:53:42.88#ibcon#enter sib2, iclass 35, count 0 2006.175.07:53:42.88#ibcon#flushed, iclass 35, count 0 2006.175.07:53:42.88#ibcon#about to write, iclass 35, count 0 2006.175.07:53:42.88#ibcon#wrote, iclass 35, count 0 2006.175.07:53:42.88#ibcon#about to read 3, iclass 35, count 0 2006.175.07:53:42.90#ibcon#read 3, iclass 35, count 0 2006.175.07:53:42.90#ibcon#about to read 4, iclass 35, count 0 2006.175.07:53:42.90#ibcon#read 4, iclass 35, count 0 2006.175.07:53:42.90#ibcon#about to read 5, iclass 35, count 0 2006.175.07:53:42.90#ibcon#read 5, iclass 35, count 0 2006.175.07:53:42.90#ibcon#about to read 6, iclass 35, count 0 2006.175.07:53:42.90#ibcon#read 6, iclass 35, count 0 2006.175.07:53:42.90#ibcon#end of sib2, iclass 35, count 0 2006.175.07:53:42.90#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:53:42.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:53:42.90#ibcon#[27=BW32\r\n] 2006.175.07:53:42.90#ibcon#*before write, iclass 35, count 0 2006.175.07:53:42.90#ibcon#enter sib2, iclass 35, count 0 2006.175.07:53:42.90#ibcon#flushed, iclass 35, count 0 2006.175.07:53:42.90#ibcon#about to write, iclass 35, count 0 2006.175.07:53:42.90#ibcon#wrote, iclass 35, count 0 2006.175.07:53:42.90#ibcon#about to read 3, iclass 35, count 0 2006.175.07:53:42.93#ibcon#read 3, iclass 35, count 0 2006.175.07:53:42.93#ibcon#about to read 4, iclass 35, count 0 2006.175.07:53:42.93#ibcon#read 4, iclass 35, count 0 2006.175.07:53:42.93#ibcon#about to read 5, iclass 35, count 0 2006.175.07:53:42.93#ibcon#read 5, iclass 35, count 0 2006.175.07:53:42.93#ibcon#about to read 6, iclass 35, count 0 2006.175.07:53:42.93#ibcon#read 6, iclass 35, count 0 2006.175.07:53:42.93#ibcon#end of sib2, iclass 35, count 0 2006.175.07:53:42.93#ibcon#*after write, iclass 35, count 0 2006.175.07:53:42.93#ibcon#*before return 0, iclass 35, count 0 2006.175.07:53:42.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:53:42.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:53:42.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:53:42.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:53:42.93$4f8m12a/ifd4f 2006.175.07:53:42.93$ifd4f/lo= 2006.175.07:53:42.93$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:53:42.93$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:53:42.93$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:53:42.93$ifd4f/patch= 2006.175.07:53:42.93$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:53:42.93$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:53:42.93$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:53:42.93$4f8m12a/"form=m,16.000,1:2 2006.175.07:53:42.93$4f8m12a/"tpicd 2006.175.07:53:42.93$4f8m12a/echo=off 2006.175.07:53:42.93$4f8m12a/xlog=off 2006.175.07:53:42.93:!2006.175.07:55:10 2006.175.07:53:42.95#abcon#<5=/04 4.3 7.5 25.85 681007.4\r\n> 2006.175.07:53:48.14#trakl#Source acquired 2006.175.07:53:49.14#flagr#flagr/antenna,acquired 2006.175.07:55:10.00:preob 2006.175.07:55:11.14/onsource/TRACKING 2006.175.07:55:11.14:!2006.175.07:55:20 2006.175.07:55:20.02:data_valid=on 2006.175.07:55:20.02:midob 2006.175.07:55:21.14/onsource/TRACKING 2006.175.07:55:21.14/wx/25.83,1007.4,69 2006.175.07:55:21.37/cable/+6.4783E-03 2006.175.07:55:22.45/va/01,08,usb,yes,30,31 2006.175.07:55:22.45/va/02,07,usb,yes,30,31 2006.175.07:55:22.45/va/03,06,usb,yes,31,32 2006.175.07:55:22.45/va/04,07,usb,yes,31,33 2006.175.07:55:22.45/va/05,07,usb,yes,31,33 2006.175.07:55:22.45/va/06,06,usb,yes,30,30 2006.175.07:55:22.45/va/07,06,usb,yes,31,30 2006.175.07:55:22.45/va/08,06,usb,yes,33,32 2006.175.07:55:22.68/valo/01,532.99,yes,locked 2006.175.07:55:22.68/valo/02,572.99,yes,locked 2006.175.07:55:22.68/valo/03,672.99,yes,locked 2006.175.07:55:22.68/valo/04,832.99,yes,locked 2006.175.07:55:22.68/valo/05,652.99,yes,locked 2006.175.07:55:22.68/valo/06,772.99,yes,locked 2006.175.07:55:22.68/valo/07,832.99,yes,locked 2006.175.07:55:22.68/valo/08,852.99,yes,locked 2006.175.07:55:23.77/vb/01,04,usb,yes,30,28 2006.175.07:55:23.77/vb/02,04,usb,yes,32,33 2006.175.07:55:23.77/vb/03,04,usb,yes,28,32 2006.175.07:55:23.77/vb/04,04,usb,yes,29,29 2006.175.07:55:23.77/vb/05,04,usb,yes,27,31 2006.175.07:55:23.77/vb/06,04,usb,yes,28,31 2006.175.07:55:23.77/vb/07,04,usb,yes,30,30 2006.175.07:55:23.77/vb/08,04,usb,yes,28,31 2006.175.07:55:24.00/vblo/01,632.99,yes,locked 2006.175.07:55:24.00/vblo/02,640.99,yes,locked 2006.175.07:55:24.00/vblo/03,656.99,yes,locked 2006.175.07:55:24.00/vblo/04,712.99,yes,locked 2006.175.07:55:24.00/vblo/05,744.99,yes,locked 2006.175.07:55:24.00/vblo/06,752.99,yes,locked 2006.175.07:55:24.00/vblo/07,734.99,yes,locked 2006.175.07:55:24.00/vblo/08,744.99,yes,locked 2006.175.07:55:24.15/vabw/8 2006.175.07:55:24.30/vbbw/8 2006.175.07:55:24.39/xfe/off,on,15.2 2006.175.07:55:24.76/ifatt/23,28,28,28 2006.175.07:55:25.08/fmout-gps/S +3.74E-07 2006.175.07:55:25.15:!2006.175.07:56:20 2006.175.07:56:20.02:data_valid=off 2006.175.07:56:20.02:postob 2006.175.07:56:20.21/cable/+6.4768E-03 2006.175.07:56:20.21/wx/25.84,1007.4,70 2006.175.07:56:21.08/fmout-gps/S +3.73E-07 2006.175.07:56:21.08:scan_name=175-0758,k06175,60 2006.175.07:56:21.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.175.07:56:22.15#flagr#flagr/antenna,new-source 2006.175.07:56:22.15:checkk5 2006.175.07:56:22.54/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:56:22.92/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:56:23.34/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:56:23.71/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:56:24.08/chk_obsdata//k5ts1/T1750755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:56:24.46/chk_obsdata//k5ts2/T1750755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:56:24.83/chk_obsdata//k5ts3/T1750755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:56:25.20/chk_obsdata//k5ts4/T1750755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:56:25.90/k5log//k5ts1_log_newline 2006.175.07:56:26.58/k5log//k5ts2_log_newline 2006.175.07:56:27.28/k5log//k5ts3_log_newline 2006.175.07:56:27.97/k5log//k5ts4_log_newline 2006.175.07:56:28.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:56:28.00:4f8m12a=2 2006.175.07:56:28.00$4f8m12a/echo=on 2006.175.07:56:28.00$4f8m12a/pcalon 2006.175.07:56:28.00$pcalon/"no phase cal control is implemented here 2006.175.07:56:28.00$4f8m12a/"tpicd=stop 2006.175.07:56:28.00$4f8m12a/vc4f8 2006.175.07:56:28.00$vc4f8/valo=1,532.99 2006.175.07:56:28.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.07:56:28.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.07:56:28.00#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:28.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:28.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:28.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:28.00#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:56:28.00#ibcon#first serial, iclass 34, count 0 2006.175.07:56:28.00#ibcon#enter sib2, iclass 34, count 0 2006.175.07:56:28.00#ibcon#flushed, iclass 34, count 0 2006.175.07:56:28.00#ibcon#about to write, iclass 34, count 0 2006.175.07:56:28.00#ibcon#wrote, iclass 34, count 0 2006.175.07:56:28.00#ibcon#about to read 3, iclass 34, count 0 2006.175.07:56:28.04#ibcon#read 3, iclass 34, count 0 2006.175.07:56:28.04#ibcon#about to read 4, iclass 34, count 0 2006.175.07:56:28.04#ibcon#read 4, iclass 34, count 0 2006.175.07:56:28.04#ibcon#about to read 5, iclass 34, count 0 2006.175.07:56:28.04#ibcon#read 5, iclass 34, count 0 2006.175.07:56:28.04#ibcon#about to read 6, iclass 34, count 0 2006.175.07:56:28.04#ibcon#read 6, iclass 34, count 0 2006.175.07:56:28.04#ibcon#end of sib2, iclass 34, count 0 2006.175.07:56:28.04#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:56:28.04#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:56:28.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:56:28.04#ibcon#*before write, iclass 34, count 0 2006.175.07:56:28.04#ibcon#enter sib2, iclass 34, count 0 2006.175.07:56:28.04#ibcon#flushed, iclass 34, count 0 2006.175.07:56:28.04#ibcon#about to write, iclass 34, count 0 2006.175.07:56:28.04#ibcon#wrote, iclass 34, count 0 2006.175.07:56:28.04#ibcon#about to read 3, iclass 34, count 0 2006.175.07:56:28.08#ibcon#read 3, iclass 34, count 0 2006.175.07:56:28.08#ibcon#about to read 4, iclass 34, count 0 2006.175.07:56:28.08#ibcon#read 4, iclass 34, count 0 2006.175.07:56:28.08#ibcon#about to read 5, iclass 34, count 0 2006.175.07:56:28.08#ibcon#read 5, iclass 34, count 0 2006.175.07:56:28.08#ibcon#about to read 6, iclass 34, count 0 2006.175.07:56:28.08#ibcon#read 6, iclass 34, count 0 2006.175.07:56:28.08#ibcon#end of sib2, iclass 34, count 0 2006.175.07:56:28.08#ibcon#*after write, iclass 34, count 0 2006.175.07:56:28.08#ibcon#*before return 0, iclass 34, count 0 2006.175.07:56:28.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:28.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:28.08#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:56:28.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:56:28.09$vc4f8/va=1,8 2006.175.07:56:28.09#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.07:56:28.09#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.07:56:28.09#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:28.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:28.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:28.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:28.09#ibcon#enter wrdev, iclass 36, count 2 2006.175.07:56:28.09#ibcon#first serial, iclass 36, count 2 2006.175.07:56:28.09#ibcon#enter sib2, iclass 36, count 2 2006.175.07:56:28.09#ibcon#flushed, iclass 36, count 2 2006.175.07:56:28.09#ibcon#about to write, iclass 36, count 2 2006.175.07:56:28.09#ibcon#wrote, iclass 36, count 2 2006.175.07:56:28.09#ibcon#about to read 3, iclass 36, count 2 2006.175.07:56:28.11#ibcon#read 3, iclass 36, count 2 2006.175.07:56:28.11#ibcon#about to read 4, iclass 36, count 2 2006.175.07:56:28.11#ibcon#read 4, iclass 36, count 2 2006.175.07:56:28.11#ibcon#about to read 5, iclass 36, count 2 2006.175.07:56:28.11#ibcon#read 5, iclass 36, count 2 2006.175.07:56:28.11#ibcon#about to read 6, iclass 36, count 2 2006.175.07:56:28.11#ibcon#read 6, iclass 36, count 2 2006.175.07:56:28.11#ibcon#end of sib2, iclass 36, count 2 2006.175.07:56:28.11#ibcon#*mode == 0, iclass 36, count 2 2006.175.07:56:28.11#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.07:56:28.11#ibcon#[25=AT01-08\r\n] 2006.175.07:56:28.11#ibcon#*before write, iclass 36, count 2 2006.175.07:56:28.11#ibcon#enter sib2, iclass 36, count 2 2006.175.07:56:28.11#ibcon#flushed, iclass 36, count 2 2006.175.07:56:28.11#ibcon#about to write, iclass 36, count 2 2006.175.07:56:28.11#ibcon#wrote, iclass 36, count 2 2006.175.07:56:28.11#ibcon#about to read 3, iclass 36, count 2 2006.175.07:56:28.13#ibcon#read 3, iclass 36, count 2 2006.175.07:56:28.13#ibcon#about to read 4, iclass 36, count 2 2006.175.07:56:28.13#ibcon#read 4, iclass 36, count 2 2006.175.07:56:28.13#ibcon#about to read 5, iclass 36, count 2 2006.175.07:56:28.13#ibcon#read 5, iclass 36, count 2 2006.175.07:56:28.13#ibcon#about to read 6, iclass 36, count 2 2006.175.07:56:28.13#ibcon#read 6, iclass 36, count 2 2006.175.07:56:28.13#ibcon#end of sib2, iclass 36, count 2 2006.175.07:56:28.13#ibcon#*after write, iclass 36, count 2 2006.175.07:56:28.13#ibcon#*before return 0, iclass 36, count 2 2006.175.07:56:28.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:28.14#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:28.14#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.07:56:28.14#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:28.14#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:28.26#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:28.26#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:28.26#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:56:28.26#ibcon#first serial, iclass 36, count 0 2006.175.07:56:28.26#ibcon#enter sib2, iclass 36, count 0 2006.175.07:56:28.26#ibcon#flushed, iclass 36, count 0 2006.175.07:56:28.26#ibcon#about to write, iclass 36, count 0 2006.175.07:56:28.26#ibcon#wrote, iclass 36, count 0 2006.175.07:56:28.26#ibcon#about to read 3, iclass 36, count 0 2006.175.07:56:28.27#ibcon#read 3, iclass 36, count 0 2006.175.07:56:28.27#ibcon#about to read 4, iclass 36, count 0 2006.175.07:56:28.27#ibcon#read 4, iclass 36, count 0 2006.175.07:56:28.27#ibcon#about to read 5, iclass 36, count 0 2006.175.07:56:28.27#ibcon#read 5, iclass 36, count 0 2006.175.07:56:28.27#ibcon#about to read 6, iclass 36, count 0 2006.175.07:56:28.27#ibcon#read 6, iclass 36, count 0 2006.175.07:56:28.27#ibcon#end of sib2, iclass 36, count 0 2006.175.07:56:28.27#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:56:28.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:56:28.27#ibcon#[25=USB\r\n] 2006.175.07:56:28.27#ibcon#*before write, iclass 36, count 0 2006.175.07:56:28.28#ibcon#enter sib2, iclass 36, count 0 2006.175.07:56:28.28#ibcon#flushed, iclass 36, count 0 2006.175.07:56:28.28#ibcon#about to write, iclass 36, count 0 2006.175.07:56:28.28#ibcon#wrote, iclass 36, count 0 2006.175.07:56:28.28#ibcon#about to read 3, iclass 36, count 0 2006.175.07:56:28.30#ibcon#read 3, iclass 36, count 0 2006.175.07:56:28.30#ibcon#about to read 4, iclass 36, count 0 2006.175.07:56:28.30#ibcon#read 4, iclass 36, count 0 2006.175.07:56:28.30#ibcon#about to read 5, iclass 36, count 0 2006.175.07:56:28.30#ibcon#read 5, iclass 36, count 0 2006.175.07:56:28.30#ibcon#about to read 6, iclass 36, count 0 2006.175.07:56:28.30#ibcon#read 6, iclass 36, count 0 2006.175.07:56:28.30#ibcon#end of sib2, iclass 36, count 0 2006.175.07:56:28.30#ibcon#*after write, iclass 36, count 0 2006.175.07:56:28.30#ibcon#*before return 0, iclass 36, count 0 2006.175.07:56:28.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:28.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:28.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:56:28.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:56:28.31$vc4f8/valo=2,572.99 2006.175.07:56:28.31#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:56:28.31#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:56:28.31#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:28.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:28.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:28.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:28.31#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:56:28.31#ibcon#first serial, iclass 38, count 0 2006.175.07:56:28.31#ibcon#enter sib2, iclass 38, count 0 2006.175.07:56:28.31#ibcon#flushed, iclass 38, count 0 2006.175.07:56:28.31#ibcon#about to write, iclass 38, count 0 2006.175.07:56:28.31#ibcon#wrote, iclass 38, count 0 2006.175.07:56:28.31#ibcon#about to read 3, iclass 38, count 0 2006.175.07:56:28.32#ibcon#read 3, iclass 38, count 0 2006.175.07:56:28.32#ibcon#about to read 4, iclass 38, count 0 2006.175.07:56:28.32#ibcon#read 4, iclass 38, count 0 2006.175.07:56:28.32#ibcon#about to read 5, iclass 38, count 0 2006.175.07:56:28.32#ibcon#read 5, iclass 38, count 0 2006.175.07:56:28.32#ibcon#about to read 6, iclass 38, count 0 2006.175.07:56:28.32#ibcon#read 6, iclass 38, count 0 2006.175.07:56:28.32#ibcon#end of sib2, iclass 38, count 0 2006.175.07:56:28.32#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:56:28.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:56:28.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:56:28.33#ibcon#*before write, iclass 38, count 0 2006.175.07:56:28.33#ibcon#enter sib2, iclass 38, count 0 2006.175.07:56:28.33#ibcon#flushed, iclass 38, count 0 2006.175.07:56:28.33#ibcon#about to write, iclass 38, count 0 2006.175.07:56:28.33#ibcon#wrote, iclass 38, count 0 2006.175.07:56:28.33#ibcon#about to read 3, iclass 38, count 0 2006.175.07:56:28.37#ibcon#read 3, iclass 38, count 0 2006.175.07:56:28.37#ibcon#about to read 4, iclass 38, count 0 2006.175.07:56:28.37#ibcon#read 4, iclass 38, count 0 2006.175.07:56:28.37#ibcon#about to read 5, iclass 38, count 0 2006.175.07:56:28.37#ibcon#read 5, iclass 38, count 0 2006.175.07:56:28.37#ibcon#about to read 6, iclass 38, count 0 2006.175.07:56:28.37#ibcon#read 6, iclass 38, count 0 2006.175.07:56:28.37#ibcon#end of sib2, iclass 38, count 0 2006.175.07:56:28.37#ibcon#*after write, iclass 38, count 0 2006.175.07:56:28.37#ibcon#*before return 0, iclass 38, count 0 2006.175.07:56:28.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:28.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:28.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:56:28.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:56:28.37$vc4f8/va=2,7 2006.175.07:56:28.37#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.07:56:28.37#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.07:56:28.37#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:28.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:28.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:28.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:28.41#ibcon#enter wrdev, iclass 40, count 2 2006.175.07:56:28.41#ibcon#first serial, iclass 40, count 2 2006.175.07:56:28.41#ibcon#enter sib2, iclass 40, count 2 2006.175.07:56:28.41#ibcon#flushed, iclass 40, count 2 2006.175.07:56:28.41#ibcon#about to write, iclass 40, count 2 2006.175.07:56:28.41#ibcon#wrote, iclass 40, count 2 2006.175.07:56:28.41#ibcon#about to read 3, iclass 40, count 2 2006.175.07:56:28.43#ibcon#read 3, iclass 40, count 2 2006.175.07:56:28.43#ibcon#about to read 4, iclass 40, count 2 2006.175.07:56:28.43#ibcon#read 4, iclass 40, count 2 2006.175.07:56:28.43#ibcon#about to read 5, iclass 40, count 2 2006.175.07:56:28.43#ibcon#read 5, iclass 40, count 2 2006.175.07:56:28.43#ibcon#about to read 6, iclass 40, count 2 2006.175.07:56:28.43#ibcon#read 6, iclass 40, count 2 2006.175.07:56:28.43#ibcon#end of sib2, iclass 40, count 2 2006.175.07:56:28.43#ibcon#*mode == 0, iclass 40, count 2 2006.175.07:56:28.43#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.07:56:28.43#ibcon#[25=AT02-07\r\n] 2006.175.07:56:28.43#ibcon#*before write, iclass 40, count 2 2006.175.07:56:28.43#ibcon#enter sib2, iclass 40, count 2 2006.175.07:56:28.44#ibcon#flushed, iclass 40, count 2 2006.175.07:56:28.44#ibcon#about to write, iclass 40, count 2 2006.175.07:56:28.44#ibcon#wrote, iclass 40, count 2 2006.175.07:56:28.44#ibcon#about to read 3, iclass 40, count 2 2006.175.07:56:28.47#ibcon#read 3, iclass 40, count 2 2006.175.07:56:28.47#ibcon#about to read 4, iclass 40, count 2 2006.175.07:56:28.47#ibcon#read 4, iclass 40, count 2 2006.175.07:56:28.47#ibcon#about to read 5, iclass 40, count 2 2006.175.07:56:28.47#ibcon#read 5, iclass 40, count 2 2006.175.07:56:28.47#ibcon#about to read 6, iclass 40, count 2 2006.175.07:56:28.47#ibcon#read 6, iclass 40, count 2 2006.175.07:56:28.47#ibcon#end of sib2, iclass 40, count 2 2006.175.07:56:28.47#ibcon#*after write, iclass 40, count 2 2006.175.07:56:28.47#ibcon#*before return 0, iclass 40, count 2 2006.175.07:56:28.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:28.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:28.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.07:56:28.47#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:28.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:28.58#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:28.58#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:28.58#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:56:28.58#ibcon#first serial, iclass 40, count 0 2006.175.07:56:28.58#ibcon#enter sib2, iclass 40, count 0 2006.175.07:56:28.58#ibcon#flushed, iclass 40, count 0 2006.175.07:56:28.58#ibcon#about to write, iclass 40, count 0 2006.175.07:56:28.58#ibcon#wrote, iclass 40, count 0 2006.175.07:56:28.58#ibcon#about to read 3, iclass 40, count 0 2006.175.07:56:28.60#ibcon#read 3, iclass 40, count 0 2006.175.07:56:28.60#ibcon#about to read 4, iclass 40, count 0 2006.175.07:56:28.60#ibcon#read 4, iclass 40, count 0 2006.175.07:56:28.60#ibcon#about to read 5, iclass 40, count 0 2006.175.07:56:28.60#ibcon#read 5, iclass 40, count 0 2006.175.07:56:28.60#ibcon#about to read 6, iclass 40, count 0 2006.175.07:56:28.60#ibcon#read 6, iclass 40, count 0 2006.175.07:56:28.60#ibcon#end of sib2, iclass 40, count 0 2006.175.07:56:28.60#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:56:28.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:56:28.60#ibcon#[25=USB\r\n] 2006.175.07:56:28.60#ibcon#*before write, iclass 40, count 0 2006.175.07:56:28.60#ibcon#enter sib2, iclass 40, count 0 2006.175.07:56:28.60#ibcon#flushed, iclass 40, count 0 2006.175.07:56:28.60#ibcon#about to write, iclass 40, count 0 2006.175.07:56:28.61#ibcon#wrote, iclass 40, count 0 2006.175.07:56:28.61#ibcon#about to read 3, iclass 40, count 0 2006.175.07:56:28.63#ibcon#read 3, iclass 40, count 0 2006.175.07:56:28.63#ibcon#about to read 4, iclass 40, count 0 2006.175.07:56:28.63#ibcon#read 4, iclass 40, count 0 2006.175.07:56:28.63#ibcon#about to read 5, iclass 40, count 0 2006.175.07:56:28.63#ibcon#read 5, iclass 40, count 0 2006.175.07:56:28.63#ibcon#about to read 6, iclass 40, count 0 2006.175.07:56:28.63#ibcon#read 6, iclass 40, count 0 2006.175.07:56:28.63#ibcon#end of sib2, iclass 40, count 0 2006.175.07:56:28.63#ibcon#*after write, iclass 40, count 0 2006.175.07:56:28.63#ibcon#*before return 0, iclass 40, count 0 2006.175.07:56:28.63#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:28.63#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:28.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:56:28.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:56:28.64$vc4f8/valo=3,672.99 2006.175.07:56:28.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:56:28.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:56:28.64#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:28.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:28.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:28.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:28.64#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:56:28.64#ibcon#first serial, iclass 4, count 0 2006.175.07:56:28.64#ibcon#enter sib2, iclass 4, count 0 2006.175.07:56:28.64#ibcon#flushed, iclass 4, count 0 2006.175.07:56:28.64#ibcon#about to write, iclass 4, count 0 2006.175.07:56:28.64#ibcon#wrote, iclass 4, count 0 2006.175.07:56:28.64#ibcon#about to read 3, iclass 4, count 0 2006.175.07:56:28.65#ibcon#read 3, iclass 4, count 0 2006.175.07:56:28.65#ibcon#about to read 4, iclass 4, count 0 2006.175.07:56:28.65#ibcon#read 4, iclass 4, count 0 2006.175.07:56:28.65#ibcon#about to read 5, iclass 4, count 0 2006.175.07:56:28.65#ibcon#read 5, iclass 4, count 0 2006.175.07:56:28.65#ibcon#about to read 6, iclass 4, count 0 2006.175.07:56:28.65#ibcon#read 6, iclass 4, count 0 2006.175.07:56:28.65#ibcon#end of sib2, iclass 4, count 0 2006.175.07:56:28.65#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:56:28.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:56:28.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:56:28.65#ibcon#*before write, iclass 4, count 0 2006.175.07:56:28.65#ibcon#enter sib2, iclass 4, count 0 2006.175.07:56:28.66#ibcon#flushed, iclass 4, count 0 2006.175.07:56:28.66#ibcon#about to write, iclass 4, count 0 2006.175.07:56:28.66#ibcon#wrote, iclass 4, count 0 2006.175.07:56:28.66#ibcon#about to read 3, iclass 4, count 0 2006.175.07:56:28.70#ibcon#read 3, iclass 4, count 0 2006.175.07:56:28.70#ibcon#about to read 4, iclass 4, count 0 2006.175.07:56:28.70#ibcon#read 4, iclass 4, count 0 2006.175.07:56:28.70#ibcon#about to read 5, iclass 4, count 0 2006.175.07:56:28.70#ibcon#read 5, iclass 4, count 0 2006.175.07:56:28.70#ibcon#about to read 6, iclass 4, count 0 2006.175.07:56:28.70#ibcon#read 6, iclass 4, count 0 2006.175.07:56:28.70#ibcon#end of sib2, iclass 4, count 0 2006.175.07:56:28.70#ibcon#*after write, iclass 4, count 0 2006.175.07:56:28.70#ibcon#*before return 0, iclass 4, count 0 2006.175.07:56:28.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:28.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:28.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:56:28.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:56:28.70$vc4f8/va=3,6 2006.175.07:56:28.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.07:56:28.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.07:56:28.70#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:28.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:28.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:28.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:28.74#ibcon#enter wrdev, iclass 6, count 2 2006.175.07:56:28.74#ibcon#first serial, iclass 6, count 2 2006.175.07:56:28.74#ibcon#enter sib2, iclass 6, count 2 2006.175.07:56:28.74#ibcon#flushed, iclass 6, count 2 2006.175.07:56:28.74#ibcon#about to write, iclass 6, count 2 2006.175.07:56:28.74#ibcon#wrote, iclass 6, count 2 2006.175.07:56:28.74#ibcon#about to read 3, iclass 6, count 2 2006.175.07:56:28.76#ibcon#read 3, iclass 6, count 2 2006.175.07:56:28.76#ibcon#about to read 4, iclass 6, count 2 2006.175.07:56:28.76#ibcon#read 4, iclass 6, count 2 2006.175.07:56:28.76#ibcon#about to read 5, iclass 6, count 2 2006.175.07:56:28.76#ibcon#read 5, iclass 6, count 2 2006.175.07:56:28.76#ibcon#about to read 6, iclass 6, count 2 2006.175.07:56:28.76#ibcon#read 6, iclass 6, count 2 2006.175.07:56:28.76#ibcon#end of sib2, iclass 6, count 2 2006.175.07:56:28.76#ibcon#*mode == 0, iclass 6, count 2 2006.175.07:56:28.76#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.07:56:28.77#ibcon#[25=AT03-06\r\n] 2006.175.07:56:28.77#ibcon#*before write, iclass 6, count 2 2006.175.07:56:28.77#ibcon#enter sib2, iclass 6, count 2 2006.175.07:56:28.77#ibcon#flushed, iclass 6, count 2 2006.175.07:56:28.77#ibcon#about to write, iclass 6, count 2 2006.175.07:56:28.77#ibcon#wrote, iclass 6, count 2 2006.175.07:56:28.77#ibcon#about to read 3, iclass 6, count 2 2006.175.07:56:28.80#ibcon#read 3, iclass 6, count 2 2006.175.07:56:28.80#ibcon#about to read 4, iclass 6, count 2 2006.175.07:56:28.80#ibcon#read 4, iclass 6, count 2 2006.175.07:56:28.80#ibcon#about to read 5, iclass 6, count 2 2006.175.07:56:28.80#ibcon#read 5, iclass 6, count 2 2006.175.07:56:28.80#ibcon#about to read 6, iclass 6, count 2 2006.175.07:56:28.80#ibcon#read 6, iclass 6, count 2 2006.175.07:56:28.80#ibcon#end of sib2, iclass 6, count 2 2006.175.07:56:28.80#ibcon#*after write, iclass 6, count 2 2006.175.07:56:28.80#ibcon#*before return 0, iclass 6, count 2 2006.175.07:56:28.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:28.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:28.80#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.07:56:28.80#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:28.80#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:28.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:28.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:28.91#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:56:28.91#ibcon#first serial, iclass 6, count 0 2006.175.07:56:28.91#ibcon#enter sib2, iclass 6, count 0 2006.175.07:56:28.91#ibcon#flushed, iclass 6, count 0 2006.175.07:56:28.92#ibcon#about to write, iclass 6, count 0 2006.175.07:56:28.92#ibcon#wrote, iclass 6, count 0 2006.175.07:56:28.92#ibcon#about to read 3, iclass 6, count 0 2006.175.07:56:28.93#ibcon#read 3, iclass 6, count 0 2006.175.07:56:28.93#ibcon#about to read 4, iclass 6, count 0 2006.175.07:56:28.93#ibcon#read 4, iclass 6, count 0 2006.175.07:56:28.93#ibcon#about to read 5, iclass 6, count 0 2006.175.07:56:28.93#ibcon#read 5, iclass 6, count 0 2006.175.07:56:28.93#ibcon#about to read 6, iclass 6, count 0 2006.175.07:56:28.93#ibcon#read 6, iclass 6, count 0 2006.175.07:56:28.93#ibcon#end of sib2, iclass 6, count 0 2006.175.07:56:28.93#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:56:28.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:56:28.93#ibcon#[25=USB\r\n] 2006.175.07:56:28.93#ibcon#*before write, iclass 6, count 0 2006.175.07:56:28.93#ibcon#enter sib2, iclass 6, count 0 2006.175.07:56:28.93#ibcon#flushed, iclass 6, count 0 2006.175.07:56:28.93#ibcon#about to write, iclass 6, count 0 2006.175.07:56:28.94#ibcon#wrote, iclass 6, count 0 2006.175.07:56:28.94#ibcon#about to read 3, iclass 6, count 0 2006.175.07:56:28.96#ibcon#read 3, iclass 6, count 0 2006.175.07:56:28.96#ibcon#about to read 4, iclass 6, count 0 2006.175.07:56:28.96#ibcon#read 4, iclass 6, count 0 2006.175.07:56:28.96#ibcon#about to read 5, iclass 6, count 0 2006.175.07:56:28.96#ibcon#read 5, iclass 6, count 0 2006.175.07:56:28.96#ibcon#about to read 6, iclass 6, count 0 2006.175.07:56:28.96#ibcon#read 6, iclass 6, count 0 2006.175.07:56:28.96#ibcon#end of sib2, iclass 6, count 0 2006.175.07:56:28.96#ibcon#*after write, iclass 6, count 0 2006.175.07:56:28.96#ibcon#*before return 0, iclass 6, count 0 2006.175.07:56:28.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:28.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:28.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:56:28.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:56:28.97$vc4f8/valo=4,832.99 2006.175.07:56:28.97#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.07:56:28.97#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.07:56:28.97#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:28.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:28.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:28.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:28.97#ibcon#enter wrdev, iclass 10, count 0 2006.175.07:56:28.97#ibcon#first serial, iclass 10, count 0 2006.175.07:56:28.97#ibcon#enter sib2, iclass 10, count 0 2006.175.07:56:28.97#ibcon#flushed, iclass 10, count 0 2006.175.07:56:28.97#ibcon#about to write, iclass 10, count 0 2006.175.07:56:28.97#ibcon#wrote, iclass 10, count 0 2006.175.07:56:28.97#ibcon#about to read 3, iclass 10, count 0 2006.175.07:56:28.98#ibcon#read 3, iclass 10, count 0 2006.175.07:56:28.98#ibcon#about to read 4, iclass 10, count 0 2006.175.07:56:28.98#ibcon#read 4, iclass 10, count 0 2006.175.07:56:28.98#ibcon#about to read 5, iclass 10, count 0 2006.175.07:56:28.98#ibcon#read 5, iclass 10, count 0 2006.175.07:56:28.98#ibcon#about to read 6, iclass 10, count 0 2006.175.07:56:28.98#ibcon#read 6, iclass 10, count 0 2006.175.07:56:28.98#ibcon#end of sib2, iclass 10, count 0 2006.175.07:56:28.98#ibcon#*mode == 0, iclass 10, count 0 2006.175.07:56:28.98#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.07:56:28.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:56:28.98#ibcon#*before write, iclass 10, count 0 2006.175.07:56:28.98#ibcon#enter sib2, iclass 10, count 0 2006.175.07:56:28.98#ibcon#flushed, iclass 10, count 0 2006.175.07:56:28.98#ibcon#about to write, iclass 10, count 0 2006.175.07:56:28.99#ibcon#wrote, iclass 10, count 0 2006.175.07:56:28.99#ibcon#about to read 3, iclass 10, count 0 2006.175.07:56:29.02#ibcon#read 3, iclass 10, count 0 2006.175.07:56:29.02#ibcon#about to read 4, iclass 10, count 0 2006.175.07:56:29.02#ibcon#read 4, iclass 10, count 0 2006.175.07:56:29.02#ibcon#about to read 5, iclass 10, count 0 2006.175.07:56:29.02#ibcon#read 5, iclass 10, count 0 2006.175.07:56:29.02#ibcon#about to read 6, iclass 10, count 0 2006.175.07:56:29.02#ibcon#read 6, iclass 10, count 0 2006.175.07:56:29.02#ibcon#end of sib2, iclass 10, count 0 2006.175.07:56:29.02#ibcon#*after write, iclass 10, count 0 2006.175.07:56:29.02#ibcon#*before return 0, iclass 10, count 0 2006.175.07:56:29.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:29.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:29.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.07:56:29.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.07:56:29.03$vc4f8/va=4,7 2006.175.07:56:29.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.07:56:29.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.07:56:29.03#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:29.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:29.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:29.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:29.07#ibcon#enter wrdev, iclass 12, count 2 2006.175.07:56:29.07#ibcon#first serial, iclass 12, count 2 2006.175.07:56:29.07#ibcon#enter sib2, iclass 12, count 2 2006.175.07:56:29.07#ibcon#flushed, iclass 12, count 2 2006.175.07:56:29.07#ibcon#about to write, iclass 12, count 2 2006.175.07:56:29.07#ibcon#wrote, iclass 12, count 2 2006.175.07:56:29.07#ibcon#about to read 3, iclass 12, count 2 2006.175.07:56:29.09#ibcon#read 3, iclass 12, count 2 2006.175.07:56:29.09#ibcon#about to read 4, iclass 12, count 2 2006.175.07:56:29.09#ibcon#read 4, iclass 12, count 2 2006.175.07:56:29.09#ibcon#about to read 5, iclass 12, count 2 2006.175.07:56:29.09#ibcon#read 5, iclass 12, count 2 2006.175.07:56:29.09#ibcon#about to read 6, iclass 12, count 2 2006.175.07:56:29.09#ibcon#read 6, iclass 12, count 2 2006.175.07:56:29.09#ibcon#end of sib2, iclass 12, count 2 2006.175.07:56:29.09#ibcon#*mode == 0, iclass 12, count 2 2006.175.07:56:29.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.07:56:29.09#ibcon#[25=AT04-07\r\n] 2006.175.07:56:29.09#ibcon#*before write, iclass 12, count 2 2006.175.07:56:29.09#ibcon#enter sib2, iclass 12, count 2 2006.175.07:56:29.09#ibcon#flushed, iclass 12, count 2 2006.175.07:56:29.09#ibcon#about to write, iclass 12, count 2 2006.175.07:56:29.10#ibcon#wrote, iclass 12, count 2 2006.175.07:56:29.10#ibcon#about to read 3, iclass 12, count 2 2006.175.07:56:29.12#ibcon#read 3, iclass 12, count 2 2006.175.07:56:29.12#ibcon#about to read 4, iclass 12, count 2 2006.175.07:56:29.12#ibcon#read 4, iclass 12, count 2 2006.175.07:56:29.12#ibcon#about to read 5, iclass 12, count 2 2006.175.07:56:29.12#ibcon#read 5, iclass 12, count 2 2006.175.07:56:29.12#ibcon#about to read 6, iclass 12, count 2 2006.175.07:56:29.12#ibcon#read 6, iclass 12, count 2 2006.175.07:56:29.12#ibcon#end of sib2, iclass 12, count 2 2006.175.07:56:29.12#ibcon#*after write, iclass 12, count 2 2006.175.07:56:29.12#ibcon#*before return 0, iclass 12, count 2 2006.175.07:56:29.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:29.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:29.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.07:56:29.12#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:29.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:29.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:29.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:29.24#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:56:29.24#ibcon#first serial, iclass 12, count 0 2006.175.07:56:29.24#ibcon#enter sib2, iclass 12, count 0 2006.175.07:56:29.24#ibcon#flushed, iclass 12, count 0 2006.175.07:56:29.24#ibcon#about to write, iclass 12, count 0 2006.175.07:56:29.24#ibcon#wrote, iclass 12, count 0 2006.175.07:56:29.24#ibcon#about to read 3, iclass 12, count 0 2006.175.07:56:29.26#ibcon#read 3, iclass 12, count 0 2006.175.07:56:29.26#ibcon#about to read 4, iclass 12, count 0 2006.175.07:56:29.26#ibcon#read 4, iclass 12, count 0 2006.175.07:56:29.26#ibcon#about to read 5, iclass 12, count 0 2006.175.07:56:29.26#ibcon#read 5, iclass 12, count 0 2006.175.07:56:29.26#ibcon#about to read 6, iclass 12, count 0 2006.175.07:56:29.26#ibcon#read 6, iclass 12, count 0 2006.175.07:56:29.26#ibcon#end of sib2, iclass 12, count 0 2006.175.07:56:29.26#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:56:29.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:56:29.26#ibcon#[25=USB\r\n] 2006.175.07:56:29.26#ibcon#*before write, iclass 12, count 0 2006.175.07:56:29.26#ibcon#enter sib2, iclass 12, count 0 2006.175.07:56:29.26#ibcon#flushed, iclass 12, count 0 2006.175.07:56:29.26#ibcon#about to write, iclass 12, count 0 2006.175.07:56:29.27#ibcon#wrote, iclass 12, count 0 2006.175.07:56:29.27#ibcon#about to read 3, iclass 12, count 0 2006.175.07:56:29.29#ibcon#read 3, iclass 12, count 0 2006.175.07:56:29.29#ibcon#about to read 4, iclass 12, count 0 2006.175.07:56:29.29#ibcon#read 4, iclass 12, count 0 2006.175.07:56:29.29#ibcon#about to read 5, iclass 12, count 0 2006.175.07:56:29.29#ibcon#read 5, iclass 12, count 0 2006.175.07:56:29.29#ibcon#about to read 6, iclass 12, count 0 2006.175.07:56:29.29#ibcon#read 6, iclass 12, count 0 2006.175.07:56:29.29#ibcon#end of sib2, iclass 12, count 0 2006.175.07:56:29.29#ibcon#*after write, iclass 12, count 0 2006.175.07:56:29.29#ibcon#*before return 0, iclass 12, count 0 2006.175.07:56:29.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:29.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:29.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:56:29.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:56:29.30$vc4f8/valo=5,652.99 2006.175.07:56:29.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.07:56:29.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.07:56:29.30#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:29.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:29.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:29.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:29.30#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:56:29.30#ibcon#first serial, iclass 14, count 0 2006.175.07:56:29.30#ibcon#enter sib2, iclass 14, count 0 2006.175.07:56:29.30#ibcon#flushed, iclass 14, count 0 2006.175.07:56:29.30#ibcon#about to write, iclass 14, count 0 2006.175.07:56:29.30#ibcon#wrote, iclass 14, count 0 2006.175.07:56:29.30#ibcon#about to read 3, iclass 14, count 0 2006.175.07:56:29.31#ibcon#read 3, iclass 14, count 0 2006.175.07:56:29.31#ibcon#about to read 4, iclass 14, count 0 2006.175.07:56:29.31#ibcon#read 4, iclass 14, count 0 2006.175.07:56:29.31#ibcon#about to read 5, iclass 14, count 0 2006.175.07:56:29.31#ibcon#read 5, iclass 14, count 0 2006.175.07:56:29.31#ibcon#about to read 6, iclass 14, count 0 2006.175.07:56:29.31#ibcon#read 6, iclass 14, count 0 2006.175.07:56:29.31#ibcon#end of sib2, iclass 14, count 0 2006.175.07:56:29.31#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:56:29.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:56:29.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:56:29.31#ibcon#*before write, iclass 14, count 0 2006.175.07:56:29.31#ibcon#enter sib2, iclass 14, count 0 2006.175.07:56:29.32#ibcon#flushed, iclass 14, count 0 2006.175.07:56:29.32#ibcon#about to write, iclass 14, count 0 2006.175.07:56:29.32#ibcon#wrote, iclass 14, count 0 2006.175.07:56:29.32#ibcon#about to read 3, iclass 14, count 0 2006.175.07:56:29.35#ibcon#read 3, iclass 14, count 0 2006.175.07:56:29.35#ibcon#about to read 4, iclass 14, count 0 2006.175.07:56:29.35#ibcon#read 4, iclass 14, count 0 2006.175.07:56:29.35#ibcon#about to read 5, iclass 14, count 0 2006.175.07:56:29.35#ibcon#read 5, iclass 14, count 0 2006.175.07:56:29.35#ibcon#about to read 6, iclass 14, count 0 2006.175.07:56:29.35#ibcon#read 6, iclass 14, count 0 2006.175.07:56:29.35#ibcon#end of sib2, iclass 14, count 0 2006.175.07:56:29.35#ibcon#*after write, iclass 14, count 0 2006.175.07:56:29.35#ibcon#*before return 0, iclass 14, count 0 2006.175.07:56:29.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:29.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:29.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:56:29.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:56:29.36$vc4f8/va=5,7 2006.175.07:56:29.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.07:56:29.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.07:56:29.36#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:29.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:29.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:29.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:29.40#ibcon#enter wrdev, iclass 16, count 2 2006.175.07:56:29.40#ibcon#first serial, iclass 16, count 2 2006.175.07:56:29.40#ibcon#enter sib2, iclass 16, count 2 2006.175.07:56:29.40#ibcon#flushed, iclass 16, count 2 2006.175.07:56:29.40#ibcon#about to write, iclass 16, count 2 2006.175.07:56:29.40#ibcon#wrote, iclass 16, count 2 2006.175.07:56:29.40#ibcon#about to read 3, iclass 16, count 2 2006.175.07:56:29.42#ibcon#read 3, iclass 16, count 2 2006.175.07:56:29.42#ibcon#about to read 4, iclass 16, count 2 2006.175.07:56:29.42#ibcon#read 4, iclass 16, count 2 2006.175.07:56:29.42#ibcon#about to read 5, iclass 16, count 2 2006.175.07:56:29.42#ibcon#read 5, iclass 16, count 2 2006.175.07:56:29.42#ibcon#about to read 6, iclass 16, count 2 2006.175.07:56:29.42#ibcon#read 6, iclass 16, count 2 2006.175.07:56:29.42#ibcon#end of sib2, iclass 16, count 2 2006.175.07:56:29.42#ibcon#*mode == 0, iclass 16, count 2 2006.175.07:56:29.42#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.07:56:29.42#ibcon#[25=AT05-07\r\n] 2006.175.07:56:29.42#ibcon#*before write, iclass 16, count 2 2006.175.07:56:29.43#ibcon#enter sib2, iclass 16, count 2 2006.175.07:56:29.43#ibcon#flushed, iclass 16, count 2 2006.175.07:56:29.43#ibcon#about to write, iclass 16, count 2 2006.175.07:56:29.43#ibcon#wrote, iclass 16, count 2 2006.175.07:56:29.43#ibcon#about to read 3, iclass 16, count 2 2006.175.07:56:29.45#ibcon#read 3, iclass 16, count 2 2006.175.07:56:29.45#ibcon#about to read 4, iclass 16, count 2 2006.175.07:56:29.45#ibcon#read 4, iclass 16, count 2 2006.175.07:56:29.45#ibcon#about to read 5, iclass 16, count 2 2006.175.07:56:29.45#ibcon#read 5, iclass 16, count 2 2006.175.07:56:29.45#ibcon#about to read 6, iclass 16, count 2 2006.175.07:56:29.45#ibcon#read 6, iclass 16, count 2 2006.175.07:56:29.45#ibcon#end of sib2, iclass 16, count 2 2006.175.07:56:29.45#ibcon#*after write, iclass 16, count 2 2006.175.07:56:29.45#ibcon#*before return 0, iclass 16, count 2 2006.175.07:56:29.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:29.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:29.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.07:56:29.45#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:29.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:29.57#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:29.57#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:29.57#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:56:29.57#ibcon#first serial, iclass 16, count 0 2006.175.07:56:29.57#ibcon#enter sib2, iclass 16, count 0 2006.175.07:56:29.57#ibcon#flushed, iclass 16, count 0 2006.175.07:56:29.57#ibcon#about to write, iclass 16, count 0 2006.175.07:56:29.57#ibcon#wrote, iclass 16, count 0 2006.175.07:56:29.57#ibcon#about to read 3, iclass 16, count 0 2006.175.07:56:29.59#ibcon#read 3, iclass 16, count 0 2006.175.07:56:29.59#ibcon#about to read 4, iclass 16, count 0 2006.175.07:56:29.59#ibcon#read 4, iclass 16, count 0 2006.175.07:56:29.59#ibcon#about to read 5, iclass 16, count 0 2006.175.07:56:29.59#ibcon#read 5, iclass 16, count 0 2006.175.07:56:29.59#ibcon#about to read 6, iclass 16, count 0 2006.175.07:56:29.59#ibcon#read 6, iclass 16, count 0 2006.175.07:56:29.59#ibcon#end of sib2, iclass 16, count 0 2006.175.07:56:29.59#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:56:29.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:56:29.59#ibcon#[25=USB\r\n] 2006.175.07:56:29.59#ibcon#*before write, iclass 16, count 0 2006.175.07:56:29.59#ibcon#enter sib2, iclass 16, count 0 2006.175.07:56:29.59#ibcon#flushed, iclass 16, count 0 2006.175.07:56:29.59#ibcon#about to write, iclass 16, count 0 2006.175.07:56:29.60#ibcon#wrote, iclass 16, count 0 2006.175.07:56:29.60#ibcon#about to read 3, iclass 16, count 0 2006.175.07:56:29.62#ibcon#read 3, iclass 16, count 0 2006.175.07:56:29.62#ibcon#about to read 4, iclass 16, count 0 2006.175.07:56:29.62#ibcon#read 4, iclass 16, count 0 2006.175.07:56:29.62#ibcon#about to read 5, iclass 16, count 0 2006.175.07:56:29.62#ibcon#read 5, iclass 16, count 0 2006.175.07:56:29.62#ibcon#about to read 6, iclass 16, count 0 2006.175.07:56:29.62#ibcon#read 6, iclass 16, count 0 2006.175.07:56:29.62#ibcon#end of sib2, iclass 16, count 0 2006.175.07:56:29.62#ibcon#*after write, iclass 16, count 0 2006.175.07:56:29.62#ibcon#*before return 0, iclass 16, count 0 2006.175.07:56:29.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:29.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:29.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:56:29.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:56:29.63$vc4f8/valo=6,772.99 2006.175.07:56:29.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.07:56:29.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.07:56:29.63#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:29.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:29.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:29.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:29.63#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:56:29.63#ibcon#first serial, iclass 18, count 0 2006.175.07:56:29.63#ibcon#enter sib2, iclass 18, count 0 2006.175.07:56:29.63#ibcon#flushed, iclass 18, count 0 2006.175.07:56:29.63#ibcon#about to write, iclass 18, count 0 2006.175.07:56:29.63#ibcon#wrote, iclass 18, count 0 2006.175.07:56:29.63#ibcon#about to read 3, iclass 18, count 0 2006.175.07:56:29.64#ibcon#read 3, iclass 18, count 0 2006.175.07:56:29.64#ibcon#about to read 4, iclass 18, count 0 2006.175.07:56:29.64#ibcon#read 4, iclass 18, count 0 2006.175.07:56:29.64#ibcon#about to read 5, iclass 18, count 0 2006.175.07:56:29.64#ibcon#read 5, iclass 18, count 0 2006.175.07:56:29.64#ibcon#about to read 6, iclass 18, count 0 2006.175.07:56:29.64#ibcon#read 6, iclass 18, count 0 2006.175.07:56:29.64#ibcon#end of sib2, iclass 18, count 0 2006.175.07:56:29.64#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:56:29.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:56:29.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:56:29.64#ibcon#*before write, iclass 18, count 0 2006.175.07:56:29.64#ibcon#enter sib2, iclass 18, count 0 2006.175.07:56:29.64#ibcon#flushed, iclass 18, count 0 2006.175.07:56:29.64#ibcon#about to write, iclass 18, count 0 2006.175.07:56:29.65#ibcon#wrote, iclass 18, count 0 2006.175.07:56:29.65#ibcon#about to read 3, iclass 18, count 0 2006.175.07:56:29.68#ibcon#read 3, iclass 18, count 0 2006.175.07:56:29.68#ibcon#about to read 4, iclass 18, count 0 2006.175.07:56:29.68#ibcon#read 4, iclass 18, count 0 2006.175.07:56:29.68#ibcon#about to read 5, iclass 18, count 0 2006.175.07:56:29.68#ibcon#read 5, iclass 18, count 0 2006.175.07:56:29.68#ibcon#about to read 6, iclass 18, count 0 2006.175.07:56:29.68#ibcon#read 6, iclass 18, count 0 2006.175.07:56:29.68#ibcon#end of sib2, iclass 18, count 0 2006.175.07:56:29.68#ibcon#*after write, iclass 18, count 0 2006.175.07:56:29.68#ibcon#*before return 0, iclass 18, count 0 2006.175.07:56:29.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:29.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:29.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:56:29.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:56:29.69$vc4f8/va=6,6 2006.175.07:56:29.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.175.07:56:29.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.175.07:56:29.69#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:29.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:56:29.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:56:29.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:56:29.73#ibcon#enter wrdev, iclass 20, count 2 2006.175.07:56:29.73#ibcon#first serial, iclass 20, count 2 2006.175.07:56:29.73#ibcon#enter sib2, iclass 20, count 2 2006.175.07:56:29.73#ibcon#flushed, iclass 20, count 2 2006.175.07:56:29.73#ibcon#about to write, iclass 20, count 2 2006.175.07:56:29.73#ibcon#wrote, iclass 20, count 2 2006.175.07:56:29.73#ibcon#about to read 3, iclass 20, count 2 2006.175.07:56:29.75#ibcon#read 3, iclass 20, count 2 2006.175.07:56:29.75#ibcon#about to read 4, iclass 20, count 2 2006.175.07:56:29.75#ibcon#read 4, iclass 20, count 2 2006.175.07:56:29.75#ibcon#about to read 5, iclass 20, count 2 2006.175.07:56:29.75#ibcon#read 5, iclass 20, count 2 2006.175.07:56:29.75#ibcon#about to read 6, iclass 20, count 2 2006.175.07:56:29.75#ibcon#read 6, iclass 20, count 2 2006.175.07:56:29.75#ibcon#end of sib2, iclass 20, count 2 2006.175.07:56:29.75#ibcon#*mode == 0, iclass 20, count 2 2006.175.07:56:29.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.175.07:56:29.75#ibcon#[25=AT06-06\r\n] 2006.175.07:56:29.75#ibcon#*before write, iclass 20, count 2 2006.175.07:56:29.75#ibcon#enter sib2, iclass 20, count 2 2006.175.07:56:29.75#ibcon#flushed, iclass 20, count 2 2006.175.07:56:29.75#ibcon#about to write, iclass 20, count 2 2006.175.07:56:29.76#ibcon#wrote, iclass 20, count 2 2006.175.07:56:29.76#ibcon#about to read 3, iclass 20, count 2 2006.175.07:56:29.78#ibcon#read 3, iclass 20, count 2 2006.175.07:56:29.78#ibcon#about to read 4, iclass 20, count 2 2006.175.07:56:29.78#ibcon#read 4, iclass 20, count 2 2006.175.07:56:29.78#ibcon#about to read 5, iclass 20, count 2 2006.175.07:56:29.78#ibcon#read 5, iclass 20, count 2 2006.175.07:56:29.78#ibcon#about to read 6, iclass 20, count 2 2006.175.07:56:29.78#ibcon#read 6, iclass 20, count 2 2006.175.07:56:29.78#ibcon#end of sib2, iclass 20, count 2 2006.175.07:56:29.78#ibcon#*after write, iclass 20, count 2 2006.175.07:56:29.78#ibcon#*before return 0, iclass 20, count 2 2006.175.07:56:29.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:56:29.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.175.07:56:29.78#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.175.07:56:29.78#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:29.78#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:56:29.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:56:29.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:56:29.90#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:56:29.90#ibcon#first serial, iclass 20, count 0 2006.175.07:56:29.90#ibcon#enter sib2, iclass 20, count 0 2006.175.07:56:29.90#ibcon#flushed, iclass 20, count 0 2006.175.07:56:29.90#ibcon#about to write, iclass 20, count 0 2006.175.07:56:29.90#ibcon#wrote, iclass 20, count 0 2006.175.07:56:29.90#ibcon#about to read 3, iclass 20, count 0 2006.175.07:56:29.92#ibcon#read 3, iclass 20, count 0 2006.175.07:56:29.92#ibcon#about to read 4, iclass 20, count 0 2006.175.07:56:29.92#ibcon#read 4, iclass 20, count 0 2006.175.07:56:29.92#ibcon#about to read 5, iclass 20, count 0 2006.175.07:56:29.92#ibcon#read 5, iclass 20, count 0 2006.175.07:56:29.92#ibcon#about to read 6, iclass 20, count 0 2006.175.07:56:29.92#ibcon#read 6, iclass 20, count 0 2006.175.07:56:29.92#ibcon#end of sib2, iclass 20, count 0 2006.175.07:56:29.92#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:56:29.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:56:29.92#ibcon#[25=USB\r\n] 2006.175.07:56:29.92#ibcon#*before write, iclass 20, count 0 2006.175.07:56:29.92#ibcon#enter sib2, iclass 20, count 0 2006.175.07:56:29.92#ibcon#flushed, iclass 20, count 0 2006.175.07:56:29.92#ibcon#about to write, iclass 20, count 0 2006.175.07:56:29.93#ibcon#wrote, iclass 20, count 0 2006.175.07:56:29.93#ibcon#about to read 3, iclass 20, count 0 2006.175.07:56:29.95#ibcon#read 3, iclass 20, count 0 2006.175.07:56:29.95#ibcon#about to read 4, iclass 20, count 0 2006.175.07:56:29.95#ibcon#read 4, iclass 20, count 0 2006.175.07:56:29.95#ibcon#about to read 5, iclass 20, count 0 2006.175.07:56:29.95#ibcon#read 5, iclass 20, count 0 2006.175.07:56:29.95#ibcon#about to read 6, iclass 20, count 0 2006.175.07:56:29.95#ibcon#read 6, iclass 20, count 0 2006.175.07:56:29.95#ibcon#end of sib2, iclass 20, count 0 2006.175.07:56:29.95#ibcon#*after write, iclass 20, count 0 2006.175.07:56:29.95#ibcon#*before return 0, iclass 20, count 0 2006.175.07:56:29.95#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:56:29.95#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.175.07:56:29.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:56:29.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:56:29.96$vc4f8/valo=7,832.99 2006.175.07:56:29.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.07:56:29.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.07:56:29.96#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:29.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:56:29.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:56:29.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:56:29.96#ibcon#enter wrdev, iclass 22, count 0 2006.175.07:56:29.96#ibcon#first serial, iclass 22, count 0 2006.175.07:56:29.96#ibcon#enter sib2, iclass 22, count 0 2006.175.07:56:29.96#ibcon#flushed, iclass 22, count 0 2006.175.07:56:29.96#ibcon#about to write, iclass 22, count 0 2006.175.07:56:29.96#ibcon#wrote, iclass 22, count 0 2006.175.07:56:29.96#ibcon#about to read 3, iclass 22, count 0 2006.175.07:56:29.97#ibcon#read 3, iclass 22, count 0 2006.175.07:56:29.97#ibcon#about to read 4, iclass 22, count 0 2006.175.07:56:29.97#ibcon#read 4, iclass 22, count 0 2006.175.07:56:29.97#ibcon#about to read 5, iclass 22, count 0 2006.175.07:56:29.97#ibcon#read 5, iclass 22, count 0 2006.175.07:56:29.97#ibcon#about to read 6, iclass 22, count 0 2006.175.07:56:29.97#ibcon#read 6, iclass 22, count 0 2006.175.07:56:29.97#ibcon#end of sib2, iclass 22, count 0 2006.175.07:56:29.97#ibcon#*mode == 0, iclass 22, count 0 2006.175.07:56:29.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.07:56:29.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.07:56:29.97#ibcon#*before write, iclass 22, count 0 2006.175.07:56:29.97#ibcon#enter sib2, iclass 22, count 0 2006.175.07:56:29.97#ibcon#flushed, iclass 22, count 0 2006.175.07:56:29.97#ibcon#about to write, iclass 22, count 0 2006.175.07:56:29.98#ibcon#wrote, iclass 22, count 0 2006.175.07:56:29.98#ibcon#about to read 3, iclass 22, count 0 2006.175.07:56:30.01#ibcon#read 3, iclass 22, count 0 2006.175.07:56:30.01#ibcon#about to read 4, iclass 22, count 0 2006.175.07:56:30.01#ibcon#read 4, iclass 22, count 0 2006.175.07:56:30.01#ibcon#about to read 5, iclass 22, count 0 2006.175.07:56:30.01#ibcon#read 5, iclass 22, count 0 2006.175.07:56:30.01#ibcon#about to read 6, iclass 22, count 0 2006.175.07:56:30.01#ibcon#read 6, iclass 22, count 0 2006.175.07:56:30.01#ibcon#end of sib2, iclass 22, count 0 2006.175.07:56:30.01#ibcon#*after write, iclass 22, count 0 2006.175.07:56:30.01#ibcon#*before return 0, iclass 22, count 0 2006.175.07:56:30.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:56:30.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.07:56:30.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.07:56:30.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.07:56:30.02$vc4f8/va=7,6 2006.175.07:56:30.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.07:56:30.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.07:56:30.02#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:30.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:56:30.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:56:30.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:56:30.06#ibcon#enter wrdev, iclass 24, count 2 2006.175.07:56:30.06#ibcon#first serial, iclass 24, count 2 2006.175.07:56:30.06#ibcon#enter sib2, iclass 24, count 2 2006.175.07:56:30.06#ibcon#flushed, iclass 24, count 2 2006.175.07:56:30.06#ibcon#about to write, iclass 24, count 2 2006.175.07:56:30.06#ibcon#wrote, iclass 24, count 2 2006.175.07:56:30.06#ibcon#about to read 3, iclass 24, count 2 2006.175.07:56:30.08#ibcon#read 3, iclass 24, count 2 2006.175.07:56:30.08#ibcon#about to read 4, iclass 24, count 2 2006.175.07:56:30.08#ibcon#read 4, iclass 24, count 2 2006.175.07:56:30.08#ibcon#about to read 5, iclass 24, count 2 2006.175.07:56:30.08#ibcon#read 5, iclass 24, count 2 2006.175.07:56:30.08#ibcon#about to read 6, iclass 24, count 2 2006.175.07:56:30.08#ibcon#read 6, iclass 24, count 2 2006.175.07:56:30.08#ibcon#end of sib2, iclass 24, count 2 2006.175.07:56:30.08#ibcon#*mode == 0, iclass 24, count 2 2006.175.07:56:30.08#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.07:56:30.08#ibcon#[25=AT07-06\r\n] 2006.175.07:56:30.08#ibcon#*before write, iclass 24, count 2 2006.175.07:56:30.08#ibcon#enter sib2, iclass 24, count 2 2006.175.07:56:30.08#ibcon#flushed, iclass 24, count 2 2006.175.07:56:30.08#ibcon#about to write, iclass 24, count 2 2006.175.07:56:30.09#ibcon#wrote, iclass 24, count 2 2006.175.07:56:30.09#ibcon#about to read 3, iclass 24, count 2 2006.175.07:56:30.11#ibcon#read 3, iclass 24, count 2 2006.175.07:56:30.11#ibcon#about to read 4, iclass 24, count 2 2006.175.07:56:30.11#ibcon#read 4, iclass 24, count 2 2006.175.07:56:30.11#ibcon#about to read 5, iclass 24, count 2 2006.175.07:56:30.11#ibcon#read 5, iclass 24, count 2 2006.175.07:56:30.11#ibcon#about to read 6, iclass 24, count 2 2006.175.07:56:30.11#ibcon#read 6, iclass 24, count 2 2006.175.07:56:30.11#ibcon#end of sib2, iclass 24, count 2 2006.175.07:56:30.11#ibcon#*after write, iclass 24, count 2 2006.175.07:56:30.11#ibcon#*before return 0, iclass 24, count 2 2006.175.07:56:30.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:56:30.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.07:56:30.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.07:56:30.11#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:30.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:56:30.23#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:56:30.23#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:56:30.23#ibcon#enter wrdev, iclass 24, count 0 2006.175.07:56:30.23#ibcon#first serial, iclass 24, count 0 2006.175.07:56:30.23#ibcon#enter sib2, iclass 24, count 0 2006.175.07:56:30.23#ibcon#flushed, iclass 24, count 0 2006.175.07:56:30.23#ibcon#about to write, iclass 24, count 0 2006.175.07:56:30.23#ibcon#wrote, iclass 24, count 0 2006.175.07:56:30.23#ibcon#about to read 3, iclass 24, count 0 2006.175.07:56:30.25#ibcon#read 3, iclass 24, count 0 2006.175.07:56:30.25#ibcon#about to read 4, iclass 24, count 0 2006.175.07:56:30.25#ibcon#read 4, iclass 24, count 0 2006.175.07:56:30.25#ibcon#about to read 5, iclass 24, count 0 2006.175.07:56:30.25#ibcon#read 5, iclass 24, count 0 2006.175.07:56:30.25#ibcon#about to read 6, iclass 24, count 0 2006.175.07:56:30.25#ibcon#read 6, iclass 24, count 0 2006.175.07:56:30.25#ibcon#end of sib2, iclass 24, count 0 2006.175.07:56:30.25#ibcon#*mode == 0, iclass 24, count 0 2006.175.07:56:30.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.07:56:30.25#ibcon#[25=USB\r\n] 2006.175.07:56:30.25#ibcon#*before write, iclass 24, count 0 2006.175.07:56:30.25#ibcon#enter sib2, iclass 24, count 0 2006.175.07:56:30.25#ibcon#flushed, iclass 24, count 0 2006.175.07:56:30.25#ibcon#about to write, iclass 24, count 0 2006.175.07:56:30.26#ibcon#wrote, iclass 24, count 0 2006.175.07:56:30.26#ibcon#about to read 3, iclass 24, count 0 2006.175.07:56:30.28#ibcon#read 3, iclass 24, count 0 2006.175.07:56:30.28#ibcon#about to read 4, iclass 24, count 0 2006.175.07:56:30.28#ibcon#read 4, iclass 24, count 0 2006.175.07:56:30.28#ibcon#about to read 5, iclass 24, count 0 2006.175.07:56:30.28#ibcon#read 5, iclass 24, count 0 2006.175.07:56:30.28#ibcon#about to read 6, iclass 24, count 0 2006.175.07:56:30.28#ibcon#read 6, iclass 24, count 0 2006.175.07:56:30.28#ibcon#end of sib2, iclass 24, count 0 2006.175.07:56:30.28#ibcon#*after write, iclass 24, count 0 2006.175.07:56:30.28#ibcon#*before return 0, iclass 24, count 0 2006.175.07:56:30.28#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:56:30.28#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.07:56:30.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.07:56:30.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.07:56:30.29$vc4f8/valo=8,852.99 2006.175.07:56:30.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.07:56:30.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.07:56:30.29#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:30.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:56:30.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:56:30.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:56:30.29#ibcon#enter wrdev, iclass 26, count 0 2006.175.07:56:30.29#ibcon#first serial, iclass 26, count 0 2006.175.07:56:30.29#ibcon#enter sib2, iclass 26, count 0 2006.175.07:56:30.29#ibcon#flushed, iclass 26, count 0 2006.175.07:56:30.29#ibcon#about to write, iclass 26, count 0 2006.175.07:56:30.29#ibcon#wrote, iclass 26, count 0 2006.175.07:56:30.29#ibcon#about to read 3, iclass 26, count 0 2006.175.07:56:30.30#ibcon#read 3, iclass 26, count 0 2006.175.07:56:30.30#ibcon#about to read 4, iclass 26, count 0 2006.175.07:56:30.30#ibcon#read 4, iclass 26, count 0 2006.175.07:56:30.30#ibcon#about to read 5, iclass 26, count 0 2006.175.07:56:30.30#ibcon#read 5, iclass 26, count 0 2006.175.07:56:30.30#ibcon#about to read 6, iclass 26, count 0 2006.175.07:56:30.30#ibcon#read 6, iclass 26, count 0 2006.175.07:56:30.30#ibcon#end of sib2, iclass 26, count 0 2006.175.07:56:30.30#ibcon#*mode == 0, iclass 26, count 0 2006.175.07:56:30.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.07:56:30.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.07:56:30.30#ibcon#*before write, iclass 26, count 0 2006.175.07:56:30.30#ibcon#enter sib2, iclass 26, count 0 2006.175.07:56:30.30#ibcon#flushed, iclass 26, count 0 2006.175.07:56:30.30#ibcon#about to write, iclass 26, count 0 2006.175.07:56:30.31#ibcon#wrote, iclass 26, count 0 2006.175.07:56:30.31#ibcon#about to read 3, iclass 26, count 0 2006.175.07:56:30.34#ibcon#read 3, iclass 26, count 0 2006.175.07:56:30.34#ibcon#about to read 4, iclass 26, count 0 2006.175.07:56:30.34#ibcon#read 4, iclass 26, count 0 2006.175.07:56:30.34#ibcon#about to read 5, iclass 26, count 0 2006.175.07:56:30.34#ibcon#read 5, iclass 26, count 0 2006.175.07:56:30.34#ibcon#about to read 6, iclass 26, count 0 2006.175.07:56:30.34#ibcon#read 6, iclass 26, count 0 2006.175.07:56:30.34#ibcon#end of sib2, iclass 26, count 0 2006.175.07:56:30.34#ibcon#*after write, iclass 26, count 0 2006.175.07:56:30.34#ibcon#*before return 0, iclass 26, count 0 2006.175.07:56:30.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:56:30.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.07:56:30.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.07:56:30.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.07:56:30.35$vc4f8/va=8,6 2006.175.07:56:30.35#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.07:56:30.35#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.07:56:30.35#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:30.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:56:30.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:56:30.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:56:30.39#ibcon#enter wrdev, iclass 28, count 2 2006.175.07:56:30.39#ibcon#first serial, iclass 28, count 2 2006.175.07:56:30.39#ibcon#enter sib2, iclass 28, count 2 2006.175.07:56:30.39#ibcon#flushed, iclass 28, count 2 2006.175.07:56:30.39#ibcon#about to write, iclass 28, count 2 2006.175.07:56:30.39#ibcon#wrote, iclass 28, count 2 2006.175.07:56:30.39#ibcon#about to read 3, iclass 28, count 2 2006.175.07:56:30.41#ibcon#read 3, iclass 28, count 2 2006.175.07:56:30.41#ibcon#about to read 4, iclass 28, count 2 2006.175.07:56:30.41#ibcon#read 4, iclass 28, count 2 2006.175.07:56:30.41#ibcon#about to read 5, iclass 28, count 2 2006.175.07:56:30.41#ibcon#read 5, iclass 28, count 2 2006.175.07:56:30.41#ibcon#about to read 6, iclass 28, count 2 2006.175.07:56:30.41#ibcon#read 6, iclass 28, count 2 2006.175.07:56:30.41#ibcon#end of sib2, iclass 28, count 2 2006.175.07:56:30.41#ibcon#*mode == 0, iclass 28, count 2 2006.175.07:56:30.41#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.07:56:30.41#ibcon#[25=AT08-06\r\n] 2006.175.07:56:30.41#ibcon#*before write, iclass 28, count 2 2006.175.07:56:30.41#ibcon#enter sib2, iclass 28, count 2 2006.175.07:56:30.42#ibcon#flushed, iclass 28, count 2 2006.175.07:56:30.42#ibcon#about to write, iclass 28, count 2 2006.175.07:56:30.42#ibcon#wrote, iclass 28, count 2 2006.175.07:56:30.42#ibcon#about to read 3, iclass 28, count 2 2006.175.07:56:30.44#ibcon#read 3, iclass 28, count 2 2006.175.07:56:30.44#ibcon#about to read 4, iclass 28, count 2 2006.175.07:56:30.44#ibcon#read 4, iclass 28, count 2 2006.175.07:56:30.44#ibcon#about to read 5, iclass 28, count 2 2006.175.07:56:30.44#ibcon#read 5, iclass 28, count 2 2006.175.07:56:30.44#ibcon#about to read 6, iclass 28, count 2 2006.175.07:56:30.44#ibcon#read 6, iclass 28, count 2 2006.175.07:56:30.44#ibcon#end of sib2, iclass 28, count 2 2006.175.07:56:30.44#ibcon#*after write, iclass 28, count 2 2006.175.07:56:30.44#ibcon#*before return 0, iclass 28, count 2 2006.175.07:56:30.44#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:56:30.44#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.07:56:30.44#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.07:56:30.44#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:30.44#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:56:30.56#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:56:30.56#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:56:30.56#ibcon#enter wrdev, iclass 28, count 0 2006.175.07:56:30.56#ibcon#first serial, iclass 28, count 0 2006.175.07:56:30.56#ibcon#enter sib2, iclass 28, count 0 2006.175.07:56:30.56#ibcon#flushed, iclass 28, count 0 2006.175.07:56:30.56#ibcon#about to write, iclass 28, count 0 2006.175.07:56:30.56#ibcon#wrote, iclass 28, count 0 2006.175.07:56:30.56#ibcon#about to read 3, iclass 28, count 0 2006.175.07:56:30.58#ibcon#read 3, iclass 28, count 0 2006.175.07:56:30.58#ibcon#about to read 4, iclass 28, count 0 2006.175.07:56:30.58#ibcon#read 4, iclass 28, count 0 2006.175.07:56:30.58#ibcon#about to read 5, iclass 28, count 0 2006.175.07:56:30.58#ibcon#read 5, iclass 28, count 0 2006.175.07:56:30.58#ibcon#about to read 6, iclass 28, count 0 2006.175.07:56:30.58#ibcon#read 6, iclass 28, count 0 2006.175.07:56:30.58#ibcon#end of sib2, iclass 28, count 0 2006.175.07:56:30.58#ibcon#*mode == 0, iclass 28, count 0 2006.175.07:56:30.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.07:56:30.58#ibcon#[25=USB\r\n] 2006.175.07:56:30.58#ibcon#*before write, iclass 28, count 0 2006.175.07:56:30.58#ibcon#enter sib2, iclass 28, count 0 2006.175.07:56:30.58#ibcon#flushed, iclass 28, count 0 2006.175.07:56:30.58#ibcon#about to write, iclass 28, count 0 2006.175.07:56:30.59#ibcon#wrote, iclass 28, count 0 2006.175.07:56:30.59#ibcon#about to read 3, iclass 28, count 0 2006.175.07:56:30.61#ibcon#read 3, iclass 28, count 0 2006.175.07:56:30.61#ibcon#about to read 4, iclass 28, count 0 2006.175.07:56:30.61#ibcon#read 4, iclass 28, count 0 2006.175.07:56:30.61#ibcon#about to read 5, iclass 28, count 0 2006.175.07:56:30.61#ibcon#read 5, iclass 28, count 0 2006.175.07:56:30.61#ibcon#about to read 6, iclass 28, count 0 2006.175.07:56:30.61#ibcon#read 6, iclass 28, count 0 2006.175.07:56:30.61#ibcon#end of sib2, iclass 28, count 0 2006.175.07:56:30.61#ibcon#*after write, iclass 28, count 0 2006.175.07:56:30.61#ibcon#*before return 0, iclass 28, count 0 2006.175.07:56:30.61#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:56:30.61#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.07:56:30.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.07:56:30.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.07:56:30.62$vc4f8/vblo=1,632.99 2006.175.07:56:30.62#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.07:56:30.62#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.07:56:30.62#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:30.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:56:30.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:56:30.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:56:30.62#ibcon#enter wrdev, iclass 30, count 0 2006.175.07:56:30.62#ibcon#first serial, iclass 30, count 0 2006.175.07:56:30.62#ibcon#enter sib2, iclass 30, count 0 2006.175.07:56:30.62#ibcon#flushed, iclass 30, count 0 2006.175.07:56:30.62#ibcon#about to write, iclass 30, count 0 2006.175.07:56:30.62#ibcon#wrote, iclass 30, count 0 2006.175.07:56:30.62#ibcon#about to read 3, iclass 30, count 0 2006.175.07:56:30.63#ibcon#read 3, iclass 30, count 0 2006.175.07:56:30.63#ibcon#about to read 4, iclass 30, count 0 2006.175.07:56:30.63#ibcon#read 4, iclass 30, count 0 2006.175.07:56:30.63#ibcon#about to read 5, iclass 30, count 0 2006.175.07:56:30.63#ibcon#read 5, iclass 30, count 0 2006.175.07:56:30.63#ibcon#about to read 6, iclass 30, count 0 2006.175.07:56:30.63#ibcon#read 6, iclass 30, count 0 2006.175.07:56:30.63#ibcon#end of sib2, iclass 30, count 0 2006.175.07:56:30.63#ibcon#*mode == 0, iclass 30, count 0 2006.175.07:56:30.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.07:56:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.07:56:30.63#ibcon#*before write, iclass 30, count 0 2006.175.07:56:30.63#ibcon#enter sib2, iclass 30, count 0 2006.175.07:56:30.64#ibcon#flushed, iclass 30, count 0 2006.175.07:56:30.64#ibcon#about to write, iclass 30, count 0 2006.175.07:56:30.64#ibcon#wrote, iclass 30, count 0 2006.175.07:56:30.64#ibcon#about to read 3, iclass 30, count 0 2006.175.07:56:30.67#ibcon#read 3, iclass 30, count 0 2006.175.07:56:30.67#ibcon#about to read 4, iclass 30, count 0 2006.175.07:56:30.67#ibcon#read 4, iclass 30, count 0 2006.175.07:56:30.67#ibcon#about to read 5, iclass 30, count 0 2006.175.07:56:30.67#ibcon#read 5, iclass 30, count 0 2006.175.07:56:30.67#ibcon#about to read 6, iclass 30, count 0 2006.175.07:56:30.67#ibcon#read 6, iclass 30, count 0 2006.175.07:56:30.67#ibcon#end of sib2, iclass 30, count 0 2006.175.07:56:30.67#ibcon#*after write, iclass 30, count 0 2006.175.07:56:30.67#ibcon#*before return 0, iclass 30, count 0 2006.175.07:56:30.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:56:30.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.07:56:30.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.07:56:30.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.07:56:30.68$vc4f8/vb=1,4 2006.175.07:56:30.68#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.07:56:30.68#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.07:56:30.68#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:30.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:56:30.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:56:30.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:56:30.68#ibcon#enter wrdev, iclass 32, count 2 2006.175.07:56:30.68#ibcon#first serial, iclass 32, count 2 2006.175.07:56:30.68#ibcon#enter sib2, iclass 32, count 2 2006.175.07:56:30.68#ibcon#flushed, iclass 32, count 2 2006.175.07:56:30.68#ibcon#about to write, iclass 32, count 2 2006.175.07:56:30.68#ibcon#wrote, iclass 32, count 2 2006.175.07:56:30.68#ibcon#about to read 3, iclass 32, count 2 2006.175.07:56:30.69#ibcon#read 3, iclass 32, count 2 2006.175.07:56:30.69#ibcon#about to read 4, iclass 32, count 2 2006.175.07:56:30.69#ibcon#read 4, iclass 32, count 2 2006.175.07:56:30.69#ibcon#about to read 5, iclass 32, count 2 2006.175.07:56:30.69#ibcon#read 5, iclass 32, count 2 2006.175.07:56:30.69#ibcon#about to read 6, iclass 32, count 2 2006.175.07:56:30.69#ibcon#read 6, iclass 32, count 2 2006.175.07:56:30.69#ibcon#end of sib2, iclass 32, count 2 2006.175.07:56:30.69#ibcon#*mode == 0, iclass 32, count 2 2006.175.07:56:30.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.07:56:30.69#ibcon#[27=AT01-04\r\n] 2006.175.07:56:30.69#ibcon#*before write, iclass 32, count 2 2006.175.07:56:30.69#ibcon#enter sib2, iclass 32, count 2 2006.175.07:56:30.70#ibcon#flushed, iclass 32, count 2 2006.175.07:56:30.70#ibcon#about to write, iclass 32, count 2 2006.175.07:56:30.70#ibcon#wrote, iclass 32, count 2 2006.175.07:56:30.70#ibcon#about to read 3, iclass 32, count 2 2006.175.07:56:30.72#ibcon#read 3, iclass 32, count 2 2006.175.07:56:30.72#ibcon#about to read 4, iclass 32, count 2 2006.175.07:56:30.72#ibcon#read 4, iclass 32, count 2 2006.175.07:56:30.72#ibcon#about to read 5, iclass 32, count 2 2006.175.07:56:30.72#ibcon#read 5, iclass 32, count 2 2006.175.07:56:30.72#ibcon#about to read 6, iclass 32, count 2 2006.175.07:56:30.72#ibcon#read 6, iclass 32, count 2 2006.175.07:56:30.72#ibcon#end of sib2, iclass 32, count 2 2006.175.07:56:30.72#ibcon#*after write, iclass 32, count 2 2006.175.07:56:30.72#ibcon#*before return 0, iclass 32, count 2 2006.175.07:56:30.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:56:30.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.07:56:30.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.07:56:30.72#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:30.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:56:30.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:56:30.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:56:30.83#ibcon#enter wrdev, iclass 32, count 0 2006.175.07:56:30.83#ibcon#first serial, iclass 32, count 0 2006.175.07:56:30.83#ibcon#enter sib2, iclass 32, count 0 2006.175.07:56:30.83#ibcon#flushed, iclass 32, count 0 2006.175.07:56:30.83#ibcon#about to write, iclass 32, count 0 2006.175.07:56:30.83#ibcon#wrote, iclass 32, count 0 2006.175.07:56:30.83#ibcon#about to read 3, iclass 32, count 0 2006.175.07:56:30.85#ibcon#read 3, iclass 32, count 0 2006.175.07:56:30.85#ibcon#about to read 4, iclass 32, count 0 2006.175.07:56:30.85#ibcon#read 4, iclass 32, count 0 2006.175.07:56:30.85#ibcon#about to read 5, iclass 32, count 0 2006.175.07:56:30.85#ibcon#read 5, iclass 32, count 0 2006.175.07:56:30.85#ibcon#about to read 6, iclass 32, count 0 2006.175.07:56:30.85#ibcon#read 6, iclass 32, count 0 2006.175.07:56:30.85#ibcon#end of sib2, iclass 32, count 0 2006.175.07:56:30.85#ibcon#*mode == 0, iclass 32, count 0 2006.175.07:56:30.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.07:56:30.85#ibcon#[27=USB\r\n] 2006.175.07:56:30.85#ibcon#*before write, iclass 32, count 0 2006.175.07:56:30.85#ibcon#enter sib2, iclass 32, count 0 2006.175.07:56:30.85#ibcon#flushed, iclass 32, count 0 2006.175.07:56:30.85#ibcon#about to write, iclass 32, count 0 2006.175.07:56:30.86#ibcon#wrote, iclass 32, count 0 2006.175.07:56:30.86#ibcon#about to read 3, iclass 32, count 0 2006.175.07:56:30.88#ibcon#read 3, iclass 32, count 0 2006.175.07:56:30.88#ibcon#about to read 4, iclass 32, count 0 2006.175.07:56:30.88#ibcon#read 4, iclass 32, count 0 2006.175.07:56:30.88#ibcon#about to read 5, iclass 32, count 0 2006.175.07:56:30.88#ibcon#read 5, iclass 32, count 0 2006.175.07:56:30.88#ibcon#about to read 6, iclass 32, count 0 2006.175.07:56:30.88#ibcon#read 6, iclass 32, count 0 2006.175.07:56:30.88#ibcon#end of sib2, iclass 32, count 0 2006.175.07:56:30.88#ibcon#*after write, iclass 32, count 0 2006.175.07:56:30.88#ibcon#*before return 0, iclass 32, count 0 2006.175.07:56:30.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:56:30.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.07:56:30.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.07:56:30.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.07:56:30.89$vc4f8/vblo=2,640.99 2006.175.07:56:30.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.07:56:30.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.07:56:30.89#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:30.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:30.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:30.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:30.89#ibcon#enter wrdev, iclass 34, count 0 2006.175.07:56:30.89#ibcon#first serial, iclass 34, count 0 2006.175.07:56:30.89#ibcon#enter sib2, iclass 34, count 0 2006.175.07:56:30.89#ibcon#flushed, iclass 34, count 0 2006.175.07:56:30.89#ibcon#about to write, iclass 34, count 0 2006.175.07:56:30.89#ibcon#wrote, iclass 34, count 0 2006.175.07:56:30.89#ibcon#about to read 3, iclass 34, count 0 2006.175.07:56:30.90#ibcon#read 3, iclass 34, count 0 2006.175.07:56:30.90#ibcon#about to read 4, iclass 34, count 0 2006.175.07:56:30.90#ibcon#read 4, iclass 34, count 0 2006.175.07:56:30.90#ibcon#about to read 5, iclass 34, count 0 2006.175.07:56:30.90#ibcon#read 5, iclass 34, count 0 2006.175.07:56:30.90#ibcon#about to read 6, iclass 34, count 0 2006.175.07:56:30.90#ibcon#read 6, iclass 34, count 0 2006.175.07:56:30.90#ibcon#end of sib2, iclass 34, count 0 2006.175.07:56:30.90#ibcon#*mode == 0, iclass 34, count 0 2006.175.07:56:30.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.07:56:30.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.07:56:30.90#ibcon#*before write, iclass 34, count 0 2006.175.07:56:30.90#ibcon#enter sib2, iclass 34, count 0 2006.175.07:56:30.90#ibcon#flushed, iclass 34, count 0 2006.175.07:56:30.90#ibcon#about to write, iclass 34, count 0 2006.175.07:56:30.91#ibcon#wrote, iclass 34, count 0 2006.175.07:56:30.91#ibcon#about to read 3, iclass 34, count 0 2006.175.07:56:30.94#ibcon#read 3, iclass 34, count 0 2006.175.07:56:30.94#ibcon#about to read 4, iclass 34, count 0 2006.175.07:56:30.94#ibcon#read 4, iclass 34, count 0 2006.175.07:56:30.94#ibcon#about to read 5, iclass 34, count 0 2006.175.07:56:30.94#ibcon#read 5, iclass 34, count 0 2006.175.07:56:30.94#ibcon#about to read 6, iclass 34, count 0 2006.175.07:56:30.94#ibcon#read 6, iclass 34, count 0 2006.175.07:56:30.94#ibcon#end of sib2, iclass 34, count 0 2006.175.07:56:30.94#ibcon#*after write, iclass 34, count 0 2006.175.07:56:30.94#ibcon#*before return 0, iclass 34, count 0 2006.175.07:56:30.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:30.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.07:56:30.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.07:56:30.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.07:56:30.95$vc4f8/vb=2,4 2006.175.07:56:30.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.07:56:30.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.07:56:30.95#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:30.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:30.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:30.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:30.99#ibcon#enter wrdev, iclass 36, count 2 2006.175.07:56:30.99#ibcon#first serial, iclass 36, count 2 2006.175.07:56:30.99#ibcon#enter sib2, iclass 36, count 2 2006.175.07:56:30.99#ibcon#flushed, iclass 36, count 2 2006.175.07:56:30.99#ibcon#about to write, iclass 36, count 2 2006.175.07:56:30.99#ibcon#wrote, iclass 36, count 2 2006.175.07:56:30.99#ibcon#about to read 3, iclass 36, count 2 2006.175.07:56:31.01#ibcon#read 3, iclass 36, count 2 2006.175.07:56:31.01#ibcon#about to read 4, iclass 36, count 2 2006.175.07:56:31.01#ibcon#read 4, iclass 36, count 2 2006.175.07:56:31.01#ibcon#about to read 5, iclass 36, count 2 2006.175.07:56:31.01#ibcon#read 5, iclass 36, count 2 2006.175.07:56:31.01#ibcon#about to read 6, iclass 36, count 2 2006.175.07:56:31.01#ibcon#read 6, iclass 36, count 2 2006.175.07:56:31.01#ibcon#end of sib2, iclass 36, count 2 2006.175.07:56:31.01#ibcon#*mode == 0, iclass 36, count 2 2006.175.07:56:31.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.07:56:31.01#ibcon#[27=AT02-04\r\n] 2006.175.07:56:31.01#ibcon#*before write, iclass 36, count 2 2006.175.07:56:31.01#ibcon#enter sib2, iclass 36, count 2 2006.175.07:56:31.01#ibcon#flushed, iclass 36, count 2 2006.175.07:56:31.01#ibcon#about to write, iclass 36, count 2 2006.175.07:56:31.02#ibcon#wrote, iclass 36, count 2 2006.175.07:56:31.02#ibcon#about to read 3, iclass 36, count 2 2006.175.07:56:31.04#ibcon#read 3, iclass 36, count 2 2006.175.07:56:31.04#ibcon#about to read 4, iclass 36, count 2 2006.175.07:56:31.04#ibcon#read 4, iclass 36, count 2 2006.175.07:56:31.04#ibcon#about to read 5, iclass 36, count 2 2006.175.07:56:31.04#ibcon#read 5, iclass 36, count 2 2006.175.07:56:31.04#ibcon#about to read 6, iclass 36, count 2 2006.175.07:56:31.04#ibcon#read 6, iclass 36, count 2 2006.175.07:56:31.04#ibcon#end of sib2, iclass 36, count 2 2006.175.07:56:31.04#ibcon#*after write, iclass 36, count 2 2006.175.07:56:31.04#ibcon#*before return 0, iclass 36, count 2 2006.175.07:56:31.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:31.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.07:56:31.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.07:56:31.04#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:31.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:31.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:31.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:31.16#ibcon#enter wrdev, iclass 36, count 0 2006.175.07:56:31.16#ibcon#first serial, iclass 36, count 0 2006.175.07:56:31.16#ibcon#enter sib2, iclass 36, count 0 2006.175.07:56:31.16#ibcon#flushed, iclass 36, count 0 2006.175.07:56:31.16#ibcon#about to write, iclass 36, count 0 2006.175.07:56:31.16#ibcon#wrote, iclass 36, count 0 2006.175.07:56:31.16#ibcon#about to read 3, iclass 36, count 0 2006.175.07:56:31.18#ibcon#read 3, iclass 36, count 0 2006.175.07:56:31.18#ibcon#about to read 4, iclass 36, count 0 2006.175.07:56:31.18#ibcon#read 4, iclass 36, count 0 2006.175.07:56:31.18#ibcon#about to read 5, iclass 36, count 0 2006.175.07:56:31.18#ibcon#read 5, iclass 36, count 0 2006.175.07:56:31.18#ibcon#about to read 6, iclass 36, count 0 2006.175.07:56:31.18#ibcon#read 6, iclass 36, count 0 2006.175.07:56:31.18#ibcon#end of sib2, iclass 36, count 0 2006.175.07:56:31.18#ibcon#*mode == 0, iclass 36, count 0 2006.175.07:56:31.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.07:56:31.18#ibcon#[27=USB\r\n] 2006.175.07:56:31.18#ibcon#*before write, iclass 36, count 0 2006.175.07:56:31.18#ibcon#enter sib2, iclass 36, count 0 2006.175.07:56:31.18#ibcon#flushed, iclass 36, count 0 2006.175.07:56:31.19#ibcon#about to write, iclass 36, count 0 2006.175.07:56:31.19#ibcon#wrote, iclass 36, count 0 2006.175.07:56:31.19#ibcon#about to read 3, iclass 36, count 0 2006.175.07:56:31.21#ibcon#read 3, iclass 36, count 0 2006.175.07:56:31.21#ibcon#about to read 4, iclass 36, count 0 2006.175.07:56:31.21#ibcon#read 4, iclass 36, count 0 2006.175.07:56:31.21#ibcon#about to read 5, iclass 36, count 0 2006.175.07:56:31.21#ibcon#read 5, iclass 36, count 0 2006.175.07:56:31.21#ibcon#about to read 6, iclass 36, count 0 2006.175.07:56:31.21#ibcon#read 6, iclass 36, count 0 2006.175.07:56:31.21#ibcon#end of sib2, iclass 36, count 0 2006.175.07:56:31.21#ibcon#*after write, iclass 36, count 0 2006.175.07:56:31.21#ibcon#*before return 0, iclass 36, count 0 2006.175.07:56:31.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:31.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.07:56:31.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.07:56:31.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.07:56:31.22$vc4f8/vblo=3,656.99 2006.175.07:56:31.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.07:56:31.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.07:56:31.22#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:31.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:31.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:31.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:31.22#ibcon#enter wrdev, iclass 38, count 0 2006.175.07:56:31.22#ibcon#first serial, iclass 38, count 0 2006.175.07:56:31.22#ibcon#enter sib2, iclass 38, count 0 2006.175.07:56:31.22#ibcon#flushed, iclass 38, count 0 2006.175.07:56:31.22#ibcon#about to write, iclass 38, count 0 2006.175.07:56:31.22#ibcon#wrote, iclass 38, count 0 2006.175.07:56:31.22#ibcon#about to read 3, iclass 38, count 0 2006.175.07:56:31.23#ibcon#read 3, iclass 38, count 0 2006.175.07:56:31.23#ibcon#about to read 4, iclass 38, count 0 2006.175.07:56:31.23#ibcon#read 4, iclass 38, count 0 2006.175.07:56:31.23#ibcon#about to read 5, iclass 38, count 0 2006.175.07:56:31.23#ibcon#read 5, iclass 38, count 0 2006.175.07:56:31.23#ibcon#about to read 6, iclass 38, count 0 2006.175.07:56:31.23#ibcon#read 6, iclass 38, count 0 2006.175.07:56:31.23#ibcon#end of sib2, iclass 38, count 0 2006.175.07:56:31.23#ibcon#*mode == 0, iclass 38, count 0 2006.175.07:56:31.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.07:56:31.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.07:56:31.23#ibcon#*before write, iclass 38, count 0 2006.175.07:56:31.23#ibcon#enter sib2, iclass 38, count 0 2006.175.07:56:31.23#ibcon#flushed, iclass 38, count 0 2006.175.07:56:31.23#ibcon#about to write, iclass 38, count 0 2006.175.07:56:31.24#ibcon#wrote, iclass 38, count 0 2006.175.07:56:31.24#ibcon#about to read 3, iclass 38, count 0 2006.175.07:56:31.27#ibcon#read 3, iclass 38, count 0 2006.175.07:56:31.27#ibcon#about to read 4, iclass 38, count 0 2006.175.07:56:31.27#ibcon#read 4, iclass 38, count 0 2006.175.07:56:31.27#ibcon#about to read 5, iclass 38, count 0 2006.175.07:56:31.27#ibcon#read 5, iclass 38, count 0 2006.175.07:56:31.27#ibcon#about to read 6, iclass 38, count 0 2006.175.07:56:31.27#ibcon#read 6, iclass 38, count 0 2006.175.07:56:31.27#ibcon#end of sib2, iclass 38, count 0 2006.175.07:56:31.27#ibcon#*after write, iclass 38, count 0 2006.175.07:56:31.27#ibcon#*before return 0, iclass 38, count 0 2006.175.07:56:31.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:31.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.07:56:31.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.07:56:31.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.07:56:31.28$vc4f8/vb=3,4 2006.175.07:56:31.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.07:56:31.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.07:56:31.28#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:31.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:31.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:31.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:31.32#ibcon#enter wrdev, iclass 40, count 2 2006.175.07:56:31.32#ibcon#first serial, iclass 40, count 2 2006.175.07:56:31.32#ibcon#enter sib2, iclass 40, count 2 2006.175.07:56:31.32#ibcon#flushed, iclass 40, count 2 2006.175.07:56:31.32#ibcon#about to write, iclass 40, count 2 2006.175.07:56:31.32#ibcon#wrote, iclass 40, count 2 2006.175.07:56:31.32#ibcon#about to read 3, iclass 40, count 2 2006.175.07:56:31.34#ibcon#read 3, iclass 40, count 2 2006.175.07:56:31.34#ibcon#about to read 4, iclass 40, count 2 2006.175.07:56:31.34#ibcon#read 4, iclass 40, count 2 2006.175.07:56:31.34#ibcon#about to read 5, iclass 40, count 2 2006.175.07:56:31.34#ibcon#read 5, iclass 40, count 2 2006.175.07:56:31.34#ibcon#about to read 6, iclass 40, count 2 2006.175.07:56:31.34#ibcon#read 6, iclass 40, count 2 2006.175.07:56:31.34#ibcon#end of sib2, iclass 40, count 2 2006.175.07:56:31.34#ibcon#*mode == 0, iclass 40, count 2 2006.175.07:56:31.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.07:56:31.34#ibcon#[27=AT03-04\r\n] 2006.175.07:56:31.34#ibcon#*before write, iclass 40, count 2 2006.175.07:56:31.34#ibcon#enter sib2, iclass 40, count 2 2006.175.07:56:31.34#ibcon#flushed, iclass 40, count 2 2006.175.07:56:31.34#ibcon#about to write, iclass 40, count 2 2006.175.07:56:31.35#ibcon#wrote, iclass 40, count 2 2006.175.07:56:31.35#ibcon#about to read 3, iclass 40, count 2 2006.175.07:56:31.37#ibcon#read 3, iclass 40, count 2 2006.175.07:56:31.37#ibcon#about to read 4, iclass 40, count 2 2006.175.07:56:31.37#ibcon#read 4, iclass 40, count 2 2006.175.07:56:31.37#ibcon#about to read 5, iclass 40, count 2 2006.175.07:56:31.37#ibcon#read 5, iclass 40, count 2 2006.175.07:56:31.37#ibcon#about to read 6, iclass 40, count 2 2006.175.07:56:31.37#ibcon#read 6, iclass 40, count 2 2006.175.07:56:31.37#ibcon#end of sib2, iclass 40, count 2 2006.175.07:56:31.37#ibcon#*after write, iclass 40, count 2 2006.175.07:56:31.37#ibcon#*before return 0, iclass 40, count 2 2006.175.07:56:31.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:31.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.07:56:31.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.07:56:31.37#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:31.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:31.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:31.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:31.49#ibcon#enter wrdev, iclass 40, count 0 2006.175.07:56:31.49#ibcon#first serial, iclass 40, count 0 2006.175.07:56:31.49#ibcon#enter sib2, iclass 40, count 0 2006.175.07:56:31.49#ibcon#flushed, iclass 40, count 0 2006.175.07:56:31.49#ibcon#about to write, iclass 40, count 0 2006.175.07:56:31.49#ibcon#wrote, iclass 40, count 0 2006.175.07:56:31.49#ibcon#about to read 3, iclass 40, count 0 2006.175.07:56:31.51#ibcon#read 3, iclass 40, count 0 2006.175.07:56:31.51#ibcon#about to read 4, iclass 40, count 0 2006.175.07:56:31.51#ibcon#read 4, iclass 40, count 0 2006.175.07:56:31.51#ibcon#about to read 5, iclass 40, count 0 2006.175.07:56:31.51#ibcon#read 5, iclass 40, count 0 2006.175.07:56:31.51#ibcon#about to read 6, iclass 40, count 0 2006.175.07:56:31.51#ibcon#read 6, iclass 40, count 0 2006.175.07:56:31.51#ibcon#end of sib2, iclass 40, count 0 2006.175.07:56:31.51#ibcon#*mode == 0, iclass 40, count 0 2006.175.07:56:31.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.07:56:31.51#ibcon#[27=USB\r\n] 2006.175.07:56:31.51#ibcon#*before write, iclass 40, count 0 2006.175.07:56:31.51#ibcon#enter sib2, iclass 40, count 0 2006.175.07:56:31.51#ibcon#flushed, iclass 40, count 0 2006.175.07:56:31.51#ibcon#about to write, iclass 40, count 0 2006.175.07:56:31.52#ibcon#wrote, iclass 40, count 0 2006.175.07:56:31.52#ibcon#about to read 3, iclass 40, count 0 2006.175.07:56:31.54#ibcon#read 3, iclass 40, count 0 2006.175.07:56:31.54#ibcon#about to read 4, iclass 40, count 0 2006.175.07:56:31.54#ibcon#read 4, iclass 40, count 0 2006.175.07:56:31.54#ibcon#about to read 5, iclass 40, count 0 2006.175.07:56:31.54#ibcon#read 5, iclass 40, count 0 2006.175.07:56:31.54#ibcon#about to read 6, iclass 40, count 0 2006.175.07:56:31.54#ibcon#read 6, iclass 40, count 0 2006.175.07:56:31.54#ibcon#end of sib2, iclass 40, count 0 2006.175.07:56:31.54#ibcon#*after write, iclass 40, count 0 2006.175.07:56:31.54#ibcon#*before return 0, iclass 40, count 0 2006.175.07:56:31.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:31.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.07:56:31.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.07:56:31.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.07:56:31.55$vc4f8/vblo=4,712.99 2006.175.07:56:31.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.07:56:31.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.07:56:31.55#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:31.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:31.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:31.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:31.55#ibcon#enter wrdev, iclass 4, count 0 2006.175.07:56:31.55#ibcon#first serial, iclass 4, count 0 2006.175.07:56:31.55#ibcon#enter sib2, iclass 4, count 0 2006.175.07:56:31.55#ibcon#flushed, iclass 4, count 0 2006.175.07:56:31.55#ibcon#about to write, iclass 4, count 0 2006.175.07:56:31.55#ibcon#wrote, iclass 4, count 0 2006.175.07:56:31.55#ibcon#about to read 3, iclass 4, count 0 2006.175.07:56:31.56#ibcon#read 3, iclass 4, count 0 2006.175.07:56:31.56#ibcon#about to read 4, iclass 4, count 0 2006.175.07:56:31.56#ibcon#read 4, iclass 4, count 0 2006.175.07:56:31.56#ibcon#about to read 5, iclass 4, count 0 2006.175.07:56:31.56#ibcon#read 5, iclass 4, count 0 2006.175.07:56:31.56#ibcon#about to read 6, iclass 4, count 0 2006.175.07:56:31.56#ibcon#read 6, iclass 4, count 0 2006.175.07:56:31.56#ibcon#end of sib2, iclass 4, count 0 2006.175.07:56:31.56#ibcon#*mode == 0, iclass 4, count 0 2006.175.07:56:31.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.07:56:31.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.07:56:31.56#ibcon#*before write, iclass 4, count 0 2006.175.07:56:31.56#ibcon#enter sib2, iclass 4, count 0 2006.175.07:56:31.56#ibcon#flushed, iclass 4, count 0 2006.175.07:56:31.56#ibcon#about to write, iclass 4, count 0 2006.175.07:56:31.57#ibcon#wrote, iclass 4, count 0 2006.175.07:56:31.57#ibcon#about to read 3, iclass 4, count 0 2006.175.07:56:31.60#ibcon#read 3, iclass 4, count 0 2006.175.07:56:31.60#ibcon#about to read 4, iclass 4, count 0 2006.175.07:56:31.60#ibcon#read 4, iclass 4, count 0 2006.175.07:56:31.60#ibcon#about to read 5, iclass 4, count 0 2006.175.07:56:31.60#ibcon#read 5, iclass 4, count 0 2006.175.07:56:31.60#ibcon#about to read 6, iclass 4, count 0 2006.175.07:56:31.60#ibcon#read 6, iclass 4, count 0 2006.175.07:56:31.60#ibcon#end of sib2, iclass 4, count 0 2006.175.07:56:31.60#ibcon#*after write, iclass 4, count 0 2006.175.07:56:31.60#ibcon#*before return 0, iclass 4, count 0 2006.175.07:56:31.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:31.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.07:56:31.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.07:56:31.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.07:56:31.61$vc4f8/vb=4,4 2006.175.07:56:31.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.07:56:31.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.07:56:31.61#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:31.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:31.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:31.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:31.65#ibcon#enter wrdev, iclass 6, count 2 2006.175.07:56:31.65#ibcon#first serial, iclass 6, count 2 2006.175.07:56:31.65#ibcon#enter sib2, iclass 6, count 2 2006.175.07:56:31.65#ibcon#flushed, iclass 6, count 2 2006.175.07:56:31.65#ibcon#about to write, iclass 6, count 2 2006.175.07:56:31.65#ibcon#wrote, iclass 6, count 2 2006.175.07:56:31.65#ibcon#about to read 3, iclass 6, count 2 2006.175.07:56:31.67#ibcon#read 3, iclass 6, count 2 2006.175.07:56:31.67#ibcon#about to read 4, iclass 6, count 2 2006.175.07:56:31.67#ibcon#read 4, iclass 6, count 2 2006.175.07:56:31.67#ibcon#about to read 5, iclass 6, count 2 2006.175.07:56:31.67#ibcon#read 5, iclass 6, count 2 2006.175.07:56:31.67#ibcon#about to read 6, iclass 6, count 2 2006.175.07:56:31.67#ibcon#read 6, iclass 6, count 2 2006.175.07:56:31.67#ibcon#end of sib2, iclass 6, count 2 2006.175.07:56:31.67#ibcon#*mode == 0, iclass 6, count 2 2006.175.07:56:31.67#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.07:56:31.67#ibcon#[27=AT04-04\r\n] 2006.175.07:56:31.67#ibcon#*before write, iclass 6, count 2 2006.175.07:56:31.67#ibcon#enter sib2, iclass 6, count 2 2006.175.07:56:31.67#ibcon#flushed, iclass 6, count 2 2006.175.07:56:31.67#ibcon#about to write, iclass 6, count 2 2006.175.07:56:31.68#ibcon#wrote, iclass 6, count 2 2006.175.07:56:31.68#ibcon#about to read 3, iclass 6, count 2 2006.175.07:56:31.70#ibcon#read 3, iclass 6, count 2 2006.175.07:56:31.70#ibcon#about to read 4, iclass 6, count 2 2006.175.07:56:31.70#ibcon#read 4, iclass 6, count 2 2006.175.07:56:31.70#ibcon#about to read 5, iclass 6, count 2 2006.175.07:56:31.70#ibcon#read 5, iclass 6, count 2 2006.175.07:56:31.70#ibcon#about to read 6, iclass 6, count 2 2006.175.07:56:31.70#ibcon#read 6, iclass 6, count 2 2006.175.07:56:31.70#ibcon#end of sib2, iclass 6, count 2 2006.175.07:56:31.70#ibcon#*after write, iclass 6, count 2 2006.175.07:56:31.70#ibcon#*before return 0, iclass 6, count 2 2006.175.07:56:31.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:31.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.07:56:31.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.07:56:31.70#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:31.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:31.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:31.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:31.81#ibcon#enter wrdev, iclass 6, count 0 2006.175.07:56:31.81#ibcon#first serial, iclass 6, count 0 2006.175.07:56:31.81#ibcon#enter sib2, iclass 6, count 0 2006.175.07:56:31.81#ibcon#flushed, iclass 6, count 0 2006.175.07:56:31.81#ibcon#about to write, iclass 6, count 0 2006.175.07:56:31.81#ibcon#wrote, iclass 6, count 0 2006.175.07:56:31.81#ibcon#about to read 3, iclass 6, count 0 2006.175.07:56:31.83#ibcon#read 3, iclass 6, count 0 2006.175.07:56:31.83#ibcon#about to read 4, iclass 6, count 0 2006.175.07:56:31.83#ibcon#read 4, iclass 6, count 0 2006.175.07:56:31.83#ibcon#about to read 5, iclass 6, count 0 2006.175.07:56:31.83#ibcon#read 5, iclass 6, count 0 2006.175.07:56:31.83#ibcon#about to read 6, iclass 6, count 0 2006.175.07:56:31.83#ibcon#read 6, iclass 6, count 0 2006.175.07:56:31.83#ibcon#end of sib2, iclass 6, count 0 2006.175.07:56:31.83#ibcon#*mode == 0, iclass 6, count 0 2006.175.07:56:31.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.07:56:31.83#ibcon#[27=USB\r\n] 2006.175.07:56:31.83#ibcon#*before write, iclass 6, count 0 2006.175.07:56:31.83#ibcon#enter sib2, iclass 6, count 0 2006.175.07:56:31.84#ibcon#flushed, iclass 6, count 0 2006.175.07:56:31.84#ibcon#about to write, iclass 6, count 0 2006.175.07:56:31.84#ibcon#wrote, iclass 6, count 0 2006.175.07:56:31.84#ibcon#about to read 3, iclass 6, count 0 2006.175.07:56:31.86#ibcon#read 3, iclass 6, count 0 2006.175.07:56:31.86#ibcon#about to read 4, iclass 6, count 0 2006.175.07:56:31.86#ibcon#read 4, iclass 6, count 0 2006.175.07:56:31.86#ibcon#about to read 5, iclass 6, count 0 2006.175.07:56:31.86#ibcon#read 5, iclass 6, count 0 2006.175.07:56:31.86#ibcon#about to read 6, iclass 6, count 0 2006.175.07:56:31.86#ibcon#read 6, iclass 6, count 0 2006.175.07:56:31.86#ibcon#end of sib2, iclass 6, count 0 2006.175.07:56:31.86#ibcon#*after write, iclass 6, count 0 2006.175.07:56:31.86#ibcon#*before return 0, iclass 6, count 0 2006.175.07:56:31.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:31.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.07:56:31.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.07:56:31.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.07:56:31.87$vc4f8/vblo=5,744.99 2006.175.07:56:31.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.07:56:31.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.07:56:31.87#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:31.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:31.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:31.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:31.87#ibcon#enter wrdev, iclass 10, count 0 2006.175.07:56:31.87#ibcon#first serial, iclass 10, count 0 2006.175.07:56:31.87#ibcon#enter sib2, iclass 10, count 0 2006.175.07:56:31.87#ibcon#flushed, iclass 10, count 0 2006.175.07:56:31.87#ibcon#about to write, iclass 10, count 0 2006.175.07:56:31.87#ibcon#wrote, iclass 10, count 0 2006.175.07:56:31.87#ibcon#about to read 3, iclass 10, count 0 2006.175.07:56:31.88#ibcon#read 3, iclass 10, count 0 2006.175.07:56:31.88#ibcon#about to read 4, iclass 10, count 0 2006.175.07:56:31.88#ibcon#read 4, iclass 10, count 0 2006.175.07:56:31.88#ibcon#about to read 5, iclass 10, count 0 2006.175.07:56:31.88#ibcon#read 5, iclass 10, count 0 2006.175.07:56:31.88#ibcon#about to read 6, iclass 10, count 0 2006.175.07:56:31.88#ibcon#read 6, iclass 10, count 0 2006.175.07:56:31.88#ibcon#end of sib2, iclass 10, count 0 2006.175.07:56:31.88#ibcon#*mode == 0, iclass 10, count 0 2006.175.07:56:31.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.07:56:31.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.07:56:31.88#ibcon#*before write, iclass 10, count 0 2006.175.07:56:31.88#ibcon#enter sib2, iclass 10, count 0 2006.175.07:56:31.88#ibcon#flushed, iclass 10, count 0 2006.175.07:56:31.88#ibcon#about to write, iclass 10, count 0 2006.175.07:56:31.89#ibcon#wrote, iclass 10, count 0 2006.175.07:56:31.89#ibcon#about to read 3, iclass 10, count 0 2006.175.07:56:31.92#ibcon#read 3, iclass 10, count 0 2006.175.07:56:31.92#ibcon#about to read 4, iclass 10, count 0 2006.175.07:56:31.92#ibcon#read 4, iclass 10, count 0 2006.175.07:56:31.92#ibcon#about to read 5, iclass 10, count 0 2006.175.07:56:31.92#ibcon#read 5, iclass 10, count 0 2006.175.07:56:31.92#ibcon#about to read 6, iclass 10, count 0 2006.175.07:56:31.92#ibcon#read 6, iclass 10, count 0 2006.175.07:56:31.92#ibcon#end of sib2, iclass 10, count 0 2006.175.07:56:31.92#ibcon#*after write, iclass 10, count 0 2006.175.07:56:31.92#ibcon#*before return 0, iclass 10, count 0 2006.175.07:56:31.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:31.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.07:56:31.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.07:56:31.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.07:56:31.93$vc4f8/vb=5,4 2006.175.07:56:31.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.07:56:31.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.07:56:31.93#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:31.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:31.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:31.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:31.98#ibcon#enter wrdev, iclass 12, count 2 2006.175.07:56:31.98#ibcon#first serial, iclass 12, count 2 2006.175.07:56:31.98#ibcon#enter sib2, iclass 12, count 2 2006.175.07:56:31.98#ibcon#flushed, iclass 12, count 2 2006.175.07:56:31.98#ibcon#about to write, iclass 12, count 2 2006.175.07:56:31.98#ibcon#wrote, iclass 12, count 2 2006.175.07:56:31.98#ibcon#about to read 3, iclass 12, count 2 2006.175.07:56:31.99#ibcon#read 3, iclass 12, count 2 2006.175.07:56:31.99#ibcon#about to read 4, iclass 12, count 2 2006.175.07:56:31.99#ibcon#read 4, iclass 12, count 2 2006.175.07:56:31.99#ibcon#about to read 5, iclass 12, count 2 2006.175.07:56:31.99#ibcon#read 5, iclass 12, count 2 2006.175.07:56:31.99#ibcon#about to read 6, iclass 12, count 2 2006.175.07:56:31.99#ibcon#read 6, iclass 12, count 2 2006.175.07:56:31.99#ibcon#end of sib2, iclass 12, count 2 2006.175.07:56:31.99#ibcon#*mode == 0, iclass 12, count 2 2006.175.07:56:31.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.07:56:31.99#ibcon#[27=AT05-04\r\n] 2006.175.07:56:31.99#ibcon#*before write, iclass 12, count 2 2006.175.07:56:31.99#ibcon#enter sib2, iclass 12, count 2 2006.175.07:56:31.99#ibcon#flushed, iclass 12, count 2 2006.175.07:56:31.99#ibcon#about to write, iclass 12, count 2 2006.175.07:56:32.00#ibcon#wrote, iclass 12, count 2 2006.175.07:56:32.00#ibcon#about to read 3, iclass 12, count 2 2006.175.07:56:32.02#ibcon#read 3, iclass 12, count 2 2006.175.07:56:32.02#ibcon#about to read 4, iclass 12, count 2 2006.175.07:56:32.02#ibcon#read 4, iclass 12, count 2 2006.175.07:56:32.02#ibcon#about to read 5, iclass 12, count 2 2006.175.07:56:32.02#ibcon#read 5, iclass 12, count 2 2006.175.07:56:32.02#ibcon#about to read 6, iclass 12, count 2 2006.175.07:56:32.02#ibcon#read 6, iclass 12, count 2 2006.175.07:56:32.02#ibcon#end of sib2, iclass 12, count 2 2006.175.07:56:32.02#ibcon#*after write, iclass 12, count 2 2006.175.07:56:32.02#ibcon#*before return 0, iclass 12, count 2 2006.175.07:56:32.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:32.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.07:56:32.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.07:56:32.02#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:32.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:32.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:32.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:32.15#ibcon#enter wrdev, iclass 12, count 0 2006.175.07:56:32.15#ibcon#first serial, iclass 12, count 0 2006.175.07:56:32.15#ibcon#enter sib2, iclass 12, count 0 2006.175.07:56:32.15#ibcon#flushed, iclass 12, count 0 2006.175.07:56:32.15#ibcon#about to write, iclass 12, count 0 2006.175.07:56:32.15#ibcon#wrote, iclass 12, count 0 2006.175.07:56:32.15#ibcon#about to read 3, iclass 12, count 0 2006.175.07:56:32.16#ibcon#read 3, iclass 12, count 0 2006.175.07:56:32.16#ibcon#about to read 4, iclass 12, count 0 2006.175.07:56:32.16#ibcon#read 4, iclass 12, count 0 2006.175.07:56:32.16#ibcon#about to read 5, iclass 12, count 0 2006.175.07:56:32.16#ibcon#read 5, iclass 12, count 0 2006.175.07:56:32.16#ibcon#about to read 6, iclass 12, count 0 2006.175.07:56:32.16#ibcon#read 6, iclass 12, count 0 2006.175.07:56:32.16#ibcon#end of sib2, iclass 12, count 0 2006.175.07:56:32.16#ibcon#*mode == 0, iclass 12, count 0 2006.175.07:56:32.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.07:56:32.16#ibcon#[27=USB\r\n] 2006.175.07:56:32.16#ibcon#*before write, iclass 12, count 0 2006.175.07:56:32.16#ibcon#enter sib2, iclass 12, count 0 2006.175.07:56:32.16#ibcon#flushed, iclass 12, count 0 2006.175.07:56:32.16#ibcon#about to write, iclass 12, count 0 2006.175.07:56:32.17#ibcon#wrote, iclass 12, count 0 2006.175.07:56:32.17#ibcon#about to read 3, iclass 12, count 0 2006.175.07:56:32.19#ibcon#read 3, iclass 12, count 0 2006.175.07:56:32.19#ibcon#about to read 4, iclass 12, count 0 2006.175.07:56:32.19#ibcon#read 4, iclass 12, count 0 2006.175.07:56:32.19#ibcon#about to read 5, iclass 12, count 0 2006.175.07:56:32.19#ibcon#read 5, iclass 12, count 0 2006.175.07:56:32.19#ibcon#about to read 6, iclass 12, count 0 2006.175.07:56:32.19#ibcon#read 6, iclass 12, count 0 2006.175.07:56:32.19#ibcon#end of sib2, iclass 12, count 0 2006.175.07:56:32.19#ibcon#*after write, iclass 12, count 0 2006.175.07:56:32.19#ibcon#*before return 0, iclass 12, count 0 2006.175.07:56:32.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:32.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.07:56:32.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.07:56:32.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.07:56:32.20$vc4f8/vblo=6,752.99 2006.175.07:56:32.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.07:56:32.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.07:56:32.20#ibcon#ireg 17 cls_cnt 0 2006.175.07:56:32.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:32.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:32.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:32.20#ibcon#enter wrdev, iclass 14, count 0 2006.175.07:56:32.20#ibcon#first serial, iclass 14, count 0 2006.175.07:56:32.20#ibcon#enter sib2, iclass 14, count 0 2006.175.07:56:32.20#ibcon#flushed, iclass 14, count 0 2006.175.07:56:32.20#ibcon#about to write, iclass 14, count 0 2006.175.07:56:32.20#ibcon#wrote, iclass 14, count 0 2006.175.07:56:32.20#ibcon#about to read 3, iclass 14, count 0 2006.175.07:56:32.21#ibcon#read 3, iclass 14, count 0 2006.175.07:56:32.21#ibcon#about to read 4, iclass 14, count 0 2006.175.07:56:32.21#ibcon#read 4, iclass 14, count 0 2006.175.07:56:32.21#ibcon#about to read 5, iclass 14, count 0 2006.175.07:56:32.21#ibcon#read 5, iclass 14, count 0 2006.175.07:56:32.21#ibcon#about to read 6, iclass 14, count 0 2006.175.07:56:32.21#ibcon#read 6, iclass 14, count 0 2006.175.07:56:32.21#ibcon#end of sib2, iclass 14, count 0 2006.175.07:56:32.21#ibcon#*mode == 0, iclass 14, count 0 2006.175.07:56:32.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.07:56:32.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.07:56:32.21#ibcon#*before write, iclass 14, count 0 2006.175.07:56:32.21#ibcon#enter sib2, iclass 14, count 0 2006.175.07:56:32.21#ibcon#flushed, iclass 14, count 0 2006.175.07:56:32.21#ibcon#about to write, iclass 14, count 0 2006.175.07:56:32.22#ibcon#wrote, iclass 14, count 0 2006.175.07:56:32.22#ibcon#about to read 3, iclass 14, count 0 2006.175.07:56:32.26#ibcon#read 3, iclass 14, count 0 2006.175.07:56:32.26#ibcon#about to read 4, iclass 14, count 0 2006.175.07:56:32.26#ibcon#read 4, iclass 14, count 0 2006.175.07:56:32.26#ibcon#about to read 5, iclass 14, count 0 2006.175.07:56:32.26#ibcon#read 5, iclass 14, count 0 2006.175.07:56:32.26#ibcon#about to read 6, iclass 14, count 0 2006.175.07:56:32.26#ibcon#read 6, iclass 14, count 0 2006.175.07:56:32.26#ibcon#end of sib2, iclass 14, count 0 2006.175.07:56:32.26#ibcon#*after write, iclass 14, count 0 2006.175.07:56:32.26#ibcon#*before return 0, iclass 14, count 0 2006.175.07:56:32.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:32.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.07:56:32.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.07:56:32.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.07:56:32.26$vc4f8/vb=6,4 2006.175.07:56:32.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.07:56:32.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.07:56:32.26#ibcon#ireg 11 cls_cnt 2 2006.175.07:56:32.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:32.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:32.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:32.30#ibcon#enter wrdev, iclass 16, count 2 2006.175.07:56:32.30#ibcon#first serial, iclass 16, count 2 2006.175.07:56:32.30#ibcon#enter sib2, iclass 16, count 2 2006.175.07:56:32.30#ibcon#flushed, iclass 16, count 2 2006.175.07:56:32.30#ibcon#about to write, iclass 16, count 2 2006.175.07:56:32.30#ibcon#wrote, iclass 16, count 2 2006.175.07:56:32.30#ibcon#about to read 3, iclass 16, count 2 2006.175.07:56:32.32#ibcon#read 3, iclass 16, count 2 2006.175.07:56:32.32#ibcon#about to read 4, iclass 16, count 2 2006.175.07:56:32.32#ibcon#read 4, iclass 16, count 2 2006.175.07:56:32.32#ibcon#about to read 5, iclass 16, count 2 2006.175.07:56:32.32#ibcon#read 5, iclass 16, count 2 2006.175.07:56:32.32#ibcon#about to read 6, iclass 16, count 2 2006.175.07:56:32.32#ibcon#read 6, iclass 16, count 2 2006.175.07:56:32.32#ibcon#end of sib2, iclass 16, count 2 2006.175.07:56:32.32#ibcon#*mode == 0, iclass 16, count 2 2006.175.07:56:32.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.07:56:32.32#ibcon#[27=AT06-04\r\n] 2006.175.07:56:32.32#ibcon#*before write, iclass 16, count 2 2006.175.07:56:32.33#ibcon#enter sib2, iclass 16, count 2 2006.175.07:56:32.33#ibcon#flushed, iclass 16, count 2 2006.175.07:56:32.33#ibcon#about to write, iclass 16, count 2 2006.175.07:56:32.33#ibcon#wrote, iclass 16, count 2 2006.175.07:56:32.33#ibcon#about to read 3, iclass 16, count 2 2006.175.07:56:32.35#ibcon#read 3, iclass 16, count 2 2006.175.07:56:32.35#ibcon#about to read 4, iclass 16, count 2 2006.175.07:56:32.35#ibcon#read 4, iclass 16, count 2 2006.175.07:56:32.35#ibcon#about to read 5, iclass 16, count 2 2006.175.07:56:32.35#ibcon#read 5, iclass 16, count 2 2006.175.07:56:32.35#ibcon#about to read 6, iclass 16, count 2 2006.175.07:56:32.35#ibcon#read 6, iclass 16, count 2 2006.175.07:56:32.35#ibcon#end of sib2, iclass 16, count 2 2006.175.07:56:32.35#ibcon#*after write, iclass 16, count 2 2006.175.07:56:32.35#ibcon#*before return 0, iclass 16, count 2 2006.175.07:56:32.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:32.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.07:56:32.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.07:56:32.35#ibcon#ireg 7 cls_cnt 0 2006.175.07:56:32.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:32.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:32.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:32.47#ibcon#enter wrdev, iclass 16, count 0 2006.175.07:56:32.47#ibcon#first serial, iclass 16, count 0 2006.175.07:56:32.47#ibcon#enter sib2, iclass 16, count 0 2006.175.07:56:32.47#ibcon#flushed, iclass 16, count 0 2006.175.07:56:32.47#ibcon#about to write, iclass 16, count 0 2006.175.07:56:32.47#ibcon#wrote, iclass 16, count 0 2006.175.07:56:32.47#ibcon#about to read 3, iclass 16, count 0 2006.175.07:56:32.49#ibcon#read 3, iclass 16, count 0 2006.175.07:56:32.49#ibcon#about to read 4, iclass 16, count 0 2006.175.07:56:32.49#ibcon#read 4, iclass 16, count 0 2006.175.07:56:32.49#ibcon#about to read 5, iclass 16, count 0 2006.175.07:56:32.49#ibcon#read 5, iclass 16, count 0 2006.175.07:56:32.49#ibcon#about to read 6, iclass 16, count 0 2006.175.07:56:32.49#ibcon#read 6, iclass 16, count 0 2006.175.07:56:32.49#ibcon#end of sib2, iclass 16, count 0 2006.175.07:56:32.49#ibcon#*mode == 0, iclass 16, count 0 2006.175.07:56:32.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.07:56:32.49#ibcon#[27=USB\r\n] 2006.175.07:56:32.49#ibcon#*before write, iclass 16, count 0 2006.175.07:56:32.49#ibcon#enter sib2, iclass 16, count 0 2006.175.07:56:32.49#ibcon#flushed, iclass 16, count 0 2006.175.07:56:32.49#ibcon#about to write, iclass 16, count 0 2006.175.07:56:32.50#ibcon#wrote, iclass 16, count 0 2006.175.07:56:32.50#ibcon#about to read 3, iclass 16, count 0 2006.175.07:56:32.52#ibcon#read 3, iclass 16, count 0 2006.175.07:56:32.52#ibcon#about to read 4, iclass 16, count 0 2006.175.07:56:32.52#ibcon#read 4, iclass 16, count 0 2006.175.07:56:32.52#ibcon#about to read 5, iclass 16, count 0 2006.175.07:56:32.52#ibcon#read 5, iclass 16, count 0 2006.175.07:56:32.52#ibcon#about to read 6, iclass 16, count 0 2006.175.07:56:32.52#ibcon#read 6, iclass 16, count 0 2006.175.07:56:32.52#ibcon#end of sib2, iclass 16, count 0 2006.175.07:56:32.52#ibcon#*after write, iclass 16, count 0 2006.175.07:56:32.52#ibcon#*before return 0, iclass 16, count 0 2006.175.07:56:32.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:32.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.07:56:32.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.07:56:32.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.07:56:32.53$vc4f8/vabw=wide 2006.175.07:56:32.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.07:56:32.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.07:56:32.53#ibcon#ireg 8 cls_cnt 0 2006.175.07:56:32.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:32.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:32.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:32.53#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:56:32.53#ibcon#first serial, iclass 18, count 0 2006.175.07:56:32.53#ibcon#enter sib2, iclass 18, count 0 2006.175.07:56:32.53#ibcon#flushed, iclass 18, count 0 2006.175.07:56:32.53#ibcon#about to write, iclass 18, count 0 2006.175.07:56:32.53#ibcon#wrote, iclass 18, count 0 2006.175.07:56:32.53#ibcon#about to read 3, iclass 18, count 0 2006.175.07:56:32.54#ibcon#read 3, iclass 18, count 0 2006.175.07:56:32.54#ibcon#about to read 4, iclass 18, count 0 2006.175.07:56:32.54#ibcon#read 4, iclass 18, count 0 2006.175.07:56:32.54#ibcon#about to read 5, iclass 18, count 0 2006.175.07:56:32.54#ibcon#read 5, iclass 18, count 0 2006.175.07:56:32.54#ibcon#about to read 6, iclass 18, count 0 2006.175.07:56:32.54#ibcon#read 6, iclass 18, count 0 2006.175.07:56:32.54#ibcon#end of sib2, iclass 18, count 0 2006.175.07:56:32.54#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:56:32.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:56:32.54#ibcon#[25=BW32\r\n] 2006.175.07:56:32.54#ibcon#*before write, iclass 18, count 0 2006.175.07:56:32.54#ibcon#enter sib2, iclass 18, count 0 2006.175.07:56:32.54#ibcon#flushed, iclass 18, count 0 2006.175.07:56:32.54#ibcon#about to write, iclass 18, count 0 2006.175.07:56:32.55#ibcon#wrote, iclass 18, count 0 2006.175.07:56:32.55#ibcon#about to read 3, iclass 18, count 0 2006.175.07:56:32.57#ibcon#read 3, iclass 18, count 0 2006.175.07:56:32.57#ibcon#about to read 4, iclass 18, count 0 2006.175.07:56:32.57#ibcon#read 4, iclass 18, count 0 2006.175.07:56:32.57#ibcon#about to read 5, iclass 18, count 0 2006.175.07:56:32.57#ibcon#read 5, iclass 18, count 0 2006.175.07:56:32.57#ibcon#about to read 6, iclass 18, count 0 2006.175.07:56:32.57#ibcon#read 6, iclass 18, count 0 2006.175.07:56:32.57#ibcon#end of sib2, iclass 18, count 0 2006.175.07:56:32.57#ibcon#*after write, iclass 18, count 0 2006.175.07:56:32.57#ibcon#*before return 0, iclass 18, count 0 2006.175.07:56:32.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:32.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.07:56:32.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:56:32.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:56:32.58$vc4f8/vbbw=wide 2006.175.07:56:32.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.07:56:32.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.07:56:32.58#ibcon#ireg 8 cls_cnt 0 2006.175.07:56:32.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:56:32.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:56:32.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:56:32.63#ibcon#enter wrdev, iclass 20, count 0 2006.175.07:56:32.63#ibcon#first serial, iclass 20, count 0 2006.175.07:56:32.63#ibcon#enter sib2, iclass 20, count 0 2006.175.07:56:32.63#ibcon#flushed, iclass 20, count 0 2006.175.07:56:32.63#ibcon#about to write, iclass 20, count 0 2006.175.07:56:32.63#ibcon#wrote, iclass 20, count 0 2006.175.07:56:32.63#ibcon#about to read 3, iclass 20, count 0 2006.175.07:56:32.65#ibcon#read 3, iclass 20, count 0 2006.175.07:56:32.65#ibcon#about to read 4, iclass 20, count 0 2006.175.07:56:32.65#ibcon#read 4, iclass 20, count 0 2006.175.07:56:32.65#ibcon#about to read 5, iclass 20, count 0 2006.175.07:56:32.65#ibcon#read 5, iclass 20, count 0 2006.175.07:56:32.65#ibcon#about to read 6, iclass 20, count 0 2006.175.07:56:32.65#ibcon#read 6, iclass 20, count 0 2006.175.07:56:32.65#ibcon#end of sib2, iclass 20, count 0 2006.175.07:56:32.65#ibcon#*mode == 0, iclass 20, count 0 2006.175.07:56:32.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.07:56:32.65#ibcon#[27=BW32\r\n] 2006.175.07:56:32.65#ibcon#*before write, iclass 20, count 0 2006.175.07:56:32.65#ibcon#enter sib2, iclass 20, count 0 2006.175.07:56:32.65#ibcon#flushed, iclass 20, count 0 2006.175.07:56:32.65#ibcon#about to write, iclass 20, count 0 2006.175.07:56:32.66#ibcon#wrote, iclass 20, count 0 2006.175.07:56:32.66#ibcon#about to read 3, iclass 20, count 0 2006.175.07:56:32.68#ibcon#read 3, iclass 20, count 0 2006.175.07:56:32.68#ibcon#about to read 4, iclass 20, count 0 2006.175.07:56:32.68#ibcon#read 4, iclass 20, count 0 2006.175.07:56:32.68#ibcon#about to read 5, iclass 20, count 0 2006.175.07:56:32.68#ibcon#read 5, iclass 20, count 0 2006.175.07:56:32.68#ibcon#about to read 6, iclass 20, count 0 2006.175.07:56:32.68#ibcon#read 6, iclass 20, count 0 2006.175.07:56:32.68#ibcon#end of sib2, iclass 20, count 0 2006.175.07:56:32.68#ibcon#*after write, iclass 20, count 0 2006.175.07:56:32.68#ibcon#*before return 0, iclass 20, count 0 2006.175.07:56:32.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:56:32.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.07:56:32.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.07:56:32.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.07:56:32.69$4f8m12a/ifd4f 2006.175.07:56:32.69$ifd4f/lo= 2006.175.07:56:32.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.07:56:32.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.07:56:32.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.07:56:32.69$ifd4f/patch= 2006.175.07:56:32.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.07:56:32.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.07:56:32.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.07:56:32.69$4f8m12a/"form=m,16.000,1:2 2006.175.07:56:32.69$4f8m12a/"tpicd 2006.175.07:56:32.69$4f8m12a/echo=off 2006.175.07:56:32.69$4f8m12a/xlog=off 2006.175.07:56:32.69:!2006.175.07:58:40 2006.175.07:56:53.14#trakl#Source acquired 2006.175.07:56:54.15#flagr#flagr/antenna,acquired 2006.175.07:58:40.01:preob 2006.175.07:58:41.13/onsource/TRACKING 2006.175.07:58:41.14:!2006.175.07:58:50 2006.175.07:58:50.01:data_valid=on 2006.175.07:58:50.02:midob 2006.175.07:58:51.13/onsource/TRACKING 2006.175.07:58:51.14/wx/25.85,1007.4,69 2006.175.07:58:51.21/cable/+6.4755E-03 2006.175.07:58:52.30/va/01,08,usb,yes,28,30 2006.175.07:58:52.30/va/02,07,usb,yes,28,30 2006.175.07:58:52.30/va/03,06,usb,yes,30,30 2006.175.07:58:52.30/va/04,07,usb,yes,29,31 2006.175.07:58:52.30/va/05,07,usb,yes,30,31 2006.175.07:58:52.30/va/06,06,usb,yes,29,29 2006.175.07:58:52.30/va/07,06,usb,yes,29,29 2006.175.07:58:52.30/va/08,06,usb,yes,31,31 2006.175.07:58:52.53/valo/01,532.99,yes,locked 2006.175.07:58:52.53/valo/02,572.99,yes,locked 2006.175.07:58:52.53/valo/03,672.99,yes,locked 2006.175.07:58:52.53/valo/04,832.99,yes,locked 2006.175.07:58:52.53/valo/05,652.99,yes,locked 2006.175.07:58:52.53/valo/06,772.99,yes,locked 2006.175.07:58:52.53/valo/07,832.99,yes,locked 2006.175.07:58:52.53/valo/08,852.99,yes,locked 2006.175.07:58:53.62/vb/01,04,usb,yes,29,27 2006.175.07:58:53.62/vb/02,04,usb,yes,31,32 2006.175.07:58:53.62/vb/03,04,usb,yes,27,31 2006.175.07:58:53.62/vb/04,04,usb,yes,28,28 2006.175.07:58:53.62/vb/05,04,usb,yes,26,30 2006.175.07:58:53.62/vb/06,04,usb,yes,27,30 2006.175.07:58:53.62/vb/07,04,usb,yes,29,29 2006.175.07:58:53.62/vb/08,04,usb,yes,27,30 2006.175.07:58:53.85/vblo/01,632.99,yes,locked 2006.175.07:58:53.85/vblo/02,640.99,yes,locked 2006.175.07:58:53.85/vblo/03,656.99,yes,locked 2006.175.07:58:53.85/vblo/04,712.99,yes,locked 2006.175.07:58:53.85/vblo/05,744.99,yes,locked 2006.175.07:58:53.85/vblo/06,752.99,yes,locked 2006.175.07:58:53.85/vblo/07,734.99,yes,locked 2006.175.07:58:53.85/vblo/08,744.99,yes,locked 2006.175.07:58:54.00/vabw/8 2006.175.07:58:54.15/vbbw/8 2006.175.07:58:54.24/xfe/off,on,14.5 2006.175.07:58:54.62/ifatt/23,28,28,28 2006.175.07:58:55.07/fmout-gps/S +3.73E-07 2006.175.07:58:55.12:!2006.175.07:59:50 2006.175.07:59:50.01:data_valid=off 2006.175.07:59:50.02:postob 2006.175.07:59:50.10/cable/+6.4764E-03 2006.175.07:59:50.11/wx/25.86,1007.4,70 2006.175.07:59:51.07/fmout-gps/S +3.73E-07 2006.175.07:59:51.08:scan_name=175-0801,k06175,60 2006.175.07:59:51.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.175.07:59:52.13#flagr#flagr/antenna,new-source 2006.175.07:59:52.14:checkk5 2006.175.07:59:52.55/chk_autoobs//k5ts1/ autoobs is running! 2006.175.07:59:52.93/chk_autoobs//k5ts2/ autoobs is running! 2006.175.07:59:53.31/chk_autoobs//k5ts3/ autoobs is running! 2006.175.07:59:53.69/chk_autoobs//k5ts4/ autoobs is running! 2006.175.07:59:54.06/chk_obsdata//k5ts1/T1750758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:59:54.43/chk_obsdata//k5ts2/T1750758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:59:54.80/chk_obsdata//k5ts3/T1750758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:59:55.18/chk_obsdata//k5ts4/T1750758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.07:59:55.86/k5log//k5ts1_log_newline 2006.175.07:59:56.56/k5log//k5ts2_log_newline 2006.175.07:59:57.27/k5log//k5ts3_log_newline 2006.175.07:59:57.96/k5log//k5ts4_log_newline 2006.175.07:59:57.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.07:59:57.99:4f8m12a=2 2006.175.07:59:57.99$4f8m12a/echo=on 2006.175.07:59:57.99$4f8m12a/pcalon 2006.175.07:59:57.99$pcalon/"no phase cal control is implemented here 2006.175.07:59:57.99$4f8m12a/"tpicd=stop 2006.175.07:59:57.99$4f8m12a/vc4f8 2006.175.07:59:57.99$vc4f8/valo=1,532.99 2006.175.07:59:57.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.07:59:57.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.07:59:57.99#ibcon#ireg 17 cls_cnt 0 2006.175.07:59:57.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:59:57.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:59:57.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:59:57.99#ibcon#enter wrdev, iclass 31, count 0 2006.175.07:59:57.99#ibcon#first serial, iclass 31, count 0 2006.175.07:59:57.99#ibcon#enter sib2, iclass 31, count 0 2006.175.07:59:57.99#ibcon#flushed, iclass 31, count 0 2006.175.07:59:57.99#ibcon#about to write, iclass 31, count 0 2006.175.07:59:57.99#ibcon#wrote, iclass 31, count 0 2006.175.07:59:57.99#ibcon#about to read 3, iclass 31, count 0 2006.175.07:59:58.03#ibcon#read 3, iclass 31, count 0 2006.175.07:59:58.03#ibcon#about to read 4, iclass 31, count 0 2006.175.07:59:58.03#ibcon#read 4, iclass 31, count 0 2006.175.07:59:58.03#ibcon#about to read 5, iclass 31, count 0 2006.175.07:59:58.03#ibcon#read 5, iclass 31, count 0 2006.175.07:59:58.03#ibcon#about to read 6, iclass 31, count 0 2006.175.07:59:58.03#ibcon#read 6, iclass 31, count 0 2006.175.07:59:58.03#ibcon#end of sib2, iclass 31, count 0 2006.175.07:59:58.03#ibcon#*mode == 0, iclass 31, count 0 2006.175.07:59:58.03#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.07:59:58.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.07:59:58.03#ibcon#*before write, iclass 31, count 0 2006.175.07:59:58.03#ibcon#enter sib2, iclass 31, count 0 2006.175.07:59:58.03#ibcon#flushed, iclass 31, count 0 2006.175.07:59:58.03#ibcon#about to write, iclass 31, count 0 2006.175.07:59:58.03#ibcon#wrote, iclass 31, count 0 2006.175.07:59:58.03#ibcon#about to read 3, iclass 31, count 0 2006.175.07:59:58.08#ibcon#read 3, iclass 31, count 0 2006.175.07:59:58.08#ibcon#about to read 4, iclass 31, count 0 2006.175.07:59:58.08#ibcon#read 4, iclass 31, count 0 2006.175.07:59:58.08#ibcon#about to read 5, iclass 31, count 0 2006.175.07:59:58.08#ibcon#read 5, iclass 31, count 0 2006.175.07:59:58.08#ibcon#about to read 6, iclass 31, count 0 2006.175.07:59:58.08#ibcon#read 6, iclass 31, count 0 2006.175.07:59:58.08#ibcon#end of sib2, iclass 31, count 0 2006.175.07:59:58.08#ibcon#*after write, iclass 31, count 0 2006.175.07:59:58.08#ibcon#*before return 0, iclass 31, count 0 2006.175.07:59:58.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:59:58.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.07:59:58.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.07:59:58.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.07:59:58.08$vc4f8/va=1,8 2006.175.07:59:58.08#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.07:59:58.08#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.07:59:58.08#ibcon#ireg 11 cls_cnt 2 2006.175.07:59:58.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:59:58.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:59:58.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:59:58.08#ibcon#enter wrdev, iclass 33, count 2 2006.175.07:59:58.08#ibcon#first serial, iclass 33, count 2 2006.175.07:59:58.08#ibcon#enter sib2, iclass 33, count 2 2006.175.07:59:58.08#ibcon#flushed, iclass 33, count 2 2006.175.07:59:58.08#ibcon#about to write, iclass 33, count 2 2006.175.07:59:58.08#ibcon#wrote, iclass 33, count 2 2006.175.07:59:58.08#ibcon#about to read 3, iclass 33, count 2 2006.175.07:59:58.10#ibcon#read 3, iclass 33, count 2 2006.175.07:59:58.10#ibcon#about to read 4, iclass 33, count 2 2006.175.07:59:58.10#ibcon#read 4, iclass 33, count 2 2006.175.07:59:58.10#ibcon#about to read 5, iclass 33, count 2 2006.175.07:59:58.10#ibcon#read 5, iclass 33, count 2 2006.175.07:59:58.10#ibcon#about to read 6, iclass 33, count 2 2006.175.07:59:58.10#ibcon#read 6, iclass 33, count 2 2006.175.07:59:58.10#ibcon#end of sib2, iclass 33, count 2 2006.175.07:59:58.10#ibcon#*mode == 0, iclass 33, count 2 2006.175.07:59:58.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.07:59:58.10#ibcon#[25=AT01-08\r\n] 2006.175.07:59:58.10#ibcon#*before write, iclass 33, count 2 2006.175.07:59:58.10#ibcon#enter sib2, iclass 33, count 2 2006.175.07:59:58.10#ibcon#flushed, iclass 33, count 2 2006.175.07:59:58.10#ibcon#about to write, iclass 33, count 2 2006.175.07:59:58.10#ibcon#wrote, iclass 33, count 2 2006.175.07:59:58.10#ibcon#about to read 3, iclass 33, count 2 2006.175.07:59:58.13#ibcon#read 3, iclass 33, count 2 2006.175.07:59:58.13#ibcon#about to read 4, iclass 33, count 2 2006.175.07:59:58.13#ibcon#read 4, iclass 33, count 2 2006.175.07:59:58.13#ibcon#about to read 5, iclass 33, count 2 2006.175.07:59:58.13#ibcon#read 5, iclass 33, count 2 2006.175.07:59:58.13#ibcon#about to read 6, iclass 33, count 2 2006.175.07:59:58.13#ibcon#read 6, iclass 33, count 2 2006.175.07:59:58.13#ibcon#end of sib2, iclass 33, count 2 2006.175.07:59:58.13#ibcon#*after write, iclass 33, count 2 2006.175.07:59:58.13#ibcon#*before return 0, iclass 33, count 2 2006.175.07:59:58.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:59:58.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.07:59:58.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.07:59:58.13#ibcon#ireg 7 cls_cnt 0 2006.175.07:59:58.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:59:58.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:59:58.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:59:58.25#ibcon#enter wrdev, iclass 33, count 0 2006.175.07:59:58.25#ibcon#first serial, iclass 33, count 0 2006.175.07:59:58.25#ibcon#enter sib2, iclass 33, count 0 2006.175.07:59:58.25#ibcon#flushed, iclass 33, count 0 2006.175.07:59:58.25#ibcon#about to write, iclass 33, count 0 2006.175.07:59:58.25#ibcon#wrote, iclass 33, count 0 2006.175.07:59:58.25#ibcon#about to read 3, iclass 33, count 0 2006.175.07:59:58.27#ibcon#read 3, iclass 33, count 0 2006.175.07:59:58.27#ibcon#about to read 4, iclass 33, count 0 2006.175.07:59:58.27#ibcon#read 4, iclass 33, count 0 2006.175.07:59:58.27#ibcon#about to read 5, iclass 33, count 0 2006.175.07:59:58.27#ibcon#read 5, iclass 33, count 0 2006.175.07:59:58.27#ibcon#about to read 6, iclass 33, count 0 2006.175.07:59:58.27#ibcon#read 6, iclass 33, count 0 2006.175.07:59:58.27#ibcon#end of sib2, iclass 33, count 0 2006.175.07:59:58.27#ibcon#*mode == 0, iclass 33, count 0 2006.175.07:59:58.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.07:59:58.27#ibcon#[25=USB\r\n] 2006.175.07:59:58.27#ibcon#*before write, iclass 33, count 0 2006.175.07:59:58.27#ibcon#enter sib2, iclass 33, count 0 2006.175.07:59:58.27#ibcon#flushed, iclass 33, count 0 2006.175.07:59:58.27#ibcon#about to write, iclass 33, count 0 2006.175.07:59:58.27#ibcon#wrote, iclass 33, count 0 2006.175.07:59:58.27#ibcon#about to read 3, iclass 33, count 0 2006.175.07:59:58.30#ibcon#read 3, iclass 33, count 0 2006.175.07:59:58.30#ibcon#about to read 4, iclass 33, count 0 2006.175.07:59:58.30#ibcon#read 4, iclass 33, count 0 2006.175.07:59:58.30#ibcon#about to read 5, iclass 33, count 0 2006.175.07:59:58.30#ibcon#read 5, iclass 33, count 0 2006.175.07:59:58.30#ibcon#about to read 6, iclass 33, count 0 2006.175.07:59:58.30#ibcon#read 6, iclass 33, count 0 2006.175.07:59:58.30#ibcon#end of sib2, iclass 33, count 0 2006.175.07:59:58.30#ibcon#*after write, iclass 33, count 0 2006.175.07:59:58.30#ibcon#*before return 0, iclass 33, count 0 2006.175.07:59:58.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:59:58.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.07:59:58.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.07:59:58.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.07:59:58.30$vc4f8/valo=2,572.99 2006.175.07:59:58.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.07:59:58.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.07:59:58.30#ibcon#ireg 17 cls_cnt 0 2006.175.07:59:58.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:59:58.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:59:58.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:59:58.30#ibcon#enter wrdev, iclass 35, count 0 2006.175.07:59:58.30#ibcon#first serial, iclass 35, count 0 2006.175.07:59:58.30#ibcon#enter sib2, iclass 35, count 0 2006.175.07:59:58.30#ibcon#flushed, iclass 35, count 0 2006.175.07:59:58.30#ibcon#about to write, iclass 35, count 0 2006.175.07:59:58.30#ibcon#wrote, iclass 35, count 0 2006.175.07:59:58.30#ibcon#about to read 3, iclass 35, count 0 2006.175.07:59:58.32#ibcon#read 3, iclass 35, count 0 2006.175.07:59:58.32#ibcon#about to read 4, iclass 35, count 0 2006.175.07:59:58.32#ibcon#read 4, iclass 35, count 0 2006.175.07:59:58.32#ibcon#about to read 5, iclass 35, count 0 2006.175.07:59:58.32#ibcon#read 5, iclass 35, count 0 2006.175.07:59:58.32#ibcon#about to read 6, iclass 35, count 0 2006.175.07:59:58.32#ibcon#read 6, iclass 35, count 0 2006.175.07:59:58.32#ibcon#end of sib2, iclass 35, count 0 2006.175.07:59:58.32#ibcon#*mode == 0, iclass 35, count 0 2006.175.07:59:58.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.07:59:58.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.07:59:58.32#ibcon#*before write, iclass 35, count 0 2006.175.07:59:58.32#ibcon#enter sib2, iclass 35, count 0 2006.175.07:59:58.32#ibcon#flushed, iclass 35, count 0 2006.175.07:59:58.32#ibcon#about to write, iclass 35, count 0 2006.175.07:59:58.32#ibcon#wrote, iclass 35, count 0 2006.175.07:59:58.32#ibcon#about to read 3, iclass 35, count 0 2006.175.07:59:58.36#ibcon#read 3, iclass 35, count 0 2006.175.07:59:58.36#ibcon#about to read 4, iclass 35, count 0 2006.175.07:59:58.36#ibcon#read 4, iclass 35, count 0 2006.175.07:59:58.36#ibcon#about to read 5, iclass 35, count 0 2006.175.07:59:58.36#ibcon#read 5, iclass 35, count 0 2006.175.07:59:58.36#ibcon#about to read 6, iclass 35, count 0 2006.175.07:59:58.36#ibcon#read 6, iclass 35, count 0 2006.175.07:59:58.36#ibcon#end of sib2, iclass 35, count 0 2006.175.07:59:58.36#ibcon#*after write, iclass 35, count 0 2006.175.07:59:58.36#ibcon#*before return 0, iclass 35, count 0 2006.175.07:59:58.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:59:58.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.07:59:58.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.07:59:58.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.07:59:58.37$vc4f8/va=2,7 2006.175.07:59:58.37#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.07:59:58.37#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.07:59:58.37#ibcon#ireg 11 cls_cnt 2 2006.175.07:59:58.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:59:58.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:59:58.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:59:58.41#ibcon#enter wrdev, iclass 37, count 2 2006.175.07:59:58.41#ibcon#first serial, iclass 37, count 2 2006.175.07:59:58.41#ibcon#enter sib2, iclass 37, count 2 2006.175.07:59:58.41#ibcon#flushed, iclass 37, count 2 2006.175.07:59:58.41#ibcon#about to write, iclass 37, count 2 2006.175.07:59:58.41#ibcon#wrote, iclass 37, count 2 2006.175.07:59:58.41#ibcon#about to read 3, iclass 37, count 2 2006.175.07:59:58.43#ibcon#read 3, iclass 37, count 2 2006.175.07:59:58.43#ibcon#about to read 4, iclass 37, count 2 2006.175.07:59:58.43#ibcon#read 4, iclass 37, count 2 2006.175.07:59:58.43#ibcon#about to read 5, iclass 37, count 2 2006.175.07:59:58.43#ibcon#read 5, iclass 37, count 2 2006.175.07:59:58.43#ibcon#about to read 6, iclass 37, count 2 2006.175.07:59:58.43#ibcon#read 6, iclass 37, count 2 2006.175.07:59:58.43#ibcon#end of sib2, iclass 37, count 2 2006.175.07:59:58.43#ibcon#*mode == 0, iclass 37, count 2 2006.175.07:59:58.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.07:59:58.43#ibcon#[25=AT02-07\r\n] 2006.175.07:59:58.43#ibcon#*before write, iclass 37, count 2 2006.175.07:59:58.43#ibcon#enter sib2, iclass 37, count 2 2006.175.07:59:58.43#ibcon#flushed, iclass 37, count 2 2006.175.07:59:58.43#ibcon#about to write, iclass 37, count 2 2006.175.07:59:58.43#ibcon#wrote, iclass 37, count 2 2006.175.07:59:58.43#ibcon#about to read 3, iclass 37, count 2 2006.175.07:59:58.46#ibcon#read 3, iclass 37, count 2 2006.175.07:59:58.46#ibcon#about to read 4, iclass 37, count 2 2006.175.07:59:58.46#ibcon#read 4, iclass 37, count 2 2006.175.07:59:58.46#ibcon#about to read 5, iclass 37, count 2 2006.175.07:59:58.46#ibcon#read 5, iclass 37, count 2 2006.175.07:59:58.46#ibcon#about to read 6, iclass 37, count 2 2006.175.07:59:58.46#ibcon#read 6, iclass 37, count 2 2006.175.07:59:58.46#ibcon#end of sib2, iclass 37, count 2 2006.175.07:59:58.46#ibcon#*after write, iclass 37, count 2 2006.175.07:59:58.46#ibcon#*before return 0, iclass 37, count 2 2006.175.07:59:58.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:59:58.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.07:59:58.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.07:59:58.46#ibcon#ireg 7 cls_cnt 0 2006.175.07:59:58.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:59:58.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:59:58.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:59:58.58#ibcon#enter wrdev, iclass 37, count 0 2006.175.07:59:58.58#ibcon#first serial, iclass 37, count 0 2006.175.07:59:58.58#ibcon#enter sib2, iclass 37, count 0 2006.175.07:59:58.58#ibcon#flushed, iclass 37, count 0 2006.175.07:59:58.58#ibcon#about to write, iclass 37, count 0 2006.175.07:59:58.58#ibcon#wrote, iclass 37, count 0 2006.175.07:59:58.58#ibcon#about to read 3, iclass 37, count 0 2006.175.07:59:58.60#ibcon#read 3, iclass 37, count 0 2006.175.07:59:58.60#ibcon#about to read 4, iclass 37, count 0 2006.175.07:59:58.60#ibcon#read 4, iclass 37, count 0 2006.175.07:59:58.60#ibcon#about to read 5, iclass 37, count 0 2006.175.07:59:58.60#ibcon#read 5, iclass 37, count 0 2006.175.07:59:58.60#ibcon#about to read 6, iclass 37, count 0 2006.175.07:59:58.60#ibcon#read 6, iclass 37, count 0 2006.175.07:59:58.60#ibcon#end of sib2, iclass 37, count 0 2006.175.07:59:58.60#ibcon#*mode == 0, iclass 37, count 0 2006.175.07:59:58.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.07:59:58.60#ibcon#[25=USB\r\n] 2006.175.07:59:58.60#ibcon#*before write, iclass 37, count 0 2006.175.07:59:58.60#ibcon#enter sib2, iclass 37, count 0 2006.175.07:59:58.60#ibcon#flushed, iclass 37, count 0 2006.175.07:59:58.60#ibcon#about to write, iclass 37, count 0 2006.175.07:59:58.60#ibcon#wrote, iclass 37, count 0 2006.175.07:59:58.60#ibcon#about to read 3, iclass 37, count 0 2006.175.07:59:58.63#ibcon#read 3, iclass 37, count 0 2006.175.07:59:58.63#ibcon#about to read 4, iclass 37, count 0 2006.175.07:59:58.63#ibcon#read 4, iclass 37, count 0 2006.175.07:59:58.63#ibcon#about to read 5, iclass 37, count 0 2006.175.07:59:58.63#ibcon#read 5, iclass 37, count 0 2006.175.07:59:58.63#ibcon#about to read 6, iclass 37, count 0 2006.175.07:59:58.63#ibcon#read 6, iclass 37, count 0 2006.175.07:59:58.63#ibcon#end of sib2, iclass 37, count 0 2006.175.07:59:58.63#ibcon#*after write, iclass 37, count 0 2006.175.07:59:58.63#ibcon#*before return 0, iclass 37, count 0 2006.175.07:59:58.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:59:58.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.07:59:58.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.07:59:58.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.07:59:58.63$vc4f8/valo=3,672.99 2006.175.07:59:58.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.07:59:58.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.07:59:58.63#ibcon#ireg 17 cls_cnt 0 2006.175.07:59:58.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:59:58.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:59:58.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:59:58.63#ibcon#enter wrdev, iclass 39, count 0 2006.175.07:59:58.63#ibcon#first serial, iclass 39, count 0 2006.175.07:59:58.63#ibcon#enter sib2, iclass 39, count 0 2006.175.07:59:58.63#ibcon#flushed, iclass 39, count 0 2006.175.07:59:58.63#ibcon#about to write, iclass 39, count 0 2006.175.07:59:58.63#ibcon#wrote, iclass 39, count 0 2006.175.07:59:58.63#ibcon#about to read 3, iclass 39, count 0 2006.175.07:59:58.65#ibcon#read 3, iclass 39, count 0 2006.175.07:59:58.65#ibcon#about to read 4, iclass 39, count 0 2006.175.07:59:58.65#ibcon#read 4, iclass 39, count 0 2006.175.07:59:58.65#ibcon#about to read 5, iclass 39, count 0 2006.175.07:59:58.65#ibcon#read 5, iclass 39, count 0 2006.175.07:59:58.65#ibcon#about to read 6, iclass 39, count 0 2006.175.07:59:58.65#ibcon#read 6, iclass 39, count 0 2006.175.07:59:58.65#ibcon#end of sib2, iclass 39, count 0 2006.175.07:59:58.65#ibcon#*mode == 0, iclass 39, count 0 2006.175.07:59:58.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.07:59:58.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.07:59:58.65#ibcon#*before write, iclass 39, count 0 2006.175.07:59:58.65#ibcon#enter sib2, iclass 39, count 0 2006.175.07:59:58.65#ibcon#flushed, iclass 39, count 0 2006.175.07:59:58.65#ibcon#about to write, iclass 39, count 0 2006.175.07:59:58.65#ibcon#wrote, iclass 39, count 0 2006.175.07:59:58.65#ibcon#about to read 3, iclass 39, count 0 2006.175.07:59:58.69#ibcon#read 3, iclass 39, count 0 2006.175.07:59:58.69#ibcon#about to read 4, iclass 39, count 0 2006.175.07:59:58.69#ibcon#read 4, iclass 39, count 0 2006.175.07:59:58.69#ibcon#about to read 5, iclass 39, count 0 2006.175.07:59:58.69#ibcon#read 5, iclass 39, count 0 2006.175.07:59:58.70#ibcon#about to read 6, iclass 39, count 0 2006.175.07:59:58.70#ibcon#read 6, iclass 39, count 0 2006.175.07:59:58.70#ibcon#end of sib2, iclass 39, count 0 2006.175.07:59:58.70#ibcon#*after write, iclass 39, count 0 2006.175.07:59:58.70#ibcon#*before return 0, iclass 39, count 0 2006.175.07:59:58.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:59:58.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.07:59:58.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.07:59:58.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.07:59:58.70$vc4f8/va=3,6 2006.175.07:59:58.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.07:59:58.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.07:59:58.70#ibcon#ireg 11 cls_cnt 2 2006.175.07:59:58.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:59:58.74#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:59:58.74#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:59:58.74#ibcon#enter wrdev, iclass 3, count 2 2006.175.07:59:58.74#ibcon#first serial, iclass 3, count 2 2006.175.07:59:58.74#ibcon#enter sib2, iclass 3, count 2 2006.175.07:59:58.74#ibcon#flushed, iclass 3, count 2 2006.175.07:59:58.74#ibcon#about to write, iclass 3, count 2 2006.175.07:59:58.74#ibcon#wrote, iclass 3, count 2 2006.175.07:59:58.74#ibcon#about to read 3, iclass 3, count 2 2006.175.07:59:58.76#ibcon#read 3, iclass 3, count 2 2006.175.07:59:58.76#ibcon#about to read 4, iclass 3, count 2 2006.175.07:59:58.76#ibcon#read 4, iclass 3, count 2 2006.175.07:59:58.76#ibcon#about to read 5, iclass 3, count 2 2006.175.07:59:58.76#ibcon#read 5, iclass 3, count 2 2006.175.07:59:58.76#ibcon#about to read 6, iclass 3, count 2 2006.175.07:59:58.76#ibcon#read 6, iclass 3, count 2 2006.175.07:59:58.76#ibcon#end of sib2, iclass 3, count 2 2006.175.07:59:58.76#ibcon#*mode == 0, iclass 3, count 2 2006.175.07:59:58.76#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.07:59:58.76#ibcon#[25=AT03-06\r\n] 2006.175.07:59:58.76#ibcon#*before write, iclass 3, count 2 2006.175.07:59:58.76#ibcon#enter sib2, iclass 3, count 2 2006.175.07:59:58.76#ibcon#flushed, iclass 3, count 2 2006.175.07:59:58.76#ibcon#about to write, iclass 3, count 2 2006.175.07:59:58.76#ibcon#wrote, iclass 3, count 2 2006.175.07:59:58.76#ibcon#about to read 3, iclass 3, count 2 2006.175.07:59:58.79#ibcon#read 3, iclass 3, count 2 2006.175.07:59:58.79#ibcon#about to read 4, iclass 3, count 2 2006.175.07:59:58.79#ibcon#read 4, iclass 3, count 2 2006.175.07:59:58.79#ibcon#about to read 5, iclass 3, count 2 2006.175.07:59:58.79#ibcon#read 5, iclass 3, count 2 2006.175.07:59:58.79#ibcon#about to read 6, iclass 3, count 2 2006.175.07:59:58.79#ibcon#read 6, iclass 3, count 2 2006.175.07:59:58.79#ibcon#end of sib2, iclass 3, count 2 2006.175.07:59:58.79#ibcon#*after write, iclass 3, count 2 2006.175.07:59:58.79#ibcon#*before return 0, iclass 3, count 2 2006.175.07:59:58.79#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:59:58.79#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.07:59:58.79#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.07:59:58.79#ibcon#ireg 7 cls_cnt 0 2006.175.07:59:58.79#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:59:58.91#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:59:58.91#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:59:58.91#ibcon#enter wrdev, iclass 3, count 0 2006.175.07:59:58.91#ibcon#first serial, iclass 3, count 0 2006.175.07:59:58.91#ibcon#enter sib2, iclass 3, count 0 2006.175.07:59:58.91#ibcon#flushed, iclass 3, count 0 2006.175.07:59:58.91#ibcon#about to write, iclass 3, count 0 2006.175.07:59:58.91#ibcon#wrote, iclass 3, count 0 2006.175.07:59:58.91#ibcon#about to read 3, iclass 3, count 0 2006.175.07:59:58.93#ibcon#read 3, iclass 3, count 0 2006.175.07:59:58.93#ibcon#about to read 4, iclass 3, count 0 2006.175.07:59:58.93#ibcon#read 4, iclass 3, count 0 2006.175.07:59:58.93#ibcon#about to read 5, iclass 3, count 0 2006.175.07:59:58.93#ibcon#read 5, iclass 3, count 0 2006.175.07:59:58.93#ibcon#about to read 6, iclass 3, count 0 2006.175.07:59:58.93#ibcon#read 6, iclass 3, count 0 2006.175.07:59:58.93#ibcon#end of sib2, iclass 3, count 0 2006.175.07:59:58.93#ibcon#*mode == 0, iclass 3, count 0 2006.175.07:59:58.93#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.07:59:58.93#ibcon#[25=USB\r\n] 2006.175.07:59:58.93#ibcon#*before write, iclass 3, count 0 2006.175.07:59:58.93#ibcon#enter sib2, iclass 3, count 0 2006.175.07:59:58.93#ibcon#flushed, iclass 3, count 0 2006.175.07:59:58.93#ibcon#about to write, iclass 3, count 0 2006.175.07:59:58.93#ibcon#wrote, iclass 3, count 0 2006.175.07:59:58.93#ibcon#about to read 3, iclass 3, count 0 2006.175.07:59:58.96#ibcon#read 3, iclass 3, count 0 2006.175.07:59:58.96#ibcon#about to read 4, iclass 3, count 0 2006.175.07:59:58.96#ibcon#read 4, iclass 3, count 0 2006.175.07:59:58.96#ibcon#about to read 5, iclass 3, count 0 2006.175.07:59:58.96#ibcon#read 5, iclass 3, count 0 2006.175.07:59:58.96#ibcon#about to read 6, iclass 3, count 0 2006.175.07:59:58.96#ibcon#read 6, iclass 3, count 0 2006.175.07:59:58.96#ibcon#end of sib2, iclass 3, count 0 2006.175.07:59:58.96#ibcon#*after write, iclass 3, count 0 2006.175.07:59:58.96#ibcon#*before return 0, iclass 3, count 0 2006.175.07:59:58.96#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:59:58.96#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.07:59:58.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.07:59:58.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.07:59:58.96$vc4f8/valo=4,832.99 2006.175.07:59:58.96#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.07:59:58.96#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.07:59:58.96#ibcon#ireg 17 cls_cnt 0 2006.175.07:59:58.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:59:58.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:59:58.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:59:58.96#ibcon#enter wrdev, iclass 5, count 0 2006.175.07:59:58.96#ibcon#first serial, iclass 5, count 0 2006.175.07:59:58.96#ibcon#enter sib2, iclass 5, count 0 2006.175.07:59:58.96#ibcon#flushed, iclass 5, count 0 2006.175.07:59:58.96#ibcon#about to write, iclass 5, count 0 2006.175.07:59:58.96#ibcon#wrote, iclass 5, count 0 2006.175.07:59:58.96#ibcon#about to read 3, iclass 5, count 0 2006.175.07:59:58.98#ibcon#read 3, iclass 5, count 0 2006.175.07:59:58.98#ibcon#about to read 4, iclass 5, count 0 2006.175.07:59:58.98#ibcon#read 4, iclass 5, count 0 2006.175.07:59:58.98#ibcon#about to read 5, iclass 5, count 0 2006.175.07:59:58.98#ibcon#read 5, iclass 5, count 0 2006.175.07:59:58.98#ibcon#about to read 6, iclass 5, count 0 2006.175.07:59:58.98#ibcon#read 6, iclass 5, count 0 2006.175.07:59:58.98#ibcon#end of sib2, iclass 5, count 0 2006.175.07:59:58.98#ibcon#*mode == 0, iclass 5, count 0 2006.175.07:59:58.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.07:59:58.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.07:59:58.98#ibcon#*before write, iclass 5, count 0 2006.175.07:59:58.98#ibcon#enter sib2, iclass 5, count 0 2006.175.07:59:58.98#ibcon#flushed, iclass 5, count 0 2006.175.07:59:58.98#ibcon#about to write, iclass 5, count 0 2006.175.07:59:58.98#ibcon#wrote, iclass 5, count 0 2006.175.07:59:58.98#ibcon#about to read 3, iclass 5, count 0 2006.175.07:59:59.02#ibcon#read 3, iclass 5, count 0 2006.175.07:59:59.02#ibcon#about to read 4, iclass 5, count 0 2006.175.07:59:59.02#ibcon#read 4, iclass 5, count 0 2006.175.07:59:59.02#ibcon#about to read 5, iclass 5, count 0 2006.175.07:59:59.02#ibcon#read 5, iclass 5, count 0 2006.175.07:59:59.02#ibcon#about to read 6, iclass 5, count 0 2006.175.07:59:59.02#ibcon#read 6, iclass 5, count 0 2006.175.07:59:59.02#ibcon#end of sib2, iclass 5, count 0 2006.175.07:59:59.02#ibcon#*after write, iclass 5, count 0 2006.175.07:59:59.02#ibcon#*before return 0, iclass 5, count 0 2006.175.07:59:59.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:59:59.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.07:59:59.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.07:59:59.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.07:59:59.02$vc4f8/va=4,7 2006.175.07:59:59.02#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.07:59:59.02#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.07:59:59.02#ibcon#ireg 11 cls_cnt 2 2006.175.07:59:59.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:59:59.08#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:59:59.08#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:59:59.08#ibcon#enter wrdev, iclass 7, count 2 2006.175.07:59:59.08#ibcon#first serial, iclass 7, count 2 2006.175.07:59:59.08#ibcon#enter sib2, iclass 7, count 2 2006.175.07:59:59.08#ibcon#flushed, iclass 7, count 2 2006.175.07:59:59.08#ibcon#about to write, iclass 7, count 2 2006.175.07:59:59.08#ibcon#wrote, iclass 7, count 2 2006.175.07:59:59.08#ibcon#about to read 3, iclass 7, count 2 2006.175.07:59:59.10#ibcon#read 3, iclass 7, count 2 2006.175.07:59:59.10#ibcon#about to read 4, iclass 7, count 2 2006.175.07:59:59.10#ibcon#read 4, iclass 7, count 2 2006.175.07:59:59.10#ibcon#about to read 5, iclass 7, count 2 2006.175.07:59:59.10#ibcon#read 5, iclass 7, count 2 2006.175.07:59:59.10#ibcon#about to read 6, iclass 7, count 2 2006.175.07:59:59.10#ibcon#read 6, iclass 7, count 2 2006.175.07:59:59.10#ibcon#end of sib2, iclass 7, count 2 2006.175.07:59:59.10#ibcon#*mode == 0, iclass 7, count 2 2006.175.07:59:59.10#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.07:59:59.10#ibcon#[25=AT04-07\r\n] 2006.175.07:59:59.10#ibcon#*before write, iclass 7, count 2 2006.175.07:59:59.10#ibcon#enter sib2, iclass 7, count 2 2006.175.07:59:59.10#ibcon#flushed, iclass 7, count 2 2006.175.07:59:59.10#ibcon#about to write, iclass 7, count 2 2006.175.07:59:59.10#ibcon#wrote, iclass 7, count 2 2006.175.07:59:59.10#ibcon#about to read 3, iclass 7, count 2 2006.175.07:59:59.13#ibcon#read 3, iclass 7, count 2 2006.175.07:59:59.13#ibcon#about to read 4, iclass 7, count 2 2006.175.07:59:59.13#ibcon#read 4, iclass 7, count 2 2006.175.07:59:59.13#ibcon#about to read 5, iclass 7, count 2 2006.175.07:59:59.13#ibcon#read 5, iclass 7, count 2 2006.175.07:59:59.13#ibcon#about to read 6, iclass 7, count 2 2006.175.07:59:59.13#ibcon#read 6, iclass 7, count 2 2006.175.07:59:59.13#ibcon#end of sib2, iclass 7, count 2 2006.175.07:59:59.13#ibcon#*after write, iclass 7, count 2 2006.175.07:59:59.13#ibcon#*before return 0, iclass 7, count 2 2006.175.07:59:59.13#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:59:59.13#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.07:59:59.13#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.07:59:59.13#ibcon#ireg 7 cls_cnt 0 2006.175.07:59:59.13#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:59:59.25#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:59:59.25#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:59:59.25#ibcon#enter wrdev, iclass 7, count 0 2006.175.07:59:59.25#ibcon#first serial, iclass 7, count 0 2006.175.07:59:59.25#ibcon#enter sib2, iclass 7, count 0 2006.175.07:59:59.25#ibcon#flushed, iclass 7, count 0 2006.175.07:59:59.25#ibcon#about to write, iclass 7, count 0 2006.175.07:59:59.25#ibcon#wrote, iclass 7, count 0 2006.175.07:59:59.25#ibcon#about to read 3, iclass 7, count 0 2006.175.07:59:59.27#ibcon#read 3, iclass 7, count 0 2006.175.07:59:59.27#ibcon#about to read 4, iclass 7, count 0 2006.175.07:59:59.27#ibcon#read 4, iclass 7, count 0 2006.175.07:59:59.27#ibcon#about to read 5, iclass 7, count 0 2006.175.07:59:59.27#ibcon#read 5, iclass 7, count 0 2006.175.07:59:59.27#ibcon#about to read 6, iclass 7, count 0 2006.175.07:59:59.27#ibcon#read 6, iclass 7, count 0 2006.175.07:59:59.27#ibcon#end of sib2, iclass 7, count 0 2006.175.07:59:59.27#ibcon#*mode == 0, iclass 7, count 0 2006.175.07:59:59.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.07:59:59.27#ibcon#[25=USB\r\n] 2006.175.07:59:59.27#ibcon#*before write, iclass 7, count 0 2006.175.07:59:59.27#ibcon#enter sib2, iclass 7, count 0 2006.175.07:59:59.27#ibcon#flushed, iclass 7, count 0 2006.175.07:59:59.27#ibcon#about to write, iclass 7, count 0 2006.175.07:59:59.27#ibcon#wrote, iclass 7, count 0 2006.175.07:59:59.27#ibcon#about to read 3, iclass 7, count 0 2006.175.07:59:59.30#ibcon#read 3, iclass 7, count 0 2006.175.07:59:59.30#ibcon#about to read 4, iclass 7, count 0 2006.175.07:59:59.30#ibcon#read 4, iclass 7, count 0 2006.175.07:59:59.30#ibcon#about to read 5, iclass 7, count 0 2006.175.07:59:59.30#ibcon#read 5, iclass 7, count 0 2006.175.07:59:59.30#ibcon#about to read 6, iclass 7, count 0 2006.175.07:59:59.30#ibcon#read 6, iclass 7, count 0 2006.175.07:59:59.30#ibcon#end of sib2, iclass 7, count 0 2006.175.07:59:59.30#ibcon#*after write, iclass 7, count 0 2006.175.07:59:59.30#ibcon#*before return 0, iclass 7, count 0 2006.175.07:59:59.30#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:59:59.30#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.07:59:59.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.07:59:59.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.07:59:59.30$vc4f8/valo=5,652.99 2006.175.07:59:59.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.07:59:59.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.07:59:59.30#ibcon#ireg 17 cls_cnt 0 2006.175.07:59:59.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:59:59.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:59:59.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:59:59.30#ibcon#enter wrdev, iclass 11, count 0 2006.175.07:59:59.30#ibcon#first serial, iclass 11, count 0 2006.175.07:59:59.30#ibcon#enter sib2, iclass 11, count 0 2006.175.07:59:59.30#ibcon#flushed, iclass 11, count 0 2006.175.07:59:59.30#ibcon#about to write, iclass 11, count 0 2006.175.07:59:59.30#ibcon#wrote, iclass 11, count 0 2006.175.07:59:59.30#ibcon#about to read 3, iclass 11, count 0 2006.175.07:59:59.32#ibcon#read 3, iclass 11, count 0 2006.175.07:59:59.32#ibcon#about to read 4, iclass 11, count 0 2006.175.07:59:59.32#ibcon#read 4, iclass 11, count 0 2006.175.07:59:59.32#ibcon#about to read 5, iclass 11, count 0 2006.175.07:59:59.32#ibcon#read 5, iclass 11, count 0 2006.175.07:59:59.32#ibcon#about to read 6, iclass 11, count 0 2006.175.07:59:59.32#ibcon#read 6, iclass 11, count 0 2006.175.07:59:59.32#ibcon#end of sib2, iclass 11, count 0 2006.175.07:59:59.32#ibcon#*mode == 0, iclass 11, count 0 2006.175.07:59:59.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.07:59:59.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.07:59:59.32#ibcon#*before write, iclass 11, count 0 2006.175.07:59:59.32#ibcon#enter sib2, iclass 11, count 0 2006.175.07:59:59.32#ibcon#flushed, iclass 11, count 0 2006.175.07:59:59.32#ibcon#about to write, iclass 11, count 0 2006.175.07:59:59.32#ibcon#wrote, iclass 11, count 0 2006.175.07:59:59.32#ibcon#about to read 3, iclass 11, count 0 2006.175.07:59:59.36#ibcon#read 3, iclass 11, count 0 2006.175.07:59:59.36#ibcon#about to read 4, iclass 11, count 0 2006.175.07:59:59.36#ibcon#read 4, iclass 11, count 0 2006.175.07:59:59.36#ibcon#about to read 5, iclass 11, count 0 2006.175.07:59:59.36#ibcon#read 5, iclass 11, count 0 2006.175.07:59:59.36#ibcon#about to read 6, iclass 11, count 0 2006.175.07:59:59.36#ibcon#read 6, iclass 11, count 0 2006.175.07:59:59.36#ibcon#end of sib2, iclass 11, count 0 2006.175.07:59:59.36#ibcon#*after write, iclass 11, count 0 2006.175.07:59:59.36#ibcon#*before return 0, iclass 11, count 0 2006.175.07:59:59.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:59:59.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.07:59:59.36#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.07:59:59.36#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.07:59:59.36$vc4f8/va=5,7 2006.175.07:59:59.36#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.07:59:59.36#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.07:59:59.36#ibcon#ireg 11 cls_cnt 2 2006.175.07:59:59.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:59:59.42#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:59:59.42#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:59:59.42#ibcon#enter wrdev, iclass 13, count 2 2006.175.07:59:59.42#ibcon#first serial, iclass 13, count 2 2006.175.07:59:59.42#ibcon#enter sib2, iclass 13, count 2 2006.175.07:59:59.42#ibcon#flushed, iclass 13, count 2 2006.175.07:59:59.42#ibcon#about to write, iclass 13, count 2 2006.175.07:59:59.42#ibcon#wrote, iclass 13, count 2 2006.175.07:59:59.42#ibcon#about to read 3, iclass 13, count 2 2006.175.07:59:59.44#ibcon#read 3, iclass 13, count 2 2006.175.07:59:59.44#ibcon#about to read 4, iclass 13, count 2 2006.175.07:59:59.44#ibcon#read 4, iclass 13, count 2 2006.175.07:59:59.44#ibcon#about to read 5, iclass 13, count 2 2006.175.07:59:59.44#ibcon#read 5, iclass 13, count 2 2006.175.07:59:59.44#ibcon#about to read 6, iclass 13, count 2 2006.175.07:59:59.44#ibcon#read 6, iclass 13, count 2 2006.175.07:59:59.44#ibcon#end of sib2, iclass 13, count 2 2006.175.07:59:59.44#ibcon#*mode == 0, iclass 13, count 2 2006.175.07:59:59.44#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.07:59:59.44#ibcon#[25=AT05-07\r\n] 2006.175.07:59:59.44#ibcon#*before write, iclass 13, count 2 2006.175.07:59:59.44#ibcon#enter sib2, iclass 13, count 2 2006.175.07:59:59.44#ibcon#flushed, iclass 13, count 2 2006.175.07:59:59.44#ibcon#about to write, iclass 13, count 2 2006.175.07:59:59.44#ibcon#wrote, iclass 13, count 2 2006.175.07:59:59.44#ibcon#about to read 3, iclass 13, count 2 2006.175.07:59:59.47#ibcon#read 3, iclass 13, count 2 2006.175.07:59:59.47#ibcon#about to read 4, iclass 13, count 2 2006.175.07:59:59.47#ibcon#read 4, iclass 13, count 2 2006.175.07:59:59.47#ibcon#about to read 5, iclass 13, count 2 2006.175.07:59:59.47#ibcon#read 5, iclass 13, count 2 2006.175.07:59:59.47#ibcon#about to read 6, iclass 13, count 2 2006.175.07:59:59.47#ibcon#read 6, iclass 13, count 2 2006.175.07:59:59.47#ibcon#end of sib2, iclass 13, count 2 2006.175.07:59:59.47#ibcon#*after write, iclass 13, count 2 2006.175.07:59:59.47#ibcon#*before return 0, iclass 13, count 2 2006.175.07:59:59.47#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:59:59.47#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.07:59:59.47#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.07:59:59.47#ibcon#ireg 7 cls_cnt 0 2006.175.07:59:59.47#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:59:59.59#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:59:59.59#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:59:59.59#ibcon#enter wrdev, iclass 13, count 0 2006.175.07:59:59.59#ibcon#first serial, iclass 13, count 0 2006.175.07:59:59.59#ibcon#enter sib2, iclass 13, count 0 2006.175.07:59:59.59#ibcon#flushed, iclass 13, count 0 2006.175.07:59:59.59#ibcon#about to write, iclass 13, count 0 2006.175.07:59:59.59#ibcon#wrote, iclass 13, count 0 2006.175.07:59:59.59#ibcon#about to read 3, iclass 13, count 0 2006.175.07:59:59.61#ibcon#read 3, iclass 13, count 0 2006.175.07:59:59.61#ibcon#about to read 4, iclass 13, count 0 2006.175.07:59:59.61#ibcon#read 4, iclass 13, count 0 2006.175.07:59:59.61#ibcon#about to read 5, iclass 13, count 0 2006.175.07:59:59.61#ibcon#read 5, iclass 13, count 0 2006.175.07:59:59.61#ibcon#about to read 6, iclass 13, count 0 2006.175.07:59:59.61#ibcon#read 6, iclass 13, count 0 2006.175.07:59:59.61#ibcon#end of sib2, iclass 13, count 0 2006.175.07:59:59.61#ibcon#*mode == 0, iclass 13, count 0 2006.175.07:59:59.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.07:59:59.61#ibcon#[25=USB\r\n] 2006.175.07:59:59.61#ibcon#*before write, iclass 13, count 0 2006.175.07:59:59.61#ibcon#enter sib2, iclass 13, count 0 2006.175.07:59:59.61#ibcon#flushed, iclass 13, count 0 2006.175.07:59:59.61#ibcon#about to write, iclass 13, count 0 2006.175.07:59:59.61#ibcon#wrote, iclass 13, count 0 2006.175.07:59:59.61#ibcon#about to read 3, iclass 13, count 0 2006.175.07:59:59.64#ibcon#read 3, iclass 13, count 0 2006.175.07:59:59.64#ibcon#about to read 4, iclass 13, count 0 2006.175.07:59:59.64#ibcon#read 4, iclass 13, count 0 2006.175.07:59:59.64#ibcon#about to read 5, iclass 13, count 0 2006.175.07:59:59.64#ibcon#read 5, iclass 13, count 0 2006.175.07:59:59.64#ibcon#about to read 6, iclass 13, count 0 2006.175.07:59:59.64#ibcon#read 6, iclass 13, count 0 2006.175.07:59:59.64#ibcon#end of sib2, iclass 13, count 0 2006.175.07:59:59.64#ibcon#*after write, iclass 13, count 0 2006.175.07:59:59.64#ibcon#*before return 0, iclass 13, count 0 2006.175.07:59:59.64#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:59:59.64#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.07:59:59.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.07:59:59.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.07:59:59.64$vc4f8/valo=6,772.99 2006.175.07:59:59.64#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.07:59:59.64#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.07:59:59.64#ibcon#ireg 17 cls_cnt 0 2006.175.07:59:59.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:59:59.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:59:59.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:59:59.64#ibcon#enter wrdev, iclass 15, count 0 2006.175.07:59:59.64#ibcon#first serial, iclass 15, count 0 2006.175.07:59:59.64#ibcon#enter sib2, iclass 15, count 0 2006.175.07:59:59.64#ibcon#flushed, iclass 15, count 0 2006.175.07:59:59.64#ibcon#about to write, iclass 15, count 0 2006.175.07:59:59.64#ibcon#wrote, iclass 15, count 0 2006.175.07:59:59.64#ibcon#about to read 3, iclass 15, count 0 2006.175.07:59:59.66#ibcon#read 3, iclass 15, count 0 2006.175.07:59:59.66#ibcon#about to read 4, iclass 15, count 0 2006.175.07:59:59.66#ibcon#read 4, iclass 15, count 0 2006.175.07:59:59.66#ibcon#about to read 5, iclass 15, count 0 2006.175.07:59:59.66#ibcon#read 5, iclass 15, count 0 2006.175.07:59:59.66#ibcon#about to read 6, iclass 15, count 0 2006.175.07:59:59.66#ibcon#read 6, iclass 15, count 0 2006.175.07:59:59.66#ibcon#end of sib2, iclass 15, count 0 2006.175.07:59:59.66#ibcon#*mode == 0, iclass 15, count 0 2006.175.07:59:59.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.07:59:59.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.07:59:59.66#ibcon#*before write, iclass 15, count 0 2006.175.07:59:59.66#ibcon#enter sib2, iclass 15, count 0 2006.175.07:59:59.66#ibcon#flushed, iclass 15, count 0 2006.175.07:59:59.66#ibcon#about to write, iclass 15, count 0 2006.175.07:59:59.66#ibcon#wrote, iclass 15, count 0 2006.175.07:59:59.66#ibcon#about to read 3, iclass 15, count 0 2006.175.07:59:59.70#ibcon#read 3, iclass 15, count 0 2006.175.07:59:59.70#ibcon#about to read 4, iclass 15, count 0 2006.175.07:59:59.70#ibcon#read 4, iclass 15, count 0 2006.175.07:59:59.70#ibcon#about to read 5, iclass 15, count 0 2006.175.07:59:59.70#ibcon#read 5, iclass 15, count 0 2006.175.07:59:59.70#ibcon#about to read 6, iclass 15, count 0 2006.175.07:59:59.70#ibcon#read 6, iclass 15, count 0 2006.175.07:59:59.70#ibcon#end of sib2, iclass 15, count 0 2006.175.07:59:59.70#ibcon#*after write, iclass 15, count 0 2006.175.07:59:59.70#ibcon#*before return 0, iclass 15, count 0 2006.175.07:59:59.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:59:59.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.07:59:59.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.07:59:59.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.07:59:59.70$vc4f8/va=6,6 2006.175.07:59:59.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.07:59:59.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.07:59:59.70#ibcon#ireg 11 cls_cnt 2 2006.175.07:59:59.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:59:59.72#abcon#<5=/04 3.6 7.5 25.86 701007.4\r\n> 2006.175.07:59:59.74#abcon#{5=INTERFACE CLEAR} 2006.175.07:59:59.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:59:59.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:59:59.76#ibcon#enter wrdev, iclass 18, count 2 2006.175.07:59:59.76#ibcon#first serial, iclass 18, count 2 2006.175.07:59:59.76#ibcon#enter sib2, iclass 18, count 2 2006.175.07:59:59.76#ibcon#flushed, iclass 18, count 2 2006.175.07:59:59.76#ibcon#about to write, iclass 18, count 2 2006.175.07:59:59.76#ibcon#wrote, iclass 18, count 2 2006.175.07:59:59.76#ibcon#about to read 3, iclass 18, count 2 2006.175.07:59:59.78#ibcon#read 3, iclass 18, count 2 2006.175.07:59:59.78#ibcon#about to read 4, iclass 18, count 2 2006.175.07:59:59.78#ibcon#read 4, iclass 18, count 2 2006.175.07:59:59.78#ibcon#about to read 5, iclass 18, count 2 2006.175.07:59:59.78#ibcon#read 5, iclass 18, count 2 2006.175.07:59:59.78#ibcon#about to read 6, iclass 18, count 2 2006.175.07:59:59.78#ibcon#read 6, iclass 18, count 2 2006.175.07:59:59.78#ibcon#end of sib2, iclass 18, count 2 2006.175.07:59:59.78#ibcon#*mode == 0, iclass 18, count 2 2006.175.07:59:59.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.07:59:59.78#ibcon#[25=AT06-06\r\n] 2006.175.07:59:59.78#ibcon#*before write, iclass 18, count 2 2006.175.07:59:59.78#ibcon#enter sib2, iclass 18, count 2 2006.175.07:59:59.78#ibcon#flushed, iclass 18, count 2 2006.175.07:59:59.78#ibcon#about to write, iclass 18, count 2 2006.175.07:59:59.78#ibcon#wrote, iclass 18, count 2 2006.175.07:59:59.78#ibcon#about to read 3, iclass 18, count 2 2006.175.07:59:59.80#abcon#[5=S1D000X0/0*\r\n] 2006.175.07:59:59.81#ibcon#read 3, iclass 18, count 2 2006.175.07:59:59.81#ibcon#about to read 4, iclass 18, count 2 2006.175.07:59:59.81#ibcon#read 4, iclass 18, count 2 2006.175.07:59:59.81#ibcon#about to read 5, iclass 18, count 2 2006.175.07:59:59.81#ibcon#read 5, iclass 18, count 2 2006.175.07:59:59.81#ibcon#about to read 6, iclass 18, count 2 2006.175.07:59:59.81#ibcon#read 6, iclass 18, count 2 2006.175.07:59:59.81#ibcon#end of sib2, iclass 18, count 2 2006.175.07:59:59.81#ibcon#*after write, iclass 18, count 2 2006.175.07:59:59.81#ibcon#*before return 0, iclass 18, count 2 2006.175.07:59:59.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:59:59.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.07:59:59.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.07:59:59.81#ibcon#ireg 7 cls_cnt 0 2006.175.07:59:59.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:59:59.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:59:59.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:59:59.93#ibcon#enter wrdev, iclass 18, count 0 2006.175.07:59:59.93#ibcon#first serial, iclass 18, count 0 2006.175.07:59:59.93#ibcon#enter sib2, iclass 18, count 0 2006.175.07:59:59.93#ibcon#flushed, iclass 18, count 0 2006.175.07:59:59.93#ibcon#about to write, iclass 18, count 0 2006.175.07:59:59.93#ibcon#wrote, iclass 18, count 0 2006.175.07:59:59.93#ibcon#about to read 3, iclass 18, count 0 2006.175.07:59:59.95#ibcon#read 3, iclass 18, count 0 2006.175.07:59:59.95#ibcon#about to read 4, iclass 18, count 0 2006.175.07:59:59.95#ibcon#read 4, iclass 18, count 0 2006.175.07:59:59.95#ibcon#about to read 5, iclass 18, count 0 2006.175.07:59:59.95#ibcon#read 5, iclass 18, count 0 2006.175.07:59:59.95#ibcon#about to read 6, iclass 18, count 0 2006.175.07:59:59.95#ibcon#read 6, iclass 18, count 0 2006.175.07:59:59.95#ibcon#end of sib2, iclass 18, count 0 2006.175.07:59:59.95#ibcon#*mode == 0, iclass 18, count 0 2006.175.07:59:59.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.07:59:59.95#ibcon#[25=USB\r\n] 2006.175.07:59:59.95#ibcon#*before write, iclass 18, count 0 2006.175.07:59:59.95#ibcon#enter sib2, iclass 18, count 0 2006.175.07:59:59.95#ibcon#flushed, iclass 18, count 0 2006.175.07:59:59.95#ibcon#about to write, iclass 18, count 0 2006.175.07:59:59.95#ibcon#wrote, iclass 18, count 0 2006.175.07:59:59.95#ibcon#about to read 3, iclass 18, count 0 2006.175.07:59:59.98#ibcon#read 3, iclass 18, count 0 2006.175.07:59:59.98#ibcon#about to read 4, iclass 18, count 0 2006.175.07:59:59.98#ibcon#read 4, iclass 18, count 0 2006.175.07:59:59.98#ibcon#about to read 5, iclass 18, count 0 2006.175.07:59:59.98#ibcon#read 5, iclass 18, count 0 2006.175.07:59:59.98#ibcon#about to read 6, iclass 18, count 0 2006.175.07:59:59.98#ibcon#read 6, iclass 18, count 0 2006.175.07:59:59.98#ibcon#end of sib2, iclass 18, count 0 2006.175.07:59:59.98#ibcon#*after write, iclass 18, count 0 2006.175.07:59:59.98#ibcon#*before return 0, iclass 18, count 0 2006.175.07:59:59.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:59:59.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.07:59:59.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.07:59:59.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.07:59:59.98$vc4f8/valo=7,832.99 2006.175.07:59:59.98#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.07:59:59.98#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.07:59:59.98#ibcon#ireg 17 cls_cnt 0 2006.175.07:59:59.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:59:59.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:59:59.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.07:59:59.98#ibcon#enter wrdev, iclass 23, count 0 2006.175.07:59:59.98#ibcon#first serial, iclass 23, count 0 2006.175.07:59:59.98#ibcon#enter sib2, iclass 23, count 0 2006.175.07:59:59.98#ibcon#flushed, iclass 23, count 0 2006.175.07:59:59.98#ibcon#about to write, iclass 23, count 0 2006.175.07:59:59.98#ibcon#wrote, iclass 23, count 0 2006.175.07:59:59.98#ibcon#about to read 3, iclass 23, count 0 2006.175.08:00:00.00#ibcon#read 3, iclass 23, count 0 2006.175.08:00:00.00#ibcon#about to read 4, iclass 23, count 0 2006.175.08:00:00.00#ibcon#read 4, iclass 23, count 0 2006.175.08:00:00.00#ibcon#about to read 5, iclass 23, count 0 2006.175.08:00:00.00#ibcon#read 5, iclass 23, count 0 2006.175.08:00:00.00#ibcon#about to read 6, iclass 23, count 0 2006.175.08:00:00.00#ibcon#read 6, iclass 23, count 0 2006.175.08:00:00.00#ibcon#end of sib2, iclass 23, count 0 2006.175.08:00:00.00#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:00:00.00#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:00:00.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:00:00.00#ibcon#*before write, iclass 23, count 0 2006.175.08:00:00.00#ibcon#enter sib2, iclass 23, count 0 2006.175.08:00:00.00#ibcon#flushed, iclass 23, count 0 2006.175.08:00:00.00#ibcon#about to write, iclass 23, count 0 2006.175.08:00:00.00#ibcon#wrote, iclass 23, count 0 2006.175.08:00:00.00#ibcon#about to read 3, iclass 23, count 0 2006.175.08:00:00.04#ibcon#read 3, iclass 23, count 0 2006.175.08:00:00.04#ibcon#about to read 4, iclass 23, count 0 2006.175.08:00:00.04#ibcon#read 4, iclass 23, count 0 2006.175.08:00:00.04#ibcon#about to read 5, iclass 23, count 0 2006.175.08:00:00.04#ibcon#read 5, iclass 23, count 0 2006.175.08:00:00.04#ibcon#about to read 6, iclass 23, count 0 2006.175.08:00:00.04#ibcon#read 6, iclass 23, count 0 2006.175.08:00:00.04#ibcon#end of sib2, iclass 23, count 0 2006.175.08:00:00.04#ibcon#*after write, iclass 23, count 0 2006.175.08:00:00.04#ibcon#*before return 0, iclass 23, count 0 2006.175.08:00:00.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:00:00.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:00:00.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:00:00.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:00:00.04$vc4f8/va=7,6 2006.175.08:00:00.04#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.08:00:00.04#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.08:00:00.04#ibcon#ireg 11 cls_cnt 2 2006.175.08:00:00.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:00:00.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:00:00.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:00:00.10#ibcon#enter wrdev, iclass 25, count 2 2006.175.08:00:00.10#ibcon#first serial, iclass 25, count 2 2006.175.08:00:00.10#ibcon#enter sib2, iclass 25, count 2 2006.175.08:00:00.10#ibcon#flushed, iclass 25, count 2 2006.175.08:00:00.10#ibcon#about to write, iclass 25, count 2 2006.175.08:00:00.10#ibcon#wrote, iclass 25, count 2 2006.175.08:00:00.10#ibcon#about to read 3, iclass 25, count 2 2006.175.08:00:00.12#ibcon#read 3, iclass 25, count 2 2006.175.08:00:00.12#ibcon#about to read 4, iclass 25, count 2 2006.175.08:00:00.12#ibcon#read 4, iclass 25, count 2 2006.175.08:00:00.12#ibcon#about to read 5, iclass 25, count 2 2006.175.08:00:00.12#ibcon#read 5, iclass 25, count 2 2006.175.08:00:00.12#ibcon#about to read 6, iclass 25, count 2 2006.175.08:00:00.12#ibcon#read 6, iclass 25, count 2 2006.175.08:00:00.12#ibcon#end of sib2, iclass 25, count 2 2006.175.08:00:00.12#ibcon#*mode == 0, iclass 25, count 2 2006.175.08:00:00.12#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.08:00:00.12#ibcon#[25=AT07-06\r\n] 2006.175.08:00:00.12#ibcon#*before write, iclass 25, count 2 2006.175.08:00:00.12#ibcon#enter sib2, iclass 25, count 2 2006.175.08:00:00.12#ibcon#flushed, iclass 25, count 2 2006.175.08:00:00.12#ibcon#about to write, iclass 25, count 2 2006.175.08:00:00.12#ibcon#wrote, iclass 25, count 2 2006.175.08:00:00.12#ibcon#about to read 3, iclass 25, count 2 2006.175.08:00:00.15#ibcon#read 3, iclass 25, count 2 2006.175.08:00:00.15#ibcon#about to read 4, iclass 25, count 2 2006.175.08:00:00.15#ibcon#read 4, iclass 25, count 2 2006.175.08:00:00.15#ibcon#about to read 5, iclass 25, count 2 2006.175.08:00:00.15#ibcon#read 5, iclass 25, count 2 2006.175.08:00:00.15#ibcon#about to read 6, iclass 25, count 2 2006.175.08:00:00.15#ibcon#read 6, iclass 25, count 2 2006.175.08:00:00.15#ibcon#end of sib2, iclass 25, count 2 2006.175.08:00:00.15#ibcon#*after write, iclass 25, count 2 2006.175.08:00:00.15#ibcon#*before return 0, iclass 25, count 2 2006.175.08:00:00.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:00:00.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:00:00.15#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.08:00:00.15#ibcon#ireg 7 cls_cnt 0 2006.175.08:00:00.15#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:00:00.27#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:00:00.27#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:00:00.27#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:00:00.27#ibcon#first serial, iclass 25, count 0 2006.175.08:00:00.27#ibcon#enter sib2, iclass 25, count 0 2006.175.08:00:00.27#ibcon#flushed, iclass 25, count 0 2006.175.08:00:00.27#ibcon#about to write, iclass 25, count 0 2006.175.08:00:00.27#ibcon#wrote, iclass 25, count 0 2006.175.08:00:00.27#ibcon#about to read 3, iclass 25, count 0 2006.175.08:00:00.29#ibcon#read 3, iclass 25, count 0 2006.175.08:00:00.29#ibcon#about to read 4, iclass 25, count 0 2006.175.08:00:00.29#ibcon#read 4, iclass 25, count 0 2006.175.08:00:00.29#ibcon#about to read 5, iclass 25, count 0 2006.175.08:00:00.29#ibcon#read 5, iclass 25, count 0 2006.175.08:00:00.29#ibcon#about to read 6, iclass 25, count 0 2006.175.08:00:00.29#ibcon#read 6, iclass 25, count 0 2006.175.08:00:00.29#ibcon#end of sib2, iclass 25, count 0 2006.175.08:00:00.29#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:00:00.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:00:00.29#ibcon#[25=USB\r\n] 2006.175.08:00:00.29#ibcon#*before write, iclass 25, count 0 2006.175.08:00:00.29#ibcon#enter sib2, iclass 25, count 0 2006.175.08:00:00.29#ibcon#flushed, iclass 25, count 0 2006.175.08:00:00.29#ibcon#about to write, iclass 25, count 0 2006.175.08:00:00.29#ibcon#wrote, iclass 25, count 0 2006.175.08:00:00.29#ibcon#about to read 3, iclass 25, count 0 2006.175.08:00:00.32#ibcon#read 3, iclass 25, count 0 2006.175.08:00:00.32#ibcon#about to read 4, iclass 25, count 0 2006.175.08:00:00.32#ibcon#read 4, iclass 25, count 0 2006.175.08:00:00.32#ibcon#about to read 5, iclass 25, count 0 2006.175.08:00:00.32#ibcon#read 5, iclass 25, count 0 2006.175.08:00:00.32#ibcon#about to read 6, iclass 25, count 0 2006.175.08:00:00.32#ibcon#read 6, iclass 25, count 0 2006.175.08:00:00.32#ibcon#end of sib2, iclass 25, count 0 2006.175.08:00:00.32#ibcon#*after write, iclass 25, count 0 2006.175.08:00:00.32#ibcon#*before return 0, iclass 25, count 0 2006.175.08:00:00.32#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:00:00.32#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:00:00.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:00:00.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:00:00.32$vc4f8/valo=8,852.99 2006.175.08:00:00.32#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.08:00:00.32#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.08:00:00.32#ibcon#ireg 17 cls_cnt 0 2006.175.08:00:00.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:00:00.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:00:00.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:00:00.32#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:00:00.32#ibcon#first serial, iclass 27, count 0 2006.175.08:00:00.32#ibcon#enter sib2, iclass 27, count 0 2006.175.08:00:00.32#ibcon#flushed, iclass 27, count 0 2006.175.08:00:00.32#ibcon#about to write, iclass 27, count 0 2006.175.08:00:00.32#ibcon#wrote, iclass 27, count 0 2006.175.08:00:00.32#ibcon#about to read 3, iclass 27, count 0 2006.175.08:00:00.34#ibcon#read 3, iclass 27, count 0 2006.175.08:00:00.34#ibcon#about to read 4, iclass 27, count 0 2006.175.08:00:00.34#ibcon#read 4, iclass 27, count 0 2006.175.08:00:00.34#ibcon#about to read 5, iclass 27, count 0 2006.175.08:00:00.34#ibcon#read 5, iclass 27, count 0 2006.175.08:00:00.34#ibcon#about to read 6, iclass 27, count 0 2006.175.08:00:00.34#ibcon#read 6, iclass 27, count 0 2006.175.08:00:00.34#ibcon#end of sib2, iclass 27, count 0 2006.175.08:00:00.34#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:00:00.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:00:00.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:00:00.34#ibcon#*before write, iclass 27, count 0 2006.175.08:00:00.34#ibcon#enter sib2, iclass 27, count 0 2006.175.08:00:00.34#ibcon#flushed, iclass 27, count 0 2006.175.08:00:00.34#ibcon#about to write, iclass 27, count 0 2006.175.08:00:00.34#ibcon#wrote, iclass 27, count 0 2006.175.08:00:00.34#ibcon#about to read 3, iclass 27, count 0 2006.175.08:00:00.38#ibcon#read 3, iclass 27, count 0 2006.175.08:00:00.38#ibcon#about to read 4, iclass 27, count 0 2006.175.08:00:00.38#ibcon#read 4, iclass 27, count 0 2006.175.08:00:00.38#ibcon#about to read 5, iclass 27, count 0 2006.175.08:00:00.38#ibcon#read 5, iclass 27, count 0 2006.175.08:00:00.38#ibcon#about to read 6, iclass 27, count 0 2006.175.08:00:00.38#ibcon#read 6, iclass 27, count 0 2006.175.08:00:00.38#ibcon#end of sib2, iclass 27, count 0 2006.175.08:00:00.38#ibcon#*after write, iclass 27, count 0 2006.175.08:00:00.38#ibcon#*before return 0, iclass 27, count 0 2006.175.08:00:00.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:00:00.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:00:00.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:00:00.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:00:00.38$vc4f8/va=8,6 2006.175.08:00:00.38#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.175.08:00:00.38#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.175.08:00:00.38#ibcon#ireg 11 cls_cnt 2 2006.175.08:00:00.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:00:00.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:00:00.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:00:00.45#ibcon#enter wrdev, iclass 29, count 2 2006.175.08:00:00.45#ibcon#first serial, iclass 29, count 2 2006.175.08:00:00.45#ibcon#enter sib2, iclass 29, count 2 2006.175.08:00:00.45#ibcon#flushed, iclass 29, count 2 2006.175.08:00:00.45#ibcon#about to write, iclass 29, count 2 2006.175.08:00:00.45#ibcon#wrote, iclass 29, count 2 2006.175.08:00:00.45#ibcon#about to read 3, iclass 29, count 2 2006.175.08:00:00.46#ibcon#read 3, iclass 29, count 2 2006.175.08:00:00.46#ibcon#about to read 4, iclass 29, count 2 2006.175.08:00:00.46#ibcon#read 4, iclass 29, count 2 2006.175.08:00:00.46#ibcon#about to read 5, iclass 29, count 2 2006.175.08:00:00.46#ibcon#read 5, iclass 29, count 2 2006.175.08:00:00.46#ibcon#about to read 6, iclass 29, count 2 2006.175.08:00:00.46#ibcon#read 6, iclass 29, count 2 2006.175.08:00:00.46#ibcon#end of sib2, iclass 29, count 2 2006.175.08:00:00.46#ibcon#*mode == 0, iclass 29, count 2 2006.175.08:00:00.46#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.175.08:00:00.46#ibcon#[25=AT08-06\r\n] 2006.175.08:00:00.46#ibcon#*before write, iclass 29, count 2 2006.175.08:00:00.46#ibcon#enter sib2, iclass 29, count 2 2006.175.08:00:00.46#ibcon#flushed, iclass 29, count 2 2006.175.08:00:00.46#ibcon#about to write, iclass 29, count 2 2006.175.08:00:00.46#ibcon#wrote, iclass 29, count 2 2006.175.08:00:00.47#ibcon#about to read 3, iclass 29, count 2 2006.175.08:00:00.49#ibcon#read 3, iclass 29, count 2 2006.175.08:00:00.49#ibcon#about to read 4, iclass 29, count 2 2006.175.08:00:00.49#ibcon#read 4, iclass 29, count 2 2006.175.08:00:00.49#ibcon#about to read 5, iclass 29, count 2 2006.175.08:00:00.49#ibcon#read 5, iclass 29, count 2 2006.175.08:00:00.49#ibcon#about to read 6, iclass 29, count 2 2006.175.08:00:00.49#ibcon#read 6, iclass 29, count 2 2006.175.08:00:00.49#ibcon#end of sib2, iclass 29, count 2 2006.175.08:00:00.49#ibcon#*after write, iclass 29, count 2 2006.175.08:00:00.49#ibcon#*before return 0, iclass 29, count 2 2006.175.08:00:00.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:00:00.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:00:00.49#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.175.08:00:00.49#ibcon#ireg 7 cls_cnt 0 2006.175.08:00:00.49#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:00:00.61#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:00:00.61#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:00:00.61#ibcon#enter wrdev, iclass 29, count 0 2006.175.08:00:00.61#ibcon#first serial, iclass 29, count 0 2006.175.08:00:00.61#ibcon#enter sib2, iclass 29, count 0 2006.175.08:00:00.61#ibcon#flushed, iclass 29, count 0 2006.175.08:00:00.61#ibcon#about to write, iclass 29, count 0 2006.175.08:00:00.61#ibcon#wrote, iclass 29, count 0 2006.175.08:00:00.61#ibcon#about to read 3, iclass 29, count 0 2006.175.08:00:00.63#ibcon#read 3, iclass 29, count 0 2006.175.08:00:00.63#ibcon#about to read 4, iclass 29, count 0 2006.175.08:00:00.63#ibcon#read 4, iclass 29, count 0 2006.175.08:00:00.63#ibcon#about to read 5, iclass 29, count 0 2006.175.08:00:00.63#ibcon#read 5, iclass 29, count 0 2006.175.08:00:00.63#ibcon#about to read 6, iclass 29, count 0 2006.175.08:00:00.63#ibcon#read 6, iclass 29, count 0 2006.175.08:00:00.63#ibcon#end of sib2, iclass 29, count 0 2006.175.08:00:00.63#ibcon#*mode == 0, iclass 29, count 0 2006.175.08:00:00.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.08:00:00.63#ibcon#[25=USB\r\n] 2006.175.08:00:00.63#ibcon#*before write, iclass 29, count 0 2006.175.08:00:00.63#ibcon#enter sib2, iclass 29, count 0 2006.175.08:00:00.63#ibcon#flushed, iclass 29, count 0 2006.175.08:00:00.63#ibcon#about to write, iclass 29, count 0 2006.175.08:00:00.63#ibcon#wrote, iclass 29, count 0 2006.175.08:00:00.63#ibcon#about to read 3, iclass 29, count 0 2006.175.08:00:00.66#ibcon#read 3, iclass 29, count 0 2006.175.08:00:00.66#ibcon#about to read 4, iclass 29, count 0 2006.175.08:00:00.66#ibcon#read 4, iclass 29, count 0 2006.175.08:00:00.66#ibcon#about to read 5, iclass 29, count 0 2006.175.08:00:00.66#ibcon#read 5, iclass 29, count 0 2006.175.08:00:00.66#ibcon#about to read 6, iclass 29, count 0 2006.175.08:00:00.66#ibcon#read 6, iclass 29, count 0 2006.175.08:00:00.66#ibcon#end of sib2, iclass 29, count 0 2006.175.08:00:00.66#ibcon#*after write, iclass 29, count 0 2006.175.08:00:00.66#ibcon#*before return 0, iclass 29, count 0 2006.175.08:00:00.66#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:00:00.66#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:00:00.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.08:00:00.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.08:00:00.66$vc4f8/vblo=1,632.99 2006.175.08:00:00.66#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.08:00:00.66#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.08:00:00.66#ibcon#ireg 17 cls_cnt 0 2006.175.08:00:00.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:00:00.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:00:00.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:00:00.66#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:00:00.66#ibcon#first serial, iclass 31, count 0 2006.175.08:00:00.66#ibcon#enter sib2, iclass 31, count 0 2006.175.08:00:00.66#ibcon#flushed, iclass 31, count 0 2006.175.08:00:00.66#ibcon#about to write, iclass 31, count 0 2006.175.08:00:00.66#ibcon#wrote, iclass 31, count 0 2006.175.08:00:00.66#ibcon#about to read 3, iclass 31, count 0 2006.175.08:00:00.68#ibcon#read 3, iclass 31, count 0 2006.175.08:00:00.68#ibcon#about to read 4, iclass 31, count 0 2006.175.08:00:00.68#ibcon#read 4, iclass 31, count 0 2006.175.08:00:00.68#ibcon#about to read 5, iclass 31, count 0 2006.175.08:00:00.68#ibcon#read 5, iclass 31, count 0 2006.175.08:00:00.68#ibcon#about to read 6, iclass 31, count 0 2006.175.08:00:00.68#ibcon#read 6, iclass 31, count 0 2006.175.08:00:00.68#ibcon#end of sib2, iclass 31, count 0 2006.175.08:00:00.68#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:00:00.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:00:00.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:00:00.68#ibcon#*before write, iclass 31, count 0 2006.175.08:00:00.68#ibcon#enter sib2, iclass 31, count 0 2006.175.08:00:00.68#ibcon#flushed, iclass 31, count 0 2006.175.08:00:00.68#ibcon#about to write, iclass 31, count 0 2006.175.08:00:00.68#ibcon#wrote, iclass 31, count 0 2006.175.08:00:00.68#ibcon#about to read 3, iclass 31, count 0 2006.175.08:00:00.72#ibcon#read 3, iclass 31, count 0 2006.175.08:00:00.72#ibcon#about to read 4, iclass 31, count 0 2006.175.08:00:00.72#ibcon#read 4, iclass 31, count 0 2006.175.08:00:00.72#ibcon#about to read 5, iclass 31, count 0 2006.175.08:00:00.72#ibcon#read 5, iclass 31, count 0 2006.175.08:00:00.72#ibcon#about to read 6, iclass 31, count 0 2006.175.08:00:00.72#ibcon#read 6, iclass 31, count 0 2006.175.08:00:00.72#ibcon#end of sib2, iclass 31, count 0 2006.175.08:00:00.72#ibcon#*after write, iclass 31, count 0 2006.175.08:00:00.72#ibcon#*before return 0, iclass 31, count 0 2006.175.08:00:00.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:00:00.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:00:00.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:00:00.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:00:00.72$vc4f8/vb=1,4 2006.175.08:00:00.72#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.08:00:00.72#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.08:00:00.72#ibcon#ireg 11 cls_cnt 2 2006.175.08:00:00.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:00:00.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:00:00.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:00:00.72#ibcon#enter wrdev, iclass 33, count 2 2006.175.08:00:00.72#ibcon#first serial, iclass 33, count 2 2006.175.08:00:00.72#ibcon#enter sib2, iclass 33, count 2 2006.175.08:00:00.72#ibcon#flushed, iclass 33, count 2 2006.175.08:00:00.72#ibcon#about to write, iclass 33, count 2 2006.175.08:00:00.72#ibcon#wrote, iclass 33, count 2 2006.175.08:00:00.72#ibcon#about to read 3, iclass 33, count 2 2006.175.08:00:00.74#ibcon#read 3, iclass 33, count 2 2006.175.08:00:00.74#ibcon#about to read 4, iclass 33, count 2 2006.175.08:00:00.74#ibcon#read 4, iclass 33, count 2 2006.175.08:00:00.74#ibcon#about to read 5, iclass 33, count 2 2006.175.08:00:00.74#ibcon#read 5, iclass 33, count 2 2006.175.08:00:00.74#ibcon#about to read 6, iclass 33, count 2 2006.175.08:00:00.74#ibcon#read 6, iclass 33, count 2 2006.175.08:00:00.74#ibcon#end of sib2, iclass 33, count 2 2006.175.08:00:00.74#ibcon#*mode == 0, iclass 33, count 2 2006.175.08:00:00.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.08:00:00.74#ibcon#[27=AT01-04\r\n] 2006.175.08:00:00.74#ibcon#*before write, iclass 33, count 2 2006.175.08:00:00.74#ibcon#enter sib2, iclass 33, count 2 2006.175.08:00:00.74#ibcon#flushed, iclass 33, count 2 2006.175.08:00:00.74#ibcon#about to write, iclass 33, count 2 2006.175.08:00:00.74#ibcon#wrote, iclass 33, count 2 2006.175.08:00:00.74#ibcon#about to read 3, iclass 33, count 2 2006.175.08:00:00.77#ibcon#read 3, iclass 33, count 2 2006.175.08:00:00.77#ibcon#about to read 4, iclass 33, count 2 2006.175.08:00:00.77#ibcon#read 4, iclass 33, count 2 2006.175.08:00:00.77#ibcon#about to read 5, iclass 33, count 2 2006.175.08:00:00.77#ibcon#read 5, iclass 33, count 2 2006.175.08:00:00.77#ibcon#about to read 6, iclass 33, count 2 2006.175.08:00:00.77#ibcon#read 6, iclass 33, count 2 2006.175.08:00:00.77#ibcon#end of sib2, iclass 33, count 2 2006.175.08:00:00.77#ibcon#*after write, iclass 33, count 2 2006.175.08:00:00.77#ibcon#*before return 0, iclass 33, count 2 2006.175.08:00:00.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:00:00.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:00:00.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.08:00:00.77#ibcon#ireg 7 cls_cnt 0 2006.175.08:00:00.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:00:00.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:00:00.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:00:00.89#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:00:00.89#ibcon#first serial, iclass 33, count 0 2006.175.08:00:00.89#ibcon#enter sib2, iclass 33, count 0 2006.175.08:00:00.89#ibcon#flushed, iclass 33, count 0 2006.175.08:00:00.89#ibcon#about to write, iclass 33, count 0 2006.175.08:00:00.89#ibcon#wrote, iclass 33, count 0 2006.175.08:00:00.89#ibcon#about to read 3, iclass 33, count 0 2006.175.08:00:00.91#ibcon#read 3, iclass 33, count 0 2006.175.08:00:00.91#ibcon#about to read 4, iclass 33, count 0 2006.175.08:00:00.91#ibcon#read 4, iclass 33, count 0 2006.175.08:00:00.91#ibcon#about to read 5, iclass 33, count 0 2006.175.08:00:00.91#ibcon#read 5, iclass 33, count 0 2006.175.08:00:00.91#ibcon#about to read 6, iclass 33, count 0 2006.175.08:00:00.91#ibcon#read 6, iclass 33, count 0 2006.175.08:00:00.91#ibcon#end of sib2, iclass 33, count 0 2006.175.08:00:00.91#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:00:00.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:00:00.91#ibcon#[27=USB\r\n] 2006.175.08:00:00.91#ibcon#*before write, iclass 33, count 0 2006.175.08:00:00.91#ibcon#enter sib2, iclass 33, count 0 2006.175.08:00:00.91#ibcon#flushed, iclass 33, count 0 2006.175.08:00:00.91#ibcon#about to write, iclass 33, count 0 2006.175.08:00:00.91#ibcon#wrote, iclass 33, count 0 2006.175.08:00:00.91#ibcon#about to read 3, iclass 33, count 0 2006.175.08:00:00.94#ibcon#read 3, iclass 33, count 0 2006.175.08:00:00.94#ibcon#about to read 4, iclass 33, count 0 2006.175.08:00:00.94#ibcon#read 4, iclass 33, count 0 2006.175.08:00:00.94#ibcon#about to read 5, iclass 33, count 0 2006.175.08:00:00.94#ibcon#read 5, iclass 33, count 0 2006.175.08:00:00.94#ibcon#about to read 6, iclass 33, count 0 2006.175.08:00:00.94#ibcon#read 6, iclass 33, count 0 2006.175.08:00:00.94#ibcon#end of sib2, iclass 33, count 0 2006.175.08:00:00.94#ibcon#*after write, iclass 33, count 0 2006.175.08:00:00.94#ibcon#*before return 0, iclass 33, count 0 2006.175.08:00:00.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:00:00.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:00:00.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:00:00.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:00:00.94$vc4f8/vblo=2,640.99 2006.175.08:00:00.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.08:00:00.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.08:00:00.94#ibcon#ireg 17 cls_cnt 0 2006.175.08:00:00.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:00:00.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:00:00.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:00:00.94#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:00:00.94#ibcon#first serial, iclass 35, count 0 2006.175.08:00:00.94#ibcon#enter sib2, iclass 35, count 0 2006.175.08:00:00.94#ibcon#flushed, iclass 35, count 0 2006.175.08:00:00.94#ibcon#about to write, iclass 35, count 0 2006.175.08:00:00.94#ibcon#wrote, iclass 35, count 0 2006.175.08:00:00.94#ibcon#about to read 3, iclass 35, count 0 2006.175.08:00:00.96#ibcon#read 3, iclass 35, count 0 2006.175.08:00:00.96#ibcon#about to read 4, iclass 35, count 0 2006.175.08:00:00.96#ibcon#read 4, iclass 35, count 0 2006.175.08:00:00.96#ibcon#about to read 5, iclass 35, count 0 2006.175.08:00:00.96#ibcon#read 5, iclass 35, count 0 2006.175.08:00:00.96#ibcon#about to read 6, iclass 35, count 0 2006.175.08:00:00.96#ibcon#read 6, iclass 35, count 0 2006.175.08:00:00.96#ibcon#end of sib2, iclass 35, count 0 2006.175.08:00:00.96#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:00:00.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:00:00.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:00:00.96#ibcon#*before write, iclass 35, count 0 2006.175.08:00:00.96#ibcon#enter sib2, iclass 35, count 0 2006.175.08:00:00.96#ibcon#flushed, iclass 35, count 0 2006.175.08:00:00.96#ibcon#about to write, iclass 35, count 0 2006.175.08:00:00.96#ibcon#wrote, iclass 35, count 0 2006.175.08:00:00.96#ibcon#about to read 3, iclass 35, count 0 2006.175.08:00:01.00#ibcon#read 3, iclass 35, count 0 2006.175.08:00:01.00#ibcon#about to read 4, iclass 35, count 0 2006.175.08:00:01.00#ibcon#read 4, iclass 35, count 0 2006.175.08:00:01.00#ibcon#about to read 5, iclass 35, count 0 2006.175.08:00:01.00#ibcon#read 5, iclass 35, count 0 2006.175.08:00:01.00#ibcon#about to read 6, iclass 35, count 0 2006.175.08:00:01.00#ibcon#read 6, iclass 35, count 0 2006.175.08:00:01.00#ibcon#end of sib2, iclass 35, count 0 2006.175.08:00:01.00#ibcon#*after write, iclass 35, count 0 2006.175.08:00:01.00#ibcon#*before return 0, iclass 35, count 0 2006.175.08:00:01.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:00:01.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:00:01.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:00:01.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:00:01.00$vc4f8/vb=2,4 2006.175.08:00:01.00#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.08:00:01.00#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.08:00:01.00#ibcon#ireg 11 cls_cnt 2 2006.175.08:00:01.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:00:01.06#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:00:01.06#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:00:01.06#ibcon#enter wrdev, iclass 37, count 2 2006.175.08:00:01.06#ibcon#first serial, iclass 37, count 2 2006.175.08:00:01.06#ibcon#enter sib2, iclass 37, count 2 2006.175.08:00:01.06#ibcon#flushed, iclass 37, count 2 2006.175.08:00:01.06#ibcon#about to write, iclass 37, count 2 2006.175.08:00:01.06#ibcon#wrote, iclass 37, count 2 2006.175.08:00:01.06#ibcon#about to read 3, iclass 37, count 2 2006.175.08:00:01.08#ibcon#read 3, iclass 37, count 2 2006.175.08:00:01.08#ibcon#about to read 4, iclass 37, count 2 2006.175.08:00:01.08#ibcon#read 4, iclass 37, count 2 2006.175.08:00:01.08#ibcon#about to read 5, iclass 37, count 2 2006.175.08:00:01.08#ibcon#read 5, iclass 37, count 2 2006.175.08:00:01.08#ibcon#about to read 6, iclass 37, count 2 2006.175.08:00:01.08#ibcon#read 6, iclass 37, count 2 2006.175.08:00:01.08#ibcon#end of sib2, iclass 37, count 2 2006.175.08:00:01.08#ibcon#*mode == 0, iclass 37, count 2 2006.175.08:00:01.08#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.08:00:01.08#ibcon#[27=AT02-04\r\n] 2006.175.08:00:01.08#ibcon#*before write, iclass 37, count 2 2006.175.08:00:01.08#ibcon#enter sib2, iclass 37, count 2 2006.175.08:00:01.08#ibcon#flushed, iclass 37, count 2 2006.175.08:00:01.08#ibcon#about to write, iclass 37, count 2 2006.175.08:00:01.08#ibcon#wrote, iclass 37, count 2 2006.175.08:00:01.08#ibcon#about to read 3, iclass 37, count 2 2006.175.08:00:01.11#ibcon#read 3, iclass 37, count 2 2006.175.08:00:01.11#ibcon#about to read 4, iclass 37, count 2 2006.175.08:00:01.11#ibcon#read 4, iclass 37, count 2 2006.175.08:00:01.11#ibcon#about to read 5, iclass 37, count 2 2006.175.08:00:01.11#ibcon#read 5, iclass 37, count 2 2006.175.08:00:01.11#ibcon#about to read 6, iclass 37, count 2 2006.175.08:00:01.11#ibcon#read 6, iclass 37, count 2 2006.175.08:00:01.11#ibcon#end of sib2, iclass 37, count 2 2006.175.08:00:01.11#ibcon#*after write, iclass 37, count 2 2006.175.08:00:01.11#ibcon#*before return 0, iclass 37, count 2 2006.175.08:00:01.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:00:01.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:00:01.11#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.08:00:01.11#ibcon#ireg 7 cls_cnt 0 2006.175.08:00:01.11#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:00:01.23#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:00:01.23#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:00:01.23#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:00:01.23#ibcon#first serial, iclass 37, count 0 2006.175.08:00:01.23#ibcon#enter sib2, iclass 37, count 0 2006.175.08:00:01.23#ibcon#flushed, iclass 37, count 0 2006.175.08:00:01.23#ibcon#about to write, iclass 37, count 0 2006.175.08:00:01.23#ibcon#wrote, iclass 37, count 0 2006.175.08:00:01.23#ibcon#about to read 3, iclass 37, count 0 2006.175.08:00:01.25#ibcon#read 3, iclass 37, count 0 2006.175.08:00:01.25#ibcon#about to read 4, iclass 37, count 0 2006.175.08:00:01.25#ibcon#read 4, iclass 37, count 0 2006.175.08:00:01.25#ibcon#about to read 5, iclass 37, count 0 2006.175.08:00:01.25#ibcon#read 5, iclass 37, count 0 2006.175.08:00:01.25#ibcon#about to read 6, iclass 37, count 0 2006.175.08:00:01.25#ibcon#read 6, iclass 37, count 0 2006.175.08:00:01.25#ibcon#end of sib2, iclass 37, count 0 2006.175.08:00:01.25#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:00:01.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:00:01.25#ibcon#[27=USB\r\n] 2006.175.08:00:01.25#ibcon#*before write, iclass 37, count 0 2006.175.08:00:01.25#ibcon#enter sib2, iclass 37, count 0 2006.175.08:00:01.25#ibcon#flushed, iclass 37, count 0 2006.175.08:00:01.25#ibcon#about to write, iclass 37, count 0 2006.175.08:00:01.25#ibcon#wrote, iclass 37, count 0 2006.175.08:00:01.25#ibcon#about to read 3, iclass 37, count 0 2006.175.08:00:01.28#ibcon#read 3, iclass 37, count 0 2006.175.08:00:01.28#ibcon#about to read 4, iclass 37, count 0 2006.175.08:00:01.28#ibcon#read 4, iclass 37, count 0 2006.175.08:00:01.28#ibcon#about to read 5, iclass 37, count 0 2006.175.08:00:01.28#ibcon#read 5, iclass 37, count 0 2006.175.08:00:01.28#ibcon#about to read 6, iclass 37, count 0 2006.175.08:00:01.28#ibcon#read 6, iclass 37, count 0 2006.175.08:00:01.28#ibcon#end of sib2, iclass 37, count 0 2006.175.08:00:01.28#ibcon#*after write, iclass 37, count 0 2006.175.08:00:01.28#ibcon#*before return 0, iclass 37, count 0 2006.175.08:00:01.28#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:00:01.28#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:00:01.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:00:01.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:00:01.28$vc4f8/vblo=3,656.99 2006.175.08:00:01.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.08:00:01.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.08:00:01.28#ibcon#ireg 17 cls_cnt 0 2006.175.08:00:01.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:00:01.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:00:01.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:00:01.28#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:00:01.28#ibcon#first serial, iclass 39, count 0 2006.175.08:00:01.28#ibcon#enter sib2, iclass 39, count 0 2006.175.08:00:01.28#ibcon#flushed, iclass 39, count 0 2006.175.08:00:01.28#ibcon#about to write, iclass 39, count 0 2006.175.08:00:01.28#ibcon#wrote, iclass 39, count 0 2006.175.08:00:01.28#ibcon#about to read 3, iclass 39, count 0 2006.175.08:00:01.30#ibcon#read 3, iclass 39, count 0 2006.175.08:00:01.30#ibcon#about to read 4, iclass 39, count 0 2006.175.08:00:01.30#ibcon#read 4, iclass 39, count 0 2006.175.08:00:01.30#ibcon#about to read 5, iclass 39, count 0 2006.175.08:00:01.30#ibcon#read 5, iclass 39, count 0 2006.175.08:00:01.30#ibcon#about to read 6, iclass 39, count 0 2006.175.08:00:01.30#ibcon#read 6, iclass 39, count 0 2006.175.08:00:01.30#ibcon#end of sib2, iclass 39, count 0 2006.175.08:00:01.30#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:00:01.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:00:01.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:00:01.30#ibcon#*before write, iclass 39, count 0 2006.175.08:00:01.30#ibcon#enter sib2, iclass 39, count 0 2006.175.08:00:01.30#ibcon#flushed, iclass 39, count 0 2006.175.08:00:01.30#ibcon#about to write, iclass 39, count 0 2006.175.08:00:01.30#ibcon#wrote, iclass 39, count 0 2006.175.08:00:01.30#ibcon#about to read 3, iclass 39, count 0 2006.175.08:00:01.34#ibcon#read 3, iclass 39, count 0 2006.175.08:00:01.34#ibcon#about to read 4, iclass 39, count 0 2006.175.08:00:01.34#ibcon#read 4, iclass 39, count 0 2006.175.08:00:01.34#ibcon#about to read 5, iclass 39, count 0 2006.175.08:00:01.34#ibcon#read 5, iclass 39, count 0 2006.175.08:00:01.34#ibcon#about to read 6, iclass 39, count 0 2006.175.08:00:01.34#ibcon#read 6, iclass 39, count 0 2006.175.08:00:01.34#ibcon#end of sib2, iclass 39, count 0 2006.175.08:00:01.34#ibcon#*after write, iclass 39, count 0 2006.175.08:00:01.34#ibcon#*before return 0, iclass 39, count 0 2006.175.08:00:01.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:00:01.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:00:01.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:00:01.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:00:01.34$vc4f8/vb=3,4 2006.175.08:00:01.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.08:00:01.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.08:00:01.34#ibcon#ireg 11 cls_cnt 2 2006.175.08:00:01.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:00:01.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:00:01.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:00:01.40#ibcon#enter wrdev, iclass 3, count 2 2006.175.08:00:01.40#ibcon#first serial, iclass 3, count 2 2006.175.08:00:01.40#ibcon#enter sib2, iclass 3, count 2 2006.175.08:00:01.40#ibcon#flushed, iclass 3, count 2 2006.175.08:00:01.40#ibcon#about to write, iclass 3, count 2 2006.175.08:00:01.40#ibcon#wrote, iclass 3, count 2 2006.175.08:00:01.40#ibcon#about to read 3, iclass 3, count 2 2006.175.08:00:01.42#ibcon#read 3, iclass 3, count 2 2006.175.08:00:01.42#ibcon#about to read 4, iclass 3, count 2 2006.175.08:00:01.42#ibcon#read 4, iclass 3, count 2 2006.175.08:00:01.42#ibcon#about to read 5, iclass 3, count 2 2006.175.08:00:01.42#ibcon#read 5, iclass 3, count 2 2006.175.08:00:01.42#ibcon#about to read 6, iclass 3, count 2 2006.175.08:00:01.42#ibcon#read 6, iclass 3, count 2 2006.175.08:00:01.42#ibcon#end of sib2, iclass 3, count 2 2006.175.08:00:01.42#ibcon#*mode == 0, iclass 3, count 2 2006.175.08:00:01.42#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.08:00:01.42#ibcon#[27=AT03-04\r\n] 2006.175.08:00:01.42#ibcon#*before write, iclass 3, count 2 2006.175.08:00:01.42#ibcon#enter sib2, iclass 3, count 2 2006.175.08:00:01.42#ibcon#flushed, iclass 3, count 2 2006.175.08:00:01.42#ibcon#about to write, iclass 3, count 2 2006.175.08:00:01.42#ibcon#wrote, iclass 3, count 2 2006.175.08:00:01.42#ibcon#about to read 3, iclass 3, count 2 2006.175.08:00:01.45#ibcon#read 3, iclass 3, count 2 2006.175.08:00:01.45#ibcon#about to read 4, iclass 3, count 2 2006.175.08:00:01.45#ibcon#read 4, iclass 3, count 2 2006.175.08:00:01.45#ibcon#about to read 5, iclass 3, count 2 2006.175.08:00:01.45#ibcon#read 5, iclass 3, count 2 2006.175.08:00:01.45#ibcon#about to read 6, iclass 3, count 2 2006.175.08:00:01.45#ibcon#read 6, iclass 3, count 2 2006.175.08:00:01.45#ibcon#end of sib2, iclass 3, count 2 2006.175.08:00:01.45#ibcon#*after write, iclass 3, count 2 2006.175.08:00:01.45#ibcon#*before return 0, iclass 3, count 2 2006.175.08:00:01.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:00:01.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:00:01.45#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.08:00:01.45#ibcon#ireg 7 cls_cnt 0 2006.175.08:00:01.45#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:00:01.57#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:00:01.57#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:00:01.57#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:00:01.57#ibcon#first serial, iclass 3, count 0 2006.175.08:00:01.57#ibcon#enter sib2, iclass 3, count 0 2006.175.08:00:01.57#ibcon#flushed, iclass 3, count 0 2006.175.08:00:01.57#ibcon#about to write, iclass 3, count 0 2006.175.08:00:01.57#ibcon#wrote, iclass 3, count 0 2006.175.08:00:01.57#ibcon#about to read 3, iclass 3, count 0 2006.175.08:00:01.59#ibcon#read 3, iclass 3, count 0 2006.175.08:00:01.59#ibcon#about to read 4, iclass 3, count 0 2006.175.08:00:01.59#ibcon#read 4, iclass 3, count 0 2006.175.08:00:01.59#ibcon#about to read 5, iclass 3, count 0 2006.175.08:00:01.59#ibcon#read 5, iclass 3, count 0 2006.175.08:00:01.59#ibcon#about to read 6, iclass 3, count 0 2006.175.08:00:01.59#ibcon#read 6, iclass 3, count 0 2006.175.08:00:01.59#ibcon#end of sib2, iclass 3, count 0 2006.175.08:00:01.59#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:00:01.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:00:01.59#ibcon#[27=USB\r\n] 2006.175.08:00:01.59#ibcon#*before write, iclass 3, count 0 2006.175.08:00:01.59#ibcon#enter sib2, iclass 3, count 0 2006.175.08:00:01.59#ibcon#flushed, iclass 3, count 0 2006.175.08:00:01.59#ibcon#about to write, iclass 3, count 0 2006.175.08:00:01.59#ibcon#wrote, iclass 3, count 0 2006.175.08:00:01.59#ibcon#about to read 3, iclass 3, count 0 2006.175.08:00:01.62#ibcon#read 3, iclass 3, count 0 2006.175.08:00:01.62#ibcon#about to read 4, iclass 3, count 0 2006.175.08:00:01.62#ibcon#read 4, iclass 3, count 0 2006.175.08:00:01.62#ibcon#about to read 5, iclass 3, count 0 2006.175.08:00:01.62#ibcon#read 5, iclass 3, count 0 2006.175.08:00:01.62#ibcon#about to read 6, iclass 3, count 0 2006.175.08:00:01.62#ibcon#read 6, iclass 3, count 0 2006.175.08:00:01.62#ibcon#end of sib2, iclass 3, count 0 2006.175.08:00:01.62#ibcon#*after write, iclass 3, count 0 2006.175.08:00:01.62#ibcon#*before return 0, iclass 3, count 0 2006.175.08:00:01.62#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:00:01.62#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:00:01.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:00:01.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:00:01.62$vc4f8/vblo=4,712.99 2006.175.08:00:01.62#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.08:00:01.62#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.08:00:01.62#ibcon#ireg 17 cls_cnt 0 2006.175.08:00:01.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:00:01.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:00:01.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:00:01.62#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:00:01.62#ibcon#first serial, iclass 5, count 0 2006.175.08:00:01.62#ibcon#enter sib2, iclass 5, count 0 2006.175.08:00:01.62#ibcon#flushed, iclass 5, count 0 2006.175.08:00:01.62#ibcon#about to write, iclass 5, count 0 2006.175.08:00:01.62#ibcon#wrote, iclass 5, count 0 2006.175.08:00:01.62#ibcon#about to read 3, iclass 5, count 0 2006.175.08:00:01.64#ibcon#read 3, iclass 5, count 0 2006.175.08:00:01.64#ibcon#about to read 4, iclass 5, count 0 2006.175.08:00:01.64#ibcon#read 4, iclass 5, count 0 2006.175.08:00:01.64#ibcon#about to read 5, iclass 5, count 0 2006.175.08:00:01.64#ibcon#read 5, iclass 5, count 0 2006.175.08:00:01.64#ibcon#about to read 6, iclass 5, count 0 2006.175.08:00:01.64#ibcon#read 6, iclass 5, count 0 2006.175.08:00:01.64#ibcon#end of sib2, iclass 5, count 0 2006.175.08:00:01.64#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:00:01.64#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:00:01.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:00:01.64#ibcon#*before write, iclass 5, count 0 2006.175.08:00:01.64#ibcon#enter sib2, iclass 5, count 0 2006.175.08:00:01.64#ibcon#flushed, iclass 5, count 0 2006.175.08:00:01.64#ibcon#about to write, iclass 5, count 0 2006.175.08:00:01.64#ibcon#wrote, iclass 5, count 0 2006.175.08:00:01.64#ibcon#about to read 3, iclass 5, count 0 2006.175.08:00:01.68#ibcon#read 3, iclass 5, count 0 2006.175.08:00:01.68#ibcon#about to read 4, iclass 5, count 0 2006.175.08:00:01.68#ibcon#read 4, iclass 5, count 0 2006.175.08:00:01.68#ibcon#about to read 5, iclass 5, count 0 2006.175.08:00:01.68#ibcon#read 5, iclass 5, count 0 2006.175.08:00:01.68#ibcon#about to read 6, iclass 5, count 0 2006.175.08:00:01.68#ibcon#read 6, iclass 5, count 0 2006.175.08:00:01.68#ibcon#end of sib2, iclass 5, count 0 2006.175.08:00:01.68#ibcon#*after write, iclass 5, count 0 2006.175.08:00:01.68#ibcon#*before return 0, iclass 5, count 0 2006.175.08:00:01.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:00:01.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:00:01.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:00:01.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:00:01.68$vc4f8/vb=4,4 2006.175.08:00:01.68#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.08:00:01.68#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.08:00:01.68#ibcon#ireg 11 cls_cnt 2 2006.175.08:00:01.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:00:01.74#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:00:01.74#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:00:01.74#ibcon#enter wrdev, iclass 7, count 2 2006.175.08:00:01.74#ibcon#first serial, iclass 7, count 2 2006.175.08:00:01.74#ibcon#enter sib2, iclass 7, count 2 2006.175.08:00:01.74#ibcon#flushed, iclass 7, count 2 2006.175.08:00:01.74#ibcon#about to write, iclass 7, count 2 2006.175.08:00:01.74#ibcon#wrote, iclass 7, count 2 2006.175.08:00:01.74#ibcon#about to read 3, iclass 7, count 2 2006.175.08:00:01.76#ibcon#read 3, iclass 7, count 2 2006.175.08:00:01.76#ibcon#about to read 4, iclass 7, count 2 2006.175.08:00:01.76#ibcon#read 4, iclass 7, count 2 2006.175.08:00:01.76#ibcon#about to read 5, iclass 7, count 2 2006.175.08:00:01.76#ibcon#read 5, iclass 7, count 2 2006.175.08:00:01.76#ibcon#about to read 6, iclass 7, count 2 2006.175.08:00:01.76#ibcon#read 6, iclass 7, count 2 2006.175.08:00:01.76#ibcon#end of sib2, iclass 7, count 2 2006.175.08:00:01.76#ibcon#*mode == 0, iclass 7, count 2 2006.175.08:00:01.76#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.08:00:01.76#ibcon#[27=AT04-04\r\n] 2006.175.08:00:01.76#ibcon#*before write, iclass 7, count 2 2006.175.08:00:01.76#ibcon#enter sib2, iclass 7, count 2 2006.175.08:00:01.76#ibcon#flushed, iclass 7, count 2 2006.175.08:00:01.76#ibcon#about to write, iclass 7, count 2 2006.175.08:00:01.76#ibcon#wrote, iclass 7, count 2 2006.175.08:00:01.76#ibcon#about to read 3, iclass 7, count 2 2006.175.08:00:01.79#ibcon#read 3, iclass 7, count 2 2006.175.08:00:01.79#ibcon#about to read 4, iclass 7, count 2 2006.175.08:00:01.79#ibcon#read 4, iclass 7, count 2 2006.175.08:00:01.79#ibcon#about to read 5, iclass 7, count 2 2006.175.08:00:01.79#ibcon#read 5, iclass 7, count 2 2006.175.08:00:01.79#ibcon#about to read 6, iclass 7, count 2 2006.175.08:00:01.79#ibcon#read 6, iclass 7, count 2 2006.175.08:00:01.79#ibcon#end of sib2, iclass 7, count 2 2006.175.08:00:01.79#ibcon#*after write, iclass 7, count 2 2006.175.08:00:01.79#ibcon#*before return 0, iclass 7, count 2 2006.175.08:00:01.79#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:00:01.79#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:00:01.79#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.08:00:01.79#ibcon#ireg 7 cls_cnt 0 2006.175.08:00:01.79#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:00:01.91#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:00:01.91#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:00:01.91#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:00:01.91#ibcon#first serial, iclass 7, count 0 2006.175.08:00:01.91#ibcon#enter sib2, iclass 7, count 0 2006.175.08:00:01.91#ibcon#flushed, iclass 7, count 0 2006.175.08:00:01.91#ibcon#about to write, iclass 7, count 0 2006.175.08:00:01.91#ibcon#wrote, iclass 7, count 0 2006.175.08:00:01.91#ibcon#about to read 3, iclass 7, count 0 2006.175.08:00:01.93#ibcon#read 3, iclass 7, count 0 2006.175.08:00:01.93#ibcon#about to read 4, iclass 7, count 0 2006.175.08:00:01.93#ibcon#read 4, iclass 7, count 0 2006.175.08:00:01.93#ibcon#about to read 5, iclass 7, count 0 2006.175.08:00:01.93#ibcon#read 5, iclass 7, count 0 2006.175.08:00:01.93#ibcon#about to read 6, iclass 7, count 0 2006.175.08:00:01.93#ibcon#read 6, iclass 7, count 0 2006.175.08:00:01.93#ibcon#end of sib2, iclass 7, count 0 2006.175.08:00:01.93#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:00:01.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:00:01.93#ibcon#[27=USB\r\n] 2006.175.08:00:01.93#ibcon#*before write, iclass 7, count 0 2006.175.08:00:01.93#ibcon#enter sib2, iclass 7, count 0 2006.175.08:00:01.93#ibcon#flushed, iclass 7, count 0 2006.175.08:00:01.93#ibcon#about to write, iclass 7, count 0 2006.175.08:00:01.93#ibcon#wrote, iclass 7, count 0 2006.175.08:00:01.93#ibcon#about to read 3, iclass 7, count 0 2006.175.08:00:01.96#ibcon#read 3, iclass 7, count 0 2006.175.08:00:01.96#ibcon#about to read 4, iclass 7, count 0 2006.175.08:00:01.96#ibcon#read 4, iclass 7, count 0 2006.175.08:00:01.96#ibcon#about to read 5, iclass 7, count 0 2006.175.08:00:01.96#ibcon#read 5, iclass 7, count 0 2006.175.08:00:01.96#ibcon#about to read 6, iclass 7, count 0 2006.175.08:00:01.96#ibcon#read 6, iclass 7, count 0 2006.175.08:00:01.96#ibcon#end of sib2, iclass 7, count 0 2006.175.08:00:01.96#ibcon#*after write, iclass 7, count 0 2006.175.08:00:01.96#ibcon#*before return 0, iclass 7, count 0 2006.175.08:00:01.96#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:00:01.96#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:00:01.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:00:01.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:00:01.96$vc4f8/vblo=5,744.99 2006.175.08:00:01.96#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.08:00:01.96#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.08:00:01.96#ibcon#ireg 17 cls_cnt 0 2006.175.08:00:01.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:00:01.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:00:01.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:00:01.96#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:00:01.96#ibcon#first serial, iclass 11, count 0 2006.175.08:00:01.96#ibcon#enter sib2, iclass 11, count 0 2006.175.08:00:01.96#ibcon#flushed, iclass 11, count 0 2006.175.08:00:01.96#ibcon#about to write, iclass 11, count 0 2006.175.08:00:01.96#ibcon#wrote, iclass 11, count 0 2006.175.08:00:01.96#ibcon#about to read 3, iclass 11, count 0 2006.175.08:00:01.98#ibcon#read 3, iclass 11, count 0 2006.175.08:00:01.98#ibcon#about to read 4, iclass 11, count 0 2006.175.08:00:01.98#ibcon#read 4, iclass 11, count 0 2006.175.08:00:01.98#ibcon#about to read 5, iclass 11, count 0 2006.175.08:00:01.98#ibcon#read 5, iclass 11, count 0 2006.175.08:00:01.98#ibcon#about to read 6, iclass 11, count 0 2006.175.08:00:01.98#ibcon#read 6, iclass 11, count 0 2006.175.08:00:01.98#ibcon#end of sib2, iclass 11, count 0 2006.175.08:00:01.98#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:00:01.98#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:00:01.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:00:01.98#ibcon#*before write, iclass 11, count 0 2006.175.08:00:01.98#ibcon#enter sib2, iclass 11, count 0 2006.175.08:00:01.98#ibcon#flushed, iclass 11, count 0 2006.175.08:00:01.98#ibcon#about to write, iclass 11, count 0 2006.175.08:00:01.98#ibcon#wrote, iclass 11, count 0 2006.175.08:00:01.98#ibcon#about to read 3, iclass 11, count 0 2006.175.08:00:02.02#ibcon#read 3, iclass 11, count 0 2006.175.08:00:02.02#ibcon#about to read 4, iclass 11, count 0 2006.175.08:00:02.02#ibcon#read 4, iclass 11, count 0 2006.175.08:00:02.02#ibcon#about to read 5, iclass 11, count 0 2006.175.08:00:02.02#ibcon#read 5, iclass 11, count 0 2006.175.08:00:02.02#ibcon#about to read 6, iclass 11, count 0 2006.175.08:00:02.02#ibcon#read 6, iclass 11, count 0 2006.175.08:00:02.02#ibcon#end of sib2, iclass 11, count 0 2006.175.08:00:02.02#ibcon#*after write, iclass 11, count 0 2006.175.08:00:02.02#ibcon#*before return 0, iclass 11, count 0 2006.175.08:00:02.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:00:02.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:00:02.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:00:02.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:00:02.02$vc4f8/vb=5,4 2006.175.08:00:02.02#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.08:00:02.02#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.08:00:02.02#ibcon#ireg 11 cls_cnt 2 2006.175.08:00:02.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:00:02.08#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:00:02.08#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:00:02.08#ibcon#enter wrdev, iclass 13, count 2 2006.175.08:00:02.08#ibcon#first serial, iclass 13, count 2 2006.175.08:00:02.08#ibcon#enter sib2, iclass 13, count 2 2006.175.08:00:02.08#ibcon#flushed, iclass 13, count 2 2006.175.08:00:02.08#ibcon#about to write, iclass 13, count 2 2006.175.08:00:02.08#ibcon#wrote, iclass 13, count 2 2006.175.08:00:02.08#ibcon#about to read 3, iclass 13, count 2 2006.175.08:00:02.10#ibcon#read 3, iclass 13, count 2 2006.175.08:00:02.10#ibcon#about to read 4, iclass 13, count 2 2006.175.08:00:02.10#ibcon#read 4, iclass 13, count 2 2006.175.08:00:02.10#ibcon#about to read 5, iclass 13, count 2 2006.175.08:00:02.10#ibcon#read 5, iclass 13, count 2 2006.175.08:00:02.10#ibcon#about to read 6, iclass 13, count 2 2006.175.08:00:02.10#ibcon#read 6, iclass 13, count 2 2006.175.08:00:02.10#ibcon#end of sib2, iclass 13, count 2 2006.175.08:00:02.10#ibcon#*mode == 0, iclass 13, count 2 2006.175.08:00:02.10#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.08:00:02.10#ibcon#[27=AT05-04\r\n] 2006.175.08:00:02.10#ibcon#*before write, iclass 13, count 2 2006.175.08:00:02.10#ibcon#enter sib2, iclass 13, count 2 2006.175.08:00:02.10#ibcon#flushed, iclass 13, count 2 2006.175.08:00:02.10#ibcon#about to write, iclass 13, count 2 2006.175.08:00:02.10#ibcon#wrote, iclass 13, count 2 2006.175.08:00:02.10#ibcon#about to read 3, iclass 13, count 2 2006.175.08:00:02.13#ibcon#read 3, iclass 13, count 2 2006.175.08:00:02.13#ibcon#about to read 4, iclass 13, count 2 2006.175.08:00:02.13#ibcon#read 4, iclass 13, count 2 2006.175.08:00:02.13#ibcon#about to read 5, iclass 13, count 2 2006.175.08:00:02.13#ibcon#read 5, iclass 13, count 2 2006.175.08:00:02.13#ibcon#about to read 6, iclass 13, count 2 2006.175.08:00:02.13#ibcon#read 6, iclass 13, count 2 2006.175.08:00:02.13#ibcon#end of sib2, iclass 13, count 2 2006.175.08:00:02.13#ibcon#*after write, iclass 13, count 2 2006.175.08:00:02.13#ibcon#*before return 0, iclass 13, count 2 2006.175.08:00:02.13#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:00:02.13#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:00:02.13#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.08:00:02.13#ibcon#ireg 7 cls_cnt 0 2006.175.08:00:02.13#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:00:02.25#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:00:02.25#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:00:02.25#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:00:02.25#ibcon#first serial, iclass 13, count 0 2006.175.08:00:02.25#ibcon#enter sib2, iclass 13, count 0 2006.175.08:00:02.25#ibcon#flushed, iclass 13, count 0 2006.175.08:00:02.25#ibcon#about to write, iclass 13, count 0 2006.175.08:00:02.25#ibcon#wrote, iclass 13, count 0 2006.175.08:00:02.25#ibcon#about to read 3, iclass 13, count 0 2006.175.08:00:02.27#ibcon#read 3, iclass 13, count 0 2006.175.08:00:02.27#ibcon#about to read 4, iclass 13, count 0 2006.175.08:00:02.27#ibcon#read 4, iclass 13, count 0 2006.175.08:00:02.27#ibcon#about to read 5, iclass 13, count 0 2006.175.08:00:02.27#ibcon#read 5, iclass 13, count 0 2006.175.08:00:02.27#ibcon#about to read 6, iclass 13, count 0 2006.175.08:00:02.27#ibcon#read 6, iclass 13, count 0 2006.175.08:00:02.27#ibcon#end of sib2, iclass 13, count 0 2006.175.08:00:02.27#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:00:02.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:00:02.27#ibcon#[27=USB\r\n] 2006.175.08:00:02.27#ibcon#*before write, iclass 13, count 0 2006.175.08:00:02.27#ibcon#enter sib2, iclass 13, count 0 2006.175.08:00:02.27#ibcon#flushed, iclass 13, count 0 2006.175.08:00:02.27#ibcon#about to write, iclass 13, count 0 2006.175.08:00:02.27#ibcon#wrote, iclass 13, count 0 2006.175.08:00:02.27#ibcon#about to read 3, iclass 13, count 0 2006.175.08:00:02.30#ibcon#read 3, iclass 13, count 0 2006.175.08:00:02.30#ibcon#about to read 4, iclass 13, count 0 2006.175.08:00:02.30#ibcon#read 4, iclass 13, count 0 2006.175.08:00:02.30#ibcon#about to read 5, iclass 13, count 0 2006.175.08:00:02.30#ibcon#read 5, iclass 13, count 0 2006.175.08:00:02.30#ibcon#about to read 6, iclass 13, count 0 2006.175.08:00:02.30#ibcon#read 6, iclass 13, count 0 2006.175.08:00:02.30#ibcon#end of sib2, iclass 13, count 0 2006.175.08:00:02.30#ibcon#*after write, iclass 13, count 0 2006.175.08:00:02.30#ibcon#*before return 0, iclass 13, count 0 2006.175.08:00:02.30#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:00:02.30#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:00:02.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:00:02.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:00:02.30$vc4f8/vblo=6,752.99 2006.175.08:00:02.30#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.08:00:02.30#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.08:00:02.30#ibcon#ireg 17 cls_cnt 0 2006.175.08:00:02.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:00:02.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:00:02.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:00:02.30#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:00:02.30#ibcon#first serial, iclass 15, count 0 2006.175.08:00:02.30#ibcon#enter sib2, iclass 15, count 0 2006.175.08:00:02.30#ibcon#flushed, iclass 15, count 0 2006.175.08:00:02.30#ibcon#about to write, iclass 15, count 0 2006.175.08:00:02.30#ibcon#wrote, iclass 15, count 0 2006.175.08:00:02.30#ibcon#about to read 3, iclass 15, count 0 2006.175.08:00:02.32#ibcon#read 3, iclass 15, count 0 2006.175.08:00:02.32#ibcon#about to read 4, iclass 15, count 0 2006.175.08:00:02.32#ibcon#read 4, iclass 15, count 0 2006.175.08:00:02.32#ibcon#about to read 5, iclass 15, count 0 2006.175.08:00:02.32#ibcon#read 5, iclass 15, count 0 2006.175.08:00:02.32#ibcon#about to read 6, iclass 15, count 0 2006.175.08:00:02.32#ibcon#read 6, iclass 15, count 0 2006.175.08:00:02.32#ibcon#end of sib2, iclass 15, count 0 2006.175.08:00:02.32#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:00:02.32#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:00:02.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:00:02.32#ibcon#*before write, iclass 15, count 0 2006.175.08:00:02.32#ibcon#enter sib2, iclass 15, count 0 2006.175.08:00:02.32#ibcon#flushed, iclass 15, count 0 2006.175.08:00:02.32#ibcon#about to write, iclass 15, count 0 2006.175.08:00:02.32#ibcon#wrote, iclass 15, count 0 2006.175.08:00:02.32#ibcon#about to read 3, iclass 15, count 0 2006.175.08:00:02.36#ibcon#read 3, iclass 15, count 0 2006.175.08:00:02.36#ibcon#about to read 4, iclass 15, count 0 2006.175.08:00:02.36#ibcon#read 4, iclass 15, count 0 2006.175.08:00:02.36#ibcon#about to read 5, iclass 15, count 0 2006.175.08:00:02.36#ibcon#read 5, iclass 15, count 0 2006.175.08:00:02.36#ibcon#about to read 6, iclass 15, count 0 2006.175.08:00:02.36#ibcon#read 6, iclass 15, count 0 2006.175.08:00:02.36#ibcon#end of sib2, iclass 15, count 0 2006.175.08:00:02.36#ibcon#*after write, iclass 15, count 0 2006.175.08:00:02.36#ibcon#*before return 0, iclass 15, count 0 2006.175.08:00:02.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:00:02.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:00:02.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:00:02.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:00:02.36$vc4f8/vb=6,4 2006.175.08:00:02.36#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.08:00:02.36#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.08:00:02.36#ibcon#ireg 11 cls_cnt 2 2006.175.08:00:02.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:00:02.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:00:02.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:00:02.42#ibcon#enter wrdev, iclass 17, count 2 2006.175.08:00:02.42#ibcon#first serial, iclass 17, count 2 2006.175.08:00:02.42#ibcon#enter sib2, iclass 17, count 2 2006.175.08:00:02.42#ibcon#flushed, iclass 17, count 2 2006.175.08:00:02.42#ibcon#about to write, iclass 17, count 2 2006.175.08:00:02.42#ibcon#wrote, iclass 17, count 2 2006.175.08:00:02.42#ibcon#about to read 3, iclass 17, count 2 2006.175.08:00:02.44#ibcon#read 3, iclass 17, count 2 2006.175.08:00:02.44#ibcon#about to read 4, iclass 17, count 2 2006.175.08:00:02.44#ibcon#read 4, iclass 17, count 2 2006.175.08:00:02.44#ibcon#about to read 5, iclass 17, count 2 2006.175.08:00:02.44#ibcon#read 5, iclass 17, count 2 2006.175.08:00:02.44#ibcon#about to read 6, iclass 17, count 2 2006.175.08:00:02.44#ibcon#read 6, iclass 17, count 2 2006.175.08:00:02.44#ibcon#end of sib2, iclass 17, count 2 2006.175.08:00:02.44#ibcon#*mode == 0, iclass 17, count 2 2006.175.08:00:02.44#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.08:00:02.44#ibcon#[27=AT06-04\r\n] 2006.175.08:00:02.44#ibcon#*before write, iclass 17, count 2 2006.175.08:00:02.44#ibcon#enter sib2, iclass 17, count 2 2006.175.08:00:02.44#ibcon#flushed, iclass 17, count 2 2006.175.08:00:02.44#ibcon#about to write, iclass 17, count 2 2006.175.08:00:02.44#ibcon#wrote, iclass 17, count 2 2006.175.08:00:02.44#ibcon#about to read 3, iclass 17, count 2 2006.175.08:00:02.47#ibcon#read 3, iclass 17, count 2 2006.175.08:00:02.47#ibcon#about to read 4, iclass 17, count 2 2006.175.08:00:02.47#ibcon#read 4, iclass 17, count 2 2006.175.08:00:02.47#ibcon#about to read 5, iclass 17, count 2 2006.175.08:00:02.47#ibcon#read 5, iclass 17, count 2 2006.175.08:00:02.47#ibcon#about to read 6, iclass 17, count 2 2006.175.08:00:02.47#ibcon#read 6, iclass 17, count 2 2006.175.08:00:02.47#ibcon#end of sib2, iclass 17, count 2 2006.175.08:00:02.47#ibcon#*after write, iclass 17, count 2 2006.175.08:00:02.47#ibcon#*before return 0, iclass 17, count 2 2006.175.08:00:02.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:00:02.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:00:02.47#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.08:00:02.47#ibcon#ireg 7 cls_cnt 0 2006.175.08:00:02.47#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:00:02.59#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:00:02.59#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:00:02.59#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:00:02.59#ibcon#first serial, iclass 17, count 0 2006.175.08:00:02.59#ibcon#enter sib2, iclass 17, count 0 2006.175.08:00:02.59#ibcon#flushed, iclass 17, count 0 2006.175.08:00:02.59#ibcon#about to write, iclass 17, count 0 2006.175.08:00:02.59#ibcon#wrote, iclass 17, count 0 2006.175.08:00:02.59#ibcon#about to read 3, iclass 17, count 0 2006.175.08:00:02.61#ibcon#read 3, iclass 17, count 0 2006.175.08:00:02.61#ibcon#about to read 4, iclass 17, count 0 2006.175.08:00:02.61#ibcon#read 4, iclass 17, count 0 2006.175.08:00:02.61#ibcon#about to read 5, iclass 17, count 0 2006.175.08:00:02.61#ibcon#read 5, iclass 17, count 0 2006.175.08:00:02.61#ibcon#about to read 6, iclass 17, count 0 2006.175.08:00:02.61#ibcon#read 6, iclass 17, count 0 2006.175.08:00:02.61#ibcon#end of sib2, iclass 17, count 0 2006.175.08:00:02.61#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:00:02.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:00:02.61#ibcon#[27=USB\r\n] 2006.175.08:00:02.61#ibcon#*before write, iclass 17, count 0 2006.175.08:00:02.61#ibcon#enter sib2, iclass 17, count 0 2006.175.08:00:02.61#ibcon#flushed, iclass 17, count 0 2006.175.08:00:02.61#ibcon#about to write, iclass 17, count 0 2006.175.08:00:02.61#ibcon#wrote, iclass 17, count 0 2006.175.08:00:02.61#ibcon#about to read 3, iclass 17, count 0 2006.175.08:00:02.64#ibcon#read 3, iclass 17, count 0 2006.175.08:00:02.64#ibcon#about to read 4, iclass 17, count 0 2006.175.08:00:02.64#ibcon#read 4, iclass 17, count 0 2006.175.08:00:02.64#ibcon#about to read 5, iclass 17, count 0 2006.175.08:00:02.64#ibcon#read 5, iclass 17, count 0 2006.175.08:00:02.64#ibcon#about to read 6, iclass 17, count 0 2006.175.08:00:02.64#ibcon#read 6, iclass 17, count 0 2006.175.08:00:02.64#ibcon#end of sib2, iclass 17, count 0 2006.175.08:00:02.64#ibcon#*after write, iclass 17, count 0 2006.175.08:00:02.64#ibcon#*before return 0, iclass 17, count 0 2006.175.08:00:02.64#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:00:02.64#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:00:02.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:00:02.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:00:02.64$vc4f8/vabw=wide 2006.175.08:00:02.64#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.08:00:02.64#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.08:00:02.64#ibcon#ireg 8 cls_cnt 0 2006.175.08:00:02.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:00:02.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:00:02.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:00:02.64#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:00:02.64#ibcon#first serial, iclass 19, count 0 2006.175.08:00:02.64#ibcon#enter sib2, iclass 19, count 0 2006.175.08:00:02.64#ibcon#flushed, iclass 19, count 0 2006.175.08:00:02.64#ibcon#about to write, iclass 19, count 0 2006.175.08:00:02.64#ibcon#wrote, iclass 19, count 0 2006.175.08:00:02.64#ibcon#about to read 3, iclass 19, count 0 2006.175.08:00:02.66#ibcon#read 3, iclass 19, count 0 2006.175.08:00:02.66#ibcon#about to read 4, iclass 19, count 0 2006.175.08:00:02.66#ibcon#read 4, iclass 19, count 0 2006.175.08:00:02.66#ibcon#about to read 5, iclass 19, count 0 2006.175.08:00:02.66#ibcon#read 5, iclass 19, count 0 2006.175.08:00:02.66#ibcon#about to read 6, iclass 19, count 0 2006.175.08:00:02.66#ibcon#read 6, iclass 19, count 0 2006.175.08:00:02.66#ibcon#end of sib2, iclass 19, count 0 2006.175.08:00:02.66#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:00:02.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:00:02.66#ibcon#[25=BW32\r\n] 2006.175.08:00:02.66#ibcon#*before write, iclass 19, count 0 2006.175.08:00:02.66#ibcon#enter sib2, iclass 19, count 0 2006.175.08:00:02.66#ibcon#flushed, iclass 19, count 0 2006.175.08:00:02.66#ibcon#about to write, iclass 19, count 0 2006.175.08:00:02.66#ibcon#wrote, iclass 19, count 0 2006.175.08:00:02.66#ibcon#about to read 3, iclass 19, count 0 2006.175.08:00:02.69#ibcon#read 3, iclass 19, count 0 2006.175.08:00:02.69#ibcon#about to read 4, iclass 19, count 0 2006.175.08:00:02.69#ibcon#read 4, iclass 19, count 0 2006.175.08:00:02.69#ibcon#about to read 5, iclass 19, count 0 2006.175.08:00:02.69#ibcon#read 5, iclass 19, count 0 2006.175.08:00:02.69#ibcon#about to read 6, iclass 19, count 0 2006.175.08:00:02.69#ibcon#read 6, iclass 19, count 0 2006.175.08:00:02.69#ibcon#end of sib2, iclass 19, count 0 2006.175.08:00:02.69#ibcon#*after write, iclass 19, count 0 2006.175.08:00:02.69#ibcon#*before return 0, iclass 19, count 0 2006.175.08:00:02.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:00:02.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:00:02.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:00:02.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:00:02.69$vc4f8/vbbw=wide 2006.175.08:00:02.69#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.08:00:02.69#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.08:00:02.69#ibcon#ireg 8 cls_cnt 0 2006.175.08:00:02.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:00:02.76#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:00:02.76#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:00:02.76#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:00:02.76#ibcon#first serial, iclass 21, count 0 2006.175.08:00:02.76#ibcon#enter sib2, iclass 21, count 0 2006.175.08:00:02.76#ibcon#flushed, iclass 21, count 0 2006.175.08:00:02.76#ibcon#about to write, iclass 21, count 0 2006.175.08:00:02.76#ibcon#wrote, iclass 21, count 0 2006.175.08:00:02.76#ibcon#about to read 3, iclass 21, count 0 2006.175.08:00:02.78#ibcon#read 3, iclass 21, count 0 2006.175.08:00:02.78#ibcon#about to read 4, iclass 21, count 0 2006.175.08:00:02.78#ibcon#read 4, iclass 21, count 0 2006.175.08:00:02.78#ibcon#about to read 5, iclass 21, count 0 2006.175.08:00:02.78#ibcon#read 5, iclass 21, count 0 2006.175.08:00:02.78#ibcon#about to read 6, iclass 21, count 0 2006.175.08:00:02.78#ibcon#read 6, iclass 21, count 0 2006.175.08:00:02.78#ibcon#end of sib2, iclass 21, count 0 2006.175.08:00:02.78#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:00:02.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:00:02.78#ibcon#[27=BW32\r\n] 2006.175.08:00:02.78#ibcon#*before write, iclass 21, count 0 2006.175.08:00:02.78#ibcon#enter sib2, iclass 21, count 0 2006.175.08:00:02.78#ibcon#flushed, iclass 21, count 0 2006.175.08:00:02.78#ibcon#about to write, iclass 21, count 0 2006.175.08:00:02.78#ibcon#wrote, iclass 21, count 0 2006.175.08:00:02.78#ibcon#about to read 3, iclass 21, count 0 2006.175.08:00:02.81#ibcon#read 3, iclass 21, count 0 2006.175.08:00:02.81#ibcon#about to read 4, iclass 21, count 0 2006.175.08:00:02.81#ibcon#read 4, iclass 21, count 0 2006.175.08:00:02.81#ibcon#about to read 5, iclass 21, count 0 2006.175.08:00:02.81#ibcon#read 5, iclass 21, count 0 2006.175.08:00:02.81#ibcon#about to read 6, iclass 21, count 0 2006.175.08:00:02.81#ibcon#read 6, iclass 21, count 0 2006.175.08:00:02.81#ibcon#end of sib2, iclass 21, count 0 2006.175.08:00:02.81#ibcon#*after write, iclass 21, count 0 2006.175.08:00:02.81#ibcon#*before return 0, iclass 21, count 0 2006.175.08:00:02.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:00:02.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:00:02.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:00:02.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:00:02.81$4f8m12a/ifd4f 2006.175.08:00:02.81$ifd4f/lo= 2006.175.08:00:02.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:00:02.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:00:02.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:00:02.82$ifd4f/patch= 2006.175.08:00:02.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:00:02.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:00:02.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:00:02.82$4f8m12a/"form=m,16.000,1:2 2006.175.08:00:02.82$4f8m12a/"tpicd 2006.175.08:00:02.82$4f8m12a/echo=off 2006.175.08:00:02.82$4f8m12a/xlog=off 2006.175.08:00:02.82:!2006.175.08:01:00 2006.175.08:00:37.14#trakl#Source acquired 2006.175.08:00:39.14#flagr#flagr/antenna,acquired 2006.175.08:01:00.01:preob 2006.175.08:01:01.14/onsource/TRACKING 2006.175.08:01:01.14:!2006.175.08:01:10 2006.175.08:01:10.00:data_valid=on 2006.175.08:01:10.00:midob 2006.175.08:01:10.14/onsource/TRACKING 2006.175.08:01:10.14/wx/25.86,1007.4,70 2006.175.08:01:10.29/cable/+6.4774E-03 2006.175.08:01:11.38/va/01,08,usb,yes,29,30 2006.175.08:01:11.38/va/02,07,usb,yes,29,30 2006.175.08:01:11.38/va/03,06,usb,yes,30,31 2006.175.08:01:11.38/va/04,07,usb,yes,30,32 2006.175.08:01:11.38/va/05,07,usb,yes,30,32 2006.175.08:01:11.38/va/06,06,usb,yes,29,29 2006.175.08:01:11.38/va/07,06,usb,yes,30,29 2006.175.08:01:11.38/va/08,06,usb,yes,32,31 2006.175.08:01:11.61/valo/01,532.99,yes,locked 2006.175.08:01:11.61/valo/02,572.99,yes,locked 2006.175.08:01:11.61/valo/03,672.99,yes,locked 2006.175.08:01:11.61/valo/04,832.99,yes,locked 2006.175.08:01:11.61/valo/05,652.99,yes,locked 2006.175.08:01:11.61/valo/06,772.99,yes,locked 2006.175.08:01:11.61/valo/07,832.99,yes,locked 2006.175.08:01:11.61/valo/08,852.99,yes,locked 2006.175.08:01:12.70/vb/01,04,usb,yes,29,28 2006.175.08:01:12.70/vb/02,04,usb,yes,31,32 2006.175.08:01:12.70/vb/03,04,usb,yes,27,31 2006.175.08:01:12.70/vb/04,04,usb,yes,28,28 2006.175.08:01:12.70/vb/05,04,usb,yes,27,31 2006.175.08:01:12.70/vb/06,04,usb,yes,28,30 2006.175.08:01:12.70/vb/07,04,usb,yes,30,29 2006.175.08:01:12.70/vb/08,04,usb,yes,27,30 2006.175.08:01:12.94/vblo/01,632.99,yes,locked 2006.175.08:01:12.94/vblo/02,640.99,yes,locked 2006.175.08:01:12.94/vblo/03,656.99,yes,locked 2006.175.08:01:12.94/vblo/04,712.99,yes,locked 2006.175.08:01:12.94/vblo/05,744.99,yes,locked 2006.175.08:01:12.94/vblo/06,752.99,yes,locked 2006.175.08:01:12.94/vblo/07,734.99,yes,locked 2006.175.08:01:12.94/vblo/08,744.99,yes,locked 2006.175.08:01:13.09/vabw/8 2006.175.08:01:13.24/vbbw/8 2006.175.08:01:13.33/xfe/off,on,14.7 2006.175.08:01:13.71/ifatt/23,28,28,28 2006.175.08:01:14.07/fmout-gps/S +3.75E-07 2006.175.08:01:14.15:!2006.175.08:02:10 2006.175.08:02:10.01:data_valid=off 2006.175.08:02:10.02:postob 2006.175.08:02:10.16/cable/+6.4779E-03 2006.175.08:02:10.17/wx/25.86,1007.4,69 2006.175.08:02:11.07/fmout-gps/S +3.74E-07 2006.175.08:02:11.08:scan_name=175-0803,k06175,60 2006.175.08:02:11.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.175.08:02:11.14#flagr#flagr/antenna,new-source 2006.175.08:02:12.14:checkk5 2006.175.08:02:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:02:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:02:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:02:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:02:14.03/chk_obsdata//k5ts1/T1750801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:02:14.40/chk_obsdata//k5ts2/T1750801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:02:14.77/chk_obsdata//k5ts3/T1750801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:02:15.15/chk_obsdata//k5ts4/T1750801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:02:15.84/k5log//k5ts1_log_newline 2006.175.08:02:16.54/k5log//k5ts2_log_newline 2006.175.08:02:17.23/k5log//k5ts3_log_newline 2006.175.08:02:17.92/k5log//k5ts4_log_newline 2006.175.08:02:17.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:02:17.95:4f8m12a=2 2006.175.08:02:17.95$4f8m12a/echo=on 2006.175.08:02:17.95$4f8m12a/pcalon 2006.175.08:02:17.95$pcalon/"no phase cal control is implemented here 2006.175.08:02:17.95$4f8m12a/"tpicd=stop 2006.175.08:02:17.95$4f8m12a/vc4f8 2006.175.08:02:17.95$vc4f8/valo=1,532.99 2006.175.08:02:17.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.08:02:17.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.08:02:17.95#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:17.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:17.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:17.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:17.95#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:02:17.95#ibcon#first serial, iclass 40, count 0 2006.175.08:02:17.95#ibcon#enter sib2, iclass 40, count 0 2006.175.08:02:17.95#ibcon#flushed, iclass 40, count 0 2006.175.08:02:17.95#ibcon#about to write, iclass 40, count 0 2006.175.08:02:17.95#ibcon#wrote, iclass 40, count 0 2006.175.08:02:17.95#ibcon#about to read 3, iclass 40, count 0 2006.175.08:02:17.99#ibcon#read 3, iclass 40, count 0 2006.175.08:02:17.99#ibcon#about to read 4, iclass 40, count 0 2006.175.08:02:17.99#ibcon#read 4, iclass 40, count 0 2006.175.08:02:17.99#ibcon#about to read 5, iclass 40, count 0 2006.175.08:02:17.99#ibcon#read 5, iclass 40, count 0 2006.175.08:02:17.99#ibcon#about to read 6, iclass 40, count 0 2006.175.08:02:17.99#ibcon#read 6, iclass 40, count 0 2006.175.08:02:17.99#ibcon#end of sib2, iclass 40, count 0 2006.175.08:02:17.99#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:02:17.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:02:17.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:02:17.99#ibcon#*before write, iclass 40, count 0 2006.175.08:02:17.99#ibcon#enter sib2, iclass 40, count 0 2006.175.08:02:17.99#ibcon#flushed, iclass 40, count 0 2006.175.08:02:17.99#ibcon#about to write, iclass 40, count 0 2006.175.08:02:17.99#ibcon#wrote, iclass 40, count 0 2006.175.08:02:17.99#ibcon#about to read 3, iclass 40, count 0 2006.175.08:02:18.04#ibcon#read 3, iclass 40, count 0 2006.175.08:02:18.04#ibcon#about to read 4, iclass 40, count 0 2006.175.08:02:18.04#ibcon#read 4, iclass 40, count 0 2006.175.08:02:18.04#ibcon#about to read 5, iclass 40, count 0 2006.175.08:02:18.04#ibcon#read 5, iclass 40, count 0 2006.175.08:02:18.04#ibcon#about to read 6, iclass 40, count 0 2006.175.08:02:18.04#ibcon#read 6, iclass 40, count 0 2006.175.08:02:18.04#ibcon#end of sib2, iclass 40, count 0 2006.175.08:02:18.04#ibcon#*after write, iclass 40, count 0 2006.175.08:02:18.04#ibcon#*before return 0, iclass 40, count 0 2006.175.08:02:18.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:18.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:18.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:02:18.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:02:18.04$vc4f8/va=1,8 2006.175.08:02:18.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.175.08:02:18.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.175.08:02:18.04#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:18.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:18.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:18.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:18.04#ibcon#enter wrdev, iclass 4, count 2 2006.175.08:02:18.04#ibcon#first serial, iclass 4, count 2 2006.175.08:02:18.04#ibcon#enter sib2, iclass 4, count 2 2006.175.08:02:18.04#ibcon#flushed, iclass 4, count 2 2006.175.08:02:18.04#ibcon#about to write, iclass 4, count 2 2006.175.08:02:18.04#ibcon#wrote, iclass 4, count 2 2006.175.08:02:18.04#ibcon#about to read 3, iclass 4, count 2 2006.175.08:02:18.06#ibcon#read 3, iclass 4, count 2 2006.175.08:02:18.06#ibcon#about to read 4, iclass 4, count 2 2006.175.08:02:18.06#ibcon#read 4, iclass 4, count 2 2006.175.08:02:18.06#ibcon#about to read 5, iclass 4, count 2 2006.175.08:02:18.06#ibcon#read 5, iclass 4, count 2 2006.175.08:02:18.06#ibcon#about to read 6, iclass 4, count 2 2006.175.08:02:18.06#ibcon#read 6, iclass 4, count 2 2006.175.08:02:18.06#ibcon#end of sib2, iclass 4, count 2 2006.175.08:02:18.06#ibcon#*mode == 0, iclass 4, count 2 2006.175.08:02:18.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.175.08:02:18.06#ibcon#[25=AT01-08\r\n] 2006.175.08:02:18.06#ibcon#*before write, iclass 4, count 2 2006.175.08:02:18.06#ibcon#enter sib2, iclass 4, count 2 2006.175.08:02:18.06#ibcon#flushed, iclass 4, count 2 2006.175.08:02:18.06#ibcon#about to write, iclass 4, count 2 2006.175.08:02:18.06#ibcon#wrote, iclass 4, count 2 2006.175.08:02:18.06#ibcon#about to read 3, iclass 4, count 2 2006.175.08:02:18.09#ibcon#read 3, iclass 4, count 2 2006.175.08:02:18.09#ibcon#about to read 4, iclass 4, count 2 2006.175.08:02:18.09#ibcon#read 4, iclass 4, count 2 2006.175.08:02:18.09#ibcon#about to read 5, iclass 4, count 2 2006.175.08:02:18.09#ibcon#read 5, iclass 4, count 2 2006.175.08:02:18.09#ibcon#about to read 6, iclass 4, count 2 2006.175.08:02:18.09#ibcon#read 6, iclass 4, count 2 2006.175.08:02:18.09#ibcon#end of sib2, iclass 4, count 2 2006.175.08:02:18.09#ibcon#*after write, iclass 4, count 2 2006.175.08:02:18.09#ibcon#*before return 0, iclass 4, count 2 2006.175.08:02:18.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:18.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:18.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.175.08:02:18.09#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:18.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:18.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:18.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:18.21#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:02:18.21#ibcon#first serial, iclass 4, count 0 2006.175.08:02:18.21#ibcon#enter sib2, iclass 4, count 0 2006.175.08:02:18.21#ibcon#flushed, iclass 4, count 0 2006.175.08:02:18.21#ibcon#about to write, iclass 4, count 0 2006.175.08:02:18.21#ibcon#wrote, iclass 4, count 0 2006.175.08:02:18.21#ibcon#about to read 3, iclass 4, count 0 2006.175.08:02:18.23#ibcon#read 3, iclass 4, count 0 2006.175.08:02:18.23#ibcon#about to read 4, iclass 4, count 0 2006.175.08:02:18.23#ibcon#read 4, iclass 4, count 0 2006.175.08:02:18.23#ibcon#about to read 5, iclass 4, count 0 2006.175.08:02:18.23#ibcon#read 5, iclass 4, count 0 2006.175.08:02:18.23#ibcon#about to read 6, iclass 4, count 0 2006.175.08:02:18.23#ibcon#read 6, iclass 4, count 0 2006.175.08:02:18.23#ibcon#end of sib2, iclass 4, count 0 2006.175.08:02:18.23#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:02:18.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:02:18.23#ibcon#[25=USB\r\n] 2006.175.08:02:18.23#ibcon#*before write, iclass 4, count 0 2006.175.08:02:18.23#ibcon#enter sib2, iclass 4, count 0 2006.175.08:02:18.23#ibcon#flushed, iclass 4, count 0 2006.175.08:02:18.23#ibcon#about to write, iclass 4, count 0 2006.175.08:02:18.23#ibcon#wrote, iclass 4, count 0 2006.175.08:02:18.23#ibcon#about to read 3, iclass 4, count 0 2006.175.08:02:18.26#ibcon#read 3, iclass 4, count 0 2006.175.08:02:18.26#ibcon#about to read 4, iclass 4, count 0 2006.175.08:02:18.26#ibcon#read 4, iclass 4, count 0 2006.175.08:02:18.26#ibcon#about to read 5, iclass 4, count 0 2006.175.08:02:18.26#ibcon#read 5, iclass 4, count 0 2006.175.08:02:18.26#ibcon#about to read 6, iclass 4, count 0 2006.175.08:02:18.26#ibcon#read 6, iclass 4, count 0 2006.175.08:02:18.26#ibcon#end of sib2, iclass 4, count 0 2006.175.08:02:18.26#ibcon#*after write, iclass 4, count 0 2006.175.08:02:18.26#ibcon#*before return 0, iclass 4, count 0 2006.175.08:02:18.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:18.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:18.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:02:18.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:02:18.26$vc4f8/valo=2,572.99 2006.175.08:02:18.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.175.08:02:18.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.175.08:02:18.26#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:18.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:18.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:18.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:18.26#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:02:18.26#ibcon#first serial, iclass 6, count 0 2006.175.08:02:18.26#ibcon#enter sib2, iclass 6, count 0 2006.175.08:02:18.26#ibcon#flushed, iclass 6, count 0 2006.175.08:02:18.26#ibcon#about to write, iclass 6, count 0 2006.175.08:02:18.26#ibcon#wrote, iclass 6, count 0 2006.175.08:02:18.26#ibcon#about to read 3, iclass 6, count 0 2006.175.08:02:18.28#ibcon#read 3, iclass 6, count 0 2006.175.08:02:18.28#ibcon#about to read 4, iclass 6, count 0 2006.175.08:02:18.28#ibcon#read 4, iclass 6, count 0 2006.175.08:02:18.28#ibcon#about to read 5, iclass 6, count 0 2006.175.08:02:18.28#ibcon#read 5, iclass 6, count 0 2006.175.08:02:18.28#ibcon#about to read 6, iclass 6, count 0 2006.175.08:02:18.28#ibcon#read 6, iclass 6, count 0 2006.175.08:02:18.28#ibcon#end of sib2, iclass 6, count 0 2006.175.08:02:18.28#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:02:18.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:02:18.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:02:18.28#ibcon#*before write, iclass 6, count 0 2006.175.08:02:18.28#ibcon#enter sib2, iclass 6, count 0 2006.175.08:02:18.28#ibcon#flushed, iclass 6, count 0 2006.175.08:02:18.28#ibcon#about to write, iclass 6, count 0 2006.175.08:02:18.28#ibcon#wrote, iclass 6, count 0 2006.175.08:02:18.28#ibcon#about to read 3, iclass 6, count 0 2006.175.08:02:18.32#ibcon#read 3, iclass 6, count 0 2006.175.08:02:18.32#ibcon#about to read 4, iclass 6, count 0 2006.175.08:02:18.32#ibcon#read 4, iclass 6, count 0 2006.175.08:02:18.32#ibcon#about to read 5, iclass 6, count 0 2006.175.08:02:18.32#ibcon#read 5, iclass 6, count 0 2006.175.08:02:18.32#ibcon#about to read 6, iclass 6, count 0 2006.175.08:02:18.32#ibcon#read 6, iclass 6, count 0 2006.175.08:02:18.32#ibcon#end of sib2, iclass 6, count 0 2006.175.08:02:18.32#ibcon#*after write, iclass 6, count 0 2006.175.08:02:18.32#ibcon#*before return 0, iclass 6, count 0 2006.175.08:02:18.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:18.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:18.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:02:18.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:02:18.32$vc4f8/va=2,7 2006.175.08:02:18.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.175.08:02:18.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.175.08:02:18.32#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:18.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:18.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:18.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:18.38#ibcon#enter wrdev, iclass 10, count 2 2006.175.08:02:18.38#ibcon#first serial, iclass 10, count 2 2006.175.08:02:18.38#ibcon#enter sib2, iclass 10, count 2 2006.175.08:02:18.38#ibcon#flushed, iclass 10, count 2 2006.175.08:02:18.38#ibcon#about to write, iclass 10, count 2 2006.175.08:02:18.38#ibcon#wrote, iclass 10, count 2 2006.175.08:02:18.38#ibcon#about to read 3, iclass 10, count 2 2006.175.08:02:18.41#ibcon#read 3, iclass 10, count 2 2006.175.08:02:18.41#ibcon#about to read 4, iclass 10, count 2 2006.175.08:02:18.41#ibcon#read 4, iclass 10, count 2 2006.175.08:02:18.41#ibcon#about to read 5, iclass 10, count 2 2006.175.08:02:18.41#ibcon#read 5, iclass 10, count 2 2006.175.08:02:18.41#ibcon#about to read 6, iclass 10, count 2 2006.175.08:02:18.41#ibcon#read 6, iclass 10, count 2 2006.175.08:02:18.41#ibcon#end of sib2, iclass 10, count 2 2006.175.08:02:18.41#ibcon#*mode == 0, iclass 10, count 2 2006.175.08:02:18.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.175.08:02:18.41#ibcon#[25=AT02-07\r\n] 2006.175.08:02:18.41#ibcon#*before write, iclass 10, count 2 2006.175.08:02:18.41#ibcon#enter sib2, iclass 10, count 2 2006.175.08:02:18.41#ibcon#flushed, iclass 10, count 2 2006.175.08:02:18.41#ibcon#about to write, iclass 10, count 2 2006.175.08:02:18.41#ibcon#wrote, iclass 10, count 2 2006.175.08:02:18.41#ibcon#about to read 3, iclass 10, count 2 2006.175.08:02:18.43#ibcon#read 3, iclass 10, count 2 2006.175.08:02:18.43#ibcon#about to read 4, iclass 10, count 2 2006.175.08:02:18.43#ibcon#read 4, iclass 10, count 2 2006.175.08:02:18.43#ibcon#about to read 5, iclass 10, count 2 2006.175.08:02:18.43#ibcon#read 5, iclass 10, count 2 2006.175.08:02:18.43#ibcon#about to read 6, iclass 10, count 2 2006.175.08:02:18.43#ibcon#read 6, iclass 10, count 2 2006.175.08:02:18.43#ibcon#end of sib2, iclass 10, count 2 2006.175.08:02:18.43#ibcon#*after write, iclass 10, count 2 2006.175.08:02:18.43#ibcon#*before return 0, iclass 10, count 2 2006.175.08:02:18.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:18.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:18.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.175.08:02:18.43#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:18.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:18.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:18.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:18.55#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:02:18.55#ibcon#first serial, iclass 10, count 0 2006.175.08:02:18.55#ibcon#enter sib2, iclass 10, count 0 2006.175.08:02:18.55#ibcon#flushed, iclass 10, count 0 2006.175.08:02:18.55#ibcon#about to write, iclass 10, count 0 2006.175.08:02:18.55#ibcon#wrote, iclass 10, count 0 2006.175.08:02:18.55#ibcon#about to read 3, iclass 10, count 0 2006.175.08:02:18.57#ibcon#read 3, iclass 10, count 0 2006.175.08:02:18.57#ibcon#about to read 4, iclass 10, count 0 2006.175.08:02:18.57#ibcon#read 4, iclass 10, count 0 2006.175.08:02:18.57#ibcon#about to read 5, iclass 10, count 0 2006.175.08:02:18.57#ibcon#read 5, iclass 10, count 0 2006.175.08:02:18.57#ibcon#about to read 6, iclass 10, count 0 2006.175.08:02:18.57#ibcon#read 6, iclass 10, count 0 2006.175.08:02:18.57#ibcon#end of sib2, iclass 10, count 0 2006.175.08:02:18.57#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:02:18.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:02:18.57#ibcon#[25=USB\r\n] 2006.175.08:02:18.57#ibcon#*before write, iclass 10, count 0 2006.175.08:02:18.57#ibcon#enter sib2, iclass 10, count 0 2006.175.08:02:18.57#ibcon#flushed, iclass 10, count 0 2006.175.08:02:18.57#ibcon#about to write, iclass 10, count 0 2006.175.08:02:18.57#ibcon#wrote, iclass 10, count 0 2006.175.08:02:18.57#ibcon#about to read 3, iclass 10, count 0 2006.175.08:02:18.60#ibcon#read 3, iclass 10, count 0 2006.175.08:02:18.60#ibcon#about to read 4, iclass 10, count 0 2006.175.08:02:18.60#ibcon#read 4, iclass 10, count 0 2006.175.08:02:18.60#ibcon#about to read 5, iclass 10, count 0 2006.175.08:02:18.60#ibcon#read 5, iclass 10, count 0 2006.175.08:02:18.60#ibcon#about to read 6, iclass 10, count 0 2006.175.08:02:18.60#ibcon#read 6, iclass 10, count 0 2006.175.08:02:18.60#ibcon#end of sib2, iclass 10, count 0 2006.175.08:02:18.60#ibcon#*after write, iclass 10, count 0 2006.175.08:02:18.60#ibcon#*before return 0, iclass 10, count 0 2006.175.08:02:18.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:18.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:18.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:02:18.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:02:18.60$vc4f8/valo=3,672.99 2006.175.08:02:18.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.08:02:18.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.08:02:18.60#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:18.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:18.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:18.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:18.60#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:02:18.60#ibcon#first serial, iclass 12, count 0 2006.175.08:02:18.60#ibcon#enter sib2, iclass 12, count 0 2006.175.08:02:18.60#ibcon#flushed, iclass 12, count 0 2006.175.08:02:18.60#ibcon#about to write, iclass 12, count 0 2006.175.08:02:18.60#ibcon#wrote, iclass 12, count 0 2006.175.08:02:18.60#ibcon#about to read 3, iclass 12, count 0 2006.175.08:02:18.62#ibcon#read 3, iclass 12, count 0 2006.175.08:02:18.62#ibcon#about to read 4, iclass 12, count 0 2006.175.08:02:18.62#ibcon#read 4, iclass 12, count 0 2006.175.08:02:18.62#ibcon#about to read 5, iclass 12, count 0 2006.175.08:02:18.62#ibcon#read 5, iclass 12, count 0 2006.175.08:02:18.62#ibcon#about to read 6, iclass 12, count 0 2006.175.08:02:18.62#ibcon#read 6, iclass 12, count 0 2006.175.08:02:18.62#ibcon#end of sib2, iclass 12, count 0 2006.175.08:02:18.62#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:02:18.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:02:18.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:02:18.62#ibcon#*before write, iclass 12, count 0 2006.175.08:02:18.62#ibcon#enter sib2, iclass 12, count 0 2006.175.08:02:18.62#ibcon#flushed, iclass 12, count 0 2006.175.08:02:18.62#ibcon#about to write, iclass 12, count 0 2006.175.08:02:18.62#ibcon#wrote, iclass 12, count 0 2006.175.08:02:18.62#ibcon#about to read 3, iclass 12, count 0 2006.175.08:02:18.66#ibcon#read 3, iclass 12, count 0 2006.175.08:02:18.66#ibcon#about to read 4, iclass 12, count 0 2006.175.08:02:18.66#ibcon#read 4, iclass 12, count 0 2006.175.08:02:18.66#ibcon#about to read 5, iclass 12, count 0 2006.175.08:02:18.66#ibcon#read 5, iclass 12, count 0 2006.175.08:02:18.66#ibcon#about to read 6, iclass 12, count 0 2006.175.08:02:18.66#ibcon#read 6, iclass 12, count 0 2006.175.08:02:18.66#ibcon#end of sib2, iclass 12, count 0 2006.175.08:02:18.66#ibcon#*after write, iclass 12, count 0 2006.175.08:02:18.66#ibcon#*before return 0, iclass 12, count 0 2006.175.08:02:18.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:18.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:18.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:02:18.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:02:18.66$vc4f8/va=3,6 2006.175.08:02:18.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.08:02:18.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.08:02:18.66#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:18.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:18.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:18.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:18.72#ibcon#enter wrdev, iclass 14, count 2 2006.175.08:02:18.72#ibcon#first serial, iclass 14, count 2 2006.175.08:02:18.72#ibcon#enter sib2, iclass 14, count 2 2006.175.08:02:18.72#ibcon#flushed, iclass 14, count 2 2006.175.08:02:18.72#ibcon#about to write, iclass 14, count 2 2006.175.08:02:18.72#ibcon#wrote, iclass 14, count 2 2006.175.08:02:18.72#ibcon#about to read 3, iclass 14, count 2 2006.175.08:02:18.75#ibcon#read 3, iclass 14, count 2 2006.175.08:02:18.75#ibcon#about to read 4, iclass 14, count 2 2006.175.08:02:18.75#ibcon#read 4, iclass 14, count 2 2006.175.08:02:18.75#ibcon#about to read 5, iclass 14, count 2 2006.175.08:02:18.75#ibcon#read 5, iclass 14, count 2 2006.175.08:02:18.75#ibcon#about to read 6, iclass 14, count 2 2006.175.08:02:18.75#ibcon#read 6, iclass 14, count 2 2006.175.08:02:18.75#ibcon#end of sib2, iclass 14, count 2 2006.175.08:02:18.75#ibcon#*mode == 0, iclass 14, count 2 2006.175.08:02:18.75#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.08:02:18.75#ibcon#[25=AT03-06\r\n] 2006.175.08:02:18.75#ibcon#*before write, iclass 14, count 2 2006.175.08:02:18.75#ibcon#enter sib2, iclass 14, count 2 2006.175.08:02:18.75#ibcon#flushed, iclass 14, count 2 2006.175.08:02:18.75#ibcon#about to write, iclass 14, count 2 2006.175.08:02:18.75#ibcon#wrote, iclass 14, count 2 2006.175.08:02:18.75#ibcon#about to read 3, iclass 14, count 2 2006.175.08:02:18.77#ibcon#read 3, iclass 14, count 2 2006.175.08:02:18.77#ibcon#about to read 4, iclass 14, count 2 2006.175.08:02:18.77#ibcon#read 4, iclass 14, count 2 2006.175.08:02:18.77#ibcon#about to read 5, iclass 14, count 2 2006.175.08:02:18.77#ibcon#read 5, iclass 14, count 2 2006.175.08:02:18.77#ibcon#about to read 6, iclass 14, count 2 2006.175.08:02:18.77#ibcon#read 6, iclass 14, count 2 2006.175.08:02:18.77#ibcon#end of sib2, iclass 14, count 2 2006.175.08:02:18.77#ibcon#*after write, iclass 14, count 2 2006.175.08:02:18.77#ibcon#*before return 0, iclass 14, count 2 2006.175.08:02:18.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:18.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:18.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.08:02:18.77#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:18.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:18.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:18.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:18.89#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:02:18.89#ibcon#first serial, iclass 14, count 0 2006.175.08:02:18.89#ibcon#enter sib2, iclass 14, count 0 2006.175.08:02:18.89#ibcon#flushed, iclass 14, count 0 2006.175.08:02:18.89#ibcon#about to write, iclass 14, count 0 2006.175.08:02:18.89#ibcon#wrote, iclass 14, count 0 2006.175.08:02:18.89#ibcon#about to read 3, iclass 14, count 0 2006.175.08:02:18.91#ibcon#read 3, iclass 14, count 0 2006.175.08:02:18.91#ibcon#about to read 4, iclass 14, count 0 2006.175.08:02:18.91#ibcon#read 4, iclass 14, count 0 2006.175.08:02:18.91#ibcon#about to read 5, iclass 14, count 0 2006.175.08:02:18.91#ibcon#read 5, iclass 14, count 0 2006.175.08:02:18.91#ibcon#about to read 6, iclass 14, count 0 2006.175.08:02:18.91#ibcon#read 6, iclass 14, count 0 2006.175.08:02:18.91#ibcon#end of sib2, iclass 14, count 0 2006.175.08:02:18.91#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:02:18.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:02:18.91#ibcon#[25=USB\r\n] 2006.175.08:02:18.91#ibcon#*before write, iclass 14, count 0 2006.175.08:02:18.91#ibcon#enter sib2, iclass 14, count 0 2006.175.08:02:18.91#ibcon#flushed, iclass 14, count 0 2006.175.08:02:18.91#ibcon#about to write, iclass 14, count 0 2006.175.08:02:18.91#ibcon#wrote, iclass 14, count 0 2006.175.08:02:18.91#ibcon#about to read 3, iclass 14, count 0 2006.175.08:02:18.94#ibcon#read 3, iclass 14, count 0 2006.175.08:02:18.94#ibcon#about to read 4, iclass 14, count 0 2006.175.08:02:18.94#ibcon#read 4, iclass 14, count 0 2006.175.08:02:18.94#ibcon#about to read 5, iclass 14, count 0 2006.175.08:02:18.94#ibcon#read 5, iclass 14, count 0 2006.175.08:02:18.94#ibcon#about to read 6, iclass 14, count 0 2006.175.08:02:18.94#ibcon#read 6, iclass 14, count 0 2006.175.08:02:18.94#ibcon#end of sib2, iclass 14, count 0 2006.175.08:02:18.94#ibcon#*after write, iclass 14, count 0 2006.175.08:02:18.94#ibcon#*before return 0, iclass 14, count 0 2006.175.08:02:18.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:18.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:18.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:02:18.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:02:18.94$vc4f8/valo=4,832.99 2006.175.08:02:18.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.08:02:18.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.08:02:18.94#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:18.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:18.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:18.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:18.94#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:02:18.94#ibcon#first serial, iclass 16, count 0 2006.175.08:02:18.94#ibcon#enter sib2, iclass 16, count 0 2006.175.08:02:18.94#ibcon#flushed, iclass 16, count 0 2006.175.08:02:18.94#ibcon#about to write, iclass 16, count 0 2006.175.08:02:18.94#ibcon#wrote, iclass 16, count 0 2006.175.08:02:18.94#ibcon#about to read 3, iclass 16, count 0 2006.175.08:02:18.96#ibcon#read 3, iclass 16, count 0 2006.175.08:02:18.96#ibcon#about to read 4, iclass 16, count 0 2006.175.08:02:18.96#ibcon#read 4, iclass 16, count 0 2006.175.08:02:18.96#ibcon#about to read 5, iclass 16, count 0 2006.175.08:02:18.96#ibcon#read 5, iclass 16, count 0 2006.175.08:02:18.96#ibcon#about to read 6, iclass 16, count 0 2006.175.08:02:18.96#ibcon#read 6, iclass 16, count 0 2006.175.08:02:18.96#ibcon#end of sib2, iclass 16, count 0 2006.175.08:02:18.96#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:02:18.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:02:18.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:02:18.96#ibcon#*before write, iclass 16, count 0 2006.175.08:02:18.96#ibcon#enter sib2, iclass 16, count 0 2006.175.08:02:18.96#ibcon#flushed, iclass 16, count 0 2006.175.08:02:18.96#ibcon#about to write, iclass 16, count 0 2006.175.08:02:18.96#ibcon#wrote, iclass 16, count 0 2006.175.08:02:18.96#ibcon#about to read 3, iclass 16, count 0 2006.175.08:02:19.00#ibcon#read 3, iclass 16, count 0 2006.175.08:02:19.00#ibcon#about to read 4, iclass 16, count 0 2006.175.08:02:19.00#ibcon#read 4, iclass 16, count 0 2006.175.08:02:19.00#ibcon#about to read 5, iclass 16, count 0 2006.175.08:02:19.00#ibcon#read 5, iclass 16, count 0 2006.175.08:02:19.00#ibcon#about to read 6, iclass 16, count 0 2006.175.08:02:19.00#ibcon#read 6, iclass 16, count 0 2006.175.08:02:19.00#ibcon#end of sib2, iclass 16, count 0 2006.175.08:02:19.00#ibcon#*after write, iclass 16, count 0 2006.175.08:02:19.00#ibcon#*before return 0, iclass 16, count 0 2006.175.08:02:19.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:19.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:19.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:02:19.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:02:19.00$vc4f8/va=4,7 2006.175.08:02:19.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.08:02:19.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.08:02:19.00#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:19.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:19.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:19.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:19.06#ibcon#enter wrdev, iclass 18, count 2 2006.175.08:02:19.06#ibcon#first serial, iclass 18, count 2 2006.175.08:02:19.06#ibcon#enter sib2, iclass 18, count 2 2006.175.08:02:19.06#ibcon#flushed, iclass 18, count 2 2006.175.08:02:19.06#ibcon#about to write, iclass 18, count 2 2006.175.08:02:19.06#ibcon#wrote, iclass 18, count 2 2006.175.08:02:19.06#ibcon#about to read 3, iclass 18, count 2 2006.175.08:02:19.08#ibcon#read 3, iclass 18, count 2 2006.175.08:02:19.08#ibcon#about to read 4, iclass 18, count 2 2006.175.08:02:19.08#ibcon#read 4, iclass 18, count 2 2006.175.08:02:19.08#ibcon#about to read 5, iclass 18, count 2 2006.175.08:02:19.08#ibcon#read 5, iclass 18, count 2 2006.175.08:02:19.08#ibcon#about to read 6, iclass 18, count 2 2006.175.08:02:19.08#ibcon#read 6, iclass 18, count 2 2006.175.08:02:19.08#ibcon#end of sib2, iclass 18, count 2 2006.175.08:02:19.08#ibcon#*mode == 0, iclass 18, count 2 2006.175.08:02:19.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.08:02:19.08#ibcon#[25=AT04-07\r\n] 2006.175.08:02:19.08#ibcon#*before write, iclass 18, count 2 2006.175.08:02:19.08#ibcon#enter sib2, iclass 18, count 2 2006.175.08:02:19.08#ibcon#flushed, iclass 18, count 2 2006.175.08:02:19.08#ibcon#about to write, iclass 18, count 2 2006.175.08:02:19.08#ibcon#wrote, iclass 18, count 2 2006.175.08:02:19.08#ibcon#about to read 3, iclass 18, count 2 2006.175.08:02:19.11#ibcon#read 3, iclass 18, count 2 2006.175.08:02:19.11#ibcon#about to read 4, iclass 18, count 2 2006.175.08:02:19.11#ibcon#read 4, iclass 18, count 2 2006.175.08:02:19.11#ibcon#about to read 5, iclass 18, count 2 2006.175.08:02:19.11#ibcon#read 5, iclass 18, count 2 2006.175.08:02:19.11#ibcon#about to read 6, iclass 18, count 2 2006.175.08:02:19.11#ibcon#read 6, iclass 18, count 2 2006.175.08:02:19.11#ibcon#end of sib2, iclass 18, count 2 2006.175.08:02:19.11#ibcon#*after write, iclass 18, count 2 2006.175.08:02:19.11#ibcon#*before return 0, iclass 18, count 2 2006.175.08:02:19.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:19.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:19.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.08:02:19.11#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:19.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:19.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:19.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:19.23#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:02:19.23#ibcon#first serial, iclass 18, count 0 2006.175.08:02:19.23#ibcon#enter sib2, iclass 18, count 0 2006.175.08:02:19.23#ibcon#flushed, iclass 18, count 0 2006.175.08:02:19.23#ibcon#about to write, iclass 18, count 0 2006.175.08:02:19.23#ibcon#wrote, iclass 18, count 0 2006.175.08:02:19.23#ibcon#about to read 3, iclass 18, count 0 2006.175.08:02:19.25#ibcon#read 3, iclass 18, count 0 2006.175.08:02:19.25#ibcon#about to read 4, iclass 18, count 0 2006.175.08:02:19.25#ibcon#read 4, iclass 18, count 0 2006.175.08:02:19.25#ibcon#about to read 5, iclass 18, count 0 2006.175.08:02:19.25#ibcon#read 5, iclass 18, count 0 2006.175.08:02:19.25#ibcon#about to read 6, iclass 18, count 0 2006.175.08:02:19.25#ibcon#read 6, iclass 18, count 0 2006.175.08:02:19.25#ibcon#end of sib2, iclass 18, count 0 2006.175.08:02:19.25#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:02:19.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:02:19.25#ibcon#[25=USB\r\n] 2006.175.08:02:19.25#ibcon#*before write, iclass 18, count 0 2006.175.08:02:19.25#ibcon#enter sib2, iclass 18, count 0 2006.175.08:02:19.25#ibcon#flushed, iclass 18, count 0 2006.175.08:02:19.25#ibcon#about to write, iclass 18, count 0 2006.175.08:02:19.25#ibcon#wrote, iclass 18, count 0 2006.175.08:02:19.25#ibcon#about to read 3, iclass 18, count 0 2006.175.08:02:19.28#ibcon#read 3, iclass 18, count 0 2006.175.08:02:19.28#ibcon#about to read 4, iclass 18, count 0 2006.175.08:02:19.28#ibcon#read 4, iclass 18, count 0 2006.175.08:02:19.28#ibcon#about to read 5, iclass 18, count 0 2006.175.08:02:19.28#ibcon#read 5, iclass 18, count 0 2006.175.08:02:19.28#ibcon#about to read 6, iclass 18, count 0 2006.175.08:02:19.28#ibcon#read 6, iclass 18, count 0 2006.175.08:02:19.28#ibcon#end of sib2, iclass 18, count 0 2006.175.08:02:19.28#ibcon#*after write, iclass 18, count 0 2006.175.08:02:19.28#ibcon#*before return 0, iclass 18, count 0 2006.175.08:02:19.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:19.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:19.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:02:19.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:02:19.28$vc4f8/valo=5,652.99 2006.175.08:02:19.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.08:02:19.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.08:02:19.28#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:19.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:02:19.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:02:19.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:02:19.28#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:02:19.28#ibcon#first serial, iclass 20, count 0 2006.175.08:02:19.28#ibcon#enter sib2, iclass 20, count 0 2006.175.08:02:19.28#ibcon#flushed, iclass 20, count 0 2006.175.08:02:19.28#ibcon#about to write, iclass 20, count 0 2006.175.08:02:19.28#ibcon#wrote, iclass 20, count 0 2006.175.08:02:19.28#ibcon#about to read 3, iclass 20, count 0 2006.175.08:02:19.30#ibcon#read 3, iclass 20, count 0 2006.175.08:02:19.30#ibcon#about to read 4, iclass 20, count 0 2006.175.08:02:19.30#ibcon#read 4, iclass 20, count 0 2006.175.08:02:19.30#ibcon#about to read 5, iclass 20, count 0 2006.175.08:02:19.30#ibcon#read 5, iclass 20, count 0 2006.175.08:02:19.30#ibcon#about to read 6, iclass 20, count 0 2006.175.08:02:19.30#ibcon#read 6, iclass 20, count 0 2006.175.08:02:19.30#ibcon#end of sib2, iclass 20, count 0 2006.175.08:02:19.30#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:02:19.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:02:19.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:02:19.30#ibcon#*before write, iclass 20, count 0 2006.175.08:02:19.30#ibcon#enter sib2, iclass 20, count 0 2006.175.08:02:19.30#ibcon#flushed, iclass 20, count 0 2006.175.08:02:19.30#ibcon#about to write, iclass 20, count 0 2006.175.08:02:19.30#ibcon#wrote, iclass 20, count 0 2006.175.08:02:19.30#ibcon#about to read 3, iclass 20, count 0 2006.175.08:02:19.34#ibcon#read 3, iclass 20, count 0 2006.175.08:02:19.34#ibcon#about to read 4, iclass 20, count 0 2006.175.08:02:19.34#ibcon#read 4, iclass 20, count 0 2006.175.08:02:19.34#ibcon#about to read 5, iclass 20, count 0 2006.175.08:02:19.34#ibcon#read 5, iclass 20, count 0 2006.175.08:02:19.34#ibcon#about to read 6, iclass 20, count 0 2006.175.08:02:19.34#ibcon#read 6, iclass 20, count 0 2006.175.08:02:19.34#ibcon#end of sib2, iclass 20, count 0 2006.175.08:02:19.34#ibcon#*after write, iclass 20, count 0 2006.175.08:02:19.34#ibcon#*before return 0, iclass 20, count 0 2006.175.08:02:19.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:02:19.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:02:19.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:02:19.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:02:19.34$vc4f8/va=5,7 2006.175.08:02:19.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.08:02:19.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.08:02:19.34#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:19.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:02:19.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:02:19.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:02:19.40#ibcon#enter wrdev, iclass 22, count 2 2006.175.08:02:19.40#ibcon#first serial, iclass 22, count 2 2006.175.08:02:19.40#ibcon#enter sib2, iclass 22, count 2 2006.175.08:02:19.40#ibcon#flushed, iclass 22, count 2 2006.175.08:02:19.40#ibcon#about to write, iclass 22, count 2 2006.175.08:02:19.40#ibcon#wrote, iclass 22, count 2 2006.175.08:02:19.40#ibcon#about to read 3, iclass 22, count 2 2006.175.08:02:19.42#ibcon#read 3, iclass 22, count 2 2006.175.08:02:19.42#ibcon#about to read 4, iclass 22, count 2 2006.175.08:02:19.42#ibcon#read 4, iclass 22, count 2 2006.175.08:02:19.42#ibcon#about to read 5, iclass 22, count 2 2006.175.08:02:19.42#ibcon#read 5, iclass 22, count 2 2006.175.08:02:19.42#ibcon#about to read 6, iclass 22, count 2 2006.175.08:02:19.42#ibcon#read 6, iclass 22, count 2 2006.175.08:02:19.42#ibcon#end of sib2, iclass 22, count 2 2006.175.08:02:19.42#ibcon#*mode == 0, iclass 22, count 2 2006.175.08:02:19.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.08:02:19.42#ibcon#[25=AT05-07\r\n] 2006.175.08:02:19.42#ibcon#*before write, iclass 22, count 2 2006.175.08:02:19.42#ibcon#enter sib2, iclass 22, count 2 2006.175.08:02:19.42#ibcon#flushed, iclass 22, count 2 2006.175.08:02:19.42#ibcon#about to write, iclass 22, count 2 2006.175.08:02:19.42#ibcon#wrote, iclass 22, count 2 2006.175.08:02:19.42#ibcon#about to read 3, iclass 22, count 2 2006.175.08:02:19.45#ibcon#read 3, iclass 22, count 2 2006.175.08:02:19.45#ibcon#about to read 4, iclass 22, count 2 2006.175.08:02:19.45#ibcon#read 4, iclass 22, count 2 2006.175.08:02:19.45#ibcon#about to read 5, iclass 22, count 2 2006.175.08:02:19.45#ibcon#read 5, iclass 22, count 2 2006.175.08:02:19.45#ibcon#about to read 6, iclass 22, count 2 2006.175.08:02:19.45#ibcon#read 6, iclass 22, count 2 2006.175.08:02:19.45#ibcon#end of sib2, iclass 22, count 2 2006.175.08:02:19.45#ibcon#*after write, iclass 22, count 2 2006.175.08:02:19.45#ibcon#*before return 0, iclass 22, count 2 2006.175.08:02:19.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:02:19.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:02:19.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.08:02:19.45#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:19.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:02:19.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:02:19.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:02:19.57#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:02:19.57#ibcon#first serial, iclass 22, count 0 2006.175.08:02:19.57#ibcon#enter sib2, iclass 22, count 0 2006.175.08:02:19.57#ibcon#flushed, iclass 22, count 0 2006.175.08:02:19.57#ibcon#about to write, iclass 22, count 0 2006.175.08:02:19.57#ibcon#wrote, iclass 22, count 0 2006.175.08:02:19.57#ibcon#about to read 3, iclass 22, count 0 2006.175.08:02:19.59#ibcon#read 3, iclass 22, count 0 2006.175.08:02:19.59#ibcon#about to read 4, iclass 22, count 0 2006.175.08:02:19.59#ibcon#read 4, iclass 22, count 0 2006.175.08:02:19.59#ibcon#about to read 5, iclass 22, count 0 2006.175.08:02:19.59#ibcon#read 5, iclass 22, count 0 2006.175.08:02:19.59#ibcon#about to read 6, iclass 22, count 0 2006.175.08:02:19.59#ibcon#read 6, iclass 22, count 0 2006.175.08:02:19.59#ibcon#end of sib2, iclass 22, count 0 2006.175.08:02:19.59#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:02:19.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:02:19.59#ibcon#[25=USB\r\n] 2006.175.08:02:19.59#ibcon#*before write, iclass 22, count 0 2006.175.08:02:19.59#ibcon#enter sib2, iclass 22, count 0 2006.175.08:02:19.59#ibcon#flushed, iclass 22, count 0 2006.175.08:02:19.59#ibcon#about to write, iclass 22, count 0 2006.175.08:02:19.59#ibcon#wrote, iclass 22, count 0 2006.175.08:02:19.59#ibcon#about to read 3, iclass 22, count 0 2006.175.08:02:19.62#ibcon#read 3, iclass 22, count 0 2006.175.08:02:19.62#ibcon#about to read 4, iclass 22, count 0 2006.175.08:02:19.62#ibcon#read 4, iclass 22, count 0 2006.175.08:02:19.62#ibcon#about to read 5, iclass 22, count 0 2006.175.08:02:19.62#ibcon#read 5, iclass 22, count 0 2006.175.08:02:19.62#ibcon#about to read 6, iclass 22, count 0 2006.175.08:02:19.62#ibcon#read 6, iclass 22, count 0 2006.175.08:02:19.62#ibcon#end of sib2, iclass 22, count 0 2006.175.08:02:19.62#ibcon#*after write, iclass 22, count 0 2006.175.08:02:19.62#ibcon#*before return 0, iclass 22, count 0 2006.175.08:02:19.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:02:19.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:02:19.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:02:19.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:02:19.62$vc4f8/valo=6,772.99 2006.175.08:02:19.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.08:02:19.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.08:02:19.62#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:19.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:19.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:19.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:19.62#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:02:19.62#ibcon#first serial, iclass 24, count 0 2006.175.08:02:19.62#ibcon#enter sib2, iclass 24, count 0 2006.175.08:02:19.62#ibcon#flushed, iclass 24, count 0 2006.175.08:02:19.62#ibcon#about to write, iclass 24, count 0 2006.175.08:02:19.62#ibcon#wrote, iclass 24, count 0 2006.175.08:02:19.62#ibcon#about to read 3, iclass 24, count 0 2006.175.08:02:19.64#ibcon#read 3, iclass 24, count 0 2006.175.08:02:19.64#ibcon#about to read 4, iclass 24, count 0 2006.175.08:02:19.64#ibcon#read 4, iclass 24, count 0 2006.175.08:02:19.64#ibcon#about to read 5, iclass 24, count 0 2006.175.08:02:19.64#ibcon#read 5, iclass 24, count 0 2006.175.08:02:19.64#ibcon#about to read 6, iclass 24, count 0 2006.175.08:02:19.64#ibcon#read 6, iclass 24, count 0 2006.175.08:02:19.64#ibcon#end of sib2, iclass 24, count 0 2006.175.08:02:19.64#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:02:19.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:02:19.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:02:19.64#ibcon#*before write, iclass 24, count 0 2006.175.08:02:19.64#ibcon#enter sib2, iclass 24, count 0 2006.175.08:02:19.64#ibcon#flushed, iclass 24, count 0 2006.175.08:02:19.64#ibcon#about to write, iclass 24, count 0 2006.175.08:02:19.64#ibcon#wrote, iclass 24, count 0 2006.175.08:02:19.64#ibcon#about to read 3, iclass 24, count 0 2006.175.08:02:19.68#ibcon#read 3, iclass 24, count 0 2006.175.08:02:19.68#ibcon#about to read 4, iclass 24, count 0 2006.175.08:02:19.68#ibcon#read 4, iclass 24, count 0 2006.175.08:02:19.68#ibcon#about to read 5, iclass 24, count 0 2006.175.08:02:19.68#ibcon#read 5, iclass 24, count 0 2006.175.08:02:19.68#ibcon#about to read 6, iclass 24, count 0 2006.175.08:02:19.68#ibcon#read 6, iclass 24, count 0 2006.175.08:02:19.68#ibcon#end of sib2, iclass 24, count 0 2006.175.08:02:19.68#ibcon#*after write, iclass 24, count 0 2006.175.08:02:19.68#ibcon#*before return 0, iclass 24, count 0 2006.175.08:02:19.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:19.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:19.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:02:19.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:02:19.68$vc4f8/va=6,6 2006.175.08:02:19.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.08:02:19.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.08:02:19.68#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:19.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:19.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:19.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:19.74#ibcon#enter wrdev, iclass 26, count 2 2006.175.08:02:19.74#ibcon#first serial, iclass 26, count 2 2006.175.08:02:19.74#ibcon#enter sib2, iclass 26, count 2 2006.175.08:02:19.74#ibcon#flushed, iclass 26, count 2 2006.175.08:02:19.74#ibcon#about to write, iclass 26, count 2 2006.175.08:02:19.74#ibcon#wrote, iclass 26, count 2 2006.175.08:02:19.74#ibcon#about to read 3, iclass 26, count 2 2006.175.08:02:19.76#ibcon#read 3, iclass 26, count 2 2006.175.08:02:19.76#ibcon#about to read 4, iclass 26, count 2 2006.175.08:02:19.76#ibcon#read 4, iclass 26, count 2 2006.175.08:02:19.76#ibcon#about to read 5, iclass 26, count 2 2006.175.08:02:19.76#ibcon#read 5, iclass 26, count 2 2006.175.08:02:19.76#ibcon#about to read 6, iclass 26, count 2 2006.175.08:02:19.76#ibcon#read 6, iclass 26, count 2 2006.175.08:02:19.76#ibcon#end of sib2, iclass 26, count 2 2006.175.08:02:19.76#ibcon#*mode == 0, iclass 26, count 2 2006.175.08:02:19.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.08:02:19.76#ibcon#[25=AT06-06\r\n] 2006.175.08:02:19.76#ibcon#*before write, iclass 26, count 2 2006.175.08:02:19.76#ibcon#enter sib2, iclass 26, count 2 2006.175.08:02:19.76#ibcon#flushed, iclass 26, count 2 2006.175.08:02:19.76#ibcon#about to write, iclass 26, count 2 2006.175.08:02:19.76#ibcon#wrote, iclass 26, count 2 2006.175.08:02:19.76#ibcon#about to read 3, iclass 26, count 2 2006.175.08:02:19.79#ibcon#read 3, iclass 26, count 2 2006.175.08:02:19.79#ibcon#about to read 4, iclass 26, count 2 2006.175.08:02:19.79#ibcon#read 4, iclass 26, count 2 2006.175.08:02:19.79#ibcon#about to read 5, iclass 26, count 2 2006.175.08:02:19.79#ibcon#read 5, iclass 26, count 2 2006.175.08:02:19.79#ibcon#about to read 6, iclass 26, count 2 2006.175.08:02:19.79#ibcon#read 6, iclass 26, count 2 2006.175.08:02:19.79#ibcon#end of sib2, iclass 26, count 2 2006.175.08:02:19.79#ibcon#*after write, iclass 26, count 2 2006.175.08:02:19.79#ibcon#*before return 0, iclass 26, count 2 2006.175.08:02:19.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:19.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:19.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.08:02:19.79#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:19.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:19.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:19.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:19.91#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:02:19.91#ibcon#first serial, iclass 26, count 0 2006.175.08:02:19.91#ibcon#enter sib2, iclass 26, count 0 2006.175.08:02:19.91#ibcon#flushed, iclass 26, count 0 2006.175.08:02:19.91#ibcon#about to write, iclass 26, count 0 2006.175.08:02:19.91#ibcon#wrote, iclass 26, count 0 2006.175.08:02:19.91#ibcon#about to read 3, iclass 26, count 0 2006.175.08:02:19.93#ibcon#read 3, iclass 26, count 0 2006.175.08:02:19.93#ibcon#about to read 4, iclass 26, count 0 2006.175.08:02:19.93#ibcon#read 4, iclass 26, count 0 2006.175.08:02:19.93#ibcon#about to read 5, iclass 26, count 0 2006.175.08:02:19.93#ibcon#read 5, iclass 26, count 0 2006.175.08:02:19.93#ibcon#about to read 6, iclass 26, count 0 2006.175.08:02:19.93#ibcon#read 6, iclass 26, count 0 2006.175.08:02:19.93#ibcon#end of sib2, iclass 26, count 0 2006.175.08:02:19.93#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:02:19.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:02:19.93#ibcon#[25=USB\r\n] 2006.175.08:02:19.93#ibcon#*before write, iclass 26, count 0 2006.175.08:02:19.93#ibcon#enter sib2, iclass 26, count 0 2006.175.08:02:19.93#ibcon#flushed, iclass 26, count 0 2006.175.08:02:19.93#ibcon#about to write, iclass 26, count 0 2006.175.08:02:19.93#ibcon#wrote, iclass 26, count 0 2006.175.08:02:19.93#ibcon#about to read 3, iclass 26, count 0 2006.175.08:02:19.96#ibcon#read 3, iclass 26, count 0 2006.175.08:02:19.96#ibcon#about to read 4, iclass 26, count 0 2006.175.08:02:19.96#ibcon#read 4, iclass 26, count 0 2006.175.08:02:19.96#ibcon#about to read 5, iclass 26, count 0 2006.175.08:02:19.96#ibcon#read 5, iclass 26, count 0 2006.175.08:02:19.96#ibcon#about to read 6, iclass 26, count 0 2006.175.08:02:19.96#ibcon#read 6, iclass 26, count 0 2006.175.08:02:19.96#ibcon#end of sib2, iclass 26, count 0 2006.175.08:02:19.96#ibcon#*after write, iclass 26, count 0 2006.175.08:02:19.96#ibcon#*before return 0, iclass 26, count 0 2006.175.08:02:19.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:19.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:19.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:02:19.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:02:19.96$vc4f8/valo=7,832.99 2006.175.08:02:19.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.08:02:19.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.08:02:19.96#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:19.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:19.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:19.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:19.96#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:02:19.96#ibcon#first serial, iclass 28, count 0 2006.175.08:02:19.96#ibcon#enter sib2, iclass 28, count 0 2006.175.08:02:19.96#ibcon#flushed, iclass 28, count 0 2006.175.08:02:19.96#ibcon#about to write, iclass 28, count 0 2006.175.08:02:19.96#ibcon#wrote, iclass 28, count 0 2006.175.08:02:19.96#ibcon#about to read 3, iclass 28, count 0 2006.175.08:02:19.98#ibcon#read 3, iclass 28, count 0 2006.175.08:02:19.98#ibcon#about to read 4, iclass 28, count 0 2006.175.08:02:19.98#ibcon#read 4, iclass 28, count 0 2006.175.08:02:19.98#ibcon#about to read 5, iclass 28, count 0 2006.175.08:02:19.98#ibcon#read 5, iclass 28, count 0 2006.175.08:02:19.98#ibcon#about to read 6, iclass 28, count 0 2006.175.08:02:19.98#ibcon#read 6, iclass 28, count 0 2006.175.08:02:19.98#ibcon#end of sib2, iclass 28, count 0 2006.175.08:02:19.98#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:02:19.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:02:19.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:02:19.98#ibcon#*before write, iclass 28, count 0 2006.175.08:02:19.98#ibcon#enter sib2, iclass 28, count 0 2006.175.08:02:19.98#ibcon#flushed, iclass 28, count 0 2006.175.08:02:19.98#ibcon#about to write, iclass 28, count 0 2006.175.08:02:19.98#ibcon#wrote, iclass 28, count 0 2006.175.08:02:19.98#ibcon#about to read 3, iclass 28, count 0 2006.175.08:02:20.02#ibcon#read 3, iclass 28, count 0 2006.175.08:02:20.02#ibcon#about to read 4, iclass 28, count 0 2006.175.08:02:20.02#ibcon#read 4, iclass 28, count 0 2006.175.08:02:20.02#ibcon#about to read 5, iclass 28, count 0 2006.175.08:02:20.02#ibcon#read 5, iclass 28, count 0 2006.175.08:02:20.02#ibcon#about to read 6, iclass 28, count 0 2006.175.08:02:20.02#ibcon#read 6, iclass 28, count 0 2006.175.08:02:20.02#ibcon#end of sib2, iclass 28, count 0 2006.175.08:02:20.02#ibcon#*after write, iclass 28, count 0 2006.175.08:02:20.02#ibcon#*before return 0, iclass 28, count 0 2006.175.08:02:20.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:20.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:20.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:02:20.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:02:20.02$vc4f8/va=7,6 2006.175.08:02:20.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.08:02:20.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.08:02:20.02#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:20.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:02:20.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:02:20.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:02:20.08#ibcon#enter wrdev, iclass 30, count 2 2006.175.08:02:20.08#ibcon#first serial, iclass 30, count 2 2006.175.08:02:20.08#ibcon#enter sib2, iclass 30, count 2 2006.175.08:02:20.08#ibcon#flushed, iclass 30, count 2 2006.175.08:02:20.08#ibcon#about to write, iclass 30, count 2 2006.175.08:02:20.08#ibcon#wrote, iclass 30, count 2 2006.175.08:02:20.08#ibcon#about to read 3, iclass 30, count 2 2006.175.08:02:20.10#ibcon#read 3, iclass 30, count 2 2006.175.08:02:20.10#ibcon#about to read 4, iclass 30, count 2 2006.175.08:02:20.10#ibcon#read 4, iclass 30, count 2 2006.175.08:02:20.10#ibcon#about to read 5, iclass 30, count 2 2006.175.08:02:20.10#ibcon#read 5, iclass 30, count 2 2006.175.08:02:20.10#ibcon#about to read 6, iclass 30, count 2 2006.175.08:02:20.10#ibcon#read 6, iclass 30, count 2 2006.175.08:02:20.10#ibcon#end of sib2, iclass 30, count 2 2006.175.08:02:20.10#ibcon#*mode == 0, iclass 30, count 2 2006.175.08:02:20.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.08:02:20.10#ibcon#[25=AT07-06\r\n] 2006.175.08:02:20.10#ibcon#*before write, iclass 30, count 2 2006.175.08:02:20.10#ibcon#enter sib2, iclass 30, count 2 2006.175.08:02:20.10#ibcon#flushed, iclass 30, count 2 2006.175.08:02:20.10#ibcon#about to write, iclass 30, count 2 2006.175.08:02:20.10#ibcon#wrote, iclass 30, count 2 2006.175.08:02:20.10#ibcon#about to read 3, iclass 30, count 2 2006.175.08:02:20.13#ibcon#read 3, iclass 30, count 2 2006.175.08:02:20.13#ibcon#about to read 4, iclass 30, count 2 2006.175.08:02:20.13#ibcon#read 4, iclass 30, count 2 2006.175.08:02:20.13#ibcon#about to read 5, iclass 30, count 2 2006.175.08:02:20.13#ibcon#read 5, iclass 30, count 2 2006.175.08:02:20.13#ibcon#about to read 6, iclass 30, count 2 2006.175.08:02:20.13#ibcon#read 6, iclass 30, count 2 2006.175.08:02:20.13#ibcon#end of sib2, iclass 30, count 2 2006.175.08:02:20.13#ibcon#*after write, iclass 30, count 2 2006.175.08:02:20.13#ibcon#*before return 0, iclass 30, count 2 2006.175.08:02:20.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:02:20.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:02:20.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.08:02:20.13#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:20.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:02:20.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:02:20.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:02:20.25#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:02:20.25#ibcon#first serial, iclass 30, count 0 2006.175.08:02:20.25#ibcon#enter sib2, iclass 30, count 0 2006.175.08:02:20.25#ibcon#flushed, iclass 30, count 0 2006.175.08:02:20.25#ibcon#about to write, iclass 30, count 0 2006.175.08:02:20.25#ibcon#wrote, iclass 30, count 0 2006.175.08:02:20.25#ibcon#about to read 3, iclass 30, count 0 2006.175.08:02:20.27#ibcon#read 3, iclass 30, count 0 2006.175.08:02:20.27#ibcon#about to read 4, iclass 30, count 0 2006.175.08:02:20.27#ibcon#read 4, iclass 30, count 0 2006.175.08:02:20.27#ibcon#about to read 5, iclass 30, count 0 2006.175.08:02:20.27#ibcon#read 5, iclass 30, count 0 2006.175.08:02:20.27#ibcon#about to read 6, iclass 30, count 0 2006.175.08:02:20.27#ibcon#read 6, iclass 30, count 0 2006.175.08:02:20.27#ibcon#end of sib2, iclass 30, count 0 2006.175.08:02:20.27#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:02:20.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:02:20.27#ibcon#[25=USB\r\n] 2006.175.08:02:20.27#ibcon#*before write, iclass 30, count 0 2006.175.08:02:20.27#ibcon#enter sib2, iclass 30, count 0 2006.175.08:02:20.27#ibcon#flushed, iclass 30, count 0 2006.175.08:02:20.27#ibcon#about to write, iclass 30, count 0 2006.175.08:02:20.27#ibcon#wrote, iclass 30, count 0 2006.175.08:02:20.27#ibcon#about to read 3, iclass 30, count 0 2006.175.08:02:20.30#ibcon#read 3, iclass 30, count 0 2006.175.08:02:20.30#ibcon#about to read 4, iclass 30, count 0 2006.175.08:02:20.30#ibcon#read 4, iclass 30, count 0 2006.175.08:02:20.30#ibcon#about to read 5, iclass 30, count 0 2006.175.08:02:20.30#ibcon#read 5, iclass 30, count 0 2006.175.08:02:20.30#ibcon#about to read 6, iclass 30, count 0 2006.175.08:02:20.30#ibcon#read 6, iclass 30, count 0 2006.175.08:02:20.30#ibcon#end of sib2, iclass 30, count 0 2006.175.08:02:20.30#ibcon#*after write, iclass 30, count 0 2006.175.08:02:20.30#ibcon#*before return 0, iclass 30, count 0 2006.175.08:02:20.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:02:20.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:02:20.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:02:20.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:02:20.30$vc4f8/valo=8,852.99 2006.175.08:02:20.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.08:02:20.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.08:02:20.30#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:20.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:02:20.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:02:20.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:02:20.30#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:02:20.30#ibcon#first serial, iclass 32, count 0 2006.175.08:02:20.30#ibcon#enter sib2, iclass 32, count 0 2006.175.08:02:20.30#ibcon#flushed, iclass 32, count 0 2006.175.08:02:20.30#ibcon#about to write, iclass 32, count 0 2006.175.08:02:20.30#ibcon#wrote, iclass 32, count 0 2006.175.08:02:20.30#ibcon#about to read 3, iclass 32, count 0 2006.175.08:02:20.32#ibcon#read 3, iclass 32, count 0 2006.175.08:02:20.32#ibcon#about to read 4, iclass 32, count 0 2006.175.08:02:20.32#ibcon#read 4, iclass 32, count 0 2006.175.08:02:20.32#ibcon#about to read 5, iclass 32, count 0 2006.175.08:02:20.32#ibcon#read 5, iclass 32, count 0 2006.175.08:02:20.32#ibcon#about to read 6, iclass 32, count 0 2006.175.08:02:20.32#ibcon#read 6, iclass 32, count 0 2006.175.08:02:20.32#ibcon#end of sib2, iclass 32, count 0 2006.175.08:02:20.32#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:02:20.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:02:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:02:20.32#ibcon#*before write, iclass 32, count 0 2006.175.08:02:20.32#ibcon#enter sib2, iclass 32, count 0 2006.175.08:02:20.32#ibcon#flushed, iclass 32, count 0 2006.175.08:02:20.32#ibcon#about to write, iclass 32, count 0 2006.175.08:02:20.32#ibcon#wrote, iclass 32, count 0 2006.175.08:02:20.32#ibcon#about to read 3, iclass 32, count 0 2006.175.08:02:20.36#ibcon#read 3, iclass 32, count 0 2006.175.08:02:20.36#ibcon#about to read 4, iclass 32, count 0 2006.175.08:02:20.36#ibcon#read 4, iclass 32, count 0 2006.175.08:02:20.36#ibcon#about to read 5, iclass 32, count 0 2006.175.08:02:20.36#ibcon#read 5, iclass 32, count 0 2006.175.08:02:20.36#ibcon#about to read 6, iclass 32, count 0 2006.175.08:02:20.36#ibcon#read 6, iclass 32, count 0 2006.175.08:02:20.36#ibcon#end of sib2, iclass 32, count 0 2006.175.08:02:20.36#ibcon#*after write, iclass 32, count 0 2006.175.08:02:20.36#ibcon#*before return 0, iclass 32, count 0 2006.175.08:02:20.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:02:20.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:02:20.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:02:20.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:02:20.36$vc4f8/va=8,6 2006.175.08:02:20.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.175.08:02:20.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.175.08:02:20.36#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:20.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:02:20.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:02:20.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:02:20.42#ibcon#enter wrdev, iclass 34, count 2 2006.175.08:02:20.42#ibcon#first serial, iclass 34, count 2 2006.175.08:02:20.42#ibcon#enter sib2, iclass 34, count 2 2006.175.08:02:20.42#ibcon#flushed, iclass 34, count 2 2006.175.08:02:20.42#ibcon#about to write, iclass 34, count 2 2006.175.08:02:20.42#ibcon#wrote, iclass 34, count 2 2006.175.08:02:20.42#ibcon#about to read 3, iclass 34, count 2 2006.175.08:02:20.44#ibcon#read 3, iclass 34, count 2 2006.175.08:02:20.44#ibcon#about to read 4, iclass 34, count 2 2006.175.08:02:20.44#ibcon#read 4, iclass 34, count 2 2006.175.08:02:20.44#ibcon#about to read 5, iclass 34, count 2 2006.175.08:02:20.44#ibcon#read 5, iclass 34, count 2 2006.175.08:02:20.44#ibcon#about to read 6, iclass 34, count 2 2006.175.08:02:20.44#ibcon#read 6, iclass 34, count 2 2006.175.08:02:20.44#ibcon#end of sib2, iclass 34, count 2 2006.175.08:02:20.44#ibcon#*mode == 0, iclass 34, count 2 2006.175.08:02:20.44#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.175.08:02:20.44#ibcon#[25=AT08-06\r\n] 2006.175.08:02:20.44#ibcon#*before write, iclass 34, count 2 2006.175.08:02:20.44#ibcon#enter sib2, iclass 34, count 2 2006.175.08:02:20.44#ibcon#flushed, iclass 34, count 2 2006.175.08:02:20.44#ibcon#about to write, iclass 34, count 2 2006.175.08:02:20.44#ibcon#wrote, iclass 34, count 2 2006.175.08:02:20.44#ibcon#about to read 3, iclass 34, count 2 2006.175.08:02:20.47#ibcon#read 3, iclass 34, count 2 2006.175.08:02:20.47#ibcon#about to read 4, iclass 34, count 2 2006.175.08:02:20.47#ibcon#read 4, iclass 34, count 2 2006.175.08:02:20.47#ibcon#about to read 5, iclass 34, count 2 2006.175.08:02:20.47#ibcon#read 5, iclass 34, count 2 2006.175.08:02:20.47#ibcon#about to read 6, iclass 34, count 2 2006.175.08:02:20.47#ibcon#read 6, iclass 34, count 2 2006.175.08:02:20.47#ibcon#end of sib2, iclass 34, count 2 2006.175.08:02:20.47#ibcon#*after write, iclass 34, count 2 2006.175.08:02:20.47#ibcon#*before return 0, iclass 34, count 2 2006.175.08:02:20.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:02:20.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:02:20.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.175.08:02:20.47#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:20.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:02:20.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:02:20.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:02:20.59#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:02:20.59#ibcon#first serial, iclass 34, count 0 2006.175.08:02:20.59#ibcon#enter sib2, iclass 34, count 0 2006.175.08:02:20.59#ibcon#flushed, iclass 34, count 0 2006.175.08:02:20.59#ibcon#about to write, iclass 34, count 0 2006.175.08:02:20.59#ibcon#wrote, iclass 34, count 0 2006.175.08:02:20.59#ibcon#about to read 3, iclass 34, count 0 2006.175.08:02:20.61#ibcon#read 3, iclass 34, count 0 2006.175.08:02:20.61#ibcon#about to read 4, iclass 34, count 0 2006.175.08:02:20.61#ibcon#read 4, iclass 34, count 0 2006.175.08:02:20.61#ibcon#about to read 5, iclass 34, count 0 2006.175.08:02:20.61#ibcon#read 5, iclass 34, count 0 2006.175.08:02:20.61#ibcon#about to read 6, iclass 34, count 0 2006.175.08:02:20.61#ibcon#read 6, iclass 34, count 0 2006.175.08:02:20.61#ibcon#end of sib2, iclass 34, count 0 2006.175.08:02:20.61#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:02:20.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:02:20.61#ibcon#[25=USB\r\n] 2006.175.08:02:20.61#ibcon#*before write, iclass 34, count 0 2006.175.08:02:20.61#ibcon#enter sib2, iclass 34, count 0 2006.175.08:02:20.61#ibcon#flushed, iclass 34, count 0 2006.175.08:02:20.61#ibcon#about to write, iclass 34, count 0 2006.175.08:02:20.61#ibcon#wrote, iclass 34, count 0 2006.175.08:02:20.61#ibcon#about to read 3, iclass 34, count 0 2006.175.08:02:20.64#ibcon#read 3, iclass 34, count 0 2006.175.08:02:20.64#ibcon#about to read 4, iclass 34, count 0 2006.175.08:02:20.64#ibcon#read 4, iclass 34, count 0 2006.175.08:02:20.64#ibcon#about to read 5, iclass 34, count 0 2006.175.08:02:20.64#ibcon#read 5, iclass 34, count 0 2006.175.08:02:20.64#ibcon#about to read 6, iclass 34, count 0 2006.175.08:02:20.64#ibcon#read 6, iclass 34, count 0 2006.175.08:02:20.64#ibcon#end of sib2, iclass 34, count 0 2006.175.08:02:20.64#ibcon#*after write, iclass 34, count 0 2006.175.08:02:20.64#ibcon#*before return 0, iclass 34, count 0 2006.175.08:02:20.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:02:20.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:02:20.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:02:20.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:02:20.64$vc4f8/vblo=1,632.99 2006.175.08:02:20.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.08:02:20.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.08:02:20.64#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:20.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:02:20.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:02:20.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:02:20.64#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:02:20.64#ibcon#first serial, iclass 36, count 0 2006.175.08:02:20.64#ibcon#enter sib2, iclass 36, count 0 2006.175.08:02:20.64#ibcon#flushed, iclass 36, count 0 2006.175.08:02:20.64#ibcon#about to write, iclass 36, count 0 2006.175.08:02:20.64#ibcon#wrote, iclass 36, count 0 2006.175.08:02:20.64#ibcon#about to read 3, iclass 36, count 0 2006.175.08:02:20.66#ibcon#read 3, iclass 36, count 0 2006.175.08:02:20.66#ibcon#about to read 4, iclass 36, count 0 2006.175.08:02:20.66#ibcon#read 4, iclass 36, count 0 2006.175.08:02:20.66#ibcon#about to read 5, iclass 36, count 0 2006.175.08:02:20.66#ibcon#read 5, iclass 36, count 0 2006.175.08:02:20.66#ibcon#about to read 6, iclass 36, count 0 2006.175.08:02:20.66#ibcon#read 6, iclass 36, count 0 2006.175.08:02:20.66#ibcon#end of sib2, iclass 36, count 0 2006.175.08:02:20.66#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:02:20.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:02:20.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:02:20.66#ibcon#*before write, iclass 36, count 0 2006.175.08:02:20.66#ibcon#enter sib2, iclass 36, count 0 2006.175.08:02:20.66#ibcon#flushed, iclass 36, count 0 2006.175.08:02:20.66#ibcon#about to write, iclass 36, count 0 2006.175.08:02:20.66#ibcon#wrote, iclass 36, count 0 2006.175.08:02:20.66#ibcon#about to read 3, iclass 36, count 0 2006.175.08:02:20.70#ibcon#read 3, iclass 36, count 0 2006.175.08:02:20.70#ibcon#about to read 4, iclass 36, count 0 2006.175.08:02:20.70#ibcon#read 4, iclass 36, count 0 2006.175.08:02:20.70#ibcon#about to read 5, iclass 36, count 0 2006.175.08:02:20.70#ibcon#read 5, iclass 36, count 0 2006.175.08:02:20.70#ibcon#about to read 6, iclass 36, count 0 2006.175.08:02:20.70#ibcon#read 6, iclass 36, count 0 2006.175.08:02:20.70#ibcon#end of sib2, iclass 36, count 0 2006.175.08:02:20.70#ibcon#*after write, iclass 36, count 0 2006.175.08:02:20.70#ibcon#*before return 0, iclass 36, count 0 2006.175.08:02:20.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:02:20.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:02:20.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:02:20.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:02:20.70$vc4f8/vb=1,4 2006.175.08:02:20.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.175.08:02:20.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.175.08:02:20.70#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:20.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:02:20.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:02:20.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:02:20.70#ibcon#enter wrdev, iclass 38, count 2 2006.175.08:02:20.70#ibcon#first serial, iclass 38, count 2 2006.175.08:02:20.70#ibcon#enter sib2, iclass 38, count 2 2006.175.08:02:20.70#ibcon#flushed, iclass 38, count 2 2006.175.08:02:20.70#ibcon#about to write, iclass 38, count 2 2006.175.08:02:20.70#ibcon#wrote, iclass 38, count 2 2006.175.08:02:20.70#ibcon#about to read 3, iclass 38, count 2 2006.175.08:02:20.72#ibcon#read 3, iclass 38, count 2 2006.175.08:02:20.72#ibcon#about to read 4, iclass 38, count 2 2006.175.08:02:20.72#ibcon#read 4, iclass 38, count 2 2006.175.08:02:20.72#ibcon#about to read 5, iclass 38, count 2 2006.175.08:02:20.72#ibcon#read 5, iclass 38, count 2 2006.175.08:02:20.72#ibcon#about to read 6, iclass 38, count 2 2006.175.08:02:20.72#ibcon#read 6, iclass 38, count 2 2006.175.08:02:20.72#ibcon#end of sib2, iclass 38, count 2 2006.175.08:02:20.72#ibcon#*mode == 0, iclass 38, count 2 2006.175.08:02:20.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.175.08:02:20.72#ibcon#[27=AT01-04\r\n] 2006.175.08:02:20.72#ibcon#*before write, iclass 38, count 2 2006.175.08:02:20.72#ibcon#enter sib2, iclass 38, count 2 2006.175.08:02:20.72#ibcon#flushed, iclass 38, count 2 2006.175.08:02:20.72#ibcon#about to write, iclass 38, count 2 2006.175.08:02:20.72#ibcon#wrote, iclass 38, count 2 2006.175.08:02:20.72#ibcon#about to read 3, iclass 38, count 2 2006.175.08:02:20.75#ibcon#read 3, iclass 38, count 2 2006.175.08:02:20.75#ibcon#about to read 4, iclass 38, count 2 2006.175.08:02:20.75#ibcon#read 4, iclass 38, count 2 2006.175.08:02:20.75#ibcon#about to read 5, iclass 38, count 2 2006.175.08:02:20.75#ibcon#read 5, iclass 38, count 2 2006.175.08:02:20.75#ibcon#about to read 6, iclass 38, count 2 2006.175.08:02:20.75#ibcon#read 6, iclass 38, count 2 2006.175.08:02:20.75#ibcon#end of sib2, iclass 38, count 2 2006.175.08:02:20.75#ibcon#*after write, iclass 38, count 2 2006.175.08:02:20.75#ibcon#*before return 0, iclass 38, count 2 2006.175.08:02:20.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:02:20.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:02:20.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.175.08:02:20.75#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:20.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:02:20.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:02:20.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:02:20.87#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:02:20.87#ibcon#first serial, iclass 38, count 0 2006.175.08:02:20.87#ibcon#enter sib2, iclass 38, count 0 2006.175.08:02:20.87#ibcon#flushed, iclass 38, count 0 2006.175.08:02:20.87#ibcon#about to write, iclass 38, count 0 2006.175.08:02:20.87#ibcon#wrote, iclass 38, count 0 2006.175.08:02:20.87#ibcon#about to read 3, iclass 38, count 0 2006.175.08:02:20.89#ibcon#read 3, iclass 38, count 0 2006.175.08:02:20.89#ibcon#about to read 4, iclass 38, count 0 2006.175.08:02:20.89#ibcon#read 4, iclass 38, count 0 2006.175.08:02:20.89#ibcon#about to read 5, iclass 38, count 0 2006.175.08:02:20.89#ibcon#read 5, iclass 38, count 0 2006.175.08:02:20.89#ibcon#about to read 6, iclass 38, count 0 2006.175.08:02:20.89#ibcon#read 6, iclass 38, count 0 2006.175.08:02:20.89#ibcon#end of sib2, iclass 38, count 0 2006.175.08:02:20.89#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:02:20.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:02:20.89#ibcon#[27=USB\r\n] 2006.175.08:02:20.89#ibcon#*before write, iclass 38, count 0 2006.175.08:02:20.89#ibcon#enter sib2, iclass 38, count 0 2006.175.08:02:20.89#ibcon#flushed, iclass 38, count 0 2006.175.08:02:20.89#ibcon#about to write, iclass 38, count 0 2006.175.08:02:20.89#ibcon#wrote, iclass 38, count 0 2006.175.08:02:20.89#ibcon#about to read 3, iclass 38, count 0 2006.175.08:02:20.92#ibcon#read 3, iclass 38, count 0 2006.175.08:02:20.92#ibcon#about to read 4, iclass 38, count 0 2006.175.08:02:20.92#ibcon#read 4, iclass 38, count 0 2006.175.08:02:20.92#ibcon#about to read 5, iclass 38, count 0 2006.175.08:02:20.92#ibcon#read 5, iclass 38, count 0 2006.175.08:02:20.92#ibcon#about to read 6, iclass 38, count 0 2006.175.08:02:20.92#ibcon#read 6, iclass 38, count 0 2006.175.08:02:20.92#ibcon#end of sib2, iclass 38, count 0 2006.175.08:02:20.92#ibcon#*after write, iclass 38, count 0 2006.175.08:02:20.92#ibcon#*before return 0, iclass 38, count 0 2006.175.08:02:20.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:02:20.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:02:20.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:02:20.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:02:20.92$vc4f8/vblo=2,640.99 2006.175.08:02:20.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.08:02:20.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.08:02:20.92#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:20.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:20.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:20.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:20.92#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:02:20.92#ibcon#first serial, iclass 40, count 0 2006.175.08:02:20.92#ibcon#enter sib2, iclass 40, count 0 2006.175.08:02:20.92#ibcon#flushed, iclass 40, count 0 2006.175.08:02:20.92#ibcon#about to write, iclass 40, count 0 2006.175.08:02:20.92#ibcon#wrote, iclass 40, count 0 2006.175.08:02:20.92#ibcon#about to read 3, iclass 40, count 0 2006.175.08:02:20.94#ibcon#read 3, iclass 40, count 0 2006.175.08:02:20.94#ibcon#about to read 4, iclass 40, count 0 2006.175.08:02:20.94#ibcon#read 4, iclass 40, count 0 2006.175.08:02:20.94#ibcon#about to read 5, iclass 40, count 0 2006.175.08:02:20.94#ibcon#read 5, iclass 40, count 0 2006.175.08:02:20.94#ibcon#about to read 6, iclass 40, count 0 2006.175.08:02:20.94#ibcon#read 6, iclass 40, count 0 2006.175.08:02:20.94#ibcon#end of sib2, iclass 40, count 0 2006.175.08:02:20.94#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:02:20.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:02:20.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:02:20.94#ibcon#*before write, iclass 40, count 0 2006.175.08:02:20.94#ibcon#enter sib2, iclass 40, count 0 2006.175.08:02:20.94#ibcon#flushed, iclass 40, count 0 2006.175.08:02:20.94#ibcon#about to write, iclass 40, count 0 2006.175.08:02:20.94#ibcon#wrote, iclass 40, count 0 2006.175.08:02:20.94#ibcon#about to read 3, iclass 40, count 0 2006.175.08:02:20.98#ibcon#read 3, iclass 40, count 0 2006.175.08:02:20.98#ibcon#about to read 4, iclass 40, count 0 2006.175.08:02:20.98#ibcon#read 4, iclass 40, count 0 2006.175.08:02:20.98#ibcon#about to read 5, iclass 40, count 0 2006.175.08:02:20.98#ibcon#read 5, iclass 40, count 0 2006.175.08:02:20.98#ibcon#about to read 6, iclass 40, count 0 2006.175.08:02:20.98#ibcon#read 6, iclass 40, count 0 2006.175.08:02:20.98#ibcon#end of sib2, iclass 40, count 0 2006.175.08:02:20.98#ibcon#*after write, iclass 40, count 0 2006.175.08:02:20.98#ibcon#*before return 0, iclass 40, count 0 2006.175.08:02:20.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:20.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:02:20.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:02:20.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:02:20.98$vc4f8/vb=2,4 2006.175.08:02:20.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.175.08:02:20.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.175.08:02:20.98#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:20.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:21.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:21.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:21.05#ibcon#enter wrdev, iclass 4, count 2 2006.175.08:02:21.05#ibcon#first serial, iclass 4, count 2 2006.175.08:02:21.05#ibcon#enter sib2, iclass 4, count 2 2006.175.08:02:21.05#ibcon#flushed, iclass 4, count 2 2006.175.08:02:21.05#ibcon#about to write, iclass 4, count 2 2006.175.08:02:21.05#ibcon#wrote, iclass 4, count 2 2006.175.08:02:21.05#ibcon#about to read 3, iclass 4, count 2 2006.175.08:02:21.06#ibcon#read 3, iclass 4, count 2 2006.175.08:02:21.06#ibcon#about to read 4, iclass 4, count 2 2006.175.08:02:21.06#ibcon#read 4, iclass 4, count 2 2006.175.08:02:21.06#ibcon#about to read 5, iclass 4, count 2 2006.175.08:02:21.06#ibcon#read 5, iclass 4, count 2 2006.175.08:02:21.06#ibcon#about to read 6, iclass 4, count 2 2006.175.08:02:21.06#ibcon#read 6, iclass 4, count 2 2006.175.08:02:21.06#ibcon#end of sib2, iclass 4, count 2 2006.175.08:02:21.06#ibcon#*mode == 0, iclass 4, count 2 2006.175.08:02:21.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.175.08:02:21.06#ibcon#[27=AT02-04\r\n] 2006.175.08:02:21.06#ibcon#*before write, iclass 4, count 2 2006.175.08:02:21.06#ibcon#enter sib2, iclass 4, count 2 2006.175.08:02:21.06#ibcon#flushed, iclass 4, count 2 2006.175.08:02:21.06#ibcon#about to write, iclass 4, count 2 2006.175.08:02:21.06#ibcon#wrote, iclass 4, count 2 2006.175.08:02:21.06#ibcon#about to read 3, iclass 4, count 2 2006.175.08:02:21.09#ibcon#read 3, iclass 4, count 2 2006.175.08:02:21.09#ibcon#about to read 4, iclass 4, count 2 2006.175.08:02:21.09#ibcon#read 4, iclass 4, count 2 2006.175.08:02:21.09#ibcon#about to read 5, iclass 4, count 2 2006.175.08:02:21.09#ibcon#read 5, iclass 4, count 2 2006.175.08:02:21.09#ibcon#about to read 6, iclass 4, count 2 2006.175.08:02:21.09#ibcon#read 6, iclass 4, count 2 2006.175.08:02:21.09#ibcon#end of sib2, iclass 4, count 2 2006.175.08:02:21.09#ibcon#*after write, iclass 4, count 2 2006.175.08:02:21.09#ibcon#*before return 0, iclass 4, count 2 2006.175.08:02:21.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:21.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:02:21.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.175.08:02:21.09#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:21.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:21.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:21.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:21.21#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:02:21.21#ibcon#first serial, iclass 4, count 0 2006.175.08:02:21.21#ibcon#enter sib2, iclass 4, count 0 2006.175.08:02:21.21#ibcon#flushed, iclass 4, count 0 2006.175.08:02:21.21#ibcon#about to write, iclass 4, count 0 2006.175.08:02:21.21#ibcon#wrote, iclass 4, count 0 2006.175.08:02:21.21#ibcon#about to read 3, iclass 4, count 0 2006.175.08:02:21.23#ibcon#read 3, iclass 4, count 0 2006.175.08:02:21.23#ibcon#about to read 4, iclass 4, count 0 2006.175.08:02:21.23#ibcon#read 4, iclass 4, count 0 2006.175.08:02:21.23#ibcon#about to read 5, iclass 4, count 0 2006.175.08:02:21.23#ibcon#read 5, iclass 4, count 0 2006.175.08:02:21.23#ibcon#about to read 6, iclass 4, count 0 2006.175.08:02:21.23#ibcon#read 6, iclass 4, count 0 2006.175.08:02:21.23#ibcon#end of sib2, iclass 4, count 0 2006.175.08:02:21.23#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:02:21.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:02:21.23#ibcon#[27=USB\r\n] 2006.175.08:02:21.23#ibcon#*before write, iclass 4, count 0 2006.175.08:02:21.23#ibcon#enter sib2, iclass 4, count 0 2006.175.08:02:21.23#ibcon#flushed, iclass 4, count 0 2006.175.08:02:21.23#ibcon#about to write, iclass 4, count 0 2006.175.08:02:21.23#ibcon#wrote, iclass 4, count 0 2006.175.08:02:21.23#ibcon#about to read 3, iclass 4, count 0 2006.175.08:02:21.26#ibcon#read 3, iclass 4, count 0 2006.175.08:02:21.26#ibcon#about to read 4, iclass 4, count 0 2006.175.08:02:21.26#ibcon#read 4, iclass 4, count 0 2006.175.08:02:21.26#ibcon#about to read 5, iclass 4, count 0 2006.175.08:02:21.26#ibcon#read 5, iclass 4, count 0 2006.175.08:02:21.26#ibcon#about to read 6, iclass 4, count 0 2006.175.08:02:21.26#ibcon#read 6, iclass 4, count 0 2006.175.08:02:21.26#ibcon#end of sib2, iclass 4, count 0 2006.175.08:02:21.26#ibcon#*after write, iclass 4, count 0 2006.175.08:02:21.26#ibcon#*before return 0, iclass 4, count 0 2006.175.08:02:21.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:21.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:02:21.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:02:21.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:02:21.26$vc4f8/vblo=3,656.99 2006.175.08:02:21.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.175.08:02:21.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.175.08:02:21.26#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:21.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:21.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:21.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:21.26#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:02:21.26#ibcon#first serial, iclass 6, count 0 2006.175.08:02:21.26#ibcon#enter sib2, iclass 6, count 0 2006.175.08:02:21.26#ibcon#flushed, iclass 6, count 0 2006.175.08:02:21.26#ibcon#about to write, iclass 6, count 0 2006.175.08:02:21.26#ibcon#wrote, iclass 6, count 0 2006.175.08:02:21.26#ibcon#about to read 3, iclass 6, count 0 2006.175.08:02:21.28#ibcon#read 3, iclass 6, count 0 2006.175.08:02:21.28#ibcon#about to read 4, iclass 6, count 0 2006.175.08:02:21.28#ibcon#read 4, iclass 6, count 0 2006.175.08:02:21.28#ibcon#about to read 5, iclass 6, count 0 2006.175.08:02:21.28#ibcon#read 5, iclass 6, count 0 2006.175.08:02:21.28#ibcon#about to read 6, iclass 6, count 0 2006.175.08:02:21.28#ibcon#read 6, iclass 6, count 0 2006.175.08:02:21.28#ibcon#end of sib2, iclass 6, count 0 2006.175.08:02:21.28#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:02:21.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:02:21.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:02:21.28#ibcon#*before write, iclass 6, count 0 2006.175.08:02:21.28#ibcon#enter sib2, iclass 6, count 0 2006.175.08:02:21.28#ibcon#flushed, iclass 6, count 0 2006.175.08:02:21.28#ibcon#about to write, iclass 6, count 0 2006.175.08:02:21.28#ibcon#wrote, iclass 6, count 0 2006.175.08:02:21.28#ibcon#about to read 3, iclass 6, count 0 2006.175.08:02:21.32#ibcon#read 3, iclass 6, count 0 2006.175.08:02:21.32#ibcon#about to read 4, iclass 6, count 0 2006.175.08:02:21.32#ibcon#read 4, iclass 6, count 0 2006.175.08:02:21.32#ibcon#about to read 5, iclass 6, count 0 2006.175.08:02:21.32#ibcon#read 5, iclass 6, count 0 2006.175.08:02:21.32#ibcon#about to read 6, iclass 6, count 0 2006.175.08:02:21.32#ibcon#read 6, iclass 6, count 0 2006.175.08:02:21.32#ibcon#end of sib2, iclass 6, count 0 2006.175.08:02:21.32#ibcon#*after write, iclass 6, count 0 2006.175.08:02:21.32#ibcon#*before return 0, iclass 6, count 0 2006.175.08:02:21.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:21.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:02:21.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:02:21.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:02:21.32$vc4f8/vb=3,4 2006.175.08:02:21.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.175.08:02:21.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.175.08:02:21.32#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:21.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:21.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:21.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:21.38#ibcon#enter wrdev, iclass 10, count 2 2006.175.08:02:21.38#ibcon#first serial, iclass 10, count 2 2006.175.08:02:21.38#ibcon#enter sib2, iclass 10, count 2 2006.175.08:02:21.38#ibcon#flushed, iclass 10, count 2 2006.175.08:02:21.38#ibcon#about to write, iclass 10, count 2 2006.175.08:02:21.38#ibcon#wrote, iclass 10, count 2 2006.175.08:02:21.38#ibcon#about to read 3, iclass 10, count 2 2006.175.08:02:21.40#ibcon#read 3, iclass 10, count 2 2006.175.08:02:21.40#ibcon#about to read 4, iclass 10, count 2 2006.175.08:02:21.40#ibcon#read 4, iclass 10, count 2 2006.175.08:02:21.40#ibcon#about to read 5, iclass 10, count 2 2006.175.08:02:21.40#ibcon#read 5, iclass 10, count 2 2006.175.08:02:21.40#ibcon#about to read 6, iclass 10, count 2 2006.175.08:02:21.40#ibcon#read 6, iclass 10, count 2 2006.175.08:02:21.40#ibcon#end of sib2, iclass 10, count 2 2006.175.08:02:21.40#ibcon#*mode == 0, iclass 10, count 2 2006.175.08:02:21.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.175.08:02:21.40#ibcon#[27=AT03-04\r\n] 2006.175.08:02:21.40#ibcon#*before write, iclass 10, count 2 2006.175.08:02:21.40#ibcon#enter sib2, iclass 10, count 2 2006.175.08:02:21.40#ibcon#flushed, iclass 10, count 2 2006.175.08:02:21.40#ibcon#about to write, iclass 10, count 2 2006.175.08:02:21.40#ibcon#wrote, iclass 10, count 2 2006.175.08:02:21.40#ibcon#about to read 3, iclass 10, count 2 2006.175.08:02:21.43#ibcon#read 3, iclass 10, count 2 2006.175.08:02:21.43#ibcon#about to read 4, iclass 10, count 2 2006.175.08:02:21.43#ibcon#read 4, iclass 10, count 2 2006.175.08:02:21.43#ibcon#about to read 5, iclass 10, count 2 2006.175.08:02:21.43#ibcon#read 5, iclass 10, count 2 2006.175.08:02:21.43#ibcon#about to read 6, iclass 10, count 2 2006.175.08:02:21.43#ibcon#read 6, iclass 10, count 2 2006.175.08:02:21.43#ibcon#end of sib2, iclass 10, count 2 2006.175.08:02:21.43#ibcon#*after write, iclass 10, count 2 2006.175.08:02:21.43#ibcon#*before return 0, iclass 10, count 2 2006.175.08:02:21.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:21.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:02:21.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.175.08:02:21.43#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:21.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:21.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:21.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:21.55#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:02:21.55#ibcon#first serial, iclass 10, count 0 2006.175.08:02:21.55#ibcon#enter sib2, iclass 10, count 0 2006.175.08:02:21.55#ibcon#flushed, iclass 10, count 0 2006.175.08:02:21.55#ibcon#about to write, iclass 10, count 0 2006.175.08:02:21.55#ibcon#wrote, iclass 10, count 0 2006.175.08:02:21.55#ibcon#about to read 3, iclass 10, count 0 2006.175.08:02:21.57#ibcon#read 3, iclass 10, count 0 2006.175.08:02:21.57#ibcon#about to read 4, iclass 10, count 0 2006.175.08:02:21.57#ibcon#read 4, iclass 10, count 0 2006.175.08:02:21.57#ibcon#about to read 5, iclass 10, count 0 2006.175.08:02:21.57#ibcon#read 5, iclass 10, count 0 2006.175.08:02:21.57#ibcon#about to read 6, iclass 10, count 0 2006.175.08:02:21.57#ibcon#read 6, iclass 10, count 0 2006.175.08:02:21.57#ibcon#end of sib2, iclass 10, count 0 2006.175.08:02:21.57#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:02:21.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:02:21.57#ibcon#[27=USB\r\n] 2006.175.08:02:21.57#ibcon#*before write, iclass 10, count 0 2006.175.08:02:21.57#ibcon#enter sib2, iclass 10, count 0 2006.175.08:02:21.57#ibcon#flushed, iclass 10, count 0 2006.175.08:02:21.57#ibcon#about to write, iclass 10, count 0 2006.175.08:02:21.57#ibcon#wrote, iclass 10, count 0 2006.175.08:02:21.57#ibcon#about to read 3, iclass 10, count 0 2006.175.08:02:21.60#ibcon#read 3, iclass 10, count 0 2006.175.08:02:21.60#ibcon#about to read 4, iclass 10, count 0 2006.175.08:02:21.60#ibcon#read 4, iclass 10, count 0 2006.175.08:02:21.60#ibcon#about to read 5, iclass 10, count 0 2006.175.08:02:21.60#ibcon#read 5, iclass 10, count 0 2006.175.08:02:21.60#ibcon#about to read 6, iclass 10, count 0 2006.175.08:02:21.60#ibcon#read 6, iclass 10, count 0 2006.175.08:02:21.60#ibcon#end of sib2, iclass 10, count 0 2006.175.08:02:21.60#ibcon#*after write, iclass 10, count 0 2006.175.08:02:21.60#ibcon#*before return 0, iclass 10, count 0 2006.175.08:02:21.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:21.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:02:21.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:02:21.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:02:21.60$vc4f8/vblo=4,712.99 2006.175.08:02:21.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.08:02:21.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.08:02:21.60#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:21.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:21.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:21.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:21.60#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:02:21.60#ibcon#first serial, iclass 12, count 0 2006.175.08:02:21.60#ibcon#enter sib2, iclass 12, count 0 2006.175.08:02:21.60#ibcon#flushed, iclass 12, count 0 2006.175.08:02:21.60#ibcon#about to write, iclass 12, count 0 2006.175.08:02:21.60#ibcon#wrote, iclass 12, count 0 2006.175.08:02:21.60#ibcon#about to read 3, iclass 12, count 0 2006.175.08:02:21.62#ibcon#read 3, iclass 12, count 0 2006.175.08:02:21.62#ibcon#about to read 4, iclass 12, count 0 2006.175.08:02:21.62#ibcon#read 4, iclass 12, count 0 2006.175.08:02:21.62#ibcon#about to read 5, iclass 12, count 0 2006.175.08:02:21.62#ibcon#read 5, iclass 12, count 0 2006.175.08:02:21.62#ibcon#about to read 6, iclass 12, count 0 2006.175.08:02:21.62#ibcon#read 6, iclass 12, count 0 2006.175.08:02:21.62#ibcon#end of sib2, iclass 12, count 0 2006.175.08:02:21.62#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:02:21.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:02:21.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:02:21.62#ibcon#*before write, iclass 12, count 0 2006.175.08:02:21.62#ibcon#enter sib2, iclass 12, count 0 2006.175.08:02:21.62#ibcon#flushed, iclass 12, count 0 2006.175.08:02:21.62#ibcon#about to write, iclass 12, count 0 2006.175.08:02:21.62#ibcon#wrote, iclass 12, count 0 2006.175.08:02:21.62#ibcon#about to read 3, iclass 12, count 0 2006.175.08:02:21.66#ibcon#read 3, iclass 12, count 0 2006.175.08:02:21.66#ibcon#about to read 4, iclass 12, count 0 2006.175.08:02:21.66#ibcon#read 4, iclass 12, count 0 2006.175.08:02:21.66#ibcon#about to read 5, iclass 12, count 0 2006.175.08:02:21.66#ibcon#read 5, iclass 12, count 0 2006.175.08:02:21.66#ibcon#about to read 6, iclass 12, count 0 2006.175.08:02:21.66#ibcon#read 6, iclass 12, count 0 2006.175.08:02:21.66#ibcon#end of sib2, iclass 12, count 0 2006.175.08:02:21.66#ibcon#*after write, iclass 12, count 0 2006.175.08:02:21.66#ibcon#*before return 0, iclass 12, count 0 2006.175.08:02:21.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:21.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:02:21.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:02:21.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:02:21.66$vc4f8/vb=4,4 2006.175.08:02:21.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.08:02:21.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.08:02:21.66#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:21.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:21.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:21.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:21.72#ibcon#enter wrdev, iclass 14, count 2 2006.175.08:02:21.72#ibcon#first serial, iclass 14, count 2 2006.175.08:02:21.72#ibcon#enter sib2, iclass 14, count 2 2006.175.08:02:21.72#ibcon#flushed, iclass 14, count 2 2006.175.08:02:21.72#ibcon#about to write, iclass 14, count 2 2006.175.08:02:21.72#ibcon#wrote, iclass 14, count 2 2006.175.08:02:21.72#ibcon#about to read 3, iclass 14, count 2 2006.175.08:02:21.74#ibcon#read 3, iclass 14, count 2 2006.175.08:02:21.74#ibcon#about to read 4, iclass 14, count 2 2006.175.08:02:21.74#ibcon#read 4, iclass 14, count 2 2006.175.08:02:21.74#ibcon#about to read 5, iclass 14, count 2 2006.175.08:02:21.74#ibcon#read 5, iclass 14, count 2 2006.175.08:02:21.74#ibcon#about to read 6, iclass 14, count 2 2006.175.08:02:21.74#ibcon#read 6, iclass 14, count 2 2006.175.08:02:21.74#ibcon#end of sib2, iclass 14, count 2 2006.175.08:02:21.74#ibcon#*mode == 0, iclass 14, count 2 2006.175.08:02:21.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.08:02:21.74#ibcon#[27=AT04-04\r\n] 2006.175.08:02:21.74#ibcon#*before write, iclass 14, count 2 2006.175.08:02:21.74#ibcon#enter sib2, iclass 14, count 2 2006.175.08:02:21.74#ibcon#flushed, iclass 14, count 2 2006.175.08:02:21.74#ibcon#about to write, iclass 14, count 2 2006.175.08:02:21.74#ibcon#wrote, iclass 14, count 2 2006.175.08:02:21.74#ibcon#about to read 3, iclass 14, count 2 2006.175.08:02:21.77#ibcon#read 3, iclass 14, count 2 2006.175.08:02:21.77#ibcon#about to read 4, iclass 14, count 2 2006.175.08:02:21.77#ibcon#read 4, iclass 14, count 2 2006.175.08:02:21.77#ibcon#about to read 5, iclass 14, count 2 2006.175.08:02:21.77#ibcon#read 5, iclass 14, count 2 2006.175.08:02:21.77#ibcon#about to read 6, iclass 14, count 2 2006.175.08:02:21.77#ibcon#read 6, iclass 14, count 2 2006.175.08:02:21.77#ibcon#end of sib2, iclass 14, count 2 2006.175.08:02:21.77#ibcon#*after write, iclass 14, count 2 2006.175.08:02:21.77#ibcon#*before return 0, iclass 14, count 2 2006.175.08:02:21.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:21.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:02:21.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.08:02:21.77#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:21.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:21.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:21.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:21.89#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:02:21.89#ibcon#first serial, iclass 14, count 0 2006.175.08:02:21.89#ibcon#enter sib2, iclass 14, count 0 2006.175.08:02:21.89#ibcon#flushed, iclass 14, count 0 2006.175.08:02:21.89#ibcon#about to write, iclass 14, count 0 2006.175.08:02:21.89#ibcon#wrote, iclass 14, count 0 2006.175.08:02:21.89#ibcon#about to read 3, iclass 14, count 0 2006.175.08:02:21.91#ibcon#read 3, iclass 14, count 0 2006.175.08:02:21.91#ibcon#about to read 4, iclass 14, count 0 2006.175.08:02:21.91#ibcon#read 4, iclass 14, count 0 2006.175.08:02:21.91#ibcon#about to read 5, iclass 14, count 0 2006.175.08:02:21.91#ibcon#read 5, iclass 14, count 0 2006.175.08:02:21.91#ibcon#about to read 6, iclass 14, count 0 2006.175.08:02:21.91#ibcon#read 6, iclass 14, count 0 2006.175.08:02:21.91#ibcon#end of sib2, iclass 14, count 0 2006.175.08:02:21.91#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:02:21.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:02:21.91#ibcon#[27=USB\r\n] 2006.175.08:02:21.91#ibcon#*before write, iclass 14, count 0 2006.175.08:02:21.91#ibcon#enter sib2, iclass 14, count 0 2006.175.08:02:21.91#ibcon#flushed, iclass 14, count 0 2006.175.08:02:21.91#ibcon#about to write, iclass 14, count 0 2006.175.08:02:21.91#ibcon#wrote, iclass 14, count 0 2006.175.08:02:21.91#ibcon#about to read 3, iclass 14, count 0 2006.175.08:02:21.94#ibcon#read 3, iclass 14, count 0 2006.175.08:02:21.94#ibcon#about to read 4, iclass 14, count 0 2006.175.08:02:21.94#ibcon#read 4, iclass 14, count 0 2006.175.08:02:21.94#ibcon#about to read 5, iclass 14, count 0 2006.175.08:02:21.94#ibcon#read 5, iclass 14, count 0 2006.175.08:02:21.94#ibcon#about to read 6, iclass 14, count 0 2006.175.08:02:21.94#ibcon#read 6, iclass 14, count 0 2006.175.08:02:21.94#ibcon#end of sib2, iclass 14, count 0 2006.175.08:02:21.94#ibcon#*after write, iclass 14, count 0 2006.175.08:02:21.94#ibcon#*before return 0, iclass 14, count 0 2006.175.08:02:21.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:21.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:02:21.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:02:21.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:02:21.94$vc4f8/vblo=5,744.99 2006.175.08:02:21.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.08:02:21.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.08:02:21.94#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:21.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:21.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:21.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:21.94#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:02:21.94#ibcon#first serial, iclass 16, count 0 2006.175.08:02:21.94#ibcon#enter sib2, iclass 16, count 0 2006.175.08:02:21.94#ibcon#flushed, iclass 16, count 0 2006.175.08:02:21.94#ibcon#about to write, iclass 16, count 0 2006.175.08:02:21.94#ibcon#wrote, iclass 16, count 0 2006.175.08:02:21.94#ibcon#about to read 3, iclass 16, count 0 2006.175.08:02:21.96#ibcon#read 3, iclass 16, count 0 2006.175.08:02:21.96#ibcon#about to read 4, iclass 16, count 0 2006.175.08:02:21.96#ibcon#read 4, iclass 16, count 0 2006.175.08:02:21.96#ibcon#about to read 5, iclass 16, count 0 2006.175.08:02:21.96#ibcon#read 5, iclass 16, count 0 2006.175.08:02:21.96#ibcon#about to read 6, iclass 16, count 0 2006.175.08:02:21.96#ibcon#read 6, iclass 16, count 0 2006.175.08:02:21.96#ibcon#end of sib2, iclass 16, count 0 2006.175.08:02:21.96#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:02:21.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:02:21.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:02:21.96#ibcon#*before write, iclass 16, count 0 2006.175.08:02:21.96#ibcon#enter sib2, iclass 16, count 0 2006.175.08:02:21.96#ibcon#flushed, iclass 16, count 0 2006.175.08:02:21.96#ibcon#about to write, iclass 16, count 0 2006.175.08:02:21.96#ibcon#wrote, iclass 16, count 0 2006.175.08:02:21.96#ibcon#about to read 3, iclass 16, count 0 2006.175.08:02:22.00#ibcon#read 3, iclass 16, count 0 2006.175.08:02:22.00#ibcon#about to read 4, iclass 16, count 0 2006.175.08:02:22.00#ibcon#read 4, iclass 16, count 0 2006.175.08:02:22.00#ibcon#about to read 5, iclass 16, count 0 2006.175.08:02:22.00#ibcon#read 5, iclass 16, count 0 2006.175.08:02:22.00#ibcon#about to read 6, iclass 16, count 0 2006.175.08:02:22.00#ibcon#read 6, iclass 16, count 0 2006.175.08:02:22.00#ibcon#end of sib2, iclass 16, count 0 2006.175.08:02:22.00#ibcon#*after write, iclass 16, count 0 2006.175.08:02:22.00#ibcon#*before return 0, iclass 16, count 0 2006.175.08:02:22.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:22.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:02:22.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:02:22.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:02:22.00$vc4f8/vb=5,4 2006.175.08:02:22.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.08:02:22.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.08:02:22.00#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:22.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:22.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:22.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:22.06#ibcon#enter wrdev, iclass 18, count 2 2006.175.08:02:22.06#ibcon#first serial, iclass 18, count 2 2006.175.08:02:22.06#ibcon#enter sib2, iclass 18, count 2 2006.175.08:02:22.06#ibcon#flushed, iclass 18, count 2 2006.175.08:02:22.06#ibcon#about to write, iclass 18, count 2 2006.175.08:02:22.06#ibcon#wrote, iclass 18, count 2 2006.175.08:02:22.06#ibcon#about to read 3, iclass 18, count 2 2006.175.08:02:22.08#ibcon#read 3, iclass 18, count 2 2006.175.08:02:22.08#ibcon#about to read 4, iclass 18, count 2 2006.175.08:02:22.08#ibcon#read 4, iclass 18, count 2 2006.175.08:02:22.08#ibcon#about to read 5, iclass 18, count 2 2006.175.08:02:22.08#ibcon#read 5, iclass 18, count 2 2006.175.08:02:22.08#ibcon#about to read 6, iclass 18, count 2 2006.175.08:02:22.08#ibcon#read 6, iclass 18, count 2 2006.175.08:02:22.08#ibcon#end of sib2, iclass 18, count 2 2006.175.08:02:22.08#ibcon#*mode == 0, iclass 18, count 2 2006.175.08:02:22.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.08:02:22.08#ibcon#[27=AT05-04\r\n] 2006.175.08:02:22.08#ibcon#*before write, iclass 18, count 2 2006.175.08:02:22.08#ibcon#enter sib2, iclass 18, count 2 2006.175.08:02:22.08#ibcon#flushed, iclass 18, count 2 2006.175.08:02:22.08#ibcon#about to write, iclass 18, count 2 2006.175.08:02:22.08#ibcon#wrote, iclass 18, count 2 2006.175.08:02:22.08#ibcon#about to read 3, iclass 18, count 2 2006.175.08:02:22.10#abcon#<5=/05 3.6 6.1 25.86 691007.4\r\n> 2006.175.08:02:22.11#ibcon#read 3, iclass 18, count 2 2006.175.08:02:22.11#ibcon#about to read 4, iclass 18, count 2 2006.175.08:02:22.11#ibcon#read 4, iclass 18, count 2 2006.175.08:02:22.11#ibcon#about to read 5, iclass 18, count 2 2006.175.08:02:22.11#ibcon#read 5, iclass 18, count 2 2006.175.08:02:22.11#ibcon#about to read 6, iclass 18, count 2 2006.175.08:02:22.11#ibcon#read 6, iclass 18, count 2 2006.175.08:02:22.11#ibcon#end of sib2, iclass 18, count 2 2006.175.08:02:22.11#ibcon#*after write, iclass 18, count 2 2006.175.08:02:22.11#ibcon#*before return 0, iclass 18, count 2 2006.175.08:02:22.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:22.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:02:22.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.08:02:22.11#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:22.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:22.12#abcon#{5=INTERFACE CLEAR} 2006.175.08:02:22.18#abcon#[5=S1D000X0/0*\r\n] 2006.175.08:02:22.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:22.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:22.23#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:02:22.23#ibcon#first serial, iclass 18, count 0 2006.175.08:02:22.23#ibcon#enter sib2, iclass 18, count 0 2006.175.08:02:22.23#ibcon#flushed, iclass 18, count 0 2006.175.08:02:22.23#ibcon#about to write, iclass 18, count 0 2006.175.08:02:22.23#ibcon#wrote, iclass 18, count 0 2006.175.08:02:22.23#ibcon#about to read 3, iclass 18, count 0 2006.175.08:02:22.25#ibcon#read 3, iclass 18, count 0 2006.175.08:02:22.25#ibcon#about to read 4, iclass 18, count 0 2006.175.08:02:22.25#ibcon#read 4, iclass 18, count 0 2006.175.08:02:22.25#ibcon#about to read 5, iclass 18, count 0 2006.175.08:02:22.25#ibcon#read 5, iclass 18, count 0 2006.175.08:02:22.25#ibcon#about to read 6, iclass 18, count 0 2006.175.08:02:22.25#ibcon#read 6, iclass 18, count 0 2006.175.08:02:22.25#ibcon#end of sib2, iclass 18, count 0 2006.175.08:02:22.25#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:02:22.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:02:22.25#ibcon#[27=USB\r\n] 2006.175.08:02:22.25#ibcon#*before write, iclass 18, count 0 2006.175.08:02:22.25#ibcon#enter sib2, iclass 18, count 0 2006.175.08:02:22.25#ibcon#flushed, iclass 18, count 0 2006.175.08:02:22.25#ibcon#about to write, iclass 18, count 0 2006.175.08:02:22.25#ibcon#wrote, iclass 18, count 0 2006.175.08:02:22.25#ibcon#about to read 3, iclass 18, count 0 2006.175.08:02:22.28#ibcon#read 3, iclass 18, count 0 2006.175.08:02:22.28#ibcon#about to read 4, iclass 18, count 0 2006.175.08:02:22.28#ibcon#read 4, iclass 18, count 0 2006.175.08:02:22.28#ibcon#about to read 5, iclass 18, count 0 2006.175.08:02:22.28#ibcon#read 5, iclass 18, count 0 2006.175.08:02:22.28#ibcon#about to read 6, iclass 18, count 0 2006.175.08:02:22.28#ibcon#read 6, iclass 18, count 0 2006.175.08:02:22.28#ibcon#end of sib2, iclass 18, count 0 2006.175.08:02:22.28#ibcon#*after write, iclass 18, count 0 2006.175.08:02:22.28#ibcon#*before return 0, iclass 18, count 0 2006.175.08:02:22.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:22.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:02:22.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:02:22.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:02:22.28$vc4f8/vblo=6,752.99 2006.175.08:02:22.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.08:02:22.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.08:02:22.28#ibcon#ireg 17 cls_cnt 0 2006.175.08:02:22.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:22.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:22.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:22.28#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:02:22.28#ibcon#first serial, iclass 24, count 0 2006.175.08:02:22.28#ibcon#enter sib2, iclass 24, count 0 2006.175.08:02:22.28#ibcon#flushed, iclass 24, count 0 2006.175.08:02:22.28#ibcon#about to write, iclass 24, count 0 2006.175.08:02:22.28#ibcon#wrote, iclass 24, count 0 2006.175.08:02:22.28#ibcon#about to read 3, iclass 24, count 0 2006.175.08:02:22.30#ibcon#read 3, iclass 24, count 0 2006.175.08:02:22.30#ibcon#about to read 4, iclass 24, count 0 2006.175.08:02:22.30#ibcon#read 4, iclass 24, count 0 2006.175.08:02:22.30#ibcon#about to read 5, iclass 24, count 0 2006.175.08:02:22.30#ibcon#read 5, iclass 24, count 0 2006.175.08:02:22.30#ibcon#about to read 6, iclass 24, count 0 2006.175.08:02:22.30#ibcon#read 6, iclass 24, count 0 2006.175.08:02:22.30#ibcon#end of sib2, iclass 24, count 0 2006.175.08:02:22.30#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:02:22.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:02:22.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:02:22.30#ibcon#*before write, iclass 24, count 0 2006.175.08:02:22.30#ibcon#enter sib2, iclass 24, count 0 2006.175.08:02:22.30#ibcon#flushed, iclass 24, count 0 2006.175.08:02:22.30#ibcon#about to write, iclass 24, count 0 2006.175.08:02:22.30#ibcon#wrote, iclass 24, count 0 2006.175.08:02:22.30#ibcon#about to read 3, iclass 24, count 0 2006.175.08:02:22.34#ibcon#read 3, iclass 24, count 0 2006.175.08:02:22.34#ibcon#about to read 4, iclass 24, count 0 2006.175.08:02:22.34#ibcon#read 4, iclass 24, count 0 2006.175.08:02:22.34#ibcon#about to read 5, iclass 24, count 0 2006.175.08:02:22.34#ibcon#read 5, iclass 24, count 0 2006.175.08:02:22.34#ibcon#about to read 6, iclass 24, count 0 2006.175.08:02:22.34#ibcon#read 6, iclass 24, count 0 2006.175.08:02:22.34#ibcon#end of sib2, iclass 24, count 0 2006.175.08:02:22.34#ibcon#*after write, iclass 24, count 0 2006.175.08:02:22.34#ibcon#*before return 0, iclass 24, count 0 2006.175.08:02:22.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:22.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:02:22.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:02:22.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:02:22.34$vc4f8/vb=6,4 2006.175.08:02:22.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.08:02:22.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.08:02:22.34#ibcon#ireg 11 cls_cnt 2 2006.175.08:02:22.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:22.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:22.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:22.40#ibcon#enter wrdev, iclass 26, count 2 2006.175.08:02:22.40#ibcon#first serial, iclass 26, count 2 2006.175.08:02:22.40#ibcon#enter sib2, iclass 26, count 2 2006.175.08:02:22.40#ibcon#flushed, iclass 26, count 2 2006.175.08:02:22.40#ibcon#about to write, iclass 26, count 2 2006.175.08:02:22.40#ibcon#wrote, iclass 26, count 2 2006.175.08:02:22.40#ibcon#about to read 3, iclass 26, count 2 2006.175.08:02:22.42#ibcon#read 3, iclass 26, count 2 2006.175.08:02:22.42#ibcon#about to read 4, iclass 26, count 2 2006.175.08:02:22.42#ibcon#read 4, iclass 26, count 2 2006.175.08:02:22.42#ibcon#about to read 5, iclass 26, count 2 2006.175.08:02:22.42#ibcon#read 5, iclass 26, count 2 2006.175.08:02:22.42#ibcon#about to read 6, iclass 26, count 2 2006.175.08:02:22.42#ibcon#read 6, iclass 26, count 2 2006.175.08:02:22.42#ibcon#end of sib2, iclass 26, count 2 2006.175.08:02:22.42#ibcon#*mode == 0, iclass 26, count 2 2006.175.08:02:22.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.08:02:22.42#ibcon#[27=AT06-04\r\n] 2006.175.08:02:22.42#ibcon#*before write, iclass 26, count 2 2006.175.08:02:22.42#ibcon#enter sib2, iclass 26, count 2 2006.175.08:02:22.42#ibcon#flushed, iclass 26, count 2 2006.175.08:02:22.42#ibcon#about to write, iclass 26, count 2 2006.175.08:02:22.42#ibcon#wrote, iclass 26, count 2 2006.175.08:02:22.42#ibcon#about to read 3, iclass 26, count 2 2006.175.08:02:22.45#ibcon#read 3, iclass 26, count 2 2006.175.08:02:22.45#ibcon#about to read 4, iclass 26, count 2 2006.175.08:02:22.45#ibcon#read 4, iclass 26, count 2 2006.175.08:02:22.45#ibcon#about to read 5, iclass 26, count 2 2006.175.08:02:22.45#ibcon#read 5, iclass 26, count 2 2006.175.08:02:22.45#ibcon#about to read 6, iclass 26, count 2 2006.175.08:02:22.45#ibcon#read 6, iclass 26, count 2 2006.175.08:02:22.45#ibcon#end of sib2, iclass 26, count 2 2006.175.08:02:22.45#ibcon#*after write, iclass 26, count 2 2006.175.08:02:22.45#ibcon#*before return 0, iclass 26, count 2 2006.175.08:02:22.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:22.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:02:22.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.08:02:22.45#ibcon#ireg 7 cls_cnt 0 2006.175.08:02:22.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:22.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:22.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:22.59#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:02:22.59#ibcon#first serial, iclass 26, count 0 2006.175.08:02:22.59#ibcon#enter sib2, iclass 26, count 0 2006.175.08:02:22.59#ibcon#flushed, iclass 26, count 0 2006.175.08:02:22.59#ibcon#about to write, iclass 26, count 0 2006.175.08:02:22.59#ibcon#wrote, iclass 26, count 0 2006.175.08:02:22.59#ibcon#about to read 3, iclass 26, count 0 2006.175.08:02:22.60#ibcon#read 3, iclass 26, count 0 2006.175.08:02:22.60#ibcon#about to read 4, iclass 26, count 0 2006.175.08:02:22.60#ibcon#read 4, iclass 26, count 0 2006.175.08:02:22.60#ibcon#about to read 5, iclass 26, count 0 2006.175.08:02:22.60#ibcon#read 5, iclass 26, count 0 2006.175.08:02:22.60#ibcon#about to read 6, iclass 26, count 0 2006.175.08:02:22.60#ibcon#read 6, iclass 26, count 0 2006.175.08:02:22.60#ibcon#end of sib2, iclass 26, count 0 2006.175.08:02:22.60#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:02:22.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:02:22.60#ibcon#[27=USB\r\n] 2006.175.08:02:22.60#ibcon#*before write, iclass 26, count 0 2006.175.08:02:22.60#ibcon#enter sib2, iclass 26, count 0 2006.175.08:02:22.60#ibcon#flushed, iclass 26, count 0 2006.175.08:02:22.60#ibcon#about to write, iclass 26, count 0 2006.175.08:02:22.60#ibcon#wrote, iclass 26, count 0 2006.175.08:02:22.60#ibcon#about to read 3, iclass 26, count 0 2006.175.08:02:22.63#ibcon#read 3, iclass 26, count 0 2006.175.08:02:22.63#ibcon#about to read 4, iclass 26, count 0 2006.175.08:02:22.63#ibcon#read 4, iclass 26, count 0 2006.175.08:02:22.63#ibcon#about to read 5, iclass 26, count 0 2006.175.08:02:22.63#ibcon#read 5, iclass 26, count 0 2006.175.08:02:22.63#ibcon#about to read 6, iclass 26, count 0 2006.175.08:02:22.63#ibcon#read 6, iclass 26, count 0 2006.175.08:02:22.63#ibcon#end of sib2, iclass 26, count 0 2006.175.08:02:22.63#ibcon#*after write, iclass 26, count 0 2006.175.08:02:22.63#ibcon#*before return 0, iclass 26, count 0 2006.175.08:02:22.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:22.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:02:22.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:02:22.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:02:22.63$vc4f8/vabw=wide 2006.175.08:02:22.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.08:02:22.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.08:02:22.63#ibcon#ireg 8 cls_cnt 0 2006.175.08:02:22.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:22.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:22.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:22.63#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:02:22.63#ibcon#first serial, iclass 28, count 0 2006.175.08:02:22.63#ibcon#enter sib2, iclass 28, count 0 2006.175.08:02:22.63#ibcon#flushed, iclass 28, count 0 2006.175.08:02:22.63#ibcon#about to write, iclass 28, count 0 2006.175.08:02:22.63#ibcon#wrote, iclass 28, count 0 2006.175.08:02:22.63#ibcon#about to read 3, iclass 28, count 0 2006.175.08:02:22.65#ibcon#read 3, iclass 28, count 0 2006.175.08:02:22.65#ibcon#about to read 4, iclass 28, count 0 2006.175.08:02:22.65#ibcon#read 4, iclass 28, count 0 2006.175.08:02:22.65#ibcon#about to read 5, iclass 28, count 0 2006.175.08:02:22.65#ibcon#read 5, iclass 28, count 0 2006.175.08:02:22.65#ibcon#about to read 6, iclass 28, count 0 2006.175.08:02:22.65#ibcon#read 6, iclass 28, count 0 2006.175.08:02:22.65#ibcon#end of sib2, iclass 28, count 0 2006.175.08:02:22.65#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:02:22.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:02:22.65#ibcon#[25=BW32\r\n] 2006.175.08:02:22.65#ibcon#*before write, iclass 28, count 0 2006.175.08:02:22.65#ibcon#enter sib2, iclass 28, count 0 2006.175.08:02:22.65#ibcon#flushed, iclass 28, count 0 2006.175.08:02:22.65#ibcon#about to write, iclass 28, count 0 2006.175.08:02:22.65#ibcon#wrote, iclass 28, count 0 2006.175.08:02:22.65#ibcon#about to read 3, iclass 28, count 0 2006.175.08:02:22.68#ibcon#read 3, iclass 28, count 0 2006.175.08:02:22.68#ibcon#about to read 4, iclass 28, count 0 2006.175.08:02:22.68#ibcon#read 4, iclass 28, count 0 2006.175.08:02:22.68#ibcon#about to read 5, iclass 28, count 0 2006.175.08:02:22.68#ibcon#read 5, iclass 28, count 0 2006.175.08:02:22.68#ibcon#about to read 6, iclass 28, count 0 2006.175.08:02:22.68#ibcon#read 6, iclass 28, count 0 2006.175.08:02:22.68#ibcon#end of sib2, iclass 28, count 0 2006.175.08:02:22.68#ibcon#*after write, iclass 28, count 0 2006.175.08:02:22.68#ibcon#*before return 0, iclass 28, count 0 2006.175.08:02:22.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:22.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:02:22.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:02:22.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:02:22.68$vc4f8/vbbw=wide 2006.175.08:02:22.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.08:02:22.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.08:02:22.68#ibcon#ireg 8 cls_cnt 0 2006.175.08:02:22.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:02:22.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:02:22.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:02:22.75#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:02:22.75#ibcon#first serial, iclass 30, count 0 2006.175.08:02:22.75#ibcon#enter sib2, iclass 30, count 0 2006.175.08:02:22.75#ibcon#flushed, iclass 30, count 0 2006.175.08:02:22.75#ibcon#about to write, iclass 30, count 0 2006.175.08:02:22.75#ibcon#wrote, iclass 30, count 0 2006.175.08:02:22.75#ibcon#about to read 3, iclass 30, count 0 2006.175.08:02:22.77#ibcon#read 3, iclass 30, count 0 2006.175.08:02:22.77#ibcon#about to read 4, iclass 30, count 0 2006.175.08:02:22.77#ibcon#read 4, iclass 30, count 0 2006.175.08:02:22.77#ibcon#about to read 5, iclass 30, count 0 2006.175.08:02:22.77#ibcon#read 5, iclass 30, count 0 2006.175.08:02:22.77#ibcon#about to read 6, iclass 30, count 0 2006.175.08:02:22.77#ibcon#read 6, iclass 30, count 0 2006.175.08:02:22.77#ibcon#end of sib2, iclass 30, count 0 2006.175.08:02:22.77#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:02:22.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:02:22.77#ibcon#[27=BW32\r\n] 2006.175.08:02:22.77#ibcon#*before write, iclass 30, count 0 2006.175.08:02:22.77#ibcon#enter sib2, iclass 30, count 0 2006.175.08:02:22.77#ibcon#flushed, iclass 30, count 0 2006.175.08:02:22.77#ibcon#about to write, iclass 30, count 0 2006.175.08:02:22.77#ibcon#wrote, iclass 30, count 0 2006.175.08:02:22.77#ibcon#about to read 3, iclass 30, count 0 2006.175.08:02:22.80#ibcon#read 3, iclass 30, count 0 2006.175.08:02:22.80#ibcon#about to read 4, iclass 30, count 0 2006.175.08:02:22.80#ibcon#read 4, iclass 30, count 0 2006.175.08:02:22.80#ibcon#about to read 5, iclass 30, count 0 2006.175.08:02:22.80#ibcon#read 5, iclass 30, count 0 2006.175.08:02:22.80#ibcon#about to read 6, iclass 30, count 0 2006.175.08:02:22.80#ibcon#read 6, iclass 30, count 0 2006.175.08:02:22.80#ibcon#end of sib2, iclass 30, count 0 2006.175.08:02:22.80#ibcon#*after write, iclass 30, count 0 2006.175.08:02:22.80#ibcon#*before return 0, iclass 30, count 0 2006.175.08:02:22.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:02:22.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:02:22.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:02:22.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:02:22.80$4f8m12a/ifd4f 2006.175.08:02:22.80$ifd4f/lo= 2006.175.08:02:22.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:02:22.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:02:22.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:02:22.80$ifd4f/patch= 2006.175.08:02:22.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:02:22.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:02:22.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:02:22.81$4f8m12a/"form=m,16.000,1:2 2006.175.08:02:22.81$4f8m12a/"tpicd 2006.175.08:02:22.81$4f8m12a/echo=off 2006.175.08:02:22.81$4f8m12a/xlog=off 2006.175.08:02:22.81:!2006.175.08:02:50 2006.175.08:02:33.14#trakl#Source acquired 2006.175.08:02:35.14#flagr#flagr/antenna,acquired 2006.175.08:02:50.01:preob 2006.175.08:02:51.14/onsource/TRACKING 2006.175.08:02:51.14:!2006.175.08:03:00 2006.175.08:03:00.00:data_valid=on 2006.175.08:03:00.00:midob 2006.175.08:03:00.14/onsource/TRACKING 2006.175.08:03:00.14/wx/25.86,1007.4,69 2006.175.08:03:00.36/cable/+6.4804E-03 2006.175.08:03:01.45/va/01,08,usb,yes,29,30 2006.175.08:03:01.45/va/02,07,usb,yes,29,30 2006.175.08:03:01.45/va/03,06,usb,yes,30,31 2006.175.08:03:01.45/va/04,07,usb,yes,29,32 2006.175.08:03:01.45/va/05,07,usb,yes,30,32 2006.175.08:03:01.45/va/06,06,usb,yes,29,29 2006.175.08:03:01.45/va/07,06,usb,yes,29,29 2006.175.08:03:01.45/va/08,06,usb,yes,32,31 2006.175.08:03:01.68/valo/01,532.99,yes,locked 2006.175.08:03:01.68/valo/02,572.99,yes,locked 2006.175.08:03:01.68/valo/03,672.99,yes,locked 2006.175.08:03:01.68/valo/04,832.99,yes,locked 2006.175.08:03:01.68/valo/05,652.99,yes,locked 2006.175.08:03:01.68/valo/06,772.99,yes,locked 2006.175.08:03:01.68/valo/07,832.99,yes,locked 2006.175.08:03:01.68/valo/08,852.99,yes,locked 2006.175.08:03:02.77/vb/01,04,usb,yes,29,28 2006.175.08:03:02.77/vb/02,04,usb,yes,31,32 2006.175.08:03:02.77/vb/03,04,usb,yes,27,31 2006.175.08:03:02.77/vb/04,04,usb,yes,28,28 2006.175.08:03:02.77/vb/05,04,usb,yes,26,30 2006.175.08:03:02.77/vb/06,04,usb,yes,27,30 2006.175.08:03:02.77/vb/07,04,usb,yes,29,29 2006.175.08:03:02.77/vb/08,04,usb,yes,27,30 2006.175.08:03:03.00/vblo/01,632.99,yes,locked 2006.175.08:03:03.00/vblo/02,640.99,yes,locked 2006.175.08:03:03.00/vblo/03,656.99,yes,locked 2006.175.08:03:03.00/vblo/04,712.99,yes,locked 2006.175.08:03:03.00/vblo/05,744.99,yes,locked 2006.175.08:03:03.00/vblo/06,752.99,yes,locked 2006.175.08:03:03.00/vblo/07,734.99,yes,locked 2006.175.08:03:03.00/vblo/08,744.99,yes,locked 2006.175.08:03:03.15/vabw/8 2006.175.08:03:03.30/vbbw/8 2006.175.08:03:03.39/xfe/off,on,14.5 2006.175.08:03:03.76/ifatt/23,28,28,28 2006.175.08:03:04.07/fmout-gps/S +3.75E-07 2006.175.08:03:04.15:!2006.175.08:04:00 2006.175.08:04:00.01:data_valid=off 2006.175.08:04:00.02:postob 2006.175.08:04:00.16/cable/+6.4779E-03 2006.175.08:04:00.17/wx/25.86,1007.4,69 2006.175.08:04:01.07/fmout-gps/S +3.75E-07 2006.175.08:04:01.08:scan_name=175-0804,k06175,60 2006.175.08:04:01.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.175.08:04:01.14#flagr#flagr/antenna,new-source 2006.175.08:04:02.14:checkk5 2006.175.08:04:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:04:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:04:06.27/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:04:06.65/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:04:07.02/chk_obsdata//k5ts1/T1750803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:04:07.39/chk_obsdata//k5ts2/T1750803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:04:07.77/chk_obsdata//k5ts3/T1750803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:04:08.14/chk_obsdata//k5ts4/T1750803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:04:08.83/k5log//k5ts1_log_newline 2006.175.08:04:09.52/k5log//k5ts2_log_newline 2006.175.08:04:10.21/k5log//k5ts3_log_newline 2006.175.08:04:10.90/k5log//k5ts4_log_newline 2006.175.08:04:10.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:04:10.93:4f8m12a=2 2006.175.08:04:10.93$4f8m12a/echo=on 2006.175.08:04:10.93$4f8m12a/pcalon 2006.175.08:04:10.93$pcalon/"no phase cal control is implemented here 2006.175.08:04:10.93$4f8m12a/"tpicd=stop 2006.175.08:04:10.93$4f8m12a/vc4f8 2006.175.08:04:10.93$vc4f8/valo=1,532.99 2006.175.08:04:10.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.08:04:10.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.08:04:10.93#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:10.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:10.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:10.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:10.93#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:04:10.93#ibcon#first serial, iclass 37, count 0 2006.175.08:04:10.93#ibcon#enter sib2, iclass 37, count 0 2006.175.08:04:10.93#ibcon#flushed, iclass 37, count 0 2006.175.08:04:10.93#ibcon#about to write, iclass 37, count 0 2006.175.08:04:10.93#ibcon#wrote, iclass 37, count 0 2006.175.08:04:10.93#ibcon#about to read 3, iclass 37, count 0 2006.175.08:04:10.94#ibcon#read 3, iclass 37, count 0 2006.175.08:04:10.94#ibcon#about to read 4, iclass 37, count 0 2006.175.08:04:10.94#ibcon#read 4, iclass 37, count 0 2006.175.08:04:10.94#ibcon#about to read 5, iclass 37, count 0 2006.175.08:04:10.94#ibcon#read 5, iclass 37, count 0 2006.175.08:04:10.94#ibcon#about to read 6, iclass 37, count 0 2006.175.08:04:10.94#ibcon#read 6, iclass 37, count 0 2006.175.08:04:10.94#ibcon#end of sib2, iclass 37, count 0 2006.175.08:04:10.94#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:04:10.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:04:10.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:04:10.94#ibcon#*before write, iclass 37, count 0 2006.175.08:04:10.94#ibcon#enter sib2, iclass 37, count 0 2006.175.08:04:10.94#ibcon#flushed, iclass 37, count 0 2006.175.08:04:10.94#ibcon#about to write, iclass 37, count 0 2006.175.08:04:10.94#ibcon#wrote, iclass 37, count 0 2006.175.08:04:10.94#ibcon#about to read 3, iclass 37, count 0 2006.175.08:04:10.99#ibcon#read 3, iclass 37, count 0 2006.175.08:04:10.99#ibcon#about to read 4, iclass 37, count 0 2006.175.08:04:10.99#ibcon#read 4, iclass 37, count 0 2006.175.08:04:10.99#ibcon#about to read 5, iclass 37, count 0 2006.175.08:04:10.99#ibcon#read 5, iclass 37, count 0 2006.175.08:04:10.99#ibcon#about to read 6, iclass 37, count 0 2006.175.08:04:10.99#ibcon#read 6, iclass 37, count 0 2006.175.08:04:10.99#ibcon#end of sib2, iclass 37, count 0 2006.175.08:04:10.99#ibcon#*after write, iclass 37, count 0 2006.175.08:04:10.99#ibcon#*before return 0, iclass 37, count 0 2006.175.08:04:10.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:10.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:10.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:04:10.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:04:10.99$vc4f8/va=1,8 2006.175.08:04:10.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.175.08:04:10.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.175.08:04:10.99#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:10.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:04:10.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:04:10.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:04:10.99#ibcon#enter wrdev, iclass 39, count 2 2006.175.08:04:10.99#ibcon#first serial, iclass 39, count 2 2006.175.08:04:10.99#ibcon#enter sib2, iclass 39, count 2 2006.175.08:04:10.99#ibcon#flushed, iclass 39, count 2 2006.175.08:04:10.99#ibcon#about to write, iclass 39, count 2 2006.175.08:04:10.99#ibcon#wrote, iclass 39, count 2 2006.175.08:04:10.99#ibcon#about to read 3, iclass 39, count 2 2006.175.08:04:11.01#ibcon#read 3, iclass 39, count 2 2006.175.08:04:11.01#ibcon#about to read 4, iclass 39, count 2 2006.175.08:04:11.01#ibcon#read 4, iclass 39, count 2 2006.175.08:04:11.01#ibcon#about to read 5, iclass 39, count 2 2006.175.08:04:11.01#ibcon#read 5, iclass 39, count 2 2006.175.08:04:11.01#ibcon#about to read 6, iclass 39, count 2 2006.175.08:04:11.01#ibcon#read 6, iclass 39, count 2 2006.175.08:04:11.01#ibcon#end of sib2, iclass 39, count 2 2006.175.08:04:11.01#ibcon#*mode == 0, iclass 39, count 2 2006.175.08:04:11.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.175.08:04:11.01#ibcon#[25=AT01-08\r\n] 2006.175.08:04:11.01#ibcon#*before write, iclass 39, count 2 2006.175.08:04:11.01#ibcon#enter sib2, iclass 39, count 2 2006.175.08:04:11.01#ibcon#flushed, iclass 39, count 2 2006.175.08:04:11.01#ibcon#about to write, iclass 39, count 2 2006.175.08:04:11.01#ibcon#wrote, iclass 39, count 2 2006.175.08:04:11.01#ibcon#about to read 3, iclass 39, count 2 2006.175.08:04:11.05#ibcon#read 3, iclass 39, count 2 2006.175.08:04:11.05#ibcon#about to read 4, iclass 39, count 2 2006.175.08:04:11.05#ibcon#read 4, iclass 39, count 2 2006.175.08:04:11.05#ibcon#about to read 5, iclass 39, count 2 2006.175.08:04:11.05#ibcon#read 5, iclass 39, count 2 2006.175.08:04:11.05#ibcon#about to read 6, iclass 39, count 2 2006.175.08:04:11.05#ibcon#read 6, iclass 39, count 2 2006.175.08:04:11.05#ibcon#end of sib2, iclass 39, count 2 2006.175.08:04:11.05#ibcon#*after write, iclass 39, count 2 2006.175.08:04:11.05#ibcon#*before return 0, iclass 39, count 2 2006.175.08:04:11.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:04:11.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:04:11.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.175.08:04:11.05#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:11.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:04:11.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:04:11.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:04:11.16#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:04:11.16#ibcon#first serial, iclass 39, count 0 2006.175.08:04:11.16#ibcon#enter sib2, iclass 39, count 0 2006.175.08:04:11.16#ibcon#flushed, iclass 39, count 0 2006.175.08:04:11.16#ibcon#about to write, iclass 39, count 0 2006.175.08:04:11.16#ibcon#wrote, iclass 39, count 0 2006.175.08:04:11.16#ibcon#about to read 3, iclass 39, count 0 2006.175.08:04:11.18#ibcon#read 3, iclass 39, count 0 2006.175.08:04:11.18#ibcon#about to read 4, iclass 39, count 0 2006.175.08:04:11.18#ibcon#read 4, iclass 39, count 0 2006.175.08:04:11.18#ibcon#about to read 5, iclass 39, count 0 2006.175.08:04:11.18#ibcon#read 5, iclass 39, count 0 2006.175.08:04:11.18#ibcon#about to read 6, iclass 39, count 0 2006.175.08:04:11.18#ibcon#read 6, iclass 39, count 0 2006.175.08:04:11.18#ibcon#end of sib2, iclass 39, count 0 2006.175.08:04:11.18#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:04:11.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:04:11.18#ibcon#[25=USB\r\n] 2006.175.08:04:11.18#ibcon#*before write, iclass 39, count 0 2006.175.08:04:11.18#ibcon#enter sib2, iclass 39, count 0 2006.175.08:04:11.18#ibcon#flushed, iclass 39, count 0 2006.175.08:04:11.18#ibcon#about to write, iclass 39, count 0 2006.175.08:04:11.18#ibcon#wrote, iclass 39, count 0 2006.175.08:04:11.18#ibcon#about to read 3, iclass 39, count 0 2006.175.08:04:11.21#ibcon#read 3, iclass 39, count 0 2006.175.08:04:11.21#ibcon#about to read 4, iclass 39, count 0 2006.175.08:04:11.21#ibcon#read 4, iclass 39, count 0 2006.175.08:04:11.21#ibcon#about to read 5, iclass 39, count 0 2006.175.08:04:11.21#ibcon#read 5, iclass 39, count 0 2006.175.08:04:11.21#ibcon#about to read 6, iclass 39, count 0 2006.175.08:04:11.21#ibcon#read 6, iclass 39, count 0 2006.175.08:04:11.21#ibcon#end of sib2, iclass 39, count 0 2006.175.08:04:11.21#ibcon#*after write, iclass 39, count 0 2006.175.08:04:11.21#ibcon#*before return 0, iclass 39, count 0 2006.175.08:04:11.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:04:11.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:04:11.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:04:11.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:04:11.21$vc4f8/valo=2,572.99 2006.175.08:04:11.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.08:04:11.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.08:04:11.21#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:11.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:04:11.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:04:11.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:04:11.21#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:04:11.21#ibcon#first serial, iclass 3, count 0 2006.175.08:04:11.21#ibcon#enter sib2, iclass 3, count 0 2006.175.08:04:11.21#ibcon#flushed, iclass 3, count 0 2006.175.08:04:11.21#ibcon#about to write, iclass 3, count 0 2006.175.08:04:11.21#ibcon#wrote, iclass 3, count 0 2006.175.08:04:11.21#ibcon#about to read 3, iclass 3, count 0 2006.175.08:04:11.23#ibcon#read 3, iclass 3, count 0 2006.175.08:04:11.23#ibcon#about to read 4, iclass 3, count 0 2006.175.08:04:11.23#ibcon#read 4, iclass 3, count 0 2006.175.08:04:11.23#ibcon#about to read 5, iclass 3, count 0 2006.175.08:04:11.23#ibcon#read 5, iclass 3, count 0 2006.175.08:04:11.23#ibcon#about to read 6, iclass 3, count 0 2006.175.08:04:11.23#ibcon#read 6, iclass 3, count 0 2006.175.08:04:11.23#ibcon#end of sib2, iclass 3, count 0 2006.175.08:04:11.23#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:04:11.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:04:11.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:04:11.23#ibcon#*before write, iclass 3, count 0 2006.175.08:04:11.23#ibcon#enter sib2, iclass 3, count 0 2006.175.08:04:11.23#ibcon#flushed, iclass 3, count 0 2006.175.08:04:11.23#ibcon#about to write, iclass 3, count 0 2006.175.08:04:11.23#ibcon#wrote, iclass 3, count 0 2006.175.08:04:11.23#ibcon#about to read 3, iclass 3, count 0 2006.175.08:04:11.27#ibcon#read 3, iclass 3, count 0 2006.175.08:04:11.27#ibcon#about to read 4, iclass 3, count 0 2006.175.08:04:11.27#ibcon#read 4, iclass 3, count 0 2006.175.08:04:11.27#ibcon#about to read 5, iclass 3, count 0 2006.175.08:04:11.27#ibcon#read 5, iclass 3, count 0 2006.175.08:04:11.27#ibcon#about to read 6, iclass 3, count 0 2006.175.08:04:11.27#ibcon#read 6, iclass 3, count 0 2006.175.08:04:11.27#ibcon#end of sib2, iclass 3, count 0 2006.175.08:04:11.27#ibcon#*after write, iclass 3, count 0 2006.175.08:04:11.27#ibcon#*before return 0, iclass 3, count 0 2006.175.08:04:11.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:04:11.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:04:11.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:04:11.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:04:11.27$vc4f8/va=2,7 2006.175.08:04:11.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.175.08:04:11.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.175.08:04:11.27#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:11.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:04:11.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:04:11.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:04:11.34#ibcon#enter wrdev, iclass 5, count 2 2006.175.08:04:11.34#ibcon#first serial, iclass 5, count 2 2006.175.08:04:11.34#ibcon#enter sib2, iclass 5, count 2 2006.175.08:04:11.34#ibcon#flushed, iclass 5, count 2 2006.175.08:04:11.34#ibcon#about to write, iclass 5, count 2 2006.175.08:04:11.34#ibcon#wrote, iclass 5, count 2 2006.175.08:04:11.34#ibcon#about to read 3, iclass 5, count 2 2006.175.08:04:11.35#ibcon#read 3, iclass 5, count 2 2006.175.08:04:11.35#ibcon#about to read 4, iclass 5, count 2 2006.175.08:04:11.35#ibcon#read 4, iclass 5, count 2 2006.175.08:04:11.35#ibcon#about to read 5, iclass 5, count 2 2006.175.08:04:11.35#ibcon#read 5, iclass 5, count 2 2006.175.08:04:11.35#ibcon#about to read 6, iclass 5, count 2 2006.175.08:04:11.35#ibcon#read 6, iclass 5, count 2 2006.175.08:04:11.35#ibcon#end of sib2, iclass 5, count 2 2006.175.08:04:11.35#ibcon#*mode == 0, iclass 5, count 2 2006.175.08:04:11.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.175.08:04:11.35#ibcon#[25=AT02-07\r\n] 2006.175.08:04:11.35#ibcon#*before write, iclass 5, count 2 2006.175.08:04:11.35#ibcon#enter sib2, iclass 5, count 2 2006.175.08:04:11.35#ibcon#flushed, iclass 5, count 2 2006.175.08:04:11.35#ibcon#about to write, iclass 5, count 2 2006.175.08:04:11.35#ibcon#wrote, iclass 5, count 2 2006.175.08:04:11.35#ibcon#about to read 3, iclass 5, count 2 2006.175.08:04:11.38#ibcon#read 3, iclass 5, count 2 2006.175.08:04:11.38#ibcon#about to read 4, iclass 5, count 2 2006.175.08:04:11.38#ibcon#read 4, iclass 5, count 2 2006.175.08:04:11.38#ibcon#about to read 5, iclass 5, count 2 2006.175.08:04:11.38#ibcon#read 5, iclass 5, count 2 2006.175.08:04:11.38#ibcon#about to read 6, iclass 5, count 2 2006.175.08:04:11.38#ibcon#read 6, iclass 5, count 2 2006.175.08:04:11.38#ibcon#end of sib2, iclass 5, count 2 2006.175.08:04:11.38#ibcon#*after write, iclass 5, count 2 2006.175.08:04:11.38#ibcon#*before return 0, iclass 5, count 2 2006.175.08:04:11.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:04:11.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:04:11.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.175.08:04:11.38#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:11.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:04:11.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:04:11.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:04:11.50#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:04:11.50#ibcon#first serial, iclass 5, count 0 2006.175.08:04:11.50#ibcon#enter sib2, iclass 5, count 0 2006.175.08:04:11.50#ibcon#flushed, iclass 5, count 0 2006.175.08:04:11.50#ibcon#about to write, iclass 5, count 0 2006.175.08:04:11.50#ibcon#wrote, iclass 5, count 0 2006.175.08:04:11.50#ibcon#about to read 3, iclass 5, count 0 2006.175.08:04:11.52#ibcon#read 3, iclass 5, count 0 2006.175.08:04:11.52#ibcon#about to read 4, iclass 5, count 0 2006.175.08:04:11.52#ibcon#read 4, iclass 5, count 0 2006.175.08:04:11.52#ibcon#about to read 5, iclass 5, count 0 2006.175.08:04:11.52#ibcon#read 5, iclass 5, count 0 2006.175.08:04:11.52#ibcon#about to read 6, iclass 5, count 0 2006.175.08:04:11.52#ibcon#read 6, iclass 5, count 0 2006.175.08:04:11.52#ibcon#end of sib2, iclass 5, count 0 2006.175.08:04:11.52#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:04:11.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:04:11.52#ibcon#[25=USB\r\n] 2006.175.08:04:11.52#ibcon#*before write, iclass 5, count 0 2006.175.08:04:11.52#ibcon#enter sib2, iclass 5, count 0 2006.175.08:04:11.52#ibcon#flushed, iclass 5, count 0 2006.175.08:04:11.52#ibcon#about to write, iclass 5, count 0 2006.175.08:04:11.52#ibcon#wrote, iclass 5, count 0 2006.175.08:04:11.52#ibcon#about to read 3, iclass 5, count 0 2006.175.08:04:11.55#ibcon#read 3, iclass 5, count 0 2006.175.08:04:11.55#ibcon#about to read 4, iclass 5, count 0 2006.175.08:04:11.55#ibcon#read 4, iclass 5, count 0 2006.175.08:04:11.55#ibcon#about to read 5, iclass 5, count 0 2006.175.08:04:11.55#ibcon#read 5, iclass 5, count 0 2006.175.08:04:11.55#ibcon#about to read 6, iclass 5, count 0 2006.175.08:04:11.55#ibcon#read 6, iclass 5, count 0 2006.175.08:04:11.55#ibcon#end of sib2, iclass 5, count 0 2006.175.08:04:11.55#ibcon#*after write, iclass 5, count 0 2006.175.08:04:11.55#ibcon#*before return 0, iclass 5, count 0 2006.175.08:04:11.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:04:11.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:04:11.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:04:11.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:04:11.55$vc4f8/valo=3,672.99 2006.175.08:04:11.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.08:04:11.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.08:04:11.55#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:11.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:11.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:11.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:11.55#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:04:11.55#ibcon#first serial, iclass 7, count 0 2006.175.08:04:11.55#ibcon#enter sib2, iclass 7, count 0 2006.175.08:04:11.55#ibcon#flushed, iclass 7, count 0 2006.175.08:04:11.55#ibcon#about to write, iclass 7, count 0 2006.175.08:04:11.55#ibcon#wrote, iclass 7, count 0 2006.175.08:04:11.55#ibcon#about to read 3, iclass 7, count 0 2006.175.08:04:11.57#ibcon#read 3, iclass 7, count 0 2006.175.08:04:11.57#ibcon#about to read 4, iclass 7, count 0 2006.175.08:04:11.57#ibcon#read 4, iclass 7, count 0 2006.175.08:04:11.57#ibcon#about to read 5, iclass 7, count 0 2006.175.08:04:11.57#ibcon#read 5, iclass 7, count 0 2006.175.08:04:11.57#ibcon#about to read 6, iclass 7, count 0 2006.175.08:04:11.57#ibcon#read 6, iclass 7, count 0 2006.175.08:04:11.57#ibcon#end of sib2, iclass 7, count 0 2006.175.08:04:11.57#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:04:11.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:04:11.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:04:11.57#ibcon#*before write, iclass 7, count 0 2006.175.08:04:11.57#ibcon#enter sib2, iclass 7, count 0 2006.175.08:04:11.57#ibcon#flushed, iclass 7, count 0 2006.175.08:04:11.57#ibcon#about to write, iclass 7, count 0 2006.175.08:04:11.57#ibcon#wrote, iclass 7, count 0 2006.175.08:04:11.57#ibcon#about to read 3, iclass 7, count 0 2006.175.08:04:11.61#ibcon#read 3, iclass 7, count 0 2006.175.08:04:11.61#ibcon#about to read 4, iclass 7, count 0 2006.175.08:04:11.61#ibcon#read 4, iclass 7, count 0 2006.175.08:04:11.61#ibcon#about to read 5, iclass 7, count 0 2006.175.08:04:11.61#ibcon#read 5, iclass 7, count 0 2006.175.08:04:11.61#ibcon#about to read 6, iclass 7, count 0 2006.175.08:04:11.61#ibcon#read 6, iclass 7, count 0 2006.175.08:04:11.61#ibcon#end of sib2, iclass 7, count 0 2006.175.08:04:11.61#ibcon#*after write, iclass 7, count 0 2006.175.08:04:11.61#ibcon#*before return 0, iclass 7, count 0 2006.175.08:04:11.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:11.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:11.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:04:11.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:04:11.61$vc4f8/va=3,6 2006.175.08:04:11.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.175.08:04:11.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.175.08:04:11.61#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:11.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:11.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:11.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:11.68#ibcon#enter wrdev, iclass 11, count 2 2006.175.08:04:11.68#ibcon#first serial, iclass 11, count 2 2006.175.08:04:11.68#ibcon#enter sib2, iclass 11, count 2 2006.175.08:04:11.68#ibcon#flushed, iclass 11, count 2 2006.175.08:04:11.68#ibcon#about to write, iclass 11, count 2 2006.175.08:04:11.68#ibcon#wrote, iclass 11, count 2 2006.175.08:04:11.68#ibcon#about to read 3, iclass 11, count 2 2006.175.08:04:11.69#ibcon#read 3, iclass 11, count 2 2006.175.08:04:11.69#ibcon#about to read 4, iclass 11, count 2 2006.175.08:04:11.69#ibcon#read 4, iclass 11, count 2 2006.175.08:04:11.69#ibcon#about to read 5, iclass 11, count 2 2006.175.08:04:11.69#ibcon#read 5, iclass 11, count 2 2006.175.08:04:11.69#ibcon#about to read 6, iclass 11, count 2 2006.175.08:04:11.69#ibcon#read 6, iclass 11, count 2 2006.175.08:04:11.69#ibcon#end of sib2, iclass 11, count 2 2006.175.08:04:11.69#ibcon#*mode == 0, iclass 11, count 2 2006.175.08:04:11.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.175.08:04:11.69#ibcon#[25=AT03-06\r\n] 2006.175.08:04:11.69#ibcon#*before write, iclass 11, count 2 2006.175.08:04:11.69#ibcon#enter sib2, iclass 11, count 2 2006.175.08:04:11.69#ibcon#flushed, iclass 11, count 2 2006.175.08:04:11.69#ibcon#about to write, iclass 11, count 2 2006.175.08:04:11.69#ibcon#wrote, iclass 11, count 2 2006.175.08:04:11.69#ibcon#about to read 3, iclass 11, count 2 2006.175.08:04:11.72#ibcon#read 3, iclass 11, count 2 2006.175.08:04:11.72#ibcon#about to read 4, iclass 11, count 2 2006.175.08:04:11.72#ibcon#read 4, iclass 11, count 2 2006.175.08:04:11.72#ibcon#about to read 5, iclass 11, count 2 2006.175.08:04:11.72#ibcon#read 5, iclass 11, count 2 2006.175.08:04:11.72#ibcon#about to read 6, iclass 11, count 2 2006.175.08:04:11.72#ibcon#read 6, iclass 11, count 2 2006.175.08:04:11.72#ibcon#end of sib2, iclass 11, count 2 2006.175.08:04:11.72#ibcon#*after write, iclass 11, count 2 2006.175.08:04:11.72#ibcon#*before return 0, iclass 11, count 2 2006.175.08:04:11.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:11.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:11.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.175.08:04:11.72#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:11.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:11.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:11.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:11.84#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:04:11.84#ibcon#first serial, iclass 11, count 0 2006.175.08:04:11.84#ibcon#enter sib2, iclass 11, count 0 2006.175.08:04:11.84#ibcon#flushed, iclass 11, count 0 2006.175.08:04:11.84#ibcon#about to write, iclass 11, count 0 2006.175.08:04:11.84#ibcon#wrote, iclass 11, count 0 2006.175.08:04:11.84#ibcon#about to read 3, iclass 11, count 0 2006.175.08:04:11.86#ibcon#read 3, iclass 11, count 0 2006.175.08:04:11.86#ibcon#about to read 4, iclass 11, count 0 2006.175.08:04:11.86#ibcon#read 4, iclass 11, count 0 2006.175.08:04:11.86#ibcon#about to read 5, iclass 11, count 0 2006.175.08:04:11.86#ibcon#read 5, iclass 11, count 0 2006.175.08:04:11.86#ibcon#about to read 6, iclass 11, count 0 2006.175.08:04:11.86#ibcon#read 6, iclass 11, count 0 2006.175.08:04:11.86#ibcon#end of sib2, iclass 11, count 0 2006.175.08:04:11.86#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:04:11.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:04:11.86#ibcon#[25=USB\r\n] 2006.175.08:04:11.86#ibcon#*before write, iclass 11, count 0 2006.175.08:04:11.86#ibcon#enter sib2, iclass 11, count 0 2006.175.08:04:11.86#ibcon#flushed, iclass 11, count 0 2006.175.08:04:11.86#ibcon#about to write, iclass 11, count 0 2006.175.08:04:11.86#ibcon#wrote, iclass 11, count 0 2006.175.08:04:11.86#ibcon#about to read 3, iclass 11, count 0 2006.175.08:04:11.89#ibcon#read 3, iclass 11, count 0 2006.175.08:04:11.89#ibcon#about to read 4, iclass 11, count 0 2006.175.08:04:11.89#ibcon#read 4, iclass 11, count 0 2006.175.08:04:11.89#ibcon#about to read 5, iclass 11, count 0 2006.175.08:04:11.89#ibcon#read 5, iclass 11, count 0 2006.175.08:04:11.89#ibcon#about to read 6, iclass 11, count 0 2006.175.08:04:11.89#ibcon#read 6, iclass 11, count 0 2006.175.08:04:11.89#ibcon#end of sib2, iclass 11, count 0 2006.175.08:04:11.89#ibcon#*after write, iclass 11, count 0 2006.175.08:04:11.89#ibcon#*before return 0, iclass 11, count 0 2006.175.08:04:11.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:11.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:11.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:04:11.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:04:11.89$vc4f8/valo=4,832.99 2006.175.08:04:11.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.175.08:04:11.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.175.08:04:11.89#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:11.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:11.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:11.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:11.89#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:04:11.89#ibcon#first serial, iclass 13, count 0 2006.175.08:04:11.89#ibcon#enter sib2, iclass 13, count 0 2006.175.08:04:11.89#ibcon#flushed, iclass 13, count 0 2006.175.08:04:11.89#ibcon#about to write, iclass 13, count 0 2006.175.08:04:11.89#ibcon#wrote, iclass 13, count 0 2006.175.08:04:11.89#ibcon#about to read 3, iclass 13, count 0 2006.175.08:04:11.91#ibcon#read 3, iclass 13, count 0 2006.175.08:04:11.91#ibcon#about to read 4, iclass 13, count 0 2006.175.08:04:11.91#ibcon#read 4, iclass 13, count 0 2006.175.08:04:11.91#ibcon#about to read 5, iclass 13, count 0 2006.175.08:04:11.91#ibcon#read 5, iclass 13, count 0 2006.175.08:04:11.91#ibcon#about to read 6, iclass 13, count 0 2006.175.08:04:11.91#ibcon#read 6, iclass 13, count 0 2006.175.08:04:11.91#ibcon#end of sib2, iclass 13, count 0 2006.175.08:04:11.91#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:04:11.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:04:11.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:04:11.91#ibcon#*before write, iclass 13, count 0 2006.175.08:04:11.91#ibcon#enter sib2, iclass 13, count 0 2006.175.08:04:11.91#ibcon#flushed, iclass 13, count 0 2006.175.08:04:11.91#ibcon#about to write, iclass 13, count 0 2006.175.08:04:11.91#ibcon#wrote, iclass 13, count 0 2006.175.08:04:11.91#ibcon#about to read 3, iclass 13, count 0 2006.175.08:04:11.95#ibcon#read 3, iclass 13, count 0 2006.175.08:04:11.95#ibcon#about to read 4, iclass 13, count 0 2006.175.08:04:11.95#ibcon#read 4, iclass 13, count 0 2006.175.08:04:11.95#ibcon#about to read 5, iclass 13, count 0 2006.175.08:04:11.95#ibcon#read 5, iclass 13, count 0 2006.175.08:04:11.95#ibcon#about to read 6, iclass 13, count 0 2006.175.08:04:11.95#ibcon#read 6, iclass 13, count 0 2006.175.08:04:11.95#ibcon#end of sib2, iclass 13, count 0 2006.175.08:04:11.95#ibcon#*after write, iclass 13, count 0 2006.175.08:04:11.95#ibcon#*before return 0, iclass 13, count 0 2006.175.08:04:11.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:11.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:11.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:04:11.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:04:11.95$vc4f8/va=4,7 2006.175.08:04:11.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.175.08:04:11.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.175.08:04:11.95#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:11.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:12.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:12.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:12.01#ibcon#enter wrdev, iclass 15, count 2 2006.175.08:04:12.01#ibcon#first serial, iclass 15, count 2 2006.175.08:04:12.01#ibcon#enter sib2, iclass 15, count 2 2006.175.08:04:12.01#ibcon#flushed, iclass 15, count 2 2006.175.08:04:12.01#ibcon#about to write, iclass 15, count 2 2006.175.08:04:12.01#ibcon#wrote, iclass 15, count 2 2006.175.08:04:12.01#ibcon#about to read 3, iclass 15, count 2 2006.175.08:04:12.03#ibcon#read 3, iclass 15, count 2 2006.175.08:04:12.03#ibcon#about to read 4, iclass 15, count 2 2006.175.08:04:12.03#ibcon#read 4, iclass 15, count 2 2006.175.08:04:12.03#ibcon#about to read 5, iclass 15, count 2 2006.175.08:04:12.03#ibcon#read 5, iclass 15, count 2 2006.175.08:04:12.03#ibcon#about to read 6, iclass 15, count 2 2006.175.08:04:12.03#ibcon#read 6, iclass 15, count 2 2006.175.08:04:12.03#ibcon#end of sib2, iclass 15, count 2 2006.175.08:04:12.03#ibcon#*mode == 0, iclass 15, count 2 2006.175.08:04:12.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.175.08:04:12.03#ibcon#[25=AT04-07\r\n] 2006.175.08:04:12.03#ibcon#*before write, iclass 15, count 2 2006.175.08:04:12.03#ibcon#enter sib2, iclass 15, count 2 2006.175.08:04:12.03#ibcon#flushed, iclass 15, count 2 2006.175.08:04:12.03#ibcon#about to write, iclass 15, count 2 2006.175.08:04:12.03#ibcon#wrote, iclass 15, count 2 2006.175.08:04:12.03#ibcon#about to read 3, iclass 15, count 2 2006.175.08:04:12.06#ibcon#read 3, iclass 15, count 2 2006.175.08:04:12.06#ibcon#about to read 4, iclass 15, count 2 2006.175.08:04:12.06#ibcon#read 4, iclass 15, count 2 2006.175.08:04:12.06#ibcon#about to read 5, iclass 15, count 2 2006.175.08:04:12.06#ibcon#read 5, iclass 15, count 2 2006.175.08:04:12.06#ibcon#about to read 6, iclass 15, count 2 2006.175.08:04:12.06#ibcon#read 6, iclass 15, count 2 2006.175.08:04:12.06#ibcon#end of sib2, iclass 15, count 2 2006.175.08:04:12.06#ibcon#*after write, iclass 15, count 2 2006.175.08:04:12.06#ibcon#*before return 0, iclass 15, count 2 2006.175.08:04:12.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:12.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:12.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.175.08:04:12.06#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:12.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:12.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:12.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:12.18#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:04:12.18#ibcon#first serial, iclass 15, count 0 2006.175.08:04:12.18#ibcon#enter sib2, iclass 15, count 0 2006.175.08:04:12.18#ibcon#flushed, iclass 15, count 0 2006.175.08:04:12.18#ibcon#about to write, iclass 15, count 0 2006.175.08:04:12.18#ibcon#wrote, iclass 15, count 0 2006.175.08:04:12.18#ibcon#about to read 3, iclass 15, count 0 2006.175.08:04:12.20#ibcon#read 3, iclass 15, count 0 2006.175.08:04:12.20#ibcon#about to read 4, iclass 15, count 0 2006.175.08:04:12.20#ibcon#read 4, iclass 15, count 0 2006.175.08:04:12.20#ibcon#about to read 5, iclass 15, count 0 2006.175.08:04:12.20#ibcon#read 5, iclass 15, count 0 2006.175.08:04:12.20#ibcon#about to read 6, iclass 15, count 0 2006.175.08:04:12.20#ibcon#read 6, iclass 15, count 0 2006.175.08:04:12.20#ibcon#end of sib2, iclass 15, count 0 2006.175.08:04:12.20#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:04:12.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:04:12.20#ibcon#[25=USB\r\n] 2006.175.08:04:12.20#ibcon#*before write, iclass 15, count 0 2006.175.08:04:12.20#ibcon#enter sib2, iclass 15, count 0 2006.175.08:04:12.20#ibcon#flushed, iclass 15, count 0 2006.175.08:04:12.20#ibcon#about to write, iclass 15, count 0 2006.175.08:04:12.20#ibcon#wrote, iclass 15, count 0 2006.175.08:04:12.20#ibcon#about to read 3, iclass 15, count 0 2006.175.08:04:12.23#ibcon#read 3, iclass 15, count 0 2006.175.08:04:12.23#ibcon#about to read 4, iclass 15, count 0 2006.175.08:04:12.23#ibcon#read 4, iclass 15, count 0 2006.175.08:04:12.23#ibcon#about to read 5, iclass 15, count 0 2006.175.08:04:12.23#ibcon#read 5, iclass 15, count 0 2006.175.08:04:12.23#ibcon#about to read 6, iclass 15, count 0 2006.175.08:04:12.23#ibcon#read 6, iclass 15, count 0 2006.175.08:04:12.23#ibcon#end of sib2, iclass 15, count 0 2006.175.08:04:12.23#ibcon#*after write, iclass 15, count 0 2006.175.08:04:12.23#ibcon#*before return 0, iclass 15, count 0 2006.175.08:04:12.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:12.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:12.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:04:12.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:04:12.23$vc4f8/valo=5,652.99 2006.175.08:04:12.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.08:04:12.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.08:04:12.23#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:12.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:12.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:12.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:12.23#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:04:12.23#ibcon#first serial, iclass 17, count 0 2006.175.08:04:12.23#ibcon#enter sib2, iclass 17, count 0 2006.175.08:04:12.23#ibcon#flushed, iclass 17, count 0 2006.175.08:04:12.23#ibcon#about to write, iclass 17, count 0 2006.175.08:04:12.23#ibcon#wrote, iclass 17, count 0 2006.175.08:04:12.23#ibcon#about to read 3, iclass 17, count 0 2006.175.08:04:12.25#ibcon#read 3, iclass 17, count 0 2006.175.08:04:12.25#ibcon#about to read 4, iclass 17, count 0 2006.175.08:04:12.25#ibcon#read 4, iclass 17, count 0 2006.175.08:04:12.25#ibcon#about to read 5, iclass 17, count 0 2006.175.08:04:12.25#ibcon#read 5, iclass 17, count 0 2006.175.08:04:12.25#ibcon#about to read 6, iclass 17, count 0 2006.175.08:04:12.25#ibcon#read 6, iclass 17, count 0 2006.175.08:04:12.25#ibcon#end of sib2, iclass 17, count 0 2006.175.08:04:12.25#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:04:12.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:04:12.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:04:12.25#ibcon#*before write, iclass 17, count 0 2006.175.08:04:12.25#ibcon#enter sib2, iclass 17, count 0 2006.175.08:04:12.25#ibcon#flushed, iclass 17, count 0 2006.175.08:04:12.25#ibcon#about to write, iclass 17, count 0 2006.175.08:04:12.25#ibcon#wrote, iclass 17, count 0 2006.175.08:04:12.25#ibcon#about to read 3, iclass 17, count 0 2006.175.08:04:12.29#ibcon#read 3, iclass 17, count 0 2006.175.08:04:12.29#ibcon#about to read 4, iclass 17, count 0 2006.175.08:04:12.29#ibcon#read 4, iclass 17, count 0 2006.175.08:04:12.29#ibcon#about to read 5, iclass 17, count 0 2006.175.08:04:12.29#ibcon#read 5, iclass 17, count 0 2006.175.08:04:12.29#ibcon#about to read 6, iclass 17, count 0 2006.175.08:04:12.29#ibcon#read 6, iclass 17, count 0 2006.175.08:04:12.29#ibcon#end of sib2, iclass 17, count 0 2006.175.08:04:12.29#ibcon#*after write, iclass 17, count 0 2006.175.08:04:12.29#ibcon#*before return 0, iclass 17, count 0 2006.175.08:04:12.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:12.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:12.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:04:12.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:04:12.29$vc4f8/va=5,7 2006.175.08:04:12.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.175.08:04:12.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.175.08:04:12.29#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:12.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:12.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:12.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:12.35#ibcon#enter wrdev, iclass 19, count 2 2006.175.08:04:12.35#ibcon#first serial, iclass 19, count 2 2006.175.08:04:12.35#ibcon#enter sib2, iclass 19, count 2 2006.175.08:04:12.35#ibcon#flushed, iclass 19, count 2 2006.175.08:04:12.35#ibcon#about to write, iclass 19, count 2 2006.175.08:04:12.35#ibcon#wrote, iclass 19, count 2 2006.175.08:04:12.35#ibcon#about to read 3, iclass 19, count 2 2006.175.08:04:12.37#ibcon#read 3, iclass 19, count 2 2006.175.08:04:12.37#ibcon#about to read 4, iclass 19, count 2 2006.175.08:04:12.37#ibcon#read 4, iclass 19, count 2 2006.175.08:04:12.37#ibcon#about to read 5, iclass 19, count 2 2006.175.08:04:12.37#ibcon#read 5, iclass 19, count 2 2006.175.08:04:12.37#ibcon#about to read 6, iclass 19, count 2 2006.175.08:04:12.37#ibcon#read 6, iclass 19, count 2 2006.175.08:04:12.37#ibcon#end of sib2, iclass 19, count 2 2006.175.08:04:12.37#ibcon#*mode == 0, iclass 19, count 2 2006.175.08:04:12.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.175.08:04:12.37#ibcon#[25=AT05-07\r\n] 2006.175.08:04:12.37#ibcon#*before write, iclass 19, count 2 2006.175.08:04:12.37#ibcon#enter sib2, iclass 19, count 2 2006.175.08:04:12.37#ibcon#flushed, iclass 19, count 2 2006.175.08:04:12.37#ibcon#about to write, iclass 19, count 2 2006.175.08:04:12.37#ibcon#wrote, iclass 19, count 2 2006.175.08:04:12.37#ibcon#about to read 3, iclass 19, count 2 2006.175.08:04:12.40#ibcon#read 3, iclass 19, count 2 2006.175.08:04:12.40#ibcon#about to read 4, iclass 19, count 2 2006.175.08:04:12.40#ibcon#read 4, iclass 19, count 2 2006.175.08:04:12.40#ibcon#about to read 5, iclass 19, count 2 2006.175.08:04:12.40#ibcon#read 5, iclass 19, count 2 2006.175.08:04:12.40#ibcon#about to read 6, iclass 19, count 2 2006.175.08:04:12.40#ibcon#read 6, iclass 19, count 2 2006.175.08:04:12.40#ibcon#end of sib2, iclass 19, count 2 2006.175.08:04:12.40#ibcon#*after write, iclass 19, count 2 2006.175.08:04:12.40#ibcon#*before return 0, iclass 19, count 2 2006.175.08:04:12.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:12.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:12.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.175.08:04:12.40#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:12.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:12.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:12.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:12.52#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:04:12.52#ibcon#first serial, iclass 19, count 0 2006.175.08:04:12.52#ibcon#enter sib2, iclass 19, count 0 2006.175.08:04:12.52#ibcon#flushed, iclass 19, count 0 2006.175.08:04:12.52#ibcon#about to write, iclass 19, count 0 2006.175.08:04:12.52#ibcon#wrote, iclass 19, count 0 2006.175.08:04:12.52#ibcon#about to read 3, iclass 19, count 0 2006.175.08:04:12.54#ibcon#read 3, iclass 19, count 0 2006.175.08:04:12.54#ibcon#about to read 4, iclass 19, count 0 2006.175.08:04:12.54#ibcon#read 4, iclass 19, count 0 2006.175.08:04:12.54#ibcon#about to read 5, iclass 19, count 0 2006.175.08:04:12.54#ibcon#read 5, iclass 19, count 0 2006.175.08:04:12.54#ibcon#about to read 6, iclass 19, count 0 2006.175.08:04:12.54#ibcon#read 6, iclass 19, count 0 2006.175.08:04:12.54#ibcon#end of sib2, iclass 19, count 0 2006.175.08:04:12.54#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:04:12.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:04:12.54#ibcon#[25=USB\r\n] 2006.175.08:04:12.54#ibcon#*before write, iclass 19, count 0 2006.175.08:04:12.54#ibcon#enter sib2, iclass 19, count 0 2006.175.08:04:12.54#ibcon#flushed, iclass 19, count 0 2006.175.08:04:12.54#ibcon#about to write, iclass 19, count 0 2006.175.08:04:12.54#ibcon#wrote, iclass 19, count 0 2006.175.08:04:12.54#ibcon#about to read 3, iclass 19, count 0 2006.175.08:04:12.57#ibcon#read 3, iclass 19, count 0 2006.175.08:04:12.57#ibcon#about to read 4, iclass 19, count 0 2006.175.08:04:12.57#ibcon#read 4, iclass 19, count 0 2006.175.08:04:12.57#ibcon#about to read 5, iclass 19, count 0 2006.175.08:04:12.57#ibcon#read 5, iclass 19, count 0 2006.175.08:04:12.57#ibcon#about to read 6, iclass 19, count 0 2006.175.08:04:12.57#ibcon#read 6, iclass 19, count 0 2006.175.08:04:12.57#ibcon#end of sib2, iclass 19, count 0 2006.175.08:04:12.57#ibcon#*after write, iclass 19, count 0 2006.175.08:04:12.57#ibcon#*before return 0, iclass 19, count 0 2006.175.08:04:12.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:12.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:12.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:04:12.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:04:12.57$vc4f8/valo=6,772.99 2006.175.08:04:12.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.08:04:12.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.08:04:12.57#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:12.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:12.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:12.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:12.57#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:04:12.57#ibcon#first serial, iclass 21, count 0 2006.175.08:04:12.57#ibcon#enter sib2, iclass 21, count 0 2006.175.08:04:12.57#ibcon#flushed, iclass 21, count 0 2006.175.08:04:12.57#ibcon#about to write, iclass 21, count 0 2006.175.08:04:12.57#ibcon#wrote, iclass 21, count 0 2006.175.08:04:12.57#ibcon#about to read 3, iclass 21, count 0 2006.175.08:04:12.59#ibcon#read 3, iclass 21, count 0 2006.175.08:04:12.59#ibcon#about to read 4, iclass 21, count 0 2006.175.08:04:12.59#ibcon#read 4, iclass 21, count 0 2006.175.08:04:12.59#ibcon#about to read 5, iclass 21, count 0 2006.175.08:04:12.59#ibcon#read 5, iclass 21, count 0 2006.175.08:04:12.59#ibcon#about to read 6, iclass 21, count 0 2006.175.08:04:12.59#ibcon#read 6, iclass 21, count 0 2006.175.08:04:12.59#ibcon#end of sib2, iclass 21, count 0 2006.175.08:04:12.59#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:04:12.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:04:12.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:04:12.59#ibcon#*before write, iclass 21, count 0 2006.175.08:04:12.59#ibcon#enter sib2, iclass 21, count 0 2006.175.08:04:12.59#ibcon#flushed, iclass 21, count 0 2006.175.08:04:12.59#ibcon#about to write, iclass 21, count 0 2006.175.08:04:12.59#ibcon#wrote, iclass 21, count 0 2006.175.08:04:12.59#ibcon#about to read 3, iclass 21, count 0 2006.175.08:04:12.63#ibcon#read 3, iclass 21, count 0 2006.175.08:04:12.63#ibcon#about to read 4, iclass 21, count 0 2006.175.08:04:12.63#ibcon#read 4, iclass 21, count 0 2006.175.08:04:12.63#ibcon#about to read 5, iclass 21, count 0 2006.175.08:04:12.63#ibcon#read 5, iclass 21, count 0 2006.175.08:04:12.63#ibcon#about to read 6, iclass 21, count 0 2006.175.08:04:12.63#ibcon#read 6, iclass 21, count 0 2006.175.08:04:12.63#ibcon#end of sib2, iclass 21, count 0 2006.175.08:04:12.63#ibcon#*after write, iclass 21, count 0 2006.175.08:04:12.63#ibcon#*before return 0, iclass 21, count 0 2006.175.08:04:12.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:12.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:12.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:04:12.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:04:12.63$vc4f8/va=6,6 2006.175.08:04:12.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.08:04:12.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.08:04:12.63#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:12.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:12.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:12.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:12.69#ibcon#enter wrdev, iclass 23, count 2 2006.175.08:04:12.69#ibcon#first serial, iclass 23, count 2 2006.175.08:04:12.69#ibcon#enter sib2, iclass 23, count 2 2006.175.08:04:12.69#ibcon#flushed, iclass 23, count 2 2006.175.08:04:12.69#ibcon#about to write, iclass 23, count 2 2006.175.08:04:12.69#ibcon#wrote, iclass 23, count 2 2006.175.08:04:12.69#ibcon#about to read 3, iclass 23, count 2 2006.175.08:04:12.71#ibcon#read 3, iclass 23, count 2 2006.175.08:04:12.71#ibcon#about to read 4, iclass 23, count 2 2006.175.08:04:12.71#ibcon#read 4, iclass 23, count 2 2006.175.08:04:12.71#ibcon#about to read 5, iclass 23, count 2 2006.175.08:04:12.71#ibcon#read 5, iclass 23, count 2 2006.175.08:04:12.71#ibcon#about to read 6, iclass 23, count 2 2006.175.08:04:12.71#ibcon#read 6, iclass 23, count 2 2006.175.08:04:12.71#ibcon#end of sib2, iclass 23, count 2 2006.175.08:04:12.71#ibcon#*mode == 0, iclass 23, count 2 2006.175.08:04:12.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.08:04:12.71#ibcon#[25=AT06-06\r\n] 2006.175.08:04:12.71#ibcon#*before write, iclass 23, count 2 2006.175.08:04:12.71#ibcon#enter sib2, iclass 23, count 2 2006.175.08:04:12.71#ibcon#flushed, iclass 23, count 2 2006.175.08:04:12.71#ibcon#about to write, iclass 23, count 2 2006.175.08:04:12.71#ibcon#wrote, iclass 23, count 2 2006.175.08:04:12.71#ibcon#about to read 3, iclass 23, count 2 2006.175.08:04:12.74#ibcon#read 3, iclass 23, count 2 2006.175.08:04:12.74#ibcon#about to read 4, iclass 23, count 2 2006.175.08:04:12.74#ibcon#read 4, iclass 23, count 2 2006.175.08:04:12.74#ibcon#about to read 5, iclass 23, count 2 2006.175.08:04:12.74#ibcon#read 5, iclass 23, count 2 2006.175.08:04:12.74#ibcon#about to read 6, iclass 23, count 2 2006.175.08:04:12.74#ibcon#read 6, iclass 23, count 2 2006.175.08:04:12.74#ibcon#end of sib2, iclass 23, count 2 2006.175.08:04:12.74#ibcon#*after write, iclass 23, count 2 2006.175.08:04:12.74#ibcon#*before return 0, iclass 23, count 2 2006.175.08:04:12.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:12.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:12.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.08:04:12.74#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:12.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:12.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:12.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:12.86#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:04:12.86#ibcon#first serial, iclass 23, count 0 2006.175.08:04:12.86#ibcon#enter sib2, iclass 23, count 0 2006.175.08:04:12.86#ibcon#flushed, iclass 23, count 0 2006.175.08:04:12.86#ibcon#about to write, iclass 23, count 0 2006.175.08:04:12.86#ibcon#wrote, iclass 23, count 0 2006.175.08:04:12.86#ibcon#about to read 3, iclass 23, count 0 2006.175.08:04:12.88#ibcon#read 3, iclass 23, count 0 2006.175.08:04:12.88#ibcon#about to read 4, iclass 23, count 0 2006.175.08:04:12.88#ibcon#read 4, iclass 23, count 0 2006.175.08:04:12.88#ibcon#about to read 5, iclass 23, count 0 2006.175.08:04:12.88#ibcon#read 5, iclass 23, count 0 2006.175.08:04:12.88#ibcon#about to read 6, iclass 23, count 0 2006.175.08:04:12.88#ibcon#read 6, iclass 23, count 0 2006.175.08:04:12.88#ibcon#end of sib2, iclass 23, count 0 2006.175.08:04:12.88#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:04:12.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:04:12.88#ibcon#[25=USB\r\n] 2006.175.08:04:12.88#ibcon#*before write, iclass 23, count 0 2006.175.08:04:12.88#ibcon#enter sib2, iclass 23, count 0 2006.175.08:04:12.88#ibcon#flushed, iclass 23, count 0 2006.175.08:04:12.88#ibcon#about to write, iclass 23, count 0 2006.175.08:04:12.88#ibcon#wrote, iclass 23, count 0 2006.175.08:04:12.88#ibcon#about to read 3, iclass 23, count 0 2006.175.08:04:12.91#ibcon#read 3, iclass 23, count 0 2006.175.08:04:12.91#ibcon#about to read 4, iclass 23, count 0 2006.175.08:04:12.91#ibcon#read 4, iclass 23, count 0 2006.175.08:04:12.91#ibcon#about to read 5, iclass 23, count 0 2006.175.08:04:12.91#ibcon#read 5, iclass 23, count 0 2006.175.08:04:12.91#ibcon#about to read 6, iclass 23, count 0 2006.175.08:04:12.91#ibcon#read 6, iclass 23, count 0 2006.175.08:04:12.91#ibcon#end of sib2, iclass 23, count 0 2006.175.08:04:12.91#ibcon#*after write, iclass 23, count 0 2006.175.08:04:12.91#ibcon#*before return 0, iclass 23, count 0 2006.175.08:04:12.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:12.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:12.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:04:12.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:04:12.91$vc4f8/valo=7,832.99 2006.175.08:04:12.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.08:04:12.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.08:04:12.91#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:12.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:12.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:12.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:12.91#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:04:12.91#ibcon#first serial, iclass 25, count 0 2006.175.08:04:12.91#ibcon#enter sib2, iclass 25, count 0 2006.175.08:04:12.91#ibcon#flushed, iclass 25, count 0 2006.175.08:04:12.91#ibcon#about to write, iclass 25, count 0 2006.175.08:04:12.91#ibcon#wrote, iclass 25, count 0 2006.175.08:04:12.91#ibcon#about to read 3, iclass 25, count 0 2006.175.08:04:12.93#ibcon#read 3, iclass 25, count 0 2006.175.08:04:12.93#ibcon#about to read 4, iclass 25, count 0 2006.175.08:04:12.93#ibcon#read 4, iclass 25, count 0 2006.175.08:04:12.93#ibcon#about to read 5, iclass 25, count 0 2006.175.08:04:12.93#ibcon#read 5, iclass 25, count 0 2006.175.08:04:12.93#ibcon#about to read 6, iclass 25, count 0 2006.175.08:04:12.93#ibcon#read 6, iclass 25, count 0 2006.175.08:04:12.93#ibcon#end of sib2, iclass 25, count 0 2006.175.08:04:12.93#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:04:12.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:04:12.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:04:12.93#ibcon#*before write, iclass 25, count 0 2006.175.08:04:12.93#ibcon#enter sib2, iclass 25, count 0 2006.175.08:04:12.93#ibcon#flushed, iclass 25, count 0 2006.175.08:04:12.93#ibcon#about to write, iclass 25, count 0 2006.175.08:04:12.93#ibcon#wrote, iclass 25, count 0 2006.175.08:04:12.93#ibcon#about to read 3, iclass 25, count 0 2006.175.08:04:12.97#ibcon#read 3, iclass 25, count 0 2006.175.08:04:12.97#ibcon#about to read 4, iclass 25, count 0 2006.175.08:04:12.97#ibcon#read 4, iclass 25, count 0 2006.175.08:04:12.97#ibcon#about to read 5, iclass 25, count 0 2006.175.08:04:12.97#ibcon#read 5, iclass 25, count 0 2006.175.08:04:12.97#ibcon#about to read 6, iclass 25, count 0 2006.175.08:04:12.97#ibcon#read 6, iclass 25, count 0 2006.175.08:04:12.97#ibcon#end of sib2, iclass 25, count 0 2006.175.08:04:12.97#ibcon#*after write, iclass 25, count 0 2006.175.08:04:12.97#ibcon#*before return 0, iclass 25, count 0 2006.175.08:04:12.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:12.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:12.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:04:12.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:04:12.97$vc4f8/va=7,6 2006.175.08:04:12.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.08:04:12.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.08:04:12.97#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:12.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:04:13.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:04:13.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:04:13.03#ibcon#enter wrdev, iclass 27, count 2 2006.175.08:04:13.03#ibcon#first serial, iclass 27, count 2 2006.175.08:04:13.03#ibcon#enter sib2, iclass 27, count 2 2006.175.08:04:13.03#ibcon#flushed, iclass 27, count 2 2006.175.08:04:13.03#ibcon#about to write, iclass 27, count 2 2006.175.08:04:13.03#ibcon#wrote, iclass 27, count 2 2006.175.08:04:13.03#ibcon#about to read 3, iclass 27, count 2 2006.175.08:04:13.05#ibcon#read 3, iclass 27, count 2 2006.175.08:04:13.05#ibcon#about to read 4, iclass 27, count 2 2006.175.08:04:13.05#ibcon#read 4, iclass 27, count 2 2006.175.08:04:13.05#ibcon#about to read 5, iclass 27, count 2 2006.175.08:04:13.05#ibcon#read 5, iclass 27, count 2 2006.175.08:04:13.05#ibcon#about to read 6, iclass 27, count 2 2006.175.08:04:13.05#ibcon#read 6, iclass 27, count 2 2006.175.08:04:13.05#ibcon#end of sib2, iclass 27, count 2 2006.175.08:04:13.05#ibcon#*mode == 0, iclass 27, count 2 2006.175.08:04:13.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.08:04:13.05#ibcon#[25=AT07-06\r\n] 2006.175.08:04:13.05#ibcon#*before write, iclass 27, count 2 2006.175.08:04:13.05#ibcon#enter sib2, iclass 27, count 2 2006.175.08:04:13.05#ibcon#flushed, iclass 27, count 2 2006.175.08:04:13.05#ibcon#about to write, iclass 27, count 2 2006.175.08:04:13.05#ibcon#wrote, iclass 27, count 2 2006.175.08:04:13.05#ibcon#about to read 3, iclass 27, count 2 2006.175.08:04:13.08#ibcon#read 3, iclass 27, count 2 2006.175.08:04:13.08#ibcon#about to read 4, iclass 27, count 2 2006.175.08:04:13.08#ibcon#read 4, iclass 27, count 2 2006.175.08:04:13.08#ibcon#about to read 5, iclass 27, count 2 2006.175.08:04:13.08#ibcon#read 5, iclass 27, count 2 2006.175.08:04:13.08#ibcon#about to read 6, iclass 27, count 2 2006.175.08:04:13.08#ibcon#read 6, iclass 27, count 2 2006.175.08:04:13.08#ibcon#end of sib2, iclass 27, count 2 2006.175.08:04:13.08#ibcon#*after write, iclass 27, count 2 2006.175.08:04:13.08#ibcon#*before return 0, iclass 27, count 2 2006.175.08:04:13.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:04:13.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:04:13.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.08:04:13.08#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:13.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:04:13.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:04:13.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:04:13.20#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:04:13.20#ibcon#first serial, iclass 27, count 0 2006.175.08:04:13.20#ibcon#enter sib2, iclass 27, count 0 2006.175.08:04:13.20#ibcon#flushed, iclass 27, count 0 2006.175.08:04:13.20#ibcon#about to write, iclass 27, count 0 2006.175.08:04:13.20#ibcon#wrote, iclass 27, count 0 2006.175.08:04:13.20#ibcon#about to read 3, iclass 27, count 0 2006.175.08:04:13.22#ibcon#read 3, iclass 27, count 0 2006.175.08:04:13.22#ibcon#about to read 4, iclass 27, count 0 2006.175.08:04:13.22#ibcon#read 4, iclass 27, count 0 2006.175.08:04:13.22#ibcon#about to read 5, iclass 27, count 0 2006.175.08:04:13.22#ibcon#read 5, iclass 27, count 0 2006.175.08:04:13.22#ibcon#about to read 6, iclass 27, count 0 2006.175.08:04:13.22#ibcon#read 6, iclass 27, count 0 2006.175.08:04:13.22#ibcon#end of sib2, iclass 27, count 0 2006.175.08:04:13.22#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:04:13.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:04:13.22#ibcon#[25=USB\r\n] 2006.175.08:04:13.22#ibcon#*before write, iclass 27, count 0 2006.175.08:04:13.22#ibcon#enter sib2, iclass 27, count 0 2006.175.08:04:13.22#ibcon#flushed, iclass 27, count 0 2006.175.08:04:13.22#ibcon#about to write, iclass 27, count 0 2006.175.08:04:13.22#ibcon#wrote, iclass 27, count 0 2006.175.08:04:13.22#ibcon#about to read 3, iclass 27, count 0 2006.175.08:04:13.25#ibcon#read 3, iclass 27, count 0 2006.175.08:04:13.25#ibcon#about to read 4, iclass 27, count 0 2006.175.08:04:13.25#ibcon#read 4, iclass 27, count 0 2006.175.08:04:13.25#ibcon#about to read 5, iclass 27, count 0 2006.175.08:04:13.25#ibcon#read 5, iclass 27, count 0 2006.175.08:04:13.25#ibcon#about to read 6, iclass 27, count 0 2006.175.08:04:13.25#ibcon#read 6, iclass 27, count 0 2006.175.08:04:13.25#ibcon#end of sib2, iclass 27, count 0 2006.175.08:04:13.25#ibcon#*after write, iclass 27, count 0 2006.175.08:04:13.25#ibcon#*before return 0, iclass 27, count 0 2006.175.08:04:13.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:04:13.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:04:13.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:04:13.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:04:13.25$vc4f8/valo=8,852.99 2006.175.08:04:13.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.08:04:13.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.08:04:13.25#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:13.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:04:13.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:04:13.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:04:13.25#ibcon#enter wrdev, iclass 29, count 0 2006.175.08:04:13.25#ibcon#first serial, iclass 29, count 0 2006.175.08:04:13.25#ibcon#enter sib2, iclass 29, count 0 2006.175.08:04:13.25#ibcon#flushed, iclass 29, count 0 2006.175.08:04:13.25#ibcon#about to write, iclass 29, count 0 2006.175.08:04:13.25#ibcon#wrote, iclass 29, count 0 2006.175.08:04:13.25#ibcon#about to read 3, iclass 29, count 0 2006.175.08:04:13.27#ibcon#read 3, iclass 29, count 0 2006.175.08:04:13.27#ibcon#about to read 4, iclass 29, count 0 2006.175.08:04:13.27#ibcon#read 4, iclass 29, count 0 2006.175.08:04:13.27#ibcon#about to read 5, iclass 29, count 0 2006.175.08:04:13.27#ibcon#read 5, iclass 29, count 0 2006.175.08:04:13.27#ibcon#about to read 6, iclass 29, count 0 2006.175.08:04:13.27#ibcon#read 6, iclass 29, count 0 2006.175.08:04:13.27#ibcon#end of sib2, iclass 29, count 0 2006.175.08:04:13.27#ibcon#*mode == 0, iclass 29, count 0 2006.175.08:04:13.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.08:04:13.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:04:13.27#ibcon#*before write, iclass 29, count 0 2006.175.08:04:13.27#ibcon#enter sib2, iclass 29, count 0 2006.175.08:04:13.27#ibcon#flushed, iclass 29, count 0 2006.175.08:04:13.27#ibcon#about to write, iclass 29, count 0 2006.175.08:04:13.27#ibcon#wrote, iclass 29, count 0 2006.175.08:04:13.27#ibcon#about to read 3, iclass 29, count 0 2006.175.08:04:13.31#ibcon#read 3, iclass 29, count 0 2006.175.08:04:13.31#ibcon#about to read 4, iclass 29, count 0 2006.175.08:04:13.31#ibcon#read 4, iclass 29, count 0 2006.175.08:04:13.31#ibcon#about to read 5, iclass 29, count 0 2006.175.08:04:13.31#ibcon#read 5, iclass 29, count 0 2006.175.08:04:13.31#ibcon#about to read 6, iclass 29, count 0 2006.175.08:04:13.31#ibcon#read 6, iclass 29, count 0 2006.175.08:04:13.31#ibcon#end of sib2, iclass 29, count 0 2006.175.08:04:13.31#ibcon#*after write, iclass 29, count 0 2006.175.08:04:13.31#ibcon#*before return 0, iclass 29, count 0 2006.175.08:04:13.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:04:13.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:04:13.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.08:04:13.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.08:04:13.31$vc4f8/va=8,6 2006.175.08:04:13.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.08:04:13.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.08:04:13.31#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:13.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:04:13.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:04:13.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:04:13.37#ibcon#enter wrdev, iclass 31, count 2 2006.175.08:04:13.37#ibcon#first serial, iclass 31, count 2 2006.175.08:04:13.37#ibcon#enter sib2, iclass 31, count 2 2006.175.08:04:13.37#ibcon#flushed, iclass 31, count 2 2006.175.08:04:13.37#ibcon#about to write, iclass 31, count 2 2006.175.08:04:13.37#ibcon#wrote, iclass 31, count 2 2006.175.08:04:13.37#ibcon#about to read 3, iclass 31, count 2 2006.175.08:04:13.39#ibcon#read 3, iclass 31, count 2 2006.175.08:04:13.39#ibcon#about to read 4, iclass 31, count 2 2006.175.08:04:13.39#ibcon#read 4, iclass 31, count 2 2006.175.08:04:13.39#ibcon#about to read 5, iclass 31, count 2 2006.175.08:04:13.39#ibcon#read 5, iclass 31, count 2 2006.175.08:04:13.39#ibcon#about to read 6, iclass 31, count 2 2006.175.08:04:13.39#ibcon#read 6, iclass 31, count 2 2006.175.08:04:13.39#ibcon#end of sib2, iclass 31, count 2 2006.175.08:04:13.39#ibcon#*mode == 0, iclass 31, count 2 2006.175.08:04:13.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.08:04:13.39#ibcon#[25=AT08-06\r\n] 2006.175.08:04:13.39#ibcon#*before write, iclass 31, count 2 2006.175.08:04:13.39#ibcon#enter sib2, iclass 31, count 2 2006.175.08:04:13.39#ibcon#flushed, iclass 31, count 2 2006.175.08:04:13.39#ibcon#about to write, iclass 31, count 2 2006.175.08:04:13.39#ibcon#wrote, iclass 31, count 2 2006.175.08:04:13.39#ibcon#about to read 3, iclass 31, count 2 2006.175.08:04:13.42#ibcon#read 3, iclass 31, count 2 2006.175.08:04:13.42#ibcon#about to read 4, iclass 31, count 2 2006.175.08:04:13.42#ibcon#read 4, iclass 31, count 2 2006.175.08:04:13.42#ibcon#about to read 5, iclass 31, count 2 2006.175.08:04:13.42#ibcon#read 5, iclass 31, count 2 2006.175.08:04:13.42#ibcon#about to read 6, iclass 31, count 2 2006.175.08:04:13.42#ibcon#read 6, iclass 31, count 2 2006.175.08:04:13.42#ibcon#end of sib2, iclass 31, count 2 2006.175.08:04:13.42#ibcon#*after write, iclass 31, count 2 2006.175.08:04:13.42#ibcon#*before return 0, iclass 31, count 2 2006.175.08:04:13.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:04:13.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:04:13.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.08:04:13.42#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:13.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:04:13.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:04:13.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:04:13.54#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:04:13.54#ibcon#first serial, iclass 31, count 0 2006.175.08:04:13.54#ibcon#enter sib2, iclass 31, count 0 2006.175.08:04:13.54#ibcon#flushed, iclass 31, count 0 2006.175.08:04:13.54#ibcon#about to write, iclass 31, count 0 2006.175.08:04:13.54#ibcon#wrote, iclass 31, count 0 2006.175.08:04:13.54#ibcon#about to read 3, iclass 31, count 0 2006.175.08:04:13.56#ibcon#read 3, iclass 31, count 0 2006.175.08:04:13.56#ibcon#about to read 4, iclass 31, count 0 2006.175.08:04:13.56#ibcon#read 4, iclass 31, count 0 2006.175.08:04:13.56#ibcon#about to read 5, iclass 31, count 0 2006.175.08:04:13.56#ibcon#read 5, iclass 31, count 0 2006.175.08:04:13.56#ibcon#about to read 6, iclass 31, count 0 2006.175.08:04:13.56#ibcon#read 6, iclass 31, count 0 2006.175.08:04:13.56#ibcon#end of sib2, iclass 31, count 0 2006.175.08:04:13.56#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:04:13.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:04:13.56#ibcon#[25=USB\r\n] 2006.175.08:04:13.56#ibcon#*before write, iclass 31, count 0 2006.175.08:04:13.56#ibcon#enter sib2, iclass 31, count 0 2006.175.08:04:13.56#ibcon#flushed, iclass 31, count 0 2006.175.08:04:13.56#ibcon#about to write, iclass 31, count 0 2006.175.08:04:13.56#ibcon#wrote, iclass 31, count 0 2006.175.08:04:13.56#ibcon#about to read 3, iclass 31, count 0 2006.175.08:04:13.59#ibcon#read 3, iclass 31, count 0 2006.175.08:04:13.59#ibcon#about to read 4, iclass 31, count 0 2006.175.08:04:13.59#ibcon#read 4, iclass 31, count 0 2006.175.08:04:13.59#ibcon#about to read 5, iclass 31, count 0 2006.175.08:04:13.59#ibcon#read 5, iclass 31, count 0 2006.175.08:04:13.59#ibcon#about to read 6, iclass 31, count 0 2006.175.08:04:13.59#ibcon#read 6, iclass 31, count 0 2006.175.08:04:13.59#ibcon#end of sib2, iclass 31, count 0 2006.175.08:04:13.59#ibcon#*after write, iclass 31, count 0 2006.175.08:04:13.59#ibcon#*before return 0, iclass 31, count 0 2006.175.08:04:13.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:04:13.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:04:13.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:04:13.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:04:13.59$vc4f8/vblo=1,632.99 2006.175.08:04:13.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.08:04:13.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.08:04:13.59#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:13.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:04:13.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:04:13.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:04:13.59#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:04:13.59#ibcon#first serial, iclass 33, count 0 2006.175.08:04:13.59#ibcon#enter sib2, iclass 33, count 0 2006.175.08:04:13.59#ibcon#flushed, iclass 33, count 0 2006.175.08:04:13.59#ibcon#about to write, iclass 33, count 0 2006.175.08:04:13.59#ibcon#wrote, iclass 33, count 0 2006.175.08:04:13.59#ibcon#about to read 3, iclass 33, count 0 2006.175.08:04:13.61#ibcon#read 3, iclass 33, count 0 2006.175.08:04:13.61#ibcon#about to read 4, iclass 33, count 0 2006.175.08:04:13.61#ibcon#read 4, iclass 33, count 0 2006.175.08:04:13.61#ibcon#about to read 5, iclass 33, count 0 2006.175.08:04:13.61#ibcon#read 5, iclass 33, count 0 2006.175.08:04:13.61#ibcon#about to read 6, iclass 33, count 0 2006.175.08:04:13.61#ibcon#read 6, iclass 33, count 0 2006.175.08:04:13.61#ibcon#end of sib2, iclass 33, count 0 2006.175.08:04:13.61#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:04:13.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:04:13.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:04:13.61#ibcon#*before write, iclass 33, count 0 2006.175.08:04:13.61#ibcon#enter sib2, iclass 33, count 0 2006.175.08:04:13.61#ibcon#flushed, iclass 33, count 0 2006.175.08:04:13.61#ibcon#about to write, iclass 33, count 0 2006.175.08:04:13.61#ibcon#wrote, iclass 33, count 0 2006.175.08:04:13.61#ibcon#about to read 3, iclass 33, count 0 2006.175.08:04:13.65#ibcon#read 3, iclass 33, count 0 2006.175.08:04:13.65#ibcon#about to read 4, iclass 33, count 0 2006.175.08:04:13.65#ibcon#read 4, iclass 33, count 0 2006.175.08:04:13.65#ibcon#about to read 5, iclass 33, count 0 2006.175.08:04:13.65#ibcon#read 5, iclass 33, count 0 2006.175.08:04:13.65#ibcon#about to read 6, iclass 33, count 0 2006.175.08:04:13.65#ibcon#read 6, iclass 33, count 0 2006.175.08:04:13.65#ibcon#end of sib2, iclass 33, count 0 2006.175.08:04:13.65#ibcon#*after write, iclass 33, count 0 2006.175.08:04:13.65#ibcon#*before return 0, iclass 33, count 0 2006.175.08:04:13.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:04:13.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:04:13.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:04:13.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:04:13.65$vc4f8/vb=1,4 2006.175.08:04:13.65#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.175.08:04:13.65#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.175.08:04:13.65#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:13.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:04:13.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:04:13.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:04:13.65#ibcon#enter wrdev, iclass 35, count 2 2006.175.08:04:13.65#ibcon#first serial, iclass 35, count 2 2006.175.08:04:13.65#ibcon#enter sib2, iclass 35, count 2 2006.175.08:04:13.65#ibcon#flushed, iclass 35, count 2 2006.175.08:04:13.65#ibcon#about to write, iclass 35, count 2 2006.175.08:04:13.65#ibcon#wrote, iclass 35, count 2 2006.175.08:04:13.65#ibcon#about to read 3, iclass 35, count 2 2006.175.08:04:13.67#ibcon#read 3, iclass 35, count 2 2006.175.08:04:13.67#ibcon#about to read 4, iclass 35, count 2 2006.175.08:04:13.67#ibcon#read 4, iclass 35, count 2 2006.175.08:04:13.67#ibcon#about to read 5, iclass 35, count 2 2006.175.08:04:13.67#ibcon#read 5, iclass 35, count 2 2006.175.08:04:13.67#ibcon#about to read 6, iclass 35, count 2 2006.175.08:04:13.67#ibcon#read 6, iclass 35, count 2 2006.175.08:04:13.67#ibcon#end of sib2, iclass 35, count 2 2006.175.08:04:13.67#ibcon#*mode == 0, iclass 35, count 2 2006.175.08:04:13.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.175.08:04:13.67#ibcon#[27=AT01-04\r\n] 2006.175.08:04:13.67#ibcon#*before write, iclass 35, count 2 2006.175.08:04:13.67#ibcon#enter sib2, iclass 35, count 2 2006.175.08:04:13.67#ibcon#flushed, iclass 35, count 2 2006.175.08:04:13.67#ibcon#about to write, iclass 35, count 2 2006.175.08:04:13.67#ibcon#wrote, iclass 35, count 2 2006.175.08:04:13.67#ibcon#about to read 3, iclass 35, count 2 2006.175.08:04:13.70#ibcon#read 3, iclass 35, count 2 2006.175.08:04:13.70#ibcon#about to read 4, iclass 35, count 2 2006.175.08:04:13.70#ibcon#read 4, iclass 35, count 2 2006.175.08:04:13.70#ibcon#about to read 5, iclass 35, count 2 2006.175.08:04:13.70#ibcon#read 5, iclass 35, count 2 2006.175.08:04:13.70#ibcon#about to read 6, iclass 35, count 2 2006.175.08:04:13.70#ibcon#read 6, iclass 35, count 2 2006.175.08:04:13.70#ibcon#end of sib2, iclass 35, count 2 2006.175.08:04:13.70#ibcon#*after write, iclass 35, count 2 2006.175.08:04:13.70#ibcon#*before return 0, iclass 35, count 2 2006.175.08:04:13.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:04:13.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:04:13.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.175.08:04:13.70#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:13.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:04:13.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:04:13.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:04:13.82#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:04:13.82#ibcon#first serial, iclass 35, count 0 2006.175.08:04:13.82#ibcon#enter sib2, iclass 35, count 0 2006.175.08:04:13.82#ibcon#flushed, iclass 35, count 0 2006.175.08:04:13.82#ibcon#about to write, iclass 35, count 0 2006.175.08:04:13.82#ibcon#wrote, iclass 35, count 0 2006.175.08:04:13.82#ibcon#about to read 3, iclass 35, count 0 2006.175.08:04:13.84#ibcon#read 3, iclass 35, count 0 2006.175.08:04:13.84#ibcon#about to read 4, iclass 35, count 0 2006.175.08:04:13.84#ibcon#read 4, iclass 35, count 0 2006.175.08:04:13.84#ibcon#about to read 5, iclass 35, count 0 2006.175.08:04:13.84#ibcon#read 5, iclass 35, count 0 2006.175.08:04:13.84#ibcon#about to read 6, iclass 35, count 0 2006.175.08:04:13.84#ibcon#read 6, iclass 35, count 0 2006.175.08:04:13.84#ibcon#end of sib2, iclass 35, count 0 2006.175.08:04:13.84#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:04:13.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:04:13.84#ibcon#[27=USB\r\n] 2006.175.08:04:13.84#ibcon#*before write, iclass 35, count 0 2006.175.08:04:13.84#ibcon#enter sib2, iclass 35, count 0 2006.175.08:04:13.84#ibcon#flushed, iclass 35, count 0 2006.175.08:04:13.84#ibcon#about to write, iclass 35, count 0 2006.175.08:04:13.84#ibcon#wrote, iclass 35, count 0 2006.175.08:04:13.84#ibcon#about to read 3, iclass 35, count 0 2006.175.08:04:13.87#ibcon#read 3, iclass 35, count 0 2006.175.08:04:13.87#ibcon#about to read 4, iclass 35, count 0 2006.175.08:04:13.87#ibcon#read 4, iclass 35, count 0 2006.175.08:04:13.87#ibcon#about to read 5, iclass 35, count 0 2006.175.08:04:13.87#ibcon#read 5, iclass 35, count 0 2006.175.08:04:13.87#ibcon#about to read 6, iclass 35, count 0 2006.175.08:04:13.87#ibcon#read 6, iclass 35, count 0 2006.175.08:04:13.87#ibcon#end of sib2, iclass 35, count 0 2006.175.08:04:13.87#ibcon#*after write, iclass 35, count 0 2006.175.08:04:13.87#ibcon#*before return 0, iclass 35, count 0 2006.175.08:04:13.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:04:13.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:04:13.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:04:13.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:04:13.87$vc4f8/vblo=2,640.99 2006.175.08:04:13.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.08:04:13.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.08:04:13.87#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:13.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:13.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:13.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:13.87#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:04:13.87#ibcon#first serial, iclass 37, count 0 2006.175.08:04:13.87#ibcon#enter sib2, iclass 37, count 0 2006.175.08:04:13.87#ibcon#flushed, iclass 37, count 0 2006.175.08:04:13.87#ibcon#about to write, iclass 37, count 0 2006.175.08:04:13.87#ibcon#wrote, iclass 37, count 0 2006.175.08:04:13.87#ibcon#about to read 3, iclass 37, count 0 2006.175.08:04:13.89#ibcon#read 3, iclass 37, count 0 2006.175.08:04:13.89#ibcon#about to read 4, iclass 37, count 0 2006.175.08:04:13.89#ibcon#read 4, iclass 37, count 0 2006.175.08:04:13.89#ibcon#about to read 5, iclass 37, count 0 2006.175.08:04:13.89#ibcon#read 5, iclass 37, count 0 2006.175.08:04:13.89#ibcon#about to read 6, iclass 37, count 0 2006.175.08:04:13.89#ibcon#read 6, iclass 37, count 0 2006.175.08:04:13.89#ibcon#end of sib2, iclass 37, count 0 2006.175.08:04:13.89#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:04:13.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:04:13.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:04:13.89#ibcon#*before write, iclass 37, count 0 2006.175.08:04:13.89#ibcon#enter sib2, iclass 37, count 0 2006.175.08:04:13.89#ibcon#flushed, iclass 37, count 0 2006.175.08:04:13.89#ibcon#about to write, iclass 37, count 0 2006.175.08:04:13.89#ibcon#wrote, iclass 37, count 0 2006.175.08:04:13.89#ibcon#about to read 3, iclass 37, count 0 2006.175.08:04:13.93#ibcon#read 3, iclass 37, count 0 2006.175.08:04:13.93#ibcon#about to read 4, iclass 37, count 0 2006.175.08:04:13.93#ibcon#read 4, iclass 37, count 0 2006.175.08:04:13.93#ibcon#about to read 5, iclass 37, count 0 2006.175.08:04:13.93#ibcon#read 5, iclass 37, count 0 2006.175.08:04:13.93#ibcon#about to read 6, iclass 37, count 0 2006.175.08:04:13.93#ibcon#read 6, iclass 37, count 0 2006.175.08:04:13.93#ibcon#end of sib2, iclass 37, count 0 2006.175.08:04:13.93#ibcon#*after write, iclass 37, count 0 2006.175.08:04:13.93#ibcon#*before return 0, iclass 37, count 0 2006.175.08:04:13.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:13.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:04:13.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:04:13.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:04:13.93$vc4f8/vb=2,4 2006.175.08:04:13.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.08:04:13.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.08:04:13.93#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:13.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:04:13.97#abcon#<5=/05 3.8 6.7 25.86 681007.4\r\n> 2006.175.08:04:13.99#abcon#{5=INTERFACE CLEAR} 2006.175.08:04:13.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:04:13.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:04:13.99#ibcon#enter wrdev, iclass 40, count 2 2006.175.08:04:13.99#ibcon#first serial, iclass 40, count 2 2006.175.08:04:13.99#ibcon#enter sib2, iclass 40, count 2 2006.175.08:04:13.99#ibcon#flushed, iclass 40, count 2 2006.175.08:04:13.99#ibcon#about to write, iclass 40, count 2 2006.175.08:04:13.99#ibcon#wrote, iclass 40, count 2 2006.175.08:04:13.99#ibcon#about to read 3, iclass 40, count 2 2006.175.08:04:14.01#ibcon#read 3, iclass 40, count 2 2006.175.08:04:14.01#ibcon#about to read 4, iclass 40, count 2 2006.175.08:04:14.01#ibcon#read 4, iclass 40, count 2 2006.175.08:04:14.01#ibcon#about to read 5, iclass 40, count 2 2006.175.08:04:14.01#ibcon#read 5, iclass 40, count 2 2006.175.08:04:14.01#ibcon#about to read 6, iclass 40, count 2 2006.175.08:04:14.01#ibcon#read 6, iclass 40, count 2 2006.175.08:04:14.01#ibcon#end of sib2, iclass 40, count 2 2006.175.08:04:14.01#ibcon#*mode == 0, iclass 40, count 2 2006.175.08:04:14.01#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.08:04:14.01#ibcon#[27=AT02-04\r\n] 2006.175.08:04:14.01#ibcon#*before write, iclass 40, count 2 2006.175.08:04:14.01#ibcon#enter sib2, iclass 40, count 2 2006.175.08:04:14.01#ibcon#flushed, iclass 40, count 2 2006.175.08:04:14.01#ibcon#about to write, iclass 40, count 2 2006.175.08:04:14.01#ibcon#wrote, iclass 40, count 2 2006.175.08:04:14.01#ibcon#about to read 3, iclass 40, count 2 2006.175.08:04:14.04#ibcon#read 3, iclass 40, count 2 2006.175.08:04:14.04#ibcon#about to read 4, iclass 40, count 2 2006.175.08:04:14.04#ibcon#read 4, iclass 40, count 2 2006.175.08:04:14.04#ibcon#about to read 5, iclass 40, count 2 2006.175.08:04:14.04#ibcon#read 5, iclass 40, count 2 2006.175.08:04:14.04#ibcon#about to read 6, iclass 40, count 2 2006.175.08:04:14.04#ibcon#read 6, iclass 40, count 2 2006.175.08:04:14.04#ibcon#end of sib2, iclass 40, count 2 2006.175.08:04:14.04#ibcon#*after write, iclass 40, count 2 2006.175.08:04:14.04#ibcon#*before return 0, iclass 40, count 2 2006.175.08:04:14.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:04:14.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:04:14.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.08:04:14.04#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:14.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:04:14.05#abcon#[5=S1D000X0/0*\r\n] 2006.175.08:04:14.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:04:14.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:04:14.16#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:04:14.16#ibcon#first serial, iclass 40, count 0 2006.175.08:04:14.16#ibcon#enter sib2, iclass 40, count 0 2006.175.08:04:14.16#ibcon#flushed, iclass 40, count 0 2006.175.08:04:14.16#ibcon#about to write, iclass 40, count 0 2006.175.08:04:14.16#ibcon#wrote, iclass 40, count 0 2006.175.08:04:14.16#ibcon#about to read 3, iclass 40, count 0 2006.175.08:04:14.18#ibcon#read 3, iclass 40, count 0 2006.175.08:04:14.18#ibcon#about to read 4, iclass 40, count 0 2006.175.08:04:14.18#ibcon#read 4, iclass 40, count 0 2006.175.08:04:14.18#ibcon#about to read 5, iclass 40, count 0 2006.175.08:04:14.18#ibcon#read 5, iclass 40, count 0 2006.175.08:04:14.18#ibcon#about to read 6, iclass 40, count 0 2006.175.08:04:14.18#ibcon#read 6, iclass 40, count 0 2006.175.08:04:14.18#ibcon#end of sib2, iclass 40, count 0 2006.175.08:04:14.18#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:04:14.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:04:14.18#ibcon#[27=USB\r\n] 2006.175.08:04:14.18#ibcon#*before write, iclass 40, count 0 2006.175.08:04:14.18#ibcon#enter sib2, iclass 40, count 0 2006.175.08:04:14.18#ibcon#flushed, iclass 40, count 0 2006.175.08:04:14.18#ibcon#about to write, iclass 40, count 0 2006.175.08:04:14.18#ibcon#wrote, iclass 40, count 0 2006.175.08:04:14.18#ibcon#about to read 3, iclass 40, count 0 2006.175.08:04:14.21#ibcon#read 3, iclass 40, count 0 2006.175.08:04:14.21#ibcon#about to read 4, iclass 40, count 0 2006.175.08:04:14.21#ibcon#read 4, iclass 40, count 0 2006.175.08:04:14.21#ibcon#about to read 5, iclass 40, count 0 2006.175.08:04:14.21#ibcon#read 5, iclass 40, count 0 2006.175.08:04:14.21#ibcon#about to read 6, iclass 40, count 0 2006.175.08:04:14.21#ibcon#read 6, iclass 40, count 0 2006.175.08:04:14.21#ibcon#end of sib2, iclass 40, count 0 2006.175.08:04:14.21#ibcon#*after write, iclass 40, count 0 2006.175.08:04:14.21#ibcon#*before return 0, iclass 40, count 0 2006.175.08:04:14.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:04:14.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:04:14.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:04:14.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:04:14.21$vc4f8/vblo=3,656.99 2006.175.08:04:14.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.08:04:14.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.08:04:14.21#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:14.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:14.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:14.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:14.21#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:04:14.21#ibcon#first serial, iclass 7, count 0 2006.175.08:04:14.21#ibcon#enter sib2, iclass 7, count 0 2006.175.08:04:14.21#ibcon#flushed, iclass 7, count 0 2006.175.08:04:14.21#ibcon#about to write, iclass 7, count 0 2006.175.08:04:14.21#ibcon#wrote, iclass 7, count 0 2006.175.08:04:14.21#ibcon#about to read 3, iclass 7, count 0 2006.175.08:04:14.23#ibcon#read 3, iclass 7, count 0 2006.175.08:04:14.23#ibcon#about to read 4, iclass 7, count 0 2006.175.08:04:14.23#ibcon#read 4, iclass 7, count 0 2006.175.08:04:14.23#ibcon#about to read 5, iclass 7, count 0 2006.175.08:04:14.23#ibcon#read 5, iclass 7, count 0 2006.175.08:04:14.23#ibcon#about to read 6, iclass 7, count 0 2006.175.08:04:14.23#ibcon#read 6, iclass 7, count 0 2006.175.08:04:14.23#ibcon#end of sib2, iclass 7, count 0 2006.175.08:04:14.23#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:04:14.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:04:14.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:04:14.23#ibcon#*before write, iclass 7, count 0 2006.175.08:04:14.23#ibcon#enter sib2, iclass 7, count 0 2006.175.08:04:14.23#ibcon#flushed, iclass 7, count 0 2006.175.08:04:14.23#ibcon#about to write, iclass 7, count 0 2006.175.08:04:14.23#ibcon#wrote, iclass 7, count 0 2006.175.08:04:14.23#ibcon#about to read 3, iclass 7, count 0 2006.175.08:04:14.27#ibcon#read 3, iclass 7, count 0 2006.175.08:04:14.27#ibcon#about to read 4, iclass 7, count 0 2006.175.08:04:14.27#ibcon#read 4, iclass 7, count 0 2006.175.08:04:14.27#ibcon#about to read 5, iclass 7, count 0 2006.175.08:04:14.27#ibcon#read 5, iclass 7, count 0 2006.175.08:04:14.27#ibcon#about to read 6, iclass 7, count 0 2006.175.08:04:14.27#ibcon#read 6, iclass 7, count 0 2006.175.08:04:14.27#ibcon#end of sib2, iclass 7, count 0 2006.175.08:04:14.27#ibcon#*after write, iclass 7, count 0 2006.175.08:04:14.27#ibcon#*before return 0, iclass 7, count 0 2006.175.08:04:14.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:14.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:04:14.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:04:14.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:04:14.27$vc4f8/vb=3,4 2006.175.08:04:14.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.175.08:04:14.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.175.08:04:14.27#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:14.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:14.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:14.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:14.33#ibcon#enter wrdev, iclass 11, count 2 2006.175.08:04:14.33#ibcon#first serial, iclass 11, count 2 2006.175.08:04:14.33#ibcon#enter sib2, iclass 11, count 2 2006.175.08:04:14.33#ibcon#flushed, iclass 11, count 2 2006.175.08:04:14.33#ibcon#about to write, iclass 11, count 2 2006.175.08:04:14.33#ibcon#wrote, iclass 11, count 2 2006.175.08:04:14.33#ibcon#about to read 3, iclass 11, count 2 2006.175.08:04:14.35#ibcon#read 3, iclass 11, count 2 2006.175.08:04:14.35#ibcon#about to read 4, iclass 11, count 2 2006.175.08:04:14.35#ibcon#read 4, iclass 11, count 2 2006.175.08:04:14.35#ibcon#about to read 5, iclass 11, count 2 2006.175.08:04:14.35#ibcon#read 5, iclass 11, count 2 2006.175.08:04:14.35#ibcon#about to read 6, iclass 11, count 2 2006.175.08:04:14.35#ibcon#read 6, iclass 11, count 2 2006.175.08:04:14.35#ibcon#end of sib2, iclass 11, count 2 2006.175.08:04:14.35#ibcon#*mode == 0, iclass 11, count 2 2006.175.08:04:14.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.175.08:04:14.35#ibcon#[27=AT03-04\r\n] 2006.175.08:04:14.35#ibcon#*before write, iclass 11, count 2 2006.175.08:04:14.35#ibcon#enter sib2, iclass 11, count 2 2006.175.08:04:14.35#ibcon#flushed, iclass 11, count 2 2006.175.08:04:14.35#ibcon#about to write, iclass 11, count 2 2006.175.08:04:14.35#ibcon#wrote, iclass 11, count 2 2006.175.08:04:14.35#ibcon#about to read 3, iclass 11, count 2 2006.175.08:04:14.38#ibcon#read 3, iclass 11, count 2 2006.175.08:04:14.38#ibcon#about to read 4, iclass 11, count 2 2006.175.08:04:14.38#ibcon#read 4, iclass 11, count 2 2006.175.08:04:14.38#ibcon#about to read 5, iclass 11, count 2 2006.175.08:04:14.38#ibcon#read 5, iclass 11, count 2 2006.175.08:04:14.38#ibcon#about to read 6, iclass 11, count 2 2006.175.08:04:14.38#ibcon#read 6, iclass 11, count 2 2006.175.08:04:14.38#ibcon#end of sib2, iclass 11, count 2 2006.175.08:04:14.38#ibcon#*after write, iclass 11, count 2 2006.175.08:04:14.38#ibcon#*before return 0, iclass 11, count 2 2006.175.08:04:14.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:14.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:04:14.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.175.08:04:14.38#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:14.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:14.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:14.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:14.50#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:04:14.50#ibcon#first serial, iclass 11, count 0 2006.175.08:04:14.50#ibcon#enter sib2, iclass 11, count 0 2006.175.08:04:14.50#ibcon#flushed, iclass 11, count 0 2006.175.08:04:14.50#ibcon#about to write, iclass 11, count 0 2006.175.08:04:14.50#ibcon#wrote, iclass 11, count 0 2006.175.08:04:14.50#ibcon#about to read 3, iclass 11, count 0 2006.175.08:04:14.52#ibcon#read 3, iclass 11, count 0 2006.175.08:04:14.52#ibcon#about to read 4, iclass 11, count 0 2006.175.08:04:14.52#ibcon#read 4, iclass 11, count 0 2006.175.08:04:14.52#ibcon#about to read 5, iclass 11, count 0 2006.175.08:04:14.52#ibcon#read 5, iclass 11, count 0 2006.175.08:04:14.52#ibcon#about to read 6, iclass 11, count 0 2006.175.08:04:14.52#ibcon#read 6, iclass 11, count 0 2006.175.08:04:14.52#ibcon#end of sib2, iclass 11, count 0 2006.175.08:04:14.52#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:04:14.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:04:14.52#ibcon#[27=USB\r\n] 2006.175.08:04:14.52#ibcon#*before write, iclass 11, count 0 2006.175.08:04:14.52#ibcon#enter sib2, iclass 11, count 0 2006.175.08:04:14.52#ibcon#flushed, iclass 11, count 0 2006.175.08:04:14.52#ibcon#about to write, iclass 11, count 0 2006.175.08:04:14.52#ibcon#wrote, iclass 11, count 0 2006.175.08:04:14.52#ibcon#about to read 3, iclass 11, count 0 2006.175.08:04:14.55#ibcon#read 3, iclass 11, count 0 2006.175.08:04:14.55#ibcon#about to read 4, iclass 11, count 0 2006.175.08:04:14.55#ibcon#read 4, iclass 11, count 0 2006.175.08:04:14.55#ibcon#about to read 5, iclass 11, count 0 2006.175.08:04:14.55#ibcon#read 5, iclass 11, count 0 2006.175.08:04:14.55#ibcon#about to read 6, iclass 11, count 0 2006.175.08:04:14.55#ibcon#read 6, iclass 11, count 0 2006.175.08:04:14.55#ibcon#end of sib2, iclass 11, count 0 2006.175.08:04:14.55#ibcon#*after write, iclass 11, count 0 2006.175.08:04:14.55#ibcon#*before return 0, iclass 11, count 0 2006.175.08:04:14.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:14.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:04:14.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:04:14.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:04:14.55$vc4f8/vblo=4,712.99 2006.175.08:04:14.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.175.08:04:14.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.175.08:04:14.55#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:14.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:14.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:14.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:14.55#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:04:14.55#ibcon#first serial, iclass 13, count 0 2006.175.08:04:14.55#ibcon#enter sib2, iclass 13, count 0 2006.175.08:04:14.55#ibcon#flushed, iclass 13, count 0 2006.175.08:04:14.55#ibcon#about to write, iclass 13, count 0 2006.175.08:04:14.55#ibcon#wrote, iclass 13, count 0 2006.175.08:04:14.55#ibcon#about to read 3, iclass 13, count 0 2006.175.08:04:14.57#ibcon#read 3, iclass 13, count 0 2006.175.08:04:14.57#ibcon#about to read 4, iclass 13, count 0 2006.175.08:04:14.57#ibcon#read 4, iclass 13, count 0 2006.175.08:04:14.57#ibcon#about to read 5, iclass 13, count 0 2006.175.08:04:14.57#ibcon#read 5, iclass 13, count 0 2006.175.08:04:14.57#ibcon#about to read 6, iclass 13, count 0 2006.175.08:04:14.57#ibcon#read 6, iclass 13, count 0 2006.175.08:04:14.57#ibcon#end of sib2, iclass 13, count 0 2006.175.08:04:14.57#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:04:14.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:04:14.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:04:14.57#ibcon#*before write, iclass 13, count 0 2006.175.08:04:14.57#ibcon#enter sib2, iclass 13, count 0 2006.175.08:04:14.57#ibcon#flushed, iclass 13, count 0 2006.175.08:04:14.57#ibcon#about to write, iclass 13, count 0 2006.175.08:04:14.57#ibcon#wrote, iclass 13, count 0 2006.175.08:04:14.57#ibcon#about to read 3, iclass 13, count 0 2006.175.08:04:14.61#ibcon#read 3, iclass 13, count 0 2006.175.08:04:14.61#ibcon#about to read 4, iclass 13, count 0 2006.175.08:04:14.61#ibcon#read 4, iclass 13, count 0 2006.175.08:04:14.61#ibcon#about to read 5, iclass 13, count 0 2006.175.08:04:14.61#ibcon#read 5, iclass 13, count 0 2006.175.08:04:14.61#ibcon#about to read 6, iclass 13, count 0 2006.175.08:04:14.61#ibcon#read 6, iclass 13, count 0 2006.175.08:04:14.61#ibcon#end of sib2, iclass 13, count 0 2006.175.08:04:14.61#ibcon#*after write, iclass 13, count 0 2006.175.08:04:14.61#ibcon#*before return 0, iclass 13, count 0 2006.175.08:04:14.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:14.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:04:14.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:04:14.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:04:14.61$vc4f8/vb=4,4 2006.175.08:04:14.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.175.08:04:14.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.175.08:04:14.61#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:14.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:14.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:14.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:14.67#ibcon#enter wrdev, iclass 15, count 2 2006.175.08:04:14.67#ibcon#first serial, iclass 15, count 2 2006.175.08:04:14.67#ibcon#enter sib2, iclass 15, count 2 2006.175.08:04:14.67#ibcon#flushed, iclass 15, count 2 2006.175.08:04:14.67#ibcon#about to write, iclass 15, count 2 2006.175.08:04:14.67#ibcon#wrote, iclass 15, count 2 2006.175.08:04:14.67#ibcon#about to read 3, iclass 15, count 2 2006.175.08:04:14.69#ibcon#read 3, iclass 15, count 2 2006.175.08:04:14.69#ibcon#about to read 4, iclass 15, count 2 2006.175.08:04:14.69#ibcon#read 4, iclass 15, count 2 2006.175.08:04:14.69#ibcon#about to read 5, iclass 15, count 2 2006.175.08:04:14.69#ibcon#read 5, iclass 15, count 2 2006.175.08:04:14.69#ibcon#about to read 6, iclass 15, count 2 2006.175.08:04:14.69#ibcon#read 6, iclass 15, count 2 2006.175.08:04:14.69#ibcon#end of sib2, iclass 15, count 2 2006.175.08:04:14.69#ibcon#*mode == 0, iclass 15, count 2 2006.175.08:04:14.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.175.08:04:14.69#ibcon#[27=AT04-04\r\n] 2006.175.08:04:14.69#ibcon#*before write, iclass 15, count 2 2006.175.08:04:14.69#ibcon#enter sib2, iclass 15, count 2 2006.175.08:04:14.69#ibcon#flushed, iclass 15, count 2 2006.175.08:04:14.69#ibcon#about to write, iclass 15, count 2 2006.175.08:04:14.69#ibcon#wrote, iclass 15, count 2 2006.175.08:04:14.69#ibcon#about to read 3, iclass 15, count 2 2006.175.08:04:14.72#ibcon#read 3, iclass 15, count 2 2006.175.08:04:14.72#ibcon#about to read 4, iclass 15, count 2 2006.175.08:04:14.72#ibcon#read 4, iclass 15, count 2 2006.175.08:04:14.72#ibcon#about to read 5, iclass 15, count 2 2006.175.08:04:14.72#ibcon#read 5, iclass 15, count 2 2006.175.08:04:14.72#ibcon#about to read 6, iclass 15, count 2 2006.175.08:04:14.72#ibcon#read 6, iclass 15, count 2 2006.175.08:04:14.72#ibcon#end of sib2, iclass 15, count 2 2006.175.08:04:14.72#ibcon#*after write, iclass 15, count 2 2006.175.08:04:14.72#ibcon#*before return 0, iclass 15, count 2 2006.175.08:04:14.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:14.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:04:14.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.175.08:04:14.72#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:14.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:14.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:14.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:14.84#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:04:14.84#ibcon#first serial, iclass 15, count 0 2006.175.08:04:14.84#ibcon#enter sib2, iclass 15, count 0 2006.175.08:04:14.84#ibcon#flushed, iclass 15, count 0 2006.175.08:04:14.84#ibcon#about to write, iclass 15, count 0 2006.175.08:04:14.84#ibcon#wrote, iclass 15, count 0 2006.175.08:04:14.84#ibcon#about to read 3, iclass 15, count 0 2006.175.08:04:14.86#ibcon#read 3, iclass 15, count 0 2006.175.08:04:14.86#ibcon#about to read 4, iclass 15, count 0 2006.175.08:04:14.86#ibcon#read 4, iclass 15, count 0 2006.175.08:04:14.86#ibcon#about to read 5, iclass 15, count 0 2006.175.08:04:14.86#ibcon#read 5, iclass 15, count 0 2006.175.08:04:14.86#ibcon#about to read 6, iclass 15, count 0 2006.175.08:04:14.86#ibcon#read 6, iclass 15, count 0 2006.175.08:04:14.86#ibcon#end of sib2, iclass 15, count 0 2006.175.08:04:14.86#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:04:14.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:04:14.86#ibcon#[27=USB\r\n] 2006.175.08:04:14.86#ibcon#*before write, iclass 15, count 0 2006.175.08:04:14.86#ibcon#enter sib2, iclass 15, count 0 2006.175.08:04:14.86#ibcon#flushed, iclass 15, count 0 2006.175.08:04:14.86#ibcon#about to write, iclass 15, count 0 2006.175.08:04:14.86#ibcon#wrote, iclass 15, count 0 2006.175.08:04:14.86#ibcon#about to read 3, iclass 15, count 0 2006.175.08:04:14.89#ibcon#read 3, iclass 15, count 0 2006.175.08:04:14.89#ibcon#about to read 4, iclass 15, count 0 2006.175.08:04:14.89#ibcon#read 4, iclass 15, count 0 2006.175.08:04:14.89#ibcon#about to read 5, iclass 15, count 0 2006.175.08:04:14.89#ibcon#read 5, iclass 15, count 0 2006.175.08:04:14.89#ibcon#about to read 6, iclass 15, count 0 2006.175.08:04:14.89#ibcon#read 6, iclass 15, count 0 2006.175.08:04:14.89#ibcon#end of sib2, iclass 15, count 0 2006.175.08:04:14.89#ibcon#*after write, iclass 15, count 0 2006.175.08:04:14.89#ibcon#*before return 0, iclass 15, count 0 2006.175.08:04:14.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:14.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:04:14.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:04:14.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:04:14.89$vc4f8/vblo=5,744.99 2006.175.08:04:14.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.08:04:14.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.08:04:14.89#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:14.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:14.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:14.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:14.89#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:04:14.89#ibcon#first serial, iclass 17, count 0 2006.175.08:04:14.89#ibcon#enter sib2, iclass 17, count 0 2006.175.08:04:14.89#ibcon#flushed, iclass 17, count 0 2006.175.08:04:14.89#ibcon#about to write, iclass 17, count 0 2006.175.08:04:14.89#ibcon#wrote, iclass 17, count 0 2006.175.08:04:14.89#ibcon#about to read 3, iclass 17, count 0 2006.175.08:04:14.91#ibcon#read 3, iclass 17, count 0 2006.175.08:04:14.91#ibcon#about to read 4, iclass 17, count 0 2006.175.08:04:14.91#ibcon#read 4, iclass 17, count 0 2006.175.08:04:14.91#ibcon#about to read 5, iclass 17, count 0 2006.175.08:04:14.91#ibcon#read 5, iclass 17, count 0 2006.175.08:04:14.91#ibcon#about to read 6, iclass 17, count 0 2006.175.08:04:14.91#ibcon#read 6, iclass 17, count 0 2006.175.08:04:14.91#ibcon#end of sib2, iclass 17, count 0 2006.175.08:04:14.91#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:04:14.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:04:14.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:04:14.91#ibcon#*before write, iclass 17, count 0 2006.175.08:04:14.91#ibcon#enter sib2, iclass 17, count 0 2006.175.08:04:14.91#ibcon#flushed, iclass 17, count 0 2006.175.08:04:14.91#ibcon#about to write, iclass 17, count 0 2006.175.08:04:14.91#ibcon#wrote, iclass 17, count 0 2006.175.08:04:14.91#ibcon#about to read 3, iclass 17, count 0 2006.175.08:04:14.95#ibcon#read 3, iclass 17, count 0 2006.175.08:04:14.95#ibcon#about to read 4, iclass 17, count 0 2006.175.08:04:14.95#ibcon#read 4, iclass 17, count 0 2006.175.08:04:14.95#ibcon#about to read 5, iclass 17, count 0 2006.175.08:04:14.95#ibcon#read 5, iclass 17, count 0 2006.175.08:04:14.95#ibcon#about to read 6, iclass 17, count 0 2006.175.08:04:14.95#ibcon#read 6, iclass 17, count 0 2006.175.08:04:14.95#ibcon#end of sib2, iclass 17, count 0 2006.175.08:04:14.95#ibcon#*after write, iclass 17, count 0 2006.175.08:04:14.95#ibcon#*before return 0, iclass 17, count 0 2006.175.08:04:14.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:14.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:04:14.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:04:14.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:04:14.95$vc4f8/vb=5,4 2006.175.08:04:14.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.175.08:04:14.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.175.08:04:14.95#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:14.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:15.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:15.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:15.01#ibcon#enter wrdev, iclass 19, count 2 2006.175.08:04:15.01#ibcon#first serial, iclass 19, count 2 2006.175.08:04:15.01#ibcon#enter sib2, iclass 19, count 2 2006.175.08:04:15.01#ibcon#flushed, iclass 19, count 2 2006.175.08:04:15.01#ibcon#about to write, iclass 19, count 2 2006.175.08:04:15.01#ibcon#wrote, iclass 19, count 2 2006.175.08:04:15.01#ibcon#about to read 3, iclass 19, count 2 2006.175.08:04:15.03#ibcon#read 3, iclass 19, count 2 2006.175.08:04:15.03#ibcon#about to read 4, iclass 19, count 2 2006.175.08:04:15.03#ibcon#read 4, iclass 19, count 2 2006.175.08:04:15.03#ibcon#about to read 5, iclass 19, count 2 2006.175.08:04:15.03#ibcon#read 5, iclass 19, count 2 2006.175.08:04:15.03#ibcon#about to read 6, iclass 19, count 2 2006.175.08:04:15.03#ibcon#read 6, iclass 19, count 2 2006.175.08:04:15.03#ibcon#end of sib2, iclass 19, count 2 2006.175.08:04:15.03#ibcon#*mode == 0, iclass 19, count 2 2006.175.08:04:15.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.175.08:04:15.03#ibcon#[27=AT05-04\r\n] 2006.175.08:04:15.03#ibcon#*before write, iclass 19, count 2 2006.175.08:04:15.03#ibcon#enter sib2, iclass 19, count 2 2006.175.08:04:15.03#ibcon#flushed, iclass 19, count 2 2006.175.08:04:15.03#ibcon#about to write, iclass 19, count 2 2006.175.08:04:15.03#ibcon#wrote, iclass 19, count 2 2006.175.08:04:15.03#ibcon#about to read 3, iclass 19, count 2 2006.175.08:04:15.06#ibcon#read 3, iclass 19, count 2 2006.175.08:04:15.06#ibcon#about to read 4, iclass 19, count 2 2006.175.08:04:15.06#ibcon#read 4, iclass 19, count 2 2006.175.08:04:15.06#ibcon#about to read 5, iclass 19, count 2 2006.175.08:04:15.06#ibcon#read 5, iclass 19, count 2 2006.175.08:04:15.06#ibcon#about to read 6, iclass 19, count 2 2006.175.08:04:15.06#ibcon#read 6, iclass 19, count 2 2006.175.08:04:15.06#ibcon#end of sib2, iclass 19, count 2 2006.175.08:04:15.06#ibcon#*after write, iclass 19, count 2 2006.175.08:04:15.06#ibcon#*before return 0, iclass 19, count 2 2006.175.08:04:15.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:15.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:04:15.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.175.08:04:15.06#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:15.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:15.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:15.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:15.18#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:04:15.18#ibcon#first serial, iclass 19, count 0 2006.175.08:04:15.18#ibcon#enter sib2, iclass 19, count 0 2006.175.08:04:15.18#ibcon#flushed, iclass 19, count 0 2006.175.08:04:15.18#ibcon#about to write, iclass 19, count 0 2006.175.08:04:15.18#ibcon#wrote, iclass 19, count 0 2006.175.08:04:15.18#ibcon#about to read 3, iclass 19, count 0 2006.175.08:04:15.20#ibcon#read 3, iclass 19, count 0 2006.175.08:04:15.20#ibcon#about to read 4, iclass 19, count 0 2006.175.08:04:15.20#ibcon#read 4, iclass 19, count 0 2006.175.08:04:15.20#ibcon#about to read 5, iclass 19, count 0 2006.175.08:04:15.20#ibcon#read 5, iclass 19, count 0 2006.175.08:04:15.20#ibcon#about to read 6, iclass 19, count 0 2006.175.08:04:15.20#ibcon#read 6, iclass 19, count 0 2006.175.08:04:15.20#ibcon#end of sib2, iclass 19, count 0 2006.175.08:04:15.20#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:04:15.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:04:15.20#ibcon#[27=USB\r\n] 2006.175.08:04:15.20#ibcon#*before write, iclass 19, count 0 2006.175.08:04:15.20#ibcon#enter sib2, iclass 19, count 0 2006.175.08:04:15.20#ibcon#flushed, iclass 19, count 0 2006.175.08:04:15.20#ibcon#about to write, iclass 19, count 0 2006.175.08:04:15.20#ibcon#wrote, iclass 19, count 0 2006.175.08:04:15.20#ibcon#about to read 3, iclass 19, count 0 2006.175.08:04:15.23#ibcon#read 3, iclass 19, count 0 2006.175.08:04:15.23#ibcon#about to read 4, iclass 19, count 0 2006.175.08:04:15.23#ibcon#read 4, iclass 19, count 0 2006.175.08:04:15.23#ibcon#about to read 5, iclass 19, count 0 2006.175.08:04:15.23#ibcon#read 5, iclass 19, count 0 2006.175.08:04:15.23#ibcon#about to read 6, iclass 19, count 0 2006.175.08:04:15.23#ibcon#read 6, iclass 19, count 0 2006.175.08:04:15.23#ibcon#end of sib2, iclass 19, count 0 2006.175.08:04:15.23#ibcon#*after write, iclass 19, count 0 2006.175.08:04:15.23#ibcon#*before return 0, iclass 19, count 0 2006.175.08:04:15.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:15.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:04:15.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:04:15.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:04:15.23$vc4f8/vblo=6,752.99 2006.175.08:04:15.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.08:04:15.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.08:04:15.23#ibcon#ireg 17 cls_cnt 0 2006.175.08:04:15.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:15.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:15.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:15.23#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:04:15.23#ibcon#first serial, iclass 21, count 0 2006.175.08:04:15.23#ibcon#enter sib2, iclass 21, count 0 2006.175.08:04:15.23#ibcon#flushed, iclass 21, count 0 2006.175.08:04:15.23#ibcon#about to write, iclass 21, count 0 2006.175.08:04:15.23#ibcon#wrote, iclass 21, count 0 2006.175.08:04:15.23#ibcon#about to read 3, iclass 21, count 0 2006.175.08:04:15.25#ibcon#read 3, iclass 21, count 0 2006.175.08:04:15.25#ibcon#about to read 4, iclass 21, count 0 2006.175.08:04:15.25#ibcon#read 4, iclass 21, count 0 2006.175.08:04:15.25#ibcon#about to read 5, iclass 21, count 0 2006.175.08:04:15.25#ibcon#read 5, iclass 21, count 0 2006.175.08:04:15.25#ibcon#about to read 6, iclass 21, count 0 2006.175.08:04:15.25#ibcon#read 6, iclass 21, count 0 2006.175.08:04:15.25#ibcon#end of sib2, iclass 21, count 0 2006.175.08:04:15.25#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:04:15.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:04:15.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:04:15.25#ibcon#*before write, iclass 21, count 0 2006.175.08:04:15.25#ibcon#enter sib2, iclass 21, count 0 2006.175.08:04:15.25#ibcon#flushed, iclass 21, count 0 2006.175.08:04:15.25#ibcon#about to write, iclass 21, count 0 2006.175.08:04:15.25#ibcon#wrote, iclass 21, count 0 2006.175.08:04:15.25#ibcon#about to read 3, iclass 21, count 0 2006.175.08:04:15.29#ibcon#read 3, iclass 21, count 0 2006.175.08:04:15.29#ibcon#about to read 4, iclass 21, count 0 2006.175.08:04:15.29#ibcon#read 4, iclass 21, count 0 2006.175.08:04:15.29#ibcon#about to read 5, iclass 21, count 0 2006.175.08:04:15.29#ibcon#read 5, iclass 21, count 0 2006.175.08:04:15.29#ibcon#about to read 6, iclass 21, count 0 2006.175.08:04:15.29#ibcon#read 6, iclass 21, count 0 2006.175.08:04:15.29#ibcon#end of sib2, iclass 21, count 0 2006.175.08:04:15.29#ibcon#*after write, iclass 21, count 0 2006.175.08:04:15.29#ibcon#*before return 0, iclass 21, count 0 2006.175.08:04:15.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:15.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:04:15.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:04:15.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:04:15.29$vc4f8/vb=6,4 2006.175.08:04:15.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.08:04:15.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.08:04:15.29#ibcon#ireg 11 cls_cnt 2 2006.175.08:04:15.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:15.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:15.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:15.35#ibcon#enter wrdev, iclass 23, count 2 2006.175.08:04:15.35#ibcon#first serial, iclass 23, count 2 2006.175.08:04:15.35#ibcon#enter sib2, iclass 23, count 2 2006.175.08:04:15.35#ibcon#flushed, iclass 23, count 2 2006.175.08:04:15.35#ibcon#about to write, iclass 23, count 2 2006.175.08:04:15.35#ibcon#wrote, iclass 23, count 2 2006.175.08:04:15.35#ibcon#about to read 3, iclass 23, count 2 2006.175.08:04:15.37#ibcon#read 3, iclass 23, count 2 2006.175.08:04:15.37#ibcon#about to read 4, iclass 23, count 2 2006.175.08:04:15.37#ibcon#read 4, iclass 23, count 2 2006.175.08:04:15.37#ibcon#about to read 5, iclass 23, count 2 2006.175.08:04:15.37#ibcon#read 5, iclass 23, count 2 2006.175.08:04:15.37#ibcon#about to read 6, iclass 23, count 2 2006.175.08:04:15.37#ibcon#read 6, iclass 23, count 2 2006.175.08:04:15.37#ibcon#end of sib2, iclass 23, count 2 2006.175.08:04:15.37#ibcon#*mode == 0, iclass 23, count 2 2006.175.08:04:15.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.08:04:15.37#ibcon#[27=AT06-04\r\n] 2006.175.08:04:15.37#ibcon#*before write, iclass 23, count 2 2006.175.08:04:15.37#ibcon#enter sib2, iclass 23, count 2 2006.175.08:04:15.37#ibcon#flushed, iclass 23, count 2 2006.175.08:04:15.37#ibcon#about to write, iclass 23, count 2 2006.175.08:04:15.37#ibcon#wrote, iclass 23, count 2 2006.175.08:04:15.37#ibcon#about to read 3, iclass 23, count 2 2006.175.08:04:15.40#ibcon#read 3, iclass 23, count 2 2006.175.08:04:15.40#ibcon#about to read 4, iclass 23, count 2 2006.175.08:04:15.40#ibcon#read 4, iclass 23, count 2 2006.175.08:04:15.40#ibcon#about to read 5, iclass 23, count 2 2006.175.08:04:15.40#ibcon#read 5, iclass 23, count 2 2006.175.08:04:15.40#ibcon#about to read 6, iclass 23, count 2 2006.175.08:04:15.40#ibcon#read 6, iclass 23, count 2 2006.175.08:04:15.40#ibcon#end of sib2, iclass 23, count 2 2006.175.08:04:15.40#ibcon#*after write, iclass 23, count 2 2006.175.08:04:15.40#ibcon#*before return 0, iclass 23, count 2 2006.175.08:04:15.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:15.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:04:15.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.08:04:15.40#ibcon#ireg 7 cls_cnt 0 2006.175.08:04:15.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:15.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:15.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:15.52#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:04:15.52#ibcon#first serial, iclass 23, count 0 2006.175.08:04:15.52#ibcon#enter sib2, iclass 23, count 0 2006.175.08:04:15.52#ibcon#flushed, iclass 23, count 0 2006.175.08:04:15.52#ibcon#about to write, iclass 23, count 0 2006.175.08:04:15.52#ibcon#wrote, iclass 23, count 0 2006.175.08:04:15.52#ibcon#about to read 3, iclass 23, count 0 2006.175.08:04:15.54#ibcon#read 3, iclass 23, count 0 2006.175.08:04:15.54#ibcon#about to read 4, iclass 23, count 0 2006.175.08:04:15.54#ibcon#read 4, iclass 23, count 0 2006.175.08:04:15.54#ibcon#about to read 5, iclass 23, count 0 2006.175.08:04:15.54#ibcon#read 5, iclass 23, count 0 2006.175.08:04:15.54#ibcon#about to read 6, iclass 23, count 0 2006.175.08:04:15.54#ibcon#read 6, iclass 23, count 0 2006.175.08:04:15.54#ibcon#end of sib2, iclass 23, count 0 2006.175.08:04:15.54#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:04:15.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:04:15.54#ibcon#[27=USB\r\n] 2006.175.08:04:15.54#ibcon#*before write, iclass 23, count 0 2006.175.08:04:15.54#ibcon#enter sib2, iclass 23, count 0 2006.175.08:04:15.54#ibcon#flushed, iclass 23, count 0 2006.175.08:04:15.54#ibcon#about to write, iclass 23, count 0 2006.175.08:04:15.54#ibcon#wrote, iclass 23, count 0 2006.175.08:04:15.54#ibcon#about to read 3, iclass 23, count 0 2006.175.08:04:15.57#ibcon#read 3, iclass 23, count 0 2006.175.08:04:15.57#ibcon#about to read 4, iclass 23, count 0 2006.175.08:04:15.57#ibcon#read 4, iclass 23, count 0 2006.175.08:04:15.57#ibcon#about to read 5, iclass 23, count 0 2006.175.08:04:15.57#ibcon#read 5, iclass 23, count 0 2006.175.08:04:15.57#ibcon#about to read 6, iclass 23, count 0 2006.175.08:04:15.57#ibcon#read 6, iclass 23, count 0 2006.175.08:04:15.57#ibcon#end of sib2, iclass 23, count 0 2006.175.08:04:15.57#ibcon#*after write, iclass 23, count 0 2006.175.08:04:15.57#ibcon#*before return 0, iclass 23, count 0 2006.175.08:04:15.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:15.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:04:15.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:04:15.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:04:15.57$vc4f8/vabw=wide 2006.175.08:04:15.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.08:04:15.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.08:04:15.57#ibcon#ireg 8 cls_cnt 0 2006.175.08:04:15.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:15.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:15.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:15.57#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:04:15.57#ibcon#first serial, iclass 25, count 0 2006.175.08:04:15.57#ibcon#enter sib2, iclass 25, count 0 2006.175.08:04:15.57#ibcon#flushed, iclass 25, count 0 2006.175.08:04:15.57#ibcon#about to write, iclass 25, count 0 2006.175.08:04:15.57#ibcon#wrote, iclass 25, count 0 2006.175.08:04:15.57#ibcon#about to read 3, iclass 25, count 0 2006.175.08:04:15.59#ibcon#read 3, iclass 25, count 0 2006.175.08:04:15.59#ibcon#about to read 4, iclass 25, count 0 2006.175.08:04:15.59#ibcon#read 4, iclass 25, count 0 2006.175.08:04:15.59#ibcon#about to read 5, iclass 25, count 0 2006.175.08:04:15.59#ibcon#read 5, iclass 25, count 0 2006.175.08:04:15.59#ibcon#about to read 6, iclass 25, count 0 2006.175.08:04:15.59#ibcon#read 6, iclass 25, count 0 2006.175.08:04:15.59#ibcon#end of sib2, iclass 25, count 0 2006.175.08:04:15.59#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:04:15.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:04:15.59#ibcon#[25=BW32\r\n] 2006.175.08:04:15.59#ibcon#*before write, iclass 25, count 0 2006.175.08:04:15.59#ibcon#enter sib2, iclass 25, count 0 2006.175.08:04:15.59#ibcon#flushed, iclass 25, count 0 2006.175.08:04:15.59#ibcon#about to write, iclass 25, count 0 2006.175.08:04:15.59#ibcon#wrote, iclass 25, count 0 2006.175.08:04:15.59#ibcon#about to read 3, iclass 25, count 0 2006.175.08:04:15.62#ibcon#read 3, iclass 25, count 0 2006.175.08:04:15.62#ibcon#about to read 4, iclass 25, count 0 2006.175.08:04:15.62#ibcon#read 4, iclass 25, count 0 2006.175.08:04:15.62#ibcon#about to read 5, iclass 25, count 0 2006.175.08:04:15.62#ibcon#read 5, iclass 25, count 0 2006.175.08:04:15.62#ibcon#about to read 6, iclass 25, count 0 2006.175.08:04:15.62#ibcon#read 6, iclass 25, count 0 2006.175.08:04:15.62#ibcon#end of sib2, iclass 25, count 0 2006.175.08:04:15.62#ibcon#*after write, iclass 25, count 0 2006.175.08:04:15.62#ibcon#*before return 0, iclass 25, count 0 2006.175.08:04:15.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:15.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:04:15.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:04:15.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:04:15.62$vc4f8/vbbw=wide 2006.175.08:04:15.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.08:04:15.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.08:04:15.62#ibcon#ireg 8 cls_cnt 0 2006.175.08:04:15.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:04:15.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:04:15.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:04:15.69#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:04:15.69#ibcon#first serial, iclass 27, count 0 2006.175.08:04:15.69#ibcon#enter sib2, iclass 27, count 0 2006.175.08:04:15.69#ibcon#flushed, iclass 27, count 0 2006.175.08:04:15.69#ibcon#about to write, iclass 27, count 0 2006.175.08:04:15.69#ibcon#wrote, iclass 27, count 0 2006.175.08:04:15.69#ibcon#about to read 3, iclass 27, count 0 2006.175.08:04:15.71#ibcon#read 3, iclass 27, count 0 2006.175.08:04:15.71#ibcon#about to read 4, iclass 27, count 0 2006.175.08:04:15.71#ibcon#read 4, iclass 27, count 0 2006.175.08:04:15.71#ibcon#about to read 5, iclass 27, count 0 2006.175.08:04:15.71#ibcon#read 5, iclass 27, count 0 2006.175.08:04:15.71#ibcon#about to read 6, iclass 27, count 0 2006.175.08:04:15.71#ibcon#read 6, iclass 27, count 0 2006.175.08:04:15.71#ibcon#end of sib2, iclass 27, count 0 2006.175.08:04:15.71#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:04:15.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:04:15.71#ibcon#[27=BW32\r\n] 2006.175.08:04:15.71#ibcon#*before write, iclass 27, count 0 2006.175.08:04:15.71#ibcon#enter sib2, iclass 27, count 0 2006.175.08:04:15.71#ibcon#flushed, iclass 27, count 0 2006.175.08:04:15.71#ibcon#about to write, iclass 27, count 0 2006.175.08:04:15.71#ibcon#wrote, iclass 27, count 0 2006.175.08:04:15.71#ibcon#about to read 3, iclass 27, count 0 2006.175.08:04:15.74#ibcon#read 3, iclass 27, count 0 2006.175.08:04:15.74#ibcon#about to read 4, iclass 27, count 0 2006.175.08:04:15.74#ibcon#read 4, iclass 27, count 0 2006.175.08:04:15.74#ibcon#about to read 5, iclass 27, count 0 2006.175.08:04:15.74#ibcon#read 5, iclass 27, count 0 2006.175.08:04:15.74#ibcon#about to read 6, iclass 27, count 0 2006.175.08:04:15.74#ibcon#read 6, iclass 27, count 0 2006.175.08:04:15.74#ibcon#end of sib2, iclass 27, count 0 2006.175.08:04:15.74#ibcon#*after write, iclass 27, count 0 2006.175.08:04:15.74#ibcon#*before return 0, iclass 27, count 0 2006.175.08:04:15.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:04:15.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:04:15.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:04:15.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:04:15.74$4f8m12a/ifd4f 2006.175.08:04:15.74$ifd4f/lo= 2006.175.08:04:15.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:04:15.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:04:15.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:04:15.74$ifd4f/patch= 2006.175.08:04:15.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:04:15.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:04:15.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:04:15.74$4f8m12a/"form=m,16.000,1:2 2006.175.08:04:15.74$4f8m12a/"tpicd 2006.175.08:04:15.75$4f8m12a/echo=off 2006.175.08:04:15.75$4f8m12a/xlog=off 2006.175.08:04:15.75:!2006.175.08:04:40 2006.175.08:04:19.14#trakl#Source acquired 2006.175.08:04:19.14#flagr#flagr/antenna,acquired 2006.175.08:04:40.01:preob 2006.175.08:04:41.14/onsource/TRACKING 2006.175.08:04:41.14:!2006.175.08:04:50 2006.175.08:04:50.00:data_valid=on 2006.175.08:04:50.00:midob 2006.175.08:04:50.14/onsource/TRACKING 2006.175.08:04:50.14/wx/25.86,1007.4,69 2006.175.08:04:50.33/cable/+6.4775E-03 2006.175.08:04:51.42/va/01,08,usb,yes,28,30 2006.175.08:04:51.42/va/02,07,usb,yes,28,30 2006.175.08:04:51.42/va/03,06,usb,yes,30,30 2006.175.08:04:51.42/va/04,07,usb,yes,29,31 2006.175.08:04:51.42/va/05,07,usb,yes,29,31 2006.175.08:04:51.42/va/06,06,usb,yes,29,28 2006.175.08:04:51.42/va/07,06,usb,yes,29,29 2006.175.08:04:51.42/va/08,06,usb,yes,31,31 2006.175.08:04:51.65/valo/01,532.99,yes,locked 2006.175.08:04:51.65/valo/02,572.99,yes,locked 2006.175.08:04:51.65/valo/03,672.99,yes,locked 2006.175.08:04:51.65/valo/04,832.99,yes,locked 2006.175.08:04:51.65/valo/05,652.99,yes,locked 2006.175.08:04:51.65/valo/06,772.99,yes,locked 2006.175.08:04:51.65/valo/07,832.99,yes,locked 2006.175.08:04:51.65/valo/08,852.99,yes,locked 2006.175.08:04:52.74/vb/01,04,usb,yes,29,27 2006.175.08:04:52.74/vb/02,04,usb,yes,30,32 2006.175.08:04:52.74/vb/03,04,usb,yes,27,30 2006.175.08:04:52.74/vb/04,04,usb,yes,28,28 2006.175.08:04:52.74/vb/05,04,usb,yes,26,30 2006.175.08:04:52.74/vb/06,04,usb,yes,27,30 2006.175.08:04:52.74/vb/07,04,usb,yes,29,29 2006.175.08:04:52.74/vb/08,04,usb,yes,27,30 2006.175.08:04:52.97/vblo/01,632.99,yes,locked 2006.175.08:04:52.97/vblo/02,640.99,yes,locked 2006.175.08:04:52.97/vblo/03,656.99,yes,locked 2006.175.08:04:52.97/vblo/04,712.99,yes,locked 2006.175.08:04:52.97/vblo/05,744.99,yes,locked 2006.175.08:04:52.97/vblo/06,752.99,yes,locked 2006.175.08:04:52.97/vblo/07,734.99,yes,locked 2006.175.08:04:52.97/vblo/08,744.99,yes,locked 2006.175.08:04:53.12/vabw/8 2006.175.08:04:53.27/vbbw/8 2006.175.08:04:53.36/xfe/off,on,15.2 2006.175.08:04:53.74/ifatt/23,28,28,28 2006.175.08:04:54.07/fmout-gps/S +3.75E-07 2006.175.08:04:54.15:!2006.175.08:05:50 2006.175.08:05:50.01:data_valid=off 2006.175.08:05:50.02:postob 2006.175.08:05:50.20/cable/+6.4758E-03 2006.175.08:05:50.21/wx/25.85,1007.4,69 2006.175.08:05:51.07/fmout-gps/S +3.76E-07 2006.175.08:05:51.08:scan_name=175-0806,k06175,60 2006.175.08:05:51.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.175.08:05:51.14#flagr#flagr/antenna,new-source 2006.175.08:05:52.14:checkk5 2006.175.08:05:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:05:52.92/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:05:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:05:53.67/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:05:54.04/chk_obsdata//k5ts1/T1750804??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.175.08:05:54.41/chk_obsdata//k5ts2/T1750804??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.175.08:05:54.79/chk_obsdata//k5ts3/T1750804??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.175.08:05:55.16/chk_obsdata//k5ts4/T1750804??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.175.08:05:55.85/k5log//k5ts1_log_newline 2006.175.08:05:56.55/k5log//k5ts2_log_newline 2006.175.08:05:57.24/k5log//k5ts3_log_newline 2006.175.08:05:57.93/k5log//k5ts4_log_newline 2006.175.08:05:57.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:05:57.96:4f8m12a=2 2006.175.08:05:57.96$4f8m12a/echo=on 2006.175.08:05:57.96$4f8m12a/pcalon 2006.175.08:05:57.96$pcalon/"no phase cal control is implemented here 2006.175.08:05:57.96$4f8m12a/"tpicd=stop 2006.175.08:05:57.96$4f8m12a/vc4f8 2006.175.08:05:57.96$vc4f8/valo=1,532.99 2006.175.08:05:57.96#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.08:05:57.96#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.08:05:57.96#ibcon#ireg 17 cls_cnt 0 2006.175.08:05:57.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:05:57.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:05:57.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:05:57.96#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:05:57.96#ibcon#first serial, iclass 34, count 0 2006.175.08:05:57.96#ibcon#enter sib2, iclass 34, count 0 2006.175.08:05:57.96#ibcon#flushed, iclass 34, count 0 2006.175.08:05:57.96#ibcon#about to write, iclass 34, count 0 2006.175.08:05:57.96#ibcon#wrote, iclass 34, count 0 2006.175.08:05:57.96#ibcon#about to read 3, iclass 34, count 0 2006.175.08:05:58.01#ibcon#read 3, iclass 34, count 0 2006.175.08:05:58.01#ibcon#about to read 4, iclass 34, count 0 2006.175.08:05:58.01#ibcon#read 4, iclass 34, count 0 2006.175.08:05:58.01#ibcon#about to read 5, iclass 34, count 0 2006.175.08:05:58.01#ibcon#read 5, iclass 34, count 0 2006.175.08:05:58.01#ibcon#about to read 6, iclass 34, count 0 2006.175.08:05:58.01#ibcon#read 6, iclass 34, count 0 2006.175.08:05:58.01#ibcon#end of sib2, iclass 34, count 0 2006.175.08:05:58.01#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:05:58.01#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:05:58.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:05:58.01#ibcon#*before write, iclass 34, count 0 2006.175.08:05:58.01#ibcon#enter sib2, iclass 34, count 0 2006.175.08:05:58.01#ibcon#flushed, iclass 34, count 0 2006.175.08:05:58.01#ibcon#about to write, iclass 34, count 0 2006.175.08:05:58.01#ibcon#wrote, iclass 34, count 0 2006.175.08:05:58.01#ibcon#about to read 3, iclass 34, count 0 2006.175.08:05:58.05#ibcon#read 3, iclass 34, count 0 2006.175.08:05:58.05#ibcon#about to read 4, iclass 34, count 0 2006.175.08:05:58.05#ibcon#read 4, iclass 34, count 0 2006.175.08:05:58.05#ibcon#about to read 5, iclass 34, count 0 2006.175.08:05:58.05#ibcon#read 5, iclass 34, count 0 2006.175.08:05:58.05#ibcon#about to read 6, iclass 34, count 0 2006.175.08:05:58.05#ibcon#read 6, iclass 34, count 0 2006.175.08:05:58.05#ibcon#end of sib2, iclass 34, count 0 2006.175.08:05:58.05#ibcon#*after write, iclass 34, count 0 2006.175.08:05:58.05#ibcon#*before return 0, iclass 34, count 0 2006.175.08:05:58.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:05:58.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:05:58.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:05:58.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:05:58.05$vc4f8/va=1,8 2006.175.08:05:58.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.08:05:58.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.08:05:58.05#ibcon#ireg 11 cls_cnt 2 2006.175.08:05:58.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:05:58.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:05:58.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:05:58.05#ibcon#enter wrdev, iclass 36, count 2 2006.175.08:05:58.05#ibcon#first serial, iclass 36, count 2 2006.175.08:05:58.05#ibcon#enter sib2, iclass 36, count 2 2006.175.08:05:58.05#ibcon#flushed, iclass 36, count 2 2006.175.08:05:58.05#ibcon#about to write, iclass 36, count 2 2006.175.08:05:58.05#ibcon#wrote, iclass 36, count 2 2006.175.08:05:58.05#ibcon#about to read 3, iclass 36, count 2 2006.175.08:05:58.07#ibcon#read 3, iclass 36, count 2 2006.175.08:05:58.07#ibcon#about to read 4, iclass 36, count 2 2006.175.08:05:58.07#ibcon#read 4, iclass 36, count 2 2006.175.08:05:58.07#ibcon#about to read 5, iclass 36, count 2 2006.175.08:05:58.07#ibcon#read 5, iclass 36, count 2 2006.175.08:05:58.07#ibcon#about to read 6, iclass 36, count 2 2006.175.08:05:58.07#ibcon#read 6, iclass 36, count 2 2006.175.08:05:58.07#ibcon#end of sib2, iclass 36, count 2 2006.175.08:05:58.07#ibcon#*mode == 0, iclass 36, count 2 2006.175.08:05:58.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.08:05:58.07#ibcon#[25=AT01-08\r\n] 2006.175.08:05:58.07#ibcon#*before write, iclass 36, count 2 2006.175.08:05:58.07#ibcon#enter sib2, iclass 36, count 2 2006.175.08:05:58.07#ibcon#flushed, iclass 36, count 2 2006.175.08:05:58.07#ibcon#about to write, iclass 36, count 2 2006.175.08:05:58.07#ibcon#wrote, iclass 36, count 2 2006.175.08:05:58.07#ibcon#about to read 3, iclass 36, count 2 2006.175.08:05:58.10#ibcon#read 3, iclass 36, count 2 2006.175.08:05:58.10#ibcon#about to read 4, iclass 36, count 2 2006.175.08:05:58.10#ibcon#read 4, iclass 36, count 2 2006.175.08:05:58.10#ibcon#about to read 5, iclass 36, count 2 2006.175.08:05:58.10#ibcon#read 5, iclass 36, count 2 2006.175.08:05:58.10#ibcon#about to read 6, iclass 36, count 2 2006.175.08:05:58.10#ibcon#read 6, iclass 36, count 2 2006.175.08:05:58.10#ibcon#end of sib2, iclass 36, count 2 2006.175.08:05:58.10#ibcon#*after write, iclass 36, count 2 2006.175.08:05:58.10#ibcon#*before return 0, iclass 36, count 2 2006.175.08:05:58.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:05:58.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:05:58.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.08:05:58.10#ibcon#ireg 7 cls_cnt 0 2006.175.08:05:58.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:05:58.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:05:58.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:05:58.22#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:05:58.22#ibcon#first serial, iclass 36, count 0 2006.175.08:05:58.22#ibcon#enter sib2, iclass 36, count 0 2006.175.08:05:58.22#ibcon#flushed, iclass 36, count 0 2006.175.08:05:58.22#ibcon#about to write, iclass 36, count 0 2006.175.08:05:58.22#ibcon#wrote, iclass 36, count 0 2006.175.08:05:58.22#ibcon#about to read 3, iclass 36, count 0 2006.175.08:05:58.24#ibcon#read 3, iclass 36, count 0 2006.175.08:05:58.24#ibcon#about to read 4, iclass 36, count 0 2006.175.08:05:58.24#ibcon#read 4, iclass 36, count 0 2006.175.08:05:58.24#ibcon#about to read 5, iclass 36, count 0 2006.175.08:05:58.24#ibcon#read 5, iclass 36, count 0 2006.175.08:05:58.24#ibcon#about to read 6, iclass 36, count 0 2006.175.08:05:58.24#ibcon#read 6, iclass 36, count 0 2006.175.08:05:58.24#ibcon#end of sib2, iclass 36, count 0 2006.175.08:05:58.24#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:05:58.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:05:58.24#ibcon#[25=USB\r\n] 2006.175.08:05:58.24#ibcon#*before write, iclass 36, count 0 2006.175.08:05:58.24#ibcon#enter sib2, iclass 36, count 0 2006.175.08:05:58.24#ibcon#flushed, iclass 36, count 0 2006.175.08:05:58.24#ibcon#about to write, iclass 36, count 0 2006.175.08:05:58.24#ibcon#wrote, iclass 36, count 0 2006.175.08:05:58.24#ibcon#about to read 3, iclass 36, count 0 2006.175.08:05:58.27#ibcon#read 3, iclass 36, count 0 2006.175.08:05:58.27#ibcon#about to read 4, iclass 36, count 0 2006.175.08:05:58.27#ibcon#read 4, iclass 36, count 0 2006.175.08:05:58.27#ibcon#about to read 5, iclass 36, count 0 2006.175.08:05:58.27#ibcon#read 5, iclass 36, count 0 2006.175.08:05:58.27#ibcon#about to read 6, iclass 36, count 0 2006.175.08:05:58.27#ibcon#read 6, iclass 36, count 0 2006.175.08:05:58.27#ibcon#end of sib2, iclass 36, count 0 2006.175.08:05:58.27#ibcon#*after write, iclass 36, count 0 2006.175.08:05:58.27#ibcon#*before return 0, iclass 36, count 0 2006.175.08:05:58.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:05:58.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:05:58.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:05:58.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:05:58.27$vc4f8/valo=2,572.99 2006.175.08:05:58.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.08:05:58.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.08:05:58.27#ibcon#ireg 17 cls_cnt 0 2006.175.08:05:58.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:05:58.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:05:58.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:05:58.27#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:05:58.27#ibcon#first serial, iclass 38, count 0 2006.175.08:05:58.27#ibcon#enter sib2, iclass 38, count 0 2006.175.08:05:58.27#ibcon#flushed, iclass 38, count 0 2006.175.08:05:58.27#ibcon#about to write, iclass 38, count 0 2006.175.08:05:58.27#ibcon#wrote, iclass 38, count 0 2006.175.08:05:58.27#ibcon#about to read 3, iclass 38, count 0 2006.175.08:05:58.29#ibcon#read 3, iclass 38, count 0 2006.175.08:05:58.29#ibcon#about to read 4, iclass 38, count 0 2006.175.08:05:58.29#ibcon#read 4, iclass 38, count 0 2006.175.08:05:58.29#ibcon#about to read 5, iclass 38, count 0 2006.175.08:05:58.29#ibcon#read 5, iclass 38, count 0 2006.175.08:05:58.29#ibcon#about to read 6, iclass 38, count 0 2006.175.08:05:58.29#ibcon#read 6, iclass 38, count 0 2006.175.08:05:58.29#ibcon#end of sib2, iclass 38, count 0 2006.175.08:05:58.29#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:05:58.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:05:58.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:05:58.29#ibcon#*before write, iclass 38, count 0 2006.175.08:05:58.29#ibcon#enter sib2, iclass 38, count 0 2006.175.08:05:58.29#ibcon#flushed, iclass 38, count 0 2006.175.08:05:58.29#ibcon#about to write, iclass 38, count 0 2006.175.08:05:58.29#ibcon#wrote, iclass 38, count 0 2006.175.08:05:58.29#ibcon#about to read 3, iclass 38, count 0 2006.175.08:05:58.33#ibcon#read 3, iclass 38, count 0 2006.175.08:05:58.33#ibcon#about to read 4, iclass 38, count 0 2006.175.08:05:58.33#ibcon#read 4, iclass 38, count 0 2006.175.08:05:58.33#ibcon#about to read 5, iclass 38, count 0 2006.175.08:05:58.33#ibcon#read 5, iclass 38, count 0 2006.175.08:05:58.33#ibcon#about to read 6, iclass 38, count 0 2006.175.08:05:58.33#ibcon#read 6, iclass 38, count 0 2006.175.08:05:58.33#ibcon#end of sib2, iclass 38, count 0 2006.175.08:05:58.33#ibcon#*after write, iclass 38, count 0 2006.175.08:05:58.33#ibcon#*before return 0, iclass 38, count 0 2006.175.08:05:58.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:05:58.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:05:58.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:05:58.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:05:58.33$vc4f8/va=2,7 2006.175.08:05:58.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.08:05:58.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.08:05:58.33#ibcon#ireg 11 cls_cnt 2 2006.175.08:05:58.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:05:58.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:05:58.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:05:58.39#ibcon#enter wrdev, iclass 40, count 2 2006.175.08:05:58.39#ibcon#first serial, iclass 40, count 2 2006.175.08:05:58.39#ibcon#enter sib2, iclass 40, count 2 2006.175.08:05:58.39#ibcon#flushed, iclass 40, count 2 2006.175.08:05:58.39#ibcon#about to write, iclass 40, count 2 2006.175.08:05:58.39#ibcon#wrote, iclass 40, count 2 2006.175.08:05:58.39#ibcon#about to read 3, iclass 40, count 2 2006.175.08:05:58.41#ibcon#read 3, iclass 40, count 2 2006.175.08:05:58.41#ibcon#about to read 4, iclass 40, count 2 2006.175.08:05:58.41#ibcon#read 4, iclass 40, count 2 2006.175.08:05:58.41#ibcon#about to read 5, iclass 40, count 2 2006.175.08:05:58.41#ibcon#read 5, iclass 40, count 2 2006.175.08:05:58.41#ibcon#about to read 6, iclass 40, count 2 2006.175.08:05:58.41#ibcon#read 6, iclass 40, count 2 2006.175.08:05:58.42#ibcon#end of sib2, iclass 40, count 2 2006.175.08:05:58.42#ibcon#*mode == 0, iclass 40, count 2 2006.175.08:05:58.42#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.08:05:58.42#ibcon#[25=AT02-07\r\n] 2006.175.08:05:58.42#ibcon#*before write, iclass 40, count 2 2006.175.08:05:58.42#ibcon#enter sib2, iclass 40, count 2 2006.175.08:05:58.42#ibcon#flushed, iclass 40, count 2 2006.175.08:05:58.42#ibcon#about to write, iclass 40, count 2 2006.175.08:05:58.42#ibcon#wrote, iclass 40, count 2 2006.175.08:05:58.42#ibcon#about to read 3, iclass 40, count 2 2006.175.08:05:58.44#ibcon#read 3, iclass 40, count 2 2006.175.08:05:58.44#ibcon#about to read 4, iclass 40, count 2 2006.175.08:05:58.44#ibcon#read 4, iclass 40, count 2 2006.175.08:05:58.44#ibcon#about to read 5, iclass 40, count 2 2006.175.08:05:58.44#ibcon#read 5, iclass 40, count 2 2006.175.08:05:58.44#ibcon#about to read 6, iclass 40, count 2 2006.175.08:05:58.44#ibcon#read 6, iclass 40, count 2 2006.175.08:05:58.44#ibcon#end of sib2, iclass 40, count 2 2006.175.08:05:58.44#ibcon#*after write, iclass 40, count 2 2006.175.08:05:58.44#ibcon#*before return 0, iclass 40, count 2 2006.175.08:05:58.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:05:58.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:05:58.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.08:05:58.44#ibcon#ireg 7 cls_cnt 0 2006.175.08:05:58.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:05:58.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:05:58.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:05:58.56#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:05:58.56#ibcon#first serial, iclass 40, count 0 2006.175.08:05:58.56#ibcon#enter sib2, iclass 40, count 0 2006.175.08:05:58.56#ibcon#flushed, iclass 40, count 0 2006.175.08:05:58.56#ibcon#about to write, iclass 40, count 0 2006.175.08:05:58.56#ibcon#wrote, iclass 40, count 0 2006.175.08:05:58.56#ibcon#about to read 3, iclass 40, count 0 2006.175.08:05:58.58#ibcon#read 3, iclass 40, count 0 2006.175.08:05:58.58#ibcon#about to read 4, iclass 40, count 0 2006.175.08:05:58.58#ibcon#read 4, iclass 40, count 0 2006.175.08:05:58.58#ibcon#about to read 5, iclass 40, count 0 2006.175.08:05:58.58#ibcon#read 5, iclass 40, count 0 2006.175.08:05:58.58#ibcon#about to read 6, iclass 40, count 0 2006.175.08:05:58.58#ibcon#read 6, iclass 40, count 0 2006.175.08:05:58.58#ibcon#end of sib2, iclass 40, count 0 2006.175.08:05:58.58#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:05:58.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:05:58.58#ibcon#[25=USB\r\n] 2006.175.08:05:58.58#ibcon#*before write, iclass 40, count 0 2006.175.08:05:58.58#ibcon#enter sib2, iclass 40, count 0 2006.175.08:05:58.58#ibcon#flushed, iclass 40, count 0 2006.175.08:05:58.58#ibcon#about to write, iclass 40, count 0 2006.175.08:05:58.58#ibcon#wrote, iclass 40, count 0 2006.175.08:05:58.58#ibcon#about to read 3, iclass 40, count 0 2006.175.08:05:58.61#ibcon#read 3, iclass 40, count 0 2006.175.08:05:58.61#ibcon#about to read 4, iclass 40, count 0 2006.175.08:05:58.61#ibcon#read 4, iclass 40, count 0 2006.175.08:05:58.61#ibcon#about to read 5, iclass 40, count 0 2006.175.08:05:58.61#ibcon#read 5, iclass 40, count 0 2006.175.08:05:58.61#ibcon#about to read 6, iclass 40, count 0 2006.175.08:05:58.61#ibcon#read 6, iclass 40, count 0 2006.175.08:05:58.61#ibcon#end of sib2, iclass 40, count 0 2006.175.08:05:58.61#ibcon#*after write, iclass 40, count 0 2006.175.08:05:58.61#ibcon#*before return 0, iclass 40, count 0 2006.175.08:05:58.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:05:58.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:05:58.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:05:58.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:05:58.61$vc4f8/valo=3,672.99 2006.175.08:05:58.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.08:05:58.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.08:05:58.61#ibcon#ireg 17 cls_cnt 0 2006.175.08:05:58.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:05:58.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:05:58.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:05:58.61#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:05:58.61#ibcon#first serial, iclass 4, count 0 2006.175.08:05:58.61#ibcon#enter sib2, iclass 4, count 0 2006.175.08:05:58.61#ibcon#flushed, iclass 4, count 0 2006.175.08:05:58.61#ibcon#about to write, iclass 4, count 0 2006.175.08:05:58.61#ibcon#wrote, iclass 4, count 0 2006.175.08:05:58.61#ibcon#about to read 3, iclass 4, count 0 2006.175.08:05:58.63#ibcon#read 3, iclass 4, count 0 2006.175.08:05:58.63#ibcon#about to read 4, iclass 4, count 0 2006.175.08:05:58.63#ibcon#read 4, iclass 4, count 0 2006.175.08:05:58.63#ibcon#about to read 5, iclass 4, count 0 2006.175.08:05:58.63#ibcon#read 5, iclass 4, count 0 2006.175.08:05:58.63#ibcon#about to read 6, iclass 4, count 0 2006.175.08:05:58.63#ibcon#read 6, iclass 4, count 0 2006.175.08:05:58.63#ibcon#end of sib2, iclass 4, count 0 2006.175.08:05:58.63#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:05:58.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:05:58.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:05:58.63#ibcon#*before write, iclass 4, count 0 2006.175.08:05:58.63#ibcon#enter sib2, iclass 4, count 0 2006.175.08:05:58.63#ibcon#flushed, iclass 4, count 0 2006.175.08:05:58.63#ibcon#about to write, iclass 4, count 0 2006.175.08:05:58.63#ibcon#wrote, iclass 4, count 0 2006.175.08:05:58.63#ibcon#about to read 3, iclass 4, count 0 2006.175.08:05:58.67#ibcon#read 3, iclass 4, count 0 2006.175.08:05:58.67#ibcon#about to read 4, iclass 4, count 0 2006.175.08:05:58.67#ibcon#read 4, iclass 4, count 0 2006.175.08:05:58.67#ibcon#about to read 5, iclass 4, count 0 2006.175.08:05:58.67#ibcon#read 5, iclass 4, count 0 2006.175.08:05:58.67#ibcon#about to read 6, iclass 4, count 0 2006.175.08:05:58.67#ibcon#read 6, iclass 4, count 0 2006.175.08:05:58.67#ibcon#end of sib2, iclass 4, count 0 2006.175.08:05:58.67#ibcon#*after write, iclass 4, count 0 2006.175.08:05:58.67#ibcon#*before return 0, iclass 4, count 0 2006.175.08:05:58.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:05:58.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:05:58.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:05:58.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:05:58.67$vc4f8/va=3,6 2006.175.08:05:58.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.08:05:58.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.08:05:58.67#ibcon#ireg 11 cls_cnt 2 2006.175.08:05:58.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:05:58.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:05:58.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:05:58.73#ibcon#enter wrdev, iclass 6, count 2 2006.175.08:05:58.73#ibcon#first serial, iclass 6, count 2 2006.175.08:05:58.73#ibcon#enter sib2, iclass 6, count 2 2006.175.08:05:58.73#ibcon#flushed, iclass 6, count 2 2006.175.08:05:58.73#ibcon#about to write, iclass 6, count 2 2006.175.08:05:58.73#ibcon#wrote, iclass 6, count 2 2006.175.08:05:58.73#ibcon#about to read 3, iclass 6, count 2 2006.175.08:05:58.75#ibcon#read 3, iclass 6, count 2 2006.175.08:05:58.75#ibcon#about to read 4, iclass 6, count 2 2006.175.08:05:58.75#ibcon#read 4, iclass 6, count 2 2006.175.08:05:58.75#ibcon#about to read 5, iclass 6, count 2 2006.175.08:05:58.75#ibcon#read 5, iclass 6, count 2 2006.175.08:05:58.75#ibcon#about to read 6, iclass 6, count 2 2006.175.08:05:58.75#ibcon#read 6, iclass 6, count 2 2006.175.08:05:58.75#ibcon#end of sib2, iclass 6, count 2 2006.175.08:05:58.76#ibcon#*mode == 0, iclass 6, count 2 2006.175.08:05:58.76#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.08:05:58.76#ibcon#[25=AT03-06\r\n] 2006.175.08:05:58.76#ibcon#*before write, iclass 6, count 2 2006.175.08:05:58.76#ibcon#enter sib2, iclass 6, count 2 2006.175.08:05:58.76#ibcon#flushed, iclass 6, count 2 2006.175.08:05:58.76#ibcon#about to write, iclass 6, count 2 2006.175.08:05:58.76#ibcon#wrote, iclass 6, count 2 2006.175.08:05:58.76#ibcon#about to read 3, iclass 6, count 2 2006.175.08:05:58.78#ibcon#read 3, iclass 6, count 2 2006.175.08:05:58.78#ibcon#about to read 4, iclass 6, count 2 2006.175.08:05:58.78#ibcon#read 4, iclass 6, count 2 2006.175.08:05:58.78#ibcon#about to read 5, iclass 6, count 2 2006.175.08:05:58.78#ibcon#read 5, iclass 6, count 2 2006.175.08:05:58.78#ibcon#about to read 6, iclass 6, count 2 2006.175.08:05:58.78#ibcon#read 6, iclass 6, count 2 2006.175.08:05:58.78#ibcon#end of sib2, iclass 6, count 2 2006.175.08:05:58.78#ibcon#*after write, iclass 6, count 2 2006.175.08:05:58.78#ibcon#*before return 0, iclass 6, count 2 2006.175.08:05:58.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:05:58.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:05:58.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.08:05:58.78#ibcon#ireg 7 cls_cnt 0 2006.175.08:05:58.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:05:58.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:05:58.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:05:58.90#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:05:58.90#ibcon#first serial, iclass 6, count 0 2006.175.08:05:58.90#ibcon#enter sib2, iclass 6, count 0 2006.175.08:05:58.90#ibcon#flushed, iclass 6, count 0 2006.175.08:05:58.90#ibcon#about to write, iclass 6, count 0 2006.175.08:05:58.90#ibcon#wrote, iclass 6, count 0 2006.175.08:05:58.90#ibcon#about to read 3, iclass 6, count 0 2006.175.08:05:58.92#ibcon#read 3, iclass 6, count 0 2006.175.08:05:58.92#ibcon#about to read 4, iclass 6, count 0 2006.175.08:05:58.92#ibcon#read 4, iclass 6, count 0 2006.175.08:05:58.92#ibcon#about to read 5, iclass 6, count 0 2006.175.08:05:58.92#ibcon#read 5, iclass 6, count 0 2006.175.08:05:58.92#ibcon#about to read 6, iclass 6, count 0 2006.175.08:05:58.92#ibcon#read 6, iclass 6, count 0 2006.175.08:05:58.92#ibcon#end of sib2, iclass 6, count 0 2006.175.08:05:58.92#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:05:58.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:05:58.92#ibcon#[25=USB\r\n] 2006.175.08:05:58.92#ibcon#*before write, iclass 6, count 0 2006.175.08:05:58.92#ibcon#enter sib2, iclass 6, count 0 2006.175.08:05:58.92#ibcon#flushed, iclass 6, count 0 2006.175.08:05:58.92#ibcon#about to write, iclass 6, count 0 2006.175.08:05:58.92#ibcon#wrote, iclass 6, count 0 2006.175.08:05:58.92#ibcon#about to read 3, iclass 6, count 0 2006.175.08:05:58.95#ibcon#read 3, iclass 6, count 0 2006.175.08:05:58.95#ibcon#about to read 4, iclass 6, count 0 2006.175.08:05:58.95#ibcon#read 4, iclass 6, count 0 2006.175.08:05:58.95#ibcon#about to read 5, iclass 6, count 0 2006.175.08:05:58.95#ibcon#read 5, iclass 6, count 0 2006.175.08:05:58.95#ibcon#about to read 6, iclass 6, count 0 2006.175.08:05:58.95#ibcon#read 6, iclass 6, count 0 2006.175.08:05:58.95#ibcon#end of sib2, iclass 6, count 0 2006.175.08:05:58.95#ibcon#*after write, iclass 6, count 0 2006.175.08:05:58.95#ibcon#*before return 0, iclass 6, count 0 2006.175.08:05:58.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:05:58.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:05:58.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:05:58.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:05:58.95$vc4f8/valo=4,832.99 2006.175.08:05:58.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.08:05:58.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.08:05:58.95#ibcon#ireg 17 cls_cnt 0 2006.175.08:05:58.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:05:58.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:05:58.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:05:58.95#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:05:58.95#ibcon#first serial, iclass 10, count 0 2006.175.08:05:58.95#ibcon#enter sib2, iclass 10, count 0 2006.175.08:05:58.95#ibcon#flushed, iclass 10, count 0 2006.175.08:05:58.95#ibcon#about to write, iclass 10, count 0 2006.175.08:05:58.95#ibcon#wrote, iclass 10, count 0 2006.175.08:05:58.95#ibcon#about to read 3, iclass 10, count 0 2006.175.08:05:58.97#ibcon#read 3, iclass 10, count 0 2006.175.08:05:58.97#ibcon#about to read 4, iclass 10, count 0 2006.175.08:05:58.97#ibcon#read 4, iclass 10, count 0 2006.175.08:05:58.97#ibcon#about to read 5, iclass 10, count 0 2006.175.08:05:58.97#ibcon#read 5, iclass 10, count 0 2006.175.08:05:58.97#ibcon#about to read 6, iclass 10, count 0 2006.175.08:05:58.97#ibcon#read 6, iclass 10, count 0 2006.175.08:05:58.97#ibcon#end of sib2, iclass 10, count 0 2006.175.08:05:58.97#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:05:58.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:05:58.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:05:58.97#ibcon#*before write, iclass 10, count 0 2006.175.08:05:58.97#ibcon#enter sib2, iclass 10, count 0 2006.175.08:05:58.97#ibcon#flushed, iclass 10, count 0 2006.175.08:05:58.97#ibcon#about to write, iclass 10, count 0 2006.175.08:05:58.97#ibcon#wrote, iclass 10, count 0 2006.175.08:05:58.97#ibcon#about to read 3, iclass 10, count 0 2006.175.08:05:59.01#ibcon#read 3, iclass 10, count 0 2006.175.08:05:59.01#ibcon#about to read 4, iclass 10, count 0 2006.175.08:05:59.01#ibcon#read 4, iclass 10, count 0 2006.175.08:05:59.01#ibcon#about to read 5, iclass 10, count 0 2006.175.08:05:59.01#ibcon#read 5, iclass 10, count 0 2006.175.08:05:59.01#ibcon#about to read 6, iclass 10, count 0 2006.175.08:05:59.01#ibcon#read 6, iclass 10, count 0 2006.175.08:05:59.01#ibcon#end of sib2, iclass 10, count 0 2006.175.08:05:59.01#ibcon#*after write, iclass 10, count 0 2006.175.08:05:59.01#ibcon#*before return 0, iclass 10, count 0 2006.175.08:05:59.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:05:59.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:05:59.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:05:59.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:05:59.01$vc4f8/va=4,7 2006.175.08:05:59.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.08:05:59.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.08:05:59.01#ibcon#ireg 11 cls_cnt 2 2006.175.08:05:59.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:05:59.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:05:59.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:05:59.07#ibcon#enter wrdev, iclass 12, count 2 2006.175.08:05:59.07#ibcon#first serial, iclass 12, count 2 2006.175.08:05:59.07#ibcon#enter sib2, iclass 12, count 2 2006.175.08:05:59.07#ibcon#flushed, iclass 12, count 2 2006.175.08:05:59.07#ibcon#about to write, iclass 12, count 2 2006.175.08:05:59.07#ibcon#wrote, iclass 12, count 2 2006.175.08:05:59.07#ibcon#about to read 3, iclass 12, count 2 2006.175.08:05:59.09#ibcon#read 3, iclass 12, count 2 2006.175.08:05:59.09#ibcon#about to read 4, iclass 12, count 2 2006.175.08:05:59.09#ibcon#read 4, iclass 12, count 2 2006.175.08:05:59.09#ibcon#about to read 5, iclass 12, count 2 2006.175.08:05:59.09#ibcon#read 5, iclass 12, count 2 2006.175.08:05:59.09#ibcon#about to read 6, iclass 12, count 2 2006.175.08:05:59.09#ibcon#read 6, iclass 12, count 2 2006.175.08:05:59.09#ibcon#end of sib2, iclass 12, count 2 2006.175.08:05:59.09#ibcon#*mode == 0, iclass 12, count 2 2006.175.08:05:59.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.08:05:59.09#ibcon#[25=AT04-07\r\n] 2006.175.08:05:59.09#ibcon#*before write, iclass 12, count 2 2006.175.08:05:59.09#ibcon#enter sib2, iclass 12, count 2 2006.175.08:05:59.09#ibcon#flushed, iclass 12, count 2 2006.175.08:05:59.09#ibcon#about to write, iclass 12, count 2 2006.175.08:05:59.09#ibcon#wrote, iclass 12, count 2 2006.175.08:05:59.09#ibcon#about to read 3, iclass 12, count 2 2006.175.08:05:59.12#ibcon#read 3, iclass 12, count 2 2006.175.08:05:59.12#ibcon#about to read 4, iclass 12, count 2 2006.175.08:05:59.12#ibcon#read 4, iclass 12, count 2 2006.175.08:05:59.12#ibcon#about to read 5, iclass 12, count 2 2006.175.08:05:59.12#ibcon#read 5, iclass 12, count 2 2006.175.08:05:59.12#ibcon#about to read 6, iclass 12, count 2 2006.175.08:05:59.12#ibcon#read 6, iclass 12, count 2 2006.175.08:05:59.12#ibcon#end of sib2, iclass 12, count 2 2006.175.08:05:59.12#ibcon#*after write, iclass 12, count 2 2006.175.08:05:59.12#ibcon#*before return 0, iclass 12, count 2 2006.175.08:05:59.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:05:59.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:05:59.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.08:05:59.12#ibcon#ireg 7 cls_cnt 0 2006.175.08:05:59.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:05:59.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:05:59.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:05:59.24#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:05:59.24#ibcon#first serial, iclass 12, count 0 2006.175.08:05:59.24#ibcon#enter sib2, iclass 12, count 0 2006.175.08:05:59.24#ibcon#flushed, iclass 12, count 0 2006.175.08:05:59.24#ibcon#about to write, iclass 12, count 0 2006.175.08:05:59.24#ibcon#wrote, iclass 12, count 0 2006.175.08:05:59.24#ibcon#about to read 3, iclass 12, count 0 2006.175.08:05:59.26#ibcon#read 3, iclass 12, count 0 2006.175.08:05:59.26#ibcon#about to read 4, iclass 12, count 0 2006.175.08:05:59.26#ibcon#read 4, iclass 12, count 0 2006.175.08:05:59.26#ibcon#about to read 5, iclass 12, count 0 2006.175.08:05:59.26#ibcon#read 5, iclass 12, count 0 2006.175.08:05:59.26#ibcon#about to read 6, iclass 12, count 0 2006.175.08:05:59.26#ibcon#read 6, iclass 12, count 0 2006.175.08:05:59.26#ibcon#end of sib2, iclass 12, count 0 2006.175.08:05:59.26#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:05:59.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:05:59.26#ibcon#[25=USB\r\n] 2006.175.08:05:59.26#ibcon#*before write, iclass 12, count 0 2006.175.08:05:59.26#ibcon#enter sib2, iclass 12, count 0 2006.175.08:05:59.26#ibcon#flushed, iclass 12, count 0 2006.175.08:05:59.26#ibcon#about to write, iclass 12, count 0 2006.175.08:05:59.26#ibcon#wrote, iclass 12, count 0 2006.175.08:05:59.26#ibcon#about to read 3, iclass 12, count 0 2006.175.08:05:59.29#ibcon#read 3, iclass 12, count 0 2006.175.08:05:59.29#ibcon#about to read 4, iclass 12, count 0 2006.175.08:05:59.29#ibcon#read 4, iclass 12, count 0 2006.175.08:05:59.29#ibcon#about to read 5, iclass 12, count 0 2006.175.08:05:59.29#ibcon#read 5, iclass 12, count 0 2006.175.08:05:59.29#ibcon#about to read 6, iclass 12, count 0 2006.175.08:05:59.29#ibcon#read 6, iclass 12, count 0 2006.175.08:05:59.29#ibcon#end of sib2, iclass 12, count 0 2006.175.08:05:59.29#ibcon#*after write, iclass 12, count 0 2006.175.08:05:59.29#ibcon#*before return 0, iclass 12, count 0 2006.175.08:05:59.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:05:59.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:05:59.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:05:59.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:05:59.29$vc4f8/valo=5,652.99 2006.175.08:05:59.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.08:05:59.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.08:05:59.29#ibcon#ireg 17 cls_cnt 0 2006.175.08:05:59.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:05:59.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:05:59.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:05:59.29#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:05:59.29#ibcon#first serial, iclass 14, count 0 2006.175.08:05:59.29#ibcon#enter sib2, iclass 14, count 0 2006.175.08:05:59.29#ibcon#flushed, iclass 14, count 0 2006.175.08:05:59.29#ibcon#about to write, iclass 14, count 0 2006.175.08:05:59.29#ibcon#wrote, iclass 14, count 0 2006.175.08:05:59.29#ibcon#about to read 3, iclass 14, count 0 2006.175.08:05:59.31#ibcon#read 3, iclass 14, count 0 2006.175.08:05:59.31#ibcon#about to read 4, iclass 14, count 0 2006.175.08:05:59.31#ibcon#read 4, iclass 14, count 0 2006.175.08:05:59.31#ibcon#about to read 5, iclass 14, count 0 2006.175.08:05:59.31#ibcon#read 5, iclass 14, count 0 2006.175.08:05:59.31#ibcon#about to read 6, iclass 14, count 0 2006.175.08:05:59.31#ibcon#read 6, iclass 14, count 0 2006.175.08:05:59.31#ibcon#end of sib2, iclass 14, count 0 2006.175.08:05:59.31#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:05:59.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:05:59.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:05:59.31#ibcon#*before write, iclass 14, count 0 2006.175.08:05:59.31#ibcon#enter sib2, iclass 14, count 0 2006.175.08:05:59.31#ibcon#flushed, iclass 14, count 0 2006.175.08:05:59.31#ibcon#about to write, iclass 14, count 0 2006.175.08:05:59.31#ibcon#wrote, iclass 14, count 0 2006.175.08:05:59.31#ibcon#about to read 3, iclass 14, count 0 2006.175.08:05:59.35#ibcon#read 3, iclass 14, count 0 2006.175.08:05:59.35#ibcon#about to read 4, iclass 14, count 0 2006.175.08:05:59.35#ibcon#read 4, iclass 14, count 0 2006.175.08:05:59.35#ibcon#about to read 5, iclass 14, count 0 2006.175.08:05:59.35#ibcon#read 5, iclass 14, count 0 2006.175.08:05:59.35#ibcon#about to read 6, iclass 14, count 0 2006.175.08:05:59.35#ibcon#read 6, iclass 14, count 0 2006.175.08:05:59.35#ibcon#end of sib2, iclass 14, count 0 2006.175.08:05:59.35#ibcon#*after write, iclass 14, count 0 2006.175.08:05:59.35#ibcon#*before return 0, iclass 14, count 0 2006.175.08:05:59.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:05:59.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:05:59.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:05:59.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:05:59.35$vc4f8/va=5,7 2006.175.08:05:59.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.08:05:59.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.08:05:59.35#ibcon#ireg 11 cls_cnt 2 2006.175.08:05:59.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:05:59.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:05:59.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:05:59.41#ibcon#enter wrdev, iclass 16, count 2 2006.175.08:05:59.41#ibcon#first serial, iclass 16, count 2 2006.175.08:05:59.41#ibcon#enter sib2, iclass 16, count 2 2006.175.08:05:59.41#ibcon#flushed, iclass 16, count 2 2006.175.08:05:59.41#ibcon#about to write, iclass 16, count 2 2006.175.08:05:59.41#ibcon#wrote, iclass 16, count 2 2006.175.08:05:59.41#ibcon#about to read 3, iclass 16, count 2 2006.175.08:05:59.43#ibcon#read 3, iclass 16, count 2 2006.175.08:05:59.43#ibcon#about to read 4, iclass 16, count 2 2006.175.08:05:59.43#ibcon#read 4, iclass 16, count 2 2006.175.08:05:59.43#ibcon#about to read 5, iclass 16, count 2 2006.175.08:05:59.43#ibcon#read 5, iclass 16, count 2 2006.175.08:05:59.43#ibcon#about to read 6, iclass 16, count 2 2006.175.08:05:59.44#ibcon#read 6, iclass 16, count 2 2006.175.08:05:59.44#ibcon#end of sib2, iclass 16, count 2 2006.175.08:05:59.44#ibcon#*mode == 0, iclass 16, count 2 2006.175.08:05:59.44#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.08:05:59.44#ibcon#[25=AT05-07\r\n] 2006.175.08:05:59.44#ibcon#*before write, iclass 16, count 2 2006.175.08:05:59.44#ibcon#enter sib2, iclass 16, count 2 2006.175.08:05:59.44#ibcon#flushed, iclass 16, count 2 2006.175.08:05:59.44#ibcon#about to write, iclass 16, count 2 2006.175.08:05:59.44#ibcon#wrote, iclass 16, count 2 2006.175.08:05:59.44#ibcon#about to read 3, iclass 16, count 2 2006.175.08:05:59.46#ibcon#read 3, iclass 16, count 2 2006.175.08:05:59.46#ibcon#about to read 4, iclass 16, count 2 2006.175.08:05:59.46#ibcon#read 4, iclass 16, count 2 2006.175.08:05:59.46#ibcon#about to read 5, iclass 16, count 2 2006.175.08:05:59.46#ibcon#read 5, iclass 16, count 2 2006.175.08:05:59.46#ibcon#about to read 6, iclass 16, count 2 2006.175.08:05:59.46#ibcon#read 6, iclass 16, count 2 2006.175.08:05:59.46#ibcon#end of sib2, iclass 16, count 2 2006.175.08:05:59.46#ibcon#*after write, iclass 16, count 2 2006.175.08:05:59.46#ibcon#*before return 0, iclass 16, count 2 2006.175.08:05:59.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:05:59.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:05:59.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.08:05:59.46#ibcon#ireg 7 cls_cnt 0 2006.175.08:05:59.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:05:59.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:05:59.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:05:59.58#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:05:59.58#ibcon#first serial, iclass 16, count 0 2006.175.08:05:59.58#ibcon#enter sib2, iclass 16, count 0 2006.175.08:05:59.58#ibcon#flushed, iclass 16, count 0 2006.175.08:05:59.58#ibcon#about to write, iclass 16, count 0 2006.175.08:05:59.58#ibcon#wrote, iclass 16, count 0 2006.175.08:05:59.58#ibcon#about to read 3, iclass 16, count 0 2006.175.08:05:59.60#ibcon#read 3, iclass 16, count 0 2006.175.08:05:59.60#ibcon#about to read 4, iclass 16, count 0 2006.175.08:05:59.60#ibcon#read 4, iclass 16, count 0 2006.175.08:05:59.60#ibcon#about to read 5, iclass 16, count 0 2006.175.08:05:59.60#ibcon#read 5, iclass 16, count 0 2006.175.08:05:59.60#ibcon#about to read 6, iclass 16, count 0 2006.175.08:05:59.60#ibcon#read 6, iclass 16, count 0 2006.175.08:05:59.60#ibcon#end of sib2, iclass 16, count 0 2006.175.08:05:59.60#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:05:59.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:05:59.60#ibcon#[25=USB\r\n] 2006.175.08:05:59.60#ibcon#*before write, iclass 16, count 0 2006.175.08:05:59.60#ibcon#enter sib2, iclass 16, count 0 2006.175.08:05:59.60#ibcon#flushed, iclass 16, count 0 2006.175.08:05:59.60#ibcon#about to write, iclass 16, count 0 2006.175.08:05:59.60#ibcon#wrote, iclass 16, count 0 2006.175.08:05:59.60#ibcon#about to read 3, iclass 16, count 0 2006.175.08:05:59.63#ibcon#read 3, iclass 16, count 0 2006.175.08:05:59.63#ibcon#about to read 4, iclass 16, count 0 2006.175.08:05:59.63#ibcon#read 4, iclass 16, count 0 2006.175.08:05:59.63#ibcon#about to read 5, iclass 16, count 0 2006.175.08:05:59.63#ibcon#read 5, iclass 16, count 0 2006.175.08:05:59.63#ibcon#about to read 6, iclass 16, count 0 2006.175.08:05:59.63#ibcon#read 6, iclass 16, count 0 2006.175.08:05:59.63#ibcon#end of sib2, iclass 16, count 0 2006.175.08:05:59.63#ibcon#*after write, iclass 16, count 0 2006.175.08:05:59.63#ibcon#*before return 0, iclass 16, count 0 2006.175.08:05:59.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:05:59.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:05:59.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:05:59.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:05:59.63$vc4f8/valo=6,772.99 2006.175.08:05:59.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.08:05:59.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.08:05:59.63#ibcon#ireg 17 cls_cnt 0 2006.175.08:05:59.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:05:59.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:05:59.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:05:59.63#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:05:59.63#ibcon#first serial, iclass 18, count 0 2006.175.08:05:59.63#ibcon#enter sib2, iclass 18, count 0 2006.175.08:05:59.63#ibcon#flushed, iclass 18, count 0 2006.175.08:05:59.63#ibcon#about to write, iclass 18, count 0 2006.175.08:05:59.63#ibcon#wrote, iclass 18, count 0 2006.175.08:05:59.63#ibcon#about to read 3, iclass 18, count 0 2006.175.08:05:59.65#ibcon#read 3, iclass 18, count 0 2006.175.08:05:59.65#ibcon#about to read 4, iclass 18, count 0 2006.175.08:05:59.65#ibcon#read 4, iclass 18, count 0 2006.175.08:05:59.65#ibcon#about to read 5, iclass 18, count 0 2006.175.08:05:59.65#ibcon#read 5, iclass 18, count 0 2006.175.08:05:59.65#ibcon#about to read 6, iclass 18, count 0 2006.175.08:05:59.65#ibcon#read 6, iclass 18, count 0 2006.175.08:05:59.65#ibcon#end of sib2, iclass 18, count 0 2006.175.08:05:59.65#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:05:59.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:05:59.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:05:59.65#ibcon#*before write, iclass 18, count 0 2006.175.08:05:59.65#ibcon#enter sib2, iclass 18, count 0 2006.175.08:05:59.65#ibcon#flushed, iclass 18, count 0 2006.175.08:05:59.65#ibcon#about to write, iclass 18, count 0 2006.175.08:05:59.65#ibcon#wrote, iclass 18, count 0 2006.175.08:05:59.65#ibcon#about to read 3, iclass 18, count 0 2006.175.08:05:59.69#ibcon#read 3, iclass 18, count 0 2006.175.08:05:59.69#ibcon#about to read 4, iclass 18, count 0 2006.175.08:05:59.69#ibcon#read 4, iclass 18, count 0 2006.175.08:05:59.69#ibcon#about to read 5, iclass 18, count 0 2006.175.08:05:59.69#ibcon#read 5, iclass 18, count 0 2006.175.08:05:59.69#ibcon#about to read 6, iclass 18, count 0 2006.175.08:05:59.69#ibcon#read 6, iclass 18, count 0 2006.175.08:05:59.69#ibcon#end of sib2, iclass 18, count 0 2006.175.08:05:59.69#ibcon#*after write, iclass 18, count 0 2006.175.08:05:59.69#ibcon#*before return 0, iclass 18, count 0 2006.175.08:05:59.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:05:59.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:05:59.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:05:59.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:05:59.69$vc4f8/va=6,6 2006.175.08:05:59.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.175.08:05:59.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.175.08:05:59.69#ibcon#ireg 11 cls_cnt 2 2006.175.08:05:59.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:05:59.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:05:59.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:05:59.75#ibcon#enter wrdev, iclass 20, count 2 2006.175.08:05:59.75#ibcon#first serial, iclass 20, count 2 2006.175.08:05:59.75#ibcon#enter sib2, iclass 20, count 2 2006.175.08:05:59.75#ibcon#flushed, iclass 20, count 2 2006.175.08:05:59.75#ibcon#about to write, iclass 20, count 2 2006.175.08:05:59.75#ibcon#wrote, iclass 20, count 2 2006.175.08:05:59.75#ibcon#about to read 3, iclass 20, count 2 2006.175.08:05:59.77#ibcon#read 3, iclass 20, count 2 2006.175.08:05:59.77#ibcon#about to read 4, iclass 20, count 2 2006.175.08:05:59.77#ibcon#read 4, iclass 20, count 2 2006.175.08:05:59.77#ibcon#about to read 5, iclass 20, count 2 2006.175.08:05:59.77#ibcon#read 5, iclass 20, count 2 2006.175.08:05:59.77#ibcon#about to read 6, iclass 20, count 2 2006.175.08:05:59.77#ibcon#read 6, iclass 20, count 2 2006.175.08:05:59.77#ibcon#end of sib2, iclass 20, count 2 2006.175.08:05:59.77#ibcon#*mode == 0, iclass 20, count 2 2006.175.08:05:59.77#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.175.08:05:59.77#ibcon#[25=AT06-06\r\n] 2006.175.08:05:59.77#ibcon#*before write, iclass 20, count 2 2006.175.08:05:59.77#ibcon#enter sib2, iclass 20, count 2 2006.175.08:05:59.77#ibcon#flushed, iclass 20, count 2 2006.175.08:05:59.77#ibcon#about to write, iclass 20, count 2 2006.175.08:05:59.77#ibcon#wrote, iclass 20, count 2 2006.175.08:05:59.77#ibcon#about to read 3, iclass 20, count 2 2006.175.08:05:59.80#ibcon#read 3, iclass 20, count 2 2006.175.08:05:59.80#ibcon#about to read 4, iclass 20, count 2 2006.175.08:05:59.80#ibcon#read 4, iclass 20, count 2 2006.175.08:05:59.80#ibcon#about to read 5, iclass 20, count 2 2006.175.08:05:59.80#ibcon#read 5, iclass 20, count 2 2006.175.08:05:59.80#ibcon#about to read 6, iclass 20, count 2 2006.175.08:05:59.80#ibcon#read 6, iclass 20, count 2 2006.175.08:05:59.80#ibcon#end of sib2, iclass 20, count 2 2006.175.08:05:59.80#ibcon#*after write, iclass 20, count 2 2006.175.08:05:59.80#ibcon#*before return 0, iclass 20, count 2 2006.175.08:05:59.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:05:59.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:05:59.80#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.175.08:05:59.80#ibcon#ireg 7 cls_cnt 0 2006.175.08:05:59.80#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:05:59.92#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:05:59.92#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:05:59.92#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:05:59.92#ibcon#first serial, iclass 20, count 0 2006.175.08:05:59.92#ibcon#enter sib2, iclass 20, count 0 2006.175.08:05:59.92#ibcon#flushed, iclass 20, count 0 2006.175.08:05:59.92#ibcon#about to write, iclass 20, count 0 2006.175.08:05:59.92#ibcon#wrote, iclass 20, count 0 2006.175.08:05:59.92#ibcon#about to read 3, iclass 20, count 0 2006.175.08:05:59.94#ibcon#read 3, iclass 20, count 0 2006.175.08:05:59.94#ibcon#about to read 4, iclass 20, count 0 2006.175.08:05:59.94#ibcon#read 4, iclass 20, count 0 2006.175.08:05:59.94#ibcon#about to read 5, iclass 20, count 0 2006.175.08:05:59.94#ibcon#read 5, iclass 20, count 0 2006.175.08:05:59.94#ibcon#about to read 6, iclass 20, count 0 2006.175.08:05:59.94#ibcon#read 6, iclass 20, count 0 2006.175.08:05:59.94#ibcon#end of sib2, iclass 20, count 0 2006.175.08:05:59.94#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:05:59.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:05:59.94#ibcon#[25=USB\r\n] 2006.175.08:05:59.94#ibcon#*before write, iclass 20, count 0 2006.175.08:05:59.94#ibcon#enter sib2, iclass 20, count 0 2006.175.08:05:59.94#ibcon#flushed, iclass 20, count 0 2006.175.08:05:59.94#ibcon#about to write, iclass 20, count 0 2006.175.08:05:59.94#ibcon#wrote, iclass 20, count 0 2006.175.08:05:59.94#ibcon#about to read 3, iclass 20, count 0 2006.175.08:05:59.97#ibcon#read 3, iclass 20, count 0 2006.175.08:05:59.97#ibcon#about to read 4, iclass 20, count 0 2006.175.08:05:59.97#ibcon#read 4, iclass 20, count 0 2006.175.08:05:59.97#ibcon#about to read 5, iclass 20, count 0 2006.175.08:05:59.97#ibcon#read 5, iclass 20, count 0 2006.175.08:05:59.97#ibcon#about to read 6, iclass 20, count 0 2006.175.08:05:59.97#ibcon#read 6, iclass 20, count 0 2006.175.08:05:59.97#ibcon#end of sib2, iclass 20, count 0 2006.175.08:05:59.97#ibcon#*after write, iclass 20, count 0 2006.175.08:05:59.97#ibcon#*before return 0, iclass 20, count 0 2006.175.08:05:59.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:05:59.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:05:59.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:05:59.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:05:59.97$vc4f8/valo=7,832.99 2006.175.08:05:59.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.08:05:59.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.08:05:59.97#ibcon#ireg 17 cls_cnt 0 2006.175.08:05:59.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:05:59.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:05:59.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:05:59.97#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:05:59.97#ibcon#first serial, iclass 22, count 0 2006.175.08:05:59.97#ibcon#enter sib2, iclass 22, count 0 2006.175.08:05:59.97#ibcon#flushed, iclass 22, count 0 2006.175.08:05:59.97#ibcon#about to write, iclass 22, count 0 2006.175.08:05:59.97#ibcon#wrote, iclass 22, count 0 2006.175.08:05:59.97#ibcon#about to read 3, iclass 22, count 0 2006.175.08:05:59.99#ibcon#read 3, iclass 22, count 0 2006.175.08:05:59.99#ibcon#about to read 4, iclass 22, count 0 2006.175.08:05:59.99#ibcon#read 4, iclass 22, count 0 2006.175.08:05:59.99#ibcon#about to read 5, iclass 22, count 0 2006.175.08:05:59.99#ibcon#read 5, iclass 22, count 0 2006.175.08:05:59.99#ibcon#about to read 6, iclass 22, count 0 2006.175.08:05:59.99#ibcon#read 6, iclass 22, count 0 2006.175.08:05:59.99#ibcon#end of sib2, iclass 22, count 0 2006.175.08:05:59.99#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:05:59.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:05:59.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:05:59.99#ibcon#*before write, iclass 22, count 0 2006.175.08:05:59.99#ibcon#enter sib2, iclass 22, count 0 2006.175.08:05:59.99#ibcon#flushed, iclass 22, count 0 2006.175.08:05:59.99#ibcon#about to write, iclass 22, count 0 2006.175.08:05:59.99#ibcon#wrote, iclass 22, count 0 2006.175.08:05:59.99#ibcon#about to read 3, iclass 22, count 0 2006.175.08:06:00.03#ibcon#read 3, iclass 22, count 0 2006.175.08:06:00.03#ibcon#about to read 4, iclass 22, count 0 2006.175.08:06:00.03#ibcon#read 4, iclass 22, count 0 2006.175.08:06:00.03#ibcon#about to read 5, iclass 22, count 0 2006.175.08:06:00.03#ibcon#read 5, iclass 22, count 0 2006.175.08:06:00.03#ibcon#about to read 6, iclass 22, count 0 2006.175.08:06:00.03#ibcon#read 6, iclass 22, count 0 2006.175.08:06:00.03#ibcon#end of sib2, iclass 22, count 0 2006.175.08:06:00.03#ibcon#*after write, iclass 22, count 0 2006.175.08:06:00.03#ibcon#*before return 0, iclass 22, count 0 2006.175.08:06:00.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:06:00.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:06:00.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:06:00.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:06:00.03$vc4f8/va=7,6 2006.175.08:06:00.03#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.08:06:00.03#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.08:06:00.03#ibcon#ireg 11 cls_cnt 2 2006.175.08:06:00.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:06:00.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:06:00.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:06:00.09#ibcon#enter wrdev, iclass 24, count 2 2006.175.08:06:00.09#ibcon#first serial, iclass 24, count 2 2006.175.08:06:00.09#ibcon#enter sib2, iclass 24, count 2 2006.175.08:06:00.09#ibcon#flushed, iclass 24, count 2 2006.175.08:06:00.09#ibcon#about to write, iclass 24, count 2 2006.175.08:06:00.09#ibcon#wrote, iclass 24, count 2 2006.175.08:06:00.09#ibcon#about to read 3, iclass 24, count 2 2006.175.08:06:00.11#ibcon#read 3, iclass 24, count 2 2006.175.08:06:00.11#ibcon#about to read 4, iclass 24, count 2 2006.175.08:06:00.11#ibcon#read 4, iclass 24, count 2 2006.175.08:06:00.11#ibcon#about to read 5, iclass 24, count 2 2006.175.08:06:00.11#ibcon#read 5, iclass 24, count 2 2006.175.08:06:00.11#ibcon#about to read 6, iclass 24, count 2 2006.175.08:06:00.11#ibcon#read 6, iclass 24, count 2 2006.175.08:06:00.11#ibcon#end of sib2, iclass 24, count 2 2006.175.08:06:00.11#ibcon#*mode == 0, iclass 24, count 2 2006.175.08:06:00.11#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.08:06:00.11#ibcon#[25=AT07-06\r\n] 2006.175.08:06:00.11#ibcon#*before write, iclass 24, count 2 2006.175.08:06:00.11#ibcon#enter sib2, iclass 24, count 2 2006.175.08:06:00.11#ibcon#flushed, iclass 24, count 2 2006.175.08:06:00.11#ibcon#about to write, iclass 24, count 2 2006.175.08:06:00.11#ibcon#wrote, iclass 24, count 2 2006.175.08:06:00.11#ibcon#about to read 3, iclass 24, count 2 2006.175.08:06:00.14#ibcon#read 3, iclass 24, count 2 2006.175.08:06:00.14#ibcon#about to read 4, iclass 24, count 2 2006.175.08:06:00.14#ibcon#read 4, iclass 24, count 2 2006.175.08:06:00.14#ibcon#about to read 5, iclass 24, count 2 2006.175.08:06:00.14#ibcon#read 5, iclass 24, count 2 2006.175.08:06:00.14#ibcon#about to read 6, iclass 24, count 2 2006.175.08:06:00.14#ibcon#read 6, iclass 24, count 2 2006.175.08:06:00.14#ibcon#end of sib2, iclass 24, count 2 2006.175.08:06:00.14#ibcon#*after write, iclass 24, count 2 2006.175.08:06:00.14#ibcon#*before return 0, iclass 24, count 2 2006.175.08:06:00.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:06:00.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:06:00.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.08:06:00.14#ibcon#ireg 7 cls_cnt 0 2006.175.08:06:00.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:06:00.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:06:00.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:06:00.26#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:06:00.26#ibcon#first serial, iclass 24, count 0 2006.175.08:06:00.26#ibcon#enter sib2, iclass 24, count 0 2006.175.08:06:00.26#ibcon#flushed, iclass 24, count 0 2006.175.08:06:00.26#ibcon#about to write, iclass 24, count 0 2006.175.08:06:00.26#ibcon#wrote, iclass 24, count 0 2006.175.08:06:00.26#ibcon#about to read 3, iclass 24, count 0 2006.175.08:06:00.28#ibcon#read 3, iclass 24, count 0 2006.175.08:06:00.28#ibcon#about to read 4, iclass 24, count 0 2006.175.08:06:00.28#ibcon#read 4, iclass 24, count 0 2006.175.08:06:00.28#ibcon#about to read 5, iclass 24, count 0 2006.175.08:06:00.28#ibcon#read 5, iclass 24, count 0 2006.175.08:06:00.28#ibcon#about to read 6, iclass 24, count 0 2006.175.08:06:00.28#ibcon#read 6, iclass 24, count 0 2006.175.08:06:00.28#ibcon#end of sib2, iclass 24, count 0 2006.175.08:06:00.28#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:06:00.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:06:00.28#ibcon#[25=USB\r\n] 2006.175.08:06:00.28#ibcon#*before write, iclass 24, count 0 2006.175.08:06:00.28#ibcon#enter sib2, iclass 24, count 0 2006.175.08:06:00.28#ibcon#flushed, iclass 24, count 0 2006.175.08:06:00.28#ibcon#about to write, iclass 24, count 0 2006.175.08:06:00.28#ibcon#wrote, iclass 24, count 0 2006.175.08:06:00.28#ibcon#about to read 3, iclass 24, count 0 2006.175.08:06:00.31#ibcon#read 3, iclass 24, count 0 2006.175.08:06:00.31#ibcon#about to read 4, iclass 24, count 0 2006.175.08:06:00.31#ibcon#read 4, iclass 24, count 0 2006.175.08:06:00.31#ibcon#about to read 5, iclass 24, count 0 2006.175.08:06:00.31#ibcon#read 5, iclass 24, count 0 2006.175.08:06:00.31#ibcon#about to read 6, iclass 24, count 0 2006.175.08:06:00.31#ibcon#read 6, iclass 24, count 0 2006.175.08:06:00.31#ibcon#end of sib2, iclass 24, count 0 2006.175.08:06:00.31#ibcon#*after write, iclass 24, count 0 2006.175.08:06:00.31#ibcon#*before return 0, iclass 24, count 0 2006.175.08:06:00.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:06:00.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:06:00.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:06:00.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:06:00.31$vc4f8/valo=8,852.99 2006.175.08:06:00.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.08:06:00.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.08:06:00.31#ibcon#ireg 17 cls_cnt 0 2006.175.08:06:00.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:06:00.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:06:00.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:06:00.31#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:06:00.31#ibcon#first serial, iclass 26, count 0 2006.175.08:06:00.31#ibcon#enter sib2, iclass 26, count 0 2006.175.08:06:00.31#ibcon#flushed, iclass 26, count 0 2006.175.08:06:00.31#ibcon#about to write, iclass 26, count 0 2006.175.08:06:00.31#ibcon#wrote, iclass 26, count 0 2006.175.08:06:00.31#ibcon#about to read 3, iclass 26, count 0 2006.175.08:06:00.33#ibcon#read 3, iclass 26, count 0 2006.175.08:06:00.33#ibcon#about to read 4, iclass 26, count 0 2006.175.08:06:00.33#ibcon#read 4, iclass 26, count 0 2006.175.08:06:00.33#ibcon#about to read 5, iclass 26, count 0 2006.175.08:06:00.33#ibcon#read 5, iclass 26, count 0 2006.175.08:06:00.33#ibcon#about to read 6, iclass 26, count 0 2006.175.08:06:00.33#ibcon#read 6, iclass 26, count 0 2006.175.08:06:00.33#ibcon#end of sib2, iclass 26, count 0 2006.175.08:06:00.33#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:06:00.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:06:00.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:06:00.33#ibcon#*before write, iclass 26, count 0 2006.175.08:06:00.33#ibcon#enter sib2, iclass 26, count 0 2006.175.08:06:00.33#ibcon#flushed, iclass 26, count 0 2006.175.08:06:00.33#ibcon#about to write, iclass 26, count 0 2006.175.08:06:00.33#ibcon#wrote, iclass 26, count 0 2006.175.08:06:00.33#ibcon#about to read 3, iclass 26, count 0 2006.175.08:06:00.37#ibcon#read 3, iclass 26, count 0 2006.175.08:06:00.37#ibcon#about to read 4, iclass 26, count 0 2006.175.08:06:00.37#ibcon#read 4, iclass 26, count 0 2006.175.08:06:00.37#ibcon#about to read 5, iclass 26, count 0 2006.175.08:06:00.37#ibcon#read 5, iclass 26, count 0 2006.175.08:06:00.37#ibcon#about to read 6, iclass 26, count 0 2006.175.08:06:00.37#ibcon#read 6, iclass 26, count 0 2006.175.08:06:00.37#ibcon#end of sib2, iclass 26, count 0 2006.175.08:06:00.37#ibcon#*after write, iclass 26, count 0 2006.175.08:06:00.37#ibcon#*before return 0, iclass 26, count 0 2006.175.08:06:00.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:06:00.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:06:00.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:06:00.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:06:00.37$vc4f8/va=8,6 2006.175.08:06:00.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.08:06:00.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.08:06:00.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:06:00.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:06:00.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:06:00.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:06:00.43#ibcon#enter wrdev, iclass 28, count 2 2006.175.08:06:00.43#ibcon#first serial, iclass 28, count 2 2006.175.08:06:00.43#ibcon#enter sib2, iclass 28, count 2 2006.175.08:06:00.43#ibcon#flushed, iclass 28, count 2 2006.175.08:06:00.43#ibcon#about to write, iclass 28, count 2 2006.175.08:06:00.43#ibcon#wrote, iclass 28, count 2 2006.175.08:06:00.43#ibcon#about to read 3, iclass 28, count 2 2006.175.08:06:00.45#ibcon#read 3, iclass 28, count 2 2006.175.08:06:00.45#ibcon#about to read 4, iclass 28, count 2 2006.175.08:06:00.45#ibcon#read 4, iclass 28, count 2 2006.175.08:06:00.45#ibcon#about to read 5, iclass 28, count 2 2006.175.08:06:00.45#ibcon#read 5, iclass 28, count 2 2006.175.08:06:00.45#ibcon#about to read 6, iclass 28, count 2 2006.175.08:06:00.45#ibcon#read 6, iclass 28, count 2 2006.175.08:06:00.45#ibcon#end of sib2, iclass 28, count 2 2006.175.08:06:00.45#ibcon#*mode == 0, iclass 28, count 2 2006.175.08:06:00.45#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.08:06:00.45#ibcon#[25=AT08-06\r\n] 2006.175.08:06:00.45#ibcon#*before write, iclass 28, count 2 2006.175.08:06:00.45#ibcon#enter sib2, iclass 28, count 2 2006.175.08:06:00.45#ibcon#flushed, iclass 28, count 2 2006.175.08:06:00.45#ibcon#about to write, iclass 28, count 2 2006.175.08:06:00.45#ibcon#wrote, iclass 28, count 2 2006.175.08:06:00.45#ibcon#about to read 3, iclass 28, count 2 2006.175.08:06:00.48#ibcon#read 3, iclass 28, count 2 2006.175.08:06:00.48#ibcon#about to read 4, iclass 28, count 2 2006.175.08:06:00.48#ibcon#read 4, iclass 28, count 2 2006.175.08:06:00.48#ibcon#about to read 5, iclass 28, count 2 2006.175.08:06:00.48#ibcon#read 5, iclass 28, count 2 2006.175.08:06:00.48#ibcon#about to read 6, iclass 28, count 2 2006.175.08:06:00.48#ibcon#read 6, iclass 28, count 2 2006.175.08:06:00.48#ibcon#end of sib2, iclass 28, count 2 2006.175.08:06:00.48#ibcon#*after write, iclass 28, count 2 2006.175.08:06:00.48#ibcon#*before return 0, iclass 28, count 2 2006.175.08:06:00.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:06:00.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:06:00.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.08:06:00.48#ibcon#ireg 7 cls_cnt 0 2006.175.08:06:00.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:06:00.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:06:00.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:06:00.60#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:06:00.60#ibcon#first serial, iclass 28, count 0 2006.175.08:06:00.60#ibcon#enter sib2, iclass 28, count 0 2006.175.08:06:00.60#ibcon#flushed, iclass 28, count 0 2006.175.08:06:00.60#ibcon#about to write, iclass 28, count 0 2006.175.08:06:00.60#ibcon#wrote, iclass 28, count 0 2006.175.08:06:00.60#ibcon#about to read 3, iclass 28, count 0 2006.175.08:06:00.62#ibcon#read 3, iclass 28, count 0 2006.175.08:06:00.62#ibcon#about to read 4, iclass 28, count 0 2006.175.08:06:00.62#ibcon#read 4, iclass 28, count 0 2006.175.08:06:00.62#ibcon#about to read 5, iclass 28, count 0 2006.175.08:06:00.62#ibcon#read 5, iclass 28, count 0 2006.175.08:06:00.62#ibcon#about to read 6, iclass 28, count 0 2006.175.08:06:00.62#ibcon#read 6, iclass 28, count 0 2006.175.08:06:00.62#ibcon#end of sib2, iclass 28, count 0 2006.175.08:06:00.62#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:06:00.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:06:00.62#ibcon#[25=USB\r\n] 2006.175.08:06:00.62#ibcon#*before write, iclass 28, count 0 2006.175.08:06:00.62#ibcon#enter sib2, iclass 28, count 0 2006.175.08:06:00.62#ibcon#flushed, iclass 28, count 0 2006.175.08:06:00.62#ibcon#about to write, iclass 28, count 0 2006.175.08:06:00.62#ibcon#wrote, iclass 28, count 0 2006.175.08:06:00.62#ibcon#about to read 3, iclass 28, count 0 2006.175.08:06:00.65#ibcon#read 3, iclass 28, count 0 2006.175.08:06:00.65#ibcon#about to read 4, iclass 28, count 0 2006.175.08:06:00.65#ibcon#read 4, iclass 28, count 0 2006.175.08:06:00.65#ibcon#about to read 5, iclass 28, count 0 2006.175.08:06:00.65#ibcon#read 5, iclass 28, count 0 2006.175.08:06:00.65#ibcon#about to read 6, iclass 28, count 0 2006.175.08:06:00.65#ibcon#read 6, iclass 28, count 0 2006.175.08:06:00.65#ibcon#end of sib2, iclass 28, count 0 2006.175.08:06:00.65#ibcon#*after write, iclass 28, count 0 2006.175.08:06:00.65#ibcon#*before return 0, iclass 28, count 0 2006.175.08:06:00.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:06:00.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:06:00.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:06:00.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:06:00.65$vc4f8/vblo=1,632.99 2006.175.08:06:00.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.08:06:00.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.08:06:00.65#ibcon#ireg 17 cls_cnt 0 2006.175.08:06:00.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:06:00.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:06:00.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:06:00.65#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:06:00.65#ibcon#first serial, iclass 30, count 0 2006.175.08:06:00.65#ibcon#enter sib2, iclass 30, count 0 2006.175.08:06:00.65#ibcon#flushed, iclass 30, count 0 2006.175.08:06:00.65#ibcon#about to write, iclass 30, count 0 2006.175.08:06:00.65#ibcon#wrote, iclass 30, count 0 2006.175.08:06:00.65#ibcon#about to read 3, iclass 30, count 0 2006.175.08:06:00.67#ibcon#read 3, iclass 30, count 0 2006.175.08:06:00.67#ibcon#about to read 4, iclass 30, count 0 2006.175.08:06:00.67#ibcon#read 4, iclass 30, count 0 2006.175.08:06:00.67#ibcon#about to read 5, iclass 30, count 0 2006.175.08:06:00.67#ibcon#read 5, iclass 30, count 0 2006.175.08:06:00.67#ibcon#about to read 6, iclass 30, count 0 2006.175.08:06:00.67#ibcon#read 6, iclass 30, count 0 2006.175.08:06:00.67#ibcon#end of sib2, iclass 30, count 0 2006.175.08:06:00.67#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:06:00.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:06:00.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:06:00.67#ibcon#*before write, iclass 30, count 0 2006.175.08:06:00.67#ibcon#enter sib2, iclass 30, count 0 2006.175.08:06:00.67#ibcon#flushed, iclass 30, count 0 2006.175.08:06:00.67#ibcon#about to write, iclass 30, count 0 2006.175.08:06:00.67#ibcon#wrote, iclass 30, count 0 2006.175.08:06:00.67#ibcon#about to read 3, iclass 30, count 0 2006.175.08:06:00.71#ibcon#read 3, iclass 30, count 0 2006.175.08:06:00.71#ibcon#about to read 4, iclass 30, count 0 2006.175.08:06:00.71#ibcon#read 4, iclass 30, count 0 2006.175.08:06:00.71#ibcon#about to read 5, iclass 30, count 0 2006.175.08:06:00.71#ibcon#read 5, iclass 30, count 0 2006.175.08:06:00.71#ibcon#about to read 6, iclass 30, count 0 2006.175.08:06:00.71#ibcon#read 6, iclass 30, count 0 2006.175.08:06:00.71#ibcon#end of sib2, iclass 30, count 0 2006.175.08:06:00.71#ibcon#*after write, iclass 30, count 0 2006.175.08:06:00.71#ibcon#*before return 0, iclass 30, count 0 2006.175.08:06:00.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:06:00.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:06:00.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:06:00.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:06:00.71$vc4f8/vb=1,4 2006.175.08:06:00.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.08:06:00.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.08:06:00.71#ibcon#ireg 11 cls_cnt 2 2006.175.08:06:00.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:06:00.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:06:00.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:06:00.71#ibcon#enter wrdev, iclass 32, count 2 2006.175.08:06:00.71#ibcon#first serial, iclass 32, count 2 2006.175.08:06:00.71#ibcon#enter sib2, iclass 32, count 2 2006.175.08:06:00.71#ibcon#flushed, iclass 32, count 2 2006.175.08:06:00.71#ibcon#about to write, iclass 32, count 2 2006.175.08:06:00.71#ibcon#wrote, iclass 32, count 2 2006.175.08:06:00.71#ibcon#about to read 3, iclass 32, count 2 2006.175.08:06:00.73#ibcon#read 3, iclass 32, count 2 2006.175.08:06:00.73#ibcon#about to read 4, iclass 32, count 2 2006.175.08:06:00.73#ibcon#read 4, iclass 32, count 2 2006.175.08:06:00.73#ibcon#about to read 5, iclass 32, count 2 2006.175.08:06:00.73#ibcon#read 5, iclass 32, count 2 2006.175.08:06:00.73#ibcon#about to read 6, iclass 32, count 2 2006.175.08:06:00.73#ibcon#read 6, iclass 32, count 2 2006.175.08:06:00.73#ibcon#end of sib2, iclass 32, count 2 2006.175.08:06:00.73#ibcon#*mode == 0, iclass 32, count 2 2006.175.08:06:00.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.08:06:00.73#ibcon#[27=AT01-04\r\n] 2006.175.08:06:00.73#ibcon#*before write, iclass 32, count 2 2006.175.08:06:00.73#ibcon#enter sib2, iclass 32, count 2 2006.175.08:06:00.73#ibcon#flushed, iclass 32, count 2 2006.175.08:06:00.73#ibcon#about to write, iclass 32, count 2 2006.175.08:06:00.73#ibcon#wrote, iclass 32, count 2 2006.175.08:06:00.73#ibcon#about to read 3, iclass 32, count 2 2006.175.08:06:00.76#ibcon#read 3, iclass 32, count 2 2006.175.08:06:00.76#ibcon#about to read 4, iclass 32, count 2 2006.175.08:06:00.76#ibcon#read 4, iclass 32, count 2 2006.175.08:06:00.76#ibcon#about to read 5, iclass 32, count 2 2006.175.08:06:00.76#ibcon#read 5, iclass 32, count 2 2006.175.08:06:00.76#ibcon#about to read 6, iclass 32, count 2 2006.175.08:06:00.76#ibcon#read 6, iclass 32, count 2 2006.175.08:06:00.76#ibcon#end of sib2, iclass 32, count 2 2006.175.08:06:00.76#ibcon#*after write, iclass 32, count 2 2006.175.08:06:00.76#ibcon#*before return 0, iclass 32, count 2 2006.175.08:06:00.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:06:00.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:06:00.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.08:06:00.76#ibcon#ireg 7 cls_cnt 0 2006.175.08:06:00.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:06:00.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:06:00.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:06:00.88#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:06:00.88#ibcon#first serial, iclass 32, count 0 2006.175.08:06:00.88#ibcon#enter sib2, iclass 32, count 0 2006.175.08:06:00.88#ibcon#flushed, iclass 32, count 0 2006.175.08:06:00.88#ibcon#about to write, iclass 32, count 0 2006.175.08:06:00.88#ibcon#wrote, iclass 32, count 0 2006.175.08:06:00.88#ibcon#about to read 3, iclass 32, count 0 2006.175.08:06:00.90#ibcon#read 3, iclass 32, count 0 2006.175.08:06:00.90#ibcon#about to read 4, iclass 32, count 0 2006.175.08:06:00.90#ibcon#read 4, iclass 32, count 0 2006.175.08:06:00.90#ibcon#about to read 5, iclass 32, count 0 2006.175.08:06:00.90#ibcon#read 5, iclass 32, count 0 2006.175.08:06:00.90#ibcon#about to read 6, iclass 32, count 0 2006.175.08:06:00.90#ibcon#read 6, iclass 32, count 0 2006.175.08:06:00.90#ibcon#end of sib2, iclass 32, count 0 2006.175.08:06:00.90#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:06:00.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:06:00.90#ibcon#[27=USB\r\n] 2006.175.08:06:00.90#ibcon#*before write, iclass 32, count 0 2006.175.08:06:00.90#ibcon#enter sib2, iclass 32, count 0 2006.175.08:06:00.90#ibcon#flushed, iclass 32, count 0 2006.175.08:06:00.90#ibcon#about to write, iclass 32, count 0 2006.175.08:06:00.90#ibcon#wrote, iclass 32, count 0 2006.175.08:06:00.90#ibcon#about to read 3, iclass 32, count 0 2006.175.08:06:00.93#ibcon#read 3, iclass 32, count 0 2006.175.08:06:00.93#ibcon#about to read 4, iclass 32, count 0 2006.175.08:06:00.93#ibcon#read 4, iclass 32, count 0 2006.175.08:06:00.93#ibcon#about to read 5, iclass 32, count 0 2006.175.08:06:00.93#ibcon#read 5, iclass 32, count 0 2006.175.08:06:00.93#ibcon#about to read 6, iclass 32, count 0 2006.175.08:06:00.93#ibcon#read 6, iclass 32, count 0 2006.175.08:06:00.93#ibcon#end of sib2, iclass 32, count 0 2006.175.08:06:00.93#ibcon#*after write, iclass 32, count 0 2006.175.08:06:00.93#ibcon#*before return 0, iclass 32, count 0 2006.175.08:06:00.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:06:00.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:06:00.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:06:00.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:06:00.93$vc4f8/vblo=2,640.99 2006.175.08:06:00.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.08:06:00.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.08:06:00.93#ibcon#ireg 17 cls_cnt 0 2006.175.08:06:00.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:06:00.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:06:00.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:06:00.93#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:06:00.93#ibcon#first serial, iclass 34, count 0 2006.175.08:06:00.93#ibcon#enter sib2, iclass 34, count 0 2006.175.08:06:00.93#ibcon#flushed, iclass 34, count 0 2006.175.08:06:00.93#ibcon#about to write, iclass 34, count 0 2006.175.08:06:00.93#ibcon#wrote, iclass 34, count 0 2006.175.08:06:00.93#ibcon#about to read 3, iclass 34, count 0 2006.175.08:06:00.95#ibcon#read 3, iclass 34, count 0 2006.175.08:06:00.95#ibcon#about to read 4, iclass 34, count 0 2006.175.08:06:00.95#ibcon#read 4, iclass 34, count 0 2006.175.08:06:00.95#ibcon#about to read 5, iclass 34, count 0 2006.175.08:06:00.95#ibcon#read 5, iclass 34, count 0 2006.175.08:06:00.95#ibcon#about to read 6, iclass 34, count 0 2006.175.08:06:00.95#ibcon#read 6, iclass 34, count 0 2006.175.08:06:00.95#ibcon#end of sib2, iclass 34, count 0 2006.175.08:06:00.95#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:06:00.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:06:00.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:06:00.95#ibcon#*before write, iclass 34, count 0 2006.175.08:06:00.95#ibcon#enter sib2, iclass 34, count 0 2006.175.08:06:00.95#ibcon#flushed, iclass 34, count 0 2006.175.08:06:00.95#ibcon#about to write, iclass 34, count 0 2006.175.08:06:00.95#ibcon#wrote, iclass 34, count 0 2006.175.08:06:00.95#ibcon#about to read 3, iclass 34, count 0 2006.175.08:06:00.99#ibcon#read 3, iclass 34, count 0 2006.175.08:06:00.99#ibcon#about to read 4, iclass 34, count 0 2006.175.08:06:00.99#ibcon#read 4, iclass 34, count 0 2006.175.08:06:00.99#ibcon#about to read 5, iclass 34, count 0 2006.175.08:06:00.99#ibcon#read 5, iclass 34, count 0 2006.175.08:06:00.99#ibcon#about to read 6, iclass 34, count 0 2006.175.08:06:00.99#ibcon#read 6, iclass 34, count 0 2006.175.08:06:00.99#ibcon#end of sib2, iclass 34, count 0 2006.175.08:06:00.99#ibcon#*after write, iclass 34, count 0 2006.175.08:06:00.99#ibcon#*before return 0, iclass 34, count 0 2006.175.08:06:00.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:06:00.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:06:00.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:06:00.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:06:00.99$vc4f8/vb=2,4 2006.175.08:06:00.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.08:06:00.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.08:06:00.99#ibcon#ireg 11 cls_cnt 2 2006.175.08:06:00.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:06:01.06#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:06:01.06#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:06:01.06#ibcon#enter wrdev, iclass 36, count 2 2006.175.08:06:01.06#ibcon#first serial, iclass 36, count 2 2006.175.08:06:01.06#ibcon#enter sib2, iclass 36, count 2 2006.175.08:06:01.06#ibcon#flushed, iclass 36, count 2 2006.175.08:06:01.06#ibcon#about to write, iclass 36, count 2 2006.175.08:06:01.06#ibcon#wrote, iclass 36, count 2 2006.175.08:06:01.06#ibcon#about to read 3, iclass 36, count 2 2006.175.08:06:01.07#ibcon#read 3, iclass 36, count 2 2006.175.08:06:01.07#ibcon#about to read 4, iclass 36, count 2 2006.175.08:06:01.07#ibcon#read 4, iclass 36, count 2 2006.175.08:06:01.07#ibcon#about to read 5, iclass 36, count 2 2006.175.08:06:01.07#ibcon#read 5, iclass 36, count 2 2006.175.08:06:01.07#ibcon#about to read 6, iclass 36, count 2 2006.175.08:06:01.07#ibcon#read 6, iclass 36, count 2 2006.175.08:06:01.07#ibcon#end of sib2, iclass 36, count 2 2006.175.08:06:01.07#ibcon#*mode == 0, iclass 36, count 2 2006.175.08:06:01.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.08:06:01.07#ibcon#[27=AT02-04\r\n] 2006.175.08:06:01.07#ibcon#*before write, iclass 36, count 2 2006.175.08:06:01.07#ibcon#enter sib2, iclass 36, count 2 2006.175.08:06:01.07#ibcon#flushed, iclass 36, count 2 2006.175.08:06:01.07#ibcon#about to write, iclass 36, count 2 2006.175.08:06:01.07#ibcon#wrote, iclass 36, count 2 2006.175.08:06:01.07#ibcon#about to read 3, iclass 36, count 2 2006.175.08:06:01.10#ibcon#read 3, iclass 36, count 2 2006.175.08:06:01.10#ibcon#about to read 4, iclass 36, count 2 2006.175.08:06:01.10#ibcon#read 4, iclass 36, count 2 2006.175.08:06:01.10#ibcon#about to read 5, iclass 36, count 2 2006.175.08:06:01.10#ibcon#read 5, iclass 36, count 2 2006.175.08:06:01.10#ibcon#about to read 6, iclass 36, count 2 2006.175.08:06:01.10#ibcon#read 6, iclass 36, count 2 2006.175.08:06:01.10#ibcon#end of sib2, iclass 36, count 2 2006.175.08:06:01.10#ibcon#*after write, iclass 36, count 2 2006.175.08:06:01.10#ibcon#*before return 0, iclass 36, count 2 2006.175.08:06:01.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:06:01.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:06:01.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.08:06:01.10#ibcon#ireg 7 cls_cnt 0 2006.175.08:06:01.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:06:01.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:06:01.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:06:01.22#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:06:01.22#ibcon#first serial, iclass 36, count 0 2006.175.08:06:01.22#ibcon#enter sib2, iclass 36, count 0 2006.175.08:06:01.22#ibcon#flushed, iclass 36, count 0 2006.175.08:06:01.22#ibcon#about to write, iclass 36, count 0 2006.175.08:06:01.22#ibcon#wrote, iclass 36, count 0 2006.175.08:06:01.22#ibcon#about to read 3, iclass 36, count 0 2006.175.08:06:01.24#ibcon#read 3, iclass 36, count 0 2006.175.08:06:01.24#ibcon#about to read 4, iclass 36, count 0 2006.175.08:06:01.24#ibcon#read 4, iclass 36, count 0 2006.175.08:06:01.24#ibcon#about to read 5, iclass 36, count 0 2006.175.08:06:01.24#ibcon#read 5, iclass 36, count 0 2006.175.08:06:01.24#ibcon#about to read 6, iclass 36, count 0 2006.175.08:06:01.24#ibcon#read 6, iclass 36, count 0 2006.175.08:06:01.24#ibcon#end of sib2, iclass 36, count 0 2006.175.08:06:01.24#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:06:01.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:06:01.24#ibcon#[27=USB\r\n] 2006.175.08:06:01.24#ibcon#*before write, iclass 36, count 0 2006.175.08:06:01.24#ibcon#enter sib2, iclass 36, count 0 2006.175.08:06:01.24#ibcon#flushed, iclass 36, count 0 2006.175.08:06:01.24#ibcon#about to write, iclass 36, count 0 2006.175.08:06:01.24#ibcon#wrote, iclass 36, count 0 2006.175.08:06:01.24#ibcon#about to read 3, iclass 36, count 0 2006.175.08:06:01.27#ibcon#read 3, iclass 36, count 0 2006.175.08:06:01.27#ibcon#about to read 4, iclass 36, count 0 2006.175.08:06:01.27#ibcon#read 4, iclass 36, count 0 2006.175.08:06:01.27#ibcon#about to read 5, iclass 36, count 0 2006.175.08:06:01.27#ibcon#read 5, iclass 36, count 0 2006.175.08:06:01.27#ibcon#about to read 6, iclass 36, count 0 2006.175.08:06:01.27#ibcon#read 6, iclass 36, count 0 2006.175.08:06:01.27#ibcon#end of sib2, iclass 36, count 0 2006.175.08:06:01.27#ibcon#*after write, iclass 36, count 0 2006.175.08:06:01.27#ibcon#*before return 0, iclass 36, count 0 2006.175.08:06:01.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:06:01.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:06:01.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:06:01.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:06:01.27$vc4f8/vblo=3,656.99 2006.175.08:06:01.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.08:06:01.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.08:06:01.27#ibcon#ireg 17 cls_cnt 0 2006.175.08:06:01.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:06:01.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:06:01.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:06:01.27#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:06:01.27#ibcon#first serial, iclass 38, count 0 2006.175.08:06:01.27#ibcon#enter sib2, iclass 38, count 0 2006.175.08:06:01.27#ibcon#flushed, iclass 38, count 0 2006.175.08:06:01.27#ibcon#about to write, iclass 38, count 0 2006.175.08:06:01.27#ibcon#wrote, iclass 38, count 0 2006.175.08:06:01.27#ibcon#about to read 3, iclass 38, count 0 2006.175.08:06:01.29#ibcon#read 3, iclass 38, count 0 2006.175.08:06:01.29#ibcon#about to read 4, iclass 38, count 0 2006.175.08:06:01.29#ibcon#read 4, iclass 38, count 0 2006.175.08:06:01.29#ibcon#about to read 5, iclass 38, count 0 2006.175.08:06:01.29#ibcon#read 5, iclass 38, count 0 2006.175.08:06:01.29#ibcon#about to read 6, iclass 38, count 0 2006.175.08:06:01.29#ibcon#read 6, iclass 38, count 0 2006.175.08:06:01.29#ibcon#end of sib2, iclass 38, count 0 2006.175.08:06:01.29#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:06:01.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:06:01.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:06:01.29#ibcon#*before write, iclass 38, count 0 2006.175.08:06:01.29#ibcon#enter sib2, iclass 38, count 0 2006.175.08:06:01.29#ibcon#flushed, iclass 38, count 0 2006.175.08:06:01.29#ibcon#about to write, iclass 38, count 0 2006.175.08:06:01.29#ibcon#wrote, iclass 38, count 0 2006.175.08:06:01.29#ibcon#about to read 3, iclass 38, count 0 2006.175.08:06:01.33#ibcon#read 3, iclass 38, count 0 2006.175.08:06:01.33#ibcon#about to read 4, iclass 38, count 0 2006.175.08:06:01.33#ibcon#read 4, iclass 38, count 0 2006.175.08:06:01.33#ibcon#about to read 5, iclass 38, count 0 2006.175.08:06:01.33#ibcon#read 5, iclass 38, count 0 2006.175.08:06:01.33#ibcon#about to read 6, iclass 38, count 0 2006.175.08:06:01.33#ibcon#read 6, iclass 38, count 0 2006.175.08:06:01.33#ibcon#end of sib2, iclass 38, count 0 2006.175.08:06:01.33#ibcon#*after write, iclass 38, count 0 2006.175.08:06:01.33#ibcon#*before return 0, iclass 38, count 0 2006.175.08:06:01.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:06:01.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:06:01.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:06:01.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:06:01.33$vc4f8/vb=3,4 2006.175.08:06:01.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.08:06:01.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.08:06:01.33#ibcon#ireg 11 cls_cnt 2 2006.175.08:06:01.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:06:01.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:06:01.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:06:01.39#ibcon#enter wrdev, iclass 40, count 2 2006.175.08:06:01.39#ibcon#first serial, iclass 40, count 2 2006.175.08:06:01.39#ibcon#enter sib2, iclass 40, count 2 2006.175.08:06:01.39#ibcon#flushed, iclass 40, count 2 2006.175.08:06:01.39#ibcon#about to write, iclass 40, count 2 2006.175.08:06:01.39#ibcon#wrote, iclass 40, count 2 2006.175.08:06:01.39#ibcon#about to read 3, iclass 40, count 2 2006.175.08:06:01.41#ibcon#read 3, iclass 40, count 2 2006.175.08:06:01.41#ibcon#about to read 4, iclass 40, count 2 2006.175.08:06:01.41#ibcon#read 4, iclass 40, count 2 2006.175.08:06:01.41#ibcon#about to read 5, iclass 40, count 2 2006.175.08:06:01.41#ibcon#read 5, iclass 40, count 2 2006.175.08:06:01.41#ibcon#about to read 6, iclass 40, count 2 2006.175.08:06:01.41#ibcon#read 6, iclass 40, count 2 2006.175.08:06:01.41#ibcon#end of sib2, iclass 40, count 2 2006.175.08:06:01.41#ibcon#*mode == 0, iclass 40, count 2 2006.175.08:06:01.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.08:06:01.41#ibcon#[27=AT03-04\r\n] 2006.175.08:06:01.41#ibcon#*before write, iclass 40, count 2 2006.175.08:06:01.41#ibcon#enter sib2, iclass 40, count 2 2006.175.08:06:01.41#ibcon#flushed, iclass 40, count 2 2006.175.08:06:01.41#ibcon#about to write, iclass 40, count 2 2006.175.08:06:01.41#ibcon#wrote, iclass 40, count 2 2006.175.08:06:01.41#ibcon#about to read 3, iclass 40, count 2 2006.175.08:06:01.44#ibcon#read 3, iclass 40, count 2 2006.175.08:06:01.44#ibcon#about to read 4, iclass 40, count 2 2006.175.08:06:01.44#ibcon#read 4, iclass 40, count 2 2006.175.08:06:01.44#ibcon#about to read 5, iclass 40, count 2 2006.175.08:06:01.44#ibcon#read 5, iclass 40, count 2 2006.175.08:06:01.44#ibcon#about to read 6, iclass 40, count 2 2006.175.08:06:01.44#ibcon#read 6, iclass 40, count 2 2006.175.08:06:01.44#ibcon#end of sib2, iclass 40, count 2 2006.175.08:06:01.44#ibcon#*after write, iclass 40, count 2 2006.175.08:06:01.44#ibcon#*before return 0, iclass 40, count 2 2006.175.08:06:01.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:06:01.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:06:01.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.08:06:01.44#ibcon#ireg 7 cls_cnt 0 2006.175.08:06:01.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:06:01.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:06:01.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:06:01.56#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:06:01.56#ibcon#first serial, iclass 40, count 0 2006.175.08:06:01.56#ibcon#enter sib2, iclass 40, count 0 2006.175.08:06:01.56#ibcon#flushed, iclass 40, count 0 2006.175.08:06:01.56#ibcon#about to write, iclass 40, count 0 2006.175.08:06:01.56#ibcon#wrote, iclass 40, count 0 2006.175.08:06:01.56#ibcon#about to read 3, iclass 40, count 0 2006.175.08:06:01.58#ibcon#read 3, iclass 40, count 0 2006.175.08:06:01.58#ibcon#about to read 4, iclass 40, count 0 2006.175.08:06:01.58#ibcon#read 4, iclass 40, count 0 2006.175.08:06:01.58#ibcon#about to read 5, iclass 40, count 0 2006.175.08:06:01.58#ibcon#read 5, iclass 40, count 0 2006.175.08:06:01.58#ibcon#about to read 6, iclass 40, count 0 2006.175.08:06:01.58#ibcon#read 6, iclass 40, count 0 2006.175.08:06:01.58#ibcon#end of sib2, iclass 40, count 0 2006.175.08:06:01.58#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:06:01.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:06:01.58#ibcon#[27=USB\r\n] 2006.175.08:06:01.58#ibcon#*before write, iclass 40, count 0 2006.175.08:06:01.58#ibcon#enter sib2, iclass 40, count 0 2006.175.08:06:01.58#ibcon#flushed, iclass 40, count 0 2006.175.08:06:01.58#ibcon#about to write, iclass 40, count 0 2006.175.08:06:01.58#ibcon#wrote, iclass 40, count 0 2006.175.08:06:01.58#ibcon#about to read 3, iclass 40, count 0 2006.175.08:06:01.61#ibcon#read 3, iclass 40, count 0 2006.175.08:06:01.61#ibcon#about to read 4, iclass 40, count 0 2006.175.08:06:01.61#ibcon#read 4, iclass 40, count 0 2006.175.08:06:01.61#ibcon#about to read 5, iclass 40, count 0 2006.175.08:06:01.61#ibcon#read 5, iclass 40, count 0 2006.175.08:06:01.61#ibcon#about to read 6, iclass 40, count 0 2006.175.08:06:01.61#ibcon#read 6, iclass 40, count 0 2006.175.08:06:01.61#ibcon#end of sib2, iclass 40, count 0 2006.175.08:06:01.61#ibcon#*after write, iclass 40, count 0 2006.175.08:06:01.61#ibcon#*before return 0, iclass 40, count 0 2006.175.08:06:01.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:06:01.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:06:01.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:06:01.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:06:01.61$vc4f8/vblo=4,712.99 2006.175.08:06:01.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.08:06:01.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.08:06:01.61#ibcon#ireg 17 cls_cnt 0 2006.175.08:06:01.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:06:01.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:06:01.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:06:01.61#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:06:01.61#ibcon#first serial, iclass 4, count 0 2006.175.08:06:01.61#ibcon#enter sib2, iclass 4, count 0 2006.175.08:06:01.61#ibcon#flushed, iclass 4, count 0 2006.175.08:06:01.61#ibcon#about to write, iclass 4, count 0 2006.175.08:06:01.61#ibcon#wrote, iclass 4, count 0 2006.175.08:06:01.61#ibcon#about to read 3, iclass 4, count 0 2006.175.08:06:01.63#ibcon#read 3, iclass 4, count 0 2006.175.08:06:01.63#ibcon#about to read 4, iclass 4, count 0 2006.175.08:06:01.63#ibcon#read 4, iclass 4, count 0 2006.175.08:06:01.63#ibcon#about to read 5, iclass 4, count 0 2006.175.08:06:01.63#ibcon#read 5, iclass 4, count 0 2006.175.08:06:01.63#ibcon#about to read 6, iclass 4, count 0 2006.175.08:06:01.63#ibcon#read 6, iclass 4, count 0 2006.175.08:06:01.63#ibcon#end of sib2, iclass 4, count 0 2006.175.08:06:01.63#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:06:01.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:06:01.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:06:01.63#ibcon#*before write, iclass 4, count 0 2006.175.08:06:01.63#ibcon#enter sib2, iclass 4, count 0 2006.175.08:06:01.63#ibcon#flushed, iclass 4, count 0 2006.175.08:06:01.63#ibcon#about to write, iclass 4, count 0 2006.175.08:06:01.63#ibcon#wrote, iclass 4, count 0 2006.175.08:06:01.63#ibcon#about to read 3, iclass 4, count 0 2006.175.08:06:01.67#ibcon#read 3, iclass 4, count 0 2006.175.08:06:01.67#ibcon#about to read 4, iclass 4, count 0 2006.175.08:06:01.67#ibcon#read 4, iclass 4, count 0 2006.175.08:06:01.67#ibcon#about to read 5, iclass 4, count 0 2006.175.08:06:01.67#ibcon#read 5, iclass 4, count 0 2006.175.08:06:01.67#ibcon#about to read 6, iclass 4, count 0 2006.175.08:06:01.67#ibcon#read 6, iclass 4, count 0 2006.175.08:06:01.67#ibcon#end of sib2, iclass 4, count 0 2006.175.08:06:01.67#ibcon#*after write, iclass 4, count 0 2006.175.08:06:01.67#ibcon#*before return 0, iclass 4, count 0 2006.175.08:06:01.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:06:01.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:06:01.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:06:01.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:06:01.67$vc4f8/vb=4,4 2006.175.08:06:01.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.08:06:01.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.08:06:01.67#ibcon#ireg 11 cls_cnt 2 2006.175.08:06:01.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:06:01.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:06:01.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:06:01.73#ibcon#enter wrdev, iclass 6, count 2 2006.175.08:06:01.73#ibcon#first serial, iclass 6, count 2 2006.175.08:06:01.73#ibcon#enter sib2, iclass 6, count 2 2006.175.08:06:01.73#ibcon#flushed, iclass 6, count 2 2006.175.08:06:01.73#ibcon#about to write, iclass 6, count 2 2006.175.08:06:01.73#ibcon#wrote, iclass 6, count 2 2006.175.08:06:01.73#ibcon#about to read 3, iclass 6, count 2 2006.175.08:06:01.75#ibcon#read 3, iclass 6, count 2 2006.175.08:06:01.75#ibcon#about to read 4, iclass 6, count 2 2006.175.08:06:01.75#ibcon#read 4, iclass 6, count 2 2006.175.08:06:01.75#ibcon#about to read 5, iclass 6, count 2 2006.175.08:06:01.75#ibcon#read 5, iclass 6, count 2 2006.175.08:06:01.75#ibcon#about to read 6, iclass 6, count 2 2006.175.08:06:01.75#ibcon#read 6, iclass 6, count 2 2006.175.08:06:01.75#ibcon#end of sib2, iclass 6, count 2 2006.175.08:06:01.75#ibcon#*mode == 0, iclass 6, count 2 2006.175.08:06:01.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.08:06:01.75#ibcon#[27=AT04-04\r\n] 2006.175.08:06:01.75#ibcon#*before write, iclass 6, count 2 2006.175.08:06:01.75#ibcon#enter sib2, iclass 6, count 2 2006.175.08:06:01.75#ibcon#flushed, iclass 6, count 2 2006.175.08:06:01.75#ibcon#about to write, iclass 6, count 2 2006.175.08:06:01.75#ibcon#wrote, iclass 6, count 2 2006.175.08:06:01.75#ibcon#about to read 3, iclass 6, count 2 2006.175.08:06:01.78#ibcon#read 3, iclass 6, count 2 2006.175.08:06:01.78#ibcon#about to read 4, iclass 6, count 2 2006.175.08:06:01.78#ibcon#read 4, iclass 6, count 2 2006.175.08:06:01.78#ibcon#about to read 5, iclass 6, count 2 2006.175.08:06:01.78#ibcon#read 5, iclass 6, count 2 2006.175.08:06:01.78#ibcon#about to read 6, iclass 6, count 2 2006.175.08:06:01.78#ibcon#read 6, iclass 6, count 2 2006.175.08:06:01.78#ibcon#end of sib2, iclass 6, count 2 2006.175.08:06:01.78#ibcon#*after write, iclass 6, count 2 2006.175.08:06:01.78#ibcon#*before return 0, iclass 6, count 2 2006.175.08:06:01.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:06:01.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:06:01.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.08:06:01.78#ibcon#ireg 7 cls_cnt 0 2006.175.08:06:01.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:06:01.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:06:01.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:06:01.90#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:06:01.90#ibcon#first serial, iclass 6, count 0 2006.175.08:06:01.90#ibcon#enter sib2, iclass 6, count 0 2006.175.08:06:01.90#ibcon#flushed, iclass 6, count 0 2006.175.08:06:01.90#ibcon#about to write, iclass 6, count 0 2006.175.08:06:01.90#ibcon#wrote, iclass 6, count 0 2006.175.08:06:01.90#ibcon#about to read 3, iclass 6, count 0 2006.175.08:06:01.92#ibcon#read 3, iclass 6, count 0 2006.175.08:06:01.92#ibcon#about to read 4, iclass 6, count 0 2006.175.08:06:01.92#ibcon#read 4, iclass 6, count 0 2006.175.08:06:01.92#ibcon#about to read 5, iclass 6, count 0 2006.175.08:06:01.92#ibcon#read 5, iclass 6, count 0 2006.175.08:06:01.92#ibcon#about to read 6, iclass 6, count 0 2006.175.08:06:01.92#ibcon#read 6, iclass 6, count 0 2006.175.08:06:01.92#ibcon#end of sib2, iclass 6, count 0 2006.175.08:06:01.92#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:06:01.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:06:01.92#ibcon#[27=USB\r\n] 2006.175.08:06:01.92#ibcon#*before write, iclass 6, count 0 2006.175.08:06:01.92#ibcon#enter sib2, iclass 6, count 0 2006.175.08:06:01.92#ibcon#flushed, iclass 6, count 0 2006.175.08:06:01.92#ibcon#about to write, iclass 6, count 0 2006.175.08:06:01.92#ibcon#wrote, iclass 6, count 0 2006.175.08:06:01.92#ibcon#about to read 3, iclass 6, count 0 2006.175.08:06:01.95#ibcon#read 3, iclass 6, count 0 2006.175.08:06:01.95#ibcon#about to read 4, iclass 6, count 0 2006.175.08:06:01.95#ibcon#read 4, iclass 6, count 0 2006.175.08:06:01.95#ibcon#about to read 5, iclass 6, count 0 2006.175.08:06:01.95#ibcon#read 5, iclass 6, count 0 2006.175.08:06:01.95#ibcon#about to read 6, iclass 6, count 0 2006.175.08:06:01.95#ibcon#read 6, iclass 6, count 0 2006.175.08:06:01.95#ibcon#end of sib2, iclass 6, count 0 2006.175.08:06:01.95#ibcon#*after write, iclass 6, count 0 2006.175.08:06:01.95#ibcon#*before return 0, iclass 6, count 0 2006.175.08:06:01.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:06:01.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:06:01.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:06:01.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:06:01.95$vc4f8/vblo=5,744.99 2006.175.08:06:01.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.08:06:01.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.08:06:01.95#ibcon#ireg 17 cls_cnt 0 2006.175.08:06:01.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:06:01.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:06:01.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:06:01.95#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:06:01.95#ibcon#first serial, iclass 10, count 0 2006.175.08:06:01.95#ibcon#enter sib2, iclass 10, count 0 2006.175.08:06:01.95#ibcon#flushed, iclass 10, count 0 2006.175.08:06:01.95#ibcon#about to write, iclass 10, count 0 2006.175.08:06:01.95#ibcon#wrote, iclass 10, count 0 2006.175.08:06:01.95#ibcon#about to read 3, iclass 10, count 0 2006.175.08:06:01.97#ibcon#read 3, iclass 10, count 0 2006.175.08:06:01.97#ibcon#about to read 4, iclass 10, count 0 2006.175.08:06:01.97#ibcon#read 4, iclass 10, count 0 2006.175.08:06:01.97#ibcon#about to read 5, iclass 10, count 0 2006.175.08:06:01.97#ibcon#read 5, iclass 10, count 0 2006.175.08:06:01.97#ibcon#about to read 6, iclass 10, count 0 2006.175.08:06:01.97#ibcon#read 6, iclass 10, count 0 2006.175.08:06:01.97#ibcon#end of sib2, iclass 10, count 0 2006.175.08:06:01.97#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:06:01.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:06:01.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:06:01.97#ibcon#*before write, iclass 10, count 0 2006.175.08:06:01.97#ibcon#enter sib2, iclass 10, count 0 2006.175.08:06:01.97#ibcon#flushed, iclass 10, count 0 2006.175.08:06:01.97#ibcon#about to write, iclass 10, count 0 2006.175.08:06:01.97#ibcon#wrote, iclass 10, count 0 2006.175.08:06:01.97#ibcon#about to read 3, iclass 10, count 0 2006.175.08:06:02.01#ibcon#read 3, iclass 10, count 0 2006.175.08:06:02.01#ibcon#about to read 4, iclass 10, count 0 2006.175.08:06:02.01#ibcon#read 4, iclass 10, count 0 2006.175.08:06:02.01#ibcon#about to read 5, iclass 10, count 0 2006.175.08:06:02.01#ibcon#read 5, iclass 10, count 0 2006.175.08:06:02.01#ibcon#about to read 6, iclass 10, count 0 2006.175.08:06:02.01#ibcon#read 6, iclass 10, count 0 2006.175.08:06:02.01#ibcon#end of sib2, iclass 10, count 0 2006.175.08:06:02.01#ibcon#*after write, iclass 10, count 0 2006.175.08:06:02.01#ibcon#*before return 0, iclass 10, count 0 2006.175.08:06:02.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:06:02.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:06:02.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:06:02.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:06:02.01$vc4f8/vb=5,4 2006.175.08:06:02.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.08:06:02.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.08:06:02.01#ibcon#ireg 11 cls_cnt 2 2006.175.08:06:02.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:06:02.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:06:02.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:06:02.07#ibcon#enter wrdev, iclass 12, count 2 2006.175.08:06:02.07#ibcon#first serial, iclass 12, count 2 2006.175.08:06:02.07#ibcon#enter sib2, iclass 12, count 2 2006.175.08:06:02.07#ibcon#flushed, iclass 12, count 2 2006.175.08:06:02.07#ibcon#about to write, iclass 12, count 2 2006.175.08:06:02.07#ibcon#wrote, iclass 12, count 2 2006.175.08:06:02.07#ibcon#about to read 3, iclass 12, count 2 2006.175.08:06:02.09#ibcon#read 3, iclass 12, count 2 2006.175.08:06:02.09#ibcon#about to read 4, iclass 12, count 2 2006.175.08:06:02.09#ibcon#read 4, iclass 12, count 2 2006.175.08:06:02.09#ibcon#about to read 5, iclass 12, count 2 2006.175.08:06:02.09#ibcon#read 5, iclass 12, count 2 2006.175.08:06:02.09#ibcon#about to read 6, iclass 12, count 2 2006.175.08:06:02.09#ibcon#read 6, iclass 12, count 2 2006.175.08:06:02.09#ibcon#end of sib2, iclass 12, count 2 2006.175.08:06:02.09#ibcon#*mode == 0, iclass 12, count 2 2006.175.08:06:02.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.08:06:02.09#ibcon#[27=AT05-04\r\n] 2006.175.08:06:02.09#ibcon#*before write, iclass 12, count 2 2006.175.08:06:02.09#ibcon#enter sib2, iclass 12, count 2 2006.175.08:06:02.09#ibcon#flushed, iclass 12, count 2 2006.175.08:06:02.09#ibcon#about to write, iclass 12, count 2 2006.175.08:06:02.09#ibcon#wrote, iclass 12, count 2 2006.175.08:06:02.09#ibcon#about to read 3, iclass 12, count 2 2006.175.08:06:02.12#ibcon#read 3, iclass 12, count 2 2006.175.08:06:02.12#ibcon#about to read 4, iclass 12, count 2 2006.175.08:06:02.12#ibcon#read 4, iclass 12, count 2 2006.175.08:06:02.12#ibcon#about to read 5, iclass 12, count 2 2006.175.08:06:02.12#ibcon#read 5, iclass 12, count 2 2006.175.08:06:02.12#ibcon#about to read 6, iclass 12, count 2 2006.175.08:06:02.12#ibcon#read 6, iclass 12, count 2 2006.175.08:06:02.12#ibcon#end of sib2, iclass 12, count 2 2006.175.08:06:02.12#ibcon#*after write, iclass 12, count 2 2006.175.08:06:02.12#ibcon#*before return 0, iclass 12, count 2 2006.175.08:06:02.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:06:02.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:06:02.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.08:06:02.12#ibcon#ireg 7 cls_cnt 0 2006.175.08:06:02.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:06:02.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:06:02.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:06:02.24#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:06:02.24#ibcon#first serial, iclass 12, count 0 2006.175.08:06:02.24#ibcon#enter sib2, iclass 12, count 0 2006.175.08:06:02.24#ibcon#flushed, iclass 12, count 0 2006.175.08:06:02.24#ibcon#about to write, iclass 12, count 0 2006.175.08:06:02.24#ibcon#wrote, iclass 12, count 0 2006.175.08:06:02.24#ibcon#about to read 3, iclass 12, count 0 2006.175.08:06:02.26#ibcon#read 3, iclass 12, count 0 2006.175.08:06:02.26#ibcon#about to read 4, iclass 12, count 0 2006.175.08:06:02.26#ibcon#read 4, iclass 12, count 0 2006.175.08:06:02.26#ibcon#about to read 5, iclass 12, count 0 2006.175.08:06:02.26#ibcon#read 5, iclass 12, count 0 2006.175.08:06:02.26#ibcon#about to read 6, iclass 12, count 0 2006.175.08:06:02.26#ibcon#read 6, iclass 12, count 0 2006.175.08:06:02.26#ibcon#end of sib2, iclass 12, count 0 2006.175.08:06:02.26#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:06:02.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:06:02.26#ibcon#[27=USB\r\n] 2006.175.08:06:02.26#ibcon#*before write, iclass 12, count 0 2006.175.08:06:02.26#ibcon#enter sib2, iclass 12, count 0 2006.175.08:06:02.26#ibcon#flushed, iclass 12, count 0 2006.175.08:06:02.26#ibcon#about to write, iclass 12, count 0 2006.175.08:06:02.26#ibcon#wrote, iclass 12, count 0 2006.175.08:06:02.26#ibcon#about to read 3, iclass 12, count 0 2006.175.08:06:02.29#ibcon#read 3, iclass 12, count 0 2006.175.08:06:02.29#ibcon#about to read 4, iclass 12, count 0 2006.175.08:06:02.29#ibcon#read 4, iclass 12, count 0 2006.175.08:06:02.29#ibcon#about to read 5, iclass 12, count 0 2006.175.08:06:02.29#ibcon#read 5, iclass 12, count 0 2006.175.08:06:02.29#ibcon#about to read 6, iclass 12, count 0 2006.175.08:06:02.29#ibcon#read 6, iclass 12, count 0 2006.175.08:06:02.29#ibcon#end of sib2, iclass 12, count 0 2006.175.08:06:02.29#ibcon#*after write, iclass 12, count 0 2006.175.08:06:02.29#ibcon#*before return 0, iclass 12, count 0 2006.175.08:06:02.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:06:02.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:06:02.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:06:02.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:06:02.29$vc4f8/vblo=6,752.99 2006.175.08:06:02.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.08:06:02.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.08:06:02.29#ibcon#ireg 17 cls_cnt 0 2006.175.08:06:02.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:06:02.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:06:02.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:06:02.29#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:06:02.29#ibcon#first serial, iclass 14, count 0 2006.175.08:06:02.29#ibcon#enter sib2, iclass 14, count 0 2006.175.08:06:02.29#ibcon#flushed, iclass 14, count 0 2006.175.08:06:02.29#ibcon#about to write, iclass 14, count 0 2006.175.08:06:02.29#ibcon#wrote, iclass 14, count 0 2006.175.08:06:02.29#ibcon#about to read 3, iclass 14, count 0 2006.175.08:06:02.31#ibcon#read 3, iclass 14, count 0 2006.175.08:06:02.31#ibcon#about to read 4, iclass 14, count 0 2006.175.08:06:02.31#ibcon#read 4, iclass 14, count 0 2006.175.08:06:02.31#ibcon#about to read 5, iclass 14, count 0 2006.175.08:06:02.31#ibcon#read 5, iclass 14, count 0 2006.175.08:06:02.31#ibcon#about to read 6, iclass 14, count 0 2006.175.08:06:02.31#ibcon#read 6, iclass 14, count 0 2006.175.08:06:02.31#ibcon#end of sib2, iclass 14, count 0 2006.175.08:06:02.31#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:06:02.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:06:02.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:06:02.31#ibcon#*before write, iclass 14, count 0 2006.175.08:06:02.31#ibcon#enter sib2, iclass 14, count 0 2006.175.08:06:02.31#ibcon#flushed, iclass 14, count 0 2006.175.08:06:02.31#ibcon#about to write, iclass 14, count 0 2006.175.08:06:02.31#ibcon#wrote, iclass 14, count 0 2006.175.08:06:02.31#ibcon#about to read 3, iclass 14, count 0 2006.175.08:06:02.35#ibcon#read 3, iclass 14, count 0 2006.175.08:06:02.35#ibcon#about to read 4, iclass 14, count 0 2006.175.08:06:02.35#ibcon#read 4, iclass 14, count 0 2006.175.08:06:02.35#ibcon#about to read 5, iclass 14, count 0 2006.175.08:06:02.35#ibcon#read 5, iclass 14, count 0 2006.175.08:06:02.35#ibcon#about to read 6, iclass 14, count 0 2006.175.08:06:02.35#ibcon#read 6, iclass 14, count 0 2006.175.08:06:02.35#ibcon#end of sib2, iclass 14, count 0 2006.175.08:06:02.35#ibcon#*after write, iclass 14, count 0 2006.175.08:06:02.35#ibcon#*before return 0, iclass 14, count 0 2006.175.08:06:02.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:06:02.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:06:02.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:06:02.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:06:02.35$vc4f8/vb=6,4 2006.175.08:06:02.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.08:06:02.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.08:06:02.35#ibcon#ireg 11 cls_cnt 2 2006.175.08:06:02.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:06:02.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:06:02.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:06:02.41#ibcon#enter wrdev, iclass 16, count 2 2006.175.08:06:02.41#ibcon#first serial, iclass 16, count 2 2006.175.08:06:02.41#ibcon#enter sib2, iclass 16, count 2 2006.175.08:06:02.41#ibcon#flushed, iclass 16, count 2 2006.175.08:06:02.41#ibcon#about to write, iclass 16, count 2 2006.175.08:06:02.41#ibcon#wrote, iclass 16, count 2 2006.175.08:06:02.41#ibcon#about to read 3, iclass 16, count 2 2006.175.08:06:02.43#ibcon#read 3, iclass 16, count 2 2006.175.08:06:02.43#ibcon#about to read 4, iclass 16, count 2 2006.175.08:06:02.43#ibcon#read 4, iclass 16, count 2 2006.175.08:06:02.43#ibcon#about to read 5, iclass 16, count 2 2006.175.08:06:02.43#ibcon#read 5, iclass 16, count 2 2006.175.08:06:02.43#ibcon#about to read 6, iclass 16, count 2 2006.175.08:06:02.43#ibcon#read 6, iclass 16, count 2 2006.175.08:06:02.43#ibcon#end of sib2, iclass 16, count 2 2006.175.08:06:02.43#ibcon#*mode == 0, iclass 16, count 2 2006.175.08:06:02.43#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.08:06:02.43#ibcon#[27=AT06-04\r\n] 2006.175.08:06:02.43#ibcon#*before write, iclass 16, count 2 2006.175.08:06:02.43#ibcon#enter sib2, iclass 16, count 2 2006.175.08:06:02.43#ibcon#flushed, iclass 16, count 2 2006.175.08:06:02.43#ibcon#about to write, iclass 16, count 2 2006.175.08:06:02.43#ibcon#wrote, iclass 16, count 2 2006.175.08:06:02.43#ibcon#about to read 3, iclass 16, count 2 2006.175.08:06:02.46#ibcon#read 3, iclass 16, count 2 2006.175.08:06:02.46#ibcon#about to read 4, iclass 16, count 2 2006.175.08:06:02.46#ibcon#read 4, iclass 16, count 2 2006.175.08:06:02.46#ibcon#about to read 5, iclass 16, count 2 2006.175.08:06:02.46#ibcon#read 5, iclass 16, count 2 2006.175.08:06:02.46#ibcon#about to read 6, iclass 16, count 2 2006.175.08:06:02.46#ibcon#read 6, iclass 16, count 2 2006.175.08:06:02.46#ibcon#end of sib2, iclass 16, count 2 2006.175.08:06:02.46#ibcon#*after write, iclass 16, count 2 2006.175.08:06:02.46#ibcon#*before return 0, iclass 16, count 2 2006.175.08:06:02.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:06:02.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:06:02.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.08:06:02.46#ibcon#ireg 7 cls_cnt 0 2006.175.08:06:02.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:06:02.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:06:02.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:06:02.58#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:06:02.58#ibcon#first serial, iclass 16, count 0 2006.175.08:06:02.58#ibcon#enter sib2, iclass 16, count 0 2006.175.08:06:02.58#ibcon#flushed, iclass 16, count 0 2006.175.08:06:02.58#ibcon#about to write, iclass 16, count 0 2006.175.08:06:02.58#ibcon#wrote, iclass 16, count 0 2006.175.08:06:02.58#ibcon#about to read 3, iclass 16, count 0 2006.175.08:06:02.60#ibcon#read 3, iclass 16, count 0 2006.175.08:06:02.60#ibcon#about to read 4, iclass 16, count 0 2006.175.08:06:02.60#ibcon#read 4, iclass 16, count 0 2006.175.08:06:02.60#ibcon#about to read 5, iclass 16, count 0 2006.175.08:06:02.60#ibcon#read 5, iclass 16, count 0 2006.175.08:06:02.60#ibcon#about to read 6, iclass 16, count 0 2006.175.08:06:02.60#ibcon#read 6, iclass 16, count 0 2006.175.08:06:02.60#ibcon#end of sib2, iclass 16, count 0 2006.175.08:06:02.60#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:06:02.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:06:02.60#ibcon#[27=USB\r\n] 2006.175.08:06:02.60#ibcon#*before write, iclass 16, count 0 2006.175.08:06:02.60#ibcon#enter sib2, iclass 16, count 0 2006.175.08:06:02.60#ibcon#flushed, iclass 16, count 0 2006.175.08:06:02.60#ibcon#about to write, iclass 16, count 0 2006.175.08:06:02.60#ibcon#wrote, iclass 16, count 0 2006.175.08:06:02.60#ibcon#about to read 3, iclass 16, count 0 2006.175.08:06:02.63#ibcon#read 3, iclass 16, count 0 2006.175.08:06:02.63#ibcon#about to read 4, iclass 16, count 0 2006.175.08:06:02.63#ibcon#read 4, iclass 16, count 0 2006.175.08:06:02.63#ibcon#about to read 5, iclass 16, count 0 2006.175.08:06:02.63#ibcon#read 5, iclass 16, count 0 2006.175.08:06:02.63#ibcon#about to read 6, iclass 16, count 0 2006.175.08:06:02.63#ibcon#read 6, iclass 16, count 0 2006.175.08:06:02.63#ibcon#end of sib2, iclass 16, count 0 2006.175.08:06:02.63#ibcon#*after write, iclass 16, count 0 2006.175.08:06:02.63#ibcon#*before return 0, iclass 16, count 0 2006.175.08:06:02.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:06:02.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:06:02.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:06:02.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:06:02.63$vc4f8/vabw=wide 2006.175.08:06:02.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.08:06:02.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.08:06:02.63#ibcon#ireg 8 cls_cnt 0 2006.175.08:06:02.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:06:02.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:06:02.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:06:02.63#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:06:02.63#ibcon#first serial, iclass 18, count 0 2006.175.08:06:02.63#ibcon#enter sib2, iclass 18, count 0 2006.175.08:06:02.63#ibcon#flushed, iclass 18, count 0 2006.175.08:06:02.63#ibcon#about to write, iclass 18, count 0 2006.175.08:06:02.63#ibcon#wrote, iclass 18, count 0 2006.175.08:06:02.63#ibcon#about to read 3, iclass 18, count 0 2006.175.08:06:02.65#ibcon#read 3, iclass 18, count 0 2006.175.08:06:02.65#ibcon#about to read 4, iclass 18, count 0 2006.175.08:06:02.65#ibcon#read 4, iclass 18, count 0 2006.175.08:06:02.65#ibcon#about to read 5, iclass 18, count 0 2006.175.08:06:02.65#ibcon#read 5, iclass 18, count 0 2006.175.08:06:02.65#ibcon#about to read 6, iclass 18, count 0 2006.175.08:06:02.65#ibcon#read 6, iclass 18, count 0 2006.175.08:06:02.65#ibcon#end of sib2, iclass 18, count 0 2006.175.08:06:02.65#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:06:02.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:06:02.65#ibcon#[25=BW32\r\n] 2006.175.08:06:02.65#ibcon#*before write, iclass 18, count 0 2006.175.08:06:02.65#ibcon#enter sib2, iclass 18, count 0 2006.175.08:06:02.65#ibcon#flushed, iclass 18, count 0 2006.175.08:06:02.65#ibcon#about to write, iclass 18, count 0 2006.175.08:06:02.65#ibcon#wrote, iclass 18, count 0 2006.175.08:06:02.65#ibcon#about to read 3, iclass 18, count 0 2006.175.08:06:02.68#ibcon#read 3, iclass 18, count 0 2006.175.08:06:02.68#ibcon#about to read 4, iclass 18, count 0 2006.175.08:06:02.68#ibcon#read 4, iclass 18, count 0 2006.175.08:06:02.68#ibcon#about to read 5, iclass 18, count 0 2006.175.08:06:02.68#ibcon#read 5, iclass 18, count 0 2006.175.08:06:02.68#ibcon#about to read 6, iclass 18, count 0 2006.175.08:06:02.68#ibcon#read 6, iclass 18, count 0 2006.175.08:06:02.68#ibcon#end of sib2, iclass 18, count 0 2006.175.08:06:02.68#ibcon#*after write, iclass 18, count 0 2006.175.08:06:02.68#ibcon#*before return 0, iclass 18, count 0 2006.175.08:06:02.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:06:02.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:06:02.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:06:02.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:06:02.68$vc4f8/vbbw=wide 2006.175.08:06:02.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.08:06:02.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.08:06:02.68#ibcon#ireg 8 cls_cnt 0 2006.175.08:06:02.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:06:02.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:06:02.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:06:02.75#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:06:02.75#ibcon#first serial, iclass 20, count 0 2006.175.08:06:02.75#ibcon#enter sib2, iclass 20, count 0 2006.175.08:06:02.75#ibcon#flushed, iclass 20, count 0 2006.175.08:06:02.75#ibcon#about to write, iclass 20, count 0 2006.175.08:06:02.75#ibcon#wrote, iclass 20, count 0 2006.175.08:06:02.75#ibcon#about to read 3, iclass 20, count 0 2006.175.08:06:02.77#ibcon#read 3, iclass 20, count 0 2006.175.08:06:02.77#ibcon#about to read 4, iclass 20, count 0 2006.175.08:06:02.77#ibcon#read 4, iclass 20, count 0 2006.175.08:06:02.77#ibcon#about to read 5, iclass 20, count 0 2006.175.08:06:02.77#ibcon#read 5, iclass 20, count 0 2006.175.08:06:02.77#ibcon#about to read 6, iclass 20, count 0 2006.175.08:06:02.77#ibcon#read 6, iclass 20, count 0 2006.175.08:06:02.77#ibcon#end of sib2, iclass 20, count 0 2006.175.08:06:02.77#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:06:02.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:06:02.77#ibcon#[27=BW32\r\n] 2006.175.08:06:02.77#ibcon#*before write, iclass 20, count 0 2006.175.08:06:02.77#ibcon#enter sib2, iclass 20, count 0 2006.175.08:06:02.77#ibcon#flushed, iclass 20, count 0 2006.175.08:06:02.77#ibcon#about to write, iclass 20, count 0 2006.175.08:06:02.77#ibcon#wrote, iclass 20, count 0 2006.175.08:06:02.77#ibcon#about to read 3, iclass 20, count 0 2006.175.08:06:02.80#ibcon#read 3, iclass 20, count 0 2006.175.08:06:02.80#ibcon#about to read 4, iclass 20, count 0 2006.175.08:06:02.80#ibcon#read 4, iclass 20, count 0 2006.175.08:06:02.80#ibcon#about to read 5, iclass 20, count 0 2006.175.08:06:02.80#ibcon#read 5, iclass 20, count 0 2006.175.08:06:02.80#ibcon#about to read 6, iclass 20, count 0 2006.175.08:06:02.80#ibcon#read 6, iclass 20, count 0 2006.175.08:06:02.80#ibcon#end of sib2, iclass 20, count 0 2006.175.08:06:02.80#ibcon#*after write, iclass 20, count 0 2006.175.08:06:02.80#ibcon#*before return 0, iclass 20, count 0 2006.175.08:06:02.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:06:02.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:06:02.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:06:02.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:06:02.80$4f8m12a/ifd4f 2006.175.08:06:02.80$ifd4f/lo= 2006.175.08:06:02.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:06:02.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:06:02.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:06:02.80$ifd4f/patch= 2006.175.08:06:02.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:06:02.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:06:02.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:06:02.80$4f8m12a/"form=m,16.000,1:2 2006.175.08:06:02.80$4f8m12a/"tpicd 2006.175.08:06:02.80$4f8m12a/echo=off 2006.175.08:06:02.80$4f8m12a/xlog=off 2006.175.08:06:02.80:!2006.175.08:06:30 2006.175.08:06:15.14#trakl#Source acquired 2006.175.08:06:15.14#flagr#flagr/antenna,acquired 2006.175.08:06:30.00:preob 2006.175.08:06:31.14/onsource/TRACKING 2006.175.08:06:31.14:!2006.175.08:06:40 2006.175.08:06:40.00:data_valid=on 2006.175.08:06:40.00:midob 2006.175.08:06:40.14/onsource/TRACKING 2006.175.08:06:40.14/wx/25.84,1007.4,68 2006.175.08:06:40.21/cable/+6.4788E-03 2006.175.08:06:41.30/va/01,08,usb,yes,29,31 2006.175.08:06:41.30/va/02,07,usb,yes,29,30 2006.175.08:06:41.30/va/03,06,usb,yes,30,31 2006.175.08:06:41.30/va/04,07,usb,yes,30,32 2006.175.08:06:41.30/va/05,07,usb,yes,30,32 2006.175.08:06:41.30/va/06,06,usb,yes,29,29 2006.175.08:06:41.30/va/07,06,usb,yes,30,29 2006.175.08:06:41.30/va/08,06,usb,yes,32,31 2006.175.08:06:41.53/valo/01,532.99,yes,locked 2006.175.08:06:41.53/valo/02,572.99,yes,locked 2006.175.08:06:41.53/valo/03,672.99,yes,locked 2006.175.08:06:41.53/valo/04,832.99,yes,locked 2006.175.08:06:41.53/valo/05,652.99,yes,locked 2006.175.08:06:41.53/valo/06,772.99,yes,locked 2006.175.08:06:41.53/valo/07,832.99,yes,locked 2006.175.08:06:41.53/valo/08,852.99,yes,locked 2006.175.08:06:42.62/vb/01,04,usb,yes,29,28 2006.175.08:06:42.62/vb/02,04,usb,yes,31,32 2006.175.08:06:42.62/vb/03,04,usb,yes,27,31 2006.175.08:06:42.62/vb/04,04,usb,yes,28,28 2006.175.08:06:42.62/vb/05,04,usb,yes,27,31 2006.175.08:06:42.62/vb/06,04,usb,yes,28,31 2006.175.08:06:42.62/vb/07,04,usb,yes,30,30 2006.175.08:06:42.62/vb/08,04,usb,yes,27,31 2006.175.08:06:42.85/vblo/01,632.99,yes,locked 2006.175.08:06:42.85/vblo/02,640.99,yes,locked 2006.175.08:06:42.85/vblo/03,656.99,yes,locked 2006.175.08:06:42.85/vblo/04,712.99,yes,locked 2006.175.08:06:42.85/vblo/05,744.99,yes,locked 2006.175.08:06:42.85/vblo/06,752.99,yes,locked 2006.175.08:06:42.85/vblo/07,734.99,yes,locked 2006.175.08:06:42.85/vblo/08,744.99,yes,locked 2006.175.08:06:43.00/vabw/8 2006.175.08:06:43.15/vbbw/8 2006.175.08:06:43.24/xfe/off,on,15.7 2006.175.08:06:43.62/ifatt/23,28,28,28 2006.175.08:06:44.07/fmout-gps/S +3.77E-07 2006.175.08:06:44.15:!2006.175.08:07:40 2006.175.08:07:40.01:data_valid=off 2006.175.08:07:40.02:postob 2006.175.08:07:40.17/cable/+6.4756E-03 2006.175.08:07:40.18/wx/25.83,1007.4,69 2006.175.08:07:41.07/fmout-gps/S +3.80E-07 2006.175.08:07:41.08:scan_name=175-0808,k06175,60 2006.175.08:07:41.08:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.175.08:07:41.13#flagr#flagr/antenna,new-source 2006.175.08:07:42.13:checkk5 2006.175.08:07:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:07:42.95/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:07:43.34/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:07:43.72/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:07:44.09/chk_obsdata//k5ts1/T1750806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:07:44.46/chk_obsdata//k5ts2/T1750806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:07:44.84/chk_obsdata//k5ts3/T1750806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:07:45.21/chk_obsdata//k5ts4/T1750806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:07:45.91/k5log//k5ts1_log_newline 2006.175.08:07:46.60/k5log//k5ts2_log_newline 2006.175.08:07:47.29/k5log//k5ts3_log_newline 2006.175.08:07:47.98/k5log//k5ts4_log_newline 2006.175.08:07:48.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:07:48.01:4f8m12a=2 2006.175.08:07:48.01$4f8m12a/echo=on 2006.175.08:07:48.01$4f8m12a/pcalon 2006.175.08:07:48.01$pcalon/"no phase cal control is implemented here 2006.175.08:07:48.01$4f8m12a/"tpicd=stop 2006.175.08:07:48.01$4f8m12a/vc4f8 2006.175.08:07:48.01$vc4f8/valo=1,532.99 2006.175.08:07:48.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.08:07:48.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.08:07:48.01#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:48.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:48.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:48.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:48.01#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:07:48.01#ibcon#first serial, iclass 31, count 0 2006.175.08:07:48.01#ibcon#enter sib2, iclass 31, count 0 2006.175.08:07:48.01#ibcon#flushed, iclass 31, count 0 2006.175.08:07:48.01#ibcon#about to write, iclass 31, count 0 2006.175.08:07:48.01#ibcon#wrote, iclass 31, count 0 2006.175.08:07:48.01#ibcon#about to read 3, iclass 31, count 0 2006.175.08:07:48.02#ibcon#read 3, iclass 31, count 0 2006.175.08:07:48.02#ibcon#about to read 4, iclass 31, count 0 2006.175.08:07:48.02#ibcon#read 4, iclass 31, count 0 2006.175.08:07:48.02#ibcon#about to read 5, iclass 31, count 0 2006.175.08:07:48.02#ibcon#read 5, iclass 31, count 0 2006.175.08:07:48.02#ibcon#about to read 6, iclass 31, count 0 2006.175.08:07:48.02#ibcon#read 6, iclass 31, count 0 2006.175.08:07:48.02#ibcon#end of sib2, iclass 31, count 0 2006.175.08:07:48.02#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:07:48.02#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:07:48.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:07:48.02#ibcon#*before write, iclass 31, count 0 2006.175.08:07:48.02#ibcon#enter sib2, iclass 31, count 0 2006.175.08:07:48.02#ibcon#flushed, iclass 31, count 0 2006.175.08:07:48.02#ibcon#about to write, iclass 31, count 0 2006.175.08:07:48.02#ibcon#wrote, iclass 31, count 0 2006.175.08:07:48.02#ibcon#about to read 3, iclass 31, count 0 2006.175.08:07:48.07#ibcon#read 3, iclass 31, count 0 2006.175.08:07:48.07#ibcon#about to read 4, iclass 31, count 0 2006.175.08:07:48.07#ibcon#read 4, iclass 31, count 0 2006.175.08:07:48.07#ibcon#about to read 5, iclass 31, count 0 2006.175.08:07:48.07#ibcon#read 5, iclass 31, count 0 2006.175.08:07:48.07#ibcon#about to read 6, iclass 31, count 0 2006.175.08:07:48.07#ibcon#read 6, iclass 31, count 0 2006.175.08:07:48.07#ibcon#end of sib2, iclass 31, count 0 2006.175.08:07:48.07#ibcon#*after write, iclass 31, count 0 2006.175.08:07:48.07#ibcon#*before return 0, iclass 31, count 0 2006.175.08:07:48.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:48.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:48.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:07:48.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:07:48.07$vc4f8/va=1,8 2006.175.08:07:48.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.08:07:48.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.08:07:48.07#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:48.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:48.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:48.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:48.07#ibcon#enter wrdev, iclass 33, count 2 2006.175.08:07:48.07#ibcon#first serial, iclass 33, count 2 2006.175.08:07:48.07#ibcon#enter sib2, iclass 33, count 2 2006.175.08:07:48.07#ibcon#flushed, iclass 33, count 2 2006.175.08:07:48.07#ibcon#about to write, iclass 33, count 2 2006.175.08:07:48.07#ibcon#wrote, iclass 33, count 2 2006.175.08:07:48.07#ibcon#about to read 3, iclass 33, count 2 2006.175.08:07:48.09#ibcon#read 3, iclass 33, count 2 2006.175.08:07:48.09#ibcon#about to read 4, iclass 33, count 2 2006.175.08:07:48.09#ibcon#read 4, iclass 33, count 2 2006.175.08:07:48.09#ibcon#about to read 5, iclass 33, count 2 2006.175.08:07:48.09#ibcon#read 5, iclass 33, count 2 2006.175.08:07:48.09#ibcon#about to read 6, iclass 33, count 2 2006.175.08:07:48.09#ibcon#read 6, iclass 33, count 2 2006.175.08:07:48.09#ibcon#end of sib2, iclass 33, count 2 2006.175.08:07:48.09#ibcon#*mode == 0, iclass 33, count 2 2006.175.08:07:48.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.08:07:48.09#ibcon#[25=AT01-08\r\n] 2006.175.08:07:48.09#ibcon#*before write, iclass 33, count 2 2006.175.08:07:48.09#ibcon#enter sib2, iclass 33, count 2 2006.175.08:07:48.09#ibcon#flushed, iclass 33, count 2 2006.175.08:07:48.09#ibcon#about to write, iclass 33, count 2 2006.175.08:07:48.09#ibcon#wrote, iclass 33, count 2 2006.175.08:07:48.09#ibcon#about to read 3, iclass 33, count 2 2006.175.08:07:48.13#ibcon#read 3, iclass 33, count 2 2006.175.08:07:48.13#ibcon#about to read 4, iclass 33, count 2 2006.175.08:07:48.13#ibcon#read 4, iclass 33, count 2 2006.175.08:07:48.13#ibcon#about to read 5, iclass 33, count 2 2006.175.08:07:48.13#ibcon#read 5, iclass 33, count 2 2006.175.08:07:48.13#ibcon#about to read 6, iclass 33, count 2 2006.175.08:07:48.13#ibcon#read 6, iclass 33, count 2 2006.175.08:07:48.13#ibcon#end of sib2, iclass 33, count 2 2006.175.08:07:48.13#ibcon#*after write, iclass 33, count 2 2006.175.08:07:48.13#ibcon#*before return 0, iclass 33, count 2 2006.175.08:07:48.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:48.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:48.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.08:07:48.13#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:48.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:48.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:48.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:48.24#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:07:48.24#ibcon#first serial, iclass 33, count 0 2006.175.08:07:48.24#ibcon#enter sib2, iclass 33, count 0 2006.175.08:07:48.24#ibcon#flushed, iclass 33, count 0 2006.175.08:07:48.24#ibcon#about to write, iclass 33, count 0 2006.175.08:07:48.24#ibcon#wrote, iclass 33, count 0 2006.175.08:07:48.24#ibcon#about to read 3, iclass 33, count 0 2006.175.08:07:48.26#ibcon#read 3, iclass 33, count 0 2006.175.08:07:48.26#ibcon#about to read 4, iclass 33, count 0 2006.175.08:07:48.26#ibcon#read 4, iclass 33, count 0 2006.175.08:07:48.26#ibcon#about to read 5, iclass 33, count 0 2006.175.08:07:48.26#ibcon#read 5, iclass 33, count 0 2006.175.08:07:48.26#ibcon#about to read 6, iclass 33, count 0 2006.175.08:07:48.26#ibcon#read 6, iclass 33, count 0 2006.175.08:07:48.26#ibcon#end of sib2, iclass 33, count 0 2006.175.08:07:48.26#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:07:48.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:07:48.26#ibcon#[25=USB\r\n] 2006.175.08:07:48.26#ibcon#*before write, iclass 33, count 0 2006.175.08:07:48.26#ibcon#enter sib2, iclass 33, count 0 2006.175.08:07:48.26#ibcon#flushed, iclass 33, count 0 2006.175.08:07:48.26#ibcon#about to write, iclass 33, count 0 2006.175.08:07:48.26#ibcon#wrote, iclass 33, count 0 2006.175.08:07:48.26#ibcon#about to read 3, iclass 33, count 0 2006.175.08:07:48.29#ibcon#read 3, iclass 33, count 0 2006.175.08:07:48.29#ibcon#about to read 4, iclass 33, count 0 2006.175.08:07:48.29#ibcon#read 4, iclass 33, count 0 2006.175.08:07:48.29#ibcon#about to read 5, iclass 33, count 0 2006.175.08:07:48.29#ibcon#read 5, iclass 33, count 0 2006.175.08:07:48.29#ibcon#about to read 6, iclass 33, count 0 2006.175.08:07:48.29#ibcon#read 6, iclass 33, count 0 2006.175.08:07:48.29#ibcon#end of sib2, iclass 33, count 0 2006.175.08:07:48.29#ibcon#*after write, iclass 33, count 0 2006.175.08:07:48.29#ibcon#*before return 0, iclass 33, count 0 2006.175.08:07:48.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:48.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:48.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:07:48.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:07:48.29$vc4f8/valo=2,572.99 2006.175.08:07:48.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.08:07:48.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.08:07:48.29#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:48.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:48.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:48.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:48.29#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:07:48.29#ibcon#first serial, iclass 35, count 0 2006.175.08:07:48.29#ibcon#enter sib2, iclass 35, count 0 2006.175.08:07:48.29#ibcon#flushed, iclass 35, count 0 2006.175.08:07:48.29#ibcon#about to write, iclass 35, count 0 2006.175.08:07:48.29#ibcon#wrote, iclass 35, count 0 2006.175.08:07:48.29#ibcon#about to read 3, iclass 35, count 0 2006.175.08:07:48.31#ibcon#read 3, iclass 35, count 0 2006.175.08:07:48.31#ibcon#about to read 4, iclass 35, count 0 2006.175.08:07:48.31#ibcon#read 4, iclass 35, count 0 2006.175.08:07:48.31#ibcon#about to read 5, iclass 35, count 0 2006.175.08:07:48.31#ibcon#read 5, iclass 35, count 0 2006.175.08:07:48.31#ibcon#about to read 6, iclass 35, count 0 2006.175.08:07:48.31#ibcon#read 6, iclass 35, count 0 2006.175.08:07:48.31#ibcon#end of sib2, iclass 35, count 0 2006.175.08:07:48.31#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:07:48.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:07:48.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:07:48.31#ibcon#*before write, iclass 35, count 0 2006.175.08:07:48.31#ibcon#enter sib2, iclass 35, count 0 2006.175.08:07:48.31#ibcon#flushed, iclass 35, count 0 2006.175.08:07:48.31#ibcon#about to write, iclass 35, count 0 2006.175.08:07:48.31#ibcon#wrote, iclass 35, count 0 2006.175.08:07:48.31#ibcon#about to read 3, iclass 35, count 0 2006.175.08:07:48.35#ibcon#read 3, iclass 35, count 0 2006.175.08:07:48.35#ibcon#about to read 4, iclass 35, count 0 2006.175.08:07:48.35#ibcon#read 4, iclass 35, count 0 2006.175.08:07:48.35#ibcon#about to read 5, iclass 35, count 0 2006.175.08:07:48.35#ibcon#read 5, iclass 35, count 0 2006.175.08:07:48.35#ibcon#about to read 6, iclass 35, count 0 2006.175.08:07:48.35#ibcon#read 6, iclass 35, count 0 2006.175.08:07:48.35#ibcon#end of sib2, iclass 35, count 0 2006.175.08:07:48.35#ibcon#*after write, iclass 35, count 0 2006.175.08:07:48.35#ibcon#*before return 0, iclass 35, count 0 2006.175.08:07:48.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:48.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:48.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:07:48.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:07:48.35$vc4f8/va=2,7 2006.175.08:07:48.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.08:07:48.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.08:07:48.35#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:48.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:48.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:48.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:48.42#ibcon#enter wrdev, iclass 37, count 2 2006.175.08:07:48.42#ibcon#first serial, iclass 37, count 2 2006.175.08:07:48.42#ibcon#enter sib2, iclass 37, count 2 2006.175.08:07:48.42#ibcon#flushed, iclass 37, count 2 2006.175.08:07:48.42#ibcon#about to write, iclass 37, count 2 2006.175.08:07:48.42#ibcon#wrote, iclass 37, count 2 2006.175.08:07:48.42#ibcon#about to read 3, iclass 37, count 2 2006.175.08:07:48.43#ibcon#read 3, iclass 37, count 2 2006.175.08:07:48.43#ibcon#about to read 4, iclass 37, count 2 2006.175.08:07:48.43#ibcon#read 4, iclass 37, count 2 2006.175.08:07:48.43#ibcon#about to read 5, iclass 37, count 2 2006.175.08:07:48.43#ibcon#read 5, iclass 37, count 2 2006.175.08:07:48.43#ibcon#about to read 6, iclass 37, count 2 2006.175.08:07:48.43#ibcon#read 6, iclass 37, count 2 2006.175.08:07:48.43#ibcon#end of sib2, iclass 37, count 2 2006.175.08:07:48.43#ibcon#*mode == 0, iclass 37, count 2 2006.175.08:07:48.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.08:07:48.43#ibcon#[25=AT02-07\r\n] 2006.175.08:07:48.43#ibcon#*before write, iclass 37, count 2 2006.175.08:07:48.43#ibcon#enter sib2, iclass 37, count 2 2006.175.08:07:48.43#ibcon#flushed, iclass 37, count 2 2006.175.08:07:48.43#ibcon#about to write, iclass 37, count 2 2006.175.08:07:48.43#ibcon#wrote, iclass 37, count 2 2006.175.08:07:48.43#ibcon#about to read 3, iclass 37, count 2 2006.175.08:07:48.46#ibcon#read 3, iclass 37, count 2 2006.175.08:07:48.46#ibcon#about to read 4, iclass 37, count 2 2006.175.08:07:48.46#ibcon#read 4, iclass 37, count 2 2006.175.08:07:48.46#ibcon#about to read 5, iclass 37, count 2 2006.175.08:07:48.46#ibcon#read 5, iclass 37, count 2 2006.175.08:07:48.46#ibcon#about to read 6, iclass 37, count 2 2006.175.08:07:48.46#ibcon#read 6, iclass 37, count 2 2006.175.08:07:48.46#ibcon#end of sib2, iclass 37, count 2 2006.175.08:07:48.46#ibcon#*after write, iclass 37, count 2 2006.175.08:07:48.46#ibcon#*before return 0, iclass 37, count 2 2006.175.08:07:48.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:48.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:48.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.08:07:48.46#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:48.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:48.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:48.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:48.58#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:07:48.58#ibcon#first serial, iclass 37, count 0 2006.175.08:07:48.58#ibcon#enter sib2, iclass 37, count 0 2006.175.08:07:48.58#ibcon#flushed, iclass 37, count 0 2006.175.08:07:48.58#ibcon#about to write, iclass 37, count 0 2006.175.08:07:48.58#ibcon#wrote, iclass 37, count 0 2006.175.08:07:48.58#ibcon#about to read 3, iclass 37, count 0 2006.175.08:07:48.60#ibcon#read 3, iclass 37, count 0 2006.175.08:07:48.60#ibcon#about to read 4, iclass 37, count 0 2006.175.08:07:48.60#ibcon#read 4, iclass 37, count 0 2006.175.08:07:48.60#ibcon#about to read 5, iclass 37, count 0 2006.175.08:07:48.60#ibcon#read 5, iclass 37, count 0 2006.175.08:07:48.60#ibcon#about to read 6, iclass 37, count 0 2006.175.08:07:48.60#ibcon#read 6, iclass 37, count 0 2006.175.08:07:48.60#ibcon#end of sib2, iclass 37, count 0 2006.175.08:07:48.60#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:07:48.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:07:48.60#ibcon#[25=USB\r\n] 2006.175.08:07:48.60#ibcon#*before write, iclass 37, count 0 2006.175.08:07:48.60#ibcon#enter sib2, iclass 37, count 0 2006.175.08:07:48.60#ibcon#flushed, iclass 37, count 0 2006.175.08:07:48.60#ibcon#about to write, iclass 37, count 0 2006.175.08:07:48.60#ibcon#wrote, iclass 37, count 0 2006.175.08:07:48.60#ibcon#about to read 3, iclass 37, count 0 2006.175.08:07:48.63#ibcon#read 3, iclass 37, count 0 2006.175.08:07:48.63#ibcon#about to read 4, iclass 37, count 0 2006.175.08:07:48.63#ibcon#read 4, iclass 37, count 0 2006.175.08:07:48.63#ibcon#about to read 5, iclass 37, count 0 2006.175.08:07:48.63#ibcon#read 5, iclass 37, count 0 2006.175.08:07:48.63#ibcon#about to read 6, iclass 37, count 0 2006.175.08:07:48.63#ibcon#read 6, iclass 37, count 0 2006.175.08:07:48.63#ibcon#end of sib2, iclass 37, count 0 2006.175.08:07:48.63#ibcon#*after write, iclass 37, count 0 2006.175.08:07:48.63#ibcon#*before return 0, iclass 37, count 0 2006.175.08:07:48.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:48.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:48.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:07:48.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:07:48.63$vc4f8/valo=3,672.99 2006.175.08:07:48.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.08:07:48.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.08:07:48.63#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:48.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:48.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:48.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:48.63#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:07:48.63#ibcon#first serial, iclass 39, count 0 2006.175.08:07:48.63#ibcon#enter sib2, iclass 39, count 0 2006.175.08:07:48.63#ibcon#flushed, iclass 39, count 0 2006.175.08:07:48.63#ibcon#about to write, iclass 39, count 0 2006.175.08:07:48.63#ibcon#wrote, iclass 39, count 0 2006.175.08:07:48.63#ibcon#about to read 3, iclass 39, count 0 2006.175.08:07:48.65#ibcon#read 3, iclass 39, count 0 2006.175.08:07:48.65#ibcon#about to read 4, iclass 39, count 0 2006.175.08:07:48.65#ibcon#read 4, iclass 39, count 0 2006.175.08:07:48.65#ibcon#about to read 5, iclass 39, count 0 2006.175.08:07:48.65#ibcon#read 5, iclass 39, count 0 2006.175.08:07:48.65#ibcon#about to read 6, iclass 39, count 0 2006.175.08:07:48.65#ibcon#read 6, iclass 39, count 0 2006.175.08:07:48.65#ibcon#end of sib2, iclass 39, count 0 2006.175.08:07:48.65#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:07:48.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:07:48.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:07:48.65#ibcon#*before write, iclass 39, count 0 2006.175.08:07:48.65#ibcon#enter sib2, iclass 39, count 0 2006.175.08:07:48.65#ibcon#flushed, iclass 39, count 0 2006.175.08:07:48.65#ibcon#about to write, iclass 39, count 0 2006.175.08:07:48.65#ibcon#wrote, iclass 39, count 0 2006.175.08:07:48.65#ibcon#about to read 3, iclass 39, count 0 2006.175.08:07:48.69#ibcon#read 3, iclass 39, count 0 2006.175.08:07:48.69#ibcon#about to read 4, iclass 39, count 0 2006.175.08:07:48.69#ibcon#read 4, iclass 39, count 0 2006.175.08:07:48.69#ibcon#about to read 5, iclass 39, count 0 2006.175.08:07:48.69#ibcon#read 5, iclass 39, count 0 2006.175.08:07:48.69#ibcon#about to read 6, iclass 39, count 0 2006.175.08:07:48.69#ibcon#read 6, iclass 39, count 0 2006.175.08:07:48.69#ibcon#end of sib2, iclass 39, count 0 2006.175.08:07:48.69#ibcon#*after write, iclass 39, count 0 2006.175.08:07:48.69#ibcon#*before return 0, iclass 39, count 0 2006.175.08:07:48.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:48.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:48.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:07:48.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:07:48.69$vc4f8/va=3,6 2006.175.08:07:48.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.08:07:48.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.08:07:48.69#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:48.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:48.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:48.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:48.76#ibcon#enter wrdev, iclass 3, count 2 2006.175.08:07:48.76#ibcon#first serial, iclass 3, count 2 2006.175.08:07:48.76#ibcon#enter sib2, iclass 3, count 2 2006.175.08:07:48.76#ibcon#flushed, iclass 3, count 2 2006.175.08:07:48.76#ibcon#about to write, iclass 3, count 2 2006.175.08:07:48.76#ibcon#wrote, iclass 3, count 2 2006.175.08:07:48.76#ibcon#about to read 3, iclass 3, count 2 2006.175.08:07:48.77#ibcon#read 3, iclass 3, count 2 2006.175.08:07:48.77#ibcon#about to read 4, iclass 3, count 2 2006.175.08:07:48.77#ibcon#read 4, iclass 3, count 2 2006.175.08:07:48.77#ibcon#about to read 5, iclass 3, count 2 2006.175.08:07:48.77#ibcon#read 5, iclass 3, count 2 2006.175.08:07:48.77#ibcon#about to read 6, iclass 3, count 2 2006.175.08:07:48.77#ibcon#read 6, iclass 3, count 2 2006.175.08:07:48.77#ibcon#end of sib2, iclass 3, count 2 2006.175.08:07:48.77#ibcon#*mode == 0, iclass 3, count 2 2006.175.08:07:48.77#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.08:07:48.77#ibcon#[25=AT03-06\r\n] 2006.175.08:07:48.77#ibcon#*before write, iclass 3, count 2 2006.175.08:07:48.77#ibcon#enter sib2, iclass 3, count 2 2006.175.08:07:48.77#ibcon#flushed, iclass 3, count 2 2006.175.08:07:48.77#ibcon#about to write, iclass 3, count 2 2006.175.08:07:48.77#ibcon#wrote, iclass 3, count 2 2006.175.08:07:48.77#ibcon#about to read 3, iclass 3, count 2 2006.175.08:07:48.80#ibcon#read 3, iclass 3, count 2 2006.175.08:07:48.80#ibcon#about to read 4, iclass 3, count 2 2006.175.08:07:48.80#ibcon#read 4, iclass 3, count 2 2006.175.08:07:48.80#ibcon#about to read 5, iclass 3, count 2 2006.175.08:07:48.80#ibcon#read 5, iclass 3, count 2 2006.175.08:07:48.80#ibcon#about to read 6, iclass 3, count 2 2006.175.08:07:48.80#ibcon#read 6, iclass 3, count 2 2006.175.08:07:48.80#ibcon#end of sib2, iclass 3, count 2 2006.175.08:07:48.80#ibcon#*after write, iclass 3, count 2 2006.175.08:07:48.80#ibcon#*before return 0, iclass 3, count 2 2006.175.08:07:48.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:48.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:48.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.08:07:48.80#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:48.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:48.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:48.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:48.92#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:07:48.92#ibcon#first serial, iclass 3, count 0 2006.175.08:07:48.92#ibcon#enter sib2, iclass 3, count 0 2006.175.08:07:48.92#ibcon#flushed, iclass 3, count 0 2006.175.08:07:48.92#ibcon#about to write, iclass 3, count 0 2006.175.08:07:48.92#ibcon#wrote, iclass 3, count 0 2006.175.08:07:48.92#ibcon#about to read 3, iclass 3, count 0 2006.175.08:07:48.94#ibcon#read 3, iclass 3, count 0 2006.175.08:07:48.94#ibcon#about to read 4, iclass 3, count 0 2006.175.08:07:48.94#ibcon#read 4, iclass 3, count 0 2006.175.08:07:48.94#ibcon#about to read 5, iclass 3, count 0 2006.175.08:07:48.94#ibcon#read 5, iclass 3, count 0 2006.175.08:07:48.94#ibcon#about to read 6, iclass 3, count 0 2006.175.08:07:48.94#ibcon#read 6, iclass 3, count 0 2006.175.08:07:48.94#ibcon#end of sib2, iclass 3, count 0 2006.175.08:07:48.94#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:07:48.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:07:48.94#ibcon#[25=USB\r\n] 2006.175.08:07:48.94#ibcon#*before write, iclass 3, count 0 2006.175.08:07:48.94#ibcon#enter sib2, iclass 3, count 0 2006.175.08:07:48.94#ibcon#flushed, iclass 3, count 0 2006.175.08:07:48.94#ibcon#about to write, iclass 3, count 0 2006.175.08:07:48.94#ibcon#wrote, iclass 3, count 0 2006.175.08:07:48.94#ibcon#about to read 3, iclass 3, count 0 2006.175.08:07:48.97#ibcon#read 3, iclass 3, count 0 2006.175.08:07:48.97#ibcon#about to read 4, iclass 3, count 0 2006.175.08:07:48.97#ibcon#read 4, iclass 3, count 0 2006.175.08:07:48.97#ibcon#about to read 5, iclass 3, count 0 2006.175.08:07:48.97#ibcon#read 5, iclass 3, count 0 2006.175.08:07:48.97#ibcon#about to read 6, iclass 3, count 0 2006.175.08:07:48.97#ibcon#read 6, iclass 3, count 0 2006.175.08:07:48.97#ibcon#end of sib2, iclass 3, count 0 2006.175.08:07:48.97#ibcon#*after write, iclass 3, count 0 2006.175.08:07:48.97#ibcon#*before return 0, iclass 3, count 0 2006.175.08:07:48.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:48.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:48.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:07:48.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:07:48.97$vc4f8/valo=4,832.99 2006.175.08:07:48.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.08:07:48.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.08:07:48.97#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:48.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:48.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:48.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:48.97#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:07:48.97#ibcon#first serial, iclass 5, count 0 2006.175.08:07:48.97#ibcon#enter sib2, iclass 5, count 0 2006.175.08:07:48.97#ibcon#flushed, iclass 5, count 0 2006.175.08:07:48.97#ibcon#about to write, iclass 5, count 0 2006.175.08:07:48.97#ibcon#wrote, iclass 5, count 0 2006.175.08:07:48.97#ibcon#about to read 3, iclass 5, count 0 2006.175.08:07:48.99#ibcon#read 3, iclass 5, count 0 2006.175.08:07:48.99#ibcon#about to read 4, iclass 5, count 0 2006.175.08:07:48.99#ibcon#read 4, iclass 5, count 0 2006.175.08:07:48.99#ibcon#about to read 5, iclass 5, count 0 2006.175.08:07:48.99#ibcon#read 5, iclass 5, count 0 2006.175.08:07:48.99#ibcon#about to read 6, iclass 5, count 0 2006.175.08:07:48.99#ibcon#read 6, iclass 5, count 0 2006.175.08:07:48.99#ibcon#end of sib2, iclass 5, count 0 2006.175.08:07:48.99#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:07:48.99#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:07:48.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:07:48.99#ibcon#*before write, iclass 5, count 0 2006.175.08:07:48.99#ibcon#enter sib2, iclass 5, count 0 2006.175.08:07:48.99#ibcon#flushed, iclass 5, count 0 2006.175.08:07:48.99#ibcon#about to write, iclass 5, count 0 2006.175.08:07:48.99#ibcon#wrote, iclass 5, count 0 2006.175.08:07:48.99#ibcon#about to read 3, iclass 5, count 0 2006.175.08:07:49.03#ibcon#read 3, iclass 5, count 0 2006.175.08:07:49.03#ibcon#about to read 4, iclass 5, count 0 2006.175.08:07:49.03#ibcon#read 4, iclass 5, count 0 2006.175.08:07:49.03#ibcon#about to read 5, iclass 5, count 0 2006.175.08:07:49.03#ibcon#read 5, iclass 5, count 0 2006.175.08:07:49.03#ibcon#about to read 6, iclass 5, count 0 2006.175.08:07:49.03#ibcon#read 6, iclass 5, count 0 2006.175.08:07:49.03#ibcon#end of sib2, iclass 5, count 0 2006.175.08:07:49.03#ibcon#*after write, iclass 5, count 0 2006.175.08:07:49.03#ibcon#*before return 0, iclass 5, count 0 2006.175.08:07:49.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:49.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:49.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:07:49.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:07:49.03$vc4f8/va=4,7 2006.175.08:07:49.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.08:07:49.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.08:07:49.03#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:49.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:49.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:49.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:49.09#ibcon#enter wrdev, iclass 7, count 2 2006.175.08:07:49.09#ibcon#first serial, iclass 7, count 2 2006.175.08:07:49.09#ibcon#enter sib2, iclass 7, count 2 2006.175.08:07:49.09#ibcon#flushed, iclass 7, count 2 2006.175.08:07:49.09#ibcon#about to write, iclass 7, count 2 2006.175.08:07:49.09#ibcon#wrote, iclass 7, count 2 2006.175.08:07:49.09#ibcon#about to read 3, iclass 7, count 2 2006.175.08:07:49.11#ibcon#read 3, iclass 7, count 2 2006.175.08:07:49.11#ibcon#about to read 4, iclass 7, count 2 2006.175.08:07:49.11#ibcon#read 4, iclass 7, count 2 2006.175.08:07:49.11#ibcon#about to read 5, iclass 7, count 2 2006.175.08:07:49.11#ibcon#read 5, iclass 7, count 2 2006.175.08:07:49.11#ibcon#about to read 6, iclass 7, count 2 2006.175.08:07:49.11#ibcon#read 6, iclass 7, count 2 2006.175.08:07:49.11#ibcon#end of sib2, iclass 7, count 2 2006.175.08:07:49.11#ibcon#*mode == 0, iclass 7, count 2 2006.175.08:07:49.11#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.08:07:49.11#ibcon#[25=AT04-07\r\n] 2006.175.08:07:49.11#ibcon#*before write, iclass 7, count 2 2006.175.08:07:49.11#ibcon#enter sib2, iclass 7, count 2 2006.175.08:07:49.11#ibcon#flushed, iclass 7, count 2 2006.175.08:07:49.11#ibcon#about to write, iclass 7, count 2 2006.175.08:07:49.11#ibcon#wrote, iclass 7, count 2 2006.175.08:07:49.11#ibcon#about to read 3, iclass 7, count 2 2006.175.08:07:49.14#ibcon#read 3, iclass 7, count 2 2006.175.08:07:49.14#ibcon#about to read 4, iclass 7, count 2 2006.175.08:07:49.14#ibcon#read 4, iclass 7, count 2 2006.175.08:07:49.14#ibcon#about to read 5, iclass 7, count 2 2006.175.08:07:49.14#ibcon#read 5, iclass 7, count 2 2006.175.08:07:49.14#ibcon#about to read 6, iclass 7, count 2 2006.175.08:07:49.14#ibcon#read 6, iclass 7, count 2 2006.175.08:07:49.14#ibcon#end of sib2, iclass 7, count 2 2006.175.08:07:49.14#ibcon#*after write, iclass 7, count 2 2006.175.08:07:49.14#ibcon#*before return 0, iclass 7, count 2 2006.175.08:07:49.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:49.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:49.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.08:07:49.14#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:49.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:49.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:49.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:49.26#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:07:49.26#ibcon#first serial, iclass 7, count 0 2006.175.08:07:49.26#ibcon#enter sib2, iclass 7, count 0 2006.175.08:07:49.26#ibcon#flushed, iclass 7, count 0 2006.175.08:07:49.26#ibcon#about to write, iclass 7, count 0 2006.175.08:07:49.26#ibcon#wrote, iclass 7, count 0 2006.175.08:07:49.26#ibcon#about to read 3, iclass 7, count 0 2006.175.08:07:49.28#ibcon#read 3, iclass 7, count 0 2006.175.08:07:49.28#ibcon#about to read 4, iclass 7, count 0 2006.175.08:07:49.28#ibcon#read 4, iclass 7, count 0 2006.175.08:07:49.28#ibcon#about to read 5, iclass 7, count 0 2006.175.08:07:49.28#ibcon#read 5, iclass 7, count 0 2006.175.08:07:49.28#ibcon#about to read 6, iclass 7, count 0 2006.175.08:07:49.28#ibcon#read 6, iclass 7, count 0 2006.175.08:07:49.28#ibcon#end of sib2, iclass 7, count 0 2006.175.08:07:49.28#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:07:49.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:07:49.28#ibcon#[25=USB\r\n] 2006.175.08:07:49.28#ibcon#*before write, iclass 7, count 0 2006.175.08:07:49.28#ibcon#enter sib2, iclass 7, count 0 2006.175.08:07:49.28#ibcon#flushed, iclass 7, count 0 2006.175.08:07:49.28#ibcon#about to write, iclass 7, count 0 2006.175.08:07:49.28#ibcon#wrote, iclass 7, count 0 2006.175.08:07:49.28#ibcon#about to read 3, iclass 7, count 0 2006.175.08:07:49.31#ibcon#read 3, iclass 7, count 0 2006.175.08:07:49.31#ibcon#about to read 4, iclass 7, count 0 2006.175.08:07:49.31#ibcon#read 4, iclass 7, count 0 2006.175.08:07:49.31#ibcon#about to read 5, iclass 7, count 0 2006.175.08:07:49.31#ibcon#read 5, iclass 7, count 0 2006.175.08:07:49.31#ibcon#about to read 6, iclass 7, count 0 2006.175.08:07:49.31#ibcon#read 6, iclass 7, count 0 2006.175.08:07:49.31#ibcon#end of sib2, iclass 7, count 0 2006.175.08:07:49.31#ibcon#*after write, iclass 7, count 0 2006.175.08:07:49.31#ibcon#*before return 0, iclass 7, count 0 2006.175.08:07:49.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:49.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:49.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:07:49.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:07:49.31$vc4f8/valo=5,652.99 2006.175.08:07:49.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.08:07:49.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.08:07:49.31#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:49.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:49.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:49.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:49.31#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:07:49.31#ibcon#first serial, iclass 11, count 0 2006.175.08:07:49.31#ibcon#enter sib2, iclass 11, count 0 2006.175.08:07:49.31#ibcon#flushed, iclass 11, count 0 2006.175.08:07:49.31#ibcon#about to write, iclass 11, count 0 2006.175.08:07:49.31#ibcon#wrote, iclass 11, count 0 2006.175.08:07:49.31#ibcon#about to read 3, iclass 11, count 0 2006.175.08:07:49.33#ibcon#read 3, iclass 11, count 0 2006.175.08:07:49.33#ibcon#about to read 4, iclass 11, count 0 2006.175.08:07:49.33#ibcon#read 4, iclass 11, count 0 2006.175.08:07:49.33#ibcon#about to read 5, iclass 11, count 0 2006.175.08:07:49.33#ibcon#read 5, iclass 11, count 0 2006.175.08:07:49.33#ibcon#about to read 6, iclass 11, count 0 2006.175.08:07:49.33#ibcon#read 6, iclass 11, count 0 2006.175.08:07:49.33#ibcon#end of sib2, iclass 11, count 0 2006.175.08:07:49.33#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:07:49.33#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:07:49.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:07:49.33#ibcon#*before write, iclass 11, count 0 2006.175.08:07:49.33#ibcon#enter sib2, iclass 11, count 0 2006.175.08:07:49.33#ibcon#flushed, iclass 11, count 0 2006.175.08:07:49.33#ibcon#about to write, iclass 11, count 0 2006.175.08:07:49.33#ibcon#wrote, iclass 11, count 0 2006.175.08:07:49.33#ibcon#about to read 3, iclass 11, count 0 2006.175.08:07:49.37#ibcon#read 3, iclass 11, count 0 2006.175.08:07:49.37#ibcon#about to read 4, iclass 11, count 0 2006.175.08:07:49.37#ibcon#read 4, iclass 11, count 0 2006.175.08:07:49.37#ibcon#about to read 5, iclass 11, count 0 2006.175.08:07:49.37#ibcon#read 5, iclass 11, count 0 2006.175.08:07:49.37#ibcon#about to read 6, iclass 11, count 0 2006.175.08:07:49.37#ibcon#read 6, iclass 11, count 0 2006.175.08:07:49.37#ibcon#end of sib2, iclass 11, count 0 2006.175.08:07:49.37#ibcon#*after write, iclass 11, count 0 2006.175.08:07:49.37#ibcon#*before return 0, iclass 11, count 0 2006.175.08:07:49.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:49.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:49.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:07:49.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:07:49.37$vc4f8/va=5,7 2006.175.08:07:49.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.08:07:49.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.08:07:49.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:49.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:49.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:49.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:49.43#ibcon#enter wrdev, iclass 13, count 2 2006.175.08:07:49.43#ibcon#first serial, iclass 13, count 2 2006.175.08:07:49.43#ibcon#enter sib2, iclass 13, count 2 2006.175.08:07:49.43#ibcon#flushed, iclass 13, count 2 2006.175.08:07:49.43#ibcon#about to write, iclass 13, count 2 2006.175.08:07:49.43#ibcon#wrote, iclass 13, count 2 2006.175.08:07:49.43#ibcon#about to read 3, iclass 13, count 2 2006.175.08:07:49.45#ibcon#read 3, iclass 13, count 2 2006.175.08:07:49.45#ibcon#about to read 4, iclass 13, count 2 2006.175.08:07:49.45#ibcon#read 4, iclass 13, count 2 2006.175.08:07:49.45#ibcon#about to read 5, iclass 13, count 2 2006.175.08:07:49.45#ibcon#read 5, iclass 13, count 2 2006.175.08:07:49.45#ibcon#about to read 6, iclass 13, count 2 2006.175.08:07:49.45#ibcon#read 6, iclass 13, count 2 2006.175.08:07:49.45#ibcon#end of sib2, iclass 13, count 2 2006.175.08:07:49.45#ibcon#*mode == 0, iclass 13, count 2 2006.175.08:07:49.45#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.08:07:49.45#ibcon#[25=AT05-07\r\n] 2006.175.08:07:49.45#ibcon#*before write, iclass 13, count 2 2006.175.08:07:49.45#ibcon#enter sib2, iclass 13, count 2 2006.175.08:07:49.45#ibcon#flushed, iclass 13, count 2 2006.175.08:07:49.45#ibcon#about to write, iclass 13, count 2 2006.175.08:07:49.45#ibcon#wrote, iclass 13, count 2 2006.175.08:07:49.45#ibcon#about to read 3, iclass 13, count 2 2006.175.08:07:49.48#ibcon#read 3, iclass 13, count 2 2006.175.08:07:49.48#ibcon#about to read 4, iclass 13, count 2 2006.175.08:07:49.48#ibcon#read 4, iclass 13, count 2 2006.175.08:07:49.48#ibcon#about to read 5, iclass 13, count 2 2006.175.08:07:49.48#ibcon#read 5, iclass 13, count 2 2006.175.08:07:49.48#ibcon#about to read 6, iclass 13, count 2 2006.175.08:07:49.48#ibcon#read 6, iclass 13, count 2 2006.175.08:07:49.48#ibcon#end of sib2, iclass 13, count 2 2006.175.08:07:49.48#ibcon#*after write, iclass 13, count 2 2006.175.08:07:49.48#ibcon#*before return 0, iclass 13, count 2 2006.175.08:07:49.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:49.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:49.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.08:07:49.48#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:49.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:49.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:49.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:49.60#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:07:49.60#ibcon#first serial, iclass 13, count 0 2006.175.08:07:49.60#ibcon#enter sib2, iclass 13, count 0 2006.175.08:07:49.60#ibcon#flushed, iclass 13, count 0 2006.175.08:07:49.60#ibcon#about to write, iclass 13, count 0 2006.175.08:07:49.60#ibcon#wrote, iclass 13, count 0 2006.175.08:07:49.60#ibcon#about to read 3, iclass 13, count 0 2006.175.08:07:49.62#ibcon#read 3, iclass 13, count 0 2006.175.08:07:49.62#ibcon#about to read 4, iclass 13, count 0 2006.175.08:07:49.62#ibcon#read 4, iclass 13, count 0 2006.175.08:07:49.62#ibcon#about to read 5, iclass 13, count 0 2006.175.08:07:49.62#ibcon#read 5, iclass 13, count 0 2006.175.08:07:49.62#ibcon#about to read 6, iclass 13, count 0 2006.175.08:07:49.62#ibcon#read 6, iclass 13, count 0 2006.175.08:07:49.62#ibcon#end of sib2, iclass 13, count 0 2006.175.08:07:49.62#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:07:49.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:07:49.62#ibcon#[25=USB\r\n] 2006.175.08:07:49.62#ibcon#*before write, iclass 13, count 0 2006.175.08:07:49.62#ibcon#enter sib2, iclass 13, count 0 2006.175.08:07:49.62#ibcon#flushed, iclass 13, count 0 2006.175.08:07:49.62#ibcon#about to write, iclass 13, count 0 2006.175.08:07:49.62#ibcon#wrote, iclass 13, count 0 2006.175.08:07:49.62#ibcon#about to read 3, iclass 13, count 0 2006.175.08:07:49.65#ibcon#read 3, iclass 13, count 0 2006.175.08:07:49.65#ibcon#about to read 4, iclass 13, count 0 2006.175.08:07:49.65#ibcon#read 4, iclass 13, count 0 2006.175.08:07:49.65#ibcon#about to read 5, iclass 13, count 0 2006.175.08:07:49.65#ibcon#read 5, iclass 13, count 0 2006.175.08:07:49.65#ibcon#about to read 6, iclass 13, count 0 2006.175.08:07:49.65#ibcon#read 6, iclass 13, count 0 2006.175.08:07:49.65#ibcon#end of sib2, iclass 13, count 0 2006.175.08:07:49.65#ibcon#*after write, iclass 13, count 0 2006.175.08:07:49.65#ibcon#*before return 0, iclass 13, count 0 2006.175.08:07:49.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:49.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:49.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:07:49.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:07:49.65$vc4f8/valo=6,772.99 2006.175.08:07:49.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.08:07:49.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.08:07:49.65#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:49.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:49.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:49.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:49.65#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:07:49.65#ibcon#first serial, iclass 15, count 0 2006.175.08:07:49.65#ibcon#enter sib2, iclass 15, count 0 2006.175.08:07:49.65#ibcon#flushed, iclass 15, count 0 2006.175.08:07:49.65#ibcon#about to write, iclass 15, count 0 2006.175.08:07:49.65#ibcon#wrote, iclass 15, count 0 2006.175.08:07:49.65#ibcon#about to read 3, iclass 15, count 0 2006.175.08:07:49.67#ibcon#read 3, iclass 15, count 0 2006.175.08:07:49.67#ibcon#about to read 4, iclass 15, count 0 2006.175.08:07:49.67#ibcon#read 4, iclass 15, count 0 2006.175.08:07:49.67#ibcon#about to read 5, iclass 15, count 0 2006.175.08:07:49.67#ibcon#read 5, iclass 15, count 0 2006.175.08:07:49.67#ibcon#about to read 6, iclass 15, count 0 2006.175.08:07:49.67#ibcon#read 6, iclass 15, count 0 2006.175.08:07:49.67#ibcon#end of sib2, iclass 15, count 0 2006.175.08:07:49.67#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:07:49.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:07:49.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:07:49.67#ibcon#*before write, iclass 15, count 0 2006.175.08:07:49.67#ibcon#enter sib2, iclass 15, count 0 2006.175.08:07:49.67#ibcon#flushed, iclass 15, count 0 2006.175.08:07:49.67#ibcon#about to write, iclass 15, count 0 2006.175.08:07:49.67#ibcon#wrote, iclass 15, count 0 2006.175.08:07:49.67#ibcon#about to read 3, iclass 15, count 0 2006.175.08:07:49.71#ibcon#read 3, iclass 15, count 0 2006.175.08:07:49.71#ibcon#about to read 4, iclass 15, count 0 2006.175.08:07:49.71#ibcon#read 4, iclass 15, count 0 2006.175.08:07:49.71#ibcon#about to read 5, iclass 15, count 0 2006.175.08:07:49.71#ibcon#read 5, iclass 15, count 0 2006.175.08:07:49.71#ibcon#about to read 6, iclass 15, count 0 2006.175.08:07:49.71#ibcon#read 6, iclass 15, count 0 2006.175.08:07:49.71#ibcon#end of sib2, iclass 15, count 0 2006.175.08:07:49.71#ibcon#*after write, iclass 15, count 0 2006.175.08:07:49.71#ibcon#*before return 0, iclass 15, count 0 2006.175.08:07:49.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:49.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:49.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:07:49.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:07:49.71$vc4f8/va=6,6 2006.175.08:07:49.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.08:07:49.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.08:07:49.71#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:49.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:07:49.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:07:49.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:07:49.77#ibcon#enter wrdev, iclass 17, count 2 2006.175.08:07:49.77#ibcon#first serial, iclass 17, count 2 2006.175.08:07:49.77#ibcon#enter sib2, iclass 17, count 2 2006.175.08:07:49.77#ibcon#flushed, iclass 17, count 2 2006.175.08:07:49.77#ibcon#about to write, iclass 17, count 2 2006.175.08:07:49.77#ibcon#wrote, iclass 17, count 2 2006.175.08:07:49.77#ibcon#about to read 3, iclass 17, count 2 2006.175.08:07:49.79#ibcon#read 3, iclass 17, count 2 2006.175.08:07:49.79#ibcon#about to read 4, iclass 17, count 2 2006.175.08:07:49.79#ibcon#read 4, iclass 17, count 2 2006.175.08:07:49.79#ibcon#about to read 5, iclass 17, count 2 2006.175.08:07:49.79#ibcon#read 5, iclass 17, count 2 2006.175.08:07:49.79#ibcon#about to read 6, iclass 17, count 2 2006.175.08:07:49.79#ibcon#read 6, iclass 17, count 2 2006.175.08:07:49.79#ibcon#end of sib2, iclass 17, count 2 2006.175.08:07:49.79#ibcon#*mode == 0, iclass 17, count 2 2006.175.08:07:49.79#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.08:07:49.79#ibcon#[25=AT06-06\r\n] 2006.175.08:07:49.79#ibcon#*before write, iclass 17, count 2 2006.175.08:07:49.79#ibcon#enter sib2, iclass 17, count 2 2006.175.08:07:49.79#ibcon#flushed, iclass 17, count 2 2006.175.08:07:49.79#ibcon#about to write, iclass 17, count 2 2006.175.08:07:49.79#ibcon#wrote, iclass 17, count 2 2006.175.08:07:49.79#ibcon#about to read 3, iclass 17, count 2 2006.175.08:07:49.82#ibcon#read 3, iclass 17, count 2 2006.175.08:07:49.82#ibcon#about to read 4, iclass 17, count 2 2006.175.08:07:49.82#ibcon#read 4, iclass 17, count 2 2006.175.08:07:49.82#ibcon#about to read 5, iclass 17, count 2 2006.175.08:07:49.82#ibcon#read 5, iclass 17, count 2 2006.175.08:07:49.82#ibcon#about to read 6, iclass 17, count 2 2006.175.08:07:49.82#ibcon#read 6, iclass 17, count 2 2006.175.08:07:49.82#ibcon#end of sib2, iclass 17, count 2 2006.175.08:07:49.82#ibcon#*after write, iclass 17, count 2 2006.175.08:07:49.82#ibcon#*before return 0, iclass 17, count 2 2006.175.08:07:49.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:07:49.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:07:49.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.08:07:49.82#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:49.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:07:49.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:07:49.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:07:49.94#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:07:49.94#ibcon#first serial, iclass 17, count 0 2006.175.08:07:49.94#ibcon#enter sib2, iclass 17, count 0 2006.175.08:07:49.94#ibcon#flushed, iclass 17, count 0 2006.175.08:07:49.94#ibcon#about to write, iclass 17, count 0 2006.175.08:07:49.94#ibcon#wrote, iclass 17, count 0 2006.175.08:07:49.94#ibcon#about to read 3, iclass 17, count 0 2006.175.08:07:49.96#ibcon#read 3, iclass 17, count 0 2006.175.08:07:49.96#ibcon#about to read 4, iclass 17, count 0 2006.175.08:07:49.96#ibcon#read 4, iclass 17, count 0 2006.175.08:07:49.96#ibcon#about to read 5, iclass 17, count 0 2006.175.08:07:49.96#ibcon#read 5, iclass 17, count 0 2006.175.08:07:49.96#ibcon#about to read 6, iclass 17, count 0 2006.175.08:07:49.96#ibcon#read 6, iclass 17, count 0 2006.175.08:07:49.96#ibcon#end of sib2, iclass 17, count 0 2006.175.08:07:49.96#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:07:49.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:07:49.96#ibcon#[25=USB\r\n] 2006.175.08:07:49.96#ibcon#*before write, iclass 17, count 0 2006.175.08:07:49.96#ibcon#enter sib2, iclass 17, count 0 2006.175.08:07:49.96#ibcon#flushed, iclass 17, count 0 2006.175.08:07:49.96#ibcon#about to write, iclass 17, count 0 2006.175.08:07:49.96#ibcon#wrote, iclass 17, count 0 2006.175.08:07:49.96#ibcon#about to read 3, iclass 17, count 0 2006.175.08:07:49.99#ibcon#read 3, iclass 17, count 0 2006.175.08:07:49.99#ibcon#about to read 4, iclass 17, count 0 2006.175.08:07:49.99#ibcon#read 4, iclass 17, count 0 2006.175.08:07:49.99#ibcon#about to read 5, iclass 17, count 0 2006.175.08:07:49.99#ibcon#read 5, iclass 17, count 0 2006.175.08:07:49.99#ibcon#about to read 6, iclass 17, count 0 2006.175.08:07:49.99#ibcon#read 6, iclass 17, count 0 2006.175.08:07:49.99#ibcon#end of sib2, iclass 17, count 0 2006.175.08:07:49.99#ibcon#*after write, iclass 17, count 0 2006.175.08:07:49.99#ibcon#*before return 0, iclass 17, count 0 2006.175.08:07:49.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:07:49.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:07:49.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:07:49.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:07:49.99$vc4f8/valo=7,832.99 2006.175.08:07:49.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.08:07:49.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.08:07:49.99#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:49.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:07:49.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:07:49.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:07:49.99#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:07:49.99#ibcon#first serial, iclass 19, count 0 2006.175.08:07:49.99#ibcon#enter sib2, iclass 19, count 0 2006.175.08:07:49.99#ibcon#flushed, iclass 19, count 0 2006.175.08:07:49.99#ibcon#about to write, iclass 19, count 0 2006.175.08:07:49.99#ibcon#wrote, iclass 19, count 0 2006.175.08:07:49.99#ibcon#about to read 3, iclass 19, count 0 2006.175.08:07:50.01#ibcon#read 3, iclass 19, count 0 2006.175.08:07:50.01#ibcon#about to read 4, iclass 19, count 0 2006.175.08:07:50.01#ibcon#read 4, iclass 19, count 0 2006.175.08:07:50.01#ibcon#about to read 5, iclass 19, count 0 2006.175.08:07:50.01#ibcon#read 5, iclass 19, count 0 2006.175.08:07:50.01#ibcon#about to read 6, iclass 19, count 0 2006.175.08:07:50.01#ibcon#read 6, iclass 19, count 0 2006.175.08:07:50.01#ibcon#end of sib2, iclass 19, count 0 2006.175.08:07:50.01#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:07:50.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:07:50.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:07:50.01#ibcon#*before write, iclass 19, count 0 2006.175.08:07:50.01#ibcon#enter sib2, iclass 19, count 0 2006.175.08:07:50.01#ibcon#flushed, iclass 19, count 0 2006.175.08:07:50.01#ibcon#about to write, iclass 19, count 0 2006.175.08:07:50.01#ibcon#wrote, iclass 19, count 0 2006.175.08:07:50.01#ibcon#about to read 3, iclass 19, count 0 2006.175.08:07:50.05#ibcon#read 3, iclass 19, count 0 2006.175.08:07:50.05#ibcon#about to read 4, iclass 19, count 0 2006.175.08:07:50.05#ibcon#read 4, iclass 19, count 0 2006.175.08:07:50.05#ibcon#about to read 5, iclass 19, count 0 2006.175.08:07:50.05#ibcon#read 5, iclass 19, count 0 2006.175.08:07:50.05#ibcon#about to read 6, iclass 19, count 0 2006.175.08:07:50.05#ibcon#read 6, iclass 19, count 0 2006.175.08:07:50.05#ibcon#end of sib2, iclass 19, count 0 2006.175.08:07:50.05#ibcon#*after write, iclass 19, count 0 2006.175.08:07:50.05#ibcon#*before return 0, iclass 19, count 0 2006.175.08:07:50.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:07:50.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:07:50.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:07:50.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:07:50.05$vc4f8/va=7,6 2006.175.08:07:50.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.08:07:50.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.08:07:50.05#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:50.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:07:50.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:07:50.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:07:50.11#ibcon#enter wrdev, iclass 21, count 2 2006.175.08:07:50.11#ibcon#first serial, iclass 21, count 2 2006.175.08:07:50.11#ibcon#enter sib2, iclass 21, count 2 2006.175.08:07:50.11#ibcon#flushed, iclass 21, count 2 2006.175.08:07:50.11#ibcon#about to write, iclass 21, count 2 2006.175.08:07:50.11#ibcon#wrote, iclass 21, count 2 2006.175.08:07:50.11#ibcon#about to read 3, iclass 21, count 2 2006.175.08:07:50.13#ibcon#read 3, iclass 21, count 2 2006.175.08:07:50.13#ibcon#about to read 4, iclass 21, count 2 2006.175.08:07:50.13#ibcon#read 4, iclass 21, count 2 2006.175.08:07:50.13#ibcon#about to read 5, iclass 21, count 2 2006.175.08:07:50.13#ibcon#read 5, iclass 21, count 2 2006.175.08:07:50.13#ibcon#about to read 6, iclass 21, count 2 2006.175.08:07:50.13#ibcon#read 6, iclass 21, count 2 2006.175.08:07:50.13#ibcon#end of sib2, iclass 21, count 2 2006.175.08:07:50.13#ibcon#*mode == 0, iclass 21, count 2 2006.175.08:07:50.13#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.08:07:50.13#ibcon#[25=AT07-06\r\n] 2006.175.08:07:50.13#ibcon#*before write, iclass 21, count 2 2006.175.08:07:50.13#ibcon#enter sib2, iclass 21, count 2 2006.175.08:07:50.13#ibcon#flushed, iclass 21, count 2 2006.175.08:07:50.13#ibcon#about to write, iclass 21, count 2 2006.175.08:07:50.13#ibcon#wrote, iclass 21, count 2 2006.175.08:07:50.13#ibcon#about to read 3, iclass 21, count 2 2006.175.08:07:50.16#ibcon#read 3, iclass 21, count 2 2006.175.08:07:50.16#ibcon#about to read 4, iclass 21, count 2 2006.175.08:07:50.16#ibcon#read 4, iclass 21, count 2 2006.175.08:07:50.16#ibcon#about to read 5, iclass 21, count 2 2006.175.08:07:50.16#ibcon#read 5, iclass 21, count 2 2006.175.08:07:50.16#ibcon#about to read 6, iclass 21, count 2 2006.175.08:07:50.16#ibcon#read 6, iclass 21, count 2 2006.175.08:07:50.16#ibcon#end of sib2, iclass 21, count 2 2006.175.08:07:50.16#ibcon#*after write, iclass 21, count 2 2006.175.08:07:50.16#ibcon#*before return 0, iclass 21, count 2 2006.175.08:07:50.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:07:50.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:07:50.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.08:07:50.16#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:50.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:07:50.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:07:50.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:07:50.28#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:07:50.28#ibcon#first serial, iclass 21, count 0 2006.175.08:07:50.28#ibcon#enter sib2, iclass 21, count 0 2006.175.08:07:50.28#ibcon#flushed, iclass 21, count 0 2006.175.08:07:50.28#ibcon#about to write, iclass 21, count 0 2006.175.08:07:50.28#ibcon#wrote, iclass 21, count 0 2006.175.08:07:50.28#ibcon#about to read 3, iclass 21, count 0 2006.175.08:07:50.30#ibcon#read 3, iclass 21, count 0 2006.175.08:07:50.30#ibcon#about to read 4, iclass 21, count 0 2006.175.08:07:50.30#ibcon#read 4, iclass 21, count 0 2006.175.08:07:50.30#ibcon#about to read 5, iclass 21, count 0 2006.175.08:07:50.30#ibcon#read 5, iclass 21, count 0 2006.175.08:07:50.30#ibcon#about to read 6, iclass 21, count 0 2006.175.08:07:50.30#ibcon#read 6, iclass 21, count 0 2006.175.08:07:50.30#ibcon#end of sib2, iclass 21, count 0 2006.175.08:07:50.30#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:07:50.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:07:50.30#ibcon#[25=USB\r\n] 2006.175.08:07:50.30#ibcon#*before write, iclass 21, count 0 2006.175.08:07:50.30#ibcon#enter sib2, iclass 21, count 0 2006.175.08:07:50.30#ibcon#flushed, iclass 21, count 0 2006.175.08:07:50.30#ibcon#about to write, iclass 21, count 0 2006.175.08:07:50.30#ibcon#wrote, iclass 21, count 0 2006.175.08:07:50.30#ibcon#about to read 3, iclass 21, count 0 2006.175.08:07:50.33#ibcon#read 3, iclass 21, count 0 2006.175.08:07:50.33#ibcon#about to read 4, iclass 21, count 0 2006.175.08:07:50.33#ibcon#read 4, iclass 21, count 0 2006.175.08:07:50.33#ibcon#about to read 5, iclass 21, count 0 2006.175.08:07:50.33#ibcon#read 5, iclass 21, count 0 2006.175.08:07:50.33#ibcon#about to read 6, iclass 21, count 0 2006.175.08:07:50.33#ibcon#read 6, iclass 21, count 0 2006.175.08:07:50.33#ibcon#end of sib2, iclass 21, count 0 2006.175.08:07:50.33#ibcon#*after write, iclass 21, count 0 2006.175.08:07:50.33#ibcon#*before return 0, iclass 21, count 0 2006.175.08:07:50.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:07:50.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:07:50.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:07:50.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:07:50.33$vc4f8/valo=8,852.99 2006.175.08:07:50.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.08:07:50.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.08:07:50.33#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:50.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:07:50.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:07:50.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:07:50.33#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:07:50.33#ibcon#first serial, iclass 23, count 0 2006.175.08:07:50.33#ibcon#enter sib2, iclass 23, count 0 2006.175.08:07:50.33#ibcon#flushed, iclass 23, count 0 2006.175.08:07:50.33#ibcon#about to write, iclass 23, count 0 2006.175.08:07:50.33#ibcon#wrote, iclass 23, count 0 2006.175.08:07:50.33#ibcon#about to read 3, iclass 23, count 0 2006.175.08:07:50.35#ibcon#read 3, iclass 23, count 0 2006.175.08:07:50.35#ibcon#about to read 4, iclass 23, count 0 2006.175.08:07:50.35#ibcon#read 4, iclass 23, count 0 2006.175.08:07:50.35#ibcon#about to read 5, iclass 23, count 0 2006.175.08:07:50.35#ibcon#read 5, iclass 23, count 0 2006.175.08:07:50.35#ibcon#about to read 6, iclass 23, count 0 2006.175.08:07:50.35#ibcon#read 6, iclass 23, count 0 2006.175.08:07:50.35#ibcon#end of sib2, iclass 23, count 0 2006.175.08:07:50.35#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:07:50.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:07:50.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:07:50.35#ibcon#*before write, iclass 23, count 0 2006.175.08:07:50.35#ibcon#enter sib2, iclass 23, count 0 2006.175.08:07:50.35#ibcon#flushed, iclass 23, count 0 2006.175.08:07:50.35#ibcon#about to write, iclass 23, count 0 2006.175.08:07:50.35#ibcon#wrote, iclass 23, count 0 2006.175.08:07:50.35#ibcon#about to read 3, iclass 23, count 0 2006.175.08:07:50.39#ibcon#read 3, iclass 23, count 0 2006.175.08:07:50.39#ibcon#about to read 4, iclass 23, count 0 2006.175.08:07:50.39#ibcon#read 4, iclass 23, count 0 2006.175.08:07:50.39#ibcon#about to read 5, iclass 23, count 0 2006.175.08:07:50.39#ibcon#read 5, iclass 23, count 0 2006.175.08:07:50.39#ibcon#about to read 6, iclass 23, count 0 2006.175.08:07:50.39#ibcon#read 6, iclass 23, count 0 2006.175.08:07:50.39#ibcon#end of sib2, iclass 23, count 0 2006.175.08:07:50.39#ibcon#*after write, iclass 23, count 0 2006.175.08:07:50.39#ibcon#*before return 0, iclass 23, count 0 2006.175.08:07:50.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:07:50.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:07:50.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:07:50.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:07:50.39$vc4f8/va=8,6 2006.175.08:07:50.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.08:07:50.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.08:07:50.39#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:50.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:07:50.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:07:50.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:07:50.45#ibcon#enter wrdev, iclass 25, count 2 2006.175.08:07:50.45#ibcon#first serial, iclass 25, count 2 2006.175.08:07:50.45#ibcon#enter sib2, iclass 25, count 2 2006.175.08:07:50.45#ibcon#flushed, iclass 25, count 2 2006.175.08:07:50.45#ibcon#about to write, iclass 25, count 2 2006.175.08:07:50.45#ibcon#wrote, iclass 25, count 2 2006.175.08:07:50.45#ibcon#about to read 3, iclass 25, count 2 2006.175.08:07:50.47#ibcon#read 3, iclass 25, count 2 2006.175.08:07:50.47#ibcon#about to read 4, iclass 25, count 2 2006.175.08:07:50.47#ibcon#read 4, iclass 25, count 2 2006.175.08:07:50.47#ibcon#about to read 5, iclass 25, count 2 2006.175.08:07:50.47#ibcon#read 5, iclass 25, count 2 2006.175.08:07:50.47#ibcon#about to read 6, iclass 25, count 2 2006.175.08:07:50.47#ibcon#read 6, iclass 25, count 2 2006.175.08:07:50.47#ibcon#end of sib2, iclass 25, count 2 2006.175.08:07:50.47#ibcon#*mode == 0, iclass 25, count 2 2006.175.08:07:50.47#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.08:07:50.47#ibcon#[25=AT08-06\r\n] 2006.175.08:07:50.47#ibcon#*before write, iclass 25, count 2 2006.175.08:07:50.47#ibcon#enter sib2, iclass 25, count 2 2006.175.08:07:50.47#ibcon#flushed, iclass 25, count 2 2006.175.08:07:50.47#ibcon#about to write, iclass 25, count 2 2006.175.08:07:50.47#ibcon#wrote, iclass 25, count 2 2006.175.08:07:50.47#ibcon#about to read 3, iclass 25, count 2 2006.175.08:07:50.50#ibcon#read 3, iclass 25, count 2 2006.175.08:07:50.50#ibcon#about to read 4, iclass 25, count 2 2006.175.08:07:50.50#ibcon#read 4, iclass 25, count 2 2006.175.08:07:50.50#ibcon#about to read 5, iclass 25, count 2 2006.175.08:07:50.50#ibcon#read 5, iclass 25, count 2 2006.175.08:07:50.50#ibcon#about to read 6, iclass 25, count 2 2006.175.08:07:50.50#ibcon#read 6, iclass 25, count 2 2006.175.08:07:50.50#ibcon#end of sib2, iclass 25, count 2 2006.175.08:07:50.50#ibcon#*after write, iclass 25, count 2 2006.175.08:07:50.50#ibcon#*before return 0, iclass 25, count 2 2006.175.08:07:50.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:07:50.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:07:50.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.08:07:50.50#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:50.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:07:50.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:07:50.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:07:50.62#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:07:50.62#ibcon#first serial, iclass 25, count 0 2006.175.08:07:50.62#ibcon#enter sib2, iclass 25, count 0 2006.175.08:07:50.62#ibcon#flushed, iclass 25, count 0 2006.175.08:07:50.62#ibcon#about to write, iclass 25, count 0 2006.175.08:07:50.62#ibcon#wrote, iclass 25, count 0 2006.175.08:07:50.62#ibcon#about to read 3, iclass 25, count 0 2006.175.08:07:50.64#ibcon#read 3, iclass 25, count 0 2006.175.08:07:50.64#ibcon#about to read 4, iclass 25, count 0 2006.175.08:07:50.64#ibcon#read 4, iclass 25, count 0 2006.175.08:07:50.64#ibcon#about to read 5, iclass 25, count 0 2006.175.08:07:50.64#ibcon#read 5, iclass 25, count 0 2006.175.08:07:50.64#ibcon#about to read 6, iclass 25, count 0 2006.175.08:07:50.64#ibcon#read 6, iclass 25, count 0 2006.175.08:07:50.64#ibcon#end of sib2, iclass 25, count 0 2006.175.08:07:50.64#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:07:50.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:07:50.64#ibcon#[25=USB\r\n] 2006.175.08:07:50.64#ibcon#*before write, iclass 25, count 0 2006.175.08:07:50.64#ibcon#enter sib2, iclass 25, count 0 2006.175.08:07:50.64#ibcon#flushed, iclass 25, count 0 2006.175.08:07:50.64#ibcon#about to write, iclass 25, count 0 2006.175.08:07:50.64#ibcon#wrote, iclass 25, count 0 2006.175.08:07:50.64#ibcon#about to read 3, iclass 25, count 0 2006.175.08:07:50.67#ibcon#read 3, iclass 25, count 0 2006.175.08:07:50.67#ibcon#about to read 4, iclass 25, count 0 2006.175.08:07:50.67#ibcon#read 4, iclass 25, count 0 2006.175.08:07:50.67#ibcon#about to read 5, iclass 25, count 0 2006.175.08:07:50.67#ibcon#read 5, iclass 25, count 0 2006.175.08:07:50.67#ibcon#about to read 6, iclass 25, count 0 2006.175.08:07:50.67#ibcon#read 6, iclass 25, count 0 2006.175.08:07:50.67#ibcon#end of sib2, iclass 25, count 0 2006.175.08:07:50.67#ibcon#*after write, iclass 25, count 0 2006.175.08:07:50.67#ibcon#*before return 0, iclass 25, count 0 2006.175.08:07:50.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:07:50.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:07:50.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:07:50.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:07:50.67$vc4f8/vblo=1,632.99 2006.175.08:07:50.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.08:07:50.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.08:07:50.67#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:50.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:07:50.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:07:50.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:07:50.67#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:07:50.67#ibcon#first serial, iclass 27, count 0 2006.175.08:07:50.67#ibcon#enter sib2, iclass 27, count 0 2006.175.08:07:50.67#ibcon#flushed, iclass 27, count 0 2006.175.08:07:50.67#ibcon#about to write, iclass 27, count 0 2006.175.08:07:50.67#ibcon#wrote, iclass 27, count 0 2006.175.08:07:50.67#ibcon#about to read 3, iclass 27, count 0 2006.175.08:07:50.69#ibcon#read 3, iclass 27, count 0 2006.175.08:07:50.69#ibcon#about to read 4, iclass 27, count 0 2006.175.08:07:50.69#ibcon#read 4, iclass 27, count 0 2006.175.08:07:50.69#ibcon#about to read 5, iclass 27, count 0 2006.175.08:07:50.69#ibcon#read 5, iclass 27, count 0 2006.175.08:07:50.69#ibcon#about to read 6, iclass 27, count 0 2006.175.08:07:50.69#ibcon#read 6, iclass 27, count 0 2006.175.08:07:50.69#ibcon#end of sib2, iclass 27, count 0 2006.175.08:07:50.69#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:07:50.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:07:50.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:07:50.69#ibcon#*before write, iclass 27, count 0 2006.175.08:07:50.69#ibcon#enter sib2, iclass 27, count 0 2006.175.08:07:50.69#ibcon#flushed, iclass 27, count 0 2006.175.08:07:50.69#ibcon#about to write, iclass 27, count 0 2006.175.08:07:50.69#ibcon#wrote, iclass 27, count 0 2006.175.08:07:50.69#ibcon#about to read 3, iclass 27, count 0 2006.175.08:07:50.73#ibcon#read 3, iclass 27, count 0 2006.175.08:07:50.73#ibcon#about to read 4, iclass 27, count 0 2006.175.08:07:50.73#ibcon#read 4, iclass 27, count 0 2006.175.08:07:50.73#ibcon#about to read 5, iclass 27, count 0 2006.175.08:07:50.73#ibcon#read 5, iclass 27, count 0 2006.175.08:07:50.73#ibcon#about to read 6, iclass 27, count 0 2006.175.08:07:50.73#ibcon#read 6, iclass 27, count 0 2006.175.08:07:50.73#ibcon#end of sib2, iclass 27, count 0 2006.175.08:07:50.73#ibcon#*after write, iclass 27, count 0 2006.175.08:07:50.73#ibcon#*before return 0, iclass 27, count 0 2006.175.08:07:50.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:07:50.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:07:50.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:07:50.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:07:50.73$vc4f8/vb=1,4 2006.175.08:07:50.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.175.08:07:50.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.175.08:07:50.73#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:50.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:07:50.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:07:50.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:07:50.73#ibcon#enter wrdev, iclass 29, count 2 2006.175.08:07:50.73#ibcon#first serial, iclass 29, count 2 2006.175.08:07:50.73#ibcon#enter sib2, iclass 29, count 2 2006.175.08:07:50.73#ibcon#flushed, iclass 29, count 2 2006.175.08:07:50.73#ibcon#about to write, iclass 29, count 2 2006.175.08:07:50.73#ibcon#wrote, iclass 29, count 2 2006.175.08:07:50.73#ibcon#about to read 3, iclass 29, count 2 2006.175.08:07:50.75#ibcon#read 3, iclass 29, count 2 2006.175.08:07:50.75#ibcon#about to read 4, iclass 29, count 2 2006.175.08:07:50.75#ibcon#read 4, iclass 29, count 2 2006.175.08:07:50.75#ibcon#about to read 5, iclass 29, count 2 2006.175.08:07:50.75#ibcon#read 5, iclass 29, count 2 2006.175.08:07:50.75#ibcon#about to read 6, iclass 29, count 2 2006.175.08:07:50.75#ibcon#read 6, iclass 29, count 2 2006.175.08:07:50.75#ibcon#end of sib2, iclass 29, count 2 2006.175.08:07:50.75#ibcon#*mode == 0, iclass 29, count 2 2006.175.08:07:50.75#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.175.08:07:50.75#ibcon#[27=AT01-04\r\n] 2006.175.08:07:50.75#ibcon#*before write, iclass 29, count 2 2006.175.08:07:50.75#ibcon#enter sib2, iclass 29, count 2 2006.175.08:07:50.75#ibcon#flushed, iclass 29, count 2 2006.175.08:07:50.75#ibcon#about to write, iclass 29, count 2 2006.175.08:07:50.75#ibcon#wrote, iclass 29, count 2 2006.175.08:07:50.75#ibcon#about to read 3, iclass 29, count 2 2006.175.08:07:50.78#ibcon#read 3, iclass 29, count 2 2006.175.08:07:50.78#ibcon#about to read 4, iclass 29, count 2 2006.175.08:07:50.78#ibcon#read 4, iclass 29, count 2 2006.175.08:07:50.78#ibcon#about to read 5, iclass 29, count 2 2006.175.08:07:50.78#ibcon#read 5, iclass 29, count 2 2006.175.08:07:50.78#ibcon#about to read 6, iclass 29, count 2 2006.175.08:07:50.78#ibcon#read 6, iclass 29, count 2 2006.175.08:07:50.78#ibcon#end of sib2, iclass 29, count 2 2006.175.08:07:50.78#ibcon#*after write, iclass 29, count 2 2006.175.08:07:50.78#ibcon#*before return 0, iclass 29, count 2 2006.175.08:07:50.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:07:50.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:07:50.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.175.08:07:50.78#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:50.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:07:50.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:07:50.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:07:50.90#ibcon#enter wrdev, iclass 29, count 0 2006.175.08:07:50.90#ibcon#first serial, iclass 29, count 0 2006.175.08:07:50.90#ibcon#enter sib2, iclass 29, count 0 2006.175.08:07:50.90#ibcon#flushed, iclass 29, count 0 2006.175.08:07:50.90#ibcon#about to write, iclass 29, count 0 2006.175.08:07:50.90#ibcon#wrote, iclass 29, count 0 2006.175.08:07:50.90#ibcon#about to read 3, iclass 29, count 0 2006.175.08:07:50.92#ibcon#read 3, iclass 29, count 0 2006.175.08:07:50.92#ibcon#about to read 4, iclass 29, count 0 2006.175.08:07:50.92#ibcon#read 4, iclass 29, count 0 2006.175.08:07:50.92#ibcon#about to read 5, iclass 29, count 0 2006.175.08:07:50.92#ibcon#read 5, iclass 29, count 0 2006.175.08:07:50.92#ibcon#about to read 6, iclass 29, count 0 2006.175.08:07:50.92#ibcon#read 6, iclass 29, count 0 2006.175.08:07:50.92#ibcon#end of sib2, iclass 29, count 0 2006.175.08:07:50.92#ibcon#*mode == 0, iclass 29, count 0 2006.175.08:07:50.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.08:07:50.92#ibcon#[27=USB\r\n] 2006.175.08:07:50.92#ibcon#*before write, iclass 29, count 0 2006.175.08:07:50.92#ibcon#enter sib2, iclass 29, count 0 2006.175.08:07:50.92#ibcon#flushed, iclass 29, count 0 2006.175.08:07:50.92#ibcon#about to write, iclass 29, count 0 2006.175.08:07:50.92#ibcon#wrote, iclass 29, count 0 2006.175.08:07:50.92#ibcon#about to read 3, iclass 29, count 0 2006.175.08:07:50.95#ibcon#read 3, iclass 29, count 0 2006.175.08:07:50.95#ibcon#about to read 4, iclass 29, count 0 2006.175.08:07:50.95#ibcon#read 4, iclass 29, count 0 2006.175.08:07:50.95#ibcon#about to read 5, iclass 29, count 0 2006.175.08:07:50.95#ibcon#read 5, iclass 29, count 0 2006.175.08:07:50.95#ibcon#about to read 6, iclass 29, count 0 2006.175.08:07:50.95#ibcon#read 6, iclass 29, count 0 2006.175.08:07:50.95#ibcon#end of sib2, iclass 29, count 0 2006.175.08:07:50.95#ibcon#*after write, iclass 29, count 0 2006.175.08:07:50.95#ibcon#*before return 0, iclass 29, count 0 2006.175.08:07:50.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:07:50.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:07:50.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.08:07:50.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.08:07:50.95$vc4f8/vblo=2,640.99 2006.175.08:07:50.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.08:07:50.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.08:07:50.95#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:50.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:50.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:50.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:50.95#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:07:50.95#ibcon#first serial, iclass 31, count 0 2006.175.08:07:50.95#ibcon#enter sib2, iclass 31, count 0 2006.175.08:07:50.95#ibcon#flushed, iclass 31, count 0 2006.175.08:07:50.95#ibcon#about to write, iclass 31, count 0 2006.175.08:07:50.95#ibcon#wrote, iclass 31, count 0 2006.175.08:07:50.95#ibcon#about to read 3, iclass 31, count 0 2006.175.08:07:50.97#ibcon#read 3, iclass 31, count 0 2006.175.08:07:50.97#ibcon#about to read 4, iclass 31, count 0 2006.175.08:07:50.97#ibcon#read 4, iclass 31, count 0 2006.175.08:07:50.97#ibcon#about to read 5, iclass 31, count 0 2006.175.08:07:50.97#ibcon#read 5, iclass 31, count 0 2006.175.08:07:50.97#ibcon#about to read 6, iclass 31, count 0 2006.175.08:07:50.97#ibcon#read 6, iclass 31, count 0 2006.175.08:07:50.97#ibcon#end of sib2, iclass 31, count 0 2006.175.08:07:50.97#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:07:50.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:07:50.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:07:50.97#ibcon#*before write, iclass 31, count 0 2006.175.08:07:50.97#ibcon#enter sib2, iclass 31, count 0 2006.175.08:07:50.97#ibcon#flushed, iclass 31, count 0 2006.175.08:07:50.97#ibcon#about to write, iclass 31, count 0 2006.175.08:07:50.97#ibcon#wrote, iclass 31, count 0 2006.175.08:07:50.97#ibcon#about to read 3, iclass 31, count 0 2006.175.08:07:51.01#ibcon#read 3, iclass 31, count 0 2006.175.08:07:51.01#ibcon#about to read 4, iclass 31, count 0 2006.175.08:07:51.01#ibcon#read 4, iclass 31, count 0 2006.175.08:07:51.01#ibcon#about to read 5, iclass 31, count 0 2006.175.08:07:51.01#ibcon#read 5, iclass 31, count 0 2006.175.08:07:51.01#ibcon#about to read 6, iclass 31, count 0 2006.175.08:07:51.01#ibcon#read 6, iclass 31, count 0 2006.175.08:07:51.01#ibcon#end of sib2, iclass 31, count 0 2006.175.08:07:51.01#ibcon#*after write, iclass 31, count 0 2006.175.08:07:51.01#ibcon#*before return 0, iclass 31, count 0 2006.175.08:07:51.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:51.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:07:51.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:07:51.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:07:51.01$vc4f8/vb=2,4 2006.175.08:07:51.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.08:07:51.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.08:07:51.01#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:51.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:51.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:51.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:51.07#ibcon#enter wrdev, iclass 33, count 2 2006.175.08:07:51.07#ibcon#first serial, iclass 33, count 2 2006.175.08:07:51.07#ibcon#enter sib2, iclass 33, count 2 2006.175.08:07:51.07#ibcon#flushed, iclass 33, count 2 2006.175.08:07:51.07#ibcon#about to write, iclass 33, count 2 2006.175.08:07:51.07#ibcon#wrote, iclass 33, count 2 2006.175.08:07:51.07#ibcon#about to read 3, iclass 33, count 2 2006.175.08:07:51.09#ibcon#read 3, iclass 33, count 2 2006.175.08:07:51.09#ibcon#about to read 4, iclass 33, count 2 2006.175.08:07:51.09#ibcon#read 4, iclass 33, count 2 2006.175.08:07:51.09#ibcon#about to read 5, iclass 33, count 2 2006.175.08:07:51.09#ibcon#read 5, iclass 33, count 2 2006.175.08:07:51.09#ibcon#about to read 6, iclass 33, count 2 2006.175.08:07:51.09#ibcon#read 6, iclass 33, count 2 2006.175.08:07:51.09#ibcon#end of sib2, iclass 33, count 2 2006.175.08:07:51.09#ibcon#*mode == 0, iclass 33, count 2 2006.175.08:07:51.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.08:07:51.09#ibcon#[27=AT02-04\r\n] 2006.175.08:07:51.09#ibcon#*before write, iclass 33, count 2 2006.175.08:07:51.09#ibcon#enter sib2, iclass 33, count 2 2006.175.08:07:51.09#ibcon#flushed, iclass 33, count 2 2006.175.08:07:51.09#ibcon#about to write, iclass 33, count 2 2006.175.08:07:51.09#ibcon#wrote, iclass 33, count 2 2006.175.08:07:51.09#ibcon#about to read 3, iclass 33, count 2 2006.175.08:07:51.12#ibcon#read 3, iclass 33, count 2 2006.175.08:07:51.12#ibcon#about to read 4, iclass 33, count 2 2006.175.08:07:51.12#ibcon#read 4, iclass 33, count 2 2006.175.08:07:51.12#ibcon#about to read 5, iclass 33, count 2 2006.175.08:07:51.12#ibcon#read 5, iclass 33, count 2 2006.175.08:07:51.12#ibcon#about to read 6, iclass 33, count 2 2006.175.08:07:51.12#ibcon#read 6, iclass 33, count 2 2006.175.08:07:51.12#ibcon#end of sib2, iclass 33, count 2 2006.175.08:07:51.12#ibcon#*after write, iclass 33, count 2 2006.175.08:07:51.12#ibcon#*before return 0, iclass 33, count 2 2006.175.08:07:51.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:51.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:07:51.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.08:07:51.12#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:51.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:51.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:51.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:51.24#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:07:51.24#ibcon#first serial, iclass 33, count 0 2006.175.08:07:51.24#ibcon#enter sib2, iclass 33, count 0 2006.175.08:07:51.24#ibcon#flushed, iclass 33, count 0 2006.175.08:07:51.24#ibcon#about to write, iclass 33, count 0 2006.175.08:07:51.24#ibcon#wrote, iclass 33, count 0 2006.175.08:07:51.24#ibcon#about to read 3, iclass 33, count 0 2006.175.08:07:51.26#ibcon#read 3, iclass 33, count 0 2006.175.08:07:51.26#ibcon#about to read 4, iclass 33, count 0 2006.175.08:07:51.26#ibcon#read 4, iclass 33, count 0 2006.175.08:07:51.26#ibcon#about to read 5, iclass 33, count 0 2006.175.08:07:51.26#ibcon#read 5, iclass 33, count 0 2006.175.08:07:51.26#ibcon#about to read 6, iclass 33, count 0 2006.175.08:07:51.26#ibcon#read 6, iclass 33, count 0 2006.175.08:07:51.26#ibcon#end of sib2, iclass 33, count 0 2006.175.08:07:51.26#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:07:51.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:07:51.26#ibcon#[27=USB\r\n] 2006.175.08:07:51.26#ibcon#*before write, iclass 33, count 0 2006.175.08:07:51.26#ibcon#enter sib2, iclass 33, count 0 2006.175.08:07:51.26#ibcon#flushed, iclass 33, count 0 2006.175.08:07:51.26#ibcon#about to write, iclass 33, count 0 2006.175.08:07:51.26#ibcon#wrote, iclass 33, count 0 2006.175.08:07:51.26#ibcon#about to read 3, iclass 33, count 0 2006.175.08:07:51.29#ibcon#read 3, iclass 33, count 0 2006.175.08:07:51.29#ibcon#about to read 4, iclass 33, count 0 2006.175.08:07:51.29#ibcon#read 4, iclass 33, count 0 2006.175.08:07:51.29#ibcon#about to read 5, iclass 33, count 0 2006.175.08:07:51.29#ibcon#read 5, iclass 33, count 0 2006.175.08:07:51.29#ibcon#about to read 6, iclass 33, count 0 2006.175.08:07:51.29#ibcon#read 6, iclass 33, count 0 2006.175.08:07:51.29#ibcon#end of sib2, iclass 33, count 0 2006.175.08:07:51.29#ibcon#*after write, iclass 33, count 0 2006.175.08:07:51.29#ibcon#*before return 0, iclass 33, count 0 2006.175.08:07:51.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:51.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:07:51.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:07:51.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:07:51.29$vc4f8/vblo=3,656.99 2006.175.08:07:51.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.08:07:51.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.08:07:51.29#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:51.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:51.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:51.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:51.29#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:07:51.29#ibcon#first serial, iclass 35, count 0 2006.175.08:07:51.29#ibcon#enter sib2, iclass 35, count 0 2006.175.08:07:51.29#ibcon#flushed, iclass 35, count 0 2006.175.08:07:51.29#ibcon#about to write, iclass 35, count 0 2006.175.08:07:51.29#ibcon#wrote, iclass 35, count 0 2006.175.08:07:51.29#ibcon#about to read 3, iclass 35, count 0 2006.175.08:07:51.31#ibcon#read 3, iclass 35, count 0 2006.175.08:07:51.31#ibcon#about to read 4, iclass 35, count 0 2006.175.08:07:51.31#ibcon#read 4, iclass 35, count 0 2006.175.08:07:51.31#ibcon#about to read 5, iclass 35, count 0 2006.175.08:07:51.31#ibcon#read 5, iclass 35, count 0 2006.175.08:07:51.31#ibcon#about to read 6, iclass 35, count 0 2006.175.08:07:51.31#ibcon#read 6, iclass 35, count 0 2006.175.08:07:51.31#ibcon#end of sib2, iclass 35, count 0 2006.175.08:07:51.31#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:07:51.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:07:51.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:07:51.31#ibcon#*before write, iclass 35, count 0 2006.175.08:07:51.31#ibcon#enter sib2, iclass 35, count 0 2006.175.08:07:51.31#ibcon#flushed, iclass 35, count 0 2006.175.08:07:51.31#ibcon#about to write, iclass 35, count 0 2006.175.08:07:51.31#ibcon#wrote, iclass 35, count 0 2006.175.08:07:51.31#ibcon#about to read 3, iclass 35, count 0 2006.175.08:07:51.35#ibcon#read 3, iclass 35, count 0 2006.175.08:07:51.35#ibcon#about to read 4, iclass 35, count 0 2006.175.08:07:51.35#ibcon#read 4, iclass 35, count 0 2006.175.08:07:51.35#ibcon#about to read 5, iclass 35, count 0 2006.175.08:07:51.35#ibcon#read 5, iclass 35, count 0 2006.175.08:07:51.35#ibcon#about to read 6, iclass 35, count 0 2006.175.08:07:51.35#ibcon#read 6, iclass 35, count 0 2006.175.08:07:51.35#ibcon#end of sib2, iclass 35, count 0 2006.175.08:07:51.35#ibcon#*after write, iclass 35, count 0 2006.175.08:07:51.35#ibcon#*before return 0, iclass 35, count 0 2006.175.08:07:51.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:51.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:07:51.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:07:51.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:07:51.35$vc4f8/vb=3,4 2006.175.08:07:51.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.08:07:51.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.08:07:51.35#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:51.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:51.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:51.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:51.41#ibcon#enter wrdev, iclass 37, count 2 2006.175.08:07:51.41#ibcon#first serial, iclass 37, count 2 2006.175.08:07:51.41#ibcon#enter sib2, iclass 37, count 2 2006.175.08:07:51.41#ibcon#flushed, iclass 37, count 2 2006.175.08:07:51.41#ibcon#about to write, iclass 37, count 2 2006.175.08:07:51.41#ibcon#wrote, iclass 37, count 2 2006.175.08:07:51.41#ibcon#about to read 3, iclass 37, count 2 2006.175.08:07:51.43#ibcon#read 3, iclass 37, count 2 2006.175.08:07:51.43#ibcon#about to read 4, iclass 37, count 2 2006.175.08:07:51.43#ibcon#read 4, iclass 37, count 2 2006.175.08:07:51.43#ibcon#about to read 5, iclass 37, count 2 2006.175.08:07:51.43#ibcon#read 5, iclass 37, count 2 2006.175.08:07:51.43#ibcon#about to read 6, iclass 37, count 2 2006.175.08:07:51.43#ibcon#read 6, iclass 37, count 2 2006.175.08:07:51.43#ibcon#end of sib2, iclass 37, count 2 2006.175.08:07:51.43#ibcon#*mode == 0, iclass 37, count 2 2006.175.08:07:51.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.08:07:51.43#ibcon#[27=AT03-04\r\n] 2006.175.08:07:51.43#ibcon#*before write, iclass 37, count 2 2006.175.08:07:51.43#ibcon#enter sib2, iclass 37, count 2 2006.175.08:07:51.43#ibcon#flushed, iclass 37, count 2 2006.175.08:07:51.43#ibcon#about to write, iclass 37, count 2 2006.175.08:07:51.43#ibcon#wrote, iclass 37, count 2 2006.175.08:07:51.43#ibcon#about to read 3, iclass 37, count 2 2006.175.08:07:51.46#ibcon#read 3, iclass 37, count 2 2006.175.08:07:51.46#ibcon#about to read 4, iclass 37, count 2 2006.175.08:07:51.46#ibcon#read 4, iclass 37, count 2 2006.175.08:07:51.46#ibcon#about to read 5, iclass 37, count 2 2006.175.08:07:51.46#ibcon#read 5, iclass 37, count 2 2006.175.08:07:51.46#ibcon#about to read 6, iclass 37, count 2 2006.175.08:07:51.46#ibcon#read 6, iclass 37, count 2 2006.175.08:07:51.46#ibcon#end of sib2, iclass 37, count 2 2006.175.08:07:51.46#ibcon#*after write, iclass 37, count 2 2006.175.08:07:51.46#ibcon#*before return 0, iclass 37, count 2 2006.175.08:07:51.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:51.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:07:51.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.08:07:51.46#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:51.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:51.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:51.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:51.58#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:07:51.58#ibcon#first serial, iclass 37, count 0 2006.175.08:07:51.58#ibcon#enter sib2, iclass 37, count 0 2006.175.08:07:51.58#ibcon#flushed, iclass 37, count 0 2006.175.08:07:51.58#ibcon#about to write, iclass 37, count 0 2006.175.08:07:51.58#ibcon#wrote, iclass 37, count 0 2006.175.08:07:51.58#ibcon#about to read 3, iclass 37, count 0 2006.175.08:07:51.60#ibcon#read 3, iclass 37, count 0 2006.175.08:07:51.60#ibcon#about to read 4, iclass 37, count 0 2006.175.08:07:51.60#ibcon#read 4, iclass 37, count 0 2006.175.08:07:51.60#ibcon#about to read 5, iclass 37, count 0 2006.175.08:07:51.60#ibcon#read 5, iclass 37, count 0 2006.175.08:07:51.60#ibcon#about to read 6, iclass 37, count 0 2006.175.08:07:51.60#ibcon#read 6, iclass 37, count 0 2006.175.08:07:51.60#ibcon#end of sib2, iclass 37, count 0 2006.175.08:07:51.60#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:07:51.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:07:51.60#ibcon#[27=USB\r\n] 2006.175.08:07:51.60#ibcon#*before write, iclass 37, count 0 2006.175.08:07:51.60#ibcon#enter sib2, iclass 37, count 0 2006.175.08:07:51.60#ibcon#flushed, iclass 37, count 0 2006.175.08:07:51.60#ibcon#about to write, iclass 37, count 0 2006.175.08:07:51.60#ibcon#wrote, iclass 37, count 0 2006.175.08:07:51.60#ibcon#about to read 3, iclass 37, count 0 2006.175.08:07:51.63#ibcon#read 3, iclass 37, count 0 2006.175.08:07:51.63#ibcon#about to read 4, iclass 37, count 0 2006.175.08:07:51.63#ibcon#read 4, iclass 37, count 0 2006.175.08:07:51.63#ibcon#about to read 5, iclass 37, count 0 2006.175.08:07:51.63#ibcon#read 5, iclass 37, count 0 2006.175.08:07:51.63#ibcon#about to read 6, iclass 37, count 0 2006.175.08:07:51.63#ibcon#read 6, iclass 37, count 0 2006.175.08:07:51.63#ibcon#end of sib2, iclass 37, count 0 2006.175.08:07:51.63#ibcon#*after write, iclass 37, count 0 2006.175.08:07:51.63#ibcon#*before return 0, iclass 37, count 0 2006.175.08:07:51.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:51.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:07:51.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:07:51.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:07:51.63$vc4f8/vblo=4,712.99 2006.175.08:07:51.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.08:07:51.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.08:07:51.63#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:51.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:51.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:51.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:51.63#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:07:51.63#ibcon#first serial, iclass 39, count 0 2006.175.08:07:51.63#ibcon#enter sib2, iclass 39, count 0 2006.175.08:07:51.63#ibcon#flushed, iclass 39, count 0 2006.175.08:07:51.63#ibcon#about to write, iclass 39, count 0 2006.175.08:07:51.63#ibcon#wrote, iclass 39, count 0 2006.175.08:07:51.63#ibcon#about to read 3, iclass 39, count 0 2006.175.08:07:51.65#ibcon#read 3, iclass 39, count 0 2006.175.08:07:51.65#ibcon#about to read 4, iclass 39, count 0 2006.175.08:07:51.65#ibcon#read 4, iclass 39, count 0 2006.175.08:07:51.65#ibcon#about to read 5, iclass 39, count 0 2006.175.08:07:51.65#ibcon#read 5, iclass 39, count 0 2006.175.08:07:51.65#ibcon#about to read 6, iclass 39, count 0 2006.175.08:07:51.65#ibcon#read 6, iclass 39, count 0 2006.175.08:07:51.65#ibcon#end of sib2, iclass 39, count 0 2006.175.08:07:51.65#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:07:51.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:07:51.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:07:51.65#ibcon#*before write, iclass 39, count 0 2006.175.08:07:51.65#ibcon#enter sib2, iclass 39, count 0 2006.175.08:07:51.65#ibcon#flushed, iclass 39, count 0 2006.175.08:07:51.65#ibcon#about to write, iclass 39, count 0 2006.175.08:07:51.65#ibcon#wrote, iclass 39, count 0 2006.175.08:07:51.65#ibcon#about to read 3, iclass 39, count 0 2006.175.08:07:51.69#ibcon#read 3, iclass 39, count 0 2006.175.08:07:51.69#ibcon#about to read 4, iclass 39, count 0 2006.175.08:07:51.69#ibcon#read 4, iclass 39, count 0 2006.175.08:07:51.69#ibcon#about to read 5, iclass 39, count 0 2006.175.08:07:51.69#ibcon#read 5, iclass 39, count 0 2006.175.08:07:51.69#ibcon#about to read 6, iclass 39, count 0 2006.175.08:07:51.69#ibcon#read 6, iclass 39, count 0 2006.175.08:07:51.69#ibcon#end of sib2, iclass 39, count 0 2006.175.08:07:51.69#ibcon#*after write, iclass 39, count 0 2006.175.08:07:51.69#ibcon#*before return 0, iclass 39, count 0 2006.175.08:07:51.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:51.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:07:51.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:07:51.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:07:51.69$vc4f8/vb=4,4 2006.175.08:07:51.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.08:07:51.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.08:07:51.69#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:51.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:51.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:51.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:51.75#ibcon#enter wrdev, iclass 3, count 2 2006.175.08:07:51.75#ibcon#first serial, iclass 3, count 2 2006.175.08:07:51.75#ibcon#enter sib2, iclass 3, count 2 2006.175.08:07:51.75#ibcon#flushed, iclass 3, count 2 2006.175.08:07:51.75#ibcon#about to write, iclass 3, count 2 2006.175.08:07:51.75#ibcon#wrote, iclass 3, count 2 2006.175.08:07:51.75#ibcon#about to read 3, iclass 3, count 2 2006.175.08:07:51.77#ibcon#read 3, iclass 3, count 2 2006.175.08:07:51.77#ibcon#about to read 4, iclass 3, count 2 2006.175.08:07:51.77#ibcon#read 4, iclass 3, count 2 2006.175.08:07:51.77#ibcon#about to read 5, iclass 3, count 2 2006.175.08:07:51.77#ibcon#read 5, iclass 3, count 2 2006.175.08:07:51.77#ibcon#about to read 6, iclass 3, count 2 2006.175.08:07:51.77#ibcon#read 6, iclass 3, count 2 2006.175.08:07:51.77#ibcon#end of sib2, iclass 3, count 2 2006.175.08:07:51.77#ibcon#*mode == 0, iclass 3, count 2 2006.175.08:07:51.77#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.08:07:51.77#ibcon#[27=AT04-04\r\n] 2006.175.08:07:51.77#ibcon#*before write, iclass 3, count 2 2006.175.08:07:51.77#ibcon#enter sib2, iclass 3, count 2 2006.175.08:07:51.77#ibcon#flushed, iclass 3, count 2 2006.175.08:07:51.77#ibcon#about to write, iclass 3, count 2 2006.175.08:07:51.77#ibcon#wrote, iclass 3, count 2 2006.175.08:07:51.77#ibcon#about to read 3, iclass 3, count 2 2006.175.08:07:51.80#ibcon#read 3, iclass 3, count 2 2006.175.08:07:51.80#ibcon#about to read 4, iclass 3, count 2 2006.175.08:07:51.80#ibcon#read 4, iclass 3, count 2 2006.175.08:07:51.80#ibcon#about to read 5, iclass 3, count 2 2006.175.08:07:51.80#ibcon#read 5, iclass 3, count 2 2006.175.08:07:51.80#ibcon#about to read 6, iclass 3, count 2 2006.175.08:07:51.80#ibcon#read 6, iclass 3, count 2 2006.175.08:07:51.80#ibcon#end of sib2, iclass 3, count 2 2006.175.08:07:51.80#ibcon#*after write, iclass 3, count 2 2006.175.08:07:51.80#ibcon#*before return 0, iclass 3, count 2 2006.175.08:07:51.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:51.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:07:51.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.08:07:51.80#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:51.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:51.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:51.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:51.92#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:07:51.92#ibcon#first serial, iclass 3, count 0 2006.175.08:07:51.92#ibcon#enter sib2, iclass 3, count 0 2006.175.08:07:51.92#ibcon#flushed, iclass 3, count 0 2006.175.08:07:51.92#ibcon#about to write, iclass 3, count 0 2006.175.08:07:51.92#ibcon#wrote, iclass 3, count 0 2006.175.08:07:51.92#ibcon#about to read 3, iclass 3, count 0 2006.175.08:07:51.94#ibcon#read 3, iclass 3, count 0 2006.175.08:07:51.94#ibcon#about to read 4, iclass 3, count 0 2006.175.08:07:51.94#ibcon#read 4, iclass 3, count 0 2006.175.08:07:51.94#ibcon#about to read 5, iclass 3, count 0 2006.175.08:07:51.94#ibcon#read 5, iclass 3, count 0 2006.175.08:07:51.94#ibcon#about to read 6, iclass 3, count 0 2006.175.08:07:51.94#ibcon#read 6, iclass 3, count 0 2006.175.08:07:51.94#ibcon#end of sib2, iclass 3, count 0 2006.175.08:07:51.94#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:07:51.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:07:51.94#ibcon#[27=USB\r\n] 2006.175.08:07:51.94#ibcon#*before write, iclass 3, count 0 2006.175.08:07:51.94#ibcon#enter sib2, iclass 3, count 0 2006.175.08:07:51.94#ibcon#flushed, iclass 3, count 0 2006.175.08:07:51.94#ibcon#about to write, iclass 3, count 0 2006.175.08:07:51.94#ibcon#wrote, iclass 3, count 0 2006.175.08:07:51.94#ibcon#about to read 3, iclass 3, count 0 2006.175.08:07:51.97#ibcon#read 3, iclass 3, count 0 2006.175.08:07:51.97#ibcon#about to read 4, iclass 3, count 0 2006.175.08:07:51.97#ibcon#read 4, iclass 3, count 0 2006.175.08:07:51.97#ibcon#about to read 5, iclass 3, count 0 2006.175.08:07:51.97#ibcon#read 5, iclass 3, count 0 2006.175.08:07:51.97#ibcon#about to read 6, iclass 3, count 0 2006.175.08:07:51.97#ibcon#read 6, iclass 3, count 0 2006.175.08:07:51.97#ibcon#end of sib2, iclass 3, count 0 2006.175.08:07:51.97#ibcon#*after write, iclass 3, count 0 2006.175.08:07:51.97#ibcon#*before return 0, iclass 3, count 0 2006.175.08:07:51.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:51.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:07:51.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:07:51.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:07:51.97$vc4f8/vblo=5,744.99 2006.175.08:07:51.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.08:07:51.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.08:07:51.97#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:51.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:51.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:51.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:51.97#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:07:51.97#ibcon#first serial, iclass 5, count 0 2006.175.08:07:51.97#ibcon#enter sib2, iclass 5, count 0 2006.175.08:07:51.97#ibcon#flushed, iclass 5, count 0 2006.175.08:07:51.97#ibcon#about to write, iclass 5, count 0 2006.175.08:07:51.97#ibcon#wrote, iclass 5, count 0 2006.175.08:07:51.97#ibcon#about to read 3, iclass 5, count 0 2006.175.08:07:51.99#ibcon#read 3, iclass 5, count 0 2006.175.08:07:51.99#ibcon#about to read 4, iclass 5, count 0 2006.175.08:07:51.99#ibcon#read 4, iclass 5, count 0 2006.175.08:07:51.99#ibcon#about to read 5, iclass 5, count 0 2006.175.08:07:51.99#ibcon#read 5, iclass 5, count 0 2006.175.08:07:51.99#ibcon#about to read 6, iclass 5, count 0 2006.175.08:07:51.99#ibcon#read 6, iclass 5, count 0 2006.175.08:07:51.99#ibcon#end of sib2, iclass 5, count 0 2006.175.08:07:51.99#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:07:51.99#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:07:51.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:07:51.99#ibcon#*before write, iclass 5, count 0 2006.175.08:07:51.99#ibcon#enter sib2, iclass 5, count 0 2006.175.08:07:51.99#ibcon#flushed, iclass 5, count 0 2006.175.08:07:51.99#ibcon#about to write, iclass 5, count 0 2006.175.08:07:51.99#ibcon#wrote, iclass 5, count 0 2006.175.08:07:51.99#ibcon#about to read 3, iclass 5, count 0 2006.175.08:07:52.03#ibcon#read 3, iclass 5, count 0 2006.175.08:07:52.03#ibcon#about to read 4, iclass 5, count 0 2006.175.08:07:52.03#ibcon#read 4, iclass 5, count 0 2006.175.08:07:52.03#ibcon#about to read 5, iclass 5, count 0 2006.175.08:07:52.03#ibcon#read 5, iclass 5, count 0 2006.175.08:07:52.03#ibcon#about to read 6, iclass 5, count 0 2006.175.08:07:52.03#ibcon#read 6, iclass 5, count 0 2006.175.08:07:52.03#ibcon#end of sib2, iclass 5, count 0 2006.175.08:07:52.03#ibcon#*after write, iclass 5, count 0 2006.175.08:07:52.03#ibcon#*before return 0, iclass 5, count 0 2006.175.08:07:52.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:52.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:07:52.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:07:52.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:07:52.03$vc4f8/vb=5,4 2006.175.08:07:52.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.08:07:52.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.08:07:52.03#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:52.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:52.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:52.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:52.09#ibcon#enter wrdev, iclass 7, count 2 2006.175.08:07:52.09#ibcon#first serial, iclass 7, count 2 2006.175.08:07:52.09#ibcon#enter sib2, iclass 7, count 2 2006.175.08:07:52.09#ibcon#flushed, iclass 7, count 2 2006.175.08:07:52.09#ibcon#about to write, iclass 7, count 2 2006.175.08:07:52.09#ibcon#wrote, iclass 7, count 2 2006.175.08:07:52.09#ibcon#about to read 3, iclass 7, count 2 2006.175.08:07:52.11#ibcon#read 3, iclass 7, count 2 2006.175.08:07:52.11#ibcon#about to read 4, iclass 7, count 2 2006.175.08:07:52.11#ibcon#read 4, iclass 7, count 2 2006.175.08:07:52.11#ibcon#about to read 5, iclass 7, count 2 2006.175.08:07:52.11#ibcon#read 5, iclass 7, count 2 2006.175.08:07:52.11#ibcon#about to read 6, iclass 7, count 2 2006.175.08:07:52.11#ibcon#read 6, iclass 7, count 2 2006.175.08:07:52.11#ibcon#end of sib2, iclass 7, count 2 2006.175.08:07:52.11#ibcon#*mode == 0, iclass 7, count 2 2006.175.08:07:52.11#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.08:07:52.11#ibcon#[27=AT05-04\r\n] 2006.175.08:07:52.11#ibcon#*before write, iclass 7, count 2 2006.175.08:07:52.11#ibcon#enter sib2, iclass 7, count 2 2006.175.08:07:52.11#ibcon#flushed, iclass 7, count 2 2006.175.08:07:52.11#ibcon#about to write, iclass 7, count 2 2006.175.08:07:52.11#ibcon#wrote, iclass 7, count 2 2006.175.08:07:52.11#ibcon#about to read 3, iclass 7, count 2 2006.175.08:07:52.14#ibcon#read 3, iclass 7, count 2 2006.175.08:07:52.14#ibcon#about to read 4, iclass 7, count 2 2006.175.08:07:52.14#ibcon#read 4, iclass 7, count 2 2006.175.08:07:52.14#ibcon#about to read 5, iclass 7, count 2 2006.175.08:07:52.14#ibcon#read 5, iclass 7, count 2 2006.175.08:07:52.14#ibcon#about to read 6, iclass 7, count 2 2006.175.08:07:52.14#ibcon#read 6, iclass 7, count 2 2006.175.08:07:52.14#ibcon#end of sib2, iclass 7, count 2 2006.175.08:07:52.14#ibcon#*after write, iclass 7, count 2 2006.175.08:07:52.14#ibcon#*before return 0, iclass 7, count 2 2006.175.08:07:52.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:52.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:07:52.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.08:07:52.14#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:52.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:52.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:52.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:52.26#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:07:52.26#ibcon#first serial, iclass 7, count 0 2006.175.08:07:52.26#ibcon#enter sib2, iclass 7, count 0 2006.175.08:07:52.26#ibcon#flushed, iclass 7, count 0 2006.175.08:07:52.26#ibcon#about to write, iclass 7, count 0 2006.175.08:07:52.26#ibcon#wrote, iclass 7, count 0 2006.175.08:07:52.26#ibcon#about to read 3, iclass 7, count 0 2006.175.08:07:52.28#ibcon#read 3, iclass 7, count 0 2006.175.08:07:52.28#ibcon#about to read 4, iclass 7, count 0 2006.175.08:07:52.28#ibcon#read 4, iclass 7, count 0 2006.175.08:07:52.28#ibcon#about to read 5, iclass 7, count 0 2006.175.08:07:52.28#ibcon#read 5, iclass 7, count 0 2006.175.08:07:52.28#ibcon#about to read 6, iclass 7, count 0 2006.175.08:07:52.28#ibcon#read 6, iclass 7, count 0 2006.175.08:07:52.28#ibcon#end of sib2, iclass 7, count 0 2006.175.08:07:52.28#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:07:52.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:07:52.28#ibcon#[27=USB\r\n] 2006.175.08:07:52.28#ibcon#*before write, iclass 7, count 0 2006.175.08:07:52.28#ibcon#enter sib2, iclass 7, count 0 2006.175.08:07:52.28#ibcon#flushed, iclass 7, count 0 2006.175.08:07:52.28#ibcon#about to write, iclass 7, count 0 2006.175.08:07:52.28#ibcon#wrote, iclass 7, count 0 2006.175.08:07:52.28#ibcon#about to read 3, iclass 7, count 0 2006.175.08:07:52.31#ibcon#read 3, iclass 7, count 0 2006.175.08:07:52.31#ibcon#about to read 4, iclass 7, count 0 2006.175.08:07:52.31#ibcon#read 4, iclass 7, count 0 2006.175.08:07:52.31#ibcon#about to read 5, iclass 7, count 0 2006.175.08:07:52.31#ibcon#read 5, iclass 7, count 0 2006.175.08:07:52.31#ibcon#about to read 6, iclass 7, count 0 2006.175.08:07:52.31#ibcon#read 6, iclass 7, count 0 2006.175.08:07:52.31#ibcon#end of sib2, iclass 7, count 0 2006.175.08:07:52.31#ibcon#*after write, iclass 7, count 0 2006.175.08:07:52.31#ibcon#*before return 0, iclass 7, count 0 2006.175.08:07:52.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:52.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:07:52.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:07:52.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:07:52.31$vc4f8/vblo=6,752.99 2006.175.08:07:52.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.08:07:52.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.08:07:52.31#ibcon#ireg 17 cls_cnt 0 2006.175.08:07:52.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:52.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:52.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:52.31#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:07:52.31#ibcon#first serial, iclass 11, count 0 2006.175.08:07:52.31#ibcon#enter sib2, iclass 11, count 0 2006.175.08:07:52.31#ibcon#flushed, iclass 11, count 0 2006.175.08:07:52.31#ibcon#about to write, iclass 11, count 0 2006.175.08:07:52.31#ibcon#wrote, iclass 11, count 0 2006.175.08:07:52.31#ibcon#about to read 3, iclass 11, count 0 2006.175.08:07:52.33#ibcon#read 3, iclass 11, count 0 2006.175.08:07:52.33#ibcon#about to read 4, iclass 11, count 0 2006.175.08:07:52.33#ibcon#read 4, iclass 11, count 0 2006.175.08:07:52.33#ibcon#about to read 5, iclass 11, count 0 2006.175.08:07:52.33#ibcon#read 5, iclass 11, count 0 2006.175.08:07:52.33#ibcon#about to read 6, iclass 11, count 0 2006.175.08:07:52.33#ibcon#read 6, iclass 11, count 0 2006.175.08:07:52.33#ibcon#end of sib2, iclass 11, count 0 2006.175.08:07:52.33#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:07:52.33#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:07:52.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:07:52.33#ibcon#*before write, iclass 11, count 0 2006.175.08:07:52.33#ibcon#enter sib2, iclass 11, count 0 2006.175.08:07:52.33#ibcon#flushed, iclass 11, count 0 2006.175.08:07:52.33#ibcon#about to write, iclass 11, count 0 2006.175.08:07:52.33#ibcon#wrote, iclass 11, count 0 2006.175.08:07:52.33#ibcon#about to read 3, iclass 11, count 0 2006.175.08:07:52.37#ibcon#read 3, iclass 11, count 0 2006.175.08:07:52.37#ibcon#about to read 4, iclass 11, count 0 2006.175.08:07:52.37#ibcon#read 4, iclass 11, count 0 2006.175.08:07:52.37#ibcon#about to read 5, iclass 11, count 0 2006.175.08:07:52.37#ibcon#read 5, iclass 11, count 0 2006.175.08:07:52.37#ibcon#about to read 6, iclass 11, count 0 2006.175.08:07:52.37#ibcon#read 6, iclass 11, count 0 2006.175.08:07:52.37#ibcon#end of sib2, iclass 11, count 0 2006.175.08:07:52.37#ibcon#*after write, iclass 11, count 0 2006.175.08:07:52.37#ibcon#*before return 0, iclass 11, count 0 2006.175.08:07:52.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:52.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:07:52.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:07:52.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:07:52.37$vc4f8/vb=6,4 2006.175.08:07:52.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.08:07:52.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.08:07:52.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:07:52.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:52.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:52.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:52.43#ibcon#enter wrdev, iclass 13, count 2 2006.175.08:07:52.43#ibcon#first serial, iclass 13, count 2 2006.175.08:07:52.43#ibcon#enter sib2, iclass 13, count 2 2006.175.08:07:52.43#ibcon#flushed, iclass 13, count 2 2006.175.08:07:52.43#ibcon#about to write, iclass 13, count 2 2006.175.08:07:52.43#ibcon#wrote, iclass 13, count 2 2006.175.08:07:52.43#ibcon#about to read 3, iclass 13, count 2 2006.175.08:07:52.45#ibcon#read 3, iclass 13, count 2 2006.175.08:07:52.45#ibcon#about to read 4, iclass 13, count 2 2006.175.08:07:52.45#ibcon#read 4, iclass 13, count 2 2006.175.08:07:52.45#ibcon#about to read 5, iclass 13, count 2 2006.175.08:07:52.45#ibcon#read 5, iclass 13, count 2 2006.175.08:07:52.45#ibcon#about to read 6, iclass 13, count 2 2006.175.08:07:52.45#ibcon#read 6, iclass 13, count 2 2006.175.08:07:52.45#ibcon#end of sib2, iclass 13, count 2 2006.175.08:07:52.45#ibcon#*mode == 0, iclass 13, count 2 2006.175.08:07:52.45#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.08:07:52.45#ibcon#[27=AT06-04\r\n] 2006.175.08:07:52.45#ibcon#*before write, iclass 13, count 2 2006.175.08:07:52.45#ibcon#enter sib2, iclass 13, count 2 2006.175.08:07:52.45#ibcon#flushed, iclass 13, count 2 2006.175.08:07:52.45#ibcon#about to write, iclass 13, count 2 2006.175.08:07:52.45#ibcon#wrote, iclass 13, count 2 2006.175.08:07:52.45#ibcon#about to read 3, iclass 13, count 2 2006.175.08:07:52.48#ibcon#read 3, iclass 13, count 2 2006.175.08:07:52.48#ibcon#about to read 4, iclass 13, count 2 2006.175.08:07:52.48#ibcon#read 4, iclass 13, count 2 2006.175.08:07:52.48#ibcon#about to read 5, iclass 13, count 2 2006.175.08:07:52.48#ibcon#read 5, iclass 13, count 2 2006.175.08:07:52.48#ibcon#about to read 6, iclass 13, count 2 2006.175.08:07:52.48#ibcon#read 6, iclass 13, count 2 2006.175.08:07:52.48#ibcon#end of sib2, iclass 13, count 2 2006.175.08:07:52.48#ibcon#*after write, iclass 13, count 2 2006.175.08:07:52.48#ibcon#*before return 0, iclass 13, count 2 2006.175.08:07:52.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:52.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:07:52.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.08:07:52.48#ibcon#ireg 7 cls_cnt 0 2006.175.08:07:52.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:52.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:52.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:52.60#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:07:52.60#ibcon#first serial, iclass 13, count 0 2006.175.08:07:52.60#ibcon#enter sib2, iclass 13, count 0 2006.175.08:07:52.60#ibcon#flushed, iclass 13, count 0 2006.175.08:07:52.60#ibcon#about to write, iclass 13, count 0 2006.175.08:07:52.60#ibcon#wrote, iclass 13, count 0 2006.175.08:07:52.60#ibcon#about to read 3, iclass 13, count 0 2006.175.08:07:52.62#ibcon#read 3, iclass 13, count 0 2006.175.08:07:52.62#ibcon#about to read 4, iclass 13, count 0 2006.175.08:07:52.62#ibcon#read 4, iclass 13, count 0 2006.175.08:07:52.62#ibcon#about to read 5, iclass 13, count 0 2006.175.08:07:52.62#ibcon#read 5, iclass 13, count 0 2006.175.08:07:52.62#ibcon#about to read 6, iclass 13, count 0 2006.175.08:07:52.62#ibcon#read 6, iclass 13, count 0 2006.175.08:07:52.62#ibcon#end of sib2, iclass 13, count 0 2006.175.08:07:52.62#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:07:52.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:07:52.62#ibcon#[27=USB\r\n] 2006.175.08:07:52.62#ibcon#*before write, iclass 13, count 0 2006.175.08:07:52.62#ibcon#enter sib2, iclass 13, count 0 2006.175.08:07:52.62#ibcon#flushed, iclass 13, count 0 2006.175.08:07:52.62#ibcon#about to write, iclass 13, count 0 2006.175.08:07:52.62#ibcon#wrote, iclass 13, count 0 2006.175.08:07:52.62#ibcon#about to read 3, iclass 13, count 0 2006.175.08:07:52.65#ibcon#read 3, iclass 13, count 0 2006.175.08:07:52.65#ibcon#about to read 4, iclass 13, count 0 2006.175.08:07:52.65#ibcon#read 4, iclass 13, count 0 2006.175.08:07:52.65#ibcon#about to read 5, iclass 13, count 0 2006.175.08:07:52.65#ibcon#read 5, iclass 13, count 0 2006.175.08:07:52.65#ibcon#about to read 6, iclass 13, count 0 2006.175.08:07:52.65#ibcon#read 6, iclass 13, count 0 2006.175.08:07:52.65#ibcon#end of sib2, iclass 13, count 0 2006.175.08:07:52.65#ibcon#*after write, iclass 13, count 0 2006.175.08:07:52.65#ibcon#*before return 0, iclass 13, count 0 2006.175.08:07:52.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:52.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:07:52.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:07:52.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:07:52.65$vc4f8/vabw=wide 2006.175.08:07:52.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.08:07:52.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.08:07:52.65#ibcon#ireg 8 cls_cnt 0 2006.175.08:07:52.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:52.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:52.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:52.65#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:07:52.65#ibcon#first serial, iclass 15, count 0 2006.175.08:07:52.65#ibcon#enter sib2, iclass 15, count 0 2006.175.08:07:52.65#ibcon#flushed, iclass 15, count 0 2006.175.08:07:52.65#ibcon#about to write, iclass 15, count 0 2006.175.08:07:52.65#ibcon#wrote, iclass 15, count 0 2006.175.08:07:52.65#ibcon#about to read 3, iclass 15, count 0 2006.175.08:07:52.67#ibcon#read 3, iclass 15, count 0 2006.175.08:07:52.67#ibcon#about to read 4, iclass 15, count 0 2006.175.08:07:52.67#ibcon#read 4, iclass 15, count 0 2006.175.08:07:52.67#ibcon#about to read 5, iclass 15, count 0 2006.175.08:07:52.67#ibcon#read 5, iclass 15, count 0 2006.175.08:07:52.67#ibcon#about to read 6, iclass 15, count 0 2006.175.08:07:52.67#ibcon#read 6, iclass 15, count 0 2006.175.08:07:52.67#ibcon#end of sib2, iclass 15, count 0 2006.175.08:07:52.67#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:07:52.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:07:52.67#ibcon#[25=BW32\r\n] 2006.175.08:07:52.67#ibcon#*before write, iclass 15, count 0 2006.175.08:07:52.67#ibcon#enter sib2, iclass 15, count 0 2006.175.08:07:52.67#ibcon#flushed, iclass 15, count 0 2006.175.08:07:52.67#ibcon#about to write, iclass 15, count 0 2006.175.08:07:52.67#ibcon#wrote, iclass 15, count 0 2006.175.08:07:52.67#ibcon#about to read 3, iclass 15, count 0 2006.175.08:07:52.70#ibcon#read 3, iclass 15, count 0 2006.175.08:07:52.70#ibcon#about to read 4, iclass 15, count 0 2006.175.08:07:52.70#ibcon#read 4, iclass 15, count 0 2006.175.08:07:52.70#ibcon#about to read 5, iclass 15, count 0 2006.175.08:07:52.70#ibcon#read 5, iclass 15, count 0 2006.175.08:07:52.70#ibcon#about to read 6, iclass 15, count 0 2006.175.08:07:52.70#ibcon#read 6, iclass 15, count 0 2006.175.08:07:52.70#ibcon#end of sib2, iclass 15, count 0 2006.175.08:07:52.70#ibcon#*after write, iclass 15, count 0 2006.175.08:07:52.70#ibcon#*before return 0, iclass 15, count 0 2006.175.08:07:52.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:52.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:07:52.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:07:52.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:07:52.70$vc4f8/vbbw=wide 2006.175.08:07:52.70#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.08:07:52.70#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.08:07:52.70#ibcon#ireg 8 cls_cnt 0 2006.175.08:07:52.70#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:07:52.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:07:52.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:07:52.77#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:07:52.77#ibcon#first serial, iclass 17, count 0 2006.175.08:07:52.77#ibcon#enter sib2, iclass 17, count 0 2006.175.08:07:52.77#ibcon#flushed, iclass 17, count 0 2006.175.08:07:52.77#ibcon#about to write, iclass 17, count 0 2006.175.08:07:52.77#ibcon#wrote, iclass 17, count 0 2006.175.08:07:52.77#ibcon#about to read 3, iclass 17, count 0 2006.175.08:07:52.79#ibcon#read 3, iclass 17, count 0 2006.175.08:07:52.79#ibcon#about to read 4, iclass 17, count 0 2006.175.08:07:52.79#ibcon#read 4, iclass 17, count 0 2006.175.08:07:52.79#ibcon#about to read 5, iclass 17, count 0 2006.175.08:07:52.79#ibcon#read 5, iclass 17, count 0 2006.175.08:07:52.79#ibcon#about to read 6, iclass 17, count 0 2006.175.08:07:52.79#ibcon#read 6, iclass 17, count 0 2006.175.08:07:52.79#ibcon#end of sib2, iclass 17, count 0 2006.175.08:07:52.79#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:07:52.79#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:07:52.79#ibcon#[27=BW32\r\n] 2006.175.08:07:52.79#ibcon#*before write, iclass 17, count 0 2006.175.08:07:52.79#ibcon#enter sib2, iclass 17, count 0 2006.175.08:07:52.79#ibcon#flushed, iclass 17, count 0 2006.175.08:07:52.79#ibcon#about to write, iclass 17, count 0 2006.175.08:07:52.79#ibcon#wrote, iclass 17, count 0 2006.175.08:07:52.79#ibcon#about to read 3, iclass 17, count 0 2006.175.08:07:52.82#ibcon#read 3, iclass 17, count 0 2006.175.08:07:52.82#ibcon#about to read 4, iclass 17, count 0 2006.175.08:07:52.82#ibcon#read 4, iclass 17, count 0 2006.175.08:07:52.82#ibcon#about to read 5, iclass 17, count 0 2006.175.08:07:52.82#ibcon#read 5, iclass 17, count 0 2006.175.08:07:52.82#ibcon#about to read 6, iclass 17, count 0 2006.175.08:07:52.82#ibcon#read 6, iclass 17, count 0 2006.175.08:07:52.82#ibcon#end of sib2, iclass 17, count 0 2006.175.08:07:52.82#ibcon#*after write, iclass 17, count 0 2006.175.08:07:52.82#ibcon#*before return 0, iclass 17, count 0 2006.175.08:07:52.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:07:52.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:07:52.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:07:52.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:07:52.82$4f8m12a/ifd4f 2006.175.08:07:52.82$ifd4f/lo= 2006.175.08:07:52.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:07:52.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:07:52.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:07:52.82$ifd4f/patch= 2006.175.08:07:52.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:07:52.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:07:52.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:07:52.82$4f8m12a/"form=m,16.000,1:2 2006.175.08:07:52.82$4f8m12a/"tpicd 2006.175.08:07:52.82$4f8m12a/echo=off 2006.175.08:07:52.82$4f8m12a/xlog=off 2006.175.08:07:52.82:!2006.175.08:08:20 2006.175.08:07:58.13#trakl#Source acquired 2006.175.08:07:59.13#flagr#flagr/antenna,acquired 2006.175.08:08:20.00:preob 2006.175.08:08:21.13/onsource/TRACKING 2006.175.08:08:21.13:!2006.175.08:08:30 2006.175.08:08:30.00:data_valid=on 2006.175.08:08:30.00:midob 2006.175.08:08:30.13/onsource/TRACKING 2006.175.08:08:30.13/wx/25.82,1007.4,69 2006.175.08:08:30.36/cable/+6.4779E-03 2006.175.08:08:31.45/va/01,08,usb,yes,28,30 2006.175.08:08:31.45/va/02,07,usb,yes,29,30 2006.175.08:08:31.45/va/03,06,usb,yes,30,30 2006.175.08:08:31.45/va/04,07,usb,yes,29,31 2006.175.08:08:31.45/va/05,07,usb,yes,30,32 2006.175.08:08:31.45/va/06,06,usb,yes,29,29 2006.175.08:08:31.45/va/07,06,usb,yes,29,29 2006.175.08:08:31.45/va/08,06,usb,yes,31,31 2006.175.08:08:31.68/valo/01,532.99,yes,locked 2006.175.08:08:31.68/valo/02,572.99,yes,locked 2006.175.08:08:31.68/valo/03,672.99,yes,locked 2006.175.08:08:31.68/valo/04,832.99,yes,locked 2006.175.08:08:31.68/valo/05,652.99,yes,locked 2006.175.08:08:31.68/valo/06,772.99,yes,locked 2006.175.08:08:31.68/valo/07,832.99,yes,locked 2006.175.08:08:31.68/valo/08,852.99,yes,locked 2006.175.08:08:32.77/vb/01,04,usb,yes,29,28 2006.175.08:08:32.77/vb/02,04,usb,yes,31,32 2006.175.08:08:32.77/vb/03,04,usb,yes,27,31 2006.175.08:08:32.77/vb/04,04,usb,yes,28,28 2006.175.08:08:32.77/vb/05,04,usb,yes,26,30 2006.175.08:08:32.77/vb/06,04,usb,yes,27,30 2006.175.08:08:32.77/vb/07,04,usb,yes,29,29 2006.175.08:08:32.77/vb/08,04,usb,yes,27,30 2006.175.08:08:33.00/vblo/01,632.99,yes,locked 2006.175.08:08:33.00/vblo/02,640.99,yes,locked 2006.175.08:08:33.00/vblo/03,656.99,yes,locked 2006.175.08:08:33.00/vblo/04,712.99,yes,locked 2006.175.08:08:33.00/vblo/05,744.99,yes,locked 2006.175.08:08:33.00/vblo/06,752.99,yes,locked 2006.175.08:08:33.00/vblo/07,734.99,yes,locked 2006.175.08:08:33.00/vblo/08,744.99,yes,locked 2006.175.08:08:33.15/vabw/8 2006.175.08:08:33.30/vbbw/8 2006.175.08:08:33.39/xfe/off,on,15.2 2006.175.08:08:33.76/ifatt/23,28,28,28 2006.175.08:08:34.07/fmout-gps/S +3.79E-07 2006.175.08:08:34.13:!2006.175.08:09:30 2006.175.08:09:30.01:data_valid=off 2006.175.08:09:30.02:postob 2006.175.08:09:30.17/cable/+6.4784E-03 2006.175.08:09:30.18/wx/25.81,1007.4,69 2006.175.08:09:31.07/fmout-gps/S +3.80E-07 2006.175.08:09:31.08:scan_name=175-0810,k06175,60 2006.175.08:09:31.08:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.175.08:09:31.14#flagr#flagr/antenna,new-source 2006.175.08:09:32.14:checkk5 2006.175.08:09:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:09:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:09:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:09:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:09:34.03/chk_obsdata//k5ts1/T1750808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:09:34.40/chk_obsdata//k5ts2/T1750808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:09:34.78/chk_obsdata//k5ts3/T1750808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:09:35.15/chk_obsdata//k5ts4/T1750808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:09:35.85/k5log//k5ts1_log_newline 2006.175.08:09:36.54/k5log//k5ts2_log_newline 2006.175.08:09:37.31/k5log//k5ts3_log_newline 2006.175.08:09:38.00/k5log//k5ts4_log_newline 2006.175.08:09:38.03/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:09:38.03:4f8m12a=2 2006.175.08:09:38.03$4f8m12a/echo=on 2006.175.08:09:38.03$4f8m12a/pcalon 2006.175.08:09:38.03$pcalon/"no phase cal control is implemented here 2006.175.08:09:38.03$4f8m12a/"tpicd=stop 2006.175.08:09:38.03$4f8m12a/vc4f8 2006.175.08:09:38.03$vc4f8/valo=1,532.99 2006.175.08:09:38.03#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.08:09:38.03#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.08:09:38.03#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:38.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:38.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:38.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:38.03#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:09:38.03#ibcon#first serial, iclass 24, count 0 2006.175.08:09:38.03#ibcon#enter sib2, iclass 24, count 0 2006.175.08:09:38.03#ibcon#flushed, iclass 24, count 0 2006.175.08:09:38.03#ibcon#about to write, iclass 24, count 0 2006.175.08:09:38.03#ibcon#wrote, iclass 24, count 0 2006.175.08:09:38.03#ibcon#about to read 3, iclass 24, count 0 2006.175.08:09:38.08#ibcon#read 3, iclass 24, count 0 2006.175.08:09:38.08#ibcon#about to read 4, iclass 24, count 0 2006.175.08:09:38.08#ibcon#read 4, iclass 24, count 0 2006.175.08:09:38.08#ibcon#about to read 5, iclass 24, count 0 2006.175.08:09:38.08#ibcon#read 5, iclass 24, count 0 2006.175.08:09:38.08#ibcon#about to read 6, iclass 24, count 0 2006.175.08:09:38.08#ibcon#read 6, iclass 24, count 0 2006.175.08:09:38.08#ibcon#end of sib2, iclass 24, count 0 2006.175.08:09:38.08#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:09:38.08#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:09:38.08#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:09:38.08#ibcon#*before write, iclass 24, count 0 2006.175.08:09:38.08#ibcon#enter sib2, iclass 24, count 0 2006.175.08:09:38.08#ibcon#flushed, iclass 24, count 0 2006.175.08:09:38.08#ibcon#about to write, iclass 24, count 0 2006.175.08:09:38.08#ibcon#wrote, iclass 24, count 0 2006.175.08:09:38.08#ibcon#about to read 3, iclass 24, count 0 2006.175.08:09:38.12#ibcon#read 3, iclass 24, count 0 2006.175.08:09:38.12#ibcon#about to read 4, iclass 24, count 0 2006.175.08:09:38.12#ibcon#read 4, iclass 24, count 0 2006.175.08:09:38.12#ibcon#about to read 5, iclass 24, count 0 2006.175.08:09:38.12#ibcon#read 5, iclass 24, count 0 2006.175.08:09:38.12#ibcon#about to read 6, iclass 24, count 0 2006.175.08:09:38.12#ibcon#read 6, iclass 24, count 0 2006.175.08:09:38.12#ibcon#end of sib2, iclass 24, count 0 2006.175.08:09:38.12#ibcon#*after write, iclass 24, count 0 2006.175.08:09:38.12#ibcon#*before return 0, iclass 24, count 0 2006.175.08:09:38.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:38.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:38.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:09:38.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:09:38.12$vc4f8/va=1,8 2006.175.08:09:38.12#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.08:09:38.12#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.08:09:38.12#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:38.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:38.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:38.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:38.12#ibcon#enter wrdev, iclass 26, count 2 2006.175.08:09:38.12#ibcon#first serial, iclass 26, count 2 2006.175.08:09:38.12#ibcon#enter sib2, iclass 26, count 2 2006.175.08:09:38.12#ibcon#flushed, iclass 26, count 2 2006.175.08:09:38.12#ibcon#about to write, iclass 26, count 2 2006.175.08:09:38.12#ibcon#wrote, iclass 26, count 2 2006.175.08:09:38.12#ibcon#about to read 3, iclass 26, count 2 2006.175.08:09:38.14#ibcon#read 3, iclass 26, count 2 2006.175.08:09:38.14#ibcon#about to read 4, iclass 26, count 2 2006.175.08:09:38.14#ibcon#read 4, iclass 26, count 2 2006.175.08:09:38.14#ibcon#about to read 5, iclass 26, count 2 2006.175.08:09:38.14#ibcon#read 5, iclass 26, count 2 2006.175.08:09:38.14#ibcon#about to read 6, iclass 26, count 2 2006.175.08:09:38.14#ibcon#read 6, iclass 26, count 2 2006.175.08:09:38.14#ibcon#end of sib2, iclass 26, count 2 2006.175.08:09:38.14#ibcon#*mode == 0, iclass 26, count 2 2006.175.08:09:38.14#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.08:09:38.14#ibcon#[25=AT01-08\r\n] 2006.175.08:09:38.14#ibcon#*before write, iclass 26, count 2 2006.175.08:09:38.14#ibcon#enter sib2, iclass 26, count 2 2006.175.08:09:38.14#ibcon#flushed, iclass 26, count 2 2006.175.08:09:38.14#ibcon#about to write, iclass 26, count 2 2006.175.08:09:38.14#ibcon#wrote, iclass 26, count 2 2006.175.08:09:38.14#ibcon#about to read 3, iclass 26, count 2 2006.175.08:09:38.17#ibcon#read 3, iclass 26, count 2 2006.175.08:09:38.17#ibcon#about to read 4, iclass 26, count 2 2006.175.08:09:38.17#ibcon#read 4, iclass 26, count 2 2006.175.08:09:38.17#ibcon#about to read 5, iclass 26, count 2 2006.175.08:09:38.17#ibcon#read 5, iclass 26, count 2 2006.175.08:09:38.17#ibcon#about to read 6, iclass 26, count 2 2006.175.08:09:38.17#ibcon#read 6, iclass 26, count 2 2006.175.08:09:38.17#ibcon#end of sib2, iclass 26, count 2 2006.175.08:09:38.17#ibcon#*after write, iclass 26, count 2 2006.175.08:09:38.17#ibcon#*before return 0, iclass 26, count 2 2006.175.08:09:38.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:38.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:38.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.08:09:38.17#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:38.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:38.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:38.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:38.29#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:09:38.29#ibcon#first serial, iclass 26, count 0 2006.175.08:09:38.29#ibcon#enter sib2, iclass 26, count 0 2006.175.08:09:38.29#ibcon#flushed, iclass 26, count 0 2006.175.08:09:38.29#ibcon#about to write, iclass 26, count 0 2006.175.08:09:38.29#ibcon#wrote, iclass 26, count 0 2006.175.08:09:38.29#ibcon#about to read 3, iclass 26, count 0 2006.175.08:09:38.31#ibcon#read 3, iclass 26, count 0 2006.175.08:09:38.31#ibcon#about to read 4, iclass 26, count 0 2006.175.08:09:38.31#ibcon#read 4, iclass 26, count 0 2006.175.08:09:38.31#ibcon#about to read 5, iclass 26, count 0 2006.175.08:09:38.31#ibcon#read 5, iclass 26, count 0 2006.175.08:09:38.31#ibcon#about to read 6, iclass 26, count 0 2006.175.08:09:38.31#ibcon#read 6, iclass 26, count 0 2006.175.08:09:38.31#ibcon#end of sib2, iclass 26, count 0 2006.175.08:09:38.31#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:09:38.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:09:38.31#ibcon#[25=USB\r\n] 2006.175.08:09:38.31#ibcon#*before write, iclass 26, count 0 2006.175.08:09:38.31#ibcon#enter sib2, iclass 26, count 0 2006.175.08:09:38.31#ibcon#flushed, iclass 26, count 0 2006.175.08:09:38.31#ibcon#about to write, iclass 26, count 0 2006.175.08:09:38.31#ibcon#wrote, iclass 26, count 0 2006.175.08:09:38.31#ibcon#about to read 3, iclass 26, count 0 2006.175.08:09:38.34#ibcon#read 3, iclass 26, count 0 2006.175.08:09:38.34#ibcon#about to read 4, iclass 26, count 0 2006.175.08:09:38.34#ibcon#read 4, iclass 26, count 0 2006.175.08:09:38.34#ibcon#about to read 5, iclass 26, count 0 2006.175.08:09:38.34#ibcon#read 5, iclass 26, count 0 2006.175.08:09:38.34#ibcon#about to read 6, iclass 26, count 0 2006.175.08:09:38.34#ibcon#read 6, iclass 26, count 0 2006.175.08:09:38.34#ibcon#end of sib2, iclass 26, count 0 2006.175.08:09:38.34#ibcon#*after write, iclass 26, count 0 2006.175.08:09:38.34#ibcon#*before return 0, iclass 26, count 0 2006.175.08:09:38.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:38.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:38.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:09:38.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:09:38.34$vc4f8/valo=2,572.99 2006.175.08:09:38.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.08:09:38.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.08:09:38.34#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:38.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:38.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:38.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:38.34#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:09:38.34#ibcon#first serial, iclass 28, count 0 2006.175.08:09:38.34#ibcon#enter sib2, iclass 28, count 0 2006.175.08:09:38.34#ibcon#flushed, iclass 28, count 0 2006.175.08:09:38.34#ibcon#about to write, iclass 28, count 0 2006.175.08:09:38.34#ibcon#wrote, iclass 28, count 0 2006.175.08:09:38.34#ibcon#about to read 3, iclass 28, count 0 2006.175.08:09:38.36#ibcon#read 3, iclass 28, count 0 2006.175.08:09:38.36#ibcon#about to read 4, iclass 28, count 0 2006.175.08:09:38.36#ibcon#read 4, iclass 28, count 0 2006.175.08:09:38.36#ibcon#about to read 5, iclass 28, count 0 2006.175.08:09:38.36#ibcon#read 5, iclass 28, count 0 2006.175.08:09:38.36#ibcon#about to read 6, iclass 28, count 0 2006.175.08:09:38.36#ibcon#read 6, iclass 28, count 0 2006.175.08:09:38.36#ibcon#end of sib2, iclass 28, count 0 2006.175.08:09:38.36#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:09:38.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:09:38.36#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:09:38.36#ibcon#*before write, iclass 28, count 0 2006.175.08:09:38.36#ibcon#enter sib2, iclass 28, count 0 2006.175.08:09:38.36#ibcon#flushed, iclass 28, count 0 2006.175.08:09:38.36#ibcon#about to write, iclass 28, count 0 2006.175.08:09:38.36#ibcon#wrote, iclass 28, count 0 2006.175.08:09:38.36#ibcon#about to read 3, iclass 28, count 0 2006.175.08:09:38.40#ibcon#read 3, iclass 28, count 0 2006.175.08:09:38.40#ibcon#about to read 4, iclass 28, count 0 2006.175.08:09:38.40#ibcon#read 4, iclass 28, count 0 2006.175.08:09:38.40#ibcon#about to read 5, iclass 28, count 0 2006.175.08:09:38.40#ibcon#read 5, iclass 28, count 0 2006.175.08:09:38.40#ibcon#about to read 6, iclass 28, count 0 2006.175.08:09:38.40#ibcon#read 6, iclass 28, count 0 2006.175.08:09:38.40#ibcon#end of sib2, iclass 28, count 0 2006.175.08:09:38.40#ibcon#*after write, iclass 28, count 0 2006.175.08:09:38.40#ibcon#*before return 0, iclass 28, count 0 2006.175.08:09:38.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:38.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:38.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:09:38.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:09:38.40$vc4f8/va=2,7 2006.175.08:09:38.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.08:09:38.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.08:09:38.40#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:38.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:38.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:38.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:38.46#ibcon#enter wrdev, iclass 30, count 2 2006.175.08:09:38.46#ibcon#first serial, iclass 30, count 2 2006.175.08:09:38.46#ibcon#enter sib2, iclass 30, count 2 2006.175.08:09:38.46#ibcon#flushed, iclass 30, count 2 2006.175.08:09:38.46#ibcon#about to write, iclass 30, count 2 2006.175.08:09:38.46#ibcon#wrote, iclass 30, count 2 2006.175.08:09:38.46#ibcon#about to read 3, iclass 30, count 2 2006.175.08:09:38.48#ibcon#read 3, iclass 30, count 2 2006.175.08:09:38.48#ibcon#about to read 4, iclass 30, count 2 2006.175.08:09:38.48#ibcon#read 4, iclass 30, count 2 2006.175.08:09:38.48#ibcon#about to read 5, iclass 30, count 2 2006.175.08:09:38.48#ibcon#read 5, iclass 30, count 2 2006.175.08:09:38.48#ibcon#about to read 6, iclass 30, count 2 2006.175.08:09:38.48#ibcon#read 6, iclass 30, count 2 2006.175.08:09:38.48#ibcon#end of sib2, iclass 30, count 2 2006.175.08:09:38.48#ibcon#*mode == 0, iclass 30, count 2 2006.175.08:09:38.48#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.08:09:38.48#ibcon#[25=AT02-07\r\n] 2006.175.08:09:38.48#ibcon#*before write, iclass 30, count 2 2006.175.08:09:38.48#ibcon#enter sib2, iclass 30, count 2 2006.175.08:09:38.48#ibcon#flushed, iclass 30, count 2 2006.175.08:09:38.48#ibcon#about to write, iclass 30, count 2 2006.175.08:09:38.48#ibcon#wrote, iclass 30, count 2 2006.175.08:09:38.48#ibcon#about to read 3, iclass 30, count 2 2006.175.08:09:38.51#ibcon#read 3, iclass 30, count 2 2006.175.08:09:38.51#ibcon#about to read 4, iclass 30, count 2 2006.175.08:09:38.51#ibcon#read 4, iclass 30, count 2 2006.175.08:09:38.51#ibcon#about to read 5, iclass 30, count 2 2006.175.08:09:38.51#ibcon#read 5, iclass 30, count 2 2006.175.08:09:38.51#ibcon#about to read 6, iclass 30, count 2 2006.175.08:09:38.51#ibcon#read 6, iclass 30, count 2 2006.175.08:09:38.51#ibcon#end of sib2, iclass 30, count 2 2006.175.08:09:38.51#ibcon#*after write, iclass 30, count 2 2006.175.08:09:38.51#ibcon#*before return 0, iclass 30, count 2 2006.175.08:09:38.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:38.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:38.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.08:09:38.51#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:38.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:38.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:38.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:38.63#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:09:38.63#ibcon#first serial, iclass 30, count 0 2006.175.08:09:38.63#ibcon#enter sib2, iclass 30, count 0 2006.175.08:09:38.63#ibcon#flushed, iclass 30, count 0 2006.175.08:09:38.63#ibcon#about to write, iclass 30, count 0 2006.175.08:09:38.63#ibcon#wrote, iclass 30, count 0 2006.175.08:09:38.63#ibcon#about to read 3, iclass 30, count 0 2006.175.08:09:38.65#ibcon#read 3, iclass 30, count 0 2006.175.08:09:38.65#ibcon#about to read 4, iclass 30, count 0 2006.175.08:09:38.65#ibcon#read 4, iclass 30, count 0 2006.175.08:09:38.65#ibcon#about to read 5, iclass 30, count 0 2006.175.08:09:38.65#ibcon#read 5, iclass 30, count 0 2006.175.08:09:38.65#ibcon#about to read 6, iclass 30, count 0 2006.175.08:09:38.65#ibcon#read 6, iclass 30, count 0 2006.175.08:09:38.65#ibcon#end of sib2, iclass 30, count 0 2006.175.08:09:38.65#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:09:38.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:09:38.65#ibcon#[25=USB\r\n] 2006.175.08:09:38.65#ibcon#*before write, iclass 30, count 0 2006.175.08:09:38.65#ibcon#enter sib2, iclass 30, count 0 2006.175.08:09:38.65#ibcon#flushed, iclass 30, count 0 2006.175.08:09:38.65#ibcon#about to write, iclass 30, count 0 2006.175.08:09:38.65#ibcon#wrote, iclass 30, count 0 2006.175.08:09:38.65#ibcon#about to read 3, iclass 30, count 0 2006.175.08:09:38.68#ibcon#read 3, iclass 30, count 0 2006.175.08:09:38.68#ibcon#about to read 4, iclass 30, count 0 2006.175.08:09:38.68#ibcon#read 4, iclass 30, count 0 2006.175.08:09:38.68#ibcon#about to read 5, iclass 30, count 0 2006.175.08:09:38.68#ibcon#read 5, iclass 30, count 0 2006.175.08:09:38.68#ibcon#about to read 6, iclass 30, count 0 2006.175.08:09:38.68#ibcon#read 6, iclass 30, count 0 2006.175.08:09:38.68#ibcon#end of sib2, iclass 30, count 0 2006.175.08:09:38.68#ibcon#*after write, iclass 30, count 0 2006.175.08:09:38.68#ibcon#*before return 0, iclass 30, count 0 2006.175.08:09:38.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:38.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:38.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:09:38.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:09:38.68$vc4f8/valo=3,672.99 2006.175.08:09:38.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.08:09:38.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.08:09:38.68#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:38.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:38.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:38.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:38.68#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:09:38.68#ibcon#first serial, iclass 32, count 0 2006.175.08:09:38.68#ibcon#enter sib2, iclass 32, count 0 2006.175.08:09:38.68#ibcon#flushed, iclass 32, count 0 2006.175.08:09:38.68#ibcon#about to write, iclass 32, count 0 2006.175.08:09:38.68#ibcon#wrote, iclass 32, count 0 2006.175.08:09:38.68#ibcon#about to read 3, iclass 32, count 0 2006.175.08:09:38.70#ibcon#read 3, iclass 32, count 0 2006.175.08:09:38.70#ibcon#about to read 4, iclass 32, count 0 2006.175.08:09:38.70#ibcon#read 4, iclass 32, count 0 2006.175.08:09:38.70#ibcon#about to read 5, iclass 32, count 0 2006.175.08:09:38.70#ibcon#read 5, iclass 32, count 0 2006.175.08:09:38.70#ibcon#about to read 6, iclass 32, count 0 2006.175.08:09:38.70#ibcon#read 6, iclass 32, count 0 2006.175.08:09:38.70#ibcon#end of sib2, iclass 32, count 0 2006.175.08:09:38.70#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:09:38.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:09:38.70#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:09:38.70#ibcon#*before write, iclass 32, count 0 2006.175.08:09:38.70#ibcon#enter sib2, iclass 32, count 0 2006.175.08:09:38.70#ibcon#flushed, iclass 32, count 0 2006.175.08:09:38.70#ibcon#about to write, iclass 32, count 0 2006.175.08:09:38.70#ibcon#wrote, iclass 32, count 0 2006.175.08:09:38.70#ibcon#about to read 3, iclass 32, count 0 2006.175.08:09:38.74#ibcon#read 3, iclass 32, count 0 2006.175.08:09:38.74#ibcon#about to read 4, iclass 32, count 0 2006.175.08:09:38.74#ibcon#read 4, iclass 32, count 0 2006.175.08:09:38.74#ibcon#about to read 5, iclass 32, count 0 2006.175.08:09:38.74#ibcon#read 5, iclass 32, count 0 2006.175.08:09:38.74#ibcon#about to read 6, iclass 32, count 0 2006.175.08:09:38.74#ibcon#read 6, iclass 32, count 0 2006.175.08:09:38.74#ibcon#end of sib2, iclass 32, count 0 2006.175.08:09:38.74#ibcon#*after write, iclass 32, count 0 2006.175.08:09:38.74#ibcon#*before return 0, iclass 32, count 0 2006.175.08:09:38.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:38.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:38.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:09:38.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:09:38.74$vc4f8/va=3,6 2006.175.08:09:38.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.175.08:09:38.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.175.08:09:38.74#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:38.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:38.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:38.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:38.80#ibcon#enter wrdev, iclass 34, count 2 2006.175.08:09:38.80#ibcon#first serial, iclass 34, count 2 2006.175.08:09:38.80#ibcon#enter sib2, iclass 34, count 2 2006.175.08:09:38.80#ibcon#flushed, iclass 34, count 2 2006.175.08:09:38.80#ibcon#about to write, iclass 34, count 2 2006.175.08:09:38.80#ibcon#wrote, iclass 34, count 2 2006.175.08:09:38.80#ibcon#about to read 3, iclass 34, count 2 2006.175.08:09:38.82#ibcon#read 3, iclass 34, count 2 2006.175.08:09:38.82#ibcon#about to read 4, iclass 34, count 2 2006.175.08:09:38.82#ibcon#read 4, iclass 34, count 2 2006.175.08:09:38.82#ibcon#about to read 5, iclass 34, count 2 2006.175.08:09:38.82#ibcon#read 5, iclass 34, count 2 2006.175.08:09:38.82#ibcon#about to read 6, iclass 34, count 2 2006.175.08:09:38.82#ibcon#read 6, iclass 34, count 2 2006.175.08:09:38.82#ibcon#end of sib2, iclass 34, count 2 2006.175.08:09:38.82#ibcon#*mode == 0, iclass 34, count 2 2006.175.08:09:38.82#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.175.08:09:38.82#ibcon#[25=AT03-06\r\n] 2006.175.08:09:38.82#ibcon#*before write, iclass 34, count 2 2006.175.08:09:38.82#ibcon#enter sib2, iclass 34, count 2 2006.175.08:09:38.82#ibcon#flushed, iclass 34, count 2 2006.175.08:09:38.82#ibcon#about to write, iclass 34, count 2 2006.175.08:09:38.82#ibcon#wrote, iclass 34, count 2 2006.175.08:09:38.82#ibcon#about to read 3, iclass 34, count 2 2006.175.08:09:38.85#ibcon#read 3, iclass 34, count 2 2006.175.08:09:38.85#ibcon#about to read 4, iclass 34, count 2 2006.175.08:09:38.85#ibcon#read 4, iclass 34, count 2 2006.175.08:09:38.85#ibcon#about to read 5, iclass 34, count 2 2006.175.08:09:38.85#ibcon#read 5, iclass 34, count 2 2006.175.08:09:38.85#ibcon#about to read 6, iclass 34, count 2 2006.175.08:09:38.85#ibcon#read 6, iclass 34, count 2 2006.175.08:09:38.85#ibcon#end of sib2, iclass 34, count 2 2006.175.08:09:38.85#ibcon#*after write, iclass 34, count 2 2006.175.08:09:38.85#ibcon#*before return 0, iclass 34, count 2 2006.175.08:09:38.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:38.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:38.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.175.08:09:38.85#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:38.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:38.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:38.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:38.97#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:09:38.97#ibcon#first serial, iclass 34, count 0 2006.175.08:09:38.97#ibcon#enter sib2, iclass 34, count 0 2006.175.08:09:38.97#ibcon#flushed, iclass 34, count 0 2006.175.08:09:38.97#ibcon#about to write, iclass 34, count 0 2006.175.08:09:38.97#ibcon#wrote, iclass 34, count 0 2006.175.08:09:38.97#ibcon#about to read 3, iclass 34, count 0 2006.175.08:09:38.99#ibcon#read 3, iclass 34, count 0 2006.175.08:09:38.99#ibcon#about to read 4, iclass 34, count 0 2006.175.08:09:38.99#ibcon#read 4, iclass 34, count 0 2006.175.08:09:38.99#ibcon#about to read 5, iclass 34, count 0 2006.175.08:09:38.99#ibcon#read 5, iclass 34, count 0 2006.175.08:09:38.99#ibcon#about to read 6, iclass 34, count 0 2006.175.08:09:38.99#ibcon#read 6, iclass 34, count 0 2006.175.08:09:38.99#ibcon#end of sib2, iclass 34, count 0 2006.175.08:09:38.99#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:09:38.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:09:38.99#ibcon#[25=USB\r\n] 2006.175.08:09:38.99#ibcon#*before write, iclass 34, count 0 2006.175.08:09:38.99#ibcon#enter sib2, iclass 34, count 0 2006.175.08:09:38.99#ibcon#flushed, iclass 34, count 0 2006.175.08:09:38.99#ibcon#about to write, iclass 34, count 0 2006.175.08:09:38.99#ibcon#wrote, iclass 34, count 0 2006.175.08:09:38.99#ibcon#about to read 3, iclass 34, count 0 2006.175.08:09:39.02#ibcon#read 3, iclass 34, count 0 2006.175.08:09:39.02#ibcon#about to read 4, iclass 34, count 0 2006.175.08:09:39.02#ibcon#read 4, iclass 34, count 0 2006.175.08:09:39.02#ibcon#about to read 5, iclass 34, count 0 2006.175.08:09:39.02#ibcon#read 5, iclass 34, count 0 2006.175.08:09:39.02#ibcon#about to read 6, iclass 34, count 0 2006.175.08:09:39.02#ibcon#read 6, iclass 34, count 0 2006.175.08:09:39.02#ibcon#end of sib2, iclass 34, count 0 2006.175.08:09:39.02#ibcon#*after write, iclass 34, count 0 2006.175.08:09:39.02#ibcon#*before return 0, iclass 34, count 0 2006.175.08:09:39.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:39.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:39.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:09:39.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:09:39.02$vc4f8/valo=4,832.99 2006.175.08:09:39.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.08:09:39.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.08:09:39.02#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:39.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:39.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:39.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:39.02#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:09:39.02#ibcon#first serial, iclass 36, count 0 2006.175.08:09:39.02#ibcon#enter sib2, iclass 36, count 0 2006.175.08:09:39.02#ibcon#flushed, iclass 36, count 0 2006.175.08:09:39.02#ibcon#about to write, iclass 36, count 0 2006.175.08:09:39.02#ibcon#wrote, iclass 36, count 0 2006.175.08:09:39.02#ibcon#about to read 3, iclass 36, count 0 2006.175.08:09:39.04#ibcon#read 3, iclass 36, count 0 2006.175.08:09:39.04#ibcon#about to read 4, iclass 36, count 0 2006.175.08:09:39.04#ibcon#read 4, iclass 36, count 0 2006.175.08:09:39.04#ibcon#about to read 5, iclass 36, count 0 2006.175.08:09:39.04#ibcon#read 5, iclass 36, count 0 2006.175.08:09:39.04#ibcon#about to read 6, iclass 36, count 0 2006.175.08:09:39.04#ibcon#read 6, iclass 36, count 0 2006.175.08:09:39.04#ibcon#end of sib2, iclass 36, count 0 2006.175.08:09:39.04#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:09:39.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:09:39.04#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:09:39.04#ibcon#*before write, iclass 36, count 0 2006.175.08:09:39.04#ibcon#enter sib2, iclass 36, count 0 2006.175.08:09:39.04#ibcon#flushed, iclass 36, count 0 2006.175.08:09:39.04#ibcon#about to write, iclass 36, count 0 2006.175.08:09:39.04#ibcon#wrote, iclass 36, count 0 2006.175.08:09:39.04#ibcon#about to read 3, iclass 36, count 0 2006.175.08:09:39.08#ibcon#read 3, iclass 36, count 0 2006.175.08:09:39.08#ibcon#about to read 4, iclass 36, count 0 2006.175.08:09:39.08#ibcon#read 4, iclass 36, count 0 2006.175.08:09:39.08#ibcon#about to read 5, iclass 36, count 0 2006.175.08:09:39.08#ibcon#read 5, iclass 36, count 0 2006.175.08:09:39.08#ibcon#about to read 6, iclass 36, count 0 2006.175.08:09:39.08#ibcon#read 6, iclass 36, count 0 2006.175.08:09:39.08#ibcon#end of sib2, iclass 36, count 0 2006.175.08:09:39.08#ibcon#*after write, iclass 36, count 0 2006.175.08:09:39.08#ibcon#*before return 0, iclass 36, count 0 2006.175.08:09:39.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:39.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:39.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:09:39.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:09:39.08$vc4f8/va=4,7 2006.175.08:09:39.08#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.175.08:09:39.08#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.175.08:09:39.08#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:39.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:39.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:39.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:39.14#ibcon#enter wrdev, iclass 38, count 2 2006.175.08:09:39.14#ibcon#first serial, iclass 38, count 2 2006.175.08:09:39.14#ibcon#enter sib2, iclass 38, count 2 2006.175.08:09:39.14#ibcon#flushed, iclass 38, count 2 2006.175.08:09:39.14#ibcon#about to write, iclass 38, count 2 2006.175.08:09:39.14#ibcon#wrote, iclass 38, count 2 2006.175.08:09:39.14#ibcon#about to read 3, iclass 38, count 2 2006.175.08:09:39.16#ibcon#read 3, iclass 38, count 2 2006.175.08:09:39.16#ibcon#about to read 4, iclass 38, count 2 2006.175.08:09:39.16#ibcon#read 4, iclass 38, count 2 2006.175.08:09:39.16#ibcon#about to read 5, iclass 38, count 2 2006.175.08:09:39.16#ibcon#read 5, iclass 38, count 2 2006.175.08:09:39.16#ibcon#about to read 6, iclass 38, count 2 2006.175.08:09:39.16#ibcon#read 6, iclass 38, count 2 2006.175.08:09:39.16#ibcon#end of sib2, iclass 38, count 2 2006.175.08:09:39.16#ibcon#*mode == 0, iclass 38, count 2 2006.175.08:09:39.16#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.175.08:09:39.16#ibcon#[25=AT04-07\r\n] 2006.175.08:09:39.16#ibcon#*before write, iclass 38, count 2 2006.175.08:09:39.16#ibcon#enter sib2, iclass 38, count 2 2006.175.08:09:39.16#ibcon#flushed, iclass 38, count 2 2006.175.08:09:39.16#ibcon#about to write, iclass 38, count 2 2006.175.08:09:39.16#ibcon#wrote, iclass 38, count 2 2006.175.08:09:39.16#ibcon#about to read 3, iclass 38, count 2 2006.175.08:09:39.19#ibcon#read 3, iclass 38, count 2 2006.175.08:09:39.19#ibcon#about to read 4, iclass 38, count 2 2006.175.08:09:39.19#ibcon#read 4, iclass 38, count 2 2006.175.08:09:39.19#ibcon#about to read 5, iclass 38, count 2 2006.175.08:09:39.19#ibcon#read 5, iclass 38, count 2 2006.175.08:09:39.19#ibcon#about to read 6, iclass 38, count 2 2006.175.08:09:39.19#ibcon#read 6, iclass 38, count 2 2006.175.08:09:39.19#ibcon#end of sib2, iclass 38, count 2 2006.175.08:09:39.19#ibcon#*after write, iclass 38, count 2 2006.175.08:09:39.19#ibcon#*before return 0, iclass 38, count 2 2006.175.08:09:39.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:39.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:39.19#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.175.08:09:39.19#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:39.19#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:39.31#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:39.31#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:39.31#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:09:39.31#ibcon#first serial, iclass 38, count 0 2006.175.08:09:39.31#ibcon#enter sib2, iclass 38, count 0 2006.175.08:09:39.31#ibcon#flushed, iclass 38, count 0 2006.175.08:09:39.31#ibcon#about to write, iclass 38, count 0 2006.175.08:09:39.31#ibcon#wrote, iclass 38, count 0 2006.175.08:09:39.31#ibcon#about to read 3, iclass 38, count 0 2006.175.08:09:39.33#ibcon#read 3, iclass 38, count 0 2006.175.08:09:39.33#ibcon#about to read 4, iclass 38, count 0 2006.175.08:09:39.33#ibcon#read 4, iclass 38, count 0 2006.175.08:09:39.33#ibcon#about to read 5, iclass 38, count 0 2006.175.08:09:39.33#ibcon#read 5, iclass 38, count 0 2006.175.08:09:39.33#ibcon#about to read 6, iclass 38, count 0 2006.175.08:09:39.33#ibcon#read 6, iclass 38, count 0 2006.175.08:09:39.33#ibcon#end of sib2, iclass 38, count 0 2006.175.08:09:39.33#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:09:39.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:09:39.33#ibcon#[25=USB\r\n] 2006.175.08:09:39.33#ibcon#*before write, iclass 38, count 0 2006.175.08:09:39.33#ibcon#enter sib2, iclass 38, count 0 2006.175.08:09:39.33#ibcon#flushed, iclass 38, count 0 2006.175.08:09:39.33#ibcon#about to write, iclass 38, count 0 2006.175.08:09:39.33#ibcon#wrote, iclass 38, count 0 2006.175.08:09:39.33#ibcon#about to read 3, iclass 38, count 0 2006.175.08:09:39.36#ibcon#read 3, iclass 38, count 0 2006.175.08:09:39.36#ibcon#about to read 4, iclass 38, count 0 2006.175.08:09:39.36#ibcon#read 4, iclass 38, count 0 2006.175.08:09:39.36#ibcon#about to read 5, iclass 38, count 0 2006.175.08:09:39.36#ibcon#read 5, iclass 38, count 0 2006.175.08:09:39.36#ibcon#about to read 6, iclass 38, count 0 2006.175.08:09:39.36#ibcon#read 6, iclass 38, count 0 2006.175.08:09:39.36#ibcon#end of sib2, iclass 38, count 0 2006.175.08:09:39.36#ibcon#*after write, iclass 38, count 0 2006.175.08:09:39.36#ibcon#*before return 0, iclass 38, count 0 2006.175.08:09:39.36#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:39.36#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:39.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:09:39.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:09:39.36$vc4f8/valo=5,652.99 2006.175.08:09:39.36#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.08:09:39.36#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.08:09:39.36#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:39.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:39.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:39.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:39.36#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:09:39.36#ibcon#first serial, iclass 40, count 0 2006.175.08:09:39.36#ibcon#enter sib2, iclass 40, count 0 2006.175.08:09:39.36#ibcon#flushed, iclass 40, count 0 2006.175.08:09:39.36#ibcon#about to write, iclass 40, count 0 2006.175.08:09:39.36#ibcon#wrote, iclass 40, count 0 2006.175.08:09:39.36#ibcon#about to read 3, iclass 40, count 0 2006.175.08:09:39.38#ibcon#read 3, iclass 40, count 0 2006.175.08:09:39.38#ibcon#about to read 4, iclass 40, count 0 2006.175.08:09:39.38#ibcon#read 4, iclass 40, count 0 2006.175.08:09:39.38#ibcon#about to read 5, iclass 40, count 0 2006.175.08:09:39.38#ibcon#read 5, iclass 40, count 0 2006.175.08:09:39.38#ibcon#about to read 6, iclass 40, count 0 2006.175.08:09:39.38#ibcon#read 6, iclass 40, count 0 2006.175.08:09:39.38#ibcon#end of sib2, iclass 40, count 0 2006.175.08:09:39.38#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:09:39.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:09:39.38#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:09:39.38#ibcon#*before write, iclass 40, count 0 2006.175.08:09:39.38#ibcon#enter sib2, iclass 40, count 0 2006.175.08:09:39.38#ibcon#flushed, iclass 40, count 0 2006.175.08:09:39.38#ibcon#about to write, iclass 40, count 0 2006.175.08:09:39.38#ibcon#wrote, iclass 40, count 0 2006.175.08:09:39.38#ibcon#about to read 3, iclass 40, count 0 2006.175.08:09:39.42#ibcon#read 3, iclass 40, count 0 2006.175.08:09:39.42#ibcon#about to read 4, iclass 40, count 0 2006.175.08:09:39.42#ibcon#read 4, iclass 40, count 0 2006.175.08:09:39.42#ibcon#about to read 5, iclass 40, count 0 2006.175.08:09:39.42#ibcon#read 5, iclass 40, count 0 2006.175.08:09:39.42#ibcon#about to read 6, iclass 40, count 0 2006.175.08:09:39.42#ibcon#read 6, iclass 40, count 0 2006.175.08:09:39.42#ibcon#end of sib2, iclass 40, count 0 2006.175.08:09:39.42#ibcon#*after write, iclass 40, count 0 2006.175.08:09:39.42#ibcon#*before return 0, iclass 40, count 0 2006.175.08:09:39.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:39.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:39.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:09:39.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:09:39.42$vc4f8/va=5,7 2006.175.08:09:39.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.175.08:09:39.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.175.08:09:39.42#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:39.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:39.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:39.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:39.48#ibcon#enter wrdev, iclass 4, count 2 2006.175.08:09:39.48#ibcon#first serial, iclass 4, count 2 2006.175.08:09:39.48#ibcon#enter sib2, iclass 4, count 2 2006.175.08:09:39.48#ibcon#flushed, iclass 4, count 2 2006.175.08:09:39.48#ibcon#about to write, iclass 4, count 2 2006.175.08:09:39.48#ibcon#wrote, iclass 4, count 2 2006.175.08:09:39.48#ibcon#about to read 3, iclass 4, count 2 2006.175.08:09:39.50#ibcon#read 3, iclass 4, count 2 2006.175.08:09:39.50#ibcon#about to read 4, iclass 4, count 2 2006.175.08:09:39.50#ibcon#read 4, iclass 4, count 2 2006.175.08:09:39.50#ibcon#about to read 5, iclass 4, count 2 2006.175.08:09:39.50#ibcon#read 5, iclass 4, count 2 2006.175.08:09:39.50#ibcon#about to read 6, iclass 4, count 2 2006.175.08:09:39.50#ibcon#read 6, iclass 4, count 2 2006.175.08:09:39.50#ibcon#end of sib2, iclass 4, count 2 2006.175.08:09:39.50#ibcon#*mode == 0, iclass 4, count 2 2006.175.08:09:39.50#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.175.08:09:39.50#ibcon#[25=AT05-07\r\n] 2006.175.08:09:39.50#ibcon#*before write, iclass 4, count 2 2006.175.08:09:39.50#ibcon#enter sib2, iclass 4, count 2 2006.175.08:09:39.50#ibcon#flushed, iclass 4, count 2 2006.175.08:09:39.50#ibcon#about to write, iclass 4, count 2 2006.175.08:09:39.50#ibcon#wrote, iclass 4, count 2 2006.175.08:09:39.50#ibcon#about to read 3, iclass 4, count 2 2006.175.08:09:39.53#ibcon#read 3, iclass 4, count 2 2006.175.08:09:39.53#ibcon#about to read 4, iclass 4, count 2 2006.175.08:09:39.53#ibcon#read 4, iclass 4, count 2 2006.175.08:09:39.53#ibcon#about to read 5, iclass 4, count 2 2006.175.08:09:39.53#ibcon#read 5, iclass 4, count 2 2006.175.08:09:39.53#ibcon#about to read 6, iclass 4, count 2 2006.175.08:09:39.53#ibcon#read 6, iclass 4, count 2 2006.175.08:09:39.53#ibcon#end of sib2, iclass 4, count 2 2006.175.08:09:39.53#ibcon#*after write, iclass 4, count 2 2006.175.08:09:39.53#ibcon#*before return 0, iclass 4, count 2 2006.175.08:09:39.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:39.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:39.53#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.175.08:09:39.53#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:39.53#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:39.55#abcon#<5=/04 4.4 7.4 25.81 691007.3\r\n> 2006.175.08:09:39.57#abcon#{5=INTERFACE CLEAR} 2006.175.08:09:39.63#abcon#[5=S1D000X0/0*\r\n] 2006.175.08:09:39.65#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:39.65#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:39.65#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:09:39.65#ibcon#first serial, iclass 4, count 0 2006.175.08:09:39.65#ibcon#enter sib2, iclass 4, count 0 2006.175.08:09:39.65#ibcon#flushed, iclass 4, count 0 2006.175.08:09:39.65#ibcon#about to write, iclass 4, count 0 2006.175.08:09:39.65#ibcon#wrote, iclass 4, count 0 2006.175.08:09:39.65#ibcon#about to read 3, iclass 4, count 0 2006.175.08:09:39.67#ibcon#read 3, iclass 4, count 0 2006.175.08:09:39.67#ibcon#about to read 4, iclass 4, count 0 2006.175.08:09:39.67#ibcon#read 4, iclass 4, count 0 2006.175.08:09:39.67#ibcon#about to read 5, iclass 4, count 0 2006.175.08:09:39.67#ibcon#read 5, iclass 4, count 0 2006.175.08:09:39.67#ibcon#about to read 6, iclass 4, count 0 2006.175.08:09:39.67#ibcon#read 6, iclass 4, count 0 2006.175.08:09:39.67#ibcon#end of sib2, iclass 4, count 0 2006.175.08:09:39.67#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:09:39.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:09:39.67#ibcon#[25=USB\r\n] 2006.175.08:09:39.67#ibcon#*before write, iclass 4, count 0 2006.175.08:09:39.67#ibcon#enter sib2, iclass 4, count 0 2006.175.08:09:39.67#ibcon#flushed, iclass 4, count 0 2006.175.08:09:39.67#ibcon#about to write, iclass 4, count 0 2006.175.08:09:39.67#ibcon#wrote, iclass 4, count 0 2006.175.08:09:39.67#ibcon#about to read 3, iclass 4, count 0 2006.175.08:09:39.70#ibcon#read 3, iclass 4, count 0 2006.175.08:09:39.70#ibcon#about to read 4, iclass 4, count 0 2006.175.08:09:39.70#ibcon#read 4, iclass 4, count 0 2006.175.08:09:39.70#ibcon#about to read 5, iclass 4, count 0 2006.175.08:09:39.70#ibcon#read 5, iclass 4, count 0 2006.175.08:09:39.70#ibcon#about to read 6, iclass 4, count 0 2006.175.08:09:39.70#ibcon#read 6, iclass 4, count 0 2006.175.08:09:39.70#ibcon#end of sib2, iclass 4, count 0 2006.175.08:09:39.70#ibcon#*after write, iclass 4, count 0 2006.175.08:09:39.70#ibcon#*before return 0, iclass 4, count 0 2006.175.08:09:39.70#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:39.70#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:39.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:09:39.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:09:39.70$vc4f8/valo=6,772.99 2006.175.08:09:39.70#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.08:09:39.70#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.08:09:39.70#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:39.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:39.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:39.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:39.70#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:09:39.70#ibcon#first serial, iclass 12, count 0 2006.175.08:09:39.70#ibcon#enter sib2, iclass 12, count 0 2006.175.08:09:39.70#ibcon#flushed, iclass 12, count 0 2006.175.08:09:39.70#ibcon#about to write, iclass 12, count 0 2006.175.08:09:39.70#ibcon#wrote, iclass 12, count 0 2006.175.08:09:39.70#ibcon#about to read 3, iclass 12, count 0 2006.175.08:09:39.72#ibcon#read 3, iclass 12, count 0 2006.175.08:09:39.72#ibcon#about to read 4, iclass 12, count 0 2006.175.08:09:39.72#ibcon#read 4, iclass 12, count 0 2006.175.08:09:39.72#ibcon#about to read 5, iclass 12, count 0 2006.175.08:09:39.72#ibcon#read 5, iclass 12, count 0 2006.175.08:09:39.72#ibcon#about to read 6, iclass 12, count 0 2006.175.08:09:39.72#ibcon#read 6, iclass 12, count 0 2006.175.08:09:39.72#ibcon#end of sib2, iclass 12, count 0 2006.175.08:09:39.72#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:09:39.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:09:39.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:09:39.72#ibcon#*before write, iclass 12, count 0 2006.175.08:09:39.72#ibcon#enter sib2, iclass 12, count 0 2006.175.08:09:39.72#ibcon#flushed, iclass 12, count 0 2006.175.08:09:39.72#ibcon#about to write, iclass 12, count 0 2006.175.08:09:39.72#ibcon#wrote, iclass 12, count 0 2006.175.08:09:39.72#ibcon#about to read 3, iclass 12, count 0 2006.175.08:09:39.76#ibcon#read 3, iclass 12, count 0 2006.175.08:09:39.76#ibcon#about to read 4, iclass 12, count 0 2006.175.08:09:39.76#ibcon#read 4, iclass 12, count 0 2006.175.08:09:39.76#ibcon#about to read 5, iclass 12, count 0 2006.175.08:09:39.76#ibcon#read 5, iclass 12, count 0 2006.175.08:09:39.76#ibcon#about to read 6, iclass 12, count 0 2006.175.08:09:39.76#ibcon#read 6, iclass 12, count 0 2006.175.08:09:39.76#ibcon#end of sib2, iclass 12, count 0 2006.175.08:09:39.76#ibcon#*after write, iclass 12, count 0 2006.175.08:09:39.76#ibcon#*before return 0, iclass 12, count 0 2006.175.08:09:39.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:39.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:39.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:09:39.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:09:39.76$vc4f8/va=6,6 2006.175.08:09:39.76#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.08:09:39.76#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.08:09:39.76#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:39.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:09:39.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:09:39.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:09:39.82#ibcon#enter wrdev, iclass 14, count 2 2006.175.08:09:39.82#ibcon#first serial, iclass 14, count 2 2006.175.08:09:39.82#ibcon#enter sib2, iclass 14, count 2 2006.175.08:09:39.82#ibcon#flushed, iclass 14, count 2 2006.175.08:09:39.82#ibcon#about to write, iclass 14, count 2 2006.175.08:09:39.82#ibcon#wrote, iclass 14, count 2 2006.175.08:09:39.82#ibcon#about to read 3, iclass 14, count 2 2006.175.08:09:39.84#ibcon#read 3, iclass 14, count 2 2006.175.08:09:39.84#ibcon#about to read 4, iclass 14, count 2 2006.175.08:09:39.84#ibcon#read 4, iclass 14, count 2 2006.175.08:09:39.84#ibcon#about to read 5, iclass 14, count 2 2006.175.08:09:39.84#ibcon#read 5, iclass 14, count 2 2006.175.08:09:39.84#ibcon#about to read 6, iclass 14, count 2 2006.175.08:09:39.84#ibcon#read 6, iclass 14, count 2 2006.175.08:09:39.84#ibcon#end of sib2, iclass 14, count 2 2006.175.08:09:39.84#ibcon#*mode == 0, iclass 14, count 2 2006.175.08:09:39.84#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.08:09:39.84#ibcon#[25=AT06-06\r\n] 2006.175.08:09:39.84#ibcon#*before write, iclass 14, count 2 2006.175.08:09:39.84#ibcon#enter sib2, iclass 14, count 2 2006.175.08:09:39.84#ibcon#flushed, iclass 14, count 2 2006.175.08:09:39.84#ibcon#about to write, iclass 14, count 2 2006.175.08:09:39.84#ibcon#wrote, iclass 14, count 2 2006.175.08:09:39.84#ibcon#about to read 3, iclass 14, count 2 2006.175.08:09:39.87#ibcon#read 3, iclass 14, count 2 2006.175.08:09:39.87#ibcon#about to read 4, iclass 14, count 2 2006.175.08:09:39.87#ibcon#read 4, iclass 14, count 2 2006.175.08:09:39.87#ibcon#about to read 5, iclass 14, count 2 2006.175.08:09:39.87#ibcon#read 5, iclass 14, count 2 2006.175.08:09:39.87#ibcon#about to read 6, iclass 14, count 2 2006.175.08:09:39.87#ibcon#read 6, iclass 14, count 2 2006.175.08:09:39.87#ibcon#end of sib2, iclass 14, count 2 2006.175.08:09:39.87#ibcon#*after write, iclass 14, count 2 2006.175.08:09:39.87#ibcon#*before return 0, iclass 14, count 2 2006.175.08:09:39.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:09:39.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:09:39.87#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.08:09:39.87#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:39.87#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:09:39.99#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:09:39.99#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:09:39.99#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:09:39.99#ibcon#first serial, iclass 14, count 0 2006.175.08:09:39.99#ibcon#enter sib2, iclass 14, count 0 2006.175.08:09:39.99#ibcon#flushed, iclass 14, count 0 2006.175.08:09:39.99#ibcon#about to write, iclass 14, count 0 2006.175.08:09:39.99#ibcon#wrote, iclass 14, count 0 2006.175.08:09:39.99#ibcon#about to read 3, iclass 14, count 0 2006.175.08:09:40.01#ibcon#read 3, iclass 14, count 0 2006.175.08:09:40.01#ibcon#about to read 4, iclass 14, count 0 2006.175.08:09:40.01#ibcon#read 4, iclass 14, count 0 2006.175.08:09:40.01#ibcon#about to read 5, iclass 14, count 0 2006.175.08:09:40.01#ibcon#read 5, iclass 14, count 0 2006.175.08:09:40.01#ibcon#about to read 6, iclass 14, count 0 2006.175.08:09:40.01#ibcon#read 6, iclass 14, count 0 2006.175.08:09:40.01#ibcon#end of sib2, iclass 14, count 0 2006.175.08:09:40.01#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:09:40.01#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:09:40.01#ibcon#[25=USB\r\n] 2006.175.08:09:40.01#ibcon#*before write, iclass 14, count 0 2006.175.08:09:40.01#ibcon#enter sib2, iclass 14, count 0 2006.175.08:09:40.01#ibcon#flushed, iclass 14, count 0 2006.175.08:09:40.01#ibcon#about to write, iclass 14, count 0 2006.175.08:09:40.01#ibcon#wrote, iclass 14, count 0 2006.175.08:09:40.01#ibcon#about to read 3, iclass 14, count 0 2006.175.08:09:40.04#ibcon#read 3, iclass 14, count 0 2006.175.08:09:40.04#ibcon#about to read 4, iclass 14, count 0 2006.175.08:09:40.04#ibcon#read 4, iclass 14, count 0 2006.175.08:09:40.04#ibcon#about to read 5, iclass 14, count 0 2006.175.08:09:40.04#ibcon#read 5, iclass 14, count 0 2006.175.08:09:40.04#ibcon#about to read 6, iclass 14, count 0 2006.175.08:09:40.04#ibcon#read 6, iclass 14, count 0 2006.175.08:09:40.04#ibcon#end of sib2, iclass 14, count 0 2006.175.08:09:40.04#ibcon#*after write, iclass 14, count 0 2006.175.08:09:40.04#ibcon#*before return 0, iclass 14, count 0 2006.175.08:09:40.04#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:09:40.04#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:09:40.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:09:40.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:09:40.04$vc4f8/valo=7,832.99 2006.175.08:09:40.04#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.08:09:40.04#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.08:09:40.04#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:40.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:09:40.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:09:40.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:09:40.04#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:09:40.04#ibcon#first serial, iclass 16, count 0 2006.175.08:09:40.04#ibcon#enter sib2, iclass 16, count 0 2006.175.08:09:40.04#ibcon#flushed, iclass 16, count 0 2006.175.08:09:40.04#ibcon#about to write, iclass 16, count 0 2006.175.08:09:40.04#ibcon#wrote, iclass 16, count 0 2006.175.08:09:40.04#ibcon#about to read 3, iclass 16, count 0 2006.175.08:09:40.06#ibcon#read 3, iclass 16, count 0 2006.175.08:09:40.06#ibcon#about to read 4, iclass 16, count 0 2006.175.08:09:40.06#ibcon#read 4, iclass 16, count 0 2006.175.08:09:40.06#ibcon#about to read 5, iclass 16, count 0 2006.175.08:09:40.06#ibcon#read 5, iclass 16, count 0 2006.175.08:09:40.06#ibcon#about to read 6, iclass 16, count 0 2006.175.08:09:40.06#ibcon#read 6, iclass 16, count 0 2006.175.08:09:40.06#ibcon#end of sib2, iclass 16, count 0 2006.175.08:09:40.06#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:09:40.06#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:09:40.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:09:40.06#ibcon#*before write, iclass 16, count 0 2006.175.08:09:40.06#ibcon#enter sib2, iclass 16, count 0 2006.175.08:09:40.06#ibcon#flushed, iclass 16, count 0 2006.175.08:09:40.06#ibcon#about to write, iclass 16, count 0 2006.175.08:09:40.06#ibcon#wrote, iclass 16, count 0 2006.175.08:09:40.06#ibcon#about to read 3, iclass 16, count 0 2006.175.08:09:40.10#ibcon#read 3, iclass 16, count 0 2006.175.08:09:40.10#ibcon#about to read 4, iclass 16, count 0 2006.175.08:09:40.10#ibcon#read 4, iclass 16, count 0 2006.175.08:09:40.10#ibcon#about to read 5, iclass 16, count 0 2006.175.08:09:40.10#ibcon#read 5, iclass 16, count 0 2006.175.08:09:40.10#ibcon#about to read 6, iclass 16, count 0 2006.175.08:09:40.10#ibcon#read 6, iclass 16, count 0 2006.175.08:09:40.10#ibcon#end of sib2, iclass 16, count 0 2006.175.08:09:40.10#ibcon#*after write, iclass 16, count 0 2006.175.08:09:40.10#ibcon#*before return 0, iclass 16, count 0 2006.175.08:09:40.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:09:40.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:09:40.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:09:40.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:09:40.10$vc4f8/va=7,6 2006.175.08:09:40.10#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.08:09:40.10#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.08:09:40.10#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:40.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:09:40.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:09:40.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:09:40.16#ibcon#enter wrdev, iclass 18, count 2 2006.175.08:09:40.16#ibcon#first serial, iclass 18, count 2 2006.175.08:09:40.16#ibcon#enter sib2, iclass 18, count 2 2006.175.08:09:40.16#ibcon#flushed, iclass 18, count 2 2006.175.08:09:40.16#ibcon#about to write, iclass 18, count 2 2006.175.08:09:40.16#ibcon#wrote, iclass 18, count 2 2006.175.08:09:40.16#ibcon#about to read 3, iclass 18, count 2 2006.175.08:09:40.18#ibcon#read 3, iclass 18, count 2 2006.175.08:09:40.18#ibcon#about to read 4, iclass 18, count 2 2006.175.08:09:40.18#ibcon#read 4, iclass 18, count 2 2006.175.08:09:40.18#ibcon#about to read 5, iclass 18, count 2 2006.175.08:09:40.18#ibcon#read 5, iclass 18, count 2 2006.175.08:09:40.18#ibcon#about to read 6, iclass 18, count 2 2006.175.08:09:40.18#ibcon#read 6, iclass 18, count 2 2006.175.08:09:40.18#ibcon#end of sib2, iclass 18, count 2 2006.175.08:09:40.18#ibcon#*mode == 0, iclass 18, count 2 2006.175.08:09:40.18#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.08:09:40.18#ibcon#[25=AT07-06\r\n] 2006.175.08:09:40.18#ibcon#*before write, iclass 18, count 2 2006.175.08:09:40.18#ibcon#enter sib2, iclass 18, count 2 2006.175.08:09:40.18#ibcon#flushed, iclass 18, count 2 2006.175.08:09:40.18#ibcon#about to write, iclass 18, count 2 2006.175.08:09:40.18#ibcon#wrote, iclass 18, count 2 2006.175.08:09:40.18#ibcon#about to read 3, iclass 18, count 2 2006.175.08:09:40.21#ibcon#read 3, iclass 18, count 2 2006.175.08:09:40.21#ibcon#about to read 4, iclass 18, count 2 2006.175.08:09:40.21#ibcon#read 4, iclass 18, count 2 2006.175.08:09:40.21#ibcon#about to read 5, iclass 18, count 2 2006.175.08:09:40.21#ibcon#read 5, iclass 18, count 2 2006.175.08:09:40.21#ibcon#about to read 6, iclass 18, count 2 2006.175.08:09:40.21#ibcon#read 6, iclass 18, count 2 2006.175.08:09:40.21#ibcon#end of sib2, iclass 18, count 2 2006.175.08:09:40.21#ibcon#*after write, iclass 18, count 2 2006.175.08:09:40.21#ibcon#*before return 0, iclass 18, count 2 2006.175.08:09:40.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:09:40.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:09:40.21#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.08:09:40.21#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:40.21#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:09:40.33#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:09:40.33#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:09:40.33#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:09:40.33#ibcon#first serial, iclass 18, count 0 2006.175.08:09:40.33#ibcon#enter sib2, iclass 18, count 0 2006.175.08:09:40.33#ibcon#flushed, iclass 18, count 0 2006.175.08:09:40.33#ibcon#about to write, iclass 18, count 0 2006.175.08:09:40.33#ibcon#wrote, iclass 18, count 0 2006.175.08:09:40.33#ibcon#about to read 3, iclass 18, count 0 2006.175.08:09:40.35#ibcon#read 3, iclass 18, count 0 2006.175.08:09:40.35#ibcon#about to read 4, iclass 18, count 0 2006.175.08:09:40.35#ibcon#read 4, iclass 18, count 0 2006.175.08:09:40.35#ibcon#about to read 5, iclass 18, count 0 2006.175.08:09:40.35#ibcon#read 5, iclass 18, count 0 2006.175.08:09:40.35#ibcon#about to read 6, iclass 18, count 0 2006.175.08:09:40.35#ibcon#read 6, iclass 18, count 0 2006.175.08:09:40.35#ibcon#end of sib2, iclass 18, count 0 2006.175.08:09:40.35#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:09:40.35#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:09:40.35#ibcon#[25=USB\r\n] 2006.175.08:09:40.35#ibcon#*before write, iclass 18, count 0 2006.175.08:09:40.35#ibcon#enter sib2, iclass 18, count 0 2006.175.08:09:40.35#ibcon#flushed, iclass 18, count 0 2006.175.08:09:40.35#ibcon#about to write, iclass 18, count 0 2006.175.08:09:40.35#ibcon#wrote, iclass 18, count 0 2006.175.08:09:40.35#ibcon#about to read 3, iclass 18, count 0 2006.175.08:09:40.38#ibcon#read 3, iclass 18, count 0 2006.175.08:09:40.38#ibcon#about to read 4, iclass 18, count 0 2006.175.08:09:40.38#ibcon#read 4, iclass 18, count 0 2006.175.08:09:40.38#ibcon#about to read 5, iclass 18, count 0 2006.175.08:09:40.38#ibcon#read 5, iclass 18, count 0 2006.175.08:09:40.38#ibcon#about to read 6, iclass 18, count 0 2006.175.08:09:40.38#ibcon#read 6, iclass 18, count 0 2006.175.08:09:40.38#ibcon#end of sib2, iclass 18, count 0 2006.175.08:09:40.38#ibcon#*after write, iclass 18, count 0 2006.175.08:09:40.38#ibcon#*before return 0, iclass 18, count 0 2006.175.08:09:40.38#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:09:40.38#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:09:40.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:09:40.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:09:40.38$vc4f8/valo=8,852.99 2006.175.08:09:40.38#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.08:09:40.38#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.08:09:40.38#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:40.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:09:40.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:09:40.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:09:40.38#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:09:40.38#ibcon#first serial, iclass 20, count 0 2006.175.08:09:40.38#ibcon#enter sib2, iclass 20, count 0 2006.175.08:09:40.38#ibcon#flushed, iclass 20, count 0 2006.175.08:09:40.38#ibcon#about to write, iclass 20, count 0 2006.175.08:09:40.38#ibcon#wrote, iclass 20, count 0 2006.175.08:09:40.38#ibcon#about to read 3, iclass 20, count 0 2006.175.08:09:40.40#ibcon#read 3, iclass 20, count 0 2006.175.08:09:40.40#ibcon#about to read 4, iclass 20, count 0 2006.175.08:09:40.40#ibcon#read 4, iclass 20, count 0 2006.175.08:09:40.40#ibcon#about to read 5, iclass 20, count 0 2006.175.08:09:40.40#ibcon#read 5, iclass 20, count 0 2006.175.08:09:40.40#ibcon#about to read 6, iclass 20, count 0 2006.175.08:09:40.40#ibcon#read 6, iclass 20, count 0 2006.175.08:09:40.40#ibcon#end of sib2, iclass 20, count 0 2006.175.08:09:40.40#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:09:40.40#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:09:40.40#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:09:40.40#ibcon#*before write, iclass 20, count 0 2006.175.08:09:40.40#ibcon#enter sib2, iclass 20, count 0 2006.175.08:09:40.40#ibcon#flushed, iclass 20, count 0 2006.175.08:09:40.40#ibcon#about to write, iclass 20, count 0 2006.175.08:09:40.40#ibcon#wrote, iclass 20, count 0 2006.175.08:09:40.40#ibcon#about to read 3, iclass 20, count 0 2006.175.08:09:40.44#ibcon#read 3, iclass 20, count 0 2006.175.08:09:40.44#ibcon#about to read 4, iclass 20, count 0 2006.175.08:09:40.44#ibcon#read 4, iclass 20, count 0 2006.175.08:09:40.44#ibcon#about to read 5, iclass 20, count 0 2006.175.08:09:40.44#ibcon#read 5, iclass 20, count 0 2006.175.08:09:40.44#ibcon#about to read 6, iclass 20, count 0 2006.175.08:09:40.44#ibcon#read 6, iclass 20, count 0 2006.175.08:09:40.44#ibcon#end of sib2, iclass 20, count 0 2006.175.08:09:40.44#ibcon#*after write, iclass 20, count 0 2006.175.08:09:40.44#ibcon#*before return 0, iclass 20, count 0 2006.175.08:09:40.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:09:40.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:09:40.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:09:40.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:09:40.44$vc4f8/va=8,6 2006.175.08:09:40.44#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.08:09:40.44#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.08:09:40.44#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:40.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:09:40.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:09:40.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:09:40.50#ibcon#enter wrdev, iclass 22, count 2 2006.175.08:09:40.50#ibcon#first serial, iclass 22, count 2 2006.175.08:09:40.50#ibcon#enter sib2, iclass 22, count 2 2006.175.08:09:40.50#ibcon#flushed, iclass 22, count 2 2006.175.08:09:40.50#ibcon#about to write, iclass 22, count 2 2006.175.08:09:40.50#ibcon#wrote, iclass 22, count 2 2006.175.08:09:40.50#ibcon#about to read 3, iclass 22, count 2 2006.175.08:09:40.52#ibcon#read 3, iclass 22, count 2 2006.175.08:09:40.52#ibcon#about to read 4, iclass 22, count 2 2006.175.08:09:40.52#ibcon#read 4, iclass 22, count 2 2006.175.08:09:40.52#ibcon#about to read 5, iclass 22, count 2 2006.175.08:09:40.52#ibcon#read 5, iclass 22, count 2 2006.175.08:09:40.52#ibcon#about to read 6, iclass 22, count 2 2006.175.08:09:40.52#ibcon#read 6, iclass 22, count 2 2006.175.08:09:40.52#ibcon#end of sib2, iclass 22, count 2 2006.175.08:09:40.52#ibcon#*mode == 0, iclass 22, count 2 2006.175.08:09:40.52#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.08:09:40.52#ibcon#[25=AT08-06\r\n] 2006.175.08:09:40.52#ibcon#*before write, iclass 22, count 2 2006.175.08:09:40.52#ibcon#enter sib2, iclass 22, count 2 2006.175.08:09:40.52#ibcon#flushed, iclass 22, count 2 2006.175.08:09:40.52#ibcon#about to write, iclass 22, count 2 2006.175.08:09:40.52#ibcon#wrote, iclass 22, count 2 2006.175.08:09:40.52#ibcon#about to read 3, iclass 22, count 2 2006.175.08:09:40.55#ibcon#read 3, iclass 22, count 2 2006.175.08:09:40.55#ibcon#about to read 4, iclass 22, count 2 2006.175.08:09:40.55#ibcon#read 4, iclass 22, count 2 2006.175.08:09:40.55#ibcon#about to read 5, iclass 22, count 2 2006.175.08:09:40.55#ibcon#read 5, iclass 22, count 2 2006.175.08:09:40.55#ibcon#about to read 6, iclass 22, count 2 2006.175.08:09:40.55#ibcon#read 6, iclass 22, count 2 2006.175.08:09:40.55#ibcon#end of sib2, iclass 22, count 2 2006.175.08:09:40.55#ibcon#*after write, iclass 22, count 2 2006.175.08:09:40.55#ibcon#*before return 0, iclass 22, count 2 2006.175.08:09:40.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:09:40.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:09:40.55#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.08:09:40.55#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:40.55#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:09:40.67#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:09:40.67#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:09:40.67#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:09:40.67#ibcon#first serial, iclass 22, count 0 2006.175.08:09:40.67#ibcon#enter sib2, iclass 22, count 0 2006.175.08:09:40.67#ibcon#flushed, iclass 22, count 0 2006.175.08:09:40.67#ibcon#about to write, iclass 22, count 0 2006.175.08:09:40.67#ibcon#wrote, iclass 22, count 0 2006.175.08:09:40.67#ibcon#about to read 3, iclass 22, count 0 2006.175.08:09:40.69#ibcon#read 3, iclass 22, count 0 2006.175.08:09:40.69#ibcon#about to read 4, iclass 22, count 0 2006.175.08:09:40.69#ibcon#read 4, iclass 22, count 0 2006.175.08:09:40.69#ibcon#about to read 5, iclass 22, count 0 2006.175.08:09:40.69#ibcon#read 5, iclass 22, count 0 2006.175.08:09:40.69#ibcon#about to read 6, iclass 22, count 0 2006.175.08:09:40.69#ibcon#read 6, iclass 22, count 0 2006.175.08:09:40.69#ibcon#end of sib2, iclass 22, count 0 2006.175.08:09:40.69#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:09:40.69#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:09:40.69#ibcon#[25=USB\r\n] 2006.175.08:09:40.69#ibcon#*before write, iclass 22, count 0 2006.175.08:09:40.69#ibcon#enter sib2, iclass 22, count 0 2006.175.08:09:40.69#ibcon#flushed, iclass 22, count 0 2006.175.08:09:40.69#ibcon#about to write, iclass 22, count 0 2006.175.08:09:40.69#ibcon#wrote, iclass 22, count 0 2006.175.08:09:40.69#ibcon#about to read 3, iclass 22, count 0 2006.175.08:09:40.72#ibcon#read 3, iclass 22, count 0 2006.175.08:09:40.72#ibcon#about to read 4, iclass 22, count 0 2006.175.08:09:40.72#ibcon#read 4, iclass 22, count 0 2006.175.08:09:40.72#ibcon#about to read 5, iclass 22, count 0 2006.175.08:09:40.72#ibcon#read 5, iclass 22, count 0 2006.175.08:09:40.72#ibcon#about to read 6, iclass 22, count 0 2006.175.08:09:40.72#ibcon#read 6, iclass 22, count 0 2006.175.08:09:40.72#ibcon#end of sib2, iclass 22, count 0 2006.175.08:09:40.72#ibcon#*after write, iclass 22, count 0 2006.175.08:09:40.72#ibcon#*before return 0, iclass 22, count 0 2006.175.08:09:40.72#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:09:40.72#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:09:40.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:09:40.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:09:40.72$vc4f8/vblo=1,632.99 2006.175.08:09:40.72#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.08:09:40.72#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.08:09:40.72#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:40.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:40.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:40.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:40.72#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:09:40.72#ibcon#first serial, iclass 24, count 0 2006.175.08:09:40.72#ibcon#enter sib2, iclass 24, count 0 2006.175.08:09:40.72#ibcon#flushed, iclass 24, count 0 2006.175.08:09:40.72#ibcon#about to write, iclass 24, count 0 2006.175.08:09:40.72#ibcon#wrote, iclass 24, count 0 2006.175.08:09:40.72#ibcon#about to read 3, iclass 24, count 0 2006.175.08:09:40.74#ibcon#read 3, iclass 24, count 0 2006.175.08:09:40.74#ibcon#about to read 4, iclass 24, count 0 2006.175.08:09:40.74#ibcon#read 4, iclass 24, count 0 2006.175.08:09:40.74#ibcon#about to read 5, iclass 24, count 0 2006.175.08:09:40.74#ibcon#read 5, iclass 24, count 0 2006.175.08:09:40.74#ibcon#about to read 6, iclass 24, count 0 2006.175.08:09:40.74#ibcon#read 6, iclass 24, count 0 2006.175.08:09:40.74#ibcon#end of sib2, iclass 24, count 0 2006.175.08:09:40.74#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:09:40.74#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:09:40.74#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:09:40.74#ibcon#*before write, iclass 24, count 0 2006.175.08:09:40.74#ibcon#enter sib2, iclass 24, count 0 2006.175.08:09:40.74#ibcon#flushed, iclass 24, count 0 2006.175.08:09:40.74#ibcon#about to write, iclass 24, count 0 2006.175.08:09:40.74#ibcon#wrote, iclass 24, count 0 2006.175.08:09:40.74#ibcon#about to read 3, iclass 24, count 0 2006.175.08:09:40.78#ibcon#read 3, iclass 24, count 0 2006.175.08:09:40.78#ibcon#about to read 4, iclass 24, count 0 2006.175.08:09:40.78#ibcon#read 4, iclass 24, count 0 2006.175.08:09:40.78#ibcon#about to read 5, iclass 24, count 0 2006.175.08:09:40.78#ibcon#read 5, iclass 24, count 0 2006.175.08:09:40.78#ibcon#about to read 6, iclass 24, count 0 2006.175.08:09:40.78#ibcon#read 6, iclass 24, count 0 2006.175.08:09:40.78#ibcon#end of sib2, iclass 24, count 0 2006.175.08:09:40.78#ibcon#*after write, iclass 24, count 0 2006.175.08:09:40.78#ibcon#*before return 0, iclass 24, count 0 2006.175.08:09:40.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:40.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:09:40.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:09:40.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:09:40.78$vc4f8/vb=1,4 2006.175.08:09:40.78#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.08:09:40.78#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.08:09:40.78#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:40.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:40.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:40.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:40.78#ibcon#enter wrdev, iclass 26, count 2 2006.175.08:09:40.78#ibcon#first serial, iclass 26, count 2 2006.175.08:09:40.78#ibcon#enter sib2, iclass 26, count 2 2006.175.08:09:40.78#ibcon#flushed, iclass 26, count 2 2006.175.08:09:40.78#ibcon#about to write, iclass 26, count 2 2006.175.08:09:40.78#ibcon#wrote, iclass 26, count 2 2006.175.08:09:40.78#ibcon#about to read 3, iclass 26, count 2 2006.175.08:09:40.80#ibcon#read 3, iclass 26, count 2 2006.175.08:09:40.80#ibcon#about to read 4, iclass 26, count 2 2006.175.08:09:40.80#ibcon#read 4, iclass 26, count 2 2006.175.08:09:40.80#ibcon#about to read 5, iclass 26, count 2 2006.175.08:09:40.80#ibcon#read 5, iclass 26, count 2 2006.175.08:09:40.80#ibcon#about to read 6, iclass 26, count 2 2006.175.08:09:40.80#ibcon#read 6, iclass 26, count 2 2006.175.08:09:40.80#ibcon#end of sib2, iclass 26, count 2 2006.175.08:09:40.80#ibcon#*mode == 0, iclass 26, count 2 2006.175.08:09:40.80#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.08:09:40.80#ibcon#[27=AT01-04\r\n] 2006.175.08:09:40.80#ibcon#*before write, iclass 26, count 2 2006.175.08:09:40.80#ibcon#enter sib2, iclass 26, count 2 2006.175.08:09:40.80#ibcon#flushed, iclass 26, count 2 2006.175.08:09:40.80#ibcon#about to write, iclass 26, count 2 2006.175.08:09:40.80#ibcon#wrote, iclass 26, count 2 2006.175.08:09:40.80#ibcon#about to read 3, iclass 26, count 2 2006.175.08:09:40.83#ibcon#read 3, iclass 26, count 2 2006.175.08:09:40.83#ibcon#about to read 4, iclass 26, count 2 2006.175.08:09:40.83#ibcon#read 4, iclass 26, count 2 2006.175.08:09:40.83#ibcon#about to read 5, iclass 26, count 2 2006.175.08:09:40.83#ibcon#read 5, iclass 26, count 2 2006.175.08:09:40.83#ibcon#about to read 6, iclass 26, count 2 2006.175.08:09:40.83#ibcon#read 6, iclass 26, count 2 2006.175.08:09:40.83#ibcon#end of sib2, iclass 26, count 2 2006.175.08:09:40.83#ibcon#*after write, iclass 26, count 2 2006.175.08:09:40.83#ibcon#*before return 0, iclass 26, count 2 2006.175.08:09:40.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:40.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:09:40.83#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.08:09:40.83#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:40.83#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:40.95#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:40.95#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:40.95#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:09:40.95#ibcon#first serial, iclass 26, count 0 2006.175.08:09:40.95#ibcon#enter sib2, iclass 26, count 0 2006.175.08:09:40.95#ibcon#flushed, iclass 26, count 0 2006.175.08:09:40.95#ibcon#about to write, iclass 26, count 0 2006.175.08:09:40.95#ibcon#wrote, iclass 26, count 0 2006.175.08:09:40.95#ibcon#about to read 3, iclass 26, count 0 2006.175.08:09:40.97#ibcon#read 3, iclass 26, count 0 2006.175.08:09:40.97#ibcon#about to read 4, iclass 26, count 0 2006.175.08:09:40.97#ibcon#read 4, iclass 26, count 0 2006.175.08:09:40.97#ibcon#about to read 5, iclass 26, count 0 2006.175.08:09:40.97#ibcon#read 5, iclass 26, count 0 2006.175.08:09:40.97#ibcon#about to read 6, iclass 26, count 0 2006.175.08:09:40.97#ibcon#read 6, iclass 26, count 0 2006.175.08:09:40.97#ibcon#end of sib2, iclass 26, count 0 2006.175.08:09:40.97#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:09:40.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:09:40.97#ibcon#[27=USB\r\n] 2006.175.08:09:40.97#ibcon#*before write, iclass 26, count 0 2006.175.08:09:40.97#ibcon#enter sib2, iclass 26, count 0 2006.175.08:09:40.97#ibcon#flushed, iclass 26, count 0 2006.175.08:09:40.97#ibcon#about to write, iclass 26, count 0 2006.175.08:09:40.97#ibcon#wrote, iclass 26, count 0 2006.175.08:09:40.97#ibcon#about to read 3, iclass 26, count 0 2006.175.08:09:41.00#ibcon#read 3, iclass 26, count 0 2006.175.08:09:41.00#ibcon#about to read 4, iclass 26, count 0 2006.175.08:09:41.00#ibcon#read 4, iclass 26, count 0 2006.175.08:09:41.00#ibcon#about to read 5, iclass 26, count 0 2006.175.08:09:41.00#ibcon#read 5, iclass 26, count 0 2006.175.08:09:41.00#ibcon#about to read 6, iclass 26, count 0 2006.175.08:09:41.00#ibcon#read 6, iclass 26, count 0 2006.175.08:09:41.00#ibcon#end of sib2, iclass 26, count 0 2006.175.08:09:41.00#ibcon#*after write, iclass 26, count 0 2006.175.08:09:41.00#ibcon#*before return 0, iclass 26, count 0 2006.175.08:09:41.00#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:41.00#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:09:41.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:09:41.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:09:41.00$vc4f8/vblo=2,640.99 2006.175.08:09:41.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.08:09:41.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.08:09:41.00#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:41.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:41.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:41.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:41.00#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:09:41.00#ibcon#first serial, iclass 28, count 0 2006.175.08:09:41.00#ibcon#enter sib2, iclass 28, count 0 2006.175.08:09:41.00#ibcon#flushed, iclass 28, count 0 2006.175.08:09:41.00#ibcon#about to write, iclass 28, count 0 2006.175.08:09:41.00#ibcon#wrote, iclass 28, count 0 2006.175.08:09:41.00#ibcon#about to read 3, iclass 28, count 0 2006.175.08:09:41.02#ibcon#read 3, iclass 28, count 0 2006.175.08:09:41.02#ibcon#about to read 4, iclass 28, count 0 2006.175.08:09:41.02#ibcon#read 4, iclass 28, count 0 2006.175.08:09:41.02#ibcon#about to read 5, iclass 28, count 0 2006.175.08:09:41.02#ibcon#read 5, iclass 28, count 0 2006.175.08:09:41.02#ibcon#about to read 6, iclass 28, count 0 2006.175.08:09:41.02#ibcon#read 6, iclass 28, count 0 2006.175.08:09:41.02#ibcon#end of sib2, iclass 28, count 0 2006.175.08:09:41.02#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:09:41.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:09:41.02#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:09:41.02#ibcon#*before write, iclass 28, count 0 2006.175.08:09:41.02#ibcon#enter sib2, iclass 28, count 0 2006.175.08:09:41.02#ibcon#flushed, iclass 28, count 0 2006.175.08:09:41.02#ibcon#about to write, iclass 28, count 0 2006.175.08:09:41.02#ibcon#wrote, iclass 28, count 0 2006.175.08:09:41.02#ibcon#about to read 3, iclass 28, count 0 2006.175.08:09:41.06#ibcon#read 3, iclass 28, count 0 2006.175.08:09:41.06#ibcon#about to read 4, iclass 28, count 0 2006.175.08:09:41.06#ibcon#read 4, iclass 28, count 0 2006.175.08:09:41.06#ibcon#about to read 5, iclass 28, count 0 2006.175.08:09:41.06#ibcon#read 5, iclass 28, count 0 2006.175.08:09:41.06#ibcon#about to read 6, iclass 28, count 0 2006.175.08:09:41.06#ibcon#read 6, iclass 28, count 0 2006.175.08:09:41.06#ibcon#end of sib2, iclass 28, count 0 2006.175.08:09:41.06#ibcon#*after write, iclass 28, count 0 2006.175.08:09:41.06#ibcon#*before return 0, iclass 28, count 0 2006.175.08:09:41.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:41.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:09:41.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:09:41.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:09:41.06$vc4f8/vb=2,4 2006.175.08:09:41.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.08:09:41.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.08:09:41.06#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:41.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:41.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:41.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:41.13#ibcon#enter wrdev, iclass 30, count 2 2006.175.08:09:41.13#ibcon#first serial, iclass 30, count 2 2006.175.08:09:41.13#ibcon#enter sib2, iclass 30, count 2 2006.175.08:09:41.13#ibcon#flushed, iclass 30, count 2 2006.175.08:09:41.13#ibcon#about to write, iclass 30, count 2 2006.175.08:09:41.13#ibcon#wrote, iclass 30, count 2 2006.175.08:09:41.13#ibcon#about to read 3, iclass 30, count 2 2006.175.08:09:41.14#ibcon#read 3, iclass 30, count 2 2006.175.08:09:41.14#ibcon#about to read 4, iclass 30, count 2 2006.175.08:09:41.14#ibcon#read 4, iclass 30, count 2 2006.175.08:09:41.14#ibcon#about to read 5, iclass 30, count 2 2006.175.08:09:41.14#ibcon#read 5, iclass 30, count 2 2006.175.08:09:41.14#ibcon#about to read 6, iclass 30, count 2 2006.175.08:09:41.14#ibcon#read 6, iclass 30, count 2 2006.175.08:09:41.14#ibcon#end of sib2, iclass 30, count 2 2006.175.08:09:41.14#ibcon#*mode == 0, iclass 30, count 2 2006.175.08:09:41.14#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.08:09:41.14#ibcon#[27=AT02-04\r\n] 2006.175.08:09:41.14#ibcon#*before write, iclass 30, count 2 2006.175.08:09:41.14#ibcon#enter sib2, iclass 30, count 2 2006.175.08:09:41.14#ibcon#flushed, iclass 30, count 2 2006.175.08:09:41.14#ibcon#about to write, iclass 30, count 2 2006.175.08:09:41.14#ibcon#wrote, iclass 30, count 2 2006.175.08:09:41.14#ibcon#about to read 3, iclass 30, count 2 2006.175.08:09:41.17#ibcon#read 3, iclass 30, count 2 2006.175.08:09:41.17#ibcon#about to read 4, iclass 30, count 2 2006.175.08:09:41.17#ibcon#read 4, iclass 30, count 2 2006.175.08:09:41.17#ibcon#about to read 5, iclass 30, count 2 2006.175.08:09:41.17#ibcon#read 5, iclass 30, count 2 2006.175.08:09:41.17#ibcon#about to read 6, iclass 30, count 2 2006.175.08:09:41.17#ibcon#read 6, iclass 30, count 2 2006.175.08:09:41.17#ibcon#end of sib2, iclass 30, count 2 2006.175.08:09:41.17#ibcon#*after write, iclass 30, count 2 2006.175.08:09:41.17#ibcon#*before return 0, iclass 30, count 2 2006.175.08:09:41.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:41.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:09:41.17#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.08:09:41.17#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:41.17#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:41.29#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:41.29#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:41.29#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:09:41.29#ibcon#first serial, iclass 30, count 0 2006.175.08:09:41.29#ibcon#enter sib2, iclass 30, count 0 2006.175.08:09:41.29#ibcon#flushed, iclass 30, count 0 2006.175.08:09:41.29#ibcon#about to write, iclass 30, count 0 2006.175.08:09:41.29#ibcon#wrote, iclass 30, count 0 2006.175.08:09:41.29#ibcon#about to read 3, iclass 30, count 0 2006.175.08:09:41.31#ibcon#read 3, iclass 30, count 0 2006.175.08:09:41.31#ibcon#about to read 4, iclass 30, count 0 2006.175.08:09:41.31#ibcon#read 4, iclass 30, count 0 2006.175.08:09:41.31#ibcon#about to read 5, iclass 30, count 0 2006.175.08:09:41.31#ibcon#read 5, iclass 30, count 0 2006.175.08:09:41.31#ibcon#about to read 6, iclass 30, count 0 2006.175.08:09:41.31#ibcon#read 6, iclass 30, count 0 2006.175.08:09:41.31#ibcon#end of sib2, iclass 30, count 0 2006.175.08:09:41.31#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:09:41.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:09:41.31#ibcon#[27=USB\r\n] 2006.175.08:09:41.31#ibcon#*before write, iclass 30, count 0 2006.175.08:09:41.31#ibcon#enter sib2, iclass 30, count 0 2006.175.08:09:41.31#ibcon#flushed, iclass 30, count 0 2006.175.08:09:41.31#ibcon#about to write, iclass 30, count 0 2006.175.08:09:41.31#ibcon#wrote, iclass 30, count 0 2006.175.08:09:41.31#ibcon#about to read 3, iclass 30, count 0 2006.175.08:09:41.34#ibcon#read 3, iclass 30, count 0 2006.175.08:09:41.34#ibcon#about to read 4, iclass 30, count 0 2006.175.08:09:41.34#ibcon#read 4, iclass 30, count 0 2006.175.08:09:41.34#ibcon#about to read 5, iclass 30, count 0 2006.175.08:09:41.34#ibcon#read 5, iclass 30, count 0 2006.175.08:09:41.34#ibcon#about to read 6, iclass 30, count 0 2006.175.08:09:41.34#ibcon#read 6, iclass 30, count 0 2006.175.08:09:41.34#ibcon#end of sib2, iclass 30, count 0 2006.175.08:09:41.34#ibcon#*after write, iclass 30, count 0 2006.175.08:09:41.34#ibcon#*before return 0, iclass 30, count 0 2006.175.08:09:41.34#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:41.34#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:09:41.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:09:41.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:09:41.34$vc4f8/vblo=3,656.99 2006.175.08:09:41.34#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.08:09:41.34#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.08:09:41.34#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:41.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:41.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:41.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:41.34#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:09:41.34#ibcon#first serial, iclass 32, count 0 2006.175.08:09:41.34#ibcon#enter sib2, iclass 32, count 0 2006.175.08:09:41.34#ibcon#flushed, iclass 32, count 0 2006.175.08:09:41.34#ibcon#about to write, iclass 32, count 0 2006.175.08:09:41.34#ibcon#wrote, iclass 32, count 0 2006.175.08:09:41.34#ibcon#about to read 3, iclass 32, count 0 2006.175.08:09:41.36#ibcon#read 3, iclass 32, count 0 2006.175.08:09:41.36#ibcon#about to read 4, iclass 32, count 0 2006.175.08:09:41.36#ibcon#read 4, iclass 32, count 0 2006.175.08:09:41.36#ibcon#about to read 5, iclass 32, count 0 2006.175.08:09:41.36#ibcon#read 5, iclass 32, count 0 2006.175.08:09:41.36#ibcon#about to read 6, iclass 32, count 0 2006.175.08:09:41.36#ibcon#read 6, iclass 32, count 0 2006.175.08:09:41.36#ibcon#end of sib2, iclass 32, count 0 2006.175.08:09:41.36#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:09:41.36#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:09:41.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:09:41.36#ibcon#*before write, iclass 32, count 0 2006.175.08:09:41.36#ibcon#enter sib2, iclass 32, count 0 2006.175.08:09:41.36#ibcon#flushed, iclass 32, count 0 2006.175.08:09:41.36#ibcon#about to write, iclass 32, count 0 2006.175.08:09:41.36#ibcon#wrote, iclass 32, count 0 2006.175.08:09:41.36#ibcon#about to read 3, iclass 32, count 0 2006.175.08:09:41.40#ibcon#read 3, iclass 32, count 0 2006.175.08:09:41.40#ibcon#about to read 4, iclass 32, count 0 2006.175.08:09:41.40#ibcon#read 4, iclass 32, count 0 2006.175.08:09:41.40#ibcon#about to read 5, iclass 32, count 0 2006.175.08:09:41.40#ibcon#read 5, iclass 32, count 0 2006.175.08:09:41.40#ibcon#about to read 6, iclass 32, count 0 2006.175.08:09:41.40#ibcon#read 6, iclass 32, count 0 2006.175.08:09:41.40#ibcon#end of sib2, iclass 32, count 0 2006.175.08:09:41.40#ibcon#*after write, iclass 32, count 0 2006.175.08:09:41.40#ibcon#*before return 0, iclass 32, count 0 2006.175.08:09:41.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:41.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:09:41.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:09:41.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:09:41.40$vc4f8/vb=3,4 2006.175.08:09:41.40#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.175.08:09:41.40#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.175.08:09:41.40#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:41.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:41.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:41.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:41.46#ibcon#enter wrdev, iclass 34, count 2 2006.175.08:09:41.46#ibcon#first serial, iclass 34, count 2 2006.175.08:09:41.46#ibcon#enter sib2, iclass 34, count 2 2006.175.08:09:41.46#ibcon#flushed, iclass 34, count 2 2006.175.08:09:41.46#ibcon#about to write, iclass 34, count 2 2006.175.08:09:41.46#ibcon#wrote, iclass 34, count 2 2006.175.08:09:41.46#ibcon#about to read 3, iclass 34, count 2 2006.175.08:09:41.48#ibcon#read 3, iclass 34, count 2 2006.175.08:09:41.48#ibcon#about to read 4, iclass 34, count 2 2006.175.08:09:41.48#ibcon#read 4, iclass 34, count 2 2006.175.08:09:41.48#ibcon#about to read 5, iclass 34, count 2 2006.175.08:09:41.48#ibcon#read 5, iclass 34, count 2 2006.175.08:09:41.48#ibcon#about to read 6, iclass 34, count 2 2006.175.08:09:41.48#ibcon#read 6, iclass 34, count 2 2006.175.08:09:41.48#ibcon#end of sib2, iclass 34, count 2 2006.175.08:09:41.48#ibcon#*mode == 0, iclass 34, count 2 2006.175.08:09:41.48#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.175.08:09:41.48#ibcon#[27=AT03-04\r\n] 2006.175.08:09:41.48#ibcon#*before write, iclass 34, count 2 2006.175.08:09:41.48#ibcon#enter sib2, iclass 34, count 2 2006.175.08:09:41.48#ibcon#flushed, iclass 34, count 2 2006.175.08:09:41.48#ibcon#about to write, iclass 34, count 2 2006.175.08:09:41.48#ibcon#wrote, iclass 34, count 2 2006.175.08:09:41.48#ibcon#about to read 3, iclass 34, count 2 2006.175.08:09:41.51#ibcon#read 3, iclass 34, count 2 2006.175.08:09:41.51#ibcon#about to read 4, iclass 34, count 2 2006.175.08:09:41.51#ibcon#read 4, iclass 34, count 2 2006.175.08:09:41.51#ibcon#about to read 5, iclass 34, count 2 2006.175.08:09:41.51#ibcon#read 5, iclass 34, count 2 2006.175.08:09:41.51#ibcon#about to read 6, iclass 34, count 2 2006.175.08:09:41.51#ibcon#read 6, iclass 34, count 2 2006.175.08:09:41.51#ibcon#end of sib2, iclass 34, count 2 2006.175.08:09:41.51#ibcon#*after write, iclass 34, count 2 2006.175.08:09:41.51#ibcon#*before return 0, iclass 34, count 2 2006.175.08:09:41.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:41.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:09:41.51#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.175.08:09:41.51#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:41.51#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:41.63#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:41.63#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:41.63#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:09:41.63#ibcon#first serial, iclass 34, count 0 2006.175.08:09:41.63#ibcon#enter sib2, iclass 34, count 0 2006.175.08:09:41.63#ibcon#flushed, iclass 34, count 0 2006.175.08:09:41.63#ibcon#about to write, iclass 34, count 0 2006.175.08:09:41.63#ibcon#wrote, iclass 34, count 0 2006.175.08:09:41.63#ibcon#about to read 3, iclass 34, count 0 2006.175.08:09:41.65#ibcon#read 3, iclass 34, count 0 2006.175.08:09:41.65#ibcon#about to read 4, iclass 34, count 0 2006.175.08:09:41.65#ibcon#read 4, iclass 34, count 0 2006.175.08:09:41.65#ibcon#about to read 5, iclass 34, count 0 2006.175.08:09:41.65#ibcon#read 5, iclass 34, count 0 2006.175.08:09:41.65#ibcon#about to read 6, iclass 34, count 0 2006.175.08:09:41.65#ibcon#read 6, iclass 34, count 0 2006.175.08:09:41.65#ibcon#end of sib2, iclass 34, count 0 2006.175.08:09:41.65#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:09:41.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:09:41.65#ibcon#[27=USB\r\n] 2006.175.08:09:41.65#ibcon#*before write, iclass 34, count 0 2006.175.08:09:41.65#ibcon#enter sib2, iclass 34, count 0 2006.175.08:09:41.65#ibcon#flushed, iclass 34, count 0 2006.175.08:09:41.65#ibcon#about to write, iclass 34, count 0 2006.175.08:09:41.65#ibcon#wrote, iclass 34, count 0 2006.175.08:09:41.65#ibcon#about to read 3, iclass 34, count 0 2006.175.08:09:41.68#ibcon#read 3, iclass 34, count 0 2006.175.08:09:41.68#ibcon#about to read 4, iclass 34, count 0 2006.175.08:09:41.68#ibcon#read 4, iclass 34, count 0 2006.175.08:09:41.68#ibcon#about to read 5, iclass 34, count 0 2006.175.08:09:41.68#ibcon#read 5, iclass 34, count 0 2006.175.08:09:41.68#ibcon#about to read 6, iclass 34, count 0 2006.175.08:09:41.68#ibcon#read 6, iclass 34, count 0 2006.175.08:09:41.68#ibcon#end of sib2, iclass 34, count 0 2006.175.08:09:41.68#ibcon#*after write, iclass 34, count 0 2006.175.08:09:41.68#ibcon#*before return 0, iclass 34, count 0 2006.175.08:09:41.68#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:41.68#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:09:41.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:09:41.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:09:41.68$vc4f8/vblo=4,712.99 2006.175.08:09:41.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.08:09:41.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.08:09:41.68#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:41.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:41.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:41.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:41.68#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:09:41.68#ibcon#first serial, iclass 36, count 0 2006.175.08:09:41.68#ibcon#enter sib2, iclass 36, count 0 2006.175.08:09:41.68#ibcon#flushed, iclass 36, count 0 2006.175.08:09:41.68#ibcon#about to write, iclass 36, count 0 2006.175.08:09:41.68#ibcon#wrote, iclass 36, count 0 2006.175.08:09:41.68#ibcon#about to read 3, iclass 36, count 0 2006.175.08:09:41.70#ibcon#read 3, iclass 36, count 0 2006.175.08:09:41.70#ibcon#about to read 4, iclass 36, count 0 2006.175.08:09:41.70#ibcon#read 4, iclass 36, count 0 2006.175.08:09:41.70#ibcon#about to read 5, iclass 36, count 0 2006.175.08:09:41.70#ibcon#read 5, iclass 36, count 0 2006.175.08:09:41.70#ibcon#about to read 6, iclass 36, count 0 2006.175.08:09:41.70#ibcon#read 6, iclass 36, count 0 2006.175.08:09:41.70#ibcon#end of sib2, iclass 36, count 0 2006.175.08:09:41.70#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:09:41.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:09:41.70#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:09:41.70#ibcon#*before write, iclass 36, count 0 2006.175.08:09:41.70#ibcon#enter sib2, iclass 36, count 0 2006.175.08:09:41.70#ibcon#flushed, iclass 36, count 0 2006.175.08:09:41.70#ibcon#about to write, iclass 36, count 0 2006.175.08:09:41.70#ibcon#wrote, iclass 36, count 0 2006.175.08:09:41.70#ibcon#about to read 3, iclass 36, count 0 2006.175.08:09:41.74#ibcon#read 3, iclass 36, count 0 2006.175.08:09:41.74#ibcon#about to read 4, iclass 36, count 0 2006.175.08:09:41.74#ibcon#read 4, iclass 36, count 0 2006.175.08:09:41.74#ibcon#about to read 5, iclass 36, count 0 2006.175.08:09:41.74#ibcon#read 5, iclass 36, count 0 2006.175.08:09:41.74#ibcon#about to read 6, iclass 36, count 0 2006.175.08:09:41.74#ibcon#read 6, iclass 36, count 0 2006.175.08:09:41.74#ibcon#end of sib2, iclass 36, count 0 2006.175.08:09:41.74#ibcon#*after write, iclass 36, count 0 2006.175.08:09:41.74#ibcon#*before return 0, iclass 36, count 0 2006.175.08:09:41.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:41.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:09:41.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:09:41.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:09:41.74$vc4f8/vb=4,4 2006.175.08:09:41.74#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.175.08:09:41.74#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.175.08:09:41.74#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:41.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:41.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:41.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:41.80#ibcon#enter wrdev, iclass 38, count 2 2006.175.08:09:41.80#ibcon#first serial, iclass 38, count 2 2006.175.08:09:41.80#ibcon#enter sib2, iclass 38, count 2 2006.175.08:09:41.80#ibcon#flushed, iclass 38, count 2 2006.175.08:09:41.80#ibcon#about to write, iclass 38, count 2 2006.175.08:09:41.80#ibcon#wrote, iclass 38, count 2 2006.175.08:09:41.80#ibcon#about to read 3, iclass 38, count 2 2006.175.08:09:41.82#ibcon#read 3, iclass 38, count 2 2006.175.08:09:41.82#ibcon#about to read 4, iclass 38, count 2 2006.175.08:09:41.82#ibcon#read 4, iclass 38, count 2 2006.175.08:09:41.82#ibcon#about to read 5, iclass 38, count 2 2006.175.08:09:41.82#ibcon#read 5, iclass 38, count 2 2006.175.08:09:41.82#ibcon#about to read 6, iclass 38, count 2 2006.175.08:09:41.82#ibcon#read 6, iclass 38, count 2 2006.175.08:09:41.82#ibcon#end of sib2, iclass 38, count 2 2006.175.08:09:41.82#ibcon#*mode == 0, iclass 38, count 2 2006.175.08:09:41.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.175.08:09:41.82#ibcon#[27=AT04-04\r\n] 2006.175.08:09:41.82#ibcon#*before write, iclass 38, count 2 2006.175.08:09:41.82#ibcon#enter sib2, iclass 38, count 2 2006.175.08:09:41.82#ibcon#flushed, iclass 38, count 2 2006.175.08:09:41.82#ibcon#about to write, iclass 38, count 2 2006.175.08:09:41.82#ibcon#wrote, iclass 38, count 2 2006.175.08:09:41.82#ibcon#about to read 3, iclass 38, count 2 2006.175.08:09:41.85#ibcon#read 3, iclass 38, count 2 2006.175.08:09:41.85#ibcon#about to read 4, iclass 38, count 2 2006.175.08:09:41.85#ibcon#read 4, iclass 38, count 2 2006.175.08:09:41.85#ibcon#about to read 5, iclass 38, count 2 2006.175.08:09:41.85#ibcon#read 5, iclass 38, count 2 2006.175.08:09:41.85#ibcon#about to read 6, iclass 38, count 2 2006.175.08:09:41.85#ibcon#read 6, iclass 38, count 2 2006.175.08:09:41.85#ibcon#end of sib2, iclass 38, count 2 2006.175.08:09:41.85#ibcon#*after write, iclass 38, count 2 2006.175.08:09:41.85#ibcon#*before return 0, iclass 38, count 2 2006.175.08:09:41.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:41.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:09:41.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.175.08:09:41.85#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:41.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:41.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:41.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:41.97#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:09:41.97#ibcon#first serial, iclass 38, count 0 2006.175.08:09:41.97#ibcon#enter sib2, iclass 38, count 0 2006.175.08:09:41.97#ibcon#flushed, iclass 38, count 0 2006.175.08:09:41.97#ibcon#about to write, iclass 38, count 0 2006.175.08:09:41.97#ibcon#wrote, iclass 38, count 0 2006.175.08:09:41.97#ibcon#about to read 3, iclass 38, count 0 2006.175.08:09:41.99#ibcon#read 3, iclass 38, count 0 2006.175.08:09:41.99#ibcon#about to read 4, iclass 38, count 0 2006.175.08:09:41.99#ibcon#read 4, iclass 38, count 0 2006.175.08:09:41.99#ibcon#about to read 5, iclass 38, count 0 2006.175.08:09:41.99#ibcon#read 5, iclass 38, count 0 2006.175.08:09:41.99#ibcon#about to read 6, iclass 38, count 0 2006.175.08:09:41.99#ibcon#read 6, iclass 38, count 0 2006.175.08:09:41.99#ibcon#end of sib2, iclass 38, count 0 2006.175.08:09:41.99#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:09:41.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:09:41.99#ibcon#[27=USB\r\n] 2006.175.08:09:41.99#ibcon#*before write, iclass 38, count 0 2006.175.08:09:41.99#ibcon#enter sib2, iclass 38, count 0 2006.175.08:09:41.99#ibcon#flushed, iclass 38, count 0 2006.175.08:09:41.99#ibcon#about to write, iclass 38, count 0 2006.175.08:09:41.99#ibcon#wrote, iclass 38, count 0 2006.175.08:09:41.99#ibcon#about to read 3, iclass 38, count 0 2006.175.08:09:42.02#ibcon#read 3, iclass 38, count 0 2006.175.08:09:42.02#ibcon#about to read 4, iclass 38, count 0 2006.175.08:09:42.02#ibcon#read 4, iclass 38, count 0 2006.175.08:09:42.02#ibcon#about to read 5, iclass 38, count 0 2006.175.08:09:42.02#ibcon#read 5, iclass 38, count 0 2006.175.08:09:42.02#ibcon#about to read 6, iclass 38, count 0 2006.175.08:09:42.02#ibcon#read 6, iclass 38, count 0 2006.175.08:09:42.02#ibcon#end of sib2, iclass 38, count 0 2006.175.08:09:42.02#ibcon#*after write, iclass 38, count 0 2006.175.08:09:42.02#ibcon#*before return 0, iclass 38, count 0 2006.175.08:09:42.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:42.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:09:42.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:09:42.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:09:42.02$vc4f8/vblo=5,744.99 2006.175.08:09:42.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.08:09:42.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.08:09:42.02#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:42.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:42.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:42.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:42.02#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:09:42.02#ibcon#first serial, iclass 40, count 0 2006.175.08:09:42.02#ibcon#enter sib2, iclass 40, count 0 2006.175.08:09:42.02#ibcon#flushed, iclass 40, count 0 2006.175.08:09:42.02#ibcon#about to write, iclass 40, count 0 2006.175.08:09:42.02#ibcon#wrote, iclass 40, count 0 2006.175.08:09:42.02#ibcon#about to read 3, iclass 40, count 0 2006.175.08:09:42.04#ibcon#read 3, iclass 40, count 0 2006.175.08:09:42.04#ibcon#about to read 4, iclass 40, count 0 2006.175.08:09:42.04#ibcon#read 4, iclass 40, count 0 2006.175.08:09:42.04#ibcon#about to read 5, iclass 40, count 0 2006.175.08:09:42.04#ibcon#read 5, iclass 40, count 0 2006.175.08:09:42.04#ibcon#about to read 6, iclass 40, count 0 2006.175.08:09:42.04#ibcon#read 6, iclass 40, count 0 2006.175.08:09:42.04#ibcon#end of sib2, iclass 40, count 0 2006.175.08:09:42.04#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:09:42.04#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:09:42.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:09:42.04#ibcon#*before write, iclass 40, count 0 2006.175.08:09:42.04#ibcon#enter sib2, iclass 40, count 0 2006.175.08:09:42.04#ibcon#flushed, iclass 40, count 0 2006.175.08:09:42.04#ibcon#about to write, iclass 40, count 0 2006.175.08:09:42.04#ibcon#wrote, iclass 40, count 0 2006.175.08:09:42.04#ibcon#about to read 3, iclass 40, count 0 2006.175.08:09:42.08#ibcon#read 3, iclass 40, count 0 2006.175.08:09:42.08#ibcon#about to read 4, iclass 40, count 0 2006.175.08:09:42.08#ibcon#read 4, iclass 40, count 0 2006.175.08:09:42.08#ibcon#about to read 5, iclass 40, count 0 2006.175.08:09:42.08#ibcon#read 5, iclass 40, count 0 2006.175.08:09:42.08#ibcon#about to read 6, iclass 40, count 0 2006.175.08:09:42.08#ibcon#read 6, iclass 40, count 0 2006.175.08:09:42.08#ibcon#end of sib2, iclass 40, count 0 2006.175.08:09:42.08#ibcon#*after write, iclass 40, count 0 2006.175.08:09:42.08#ibcon#*before return 0, iclass 40, count 0 2006.175.08:09:42.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:42.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:09:42.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:09:42.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:09:42.08$vc4f8/vb=5,4 2006.175.08:09:42.08#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.175.08:09:42.08#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.175.08:09:42.08#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:42.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:42.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:42.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:42.14#ibcon#enter wrdev, iclass 4, count 2 2006.175.08:09:42.14#ibcon#first serial, iclass 4, count 2 2006.175.08:09:42.14#ibcon#enter sib2, iclass 4, count 2 2006.175.08:09:42.14#ibcon#flushed, iclass 4, count 2 2006.175.08:09:42.14#ibcon#about to write, iclass 4, count 2 2006.175.08:09:42.14#ibcon#wrote, iclass 4, count 2 2006.175.08:09:42.14#ibcon#about to read 3, iclass 4, count 2 2006.175.08:09:42.16#ibcon#read 3, iclass 4, count 2 2006.175.08:09:42.16#ibcon#about to read 4, iclass 4, count 2 2006.175.08:09:42.16#ibcon#read 4, iclass 4, count 2 2006.175.08:09:42.16#ibcon#about to read 5, iclass 4, count 2 2006.175.08:09:42.16#ibcon#read 5, iclass 4, count 2 2006.175.08:09:42.16#ibcon#about to read 6, iclass 4, count 2 2006.175.08:09:42.16#ibcon#read 6, iclass 4, count 2 2006.175.08:09:42.16#ibcon#end of sib2, iclass 4, count 2 2006.175.08:09:42.16#ibcon#*mode == 0, iclass 4, count 2 2006.175.08:09:42.16#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.175.08:09:42.16#ibcon#[27=AT05-04\r\n] 2006.175.08:09:42.16#ibcon#*before write, iclass 4, count 2 2006.175.08:09:42.16#ibcon#enter sib2, iclass 4, count 2 2006.175.08:09:42.16#ibcon#flushed, iclass 4, count 2 2006.175.08:09:42.16#ibcon#about to write, iclass 4, count 2 2006.175.08:09:42.16#ibcon#wrote, iclass 4, count 2 2006.175.08:09:42.16#ibcon#about to read 3, iclass 4, count 2 2006.175.08:09:42.19#ibcon#read 3, iclass 4, count 2 2006.175.08:09:42.19#ibcon#about to read 4, iclass 4, count 2 2006.175.08:09:42.19#ibcon#read 4, iclass 4, count 2 2006.175.08:09:42.19#ibcon#about to read 5, iclass 4, count 2 2006.175.08:09:42.19#ibcon#read 5, iclass 4, count 2 2006.175.08:09:42.19#ibcon#about to read 6, iclass 4, count 2 2006.175.08:09:42.19#ibcon#read 6, iclass 4, count 2 2006.175.08:09:42.19#ibcon#end of sib2, iclass 4, count 2 2006.175.08:09:42.19#ibcon#*after write, iclass 4, count 2 2006.175.08:09:42.19#ibcon#*before return 0, iclass 4, count 2 2006.175.08:09:42.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:42.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:09:42.19#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.175.08:09:42.19#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:42.19#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:42.31#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:42.31#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:42.31#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:09:42.31#ibcon#first serial, iclass 4, count 0 2006.175.08:09:42.31#ibcon#enter sib2, iclass 4, count 0 2006.175.08:09:42.31#ibcon#flushed, iclass 4, count 0 2006.175.08:09:42.31#ibcon#about to write, iclass 4, count 0 2006.175.08:09:42.31#ibcon#wrote, iclass 4, count 0 2006.175.08:09:42.31#ibcon#about to read 3, iclass 4, count 0 2006.175.08:09:42.33#ibcon#read 3, iclass 4, count 0 2006.175.08:09:42.33#ibcon#about to read 4, iclass 4, count 0 2006.175.08:09:42.33#ibcon#read 4, iclass 4, count 0 2006.175.08:09:42.33#ibcon#about to read 5, iclass 4, count 0 2006.175.08:09:42.33#ibcon#read 5, iclass 4, count 0 2006.175.08:09:42.33#ibcon#about to read 6, iclass 4, count 0 2006.175.08:09:42.33#ibcon#read 6, iclass 4, count 0 2006.175.08:09:42.33#ibcon#end of sib2, iclass 4, count 0 2006.175.08:09:42.33#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:09:42.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:09:42.33#ibcon#[27=USB\r\n] 2006.175.08:09:42.33#ibcon#*before write, iclass 4, count 0 2006.175.08:09:42.33#ibcon#enter sib2, iclass 4, count 0 2006.175.08:09:42.33#ibcon#flushed, iclass 4, count 0 2006.175.08:09:42.33#ibcon#about to write, iclass 4, count 0 2006.175.08:09:42.33#ibcon#wrote, iclass 4, count 0 2006.175.08:09:42.33#ibcon#about to read 3, iclass 4, count 0 2006.175.08:09:42.36#ibcon#read 3, iclass 4, count 0 2006.175.08:09:42.36#ibcon#about to read 4, iclass 4, count 0 2006.175.08:09:42.36#ibcon#read 4, iclass 4, count 0 2006.175.08:09:42.36#ibcon#about to read 5, iclass 4, count 0 2006.175.08:09:42.36#ibcon#read 5, iclass 4, count 0 2006.175.08:09:42.36#ibcon#about to read 6, iclass 4, count 0 2006.175.08:09:42.36#ibcon#read 6, iclass 4, count 0 2006.175.08:09:42.36#ibcon#end of sib2, iclass 4, count 0 2006.175.08:09:42.36#ibcon#*after write, iclass 4, count 0 2006.175.08:09:42.36#ibcon#*before return 0, iclass 4, count 0 2006.175.08:09:42.36#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:42.36#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:09:42.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:09:42.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:09:42.36$vc4f8/vblo=6,752.99 2006.175.08:09:42.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.175.08:09:42.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.175.08:09:42.36#ibcon#ireg 17 cls_cnt 0 2006.175.08:09:42.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:09:42.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:09:42.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:09:42.36#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:09:42.36#ibcon#first serial, iclass 6, count 0 2006.175.08:09:42.36#ibcon#enter sib2, iclass 6, count 0 2006.175.08:09:42.36#ibcon#flushed, iclass 6, count 0 2006.175.08:09:42.36#ibcon#about to write, iclass 6, count 0 2006.175.08:09:42.36#ibcon#wrote, iclass 6, count 0 2006.175.08:09:42.36#ibcon#about to read 3, iclass 6, count 0 2006.175.08:09:42.38#ibcon#read 3, iclass 6, count 0 2006.175.08:09:42.38#ibcon#about to read 4, iclass 6, count 0 2006.175.08:09:42.38#ibcon#read 4, iclass 6, count 0 2006.175.08:09:42.38#ibcon#about to read 5, iclass 6, count 0 2006.175.08:09:42.38#ibcon#read 5, iclass 6, count 0 2006.175.08:09:42.38#ibcon#about to read 6, iclass 6, count 0 2006.175.08:09:42.38#ibcon#read 6, iclass 6, count 0 2006.175.08:09:42.38#ibcon#end of sib2, iclass 6, count 0 2006.175.08:09:42.38#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:09:42.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:09:42.38#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:09:42.38#ibcon#*before write, iclass 6, count 0 2006.175.08:09:42.38#ibcon#enter sib2, iclass 6, count 0 2006.175.08:09:42.38#ibcon#flushed, iclass 6, count 0 2006.175.08:09:42.38#ibcon#about to write, iclass 6, count 0 2006.175.08:09:42.38#ibcon#wrote, iclass 6, count 0 2006.175.08:09:42.38#ibcon#about to read 3, iclass 6, count 0 2006.175.08:09:42.42#ibcon#read 3, iclass 6, count 0 2006.175.08:09:42.42#ibcon#about to read 4, iclass 6, count 0 2006.175.08:09:42.42#ibcon#read 4, iclass 6, count 0 2006.175.08:09:42.42#ibcon#about to read 5, iclass 6, count 0 2006.175.08:09:42.42#ibcon#read 5, iclass 6, count 0 2006.175.08:09:42.42#ibcon#about to read 6, iclass 6, count 0 2006.175.08:09:42.42#ibcon#read 6, iclass 6, count 0 2006.175.08:09:42.42#ibcon#end of sib2, iclass 6, count 0 2006.175.08:09:42.42#ibcon#*after write, iclass 6, count 0 2006.175.08:09:42.42#ibcon#*before return 0, iclass 6, count 0 2006.175.08:09:42.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:09:42.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:09:42.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:09:42.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:09:42.42$vc4f8/vb=6,4 2006.175.08:09:42.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.175.08:09:42.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.175.08:09:42.42#ibcon#ireg 11 cls_cnt 2 2006.175.08:09:42.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:09:42.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:09:42.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:09:42.48#ibcon#enter wrdev, iclass 10, count 2 2006.175.08:09:42.48#ibcon#first serial, iclass 10, count 2 2006.175.08:09:42.48#ibcon#enter sib2, iclass 10, count 2 2006.175.08:09:42.48#ibcon#flushed, iclass 10, count 2 2006.175.08:09:42.48#ibcon#about to write, iclass 10, count 2 2006.175.08:09:42.48#ibcon#wrote, iclass 10, count 2 2006.175.08:09:42.48#ibcon#about to read 3, iclass 10, count 2 2006.175.08:09:42.50#ibcon#read 3, iclass 10, count 2 2006.175.08:09:42.50#ibcon#about to read 4, iclass 10, count 2 2006.175.08:09:42.50#ibcon#read 4, iclass 10, count 2 2006.175.08:09:42.50#ibcon#about to read 5, iclass 10, count 2 2006.175.08:09:42.50#ibcon#read 5, iclass 10, count 2 2006.175.08:09:42.50#ibcon#about to read 6, iclass 10, count 2 2006.175.08:09:42.50#ibcon#read 6, iclass 10, count 2 2006.175.08:09:42.50#ibcon#end of sib2, iclass 10, count 2 2006.175.08:09:42.50#ibcon#*mode == 0, iclass 10, count 2 2006.175.08:09:42.50#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.175.08:09:42.50#ibcon#[27=AT06-04\r\n] 2006.175.08:09:42.50#ibcon#*before write, iclass 10, count 2 2006.175.08:09:42.50#ibcon#enter sib2, iclass 10, count 2 2006.175.08:09:42.50#ibcon#flushed, iclass 10, count 2 2006.175.08:09:42.50#ibcon#about to write, iclass 10, count 2 2006.175.08:09:42.50#ibcon#wrote, iclass 10, count 2 2006.175.08:09:42.50#ibcon#about to read 3, iclass 10, count 2 2006.175.08:09:42.53#ibcon#read 3, iclass 10, count 2 2006.175.08:09:42.53#ibcon#about to read 4, iclass 10, count 2 2006.175.08:09:42.53#ibcon#read 4, iclass 10, count 2 2006.175.08:09:42.53#ibcon#about to read 5, iclass 10, count 2 2006.175.08:09:42.53#ibcon#read 5, iclass 10, count 2 2006.175.08:09:42.53#ibcon#about to read 6, iclass 10, count 2 2006.175.08:09:42.53#ibcon#read 6, iclass 10, count 2 2006.175.08:09:42.53#ibcon#end of sib2, iclass 10, count 2 2006.175.08:09:42.53#ibcon#*after write, iclass 10, count 2 2006.175.08:09:42.53#ibcon#*before return 0, iclass 10, count 2 2006.175.08:09:42.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:09:42.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:09:42.53#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.175.08:09:42.53#ibcon#ireg 7 cls_cnt 0 2006.175.08:09:42.53#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:09:42.65#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:09:42.65#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:09:42.65#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:09:42.65#ibcon#first serial, iclass 10, count 0 2006.175.08:09:42.65#ibcon#enter sib2, iclass 10, count 0 2006.175.08:09:42.65#ibcon#flushed, iclass 10, count 0 2006.175.08:09:42.65#ibcon#about to write, iclass 10, count 0 2006.175.08:09:42.65#ibcon#wrote, iclass 10, count 0 2006.175.08:09:42.65#ibcon#about to read 3, iclass 10, count 0 2006.175.08:09:42.67#ibcon#read 3, iclass 10, count 0 2006.175.08:09:42.67#ibcon#about to read 4, iclass 10, count 0 2006.175.08:09:42.67#ibcon#read 4, iclass 10, count 0 2006.175.08:09:42.67#ibcon#about to read 5, iclass 10, count 0 2006.175.08:09:42.67#ibcon#read 5, iclass 10, count 0 2006.175.08:09:42.67#ibcon#about to read 6, iclass 10, count 0 2006.175.08:09:42.67#ibcon#read 6, iclass 10, count 0 2006.175.08:09:42.67#ibcon#end of sib2, iclass 10, count 0 2006.175.08:09:42.67#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:09:42.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:09:42.67#ibcon#[27=USB\r\n] 2006.175.08:09:42.67#ibcon#*before write, iclass 10, count 0 2006.175.08:09:42.67#ibcon#enter sib2, iclass 10, count 0 2006.175.08:09:42.67#ibcon#flushed, iclass 10, count 0 2006.175.08:09:42.67#ibcon#about to write, iclass 10, count 0 2006.175.08:09:42.67#ibcon#wrote, iclass 10, count 0 2006.175.08:09:42.67#ibcon#about to read 3, iclass 10, count 0 2006.175.08:09:42.70#ibcon#read 3, iclass 10, count 0 2006.175.08:09:42.70#ibcon#about to read 4, iclass 10, count 0 2006.175.08:09:42.70#ibcon#read 4, iclass 10, count 0 2006.175.08:09:42.70#ibcon#about to read 5, iclass 10, count 0 2006.175.08:09:42.70#ibcon#read 5, iclass 10, count 0 2006.175.08:09:42.70#ibcon#about to read 6, iclass 10, count 0 2006.175.08:09:42.70#ibcon#read 6, iclass 10, count 0 2006.175.08:09:42.70#ibcon#end of sib2, iclass 10, count 0 2006.175.08:09:42.70#ibcon#*after write, iclass 10, count 0 2006.175.08:09:42.70#ibcon#*before return 0, iclass 10, count 0 2006.175.08:09:42.70#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:09:42.70#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:09:42.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:09:42.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:09:42.70$vc4f8/vabw=wide 2006.175.08:09:42.70#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.08:09:42.70#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.08:09:42.70#ibcon#ireg 8 cls_cnt 0 2006.175.08:09:42.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:42.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:42.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:42.70#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:09:42.70#ibcon#first serial, iclass 12, count 0 2006.175.08:09:42.70#ibcon#enter sib2, iclass 12, count 0 2006.175.08:09:42.70#ibcon#flushed, iclass 12, count 0 2006.175.08:09:42.70#ibcon#about to write, iclass 12, count 0 2006.175.08:09:42.70#ibcon#wrote, iclass 12, count 0 2006.175.08:09:42.70#ibcon#about to read 3, iclass 12, count 0 2006.175.08:09:42.72#ibcon#read 3, iclass 12, count 0 2006.175.08:09:42.72#ibcon#about to read 4, iclass 12, count 0 2006.175.08:09:42.72#ibcon#read 4, iclass 12, count 0 2006.175.08:09:42.72#ibcon#about to read 5, iclass 12, count 0 2006.175.08:09:42.72#ibcon#read 5, iclass 12, count 0 2006.175.08:09:42.72#ibcon#about to read 6, iclass 12, count 0 2006.175.08:09:42.72#ibcon#read 6, iclass 12, count 0 2006.175.08:09:42.72#ibcon#end of sib2, iclass 12, count 0 2006.175.08:09:42.72#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:09:42.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:09:42.72#ibcon#[25=BW32\r\n] 2006.175.08:09:42.72#ibcon#*before write, iclass 12, count 0 2006.175.08:09:42.72#ibcon#enter sib2, iclass 12, count 0 2006.175.08:09:42.72#ibcon#flushed, iclass 12, count 0 2006.175.08:09:42.72#ibcon#about to write, iclass 12, count 0 2006.175.08:09:42.72#ibcon#wrote, iclass 12, count 0 2006.175.08:09:42.72#ibcon#about to read 3, iclass 12, count 0 2006.175.08:09:42.75#ibcon#read 3, iclass 12, count 0 2006.175.08:09:42.75#ibcon#about to read 4, iclass 12, count 0 2006.175.08:09:42.75#ibcon#read 4, iclass 12, count 0 2006.175.08:09:42.75#ibcon#about to read 5, iclass 12, count 0 2006.175.08:09:42.75#ibcon#read 5, iclass 12, count 0 2006.175.08:09:42.75#ibcon#about to read 6, iclass 12, count 0 2006.175.08:09:42.75#ibcon#read 6, iclass 12, count 0 2006.175.08:09:42.75#ibcon#end of sib2, iclass 12, count 0 2006.175.08:09:42.75#ibcon#*after write, iclass 12, count 0 2006.175.08:09:42.75#ibcon#*before return 0, iclass 12, count 0 2006.175.08:09:42.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:42.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:09:42.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:09:42.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:09:42.75$vc4f8/vbbw=wide 2006.175.08:09:42.75#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.08:09:42.75#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.08:09:42.75#ibcon#ireg 8 cls_cnt 0 2006.175.08:09:42.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:09:42.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:09:42.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:09:42.82#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:09:42.82#ibcon#first serial, iclass 14, count 0 2006.175.08:09:42.82#ibcon#enter sib2, iclass 14, count 0 2006.175.08:09:42.82#ibcon#flushed, iclass 14, count 0 2006.175.08:09:42.82#ibcon#about to write, iclass 14, count 0 2006.175.08:09:42.82#ibcon#wrote, iclass 14, count 0 2006.175.08:09:42.82#ibcon#about to read 3, iclass 14, count 0 2006.175.08:09:42.84#ibcon#read 3, iclass 14, count 0 2006.175.08:09:42.84#ibcon#about to read 4, iclass 14, count 0 2006.175.08:09:42.84#ibcon#read 4, iclass 14, count 0 2006.175.08:09:42.84#ibcon#about to read 5, iclass 14, count 0 2006.175.08:09:42.84#ibcon#read 5, iclass 14, count 0 2006.175.08:09:42.84#ibcon#about to read 6, iclass 14, count 0 2006.175.08:09:42.84#ibcon#read 6, iclass 14, count 0 2006.175.08:09:42.84#ibcon#end of sib2, iclass 14, count 0 2006.175.08:09:42.84#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:09:42.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:09:42.84#ibcon#[27=BW32\r\n] 2006.175.08:09:42.84#ibcon#*before write, iclass 14, count 0 2006.175.08:09:42.84#ibcon#enter sib2, iclass 14, count 0 2006.175.08:09:42.84#ibcon#flushed, iclass 14, count 0 2006.175.08:09:42.84#ibcon#about to write, iclass 14, count 0 2006.175.08:09:42.84#ibcon#wrote, iclass 14, count 0 2006.175.08:09:42.84#ibcon#about to read 3, iclass 14, count 0 2006.175.08:09:42.87#ibcon#read 3, iclass 14, count 0 2006.175.08:09:42.87#ibcon#about to read 4, iclass 14, count 0 2006.175.08:09:42.87#ibcon#read 4, iclass 14, count 0 2006.175.08:09:42.87#ibcon#about to read 5, iclass 14, count 0 2006.175.08:09:42.87#ibcon#read 5, iclass 14, count 0 2006.175.08:09:42.87#ibcon#about to read 6, iclass 14, count 0 2006.175.08:09:42.87#ibcon#read 6, iclass 14, count 0 2006.175.08:09:42.87#ibcon#end of sib2, iclass 14, count 0 2006.175.08:09:42.87#ibcon#*after write, iclass 14, count 0 2006.175.08:09:42.87#ibcon#*before return 0, iclass 14, count 0 2006.175.08:09:42.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:09:42.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:09:42.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:09:42.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:09:42.87$4f8m12a/ifd4f 2006.175.08:09:42.87$ifd4f/lo= 2006.175.08:09:42.87$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:09:42.87$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:09:42.87$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:09:42.87$ifd4f/patch= 2006.175.08:09:42.87$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:09:42.87$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:09:42.87$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:09:42.87$4f8m12a/"form=m,16.000,1:2 2006.175.08:09:42.87$4f8m12a/"tpicd 2006.175.08:09:42.87$4f8m12a/echo=off 2006.175.08:09:42.87$4f8m12a/xlog=off 2006.175.08:09:42.87:!2006.175.08:10:10 2006.175.08:09:53.14#trakl#Source acquired 2006.175.08:09:55.14#flagr#flagr/antenna,acquired 2006.175.08:10:10.00:preob 2006.175.08:10:11.14/onsource/TRACKING 2006.175.08:10:11.14:!2006.175.08:10:20 2006.175.08:10:20.00:data_valid=on 2006.175.08:10:20.00:midob 2006.175.08:10:20.14/onsource/TRACKING 2006.175.08:10:20.14/wx/25.80,1007.3,69 2006.175.08:10:20.33/cable/+6.4790E-03 2006.175.08:10:21.42/va/01,08,usb,yes,28,30 2006.175.08:10:21.42/va/02,07,usb,yes,29,30 2006.175.08:10:21.42/va/03,06,usb,yes,30,30 2006.175.08:10:21.42/va/04,07,usb,yes,29,32 2006.175.08:10:21.42/va/05,07,usb,yes,30,31 2006.175.08:10:21.42/va/06,06,usb,yes,29,29 2006.175.08:10:21.42/va/07,06,usb,yes,29,29 2006.175.08:10:21.42/va/08,06,usb,yes,31,31 2006.175.08:10:21.65/valo/01,532.99,yes,locked 2006.175.08:10:21.65/valo/02,572.99,yes,locked 2006.175.08:10:21.65/valo/03,672.99,yes,locked 2006.175.08:10:21.65/valo/04,832.99,yes,locked 2006.175.08:10:21.65/valo/05,652.99,yes,locked 2006.175.08:10:21.65/valo/06,772.99,yes,locked 2006.175.08:10:21.65/valo/07,832.99,yes,locked 2006.175.08:10:21.65/valo/08,852.99,yes,locked 2006.175.08:10:22.74/vb/01,04,usb,yes,29,28 2006.175.08:10:22.74/vb/02,04,usb,yes,31,32 2006.175.08:10:22.74/vb/03,04,usb,yes,27,31 2006.175.08:10:22.74/vb/04,04,usb,yes,28,28 2006.175.08:10:22.74/vb/05,04,usb,yes,27,30 2006.175.08:10:22.74/vb/06,04,usb,yes,28,30 2006.175.08:10:22.74/vb/07,04,usb,yes,29,29 2006.175.08:10:22.74/vb/08,04,usb,yes,27,30 2006.175.08:10:22.98/vblo/01,632.99,yes,locked 2006.175.08:10:22.98/vblo/02,640.99,yes,locked 2006.175.08:10:22.98/vblo/03,656.99,yes,locked 2006.175.08:10:22.98/vblo/04,712.99,yes,locked 2006.175.08:10:22.98/vblo/05,744.99,yes,locked 2006.175.08:10:22.98/vblo/06,752.99,yes,locked 2006.175.08:10:22.98/vblo/07,734.99,yes,locked 2006.175.08:10:22.98/vblo/08,744.99,yes,locked 2006.175.08:10:23.13/vabw/8 2006.175.08:10:23.28/vbbw/8 2006.175.08:10:23.44/xfe/off,on,15.0 2006.175.08:10:23.82/ifatt/23,28,28,28 2006.175.08:10:24.07/fmout-gps/S +3.81E-07 2006.175.08:10:24.11:!2006.175.08:11:20 2006.175.08:11:20.01:data_valid=off 2006.175.08:11:20.02:postob 2006.175.08:11:20.20/cable/+6.4785E-03 2006.175.08:11:20.21/wx/25.79,1007.3,70 2006.175.08:11:21.07/fmout-gps/S +3.80E-07 2006.175.08:11:21.08:scan_name=175-0812,k06175,60 2006.175.08:11:21.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.175.08:11:21.14#flagr#flagr/antenna,new-source 2006.175.08:11:22.14:checkk5 2006.175.08:11:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:11:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:11:23.30/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:11:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:11:24.04/chk_obsdata//k5ts1/T1750810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.175.08:11:24.41/chk_obsdata//k5ts2/T1750810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.175.08:11:24.80/chk_obsdata//k5ts3/T1750810??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.175.08:11:25.18/chk_obsdata//k5ts4/T1750810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.175.08:11:25.88/k5log//k5ts1_log_newline 2006.175.08:11:26.58/k5log//k5ts2_log_newline 2006.175.08:11:27.27/k5log//k5ts3_log_newline 2006.175.08:11:27.96/k5log//k5ts4_log_newline 2006.175.08:11:27.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:11:27.99:4f8m12a=2 2006.175.08:11:27.99$4f8m12a/echo=on 2006.175.08:11:27.99$4f8m12a/pcalon 2006.175.08:11:27.99$pcalon/"no phase cal control is implemented here 2006.175.08:11:27.99$4f8m12a/"tpicd=stop 2006.175.08:11:27.99$4f8m12a/vc4f8 2006.175.08:11:27.99$vc4f8/valo=1,532.99 2006.175.08:11:27.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.08:11:27.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.08:11:27.99#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:27.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:27.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:27.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:27.99#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:11:27.99#ibcon#first serial, iclass 21, count 0 2006.175.08:11:27.99#ibcon#enter sib2, iclass 21, count 0 2006.175.08:11:27.99#ibcon#flushed, iclass 21, count 0 2006.175.08:11:27.99#ibcon#about to write, iclass 21, count 0 2006.175.08:11:27.99#ibcon#wrote, iclass 21, count 0 2006.175.08:11:27.99#ibcon#about to read 3, iclass 21, count 0 2006.175.08:11:28.04#ibcon#read 3, iclass 21, count 0 2006.175.08:11:28.04#ibcon#about to read 4, iclass 21, count 0 2006.175.08:11:28.04#ibcon#read 4, iclass 21, count 0 2006.175.08:11:28.04#ibcon#about to read 5, iclass 21, count 0 2006.175.08:11:28.04#ibcon#read 5, iclass 21, count 0 2006.175.08:11:28.04#ibcon#about to read 6, iclass 21, count 0 2006.175.08:11:28.04#ibcon#read 6, iclass 21, count 0 2006.175.08:11:28.04#ibcon#end of sib2, iclass 21, count 0 2006.175.08:11:28.04#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:11:28.04#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:11:28.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:11:28.04#ibcon#*before write, iclass 21, count 0 2006.175.08:11:28.04#ibcon#enter sib2, iclass 21, count 0 2006.175.08:11:28.04#ibcon#flushed, iclass 21, count 0 2006.175.08:11:28.04#ibcon#about to write, iclass 21, count 0 2006.175.08:11:28.04#ibcon#wrote, iclass 21, count 0 2006.175.08:11:28.04#ibcon#about to read 3, iclass 21, count 0 2006.175.08:11:28.09#ibcon#read 3, iclass 21, count 0 2006.175.08:11:28.09#ibcon#about to read 4, iclass 21, count 0 2006.175.08:11:28.09#ibcon#read 4, iclass 21, count 0 2006.175.08:11:28.09#ibcon#about to read 5, iclass 21, count 0 2006.175.08:11:28.09#ibcon#read 5, iclass 21, count 0 2006.175.08:11:28.09#ibcon#about to read 6, iclass 21, count 0 2006.175.08:11:28.09#ibcon#read 6, iclass 21, count 0 2006.175.08:11:28.09#ibcon#end of sib2, iclass 21, count 0 2006.175.08:11:28.09#ibcon#*after write, iclass 21, count 0 2006.175.08:11:28.09#ibcon#*before return 0, iclass 21, count 0 2006.175.08:11:28.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:28.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:28.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:11:28.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:11:28.09$vc4f8/va=1,8 2006.175.08:11:28.09#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.08:11:28.09#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.08:11:28.09#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:28.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:28.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:28.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:28.09#ibcon#enter wrdev, iclass 23, count 2 2006.175.08:11:28.09#ibcon#first serial, iclass 23, count 2 2006.175.08:11:28.09#ibcon#enter sib2, iclass 23, count 2 2006.175.08:11:28.09#ibcon#flushed, iclass 23, count 2 2006.175.08:11:28.09#ibcon#about to write, iclass 23, count 2 2006.175.08:11:28.09#ibcon#wrote, iclass 23, count 2 2006.175.08:11:28.09#ibcon#about to read 3, iclass 23, count 2 2006.175.08:11:28.11#ibcon#read 3, iclass 23, count 2 2006.175.08:11:28.11#ibcon#about to read 4, iclass 23, count 2 2006.175.08:11:28.11#ibcon#read 4, iclass 23, count 2 2006.175.08:11:28.11#ibcon#about to read 5, iclass 23, count 2 2006.175.08:11:28.11#ibcon#read 5, iclass 23, count 2 2006.175.08:11:28.11#ibcon#about to read 6, iclass 23, count 2 2006.175.08:11:28.11#ibcon#read 6, iclass 23, count 2 2006.175.08:11:28.11#ibcon#end of sib2, iclass 23, count 2 2006.175.08:11:28.11#ibcon#*mode == 0, iclass 23, count 2 2006.175.08:11:28.11#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.08:11:28.11#ibcon#[25=AT01-08\r\n] 2006.175.08:11:28.11#ibcon#*before write, iclass 23, count 2 2006.175.08:11:28.11#ibcon#enter sib2, iclass 23, count 2 2006.175.08:11:28.11#ibcon#flushed, iclass 23, count 2 2006.175.08:11:28.11#ibcon#about to write, iclass 23, count 2 2006.175.08:11:28.11#ibcon#wrote, iclass 23, count 2 2006.175.08:11:28.11#ibcon#about to read 3, iclass 23, count 2 2006.175.08:11:28.14#ibcon#read 3, iclass 23, count 2 2006.175.08:11:28.14#ibcon#about to read 4, iclass 23, count 2 2006.175.08:11:28.14#ibcon#read 4, iclass 23, count 2 2006.175.08:11:28.14#ibcon#about to read 5, iclass 23, count 2 2006.175.08:11:28.14#ibcon#read 5, iclass 23, count 2 2006.175.08:11:28.14#ibcon#about to read 6, iclass 23, count 2 2006.175.08:11:28.14#ibcon#read 6, iclass 23, count 2 2006.175.08:11:28.14#ibcon#end of sib2, iclass 23, count 2 2006.175.08:11:28.14#ibcon#*after write, iclass 23, count 2 2006.175.08:11:28.14#ibcon#*before return 0, iclass 23, count 2 2006.175.08:11:28.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:28.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:28.14#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.08:11:28.14#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:28.14#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:28.26#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:28.26#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:28.26#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:11:28.26#ibcon#first serial, iclass 23, count 0 2006.175.08:11:28.26#ibcon#enter sib2, iclass 23, count 0 2006.175.08:11:28.26#ibcon#flushed, iclass 23, count 0 2006.175.08:11:28.26#ibcon#about to write, iclass 23, count 0 2006.175.08:11:28.26#ibcon#wrote, iclass 23, count 0 2006.175.08:11:28.26#ibcon#about to read 3, iclass 23, count 0 2006.175.08:11:28.28#ibcon#read 3, iclass 23, count 0 2006.175.08:11:28.28#ibcon#about to read 4, iclass 23, count 0 2006.175.08:11:28.28#ibcon#read 4, iclass 23, count 0 2006.175.08:11:28.28#ibcon#about to read 5, iclass 23, count 0 2006.175.08:11:28.28#ibcon#read 5, iclass 23, count 0 2006.175.08:11:28.28#ibcon#about to read 6, iclass 23, count 0 2006.175.08:11:28.28#ibcon#read 6, iclass 23, count 0 2006.175.08:11:28.28#ibcon#end of sib2, iclass 23, count 0 2006.175.08:11:28.28#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:11:28.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:11:28.28#ibcon#[25=USB\r\n] 2006.175.08:11:28.28#ibcon#*before write, iclass 23, count 0 2006.175.08:11:28.28#ibcon#enter sib2, iclass 23, count 0 2006.175.08:11:28.28#ibcon#flushed, iclass 23, count 0 2006.175.08:11:28.28#ibcon#about to write, iclass 23, count 0 2006.175.08:11:28.28#ibcon#wrote, iclass 23, count 0 2006.175.08:11:28.28#ibcon#about to read 3, iclass 23, count 0 2006.175.08:11:28.31#ibcon#read 3, iclass 23, count 0 2006.175.08:11:28.31#ibcon#about to read 4, iclass 23, count 0 2006.175.08:11:28.31#ibcon#read 4, iclass 23, count 0 2006.175.08:11:28.31#ibcon#about to read 5, iclass 23, count 0 2006.175.08:11:28.31#ibcon#read 5, iclass 23, count 0 2006.175.08:11:28.31#ibcon#about to read 6, iclass 23, count 0 2006.175.08:11:28.31#ibcon#read 6, iclass 23, count 0 2006.175.08:11:28.31#ibcon#end of sib2, iclass 23, count 0 2006.175.08:11:28.31#ibcon#*after write, iclass 23, count 0 2006.175.08:11:28.31#ibcon#*before return 0, iclass 23, count 0 2006.175.08:11:28.31#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:28.31#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:28.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:11:28.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:11:28.31$vc4f8/valo=2,572.99 2006.175.08:11:28.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.08:11:28.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.08:11:28.31#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:28.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:28.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:28.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:28.31#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:11:28.31#ibcon#first serial, iclass 25, count 0 2006.175.08:11:28.31#ibcon#enter sib2, iclass 25, count 0 2006.175.08:11:28.31#ibcon#flushed, iclass 25, count 0 2006.175.08:11:28.31#ibcon#about to write, iclass 25, count 0 2006.175.08:11:28.31#ibcon#wrote, iclass 25, count 0 2006.175.08:11:28.31#ibcon#about to read 3, iclass 25, count 0 2006.175.08:11:28.33#ibcon#read 3, iclass 25, count 0 2006.175.08:11:28.33#ibcon#about to read 4, iclass 25, count 0 2006.175.08:11:28.33#ibcon#read 4, iclass 25, count 0 2006.175.08:11:28.33#ibcon#about to read 5, iclass 25, count 0 2006.175.08:11:28.33#ibcon#read 5, iclass 25, count 0 2006.175.08:11:28.33#ibcon#about to read 6, iclass 25, count 0 2006.175.08:11:28.33#ibcon#read 6, iclass 25, count 0 2006.175.08:11:28.33#ibcon#end of sib2, iclass 25, count 0 2006.175.08:11:28.33#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:11:28.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:11:28.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:11:28.33#ibcon#*before write, iclass 25, count 0 2006.175.08:11:28.33#ibcon#enter sib2, iclass 25, count 0 2006.175.08:11:28.33#ibcon#flushed, iclass 25, count 0 2006.175.08:11:28.33#ibcon#about to write, iclass 25, count 0 2006.175.08:11:28.33#ibcon#wrote, iclass 25, count 0 2006.175.08:11:28.33#ibcon#about to read 3, iclass 25, count 0 2006.175.08:11:28.37#ibcon#read 3, iclass 25, count 0 2006.175.08:11:28.37#ibcon#about to read 4, iclass 25, count 0 2006.175.08:11:28.37#ibcon#read 4, iclass 25, count 0 2006.175.08:11:28.37#ibcon#about to read 5, iclass 25, count 0 2006.175.08:11:28.37#ibcon#read 5, iclass 25, count 0 2006.175.08:11:28.37#ibcon#about to read 6, iclass 25, count 0 2006.175.08:11:28.37#ibcon#read 6, iclass 25, count 0 2006.175.08:11:28.37#ibcon#end of sib2, iclass 25, count 0 2006.175.08:11:28.37#ibcon#*after write, iclass 25, count 0 2006.175.08:11:28.37#ibcon#*before return 0, iclass 25, count 0 2006.175.08:11:28.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:28.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:28.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:11:28.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:11:28.37$vc4f8/va=2,7 2006.175.08:11:28.37#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.08:11:28.37#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.08:11:28.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:28.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:28.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:28.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:28.43#ibcon#enter wrdev, iclass 27, count 2 2006.175.08:11:28.43#ibcon#first serial, iclass 27, count 2 2006.175.08:11:28.43#ibcon#enter sib2, iclass 27, count 2 2006.175.08:11:28.43#ibcon#flushed, iclass 27, count 2 2006.175.08:11:28.43#ibcon#about to write, iclass 27, count 2 2006.175.08:11:28.43#ibcon#wrote, iclass 27, count 2 2006.175.08:11:28.43#ibcon#about to read 3, iclass 27, count 2 2006.175.08:11:28.45#ibcon#read 3, iclass 27, count 2 2006.175.08:11:28.45#ibcon#about to read 4, iclass 27, count 2 2006.175.08:11:28.45#ibcon#read 4, iclass 27, count 2 2006.175.08:11:28.45#ibcon#about to read 5, iclass 27, count 2 2006.175.08:11:28.45#ibcon#read 5, iclass 27, count 2 2006.175.08:11:28.45#ibcon#about to read 6, iclass 27, count 2 2006.175.08:11:28.45#ibcon#read 6, iclass 27, count 2 2006.175.08:11:28.45#ibcon#end of sib2, iclass 27, count 2 2006.175.08:11:28.45#ibcon#*mode == 0, iclass 27, count 2 2006.175.08:11:28.45#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.08:11:28.45#ibcon#[25=AT02-07\r\n] 2006.175.08:11:28.45#ibcon#*before write, iclass 27, count 2 2006.175.08:11:28.45#ibcon#enter sib2, iclass 27, count 2 2006.175.08:11:28.45#ibcon#flushed, iclass 27, count 2 2006.175.08:11:28.45#ibcon#about to write, iclass 27, count 2 2006.175.08:11:28.45#ibcon#wrote, iclass 27, count 2 2006.175.08:11:28.45#ibcon#about to read 3, iclass 27, count 2 2006.175.08:11:28.48#ibcon#read 3, iclass 27, count 2 2006.175.08:11:28.48#ibcon#about to read 4, iclass 27, count 2 2006.175.08:11:28.48#ibcon#read 4, iclass 27, count 2 2006.175.08:11:28.48#ibcon#about to read 5, iclass 27, count 2 2006.175.08:11:28.48#ibcon#read 5, iclass 27, count 2 2006.175.08:11:28.48#ibcon#about to read 6, iclass 27, count 2 2006.175.08:11:28.48#ibcon#read 6, iclass 27, count 2 2006.175.08:11:28.48#ibcon#end of sib2, iclass 27, count 2 2006.175.08:11:28.48#ibcon#*after write, iclass 27, count 2 2006.175.08:11:28.48#ibcon#*before return 0, iclass 27, count 2 2006.175.08:11:28.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:28.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:28.48#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.08:11:28.48#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:28.48#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:28.60#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:28.60#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:28.60#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:11:28.60#ibcon#first serial, iclass 27, count 0 2006.175.08:11:28.60#ibcon#enter sib2, iclass 27, count 0 2006.175.08:11:28.60#ibcon#flushed, iclass 27, count 0 2006.175.08:11:28.60#ibcon#about to write, iclass 27, count 0 2006.175.08:11:28.60#ibcon#wrote, iclass 27, count 0 2006.175.08:11:28.60#ibcon#about to read 3, iclass 27, count 0 2006.175.08:11:28.62#ibcon#read 3, iclass 27, count 0 2006.175.08:11:28.62#ibcon#about to read 4, iclass 27, count 0 2006.175.08:11:28.62#ibcon#read 4, iclass 27, count 0 2006.175.08:11:28.62#ibcon#about to read 5, iclass 27, count 0 2006.175.08:11:28.62#ibcon#read 5, iclass 27, count 0 2006.175.08:11:28.62#ibcon#about to read 6, iclass 27, count 0 2006.175.08:11:28.62#ibcon#read 6, iclass 27, count 0 2006.175.08:11:28.62#ibcon#end of sib2, iclass 27, count 0 2006.175.08:11:28.62#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:11:28.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:11:28.62#ibcon#[25=USB\r\n] 2006.175.08:11:28.62#ibcon#*before write, iclass 27, count 0 2006.175.08:11:28.62#ibcon#enter sib2, iclass 27, count 0 2006.175.08:11:28.62#ibcon#flushed, iclass 27, count 0 2006.175.08:11:28.62#ibcon#about to write, iclass 27, count 0 2006.175.08:11:28.62#ibcon#wrote, iclass 27, count 0 2006.175.08:11:28.62#ibcon#about to read 3, iclass 27, count 0 2006.175.08:11:28.65#ibcon#read 3, iclass 27, count 0 2006.175.08:11:28.65#ibcon#about to read 4, iclass 27, count 0 2006.175.08:11:28.65#ibcon#read 4, iclass 27, count 0 2006.175.08:11:28.65#ibcon#about to read 5, iclass 27, count 0 2006.175.08:11:28.65#ibcon#read 5, iclass 27, count 0 2006.175.08:11:28.65#ibcon#about to read 6, iclass 27, count 0 2006.175.08:11:28.65#ibcon#read 6, iclass 27, count 0 2006.175.08:11:28.65#ibcon#end of sib2, iclass 27, count 0 2006.175.08:11:28.65#ibcon#*after write, iclass 27, count 0 2006.175.08:11:28.65#ibcon#*before return 0, iclass 27, count 0 2006.175.08:11:28.65#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:28.65#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:28.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:11:28.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:11:28.65$vc4f8/valo=3,672.99 2006.175.08:11:28.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.08:11:28.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.08:11:28.65#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:28.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:11:28.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:11:28.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:11:28.65#ibcon#enter wrdev, iclass 29, count 0 2006.175.08:11:28.65#ibcon#first serial, iclass 29, count 0 2006.175.08:11:28.65#ibcon#enter sib2, iclass 29, count 0 2006.175.08:11:28.65#ibcon#flushed, iclass 29, count 0 2006.175.08:11:28.65#ibcon#about to write, iclass 29, count 0 2006.175.08:11:28.65#ibcon#wrote, iclass 29, count 0 2006.175.08:11:28.65#ibcon#about to read 3, iclass 29, count 0 2006.175.08:11:28.67#ibcon#read 3, iclass 29, count 0 2006.175.08:11:28.67#ibcon#about to read 4, iclass 29, count 0 2006.175.08:11:28.67#ibcon#read 4, iclass 29, count 0 2006.175.08:11:28.67#ibcon#about to read 5, iclass 29, count 0 2006.175.08:11:28.67#ibcon#read 5, iclass 29, count 0 2006.175.08:11:28.67#ibcon#about to read 6, iclass 29, count 0 2006.175.08:11:28.67#ibcon#read 6, iclass 29, count 0 2006.175.08:11:28.67#ibcon#end of sib2, iclass 29, count 0 2006.175.08:11:28.67#ibcon#*mode == 0, iclass 29, count 0 2006.175.08:11:28.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.08:11:28.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:11:28.67#ibcon#*before write, iclass 29, count 0 2006.175.08:11:28.67#ibcon#enter sib2, iclass 29, count 0 2006.175.08:11:28.67#ibcon#flushed, iclass 29, count 0 2006.175.08:11:28.67#ibcon#about to write, iclass 29, count 0 2006.175.08:11:28.67#ibcon#wrote, iclass 29, count 0 2006.175.08:11:28.67#ibcon#about to read 3, iclass 29, count 0 2006.175.08:11:28.71#ibcon#read 3, iclass 29, count 0 2006.175.08:11:28.71#ibcon#about to read 4, iclass 29, count 0 2006.175.08:11:28.71#ibcon#read 4, iclass 29, count 0 2006.175.08:11:28.71#ibcon#about to read 5, iclass 29, count 0 2006.175.08:11:28.71#ibcon#read 5, iclass 29, count 0 2006.175.08:11:28.71#ibcon#about to read 6, iclass 29, count 0 2006.175.08:11:28.71#ibcon#read 6, iclass 29, count 0 2006.175.08:11:28.71#ibcon#end of sib2, iclass 29, count 0 2006.175.08:11:28.71#ibcon#*after write, iclass 29, count 0 2006.175.08:11:28.71#ibcon#*before return 0, iclass 29, count 0 2006.175.08:11:28.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:11:28.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:11:28.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.08:11:28.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.08:11:28.71$vc4f8/va=3,6 2006.175.08:11:28.71#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.08:11:28.71#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.08:11:28.71#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:28.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:11:28.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:11:28.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:11:28.77#ibcon#enter wrdev, iclass 31, count 2 2006.175.08:11:28.77#ibcon#first serial, iclass 31, count 2 2006.175.08:11:28.77#ibcon#enter sib2, iclass 31, count 2 2006.175.08:11:28.77#ibcon#flushed, iclass 31, count 2 2006.175.08:11:28.77#ibcon#about to write, iclass 31, count 2 2006.175.08:11:28.77#ibcon#wrote, iclass 31, count 2 2006.175.08:11:28.77#ibcon#about to read 3, iclass 31, count 2 2006.175.08:11:28.79#ibcon#read 3, iclass 31, count 2 2006.175.08:11:28.79#ibcon#about to read 4, iclass 31, count 2 2006.175.08:11:28.79#ibcon#read 4, iclass 31, count 2 2006.175.08:11:28.79#ibcon#about to read 5, iclass 31, count 2 2006.175.08:11:28.79#ibcon#read 5, iclass 31, count 2 2006.175.08:11:28.79#ibcon#about to read 6, iclass 31, count 2 2006.175.08:11:28.79#ibcon#read 6, iclass 31, count 2 2006.175.08:11:28.79#ibcon#end of sib2, iclass 31, count 2 2006.175.08:11:28.79#ibcon#*mode == 0, iclass 31, count 2 2006.175.08:11:28.79#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.08:11:28.79#ibcon#[25=AT03-06\r\n] 2006.175.08:11:28.79#ibcon#*before write, iclass 31, count 2 2006.175.08:11:28.79#ibcon#enter sib2, iclass 31, count 2 2006.175.08:11:28.79#ibcon#flushed, iclass 31, count 2 2006.175.08:11:28.79#ibcon#about to write, iclass 31, count 2 2006.175.08:11:28.79#ibcon#wrote, iclass 31, count 2 2006.175.08:11:28.79#ibcon#about to read 3, iclass 31, count 2 2006.175.08:11:28.82#ibcon#read 3, iclass 31, count 2 2006.175.08:11:28.82#ibcon#about to read 4, iclass 31, count 2 2006.175.08:11:28.82#ibcon#read 4, iclass 31, count 2 2006.175.08:11:28.82#ibcon#about to read 5, iclass 31, count 2 2006.175.08:11:28.82#ibcon#read 5, iclass 31, count 2 2006.175.08:11:28.82#ibcon#about to read 6, iclass 31, count 2 2006.175.08:11:28.82#ibcon#read 6, iclass 31, count 2 2006.175.08:11:28.82#ibcon#end of sib2, iclass 31, count 2 2006.175.08:11:28.82#ibcon#*after write, iclass 31, count 2 2006.175.08:11:28.82#ibcon#*before return 0, iclass 31, count 2 2006.175.08:11:28.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:11:28.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:11:28.82#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.08:11:28.82#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:28.82#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:11:28.94#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:11:28.94#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:11:28.94#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:11:28.94#ibcon#first serial, iclass 31, count 0 2006.175.08:11:28.94#ibcon#enter sib2, iclass 31, count 0 2006.175.08:11:28.94#ibcon#flushed, iclass 31, count 0 2006.175.08:11:28.94#ibcon#about to write, iclass 31, count 0 2006.175.08:11:28.94#ibcon#wrote, iclass 31, count 0 2006.175.08:11:28.94#ibcon#about to read 3, iclass 31, count 0 2006.175.08:11:28.96#ibcon#read 3, iclass 31, count 0 2006.175.08:11:28.96#ibcon#about to read 4, iclass 31, count 0 2006.175.08:11:28.96#ibcon#read 4, iclass 31, count 0 2006.175.08:11:28.96#ibcon#about to read 5, iclass 31, count 0 2006.175.08:11:28.96#ibcon#read 5, iclass 31, count 0 2006.175.08:11:28.96#ibcon#about to read 6, iclass 31, count 0 2006.175.08:11:28.96#ibcon#read 6, iclass 31, count 0 2006.175.08:11:28.96#ibcon#end of sib2, iclass 31, count 0 2006.175.08:11:28.96#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:11:28.96#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:11:28.96#ibcon#[25=USB\r\n] 2006.175.08:11:28.96#ibcon#*before write, iclass 31, count 0 2006.175.08:11:28.96#ibcon#enter sib2, iclass 31, count 0 2006.175.08:11:28.96#ibcon#flushed, iclass 31, count 0 2006.175.08:11:28.96#ibcon#about to write, iclass 31, count 0 2006.175.08:11:28.96#ibcon#wrote, iclass 31, count 0 2006.175.08:11:28.96#ibcon#about to read 3, iclass 31, count 0 2006.175.08:11:28.99#ibcon#read 3, iclass 31, count 0 2006.175.08:11:28.99#ibcon#about to read 4, iclass 31, count 0 2006.175.08:11:28.99#ibcon#read 4, iclass 31, count 0 2006.175.08:11:28.99#ibcon#about to read 5, iclass 31, count 0 2006.175.08:11:28.99#ibcon#read 5, iclass 31, count 0 2006.175.08:11:28.99#ibcon#about to read 6, iclass 31, count 0 2006.175.08:11:28.99#ibcon#read 6, iclass 31, count 0 2006.175.08:11:28.99#ibcon#end of sib2, iclass 31, count 0 2006.175.08:11:28.99#ibcon#*after write, iclass 31, count 0 2006.175.08:11:28.99#ibcon#*before return 0, iclass 31, count 0 2006.175.08:11:28.99#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:11:28.99#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:11:28.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:11:28.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:11:28.99$vc4f8/valo=4,832.99 2006.175.08:11:28.99#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.08:11:28.99#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.08:11:28.99#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:28.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:28.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:28.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:28.99#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:11:28.99#ibcon#first serial, iclass 33, count 0 2006.175.08:11:28.99#ibcon#enter sib2, iclass 33, count 0 2006.175.08:11:28.99#ibcon#flushed, iclass 33, count 0 2006.175.08:11:28.99#ibcon#about to write, iclass 33, count 0 2006.175.08:11:28.99#ibcon#wrote, iclass 33, count 0 2006.175.08:11:28.99#ibcon#about to read 3, iclass 33, count 0 2006.175.08:11:29.01#ibcon#read 3, iclass 33, count 0 2006.175.08:11:29.01#ibcon#about to read 4, iclass 33, count 0 2006.175.08:11:29.01#ibcon#read 4, iclass 33, count 0 2006.175.08:11:29.01#ibcon#about to read 5, iclass 33, count 0 2006.175.08:11:29.01#ibcon#read 5, iclass 33, count 0 2006.175.08:11:29.01#ibcon#about to read 6, iclass 33, count 0 2006.175.08:11:29.01#ibcon#read 6, iclass 33, count 0 2006.175.08:11:29.01#ibcon#end of sib2, iclass 33, count 0 2006.175.08:11:29.01#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:11:29.01#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:11:29.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:11:29.01#ibcon#*before write, iclass 33, count 0 2006.175.08:11:29.01#ibcon#enter sib2, iclass 33, count 0 2006.175.08:11:29.01#ibcon#flushed, iclass 33, count 0 2006.175.08:11:29.01#ibcon#about to write, iclass 33, count 0 2006.175.08:11:29.01#ibcon#wrote, iclass 33, count 0 2006.175.08:11:29.01#ibcon#about to read 3, iclass 33, count 0 2006.175.08:11:29.05#ibcon#read 3, iclass 33, count 0 2006.175.08:11:29.05#ibcon#about to read 4, iclass 33, count 0 2006.175.08:11:29.05#ibcon#read 4, iclass 33, count 0 2006.175.08:11:29.05#ibcon#about to read 5, iclass 33, count 0 2006.175.08:11:29.05#ibcon#read 5, iclass 33, count 0 2006.175.08:11:29.05#ibcon#about to read 6, iclass 33, count 0 2006.175.08:11:29.05#ibcon#read 6, iclass 33, count 0 2006.175.08:11:29.05#ibcon#end of sib2, iclass 33, count 0 2006.175.08:11:29.05#ibcon#*after write, iclass 33, count 0 2006.175.08:11:29.05#ibcon#*before return 0, iclass 33, count 0 2006.175.08:11:29.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:29.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:29.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:11:29.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:11:29.05$vc4f8/va=4,7 2006.175.08:11:29.05#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.175.08:11:29.05#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.175.08:11:29.05#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:29.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:29.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:29.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:29.11#ibcon#enter wrdev, iclass 35, count 2 2006.175.08:11:29.11#ibcon#first serial, iclass 35, count 2 2006.175.08:11:29.11#ibcon#enter sib2, iclass 35, count 2 2006.175.08:11:29.11#ibcon#flushed, iclass 35, count 2 2006.175.08:11:29.11#ibcon#about to write, iclass 35, count 2 2006.175.08:11:29.11#ibcon#wrote, iclass 35, count 2 2006.175.08:11:29.11#ibcon#about to read 3, iclass 35, count 2 2006.175.08:11:29.13#ibcon#read 3, iclass 35, count 2 2006.175.08:11:29.13#ibcon#about to read 4, iclass 35, count 2 2006.175.08:11:29.13#ibcon#read 4, iclass 35, count 2 2006.175.08:11:29.13#ibcon#about to read 5, iclass 35, count 2 2006.175.08:11:29.13#ibcon#read 5, iclass 35, count 2 2006.175.08:11:29.13#ibcon#about to read 6, iclass 35, count 2 2006.175.08:11:29.13#ibcon#read 6, iclass 35, count 2 2006.175.08:11:29.13#ibcon#end of sib2, iclass 35, count 2 2006.175.08:11:29.13#ibcon#*mode == 0, iclass 35, count 2 2006.175.08:11:29.13#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.175.08:11:29.13#ibcon#[25=AT04-07\r\n] 2006.175.08:11:29.13#ibcon#*before write, iclass 35, count 2 2006.175.08:11:29.13#ibcon#enter sib2, iclass 35, count 2 2006.175.08:11:29.13#ibcon#flushed, iclass 35, count 2 2006.175.08:11:29.13#ibcon#about to write, iclass 35, count 2 2006.175.08:11:29.13#ibcon#wrote, iclass 35, count 2 2006.175.08:11:29.13#ibcon#about to read 3, iclass 35, count 2 2006.175.08:11:29.16#ibcon#read 3, iclass 35, count 2 2006.175.08:11:29.16#ibcon#about to read 4, iclass 35, count 2 2006.175.08:11:29.16#ibcon#read 4, iclass 35, count 2 2006.175.08:11:29.16#ibcon#about to read 5, iclass 35, count 2 2006.175.08:11:29.16#ibcon#read 5, iclass 35, count 2 2006.175.08:11:29.16#ibcon#about to read 6, iclass 35, count 2 2006.175.08:11:29.16#ibcon#read 6, iclass 35, count 2 2006.175.08:11:29.16#ibcon#end of sib2, iclass 35, count 2 2006.175.08:11:29.16#ibcon#*after write, iclass 35, count 2 2006.175.08:11:29.16#ibcon#*before return 0, iclass 35, count 2 2006.175.08:11:29.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:29.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:29.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.175.08:11:29.16#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:29.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:29.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:29.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:29.28#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:11:29.28#ibcon#first serial, iclass 35, count 0 2006.175.08:11:29.28#ibcon#enter sib2, iclass 35, count 0 2006.175.08:11:29.28#ibcon#flushed, iclass 35, count 0 2006.175.08:11:29.28#ibcon#about to write, iclass 35, count 0 2006.175.08:11:29.28#ibcon#wrote, iclass 35, count 0 2006.175.08:11:29.28#ibcon#about to read 3, iclass 35, count 0 2006.175.08:11:29.30#ibcon#read 3, iclass 35, count 0 2006.175.08:11:29.30#ibcon#about to read 4, iclass 35, count 0 2006.175.08:11:29.30#ibcon#read 4, iclass 35, count 0 2006.175.08:11:29.30#ibcon#about to read 5, iclass 35, count 0 2006.175.08:11:29.30#ibcon#read 5, iclass 35, count 0 2006.175.08:11:29.30#ibcon#about to read 6, iclass 35, count 0 2006.175.08:11:29.30#ibcon#read 6, iclass 35, count 0 2006.175.08:11:29.30#ibcon#end of sib2, iclass 35, count 0 2006.175.08:11:29.30#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:11:29.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:11:29.30#ibcon#[25=USB\r\n] 2006.175.08:11:29.30#ibcon#*before write, iclass 35, count 0 2006.175.08:11:29.30#ibcon#enter sib2, iclass 35, count 0 2006.175.08:11:29.30#ibcon#flushed, iclass 35, count 0 2006.175.08:11:29.30#ibcon#about to write, iclass 35, count 0 2006.175.08:11:29.30#ibcon#wrote, iclass 35, count 0 2006.175.08:11:29.30#ibcon#about to read 3, iclass 35, count 0 2006.175.08:11:29.33#ibcon#read 3, iclass 35, count 0 2006.175.08:11:29.33#ibcon#about to read 4, iclass 35, count 0 2006.175.08:11:29.33#ibcon#read 4, iclass 35, count 0 2006.175.08:11:29.33#ibcon#about to read 5, iclass 35, count 0 2006.175.08:11:29.33#ibcon#read 5, iclass 35, count 0 2006.175.08:11:29.33#ibcon#about to read 6, iclass 35, count 0 2006.175.08:11:29.33#ibcon#read 6, iclass 35, count 0 2006.175.08:11:29.33#ibcon#end of sib2, iclass 35, count 0 2006.175.08:11:29.33#ibcon#*after write, iclass 35, count 0 2006.175.08:11:29.33#ibcon#*before return 0, iclass 35, count 0 2006.175.08:11:29.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:29.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:29.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:11:29.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:11:29.33$vc4f8/valo=5,652.99 2006.175.08:11:29.33#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.08:11:29.33#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.08:11:29.33#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:29.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:29.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:29.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:29.33#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:11:29.33#ibcon#first serial, iclass 37, count 0 2006.175.08:11:29.33#ibcon#enter sib2, iclass 37, count 0 2006.175.08:11:29.33#ibcon#flushed, iclass 37, count 0 2006.175.08:11:29.33#ibcon#about to write, iclass 37, count 0 2006.175.08:11:29.33#ibcon#wrote, iclass 37, count 0 2006.175.08:11:29.33#ibcon#about to read 3, iclass 37, count 0 2006.175.08:11:29.35#ibcon#read 3, iclass 37, count 0 2006.175.08:11:29.35#ibcon#about to read 4, iclass 37, count 0 2006.175.08:11:29.35#ibcon#read 4, iclass 37, count 0 2006.175.08:11:29.35#ibcon#about to read 5, iclass 37, count 0 2006.175.08:11:29.35#ibcon#read 5, iclass 37, count 0 2006.175.08:11:29.35#ibcon#about to read 6, iclass 37, count 0 2006.175.08:11:29.35#ibcon#read 6, iclass 37, count 0 2006.175.08:11:29.35#ibcon#end of sib2, iclass 37, count 0 2006.175.08:11:29.35#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:11:29.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:11:29.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:11:29.35#ibcon#*before write, iclass 37, count 0 2006.175.08:11:29.35#ibcon#enter sib2, iclass 37, count 0 2006.175.08:11:29.35#ibcon#flushed, iclass 37, count 0 2006.175.08:11:29.35#ibcon#about to write, iclass 37, count 0 2006.175.08:11:29.35#ibcon#wrote, iclass 37, count 0 2006.175.08:11:29.35#ibcon#about to read 3, iclass 37, count 0 2006.175.08:11:29.39#ibcon#read 3, iclass 37, count 0 2006.175.08:11:29.39#ibcon#about to read 4, iclass 37, count 0 2006.175.08:11:29.39#ibcon#read 4, iclass 37, count 0 2006.175.08:11:29.39#ibcon#about to read 5, iclass 37, count 0 2006.175.08:11:29.39#ibcon#read 5, iclass 37, count 0 2006.175.08:11:29.39#ibcon#about to read 6, iclass 37, count 0 2006.175.08:11:29.39#ibcon#read 6, iclass 37, count 0 2006.175.08:11:29.39#ibcon#end of sib2, iclass 37, count 0 2006.175.08:11:29.39#ibcon#*after write, iclass 37, count 0 2006.175.08:11:29.39#ibcon#*before return 0, iclass 37, count 0 2006.175.08:11:29.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:29.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:29.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:11:29.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:11:29.39$vc4f8/va=5,7 2006.175.08:11:29.39#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.175.08:11:29.39#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.175.08:11:29.39#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:29.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:29.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:29.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:29.45#ibcon#enter wrdev, iclass 39, count 2 2006.175.08:11:29.45#ibcon#first serial, iclass 39, count 2 2006.175.08:11:29.45#ibcon#enter sib2, iclass 39, count 2 2006.175.08:11:29.45#ibcon#flushed, iclass 39, count 2 2006.175.08:11:29.45#ibcon#about to write, iclass 39, count 2 2006.175.08:11:29.45#ibcon#wrote, iclass 39, count 2 2006.175.08:11:29.45#ibcon#about to read 3, iclass 39, count 2 2006.175.08:11:29.47#ibcon#read 3, iclass 39, count 2 2006.175.08:11:29.47#ibcon#about to read 4, iclass 39, count 2 2006.175.08:11:29.47#ibcon#read 4, iclass 39, count 2 2006.175.08:11:29.47#ibcon#about to read 5, iclass 39, count 2 2006.175.08:11:29.47#ibcon#read 5, iclass 39, count 2 2006.175.08:11:29.47#ibcon#about to read 6, iclass 39, count 2 2006.175.08:11:29.47#ibcon#read 6, iclass 39, count 2 2006.175.08:11:29.47#ibcon#end of sib2, iclass 39, count 2 2006.175.08:11:29.47#ibcon#*mode == 0, iclass 39, count 2 2006.175.08:11:29.47#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.175.08:11:29.47#ibcon#[25=AT05-07\r\n] 2006.175.08:11:29.47#ibcon#*before write, iclass 39, count 2 2006.175.08:11:29.47#ibcon#enter sib2, iclass 39, count 2 2006.175.08:11:29.47#ibcon#flushed, iclass 39, count 2 2006.175.08:11:29.47#ibcon#about to write, iclass 39, count 2 2006.175.08:11:29.47#ibcon#wrote, iclass 39, count 2 2006.175.08:11:29.47#ibcon#about to read 3, iclass 39, count 2 2006.175.08:11:29.50#ibcon#read 3, iclass 39, count 2 2006.175.08:11:29.50#ibcon#about to read 4, iclass 39, count 2 2006.175.08:11:29.50#ibcon#read 4, iclass 39, count 2 2006.175.08:11:29.50#ibcon#about to read 5, iclass 39, count 2 2006.175.08:11:29.50#ibcon#read 5, iclass 39, count 2 2006.175.08:11:29.50#ibcon#about to read 6, iclass 39, count 2 2006.175.08:11:29.50#ibcon#read 6, iclass 39, count 2 2006.175.08:11:29.50#ibcon#end of sib2, iclass 39, count 2 2006.175.08:11:29.50#ibcon#*after write, iclass 39, count 2 2006.175.08:11:29.50#ibcon#*before return 0, iclass 39, count 2 2006.175.08:11:29.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:29.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:29.50#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.175.08:11:29.50#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:29.50#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:29.62#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:29.62#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:29.62#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:11:29.62#ibcon#first serial, iclass 39, count 0 2006.175.08:11:29.62#ibcon#enter sib2, iclass 39, count 0 2006.175.08:11:29.62#ibcon#flushed, iclass 39, count 0 2006.175.08:11:29.62#ibcon#about to write, iclass 39, count 0 2006.175.08:11:29.62#ibcon#wrote, iclass 39, count 0 2006.175.08:11:29.62#ibcon#about to read 3, iclass 39, count 0 2006.175.08:11:29.64#ibcon#read 3, iclass 39, count 0 2006.175.08:11:29.64#ibcon#about to read 4, iclass 39, count 0 2006.175.08:11:29.64#ibcon#read 4, iclass 39, count 0 2006.175.08:11:29.64#ibcon#about to read 5, iclass 39, count 0 2006.175.08:11:29.64#ibcon#read 5, iclass 39, count 0 2006.175.08:11:29.64#ibcon#about to read 6, iclass 39, count 0 2006.175.08:11:29.64#ibcon#read 6, iclass 39, count 0 2006.175.08:11:29.64#ibcon#end of sib2, iclass 39, count 0 2006.175.08:11:29.64#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:11:29.64#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:11:29.64#ibcon#[25=USB\r\n] 2006.175.08:11:29.64#ibcon#*before write, iclass 39, count 0 2006.175.08:11:29.64#ibcon#enter sib2, iclass 39, count 0 2006.175.08:11:29.64#ibcon#flushed, iclass 39, count 0 2006.175.08:11:29.64#ibcon#about to write, iclass 39, count 0 2006.175.08:11:29.64#ibcon#wrote, iclass 39, count 0 2006.175.08:11:29.64#ibcon#about to read 3, iclass 39, count 0 2006.175.08:11:29.67#ibcon#read 3, iclass 39, count 0 2006.175.08:11:29.67#ibcon#about to read 4, iclass 39, count 0 2006.175.08:11:29.67#ibcon#read 4, iclass 39, count 0 2006.175.08:11:29.67#ibcon#about to read 5, iclass 39, count 0 2006.175.08:11:29.67#ibcon#read 5, iclass 39, count 0 2006.175.08:11:29.67#ibcon#about to read 6, iclass 39, count 0 2006.175.08:11:29.67#ibcon#read 6, iclass 39, count 0 2006.175.08:11:29.67#ibcon#end of sib2, iclass 39, count 0 2006.175.08:11:29.67#ibcon#*after write, iclass 39, count 0 2006.175.08:11:29.67#ibcon#*before return 0, iclass 39, count 0 2006.175.08:11:29.67#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:29.67#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:29.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:11:29.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:11:29.67$vc4f8/valo=6,772.99 2006.175.08:11:29.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.08:11:29.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.08:11:29.67#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:29.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:29.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:29.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:29.67#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:11:29.67#ibcon#first serial, iclass 3, count 0 2006.175.08:11:29.67#ibcon#enter sib2, iclass 3, count 0 2006.175.08:11:29.67#ibcon#flushed, iclass 3, count 0 2006.175.08:11:29.67#ibcon#about to write, iclass 3, count 0 2006.175.08:11:29.67#ibcon#wrote, iclass 3, count 0 2006.175.08:11:29.67#ibcon#about to read 3, iclass 3, count 0 2006.175.08:11:29.69#ibcon#read 3, iclass 3, count 0 2006.175.08:11:29.69#ibcon#about to read 4, iclass 3, count 0 2006.175.08:11:29.69#ibcon#read 4, iclass 3, count 0 2006.175.08:11:29.69#ibcon#about to read 5, iclass 3, count 0 2006.175.08:11:29.69#ibcon#read 5, iclass 3, count 0 2006.175.08:11:29.69#ibcon#about to read 6, iclass 3, count 0 2006.175.08:11:29.69#ibcon#read 6, iclass 3, count 0 2006.175.08:11:29.69#ibcon#end of sib2, iclass 3, count 0 2006.175.08:11:29.69#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:11:29.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:11:29.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:11:29.69#ibcon#*before write, iclass 3, count 0 2006.175.08:11:29.69#ibcon#enter sib2, iclass 3, count 0 2006.175.08:11:29.69#ibcon#flushed, iclass 3, count 0 2006.175.08:11:29.69#ibcon#about to write, iclass 3, count 0 2006.175.08:11:29.69#ibcon#wrote, iclass 3, count 0 2006.175.08:11:29.69#ibcon#about to read 3, iclass 3, count 0 2006.175.08:11:29.73#ibcon#read 3, iclass 3, count 0 2006.175.08:11:29.73#ibcon#about to read 4, iclass 3, count 0 2006.175.08:11:29.73#ibcon#read 4, iclass 3, count 0 2006.175.08:11:29.73#ibcon#about to read 5, iclass 3, count 0 2006.175.08:11:29.73#ibcon#read 5, iclass 3, count 0 2006.175.08:11:29.73#ibcon#about to read 6, iclass 3, count 0 2006.175.08:11:29.73#ibcon#read 6, iclass 3, count 0 2006.175.08:11:29.73#ibcon#end of sib2, iclass 3, count 0 2006.175.08:11:29.73#ibcon#*after write, iclass 3, count 0 2006.175.08:11:29.73#ibcon#*before return 0, iclass 3, count 0 2006.175.08:11:29.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:29.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:29.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:11:29.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:11:29.73$vc4f8/va=6,6 2006.175.08:11:29.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.175.08:11:29.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.175.08:11:29.73#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:29.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:29.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:29.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:29.79#ibcon#enter wrdev, iclass 5, count 2 2006.175.08:11:29.79#ibcon#first serial, iclass 5, count 2 2006.175.08:11:29.79#ibcon#enter sib2, iclass 5, count 2 2006.175.08:11:29.79#ibcon#flushed, iclass 5, count 2 2006.175.08:11:29.79#ibcon#about to write, iclass 5, count 2 2006.175.08:11:29.79#ibcon#wrote, iclass 5, count 2 2006.175.08:11:29.79#ibcon#about to read 3, iclass 5, count 2 2006.175.08:11:29.81#ibcon#read 3, iclass 5, count 2 2006.175.08:11:29.81#ibcon#about to read 4, iclass 5, count 2 2006.175.08:11:29.81#ibcon#read 4, iclass 5, count 2 2006.175.08:11:29.81#ibcon#about to read 5, iclass 5, count 2 2006.175.08:11:29.81#ibcon#read 5, iclass 5, count 2 2006.175.08:11:29.81#ibcon#about to read 6, iclass 5, count 2 2006.175.08:11:29.81#ibcon#read 6, iclass 5, count 2 2006.175.08:11:29.81#ibcon#end of sib2, iclass 5, count 2 2006.175.08:11:29.81#ibcon#*mode == 0, iclass 5, count 2 2006.175.08:11:29.81#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.175.08:11:29.81#ibcon#[25=AT06-06\r\n] 2006.175.08:11:29.81#ibcon#*before write, iclass 5, count 2 2006.175.08:11:29.81#ibcon#enter sib2, iclass 5, count 2 2006.175.08:11:29.81#ibcon#flushed, iclass 5, count 2 2006.175.08:11:29.81#ibcon#about to write, iclass 5, count 2 2006.175.08:11:29.81#ibcon#wrote, iclass 5, count 2 2006.175.08:11:29.81#ibcon#about to read 3, iclass 5, count 2 2006.175.08:11:29.84#ibcon#read 3, iclass 5, count 2 2006.175.08:11:29.84#ibcon#about to read 4, iclass 5, count 2 2006.175.08:11:29.84#ibcon#read 4, iclass 5, count 2 2006.175.08:11:29.84#ibcon#about to read 5, iclass 5, count 2 2006.175.08:11:29.84#ibcon#read 5, iclass 5, count 2 2006.175.08:11:29.84#ibcon#about to read 6, iclass 5, count 2 2006.175.08:11:29.84#ibcon#read 6, iclass 5, count 2 2006.175.08:11:29.84#ibcon#end of sib2, iclass 5, count 2 2006.175.08:11:29.84#ibcon#*after write, iclass 5, count 2 2006.175.08:11:29.84#ibcon#*before return 0, iclass 5, count 2 2006.175.08:11:29.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:29.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:29.84#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.175.08:11:29.84#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:29.84#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:29.96#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:29.96#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:29.96#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:11:29.96#ibcon#first serial, iclass 5, count 0 2006.175.08:11:29.96#ibcon#enter sib2, iclass 5, count 0 2006.175.08:11:29.96#ibcon#flushed, iclass 5, count 0 2006.175.08:11:29.96#ibcon#about to write, iclass 5, count 0 2006.175.08:11:29.96#ibcon#wrote, iclass 5, count 0 2006.175.08:11:29.96#ibcon#about to read 3, iclass 5, count 0 2006.175.08:11:29.98#ibcon#read 3, iclass 5, count 0 2006.175.08:11:29.98#ibcon#about to read 4, iclass 5, count 0 2006.175.08:11:29.98#ibcon#read 4, iclass 5, count 0 2006.175.08:11:29.98#ibcon#about to read 5, iclass 5, count 0 2006.175.08:11:29.98#ibcon#read 5, iclass 5, count 0 2006.175.08:11:29.98#ibcon#about to read 6, iclass 5, count 0 2006.175.08:11:29.98#ibcon#read 6, iclass 5, count 0 2006.175.08:11:29.98#ibcon#end of sib2, iclass 5, count 0 2006.175.08:11:29.98#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:11:29.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:11:29.98#ibcon#[25=USB\r\n] 2006.175.08:11:29.98#ibcon#*before write, iclass 5, count 0 2006.175.08:11:29.98#ibcon#enter sib2, iclass 5, count 0 2006.175.08:11:29.98#ibcon#flushed, iclass 5, count 0 2006.175.08:11:29.98#ibcon#about to write, iclass 5, count 0 2006.175.08:11:29.98#ibcon#wrote, iclass 5, count 0 2006.175.08:11:29.98#ibcon#about to read 3, iclass 5, count 0 2006.175.08:11:30.01#ibcon#read 3, iclass 5, count 0 2006.175.08:11:30.01#ibcon#about to read 4, iclass 5, count 0 2006.175.08:11:30.01#ibcon#read 4, iclass 5, count 0 2006.175.08:11:30.01#ibcon#about to read 5, iclass 5, count 0 2006.175.08:11:30.01#ibcon#read 5, iclass 5, count 0 2006.175.08:11:30.01#ibcon#about to read 6, iclass 5, count 0 2006.175.08:11:30.01#ibcon#read 6, iclass 5, count 0 2006.175.08:11:30.01#ibcon#end of sib2, iclass 5, count 0 2006.175.08:11:30.01#ibcon#*after write, iclass 5, count 0 2006.175.08:11:30.01#ibcon#*before return 0, iclass 5, count 0 2006.175.08:11:30.01#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:30.01#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:30.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:11:30.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:11:30.01$vc4f8/valo=7,832.99 2006.175.08:11:30.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.08:11:30.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.08:11:30.01#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:30.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:30.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:30.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:30.01#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:11:30.01#ibcon#first serial, iclass 7, count 0 2006.175.08:11:30.01#ibcon#enter sib2, iclass 7, count 0 2006.175.08:11:30.01#ibcon#flushed, iclass 7, count 0 2006.175.08:11:30.01#ibcon#about to write, iclass 7, count 0 2006.175.08:11:30.01#ibcon#wrote, iclass 7, count 0 2006.175.08:11:30.01#ibcon#about to read 3, iclass 7, count 0 2006.175.08:11:30.03#ibcon#read 3, iclass 7, count 0 2006.175.08:11:30.03#ibcon#about to read 4, iclass 7, count 0 2006.175.08:11:30.03#ibcon#read 4, iclass 7, count 0 2006.175.08:11:30.03#ibcon#about to read 5, iclass 7, count 0 2006.175.08:11:30.03#ibcon#read 5, iclass 7, count 0 2006.175.08:11:30.03#ibcon#about to read 6, iclass 7, count 0 2006.175.08:11:30.03#ibcon#read 6, iclass 7, count 0 2006.175.08:11:30.03#ibcon#end of sib2, iclass 7, count 0 2006.175.08:11:30.03#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:11:30.03#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:11:30.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:11:30.03#ibcon#*before write, iclass 7, count 0 2006.175.08:11:30.03#ibcon#enter sib2, iclass 7, count 0 2006.175.08:11:30.03#ibcon#flushed, iclass 7, count 0 2006.175.08:11:30.03#ibcon#about to write, iclass 7, count 0 2006.175.08:11:30.03#ibcon#wrote, iclass 7, count 0 2006.175.08:11:30.03#ibcon#about to read 3, iclass 7, count 0 2006.175.08:11:30.07#ibcon#read 3, iclass 7, count 0 2006.175.08:11:30.07#ibcon#about to read 4, iclass 7, count 0 2006.175.08:11:30.07#ibcon#read 4, iclass 7, count 0 2006.175.08:11:30.07#ibcon#about to read 5, iclass 7, count 0 2006.175.08:11:30.07#ibcon#read 5, iclass 7, count 0 2006.175.08:11:30.07#ibcon#about to read 6, iclass 7, count 0 2006.175.08:11:30.07#ibcon#read 6, iclass 7, count 0 2006.175.08:11:30.07#ibcon#end of sib2, iclass 7, count 0 2006.175.08:11:30.07#ibcon#*after write, iclass 7, count 0 2006.175.08:11:30.07#ibcon#*before return 0, iclass 7, count 0 2006.175.08:11:30.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:30.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:30.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:11:30.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:11:30.07$vc4f8/va=7,6 2006.175.08:11:30.07#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.175.08:11:30.07#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.175.08:11:30.07#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:30.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:11:30.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:11:30.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:11:30.13#ibcon#enter wrdev, iclass 11, count 2 2006.175.08:11:30.13#ibcon#first serial, iclass 11, count 2 2006.175.08:11:30.13#ibcon#enter sib2, iclass 11, count 2 2006.175.08:11:30.13#ibcon#flushed, iclass 11, count 2 2006.175.08:11:30.13#ibcon#about to write, iclass 11, count 2 2006.175.08:11:30.13#ibcon#wrote, iclass 11, count 2 2006.175.08:11:30.13#ibcon#about to read 3, iclass 11, count 2 2006.175.08:11:30.15#ibcon#read 3, iclass 11, count 2 2006.175.08:11:30.15#ibcon#about to read 4, iclass 11, count 2 2006.175.08:11:30.15#ibcon#read 4, iclass 11, count 2 2006.175.08:11:30.15#ibcon#about to read 5, iclass 11, count 2 2006.175.08:11:30.15#ibcon#read 5, iclass 11, count 2 2006.175.08:11:30.15#ibcon#about to read 6, iclass 11, count 2 2006.175.08:11:30.15#ibcon#read 6, iclass 11, count 2 2006.175.08:11:30.15#ibcon#end of sib2, iclass 11, count 2 2006.175.08:11:30.15#ibcon#*mode == 0, iclass 11, count 2 2006.175.08:11:30.15#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.175.08:11:30.15#ibcon#[25=AT07-06\r\n] 2006.175.08:11:30.15#ibcon#*before write, iclass 11, count 2 2006.175.08:11:30.15#ibcon#enter sib2, iclass 11, count 2 2006.175.08:11:30.15#ibcon#flushed, iclass 11, count 2 2006.175.08:11:30.15#ibcon#about to write, iclass 11, count 2 2006.175.08:11:30.15#ibcon#wrote, iclass 11, count 2 2006.175.08:11:30.15#ibcon#about to read 3, iclass 11, count 2 2006.175.08:11:30.18#ibcon#read 3, iclass 11, count 2 2006.175.08:11:30.18#ibcon#about to read 4, iclass 11, count 2 2006.175.08:11:30.18#ibcon#read 4, iclass 11, count 2 2006.175.08:11:30.18#ibcon#about to read 5, iclass 11, count 2 2006.175.08:11:30.18#ibcon#read 5, iclass 11, count 2 2006.175.08:11:30.18#ibcon#about to read 6, iclass 11, count 2 2006.175.08:11:30.18#ibcon#read 6, iclass 11, count 2 2006.175.08:11:30.18#ibcon#end of sib2, iclass 11, count 2 2006.175.08:11:30.18#ibcon#*after write, iclass 11, count 2 2006.175.08:11:30.18#ibcon#*before return 0, iclass 11, count 2 2006.175.08:11:30.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:11:30.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:11:30.18#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.175.08:11:30.18#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:30.18#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:11:30.30#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:11:30.30#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:11:30.30#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:11:30.30#ibcon#first serial, iclass 11, count 0 2006.175.08:11:30.30#ibcon#enter sib2, iclass 11, count 0 2006.175.08:11:30.30#ibcon#flushed, iclass 11, count 0 2006.175.08:11:30.30#ibcon#about to write, iclass 11, count 0 2006.175.08:11:30.30#ibcon#wrote, iclass 11, count 0 2006.175.08:11:30.30#ibcon#about to read 3, iclass 11, count 0 2006.175.08:11:30.32#ibcon#read 3, iclass 11, count 0 2006.175.08:11:30.32#ibcon#about to read 4, iclass 11, count 0 2006.175.08:11:30.32#ibcon#read 4, iclass 11, count 0 2006.175.08:11:30.32#ibcon#about to read 5, iclass 11, count 0 2006.175.08:11:30.32#ibcon#read 5, iclass 11, count 0 2006.175.08:11:30.32#ibcon#about to read 6, iclass 11, count 0 2006.175.08:11:30.32#ibcon#read 6, iclass 11, count 0 2006.175.08:11:30.32#ibcon#end of sib2, iclass 11, count 0 2006.175.08:11:30.32#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:11:30.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:11:30.32#ibcon#[25=USB\r\n] 2006.175.08:11:30.32#ibcon#*before write, iclass 11, count 0 2006.175.08:11:30.32#ibcon#enter sib2, iclass 11, count 0 2006.175.08:11:30.32#ibcon#flushed, iclass 11, count 0 2006.175.08:11:30.32#ibcon#about to write, iclass 11, count 0 2006.175.08:11:30.32#ibcon#wrote, iclass 11, count 0 2006.175.08:11:30.32#ibcon#about to read 3, iclass 11, count 0 2006.175.08:11:30.35#ibcon#read 3, iclass 11, count 0 2006.175.08:11:30.35#ibcon#about to read 4, iclass 11, count 0 2006.175.08:11:30.35#ibcon#read 4, iclass 11, count 0 2006.175.08:11:30.35#ibcon#about to read 5, iclass 11, count 0 2006.175.08:11:30.35#ibcon#read 5, iclass 11, count 0 2006.175.08:11:30.35#ibcon#about to read 6, iclass 11, count 0 2006.175.08:11:30.35#ibcon#read 6, iclass 11, count 0 2006.175.08:11:30.35#ibcon#end of sib2, iclass 11, count 0 2006.175.08:11:30.35#ibcon#*after write, iclass 11, count 0 2006.175.08:11:30.35#ibcon#*before return 0, iclass 11, count 0 2006.175.08:11:30.35#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:11:30.35#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:11:30.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:11:30.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:11:30.35$vc4f8/valo=8,852.99 2006.175.08:11:30.35#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.175.08:11:30.35#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.175.08:11:30.35#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:30.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:11:30.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:11:30.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:11:30.35#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:11:30.35#ibcon#first serial, iclass 13, count 0 2006.175.08:11:30.35#ibcon#enter sib2, iclass 13, count 0 2006.175.08:11:30.35#ibcon#flushed, iclass 13, count 0 2006.175.08:11:30.35#ibcon#about to write, iclass 13, count 0 2006.175.08:11:30.35#ibcon#wrote, iclass 13, count 0 2006.175.08:11:30.35#ibcon#about to read 3, iclass 13, count 0 2006.175.08:11:30.37#ibcon#read 3, iclass 13, count 0 2006.175.08:11:30.37#ibcon#about to read 4, iclass 13, count 0 2006.175.08:11:30.37#ibcon#read 4, iclass 13, count 0 2006.175.08:11:30.37#ibcon#about to read 5, iclass 13, count 0 2006.175.08:11:30.37#ibcon#read 5, iclass 13, count 0 2006.175.08:11:30.37#ibcon#about to read 6, iclass 13, count 0 2006.175.08:11:30.37#ibcon#read 6, iclass 13, count 0 2006.175.08:11:30.37#ibcon#end of sib2, iclass 13, count 0 2006.175.08:11:30.37#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:11:30.37#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:11:30.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:11:30.37#ibcon#*before write, iclass 13, count 0 2006.175.08:11:30.37#ibcon#enter sib2, iclass 13, count 0 2006.175.08:11:30.37#ibcon#flushed, iclass 13, count 0 2006.175.08:11:30.37#ibcon#about to write, iclass 13, count 0 2006.175.08:11:30.37#ibcon#wrote, iclass 13, count 0 2006.175.08:11:30.37#ibcon#about to read 3, iclass 13, count 0 2006.175.08:11:30.41#ibcon#read 3, iclass 13, count 0 2006.175.08:11:30.41#ibcon#about to read 4, iclass 13, count 0 2006.175.08:11:30.41#ibcon#read 4, iclass 13, count 0 2006.175.08:11:30.41#ibcon#about to read 5, iclass 13, count 0 2006.175.08:11:30.41#ibcon#read 5, iclass 13, count 0 2006.175.08:11:30.41#ibcon#about to read 6, iclass 13, count 0 2006.175.08:11:30.41#ibcon#read 6, iclass 13, count 0 2006.175.08:11:30.41#ibcon#end of sib2, iclass 13, count 0 2006.175.08:11:30.41#ibcon#*after write, iclass 13, count 0 2006.175.08:11:30.41#ibcon#*before return 0, iclass 13, count 0 2006.175.08:11:30.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:11:30.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:11:30.41#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:11:30.41#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:11:30.41$vc4f8/va=8,6 2006.175.08:11:30.41#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.175.08:11:30.41#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.175.08:11:30.41#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:30.41#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:11:30.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:11:30.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:11:30.47#ibcon#enter wrdev, iclass 15, count 2 2006.175.08:11:30.47#ibcon#first serial, iclass 15, count 2 2006.175.08:11:30.47#ibcon#enter sib2, iclass 15, count 2 2006.175.08:11:30.47#ibcon#flushed, iclass 15, count 2 2006.175.08:11:30.47#ibcon#about to write, iclass 15, count 2 2006.175.08:11:30.47#ibcon#wrote, iclass 15, count 2 2006.175.08:11:30.47#ibcon#about to read 3, iclass 15, count 2 2006.175.08:11:30.49#ibcon#read 3, iclass 15, count 2 2006.175.08:11:30.49#ibcon#about to read 4, iclass 15, count 2 2006.175.08:11:30.49#ibcon#read 4, iclass 15, count 2 2006.175.08:11:30.49#ibcon#about to read 5, iclass 15, count 2 2006.175.08:11:30.49#ibcon#read 5, iclass 15, count 2 2006.175.08:11:30.49#ibcon#about to read 6, iclass 15, count 2 2006.175.08:11:30.49#ibcon#read 6, iclass 15, count 2 2006.175.08:11:30.49#ibcon#end of sib2, iclass 15, count 2 2006.175.08:11:30.49#ibcon#*mode == 0, iclass 15, count 2 2006.175.08:11:30.49#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.175.08:11:30.49#ibcon#[25=AT08-06\r\n] 2006.175.08:11:30.49#ibcon#*before write, iclass 15, count 2 2006.175.08:11:30.49#ibcon#enter sib2, iclass 15, count 2 2006.175.08:11:30.49#ibcon#flushed, iclass 15, count 2 2006.175.08:11:30.49#ibcon#about to write, iclass 15, count 2 2006.175.08:11:30.49#ibcon#wrote, iclass 15, count 2 2006.175.08:11:30.49#ibcon#about to read 3, iclass 15, count 2 2006.175.08:11:30.52#ibcon#read 3, iclass 15, count 2 2006.175.08:11:30.52#ibcon#about to read 4, iclass 15, count 2 2006.175.08:11:30.52#ibcon#read 4, iclass 15, count 2 2006.175.08:11:30.52#ibcon#about to read 5, iclass 15, count 2 2006.175.08:11:30.52#ibcon#read 5, iclass 15, count 2 2006.175.08:11:30.52#ibcon#about to read 6, iclass 15, count 2 2006.175.08:11:30.52#ibcon#read 6, iclass 15, count 2 2006.175.08:11:30.52#ibcon#end of sib2, iclass 15, count 2 2006.175.08:11:30.52#ibcon#*after write, iclass 15, count 2 2006.175.08:11:30.52#ibcon#*before return 0, iclass 15, count 2 2006.175.08:11:30.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:11:30.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:11:30.52#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.175.08:11:30.52#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:30.52#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:11:30.64#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:11:30.64#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:11:30.64#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:11:30.64#ibcon#first serial, iclass 15, count 0 2006.175.08:11:30.64#ibcon#enter sib2, iclass 15, count 0 2006.175.08:11:30.64#ibcon#flushed, iclass 15, count 0 2006.175.08:11:30.64#ibcon#about to write, iclass 15, count 0 2006.175.08:11:30.64#ibcon#wrote, iclass 15, count 0 2006.175.08:11:30.64#ibcon#about to read 3, iclass 15, count 0 2006.175.08:11:30.66#ibcon#read 3, iclass 15, count 0 2006.175.08:11:30.66#ibcon#about to read 4, iclass 15, count 0 2006.175.08:11:30.66#ibcon#read 4, iclass 15, count 0 2006.175.08:11:30.66#ibcon#about to read 5, iclass 15, count 0 2006.175.08:11:30.66#ibcon#read 5, iclass 15, count 0 2006.175.08:11:30.66#ibcon#about to read 6, iclass 15, count 0 2006.175.08:11:30.66#ibcon#read 6, iclass 15, count 0 2006.175.08:11:30.66#ibcon#end of sib2, iclass 15, count 0 2006.175.08:11:30.66#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:11:30.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:11:30.66#ibcon#[25=USB\r\n] 2006.175.08:11:30.66#ibcon#*before write, iclass 15, count 0 2006.175.08:11:30.66#ibcon#enter sib2, iclass 15, count 0 2006.175.08:11:30.66#ibcon#flushed, iclass 15, count 0 2006.175.08:11:30.66#ibcon#about to write, iclass 15, count 0 2006.175.08:11:30.66#ibcon#wrote, iclass 15, count 0 2006.175.08:11:30.66#ibcon#about to read 3, iclass 15, count 0 2006.175.08:11:30.69#ibcon#read 3, iclass 15, count 0 2006.175.08:11:30.69#ibcon#about to read 4, iclass 15, count 0 2006.175.08:11:30.69#ibcon#read 4, iclass 15, count 0 2006.175.08:11:30.69#ibcon#about to read 5, iclass 15, count 0 2006.175.08:11:30.69#ibcon#read 5, iclass 15, count 0 2006.175.08:11:30.69#ibcon#about to read 6, iclass 15, count 0 2006.175.08:11:30.69#ibcon#read 6, iclass 15, count 0 2006.175.08:11:30.69#ibcon#end of sib2, iclass 15, count 0 2006.175.08:11:30.69#ibcon#*after write, iclass 15, count 0 2006.175.08:11:30.69#ibcon#*before return 0, iclass 15, count 0 2006.175.08:11:30.69#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:11:30.69#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:11:30.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:11:30.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:11:30.69$vc4f8/vblo=1,632.99 2006.175.08:11:30.69#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.08:11:30.69#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.08:11:30.69#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:30.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:11:30.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:11:30.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:11:30.69#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:11:30.69#ibcon#first serial, iclass 17, count 0 2006.175.08:11:30.69#ibcon#enter sib2, iclass 17, count 0 2006.175.08:11:30.69#ibcon#flushed, iclass 17, count 0 2006.175.08:11:30.69#ibcon#about to write, iclass 17, count 0 2006.175.08:11:30.69#ibcon#wrote, iclass 17, count 0 2006.175.08:11:30.69#ibcon#about to read 3, iclass 17, count 0 2006.175.08:11:30.71#ibcon#read 3, iclass 17, count 0 2006.175.08:11:30.71#ibcon#about to read 4, iclass 17, count 0 2006.175.08:11:30.71#ibcon#read 4, iclass 17, count 0 2006.175.08:11:30.71#ibcon#about to read 5, iclass 17, count 0 2006.175.08:11:30.71#ibcon#read 5, iclass 17, count 0 2006.175.08:11:30.71#ibcon#about to read 6, iclass 17, count 0 2006.175.08:11:30.71#ibcon#read 6, iclass 17, count 0 2006.175.08:11:30.71#ibcon#end of sib2, iclass 17, count 0 2006.175.08:11:30.71#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:11:30.71#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:11:30.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:11:30.71#ibcon#*before write, iclass 17, count 0 2006.175.08:11:30.71#ibcon#enter sib2, iclass 17, count 0 2006.175.08:11:30.71#ibcon#flushed, iclass 17, count 0 2006.175.08:11:30.71#ibcon#about to write, iclass 17, count 0 2006.175.08:11:30.71#ibcon#wrote, iclass 17, count 0 2006.175.08:11:30.71#ibcon#about to read 3, iclass 17, count 0 2006.175.08:11:30.75#ibcon#read 3, iclass 17, count 0 2006.175.08:11:30.75#ibcon#about to read 4, iclass 17, count 0 2006.175.08:11:30.75#ibcon#read 4, iclass 17, count 0 2006.175.08:11:30.75#ibcon#about to read 5, iclass 17, count 0 2006.175.08:11:30.75#ibcon#read 5, iclass 17, count 0 2006.175.08:11:30.75#ibcon#about to read 6, iclass 17, count 0 2006.175.08:11:30.75#ibcon#read 6, iclass 17, count 0 2006.175.08:11:30.75#ibcon#end of sib2, iclass 17, count 0 2006.175.08:11:30.75#ibcon#*after write, iclass 17, count 0 2006.175.08:11:30.75#ibcon#*before return 0, iclass 17, count 0 2006.175.08:11:30.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:11:30.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:11:30.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:11:30.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:11:30.75$vc4f8/vb=1,4 2006.175.08:11:30.75#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.175.08:11:30.75#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.175.08:11:30.75#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:30.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:11:30.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:11:30.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:11:30.75#ibcon#enter wrdev, iclass 19, count 2 2006.175.08:11:30.75#ibcon#first serial, iclass 19, count 2 2006.175.08:11:30.75#ibcon#enter sib2, iclass 19, count 2 2006.175.08:11:30.75#ibcon#flushed, iclass 19, count 2 2006.175.08:11:30.75#ibcon#about to write, iclass 19, count 2 2006.175.08:11:30.75#ibcon#wrote, iclass 19, count 2 2006.175.08:11:30.75#ibcon#about to read 3, iclass 19, count 2 2006.175.08:11:30.77#ibcon#read 3, iclass 19, count 2 2006.175.08:11:30.77#ibcon#about to read 4, iclass 19, count 2 2006.175.08:11:30.77#ibcon#read 4, iclass 19, count 2 2006.175.08:11:30.77#ibcon#about to read 5, iclass 19, count 2 2006.175.08:11:30.77#ibcon#read 5, iclass 19, count 2 2006.175.08:11:30.77#ibcon#about to read 6, iclass 19, count 2 2006.175.08:11:30.77#ibcon#read 6, iclass 19, count 2 2006.175.08:11:30.77#ibcon#end of sib2, iclass 19, count 2 2006.175.08:11:30.77#ibcon#*mode == 0, iclass 19, count 2 2006.175.08:11:30.77#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.175.08:11:30.77#ibcon#[27=AT01-04\r\n] 2006.175.08:11:30.77#ibcon#*before write, iclass 19, count 2 2006.175.08:11:30.77#ibcon#enter sib2, iclass 19, count 2 2006.175.08:11:30.77#ibcon#flushed, iclass 19, count 2 2006.175.08:11:30.77#ibcon#about to write, iclass 19, count 2 2006.175.08:11:30.77#ibcon#wrote, iclass 19, count 2 2006.175.08:11:30.77#ibcon#about to read 3, iclass 19, count 2 2006.175.08:11:30.80#ibcon#read 3, iclass 19, count 2 2006.175.08:11:30.80#ibcon#about to read 4, iclass 19, count 2 2006.175.08:11:30.80#ibcon#read 4, iclass 19, count 2 2006.175.08:11:30.80#ibcon#about to read 5, iclass 19, count 2 2006.175.08:11:30.80#ibcon#read 5, iclass 19, count 2 2006.175.08:11:30.80#ibcon#about to read 6, iclass 19, count 2 2006.175.08:11:30.80#ibcon#read 6, iclass 19, count 2 2006.175.08:11:30.80#ibcon#end of sib2, iclass 19, count 2 2006.175.08:11:30.80#ibcon#*after write, iclass 19, count 2 2006.175.08:11:30.80#ibcon#*before return 0, iclass 19, count 2 2006.175.08:11:30.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:11:30.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:11:30.80#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.175.08:11:30.80#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:30.80#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:11:30.92#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:11:30.92#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:11:30.92#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:11:30.92#ibcon#first serial, iclass 19, count 0 2006.175.08:11:30.92#ibcon#enter sib2, iclass 19, count 0 2006.175.08:11:30.92#ibcon#flushed, iclass 19, count 0 2006.175.08:11:30.92#ibcon#about to write, iclass 19, count 0 2006.175.08:11:30.92#ibcon#wrote, iclass 19, count 0 2006.175.08:11:30.92#ibcon#about to read 3, iclass 19, count 0 2006.175.08:11:30.94#ibcon#read 3, iclass 19, count 0 2006.175.08:11:30.94#ibcon#about to read 4, iclass 19, count 0 2006.175.08:11:30.94#ibcon#read 4, iclass 19, count 0 2006.175.08:11:30.94#ibcon#about to read 5, iclass 19, count 0 2006.175.08:11:30.94#ibcon#read 5, iclass 19, count 0 2006.175.08:11:30.94#ibcon#about to read 6, iclass 19, count 0 2006.175.08:11:30.94#ibcon#read 6, iclass 19, count 0 2006.175.08:11:30.94#ibcon#end of sib2, iclass 19, count 0 2006.175.08:11:30.94#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:11:30.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:11:30.94#ibcon#[27=USB\r\n] 2006.175.08:11:30.94#ibcon#*before write, iclass 19, count 0 2006.175.08:11:30.94#ibcon#enter sib2, iclass 19, count 0 2006.175.08:11:30.94#ibcon#flushed, iclass 19, count 0 2006.175.08:11:30.94#ibcon#about to write, iclass 19, count 0 2006.175.08:11:30.94#ibcon#wrote, iclass 19, count 0 2006.175.08:11:30.94#ibcon#about to read 3, iclass 19, count 0 2006.175.08:11:30.97#ibcon#read 3, iclass 19, count 0 2006.175.08:11:30.97#ibcon#about to read 4, iclass 19, count 0 2006.175.08:11:30.97#ibcon#read 4, iclass 19, count 0 2006.175.08:11:30.97#ibcon#about to read 5, iclass 19, count 0 2006.175.08:11:30.97#ibcon#read 5, iclass 19, count 0 2006.175.08:11:30.97#ibcon#about to read 6, iclass 19, count 0 2006.175.08:11:30.97#ibcon#read 6, iclass 19, count 0 2006.175.08:11:30.97#ibcon#end of sib2, iclass 19, count 0 2006.175.08:11:30.97#ibcon#*after write, iclass 19, count 0 2006.175.08:11:30.97#ibcon#*before return 0, iclass 19, count 0 2006.175.08:11:30.97#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:11:30.97#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:11:30.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:11:30.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:11:30.97$vc4f8/vblo=2,640.99 2006.175.08:11:30.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.08:11:30.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.08:11:30.97#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:30.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:30.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:30.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:30.97#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:11:30.97#ibcon#first serial, iclass 21, count 0 2006.175.08:11:30.97#ibcon#enter sib2, iclass 21, count 0 2006.175.08:11:30.97#ibcon#flushed, iclass 21, count 0 2006.175.08:11:30.97#ibcon#about to write, iclass 21, count 0 2006.175.08:11:30.97#ibcon#wrote, iclass 21, count 0 2006.175.08:11:30.97#ibcon#about to read 3, iclass 21, count 0 2006.175.08:11:30.99#ibcon#read 3, iclass 21, count 0 2006.175.08:11:30.99#ibcon#about to read 4, iclass 21, count 0 2006.175.08:11:30.99#ibcon#read 4, iclass 21, count 0 2006.175.08:11:30.99#ibcon#about to read 5, iclass 21, count 0 2006.175.08:11:30.99#ibcon#read 5, iclass 21, count 0 2006.175.08:11:30.99#ibcon#about to read 6, iclass 21, count 0 2006.175.08:11:30.99#ibcon#read 6, iclass 21, count 0 2006.175.08:11:30.99#ibcon#end of sib2, iclass 21, count 0 2006.175.08:11:30.99#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:11:30.99#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:11:30.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:11:30.99#ibcon#*before write, iclass 21, count 0 2006.175.08:11:30.99#ibcon#enter sib2, iclass 21, count 0 2006.175.08:11:30.99#ibcon#flushed, iclass 21, count 0 2006.175.08:11:30.99#ibcon#about to write, iclass 21, count 0 2006.175.08:11:30.99#ibcon#wrote, iclass 21, count 0 2006.175.08:11:30.99#ibcon#about to read 3, iclass 21, count 0 2006.175.08:11:31.03#ibcon#read 3, iclass 21, count 0 2006.175.08:11:31.03#ibcon#about to read 4, iclass 21, count 0 2006.175.08:11:31.03#ibcon#read 4, iclass 21, count 0 2006.175.08:11:31.03#ibcon#about to read 5, iclass 21, count 0 2006.175.08:11:31.03#ibcon#read 5, iclass 21, count 0 2006.175.08:11:31.03#ibcon#about to read 6, iclass 21, count 0 2006.175.08:11:31.03#ibcon#read 6, iclass 21, count 0 2006.175.08:11:31.03#ibcon#end of sib2, iclass 21, count 0 2006.175.08:11:31.03#ibcon#*after write, iclass 21, count 0 2006.175.08:11:31.03#ibcon#*before return 0, iclass 21, count 0 2006.175.08:11:31.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:31.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:11:31.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:11:31.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:11:31.03$vc4f8/vb=2,4 2006.175.08:11:31.03#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.08:11:31.03#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.08:11:31.03#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:31.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:31.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:31.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:31.09#ibcon#enter wrdev, iclass 23, count 2 2006.175.08:11:31.09#ibcon#first serial, iclass 23, count 2 2006.175.08:11:31.09#ibcon#enter sib2, iclass 23, count 2 2006.175.08:11:31.09#ibcon#flushed, iclass 23, count 2 2006.175.08:11:31.09#ibcon#about to write, iclass 23, count 2 2006.175.08:11:31.09#ibcon#wrote, iclass 23, count 2 2006.175.08:11:31.09#ibcon#about to read 3, iclass 23, count 2 2006.175.08:11:31.11#ibcon#read 3, iclass 23, count 2 2006.175.08:11:31.11#ibcon#about to read 4, iclass 23, count 2 2006.175.08:11:31.11#ibcon#read 4, iclass 23, count 2 2006.175.08:11:31.11#ibcon#about to read 5, iclass 23, count 2 2006.175.08:11:31.11#ibcon#read 5, iclass 23, count 2 2006.175.08:11:31.11#ibcon#about to read 6, iclass 23, count 2 2006.175.08:11:31.11#ibcon#read 6, iclass 23, count 2 2006.175.08:11:31.11#ibcon#end of sib2, iclass 23, count 2 2006.175.08:11:31.11#ibcon#*mode == 0, iclass 23, count 2 2006.175.08:11:31.11#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.08:11:31.11#ibcon#[27=AT02-04\r\n] 2006.175.08:11:31.11#ibcon#*before write, iclass 23, count 2 2006.175.08:11:31.11#ibcon#enter sib2, iclass 23, count 2 2006.175.08:11:31.11#ibcon#flushed, iclass 23, count 2 2006.175.08:11:31.11#ibcon#about to write, iclass 23, count 2 2006.175.08:11:31.11#ibcon#wrote, iclass 23, count 2 2006.175.08:11:31.11#ibcon#about to read 3, iclass 23, count 2 2006.175.08:11:31.14#ibcon#read 3, iclass 23, count 2 2006.175.08:11:31.14#ibcon#about to read 4, iclass 23, count 2 2006.175.08:11:31.14#ibcon#read 4, iclass 23, count 2 2006.175.08:11:31.14#ibcon#about to read 5, iclass 23, count 2 2006.175.08:11:31.14#ibcon#read 5, iclass 23, count 2 2006.175.08:11:31.14#ibcon#about to read 6, iclass 23, count 2 2006.175.08:11:31.14#ibcon#read 6, iclass 23, count 2 2006.175.08:11:31.14#ibcon#end of sib2, iclass 23, count 2 2006.175.08:11:31.14#ibcon#*after write, iclass 23, count 2 2006.175.08:11:31.14#ibcon#*before return 0, iclass 23, count 2 2006.175.08:11:31.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:31.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:11:31.14#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.08:11:31.14#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:31.14#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:31.26#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:31.26#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:31.26#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:11:31.26#ibcon#first serial, iclass 23, count 0 2006.175.08:11:31.26#ibcon#enter sib2, iclass 23, count 0 2006.175.08:11:31.26#ibcon#flushed, iclass 23, count 0 2006.175.08:11:31.26#ibcon#about to write, iclass 23, count 0 2006.175.08:11:31.26#ibcon#wrote, iclass 23, count 0 2006.175.08:11:31.26#ibcon#about to read 3, iclass 23, count 0 2006.175.08:11:31.28#ibcon#read 3, iclass 23, count 0 2006.175.08:11:31.28#ibcon#about to read 4, iclass 23, count 0 2006.175.08:11:31.28#ibcon#read 4, iclass 23, count 0 2006.175.08:11:31.28#ibcon#about to read 5, iclass 23, count 0 2006.175.08:11:31.28#ibcon#read 5, iclass 23, count 0 2006.175.08:11:31.28#ibcon#about to read 6, iclass 23, count 0 2006.175.08:11:31.28#ibcon#read 6, iclass 23, count 0 2006.175.08:11:31.28#ibcon#end of sib2, iclass 23, count 0 2006.175.08:11:31.28#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:11:31.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:11:31.28#ibcon#[27=USB\r\n] 2006.175.08:11:31.28#ibcon#*before write, iclass 23, count 0 2006.175.08:11:31.28#ibcon#enter sib2, iclass 23, count 0 2006.175.08:11:31.28#ibcon#flushed, iclass 23, count 0 2006.175.08:11:31.28#ibcon#about to write, iclass 23, count 0 2006.175.08:11:31.28#ibcon#wrote, iclass 23, count 0 2006.175.08:11:31.28#ibcon#about to read 3, iclass 23, count 0 2006.175.08:11:31.31#ibcon#read 3, iclass 23, count 0 2006.175.08:11:31.31#ibcon#about to read 4, iclass 23, count 0 2006.175.08:11:31.31#ibcon#read 4, iclass 23, count 0 2006.175.08:11:31.31#ibcon#about to read 5, iclass 23, count 0 2006.175.08:11:31.31#ibcon#read 5, iclass 23, count 0 2006.175.08:11:31.31#ibcon#about to read 6, iclass 23, count 0 2006.175.08:11:31.31#ibcon#read 6, iclass 23, count 0 2006.175.08:11:31.31#ibcon#end of sib2, iclass 23, count 0 2006.175.08:11:31.31#ibcon#*after write, iclass 23, count 0 2006.175.08:11:31.31#ibcon#*before return 0, iclass 23, count 0 2006.175.08:11:31.31#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:31.31#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:11:31.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:11:31.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:11:31.31$vc4f8/vblo=3,656.99 2006.175.08:11:31.31#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.08:11:31.31#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.08:11:31.31#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:31.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:31.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:31.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:31.31#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:11:31.31#ibcon#first serial, iclass 25, count 0 2006.175.08:11:31.31#ibcon#enter sib2, iclass 25, count 0 2006.175.08:11:31.31#ibcon#flushed, iclass 25, count 0 2006.175.08:11:31.31#ibcon#about to write, iclass 25, count 0 2006.175.08:11:31.31#ibcon#wrote, iclass 25, count 0 2006.175.08:11:31.31#ibcon#about to read 3, iclass 25, count 0 2006.175.08:11:31.33#ibcon#read 3, iclass 25, count 0 2006.175.08:11:31.33#ibcon#about to read 4, iclass 25, count 0 2006.175.08:11:31.33#ibcon#read 4, iclass 25, count 0 2006.175.08:11:31.33#ibcon#about to read 5, iclass 25, count 0 2006.175.08:11:31.33#ibcon#read 5, iclass 25, count 0 2006.175.08:11:31.33#ibcon#about to read 6, iclass 25, count 0 2006.175.08:11:31.33#ibcon#read 6, iclass 25, count 0 2006.175.08:11:31.33#ibcon#end of sib2, iclass 25, count 0 2006.175.08:11:31.33#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:11:31.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:11:31.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:11:31.33#ibcon#*before write, iclass 25, count 0 2006.175.08:11:31.33#ibcon#enter sib2, iclass 25, count 0 2006.175.08:11:31.33#ibcon#flushed, iclass 25, count 0 2006.175.08:11:31.33#ibcon#about to write, iclass 25, count 0 2006.175.08:11:31.33#ibcon#wrote, iclass 25, count 0 2006.175.08:11:31.33#ibcon#about to read 3, iclass 25, count 0 2006.175.08:11:31.37#ibcon#read 3, iclass 25, count 0 2006.175.08:11:31.37#ibcon#about to read 4, iclass 25, count 0 2006.175.08:11:31.37#ibcon#read 4, iclass 25, count 0 2006.175.08:11:31.37#ibcon#about to read 5, iclass 25, count 0 2006.175.08:11:31.37#ibcon#read 5, iclass 25, count 0 2006.175.08:11:31.37#ibcon#about to read 6, iclass 25, count 0 2006.175.08:11:31.37#ibcon#read 6, iclass 25, count 0 2006.175.08:11:31.37#ibcon#end of sib2, iclass 25, count 0 2006.175.08:11:31.37#ibcon#*after write, iclass 25, count 0 2006.175.08:11:31.37#ibcon#*before return 0, iclass 25, count 0 2006.175.08:11:31.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:31.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:11:31.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:11:31.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:11:31.37$vc4f8/vb=3,4 2006.175.08:11:31.37#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.08:11:31.37#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.08:11:31.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:31.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:31.42#abcon#<5=/04 4.5 7.4 25.78 701007.3\r\n> 2006.175.08:11:31.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:31.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:31.43#ibcon#enter wrdev, iclass 27, count 2 2006.175.08:11:31.43#ibcon#first serial, iclass 27, count 2 2006.175.08:11:31.43#ibcon#enter sib2, iclass 27, count 2 2006.175.08:11:31.43#ibcon#flushed, iclass 27, count 2 2006.175.08:11:31.43#ibcon#about to write, iclass 27, count 2 2006.175.08:11:31.43#ibcon#wrote, iclass 27, count 2 2006.175.08:11:31.43#ibcon#about to read 3, iclass 27, count 2 2006.175.08:11:31.44#abcon#{5=INTERFACE CLEAR} 2006.175.08:11:31.45#ibcon#read 3, iclass 27, count 2 2006.175.08:11:31.45#ibcon#about to read 4, iclass 27, count 2 2006.175.08:11:31.45#ibcon#read 4, iclass 27, count 2 2006.175.08:11:31.45#ibcon#about to read 5, iclass 27, count 2 2006.175.08:11:31.45#ibcon#read 5, iclass 27, count 2 2006.175.08:11:31.45#ibcon#about to read 6, iclass 27, count 2 2006.175.08:11:31.45#ibcon#read 6, iclass 27, count 2 2006.175.08:11:31.45#ibcon#end of sib2, iclass 27, count 2 2006.175.08:11:31.45#ibcon#*mode == 0, iclass 27, count 2 2006.175.08:11:31.45#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.08:11:31.45#ibcon#[27=AT03-04\r\n] 2006.175.08:11:31.45#ibcon#*before write, iclass 27, count 2 2006.175.08:11:31.45#ibcon#enter sib2, iclass 27, count 2 2006.175.08:11:31.45#ibcon#flushed, iclass 27, count 2 2006.175.08:11:31.45#ibcon#about to write, iclass 27, count 2 2006.175.08:11:31.45#ibcon#wrote, iclass 27, count 2 2006.175.08:11:31.45#ibcon#about to read 3, iclass 27, count 2 2006.175.08:11:31.48#ibcon#read 3, iclass 27, count 2 2006.175.08:11:31.48#ibcon#about to read 4, iclass 27, count 2 2006.175.08:11:31.48#ibcon#read 4, iclass 27, count 2 2006.175.08:11:31.48#ibcon#about to read 5, iclass 27, count 2 2006.175.08:11:31.48#ibcon#read 5, iclass 27, count 2 2006.175.08:11:31.48#ibcon#about to read 6, iclass 27, count 2 2006.175.08:11:31.48#ibcon#read 6, iclass 27, count 2 2006.175.08:11:31.48#ibcon#end of sib2, iclass 27, count 2 2006.175.08:11:31.48#ibcon#*after write, iclass 27, count 2 2006.175.08:11:31.48#ibcon#*before return 0, iclass 27, count 2 2006.175.08:11:31.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:31.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:11:31.48#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.08:11:31.48#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:31.48#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:31.50#abcon#[5=S1D000X0/0*\r\n] 2006.175.08:11:31.60#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:31.60#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:31.60#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:11:31.60#ibcon#first serial, iclass 27, count 0 2006.175.08:11:31.60#ibcon#enter sib2, iclass 27, count 0 2006.175.08:11:31.60#ibcon#flushed, iclass 27, count 0 2006.175.08:11:31.60#ibcon#about to write, iclass 27, count 0 2006.175.08:11:31.60#ibcon#wrote, iclass 27, count 0 2006.175.08:11:31.60#ibcon#about to read 3, iclass 27, count 0 2006.175.08:11:31.62#ibcon#read 3, iclass 27, count 0 2006.175.08:11:31.62#ibcon#about to read 4, iclass 27, count 0 2006.175.08:11:31.62#ibcon#read 4, iclass 27, count 0 2006.175.08:11:31.62#ibcon#about to read 5, iclass 27, count 0 2006.175.08:11:31.62#ibcon#read 5, iclass 27, count 0 2006.175.08:11:31.62#ibcon#about to read 6, iclass 27, count 0 2006.175.08:11:31.62#ibcon#read 6, iclass 27, count 0 2006.175.08:11:31.62#ibcon#end of sib2, iclass 27, count 0 2006.175.08:11:31.62#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:11:31.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:11:31.62#ibcon#[27=USB\r\n] 2006.175.08:11:31.62#ibcon#*before write, iclass 27, count 0 2006.175.08:11:31.62#ibcon#enter sib2, iclass 27, count 0 2006.175.08:11:31.62#ibcon#flushed, iclass 27, count 0 2006.175.08:11:31.62#ibcon#about to write, iclass 27, count 0 2006.175.08:11:31.62#ibcon#wrote, iclass 27, count 0 2006.175.08:11:31.62#ibcon#about to read 3, iclass 27, count 0 2006.175.08:11:31.65#ibcon#read 3, iclass 27, count 0 2006.175.08:11:31.65#ibcon#about to read 4, iclass 27, count 0 2006.175.08:11:31.65#ibcon#read 4, iclass 27, count 0 2006.175.08:11:31.65#ibcon#about to read 5, iclass 27, count 0 2006.175.08:11:31.65#ibcon#read 5, iclass 27, count 0 2006.175.08:11:31.65#ibcon#about to read 6, iclass 27, count 0 2006.175.08:11:31.65#ibcon#read 6, iclass 27, count 0 2006.175.08:11:31.65#ibcon#end of sib2, iclass 27, count 0 2006.175.08:11:31.65#ibcon#*after write, iclass 27, count 0 2006.175.08:11:31.65#ibcon#*before return 0, iclass 27, count 0 2006.175.08:11:31.65#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:31.65#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:11:31.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:11:31.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:11:31.65$vc4f8/vblo=4,712.99 2006.175.08:11:31.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.08:11:31.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.08:11:31.65#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:31.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:31.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:31.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:31.65#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:11:31.65#ibcon#first serial, iclass 33, count 0 2006.175.08:11:31.65#ibcon#enter sib2, iclass 33, count 0 2006.175.08:11:31.65#ibcon#flushed, iclass 33, count 0 2006.175.08:11:31.65#ibcon#about to write, iclass 33, count 0 2006.175.08:11:31.65#ibcon#wrote, iclass 33, count 0 2006.175.08:11:31.65#ibcon#about to read 3, iclass 33, count 0 2006.175.08:11:31.67#ibcon#read 3, iclass 33, count 0 2006.175.08:11:31.67#ibcon#about to read 4, iclass 33, count 0 2006.175.08:11:31.67#ibcon#read 4, iclass 33, count 0 2006.175.08:11:31.67#ibcon#about to read 5, iclass 33, count 0 2006.175.08:11:31.67#ibcon#read 5, iclass 33, count 0 2006.175.08:11:31.67#ibcon#about to read 6, iclass 33, count 0 2006.175.08:11:31.67#ibcon#read 6, iclass 33, count 0 2006.175.08:11:31.67#ibcon#end of sib2, iclass 33, count 0 2006.175.08:11:31.67#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:11:31.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:11:31.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:11:31.67#ibcon#*before write, iclass 33, count 0 2006.175.08:11:31.67#ibcon#enter sib2, iclass 33, count 0 2006.175.08:11:31.67#ibcon#flushed, iclass 33, count 0 2006.175.08:11:31.67#ibcon#about to write, iclass 33, count 0 2006.175.08:11:31.67#ibcon#wrote, iclass 33, count 0 2006.175.08:11:31.67#ibcon#about to read 3, iclass 33, count 0 2006.175.08:11:31.71#ibcon#read 3, iclass 33, count 0 2006.175.08:11:31.71#ibcon#about to read 4, iclass 33, count 0 2006.175.08:11:31.71#ibcon#read 4, iclass 33, count 0 2006.175.08:11:31.71#ibcon#about to read 5, iclass 33, count 0 2006.175.08:11:31.71#ibcon#read 5, iclass 33, count 0 2006.175.08:11:31.71#ibcon#about to read 6, iclass 33, count 0 2006.175.08:11:31.71#ibcon#read 6, iclass 33, count 0 2006.175.08:11:31.71#ibcon#end of sib2, iclass 33, count 0 2006.175.08:11:31.71#ibcon#*after write, iclass 33, count 0 2006.175.08:11:31.71#ibcon#*before return 0, iclass 33, count 0 2006.175.08:11:31.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:31.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:11:31.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:11:31.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:11:31.71$vc4f8/vb=4,4 2006.175.08:11:31.71#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.175.08:11:31.71#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.175.08:11:31.71#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:31.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:31.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:31.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:31.77#ibcon#enter wrdev, iclass 35, count 2 2006.175.08:11:31.77#ibcon#first serial, iclass 35, count 2 2006.175.08:11:31.77#ibcon#enter sib2, iclass 35, count 2 2006.175.08:11:31.77#ibcon#flushed, iclass 35, count 2 2006.175.08:11:31.77#ibcon#about to write, iclass 35, count 2 2006.175.08:11:31.77#ibcon#wrote, iclass 35, count 2 2006.175.08:11:31.77#ibcon#about to read 3, iclass 35, count 2 2006.175.08:11:31.79#ibcon#read 3, iclass 35, count 2 2006.175.08:11:31.79#ibcon#about to read 4, iclass 35, count 2 2006.175.08:11:31.79#ibcon#read 4, iclass 35, count 2 2006.175.08:11:31.79#ibcon#about to read 5, iclass 35, count 2 2006.175.08:11:31.79#ibcon#read 5, iclass 35, count 2 2006.175.08:11:31.79#ibcon#about to read 6, iclass 35, count 2 2006.175.08:11:31.79#ibcon#read 6, iclass 35, count 2 2006.175.08:11:31.79#ibcon#end of sib2, iclass 35, count 2 2006.175.08:11:31.79#ibcon#*mode == 0, iclass 35, count 2 2006.175.08:11:31.79#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.175.08:11:31.79#ibcon#[27=AT04-04\r\n] 2006.175.08:11:31.79#ibcon#*before write, iclass 35, count 2 2006.175.08:11:31.79#ibcon#enter sib2, iclass 35, count 2 2006.175.08:11:31.79#ibcon#flushed, iclass 35, count 2 2006.175.08:11:31.79#ibcon#about to write, iclass 35, count 2 2006.175.08:11:31.79#ibcon#wrote, iclass 35, count 2 2006.175.08:11:31.79#ibcon#about to read 3, iclass 35, count 2 2006.175.08:11:31.82#ibcon#read 3, iclass 35, count 2 2006.175.08:11:31.82#ibcon#about to read 4, iclass 35, count 2 2006.175.08:11:31.82#ibcon#read 4, iclass 35, count 2 2006.175.08:11:31.82#ibcon#about to read 5, iclass 35, count 2 2006.175.08:11:31.82#ibcon#read 5, iclass 35, count 2 2006.175.08:11:31.82#ibcon#about to read 6, iclass 35, count 2 2006.175.08:11:31.82#ibcon#read 6, iclass 35, count 2 2006.175.08:11:31.82#ibcon#end of sib2, iclass 35, count 2 2006.175.08:11:31.82#ibcon#*after write, iclass 35, count 2 2006.175.08:11:31.82#ibcon#*before return 0, iclass 35, count 2 2006.175.08:11:31.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:31.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:11:31.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.175.08:11:31.82#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:31.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:31.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:31.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:31.94#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:11:31.94#ibcon#first serial, iclass 35, count 0 2006.175.08:11:31.94#ibcon#enter sib2, iclass 35, count 0 2006.175.08:11:31.94#ibcon#flushed, iclass 35, count 0 2006.175.08:11:31.94#ibcon#about to write, iclass 35, count 0 2006.175.08:11:31.94#ibcon#wrote, iclass 35, count 0 2006.175.08:11:31.94#ibcon#about to read 3, iclass 35, count 0 2006.175.08:11:31.96#ibcon#read 3, iclass 35, count 0 2006.175.08:11:31.96#ibcon#about to read 4, iclass 35, count 0 2006.175.08:11:31.96#ibcon#read 4, iclass 35, count 0 2006.175.08:11:31.96#ibcon#about to read 5, iclass 35, count 0 2006.175.08:11:31.96#ibcon#read 5, iclass 35, count 0 2006.175.08:11:31.96#ibcon#about to read 6, iclass 35, count 0 2006.175.08:11:31.96#ibcon#read 6, iclass 35, count 0 2006.175.08:11:31.96#ibcon#end of sib2, iclass 35, count 0 2006.175.08:11:31.96#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:11:31.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:11:31.96#ibcon#[27=USB\r\n] 2006.175.08:11:31.96#ibcon#*before write, iclass 35, count 0 2006.175.08:11:31.96#ibcon#enter sib2, iclass 35, count 0 2006.175.08:11:31.96#ibcon#flushed, iclass 35, count 0 2006.175.08:11:31.96#ibcon#about to write, iclass 35, count 0 2006.175.08:11:31.96#ibcon#wrote, iclass 35, count 0 2006.175.08:11:31.96#ibcon#about to read 3, iclass 35, count 0 2006.175.08:11:31.99#ibcon#read 3, iclass 35, count 0 2006.175.08:11:31.99#ibcon#about to read 4, iclass 35, count 0 2006.175.08:11:31.99#ibcon#read 4, iclass 35, count 0 2006.175.08:11:31.99#ibcon#about to read 5, iclass 35, count 0 2006.175.08:11:31.99#ibcon#read 5, iclass 35, count 0 2006.175.08:11:31.99#ibcon#about to read 6, iclass 35, count 0 2006.175.08:11:31.99#ibcon#read 6, iclass 35, count 0 2006.175.08:11:31.99#ibcon#end of sib2, iclass 35, count 0 2006.175.08:11:31.99#ibcon#*after write, iclass 35, count 0 2006.175.08:11:31.99#ibcon#*before return 0, iclass 35, count 0 2006.175.08:11:31.99#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:31.99#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:11:31.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:11:31.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:11:31.99$vc4f8/vblo=5,744.99 2006.175.08:11:31.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.08:11:31.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.08:11:31.99#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:31.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:31.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:31.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:31.99#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:11:31.99#ibcon#first serial, iclass 37, count 0 2006.175.08:11:31.99#ibcon#enter sib2, iclass 37, count 0 2006.175.08:11:31.99#ibcon#flushed, iclass 37, count 0 2006.175.08:11:31.99#ibcon#about to write, iclass 37, count 0 2006.175.08:11:31.99#ibcon#wrote, iclass 37, count 0 2006.175.08:11:31.99#ibcon#about to read 3, iclass 37, count 0 2006.175.08:11:32.01#ibcon#read 3, iclass 37, count 0 2006.175.08:11:32.01#ibcon#about to read 4, iclass 37, count 0 2006.175.08:11:32.01#ibcon#read 4, iclass 37, count 0 2006.175.08:11:32.01#ibcon#about to read 5, iclass 37, count 0 2006.175.08:11:32.01#ibcon#read 5, iclass 37, count 0 2006.175.08:11:32.01#ibcon#about to read 6, iclass 37, count 0 2006.175.08:11:32.01#ibcon#read 6, iclass 37, count 0 2006.175.08:11:32.01#ibcon#end of sib2, iclass 37, count 0 2006.175.08:11:32.01#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:11:32.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:11:32.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:11:32.01#ibcon#*before write, iclass 37, count 0 2006.175.08:11:32.01#ibcon#enter sib2, iclass 37, count 0 2006.175.08:11:32.01#ibcon#flushed, iclass 37, count 0 2006.175.08:11:32.01#ibcon#about to write, iclass 37, count 0 2006.175.08:11:32.01#ibcon#wrote, iclass 37, count 0 2006.175.08:11:32.01#ibcon#about to read 3, iclass 37, count 0 2006.175.08:11:32.05#ibcon#read 3, iclass 37, count 0 2006.175.08:11:32.05#ibcon#about to read 4, iclass 37, count 0 2006.175.08:11:32.05#ibcon#read 4, iclass 37, count 0 2006.175.08:11:32.05#ibcon#about to read 5, iclass 37, count 0 2006.175.08:11:32.05#ibcon#read 5, iclass 37, count 0 2006.175.08:11:32.05#ibcon#about to read 6, iclass 37, count 0 2006.175.08:11:32.05#ibcon#read 6, iclass 37, count 0 2006.175.08:11:32.05#ibcon#end of sib2, iclass 37, count 0 2006.175.08:11:32.05#ibcon#*after write, iclass 37, count 0 2006.175.08:11:32.05#ibcon#*before return 0, iclass 37, count 0 2006.175.08:11:32.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:32.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:11:32.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:11:32.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:11:32.05$vc4f8/vb=5,4 2006.175.08:11:32.05#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.175.08:11:32.05#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.175.08:11:32.05#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:32.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:32.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:32.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:32.11#ibcon#enter wrdev, iclass 39, count 2 2006.175.08:11:32.11#ibcon#first serial, iclass 39, count 2 2006.175.08:11:32.11#ibcon#enter sib2, iclass 39, count 2 2006.175.08:11:32.11#ibcon#flushed, iclass 39, count 2 2006.175.08:11:32.11#ibcon#about to write, iclass 39, count 2 2006.175.08:11:32.11#ibcon#wrote, iclass 39, count 2 2006.175.08:11:32.11#ibcon#about to read 3, iclass 39, count 2 2006.175.08:11:32.13#ibcon#read 3, iclass 39, count 2 2006.175.08:11:32.13#ibcon#about to read 4, iclass 39, count 2 2006.175.08:11:32.13#ibcon#read 4, iclass 39, count 2 2006.175.08:11:32.13#ibcon#about to read 5, iclass 39, count 2 2006.175.08:11:32.13#ibcon#read 5, iclass 39, count 2 2006.175.08:11:32.13#ibcon#about to read 6, iclass 39, count 2 2006.175.08:11:32.13#ibcon#read 6, iclass 39, count 2 2006.175.08:11:32.13#ibcon#end of sib2, iclass 39, count 2 2006.175.08:11:32.13#ibcon#*mode == 0, iclass 39, count 2 2006.175.08:11:32.13#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.175.08:11:32.13#ibcon#[27=AT05-04\r\n] 2006.175.08:11:32.13#ibcon#*before write, iclass 39, count 2 2006.175.08:11:32.13#ibcon#enter sib2, iclass 39, count 2 2006.175.08:11:32.13#ibcon#flushed, iclass 39, count 2 2006.175.08:11:32.13#ibcon#about to write, iclass 39, count 2 2006.175.08:11:32.13#ibcon#wrote, iclass 39, count 2 2006.175.08:11:32.13#ibcon#about to read 3, iclass 39, count 2 2006.175.08:11:32.16#ibcon#read 3, iclass 39, count 2 2006.175.08:11:32.16#ibcon#about to read 4, iclass 39, count 2 2006.175.08:11:32.16#ibcon#read 4, iclass 39, count 2 2006.175.08:11:32.16#ibcon#about to read 5, iclass 39, count 2 2006.175.08:11:32.16#ibcon#read 5, iclass 39, count 2 2006.175.08:11:32.16#ibcon#about to read 6, iclass 39, count 2 2006.175.08:11:32.16#ibcon#read 6, iclass 39, count 2 2006.175.08:11:32.16#ibcon#end of sib2, iclass 39, count 2 2006.175.08:11:32.16#ibcon#*after write, iclass 39, count 2 2006.175.08:11:32.16#ibcon#*before return 0, iclass 39, count 2 2006.175.08:11:32.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:32.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:11:32.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.175.08:11:32.16#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:32.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:32.28#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:32.28#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:32.28#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:11:32.28#ibcon#first serial, iclass 39, count 0 2006.175.08:11:32.28#ibcon#enter sib2, iclass 39, count 0 2006.175.08:11:32.28#ibcon#flushed, iclass 39, count 0 2006.175.08:11:32.28#ibcon#about to write, iclass 39, count 0 2006.175.08:11:32.28#ibcon#wrote, iclass 39, count 0 2006.175.08:11:32.28#ibcon#about to read 3, iclass 39, count 0 2006.175.08:11:32.30#ibcon#read 3, iclass 39, count 0 2006.175.08:11:32.30#ibcon#about to read 4, iclass 39, count 0 2006.175.08:11:32.30#ibcon#read 4, iclass 39, count 0 2006.175.08:11:32.30#ibcon#about to read 5, iclass 39, count 0 2006.175.08:11:32.30#ibcon#read 5, iclass 39, count 0 2006.175.08:11:32.30#ibcon#about to read 6, iclass 39, count 0 2006.175.08:11:32.30#ibcon#read 6, iclass 39, count 0 2006.175.08:11:32.30#ibcon#end of sib2, iclass 39, count 0 2006.175.08:11:32.30#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:11:32.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:11:32.30#ibcon#[27=USB\r\n] 2006.175.08:11:32.30#ibcon#*before write, iclass 39, count 0 2006.175.08:11:32.30#ibcon#enter sib2, iclass 39, count 0 2006.175.08:11:32.30#ibcon#flushed, iclass 39, count 0 2006.175.08:11:32.30#ibcon#about to write, iclass 39, count 0 2006.175.08:11:32.30#ibcon#wrote, iclass 39, count 0 2006.175.08:11:32.30#ibcon#about to read 3, iclass 39, count 0 2006.175.08:11:32.33#ibcon#read 3, iclass 39, count 0 2006.175.08:11:32.33#ibcon#about to read 4, iclass 39, count 0 2006.175.08:11:32.33#ibcon#read 4, iclass 39, count 0 2006.175.08:11:32.33#ibcon#about to read 5, iclass 39, count 0 2006.175.08:11:32.33#ibcon#read 5, iclass 39, count 0 2006.175.08:11:32.33#ibcon#about to read 6, iclass 39, count 0 2006.175.08:11:32.33#ibcon#read 6, iclass 39, count 0 2006.175.08:11:32.33#ibcon#end of sib2, iclass 39, count 0 2006.175.08:11:32.33#ibcon#*after write, iclass 39, count 0 2006.175.08:11:32.33#ibcon#*before return 0, iclass 39, count 0 2006.175.08:11:32.33#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:32.33#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:11:32.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:11:32.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:11:32.33$vc4f8/vblo=6,752.99 2006.175.08:11:32.33#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.08:11:32.33#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.08:11:32.33#ibcon#ireg 17 cls_cnt 0 2006.175.08:11:32.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:32.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:32.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:32.33#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:11:32.33#ibcon#first serial, iclass 3, count 0 2006.175.08:11:32.33#ibcon#enter sib2, iclass 3, count 0 2006.175.08:11:32.33#ibcon#flushed, iclass 3, count 0 2006.175.08:11:32.33#ibcon#about to write, iclass 3, count 0 2006.175.08:11:32.33#ibcon#wrote, iclass 3, count 0 2006.175.08:11:32.33#ibcon#about to read 3, iclass 3, count 0 2006.175.08:11:32.35#ibcon#read 3, iclass 3, count 0 2006.175.08:11:32.35#ibcon#about to read 4, iclass 3, count 0 2006.175.08:11:32.35#ibcon#read 4, iclass 3, count 0 2006.175.08:11:32.35#ibcon#about to read 5, iclass 3, count 0 2006.175.08:11:32.35#ibcon#read 5, iclass 3, count 0 2006.175.08:11:32.35#ibcon#about to read 6, iclass 3, count 0 2006.175.08:11:32.35#ibcon#read 6, iclass 3, count 0 2006.175.08:11:32.35#ibcon#end of sib2, iclass 3, count 0 2006.175.08:11:32.35#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:11:32.35#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:11:32.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:11:32.35#ibcon#*before write, iclass 3, count 0 2006.175.08:11:32.35#ibcon#enter sib2, iclass 3, count 0 2006.175.08:11:32.35#ibcon#flushed, iclass 3, count 0 2006.175.08:11:32.35#ibcon#about to write, iclass 3, count 0 2006.175.08:11:32.35#ibcon#wrote, iclass 3, count 0 2006.175.08:11:32.35#ibcon#about to read 3, iclass 3, count 0 2006.175.08:11:32.39#ibcon#read 3, iclass 3, count 0 2006.175.08:11:32.39#ibcon#about to read 4, iclass 3, count 0 2006.175.08:11:32.39#ibcon#read 4, iclass 3, count 0 2006.175.08:11:32.39#ibcon#about to read 5, iclass 3, count 0 2006.175.08:11:32.39#ibcon#read 5, iclass 3, count 0 2006.175.08:11:32.39#ibcon#about to read 6, iclass 3, count 0 2006.175.08:11:32.39#ibcon#read 6, iclass 3, count 0 2006.175.08:11:32.39#ibcon#end of sib2, iclass 3, count 0 2006.175.08:11:32.39#ibcon#*after write, iclass 3, count 0 2006.175.08:11:32.39#ibcon#*before return 0, iclass 3, count 0 2006.175.08:11:32.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:32.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:11:32.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:11:32.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:11:32.39$vc4f8/vb=6,4 2006.175.08:11:32.39#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.175.08:11:32.39#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.175.08:11:32.39#ibcon#ireg 11 cls_cnt 2 2006.175.08:11:32.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:32.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:32.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:32.45#ibcon#enter wrdev, iclass 5, count 2 2006.175.08:11:32.45#ibcon#first serial, iclass 5, count 2 2006.175.08:11:32.45#ibcon#enter sib2, iclass 5, count 2 2006.175.08:11:32.45#ibcon#flushed, iclass 5, count 2 2006.175.08:11:32.45#ibcon#about to write, iclass 5, count 2 2006.175.08:11:32.45#ibcon#wrote, iclass 5, count 2 2006.175.08:11:32.45#ibcon#about to read 3, iclass 5, count 2 2006.175.08:11:32.47#ibcon#read 3, iclass 5, count 2 2006.175.08:11:32.47#ibcon#about to read 4, iclass 5, count 2 2006.175.08:11:32.47#ibcon#read 4, iclass 5, count 2 2006.175.08:11:32.47#ibcon#about to read 5, iclass 5, count 2 2006.175.08:11:32.47#ibcon#read 5, iclass 5, count 2 2006.175.08:11:32.47#ibcon#about to read 6, iclass 5, count 2 2006.175.08:11:32.47#ibcon#read 6, iclass 5, count 2 2006.175.08:11:32.47#ibcon#end of sib2, iclass 5, count 2 2006.175.08:11:32.47#ibcon#*mode == 0, iclass 5, count 2 2006.175.08:11:32.47#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.175.08:11:32.47#ibcon#[27=AT06-04\r\n] 2006.175.08:11:32.47#ibcon#*before write, iclass 5, count 2 2006.175.08:11:32.47#ibcon#enter sib2, iclass 5, count 2 2006.175.08:11:32.47#ibcon#flushed, iclass 5, count 2 2006.175.08:11:32.47#ibcon#about to write, iclass 5, count 2 2006.175.08:11:32.47#ibcon#wrote, iclass 5, count 2 2006.175.08:11:32.47#ibcon#about to read 3, iclass 5, count 2 2006.175.08:11:32.50#ibcon#read 3, iclass 5, count 2 2006.175.08:11:32.50#ibcon#about to read 4, iclass 5, count 2 2006.175.08:11:32.50#ibcon#read 4, iclass 5, count 2 2006.175.08:11:32.50#ibcon#about to read 5, iclass 5, count 2 2006.175.08:11:32.50#ibcon#read 5, iclass 5, count 2 2006.175.08:11:32.50#ibcon#about to read 6, iclass 5, count 2 2006.175.08:11:32.50#ibcon#read 6, iclass 5, count 2 2006.175.08:11:32.50#ibcon#end of sib2, iclass 5, count 2 2006.175.08:11:32.50#ibcon#*after write, iclass 5, count 2 2006.175.08:11:32.50#ibcon#*before return 0, iclass 5, count 2 2006.175.08:11:32.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:32.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:11:32.50#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.175.08:11:32.50#ibcon#ireg 7 cls_cnt 0 2006.175.08:11:32.50#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:32.62#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:32.62#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:32.62#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:11:32.62#ibcon#first serial, iclass 5, count 0 2006.175.08:11:32.62#ibcon#enter sib2, iclass 5, count 0 2006.175.08:11:32.62#ibcon#flushed, iclass 5, count 0 2006.175.08:11:32.62#ibcon#about to write, iclass 5, count 0 2006.175.08:11:32.62#ibcon#wrote, iclass 5, count 0 2006.175.08:11:32.62#ibcon#about to read 3, iclass 5, count 0 2006.175.08:11:32.64#ibcon#read 3, iclass 5, count 0 2006.175.08:11:32.64#ibcon#about to read 4, iclass 5, count 0 2006.175.08:11:32.64#ibcon#read 4, iclass 5, count 0 2006.175.08:11:32.64#ibcon#about to read 5, iclass 5, count 0 2006.175.08:11:32.64#ibcon#read 5, iclass 5, count 0 2006.175.08:11:32.64#ibcon#about to read 6, iclass 5, count 0 2006.175.08:11:32.64#ibcon#read 6, iclass 5, count 0 2006.175.08:11:32.64#ibcon#end of sib2, iclass 5, count 0 2006.175.08:11:32.64#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:11:32.64#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:11:32.64#ibcon#[27=USB\r\n] 2006.175.08:11:32.64#ibcon#*before write, iclass 5, count 0 2006.175.08:11:32.64#ibcon#enter sib2, iclass 5, count 0 2006.175.08:11:32.64#ibcon#flushed, iclass 5, count 0 2006.175.08:11:32.64#ibcon#about to write, iclass 5, count 0 2006.175.08:11:32.64#ibcon#wrote, iclass 5, count 0 2006.175.08:11:32.64#ibcon#about to read 3, iclass 5, count 0 2006.175.08:11:32.67#ibcon#read 3, iclass 5, count 0 2006.175.08:11:32.67#ibcon#about to read 4, iclass 5, count 0 2006.175.08:11:32.67#ibcon#read 4, iclass 5, count 0 2006.175.08:11:32.67#ibcon#about to read 5, iclass 5, count 0 2006.175.08:11:32.67#ibcon#read 5, iclass 5, count 0 2006.175.08:11:32.67#ibcon#about to read 6, iclass 5, count 0 2006.175.08:11:32.67#ibcon#read 6, iclass 5, count 0 2006.175.08:11:32.67#ibcon#end of sib2, iclass 5, count 0 2006.175.08:11:32.67#ibcon#*after write, iclass 5, count 0 2006.175.08:11:32.67#ibcon#*before return 0, iclass 5, count 0 2006.175.08:11:32.67#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:32.67#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:11:32.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:11:32.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:11:32.67$vc4f8/vabw=wide 2006.175.08:11:32.67#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.08:11:32.67#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.08:11:32.67#ibcon#ireg 8 cls_cnt 0 2006.175.08:11:32.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:32.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:32.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:32.67#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:11:32.67#ibcon#first serial, iclass 7, count 0 2006.175.08:11:32.67#ibcon#enter sib2, iclass 7, count 0 2006.175.08:11:32.67#ibcon#flushed, iclass 7, count 0 2006.175.08:11:32.67#ibcon#about to write, iclass 7, count 0 2006.175.08:11:32.67#ibcon#wrote, iclass 7, count 0 2006.175.08:11:32.67#ibcon#about to read 3, iclass 7, count 0 2006.175.08:11:32.69#ibcon#read 3, iclass 7, count 0 2006.175.08:11:32.69#ibcon#about to read 4, iclass 7, count 0 2006.175.08:11:32.69#ibcon#read 4, iclass 7, count 0 2006.175.08:11:32.69#ibcon#about to read 5, iclass 7, count 0 2006.175.08:11:32.69#ibcon#read 5, iclass 7, count 0 2006.175.08:11:32.69#ibcon#about to read 6, iclass 7, count 0 2006.175.08:11:32.69#ibcon#read 6, iclass 7, count 0 2006.175.08:11:32.69#ibcon#end of sib2, iclass 7, count 0 2006.175.08:11:32.69#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:11:32.69#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:11:32.69#ibcon#[25=BW32\r\n] 2006.175.08:11:32.69#ibcon#*before write, iclass 7, count 0 2006.175.08:11:32.69#ibcon#enter sib2, iclass 7, count 0 2006.175.08:11:32.69#ibcon#flushed, iclass 7, count 0 2006.175.08:11:32.69#ibcon#about to write, iclass 7, count 0 2006.175.08:11:32.69#ibcon#wrote, iclass 7, count 0 2006.175.08:11:32.69#ibcon#about to read 3, iclass 7, count 0 2006.175.08:11:32.72#ibcon#read 3, iclass 7, count 0 2006.175.08:11:32.72#ibcon#about to read 4, iclass 7, count 0 2006.175.08:11:32.72#ibcon#read 4, iclass 7, count 0 2006.175.08:11:32.72#ibcon#about to read 5, iclass 7, count 0 2006.175.08:11:32.72#ibcon#read 5, iclass 7, count 0 2006.175.08:11:32.72#ibcon#about to read 6, iclass 7, count 0 2006.175.08:11:32.72#ibcon#read 6, iclass 7, count 0 2006.175.08:11:32.72#ibcon#end of sib2, iclass 7, count 0 2006.175.08:11:32.72#ibcon#*after write, iclass 7, count 0 2006.175.08:11:32.72#ibcon#*before return 0, iclass 7, count 0 2006.175.08:11:32.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:32.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:11:32.72#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:11:32.72#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:11:32.72$vc4f8/vbbw=wide 2006.175.08:11:32.72#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.08:11:32.72#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.08:11:32.72#ibcon#ireg 8 cls_cnt 0 2006.175.08:11:32.72#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:11:32.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:11:32.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:11:32.79#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:11:32.79#ibcon#first serial, iclass 11, count 0 2006.175.08:11:32.79#ibcon#enter sib2, iclass 11, count 0 2006.175.08:11:32.79#ibcon#flushed, iclass 11, count 0 2006.175.08:11:32.79#ibcon#about to write, iclass 11, count 0 2006.175.08:11:32.79#ibcon#wrote, iclass 11, count 0 2006.175.08:11:32.79#ibcon#about to read 3, iclass 11, count 0 2006.175.08:11:32.81#ibcon#read 3, iclass 11, count 0 2006.175.08:11:32.81#ibcon#about to read 4, iclass 11, count 0 2006.175.08:11:32.81#ibcon#read 4, iclass 11, count 0 2006.175.08:11:32.81#ibcon#about to read 5, iclass 11, count 0 2006.175.08:11:32.81#ibcon#read 5, iclass 11, count 0 2006.175.08:11:32.81#ibcon#about to read 6, iclass 11, count 0 2006.175.08:11:32.81#ibcon#read 6, iclass 11, count 0 2006.175.08:11:32.81#ibcon#end of sib2, iclass 11, count 0 2006.175.08:11:32.81#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:11:32.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:11:32.81#ibcon#[27=BW32\r\n] 2006.175.08:11:32.81#ibcon#*before write, iclass 11, count 0 2006.175.08:11:32.81#ibcon#enter sib2, iclass 11, count 0 2006.175.08:11:32.81#ibcon#flushed, iclass 11, count 0 2006.175.08:11:32.81#ibcon#about to write, iclass 11, count 0 2006.175.08:11:32.81#ibcon#wrote, iclass 11, count 0 2006.175.08:11:32.81#ibcon#about to read 3, iclass 11, count 0 2006.175.08:11:32.84#ibcon#read 3, iclass 11, count 0 2006.175.08:11:32.84#ibcon#about to read 4, iclass 11, count 0 2006.175.08:11:32.84#ibcon#read 4, iclass 11, count 0 2006.175.08:11:32.84#ibcon#about to read 5, iclass 11, count 0 2006.175.08:11:32.84#ibcon#read 5, iclass 11, count 0 2006.175.08:11:32.84#ibcon#about to read 6, iclass 11, count 0 2006.175.08:11:32.84#ibcon#read 6, iclass 11, count 0 2006.175.08:11:32.84#ibcon#end of sib2, iclass 11, count 0 2006.175.08:11:32.84#ibcon#*after write, iclass 11, count 0 2006.175.08:11:32.84#ibcon#*before return 0, iclass 11, count 0 2006.175.08:11:32.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:11:32.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:11:32.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:11:32.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:11:32.84$4f8m12a/ifd4f 2006.175.08:11:32.84$ifd4f/lo= 2006.175.08:11:32.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:11:32.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:11:32.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:11:32.84$ifd4f/patch= 2006.175.08:11:32.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:11:32.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:11:32.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:11:32.84$4f8m12a/"form=m,16.000,1:2 2006.175.08:11:32.84$4f8m12a/"tpicd 2006.175.08:11:32.84$4f8m12a/echo=off 2006.175.08:11:32.84$4f8m12a/xlog=off 2006.175.08:11:32.84:!2006.175.08:12:00 2006.175.08:11:41.14#trakl#Source acquired 2006.175.08:11:42.14#flagr#flagr/antenna,acquired 2006.175.08:12:00.00:preob 2006.175.08:12:01.14/onsource/TRACKING 2006.175.08:12:01.14:!2006.175.08:12:10 2006.175.08:12:10.00:data_valid=on 2006.175.08:12:10.00:midob 2006.175.08:12:10.14/onsource/TRACKING 2006.175.08:12:10.14/wx/25.78,1007.3,71 2006.175.08:12:10.33/cable/+6.4792E-03 2006.175.08:12:11.42/va/01,08,usb,yes,29,30 2006.175.08:12:11.42/va/02,07,usb,yes,29,30 2006.175.08:12:11.42/va/03,06,usb,yes,31,31 2006.175.08:12:11.42/va/04,07,usb,yes,30,32 2006.175.08:12:11.42/va/05,07,usb,yes,30,32 2006.175.08:12:11.42/va/06,06,usb,yes,29,29 2006.175.08:12:11.42/va/07,06,usb,yes,30,29 2006.175.08:12:11.42/va/08,06,usb,yes,32,31 2006.175.08:12:11.65/valo/01,532.99,yes,locked 2006.175.08:12:11.65/valo/02,572.99,yes,locked 2006.175.08:12:11.65/valo/03,672.99,yes,locked 2006.175.08:12:11.65/valo/04,832.99,yes,locked 2006.175.08:12:11.65/valo/05,652.99,yes,locked 2006.175.08:12:11.65/valo/06,772.99,yes,locked 2006.175.08:12:11.65/valo/07,832.99,yes,locked 2006.175.08:12:11.65/valo/08,852.99,yes,locked 2006.175.08:12:12.74/vb/01,04,usb,yes,29,28 2006.175.08:12:12.74/vb/02,04,usb,yes,31,33 2006.175.08:12:12.74/vb/03,04,usb,yes,27,31 2006.175.08:12:12.74/vb/04,04,usb,yes,28,28 2006.175.08:12:12.74/vb/05,04,usb,yes,27,31 2006.175.08:12:12.74/vb/06,04,usb,yes,28,30 2006.175.08:12:12.74/vb/07,04,usb,yes,30,30 2006.175.08:12:12.74/vb/08,04,usb,yes,27,31 2006.175.08:12:12.97/vblo/01,632.99,yes,locked 2006.175.08:12:12.97/vblo/02,640.99,yes,locked 2006.175.08:12:12.97/vblo/03,656.99,yes,locked 2006.175.08:12:12.97/vblo/04,712.99,yes,locked 2006.175.08:12:12.97/vblo/05,744.99,yes,locked 2006.175.08:12:12.97/vblo/06,752.99,yes,locked 2006.175.08:12:12.97/vblo/07,734.99,yes,locked 2006.175.08:12:12.97/vblo/08,744.99,yes,locked 2006.175.08:12:13.12/vabw/8 2006.175.08:12:13.27/vbbw/8 2006.175.08:12:13.36/xfe/off,on,15.0 2006.175.08:12:13.73/ifatt/23,28,28,28 2006.175.08:12:14.07/fmout-gps/S +3.80E-07 2006.175.08:12:14.15:!2006.175.08:13:10 2006.175.08:13:10.00:data_valid=off 2006.175.08:13:10.00:postob 2006.175.08:13:10.21/cable/+6.4780E-03 2006.175.08:13:10.21/wx/25.77,1007.3,71 2006.175.08:13:11.07/fmout-gps/S +3.81E-07 2006.175.08:13:11.07:scan_name=175-0814,k06175,60 2006.175.08:13:11.08:source=oj287,085448.87,200630.6,2000.0,ccw 2006.175.08:13:11.14#flagr#flagr/antenna,new-source 2006.175.08:13:12.14:checkk5 2006.175.08:13:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:13:12.91/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:13:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:13:13.67/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:13:14.04/chk_obsdata//k5ts1/T1750812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:13:14.41/chk_obsdata//k5ts2/T1750812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:13:14.78/chk_obsdata//k5ts3/T1750812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:13:15.15/chk_obsdata//k5ts4/T1750812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:13:15.84/k5log//k5ts1_log_newline 2006.175.08:13:16.53/k5log//k5ts2_log_newline 2006.175.08:13:17.24/k5log//k5ts3_log_newline 2006.175.08:13:17.93/k5log//k5ts4_log_newline 2006.175.08:13:17.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:13:17.96:4f8m12a=2 2006.175.08:13:17.96$4f8m12a/echo=on 2006.175.08:13:17.96$4f8m12a/pcalon 2006.175.08:13:17.96$pcalon/"no phase cal control is implemented here 2006.175.08:13:17.96$4f8m12a/"tpicd=stop 2006.175.08:13:17.96$4f8m12a/vc4f8 2006.175.08:13:17.96$vc4f8/valo=1,532.99 2006.175.08:13:17.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.08:13:17.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.08:13:17.96#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:17.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:17.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:17.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:17.96#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:13:17.96#ibcon#first serial, iclass 18, count 0 2006.175.08:13:17.96#ibcon#enter sib2, iclass 18, count 0 2006.175.08:13:17.96#ibcon#flushed, iclass 18, count 0 2006.175.08:13:17.96#ibcon#about to write, iclass 18, count 0 2006.175.08:13:17.96#ibcon#wrote, iclass 18, count 0 2006.175.08:13:17.96#ibcon#about to read 3, iclass 18, count 0 2006.175.08:13:18.01#ibcon#read 3, iclass 18, count 0 2006.175.08:13:18.01#ibcon#about to read 4, iclass 18, count 0 2006.175.08:13:18.01#ibcon#read 4, iclass 18, count 0 2006.175.08:13:18.01#ibcon#about to read 5, iclass 18, count 0 2006.175.08:13:18.01#ibcon#read 5, iclass 18, count 0 2006.175.08:13:18.01#ibcon#about to read 6, iclass 18, count 0 2006.175.08:13:18.01#ibcon#read 6, iclass 18, count 0 2006.175.08:13:18.01#ibcon#end of sib2, iclass 18, count 0 2006.175.08:13:18.01#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:13:18.01#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:13:18.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:13:18.01#ibcon#*before write, iclass 18, count 0 2006.175.08:13:18.01#ibcon#enter sib2, iclass 18, count 0 2006.175.08:13:18.01#ibcon#flushed, iclass 18, count 0 2006.175.08:13:18.01#ibcon#about to write, iclass 18, count 0 2006.175.08:13:18.01#ibcon#wrote, iclass 18, count 0 2006.175.08:13:18.01#ibcon#about to read 3, iclass 18, count 0 2006.175.08:13:18.05#ibcon#read 3, iclass 18, count 0 2006.175.08:13:18.05#ibcon#about to read 4, iclass 18, count 0 2006.175.08:13:18.05#ibcon#read 4, iclass 18, count 0 2006.175.08:13:18.05#ibcon#about to read 5, iclass 18, count 0 2006.175.08:13:18.05#ibcon#read 5, iclass 18, count 0 2006.175.08:13:18.05#ibcon#about to read 6, iclass 18, count 0 2006.175.08:13:18.05#ibcon#read 6, iclass 18, count 0 2006.175.08:13:18.05#ibcon#end of sib2, iclass 18, count 0 2006.175.08:13:18.05#ibcon#*after write, iclass 18, count 0 2006.175.08:13:18.05#ibcon#*before return 0, iclass 18, count 0 2006.175.08:13:18.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:18.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:18.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:13:18.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:13:18.05$vc4f8/va=1,8 2006.175.08:13:18.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.175.08:13:18.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.175.08:13:18.05#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:18.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:18.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:18.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:18.05#ibcon#enter wrdev, iclass 20, count 2 2006.175.08:13:18.05#ibcon#first serial, iclass 20, count 2 2006.175.08:13:18.05#ibcon#enter sib2, iclass 20, count 2 2006.175.08:13:18.05#ibcon#flushed, iclass 20, count 2 2006.175.08:13:18.05#ibcon#about to write, iclass 20, count 2 2006.175.08:13:18.05#ibcon#wrote, iclass 20, count 2 2006.175.08:13:18.05#ibcon#about to read 3, iclass 20, count 2 2006.175.08:13:18.07#ibcon#read 3, iclass 20, count 2 2006.175.08:13:18.07#ibcon#about to read 4, iclass 20, count 2 2006.175.08:13:18.07#ibcon#read 4, iclass 20, count 2 2006.175.08:13:18.07#ibcon#about to read 5, iclass 20, count 2 2006.175.08:13:18.07#ibcon#read 5, iclass 20, count 2 2006.175.08:13:18.07#ibcon#about to read 6, iclass 20, count 2 2006.175.08:13:18.07#ibcon#read 6, iclass 20, count 2 2006.175.08:13:18.07#ibcon#end of sib2, iclass 20, count 2 2006.175.08:13:18.07#ibcon#*mode == 0, iclass 20, count 2 2006.175.08:13:18.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.175.08:13:18.07#ibcon#[25=AT01-08\r\n] 2006.175.08:13:18.07#ibcon#*before write, iclass 20, count 2 2006.175.08:13:18.07#ibcon#enter sib2, iclass 20, count 2 2006.175.08:13:18.07#ibcon#flushed, iclass 20, count 2 2006.175.08:13:18.07#ibcon#about to write, iclass 20, count 2 2006.175.08:13:18.07#ibcon#wrote, iclass 20, count 2 2006.175.08:13:18.07#ibcon#about to read 3, iclass 20, count 2 2006.175.08:13:18.10#ibcon#read 3, iclass 20, count 2 2006.175.08:13:18.10#ibcon#about to read 4, iclass 20, count 2 2006.175.08:13:18.10#ibcon#read 4, iclass 20, count 2 2006.175.08:13:18.10#ibcon#about to read 5, iclass 20, count 2 2006.175.08:13:18.10#ibcon#read 5, iclass 20, count 2 2006.175.08:13:18.10#ibcon#about to read 6, iclass 20, count 2 2006.175.08:13:18.10#ibcon#read 6, iclass 20, count 2 2006.175.08:13:18.10#ibcon#end of sib2, iclass 20, count 2 2006.175.08:13:18.10#ibcon#*after write, iclass 20, count 2 2006.175.08:13:18.10#ibcon#*before return 0, iclass 20, count 2 2006.175.08:13:18.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:18.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:18.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.175.08:13:18.10#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:18.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:18.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:18.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:18.22#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:13:18.22#ibcon#first serial, iclass 20, count 0 2006.175.08:13:18.22#ibcon#enter sib2, iclass 20, count 0 2006.175.08:13:18.22#ibcon#flushed, iclass 20, count 0 2006.175.08:13:18.22#ibcon#about to write, iclass 20, count 0 2006.175.08:13:18.22#ibcon#wrote, iclass 20, count 0 2006.175.08:13:18.22#ibcon#about to read 3, iclass 20, count 0 2006.175.08:13:18.24#ibcon#read 3, iclass 20, count 0 2006.175.08:13:18.24#ibcon#about to read 4, iclass 20, count 0 2006.175.08:13:18.24#ibcon#read 4, iclass 20, count 0 2006.175.08:13:18.24#ibcon#about to read 5, iclass 20, count 0 2006.175.08:13:18.24#ibcon#read 5, iclass 20, count 0 2006.175.08:13:18.24#ibcon#about to read 6, iclass 20, count 0 2006.175.08:13:18.24#ibcon#read 6, iclass 20, count 0 2006.175.08:13:18.24#ibcon#end of sib2, iclass 20, count 0 2006.175.08:13:18.24#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:13:18.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:13:18.24#ibcon#[25=USB\r\n] 2006.175.08:13:18.24#ibcon#*before write, iclass 20, count 0 2006.175.08:13:18.24#ibcon#enter sib2, iclass 20, count 0 2006.175.08:13:18.24#ibcon#flushed, iclass 20, count 0 2006.175.08:13:18.24#ibcon#about to write, iclass 20, count 0 2006.175.08:13:18.24#ibcon#wrote, iclass 20, count 0 2006.175.08:13:18.24#ibcon#about to read 3, iclass 20, count 0 2006.175.08:13:18.27#ibcon#read 3, iclass 20, count 0 2006.175.08:13:18.27#ibcon#about to read 4, iclass 20, count 0 2006.175.08:13:18.27#ibcon#read 4, iclass 20, count 0 2006.175.08:13:18.27#ibcon#about to read 5, iclass 20, count 0 2006.175.08:13:18.27#ibcon#read 5, iclass 20, count 0 2006.175.08:13:18.27#ibcon#about to read 6, iclass 20, count 0 2006.175.08:13:18.27#ibcon#read 6, iclass 20, count 0 2006.175.08:13:18.27#ibcon#end of sib2, iclass 20, count 0 2006.175.08:13:18.27#ibcon#*after write, iclass 20, count 0 2006.175.08:13:18.27#ibcon#*before return 0, iclass 20, count 0 2006.175.08:13:18.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:18.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:18.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:13:18.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:13:18.27$vc4f8/valo=2,572.99 2006.175.08:13:18.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.08:13:18.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.08:13:18.27#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:18.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:18.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:18.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:18.27#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:13:18.27#ibcon#first serial, iclass 22, count 0 2006.175.08:13:18.27#ibcon#enter sib2, iclass 22, count 0 2006.175.08:13:18.27#ibcon#flushed, iclass 22, count 0 2006.175.08:13:18.27#ibcon#about to write, iclass 22, count 0 2006.175.08:13:18.27#ibcon#wrote, iclass 22, count 0 2006.175.08:13:18.27#ibcon#about to read 3, iclass 22, count 0 2006.175.08:13:18.29#ibcon#read 3, iclass 22, count 0 2006.175.08:13:18.29#ibcon#about to read 4, iclass 22, count 0 2006.175.08:13:18.29#ibcon#read 4, iclass 22, count 0 2006.175.08:13:18.29#ibcon#about to read 5, iclass 22, count 0 2006.175.08:13:18.29#ibcon#read 5, iclass 22, count 0 2006.175.08:13:18.29#ibcon#about to read 6, iclass 22, count 0 2006.175.08:13:18.29#ibcon#read 6, iclass 22, count 0 2006.175.08:13:18.29#ibcon#end of sib2, iclass 22, count 0 2006.175.08:13:18.29#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:13:18.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:13:18.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:13:18.29#ibcon#*before write, iclass 22, count 0 2006.175.08:13:18.29#ibcon#enter sib2, iclass 22, count 0 2006.175.08:13:18.29#ibcon#flushed, iclass 22, count 0 2006.175.08:13:18.29#ibcon#about to write, iclass 22, count 0 2006.175.08:13:18.29#ibcon#wrote, iclass 22, count 0 2006.175.08:13:18.29#ibcon#about to read 3, iclass 22, count 0 2006.175.08:13:18.33#ibcon#read 3, iclass 22, count 0 2006.175.08:13:18.33#ibcon#about to read 4, iclass 22, count 0 2006.175.08:13:18.33#ibcon#read 4, iclass 22, count 0 2006.175.08:13:18.33#ibcon#about to read 5, iclass 22, count 0 2006.175.08:13:18.33#ibcon#read 5, iclass 22, count 0 2006.175.08:13:18.33#ibcon#about to read 6, iclass 22, count 0 2006.175.08:13:18.33#ibcon#read 6, iclass 22, count 0 2006.175.08:13:18.33#ibcon#end of sib2, iclass 22, count 0 2006.175.08:13:18.33#ibcon#*after write, iclass 22, count 0 2006.175.08:13:18.33#ibcon#*before return 0, iclass 22, count 0 2006.175.08:13:18.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:18.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:18.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:13:18.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:13:18.33$vc4f8/va=2,7 2006.175.08:13:18.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.08:13:18.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.08:13:18.33#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:18.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:18.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:18.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:18.39#ibcon#enter wrdev, iclass 24, count 2 2006.175.08:13:18.39#ibcon#first serial, iclass 24, count 2 2006.175.08:13:18.39#ibcon#enter sib2, iclass 24, count 2 2006.175.08:13:18.39#ibcon#flushed, iclass 24, count 2 2006.175.08:13:18.39#ibcon#about to write, iclass 24, count 2 2006.175.08:13:18.39#ibcon#wrote, iclass 24, count 2 2006.175.08:13:18.39#ibcon#about to read 3, iclass 24, count 2 2006.175.08:13:18.41#ibcon#read 3, iclass 24, count 2 2006.175.08:13:18.41#ibcon#about to read 4, iclass 24, count 2 2006.175.08:13:18.41#ibcon#read 4, iclass 24, count 2 2006.175.08:13:18.41#ibcon#about to read 5, iclass 24, count 2 2006.175.08:13:18.41#ibcon#read 5, iclass 24, count 2 2006.175.08:13:18.41#ibcon#about to read 6, iclass 24, count 2 2006.175.08:13:18.41#ibcon#read 6, iclass 24, count 2 2006.175.08:13:18.41#ibcon#end of sib2, iclass 24, count 2 2006.175.08:13:18.41#ibcon#*mode == 0, iclass 24, count 2 2006.175.08:13:18.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.08:13:18.41#ibcon#[25=AT02-07\r\n] 2006.175.08:13:18.41#ibcon#*before write, iclass 24, count 2 2006.175.08:13:18.41#ibcon#enter sib2, iclass 24, count 2 2006.175.08:13:18.41#ibcon#flushed, iclass 24, count 2 2006.175.08:13:18.41#ibcon#about to write, iclass 24, count 2 2006.175.08:13:18.41#ibcon#wrote, iclass 24, count 2 2006.175.08:13:18.41#ibcon#about to read 3, iclass 24, count 2 2006.175.08:13:18.44#ibcon#read 3, iclass 24, count 2 2006.175.08:13:18.44#ibcon#about to read 4, iclass 24, count 2 2006.175.08:13:18.44#ibcon#read 4, iclass 24, count 2 2006.175.08:13:18.44#ibcon#about to read 5, iclass 24, count 2 2006.175.08:13:18.44#ibcon#read 5, iclass 24, count 2 2006.175.08:13:18.44#ibcon#about to read 6, iclass 24, count 2 2006.175.08:13:18.44#ibcon#read 6, iclass 24, count 2 2006.175.08:13:18.44#ibcon#end of sib2, iclass 24, count 2 2006.175.08:13:18.44#ibcon#*after write, iclass 24, count 2 2006.175.08:13:18.44#ibcon#*before return 0, iclass 24, count 2 2006.175.08:13:18.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:18.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:18.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.08:13:18.44#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:18.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:18.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:18.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:18.56#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:13:18.56#ibcon#first serial, iclass 24, count 0 2006.175.08:13:18.56#ibcon#enter sib2, iclass 24, count 0 2006.175.08:13:18.56#ibcon#flushed, iclass 24, count 0 2006.175.08:13:18.56#ibcon#about to write, iclass 24, count 0 2006.175.08:13:18.56#ibcon#wrote, iclass 24, count 0 2006.175.08:13:18.56#ibcon#about to read 3, iclass 24, count 0 2006.175.08:13:18.58#ibcon#read 3, iclass 24, count 0 2006.175.08:13:18.58#ibcon#about to read 4, iclass 24, count 0 2006.175.08:13:18.58#ibcon#read 4, iclass 24, count 0 2006.175.08:13:18.58#ibcon#about to read 5, iclass 24, count 0 2006.175.08:13:18.58#ibcon#read 5, iclass 24, count 0 2006.175.08:13:18.58#ibcon#about to read 6, iclass 24, count 0 2006.175.08:13:18.58#ibcon#read 6, iclass 24, count 0 2006.175.08:13:18.58#ibcon#end of sib2, iclass 24, count 0 2006.175.08:13:18.58#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:13:18.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:13:18.58#ibcon#[25=USB\r\n] 2006.175.08:13:18.58#ibcon#*before write, iclass 24, count 0 2006.175.08:13:18.58#ibcon#enter sib2, iclass 24, count 0 2006.175.08:13:18.58#ibcon#flushed, iclass 24, count 0 2006.175.08:13:18.58#ibcon#about to write, iclass 24, count 0 2006.175.08:13:18.58#ibcon#wrote, iclass 24, count 0 2006.175.08:13:18.58#ibcon#about to read 3, iclass 24, count 0 2006.175.08:13:18.61#ibcon#read 3, iclass 24, count 0 2006.175.08:13:18.61#ibcon#about to read 4, iclass 24, count 0 2006.175.08:13:18.61#ibcon#read 4, iclass 24, count 0 2006.175.08:13:18.61#ibcon#about to read 5, iclass 24, count 0 2006.175.08:13:18.61#ibcon#read 5, iclass 24, count 0 2006.175.08:13:18.61#ibcon#about to read 6, iclass 24, count 0 2006.175.08:13:18.61#ibcon#read 6, iclass 24, count 0 2006.175.08:13:18.61#ibcon#end of sib2, iclass 24, count 0 2006.175.08:13:18.61#ibcon#*after write, iclass 24, count 0 2006.175.08:13:18.61#ibcon#*before return 0, iclass 24, count 0 2006.175.08:13:18.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:18.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:18.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:13:18.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:13:18.61$vc4f8/valo=3,672.99 2006.175.08:13:18.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.08:13:18.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.08:13:18.61#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:18.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:18.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:18.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:18.61#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:13:18.61#ibcon#first serial, iclass 26, count 0 2006.175.08:13:18.61#ibcon#enter sib2, iclass 26, count 0 2006.175.08:13:18.61#ibcon#flushed, iclass 26, count 0 2006.175.08:13:18.61#ibcon#about to write, iclass 26, count 0 2006.175.08:13:18.61#ibcon#wrote, iclass 26, count 0 2006.175.08:13:18.61#ibcon#about to read 3, iclass 26, count 0 2006.175.08:13:18.63#ibcon#read 3, iclass 26, count 0 2006.175.08:13:18.63#ibcon#about to read 4, iclass 26, count 0 2006.175.08:13:18.63#ibcon#read 4, iclass 26, count 0 2006.175.08:13:18.63#ibcon#about to read 5, iclass 26, count 0 2006.175.08:13:18.63#ibcon#read 5, iclass 26, count 0 2006.175.08:13:18.63#ibcon#about to read 6, iclass 26, count 0 2006.175.08:13:18.63#ibcon#read 6, iclass 26, count 0 2006.175.08:13:18.63#ibcon#end of sib2, iclass 26, count 0 2006.175.08:13:18.63#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:13:18.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:13:18.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:13:18.63#ibcon#*before write, iclass 26, count 0 2006.175.08:13:18.63#ibcon#enter sib2, iclass 26, count 0 2006.175.08:13:18.63#ibcon#flushed, iclass 26, count 0 2006.175.08:13:18.63#ibcon#about to write, iclass 26, count 0 2006.175.08:13:18.63#ibcon#wrote, iclass 26, count 0 2006.175.08:13:18.63#ibcon#about to read 3, iclass 26, count 0 2006.175.08:13:18.67#ibcon#read 3, iclass 26, count 0 2006.175.08:13:18.67#ibcon#about to read 4, iclass 26, count 0 2006.175.08:13:18.67#ibcon#read 4, iclass 26, count 0 2006.175.08:13:18.67#ibcon#about to read 5, iclass 26, count 0 2006.175.08:13:18.67#ibcon#read 5, iclass 26, count 0 2006.175.08:13:18.67#ibcon#about to read 6, iclass 26, count 0 2006.175.08:13:18.67#ibcon#read 6, iclass 26, count 0 2006.175.08:13:18.67#ibcon#end of sib2, iclass 26, count 0 2006.175.08:13:18.67#ibcon#*after write, iclass 26, count 0 2006.175.08:13:18.67#ibcon#*before return 0, iclass 26, count 0 2006.175.08:13:18.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:18.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:18.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:13:18.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:13:18.67$vc4f8/va=3,6 2006.175.08:13:18.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.08:13:18.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.08:13:18.67#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:18.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:18.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:18.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:18.73#ibcon#enter wrdev, iclass 28, count 2 2006.175.08:13:18.73#ibcon#first serial, iclass 28, count 2 2006.175.08:13:18.73#ibcon#enter sib2, iclass 28, count 2 2006.175.08:13:18.73#ibcon#flushed, iclass 28, count 2 2006.175.08:13:18.73#ibcon#about to write, iclass 28, count 2 2006.175.08:13:18.73#ibcon#wrote, iclass 28, count 2 2006.175.08:13:18.73#ibcon#about to read 3, iclass 28, count 2 2006.175.08:13:18.75#ibcon#read 3, iclass 28, count 2 2006.175.08:13:18.75#ibcon#about to read 4, iclass 28, count 2 2006.175.08:13:18.75#ibcon#read 4, iclass 28, count 2 2006.175.08:13:18.75#ibcon#about to read 5, iclass 28, count 2 2006.175.08:13:18.75#ibcon#read 5, iclass 28, count 2 2006.175.08:13:18.75#ibcon#about to read 6, iclass 28, count 2 2006.175.08:13:18.75#ibcon#read 6, iclass 28, count 2 2006.175.08:13:18.75#ibcon#end of sib2, iclass 28, count 2 2006.175.08:13:18.75#ibcon#*mode == 0, iclass 28, count 2 2006.175.08:13:18.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.08:13:18.75#ibcon#[25=AT03-06\r\n] 2006.175.08:13:18.75#ibcon#*before write, iclass 28, count 2 2006.175.08:13:18.75#ibcon#enter sib2, iclass 28, count 2 2006.175.08:13:18.75#ibcon#flushed, iclass 28, count 2 2006.175.08:13:18.75#ibcon#about to write, iclass 28, count 2 2006.175.08:13:18.75#ibcon#wrote, iclass 28, count 2 2006.175.08:13:18.75#ibcon#about to read 3, iclass 28, count 2 2006.175.08:13:18.78#ibcon#read 3, iclass 28, count 2 2006.175.08:13:18.78#ibcon#about to read 4, iclass 28, count 2 2006.175.08:13:18.78#ibcon#read 4, iclass 28, count 2 2006.175.08:13:18.78#ibcon#about to read 5, iclass 28, count 2 2006.175.08:13:18.78#ibcon#read 5, iclass 28, count 2 2006.175.08:13:18.78#ibcon#about to read 6, iclass 28, count 2 2006.175.08:13:18.78#ibcon#read 6, iclass 28, count 2 2006.175.08:13:18.78#ibcon#end of sib2, iclass 28, count 2 2006.175.08:13:18.78#ibcon#*after write, iclass 28, count 2 2006.175.08:13:18.78#ibcon#*before return 0, iclass 28, count 2 2006.175.08:13:18.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:18.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:18.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.08:13:18.78#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:18.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:18.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:18.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:18.90#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:13:18.90#ibcon#first serial, iclass 28, count 0 2006.175.08:13:18.90#ibcon#enter sib2, iclass 28, count 0 2006.175.08:13:18.90#ibcon#flushed, iclass 28, count 0 2006.175.08:13:18.90#ibcon#about to write, iclass 28, count 0 2006.175.08:13:18.90#ibcon#wrote, iclass 28, count 0 2006.175.08:13:18.90#ibcon#about to read 3, iclass 28, count 0 2006.175.08:13:18.92#ibcon#read 3, iclass 28, count 0 2006.175.08:13:18.92#ibcon#about to read 4, iclass 28, count 0 2006.175.08:13:18.92#ibcon#read 4, iclass 28, count 0 2006.175.08:13:18.92#ibcon#about to read 5, iclass 28, count 0 2006.175.08:13:18.92#ibcon#read 5, iclass 28, count 0 2006.175.08:13:18.92#ibcon#about to read 6, iclass 28, count 0 2006.175.08:13:18.92#ibcon#read 6, iclass 28, count 0 2006.175.08:13:18.92#ibcon#end of sib2, iclass 28, count 0 2006.175.08:13:18.92#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:13:18.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:13:18.92#ibcon#[25=USB\r\n] 2006.175.08:13:18.92#ibcon#*before write, iclass 28, count 0 2006.175.08:13:18.92#ibcon#enter sib2, iclass 28, count 0 2006.175.08:13:18.92#ibcon#flushed, iclass 28, count 0 2006.175.08:13:18.92#ibcon#about to write, iclass 28, count 0 2006.175.08:13:18.92#ibcon#wrote, iclass 28, count 0 2006.175.08:13:18.92#ibcon#about to read 3, iclass 28, count 0 2006.175.08:13:18.95#ibcon#read 3, iclass 28, count 0 2006.175.08:13:18.95#ibcon#about to read 4, iclass 28, count 0 2006.175.08:13:18.95#ibcon#read 4, iclass 28, count 0 2006.175.08:13:18.95#ibcon#about to read 5, iclass 28, count 0 2006.175.08:13:18.95#ibcon#read 5, iclass 28, count 0 2006.175.08:13:18.95#ibcon#about to read 6, iclass 28, count 0 2006.175.08:13:18.95#ibcon#read 6, iclass 28, count 0 2006.175.08:13:18.95#ibcon#end of sib2, iclass 28, count 0 2006.175.08:13:18.95#ibcon#*after write, iclass 28, count 0 2006.175.08:13:18.95#ibcon#*before return 0, iclass 28, count 0 2006.175.08:13:18.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:18.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:18.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:13:18.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:13:18.95$vc4f8/valo=4,832.99 2006.175.08:13:18.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.08:13:18.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.08:13:18.95#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:18.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:18.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:18.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:18.95#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:13:18.95#ibcon#first serial, iclass 30, count 0 2006.175.08:13:18.95#ibcon#enter sib2, iclass 30, count 0 2006.175.08:13:18.95#ibcon#flushed, iclass 30, count 0 2006.175.08:13:18.95#ibcon#about to write, iclass 30, count 0 2006.175.08:13:18.95#ibcon#wrote, iclass 30, count 0 2006.175.08:13:18.95#ibcon#about to read 3, iclass 30, count 0 2006.175.08:13:18.97#ibcon#read 3, iclass 30, count 0 2006.175.08:13:18.97#ibcon#about to read 4, iclass 30, count 0 2006.175.08:13:18.97#ibcon#read 4, iclass 30, count 0 2006.175.08:13:18.97#ibcon#about to read 5, iclass 30, count 0 2006.175.08:13:18.97#ibcon#read 5, iclass 30, count 0 2006.175.08:13:18.97#ibcon#about to read 6, iclass 30, count 0 2006.175.08:13:18.97#ibcon#read 6, iclass 30, count 0 2006.175.08:13:18.97#ibcon#end of sib2, iclass 30, count 0 2006.175.08:13:18.97#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:13:18.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:13:18.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:13:18.97#ibcon#*before write, iclass 30, count 0 2006.175.08:13:18.97#ibcon#enter sib2, iclass 30, count 0 2006.175.08:13:18.97#ibcon#flushed, iclass 30, count 0 2006.175.08:13:18.97#ibcon#about to write, iclass 30, count 0 2006.175.08:13:18.97#ibcon#wrote, iclass 30, count 0 2006.175.08:13:18.97#ibcon#about to read 3, iclass 30, count 0 2006.175.08:13:19.01#ibcon#read 3, iclass 30, count 0 2006.175.08:13:19.01#ibcon#about to read 4, iclass 30, count 0 2006.175.08:13:19.01#ibcon#read 4, iclass 30, count 0 2006.175.08:13:19.01#ibcon#about to read 5, iclass 30, count 0 2006.175.08:13:19.01#ibcon#read 5, iclass 30, count 0 2006.175.08:13:19.01#ibcon#about to read 6, iclass 30, count 0 2006.175.08:13:19.01#ibcon#read 6, iclass 30, count 0 2006.175.08:13:19.01#ibcon#end of sib2, iclass 30, count 0 2006.175.08:13:19.01#ibcon#*after write, iclass 30, count 0 2006.175.08:13:19.01#ibcon#*before return 0, iclass 30, count 0 2006.175.08:13:19.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:19.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:19.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:13:19.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:13:19.01$vc4f8/va=4,7 2006.175.08:13:19.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.08:13:19.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.08:13:19.01#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:19.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:19.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:19.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:19.07#ibcon#enter wrdev, iclass 32, count 2 2006.175.08:13:19.07#ibcon#first serial, iclass 32, count 2 2006.175.08:13:19.07#ibcon#enter sib2, iclass 32, count 2 2006.175.08:13:19.07#ibcon#flushed, iclass 32, count 2 2006.175.08:13:19.07#ibcon#about to write, iclass 32, count 2 2006.175.08:13:19.07#ibcon#wrote, iclass 32, count 2 2006.175.08:13:19.07#ibcon#about to read 3, iclass 32, count 2 2006.175.08:13:19.09#ibcon#read 3, iclass 32, count 2 2006.175.08:13:19.09#ibcon#about to read 4, iclass 32, count 2 2006.175.08:13:19.09#ibcon#read 4, iclass 32, count 2 2006.175.08:13:19.09#ibcon#about to read 5, iclass 32, count 2 2006.175.08:13:19.09#ibcon#read 5, iclass 32, count 2 2006.175.08:13:19.09#ibcon#about to read 6, iclass 32, count 2 2006.175.08:13:19.09#ibcon#read 6, iclass 32, count 2 2006.175.08:13:19.09#ibcon#end of sib2, iclass 32, count 2 2006.175.08:13:19.09#ibcon#*mode == 0, iclass 32, count 2 2006.175.08:13:19.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.08:13:19.09#ibcon#[25=AT04-07\r\n] 2006.175.08:13:19.09#ibcon#*before write, iclass 32, count 2 2006.175.08:13:19.09#ibcon#enter sib2, iclass 32, count 2 2006.175.08:13:19.09#ibcon#flushed, iclass 32, count 2 2006.175.08:13:19.09#ibcon#about to write, iclass 32, count 2 2006.175.08:13:19.09#ibcon#wrote, iclass 32, count 2 2006.175.08:13:19.09#ibcon#about to read 3, iclass 32, count 2 2006.175.08:13:19.12#ibcon#read 3, iclass 32, count 2 2006.175.08:13:19.12#ibcon#about to read 4, iclass 32, count 2 2006.175.08:13:19.12#ibcon#read 4, iclass 32, count 2 2006.175.08:13:19.12#ibcon#about to read 5, iclass 32, count 2 2006.175.08:13:19.12#ibcon#read 5, iclass 32, count 2 2006.175.08:13:19.12#ibcon#about to read 6, iclass 32, count 2 2006.175.08:13:19.12#ibcon#read 6, iclass 32, count 2 2006.175.08:13:19.12#ibcon#end of sib2, iclass 32, count 2 2006.175.08:13:19.12#ibcon#*after write, iclass 32, count 2 2006.175.08:13:19.12#ibcon#*before return 0, iclass 32, count 2 2006.175.08:13:19.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:19.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:19.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.08:13:19.12#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:19.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:19.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:19.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:19.24#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:13:19.24#ibcon#first serial, iclass 32, count 0 2006.175.08:13:19.24#ibcon#enter sib2, iclass 32, count 0 2006.175.08:13:19.24#ibcon#flushed, iclass 32, count 0 2006.175.08:13:19.24#ibcon#about to write, iclass 32, count 0 2006.175.08:13:19.24#ibcon#wrote, iclass 32, count 0 2006.175.08:13:19.24#ibcon#about to read 3, iclass 32, count 0 2006.175.08:13:19.26#ibcon#read 3, iclass 32, count 0 2006.175.08:13:19.26#ibcon#about to read 4, iclass 32, count 0 2006.175.08:13:19.26#ibcon#read 4, iclass 32, count 0 2006.175.08:13:19.26#ibcon#about to read 5, iclass 32, count 0 2006.175.08:13:19.26#ibcon#read 5, iclass 32, count 0 2006.175.08:13:19.26#ibcon#about to read 6, iclass 32, count 0 2006.175.08:13:19.26#ibcon#read 6, iclass 32, count 0 2006.175.08:13:19.26#ibcon#end of sib2, iclass 32, count 0 2006.175.08:13:19.26#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:13:19.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:13:19.26#ibcon#[25=USB\r\n] 2006.175.08:13:19.26#ibcon#*before write, iclass 32, count 0 2006.175.08:13:19.26#ibcon#enter sib2, iclass 32, count 0 2006.175.08:13:19.26#ibcon#flushed, iclass 32, count 0 2006.175.08:13:19.26#ibcon#about to write, iclass 32, count 0 2006.175.08:13:19.26#ibcon#wrote, iclass 32, count 0 2006.175.08:13:19.26#ibcon#about to read 3, iclass 32, count 0 2006.175.08:13:19.29#ibcon#read 3, iclass 32, count 0 2006.175.08:13:19.29#ibcon#about to read 4, iclass 32, count 0 2006.175.08:13:19.29#ibcon#read 4, iclass 32, count 0 2006.175.08:13:19.29#ibcon#about to read 5, iclass 32, count 0 2006.175.08:13:19.29#ibcon#read 5, iclass 32, count 0 2006.175.08:13:19.29#ibcon#about to read 6, iclass 32, count 0 2006.175.08:13:19.29#ibcon#read 6, iclass 32, count 0 2006.175.08:13:19.29#ibcon#end of sib2, iclass 32, count 0 2006.175.08:13:19.29#ibcon#*after write, iclass 32, count 0 2006.175.08:13:19.29#ibcon#*before return 0, iclass 32, count 0 2006.175.08:13:19.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:19.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:19.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:13:19.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:13:19.29$vc4f8/valo=5,652.99 2006.175.08:13:19.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.08:13:19.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.08:13:19.29#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:19.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:19.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:19.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:19.29#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:13:19.29#ibcon#first serial, iclass 34, count 0 2006.175.08:13:19.29#ibcon#enter sib2, iclass 34, count 0 2006.175.08:13:19.29#ibcon#flushed, iclass 34, count 0 2006.175.08:13:19.29#ibcon#about to write, iclass 34, count 0 2006.175.08:13:19.29#ibcon#wrote, iclass 34, count 0 2006.175.08:13:19.29#ibcon#about to read 3, iclass 34, count 0 2006.175.08:13:19.31#ibcon#read 3, iclass 34, count 0 2006.175.08:13:19.31#ibcon#about to read 4, iclass 34, count 0 2006.175.08:13:19.31#ibcon#read 4, iclass 34, count 0 2006.175.08:13:19.31#ibcon#about to read 5, iclass 34, count 0 2006.175.08:13:19.31#ibcon#read 5, iclass 34, count 0 2006.175.08:13:19.31#ibcon#about to read 6, iclass 34, count 0 2006.175.08:13:19.31#ibcon#read 6, iclass 34, count 0 2006.175.08:13:19.31#ibcon#end of sib2, iclass 34, count 0 2006.175.08:13:19.31#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:13:19.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:13:19.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:13:19.31#ibcon#*before write, iclass 34, count 0 2006.175.08:13:19.31#ibcon#enter sib2, iclass 34, count 0 2006.175.08:13:19.31#ibcon#flushed, iclass 34, count 0 2006.175.08:13:19.31#ibcon#about to write, iclass 34, count 0 2006.175.08:13:19.31#ibcon#wrote, iclass 34, count 0 2006.175.08:13:19.31#ibcon#about to read 3, iclass 34, count 0 2006.175.08:13:19.35#ibcon#read 3, iclass 34, count 0 2006.175.08:13:19.35#ibcon#about to read 4, iclass 34, count 0 2006.175.08:13:19.35#ibcon#read 4, iclass 34, count 0 2006.175.08:13:19.35#ibcon#about to read 5, iclass 34, count 0 2006.175.08:13:19.35#ibcon#read 5, iclass 34, count 0 2006.175.08:13:19.35#ibcon#about to read 6, iclass 34, count 0 2006.175.08:13:19.35#ibcon#read 6, iclass 34, count 0 2006.175.08:13:19.35#ibcon#end of sib2, iclass 34, count 0 2006.175.08:13:19.35#ibcon#*after write, iclass 34, count 0 2006.175.08:13:19.35#ibcon#*before return 0, iclass 34, count 0 2006.175.08:13:19.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:19.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:19.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:13:19.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:13:19.35$vc4f8/va=5,7 2006.175.08:13:19.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.08:13:19.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.08:13:19.35#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:19.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:19.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:19.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:19.41#ibcon#enter wrdev, iclass 36, count 2 2006.175.08:13:19.41#ibcon#first serial, iclass 36, count 2 2006.175.08:13:19.41#ibcon#enter sib2, iclass 36, count 2 2006.175.08:13:19.41#ibcon#flushed, iclass 36, count 2 2006.175.08:13:19.41#ibcon#about to write, iclass 36, count 2 2006.175.08:13:19.41#ibcon#wrote, iclass 36, count 2 2006.175.08:13:19.41#ibcon#about to read 3, iclass 36, count 2 2006.175.08:13:19.43#ibcon#read 3, iclass 36, count 2 2006.175.08:13:19.43#ibcon#about to read 4, iclass 36, count 2 2006.175.08:13:19.43#ibcon#read 4, iclass 36, count 2 2006.175.08:13:19.43#ibcon#about to read 5, iclass 36, count 2 2006.175.08:13:19.43#ibcon#read 5, iclass 36, count 2 2006.175.08:13:19.43#ibcon#about to read 6, iclass 36, count 2 2006.175.08:13:19.43#ibcon#read 6, iclass 36, count 2 2006.175.08:13:19.43#ibcon#end of sib2, iclass 36, count 2 2006.175.08:13:19.43#ibcon#*mode == 0, iclass 36, count 2 2006.175.08:13:19.43#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.08:13:19.43#ibcon#[25=AT05-07\r\n] 2006.175.08:13:19.43#ibcon#*before write, iclass 36, count 2 2006.175.08:13:19.43#ibcon#enter sib2, iclass 36, count 2 2006.175.08:13:19.43#ibcon#flushed, iclass 36, count 2 2006.175.08:13:19.43#ibcon#about to write, iclass 36, count 2 2006.175.08:13:19.43#ibcon#wrote, iclass 36, count 2 2006.175.08:13:19.43#ibcon#about to read 3, iclass 36, count 2 2006.175.08:13:19.46#ibcon#read 3, iclass 36, count 2 2006.175.08:13:19.46#ibcon#about to read 4, iclass 36, count 2 2006.175.08:13:19.46#ibcon#read 4, iclass 36, count 2 2006.175.08:13:19.46#ibcon#about to read 5, iclass 36, count 2 2006.175.08:13:19.46#ibcon#read 5, iclass 36, count 2 2006.175.08:13:19.46#ibcon#about to read 6, iclass 36, count 2 2006.175.08:13:19.46#ibcon#read 6, iclass 36, count 2 2006.175.08:13:19.46#ibcon#end of sib2, iclass 36, count 2 2006.175.08:13:19.46#ibcon#*after write, iclass 36, count 2 2006.175.08:13:19.46#ibcon#*before return 0, iclass 36, count 2 2006.175.08:13:19.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:19.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:19.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.08:13:19.46#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:19.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:19.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:19.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:19.58#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:13:19.58#ibcon#first serial, iclass 36, count 0 2006.175.08:13:19.58#ibcon#enter sib2, iclass 36, count 0 2006.175.08:13:19.58#ibcon#flushed, iclass 36, count 0 2006.175.08:13:19.58#ibcon#about to write, iclass 36, count 0 2006.175.08:13:19.58#ibcon#wrote, iclass 36, count 0 2006.175.08:13:19.58#ibcon#about to read 3, iclass 36, count 0 2006.175.08:13:19.60#ibcon#read 3, iclass 36, count 0 2006.175.08:13:19.60#ibcon#about to read 4, iclass 36, count 0 2006.175.08:13:19.60#ibcon#read 4, iclass 36, count 0 2006.175.08:13:19.60#ibcon#about to read 5, iclass 36, count 0 2006.175.08:13:19.60#ibcon#read 5, iclass 36, count 0 2006.175.08:13:19.60#ibcon#about to read 6, iclass 36, count 0 2006.175.08:13:19.60#ibcon#read 6, iclass 36, count 0 2006.175.08:13:19.60#ibcon#end of sib2, iclass 36, count 0 2006.175.08:13:19.60#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:13:19.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:13:19.60#ibcon#[25=USB\r\n] 2006.175.08:13:19.60#ibcon#*before write, iclass 36, count 0 2006.175.08:13:19.60#ibcon#enter sib2, iclass 36, count 0 2006.175.08:13:19.60#ibcon#flushed, iclass 36, count 0 2006.175.08:13:19.60#ibcon#about to write, iclass 36, count 0 2006.175.08:13:19.60#ibcon#wrote, iclass 36, count 0 2006.175.08:13:19.60#ibcon#about to read 3, iclass 36, count 0 2006.175.08:13:19.63#ibcon#read 3, iclass 36, count 0 2006.175.08:13:19.63#ibcon#about to read 4, iclass 36, count 0 2006.175.08:13:19.63#ibcon#read 4, iclass 36, count 0 2006.175.08:13:19.63#ibcon#about to read 5, iclass 36, count 0 2006.175.08:13:19.63#ibcon#read 5, iclass 36, count 0 2006.175.08:13:19.63#ibcon#about to read 6, iclass 36, count 0 2006.175.08:13:19.63#ibcon#read 6, iclass 36, count 0 2006.175.08:13:19.63#ibcon#end of sib2, iclass 36, count 0 2006.175.08:13:19.63#ibcon#*after write, iclass 36, count 0 2006.175.08:13:19.63#ibcon#*before return 0, iclass 36, count 0 2006.175.08:13:19.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:19.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:19.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:13:19.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:13:19.63$vc4f8/valo=6,772.99 2006.175.08:13:19.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.08:13:19.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.08:13:19.63#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:19.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:19.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:19.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:19.63#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:13:19.63#ibcon#first serial, iclass 38, count 0 2006.175.08:13:19.63#ibcon#enter sib2, iclass 38, count 0 2006.175.08:13:19.63#ibcon#flushed, iclass 38, count 0 2006.175.08:13:19.63#ibcon#about to write, iclass 38, count 0 2006.175.08:13:19.63#ibcon#wrote, iclass 38, count 0 2006.175.08:13:19.63#ibcon#about to read 3, iclass 38, count 0 2006.175.08:13:19.65#ibcon#read 3, iclass 38, count 0 2006.175.08:13:19.65#ibcon#about to read 4, iclass 38, count 0 2006.175.08:13:19.65#ibcon#read 4, iclass 38, count 0 2006.175.08:13:19.65#ibcon#about to read 5, iclass 38, count 0 2006.175.08:13:19.65#ibcon#read 5, iclass 38, count 0 2006.175.08:13:19.65#ibcon#about to read 6, iclass 38, count 0 2006.175.08:13:19.65#ibcon#read 6, iclass 38, count 0 2006.175.08:13:19.65#ibcon#end of sib2, iclass 38, count 0 2006.175.08:13:19.65#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:13:19.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:13:19.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:13:19.65#ibcon#*before write, iclass 38, count 0 2006.175.08:13:19.65#ibcon#enter sib2, iclass 38, count 0 2006.175.08:13:19.65#ibcon#flushed, iclass 38, count 0 2006.175.08:13:19.65#ibcon#about to write, iclass 38, count 0 2006.175.08:13:19.65#ibcon#wrote, iclass 38, count 0 2006.175.08:13:19.65#ibcon#about to read 3, iclass 38, count 0 2006.175.08:13:19.69#ibcon#read 3, iclass 38, count 0 2006.175.08:13:19.69#ibcon#about to read 4, iclass 38, count 0 2006.175.08:13:19.69#ibcon#read 4, iclass 38, count 0 2006.175.08:13:19.69#ibcon#about to read 5, iclass 38, count 0 2006.175.08:13:19.69#ibcon#read 5, iclass 38, count 0 2006.175.08:13:19.69#ibcon#about to read 6, iclass 38, count 0 2006.175.08:13:19.69#ibcon#read 6, iclass 38, count 0 2006.175.08:13:19.69#ibcon#end of sib2, iclass 38, count 0 2006.175.08:13:19.69#ibcon#*after write, iclass 38, count 0 2006.175.08:13:19.69#ibcon#*before return 0, iclass 38, count 0 2006.175.08:13:19.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:19.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:19.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:13:19.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:13:19.69$vc4f8/va=6,6 2006.175.08:13:19.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.08:13:19.69#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.08:13:19.69#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:19.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:13:19.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:13:19.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:13:19.75#ibcon#enter wrdev, iclass 40, count 2 2006.175.08:13:19.75#ibcon#first serial, iclass 40, count 2 2006.175.08:13:19.75#ibcon#enter sib2, iclass 40, count 2 2006.175.08:13:19.75#ibcon#flushed, iclass 40, count 2 2006.175.08:13:19.75#ibcon#about to write, iclass 40, count 2 2006.175.08:13:19.75#ibcon#wrote, iclass 40, count 2 2006.175.08:13:19.75#ibcon#about to read 3, iclass 40, count 2 2006.175.08:13:19.77#ibcon#read 3, iclass 40, count 2 2006.175.08:13:19.77#ibcon#about to read 4, iclass 40, count 2 2006.175.08:13:19.77#ibcon#read 4, iclass 40, count 2 2006.175.08:13:19.77#ibcon#about to read 5, iclass 40, count 2 2006.175.08:13:19.77#ibcon#read 5, iclass 40, count 2 2006.175.08:13:19.77#ibcon#about to read 6, iclass 40, count 2 2006.175.08:13:19.77#ibcon#read 6, iclass 40, count 2 2006.175.08:13:19.77#ibcon#end of sib2, iclass 40, count 2 2006.175.08:13:19.77#ibcon#*mode == 0, iclass 40, count 2 2006.175.08:13:19.77#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.08:13:19.77#ibcon#[25=AT06-06\r\n] 2006.175.08:13:19.77#ibcon#*before write, iclass 40, count 2 2006.175.08:13:19.77#ibcon#enter sib2, iclass 40, count 2 2006.175.08:13:19.77#ibcon#flushed, iclass 40, count 2 2006.175.08:13:19.77#ibcon#about to write, iclass 40, count 2 2006.175.08:13:19.77#ibcon#wrote, iclass 40, count 2 2006.175.08:13:19.77#ibcon#about to read 3, iclass 40, count 2 2006.175.08:13:19.80#ibcon#read 3, iclass 40, count 2 2006.175.08:13:19.80#ibcon#about to read 4, iclass 40, count 2 2006.175.08:13:19.80#ibcon#read 4, iclass 40, count 2 2006.175.08:13:19.80#ibcon#about to read 5, iclass 40, count 2 2006.175.08:13:19.80#ibcon#read 5, iclass 40, count 2 2006.175.08:13:19.80#ibcon#about to read 6, iclass 40, count 2 2006.175.08:13:19.80#ibcon#read 6, iclass 40, count 2 2006.175.08:13:19.80#ibcon#end of sib2, iclass 40, count 2 2006.175.08:13:19.80#ibcon#*after write, iclass 40, count 2 2006.175.08:13:19.80#ibcon#*before return 0, iclass 40, count 2 2006.175.08:13:19.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:13:19.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:13:19.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.08:13:19.80#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:19.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:13:19.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:13:19.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:13:19.92#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:13:19.92#ibcon#first serial, iclass 40, count 0 2006.175.08:13:19.92#ibcon#enter sib2, iclass 40, count 0 2006.175.08:13:19.92#ibcon#flushed, iclass 40, count 0 2006.175.08:13:19.92#ibcon#about to write, iclass 40, count 0 2006.175.08:13:19.92#ibcon#wrote, iclass 40, count 0 2006.175.08:13:19.92#ibcon#about to read 3, iclass 40, count 0 2006.175.08:13:19.94#ibcon#read 3, iclass 40, count 0 2006.175.08:13:19.94#ibcon#about to read 4, iclass 40, count 0 2006.175.08:13:19.94#ibcon#read 4, iclass 40, count 0 2006.175.08:13:19.94#ibcon#about to read 5, iclass 40, count 0 2006.175.08:13:19.94#ibcon#read 5, iclass 40, count 0 2006.175.08:13:19.94#ibcon#about to read 6, iclass 40, count 0 2006.175.08:13:19.94#ibcon#read 6, iclass 40, count 0 2006.175.08:13:19.94#ibcon#end of sib2, iclass 40, count 0 2006.175.08:13:19.94#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:13:19.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:13:19.94#ibcon#[25=USB\r\n] 2006.175.08:13:19.94#ibcon#*before write, iclass 40, count 0 2006.175.08:13:19.94#ibcon#enter sib2, iclass 40, count 0 2006.175.08:13:19.94#ibcon#flushed, iclass 40, count 0 2006.175.08:13:19.94#ibcon#about to write, iclass 40, count 0 2006.175.08:13:19.94#ibcon#wrote, iclass 40, count 0 2006.175.08:13:19.94#ibcon#about to read 3, iclass 40, count 0 2006.175.08:13:19.97#ibcon#read 3, iclass 40, count 0 2006.175.08:13:19.97#ibcon#about to read 4, iclass 40, count 0 2006.175.08:13:19.97#ibcon#read 4, iclass 40, count 0 2006.175.08:13:19.97#ibcon#about to read 5, iclass 40, count 0 2006.175.08:13:19.97#ibcon#read 5, iclass 40, count 0 2006.175.08:13:19.97#ibcon#about to read 6, iclass 40, count 0 2006.175.08:13:19.97#ibcon#read 6, iclass 40, count 0 2006.175.08:13:19.97#ibcon#end of sib2, iclass 40, count 0 2006.175.08:13:19.97#ibcon#*after write, iclass 40, count 0 2006.175.08:13:19.97#ibcon#*before return 0, iclass 40, count 0 2006.175.08:13:19.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:13:19.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:13:19.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:13:19.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:13:19.97$vc4f8/valo=7,832.99 2006.175.08:13:19.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.08:13:19.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.08:13:19.97#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:19.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:13:19.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:13:19.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:13:19.97#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:13:19.97#ibcon#first serial, iclass 4, count 0 2006.175.08:13:19.97#ibcon#enter sib2, iclass 4, count 0 2006.175.08:13:19.97#ibcon#flushed, iclass 4, count 0 2006.175.08:13:19.97#ibcon#about to write, iclass 4, count 0 2006.175.08:13:19.97#ibcon#wrote, iclass 4, count 0 2006.175.08:13:19.97#ibcon#about to read 3, iclass 4, count 0 2006.175.08:13:19.99#ibcon#read 3, iclass 4, count 0 2006.175.08:13:19.99#ibcon#about to read 4, iclass 4, count 0 2006.175.08:13:19.99#ibcon#read 4, iclass 4, count 0 2006.175.08:13:19.99#ibcon#about to read 5, iclass 4, count 0 2006.175.08:13:19.99#ibcon#read 5, iclass 4, count 0 2006.175.08:13:19.99#ibcon#about to read 6, iclass 4, count 0 2006.175.08:13:19.99#ibcon#read 6, iclass 4, count 0 2006.175.08:13:19.99#ibcon#end of sib2, iclass 4, count 0 2006.175.08:13:19.99#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:13:19.99#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:13:19.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:13:19.99#ibcon#*before write, iclass 4, count 0 2006.175.08:13:19.99#ibcon#enter sib2, iclass 4, count 0 2006.175.08:13:19.99#ibcon#flushed, iclass 4, count 0 2006.175.08:13:19.99#ibcon#about to write, iclass 4, count 0 2006.175.08:13:19.99#ibcon#wrote, iclass 4, count 0 2006.175.08:13:19.99#ibcon#about to read 3, iclass 4, count 0 2006.175.08:13:20.03#ibcon#read 3, iclass 4, count 0 2006.175.08:13:20.03#ibcon#about to read 4, iclass 4, count 0 2006.175.08:13:20.03#ibcon#read 4, iclass 4, count 0 2006.175.08:13:20.03#ibcon#about to read 5, iclass 4, count 0 2006.175.08:13:20.03#ibcon#read 5, iclass 4, count 0 2006.175.08:13:20.03#ibcon#about to read 6, iclass 4, count 0 2006.175.08:13:20.03#ibcon#read 6, iclass 4, count 0 2006.175.08:13:20.03#ibcon#end of sib2, iclass 4, count 0 2006.175.08:13:20.03#ibcon#*after write, iclass 4, count 0 2006.175.08:13:20.03#ibcon#*before return 0, iclass 4, count 0 2006.175.08:13:20.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:13:20.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:13:20.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:13:20.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:13:20.03$vc4f8/va=7,6 2006.175.08:13:20.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.08:13:20.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.08:13:20.03#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:20.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:13:20.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:13:20.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:13:20.09#ibcon#enter wrdev, iclass 6, count 2 2006.175.08:13:20.09#ibcon#first serial, iclass 6, count 2 2006.175.08:13:20.09#ibcon#enter sib2, iclass 6, count 2 2006.175.08:13:20.09#ibcon#flushed, iclass 6, count 2 2006.175.08:13:20.09#ibcon#about to write, iclass 6, count 2 2006.175.08:13:20.09#ibcon#wrote, iclass 6, count 2 2006.175.08:13:20.09#ibcon#about to read 3, iclass 6, count 2 2006.175.08:13:20.11#ibcon#read 3, iclass 6, count 2 2006.175.08:13:20.11#ibcon#about to read 4, iclass 6, count 2 2006.175.08:13:20.11#ibcon#read 4, iclass 6, count 2 2006.175.08:13:20.11#ibcon#about to read 5, iclass 6, count 2 2006.175.08:13:20.11#ibcon#read 5, iclass 6, count 2 2006.175.08:13:20.11#ibcon#about to read 6, iclass 6, count 2 2006.175.08:13:20.11#ibcon#read 6, iclass 6, count 2 2006.175.08:13:20.11#ibcon#end of sib2, iclass 6, count 2 2006.175.08:13:20.11#ibcon#*mode == 0, iclass 6, count 2 2006.175.08:13:20.11#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.08:13:20.11#ibcon#[25=AT07-06\r\n] 2006.175.08:13:20.11#ibcon#*before write, iclass 6, count 2 2006.175.08:13:20.11#ibcon#enter sib2, iclass 6, count 2 2006.175.08:13:20.11#ibcon#flushed, iclass 6, count 2 2006.175.08:13:20.11#ibcon#about to write, iclass 6, count 2 2006.175.08:13:20.11#ibcon#wrote, iclass 6, count 2 2006.175.08:13:20.11#ibcon#about to read 3, iclass 6, count 2 2006.175.08:13:20.14#ibcon#read 3, iclass 6, count 2 2006.175.08:13:20.14#ibcon#about to read 4, iclass 6, count 2 2006.175.08:13:20.14#ibcon#read 4, iclass 6, count 2 2006.175.08:13:20.14#ibcon#about to read 5, iclass 6, count 2 2006.175.08:13:20.14#ibcon#read 5, iclass 6, count 2 2006.175.08:13:20.14#ibcon#about to read 6, iclass 6, count 2 2006.175.08:13:20.14#ibcon#read 6, iclass 6, count 2 2006.175.08:13:20.14#ibcon#end of sib2, iclass 6, count 2 2006.175.08:13:20.14#ibcon#*after write, iclass 6, count 2 2006.175.08:13:20.14#ibcon#*before return 0, iclass 6, count 2 2006.175.08:13:20.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:13:20.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:13:20.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.08:13:20.14#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:20.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:13:20.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:13:20.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:13:20.26#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:13:20.26#ibcon#first serial, iclass 6, count 0 2006.175.08:13:20.26#ibcon#enter sib2, iclass 6, count 0 2006.175.08:13:20.26#ibcon#flushed, iclass 6, count 0 2006.175.08:13:20.26#ibcon#about to write, iclass 6, count 0 2006.175.08:13:20.26#ibcon#wrote, iclass 6, count 0 2006.175.08:13:20.26#ibcon#about to read 3, iclass 6, count 0 2006.175.08:13:20.28#ibcon#read 3, iclass 6, count 0 2006.175.08:13:20.28#ibcon#about to read 4, iclass 6, count 0 2006.175.08:13:20.28#ibcon#read 4, iclass 6, count 0 2006.175.08:13:20.28#ibcon#about to read 5, iclass 6, count 0 2006.175.08:13:20.28#ibcon#read 5, iclass 6, count 0 2006.175.08:13:20.28#ibcon#about to read 6, iclass 6, count 0 2006.175.08:13:20.28#ibcon#read 6, iclass 6, count 0 2006.175.08:13:20.28#ibcon#end of sib2, iclass 6, count 0 2006.175.08:13:20.28#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:13:20.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:13:20.28#ibcon#[25=USB\r\n] 2006.175.08:13:20.28#ibcon#*before write, iclass 6, count 0 2006.175.08:13:20.28#ibcon#enter sib2, iclass 6, count 0 2006.175.08:13:20.28#ibcon#flushed, iclass 6, count 0 2006.175.08:13:20.28#ibcon#about to write, iclass 6, count 0 2006.175.08:13:20.28#ibcon#wrote, iclass 6, count 0 2006.175.08:13:20.28#ibcon#about to read 3, iclass 6, count 0 2006.175.08:13:20.31#ibcon#read 3, iclass 6, count 0 2006.175.08:13:20.31#ibcon#about to read 4, iclass 6, count 0 2006.175.08:13:20.31#ibcon#read 4, iclass 6, count 0 2006.175.08:13:20.31#ibcon#about to read 5, iclass 6, count 0 2006.175.08:13:20.31#ibcon#read 5, iclass 6, count 0 2006.175.08:13:20.31#ibcon#about to read 6, iclass 6, count 0 2006.175.08:13:20.31#ibcon#read 6, iclass 6, count 0 2006.175.08:13:20.31#ibcon#end of sib2, iclass 6, count 0 2006.175.08:13:20.31#ibcon#*after write, iclass 6, count 0 2006.175.08:13:20.31#ibcon#*before return 0, iclass 6, count 0 2006.175.08:13:20.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:13:20.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:13:20.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:13:20.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:13:20.31$vc4f8/valo=8,852.99 2006.175.08:13:20.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.08:13:20.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.08:13:20.31#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:20.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:13:20.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:13:20.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:13:20.31#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:13:20.31#ibcon#first serial, iclass 10, count 0 2006.175.08:13:20.31#ibcon#enter sib2, iclass 10, count 0 2006.175.08:13:20.31#ibcon#flushed, iclass 10, count 0 2006.175.08:13:20.31#ibcon#about to write, iclass 10, count 0 2006.175.08:13:20.31#ibcon#wrote, iclass 10, count 0 2006.175.08:13:20.31#ibcon#about to read 3, iclass 10, count 0 2006.175.08:13:20.33#ibcon#read 3, iclass 10, count 0 2006.175.08:13:20.33#ibcon#about to read 4, iclass 10, count 0 2006.175.08:13:20.33#ibcon#read 4, iclass 10, count 0 2006.175.08:13:20.33#ibcon#about to read 5, iclass 10, count 0 2006.175.08:13:20.33#ibcon#read 5, iclass 10, count 0 2006.175.08:13:20.33#ibcon#about to read 6, iclass 10, count 0 2006.175.08:13:20.33#ibcon#read 6, iclass 10, count 0 2006.175.08:13:20.33#ibcon#end of sib2, iclass 10, count 0 2006.175.08:13:20.33#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:13:20.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:13:20.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:13:20.33#ibcon#*before write, iclass 10, count 0 2006.175.08:13:20.33#ibcon#enter sib2, iclass 10, count 0 2006.175.08:13:20.33#ibcon#flushed, iclass 10, count 0 2006.175.08:13:20.33#ibcon#about to write, iclass 10, count 0 2006.175.08:13:20.33#ibcon#wrote, iclass 10, count 0 2006.175.08:13:20.33#ibcon#about to read 3, iclass 10, count 0 2006.175.08:13:20.37#ibcon#read 3, iclass 10, count 0 2006.175.08:13:20.37#ibcon#about to read 4, iclass 10, count 0 2006.175.08:13:20.37#ibcon#read 4, iclass 10, count 0 2006.175.08:13:20.37#ibcon#about to read 5, iclass 10, count 0 2006.175.08:13:20.37#ibcon#read 5, iclass 10, count 0 2006.175.08:13:20.37#ibcon#about to read 6, iclass 10, count 0 2006.175.08:13:20.37#ibcon#read 6, iclass 10, count 0 2006.175.08:13:20.37#ibcon#end of sib2, iclass 10, count 0 2006.175.08:13:20.37#ibcon#*after write, iclass 10, count 0 2006.175.08:13:20.37#ibcon#*before return 0, iclass 10, count 0 2006.175.08:13:20.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:13:20.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:13:20.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:13:20.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:13:20.37$vc4f8/va=8,6 2006.175.08:13:20.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.08:13:20.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.08:13:20.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:20.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:13:20.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:13:20.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:13:20.43#ibcon#enter wrdev, iclass 12, count 2 2006.175.08:13:20.43#ibcon#first serial, iclass 12, count 2 2006.175.08:13:20.43#ibcon#enter sib2, iclass 12, count 2 2006.175.08:13:20.43#ibcon#flushed, iclass 12, count 2 2006.175.08:13:20.43#ibcon#about to write, iclass 12, count 2 2006.175.08:13:20.43#ibcon#wrote, iclass 12, count 2 2006.175.08:13:20.43#ibcon#about to read 3, iclass 12, count 2 2006.175.08:13:20.45#ibcon#read 3, iclass 12, count 2 2006.175.08:13:20.45#ibcon#about to read 4, iclass 12, count 2 2006.175.08:13:20.45#ibcon#read 4, iclass 12, count 2 2006.175.08:13:20.45#ibcon#about to read 5, iclass 12, count 2 2006.175.08:13:20.45#ibcon#read 5, iclass 12, count 2 2006.175.08:13:20.45#ibcon#about to read 6, iclass 12, count 2 2006.175.08:13:20.45#ibcon#read 6, iclass 12, count 2 2006.175.08:13:20.45#ibcon#end of sib2, iclass 12, count 2 2006.175.08:13:20.45#ibcon#*mode == 0, iclass 12, count 2 2006.175.08:13:20.45#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.08:13:20.45#ibcon#[25=AT08-06\r\n] 2006.175.08:13:20.45#ibcon#*before write, iclass 12, count 2 2006.175.08:13:20.45#ibcon#enter sib2, iclass 12, count 2 2006.175.08:13:20.45#ibcon#flushed, iclass 12, count 2 2006.175.08:13:20.45#ibcon#about to write, iclass 12, count 2 2006.175.08:13:20.45#ibcon#wrote, iclass 12, count 2 2006.175.08:13:20.45#ibcon#about to read 3, iclass 12, count 2 2006.175.08:13:20.48#ibcon#read 3, iclass 12, count 2 2006.175.08:13:20.48#ibcon#about to read 4, iclass 12, count 2 2006.175.08:13:20.48#ibcon#read 4, iclass 12, count 2 2006.175.08:13:20.48#ibcon#about to read 5, iclass 12, count 2 2006.175.08:13:20.48#ibcon#read 5, iclass 12, count 2 2006.175.08:13:20.48#ibcon#about to read 6, iclass 12, count 2 2006.175.08:13:20.48#ibcon#read 6, iclass 12, count 2 2006.175.08:13:20.48#ibcon#end of sib2, iclass 12, count 2 2006.175.08:13:20.48#ibcon#*after write, iclass 12, count 2 2006.175.08:13:20.48#ibcon#*before return 0, iclass 12, count 2 2006.175.08:13:20.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:13:20.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:13:20.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.08:13:20.48#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:20.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:13:20.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:13:20.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:13:20.60#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:13:20.60#ibcon#first serial, iclass 12, count 0 2006.175.08:13:20.60#ibcon#enter sib2, iclass 12, count 0 2006.175.08:13:20.60#ibcon#flushed, iclass 12, count 0 2006.175.08:13:20.60#ibcon#about to write, iclass 12, count 0 2006.175.08:13:20.60#ibcon#wrote, iclass 12, count 0 2006.175.08:13:20.60#ibcon#about to read 3, iclass 12, count 0 2006.175.08:13:20.62#ibcon#read 3, iclass 12, count 0 2006.175.08:13:20.62#ibcon#about to read 4, iclass 12, count 0 2006.175.08:13:20.62#ibcon#read 4, iclass 12, count 0 2006.175.08:13:20.62#ibcon#about to read 5, iclass 12, count 0 2006.175.08:13:20.62#ibcon#read 5, iclass 12, count 0 2006.175.08:13:20.62#ibcon#about to read 6, iclass 12, count 0 2006.175.08:13:20.62#ibcon#read 6, iclass 12, count 0 2006.175.08:13:20.62#ibcon#end of sib2, iclass 12, count 0 2006.175.08:13:20.62#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:13:20.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:13:20.62#ibcon#[25=USB\r\n] 2006.175.08:13:20.62#ibcon#*before write, iclass 12, count 0 2006.175.08:13:20.62#ibcon#enter sib2, iclass 12, count 0 2006.175.08:13:20.62#ibcon#flushed, iclass 12, count 0 2006.175.08:13:20.62#ibcon#about to write, iclass 12, count 0 2006.175.08:13:20.62#ibcon#wrote, iclass 12, count 0 2006.175.08:13:20.62#ibcon#about to read 3, iclass 12, count 0 2006.175.08:13:20.65#ibcon#read 3, iclass 12, count 0 2006.175.08:13:20.65#ibcon#about to read 4, iclass 12, count 0 2006.175.08:13:20.65#ibcon#read 4, iclass 12, count 0 2006.175.08:13:20.65#ibcon#about to read 5, iclass 12, count 0 2006.175.08:13:20.65#ibcon#read 5, iclass 12, count 0 2006.175.08:13:20.65#ibcon#about to read 6, iclass 12, count 0 2006.175.08:13:20.65#ibcon#read 6, iclass 12, count 0 2006.175.08:13:20.65#ibcon#end of sib2, iclass 12, count 0 2006.175.08:13:20.65#ibcon#*after write, iclass 12, count 0 2006.175.08:13:20.65#ibcon#*before return 0, iclass 12, count 0 2006.175.08:13:20.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:13:20.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:13:20.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:13:20.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:13:20.65$vc4f8/vblo=1,632.99 2006.175.08:13:20.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.08:13:20.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.08:13:20.65#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:20.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:13:20.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:13:20.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:13:20.65#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:13:20.65#ibcon#first serial, iclass 14, count 0 2006.175.08:13:20.65#ibcon#enter sib2, iclass 14, count 0 2006.175.08:13:20.65#ibcon#flushed, iclass 14, count 0 2006.175.08:13:20.65#ibcon#about to write, iclass 14, count 0 2006.175.08:13:20.65#ibcon#wrote, iclass 14, count 0 2006.175.08:13:20.65#ibcon#about to read 3, iclass 14, count 0 2006.175.08:13:20.67#ibcon#read 3, iclass 14, count 0 2006.175.08:13:20.67#ibcon#about to read 4, iclass 14, count 0 2006.175.08:13:20.67#ibcon#read 4, iclass 14, count 0 2006.175.08:13:20.67#ibcon#about to read 5, iclass 14, count 0 2006.175.08:13:20.67#ibcon#read 5, iclass 14, count 0 2006.175.08:13:20.67#ibcon#about to read 6, iclass 14, count 0 2006.175.08:13:20.67#ibcon#read 6, iclass 14, count 0 2006.175.08:13:20.67#ibcon#end of sib2, iclass 14, count 0 2006.175.08:13:20.67#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:13:20.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:13:20.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:13:20.67#ibcon#*before write, iclass 14, count 0 2006.175.08:13:20.67#ibcon#enter sib2, iclass 14, count 0 2006.175.08:13:20.67#ibcon#flushed, iclass 14, count 0 2006.175.08:13:20.67#ibcon#about to write, iclass 14, count 0 2006.175.08:13:20.67#ibcon#wrote, iclass 14, count 0 2006.175.08:13:20.67#ibcon#about to read 3, iclass 14, count 0 2006.175.08:13:20.71#ibcon#read 3, iclass 14, count 0 2006.175.08:13:20.71#ibcon#about to read 4, iclass 14, count 0 2006.175.08:13:20.71#ibcon#read 4, iclass 14, count 0 2006.175.08:13:20.71#ibcon#about to read 5, iclass 14, count 0 2006.175.08:13:20.71#ibcon#read 5, iclass 14, count 0 2006.175.08:13:20.71#ibcon#about to read 6, iclass 14, count 0 2006.175.08:13:20.71#ibcon#read 6, iclass 14, count 0 2006.175.08:13:20.71#ibcon#end of sib2, iclass 14, count 0 2006.175.08:13:20.71#ibcon#*after write, iclass 14, count 0 2006.175.08:13:20.71#ibcon#*before return 0, iclass 14, count 0 2006.175.08:13:20.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:13:20.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:13:20.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:13:20.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:13:20.71$vc4f8/vb=1,4 2006.175.08:13:20.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.08:13:20.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.08:13:20.71#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:20.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:13:20.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:13:20.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:13:20.71#ibcon#enter wrdev, iclass 16, count 2 2006.175.08:13:20.71#ibcon#first serial, iclass 16, count 2 2006.175.08:13:20.71#ibcon#enter sib2, iclass 16, count 2 2006.175.08:13:20.71#ibcon#flushed, iclass 16, count 2 2006.175.08:13:20.71#ibcon#about to write, iclass 16, count 2 2006.175.08:13:20.71#ibcon#wrote, iclass 16, count 2 2006.175.08:13:20.71#ibcon#about to read 3, iclass 16, count 2 2006.175.08:13:20.73#ibcon#read 3, iclass 16, count 2 2006.175.08:13:20.73#ibcon#about to read 4, iclass 16, count 2 2006.175.08:13:20.73#ibcon#read 4, iclass 16, count 2 2006.175.08:13:20.73#ibcon#about to read 5, iclass 16, count 2 2006.175.08:13:20.73#ibcon#read 5, iclass 16, count 2 2006.175.08:13:20.73#ibcon#about to read 6, iclass 16, count 2 2006.175.08:13:20.73#ibcon#read 6, iclass 16, count 2 2006.175.08:13:20.73#ibcon#end of sib2, iclass 16, count 2 2006.175.08:13:20.73#ibcon#*mode == 0, iclass 16, count 2 2006.175.08:13:20.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.08:13:20.73#ibcon#[27=AT01-04\r\n] 2006.175.08:13:20.73#ibcon#*before write, iclass 16, count 2 2006.175.08:13:20.73#ibcon#enter sib2, iclass 16, count 2 2006.175.08:13:20.73#ibcon#flushed, iclass 16, count 2 2006.175.08:13:20.73#ibcon#about to write, iclass 16, count 2 2006.175.08:13:20.73#ibcon#wrote, iclass 16, count 2 2006.175.08:13:20.73#ibcon#about to read 3, iclass 16, count 2 2006.175.08:13:20.76#ibcon#read 3, iclass 16, count 2 2006.175.08:13:20.76#ibcon#about to read 4, iclass 16, count 2 2006.175.08:13:20.76#ibcon#read 4, iclass 16, count 2 2006.175.08:13:20.76#ibcon#about to read 5, iclass 16, count 2 2006.175.08:13:20.76#ibcon#read 5, iclass 16, count 2 2006.175.08:13:20.76#ibcon#about to read 6, iclass 16, count 2 2006.175.08:13:20.76#ibcon#read 6, iclass 16, count 2 2006.175.08:13:20.76#ibcon#end of sib2, iclass 16, count 2 2006.175.08:13:20.76#ibcon#*after write, iclass 16, count 2 2006.175.08:13:20.76#ibcon#*before return 0, iclass 16, count 2 2006.175.08:13:20.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:13:20.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:13:20.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.08:13:20.76#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:20.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:13:20.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:13:20.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:13:20.88#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:13:20.88#ibcon#first serial, iclass 16, count 0 2006.175.08:13:20.88#ibcon#enter sib2, iclass 16, count 0 2006.175.08:13:20.88#ibcon#flushed, iclass 16, count 0 2006.175.08:13:20.88#ibcon#about to write, iclass 16, count 0 2006.175.08:13:20.88#ibcon#wrote, iclass 16, count 0 2006.175.08:13:20.88#ibcon#about to read 3, iclass 16, count 0 2006.175.08:13:20.90#ibcon#read 3, iclass 16, count 0 2006.175.08:13:20.90#ibcon#about to read 4, iclass 16, count 0 2006.175.08:13:20.90#ibcon#read 4, iclass 16, count 0 2006.175.08:13:20.90#ibcon#about to read 5, iclass 16, count 0 2006.175.08:13:20.90#ibcon#read 5, iclass 16, count 0 2006.175.08:13:20.90#ibcon#about to read 6, iclass 16, count 0 2006.175.08:13:20.90#ibcon#read 6, iclass 16, count 0 2006.175.08:13:20.90#ibcon#end of sib2, iclass 16, count 0 2006.175.08:13:20.90#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:13:20.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:13:20.90#ibcon#[27=USB\r\n] 2006.175.08:13:20.90#ibcon#*before write, iclass 16, count 0 2006.175.08:13:20.90#ibcon#enter sib2, iclass 16, count 0 2006.175.08:13:20.90#ibcon#flushed, iclass 16, count 0 2006.175.08:13:20.90#ibcon#about to write, iclass 16, count 0 2006.175.08:13:20.90#ibcon#wrote, iclass 16, count 0 2006.175.08:13:20.90#ibcon#about to read 3, iclass 16, count 0 2006.175.08:13:20.93#ibcon#read 3, iclass 16, count 0 2006.175.08:13:20.93#ibcon#about to read 4, iclass 16, count 0 2006.175.08:13:20.93#ibcon#read 4, iclass 16, count 0 2006.175.08:13:20.93#ibcon#about to read 5, iclass 16, count 0 2006.175.08:13:20.93#ibcon#read 5, iclass 16, count 0 2006.175.08:13:20.93#ibcon#about to read 6, iclass 16, count 0 2006.175.08:13:20.93#ibcon#read 6, iclass 16, count 0 2006.175.08:13:20.93#ibcon#end of sib2, iclass 16, count 0 2006.175.08:13:20.93#ibcon#*after write, iclass 16, count 0 2006.175.08:13:20.93#ibcon#*before return 0, iclass 16, count 0 2006.175.08:13:20.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:13:20.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:13:20.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:13:20.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:13:20.93$vc4f8/vblo=2,640.99 2006.175.08:13:20.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.08:13:20.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.08:13:20.93#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:20.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:20.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:20.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:20.93#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:13:20.93#ibcon#first serial, iclass 18, count 0 2006.175.08:13:20.93#ibcon#enter sib2, iclass 18, count 0 2006.175.08:13:20.93#ibcon#flushed, iclass 18, count 0 2006.175.08:13:20.93#ibcon#about to write, iclass 18, count 0 2006.175.08:13:20.93#ibcon#wrote, iclass 18, count 0 2006.175.08:13:20.93#ibcon#about to read 3, iclass 18, count 0 2006.175.08:13:20.95#ibcon#read 3, iclass 18, count 0 2006.175.08:13:20.95#ibcon#about to read 4, iclass 18, count 0 2006.175.08:13:20.95#ibcon#read 4, iclass 18, count 0 2006.175.08:13:20.95#ibcon#about to read 5, iclass 18, count 0 2006.175.08:13:20.95#ibcon#read 5, iclass 18, count 0 2006.175.08:13:20.95#ibcon#about to read 6, iclass 18, count 0 2006.175.08:13:20.95#ibcon#read 6, iclass 18, count 0 2006.175.08:13:20.95#ibcon#end of sib2, iclass 18, count 0 2006.175.08:13:20.95#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:13:20.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:13:20.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:13:20.95#ibcon#*before write, iclass 18, count 0 2006.175.08:13:20.95#ibcon#enter sib2, iclass 18, count 0 2006.175.08:13:20.95#ibcon#flushed, iclass 18, count 0 2006.175.08:13:20.95#ibcon#about to write, iclass 18, count 0 2006.175.08:13:20.95#ibcon#wrote, iclass 18, count 0 2006.175.08:13:20.95#ibcon#about to read 3, iclass 18, count 0 2006.175.08:13:20.99#ibcon#read 3, iclass 18, count 0 2006.175.08:13:20.99#ibcon#about to read 4, iclass 18, count 0 2006.175.08:13:20.99#ibcon#read 4, iclass 18, count 0 2006.175.08:13:20.99#ibcon#about to read 5, iclass 18, count 0 2006.175.08:13:20.99#ibcon#read 5, iclass 18, count 0 2006.175.08:13:20.99#ibcon#about to read 6, iclass 18, count 0 2006.175.08:13:20.99#ibcon#read 6, iclass 18, count 0 2006.175.08:13:20.99#ibcon#end of sib2, iclass 18, count 0 2006.175.08:13:20.99#ibcon#*after write, iclass 18, count 0 2006.175.08:13:20.99#ibcon#*before return 0, iclass 18, count 0 2006.175.08:13:20.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:20.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:13:20.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:13:20.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:13:20.99$vc4f8/vb=2,4 2006.175.08:13:20.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.175.08:13:20.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.175.08:13:20.99#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:20.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:21.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:21.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:21.06#ibcon#enter wrdev, iclass 20, count 2 2006.175.08:13:21.06#ibcon#first serial, iclass 20, count 2 2006.175.08:13:21.06#ibcon#enter sib2, iclass 20, count 2 2006.175.08:13:21.06#ibcon#flushed, iclass 20, count 2 2006.175.08:13:21.06#ibcon#about to write, iclass 20, count 2 2006.175.08:13:21.06#ibcon#wrote, iclass 20, count 2 2006.175.08:13:21.06#ibcon#about to read 3, iclass 20, count 2 2006.175.08:13:21.07#ibcon#read 3, iclass 20, count 2 2006.175.08:13:21.07#ibcon#about to read 4, iclass 20, count 2 2006.175.08:13:21.07#ibcon#read 4, iclass 20, count 2 2006.175.08:13:21.07#ibcon#about to read 5, iclass 20, count 2 2006.175.08:13:21.07#ibcon#read 5, iclass 20, count 2 2006.175.08:13:21.07#ibcon#about to read 6, iclass 20, count 2 2006.175.08:13:21.07#ibcon#read 6, iclass 20, count 2 2006.175.08:13:21.07#ibcon#end of sib2, iclass 20, count 2 2006.175.08:13:21.07#ibcon#*mode == 0, iclass 20, count 2 2006.175.08:13:21.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.175.08:13:21.07#ibcon#[27=AT02-04\r\n] 2006.175.08:13:21.07#ibcon#*before write, iclass 20, count 2 2006.175.08:13:21.07#ibcon#enter sib2, iclass 20, count 2 2006.175.08:13:21.07#ibcon#flushed, iclass 20, count 2 2006.175.08:13:21.07#ibcon#about to write, iclass 20, count 2 2006.175.08:13:21.07#ibcon#wrote, iclass 20, count 2 2006.175.08:13:21.07#ibcon#about to read 3, iclass 20, count 2 2006.175.08:13:21.10#ibcon#read 3, iclass 20, count 2 2006.175.08:13:21.10#ibcon#about to read 4, iclass 20, count 2 2006.175.08:13:21.10#ibcon#read 4, iclass 20, count 2 2006.175.08:13:21.10#ibcon#about to read 5, iclass 20, count 2 2006.175.08:13:21.10#ibcon#read 5, iclass 20, count 2 2006.175.08:13:21.10#ibcon#about to read 6, iclass 20, count 2 2006.175.08:13:21.10#ibcon#read 6, iclass 20, count 2 2006.175.08:13:21.10#ibcon#end of sib2, iclass 20, count 2 2006.175.08:13:21.10#ibcon#*after write, iclass 20, count 2 2006.175.08:13:21.10#ibcon#*before return 0, iclass 20, count 2 2006.175.08:13:21.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:21.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:13:21.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.175.08:13:21.10#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:21.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:21.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:21.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:21.22#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:13:21.22#ibcon#first serial, iclass 20, count 0 2006.175.08:13:21.22#ibcon#enter sib2, iclass 20, count 0 2006.175.08:13:21.22#ibcon#flushed, iclass 20, count 0 2006.175.08:13:21.22#ibcon#about to write, iclass 20, count 0 2006.175.08:13:21.22#ibcon#wrote, iclass 20, count 0 2006.175.08:13:21.22#ibcon#about to read 3, iclass 20, count 0 2006.175.08:13:21.24#ibcon#read 3, iclass 20, count 0 2006.175.08:13:21.24#ibcon#about to read 4, iclass 20, count 0 2006.175.08:13:21.24#ibcon#read 4, iclass 20, count 0 2006.175.08:13:21.24#ibcon#about to read 5, iclass 20, count 0 2006.175.08:13:21.24#ibcon#read 5, iclass 20, count 0 2006.175.08:13:21.24#ibcon#about to read 6, iclass 20, count 0 2006.175.08:13:21.24#ibcon#read 6, iclass 20, count 0 2006.175.08:13:21.24#ibcon#end of sib2, iclass 20, count 0 2006.175.08:13:21.24#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:13:21.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:13:21.24#ibcon#[27=USB\r\n] 2006.175.08:13:21.24#ibcon#*before write, iclass 20, count 0 2006.175.08:13:21.24#ibcon#enter sib2, iclass 20, count 0 2006.175.08:13:21.24#ibcon#flushed, iclass 20, count 0 2006.175.08:13:21.24#ibcon#about to write, iclass 20, count 0 2006.175.08:13:21.24#ibcon#wrote, iclass 20, count 0 2006.175.08:13:21.24#ibcon#about to read 3, iclass 20, count 0 2006.175.08:13:21.27#ibcon#read 3, iclass 20, count 0 2006.175.08:13:21.27#ibcon#about to read 4, iclass 20, count 0 2006.175.08:13:21.27#ibcon#read 4, iclass 20, count 0 2006.175.08:13:21.27#ibcon#about to read 5, iclass 20, count 0 2006.175.08:13:21.27#ibcon#read 5, iclass 20, count 0 2006.175.08:13:21.27#ibcon#about to read 6, iclass 20, count 0 2006.175.08:13:21.27#ibcon#read 6, iclass 20, count 0 2006.175.08:13:21.27#ibcon#end of sib2, iclass 20, count 0 2006.175.08:13:21.27#ibcon#*after write, iclass 20, count 0 2006.175.08:13:21.27#ibcon#*before return 0, iclass 20, count 0 2006.175.08:13:21.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:21.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:13:21.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:13:21.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:13:21.27$vc4f8/vblo=3,656.99 2006.175.08:13:21.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.08:13:21.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.08:13:21.27#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:21.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:21.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:21.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:21.27#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:13:21.27#ibcon#first serial, iclass 22, count 0 2006.175.08:13:21.27#ibcon#enter sib2, iclass 22, count 0 2006.175.08:13:21.27#ibcon#flushed, iclass 22, count 0 2006.175.08:13:21.27#ibcon#about to write, iclass 22, count 0 2006.175.08:13:21.27#ibcon#wrote, iclass 22, count 0 2006.175.08:13:21.27#ibcon#about to read 3, iclass 22, count 0 2006.175.08:13:21.29#ibcon#read 3, iclass 22, count 0 2006.175.08:13:21.29#ibcon#about to read 4, iclass 22, count 0 2006.175.08:13:21.29#ibcon#read 4, iclass 22, count 0 2006.175.08:13:21.29#ibcon#about to read 5, iclass 22, count 0 2006.175.08:13:21.29#ibcon#read 5, iclass 22, count 0 2006.175.08:13:21.29#ibcon#about to read 6, iclass 22, count 0 2006.175.08:13:21.29#ibcon#read 6, iclass 22, count 0 2006.175.08:13:21.29#ibcon#end of sib2, iclass 22, count 0 2006.175.08:13:21.29#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:13:21.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:13:21.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:13:21.29#ibcon#*before write, iclass 22, count 0 2006.175.08:13:21.29#ibcon#enter sib2, iclass 22, count 0 2006.175.08:13:21.29#ibcon#flushed, iclass 22, count 0 2006.175.08:13:21.29#ibcon#about to write, iclass 22, count 0 2006.175.08:13:21.29#ibcon#wrote, iclass 22, count 0 2006.175.08:13:21.29#ibcon#about to read 3, iclass 22, count 0 2006.175.08:13:21.33#ibcon#read 3, iclass 22, count 0 2006.175.08:13:21.33#ibcon#about to read 4, iclass 22, count 0 2006.175.08:13:21.33#ibcon#read 4, iclass 22, count 0 2006.175.08:13:21.33#ibcon#about to read 5, iclass 22, count 0 2006.175.08:13:21.33#ibcon#read 5, iclass 22, count 0 2006.175.08:13:21.33#ibcon#about to read 6, iclass 22, count 0 2006.175.08:13:21.33#ibcon#read 6, iclass 22, count 0 2006.175.08:13:21.33#ibcon#end of sib2, iclass 22, count 0 2006.175.08:13:21.33#ibcon#*after write, iclass 22, count 0 2006.175.08:13:21.33#ibcon#*before return 0, iclass 22, count 0 2006.175.08:13:21.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:21.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:13:21.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:13:21.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:13:21.33$vc4f8/vb=3,4 2006.175.08:13:21.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.08:13:21.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.08:13:21.33#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:21.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:21.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:21.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:21.39#ibcon#enter wrdev, iclass 24, count 2 2006.175.08:13:21.39#ibcon#first serial, iclass 24, count 2 2006.175.08:13:21.39#ibcon#enter sib2, iclass 24, count 2 2006.175.08:13:21.39#ibcon#flushed, iclass 24, count 2 2006.175.08:13:21.39#ibcon#about to write, iclass 24, count 2 2006.175.08:13:21.39#ibcon#wrote, iclass 24, count 2 2006.175.08:13:21.39#ibcon#about to read 3, iclass 24, count 2 2006.175.08:13:21.41#ibcon#read 3, iclass 24, count 2 2006.175.08:13:21.41#ibcon#about to read 4, iclass 24, count 2 2006.175.08:13:21.41#ibcon#read 4, iclass 24, count 2 2006.175.08:13:21.41#ibcon#about to read 5, iclass 24, count 2 2006.175.08:13:21.41#ibcon#read 5, iclass 24, count 2 2006.175.08:13:21.41#ibcon#about to read 6, iclass 24, count 2 2006.175.08:13:21.41#ibcon#read 6, iclass 24, count 2 2006.175.08:13:21.41#ibcon#end of sib2, iclass 24, count 2 2006.175.08:13:21.41#ibcon#*mode == 0, iclass 24, count 2 2006.175.08:13:21.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.08:13:21.41#ibcon#[27=AT03-04\r\n] 2006.175.08:13:21.41#ibcon#*before write, iclass 24, count 2 2006.175.08:13:21.41#ibcon#enter sib2, iclass 24, count 2 2006.175.08:13:21.41#ibcon#flushed, iclass 24, count 2 2006.175.08:13:21.41#ibcon#about to write, iclass 24, count 2 2006.175.08:13:21.41#ibcon#wrote, iclass 24, count 2 2006.175.08:13:21.41#ibcon#about to read 3, iclass 24, count 2 2006.175.08:13:21.44#ibcon#read 3, iclass 24, count 2 2006.175.08:13:21.44#ibcon#about to read 4, iclass 24, count 2 2006.175.08:13:21.44#ibcon#read 4, iclass 24, count 2 2006.175.08:13:21.44#ibcon#about to read 5, iclass 24, count 2 2006.175.08:13:21.44#ibcon#read 5, iclass 24, count 2 2006.175.08:13:21.44#ibcon#about to read 6, iclass 24, count 2 2006.175.08:13:21.44#ibcon#read 6, iclass 24, count 2 2006.175.08:13:21.44#ibcon#end of sib2, iclass 24, count 2 2006.175.08:13:21.44#ibcon#*after write, iclass 24, count 2 2006.175.08:13:21.44#ibcon#*before return 0, iclass 24, count 2 2006.175.08:13:21.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:21.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:13:21.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.08:13:21.44#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:21.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:21.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:21.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:21.56#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:13:21.56#ibcon#first serial, iclass 24, count 0 2006.175.08:13:21.56#ibcon#enter sib2, iclass 24, count 0 2006.175.08:13:21.56#ibcon#flushed, iclass 24, count 0 2006.175.08:13:21.56#ibcon#about to write, iclass 24, count 0 2006.175.08:13:21.56#ibcon#wrote, iclass 24, count 0 2006.175.08:13:21.56#ibcon#about to read 3, iclass 24, count 0 2006.175.08:13:21.58#ibcon#read 3, iclass 24, count 0 2006.175.08:13:21.58#ibcon#about to read 4, iclass 24, count 0 2006.175.08:13:21.58#ibcon#read 4, iclass 24, count 0 2006.175.08:13:21.58#ibcon#about to read 5, iclass 24, count 0 2006.175.08:13:21.58#ibcon#read 5, iclass 24, count 0 2006.175.08:13:21.58#ibcon#about to read 6, iclass 24, count 0 2006.175.08:13:21.58#ibcon#read 6, iclass 24, count 0 2006.175.08:13:21.58#ibcon#end of sib2, iclass 24, count 0 2006.175.08:13:21.58#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:13:21.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:13:21.58#ibcon#[27=USB\r\n] 2006.175.08:13:21.58#ibcon#*before write, iclass 24, count 0 2006.175.08:13:21.58#ibcon#enter sib2, iclass 24, count 0 2006.175.08:13:21.58#ibcon#flushed, iclass 24, count 0 2006.175.08:13:21.58#ibcon#about to write, iclass 24, count 0 2006.175.08:13:21.58#ibcon#wrote, iclass 24, count 0 2006.175.08:13:21.58#ibcon#about to read 3, iclass 24, count 0 2006.175.08:13:21.61#ibcon#read 3, iclass 24, count 0 2006.175.08:13:21.61#ibcon#about to read 4, iclass 24, count 0 2006.175.08:13:21.61#ibcon#read 4, iclass 24, count 0 2006.175.08:13:21.61#ibcon#about to read 5, iclass 24, count 0 2006.175.08:13:21.61#ibcon#read 5, iclass 24, count 0 2006.175.08:13:21.61#ibcon#about to read 6, iclass 24, count 0 2006.175.08:13:21.61#ibcon#read 6, iclass 24, count 0 2006.175.08:13:21.61#ibcon#end of sib2, iclass 24, count 0 2006.175.08:13:21.61#ibcon#*after write, iclass 24, count 0 2006.175.08:13:21.61#ibcon#*before return 0, iclass 24, count 0 2006.175.08:13:21.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:21.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:13:21.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:13:21.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:13:21.61$vc4f8/vblo=4,712.99 2006.175.08:13:21.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.08:13:21.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.08:13:21.61#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:21.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:21.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:21.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:21.61#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:13:21.61#ibcon#first serial, iclass 26, count 0 2006.175.08:13:21.61#ibcon#enter sib2, iclass 26, count 0 2006.175.08:13:21.61#ibcon#flushed, iclass 26, count 0 2006.175.08:13:21.61#ibcon#about to write, iclass 26, count 0 2006.175.08:13:21.61#ibcon#wrote, iclass 26, count 0 2006.175.08:13:21.61#ibcon#about to read 3, iclass 26, count 0 2006.175.08:13:21.63#ibcon#read 3, iclass 26, count 0 2006.175.08:13:21.63#ibcon#about to read 4, iclass 26, count 0 2006.175.08:13:21.63#ibcon#read 4, iclass 26, count 0 2006.175.08:13:21.63#ibcon#about to read 5, iclass 26, count 0 2006.175.08:13:21.63#ibcon#read 5, iclass 26, count 0 2006.175.08:13:21.63#ibcon#about to read 6, iclass 26, count 0 2006.175.08:13:21.63#ibcon#read 6, iclass 26, count 0 2006.175.08:13:21.63#ibcon#end of sib2, iclass 26, count 0 2006.175.08:13:21.63#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:13:21.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:13:21.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:13:21.63#ibcon#*before write, iclass 26, count 0 2006.175.08:13:21.63#ibcon#enter sib2, iclass 26, count 0 2006.175.08:13:21.63#ibcon#flushed, iclass 26, count 0 2006.175.08:13:21.63#ibcon#about to write, iclass 26, count 0 2006.175.08:13:21.63#ibcon#wrote, iclass 26, count 0 2006.175.08:13:21.63#ibcon#about to read 3, iclass 26, count 0 2006.175.08:13:21.67#ibcon#read 3, iclass 26, count 0 2006.175.08:13:21.67#ibcon#about to read 4, iclass 26, count 0 2006.175.08:13:21.67#ibcon#read 4, iclass 26, count 0 2006.175.08:13:21.67#ibcon#about to read 5, iclass 26, count 0 2006.175.08:13:21.67#ibcon#read 5, iclass 26, count 0 2006.175.08:13:21.67#ibcon#about to read 6, iclass 26, count 0 2006.175.08:13:21.67#ibcon#read 6, iclass 26, count 0 2006.175.08:13:21.67#ibcon#end of sib2, iclass 26, count 0 2006.175.08:13:21.67#ibcon#*after write, iclass 26, count 0 2006.175.08:13:21.67#ibcon#*before return 0, iclass 26, count 0 2006.175.08:13:21.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:21.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:13:21.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:13:21.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:13:21.67$vc4f8/vb=4,4 2006.175.08:13:21.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.08:13:21.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.08:13:21.67#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:21.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:21.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:21.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:21.73#ibcon#enter wrdev, iclass 28, count 2 2006.175.08:13:21.73#ibcon#first serial, iclass 28, count 2 2006.175.08:13:21.73#ibcon#enter sib2, iclass 28, count 2 2006.175.08:13:21.73#ibcon#flushed, iclass 28, count 2 2006.175.08:13:21.73#ibcon#about to write, iclass 28, count 2 2006.175.08:13:21.73#ibcon#wrote, iclass 28, count 2 2006.175.08:13:21.73#ibcon#about to read 3, iclass 28, count 2 2006.175.08:13:21.75#ibcon#read 3, iclass 28, count 2 2006.175.08:13:21.75#ibcon#about to read 4, iclass 28, count 2 2006.175.08:13:21.75#ibcon#read 4, iclass 28, count 2 2006.175.08:13:21.75#ibcon#about to read 5, iclass 28, count 2 2006.175.08:13:21.75#ibcon#read 5, iclass 28, count 2 2006.175.08:13:21.75#ibcon#about to read 6, iclass 28, count 2 2006.175.08:13:21.75#ibcon#read 6, iclass 28, count 2 2006.175.08:13:21.75#ibcon#end of sib2, iclass 28, count 2 2006.175.08:13:21.75#ibcon#*mode == 0, iclass 28, count 2 2006.175.08:13:21.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.08:13:21.75#ibcon#[27=AT04-04\r\n] 2006.175.08:13:21.75#ibcon#*before write, iclass 28, count 2 2006.175.08:13:21.75#ibcon#enter sib2, iclass 28, count 2 2006.175.08:13:21.75#ibcon#flushed, iclass 28, count 2 2006.175.08:13:21.75#ibcon#about to write, iclass 28, count 2 2006.175.08:13:21.75#ibcon#wrote, iclass 28, count 2 2006.175.08:13:21.75#ibcon#about to read 3, iclass 28, count 2 2006.175.08:13:21.78#ibcon#read 3, iclass 28, count 2 2006.175.08:13:21.78#ibcon#about to read 4, iclass 28, count 2 2006.175.08:13:21.78#ibcon#read 4, iclass 28, count 2 2006.175.08:13:21.78#ibcon#about to read 5, iclass 28, count 2 2006.175.08:13:21.78#ibcon#read 5, iclass 28, count 2 2006.175.08:13:21.78#ibcon#about to read 6, iclass 28, count 2 2006.175.08:13:21.78#ibcon#read 6, iclass 28, count 2 2006.175.08:13:21.78#ibcon#end of sib2, iclass 28, count 2 2006.175.08:13:21.78#ibcon#*after write, iclass 28, count 2 2006.175.08:13:21.78#ibcon#*before return 0, iclass 28, count 2 2006.175.08:13:21.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:21.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:13:21.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.08:13:21.78#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:21.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:21.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:21.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:21.90#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:13:21.90#ibcon#first serial, iclass 28, count 0 2006.175.08:13:21.90#ibcon#enter sib2, iclass 28, count 0 2006.175.08:13:21.90#ibcon#flushed, iclass 28, count 0 2006.175.08:13:21.90#ibcon#about to write, iclass 28, count 0 2006.175.08:13:21.90#ibcon#wrote, iclass 28, count 0 2006.175.08:13:21.90#ibcon#about to read 3, iclass 28, count 0 2006.175.08:13:21.92#ibcon#read 3, iclass 28, count 0 2006.175.08:13:21.92#ibcon#about to read 4, iclass 28, count 0 2006.175.08:13:21.92#ibcon#read 4, iclass 28, count 0 2006.175.08:13:21.92#ibcon#about to read 5, iclass 28, count 0 2006.175.08:13:21.92#ibcon#read 5, iclass 28, count 0 2006.175.08:13:21.92#ibcon#about to read 6, iclass 28, count 0 2006.175.08:13:21.92#ibcon#read 6, iclass 28, count 0 2006.175.08:13:21.92#ibcon#end of sib2, iclass 28, count 0 2006.175.08:13:21.92#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:13:21.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:13:21.92#ibcon#[27=USB\r\n] 2006.175.08:13:21.92#ibcon#*before write, iclass 28, count 0 2006.175.08:13:21.92#ibcon#enter sib2, iclass 28, count 0 2006.175.08:13:21.92#ibcon#flushed, iclass 28, count 0 2006.175.08:13:21.92#ibcon#about to write, iclass 28, count 0 2006.175.08:13:21.92#ibcon#wrote, iclass 28, count 0 2006.175.08:13:21.92#ibcon#about to read 3, iclass 28, count 0 2006.175.08:13:21.95#ibcon#read 3, iclass 28, count 0 2006.175.08:13:21.95#ibcon#about to read 4, iclass 28, count 0 2006.175.08:13:21.95#ibcon#read 4, iclass 28, count 0 2006.175.08:13:21.95#ibcon#about to read 5, iclass 28, count 0 2006.175.08:13:21.95#ibcon#read 5, iclass 28, count 0 2006.175.08:13:21.95#ibcon#about to read 6, iclass 28, count 0 2006.175.08:13:21.95#ibcon#read 6, iclass 28, count 0 2006.175.08:13:21.95#ibcon#end of sib2, iclass 28, count 0 2006.175.08:13:21.95#ibcon#*after write, iclass 28, count 0 2006.175.08:13:21.95#ibcon#*before return 0, iclass 28, count 0 2006.175.08:13:21.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:21.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:13:21.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:13:21.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:13:21.95$vc4f8/vblo=5,744.99 2006.175.08:13:21.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.08:13:21.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.08:13:21.95#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:21.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:21.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:21.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:21.95#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:13:21.95#ibcon#first serial, iclass 30, count 0 2006.175.08:13:21.95#ibcon#enter sib2, iclass 30, count 0 2006.175.08:13:21.95#ibcon#flushed, iclass 30, count 0 2006.175.08:13:21.95#ibcon#about to write, iclass 30, count 0 2006.175.08:13:21.95#ibcon#wrote, iclass 30, count 0 2006.175.08:13:21.95#ibcon#about to read 3, iclass 30, count 0 2006.175.08:13:21.97#ibcon#read 3, iclass 30, count 0 2006.175.08:13:21.97#ibcon#about to read 4, iclass 30, count 0 2006.175.08:13:21.97#ibcon#read 4, iclass 30, count 0 2006.175.08:13:21.97#ibcon#about to read 5, iclass 30, count 0 2006.175.08:13:21.97#ibcon#read 5, iclass 30, count 0 2006.175.08:13:21.97#ibcon#about to read 6, iclass 30, count 0 2006.175.08:13:21.97#ibcon#read 6, iclass 30, count 0 2006.175.08:13:21.97#ibcon#end of sib2, iclass 30, count 0 2006.175.08:13:21.97#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:13:21.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:13:21.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:13:21.97#ibcon#*before write, iclass 30, count 0 2006.175.08:13:21.97#ibcon#enter sib2, iclass 30, count 0 2006.175.08:13:21.97#ibcon#flushed, iclass 30, count 0 2006.175.08:13:21.97#ibcon#about to write, iclass 30, count 0 2006.175.08:13:21.97#ibcon#wrote, iclass 30, count 0 2006.175.08:13:21.97#ibcon#about to read 3, iclass 30, count 0 2006.175.08:13:22.01#ibcon#read 3, iclass 30, count 0 2006.175.08:13:22.01#ibcon#about to read 4, iclass 30, count 0 2006.175.08:13:22.01#ibcon#read 4, iclass 30, count 0 2006.175.08:13:22.01#ibcon#about to read 5, iclass 30, count 0 2006.175.08:13:22.01#ibcon#read 5, iclass 30, count 0 2006.175.08:13:22.01#ibcon#about to read 6, iclass 30, count 0 2006.175.08:13:22.01#ibcon#read 6, iclass 30, count 0 2006.175.08:13:22.01#ibcon#end of sib2, iclass 30, count 0 2006.175.08:13:22.01#ibcon#*after write, iclass 30, count 0 2006.175.08:13:22.01#ibcon#*before return 0, iclass 30, count 0 2006.175.08:13:22.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:22.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:13:22.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:13:22.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:13:22.01$vc4f8/vb=5,4 2006.175.08:13:22.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.08:13:22.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.08:13:22.01#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:22.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:22.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:22.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:22.07#ibcon#enter wrdev, iclass 32, count 2 2006.175.08:13:22.07#ibcon#first serial, iclass 32, count 2 2006.175.08:13:22.07#ibcon#enter sib2, iclass 32, count 2 2006.175.08:13:22.07#ibcon#flushed, iclass 32, count 2 2006.175.08:13:22.07#ibcon#about to write, iclass 32, count 2 2006.175.08:13:22.07#ibcon#wrote, iclass 32, count 2 2006.175.08:13:22.07#ibcon#about to read 3, iclass 32, count 2 2006.175.08:13:22.09#ibcon#read 3, iclass 32, count 2 2006.175.08:13:22.09#ibcon#about to read 4, iclass 32, count 2 2006.175.08:13:22.09#ibcon#read 4, iclass 32, count 2 2006.175.08:13:22.09#ibcon#about to read 5, iclass 32, count 2 2006.175.08:13:22.09#ibcon#read 5, iclass 32, count 2 2006.175.08:13:22.09#ibcon#about to read 6, iclass 32, count 2 2006.175.08:13:22.09#ibcon#read 6, iclass 32, count 2 2006.175.08:13:22.09#ibcon#end of sib2, iclass 32, count 2 2006.175.08:13:22.09#ibcon#*mode == 0, iclass 32, count 2 2006.175.08:13:22.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.08:13:22.09#ibcon#[27=AT05-04\r\n] 2006.175.08:13:22.09#ibcon#*before write, iclass 32, count 2 2006.175.08:13:22.09#ibcon#enter sib2, iclass 32, count 2 2006.175.08:13:22.09#ibcon#flushed, iclass 32, count 2 2006.175.08:13:22.09#ibcon#about to write, iclass 32, count 2 2006.175.08:13:22.09#ibcon#wrote, iclass 32, count 2 2006.175.08:13:22.09#ibcon#about to read 3, iclass 32, count 2 2006.175.08:13:22.12#ibcon#read 3, iclass 32, count 2 2006.175.08:13:22.12#ibcon#about to read 4, iclass 32, count 2 2006.175.08:13:22.12#ibcon#read 4, iclass 32, count 2 2006.175.08:13:22.12#ibcon#about to read 5, iclass 32, count 2 2006.175.08:13:22.12#ibcon#read 5, iclass 32, count 2 2006.175.08:13:22.12#ibcon#about to read 6, iclass 32, count 2 2006.175.08:13:22.12#ibcon#read 6, iclass 32, count 2 2006.175.08:13:22.12#ibcon#end of sib2, iclass 32, count 2 2006.175.08:13:22.12#ibcon#*after write, iclass 32, count 2 2006.175.08:13:22.12#ibcon#*before return 0, iclass 32, count 2 2006.175.08:13:22.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:22.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:13:22.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.08:13:22.12#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:22.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:22.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:22.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:22.24#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:13:22.24#ibcon#first serial, iclass 32, count 0 2006.175.08:13:22.24#ibcon#enter sib2, iclass 32, count 0 2006.175.08:13:22.24#ibcon#flushed, iclass 32, count 0 2006.175.08:13:22.24#ibcon#about to write, iclass 32, count 0 2006.175.08:13:22.24#ibcon#wrote, iclass 32, count 0 2006.175.08:13:22.24#ibcon#about to read 3, iclass 32, count 0 2006.175.08:13:22.26#ibcon#read 3, iclass 32, count 0 2006.175.08:13:22.26#ibcon#about to read 4, iclass 32, count 0 2006.175.08:13:22.26#ibcon#read 4, iclass 32, count 0 2006.175.08:13:22.26#ibcon#about to read 5, iclass 32, count 0 2006.175.08:13:22.26#ibcon#read 5, iclass 32, count 0 2006.175.08:13:22.26#ibcon#about to read 6, iclass 32, count 0 2006.175.08:13:22.26#ibcon#read 6, iclass 32, count 0 2006.175.08:13:22.26#ibcon#end of sib2, iclass 32, count 0 2006.175.08:13:22.26#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:13:22.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:13:22.26#ibcon#[27=USB\r\n] 2006.175.08:13:22.26#ibcon#*before write, iclass 32, count 0 2006.175.08:13:22.26#ibcon#enter sib2, iclass 32, count 0 2006.175.08:13:22.26#ibcon#flushed, iclass 32, count 0 2006.175.08:13:22.26#ibcon#about to write, iclass 32, count 0 2006.175.08:13:22.26#ibcon#wrote, iclass 32, count 0 2006.175.08:13:22.26#ibcon#about to read 3, iclass 32, count 0 2006.175.08:13:22.29#ibcon#read 3, iclass 32, count 0 2006.175.08:13:22.29#ibcon#about to read 4, iclass 32, count 0 2006.175.08:13:22.29#ibcon#read 4, iclass 32, count 0 2006.175.08:13:22.29#ibcon#about to read 5, iclass 32, count 0 2006.175.08:13:22.29#ibcon#read 5, iclass 32, count 0 2006.175.08:13:22.29#ibcon#about to read 6, iclass 32, count 0 2006.175.08:13:22.29#ibcon#read 6, iclass 32, count 0 2006.175.08:13:22.29#ibcon#end of sib2, iclass 32, count 0 2006.175.08:13:22.29#ibcon#*after write, iclass 32, count 0 2006.175.08:13:22.29#ibcon#*before return 0, iclass 32, count 0 2006.175.08:13:22.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:22.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:13:22.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:13:22.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:13:22.29$vc4f8/vblo=6,752.99 2006.175.08:13:22.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.08:13:22.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.08:13:22.29#ibcon#ireg 17 cls_cnt 0 2006.175.08:13:22.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:22.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:22.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:22.29#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:13:22.29#ibcon#first serial, iclass 34, count 0 2006.175.08:13:22.29#ibcon#enter sib2, iclass 34, count 0 2006.175.08:13:22.29#ibcon#flushed, iclass 34, count 0 2006.175.08:13:22.29#ibcon#about to write, iclass 34, count 0 2006.175.08:13:22.29#ibcon#wrote, iclass 34, count 0 2006.175.08:13:22.29#ibcon#about to read 3, iclass 34, count 0 2006.175.08:13:22.31#ibcon#read 3, iclass 34, count 0 2006.175.08:13:22.31#ibcon#about to read 4, iclass 34, count 0 2006.175.08:13:22.31#ibcon#read 4, iclass 34, count 0 2006.175.08:13:22.31#ibcon#about to read 5, iclass 34, count 0 2006.175.08:13:22.31#ibcon#read 5, iclass 34, count 0 2006.175.08:13:22.31#ibcon#about to read 6, iclass 34, count 0 2006.175.08:13:22.31#ibcon#read 6, iclass 34, count 0 2006.175.08:13:22.31#ibcon#end of sib2, iclass 34, count 0 2006.175.08:13:22.31#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:13:22.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:13:22.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:13:22.31#ibcon#*before write, iclass 34, count 0 2006.175.08:13:22.31#ibcon#enter sib2, iclass 34, count 0 2006.175.08:13:22.31#ibcon#flushed, iclass 34, count 0 2006.175.08:13:22.31#ibcon#about to write, iclass 34, count 0 2006.175.08:13:22.31#ibcon#wrote, iclass 34, count 0 2006.175.08:13:22.31#ibcon#about to read 3, iclass 34, count 0 2006.175.08:13:22.35#ibcon#read 3, iclass 34, count 0 2006.175.08:13:22.35#ibcon#about to read 4, iclass 34, count 0 2006.175.08:13:22.35#ibcon#read 4, iclass 34, count 0 2006.175.08:13:22.35#ibcon#about to read 5, iclass 34, count 0 2006.175.08:13:22.35#ibcon#read 5, iclass 34, count 0 2006.175.08:13:22.35#ibcon#about to read 6, iclass 34, count 0 2006.175.08:13:22.35#ibcon#read 6, iclass 34, count 0 2006.175.08:13:22.35#ibcon#end of sib2, iclass 34, count 0 2006.175.08:13:22.35#ibcon#*after write, iclass 34, count 0 2006.175.08:13:22.35#ibcon#*before return 0, iclass 34, count 0 2006.175.08:13:22.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:22.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:13:22.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:13:22.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:13:22.35$vc4f8/vb=6,4 2006.175.08:13:22.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.08:13:22.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.08:13:22.35#ibcon#ireg 11 cls_cnt 2 2006.175.08:13:22.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:22.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:22.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:22.41#ibcon#enter wrdev, iclass 36, count 2 2006.175.08:13:22.41#ibcon#first serial, iclass 36, count 2 2006.175.08:13:22.41#ibcon#enter sib2, iclass 36, count 2 2006.175.08:13:22.41#ibcon#flushed, iclass 36, count 2 2006.175.08:13:22.41#ibcon#about to write, iclass 36, count 2 2006.175.08:13:22.41#ibcon#wrote, iclass 36, count 2 2006.175.08:13:22.41#ibcon#about to read 3, iclass 36, count 2 2006.175.08:13:22.43#ibcon#read 3, iclass 36, count 2 2006.175.08:13:22.43#ibcon#about to read 4, iclass 36, count 2 2006.175.08:13:22.43#ibcon#read 4, iclass 36, count 2 2006.175.08:13:22.43#ibcon#about to read 5, iclass 36, count 2 2006.175.08:13:22.43#ibcon#read 5, iclass 36, count 2 2006.175.08:13:22.43#ibcon#about to read 6, iclass 36, count 2 2006.175.08:13:22.43#ibcon#read 6, iclass 36, count 2 2006.175.08:13:22.43#ibcon#end of sib2, iclass 36, count 2 2006.175.08:13:22.43#ibcon#*mode == 0, iclass 36, count 2 2006.175.08:13:22.43#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.08:13:22.43#ibcon#[27=AT06-04\r\n] 2006.175.08:13:22.43#ibcon#*before write, iclass 36, count 2 2006.175.08:13:22.43#ibcon#enter sib2, iclass 36, count 2 2006.175.08:13:22.43#ibcon#flushed, iclass 36, count 2 2006.175.08:13:22.43#ibcon#about to write, iclass 36, count 2 2006.175.08:13:22.43#ibcon#wrote, iclass 36, count 2 2006.175.08:13:22.43#ibcon#about to read 3, iclass 36, count 2 2006.175.08:13:22.46#ibcon#read 3, iclass 36, count 2 2006.175.08:13:22.46#ibcon#about to read 4, iclass 36, count 2 2006.175.08:13:22.46#ibcon#read 4, iclass 36, count 2 2006.175.08:13:22.46#ibcon#about to read 5, iclass 36, count 2 2006.175.08:13:22.46#ibcon#read 5, iclass 36, count 2 2006.175.08:13:22.46#ibcon#about to read 6, iclass 36, count 2 2006.175.08:13:22.46#ibcon#read 6, iclass 36, count 2 2006.175.08:13:22.46#ibcon#end of sib2, iclass 36, count 2 2006.175.08:13:22.46#ibcon#*after write, iclass 36, count 2 2006.175.08:13:22.46#ibcon#*before return 0, iclass 36, count 2 2006.175.08:13:22.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:22.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:13:22.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.08:13:22.46#ibcon#ireg 7 cls_cnt 0 2006.175.08:13:22.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:22.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:22.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:22.58#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:13:22.58#ibcon#first serial, iclass 36, count 0 2006.175.08:13:22.58#ibcon#enter sib2, iclass 36, count 0 2006.175.08:13:22.58#ibcon#flushed, iclass 36, count 0 2006.175.08:13:22.58#ibcon#about to write, iclass 36, count 0 2006.175.08:13:22.58#ibcon#wrote, iclass 36, count 0 2006.175.08:13:22.58#ibcon#about to read 3, iclass 36, count 0 2006.175.08:13:22.60#ibcon#read 3, iclass 36, count 0 2006.175.08:13:22.60#ibcon#about to read 4, iclass 36, count 0 2006.175.08:13:22.60#ibcon#read 4, iclass 36, count 0 2006.175.08:13:22.60#ibcon#about to read 5, iclass 36, count 0 2006.175.08:13:22.60#ibcon#read 5, iclass 36, count 0 2006.175.08:13:22.60#ibcon#about to read 6, iclass 36, count 0 2006.175.08:13:22.60#ibcon#read 6, iclass 36, count 0 2006.175.08:13:22.60#ibcon#end of sib2, iclass 36, count 0 2006.175.08:13:22.60#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:13:22.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:13:22.60#ibcon#[27=USB\r\n] 2006.175.08:13:22.60#ibcon#*before write, iclass 36, count 0 2006.175.08:13:22.60#ibcon#enter sib2, iclass 36, count 0 2006.175.08:13:22.60#ibcon#flushed, iclass 36, count 0 2006.175.08:13:22.60#ibcon#about to write, iclass 36, count 0 2006.175.08:13:22.60#ibcon#wrote, iclass 36, count 0 2006.175.08:13:22.60#ibcon#about to read 3, iclass 36, count 0 2006.175.08:13:22.63#ibcon#read 3, iclass 36, count 0 2006.175.08:13:22.63#ibcon#about to read 4, iclass 36, count 0 2006.175.08:13:22.63#ibcon#read 4, iclass 36, count 0 2006.175.08:13:22.63#ibcon#about to read 5, iclass 36, count 0 2006.175.08:13:22.63#ibcon#read 5, iclass 36, count 0 2006.175.08:13:22.63#ibcon#about to read 6, iclass 36, count 0 2006.175.08:13:22.63#ibcon#read 6, iclass 36, count 0 2006.175.08:13:22.63#ibcon#end of sib2, iclass 36, count 0 2006.175.08:13:22.63#ibcon#*after write, iclass 36, count 0 2006.175.08:13:22.63#ibcon#*before return 0, iclass 36, count 0 2006.175.08:13:22.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:22.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:13:22.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:13:22.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:13:22.63$vc4f8/vabw=wide 2006.175.08:13:22.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.08:13:22.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.08:13:22.63#ibcon#ireg 8 cls_cnt 0 2006.175.08:13:22.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:22.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:22.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:22.63#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:13:22.63#ibcon#first serial, iclass 38, count 0 2006.175.08:13:22.63#ibcon#enter sib2, iclass 38, count 0 2006.175.08:13:22.63#ibcon#flushed, iclass 38, count 0 2006.175.08:13:22.63#ibcon#about to write, iclass 38, count 0 2006.175.08:13:22.63#ibcon#wrote, iclass 38, count 0 2006.175.08:13:22.63#ibcon#about to read 3, iclass 38, count 0 2006.175.08:13:22.65#ibcon#read 3, iclass 38, count 0 2006.175.08:13:22.65#ibcon#about to read 4, iclass 38, count 0 2006.175.08:13:22.65#ibcon#read 4, iclass 38, count 0 2006.175.08:13:22.65#ibcon#about to read 5, iclass 38, count 0 2006.175.08:13:22.65#ibcon#read 5, iclass 38, count 0 2006.175.08:13:22.65#ibcon#about to read 6, iclass 38, count 0 2006.175.08:13:22.65#ibcon#read 6, iclass 38, count 0 2006.175.08:13:22.65#ibcon#end of sib2, iclass 38, count 0 2006.175.08:13:22.65#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:13:22.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:13:22.65#ibcon#[25=BW32\r\n] 2006.175.08:13:22.65#ibcon#*before write, iclass 38, count 0 2006.175.08:13:22.65#ibcon#enter sib2, iclass 38, count 0 2006.175.08:13:22.65#ibcon#flushed, iclass 38, count 0 2006.175.08:13:22.65#ibcon#about to write, iclass 38, count 0 2006.175.08:13:22.65#ibcon#wrote, iclass 38, count 0 2006.175.08:13:22.65#ibcon#about to read 3, iclass 38, count 0 2006.175.08:13:22.68#ibcon#read 3, iclass 38, count 0 2006.175.08:13:22.68#ibcon#about to read 4, iclass 38, count 0 2006.175.08:13:22.68#ibcon#read 4, iclass 38, count 0 2006.175.08:13:22.68#ibcon#about to read 5, iclass 38, count 0 2006.175.08:13:22.68#ibcon#read 5, iclass 38, count 0 2006.175.08:13:22.68#ibcon#about to read 6, iclass 38, count 0 2006.175.08:13:22.68#ibcon#read 6, iclass 38, count 0 2006.175.08:13:22.68#ibcon#end of sib2, iclass 38, count 0 2006.175.08:13:22.68#ibcon#*after write, iclass 38, count 0 2006.175.08:13:22.68#ibcon#*before return 0, iclass 38, count 0 2006.175.08:13:22.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:22.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:13:22.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:13:22.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:13:22.68$vc4f8/vbbw=wide 2006.175.08:13:22.68#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.08:13:22.68#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.08:13:22.68#ibcon#ireg 8 cls_cnt 0 2006.175.08:13:22.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:13:22.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:13:22.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:13:22.75#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:13:22.75#ibcon#first serial, iclass 40, count 0 2006.175.08:13:22.75#ibcon#enter sib2, iclass 40, count 0 2006.175.08:13:22.75#ibcon#flushed, iclass 40, count 0 2006.175.08:13:22.75#ibcon#about to write, iclass 40, count 0 2006.175.08:13:22.75#ibcon#wrote, iclass 40, count 0 2006.175.08:13:22.75#ibcon#about to read 3, iclass 40, count 0 2006.175.08:13:22.77#ibcon#read 3, iclass 40, count 0 2006.175.08:13:22.77#ibcon#about to read 4, iclass 40, count 0 2006.175.08:13:22.77#ibcon#read 4, iclass 40, count 0 2006.175.08:13:22.77#ibcon#about to read 5, iclass 40, count 0 2006.175.08:13:22.77#ibcon#read 5, iclass 40, count 0 2006.175.08:13:22.77#ibcon#about to read 6, iclass 40, count 0 2006.175.08:13:22.77#ibcon#read 6, iclass 40, count 0 2006.175.08:13:22.77#ibcon#end of sib2, iclass 40, count 0 2006.175.08:13:22.77#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:13:22.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:13:22.77#ibcon#[27=BW32\r\n] 2006.175.08:13:22.77#ibcon#*before write, iclass 40, count 0 2006.175.08:13:22.77#ibcon#enter sib2, iclass 40, count 0 2006.175.08:13:22.77#ibcon#flushed, iclass 40, count 0 2006.175.08:13:22.77#ibcon#about to write, iclass 40, count 0 2006.175.08:13:22.77#ibcon#wrote, iclass 40, count 0 2006.175.08:13:22.77#ibcon#about to read 3, iclass 40, count 0 2006.175.08:13:22.80#ibcon#read 3, iclass 40, count 0 2006.175.08:13:22.80#ibcon#about to read 4, iclass 40, count 0 2006.175.08:13:22.80#ibcon#read 4, iclass 40, count 0 2006.175.08:13:22.80#ibcon#about to read 5, iclass 40, count 0 2006.175.08:13:22.80#ibcon#read 5, iclass 40, count 0 2006.175.08:13:22.80#ibcon#about to read 6, iclass 40, count 0 2006.175.08:13:22.80#ibcon#read 6, iclass 40, count 0 2006.175.08:13:22.80#ibcon#end of sib2, iclass 40, count 0 2006.175.08:13:22.80#ibcon#*after write, iclass 40, count 0 2006.175.08:13:22.80#ibcon#*before return 0, iclass 40, count 0 2006.175.08:13:22.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:13:22.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:13:22.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:13:22.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:13:22.80$4f8m12a/ifd4f 2006.175.08:13:22.80$ifd4f/lo= 2006.175.08:13:22.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:13:22.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:13:22.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:13:22.80$ifd4f/patch= 2006.175.08:13:22.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:13:22.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:13:22.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:13:22.80$4f8m12a/"form=m,16.000,1:2 2006.175.08:13:22.80$4f8m12a/"tpicd 2006.175.08:13:22.80$4f8m12a/echo=off 2006.175.08:13:22.80$4f8m12a/xlog=off 2006.175.08:13:22.80:!2006.175.08:13:50 2006.175.08:13:28.14#trakl#Source acquired 2006.175.08:13:29.14#flagr#flagr/antenna,acquired 2006.175.08:13:50.00:preob 2006.175.08:13:51.14/onsource/TRACKING 2006.175.08:13:51.14:!2006.175.08:14:00 2006.175.08:14:00.00:data_valid=on 2006.175.08:14:00.00:midob 2006.175.08:14:00.14/onsource/TRACKING 2006.175.08:14:00.14/wx/25.76,1007.3,71 2006.175.08:14:00.21/cable/+6.4794E-03 2006.175.08:14:01.30/va/01,08,usb,yes,28,30 2006.175.08:14:01.30/va/02,07,usb,yes,29,30 2006.175.08:14:01.30/va/03,06,usb,yes,30,30 2006.175.08:14:01.30/va/04,07,usb,yes,29,31 2006.175.08:14:01.30/va/05,07,usb,yes,30,31 2006.175.08:14:01.30/va/06,06,usb,yes,29,28 2006.175.08:14:01.30/va/07,06,usb,yes,29,29 2006.175.08:14:01.30/va/08,06,usb,yes,31,31 2006.175.08:14:01.53/valo/01,532.99,yes,locked 2006.175.08:14:01.53/valo/02,572.99,yes,locked 2006.175.08:14:01.53/valo/03,672.99,yes,locked 2006.175.08:14:01.53/valo/04,832.99,yes,locked 2006.175.08:14:01.53/valo/05,652.99,yes,locked 2006.175.08:14:01.53/valo/06,772.99,yes,locked 2006.175.08:14:01.53/valo/07,832.99,yes,locked 2006.175.08:14:01.53/valo/08,852.99,yes,locked 2006.175.08:14:02.62/vb/01,04,usb,yes,29,27 2006.175.08:14:02.62/vb/02,04,usb,yes,30,32 2006.175.08:14:02.62/vb/03,04,usb,yes,27,30 2006.175.08:14:02.62/vb/04,04,usb,yes,28,28 2006.175.08:14:02.62/vb/05,04,usb,yes,26,30 2006.175.08:14:02.62/vb/06,04,usb,yes,27,30 2006.175.08:14:02.62/vb/07,04,usb,yes,29,29 2006.175.08:14:02.62/vb/08,04,usb,yes,27,30 2006.175.08:14:02.85/vblo/01,632.99,yes,locked 2006.175.08:14:02.85/vblo/02,640.99,yes,locked 2006.175.08:14:02.85/vblo/03,656.99,yes,locked 2006.175.08:14:02.85/vblo/04,712.99,yes,locked 2006.175.08:14:02.85/vblo/05,744.99,yes,locked 2006.175.08:14:02.85/vblo/06,752.99,yes,locked 2006.175.08:14:02.85/vblo/07,734.99,yes,locked 2006.175.08:14:02.85/vblo/08,744.99,yes,locked 2006.175.08:14:03.00/vabw/8 2006.175.08:14:03.15/vbbw/8 2006.175.08:14:03.24/xfe/off,on,15.2 2006.175.08:14:03.63/ifatt/23,28,28,28 2006.175.08:14:04.07/fmout-gps/S +3.81E-07 2006.175.08:14:04.15:!2006.175.08:15:00 2006.175.08:15:00.00:data_valid=off 2006.175.08:15:00.00:postob 2006.175.08:15:00.20/cable/+6.4790E-03 2006.175.08:15:00.20/wx/25.75,1007.3,71 2006.175.08:15:01.07/fmout-gps/S +3.80E-07 2006.175.08:15:01.07:scan_name=175-0815,k06175,60 2006.175.08:15:01.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.175.08:15:01.14#flagr#flagr/antenna,new-source 2006.175.08:15:02.14:checkk5 2006.175.08:15:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:15:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:15:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:15:03.67/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:15:04.04/chk_obsdata//k5ts1/T1750814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:15:04.41/chk_obsdata//k5ts2/T1750814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:15:04.78/chk_obsdata//k5ts3/T1750814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:15:05.16/chk_obsdata//k5ts4/T1750814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:15:05.85/k5log//k5ts1_log_newline 2006.175.08:15:06.55/k5log//k5ts2_log_newline 2006.175.08:15:07.24/k5log//k5ts3_log_newline 2006.175.08:15:07.93/k5log//k5ts4_log_newline 2006.175.08:15:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:15:07.96:4f8m12a=2 2006.175.08:15:07.96$4f8m12a/echo=on 2006.175.08:15:07.96$4f8m12a/pcalon 2006.175.08:15:07.96$pcalon/"no phase cal control is implemented here 2006.175.08:15:07.96$4f8m12a/"tpicd=stop 2006.175.08:15:07.96$4f8m12a/vc4f8 2006.175.08:15:07.96$vc4f8/valo=1,532.99 2006.175.08:15:07.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.08:15:07.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.08:15:07.96#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:07.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:07.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:07.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:07.96#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:15:07.96#ibcon#first serial, iclass 15, count 0 2006.175.08:15:07.96#ibcon#enter sib2, iclass 15, count 0 2006.175.08:15:07.96#ibcon#flushed, iclass 15, count 0 2006.175.08:15:07.96#ibcon#about to write, iclass 15, count 0 2006.175.08:15:07.96#ibcon#wrote, iclass 15, count 0 2006.175.08:15:07.96#ibcon#about to read 3, iclass 15, count 0 2006.175.08:15:08.01#ibcon#read 3, iclass 15, count 0 2006.175.08:15:08.01#ibcon#about to read 4, iclass 15, count 0 2006.175.08:15:08.01#ibcon#read 4, iclass 15, count 0 2006.175.08:15:08.01#ibcon#about to read 5, iclass 15, count 0 2006.175.08:15:08.01#ibcon#read 5, iclass 15, count 0 2006.175.08:15:08.01#ibcon#about to read 6, iclass 15, count 0 2006.175.08:15:08.01#ibcon#read 6, iclass 15, count 0 2006.175.08:15:08.01#ibcon#end of sib2, iclass 15, count 0 2006.175.08:15:08.01#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:15:08.01#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:15:08.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:15:08.01#ibcon#*before write, iclass 15, count 0 2006.175.08:15:08.01#ibcon#enter sib2, iclass 15, count 0 2006.175.08:15:08.01#ibcon#flushed, iclass 15, count 0 2006.175.08:15:08.01#ibcon#about to write, iclass 15, count 0 2006.175.08:15:08.01#ibcon#wrote, iclass 15, count 0 2006.175.08:15:08.01#ibcon#about to read 3, iclass 15, count 0 2006.175.08:15:08.05#ibcon#read 3, iclass 15, count 0 2006.175.08:15:08.05#ibcon#about to read 4, iclass 15, count 0 2006.175.08:15:08.05#ibcon#read 4, iclass 15, count 0 2006.175.08:15:08.05#ibcon#about to read 5, iclass 15, count 0 2006.175.08:15:08.05#ibcon#read 5, iclass 15, count 0 2006.175.08:15:08.05#ibcon#about to read 6, iclass 15, count 0 2006.175.08:15:08.05#ibcon#read 6, iclass 15, count 0 2006.175.08:15:08.05#ibcon#end of sib2, iclass 15, count 0 2006.175.08:15:08.05#ibcon#*after write, iclass 15, count 0 2006.175.08:15:08.05#ibcon#*before return 0, iclass 15, count 0 2006.175.08:15:08.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:08.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:08.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:15:08.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:15:08.05$vc4f8/va=1,8 2006.175.08:15:08.05#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.08:15:08.05#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.08:15:08.05#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:08.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:08.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:08.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:08.05#ibcon#enter wrdev, iclass 17, count 2 2006.175.08:15:08.05#ibcon#first serial, iclass 17, count 2 2006.175.08:15:08.05#ibcon#enter sib2, iclass 17, count 2 2006.175.08:15:08.05#ibcon#flushed, iclass 17, count 2 2006.175.08:15:08.05#ibcon#about to write, iclass 17, count 2 2006.175.08:15:08.05#ibcon#wrote, iclass 17, count 2 2006.175.08:15:08.05#ibcon#about to read 3, iclass 17, count 2 2006.175.08:15:08.07#ibcon#read 3, iclass 17, count 2 2006.175.08:15:08.07#ibcon#about to read 4, iclass 17, count 2 2006.175.08:15:08.07#ibcon#read 4, iclass 17, count 2 2006.175.08:15:08.07#ibcon#about to read 5, iclass 17, count 2 2006.175.08:15:08.07#ibcon#read 5, iclass 17, count 2 2006.175.08:15:08.07#ibcon#about to read 6, iclass 17, count 2 2006.175.08:15:08.07#ibcon#read 6, iclass 17, count 2 2006.175.08:15:08.07#ibcon#end of sib2, iclass 17, count 2 2006.175.08:15:08.07#ibcon#*mode == 0, iclass 17, count 2 2006.175.08:15:08.07#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.08:15:08.07#ibcon#[25=AT01-08\r\n] 2006.175.08:15:08.07#ibcon#*before write, iclass 17, count 2 2006.175.08:15:08.07#ibcon#enter sib2, iclass 17, count 2 2006.175.08:15:08.07#ibcon#flushed, iclass 17, count 2 2006.175.08:15:08.07#ibcon#about to write, iclass 17, count 2 2006.175.08:15:08.07#ibcon#wrote, iclass 17, count 2 2006.175.08:15:08.07#ibcon#about to read 3, iclass 17, count 2 2006.175.08:15:08.10#ibcon#read 3, iclass 17, count 2 2006.175.08:15:08.10#ibcon#about to read 4, iclass 17, count 2 2006.175.08:15:08.10#ibcon#read 4, iclass 17, count 2 2006.175.08:15:08.10#ibcon#about to read 5, iclass 17, count 2 2006.175.08:15:08.10#ibcon#read 5, iclass 17, count 2 2006.175.08:15:08.10#ibcon#about to read 6, iclass 17, count 2 2006.175.08:15:08.10#ibcon#read 6, iclass 17, count 2 2006.175.08:15:08.10#ibcon#end of sib2, iclass 17, count 2 2006.175.08:15:08.10#ibcon#*after write, iclass 17, count 2 2006.175.08:15:08.10#ibcon#*before return 0, iclass 17, count 2 2006.175.08:15:08.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:08.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:08.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.08:15:08.10#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:08.10#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:08.22#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:08.22#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:08.22#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:15:08.22#ibcon#first serial, iclass 17, count 0 2006.175.08:15:08.22#ibcon#enter sib2, iclass 17, count 0 2006.175.08:15:08.22#ibcon#flushed, iclass 17, count 0 2006.175.08:15:08.22#ibcon#about to write, iclass 17, count 0 2006.175.08:15:08.22#ibcon#wrote, iclass 17, count 0 2006.175.08:15:08.22#ibcon#about to read 3, iclass 17, count 0 2006.175.08:15:08.24#ibcon#read 3, iclass 17, count 0 2006.175.08:15:08.24#ibcon#about to read 4, iclass 17, count 0 2006.175.08:15:08.24#ibcon#read 4, iclass 17, count 0 2006.175.08:15:08.24#ibcon#about to read 5, iclass 17, count 0 2006.175.08:15:08.24#ibcon#read 5, iclass 17, count 0 2006.175.08:15:08.24#ibcon#about to read 6, iclass 17, count 0 2006.175.08:15:08.24#ibcon#read 6, iclass 17, count 0 2006.175.08:15:08.24#ibcon#end of sib2, iclass 17, count 0 2006.175.08:15:08.24#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:15:08.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:15:08.24#ibcon#[25=USB\r\n] 2006.175.08:15:08.24#ibcon#*before write, iclass 17, count 0 2006.175.08:15:08.24#ibcon#enter sib2, iclass 17, count 0 2006.175.08:15:08.24#ibcon#flushed, iclass 17, count 0 2006.175.08:15:08.24#ibcon#about to write, iclass 17, count 0 2006.175.08:15:08.24#ibcon#wrote, iclass 17, count 0 2006.175.08:15:08.24#ibcon#about to read 3, iclass 17, count 0 2006.175.08:15:08.27#ibcon#read 3, iclass 17, count 0 2006.175.08:15:08.27#ibcon#about to read 4, iclass 17, count 0 2006.175.08:15:08.27#ibcon#read 4, iclass 17, count 0 2006.175.08:15:08.27#ibcon#about to read 5, iclass 17, count 0 2006.175.08:15:08.27#ibcon#read 5, iclass 17, count 0 2006.175.08:15:08.27#ibcon#about to read 6, iclass 17, count 0 2006.175.08:15:08.27#ibcon#read 6, iclass 17, count 0 2006.175.08:15:08.27#ibcon#end of sib2, iclass 17, count 0 2006.175.08:15:08.27#ibcon#*after write, iclass 17, count 0 2006.175.08:15:08.27#ibcon#*before return 0, iclass 17, count 0 2006.175.08:15:08.27#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:08.27#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:08.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:15:08.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:15:08.27$vc4f8/valo=2,572.99 2006.175.08:15:08.27#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.08:15:08.27#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.08:15:08.27#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:08.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:08.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:08.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:08.27#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:15:08.27#ibcon#first serial, iclass 19, count 0 2006.175.08:15:08.27#ibcon#enter sib2, iclass 19, count 0 2006.175.08:15:08.27#ibcon#flushed, iclass 19, count 0 2006.175.08:15:08.27#ibcon#about to write, iclass 19, count 0 2006.175.08:15:08.27#ibcon#wrote, iclass 19, count 0 2006.175.08:15:08.27#ibcon#about to read 3, iclass 19, count 0 2006.175.08:15:08.29#ibcon#read 3, iclass 19, count 0 2006.175.08:15:08.29#ibcon#about to read 4, iclass 19, count 0 2006.175.08:15:08.29#ibcon#read 4, iclass 19, count 0 2006.175.08:15:08.29#ibcon#about to read 5, iclass 19, count 0 2006.175.08:15:08.29#ibcon#read 5, iclass 19, count 0 2006.175.08:15:08.29#ibcon#about to read 6, iclass 19, count 0 2006.175.08:15:08.29#ibcon#read 6, iclass 19, count 0 2006.175.08:15:08.29#ibcon#end of sib2, iclass 19, count 0 2006.175.08:15:08.29#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:15:08.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:15:08.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:15:08.29#ibcon#*before write, iclass 19, count 0 2006.175.08:15:08.29#ibcon#enter sib2, iclass 19, count 0 2006.175.08:15:08.29#ibcon#flushed, iclass 19, count 0 2006.175.08:15:08.29#ibcon#about to write, iclass 19, count 0 2006.175.08:15:08.29#ibcon#wrote, iclass 19, count 0 2006.175.08:15:08.29#ibcon#about to read 3, iclass 19, count 0 2006.175.08:15:08.33#ibcon#read 3, iclass 19, count 0 2006.175.08:15:08.33#ibcon#about to read 4, iclass 19, count 0 2006.175.08:15:08.33#ibcon#read 4, iclass 19, count 0 2006.175.08:15:08.33#ibcon#about to read 5, iclass 19, count 0 2006.175.08:15:08.33#ibcon#read 5, iclass 19, count 0 2006.175.08:15:08.33#ibcon#about to read 6, iclass 19, count 0 2006.175.08:15:08.33#ibcon#read 6, iclass 19, count 0 2006.175.08:15:08.33#ibcon#end of sib2, iclass 19, count 0 2006.175.08:15:08.33#ibcon#*after write, iclass 19, count 0 2006.175.08:15:08.33#ibcon#*before return 0, iclass 19, count 0 2006.175.08:15:08.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:08.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:08.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:15:08.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:15:08.33$vc4f8/va=2,7 2006.175.08:15:08.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.08:15:08.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.08:15:08.33#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:08.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:08.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:08.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:08.39#ibcon#enter wrdev, iclass 21, count 2 2006.175.08:15:08.39#ibcon#first serial, iclass 21, count 2 2006.175.08:15:08.39#ibcon#enter sib2, iclass 21, count 2 2006.175.08:15:08.39#ibcon#flushed, iclass 21, count 2 2006.175.08:15:08.39#ibcon#about to write, iclass 21, count 2 2006.175.08:15:08.39#ibcon#wrote, iclass 21, count 2 2006.175.08:15:08.39#ibcon#about to read 3, iclass 21, count 2 2006.175.08:15:08.41#ibcon#read 3, iclass 21, count 2 2006.175.08:15:08.41#ibcon#about to read 4, iclass 21, count 2 2006.175.08:15:08.41#ibcon#read 4, iclass 21, count 2 2006.175.08:15:08.41#ibcon#about to read 5, iclass 21, count 2 2006.175.08:15:08.41#ibcon#read 5, iclass 21, count 2 2006.175.08:15:08.41#ibcon#about to read 6, iclass 21, count 2 2006.175.08:15:08.41#ibcon#read 6, iclass 21, count 2 2006.175.08:15:08.41#ibcon#end of sib2, iclass 21, count 2 2006.175.08:15:08.41#ibcon#*mode == 0, iclass 21, count 2 2006.175.08:15:08.41#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.08:15:08.41#ibcon#[25=AT02-07\r\n] 2006.175.08:15:08.41#ibcon#*before write, iclass 21, count 2 2006.175.08:15:08.41#ibcon#enter sib2, iclass 21, count 2 2006.175.08:15:08.41#ibcon#flushed, iclass 21, count 2 2006.175.08:15:08.41#ibcon#about to write, iclass 21, count 2 2006.175.08:15:08.41#ibcon#wrote, iclass 21, count 2 2006.175.08:15:08.41#ibcon#about to read 3, iclass 21, count 2 2006.175.08:15:08.44#ibcon#read 3, iclass 21, count 2 2006.175.08:15:08.44#ibcon#about to read 4, iclass 21, count 2 2006.175.08:15:08.44#ibcon#read 4, iclass 21, count 2 2006.175.08:15:08.44#ibcon#about to read 5, iclass 21, count 2 2006.175.08:15:08.44#ibcon#read 5, iclass 21, count 2 2006.175.08:15:08.44#ibcon#about to read 6, iclass 21, count 2 2006.175.08:15:08.44#ibcon#read 6, iclass 21, count 2 2006.175.08:15:08.44#ibcon#end of sib2, iclass 21, count 2 2006.175.08:15:08.44#ibcon#*after write, iclass 21, count 2 2006.175.08:15:08.44#ibcon#*before return 0, iclass 21, count 2 2006.175.08:15:08.44#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:08.44#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:08.44#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.08:15:08.44#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:08.44#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:08.56#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:08.56#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:08.56#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:15:08.56#ibcon#first serial, iclass 21, count 0 2006.175.08:15:08.56#ibcon#enter sib2, iclass 21, count 0 2006.175.08:15:08.56#ibcon#flushed, iclass 21, count 0 2006.175.08:15:08.56#ibcon#about to write, iclass 21, count 0 2006.175.08:15:08.56#ibcon#wrote, iclass 21, count 0 2006.175.08:15:08.56#ibcon#about to read 3, iclass 21, count 0 2006.175.08:15:08.58#ibcon#read 3, iclass 21, count 0 2006.175.08:15:08.58#ibcon#about to read 4, iclass 21, count 0 2006.175.08:15:08.58#ibcon#read 4, iclass 21, count 0 2006.175.08:15:08.58#ibcon#about to read 5, iclass 21, count 0 2006.175.08:15:08.58#ibcon#read 5, iclass 21, count 0 2006.175.08:15:08.58#ibcon#about to read 6, iclass 21, count 0 2006.175.08:15:08.58#ibcon#read 6, iclass 21, count 0 2006.175.08:15:08.58#ibcon#end of sib2, iclass 21, count 0 2006.175.08:15:08.58#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:15:08.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:15:08.58#ibcon#[25=USB\r\n] 2006.175.08:15:08.58#ibcon#*before write, iclass 21, count 0 2006.175.08:15:08.58#ibcon#enter sib2, iclass 21, count 0 2006.175.08:15:08.58#ibcon#flushed, iclass 21, count 0 2006.175.08:15:08.58#ibcon#about to write, iclass 21, count 0 2006.175.08:15:08.58#ibcon#wrote, iclass 21, count 0 2006.175.08:15:08.58#ibcon#about to read 3, iclass 21, count 0 2006.175.08:15:08.61#ibcon#read 3, iclass 21, count 0 2006.175.08:15:08.61#ibcon#about to read 4, iclass 21, count 0 2006.175.08:15:08.61#ibcon#read 4, iclass 21, count 0 2006.175.08:15:08.61#ibcon#about to read 5, iclass 21, count 0 2006.175.08:15:08.61#ibcon#read 5, iclass 21, count 0 2006.175.08:15:08.61#ibcon#about to read 6, iclass 21, count 0 2006.175.08:15:08.61#ibcon#read 6, iclass 21, count 0 2006.175.08:15:08.61#ibcon#end of sib2, iclass 21, count 0 2006.175.08:15:08.61#ibcon#*after write, iclass 21, count 0 2006.175.08:15:08.61#ibcon#*before return 0, iclass 21, count 0 2006.175.08:15:08.61#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:08.61#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:08.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:15:08.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:15:08.61$vc4f8/valo=3,672.99 2006.175.08:15:08.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.08:15:08.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.08:15:08.61#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:08.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:08.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:08.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:08.61#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:15:08.61#ibcon#first serial, iclass 23, count 0 2006.175.08:15:08.61#ibcon#enter sib2, iclass 23, count 0 2006.175.08:15:08.61#ibcon#flushed, iclass 23, count 0 2006.175.08:15:08.61#ibcon#about to write, iclass 23, count 0 2006.175.08:15:08.61#ibcon#wrote, iclass 23, count 0 2006.175.08:15:08.61#ibcon#about to read 3, iclass 23, count 0 2006.175.08:15:08.63#ibcon#read 3, iclass 23, count 0 2006.175.08:15:08.63#ibcon#about to read 4, iclass 23, count 0 2006.175.08:15:08.63#ibcon#read 4, iclass 23, count 0 2006.175.08:15:08.63#ibcon#about to read 5, iclass 23, count 0 2006.175.08:15:08.63#ibcon#read 5, iclass 23, count 0 2006.175.08:15:08.63#ibcon#about to read 6, iclass 23, count 0 2006.175.08:15:08.63#ibcon#read 6, iclass 23, count 0 2006.175.08:15:08.63#ibcon#end of sib2, iclass 23, count 0 2006.175.08:15:08.63#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:15:08.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:15:08.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:15:08.63#ibcon#*before write, iclass 23, count 0 2006.175.08:15:08.63#ibcon#enter sib2, iclass 23, count 0 2006.175.08:15:08.63#ibcon#flushed, iclass 23, count 0 2006.175.08:15:08.63#ibcon#about to write, iclass 23, count 0 2006.175.08:15:08.63#ibcon#wrote, iclass 23, count 0 2006.175.08:15:08.63#ibcon#about to read 3, iclass 23, count 0 2006.175.08:15:08.67#ibcon#read 3, iclass 23, count 0 2006.175.08:15:08.67#ibcon#about to read 4, iclass 23, count 0 2006.175.08:15:08.67#ibcon#read 4, iclass 23, count 0 2006.175.08:15:08.67#ibcon#about to read 5, iclass 23, count 0 2006.175.08:15:08.67#ibcon#read 5, iclass 23, count 0 2006.175.08:15:08.67#ibcon#about to read 6, iclass 23, count 0 2006.175.08:15:08.67#ibcon#read 6, iclass 23, count 0 2006.175.08:15:08.67#ibcon#end of sib2, iclass 23, count 0 2006.175.08:15:08.67#ibcon#*after write, iclass 23, count 0 2006.175.08:15:08.67#ibcon#*before return 0, iclass 23, count 0 2006.175.08:15:08.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:08.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:08.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:15:08.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:15:08.67$vc4f8/va=3,6 2006.175.08:15:08.67#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.08:15:08.67#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.08:15:08.67#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:08.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:08.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:08.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:08.73#ibcon#enter wrdev, iclass 25, count 2 2006.175.08:15:08.73#ibcon#first serial, iclass 25, count 2 2006.175.08:15:08.73#ibcon#enter sib2, iclass 25, count 2 2006.175.08:15:08.73#ibcon#flushed, iclass 25, count 2 2006.175.08:15:08.73#ibcon#about to write, iclass 25, count 2 2006.175.08:15:08.73#ibcon#wrote, iclass 25, count 2 2006.175.08:15:08.73#ibcon#about to read 3, iclass 25, count 2 2006.175.08:15:08.75#ibcon#read 3, iclass 25, count 2 2006.175.08:15:08.75#ibcon#about to read 4, iclass 25, count 2 2006.175.08:15:08.75#ibcon#read 4, iclass 25, count 2 2006.175.08:15:08.75#ibcon#about to read 5, iclass 25, count 2 2006.175.08:15:08.75#ibcon#read 5, iclass 25, count 2 2006.175.08:15:08.75#ibcon#about to read 6, iclass 25, count 2 2006.175.08:15:08.75#ibcon#read 6, iclass 25, count 2 2006.175.08:15:08.75#ibcon#end of sib2, iclass 25, count 2 2006.175.08:15:08.75#ibcon#*mode == 0, iclass 25, count 2 2006.175.08:15:08.75#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.08:15:08.75#ibcon#[25=AT03-06\r\n] 2006.175.08:15:08.75#ibcon#*before write, iclass 25, count 2 2006.175.08:15:08.75#ibcon#enter sib2, iclass 25, count 2 2006.175.08:15:08.75#ibcon#flushed, iclass 25, count 2 2006.175.08:15:08.75#ibcon#about to write, iclass 25, count 2 2006.175.08:15:08.75#ibcon#wrote, iclass 25, count 2 2006.175.08:15:08.75#ibcon#about to read 3, iclass 25, count 2 2006.175.08:15:08.78#ibcon#read 3, iclass 25, count 2 2006.175.08:15:08.78#ibcon#about to read 4, iclass 25, count 2 2006.175.08:15:08.78#ibcon#read 4, iclass 25, count 2 2006.175.08:15:08.78#ibcon#about to read 5, iclass 25, count 2 2006.175.08:15:08.78#ibcon#read 5, iclass 25, count 2 2006.175.08:15:08.78#ibcon#about to read 6, iclass 25, count 2 2006.175.08:15:08.78#ibcon#read 6, iclass 25, count 2 2006.175.08:15:08.78#ibcon#end of sib2, iclass 25, count 2 2006.175.08:15:08.78#ibcon#*after write, iclass 25, count 2 2006.175.08:15:08.78#ibcon#*before return 0, iclass 25, count 2 2006.175.08:15:08.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:08.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:08.78#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.08:15:08.78#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:08.78#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:08.90#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:08.90#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:08.90#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:15:08.90#ibcon#first serial, iclass 25, count 0 2006.175.08:15:08.90#ibcon#enter sib2, iclass 25, count 0 2006.175.08:15:08.90#ibcon#flushed, iclass 25, count 0 2006.175.08:15:08.90#ibcon#about to write, iclass 25, count 0 2006.175.08:15:08.90#ibcon#wrote, iclass 25, count 0 2006.175.08:15:08.90#ibcon#about to read 3, iclass 25, count 0 2006.175.08:15:08.92#ibcon#read 3, iclass 25, count 0 2006.175.08:15:08.92#ibcon#about to read 4, iclass 25, count 0 2006.175.08:15:08.92#ibcon#read 4, iclass 25, count 0 2006.175.08:15:08.92#ibcon#about to read 5, iclass 25, count 0 2006.175.08:15:08.92#ibcon#read 5, iclass 25, count 0 2006.175.08:15:08.92#ibcon#about to read 6, iclass 25, count 0 2006.175.08:15:08.92#ibcon#read 6, iclass 25, count 0 2006.175.08:15:08.92#ibcon#end of sib2, iclass 25, count 0 2006.175.08:15:08.92#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:15:08.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:15:08.92#ibcon#[25=USB\r\n] 2006.175.08:15:08.92#ibcon#*before write, iclass 25, count 0 2006.175.08:15:08.92#ibcon#enter sib2, iclass 25, count 0 2006.175.08:15:08.92#ibcon#flushed, iclass 25, count 0 2006.175.08:15:08.92#ibcon#about to write, iclass 25, count 0 2006.175.08:15:08.92#ibcon#wrote, iclass 25, count 0 2006.175.08:15:08.92#ibcon#about to read 3, iclass 25, count 0 2006.175.08:15:08.95#ibcon#read 3, iclass 25, count 0 2006.175.08:15:08.95#ibcon#about to read 4, iclass 25, count 0 2006.175.08:15:08.95#ibcon#read 4, iclass 25, count 0 2006.175.08:15:08.95#ibcon#about to read 5, iclass 25, count 0 2006.175.08:15:08.95#ibcon#read 5, iclass 25, count 0 2006.175.08:15:08.95#ibcon#about to read 6, iclass 25, count 0 2006.175.08:15:08.95#ibcon#read 6, iclass 25, count 0 2006.175.08:15:08.95#ibcon#end of sib2, iclass 25, count 0 2006.175.08:15:08.95#ibcon#*after write, iclass 25, count 0 2006.175.08:15:08.95#ibcon#*before return 0, iclass 25, count 0 2006.175.08:15:08.95#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:08.95#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:08.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:15:08.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:15:08.95$vc4f8/valo=4,832.99 2006.175.08:15:08.95#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.08:15:08.95#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.08:15:08.95#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:08.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:08.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:08.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:08.95#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:15:08.95#ibcon#first serial, iclass 27, count 0 2006.175.08:15:08.95#ibcon#enter sib2, iclass 27, count 0 2006.175.08:15:08.95#ibcon#flushed, iclass 27, count 0 2006.175.08:15:08.95#ibcon#about to write, iclass 27, count 0 2006.175.08:15:08.95#ibcon#wrote, iclass 27, count 0 2006.175.08:15:08.95#ibcon#about to read 3, iclass 27, count 0 2006.175.08:15:08.97#ibcon#read 3, iclass 27, count 0 2006.175.08:15:08.97#ibcon#about to read 4, iclass 27, count 0 2006.175.08:15:08.97#ibcon#read 4, iclass 27, count 0 2006.175.08:15:08.97#ibcon#about to read 5, iclass 27, count 0 2006.175.08:15:08.97#ibcon#read 5, iclass 27, count 0 2006.175.08:15:08.97#ibcon#about to read 6, iclass 27, count 0 2006.175.08:15:08.97#ibcon#read 6, iclass 27, count 0 2006.175.08:15:08.97#ibcon#end of sib2, iclass 27, count 0 2006.175.08:15:08.97#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:15:08.97#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:15:08.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:15:08.97#ibcon#*before write, iclass 27, count 0 2006.175.08:15:08.97#ibcon#enter sib2, iclass 27, count 0 2006.175.08:15:08.97#ibcon#flushed, iclass 27, count 0 2006.175.08:15:08.97#ibcon#about to write, iclass 27, count 0 2006.175.08:15:08.97#ibcon#wrote, iclass 27, count 0 2006.175.08:15:08.97#ibcon#about to read 3, iclass 27, count 0 2006.175.08:15:09.01#ibcon#read 3, iclass 27, count 0 2006.175.08:15:09.01#ibcon#about to read 4, iclass 27, count 0 2006.175.08:15:09.01#ibcon#read 4, iclass 27, count 0 2006.175.08:15:09.01#ibcon#about to read 5, iclass 27, count 0 2006.175.08:15:09.01#ibcon#read 5, iclass 27, count 0 2006.175.08:15:09.01#ibcon#about to read 6, iclass 27, count 0 2006.175.08:15:09.01#ibcon#read 6, iclass 27, count 0 2006.175.08:15:09.01#ibcon#end of sib2, iclass 27, count 0 2006.175.08:15:09.01#ibcon#*after write, iclass 27, count 0 2006.175.08:15:09.01#ibcon#*before return 0, iclass 27, count 0 2006.175.08:15:09.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:09.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:09.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:15:09.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:15:09.01$vc4f8/va=4,7 2006.175.08:15:09.01#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.175.08:15:09.01#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.175.08:15:09.01#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:09.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:09.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:09.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:09.07#ibcon#enter wrdev, iclass 29, count 2 2006.175.08:15:09.07#ibcon#first serial, iclass 29, count 2 2006.175.08:15:09.07#ibcon#enter sib2, iclass 29, count 2 2006.175.08:15:09.07#ibcon#flushed, iclass 29, count 2 2006.175.08:15:09.07#ibcon#about to write, iclass 29, count 2 2006.175.08:15:09.07#ibcon#wrote, iclass 29, count 2 2006.175.08:15:09.07#ibcon#about to read 3, iclass 29, count 2 2006.175.08:15:09.09#ibcon#read 3, iclass 29, count 2 2006.175.08:15:09.09#ibcon#about to read 4, iclass 29, count 2 2006.175.08:15:09.09#ibcon#read 4, iclass 29, count 2 2006.175.08:15:09.09#ibcon#about to read 5, iclass 29, count 2 2006.175.08:15:09.09#ibcon#read 5, iclass 29, count 2 2006.175.08:15:09.09#ibcon#about to read 6, iclass 29, count 2 2006.175.08:15:09.09#ibcon#read 6, iclass 29, count 2 2006.175.08:15:09.09#ibcon#end of sib2, iclass 29, count 2 2006.175.08:15:09.09#ibcon#*mode == 0, iclass 29, count 2 2006.175.08:15:09.09#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.175.08:15:09.09#ibcon#[25=AT04-07\r\n] 2006.175.08:15:09.09#ibcon#*before write, iclass 29, count 2 2006.175.08:15:09.09#ibcon#enter sib2, iclass 29, count 2 2006.175.08:15:09.09#ibcon#flushed, iclass 29, count 2 2006.175.08:15:09.09#ibcon#about to write, iclass 29, count 2 2006.175.08:15:09.09#ibcon#wrote, iclass 29, count 2 2006.175.08:15:09.09#ibcon#about to read 3, iclass 29, count 2 2006.175.08:15:09.12#ibcon#read 3, iclass 29, count 2 2006.175.08:15:09.12#ibcon#about to read 4, iclass 29, count 2 2006.175.08:15:09.12#ibcon#read 4, iclass 29, count 2 2006.175.08:15:09.12#ibcon#about to read 5, iclass 29, count 2 2006.175.08:15:09.12#ibcon#read 5, iclass 29, count 2 2006.175.08:15:09.12#ibcon#about to read 6, iclass 29, count 2 2006.175.08:15:09.12#ibcon#read 6, iclass 29, count 2 2006.175.08:15:09.12#ibcon#end of sib2, iclass 29, count 2 2006.175.08:15:09.12#ibcon#*after write, iclass 29, count 2 2006.175.08:15:09.12#ibcon#*before return 0, iclass 29, count 2 2006.175.08:15:09.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:09.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:09.12#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.175.08:15:09.12#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:09.12#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:09.24#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:09.24#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:09.24#ibcon#enter wrdev, iclass 29, count 0 2006.175.08:15:09.24#ibcon#first serial, iclass 29, count 0 2006.175.08:15:09.24#ibcon#enter sib2, iclass 29, count 0 2006.175.08:15:09.24#ibcon#flushed, iclass 29, count 0 2006.175.08:15:09.24#ibcon#about to write, iclass 29, count 0 2006.175.08:15:09.24#ibcon#wrote, iclass 29, count 0 2006.175.08:15:09.24#ibcon#about to read 3, iclass 29, count 0 2006.175.08:15:09.26#ibcon#read 3, iclass 29, count 0 2006.175.08:15:09.26#ibcon#about to read 4, iclass 29, count 0 2006.175.08:15:09.26#ibcon#read 4, iclass 29, count 0 2006.175.08:15:09.26#ibcon#about to read 5, iclass 29, count 0 2006.175.08:15:09.26#ibcon#read 5, iclass 29, count 0 2006.175.08:15:09.26#ibcon#about to read 6, iclass 29, count 0 2006.175.08:15:09.26#ibcon#read 6, iclass 29, count 0 2006.175.08:15:09.26#ibcon#end of sib2, iclass 29, count 0 2006.175.08:15:09.26#ibcon#*mode == 0, iclass 29, count 0 2006.175.08:15:09.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.08:15:09.26#ibcon#[25=USB\r\n] 2006.175.08:15:09.26#ibcon#*before write, iclass 29, count 0 2006.175.08:15:09.26#ibcon#enter sib2, iclass 29, count 0 2006.175.08:15:09.26#ibcon#flushed, iclass 29, count 0 2006.175.08:15:09.26#ibcon#about to write, iclass 29, count 0 2006.175.08:15:09.26#ibcon#wrote, iclass 29, count 0 2006.175.08:15:09.26#ibcon#about to read 3, iclass 29, count 0 2006.175.08:15:09.29#ibcon#read 3, iclass 29, count 0 2006.175.08:15:09.29#ibcon#about to read 4, iclass 29, count 0 2006.175.08:15:09.29#ibcon#read 4, iclass 29, count 0 2006.175.08:15:09.29#ibcon#about to read 5, iclass 29, count 0 2006.175.08:15:09.29#ibcon#read 5, iclass 29, count 0 2006.175.08:15:09.29#ibcon#about to read 6, iclass 29, count 0 2006.175.08:15:09.29#ibcon#read 6, iclass 29, count 0 2006.175.08:15:09.29#ibcon#end of sib2, iclass 29, count 0 2006.175.08:15:09.29#ibcon#*after write, iclass 29, count 0 2006.175.08:15:09.29#ibcon#*before return 0, iclass 29, count 0 2006.175.08:15:09.29#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:09.29#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:09.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.08:15:09.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.08:15:09.29$vc4f8/valo=5,652.99 2006.175.08:15:09.29#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.08:15:09.29#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.08:15:09.29#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:09.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:09.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:09.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:09.29#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:15:09.29#ibcon#first serial, iclass 31, count 0 2006.175.08:15:09.29#ibcon#enter sib2, iclass 31, count 0 2006.175.08:15:09.29#ibcon#flushed, iclass 31, count 0 2006.175.08:15:09.29#ibcon#about to write, iclass 31, count 0 2006.175.08:15:09.29#ibcon#wrote, iclass 31, count 0 2006.175.08:15:09.29#ibcon#about to read 3, iclass 31, count 0 2006.175.08:15:09.31#ibcon#read 3, iclass 31, count 0 2006.175.08:15:09.31#ibcon#about to read 4, iclass 31, count 0 2006.175.08:15:09.31#ibcon#read 4, iclass 31, count 0 2006.175.08:15:09.31#ibcon#about to read 5, iclass 31, count 0 2006.175.08:15:09.31#ibcon#read 5, iclass 31, count 0 2006.175.08:15:09.31#ibcon#about to read 6, iclass 31, count 0 2006.175.08:15:09.31#ibcon#read 6, iclass 31, count 0 2006.175.08:15:09.31#ibcon#end of sib2, iclass 31, count 0 2006.175.08:15:09.31#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:15:09.31#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:15:09.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:15:09.31#ibcon#*before write, iclass 31, count 0 2006.175.08:15:09.31#ibcon#enter sib2, iclass 31, count 0 2006.175.08:15:09.31#ibcon#flushed, iclass 31, count 0 2006.175.08:15:09.31#ibcon#about to write, iclass 31, count 0 2006.175.08:15:09.31#ibcon#wrote, iclass 31, count 0 2006.175.08:15:09.31#ibcon#about to read 3, iclass 31, count 0 2006.175.08:15:09.35#ibcon#read 3, iclass 31, count 0 2006.175.08:15:09.35#ibcon#about to read 4, iclass 31, count 0 2006.175.08:15:09.35#ibcon#read 4, iclass 31, count 0 2006.175.08:15:09.35#ibcon#about to read 5, iclass 31, count 0 2006.175.08:15:09.35#ibcon#read 5, iclass 31, count 0 2006.175.08:15:09.35#ibcon#about to read 6, iclass 31, count 0 2006.175.08:15:09.35#ibcon#read 6, iclass 31, count 0 2006.175.08:15:09.35#ibcon#end of sib2, iclass 31, count 0 2006.175.08:15:09.35#ibcon#*after write, iclass 31, count 0 2006.175.08:15:09.35#ibcon#*before return 0, iclass 31, count 0 2006.175.08:15:09.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:09.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:09.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:15:09.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:15:09.35$vc4f8/va=5,7 2006.175.08:15:09.35#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.08:15:09.35#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.08:15:09.35#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:09.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:09.41#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:09.41#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:09.41#ibcon#enter wrdev, iclass 33, count 2 2006.175.08:15:09.41#ibcon#first serial, iclass 33, count 2 2006.175.08:15:09.41#ibcon#enter sib2, iclass 33, count 2 2006.175.08:15:09.41#ibcon#flushed, iclass 33, count 2 2006.175.08:15:09.41#ibcon#about to write, iclass 33, count 2 2006.175.08:15:09.41#ibcon#wrote, iclass 33, count 2 2006.175.08:15:09.41#ibcon#about to read 3, iclass 33, count 2 2006.175.08:15:09.43#ibcon#read 3, iclass 33, count 2 2006.175.08:15:09.43#ibcon#about to read 4, iclass 33, count 2 2006.175.08:15:09.43#ibcon#read 4, iclass 33, count 2 2006.175.08:15:09.43#ibcon#about to read 5, iclass 33, count 2 2006.175.08:15:09.43#ibcon#read 5, iclass 33, count 2 2006.175.08:15:09.43#ibcon#about to read 6, iclass 33, count 2 2006.175.08:15:09.43#ibcon#read 6, iclass 33, count 2 2006.175.08:15:09.43#ibcon#end of sib2, iclass 33, count 2 2006.175.08:15:09.43#ibcon#*mode == 0, iclass 33, count 2 2006.175.08:15:09.43#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.08:15:09.43#ibcon#[25=AT05-07\r\n] 2006.175.08:15:09.43#ibcon#*before write, iclass 33, count 2 2006.175.08:15:09.43#ibcon#enter sib2, iclass 33, count 2 2006.175.08:15:09.43#ibcon#flushed, iclass 33, count 2 2006.175.08:15:09.43#ibcon#about to write, iclass 33, count 2 2006.175.08:15:09.43#ibcon#wrote, iclass 33, count 2 2006.175.08:15:09.43#ibcon#about to read 3, iclass 33, count 2 2006.175.08:15:09.46#ibcon#read 3, iclass 33, count 2 2006.175.08:15:09.46#ibcon#about to read 4, iclass 33, count 2 2006.175.08:15:09.46#ibcon#read 4, iclass 33, count 2 2006.175.08:15:09.46#ibcon#about to read 5, iclass 33, count 2 2006.175.08:15:09.46#ibcon#read 5, iclass 33, count 2 2006.175.08:15:09.46#ibcon#about to read 6, iclass 33, count 2 2006.175.08:15:09.46#ibcon#read 6, iclass 33, count 2 2006.175.08:15:09.46#ibcon#end of sib2, iclass 33, count 2 2006.175.08:15:09.46#ibcon#*after write, iclass 33, count 2 2006.175.08:15:09.46#ibcon#*before return 0, iclass 33, count 2 2006.175.08:15:09.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:09.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:09.46#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.08:15:09.46#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:09.46#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:09.58#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:09.58#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:09.58#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:15:09.58#ibcon#first serial, iclass 33, count 0 2006.175.08:15:09.58#ibcon#enter sib2, iclass 33, count 0 2006.175.08:15:09.58#ibcon#flushed, iclass 33, count 0 2006.175.08:15:09.58#ibcon#about to write, iclass 33, count 0 2006.175.08:15:09.58#ibcon#wrote, iclass 33, count 0 2006.175.08:15:09.58#ibcon#about to read 3, iclass 33, count 0 2006.175.08:15:09.60#ibcon#read 3, iclass 33, count 0 2006.175.08:15:09.60#ibcon#about to read 4, iclass 33, count 0 2006.175.08:15:09.60#ibcon#read 4, iclass 33, count 0 2006.175.08:15:09.60#ibcon#about to read 5, iclass 33, count 0 2006.175.08:15:09.60#ibcon#read 5, iclass 33, count 0 2006.175.08:15:09.60#ibcon#about to read 6, iclass 33, count 0 2006.175.08:15:09.60#ibcon#read 6, iclass 33, count 0 2006.175.08:15:09.60#ibcon#end of sib2, iclass 33, count 0 2006.175.08:15:09.60#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:15:09.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:15:09.60#ibcon#[25=USB\r\n] 2006.175.08:15:09.60#ibcon#*before write, iclass 33, count 0 2006.175.08:15:09.60#ibcon#enter sib2, iclass 33, count 0 2006.175.08:15:09.60#ibcon#flushed, iclass 33, count 0 2006.175.08:15:09.60#ibcon#about to write, iclass 33, count 0 2006.175.08:15:09.60#ibcon#wrote, iclass 33, count 0 2006.175.08:15:09.60#ibcon#about to read 3, iclass 33, count 0 2006.175.08:15:09.63#ibcon#read 3, iclass 33, count 0 2006.175.08:15:09.63#ibcon#about to read 4, iclass 33, count 0 2006.175.08:15:09.63#ibcon#read 4, iclass 33, count 0 2006.175.08:15:09.63#ibcon#about to read 5, iclass 33, count 0 2006.175.08:15:09.63#ibcon#read 5, iclass 33, count 0 2006.175.08:15:09.63#ibcon#about to read 6, iclass 33, count 0 2006.175.08:15:09.63#ibcon#read 6, iclass 33, count 0 2006.175.08:15:09.63#ibcon#end of sib2, iclass 33, count 0 2006.175.08:15:09.63#ibcon#*after write, iclass 33, count 0 2006.175.08:15:09.63#ibcon#*before return 0, iclass 33, count 0 2006.175.08:15:09.63#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:09.63#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:09.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:15:09.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:15:09.63$vc4f8/valo=6,772.99 2006.175.08:15:09.63#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.08:15:09.63#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.08:15:09.63#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:09.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:09.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:09.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:09.63#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:15:09.63#ibcon#first serial, iclass 35, count 0 2006.175.08:15:09.63#ibcon#enter sib2, iclass 35, count 0 2006.175.08:15:09.63#ibcon#flushed, iclass 35, count 0 2006.175.08:15:09.63#ibcon#about to write, iclass 35, count 0 2006.175.08:15:09.63#ibcon#wrote, iclass 35, count 0 2006.175.08:15:09.63#ibcon#about to read 3, iclass 35, count 0 2006.175.08:15:09.65#ibcon#read 3, iclass 35, count 0 2006.175.08:15:09.65#ibcon#about to read 4, iclass 35, count 0 2006.175.08:15:09.65#ibcon#read 4, iclass 35, count 0 2006.175.08:15:09.65#ibcon#about to read 5, iclass 35, count 0 2006.175.08:15:09.65#ibcon#read 5, iclass 35, count 0 2006.175.08:15:09.65#ibcon#about to read 6, iclass 35, count 0 2006.175.08:15:09.65#ibcon#read 6, iclass 35, count 0 2006.175.08:15:09.65#ibcon#end of sib2, iclass 35, count 0 2006.175.08:15:09.65#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:15:09.65#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:15:09.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:15:09.65#ibcon#*before write, iclass 35, count 0 2006.175.08:15:09.65#ibcon#enter sib2, iclass 35, count 0 2006.175.08:15:09.65#ibcon#flushed, iclass 35, count 0 2006.175.08:15:09.65#ibcon#about to write, iclass 35, count 0 2006.175.08:15:09.65#ibcon#wrote, iclass 35, count 0 2006.175.08:15:09.65#ibcon#about to read 3, iclass 35, count 0 2006.175.08:15:09.69#ibcon#read 3, iclass 35, count 0 2006.175.08:15:09.69#ibcon#about to read 4, iclass 35, count 0 2006.175.08:15:09.69#ibcon#read 4, iclass 35, count 0 2006.175.08:15:09.69#ibcon#about to read 5, iclass 35, count 0 2006.175.08:15:09.69#ibcon#read 5, iclass 35, count 0 2006.175.08:15:09.69#ibcon#about to read 6, iclass 35, count 0 2006.175.08:15:09.69#ibcon#read 6, iclass 35, count 0 2006.175.08:15:09.69#ibcon#end of sib2, iclass 35, count 0 2006.175.08:15:09.69#ibcon#*after write, iclass 35, count 0 2006.175.08:15:09.69#ibcon#*before return 0, iclass 35, count 0 2006.175.08:15:09.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:09.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:09.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:15:09.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:15:09.69$vc4f8/va=6,6 2006.175.08:15:09.69#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.08:15:09.69#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.08:15:09.69#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:09.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:15:09.75#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:15:09.75#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:15:09.75#ibcon#enter wrdev, iclass 37, count 2 2006.175.08:15:09.75#ibcon#first serial, iclass 37, count 2 2006.175.08:15:09.75#ibcon#enter sib2, iclass 37, count 2 2006.175.08:15:09.75#ibcon#flushed, iclass 37, count 2 2006.175.08:15:09.75#ibcon#about to write, iclass 37, count 2 2006.175.08:15:09.75#ibcon#wrote, iclass 37, count 2 2006.175.08:15:09.75#ibcon#about to read 3, iclass 37, count 2 2006.175.08:15:09.77#ibcon#read 3, iclass 37, count 2 2006.175.08:15:09.77#ibcon#about to read 4, iclass 37, count 2 2006.175.08:15:09.77#ibcon#read 4, iclass 37, count 2 2006.175.08:15:09.77#ibcon#about to read 5, iclass 37, count 2 2006.175.08:15:09.77#ibcon#read 5, iclass 37, count 2 2006.175.08:15:09.77#ibcon#about to read 6, iclass 37, count 2 2006.175.08:15:09.77#ibcon#read 6, iclass 37, count 2 2006.175.08:15:09.77#ibcon#end of sib2, iclass 37, count 2 2006.175.08:15:09.77#ibcon#*mode == 0, iclass 37, count 2 2006.175.08:15:09.77#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.08:15:09.77#ibcon#[25=AT06-06\r\n] 2006.175.08:15:09.77#ibcon#*before write, iclass 37, count 2 2006.175.08:15:09.77#ibcon#enter sib2, iclass 37, count 2 2006.175.08:15:09.77#ibcon#flushed, iclass 37, count 2 2006.175.08:15:09.77#ibcon#about to write, iclass 37, count 2 2006.175.08:15:09.77#ibcon#wrote, iclass 37, count 2 2006.175.08:15:09.77#ibcon#about to read 3, iclass 37, count 2 2006.175.08:15:09.80#ibcon#read 3, iclass 37, count 2 2006.175.08:15:09.80#ibcon#about to read 4, iclass 37, count 2 2006.175.08:15:09.80#ibcon#read 4, iclass 37, count 2 2006.175.08:15:09.80#ibcon#about to read 5, iclass 37, count 2 2006.175.08:15:09.80#ibcon#read 5, iclass 37, count 2 2006.175.08:15:09.80#ibcon#about to read 6, iclass 37, count 2 2006.175.08:15:09.80#ibcon#read 6, iclass 37, count 2 2006.175.08:15:09.80#ibcon#end of sib2, iclass 37, count 2 2006.175.08:15:09.80#ibcon#*after write, iclass 37, count 2 2006.175.08:15:09.80#ibcon#*before return 0, iclass 37, count 2 2006.175.08:15:09.80#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:15:09.80#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:15:09.80#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.08:15:09.80#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:09.80#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:15:09.92#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:15:09.92#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:15:09.92#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:15:09.92#ibcon#first serial, iclass 37, count 0 2006.175.08:15:09.92#ibcon#enter sib2, iclass 37, count 0 2006.175.08:15:09.92#ibcon#flushed, iclass 37, count 0 2006.175.08:15:09.92#ibcon#about to write, iclass 37, count 0 2006.175.08:15:09.92#ibcon#wrote, iclass 37, count 0 2006.175.08:15:09.92#ibcon#about to read 3, iclass 37, count 0 2006.175.08:15:09.94#ibcon#read 3, iclass 37, count 0 2006.175.08:15:09.94#ibcon#about to read 4, iclass 37, count 0 2006.175.08:15:09.94#ibcon#read 4, iclass 37, count 0 2006.175.08:15:09.94#ibcon#about to read 5, iclass 37, count 0 2006.175.08:15:09.94#ibcon#read 5, iclass 37, count 0 2006.175.08:15:09.94#ibcon#about to read 6, iclass 37, count 0 2006.175.08:15:09.94#ibcon#read 6, iclass 37, count 0 2006.175.08:15:09.94#ibcon#end of sib2, iclass 37, count 0 2006.175.08:15:09.94#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:15:09.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:15:09.94#ibcon#[25=USB\r\n] 2006.175.08:15:09.94#ibcon#*before write, iclass 37, count 0 2006.175.08:15:09.94#ibcon#enter sib2, iclass 37, count 0 2006.175.08:15:09.94#ibcon#flushed, iclass 37, count 0 2006.175.08:15:09.94#ibcon#about to write, iclass 37, count 0 2006.175.08:15:09.94#ibcon#wrote, iclass 37, count 0 2006.175.08:15:09.94#ibcon#about to read 3, iclass 37, count 0 2006.175.08:15:09.97#ibcon#read 3, iclass 37, count 0 2006.175.08:15:09.97#ibcon#about to read 4, iclass 37, count 0 2006.175.08:15:09.97#ibcon#read 4, iclass 37, count 0 2006.175.08:15:09.97#ibcon#about to read 5, iclass 37, count 0 2006.175.08:15:09.97#ibcon#read 5, iclass 37, count 0 2006.175.08:15:09.97#ibcon#about to read 6, iclass 37, count 0 2006.175.08:15:09.97#ibcon#read 6, iclass 37, count 0 2006.175.08:15:09.97#ibcon#end of sib2, iclass 37, count 0 2006.175.08:15:09.97#ibcon#*after write, iclass 37, count 0 2006.175.08:15:09.97#ibcon#*before return 0, iclass 37, count 0 2006.175.08:15:09.97#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:15:09.97#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:15:09.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:15:09.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:15:09.97$vc4f8/valo=7,832.99 2006.175.08:15:09.97#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.08:15:09.97#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.08:15:09.97#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:09.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:15:09.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:15:09.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:15:09.97#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:15:09.97#ibcon#first serial, iclass 39, count 0 2006.175.08:15:09.97#ibcon#enter sib2, iclass 39, count 0 2006.175.08:15:09.97#ibcon#flushed, iclass 39, count 0 2006.175.08:15:09.97#ibcon#about to write, iclass 39, count 0 2006.175.08:15:09.97#ibcon#wrote, iclass 39, count 0 2006.175.08:15:09.97#ibcon#about to read 3, iclass 39, count 0 2006.175.08:15:09.99#ibcon#read 3, iclass 39, count 0 2006.175.08:15:09.99#ibcon#about to read 4, iclass 39, count 0 2006.175.08:15:09.99#ibcon#read 4, iclass 39, count 0 2006.175.08:15:09.99#ibcon#about to read 5, iclass 39, count 0 2006.175.08:15:09.99#ibcon#read 5, iclass 39, count 0 2006.175.08:15:09.99#ibcon#about to read 6, iclass 39, count 0 2006.175.08:15:09.99#ibcon#read 6, iclass 39, count 0 2006.175.08:15:09.99#ibcon#end of sib2, iclass 39, count 0 2006.175.08:15:09.99#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:15:09.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:15:09.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:15:09.99#ibcon#*before write, iclass 39, count 0 2006.175.08:15:09.99#ibcon#enter sib2, iclass 39, count 0 2006.175.08:15:09.99#ibcon#flushed, iclass 39, count 0 2006.175.08:15:09.99#ibcon#about to write, iclass 39, count 0 2006.175.08:15:09.99#ibcon#wrote, iclass 39, count 0 2006.175.08:15:09.99#ibcon#about to read 3, iclass 39, count 0 2006.175.08:15:10.03#ibcon#read 3, iclass 39, count 0 2006.175.08:15:10.03#ibcon#about to read 4, iclass 39, count 0 2006.175.08:15:10.03#ibcon#read 4, iclass 39, count 0 2006.175.08:15:10.03#ibcon#about to read 5, iclass 39, count 0 2006.175.08:15:10.03#ibcon#read 5, iclass 39, count 0 2006.175.08:15:10.03#ibcon#about to read 6, iclass 39, count 0 2006.175.08:15:10.03#ibcon#read 6, iclass 39, count 0 2006.175.08:15:10.03#ibcon#end of sib2, iclass 39, count 0 2006.175.08:15:10.03#ibcon#*after write, iclass 39, count 0 2006.175.08:15:10.03#ibcon#*before return 0, iclass 39, count 0 2006.175.08:15:10.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:15:10.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:15:10.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:15:10.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:15:10.03$vc4f8/va=7,6 2006.175.08:15:10.03#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.08:15:10.03#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.08:15:10.03#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:10.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:15:10.09#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:15:10.09#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:15:10.09#ibcon#enter wrdev, iclass 3, count 2 2006.175.08:15:10.09#ibcon#first serial, iclass 3, count 2 2006.175.08:15:10.09#ibcon#enter sib2, iclass 3, count 2 2006.175.08:15:10.09#ibcon#flushed, iclass 3, count 2 2006.175.08:15:10.09#ibcon#about to write, iclass 3, count 2 2006.175.08:15:10.09#ibcon#wrote, iclass 3, count 2 2006.175.08:15:10.09#ibcon#about to read 3, iclass 3, count 2 2006.175.08:15:10.11#ibcon#read 3, iclass 3, count 2 2006.175.08:15:10.11#ibcon#about to read 4, iclass 3, count 2 2006.175.08:15:10.11#ibcon#read 4, iclass 3, count 2 2006.175.08:15:10.11#ibcon#about to read 5, iclass 3, count 2 2006.175.08:15:10.11#ibcon#read 5, iclass 3, count 2 2006.175.08:15:10.11#ibcon#about to read 6, iclass 3, count 2 2006.175.08:15:10.11#ibcon#read 6, iclass 3, count 2 2006.175.08:15:10.11#ibcon#end of sib2, iclass 3, count 2 2006.175.08:15:10.11#ibcon#*mode == 0, iclass 3, count 2 2006.175.08:15:10.11#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.08:15:10.11#ibcon#[25=AT07-06\r\n] 2006.175.08:15:10.11#ibcon#*before write, iclass 3, count 2 2006.175.08:15:10.11#ibcon#enter sib2, iclass 3, count 2 2006.175.08:15:10.11#ibcon#flushed, iclass 3, count 2 2006.175.08:15:10.11#ibcon#about to write, iclass 3, count 2 2006.175.08:15:10.11#ibcon#wrote, iclass 3, count 2 2006.175.08:15:10.11#ibcon#about to read 3, iclass 3, count 2 2006.175.08:15:10.14#ibcon#read 3, iclass 3, count 2 2006.175.08:15:10.14#ibcon#about to read 4, iclass 3, count 2 2006.175.08:15:10.14#ibcon#read 4, iclass 3, count 2 2006.175.08:15:10.14#ibcon#about to read 5, iclass 3, count 2 2006.175.08:15:10.14#ibcon#read 5, iclass 3, count 2 2006.175.08:15:10.14#ibcon#about to read 6, iclass 3, count 2 2006.175.08:15:10.14#ibcon#read 6, iclass 3, count 2 2006.175.08:15:10.14#ibcon#end of sib2, iclass 3, count 2 2006.175.08:15:10.14#ibcon#*after write, iclass 3, count 2 2006.175.08:15:10.14#ibcon#*before return 0, iclass 3, count 2 2006.175.08:15:10.14#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:15:10.14#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:15:10.14#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.08:15:10.14#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:10.14#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:15:10.26#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:15:10.26#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:15:10.26#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:15:10.26#ibcon#first serial, iclass 3, count 0 2006.175.08:15:10.26#ibcon#enter sib2, iclass 3, count 0 2006.175.08:15:10.26#ibcon#flushed, iclass 3, count 0 2006.175.08:15:10.26#ibcon#about to write, iclass 3, count 0 2006.175.08:15:10.26#ibcon#wrote, iclass 3, count 0 2006.175.08:15:10.26#ibcon#about to read 3, iclass 3, count 0 2006.175.08:15:10.28#ibcon#read 3, iclass 3, count 0 2006.175.08:15:10.28#ibcon#about to read 4, iclass 3, count 0 2006.175.08:15:10.28#ibcon#read 4, iclass 3, count 0 2006.175.08:15:10.28#ibcon#about to read 5, iclass 3, count 0 2006.175.08:15:10.28#ibcon#read 5, iclass 3, count 0 2006.175.08:15:10.28#ibcon#about to read 6, iclass 3, count 0 2006.175.08:15:10.28#ibcon#read 6, iclass 3, count 0 2006.175.08:15:10.28#ibcon#end of sib2, iclass 3, count 0 2006.175.08:15:10.28#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:15:10.28#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:15:10.28#ibcon#[25=USB\r\n] 2006.175.08:15:10.28#ibcon#*before write, iclass 3, count 0 2006.175.08:15:10.28#ibcon#enter sib2, iclass 3, count 0 2006.175.08:15:10.28#ibcon#flushed, iclass 3, count 0 2006.175.08:15:10.28#ibcon#about to write, iclass 3, count 0 2006.175.08:15:10.28#ibcon#wrote, iclass 3, count 0 2006.175.08:15:10.28#ibcon#about to read 3, iclass 3, count 0 2006.175.08:15:10.31#ibcon#read 3, iclass 3, count 0 2006.175.08:15:10.31#ibcon#about to read 4, iclass 3, count 0 2006.175.08:15:10.31#ibcon#read 4, iclass 3, count 0 2006.175.08:15:10.31#ibcon#about to read 5, iclass 3, count 0 2006.175.08:15:10.31#ibcon#read 5, iclass 3, count 0 2006.175.08:15:10.31#ibcon#about to read 6, iclass 3, count 0 2006.175.08:15:10.31#ibcon#read 6, iclass 3, count 0 2006.175.08:15:10.31#ibcon#end of sib2, iclass 3, count 0 2006.175.08:15:10.31#ibcon#*after write, iclass 3, count 0 2006.175.08:15:10.31#ibcon#*before return 0, iclass 3, count 0 2006.175.08:15:10.31#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:15:10.31#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:15:10.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:15:10.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:15:10.31$vc4f8/valo=8,852.99 2006.175.08:15:10.31#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.08:15:10.31#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.08:15:10.31#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:10.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:15:10.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:15:10.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:15:10.31#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:15:10.31#ibcon#first serial, iclass 5, count 0 2006.175.08:15:10.31#ibcon#enter sib2, iclass 5, count 0 2006.175.08:15:10.31#ibcon#flushed, iclass 5, count 0 2006.175.08:15:10.31#ibcon#about to write, iclass 5, count 0 2006.175.08:15:10.31#ibcon#wrote, iclass 5, count 0 2006.175.08:15:10.31#ibcon#about to read 3, iclass 5, count 0 2006.175.08:15:10.33#ibcon#read 3, iclass 5, count 0 2006.175.08:15:10.33#ibcon#about to read 4, iclass 5, count 0 2006.175.08:15:10.33#ibcon#read 4, iclass 5, count 0 2006.175.08:15:10.33#ibcon#about to read 5, iclass 5, count 0 2006.175.08:15:10.33#ibcon#read 5, iclass 5, count 0 2006.175.08:15:10.33#ibcon#about to read 6, iclass 5, count 0 2006.175.08:15:10.33#ibcon#read 6, iclass 5, count 0 2006.175.08:15:10.33#ibcon#end of sib2, iclass 5, count 0 2006.175.08:15:10.33#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:15:10.33#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:15:10.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:15:10.33#ibcon#*before write, iclass 5, count 0 2006.175.08:15:10.33#ibcon#enter sib2, iclass 5, count 0 2006.175.08:15:10.33#ibcon#flushed, iclass 5, count 0 2006.175.08:15:10.33#ibcon#about to write, iclass 5, count 0 2006.175.08:15:10.33#ibcon#wrote, iclass 5, count 0 2006.175.08:15:10.33#ibcon#about to read 3, iclass 5, count 0 2006.175.08:15:10.37#ibcon#read 3, iclass 5, count 0 2006.175.08:15:10.37#ibcon#about to read 4, iclass 5, count 0 2006.175.08:15:10.37#ibcon#read 4, iclass 5, count 0 2006.175.08:15:10.37#ibcon#about to read 5, iclass 5, count 0 2006.175.08:15:10.37#ibcon#read 5, iclass 5, count 0 2006.175.08:15:10.37#ibcon#about to read 6, iclass 5, count 0 2006.175.08:15:10.37#ibcon#read 6, iclass 5, count 0 2006.175.08:15:10.37#ibcon#end of sib2, iclass 5, count 0 2006.175.08:15:10.37#ibcon#*after write, iclass 5, count 0 2006.175.08:15:10.37#ibcon#*before return 0, iclass 5, count 0 2006.175.08:15:10.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:15:10.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:15:10.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:15:10.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:15:10.37$vc4f8/va=8,6 2006.175.08:15:10.37#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.08:15:10.37#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.08:15:10.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:10.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:15:10.43#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:15:10.43#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:15:10.43#ibcon#enter wrdev, iclass 7, count 2 2006.175.08:15:10.43#ibcon#first serial, iclass 7, count 2 2006.175.08:15:10.43#ibcon#enter sib2, iclass 7, count 2 2006.175.08:15:10.43#ibcon#flushed, iclass 7, count 2 2006.175.08:15:10.43#ibcon#about to write, iclass 7, count 2 2006.175.08:15:10.43#ibcon#wrote, iclass 7, count 2 2006.175.08:15:10.43#ibcon#about to read 3, iclass 7, count 2 2006.175.08:15:10.45#ibcon#read 3, iclass 7, count 2 2006.175.08:15:10.45#ibcon#about to read 4, iclass 7, count 2 2006.175.08:15:10.45#ibcon#read 4, iclass 7, count 2 2006.175.08:15:10.45#ibcon#about to read 5, iclass 7, count 2 2006.175.08:15:10.45#ibcon#read 5, iclass 7, count 2 2006.175.08:15:10.45#ibcon#about to read 6, iclass 7, count 2 2006.175.08:15:10.45#ibcon#read 6, iclass 7, count 2 2006.175.08:15:10.45#ibcon#end of sib2, iclass 7, count 2 2006.175.08:15:10.45#ibcon#*mode == 0, iclass 7, count 2 2006.175.08:15:10.45#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.08:15:10.45#ibcon#[25=AT08-06\r\n] 2006.175.08:15:10.45#ibcon#*before write, iclass 7, count 2 2006.175.08:15:10.45#ibcon#enter sib2, iclass 7, count 2 2006.175.08:15:10.45#ibcon#flushed, iclass 7, count 2 2006.175.08:15:10.45#ibcon#about to write, iclass 7, count 2 2006.175.08:15:10.45#ibcon#wrote, iclass 7, count 2 2006.175.08:15:10.45#ibcon#about to read 3, iclass 7, count 2 2006.175.08:15:10.48#ibcon#read 3, iclass 7, count 2 2006.175.08:15:10.48#ibcon#about to read 4, iclass 7, count 2 2006.175.08:15:10.48#ibcon#read 4, iclass 7, count 2 2006.175.08:15:10.48#ibcon#about to read 5, iclass 7, count 2 2006.175.08:15:10.48#ibcon#read 5, iclass 7, count 2 2006.175.08:15:10.48#ibcon#about to read 6, iclass 7, count 2 2006.175.08:15:10.48#ibcon#read 6, iclass 7, count 2 2006.175.08:15:10.48#ibcon#end of sib2, iclass 7, count 2 2006.175.08:15:10.48#ibcon#*after write, iclass 7, count 2 2006.175.08:15:10.48#ibcon#*before return 0, iclass 7, count 2 2006.175.08:15:10.48#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:15:10.48#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:15:10.48#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.08:15:10.48#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:10.48#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:15:10.60#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:15:10.60#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:15:10.60#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:15:10.60#ibcon#first serial, iclass 7, count 0 2006.175.08:15:10.60#ibcon#enter sib2, iclass 7, count 0 2006.175.08:15:10.60#ibcon#flushed, iclass 7, count 0 2006.175.08:15:10.60#ibcon#about to write, iclass 7, count 0 2006.175.08:15:10.60#ibcon#wrote, iclass 7, count 0 2006.175.08:15:10.60#ibcon#about to read 3, iclass 7, count 0 2006.175.08:15:10.62#ibcon#read 3, iclass 7, count 0 2006.175.08:15:10.62#ibcon#about to read 4, iclass 7, count 0 2006.175.08:15:10.62#ibcon#read 4, iclass 7, count 0 2006.175.08:15:10.62#ibcon#about to read 5, iclass 7, count 0 2006.175.08:15:10.62#ibcon#read 5, iclass 7, count 0 2006.175.08:15:10.62#ibcon#about to read 6, iclass 7, count 0 2006.175.08:15:10.62#ibcon#read 6, iclass 7, count 0 2006.175.08:15:10.62#ibcon#end of sib2, iclass 7, count 0 2006.175.08:15:10.62#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:15:10.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:15:10.62#ibcon#[25=USB\r\n] 2006.175.08:15:10.62#ibcon#*before write, iclass 7, count 0 2006.175.08:15:10.62#ibcon#enter sib2, iclass 7, count 0 2006.175.08:15:10.62#ibcon#flushed, iclass 7, count 0 2006.175.08:15:10.62#ibcon#about to write, iclass 7, count 0 2006.175.08:15:10.62#ibcon#wrote, iclass 7, count 0 2006.175.08:15:10.62#ibcon#about to read 3, iclass 7, count 0 2006.175.08:15:10.65#ibcon#read 3, iclass 7, count 0 2006.175.08:15:10.65#ibcon#about to read 4, iclass 7, count 0 2006.175.08:15:10.65#ibcon#read 4, iclass 7, count 0 2006.175.08:15:10.65#ibcon#about to read 5, iclass 7, count 0 2006.175.08:15:10.65#ibcon#read 5, iclass 7, count 0 2006.175.08:15:10.65#ibcon#about to read 6, iclass 7, count 0 2006.175.08:15:10.65#ibcon#read 6, iclass 7, count 0 2006.175.08:15:10.65#ibcon#end of sib2, iclass 7, count 0 2006.175.08:15:10.65#ibcon#*after write, iclass 7, count 0 2006.175.08:15:10.65#ibcon#*before return 0, iclass 7, count 0 2006.175.08:15:10.65#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:15:10.65#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:15:10.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:15:10.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:15:10.65$vc4f8/vblo=1,632.99 2006.175.08:15:10.65#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.08:15:10.65#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.08:15:10.65#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:10.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:15:10.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:15:10.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:15:10.65#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:15:10.65#ibcon#first serial, iclass 11, count 0 2006.175.08:15:10.65#ibcon#enter sib2, iclass 11, count 0 2006.175.08:15:10.65#ibcon#flushed, iclass 11, count 0 2006.175.08:15:10.65#ibcon#about to write, iclass 11, count 0 2006.175.08:15:10.65#ibcon#wrote, iclass 11, count 0 2006.175.08:15:10.65#ibcon#about to read 3, iclass 11, count 0 2006.175.08:15:10.67#ibcon#read 3, iclass 11, count 0 2006.175.08:15:10.67#ibcon#about to read 4, iclass 11, count 0 2006.175.08:15:10.67#ibcon#read 4, iclass 11, count 0 2006.175.08:15:10.67#ibcon#about to read 5, iclass 11, count 0 2006.175.08:15:10.67#ibcon#read 5, iclass 11, count 0 2006.175.08:15:10.67#ibcon#about to read 6, iclass 11, count 0 2006.175.08:15:10.67#ibcon#read 6, iclass 11, count 0 2006.175.08:15:10.67#ibcon#end of sib2, iclass 11, count 0 2006.175.08:15:10.67#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:15:10.67#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:15:10.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:15:10.67#ibcon#*before write, iclass 11, count 0 2006.175.08:15:10.67#ibcon#enter sib2, iclass 11, count 0 2006.175.08:15:10.67#ibcon#flushed, iclass 11, count 0 2006.175.08:15:10.67#ibcon#about to write, iclass 11, count 0 2006.175.08:15:10.67#ibcon#wrote, iclass 11, count 0 2006.175.08:15:10.67#ibcon#about to read 3, iclass 11, count 0 2006.175.08:15:10.71#ibcon#read 3, iclass 11, count 0 2006.175.08:15:10.71#ibcon#about to read 4, iclass 11, count 0 2006.175.08:15:10.71#ibcon#read 4, iclass 11, count 0 2006.175.08:15:10.71#ibcon#about to read 5, iclass 11, count 0 2006.175.08:15:10.71#ibcon#read 5, iclass 11, count 0 2006.175.08:15:10.71#ibcon#about to read 6, iclass 11, count 0 2006.175.08:15:10.71#ibcon#read 6, iclass 11, count 0 2006.175.08:15:10.71#ibcon#end of sib2, iclass 11, count 0 2006.175.08:15:10.71#ibcon#*after write, iclass 11, count 0 2006.175.08:15:10.71#ibcon#*before return 0, iclass 11, count 0 2006.175.08:15:10.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:15:10.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:15:10.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:15:10.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:15:10.71$vc4f8/vb=1,4 2006.175.08:15:10.71#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.08:15:10.71#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.08:15:10.71#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:10.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:15:10.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:15:10.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:15:10.71#ibcon#enter wrdev, iclass 13, count 2 2006.175.08:15:10.71#ibcon#first serial, iclass 13, count 2 2006.175.08:15:10.71#ibcon#enter sib2, iclass 13, count 2 2006.175.08:15:10.71#ibcon#flushed, iclass 13, count 2 2006.175.08:15:10.71#ibcon#about to write, iclass 13, count 2 2006.175.08:15:10.71#ibcon#wrote, iclass 13, count 2 2006.175.08:15:10.71#ibcon#about to read 3, iclass 13, count 2 2006.175.08:15:10.73#ibcon#read 3, iclass 13, count 2 2006.175.08:15:10.73#ibcon#about to read 4, iclass 13, count 2 2006.175.08:15:10.73#ibcon#read 4, iclass 13, count 2 2006.175.08:15:10.73#ibcon#about to read 5, iclass 13, count 2 2006.175.08:15:10.73#ibcon#read 5, iclass 13, count 2 2006.175.08:15:10.73#ibcon#about to read 6, iclass 13, count 2 2006.175.08:15:10.73#ibcon#read 6, iclass 13, count 2 2006.175.08:15:10.73#ibcon#end of sib2, iclass 13, count 2 2006.175.08:15:10.73#ibcon#*mode == 0, iclass 13, count 2 2006.175.08:15:10.73#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.08:15:10.73#ibcon#[27=AT01-04\r\n] 2006.175.08:15:10.73#ibcon#*before write, iclass 13, count 2 2006.175.08:15:10.73#ibcon#enter sib2, iclass 13, count 2 2006.175.08:15:10.73#ibcon#flushed, iclass 13, count 2 2006.175.08:15:10.73#ibcon#about to write, iclass 13, count 2 2006.175.08:15:10.73#ibcon#wrote, iclass 13, count 2 2006.175.08:15:10.73#ibcon#about to read 3, iclass 13, count 2 2006.175.08:15:10.76#ibcon#read 3, iclass 13, count 2 2006.175.08:15:10.76#ibcon#about to read 4, iclass 13, count 2 2006.175.08:15:10.76#ibcon#read 4, iclass 13, count 2 2006.175.08:15:10.76#ibcon#about to read 5, iclass 13, count 2 2006.175.08:15:10.76#ibcon#read 5, iclass 13, count 2 2006.175.08:15:10.76#ibcon#about to read 6, iclass 13, count 2 2006.175.08:15:10.76#ibcon#read 6, iclass 13, count 2 2006.175.08:15:10.76#ibcon#end of sib2, iclass 13, count 2 2006.175.08:15:10.76#ibcon#*after write, iclass 13, count 2 2006.175.08:15:10.76#ibcon#*before return 0, iclass 13, count 2 2006.175.08:15:10.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:15:10.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:15:10.76#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.08:15:10.76#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:10.76#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:15:10.88#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:15:10.88#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:15:10.88#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:15:10.88#ibcon#first serial, iclass 13, count 0 2006.175.08:15:10.88#ibcon#enter sib2, iclass 13, count 0 2006.175.08:15:10.88#ibcon#flushed, iclass 13, count 0 2006.175.08:15:10.88#ibcon#about to write, iclass 13, count 0 2006.175.08:15:10.88#ibcon#wrote, iclass 13, count 0 2006.175.08:15:10.88#ibcon#about to read 3, iclass 13, count 0 2006.175.08:15:10.90#ibcon#read 3, iclass 13, count 0 2006.175.08:15:10.90#ibcon#about to read 4, iclass 13, count 0 2006.175.08:15:10.90#ibcon#read 4, iclass 13, count 0 2006.175.08:15:10.90#ibcon#about to read 5, iclass 13, count 0 2006.175.08:15:10.90#ibcon#read 5, iclass 13, count 0 2006.175.08:15:10.90#ibcon#about to read 6, iclass 13, count 0 2006.175.08:15:10.90#ibcon#read 6, iclass 13, count 0 2006.175.08:15:10.90#ibcon#end of sib2, iclass 13, count 0 2006.175.08:15:10.90#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:15:10.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:15:10.90#ibcon#[27=USB\r\n] 2006.175.08:15:10.90#ibcon#*before write, iclass 13, count 0 2006.175.08:15:10.90#ibcon#enter sib2, iclass 13, count 0 2006.175.08:15:10.90#ibcon#flushed, iclass 13, count 0 2006.175.08:15:10.90#ibcon#about to write, iclass 13, count 0 2006.175.08:15:10.90#ibcon#wrote, iclass 13, count 0 2006.175.08:15:10.90#ibcon#about to read 3, iclass 13, count 0 2006.175.08:15:10.93#ibcon#read 3, iclass 13, count 0 2006.175.08:15:10.93#ibcon#about to read 4, iclass 13, count 0 2006.175.08:15:10.93#ibcon#read 4, iclass 13, count 0 2006.175.08:15:10.93#ibcon#about to read 5, iclass 13, count 0 2006.175.08:15:10.93#ibcon#read 5, iclass 13, count 0 2006.175.08:15:10.93#ibcon#about to read 6, iclass 13, count 0 2006.175.08:15:10.93#ibcon#read 6, iclass 13, count 0 2006.175.08:15:10.93#ibcon#end of sib2, iclass 13, count 0 2006.175.08:15:10.93#ibcon#*after write, iclass 13, count 0 2006.175.08:15:10.93#ibcon#*before return 0, iclass 13, count 0 2006.175.08:15:10.93#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:15:10.93#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:15:10.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:15:10.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:15:10.93$vc4f8/vblo=2,640.99 2006.175.08:15:10.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.08:15:10.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.08:15:10.93#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:10.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:10.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:10.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:10.93#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:15:10.93#ibcon#first serial, iclass 15, count 0 2006.175.08:15:10.93#ibcon#enter sib2, iclass 15, count 0 2006.175.08:15:10.93#ibcon#flushed, iclass 15, count 0 2006.175.08:15:10.93#ibcon#about to write, iclass 15, count 0 2006.175.08:15:10.93#ibcon#wrote, iclass 15, count 0 2006.175.08:15:10.93#ibcon#about to read 3, iclass 15, count 0 2006.175.08:15:10.95#ibcon#read 3, iclass 15, count 0 2006.175.08:15:10.95#ibcon#about to read 4, iclass 15, count 0 2006.175.08:15:10.95#ibcon#read 4, iclass 15, count 0 2006.175.08:15:10.95#ibcon#about to read 5, iclass 15, count 0 2006.175.08:15:10.95#ibcon#read 5, iclass 15, count 0 2006.175.08:15:10.95#ibcon#about to read 6, iclass 15, count 0 2006.175.08:15:10.95#ibcon#read 6, iclass 15, count 0 2006.175.08:15:10.95#ibcon#end of sib2, iclass 15, count 0 2006.175.08:15:10.95#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:15:10.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:15:10.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:15:10.95#ibcon#*before write, iclass 15, count 0 2006.175.08:15:10.95#ibcon#enter sib2, iclass 15, count 0 2006.175.08:15:10.95#ibcon#flushed, iclass 15, count 0 2006.175.08:15:10.95#ibcon#about to write, iclass 15, count 0 2006.175.08:15:10.95#ibcon#wrote, iclass 15, count 0 2006.175.08:15:10.95#ibcon#about to read 3, iclass 15, count 0 2006.175.08:15:10.99#ibcon#read 3, iclass 15, count 0 2006.175.08:15:10.99#ibcon#about to read 4, iclass 15, count 0 2006.175.08:15:10.99#ibcon#read 4, iclass 15, count 0 2006.175.08:15:10.99#ibcon#about to read 5, iclass 15, count 0 2006.175.08:15:10.99#ibcon#read 5, iclass 15, count 0 2006.175.08:15:10.99#ibcon#about to read 6, iclass 15, count 0 2006.175.08:15:10.99#ibcon#read 6, iclass 15, count 0 2006.175.08:15:10.99#ibcon#end of sib2, iclass 15, count 0 2006.175.08:15:10.99#ibcon#*after write, iclass 15, count 0 2006.175.08:15:10.99#ibcon#*before return 0, iclass 15, count 0 2006.175.08:15:10.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:10.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:15:10.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:15:10.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:15:10.99$vc4f8/vb=2,4 2006.175.08:15:10.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.08:15:10.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.08:15:10.99#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:10.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:11.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:11.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:11.05#ibcon#enter wrdev, iclass 17, count 2 2006.175.08:15:11.05#ibcon#first serial, iclass 17, count 2 2006.175.08:15:11.05#ibcon#enter sib2, iclass 17, count 2 2006.175.08:15:11.05#ibcon#flushed, iclass 17, count 2 2006.175.08:15:11.05#ibcon#about to write, iclass 17, count 2 2006.175.08:15:11.05#ibcon#wrote, iclass 17, count 2 2006.175.08:15:11.05#ibcon#about to read 3, iclass 17, count 2 2006.175.08:15:11.07#ibcon#read 3, iclass 17, count 2 2006.175.08:15:11.07#ibcon#about to read 4, iclass 17, count 2 2006.175.08:15:11.07#ibcon#read 4, iclass 17, count 2 2006.175.08:15:11.07#ibcon#about to read 5, iclass 17, count 2 2006.175.08:15:11.07#ibcon#read 5, iclass 17, count 2 2006.175.08:15:11.07#ibcon#about to read 6, iclass 17, count 2 2006.175.08:15:11.07#ibcon#read 6, iclass 17, count 2 2006.175.08:15:11.07#ibcon#end of sib2, iclass 17, count 2 2006.175.08:15:11.07#ibcon#*mode == 0, iclass 17, count 2 2006.175.08:15:11.07#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.08:15:11.07#ibcon#[27=AT02-04\r\n] 2006.175.08:15:11.07#ibcon#*before write, iclass 17, count 2 2006.175.08:15:11.07#ibcon#enter sib2, iclass 17, count 2 2006.175.08:15:11.07#ibcon#flushed, iclass 17, count 2 2006.175.08:15:11.07#ibcon#about to write, iclass 17, count 2 2006.175.08:15:11.07#ibcon#wrote, iclass 17, count 2 2006.175.08:15:11.07#ibcon#about to read 3, iclass 17, count 2 2006.175.08:15:11.10#ibcon#read 3, iclass 17, count 2 2006.175.08:15:11.10#ibcon#about to read 4, iclass 17, count 2 2006.175.08:15:11.10#ibcon#read 4, iclass 17, count 2 2006.175.08:15:11.10#ibcon#about to read 5, iclass 17, count 2 2006.175.08:15:11.10#ibcon#read 5, iclass 17, count 2 2006.175.08:15:11.10#ibcon#about to read 6, iclass 17, count 2 2006.175.08:15:11.10#ibcon#read 6, iclass 17, count 2 2006.175.08:15:11.10#ibcon#end of sib2, iclass 17, count 2 2006.175.08:15:11.10#ibcon#*after write, iclass 17, count 2 2006.175.08:15:11.10#ibcon#*before return 0, iclass 17, count 2 2006.175.08:15:11.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:11.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:15:11.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.08:15:11.10#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:11.10#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:11.22#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:11.22#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:11.22#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:15:11.22#ibcon#first serial, iclass 17, count 0 2006.175.08:15:11.22#ibcon#enter sib2, iclass 17, count 0 2006.175.08:15:11.22#ibcon#flushed, iclass 17, count 0 2006.175.08:15:11.22#ibcon#about to write, iclass 17, count 0 2006.175.08:15:11.22#ibcon#wrote, iclass 17, count 0 2006.175.08:15:11.22#ibcon#about to read 3, iclass 17, count 0 2006.175.08:15:11.24#ibcon#read 3, iclass 17, count 0 2006.175.08:15:11.24#ibcon#about to read 4, iclass 17, count 0 2006.175.08:15:11.24#ibcon#read 4, iclass 17, count 0 2006.175.08:15:11.24#ibcon#about to read 5, iclass 17, count 0 2006.175.08:15:11.24#ibcon#read 5, iclass 17, count 0 2006.175.08:15:11.24#ibcon#about to read 6, iclass 17, count 0 2006.175.08:15:11.24#ibcon#read 6, iclass 17, count 0 2006.175.08:15:11.24#ibcon#end of sib2, iclass 17, count 0 2006.175.08:15:11.24#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:15:11.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:15:11.24#ibcon#[27=USB\r\n] 2006.175.08:15:11.24#ibcon#*before write, iclass 17, count 0 2006.175.08:15:11.24#ibcon#enter sib2, iclass 17, count 0 2006.175.08:15:11.24#ibcon#flushed, iclass 17, count 0 2006.175.08:15:11.24#ibcon#about to write, iclass 17, count 0 2006.175.08:15:11.24#ibcon#wrote, iclass 17, count 0 2006.175.08:15:11.24#ibcon#about to read 3, iclass 17, count 0 2006.175.08:15:11.27#ibcon#read 3, iclass 17, count 0 2006.175.08:15:11.27#ibcon#about to read 4, iclass 17, count 0 2006.175.08:15:11.27#ibcon#read 4, iclass 17, count 0 2006.175.08:15:11.27#ibcon#about to read 5, iclass 17, count 0 2006.175.08:15:11.27#ibcon#read 5, iclass 17, count 0 2006.175.08:15:11.27#ibcon#about to read 6, iclass 17, count 0 2006.175.08:15:11.27#ibcon#read 6, iclass 17, count 0 2006.175.08:15:11.27#ibcon#end of sib2, iclass 17, count 0 2006.175.08:15:11.27#ibcon#*after write, iclass 17, count 0 2006.175.08:15:11.27#ibcon#*before return 0, iclass 17, count 0 2006.175.08:15:11.27#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:11.27#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:15:11.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:15:11.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:15:11.27$vc4f8/vblo=3,656.99 2006.175.08:15:11.27#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.08:15:11.27#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.08:15:11.27#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:11.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:11.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:11.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:11.27#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:15:11.27#ibcon#first serial, iclass 19, count 0 2006.175.08:15:11.27#ibcon#enter sib2, iclass 19, count 0 2006.175.08:15:11.27#ibcon#flushed, iclass 19, count 0 2006.175.08:15:11.27#ibcon#about to write, iclass 19, count 0 2006.175.08:15:11.27#ibcon#wrote, iclass 19, count 0 2006.175.08:15:11.27#ibcon#about to read 3, iclass 19, count 0 2006.175.08:15:11.29#ibcon#read 3, iclass 19, count 0 2006.175.08:15:11.29#ibcon#about to read 4, iclass 19, count 0 2006.175.08:15:11.29#ibcon#read 4, iclass 19, count 0 2006.175.08:15:11.29#ibcon#about to read 5, iclass 19, count 0 2006.175.08:15:11.29#ibcon#read 5, iclass 19, count 0 2006.175.08:15:11.29#ibcon#about to read 6, iclass 19, count 0 2006.175.08:15:11.29#ibcon#read 6, iclass 19, count 0 2006.175.08:15:11.29#ibcon#end of sib2, iclass 19, count 0 2006.175.08:15:11.29#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:15:11.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:15:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:15:11.29#ibcon#*before write, iclass 19, count 0 2006.175.08:15:11.29#ibcon#enter sib2, iclass 19, count 0 2006.175.08:15:11.29#ibcon#flushed, iclass 19, count 0 2006.175.08:15:11.29#ibcon#about to write, iclass 19, count 0 2006.175.08:15:11.29#ibcon#wrote, iclass 19, count 0 2006.175.08:15:11.29#ibcon#about to read 3, iclass 19, count 0 2006.175.08:15:11.33#ibcon#read 3, iclass 19, count 0 2006.175.08:15:11.33#ibcon#about to read 4, iclass 19, count 0 2006.175.08:15:11.33#ibcon#read 4, iclass 19, count 0 2006.175.08:15:11.33#ibcon#about to read 5, iclass 19, count 0 2006.175.08:15:11.33#ibcon#read 5, iclass 19, count 0 2006.175.08:15:11.33#ibcon#about to read 6, iclass 19, count 0 2006.175.08:15:11.33#ibcon#read 6, iclass 19, count 0 2006.175.08:15:11.33#ibcon#end of sib2, iclass 19, count 0 2006.175.08:15:11.33#ibcon#*after write, iclass 19, count 0 2006.175.08:15:11.33#ibcon#*before return 0, iclass 19, count 0 2006.175.08:15:11.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:11.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:15:11.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:15:11.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:15:11.33$vc4f8/vb=3,4 2006.175.08:15:11.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.08:15:11.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.08:15:11.33#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:11.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:11.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:11.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:11.39#ibcon#enter wrdev, iclass 21, count 2 2006.175.08:15:11.39#ibcon#first serial, iclass 21, count 2 2006.175.08:15:11.39#ibcon#enter sib2, iclass 21, count 2 2006.175.08:15:11.39#ibcon#flushed, iclass 21, count 2 2006.175.08:15:11.39#ibcon#about to write, iclass 21, count 2 2006.175.08:15:11.39#ibcon#wrote, iclass 21, count 2 2006.175.08:15:11.39#ibcon#about to read 3, iclass 21, count 2 2006.175.08:15:11.41#ibcon#read 3, iclass 21, count 2 2006.175.08:15:11.41#ibcon#about to read 4, iclass 21, count 2 2006.175.08:15:11.41#ibcon#read 4, iclass 21, count 2 2006.175.08:15:11.41#ibcon#about to read 5, iclass 21, count 2 2006.175.08:15:11.41#ibcon#read 5, iclass 21, count 2 2006.175.08:15:11.41#ibcon#about to read 6, iclass 21, count 2 2006.175.08:15:11.41#ibcon#read 6, iclass 21, count 2 2006.175.08:15:11.41#ibcon#end of sib2, iclass 21, count 2 2006.175.08:15:11.41#ibcon#*mode == 0, iclass 21, count 2 2006.175.08:15:11.41#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.08:15:11.41#ibcon#[27=AT03-04\r\n] 2006.175.08:15:11.41#ibcon#*before write, iclass 21, count 2 2006.175.08:15:11.41#ibcon#enter sib2, iclass 21, count 2 2006.175.08:15:11.41#ibcon#flushed, iclass 21, count 2 2006.175.08:15:11.41#ibcon#about to write, iclass 21, count 2 2006.175.08:15:11.41#ibcon#wrote, iclass 21, count 2 2006.175.08:15:11.41#ibcon#about to read 3, iclass 21, count 2 2006.175.08:15:11.44#ibcon#read 3, iclass 21, count 2 2006.175.08:15:11.44#ibcon#about to read 4, iclass 21, count 2 2006.175.08:15:11.44#ibcon#read 4, iclass 21, count 2 2006.175.08:15:11.44#ibcon#about to read 5, iclass 21, count 2 2006.175.08:15:11.44#ibcon#read 5, iclass 21, count 2 2006.175.08:15:11.44#ibcon#about to read 6, iclass 21, count 2 2006.175.08:15:11.44#ibcon#read 6, iclass 21, count 2 2006.175.08:15:11.44#ibcon#end of sib2, iclass 21, count 2 2006.175.08:15:11.44#ibcon#*after write, iclass 21, count 2 2006.175.08:15:11.44#ibcon#*before return 0, iclass 21, count 2 2006.175.08:15:11.44#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:11.44#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:15:11.44#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.08:15:11.44#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:11.44#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:11.56#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:11.56#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:11.56#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:15:11.56#ibcon#first serial, iclass 21, count 0 2006.175.08:15:11.56#ibcon#enter sib2, iclass 21, count 0 2006.175.08:15:11.56#ibcon#flushed, iclass 21, count 0 2006.175.08:15:11.56#ibcon#about to write, iclass 21, count 0 2006.175.08:15:11.56#ibcon#wrote, iclass 21, count 0 2006.175.08:15:11.56#ibcon#about to read 3, iclass 21, count 0 2006.175.08:15:11.58#ibcon#read 3, iclass 21, count 0 2006.175.08:15:11.58#ibcon#about to read 4, iclass 21, count 0 2006.175.08:15:11.58#ibcon#read 4, iclass 21, count 0 2006.175.08:15:11.58#ibcon#about to read 5, iclass 21, count 0 2006.175.08:15:11.58#ibcon#read 5, iclass 21, count 0 2006.175.08:15:11.58#ibcon#about to read 6, iclass 21, count 0 2006.175.08:15:11.58#ibcon#read 6, iclass 21, count 0 2006.175.08:15:11.58#ibcon#end of sib2, iclass 21, count 0 2006.175.08:15:11.58#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:15:11.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:15:11.58#ibcon#[27=USB\r\n] 2006.175.08:15:11.58#ibcon#*before write, iclass 21, count 0 2006.175.08:15:11.58#ibcon#enter sib2, iclass 21, count 0 2006.175.08:15:11.58#ibcon#flushed, iclass 21, count 0 2006.175.08:15:11.58#ibcon#about to write, iclass 21, count 0 2006.175.08:15:11.58#ibcon#wrote, iclass 21, count 0 2006.175.08:15:11.58#ibcon#about to read 3, iclass 21, count 0 2006.175.08:15:11.61#ibcon#read 3, iclass 21, count 0 2006.175.08:15:11.61#ibcon#about to read 4, iclass 21, count 0 2006.175.08:15:11.61#ibcon#read 4, iclass 21, count 0 2006.175.08:15:11.61#ibcon#about to read 5, iclass 21, count 0 2006.175.08:15:11.61#ibcon#read 5, iclass 21, count 0 2006.175.08:15:11.61#ibcon#about to read 6, iclass 21, count 0 2006.175.08:15:11.61#ibcon#read 6, iclass 21, count 0 2006.175.08:15:11.61#ibcon#end of sib2, iclass 21, count 0 2006.175.08:15:11.61#ibcon#*after write, iclass 21, count 0 2006.175.08:15:11.61#ibcon#*before return 0, iclass 21, count 0 2006.175.08:15:11.61#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:11.61#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:15:11.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:15:11.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:15:11.61$vc4f8/vblo=4,712.99 2006.175.08:15:11.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.08:15:11.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.08:15:11.61#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:11.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:11.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:11.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:11.61#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:15:11.61#ibcon#first serial, iclass 23, count 0 2006.175.08:15:11.61#ibcon#enter sib2, iclass 23, count 0 2006.175.08:15:11.61#ibcon#flushed, iclass 23, count 0 2006.175.08:15:11.61#ibcon#about to write, iclass 23, count 0 2006.175.08:15:11.61#ibcon#wrote, iclass 23, count 0 2006.175.08:15:11.61#ibcon#about to read 3, iclass 23, count 0 2006.175.08:15:11.63#ibcon#read 3, iclass 23, count 0 2006.175.08:15:11.63#ibcon#about to read 4, iclass 23, count 0 2006.175.08:15:11.63#ibcon#read 4, iclass 23, count 0 2006.175.08:15:11.63#ibcon#about to read 5, iclass 23, count 0 2006.175.08:15:11.63#ibcon#read 5, iclass 23, count 0 2006.175.08:15:11.63#ibcon#about to read 6, iclass 23, count 0 2006.175.08:15:11.63#ibcon#read 6, iclass 23, count 0 2006.175.08:15:11.63#ibcon#end of sib2, iclass 23, count 0 2006.175.08:15:11.63#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:15:11.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:15:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:15:11.63#ibcon#*before write, iclass 23, count 0 2006.175.08:15:11.63#ibcon#enter sib2, iclass 23, count 0 2006.175.08:15:11.63#ibcon#flushed, iclass 23, count 0 2006.175.08:15:11.63#ibcon#about to write, iclass 23, count 0 2006.175.08:15:11.63#ibcon#wrote, iclass 23, count 0 2006.175.08:15:11.63#ibcon#about to read 3, iclass 23, count 0 2006.175.08:15:11.67#ibcon#read 3, iclass 23, count 0 2006.175.08:15:11.67#ibcon#about to read 4, iclass 23, count 0 2006.175.08:15:11.67#ibcon#read 4, iclass 23, count 0 2006.175.08:15:11.67#ibcon#about to read 5, iclass 23, count 0 2006.175.08:15:11.67#ibcon#read 5, iclass 23, count 0 2006.175.08:15:11.67#ibcon#about to read 6, iclass 23, count 0 2006.175.08:15:11.67#ibcon#read 6, iclass 23, count 0 2006.175.08:15:11.67#ibcon#end of sib2, iclass 23, count 0 2006.175.08:15:11.67#ibcon#*after write, iclass 23, count 0 2006.175.08:15:11.67#ibcon#*before return 0, iclass 23, count 0 2006.175.08:15:11.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:11.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:15:11.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:15:11.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:15:11.67$vc4f8/vb=4,4 2006.175.08:15:11.67#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.08:15:11.67#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.08:15:11.67#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:11.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:11.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:11.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:11.73#ibcon#enter wrdev, iclass 25, count 2 2006.175.08:15:11.73#ibcon#first serial, iclass 25, count 2 2006.175.08:15:11.73#ibcon#enter sib2, iclass 25, count 2 2006.175.08:15:11.73#ibcon#flushed, iclass 25, count 2 2006.175.08:15:11.73#ibcon#about to write, iclass 25, count 2 2006.175.08:15:11.73#ibcon#wrote, iclass 25, count 2 2006.175.08:15:11.73#ibcon#about to read 3, iclass 25, count 2 2006.175.08:15:11.75#ibcon#read 3, iclass 25, count 2 2006.175.08:15:11.75#ibcon#about to read 4, iclass 25, count 2 2006.175.08:15:11.75#ibcon#read 4, iclass 25, count 2 2006.175.08:15:11.75#ibcon#about to read 5, iclass 25, count 2 2006.175.08:15:11.75#ibcon#read 5, iclass 25, count 2 2006.175.08:15:11.75#ibcon#about to read 6, iclass 25, count 2 2006.175.08:15:11.75#ibcon#read 6, iclass 25, count 2 2006.175.08:15:11.75#ibcon#end of sib2, iclass 25, count 2 2006.175.08:15:11.75#ibcon#*mode == 0, iclass 25, count 2 2006.175.08:15:11.75#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.08:15:11.75#ibcon#[27=AT04-04\r\n] 2006.175.08:15:11.75#ibcon#*before write, iclass 25, count 2 2006.175.08:15:11.75#ibcon#enter sib2, iclass 25, count 2 2006.175.08:15:11.75#ibcon#flushed, iclass 25, count 2 2006.175.08:15:11.75#ibcon#about to write, iclass 25, count 2 2006.175.08:15:11.75#ibcon#wrote, iclass 25, count 2 2006.175.08:15:11.75#ibcon#about to read 3, iclass 25, count 2 2006.175.08:15:11.78#ibcon#read 3, iclass 25, count 2 2006.175.08:15:11.78#ibcon#about to read 4, iclass 25, count 2 2006.175.08:15:11.78#ibcon#read 4, iclass 25, count 2 2006.175.08:15:11.78#ibcon#about to read 5, iclass 25, count 2 2006.175.08:15:11.78#ibcon#read 5, iclass 25, count 2 2006.175.08:15:11.78#ibcon#about to read 6, iclass 25, count 2 2006.175.08:15:11.78#ibcon#read 6, iclass 25, count 2 2006.175.08:15:11.78#ibcon#end of sib2, iclass 25, count 2 2006.175.08:15:11.78#ibcon#*after write, iclass 25, count 2 2006.175.08:15:11.78#ibcon#*before return 0, iclass 25, count 2 2006.175.08:15:11.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:11.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:15:11.78#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.08:15:11.78#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:11.78#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:11.90#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:11.90#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:11.90#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:15:11.90#ibcon#first serial, iclass 25, count 0 2006.175.08:15:11.90#ibcon#enter sib2, iclass 25, count 0 2006.175.08:15:11.90#ibcon#flushed, iclass 25, count 0 2006.175.08:15:11.90#ibcon#about to write, iclass 25, count 0 2006.175.08:15:11.90#ibcon#wrote, iclass 25, count 0 2006.175.08:15:11.90#ibcon#about to read 3, iclass 25, count 0 2006.175.08:15:11.92#ibcon#read 3, iclass 25, count 0 2006.175.08:15:11.92#ibcon#about to read 4, iclass 25, count 0 2006.175.08:15:11.92#ibcon#read 4, iclass 25, count 0 2006.175.08:15:11.92#ibcon#about to read 5, iclass 25, count 0 2006.175.08:15:11.92#ibcon#read 5, iclass 25, count 0 2006.175.08:15:11.92#ibcon#about to read 6, iclass 25, count 0 2006.175.08:15:11.92#ibcon#read 6, iclass 25, count 0 2006.175.08:15:11.92#ibcon#end of sib2, iclass 25, count 0 2006.175.08:15:11.92#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:15:11.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:15:11.92#ibcon#[27=USB\r\n] 2006.175.08:15:11.92#ibcon#*before write, iclass 25, count 0 2006.175.08:15:11.92#ibcon#enter sib2, iclass 25, count 0 2006.175.08:15:11.92#ibcon#flushed, iclass 25, count 0 2006.175.08:15:11.92#ibcon#about to write, iclass 25, count 0 2006.175.08:15:11.92#ibcon#wrote, iclass 25, count 0 2006.175.08:15:11.92#ibcon#about to read 3, iclass 25, count 0 2006.175.08:15:11.95#ibcon#read 3, iclass 25, count 0 2006.175.08:15:11.95#ibcon#about to read 4, iclass 25, count 0 2006.175.08:15:11.95#ibcon#read 4, iclass 25, count 0 2006.175.08:15:11.95#ibcon#about to read 5, iclass 25, count 0 2006.175.08:15:11.95#ibcon#read 5, iclass 25, count 0 2006.175.08:15:11.95#ibcon#about to read 6, iclass 25, count 0 2006.175.08:15:11.95#ibcon#read 6, iclass 25, count 0 2006.175.08:15:11.95#ibcon#end of sib2, iclass 25, count 0 2006.175.08:15:11.95#ibcon#*after write, iclass 25, count 0 2006.175.08:15:11.95#ibcon#*before return 0, iclass 25, count 0 2006.175.08:15:11.95#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:11.95#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:15:11.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:15:11.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:15:11.95$vc4f8/vblo=5,744.99 2006.175.08:15:11.95#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.08:15:11.95#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.08:15:11.95#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:11.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:11.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:11.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:11.95#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:15:11.95#ibcon#first serial, iclass 27, count 0 2006.175.08:15:11.95#ibcon#enter sib2, iclass 27, count 0 2006.175.08:15:11.95#ibcon#flushed, iclass 27, count 0 2006.175.08:15:11.95#ibcon#about to write, iclass 27, count 0 2006.175.08:15:11.95#ibcon#wrote, iclass 27, count 0 2006.175.08:15:11.95#ibcon#about to read 3, iclass 27, count 0 2006.175.08:15:11.97#ibcon#read 3, iclass 27, count 0 2006.175.08:15:11.97#ibcon#about to read 4, iclass 27, count 0 2006.175.08:15:11.97#ibcon#read 4, iclass 27, count 0 2006.175.08:15:11.97#ibcon#about to read 5, iclass 27, count 0 2006.175.08:15:11.97#ibcon#read 5, iclass 27, count 0 2006.175.08:15:11.97#ibcon#about to read 6, iclass 27, count 0 2006.175.08:15:11.97#ibcon#read 6, iclass 27, count 0 2006.175.08:15:11.97#ibcon#end of sib2, iclass 27, count 0 2006.175.08:15:11.97#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:15:11.97#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:15:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:15:11.97#ibcon#*before write, iclass 27, count 0 2006.175.08:15:11.97#ibcon#enter sib2, iclass 27, count 0 2006.175.08:15:11.97#ibcon#flushed, iclass 27, count 0 2006.175.08:15:11.97#ibcon#about to write, iclass 27, count 0 2006.175.08:15:11.97#ibcon#wrote, iclass 27, count 0 2006.175.08:15:11.97#ibcon#about to read 3, iclass 27, count 0 2006.175.08:15:12.01#ibcon#read 3, iclass 27, count 0 2006.175.08:15:12.01#ibcon#about to read 4, iclass 27, count 0 2006.175.08:15:12.01#ibcon#read 4, iclass 27, count 0 2006.175.08:15:12.01#ibcon#about to read 5, iclass 27, count 0 2006.175.08:15:12.01#ibcon#read 5, iclass 27, count 0 2006.175.08:15:12.01#ibcon#about to read 6, iclass 27, count 0 2006.175.08:15:12.01#ibcon#read 6, iclass 27, count 0 2006.175.08:15:12.01#ibcon#end of sib2, iclass 27, count 0 2006.175.08:15:12.01#ibcon#*after write, iclass 27, count 0 2006.175.08:15:12.01#ibcon#*before return 0, iclass 27, count 0 2006.175.08:15:12.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:12.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:15:12.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:15:12.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:15:12.01$vc4f8/vb=5,4 2006.175.08:15:12.01#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.175.08:15:12.01#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.175.08:15:12.01#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:12.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:12.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:12.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:12.07#ibcon#enter wrdev, iclass 29, count 2 2006.175.08:15:12.07#ibcon#first serial, iclass 29, count 2 2006.175.08:15:12.07#ibcon#enter sib2, iclass 29, count 2 2006.175.08:15:12.07#ibcon#flushed, iclass 29, count 2 2006.175.08:15:12.07#ibcon#about to write, iclass 29, count 2 2006.175.08:15:12.07#ibcon#wrote, iclass 29, count 2 2006.175.08:15:12.07#ibcon#about to read 3, iclass 29, count 2 2006.175.08:15:12.09#ibcon#read 3, iclass 29, count 2 2006.175.08:15:12.09#ibcon#about to read 4, iclass 29, count 2 2006.175.08:15:12.09#ibcon#read 4, iclass 29, count 2 2006.175.08:15:12.09#ibcon#about to read 5, iclass 29, count 2 2006.175.08:15:12.09#ibcon#read 5, iclass 29, count 2 2006.175.08:15:12.09#ibcon#about to read 6, iclass 29, count 2 2006.175.08:15:12.09#ibcon#read 6, iclass 29, count 2 2006.175.08:15:12.09#ibcon#end of sib2, iclass 29, count 2 2006.175.08:15:12.09#ibcon#*mode == 0, iclass 29, count 2 2006.175.08:15:12.09#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.175.08:15:12.09#ibcon#[27=AT05-04\r\n] 2006.175.08:15:12.09#ibcon#*before write, iclass 29, count 2 2006.175.08:15:12.09#ibcon#enter sib2, iclass 29, count 2 2006.175.08:15:12.09#ibcon#flushed, iclass 29, count 2 2006.175.08:15:12.09#ibcon#about to write, iclass 29, count 2 2006.175.08:15:12.09#ibcon#wrote, iclass 29, count 2 2006.175.08:15:12.09#ibcon#about to read 3, iclass 29, count 2 2006.175.08:15:12.12#ibcon#read 3, iclass 29, count 2 2006.175.08:15:12.12#ibcon#about to read 4, iclass 29, count 2 2006.175.08:15:12.12#ibcon#read 4, iclass 29, count 2 2006.175.08:15:12.12#ibcon#about to read 5, iclass 29, count 2 2006.175.08:15:12.12#ibcon#read 5, iclass 29, count 2 2006.175.08:15:12.12#ibcon#about to read 6, iclass 29, count 2 2006.175.08:15:12.12#ibcon#read 6, iclass 29, count 2 2006.175.08:15:12.12#ibcon#end of sib2, iclass 29, count 2 2006.175.08:15:12.12#ibcon#*after write, iclass 29, count 2 2006.175.08:15:12.12#ibcon#*before return 0, iclass 29, count 2 2006.175.08:15:12.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:12.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:15:12.12#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.175.08:15:12.12#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:12.12#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:12.24#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:12.24#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:12.24#ibcon#enter wrdev, iclass 29, count 0 2006.175.08:15:12.24#ibcon#first serial, iclass 29, count 0 2006.175.08:15:12.24#ibcon#enter sib2, iclass 29, count 0 2006.175.08:15:12.24#ibcon#flushed, iclass 29, count 0 2006.175.08:15:12.24#ibcon#about to write, iclass 29, count 0 2006.175.08:15:12.24#ibcon#wrote, iclass 29, count 0 2006.175.08:15:12.24#ibcon#about to read 3, iclass 29, count 0 2006.175.08:15:12.26#ibcon#read 3, iclass 29, count 0 2006.175.08:15:12.26#ibcon#about to read 4, iclass 29, count 0 2006.175.08:15:12.26#ibcon#read 4, iclass 29, count 0 2006.175.08:15:12.26#ibcon#about to read 5, iclass 29, count 0 2006.175.08:15:12.26#ibcon#read 5, iclass 29, count 0 2006.175.08:15:12.26#ibcon#about to read 6, iclass 29, count 0 2006.175.08:15:12.26#ibcon#read 6, iclass 29, count 0 2006.175.08:15:12.26#ibcon#end of sib2, iclass 29, count 0 2006.175.08:15:12.26#ibcon#*mode == 0, iclass 29, count 0 2006.175.08:15:12.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.08:15:12.26#ibcon#[27=USB\r\n] 2006.175.08:15:12.26#ibcon#*before write, iclass 29, count 0 2006.175.08:15:12.26#ibcon#enter sib2, iclass 29, count 0 2006.175.08:15:12.26#ibcon#flushed, iclass 29, count 0 2006.175.08:15:12.26#ibcon#about to write, iclass 29, count 0 2006.175.08:15:12.26#ibcon#wrote, iclass 29, count 0 2006.175.08:15:12.26#ibcon#about to read 3, iclass 29, count 0 2006.175.08:15:12.29#ibcon#read 3, iclass 29, count 0 2006.175.08:15:12.29#ibcon#about to read 4, iclass 29, count 0 2006.175.08:15:12.29#ibcon#read 4, iclass 29, count 0 2006.175.08:15:12.29#ibcon#about to read 5, iclass 29, count 0 2006.175.08:15:12.29#ibcon#read 5, iclass 29, count 0 2006.175.08:15:12.29#ibcon#about to read 6, iclass 29, count 0 2006.175.08:15:12.29#ibcon#read 6, iclass 29, count 0 2006.175.08:15:12.29#ibcon#end of sib2, iclass 29, count 0 2006.175.08:15:12.29#ibcon#*after write, iclass 29, count 0 2006.175.08:15:12.29#ibcon#*before return 0, iclass 29, count 0 2006.175.08:15:12.29#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:12.29#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:15:12.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.08:15:12.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.08:15:12.29$vc4f8/vblo=6,752.99 2006.175.08:15:12.29#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.08:15:12.29#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.08:15:12.29#ibcon#ireg 17 cls_cnt 0 2006.175.08:15:12.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:12.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:12.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:12.29#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:15:12.29#ibcon#first serial, iclass 31, count 0 2006.175.08:15:12.29#ibcon#enter sib2, iclass 31, count 0 2006.175.08:15:12.29#ibcon#flushed, iclass 31, count 0 2006.175.08:15:12.29#ibcon#about to write, iclass 31, count 0 2006.175.08:15:12.29#ibcon#wrote, iclass 31, count 0 2006.175.08:15:12.29#ibcon#about to read 3, iclass 31, count 0 2006.175.08:15:12.31#ibcon#read 3, iclass 31, count 0 2006.175.08:15:12.31#ibcon#about to read 4, iclass 31, count 0 2006.175.08:15:12.31#ibcon#read 4, iclass 31, count 0 2006.175.08:15:12.31#ibcon#about to read 5, iclass 31, count 0 2006.175.08:15:12.31#ibcon#read 5, iclass 31, count 0 2006.175.08:15:12.31#ibcon#about to read 6, iclass 31, count 0 2006.175.08:15:12.31#ibcon#read 6, iclass 31, count 0 2006.175.08:15:12.31#ibcon#end of sib2, iclass 31, count 0 2006.175.08:15:12.31#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:15:12.31#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:15:12.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:15:12.31#ibcon#*before write, iclass 31, count 0 2006.175.08:15:12.31#ibcon#enter sib2, iclass 31, count 0 2006.175.08:15:12.31#ibcon#flushed, iclass 31, count 0 2006.175.08:15:12.31#ibcon#about to write, iclass 31, count 0 2006.175.08:15:12.31#ibcon#wrote, iclass 31, count 0 2006.175.08:15:12.31#ibcon#about to read 3, iclass 31, count 0 2006.175.08:15:12.35#ibcon#read 3, iclass 31, count 0 2006.175.08:15:12.35#ibcon#about to read 4, iclass 31, count 0 2006.175.08:15:12.35#ibcon#read 4, iclass 31, count 0 2006.175.08:15:12.35#ibcon#about to read 5, iclass 31, count 0 2006.175.08:15:12.35#ibcon#read 5, iclass 31, count 0 2006.175.08:15:12.35#ibcon#about to read 6, iclass 31, count 0 2006.175.08:15:12.35#ibcon#read 6, iclass 31, count 0 2006.175.08:15:12.35#ibcon#end of sib2, iclass 31, count 0 2006.175.08:15:12.35#ibcon#*after write, iclass 31, count 0 2006.175.08:15:12.35#ibcon#*before return 0, iclass 31, count 0 2006.175.08:15:12.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:12.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:15:12.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:15:12.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:15:12.35$vc4f8/vb=6,4 2006.175.08:15:12.35#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.08:15:12.35#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.08:15:12.35#ibcon#ireg 11 cls_cnt 2 2006.175.08:15:12.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:12.41#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:12.41#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:12.41#ibcon#enter wrdev, iclass 33, count 2 2006.175.08:15:12.41#ibcon#first serial, iclass 33, count 2 2006.175.08:15:12.41#ibcon#enter sib2, iclass 33, count 2 2006.175.08:15:12.41#ibcon#flushed, iclass 33, count 2 2006.175.08:15:12.41#ibcon#about to write, iclass 33, count 2 2006.175.08:15:12.41#ibcon#wrote, iclass 33, count 2 2006.175.08:15:12.41#ibcon#about to read 3, iclass 33, count 2 2006.175.08:15:12.43#ibcon#read 3, iclass 33, count 2 2006.175.08:15:12.43#ibcon#about to read 4, iclass 33, count 2 2006.175.08:15:12.43#ibcon#read 4, iclass 33, count 2 2006.175.08:15:12.43#ibcon#about to read 5, iclass 33, count 2 2006.175.08:15:12.43#ibcon#read 5, iclass 33, count 2 2006.175.08:15:12.43#ibcon#about to read 6, iclass 33, count 2 2006.175.08:15:12.43#ibcon#read 6, iclass 33, count 2 2006.175.08:15:12.43#ibcon#end of sib2, iclass 33, count 2 2006.175.08:15:12.43#ibcon#*mode == 0, iclass 33, count 2 2006.175.08:15:12.43#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.08:15:12.43#ibcon#[27=AT06-04\r\n] 2006.175.08:15:12.43#ibcon#*before write, iclass 33, count 2 2006.175.08:15:12.43#ibcon#enter sib2, iclass 33, count 2 2006.175.08:15:12.43#ibcon#flushed, iclass 33, count 2 2006.175.08:15:12.43#ibcon#about to write, iclass 33, count 2 2006.175.08:15:12.43#ibcon#wrote, iclass 33, count 2 2006.175.08:15:12.43#ibcon#about to read 3, iclass 33, count 2 2006.175.08:15:12.46#ibcon#read 3, iclass 33, count 2 2006.175.08:15:12.46#ibcon#about to read 4, iclass 33, count 2 2006.175.08:15:12.46#ibcon#read 4, iclass 33, count 2 2006.175.08:15:12.46#ibcon#about to read 5, iclass 33, count 2 2006.175.08:15:12.46#ibcon#read 5, iclass 33, count 2 2006.175.08:15:12.46#ibcon#about to read 6, iclass 33, count 2 2006.175.08:15:12.46#ibcon#read 6, iclass 33, count 2 2006.175.08:15:12.46#ibcon#end of sib2, iclass 33, count 2 2006.175.08:15:12.46#ibcon#*after write, iclass 33, count 2 2006.175.08:15:12.46#ibcon#*before return 0, iclass 33, count 2 2006.175.08:15:12.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:12.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:15:12.46#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.08:15:12.46#ibcon#ireg 7 cls_cnt 0 2006.175.08:15:12.46#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:12.58#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:12.58#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:12.58#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:15:12.58#ibcon#first serial, iclass 33, count 0 2006.175.08:15:12.58#ibcon#enter sib2, iclass 33, count 0 2006.175.08:15:12.58#ibcon#flushed, iclass 33, count 0 2006.175.08:15:12.58#ibcon#about to write, iclass 33, count 0 2006.175.08:15:12.58#ibcon#wrote, iclass 33, count 0 2006.175.08:15:12.58#ibcon#about to read 3, iclass 33, count 0 2006.175.08:15:12.60#ibcon#read 3, iclass 33, count 0 2006.175.08:15:12.60#ibcon#about to read 4, iclass 33, count 0 2006.175.08:15:12.60#ibcon#read 4, iclass 33, count 0 2006.175.08:15:12.60#ibcon#about to read 5, iclass 33, count 0 2006.175.08:15:12.60#ibcon#read 5, iclass 33, count 0 2006.175.08:15:12.60#ibcon#about to read 6, iclass 33, count 0 2006.175.08:15:12.60#ibcon#read 6, iclass 33, count 0 2006.175.08:15:12.60#ibcon#end of sib2, iclass 33, count 0 2006.175.08:15:12.60#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:15:12.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:15:12.60#ibcon#[27=USB\r\n] 2006.175.08:15:12.60#ibcon#*before write, iclass 33, count 0 2006.175.08:15:12.60#ibcon#enter sib2, iclass 33, count 0 2006.175.08:15:12.60#ibcon#flushed, iclass 33, count 0 2006.175.08:15:12.60#ibcon#about to write, iclass 33, count 0 2006.175.08:15:12.60#ibcon#wrote, iclass 33, count 0 2006.175.08:15:12.60#ibcon#about to read 3, iclass 33, count 0 2006.175.08:15:12.63#ibcon#read 3, iclass 33, count 0 2006.175.08:15:12.63#ibcon#about to read 4, iclass 33, count 0 2006.175.08:15:12.63#ibcon#read 4, iclass 33, count 0 2006.175.08:15:12.63#ibcon#about to read 5, iclass 33, count 0 2006.175.08:15:12.63#ibcon#read 5, iclass 33, count 0 2006.175.08:15:12.63#ibcon#about to read 6, iclass 33, count 0 2006.175.08:15:12.63#ibcon#read 6, iclass 33, count 0 2006.175.08:15:12.63#ibcon#end of sib2, iclass 33, count 0 2006.175.08:15:12.63#ibcon#*after write, iclass 33, count 0 2006.175.08:15:12.63#ibcon#*before return 0, iclass 33, count 0 2006.175.08:15:12.63#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:12.63#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:15:12.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:15:12.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:15:12.63$vc4f8/vabw=wide 2006.175.08:15:12.63#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.08:15:12.63#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.08:15:12.63#ibcon#ireg 8 cls_cnt 0 2006.175.08:15:12.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:12.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:12.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:12.63#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:15:12.63#ibcon#first serial, iclass 35, count 0 2006.175.08:15:12.63#ibcon#enter sib2, iclass 35, count 0 2006.175.08:15:12.63#ibcon#flushed, iclass 35, count 0 2006.175.08:15:12.63#ibcon#about to write, iclass 35, count 0 2006.175.08:15:12.63#ibcon#wrote, iclass 35, count 0 2006.175.08:15:12.63#ibcon#about to read 3, iclass 35, count 0 2006.175.08:15:12.65#ibcon#read 3, iclass 35, count 0 2006.175.08:15:12.65#ibcon#about to read 4, iclass 35, count 0 2006.175.08:15:12.65#ibcon#read 4, iclass 35, count 0 2006.175.08:15:12.65#ibcon#about to read 5, iclass 35, count 0 2006.175.08:15:12.65#ibcon#read 5, iclass 35, count 0 2006.175.08:15:12.65#ibcon#about to read 6, iclass 35, count 0 2006.175.08:15:12.65#ibcon#read 6, iclass 35, count 0 2006.175.08:15:12.65#ibcon#end of sib2, iclass 35, count 0 2006.175.08:15:12.65#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:15:12.65#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:15:12.65#ibcon#[25=BW32\r\n] 2006.175.08:15:12.65#ibcon#*before write, iclass 35, count 0 2006.175.08:15:12.65#ibcon#enter sib2, iclass 35, count 0 2006.175.08:15:12.65#ibcon#flushed, iclass 35, count 0 2006.175.08:15:12.65#ibcon#about to write, iclass 35, count 0 2006.175.08:15:12.65#ibcon#wrote, iclass 35, count 0 2006.175.08:15:12.65#ibcon#about to read 3, iclass 35, count 0 2006.175.08:15:12.68#ibcon#read 3, iclass 35, count 0 2006.175.08:15:12.68#ibcon#about to read 4, iclass 35, count 0 2006.175.08:15:12.68#ibcon#read 4, iclass 35, count 0 2006.175.08:15:12.68#ibcon#about to read 5, iclass 35, count 0 2006.175.08:15:12.68#ibcon#read 5, iclass 35, count 0 2006.175.08:15:12.68#ibcon#about to read 6, iclass 35, count 0 2006.175.08:15:12.68#ibcon#read 6, iclass 35, count 0 2006.175.08:15:12.68#ibcon#end of sib2, iclass 35, count 0 2006.175.08:15:12.68#ibcon#*after write, iclass 35, count 0 2006.175.08:15:12.68#ibcon#*before return 0, iclass 35, count 0 2006.175.08:15:12.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:12.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:15:12.68#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:15:12.68#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:15:12.68$vc4f8/vbbw=wide 2006.175.08:15:12.68#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.08:15:12.68#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.08:15:12.68#ibcon#ireg 8 cls_cnt 0 2006.175.08:15:12.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:15:12.75#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:15:12.75#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:15:12.75#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:15:12.75#ibcon#first serial, iclass 37, count 0 2006.175.08:15:12.75#ibcon#enter sib2, iclass 37, count 0 2006.175.08:15:12.75#ibcon#flushed, iclass 37, count 0 2006.175.08:15:12.75#ibcon#about to write, iclass 37, count 0 2006.175.08:15:12.75#ibcon#wrote, iclass 37, count 0 2006.175.08:15:12.75#ibcon#about to read 3, iclass 37, count 0 2006.175.08:15:12.77#ibcon#read 3, iclass 37, count 0 2006.175.08:15:12.77#ibcon#about to read 4, iclass 37, count 0 2006.175.08:15:12.77#ibcon#read 4, iclass 37, count 0 2006.175.08:15:12.77#ibcon#about to read 5, iclass 37, count 0 2006.175.08:15:12.77#ibcon#read 5, iclass 37, count 0 2006.175.08:15:12.77#ibcon#about to read 6, iclass 37, count 0 2006.175.08:15:12.77#ibcon#read 6, iclass 37, count 0 2006.175.08:15:12.77#ibcon#end of sib2, iclass 37, count 0 2006.175.08:15:12.77#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:15:12.77#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:15:12.77#ibcon#[27=BW32\r\n] 2006.175.08:15:12.77#ibcon#*before write, iclass 37, count 0 2006.175.08:15:12.77#ibcon#enter sib2, iclass 37, count 0 2006.175.08:15:12.77#ibcon#flushed, iclass 37, count 0 2006.175.08:15:12.77#ibcon#about to write, iclass 37, count 0 2006.175.08:15:12.77#ibcon#wrote, iclass 37, count 0 2006.175.08:15:12.77#ibcon#about to read 3, iclass 37, count 0 2006.175.08:15:12.80#ibcon#read 3, iclass 37, count 0 2006.175.08:15:12.80#ibcon#about to read 4, iclass 37, count 0 2006.175.08:15:12.80#ibcon#read 4, iclass 37, count 0 2006.175.08:15:12.80#ibcon#about to read 5, iclass 37, count 0 2006.175.08:15:12.80#ibcon#read 5, iclass 37, count 0 2006.175.08:15:12.80#ibcon#about to read 6, iclass 37, count 0 2006.175.08:15:12.80#ibcon#read 6, iclass 37, count 0 2006.175.08:15:12.80#ibcon#end of sib2, iclass 37, count 0 2006.175.08:15:12.80#ibcon#*after write, iclass 37, count 0 2006.175.08:15:12.80#ibcon#*before return 0, iclass 37, count 0 2006.175.08:15:12.80#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:15:12.80#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:15:12.80#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:15:12.80#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:15:12.80$4f8m12a/ifd4f 2006.175.08:15:12.80$ifd4f/lo= 2006.175.08:15:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:15:12.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:15:12.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:15:12.80$ifd4f/patch= 2006.175.08:15:12.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:15:12.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:15:12.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:15:12.80$4f8m12a/"form=m,16.000,1:2 2006.175.08:15:12.80$4f8m12a/"tpicd 2006.175.08:15:12.80$4f8m12a/echo=off 2006.175.08:15:12.80$4f8m12a/xlog=off 2006.175.08:15:12.80:!2006.175.08:15:40 2006.175.08:15:20.13#trakl#Source acquired 2006.175.08:15:22.13#flagr#flagr/antenna,acquired 2006.175.08:15:40.00:preob 2006.175.08:15:41.13/onsource/TRACKING 2006.175.08:15:41.13:!2006.175.08:15:50 2006.175.08:15:50.00:data_valid=on 2006.175.08:15:50.00:midob 2006.175.08:15:50.13/onsource/TRACKING 2006.175.08:15:50.13/wx/25.74,1007.4,71 2006.175.08:15:50.21/cable/+6.4779E-03 2006.175.08:15:51.30/va/01,08,usb,yes,29,30 2006.175.08:15:51.30/va/02,07,usb,yes,29,30 2006.175.08:15:51.30/va/03,06,usb,yes,30,31 2006.175.08:15:51.30/va/04,07,usb,yes,30,32 2006.175.08:15:51.30/va/05,07,usb,yes,30,32 2006.175.08:15:51.30/va/06,06,usb,yes,29,29 2006.175.08:15:51.30/va/07,06,usb,yes,30,29 2006.175.08:15:51.30/va/08,06,usb,yes,32,31 2006.175.08:15:51.53/valo/01,532.99,yes,locked 2006.175.08:15:51.53/valo/02,572.99,yes,locked 2006.175.08:15:51.53/valo/03,672.99,yes,locked 2006.175.08:15:51.53/valo/04,832.99,yes,locked 2006.175.08:15:51.53/valo/05,652.99,yes,locked 2006.175.08:15:51.53/valo/06,772.99,yes,locked 2006.175.08:15:51.53/valo/07,832.99,yes,locked 2006.175.08:15:51.53/valo/08,852.99,yes,locked 2006.175.08:15:52.62/vb/01,04,usb,yes,29,27 2006.175.08:15:52.62/vb/02,04,usb,yes,30,32 2006.175.08:15:52.62/vb/03,04,usb,yes,27,30 2006.175.08:15:52.62/vb/04,04,usb,yes,28,28 2006.175.08:15:52.62/vb/05,04,usb,yes,26,30 2006.175.08:15:52.62/vb/06,04,usb,yes,27,30 2006.175.08:15:52.62/vb/07,04,usb,yes,29,29 2006.175.08:15:52.62/vb/08,04,usb,yes,27,30 2006.175.08:15:52.85/vblo/01,632.99,yes,locked 2006.175.08:15:52.85/vblo/02,640.99,yes,locked 2006.175.08:15:52.85/vblo/03,656.99,yes,locked 2006.175.08:15:52.85/vblo/04,712.99,yes,locked 2006.175.08:15:52.85/vblo/05,744.99,yes,locked 2006.175.08:15:52.85/vblo/06,752.99,yes,locked 2006.175.08:15:52.85/vblo/07,734.99,yes,locked 2006.175.08:15:52.85/vblo/08,744.99,yes,locked 2006.175.08:15:53.00/vabw/8 2006.175.08:15:53.15/vbbw/8 2006.175.08:15:53.24/xfe/off,on,15.0 2006.175.08:15:53.63/ifatt/23,28,28,28 2006.175.08:15:54.07/fmout-gps/S +3.80E-07 2006.175.08:15:54.15:!2006.175.08:16:50 2006.175.08:16:50.00:data_valid=off 2006.175.08:16:50.00:postob 2006.175.08:16:50.17/cable/+6.4783E-03 2006.175.08:16:50.21/wx/25.73,1007.4,71 2006.175.08:16:51.08/fmout-gps/S +3.80E-07 2006.175.08:16:51.08:scan_name=175-0817,k06175,60 2006.175.08:16:51.09:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.175.08:16:51.13#flagr#flagr/antenna,new-source 2006.175.08:16:52.13:checkk5 2006.175.08:16:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:16:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:16:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:16:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:16:54.03/chk_obsdata//k5ts1/T1750815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:16:54.40/chk_obsdata//k5ts2/T1750815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:16:54.77/chk_obsdata//k5ts3/T1750815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:16:55.15/chk_obsdata//k5ts4/T1750815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:16:55.86/k5log//k5ts1_log_newline 2006.175.08:16:56.56/k5log//k5ts2_log_newline 2006.175.08:16:57.26/k5log//k5ts3_log_newline 2006.175.08:16:57.97/k5log//k5ts4_log_newline 2006.175.08:16:57.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:16:57.99:4f8m12a=2 2006.175.08:16:57.99$4f8m12a/echo=on 2006.175.08:16:57.99$4f8m12a/pcalon 2006.175.08:16:57.99$pcalon/"no phase cal control is implemented here 2006.175.08:16:57.99$4f8m12a/"tpicd=stop 2006.175.08:16:57.99$4f8m12a/vc4f8 2006.175.08:16:57.99$vc4f8/valo=1,532.99 2006.175.08:16:58.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.08:16:58.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.08:16:58.00#ibcon#ireg 17 cls_cnt 0 2006.175.08:16:58.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:16:58.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:16:58.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:16:58.00#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:16:58.00#ibcon#first serial, iclass 12, count 0 2006.175.08:16:58.00#ibcon#enter sib2, iclass 12, count 0 2006.175.08:16:58.00#ibcon#flushed, iclass 12, count 0 2006.175.08:16:58.00#ibcon#about to write, iclass 12, count 0 2006.175.08:16:58.00#ibcon#wrote, iclass 12, count 0 2006.175.08:16:58.00#ibcon#about to read 3, iclass 12, count 0 2006.175.08:16:58.04#ibcon#read 3, iclass 12, count 0 2006.175.08:16:58.04#ibcon#about to read 4, iclass 12, count 0 2006.175.08:16:58.04#ibcon#read 4, iclass 12, count 0 2006.175.08:16:58.04#ibcon#about to read 5, iclass 12, count 0 2006.175.08:16:58.04#ibcon#read 5, iclass 12, count 0 2006.175.08:16:58.04#ibcon#about to read 6, iclass 12, count 0 2006.175.08:16:58.04#ibcon#read 6, iclass 12, count 0 2006.175.08:16:58.04#ibcon#end of sib2, iclass 12, count 0 2006.175.08:16:58.04#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:16:58.04#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:16:58.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:16:58.04#ibcon#*before write, iclass 12, count 0 2006.175.08:16:58.04#ibcon#enter sib2, iclass 12, count 0 2006.175.08:16:58.04#ibcon#flushed, iclass 12, count 0 2006.175.08:16:58.04#ibcon#about to write, iclass 12, count 0 2006.175.08:16:58.04#ibcon#wrote, iclass 12, count 0 2006.175.08:16:58.04#ibcon#about to read 3, iclass 12, count 0 2006.175.08:16:58.09#ibcon#read 3, iclass 12, count 0 2006.175.08:16:58.09#ibcon#about to read 4, iclass 12, count 0 2006.175.08:16:58.09#ibcon#read 4, iclass 12, count 0 2006.175.08:16:58.09#ibcon#about to read 5, iclass 12, count 0 2006.175.08:16:58.09#ibcon#read 5, iclass 12, count 0 2006.175.08:16:58.09#ibcon#about to read 6, iclass 12, count 0 2006.175.08:16:58.09#ibcon#read 6, iclass 12, count 0 2006.175.08:16:58.09#ibcon#end of sib2, iclass 12, count 0 2006.175.08:16:58.09#ibcon#*after write, iclass 12, count 0 2006.175.08:16:58.09#ibcon#*before return 0, iclass 12, count 0 2006.175.08:16:58.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:16:58.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:16:58.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:16:58.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:16:58.09$vc4f8/va=1,8 2006.175.08:16:58.09#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.08:16:58.09#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.08:16:58.09#ibcon#ireg 11 cls_cnt 2 2006.175.08:16:58.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:16:58.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:16:58.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:16:58.09#ibcon#enter wrdev, iclass 14, count 2 2006.175.08:16:58.09#ibcon#first serial, iclass 14, count 2 2006.175.08:16:58.09#ibcon#enter sib2, iclass 14, count 2 2006.175.08:16:58.09#ibcon#flushed, iclass 14, count 2 2006.175.08:16:58.09#ibcon#about to write, iclass 14, count 2 2006.175.08:16:58.09#ibcon#wrote, iclass 14, count 2 2006.175.08:16:58.09#ibcon#about to read 3, iclass 14, count 2 2006.175.08:16:58.11#ibcon#read 3, iclass 14, count 2 2006.175.08:16:58.11#ibcon#about to read 4, iclass 14, count 2 2006.175.08:16:58.11#ibcon#read 4, iclass 14, count 2 2006.175.08:16:58.11#ibcon#about to read 5, iclass 14, count 2 2006.175.08:16:58.11#ibcon#read 5, iclass 14, count 2 2006.175.08:16:58.11#ibcon#about to read 6, iclass 14, count 2 2006.175.08:16:58.11#ibcon#read 6, iclass 14, count 2 2006.175.08:16:58.11#ibcon#end of sib2, iclass 14, count 2 2006.175.08:16:58.11#ibcon#*mode == 0, iclass 14, count 2 2006.175.08:16:58.11#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.08:16:58.11#ibcon#[25=AT01-08\r\n] 2006.175.08:16:58.11#ibcon#*before write, iclass 14, count 2 2006.175.08:16:58.11#ibcon#enter sib2, iclass 14, count 2 2006.175.08:16:58.11#ibcon#flushed, iclass 14, count 2 2006.175.08:16:58.11#ibcon#about to write, iclass 14, count 2 2006.175.08:16:58.11#ibcon#wrote, iclass 14, count 2 2006.175.08:16:58.11#ibcon#about to read 3, iclass 14, count 2 2006.175.08:16:58.14#ibcon#read 3, iclass 14, count 2 2006.175.08:16:58.14#ibcon#about to read 4, iclass 14, count 2 2006.175.08:16:58.14#ibcon#read 4, iclass 14, count 2 2006.175.08:16:58.14#ibcon#about to read 5, iclass 14, count 2 2006.175.08:16:58.14#ibcon#read 5, iclass 14, count 2 2006.175.08:16:58.14#ibcon#about to read 6, iclass 14, count 2 2006.175.08:16:58.14#ibcon#read 6, iclass 14, count 2 2006.175.08:16:58.14#ibcon#end of sib2, iclass 14, count 2 2006.175.08:16:58.14#ibcon#*after write, iclass 14, count 2 2006.175.08:16:58.14#ibcon#*before return 0, iclass 14, count 2 2006.175.08:16:58.14#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:16:58.14#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:16:58.14#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.08:16:58.14#ibcon#ireg 7 cls_cnt 0 2006.175.08:16:58.14#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:16:58.26#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:16:58.26#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:16:58.26#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:16:58.26#ibcon#first serial, iclass 14, count 0 2006.175.08:16:58.26#ibcon#enter sib2, iclass 14, count 0 2006.175.08:16:58.26#ibcon#flushed, iclass 14, count 0 2006.175.08:16:58.26#ibcon#about to write, iclass 14, count 0 2006.175.08:16:58.26#ibcon#wrote, iclass 14, count 0 2006.175.08:16:58.26#ibcon#about to read 3, iclass 14, count 0 2006.175.08:16:58.28#ibcon#read 3, iclass 14, count 0 2006.175.08:16:58.28#ibcon#about to read 4, iclass 14, count 0 2006.175.08:16:58.28#ibcon#read 4, iclass 14, count 0 2006.175.08:16:58.28#ibcon#about to read 5, iclass 14, count 0 2006.175.08:16:58.28#ibcon#read 5, iclass 14, count 0 2006.175.08:16:58.28#ibcon#about to read 6, iclass 14, count 0 2006.175.08:16:58.28#ibcon#read 6, iclass 14, count 0 2006.175.08:16:58.28#ibcon#end of sib2, iclass 14, count 0 2006.175.08:16:58.28#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:16:58.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:16:58.28#ibcon#[25=USB\r\n] 2006.175.08:16:58.28#ibcon#*before write, iclass 14, count 0 2006.175.08:16:58.28#ibcon#enter sib2, iclass 14, count 0 2006.175.08:16:58.28#ibcon#flushed, iclass 14, count 0 2006.175.08:16:58.28#ibcon#about to write, iclass 14, count 0 2006.175.08:16:58.28#ibcon#wrote, iclass 14, count 0 2006.175.08:16:58.28#ibcon#about to read 3, iclass 14, count 0 2006.175.08:16:58.31#ibcon#read 3, iclass 14, count 0 2006.175.08:16:58.31#ibcon#about to read 4, iclass 14, count 0 2006.175.08:16:58.31#ibcon#read 4, iclass 14, count 0 2006.175.08:16:58.31#ibcon#about to read 5, iclass 14, count 0 2006.175.08:16:58.31#ibcon#read 5, iclass 14, count 0 2006.175.08:16:58.31#ibcon#about to read 6, iclass 14, count 0 2006.175.08:16:58.31#ibcon#read 6, iclass 14, count 0 2006.175.08:16:58.31#ibcon#end of sib2, iclass 14, count 0 2006.175.08:16:58.31#ibcon#*after write, iclass 14, count 0 2006.175.08:16:58.31#ibcon#*before return 0, iclass 14, count 0 2006.175.08:16:58.31#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:16:58.31#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:16:58.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:16:58.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:16:58.31$vc4f8/valo=2,572.99 2006.175.08:16:58.31#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.08:16:58.31#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.08:16:58.31#ibcon#ireg 17 cls_cnt 0 2006.175.08:16:58.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:16:58.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:16:58.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:16:58.31#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:16:58.31#ibcon#first serial, iclass 16, count 0 2006.175.08:16:58.31#ibcon#enter sib2, iclass 16, count 0 2006.175.08:16:58.31#ibcon#flushed, iclass 16, count 0 2006.175.08:16:58.31#ibcon#about to write, iclass 16, count 0 2006.175.08:16:58.31#ibcon#wrote, iclass 16, count 0 2006.175.08:16:58.31#ibcon#about to read 3, iclass 16, count 0 2006.175.08:16:58.33#ibcon#read 3, iclass 16, count 0 2006.175.08:16:58.33#ibcon#about to read 4, iclass 16, count 0 2006.175.08:16:58.33#ibcon#read 4, iclass 16, count 0 2006.175.08:16:58.33#ibcon#about to read 5, iclass 16, count 0 2006.175.08:16:58.33#ibcon#read 5, iclass 16, count 0 2006.175.08:16:58.33#ibcon#about to read 6, iclass 16, count 0 2006.175.08:16:58.33#ibcon#read 6, iclass 16, count 0 2006.175.08:16:58.33#ibcon#end of sib2, iclass 16, count 0 2006.175.08:16:58.33#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:16:58.33#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:16:58.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:16:58.33#ibcon#*before write, iclass 16, count 0 2006.175.08:16:58.33#ibcon#enter sib2, iclass 16, count 0 2006.175.08:16:58.33#ibcon#flushed, iclass 16, count 0 2006.175.08:16:58.33#ibcon#about to write, iclass 16, count 0 2006.175.08:16:58.33#ibcon#wrote, iclass 16, count 0 2006.175.08:16:58.33#ibcon#about to read 3, iclass 16, count 0 2006.175.08:16:58.37#ibcon#read 3, iclass 16, count 0 2006.175.08:16:58.37#ibcon#about to read 4, iclass 16, count 0 2006.175.08:16:58.37#ibcon#read 4, iclass 16, count 0 2006.175.08:16:58.37#ibcon#about to read 5, iclass 16, count 0 2006.175.08:16:58.37#ibcon#read 5, iclass 16, count 0 2006.175.08:16:58.37#ibcon#about to read 6, iclass 16, count 0 2006.175.08:16:58.37#ibcon#read 6, iclass 16, count 0 2006.175.08:16:58.37#ibcon#end of sib2, iclass 16, count 0 2006.175.08:16:58.37#ibcon#*after write, iclass 16, count 0 2006.175.08:16:58.37#ibcon#*before return 0, iclass 16, count 0 2006.175.08:16:58.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:16:58.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:16:58.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:16:58.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:16:58.37$vc4f8/va=2,7 2006.175.08:16:58.37#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.08:16:58.37#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.08:16:58.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:16:58.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:16:58.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:16:58.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:16:58.43#ibcon#enter wrdev, iclass 18, count 2 2006.175.08:16:58.43#ibcon#first serial, iclass 18, count 2 2006.175.08:16:58.43#ibcon#enter sib2, iclass 18, count 2 2006.175.08:16:58.43#ibcon#flushed, iclass 18, count 2 2006.175.08:16:58.43#ibcon#about to write, iclass 18, count 2 2006.175.08:16:58.43#ibcon#wrote, iclass 18, count 2 2006.175.08:16:58.43#ibcon#about to read 3, iclass 18, count 2 2006.175.08:16:58.45#ibcon#read 3, iclass 18, count 2 2006.175.08:16:58.45#ibcon#about to read 4, iclass 18, count 2 2006.175.08:16:58.45#ibcon#read 4, iclass 18, count 2 2006.175.08:16:58.45#ibcon#about to read 5, iclass 18, count 2 2006.175.08:16:58.45#ibcon#read 5, iclass 18, count 2 2006.175.08:16:58.45#ibcon#about to read 6, iclass 18, count 2 2006.175.08:16:58.45#ibcon#read 6, iclass 18, count 2 2006.175.08:16:58.45#ibcon#end of sib2, iclass 18, count 2 2006.175.08:16:58.45#ibcon#*mode == 0, iclass 18, count 2 2006.175.08:16:58.45#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.08:16:58.45#ibcon#[25=AT02-07\r\n] 2006.175.08:16:58.45#ibcon#*before write, iclass 18, count 2 2006.175.08:16:58.45#ibcon#enter sib2, iclass 18, count 2 2006.175.08:16:58.45#ibcon#flushed, iclass 18, count 2 2006.175.08:16:58.45#ibcon#about to write, iclass 18, count 2 2006.175.08:16:58.45#ibcon#wrote, iclass 18, count 2 2006.175.08:16:58.45#ibcon#about to read 3, iclass 18, count 2 2006.175.08:16:58.48#ibcon#read 3, iclass 18, count 2 2006.175.08:16:58.48#ibcon#about to read 4, iclass 18, count 2 2006.175.08:16:58.48#ibcon#read 4, iclass 18, count 2 2006.175.08:16:58.48#ibcon#about to read 5, iclass 18, count 2 2006.175.08:16:58.48#ibcon#read 5, iclass 18, count 2 2006.175.08:16:58.48#ibcon#about to read 6, iclass 18, count 2 2006.175.08:16:58.48#ibcon#read 6, iclass 18, count 2 2006.175.08:16:58.48#ibcon#end of sib2, iclass 18, count 2 2006.175.08:16:58.48#ibcon#*after write, iclass 18, count 2 2006.175.08:16:58.48#ibcon#*before return 0, iclass 18, count 2 2006.175.08:16:58.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:16:58.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:16:58.48#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.08:16:58.48#ibcon#ireg 7 cls_cnt 0 2006.175.08:16:58.48#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:16:58.60#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:16:58.60#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:16:58.60#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:16:58.60#ibcon#first serial, iclass 18, count 0 2006.175.08:16:58.60#ibcon#enter sib2, iclass 18, count 0 2006.175.08:16:58.60#ibcon#flushed, iclass 18, count 0 2006.175.08:16:58.60#ibcon#about to write, iclass 18, count 0 2006.175.08:16:58.60#ibcon#wrote, iclass 18, count 0 2006.175.08:16:58.60#ibcon#about to read 3, iclass 18, count 0 2006.175.08:16:58.62#ibcon#read 3, iclass 18, count 0 2006.175.08:16:58.62#ibcon#about to read 4, iclass 18, count 0 2006.175.08:16:58.62#ibcon#read 4, iclass 18, count 0 2006.175.08:16:58.62#ibcon#about to read 5, iclass 18, count 0 2006.175.08:16:58.62#ibcon#read 5, iclass 18, count 0 2006.175.08:16:58.62#ibcon#about to read 6, iclass 18, count 0 2006.175.08:16:58.62#ibcon#read 6, iclass 18, count 0 2006.175.08:16:58.62#ibcon#end of sib2, iclass 18, count 0 2006.175.08:16:58.62#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:16:58.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:16:58.62#ibcon#[25=USB\r\n] 2006.175.08:16:58.62#ibcon#*before write, iclass 18, count 0 2006.175.08:16:58.62#ibcon#enter sib2, iclass 18, count 0 2006.175.08:16:58.62#ibcon#flushed, iclass 18, count 0 2006.175.08:16:58.62#ibcon#about to write, iclass 18, count 0 2006.175.08:16:58.62#ibcon#wrote, iclass 18, count 0 2006.175.08:16:58.62#ibcon#about to read 3, iclass 18, count 0 2006.175.08:16:58.65#ibcon#read 3, iclass 18, count 0 2006.175.08:16:58.65#ibcon#about to read 4, iclass 18, count 0 2006.175.08:16:58.65#ibcon#read 4, iclass 18, count 0 2006.175.08:16:58.65#ibcon#about to read 5, iclass 18, count 0 2006.175.08:16:58.65#ibcon#read 5, iclass 18, count 0 2006.175.08:16:58.65#ibcon#about to read 6, iclass 18, count 0 2006.175.08:16:58.65#ibcon#read 6, iclass 18, count 0 2006.175.08:16:58.65#ibcon#end of sib2, iclass 18, count 0 2006.175.08:16:58.65#ibcon#*after write, iclass 18, count 0 2006.175.08:16:58.65#ibcon#*before return 0, iclass 18, count 0 2006.175.08:16:58.65#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:16:58.65#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:16:58.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:16:58.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:16:58.65$vc4f8/valo=3,672.99 2006.175.08:16:58.65#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.08:16:58.65#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.08:16:58.65#ibcon#ireg 17 cls_cnt 0 2006.175.08:16:58.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:16:58.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:16:58.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:16:58.65#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:16:58.65#ibcon#first serial, iclass 20, count 0 2006.175.08:16:58.65#ibcon#enter sib2, iclass 20, count 0 2006.175.08:16:58.65#ibcon#flushed, iclass 20, count 0 2006.175.08:16:58.65#ibcon#about to write, iclass 20, count 0 2006.175.08:16:58.65#ibcon#wrote, iclass 20, count 0 2006.175.08:16:58.65#ibcon#about to read 3, iclass 20, count 0 2006.175.08:16:58.67#ibcon#read 3, iclass 20, count 0 2006.175.08:16:58.67#ibcon#about to read 4, iclass 20, count 0 2006.175.08:16:58.67#ibcon#read 4, iclass 20, count 0 2006.175.08:16:58.67#ibcon#about to read 5, iclass 20, count 0 2006.175.08:16:58.67#ibcon#read 5, iclass 20, count 0 2006.175.08:16:58.67#ibcon#about to read 6, iclass 20, count 0 2006.175.08:16:58.67#ibcon#read 6, iclass 20, count 0 2006.175.08:16:58.67#ibcon#end of sib2, iclass 20, count 0 2006.175.08:16:58.67#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:16:58.67#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:16:58.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:16:58.67#ibcon#*before write, iclass 20, count 0 2006.175.08:16:58.67#ibcon#enter sib2, iclass 20, count 0 2006.175.08:16:58.67#ibcon#flushed, iclass 20, count 0 2006.175.08:16:58.67#ibcon#about to write, iclass 20, count 0 2006.175.08:16:58.67#ibcon#wrote, iclass 20, count 0 2006.175.08:16:58.67#ibcon#about to read 3, iclass 20, count 0 2006.175.08:16:58.71#ibcon#read 3, iclass 20, count 0 2006.175.08:16:58.71#ibcon#about to read 4, iclass 20, count 0 2006.175.08:16:58.71#ibcon#read 4, iclass 20, count 0 2006.175.08:16:58.71#ibcon#about to read 5, iclass 20, count 0 2006.175.08:16:58.71#ibcon#read 5, iclass 20, count 0 2006.175.08:16:58.71#ibcon#about to read 6, iclass 20, count 0 2006.175.08:16:58.71#ibcon#read 6, iclass 20, count 0 2006.175.08:16:58.71#ibcon#end of sib2, iclass 20, count 0 2006.175.08:16:58.71#ibcon#*after write, iclass 20, count 0 2006.175.08:16:58.71#ibcon#*before return 0, iclass 20, count 0 2006.175.08:16:58.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:16:58.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:16:58.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:16:58.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:16:58.71$vc4f8/va=3,6 2006.175.08:16:58.71#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.08:16:58.71#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.08:16:58.71#ibcon#ireg 11 cls_cnt 2 2006.175.08:16:58.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:16:58.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:16:58.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:16:58.77#ibcon#enter wrdev, iclass 22, count 2 2006.175.08:16:58.77#ibcon#first serial, iclass 22, count 2 2006.175.08:16:58.77#ibcon#enter sib2, iclass 22, count 2 2006.175.08:16:58.77#ibcon#flushed, iclass 22, count 2 2006.175.08:16:58.77#ibcon#about to write, iclass 22, count 2 2006.175.08:16:58.77#ibcon#wrote, iclass 22, count 2 2006.175.08:16:58.77#ibcon#about to read 3, iclass 22, count 2 2006.175.08:16:58.79#ibcon#read 3, iclass 22, count 2 2006.175.08:16:58.79#ibcon#about to read 4, iclass 22, count 2 2006.175.08:16:58.79#ibcon#read 4, iclass 22, count 2 2006.175.08:16:58.79#ibcon#about to read 5, iclass 22, count 2 2006.175.08:16:58.79#ibcon#read 5, iclass 22, count 2 2006.175.08:16:58.79#ibcon#about to read 6, iclass 22, count 2 2006.175.08:16:58.79#ibcon#read 6, iclass 22, count 2 2006.175.08:16:58.79#ibcon#end of sib2, iclass 22, count 2 2006.175.08:16:58.79#ibcon#*mode == 0, iclass 22, count 2 2006.175.08:16:58.79#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.08:16:58.79#ibcon#[25=AT03-06\r\n] 2006.175.08:16:58.79#ibcon#*before write, iclass 22, count 2 2006.175.08:16:58.79#ibcon#enter sib2, iclass 22, count 2 2006.175.08:16:58.79#ibcon#flushed, iclass 22, count 2 2006.175.08:16:58.79#ibcon#about to write, iclass 22, count 2 2006.175.08:16:58.79#ibcon#wrote, iclass 22, count 2 2006.175.08:16:58.79#ibcon#about to read 3, iclass 22, count 2 2006.175.08:16:58.82#ibcon#read 3, iclass 22, count 2 2006.175.08:16:58.82#ibcon#about to read 4, iclass 22, count 2 2006.175.08:16:58.82#ibcon#read 4, iclass 22, count 2 2006.175.08:16:58.82#ibcon#about to read 5, iclass 22, count 2 2006.175.08:16:58.82#ibcon#read 5, iclass 22, count 2 2006.175.08:16:58.82#ibcon#about to read 6, iclass 22, count 2 2006.175.08:16:58.82#ibcon#read 6, iclass 22, count 2 2006.175.08:16:58.82#ibcon#end of sib2, iclass 22, count 2 2006.175.08:16:58.82#ibcon#*after write, iclass 22, count 2 2006.175.08:16:58.82#ibcon#*before return 0, iclass 22, count 2 2006.175.08:16:58.82#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:16:58.82#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:16:58.82#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.08:16:58.82#ibcon#ireg 7 cls_cnt 0 2006.175.08:16:58.82#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:16:58.94#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:16:58.94#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:16:58.94#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:16:58.94#ibcon#first serial, iclass 22, count 0 2006.175.08:16:58.94#ibcon#enter sib2, iclass 22, count 0 2006.175.08:16:58.94#ibcon#flushed, iclass 22, count 0 2006.175.08:16:58.94#ibcon#about to write, iclass 22, count 0 2006.175.08:16:58.94#ibcon#wrote, iclass 22, count 0 2006.175.08:16:58.94#ibcon#about to read 3, iclass 22, count 0 2006.175.08:16:58.96#ibcon#read 3, iclass 22, count 0 2006.175.08:16:58.96#ibcon#about to read 4, iclass 22, count 0 2006.175.08:16:58.96#ibcon#read 4, iclass 22, count 0 2006.175.08:16:58.96#ibcon#about to read 5, iclass 22, count 0 2006.175.08:16:58.96#ibcon#read 5, iclass 22, count 0 2006.175.08:16:58.96#ibcon#about to read 6, iclass 22, count 0 2006.175.08:16:58.96#ibcon#read 6, iclass 22, count 0 2006.175.08:16:58.96#ibcon#end of sib2, iclass 22, count 0 2006.175.08:16:58.96#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:16:58.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:16:58.96#ibcon#[25=USB\r\n] 2006.175.08:16:58.96#ibcon#*before write, iclass 22, count 0 2006.175.08:16:58.96#ibcon#enter sib2, iclass 22, count 0 2006.175.08:16:58.96#ibcon#flushed, iclass 22, count 0 2006.175.08:16:58.96#ibcon#about to write, iclass 22, count 0 2006.175.08:16:58.96#ibcon#wrote, iclass 22, count 0 2006.175.08:16:58.96#ibcon#about to read 3, iclass 22, count 0 2006.175.08:16:58.99#ibcon#read 3, iclass 22, count 0 2006.175.08:16:58.99#ibcon#about to read 4, iclass 22, count 0 2006.175.08:16:58.99#ibcon#read 4, iclass 22, count 0 2006.175.08:16:58.99#ibcon#about to read 5, iclass 22, count 0 2006.175.08:16:58.99#ibcon#read 5, iclass 22, count 0 2006.175.08:16:58.99#ibcon#about to read 6, iclass 22, count 0 2006.175.08:16:58.99#ibcon#read 6, iclass 22, count 0 2006.175.08:16:58.99#ibcon#end of sib2, iclass 22, count 0 2006.175.08:16:58.99#ibcon#*after write, iclass 22, count 0 2006.175.08:16:58.99#ibcon#*before return 0, iclass 22, count 0 2006.175.08:16:58.99#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:16:58.99#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:16:58.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:16:58.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:16:58.99$vc4f8/valo=4,832.99 2006.175.08:16:58.99#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.08:16:58.99#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.08:16:58.99#ibcon#ireg 17 cls_cnt 0 2006.175.08:16:58.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:16:58.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:16:58.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:16:58.99#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:16:58.99#ibcon#first serial, iclass 24, count 0 2006.175.08:16:58.99#ibcon#enter sib2, iclass 24, count 0 2006.175.08:16:58.99#ibcon#flushed, iclass 24, count 0 2006.175.08:16:58.99#ibcon#about to write, iclass 24, count 0 2006.175.08:16:58.99#ibcon#wrote, iclass 24, count 0 2006.175.08:16:58.99#ibcon#about to read 3, iclass 24, count 0 2006.175.08:16:59.01#ibcon#read 3, iclass 24, count 0 2006.175.08:16:59.01#ibcon#about to read 4, iclass 24, count 0 2006.175.08:16:59.01#ibcon#read 4, iclass 24, count 0 2006.175.08:16:59.01#ibcon#about to read 5, iclass 24, count 0 2006.175.08:16:59.01#ibcon#read 5, iclass 24, count 0 2006.175.08:16:59.01#ibcon#about to read 6, iclass 24, count 0 2006.175.08:16:59.01#ibcon#read 6, iclass 24, count 0 2006.175.08:16:59.01#ibcon#end of sib2, iclass 24, count 0 2006.175.08:16:59.01#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:16:59.01#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:16:59.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:16:59.01#ibcon#*before write, iclass 24, count 0 2006.175.08:16:59.01#ibcon#enter sib2, iclass 24, count 0 2006.175.08:16:59.01#ibcon#flushed, iclass 24, count 0 2006.175.08:16:59.01#ibcon#about to write, iclass 24, count 0 2006.175.08:16:59.01#ibcon#wrote, iclass 24, count 0 2006.175.08:16:59.01#ibcon#about to read 3, iclass 24, count 0 2006.175.08:16:59.05#ibcon#read 3, iclass 24, count 0 2006.175.08:16:59.05#ibcon#about to read 4, iclass 24, count 0 2006.175.08:16:59.05#ibcon#read 4, iclass 24, count 0 2006.175.08:16:59.05#ibcon#about to read 5, iclass 24, count 0 2006.175.08:16:59.05#ibcon#read 5, iclass 24, count 0 2006.175.08:16:59.05#ibcon#about to read 6, iclass 24, count 0 2006.175.08:16:59.05#ibcon#read 6, iclass 24, count 0 2006.175.08:16:59.05#ibcon#end of sib2, iclass 24, count 0 2006.175.08:16:59.05#ibcon#*after write, iclass 24, count 0 2006.175.08:16:59.05#ibcon#*before return 0, iclass 24, count 0 2006.175.08:16:59.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:16:59.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:16:59.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:16:59.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:16:59.05$vc4f8/va=4,7 2006.175.08:16:59.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.08:16:59.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.08:16:59.05#ibcon#ireg 11 cls_cnt 2 2006.175.08:16:59.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:16:59.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:16:59.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:16:59.11#ibcon#enter wrdev, iclass 26, count 2 2006.175.08:16:59.11#ibcon#first serial, iclass 26, count 2 2006.175.08:16:59.11#ibcon#enter sib2, iclass 26, count 2 2006.175.08:16:59.11#ibcon#flushed, iclass 26, count 2 2006.175.08:16:59.11#ibcon#about to write, iclass 26, count 2 2006.175.08:16:59.11#ibcon#wrote, iclass 26, count 2 2006.175.08:16:59.11#ibcon#about to read 3, iclass 26, count 2 2006.175.08:16:59.13#ibcon#read 3, iclass 26, count 2 2006.175.08:16:59.13#ibcon#about to read 4, iclass 26, count 2 2006.175.08:16:59.13#ibcon#read 4, iclass 26, count 2 2006.175.08:16:59.13#ibcon#about to read 5, iclass 26, count 2 2006.175.08:16:59.13#ibcon#read 5, iclass 26, count 2 2006.175.08:16:59.13#ibcon#about to read 6, iclass 26, count 2 2006.175.08:16:59.13#ibcon#read 6, iclass 26, count 2 2006.175.08:16:59.13#ibcon#end of sib2, iclass 26, count 2 2006.175.08:16:59.13#ibcon#*mode == 0, iclass 26, count 2 2006.175.08:16:59.13#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.08:16:59.13#ibcon#[25=AT04-07\r\n] 2006.175.08:16:59.13#ibcon#*before write, iclass 26, count 2 2006.175.08:16:59.13#ibcon#enter sib2, iclass 26, count 2 2006.175.08:16:59.13#ibcon#flushed, iclass 26, count 2 2006.175.08:16:59.13#ibcon#about to write, iclass 26, count 2 2006.175.08:16:59.13#ibcon#wrote, iclass 26, count 2 2006.175.08:16:59.13#ibcon#about to read 3, iclass 26, count 2 2006.175.08:16:59.16#ibcon#read 3, iclass 26, count 2 2006.175.08:16:59.16#ibcon#about to read 4, iclass 26, count 2 2006.175.08:16:59.16#ibcon#read 4, iclass 26, count 2 2006.175.08:16:59.16#ibcon#about to read 5, iclass 26, count 2 2006.175.08:16:59.16#ibcon#read 5, iclass 26, count 2 2006.175.08:16:59.16#ibcon#about to read 6, iclass 26, count 2 2006.175.08:16:59.16#ibcon#read 6, iclass 26, count 2 2006.175.08:16:59.16#ibcon#end of sib2, iclass 26, count 2 2006.175.08:16:59.16#ibcon#*after write, iclass 26, count 2 2006.175.08:16:59.16#ibcon#*before return 0, iclass 26, count 2 2006.175.08:16:59.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:16:59.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:16:59.16#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.08:16:59.16#ibcon#ireg 7 cls_cnt 0 2006.175.08:16:59.16#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:16:59.28#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:16:59.28#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:16:59.28#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:16:59.28#ibcon#first serial, iclass 26, count 0 2006.175.08:16:59.28#ibcon#enter sib2, iclass 26, count 0 2006.175.08:16:59.28#ibcon#flushed, iclass 26, count 0 2006.175.08:16:59.28#ibcon#about to write, iclass 26, count 0 2006.175.08:16:59.28#ibcon#wrote, iclass 26, count 0 2006.175.08:16:59.28#ibcon#about to read 3, iclass 26, count 0 2006.175.08:16:59.30#ibcon#read 3, iclass 26, count 0 2006.175.08:16:59.30#ibcon#about to read 4, iclass 26, count 0 2006.175.08:16:59.30#ibcon#read 4, iclass 26, count 0 2006.175.08:16:59.30#ibcon#about to read 5, iclass 26, count 0 2006.175.08:16:59.30#ibcon#read 5, iclass 26, count 0 2006.175.08:16:59.30#ibcon#about to read 6, iclass 26, count 0 2006.175.08:16:59.30#ibcon#read 6, iclass 26, count 0 2006.175.08:16:59.30#ibcon#end of sib2, iclass 26, count 0 2006.175.08:16:59.30#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:16:59.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:16:59.30#ibcon#[25=USB\r\n] 2006.175.08:16:59.30#ibcon#*before write, iclass 26, count 0 2006.175.08:16:59.30#ibcon#enter sib2, iclass 26, count 0 2006.175.08:16:59.30#ibcon#flushed, iclass 26, count 0 2006.175.08:16:59.30#ibcon#about to write, iclass 26, count 0 2006.175.08:16:59.30#ibcon#wrote, iclass 26, count 0 2006.175.08:16:59.30#ibcon#about to read 3, iclass 26, count 0 2006.175.08:16:59.33#ibcon#read 3, iclass 26, count 0 2006.175.08:16:59.33#ibcon#about to read 4, iclass 26, count 0 2006.175.08:16:59.33#ibcon#read 4, iclass 26, count 0 2006.175.08:16:59.33#ibcon#about to read 5, iclass 26, count 0 2006.175.08:16:59.33#ibcon#read 5, iclass 26, count 0 2006.175.08:16:59.33#ibcon#about to read 6, iclass 26, count 0 2006.175.08:16:59.33#ibcon#read 6, iclass 26, count 0 2006.175.08:16:59.33#ibcon#end of sib2, iclass 26, count 0 2006.175.08:16:59.33#ibcon#*after write, iclass 26, count 0 2006.175.08:16:59.33#ibcon#*before return 0, iclass 26, count 0 2006.175.08:16:59.33#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:16:59.33#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:16:59.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:16:59.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:16:59.33$vc4f8/valo=5,652.99 2006.175.08:16:59.33#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.08:16:59.33#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.08:16:59.33#ibcon#ireg 17 cls_cnt 0 2006.175.08:16:59.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:16:59.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:16:59.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:16:59.33#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:16:59.33#ibcon#first serial, iclass 28, count 0 2006.175.08:16:59.33#ibcon#enter sib2, iclass 28, count 0 2006.175.08:16:59.33#ibcon#flushed, iclass 28, count 0 2006.175.08:16:59.33#ibcon#about to write, iclass 28, count 0 2006.175.08:16:59.33#ibcon#wrote, iclass 28, count 0 2006.175.08:16:59.33#ibcon#about to read 3, iclass 28, count 0 2006.175.08:16:59.35#ibcon#read 3, iclass 28, count 0 2006.175.08:16:59.35#ibcon#about to read 4, iclass 28, count 0 2006.175.08:16:59.35#ibcon#read 4, iclass 28, count 0 2006.175.08:16:59.35#ibcon#about to read 5, iclass 28, count 0 2006.175.08:16:59.35#ibcon#read 5, iclass 28, count 0 2006.175.08:16:59.35#ibcon#about to read 6, iclass 28, count 0 2006.175.08:16:59.35#ibcon#read 6, iclass 28, count 0 2006.175.08:16:59.35#ibcon#end of sib2, iclass 28, count 0 2006.175.08:16:59.35#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:16:59.35#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:16:59.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:16:59.35#ibcon#*before write, iclass 28, count 0 2006.175.08:16:59.35#ibcon#enter sib2, iclass 28, count 0 2006.175.08:16:59.35#ibcon#flushed, iclass 28, count 0 2006.175.08:16:59.35#ibcon#about to write, iclass 28, count 0 2006.175.08:16:59.35#ibcon#wrote, iclass 28, count 0 2006.175.08:16:59.35#ibcon#about to read 3, iclass 28, count 0 2006.175.08:16:59.39#ibcon#read 3, iclass 28, count 0 2006.175.08:16:59.39#ibcon#about to read 4, iclass 28, count 0 2006.175.08:16:59.39#ibcon#read 4, iclass 28, count 0 2006.175.08:16:59.39#ibcon#about to read 5, iclass 28, count 0 2006.175.08:16:59.39#ibcon#read 5, iclass 28, count 0 2006.175.08:16:59.39#ibcon#about to read 6, iclass 28, count 0 2006.175.08:16:59.39#ibcon#read 6, iclass 28, count 0 2006.175.08:16:59.39#ibcon#end of sib2, iclass 28, count 0 2006.175.08:16:59.39#ibcon#*after write, iclass 28, count 0 2006.175.08:16:59.39#ibcon#*before return 0, iclass 28, count 0 2006.175.08:16:59.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:16:59.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:16:59.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:16:59.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:16:59.39$vc4f8/va=5,7 2006.175.08:16:59.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.08:16:59.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.08:16:59.39#ibcon#ireg 11 cls_cnt 2 2006.175.08:16:59.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:16:59.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:16:59.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:16:59.45#ibcon#enter wrdev, iclass 30, count 2 2006.175.08:16:59.45#ibcon#first serial, iclass 30, count 2 2006.175.08:16:59.45#ibcon#enter sib2, iclass 30, count 2 2006.175.08:16:59.45#ibcon#flushed, iclass 30, count 2 2006.175.08:16:59.45#ibcon#about to write, iclass 30, count 2 2006.175.08:16:59.45#ibcon#wrote, iclass 30, count 2 2006.175.08:16:59.45#ibcon#about to read 3, iclass 30, count 2 2006.175.08:16:59.47#ibcon#read 3, iclass 30, count 2 2006.175.08:16:59.47#ibcon#about to read 4, iclass 30, count 2 2006.175.08:16:59.47#ibcon#read 4, iclass 30, count 2 2006.175.08:16:59.47#ibcon#about to read 5, iclass 30, count 2 2006.175.08:16:59.47#ibcon#read 5, iclass 30, count 2 2006.175.08:16:59.47#ibcon#about to read 6, iclass 30, count 2 2006.175.08:16:59.47#ibcon#read 6, iclass 30, count 2 2006.175.08:16:59.47#ibcon#end of sib2, iclass 30, count 2 2006.175.08:16:59.47#ibcon#*mode == 0, iclass 30, count 2 2006.175.08:16:59.47#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.08:16:59.47#ibcon#[25=AT05-07\r\n] 2006.175.08:16:59.47#ibcon#*before write, iclass 30, count 2 2006.175.08:16:59.47#ibcon#enter sib2, iclass 30, count 2 2006.175.08:16:59.47#ibcon#flushed, iclass 30, count 2 2006.175.08:16:59.47#ibcon#about to write, iclass 30, count 2 2006.175.08:16:59.47#ibcon#wrote, iclass 30, count 2 2006.175.08:16:59.47#ibcon#about to read 3, iclass 30, count 2 2006.175.08:16:59.50#ibcon#read 3, iclass 30, count 2 2006.175.08:16:59.50#ibcon#about to read 4, iclass 30, count 2 2006.175.08:16:59.50#ibcon#read 4, iclass 30, count 2 2006.175.08:16:59.50#ibcon#about to read 5, iclass 30, count 2 2006.175.08:16:59.50#ibcon#read 5, iclass 30, count 2 2006.175.08:16:59.50#ibcon#about to read 6, iclass 30, count 2 2006.175.08:16:59.50#ibcon#read 6, iclass 30, count 2 2006.175.08:16:59.50#ibcon#end of sib2, iclass 30, count 2 2006.175.08:16:59.50#ibcon#*after write, iclass 30, count 2 2006.175.08:16:59.50#ibcon#*before return 0, iclass 30, count 2 2006.175.08:16:59.50#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:16:59.50#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:16:59.50#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.08:16:59.50#ibcon#ireg 7 cls_cnt 0 2006.175.08:16:59.50#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:16:59.62#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:16:59.62#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:16:59.62#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:16:59.62#ibcon#first serial, iclass 30, count 0 2006.175.08:16:59.62#ibcon#enter sib2, iclass 30, count 0 2006.175.08:16:59.62#ibcon#flushed, iclass 30, count 0 2006.175.08:16:59.62#ibcon#about to write, iclass 30, count 0 2006.175.08:16:59.62#ibcon#wrote, iclass 30, count 0 2006.175.08:16:59.62#ibcon#about to read 3, iclass 30, count 0 2006.175.08:16:59.64#ibcon#read 3, iclass 30, count 0 2006.175.08:16:59.64#ibcon#about to read 4, iclass 30, count 0 2006.175.08:16:59.64#ibcon#read 4, iclass 30, count 0 2006.175.08:16:59.64#ibcon#about to read 5, iclass 30, count 0 2006.175.08:16:59.64#ibcon#read 5, iclass 30, count 0 2006.175.08:16:59.64#ibcon#about to read 6, iclass 30, count 0 2006.175.08:16:59.64#ibcon#read 6, iclass 30, count 0 2006.175.08:16:59.64#ibcon#end of sib2, iclass 30, count 0 2006.175.08:16:59.64#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:16:59.64#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:16:59.64#ibcon#[25=USB\r\n] 2006.175.08:16:59.64#ibcon#*before write, iclass 30, count 0 2006.175.08:16:59.64#ibcon#enter sib2, iclass 30, count 0 2006.175.08:16:59.64#ibcon#flushed, iclass 30, count 0 2006.175.08:16:59.64#ibcon#about to write, iclass 30, count 0 2006.175.08:16:59.64#ibcon#wrote, iclass 30, count 0 2006.175.08:16:59.64#ibcon#about to read 3, iclass 30, count 0 2006.175.08:16:59.67#ibcon#read 3, iclass 30, count 0 2006.175.08:16:59.67#ibcon#about to read 4, iclass 30, count 0 2006.175.08:16:59.67#ibcon#read 4, iclass 30, count 0 2006.175.08:16:59.67#ibcon#about to read 5, iclass 30, count 0 2006.175.08:16:59.67#ibcon#read 5, iclass 30, count 0 2006.175.08:16:59.67#ibcon#about to read 6, iclass 30, count 0 2006.175.08:16:59.67#ibcon#read 6, iclass 30, count 0 2006.175.08:16:59.67#ibcon#end of sib2, iclass 30, count 0 2006.175.08:16:59.67#ibcon#*after write, iclass 30, count 0 2006.175.08:16:59.67#ibcon#*before return 0, iclass 30, count 0 2006.175.08:16:59.67#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:16:59.67#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:16:59.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:16:59.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:16:59.67$vc4f8/valo=6,772.99 2006.175.08:16:59.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.08:16:59.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.08:16:59.67#ibcon#ireg 17 cls_cnt 0 2006.175.08:16:59.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:16:59.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:16:59.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:16:59.67#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:16:59.67#ibcon#first serial, iclass 32, count 0 2006.175.08:16:59.67#ibcon#enter sib2, iclass 32, count 0 2006.175.08:16:59.67#ibcon#flushed, iclass 32, count 0 2006.175.08:16:59.67#ibcon#about to write, iclass 32, count 0 2006.175.08:16:59.67#ibcon#wrote, iclass 32, count 0 2006.175.08:16:59.67#ibcon#about to read 3, iclass 32, count 0 2006.175.08:16:59.69#ibcon#read 3, iclass 32, count 0 2006.175.08:16:59.69#ibcon#about to read 4, iclass 32, count 0 2006.175.08:16:59.69#ibcon#read 4, iclass 32, count 0 2006.175.08:16:59.69#ibcon#about to read 5, iclass 32, count 0 2006.175.08:16:59.69#ibcon#read 5, iclass 32, count 0 2006.175.08:16:59.69#ibcon#about to read 6, iclass 32, count 0 2006.175.08:16:59.69#ibcon#read 6, iclass 32, count 0 2006.175.08:16:59.69#ibcon#end of sib2, iclass 32, count 0 2006.175.08:16:59.69#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:16:59.69#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:16:59.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:16:59.69#ibcon#*before write, iclass 32, count 0 2006.175.08:16:59.69#ibcon#enter sib2, iclass 32, count 0 2006.175.08:16:59.69#ibcon#flushed, iclass 32, count 0 2006.175.08:16:59.69#ibcon#about to write, iclass 32, count 0 2006.175.08:16:59.69#ibcon#wrote, iclass 32, count 0 2006.175.08:16:59.69#ibcon#about to read 3, iclass 32, count 0 2006.175.08:16:59.73#ibcon#read 3, iclass 32, count 0 2006.175.08:16:59.73#ibcon#about to read 4, iclass 32, count 0 2006.175.08:16:59.73#ibcon#read 4, iclass 32, count 0 2006.175.08:16:59.73#ibcon#about to read 5, iclass 32, count 0 2006.175.08:16:59.73#ibcon#read 5, iclass 32, count 0 2006.175.08:16:59.73#ibcon#about to read 6, iclass 32, count 0 2006.175.08:16:59.73#ibcon#read 6, iclass 32, count 0 2006.175.08:16:59.73#ibcon#end of sib2, iclass 32, count 0 2006.175.08:16:59.73#ibcon#*after write, iclass 32, count 0 2006.175.08:16:59.73#ibcon#*before return 0, iclass 32, count 0 2006.175.08:16:59.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:16:59.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:16:59.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:16:59.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:16:59.73$vc4f8/va=6,6 2006.175.08:16:59.73#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.175.08:16:59.73#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.175.08:16:59.73#ibcon#ireg 11 cls_cnt 2 2006.175.08:16:59.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:16:59.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:16:59.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:16:59.79#ibcon#enter wrdev, iclass 34, count 2 2006.175.08:16:59.79#ibcon#first serial, iclass 34, count 2 2006.175.08:16:59.79#ibcon#enter sib2, iclass 34, count 2 2006.175.08:16:59.79#ibcon#flushed, iclass 34, count 2 2006.175.08:16:59.79#ibcon#about to write, iclass 34, count 2 2006.175.08:16:59.79#ibcon#wrote, iclass 34, count 2 2006.175.08:16:59.79#ibcon#about to read 3, iclass 34, count 2 2006.175.08:16:59.81#ibcon#read 3, iclass 34, count 2 2006.175.08:16:59.81#ibcon#about to read 4, iclass 34, count 2 2006.175.08:16:59.81#ibcon#read 4, iclass 34, count 2 2006.175.08:16:59.81#ibcon#about to read 5, iclass 34, count 2 2006.175.08:16:59.81#ibcon#read 5, iclass 34, count 2 2006.175.08:16:59.81#ibcon#about to read 6, iclass 34, count 2 2006.175.08:16:59.81#ibcon#read 6, iclass 34, count 2 2006.175.08:16:59.81#ibcon#end of sib2, iclass 34, count 2 2006.175.08:16:59.81#ibcon#*mode == 0, iclass 34, count 2 2006.175.08:16:59.81#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.175.08:16:59.81#ibcon#[25=AT06-06\r\n] 2006.175.08:16:59.81#ibcon#*before write, iclass 34, count 2 2006.175.08:16:59.81#ibcon#enter sib2, iclass 34, count 2 2006.175.08:16:59.81#ibcon#flushed, iclass 34, count 2 2006.175.08:16:59.81#ibcon#about to write, iclass 34, count 2 2006.175.08:16:59.81#ibcon#wrote, iclass 34, count 2 2006.175.08:16:59.81#ibcon#about to read 3, iclass 34, count 2 2006.175.08:16:59.84#ibcon#read 3, iclass 34, count 2 2006.175.08:16:59.84#ibcon#about to read 4, iclass 34, count 2 2006.175.08:16:59.84#ibcon#read 4, iclass 34, count 2 2006.175.08:16:59.84#ibcon#about to read 5, iclass 34, count 2 2006.175.08:16:59.84#ibcon#read 5, iclass 34, count 2 2006.175.08:16:59.84#ibcon#about to read 6, iclass 34, count 2 2006.175.08:16:59.84#ibcon#read 6, iclass 34, count 2 2006.175.08:16:59.84#ibcon#end of sib2, iclass 34, count 2 2006.175.08:16:59.84#ibcon#*after write, iclass 34, count 2 2006.175.08:16:59.84#ibcon#*before return 0, iclass 34, count 2 2006.175.08:16:59.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:16:59.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:16:59.84#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.175.08:16:59.84#ibcon#ireg 7 cls_cnt 0 2006.175.08:16:59.84#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:16:59.96#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:16:59.96#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:16:59.96#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:16:59.96#ibcon#first serial, iclass 34, count 0 2006.175.08:16:59.96#ibcon#enter sib2, iclass 34, count 0 2006.175.08:16:59.96#ibcon#flushed, iclass 34, count 0 2006.175.08:16:59.96#ibcon#about to write, iclass 34, count 0 2006.175.08:16:59.96#ibcon#wrote, iclass 34, count 0 2006.175.08:16:59.96#ibcon#about to read 3, iclass 34, count 0 2006.175.08:16:59.98#ibcon#read 3, iclass 34, count 0 2006.175.08:16:59.98#ibcon#about to read 4, iclass 34, count 0 2006.175.08:16:59.98#ibcon#read 4, iclass 34, count 0 2006.175.08:16:59.98#ibcon#about to read 5, iclass 34, count 0 2006.175.08:16:59.98#ibcon#read 5, iclass 34, count 0 2006.175.08:16:59.98#ibcon#about to read 6, iclass 34, count 0 2006.175.08:16:59.98#ibcon#read 6, iclass 34, count 0 2006.175.08:16:59.98#ibcon#end of sib2, iclass 34, count 0 2006.175.08:16:59.98#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:16:59.98#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:16:59.98#ibcon#[25=USB\r\n] 2006.175.08:16:59.98#ibcon#*before write, iclass 34, count 0 2006.175.08:16:59.98#ibcon#enter sib2, iclass 34, count 0 2006.175.08:16:59.98#ibcon#flushed, iclass 34, count 0 2006.175.08:16:59.98#ibcon#about to write, iclass 34, count 0 2006.175.08:16:59.98#ibcon#wrote, iclass 34, count 0 2006.175.08:16:59.98#ibcon#about to read 3, iclass 34, count 0 2006.175.08:17:00.01#ibcon#read 3, iclass 34, count 0 2006.175.08:17:00.01#ibcon#about to read 4, iclass 34, count 0 2006.175.08:17:00.01#ibcon#read 4, iclass 34, count 0 2006.175.08:17:00.01#ibcon#about to read 5, iclass 34, count 0 2006.175.08:17:00.01#ibcon#read 5, iclass 34, count 0 2006.175.08:17:00.01#ibcon#about to read 6, iclass 34, count 0 2006.175.08:17:00.01#ibcon#read 6, iclass 34, count 0 2006.175.08:17:00.01#ibcon#end of sib2, iclass 34, count 0 2006.175.08:17:00.01#ibcon#*after write, iclass 34, count 0 2006.175.08:17:00.01#ibcon#*before return 0, iclass 34, count 0 2006.175.08:17:00.01#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:17:00.01#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:17:00.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:17:00.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:17:00.01$vc4f8/valo=7,832.99 2006.175.08:17:00.01#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.08:17:00.01#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.08:17:00.01#ibcon#ireg 17 cls_cnt 0 2006.175.08:17:00.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:17:00.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:17:00.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:17:00.01#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:17:00.01#ibcon#first serial, iclass 36, count 0 2006.175.08:17:00.01#ibcon#enter sib2, iclass 36, count 0 2006.175.08:17:00.01#ibcon#flushed, iclass 36, count 0 2006.175.08:17:00.01#ibcon#about to write, iclass 36, count 0 2006.175.08:17:00.01#ibcon#wrote, iclass 36, count 0 2006.175.08:17:00.01#ibcon#about to read 3, iclass 36, count 0 2006.175.08:17:00.03#ibcon#read 3, iclass 36, count 0 2006.175.08:17:00.03#ibcon#about to read 4, iclass 36, count 0 2006.175.08:17:00.03#ibcon#read 4, iclass 36, count 0 2006.175.08:17:00.03#ibcon#about to read 5, iclass 36, count 0 2006.175.08:17:00.03#ibcon#read 5, iclass 36, count 0 2006.175.08:17:00.03#ibcon#about to read 6, iclass 36, count 0 2006.175.08:17:00.03#ibcon#read 6, iclass 36, count 0 2006.175.08:17:00.03#ibcon#end of sib2, iclass 36, count 0 2006.175.08:17:00.03#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:17:00.03#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:17:00.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:17:00.03#ibcon#*before write, iclass 36, count 0 2006.175.08:17:00.03#ibcon#enter sib2, iclass 36, count 0 2006.175.08:17:00.03#ibcon#flushed, iclass 36, count 0 2006.175.08:17:00.03#ibcon#about to write, iclass 36, count 0 2006.175.08:17:00.03#ibcon#wrote, iclass 36, count 0 2006.175.08:17:00.03#ibcon#about to read 3, iclass 36, count 0 2006.175.08:17:00.07#ibcon#read 3, iclass 36, count 0 2006.175.08:17:00.07#ibcon#about to read 4, iclass 36, count 0 2006.175.08:17:00.07#ibcon#read 4, iclass 36, count 0 2006.175.08:17:00.07#ibcon#about to read 5, iclass 36, count 0 2006.175.08:17:00.07#ibcon#read 5, iclass 36, count 0 2006.175.08:17:00.07#ibcon#about to read 6, iclass 36, count 0 2006.175.08:17:00.07#ibcon#read 6, iclass 36, count 0 2006.175.08:17:00.07#ibcon#end of sib2, iclass 36, count 0 2006.175.08:17:00.07#ibcon#*after write, iclass 36, count 0 2006.175.08:17:00.07#ibcon#*before return 0, iclass 36, count 0 2006.175.08:17:00.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:17:00.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:17:00.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:17:00.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:17:00.07$vc4f8/va=7,6 2006.175.08:17:00.07#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.175.08:17:00.07#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.175.08:17:00.07#ibcon#ireg 11 cls_cnt 2 2006.175.08:17:00.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:17:00.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:17:00.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:17:00.13#ibcon#enter wrdev, iclass 38, count 2 2006.175.08:17:00.13#ibcon#first serial, iclass 38, count 2 2006.175.08:17:00.13#ibcon#enter sib2, iclass 38, count 2 2006.175.08:17:00.13#ibcon#flushed, iclass 38, count 2 2006.175.08:17:00.13#ibcon#about to write, iclass 38, count 2 2006.175.08:17:00.13#ibcon#wrote, iclass 38, count 2 2006.175.08:17:00.13#ibcon#about to read 3, iclass 38, count 2 2006.175.08:17:00.15#ibcon#read 3, iclass 38, count 2 2006.175.08:17:00.15#ibcon#about to read 4, iclass 38, count 2 2006.175.08:17:00.15#ibcon#read 4, iclass 38, count 2 2006.175.08:17:00.15#ibcon#about to read 5, iclass 38, count 2 2006.175.08:17:00.15#ibcon#read 5, iclass 38, count 2 2006.175.08:17:00.15#ibcon#about to read 6, iclass 38, count 2 2006.175.08:17:00.15#ibcon#read 6, iclass 38, count 2 2006.175.08:17:00.15#ibcon#end of sib2, iclass 38, count 2 2006.175.08:17:00.15#ibcon#*mode == 0, iclass 38, count 2 2006.175.08:17:00.15#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.175.08:17:00.15#ibcon#[25=AT07-06\r\n] 2006.175.08:17:00.15#ibcon#*before write, iclass 38, count 2 2006.175.08:17:00.15#ibcon#enter sib2, iclass 38, count 2 2006.175.08:17:00.15#ibcon#flushed, iclass 38, count 2 2006.175.08:17:00.15#ibcon#about to write, iclass 38, count 2 2006.175.08:17:00.15#ibcon#wrote, iclass 38, count 2 2006.175.08:17:00.15#ibcon#about to read 3, iclass 38, count 2 2006.175.08:17:00.18#ibcon#read 3, iclass 38, count 2 2006.175.08:17:00.18#ibcon#about to read 4, iclass 38, count 2 2006.175.08:17:00.18#ibcon#read 4, iclass 38, count 2 2006.175.08:17:00.18#ibcon#about to read 5, iclass 38, count 2 2006.175.08:17:00.18#ibcon#read 5, iclass 38, count 2 2006.175.08:17:00.18#ibcon#about to read 6, iclass 38, count 2 2006.175.08:17:00.18#ibcon#read 6, iclass 38, count 2 2006.175.08:17:00.18#ibcon#end of sib2, iclass 38, count 2 2006.175.08:17:00.18#ibcon#*after write, iclass 38, count 2 2006.175.08:17:00.18#ibcon#*before return 0, iclass 38, count 2 2006.175.08:17:00.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:17:00.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:17:00.18#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.175.08:17:00.18#ibcon#ireg 7 cls_cnt 0 2006.175.08:17:00.18#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:17:00.30#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:17:00.30#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:17:00.30#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:17:00.30#ibcon#first serial, iclass 38, count 0 2006.175.08:17:00.30#ibcon#enter sib2, iclass 38, count 0 2006.175.08:17:00.30#ibcon#flushed, iclass 38, count 0 2006.175.08:17:00.30#ibcon#about to write, iclass 38, count 0 2006.175.08:17:00.30#ibcon#wrote, iclass 38, count 0 2006.175.08:17:00.30#ibcon#about to read 3, iclass 38, count 0 2006.175.08:17:00.32#ibcon#read 3, iclass 38, count 0 2006.175.08:17:00.32#ibcon#about to read 4, iclass 38, count 0 2006.175.08:17:00.32#ibcon#read 4, iclass 38, count 0 2006.175.08:17:00.32#ibcon#about to read 5, iclass 38, count 0 2006.175.08:17:00.32#ibcon#read 5, iclass 38, count 0 2006.175.08:17:00.32#ibcon#about to read 6, iclass 38, count 0 2006.175.08:17:00.32#ibcon#read 6, iclass 38, count 0 2006.175.08:17:00.32#ibcon#end of sib2, iclass 38, count 0 2006.175.08:17:00.32#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:17:00.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:17:00.32#ibcon#[25=USB\r\n] 2006.175.08:17:00.32#ibcon#*before write, iclass 38, count 0 2006.175.08:17:00.32#ibcon#enter sib2, iclass 38, count 0 2006.175.08:17:00.32#ibcon#flushed, iclass 38, count 0 2006.175.08:17:00.32#ibcon#about to write, iclass 38, count 0 2006.175.08:17:00.32#ibcon#wrote, iclass 38, count 0 2006.175.08:17:00.32#ibcon#about to read 3, iclass 38, count 0 2006.175.08:17:00.35#ibcon#read 3, iclass 38, count 0 2006.175.08:17:00.35#ibcon#about to read 4, iclass 38, count 0 2006.175.08:17:00.35#ibcon#read 4, iclass 38, count 0 2006.175.08:17:00.35#ibcon#about to read 5, iclass 38, count 0 2006.175.08:17:00.35#ibcon#read 5, iclass 38, count 0 2006.175.08:17:00.35#ibcon#about to read 6, iclass 38, count 0 2006.175.08:17:00.35#ibcon#read 6, iclass 38, count 0 2006.175.08:17:00.35#ibcon#end of sib2, iclass 38, count 0 2006.175.08:17:00.35#ibcon#*after write, iclass 38, count 0 2006.175.08:17:00.35#ibcon#*before return 0, iclass 38, count 0 2006.175.08:17:00.35#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:17:00.35#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:17:00.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:17:00.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:17:00.35$vc4f8/valo=8,852.99 2006.175.08:17:00.35#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.08:17:00.35#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.08:17:00.35#ibcon#ireg 17 cls_cnt 0 2006.175.08:17:00.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:17:00.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:17:00.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:17:00.35#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:17:00.35#ibcon#first serial, iclass 40, count 0 2006.175.08:17:00.35#ibcon#enter sib2, iclass 40, count 0 2006.175.08:17:00.35#ibcon#flushed, iclass 40, count 0 2006.175.08:17:00.35#ibcon#about to write, iclass 40, count 0 2006.175.08:17:00.35#ibcon#wrote, iclass 40, count 0 2006.175.08:17:00.35#ibcon#about to read 3, iclass 40, count 0 2006.175.08:17:00.37#ibcon#read 3, iclass 40, count 0 2006.175.08:17:00.37#ibcon#about to read 4, iclass 40, count 0 2006.175.08:17:00.37#ibcon#read 4, iclass 40, count 0 2006.175.08:17:00.37#ibcon#about to read 5, iclass 40, count 0 2006.175.08:17:00.37#ibcon#read 5, iclass 40, count 0 2006.175.08:17:00.37#ibcon#about to read 6, iclass 40, count 0 2006.175.08:17:00.37#ibcon#read 6, iclass 40, count 0 2006.175.08:17:00.37#ibcon#end of sib2, iclass 40, count 0 2006.175.08:17:00.37#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:17:00.37#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:17:00.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:17:00.37#ibcon#*before write, iclass 40, count 0 2006.175.08:17:00.37#ibcon#enter sib2, iclass 40, count 0 2006.175.08:17:00.37#ibcon#flushed, iclass 40, count 0 2006.175.08:17:00.37#ibcon#about to write, iclass 40, count 0 2006.175.08:17:00.37#ibcon#wrote, iclass 40, count 0 2006.175.08:17:00.37#ibcon#about to read 3, iclass 40, count 0 2006.175.08:17:00.41#ibcon#read 3, iclass 40, count 0 2006.175.08:17:00.41#ibcon#about to read 4, iclass 40, count 0 2006.175.08:17:00.41#ibcon#read 4, iclass 40, count 0 2006.175.08:17:00.41#ibcon#about to read 5, iclass 40, count 0 2006.175.08:17:00.41#ibcon#read 5, iclass 40, count 0 2006.175.08:17:00.41#ibcon#about to read 6, iclass 40, count 0 2006.175.08:17:00.41#ibcon#read 6, iclass 40, count 0 2006.175.08:17:00.41#ibcon#end of sib2, iclass 40, count 0 2006.175.08:17:00.41#ibcon#*after write, iclass 40, count 0 2006.175.08:17:00.41#ibcon#*before return 0, iclass 40, count 0 2006.175.08:17:00.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:17:00.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:17:00.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:17:00.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:17:00.41$vc4f8/va=8,6 2006.175.08:17:00.41#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.175.08:17:00.41#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.175.08:17:00.41#ibcon#ireg 11 cls_cnt 2 2006.175.08:17:00.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:17:00.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:17:00.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:17:00.47#ibcon#enter wrdev, iclass 4, count 2 2006.175.08:17:00.47#ibcon#first serial, iclass 4, count 2 2006.175.08:17:00.47#ibcon#enter sib2, iclass 4, count 2 2006.175.08:17:00.47#ibcon#flushed, iclass 4, count 2 2006.175.08:17:00.47#ibcon#about to write, iclass 4, count 2 2006.175.08:17:00.47#ibcon#wrote, iclass 4, count 2 2006.175.08:17:00.47#ibcon#about to read 3, iclass 4, count 2 2006.175.08:17:00.49#ibcon#read 3, iclass 4, count 2 2006.175.08:17:00.49#ibcon#about to read 4, iclass 4, count 2 2006.175.08:17:00.49#ibcon#read 4, iclass 4, count 2 2006.175.08:17:00.49#ibcon#about to read 5, iclass 4, count 2 2006.175.08:17:00.49#ibcon#read 5, iclass 4, count 2 2006.175.08:17:00.49#ibcon#about to read 6, iclass 4, count 2 2006.175.08:17:00.49#ibcon#read 6, iclass 4, count 2 2006.175.08:17:00.49#ibcon#end of sib2, iclass 4, count 2 2006.175.08:17:00.49#ibcon#*mode == 0, iclass 4, count 2 2006.175.08:17:00.49#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.175.08:17:00.49#ibcon#[25=AT08-06\r\n] 2006.175.08:17:00.49#ibcon#*before write, iclass 4, count 2 2006.175.08:17:00.49#ibcon#enter sib2, iclass 4, count 2 2006.175.08:17:00.49#ibcon#flushed, iclass 4, count 2 2006.175.08:17:00.49#ibcon#about to write, iclass 4, count 2 2006.175.08:17:00.49#ibcon#wrote, iclass 4, count 2 2006.175.08:17:00.49#ibcon#about to read 3, iclass 4, count 2 2006.175.08:17:00.52#ibcon#read 3, iclass 4, count 2 2006.175.08:17:00.52#ibcon#about to read 4, iclass 4, count 2 2006.175.08:17:00.52#ibcon#read 4, iclass 4, count 2 2006.175.08:17:00.52#ibcon#about to read 5, iclass 4, count 2 2006.175.08:17:00.52#ibcon#read 5, iclass 4, count 2 2006.175.08:17:00.52#ibcon#about to read 6, iclass 4, count 2 2006.175.08:17:00.52#ibcon#read 6, iclass 4, count 2 2006.175.08:17:00.52#ibcon#end of sib2, iclass 4, count 2 2006.175.08:17:00.52#ibcon#*after write, iclass 4, count 2 2006.175.08:17:00.52#ibcon#*before return 0, iclass 4, count 2 2006.175.08:17:00.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:17:00.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:17:00.52#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.175.08:17:00.52#ibcon#ireg 7 cls_cnt 0 2006.175.08:17:00.52#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:17:00.64#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:17:00.64#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:17:00.64#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:17:00.64#ibcon#first serial, iclass 4, count 0 2006.175.08:17:00.64#ibcon#enter sib2, iclass 4, count 0 2006.175.08:17:00.64#ibcon#flushed, iclass 4, count 0 2006.175.08:17:00.64#ibcon#about to write, iclass 4, count 0 2006.175.08:17:00.64#ibcon#wrote, iclass 4, count 0 2006.175.08:17:00.64#ibcon#about to read 3, iclass 4, count 0 2006.175.08:17:00.66#ibcon#read 3, iclass 4, count 0 2006.175.08:17:00.66#ibcon#about to read 4, iclass 4, count 0 2006.175.08:17:00.66#ibcon#read 4, iclass 4, count 0 2006.175.08:17:00.66#ibcon#about to read 5, iclass 4, count 0 2006.175.08:17:00.66#ibcon#read 5, iclass 4, count 0 2006.175.08:17:00.66#ibcon#about to read 6, iclass 4, count 0 2006.175.08:17:00.66#ibcon#read 6, iclass 4, count 0 2006.175.08:17:00.66#ibcon#end of sib2, iclass 4, count 0 2006.175.08:17:00.66#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:17:00.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:17:00.66#ibcon#[25=USB\r\n] 2006.175.08:17:00.66#ibcon#*before write, iclass 4, count 0 2006.175.08:17:00.66#ibcon#enter sib2, iclass 4, count 0 2006.175.08:17:00.66#ibcon#flushed, iclass 4, count 0 2006.175.08:17:00.66#ibcon#about to write, iclass 4, count 0 2006.175.08:17:00.66#ibcon#wrote, iclass 4, count 0 2006.175.08:17:00.66#ibcon#about to read 3, iclass 4, count 0 2006.175.08:17:00.69#ibcon#read 3, iclass 4, count 0 2006.175.08:17:00.69#ibcon#about to read 4, iclass 4, count 0 2006.175.08:17:00.69#ibcon#read 4, iclass 4, count 0 2006.175.08:17:00.69#ibcon#about to read 5, iclass 4, count 0 2006.175.08:17:00.69#ibcon#read 5, iclass 4, count 0 2006.175.08:17:00.69#ibcon#about to read 6, iclass 4, count 0 2006.175.08:17:00.69#ibcon#read 6, iclass 4, count 0 2006.175.08:17:00.69#ibcon#end of sib2, iclass 4, count 0 2006.175.08:17:00.69#ibcon#*after write, iclass 4, count 0 2006.175.08:17:00.69#ibcon#*before return 0, iclass 4, count 0 2006.175.08:17:00.69#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:17:00.69#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:17:00.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:17:00.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:17:00.69$vc4f8/vblo=1,632.99 2006.175.08:17:00.69#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.175.08:17:00.69#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.175.08:17:00.69#ibcon#ireg 17 cls_cnt 0 2006.175.08:17:00.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:17:00.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:17:00.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:17:00.69#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:17:00.69#ibcon#first serial, iclass 6, count 0 2006.175.08:17:00.69#ibcon#enter sib2, iclass 6, count 0 2006.175.08:17:00.69#ibcon#flushed, iclass 6, count 0 2006.175.08:17:00.69#ibcon#about to write, iclass 6, count 0 2006.175.08:17:00.69#ibcon#wrote, iclass 6, count 0 2006.175.08:17:00.69#ibcon#about to read 3, iclass 6, count 0 2006.175.08:17:00.71#ibcon#read 3, iclass 6, count 0 2006.175.08:17:00.71#ibcon#about to read 4, iclass 6, count 0 2006.175.08:17:00.71#ibcon#read 4, iclass 6, count 0 2006.175.08:17:00.71#ibcon#about to read 5, iclass 6, count 0 2006.175.08:17:00.71#ibcon#read 5, iclass 6, count 0 2006.175.08:17:00.71#ibcon#about to read 6, iclass 6, count 0 2006.175.08:17:00.71#ibcon#read 6, iclass 6, count 0 2006.175.08:17:00.71#ibcon#end of sib2, iclass 6, count 0 2006.175.08:17:00.71#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:17:00.71#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:17:00.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:17:00.71#ibcon#*before write, iclass 6, count 0 2006.175.08:17:00.71#ibcon#enter sib2, iclass 6, count 0 2006.175.08:17:00.71#ibcon#flushed, iclass 6, count 0 2006.175.08:17:00.71#ibcon#about to write, iclass 6, count 0 2006.175.08:17:00.71#ibcon#wrote, iclass 6, count 0 2006.175.08:17:00.71#ibcon#about to read 3, iclass 6, count 0 2006.175.08:17:00.75#ibcon#read 3, iclass 6, count 0 2006.175.08:17:00.75#ibcon#about to read 4, iclass 6, count 0 2006.175.08:17:00.75#ibcon#read 4, iclass 6, count 0 2006.175.08:17:00.75#ibcon#about to read 5, iclass 6, count 0 2006.175.08:17:00.75#ibcon#read 5, iclass 6, count 0 2006.175.08:17:00.75#ibcon#about to read 6, iclass 6, count 0 2006.175.08:17:00.75#ibcon#read 6, iclass 6, count 0 2006.175.08:17:00.75#ibcon#end of sib2, iclass 6, count 0 2006.175.08:17:00.75#ibcon#*after write, iclass 6, count 0 2006.175.08:17:00.75#ibcon#*before return 0, iclass 6, count 0 2006.175.08:17:00.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:17:00.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:17:00.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:17:00.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:17:00.75$vc4f8/vb=1,4 2006.175.08:17:00.75#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.175.08:17:00.75#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.175.08:17:00.75#ibcon#ireg 11 cls_cnt 2 2006.175.08:17:00.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:17:00.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:17:00.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:17:00.75#ibcon#enter wrdev, iclass 10, count 2 2006.175.08:17:00.75#ibcon#first serial, iclass 10, count 2 2006.175.08:17:00.75#ibcon#enter sib2, iclass 10, count 2 2006.175.08:17:00.75#ibcon#flushed, iclass 10, count 2 2006.175.08:17:00.75#ibcon#about to write, iclass 10, count 2 2006.175.08:17:00.75#ibcon#wrote, iclass 10, count 2 2006.175.08:17:00.75#ibcon#about to read 3, iclass 10, count 2 2006.175.08:17:00.77#ibcon#read 3, iclass 10, count 2 2006.175.08:17:00.77#ibcon#about to read 4, iclass 10, count 2 2006.175.08:17:00.77#ibcon#read 4, iclass 10, count 2 2006.175.08:17:00.77#ibcon#about to read 5, iclass 10, count 2 2006.175.08:17:00.77#ibcon#read 5, iclass 10, count 2 2006.175.08:17:00.77#ibcon#about to read 6, iclass 10, count 2 2006.175.08:17:00.77#ibcon#read 6, iclass 10, count 2 2006.175.08:17:00.77#ibcon#end of sib2, iclass 10, count 2 2006.175.08:17:00.77#ibcon#*mode == 0, iclass 10, count 2 2006.175.08:17:00.77#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.175.08:17:00.77#ibcon#[27=AT01-04\r\n] 2006.175.08:17:00.77#ibcon#*before write, iclass 10, count 2 2006.175.08:17:00.77#ibcon#enter sib2, iclass 10, count 2 2006.175.08:17:00.77#ibcon#flushed, iclass 10, count 2 2006.175.08:17:00.77#ibcon#about to write, iclass 10, count 2 2006.175.08:17:00.77#ibcon#wrote, iclass 10, count 2 2006.175.08:17:00.77#ibcon#about to read 3, iclass 10, count 2 2006.175.08:17:00.80#ibcon#read 3, iclass 10, count 2 2006.175.08:17:00.80#ibcon#about to read 4, iclass 10, count 2 2006.175.08:17:00.80#ibcon#read 4, iclass 10, count 2 2006.175.08:17:00.80#ibcon#about to read 5, iclass 10, count 2 2006.175.08:17:00.80#ibcon#read 5, iclass 10, count 2 2006.175.08:17:00.80#ibcon#about to read 6, iclass 10, count 2 2006.175.08:17:00.80#ibcon#read 6, iclass 10, count 2 2006.175.08:17:00.80#ibcon#end of sib2, iclass 10, count 2 2006.175.08:17:00.80#ibcon#*after write, iclass 10, count 2 2006.175.08:17:00.80#ibcon#*before return 0, iclass 10, count 2 2006.175.08:17:00.80#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:17:00.80#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:17:00.80#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.175.08:17:00.80#ibcon#ireg 7 cls_cnt 0 2006.175.08:17:00.80#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:17:00.92#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:17:00.92#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:17:00.92#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:17:00.92#ibcon#first serial, iclass 10, count 0 2006.175.08:17:00.92#ibcon#enter sib2, iclass 10, count 0 2006.175.08:17:00.92#ibcon#flushed, iclass 10, count 0 2006.175.08:17:00.92#ibcon#about to write, iclass 10, count 0 2006.175.08:17:00.92#ibcon#wrote, iclass 10, count 0 2006.175.08:17:00.92#ibcon#about to read 3, iclass 10, count 0 2006.175.08:17:00.94#ibcon#read 3, iclass 10, count 0 2006.175.08:17:00.94#ibcon#about to read 4, iclass 10, count 0 2006.175.08:17:00.94#ibcon#read 4, iclass 10, count 0 2006.175.08:17:00.94#ibcon#about to read 5, iclass 10, count 0 2006.175.08:17:00.94#ibcon#read 5, iclass 10, count 0 2006.175.08:17:00.94#ibcon#about to read 6, iclass 10, count 0 2006.175.08:17:00.94#ibcon#read 6, iclass 10, count 0 2006.175.08:17:00.94#ibcon#end of sib2, iclass 10, count 0 2006.175.08:17:00.94#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:17:00.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:17:00.94#ibcon#[27=USB\r\n] 2006.175.08:17:00.94#ibcon#*before write, iclass 10, count 0 2006.175.08:17:00.94#ibcon#enter sib2, iclass 10, count 0 2006.175.08:17:00.94#ibcon#flushed, iclass 10, count 0 2006.175.08:17:00.94#ibcon#about to write, iclass 10, count 0 2006.175.08:17:00.94#ibcon#wrote, iclass 10, count 0 2006.175.08:17:00.94#ibcon#about to read 3, iclass 10, count 0 2006.175.08:17:00.97#ibcon#read 3, iclass 10, count 0 2006.175.08:17:00.97#ibcon#about to read 4, iclass 10, count 0 2006.175.08:17:00.97#ibcon#read 4, iclass 10, count 0 2006.175.08:17:00.97#ibcon#about to read 5, iclass 10, count 0 2006.175.08:17:00.97#ibcon#read 5, iclass 10, count 0 2006.175.08:17:00.97#ibcon#about to read 6, iclass 10, count 0 2006.175.08:17:00.97#ibcon#read 6, iclass 10, count 0 2006.175.08:17:00.97#ibcon#end of sib2, iclass 10, count 0 2006.175.08:17:00.97#ibcon#*after write, iclass 10, count 0 2006.175.08:17:00.97#ibcon#*before return 0, iclass 10, count 0 2006.175.08:17:00.97#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:17:00.97#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:17:00.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:17:00.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:17:00.97$vc4f8/vblo=2,640.99 2006.175.08:17:00.97#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.08:17:00.97#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.08:17:00.97#ibcon#ireg 17 cls_cnt 0 2006.175.08:17:00.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:17:00.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:17:00.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:17:00.97#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:17:00.97#ibcon#first serial, iclass 12, count 0 2006.175.08:17:00.97#ibcon#enter sib2, iclass 12, count 0 2006.175.08:17:00.97#ibcon#flushed, iclass 12, count 0 2006.175.08:17:00.97#ibcon#about to write, iclass 12, count 0 2006.175.08:17:00.97#ibcon#wrote, iclass 12, count 0 2006.175.08:17:00.97#ibcon#about to read 3, iclass 12, count 0 2006.175.08:17:00.99#ibcon#read 3, iclass 12, count 0 2006.175.08:17:00.99#ibcon#about to read 4, iclass 12, count 0 2006.175.08:17:00.99#ibcon#read 4, iclass 12, count 0 2006.175.08:17:00.99#ibcon#about to read 5, iclass 12, count 0 2006.175.08:17:00.99#ibcon#read 5, iclass 12, count 0 2006.175.08:17:00.99#ibcon#about to read 6, iclass 12, count 0 2006.175.08:17:00.99#ibcon#read 6, iclass 12, count 0 2006.175.08:17:00.99#ibcon#end of sib2, iclass 12, count 0 2006.175.08:17:00.99#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:17:00.99#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:17:00.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:17:00.99#ibcon#*before write, iclass 12, count 0 2006.175.08:17:00.99#ibcon#enter sib2, iclass 12, count 0 2006.175.08:17:00.99#ibcon#flushed, iclass 12, count 0 2006.175.08:17:00.99#ibcon#about to write, iclass 12, count 0 2006.175.08:17:00.99#ibcon#wrote, iclass 12, count 0 2006.175.08:17:00.99#ibcon#about to read 3, iclass 12, count 0 2006.175.08:17:01.03#ibcon#read 3, iclass 12, count 0 2006.175.08:17:01.03#ibcon#about to read 4, iclass 12, count 0 2006.175.08:17:01.03#ibcon#read 4, iclass 12, count 0 2006.175.08:17:01.03#ibcon#about to read 5, iclass 12, count 0 2006.175.08:17:01.03#ibcon#read 5, iclass 12, count 0 2006.175.08:17:01.03#ibcon#about to read 6, iclass 12, count 0 2006.175.08:17:01.03#ibcon#read 6, iclass 12, count 0 2006.175.08:17:01.03#ibcon#end of sib2, iclass 12, count 0 2006.175.08:17:01.03#ibcon#*after write, iclass 12, count 0 2006.175.08:17:01.03#ibcon#*before return 0, iclass 12, count 0 2006.175.08:17:01.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:17:01.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:17:01.03#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:17:01.03#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:17:01.03$vc4f8/vb=2,4 2006.175.08:17:01.03#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.08:17:01.03#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.08:17:01.03#ibcon#ireg 11 cls_cnt 2 2006.175.08:17:01.03#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:17:01.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:17:01.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:17:01.09#ibcon#enter wrdev, iclass 14, count 2 2006.175.08:17:01.09#ibcon#first serial, iclass 14, count 2 2006.175.08:17:01.09#ibcon#enter sib2, iclass 14, count 2 2006.175.08:17:01.09#ibcon#flushed, iclass 14, count 2 2006.175.08:17:01.09#ibcon#about to write, iclass 14, count 2 2006.175.08:17:01.09#ibcon#wrote, iclass 14, count 2 2006.175.08:17:01.09#ibcon#about to read 3, iclass 14, count 2 2006.175.08:17:01.11#ibcon#read 3, iclass 14, count 2 2006.175.08:17:01.11#ibcon#about to read 4, iclass 14, count 2 2006.175.08:17:01.11#ibcon#read 4, iclass 14, count 2 2006.175.08:17:01.11#ibcon#about to read 5, iclass 14, count 2 2006.175.08:17:01.11#ibcon#read 5, iclass 14, count 2 2006.175.08:17:01.11#ibcon#about to read 6, iclass 14, count 2 2006.175.08:17:01.11#ibcon#read 6, iclass 14, count 2 2006.175.08:17:01.11#ibcon#end of sib2, iclass 14, count 2 2006.175.08:17:01.11#ibcon#*mode == 0, iclass 14, count 2 2006.175.08:17:01.11#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.08:17:01.11#ibcon#[27=AT02-04\r\n] 2006.175.08:17:01.11#ibcon#*before write, iclass 14, count 2 2006.175.08:17:01.11#ibcon#enter sib2, iclass 14, count 2 2006.175.08:17:01.11#ibcon#flushed, iclass 14, count 2 2006.175.08:17:01.11#ibcon#about to write, iclass 14, count 2 2006.175.08:17:01.11#ibcon#wrote, iclass 14, count 2 2006.175.08:17:01.11#ibcon#about to read 3, iclass 14, count 2 2006.175.08:17:01.14#ibcon#read 3, iclass 14, count 2 2006.175.08:17:01.14#ibcon#about to read 4, iclass 14, count 2 2006.175.08:17:01.14#ibcon#read 4, iclass 14, count 2 2006.175.08:17:01.14#ibcon#about to read 5, iclass 14, count 2 2006.175.08:17:01.14#ibcon#read 5, iclass 14, count 2 2006.175.08:17:01.14#ibcon#about to read 6, iclass 14, count 2 2006.175.08:17:01.14#ibcon#read 6, iclass 14, count 2 2006.175.08:17:01.14#ibcon#end of sib2, iclass 14, count 2 2006.175.08:17:01.14#ibcon#*after write, iclass 14, count 2 2006.175.08:17:01.14#ibcon#*before return 0, iclass 14, count 2 2006.175.08:17:01.14#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:17:01.14#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:17:01.14#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.08:17:01.14#ibcon#ireg 7 cls_cnt 0 2006.175.08:17:01.14#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:17:01.26#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:17:01.26#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:17:01.26#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:17:01.26#ibcon#first serial, iclass 14, count 0 2006.175.08:17:01.26#ibcon#enter sib2, iclass 14, count 0 2006.175.08:17:01.26#ibcon#flushed, iclass 14, count 0 2006.175.08:17:01.26#ibcon#about to write, iclass 14, count 0 2006.175.08:17:01.26#ibcon#wrote, iclass 14, count 0 2006.175.08:17:01.26#ibcon#about to read 3, iclass 14, count 0 2006.175.08:17:01.28#ibcon#read 3, iclass 14, count 0 2006.175.08:17:01.28#ibcon#about to read 4, iclass 14, count 0 2006.175.08:17:01.28#ibcon#read 4, iclass 14, count 0 2006.175.08:17:01.28#ibcon#about to read 5, iclass 14, count 0 2006.175.08:17:01.28#ibcon#read 5, iclass 14, count 0 2006.175.08:17:01.28#ibcon#about to read 6, iclass 14, count 0 2006.175.08:17:01.28#ibcon#read 6, iclass 14, count 0 2006.175.08:17:01.28#ibcon#end of sib2, iclass 14, count 0 2006.175.08:17:01.28#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:17:01.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:17:01.28#ibcon#[27=USB\r\n] 2006.175.08:17:01.28#ibcon#*before write, iclass 14, count 0 2006.175.08:17:01.28#ibcon#enter sib2, iclass 14, count 0 2006.175.08:17:01.28#ibcon#flushed, iclass 14, count 0 2006.175.08:17:01.28#ibcon#about to write, iclass 14, count 0 2006.175.08:17:01.28#ibcon#wrote, iclass 14, count 0 2006.175.08:17:01.28#ibcon#about to read 3, iclass 14, count 0 2006.175.08:17:01.31#ibcon#read 3, iclass 14, count 0 2006.175.08:17:01.31#ibcon#about to read 4, iclass 14, count 0 2006.175.08:17:01.31#ibcon#read 4, iclass 14, count 0 2006.175.08:17:01.31#ibcon#about to read 5, iclass 14, count 0 2006.175.08:17:01.31#ibcon#read 5, iclass 14, count 0 2006.175.08:17:01.31#ibcon#about to read 6, iclass 14, count 0 2006.175.08:17:01.31#ibcon#read 6, iclass 14, count 0 2006.175.08:17:01.31#ibcon#end of sib2, iclass 14, count 0 2006.175.08:17:01.31#ibcon#*after write, iclass 14, count 0 2006.175.08:17:01.31#ibcon#*before return 0, iclass 14, count 0 2006.175.08:17:01.31#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:17:01.31#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:17:01.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:17:01.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:17:01.31$vc4f8/vblo=3,656.99 2006.175.08:17:01.31#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.08:17:01.31#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.08:17:01.31#ibcon#ireg 17 cls_cnt 0 2006.175.08:17:01.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:17:01.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:17:01.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:17:01.31#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:17:01.31#ibcon#first serial, iclass 16, count 0 2006.175.08:17:01.31#ibcon#enter sib2, iclass 16, count 0 2006.175.08:17:01.31#ibcon#flushed, iclass 16, count 0 2006.175.08:17:01.31#ibcon#about to write, iclass 16, count 0 2006.175.08:17:01.31#ibcon#wrote, iclass 16, count 0 2006.175.08:17:01.31#ibcon#about to read 3, iclass 16, count 0 2006.175.08:17:01.33#ibcon#read 3, iclass 16, count 0 2006.175.08:17:01.33#ibcon#about to read 4, iclass 16, count 0 2006.175.08:17:01.33#ibcon#read 4, iclass 16, count 0 2006.175.08:17:01.33#ibcon#about to read 5, iclass 16, count 0 2006.175.08:17:01.33#ibcon#read 5, iclass 16, count 0 2006.175.08:17:01.33#ibcon#about to read 6, iclass 16, count 0 2006.175.08:17:01.33#ibcon#read 6, iclass 16, count 0 2006.175.08:17:01.33#ibcon#end of sib2, iclass 16, count 0 2006.175.08:17:01.33#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:17:01.33#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:17:01.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:17:01.33#ibcon#*before write, iclass 16, count 0 2006.175.08:17:01.33#ibcon#enter sib2, iclass 16, count 0 2006.175.08:17:01.33#ibcon#flushed, iclass 16, count 0 2006.175.08:17:01.33#ibcon#about to write, iclass 16, count 0 2006.175.08:17:01.33#ibcon#wrote, iclass 16, count 0 2006.175.08:17:01.33#ibcon#about to read 3, iclass 16, count 0 2006.175.08:17:01.37#ibcon#read 3, iclass 16, count 0 2006.175.08:17:01.37#ibcon#about to read 4, iclass 16, count 0 2006.175.08:17:01.37#ibcon#read 4, iclass 16, count 0 2006.175.08:17:01.37#ibcon#about to read 5, iclass 16, count 0 2006.175.08:17:01.37#ibcon#read 5, iclass 16, count 0 2006.175.08:17:01.37#ibcon#about to read 6, iclass 16, count 0 2006.175.08:17:01.37#ibcon#read 6, iclass 16, count 0 2006.175.08:17:01.37#ibcon#end of sib2, iclass 16, count 0 2006.175.08:17:01.37#ibcon#*after write, iclass 16, count 0 2006.175.08:17:01.37#ibcon#*before return 0, iclass 16, count 0 2006.175.08:17:01.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:17:01.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:17:01.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:17:01.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:17:01.37$vc4f8/vb=3,4 2006.175.08:17:01.37#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.08:17:01.37#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.08:17:01.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:17:01.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:17:01.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:17:01.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:17:01.43#ibcon#enter wrdev, iclass 18, count 2 2006.175.08:17:01.43#ibcon#first serial, iclass 18, count 2 2006.175.08:17:01.43#ibcon#enter sib2, iclass 18, count 2 2006.175.08:17:01.43#ibcon#flushed, iclass 18, count 2 2006.175.08:17:01.43#ibcon#about to write, iclass 18, count 2 2006.175.08:17:01.43#ibcon#wrote, iclass 18, count 2 2006.175.08:17:01.43#ibcon#about to read 3, iclass 18, count 2 2006.175.08:17:01.45#ibcon#read 3, iclass 18, count 2 2006.175.08:17:01.45#ibcon#about to read 4, iclass 18, count 2 2006.175.08:17:01.45#ibcon#read 4, iclass 18, count 2 2006.175.08:17:01.45#ibcon#about to read 5, iclass 18, count 2 2006.175.08:17:01.45#ibcon#read 5, iclass 18, count 2 2006.175.08:17:01.45#ibcon#about to read 6, iclass 18, count 2 2006.175.08:17:01.45#ibcon#read 6, iclass 18, count 2 2006.175.08:17:01.45#ibcon#end of sib2, iclass 18, count 2 2006.175.08:17:01.45#ibcon#*mode == 0, iclass 18, count 2 2006.175.08:17:01.45#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.08:17:01.45#ibcon#[27=AT03-04\r\n] 2006.175.08:17:01.45#ibcon#*before write, iclass 18, count 2 2006.175.08:17:01.45#ibcon#enter sib2, iclass 18, count 2 2006.175.08:17:01.45#ibcon#flushed, iclass 18, count 2 2006.175.08:17:01.45#ibcon#about to write, iclass 18, count 2 2006.175.08:17:01.45#ibcon#wrote, iclass 18, count 2 2006.175.08:17:01.45#ibcon#about to read 3, iclass 18, count 2 2006.175.08:17:01.48#ibcon#read 3, iclass 18, count 2 2006.175.08:17:01.48#ibcon#about to read 4, iclass 18, count 2 2006.175.08:17:01.48#ibcon#read 4, iclass 18, count 2 2006.175.08:17:01.48#ibcon#about to read 5, iclass 18, count 2 2006.175.08:17:01.48#ibcon#read 5, iclass 18, count 2 2006.175.08:17:01.48#ibcon#about to read 6, iclass 18, count 2 2006.175.08:17:01.48#ibcon#read 6, iclass 18, count 2 2006.175.08:17:01.48#ibcon#end of sib2, iclass 18, count 2 2006.175.08:17:01.48#ibcon#*after write, iclass 18, count 2 2006.175.08:17:01.48#ibcon#*before return 0, iclass 18, count 2 2006.175.08:17:01.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:17:01.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:17:01.48#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.08:17:01.48#ibcon#ireg 7 cls_cnt 0 2006.175.08:17:01.48#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:17:01.60#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:17:01.60#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:17:01.60#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:17:01.60#ibcon#first serial, iclass 18, count 0 2006.175.08:17:01.60#ibcon#enter sib2, iclass 18, count 0 2006.175.08:17:01.60#ibcon#flushed, iclass 18, count 0 2006.175.08:17:01.60#ibcon#about to write, iclass 18, count 0 2006.175.08:17:01.60#ibcon#wrote, iclass 18, count 0 2006.175.08:17:01.60#ibcon#about to read 3, iclass 18, count 0 2006.175.08:17:01.62#ibcon#read 3, iclass 18, count 0 2006.175.08:17:01.62#ibcon#about to read 4, iclass 18, count 0 2006.175.08:17:01.62#ibcon#read 4, iclass 18, count 0 2006.175.08:17:01.62#ibcon#about to read 5, iclass 18, count 0 2006.175.08:17:01.62#ibcon#read 5, iclass 18, count 0 2006.175.08:17:01.62#ibcon#about to read 6, iclass 18, count 0 2006.175.08:17:01.62#ibcon#read 6, iclass 18, count 0 2006.175.08:17:01.62#ibcon#end of sib2, iclass 18, count 0 2006.175.08:17:01.62#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:17:01.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:17:01.62#ibcon#[27=USB\r\n] 2006.175.08:17:01.62#ibcon#*before write, iclass 18, count 0 2006.175.08:17:01.62#ibcon#enter sib2, iclass 18, count 0 2006.175.08:17:01.62#ibcon#flushed, iclass 18, count 0 2006.175.08:17:01.62#ibcon#about to write, iclass 18, count 0 2006.175.08:17:01.62#ibcon#wrote, iclass 18, count 0 2006.175.08:17:01.62#ibcon#about to read 3, iclass 18, count 0 2006.175.08:17:01.65#ibcon#read 3, iclass 18, count 0 2006.175.08:17:01.65#ibcon#about to read 4, iclass 18, count 0 2006.175.08:17:01.65#ibcon#read 4, iclass 18, count 0 2006.175.08:17:01.65#ibcon#about to read 5, iclass 18, count 0 2006.175.08:17:01.65#ibcon#read 5, iclass 18, count 0 2006.175.08:17:01.65#ibcon#about to read 6, iclass 18, count 0 2006.175.08:17:01.65#ibcon#read 6, iclass 18, count 0 2006.175.08:17:01.65#ibcon#end of sib2, iclass 18, count 0 2006.175.08:17:01.65#ibcon#*after write, iclass 18, count 0 2006.175.08:17:01.65#ibcon#*before return 0, iclass 18, count 0 2006.175.08:17:01.65#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:17:01.65#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:17:01.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:17:01.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:17:01.65$vc4f8/vblo=4,712.99 2006.175.08:17:01.65#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.08:17:01.65#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.08:17:01.65#ibcon#ireg 17 cls_cnt 0 2006.175.08:17:01.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:17:01.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:17:01.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:17:01.65#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:17:01.65#ibcon#first serial, iclass 20, count 0 2006.175.08:17:01.65#ibcon#enter sib2, iclass 20, count 0 2006.175.08:17:01.65#ibcon#flushed, iclass 20, count 0 2006.175.08:17:01.65#ibcon#about to write, iclass 20, count 0 2006.175.08:17:01.65#ibcon#wrote, iclass 20, count 0 2006.175.08:17:01.65#ibcon#about to read 3, iclass 20, count 0 2006.175.08:17:01.67#ibcon#read 3, iclass 20, count 0 2006.175.08:17:01.67#ibcon#about to read 4, iclass 20, count 0 2006.175.08:17:01.67#ibcon#read 4, iclass 20, count 0 2006.175.08:17:01.67#ibcon#about to read 5, iclass 20, count 0 2006.175.08:17:01.67#ibcon#read 5, iclass 20, count 0 2006.175.08:17:01.67#ibcon#about to read 6, iclass 20, count 0 2006.175.08:17:01.67#ibcon#read 6, iclass 20, count 0 2006.175.08:17:01.67#ibcon#end of sib2, iclass 20, count 0 2006.175.08:17:01.67#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:17:01.67#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:17:01.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:17:01.67#ibcon#*before write, iclass 20, count 0 2006.175.08:17:01.67#ibcon#enter sib2, iclass 20, count 0 2006.175.08:17:01.67#ibcon#flushed, iclass 20, count 0 2006.175.08:17:01.67#ibcon#about to write, iclass 20, count 0 2006.175.08:17:01.67#ibcon#wrote, iclass 20, count 0 2006.175.08:17:01.67#ibcon#about to read 3, iclass 20, count 0 2006.175.08:17:01.71#ibcon#read 3, iclass 20, count 0 2006.175.08:17:01.71#ibcon#about to read 4, iclass 20, count 0 2006.175.08:17:01.71#ibcon#read 4, iclass 20, count 0 2006.175.08:17:01.71#ibcon#about to read 5, iclass 20, count 0 2006.175.08:17:01.71#ibcon#read 5, iclass 20, count 0 2006.175.08:17:01.71#ibcon#about to read 6, iclass 20, count 0 2006.175.08:17:01.71#ibcon#read 6, iclass 20, count 0 2006.175.08:17:01.71#ibcon#end of sib2, iclass 20, count 0 2006.175.08:17:01.71#ibcon#*after write, iclass 20, count 0 2006.175.08:17:01.71#ibcon#*before return 0, iclass 20, count 0 2006.175.08:17:01.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:17:01.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:17:01.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:17:01.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:17:01.71$vc4f8/vb=4,4 2006.175.08:17:01.71#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.08:17:01.71#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.08:17:01.71#ibcon#ireg 11 cls_cnt 2 2006.175.08:17:01.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:17:01.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:17:01.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:17:01.77#ibcon#enter wrdev, iclass 22, count 2 2006.175.08:17:01.77#ibcon#first serial, iclass 22, count 2 2006.175.08:17:01.77#ibcon#enter sib2, iclass 22, count 2 2006.175.08:17:01.77#ibcon#flushed, iclass 22, count 2 2006.175.08:17:01.77#ibcon#about to write, iclass 22, count 2 2006.175.08:17:01.77#ibcon#wrote, iclass 22, count 2 2006.175.08:17:01.77#ibcon#about to read 3, iclass 22, count 2 2006.175.08:17:01.79#ibcon#read 3, iclass 22, count 2 2006.175.08:17:01.79#ibcon#about to read 4, iclass 22, count 2 2006.175.08:17:01.79#ibcon#read 4, iclass 22, count 2 2006.175.08:17:01.79#ibcon#about to read 5, iclass 22, count 2 2006.175.08:17:01.79#ibcon#read 5, iclass 22, count 2 2006.175.08:17:01.79#ibcon#about to read 6, iclass 22, count 2 2006.175.08:17:01.79#ibcon#read 6, iclass 22, count 2 2006.175.08:17:01.79#ibcon#end of sib2, iclass 22, count 2 2006.175.08:17:01.79#ibcon#*mode == 0, iclass 22, count 2 2006.175.08:17:01.79#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.08:17:01.79#ibcon#[27=AT04-04\r\n] 2006.175.08:17:01.79#ibcon#*before write, iclass 22, count 2 2006.175.08:17:01.79#ibcon#enter sib2, iclass 22, count 2 2006.175.08:17:01.79#ibcon#flushed, iclass 22, count 2 2006.175.08:17:01.79#ibcon#about to write, iclass 22, count 2 2006.175.08:17:01.79#ibcon#wrote, iclass 22, count 2 2006.175.08:17:01.79#ibcon#about to read 3, iclass 22, count 2 2006.175.08:17:01.82#ibcon#read 3, iclass 22, count 2 2006.175.08:17:01.82#ibcon#about to read 4, iclass 22, count 2 2006.175.08:17:01.82#ibcon#read 4, iclass 22, count 2 2006.175.08:17:01.82#ibcon#about to read 5, iclass 22, count 2 2006.175.08:17:01.82#ibcon#read 5, iclass 22, count 2 2006.175.08:17:01.82#ibcon#about to read 6, iclass 22, count 2 2006.175.08:17:01.82#ibcon#read 6, iclass 22, count 2 2006.175.08:17:01.82#ibcon#end of sib2, iclass 22, count 2 2006.175.08:17:01.82#ibcon#*after write, iclass 22, count 2 2006.175.08:17:01.82#ibcon#*before return 0, iclass 22, count 2 2006.175.08:17:01.82#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:17:01.82#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:17:01.82#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.08:17:01.82#ibcon#ireg 7 cls_cnt 0 2006.175.08:17:01.82#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:17:01.94#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:17:01.94#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:17:01.94#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:17:01.94#ibcon#first serial, iclass 22, count 0 2006.175.08:17:01.94#ibcon#enter sib2, iclass 22, count 0 2006.175.08:17:01.94#ibcon#flushed, iclass 22, count 0 2006.175.08:17:01.94#ibcon#about to write, iclass 22, count 0 2006.175.08:17:01.94#ibcon#wrote, iclass 22, count 0 2006.175.08:17:01.94#ibcon#about to read 3, iclass 22, count 0 2006.175.08:17:01.96#ibcon#read 3, iclass 22, count 0 2006.175.08:17:01.96#ibcon#about to read 4, iclass 22, count 0 2006.175.08:17:01.96#ibcon#read 4, iclass 22, count 0 2006.175.08:17:01.96#ibcon#about to read 5, iclass 22, count 0 2006.175.08:17:01.96#ibcon#read 5, iclass 22, count 0 2006.175.08:17:01.96#ibcon#about to read 6, iclass 22, count 0 2006.175.08:17:01.96#ibcon#read 6, iclass 22, count 0 2006.175.08:17:01.96#ibcon#end of sib2, iclass 22, count 0 2006.175.08:17:01.96#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:17:01.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:17:01.96#ibcon#[27=USB\r\n] 2006.175.08:17:01.96#ibcon#*before write, iclass 22, count 0 2006.175.08:17:01.96#ibcon#enter sib2, iclass 22, count 0 2006.175.08:17:01.96#ibcon#flushed, iclass 22, count 0 2006.175.08:17:01.96#ibcon#about to write, iclass 22, count 0 2006.175.08:17:01.96#ibcon#wrote, iclass 22, count 0 2006.175.08:17:01.96#ibcon#about to read 3, iclass 22, count 0 2006.175.08:17:01.99#ibcon#read 3, iclass 22, count 0 2006.175.08:17:01.99#ibcon#about to read 4, iclass 22, count 0 2006.175.08:17:01.99#ibcon#read 4, iclass 22, count 0 2006.175.08:17:01.99#ibcon#about to read 5, iclass 22, count 0 2006.175.08:17:01.99#ibcon#read 5, iclass 22, count 0 2006.175.08:17:01.99#ibcon#about to read 6, iclass 22, count 0 2006.175.08:17:01.99#ibcon#read 6, iclass 22, count 0 2006.175.08:17:01.99#ibcon#end of sib2, iclass 22, count 0 2006.175.08:17:01.99#ibcon#*after write, iclass 22, count 0 2006.175.08:17:01.99#ibcon#*before return 0, iclass 22, count 0 2006.175.08:17:01.99#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:17:01.99#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:17:01.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:17:01.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:17:01.99$vc4f8/vblo=5,744.99 2006.175.08:17:01.99#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.08:17:01.99#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.08:17:01.99#ibcon#ireg 17 cls_cnt 0 2006.175.08:17:01.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:17:01.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:17:01.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:17:01.99#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:17:01.99#ibcon#first serial, iclass 24, count 0 2006.175.08:17:01.99#ibcon#enter sib2, iclass 24, count 0 2006.175.08:17:01.99#ibcon#flushed, iclass 24, count 0 2006.175.08:17:01.99#ibcon#about to write, iclass 24, count 0 2006.175.08:17:01.99#ibcon#wrote, iclass 24, count 0 2006.175.08:17:01.99#ibcon#about to read 3, iclass 24, count 0 2006.175.08:17:02.01#ibcon#read 3, iclass 24, count 0 2006.175.08:17:02.01#ibcon#about to read 4, iclass 24, count 0 2006.175.08:17:02.01#ibcon#read 4, iclass 24, count 0 2006.175.08:17:02.01#ibcon#about to read 5, iclass 24, count 0 2006.175.08:17:02.01#ibcon#read 5, iclass 24, count 0 2006.175.08:17:02.01#ibcon#about to read 6, iclass 24, count 0 2006.175.08:17:02.01#ibcon#read 6, iclass 24, count 0 2006.175.08:17:02.01#ibcon#end of sib2, iclass 24, count 0 2006.175.08:17:02.01#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:17:02.01#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:17:02.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:17:02.01#ibcon#*before write, iclass 24, count 0 2006.175.08:17:02.01#ibcon#enter sib2, iclass 24, count 0 2006.175.08:17:02.01#ibcon#flushed, iclass 24, count 0 2006.175.08:17:02.01#ibcon#about to write, iclass 24, count 0 2006.175.08:17:02.01#ibcon#wrote, iclass 24, count 0 2006.175.08:17:02.01#ibcon#about to read 3, iclass 24, count 0 2006.175.08:17:02.05#ibcon#read 3, iclass 24, count 0 2006.175.08:17:02.05#ibcon#about to read 4, iclass 24, count 0 2006.175.08:17:02.05#ibcon#read 4, iclass 24, count 0 2006.175.08:17:02.05#ibcon#about to read 5, iclass 24, count 0 2006.175.08:17:02.05#ibcon#read 5, iclass 24, count 0 2006.175.08:17:02.05#ibcon#about to read 6, iclass 24, count 0 2006.175.08:17:02.05#ibcon#read 6, iclass 24, count 0 2006.175.08:17:02.05#ibcon#end of sib2, iclass 24, count 0 2006.175.08:17:02.05#ibcon#*after write, iclass 24, count 0 2006.175.08:17:02.05#ibcon#*before return 0, iclass 24, count 0 2006.175.08:17:02.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:17:02.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:17:02.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:17:02.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:17:02.05$vc4f8/vb=5,4 2006.175.08:17:02.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.08:17:02.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.08:17:02.05#ibcon#ireg 11 cls_cnt 2 2006.175.08:17:02.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:17:02.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:17:02.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:17:02.11#ibcon#enter wrdev, iclass 26, count 2 2006.175.08:17:02.11#ibcon#first serial, iclass 26, count 2 2006.175.08:17:02.11#ibcon#enter sib2, iclass 26, count 2 2006.175.08:17:02.11#ibcon#flushed, iclass 26, count 2 2006.175.08:17:02.11#ibcon#about to write, iclass 26, count 2 2006.175.08:17:02.11#ibcon#wrote, iclass 26, count 2 2006.175.08:17:02.11#ibcon#about to read 3, iclass 26, count 2 2006.175.08:17:02.13#ibcon#read 3, iclass 26, count 2 2006.175.08:17:02.13#ibcon#about to read 4, iclass 26, count 2 2006.175.08:17:02.13#ibcon#read 4, iclass 26, count 2 2006.175.08:17:02.13#ibcon#about to read 5, iclass 26, count 2 2006.175.08:17:02.13#ibcon#read 5, iclass 26, count 2 2006.175.08:17:02.13#ibcon#about to read 6, iclass 26, count 2 2006.175.08:17:02.13#ibcon#read 6, iclass 26, count 2 2006.175.08:17:02.13#ibcon#end of sib2, iclass 26, count 2 2006.175.08:17:02.13#ibcon#*mode == 0, iclass 26, count 2 2006.175.08:17:02.13#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.08:17:02.13#ibcon#[27=AT05-04\r\n] 2006.175.08:17:02.13#ibcon#*before write, iclass 26, count 2 2006.175.08:17:02.13#ibcon#enter sib2, iclass 26, count 2 2006.175.08:17:02.13#ibcon#flushed, iclass 26, count 2 2006.175.08:17:02.13#ibcon#about to write, iclass 26, count 2 2006.175.08:17:02.13#ibcon#wrote, iclass 26, count 2 2006.175.08:17:02.13#ibcon#about to read 3, iclass 26, count 2 2006.175.08:17:02.16#ibcon#read 3, iclass 26, count 2 2006.175.08:17:02.16#ibcon#about to read 4, iclass 26, count 2 2006.175.08:17:02.16#ibcon#read 4, iclass 26, count 2 2006.175.08:17:02.16#ibcon#about to read 5, iclass 26, count 2 2006.175.08:17:02.16#ibcon#read 5, iclass 26, count 2 2006.175.08:17:02.16#ibcon#about to read 6, iclass 26, count 2 2006.175.08:17:02.16#ibcon#read 6, iclass 26, count 2 2006.175.08:17:02.16#ibcon#end of sib2, iclass 26, count 2 2006.175.08:17:02.16#ibcon#*after write, iclass 26, count 2 2006.175.08:17:02.16#ibcon#*before return 0, iclass 26, count 2 2006.175.08:17:02.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:17:02.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:17:02.16#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.08:17:02.16#ibcon#ireg 7 cls_cnt 0 2006.175.08:17:02.16#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:17:02.28#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:17:02.28#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:17:02.28#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:17:02.28#ibcon#first serial, iclass 26, count 0 2006.175.08:17:02.28#ibcon#enter sib2, iclass 26, count 0 2006.175.08:17:02.28#ibcon#flushed, iclass 26, count 0 2006.175.08:17:02.28#ibcon#about to write, iclass 26, count 0 2006.175.08:17:02.28#ibcon#wrote, iclass 26, count 0 2006.175.08:17:02.28#ibcon#about to read 3, iclass 26, count 0 2006.175.08:17:02.30#ibcon#read 3, iclass 26, count 0 2006.175.08:17:02.30#ibcon#about to read 4, iclass 26, count 0 2006.175.08:17:02.30#ibcon#read 4, iclass 26, count 0 2006.175.08:17:02.30#ibcon#about to read 5, iclass 26, count 0 2006.175.08:17:02.30#ibcon#read 5, iclass 26, count 0 2006.175.08:17:02.30#ibcon#about to read 6, iclass 26, count 0 2006.175.08:17:02.30#ibcon#read 6, iclass 26, count 0 2006.175.08:17:02.30#ibcon#end of sib2, iclass 26, count 0 2006.175.08:17:02.30#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:17:02.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:17:02.30#ibcon#[27=USB\r\n] 2006.175.08:17:02.30#ibcon#*before write, iclass 26, count 0 2006.175.08:17:02.30#ibcon#enter sib2, iclass 26, count 0 2006.175.08:17:02.30#ibcon#flushed, iclass 26, count 0 2006.175.08:17:02.30#ibcon#about to write, iclass 26, count 0 2006.175.08:17:02.30#ibcon#wrote, iclass 26, count 0 2006.175.08:17:02.30#ibcon#about to read 3, iclass 26, count 0 2006.175.08:17:02.33#ibcon#read 3, iclass 26, count 0 2006.175.08:17:02.33#ibcon#about to read 4, iclass 26, count 0 2006.175.08:17:02.33#ibcon#read 4, iclass 26, count 0 2006.175.08:17:02.33#ibcon#about to read 5, iclass 26, count 0 2006.175.08:17:02.33#ibcon#read 5, iclass 26, count 0 2006.175.08:17:02.33#ibcon#about to read 6, iclass 26, count 0 2006.175.08:17:02.33#ibcon#read 6, iclass 26, count 0 2006.175.08:17:02.33#ibcon#end of sib2, iclass 26, count 0 2006.175.08:17:02.33#ibcon#*after write, iclass 26, count 0 2006.175.08:17:02.33#ibcon#*before return 0, iclass 26, count 0 2006.175.08:17:02.33#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:17:02.33#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:17:02.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:17:02.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:17:02.33$vc4f8/vblo=6,752.99 2006.175.08:17:02.33#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.08:17:02.33#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.08:17:02.33#ibcon#ireg 17 cls_cnt 0 2006.175.08:17:02.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:17:02.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:17:02.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:17:02.33#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:17:02.33#ibcon#first serial, iclass 28, count 0 2006.175.08:17:02.33#ibcon#enter sib2, iclass 28, count 0 2006.175.08:17:02.33#ibcon#flushed, iclass 28, count 0 2006.175.08:17:02.33#ibcon#about to write, iclass 28, count 0 2006.175.08:17:02.33#ibcon#wrote, iclass 28, count 0 2006.175.08:17:02.33#ibcon#about to read 3, iclass 28, count 0 2006.175.08:17:02.35#ibcon#read 3, iclass 28, count 0 2006.175.08:17:02.35#ibcon#about to read 4, iclass 28, count 0 2006.175.08:17:02.35#ibcon#read 4, iclass 28, count 0 2006.175.08:17:02.35#ibcon#about to read 5, iclass 28, count 0 2006.175.08:17:02.35#ibcon#read 5, iclass 28, count 0 2006.175.08:17:02.35#ibcon#about to read 6, iclass 28, count 0 2006.175.08:17:02.35#ibcon#read 6, iclass 28, count 0 2006.175.08:17:02.35#ibcon#end of sib2, iclass 28, count 0 2006.175.08:17:02.35#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:17:02.35#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:17:02.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:17:02.35#ibcon#*before write, iclass 28, count 0 2006.175.08:17:02.35#ibcon#enter sib2, iclass 28, count 0 2006.175.08:17:02.35#ibcon#flushed, iclass 28, count 0 2006.175.08:17:02.35#ibcon#about to write, iclass 28, count 0 2006.175.08:17:02.35#ibcon#wrote, iclass 28, count 0 2006.175.08:17:02.35#ibcon#about to read 3, iclass 28, count 0 2006.175.08:17:02.39#ibcon#read 3, iclass 28, count 0 2006.175.08:17:02.39#ibcon#about to read 4, iclass 28, count 0 2006.175.08:17:02.39#ibcon#read 4, iclass 28, count 0 2006.175.08:17:02.39#ibcon#about to read 5, iclass 28, count 0 2006.175.08:17:02.39#ibcon#read 5, iclass 28, count 0 2006.175.08:17:02.39#ibcon#about to read 6, iclass 28, count 0 2006.175.08:17:02.39#ibcon#read 6, iclass 28, count 0 2006.175.08:17:02.39#ibcon#end of sib2, iclass 28, count 0 2006.175.08:17:02.39#ibcon#*after write, iclass 28, count 0 2006.175.08:17:02.39#ibcon#*before return 0, iclass 28, count 0 2006.175.08:17:02.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:17:02.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:17:02.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:17:02.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:17:02.39$vc4f8/vb=6,4 2006.175.08:17:02.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.08:17:02.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.08:17:02.39#ibcon#ireg 11 cls_cnt 2 2006.175.08:17:02.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:17:02.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:17:02.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:17:02.45#ibcon#enter wrdev, iclass 30, count 2 2006.175.08:17:02.45#ibcon#first serial, iclass 30, count 2 2006.175.08:17:02.45#ibcon#enter sib2, iclass 30, count 2 2006.175.08:17:02.45#ibcon#flushed, iclass 30, count 2 2006.175.08:17:02.45#ibcon#about to write, iclass 30, count 2 2006.175.08:17:02.45#ibcon#wrote, iclass 30, count 2 2006.175.08:17:02.45#ibcon#about to read 3, iclass 30, count 2 2006.175.08:17:02.47#ibcon#read 3, iclass 30, count 2 2006.175.08:17:02.47#ibcon#about to read 4, iclass 30, count 2 2006.175.08:17:02.47#ibcon#read 4, iclass 30, count 2 2006.175.08:17:02.47#ibcon#about to read 5, iclass 30, count 2 2006.175.08:17:02.47#ibcon#read 5, iclass 30, count 2 2006.175.08:17:02.47#ibcon#about to read 6, iclass 30, count 2 2006.175.08:17:02.47#ibcon#read 6, iclass 30, count 2 2006.175.08:17:02.47#ibcon#end of sib2, iclass 30, count 2 2006.175.08:17:02.47#ibcon#*mode == 0, iclass 30, count 2 2006.175.08:17:02.47#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.08:17:02.47#ibcon#[27=AT06-04\r\n] 2006.175.08:17:02.47#ibcon#*before write, iclass 30, count 2 2006.175.08:17:02.47#ibcon#enter sib2, iclass 30, count 2 2006.175.08:17:02.47#ibcon#flushed, iclass 30, count 2 2006.175.08:17:02.47#ibcon#about to write, iclass 30, count 2 2006.175.08:17:02.47#ibcon#wrote, iclass 30, count 2 2006.175.08:17:02.47#ibcon#about to read 3, iclass 30, count 2 2006.175.08:17:02.50#ibcon#read 3, iclass 30, count 2 2006.175.08:17:02.50#ibcon#about to read 4, iclass 30, count 2 2006.175.08:17:02.50#ibcon#read 4, iclass 30, count 2 2006.175.08:17:02.50#ibcon#about to read 5, iclass 30, count 2 2006.175.08:17:02.50#ibcon#read 5, iclass 30, count 2 2006.175.08:17:02.50#ibcon#about to read 6, iclass 30, count 2 2006.175.08:17:02.50#ibcon#read 6, iclass 30, count 2 2006.175.08:17:02.50#ibcon#end of sib2, iclass 30, count 2 2006.175.08:17:02.50#ibcon#*after write, iclass 30, count 2 2006.175.08:17:02.50#ibcon#*before return 0, iclass 30, count 2 2006.175.08:17:02.50#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:17:02.50#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:17:02.50#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.08:17:02.50#ibcon#ireg 7 cls_cnt 0 2006.175.08:17:02.50#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:17:02.62#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:17:02.62#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:17:02.62#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:17:02.62#ibcon#first serial, iclass 30, count 0 2006.175.08:17:02.62#ibcon#enter sib2, iclass 30, count 0 2006.175.08:17:02.62#ibcon#flushed, iclass 30, count 0 2006.175.08:17:02.62#ibcon#about to write, iclass 30, count 0 2006.175.08:17:02.62#ibcon#wrote, iclass 30, count 0 2006.175.08:17:02.62#ibcon#about to read 3, iclass 30, count 0 2006.175.08:17:02.64#ibcon#read 3, iclass 30, count 0 2006.175.08:17:02.64#ibcon#about to read 4, iclass 30, count 0 2006.175.08:17:02.64#ibcon#read 4, iclass 30, count 0 2006.175.08:17:02.64#ibcon#about to read 5, iclass 30, count 0 2006.175.08:17:02.64#ibcon#read 5, iclass 30, count 0 2006.175.08:17:02.64#ibcon#about to read 6, iclass 30, count 0 2006.175.08:17:02.64#ibcon#read 6, iclass 30, count 0 2006.175.08:17:02.64#ibcon#end of sib2, iclass 30, count 0 2006.175.08:17:02.64#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:17:02.64#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:17:02.64#ibcon#[27=USB\r\n] 2006.175.08:17:02.64#ibcon#*before write, iclass 30, count 0 2006.175.08:17:02.64#ibcon#enter sib2, iclass 30, count 0 2006.175.08:17:02.64#ibcon#flushed, iclass 30, count 0 2006.175.08:17:02.64#ibcon#about to write, iclass 30, count 0 2006.175.08:17:02.64#ibcon#wrote, iclass 30, count 0 2006.175.08:17:02.64#ibcon#about to read 3, iclass 30, count 0 2006.175.08:17:02.67#ibcon#read 3, iclass 30, count 0 2006.175.08:17:02.67#ibcon#about to read 4, iclass 30, count 0 2006.175.08:17:02.67#ibcon#read 4, iclass 30, count 0 2006.175.08:17:02.67#ibcon#about to read 5, iclass 30, count 0 2006.175.08:17:02.67#ibcon#read 5, iclass 30, count 0 2006.175.08:17:02.67#ibcon#about to read 6, iclass 30, count 0 2006.175.08:17:02.67#ibcon#read 6, iclass 30, count 0 2006.175.08:17:02.67#ibcon#end of sib2, iclass 30, count 0 2006.175.08:17:02.67#ibcon#*after write, iclass 30, count 0 2006.175.08:17:02.67#ibcon#*before return 0, iclass 30, count 0 2006.175.08:17:02.67#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:17:02.67#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:17:02.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:17:02.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:17:02.67$vc4f8/vabw=wide 2006.175.08:17:02.67#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.08:17:02.67#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.08:17:02.67#ibcon#ireg 8 cls_cnt 0 2006.175.08:17:02.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:17:02.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:17:02.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:17:02.67#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:17:02.67#ibcon#first serial, iclass 32, count 0 2006.175.08:17:02.67#ibcon#enter sib2, iclass 32, count 0 2006.175.08:17:02.67#ibcon#flushed, iclass 32, count 0 2006.175.08:17:02.67#ibcon#about to write, iclass 32, count 0 2006.175.08:17:02.67#ibcon#wrote, iclass 32, count 0 2006.175.08:17:02.67#ibcon#about to read 3, iclass 32, count 0 2006.175.08:17:02.69#ibcon#read 3, iclass 32, count 0 2006.175.08:17:02.69#ibcon#about to read 4, iclass 32, count 0 2006.175.08:17:02.69#ibcon#read 4, iclass 32, count 0 2006.175.08:17:02.69#ibcon#about to read 5, iclass 32, count 0 2006.175.08:17:02.69#ibcon#read 5, iclass 32, count 0 2006.175.08:17:02.69#ibcon#about to read 6, iclass 32, count 0 2006.175.08:17:02.69#ibcon#read 6, iclass 32, count 0 2006.175.08:17:02.69#ibcon#end of sib2, iclass 32, count 0 2006.175.08:17:02.69#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:17:02.69#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:17:02.69#ibcon#[25=BW32\r\n] 2006.175.08:17:02.69#ibcon#*before write, iclass 32, count 0 2006.175.08:17:02.69#ibcon#enter sib2, iclass 32, count 0 2006.175.08:17:02.69#ibcon#flushed, iclass 32, count 0 2006.175.08:17:02.69#ibcon#about to write, iclass 32, count 0 2006.175.08:17:02.69#ibcon#wrote, iclass 32, count 0 2006.175.08:17:02.69#ibcon#about to read 3, iclass 32, count 0 2006.175.08:17:02.72#ibcon#read 3, iclass 32, count 0 2006.175.08:17:02.72#ibcon#about to read 4, iclass 32, count 0 2006.175.08:17:02.72#ibcon#read 4, iclass 32, count 0 2006.175.08:17:02.72#ibcon#about to read 5, iclass 32, count 0 2006.175.08:17:02.72#ibcon#read 5, iclass 32, count 0 2006.175.08:17:02.72#ibcon#about to read 6, iclass 32, count 0 2006.175.08:17:02.72#ibcon#read 6, iclass 32, count 0 2006.175.08:17:02.72#ibcon#end of sib2, iclass 32, count 0 2006.175.08:17:02.72#ibcon#*after write, iclass 32, count 0 2006.175.08:17:02.72#ibcon#*before return 0, iclass 32, count 0 2006.175.08:17:02.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:17:02.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:17:02.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:17:02.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:17:02.72$vc4f8/vbbw=wide 2006.175.08:17:02.72#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.08:17:02.72#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.08:17:02.72#ibcon#ireg 8 cls_cnt 0 2006.175.08:17:02.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:17:02.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:17:02.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:17:02.79#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:17:02.79#ibcon#first serial, iclass 34, count 0 2006.175.08:17:02.79#ibcon#enter sib2, iclass 34, count 0 2006.175.08:17:02.79#ibcon#flushed, iclass 34, count 0 2006.175.08:17:02.79#ibcon#about to write, iclass 34, count 0 2006.175.08:17:02.79#ibcon#wrote, iclass 34, count 0 2006.175.08:17:02.79#ibcon#about to read 3, iclass 34, count 0 2006.175.08:17:02.81#ibcon#read 3, iclass 34, count 0 2006.175.08:17:02.81#ibcon#about to read 4, iclass 34, count 0 2006.175.08:17:02.81#ibcon#read 4, iclass 34, count 0 2006.175.08:17:02.81#ibcon#about to read 5, iclass 34, count 0 2006.175.08:17:02.81#ibcon#read 5, iclass 34, count 0 2006.175.08:17:02.81#ibcon#about to read 6, iclass 34, count 0 2006.175.08:17:02.81#ibcon#read 6, iclass 34, count 0 2006.175.08:17:02.81#ibcon#end of sib2, iclass 34, count 0 2006.175.08:17:02.81#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:17:02.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:17:02.81#ibcon#[27=BW32\r\n] 2006.175.08:17:02.81#ibcon#*before write, iclass 34, count 0 2006.175.08:17:02.81#ibcon#enter sib2, iclass 34, count 0 2006.175.08:17:02.81#ibcon#flushed, iclass 34, count 0 2006.175.08:17:02.81#ibcon#about to write, iclass 34, count 0 2006.175.08:17:02.81#ibcon#wrote, iclass 34, count 0 2006.175.08:17:02.81#ibcon#about to read 3, iclass 34, count 0 2006.175.08:17:02.84#ibcon#read 3, iclass 34, count 0 2006.175.08:17:02.84#ibcon#about to read 4, iclass 34, count 0 2006.175.08:17:02.84#ibcon#read 4, iclass 34, count 0 2006.175.08:17:02.84#ibcon#about to read 5, iclass 34, count 0 2006.175.08:17:02.84#ibcon#read 5, iclass 34, count 0 2006.175.08:17:02.84#ibcon#about to read 6, iclass 34, count 0 2006.175.08:17:02.84#ibcon#read 6, iclass 34, count 0 2006.175.08:17:02.84#ibcon#end of sib2, iclass 34, count 0 2006.175.08:17:02.84#ibcon#*after write, iclass 34, count 0 2006.175.08:17:02.84#ibcon#*before return 0, iclass 34, count 0 2006.175.08:17:02.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:17:02.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:17:02.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:17:02.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:17:02.84$4f8m12a/ifd4f 2006.175.08:17:02.84$ifd4f/lo= 2006.175.08:17:02.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:17:02.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:17:02.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:17:02.84$ifd4f/patch= 2006.175.08:17:02.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:17:02.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:17:02.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:17:02.84$4f8m12a/"form=m,16.000,1:2 2006.175.08:17:02.84$4f8m12a/"tpicd 2006.175.08:17:02.84$4f8m12a/echo=off 2006.175.08:17:02.84$4f8m12a/xlog=off 2006.175.08:17:02.84:!2006.175.08:17:30 2006.175.08:17:13.14#trakl#Source acquired 2006.175.08:17:15.14#flagr#flagr/antenna,acquired 2006.175.08:17:30.00:preob 2006.175.08:17:31.14/onsource/TRACKING 2006.175.08:17:31.14:!2006.175.08:17:40 2006.175.08:17:40.00:data_valid=on 2006.175.08:17:40.00:midob 2006.175.08:17:40.14/onsource/TRACKING 2006.175.08:17:40.14/wx/25.73,1007.4,72 2006.175.08:17:40.25/cable/+6.4794E-03 2006.175.08:17:41.34/va/01,08,usb,yes,28,30 2006.175.08:17:41.34/va/02,07,usb,yes,28,29 2006.175.08:17:41.34/va/03,06,usb,yes,30,30 2006.175.08:17:41.34/va/04,07,usb,yes,29,31 2006.175.08:17:41.34/va/05,07,usb,yes,29,31 2006.175.08:17:41.34/va/06,06,usb,yes,29,28 2006.175.08:17:41.34/va/07,06,usb,yes,29,29 2006.175.08:17:41.34/va/08,06,usb,yes,31,31 2006.175.08:17:41.57/valo/01,532.99,yes,locked 2006.175.08:17:41.57/valo/02,572.99,yes,locked 2006.175.08:17:41.57/valo/03,672.99,yes,locked 2006.175.08:17:41.57/valo/04,832.99,yes,locked 2006.175.08:17:41.57/valo/05,652.99,yes,locked 2006.175.08:17:41.57/valo/06,772.99,yes,locked 2006.175.08:17:41.57/valo/07,832.99,yes,locked 2006.175.08:17:41.57/valo/08,852.99,yes,locked 2006.175.08:17:42.66/vb/01,04,usb,yes,29,27 2006.175.08:17:42.66/vb/02,04,usb,yes,30,32 2006.175.08:17:42.66/vb/03,04,usb,yes,27,30 2006.175.08:17:42.66/vb/04,04,usb,yes,28,28 2006.175.08:17:42.66/vb/05,04,usb,yes,26,30 2006.175.08:17:42.66/vb/06,04,usb,yes,27,30 2006.175.08:17:42.66/vb/07,04,usb,yes,29,29 2006.175.08:17:42.66/vb/08,04,usb,yes,27,30 2006.175.08:17:42.90/vblo/01,632.99,yes,locked 2006.175.08:17:42.90/vblo/02,640.99,yes,locked 2006.175.08:17:42.90/vblo/03,656.99,yes,locked 2006.175.08:17:42.90/vblo/04,712.99,yes,locked 2006.175.08:17:42.90/vblo/05,744.99,yes,locked 2006.175.08:17:42.90/vblo/06,752.99,yes,locked 2006.175.08:17:42.90/vblo/07,734.99,yes,locked 2006.175.08:17:42.90/vblo/08,744.99,yes,locked 2006.175.08:17:43.05/vabw/8 2006.175.08:17:43.20/vbbw/8 2006.175.08:17:43.29/xfe/off,on,14.7 2006.175.08:17:43.66/ifatt/23,28,28,28 2006.175.08:17:44.08/fmout-gps/S +3.81E-07 2006.175.08:17:44.12:!2006.175.08:18:40 2006.175.08:18:40.00:data_valid=off 2006.175.08:18:40.00:postob 2006.175.08:18:40.17/cable/+6.4781E-03 2006.175.08:18:40.17/wx/25.72,1007.4,70 2006.175.08:18:41.08/fmout-gps/S +3.80E-07 2006.175.08:18:41.08:scan_name=175-0820,k06175,60 2006.175.08:18:41.09:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.175.08:18:41.14#flagr#flagr/antenna,new-source 2006.175.08:18:42.14:checkk5 2006.175.08:18:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:18:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:18:46.28/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:18:46.67/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:18:47.04/chk_obsdata//k5ts1/T1750817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:18:47.42/chk_obsdata//k5ts2/T1750817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:18:47.78/chk_obsdata//k5ts3/T1750817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:18:48.16/chk_obsdata//k5ts4/T1750817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:18:48.87/k5log//k5ts1_log_newline 2006.175.08:18:49.57/k5log//k5ts2_log_newline 2006.175.08:18:50.28/k5log//k5ts3_log_newline 2006.175.08:18:50.97/k5log//k5ts4_log_newline 2006.175.08:18:51.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:18:51.00:4f8m12a=3 2006.175.08:18:51.00$4f8m12a/echo=on 2006.175.08:18:51.00$4f8m12a/pcalon 2006.175.08:18:51.00$pcalon/"no phase cal control is implemented here 2006.175.08:18:51.00$4f8m12a/"tpicd=stop 2006.175.08:18:51.00$4f8m12a/vc4f8 2006.175.08:18:51.00$vc4f8/valo=1,532.99 2006.175.08:18:51.00#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.08:18:51.00#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.08:18:51.00#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:51.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:51.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:51.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:51.00#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:18:51.00#ibcon#first serial, iclass 36, count 0 2006.175.08:18:51.00#ibcon#enter sib2, iclass 36, count 0 2006.175.08:18:51.00#ibcon#flushed, iclass 36, count 0 2006.175.08:18:51.00#ibcon#about to write, iclass 36, count 0 2006.175.08:18:51.00#ibcon#wrote, iclass 36, count 0 2006.175.08:18:51.00#ibcon#about to read 3, iclass 36, count 0 2006.175.08:18:51.04#ibcon#read 3, iclass 36, count 0 2006.175.08:18:51.04#ibcon#about to read 4, iclass 36, count 0 2006.175.08:18:51.05#ibcon#read 4, iclass 36, count 0 2006.175.08:18:51.05#ibcon#about to read 5, iclass 36, count 0 2006.175.08:18:51.05#ibcon#read 5, iclass 36, count 0 2006.175.08:18:51.05#ibcon#about to read 6, iclass 36, count 0 2006.175.08:18:51.05#ibcon#read 6, iclass 36, count 0 2006.175.08:18:51.05#ibcon#end of sib2, iclass 36, count 0 2006.175.08:18:51.05#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:18:51.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:18:51.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:18:51.05#ibcon#*before write, iclass 36, count 0 2006.175.08:18:51.05#ibcon#enter sib2, iclass 36, count 0 2006.175.08:18:51.05#ibcon#flushed, iclass 36, count 0 2006.175.08:18:51.05#ibcon#about to write, iclass 36, count 0 2006.175.08:18:51.05#ibcon#wrote, iclass 36, count 0 2006.175.08:18:51.05#ibcon#about to read 3, iclass 36, count 0 2006.175.08:18:51.09#ibcon#read 3, iclass 36, count 0 2006.175.08:18:51.09#ibcon#about to read 4, iclass 36, count 0 2006.175.08:18:51.09#ibcon#read 4, iclass 36, count 0 2006.175.08:18:51.09#ibcon#about to read 5, iclass 36, count 0 2006.175.08:18:51.09#ibcon#read 5, iclass 36, count 0 2006.175.08:18:51.09#ibcon#about to read 6, iclass 36, count 0 2006.175.08:18:51.09#ibcon#read 6, iclass 36, count 0 2006.175.08:18:51.09#ibcon#end of sib2, iclass 36, count 0 2006.175.08:18:51.09#ibcon#*after write, iclass 36, count 0 2006.175.08:18:51.09#ibcon#*before return 0, iclass 36, count 0 2006.175.08:18:51.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:51.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:51.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:18:51.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:18:51.09$vc4f8/va=1,8 2006.175.08:18:51.09#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.175.08:18:51.09#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.175.08:18:51.09#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:51.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:51.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:51.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:51.09#ibcon#enter wrdev, iclass 38, count 2 2006.175.08:18:51.09#ibcon#first serial, iclass 38, count 2 2006.175.08:18:51.09#ibcon#enter sib2, iclass 38, count 2 2006.175.08:18:51.09#ibcon#flushed, iclass 38, count 2 2006.175.08:18:51.09#ibcon#about to write, iclass 38, count 2 2006.175.08:18:51.09#ibcon#wrote, iclass 38, count 2 2006.175.08:18:51.09#ibcon#about to read 3, iclass 38, count 2 2006.175.08:18:51.12#ibcon#read 3, iclass 38, count 2 2006.175.08:18:51.12#ibcon#about to read 4, iclass 38, count 2 2006.175.08:18:51.12#ibcon#read 4, iclass 38, count 2 2006.175.08:18:51.12#ibcon#about to read 5, iclass 38, count 2 2006.175.08:18:51.12#ibcon#read 5, iclass 38, count 2 2006.175.08:18:51.12#ibcon#about to read 6, iclass 38, count 2 2006.175.08:18:51.12#ibcon#read 6, iclass 38, count 2 2006.175.08:18:51.12#ibcon#end of sib2, iclass 38, count 2 2006.175.08:18:51.12#ibcon#*mode == 0, iclass 38, count 2 2006.175.08:18:51.12#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.175.08:18:51.12#ibcon#[25=AT01-08\r\n] 2006.175.08:18:51.12#ibcon#*before write, iclass 38, count 2 2006.175.08:18:51.12#ibcon#enter sib2, iclass 38, count 2 2006.175.08:18:51.12#ibcon#flushed, iclass 38, count 2 2006.175.08:18:51.12#ibcon#about to write, iclass 38, count 2 2006.175.08:18:51.12#ibcon#wrote, iclass 38, count 2 2006.175.08:18:51.12#ibcon#about to read 3, iclass 38, count 2 2006.175.08:18:51.15#ibcon#read 3, iclass 38, count 2 2006.175.08:18:51.15#ibcon#about to read 4, iclass 38, count 2 2006.175.08:18:51.15#ibcon#read 4, iclass 38, count 2 2006.175.08:18:51.15#ibcon#about to read 5, iclass 38, count 2 2006.175.08:18:51.15#ibcon#read 5, iclass 38, count 2 2006.175.08:18:51.15#ibcon#about to read 6, iclass 38, count 2 2006.175.08:18:51.15#ibcon#read 6, iclass 38, count 2 2006.175.08:18:51.15#ibcon#end of sib2, iclass 38, count 2 2006.175.08:18:51.15#ibcon#*after write, iclass 38, count 2 2006.175.08:18:51.15#ibcon#*before return 0, iclass 38, count 2 2006.175.08:18:51.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:51.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:51.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.175.08:18:51.15#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:51.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:51.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:51.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:51.27#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:18:51.27#ibcon#first serial, iclass 38, count 0 2006.175.08:18:51.27#ibcon#enter sib2, iclass 38, count 0 2006.175.08:18:51.27#ibcon#flushed, iclass 38, count 0 2006.175.08:18:51.27#ibcon#about to write, iclass 38, count 0 2006.175.08:18:51.27#ibcon#wrote, iclass 38, count 0 2006.175.08:18:51.27#ibcon#about to read 3, iclass 38, count 0 2006.175.08:18:51.29#ibcon#read 3, iclass 38, count 0 2006.175.08:18:51.29#ibcon#about to read 4, iclass 38, count 0 2006.175.08:18:51.29#ibcon#read 4, iclass 38, count 0 2006.175.08:18:51.29#ibcon#about to read 5, iclass 38, count 0 2006.175.08:18:51.29#ibcon#read 5, iclass 38, count 0 2006.175.08:18:51.29#ibcon#about to read 6, iclass 38, count 0 2006.175.08:18:51.29#ibcon#read 6, iclass 38, count 0 2006.175.08:18:51.29#ibcon#end of sib2, iclass 38, count 0 2006.175.08:18:51.29#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:18:51.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:18:51.29#ibcon#[25=USB\r\n] 2006.175.08:18:51.29#ibcon#*before write, iclass 38, count 0 2006.175.08:18:51.29#ibcon#enter sib2, iclass 38, count 0 2006.175.08:18:51.29#ibcon#flushed, iclass 38, count 0 2006.175.08:18:51.29#ibcon#about to write, iclass 38, count 0 2006.175.08:18:51.29#ibcon#wrote, iclass 38, count 0 2006.175.08:18:51.29#ibcon#about to read 3, iclass 38, count 0 2006.175.08:18:51.32#ibcon#read 3, iclass 38, count 0 2006.175.08:18:51.32#ibcon#about to read 4, iclass 38, count 0 2006.175.08:18:51.32#ibcon#read 4, iclass 38, count 0 2006.175.08:18:51.32#ibcon#about to read 5, iclass 38, count 0 2006.175.08:18:51.32#ibcon#read 5, iclass 38, count 0 2006.175.08:18:51.32#ibcon#about to read 6, iclass 38, count 0 2006.175.08:18:51.32#ibcon#read 6, iclass 38, count 0 2006.175.08:18:51.32#ibcon#end of sib2, iclass 38, count 0 2006.175.08:18:51.32#ibcon#*after write, iclass 38, count 0 2006.175.08:18:51.32#ibcon#*before return 0, iclass 38, count 0 2006.175.08:18:51.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:51.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:51.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:18:51.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:18:51.32$vc4f8/valo=2,572.99 2006.175.08:18:51.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.08:18:51.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.08:18:51.32#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:51.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:51.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:51.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:51.32#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:18:51.32#ibcon#first serial, iclass 40, count 0 2006.175.08:18:51.32#ibcon#enter sib2, iclass 40, count 0 2006.175.08:18:51.32#ibcon#flushed, iclass 40, count 0 2006.175.08:18:51.32#ibcon#about to write, iclass 40, count 0 2006.175.08:18:51.32#ibcon#wrote, iclass 40, count 0 2006.175.08:18:51.32#ibcon#about to read 3, iclass 40, count 0 2006.175.08:18:51.34#ibcon#read 3, iclass 40, count 0 2006.175.08:18:51.34#ibcon#about to read 4, iclass 40, count 0 2006.175.08:18:51.34#ibcon#read 4, iclass 40, count 0 2006.175.08:18:51.34#ibcon#about to read 5, iclass 40, count 0 2006.175.08:18:51.34#ibcon#read 5, iclass 40, count 0 2006.175.08:18:51.34#ibcon#about to read 6, iclass 40, count 0 2006.175.08:18:51.34#ibcon#read 6, iclass 40, count 0 2006.175.08:18:51.34#ibcon#end of sib2, iclass 40, count 0 2006.175.08:18:51.34#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:18:51.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:18:51.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:18:51.34#ibcon#*before write, iclass 40, count 0 2006.175.08:18:51.34#ibcon#enter sib2, iclass 40, count 0 2006.175.08:18:51.34#ibcon#flushed, iclass 40, count 0 2006.175.08:18:51.34#ibcon#about to write, iclass 40, count 0 2006.175.08:18:51.34#ibcon#wrote, iclass 40, count 0 2006.175.08:18:51.34#ibcon#about to read 3, iclass 40, count 0 2006.175.08:18:51.38#ibcon#read 3, iclass 40, count 0 2006.175.08:18:51.38#ibcon#about to read 4, iclass 40, count 0 2006.175.08:18:51.38#ibcon#read 4, iclass 40, count 0 2006.175.08:18:51.38#ibcon#about to read 5, iclass 40, count 0 2006.175.08:18:51.38#ibcon#read 5, iclass 40, count 0 2006.175.08:18:51.38#ibcon#about to read 6, iclass 40, count 0 2006.175.08:18:51.38#ibcon#read 6, iclass 40, count 0 2006.175.08:18:51.38#ibcon#end of sib2, iclass 40, count 0 2006.175.08:18:51.38#ibcon#*after write, iclass 40, count 0 2006.175.08:18:51.38#ibcon#*before return 0, iclass 40, count 0 2006.175.08:18:51.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:51.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:51.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:18:51.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:18:51.38$vc4f8/va=2,7 2006.175.08:18:51.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.175.08:18:51.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.175.08:18:51.38#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:51.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:51.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:51.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:51.44#ibcon#enter wrdev, iclass 4, count 2 2006.175.08:18:51.44#ibcon#first serial, iclass 4, count 2 2006.175.08:18:51.44#ibcon#enter sib2, iclass 4, count 2 2006.175.08:18:51.44#ibcon#flushed, iclass 4, count 2 2006.175.08:18:51.44#ibcon#about to write, iclass 4, count 2 2006.175.08:18:51.44#ibcon#wrote, iclass 4, count 2 2006.175.08:18:51.44#ibcon#about to read 3, iclass 4, count 2 2006.175.08:18:51.46#ibcon#read 3, iclass 4, count 2 2006.175.08:18:51.46#ibcon#about to read 4, iclass 4, count 2 2006.175.08:18:51.46#ibcon#read 4, iclass 4, count 2 2006.175.08:18:51.46#ibcon#about to read 5, iclass 4, count 2 2006.175.08:18:51.46#ibcon#read 5, iclass 4, count 2 2006.175.08:18:51.46#ibcon#about to read 6, iclass 4, count 2 2006.175.08:18:51.46#ibcon#read 6, iclass 4, count 2 2006.175.08:18:51.46#ibcon#end of sib2, iclass 4, count 2 2006.175.08:18:51.46#ibcon#*mode == 0, iclass 4, count 2 2006.175.08:18:51.46#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.175.08:18:51.46#ibcon#[25=AT02-07\r\n] 2006.175.08:18:51.46#ibcon#*before write, iclass 4, count 2 2006.175.08:18:51.46#ibcon#enter sib2, iclass 4, count 2 2006.175.08:18:51.46#ibcon#flushed, iclass 4, count 2 2006.175.08:18:51.46#ibcon#about to write, iclass 4, count 2 2006.175.08:18:51.46#ibcon#wrote, iclass 4, count 2 2006.175.08:18:51.46#ibcon#about to read 3, iclass 4, count 2 2006.175.08:18:51.49#ibcon#read 3, iclass 4, count 2 2006.175.08:18:51.49#ibcon#about to read 4, iclass 4, count 2 2006.175.08:18:51.49#ibcon#read 4, iclass 4, count 2 2006.175.08:18:51.49#ibcon#about to read 5, iclass 4, count 2 2006.175.08:18:51.49#ibcon#read 5, iclass 4, count 2 2006.175.08:18:51.49#ibcon#about to read 6, iclass 4, count 2 2006.175.08:18:51.49#ibcon#read 6, iclass 4, count 2 2006.175.08:18:51.49#ibcon#end of sib2, iclass 4, count 2 2006.175.08:18:51.49#ibcon#*after write, iclass 4, count 2 2006.175.08:18:51.49#ibcon#*before return 0, iclass 4, count 2 2006.175.08:18:51.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:51.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:51.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.175.08:18:51.49#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:51.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:51.58#abcon#<5=/05 4.3 7.2 25.72 701007.4\r\n> 2006.175.08:18:51.60#abcon#{5=INTERFACE CLEAR} 2006.175.08:18:51.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:51.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:51.61#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:18:51.61#ibcon#first serial, iclass 4, count 0 2006.175.08:18:51.61#ibcon#enter sib2, iclass 4, count 0 2006.175.08:18:51.61#ibcon#flushed, iclass 4, count 0 2006.175.08:18:51.61#ibcon#about to write, iclass 4, count 0 2006.175.08:18:51.61#ibcon#wrote, iclass 4, count 0 2006.175.08:18:51.61#ibcon#about to read 3, iclass 4, count 0 2006.175.08:18:51.63#ibcon#read 3, iclass 4, count 0 2006.175.08:18:51.63#ibcon#about to read 4, iclass 4, count 0 2006.175.08:18:51.63#ibcon#read 4, iclass 4, count 0 2006.175.08:18:51.63#ibcon#about to read 5, iclass 4, count 0 2006.175.08:18:51.63#ibcon#read 5, iclass 4, count 0 2006.175.08:18:51.63#ibcon#about to read 6, iclass 4, count 0 2006.175.08:18:51.63#ibcon#read 6, iclass 4, count 0 2006.175.08:18:51.63#ibcon#end of sib2, iclass 4, count 0 2006.175.08:18:51.63#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:18:51.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:18:51.63#ibcon#[25=USB\r\n] 2006.175.08:18:51.63#ibcon#*before write, iclass 4, count 0 2006.175.08:18:51.63#ibcon#enter sib2, iclass 4, count 0 2006.175.08:18:51.63#ibcon#flushed, iclass 4, count 0 2006.175.08:18:51.63#ibcon#about to write, iclass 4, count 0 2006.175.08:18:51.63#ibcon#wrote, iclass 4, count 0 2006.175.08:18:51.63#ibcon#about to read 3, iclass 4, count 0 2006.175.08:18:51.66#ibcon#read 3, iclass 4, count 0 2006.175.08:18:51.66#ibcon#about to read 4, iclass 4, count 0 2006.175.08:18:51.66#ibcon#read 4, iclass 4, count 0 2006.175.08:18:51.66#ibcon#about to read 5, iclass 4, count 0 2006.175.08:18:51.66#ibcon#read 5, iclass 4, count 0 2006.175.08:18:51.66#ibcon#about to read 6, iclass 4, count 0 2006.175.08:18:51.66#ibcon#read 6, iclass 4, count 0 2006.175.08:18:51.66#ibcon#end of sib2, iclass 4, count 0 2006.175.08:18:51.66#ibcon#*after write, iclass 4, count 0 2006.175.08:18:51.66#ibcon#*before return 0, iclass 4, count 0 2006.175.08:18:51.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:51.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:51.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:18:51.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:18:51.66$vc4f8/valo=3,672.99 2006.175.08:18:51.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.08:18:51.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.08:18:51.66#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:51.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:51.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:51.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:51.66#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:18:51.66#ibcon#first serial, iclass 12, count 0 2006.175.08:18:51.66#ibcon#enter sib2, iclass 12, count 0 2006.175.08:18:51.66#ibcon#flushed, iclass 12, count 0 2006.175.08:18:51.66#ibcon#about to write, iclass 12, count 0 2006.175.08:18:51.66#ibcon#wrote, iclass 12, count 0 2006.175.08:18:51.66#ibcon#about to read 3, iclass 12, count 0 2006.175.08:18:51.67#abcon#[5=S1D000X0/0*\r\n] 2006.175.08:18:51.68#ibcon#read 3, iclass 12, count 0 2006.175.08:18:51.68#ibcon#about to read 4, iclass 12, count 0 2006.175.08:18:51.68#ibcon#read 4, iclass 12, count 0 2006.175.08:18:51.68#ibcon#about to read 5, iclass 12, count 0 2006.175.08:18:51.68#ibcon#read 5, iclass 12, count 0 2006.175.08:18:51.68#ibcon#about to read 6, iclass 12, count 0 2006.175.08:18:51.68#ibcon#read 6, iclass 12, count 0 2006.175.08:18:51.68#ibcon#end of sib2, iclass 12, count 0 2006.175.08:18:51.68#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:18:51.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:18:51.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:18:51.68#ibcon#*before write, iclass 12, count 0 2006.175.08:18:51.68#ibcon#enter sib2, iclass 12, count 0 2006.175.08:18:51.68#ibcon#flushed, iclass 12, count 0 2006.175.08:18:51.68#ibcon#about to write, iclass 12, count 0 2006.175.08:18:51.68#ibcon#wrote, iclass 12, count 0 2006.175.08:18:51.68#ibcon#about to read 3, iclass 12, count 0 2006.175.08:18:51.72#ibcon#read 3, iclass 12, count 0 2006.175.08:18:51.72#ibcon#about to read 4, iclass 12, count 0 2006.175.08:18:51.72#ibcon#read 4, iclass 12, count 0 2006.175.08:18:51.72#ibcon#about to read 5, iclass 12, count 0 2006.175.08:18:51.72#ibcon#read 5, iclass 12, count 0 2006.175.08:18:51.72#ibcon#about to read 6, iclass 12, count 0 2006.175.08:18:51.72#ibcon#read 6, iclass 12, count 0 2006.175.08:18:51.72#ibcon#end of sib2, iclass 12, count 0 2006.175.08:18:51.72#ibcon#*after write, iclass 12, count 0 2006.175.08:18:51.72#ibcon#*before return 0, iclass 12, count 0 2006.175.08:18:51.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:51.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:51.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:18:51.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:18:51.72$vc4f8/va=3,6 2006.175.08:18:51.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.08:18:51.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.08:18:51.72#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:51.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:51.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:51.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:51.78#ibcon#enter wrdev, iclass 14, count 2 2006.175.08:18:51.78#ibcon#first serial, iclass 14, count 2 2006.175.08:18:51.78#ibcon#enter sib2, iclass 14, count 2 2006.175.08:18:51.78#ibcon#flushed, iclass 14, count 2 2006.175.08:18:51.78#ibcon#about to write, iclass 14, count 2 2006.175.08:18:51.78#ibcon#wrote, iclass 14, count 2 2006.175.08:18:51.78#ibcon#about to read 3, iclass 14, count 2 2006.175.08:18:51.80#ibcon#read 3, iclass 14, count 2 2006.175.08:18:51.80#ibcon#about to read 4, iclass 14, count 2 2006.175.08:18:51.80#ibcon#read 4, iclass 14, count 2 2006.175.08:18:51.80#ibcon#about to read 5, iclass 14, count 2 2006.175.08:18:51.80#ibcon#read 5, iclass 14, count 2 2006.175.08:18:51.80#ibcon#about to read 6, iclass 14, count 2 2006.175.08:18:51.80#ibcon#read 6, iclass 14, count 2 2006.175.08:18:51.80#ibcon#end of sib2, iclass 14, count 2 2006.175.08:18:51.80#ibcon#*mode == 0, iclass 14, count 2 2006.175.08:18:51.80#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.08:18:51.80#ibcon#[25=AT03-06\r\n] 2006.175.08:18:51.80#ibcon#*before write, iclass 14, count 2 2006.175.08:18:51.80#ibcon#enter sib2, iclass 14, count 2 2006.175.08:18:51.80#ibcon#flushed, iclass 14, count 2 2006.175.08:18:51.80#ibcon#about to write, iclass 14, count 2 2006.175.08:18:51.80#ibcon#wrote, iclass 14, count 2 2006.175.08:18:51.80#ibcon#about to read 3, iclass 14, count 2 2006.175.08:18:51.83#ibcon#read 3, iclass 14, count 2 2006.175.08:18:51.83#ibcon#about to read 4, iclass 14, count 2 2006.175.08:18:51.83#ibcon#read 4, iclass 14, count 2 2006.175.08:18:51.83#ibcon#about to read 5, iclass 14, count 2 2006.175.08:18:51.83#ibcon#read 5, iclass 14, count 2 2006.175.08:18:51.83#ibcon#about to read 6, iclass 14, count 2 2006.175.08:18:51.83#ibcon#read 6, iclass 14, count 2 2006.175.08:18:51.83#ibcon#end of sib2, iclass 14, count 2 2006.175.08:18:51.83#ibcon#*after write, iclass 14, count 2 2006.175.08:18:51.83#ibcon#*before return 0, iclass 14, count 2 2006.175.08:18:51.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:51.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:51.83#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.08:18:51.83#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:51.83#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:51.95#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:51.95#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:51.95#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:18:51.95#ibcon#first serial, iclass 14, count 0 2006.175.08:18:51.95#ibcon#enter sib2, iclass 14, count 0 2006.175.08:18:51.95#ibcon#flushed, iclass 14, count 0 2006.175.08:18:51.95#ibcon#about to write, iclass 14, count 0 2006.175.08:18:51.95#ibcon#wrote, iclass 14, count 0 2006.175.08:18:51.95#ibcon#about to read 3, iclass 14, count 0 2006.175.08:18:51.97#ibcon#read 3, iclass 14, count 0 2006.175.08:18:51.97#ibcon#about to read 4, iclass 14, count 0 2006.175.08:18:51.97#ibcon#read 4, iclass 14, count 0 2006.175.08:18:51.97#ibcon#about to read 5, iclass 14, count 0 2006.175.08:18:51.97#ibcon#read 5, iclass 14, count 0 2006.175.08:18:51.97#ibcon#about to read 6, iclass 14, count 0 2006.175.08:18:51.97#ibcon#read 6, iclass 14, count 0 2006.175.08:18:51.97#ibcon#end of sib2, iclass 14, count 0 2006.175.08:18:51.97#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:18:51.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:18:51.97#ibcon#[25=USB\r\n] 2006.175.08:18:51.97#ibcon#*before write, iclass 14, count 0 2006.175.08:18:51.97#ibcon#enter sib2, iclass 14, count 0 2006.175.08:18:51.97#ibcon#flushed, iclass 14, count 0 2006.175.08:18:51.97#ibcon#about to write, iclass 14, count 0 2006.175.08:18:51.97#ibcon#wrote, iclass 14, count 0 2006.175.08:18:51.97#ibcon#about to read 3, iclass 14, count 0 2006.175.08:18:52.00#ibcon#read 3, iclass 14, count 0 2006.175.08:18:52.00#ibcon#about to read 4, iclass 14, count 0 2006.175.08:18:52.00#ibcon#read 4, iclass 14, count 0 2006.175.08:18:52.00#ibcon#about to read 5, iclass 14, count 0 2006.175.08:18:52.00#ibcon#read 5, iclass 14, count 0 2006.175.08:18:52.00#ibcon#about to read 6, iclass 14, count 0 2006.175.08:18:52.00#ibcon#read 6, iclass 14, count 0 2006.175.08:18:52.00#ibcon#end of sib2, iclass 14, count 0 2006.175.08:18:52.00#ibcon#*after write, iclass 14, count 0 2006.175.08:18:52.00#ibcon#*before return 0, iclass 14, count 0 2006.175.08:18:52.00#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:52.00#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:52.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:18:52.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:18:52.00$vc4f8/valo=4,832.99 2006.175.08:18:52.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.08:18:52.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.08:18:52.00#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:52.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:52.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:52.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:52.00#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:18:52.00#ibcon#first serial, iclass 16, count 0 2006.175.08:18:52.00#ibcon#enter sib2, iclass 16, count 0 2006.175.08:18:52.00#ibcon#flushed, iclass 16, count 0 2006.175.08:18:52.00#ibcon#about to write, iclass 16, count 0 2006.175.08:18:52.00#ibcon#wrote, iclass 16, count 0 2006.175.08:18:52.00#ibcon#about to read 3, iclass 16, count 0 2006.175.08:18:52.02#ibcon#read 3, iclass 16, count 0 2006.175.08:18:52.02#ibcon#about to read 4, iclass 16, count 0 2006.175.08:18:52.02#ibcon#read 4, iclass 16, count 0 2006.175.08:18:52.02#ibcon#about to read 5, iclass 16, count 0 2006.175.08:18:52.02#ibcon#read 5, iclass 16, count 0 2006.175.08:18:52.02#ibcon#about to read 6, iclass 16, count 0 2006.175.08:18:52.02#ibcon#read 6, iclass 16, count 0 2006.175.08:18:52.02#ibcon#end of sib2, iclass 16, count 0 2006.175.08:18:52.02#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:18:52.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:18:52.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:18:52.02#ibcon#*before write, iclass 16, count 0 2006.175.08:18:52.02#ibcon#enter sib2, iclass 16, count 0 2006.175.08:18:52.02#ibcon#flushed, iclass 16, count 0 2006.175.08:18:52.02#ibcon#about to write, iclass 16, count 0 2006.175.08:18:52.02#ibcon#wrote, iclass 16, count 0 2006.175.08:18:52.02#ibcon#about to read 3, iclass 16, count 0 2006.175.08:18:52.06#ibcon#read 3, iclass 16, count 0 2006.175.08:18:52.06#ibcon#about to read 4, iclass 16, count 0 2006.175.08:18:52.06#ibcon#read 4, iclass 16, count 0 2006.175.08:18:52.06#ibcon#about to read 5, iclass 16, count 0 2006.175.08:18:52.06#ibcon#read 5, iclass 16, count 0 2006.175.08:18:52.06#ibcon#about to read 6, iclass 16, count 0 2006.175.08:18:52.06#ibcon#read 6, iclass 16, count 0 2006.175.08:18:52.06#ibcon#end of sib2, iclass 16, count 0 2006.175.08:18:52.06#ibcon#*after write, iclass 16, count 0 2006.175.08:18:52.06#ibcon#*before return 0, iclass 16, count 0 2006.175.08:18:52.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:52.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:52.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:18:52.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:18:52.06$vc4f8/va=4,7 2006.175.08:18:52.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.08:18:52.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.08:18:52.06#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:52.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:52.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:52.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:52.12#ibcon#enter wrdev, iclass 18, count 2 2006.175.08:18:52.12#ibcon#first serial, iclass 18, count 2 2006.175.08:18:52.12#ibcon#enter sib2, iclass 18, count 2 2006.175.08:18:52.12#ibcon#flushed, iclass 18, count 2 2006.175.08:18:52.12#ibcon#about to write, iclass 18, count 2 2006.175.08:18:52.12#ibcon#wrote, iclass 18, count 2 2006.175.08:18:52.12#ibcon#about to read 3, iclass 18, count 2 2006.175.08:18:52.14#ibcon#read 3, iclass 18, count 2 2006.175.08:18:52.14#ibcon#about to read 4, iclass 18, count 2 2006.175.08:18:52.14#ibcon#read 4, iclass 18, count 2 2006.175.08:18:52.14#ibcon#about to read 5, iclass 18, count 2 2006.175.08:18:52.14#ibcon#read 5, iclass 18, count 2 2006.175.08:18:52.14#ibcon#about to read 6, iclass 18, count 2 2006.175.08:18:52.14#ibcon#read 6, iclass 18, count 2 2006.175.08:18:52.14#ibcon#end of sib2, iclass 18, count 2 2006.175.08:18:52.14#ibcon#*mode == 0, iclass 18, count 2 2006.175.08:18:52.14#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.08:18:52.14#ibcon#[25=AT04-07\r\n] 2006.175.08:18:52.14#ibcon#*before write, iclass 18, count 2 2006.175.08:18:52.14#ibcon#enter sib2, iclass 18, count 2 2006.175.08:18:52.14#ibcon#flushed, iclass 18, count 2 2006.175.08:18:52.14#ibcon#about to write, iclass 18, count 2 2006.175.08:18:52.14#ibcon#wrote, iclass 18, count 2 2006.175.08:18:52.14#ibcon#about to read 3, iclass 18, count 2 2006.175.08:18:52.17#ibcon#read 3, iclass 18, count 2 2006.175.08:18:52.17#ibcon#about to read 4, iclass 18, count 2 2006.175.08:18:52.17#ibcon#read 4, iclass 18, count 2 2006.175.08:18:52.17#ibcon#about to read 5, iclass 18, count 2 2006.175.08:18:52.17#ibcon#read 5, iclass 18, count 2 2006.175.08:18:52.17#ibcon#about to read 6, iclass 18, count 2 2006.175.08:18:52.17#ibcon#read 6, iclass 18, count 2 2006.175.08:18:52.17#ibcon#end of sib2, iclass 18, count 2 2006.175.08:18:52.17#ibcon#*after write, iclass 18, count 2 2006.175.08:18:52.17#ibcon#*before return 0, iclass 18, count 2 2006.175.08:18:52.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:52.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:52.17#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.08:18:52.17#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:52.17#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:52.29#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:52.29#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:52.29#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:18:52.29#ibcon#first serial, iclass 18, count 0 2006.175.08:18:52.29#ibcon#enter sib2, iclass 18, count 0 2006.175.08:18:52.29#ibcon#flushed, iclass 18, count 0 2006.175.08:18:52.29#ibcon#about to write, iclass 18, count 0 2006.175.08:18:52.29#ibcon#wrote, iclass 18, count 0 2006.175.08:18:52.29#ibcon#about to read 3, iclass 18, count 0 2006.175.08:18:52.31#ibcon#read 3, iclass 18, count 0 2006.175.08:18:52.31#ibcon#about to read 4, iclass 18, count 0 2006.175.08:18:52.31#ibcon#read 4, iclass 18, count 0 2006.175.08:18:52.31#ibcon#about to read 5, iclass 18, count 0 2006.175.08:18:52.31#ibcon#read 5, iclass 18, count 0 2006.175.08:18:52.31#ibcon#about to read 6, iclass 18, count 0 2006.175.08:18:52.31#ibcon#read 6, iclass 18, count 0 2006.175.08:18:52.31#ibcon#end of sib2, iclass 18, count 0 2006.175.08:18:52.31#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:18:52.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:18:52.31#ibcon#[25=USB\r\n] 2006.175.08:18:52.31#ibcon#*before write, iclass 18, count 0 2006.175.08:18:52.31#ibcon#enter sib2, iclass 18, count 0 2006.175.08:18:52.31#ibcon#flushed, iclass 18, count 0 2006.175.08:18:52.31#ibcon#about to write, iclass 18, count 0 2006.175.08:18:52.31#ibcon#wrote, iclass 18, count 0 2006.175.08:18:52.31#ibcon#about to read 3, iclass 18, count 0 2006.175.08:18:52.34#ibcon#read 3, iclass 18, count 0 2006.175.08:18:52.34#ibcon#about to read 4, iclass 18, count 0 2006.175.08:18:52.34#ibcon#read 4, iclass 18, count 0 2006.175.08:18:52.34#ibcon#about to read 5, iclass 18, count 0 2006.175.08:18:52.34#ibcon#read 5, iclass 18, count 0 2006.175.08:18:52.34#ibcon#about to read 6, iclass 18, count 0 2006.175.08:18:52.34#ibcon#read 6, iclass 18, count 0 2006.175.08:18:52.34#ibcon#end of sib2, iclass 18, count 0 2006.175.08:18:52.34#ibcon#*after write, iclass 18, count 0 2006.175.08:18:52.34#ibcon#*before return 0, iclass 18, count 0 2006.175.08:18:52.34#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:52.34#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:52.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:18:52.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:18:52.34$vc4f8/valo=5,652.99 2006.175.08:18:52.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.08:18:52.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.08:18:52.34#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:52.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:52.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:52.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:52.34#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:18:52.34#ibcon#first serial, iclass 20, count 0 2006.175.08:18:52.34#ibcon#enter sib2, iclass 20, count 0 2006.175.08:18:52.34#ibcon#flushed, iclass 20, count 0 2006.175.08:18:52.34#ibcon#about to write, iclass 20, count 0 2006.175.08:18:52.34#ibcon#wrote, iclass 20, count 0 2006.175.08:18:52.34#ibcon#about to read 3, iclass 20, count 0 2006.175.08:18:52.36#ibcon#read 3, iclass 20, count 0 2006.175.08:18:52.36#ibcon#about to read 4, iclass 20, count 0 2006.175.08:18:52.36#ibcon#read 4, iclass 20, count 0 2006.175.08:18:52.36#ibcon#about to read 5, iclass 20, count 0 2006.175.08:18:52.36#ibcon#read 5, iclass 20, count 0 2006.175.08:18:52.36#ibcon#about to read 6, iclass 20, count 0 2006.175.08:18:52.36#ibcon#read 6, iclass 20, count 0 2006.175.08:18:52.36#ibcon#end of sib2, iclass 20, count 0 2006.175.08:18:52.36#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:18:52.36#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:18:52.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:18:52.36#ibcon#*before write, iclass 20, count 0 2006.175.08:18:52.36#ibcon#enter sib2, iclass 20, count 0 2006.175.08:18:52.36#ibcon#flushed, iclass 20, count 0 2006.175.08:18:52.36#ibcon#about to write, iclass 20, count 0 2006.175.08:18:52.36#ibcon#wrote, iclass 20, count 0 2006.175.08:18:52.36#ibcon#about to read 3, iclass 20, count 0 2006.175.08:18:52.40#ibcon#read 3, iclass 20, count 0 2006.175.08:18:52.40#ibcon#about to read 4, iclass 20, count 0 2006.175.08:18:52.40#ibcon#read 4, iclass 20, count 0 2006.175.08:18:52.40#ibcon#about to read 5, iclass 20, count 0 2006.175.08:18:52.40#ibcon#read 5, iclass 20, count 0 2006.175.08:18:52.40#ibcon#about to read 6, iclass 20, count 0 2006.175.08:18:52.40#ibcon#read 6, iclass 20, count 0 2006.175.08:18:52.40#ibcon#end of sib2, iclass 20, count 0 2006.175.08:18:52.40#ibcon#*after write, iclass 20, count 0 2006.175.08:18:52.40#ibcon#*before return 0, iclass 20, count 0 2006.175.08:18:52.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:52.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:52.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:18:52.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:18:52.40$vc4f8/va=5,7 2006.175.08:18:52.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.08:18:52.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.08:18:52.40#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:52.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:52.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:52.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:52.46#ibcon#enter wrdev, iclass 22, count 2 2006.175.08:18:52.46#ibcon#first serial, iclass 22, count 2 2006.175.08:18:52.46#ibcon#enter sib2, iclass 22, count 2 2006.175.08:18:52.46#ibcon#flushed, iclass 22, count 2 2006.175.08:18:52.46#ibcon#about to write, iclass 22, count 2 2006.175.08:18:52.46#ibcon#wrote, iclass 22, count 2 2006.175.08:18:52.46#ibcon#about to read 3, iclass 22, count 2 2006.175.08:18:52.48#ibcon#read 3, iclass 22, count 2 2006.175.08:18:52.48#ibcon#about to read 4, iclass 22, count 2 2006.175.08:18:52.48#ibcon#read 4, iclass 22, count 2 2006.175.08:18:52.48#ibcon#about to read 5, iclass 22, count 2 2006.175.08:18:52.48#ibcon#read 5, iclass 22, count 2 2006.175.08:18:52.48#ibcon#about to read 6, iclass 22, count 2 2006.175.08:18:52.48#ibcon#read 6, iclass 22, count 2 2006.175.08:18:52.48#ibcon#end of sib2, iclass 22, count 2 2006.175.08:18:52.48#ibcon#*mode == 0, iclass 22, count 2 2006.175.08:18:52.48#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.08:18:52.48#ibcon#[25=AT05-07\r\n] 2006.175.08:18:52.48#ibcon#*before write, iclass 22, count 2 2006.175.08:18:52.48#ibcon#enter sib2, iclass 22, count 2 2006.175.08:18:52.48#ibcon#flushed, iclass 22, count 2 2006.175.08:18:52.48#ibcon#about to write, iclass 22, count 2 2006.175.08:18:52.48#ibcon#wrote, iclass 22, count 2 2006.175.08:18:52.48#ibcon#about to read 3, iclass 22, count 2 2006.175.08:18:52.51#ibcon#read 3, iclass 22, count 2 2006.175.08:18:52.51#ibcon#about to read 4, iclass 22, count 2 2006.175.08:18:52.51#ibcon#read 4, iclass 22, count 2 2006.175.08:18:52.51#ibcon#about to read 5, iclass 22, count 2 2006.175.08:18:52.51#ibcon#read 5, iclass 22, count 2 2006.175.08:18:52.51#ibcon#about to read 6, iclass 22, count 2 2006.175.08:18:52.51#ibcon#read 6, iclass 22, count 2 2006.175.08:18:52.51#ibcon#end of sib2, iclass 22, count 2 2006.175.08:18:52.51#ibcon#*after write, iclass 22, count 2 2006.175.08:18:52.51#ibcon#*before return 0, iclass 22, count 2 2006.175.08:18:52.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:52.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:52.51#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.08:18:52.51#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:52.51#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:52.63#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:52.63#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:52.63#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:18:52.63#ibcon#first serial, iclass 22, count 0 2006.175.08:18:52.63#ibcon#enter sib2, iclass 22, count 0 2006.175.08:18:52.63#ibcon#flushed, iclass 22, count 0 2006.175.08:18:52.63#ibcon#about to write, iclass 22, count 0 2006.175.08:18:52.63#ibcon#wrote, iclass 22, count 0 2006.175.08:18:52.63#ibcon#about to read 3, iclass 22, count 0 2006.175.08:18:52.65#ibcon#read 3, iclass 22, count 0 2006.175.08:18:52.65#ibcon#about to read 4, iclass 22, count 0 2006.175.08:18:52.65#ibcon#read 4, iclass 22, count 0 2006.175.08:18:52.65#ibcon#about to read 5, iclass 22, count 0 2006.175.08:18:52.65#ibcon#read 5, iclass 22, count 0 2006.175.08:18:52.65#ibcon#about to read 6, iclass 22, count 0 2006.175.08:18:52.65#ibcon#read 6, iclass 22, count 0 2006.175.08:18:52.65#ibcon#end of sib2, iclass 22, count 0 2006.175.08:18:52.65#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:18:52.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:18:52.65#ibcon#[25=USB\r\n] 2006.175.08:18:52.65#ibcon#*before write, iclass 22, count 0 2006.175.08:18:52.65#ibcon#enter sib2, iclass 22, count 0 2006.175.08:18:52.65#ibcon#flushed, iclass 22, count 0 2006.175.08:18:52.65#ibcon#about to write, iclass 22, count 0 2006.175.08:18:52.65#ibcon#wrote, iclass 22, count 0 2006.175.08:18:52.65#ibcon#about to read 3, iclass 22, count 0 2006.175.08:18:52.68#ibcon#read 3, iclass 22, count 0 2006.175.08:18:52.68#ibcon#about to read 4, iclass 22, count 0 2006.175.08:18:52.68#ibcon#read 4, iclass 22, count 0 2006.175.08:18:52.68#ibcon#about to read 5, iclass 22, count 0 2006.175.08:18:52.68#ibcon#read 5, iclass 22, count 0 2006.175.08:18:52.68#ibcon#about to read 6, iclass 22, count 0 2006.175.08:18:52.68#ibcon#read 6, iclass 22, count 0 2006.175.08:18:52.68#ibcon#end of sib2, iclass 22, count 0 2006.175.08:18:52.68#ibcon#*after write, iclass 22, count 0 2006.175.08:18:52.68#ibcon#*before return 0, iclass 22, count 0 2006.175.08:18:52.68#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:52.68#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:52.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:18:52.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:18:52.68$vc4f8/valo=6,772.99 2006.175.08:18:52.68#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.08:18:52.68#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.08:18:52.68#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:52.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:52.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:52.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:52.68#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:18:52.68#ibcon#first serial, iclass 24, count 0 2006.175.08:18:52.68#ibcon#enter sib2, iclass 24, count 0 2006.175.08:18:52.68#ibcon#flushed, iclass 24, count 0 2006.175.08:18:52.68#ibcon#about to write, iclass 24, count 0 2006.175.08:18:52.68#ibcon#wrote, iclass 24, count 0 2006.175.08:18:52.68#ibcon#about to read 3, iclass 24, count 0 2006.175.08:18:52.70#ibcon#read 3, iclass 24, count 0 2006.175.08:18:52.70#ibcon#about to read 4, iclass 24, count 0 2006.175.08:18:52.70#ibcon#read 4, iclass 24, count 0 2006.175.08:18:52.70#ibcon#about to read 5, iclass 24, count 0 2006.175.08:18:52.70#ibcon#read 5, iclass 24, count 0 2006.175.08:18:52.70#ibcon#about to read 6, iclass 24, count 0 2006.175.08:18:52.70#ibcon#read 6, iclass 24, count 0 2006.175.08:18:52.70#ibcon#end of sib2, iclass 24, count 0 2006.175.08:18:52.70#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:18:52.70#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:18:52.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:18:52.70#ibcon#*before write, iclass 24, count 0 2006.175.08:18:52.70#ibcon#enter sib2, iclass 24, count 0 2006.175.08:18:52.70#ibcon#flushed, iclass 24, count 0 2006.175.08:18:52.70#ibcon#about to write, iclass 24, count 0 2006.175.08:18:52.70#ibcon#wrote, iclass 24, count 0 2006.175.08:18:52.70#ibcon#about to read 3, iclass 24, count 0 2006.175.08:18:52.74#ibcon#read 3, iclass 24, count 0 2006.175.08:18:52.74#ibcon#about to read 4, iclass 24, count 0 2006.175.08:18:52.74#ibcon#read 4, iclass 24, count 0 2006.175.08:18:52.74#ibcon#about to read 5, iclass 24, count 0 2006.175.08:18:52.74#ibcon#read 5, iclass 24, count 0 2006.175.08:18:52.74#ibcon#about to read 6, iclass 24, count 0 2006.175.08:18:52.74#ibcon#read 6, iclass 24, count 0 2006.175.08:18:52.74#ibcon#end of sib2, iclass 24, count 0 2006.175.08:18:52.74#ibcon#*after write, iclass 24, count 0 2006.175.08:18:52.74#ibcon#*before return 0, iclass 24, count 0 2006.175.08:18:52.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:52.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:52.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:18:52.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:18:52.74$vc4f8/va=6,6 2006.175.08:18:52.74#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.175.08:18:52.74#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.175.08:18:52.74#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:52.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:18:52.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:18:52.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:18:52.80#ibcon#enter wrdev, iclass 26, count 2 2006.175.08:18:52.80#ibcon#first serial, iclass 26, count 2 2006.175.08:18:52.80#ibcon#enter sib2, iclass 26, count 2 2006.175.08:18:52.80#ibcon#flushed, iclass 26, count 2 2006.175.08:18:52.80#ibcon#about to write, iclass 26, count 2 2006.175.08:18:52.80#ibcon#wrote, iclass 26, count 2 2006.175.08:18:52.80#ibcon#about to read 3, iclass 26, count 2 2006.175.08:18:52.82#ibcon#read 3, iclass 26, count 2 2006.175.08:18:52.82#ibcon#about to read 4, iclass 26, count 2 2006.175.08:18:52.82#ibcon#read 4, iclass 26, count 2 2006.175.08:18:52.82#ibcon#about to read 5, iclass 26, count 2 2006.175.08:18:52.82#ibcon#read 5, iclass 26, count 2 2006.175.08:18:52.82#ibcon#about to read 6, iclass 26, count 2 2006.175.08:18:52.82#ibcon#read 6, iclass 26, count 2 2006.175.08:18:52.82#ibcon#end of sib2, iclass 26, count 2 2006.175.08:18:52.82#ibcon#*mode == 0, iclass 26, count 2 2006.175.08:18:52.82#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.175.08:18:52.82#ibcon#[25=AT06-06\r\n] 2006.175.08:18:52.82#ibcon#*before write, iclass 26, count 2 2006.175.08:18:52.82#ibcon#enter sib2, iclass 26, count 2 2006.175.08:18:52.82#ibcon#flushed, iclass 26, count 2 2006.175.08:18:52.82#ibcon#about to write, iclass 26, count 2 2006.175.08:18:52.82#ibcon#wrote, iclass 26, count 2 2006.175.08:18:52.82#ibcon#about to read 3, iclass 26, count 2 2006.175.08:18:52.85#ibcon#read 3, iclass 26, count 2 2006.175.08:18:52.85#ibcon#about to read 4, iclass 26, count 2 2006.175.08:18:52.85#ibcon#read 4, iclass 26, count 2 2006.175.08:18:52.85#ibcon#about to read 5, iclass 26, count 2 2006.175.08:18:52.85#ibcon#read 5, iclass 26, count 2 2006.175.08:18:52.85#ibcon#about to read 6, iclass 26, count 2 2006.175.08:18:52.85#ibcon#read 6, iclass 26, count 2 2006.175.08:18:52.85#ibcon#end of sib2, iclass 26, count 2 2006.175.08:18:52.85#ibcon#*after write, iclass 26, count 2 2006.175.08:18:52.85#ibcon#*before return 0, iclass 26, count 2 2006.175.08:18:52.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:18:52.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.175.08:18:52.85#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.175.08:18:52.85#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:52.85#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:18:52.97#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:18:52.97#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:18:52.97#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:18:52.97#ibcon#first serial, iclass 26, count 0 2006.175.08:18:52.97#ibcon#enter sib2, iclass 26, count 0 2006.175.08:18:52.97#ibcon#flushed, iclass 26, count 0 2006.175.08:18:52.97#ibcon#about to write, iclass 26, count 0 2006.175.08:18:52.97#ibcon#wrote, iclass 26, count 0 2006.175.08:18:52.97#ibcon#about to read 3, iclass 26, count 0 2006.175.08:18:52.99#ibcon#read 3, iclass 26, count 0 2006.175.08:18:52.99#ibcon#about to read 4, iclass 26, count 0 2006.175.08:18:52.99#ibcon#read 4, iclass 26, count 0 2006.175.08:18:52.99#ibcon#about to read 5, iclass 26, count 0 2006.175.08:18:52.99#ibcon#read 5, iclass 26, count 0 2006.175.08:18:52.99#ibcon#about to read 6, iclass 26, count 0 2006.175.08:18:52.99#ibcon#read 6, iclass 26, count 0 2006.175.08:18:52.99#ibcon#end of sib2, iclass 26, count 0 2006.175.08:18:52.99#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:18:52.99#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:18:52.99#ibcon#[25=USB\r\n] 2006.175.08:18:52.99#ibcon#*before write, iclass 26, count 0 2006.175.08:18:52.99#ibcon#enter sib2, iclass 26, count 0 2006.175.08:18:52.99#ibcon#flushed, iclass 26, count 0 2006.175.08:18:52.99#ibcon#about to write, iclass 26, count 0 2006.175.08:18:52.99#ibcon#wrote, iclass 26, count 0 2006.175.08:18:52.99#ibcon#about to read 3, iclass 26, count 0 2006.175.08:18:53.02#ibcon#read 3, iclass 26, count 0 2006.175.08:18:53.02#ibcon#about to read 4, iclass 26, count 0 2006.175.08:18:53.02#ibcon#read 4, iclass 26, count 0 2006.175.08:18:53.02#ibcon#about to read 5, iclass 26, count 0 2006.175.08:18:53.02#ibcon#read 5, iclass 26, count 0 2006.175.08:18:53.02#ibcon#about to read 6, iclass 26, count 0 2006.175.08:18:53.02#ibcon#read 6, iclass 26, count 0 2006.175.08:18:53.02#ibcon#end of sib2, iclass 26, count 0 2006.175.08:18:53.02#ibcon#*after write, iclass 26, count 0 2006.175.08:18:53.02#ibcon#*before return 0, iclass 26, count 0 2006.175.08:18:53.02#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:18:53.02#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.175.08:18:53.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:18:53.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:18:53.02$vc4f8/valo=7,832.99 2006.175.08:18:53.02#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.175.08:18:53.02#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.175.08:18:53.02#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:53.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:18:53.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:18:53.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:18:53.02#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:18:53.02#ibcon#first serial, iclass 28, count 0 2006.175.08:18:53.02#ibcon#enter sib2, iclass 28, count 0 2006.175.08:18:53.02#ibcon#flushed, iclass 28, count 0 2006.175.08:18:53.02#ibcon#about to write, iclass 28, count 0 2006.175.08:18:53.02#ibcon#wrote, iclass 28, count 0 2006.175.08:18:53.02#ibcon#about to read 3, iclass 28, count 0 2006.175.08:18:53.04#ibcon#read 3, iclass 28, count 0 2006.175.08:18:53.04#ibcon#about to read 4, iclass 28, count 0 2006.175.08:18:53.04#ibcon#read 4, iclass 28, count 0 2006.175.08:18:53.04#ibcon#about to read 5, iclass 28, count 0 2006.175.08:18:53.04#ibcon#read 5, iclass 28, count 0 2006.175.08:18:53.04#ibcon#about to read 6, iclass 28, count 0 2006.175.08:18:53.04#ibcon#read 6, iclass 28, count 0 2006.175.08:18:53.04#ibcon#end of sib2, iclass 28, count 0 2006.175.08:18:53.04#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:18:53.04#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:18:53.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:18:53.04#ibcon#*before write, iclass 28, count 0 2006.175.08:18:53.04#ibcon#enter sib2, iclass 28, count 0 2006.175.08:18:53.04#ibcon#flushed, iclass 28, count 0 2006.175.08:18:53.04#ibcon#about to write, iclass 28, count 0 2006.175.08:18:53.04#ibcon#wrote, iclass 28, count 0 2006.175.08:18:53.04#ibcon#about to read 3, iclass 28, count 0 2006.175.08:18:53.08#ibcon#read 3, iclass 28, count 0 2006.175.08:18:53.08#ibcon#about to read 4, iclass 28, count 0 2006.175.08:18:53.08#ibcon#read 4, iclass 28, count 0 2006.175.08:18:53.08#ibcon#about to read 5, iclass 28, count 0 2006.175.08:18:53.08#ibcon#read 5, iclass 28, count 0 2006.175.08:18:53.08#ibcon#about to read 6, iclass 28, count 0 2006.175.08:18:53.08#ibcon#read 6, iclass 28, count 0 2006.175.08:18:53.08#ibcon#end of sib2, iclass 28, count 0 2006.175.08:18:53.08#ibcon#*after write, iclass 28, count 0 2006.175.08:18:53.08#ibcon#*before return 0, iclass 28, count 0 2006.175.08:18:53.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:18:53.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.175.08:18:53.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:18:53.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:18:53.08$vc4f8/va=7,6 2006.175.08:18:53.08#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.175.08:18:53.08#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.175.08:18:53.08#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:53.08#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:18:53.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:18:53.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:18:53.14#ibcon#enter wrdev, iclass 30, count 2 2006.175.08:18:53.14#ibcon#first serial, iclass 30, count 2 2006.175.08:18:53.14#ibcon#enter sib2, iclass 30, count 2 2006.175.08:18:53.14#ibcon#flushed, iclass 30, count 2 2006.175.08:18:53.14#ibcon#about to write, iclass 30, count 2 2006.175.08:18:53.14#ibcon#wrote, iclass 30, count 2 2006.175.08:18:53.14#ibcon#about to read 3, iclass 30, count 2 2006.175.08:18:53.16#ibcon#read 3, iclass 30, count 2 2006.175.08:18:53.16#ibcon#about to read 4, iclass 30, count 2 2006.175.08:18:53.16#ibcon#read 4, iclass 30, count 2 2006.175.08:18:53.16#ibcon#about to read 5, iclass 30, count 2 2006.175.08:18:53.16#ibcon#read 5, iclass 30, count 2 2006.175.08:18:53.16#ibcon#about to read 6, iclass 30, count 2 2006.175.08:18:53.16#ibcon#read 6, iclass 30, count 2 2006.175.08:18:53.16#ibcon#end of sib2, iclass 30, count 2 2006.175.08:18:53.16#ibcon#*mode == 0, iclass 30, count 2 2006.175.08:18:53.16#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.175.08:18:53.16#ibcon#[25=AT07-06\r\n] 2006.175.08:18:53.16#ibcon#*before write, iclass 30, count 2 2006.175.08:18:53.16#ibcon#enter sib2, iclass 30, count 2 2006.175.08:18:53.16#ibcon#flushed, iclass 30, count 2 2006.175.08:18:53.16#ibcon#about to write, iclass 30, count 2 2006.175.08:18:53.16#ibcon#wrote, iclass 30, count 2 2006.175.08:18:53.16#ibcon#about to read 3, iclass 30, count 2 2006.175.08:18:53.19#ibcon#read 3, iclass 30, count 2 2006.175.08:18:53.19#ibcon#about to read 4, iclass 30, count 2 2006.175.08:18:53.19#ibcon#read 4, iclass 30, count 2 2006.175.08:18:53.19#ibcon#about to read 5, iclass 30, count 2 2006.175.08:18:53.19#ibcon#read 5, iclass 30, count 2 2006.175.08:18:53.19#ibcon#about to read 6, iclass 30, count 2 2006.175.08:18:53.19#ibcon#read 6, iclass 30, count 2 2006.175.08:18:53.19#ibcon#end of sib2, iclass 30, count 2 2006.175.08:18:53.19#ibcon#*after write, iclass 30, count 2 2006.175.08:18:53.19#ibcon#*before return 0, iclass 30, count 2 2006.175.08:18:53.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:18:53.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.175.08:18:53.19#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.175.08:18:53.19#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:53.19#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:18:53.31#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:18:53.31#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:18:53.31#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:18:53.31#ibcon#first serial, iclass 30, count 0 2006.175.08:18:53.31#ibcon#enter sib2, iclass 30, count 0 2006.175.08:18:53.31#ibcon#flushed, iclass 30, count 0 2006.175.08:18:53.31#ibcon#about to write, iclass 30, count 0 2006.175.08:18:53.31#ibcon#wrote, iclass 30, count 0 2006.175.08:18:53.31#ibcon#about to read 3, iclass 30, count 0 2006.175.08:18:53.33#ibcon#read 3, iclass 30, count 0 2006.175.08:18:53.33#ibcon#about to read 4, iclass 30, count 0 2006.175.08:18:53.33#ibcon#read 4, iclass 30, count 0 2006.175.08:18:53.33#ibcon#about to read 5, iclass 30, count 0 2006.175.08:18:53.33#ibcon#read 5, iclass 30, count 0 2006.175.08:18:53.33#ibcon#about to read 6, iclass 30, count 0 2006.175.08:18:53.33#ibcon#read 6, iclass 30, count 0 2006.175.08:18:53.33#ibcon#end of sib2, iclass 30, count 0 2006.175.08:18:53.33#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:18:53.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:18:53.33#ibcon#[25=USB\r\n] 2006.175.08:18:53.33#ibcon#*before write, iclass 30, count 0 2006.175.08:18:53.33#ibcon#enter sib2, iclass 30, count 0 2006.175.08:18:53.33#ibcon#flushed, iclass 30, count 0 2006.175.08:18:53.33#ibcon#about to write, iclass 30, count 0 2006.175.08:18:53.33#ibcon#wrote, iclass 30, count 0 2006.175.08:18:53.33#ibcon#about to read 3, iclass 30, count 0 2006.175.08:18:53.36#ibcon#read 3, iclass 30, count 0 2006.175.08:18:53.36#ibcon#about to read 4, iclass 30, count 0 2006.175.08:18:53.36#ibcon#read 4, iclass 30, count 0 2006.175.08:18:53.36#ibcon#about to read 5, iclass 30, count 0 2006.175.08:18:53.36#ibcon#read 5, iclass 30, count 0 2006.175.08:18:53.36#ibcon#about to read 6, iclass 30, count 0 2006.175.08:18:53.36#ibcon#read 6, iclass 30, count 0 2006.175.08:18:53.36#ibcon#end of sib2, iclass 30, count 0 2006.175.08:18:53.36#ibcon#*after write, iclass 30, count 0 2006.175.08:18:53.36#ibcon#*before return 0, iclass 30, count 0 2006.175.08:18:53.36#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:18:53.36#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.175.08:18:53.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:18:53.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:18:53.36$vc4f8/valo=8,852.99 2006.175.08:18:53.36#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.175.08:18:53.36#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.175.08:18:53.36#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:53.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:18:53.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:18:53.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:18:53.36#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:18:53.36#ibcon#first serial, iclass 32, count 0 2006.175.08:18:53.36#ibcon#enter sib2, iclass 32, count 0 2006.175.08:18:53.36#ibcon#flushed, iclass 32, count 0 2006.175.08:18:53.36#ibcon#about to write, iclass 32, count 0 2006.175.08:18:53.36#ibcon#wrote, iclass 32, count 0 2006.175.08:18:53.36#ibcon#about to read 3, iclass 32, count 0 2006.175.08:18:53.38#ibcon#read 3, iclass 32, count 0 2006.175.08:18:53.38#ibcon#about to read 4, iclass 32, count 0 2006.175.08:18:53.38#ibcon#read 4, iclass 32, count 0 2006.175.08:18:53.38#ibcon#about to read 5, iclass 32, count 0 2006.175.08:18:53.38#ibcon#read 5, iclass 32, count 0 2006.175.08:18:53.38#ibcon#about to read 6, iclass 32, count 0 2006.175.08:18:53.38#ibcon#read 6, iclass 32, count 0 2006.175.08:18:53.38#ibcon#end of sib2, iclass 32, count 0 2006.175.08:18:53.38#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:18:53.38#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:18:53.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:18:53.38#ibcon#*before write, iclass 32, count 0 2006.175.08:18:53.38#ibcon#enter sib2, iclass 32, count 0 2006.175.08:18:53.38#ibcon#flushed, iclass 32, count 0 2006.175.08:18:53.38#ibcon#about to write, iclass 32, count 0 2006.175.08:18:53.38#ibcon#wrote, iclass 32, count 0 2006.175.08:18:53.38#ibcon#about to read 3, iclass 32, count 0 2006.175.08:18:53.42#ibcon#read 3, iclass 32, count 0 2006.175.08:18:53.42#ibcon#about to read 4, iclass 32, count 0 2006.175.08:18:53.42#ibcon#read 4, iclass 32, count 0 2006.175.08:18:53.42#ibcon#about to read 5, iclass 32, count 0 2006.175.08:18:53.42#ibcon#read 5, iclass 32, count 0 2006.175.08:18:53.42#ibcon#about to read 6, iclass 32, count 0 2006.175.08:18:53.42#ibcon#read 6, iclass 32, count 0 2006.175.08:18:53.42#ibcon#end of sib2, iclass 32, count 0 2006.175.08:18:53.42#ibcon#*after write, iclass 32, count 0 2006.175.08:18:53.42#ibcon#*before return 0, iclass 32, count 0 2006.175.08:18:53.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:18:53.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.175.08:18:53.42#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:18:53.42#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:18:53.42$vc4f8/va=8,6 2006.175.08:18:53.42#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.175.08:18:53.42#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.175.08:18:53.42#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:53.42#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:18:53.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:18:53.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:18:53.48#ibcon#enter wrdev, iclass 34, count 2 2006.175.08:18:53.48#ibcon#first serial, iclass 34, count 2 2006.175.08:18:53.48#ibcon#enter sib2, iclass 34, count 2 2006.175.08:18:53.48#ibcon#flushed, iclass 34, count 2 2006.175.08:18:53.48#ibcon#about to write, iclass 34, count 2 2006.175.08:18:53.48#ibcon#wrote, iclass 34, count 2 2006.175.08:18:53.48#ibcon#about to read 3, iclass 34, count 2 2006.175.08:18:53.50#ibcon#read 3, iclass 34, count 2 2006.175.08:18:53.50#ibcon#about to read 4, iclass 34, count 2 2006.175.08:18:53.50#ibcon#read 4, iclass 34, count 2 2006.175.08:18:53.50#ibcon#about to read 5, iclass 34, count 2 2006.175.08:18:53.50#ibcon#read 5, iclass 34, count 2 2006.175.08:18:53.50#ibcon#about to read 6, iclass 34, count 2 2006.175.08:18:53.50#ibcon#read 6, iclass 34, count 2 2006.175.08:18:53.50#ibcon#end of sib2, iclass 34, count 2 2006.175.08:18:53.50#ibcon#*mode == 0, iclass 34, count 2 2006.175.08:18:53.50#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.175.08:18:53.50#ibcon#[25=AT08-06\r\n] 2006.175.08:18:53.50#ibcon#*before write, iclass 34, count 2 2006.175.08:18:53.50#ibcon#enter sib2, iclass 34, count 2 2006.175.08:18:53.50#ibcon#flushed, iclass 34, count 2 2006.175.08:18:53.50#ibcon#about to write, iclass 34, count 2 2006.175.08:18:53.50#ibcon#wrote, iclass 34, count 2 2006.175.08:18:53.50#ibcon#about to read 3, iclass 34, count 2 2006.175.08:18:53.53#ibcon#read 3, iclass 34, count 2 2006.175.08:18:53.53#ibcon#about to read 4, iclass 34, count 2 2006.175.08:18:53.53#ibcon#read 4, iclass 34, count 2 2006.175.08:18:53.53#ibcon#about to read 5, iclass 34, count 2 2006.175.08:18:53.53#ibcon#read 5, iclass 34, count 2 2006.175.08:18:53.53#ibcon#about to read 6, iclass 34, count 2 2006.175.08:18:53.53#ibcon#read 6, iclass 34, count 2 2006.175.08:18:53.53#ibcon#end of sib2, iclass 34, count 2 2006.175.08:18:53.53#ibcon#*after write, iclass 34, count 2 2006.175.08:18:53.53#ibcon#*before return 0, iclass 34, count 2 2006.175.08:18:53.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:18:53.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.175.08:18:53.53#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.175.08:18:53.53#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:53.53#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:18:53.65#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:18:53.65#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:18:53.65#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:18:53.65#ibcon#first serial, iclass 34, count 0 2006.175.08:18:53.65#ibcon#enter sib2, iclass 34, count 0 2006.175.08:18:53.65#ibcon#flushed, iclass 34, count 0 2006.175.08:18:53.65#ibcon#about to write, iclass 34, count 0 2006.175.08:18:53.65#ibcon#wrote, iclass 34, count 0 2006.175.08:18:53.65#ibcon#about to read 3, iclass 34, count 0 2006.175.08:18:53.67#ibcon#read 3, iclass 34, count 0 2006.175.08:18:53.67#ibcon#about to read 4, iclass 34, count 0 2006.175.08:18:53.67#ibcon#read 4, iclass 34, count 0 2006.175.08:18:53.67#ibcon#about to read 5, iclass 34, count 0 2006.175.08:18:53.67#ibcon#read 5, iclass 34, count 0 2006.175.08:18:53.67#ibcon#about to read 6, iclass 34, count 0 2006.175.08:18:53.67#ibcon#read 6, iclass 34, count 0 2006.175.08:18:53.67#ibcon#end of sib2, iclass 34, count 0 2006.175.08:18:53.67#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:18:53.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:18:53.67#ibcon#[25=USB\r\n] 2006.175.08:18:53.67#ibcon#*before write, iclass 34, count 0 2006.175.08:18:53.67#ibcon#enter sib2, iclass 34, count 0 2006.175.08:18:53.67#ibcon#flushed, iclass 34, count 0 2006.175.08:18:53.67#ibcon#about to write, iclass 34, count 0 2006.175.08:18:53.67#ibcon#wrote, iclass 34, count 0 2006.175.08:18:53.67#ibcon#about to read 3, iclass 34, count 0 2006.175.08:18:53.70#ibcon#read 3, iclass 34, count 0 2006.175.08:18:53.70#ibcon#about to read 4, iclass 34, count 0 2006.175.08:18:53.70#ibcon#read 4, iclass 34, count 0 2006.175.08:18:53.70#ibcon#about to read 5, iclass 34, count 0 2006.175.08:18:53.70#ibcon#read 5, iclass 34, count 0 2006.175.08:18:53.70#ibcon#about to read 6, iclass 34, count 0 2006.175.08:18:53.70#ibcon#read 6, iclass 34, count 0 2006.175.08:18:53.70#ibcon#end of sib2, iclass 34, count 0 2006.175.08:18:53.70#ibcon#*after write, iclass 34, count 0 2006.175.08:18:53.70#ibcon#*before return 0, iclass 34, count 0 2006.175.08:18:53.70#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:18:53.70#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.175.08:18:53.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:18:53.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:18:53.70$vc4f8/vblo=1,632.99 2006.175.08:18:53.70#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.175.08:18:53.70#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.175.08:18:53.70#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:53.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:53.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:53.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:53.70#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:18:53.70#ibcon#first serial, iclass 36, count 0 2006.175.08:18:53.70#ibcon#enter sib2, iclass 36, count 0 2006.175.08:18:53.70#ibcon#flushed, iclass 36, count 0 2006.175.08:18:53.70#ibcon#about to write, iclass 36, count 0 2006.175.08:18:53.70#ibcon#wrote, iclass 36, count 0 2006.175.08:18:53.70#ibcon#about to read 3, iclass 36, count 0 2006.175.08:18:53.72#ibcon#read 3, iclass 36, count 0 2006.175.08:18:53.72#ibcon#about to read 4, iclass 36, count 0 2006.175.08:18:53.72#ibcon#read 4, iclass 36, count 0 2006.175.08:18:53.72#ibcon#about to read 5, iclass 36, count 0 2006.175.08:18:53.72#ibcon#read 5, iclass 36, count 0 2006.175.08:18:53.72#ibcon#about to read 6, iclass 36, count 0 2006.175.08:18:53.72#ibcon#read 6, iclass 36, count 0 2006.175.08:18:53.72#ibcon#end of sib2, iclass 36, count 0 2006.175.08:18:53.72#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:18:53.72#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:18:53.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:18:53.72#ibcon#*before write, iclass 36, count 0 2006.175.08:18:53.72#ibcon#enter sib2, iclass 36, count 0 2006.175.08:18:53.72#ibcon#flushed, iclass 36, count 0 2006.175.08:18:53.72#ibcon#about to write, iclass 36, count 0 2006.175.08:18:53.72#ibcon#wrote, iclass 36, count 0 2006.175.08:18:53.72#ibcon#about to read 3, iclass 36, count 0 2006.175.08:18:53.76#ibcon#read 3, iclass 36, count 0 2006.175.08:18:53.76#ibcon#about to read 4, iclass 36, count 0 2006.175.08:18:53.76#ibcon#read 4, iclass 36, count 0 2006.175.08:18:53.76#ibcon#about to read 5, iclass 36, count 0 2006.175.08:18:53.76#ibcon#read 5, iclass 36, count 0 2006.175.08:18:53.76#ibcon#about to read 6, iclass 36, count 0 2006.175.08:18:53.76#ibcon#read 6, iclass 36, count 0 2006.175.08:18:53.76#ibcon#end of sib2, iclass 36, count 0 2006.175.08:18:53.76#ibcon#*after write, iclass 36, count 0 2006.175.08:18:53.76#ibcon#*before return 0, iclass 36, count 0 2006.175.08:18:53.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:53.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.175.08:18:53.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:18:53.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:18:53.76$vc4f8/vb=1,4 2006.175.08:18:53.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.175.08:18:53.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.175.08:18:53.76#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:53.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:53.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:53.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:53.76#ibcon#enter wrdev, iclass 38, count 2 2006.175.08:18:53.76#ibcon#first serial, iclass 38, count 2 2006.175.08:18:53.76#ibcon#enter sib2, iclass 38, count 2 2006.175.08:18:53.76#ibcon#flushed, iclass 38, count 2 2006.175.08:18:53.76#ibcon#about to write, iclass 38, count 2 2006.175.08:18:53.76#ibcon#wrote, iclass 38, count 2 2006.175.08:18:53.76#ibcon#about to read 3, iclass 38, count 2 2006.175.08:18:53.78#ibcon#read 3, iclass 38, count 2 2006.175.08:18:53.78#ibcon#about to read 4, iclass 38, count 2 2006.175.08:18:53.78#ibcon#read 4, iclass 38, count 2 2006.175.08:18:53.78#ibcon#about to read 5, iclass 38, count 2 2006.175.08:18:53.78#ibcon#read 5, iclass 38, count 2 2006.175.08:18:53.78#ibcon#about to read 6, iclass 38, count 2 2006.175.08:18:53.78#ibcon#read 6, iclass 38, count 2 2006.175.08:18:53.78#ibcon#end of sib2, iclass 38, count 2 2006.175.08:18:53.78#ibcon#*mode == 0, iclass 38, count 2 2006.175.08:18:53.78#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.175.08:18:53.78#ibcon#[27=AT01-04\r\n] 2006.175.08:18:53.78#ibcon#*before write, iclass 38, count 2 2006.175.08:18:53.78#ibcon#enter sib2, iclass 38, count 2 2006.175.08:18:53.78#ibcon#flushed, iclass 38, count 2 2006.175.08:18:53.78#ibcon#about to write, iclass 38, count 2 2006.175.08:18:53.78#ibcon#wrote, iclass 38, count 2 2006.175.08:18:53.78#ibcon#about to read 3, iclass 38, count 2 2006.175.08:18:53.81#ibcon#read 3, iclass 38, count 2 2006.175.08:18:53.81#ibcon#about to read 4, iclass 38, count 2 2006.175.08:18:53.81#ibcon#read 4, iclass 38, count 2 2006.175.08:18:53.81#ibcon#about to read 5, iclass 38, count 2 2006.175.08:18:53.81#ibcon#read 5, iclass 38, count 2 2006.175.08:18:53.81#ibcon#about to read 6, iclass 38, count 2 2006.175.08:18:53.81#ibcon#read 6, iclass 38, count 2 2006.175.08:18:53.81#ibcon#end of sib2, iclass 38, count 2 2006.175.08:18:53.81#ibcon#*after write, iclass 38, count 2 2006.175.08:18:53.81#ibcon#*before return 0, iclass 38, count 2 2006.175.08:18:53.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:53.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.175.08:18:53.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.175.08:18:53.81#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:53.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:53.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:53.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:53.93#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:18:53.93#ibcon#first serial, iclass 38, count 0 2006.175.08:18:53.93#ibcon#enter sib2, iclass 38, count 0 2006.175.08:18:53.93#ibcon#flushed, iclass 38, count 0 2006.175.08:18:53.93#ibcon#about to write, iclass 38, count 0 2006.175.08:18:53.93#ibcon#wrote, iclass 38, count 0 2006.175.08:18:53.93#ibcon#about to read 3, iclass 38, count 0 2006.175.08:18:53.95#ibcon#read 3, iclass 38, count 0 2006.175.08:18:53.95#ibcon#about to read 4, iclass 38, count 0 2006.175.08:18:53.95#ibcon#read 4, iclass 38, count 0 2006.175.08:18:53.95#ibcon#about to read 5, iclass 38, count 0 2006.175.08:18:53.95#ibcon#read 5, iclass 38, count 0 2006.175.08:18:53.95#ibcon#about to read 6, iclass 38, count 0 2006.175.08:18:53.95#ibcon#read 6, iclass 38, count 0 2006.175.08:18:53.95#ibcon#end of sib2, iclass 38, count 0 2006.175.08:18:53.95#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:18:53.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:18:53.95#ibcon#[27=USB\r\n] 2006.175.08:18:53.95#ibcon#*before write, iclass 38, count 0 2006.175.08:18:53.95#ibcon#enter sib2, iclass 38, count 0 2006.175.08:18:53.95#ibcon#flushed, iclass 38, count 0 2006.175.08:18:53.95#ibcon#about to write, iclass 38, count 0 2006.175.08:18:53.95#ibcon#wrote, iclass 38, count 0 2006.175.08:18:53.95#ibcon#about to read 3, iclass 38, count 0 2006.175.08:18:53.98#ibcon#read 3, iclass 38, count 0 2006.175.08:18:53.98#ibcon#about to read 4, iclass 38, count 0 2006.175.08:18:53.98#ibcon#read 4, iclass 38, count 0 2006.175.08:18:53.98#ibcon#about to read 5, iclass 38, count 0 2006.175.08:18:53.98#ibcon#read 5, iclass 38, count 0 2006.175.08:18:53.98#ibcon#about to read 6, iclass 38, count 0 2006.175.08:18:53.98#ibcon#read 6, iclass 38, count 0 2006.175.08:18:53.98#ibcon#end of sib2, iclass 38, count 0 2006.175.08:18:53.98#ibcon#*after write, iclass 38, count 0 2006.175.08:18:53.98#ibcon#*before return 0, iclass 38, count 0 2006.175.08:18:53.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:53.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.175.08:18:53.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:18:53.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:18:53.98$vc4f8/vblo=2,640.99 2006.175.08:18:53.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.175.08:18:53.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.175.08:18:53.98#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:53.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:53.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:53.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:53.98#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:18:53.98#ibcon#first serial, iclass 40, count 0 2006.175.08:18:53.98#ibcon#enter sib2, iclass 40, count 0 2006.175.08:18:53.98#ibcon#flushed, iclass 40, count 0 2006.175.08:18:53.98#ibcon#about to write, iclass 40, count 0 2006.175.08:18:53.98#ibcon#wrote, iclass 40, count 0 2006.175.08:18:53.98#ibcon#about to read 3, iclass 40, count 0 2006.175.08:18:54.00#ibcon#read 3, iclass 40, count 0 2006.175.08:18:54.00#ibcon#about to read 4, iclass 40, count 0 2006.175.08:18:54.00#ibcon#read 4, iclass 40, count 0 2006.175.08:18:54.00#ibcon#about to read 5, iclass 40, count 0 2006.175.08:18:54.00#ibcon#read 5, iclass 40, count 0 2006.175.08:18:54.00#ibcon#about to read 6, iclass 40, count 0 2006.175.08:18:54.00#ibcon#read 6, iclass 40, count 0 2006.175.08:18:54.00#ibcon#end of sib2, iclass 40, count 0 2006.175.08:18:54.00#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:18:54.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:18:54.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:18:54.00#ibcon#*before write, iclass 40, count 0 2006.175.08:18:54.00#ibcon#enter sib2, iclass 40, count 0 2006.175.08:18:54.00#ibcon#flushed, iclass 40, count 0 2006.175.08:18:54.00#ibcon#about to write, iclass 40, count 0 2006.175.08:18:54.00#ibcon#wrote, iclass 40, count 0 2006.175.08:18:54.00#ibcon#about to read 3, iclass 40, count 0 2006.175.08:18:54.04#ibcon#read 3, iclass 40, count 0 2006.175.08:18:54.04#ibcon#about to read 4, iclass 40, count 0 2006.175.08:18:54.04#ibcon#read 4, iclass 40, count 0 2006.175.08:18:54.04#ibcon#about to read 5, iclass 40, count 0 2006.175.08:18:54.04#ibcon#read 5, iclass 40, count 0 2006.175.08:18:54.04#ibcon#about to read 6, iclass 40, count 0 2006.175.08:18:54.04#ibcon#read 6, iclass 40, count 0 2006.175.08:18:54.04#ibcon#end of sib2, iclass 40, count 0 2006.175.08:18:54.04#ibcon#*after write, iclass 40, count 0 2006.175.08:18:54.04#ibcon#*before return 0, iclass 40, count 0 2006.175.08:18:54.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:54.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.175.08:18:54.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:18:54.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:18:54.04$vc4f8/vb=2,4 2006.175.08:18:54.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.175.08:18:54.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.175.08:18:54.04#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:54.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:54.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:54.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:54.10#ibcon#enter wrdev, iclass 4, count 2 2006.175.08:18:54.10#ibcon#first serial, iclass 4, count 2 2006.175.08:18:54.10#ibcon#enter sib2, iclass 4, count 2 2006.175.08:18:54.10#ibcon#flushed, iclass 4, count 2 2006.175.08:18:54.10#ibcon#about to write, iclass 4, count 2 2006.175.08:18:54.10#ibcon#wrote, iclass 4, count 2 2006.175.08:18:54.10#ibcon#about to read 3, iclass 4, count 2 2006.175.08:18:54.13#ibcon#read 3, iclass 4, count 2 2006.175.08:18:54.13#ibcon#about to read 4, iclass 4, count 2 2006.175.08:18:54.13#ibcon#read 4, iclass 4, count 2 2006.175.08:18:54.13#ibcon#about to read 5, iclass 4, count 2 2006.175.08:18:54.13#ibcon#read 5, iclass 4, count 2 2006.175.08:18:54.13#ibcon#about to read 6, iclass 4, count 2 2006.175.08:18:54.13#ibcon#read 6, iclass 4, count 2 2006.175.08:18:54.13#ibcon#end of sib2, iclass 4, count 2 2006.175.08:18:54.13#ibcon#*mode == 0, iclass 4, count 2 2006.175.08:18:54.13#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.175.08:18:54.13#ibcon#[27=AT02-04\r\n] 2006.175.08:18:54.13#ibcon#*before write, iclass 4, count 2 2006.175.08:18:54.13#ibcon#enter sib2, iclass 4, count 2 2006.175.08:18:54.13#ibcon#flushed, iclass 4, count 2 2006.175.08:18:54.13#ibcon#about to write, iclass 4, count 2 2006.175.08:18:54.13#ibcon#wrote, iclass 4, count 2 2006.175.08:18:54.13#ibcon#about to read 3, iclass 4, count 2 2006.175.08:18:54.16#ibcon#read 3, iclass 4, count 2 2006.175.08:18:54.16#ibcon#about to read 4, iclass 4, count 2 2006.175.08:18:54.16#ibcon#read 4, iclass 4, count 2 2006.175.08:18:54.16#ibcon#about to read 5, iclass 4, count 2 2006.175.08:18:54.16#ibcon#read 5, iclass 4, count 2 2006.175.08:18:54.16#ibcon#about to read 6, iclass 4, count 2 2006.175.08:18:54.16#ibcon#read 6, iclass 4, count 2 2006.175.08:18:54.16#ibcon#end of sib2, iclass 4, count 2 2006.175.08:18:54.16#ibcon#*after write, iclass 4, count 2 2006.175.08:18:54.16#ibcon#*before return 0, iclass 4, count 2 2006.175.08:18:54.16#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:54.16#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.175.08:18:54.16#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.175.08:18:54.16#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:54.16#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:54.28#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:54.28#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:54.28#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:18:54.28#ibcon#first serial, iclass 4, count 0 2006.175.08:18:54.28#ibcon#enter sib2, iclass 4, count 0 2006.175.08:18:54.28#ibcon#flushed, iclass 4, count 0 2006.175.08:18:54.28#ibcon#about to write, iclass 4, count 0 2006.175.08:18:54.28#ibcon#wrote, iclass 4, count 0 2006.175.08:18:54.28#ibcon#about to read 3, iclass 4, count 0 2006.175.08:18:54.30#ibcon#read 3, iclass 4, count 0 2006.175.08:18:54.30#ibcon#about to read 4, iclass 4, count 0 2006.175.08:18:54.30#ibcon#read 4, iclass 4, count 0 2006.175.08:18:54.30#ibcon#about to read 5, iclass 4, count 0 2006.175.08:18:54.30#ibcon#read 5, iclass 4, count 0 2006.175.08:18:54.30#ibcon#about to read 6, iclass 4, count 0 2006.175.08:18:54.30#ibcon#read 6, iclass 4, count 0 2006.175.08:18:54.30#ibcon#end of sib2, iclass 4, count 0 2006.175.08:18:54.30#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:18:54.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:18:54.30#ibcon#[27=USB\r\n] 2006.175.08:18:54.30#ibcon#*before write, iclass 4, count 0 2006.175.08:18:54.30#ibcon#enter sib2, iclass 4, count 0 2006.175.08:18:54.30#ibcon#flushed, iclass 4, count 0 2006.175.08:18:54.30#ibcon#about to write, iclass 4, count 0 2006.175.08:18:54.30#ibcon#wrote, iclass 4, count 0 2006.175.08:18:54.30#ibcon#about to read 3, iclass 4, count 0 2006.175.08:18:54.33#ibcon#read 3, iclass 4, count 0 2006.175.08:18:54.33#ibcon#about to read 4, iclass 4, count 0 2006.175.08:18:54.33#ibcon#read 4, iclass 4, count 0 2006.175.08:18:54.33#ibcon#about to read 5, iclass 4, count 0 2006.175.08:18:54.33#ibcon#read 5, iclass 4, count 0 2006.175.08:18:54.33#ibcon#about to read 6, iclass 4, count 0 2006.175.08:18:54.33#ibcon#read 6, iclass 4, count 0 2006.175.08:18:54.33#ibcon#end of sib2, iclass 4, count 0 2006.175.08:18:54.33#ibcon#*after write, iclass 4, count 0 2006.175.08:18:54.33#ibcon#*before return 0, iclass 4, count 0 2006.175.08:18:54.33#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:54.33#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.175.08:18:54.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:18:54.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:18:54.33$vc4f8/vblo=3,656.99 2006.175.08:18:54.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.175.08:18:54.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.175.08:18:54.33#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:54.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:18:54.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:18:54.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:18:54.33#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:18:54.33#ibcon#first serial, iclass 6, count 0 2006.175.08:18:54.33#ibcon#enter sib2, iclass 6, count 0 2006.175.08:18:54.33#ibcon#flushed, iclass 6, count 0 2006.175.08:18:54.33#ibcon#about to write, iclass 6, count 0 2006.175.08:18:54.33#ibcon#wrote, iclass 6, count 0 2006.175.08:18:54.33#ibcon#about to read 3, iclass 6, count 0 2006.175.08:18:54.35#ibcon#read 3, iclass 6, count 0 2006.175.08:18:54.35#ibcon#about to read 4, iclass 6, count 0 2006.175.08:18:54.35#ibcon#read 4, iclass 6, count 0 2006.175.08:18:54.35#ibcon#about to read 5, iclass 6, count 0 2006.175.08:18:54.35#ibcon#read 5, iclass 6, count 0 2006.175.08:18:54.35#ibcon#about to read 6, iclass 6, count 0 2006.175.08:18:54.35#ibcon#read 6, iclass 6, count 0 2006.175.08:18:54.35#ibcon#end of sib2, iclass 6, count 0 2006.175.08:18:54.35#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:18:54.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:18:54.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:18:54.35#ibcon#*before write, iclass 6, count 0 2006.175.08:18:54.35#ibcon#enter sib2, iclass 6, count 0 2006.175.08:18:54.35#ibcon#flushed, iclass 6, count 0 2006.175.08:18:54.35#ibcon#about to write, iclass 6, count 0 2006.175.08:18:54.35#ibcon#wrote, iclass 6, count 0 2006.175.08:18:54.35#ibcon#about to read 3, iclass 6, count 0 2006.175.08:18:54.39#ibcon#read 3, iclass 6, count 0 2006.175.08:18:54.39#ibcon#about to read 4, iclass 6, count 0 2006.175.08:18:54.39#ibcon#read 4, iclass 6, count 0 2006.175.08:18:54.39#ibcon#about to read 5, iclass 6, count 0 2006.175.08:18:54.39#ibcon#read 5, iclass 6, count 0 2006.175.08:18:54.39#ibcon#about to read 6, iclass 6, count 0 2006.175.08:18:54.39#ibcon#read 6, iclass 6, count 0 2006.175.08:18:54.39#ibcon#end of sib2, iclass 6, count 0 2006.175.08:18:54.39#ibcon#*after write, iclass 6, count 0 2006.175.08:18:54.39#ibcon#*before return 0, iclass 6, count 0 2006.175.08:18:54.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:18:54.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.175.08:18:54.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:18:54.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:18:54.39$vc4f8/vb=3,4 2006.175.08:18:54.39#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.175.08:18:54.39#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.175.08:18:54.39#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:54.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:18:54.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:18:54.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:18:54.45#ibcon#enter wrdev, iclass 10, count 2 2006.175.08:18:54.45#ibcon#first serial, iclass 10, count 2 2006.175.08:18:54.45#ibcon#enter sib2, iclass 10, count 2 2006.175.08:18:54.45#ibcon#flushed, iclass 10, count 2 2006.175.08:18:54.45#ibcon#about to write, iclass 10, count 2 2006.175.08:18:54.45#ibcon#wrote, iclass 10, count 2 2006.175.08:18:54.45#ibcon#about to read 3, iclass 10, count 2 2006.175.08:18:54.47#ibcon#read 3, iclass 10, count 2 2006.175.08:18:54.47#ibcon#about to read 4, iclass 10, count 2 2006.175.08:18:54.47#ibcon#read 4, iclass 10, count 2 2006.175.08:18:54.47#ibcon#about to read 5, iclass 10, count 2 2006.175.08:18:54.47#ibcon#read 5, iclass 10, count 2 2006.175.08:18:54.47#ibcon#about to read 6, iclass 10, count 2 2006.175.08:18:54.47#ibcon#read 6, iclass 10, count 2 2006.175.08:18:54.47#ibcon#end of sib2, iclass 10, count 2 2006.175.08:18:54.47#ibcon#*mode == 0, iclass 10, count 2 2006.175.08:18:54.47#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.175.08:18:54.47#ibcon#[27=AT03-04\r\n] 2006.175.08:18:54.47#ibcon#*before write, iclass 10, count 2 2006.175.08:18:54.47#ibcon#enter sib2, iclass 10, count 2 2006.175.08:18:54.47#ibcon#flushed, iclass 10, count 2 2006.175.08:18:54.47#ibcon#about to write, iclass 10, count 2 2006.175.08:18:54.47#ibcon#wrote, iclass 10, count 2 2006.175.08:18:54.47#ibcon#about to read 3, iclass 10, count 2 2006.175.08:18:54.50#ibcon#read 3, iclass 10, count 2 2006.175.08:18:54.50#ibcon#about to read 4, iclass 10, count 2 2006.175.08:18:54.50#ibcon#read 4, iclass 10, count 2 2006.175.08:18:54.50#ibcon#about to read 5, iclass 10, count 2 2006.175.08:18:54.50#ibcon#read 5, iclass 10, count 2 2006.175.08:18:54.50#ibcon#about to read 6, iclass 10, count 2 2006.175.08:18:54.50#ibcon#read 6, iclass 10, count 2 2006.175.08:18:54.50#ibcon#end of sib2, iclass 10, count 2 2006.175.08:18:54.50#ibcon#*after write, iclass 10, count 2 2006.175.08:18:54.50#ibcon#*before return 0, iclass 10, count 2 2006.175.08:18:54.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:18:54.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.175.08:18:54.50#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.175.08:18:54.50#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:54.50#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:18:54.62#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:18:54.62#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:18:54.62#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:18:54.62#ibcon#first serial, iclass 10, count 0 2006.175.08:18:54.62#ibcon#enter sib2, iclass 10, count 0 2006.175.08:18:54.62#ibcon#flushed, iclass 10, count 0 2006.175.08:18:54.62#ibcon#about to write, iclass 10, count 0 2006.175.08:18:54.62#ibcon#wrote, iclass 10, count 0 2006.175.08:18:54.62#ibcon#about to read 3, iclass 10, count 0 2006.175.08:18:54.64#ibcon#read 3, iclass 10, count 0 2006.175.08:18:54.64#ibcon#about to read 4, iclass 10, count 0 2006.175.08:18:54.64#ibcon#read 4, iclass 10, count 0 2006.175.08:18:54.64#ibcon#about to read 5, iclass 10, count 0 2006.175.08:18:54.64#ibcon#read 5, iclass 10, count 0 2006.175.08:18:54.64#ibcon#about to read 6, iclass 10, count 0 2006.175.08:18:54.64#ibcon#read 6, iclass 10, count 0 2006.175.08:18:54.64#ibcon#end of sib2, iclass 10, count 0 2006.175.08:18:54.64#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:18:54.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:18:54.64#ibcon#[27=USB\r\n] 2006.175.08:18:54.64#ibcon#*before write, iclass 10, count 0 2006.175.08:18:54.64#ibcon#enter sib2, iclass 10, count 0 2006.175.08:18:54.64#ibcon#flushed, iclass 10, count 0 2006.175.08:18:54.64#ibcon#about to write, iclass 10, count 0 2006.175.08:18:54.64#ibcon#wrote, iclass 10, count 0 2006.175.08:18:54.64#ibcon#about to read 3, iclass 10, count 0 2006.175.08:18:54.67#ibcon#read 3, iclass 10, count 0 2006.175.08:18:54.67#ibcon#about to read 4, iclass 10, count 0 2006.175.08:18:54.67#ibcon#read 4, iclass 10, count 0 2006.175.08:18:54.67#ibcon#about to read 5, iclass 10, count 0 2006.175.08:18:54.67#ibcon#read 5, iclass 10, count 0 2006.175.08:18:54.67#ibcon#about to read 6, iclass 10, count 0 2006.175.08:18:54.67#ibcon#read 6, iclass 10, count 0 2006.175.08:18:54.67#ibcon#end of sib2, iclass 10, count 0 2006.175.08:18:54.67#ibcon#*after write, iclass 10, count 0 2006.175.08:18:54.67#ibcon#*before return 0, iclass 10, count 0 2006.175.08:18:54.67#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:18:54.67#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.175.08:18:54.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:18:54.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:18:54.67$vc4f8/vblo=4,712.99 2006.175.08:18:54.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.08:18:54.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.08:18:54.67#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:54.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:54.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:54.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:54.67#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:18:54.67#ibcon#first serial, iclass 12, count 0 2006.175.08:18:54.67#ibcon#enter sib2, iclass 12, count 0 2006.175.08:18:54.67#ibcon#flushed, iclass 12, count 0 2006.175.08:18:54.67#ibcon#about to write, iclass 12, count 0 2006.175.08:18:54.67#ibcon#wrote, iclass 12, count 0 2006.175.08:18:54.67#ibcon#about to read 3, iclass 12, count 0 2006.175.08:18:54.69#ibcon#read 3, iclass 12, count 0 2006.175.08:18:54.69#ibcon#about to read 4, iclass 12, count 0 2006.175.08:18:54.69#ibcon#read 4, iclass 12, count 0 2006.175.08:18:54.69#ibcon#about to read 5, iclass 12, count 0 2006.175.08:18:54.69#ibcon#read 5, iclass 12, count 0 2006.175.08:18:54.69#ibcon#about to read 6, iclass 12, count 0 2006.175.08:18:54.69#ibcon#read 6, iclass 12, count 0 2006.175.08:18:54.69#ibcon#end of sib2, iclass 12, count 0 2006.175.08:18:54.69#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:18:54.69#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:18:54.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:18:54.69#ibcon#*before write, iclass 12, count 0 2006.175.08:18:54.69#ibcon#enter sib2, iclass 12, count 0 2006.175.08:18:54.69#ibcon#flushed, iclass 12, count 0 2006.175.08:18:54.69#ibcon#about to write, iclass 12, count 0 2006.175.08:18:54.69#ibcon#wrote, iclass 12, count 0 2006.175.08:18:54.69#ibcon#about to read 3, iclass 12, count 0 2006.175.08:18:54.73#ibcon#read 3, iclass 12, count 0 2006.175.08:18:54.73#ibcon#about to read 4, iclass 12, count 0 2006.175.08:18:54.73#ibcon#read 4, iclass 12, count 0 2006.175.08:18:54.73#ibcon#about to read 5, iclass 12, count 0 2006.175.08:18:54.73#ibcon#read 5, iclass 12, count 0 2006.175.08:18:54.73#ibcon#about to read 6, iclass 12, count 0 2006.175.08:18:54.73#ibcon#read 6, iclass 12, count 0 2006.175.08:18:54.73#ibcon#end of sib2, iclass 12, count 0 2006.175.08:18:54.73#ibcon#*after write, iclass 12, count 0 2006.175.08:18:54.73#ibcon#*before return 0, iclass 12, count 0 2006.175.08:18:54.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:54.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:18:54.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:18:54.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:18:54.73$vc4f8/vb=4,4 2006.175.08:18:54.73#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.175.08:18:54.73#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.175.08:18:54.73#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:54.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:54.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:54.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:54.79#ibcon#enter wrdev, iclass 14, count 2 2006.175.08:18:54.79#ibcon#first serial, iclass 14, count 2 2006.175.08:18:54.79#ibcon#enter sib2, iclass 14, count 2 2006.175.08:18:54.79#ibcon#flushed, iclass 14, count 2 2006.175.08:18:54.79#ibcon#about to write, iclass 14, count 2 2006.175.08:18:54.79#ibcon#wrote, iclass 14, count 2 2006.175.08:18:54.79#ibcon#about to read 3, iclass 14, count 2 2006.175.08:18:54.81#ibcon#read 3, iclass 14, count 2 2006.175.08:18:54.81#ibcon#about to read 4, iclass 14, count 2 2006.175.08:18:54.81#ibcon#read 4, iclass 14, count 2 2006.175.08:18:54.81#ibcon#about to read 5, iclass 14, count 2 2006.175.08:18:54.81#ibcon#read 5, iclass 14, count 2 2006.175.08:18:54.81#ibcon#about to read 6, iclass 14, count 2 2006.175.08:18:54.81#ibcon#read 6, iclass 14, count 2 2006.175.08:18:54.81#ibcon#end of sib2, iclass 14, count 2 2006.175.08:18:54.81#ibcon#*mode == 0, iclass 14, count 2 2006.175.08:18:54.81#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.175.08:18:54.81#ibcon#[27=AT04-04\r\n] 2006.175.08:18:54.81#ibcon#*before write, iclass 14, count 2 2006.175.08:18:54.81#ibcon#enter sib2, iclass 14, count 2 2006.175.08:18:54.81#ibcon#flushed, iclass 14, count 2 2006.175.08:18:54.81#ibcon#about to write, iclass 14, count 2 2006.175.08:18:54.81#ibcon#wrote, iclass 14, count 2 2006.175.08:18:54.81#ibcon#about to read 3, iclass 14, count 2 2006.175.08:18:54.84#ibcon#read 3, iclass 14, count 2 2006.175.08:18:54.84#ibcon#about to read 4, iclass 14, count 2 2006.175.08:18:54.84#ibcon#read 4, iclass 14, count 2 2006.175.08:18:54.84#ibcon#about to read 5, iclass 14, count 2 2006.175.08:18:54.84#ibcon#read 5, iclass 14, count 2 2006.175.08:18:54.84#ibcon#about to read 6, iclass 14, count 2 2006.175.08:18:54.84#ibcon#read 6, iclass 14, count 2 2006.175.08:18:54.84#ibcon#end of sib2, iclass 14, count 2 2006.175.08:18:54.84#ibcon#*after write, iclass 14, count 2 2006.175.08:18:54.84#ibcon#*before return 0, iclass 14, count 2 2006.175.08:18:54.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:54.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.175.08:18:54.84#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.175.08:18:54.84#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:54.84#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:54.96#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:54.96#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:54.96#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:18:54.96#ibcon#first serial, iclass 14, count 0 2006.175.08:18:54.96#ibcon#enter sib2, iclass 14, count 0 2006.175.08:18:54.96#ibcon#flushed, iclass 14, count 0 2006.175.08:18:54.96#ibcon#about to write, iclass 14, count 0 2006.175.08:18:54.96#ibcon#wrote, iclass 14, count 0 2006.175.08:18:54.96#ibcon#about to read 3, iclass 14, count 0 2006.175.08:18:54.98#ibcon#read 3, iclass 14, count 0 2006.175.08:18:54.98#ibcon#about to read 4, iclass 14, count 0 2006.175.08:18:54.98#ibcon#read 4, iclass 14, count 0 2006.175.08:18:54.98#ibcon#about to read 5, iclass 14, count 0 2006.175.08:18:54.98#ibcon#read 5, iclass 14, count 0 2006.175.08:18:54.98#ibcon#about to read 6, iclass 14, count 0 2006.175.08:18:54.98#ibcon#read 6, iclass 14, count 0 2006.175.08:18:54.98#ibcon#end of sib2, iclass 14, count 0 2006.175.08:18:54.98#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:18:54.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:18:54.98#ibcon#[27=USB\r\n] 2006.175.08:18:54.98#ibcon#*before write, iclass 14, count 0 2006.175.08:18:54.98#ibcon#enter sib2, iclass 14, count 0 2006.175.08:18:54.98#ibcon#flushed, iclass 14, count 0 2006.175.08:18:54.98#ibcon#about to write, iclass 14, count 0 2006.175.08:18:54.98#ibcon#wrote, iclass 14, count 0 2006.175.08:18:54.98#ibcon#about to read 3, iclass 14, count 0 2006.175.08:18:55.01#ibcon#read 3, iclass 14, count 0 2006.175.08:18:55.01#ibcon#about to read 4, iclass 14, count 0 2006.175.08:18:55.01#ibcon#read 4, iclass 14, count 0 2006.175.08:18:55.01#ibcon#about to read 5, iclass 14, count 0 2006.175.08:18:55.01#ibcon#read 5, iclass 14, count 0 2006.175.08:18:55.01#ibcon#about to read 6, iclass 14, count 0 2006.175.08:18:55.01#ibcon#read 6, iclass 14, count 0 2006.175.08:18:55.01#ibcon#end of sib2, iclass 14, count 0 2006.175.08:18:55.01#ibcon#*after write, iclass 14, count 0 2006.175.08:18:55.01#ibcon#*before return 0, iclass 14, count 0 2006.175.08:18:55.01#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:55.01#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.175.08:18:55.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:18:55.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:18:55.01$vc4f8/vblo=5,744.99 2006.175.08:18:55.01#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.175.08:18:55.01#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.175.08:18:55.01#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:55.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:55.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:55.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:55.01#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:18:55.01#ibcon#first serial, iclass 16, count 0 2006.175.08:18:55.01#ibcon#enter sib2, iclass 16, count 0 2006.175.08:18:55.01#ibcon#flushed, iclass 16, count 0 2006.175.08:18:55.01#ibcon#about to write, iclass 16, count 0 2006.175.08:18:55.01#ibcon#wrote, iclass 16, count 0 2006.175.08:18:55.01#ibcon#about to read 3, iclass 16, count 0 2006.175.08:18:55.03#ibcon#read 3, iclass 16, count 0 2006.175.08:18:55.03#ibcon#about to read 4, iclass 16, count 0 2006.175.08:18:55.03#ibcon#read 4, iclass 16, count 0 2006.175.08:18:55.03#ibcon#about to read 5, iclass 16, count 0 2006.175.08:18:55.03#ibcon#read 5, iclass 16, count 0 2006.175.08:18:55.03#ibcon#about to read 6, iclass 16, count 0 2006.175.08:18:55.03#ibcon#read 6, iclass 16, count 0 2006.175.08:18:55.03#ibcon#end of sib2, iclass 16, count 0 2006.175.08:18:55.03#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:18:55.03#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:18:55.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:18:55.03#ibcon#*before write, iclass 16, count 0 2006.175.08:18:55.03#ibcon#enter sib2, iclass 16, count 0 2006.175.08:18:55.03#ibcon#flushed, iclass 16, count 0 2006.175.08:18:55.03#ibcon#about to write, iclass 16, count 0 2006.175.08:18:55.03#ibcon#wrote, iclass 16, count 0 2006.175.08:18:55.03#ibcon#about to read 3, iclass 16, count 0 2006.175.08:18:55.07#ibcon#read 3, iclass 16, count 0 2006.175.08:18:55.07#ibcon#about to read 4, iclass 16, count 0 2006.175.08:18:55.07#ibcon#read 4, iclass 16, count 0 2006.175.08:18:55.07#ibcon#about to read 5, iclass 16, count 0 2006.175.08:18:55.07#ibcon#read 5, iclass 16, count 0 2006.175.08:18:55.07#ibcon#about to read 6, iclass 16, count 0 2006.175.08:18:55.07#ibcon#read 6, iclass 16, count 0 2006.175.08:18:55.07#ibcon#end of sib2, iclass 16, count 0 2006.175.08:18:55.07#ibcon#*after write, iclass 16, count 0 2006.175.08:18:55.07#ibcon#*before return 0, iclass 16, count 0 2006.175.08:18:55.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:55.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.175.08:18:55.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:18:55.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:18:55.07$vc4f8/vb=5,4 2006.175.08:18:55.07#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.175.08:18:55.07#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.175.08:18:55.07#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:55.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:55.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:55.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:55.13#ibcon#enter wrdev, iclass 18, count 2 2006.175.08:18:55.13#ibcon#first serial, iclass 18, count 2 2006.175.08:18:55.13#ibcon#enter sib2, iclass 18, count 2 2006.175.08:18:55.13#ibcon#flushed, iclass 18, count 2 2006.175.08:18:55.13#ibcon#about to write, iclass 18, count 2 2006.175.08:18:55.13#ibcon#wrote, iclass 18, count 2 2006.175.08:18:55.13#ibcon#about to read 3, iclass 18, count 2 2006.175.08:18:55.15#ibcon#read 3, iclass 18, count 2 2006.175.08:18:55.15#ibcon#about to read 4, iclass 18, count 2 2006.175.08:18:55.15#ibcon#read 4, iclass 18, count 2 2006.175.08:18:55.15#ibcon#about to read 5, iclass 18, count 2 2006.175.08:18:55.15#ibcon#read 5, iclass 18, count 2 2006.175.08:18:55.15#ibcon#about to read 6, iclass 18, count 2 2006.175.08:18:55.15#ibcon#read 6, iclass 18, count 2 2006.175.08:18:55.15#ibcon#end of sib2, iclass 18, count 2 2006.175.08:18:55.15#ibcon#*mode == 0, iclass 18, count 2 2006.175.08:18:55.15#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.175.08:18:55.15#ibcon#[27=AT05-04\r\n] 2006.175.08:18:55.15#ibcon#*before write, iclass 18, count 2 2006.175.08:18:55.15#ibcon#enter sib2, iclass 18, count 2 2006.175.08:18:55.15#ibcon#flushed, iclass 18, count 2 2006.175.08:18:55.15#ibcon#about to write, iclass 18, count 2 2006.175.08:18:55.15#ibcon#wrote, iclass 18, count 2 2006.175.08:18:55.15#ibcon#about to read 3, iclass 18, count 2 2006.175.08:18:55.18#ibcon#read 3, iclass 18, count 2 2006.175.08:18:55.18#ibcon#about to read 4, iclass 18, count 2 2006.175.08:18:55.18#ibcon#read 4, iclass 18, count 2 2006.175.08:18:55.18#ibcon#about to read 5, iclass 18, count 2 2006.175.08:18:55.18#ibcon#read 5, iclass 18, count 2 2006.175.08:18:55.18#ibcon#about to read 6, iclass 18, count 2 2006.175.08:18:55.18#ibcon#read 6, iclass 18, count 2 2006.175.08:18:55.18#ibcon#end of sib2, iclass 18, count 2 2006.175.08:18:55.18#ibcon#*after write, iclass 18, count 2 2006.175.08:18:55.18#ibcon#*before return 0, iclass 18, count 2 2006.175.08:18:55.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:55.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.175.08:18:55.18#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.175.08:18:55.18#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:55.18#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:55.30#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:55.30#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:55.30#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:18:55.30#ibcon#first serial, iclass 18, count 0 2006.175.08:18:55.30#ibcon#enter sib2, iclass 18, count 0 2006.175.08:18:55.30#ibcon#flushed, iclass 18, count 0 2006.175.08:18:55.30#ibcon#about to write, iclass 18, count 0 2006.175.08:18:55.30#ibcon#wrote, iclass 18, count 0 2006.175.08:18:55.30#ibcon#about to read 3, iclass 18, count 0 2006.175.08:18:55.32#ibcon#read 3, iclass 18, count 0 2006.175.08:18:55.32#ibcon#about to read 4, iclass 18, count 0 2006.175.08:18:55.32#ibcon#read 4, iclass 18, count 0 2006.175.08:18:55.32#ibcon#about to read 5, iclass 18, count 0 2006.175.08:18:55.32#ibcon#read 5, iclass 18, count 0 2006.175.08:18:55.32#ibcon#about to read 6, iclass 18, count 0 2006.175.08:18:55.32#ibcon#read 6, iclass 18, count 0 2006.175.08:18:55.32#ibcon#end of sib2, iclass 18, count 0 2006.175.08:18:55.32#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:18:55.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:18:55.32#ibcon#[27=USB\r\n] 2006.175.08:18:55.32#ibcon#*before write, iclass 18, count 0 2006.175.08:18:55.32#ibcon#enter sib2, iclass 18, count 0 2006.175.08:18:55.32#ibcon#flushed, iclass 18, count 0 2006.175.08:18:55.32#ibcon#about to write, iclass 18, count 0 2006.175.08:18:55.32#ibcon#wrote, iclass 18, count 0 2006.175.08:18:55.32#ibcon#about to read 3, iclass 18, count 0 2006.175.08:18:55.35#ibcon#read 3, iclass 18, count 0 2006.175.08:18:55.35#ibcon#about to read 4, iclass 18, count 0 2006.175.08:18:55.35#ibcon#read 4, iclass 18, count 0 2006.175.08:18:55.35#ibcon#about to read 5, iclass 18, count 0 2006.175.08:18:55.35#ibcon#read 5, iclass 18, count 0 2006.175.08:18:55.35#ibcon#about to read 6, iclass 18, count 0 2006.175.08:18:55.35#ibcon#read 6, iclass 18, count 0 2006.175.08:18:55.35#ibcon#end of sib2, iclass 18, count 0 2006.175.08:18:55.35#ibcon#*after write, iclass 18, count 0 2006.175.08:18:55.35#ibcon#*before return 0, iclass 18, count 0 2006.175.08:18:55.35#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:55.35#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.175.08:18:55.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:18:55.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:18:55.35$vc4f8/vblo=6,752.99 2006.175.08:18:55.35#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.175.08:18:55.35#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.175.08:18:55.35#ibcon#ireg 17 cls_cnt 0 2006.175.08:18:55.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:55.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:55.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:55.35#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:18:55.35#ibcon#first serial, iclass 20, count 0 2006.175.08:18:55.35#ibcon#enter sib2, iclass 20, count 0 2006.175.08:18:55.35#ibcon#flushed, iclass 20, count 0 2006.175.08:18:55.35#ibcon#about to write, iclass 20, count 0 2006.175.08:18:55.35#ibcon#wrote, iclass 20, count 0 2006.175.08:18:55.35#ibcon#about to read 3, iclass 20, count 0 2006.175.08:18:55.37#ibcon#read 3, iclass 20, count 0 2006.175.08:18:55.37#ibcon#about to read 4, iclass 20, count 0 2006.175.08:18:55.37#ibcon#read 4, iclass 20, count 0 2006.175.08:18:55.37#ibcon#about to read 5, iclass 20, count 0 2006.175.08:18:55.37#ibcon#read 5, iclass 20, count 0 2006.175.08:18:55.37#ibcon#about to read 6, iclass 20, count 0 2006.175.08:18:55.37#ibcon#read 6, iclass 20, count 0 2006.175.08:18:55.37#ibcon#end of sib2, iclass 20, count 0 2006.175.08:18:55.37#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:18:55.37#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:18:55.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:18:55.37#ibcon#*before write, iclass 20, count 0 2006.175.08:18:55.37#ibcon#enter sib2, iclass 20, count 0 2006.175.08:18:55.37#ibcon#flushed, iclass 20, count 0 2006.175.08:18:55.37#ibcon#about to write, iclass 20, count 0 2006.175.08:18:55.37#ibcon#wrote, iclass 20, count 0 2006.175.08:18:55.37#ibcon#about to read 3, iclass 20, count 0 2006.175.08:18:55.41#ibcon#read 3, iclass 20, count 0 2006.175.08:18:55.41#ibcon#about to read 4, iclass 20, count 0 2006.175.08:18:55.41#ibcon#read 4, iclass 20, count 0 2006.175.08:18:55.41#ibcon#about to read 5, iclass 20, count 0 2006.175.08:18:55.41#ibcon#read 5, iclass 20, count 0 2006.175.08:18:55.41#ibcon#about to read 6, iclass 20, count 0 2006.175.08:18:55.41#ibcon#read 6, iclass 20, count 0 2006.175.08:18:55.41#ibcon#end of sib2, iclass 20, count 0 2006.175.08:18:55.41#ibcon#*after write, iclass 20, count 0 2006.175.08:18:55.41#ibcon#*before return 0, iclass 20, count 0 2006.175.08:18:55.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:55.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.175.08:18:55.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:18:55.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:18:55.41$vc4f8/vb=6,4 2006.175.08:18:55.41#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.175.08:18:55.41#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.175.08:18:55.41#ibcon#ireg 11 cls_cnt 2 2006.175.08:18:55.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:55.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:55.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:55.47#ibcon#enter wrdev, iclass 22, count 2 2006.175.08:18:55.47#ibcon#first serial, iclass 22, count 2 2006.175.08:18:55.47#ibcon#enter sib2, iclass 22, count 2 2006.175.08:18:55.47#ibcon#flushed, iclass 22, count 2 2006.175.08:18:55.47#ibcon#about to write, iclass 22, count 2 2006.175.08:18:55.47#ibcon#wrote, iclass 22, count 2 2006.175.08:18:55.47#ibcon#about to read 3, iclass 22, count 2 2006.175.08:18:55.49#ibcon#read 3, iclass 22, count 2 2006.175.08:18:55.49#ibcon#about to read 4, iclass 22, count 2 2006.175.08:18:55.49#ibcon#read 4, iclass 22, count 2 2006.175.08:18:55.49#ibcon#about to read 5, iclass 22, count 2 2006.175.08:18:55.49#ibcon#read 5, iclass 22, count 2 2006.175.08:18:55.49#ibcon#about to read 6, iclass 22, count 2 2006.175.08:18:55.49#ibcon#read 6, iclass 22, count 2 2006.175.08:18:55.49#ibcon#end of sib2, iclass 22, count 2 2006.175.08:18:55.49#ibcon#*mode == 0, iclass 22, count 2 2006.175.08:18:55.49#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.175.08:18:55.49#ibcon#[27=AT06-04\r\n] 2006.175.08:18:55.49#ibcon#*before write, iclass 22, count 2 2006.175.08:18:55.49#ibcon#enter sib2, iclass 22, count 2 2006.175.08:18:55.49#ibcon#flushed, iclass 22, count 2 2006.175.08:18:55.49#ibcon#about to write, iclass 22, count 2 2006.175.08:18:55.49#ibcon#wrote, iclass 22, count 2 2006.175.08:18:55.49#ibcon#about to read 3, iclass 22, count 2 2006.175.08:18:55.52#ibcon#read 3, iclass 22, count 2 2006.175.08:18:55.52#ibcon#about to read 4, iclass 22, count 2 2006.175.08:18:55.52#ibcon#read 4, iclass 22, count 2 2006.175.08:18:55.52#ibcon#about to read 5, iclass 22, count 2 2006.175.08:18:55.52#ibcon#read 5, iclass 22, count 2 2006.175.08:18:55.52#ibcon#about to read 6, iclass 22, count 2 2006.175.08:18:55.52#ibcon#read 6, iclass 22, count 2 2006.175.08:18:55.52#ibcon#end of sib2, iclass 22, count 2 2006.175.08:18:55.52#ibcon#*after write, iclass 22, count 2 2006.175.08:18:55.52#ibcon#*before return 0, iclass 22, count 2 2006.175.08:18:55.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:55.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.175.08:18:55.52#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.175.08:18:55.52#ibcon#ireg 7 cls_cnt 0 2006.175.08:18:55.52#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:55.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:55.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:55.64#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:18:55.64#ibcon#first serial, iclass 22, count 0 2006.175.08:18:55.64#ibcon#enter sib2, iclass 22, count 0 2006.175.08:18:55.64#ibcon#flushed, iclass 22, count 0 2006.175.08:18:55.64#ibcon#about to write, iclass 22, count 0 2006.175.08:18:55.64#ibcon#wrote, iclass 22, count 0 2006.175.08:18:55.64#ibcon#about to read 3, iclass 22, count 0 2006.175.08:18:55.66#ibcon#read 3, iclass 22, count 0 2006.175.08:18:55.66#ibcon#about to read 4, iclass 22, count 0 2006.175.08:18:55.66#ibcon#read 4, iclass 22, count 0 2006.175.08:18:55.66#ibcon#about to read 5, iclass 22, count 0 2006.175.08:18:55.66#ibcon#read 5, iclass 22, count 0 2006.175.08:18:55.66#ibcon#about to read 6, iclass 22, count 0 2006.175.08:18:55.66#ibcon#read 6, iclass 22, count 0 2006.175.08:18:55.66#ibcon#end of sib2, iclass 22, count 0 2006.175.08:18:55.66#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:18:55.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:18:55.66#ibcon#[27=USB\r\n] 2006.175.08:18:55.66#ibcon#*before write, iclass 22, count 0 2006.175.08:18:55.66#ibcon#enter sib2, iclass 22, count 0 2006.175.08:18:55.66#ibcon#flushed, iclass 22, count 0 2006.175.08:18:55.66#ibcon#about to write, iclass 22, count 0 2006.175.08:18:55.66#ibcon#wrote, iclass 22, count 0 2006.175.08:18:55.66#ibcon#about to read 3, iclass 22, count 0 2006.175.08:18:55.69#ibcon#read 3, iclass 22, count 0 2006.175.08:18:55.69#ibcon#about to read 4, iclass 22, count 0 2006.175.08:18:55.69#ibcon#read 4, iclass 22, count 0 2006.175.08:18:55.69#ibcon#about to read 5, iclass 22, count 0 2006.175.08:18:55.69#ibcon#read 5, iclass 22, count 0 2006.175.08:18:55.69#ibcon#about to read 6, iclass 22, count 0 2006.175.08:18:55.69#ibcon#read 6, iclass 22, count 0 2006.175.08:18:55.69#ibcon#end of sib2, iclass 22, count 0 2006.175.08:18:55.69#ibcon#*after write, iclass 22, count 0 2006.175.08:18:55.69#ibcon#*before return 0, iclass 22, count 0 2006.175.08:18:55.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:55.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.175.08:18:55.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:18:55.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:18:55.69$vc4f8/vabw=wide 2006.175.08:18:55.69#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.175.08:18:55.69#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.175.08:18:55.69#ibcon#ireg 8 cls_cnt 0 2006.175.08:18:55.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:55.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:55.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:55.69#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:18:55.69#ibcon#first serial, iclass 24, count 0 2006.175.08:18:55.69#ibcon#enter sib2, iclass 24, count 0 2006.175.08:18:55.69#ibcon#flushed, iclass 24, count 0 2006.175.08:18:55.69#ibcon#about to write, iclass 24, count 0 2006.175.08:18:55.69#ibcon#wrote, iclass 24, count 0 2006.175.08:18:55.69#ibcon#about to read 3, iclass 24, count 0 2006.175.08:18:55.71#ibcon#read 3, iclass 24, count 0 2006.175.08:18:55.71#ibcon#about to read 4, iclass 24, count 0 2006.175.08:18:55.71#ibcon#read 4, iclass 24, count 0 2006.175.08:18:55.71#ibcon#about to read 5, iclass 24, count 0 2006.175.08:18:55.71#ibcon#read 5, iclass 24, count 0 2006.175.08:18:55.71#ibcon#about to read 6, iclass 24, count 0 2006.175.08:18:55.71#ibcon#read 6, iclass 24, count 0 2006.175.08:18:55.71#ibcon#end of sib2, iclass 24, count 0 2006.175.08:18:55.71#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:18:55.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:18:55.71#ibcon#[25=BW32\r\n] 2006.175.08:18:55.71#ibcon#*before write, iclass 24, count 0 2006.175.08:18:55.71#ibcon#enter sib2, iclass 24, count 0 2006.175.08:18:55.71#ibcon#flushed, iclass 24, count 0 2006.175.08:18:55.71#ibcon#about to write, iclass 24, count 0 2006.175.08:18:55.71#ibcon#wrote, iclass 24, count 0 2006.175.08:18:55.71#ibcon#about to read 3, iclass 24, count 0 2006.175.08:18:55.74#ibcon#read 3, iclass 24, count 0 2006.175.08:18:55.74#ibcon#about to read 4, iclass 24, count 0 2006.175.08:18:55.74#ibcon#read 4, iclass 24, count 0 2006.175.08:18:55.74#ibcon#about to read 5, iclass 24, count 0 2006.175.08:18:55.74#ibcon#read 5, iclass 24, count 0 2006.175.08:18:55.74#ibcon#about to read 6, iclass 24, count 0 2006.175.08:18:55.74#ibcon#read 6, iclass 24, count 0 2006.175.08:18:55.74#ibcon#end of sib2, iclass 24, count 0 2006.175.08:18:55.74#ibcon#*after write, iclass 24, count 0 2006.175.08:18:55.74#ibcon#*before return 0, iclass 24, count 0 2006.175.08:18:55.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:55.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.175.08:18:55.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:18:55.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:18:55.74$vc4f8/vbbw=wide 2006.175.08:18:55.74#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.08:18:55.74#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.08:18:55.74#ibcon#ireg 8 cls_cnt 0 2006.175.08:18:55.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:18:55.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:18:55.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:18:55.81#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:18:55.81#ibcon#first serial, iclass 26, count 0 2006.175.08:18:55.81#ibcon#enter sib2, iclass 26, count 0 2006.175.08:18:55.81#ibcon#flushed, iclass 26, count 0 2006.175.08:18:55.81#ibcon#about to write, iclass 26, count 0 2006.175.08:18:55.81#ibcon#wrote, iclass 26, count 0 2006.175.08:18:55.81#ibcon#about to read 3, iclass 26, count 0 2006.175.08:18:55.83#ibcon#read 3, iclass 26, count 0 2006.175.08:18:55.83#ibcon#about to read 4, iclass 26, count 0 2006.175.08:18:55.83#ibcon#read 4, iclass 26, count 0 2006.175.08:18:55.83#ibcon#about to read 5, iclass 26, count 0 2006.175.08:18:55.83#ibcon#read 5, iclass 26, count 0 2006.175.08:18:55.83#ibcon#about to read 6, iclass 26, count 0 2006.175.08:18:55.83#ibcon#read 6, iclass 26, count 0 2006.175.08:18:55.83#ibcon#end of sib2, iclass 26, count 0 2006.175.08:18:55.83#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:18:55.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:18:55.83#ibcon#[27=BW32\r\n] 2006.175.08:18:55.83#ibcon#*before write, iclass 26, count 0 2006.175.08:18:55.83#ibcon#enter sib2, iclass 26, count 0 2006.175.08:18:55.83#ibcon#flushed, iclass 26, count 0 2006.175.08:18:55.83#ibcon#about to write, iclass 26, count 0 2006.175.08:18:55.83#ibcon#wrote, iclass 26, count 0 2006.175.08:18:55.83#ibcon#about to read 3, iclass 26, count 0 2006.175.08:18:55.86#ibcon#read 3, iclass 26, count 0 2006.175.08:18:55.86#ibcon#about to read 4, iclass 26, count 0 2006.175.08:18:55.86#ibcon#read 4, iclass 26, count 0 2006.175.08:18:55.86#ibcon#about to read 5, iclass 26, count 0 2006.175.08:18:55.86#ibcon#read 5, iclass 26, count 0 2006.175.08:18:55.86#ibcon#about to read 6, iclass 26, count 0 2006.175.08:18:55.86#ibcon#read 6, iclass 26, count 0 2006.175.08:18:55.86#ibcon#end of sib2, iclass 26, count 0 2006.175.08:18:55.86#ibcon#*after write, iclass 26, count 0 2006.175.08:18:55.86#ibcon#*before return 0, iclass 26, count 0 2006.175.08:18:55.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:18:55.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:18:55.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:18:55.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:18:55.86$4f8m12a/ifd4f 2006.175.08:18:55.86$ifd4f/lo= 2006.175.08:18:55.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:18:55.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:18:55.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:18:55.86$ifd4f/patch= 2006.175.08:18:55.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:18:55.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:18:55.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:18:55.86$4f8m12a/"form=m,16.000,1:2 2006.175.08:18:55.86$4f8m12a/"tpicd 2006.175.08:18:55.86$4f8m12a/echo=off 2006.175.08:18:55.86$4f8m12a/xlog=off 2006.175.08:18:55.86:!2006.175.08:20:30 2006.175.08:19:01.14#trakl#Source acquired 2006.175.08:19:02.14#flagr#flagr/antenna,acquired 2006.175.08:20:30.00:preob 2006.175.08:20:30.14/onsource/TRACKING 2006.175.08:20:30.14:!2006.175.08:20:40 2006.175.08:20:40.00:data_valid=on 2006.175.08:20:40.00:midob 2006.175.08:20:41.14/onsource/TRACKING 2006.175.08:20:41.14/wx/25.70,1007.4,71 2006.175.08:20:41.30/cable/+6.4787E-03 2006.175.08:20:42.39/va/01,08,usb,yes,28,30 2006.175.08:20:42.39/va/02,07,usb,yes,28,30 2006.175.08:20:42.39/va/03,06,usb,yes,30,30 2006.175.08:20:42.39/va/04,07,usb,yes,29,31 2006.175.08:20:42.39/va/05,07,usb,yes,30,31 2006.175.08:20:42.39/va/06,06,usb,yes,29,28 2006.175.08:20:42.39/va/07,06,usb,yes,29,29 2006.175.08:20:42.39/va/08,06,usb,yes,31,31 2006.175.08:20:42.62/valo/01,532.99,yes,locked 2006.175.08:20:42.62/valo/02,572.99,yes,locked 2006.175.08:20:42.62/valo/03,672.99,yes,locked 2006.175.08:20:42.62/valo/04,832.99,yes,locked 2006.175.08:20:42.62/valo/05,652.99,yes,locked 2006.175.08:20:42.62/valo/06,772.99,yes,locked 2006.175.08:20:42.62/valo/07,832.99,yes,locked 2006.175.08:20:42.62/valo/08,852.99,yes,locked 2006.175.08:20:43.71/vb/01,04,usb,yes,29,27 2006.175.08:20:43.71/vb/02,04,usb,yes,30,32 2006.175.08:20:43.71/vb/03,04,usb,yes,27,30 2006.175.08:20:43.71/vb/04,04,usb,yes,28,28 2006.175.08:20:43.71/vb/05,04,usb,yes,26,30 2006.175.08:20:43.71/vb/06,04,usb,yes,27,30 2006.175.08:20:43.71/vb/07,04,usb,yes,29,29 2006.175.08:20:43.71/vb/08,04,usb,yes,27,30 2006.175.08:20:43.94/vblo/01,632.99,yes,locked 2006.175.08:20:43.94/vblo/02,640.99,yes,locked 2006.175.08:20:43.94/vblo/03,656.99,yes,locked 2006.175.08:20:43.94/vblo/04,712.99,yes,locked 2006.175.08:20:43.94/vblo/05,744.99,yes,locked 2006.175.08:20:43.94/vblo/06,752.99,yes,locked 2006.175.08:20:43.94/vblo/07,734.99,yes,locked 2006.175.08:20:43.94/vblo/08,744.99,yes,locked 2006.175.08:20:44.09/vabw/8 2006.175.08:20:44.24/vbbw/8 2006.175.08:20:44.33/xfe/off,on,14.7 2006.175.08:20:44.70/ifatt/23,28,28,28 2006.175.08:20:45.08/fmout-gps/S +3.81E-07 2006.175.08:20:45.16:!2006.175.08:21:40 2006.175.08:21:40.00:data_valid=off 2006.175.08:21:40.00:postob 2006.175.08:21:40.22/cable/+6.4798E-03 2006.175.08:21:40.22/wx/25.68,1007.4,71 2006.175.08:21:41.07/fmout-gps/S +3.82E-07 2006.175.08:21:41.07:scan_name=175-0824,k06175,60 2006.175.08:21:41.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.175.08:21:41.14#flagr#flagr/antenna,new-source 2006.175.08:21:42.14:checkk5 2006.175.08:21:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:21:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:21:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:21:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:21:44.04/chk_obsdata//k5ts1/T1750820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:21:44.41/chk_obsdata//k5ts2/T1750820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:21:44.78/chk_obsdata//k5ts3/T1750820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:21:45.15/chk_obsdata//k5ts4/T1750820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:21:45.84/k5log//k5ts1_log_newline 2006.175.08:21:46.52/k5log//k5ts2_log_newline 2006.175.08:21:47.22/k5log//k5ts3_log_newline 2006.175.08:21:47.90/k5log//k5ts4_log_newline 2006.175.08:21:47.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:21:47.93:4f8m12a=3 2006.175.08:21:47.93$4f8m12a/echo=on 2006.175.08:21:47.93$4f8m12a/pcalon 2006.175.08:21:47.93$pcalon/"no phase cal control is implemented here 2006.175.08:21:47.93$4f8m12a/"tpicd=stop 2006.175.08:21:47.93$4f8m12a/vc4f8 2006.175.08:21:47.93$vc4f8/valo=1,532.99 2006.175.08:21:47.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.08:21:47.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.08:21:47.93#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:47.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:47.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:47.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:47.93#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:21:47.93#ibcon#first serial, iclass 25, count 0 2006.175.08:21:47.93#ibcon#enter sib2, iclass 25, count 0 2006.175.08:21:47.93#ibcon#flushed, iclass 25, count 0 2006.175.08:21:47.93#ibcon#about to write, iclass 25, count 0 2006.175.08:21:47.93#ibcon#wrote, iclass 25, count 0 2006.175.08:21:47.93#ibcon#about to read 3, iclass 25, count 0 2006.175.08:21:47.98#ibcon#read 3, iclass 25, count 0 2006.175.08:21:47.98#ibcon#about to read 4, iclass 25, count 0 2006.175.08:21:47.98#ibcon#read 4, iclass 25, count 0 2006.175.08:21:47.98#ibcon#about to read 5, iclass 25, count 0 2006.175.08:21:47.98#ibcon#read 5, iclass 25, count 0 2006.175.08:21:47.98#ibcon#about to read 6, iclass 25, count 0 2006.175.08:21:47.98#ibcon#read 6, iclass 25, count 0 2006.175.08:21:47.98#ibcon#end of sib2, iclass 25, count 0 2006.175.08:21:47.98#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:21:47.98#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:21:47.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:21:47.98#ibcon#*before write, iclass 25, count 0 2006.175.08:21:47.98#ibcon#enter sib2, iclass 25, count 0 2006.175.08:21:47.98#ibcon#flushed, iclass 25, count 0 2006.175.08:21:47.98#ibcon#about to write, iclass 25, count 0 2006.175.08:21:47.98#ibcon#wrote, iclass 25, count 0 2006.175.08:21:47.98#ibcon#about to read 3, iclass 25, count 0 2006.175.08:21:48.02#ibcon#read 3, iclass 25, count 0 2006.175.08:21:48.02#ibcon#about to read 4, iclass 25, count 0 2006.175.08:21:48.02#ibcon#read 4, iclass 25, count 0 2006.175.08:21:48.02#ibcon#about to read 5, iclass 25, count 0 2006.175.08:21:48.02#ibcon#read 5, iclass 25, count 0 2006.175.08:21:48.02#ibcon#about to read 6, iclass 25, count 0 2006.175.08:21:48.02#ibcon#read 6, iclass 25, count 0 2006.175.08:21:48.02#ibcon#end of sib2, iclass 25, count 0 2006.175.08:21:48.02#ibcon#*after write, iclass 25, count 0 2006.175.08:21:48.02#ibcon#*before return 0, iclass 25, count 0 2006.175.08:21:48.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:48.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:48.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:21:48.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:21:48.02$vc4f8/va=1,8 2006.175.08:21:48.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.08:21:48.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.08:21:48.02#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:48.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:48.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:48.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:48.02#ibcon#enter wrdev, iclass 27, count 2 2006.175.08:21:48.02#ibcon#first serial, iclass 27, count 2 2006.175.08:21:48.02#ibcon#enter sib2, iclass 27, count 2 2006.175.08:21:48.02#ibcon#flushed, iclass 27, count 2 2006.175.08:21:48.02#ibcon#about to write, iclass 27, count 2 2006.175.08:21:48.02#ibcon#wrote, iclass 27, count 2 2006.175.08:21:48.02#ibcon#about to read 3, iclass 27, count 2 2006.175.08:21:48.04#ibcon#read 3, iclass 27, count 2 2006.175.08:21:48.04#ibcon#about to read 4, iclass 27, count 2 2006.175.08:21:48.04#ibcon#read 4, iclass 27, count 2 2006.175.08:21:48.04#ibcon#about to read 5, iclass 27, count 2 2006.175.08:21:48.04#ibcon#read 5, iclass 27, count 2 2006.175.08:21:48.04#ibcon#about to read 6, iclass 27, count 2 2006.175.08:21:48.04#ibcon#read 6, iclass 27, count 2 2006.175.08:21:48.04#ibcon#end of sib2, iclass 27, count 2 2006.175.08:21:48.04#ibcon#*mode == 0, iclass 27, count 2 2006.175.08:21:48.04#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.08:21:48.04#ibcon#[25=AT01-08\r\n] 2006.175.08:21:48.04#ibcon#*before write, iclass 27, count 2 2006.175.08:21:48.04#ibcon#enter sib2, iclass 27, count 2 2006.175.08:21:48.04#ibcon#flushed, iclass 27, count 2 2006.175.08:21:48.04#ibcon#about to write, iclass 27, count 2 2006.175.08:21:48.04#ibcon#wrote, iclass 27, count 2 2006.175.08:21:48.04#ibcon#about to read 3, iclass 27, count 2 2006.175.08:21:48.07#ibcon#read 3, iclass 27, count 2 2006.175.08:21:48.07#ibcon#about to read 4, iclass 27, count 2 2006.175.08:21:48.07#ibcon#read 4, iclass 27, count 2 2006.175.08:21:48.07#ibcon#about to read 5, iclass 27, count 2 2006.175.08:21:48.07#ibcon#read 5, iclass 27, count 2 2006.175.08:21:48.07#ibcon#about to read 6, iclass 27, count 2 2006.175.08:21:48.07#ibcon#read 6, iclass 27, count 2 2006.175.08:21:48.07#ibcon#end of sib2, iclass 27, count 2 2006.175.08:21:48.07#ibcon#*after write, iclass 27, count 2 2006.175.08:21:48.07#ibcon#*before return 0, iclass 27, count 2 2006.175.08:21:48.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:48.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:48.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.08:21:48.07#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:48.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:48.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:48.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:48.19#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:21:48.19#ibcon#first serial, iclass 27, count 0 2006.175.08:21:48.19#ibcon#enter sib2, iclass 27, count 0 2006.175.08:21:48.19#ibcon#flushed, iclass 27, count 0 2006.175.08:21:48.19#ibcon#about to write, iclass 27, count 0 2006.175.08:21:48.19#ibcon#wrote, iclass 27, count 0 2006.175.08:21:48.19#ibcon#about to read 3, iclass 27, count 0 2006.175.08:21:48.21#ibcon#read 3, iclass 27, count 0 2006.175.08:21:48.21#ibcon#about to read 4, iclass 27, count 0 2006.175.08:21:48.21#ibcon#read 4, iclass 27, count 0 2006.175.08:21:48.21#ibcon#about to read 5, iclass 27, count 0 2006.175.08:21:48.21#ibcon#read 5, iclass 27, count 0 2006.175.08:21:48.21#ibcon#about to read 6, iclass 27, count 0 2006.175.08:21:48.21#ibcon#read 6, iclass 27, count 0 2006.175.08:21:48.21#ibcon#end of sib2, iclass 27, count 0 2006.175.08:21:48.21#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:21:48.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:21:48.21#ibcon#[25=USB\r\n] 2006.175.08:21:48.21#ibcon#*before write, iclass 27, count 0 2006.175.08:21:48.21#ibcon#enter sib2, iclass 27, count 0 2006.175.08:21:48.21#ibcon#flushed, iclass 27, count 0 2006.175.08:21:48.21#ibcon#about to write, iclass 27, count 0 2006.175.08:21:48.21#ibcon#wrote, iclass 27, count 0 2006.175.08:21:48.21#ibcon#about to read 3, iclass 27, count 0 2006.175.08:21:48.24#ibcon#read 3, iclass 27, count 0 2006.175.08:21:48.24#ibcon#about to read 4, iclass 27, count 0 2006.175.08:21:48.24#ibcon#read 4, iclass 27, count 0 2006.175.08:21:48.24#ibcon#about to read 5, iclass 27, count 0 2006.175.08:21:48.24#ibcon#read 5, iclass 27, count 0 2006.175.08:21:48.24#ibcon#about to read 6, iclass 27, count 0 2006.175.08:21:48.24#ibcon#read 6, iclass 27, count 0 2006.175.08:21:48.24#ibcon#end of sib2, iclass 27, count 0 2006.175.08:21:48.24#ibcon#*after write, iclass 27, count 0 2006.175.08:21:48.24#ibcon#*before return 0, iclass 27, count 0 2006.175.08:21:48.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:48.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:48.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:21:48.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:21:48.24$vc4f8/valo=2,572.99 2006.175.08:21:48.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.08:21:48.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.08:21:48.24#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:48.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:48.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:48.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:48.24#ibcon#enter wrdev, iclass 29, count 0 2006.175.08:21:48.24#ibcon#first serial, iclass 29, count 0 2006.175.08:21:48.24#ibcon#enter sib2, iclass 29, count 0 2006.175.08:21:48.24#ibcon#flushed, iclass 29, count 0 2006.175.08:21:48.24#ibcon#about to write, iclass 29, count 0 2006.175.08:21:48.24#ibcon#wrote, iclass 29, count 0 2006.175.08:21:48.24#ibcon#about to read 3, iclass 29, count 0 2006.175.08:21:48.26#ibcon#read 3, iclass 29, count 0 2006.175.08:21:48.26#ibcon#about to read 4, iclass 29, count 0 2006.175.08:21:48.26#ibcon#read 4, iclass 29, count 0 2006.175.08:21:48.26#ibcon#about to read 5, iclass 29, count 0 2006.175.08:21:48.26#ibcon#read 5, iclass 29, count 0 2006.175.08:21:48.26#ibcon#about to read 6, iclass 29, count 0 2006.175.08:21:48.26#ibcon#read 6, iclass 29, count 0 2006.175.08:21:48.26#ibcon#end of sib2, iclass 29, count 0 2006.175.08:21:48.26#ibcon#*mode == 0, iclass 29, count 0 2006.175.08:21:48.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.08:21:48.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:21:48.26#ibcon#*before write, iclass 29, count 0 2006.175.08:21:48.26#ibcon#enter sib2, iclass 29, count 0 2006.175.08:21:48.26#ibcon#flushed, iclass 29, count 0 2006.175.08:21:48.26#ibcon#about to write, iclass 29, count 0 2006.175.08:21:48.26#ibcon#wrote, iclass 29, count 0 2006.175.08:21:48.26#ibcon#about to read 3, iclass 29, count 0 2006.175.08:21:48.30#ibcon#read 3, iclass 29, count 0 2006.175.08:21:48.30#ibcon#about to read 4, iclass 29, count 0 2006.175.08:21:48.30#ibcon#read 4, iclass 29, count 0 2006.175.08:21:48.30#ibcon#about to read 5, iclass 29, count 0 2006.175.08:21:48.30#ibcon#read 5, iclass 29, count 0 2006.175.08:21:48.30#ibcon#about to read 6, iclass 29, count 0 2006.175.08:21:48.30#ibcon#read 6, iclass 29, count 0 2006.175.08:21:48.30#ibcon#end of sib2, iclass 29, count 0 2006.175.08:21:48.30#ibcon#*after write, iclass 29, count 0 2006.175.08:21:48.30#ibcon#*before return 0, iclass 29, count 0 2006.175.08:21:48.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:48.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:48.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.08:21:48.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.08:21:48.30$vc4f8/va=2,7 2006.175.08:21:48.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.08:21:48.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.08:21:48.30#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:48.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:48.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:48.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:48.36#ibcon#enter wrdev, iclass 31, count 2 2006.175.08:21:48.36#ibcon#first serial, iclass 31, count 2 2006.175.08:21:48.36#ibcon#enter sib2, iclass 31, count 2 2006.175.08:21:48.36#ibcon#flushed, iclass 31, count 2 2006.175.08:21:48.36#ibcon#about to write, iclass 31, count 2 2006.175.08:21:48.36#ibcon#wrote, iclass 31, count 2 2006.175.08:21:48.36#ibcon#about to read 3, iclass 31, count 2 2006.175.08:21:48.38#ibcon#read 3, iclass 31, count 2 2006.175.08:21:48.38#ibcon#about to read 4, iclass 31, count 2 2006.175.08:21:48.38#ibcon#read 4, iclass 31, count 2 2006.175.08:21:48.38#ibcon#about to read 5, iclass 31, count 2 2006.175.08:21:48.38#ibcon#read 5, iclass 31, count 2 2006.175.08:21:48.38#ibcon#about to read 6, iclass 31, count 2 2006.175.08:21:48.38#ibcon#read 6, iclass 31, count 2 2006.175.08:21:48.38#ibcon#end of sib2, iclass 31, count 2 2006.175.08:21:48.38#ibcon#*mode == 0, iclass 31, count 2 2006.175.08:21:48.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.08:21:48.38#ibcon#[25=AT02-07\r\n] 2006.175.08:21:48.38#ibcon#*before write, iclass 31, count 2 2006.175.08:21:48.38#ibcon#enter sib2, iclass 31, count 2 2006.175.08:21:48.38#ibcon#flushed, iclass 31, count 2 2006.175.08:21:48.38#ibcon#about to write, iclass 31, count 2 2006.175.08:21:48.38#ibcon#wrote, iclass 31, count 2 2006.175.08:21:48.38#ibcon#about to read 3, iclass 31, count 2 2006.175.08:21:48.41#ibcon#read 3, iclass 31, count 2 2006.175.08:21:48.41#ibcon#about to read 4, iclass 31, count 2 2006.175.08:21:48.41#ibcon#read 4, iclass 31, count 2 2006.175.08:21:48.41#ibcon#about to read 5, iclass 31, count 2 2006.175.08:21:48.41#ibcon#read 5, iclass 31, count 2 2006.175.08:21:48.41#ibcon#about to read 6, iclass 31, count 2 2006.175.08:21:48.41#ibcon#read 6, iclass 31, count 2 2006.175.08:21:48.41#ibcon#end of sib2, iclass 31, count 2 2006.175.08:21:48.41#ibcon#*after write, iclass 31, count 2 2006.175.08:21:48.41#ibcon#*before return 0, iclass 31, count 2 2006.175.08:21:48.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:48.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:48.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.08:21:48.41#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:48.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:48.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:48.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:48.53#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:21:48.53#ibcon#first serial, iclass 31, count 0 2006.175.08:21:48.53#ibcon#enter sib2, iclass 31, count 0 2006.175.08:21:48.53#ibcon#flushed, iclass 31, count 0 2006.175.08:21:48.53#ibcon#about to write, iclass 31, count 0 2006.175.08:21:48.53#ibcon#wrote, iclass 31, count 0 2006.175.08:21:48.53#ibcon#about to read 3, iclass 31, count 0 2006.175.08:21:48.55#ibcon#read 3, iclass 31, count 0 2006.175.08:21:48.55#ibcon#about to read 4, iclass 31, count 0 2006.175.08:21:48.55#ibcon#read 4, iclass 31, count 0 2006.175.08:21:48.55#ibcon#about to read 5, iclass 31, count 0 2006.175.08:21:48.55#ibcon#read 5, iclass 31, count 0 2006.175.08:21:48.55#ibcon#about to read 6, iclass 31, count 0 2006.175.08:21:48.55#ibcon#read 6, iclass 31, count 0 2006.175.08:21:48.55#ibcon#end of sib2, iclass 31, count 0 2006.175.08:21:48.55#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:21:48.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:21:48.55#ibcon#[25=USB\r\n] 2006.175.08:21:48.55#ibcon#*before write, iclass 31, count 0 2006.175.08:21:48.55#ibcon#enter sib2, iclass 31, count 0 2006.175.08:21:48.55#ibcon#flushed, iclass 31, count 0 2006.175.08:21:48.55#ibcon#about to write, iclass 31, count 0 2006.175.08:21:48.55#ibcon#wrote, iclass 31, count 0 2006.175.08:21:48.55#ibcon#about to read 3, iclass 31, count 0 2006.175.08:21:48.58#ibcon#read 3, iclass 31, count 0 2006.175.08:21:48.58#ibcon#about to read 4, iclass 31, count 0 2006.175.08:21:48.58#ibcon#read 4, iclass 31, count 0 2006.175.08:21:48.58#ibcon#about to read 5, iclass 31, count 0 2006.175.08:21:48.58#ibcon#read 5, iclass 31, count 0 2006.175.08:21:48.58#ibcon#about to read 6, iclass 31, count 0 2006.175.08:21:48.58#ibcon#read 6, iclass 31, count 0 2006.175.08:21:48.58#ibcon#end of sib2, iclass 31, count 0 2006.175.08:21:48.58#ibcon#*after write, iclass 31, count 0 2006.175.08:21:48.58#ibcon#*before return 0, iclass 31, count 0 2006.175.08:21:48.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:48.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:48.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:21:48.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:21:48.58$vc4f8/valo=3,672.99 2006.175.08:21:48.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.08:21:48.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.08:21:48.58#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:48.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:48.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:48.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:48.58#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:21:48.58#ibcon#first serial, iclass 33, count 0 2006.175.08:21:48.58#ibcon#enter sib2, iclass 33, count 0 2006.175.08:21:48.58#ibcon#flushed, iclass 33, count 0 2006.175.08:21:48.58#ibcon#about to write, iclass 33, count 0 2006.175.08:21:48.58#ibcon#wrote, iclass 33, count 0 2006.175.08:21:48.58#ibcon#about to read 3, iclass 33, count 0 2006.175.08:21:48.60#ibcon#read 3, iclass 33, count 0 2006.175.08:21:48.60#ibcon#about to read 4, iclass 33, count 0 2006.175.08:21:48.60#ibcon#read 4, iclass 33, count 0 2006.175.08:21:48.60#ibcon#about to read 5, iclass 33, count 0 2006.175.08:21:48.60#ibcon#read 5, iclass 33, count 0 2006.175.08:21:48.60#ibcon#about to read 6, iclass 33, count 0 2006.175.08:21:48.60#ibcon#read 6, iclass 33, count 0 2006.175.08:21:48.60#ibcon#end of sib2, iclass 33, count 0 2006.175.08:21:48.60#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:21:48.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:21:48.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:21:48.60#ibcon#*before write, iclass 33, count 0 2006.175.08:21:48.60#ibcon#enter sib2, iclass 33, count 0 2006.175.08:21:48.60#ibcon#flushed, iclass 33, count 0 2006.175.08:21:48.60#ibcon#about to write, iclass 33, count 0 2006.175.08:21:48.60#ibcon#wrote, iclass 33, count 0 2006.175.08:21:48.60#ibcon#about to read 3, iclass 33, count 0 2006.175.08:21:48.64#ibcon#read 3, iclass 33, count 0 2006.175.08:21:48.64#ibcon#about to read 4, iclass 33, count 0 2006.175.08:21:48.64#ibcon#read 4, iclass 33, count 0 2006.175.08:21:48.64#ibcon#about to read 5, iclass 33, count 0 2006.175.08:21:48.64#ibcon#read 5, iclass 33, count 0 2006.175.08:21:48.64#ibcon#about to read 6, iclass 33, count 0 2006.175.08:21:48.64#ibcon#read 6, iclass 33, count 0 2006.175.08:21:48.64#ibcon#end of sib2, iclass 33, count 0 2006.175.08:21:48.64#ibcon#*after write, iclass 33, count 0 2006.175.08:21:48.64#ibcon#*before return 0, iclass 33, count 0 2006.175.08:21:48.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:48.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:48.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:21:48.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:21:48.64$vc4f8/va=3,6 2006.175.08:21:48.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.175.08:21:48.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.175.08:21:48.64#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:48.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:48.70#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:48.70#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:48.70#ibcon#enter wrdev, iclass 35, count 2 2006.175.08:21:48.70#ibcon#first serial, iclass 35, count 2 2006.175.08:21:48.70#ibcon#enter sib2, iclass 35, count 2 2006.175.08:21:48.70#ibcon#flushed, iclass 35, count 2 2006.175.08:21:48.70#ibcon#about to write, iclass 35, count 2 2006.175.08:21:48.70#ibcon#wrote, iclass 35, count 2 2006.175.08:21:48.70#ibcon#about to read 3, iclass 35, count 2 2006.175.08:21:48.72#ibcon#read 3, iclass 35, count 2 2006.175.08:21:48.72#ibcon#about to read 4, iclass 35, count 2 2006.175.08:21:48.72#ibcon#read 4, iclass 35, count 2 2006.175.08:21:48.72#ibcon#about to read 5, iclass 35, count 2 2006.175.08:21:48.72#ibcon#read 5, iclass 35, count 2 2006.175.08:21:48.72#ibcon#about to read 6, iclass 35, count 2 2006.175.08:21:48.72#ibcon#read 6, iclass 35, count 2 2006.175.08:21:48.72#ibcon#end of sib2, iclass 35, count 2 2006.175.08:21:48.72#ibcon#*mode == 0, iclass 35, count 2 2006.175.08:21:48.72#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.175.08:21:48.72#ibcon#[25=AT03-06\r\n] 2006.175.08:21:48.72#ibcon#*before write, iclass 35, count 2 2006.175.08:21:48.72#ibcon#enter sib2, iclass 35, count 2 2006.175.08:21:48.72#ibcon#flushed, iclass 35, count 2 2006.175.08:21:48.72#ibcon#about to write, iclass 35, count 2 2006.175.08:21:48.72#ibcon#wrote, iclass 35, count 2 2006.175.08:21:48.72#ibcon#about to read 3, iclass 35, count 2 2006.175.08:21:48.75#ibcon#read 3, iclass 35, count 2 2006.175.08:21:48.75#ibcon#about to read 4, iclass 35, count 2 2006.175.08:21:48.75#ibcon#read 4, iclass 35, count 2 2006.175.08:21:48.75#ibcon#about to read 5, iclass 35, count 2 2006.175.08:21:48.75#ibcon#read 5, iclass 35, count 2 2006.175.08:21:48.75#ibcon#about to read 6, iclass 35, count 2 2006.175.08:21:48.75#ibcon#read 6, iclass 35, count 2 2006.175.08:21:48.75#ibcon#end of sib2, iclass 35, count 2 2006.175.08:21:48.75#ibcon#*after write, iclass 35, count 2 2006.175.08:21:48.75#ibcon#*before return 0, iclass 35, count 2 2006.175.08:21:48.75#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:48.75#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:48.75#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.175.08:21:48.75#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:48.75#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:48.87#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:48.87#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:48.87#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:21:48.87#ibcon#first serial, iclass 35, count 0 2006.175.08:21:48.87#ibcon#enter sib2, iclass 35, count 0 2006.175.08:21:48.87#ibcon#flushed, iclass 35, count 0 2006.175.08:21:48.87#ibcon#about to write, iclass 35, count 0 2006.175.08:21:48.87#ibcon#wrote, iclass 35, count 0 2006.175.08:21:48.87#ibcon#about to read 3, iclass 35, count 0 2006.175.08:21:48.89#ibcon#read 3, iclass 35, count 0 2006.175.08:21:48.89#ibcon#about to read 4, iclass 35, count 0 2006.175.08:21:48.89#ibcon#read 4, iclass 35, count 0 2006.175.08:21:48.89#ibcon#about to read 5, iclass 35, count 0 2006.175.08:21:48.89#ibcon#read 5, iclass 35, count 0 2006.175.08:21:48.89#ibcon#about to read 6, iclass 35, count 0 2006.175.08:21:48.89#ibcon#read 6, iclass 35, count 0 2006.175.08:21:48.89#ibcon#end of sib2, iclass 35, count 0 2006.175.08:21:48.89#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:21:48.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:21:48.89#ibcon#[25=USB\r\n] 2006.175.08:21:48.89#ibcon#*before write, iclass 35, count 0 2006.175.08:21:48.89#ibcon#enter sib2, iclass 35, count 0 2006.175.08:21:48.89#ibcon#flushed, iclass 35, count 0 2006.175.08:21:48.89#ibcon#about to write, iclass 35, count 0 2006.175.08:21:48.89#ibcon#wrote, iclass 35, count 0 2006.175.08:21:48.89#ibcon#about to read 3, iclass 35, count 0 2006.175.08:21:48.92#ibcon#read 3, iclass 35, count 0 2006.175.08:21:48.92#ibcon#about to read 4, iclass 35, count 0 2006.175.08:21:48.92#ibcon#read 4, iclass 35, count 0 2006.175.08:21:48.92#ibcon#about to read 5, iclass 35, count 0 2006.175.08:21:48.92#ibcon#read 5, iclass 35, count 0 2006.175.08:21:48.92#ibcon#about to read 6, iclass 35, count 0 2006.175.08:21:48.92#ibcon#read 6, iclass 35, count 0 2006.175.08:21:48.92#ibcon#end of sib2, iclass 35, count 0 2006.175.08:21:48.92#ibcon#*after write, iclass 35, count 0 2006.175.08:21:48.92#ibcon#*before return 0, iclass 35, count 0 2006.175.08:21:48.92#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:48.92#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:48.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:21:48.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:21:48.92$vc4f8/valo=4,832.99 2006.175.08:21:48.92#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.08:21:48.92#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.08:21:48.92#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:48.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:48.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:48.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:48.92#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:21:48.92#ibcon#first serial, iclass 37, count 0 2006.175.08:21:48.92#ibcon#enter sib2, iclass 37, count 0 2006.175.08:21:48.92#ibcon#flushed, iclass 37, count 0 2006.175.08:21:48.92#ibcon#about to write, iclass 37, count 0 2006.175.08:21:48.92#ibcon#wrote, iclass 37, count 0 2006.175.08:21:48.92#ibcon#about to read 3, iclass 37, count 0 2006.175.08:21:48.94#ibcon#read 3, iclass 37, count 0 2006.175.08:21:48.94#ibcon#about to read 4, iclass 37, count 0 2006.175.08:21:48.94#ibcon#read 4, iclass 37, count 0 2006.175.08:21:48.94#ibcon#about to read 5, iclass 37, count 0 2006.175.08:21:48.94#ibcon#read 5, iclass 37, count 0 2006.175.08:21:48.94#ibcon#about to read 6, iclass 37, count 0 2006.175.08:21:48.94#ibcon#read 6, iclass 37, count 0 2006.175.08:21:48.94#ibcon#end of sib2, iclass 37, count 0 2006.175.08:21:48.94#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:21:48.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:21:48.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:21:48.94#ibcon#*before write, iclass 37, count 0 2006.175.08:21:48.94#ibcon#enter sib2, iclass 37, count 0 2006.175.08:21:48.94#ibcon#flushed, iclass 37, count 0 2006.175.08:21:48.94#ibcon#about to write, iclass 37, count 0 2006.175.08:21:48.94#ibcon#wrote, iclass 37, count 0 2006.175.08:21:48.94#ibcon#about to read 3, iclass 37, count 0 2006.175.08:21:48.98#ibcon#read 3, iclass 37, count 0 2006.175.08:21:48.98#ibcon#about to read 4, iclass 37, count 0 2006.175.08:21:48.98#ibcon#read 4, iclass 37, count 0 2006.175.08:21:48.98#ibcon#about to read 5, iclass 37, count 0 2006.175.08:21:48.98#ibcon#read 5, iclass 37, count 0 2006.175.08:21:48.98#ibcon#about to read 6, iclass 37, count 0 2006.175.08:21:48.98#ibcon#read 6, iclass 37, count 0 2006.175.08:21:48.98#ibcon#end of sib2, iclass 37, count 0 2006.175.08:21:48.98#ibcon#*after write, iclass 37, count 0 2006.175.08:21:48.98#ibcon#*before return 0, iclass 37, count 0 2006.175.08:21:48.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:48.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:48.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:21:48.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:21:48.98$vc4f8/va=4,7 2006.175.08:21:48.98#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.175.08:21:48.98#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.175.08:21:48.98#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:48.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:49.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:49.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:49.04#ibcon#enter wrdev, iclass 39, count 2 2006.175.08:21:49.04#ibcon#first serial, iclass 39, count 2 2006.175.08:21:49.04#ibcon#enter sib2, iclass 39, count 2 2006.175.08:21:49.04#ibcon#flushed, iclass 39, count 2 2006.175.08:21:49.04#ibcon#about to write, iclass 39, count 2 2006.175.08:21:49.04#ibcon#wrote, iclass 39, count 2 2006.175.08:21:49.04#ibcon#about to read 3, iclass 39, count 2 2006.175.08:21:49.06#ibcon#read 3, iclass 39, count 2 2006.175.08:21:49.06#ibcon#about to read 4, iclass 39, count 2 2006.175.08:21:49.06#ibcon#read 4, iclass 39, count 2 2006.175.08:21:49.06#ibcon#about to read 5, iclass 39, count 2 2006.175.08:21:49.06#ibcon#read 5, iclass 39, count 2 2006.175.08:21:49.06#ibcon#about to read 6, iclass 39, count 2 2006.175.08:21:49.06#ibcon#read 6, iclass 39, count 2 2006.175.08:21:49.06#ibcon#end of sib2, iclass 39, count 2 2006.175.08:21:49.06#ibcon#*mode == 0, iclass 39, count 2 2006.175.08:21:49.06#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.175.08:21:49.06#ibcon#[25=AT04-07\r\n] 2006.175.08:21:49.06#ibcon#*before write, iclass 39, count 2 2006.175.08:21:49.06#ibcon#enter sib2, iclass 39, count 2 2006.175.08:21:49.06#ibcon#flushed, iclass 39, count 2 2006.175.08:21:49.06#ibcon#about to write, iclass 39, count 2 2006.175.08:21:49.06#ibcon#wrote, iclass 39, count 2 2006.175.08:21:49.06#ibcon#about to read 3, iclass 39, count 2 2006.175.08:21:49.09#ibcon#read 3, iclass 39, count 2 2006.175.08:21:49.09#ibcon#about to read 4, iclass 39, count 2 2006.175.08:21:49.09#ibcon#read 4, iclass 39, count 2 2006.175.08:21:49.09#ibcon#about to read 5, iclass 39, count 2 2006.175.08:21:49.09#ibcon#read 5, iclass 39, count 2 2006.175.08:21:49.09#ibcon#about to read 6, iclass 39, count 2 2006.175.08:21:49.09#ibcon#read 6, iclass 39, count 2 2006.175.08:21:49.09#ibcon#end of sib2, iclass 39, count 2 2006.175.08:21:49.09#ibcon#*after write, iclass 39, count 2 2006.175.08:21:49.09#ibcon#*before return 0, iclass 39, count 2 2006.175.08:21:49.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:49.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:49.09#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.175.08:21:49.09#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:49.09#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:49.21#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:49.21#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:49.21#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:21:49.21#ibcon#first serial, iclass 39, count 0 2006.175.08:21:49.21#ibcon#enter sib2, iclass 39, count 0 2006.175.08:21:49.21#ibcon#flushed, iclass 39, count 0 2006.175.08:21:49.21#ibcon#about to write, iclass 39, count 0 2006.175.08:21:49.21#ibcon#wrote, iclass 39, count 0 2006.175.08:21:49.21#ibcon#about to read 3, iclass 39, count 0 2006.175.08:21:49.23#ibcon#read 3, iclass 39, count 0 2006.175.08:21:49.23#ibcon#about to read 4, iclass 39, count 0 2006.175.08:21:49.23#ibcon#read 4, iclass 39, count 0 2006.175.08:21:49.23#ibcon#about to read 5, iclass 39, count 0 2006.175.08:21:49.23#ibcon#read 5, iclass 39, count 0 2006.175.08:21:49.23#ibcon#about to read 6, iclass 39, count 0 2006.175.08:21:49.23#ibcon#read 6, iclass 39, count 0 2006.175.08:21:49.23#ibcon#end of sib2, iclass 39, count 0 2006.175.08:21:49.23#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:21:49.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:21:49.23#ibcon#[25=USB\r\n] 2006.175.08:21:49.23#ibcon#*before write, iclass 39, count 0 2006.175.08:21:49.23#ibcon#enter sib2, iclass 39, count 0 2006.175.08:21:49.23#ibcon#flushed, iclass 39, count 0 2006.175.08:21:49.23#ibcon#about to write, iclass 39, count 0 2006.175.08:21:49.23#ibcon#wrote, iclass 39, count 0 2006.175.08:21:49.23#ibcon#about to read 3, iclass 39, count 0 2006.175.08:21:49.26#ibcon#read 3, iclass 39, count 0 2006.175.08:21:49.26#ibcon#about to read 4, iclass 39, count 0 2006.175.08:21:49.26#ibcon#read 4, iclass 39, count 0 2006.175.08:21:49.26#ibcon#about to read 5, iclass 39, count 0 2006.175.08:21:49.26#ibcon#read 5, iclass 39, count 0 2006.175.08:21:49.26#ibcon#about to read 6, iclass 39, count 0 2006.175.08:21:49.26#ibcon#read 6, iclass 39, count 0 2006.175.08:21:49.26#ibcon#end of sib2, iclass 39, count 0 2006.175.08:21:49.26#ibcon#*after write, iclass 39, count 0 2006.175.08:21:49.26#ibcon#*before return 0, iclass 39, count 0 2006.175.08:21:49.26#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:49.26#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:49.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:21:49.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:21:49.26$vc4f8/valo=5,652.99 2006.175.08:21:49.26#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.08:21:49.26#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.08:21:49.26#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:49.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:49.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:49.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:49.26#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:21:49.26#ibcon#first serial, iclass 3, count 0 2006.175.08:21:49.26#ibcon#enter sib2, iclass 3, count 0 2006.175.08:21:49.26#ibcon#flushed, iclass 3, count 0 2006.175.08:21:49.26#ibcon#about to write, iclass 3, count 0 2006.175.08:21:49.26#ibcon#wrote, iclass 3, count 0 2006.175.08:21:49.26#ibcon#about to read 3, iclass 3, count 0 2006.175.08:21:49.28#ibcon#read 3, iclass 3, count 0 2006.175.08:21:49.28#ibcon#about to read 4, iclass 3, count 0 2006.175.08:21:49.28#ibcon#read 4, iclass 3, count 0 2006.175.08:21:49.28#ibcon#about to read 5, iclass 3, count 0 2006.175.08:21:49.28#ibcon#read 5, iclass 3, count 0 2006.175.08:21:49.28#ibcon#about to read 6, iclass 3, count 0 2006.175.08:21:49.28#ibcon#read 6, iclass 3, count 0 2006.175.08:21:49.28#ibcon#end of sib2, iclass 3, count 0 2006.175.08:21:49.28#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:21:49.28#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:21:49.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:21:49.28#ibcon#*before write, iclass 3, count 0 2006.175.08:21:49.28#ibcon#enter sib2, iclass 3, count 0 2006.175.08:21:49.28#ibcon#flushed, iclass 3, count 0 2006.175.08:21:49.28#ibcon#about to write, iclass 3, count 0 2006.175.08:21:49.28#ibcon#wrote, iclass 3, count 0 2006.175.08:21:49.28#ibcon#about to read 3, iclass 3, count 0 2006.175.08:21:49.32#ibcon#read 3, iclass 3, count 0 2006.175.08:21:49.32#ibcon#about to read 4, iclass 3, count 0 2006.175.08:21:49.32#ibcon#read 4, iclass 3, count 0 2006.175.08:21:49.32#ibcon#about to read 5, iclass 3, count 0 2006.175.08:21:49.32#ibcon#read 5, iclass 3, count 0 2006.175.08:21:49.32#ibcon#about to read 6, iclass 3, count 0 2006.175.08:21:49.32#ibcon#read 6, iclass 3, count 0 2006.175.08:21:49.32#ibcon#end of sib2, iclass 3, count 0 2006.175.08:21:49.32#ibcon#*after write, iclass 3, count 0 2006.175.08:21:49.32#ibcon#*before return 0, iclass 3, count 0 2006.175.08:21:49.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:49.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:49.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:21:49.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:21:49.32$vc4f8/va=5,7 2006.175.08:21:49.32#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.175.08:21:49.32#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.175.08:21:49.32#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:49.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:49.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:49.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:49.38#ibcon#enter wrdev, iclass 5, count 2 2006.175.08:21:49.38#ibcon#first serial, iclass 5, count 2 2006.175.08:21:49.38#ibcon#enter sib2, iclass 5, count 2 2006.175.08:21:49.38#ibcon#flushed, iclass 5, count 2 2006.175.08:21:49.38#ibcon#about to write, iclass 5, count 2 2006.175.08:21:49.38#ibcon#wrote, iclass 5, count 2 2006.175.08:21:49.38#ibcon#about to read 3, iclass 5, count 2 2006.175.08:21:49.40#ibcon#read 3, iclass 5, count 2 2006.175.08:21:49.40#ibcon#about to read 4, iclass 5, count 2 2006.175.08:21:49.40#ibcon#read 4, iclass 5, count 2 2006.175.08:21:49.40#ibcon#about to read 5, iclass 5, count 2 2006.175.08:21:49.40#ibcon#read 5, iclass 5, count 2 2006.175.08:21:49.40#ibcon#about to read 6, iclass 5, count 2 2006.175.08:21:49.40#ibcon#read 6, iclass 5, count 2 2006.175.08:21:49.40#ibcon#end of sib2, iclass 5, count 2 2006.175.08:21:49.40#ibcon#*mode == 0, iclass 5, count 2 2006.175.08:21:49.40#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.175.08:21:49.40#ibcon#[25=AT05-07\r\n] 2006.175.08:21:49.40#ibcon#*before write, iclass 5, count 2 2006.175.08:21:49.40#ibcon#enter sib2, iclass 5, count 2 2006.175.08:21:49.40#ibcon#flushed, iclass 5, count 2 2006.175.08:21:49.40#ibcon#about to write, iclass 5, count 2 2006.175.08:21:49.40#ibcon#wrote, iclass 5, count 2 2006.175.08:21:49.40#ibcon#about to read 3, iclass 5, count 2 2006.175.08:21:49.43#ibcon#read 3, iclass 5, count 2 2006.175.08:21:49.43#ibcon#about to read 4, iclass 5, count 2 2006.175.08:21:49.43#ibcon#read 4, iclass 5, count 2 2006.175.08:21:49.43#ibcon#about to read 5, iclass 5, count 2 2006.175.08:21:49.43#ibcon#read 5, iclass 5, count 2 2006.175.08:21:49.43#ibcon#about to read 6, iclass 5, count 2 2006.175.08:21:49.43#ibcon#read 6, iclass 5, count 2 2006.175.08:21:49.44#ibcon#end of sib2, iclass 5, count 2 2006.175.08:21:49.44#ibcon#*after write, iclass 5, count 2 2006.175.08:21:49.44#ibcon#*before return 0, iclass 5, count 2 2006.175.08:21:49.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:49.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:49.44#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.175.08:21:49.44#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:49.44#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:49.55#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:49.55#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:49.55#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:21:49.55#ibcon#first serial, iclass 5, count 0 2006.175.08:21:49.55#ibcon#enter sib2, iclass 5, count 0 2006.175.08:21:49.55#ibcon#flushed, iclass 5, count 0 2006.175.08:21:49.55#ibcon#about to write, iclass 5, count 0 2006.175.08:21:49.55#ibcon#wrote, iclass 5, count 0 2006.175.08:21:49.55#ibcon#about to read 3, iclass 5, count 0 2006.175.08:21:49.57#ibcon#read 3, iclass 5, count 0 2006.175.08:21:49.57#ibcon#about to read 4, iclass 5, count 0 2006.175.08:21:49.57#ibcon#read 4, iclass 5, count 0 2006.175.08:21:49.57#ibcon#about to read 5, iclass 5, count 0 2006.175.08:21:49.57#ibcon#read 5, iclass 5, count 0 2006.175.08:21:49.57#ibcon#about to read 6, iclass 5, count 0 2006.175.08:21:49.57#ibcon#read 6, iclass 5, count 0 2006.175.08:21:49.57#ibcon#end of sib2, iclass 5, count 0 2006.175.08:21:49.57#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:21:49.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:21:49.57#ibcon#[25=USB\r\n] 2006.175.08:21:49.57#ibcon#*before write, iclass 5, count 0 2006.175.08:21:49.57#ibcon#enter sib2, iclass 5, count 0 2006.175.08:21:49.57#ibcon#flushed, iclass 5, count 0 2006.175.08:21:49.57#ibcon#about to write, iclass 5, count 0 2006.175.08:21:49.57#ibcon#wrote, iclass 5, count 0 2006.175.08:21:49.57#ibcon#about to read 3, iclass 5, count 0 2006.175.08:21:49.60#ibcon#read 3, iclass 5, count 0 2006.175.08:21:49.60#ibcon#about to read 4, iclass 5, count 0 2006.175.08:21:49.60#ibcon#read 4, iclass 5, count 0 2006.175.08:21:49.60#ibcon#about to read 5, iclass 5, count 0 2006.175.08:21:49.60#ibcon#read 5, iclass 5, count 0 2006.175.08:21:49.60#ibcon#about to read 6, iclass 5, count 0 2006.175.08:21:49.60#ibcon#read 6, iclass 5, count 0 2006.175.08:21:49.60#ibcon#end of sib2, iclass 5, count 0 2006.175.08:21:49.60#ibcon#*after write, iclass 5, count 0 2006.175.08:21:49.60#ibcon#*before return 0, iclass 5, count 0 2006.175.08:21:49.60#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:49.60#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:49.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:21:49.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:21:49.60$vc4f8/valo=6,772.99 2006.175.08:21:49.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.08:21:49.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.08:21:49.60#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:49.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:49.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:49.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:49.60#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:21:49.60#ibcon#first serial, iclass 7, count 0 2006.175.08:21:49.60#ibcon#enter sib2, iclass 7, count 0 2006.175.08:21:49.60#ibcon#flushed, iclass 7, count 0 2006.175.08:21:49.60#ibcon#about to write, iclass 7, count 0 2006.175.08:21:49.60#ibcon#wrote, iclass 7, count 0 2006.175.08:21:49.60#ibcon#about to read 3, iclass 7, count 0 2006.175.08:21:49.62#ibcon#read 3, iclass 7, count 0 2006.175.08:21:49.62#ibcon#about to read 4, iclass 7, count 0 2006.175.08:21:49.62#ibcon#read 4, iclass 7, count 0 2006.175.08:21:49.62#ibcon#about to read 5, iclass 7, count 0 2006.175.08:21:49.62#ibcon#read 5, iclass 7, count 0 2006.175.08:21:49.62#ibcon#about to read 6, iclass 7, count 0 2006.175.08:21:49.62#ibcon#read 6, iclass 7, count 0 2006.175.08:21:49.62#ibcon#end of sib2, iclass 7, count 0 2006.175.08:21:49.62#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:21:49.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:21:49.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:21:49.62#ibcon#*before write, iclass 7, count 0 2006.175.08:21:49.62#ibcon#enter sib2, iclass 7, count 0 2006.175.08:21:49.62#ibcon#flushed, iclass 7, count 0 2006.175.08:21:49.62#ibcon#about to write, iclass 7, count 0 2006.175.08:21:49.62#ibcon#wrote, iclass 7, count 0 2006.175.08:21:49.62#ibcon#about to read 3, iclass 7, count 0 2006.175.08:21:49.66#ibcon#read 3, iclass 7, count 0 2006.175.08:21:49.66#ibcon#about to read 4, iclass 7, count 0 2006.175.08:21:49.66#ibcon#read 4, iclass 7, count 0 2006.175.08:21:49.66#ibcon#about to read 5, iclass 7, count 0 2006.175.08:21:49.66#ibcon#read 5, iclass 7, count 0 2006.175.08:21:49.66#ibcon#about to read 6, iclass 7, count 0 2006.175.08:21:49.66#ibcon#read 6, iclass 7, count 0 2006.175.08:21:49.66#ibcon#end of sib2, iclass 7, count 0 2006.175.08:21:49.66#ibcon#*after write, iclass 7, count 0 2006.175.08:21:49.66#ibcon#*before return 0, iclass 7, count 0 2006.175.08:21:49.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:49.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:49.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:21:49.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:21:49.66$vc4f8/va=6,6 2006.175.08:21:49.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.175.08:21:49.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.175.08:21:49.66#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:49.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:21:49.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:21:49.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:21:49.72#ibcon#enter wrdev, iclass 11, count 2 2006.175.08:21:49.72#ibcon#first serial, iclass 11, count 2 2006.175.08:21:49.72#ibcon#enter sib2, iclass 11, count 2 2006.175.08:21:49.72#ibcon#flushed, iclass 11, count 2 2006.175.08:21:49.72#ibcon#about to write, iclass 11, count 2 2006.175.08:21:49.72#ibcon#wrote, iclass 11, count 2 2006.175.08:21:49.72#ibcon#about to read 3, iclass 11, count 2 2006.175.08:21:49.74#ibcon#read 3, iclass 11, count 2 2006.175.08:21:49.74#ibcon#about to read 4, iclass 11, count 2 2006.175.08:21:49.74#ibcon#read 4, iclass 11, count 2 2006.175.08:21:49.74#ibcon#about to read 5, iclass 11, count 2 2006.175.08:21:49.74#ibcon#read 5, iclass 11, count 2 2006.175.08:21:49.74#ibcon#about to read 6, iclass 11, count 2 2006.175.08:21:49.74#ibcon#read 6, iclass 11, count 2 2006.175.08:21:49.74#ibcon#end of sib2, iclass 11, count 2 2006.175.08:21:49.74#ibcon#*mode == 0, iclass 11, count 2 2006.175.08:21:49.74#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.175.08:21:49.74#ibcon#[25=AT06-06\r\n] 2006.175.08:21:49.74#ibcon#*before write, iclass 11, count 2 2006.175.08:21:49.74#ibcon#enter sib2, iclass 11, count 2 2006.175.08:21:49.74#ibcon#flushed, iclass 11, count 2 2006.175.08:21:49.74#ibcon#about to write, iclass 11, count 2 2006.175.08:21:49.74#ibcon#wrote, iclass 11, count 2 2006.175.08:21:49.74#ibcon#about to read 3, iclass 11, count 2 2006.175.08:21:49.77#ibcon#read 3, iclass 11, count 2 2006.175.08:21:49.77#ibcon#about to read 4, iclass 11, count 2 2006.175.08:21:49.77#ibcon#read 4, iclass 11, count 2 2006.175.08:21:49.77#ibcon#about to read 5, iclass 11, count 2 2006.175.08:21:49.77#ibcon#read 5, iclass 11, count 2 2006.175.08:21:49.77#ibcon#about to read 6, iclass 11, count 2 2006.175.08:21:49.77#ibcon#read 6, iclass 11, count 2 2006.175.08:21:49.77#ibcon#end of sib2, iclass 11, count 2 2006.175.08:21:49.77#ibcon#*after write, iclass 11, count 2 2006.175.08:21:49.77#ibcon#*before return 0, iclass 11, count 2 2006.175.08:21:49.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:21:49.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.175.08:21:49.77#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.175.08:21:49.77#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:49.77#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:21:49.89#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:21:49.89#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:21:49.89#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:21:49.89#ibcon#first serial, iclass 11, count 0 2006.175.08:21:49.89#ibcon#enter sib2, iclass 11, count 0 2006.175.08:21:49.89#ibcon#flushed, iclass 11, count 0 2006.175.08:21:49.89#ibcon#about to write, iclass 11, count 0 2006.175.08:21:49.89#ibcon#wrote, iclass 11, count 0 2006.175.08:21:49.89#ibcon#about to read 3, iclass 11, count 0 2006.175.08:21:49.91#ibcon#read 3, iclass 11, count 0 2006.175.08:21:49.91#ibcon#about to read 4, iclass 11, count 0 2006.175.08:21:49.91#ibcon#read 4, iclass 11, count 0 2006.175.08:21:49.91#ibcon#about to read 5, iclass 11, count 0 2006.175.08:21:49.91#ibcon#read 5, iclass 11, count 0 2006.175.08:21:49.91#ibcon#about to read 6, iclass 11, count 0 2006.175.08:21:49.91#ibcon#read 6, iclass 11, count 0 2006.175.08:21:49.91#ibcon#end of sib2, iclass 11, count 0 2006.175.08:21:49.91#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:21:49.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:21:49.91#ibcon#[25=USB\r\n] 2006.175.08:21:49.91#ibcon#*before write, iclass 11, count 0 2006.175.08:21:49.91#ibcon#enter sib2, iclass 11, count 0 2006.175.08:21:49.91#ibcon#flushed, iclass 11, count 0 2006.175.08:21:49.91#ibcon#about to write, iclass 11, count 0 2006.175.08:21:49.91#ibcon#wrote, iclass 11, count 0 2006.175.08:21:49.91#ibcon#about to read 3, iclass 11, count 0 2006.175.08:21:49.94#ibcon#read 3, iclass 11, count 0 2006.175.08:21:49.94#ibcon#about to read 4, iclass 11, count 0 2006.175.08:21:49.94#ibcon#read 4, iclass 11, count 0 2006.175.08:21:49.94#ibcon#about to read 5, iclass 11, count 0 2006.175.08:21:49.94#ibcon#read 5, iclass 11, count 0 2006.175.08:21:49.94#ibcon#about to read 6, iclass 11, count 0 2006.175.08:21:49.94#ibcon#read 6, iclass 11, count 0 2006.175.08:21:49.94#ibcon#end of sib2, iclass 11, count 0 2006.175.08:21:49.94#ibcon#*after write, iclass 11, count 0 2006.175.08:21:49.94#ibcon#*before return 0, iclass 11, count 0 2006.175.08:21:49.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:21:49.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.175.08:21:49.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:21:49.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:21:49.94$vc4f8/valo=7,832.99 2006.175.08:21:49.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.175.08:21:49.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.175.08:21:49.94#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:49.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:21:49.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:21:49.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:21:49.94#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:21:49.94#ibcon#first serial, iclass 13, count 0 2006.175.08:21:49.94#ibcon#enter sib2, iclass 13, count 0 2006.175.08:21:49.94#ibcon#flushed, iclass 13, count 0 2006.175.08:21:49.94#ibcon#about to write, iclass 13, count 0 2006.175.08:21:49.94#ibcon#wrote, iclass 13, count 0 2006.175.08:21:49.94#ibcon#about to read 3, iclass 13, count 0 2006.175.08:21:49.96#ibcon#read 3, iclass 13, count 0 2006.175.08:21:49.96#ibcon#about to read 4, iclass 13, count 0 2006.175.08:21:49.96#ibcon#read 4, iclass 13, count 0 2006.175.08:21:49.96#ibcon#about to read 5, iclass 13, count 0 2006.175.08:21:49.96#ibcon#read 5, iclass 13, count 0 2006.175.08:21:49.96#ibcon#about to read 6, iclass 13, count 0 2006.175.08:21:49.96#ibcon#read 6, iclass 13, count 0 2006.175.08:21:49.96#ibcon#end of sib2, iclass 13, count 0 2006.175.08:21:49.96#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:21:49.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:21:49.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:21:49.96#ibcon#*before write, iclass 13, count 0 2006.175.08:21:49.96#ibcon#enter sib2, iclass 13, count 0 2006.175.08:21:49.96#ibcon#flushed, iclass 13, count 0 2006.175.08:21:49.96#ibcon#about to write, iclass 13, count 0 2006.175.08:21:49.96#ibcon#wrote, iclass 13, count 0 2006.175.08:21:49.96#ibcon#about to read 3, iclass 13, count 0 2006.175.08:21:50.00#ibcon#read 3, iclass 13, count 0 2006.175.08:21:50.00#ibcon#about to read 4, iclass 13, count 0 2006.175.08:21:50.00#ibcon#read 4, iclass 13, count 0 2006.175.08:21:50.00#ibcon#about to read 5, iclass 13, count 0 2006.175.08:21:50.00#ibcon#read 5, iclass 13, count 0 2006.175.08:21:50.00#ibcon#about to read 6, iclass 13, count 0 2006.175.08:21:50.00#ibcon#read 6, iclass 13, count 0 2006.175.08:21:50.00#ibcon#end of sib2, iclass 13, count 0 2006.175.08:21:50.00#ibcon#*after write, iclass 13, count 0 2006.175.08:21:50.00#ibcon#*before return 0, iclass 13, count 0 2006.175.08:21:50.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:21:50.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.175.08:21:50.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:21:50.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:21:50.00$vc4f8/va=7,6 2006.175.08:21:50.00#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.175.08:21:50.00#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.175.08:21:50.00#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:50.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:21:50.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:21:50.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:21:50.06#ibcon#enter wrdev, iclass 15, count 2 2006.175.08:21:50.06#ibcon#first serial, iclass 15, count 2 2006.175.08:21:50.06#ibcon#enter sib2, iclass 15, count 2 2006.175.08:21:50.06#ibcon#flushed, iclass 15, count 2 2006.175.08:21:50.06#ibcon#about to write, iclass 15, count 2 2006.175.08:21:50.06#ibcon#wrote, iclass 15, count 2 2006.175.08:21:50.06#ibcon#about to read 3, iclass 15, count 2 2006.175.08:21:50.08#ibcon#read 3, iclass 15, count 2 2006.175.08:21:50.08#ibcon#about to read 4, iclass 15, count 2 2006.175.08:21:50.08#ibcon#read 4, iclass 15, count 2 2006.175.08:21:50.08#ibcon#about to read 5, iclass 15, count 2 2006.175.08:21:50.08#ibcon#read 5, iclass 15, count 2 2006.175.08:21:50.08#ibcon#about to read 6, iclass 15, count 2 2006.175.08:21:50.08#ibcon#read 6, iclass 15, count 2 2006.175.08:21:50.08#ibcon#end of sib2, iclass 15, count 2 2006.175.08:21:50.08#ibcon#*mode == 0, iclass 15, count 2 2006.175.08:21:50.08#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.175.08:21:50.08#ibcon#[25=AT07-06\r\n] 2006.175.08:21:50.08#ibcon#*before write, iclass 15, count 2 2006.175.08:21:50.08#ibcon#enter sib2, iclass 15, count 2 2006.175.08:21:50.08#ibcon#flushed, iclass 15, count 2 2006.175.08:21:50.08#ibcon#about to write, iclass 15, count 2 2006.175.08:21:50.08#ibcon#wrote, iclass 15, count 2 2006.175.08:21:50.08#ibcon#about to read 3, iclass 15, count 2 2006.175.08:21:50.11#ibcon#read 3, iclass 15, count 2 2006.175.08:21:50.11#ibcon#about to read 4, iclass 15, count 2 2006.175.08:21:50.11#ibcon#read 4, iclass 15, count 2 2006.175.08:21:50.11#ibcon#about to read 5, iclass 15, count 2 2006.175.08:21:50.11#ibcon#read 5, iclass 15, count 2 2006.175.08:21:50.11#ibcon#about to read 6, iclass 15, count 2 2006.175.08:21:50.11#ibcon#read 6, iclass 15, count 2 2006.175.08:21:50.11#ibcon#end of sib2, iclass 15, count 2 2006.175.08:21:50.11#ibcon#*after write, iclass 15, count 2 2006.175.08:21:50.11#ibcon#*before return 0, iclass 15, count 2 2006.175.08:21:50.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:21:50.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.175.08:21:50.11#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.175.08:21:50.11#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:50.11#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:21:50.23#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:21:50.23#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:21:50.23#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:21:50.23#ibcon#first serial, iclass 15, count 0 2006.175.08:21:50.23#ibcon#enter sib2, iclass 15, count 0 2006.175.08:21:50.23#ibcon#flushed, iclass 15, count 0 2006.175.08:21:50.23#ibcon#about to write, iclass 15, count 0 2006.175.08:21:50.23#ibcon#wrote, iclass 15, count 0 2006.175.08:21:50.23#ibcon#about to read 3, iclass 15, count 0 2006.175.08:21:50.27#ibcon#read 3, iclass 15, count 0 2006.175.08:21:50.27#ibcon#about to read 4, iclass 15, count 0 2006.175.08:21:50.27#ibcon#read 4, iclass 15, count 0 2006.175.08:21:50.27#ibcon#about to read 5, iclass 15, count 0 2006.175.08:21:50.27#ibcon#read 5, iclass 15, count 0 2006.175.08:21:50.27#ibcon#about to read 6, iclass 15, count 0 2006.175.08:21:50.27#ibcon#read 6, iclass 15, count 0 2006.175.08:21:50.27#ibcon#end of sib2, iclass 15, count 0 2006.175.08:21:50.27#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:21:50.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:21:50.27#ibcon#[25=USB\r\n] 2006.175.08:21:50.27#ibcon#*before write, iclass 15, count 0 2006.175.08:21:50.27#ibcon#enter sib2, iclass 15, count 0 2006.175.08:21:50.27#ibcon#flushed, iclass 15, count 0 2006.175.08:21:50.27#ibcon#about to write, iclass 15, count 0 2006.175.08:21:50.27#ibcon#wrote, iclass 15, count 0 2006.175.08:21:50.27#ibcon#about to read 3, iclass 15, count 0 2006.175.08:21:50.30#ibcon#read 3, iclass 15, count 0 2006.175.08:21:50.30#ibcon#about to read 4, iclass 15, count 0 2006.175.08:21:50.30#ibcon#read 4, iclass 15, count 0 2006.175.08:21:50.30#ibcon#about to read 5, iclass 15, count 0 2006.175.08:21:50.30#ibcon#read 5, iclass 15, count 0 2006.175.08:21:50.30#ibcon#about to read 6, iclass 15, count 0 2006.175.08:21:50.30#ibcon#read 6, iclass 15, count 0 2006.175.08:21:50.30#ibcon#end of sib2, iclass 15, count 0 2006.175.08:21:50.30#ibcon#*after write, iclass 15, count 0 2006.175.08:21:50.30#ibcon#*before return 0, iclass 15, count 0 2006.175.08:21:50.30#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:21:50.30#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.175.08:21:50.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:21:50.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:21:50.30$vc4f8/valo=8,852.99 2006.175.08:21:50.30#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.175.08:21:50.30#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.175.08:21:50.30#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:50.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:21:50.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:21:50.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:21:50.30#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:21:50.30#ibcon#first serial, iclass 17, count 0 2006.175.08:21:50.30#ibcon#enter sib2, iclass 17, count 0 2006.175.08:21:50.30#ibcon#flushed, iclass 17, count 0 2006.175.08:21:50.30#ibcon#about to write, iclass 17, count 0 2006.175.08:21:50.30#ibcon#wrote, iclass 17, count 0 2006.175.08:21:50.30#ibcon#about to read 3, iclass 17, count 0 2006.175.08:21:50.33#ibcon#read 3, iclass 17, count 0 2006.175.08:21:50.33#ibcon#about to read 4, iclass 17, count 0 2006.175.08:21:50.33#ibcon#read 4, iclass 17, count 0 2006.175.08:21:50.33#ibcon#about to read 5, iclass 17, count 0 2006.175.08:21:50.33#ibcon#read 5, iclass 17, count 0 2006.175.08:21:50.33#ibcon#about to read 6, iclass 17, count 0 2006.175.08:21:50.33#ibcon#read 6, iclass 17, count 0 2006.175.08:21:50.33#ibcon#end of sib2, iclass 17, count 0 2006.175.08:21:50.33#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:21:50.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:21:50.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:21:50.33#ibcon#*before write, iclass 17, count 0 2006.175.08:21:50.33#ibcon#enter sib2, iclass 17, count 0 2006.175.08:21:50.33#ibcon#flushed, iclass 17, count 0 2006.175.08:21:50.33#ibcon#about to write, iclass 17, count 0 2006.175.08:21:50.33#ibcon#wrote, iclass 17, count 0 2006.175.08:21:50.33#ibcon#about to read 3, iclass 17, count 0 2006.175.08:21:50.37#ibcon#read 3, iclass 17, count 0 2006.175.08:21:50.37#ibcon#about to read 4, iclass 17, count 0 2006.175.08:21:50.37#ibcon#read 4, iclass 17, count 0 2006.175.08:21:50.37#ibcon#about to read 5, iclass 17, count 0 2006.175.08:21:50.37#ibcon#read 5, iclass 17, count 0 2006.175.08:21:50.37#ibcon#about to read 6, iclass 17, count 0 2006.175.08:21:50.37#ibcon#read 6, iclass 17, count 0 2006.175.08:21:50.37#ibcon#end of sib2, iclass 17, count 0 2006.175.08:21:50.37#ibcon#*after write, iclass 17, count 0 2006.175.08:21:50.37#ibcon#*before return 0, iclass 17, count 0 2006.175.08:21:50.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:21:50.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.175.08:21:50.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:21:50.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:21:50.37$vc4f8/va=8,6 2006.175.08:21:50.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.175.08:21:50.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.175.08:21:50.37#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:50.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:21:50.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:21:50.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:21:50.42#ibcon#enter wrdev, iclass 19, count 2 2006.175.08:21:50.42#ibcon#first serial, iclass 19, count 2 2006.175.08:21:50.42#ibcon#enter sib2, iclass 19, count 2 2006.175.08:21:50.42#ibcon#flushed, iclass 19, count 2 2006.175.08:21:50.42#ibcon#about to write, iclass 19, count 2 2006.175.08:21:50.42#ibcon#wrote, iclass 19, count 2 2006.175.08:21:50.42#ibcon#about to read 3, iclass 19, count 2 2006.175.08:21:50.44#ibcon#read 3, iclass 19, count 2 2006.175.08:21:50.44#ibcon#about to read 4, iclass 19, count 2 2006.175.08:21:50.44#ibcon#read 4, iclass 19, count 2 2006.175.08:21:50.44#ibcon#about to read 5, iclass 19, count 2 2006.175.08:21:50.44#ibcon#read 5, iclass 19, count 2 2006.175.08:21:50.44#ibcon#about to read 6, iclass 19, count 2 2006.175.08:21:50.44#ibcon#read 6, iclass 19, count 2 2006.175.08:21:50.44#ibcon#end of sib2, iclass 19, count 2 2006.175.08:21:50.44#ibcon#*mode == 0, iclass 19, count 2 2006.175.08:21:50.44#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.175.08:21:50.44#ibcon#[25=AT08-06\r\n] 2006.175.08:21:50.44#ibcon#*before write, iclass 19, count 2 2006.175.08:21:50.44#ibcon#enter sib2, iclass 19, count 2 2006.175.08:21:50.44#ibcon#flushed, iclass 19, count 2 2006.175.08:21:50.44#ibcon#about to write, iclass 19, count 2 2006.175.08:21:50.44#ibcon#wrote, iclass 19, count 2 2006.175.08:21:50.44#ibcon#about to read 3, iclass 19, count 2 2006.175.08:21:50.47#ibcon#read 3, iclass 19, count 2 2006.175.08:21:50.47#ibcon#about to read 4, iclass 19, count 2 2006.175.08:21:50.47#ibcon#read 4, iclass 19, count 2 2006.175.08:21:50.47#ibcon#about to read 5, iclass 19, count 2 2006.175.08:21:50.47#ibcon#read 5, iclass 19, count 2 2006.175.08:21:50.47#ibcon#about to read 6, iclass 19, count 2 2006.175.08:21:50.47#ibcon#read 6, iclass 19, count 2 2006.175.08:21:50.47#ibcon#end of sib2, iclass 19, count 2 2006.175.08:21:50.47#ibcon#*after write, iclass 19, count 2 2006.175.08:21:50.47#ibcon#*before return 0, iclass 19, count 2 2006.175.08:21:50.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:21:50.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.175.08:21:50.47#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.175.08:21:50.47#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:50.47#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:21:50.59#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:21:50.59#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:21:50.59#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:21:50.59#ibcon#first serial, iclass 19, count 0 2006.175.08:21:50.59#ibcon#enter sib2, iclass 19, count 0 2006.175.08:21:50.59#ibcon#flushed, iclass 19, count 0 2006.175.08:21:50.59#ibcon#about to write, iclass 19, count 0 2006.175.08:21:50.59#ibcon#wrote, iclass 19, count 0 2006.175.08:21:50.59#ibcon#about to read 3, iclass 19, count 0 2006.175.08:21:50.61#ibcon#read 3, iclass 19, count 0 2006.175.08:21:50.61#ibcon#about to read 4, iclass 19, count 0 2006.175.08:21:50.61#ibcon#read 4, iclass 19, count 0 2006.175.08:21:50.61#ibcon#about to read 5, iclass 19, count 0 2006.175.08:21:50.61#ibcon#read 5, iclass 19, count 0 2006.175.08:21:50.61#ibcon#about to read 6, iclass 19, count 0 2006.175.08:21:50.61#ibcon#read 6, iclass 19, count 0 2006.175.08:21:50.61#ibcon#end of sib2, iclass 19, count 0 2006.175.08:21:50.61#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:21:50.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:21:50.61#ibcon#[25=USB\r\n] 2006.175.08:21:50.61#ibcon#*before write, iclass 19, count 0 2006.175.08:21:50.61#ibcon#enter sib2, iclass 19, count 0 2006.175.08:21:50.61#ibcon#flushed, iclass 19, count 0 2006.175.08:21:50.61#ibcon#about to write, iclass 19, count 0 2006.175.08:21:50.61#ibcon#wrote, iclass 19, count 0 2006.175.08:21:50.61#ibcon#about to read 3, iclass 19, count 0 2006.175.08:21:50.64#ibcon#read 3, iclass 19, count 0 2006.175.08:21:50.64#ibcon#about to read 4, iclass 19, count 0 2006.175.08:21:50.64#ibcon#read 4, iclass 19, count 0 2006.175.08:21:50.64#ibcon#about to read 5, iclass 19, count 0 2006.175.08:21:50.64#ibcon#read 5, iclass 19, count 0 2006.175.08:21:50.64#ibcon#about to read 6, iclass 19, count 0 2006.175.08:21:50.64#ibcon#read 6, iclass 19, count 0 2006.175.08:21:50.64#ibcon#end of sib2, iclass 19, count 0 2006.175.08:21:50.64#ibcon#*after write, iclass 19, count 0 2006.175.08:21:50.64#ibcon#*before return 0, iclass 19, count 0 2006.175.08:21:50.64#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:21:50.64#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.175.08:21:50.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:21:50.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:21:50.64$vc4f8/vblo=1,632.99 2006.175.08:21:50.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.175.08:21:50.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.175.08:21:50.64#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:50.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:21:50.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:21:50.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:21:50.64#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:21:50.64#ibcon#first serial, iclass 21, count 0 2006.175.08:21:50.64#ibcon#enter sib2, iclass 21, count 0 2006.175.08:21:50.64#ibcon#flushed, iclass 21, count 0 2006.175.08:21:50.64#ibcon#about to write, iclass 21, count 0 2006.175.08:21:50.64#ibcon#wrote, iclass 21, count 0 2006.175.08:21:50.64#ibcon#about to read 3, iclass 21, count 0 2006.175.08:21:50.66#ibcon#read 3, iclass 21, count 0 2006.175.08:21:50.66#ibcon#about to read 4, iclass 21, count 0 2006.175.08:21:50.66#ibcon#read 4, iclass 21, count 0 2006.175.08:21:50.66#ibcon#about to read 5, iclass 21, count 0 2006.175.08:21:50.66#ibcon#read 5, iclass 21, count 0 2006.175.08:21:50.66#ibcon#about to read 6, iclass 21, count 0 2006.175.08:21:50.66#ibcon#read 6, iclass 21, count 0 2006.175.08:21:50.66#ibcon#end of sib2, iclass 21, count 0 2006.175.08:21:50.66#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:21:50.66#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:21:50.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:21:50.66#ibcon#*before write, iclass 21, count 0 2006.175.08:21:50.66#ibcon#enter sib2, iclass 21, count 0 2006.175.08:21:50.66#ibcon#flushed, iclass 21, count 0 2006.175.08:21:50.66#ibcon#about to write, iclass 21, count 0 2006.175.08:21:50.66#ibcon#wrote, iclass 21, count 0 2006.175.08:21:50.66#ibcon#about to read 3, iclass 21, count 0 2006.175.08:21:50.70#ibcon#read 3, iclass 21, count 0 2006.175.08:21:50.70#ibcon#about to read 4, iclass 21, count 0 2006.175.08:21:50.70#ibcon#read 4, iclass 21, count 0 2006.175.08:21:50.70#ibcon#about to read 5, iclass 21, count 0 2006.175.08:21:50.70#ibcon#read 5, iclass 21, count 0 2006.175.08:21:50.70#ibcon#about to read 6, iclass 21, count 0 2006.175.08:21:50.70#ibcon#read 6, iclass 21, count 0 2006.175.08:21:50.70#ibcon#end of sib2, iclass 21, count 0 2006.175.08:21:50.70#ibcon#*after write, iclass 21, count 0 2006.175.08:21:50.70#ibcon#*before return 0, iclass 21, count 0 2006.175.08:21:50.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:21:50.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.175.08:21:50.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:21:50.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:21:50.70$vc4f8/vb=1,4 2006.175.08:21:50.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.175.08:21:50.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.175.08:21:50.70#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:50.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:21:50.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:21:50.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:21:50.70#ibcon#enter wrdev, iclass 23, count 2 2006.175.08:21:50.70#ibcon#first serial, iclass 23, count 2 2006.175.08:21:50.70#ibcon#enter sib2, iclass 23, count 2 2006.175.08:21:50.70#ibcon#flushed, iclass 23, count 2 2006.175.08:21:50.70#ibcon#about to write, iclass 23, count 2 2006.175.08:21:50.70#ibcon#wrote, iclass 23, count 2 2006.175.08:21:50.70#ibcon#about to read 3, iclass 23, count 2 2006.175.08:21:50.72#ibcon#read 3, iclass 23, count 2 2006.175.08:21:50.72#ibcon#about to read 4, iclass 23, count 2 2006.175.08:21:50.72#ibcon#read 4, iclass 23, count 2 2006.175.08:21:50.72#ibcon#about to read 5, iclass 23, count 2 2006.175.08:21:50.72#ibcon#read 5, iclass 23, count 2 2006.175.08:21:50.72#ibcon#about to read 6, iclass 23, count 2 2006.175.08:21:50.72#ibcon#read 6, iclass 23, count 2 2006.175.08:21:50.72#ibcon#end of sib2, iclass 23, count 2 2006.175.08:21:50.72#ibcon#*mode == 0, iclass 23, count 2 2006.175.08:21:50.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.175.08:21:50.72#ibcon#[27=AT01-04\r\n] 2006.175.08:21:50.72#ibcon#*before write, iclass 23, count 2 2006.175.08:21:50.72#ibcon#enter sib2, iclass 23, count 2 2006.175.08:21:50.72#ibcon#flushed, iclass 23, count 2 2006.175.08:21:50.72#ibcon#about to write, iclass 23, count 2 2006.175.08:21:50.72#ibcon#wrote, iclass 23, count 2 2006.175.08:21:50.72#ibcon#about to read 3, iclass 23, count 2 2006.175.08:21:50.75#ibcon#read 3, iclass 23, count 2 2006.175.08:21:50.75#ibcon#about to read 4, iclass 23, count 2 2006.175.08:21:50.75#ibcon#read 4, iclass 23, count 2 2006.175.08:21:50.75#ibcon#about to read 5, iclass 23, count 2 2006.175.08:21:50.75#ibcon#read 5, iclass 23, count 2 2006.175.08:21:50.75#ibcon#about to read 6, iclass 23, count 2 2006.175.08:21:50.75#ibcon#read 6, iclass 23, count 2 2006.175.08:21:50.75#ibcon#end of sib2, iclass 23, count 2 2006.175.08:21:50.75#ibcon#*after write, iclass 23, count 2 2006.175.08:21:50.75#ibcon#*before return 0, iclass 23, count 2 2006.175.08:21:50.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:21:50.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.175.08:21:50.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.175.08:21:50.75#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:50.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:21:50.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:21:50.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:21:50.87#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:21:50.87#ibcon#first serial, iclass 23, count 0 2006.175.08:21:50.87#ibcon#enter sib2, iclass 23, count 0 2006.175.08:21:50.87#ibcon#flushed, iclass 23, count 0 2006.175.08:21:50.87#ibcon#about to write, iclass 23, count 0 2006.175.08:21:50.87#ibcon#wrote, iclass 23, count 0 2006.175.08:21:50.87#ibcon#about to read 3, iclass 23, count 0 2006.175.08:21:50.89#ibcon#read 3, iclass 23, count 0 2006.175.08:21:50.89#ibcon#about to read 4, iclass 23, count 0 2006.175.08:21:50.89#ibcon#read 4, iclass 23, count 0 2006.175.08:21:50.89#ibcon#about to read 5, iclass 23, count 0 2006.175.08:21:50.89#ibcon#read 5, iclass 23, count 0 2006.175.08:21:50.89#ibcon#about to read 6, iclass 23, count 0 2006.175.08:21:50.89#ibcon#read 6, iclass 23, count 0 2006.175.08:21:50.89#ibcon#end of sib2, iclass 23, count 0 2006.175.08:21:50.89#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:21:50.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:21:50.89#ibcon#[27=USB\r\n] 2006.175.08:21:50.89#ibcon#*before write, iclass 23, count 0 2006.175.08:21:50.89#ibcon#enter sib2, iclass 23, count 0 2006.175.08:21:50.89#ibcon#flushed, iclass 23, count 0 2006.175.08:21:50.89#ibcon#about to write, iclass 23, count 0 2006.175.08:21:50.89#ibcon#wrote, iclass 23, count 0 2006.175.08:21:50.89#ibcon#about to read 3, iclass 23, count 0 2006.175.08:21:50.92#ibcon#read 3, iclass 23, count 0 2006.175.08:21:50.92#ibcon#about to read 4, iclass 23, count 0 2006.175.08:21:50.92#ibcon#read 4, iclass 23, count 0 2006.175.08:21:50.92#ibcon#about to read 5, iclass 23, count 0 2006.175.08:21:50.92#ibcon#read 5, iclass 23, count 0 2006.175.08:21:50.92#ibcon#about to read 6, iclass 23, count 0 2006.175.08:21:50.92#ibcon#read 6, iclass 23, count 0 2006.175.08:21:50.92#ibcon#end of sib2, iclass 23, count 0 2006.175.08:21:50.92#ibcon#*after write, iclass 23, count 0 2006.175.08:21:50.92#ibcon#*before return 0, iclass 23, count 0 2006.175.08:21:50.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:21:50.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.175.08:21:50.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:21:50.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:21:50.92$vc4f8/vblo=2,640.99 2006.175.08:21:50.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.08:21:50.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.08:21:50.92#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:50.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:50.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:50.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:50.92#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:21:50.92#ibcon#first serial, iclass 25, count 0 2006.175.08:21:50.92#ibcon#enter sib2, iclass 25, count 0 2006.175.08:21:50.92#ibcon#flushed, iclass 25, count 0 2006.175.08:21:50.92#ibcon#about to write, iclass 25, count 0 2006.175.08:21:50.92#ibcon#wrote, iclass 25, count 0 2006.175.08:21:50.92#ibcon#about to read 3, iclass 25, count 0 2006.175.08:21:50.94#ibcon#read 3, iclass 25, count 0 2006.175.08:21:50.94#ibcon#about to read 4, iclass 25, count 0 2006.175.08:21:50.94#ibcon#read 4, iclass 25, count 0 2006.175.08:21:50.94#ibcon#about to read 5, iclass 25, count 0 2006.175.08:21:50.94#ibcon#read 5, iclass 25, count 0 2006.175.08:21:50.94#ibcon#about to read 6, iclass 25, count 0 2006.175.08:21:50.94#ibcon#read 6, iclass 25, count 0 2006.175.08:21:50.94#ibcon#end of sib2, iclass 25, count 0 2006.175.08:21:50.94#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:21:50.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:21:50.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:21:50.94#ibcon#*before write, iclass 25, count 0 2006.175.08:21:50.94#ibcon#enter sib2, iclass 25, count 0 2006.175.08:21:50.94#ibcon#flushed, iclass 25, count 0 2006.175.08:21:50.94#ibcon#about to write, iclass 25, count 0 2006.175.08:21:50.94#ibcon#wrote, iclass 25, count 0 2006.175.08:21:50.94#ibcon#about to read 3, iclass 25, count 0 2006.175.08:21:50.98#ibcon#read 3, iclass 25, count 0 2006.175.08:21:50.98#ibcon#about to read 4, iclass 25, count 0 2006.175.08:21:50.98#ibcon#read 4, iclass 25, count 0 2006.175.08:21:50.98#ibcon#about to read 5, iclass 25, count 0 2006.175.08:21:50.98#ibcon#read 5, iclass 25, count 0 2006.175.08:21:50.98#ibcon#about to read 6, iclass 25, count 0 2006.175.08:21:50.98#ibcon#read 6, iclass 25, count 0 2006.175.08:21:50.98#ibcon#end of sib2, iclass 25, count 0 2006.175.08:21:50.98#ibcon#*after write, iclass 25, count 0 2006.175.08:21:50.98#ibcon#*before return 0, iclass 25, count 0 2006.175.08:21:50.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:50.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:21:50.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:21:50.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:21:50.98$vc4f8/vb=2,4 2006.175.08:21:50.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.175.08:21:50.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.175.08:21:50.98#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:50.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:51.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:51.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:51.04#ibcon#enter wrdev, iclass 27, count 2 2006.175.08:21:51.04#ibcon#first serial, iclass 27, count 2 2006.175.08:21:51.04#ibcon#enter sib2, iclass 27, count 2 2006.175.08:21:51.04#ibcon#flushed, iclass 27, count 2 2006.175.08:21:51.04#ibcon#about to write, iclass 27, count 2 2006.175.08:21:51.04#ibcon#wrote, iclass 27, count 2 2006.175.08:21:51.04#ibcon#about to read 3, iclass 27, count 2 2006.175.08:21:51.06#ibcon#read 3, iclass 27, count 2 2006.175.08:21:51.06#ibcon#about to read 4, iclass 27, count 2 2006.175.08:21:51.06#ibcon#read 4, iclass 27, count 2 2006.175.08:21:51.06#ibcon#about to read 5, iclass 27, count 2 2006.175.08:21:51.06#ibcon#read 5, iclass 27, count 2 2006.175.08:21:51.06#ibcon#about to read 6, iclass 27, count 2 2006.175.08:21:51.06#ibcon#read 6, iclass 27, count 2 2006.175.08:21:51.06#ibcon#end of sib2, iclass 27, count 2 2006.175.08:21:51.06#ibcon#*mode == 0, iclass 27, count 2 2006.175.08:21:51.06#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.175.08:21:51.06#ibcon#[27=AT02-04\r\n] 2006.175.08:21:51.06#ibcon#*before write, iclass 27, count 2 2006.175.08:21:51.06#ibcon#enter sib2, iclass 27, count 2 2006.175.08:21:51.06#ibcon#flushed, iclass 27, count 2 2006.175.08:21:51.06#ibcon#about to write, iclass 27, count 2 2006.175.08:21:51.06#ibcon#wrote, iclass 27, count 2 2006.175.08:21:51.06#ibcon#about to read 3, iclass 27, count 2 2006.175.08:21:51.09#ibcon#read 3, iclass 27, count 2 2006.175.08:21:51.09#ibcon#about to read 4, iclass 27, count 2 2006.175.08:21:51.09#ibcon#read 4, iclass 27, count 2 2006.175.08:21:51.09#ibcon#about to read 5, iclass 27, count 2 2006.175.08:21:51.09#ibcon#read 5, iclass 27, count 2 2006.175.08:21:51.09#ibcon#about to read 6, iclass 27, count 2 2006.175.08:21:51.09#ibcon#read 6, iclass 27, count 2 2006.175.08:21:51.09#ibcon#end of sib2, iclass 27, count 2 2006.175.08:21:51.09#ibcon#*after write, iclass 27, count 2 2006.175.08:21:51.09#ibcon#*before return 0, iclass 27, count 2 2006.175.08:21:51.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:51.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.175.08:21:51.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.175.08:21:51.09#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:51.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:51.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:51.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:51.21#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:21:51.21#ibcon#first serial, iclass 27, count 0 2006.175.08:21:51.21#ibcon#enter sib2, iclass 27, count 0 2006.175.08:21:51.21#ibcon#flushed, iclass 27, count 0 2006.175.08:21:51.21#ibcon#about to write, iclass 27, count 0 2006.175.08:21:51.21#ibcon#wrote, iclass 27, count 0 2006.175.08:21:51.21#ibcon#about to read 3, iclass 27, count 0 2006.175.08:21:51.23#ibcon#read 3, iclass 27, count 0 2006.175.08:21:51.23#ibcon#about to read 4, iclass 27, count 0 2006.175.08:21:51.23#ibcon#read 4, iclass 27, count 0 2006.175.08:21:51.23#ibcon#about to read 5, iclass 27, count 0 2006.175.08:21:51.23#ibcon#read 5, iclass 27, count 0 2006.175.08:21:51.23#ibcon#about to read 6, iclass 27, count 0 2006.175.08:21:51.23#ibcon#read 6, iclass 27, count 0 2006.175.08:21:51.23#ibcon#end of sib2, iclass 27, count 0 2006.175.08:21:51.23#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:21:51.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:21:51.23#ibcon#[27=USB\r\n] 2006.175.08:21:51.23#ibcon#*before write, iclass 27, count 0 2006.175.08:21:51.23#ibcon#enter sib2, iclass 27, count 0 2006.175.08:21:51.23#ibcon#flushed, iclass 27, count 0 2006.175.08:21:51.23#ibcon#about to write, iclass 27, count 0 2006.175.08:21:51.23#ibcon#wrote, iclass 27, count 0 2006.175.08:21:51.23#ibcon#about to read 3, iclass 27, count 0 2006.175.08:21:51.26#ibcon#read 3, iclass 27, count 0 2006.175.08:21:51.26#ibcon#about to read 4, iclass 27, count 0 2006.175.08:21:51.26#ibcon#read 4, iclass 27, count 0 2006.175.08:21:51.26#ibcon#about to read 5, iclass 27, count 0 2006.175.08:21:51.26#ibcon#read 5, iclass 27, count 0 2006.175.08:21:51.26#ibcon#about to read 6, iclass 27, count 0 2006.175.08:21:51.26#ibcon#read 6, iclass 27, count 0 2006.175.08:21:51.26#ibcon#end of sib2, iclass 27, count 0 2006.175.08:21:51.26#ibcon#*after write, iclass 27, count 0 2006.175.08:21:51.26#ibcon#*before return 0, iclass 27, count 0 2006.175.08:21:51.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:51.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.175.08:21:51.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:21:51.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:21:51.26$vc4f8/vblo=3,656.99 2006.175.08:21:51.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.175.08:21:51.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.175.08:21:51.26#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:51.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:51.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:51.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:51.26#ibcon#enter wrdev, iclass 29, count 0 2006.175.08:21:51.26#ibcon#first serial, iclass 29, count 0 2006.175.08:21:51.26#ibcon#enter sib2, iclass 29, count 0 2006.175.08:21:51.26#ibcon#flushed, iclass 29, count 0 2006.175.08:21:51.26#ibcon#about to write, iclass 29, count 0 2006.175.08:21:51.26#ibcon#wrote, iclass 29, count 0 2006.175.08:21:51.26#ibcon#about to read 3, iclass 29, count 0 2006.175.08:21:51.28#ibcon#read 3, iclass 29, count 0 2006.175.08:21:51.28#ibcon#about to read 4, iclass 29, count 0 2006.175.08:21:51.28#ibcon#read 4, iclass 29, count 0 2006.175.08:21:51.28#ibcon#about to read 5, iclass 29, count 0 2006.175.08:21:51.28#ibcon#read 5, iclass 29, count 0 2006.175.08:21:51.28#ibcon#about to read 6, iclass 29, count 0 2006.175.08:21:51.28#ibcon#read 6, iclass 29, count 0 2006.175.08:21:51.28#ibcon#end of sib2, iclass 29, count 0 2006.175.08:21:51.28#ibcon#*mode == 0, iclass 29, count 0 2006.175.08:21:51.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.08:21:51.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:21:51.28#ibcon#*before write, iclass 29, count 0 2006.175.08:21:51.28#ibcon#enter sib2, iclass 29, count 0 2006.175.08:21:51.28#ibcon#flushed, iclass 29, count 0 2006.175.08:21:51.28#ibcon#about to write, iclass 29, count 0 2006.175.08:21:51.28#ibcon#wrote, iclass 29, count 0 2006.175.08:21:51.28#ibcon#about to read 3, iclass 29, count 0 2006.175.08:21:51.32#ibcon#read 3, iclass 29, count 0 2006.175.08:21:51.32#ibcon#about to read 4, iclass 29, count 0 2006.175.08:21:51.32#ibcon#read 4, iclass 29, count 0 2006.175.08:21:51.32#ibcon#about to read 5, iclass 29, count 0 2006.175.08:21:51.32#ibcon#read 5, iclass 29, count 0 2006.175.08:21:51.32#ibcon#about to read 6, iclass 29, count 0 2006.175.08:21:51.32#ibcon#read 6, iclass 29, count 0 2006.175.08:21:51.32#ibcon#end of sib2, iclass 29, count 0 2006.175.08:21:51.32#ibcon#*after write, iclass 29, count 0 2006.175.08:21:51.32#ibcon#*before return 0, iclass 29, count 0 2006.175.08:21:51.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:51.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.175.08:21:51.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.08:21:51.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.08:21:51.32$vc4f8/vb=3,4 2006.175.08:21:51.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.175.08:21:51.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.175.08:21:51.32#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:51.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:51.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:51.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:51.38#ibcon#enter wrdev, iclass 31, count 2 2006.175.08:21:51.38#ibcon#first serial, iclass 31, count 2 2006.175.08:21:51.38#ibcon#enter sib2, iclass 31, count 2 2006.175.08:21:51.38#ibcon#flushed, iclass 31, count 2 2006.175.08:21:51.38#ibcon#about to write, iclass 31, count 2 2006.175.08:21:51.38#ibcon#wrote, iclass 31, count 2 2006.175.08:21:51.38#ibcon#about to read 3, iclass 31, count 2 2006.175.08:21:51.40#ibcon#read 3, iclass 31, count 2 2006.175.08:21:51.40#ibcon#about to read 4, iclass 31, count 2 2006.175.08:21:51.40#ibcon#read 4, iclass 31, count 2 2006.175.08:21:51.40#ibcon#about to read 5, iclass 31, count 2 2006.175.08:21:51.40#ibcon#read 5, iclass 31, count 2 2006.175.08:21:51.40#ibcon#about to read 6, iclass 31, count 2 2006.175.08:21:51.40#ibcon#read 6, iclass 31, count 2 2006.175.08:21:51.40#ibcon#end of sib2, iclass 31, count 2 2006.175.08:21:51.40#ibcon#*mode == 0, iclass 31, count 2 2006.175.08:21:51.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.175.08:21:51.40#ibcon#[27=AT03-04\r\n] 2006.175.08:21:51.40#ibcon#*before write, iclass 31, count 2 2006.175.08:21:51.40#ibcon#enter sib2, iclass 31, count 2 2006.175.08:21:51.40#ibcon#flushed, iclass 31, count 2 2006.175.08:21:51.40#ibcon#about to write, iclass 31, count 2 2006.175.08:21:51.40#ibcon#wrote, iclass 31, count 2 2006.175.08:21:51.40#ibcon#about to read 3, iclass 31, count 2 2006.175.08:21:51.43#ibcon#read 3, iclass 31, count 2 2006.175.08:21:51.43#ibcon#about to read 4, iclass 31, count 2 2006.175.08:21:51.43#ibcon#read 4, iclass 31, count 2 2006.175.08:21:51.43#ibcon#about to read 5, iclass 31, count 2 2006.175.08:21:51.43#ibcon#read 5, iclass 31, count 2 2006.175.08:21:51.43#ibcon#about to read 6, iclass 31, count 2 2006.175.08:21:51.43#ibcon#read 6, iclass 31, count 2 2006.175.08:21:51.43#ibcon#end of sib2, iclass 31, count 2 2006.175.08:21:51.43#ibcon#*after write, iclass 31, count 2 2006.175.08:21:51.43#ibcon#*before return 0, iclass 31, count 2 2006.175.08:21:51.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:51.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.175.08:21:51.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.175.08:21:51.43#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:51.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:51.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:51.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:51.55#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:21:51.55#ibcon#first serial, iclass 31, count 0 2006.175.08:21:51.55#ibcon#enter sib2, iclass 31, count 0 2006.175.08:21:51.55#ibcon#flushed, iclass 31, count 0 2006.175.08:21:51.55#ibcon#about to write, iclass 31, count 0 2006.175.08:21:51.55#ibcon#wrote, iclass 31, count 0 2006.175.08:21:51.55#ibcon#about to read 3, iclass 31, count 0 2006.175.08:21:51.57#ibcon#read 3, iclass 31, count 0 2006.175.08:21:51.57#ibcon#about to read 4, iclass 31, count 0 2006.175.08:21:51.57#ibcon#read 4, iclass 31, count 0 2006.175.08:21:51.57#ibcon#about to read 5, iclass 31, count 0 2006.175.08:21:51.57#ibcon#read 5, iclass 31, count 0 2006.175.08:21:51.57#ibcon#about to read 6, iclass 31, count 0 2006.175.08:21:51.57#ibcon#read 6, iclass 31, count 0 2006.175.08:21:51.57#ibcon#end of sib2, iclass 31, count 0 2006.175.08:21:51.57#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:21:51.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:21:51.57#ibcon#[27=USB\r\n] 2006.175.08:21:51.57#ibcon#*before write, iclass 31, count 0 2006.175.08:21:51.57#ibcon#enter sib2, iclass 31, count 0 2006.175.08:21:51.57#ibcon#flushed, iclass 31, count 0 2006.175.08:21:51.57#ibcon#about to write, iclass 31, count 0 2006.175.08:21:51.57#ibcon#wrote, iclass 31, count 0 2006.175.08:21:51.57#ibcon#about to read 3, iclass 31, count 0 2006.175.08:21:51.60#ibcon#read 3, iclass 31, count 0 2006.175.08:21:51.60#ibcon#about to read 4, iclass 31, count 0 2006.175.08:21:51.60#ibcon#read 4, iclass 31, count 0 2006.175.08:21:51.60#ibcon#about to read 5, iclass 31, count 0 2006.175.08:21:51.60#ibcon#read 5, iclass 31, count 0 2006.175.08:21:51.60#ibcon#about to read 6, iclass 31, count 0 2006.175.08:21:51.60#ibcon#read 6, iclass 31, count 0 2006.175.08:21:51.60#ibcon#end of sib2, iclass 31, count 0 2006.175.08:21:51.60#ibcon#*after write, iclass 31, count 0 2006.175.08:21:51.60#ibcon#*before return 0, iclass 31, count 0 2006.175.08:21:51.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:51.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.175.08:21:51.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:21:51.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:21:51.60$vc4f8/vblo=4,712.99 2006.175.08:21:51.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.175.08:21:51.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.175.08:21:51.60#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:51.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:51.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:51.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:51.60#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:21:51.60#ibcon#first serial, iclass 33, count 0 2006.175.08:21:51.60#ibcon#enter sib2, iclass 33, count 0 2006.175.08:21:51.60#ibcon#flushed, iclass 33, count 0 2006.175.08:21:51.60#ibcon#about to write, iclass 33, count 0 2006.175.08:21:51.60#ibcon#wrote, iclass 33, count 0 2006.175.08:21:51.60#ibcon#about to read 3, iclass 33, count 0 2006.175.08:21:51.62#ibcon#read 3, iclass 33, count 0 2006.175.08:21:51.62#ibcon#about to read 4, iclass 33, count 0 2006.175.08:21:51.62#ibcon#read 4, iclass 33, count 0 2006.175.08:21:51.62#ibcon#about to read 5, iclass 33, count 0 2006.175.08:21:51.62#ibcon#read 5, iclass 33, count 0 2006.175.08:21:51.62#ibcon#about to read 6, iclass 33, count 0 2006.175.08:21:51.62#ibcon#read 6, iclass 33, count 0 2006.175.08:21:51.62#ibcon#end of sib2, iclass 33, count 0 2006.175.08:21:51.62#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:21:51.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:21:51.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:21:51.62#ibcon#*before write, iclass 33, count 0 2006.175.08:21:51.62#ibcon#enter sib2, iclass 33, count 0 2006.175.08:21:51.62#ibcon#flushed, iclass 33, count 0 2006.175.08:21:51.62#ibcon#about to write, iclass 33, count 0 2006.175.08:21:51.62#ibcon#wrote, iclass 33, count 0 2006.175.08:21:51.62#ibcon#about to read 3, iclass 33, count 0 2006.175.08:21:51.66#ibcon#read 3, iclass 33, count 0 2006.175.08:21:51.66#ibcon#about to read 4, iclass 33, count 0 2006.175.08:21:51.66#ibcon#read 4, iclass 33, count 0 2006.175.08:21:51.66#ibcon#about to read 5, iclass 33, count 0 2006.175.08:21:51.66#ibcon#read 5, iclass 33, count 0 2006.175.08:21:51.66#ibcon#about to read 6, iclass 33, count 0 2006.175.08:21:51.66#ibcon#read 6, iclass 33, count 0 2006.175.08:21:51.66#ibcon#end of sib2, iclass 33, count 0 2006.175.08:21:51.66#ibcon#*after write, iclass 33, count 0 2006.175.08:21:51.66#ibcon#*before return 0, iclass 33, count 0 2006.175.08:21:51.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:51.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.175.08:21:51.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:21:51.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:21:51.66$vc4f8/vb=4,4 2006.175.08:21:51.66#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.175.08:21:51.66#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.175.08:21:51.66#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:51.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:51.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:51.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:51.72#ibcon#enter wrdev, iclass 35, count 2 2006.175.08:21:51.72#ibcon#first serial, iclass 35, count 2 2006.175.08:21:51.72#ibcon#enter sib2, iclass 35, count 2 2006.175.08:21:51.72#ibcon#flushed, iclass 35, count 2 2006.175.08:21:51.72#ibcon#about to write, iclass 35, count 2 2006.175.08:21:51.72#ibcon#wrote, iclass 35, count 2 2006.175.08:21:51.72#ibcon#about to read 3, iclass 35, count 2 2006.175.08:21:51.74#ibcon#read 3, iclass 35, count 2 2006.175.08:21:51.74#ibcon#about to read 4, iclass 35, count 2 2006.175.08:21:51.74#ibcon#read 4, iclass 35, count 2 2006.175.08:21:51.74#ibcon#about to read 5, iclass 35, count 2 2006.175.08:21:51.74#ibcon#read 5, iclass 35, count 2 2006.175.08:21:51.74#ibcon#about to read 6, iclass 35, count 2 2006.175.08:21:51.74#ibcon#read 6, iclass 35, count 2 2006.175.08:21:51.74#ibcon#end of sib2, iclass 35, count 2 2006.175.08:21:51.74#ibcon#*mode == 0, iclass 35, count 2 2006.175.08:21:51.74#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.175.08:21:51.74#ibcon#[27=AT04-04\r\n] 2006.175.08:21:51.74#ibcon#*before write, iclass 35, count 2 2006.175.08:21:51.74#ibcon#enter sib2, iclass 35, count 2 2006.175.08:21:51.74#ibcon#flushed, iclass 35, count 2 2006.175.08:21:51.74#ibcon#about to write, iclass 35, count 2 2006.175.08:21:51.74#ibcon#wrote, iclass 35, count 2 2006.175.08:21:51.74#ibcon#about to read 3, iclass 35, count 2 2006.175.08:21:51.77#ibcon#read 3, iclass 35, count 2 2006.175.08:21:51.77#ibcon#about to read 4, iclass 35, count 2 2006.175.08:21:51.77#ibcon#read 4, iclass 35, count 2 2006.175.08:21:51.77#ibcon#about to read 5, iclass 35, count 2 2006.175.08:21:51.77#ibcon#read 5, iclass 35, count 2 2006.175.08:21:51.77#ibcon#about to read 6, iclass 35, count 2 2006.175.08:21:51.77#ibcon#read 6, iclass 35, count 2 2006.175.08:21:51.77#ibcon#end of sib2, iclass 35, count 2 2006.175.08:21:51.77#ibcon#*after write, iclass 35, count 2 2006.175.08:21:51.77#ibcon#*before return 0, iclass 35, count 2 2006.175.08:21:51.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:51.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.175.08:21:51.77#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.175.08:21:51.77#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:51.77#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:51.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:51.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:51.89#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:21:51.89#ibcon#first serial, iclass 35, count 0 2006.175.08:21:51.89#ibcon#enter sib2, iclass 35, count 0 2006.175.08:21:51.89#ibcon#flushed, iclass 35, count 0 2006.175.08:21:51.89#ibcon#about to write, iclass 35, count 0 2006.175.08:21:51.89#ibcon#wrote, iclass 35, count 0 2006.175.08:21:51.89#ibcon#about to read 3, iclass 35, count 0 2006.175.08:21:51.91#ibcon#read 3, iclass 35, count 0 2006.175.08:21:51.91#ibcon#about to read 4, iclass 35, count 0 2006.175.08:21:51.91#ibcon#read 4, iclass 35, count 0 2006.175.08:21:51.91#ibcon#about to read 5, iclass 35, count 0 2006.175.08:21:51.91#ibcon#read 5, iclass 35, count 0 2006.175.08:21:51.91#ibcon#about to read 6, iclass 35, count 0 2006.175.08:21:51.91#ibcon#read 6, iclass 35, count 0 2006.175.08:21:51.91#ibcon#end of sib2, iclass 35, count 0 2006.175.08:21:51.91#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:21:51.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:21:51.91#ibcon#[27=USB\r\n] 2006.175.08:21:51.91#ibcon#*before write, iclass 35, count 0 2006.175.08:21:51.91#ibcon#enter sib2, iclass 35, count 0 2006.175.08:21:51.91#ibcon#flushed, iclass 35, count 0 2006.175.08:21:51.91#ibcon#about to write, iclass 35, count 0 2006.175.08:21:51.91#ibcon#wrote, iclass 35, count 0 2006.175.08:21:51.91#ibcon#about to read 3, iclass 35, count 0 2006.175.08:21:51.94#ibcon#read 3, iclass 35, count 0 2006.175.08:21:51.94#ibcon#about to read 4, iclass 35, count 0 2006.175.08:21:51.94#ibcon#read 4, iclass 35, count 0 2006.175.08:21:51.94#ibcon#about to read 5, iclass 35, count 0 2006.175.08:21:51.94#ibcon#read 5, iclass 35, count 0 2006.175.08:21:51.94#ibcon#about to read 6, iclass 35, count 0 2006.175.08:21:51.94#ibcon#read 6, iclass 35, count 0 2006.175.08:21:51.94#ibcon#end of sib2, iclass 35, count 0 2006.175.08:21:51.94#ibcon#*after write, iclass 35, count 0 2006.175.08:21:51.94#ibcon#*before return 0, iclass 35, count 0 2006.175.08:21:51.94#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:51.94#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.175.08:21:51.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:21:51.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:21:51.94$vc4f8/vblo=5,744.99 2006.175.08:21:51.94#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.175.08:21:51.94#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.175.08:21:51.94#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:51.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:51.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:51.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:51.94#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:21:51.94#ibcon#first serial, iclass 37, count 0 2006.175.08:21:51.94#ibcon#enter sib2, iclass 37, count 0 2006.175.08:21:51.94#ibcon#flushed, iclass 37, count 0 2006.175.08:21:51.94#ibcon#about to write, iclass 37, count 0 2006.175.08:21:51.94#ibcon#wrote, iclass 37, count 0 2006.175.08:21:51.94#ibcon#about to read 3, iclass 37, count 0 2006.175.08:21:51.96#ibcon#read 3, iclass 37, count 0 2006.175.08:21:51.96#ibcon#about to read 4, iclass 37, count 0 2006.175.08:21:51.96#ibcon#read 4, iclass 37, count 0 2006.175.08:21:51.96#ibcon#about to read 5, iclass 37, count 0 2006.175.08:21:51.96#ibcon#read 5, iclass 37, count 0 2006.175.08:21:51.96#ibcon#about to read 6, iclass 37, count 0 2006.175.08:21:51.96#ibcon#read 6, iclass 37, count 0 2006.175.08:21:51.96#ibcon#end of sib2, iclass 37, count 0 2006.175.08:21:51.96#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:21:51.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:21:51.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:21:51.96#ibcon#*before write, iclass 37, count 0 2006.175.08:21:51.96#ibcon#enter sib2, iclass 37, count 0 2006.175.08:21:51.96#ibcon#flushed, iclass 37, count 0 2006.175.08:21:51.96#ibcon#about to write, iclass 37, count 0 2006.175.08:21:51.96#ibcon#wrote, iclass 37, count 0 2006.175.08:21:51.96#ibcon#about to read 3, iclass 37, count 0 2006.175.08:21:52.00#ibcon#read 3, iclass 37, count 0 2006.175.08:21:52.00#ibcon#about to read 4, iclass 37, count 0 2006.175.08:21:52.00#ibcon#read 4, iclass 37, count 0 2006.175.08:21:52.00#ibcon#about to read 5, iclass 37, count 0 2006.175.08:21:52.00#ibcon#read 5, iclass 37, count 0 2006.175.08:21:52.00#ibcon#about to read 6, iclass 37, count 0 2006.175.08:21:52.00#ibcon#read 6, iclass 37, count 0 2006.175.08:21:52.00#ibcon#end of sib2, iclass 37, count 0 2006.175.08:21:52.00#ibcon#*after write, iclass 37, count 0 2006.175.08:21:52.00#ibcon#*before return 0, iclass 37, count 0 2006.175.08:21:52.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:52.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.175.08:21:52.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:21:52.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:21:52.00$vc4f8/vb=5,4 2006.175.08:21:52.00#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.175.08:21:52.00#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.175.08:21:52.00#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:52.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:52.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:52.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:52.06#ibcon#enter wrdev, iclass 39, count 2 2006.175.08:21:52.06#ibcon#first serial, iclass 39, count 2 2006.175.08:21:52.06#ibcon#enter sib2, iclass 39, count 2 2006.175.08:21:52.06#ibcon#flushed, iclass 39, count 2 2006.175.08:21:52.06#ibcon#about to write, iclass 39, count 2 2006.175.08:21:52.06#ibcon#wrote, iclass 39, count 2 2006.175.08:21:52.06#ibcon#about to read 3, iclass 39, count 2 2006.175.08:21:52.08#ibcon#read 3, iclass 39, count 2 2006.175.08:21:52.08#ibcon#about to read 4, iclass 39, count 2 2006.175.08:21:52.08#ibcon#read 4, iclass 39, count 2 2006.175.08:21:52.08#ibcon#about to read 5, iclass 39, count 2 2006.175.08:21:52.08#ibcon#read 5, iclass 39, count 2 2006.175.08:21:52.08#ibcon#about to read 6, iclass 39, count 2 2006.175.08:21:52.08#ibcon#read 6, iclass 39, count 2 2006.175.08:21:52.08#ibcon#end of sib2, iclass 39, count 2 2006.175.08:21:52.08#ibcon#*mode == 0, iclass 39, count 2 2006.175.08:21:52.08#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.175.08:21:52.08#ibcon#[27=AT05-04\r\n] 2006.175.08:21:52.08#ibcon#*before write, iclass 39, count 2 2006.175.08:21:52.08#ibcon#enter sib2, iclass 39, count 2 2006.175.08:21:52.08#ibcon#flushed, iclass 39, count 2 2006.175.08:21:52.08#ibcon#about to write, iclass 39, count 2 2006.175.08:21:52.08#ibcon#wrote, iclass 39, count 2 2006.175.08:21:52.08#ibcon#about to read 3, iclass 39, count 2 2006.175.08:21:52.11#ibcon#read 3, iclass 39, count 2 2006.175.08:21:52.11#ibcon#about to read 4, iclass 39, count 2 2006.175.08:21:52.11#ibcon#read 4, iclass 39, count 2 2006.175.08:21:52.11#ibcon#about to read 5, iclass 39, count 2 2006.175.08:21:52.11#ibcon#read 5, iclass 39, count 2 2006.175.08:21:52.11#ibcon#about to read 6, iclass 39, count 2 2006.175.08:21:52.11#ibcon#read 6, iclass 39, count 2 2006.175.08:21:52.11#ibcon#end of sib2, iclass 39, count 2 2006.175.08:21:52.11#ibcon#*after write, iclass 39, count 2 2006.175.08:21:52.11#ibcon#*before return 0, iclass 39, count 2 2006.175.08:21:52.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:52.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.175.08:21:52.11#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.175.08:21:52.11#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:52.11#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:52.23#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:52.23#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:52.23#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:21:52.23#ibcon#first serial, iclass 39, count 0 2006.175.08:21:52.23#ibcon#enter sib2, iclass 39, count 0 2006.175.08:21:52.23#ibcon#flushed, iclass 39, count 0 2006.175.08:21:52.23#ibcon#about to write, iclass 39, count 0 2006.175.08:21:52.23#ibcon#wrote, iclass 39, count 0 2006.175.08:21:52.23#ibcon#about to read 3, iclass 39, count 0 2006.175.08:21:52.25#ibcon#read 3, iclass 39, count 0 2006.175.08:21:52.25#ibcon#about to read 4, iclass 39, count 0 2006.175.08:21:52.25#ibcon#read 4, iclass 39, count 0 2006.175.08:21:52.25#ibcon#about to read 5, iclass 39, count 0 2006.175.08:21:52.25#ibcon#read 5, iclass 39, count 0 2006.175.08:21:52.25#ibcon#about to read 6, iclass 39, count 0 2006.175.08:21:52.25#ibcon#read 6, iclass 39, count 0 2006.175.08:21:52.25#ibcon#end of sib2, iclass 39, count 0 2006.175.08:21:52.25#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:21:52.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:21:52.25#ibcon#[27=USB\r\n] 2006.175.08:21:52.25#ibcon#*before write, iclass 39, count 0 2006.175.08:21:52.25#ibcon#enter sib2, iclass 39, count 0 2006.175.08:21:52.25#ibcon#flushed, iclass 39, count 0 2006.175.08:21:52.25#ibcon#about to write, iclass 39, count 0 2006.175.08:21:52.25#ibcon#wrote, iclass 39, count 0 2006.175.08:21:52.25#ibcon#about to read 3, iclass 39, count 0 2006.175.08:21:52.28#ibcon#read 3, iclass 39, count 0 2006.175.08:21:52.28#ibcon#about to read 4, iclass 39, count 0 2006.175.08:21:52.28#ibcon#read 4, iclass 39, count 0 2006.175.08:21:52.28#ibcon#about to read 5, iclass 39, count 0 2006.175.08:21:52.28#ibcon#read 5, iclass 39, count 0 2006.175.08:21:52.28#ibcon#about to read 6, iclass 39, count 0 2006.175.08:21:52.28#ibcon#read 6, iclass 39, count 0 2006.175.08:21:52.28#ibcon#end of sib2, iclass 39, count 0 2006.175.08:21:52.28#ibcon#*after write, iclass 39, count 0 2006.175.08:21:52.28#ibcon#*before return 0, iclass 39, count 0 2006.175.08:21:52.28#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:52.28#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.175.08:21:52.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:21:52.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:21:52.28$vc4f8/vblo=6,752.99 2006.175.08:21:52.28#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.175.08:21:52.28#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.175.08:21:52.28#ibcon#ireg 17 cls_cnt 0 2006.175.08:21:52.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:52.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:52.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:52.28#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:21:52.28#ibcon#first serial, iclass 3, count 0 2006.175.08:21:52.28#ibcon#enter sib2, iclass 3, count 0 2006.175.08:21:52.28#ibcon#flushed, iclass 3, count 0 2006.175.08:21:52.28#ibcon#about to write, iclass 3, count 0 2006.175.08:21:52.28#ibcon#wrote, iclass 3, count 0 2006.175.08:21:52.28#ibcon#about to read 3, iclass 3, count 0 2006.175.08:21:52.30#ibcon#read 3, iclass 3, count 0 2006.175.08:21:52.30#ibcon#about to read 4, iclass 3, count 0 2006.175.08:21:52.30#ibcon#read 4, iclass 3, count 0 2006.175.08:21:52.30#ibcon#about to read 5, iclass 3, count 0 2006.175.08:21:52.30#ibcon#read 5, iclass 3, count 0 2006.175.08:21:52.30#ibcon#about to read 6, iclass 3, count 0 2006.175.08:21:52.30#ibcon#read 6, iclass 3, count 0 2006.175.08:21:52.30#ibcon#end of sib2, iclass 3, count 0 2006.175.08:21:52.30#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:21:52.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:21:52.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:21:52.30#ibcon#*before write, iclass 3, count 0 2006.175.08:21:52.30#ibcon#enter sib2, iclass 3, count 0 2006.175.08:21:52.30#ibcon#flushed, iclass 3, count 0 2006.175.08:21:52.30#ibcon#about to write, iclass 3, count 0 2006.175.08:21:52.30#ibcon#wrote, iclass 3, count 0 2006.175.08:21:52.30#ibcon#about to read 3, iclass 3, count 0 2006.175.08:21:52.34#ibcon#read 3, iclass 3, count 0 2006.175.08:21:52.34#ibcon#about to read 4, iclass 3, count 0 2006.175.08:21:52.34#ibcon#read 4, iclass 3, count 0 2006.175.08:21:52.34#ibcon#about to read 5, iclass 3, count 0 2006.175.08:21:52.34#ibcon#read 5, iclass 3, count 0 2006.175.08:21:52.34#ibcon#about to read 6, iclass 3, count 0 2006.175.08:21:52.34#ibcon#read 6, iclass 3, count 0 2006.175.08:21:52.34#ibcon#end of sib2, iclass 3, count 0 2006.175.08:21:52.34#ibcon#*after write, iclass 3, count 0 2006.175.08:21:52.34#ibcon#*before return 0, iclass 3, count 0 2006.175.08:21:52.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:52.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.175.08:21:52.34#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:21:52.34#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:21:52.34$vc4f8/vb=6,4 2006.175.08:21:52.34#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.175.08:21:52.34#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.175.08:21:52.34#ibcon#ireg 11 cls_cnt 2 2006.175.08:21:52.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:52.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:52.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:52.40#ibcon#enter wrdev, iclass 5, count 2 2006.175.08:21:52.40#ibcon#first serial, iclass 5, count 2 2006.175.08:21:52.40#ibcon#enter sib2, iclass 5, count 2 2006.175.08:21:52.40#ibcon#flushed, iclass 5, count 2 2006.175.08:21:52.40#ibcon#about to write, iclass 5, count 2 2006.175.08:21:52.40#ibcon#wrote, iclass 5, count 2 2006.175.08:21:52.40#ibcon#about to read 3, iclass 5, count 2 2006.175.08:21:52.42#ibcon#read 3, iclass 5, count 2 2006.175.08:21:52.42#ibcon#about to read 4, iclass 5, count 2 2006.175.08:21:52.42#ibcon#read 4, iclass 5, count 2 2006.175.08:21:52.42#ibcon#about to read 5, iclass 5, count 2 2006.175.08:21:52.42#ibcon#read 5, iclass 5, count 2 2006.175.08:21:52.42#ibcon#about to read 6, iclass 5, count 2 2006.175.08:21:52.42#ibcon#read 6, iclass 5, count 2 2006.175.08:21:52.42#ibcon#end of sib2, iclass 5, count 2 2006.175.08:21:52.42#ibcon#*mode == 0, iclass 5, count 2 2006.175.08:21:52.42#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.175.08:21:52.42#ibcon#[27=AT06-04\r\n] 2006.175.08:21:52.42#ibcon#*before write, iclass 5, count 2 2006.175.08:21:52.42#ibcon#enter sib2, iclass 5, count 2 2006.175.08:21:52.42#ibcon#flushed, iclass 5, count 2 2006.175.08:21:52.42#ibcon#about to write, iclass 5, count 2 2006.175.08:21:52.42#ibcon#wrote, iclass 5, count 2 2006.175.08:21:52.42#ibcon#about to read 3, iclass 5, count 2 2006.175.08:21:52.45#ibcon#read 3, iclass 5, count 2 2006.175.08:21:52.45#ibcon#about to read 4, iclass 5, count 2 2006.175.08:21:52.45#ibcon#read 4, iclass 5, count 2 2006.175.08:21:52.45#ibcon#about to read 5, iclass 5, count 2 2006.175.08:21:52.45#ibcon#read 5, iclass 5, count 2 2006.175.08:21:52.45#ibcon#about to read 6, iclass 5, count 2 2006.175.08:21:52.45#ibcon#read 6, iclass 5, count 2 2006.175.08:21:52.45#ibcon#end of sib2, iclass 5, count 2 2006.175.08:21:52.45#ibcon#*after write, iclass 5, count 2 2006.175.08:21:52.45#ibcon#*before return 0, iclass 5, count 2 2006.175.08:21:52.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:52.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.175.08:21:52.45#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.175.08:21:52.45#ibcon#ireg 7 cls_cnt 0 2006.175.08:21:52.45#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:52.57#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:52.57#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:52.57#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:21:52.57#ibcon#first serial, iclass 5, count 0 2006.175.08:21:52.57#ibcon#enter sib2, iclass 5, count 0 2006.175.08:21:52.57#ibcon#flushed, iclass 5, count 0 2006.175.08:21:52.57#ibcon#about to write, iclass 5, count 0 2006.175.08:21:52.57#ibcon#wrote, iclass 5, count 0 2006.175.08:21:52.57#ibcon#about to read 3, iclass 5, count 0 2006.175.08:21:52.59#ibcon#read 3, iclass 5, count 0 2006.175.08:21:52.59#ibcon#about to read 4, iclass 5, count 0 2006.175.08:21:52.59#ibcon#read 4, iclass 5, count 0 2006.175.08:21:52.59#ibcon#about to read 5, iclass 5, count 0 2006.175.08:21:52.59#ibcon#read 5, iclass 5, count 0 2006.175.08:21:52.59#ibcon#about to read 6, iclass 5, count 0 2006.175.08:21:52.59#ibcon#read 6, iclass 5, count 0 2006.175.08:21:52.59#ibcon#end of sib2, iclass 5, count 0 2006.175.08:21:52.59#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:21:52.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:21:52.59#ibcon#[27=USB\r\n] 2006.175.08:21:52.59#ibcon#*before write, iclass 5, count 0 2006.175.08:21:52.59#ibcon#enter sib2, iclass 5, count 0 2006.175.08:21:52.59#ibcon#flushed, iclass 5, count 0 2006.175.08:21:52.59#ibcon#about to write, iclass 5, count 0 2006.175.08:21:52.59#ibcon#wrote, iclass 5, count 0 2006.175.08:21:52.59#ibcon#about to read 3, iclass 5, count 0 2006.175.08:21:52.62#ibcon#read 3, iclass 5, count 0 2006.175.08:21:52.62#ibcon#about to read 4, iclass 5, count 0 2006.175.08:21:52.62#ibcon#read 4, iclass 5, count 0 2006.175.08:21:52.62#ibcon#about to read 5, iclass 5, count 0 2006.175.08:21:52.62#ibcon#read 5, iclass 5, count 0 2006.175.08:21:52.62#ibcon#about to read 6, iclass 5, count 0 2006.175.08:21:52.62#ibcon#read 6, iclass 5, count 0 2006.175.08:21:52.62#ibcon#end of sib2, iclass 5, count 0 2006.175.08:21:52.62#ibcon#*after write, iclass 5, count 0 2006.175.08:21:52.62#ibcon#*before return 0, iclass 5, count 0 2006.175.08:21:52.62#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:52.62#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.175.08:21:52.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:21:52.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:21:52.62$vc4f8/vabw=wide 2006.175.08:21:52.62#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.175.08:21:52.62#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.175.08:21:52.62#ibcon#ireg 8 cls_cnt 0 2006.175.08:21:52.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:52.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:52.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:52.62#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:21:52.62#ibcon#first serial, iclass 7, count 0 2006.175.08:21:52.62#ibcon#enter sib2, iclass 7, count 0 2006.175.08:21:52.62#ibcon#flushed, iclass 7, count 0 2006.175.08:21:52.62#ibcon#about to write, iclass 7, count 0 2006.175.08:21:52.62#ibcon#wrote, iclass 7, count 0 2006.175.08:21:52.62#ibcon#about to read 3, iclass 7, count 0 2006.175.08:21:52.64#ibcon#read 3, iclass 7, count 0 2006.175.08:21:52.64#ibcon#about to read 4, iclass 7, count 0 2006.175.08:21:52.64#ibcon#read 4, iclass 7, count 0 2006.175.08:21:52.64#ibcon#about to read 5, iclass 7, count 0 2006.175.08:21:52.64#ibcon#read 5, iclass 7, count 0 2006.175.08:21:52.64#ibcon#about to read 6, iclass 7, count 0 2006.175.08:21:52.64#ibcon#read 6, iclass 7, count 0 2006.175.08:21:52.64#ibcon#end of sib2, iclass 7, count 0 2006.175.08:21:52.64#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:21:52.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:21:52.64#ibcon#[25=BW32\r\n] 2006.175.08:21:52.64#ibcon#*before write, iclass 7, count 0 2006.175.08:21:52.64#ibcon#enter sib2, iclass 7, count 0 2006.175.08:21:52.64#ibcon#flushed, iclass 7, count 0 2006.175.08:21:52.64#ibcon#about to write, iclass 7, count 0 2006.175.08:21:52.64#ibcon#wrote, iclass 7, count 0 2006.175.08:21:52.64#ibcon#about to read 3, iclass 7, count 0 2006.175.08:21:52.67#ibcon#read 3, iclass 7, count 0 2006.175.08:21:52.67#ibcon#about to read 4, iclass 7, count 0 2006.175.08:21:52.67#ibcon#read 4, iclass 7, count 0 2006.175.08:21:52.67#ibcon#about to read 5, iclass 7, count 0 2006.175.08:21:52.67#ibcon#read 5, iclass 7, count 0 2006.175.08:21:52.67#ibcon#about to read 6, iclass 7, count 0 2006.175.08:21:52.67#ibcon#read 6, iclass 7, count 0 2006.175.08:21:52.67#ibcon#end of sib2, iclass 7, count 0 2006.175.08:21:52.67#ibcon#*after write, iclass 7, count 0 2006.175.08:21:52.67#ibcon#*before return 0, iclass 7, count 0 2006.175.08:21:52.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:52.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.175.08:21:52.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:21:52.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:21:52.67$vc4f8/vbbw=wide 2006.175.08:21:52.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.08:21:52.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.08:21:52.67#ibcon#ireg 8 cls_cnt 0 2006.175.08:21:52.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:21:52.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:21:52.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:21:52.74#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:21:52.74#ibcon#first serial, iclass 11, count 0 2006.175.08:21:52.74#ibcon#enter sib2, iclass 11, count 0 2006.175.08:21:52.74#ibcon#flushed, iclass 11, count 0 2006.175.08:21:52.74#ibcon#about to write, iclass 11, count 0 2006.175.08:21:52.74#ibcon#wrote, iclass 11, count 0 2006.175.08:21:52.74#ibcon#about to read 3, iclass 11, count 0 2006.175.08:21:52.76#ibcon#read 3, iclass 11, count 0 2006.175.08:21:52.76#ibcon#about to read 4, iclass 11, count 0 2006.175.08:21:52.76#ibcon#read 4, iclass 11, count 0 2006.175.08:21:52.76#ibcon#about to read 5, iclass 11, count 0 2006.175.08:21:52.76#ibcon#read 5, iclass 11, count 0 2006.175.08:21:52.76#ibcon#about to read 6, iclass 11, count 0 2006.175.08:21:52.76#ibcon#read 6, iclass 11, count 0 2006.175.08:21:52.76#ibcon#end of sib2, iclass 11, count 0 2006.175.08:21:52.76#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:21:52.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:21:52.76#ibcon#[27=BW32\r\n] 2006.175.08:21:52.76#ibcon#*before write, iclass 11, count 0 2006.175.08:21:52.76#ibcon#enter sib2, iclass 11, count 0 2006.175.08:21:52.76#ibcon#flushed, iclass 11, count 0 2006.175.08:21:52.76#ibcon#about to write, iclass 11, count 0 2006.175.08:21:52.76#ibcon#wrote, iclass 11, count 0 2006.175.08:21:52.76#ibcon#about to read 3, iclass 11, count 0 2006.175.08:21:52.79#ibcon#read 3, iclass 11, count 0 2006.175.08:21:52.79#ibcon#about to read 4, iclass 11, count 0 2006.175.08:21:52.79#ibcon#read 4, iclass 11, count 0 2006.175.08:21:52.79#ibcon#about to read 5, iclass 11, count 0 2006.175.08:21:52.79#ibcon#read 5, iclass 11, count 0 2006.175.08:21:52.79#ibcon#about to read 6, iclass 11, count 0 2006.175.08:21:52.79#ibcon#read 6, iclass 11, count 0 2006.175.08:21:52.79#ibcon#end of sib2, iclass 11, count 0 2006.175.08:21:52.79#ibcon#*after write, iclass 11, count 0 2006.175.08:21:52.79#ibcon#*before return 0, iclass 11, count 0 2006.175.08:21:52.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:21:52.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:21:52.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:21:52.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:21:52.79$4f8m12a/ifd4f 2006.175.08:21:52.79$ifd4f/lo= 2006.175.08:21:52.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:21:52.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:21:52.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:21:52.79$ifd4f/patch= 2006.175.08:21:52.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:21:52.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:21:52.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:21:52.79$4f8m12a/"form=m,16.000,1:2 2006.175.08:21:52.79$4f8m12a/"tpicd 2006.175.08:21:52.79$4f8m12a/echo=off 2006.175.08:21:52.79$4f8m12a/xlog=off 2006.175.08:21:52.79:!2006.175.08:24:00 2006.175.08:22:22.14#trakl#Source acquired 2006.175.08:22:23.14#flagr#flagr/antenna,acquired 2006.175.08:24:00.00:preob 2006.175.08:24:00.13/onsource/TRACKING 2006.175.08:24:00.13:!2006.175.08:24:10 2006.175.08:24:10.00:data_valid=on 2006.175.08:24:10.00:midob 2006.175.08:24:11.13/onsource/TRACKING 2006.175.08:24:11.13/wx/25.65,1007.4,71 2006.175.08:24:11.29/cable/+6.4773E-03 2006.175.08:24:12.38/va/01,08,usb,yes,29,31 2006.175.08:24:12.38/va/02,07,usb,yes,29,31 2006.175.08:24:12.38/va/03,06,usb,yes,31,31 2006.175.08:24:12.38/va/04,07,usb,yes,30,32 2006.175.08:24:12.38/va/05,07,usb,yes,31,33 2006.175.08:24:12.38/va/06,06,usb,yes,30,30 2006.175.08:24:12.38/va/07,06,usb,yes,31,30 2006.175.08:24:12.38/va/08,06,usb,yes,33,32 2006.175.08:24:12.61/valo/01,532.99,yes,locked 2006.175.08:24:12.61/valo/02,572.99,yes,locked 2006.175.08:24:12.61/valo/03,672.99,yes,locked 2006.175.08:24:12.61/valo/04,832.99,yes,locked 2006.175.08:24:12.61/valo/05,652.99,yes,locked 2006.175.08:24:12.61/valo/06,772.99,yes,locked 2006.175.08:24:12.61/valo/07,832.99,yes,locked 2006.175.08:24:12.61/valo/08,852.99,yes,locked 2006.175.08:24:13.70/vb/01,04,usb,yes,29,28 2006.175.08:24:13.70/vb/02,04,usb,yes,31,33 2006.175.08:24:13.70/vb/03,04,usb,yes,28,31 2006.175.08:24:13.70/vb/04,04,usb,yes,28,29 2006.175.08:24:13.70/vb/05,04,usb,yes,27,31 2006.175.08:24:13.70/vb/06,04,usb,yes,28,31 2006.175.08:24:13.70/vb/07,04,usb,yes,30,30 2006.175.08:24:13.70/vb/08,04,usb,yes,28,31 2006.175.08:24:13.94/vblo/01,632.99,yes,locked 2006.175.08:24:13.94/vblo/02,640.99,yes,locked 2006.175.08:24:13.94/vblo/03,656.99,yes,locked 2006.175.08:24:13.94/vblo/04,712.99,yes,locked 2006.175.08:24:13.94/vblo/05,744.99,yes,locked 2006.175.08:24:13.94/vblo/06,752.99,yes,locked 2006.175.08:24:13.94/vblo/07,734.99,yes,locked 2006.175.08:24:13.94/vblo/08,744.99,yes,locked 2006.175.08:24:14.09/vabw/8 2006.175.08:24:14.24/vbbw/8 2006.175.08:24:14.33/xfe/off,on,15.0 2006.175.08:24:14.70/ifatt/23,28,28,28 2006.175.08:24:15.07/fmout-gps/S +3.81E-07 2006.175.08:24:15.15:!2006.175.08:25:10 2006.175.08:25:10.00:data_valid=off 2006.175.08:25:10.00:postob 2006.175.08:25:10.09/cable/+6.4779E-03 2006.175.08:25:10.09/wx/25.64,1007.5,71 2006.175.08:25:11.08/fmout-gps/S +3.81E-07 2006.175.08:25:11.08:scan_name=175-0826,k06175,60 2006.175.08:25:11.09:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.175.08:25:11.13#flagr#flagr/antenna,new-source 2006.175.08:25:12.13:checkk5 2006.175.08:25:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:25:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:25:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:25:13.78/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:25:14.15/chk_obsdata//k5ts1/T1750824??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:25:14.52/chk_obsdata//k5ts2/T1750824??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:25:14.89/chk_obsdata//k5ts3/T1750824??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:25:15.26/chk_obsdata//k5ts4/T1750824??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:25:15.95/k5log//k5ts1_log_newline 2006.175.08:25:16.64/k5log//k5ts2_log_newline 2006.175.08:25:17.34/k5log//k5ts3_log_newline 2006.175.08:25:18.03/k5log//k5ts4_log_newline 2006.175.08:25:18.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:25:18.09:4f8m12a=3 2006.175.08:25:18.09$4f8m12a/echo=on 2006.175.08:25:18.09$4f8m12a/pcalon 2006.175.08:25:18.09$pcalon/"no phase cal control is implemented here 2006.175.08:25:18.09$4f8m12a/"tpicd=stop 2006.175.08:25:18.09$4f8m12a/vc4f8 2006.175.08:25:18.09$vc4f8/valo=1,532.99 2006.175.08:25:18.09#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.08:25:18.09#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.08:25:18.09#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:18.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:18.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:18.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:18.09#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:25:18.09#ibcon#first serial, iclass 22, count 0 2006.175.08:25:18.09#ibcon#enter sib2, iclass 22, count 0 2006.175.08:25:18.09#ibcon#flushed, iclass 22, count 0 2006.175.08:25:18.09#ibcon#about to write, iclass 22, count 0 2006.175.08:25:18.09#ibcon#wrote, iclass 22, count 0 2006.175.08:25:18.09#ibcon#about to read 3, iclass 22, count 0 2006.175.08:25:18.11#ibcon#read 3, iclass 22, count 0 2006.175.08:25:18.11#ibcon#about to read 4, iclass 22, count 0 2006.175.08:25:18.11#ibcon#read 4, iclass 22, count 0 2006.175.08:25:18.11#ibcon#about to read 5, iclass 22, count 0 2006.175.08:25:18.11#ibcon#read 5, iclass 22, count 0 2006.175.08:25:18.11#ibcon#about to read 6, iclass 22, count 0 2006.175.08:25:18.11#ibcon#read 6, iclass 22, count 0 2006.175.08:25:18.11#ibcon#end of sib2, iclass 22, count 0 2006.175.08:25:18.11#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:25:18.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:25:18.11#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:25:18.11#ibcon#*before write, iclass 22, count 0 2006.175.08:25:18.11#ibcon#enter sib2, iclass 22, count 0 2006.175.08:25:18.11#ibcon#flushed, iclass 22, count 0 2006.175.08:25:18.11#ibcon#about to write, iclass 22, count 0 2006.175.08:25:18.11#ibcon#wrote, iclass 22, count 0 2006.175.08:25:18.11#ibcon#about to read 3, iclass 22, count 0 2006.175.08:25:18.16#ibcon#read 3, iclass 22, count 0 2006.175.08:25:18.16#ibcon#about to read 4, iclass 22, count 0 2006.175.08:25:18.16#ibcon#read 4, iclass 22, count 0 2006.175.08:25:18.16#ibcon#about to read 5, iclass 22, count 0 2006.175.08:25:18.16#ibcon#read 5, iclass 22, count 0 2006.175.08:25:18.16#ibcon#about to read 6, iclass 22, count 0 2006.175.08:25:18.16#ibcon#read 6, iclass 22, count 0 2006.175.08:25:18.16#ibcon#end of sib2, iclass 22, count 0 2006.175.08:25:18.16#ibcon#*after write, iclass 22, count 0 2006.175.08:25:18.16#ibcon#*before return 0, iclass 22, count 0 2006.175.08:25:18.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:18.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:18.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:25:18.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:25:18.16$vc4f8/va=1,8 2006.175.08:25:18.16#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.08:25:18.16#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.08:25:18.16#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:18.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:25:18.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:25:18.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:25:18.16#ibcon#enter wrdev, iclass 25, count 2 2006.175.08:25:18.16#ibcon#first serial, iclass 25, count 2 2006.175.08:25:18.16#ibcon#enter sib2, iclass 25, count 2 2006.175.08:25:18.16#ibcon#flushed, iclass 25, count 2 2006.175.08:25:18.16#ibcon#about to write, iclass 25, count 2 2006.175.08:25:18.16#ibcon#wrote, iclass 25, count 2 2006.175.08:25:18.16#ibcon#about to read 3, iclass 25, count 2 2006.175.08:25:18.18#ibcon#read 3, iclass 25, count 2 2006.175.08:25:18.18#ibcon#about to read 4, iclass 25, count 2 2006.175.08:25:18.18#ibcon#read 4, iclass 25, count 2 2006.175.08:25:18.18#ibcon#about to read 5, iclass 25, count 2 2006.175.08:25:18.18#ibcon#read 5, iclass 25, count 2 2006.175.08:25:18.18#ibcon#about to read 6, iclass 25, count 2 2006.175.08:25:18.18#ibcon#read 6, iclass 25, count 2 2006.175.08:25:18.18#ibcon#end of sib2, iclass 25, count 2 2006.175.08:25:18.18#ibcon#*mode == 0, iclass 25, count 2 2006.175.08:25:18.18#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.08:25:18.18#ibcon#[25=AT01-08\r\n] 2006.175.08:25:18.18#ibcon#*before write, iclass 25, count 2 2006.175.08:25:18.18#ibcon#enter sib2, iclass 25, count 2 2006.175.08:25:18.18#ibcon#flushed, iclass 25, count 2 2006.175.08:25:18.18#ibcon#about to write, iclass 25, count 2 2006.175.08:25:18.18#ibcon#wrote, iclass 25, count 2 2006.175.08:25:18.18#ibcon#about to read 3, iclass 25, count 2 2006.175.08:25:18.20#abcon#<5=/05 3.9 6.7 25.63 711007.5\r\n> 2006.175.08:25:18.21#ibcon#read 3, iclass 25, count 2 2006.175.08:25:18.21#ibcon#about to read 4, iclass 25, count 2 2006.175.08:25:18.21#ibcon#read 4, iclass 25, count 2 2006.175.08:25:18.21#ibcon#about to read 5, iclass 25, count 2 2006.175.08:25:18.21#ibcon#read 5, iclass 25, count 2 2006.175.08:25:18.21#ibcon#about to read 6, iclass 25, count 2 2006.175.08:25:18.21#ibcon#read 6, iclass 25, count 2 2006.175.08:25:18.21#ibcon#end of sib2, iclass 25, count 2 2006.175.08:25:18.21#ibcon#*after write, iclass 25, count 2 2006.175.08:25:18.21#ibcon#*before return 0, iclass 25, count 2 2006.175.08:25:18.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:25:18.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:25:18.21#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.08:25:18.21#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:18.21#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:25:18.22#abcon#{5=INTERFACE CLEAR} 2006.175.08:25:18.28#abcon#[5=S1D000X0/0*\r\n] 2006.175.08:25:18.33#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:25:18.33#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:25:18.33#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:25:18.33#ibcon#first serial, iclass 25, count 0 2006.175.08:25:18.33#ibcon#enter sib2, iclass 25, count 0 2006.175.08:25:18.33#ibcon#flushed, iclass 25, count 0 2006.175.08:25:18.33#ibcon#about to write, iclass 25, count 0 2006.175.08:25:18.33#ibcon#wrote, iclass 25, count 0 2006.175.08:25:18.33#ibcon#about to read 3, iclass 25, count 0 2006.175.08:25:18.36#ibcon#read 3, iclass 25, count 0 2006.175.08:25:18.36#ibcon#about to read 4, iclass 25, count 0 2006.175.08:25:18.36#ibcon#read 4, iclass 25, count 0 2006.175.08:25:18.36#ibcon#about to read 5, iclass 25, count 0 2006.175.08:25:18.36#ibcon#read 5, iclass 25, count 0 2006.175.08:25:18.36#ibcon#about to read 6, iclass 25, count 0 2006.175.08:25:18.36#ibcon#read 6, iclass 25, count 0 2006.175.08:25:18.36#ibcon#end of sib2, iclass 25, count 0 2006.175.08:25:18.36#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:25:18.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:25:18.36#ibcon#[25=USB\r\n] 2006.175.08:25:18.36#ibcon#*before write, iclass 25, count 0 2006.175.08:25:18.36#ibcon#enter sib2, iclass 25, count 0 2006.175.08:25:18.36#ibcon#flushed, iclass 25, count 0 2006.175.08:25:18.36#ibcon#about to write, iclass 25, count 0 2006.175.08:25:18.36#ibcon#wrote, iclass 25, count 0 2006.175.08:25:18.36#ibcon#about to read 3, iclass 25, count 0 2006.175.08:25:18.39#ibcon#read 3, iclass 25, count 0 2006.175.08:25:18.39#ibcon#about to read 4, iclass 25, count 0 2006.175.08:25:18.39#ibcon#read 4, iclass 25, count 0 2006.175.08:25:18.39#ibcon#about to read 5, iclass 25, count 0 2006.175.08:25:18.39#ibcon#read 5, iclass 25, count 0 2006.175.08:25:18.39#ibcon#about to read 6, iclass 25, count 0 2006.175.08:25:18.39#ibcon#read 6, iclass 25, count 0 2006.175.08:25:18.39#ibcon#end of sib2, iclass 25, count 0 2006.175.08:25:18.39#ibcon#*after write, iclass 25, count 0 2006.175.08:25:18.39#ibcon#*before return 0, iclass 25, count 0 2006.175.08:25:18.39#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:25:18.39#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:25:18.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:25:18.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:25:18.39$vc4f8/valo=2,572.99 2006.175.08:25:18.39#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.08:25:18.39#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.08:25:18.39#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:18.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:18.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:18.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:18.39#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:25:18.39#ibcon#first serial, iclass 30, count 0 2006.175.08:25:18.39#ibcon#enter sib2, iclass 30, count 0 2006.175.08:25:18.39#ibcon#flushed, iclass 30, count 0 2006.175.08:25:18.39#ibcon#about to write, iclass 30, count 0 2006.175.08:25:18.39#ibcon#wrote, iclass 30, count 0 2006.175.08:25:18.39#ibcon#about to read 3, iclass 30, count 0 2006.175.08:25:18.41#ibcon#read 3, iclass 30, count 0 2006.175.08:25:18.41#ibcon#about to read 4, iclass 30, count 0 2006.175.08:25:18.41#ibcon#read 4, iclass 30, count 0 2006.175.08:25:18.41#ibcon#about to read 5, iclass 30, count 0 2006.175.08:25:18.41#ibcon#read 5, iclass 30, count 0 2006.175.08:25:18.41#ibcon#about to read 6, iclass 30, count 0 2006.175.08:25:18.41#ibcon#read 6, iclass 30, count 0 2006.175.08:25:18.41#ibcon#end of sib2, iclass 30, count 0 2006.175.08:25:18.41#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:25:18.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:25:18.41#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:25:18.41#ibcon#*before write, iclass 30, count 0 2006.175.08:25:18.41#ibcon#enter sib2, iclass 30, count 0 2006.175.08:25:18.41#ibcon#flushed, iclass 30, count 0 2006.175.08:25:18.41#ibcon#about to write, iclass 30, count 0 2006.175.08:25:18.41#ibcon#wrote, iclass 30, count 0 2006.175.08:25:18.41#ibcon#about to read 3, iclass 30, count 0 2006.175.08:25:18.45#ibcon#read 3, iclass 30, count 0 2006.175.08:25:18.45#ibcon#about to read 4, iclass 30, count 0 2006.175.08:25:18.45#ibcon#read 4, iclass 30, count 0 2006.175.08:25:18.45#ibcon#about to read 5, iclass 30, count 0 2006.175.08:25:18.45#ibcon#read 5, iclass 30, count 0 2006.175.08:25:18.45#ibcon#about to read 6, iclass 30, count 0 2006.175.08:25:18.45#ibcon#read 6, iclass 30, count 0 2006.175.08:25:18.45#ibcon#end of sib2, iclass 30, count 0 2006.175.08:25:18.45#ibcon#*after write, iclass 30, count 0 2006.175.08:25:18.45#ibcon#*before return 0, iclass 30, count 0 2006.175.08:25:18.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:18.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:18.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:25:18.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:25:18.45$vc4f8/va=2,7 2006.175.08:25:18.45#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.08:25:18.45#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.08:25:18.45#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:18.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:18.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:18.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:18.51#ibcon#enter wrdev, iclass 32, count 2 2006.175.08:25:18.51#ibcon#first serial, iclass 32, count 2 2006.175.08:25:18.51#ibcon#enter sib2, iclass 32, count 2 2006.175.08:25:18.51#ibcon#flushed, iclass 32, count 2 2006.175.08:25:18.51#ibcon#about to write, iclass 32, count 2 2006.175.08:25:18.51#ibcon#wrote, iclass 32, count 2 2006.175.08:25:18.51#ibcon#about to read 3, iclass 32, count 2 2006.175.08:25:18.53#ibcon#read 3, iclass 32, count 2 2006.175.08:25:18.53#ibcon#about to read 4, iclass 32, count 2 2006.175.08:25:18.53#ibcon#read 4, iclass 32, count 2 2006.175.08:25:18.53#ibcon#about to read 5, iclass 32, count 2 2006.175.08:25:18.53#ibcon#read 5, iclass 32, count 2 2006.175.08:25:18.53#ibcon#about to read 6, iclass 32, count 2 2006.175.08:25:18.53#ibcon#read 6, iclass 32, count 2 2006.175.08:25:18.53#ibcon#end of sib2, iclass 32, count 2 2006.175.08:25:18.53#ibcon#*mode == 0, iclass 32, count 2 2006.175.08:25:18.53#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.08:25:18.53#ibcon#[25=AT02-07\r\n] 2006.175.08:25:18.53#ibcon#*before write, iclass 32, count 2 2006.175.08:25:18.53#ibcon#enter sib2, iclass 32, count 2 2006.175.08:25:18.53#ibcon#flushed, iclass 32, count 2 2006.175.08:25:18.53#ibcon#about to write, iclass 32, count 2 2006.175.08:25:18.53#ibcon#wrote, iclass 32, count 2 2006.175.08:25:18.53#ibcon#about to read 3, iclass 32, count 2 2006.175.08:25:18.56#ibcon#read 3, iclass 32, count 2 2006.175.08:25:18.56#ibcon#about to read 4, iclass 32, count 2 2006.175.08:25:18.56#ibcon#read 4, iclass 32, count 2 2006.175.08:25:18.56#ibcon#about to read 5, iclass 32, count 2 2006.175.08:25:18.56#ibcon#read 5, iclass 32, count 2 2006.175.08:25:18.56#ibcon#about to read 6, iclass 32, count 2 2006.175.08:25:18.56#ibcon#read 6, iclass 32, count 2 2006.175.08:25:18.56#ibcon#end of sib2, iclass 32, count 2 2006.175.08:25:18.56#ibcon#*after write, iclass 32, count 2 2006.175.08:25:18.56#ibcon#*before return 0, iclass 32, count 2 2006.175.08:25:18.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:18.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:18.56#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.08:25:18.56#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:18.56#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:18.68#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:18.68#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:18.68#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:25:18.68#ibcon#first serial, iclass 32, count 0 2006.175.08:25:18.68#ibcon#enter sib2, iclass 32, count 0 2006.175.08:25:18.68#ibcon#flushed, iclass 32, count 0 2006.175.08:25:18.68#ibcon#about to write, iclass 32, count 0 2006.175.08:25:18.68#ibcon#wrote, iclass 32, count 0 2006.175.08:25:18.68#ibcon#about to read 3, iclass 32, count 0 2006.175.08:25:18.70#ibcon#read 3, iclass 32, count 0 2006.175.08:25:18.70#ibcon#about to read 4, iclass 32, count 0 2006.175.08:25:18.70#ibcon#read 4, iclass 32, count 0 2006.175.08:25:18.70#ibcon#about to read 5, iclass 32, count 0 2006.175.08:25:18.70#ibcon#read 5, iclass 32, count 0 2006.175.08:25:18.70#ibcon#about to read 6, iclass 32, count 0 2006.175.08:25:18.70#ibcon#read 6, iclass 32, count 0 2006.175.08:25:18.70#ibcon#end of sib2, iclass 32, count 0 2006.175.08:25:18.70#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:25:18.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:25:18.70#ibcon#[25=USB\r\n] 2006.175.08:25:18.70#ibcon#*before write, iclass 32, count 0 2006.175.08:25:18.70#ibcon#enter sib2, iclass 32, count 0 2006.175.08:25:18.70#ibcon#flushed, iclass 32, count 0 2006.175.08:25:18.70#ibcon#about to write, iclass 32, count 0 2006.175.08:25:18.70#ibcon#wrote, iclass 32, count 0 2006.175.08:25:18.70#ibcon#about to read 3, iclass 32, count 0 2006.175.08:25:18.73#ibcon#read 3, iclass 32, count 0 2006.175.08:25:18.73#ibcon#about to read 4, iclass 32, count 0 2006.175.08:25:18.73#ibcon#read 4, iclass 32, count 0 2006.175.08:25:18.73#ibcon#about to read 5, iclass 32, count 0 2006.175.08:25:18.73#ibcon#read 5, iclass 32, count 0 2006.175.08:25:18.73#ibcon#about to read 6, iclass 32, count 0 2006.175.08:25:18.73#ibcon#read 6, iclass 32, count 0 2006.175.08:25:18.73#ibcon#end of sib2, iclass 32, count 0 2006.175.08:25:18.73#ibcon#*after write, iclass 32, count 0 2006.175.08:25:18.73#ibcon#*before return 0, iclass 32, count 0 2006.175.08:25:18.73#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:18.73#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:18.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:25:18.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:25:18.73$vc4f8/valo=3,672.99 2006.175.08:25:18.73#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.08:25:18.73#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.08:25:18.73#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:18.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:18.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:18.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:18.73#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:25:18.73#ibcon#first serial, iclass 34, count 0 2006.175.08:25:18.73#ibcon#enter sib2, iclass 34, count 0 2006.175.08:25:18.73#ibcon#flushed, iclass 34, count 0 2006.175.08:25:18.73#ibcon#about to write, iclass 34, count 0 2006.175.08:25:18.73#ibcon#wrote, iclass 34, count 0 2006.175.08:25:18.73#ibcon#about to read 3, iclass 34, count 0 2006.175.08:25:18.75#ibcon#read 3, iclass 34, count 0 2006.175.08:25:18.75#ibcon#about to read 4, iclass 34, count 0 2006.175.08:25:18.75#ibcon#read 4, iclass 34, count 0 2006.175.08:25:18.75#ibcon#about to read 5, iclass 34, count 0 2006.175.08:25:18.75#ibcon#read 5, iclass 34, count 0 2006.175.08:25:18.75#ibcon#about to read 6, iclass 34, count 0 2006.175.08:25:18.75#ibcon#read 6, iclass 34, count 0 2006.175.08:25:18.75#ibcon#end of sib2, iclass 34, count 0 2006.175.08:25:18.75#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:25:18.75#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:25:18.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:25:18.75#ibcon#*before write, iclass 34, count 0 2006.175.08:25:18.75#ibcon#enter sib2, iclass 34, count 0 2006.175.08:25:18.75#ibcon#flushed, iclass 34, count 0 2006.175.08:25:18.75#ibcon#about to write, iclass 34, count 0 2006.175.08:25:18.75#ibcon#wrote, iclass 34, count 0 2006.175.08:25:18.75#ibcon#about to read 3, iclass 34, count 0 2006.175.08:25:18.79#ibcon#read 3, iclass 34, count 0 2006.175.08:25:18.79#ibcon#about to read 4, iclass 34, count 0 2006.175.08:25:18.79#ibcon#read 4, iclass 34, count 0 2006.175.08:25:18.79#ibcon#about to read 5, iclass 34, count 0 2006.175.08:25:18.79#ibcon#read 5, iclass 34, count 0 2006.175.08:25:18.79#ibcon#about to read 6, iclass 34, count 0 2006.175.08:25:18.79#ibcon#read 6, iclass 34, count 0 2006.175.08:25:18.79#ibcon#end of sib2, iclass 34, count 0 2006.175.08:25:18.79#ibcon#*after write, iclass 34, count 0 2006.175.08:25:18.79#ibcon#*before return 0, iclass 34, count 0 2006.175.08:25:18.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:18.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:18.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:25:18.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:25:18.79$vc4f8/va=3,6 2006.175.08:25:18.79#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.08:25:18.79#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.08:25:18.79#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:18.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:18.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:18.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:18.85#ibcon#enter wrdev, iclass 36, count 2 2006.175.08:25:18.85#ibcon#first serial, iclass 36, count 2 2006.175.08:25:18.85#ibcon#enter sib2, iclass 36, count 2 2006.175.08:25:18.85#ibcon#flushed, iclass 36, count 2 2006.175.08:25:18.85#ibcon#about to write, iclass 36, count 2 2006.175.08:25:18.85#ibcon#wrote, iclass 36, count 2 2006.175.08:25:18.85#ibcon#about to read 3, iclass 36, count 2 2006.175.08:25:18.87#ibcon#read 3, iclass 36, count 2 2006.175.08:25:18.87#ibcon#about to read 4, iclass 36, count 2 2006.175.08:25:18.87#ibcon#read 4, iclass 36, count 2 2006.175.08:25:18.87#ibcon#about to read 5, iclass 36, count 2 2006.175.08:25:18.87#ibcon#read 5, iclass 36, count 2 2006.175.08:25:18.87#ibcon#about to read 6, iclass 36, count 2 2006.175.08:25:18.87#ibcon#read 6, iclass 36, count 2 2006.175.08:25:18.87#ibcon#end of sib2, iclass 36, count 2 2006.175.08:25:18.87#ibcon#*mode == 0, iclass 36, count 2 2006.175.08:25:18.87#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.08:25:18.87#ibcon#[25=AT03-06\r\n] 2006.175.08:25:18.87#ibcon#*before write, iclass 36, count 2 2006.175.08:25:18.87#ibcon#enter sib2, iclass 36, count 2 2006.175.08:25:18.87#ibcon#flushed, iclass 36, count 2 2006.175.08:25:18.87#ibcon#about to write, iclass 36, count 2 2006.175.08:25:18.87#ibcon#wrote, iclass 36, count 2 2006.175.08:25:18.87#ibcon#about to read 3, iclass 36, count 2 2006.175.08:25:18.90#ibcon#read 3, iclass 36, count 2 2006.175.08:25:18.90#ibcon#about to read 4, iclass 36, count 2 2006.175.08:25:18.90#ibcon#read 4, iclass 36, count 2 2006.175.08:25:18.90#ibcon#about to read 5, iclass 36, count 2 2006.175.08:25:18.90#ibcon#read 5, iclass 36, count 2 2006.175.08:25:18.90#ibcon#about to read 6, iclass 36, count 2 2006.175.08:25:18.90#ibcon#read 6, iclass 36, count 2 2006.175.08:25:18.90#ibcon#end of sib2, iclass 36, count 2 2006.175.08:25:18.90#ibcon#*after write, iclass 36, count 2 2006.175.08:25:18.90#ibcon#*before return 0, iclass 36, count 2 2006.175.08:25:18.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:18.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:18.90#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.08:25:18.90#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:18.90#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:19.02#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:19.02#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:19.02#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:25:19.02#ibcon#first serial, iclass 36, count 0 2006.175.08:25:19.02#ibcon#enter sib2, iclass 36, count 0 2006.175.08:25:19.02#ibcon#flushed, iclass 36, count 0 2006.175.08:25:19.02#ibcon#about to write, iclass 36, count 0 2006.175.08:25:19.02#ibcon#wrote, iclass 36, count 0 2006.175.08:25:19.02#ibcon#about to read 3, iclass 36, count 0 2006.175.08:25:19.04#ibcon#read 3, iclass 36, count 0 2006.175.08:25:19.04#ibcon#about to read 4, iclass 36, count 0 2006.175.08:25:19.04#ibcon#read 4, iclass 36, count 0 2006.175.08:25:19.04#ibcon#about to read 5, iclass 36, count 0 2006.175.08:25:19.04#ibcon#read 5, iclass 36, count 0 2006.175.08:25:19.04#ibcon#about to read 6, iclass 36, count 0 2006.175.08:25:19.04#ibcon#read 6, iclass 36, count 0 2006.175.08:25:19.04#ibcon#end of sib2, iclass 36, count 0 2006.175.08:25:19.04#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:25:19.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:25:19.04#ibcon#[25=USB\r\n] 2006.175.08:25:19.04#ibcon#*before write, iclass 36, count 0 2006.175.08:25:19.04#ibcon#enter sib2, iclass 36, count 0 2006.175.08:25:19.04#ibcon#flushed, iclass 36, count 0 2006.175.08:25:19.04#ibcon#about to write, iclass 36, count 0 2006.175.08:25:19.04#ibcon#wrote, iclass 36, count 0 2006.175.08:25:19.04#ibcon#about to read 3, iclass 36, count 0 2006.175.08:25:19.07#ibcon#read 3, iclass 36, count 0 2006.175.08:25:19.07#ibcon#about to read 4, iclass 36, count 0 2006.175.08:25:19.07#ibcon#read 4, iclass 36, count 0 2006.175.08:25:19.07#ibcon#about to read 5, iclass 36, count 0 2006.175.08:25:19.07#ibcon#read 5, iclass 36, count 0 2006.175.08:25:19.07#ibcon#about to read 6, iclass 36, count 0 2006.175.08:25:19.07#ibcon#read 6, iclass 36, count 0 2006.175.08:25:19.07#ibcon#end of sib2, iclass 36, count 0 2006.175.08:25:19.07#ibcon#*after write, iclass 36, count 0 2006.175.08:25:19.07#ibcon#*before return 0, iclass 36, count 0 2006.175.08:25:19.07#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:19.07#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:19.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:25:19.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:25:19.07$vc4f8/valo=4,832.99 2006.175.08:25:19.07#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.08:25:19.07#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.08:25:19.07#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:19.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:19.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:19.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:19.07#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:25:19.07#ibcon#first serial, iclass 38, count 0 2006.175.08:25:19.07#ibcon#enter sib2, iclass 38, count 0 2006.175.08:25:19.07#ibcon#flushed, iclass 38, count 0 2006.175.08:25:19.07#ibcon#about to write, iclass 38, count 0 2006.175.08:25:19.07#ibcon#wrote, iclass 38, count 0 2006.175.08:25:19.07#ibcon#about to read 3, iclass 38, count 0 2006.175.08:25:19.09#ibcon#read 3, iclass 38, count 0 2006.175.08:25:19.09#ibcon#about to read 4, iclass 38, count 0 2006.175.08:25:19.09#ibcon#read 4, iclass 38, count 0 2006.175.08:25:19.09#ibcon#about to read 5, iclass 38, count 0 2006.175.08:25:19.09#ibcon#read 5, iclass 38, count 0 2006.175.08:25:19.09#ibcon#about to read 6, iclass 38, count 0 2006.175.08:25:19.09#ibcon#read 6, iclass 38, count 0 2006.175.08:25:19.09#ibcon#end of sib2, iclass 38, count 0 2006.175.08:25:19.09#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:25:19.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:25:19.09#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:25:19.09#ibcon#*before write, iclass 38, count 0 2006.175.08:25:19.09#ibcon#enter sib2, iclass 38, count 0 2006.175.08:25:19.09#ibcon#flushed, iclass 38, count 0 2006.175.08:25:19.09#ibcon#about to write, iclass 38, count 0 2006.175.08:25:19.09#ibcon#wrote, iclass 38, count 0 2006.175.08:25:19.09#ibcon#about to read 3, iclass 38, count 0 2006.175.08:25:19.13#ibcon#read 3, iclass 38, count 0 2006.175.08:25:19.13#ibcon#about to read 4, iclass 38, count 0 2006.175.08:25:19.13#ibcon#read 4, iclass 38, count 0 2006.175.08:25:19.13#ibcon#about to read 5, iclass 38, count 0 2006.175.08:25:19.13#ibcon#read 5, iclass 38, count 0 2006.175.08:25:19.13#ibcon#about to read 6, iclass 38, count 0 2006.175.08:25:19.13#ibcon#read 6, iclass 38, count 0 2006.175.08:25:19.13#ibcon#end of sib2, iclass 38, count 0 2006.175.08:25:19.13#ibcon#*after write, iclass 38, count 0 2006.175.08:25:19.13#ibcon#*before return 0, iclass 38, count 0 2006.175.08:25:19.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:19.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:19.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:25:19.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:25:19.13$vc4f8/va=4,7 2006.175.08:25:19.13#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.08:25:19.13#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.08:25:19.13#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:19.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:19.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:19.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:19.19#ibcon#enter wrdev, iclass 40, count 2 2006.175.08:25:19.19#ibcon#first serial, iclass 40, count 2 2006.175.08:25:19.19#ibcon#enter sib2, iclass 40, count 2 2006.175.08:25:19.19#ibcon#flushed, iclass 40, count 2 2006.175.08:25:19.19#ibcon#about to write, iclass 40, count 2 2006.175.08:25:19.19#ibcon#wrote, iclass 40, count 2 2006.175.08:25:19.19#ibcon#about to read 3, iclass 40, count 2 2006.175.08:25:19.21#ibcon#read 3, iclass 40, count 2 2006.175.08:25:19.21#ibcon#about to read 4, iclass 40, count 2 2006.175.08:25:19.21#ibcon#read 4, iclass 40, count 2 2006.175.08:25:19.21#ibcon#about to read 5, iclass 40, count 2 2006.175.08:25:19.21#ibcon#read 5, iclass 40, count 2 2006.175.08:25:19.21#ibcon#about to read 6, iclass 40, count 2 2006.175.08:25:19.21#ibcon#read 6, iclass 40, count 2 2006.175.08:25:19.21#ibcon#end of sib2, iclass 40, count 2 2006.175.08:25:19.21#ibcon#*mode == 0, iclass 40, count 2 2006.175.08:25:19.21#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.08:25:19.21#ibcon#[25=AT04-07\r\n] 2006.175.08:25:19.21#ibcon#*before write, iclass 40, count 2 2006.175.08:25:19.21#ibcon#enter sib2, iclass 40, count 2 2006.175.08:25:19.21#ibcon#flushed, iclass 40, count 2 2006.175.08:25:19.21#ibcon#about to write, iclass 40, count 2 2006.175.08:25:19.21#ibcon#wrote, iclass 40, count 2 2006.175.08:25:19.21#ibcon#about to read 3, iclass 40, count 2 2006.175.08:25:19.24#ibcon#read 3, iclass 40, count 2 2006.175.08:25:19.24#ibcon#about to read 4, iclass 40, count 2 2006.175.08:25:19.24#ibcon#read 4, iclass 40, count 2 2006.175.08:25:19.24#ibcon#about to read 5, iclass 40, count 2 2006.175.08:25:19.24#ibcon#read 5, iclass 40, count 2 2006.175.08:25:19.24#ibcon#about to read 6, iclass 40, count 2 2006.175.08:25:19.24#ibcon#read 6, iclass 40, count 2 2006.175.08:25:19.24#ibcon#end of sib2, iclass 40, count 2 2006.175.08:25:19.24#ibcon#*after write, iclass 40, count 2 2006.175.08:25:19.24#ibcon#*before return 0, iclass 40, count 2 2006.175.08:25:19.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:19.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:19.24#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.08:25:19.24#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:19.24#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:19.36#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:19.36#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:19.36#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:25:19.36#ibcon#first serial, iclass 40, count 0 2006.175.08:25:19.36#ibcon#enter sib2, iclass 40, count 0 2006.175.08:25:19.36#ibcon#flushed, iclass 40, count 0 2006.175.08:25:19.36#ibcon#about to write, iclass 40, count 0 2006.175.08:25:19.36#ibcon#wrote, iclass 40, count 0 2006.175.08:25:19.36#ibcon#about to read 3, iclass 40, count 0 2006.175.08:25:19.38#ibcon#read 3, iclass 40, count 0 2006.175.08:25:19.38#ibcon#about to read 4, iclass 40, count 0 2006.175.08:25:19.38#ibcon#read 4, iclass 40, count 0 2006.175.08:25:19.38#ibcon#about to read 5, iclass 40, count 0 2006.175.08:25:19.38#ibcon#read 5, iclass 40, count 0 2006.175.08:25:19.38#ibcon#about to read 6, iclass 40, count 0 2006.175.08:25:19.38#ibcon#read 6, iclass 40, count 0 2006.175.08:25:19.38#ibcon#end of sib2, iclass 40, count 0 2006.175.08:25:19.38#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:25:19.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:25:19.38#ibcon#[25=USB\r\n] 2006.175.08:25:19.38#ibcon#*before write, iclass 40, count 0 2006.175.08:25:19.38#ibcon#enter sib2, iclass 40, count 0 2006.175.08:25:19.38#ibcon#flushed, iclass 40, count 0 2006.175.08:25:19.38#ibcon#about to write, iclass 40, count 0 2006.175.08:25:19.38#ibcon#wrote, iclass 40, count 0 2006.175.08:25:19.38#ibcon#about to read 3, iclass 40, count 0 2006.175.08:25:19.41#ibcon#read 3, iclass 40, count 0 2006.175.08:25:19.41#ibcon#about to read 4, iclass 40, count 0 2006.175.08:25:19.41#ibcon#read 4, iclass 40, count 0 2006.175.08:25:19.41#ibcon#about to read 5, iclass 40, count 0 2006.175.08:25:19.41#ibcon#read 5, iclass 40, count 0 2006.175.08:25:19.41#ibcon#about to read 6, iclass 40, count 0 2006.175.08:25:19.41#ibcon#read 6, iclass 40, count 0 2006.175.08:25:19.41#ibcon#end of sib2, iclass 40, count 0 2006.175.08:25:19.41#ibcon#*after write, iclass 40, count 0 2006.175.08:25:19.41#ibcon#*before return 0, iclass 40, count 0 2006.175.08:25:19.41#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:19.41#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:19.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:25:19.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:25:19.41$vc4f8/valo=5,652.99 2006.175.08:25:19.41#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.08:25:19.41#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.08:25:19.41#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:19.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:19.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:19.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:19.41#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:25:19.41#ibcon#first serial, iclass 4, count 0 2006.175.08:25:19.41#ibcon#enter sib2, iclass 4, count 0 2006.175.08:25:19.41#ibcon#flushed, iclass 4, count 0 2006.175.08:25:19.41#ibcon#about to write, iclass 4, count 0 2006.175.08:25:19.41#ibcon#wrote, iclass 4, count 0 2006.175.08:25:19.41#ibcon#about to read 3, iclass 4, count 0 2006.175.08:25:19.43#ibcon#read 3, iclass 4, count 0 2006.175.08:25:19.43#ibcon#about to read 4, iclass 4, count 0 2006.175.08:25:19.43#ibcon#read 4, iclass 4, count 0 2006.175.08:25:19.43#ibcon#about to read 5, iclass 4, count 0 2006.175.08:25:19.43#ibcon#read 5, iclass 4, count 0 2006.175.08:25:19.43#ibcon#about to read 6, iclass 4, count 0 2006.175.08:25:19.43#ibcon#read 6, iclass 4, count 0 2006.175.08:25:19.43#ibcon#end of sib2, iclass 4, count 0 2006.175.08:25:19.43#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:25:19.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:25:19.43#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:25:19.43#ibcon#*before write, iclass 4, count 0 2006.175.08:25:19.43#ibcon#enter sib2, iclass 4, count 0 2006.175.08:25:19.43#ibcon#flushed, iclass 4, count 0 2006.175.08:25:19.43#ibcon#about to write, iclass 4, count 0 2006.175.08:25:19.43#ibcon#wrote, iclass 4, count 0 2006.175.08:25:19.43#ibcon#about to read 3, iclass 4, count 0 2006.175.08:25:19.47#ibcon#read 3, iclass 4, count 0 2006.175.08:25:19.47#ibcon#about to read 4, iclass 4, count 0 2006.175.08:25:19.47#ibcon#read 4, iclass 4, count 0 2006.175.08:25:19.47#ibcon#about to read 5, iclass 4, count 0 2006.175.08:25:19.47#ibcon#read 5, iclass 4, count 0 2006.175.08:25:19.47#ibcon#about to read 6, iclass 4, count 0 2006.175.08:25:19.47#ibcon#read 6, iclass 4, count 0 2006.175.08:25:19.47#ibcon#end of sib2, iclass 4, count 0 2006.175.08:25:19.47#ibcon#*after write, iclass 4, count 0 2006.175.08:25:19.47#ibcon#*before return 0, iclass 4, count 0 2006.175.08:25:19.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:19.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:19.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:25:19.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:25:19.47$vc4f8/va=5,7 2006.175.08:25:19.47#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.08:25:19.47#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.08:25:19.47#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:19.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:19.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:19.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:19.53#ibcon#enter wrdev, iclass 6, count 2 2006.175.08:25:19.53#ibcon#first serial, iclass 6, count 2 2006.175.08:25:19.53#ibcon#enter sib2, iclass 6, count 2 2006.175.08:25:19.53#ibcon#flushed, iclass 6, count 2 2006.175.08:25:19.53#ibcon#about to write, iclass 6, count 2 2006.175.08:25:19.53#ibcon#wrote, iclass 6, count 2 2006.175.08:25:19.53#ibcon#about to read 3, iclass 6, count 2 2006.175.08:25:19.55#ibcon#read 3, iclass 6, count 2 2006.175.08:25:19.55#ibcon#about to read 4, iclass 6, count 2 2006.175.08:25:19.55#ibcon#read 4, iclass 6, count 2 2006.175.08:25:19.55#ibcon#about to read 5, iclass 6, count 2 2006.175.08:25:19.55#ibcon#read 5, iclass 6, count 2 2006.175.08:25:19.55#ibcon#about to read 6, iclass 6, count 2 2006.175.08:25:19.55#ibcon#read 6, iclass 6, count 2 2006.175.08:25:19.55#ibcon#end of sib2, iclass 6, count 2 2006.175.08:25:19.55#ibcon#*mode == 0, iclass 6, count 2 2006.175.08:25:19.55#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.08:25:19.55#ibcon#[25=AT05-07\r\n] 2006.175.08:25:19.55#ibcon#*before write, iclass 6, count 2 2006.175.08:25:19.55#ibcon#enter sib2, iclass 6, count 2 2006.175.08:25:19.55#ibcon#flushed, iclass 6, count 2 2006.175.08:25:19.55#ibcon#about to write, iclass 6, count 2 2006.175.08:25:19.55#ibcon#wrote, iclass 6, count 2 2006.175.08:25:19.55#ibcon#about to read 3, iclass 6, count 2 2006.175.08:25:19.58#ibcon#read 3, iclass 6, count 2 2006.175.08:25:19.58#ibcon#about to read 4, iclass 6, count 2 2006.175.08:25:19.58#ibcon#read 4, iclass 6, count 2 2006.175.08:25:19.58#ibcon#about to read 5, iclass 6, count 2 2006.175.08:25:19.58#ibcon#read 5, iclass 6, count 2 2006.175.08:25:19.58#ibcon#about to read 6, iclass 6, count 2 2006.175.08:25:19.58#ibcon#read 6, iclass 6, count 2 2006.175.08:25:19.58#ibcon#end of sib2, iclass 6, count 2 2006.175.08:25:19.58#ibcon#*after write, iclass 6, count 2 2006.175.08:25:19.58#ibcon#*before return 0, iclass 6, count 2 2006.175.08:25:19.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:19.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:19.58#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.08:25:19.58#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:19.58#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:19.70#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:19.70#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:19.70#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:25:19.70#ibcon#first serial, iclass 6, count 0 2006.175.08:25:19.70#ibcon#enter sib2, iclass 6, count 0 2006.175.08:25:19.70#ibcon#flushed, iclass 6, count 0 2006.175.08:25:19.70#ibcon#about to write, iclass 6, count 0 2006.175.08:25:19.70#ibcon#wrote, iclass 6, count 0 2006.175.08:25:19.70#ibcon#about to read 3, iclass 6, count 0 2006.175.08:25:19.72#ibcon#read 3, iclass 6, count 0 2006.175.08:25:19.72#ibcon#about to read 4, iclass 6, count 0 2006.175.08:25:19.72#ibcon#read 4, iclass 6, count 0 2006.175.08:25:19.72#ibcon#about to read 5, iclass 6, count 0 2006.175.08:25:19.72#ibcon#read 5, iclass 6, count 0 2006.175.08:25:19.72#ibcon#about to read 6, iclass 6, count 0 2006.175.08:25:19.72#ibcon#read 6, iclass 6, count 0 2006.175.08:25:19.72#ibcon#end of sib2, iclass 6, count 0 2006.175.08:25:19.72#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:25:19.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:25:19.72#ibcon#[25=USB\r\n] 2006.175.08:25:19.72#ibcon#*before write, iclass 6, count 0 2006.175.08:25:19.72#ibcon#enter sib2, iclass 6, count 0 2006.175.08:25:19.72#ibcon#flushed, iclass 6, count 0 2006.175.08:25:19.72#ibcon#about to write, iclass 6, count 0 2006.175.08:25:19.72#ibcon#wrote, iclass 6, count 0 2006.175.08:25:19.72#ibcon#about to read 3, iclass 6, count 0 2006.175.08:25:19.75#ibcon#read 3, iclass 6, count 0 2006.175.08:25:19.75#ibcon#about to read 4, iclass 6, count 0 2006.175.08:25:19.75#ibcon#read 4, iclass 6, count 0 2006.175.08:25:19.75#ibcon#about to read 5, iclass 6, count 0 2006.175.08:25:19.75#ibcon#read 5, iclass 6, count 0 2006.175.08:25:19.75#ibcon#about to read 6, iclass 6, count 0 2006.175.08:25:19.75#ibcon#read 6, iclass 6, count 0 2006.175.08:25:19.75#ibcon#end of sib2, iclass 6, count 0 2006.175.08:25:19.75#ibcon#*after write, iclass 6, count 0 2006.175.08:25:19.75#ibcon#*before return 0, iclass 6, count 0 2006.175.08:25:19.75#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:19.75#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:19.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:25:19.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:25:19.75$vc4f8/valo=6,772.99 2006.175.08:25:19.75#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.08:25:19.75#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.08:25:19.75#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:19.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:19.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:19.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:19.75#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:25:19.75#ibcon#first serial, iclass 10, count 0 2006.175.08:25:19.75#ibcon#enter sib2, iclass 10, count 0 2006.175.08:25:19.75#ibcon#flushed, iclass 10, count 0 2006.175.08:25:19.75#ibcon#about to write, iclass 10, count 0 2006.175.08:25:19.75#ibcon#wrote, iclass 10, count 0 2006.175.08:25:19.75#ibcon#about to read 3, iclass 10, count 0 2006.175.08:25:19.77#ibcon#read 3, iclass 10, count 0 2006.175.08:25:19.77#ibcon#about to read 4, iclass 10, count 0 2006.175.08:25:19.77#ibcon#read 4, iclass 10, count 0 2006.175.08:25:19.77#ibcon#about to read 5, iclass 10, count 0 2006.175.08:25:19.77#ibcon#read 5, iclass 10, count 0 2006.175.08:25:19.77#ibcon#about to read 6, iclass 10, count 0 2006.175.08:25:19.77#ibcon#read 6, iclass 10, count 0 2006.175.08:25:19.77#ibcon#end of sib2, iclass 10, count 0 2006.175.08:25:19.77#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:25:19.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:25:19.77#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:25:19.77#ibcon#*before write, iclass 10, count 0 2006.175.08:25:19.77#ibcon#enter sib2, iclass 10, count 0 2006.175.08:25:19.77#ibcon#flushed, iclass 10, count 0 2006.175.08:25:19.77#ibcon#about to write, iclass 10, count 0 2006.175.08:25:19.77#ibcon#wrote, iclass 10, count 0 2006.175.08:25:19.77#ibcon#about to read 3, iclass 10, count 0 2006.175.08:25:19.81#ibcon#read 3, iclass 10, count 0 2006.175.08:25:19.81#ibcon#about to read 4, iclass 10, count 0 2006.175.08:25:19.81#ibcon#read 4, iclass 10, count 0 2006.175.08:25:19.81#ibcon#about to read 5, iclass 10, count 0 2006.175.08:25:19.81#ibcon#read 5, iclass 10, count 0 2006.175.08:25:19.81#ibcon#about to read 6, iclass 10, count 0 2006.175.08:25:19.81#ibcon#read 6, iclass 10, count 0 2006.175.08:25:19.81#ibcon#end of sib2, iclass 10, count 0 2006.175.08:25:19.81#ibcon#*after write, iclass 10, count 0 2006.175.08:25:19.81#ibcon#*before return 0, iclass 10, count 0 2006.175.08:25:19.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:19.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:19.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:25:19.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:25:19.81$vc4f8/va=6,6 2006.175.08:25:19.81#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.175.08:25:19.81#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.175.08:25:19.81#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:19.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:25:19.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:25:19.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:25:19.87#ibcon#enter wrdev, iclass 12, count 2 2006.175.08:25:19.87#ibcon#first serial, iclass 12, count 2 2006.175.08:25:19.87#ibcon#enter sib2, iclass 12, count 2 2006.175.08:25:19.87#ibcon#flushed, iclass 12, count 2 2006.175.08:25:19.87#ibcon#about to write, iclass 12, count 2 2006.175.08:25:19.87#ibcon#wrote, iclass 12, count 2 2006.175.08:25:19.87#ibcon#about to read 3, iclass 12, count 2 2006.175.08:25:19.89#ibcon#read 3, iclass 12, count 2 2006.175.08:25:19.89#ibcon#about to read 4, iclass 12, count 2 2006.175.08:25:19.89#ibcon#read 4, iclass 12, count 2 2006.175.08:25:19.89#ibcon#about to read 5, iclass 12, count 2 2006.175.08:25:19.89#ibcon#read 5, iclass 12, count 2 2006.175.08:25:19.89#ibcon#about to read 6, iclass 12, count 2 2006.175.08:25:19.89#ibcon#read 6, iclass 12, count 2 2006.175.08:25:19.89#ibcon#end of sib2, iclass 12, count 2 2006.175.08:25:19.89#ibcon#*mode == 0, iclass 12, count 2 2006.175.08:25:19.89#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.175.08:25:19.89#ibcon#[25=AT06-06\r\n] 2006.175.08:25:19.89#ibcon#*before write, iclass 12, count 2 2006.175.08:25:19.89#ibcon#enter sib2, iclass 12, count 2 2006.175.08:25:19.89#ibcon#flushed, iclass 12, count 2 2006.175.08:25:19.89#ibcon#about to write, iclass 12, count 2 2006.175.08:25:19.89#ibcon#wrote, iclass 12, count 2 2006.175.08:25:19.89#ibcon#about to read 3, iclass 12, count 2 2006.175.08:25:19.92#ibcon#read 3, iclass 12, count 2 2006.175.08:25:19.92#ibcon#about to read 4, iclass 12, count 2 2006.175.08:25:19.92#ibcon#read 4, iclass 12, count 2 2006.175.08:25:19.92#ibcon#about to read 5, iclass 12, count 2 2006.175.08:25:19.92#ibcon#read 5, iclass 12, count 2 2006.175.08:25:19.92#ibcon#about to read 6, iclass 12, count 2 2006.175.08:25:19.92#ibcon#read 6, iclass 12, count 2 2006.175.08:25:19.92#ibcon#end of sib2, iclass 12, count 2 2006.175.08:25:19.92#ibcon#*after write, iclass 12, count 2 2006.175.08:25:19.92#ibcon#*before return 0, iclass 12, count 2 2006.175.08:25:19.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:25:19.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.175.08:25:19.92#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.175.08:25:19.92#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:19.92#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:25:20.04#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:25:20.04#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:25:20.04#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:25:20.04#ibcon#first serial, iclass 12, count 0 2006.175.08:25:20.04#ibcon#enter sib2, iclass 12, count 0 2006.175.08:25:20.04#ibcon#flushed, iclass 12, count 0 2006.175.08:25:20.04#ibcon#about to write, iclass 12, count 0 2006.175.08:25:20.04#ibcon#wrote, iclass 12, count 0 2006.175.08:25:20.04#ibcon#about to read 3, iclass 12, count 0 2006.175.08:25:20.06#ibcon#read 3, iclass 12, count 0 2006.175.08:25:20.06#ibcon#about to read 4, iclass 12, count 0 2006.175.08:25:20.06#ibcon#read 4, iclass 12, count 0 2006.175.08:25:20.06#ibcon#about to read 5, iclass 12, count 0 2006.175.08:25:20.06#ibcon#read 5, iclass 12, count 0 2006.175.08:25:20.06#ibcon#about to read 6, iclass 12, count 0 2006.175.08:25:20.06#ibcon#read 6, iclass 12, count 0 2006.175.08:25:20.06#ibcon#end of sib2, iclass 12, count 0 2006.175.08:25:20.06#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:25:20.06#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:25:20.06#ibcon#[25=USB\r\n] 2006.175.08:25:20.06#ibcon#*before write, iclass 12, count 0 2006.175.08:25:20.06#ibcon#enter sib2, iclass 12, count 0 2006.175.08:25:20.06#ibcon#flushed, iclass 12, count 0 2006.175.08:25:20.06#ibcon#about to write, iclass 12, count 0 2006.175.08:25:20.06#ibcon#wrote, iclass 12, count 0 2006.175.08:25:20.06#ibcon#about to read 3, iclass 12, count 0 2006.175.08:25:20.09#ibcon#read 3, iclass 12, count 0 2006.175.08:25:20.09#ibcon#about to read 4, iclass 12, count 0 2006.175.08:25:20.09#ibcon#read 4, iclass 12, count 0 2006.175.08:25:20.09#ibcon#about to read 5, iclass 12, count 0 2006.175.08:25:20.09#ibcon#read 5, iclass 12, count 0 2006.175.08:25:20.09#ibcon#about to read 6, iclass 12, count 0 2006.175.08:25:20.09#ibcon#read 6, iclass 12, count 0 2006.175.08:25:20.09#ibcon#end of sib2, iclass 12, count 0 2006.175.08:25:20.09#ibcon#*after write, iclass 12, count 0 2006.175.08:25:20.09#ibcon#*before return 0, iclass 12, count 0 2006.175.08:25:20.09#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:25:20.09#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.175.08:25:20.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:25:20.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:25:20.09$vc4f8/valo=7,832.99 2006.175.08:25:20.09#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.175.08:25:20.09#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.175.08:25:20.09#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:20.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:25:20.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:25:20.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:25:20.09#ibcon#enter wrdev, iclass 14, count 0 2006.175.08:25:20.09#ibcon#first serial, iclass 14, count 0 2006.175.08:25:20.09#ibcon#enter sib2, iclass 14, count 0 2006.175.08:25:20.09#ibcon#flushed, iclass 14, count 0 2006.175.08:25:20.09#ibcon#about to write, iclass 14, count 0 2006.175.08:25:20.09#ibcon#wrote, iclass 14, count 0 2006.175.08:25:20.09#ibcon#about to read 3, iclass 14, count 0 2006.175.08:25:20.11#ibcon#read 3, iclass 14, count 0 2006.175.08:25:20.11#ibcon#about to read 4, iclass 14, count 0 2006.175.08:25:20.11#ibcon#read 4, iclass 14, count 0 2006.175.08:25:20.11#ibcon#about to read 5, iclass 14, count 0 2006.175.08:25:20.11#ibcon#read 5, iclass 14, count 0 2006.175.08:25:20.11#ibcon#about to read 6, iclass 14, count 0 2006.175.08:25:20.11#ibcon#read 6, iclass 14, count 0 2006.175.08:25:20.11#ibcon#end of sib2, iclass 14, count 0 2006.175.08:25:20.11#ibcon#*mode == 0, iclass 14, count 0 2006.175.08:25:20.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.175.08:25:20.11#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:25:20.11#ibcon#*before write, iclass 14, count 0 2006.175.08:25:20.11#ibcon#enter sib2, iclass 14, count 0 2006.175.08:25:20.11#ibcon#flushed, iclass 14, count 0 2006.175.08:25:20.11#ibcon#about to write, iclass 14, count 0 2006.175.08:25:20.11#ibcon#wrote, iclass 14, count 0 2006.175.08:25:20.11#ibcon#about to read 3, iclass 14, count 0 2006.175.08:25:20.15#ibcon#read 3, iclass 14, count 0 2006.175.08:25:20.15#ibcon#about to read 4, iclass 14, count 0 2006.175.08:25:20.15#ibcon#read 4, iclass 14, count 0 2006.175.08:25:20.15#ibcon#about to read 5, iclass 14, count 0 2006.175.08:25:20.15#ibcon#read 5, iclass 14, count 0 2006.175.08:25:20.15#ibcon#about to read 6, iclass 14, count 0 2006.175.08:25:20.15#ibcon#read 6, iclass 14, count 0 2006.175.08:25:20.15#ibcon#end of sib2, iclass 14, count 0 2006.175.08:25:20.15#ibcon#*after write, iclass 14, count 0 2006.175.08:25:20.15#ibcon#*before return 0, iclass 14, count 0 2006.175.08:25:20.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:25:20.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.175.08:25:20.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.175.08:25:20.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.175.08:25:20.15$vc4f8/va=7,6 2006.175.08:25:20.15#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.175.08:25:20.15#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.175.08:25:20.15#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:20.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:25:20.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:25:20.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:25:20.21#ibcon#enter wrdev, iclass 16, count 2 2006.175.08:25:20.21#ibcon#first serial, iclass 16, count 2 2006.175.08:25:20.21#ibcon#enter sib2, iclass 16, count 2 2006.175.08:25:20.21#ibcon#flushed, iclass 16, count 2 2006.175.08:25:20.21#ibcon#about to write, iclass 16, count 2 2006.175.08:25:20.21#ibcon#wrote, iclass 16, count 2 2006.175.08:25:20.21#ibcon#about to read 3, iclass 16, count 2 2006.175.08:25:20.23#ibcon#read 3, iclass 16, count 2 2006.175.08:25:20.23#ibcon#about to read 4, iclass 16, count 2 2006.175.08:25:20.23#ibcon#read 4, iclass 16, count 2 2006.175.08:25:20.23#ibcon#about to read 5, iclass 16, count 2 2006.175.08:25:20.23#ibcon#read 5, iclass 16, count 2 2006.175.08:25:20.23#ibcon#about to read 6, iclass 16, count 2 2006.175.08:25:20.23#ibcon#read 6, iclass 16, count 2 2006.175.08:25:20.23#ibcon#end of sib2, iclass 16, count 2 2006.175.08:25:20.23#ibcon#*mode == 0, iclass 16, count 2 2006.175.08:25:20.23#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.175.08:25:20.23#ibcon#[25=AT07-06\r\n] 2006.175.08:25:20.23#ibcon#*before write, iclass 16, count 2 2006.175.08:25:20.23#ibcon#enter sib2, iclass 16, count 2 2006.175.08:25:20.23#ibcon#flushed, iclass 16, count 2 2006.175.08:25:20.23#ibcon#about to write, iclass 16, count 2 2006.175.08:25:20.23#ibcon#wrote, iclass 16, count 2 2006.175.08:25:20.23#ibcon#about to read 3, iclass 16, count 2 2006.175.08:25:20.26#ibcon#read 3, iclass 16, count 2 2006.175.08:25:20.26#ibcon#about to read 4, iclass 16, count 2 2006.175.08:25:20.26#ibcon#read 4, iclass 16, count 2 2006.175.08:25:20.26#ibcon#about to read 5, iclass 16, count 2 2006.175.08:25:20.26#ibcon#read 5, iclass 16, count 2 2006.175.08:25:20.26#ibcon#about to read 6, iclass 16, count 2 2006.175.08:25:20.26#ibcon#read 6, iclass 16, count 2 2006.175.08:25:20.26#ibcon#end of sib2, iclass 16, count 2 2006.175.08:25:20.26#ibcon#*after write, iclass 16, count 2 2006.175.08:25:20.26#ibcon#*before return 0, iclass 16, count 2 2006.175.08:25:20.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:25:20.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.175.08:25:20.26#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.175.08:25:20.26#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:20.26#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:25:20.38#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:25:20.38#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:25:20.38#ibcon#enter wrdev, iclass 16, count 0 2006.175.08:25:20.38#ibcon#first serial, iclass 16, count 0 2006.175.08:25:20.38#ibcon#enter sib2, iclass 16, count 0 2006.175.08:25:20.38#ibcon#flushed, iclass 16, count 0 2006.175.08:25:20.38#ibcon#about to write, iclass 16, count 0 2006.175.08:25:20.38#ibcon#wrote, iclass 16, count 0 2006.175.08:25:20.38#ibcon#about to read 3, iclass 16, count 0 2006.175.08:25:20.40#ibcon#read 3, iclass 16, count 0 2006.175.08:25:20.40#ibcon#about to read 4, iclass 16, count 0 2006.175.08:25:20.40#ibcon#read 4, iclass 16, count 0 2006.175.08:25:20.40#ibcon#about to read 5, iclass 16, count 0 2006.175.08:25:20.40#ibcon#read 5, iclass 16, count 0 2006.175.08:25:20.40#ibcon#about to read 6, iclass 16, count 0 2006.175.08:25:20.40#ibcon#read 6, iclass 16, count 0 2006.175.08:25:20.40#ibcon#end of sib2, iclass 16, count 0 2006.175.08:25:20.40#ibcon#*mode == 0, iclass 16, count 0 2006.175.08:25:20.40#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.175.08:25:20.40#ibcon#[25=USB\r\n] 2006.175.08:25:20.40#ibcon#*before write, iclass 16, count 0 2006.175.08:25:20.40#ibcon#enter sib2, iclass 16, count 0 2006.175.08:25:20.40#ibcon#flushed, iclass 16, count 0 2006.175.08:25:20.40#ibcon#about to write, iclass 16, count 0 2006.175.08:25:20.40#ibcon#wrote, iclass 16, count 0 2006.175.08:25:20.40#ibcon#about to read 3, iclass 16, count 0 2006.175.08:25:20.43#ibcon#read 3, iclass 16, count 0 2006.175.08:25:20.43#ibcon#about to read 4, iclass 16, count 0 2006.175.08:25:20.43#ibcon#read 4, iclass 16, count 0 2006.175.08:25:20.43#ibcon#about to read 5, iclass 16, count 0 2006.175.08:25:20.43#ibcon#read 5, iclass 16, count 0 2006.175.08:25:20.43#ibcon#about to read 6, iclass 16, count 0 2006.175.08:25:20.43#ibcon#read 6, iclass 16, count 0 2006.175.08:25:20.43#ibcon#end of sib2, iclass 16, count 0 2006.175.08:25:20.43#ibcon#*after write, iclass 16, count 0 2006.175.08:25:20.43#ibcon#*before return 0, iclass 16, count 0 2006.175.08:25:20.43#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:25:20.43#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.175.08:25:20.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.175.08:25:20.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.175.08:25:20.43$vc4f8/valo=8,852.99 2006.175.08:25:20.43#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.175.08:25:20.43#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.175.08:25:20.43#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:20.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:25:20.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:25:20.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:25:20.43#ibcon#enter wrdev, iclass 18, count 0 2006.175.08:25:20.43#ibcon#first serial, iclass 18, count 0 2006.175.08:25:20.43#ibcon#enter sib2, iclass 18, count 0 2006.175.08:25:20.43#ibcon#flushed, iclass 18, count 0 2006.175.08:25:20.43#ibcon#about to write, iclass 18, count 0 2006.175.08:25:20.43#ibcon#wrote, iclass 18, count 0 2006.175.08:25:20.43#ibcon#about to read 3, iclass 18, count 0 2006.175.08:25:20.45#ibcon#read 3, iclass 18, count 0 2006.175.08:25:20.45#ibcon#about to read 4, iclass 18, count 0 2006.175.08:25:20.45#ibcon#read 4, iclass 18, count 0 2006.175.08:25:20.45#ibcon#about to read 5, iclass 18, count 0 2006.175.08:25:20.45#ibcon#read 5, iclass 18, count 0 2006.175.08:25:20.45#ibcon#about to read 6, iclass 18, count 0 2006.175.08:25:20.45#ibcon#read 6, iclass 18, count 0 2006.175.08:25:20.45#ibcon#end of sib2, iclass 18, count 0 2006.175.08:25:20.45#ibcon#*mode == 0, iclass 18, count 0 2006.175.08:25:20.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.175.08:25:20.45#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:25:20.45#ibcon#*before write, iclass 18, count 0 2006.175.08:25:20.45#ibcon#enter sib2, iclass 18, count 0 2006.175.08:25:20.45#ibcon#flushed, iclass 18, count 0 2006.175.08:25:20.45#ibcon#about to write, iclass 18, count 0 2006.175.08:25:20.45#ibcon#wrote, iclass 18, count 0 2006.175.08:25:20.45#ibcon#about to read 3, iclass 18, count 0 2006.175.08:25:20.49#ibcon#read 3, iclass 18, count 0 2006.175.08:25:20.49#ibcon#about to read 4, iclass 18, count 0 2006.175.08:25:20.49#ibcon#read 4, iclass 18, count 0 2006.175.08:25:20.49#ibcon#about to read 5, iclass 18, count 0 2006.175.08:25:20.49#ibcon#read 5, iclass 18, count 0 2006.175.08:25:20.49#ibcon#about to read 6, iclass 18, count 0 2006.175.08:25:20.49#ibcon#read 6, iclass 18, count 0 2006.175.08:25:20.49#ibcon#end of sib2, iclass 18, count 0 2006.175.08:25:20.49#ibcon#*after write, iclass 18, count 0 2006.175.08:25:20.49#ibcon#*before return 0, iclass 18, count 0 2006.175.08:25:20.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:25:20.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.175.08:25:20.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.175.08:25:20.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.175.08:25:20.49$vc4f8/va=8,6 2006.175.08:25:20.49#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.175.08:25:20.49#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.175.08:25:20.49#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:20.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:25:20.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:25:20.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:25:20.55#ibcon#enter wrdev, iclass 20, count 2 2006.175.08:25:20.55#ibcon#first serial, iclass 20, count 2 2006.175.08:25:20.55#ibcon#enter sib2, iclass 20, count 2 2006.175.08:25:20.55#ibcon#flushed, iclass 20, count 2 2006.175.08:25:20.55#ibcon#about to write, iclass 20, count 2 2006.175.08:25:20.55#ibcon#wrote, iclass 20, count 2 2006.175.08:25:20.55#ibcon#about to read 3, iclass 20, count 2 2006.175.08:25:20.57#ibcon#read 3, iclass 20, count 2 2006.175.08:25:20.57#ibcon#about to read 4, iclass 20, count 2 2006.175.08:25:20.57#ibcon#read 4, iclass 20, count 2 2006.175.08:25:20.57#ibcon#about to read 5, iclass 20, count 2 2006.175.08:25:20.57#ibcon#read 5, iclass 20, count 2 2006.175.08:25:20.57#ibcon#about to read 6, iclass 20, count 2 2006.175.08:25:20.57#ibcon#read 6, iclass 20, count 2 2006.175.08:25:20.57#ibcon#end of sib2, iclass 20, count 2 2006.175.08:25:20.57#ibcon#*mode == 0, iclass 20, count 2 2006.175.08:25:20.57#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.175.08:25:20.57#ibcon#[25=AT08-06\r\n] 2006.175.08:25:20.57#ibcon#*before write, iclass 20, count 2 2006.175.08:25:20.57#ibcon#enter sib2, iclass 20, count 2 2006.175.08:25:20.57#ibcon#flushed, iclass 20, count 2 2006.175.08:25:20.57#ibcon#about to write, iclass 20, count 2 2006.175.08:25:20.57#ibcon#wrote, iclass 20, count 2 2006.175.08:25:20.57#ibcon#about to read 3, iclass 20, count 2 2006.175.08:25:20.60#ibcon#read 3, iclass 20, count 2 2006.175.08:25:20.60#ibcon#about to read 4, iclass 20, count 2 2006.175.08:25:20.60#ibcon#read 4, iclass 20, count 2 2006.175.08:25:20.60#ibcon#about to read 5, iclass 20, count 2 2006.175.08:25:20.60#ibcon#read 5, iclass 20, count 2 2006.175.08:25:20.60#ibcon#about to read 6, iclass 20, count 2 2006.175.08:25:20.60#ibcon#read 6, iclass 20, count 2 2006.175.08:25:20.60#ibcon#end of sib2, iclass 20, count 2 2006.175.08:25:20.60#ibcon#*after write, iclass 20, count 2 2006.175.08:25:20.60#ibcon#*before return 0, iclass 20, count 2 2006.175.08:25:20.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:25:20.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.175.08:25:20.60#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.175.08:25:20.60#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:20.60#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:25:20.72#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:25:20.72#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:25:20.72#ibcon#enter wrdev, iclass 20, count 0 2006.175.08:25:20.72#ibcon#first serial, iclass 20, count 0 2006.175.08:25:20.72#ibcon#enter sib2, iclass 20, count 0 2006.175.08:25:20.72#ibcon#flushed, iclass 20, count 0 2006.175.08:25:20.72#ibcon#about to write, iclass 20, count 0 2006.175.08:25:20.72#ibcon#wrote, iclass 20, count 0 2006.175.08:25:20.72#ibcon#about to read 3, iclass 20, count 0 2006.175.08:25:20.74#ibcon#read 3, iclass 20, count 0 2006.175.08:25:20.74#ibcon#about to read 4, iclass 20, count 0 2006.175.08:25:20.74#ibcon#read 4, iclass 20, count 0 2006.175.08:25:20.74#ibcon#about to read 5, iclass 20, count 0 2006.175.08:25:20.74#ibcon#read 5, iclass 20, count 0 2006.175.08:25:20.74#ibcon#about to read 6, iclass 20, count 0 2006.175.08:25:20.74#ibcon#read 6, iclass 20, count 0 2006.175.08:25:20.74#ibcon#end of sib2, iclass 20, count 0 2006.175.08:25:20.74#ibcon#*mode == 0, iclass 20, count 0 2006.175.08:25:20.74#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.175.08:25:20.74#ibcon#[25=USB\r\n] 2006.175.08:25:20.74#ibcon#*before write, iclass 20, count 0 2006.175.08:25:20.74#ibcon#enter sib2, iclass 20, count 0 2006.175.08:25:20.74#ibcon#flushed, iclass 20, count 0 2006.175.08:25:20.74#ibcon#about to write, iclass 20, count 0 2006.175.08:25:20.74#ibcon#wrote, iclass 20, count 0 2006.175.08:25:20.74#ibcon#about to read 3, iclass 20, count 0 2006.175.08:25:20.77#ibcon#read 3, iclass 20, count 0 2006.175.08:25:20.77#ibcon#about to read 4, iclass 20, count 0 2006.175.08:25:20.77#ibcon#read 4, iclass 20, count 0 2006.175.08:25:20.77#ibcon#about to read 5, iclass 20, count 0 2006.175.08:25:20.77#ibcon#read 5, iclass 20, count 0 2006.175.08:25:20.77#ibcon#about to read 6, iclass 20, count 0 2006.175.08:25:20.77#ibcon#read 6, iclass 20, count 0 2006.175.08:25:20.77#ibcon#end of sib2, iclass 20, count 0 2006.175.08:25:20.77#ibcon#*after write, iclass 20, count 0 2006.175.08:25:20.77#ibcon#*before return 0, iclass 20, count 0 2006.175.08:25:20.77#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:25:20.77#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.175.08:25:20.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.175.08:25:20.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.175.08:25:20.77$vc4f8/vblo=1,632.99 2006.175.08:25:20.77#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.175.08:25:20.77#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.175.08:25:20.77#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:20.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:20.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:20.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:20.77#ibcon#enter wrdev, iclass 22, count 0 2006.175.08:25:20.77#ibcon#first serial, iclass 22, count 0 2006.175.08:25:20.77#ibcon#enter sib2, iclass 22, count 0 2006.175.08:25:20.77#ibcon#flushed, iclass 22, count 0 2006.175.08:25:20.77#ibcon#about to write, iclass 22, count 0 2006.175.08:25:20.77#ibcon#wrote, iclass 22, count 0 2006.175.08:25:20.77#ibcon#about to read 3, iclass 22, count 0 2006.175.08:25:20.79#ibcon#read 3, iclass 22, count 0 2006.175.08:25:20.79#ibcon#about to read 4, iclass 22, count 0 2006.175.08:25:20.79#ibcon#read 4, iclass 22, count 0 2006.175.08:25:20.79#ibcon#about to read 5, iclass 22, count 0 2006.175.08:25:20.79#ibcon#read 5, iclass 22, count 0 2006.175.08:25:20.79#ibcon#about to read 6, iclass 22, count 0 2006.175.08:25:20.79#ibcon#read 6, iclass 22, count 0 2006.175.08:25:20.79#ibcon#end of sib2, iclass 22, count 0 2006.175.08:25:20.79#ibcon#*mode == 0, iclass 22, count 0 2006.175.08:25:20.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.175.08:25:20.79#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:25:20.79#ibcon#*before write, iclass 22, count 0 2006.175.08:25:20.79#ibcon#enter sib2, iclass 22, count 0 2006.175.08:25:20.79#ibcon#flushed, iclass 22, count 0 2006.175.08:25:20.79#ibcon#about to write, iclass 22, count 0 2006.175.08:25:20.79#ibcon#wrote, iclass 22, count 0 2006.175.08:25:20.79#ibcon#about to read 3, iclass 22, count 0 2006.175.08:25:20.83#ibcon#read 3, iclass 22, count 0 2006.175.08:25:20.83#ibcon#about to read 4, iclass 22, count 0 2006.175.08:25:20.83#ibcon#read 4, iclass 22, count 0 2006.175.08:25:20.83#ibcon#about to read 5, iclass 22, count 0 2006.175.08:25:20.83#ibcon#read 5, iclass 22, count 0 2006.175.08:25:20.83#ibcon#about to read 6, iclass 22, count 0 2006.175.08:25:20.83#ibcon#read 6, iclass 22, count 0 2006.175.08:25:20.83#ibcon#end of sib2, iclass 22, count 0 2006.175.08:25:20.83#ibcon#*after write, iclass 22, count 0 2006.175.08:25:20.83#ibcon#*before return 0, iclass 22, count 0 2006.175.08:25:20.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:20.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.175.08:25:20.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.175.08:25:20.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.175.08:25:20.83$vc4f8/vb=1,4 2006.175.08:25:20.83#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.175.08:25:20.83#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.175.08:25:20.83#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:20.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:25:20.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:25:20.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:25:20.83#ibcon#enter wrdev, iclass 24, count 2 2006.175.08:25:20.83#ibcon#first serial, iclass 24, count 2 2006.175.08:25:20.83#ibcon#enter sib2, iclass 24, count 2 2006.175.08:25:20.83#ibcon#flushed, iclass 24, count 2 2006.175.08:25:20.83#ibcon#about to write, iclass 24, count 2 2006.175.08:25:20.83#ibcon#wrote, iclass 24, count 2 2006.175.08:25:20.83#ibcon#about to read 3, iclass 24, count 2 2006.175.08:25:20.85#ibcon#read 3, iclass 24, count 2 2006.175.08:25:20.85#ibcon#about to read 4, iclass 24, count 2 2006.175.08:25:20.85#ibcon#read 4, iclass 24, count 2 2006.175.08:25:20.85#ibcon#about to read 5, iclass 24, count 2 2006.175.08:25:20.85#ibcon#read 5, iclass 24, count 2 2006.175.08:25:20.85#ibcon#about to read 6, iclass 24, count 2 2006.175.08:25:20.85#ibcon#read 6, iclass 24, count 2 2006.175.08:25:20.85#ibcon#end of sib2, iclass 24, count 2 2006.175.08:25:20.85#ibcon#*mode == 0, iclass 24, count 2 2006.175.08:25:20.85#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.175.08:25:20.85#ibcon#[27=AT01-04\r\n] 2006.175.08:25:20.85#ibcon#*before write, iclass 24, count 2 2006.175.08:25:20.85#ibcon#enter sib2, iclass 24, count 2 2006.175.08:25:20.85#ibcon#flushed, iclass 24, count 2 2006.175.08:25:20.85#ibcon#about to write, iclass 24, count 2 2006.175.08:25:20.85#ibcon#wrote, iclass 24, count 2 2006.175.08:25:20.85#ibcon#about to read 3, iclass 24, count 2 2006.175.08:25:20.88#ibcon#read 3, iclass 24, count 2 2006.175.08:25:20.88#ibcon#about to read 4, iclass 24, count 2 2006.175.08:25:20.88#ibcon#read 4, iclass 24, count 2 2006.175.08:25:20.88#ibcon#about to read 5, iclass 24, count 2 2006.175.08:25:20.88#ibcon#read 5, iclass 24, count 2 2006.175.08:25:20.88#ibcon#about to read 6, iclass 24, count 2 2006.175.08:25:20.88#ibcon#read 6, iclass 24, count 2 2006.175.08:25:20.88#ibcon#end of sib2, iclass 24, count 2 2006.175.08:25:20.88#ibcon#*after write, iclass 24, count 2 2006.175.08:25:20.88#ibcon#*before return 0, iclass 24, count 2 2006.175.08:25:20.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:25:20.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.175.08:25:20.88#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.175.08:25:20.88#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:20.88#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:25:21.00#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:25:21.00#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:25:21.00#ibcon#enter wrdev, iclass 24, count 0 2006.175.08:25:21.00#ibcon#first serial, iclass 24, count 0 2006.175.08:25:21.00#ibcon#enter sib2, iclass 24, count 0 2006.175.08:25:21.00#ibcon#flushed, iclass 24, count 0 2006.175.08:25:21.00#ibcon#about to write, iclass 24, count 0 2006.175.08:25:21.00#ibcon#wrote, iclass 24, count 0 2006.175.08:25:21.00#ibcon#about to read 3, iclass 24, count 0 2006.175.08:25:21.02#ibcon#read 3, iclass 24, count 0 2006.175.08:25:21.02#ibcon#about to read 4, iclass 24, count 0 2006.175.08:25:21.02#ibcon#read 4, iclass 24, count 0 2006.175.08:25:21.02#ibcon#about to read 5, iclass 24, count 0 2006.175.08:25:21.02#ibcon#read 5, iclass 24, count 0 2006.175.08:25:21.02#ibcon#about to read 6, iclass 24, count 0 2006.175.08:25:21.02#ibcon#read 6, iclass 24, count 0 2006.175.08:25:21.02#ibcon#end of sib2, iclass 24, count 0 2006.175.08:25:21.02#ibcon#*mode == 0, iclass 24, count 0 2006.175.08:25:21.02#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.175.08:25:21.02#ibcon#[27=USB\r\n] 2006.175.08:25:21.02#ibcon#*before write, iclass 24, count 0 2006.175.08:25:21.02#ibcon#enter sib2, iclass 24, count 0 2006.175.08:25:21.02#ibcon#flushed, iclass 24, count 0 2006.175.08:25:21.02#ibcon#about to write, iclass 24, count 0 2006.175.08:25:21.02#ibcon#wrote, iclass 24, count 0 2006.175.08:25:21.02#ibcon#about to read 3, iclass 24, count 0 2006.175.08:25:21.05#ibcon#read 3, iclass 24, count 0 2006.175.08:25:21.05#ibcon#about to read 4, iclass 24, count 0 2006.175.08:25:21.05#ibcon#read 4, iclass 24, count 0 2006.175.08:25:21.05#ibcon#about to read 5, iclass 24, count 0 2006.175.08:25:21.05#ibcon#read 5, iclass 24, count 0 2006.175.08:25:21.05#ibcon#about to read 6, iclass 24, count 0 2006.175.08:25:21.05#ibcon#read 6, iclass 24, count 0 2006.175.08:25:21.05#ibcon#end of sib2, iclass 24, count 0 2006.175.08:25:21.05#ibcon#*after write, iclass 24, count 0 2006.175.08:25:21.05#ibcon#*before return 0, iclass 24, count 0 2006.175.08:25:21.05#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:25:21.05#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.175.08:25:21.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.175.08:25:21.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.175.08:25:21.05$vc4f8/vblo=2,640.99 2006.175.08:25:21.05#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.175.08:25:21.05#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.175.08:25:21.05#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:21.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:25:21.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:25:21.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:25:21.05#ibcon#enter wrdev, iclass 26, count 0 2006.175.08:25:21.05#ibcon#first serial, iclass 26, count 0 2006.175.08:25:21.05#ibcon#enter sib2, iclass 26, count 0 2006.175.08:25:21.05#ibcon#flushed, iclass 26, count 0 2006.175.08:25:21.05#ibcon#about to write, iclass 26, count 0 2006.175.08:25:21.05#ibcon#wrote, iclass 26, count 0 2006.175.08:25:21.05#ibcon#about to read 3, iclass 26, count 0 2006.175.08:25:21.07#ibcon#read 3, iclass 26, count 0 2006.175.08:25:21.07#ibcon#about to read 4, iclass 26, count 0 2006.175.08:25:21.07#ibcon#read 4, iclass 26, count 0 2006.175.08:25:21.07#ibcon#about to read 5, iclass 26, count 0 2006.175.08:25:21.07#ibcon#read 5, iclass 26, count 0 2006.175.08:25:21.07#ibcon#about to read 6, iclass 26, count 0 2006.175.08:25:21.07#ibcon#read 6, iclass 26, count 0 2006.175.08:25:21.07#ibcon#end of sib2, iclass 26, count 0 2006.175.08:25:21.07#ibcon#*mode == 0, iclass 26, count 0 2006.175.08:25:21.07#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.175.08:25:21.07#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:25:21.07#ibcon#*before write, iclass 26, count 0 2006.175.08:25:21.07#ibcon#enter sib2, iclass 26, count 0 2006.175.08:25:21.07#ibcon#flushed, iclass 26, count 0 2006.175.08:25:21.07#ibcon#about to write, iclass 26, count 0 2006.175.08:25:21.07#ibcon#wrote, iclass 26, count 0 2006.175.08:25:21.07#ibcon#about to read 3, iclass 26, count 0 2006.175.08:25:21.11#ibcon#read 3, iclass 26, count 0 2006.175.08:25:21.11#ibcon#about to read 4, iclass 26, count 0 2006.175.08:25:21.11#ibcon#read 4, iclass 26, count 0 2006.175.08:25:21.11#ibcon#about to read 5, iclass 26, count 0 2006.175.08:25:21.11#ibcon#read 5, iclass 26, count 0 2006.175.08:25:21.11#ibcon#about to read 6, iclass 26, count 0 2006.175.08:25:21.11#ibcon#read 6, iclass 26, count 0 2006.175.08:25:21.11#ibcon#end of sib2, iclass 26, count 0 2006.175.08:25:21.11#ibcon#*after write, iclass 26, count 0 2006.175.08:25:21.11#ibcon#*before return 0, iclass 26, count 0 2006.175.08:25:21.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:25:21.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.175.08:25:21.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.175.08:25:21.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.175.08:25:21.11$vc4f8/vb=2,4 2006.175.08:25:21.11#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.175.08:25:21.11#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.175.08:25:21.11#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:21.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:25:21.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:25:21.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:25:21.17#ibcon#enter wrdev, iclass 28, count 2 2006.175.08:25:21.17#ibcon#first serial, iclass 28, count 2 2006.175.08:25:21.17#ibcon#enter sib2, iclass 28, count 2 2006.175.08:25:21.17#ibcon#flushed, iclass 28, count 2 2006.175.08:25:21.17#ibcon#about to write, iclass 28, count 2 2006.175.08:25:21.17#ibcon#wrote, iclass 28, count 2 2006.175.08:25:21.17#ibcon#about to read 3, iclass 28, count 2 2006.175.08:25:21.19#ibcon#read 3, iclass 28, count 2 2006.175.08:25:21.19#ibcon#about to read 4, iclass 28, count 2 2006.175.08:25:21.19#ibcon#read 4, iclass 28, count 2 2006.175.08:25:21.19#ibcon#about to read 5, iclass 28, count 2 2006.175.08:25:21.19#ibcon#read 5, iclass 28, count 2 2006.175.08:25:21.19#ibcon#about to read 6, iclass 28, count 2 2006.175.08:25:21.19#ibcon#read 6, iclass 28, count 2 2006.175.08:25:21.19#ibcon#end of sib2, iclass 28, count 2 2006.175.08:25:21.19#ibcon#*mode == 0, iclass 28, count 2 2006.175.08:25:21.19#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.175.08:25:21.19#ibcon#[27=AT02-04\r\n] 2006.175.08:25:21.19#ibcon#*before write, iclass 28, count 2 2006.175.08:25:21.19#ibcon#enter sib2, iclass 28, count 2 2006.175.08:25:21.19#ibcon#flushed, iclass 28, count 2 2006.175.08:25:21.19#ibcon#about to write, iclass 28, count 2 2006.175.08:25:21.19#ibcon#wrote, iclass 28, count 2 2006.175.08:25:21.19#ibcon#about to read 3, iclass 28, count 2 2006.175.08:25:21.22#ibcon#read 3, iclass 28, count 2 2006.175.08:25:21.22#ibcon#about to read 4, iclass 28, count 2 2006.175.08:25:21.22#ibcon#read 4, iclass 28, count 2 2006.175.08:25:21.22#ibcon#about to read 5, iclass 28, count 2 2006.175.08:25:21.22#ibcon#read 5, iclass 28, count 2 2006.175.08:25:21.22#ibcon#about to read 6, iclass 28, count 2 2006.175.08:25:21.22#ibcon#read 6, iclass 28, count 2 2006.175.08:25:21.22#ibcon#end of sib2, iclass 28, count 2 2006.175.08:25:21.22#ibcon#*after write, iclass 28, count 2 2006.175.08:25:21.22#ibcon#*before return 0, iclass 28, count 2 2006.175.08:25:21.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:25:21.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.175.08:25:21.22#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.175.08:25:21.22#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:21.22#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:25:21.34#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:25:21.34#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:25:21.34#ibcon#enter wrdev, iclass 28, count 0 2006.175.08:25:21.34#ibcon#first serial, iclass 28, count 0 2006.175.08:25:21.34#ibcon#enter sib2, iclass 28, count 0 2006.175.08:25:21.34#ibcon#flushed, iclass 28, count 0 2006.175.08:25:21.34#ibcon#about to write, iclass 28, count 0 2006.175.08:25:21.34#ibcon#wrote, iclass 28, count 0 2006.175.08:25:21.34#ibcon#about to read 3, iclass 28, count 0 2006.175.08:25:21.36#ibcon#read 3, iclass 28, count 0 2006.175.08:25:21.36#ibcon#about to read 4, iclass 28, count 0 2006.175.08:25:21.36#ibcon#read 4, iclass 28, count 0 2006.175.08:25:21.36#ibcon#about to read 5, iclass 28, count 0 2006.175.08:25:21.36#ibcon#read 5, iclass 28, count 0 2006.175.08:25:21.36#ibcon#about to read 6, iclass 28, count 0 2006.175.08:25:21.36#ibcon#read 6, iclass 28, count 0 2006.175.08:25:21.36#ibcon#end of sib2, iclass 28, count 0 2006.175.08:25:21.36#ibcon#*mode == 0, iclass 28, count 0 2006.175.08:25:21.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.175.08:25:21.36#ibcon#[27=USB\r\n] 2006.175.08:25:21.36#ibcon#*before write, iclass 28, count 0 2006.175.08:25:21.36#ibcon#enter sib2, iclass 28, count 0 2006.175.08:25:21.36#ibcon#flushed, iclass 28, count 0 2006.175.08:25:21.36#ibcon#about to write, iclass 28, count 0 2006.175.08:25:21.36#ibcon#wrote, iclass 28, count 0 2006.175.08:25:21.36#ibcon#about to read 3, iclass 28, count 0 2006.175.08:25:21.39#ibcon#read 3, iclass 28, count 0 2006.175.08:25:21.39#ibcon#about to read 4, iclass 28, count 0 2006.175.08:25:21.39#ibcon#read 4, iclass 28, count 0 2006.175.08:25:21.39#ibcon#about to read 5, iclass 28, count 0 2006.175.08:25:21.39#ibcon#read 5, iclass 28, count 0 2006.175.08:25:21.39#ibcon#about to read 6, iclass 28, count 0 2006.175.08:25:21.39#ibcon#read 6, iclass 28, count 0 2006.175.08:25:21.39#ibcon#end of sib2, iclass 28, count 0 2006.175.08:25:21.39#ibcon#*after write, iclass 28, count 0 2006.175.08:25:21.39#ibcon#*before return 0, iclass 28, count 0 2006.175.08:25:21.39#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:25:21.39#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.175.08:25:21.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.175.08:25:21.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.175.08:25:21.39$vc4f8/vblo=3,656.99 2006.175.08:25:21.39#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.175.08:25:21.39#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.175.08:25:21.39#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:21.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:21.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:21.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:21.39#ibcon#enter wrdev, iclass 30, count 0 2006.175.08:25:21.39#ibcon#first serial, iclass 30, count 0 2006.175.08:25:21.39#ibcon#enter sib2, iclass 30, count 0 2006.175.08:25:21.39#ibcon#flushed, iclass 30, count 0 2006.175.08:25:21.39#ibcon#about to write, iclass 30, count 0 2006.175.08:25:21.39#ibcon#wrote, iclass 30, count 0 2006.175.08:25:21.39#ibcon#about to read 3, iclass 30, count 0 2006.175.08:25:21.41#ibcon#read 3, iclass 30, count 0 2006.175.08:25:21.41#ibcon#about to read 4, iclass 30, count 0 2006.175.08:25:21.41#ibcon#read 4, iclass 30, count 0 2006.175.08:25:21.41#ibcon#about to read 5, iclass 30, count 0 2006.175.08:25:21.41#ibcon#read 5, iclass 30, count 0 2006.175.08:25:21.41#ibcon#about to read 6, iclass 30, count 0 2006.175.08:25:21.41#ibcon#read 6, iclass 30, count 0 2006.175.08:25:21.41#ibcon#end of sib2, iclass 30, count 0 2006.175.08:25:21.41#ibcon#*mode == 0, iclass 30, count 0 2006.175.08:25:21.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.175.08:25:21.41#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:25:21.41#ibcon#*before write, iclass 30, count 0 2006.175.08:25:21.41#ibcon#enter sib2, iclass 30, count 0 2006.175.08:25:21.41#ibcon#flushed, iclass 30, count 0 2006.175.08:25:21.41#ibcon#about to write, iclass 30, count 0 2006.175.08:25:21.41#ibcon#wrote, iclass 30, count 0 2006.175.08:25:21.41#ibcon#about to read 3, iclass 30, count 0 2006.175.08:25:21.45#ibcon#read 3, iclass 30, count 0 2006.175.08:25:21.45#ibcon#about to read 4, iclass 30, count 0 2006.175.08:25:21.45#ibcon#read 4, iclass 30, count 0 2006.175.08:25:21.45#ibcon#about to read 5, iclass 30, count 0 2006.175.08:25:21.45#ibcon#read 5, iclass 30, count 0 2006.175.08:25:21.45#ibcon#about to read 6, iclass 30, count 0 2006.175.08:25:21.45#ibcon#read 6, iclass 30, count 0 2006.175.08:25:21.45#ibcon#end of sib2, iclass 30, count 0 2006.175.08:25:21.45#ibcon#*after write, iclass 30, count 0 2006.175.08:25:21.45#ibcon#*before return 0, iclass 30, count 0 2006.175.08:25:21.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:21.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.175.08:25:21.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.175.08:25:21.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.175.08:25:21.45$vc4f8/vb=3,4 2006.175.08:25:21.45#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.175.08:25:21.45#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.175.08:25:21.45#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:21.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:21.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:21.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:21.51#ibcon#enter wrdev, iclass 32, count 2 2006.175.08:25:21.51#ibcon#first serial, iclass 32, count 2 2006.175.08:25:21.51#ibcon#enter sib2, iclass 32, count 2 2006.175.08:25:21.51#ibcon#flushed, iclass 32, count 2 2006.175.08:25:21.51#ibcon#about to write, iclass 32, count 2 2006.175.08:25:21.51#ibcon#wrote, iclass 32, count 2 2006.175.08:25:21.51#ibcon#about to read 3, iclass 32, count 2 2006.175.08:25:21.53#ibcon#read 3, iclass 32, count 2 2006.175.08:25:21.53#ibcon#about to read 4, iclass 32, count 2 2006.175.08:25:21.53#ibcon#read 4, iclass 32, count 2 2006.175.08:25:21.53#ibcon#about to read 5, iclass 32, count 2 2006.175.08:25:21.53#ibcon#read 5, iclass 32, count 2 2006.175.08:25:21.53#ibcon#about to read 6, iclass 32, count 2 2006.175.08:25:21.53#ibcon#read 6, iclass 32, count 2 2006.175.08:25:21.53#ibcon#end of sib2, iclass 32, count 2 2006.175.08:25:21.53#ibcon#*mode == 0, iclass 32, count 2 2006.175.08:25:21.53#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.175.08:25:21.53#ibcon#[27=AT03-04\r\n] 2006.175.08:25:21.53#ibcon#*before write, iclass 32, count 2 2006.175.08:25:21.53#ibcon#enter sib2, iclass 32, count 2 2006.175.08:25:21.53#ibcon#flushed, iclass 32, count 2 2006.175.08:25:21.53#ibcon#about to write, iclass 32, count 2 2006.175.08:25:21.53#ibcon#wrote, iclass 32, count 2 2006.175.08:25:21.53#ibcon#about to read 3, iclass 32, count 2 2006.175.08:25:21.56#ibcon#read 3, iclass 32, count 2 2006.175.08:25:21.56#ibcon#about to read 4, iclass 32, count 2 2006.175.08:25:21.56#ibcon#read 4, iclass 32, count 2 2006.175.08:25:21.56#ibcon#about to read 5, iclass 32, count 2 2006.175.08:25:21.56#ibcon#read 5, iclass 32, count 2 2006.175.08:25:21.56#ibcon#about to read 6, iclass 32, count 2 2006.175.08:25:21.56#ibcon#read 6, iclass 32, count 2 2006.175.08:25:21.56#ibcon#end of sib2, iclass 32, count 2 2006.175.08:25:21.56#ibcon#*after write, iclass 32, count 2 2006.175.08:25:21.56#ibcon#*before return 0, iclass 32, count 2 2006.175.08:25:21.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:21.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.175.08:25:21.56#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.175.08:25:21.56#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:21.56#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:21.68#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:21.68#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:21.68#ibcon#enter wrdev, iclass 32, count 0 2006.175.08:25:21.68#ibcon#first serial, iclass 32, count 0 2006.175.08:25:21.68#ibcon#enter sib2, iclass 32, count 0 2006.175.08:25:21.68#ibcon#flushed, iclass 32, count 0 2006.175.08:25:21.68#ibcon#about to write, iclass 32, count 0 2006.175.08:25:21.68#ibcon#wrote, iclass 32, count 0 2006.175.08:25:21.68#ibcon#about to read 3, iclass 32, count 0 2006.175.08:25:21.70#ibcon#read 3, iclass 32, count 0 2006.175.08:25:21.70#ibcon#about to read 4, iclass 32, count 0 2006.175.08:25:21.70#ibcon#read 4, iclass 32, count 0 2006.175.08:25:21.70#ibcon#about to read 5, iclass 32, count 0 2006.175.08:25:21.70#ibcon#read 5, iclass 32, count 0 2006.175.08:25:21.70#ibcon#about to read 6, iclass 32, count 0 2006.175.08:25:21.70#ibcon#read 6, iclass 32, count 0 2006.175.08:25:21.70#ibcon#end of sib2, iclass 32, count 0 2006.175.08:25:21.70#ibcon#*mode == 0, iclass 32, count 0 2006.175.08:25:21.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.175.08:25:21.70#ibcon#[27=USB\r\n] 2006.175.08:25:21.70#ibcon#*before write, iclass 32, count 0 2006.175.08:25:21.70#ibcon#enter sib2, iclass 32, count 0 2006.175.08:25:21.70#ibcon#flushed, iclass 32, count 0 2006.175.08:25:21.70#ibcon#about to write, iclass 32, count 0 2006.175.08:25:21.70#ibcon#wrote, iclass 32, count 0 2006.175.08:25:21.70#ibcon#about to read 3, iclass 32, count 0 2006.175.08:25:21.73#ibcon#read 3, iclass 32, count 0 2006.175.08:25:21.73#ibcon#about to read 4, iclass 32, count 0 2006.175.08:25:21.73#ibcon#read 4, iclass 32, count 0 2006.175.08:25:21.73#ibcon#about to read 5, iclass 32, count 0 2006.175.08:25:21.73#ibcon#read 5, iclass 32, count 0 2006.175.08:25:21.73#ibcon#about to read 6, iclass 32, count 0 2006.175.08:25:21.73#ibcon#read 6, iclass 32, count 0 2006.175.08:25:21.73#ibcon#end of sib2, iclass 32, count 0 2006.175.08:25:21.73#ibcon#*after write, iclass 32, count 0 2006.175.08:25:21.73#ibcon#*before return 0, iclass 32, count 0 2006.175.08:25:21.73#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:21.73#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.175.08:25:21.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.175.08:25:21.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.175.08:25:21.73$vc4f8/vblo=4,712.99 2006.175.08:25:21.73#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.175.08:25:21.73#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.175.08:25:21.73#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:21.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:21.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:21.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:21.73#ibcon#enter wrdev, iclass 34, count 0 2006.175.08:25:21.73#ibcon#first serial, iclass 34, count 0 2006.175.08:25:21.73#ibcon#enter sib2, iclass 34, count 0 2006.175.08:25:21.73#ibcon#flushed, iclass 34, count 0 2006.175.08:25:21.73#ibcon#about to write, iclass 34, count 0 2006.175.08:25:21.73#ibcon#wrote, iclass 34, count 0 2006.175.08:25:21.73#ibcon#about to read 3, iclass 34, count 0 2006.175.08:25:21.75#ibcon#read 3, iclass 34, count 0 2006.175.08:25:21.75#ibcon#about to read 4, iclass 34, count 0 2006.175.08:25:21.75#ibcon#read 4, iclass 34, count 0 2006.175.08:25:21.75#ibcon#about to read 5, iclass 34, count 0 2006.175.08:25:21.75#ibcon#read 5, iclass 34, count 0 2006.175.08:25:21.75#ibcon#about to read 6, iclass 34, count 0 2006.175.08:25:21.75#ibcon#read 6, iclass 34, count 0 2006.175.08:25:21.75#ibcon#end of sib2, iclass 34, count 0 2006.175.08:25:21.75#ibcon#*mode == 0, iclass 34, count 0 2006.175.08:25:21.75#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.175.08:25:21.75#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:25:21.75#ibcon#*before write, iclass 34, count 0 2006.175.08:25:21.75#ibcon#enter sib2, iclass 34, count 0 2006.175.08:25:21.75#ibcon#flushed, iclass 34, count 0 2006.175.08:25:21.75#ibcon#about to write, iclass 34, count 0 2006.175.08:25:21.75#ibcon#wrote, iclass 34, count 0 2006.175.08:25:21.75#ibcon#about to read 3, iclass 34, count 0 2006.175.08:25:21.79#ibcon#read 3, iclass 34, count 0 2006.175.08:25:21.79#ibcon#about to read 4, iclass 34, count 0 2006.175.08:25:21.79#ibcon#read 4, iclass 34, count 0 2006.175.08:25:21.79#ibcon#about to read 5, iclass 34, count 0 2006.175.08:25:21.79#ibcon#read 5, iclass 34, count 0 2006.175.08:25:21.79#ibcon#about to read 6, iclass 34, count 0 2006.175.08:25:21.79#ibcon#read 6, iclass 34, count 0 2006.175.08:25:21.79#ibcon#end of sib2, iclass 34, count 0 2006.175.08:25:21.79#ibcon#*after write, iclass 34, count 0 2006.175.08:25:21.79#ibcon#*before return 0, iclass 34, count 0 2006.175.08:25:21.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:21.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.175.08:25:21.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.175.08:25:21.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.175.08:25:21.79$vc4f8/vb=4,4 2006.175.08:25:21.79#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.175.08:25:21.79#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.175.08:25:21.79#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:21.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:21.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:21.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:21.85#ibcon#enter wrdev, iclass 36, count 2 2006.175.08:25:21.85#ibcon#first serial, iclass 36, count 2 2006.175.08:25:21.85#ibcon#enter sib2, iclass 36, count 2 2006.175.08:25:21.85#ibcon#flushed, iclass 36, count 2 2006.175.08:25:21.85#ibcon#about to write, iclass 36, count 2 2006.175.08:25:21.85#ibcon#wrote, iclass 36, count 2 2006.175.08:25:21.85#ibcon#about to read 3, iclass 36, count 2 2006.175.08:25:21.87#ibcon#read 3, iclass 36, count 2 2006.175.08:25:21.87#ibcon#about to read 4, iclass 36, count 2 2006.175.08:25:21.87#ibcon#read 4, iclass 36, count 2 2006.175.08:25:21.87#ibcon#about to read 5, iclass 36, count 2 2006.175.08:25:21.87#ibcon#read 5, iclass 36, count 2 2006.175.08:25:21.87#ibcon#about to read 6, iclass 36, count 2 2006.175.08:25:21.87#ibcon#read 6, iclass 36, count 2 2006.175.08:25:21.87#ibcon#end of sib2, iclass 36, count 2 2006.175.08:25:21.87#ibcon#*mode == 0, iclass 36, count 2 2006.175.08:25:21.87#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.175.08:25:21.87#ibcon#[27=AT04-04\r\n] 2006.175.08:25:21.87#ibcon#*before write, iclass 36, count 2 2006.175.08:25:21.87#ibcon#enter sib2, iclass 36, count 2 2006.175.08:25:21.87#ibcon#flushed, iclass 36, count 2 2006.175.08:25:21.87#ibcon#about to write, iclass 36, count 2 2006.175.08:25:21.87#ibcon#wrote, iclass 36, count 2 2006.175.08:25:21.87#ibcon#about to read 3, iclass 36, count 2 2006.175.08:25:21.90#ibcon#read 3, iclass 36, count 2 2006.175.08:25:21.90#ibcon#about to read 4, iclass 36, count 2 2006.175.08:25:21.90#ibcon#read 4, iclass 36, count 2 2006.175.08:25:21.90#ibcon#about to read 5, iclass 36, count 2 2006.175.08:25:21.90#ibcon#read 5, iclass 36, count 2 2006.175.08:25:21.90#ibcon#about to read 6, iclass 36, count 2 2006.175.08:25:21.90#ibcon#read 6, iclass 36, count 2 2006.175.08:25:21.90#ibcon#end of sib2, iclass 36, count 2 2006.175.08:25:21.90#ibcon#*after write, iclass 36, count 2 2006.175.08:25:21.90#ibcon#*before return 0, iclass 36, count 2 2006.175.08:25:21.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:21.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.175.08:25:21.90#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.175.08:25:21.90#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:21.90#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:22.02#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:22.02#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:22.02#ibcon#enter wrdev, iclass 36, count 0 2006.175.08:25:22.02#ibcon#first serial, iclass 36, count 0 2006.175.08:25:22.02#ibcon#enter sib2, iclass 36, count 0 2006.175.08:25:22.02#ibcon#flushed, iclass 36, count 0 2006.175.08:25:22.02#ibcon#about to write, iclass 36, count 0 2006.175.08:25:22.02#ibcon#wrote, iclass 36, count 0 2006.175.08:25:22.02#ibcon#about to read 3, iclass 36, count 0 2006.175.08:25:22.04#ibcon#read 3, iclass 36, count 0 2006.175.08:25:22.04#ibcon#about to read 4, iclass 36, count 0 2006.175.08:25:22.04#ibcon#read 4, iclass 36, count 0 2006.175.08:25:22.04#ibcon#about to read 5, iclass 36, count 0 2006.175.08:25:22.04#ibcon#read 5, iclass 36, count 0 2006.175.08:25:22.04#ibcon#about to read 6, iclass 36, count 0 2006.175.08:25:22.04#ibcon#read 6, iclass 36, count 0 2006.175.08:25:22.04#ibcon#end of sib2, iclass 36, count 0 2006.175.08:25:22.04#ibcon#*mode == 0, iclass 36, count 0 2006.175.08:25:22.04#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.175.08:25:22.04#ibcon#[27=USB\r\n] 2006.175.08:25:22.04#ibcon#*before write, iclass 36, count 0 2006.175.08:25:22.04#ibcon#enter sib2, iclass 36, count 0 2006.175.08:25:22.04#ibcon#flushed, iclass 36, count 0 2006.175.08:25:22.04#ibcon#about to write, iclass 36, count 0 2006.175.08:25:22.04#ibcon#wrote, iclass 36, count 0 2006.175.08:25:22.04#ibcon#about to read 3, iclass 36, count 0 2006.175.08:25:22.07#ibcon#read 3, iclass 36, count 0 2006.175.08:25:22.07#ibcon#about to read 4, iclass 36, count 0 2006.175.08:25:22.07#ibcon#read 4, iclass 36, count 0 2006.175.08:25:22.07#ibcon#about to read 5, iclass 36, count 0 2006.175.08:25:22.07#ibcon#read 5, iclass 36, count 0 2006.175.08:25:22.07#ibcon#about to read 6, iclass 36, count 0 2006.175.08:25:22.07#ibcon#read 6, iclass 36, count 0 2006.175.08:25:22.07#ibcon#end of sib2, iclass 36, count 0 2006.175.08:25:22.07#ibcon#*after write, iclass 36, count 0 2006.175.08:25:22.07#ibcon#*before return 0, iclass 36, count 0 2006.175.08:25:22.07#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:22.07#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.175.08:25:22.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.175.08:25:22.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.175.08:25:22.07$vc4f8/vblo=5,744.99 2006.175.08:25:22.07#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.175.08:25:22.07#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.175.08:25:22.07#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:22.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:22.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:22.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:22.07#ibcon#enter wrdev, iclass 38, count 0 2006.175.08:25:22.07#ibcon#first serial, iclass 38, count 0 2006.175.08:25:22.07#ibcon#enter sib2, iclass 38, count 0 2006.175.08:25:22.07#ibcon#flushed, iclass 38, count 0 2006.175.08:25:22.07#ibcon#about to write, iclass 38, count 0 2006.175.08:25:22.07#ibcon#wrote, iclass 38, count 0 2006.175.08:25:22.07#ibcon#about to read 3, iclass 38, count 0 2006.175.08:25:22.09#ibcon#read 3, iclass 38, count 0 2006.175.08:25:22.09#ibcon#about to read 4, iclass 38, count 0 2006.175.08:25:22.09#ibcon#read 4, iclass 38, count 0 2006.175.08:25:22.09#ibcon#about to read 5, iclass 38, count 0 2006.175.08:25:22.09#ibcon#read 5, iclass 38, count 0 2006.175.08:25:22.09#ibcon#about to read 6, iclass 38, count 0 2006.175.08:25:22.09#ibcon#read 6, iclass 38, count 0 2006.175.08:25:22.09#ibcon#end of sib2, iclass 38, count 0 2006.175.08:25:22.09#ibcon#*mode == 0, iclass 38, count 0 2006.175.08:25:22.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.175.08:25:22.09#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:25:22.09#ibcon#*before write, iclass 38, count 0 2006.175.08:25:22.09#ibcon#enter sib2, iclass 38, count 0 2006.175.08:25:22.09#ibcon#flushed, iclass 38, count 0 2006.175.08:25:22.09#ibcon#about to write, iclass 38, count 0 2006.175.08:25:22.09#ibcon#wrote, iclass 38, count 0 2006.175.08:25:22.09#ibcon#about to read 3, iclass 38, count 0 2006.175.08:25:22.13#ibcon#read 3, iclass 38, count 0 2006.175.08:25:22.13#ibcon#about to read 4, iclass 38, count 0 2006.175.08:25:22.13#ibcon#read 4, iclass 38, count 0 2006.175.08:25:22.13#ibcon#about to read 5, iclass 38, count 0 2006.175.08:25:22.13#ibcon#read 5, iclass 38, count 0 2006.175.08:25:22.13#ibcon#about to read 6, iclass 38, count 0 2006.175.08:25:22.13#ibcon#read 6, iclass 38, count 0 2006.175.08:25:22.13#ibcon#end of sib2, iclass 38, count 0 2006.175.08:25:22.13#ibcon#*after write, iclass 38, count 0 2006.175.08:25:22.13#ibcon#*before return 0, iclass 38, count 0 2006.175.08:25:22.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:22.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.175.08:25:22.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.175.08:25:22.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.175.08:25:22.13$vc4f8/vb=5,4 2006.175.08:25:22.13#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.175.08:25:22.13#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.175.08:25:22.13#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:22.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:22.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:22.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:22.19#ibcon#enter wrdev, iclass 40, count 2 2006.175.08:25:22.19#ibcon#first serial, iclass 40, count 2 2006.175.08:25:22.19#ibcon#enter sib2, iclass 40, count 2 2006.175.08:25:22.19#ibcon#flushed, iclass 40, count 2 2006.175.08:25:22.19#ibcon#about to write, iclass 40, count 2 2006.175.08:25:22.19#ibcon#wrote, iclass 40, count 2 2006.175.08:25:22.19#ibcon#about to read 3, iclass 40, count 2 2006.175.08:25:22.21#ibcon#read 3, iclass 40, count 2 2006.175.08:25:22.21#ibcon#about to read 4, iclass 40, count 2 2006.175.08:25:22.21#ibcon#read 4, iclass 40, count 2 2006.175.08:25:22.21#ibcon#about to read 5, iclass 40, count 2 2006.175.08:25:22.21#ibcon#read 5, iclass 40, count 2 2006.175.08:25:22.21#ibcon#about to read 6, iclass 40, count 2 2006.175.08:25:22.21#ibcon#read 6, iclass 40, count 2 2006.175.08:25:22.21#ibcon#end of sib2, iclass 40, count 2 2006.175.08:25:22.21#ibcon#*mode == 0, iclass 40, count 2 2006.175.08:25:22.21#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.175.08:25:22.21#ibcon#[27=AT05-04\r\n] 2006.175.08:25:22.21#ibcon#*before write, iclass 40, count 2 2006.175.08:25:22.21#ibcon#enter sib2, iclass 40, count 2 2006.175.08:25:22.21#ibcon#flushed, iclass 40, count 2 2006.175.08:25:22.21#ibcon#about to write, iclass 40, count 2 2006.175.08:25:22.21#ibcon#wrote, iclass 40, count 2 2006.175.08:25:22.21#ibcon#about to read 3, iclass 40, count 2 2006.175.08:25:22.24#ibcon#read 3, iclass 40, count 2 2006.175.08:25:22.24#ibcon#about to read 4, iclass 40, count 2 2006.175.08:25:22.24#ibcon#read 4, iclass 40, count 2 2006.175.08:25:22.24#ibcon#about to read 5, iclass 40, count 2 2006.175.08:25:22.24#ibcon#read 5, iclass 40, count 2 2006.175.08:25:22.24#ibcon#about to read 6, iclass 40, count 2 2006.175.08:25:22.24#ibcon#read 6, iclass 40, count 2 2006.175.08:25:22.24#ibcon#end of sib2, iclass 40, count 2 2006.175.08:25:22.24#ibcon#*after write, iclass 40, count 2 2006.175.08:25:22.24#ibcon#*before return 0, iclass 40, count 2 2006.175.08:25:22.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:22.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.175.08:25:22.24#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.175.08:25:22.24#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:22.24#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:22.36#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:22.36#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:22.36#ibcon#enter wrdev, iclass 40, count 0 2006.175.08:25:22.36#ibcon#first serial, iclass 40, count 0 2006.175.08:25:22.36#ibcon#enter sib2, iclass 40, count 0 2006.175.08:25:22.36#ibcon#flushed, iclass 40, count 0 2006.175.08:25:22.36#ibcon#about to write, iclass 40, count 0 2006.175.08:25:22.36#ibcon#wrote, iclass 40, count 0 2006.175.08:25:22.36#ibcon#about to read 3, iclass 40, count 0 2006.175.08:25:22.38#ibcon#read 3, iclass 40, count 0 2006.175.08:25:22.38#ibcon#about to read 4, iclass 40, count 0 2006.175.08:25:22.38#ibcon#read 4, iclass 40, count 0 2006.175.08:25:22.38#ibcon#about to read 5, iclass 40, count 0 2006.175.08:25:22.38#ibcon#read 5, iclass 40, count 0 2006.175.08:25:22.38#ibcon#about to read 6, iclass 40, count 0 2006.175.08:25:22.38#ibcon#read 6, iclass 40, count 0 2006.175.08:25:22.38#ibcon#end of sib2, iclass 40, count 0 2006.175.08:25:22.38#ibcon#*mode == 0, iclass 40, count 0 2006.175.08:25:22.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.175.08:25:22.38#ibcon#[27=USB\r\n] 2006.175.08:25:22.38#ibcon#*before write, iclass 40, count 0 2006.175.08:25:22.38#ibcon#enter sib2, iclass 40, count 0 2006.175.08:25:22.38#ibcon#flushed, iclass 40, count 0 2006.175.08:25:22.38#ibcon#about to write, iclass 40, count 0 2006.175.08:25:22.38#ibcon#wrote, iclass 40, count 0 2006.175.08:25:22.38#ibcon#about to read 3, iclass 40, count 0 2006.175.08:25:22.41#ibcon#read 3, iclass 40, count 0 2006.175.08:25:22.41#ibcon#about to read 4, iclass 40, count 0 2006.175.08:25:22.41#ibcon#read 4, iclass 40, count 0 2006.175.08:25:22.41#ibcon#about to read 5, iclass 40, count 0 2006.175.08:25:22.41#ibcon#read 5, iclass 40, count 0 2006.175.08:25:22.41#ibcon#about to read 6, iclass 40, count 0 2006.175.08:25:22.41#ibcon#read 6, iclass 40, count 0 2006.175.08:25:22.41#ibcon#end of sib2, iclass 40, count 0 2006.175.08:25:22.41#ibcon#*after write, iclass 40, count 0 2006.175.08:25:22.41#ibcon#*before return 0, iclass 40, count 0 2006.175.08:25:22.41#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:22.41#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.175.08:25:22.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.175.08:25:22.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.175.08:25:22.41$vc4f8/vblo=6,752.99 2006.175.08:25:22.41#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.175.08:25:22.41#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.175.08:25:22.41#ibcon#ireg 17 cls_cnt 0 2006.175.08:25:22.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:22.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:22.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:22.41#ibcon#enter wrdev, iclass 4, count 0 2006.175.08:25:22.41#ibcon#first serial, iclass 4, count 0 2006.175.08:25:22.41#ibcon#enter sib2, iclass 4, count 0 2006.175.08:25:22.41#ibcon#flushed, iclass 4, count 0 2006.175.08:25:22.41#ibcon#about to write, iclass 4, count 0 2006.175.08:25:22.41#ibcon#wrote, iclass 4, count 0 2006.175.08:25:22.41#ibcon#about to read 3, iclass 4, count 0 2006.175.08:25:22.43#ibcon#read 3, iclass 4, count 0 2006.175.08:25:22.43#ibcon#about to read 4, iclass 4, count 0 2006.175.08:25:22.43#ibcon#read 4, iclass 4, count 0 2006.175.08:25:22.43#ibcon#about to read 5, iclass 4, count 0 2006.175.08:25:22.43#ibcon#read 5, iclass 4, count 0 2006.175.08:25:22.43#ibcon#about to read 6, iclass 4, count 0 2006.175.08:25:22.43#ibcon#read 6, iclass 4, count 0 2006.175.08:25:22.43#ibcon#end of sib2, iclass 4, count 0 2006.175.08:25:22.43#ibcon#*mode == 0, iclass 4, count 0 2006.175.08:25:22.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.175.08:25:22.43#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:25:22.43#ibcon#*before write, iclass 4, count 0 2006.175.08:25:22.43#ibcon#enter sib2, iclass 4, count 0 2006.175.08:25:22.43#ibcon#flushed, iclass 4, count 0 2006.175.08:25:22.43#ibcon#about to write, iclass 4, count 0 2006.175.08:25:22.43#ibcon#wrote, iclass 4, count 0 2006.175.08:25:22.43#ibcon#about to read 3, iclass 4, count 0 2006.175.08:25:22.47#ibcon#read 3, iclass 4, count 0 2006.175.08:25:22.47#ibcon#about to read 4, iclass 4, count 0 2006.175.08:25:22.47#ibcon#read 4, iclass 4, count 0 2006.175.08:25:22.47#ibcon#about to read 5, iclass 4, count 0 2006.175.08:25:22.47#ibcon#read 5, iclass 4, count 0 2006.175.08:25:22.47#ibcon#about to read 6, iclass 4, count 0 2006.175.08:25:22.47#ibcon#read 6, iclass 4, count 0 2006.175.08:25:22.47#ibcon#end of sib2, iclass 4, count 0 2006.175.08:25:22.47#ibcon#*after write, iclass 4, count 0 2006.175.08:25:22.47#ibcon#*before return 0, iclass 4, count 0 2006.175.08:25:22.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:22.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.175.08:25:22.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.175.08:25:22.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.175.08:25:22.47$vc4f8/vb=6,4 2006.175.08:25:22.47#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.175.08:25:22.47#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.175.08:25:22.47#ibcon#ireg 11 cls_cnt 2 2006.175.08:25:22.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:22.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:22.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:22.53#ibcon#enter wrdev, iclass 6, count 2 2006.175.08:25:22.53#ibcon#first serial, iclass 6, count 2 2006.175.08:25:22.53#ibcon#enter sib2, iclass 6, count 2 2006.175.08:25:22.53#ibcon#flushed, iclass 6, count 2 2006.175.08:25:22.53#ibcon#about to write, iclass 6, count 2 2006.175.08:25:22.53#ibcon#wrote, iclass 6, count 2 2006.175.08:25:22.53#ibcon#about to read 3, iclass 6, count 2 2006.175.08:25:22.55#ibcon#read 3, iclass 6, count 2 2006.175.08:25:22.55#ibcon#about to read 4, iclass 6, count 2 2006.175.08:25:22.55#ibcon#read 4, iclass 6, count 2 2006.175.08:25:22.55#ibcon#about to read 5, iclass 6, count 2 2006.175.08:25:22.55#ibcon#read 5, iclass 6, count 2 2006.175.08:25:22.55#ibcon#about to read 6, iclass 6, count 2 2006.175.08:25:22.55#ibcon#read 6, iclass 6, count 2 2006.175.08:25:22.55#ibcon#end of sib2, iclass 6, count 2 2006.175.08:25:22.55#ibcon#*mode == 0, iclass 6, count 2 2006.175.08:25:22.55#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.175.08:25:22.55#ibcon#[27=AT06-04\r\n] 2006.175.08:25:22.55#ibcon#*before write, iclass 6, count 2 2006.175.08:25:22.55#ibcon#enter sib2, iclass 6, count 2 2006.175.08:25:22.55#ibcon#flushed, iclass 6, count 2 2006.175.08:25:22.55#ibcon#about to write, iclass 6, count 2 2006.175.08:25:22.55#ibcon#wrote, iclass 6, count 2 2006.175.08:25:22.55#ibcon#about to read 3, iclass 6, count 2 2006.175.08:25:22.58#ibcon#read 3, iclass 6, count 2 2006.175.08:25:22.58#ibcon#about to read 4, iclass 6, count 2 2006.175.08:25:22.58#ibcon#read 4, iclass 6, count 2 2006.175.08:25:22.58#ibcon#about to read 5, iclass 6, count 2 2006.175.08:25:22.58#ibcon#read 5, iclass 6, count 2 2006.175.08:25:22.58#ibcon#about to read 6, iclass 6, count 2 2006.175.08:25:22.58#ibcon#read 6, iclass 6, count 2 2006.175.08:25:22.58#ibcon#end of sib2, iclass 6, count 2 2006.175.08:25:22.58#ibcon#*after write, iclass 6, count 2 2006.175.08:25:22.58#ibcon#*before return 0, iclass 6, count 2 2006.175.08:25:22.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:22.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.175.08:25:22.58#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.175.08:25:22.58#ibcon#ireg 7 cls_cnt 0 2006.175.08:25:22.58#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:22.70#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:22.70#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:22.70#ibcon#enter wrdev, iclass 6, count 0 2006.175.08:25:22.70#ibcon#first serial, iclass 6, count 0 2006.175.08:25:22.70#ibcon#enter sib2, iclass 6, count 0 2006.175.08:25:22.70#ibcon#flushed, iclass 6, count 0 2006.175.08:25:22.70#ibcon#about to write, iclass 6, count 0 2006.175.08:25:22.70#ibcon#wrote, iclass 6, count 0 2006.175.08:25:22.70#ibcon#about to read 3, iclass 6, count 0 2006.175.08:25:22.72#ibcon#read 3, iclass 6, count 0 2006.175.08:25:22.72#ibcon#about to read 4, iclass 6, count 0 2006.175.08:25:22.72#ibcon#read 4, iclass 6, count 0 2006.175.08:25:22.72#ibcon#about to read 5, iclass 6, count 0 2006.175.08:25:22.72#ibcon#read 5, iclass 6, count 0 2006.175.08:25:22.72#ibcon#about to read 6, iclass 6, count 0 2006.175.08:25:22.72#ibcon#read 6, iclass 6, count 0 2006.175.08:25:22.72#ibcon#end of sib2, iclass 6, count 0 2006.175.08:25:22.72#ibcon#*mode == 0, iclass 6, count 0 2006.175.08:25:22.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.175.08:25:22.72#ibcon#[27=USB\r\n] 2006.175.08:25:22.72#ibcon#*before write, iclass 6, count 0 2006.175.08:25:22.72#ibcon#enter sib2, iclass 6, count 0 2006.175.08:25:22.72#ibcon#flushed, iclass 6, count 0 2006.175.08:25:22.72#ibcon#about to write, iclass 6, count 0 2006.175.08:25:22.72#ibcon#wrote, iclass 6, count 0 2006.175.08:25:22.72#ibcon#about to read 3, iclass 6, count 0 2006.175.08:25:22.75#ibcon#read 3, iclass 6, count 0 2006.175.08:25:22.75#ibcon#about to read 4, iclass 6, count 0 2006.175.08:25:22.75#ibcon#read 4, iclass 6, count 0 2006.175.08:25:22.75#ibcon#about to read 5, iclass 6, count 0 2006.175.08:25:22.75#ibcon#read 5, iclass 6, count 0 2006.175.08:25:22.75#ibcon#about to read 6, iclass 6, count 0 2006.175.08:25:22.75#ibcon#read 6, iclass 6, count 0 2006.175.08:25:22.75#ibcon#end of sib2, iclass 6, count 0 2006.175.08:25:22.75#ibcon#*after write, iclass 6, count 0 2006.175.08:25:22.75#ibcon#*before return 0, iclass 6, count 0 2006.175.08:25:22.75#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:22.75#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.175.08:25:22.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.175.08:25:22.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.175.08:25:22.75$vc4f8/vabw=wide 2006.175.08:25:22.75#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.175.08:25:22.75#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.175.08:25:22.75#ibcon#ireg 8 cls_cnt 0 2006.175.08:25:22.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:22.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:22.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:22.75#ibcon#enter wrdev, iclass 10, count 0 2006.175.08:25:22.75#ibcon#first serial, iclass 10, count 0 2006.175.08:25:22.75#ibcon#enter sib2, iclass 10, count 0 2006.175.08:25:22.75#ibcon#flushed, iclass 10, count 0 2006.175.08:25:22.75#ibcon#about to write, iclass 10, count 0 2006.175.08:25:22.75#ibcon#wrote, iclass 10, count 0 2006.175.08:25:22.75#ibcon#about to read 3, iclass 10, count 0 2006.175.08:25:22.77#ibcon#read 3, iclass 10, count 0 2006.175.08:25:22.77#ibcon#about to read 4, iclass 10, count 0 2006.175.08:25:22.77#ibcon#read 4, iclass 10, count 0 2006.175.08:25:22.77#ibcon#about to read 5, iclass 10, count 0 2006.175.08:25:22.77#ibcon#read 5, iclass 10, count 0 2006.175.08:25:22.77#ibcon#about to read 6, iclass 10, count 0 2006.175.08:25:22.77#ibcon#read 6, iclass 10, count 0 2006.175.08:25:22.77#ibcon#end of sib2, iclass 10, count 0 2006.175.08:25:22.77#ibcon#*mode == 0, iclass 10, count 0 2006.175.08:25:22.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.175.08:25:22.77#ibcon#[25=BW32\r\n] 2006.175.08:25:22.77#ibcon#*before write, iclass 10, count 0 2006.175.08:25:22.77#ibcon#enter sib2, iclass 10, count 0 2006.175.08:25:22.77#ibcon#flushed, iclass 10, count 0 2006.175.08:25:22.77#ibcon#about to write, iclass 10, count 0 2006.175.08:25:22.77#ibcon#wrote, iclass 10, count 0 2006.175.08:25:22.77#ibcon#about to read 3, iclass 10, count 0 2006.175.08:25:22.80#ibcon#read 3, iclass 10, count 0 2006.175.08:25:22.80#ibcon#about to read 4, iclass 10, count 0 2006.175.08:25:22.80#ibcon#read 4, iclass 10, count 0 2006.175.08:25:22.80#ibcon#about to read 5, iclass 10, count 0 2006.175.08:25:22.80#ibcon#read 5, iclass 10, count 0 2006.175.08:25:22.80#ibcon#about to read 6, iclass 10, count 0 2006.175.08:25:22.80#ibcon#read 6, iclass 10, count 0 2006.175.08:25:22.80#ibcon#end of sib2, iclass 10, count 0 2006.175.08:25:22.80#ibcon#*after write, iclass 10, count 0 2006.175.08:25:22.80#ibcon#*before return 0, iclass 10, count 0 2006.175.08:25:22.80#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:22.80#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.175.08:25:22.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.175.08:25:22.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.175.08:25:22.80$vc4f8/vbbw=wide 2006.175.08:25:22.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.175.08:25:22.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.175.08:25:22.80#ibcon#ireg 8 cls_cnt 0 2006.175.08:25:22.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:25:22.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:25:22.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:25:22.87#ibcon#enter wrdev, iclass 12, count 0 2006.175.08:25:22.87#ibcon#first serial, iclass 12, count 0 2006.175.08:25:22.87#ibcon#enter sib2, iclass 12, count 0 2006.175.08:25:22.87#ibcon#flushed, iclass 12, count 0 2006.175.08:25:22.87#ibcon#about to write, iclass 12, count 0 2006.175.08:25:22.87#ibcon#wrote, iclass 12, count 0 2006.175.08:25:22.87#ibcon#about to read 3, iclass 12, count 0 2006.175.08:25:22.89#ibcon#read 3, iclass 12, count 0 2006.175.08:25:22.89#ibcon#about to read 4, iclass 12, count 0 2006.175.08:25:22.89#ibcon#read 4, iclass 12, count 0 2006.175.08:25:22.89#ibcon#about to read 5, iclass 12, count 0 2006.175.08:25:22.89#ibcon#read 5, iclass 12, count 0 2006.175.08:25:22.89#ibcon#about to read 6, iclass 12, count 0 2006.175.08:25:22.89#ibcon#read 6, iclass 12, count 0 2006.175.08:25:22.89#ibcon#end of sib2, iclass 12, count 0 2006.175.08:25:22.89#ibcon#*mode == 0, iclass 12, count 0 2006.175.08:25:22.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.175.08:25:22.89#ibcon#[27=BW32\r\n] 2006.175.08:25:22.89#ibcon#*before write, iclass 12, count 0 2006.175.08:25:22.89#ibcon#enter sib2, iclass 12, count 0 2006.175.08:25:22.89#ibcon#flushed, iclass 12, count 0 2006.175.08:25:22.89#ibcon#about to write, iclass 12, count 0 2006.175.08:25:22.89#ibcon#wrote, iclass 12, count 0 2006.175.08:25:22.89#ibcon#about to read 3, iclass 12, count 0 2006.175.08:25:22.92#ibcon#read 3, iclass 12, count 0 2006.175.08:25:22.92#ibcon#about to read 4, iclass 12, count 0 2006.175.08:25:22.92#ibcon#read 4, iclass 12, count 0 2006.175.08:25:22.92#ibcon#about to read 5, iclass 12, count 0 2006.175.08:25:22.92#ibcon#read 5, iclass 12, count 0 2006.175.08:25:22.92#ibcon#about to read 6, iclass 12, count 0 2006.175.08:25:22.92#ibcon#read 6, iclass 12, count 0 2006.175.08:25:22.92#ibcon#end of sib2, iclass 12, count 0 2006.175.08:25:22.92#ibcon#*after write, iclass 12, count 0 2006.175.08:25:22.92#ibcon#*before return 0, iclass 12, count 0 2006.175.08:25:22.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:25:22.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.175.08:25:22.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.175.08:25:22.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.175.08:25:22.92$4f8m12a/ifd4f 2006.175.08:25:22.92$ifd4f/lo= 2006.175.08:25:22.92$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:25:22.92$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:25:22.92$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:25:22.92$ifd4f/patch= 2006.175.08:25:22.92$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:25:22.92$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:25:22.92$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:25:22.92$4f8m12a/"form=m,16.000,1:2 2006.175.08:25:22.92$4f8m12a/"tpicd 2006.175.08:25:22.92$4f8m12a/echo=off 2006.175.08:25:22.92$4f8m12a/xlog=off 2006.175.08:25:22.92:!2006.175.08:26:30 2006.175.08:26:10.14#trakl#Source acquired 2006.175.08:26:11.14#flagr#flagr/antenna,acquired 2006.175.08:26:30.00:preob 2006.175.08:26:30.14/onsource/TRACKING 2006.175.08:26:30.14:!2006.175.08:26:40 2006.175.08:26:40.00:data_valid=on 2006.175.08:26:40.00:midob 2006.175.08:26:41.14/onsource/TRACKING 2006.175.08:26:41.14/wx/25.62,1007.5,72 2006.175.08:26:41.29/cable/+6.4789E-03 2006.175.08:26:42.38/va/01,08,usb,yes,33,35 2006.175.08:26:42.38/va/02,07,usb,yes,33,35 2006.175.08:26:42.38/va/03,06,usb,yes,35,35 2006.175.08:26:42.38/va/04,07,usb,yes,34,37 2006.175.08:26:42.38/va/05,07,usb,yes,35,37 2006.175.08:26:42.38/va/06,06,usb,yes,34,34 2006.175.08:26:42.38/va/07,06,usb,yes,35,34 2006.175.08:26:42.38/va/08,06,usb,yes,37,36 2006.175.08:26:42.61/valo/01,532.99,yes,locked 2006.175.08:26:42.61/valo/02,572.99,yes,locked 2006.175.08:26:42.61/valo/03,672.99,yes,locked 2006.175.08:26:42.61/valo/04,832.99,yes,locked 2006.175.08:26:42.61/valo/05,652.99,yes,locked 2006.175.08:26:42.61/valo/06,772.99,yes,locked 2006.175.08:26:42.61/valo/07,832.99,yes,locked 2006.175.08:26:42.61/valo/08,852.99,yes,locked 2006.175.08:26:43.70/vb/01,04,usb,yes,32,30 2006.175.08:26:43.70/vb/02,04,usb,yes,33,35 2006.175.08:26:43.70/vb/03,04,usb,yes,30,33 2006.175.08:26:43.70/vb/04,04,usb,yes,31,31 2006.175.08:26:43.70/vb/05,04,usb,yes,29,33 2006.175.08:26:43.70/vb/06,04,usb,yes,30,33 2006.175.08:26:43.70/vb/07,04,usb,yes,32,32 2006.175.08:26:43.70/vb/08,04,usb,yes,30,33 2006.175.08:26:43.93/vblo/01,632.99,yes,locked 2006.175.08:26:43.93/vblo/02,640.99,yes,locked 2006.175.08:26:43.93/vblo/03,656.99,yes,locked 2006.175.08:26:43.93/vblo/04,712.99,yes,locked 2006.175.08:26:43.93/vblo/05,744.99,yes,locked 2006.175.08:26:43.93/vblo/06,752.99,yes,locked 2006.175.08:26:43.93/vblo/07,734.99,yes,locked 2006.175.08:26:43.93/vblo/08,744.99,yes,locked 2006.175.08:26:44.08/vabw/8 2006.175.08:26:44.23/vbbw/8 2006.175.08:26:44.32/xfe/off,on,16.0 2006.175.08:26:44.70/ifatt/23,28,28,28 2006.175.08:26:45.08/fmout-gps/S +3.80E-07 2006.175.08:26:45.16:!2006.175.08:27:40 2006.175.08:27:40.00:data_valid=off 2006.175.08:27:40.00:postob 2006.175.08:27:40.12/cable/+6.4809E-03 2006.175.08:27:40.12/wx/25.61,1007.5,71 2006.175.08:27:41.08/fmout-gps/S +3.78E-07 2006.175.08:27:41.08:scan_name=175-0828,k06175,60 2006.175.08:27:41.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.175.08:27:41.14#flagr#flagr/antenna,new-source 2006.175.08:27:42.14:checkk5 2006.175.08:27:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.175.08:27:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.175.08:27:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.175.08:27:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.175.08:27:44.03/chk_obsdata//k5ts1/T1750826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:27:44.41/chk_obsdata//k5ts2/T1750826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:27:44.78/chk_obsdata//k5ts3/T1750826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:27:45.15/chk_obsdata//k5ts4/T1750826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:27:45.84/k5log//k5ts1_log_newline 2006.175.08:27:46.54/k5log//k5ts2_log_newline 2006.175.08:27:47.23/k5log//k5ts3_log_newline 2006.175.08:27:47.92/k5log//k5ts4_log_newline 2006.175.08:27:47.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:27:47.94:4f8m12a=3 2006.175.08:27:47.94$4f8m12a/echo=on 2006.175.08:27:47.94$4f8m12a/pcalon 2006.175.08:27:47.94$pcalon/"no phase cal control is implemented here 2006.175.08:27:47.94$4f8m12a/"tpicd=stop 2006.175.08:27:47.94$4f8m12a/vc4f8 2006.175.08:27:47.94$vc4f8/valo=1,532.99 2006.175.08:27:47.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.175.08:27:47.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.175.08:27:47.94#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:47.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:27:47.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:27:47.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:27:47.94#ibcon#enter wrdev, iclass 35, count 0 2006.175.08:27:47.94#ibcon#first serial, iclass 35, count 0 2006.175.08:27:47.94#ibcon#enter sib2, iclass 35, count 0 2006.175.08:27:47.94#ibcon#flushed, iclass 35, count 0 2006.175.08:27:47.94#ibcon#about to write, iclass 35, count 0 2006.175.08:27:47.94#ibcon#wrote, iclass 35, count 0 2006.175.08:27:47.94#ibcon#about to read 3, iclass 35, count 0 2006.175.08:27:47.96#ibcon#read 3, iclass 35, count 0 2006.175.08:27:47.96#ibcon#about to read 4, iclass 35, count 0 2006.175.08:27:47.96#ibcon#read 4, iclass 35, count 0 2006.175.08:27:47.96#ibcon#about to read 5, iclass 35, count 0 2006.175.08:27:47.96#ibcon#read 5, iclass 35, count 0 2006.175.08:27:47.96#ibcon#about to read 6, iclass 35, count 0 2006.175.08:27:47.96#ibcon#read 6, iclass 35, count 0 2006.175.08:27:47.96#ibcon#end of sib2, iclass 35, count 0 2006.175.08:27:47.96#ibcon#*mode == 0, iclass 35, count 0 2006.175.08:27:47.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.175.08:27:47.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.175.08:27:47.96#ibcon#*before write, iclass 35, count 0 2006.175.08:27:47.96#ibcon#enter sib2, iclass 35, count 0 2006.175.08:27:47.96#ibcon#flushed, iclass 35, count 0 2006.175.08:27:47.96#ibcon#about to write, iclass 35, count 0 2006.175.08:27:47.96#ibcon#wrote, iclass 35, count 0 2006.175.08:27:47.96#ibcon#about to read 3, iclass 35, count 0 2006.175.08:27:48.01#ibcon#read 3, iclass 35, count 0 2006.175.08:27:48.01#ibcon#about to read 4, iclass 35, count 0 2006.175.08:27:48.01#ibcon#read 4, iclass 35, count 0 2006.175.08:27:48.01#ibcon#about to read 5, iclass 35, count 0 2006.175.08:27:48.01#ibcon#read 5, iclass 35, count 0 2006.175.08:27:48.01#ibcon#about to read 6, iclass 35, count 0 2006.175.08:27:48.01#ibcon#read 6, iclass 35, count 0 2006.175.08:27:48.01#ibcon#end of sib2, iclass 35, count 0 2006.175.08:27:48.01#ibcon#*after write, iclass 35, count 0 2006.175.08:27:48.01#ibcon#*before return 0, iclass 35, count 0 2006.175.08:27:48.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:27:48.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.175.08:27:48.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.175.08:27:48.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.175.08:27:48.01$vc4f8/va=1,8 2006.175.08:27:48.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.175.08:27:48.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.175.08:27:48.01#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:48.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:27:48.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:27:48.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:27:48.01#ibcon#enter wrdev, iclass 37, count 2 2006.175.08:27:48.01#ibcon#first serial, iclass 37, count 2 2006.175.08:27:48.01#ibcon#enter sib2, iclass 37, count 2 2006.175.08:27:48.01#ibcon#flushed, iclass 37, count 2 2006.175.08:27:48.01#ibcon#about to write, iclass 37, count 2 2006.175.08:27:48.01#ibcon#wrote, iclass 37, count 2 2006.175.08:27:48.01#ibcon#about to read 3, iclass 37, count 2 2006.175.08:27:48.03#ibcon#read 3, iclass 37, count 2 2006.175.08:27:48.03#ibcon#about to read 4, iclass 37, count 2 2006.175.08:27:48.03#ibcon#read 4, iclass 37, count 2 2006.175.08:27:48.03#ibcon#about to read 5, iclass 37, count 2 2006.175.08:27:48.03#ibcon#read 5, iclass 37, count 2 2006.175.08:27:48.03#ibcon#about to read 6, iclass 37, count 2 2006.175.08:27:48.03#ibcon#read 6, iclass 37, count 2 2006.175.08:27:48.03#ibcon#end of sib2, iclass 37, count 2 2006.175.08:27:48.03#ibcon#*mode == 0, iclass 37, count 2 2006.175.08:27:48.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.175.08:27:48.03#ibcon#[25=AT01-08\r\n] 2006.175.08:27:48.03#ibcon#*before write, iclass 37, count 2 2006.175.08:27:48.03#ibcon#enter sib2, iclass 37, count 2 2006.175.08:27:48.03#ibcon#flushed, iclass 37, count 2 2006.175.08:27:48.03#ibcon#about to write, iclass 37, count 2 2006.175.08:27:48.03#ibcon#wrote, iclass 37, count 2 2006.175.08:27:48.03#ibcon#about to read 3, iclass 37, count 2 2006.175.08:27:48.06#ibcon#read 3, iclass 37, count 2 2006.175.08:27:48.06#ibcon#about to read 4, iclass 37, count 2 2006.175.08:27:48.06#ibcon#read 4, iclass 37, count 2 2006.175.08:27:48.06#ibcon#about to read 5, iclass 37, count 2 2006.175.08:27:48.06#ibcon#read 5, iclass 37, count 2 2006.175.08:27:48.06#ibcon#about to read 6, iclass 37, count 2 2006.175.08:27:48.06#ibcon#read 6, iclass 37, count 2 2006.175.08:27:48.06#ibcon#end of sib2, iclass 37, count 2 2006.175.08:27:48.06#ibcon#*after write, iclass 37, count 2 2006.175.08:27:48.06#ibcon#*before return 0, iclass 37, count 2 2006.175.08:27:48.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:27:48.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.175.08:27:48.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.175.08:27:48.06#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:48.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:27:48.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:27:48.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:27:48.18#ibcon#enter wrdev, iclass 37, count 0 2006.175.08:27:48.18#ibcon#first serial, iclass 37, count 0 2006.175.08:27:48.18#ibcon#enter sib2, iclass 37, count 0 2006.175.08:27:48.18#ibcon#flushed, iclass 37, count 0 2006.175.08:27:48.18#ibcon#about to write, iclass 37, count 0 2006.175.08:27:48.18#ibcon#wrote, iclass 37, count 0 2006.175.08:27:48.18#ibcon#about to read 3, iclass 37, count 0 2006.175.08:27:48.20#ibcon#read 3, iclass 37, count 0 2006.175.08:27:48.20#ibcon#about to read 4, iclass 37, count 0 2006.175.08:27:48.20#ibcon#read 4, iclass 37, count 0 2006.175.08:27:48.20#ibcon#about to read 5, iclass 37, count 0 2006.175.08:27:48.20#ibcon#read 5, iclass 37, count 0 2006.175.08:27:48.20#ibcon#about to read 6, iclass 37, count 0 2006.175.08:27:48.20#ibcon#read 6, iclass 37, count 0 2006.175.08:27:48.20#ibcon#end of sib2, iclass 37, count 0 2006.175.08:27:48.20#ibcon#*mode == 0, iclass 37, count 0 2006.175.08:27:48.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.175.08:27:48.20#ibcon#[25=USB\r\n] 2006.175.08:27:48.20#ibcon#*before write, iclass 37, count 0 2006.175.08:27:48.20#ibcon#enter sib2, iclass 37, count 0 2006.175.08:27:48.20#ibcon#flushed, iclass 37, count 0 2006.175.08:27:48.20#ibcon#about to write, iclass 37, count 0 2006.175.08:27:48.20#ibcon#wrote, iclass 37, count 0 2006.175.08:27:48.20#ibcon#about to read 3, iclass 37, count 0 2006.175.08:27:48.23#ibcon#read 3, iclass 37, count 0 2006.175.08:27:48.23#ibcon#about to read 4, iclass 37, count 0 2006.175.08:27:48.23#ibcon#read 4, iclass 37, count 0 2006.175.08:27:48.23#ibcon#about to read 5, iclass 37, count 0 2006.175.08:27:48.23#ibcon#read 5, iclass 37, count 0 2006.175.08:27:48.23#ibcon#about to read 6, iclass 37, count 0 2006.175.08:27:48.23#ibcon#read 6, iclass 37, count 0 2006.175.08:27:48.23#ibcon#end of sib2, iclass 37, count 0 2006.175.08:27:48.23#ibcon#*after write, iclass 37, count 0 2006.175.08:27:48.23#ibcon#*before return 0, iclass 37, count 0 2006.175.08:27:48.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:27:48.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.175.08:27:48.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.175.08:27:48.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.175.08:27:48.23$vc4f8/valo=2,572.99 2006.175.08:27:48.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.08:27:48.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.08:27:48.23#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:48.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:48.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:48.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:48.23#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:27:48.23#ibcon#first serial, iclass 39, count 0 2006.175.08:27:48.23#ibcon#enter sib2, iclass 39, count 0 2006.175.08:27:48.23#ibcon#flushed, iclass 39, count 0 2006.175.08:27:48.23#ibcon#about to write, iclass 39, count 0 2006.175.08:27:48.23#ibcon#wrote, iclass 39, count 0 2006.175.08:27:48.23#ibcon#about to read 3, iclass 39, count 0 2006.175.08:27:48.25#ibcon#read 3, iclass 39, count 0 2006.175.08:27:48.25#ibcon#about to read 4, iclass 39, count 0 2006.175.08:27:48.25#ibcon#read 4, iclass 39, count 0 2006.175.08:27:48.25#ibcon#about to read 5, iclass 39, count 0 2006.175.08:27:48.25#ibcon#read 5, iclass 39, count 0 2006.175.08:27:48.25#ibcon#about to read 6, iclass 39, count 0 2006.175.08:27:48.25#ibcon#read 6, iclass 39, count 0 2006.175.08:27:48.25#ibcon#end of sib2, iclass 39, count 0 2006.175.08:27:48.25#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:27:48.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:27:48.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.175.08:27:48.25#ibcon#*before write, iclass 39, count 0 2006.175.08:27:48.25#ibcon#enter sib2, iclass 39, count 0 2006.175.08:27:48.25#ibcon#flushed, iclass 39, count 0 2006.175.08:27:48.25#ibcon#about to write, iclass 39, count 0 2006.175.08:27:48.25#ibcon#wrote, iclass 39, count 0 2006.175.08:27:48.25#ibcon#about to read 3, iclass 39, count 0 2006.175.08:27:48.29#ibcon#read 3, iclass 39, count 0 2006.175.08:27:48.29#ibcon#about to read 4, iclass 39, count 0 2006.175.08:27:48.29#ibcon#read 4, iclass 39, count 0 2006.175.08:27:48.29#ibcon#about to read 5, iclass 39, count 0 2006.175.08:27:48.29#ibcon#read 5, iclass 39, count 0 2006.175.08:27:48.29#ibcon#about to read 6, iclass 39, count 0 2006.175.08:27:48.29#ibcon#read 6, iclass 39, count 0 2006.175.08:27:48.29#ibcon#end of sib2, iclass 39, count 0 2006.175.08:27:48.29#ibcon#*after write, iclass 39, count 0 2006.175.08:27:48.29#ibcon#*before return 0, iclass 39, count 0 2006.175.08:27:48.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:48.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:48.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:27:48.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:27:48.29$vc4f8/va=2,7 2006.175.08:27:48.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.08:27:48.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.08:27:48.29#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:48.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:48.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:48.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:48.35#ibcon#enter wrdev, iclass 3, count 2 2006.175.08:27:48.35#ibcon#first serial, iclass 3, count 2 2006.175.08:27:48.35#ibcon#enter sib2, iclass 3, count 2 2006.175.08:27:48.35#ibcon#flushed, iclass 3, count 2 2006.175.08:27:48.35#ibcon#about to write, iclass 3, count 2 2006.175.08:27:48.35#ibcon#wrote, iclass 3, count 2 2006.175.08:27:48.35#ibcon#about to read 3, iclass 3, count 2 2006.175.08:27:48.37#ibcon#read 3, iclass 3, count 2 2006.175.08:27:48.37#ibcon#about to read 4, iclass 3, count 2 2006.175.08:27:48.37#ibcon#read 4, iclass 3, count 2 2006.175.08:27:48.37#ibcon#about to read 5, iclass 3, count 2 2006.175.08:27:48.37#ibcon#read 5, iclass 3, count 2 2006.175.08:27:48.37#ibcon#about to read 6, iclass 3, count 2 2006.175.08:27:48.37#ibcon#read 6, iclass 3, count 2 2006.175.08:27:48.37#ibcon#end of sib2, iclass 3, count 2 2006.175.08:27:48.37#ibcon#*mode == 0, iclass 3, count 2 2006.175.08:27:48.37#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.08:27:48.37#ibcon#[25=AT02-07\r\n] 2006.175.08:27:48.37#ibcon#*before write, iclass 3, count 2 2006.175.08:27:48.37#ibcon#enter sib2, iclass 3, count 2 2006.175.08:27:48.37#ibcon#flushed, iclass 3, count 2 2006.175.08:27:48.37#ibcon#about to write, iclass 3, count 2 2006.175.08:27:48.37#ibcon#wrote, iclass 3, count 2 2006.175.08:27:48.37#ibcon#about to read 3, iclass 3, count 2 2006.175.08:27:48.40#ibcon#read 3, iclass 3, count 2 2006.175.08:27:48.40#ibcon#about to read 4, iclass 3, count 2 2006.175.08:27:48.40#ibcon#read 4, iclass 3, count 2 2006.175.08:27:48.40#ibcon#about to read 5, iclass 3, count 2 2006.175.08:27:48.40#ibcon#read 5, iclass 3, count 2 2006.175.08:27:48.40#ibcon#about to read 6, iclass 3, count 2 2006.175.08:27:48.40#ibcon#read 6, iclass 3, count 2 2006.175.08:27:48.40#ibcon#end of sib2, iclass 3, count 2 2006.175.08:27:48.40#ibcon#*after write, iclass 3, count 2 2006.175.08:27:48.40#ibcon#*before return 0, iclass 3, count 2 2006.175.08:27:48.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:48.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:48.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.08:27:48.40#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:48.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:48.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:48.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:48.52#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:27:48.52#ibcon#first serial, iclass 3, count 0 2006.175.08:27:48.52#ibcon#enter sib2, iclass 3, count 0 2006.175.08:27:48.52#ibcon#flushed, iclass 3, count 0 2006.175.08:27:48.52#ibcon#about to write, iclass 3, count 0 2006.175.08:27:48.52#ibcon#wrote, iclass 3, count 0 2006.175.08:27:48.52#ibcon#about to read 3, iclass 3, count 0 2006.175.08:27:48.54#ibcon#read 3, iclass 3, count 0 2006.175.08:27:48.54#ibcon#about to read 4, iclass 3, count 0 2006.175.08:27:48.54#ibcon#read 4, iclass 3, count 0 2006.175.08:27:48.54#ibcon#about to read 5, iclass 3, count 0 2006.175.08:27:48.54#ibcon#read 5, iclass 3, count 0 2006.175.08:27:48.54#ibcon#about to read 6, iclass 3, count 0 2006.175.08:27:48.54#ibcon#read 6, iclass 3, count 0 2006.175.08:27:48.54#ibcon#end of sib2, iclass 3, count 0 2006.175.08:27:48.54#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:27:48.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:27:48.54#ibcon#[25=USB\r\n] 2006.175.08:27:48.54#ibcon#*before write, iclass 3, count 0 2006.175.08:27:48.54#ibcon#enter sib2, iclass 3, count 0 2006.175.08:27:48.54#ibcon#flushed, iclass 3, count 0 2006.175.08:27:48.54#ibcon#about to write, iclass 3, count 0 2006.175.08:27:48.54#ibcon#wrote, iclass 3, count 0 2006.175.08:27:48.54#ibcon#about to read 3, iclass 3, count 0 2006.175.08:27:48.57#ibcon#read 3, iclass 3, count 0 2006.175.08:27:48.57#ibcon#about to read 4, iclass 3, count 0 2006.175.08:27:48.57#ibcon#read 4, iclass 3, count 0 2006.175.08:27:48.57#ibcon#about to read 5, iclass 3, count 0 2006.175.08:27:48.57#ibcon#read 5, iclass 3, count 0 2006.175.08:27:48.57#ibcon#about to read 6, iclass 3, count 0 2006.175.08:27:48.57#ibcon#read 6, iclass 3, count 0 2006.175.08:27:48.57#ibcon#end of sib2, iclass 3, count 0 2006.175.08:27:48.57#ibcon#*after write, iclass 3, count 0 2006.175.08:27:48.57#ibcon#*before return 0, iclass 3, count 0 2006.175.08:27:48.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:48.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:48.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:27:48.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:27:48.57$vc4f8/valo=3,672.99 2006.175.08:27:48.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.08:27:48.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.08:27:48.57#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:48.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:48.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:48.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:48.57#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:27:48.57#ibcon#first serial, iclass 5, count 0 2006.175.08:27:48.57#ibcon#enter sib2, iclass 5, count 0 2006.175.08:27:48.57#ibcon#flushed, iclass 5, count 0 2006.175.08:27:48.57#ibcon#about to write, iclass 5, count 0 2006.175.08:27:48.57#ibcon#wrote, iclass 5, count 0 2006.175.08:27:48.57#ibcon#about to read 3, iclass 5, count 0 2006.175.08:27:48.59#ibcon#read 3, iclass 5, count 0 2006.175.08:27:48.59#ibcon#about to read 4, iclass 5, count 0 2006.175.08:27:48.59#ibcon#read 4, iclass 5, count 0 2006.175.08:27:48.59#ibcon#about to read 5, iclass 5, count 0 2006.175.08:27:48.59#ibcon#read 5, iclass 5, count 0 2006.175.08:27:48.59#ibcon#about to read 6, iclass 5, count 0 2006.175.08:27:48.59#ibcon#read 6, iclass 5, count 0 2006.175.08:27:48.59#ibcon#end of sib2, iclass 5, count 0 2006.175.08:27:48.59#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:27:48.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:27:48.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.175.08:27:48.59#ibcon#*before write, iclass 5, count 0 2006.175.08:27:48.59#ibcon#enter sib2, iclass 5, count 0 2006.175.08:27:48.59#ibcon#flushed, iclass 5, count 0 2006.175.08:27:48.59#ibcon#about to write, iclass 5, count 0 2006.175.08:27:48.59#ibcon#wrote, iclass 5, count 0 2006.175.08:27:48.59#ibcon#about to read 3, iclass 5, count 0 2006.175.08:27:48.63#ibcon#read 3, iclass 5, count 0 2006.175.08:27:48.63#ibcon#about to read 4, iclass 5, count 0 2006.175.08:27:48.63#ibcon#read 4, iclass 5, count 0 2006.175.08:27:48.63#ibcon#about to read 5, iclass 5, count 0 2006.175.08:27:48.63#ibcon#read 5, iclass 5, count 0 2006.175.08:27:48.63#ibcon#about to read 6, iclass 5, count 0 2006.175.08:27:48.63#ibcon#read 6, iclass 5, count 0 2006.175.08:27:48.63#ibcon#end of sib2, iclass 5, count 0 2006.175.08:27:48.63#ibcon#*after write, iclass 5, count 0 2006.175.08:27:48.63#ibcon#*before return 0, iclass 5, count 0 2006.175.08:27:48.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:48.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:48.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:27:48.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:27:48.63$vc4f8/va=3,6 2006.175.08:27:48.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.08:27:48.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.08:27:48.63#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:48.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:48.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:48.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:48.69#ibcon#enter wrdev, iclass 7, count 2 2006.175.08:27:48.69#ibcon#first serial, iclass 7, count 2 2006.175.08:27:48.69#ibcon#enter sib2, iclass 7, count 2 2006.175.08:27:48.69#ibcon#flushed, iclass 7, count 2 2006.175.08:27:48.69#ibcon#about to write, iclass 7, count 2 2006.175.08:27:48.69#ibcon#wrote, iclass 7, count 2 2006.175.08:27:48.69#ibcon#about to read 3, iclass 7, count 2 2006.175.08:27:48.71#ibcon#read 3, iclass 7, count 2 2006.175.08:27:48.71#ibcon#about to read 4, iclass 7, count 2 2006.175.08:27:48.71#ibcon#read 4, iclass 7, count 2 2006.175.08:27:48.71#ibcon#about to read 5, iclass 7, count 2 2006.175.08:27:48.71#ibcon#read 5, iclass 7, count 2 2006.175.08:27:48.71#ibcon#about to read 6, iclass 7, count 2 2006.175.08:27:48.71#ibcon#read 6, iclass 7, count 2 2006.175.08:27:48.71#ibcon#end of sib2, iclass 7, count 2 2006.175.08:27:48.71#ibcon#*mode == 0, iclass 7, count 2 2006.175.08:27:48.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.08:27:48.71#ibcon#[25=AT03-06\r\n] 2006.175.08:27:48.71#ibcon#*before write, iclass 7, count 2 2006.175.08:27:48.71#ibcon#enter sib2, iclass 7, count 2 2006.175.08:27:48.71#ibcon#flushed, iclass 7, count 2 2006.175.08:27:48.71#ibcon#about to write, iclass 7, count 2 2006.175.08:27:48.71#ibcon#wrote, iclass 7, count 2 2006.175.08:27:48.71#ibcon#about to read 3, iclass 7, count 2 2006.175.08:27:48.74#ibcon#read 3, iclass 7, count 2 2006.175.08:27:48.74#ibcon#about to read 4, iclass 7, count 2 2006.175.08:27:48.74#ibcon#read 4, iclass 7, count 2 2006.175.08:27:48.74#ibcon#about to read 5, iclass 7, count 2 2006.175.08:27:48.74#ibcon#read 5, iclass 7, count 2 2006.175.08:27:48.74#ibcon#about to read 6, iclass 7, count 2 2006.175.08:27:48.74#ibcon#read 6, iclass 7, count 2 2006.175.08:27:48.74#ibcon#end of sib2, iclass 7, count 2 2006.175.08:27:48.74#ibcon#*after write, iclass 7, count 2 2006.175.08:27:48.74#ibcon#*before return 0, iclass 7, count 2 2006.175.08:27:48.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:48.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:48.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.08:27:48.74#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:48.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:48.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:48.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:48.86#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:27:48.86#ibcon#first serial, iclass 7, count 0 2006.175.08:27:48.86#ibcon#enter sib2, iclass 7, count 0 2006.175.08:27:48.86#ibcon#flushed, iclass 7, count 0 2006.175.08:27:48.86#ibcon#about to write, iclass 7, count 0 2006.175.08:27:48.86#ibcon#wrote, iclass 7, count 0 2006.175.08:27:48.86#ibcon#about to read 3, iclass 7, count 0 2006.175.08:27:48.88#ibcon#read 3, iclass 7, count 0 2006.175.08:27:48.88#ibcon#about to read 4, iclass 7, count 0 2006.175.08:27:48.88#ibcon#read 4, iclass 7, count 0 2006.175.08:27:48.88#ibcon#about to read 5, iclass 7, count 0 2006.175.08:27:48.88#ibcon#read 5, iclass 7, count 0 2006.175.08:27:48.88#ibcon#about to read 6, iclass 7, count 0 2006.175.08:27:48.88#ibcon#read 6, iclass 7, count 0 2006.175.08:27:48.88#ibcon#end of sib2, iclass 7, count 0 2006.175.08:27:48.88#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:27:48.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:27:48.88#ibcon#[25=USB\r\n] 2006.175.08:27:48.88#ibcon#*before write, iclass 7, count 0 2006.175.08:27:48.88#ibcon#enter sib2, iclass 7, count 0 2006.175.08:27:48.88#ibcon#flushed, iclass 7, count 0 2006.175.08:27:48.88#ibcon#about to write, iclass 7, count 0 2006.175.08:27:48.88#ibcon#wrote, iclass 7, count 0 2006.175.08:27:48.88#ibcon#about to read 3, iclass 7, count 0 2006.175.08:27:48.91#ibcon#read 3, iclass 7, count 0 2006.175.08:27:48.91#ibcon#about to read 4, iclass 7, count 0 2006.175.08:27:48.91#ibcon#read 4, iclass 7, count 0 2006.175.08:27:48.91#ibcon#about to read 5, iclass 7, count 0 2006.175.08:27:48.91#ibcon#read 5, iclass 7, count 0 2006.175.08:27:48.91#ibcon#about to read 6, iclass 7, count 0 2006.175.08:27:48.91#ibcon#read 6, iclass 7, count 0 2006.175.08:27:48.91#ibcon#end of sib2, iclass 7, count 0 2006.175.08:27:48.91#ibcon#*after write, iclass 7, count 0 2006.175.08:27:48.91#ibcon#*before return 0, iclass 7, count 0 2006.175.08:27:48.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:48.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:48.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:27:48.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:27:48.91$vc4f8/valo=4,832.99 2006.175.08:27:48.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.08:27:48.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.08:27:48.91#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:48.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:48.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:48.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:48.91#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:27:48.91#ibcon#first serial, iclass 11, count 0 2006.175.08:27:48.91#ibcon#enter sib2, iclass 11, count 0 2006.175.08:27:48.91#ibcon#flushed, iclass 11, count 0 2006.175.08:27:48.91#ibcon#about to write, iclass 11, count 0 2006.175.08:27:48.91#ibcon#wrote, iclass 11, count 0 2006.175.08:27:48.91#ibcon#about to read 3, iclass 11, count 0 2006.175.08:27:48.93#ibcon#read 3, iclass 11, count 0 2006.175.08:27:48.93#ibcon#about to read 4, iclass 11, count 0 2006.175.08:27:48.93#ibcon#read 4, iclass 11, count 0 2006.175.08:27:48.93#ibcon#about to read 5, iclass 11, count 0 2006.175.08:27:48.93#ibcon#read 5, iclass 11, count 0 2006.175.08:27:48.93#ibcon#about to read 6, iclass 11, count 0 2006.175.08:27:48.93#ibcon#read 6, iclass 11, count 0 2006.175.08:27:48.93#ibcon#end of sib2, iclass 11, count 0 2006.175.08:27:48.93#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:27:48.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:27:48.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.175.08:27:48.93#ibcon#*before write, iclass 11, count 0 2006.175.08:27:48.93#ibcon#enter sib2, iclass 11, count 0 2006.175.08:27:48.93#ibcon#flushed, iclass 11, count 0 2006.175.08:27:48.93#ibcon#about to write, iclass 11, count 0 2006.175.08:27:48.93#ibcon#wrote, iclass 11, count 0 2006.175.08:27:48.93#ibcon#about to read 3, iclass 11, count 0 2006.175.08:27:48.97#ibcon#read 3, iclass 11, count 0 2006.175.08:27:48.97#ibcon#about to read 4, iclass 11, count 0 2006.175.08:27:48.97#ibcon#read 4, iclass 11, count 0 2006.175.08:27:48.97#ibcon#about to read 5, iclass 11, count 0 2006.175.08:27:48.97#ibcon#read 5, iclass 11, count 0 2006.175.08:27:48.97#ibcon#about to read 6, iclass 11, count 0 2006.175.08:27:48.97#ibcon#read 6, iclass 11, count 0 2006.175.08:27:48.97#ibcon#end of sib2, iclass 11, count 0 2006.175.08:27:48.97#ibcon#*after write, iclass 11, count 0 2006.175.08:27:48.97#ibcon#*before return 0, iclass 11, count 0 2006.175.08:27:48.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:48.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:48.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:27:48.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:27:48.97$vc4f8/va=4,7 2006.175.08:27:48.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.08:27:48.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.08:27:48.97#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:48.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:49.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:49.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:49.03#ibcon#enter wrdev, iclass 13, count 2 2006.175.08:27:49.03#ibcon#first serial, iclass 13, count 2 2006.175.08:27:49.03#ibcon#enter sib2, iclass 13, count 2 2006.175.08:27:49.03#ibcon#flushed, iclass 13, count 2 2006.175.08:27:49.03#ibcon#about to write, iclass 13, count 2 2006.175.08:27:49.03#ibcon#wrote, iclass 13, count 2 2006.175.08:27:49.03#ibcon#about to read 3, iclass 13, count 2 2006.175.08:27:49.05#ibcon#read 3, iclass 13, count 2 2006.175.08:27:49.05#ibcon#about to read 4, iclass 13, count 2 2006.175.08:27:49.05#ibcon#read 4, iclass 13, count 2 2006.175.08:27:49.05#ibcon#about to read 5, iclass 13, count 2 2006.175.08:27:49.05#ibcon#read 5, iclass 13, count 2 2006.175.08:27:49.05#ibcon#about to read 6, iclass 13, count 2 2006.175.08:27:49.05#ibcon#read 6, iclass 13, count 2 2006.175.08:27:49.05#ibcon#end of sib2, iclass 13, count 2 2006.175.08:27:49.05#ibcon#*mode == 0, iclass 13, count 2 2006.175.08:27:49.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.08:27:49.05#ibcon#[25=AT04-07\r\n] 2006.175.08:27:49.05#ibcon#*before write, iclass 13, count 2 2006.175.08:27:49.05#ibcon#enter sib2, iclass 13, count 2 2006.175.08:27:49.05#ibcon#flushed, iclass 13, count 2 2006.175.08:27:49.05#ibcon#about to write, iclass 13, count 2 2006.175.08:27:49.05#ibcon#wrote, iclass 13, count 2 2006.175.08:27:49.05#ibcon#about to read 3, iclass 13, count 2 2006.175.08:27:49.08#ibcon#read 3, iclass 13, count 2 2006.175.08:27:49.08#ibcon#about to read 4, iclass 13, count 2 2006.175.08:27:49.08#ibcon#read 4, iclass 13, count 2 2006.175.08:27:49.08#ibcon#about to read 5, iclass 13, count 2 2006.175.08:27:49.08#ibcon#read 5, iclass 13, count 2 2006.175.08:27:49.08#ibcon#about to read 6, iclass 13, count 2 2006.175.08:27:49.08#ibcon#read 6, iclass 13, count 2 2006.175.08:27:49.08#ibcon#end of sib2, iclass 13, count 2 2006.175.08:27:49.08#ibcon#*after write, iclass 13, count 2 2006.175.08:27:49.08#ibcon#*before return 0, iclass 13, count 2 2006.175.08:27:49.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:49.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:49.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.08:27:49.08#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:49.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:49.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:49.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:49.20#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:27:49.20#ibcon#first serial, iclass 13, count 0 2006.175.08:27:49.20#ibcon#enter sib2, iclass 13, count 0 2006.175.08:27:49.20#ibcon#flushed, iclass 13, count 0 2006.175.08:27:49.20#ibcon#about to write, iclass 13, count 0 2006.175.08:27:49.20#ibcon#wrote, iclass 13, count 0 2006.175.08:27:49.20#ibcon#about to read 3, iclass 13, count 0 2006.175.08:27:49.22#ibcon#read 3, iclass 13, count 0 2006.175.08:27:49.22#ibcon#about to read 4, iclass 13, count 0 2006.175.08:27:49.22#ibcon#read 4, iclass 13, count 0 2006.175.08:27:49.22#ibcon#about to read 5, iclass 13, count 0 2006.175.08:27:49.22#ibcon#read 5, iclass 13, count 0 2006.175.08:27:49.22#ibcon#about to read 6, iclass 13, count 0 2006.175.08:27:49.22#ibcon#read 6, iclass 13, count 0 2006.175.08:27:49.22#ibcon#end of sib2, iclass 13, count 0 2006.175.08:27:49.22#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:27:49.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:27:49.22#ibcon#[25=USB\r\n] 2006.175.08:27:49.22#ibcon#*before write, iclass 13, count 0 2006.175.08:27:49.22#ibcon#enter sib2, iclass 13, count 0 2006.175.08:27:49.22#ibcon#flushed, iclass 13, count 0 2006.175.08:27:49.22#ibcon#about to write, iclass 13, count 0 2006.175.08:27:49.22#ibcon#wrote, iclass 13, count 0 2006.175.08:27:49.22#ibcon#about to read 3, iclass 13, count 0 2006.175.08:27:49.25#ibcon#read 3, iclass 13, count 0 2006.175.08:27:49.25#ibcon#about to read 4, iclass 13, count 0 2006.175.08:27:49.25#ibcon#read 4, iclass 13, count 0 2006.175.08:27:49.25#ibcon#about to read 5, iclass 13, count 0 2006.175.08:27:49.25#ibcon#read 5, iclass 13, count 0 2006.175.08:27:49.25#ibcon#about to read 6, iclass 13, count 0 2006.175.08:27:49.25#ibcon#read 6, iclass 13, count 0 2006.175.08:27:49.25#ibcon#end of sib2, iclass 13, count 0 2006.175.08:27:49.25#ibcon#*after write, iclass 13, count 0 2006.175.08:27:49.25#ibcon#*before return 0, iclass 13, count 0 2006.175.08:27:49.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:49.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:49.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:27:49.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:27:49.25$vc4f8/valo=5,652.99 2006.175.08:27:49.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.08:27:49.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.08:27:49.25#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:49.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:49.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:49.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:49.25#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:27:49.25#ibcon#first serial, iclass 15, count 0 2006.175.08:27:49.25#ibcon#enter sib2, iclass 15, count 0 2006.175.08:27:49.25#ibcon#flushed, iclass 15, count 0 2006.175.08:27:49.25#ibcon#about to write, iclass 15, count 0 2006.175.08:27:49.25#ibcon#wrote, iclass 15, count 0 2006.175.08:27:49.25#ibcon#about to read 3, iclass 15, count 0 2006.175.08:27:49.27#ibcon#read 3, iclass 15, count 0 2006.175.08:27:49.27#ibcon#about to read 4, iclass 15, count 0 2006.175.08:27:49.27#ibcon#read 4, iclass 15, count 0 2006.175.08:27:49.27#ibcon#about to read 5, iclass 15, count 0 2006.175.08:27:49.27#ibcon#read 5, iclass 15, count 0 2006.175.08:27:49.27#ibcon#about to read 6, iclass 15, count 0 2006.175.08:27:49.27#ibcon#read 6, iclass 15, count 0 2006.175.08:27:49.27#ibcon#end of sib2, iclass 15, count 0 2006.175.08:27:49.27#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:27:49.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:27:49.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.175.08:27:49.27#ibcon#*before write, iclass 15, count 0 2006.175.08:27:49.27#ibcon#enter sib2, iclass 15, count 0 2006.175.08:27:49.27#ibcon#flushed, iclass 15, count 0 2006.175.08:27:49.27#ibcon#about to write, iclass 15, count 0 2006.175.08:27:49.27#ibcon#wrote, iclass 15, count 0 2006.175.08:27:49.27#ibcon#about to read 3, iclass 15, count 0 2006.175.08:27:49.31#ibcon#read 3, iclass 15, count 0 2006.175.08:27:49.31#ibcon#about to read 4, iclass 15, count 0 2006.175.08:27:49.31#ibcon#read 4, iclass 15, count 0 2006.175.08:27:49.31#ibcon#about to read 5, iclass 15, count 0 2006.175.08:27:49.31#ibcon#read 5, iclass 15, count 0 2006.175.08:27:49.31#ibcon#about to read 6, iclass 15, count 0 2006.175.08:27:49.31#ibcon#read 6, iclass 15, count 0 2006.175.08:27:49.31#ibcon#end of sib2, iclass 15, count 0 2006.175.08:27:49.31#ibcon#*after write, iclass 15, count 0 2006.175.08:27:49.31#ibcon#*before return 0, iclass 15, count 0 2006.175.08:27:49.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:49.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:49.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:27:49.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:27:49.31$vc4f8/va=5,7 2006.175.08:27:49.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.08:27:49.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.08:27:49.31#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:49.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:49.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:49.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:49.37#ibcon#enter wrdev, iclass 17, count 2 2006.175.08:27:49.37#ibcon#first serial, iclass 17, count 2 2006.175.08:27:49.37#ibcon#enter sib2, iclass 17, count 2 2006.175.08:27:49.37#ibcon#flushed, iclass 17, count 2 2006.175.08:27:49.37#ibcon#about to write, iclass 17, count 2 2006.175.08:27:49.37#ibcon#wrote, iclass 17, count 2 2006.175.08:27:49.37#ibcon#about to read 3, iclass 17, count 2 2006.175.08:27:49.39#ibcon#read 3, iclass 17, count 2 2006.175.08:27:49.39#ibcon#about to read 4, iclass 17, count 2 2006.175.08:27:49.39#ibcon#read 4, iclass 17, count 2 2006.175.08:27:49.39#ibcon#about to read 5, iclass 17, count 2 2006.175.08:27:49.39#ibcon#read 5, iclass 17, count 2 2006.175.08:27:49.39#ibcon#about to read 6, iclass 17, count 2 2006.175.08:27:49.39#ibcon#read 6, iclass 17, count 2 2006.175.08:27:49.39#ibcon#end of sib2, iclass 17, count 2 2006.175.08:27:49.39#ibcon#*mode == 0, iclass 17, count 2 2006.175.08:27:49.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.08:27:49.39#ibcon#[25=AT05-07\r\n] 2006.175.08:27:49.39#ibcon#*before write, iclass 17, count 2 2006.175.08:27:49.39#ibcon#enter sib2, iclass 17, count 2 2006.175.08:27:49.39#ibcon#flushed, iclass 17, count 2 2006.175.08:27:49.39#ibcon#about to write, iclass 17, count 2 2006.175.08:27:49.39#ibcon#wrote, iclass 17, count 2 2006.175.08:27:49.39#ibcon#about to read 3, iclass 17, count 2 2006.175.08:27:49.42#ibcon#read 3, iclass 17, count 2 2006.175.08:27:49.42#ibcon#about to read 4, iclass 17, count 2 2006.175.08:27:49.42#ibcon#read 4, iclass 17, count 2 2006.175.08:27:49.42#ibcon#about to read 5, iclass 17, count 2 2006.175.08:27:49.42#ibcon#read 5, iclass 17, count 2 2006.175.08:27:49.42#ibcon#about to read 6, iclass 17, count 2 2006.175.08:27:49.42#ibcon#read 6, iclass 17, count 2 2006.175.08:27:49.42#ibcon#end of sib2, iclass 17, count 2 2006.175.08:27:49.42#ibcon#*after write, iclass 17, count 2 2006.175.08:27:49.42#ibcon#*before return 0, iclass 17, count 2 2006.175.08:27:49.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:49.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:49.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.08:27:49.42#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:49.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:49.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:49.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:49.54#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:27:49.54#ibcon#first serial, iclass 17, count 0 2006.175.08:27:49.54#ibcon#enter sib2, iclass 17, count 0 2006.175.08:27:49.54#ibcon#flushed, iclass 17, count 0 2006.175.08:27:49.54#ibcon#about to write, iclass 17, count 0 2006.175.08:27:49.54#ibcon#wrote, iclass 17, count 0 2006.175.08:27:49.54#ibcon#about to read 3, iclass 17, count 0 2006.175.08:27:49.56#ibcon#read 3, iclass 17, count 0 2006.175.08:27:49.56#ibcon#about to read 4, iclass 17, count 0 2006.175.08:27:49.56#ibcon#read 4, iclass 17, count 0 2006.175.08:27:49.56#ibcon#about to read 5, iclass 17, count 0 2006.175.08:27:49.56#ibcon#read 5, iclass 17, count 0 2006.175.08:27:49.56#ibcon#about to read 6, iclass 17, count 0 2006.175.08:27:49.56#ibcon#read 6, iclass 17, count 0 2006.175.08:27:49.56#ibcon#end of sib2, iclass 17, count 0 2006.175.08:27:49.56#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:27:49.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:27:49.56#ibcon#[25=USB\r\n] 2006.175.08:27:49.56#ibcon#*before write, iclass 17, count 0 2006.175.08:27:49.56#ibcon#enter sib2, iclass 17, count 0 2006.175.08:27:49.56#ibcon#flushed, iclass 17, count 0 2006.175.08:27:49.56#ibcon#about to write, iclass 17, count 0 2006.175.08:27:49.56#ibcon#wrote, iclass 17, count 0 2006.175.08:27:49.56#ibcon#about to read 3, iclass 17, count 0 2006.175.08:27:49.59#ibcon#read 3, iclass 17, count 0 2006.175.08:27:49.59#ibcon#about to read 4, iclass 17, count 0 2006.175.08:27:49.59#ibcon#read 4, iclass 17, count 0 2006.175.08:27:49.59#ibcon#about to read 5, iclass 17, count 0 2006.175.08:27:49.59#ibcon#read 5, iclass 17, count 0 2006.175.08:27:49.59#ibcon#about to read 6, iclass 17, count 0 2006.175.08:27:49.59#ibcon#read 6, iclass 17, count 0 2006.175.08:27:49.59#ibcon#end of sib2, iclass 17, count 0 2006.175.08:27:49.59#ibcon#*after write, iclass 17, count 0 2006.175.08:27:49.59#ibcon#*before return 0, iclass 17, count 0 2006.175.08:27:49.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:49.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:49.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:27:49.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:27:49.59$vc4f8/valo=6,772.99 2006.175.08:27:49.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.08:27:49.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.08:27:49.59#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:49.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:49.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:49.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:49.59#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:27:49.59#ibcon#first serial, iclass 19, count 0 2006.175.08:27:49.59#ibcon#enter sib2, iclass 19, count 0 2006.175.08:27:49.59#ibcon#flushed, iclass 19, count 0 2006.175.08:27:49.59#ibcon#about to write, iclass 19, count 0 2006.175.08:27:49.59#ibcon#wrote, iclass 19, count 0 2006.175.08:27:49.59#ibcon#about to read 3, iclass 19, count 0 2006.175.08:27:49.61#ibcon#read 3, iclass 19, count 0 2006.175.08:27:49.61#ibcon#about to read 4, iclass 19, count 0 2006.175.08:27:49.61#ibcon#read 4, iclass 19, count 0 2006.175.08:27:49.61#ibcon#about to read 5, iclass 19, count 0 2006.175.08:27:49.61#ibcon#read 5, iclass 19, count 0 2006.175.08:27:49.61#ibcon#about to read 6, iclass 19, count 0 2006.175.08:27:49.61#ibcon#read 6, iclass 19, count 0 2006.175.08:27:49.61#ibcon#end of sib2, iclass 19, count 0 2006.175.08:27:49.61#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:27:49.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:27:49.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.175.08:27:49.61#ibcon#*before write, iclass 19, count 0 2006.175.08:27:49.61#ibcon#enter sib2, iclass 19, count 0 2006.175.08:27:49.61#ibcon#flushed, iclass 19, count 0 2006.175.08:27:49.61#ibcon#about to write, iclass 19, count 0 2006.175.08:27:49.61#ibcon#wrote, iclass 19, count 0 2006.175.08:27:49.61#ibcon#about to read 3, iclass 19, count 0 2006.175.08:27:49.65#ibcon#read 3, iclass 19, count 0 2006.175.08:27:49.65#ibcon#about to read 4, iclass 19, count 0 2006.175.08:27:49.65#ibcon#read 4, iclass 19, count 0 2006.175.08:27:49.65#ibcon#about to read 5, iclass 19, count 0 2006.175.08:27:49.65#ibcon#read 5, iclass 19, count 0 2006.175.08:27:49.65#ibcon#about to read 6, iclass 19, count 0 2006.175.08:27:49.65#ibcon#read 6, iclass 19, count 0 2006.175.08:27:49.65#ibcon#end of sib2, iclass 19, count 0 2006.175.08:27:49.65#ibcon#*after write, iclass 19, count 0 2006.175.08:27:49.65#ibcon#*before return 0, iclass 19, count 0 2006.175.08:27:49.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:49.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:49.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:27:49.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:27:49.65$vc4f8/va=6,6 2006.175.08:27:49.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.08:27:49.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.08:27:49.65#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:49.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:49.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:49.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:49.71#ibcon#enter wrdev, iclass 21, count 2 2006.175.08:27:49.71#ibcon#first serial, iclass 21, count 2 2006.175.08:27:49.71#ibcon#enter sib2, iclass 21, count 2 2006.175.08:27:49.71#ibcon#flushed, iclass 21, count 2 2006.175.08:27:49.71#ibcon#about to write, iclass 21, count 2 2006.175.08:27:49.71#ibcon#wrote, iclass 21, count 2 2006.175.08:27:49.71#ibcon#about to read 3, iclass 21, count 2 2006.175.08:27:49.73#ibcon#read 3, iclass 21, count 2 2006.175.08:27:49.73#ibcon#about to read 4, iclass 21, count 2 2006.175.08:27:49.73#ibcon#read 4, iclass 21, count 2 2006.175.08:27:49.73#ibcon#about to read 5, iclass 21, count 2 2006.175.08:27:49.73#ibcon#read 5, iclass 21, count 2 2006.175.08:27:49.73#ibcon#about to read 6, iclass 21, count 2 2006.175.08:27:49.73#ibcon#read 6, iclass 21, count 2 2006.175.08:27:49.73#ibcon#end of sib2, iclass 21, count 2 2006.175.08:27:49.73#ibcon#*mode == 0, iclass 21, count 2 2006.175.08:27:49.73#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.08:27:49.73#ibcon#[25=AT06-06\r\n] 2006.175.08:27:49.73#ibcon#*before write, iclass 21, count 2 2006.175.08:27:49.73#ibcon#enter sib2, iclass 21, count 2 2006.175.08:27:49.73#ibcon#flushed, iclass 21, count 2 2006.175.08:27:49.73#ibcon#about to write, iclass 21, count 2 2006.175.08:27:49.73#ibcon#wrote, iclass 21, count 2 2006.175.08:27:49.73#ibcon#about to read 3, iclass 21, count 2 2006.175.08:27:49.76#ibcon#read 3, iclass 21, count 2 2006.175.08:27:49.76#ibcon#about to read 4, iclass 21, count 2 2006.175.08:27:49.76#ibcon#read 4, iclass 21, count 2 2006.175.08:27:49.76#ibcon#about to read 5, iclass 21, count 2 2006.175.08:27:49.76#ibcon#read 5, iclass 21, count 2 2006.175.08:27:49.76#ibcon#about to read 6, iclass 21, count 2 2006.175.08:27:49.76#ibcon#read 6, iclass 21, count 2 2006.175.08:27:49.76#ibcon#end of sib2, iclass 21, count 2 2006.175.08:27:49.76#ibcon#*after write, iclass 21, count 2 2006.175.08:27:49.76#ibcon#*before return 0, iclass 21, count 2 2006.175.08:27:49.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:49.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:49.76#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.08:27:49.76#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:49.76#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:49.88#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:49.88#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:49.88#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:27:49.88#ibcon#first serial, iclass 21, count 0 2006.175.08:27:49.88#ibcon#enter sib2, iclass 21, count 0 2006.175.08:27:49.88#ibcon#flushed, iclass 21, count 0 2006.175.08:27:49.88#ibcon#about to write, iclass 21, count 0 2006.175.08:27:49.88#ibcon#wrote, iclass 21, count 0 2006.175.08:27:49.88#ibcon#about to read 3, iclass 21, count 0 2006.175.08:27:49.90#ibcon#read 3, iclass 21, count 0 2006.175.08:27:49.90#ibcon#about to read 4, iclass 21, count 0 2006.175.08:27:49.90#ibcon#read 4, iclass 21, count 0 2006.175.08:27:49.90#ibcon#about to read 5, iclass 21, count 0 2006.175.08:27:49.90#ibcon#read 5, iclass 21, count 0 2006.175.08:27:49.90#ibcon#about to read 6, iclass 21, count 0 2006.175.08:27:49.90#ibcon#read 6, iclass 21, count 0 2006.175.08:27:49.90#ibcon#end of sib2, iclass 21, count 0 2006.175.08:27:49.90#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:27:49.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:27:49.90#ibcon#[25=USB\r\n] 2006.175.08:27:49.90#ibcon#*before write, iclass 21, count 0 2006.175.08:27:49.90#ibcon#enter sib2, iclass 21, count 0 2006.175.08:27:49.90#ibcon#flushed, iclass 21, count 0 2006.175.08:27:49.90#ibcon#about to write, iclass 21, count 0 2006.175.08:27:49.90#ibcon#wrote, iclass 21, count 0 2006.175.08:27:49.90#ibcon#about to read 3, iclass 21, count 0 2006.175.08:27:49.93#ibcon#read 3, iclass 21, count 0 2006.175.08:27:49.93#ibcon#about to read 4, iclass 21, count 0 2006.175.08:27:49.93#ibcon#read 4, iclass 21, count 0 2006.175.08:27:49.93#ibcon#about to read 5, iclass 21, count 0 2006.175.08:27:49.93#ibcon#read 5, iclass 21, count 0 2006.175.08:27:49.93#ibcon#about to read 6, iclass 21, count 0 2006.175.08:27:49.93#ibcon#read 6, iclass 21, count 0 2006.175.08:27:49.93#ibcon#end of sib2, iclass 21, count 0 2006.175.08:27:49.93#ibcon#*after write, iclass 21, count 0 2006.175.08:27:49.93#ibcon#*before return 0, iclass 21, count 0 2006.175.08:27:49.93#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:49.93#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:49.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:27:49.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:27:49.93$vc4f8/valo=7,832.99 2006.175.08:27:49.93#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.08:27:49.93#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.08:27:49.93#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:49.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:49.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:49.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:49.93#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:27:49.93#ibcon#first serial, iclass 23, count 0 2006.175.08:27:49.93#ibcon#enter sib2, iclass 23, count 0 2006.175.08:27:49.93#ibcon#flushed, iclass 23, count 0 2006.175.08:27:49.93#ibcon#about to write, iclass 23, count 0 2006.175.08:27:49.93#ibcon#wrote, iclass 23, count 0 2006.175.08:27:49.93#ibcon#about to read 3, iclass 23, count 0 2006.175.08:27:49.95#ibcon#read 3, iclass 23, count 0 2006.175.08:27:49.95#ibcon#about to read 4, iclass 23, count 0 2006.175.08:27:49.95#ibcon#read 4, iclass 23, count 0 2006.175.08:27:49.95#ibcon#about to read 5, iclass 23, count 0 2006.175.08:27:49.95#ibcon#read 5, iclass 23, count 0 2006.175.08:27:49.95#ibcon#about to read 6, iclass 23, count 0 2006.175.08:27:49.95#ibcon#read 6, iclass 23, count 0 2006.175.08:27:49.95#ibcon#end of sib2, iclass 23, count 0 2006.175.08:27:49.95#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:27:49.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:27:49.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.175.08:27:49.95#ibcon#*before write, iclass 23, count 0 2006.175.08:27:49.95#ibcon#enter sib2, iclass 23, count 0 2006.175.08:27:49.95#ibcon#flushed, iclass 23, count 0 2006.175.08:27:49.95#ibcon#about to write, iclass 23, count 0 2006.175.08:27:49.95#ibcon#wrote, iclass 23, count 0 2006.175.08:27:49.95#ibcon#about to read 3, iclass 23, count 0 2006.175.08:27:49.99#ibcon#read 3, iclass 23, count 0 2006.175.08:27:49.99#ibcon#about to read 4, iclass 23, count 0 2006.175.08:27:49.99#ibcon#read 4, iclass 23, count 0 2006.175.08:27:49.99#ibcon#about to read 5, iclass 23, count 0 2006.175.08:27:49.99#ibcon#read 5, iclass 23, count 0 2006.175.08:27:49.99#ibcon#about to read 6, iclass 23, count 0 2006.175.08:27:49.99#ibcon#read 6, iclass 23, count 0 2006.175.08:27:49.99#ibcon#end of sib2, iclass 23, count 0 2006.175.08:27:49.99#ibcon#*after write, iclass 23, count 0 2006.175.08:27:49.99#ibcon#*before return 0, iclass 23, count 0 2006.175.08:27:49.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:49.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:49.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:27:49.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:27:49.99$vc4f8/va=7,6 2006.175.08:27:49.99#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.175.08:27:49.99#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.175.08:27:49.99#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:49.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:27:50.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:27:50.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:27:50.05#ibcon#enter wrdev, iclass 25, count 2 2006.175.08:27:50.05#ibcon#first serial, iclass 25, count 2 2006.175.08:27:50.05#ibcon#enter sib2, iclass 25, count 2 2006.175.08:27:50.05#ibcon#flushed, iclass 25, count 2 2006.175.08:27:50.05#ibcon#about to write, iclass 25, count 2 2006.175.08:27:50.05#ibcon#wrote, iclass 25, count 2 2006.175.08:27:50.05#ibcon#about to read 3, iclass 25, count 2 2006.175.08:27:50.07#ibcon#read 3, iclass 25, count 2 2006.175.08:27:50.07#ibcon#about to read 4, iclass 25, count 2 2006.175.08:27:50.07#ibcon#read 4, iclass 25, count 2 2006.175.08:27:50.07#ibcon#about to read 5, iclass 25, count 2 2006.175.08:27:50.07#ibcon#read 5, iclass 25, count 2 2006.175.08:27:50.07#ibcon#about to read 6, iclass 25, count 2 2006.175.08:27:50.07#ibcon#read 6, iclass 25, count 2 2006.175.08:27:50.07#ibcon#end of sib2, iclass 25, count 2 2006.175.08:27:50.07#ibcon#*mode == 0, iclass 25, count 2 2006.175.08:27:50.07#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.175.08:27:50.07#ibcon#[25=AT07-06\r\n] 2006.175.08:27:50.07#ibcon#*before write, iclass 25, count 2 2006.175.08:27:50.07#ibcon#enter sib2, iclass 25, count 2 2006.175.08:27:50.07#ibcon#flushed, iclass 25, count 2 2006.175.08:27:50.07#ibcon#about to write, iclass 25, count 2 2006.175.08:27:50.07#ibcon#wrote, iclass 25, count 2 2006.175.08:27:50.07#ibcon#about to read 3, iclass 25, count 2 2006.175.08:27:50.10#ibcon#read 3, iclass 25, count 2 2006.175.08:27:50.10#ibcon#about to read 4, iclass 25, count 2 2006.175.08:27:50.10#ibcon#read 4, iclass 25, count 2 2006.175.08:27:50.10#ibcon#about to read 5, iclass 25, count 2 2006.175.08:27:50.10#ibcon#read 5, iclass 25, count 2 2006.175.08:27:50.10#ibcon#about to read 6, iclass 25, count 2 2006.175.08:27:50.10#ibcon#read 6, iclass 25, count 2 2006.175.08:27:50.10#ibcon#end of sib2, iclass 25, count 2 2006.175.08:27:50.10#ibcon#*after write, iclass 25, count 2 2006.175.08:27:50.10#ibcon#*before return 0, iclass 25, count 2 2006.175.08:27:50.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:27:50.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.175.08:27:50.10#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.175.08:27:50.10#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:50.10#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:27:50.22#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:27:50.22#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:27:50.22#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:27:50.22#ibcon#first serial, iclass 25, count 0 2006.175.08:27:50.22#ibcon#enter sib2, iclass 25, count 0 2006.175.08:27:50.22#ibcon#flushed, iclass 25, count 0 2006.175.08:27:50.22#ibcon#about to write, iclass 25, count 0 2006.175.08:27:50.22#ibcon#wrote, iclass 25, count 0 2006.175.08:27:50.22#ibcon#about to read 3, iclass 25, count 0 2006.175.08:27:50.24#ibcon#read 3, iclass 25, count 0 2006.175.08:27:50.24#ibcon#about to read 4, iclass 25, count 0 2006.175.08:27:50.24#ibcon#read 4, iclass 25, count 0 2006.175.08:27:50.24#ibcon#about to read 5, iclass 25, count 0 2006.175.08:27:50.24#ibcon#read 5, iclass 25, count 0 2006.175.08:27:50.24#ibcon#about to read 6, iclass 25, count 0 2006.175.08:27:50.24#ibcon#read 6, iclass 25, count 0 2006.175.08:27:50.24#ibcon#end of sib2, iclass 25, count 0 2006.175.08:27:50.24#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:27:50.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:27:50.24#ibcon#[25=USB\r\n] 2006.175.08:27:50.24#ibcon#*before write, iclass 25, count 0 2006.175.08:27:50.24#ibcon#enter sib2, iclass 25, count 0 2006.175.08:27:50.24#ibcon#flushed, iclass 25, count 0 2006.175.08:27:50.24#ibcon#about to write, iclass 25, count 0 2006.175.08:27:50.24#ibcon#wrote, iclass 25, count 0 2006.175.08:27:50.24#ibcon#about to read 3, iclass 25, count 0 2006.175.08:27:50.27#ibcon#read 3, iclass 25, count 0 2006.175.08:27:50.27#ibcon#about to read 4, iclass 25, count 0 2006.175.08:27:50.27#ibcon#read 4, iclass 25, count 0 2006.175.08:27:50.27#ibcon#about to read 5, iclass 25, count 0 2006.175.08:27:50.27#ibcon#read 5, iclass 25, count 0 2006.175.08:27:50.27#ibcon#about to read 6, iclass 25, count 0 2006.175.08:27:50.27#ibcon#read 6, iclass 25, count 0 2006.175.08:27:50.27#ibcon#end of sib2, iclass 25, count 0 2006.175.08:27:50.27#ibcon#*after write, iclass 25, count 0 2006.175.08:27:50.27#ibcon#*before return 0, iclass 25, count 0 2006.175.08:27:50.27#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:27:50.27#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.175.08:27:50.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:27:50.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:27:50.27$vc4f8/valo=8,852.99 2006.175.08:27:50.27#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.175.08:27:50.27#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.175.08:27:50.27#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:50.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:27:50.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:27:50.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:27:50.27#ibcon#enter wrdev, iclass 27, count 0 2006.175.08:27:50.27#ibcon#first serial, iclass 27, count 0 2006.175.08:27:50.27#ibcon#enter sib2, iclass 27, count 0 2006.175.08:27:50.27#ibcon#flushed, iclass 27, count 0 2006.175.08:27:50.27#ibcon#about to write, iclass 27, count 0 2006.175.08:27:50.27#ibcon#wrote, iclass 27, count 0 2006.175.08:27:50.27#ibcon#about to read 3, iclass 27, count 0 2006.175.08:27:50.29#ibcon#read 3, iclass 27, count 0 2006.175.08:27:50.29#ibcon#about to read 4, iclass 27, count 0 2006.175.08:27:50.29#ibcon#read 4, iclass 27, count 0 2006.175.08:27:50.29#ibcon#about to read 5, iclass 27, count 0 2006.175.08:27:50.29#ibcon#read 5, iclass 27, count 0 2006.175.08:27:50.29#ibcon#about to read 6, iclass 27, count 0 2006.175.08:27:50.29#ibcon#read 6, iclass 27, count 0 2006.175.08:27:50.29#ibcon#end of sib2, iclass 27, count 0 2006.175.08:27:50.29#ibcon#*mode == 0, iclass 27, count 0 2006.175.08:27:50.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.175.08:27:50.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.175.08:27:50.29#ibcon#*before write, iclass 27, count 0 2006.175.08:27:50.29#ibcon#enter sib2, iclass 27, count 0 2006.175.08:27:50.29#ibcon#flushed, iclass 27, count 0 2006.175.08:27:50.29#ibcon#about to write, iclass 27, count 0 2006.175.08:27:50.29#ibcon#wrote, iclass 27, count 0 2006.175.08:27:50.29#ibcon#about to read 3, iclass 27, count 0 2006.175.08:27:50.33#ibcon#read 3, iclass 27, count 0 2006.175.08:27:50.33#ibcon#about to read 4, iclass 27, count 0 2006.175.08:27:50.33#ibcon#read 4, iclass 27, count 0 2006.175.08:27:50.33#ibcon#about to read 5, iclass 27, count 0 2006.175.08:27:50.33#ibcon#read 5, iclass 27, count 0 2006.175.08:27:50.33#ibcon#about to read 6, iclass 27, count 0 2006.175.08:27:50.33#ibcon#read 6, iclass 27, count 0 2006.175.08:27:50.33#ibcon#end of sib2, iclass 27, count 0 2006.175.08:27:50.33#ibcon#*after write, iclass 27, count 0 2006.175.08:27:50.33#ibcon#*before return 0, iclass 27, count 0 2006.175.08:27:50.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:27:50.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.175.08:27:50.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.175.08:27:50.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.175.08:27:50.33$vc4f8/va=8,6 2006.175.08:27:50.33#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.175.08:27:50.33#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.175.08:27:50.33#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:50.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:27:50.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:27:50.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:27:50.39#ibcon#enter wrdev, iclass 29, count 2 2006.175.08:27:50.39#ibcon#first serial, iclass 29, count 2 2006.175.08:27:50.39#ibcon#enter sib2, iclass 29, count 2 2006.175.08:27:50.39#ibcon#flushed, iclass 29, count 2 2006.175.08:27:50.39#ibcon#about to write, iclass 29, count 2 2006.175.08:27:50.39#ibcon#wrote, iclass 29, count 2 2006.175.08:27:50.39#ibcon#about to read 3, iclass 29, count 2 2006.175.08:27:50.41#ibcon#read 3, iclass 29, count 2 2006.175.08:27:50.41#ibcon#about to read 4, iclass 29, count 2 2006.175.08:27:50.41#ibcon#read 4, iclass 29, count 2 2006.175.08:27:50.41#ibcon#about to read 5, iclass 29, count 2 2006.175.08:27:50.41#ibcon#read 5, iclass 29, count 2 2006.175.08:27:50.41#ibcon#about to read 6, iclass 29, count 2 2006.175.08:27:50.41#ibcon#read 6, iclass 29, count 2 2006.175.08:27:50.41#ibcon#end of sib2, iclass 29, count 2 2006.175.08:27:50.41#ibcon#*mode == 0, iclass 29, count 2 2006.175.08:27:50.41#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.175.08:27:50.41#ibcon#[25=AT08-06\r\n] 2006.175.08:27:50.41#ibcon#*before write, iclass 29, count 2 2006.175.08:27:50.41#ibcon#enter sib2, iclass 29, count 2 2006.175.08:27:50.41#ibcon#flushed, iclass 29, count 2 2006.175.08:27:50.41#ibcon#about to write, iclass 29, count 2 2006.175.08:27:50.41#ibcon#wrote, iclass 29, count 2 2006.175.08:27:50.41#ibcon#about to read 3, iclass 29, count 2 2006.175.08:27:50.44#ibcon#read 3, iclass 29, count 2 2006.175.08:27:50.44#ibcon#about to read 4, iclass 29, count 2 2006.175.08:27:50.44#ibcon#read 4, iclass 29, count 2 2006.175.08:27:50.44#ibcon#about to read 5, iclass 29, count 2 2006.175.08:27:50.44#ibcon#read 5, iclass 29, count 2 2006.175.08:27:50.44#ibcon#about to read 6, iclass 29, count 2 2006.175.08:27:50.44#ibcon#read 6, iclass 29, count 2 2006.175.08:27:50.44#ibcon#end of sib2, iclass 29, count 2 2006.175.08:27:50.44#ibcon#*after write, iclass 29, count 2 2006.175.08:27:50.44#ibcon#*before return 0, iclass 29, count 2 2006.175.08:27:50.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:27:50.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.175.08:27:50.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.175.08:27:50.44#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:50.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:27:50.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:27:50.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:27:50.56#ibcon#enter wrdev, iclass 29, count 0 2006.175.08:27:50.56#ibcon#first serial, iclass 29, count 0 2006.175.08:27:50.56#ibcon#enter sib2, iclass 29, count 0 2006.175.08:27:50.56#ibcon#flushed, iclass 29, count 0 2006.175.08:27:50.56#ibcon#about to write, iclass 29, count 0 2006.175.08:27:50.56#ibcon#wrote, iclass 29, count 0 2006.175.08:27:50.56#ibcon#about to read 3, iclass 29, count 0 2006.175.08:27:50.58#ibcon#read 3, iclass 29, count 0 2006.175.08:27:50.58#ibcon#about to read 4, iclass 29, count 0 2006.175.08:27:50.58#ibcon#read 4, iclass 29, count 0 2006.175.08:27:50.58#ibcon#about to read 5, iclass 29, count 0 2006.175.08:27:50.58#ibcon#read 5, iclass 29, count 0 2006.175.08:27:50.58#ibcon#about to read 6, iclass 29, count 0 2006.175.08:27:50.58#ibcon#read 6, iclass 29, count 0 2006.175.08:27:50.58#ibcon#end of sib2, iclass 29, count 0 2006.175.08:27:50.58#ibcon#*mode == 0, iclass 29, count 0 2006.175.08:27:50.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.175.08:27:50.58#ibcon#[25=USB\r\n] 2006.175.08:27:50.58#ibcon#*before write, iclass 29, count 0 2006.175.08:27:50.58#ibcon#enter sib2, iclass 29, count 0 2006.175.08:27:50.58#ibcon#flushed, iclass 29, count 0 2006.175.08:27:50.58#ibcon#about to write, iclass 29, count 0 2006.175.08:27:50.58#ibcon#wrote, iclass 29, count 0 2006.175.08:27:50.58#ibcon#about to read 3, iclass 29, count 0 2006.175.08:27:50.61#ibcon#read 3, iclass 29, count 0 2006.175.08:27:50.61#ibcon#about to read 4, iclass 29, count 0 2006.175.08:27:50.61#ibcon#read 4, iclass 29, count 0 2006.175.08:27:50.61#ibcon#about to read 5, iclass 29, count 0 2006.175.08:27:50.61#ibcon#read 5, iclass 29, count 0 2006.175.08:27:50.61#ibcon#about to read 6, iclass 29, count 0 2006.175.08:27:50.61#ibcon#read 6, iclass 29, count 0 2006.175.08:27:50.61#ibcon#end of sib2, iclass 29, count 0 2006.175.08:27:50.61#ibcon#*after write, iclass 29, count 0 2006.175.08:27:50.61#ibcon#*before return 0, iclass 29, count 0 2006.175.08:27:50.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:27:50.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.175.08:27:50.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.175.08:27:50.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.175.08:27:50.61$vc4f8/vblo=1,632.99 2006.175.08:27:50.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.175.08:27:50.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.175.08:27:50.61#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:50.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:27:50.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:27:50.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:27:50.61#ibcon#enter wrdev, iclass 31, count 0 2006.175.08:27:50.61#ibcon#first serial, iclass 31, count 0 2006.175.08:27:50.61#ibcon#enter sib2, iclass 31, count 0 2006.175.08:27:50.61#ibcon#flushed, iclass 31, count 0 2006.175.08:27:50.61#ibcon#about to write, iclass 31, count 0 2006.175.08:27:50.61#ibcon#wrote, iclass 31, count 0 2006.175.08:27:50.61#ibcon#about to read 3, iclass 31, count 0 2006.175.08:27:50.63#ibcon#read 3, iclass 31, count 0 2006.175.08:27:50.63#ibcon#about to read 4, iclass 31, count 0 2006.175.08:27:50.63#ibcon#read 4, iclass 31, count 0 2006.175.08:27:50.63#ibcon#about to read 5, iclass 31, count 0 2006.175.08:27:50.63#ibcon#read 5, iclass 31, count 0 2006.175.08:27:50.63#ibcon#about to read 6, iclass 31, count 0 2006.175.08:27:50.63#ibcon#read 6, iclass 31, count 0 2006.175.08:27:50.63#ibcon#end of sib2, iclass 31, count 0 2006.175.08:27:50.63#ibcon#*mode == 0, iclass 31, count 0 2006.175.08:27:50.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.175.08:27:50.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.175.08:27:50.63#ibcon#*before write, iclass 31, count 0 2006.175.08:27:50.63#ibcon#enter sib2, iclass 31, count 0 2006.175.08:27:50.63#ibcon#flushed, iclass 31, count 0 2006.175.08:27:50.63#ibcon#about to write, iclass 31, count 0 2006.175.08:27:50.63#ibcon#wrote, iclass 31, count 0 2006.175.08:27:50.63#ibcon#about to read 3, iclass 31, count 0 2006.175.08:27:50.67#ibcon#read 3, iclass 31, count 0 2006.175.08:27:50.67#ibcon#about to read 4, iclass 31, count 0 2006.175.08:27:50.67#ibcon#read 4, iclass 31, count 0 2006.175.08:27:50.67#ibcon#about to read 5, iclass 31, count 0 2006.175.08:27:50.67#ibcon#read 5, iclass 31, count 0 2006.175.08:27:50.67#ibcon#about to read 6, iclass 31, count 0 2006.175.08:27:50.67#ibcon#read 6, iclass 31, count 0 2006.175.08:27:50.67#ibcon#end of sib2, iclass 31, count 0 2006.175.08:27:50.67#ibcon#*after write, iclass 31, count 0 2006.175.08:27:50.67#ibcon#*before return 0, iclass 31, count 0 2006.175.08:27:50.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:27:50.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.175.08:27:50.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.175.08:27:50.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.175.08:27:50.67$vc4f8/vb=1,4 2006.175.08:27:50.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.175.08:27:50.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.175.08:27:50.67#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:50.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:27:50.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:27:50.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:27:50.67#ibcon#enter wrdev, iclass 33, count 2 2006.175.08:27:50.67#ibcon#first serial, iclass 33, count 2 2006.175.08:27:50.67#ibcon#enter sib2, iclass 33, count 2 2006.175.08:27:50.67#ibcon#flushed, iclass 33, count 2 2006.175.08:27:50.67#ibcon#about to write, iclass 33, count 2 2006.175.08:27:50.67#ibcon#wrote, iclass 33, count 2 2006.175.08:27:50.67#ibcon#about to read 3, iclass 33, count 2 2006.175.08:27:50.69#ibcon#read 3, iclass 33, count 2 2006.175.08:27:50.69#ibcon#about to read 4, iclass 33, count 2 2006.175.08:27:50.69#ibcon#read 4, iclass 33, count 2 2006.175.08:27:50.69#ibcon#about to read 5, iclass 33, count 2 2006.175.08:27:50.69#ibcon#read 5, iclass 33, count 2 2006.175.08:27:50.69#ibcon#about to read 6, iclass 33, count 2 2006.175.08:27:50.69#ibcon#read 6, iclass 33, count 2 2006.175.08:27:50.69#ibcon#end of sib2, iclass 33, count 2 2006.175.08:27:50.69#ibcon#*mode == 0, iclass 33, count 2 2006.175.08:27:50.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.175.08:27:50.69#ibcon#[27=AT01-04\r\n] 2006.175.08:27:50.69#ibcon#*before write, iclass 33, count 2 2006.175.08:27:50.69#ibcon#enter sib2, iclass 33, count 2 2006.175.08:27:50.69#ibcon#flushed, iclass 33, count 2 2006.175.08:27:50.69#ibcon#about to write, iclass 33, count 2 2006.175.08:27:50.69#ibcon#wrote, iclass 33, count 2 2006.175.08:27:50.69#ibcon#about to read 3, iclass 33, count 2 2006.175.08:27:50.72#ibcon#read 3, iclass 33, count 2 2006.175.08:27:50.72#ibcon#about to read 4, iclass 33, count 2 2006.175.08:27:50.72#ibcon#read 4, iclass 33, count 2 2006.175.08:27:50.72#ibcon#about to read 5, iclass 33, count 2 2006.175.08:27:50.72#ibcon#read 5, iclass 33, count 2 2006.175.08:27:50.72#ibcon#about to read 6, iclass 33, count 2 2006.175.08:27:50.72#ibcon#read 6, iclass 33, count 2 2006.175.08:27:50.72#ibcon#end of sib2, iclass 33, count 2 2006.175.08:27:50.72#ibcon#*after write, iclass 33, count 2 2006.175.08:27:50.72#ibcon#*before return 0, iclass 33, count 2 2006.175.08:27:50.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:27:50.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.175.08:27:50.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.175.08:27:50.72#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:50.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:27:50.75#abcon#<5=/05 3.7 6.1 25.60 721007.5\r\n> 2006.175.08:27:50.77#abcon#{5=INTERFACE CLEAR} 2006.175.08:27:50.83#abcon#[5=S1D000X0/0*\r\n] 2006.175.08:27:50.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:27:50.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:27:50.84#ibcon#enter wrdev, iclass 33, count 0 2006.175.08:27:50.84#ibcon#first serial, iclass 33, count 0 2006.175.08:27:50.84#ibcon#enter sib2, iclass 33, count 0 2006.175.08:27:50.84#ibcon#flushed, iclass 33, count 0 2006.175.08:27:50.84#ibcon#about to write, iclass 33, count 0 2006.175.08:27:50.84#ibcon#wrote, iclass 33, count 0 2006.175.08:27:50.84#ibcon#about to read 3, iclass 33, count 0 2006.175.08:27:50.86#ibcon#read 3, iclass 33, count 0 2006.175.08:27:50.86#ibcon#about to read 4, iclass 33, count 0 2006.175.08:27:50.86#ibcon#read 4, iclass 33, count 0 2006.175.08:27:50.86#ibcon#about to read 5, iclass 33, count 0 2006.175.08:27:50.86#ibcon#read 5, iclass 33, count 0 2006.175.08:27:50.86#ibcon#about to read 6, iclass 33, count 0 2006.175.08:27:50.86#ibcon#read 6, iclass 33, count 0 2006.175.08:27:50.86#ibcon#end of sib2, iclass 33, count 0 2006.175.08:27:50.86#ibcon#*mode == 0, iclass 33, count 0 2006.175.08:27:50.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.175.08:27:50.86#ibcon#[27=USB\r\n] 2006.175.08:27:50.86#ibcon#*before write, iclass 33, count 0 2006.175.08:27:50.86#ibcon#enter sib2, iclass 33, count 0 2006.175.08:27:50.86#ibcon#flushed, iclass 33, count 0 2006.175.08:27:50.86#ibcon#about to write, iclass 33, count 0 2006.175.08:27:50.86#ibcon#wrote, iclass 33, count 0 2006.175.08:27:50.86#ibcon#about to read 3, iclass 33, count 0 2006.175.08:27:50.89#ibcon#read 3, iclass 33, count 0 2006.175.08:27:50.89#ibcon#about to read 4, iclass 33, count 0 2006.175.08:27:50.89#ibcon#read 4, iclass 33, count 0 2006.175.08:27:50.89#ibcon#about to read 5, iclass 33, count 0 2006.175.08:27:50.89#ibcon#read 5, iclass 33, count 0 2006.175.08:27:50.89#ibcon#about to read 6, iclass 33, count 0 2006.175.08:27:50.89#ibcon#read 6, iclass 33, count 0 2006.175.08:27:50.89#ibcon#end of sib2, iclass 33, count 0 2006.175.08:27:50.89#ibcon#*after write, iclass 33, count 0 2006.175.08:27:50.89#ibcon#*before return 0, iclass 33, count 0 2006.175.08:27:50.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:27:50.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.175.08:27:50.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.175.08:27:50.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.175.08:27:50.89$vc4f8/vblo=2,640.99 2006.175.08:27:50.89#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.175.08:27:50.89#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.175.08:27:50.89#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:50.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:50.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:50.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:50.89#ibcon#enter wrdev, iclass 39, count 0 2006.175.08:27:50.89#ibcon#first serial, iclass 39, count 0 2006.175.08:27:50.89#ibcon#enter sib2, iclass 39, count 0 2006.175.08:27:50.89#ibcon#flushed, iclass 39, count 0 2006.175.08:27:50.89#ibcon#about to write, iclass 39, count 0 2006.175.08:27:50.89#ibcon#wrote, iclass 39, count 0 2006.175.08:27:50.89#ibcon#about to read 3, iclass 39, count 0 2006.175.08:27:50.91#ibcon#read 3, iclass 39, count 0 2006.175.08:27:50.91#ibcon#about to read 4, iclass 39, count 0 2006.175.08:27:50.91#ibcon#read 4, iclass 39, count 0 2006.175.08:27:50.91#ibcon#about to read 5, iclass 39, count 0 2006.175.08:27:50.91#ibcon#read 5, iclass 39, count 0 2006.175.08:27:50.91#ibcon#about to read 6, iclass 39, count 0 2006.175.08:27:50.91#ibcon#read 6, iclass 39, count 0 2006.175.08:27:50.91#ibcon#end of sib2, iclass 39, count 0 2006.175.08:27:50.91#ibcon#*mode == 0, iclass 39, count 0 2006.175.08:27:50.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.175.08:27:50.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.175.08:27:50.91#ibcon#*before write, iclass 39, count 0 2006.175.08:27:50.91#ibcon#enter sib2, iclass 39, count 0 2006.175.08:27:50.91#ibcon#flushed, iclass 39, count 0 2006.175.08:27:50.91#ibcon#about to write, iclass 39, count 0 2006.175.08:27:50.91#ibcon#wrote, iclass 39, count 0 2006.175.08:27:50.91#ibcon#about to read 3, iclass 39, count 0 2006.175.08:27:50.95#ibcon#read 3, iclass 39, count 0 2006.175.08:27:50.95#ibcon#about to read 4, iclass 39, count 0 2006.175.08:27:50.95#ibcon#read 4, iclass 39, count 0 2006.175.08:27:50.95#ibcon#about to read 5, iclass 39, count 0 2006.175.08:27:50.95#ibcon#read 5, iclass 39, count 0 2006.175.08:27:50.95#ibcon#about to read 6, iclass 39, count 0 2006.175.08:27:50.95#ibcon#read 6, iclass 39, count 0 2006.175.08:27:50.95#ibcon#end of sib2, iclass 39, count 0 2006.175.08:27:50.95#ibcon#*after write, iclass 39, count 0 2006.175.08:27:50.95#ibcon#*before return 0, iclass 39, count 0 2006.175.08:27:50.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:50.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.175.08:27:50.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.175.08:27:50.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.175.08:27:50.95$vc4f8/vb=2,4 2006.175.08:27:50.95#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.175.08:27:50.95#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.175.08:27:50.95#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:50.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:51.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:51.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:51.01#ibcon#enter wrdev, iclass 3, count 2 2006.175.08:27:51.01#ibcon#first serial, iclass 3, count 2 2006.175.08:27:51.01#ibcon#enter sib2, iclass 3, count 2 2006.175.08:27:51.01#ibcon#flushed, iclass 3, count 2 2006.175.08:27:51.01#ibcon#about to write, iclass 3, count 2 2006.175.08:27:51.01#ibcon#wrote, iclass 3, count 2 2006.175.08:27:51.01#ibcon#about to read 3, iclass 3, count 2 2006.175.08:27:51.03#ibcon#read 3, iclass 3, count 2 2006.175.08:27:51.03#ibcon#about to read 4, iclass 3, count 2 2006.175.08:27:51.03#ibcon#read 4, iclass 3, count 2 2006.175.08:27:51.03#ibcon#about to read 5, iclass 3, count 2 2006.175.08:27:51.03#ibcon#read 5, iclass 3, count 2 2006.175.08:27:51.03#ibcon#about to read 6, iclass 3, count 2 2006.175.08:27:51.03#ibcon#read 6, iclass 3, count 2 2006.175.08:27:51.03#ibcon#end of sib2, iclass 3, count 2 2006.175.08:27:51.03#ibcon#*mode == 0, iclass 3, count 2 2006.175.08:27:51.03#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.175.08:27:51.03#ibcon#[27=AT02-04\r\n] 2006.175.08:27:51.03#ibcon#*before write, iclass 3, count 2 2006.175.08:27:51.03#ibcon#enter sib2, iclass 3, count 2 2006.175.08:27:51.03#ibcon#flushed, iclass 3, count 2 2006.175.08:27:51.03#ibcon#about to write, iclass 3, count 2 2006.175.08:27:51.03#ibcon#wrote, iclass 3, count 2 2006.175.08:27:51.03#ibcon#about to read 3, iclass 3, count 2 2006.175.08:27:51.06#ibcon#read 3, iclass 3, count 2 2006.175.08:27:51.06#ibcon#about to read 4, iclass 3, count 2 2006.175.08:27:51.06#ibcon#read 4, iclass 3, count 2 2006.175.08:27:51.06#ibcon#about to read 5, iclass 3, count 2 2006.175.08:27:51.06#ibcon#read 5, iclass 3, count 2 2006.175.08:27:51.06#ibcon#about to read 6, iclass 3, count 2 2006.175.08:27:51.06#ibcon#read 6, iclass 3, count 2 2006.175.08:27:51.06#ibcon#end of sib2, iclass 3, count 2 2006.175.08:27:51.06#ibcon#*after write, iclass 3, count 2 2006.175.08:27:51.06#ibcon#*before return 0, iclass 3, count 2 2006.175.08:27:51.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:51.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.175.08:27:51.06#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.175.08:27:51.06#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:51.06#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:51.18#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:51.18#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:51.18#ibcon#enter wrdev, iclass 3, count 0 2006.175.08:27:51.18#ibcon#first serial, iclass 3, count 0 2006.175.08:27:51.18#ibcon#enter sib2, iclass 3, count 0 2006.175.08:27:51.18#ibcon#flushed, iclass 3, count 0 2006.175.08:27:51.18#ibcon#about to write, iclass 3, count 0 2006.175.08:27:51.18#ibcon#wrote, iclass 3, count 0 2006.175.08:27:51.18#ibcon#about to read 3, iclass 3, count 0 2006.175.08:27:51.20#ibcon#read 3, iclass 3, count 0 2006.175.08:27:51.20#ibcon#about to read 4, iclass 3, count 0 2006.175.08:27:51.20#ibcon#read 4, iclass 3, count 0 2006.175.08:27:51.20#ibcon#about to read 5, iclass 3, count 0 2006.175.08:27:51.20#ibcon#read 5, iclass 3, count 0 2006.175.08:27:51.20#ibcon#about to read 6, iclass 3, count 0 2006.175.08:27:51.20#ibcon#read 6, iclass 3, count 0 2006.175.08:27:51.20#ibcon#end of sib2, iclass 3, count 0 2006.175.08:27:51.20#ibcon#*mode == 0, iclass 3, count 0 2006.175.08:27:51.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.175.08:27:51.20#ibcon#[27=USB\r\n] 2006.175.08:27:51.20#ibcon#*before write, iclass 3, count 0 2006.175.08:27:51.20#ibcon#enter sib2, iclass 3, count 0 2006.175.08:27:51.20#ibcon#flushed, iclass 3, count 0 2006.175.08:27:51.20#ibcon#about to write, iclass 3, count 0 2006.175.08:27:51.20#ibcon#wrote, iclass 3, count 0 2006.175.08:27:51.20#ibcon#about to read 3, iclass 3, count 0 2006.175.08:27:51.23#ibcon#read 3, iclass 3, count 0 2006.175.08:27:51.23#ibcon#about to read 4, iclass 3, count 0 2006.175.08:27:51.23#ibcon#read 4, iclass 3, count 0 2006.175.08:27:51.23#ibcon#about to read 5, iclass 3, count 0 2006.175.08:27:51.23#ibcon#read 5, iclass 3, count 0 2006.175.08:27:51.23#ibcon#about to read 6, iclass 3, count 0 2006.175.08:27:51.23#ibcon#read 6, iclass 3, count 0 2006.175.08:27:51.23#ibcon#end of sib2, iclass 3, count 0 2006.175.08:27:51.23#ibcon#*after write, iclass 3, count 0 2006.175.08:27:51.23#ibcon#*before return 0, iclass 3, count 0 2006.175.08:27:51.23#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:51.23#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.175.08:27:51.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.175.08:27:51.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.175.08:27:51.23$vc4f8/vblo=3,656.99 2006.175.08:27:51.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.175.08:27:51.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.175.08:27:51.23#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:51.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:51.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:51.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:51.23#ibcon#enter wrdev, iclass 5, count 0 2006.175.08:27:51.23#ibcon#first serial, iclass 5, count 0 2006.175.08:27:51.23#ibcon#enter sib2, iclass 5, count 0 2006.175.08:27:51.23#ibcon#flushed, iclass 5, count 0 2006.175.08:27:51.23#ibcon#about to write, iclass 5, count 0 2006.175.08:27:51.23#ibcon#wrote, iclass 5, count 0 2006.175.08:27:51.23#ibcon#about to read 3, iclass 5, count 0 2006.175.08:27:51.25#ibcon#read 3, iclass 5, count 0 2006.175.08:27:51.25#ibcon#about to read 4, iclass 5, count 0 2006.175.08:27:51.25#ibcon#read 4, iclass 5, count 0 2006.175.08:27:51.25#ibcon#about to read 5, iclass 5, count 0 2006.175.08:27:51.25#ibcon#read 5, iclass 5, count 0 2006.175.08:27:51.25#ibcon#about to read 6, iclass 5, count 0 2006.175.08:27:51.25#ibcon#read 6, iclass 5, count 0 2006.175.08:27:51.25#ibcon#end of sib2, iclass 5, count 0 2006.175.08:27:51.25#ibcon#*mode == 0, iclass 5, count 0 2006.175.08:27:51.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.175.08:27:51.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.175.08:27:51.25#ibcon#*before write, iclass 5, count 0 2006.175.08:27:51.25#ibcon#enter sib2, iclass 5, count 0 2006.175.08:27:51.25#ibcon#flushed, iclass 5, count 0 2006.175.08:27:51.25#ibcon#about to write, iclass 5, count 0 2006.175.08:27:51.25#ibcon#wrote, iclass 5, count 0 2006.175.08:27:51.25#ibcon#about to read 3, iclass 5, count 0 2006.175.08:27:51.29#ibcon#read 3, iclass 5, count 0 2006.175.08:27:51.29#ibcon#about to read 4, iclass 5, count 0 2006.175.08:27:51.29#ibcon#read 4, iclass 5, count 0 2006.175.08:27:51.29#ibcon#about to read 5, iclass 5, count 0 2006.175.08:27:51.29#ibcon#read 5, iclass 5, count 0 2006.175.08:27:51.29#ibcon#about to read 6, iclass 5, count 0 2006.175.08:27:51.29#ibcon#read 6, iclass 5, count 0 2006.175.08:27:51.29#ibcon#end of sib2, iclass 5, count 0 2006.175.08:27:51.29#ibcon#*after write, iclass 5, count 0 2006.175.08:27:51.29#ibcon#*before return 0, iclass 5, count 0 2006.175.08:27:51.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:51.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.175.08:27:51.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.175.08:27:51.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.175.08:27:51.29$vc4f8/vb=3,4 2006.175.08:27:51.29#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.175.08:27:51.29#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.175.08:27:51.29#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:51.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:51.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:51.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:51.35#ibcon#enter wrdev, iclass 7, count 2 2006.175.08:27:51.35#ibcon#first serial, iclass 7, count 2 2006.175.08:27:51.35#ibcon#enter sib2, iclass 7, count 2 2006.175.08:27:51.35#ibcon#flushed, iclass 7, count 2 2006.175.08:27:51.35#ibcon#about to write, iclass 7, count 2 2006.175.08:27:51.35#ibcon#wrote, iclass 7, count 2 2006.175.08:27:51.35#ibcon#about to read 3, iclass 7, count 2 2006.175.08:27:51.37#ibcon#read 3, iclass 7, count 2 2006.175.08:27:51.37#ibcon#about to read 4, iclass 7, count 2 2006.175.08:27:51.37#ibcon#read 4, iclass 7, count 2 2006.175.08:27:51.37#ibcon#about to read 5, iclass 7, count 2 2006.175.08:27:51.37#ibcon#read 5, iclass 7, count 2 2006.175.08:27:51.37#ibcon#about to read 6, iclass 7, count 2 2006.175.08:27:51.37#ibcon#read 6, iclass 7, count 2 2006.175.08:27:51.37#ibcon#end of sib2, iclass 7, count 2 2006.175.08:27:51.37#ibcon#*mode == 0, iclass 7, count 2 2006.175.08:27:51.37#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.175.08:27:51.37#ibcon#[27=AT03-04\r\n] 2006.175.08:27:51.37#ibcon#*before write, iclass 7, count 2 2006.175.08:27:51.37#ibcon#enter sib2, iclass 7, count 2 2006.175.08:27:51.37#ibcon#flushed, iclass 7, count 2 2006.175.08:27:51.37#ibcon#about to write, iclass 7, count 2 2006.175.08:27:51.37#ibcon#wrote, iclass 7, count 2 2006.175.08:27:51.37#ibcon#about to read 3, iclass 7, count 2 2006.175.08:27:51.40#ibcon#read 3, iclass 7, count 2 2006.175.08:27:51.40#ibcon#about to read 4, iclass 7, count 2 2006.175.08:27:51.40#ibcon#read 4, iclass 7, count 2 2006.175.08:27:51.40#ibcon#about to read 5, iclass 7, count 2 2006.175.08:27:51.40#ibcon#read 5, iclass 7, count 2 2006.175.08:27:51.40#ibcon#about to read 6, iclass 7, count 2 2006.175.08:27:51.40#ibcon#read 6, iclass 7, count 2 2006.175.08:27:51.40#ibcon#end of sib2, iclass 7, count 2 2006.175.08:27:51.40#ibcon#*after write, iclass 7, count 2 2006.175.08:27:51.40#ibcon#*before return 0, iclass 7, count 2 2006.175.08:27:51.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:51.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.175.08:27:51.40#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.175.08:27:51.40#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:51.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:51.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:51.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:51.52#ibcon#enter wrdev, iclass 7, count 0 2006.175.08:27:51.52#ibcon#first serial, iclass 7, count 0 2006.175.08:27:51.52#ibcon#enter sib2, iclass 7, count 0 2006.175.08:27:51.52#ibcon#flushed, iclass 7, count 0 2006.175.08:27:51.52#ibcon#about to write, iclass 7, count 0 2006.175.08:27:51.52#ibcon#wrote, iclass 7, count 0 2006.175.08:27:51.52#ibcon#about to read 3, iclass 7, count 0 2006.175.08:27:51.54#ibcon#read 3, iclass 7, count 0 2006.175.08:27:51.54#ibcon#about to read 4, iclass 7, count 0 2006.175.08:27:51.54#ibcon#read 4, iclass 7, count 0 2006.175.08:27:51.54#ibcon#about to read 5, iclass 7, count 0 2006.175.08:27:51.54#ibcon#read 5, iclass 7, count 0 2006.175.08:27:51.54#ibcon#about to read 6, iclass 7, count 0 2006.175.08:27:51.54#ibcon#read 6, iclass 7, count 0 2006.175.08:27:51.54#ibcon#end of sib2, iclass 7, count 0 2006.175.08:27:51.54#ibcon#*mode == 0, iclass 7, count 0 2006.175.08:27:51.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.175.08:27:51.54#ibcon#[27=USB\r\n] 2006.175.08:27:51.54#ibcon#*before write, iclass 7, count 0 2006.175.08:27:51.54#ibcon#enter sib2, iclass 7, count 0 2006.175.08:27:51.54#ibcon#flushed, iclass 7, count 0 2006.175.08:27:51.54#ibcon#about to write, iclass 7, count 0 2006.175.08:27:51.54#ibcon#wrote, iclass 7, count 0 2006.175.08:27:51.54#ibcon#about to read 3, iclass 7, count 0 2006.175.08:27:51.57#ibcon#read 3, iclass 7, count 0 2006.175.08:27:51.57#ibcon#about to read 4, iclass 7, count 0 2006.175.08:27:51.57#ibcon#read 4, iclass 7, count 0 2006.175.08:27:51.57#ibcon#about to read 5, iclass 7, count 0 2006.175.08:27:51.57#ibcon#read 5, iclass 7, count 0 2006.175.08:27:51.57#ibcon#about to read 6, iclass 7, count 0 2006.175.08:27:51.57#ibcon#read 6, iclass 7, count 0 2006.175.08:27:51.57#ibcon#end of sib2, iclass 7, count 0 2006.175.08:27:51.57#ibcon#*after write, iclass 7, count 0 2006.175.08:27:51.57#ibcon#*before return 0, iclass 7, count 0 2006.175.08:27:51.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:51.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.175.08:27:51.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.175.08:27:51.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.175.08:27:51.57$vc4f8/vblo=4,712.99 2006.175.08:27:51.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.175.08:27:51.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.175.08:27:51.57#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:51.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:51.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:51.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:51.57#ibcon#enter wrdev, iclass 11, count 0 2006.175.08:27:51.57#ibcon#first serial, iclass 11, count 0 2006.175.08:27:51.57#ibcon#enter sib2, iclass 11, count 0 2006.175.08:27:51.57#ibcon#flushed, iclass 11, count 0 2006.175.08:27:51.57#ibcon#about to write, iclass 11, count 0 2006.175.08:27:51.57#ibcon#wrote, iclass 11, count 0 2006.175.08:27:51.57#ibcon#about to read 3, iclass 11, count 0 2006.175.08:27:51.59#ibcon#read 3, iclass 11, count 0 2006.175.08:27:51.59#ibcon#about to read 4, iclass 11, count 0 2006.175.08:27:51.59#ibcon#read 4, iclass 11, count 0 2006.175.08:27:51.59#ibcon#about to read 5, iclass 11, count 0 2006.175.08:27:51.59#ibcon#read 5, iclass 11, count 0 2006.175.08:27:51.59#ibcon#about to read 6, iclass 11, count 0 2006.175.08:27:51.59#ibcon#read 6, iclass 11, count 0 2006.175.08:27:51.59#ibcon#end of sib2, iclass 11, count 0 2006.175.08:27:51.59#ibcon#*mode == 0, iclass 11, count 0 2006.175.08:27:51.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.175.08:27:51.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.175.08:27:51.59#ibcon#*before write, iclass 11, count 0 2006.175.08:27:51.59#ibcon#enter sib2, iclass 11, count 0 2006.175.08:27:51.59#ibcon#flushed, iclass 11, count 0 2006.175.08:27:51.59#ibcon#about to write, iclass 11, count 0 2006.175.08:27:51.59#ibcon#wrote, iclass 11, count 0 2006.175.08:27:51.59#ibcon#about to read 3, iclass 11, count 0 2006.175.08:27:51.63#ibcon#read 3, iclass 11, count 0 2006.175.08:27:51.63#ibcon#about to read 4, iclass 11, count 0 2006.175.08:27:51.63#ibcon#read 4, iclass 11, count 0 2006.175.08:27:51.63#ibcon#about to read 5, iclass 11, count 0 2006.175.08:27:51.63#ibcon#read 5, iclass 11, count 0 2006.175.08:27:51.63#ibcon#about to read 6, iclass 11, count 0 2006.175.08:27:51.63#ibcon#read 6, iclass 11, count 0 2006.175.08:27:51.63#ibcon#end of sib2, iclass 11, count 0 2006.175.08:27:51.63#ibcon#*after write, iclass 11, count 0 2006.175.08:27:51.63#ibcon#*before return 0, iclass 11, count 0 2006.175.08:27:51.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:51.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.175.08:27:51.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.175.08:27:51.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.175.08:27:51.63$vc4f8/vb=4,4 2006.175.08:27:51.63#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.175.08:27:51.63#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.175.08:27:51.63#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:51.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:51.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:51.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:51.69#ibcon#enter wrdev, iclass 13, count 2 2006.175.08:27:51.69#ibcon#first serial, iclass 13, count 2 2006.175.08:27:51.69#ibcon#enter sib2, iclass 13, count 2 2006.175.08:27:51.69#ibcon#flushed, iclass 13, count 2 2006.175.08:27:51.69#ibcon#about to write, iclass 13, count 2 2006.175.08:27:51.69#ibcon#wrote, iclass 13, count 2 2006.175.08:27:51.69#ibcon#about to read 3, iclass 13, count 2 2006.175.08:27:51.71#ibcon#read 3, iclass 13, count 2 2006.175.08:27:51.71#ibcon#about to read 4, iclass 13, count 2 2006.175.08:27:51.71#ibcon#read 4, iclass 13, count 2 2006.175.08:27:51.71#ibcon#about to read 5, iclass 13, count 2 2006.175.08:27:51.71#ibcon#read 5, iclass 13, count 2 2006.175.08:27:51.71#ibcon#about to read 6, iclass 13, count 2 2006.175.08:27:51.71#ibcon#read 6, iclass 13, count 2 2006.175.08:27:51.71#ibcon#end of sib2, iclass 13, count 2 2006.175.08:27:51.71#ibcon#*mode == 0, iclass 13, count 2 2006.175.08:27:51.71#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.175.08:27:51.71#ibcon#[27=AT04-04\r\n] 2006.175.08:27:51.71#ibcon#*before write, iclass 13, count 2 2006.175.08:27:51.71#ibcon#enter sib2, iclass 13, count 2 2006.175.08:27:51.71#ibcon#flushed, iclass 13, count 2 2006.175.08:27:51.71#ibcon#about to write, iclass 13, count 2 2006.175.08:27:51.71#ibcon#wrote, iclass 13, count 2 2006.175.08:27:51.71#ibcon#about to read 3, iclass 13, count 2 2006.175.08:27:51.74#ibcon#read 3, iclass 13, count 2 2006.175.08:27:51.74#ibcon#about to read 4, iclass 13, count 2 2006.175.08:27:51.74#ibcon#read 4, iclass 13, count 2 2006.175.08:27:51.74#ibcon#about to read 5, iclass 13, count 2 2006.175.08:27:51.74#ibcon#read 5, iclass 13, count 2 2006.175.08:27:51.74#ibcon#about to read 6, iclass 13, count 2 2006.175.08:27:51.74#ibcon#read 6, iclass 13, count 2 2006.175.08:27:51.74#ibcon#end of sib2, iclass 13, count 2 2006.175.08:27:51.74#ibcon#*after write, iclass 13, count 2 2006.175.08:27:51.74#ibcon#*before return 0, iclass 13, count 2 2006.175.08:27:51.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:51.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.175.08:27:51.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.175.08:27:51.74#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:51.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:51.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:51.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:51.86#ibcon#enter wrdev, iclass 13, count 0 2006.175.08:27:51.86#ibcon#first serial, iclass 13, count 0 2006.175.08:27:51.86#ibcon#enter sib2, iclass 13, count 0 2006.175.08:27:51.86#ibcon#flushed, iclass 13, count 0 2006.175.08:27:51.86#ibcon#about to write, iclass 13, count 0 2006.175.08:27:51.86#ibcon#wrote, iclass 13, count 0 2006.175.08:27:51.86#ibcon#about to read 3, iclass 13, count 0 2006.175.08:27:51.88#ibcon#read 3, iclass 13, count 0 2006.175.08:27:51.88#ibcon#about to read 4, iclass 13, count 0 2006.175.08:27:51.88#ibcon#read 4, iclass 13, count 0 2006.175.08:27:51.88#ibcon#about to read 5, iclass 13, count 0 2006.175.08:27:51.88#ibcon#read 5, iclass 13, count 0 2006.175.08:27:51.88#ibcon#about to read 6, iclass 13, count 0 2006.175.08:27:51.88#ibcon#read 6, iclass 13, count 0 2006.175.08:27:51.88#ibcon#end of sib2, iclass 13, count 0 2006.175.08:27:51.88#ibcon#*mode == 0, iclass 13, count 0 2006.175.08:27:51.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.175.08:27:51.88#ibcon#[27=USB\r\n] 2006.175.08:27:51.88#ibcon#*before write, iclass 13, count 0 2006.175.08:27:51.88#ibcon#enter sib2, iclass 13, count 0 2006.175.08:27:51.88#ibcon#flushed, iclass 13, count 0 2006.175.08:27:51.88#ibcon#about to write, iclass 13, count 0 2006.175.08:27:51.88#ibcon#wrote, iclass 13, count 0 2006.175.08:27:51.88#ibcon#about to read 3, iclass 13, count 0 2006.175.08:27:51.91#ibcon#read 3, iclass 13, count 0 2006.175.08:27:51.91#ibcon#about to read 4, iclass 13, count 0 2006.175.08:27:51.91#ibcon#read 4, iclass 13, count 0 2006.175.08:27:51.91#ibcon#about to read 5, iclass 13, count 0 2006.175.08:27:51.91#ibcon#read 5, iclass 13, count 0 2006.175.08:27:51.91#ibcon#about to read 6, iclass 13, count 0 2006.175.08:27:51.91#ibcon#read 6, iclass 13, count 0 2006.175.08:27:51.91#ibcon#end of sib2, iclass 13, count 0 2006.175.08:27:51.91#ibcon#*after write, iclass 13, count 0 2006.175.08:27:51.91#ibcon#*before return 0, iclass 13, count 0 2006.175.08:27:51.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:51.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.175.08:27:51.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.175.08:27:51.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.175.08:27:51.91$vc4f8/vblo=5,744.99 2006.175.08:27:51.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.175.08:27:51.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.175.08:27:51.91#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:51.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:51.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:51.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:51.91#ibcon#enter wrdev, iclass 15, count 0 2006.175.08:27:51.91#ibcon#first serial, iclass 15, count 0 2006.175.08:27:51.91#ibcon#enter sib2, iclass 15, count 0 2006.175.08:27:51.91#ibcon#flushed, iclass 15, count 0 2006.175.08:27:51.91#ibcon#about to write, iclass 15, count 0 2006.175.08:27:51.91#ibcon#wrote, iclass 15, count 0 2006.175.08:27:51.91#ibcon#about to read 3, iclass 15, count 0 2006.175.08:27:51.93#ibcon#read 3, iclass 15, count 0 2006.175.08:27:51.93#ibcon#about to read 4, iclass 15, count 0 2006.175.08:27:51.93#ibcon#read 4, iclass 15, count 0 2006.175.08:27:51.93#ibcon#about to read 5, iclass 15, count 0 2006.175.08:27:51.93#ibcon#read 5, iclass 15, count 0 2006.175.08:27:51.93#ibcon#about to read 6, iclass 15, count 0 2006.175.08:27:51.93#ibcon#read 6, iclass 15, count 0 2006.175.08:27:51.93#ibcon#end of sib2, iclass 15, count 0 2006.175.08:27:51.93#ibcon#*mode == 0, iclass 15, count 0 2006.175.08:27:51.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.175.08:27:51.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.175.08:27:51.93#ibcon#*before write, iclass 15, count 0 2006.175.08:27:51.93#ibcon#enter sib2, iclass 15, count 0 2006.175.08:27:51.93#ibcon#flushed, iclass 15, count 0 2006.175.08:27:51.93#ibcon#about to write, iclass 15, count 0 2006.175.08:27:51.93#ibcon#wrote, iclass 15, count 0 2006.175.08:27:51.93#ibcon#about to read 3, iclass 15, count 0 2006.175.08:27:51.97#ibcon#read 3, iclass 15, count 0 2006.175.08:27:51.97#ibcon#about to read 4, iclass 15, count 0 2006.175.08:27:51.97#ibcon#read 4, iclass 15, count 0 2006.175.08:27:51.97#ibcon#about to read 5, iclass 15, count 0 2006.175.08:27:51.97#ibcon#read 5, iclass 15, count 0 2006.175.08:27:51.97#ibcon#about to read 6, iclass 15, count 0 2006.175.08:27:51.97#ibcon#read 6, iclass 15, count 0 2006.175.08:27:51.97#ibcon#end of sib2, iclass 15, count 0 2006.175.08:27:51.97#ibcon#*after write, iclass 15, count 0 2006.175.08:27:51.97#ibcon#*before return 0, iclass 15, count 0 2006.175.08:27:51.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:51.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.175.08:27:51.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.175.08:27:51.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.175.08:27:51.97$vc4f8/vb=5,4 2006.175.08:27:51.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.175.08:27:51.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.175.08:27:51.97#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:51.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:52.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:52.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:52.03#ibcon#enter wrdev, iclass 17, count 2 2006.175.08:27:52.03#ibcon#first serial, iclass 17, count 2 2006.175.08:27:52.03#ibcon#enter sib2, iclass 17, count 2 2006.175.08:27:52.03#ibcon#flushed, iclass 17, count 2 2006.175.08:27:52.03#ibcon#about to write, iclass 17, count 2 2006.175.08:27:52.03#ibcon#wrote, iclass 17, count 2 2006.175.08:27:52.03#ibcon#about to read 3, iclass 17, count 2 2006.175.08:27:52.05#ibcon#read 3, iclass 17, count 2 2006.175.08:27:52.05#ibcon#about to read 4, iclass 17, count 2 2006.175.08:27:52.05#ibcon#read 4, iclass 17, count 2 2006.175.08:27:52.05#ibcon#about to read 5, iclass 17, count 2 2006.175.08:27:52.05#ibcon#read 5, iclass 17, count 2 2006.175.08:27:52.05#ibcon#about to read 6, iclass 17, count 2 2006.175.08:27:52.05#ibcon#read 6, iclass 17, count 2 2006.175.08:27:52.05#ibcon#end of sib2, iclass 17, count 2 2006.175.08:27:52.05#ibcon#*mode == 0, iclass 17, count 2 2006.175.08:27:52.05#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.175.08:27:52.05#ibcon#[27=AT05-04\r\n] 2006.175.08:27:52.05#ibcon#*before write, iclass 17, count 2 2006.175.08:27:52.05#ibcon#enter sib2, iclass 17, count 2 2006.175.08:27:52.05#ibcon#flushed, iclass 17, count 2 2006.175.08:27:52.05#ibcon#about to write, iclass 17, count 2 2006.175.08:27:52.05#ibcon#wrote, iclass 17, count 2 2006.175.08:27:52.05#ibcon#about to read 3, iclass 17, count 2 2006.175.08:27:52.08#ibcon#read 3, iclass 17, count 2 2006.175.08:27:52.08#ibcon#about to read 4, iclass 17, count 2 2006.175.08:27:52.08#ibcon#read 4, iclass 17, count 2 2006.175.08:27:52.08#ibcon#about to read 5, iclass 17, count 2 2006.175.08:27:52.08#ibcon#read 5, iclass 17, count 2 2006.175.08:27:52.08#ibcon#about to read 6, iclass 17, count 2 2006.175.08:27:52.08#ibcon#read 6, iclass 17, count 2 2006.175.08:27:52.08#ibcon#end of sib2, iclass 17, count 2 2006.175.08:27:52.08#ibcon#*after write, iclass 17, count 2 2006.175.08:27:52.08#ibcon#*before return 0, iclass 17, count 2 2006.175.08:27:52.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:52.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.175.08:27:52.08#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.175.08:27:52.08#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:52.08#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:52.20#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:52.20#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:52.20#ibcon#enter wrdev, iclass 17, count 0 2006.175.08:27:52.20#ibcon#first serial, iclass 17, count 0 2006.175.08:27:52.20#ibcon#enter sib2, iclass 17, count 0 2006.175.08:27:52.20#ibcon#flushed, iclass 17, count 0 2006.175.08:27:52.20#ibcon#about to write, iclass 17, count 0 2006.175.08:27:52.20#ibcon#wrote, iclass 17, count 0 2006.175.08:27:52.20#ibcon#about to read 3, iclass 17, count 0 2006.175.08:27:52.22#ibcon#read 3, iclass 17, count 0 2006.175.08:27:52.22#ibcon#about to read 4, iclass 17, count 0 2006.175.08:27:52.22#ibcon#read 4, iclass 17, count 0 2006.175.08:27:52.22#ibcon#about to read 5, iclass 17, count 0 2006.175.08:27:52.22#ibcon#read 5, iclass 17, count 0 2006.175.08:27:52.22#ibcon#about to read 6, iclass 17, count 0 2006.175.08:27:52.22#ibcon#read 6, iclass 17, count 0 2006.175.08:27:52.22#ibcon#end of sib2, iclass 17, count 0 2006.175.08:27:52.22#ibcon#*mode == 0, iclass 17, count 0 2006.175.08:27:52.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.175.08:27:52.22#ibcon#[27=USB\r\n] 2006.175.08:27:52.22#ibcon#*before write, iclass 17, count 0 2006.175.08:27:52.22#ibcon#enter sib2, iclass 17, count 0 2006.175.08:27:52.22#ibcon#flushed, iclass 17, count 0 2006.175.08:27:52.22#ibcon#about to write, iclass 17, count 0 2006.175.08:27:52.22#ibcon#wrote, iclass 17, count 0 2006.175.08:27:52.22#ibcon#about to read 3, iclass 17, count 0 2006.175.08:27:52.25#ibcon#read 3, iclass 17, count 0 2006.175.08:27:52.25#ibcon#about to read 4, iclass 17, count 0 2006.175.08:27:52.25#ibcon#read 4, iclass 17, count 0 2006.175.08:27:52.25#ibcon#about to read 5, iclass 17, count 0 2006.175.08:27:52.25#ibcon#read 5, iclass 17, count 0 2006.175.08:27:52.25#ibcon#about to read 6, iclass 17, count 0 2006.175.08:27:52.25#ibcon#read 6, iclass 17, count 0 2006.175.08:27:52.25#ibcon#end of sib2, iclass 17, count 0 2006.175.08:27:52.25#ibcon#*after write, iclass 17, count 0 2006.175.08:27:52.25#ibcon#*before return 0, iclass 17, count 0 2006.175.08:27:52.25#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:52.25#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.175.08:27:52.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.175.08:27:52.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.175.08:27:52.25$vc4f8/vblo=6,752.99 2006.175.08:27:52.25#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.175.08:27:52.25#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.175.08:27:52.25#ibcon#ireg 17 cls_cnt 0 2006.175.08:27:52.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:52.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:52.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:52.25#ibcon#enter wrdev, iclass 19, count 0 2006.175.08:27:52.25#ibcon#first serial, iclass 19, count 0 2006.175.08:27:52.25#ibcon#enter sib2, iclass 19, count 0 2006.175.08:27:52.25#ibcon#flushed, iclass 19, count 0 2006.175.08:27:52.25#ibcon#about to write, iclass 19, count 0 2006.175.08:27:52.25#ibcon#wrote, iclass 19, count 0 2006.175.08:27:52.25#ibcon#about to read 3, iclass 19, count 0 2006.175.08:27:52.27#ibcon#read 3, iclass 19, count 0 2006.175.08:27:52.27#ibcon#about to read 4, iclass 19, count 0 2006.175.08:27:52.27#ibcon#read 4, iclass 19, count 0 2006.175.08:27:52.27#ibcon#about to read 5, iclass 19, count 0 2006.175.08:27:52.27#ibcon#read 5, iclass 19, count 0 2006.175.08:27:52.27#ibcon#about to read 6, iclass 19, count 0 2006.175.08:27:52.27#ibcon#read 6, iclass 19, count 0 2006.175.08:27:52.27#ibcon#end of sib2, iclass 19, count 0 2006.175.08:27:52.27#ibcon#*mode == 0, iclass 19, count 0 2006.175.08:27:52.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.175.08:27:52.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.175.08:27:52.27#ibcon#*before write, iclass 19, count 0 2006.175.08:27:52.27#ibcon#enter sib2, iclass 19, count 0 2006.175.08:27:52.27#ibcon#flushed, iclass 19, count 0 2006.175.08:27:52.27#ibcon#about to write, iclass 19, count 0 2006.175.08:27:52.27#ibcon#wrote, iclass 19, count 0 2006.175.08:27:52.27#ibcon#about to read 3, iclass 19, count 0 2006.175.08:27:52.31#ibcon#read 3, iclass 19, count 0 2006.175.08:27:52.31#ibcon#about to read 4, iclass 19, count 0 2006.175.08:27:52.31#ibcon#read 4, iclass 19, count 0 2006.175.08:27:52.31#ibcon#about to read 5, iclass 19, count 0 2006.175.08:27:52.31#ibcon#read 5, iclass 19, count 0 2006.175.08:27:52.31#ibcon#about to read 6, iclass 19, count 0 2006.175.08:27:52.31#ibcon#read 6, iclass 19, count 0 2006.175.08:27:52.31#ibcon#end of sib2, iclass 19, count 0 2006.175.08:27:52.31#ibcon#*after write, iclass 19, count 0 2006.175.08:27:52.31#ibcon#*before return 0, iclass 19, count 0 2006.175.08:27:52.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:52.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.175.08:27:52.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.175.08:27:52.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.175.08:27:52.31$vc4f8/vb=6,4 2006.175.08:27:52.31#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.175.08:27:52.31#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.175.08:27:52.31#ibcon#ireg 11 cls_cnt 2 2006.175.08:27:52.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:52.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:52.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:52.37#ibcon#enter wrdev, iclass 21, count 2 2006.175.08:27:52.37#ibcon#first serial, iclass 21, count 2 2006.175.08:27:52.37#ibcon#enter sib2, iclass 21, count 2 2006.175.08:27:52.37#ibcon#flushed, iclass 21, count 2 2006.175.08:27:52.37#ibcon#about to write, iclass 21, count 2 2006.175.08:27:52.37#ibcon#wrote, iclass 21, count 2 2006.175.08:27:52.37#ibcon#about to read 3, iclass 21, count 2 2006.175.08:27:52.39#ibcon#read 3, iclass 21, count 2 2006.175.08:27:52.39#ibcon#about to read 4, iclass 21, count 2 2006.175.08:27:52.39#ibcon#read 4, iclass 21, count 2 2006.175.08:27:52.39#ibcon#about to read 5, iclass 21, count 2 2006.175.08:27:52.39#ibcon#read 5, iclass 21, count 2 2006.175.08:27:52.39#ibcon#about to read 6, iclass 21, count 2 2006.175.08:27:52.39#ibcon#read 6, iclass 21, count 2 2006.175.08:27:52.39#ibcon#end of sib2, iclass 21, count 2 2006.175.08:27:52.39#ibcon#*mode == 0, iclass 21, count 2 2006.175.08:27:52.39#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.175.08:27:52.39#ibcon#[27=AT06-04\r\n] 2006.175.08:27:52.39#ibcon#*before write, iclass 21, count 2 2006.175.08:27:52.39#ibcon#enter sib2, iclass 21, count 2 2006.175.08:27:52.39#ibcon#flushed, iclass 21, count 2 2006.175.08:27:52.39#ibcon#about to write, iclass 21, count 2 2006.175.08:27:52.39#ibcon#wrote, iclass 21, count 2 2006.175.08:27:52.39#ibcon#about to read 3, iclass 21, count 2 2006.175.08:27:52.42#ibcon#read 3, iclass 21, count 2 2006.175.08:27:52.42#ibcon#about to read 4, iclass 21, count 2 2006.175.08:27:52.42#ibcon#read 4, iclass 21, count 2 2006.175.08:27:52.42#ibcon#about to read 5, iclass 21, count 2 2006.175.08:27:52.42#ibcon#read 5, iclass 21, count 2 2006.175.08:27:52.42#ibcon#about to read 6, iclass 21, count 2 2006.175.08:27:52.42#ibcon#read 6, iclass 21, count 2 2006.175.08:27:52.42#ibcon#end of sib2, iclass 21, count 2 2006.175.08:27:52.42#ibcon#*after write, iclass 21, count 2 2006.175.08:27:52.42#ibcon#*before return 0, iclass 21, count 2 2006.175.08:27:52.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:52.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.175.08:27:52.42#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.175.08:27:52.42#ibcon#ireg 7 cls_cnt 0 2006.175.08:27:52.42#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:52.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:52.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:52.54#ibcon#enter wrdev, iclass 21, count 0 2006.175.08:27:52.54#ibcon#first serial, iclass 21, count 0 2006.175.08:27:52.54#ibcon#enter sib2, iclass 21, count 0 2006.175.08:27:52.54#ibcon#flushed, iclass 21, count 0 2006.175.08:27:52.54#ibcon#about to write, iclass 21, count 0 2006.175.08:27:52.54#ibcon#wrote, iclass 21, count 0 2006.175.08:27:52.54#ibcon#about to read 3, iclass 21, count 0 2006.175.08:27:52.56#ibcon#read 3, iclass 21, count 0 2006.175.08:27:52.56#ibcon#about to read 4, iclass 21, count 0 2006.175.08:27:52.56#ibcon#read 4, iclass 21, count 0 2006.175.08:27:52.56#ibcon#about to read 5, iclass 21, count 0 2006.175.08:27:52.56#ibcon#read 5, iclass 21, count 0 2006.175.08:27:52.56#ibcon#about to read 6, iclass 21, count 0 2006.175.08:27:52.56#ibcon#read 6, iclass 21, count 0 2006.175.08:27:52.56#ibcon#end of sib2, iclass 21, count 0 2006.175.08:27:52.56#ibcon#*mode == 0, iclass 21, count 0 2006.175.08:27:52.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.175.08:27:52.56#ibcon#[27=USB\r\n] 2006.175.08:27:52.56#ibcon#*before write, iclass 21, count 0 2006.175.08:27:52.56#ibcon#enter sib2, iclass 21, count 0 2006.175.08:27:52.56#ibcon#flushed, iclass 21, count 0 2006.175.08:27:52.56#ibcon#about to write, iclass 21, count 0 2006.175.08:27:52.56#ibcon#wrote, iclass 21, count 0 2006.175.08:27:52.56#ibcon#about to read 3, iclass 21, count 0 2006.175.08:27:52.59#ibcon#read 3, iclass 21, count 0 2006.175.08:27:52.59#ibcon#about to read 4, iclass 21, count 0 2006.175.08:27:52.59#ibcon#read 4, iclass 21, count 0 2006.175.08:27:52.59#ibcon#about to read 5, iclass 21, count 0 2006.175.08:27:52.59#ibcon#read 5, iclass 21, count 0 2006.175.08:27:52.59#ibcon#about to read 6, iclass 21, count 0 2006.175.08:27:52.59#ibcon#read 6, iclass 21, count 0 2006.175.08:27:52.59#ibcon#end of sib2, iclass 21, count 0 2006.175.08:27:52.59#ibcon#*after write, iclass 21, count 0 2006.175.08:27:52.59#ibcon#*before return 0, iclass 21, count 0 2006.175.08:27:52.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:52.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.175.08:27:52.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.175.08:27:52.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.175.08:27:52.59$vc4f8/vabw=wide 2006.175.08:27:52.59#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.175.08:27:52.59#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.175.08:27:52.59#ibcon#ireg 8 cls_cnt 0 2006.175.08:27:52.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:52.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:52.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:52.59#ibcon#enter wrdev, iclass 23, count 0 2006.175.08:27:52.59#ibcon#first serial, iclass 23, count 0 2006.175.08:27:52.59#ibcon#enter sib2, iclass 23, count 0 2006.175.08:27:52.59#ibcon#flushed, iclass 23, count 0 2006.175.08:27:52.59#ibcon#about to write, iclass 23, count 0 2006.175.08:27:52.59#ibcon#wrote, iclass 23, count 0 2006.175.08:27:52.59#ibcon#about to read 3, iclass 23, count 0 2006.175.08:27:52.61#ibcon#read 3, iclass 23, count 0 2006.175.08:27:52.61#ibcon#about to read 4, iclass 23, count 0 2006.175.08:27:52.61#ibcon#read 4, iclass 23, count 0 2006.175.08:27:52.61#ibcon#about to read 5, iclass 23, count 0 2006.175.08:27:52.61#ibcon#read 5, iclass 23, count 0 2006.175.08:27:52.61#ibcon#about to read 6, iclass 23, count 0 2006.175.08:27:52.61#ibcon#read 6, iclass 23, count 0 2006.175.08:27:52.61#ibcon#end of sib2, iclass 23, count 0 2006.175.08:27:52.61#ibcon#*mode == 0, iclass 23, count 0 2006.175.08:27:52.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.175.08:27:52.61#ibcon#[25=BW32\r\n] 2006.175.08:27:52.61#ibcon#*before write, iclass 23, count 0 2006.175.08:27:52.61#ibcon#enter sib2, iclass 23, count 0 2006.175.08:27:52.61#ibcon#flushed, iclass 23, count 0 2006.175.08:27:52.61#ibcon#about to write, iclass 23, count 0 2006.175.08:27:52.61#ibcon#wrote, iclass 23, count 0 2006.175.08:27:52.61#ibcon#about to read 3, iclass 23, count 0 2006.175.08:27:52.64#ibcon#read 3, iclass 23, count 0 2006.175.08:27:52.64#ibcon#about to read 4, iclass 23, count 0 2006.175.08:27:52.64#ibcon#read 4, iclass 23, count 0 2006.175.08:27:52.64#ibcon#about to read 5, iclass 23, count 0 2006.175.08:27:52.64#ibcon#read 5, iclass 23, count 0 2006.175.08:27:52.64#ibcon#about to read 6, iclass 23, count 0 2006.175.08:27:52.64#ibcon#read 6, iclass 23, count 0 2006.175.08:27:52.64#ibcon#end of sib2, iclass 23, count 0 2006.175.08:27:52.64#ibcon#*after write, iclass 23, count 0 2006.175.08:27:52.64#ibcon#*before return 0, iclass 23, count 0 2006.175.08:27:52.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:52.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.175.08:27:52.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.175.08:27:52.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.175.08:27:52.64$vc4f8/vbbw=wide 2006.175.08:27:52.64#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.175.08:27:52.64#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.175.08:27:52.64#ibcon#ireg 8 cls_cnt 0 2006.175.08:27:52.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:27:52.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:27:52.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:27:52.71#ibcon#enter wrdev, iclass 25, count 0 2006.175.08:27:52.71#ibcon#first serial, iclass 25, count 0 2006.175.08:27:52.71#ibcon#enter sib2, iclass 25, count 0 2006.175.08:27:52.71#ibcon#flushed, iclass 25, count 0 2006.175.08:27:52.71#ibcon#about to write, iclass 25, count 0 2006.175.08:27:52.71#ibcon#wrote, iclass 25, count 0 2006.175.08:27:52.71#ibcon#about to read 3, iclass 25, count 0 2006.175.08:27:52.73#ibcon#read 3, iclass 25, count 0 2006.175.08:27:52.73#ibcon#about to read 4, iclass 25, count 0 2006.175.08:27:52.73#ibcon#read 4, iclass 25, count 0 2006.175.08:27:52.73#ibcon#about to read 5, iclass 25, count 0 2006.175.08:27:52.73#ibcon#read 5, iclass 25, count 0 2006.175.08:27:52.73#ibcon#about to read 6, iclass 25, count 0 2006.175.08:27:52.73#ibcon#read 6, iclass 25, count 0 2006.175.08:27:52.73#ibcon#end of sib2, iclass 25, count 0 2006.175.08:27:52.73#ibcon#*mode == 0, iclass 25, count 0 2006.175.08:27:52.73#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.175.08:27:52.73#ibcon#[27=BW32\r\n] 2006.175.08:27:52.73#ibcon#*before write, iclass 25, count 0 2006.175.08:27:52.73#ibcon#enter sib2, iclass 25, count 0 2006.175.08:27:52.73#ibcon#flushed, iclass 25, count 0 2006.175.08:27:52.73#ibcon#about to write, iclass 25, count 0 2006.175.08:27:52.73#ibcon#wrote, iclass 25, count 0 2006.175.08:27:52.73#ibcon#about to read 3, iclass 25, count 0 2006.175.08:27:52.76#ibcon#read 3, iclass 25, count 0 2006.175.08:27:52.76#ibcon#about to read 4, iclass 25, count 0 2006.175.08:27:52.76#ibcon#read 4, iclass 25, count 0 2006.175.08:27:52.76#ibcon#about to read 5, iclass 25, count 0 2006.175.08:27:52.76#ibcon#read 5, iclass 25, count 0 2006.175.08:27:52.76#ibcon#about to read 6, iclass 25, count 0 2006.175.08:27:52.76#ibcon#read 6, iclass 25, count 0 2006.175.08:27:52.76#ibcon#end of sib2, iclass 25, count 0 2006.175.08:27:52.76#ibcon#*after write, iclass 25, count 0 2006.175.08:27:52.76#ibcon#*before return 0, iclass 25, count 0 2006.175.08:27:52.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:27:52.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.175.08:27:52.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.175.08:27:52.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.175.08:27:52.76$4f8m12a/ifd4f 2006.175.08:27:52.76$ifd4f/lo= 2006.175.08:27:52.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.175.08:27:52.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.175.08:27:52.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.175.08:27:52.76$ifd4f/patch= 2006.175.08:27:52.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.175.08:27:52.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.175.08:27:52.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.175.08:27:52.76$4f8m12a/"form=m,16.000,1:2 2006.175.08:27:52.76$4f8m12a/"tpicd 2006.175.08:27:52.76$4f8m12a/echo=off 2006.175.08:27:52.76$4f8m12a/xlog=off 2006.175.08:27:52.76:!2006.175.08:28:20 2006.175.08:28:00.14#trakl#Source acquired 2006.175.08:28:02.14#flagr#flagr/antenna,acquired 2006.175.08:28:20.00:preob 2006.175.08:28:21.14/onsource/TRACKING 2006.175.08:28:21.14:!2006.175.08:28:30 2006.175.08:28:30.00:data_valid=on 2006.175.08:28:30.00:midob 2006.175.08:28:30.14/onsource/TRACKING 2006.175.08:28:30.14/wx/25.60,1007.5,70 2006.175.08:28:30.30/cable/+6.4768E-03 2006.175.08:28:31.39/va/01,08,usb,yes,29,31 2006.175.08:28:31.39/va/02,07,usb,yes,29,31 2006.175.08:28:31.39/va/03,06,usb,yes,31,31 2006.175.08:28:31.39/va/04,07,usb,yes,30,32 2006.175.08:28:31.39/va/05,07,usb,yes,30,32 2006.175.08:28:31.39/va/06,06,usb,yes,30,29 2006.175.08:28:31.39/va/07,06,usb,yes,30,30 2006.175.08:28:31.39/va/08,06,usb,yes,32,32 2006.175.08:28:31.62/valo/01,532.99,yes,locked 2006.175.08:28:31.62/valo/02,572.99,yes,locked 2006.175.08:28:31.62/valo/03,672.99,yes,locked 2006.175.08:28:31.62/valo/04,832.99,yes,locked 2006.175.08:28:31.62/valo/05,652.99,yes,locked 2006.175.08:28:31.62/valo/06,772.99,yes,locked 2006.175.08:28:31.62/valo/07,832.99,yes,locked 2006.175.08:28:31.62/valo/08,852.99,yes,locked 2006.175.08:28:32.71/vb/01,04,usb,yes,29,28 2006.175.08:28:32.71/vb/02,04,usb,yes,31,33 2006.175.08:28:32.71/vb/03,04,usb,yes,27,31 2006.175.08:28:32.71/vb/04,04,usb,yes,28,28 2006.175.08:28:32.71/vb/05,04,usb,yes,27,31 2006.175.08:28:32.71/vb/06,04,usb,yes,28,31 2006.175.08:28:32.71/vb/07,04,usb,yes,30,30 2006.175.08:28:32.71/vb/08,04,usb,yes,27,31 2006.175.08:28:32.94/vblo/01,632.99,yes,locked 2006.175.08:28:32.94/vblo/02,640.99,yes,locked 2006.175.08:28:32.94/vblo/03,656.99,yes,locked 2006.175.08:28:32.94/vblo/04,712.99,yes,locked 2006.175.08:28:32.94/vblo/05,744.99,yes,locked 2006.175.08:28:32.94/vblo/06,752.99,yes,locked 2006.175.08:28:32.94/vblo/07,734.99,yes,locked 2006.175.08:28:32.94/vblo/08,744.99,yes,locked 2006.175.08:28:33.09/vabw/8 2006.175.08:28:33.24/vbbw/8 2006.175.08:28:33.33/xfe/off,on,15.2 2006.175.08:28:33.71/ifatt/23,28,28,28 2006.175.08:28:34.08/fmout-gps/S +3.77E-07 2006.175.08:28:34.12:!2006.175.08:29:30 2006.175.08:29:30.00:data_valid=off 2006.175.08:29:30.00:postob 2006.175.08:29:30.09/cable/+6.4770E-03 2006.175.08:29:30.09/wx/25.58,1007.5,71 2006.175.08:29:31.08/fmout-gps/S +3.77E-07 2006.175.08:29:31.08:checkk5last 2006.175.08:29:31.08&checkk5last/chk_obsdata=1 2006.175.08:29:31.09&checkk5last/chk_obsdata=2 2006.175.08:29:31.09&checkk5last/chk_obsdata=3 2006.175.08:29:31.09&checkk5last/chk_obsdata=4 2006.175.08:29:31.10&checkk5last/k5log=1 2006.175.08:29:31.10&checkk5last/k5log=2 2006.175.08:29:31.11&checkk5last/k5log=3 2006.175.08:29:31.11&checkk5last/k5log=4 2006.175.08:29:31.11&checkk5last/obsinfo 2006.175.08:29:31.52/chk_obsdata//k5ts1/T1750828??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:29:31.93/chk_obsdata//k5ts2/T1750828??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:29:32.34/chk_obsdata//k5ts3/T1750828??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:29:32.72/chk_obsdata//k5ts4/T1750828??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.175.08:29:33.43/k5log//k5ts1_log_newline 2006.175.08:29:34.12/k5log//k5ts2_log_newline 2006.175.08:29:34.81/k5log//k5ts3_log_newline 2006.175.08:29:35.50/k5log//k5ts4_log_newline 2006.175.08:29:35.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.175.08:29:35.52:"sched_end 2006.175.08:29:35.52:source=idle 2006.175.08:29:36.14:stow 2006.175.08:29:36.14&stow/source=idle 2006.175.08:29:36.14&stow/"this is stow command. 2006.175.08:29:36.14&stow/antenna=m3 2006.175.08:29:36.14#flagr#flagr/antenna,new-source 2006.175.08:29:39.01:!+10m 2006.175.08:39:39.02:standby 2006.175.08:39:39.02&standby/"this is standby command. 2006.175.08:39:39.02&standby/antenna=m0 2006.175.08:39:40.01:sy=cp /usr2/log/k06175ts.log /usr2/log_backup/ 2006.175.08:39:40.06:log=k06176ts